diff --git a/Info.md b/Info.md index 00b977e..f1a6b42 100644 --- a/Info.md +++ b/Info.md @@ -37,26 +37,27 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING). # Details -Last updated on Wed Oct 24 23:57:13 UTC 2018 (2018-10-24T23:57:13+00:00). +Last updated on Thu Oct 25 23:18:25 UTC 2018 (2018-10-25T23:18:25+00:00). -Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-902-g3247963](https://github.com/SymbiFlow/prjxray/commit/32479630be1a661d1cfd6e5e6f1961e64c263db7). +Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-903-ga0cfca8](https://github.com/SymbiFlow/prjxray/commit/a0cfca860872a99ac81b223ee1e5e9ae567b9590). Latest commit was; ``` -commit 32479630be1a661d1cfd6e5e6f1961e64c263db7 -Author: Tim 'mithro' Ansell -Date: Wed Oct 24 16:49:20 2018 -0700 +commit a0cfca860872a99ac81b223ee1e5e9ae567b9590 +Merge: d33fdb7 3247963 +Author: Tim Ansell +Date: Wed Oct 24 17:00:19 2018 -0700 - minitests/roi_harness: Remove hardcoded values in Makefile. + Merge pull request #191 from mithro/master - Signed-off-by: Tim 'mithro' Ansell + minitests/roi_harness: Add XRAY_PIN values valid for Arty. ``` ## Database for [artix7](artix7/) ### Settings -Created using following [settings.sh (sha256: cb777c1e854d877556482ff2067eff348386ce627caa0ef5617a6e5dea01dc6a)](https://github.com/SymbiFlow/prjxray/blob/32479630be1a661d1cfd6e5e6f1961e64c263db7/database/artix7/settings.sh) +Created using following [settings.sh (sha256: cb777c1e854d877556482ff2067eff348386ce627caa0ef5617a6e5dea01dc6a)](https://github.com/SymbiFlow/prjxray/blob/a0cfca860872a99ac81b223ee1e5e9ae567b9590/database/artix7/settings.sh) ```shell export XRAY_DATABASE="artix7" export XRAY_PART="xc7a50tfgg484-1" @@ -101,13 +102,13 @@ Results have checksums; * [`cd4000b96378f736d31686b381ebd4349898b3b8bd09606223c7ca48cb1a5aba ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt) * [`4c0a815ab8943181331f7aa9ac77655a0a640d9a409a602e4f24f8feb5f905e9 ./artix7/harness/README.md`](./artix7/harness/README.md) * [`69f298082e6c8e537d8348b9d4c01f582d0d86fdeddf1e6606b90e800994bcdd ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db) - * [`8fae8a634efb8929db28581b2acd436fd4c31a0bd241dd4643e5692e2da8e648 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db) + * [`169a5dc2a069653f17dad854fff1895e3981bcd703109304f719d7f1b3a02ab1 ./artix7/mask_bram_r.db`](./artix7/mask_bram_r.db) * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_l.db`](./artix7/mask_clbll_l.db) * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clbll_r.db`](./artix7/mask_clbll_r.db) * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_l.db`](./artix7/mask_clblm_l.db) * [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./artix7/mask_clblm_r.db`](./artix7/mask_clblm_r.db) * [`69f298082e6c8e537d8348b9d4c01f582d0d86fdeddf1e6606b90e800994bcdd ./artix7/mask_dsp_l.db`](./artix7/mask_dsp_l.db) - * [`8fae8a634efb8929db28581b2acd436fd4c31a0bd241dd4643e5692e2da8e648 ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db) + * [`169a5dc2a069653f17dad854fff1895e3981bcd703109304f719d7f1b3a02ab1 ./artix7/mask_dsp_r.db`](./artix7/mask_dsp_r.db) * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_l.db`](./artix7/mask_hclk_l.db) * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db) * [`6baea72435613b87334f95cfe2b1ab36da4d57ada20b71a7dd870715b3e430c4 ./artix7/ppips_clbll_l.db`](./artix7/ppips_clbll_l.db) @@ -118,173 +119,173 @@ Results have checksums; * [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./artix7/ppips_hclk_r.db`](./artix7/ppips_hclk_r.db) * [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./artix7/ppips_int_l.db`](./artix7/ppips_int_l.db) * [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./artix7/ppips_int_r.db`](./artix7/ppips_int_r.db) - * [`ce8aa28ad2ae2834d6182d6044cd0eae62da84551c486c1b04e3400116718f67 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db) - * [`087a5f7c98aa864b1a1232660806ecbd2f4fc1a963f387821ddab47d9c358d2c ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db) - * [`e2b4f7eda0ee7cc02db131660a9677e3264ab2ec2d1bdc833fa9218fbe62f97f ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db) - * [`d67044a5aeac20f746130c86c3a104fb7173f012325aeb181c19c9adaba3dbae ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db) + * [`3b359f4fa09bb224b88ce7c3060b890a611bf1d68319b3dabeed5157d3f42bb8 ./artix7/segbits_clbll_l.db`](./artix7/segbits_clbll_l.db) + * [`d21b75b8912c30de5e1ab0256bdb7dbb0590d205c36fcfca11ce522d84854eef ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db) + * [`816ae2c85b352788bcccf62bdfff1935a9d4871eb975196b0cc2d07f25ef0068 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db) + * [`4108286bcffee65beea5574e8f068a74c0321bab27349eb312376ed71cfc3010 ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db) * [`20f7bf469951b04a56e5e140b6327470750b08960643353384b35baf85eb9117 ./artix7/segbits_hclk_l.db`](./artix7/segbits_hclk_l.db) * [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db) * [`08dee581e565abbd09db559f9226139ba5a253f8aec4f3492152d8df8a87bbab ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db) - * [`be5f0c64ee17ad010dfea5125200216b2c69a558477a80133d043ed466e565be ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db) + * [`13bc58bf4a42029adf4f9b06ffd7c9436e2294bf4fdc16cdaa70505c28a2a7b7 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db) * [`cb777c1e854d877556482ff2067eff348386ce627caa0ef5617a6e5dea01dc6a ./artix7/settings.sh`](./artix7/settings.sh) - * [`719d5ba5500fd77e2f07a161c67c6988999abdd7006db0187c8cbdcb04af44b8 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json) - * [`bb7ad365e043f69cbfcb943afb4943ccf732ea876ac8b07c926cb28007e65bbb ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json) - * [`a48f00785f54cbe2ca3ea567ceb02bf25d9d13fc868537ea8c720faf4331ad39 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json) - * [`6cb08677bcd99755d90f2df53630c3dc9c0b5d63c10c85aeef88a47ace492a93 ./artix7/site_type_BUFIO.json`](./artix7/site_type_BUFIO.json) - * [`5688ee246f3f3e736e0c0b2d96e3338e72119f1584e4447d4a8fbfe19ad0290e ./artix7/site_type_BUFMRCE.json`](./artix7/site_type_BUFMRCE.json) - * [`dfdf5a8dba3a9e03a7c74baf3bf6cdedeb3b6284d1c602b51a8076c551f940c6 ./artix7/site_type_BUFR.json`](./artix7/site_type_BUFR.json) - * [`a7b5800d4648666eaf72226199f1f7d4f93b2e69aa8d46e60883ea4b617f6d9e ./artix7/site_type_CAPTURE.json`](./artix7/site_type_CAPTURE.json) - * [`c78abb27787d2e81a93a5b264187a250f5ec035f004c09fa03858ed322f27886 ./artix7/site_type_DCIRESET.json`](./artix7/site_type_DCIRESET.json) - * [`57a442cefa8bc14d804ba6694ca7a81e1b601f4acd30d9c0e90d5b4a9db9087a ./artix7/site_type_DNA_PORT.json`](./artix7/site_type_DNA_PORT.json) - * [`01bf735ad5e616c1e177edeb549f69b6f47e869af8d58ac5acf17ca715ea0475 ./artix7/site_type_DSP48E1.json`](./artix7/site_type_DSP48E1.json) - * [`6eab82a31e033f73042853568f7d2b2c58574d1246393f6171a91796d00cb009 ./artix7/site_type_EFUSE_USR.json`](./artix7/site_type_EFUSE_USR.json) - * [`942b9bda74fc803bbc3c2c4ca1f468018e14f323dd2222c8bcf9506c5b5d15e5 ./artix7/site_type_FIFO18E1.json`](./artix7/site_type_FIFO18E1.json) - * [`e62595ccfb6649d74705597ed3dd6772a44f65c13f2ecc1fb4839c35f4b80662 ./artix7/site_type_FRAME_ECC.json`](./artix7/site_type_FRAME_ECC.json) - * [`fc9aa800af2b598c9da95a1d0a7cd1aa368978954c67ada00d153dac2dba0870 ./artix7/site_type_GTPE2_CHANNEL.json`](./artix7/site_type_GTPE2_CHANNEL.json) - * [`d0fe43e07827ac8662a939d79f23a975dffef400dc3a7308580c02352379e111 ./artix7/site_type_GTPE2_COMMON.json`](./artix7/site_type_GTPE2_COMMON.json) - * [`23f8ebf5ab129a2d4a8dd2f2246e2ca963b969aa95a3d8cc3b2cbc581cdce035 ./artix7/site_type_IBUFDS_GTE2.json`](./artix7/site_type_IBUFDS_GTE2.json) - * [`062968a37351ac566c60232cd5f618c145f76f2dca8fe16ba37dd05650ca9ec1 ./artix7/site_type_ICAP.json`](./artix7/site_type_ICAP.json) - * [`f1c204574ca89912b1f2919aa7eda4fbedafacc44814612a3efcded392c194e2 ./artix7/site_type_IDELAYCTRL.json`](./artix7/site_type_IDELAYCTRL.json) - * [`3e5a5a083444d1f0722a80ce21bb43e16606c3007aab7f441044c4aa1f1226a3 ./artix7/site_type_IDELAYE2.json`](./artix7/site_type_IDELAYE2.json) - * [`c2886064c75316bff38b1aa03b60f24b1a646f96f918a2b9fbd2c1d904094f37 ./artix7/site_type_ILOGICE3.json`](./artix7/site_type_ILOGICE3.json) - * [`e20dd0d79a5544f65c0064ab03c7647a6e187bfb94341f57e444593e9eafbc73 ./artix7/site_type_IN_FIFO.json`](./artix7/site_type_IN_FIFO.json) - * [`449635c5afeb495eb1c0f80db8793d2414e06d84086e26cd545a707e74ea3575 ./artix7/site_type_IOB33.json`](./artix7/site_type_IOB33.json) - * [`1368e7129596d2d28b513271c2b4c234a02135d98d0f7cdcc2d8b051561f1893 ./artix7/site_type_IOB33M.json`](./artix7/site_type_IOB33M.json) - * [`62391d653ecf1901c6e1d5d287e7de3b10b83fd01ae087bacf6b66cf7454beb2 ./artix7/site_type_IOB33S.json`](./artix7/site_type_IOB33S.json) - * [`2272f38176d4642a903727400d07f05b2e2f2789a446746d8cba0ce3efe46f74 ./artix7/site_type_IPAD.json`](./artix7/site_type_IPAD.json) - * [`bd89171e213d5a48cb0b0b259f4d87c93e61f37ef91bb8cbcd36e1edba957c0f ./artix7/site_type_MMCME2_ADV.json`](./artix7/site_type_MMCME2_ADV.json) - * [`c46ad6bdb62ad4de869f99521322f8a770592752ed17930eb1cbfdfc65cf3b69 ./artix7/site_type_OLOGICE3.json`](./artix7/site_type_OLOGICE3.json) - * [`b12f99c0eb9701d8995d421676c1699492ef88a155245a779be9569649c6617b ./artix7/site_type_OPAD.json`](./artix7/site_type_OPAD.json) - * [`97535aee9434b6b11a4f3d61ff3c0600206db0fc03ac8d75a9558f19c4fc8f5e ./artix7/site_type_OUT_FIFO.json`](./artix7/site_type_OUT_FIFO.json) - * [`b5f1988c0f167df0a2fdde664ed9a4fd8b6628c06e0e7fab9a1f5050eb4a466e ./artix7/site_type_PCIE_2_1.json`](./artix7/site_type_PCIE_2_1.json) - * [`47cec6b60c551a15721c6da588c14f3484be755d588f90d296ea7a11d04d46ba ./artix7/site_type_PHASER_IN_PHY.json`](./artix7/site_type_PHASER_IN_PHY.json) - * [`bb157302ba77dabd09614c88b959c9541150a0914b30c7a9c57f69d6c35d107b ./artix7/site_type_PHASER_OUT_PHY.json`](./artix7/site_type_PHASER_OUT_PHY.json) - * [`3b3b43e156ec1c4dc3c194eac174b87c2928a3ab28b3042cac446049610560b5 ./artix7/site_type_PHASER_REF.json`](./artix7/site_type_PHASER_REF.json) - * [`e2c65ca031e4f50f1cc72ab519daeb8c0564efa6fee6a0c92969a7c945357358 ./artix7/site_type_PHY_CONTROL.json`](./artix7/site_type_PHY_CONTROL.json) - * [`b1cfea0c3fc9a36a1ef6b3664af04d254aeb0a085ca2ae9ae8b84c104724ff27 ./artix7/site_type_PLLE2_ADV.json`](./artix7/site_type_PLLE2_ADV.json) - * [`7641e6cbe65165dd0f67ce0ab1650a737683d37dde8c9aa798d665c99fc3d8c2 ./artix7/site_type_PMV2.json`](./artix7/site_type_PMV2.json) - * [`3f8e9ada0f370ff1b40de2868064f7276fe73727fcfd6b725658ffbd57dcb8bf ./artix7/site_type_RAMB18E1.json`](./artix7/site_type_RAMB18E1.json) - * [`3aeb5f2a82ab0ed60295da343d05a4ca02f8d1774940b68659c495ec2de5daac ./artix7/site_type_RAMBFIFO36E1.json`](./artix7/site_type_RAMBFIFO36E1.json) - * [`1359e0ef3a2891cd173d9e8fd4306f445048484b4fb84acd83bd73b6be6a35d3 ./artix7/site_type_SLICEL.json`](./artix7/site_type_SLICEL.json) - * [`93437b1d74625a1e627b5b9c20c1598e67fe4d265b218b8e8db6fdeac7f5345e ./artix7/site_type_SLICEM.json`](./artix7/site_type_SLICEM.json) - * [`69d0f7f4b92699b729766dcde4f2467c9d5d1f91093de2119729b295b91637d6 ./artix7/site_type_STARTUP.json`](./artix7/site_type_STARTUP.json) - * [`1503bd8cd2bec47dd55ffad89ddc82e804dfd2c61e65c8770bc368ad7be9c8fa ./artix7/site_type_TIEOFF.json`](./artix7/site_type_TIEOFF.json) - * [`ac84a3db9159a0419d620dc2abb89e7f96de654239927a7400f9ed1fc41b977b ./artix7/site_type_USR_ACCESS.json`](./artix7/site_type_USR_ACCESS.json) - * [`78f4f1888dd814586b25e1008f59e0c0f094edeec8716e3acf962bc8ff13c9c1 ./artix7/site_type_XADC.json`](./artix7/site_type_XADC.json) - * [`55bf341c1e05591dc68c29d5a4a3887ce7d7d83b1413d056ae31cbed5b2ceacf ./artix7/tileconn.json`](./artix7/tileconn.json) - * [`252a413af7d6bcc43aa55374acd45fbc5f15d1149a95b90494660d5581a88883 ./artix7/tilegrid.json`](./artix7/tilegrid.json) - * [`fbf9a61be612301cff451f2838fda1331bd271f86e4ad7a46635443f0a864464 ./artix7/tile_type_BRAM_INT_INTERFACE_L.json`](./artix7/tile_type_BRAM_INT_INTERFACE_L.json) - * [`9ecd392e781177913a73cc1fa7e45ceb5a9773948fe5d9f11835683dbb7b13ca ./artix7/tile_type_BRAM_INT_INTERFACE_R.json`](./artix7/tile_type_BRAM_INT_INTERFACE_R.json) - * [`c1d01ef9bfb2533b487b73bbbe0906990fea5640c7dadba04293c0b0074ff91b ./artix7/tile_type_BRAM_L.json`](./artix7/tile_type_BRAM_L.json) - * [`457e498e91bb77772a54d5a8afc666fcbd9a6e7a9acb32a3d5115c830afec5d7 ./artix7/tile_type_BRAM_R.json`](./artix7/tile_type_BRAM_R.json) - * [`a13fddea8cd377ee4b783bead9ff50cac0e5801531c76607eb2ec66ecd6a67bb ./artix7/tile_type_BRKH_BRAM.json`](./artix7/tile_type_BRKH_BRAM.json) - * [`45c79e6fb0b495cff13416f6432904cdd01f470e751cfb4df1ef0ab6c2211e96 ./artix7/tile_type_BRKH_B_TERM_INT.json`](./artix7/tile_type_BRKH_B_TERM_INT.json) - * [`56ec8fba5a5b60edfe4856ff0de807eff3133e47b04fba38598b8689512a14bc ./artix7/tile_type_BRKH_CLB.json`](./artix7/tile_type_BRKH_CLB.json) - * [`23bfbe9b4c732c6d51898cd73e8b4973fe283e6a34596663be7f1eafb17cd55d ./artix7/tile_type_BRKH_CLK.json`](./artix7/tile_type_BRKH_CLK.json) - * [`c392b0992733376bca89170108f25bc519cd06b1c2a7728a587851ec10a31b9c ./artix7/tile_type_BRKH_CMT.json`](./artix7/tile_type_BRKH_CMT.json) - * [`053b695a0caa573d233e594e05b8de80eb9811b1b9449aa7727d29d985003217 ./artix7/tile_type_BRKH_DSP_L.json`](./artix7/tile_type_BRKH_DSP_L.json) - * [`086e76a9b644fde9f16830a0cc8c2e69b0e5ceacc3bff301e296cab6e46def5d ./artix7/tile_type_BRKH_DSP_R.json`](./artix7/tile_type_BRKH_DSP_R.json) - * [`cd3292cd07e35176dbefb646091d16baaaec74c736bc1adb843a0190f51d24af ./artix7/tile_type_BRKH_GTX.json`](./artix7/tile_type_BRKH_GTX.json) - * [`783d3d6baa2d053c918135919f638b5ff32e2b6e6c8a08efaea319456b8f0a7e ./artix7/tile_type_BRKH_INT.json`](./artix7/tile_type_BRKH_INT.json) - * [`8da1c4f26f810b32ad36183bfaf4d297c0bba54654dbdf0598d1dbb567689738 ./artix7/tile_type_BRKH_TERM_INT.json`](./artix7/tile_type_BRKH_TERM_INT.json) - * [`bba1dbca008dd4848a28786bf4615f3c1c808bf6cf954b1d9361e071cfb79927 ./artix7/tile_type_B_TERM_INT.json`](./artix7/tile_type_B_TERM_INT.json) - * [`0a3cddc74a5e6ab37cf4a7c1deaf523b70d31fe321575f3f41eb1178cb72b69b ./artix7/tile_type_CFG_CENTER_BOT.json`](./artix7/tile_type_CFG_CENTER_BOT.json) - * [`701d86922f2e283b19d3aec708dfc2d2943b765f910e106388d6ec5ea2ae4d80 ./artix7/tile_type_CFG_CENTER_MID.json`](./artix7/tile_type_CFG_CENTER_MID.json) - * [`500c4949209a249f8998c1ca28c51f55995b5d8bbba6875806368e3b4dc68e83 ./artix7/tile_type_CFG_CENTER_TOP.json`](./artix7/tile_type_CFG_CENTER_TOP.json) - * [`af4b4675ea714d3b7518297d2a4075dc8fdfb3fcc651b12b4f742b2cd6f46445 ./artix7/tile_type_CLBLL_L.json`](./artix7/tile_type_CLBLL_L.json) - * [`3dc18dec76cf080a3ab430eeeb966308565025f8144f9032e312fa51a8947020 ./artix7/tile_type_CLBLL_R.json`](./artix7/tile_type_CLBLL_R.json) - * [`73426d37d590fadbdb25d65eecfaf5ac9940f9722d115a22cfb87282fd6eddf8 ./artix7/tile_type_CLBLM_L.json`](./artix7/tile_type_CLBLM_L.json) - * [`2c033c3a5bece3055e38144c3897c8a55a83a1a344ec432aa77e6f751c9e75b1 ./artix7/tile_type_CLBLM_R.json`](./artix7/tile_type_CLBLM_R.json) - * [`587d08841fdde19107be139169b561d120974f9092f741b37eabe5ddea15b641 ./artix7/tile_type_CLK_BUFG_BOT_R.json`](./artix7/tile_type_CLK_BUFG_BOT_R.json) - * [`de8913143bf5b996e57d02d75710b7372a761d4f900036a75b03496797cee9e4 ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json) - * [`6c6693b97f6d461b9815e05fc7a20b0b00fb3c19301711be04226496057a204b ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json) - * [`c9532a45b785d3533e2033969e029f13062ecc42b805c0d2b23ee218ceab45eb ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json) - * [`1c632ab0754f6227a8dbafd07a0e02bda0911cabd245dce22b78ff4e02645d36 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json) - * [`be9d7e276eae46e1610b0dc43e15c94d2f62eb6621841de19193322faf7f965d ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json) - * [`70c631e800c0cc9805008ce98ef6cf24f39adc6a52609f3cf60a6779b0e6cedf ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json) - * [`43951c358c372eec561ab8c85bc32a2fb587b12aae11df3ff267b63f35737e9a ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json) - * [`9e20005e5e7f408baf72be5dc81afb67a955025a7dcf326e0cdb55c7998c5c0b ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json) - * [`906947ad12479e10b27b425aec2436dea8805ea450c51b1078292db31b864408 ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json) - * [`20375dee2190e4fd7c14649ed1b8d3530f77707b55384f91f2653765591927ef ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json) - * [`73efe99e80904057c04de32e440cb43ded9c650c7df7bd60d5c0a0a33763a8e8 ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json) - * [`506844d8f2ba25985a75da70b91923e8291185b378db5e519ce3b6f9796888b6 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json) - * [`372e0e8c12570745bb871ba1a3af507e5a2ec7221a2737d6bf25ff81b42062a5 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json) - * [`a8c3d0926852c2d75ed88ac4da930b1deb1a388f7bbe7c7c2d32b2ca8cf85d27 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json) - * [`11804b256e364ae6fe0c2df27b84b266f50287516d47824f5dc8a43a8dc93f7c ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json) - * [`c8115d9218adc87294f5adc8215a3364ec85e24b391b4bf75d0045b85568226d ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json) - * [`25fe320f8407a75982acc46a025676f27a6be2efaa34e5770adb52a9241ed95f ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json) - * [`2071d7876faa386a2ac1ad94d972893818f94db4170f8c4c05b0af8de695f8f3 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json) - * [`9b8d21d151f144632cb718416d9ec5407f712e8940b65495d1a72b1beb80f0c8 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json) - * [`84c14df1c55d309511cedd7fcd613a282cd303fc02094b9dcae4c57c0c9954ab ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json) - * [`179a16f60b86284ce8d527c29e305ac4ad9173b0017e5e5ac4921eea3543ebd4 ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json) - * [`801471c567005d6a9bcf9d3ff721e25971059f0436339d89e470c659b2d7b16f ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json) - * [`753feebf0d24ba3b1e758035842cbb1a064b4de3e16e8cb95df829031beee92f ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json) - * [`f2d9f69bd40843d8344bc13d5aefd5ddbb76dc71627711b821e57e8fa43bbcbb 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[`c528ad2c4bc67e0aba5bc2f0e1428647beb687ae3adfa77bfc70a34a29fc0388 ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json) - * [`26f90d4bf3ae82c8ce379f512ae0268c55fc704b5c6c8598c53956b91529572b ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json) - * [`3bdf08d4f43e8a9dc2bc12851f8e38e51413c9ec0683f420937498eed45aafc6 ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json) - * [`c78dd2e261f0a5fc6eafd71c8003205dbed53de9ed7a5742ca246b22047b55b0 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json) - * [`109b67fe5bbbcd6268fb86fed4764c912d15f77c9ddc430e8a228bf73ec00bfe ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json) - * [`5be1593662a6e1ec359df098ba71caa5f108309424cc11117339854f56a1c33c ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json) - * [`85c6b7ac250bbeb1fe16926c0b9fe3ebde3abc150c95c68e07dcb0edb54b967f ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json) - * [`3e31fcf205a9c67f5a24be910469e8b8760514278d13750dc999fe32c77edfad ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json) - * [`5d07288892cd1a21f8523e3c685ca2ac0247bf8271805b002a2787636049254c ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json) - * [`7df47db37e12f3784ab35c17380d080d274deca72e9d34fe6df62b759d42dcd2 ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json) - * [`fa3811fac61d8faa25a02abf59c1f503742564810bd017881dd7d5761e518b96 ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json) - * [`1de429f755bfb2eea7d5baa133a878909ad14cfda5110ab09ae0a6d981d15930 ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json) - * [`4eebe24c98614a1790dca73de5d59df9ce584e9fa83f2dfdf65e45687f8ea408 ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json) - * [`440a6be2c50ad4e65da67d6d562eaa94c9d5d39515f680812b69de893a7b3ae8 ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json) - * [`8d52c10eef9c998da9f580947259e8870fc03a78c1c4576de55f374b20400a06 ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json) - * [`2dd453008337e840b6000776e01e6492774e233f1c6a229a564d43b0b40e7c90 ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json) - * [`ec18789fe138cb9a7f55092e7454008f448f61ff6114374761223514a3141a5c ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json) - * [`0ff88dcc12f1174afbb9762d5f9a51c94b1f48e9fce7a2e270612f49a778fdd7 ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json) - * [`35d4e6f1829f4f8caa20144b93747f7413e2c3b2ed98b0bf10af41158bf81f46 ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json) - * [`c7f8b5def602269f1897e40d1c3ac9b0b12c5b7a544bd3f309e710154719c321 ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json) - * [`33d48102d07627a90a0d45cde55180cd54a41c4221d8000a3086116b5e163076 ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json) - * [`ad0f50a03faa49e02dbc39600861e3c353a490e22f1334f8ab774bc1bd3ad4c0 ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json) - * [`cc895f8d7eb437df6282b7c1eca5ceb157fbac7a95b1fd1c93fa65621cd112ca ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json) - * [`12ad58aa01c4a2399ebf2b49c334c06188341ddd3aee0d7f79f44228a74ae94c ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json) - * [`c0921f4040358b3ccc5205e54c788448d751c0c130dfadcf23a843f4508503d0 ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json) - * [`86dc9518591ed0dd2e2c61e9b2d50e6da3ee4d2d684472f7429001bcbcbda2bb ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json) - * [`3dcb7f202b74d980159e2de40257d5098e6f900477d06297f80990b0e9155751 ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json) - * [`b4e4f309fe6917bb52b4661a53e9ea8bd6a192cd6cb65bb4bd9cca898d16cf55 ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json) - * [`9dab8290edf106109e221c7e759ae45d3050b8d5e9574f7bf5058361e3ae4e2a ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json) - * [`87f6ae714d73ec34eaae4f4d3299c5048b29b9ecdc9b9a025101af7c8ea4bd38 ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json) - * [`b2f0206eea59366caf11ac3431a8677fb31def9541a465f8215fce9e31a4cdf2 ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json) - * [`6a4b98bd6ba5778c8f01e0d809f605e549f225a040f0a679b8e1b4bc5760c3f6 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json) - * [`a9afa4ac21293b465e15ec1cf3957882a42bf79a00880c34e5e2922cc213b670 ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json) - * [`1989a5d335af8e857dfdbcdfa3d1ebae142f467f115b1534ba4279d6f8289c04 ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json) - * [`b6e2459db179551ddb5667c88aace86b5b1ebc15d25e9ed16e5f3a1a89eb8b7c ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json) - * [`8479bc74592125bb6f90c9c0006ebf0a8cc95c81800dd7ba7149c4c80d91d101 ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json) - * [`10376bfc02f7c4e7510c81a3e8aa24aca76eeab6c036ed25e9a1165da7b6dec9 ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json) - * [`0bac0a1dab6df6c11cf9b4a91272d32c25fd0ab52d5ec7318eceed7efafedf94 ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json) - * [`2cd0b749aad9258f7bee31812865ac916833a2d70a5bafd4cbee93aedf046bff ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json) - * [`9a3ff3040e1641921d333a3572425429a26594385d2712b76aef329e31bb9111 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[`64bfc2aef95d3c080bc0eb89ad2fe78946dd08f3b18d02bdac8a6edcc5e8a874 ./artix7/tile_type_CLK_BUFG_REBUF.json`](./artix7/tile_type_CLK_BUFG_REBUF.json) + * [`26b5499eaf4c78ebbcfbedbd353c75a739b0e74cc3b56d18ed1a9216d67d3977 ./artix7/tile_type_CLK_BUFG_TOP_R.json`](./artix7/tile_type_CLK_BUFG_TOP_R.json) + * [`b56c24f19f8a4629c7f110d31fac19c362d90c72ab7a5c824a087a23179b5d51 ./artix7/tile_type_CLK_FEED.json`](./artix7/tile_type_CLK_FEED.json) + * [`1d31b4dbec6587875144c362e15871a51747da31d83da93dcfa0b0323a12f3c9 ./artix7/tile_type_CLK_HROW_BOT_R.json`](./artix7/tile_type_CLK_HROW_BOT_R.json) + * [`b31aff49780d075be6bb5805465206d9de7b3fb9b58dfd0cc6f47f73bd16448f ./artix7/tile_type_CLK_HROW_TOP_R.json`](./artix7/tile_type_CLK_HROW_TOP_R.json) + * [`57c35d6ffa8ef48238dc8ce9ae2410dea367f9d3ad913f5e79dd460b44530130 ./artix7/tile_type_CLK_MTBF2.json`](./artix7/tile_type_CLK_MTBF2.json) + * [`640ec690886110946ba82e5285c8e49f0a05d08ff734a5c29350d8e29b712d61 ./artix7/tile_type_CLK_PMV2.json`](./artix7/tile_type_CLK_PMV2.json) + * [`3594df245c20773ddcb284051106e849965f4ff2805ad860b4e30e81ec7394b8 ./artix7/tile_type_CLK_PMV2_SVT.json`](./artix7/tile_type_CLK_PMV2_SVT.json) + * [`4224e30e6cd0ef19a2e6e8c4d6f6a79f5c2ec32d3611a9828643e166310f5ba9 ./artix7/tile_type_CLK_PMVIOB.json`](./artix7/tile_type_CLK_PMVIOB.json) + * [`07127da65c6d3f4626f9f9998bff4c765d2915105c9ed7e221ce15e55d48b931 ./artix7/tile_type_CLK_PMV.json`](./artix7/tile_type_CLK_PMV.json) + * [`d68d9a3d3deda97961c6b0f4291cd5d4abaa43f857a58ce54c5382f27f50d87b ./artix7/tile_type_CLK_TERM.json`](./artix7/tile_type_CLK_TERM.json) + * [`75a6fb608f520f0426d80248dfd494c8e12a18e61eb9987c1db899b7095924e1 ./artix7/tile_type_CMT_FIFO_L.json`](./artix7/tile_type_CMT_FIFO_L.json) + * [`31d4070f65a35538fdad0bd8a83323b2dbc639c0045b29ade3aacf3a42ea75d3 ./artix7/tile_type_CMT_FIFO_R.json`](./artix7/tile_type_CMT_FIFO_R.json) + * [`459f15606ca5b02f0f111b61ac5d5a77343b4ad0526d8071b3ae75b93620b856 ./artix7/tile_type_CMT_PMV.json`](./artix7/tile_type_CMT_PMV.json) + * [`73e78465cea1179ed85ed7e4af40586d74b5f865443c1fe5421157bea5373dae ./artix7/tile_type_CMT_PMV_L.json`](./artix7/tile_type_CMT_PMV_L.json) + * [`22225c63385fe168ebb71620d5f3dcde16390493d69a94e2bb980f52240de032 ./artix7/tile_type_CMT_TOP_L_LOWER_B.json`](./artix7/tile_type_CMT_TOP_L_LOWER_B.json) + * [`b525c403635abbd7d25758783ead521a7f48ce74aa82d187b4c40aac11ccff63 ./artix7/tile_type_CMT_TOP_L_LOWER_T.json`](./artix7/tile_type_CMT_TOP_L_LOWER_T.json) + * [`423c600a061a44d2c5992a74489e043156f0ce51bddea0179ad3839118d97300 ./artix7/tile_type_CMT_TOP_L_UPPER_B.json`](./artix7/tile_type_CMT_TOP_L_UPPER_B.json) + * [`cd031c507deb41780832b200a1ad529875cb6e6e37fe9d297de6da09bca9a862 ./artix7/tile_type_CMT_TOP_L_UPPER_T.json`](./artix7/tile_type_CMT_TOP_L_UPPER_T.json) + * [`5abf0285d3445d56cf14f84e5c35f9f08b38d5536d0450da2dbcb2ee402843af ./artix7/tile_type_CMT_TOP_R_LOWER_B.json`](./artix7/tile_type_CMT_TOP_R_LOWER_B.json) + * [`b5c0c6a388c2daef9f015ed902eafcb39e188fd6f703d26278567c23d563d05a ./artix7/tile_type_CMT_TOP_R_LOWER_T.json`](./artix7/tile_type_CMT_TOP_R_LOWER_T.json) + * [`e8b16871b40ad1723c81b947273f3076e3822ee481618ac9225a171880e874e8 ./artix7/tile_type_CMT_TOP_R_UPPER_B.json`](./artix7/tile_type_CMT_TOP_R_UPPER_B.json) + * [`2b1da4927adbd17c1bbbc8065660fba5b86cc0bf1744fd5a29093b15ca7fd4a3 ./artix7/tile_type_CMT_TOP_R_UPPER_T.json`](./artix7/tile_type_CMT_TOP_R_UPPER_T.json) + * [`66ad652bb45bbac2e97037a3abf6e4ce84f156991f957dba26b45a7e16fe3ff0 ./artix7/tile_type_DSP_L.json`](./artix7/tile_type_DSP_L.json) + * [`acaf6cef3d56adae402461ae65436adecbfe917b51130815d70a7687decc9349 ./artix7/tile_type_DSP_R.json`](./artix7/tile_type_DSP_R.json) + * [`32f16cf599af10eb001ffde848d2d2ca7639e9a0a0a1ad71e4ad00839e779f15 ./artix7/tile_type_GTP_CHANNEL_0.json`](./artix7/tile_type_GTP_CHANNEL_0.json) + * [`93f44305d6c81e5d79086bf1a4788f0f330289b6488d6b39a6223a929deb3bb3 ./artix7/tile_type_GTP_CHANNEL_1.json`](./artix7/tile_type_GTP_CHANNEL_1.json) + * [`8f6f73d74921ef0b581535cf6e772bd36da38e065c1d40c3e273b4bb8a03c0fa ./artix7/tile_type_GTP_CHANNEL_2.json`](./artix7/tile_type_GTP_CHANNEL_2.json) + * [`c7b191abe2299171aedfcbff19d8119dadc07e8374eb25cf03ba66464aa36d63 ./artix7/tile_type_GTP_CHANNEL_3.json`](./artix7/tile_type_GTP_CHANNEL_3.json) + * [`ac6166d744ff39b887886012f52cf0f9ccb658a187b438e83d43e1fcba331580 ./artix7/tile_type_GTP_COMMON.json`](./artix7/tile_type_GTP_COMMON.json) + * [`99b8469c4d666836daeaab3b6417375242bcae0754109102f85b5c7eea62e545 ./artix7/tile_type_GTP_INT_INTERFACE.json`](./artix7/tile_type_GTP_INT_INTERFACE.json) + * [`d2b19757fd7c73d130ddafbed0faf72d4e4436eead7f4675ae1181d6d8a68d50 ./artix7/tile_type_HCLK_BRAM.json`](./artix7/tile_type_HCLK_BRAM.json) + * [`7602524759035e96bb966ed5ac3c42734376ea9774588918e323796ccf9f6f3a ./artix7/tile_type_HCLK_CLB.json`](./artix7/tile_type_HCLK_CLB.json) + * [`3bac2f61dcbf39fea3066fd3c5f0162b0f9b9928c630046c5081a1a00562c682 ./artix7/tile_type_HCLK_CMT.json`](./artix7/tile_type_HCLK_CMT.json) + * [`75624a70cf598442283771416ffe99c961d7ad655235e955631e2e3a3c76eb9e ./artix7/tile_type_HCLK_CMT_L.json`](./artix7/tile_type_HCLK_CMT_L.json) + * [`a696906513f868f89c4429f00e6c0451336544ad23b9033df6d3f75370b87183 ./artix7/tile_type_HCLK_DSP_L.json`](./artix7/tile_type_HCLK_DSP_L.json) + * [`c2bb2ba94a8d789c22856014cb5257b9bd7f1c93b9d9c4bf2865188d5a5891b1 ./artix7/tile_type_HCLK_DSP_R.json`](./artix7/tile_type_HCLK_DSP_R.json) + * [`836677a427eb6530e5808d8bdf26b03b7a27ac786615a8c2ca6f84941dff3d74 ./artix7/tile_type_HCLK_FEEDTHRU_1.json`](./artix7/tile_type_HCLK_FEEDTHRU_1.json) + * [`7c9c6a027ebd89f54b57ba9a135d9eb1843a80a1e707ef37c64d3fead885c17e ./artix7/tile_type_HCLK_FEEDTHRU_2.json`](./artix7/tile_type_HCLK_FEEDTHRU_2.json) + * [`881869baa9874c48fa3d11b78cd8fac446202a3bff4ebf30c9413640ba26ac39 ./artix7/tile_type_HCLK_FIFO_L.json`](./artix7/tile_type_HCLK_FIFO_L.json) + * [`6954fd8e515e8beed9ce26f65abf3269b119fdb86b7247a0082c1618fc0d5e4d ./artix7/tile_type_HCLK_GTX.json`](./artix7/tile_type_HCLK_GTX.json) + * [`d3e5b322b3847e5ca61436500fbffec6f9eee2ba813e3b4e997ebb501318ab38 ./artix7/tile_type_HCLK_INT_INTERFACE.json`](./artix7/tile_type_HCLK_INT_INTERFACE.json) + * [`6b4850191cb040d640a4e99e4727c47b305cc9bee828143c0ddf02fc73ade8f8 ./artix7/tile_type_HCLK_IOB.json`](./artix7/tile_type_HCLK_IOB.json) + * [`02b7b54a7ec81534bef46ab8c57c7eb232ddde7b7434f14705857ba4dfef6cab ./artix7/tile_type_HCLK_IOI3.json`](./artix7/tile_type_HCLK_IOI3.json) + * [`86d4dc44b7ada38f320144986f77dadd48ab1441868f982e75f9f6b8f8f6e694 ./artix7/tile_type_HCLK_L_BOT_UTURN.json`](./artix7/tile_type_HCLK_L_BOT_UTURN.json) + * [`226a6787452e47288a68f7458e367ec0a39ed7925b6404ac789b32dc2fe006ed ./artix7/tile_type_HCLK_L.json`](./artix7/tile_type_HCLK_L.json) + * [`e4f0a9a1594a425ff5a99f84a2f34515b61ba1323a815b08dd57bd947eb7b545 ./artix7/tile_type_HCLK_R_BOT_UTURN.json`](./artix7/tile_type_HCLK_R_BOT_UTURN.json) + * [`d87c6ac4b94c69d5bab4c12996d95d4389ab0a2a615e7397e1dd96c75c7a40d4 ./artix7/tile_type_HCLK_R.json`](./artix7/tile_type_HCLK_R.json) + * [`33ea81f2555030771b7bd44c6619ca0e5583433da0e01ee0e2930e5a1f33d60e ./artix7/tile_type_HCLK_TERM_GTX.json`](./artix7/tile_type_HCLK_TERM_GTX.json) + * [`81875ea3bce1aa1cdb2cc73b48d39911807bc2948b81a062f7d587c8dc43e13b ./artix7/tile_type_HCLK_TERM.json`](./artix7/tile_type_HCLK_TERM.json) + * [`30cc3e3002a88010d7031cf128a37149c9ba05fb862ed4f2761543f7c0e76117 ./artix7/tile_type_HCLK_VBRK.json`](./artix7/tile_type_HCLK_VBRK.json) + * [`4ff9d85171843ed8854c4991e5f425b4f83d6125fad1d523547ff49e1327c093 ./artix7/tile_type_HCLK_VFRAME.json`](./artix7/tile_type_HCLK_VFRAME.json) + * [`5fb8b135a485853e88853d5d88044eaa8a2cbcdd4cd8c2192276e4dbbc79c2dc ./artix7/tile_type_INT_FEEDTHRU_1.json`](./artix7/tile_type_INT_FEEDTHRU_1.json) + * [`69046907543c5d2821690b8217a2f6c4d94ada5cbbc446c1c3f3121bb8bf5a63 ./artix7/tile_type_INT_FEEDTHRU_2.json`](./artix7/tile_type_INT_FEEDTHRU_2.json) + * [`e2a128688fa2cb0dcf0d9a2865d1be99e709ca79f032c5012ef0d0a456f8672e ./artix7/tile_type_INT_INTERFACE_L.json`](./artix7/tile_type_INT_INTERFACE_L.json) + * [`14354fb555d1a48ba80df13a75fc3a6d10bbcaf164ee4bba4ad168d5b0b30a66 ./artix7/tile_type_INT_INTERFACE_R.json`](./artix7/tile_type_INT_INTERFACE_R.json) + * [`ddc6f7153fc2c363a568f744fbf934971f978a02bc16d797d8e364cfd75526ca ./artix7/tile_type_INT_L.json`](./artix7/tile_type_INT_L.json) + * [`92f8d11bfac53f072a60176dd88db65eafc72836b94ef32fbbdf62566dbc58d1 ./artix7/tile_type_INT_R.json`](./artix7/tile_type_INT_R.json) + * [`77b19fbc668f84f06bf5eb97fd57c5384736e2bd421066a5f1153f3c4a0c5218 ./artix7/tile_type_IO_INT_INTERFACE_L.json`](./artix7/tile_type_IO_INT_INTERFACE_L.json) + * [`db8165acebe5ab2f999947e47671aa2ecc2c4c55fca01477e972feedf8743a95 ./artix7/tile_type_IO_INT_INTERFACE_R.json`](./artix7/tile_type_IO_INT_INTERFACE_R.json) + * [`a74a5d13a115b33869f44a586df07fdbbe220cf7b4b5127631465908dd2b0704 ./artix7/tile_type_LIOB33.json`](./artix7/tile_type_LIOB33.json) + * [`0aa3ef5d5cfa96f983d34caa2622d717b5246d6527b8d99bc1e696085d2489e5 ./artix7/tile_type_LIOB33_SING.json`](./artix7/tile_type_LIOB33_SING.json) + * [`298c949bf1d572fb1d887107e938a53f57d8d9df2c3cec6f5e83120379ccee37 ./artix7/tile_type_LIOI3.json`](./artix7/tile_type_LIOI3.json) + * [`57f8b4bd7596ba9205151f1590bb31951224f5725a2064d8157b5e90014aef2d ./artix7/tile_type_LIOI3_SING.json`](./artix7/tile_type_LIOI3_SING.json) + * [`b39aed9f4ee86472202ee8e986e378e6a517d9985927c3dbf1efdf6138887f6b ./artix7/tile_type_LIOI3_TBYTESRC.json`](./artix7/tile_type_LIOI3_TBYTESRC.json) + * [`6dfa1fd318de1a04abc2601c53ce5a8d62f518c7116475eb9057bc121860d70a ./artix7/tile_type_LIOI3_TBYTETERM.json`](./artix7/tile_type_LIOI3_TBYTETERM.json) + * [`0d9afa21f52f65fb0d541dba5a530e8ccbec906c5b58683648896f3092a52310 ./artix7/tile_type_L_TERM_INT.json`](./artix7/tile_type_L_TERM_INT.json) + * [`7f1088bfbf484521a6316c918b75c9e84dd32e7846e6a32499d3fb6c842732f1 ./artix7/tile_type_MONITOR_BOT.json`](./artix7/tile_type_MONITOR_BOT.json) + * [`333f69423f69afee987546623ab07298f166fb958fccafd51cf57a22eea04cdd ./artix7/tile_type_MONITOR_MID.json`](./artix7/tile_type_MONITOR_MID.json) + * [`c86dc3f82a8c0d2dd19c41c993f2ee3ebe18c19a7ae63c0cab2bfc8f4fd48f66 ./artix7/tile_type_MONITOR_TOP.json`](./artix7/tile_type_MONITOR_TOP.json) + * [`6b16e9202757be322b72cdcd73f45a1e61252444ef4ee6557272fc8361d87557 ./artix7/tile_type_NULL.json`](./artix7/tile_type_NULL.json) + * [`f5f3dcd3a4cb9ccb9e2a5774372eeba4f07dfe58ff3b6c38729c6b2c801ddfc8 ./artix7/tile_type_PCIE_BOT.json`](./artix7/tile_type_PCIE_BOT.json) + * [`9e07f51515ad2162c9921af8837a5d75923721395832cd0e83e3ac16b37b135d ./artix7/tile_type_PCIE_INT_INTERFACE_L.json`](./artix7/tile_type_PCIE_INT_INTERFACE_L.json) + * [`9c62f669675e111af20f6b42602a36ed961ca7eb8dcbc1e5a849772a2a040063 ./artix7/tile_type_PCIE_INT_INTERFACE_R.json`](./artix7/tile_type_PCIE_INT_INTERFACE_R.json) + * [`e39fb1e8b8c9d0d9da3307a260fee2bf05ad0f6dfa9456b90a031893b7131e2e ./artix7/tile_type_PCIE_NULL.json`](./artix7/tile_type_PCIE_NULL.json) + * [`30e27f1479d7cd53afa17cc4f68da1c334072c05121bb5d00558aa95d1950b51 ./artix7/tile_type_PCIE_TOP.json`](./artix7/tile_type_PCIE_TOP.json) + * [`80437b8acb8a79337e8604d2766a332b7816d8c7fbe1af5861da0a9189e27279 ./artix7/tile_type_RIOB33.json`](./artix7/tile_type_RIOB33.json) + * [`9e082720755498836ae16cb09db4a3deb7915b57cf717a53bcfb59b49d4a980a ./artix7/tile_type_RIOB33_SING.json`](./artix7/tile_type_RIOB33_SING.json) + * [`c558aadec95a82ba7f5fd7ebee72eff73f4f59ae45cf837481f017ae752f90df ./artix7/tile_type_RIOI3.json`](./artix7/tile_type_RIOI3.json) + * [`3a774afda9268b4b78c94d97f2c82b61537aa16dced637ca4e69ec42a8ac3a74 ./artix7/tile_type_RIOI3_SING.json`](./artix7/tile_type_RIOI3_SING.json) + * [`ff45bb72c86e2b1e88af816947d699e9d908c73e041d25a096036bbc396ce631 ./artix7/tile_type_RIOI3_TBYTESRC.json`](./artix7/tile_type_RIOI3_TBYTESRC.json) + * [`7a1281adf9833c32c2b64ad874598a09b8a14578e8d14e2ab5dd7efab65b05ad ./artix7/tile_type_RIOI3_TBYTETERM.json`](./artix7/tile_type_RIOI3_TBYTETERM.json) + * [`149e968062620a4cb5e16e85098b9f7240a64cb50e437fbd8f437ee031d82904 ./artix7/tile_type_R_TERM_INT_GTX.json`](./artix7/tile_type_R_TERM_INT_GTX.json) + * [`7fdd280c9986b37a81b9f1963679a2fb71f4426108e301f419d1f8817a3ccde3 ./artix7/tile_type_R_TERM_INT.json`](./artix7/tile_type_R_TERM_INT.json) + * [`13025cce4075e992a43f68e5ad8b59dba49ffdafd7735b5e81b7a416e34706c8 ./artix7/tile_type_TERM_CMT.json`](./artix7/tile_type_TERM_CMT.json) + * [`23fc2dd5d45bd155822efb3b40b885999b389ddddc1bd50b6ea1e6ae09b0d2a8 ./artix7/tile_type_T_TERM_INT.json`](./artix7/tile_type_T_TERM_INT.json) + * [`8e5aa8d4838cbb4c8da2cd821fecf563e945ec8b55bfccfdbeee615e0e076389 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json) + * [`6331c61d466365b90461b3f907fc150388566d478c935076f72e853eb31e3b23 ./artix7/tile_type_VBRK.json`](./artix7/tile_type_VBRK.json) + * [`19035b8ca97a918c6029371c3caed0a81d0874582dbe82396c3b9fe03abb606a ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json) * [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcpg236-1.yaml`](./artix7/xc7a35tcpg236-1.yaml) * [`ef0724733da87455426a0f833642d96e9d206d047f4eb97072c3093f80c40d7d ./artix7/xc7a35tcsg324-1.yaml`](./artix7/xc7a35tcsg324-1.yaml) * [`41c360b1e2f7e08b9051f1160a34954ce4c05a445a07f226f1f4059caf1fa1d3 ./artix7/xc7a50tfgg484-1.yaml`](./artix7/xc7a50tfgg484-1.yaml) @@ -293,7 +294,7 @@ Results have checksums; ### Settings -Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/32479630be1a661d1cfd6e5e6f1961e64c263db7/database/kintex7/settings.sh) +Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/a0cfca860872a99ac81b223ee1e5e9ae567b9590/database/kintex7/settings.sh) ```shell export XRAY_DATABASE="kintex7" export XRAY_PART="xc7k70tfbg676-2" diff --git a/artix7/mask_bram_r.db b/artix7/mask_bram_r.db index 5a0a56f..e7d0fe1 100644 --- a/artix7/mask_bram_r.db +++ b/artix7/mask_bram_r.db @@ -6,6 +6,7 @@ bit 00_06 bit 00_07 bit 00_09 bit 00_10 +bit 00_100 bit 00_101 bit 00_102 bit 00_103 @@ -58,6 +59,7 @@ bit 00_158 bit 00_161 bit 00_162 bit 00_163 +bit 00_164 bit 00_165 bit 00_166 bit 00_167 @@ -112,6 +114,7 @@ bit 00_222 bit 00_225 bit 00_226 bit 00_227 +bit 00_228 bit 00_229 bit 00_23 bit 00_230 @@ -165,6 +168,7 @@ bit 00_289 bit 00_29 bit 00_290 bit 00_291 +bit 00_292 bit 00_293 bit 00_294 bit 00_295 @@ -190,6 +194,7 @@ bit 00_319 bit 00_33 bit 00_34 bit 00_35 +bit 00_36 bit 00_37 bit 00_38 bit 00_39 diff --git a/artix7/mask_dsp_r.db b/artix7/mask_dsp_r.db index 5a0a56f..e7d0fe1 100644 --- a/artix7/mask_dsp_r.db +++ b/artix7/mask_dsp_r.db @@ -6,6 +6,7 @@ bit 00_06 bit 00_07 bit 00_09 bit 00_10 +bit 00_100 bit 00_101 bit 00_102 bit 00_103 @@ -58,6 +59,7 @@ bit 00_158 bit 00_161 bit 00_162 bit 00_163 +bit 00_164 bit 00_165 bit 00_166 bit 00_167 @@ -112,6 +114,7 @@ bit 00_222 bit 00_225 bit 00_226 bit 00_227 +bit 00_228 bit 00_229 bit 00_23 bit 00_230 @@ -165,6 +168,7 @@ bit 00_289 bit 00_29 bit 00_290 bit 00_291 +bit 00_292 bit 00_293 bit 00_294 bit 00_295 @@ -190,6 +194,7 @@ bit 00_319 bit 00_33 bit 00_34 bit 00_35 +bit 00_36 bit 00_37 bit 00_38 bit 00_39 diff --git a/artix7/segbits_clbll_l.db b/artix7/segbits_clbll_l.db index 9acac84..0d6e891 100644 --- a/artix7/segbits_clbll_l.db +++ b/artix7/segbits_clbll_l.db @@ -306,6 +306,7 @@ CLBLL_L.SLICEL_X0.D5FF.MUX.B 30_54 CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51 CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55 CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55 +CLBLL_L.SLICEL_X0.D5FFMUX.IN_B !22_55 !23_55 !24_55 25_55 30_54 CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54 CLBLL_L.SLICEL_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62 CLBLL_L.SLICEL_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61 diff --git a/artix7/segbits_clbll_r.db b/artix7/segbits_clbll_r.db index 3d2ee51..35e785f 100644 --- a/artix7/segbits_clbll_r.db +++ b/artix7/segbits_clbll_r.db @@ -306,6 +306,7 @@ CLBLL_R.SLICEL_X0.D5FF.MUX.B 30_54 CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51 CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55 CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55 +CLBLL_R.SLICEL_X0.D5FFMUX.IN_B !22_55 !23_55 !24_55 25_55 30_54 CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54 CLBLL_R.SLICEL_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62 CLBLL_R.SLICEL_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61 diff --git a/artix7/segbits_clblm_l.db b/artix7/segbits_clblm_l.db index d5b10c0..fe5af05 100644 --- a/artix7/segbits_clblm_l.db +++ b/artix7/segbits_clblm_l.db @@ -695,6 +695,7 @@ CLBLM_L.SLICEM_X0.D5FF.MUX.B 30_54 CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51 CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55 CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55 +CLBLM_L.SLICEM_X0.D5FFMUX.IN_B !22_55 !23_55 !24_55 25_55 30_54 CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54 CLBLM_L.SLICEM_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62 CLBLM_L.SLICEM_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61 diff --git a/artix7/segbits_clblm_r.db b/artix7/segbits_clblm_r.db index 6e5920b..30504bf 100644 --- a/artix7/segbits_clblm_r.db +++ b/artix7/segbits_clblm_r.db @@ -695,6 +695,7 @@ CLBLM_R.SLICEM_X0.D5FF.MUX.B 30_54 CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51 CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55 CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55 +CLBLM_R.SLICEM_X0.D5FFMUX.IN_B !22_55 !23_55 !24_55 25_55 30_54 CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54 CLBLM_R.SLICEM_X0.DFF.DMUX.CY !30_59 !30_61 30_60 30_62 CLBLM_R.SLICEM_X0.DFF.DMUX.DX !30_59 !30_60 !30_62 30_61 diff --git a/artix7/segbits_int_r.db b/artix7/segbits_int_r.db index 3e598f4..40e76ca 100644 --- a/artix7/segbits_int_r.db +++ b/artix7/segbits_int_r.db @@ -728,6 +728,7 @@ INT_R.FAN_ALT6.EL1END1 !22_24 16_24 23_24 24_24 25_24 INT_R.FAN_ALT6.ER1END1 !23_24 17_24 22_24 24_24 25_24 INT_R.FAN_ALT6.FAN_BOUNCE1 !22_24 20_24 23_24 24_24 25_24 INT_R.FAN_ALT6.FAN_BOUNCE7 !23_24 20_24 22_24 24_24 25_24 +INT_R.FAN_ALT6.GFAN0 !22_24 !23_24 !24_24 00_36 21_24 25_24 INT_R.FAN_ALT6.GFAN0 !22_24 !23_24 !24_24 21_24 25_24 INT_R.FAN_ALT6.LOGIC_OUTS1 !23_24 21_24 22_24 24_24 25_24 INT_R.FAN_ALT6.LOGIC_OUTS13 !22_24 21_24 23_24 24_24 25_24 diff --git a/artix7/site_type_BSCAN.json b/artix7/site_type_BSCAN.json index 541fcf6..2527ebb 100644 --- a/artix7/site_type_BSCAN.json +++ b/artix7/site_type_BSCAN.json @@ -1,39 +1,39 @@ { + "type": "BSCAN", + "site_pips": {}, "site_pins": { - "RESET": { - "direction": "OUT" - }, - "TMS": { - "direction": "OUT" - }, - "TDO": { - "direction": "IN" - }, - "SEL": { - "direction": "OUT" - }, "TDI": { "direction": "OUT" }, - "RUNTEST": { + "SEL": { "direction": "OUT" }, "CAPTURE": { "direction": "OUT" }, - "DRCK": { + "SHIFT": { + "direction": "OUT" + }, + "TDO": { + "direction": "IN" + }, + "RESET": { "direction": "OUT" }, "TCK": { "direction": "OUT" }, - "SHIFT": { - "direction": "OUT" - }, "UPDATE": { "direction": "OUT" + }, + "DRCK": { + "direction": "OUT" + }, + "RUNTEST": { + "direction": "OUT" + }, + "TMS": { + "direction": "OUT" } - }, - "type": "BSCAN", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_BUFGCTRL.json b/artix7/site_type_BUFGCTRL.json index 5dada93..5294608 100644 --- a/artix7/site_type_BUFGCTRL.json +++ b/artix7/site_type_BUFGCTRL.json @@ -1,82 +1,82 @@ { + "type": "BUFGCTRL", + "site_pips": { + "CE0INV:CE0": { + "to_pin": "OUT", + "from_pin": "CE0" + }, + "S0INV:S0_B": { + "to_pin": "OUT", + "from_pin": "S0_B" + }, + "CE1INV:CE1_B": { + "to_pin": "OUT", + "from_pin": "CE1_B" + }, + "IGNORE0INV:IGNORE0_B": { + "to_pin": "OUT", + "from_pin": "IGNORE0_B" + }, + "CE1INV:CE1": { + "to_pin": "OUT", + "from_pin": "CE1" + }, + "S0INV:S0": { + "to_pin": "OUT", + "from_pin": "S0" + }, + "IGNORE1INV:IGNORE1": { + "to_pin": "OUT", + "from_pin": "IGNORE1" + }, + "S1INV:S1": { + "to_pin": "OUT", + "from_pin": "S1" + }, + "IGNORE1INV:IGNORE1_B": { + "to_pin": "OUT", + "from_pin": "IGNORE1_B" + }, + "IGNORE0INV:IGNORE0": { + "to_pin": "OUT", + "from_pin": "IGNORE0" + }, + "S1INV:S1_B": { + "to_pin": "OUT", + "from_pin": "S1_B" + }, + "CE0INV:CE0_B": { + "to_pin": "OUT", + "from_pin": "CE0_B" + } + }, "site_pins": { + "O": { + "direction": "OUT" + }, + "I0": { + "direction": "IN" + }, + "IGNORE0": { + "direction": "IN" + }, + "IGNORE1": { + "direction": "IN" + }, + "S0": { + "direction": "IN" + }, + "I1": { + "direction": "IN" + }, "CE1": { "direction": "IN" }, "CE0": { "direction": "IN" }, - "O": { - "direction": "OUT" - }, - "IGNORE1": { - "direction": "IN" - }, - "I0": { - "direction": "IN" - }, - "I1": { - "direction": "IN" - }, "S1": { "direction": "IN" - }, - "S0": { - "direction": "IN" - }, - "IGNORE0": { - "direction": "IN" - } - }, - "type": "BUFGCTRL", - "site_pips": { - "CE0INV:CE0": { - "from_pin": "CE0", - "to_pin": "OUT" - }, - "S0INV:S0": { - "from_pin": "S0", - "to_pin": "OUT" - }, - "CE0INV:CE0_B": { - "from_pin": "CE0_B", - "to_pin": "OUT" - }, - "S0INV:S0_B": { - "from_pin": "S0_B", - "to_pin": "OUT" - }, - "IGNORE1INV:IGNORE1": { - "from_pin": "IGNORE1", - "to_pin": "OUT" - }, - "IGNORE0INV:IGNORE0_B": { - "from_pin": "IGNORE0_B", - "to_pin": "OUT" - }, - "CE1INV:CE1": { - "from_pin": "CE1", - "to_pin": "OUT" - }, - "IGNORE0INV:IGNORE0": { - "from_pin": "IGNORE0", - "to_pin": "OUT" - }, - "S1INV:S1_B": { - "from_pin": "S1_B", - "to_pin": "OUT" - }, - "S1INV:S1": { - "from_pin": "S1", - "to_pin": "OUT" - }, - "IGNORE1INV:IGNORE1_B": { - "from_pin": "IGNORE1_B", - "to_pin": "OUT" - }, - "CE1INV:CE1_B": { - "from_pin": "CE1_B", - "to_pin": "OUT" } } } \ No newline at end of file diff --git a/artix7/site_type_BUFHCE.json b/artix7/site_type_BUFHCE.json index 3af7a43..c32402b 100644 --- a/artix7/site_type_BUFHCE.json +++ b/artix7/site_type_BUFHCE.json @@ -1,24 +1,24 @@ { + "type": "BUFHCE", + "site_pips": { + "CEINV:CE_B": { + "to_pin": "OUT", + "from_pin": "CE_B" + }, + "CEINV:CE": { + "to_pin": "OUT", + "from_pin": "CE" + } + }, "site_pins": { + "I": { + "direction": "IN" + }, "CE": { "direction": "IN" }, "O": { "direction": "OUT" - }, - "I": { - "direction": "IN" - } - }, - "type": "BUFHCE", - "site_pips": { - "CEINV:CE_B": { - "from_pin": "CE_B", - "to_pin": "OUT" - }, - "CEINV:CE": { - "from_pin": "CE", - "to_pin": "OUT" } } } \ No newline at end of file diff --git a/artix7/site_type_BUFIO.json b/artix7/site_type_BUFIO.json index 436387f..b152cdc 100644 --- a/artix7/site_type_BUFIO.json +++ b/artix7/site_type_BUFIO.json @@ -1,12 +1,12 @@ { + "type": "BUFIO", + "site_pips": {}, "site_pins": { - "O": { - "direction": "OUT" - }, "I": { "direction": "IN" + }, + "O": { + "direction": "OUT" } - }, - "type": "BUFIO", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_BUFMRCE.json b/artix7/site_type_BUFMRCE.json index 4185d53..380f6f3 100644 --- a/artix7/site_type_BUFMRCE.json +++ b/artix7/site_type_BUFMRCE.json @@ -1,24 +1,24 @@ { + "type": "BUFMRCE", + "site_pips": { + "CEINV:CE_B": { + "to_pin": "OUT", + "from_pin": "CE_B" + }, + "CEINV:CE": { + "to_pin": "OUT", + "from_pin": "CE" + } + }, "site_pins": { + "I": { + "direction": "IN" + }, "CE": { "direction": "IN" }, "O": { "direction": "OUT" - }, - "I": { - "direction": "IN" - } - }, - "type": "BUFMRCE", - "site_pips": { - "CEINV:CE_B": { - "from_pin": "CE_B", - "to_pin": "OUT" - }, - "CEINV:CE": { - "from_pin": "CE", - "to_pin": "OUT" } } } \ No newline at end of file diff --git a/artix7/site_type_BUFR.json b/artix7/site_type_BUFR.json index 1dbb88b..147e305 100644 --- a/artix7/site_type_BUFR.json +++ b/artix7/site_type_BUFR.json @@ -1,5 +1,10 @@ { + "type": "BUFR", + "site_pips": {}, "site_pins": { + "I": { + "direction": "IN" + }, "CE": { "direction": "IN" }, @@ -8,11 +13,6 @@ }, "O": { "direction": "OUT" - }, - "I": { - "direction": "IN" } - }, - "type": "BUFR", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_CAPTURE.json b/artix7/site_type_CAPTURE.json index 0c6e6b0..8a4e9c3 100644 --- a/artix7/site_type_CAPTURE.json +++ b/artix7/site_type_CAPTURE.json @@ -1,12 +1,12 @@ { + "type": "CAPTURE", + "site_pips": {}, "site_pins": { - "CLK": { - "direction": "IN" - }, "CAP": { "direction": "IN" + }, + "CLK": { + "direction": "IN" } - }, - "type": "CAPTURE", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_DCIRESET.json b/artix7/site_type_DCIRESET.json index c1a62fe..b1e4d52 100644 --- a/artix7/site_type_DCIRESET.json +++ b/artix7/site_type_DCIRESET.json @@ -1,12 +1,12 @@ { + "type": "DCIRESET", + "site_pips": {}, "site_pins": { - "LOCKED": { - "direction": "OUT" - }, "RST": { "direction": "IN" + }, + "LOCKED": { + "direction": "OUT" } - }, - "type": "DCIRESET", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_DNA_PORT.json b/artix7/site_type_DNA_PORT.json index f603512..873a1b4 100644 --- a/artix7/site_type_DNA_PORT.json +++ b/artix7/site_type_DNA_PORT.json @@ -1,21 +1,21 @@ { + "type": "DNA_PORT", + "site_pips": {}, "site_pins": { - "CLK": { + "SHIFT": { "direction": "IN" }, "READ": { "direction": "IN" }, - "DOUT": { - "direction": "OUT" + "CLK": { + "direction": "IN" }, "DIN": { "direction": "IN" }, - "SHIFT": { - "direction": "IN" + "DOUT": { + "direction": "OUT" } - }, - "type": "DNA_PORT", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_DSP48E1.json b/artix7/site_type_DSP48E1.json index 4a8c71b..3a698f4 100644 --- a/artix7/site_type_DSP48E1.json +++ b/artix7/site_type_DSP48E1.json @@ -1,1402 +1,1402 @@ { + "type": "DSP48E1", + "site_pips": { + "CARRYININV:CARRYIN": { + "to_pin": "OUT", + "from_pin": "CARRYIN" + }, + "ALUMODE1INV:ALUMODE1_B": { + "to_pin": "OUT", + "from_pin": "ALUMODE1_B" + }, + "ALUMODE3INV:ALUMODE3": { + "to_pin": "OUT", + "from_pin": "ALUMODE3" + }, + "INMODE1INV:INMODE1": { + "to_pin": "OUT", + "from_pin": "INMODE1" + }, + "OPMODE3INV:OPMODE3": { + "to_pin": "OUT", + "from_pin": "OPMODE3" + }, + "ALUMODE3INV:ALUMODE3_B": { + "to_pin": "OUT", + "from_pin": "ALUMODE3_B" + }, + "INMODE1INV:INMODE1_B": { + "to_pin": "OUT", + "from_pin": "INMODE1_B" + }, + "OPMODE0INV:OPMODE0": { + "to_pin": "OUT", + "from_pin": "OPMODE0" + }, + "INMODE2INV:INMODE2": { + "to_pin": "OUT", + "from_pin": "INMODE2" + }, + "INMODE0INV:INMODE0": { + "to_pin": "OUT", + "from_pin": "INMODE0" + }, + "CLKINV:CLK_B": { + "to_pin": "OUT", + "from_pin": "CLK_B" + }, + "ALUMODE2INV:ALUMODE2": { + "to_pin": "OUT", + "from_pin": "ALUMODE2" + }, + "OPMODE5INV:OPMODE5": { + "to_pin": "OUT", + "from_pin": "OPMODE5" + }, + "INMODE3INV:INMODE3_B": { + "to_pin": "OUT", + "from_pin": "INMODE3_B" + }, + "OPMODE1INV:OPMODE1": { + "to_pin": "OUT", + "from_pin": "OPMODE1" + }, + "OPMODE1INV:OPMODE1_B": { + "to_pin": "OUT", + "from_pin": "OPMODE1_B" + }, + "OPMODE6INV:OPMODE6_B": { + "to_pin": "OUT", + "from_pin": "OPMODE6_B" + }, + "ALUMODE0INV:ALUMODE0_B": { + "to_pin": "OUT", + "from_pin": "ALUMODE0_B" + }, + "CLKINV:CLK": { + "to_pin": "OUT", + "from_pin": "CLK" + }, + "INMODE0INV:INMODE0_B": { + "to_pin": "OUT", + "from_pin": "INMODE0_B" + }, + "INMODE4INV:INMODE4": { + "to_pin": "OUT", + "from_pin": "INMODE4" + }, + "ALUMODE2INV:ALUMODE2_B": { + "to_pin": "OUT", + "from_pin": "ALUMODE2_B" + }, + "OPMODE4INV:OPMODE4": { + "to_pin": "OUT", + "from_pin": "OPMODE4" + }, + "ALUMODE0INV:ALUMODE0": { + "to_pin": "OUT", + "from_pin": "ALUMODE0" + }, + "INMODE2INV:INMODE2_B": { + "to_pin": "OUT", + "from_pin": "INMODE2_B" + }, + "OPMODE6INV:OPMODE6": { + "to_pin": "OUT", + "from_pin": "OPMODE6" + }, + "OPMODE0INV:OPMODE0_B": { + "to_pin": "OUT", + "from_pin": "OPMODE0_B" + }, + "ALUMODE1INV:ALUMODE1": { + "to_pin": "OUT", + "from_pin": "ALUMODE1" + }, + "OPMODE3INV:OPMODE3_B": { + "to_pin": "OUT", + "from_pin": "OPMODE3_B" + }, + "OPMODE2INV:OPMODE2": { + "to_pin": "OUT", + "from_pin": "OPMODE2" + }, + "OPMODE2INV:OPMODE2_B": { + "to_pin": "OUT", + "from_pin": "OPMODE2_B" + }, + "CARRYININV:CARRYIN_B": { + "to_pin": "OUT", + "from_pin": "CARRYIN_B" + }, + "OPMODE5INV:OPMODE5_B": { + "to_pin": "OUT", + "from_pin": "OPMODE5_B" + }, + "INMODE4INV:INMODE4_B": { + "to_pin": "OUT", + "from_pin": "INMODE4_B" + }, + "OPMODE4INV:OPMODE4_B": { + "to_pin": "OUT", + "from_pin": "OPMODE4_B" + }, + "INMODE3INV:INMODE3": { + "to_pin": "OUT", + "from_pin": "INMODE3" + } + }, "site_pins": { - "PCIN6": { - "direction": "IN" - }, - "ACIN3": { - "direction": "IN" - }, - "ACOUT11": { + "P22": { "direction": "OUT" }, - "ACOUT28": { + "PCIN21": { + "direction": "IN" + }, + "P3": { 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+ "BCIN12": { + "direction": "IN" + }, + "C15": { + "direction": "IN" + }, + "C26": { + "direction": "IN" + }, + "A16": { + "direction": "IN" + }, + "ACOUT11": { + "direction": "OUT" + }, + "P29": { + "direction": "OUT" + }, + "D5": { + "direction": "IN" + }, + "ACIN27": { + "direction": "IN" + }, + "ACOUT24": { + "direction": "OUT" + }, + "ACOUT28": { + "direction": "OUT" + }, + "PCOUT37": { + "direction": "OUT" + }, + "PCIN18": { + "direction": "IN" + }, + "CEA1": { + "direction": "IN" + }, + "RSTM": { + "direction": "IN" + }, + "C31": { + "direction": "IN" + }, + "PCIN43": { + "direction": "IN" + }, + "P28": { + "direction": "OUT" + }, + "A28": { + "direction": "IN" + }, + "BCIN17": { + "direction": "IN" + }, + "P13": { + "direction": "OUT" + }, + "PCOUT36": { + "direction": "OUT" + }, + "D16": { + "direction": "IN" + }, + "PCOUT24": { + "direction": "OUT" + }, + "PCOUT17": { + "direction": "OUT" + }, + "PCIN5": { + "direction": "IN" + }, + "RSTCTRL": { + "direction": "IN" + }, + "C5": { + "direction": "IN" + }, + "B4": { + "direction": "IN" + }, + "C33": { + "direction": "IN" + }, + "BCIN8": { + "direction": "IN" + }, + "CARRYIN": { + "direction": "IN" + }, + "B15": { + "direction": "IN" + }, + "INMODE3": { + "direction": "IN" + }, + "PCIN46": { + "direction": "IN" + }, + "P20": { + "direction": "OUT" + }, + "PCIN10": { + "direction": "IN" + }, + "RSTA": { + "direction": "IN" + }, + "BCOUT7": { + "direction": "OUT" + }, + "PCOUT4": { + "direction": "OUT" + }, + "BCIN7": { + "direction": "IN" + }, + "PCIN4": { + "direction": "IN" + }, + "ACIN22": { + "direction": "IN" + }, + "UNDERFLOW": { + "direction": "OUT" + }, + "C3": { + "direction": "IN" + }, + "B12": { + "direction": "IN" + }, + "PCIN36": { + "direction": "IN" + }, + "PCOUT27": { + "direction": "OUT" + }, + "ACIN0": { + "direction": "IN" + }, + "PCIN17": { + "direction": "IN" + }, + "ACIN24": { + "direction": "IN" + }, + "A29": { + "direction": "IN" + }, + "ACOUT17": { + "direction": "OUT" + }, + "ACIN21": { + "direction": "IN" + }, + "PCIN6": { + "direction": "IN" + }, + "ACIN17": { + "direction": "IN" + }, + "C18": { + "direction": "IN" + }, + "BCIN13": { + "direction": "IN" + }, + "PCIN16": { + "direction": "IN" + }, + "PCOUT9": { + "direction": "OUT" + }, + "PCIN37": { + "direction": "IN" + }, + "P39": { + "direction": "OUT" + }, + "ACOUT1": { + "direction": "OUT" + }, + "CARRYINSEL1": { + "direction": "IN" + }, + "C7": { + "direction": "IN" + }, + "C24": { + "direction": "IN" + }, + "D2": { + "direction": "IN" + }, + "P45": { + "direction": "OUT" + }, + "ACOUT14": { + "direction": "OUT" + }, + "P46": { + "direction": "OUT" + }, + "C45": { + "direction": "IN" + }, + "PCIN14": { + "direction": "IN" + }, + "C14": { + "direction": "IN" + }, + "ACOUT25": { + "direction": "OUT" + }, + "ACOUT22": { + "direction": "OUT" + }, + "D23": { + "direction": "IN" + }, + "CLK": { + "direction": "IN" + }, + "C30": { + "direction": "IN" + }, + "ACIN3": { + "direction": "IN" + }, + "BCOUT11": { + "direction": "OUT" + }, + "D1": { + "direction": "IN" + }, + "P34": { + "direction": "OUT" + }, + "ACIN8": { + "direction": "IN" + }, + "P40": { + "direction": "OUT" + }, + "PCIN25": { + "direction": "IN" + }, "P9": { "direction": "OUT" }, "PCIN26": { "direction": "IN" }, - "ACIN4": { - "direction": "IN" - }, - "C41": { - "direction": "IN" - }, - "A23": { - "direction": "IN" - }, - "A21": { - "direction": "IN" - }, - "PCOUT26": { - "direction": "OUT" - }, - "BCOUT8": { - "direction": "OUT" - }, - "P4": { - "direction": "OUT" - }, - "ACIN21": { - "direction": "IN" - }, - "ACIN24": { - "direction": "IN" - }, - "C34": { - "direction": "IN" - }, - "PCOUT5": { - "direction": "OUT" - }, - "ACIN28": { - "direction": "IN" - }, - "PCIN22": { - "direction": "IN" - }, - "P19": { - "direction": "OUT" - }, - "PCIN11": { - "direction": "IN" - }, - "P42": { - "direction": "OUT" - }, - "PCIN20": { - "direction": "IN" - }, - "BCIN1": { - "direction": "IN" - }, - "PCIN45": { - "direction": "IN" - }, - "P7": { - "direction": "OUT" - }, - "PCIN35": { - "direction": "IN" - }, - "PCOUT47": { - "direction": "OUT" - }, - "C14": { - "direction": "IN" - }, - "ACOUT3": { - "direction": "OUT" - }, - "P45": { - "direction": "OUT" - }, - "C16": { - "direction": "IN" - }, - "D1": { - "direction": "IN" - }, - "PCOUT12": { - "direction": "OUT" - }, - "D18": { - "direction": "IN" - }, - "ACIN12": { - "direction": "IN" - }, - "ACIN23": { - "direction": "IN" - }, - "BCIN5": { - "direction": "IN" - }, - "B16": { - "direction": "IN" - }, - "B11": { - "direction": "IN" - }, - "BCOUT0": { - "direction": "OUT" - }, - "CARRYOUT1": { - "direction": "OUT" - }, - "PCOUT27": { - "direction": "OUT" - }, - "P15": { - "direction": "OUT" - }, - "P22": { - "direction": "OUT" - }, - "PCIN0": { - "direction": "IN" - }, - "OVERFLOW": { - "direction": "OUT" - }, - "PCIN5": { - "direction": "IN" - }, - "CEP": { - "direction": "IN" - }, - "OPMODE0": { - "direction": "IN" - }, - "PCOUT43": { - "direction": "OUT" - }, - "C42": { - "direction": "IN" - }, - "A22": { - "direction": "IN" - }, - "ALUMODE2": { - "direction": "IN" - }, - "D8": { - "direction": "IN" - }, - "PCIN41": { - "direction": "IN" - }, - "ACOUT27": { - "direction": "OUT" - }, - "P44": { - "direction": "OUT" - }, "D13": { "direction": "IN" }, - "B12": { + "A2": { "direction": "IN" }, - "C12": { - "direction": "IN" - }, - "P28": { + "ACOUT6": { "direction": "OUT" }, - "PCIN27": { - "direction": "IN" - }, - "PCOUT17": { - "direction": "OUT" - }, - "BCOUT11": { - "direction": "OUT" - }, - "BCOUT16": { - "direction": "OUT" - }, - "RSTM": { - "direction": "IN" - }, - "PCOUT13": { - "direction": "OUT" - }, - "PCOUT21": { - "direction": "OUT" - }, - "PCOUT37": { - "direction": "OUT" - }, - "PCIN10": { - "direction": "IN" - }, - "ACIN11": { - "direction": "IN" - }, - "C9": { - "direction": "IN" - }, - "RSTB": { - "direction": "IN" - }, - "D9": { - "direction": "IN" - }, - "A10": { - "direction": "IN" - }, - "ACOUT26": { - "direction": "OUT" - }, - "A20": { - "direction": "IN" - }, - "D20": { - "direction": "IN" - }, - "MULTSIGNIN": { - "direction": "IN" - }, - "PCIN28": { - "direction": "IN" - }, - "A25": { - "direction": "IN" - }, - "BCIN13": { - "direction": "IN" - }, - "ACIN20": { - "direction": "IN" - }, - "PCIN7": { - "direction": "IN" - }, - "ACIN10": { - "direction": "IN" - }, - "BCIN10": { - "direction": "IN" - }, - "D2": { - "direction": "IN" - }, - "ACIN17": { - "direction": "IN" - }, - "PCIN33": { - "direction": "IN" - }, - "P17": { - "direction": "OUT" - }, - "A9": { - "direction": "IN" - }, - "D4": { - "direction": "IN" - }, - "PCIN4": { - "direction": "IN" - }, - "PCOUT34": { - "direction": "OUT" - }, - "CEINMODE": { - "direction": "IN" - }, - "PCIN8": { - "direction": "IN" - }, - "ACIN2": { - "direction": "IN" - }, - "B4": { - "direction": "IN" - }, - "PCIN13": { - "direction": "IN" - }, - "ACIN7": { - "direction": "IN" - }, - "PCOUT28": { - "direction": "OUT" - }, - "D14": { - "direction": "IN" - }, - "PCOUT1": { - "direction": "OUT" - }, - "ACOUT22": { - "direction": "OUT" - }, - "BCOUT13": { - "direction": "OUT" - }, - "P5": { - "direction": "OUT" - }, - "C33": { - "direction": "IN" - }, - "ACOUT21": { - "direction": "OUT" - }, - "BCOUT1": { - "direction": "OUT" - }, - "OPMODE3": { - "direction": "IN" - }, - "BCOUT15": { - "direction": "OUT" - }, - "B10": { - "direction": "IN" - }, - "BCIN0": { - "direction": "IN" - }, - "ACIN22": { - "direction": "IN" - }, - "ACIN25": { - "direction": "IN" - }, - "CEALUMODE": { - "direction": "IN" - }, - "CARRYOUT0": { - "direction": "OUT" - }, - "D17": { - "direction": "IN" - }, - "P25": { - "direction": "OUT" - }, - "PCOUT35": { - "direction": "OUT" - }, - "PCIN36": { - "direction": "IN" - }, - "A4": { - "direction": "IN" - }, - "PCOUT14": { - "direction": "OUT" - }, - "P27": { - "direction": "OUT" - }, - "C35": { - "direction": "IN" - }, - "P26": { - "direction": "OUT" - }, - "C28": { - "direction": "IN" - }, - "PCIN21": { - "direction": "IN" - }, - "PCIN23": { - "direction": "IN" - }, - "PCIN31": { - "direction": "IN" - }, - "D15": { - "direction": "IN" - }, - "PCOUT9": { - "direction": "OUT" - }, - "P16": { - "direction": "OUT" - }, - "PCIN19": { - "direction": "IN" - }, - "C26": { - "direction": "IN" - }, - "BCOUT4": { - "direction": "OUT" - }, - "ACIN5": { - "direction": "IN" - }, - "ACIN0": { - "direction": "IN" - }, - "B6": { - "direction": "IN" - }, - "PCIN2": { - "direction": "IN" - }, - "D19": { - "direction": "IN" - }, - "P33": { - "direction": "OUT" - }, - "A28": { - "direction": "IN" - }, - "CEA2": { - "direction": "IN" - }, - "ACOUT1": { - "direction": "OUT" - }, - "C25": { - "direction": "IN" - }, - "CARRYINSEL1": { - "direction": "IN" - }, - "D24": { - "direction": "IN" - }, - "RSTALLCARRYIN": { - "direction": "IN" - }, - "D11": { - "direction": "IN" - }, - "A18": { - "direction": "IN" - }, - "P41": { - "direction": "OUT" - }, - "B3": { - "direction": "IN" - }, - "INMODE0": { - "direction": "IN" - }, - "C4": { - "direction": "IN" - }, - "ACIN15": { - "direction": "IN" - }, - "PCOUT33": { - "direction": "OUT" - }, - "C24": { - "direction": "IN" - }, - "PCOUT46": { - "direction": "OUT" - }, - "PATTERNBDETECT": { - "direction": "OUT" - }, - "P23": { - "direction": "OUT" - }, - "A11": { - "direction": "IN" - }, - "ACIN13": { - "direction": "IN" - }, - "C38": { - "direction": "IN" - }, - "P36": { + "P19": { "direction": "OUT" }, "D22": { "direction": "IN" }, - "P43": { + "P30": { "direction": "OUT" }, - "BCIN15": { + "A19": { "direction": "IN" }, - "PCOUT25": { + "ACOUT27": { "direction": "OUT" }, - "BCIN16": { + "PCIN23": { "direction": "IN" }, - "D6": { - "direction": "IN" - }, - "INMODE4": { - "direction": "IN" - }, - "BCOUT3": { + "ACOUT16": { "direction": "OUT" }, - "P34": { - "direction": "OUT" - }, - "B2": { + "RSTINMODE": { "direction": "IN" }, - "PCIN18": { + "OPMODE0": { "direction": "IN" }, - "PCOUT44": { - "direction": "OUT" - }, - "ACOUT15": { - "direction": "OUT" - }, - "P18": { - "direction": "OUT" - }, - "B5": { + "PCIN30": { "direction": "IN" }, - "C13": { - "direction": "IN" - }, - "ACOUT4": { + "PCOUT41": { "direction": "OUT" }, - "ACOUT24": { + "BCIN0": { + "direction": "IN" + }, + "BCOUT13": { "direction": "OUT" }, - "CARRYINSEL0": { + "BCIN10": { "direction": "IN" }, - "PCOUT7": { + "BCOUT4": { "direction": "OUT" }, - "ACOUT10": { + "PCIN33": { + "direction": "IN" + }, + "PCOUT35": { "direction": "OUT" }, - "ACIN16": { + "P24": { + "direction": "OUT" + }, + "RSTD": { "direction": "IN" }, - "B1": { - "direction": "IN" - }, - "BCIN17": { - "direction": "IN" - }, - "PCIN9": { + "PCIN45": { "direction": "IN" }, "BCOUT5": { "direction": "OUT" }, - "D16": { + "D21": { "direction": "IN" }, - "P30": { + "A6": { + "direction": "IN" + }, + "P41": { "direction": "OUT" }, - "P32": { + "C23": { + "direction": "IN" + }, + "P18": { "direction": "OUT" }, - "ALUMODE3": { + "B17": { + "direction": "IN" + }, + "P7": { + "direction": "OUT" + }, + "ACIN16": { + "direction": "IN" + }, + "A23": { + "direction": "IN" + }, + "CEP": { "direction": "IN" }, "C27": { "direction": "IN" }, - "P39": { + "P27": { "direction": "OUT" }, - "D0": { - "direction": "IN" - }, - "B7": { - "direction": "IN" - }, - "C43": { - "direction": "IN" - }, - "OPMODE5": { - "direction": "IN" - }, - "P1": { - "direction": "OUT" - }, - "BCOUT14": { - "direction": "OUT" - }, - "BCOUT7": { - "direction": "OUT" - }, - "A12": { - "direction": "IN" - }, - "PCIN25": { - "direction": "IN" - }, - "ACIN27": { - "direction": "IN" - }, - "B17": { - "direction": "IN" - }, - "ACIN1": { - "direction": "IN" - }, - "A0": { - "direction": "IN" - }, - "CLK": { - "direction": "IN" - }, - "CARRYCASCIN": { - "direction": "IN" - }, - "ACIN18": { - "direction": "IN" - }, - "D3": { - "direction": "IN" - }, - "PCIN37": { - "direction": "IN" - }, - "C37": { - "direction": "IN" - }, - "PCOUT24": { - "direction": "OUT" - }, - "C6": { - "direction": "IN" - }, - "CARRYCASCOUT": { - "direction": "OUT" - }, - "PCIN32": { - "direction": "IN" - }, - "C36": { - "direction": "IN" - }, - "CEB1": { - "direction": "IN" - }, - "ACOUT25": { - "direction": "OUT" - }, - "C7": { - "direction": "IN" - }, - "P8": { - "direction": "OUT" - }, - "MULTSIGNOUT": { - "direction": "OUT" - }, - "ACOUT13": { - "direction": "OUT" - }, - "ACIN26": { - "direction": "IN" - }, - "RSTCTRL": { - "direction": "IN" - }, - "RSTALUMODE": { + "D9": { "direction": "IN" }, "P11": { "direction": "OUT" }, - "D10": { + "ACIN28": { "direction": "IN" }, - "C29": { + "PCIN8": { "direction": "IN" }, - "A1": { + "C10": { "direction": "IN" }, - "C21": { + "BCIN4": { "direction": "IN" }, - "PCOUT19": { + "BCIN9": { + "direction": "IN" + }, + "ACIN9": { + "direction": "IN" + }, + "BCOUT9": { "direction": "OUT" }, - "C2": { - "direction": "IN" - }, - "C22": { - "direction": "IN" - }, - "BCIN8": { - "direction": "IN" - }, - "PCOUT20": { + "BCOUT6": { "direction": "OUT" }, - "D5": { + "PCIN47": { "direction": "IN" }, - "INMODE3": { - "direction": "IN" - }, - "PCIN42": { - "direction": "IN" - }, - "C30": { - "direction": "IN" - }, - "P13": { + "CARRYOUT0": { "direction": "OUT" }, - "ACOUT8": { + "C17": { + "direction": "IN" + }, + "P31": { "direction": "OUT" }, - "A5": { + "BCIN5": { "direction": "IN" }, - "C5": { + "PCOUT6": { + "direction": "OUT" + }, + "B8": { "direction": "IN" }, - "PCIN44": { - "direction": "IN" - }, - "A17": { - "direction": "IN" - }, - "D12": { + "C39": { "direction": "IN" }, "PCOUT16": { "direction": "OUT" }, - "CEC": { + "A24": { "direction": "IN" }, - "BCIN11": { + "C20": { "direction": "IN" }, - "P20": { + "ACOUT12": { "direction": "OUT" - } - }, - "type": "DSP48E1", - "site_pips": { - "CARRYININV:CARRYIN": { - "from_pin": "CARRYIN", - "to_pin": "OUT" }, - "OPMODE4INV:OPMODE4": { - "from_pin": "OPMODE4", - "to_pin": "OUT" + "CEM": { + "direction": "IN" }, - "OPMODE3INV:OPMODE3": { - "from_pin": "OPMODE3", - "to_pin": "OUT" + "ACOUT15": { + "direction": "OUT" }, - "INMODE0INV:INMODE0": { - "from_pin": "INMODE0", - "to_pin": "OUT" + "A26": { + "direction": "IN" }, - "ALUMODE1INV:ALUMODE1": { - "from_pin": "ALUMODE1", - "to_pin": "OUT" + "B1": { + "direction": "IN" }, - "INMODE3INV:INMODE3": { - "from_pin": "INMODE3", - "to_pin": "OUT" + "P6": { + "direction": "OUT" }, - "INMODE4INV:INMODE4": { - "from_pin": "INMODE4", - "to_pin": "OUT" + "ACOUT20": { + "direction": "OUT" }, - "OPMODE3INV:OPMODE3_B": { - "from_pin": "OPMODE3_B", - "to_pin": "OUT" + "P16": { + "direction": "OUT" }, - "OPMODE6INV:OPMODE6": { - "from_pin": "OPMODE6", - "to_pin": "OUT" + "OVERFLOW": { + "direction": "OUT" }, - "INMODE1INV:INMODE1_B": { - "from_pin": "INMODE1_B", - "to_pin": "OUT" + "CEB2": { + "direction": "IN" }, - "OPMODE5INV:OPMODE5": { - "from_pin": "OPMODE5", - "to_pin": "OUT" + "C35": { + "direction": "IN" }, - "ALUMODE2INV:ALUMODE2": { - "from_pin": "ALUMODE2", - "to_pin": "OUT" + "A12": { + "direction": "IN" }, - "OPMODE5INV:OPMODE5_B": { - "from_pin": "OPMODE5_B", - "to_pin": "OUT" + "ACIN13": { + "direction": "IN" }, - "OPMODE0INV:OPMODE0": { - "from_pin": "OPMODE0", - "to_pin": "OUT" + "P10": { + "direction": "OUT" }, - "ALUMODE0INV:ALUMODE0_B": { - "from_pin": "ALUMODE0_B", - "to_pin": "OUT" + "ACOUT0": { + "direction": "OUT" }, - "OPMODE1INV:OPMODE1": { - "from_pin": "OPMODE1", - "to_pin": "OUT" + "BCOUT1": { + "direction": "OUT" }, - "ALUMODE0INV:ALUMODE0": { - "from_pin": "ALUMODE0", - "to_pin": "OUT" + "B16": { + "direction": "IN" }, - "OPMODE4INV:OPMODE4_B": { - "from_pin": "OPMODE4_B", - "to_pin": "OUT" + "C32": { + "direction": "IN" }, - "INMODE4INV:INMODE4_B": { - "from_pin": "INMODE4_B", - "to_pin": "OUT" + "C8": { + "direction": "IN" }, - "INMODE2INV:INMODE2": { - "from_pin": "INMODE2", - "to_pin": "OUT" + "PCOUT43": { + "direction": "OUT" }, - "CARRYININV:CARRYIN_B": { - "from_pin": "CARRYIN_B", - "to_pin": "OUT" + "ACOUT18": { + "direction": "OUT" }, - "INMODE2INV:INMODE2_B": { - "from_pin": "INMODE2_B", - "to_pin": "OUT" + "BCOUT16": { + "direction": "OUT" }, - "OPMODE1INV:OPMODE1_B": { - "from_pin": "OPMODE1_B", - "to_pin": "OUT" - }, - "ALUMODE2INV:ALUMODE2_B": { - "from_pin": "ALUMODE2_B", - "to_pin": "OUT" - }, - "OPMODE6INV:OPMODE6_B": { - "from_pin": "OPMODE6_B", - "to_pin": "OUT" - }, - "OPMODE0INV:OPMODE0_B": { - "from_pin": "OPMODE0_B", - "to_pin": "OUT" - }, - "ALUMODE3INV:ALUMODE3": { - "from_pin": "ALUMODE3", - "to_pin": "OUT" - }, - "ALUMODE3INV:ALUMODE3_B": { - "from_pin": "ALUMODE3_B", - "to_pin": "OUT" - }, - "OPMODE2INV:OPMODE2": { - "from_pin": "OPMODE2", - "to_pin": "OUT" - }, - "INMODE1INV:INMODE1": { - "from_pin": "INMODE1", - "to_pin": "OUT" - }, - "INMODE3INV:INMODE3_B": { - "from_pin": "INMODE3_B", - "to_pin": "OUT" - }, - "OPMODE2INV:OPMODE2_B": { - "from_pin": "OPMODE2_B", - "to_pin": "OUT" - }, - "CLKINV:CLK_B": { - "from_pin": "CLK_B", - "to_pin": "OUT" - }, - "ALUMODE1INV:ALUMODE1_B": { - "from_pin": "ALUMODE1_B", - "to_pin": "OUT" - }, - "CLKINV:CLK": { - "from_pin": "CLK", - "to_pin": "OUT" - }, - "INMODE0INV:INMODE0_B": { - "from_pin": "INMODE0_B", - "to_pin": "OUT" + "D11": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_EFUSE_USR.json b/artix7/site_type_EFUSE_USR.json index c61d9c2..6ba0d2f 100644 --- a/artix7/site_type_EFUSE_USR.json +++ b/artix7/site_type_EFUSE_USR.json @@ -1,9 +1,8 @@ { + "type": "EFUSE_USR", + "site_pips": {}, "site_pins": { - "EFUSEUSR5": { - "direction": "OUT" - }, - "EFUSEUSR26": { + "EFUSEUSR19": { "direction": "OUT" }, "EFUSEUSR23": { @@ -12,76 +11,25 @@ "EFUSEUSR7": { "direction": "OUT" }, - "EFUSEUSR19": { + "EFUSEUSR5": { "direction": "OUT" }, - "EFUSEUSR21": { - "direction": "OUT" - }, - "EFUSEUSR9": { - "direction": "OUT" - }, - "EFUSEUSR8": { - "direction": "OUT" - }, - "EFUSEUSR29": { - "direction": "OUT" - }, - "EFUSEUSR27": { - "direction": "OUT" - }, - "EFUSEUSR13": { - "direction": "OUT" - }, - "EFUSEUSR3": { - "direction": "OUT" - }, - "EFUSEUSR31": { - "direction": "OUT" - }, - "EFUSEUSR2": { - "direction": "OUT" - }, - "EFUSEUSR20": { - "direction": "OUT" - }, - "EFUSEUSR16": { - "direction": "OUT" - }, - "EFUSEUSR1": { - "direction": "OUT" - }, - "EFUSEUSR14": { - "direction": "OUT" - }, - "EFUSEUSR17": { - "direction": "OUT" - }, - "EFUSEUSR6": { - "direction": "OUT" - }, - "EFUSEUSR28": { - "direction": "OUT" - }, - "EFUSEUSR25": { - "direction": "OUT" - }, - "EFUSEUSR4": { - "direction": "OUT" - }, - "EFUSEUSR15": { - "direction": "OUT" - }, - "EFUSEUSR30": { + "EFUSEUSR11": { "direction": "OUT" }, "EFUSEUSR22": { "direction": "OUT" }, - "EFUSEUSR10": { + "EFUSEUSR2": { "direction": "OUT" }, - "EFUSEUSR12": { + "EFUSEUSR27": { + "direction": "OUT" + }, + "EFUSEUSR3": { + "direction": "OUT" + }, + "EFUSEUSR9": { "direction": "OUT" }, "EFUSEUSR24": { @@ -90,13 +38,65 @@ "EFUSEUSR0": { "direction": "OUT" }, - "EFUSEUSR11": { + "EFUSEUSR8": { + "direction": "OUT" + }, + "EFUSEUSR20": { + "direction": "OUT" + }, + "EFUSEUSR13": { + "direction": "OUT" + }, + "EFUSEUSR26": { + "direction": "OUT" + }, + "EFUSEUSR31": { + "direction": "OUT" + }, + "EFUSEUSR10": { + "direction": "OUT" + }, + "EFUSEUSR14": { + "direction": "OUT" + }, + "EFUSEUSR30": { + "direction": "OUT" + }, + "EFUSEUSR21": { + "direction": "OUT" + }, + "EFUSEUSR28": { + "direction": "OUT" + }, + "EFUSEUSR6": { + "direction": "OUT" + }, + "EFUSEUSR4": { + "direction": "OUT" + }, + "EFUSEUSR15": { "direction": "OUT" }, "EFUSEUSR18": { "direction": "OUT" + }, + "EFUSEUSR1": { + "direction": "OUT" + }, + "EFUSEUSR25": { + "direction": "OUT" + }, + "EFUSEUSR29": { + "direction": "OUT" + }, + "EFUSEUSR16": { + "direction": "OUT" + }, + "EFUSEUSR17": { + "direction": "OUT" + }, + "EFUSEUSR12": { + "direction": "OUT" } - }, - "type": "EFUSE_USR", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_FIFO18E1.json b/artix7/site_type_FIFO18E1.json index 409a6c8..dcc904a 100644 --- a/artix7/site_type_FIFO18E1.json +++ b/artix7/site_type_FIFO18E1.json @@ -1,117 +1,194 @@ { + "type": "FIFO18E1", + "site_pips": { + "RDCLKINV:RDCLK_B": { + "to_pin": "OUT", + "from_pin": "RDCLK_B" + }, + "RSTINV:RST": { + "to_pin": "OUT", + "from_pin": "RST" + }, + "RSTINV:RST_B": { + "to_pin": "OUT", + "from_pin": "RST_B" + }, + "RDENINV:RDEN_B": { + "to_pin": "OUT", + "from_pin": "RDEN_B" + }, + "WRENINV:WREN_B": { + "to_pin": "OUT", + "from_pin": "WREN_B" + }, + "RDCLKINV:RDCLK": { + "to_pin": "OUT", + "from_pin": "RDCLK" + }, + "RSTREGINV:RSTREG": { + "to_pin": "OUT", + "from_pin": "RSTREG" + }, + "WRENINV:WREN": { + "to_pin": "OUT", + "from_pin": "WREN" + }, + "RDRCLKINV:RDRCLK": { + "to_pin": "OUT", + "from_pin": "RDRCLK" + }, + "RDRCLKINV:RDRCLK_B": { + "to_pin": "OUT", + "from_pin": "RDRCLK_B" + }, + "WRCLKINV:WRCLK_B": { + "to_pin": "OUT", + "from_pin": "WRCLK_B" + }, + "WRCLKINV:WRCLK": { + "to_pin": "OUT", + "from_pin": "WRCLK" + }, + "RDENINV:RDEN": { + "to_pin": "OUT", + "from_pin": "RDEN" + }, + "RSTREGINV:RSTREG_B": { + "to_pin": "OUT", + "from_pin": "RSTREG_B" + } + }, "site_pins": { - "RDCOUNT4": { + "DO21": { "direction": "OUT" }, - "DIADI4": { - "direction": "IN" - }, - "DO25": { - "direction": "OUT" - }, - "DIADI0": { - "direction": "IN" - }, - "DIADI1": { - "direction": "IN" - }, - "DO17": { - "direction": "OUT" - }, - "ADDRARDADDR7": { - "direction": "IN" - }, - "ADDRARDADDR11": { - "direction": "IN" - }, - "REGCE": { - "direction": "IN" - }, - "WEBWE7": { - "direction": "IN" - }, - "DO23": { - "direction": "OUT" - }, - "ADDRBWRADDR3": { - "direction": "IN" - }, - "WEA0": { - "direction": "IN" - }, - "DIBDI0": { - "direction": "IN" - }, - "RDCOUNT9": { - "direction": "OUT" - }, - "ADDRARDADDR3": { - "direction": "IN" - }, "DIBDI10": { "direction": "IN" }, - "EMPTY": { + "RDRCLK": { + "direction": "IN" + }, + "DO9": { "direction": "OUT" }, - "WRCOUNT11": { + "DO22": { "direction": "OUT" }, - "DO6": { + "RDCOUNT0": { "direction": "OUT" }, - "DO5": { + "ADDRBWRADDR1": { + "direction": "IN" + }, + "WRCOUNT2": { + "direction": "OUT" + }, + "WEBWE6": { + "direction": "IN" + }, + "DO26": { + "direction": "OUT" + }, + "WRCOUNT9": { + "direction": "OUT" + }, + "ADDRBWRADDR12": { + "direction": "IN" + }, + "DO11": { + "direction": "OUT" + }, + "WRCOUNT10": { "direction": "OUT" }, "ADDRARDADDR8": { "direction": "IN" }, - "ADDRBWRADDR0": { + "DIADI10": { "direction": "IN" }, - "ADDRBTIEHIGH1": { - "direction": "IN" - }, - "ADDRARDADDR4": { - "direction": "IN" - }, - "DIPADIP0": { - "direction": "IN" - }, - "WRCOUNT0": { + "DO24": { "direction": "OUT" }, - "DIADI6": { + "ADDRARDADDR3": { "direction": "IN" }, - "DIADI7": { + "REGCEB": { "direction": "IN" }, - "DIADI12": { - "direction": "IN" - }, - "WRCOUNT5": { + "RDCOUNT5": { "direction": "OUT" }, - "ADDRBWRADDR4": { + "DO14": { + "direction": "OUT" + }, + "DIADI11": { "direction": "IN" }, - "REGCLKB": { - "direction": "IN" + "DO23": { + "direction": "OUT" }, - "ADDRATIEHIGH1": { - "direction": "IN" - }, - "ADDRBWRADDR5": { - "direction": "IN" - }, - "DIBDI1": { + "DIADI14": { "direction": "IN" }, "RSTRAMB": { "direction": "IN" }, - "ADDRBWRADDR7": { + "RDCOUNT2": { + "direction": "OUT" + }, + "WRCOUNT6": { + "direction": "OUT" + }, + "WEA1": { + "direction": "IN" + }, + "ADDRARDADDR13": { + "direction": "IN" + }, + "WRCOUNT0": { + "direction": "OUT" + }, + "ALMOSTFULL": { + "direction": "OUT" + }, + "DO19": { + "direction": "OUT" + }, + "DO8": { + "direction": "OUT" + }, + "DO5": { + "direction": "OUT" + }, + "DIADI1": { + "direction": "IN" + }, + "DIADI13": { + "direction": "IN" + }, + "ADDRARDADDR7": { + "direction": "IN" + }, + "ADDRBWRADDR5": { + "direction": "IN" + }, + "DIPBDIP1": { + "direction": "IN" + }, + "WEBWE7": { + "direction": "IN" + }, + "ADDRBTIEHIGH0": { + "direction": "IN" + }, + "DIADI6": { + "direction": "IN" + }, + "DIADI5": { + "direction": "IN" + }, + "RST": { "direction": "IN" }, "DIBDI7": { @@ -120,418 +197,341 @@ "FULL": { "direction": "OUT" }, - "ADDRBWRADDR6": { - "direction": "IN" - }, - "WEBWE0": { - "direction": "IN" - }, - "ADDRBWRADDR13": { - "direction": "IN" - }, - "RST": { - "direction": "IN" - }, - "DOP2": { - "direction": "OUT" - }, - "WEA2": { - "direction": "IN" - }, - "DIBDI14": { - "direction": "IN" - }, - "DIBDI6": { - "direction": "IN" - }, - "ADDRBWRADDR1": { - "direction": "IN" - }, - "DIPBDIP0": { - "direction": "IN" - }, - "WEBWE2": { - "direction": "IN" - }, - "RDERR": { - "direction": "OUT" - }, - "ADDRARDADDR1": { - "direction": "IN" - }, - "DIADI11": { - "direction": "IN" - }, - "DIPBDIP1": { - "direction": "IN" - }, - "ADDRBWRADDR2": { - "direction": "IN" - }, - "ADDRARDADDR13": { - "direction": "IN" - }, - "ADDRATIEHIGH0": { - "direction": "IN" - }, - "DO0": { - "direction": "OUT" - }, - "ADDRBWRADDR11": { - "direction": "IN" - }, - "DO12": { - "direction": "OUT" - }, - "DO2": { - "direction": "OUT" - }, - "WEBWE3": { - "direction": "IN" - }, - "DIBDI8": { - "direction": "IN" - }, - "ADDRBWRADDR8": { - "direction": "IN" - }, - "DIBDI3": { - "direction": "IN" - }, - "DO9": { - "direction": "OUT" - }, - "RDCOUNT1": { - "direction": "OUT" - }, - "RDCOUNT6": { - "direction": "OUT" - }, - "ADDRARDADDR0": { - "direction": "IN" - }, - "ADDRARDADDR5": { - "direction": "IN" - }, - "DIBDI11": { - "direction": "IN" - }, - "WRCOUNT3": { - "direction": "OUT" - }, - "DO16": { - "direction": "OUT" - }, - "RSTREGB": { - "direction": "IN" - }, - "RDCOUNT0": { - "direction": "OUT" - }, - "DO8": { - "direction": "OUT" - }, - "DIADI8": { - "direction": "IN" - }, - "ALMOSTFULL": { - "direction": "OUT" - }, - "WEA3": { - "direction": "IN" - }, - "WEBWE5": { - "direction": "IN" - }, - "DO18": { - "direction": "OUT" - }, - "ADDRBWRADDR9": { - "direction": "IN" - }, - "WEBWE6": { - "direction": "IN" - }, - "WRCOUNT6": { - "direction": "OUT" - }, - "RDCOUNT11": { - "direction": "OUT" - }, - "DO24": { - "direction": "OUT" - }, - "DO20": { - "direction": "OUT" - }, - "RDRCLK": { - "direction": "IN" - }, - "ADDRARDADDR9": { - "direction": "IN" - }, - "DOP0": { - "direction": "OUT" - }, "DIADI2": { "direction": "IN" }, - "DO19": { - "direction": "OUT" - }, - "DIPADIP1": { - "direction": "IN" - }, - "RDCOUNT8": { - "direction": "OUT" - }, - "DO3": { - "direction": "OUT" - }, - "DOP1": { - "direction": "OUT" - }, - "ADDRBWRADDR12": { - "direction": "IN" - }, - "DO14": { - "direction": "OUT" - }, - "DIADI10": { - "direction": "IN" - }, - "DIBDI4": { - "direction": "IN" - }, - "DO4": { - "direction": "OUT" - }, - "WRCOUNT10": { - "direction": "OUT" - }, - "ALMOSTEMPTY": { - "direction": "OUT" - }, - "DIADI13": { - "direction": "IN" - }, - "DIADI14": { - "direction": "IN" - }, - "ADDRBTIEHIGH0": { - "direction": "IN" - }, - "DIBDI2": { - "direction": "IN" - }, "ADDRARDADDR2": { "direction": "IN" }, - "DO31": { + "ADDRARDADDR5": { + "direction": "IN" + }, + "DIBDI15": { + "direction": "IN" + }, + "WEBWE4": { + "direction": "IN" + }, + "DO3": { "direction": "OUT" }, - "WRCOUNT2": { + "DOP0": { "direction": "OUT" }, - "DIADI15": { + "DO18": { + "direction": "OUT" + }, + "DOP2": { + "direction": "OUT" + }, + "ADDRBWRADDR8": { + "direction": "IN" + }, + "ADDRARDADDR0": { + "direction": "IN" + }, + "DIADI3": { "direction": "IN" }, "RDCLK": { "direction": "IN" }, - "DO22": { + "ADDRBWRADDR0": { + "direction": "IN" + }, + "RSTREG": { + "direction": "IN" + }, + "DO25": { "direction": "OUT" }, - "REGCEB": { + "ADDRBWRADDR6": { "direction": "IN" }, + "DIBDI0": { + "direction": "IN" + }, + "DO12": { + "direction": "OUT" + }, + "DO16": { + "direction": "OUT" + }, + "DIADI12": { + "direction": "IN" + }, + "RSTREGB": { + "direction": "IN" + }, + "DIBDI8": { + "direction": "IN" + }, + "WEA3": { + "direction": "IN" + }, + "DO10": { + "direction": "OUT" + }, "WRCOUNT1": { "direction": "OUT" }, + "RDCOUNT6": { + "direction": "OUT" + }, + "DO31": { + "direction": "OUT" + }, + "DIBDI3": { + "direction": "IN" + }, + "ADDRBWRADDR2": { + "direction": "IN" + }, + "DIADI15": { + "direction": "IN" + }, + "EMPTY": { + "direction": "OUT" + }, + "DIBDI5": { + "direction": "IN" + }, + "ADDRBWRADDR3": { + "direction": "IN" + }, + "DIADI4": { + "direction": "IN" + }, + "DO1": { + "direction": "OUT" + }, + "ADDRBWRADDR9": { + "direction": "IN" + }, + "DOP1": { + "direction": "OUT" + }, + "DO0": { + "direction": "OUT" + }, + "WEBWE2": { + "direction": "IN" + }, + "DO28": { + "direction": "OUT" + }, + "WEBWE1": { + "direction": "IN" + }, + "RDCOUNT4": { + "direction": "OUT" + }, + "WEBWE5": { + "direction": "IN" + }, + "DIBDI9": { + "direction": "IN" + }, + "WREN": { + "direction": "IN" + }, + "RDCOUNT10": { + "direction": "OUT" + }, + "DIPBDIP0": { + "direction": "IN" + }, + "DIADI9": { + "direction": "IN" + }, + "ADDRARDADDR11": { + "direction": "IN" + }, + "RDCOUNT8": { + "direction": "OUT" + }, + "RDCOUNT1": { + "direction": "OUT" + }, + "ADDRARDADDR12": { + "direction": "IN" + }, + "WRCLK": { + "direction": "IN" + }, + "ADDRBWRADDR13": { + "direction": "IN" + }, + "DO17": { + "direction": "OUT" + }, + "DIBDI1": { + "direction": "IN" + }, + "DO30": { + "direction": "OUT" + }, + "DIBDI14": { + "direction": "IN" + }, + "ADDRARDADDR10": { + "direction": "IN" + }, + "REGCLKB": { + "direction": "IN" + }, + "DO27": { + "direction": "OUT" + }, + "DIBDI12": { + "direction": "IN" + }, + "DIADI7": { + "direction": "IN" + }, + "REGCE": { + "direction": "IN" + }, + "DIPADIP1": { + "direction": "IN" + }, "DO15": { "direction": "OUT" }, "DO29": { "direction": "OUT" }, - "DO11": { + "DIADI0": { + "direction": "IN" + }, + "ADDRARDADDR4": { + "direction": "IN" + }, + "DO6": { "direction": "OUT" }, - "DIADI5": { - "direction": "IN" - }, - "DIADI3": { - "direction": "IN" - }, - "RSTREG": { + "DIADI8": { "direction": "IN" }, "DO7": { "direction": "OUT" }, - "DIBDI12": { - "direction": "IN" - }, - "WRERR": { - "direction": "OUT" - }, - "WEBWE4": { - "direction": "IN" - }, - "WEBWE1": { - "direction": "IN" - }, - "DO10": { - "direction": "OUT" - }, - "RDEN": { - "direction": "IN" - }, - "WREN": { - "direction": "IN" - }, - "DO26": { - "direction": "OUT" - }, - "RDCOUNT7": { - "direction": "OUT" - }, - "ADDRBWRADDR10": { - "direction": "IN" - }, - "RDCOUNT3": { - "direction": "OUT" - }, - "WRCOUNT7": { - "direction": "OUT" - }, - "ADDRARDADDR6": { - "direction": "IN" - }, - "WEA1": { - "direction": "IN" - }, - "WRCOUNT9": { - "direction": "OUT" - }, - "WRCOUNT4": { - "direction": "OUT" - }, - "DIBDI13": { - "direction": "IN" - }, - "DO27": { - "direction": "OUT" - }, - "DIBDI15": { - "direction": "IN" - }, - "DO30": { - "direction": "OUT" - }, - "DIADI9": { - "direction": "IN" - }, - "DIBDI5": { - "direction": "IN" - }, - "DO13": { - "direction": "OUT" - }, - "ADDRARDADDR12": { - "direction": "IN" - }, - "ADDRARDADDR10": { - "direction": "IN" - }, - "RDCOUNT5": { - "direction": "OUT" - }, - "WRCOUNT8": { - "direction": "OUT" - }, - "DIBDI9": { - "direction": "IN" - }, - "WRCLK": { - "direction": "IN" - }, - "DO1": { - "direction": "OUT" - }, - "RDCOUNT2": { - "direction": "OUT" - }, - "DO28": { - "direction": "OUT" - }, - "RDCOUNT10": { + "ALMOSTEMPTY": { "direction": "OUT" }, "DOP3": { "direction": "OUT" }, - "DO21": { + "ADDRARDADDR1": { + "direction": "IN" + }, + "DIBDI4": { + "direction": "IN" + }, + "ADDRATIEHIGH0": { + "direction": "IN" + }, + "WEBWE0": { + "direction": "IN" + }, + "ADDRBWRADDR11": { + "direction": "IN" + }, + "WEBWE3": { + "direction": "IN" + }, + "ADDRARDADDR6": { + "direction": "IN" + }, + "ADDRATIEHIGH1": { + "direction": "IN" + }, + "RDEN": { + "direction": "IN" + }, + "WRCOUNT8": { "direction": "OUT" - } - }, - "type": "FIFO18E1", - "site_pips": { - "RDENINV:RDEN_B": { - "from_pin": "RDEN_B", - "to_pin": "OUT" }, - "WRENINV:WREN_B": { - "from_pin": "WREN_B", - "to_pin": "OUT" + "WEA0": { + "direction": "IN" }, - "WRCLKINV:WRCLK_B": { - "from_pin": "WRCLK_B", - "to_pin": "OUT" + "RDCOUNT7": { + "direction": "OUT" }, - "RSTREGINV:RSTREG": { - "from_pin": "RSTREG", - "to_pin": "OUT" + "DIPADIP0": { + "direction": "IN" }, - "RSTINV:RST": { - "from_pin": "RST", - "to_pin": "OUT" + "WRCOUNT3": { + "direction": "OUT" }, - "RDCLKINV:RDCLK": { - "from_pin": "RDCLK", - "to_pin": "OUT" + "ADDRBWRADDR7": { + "direction": "IN" }, - "WRCLKINV:WRCLK": { - "from_pin": "WRCLK", - "to_pin": "OUT" + "DO4": { + "direction": "OUT" }, - "RSTINV:RST_B": { - "from_pin": "RST_B", - "to_pin": "OUT" + "WRERR": { + "direction": "OUT" }, - "WRENINV:WREN": { - "from_pin": "WREN", - "to_pin": "OUT" + "ADDRBWRADDR10": { + "direction": "IN" }, - "RDRCLKINV:RDRCLK": { - "from_pin": "RDRCLK", - "to_pin": "OUT" + "WRCOUNT5": { + "direction": "OUT" }, - "RDENINV:RDEN": { - "from_pin": "RDEN", - "to_pin": "OUT" + "WRCOUNT4": { + "direction": "OUT" }, - "RDRCLKINV:RDRCLK_B": { - "from_pin": "RDRCLK_B", - "to_pin": "OUT" + "RDCOUNT11": { + "direction": "OUT" }, - "RSTREGINV:RSTREG_B": { - "from_pin": "RSTREG_B", - "to_pin": "OUT" + "ADDRBWRADDR4": { + "direction": "IN" }, - "RDCLKINV:RDCLK_B": { - "from_pin": "RDCLK_B", - "to_pin": "OUT" + "WRCOUNT11": { + "direction": "OUT" + }, + "WRCOUNT7": { + "direction": "OUT" + }, + "DIBDI13": { + "direction": "IN" + }, + "DO2": { + "direction": "OUT" + }, + "RDCOUNT9": { + "direction": "OUT" + }, + "ADDRARDADDR9": { + "direction": "IN" + }, + "DIBDI2": { + "direction": "IN" + }, + "DO20": { + "direction": "OUT" + }, + "DIBDI11": { + "direction": "IN" + }, + "RDCOUNT3": { + "direction": "OUT" + }, + "ADDRBTIEHIGH1": { + "direction": "IN" + }, + "DO13": { + "direction": "OUT" + }, + "DIBDI6": { + "direction": "IN" + }, + "WEA2": { + "direction": "IN" + }, + "RDERR": { + "direction": "OUT" } } } \ No newline at end of file diff --git a/artix7/site_type_FRAME_ECC.json b/artix7/site_type_FRAME_ECC.json index 9de5d14..c5881ef 100644 --- a/artix7/site_type_FRAME_ECC.json +++ b/artix7/site_type_FRAME_ECC.json @@ -1,171 +1,171 @@ { + "type": "FRAME_ECC", + "site_pips": {}, "site_pins": { - "SYNWORD1": { - "direction": "OUT" - }, - "ECCERRORSINGLE": { - "direction": "OUT" - }, - "SYNDROME10": { + "FAR18": { "direction": "OUT" }, "SYNWORD3": { "direction": "OUT" }, - "FAR14": { - "direction": "OUT" - }, - "FAR22": { - "direction": "OUT" - }, - "FAR12": { - "direction": "OUT" - }, - "ECCERROR": { - "direction": "OUT" - }, - "FAR1": { - "direction": "OUT" - }, - "FAR10": { - "direction": "OUT" - }, - "FAR19": { - "direction": "OUT" - }, - "SYNBIT2": { - "direction": "OUT" - }, - "FAR13": { - "direction": "OUT" - }, - "SYNDROME2": { - "direction": "OUT" - }, - "SYNDROME4": { - "direction": "OUT" - }, - "SYNDROME11": { - "direction": "OUT" - }, - "FAR21": { - "direction": "OUT" - }, - "FAR5": { - "direction": "OUT" - }, - "FAR3": { + "FAR2": { "direction": "OUT" }, "FAR20": { "direction": "OUT" }, - "SYNDROME0": { + "SYNDROME5": { "direction": "OUT" }, - "FAR18": { + "FAR6": { "direction": "OUT" }, - "SYNDROME3": { - "direction": "OUT" - }, - "FAR15": { - "direction": "OUT" - }, - "FAR8": { - "direction": "OUT" - }, - "SYNDROME1": { - "direction": "OUT" - }, - "SYNBIT4": { - "direction": "OUT" - }, - "SYNDROME9": { - "direction": "OUT" - }, - "CRCERROR": { - "direction": "OUT" - }, - "FAR17": { - "direction": "OUT" - }, - "SYNBIT3": { - "direction": "OUT" - }, - "SYNWORD4": { - "direction": "OUT" - }, - "FAR25": { - "direction": "OUT" - }, - "FAR0": { - "direction": "OUT" - }, - "FAR16": { - "direction": "OUT" - }, - "SYNWORD6": { + "FAR10": { "direction": "OUT" }, "SYNDROME12": { "direction": "OUT" }, - "SYNWORD5": { - "direction": "OUT" - }, - "FAR4": { - "direction": "OUT" - }, - "SYNDROME5": { - "direction": "OUT" - }, - "SYNWORD2": { - "direction": "OUT" - }, - "FAR2": { - "direction": "OUT" - }, - "SYNWORD0": { - "direction": "OUT" - }, - "FAR9": { - "direction": "OUT" - }, - "FAR11": { - "direction": "OUT" - }, "SYNDROME8": { "direction": "OUT" }, - "SYNDROME7": { + "FAR15": { + "direction": "OUT" + }, + "FAR14": { + "direction": "OUT" + }, + "SYNDROME1": { + "direction": "OUT" + }, + "SYNWORD6": { + "direction": "OUT" + }, + "FAR0": { + "direction": "OUT" + }, + "SYNWORD1": { + "direction": "OUT" + }, + "FAR3": { + "direction": "OUT" + }, + "SYNBIT4": { "direction": "OUT" }, "FAR23": { "direction": "OUT" }, - "SYNDROME6": { - "direction": "OUT" - }, - "FAR7": { - "direction": "OUT" - }, - "FAR24": { - "direction": "OUT" - }, - "SYNBIT1": { + "CRCERROR": { "direction": "OUT" }, "SYNDROMEVALID": { "direction": "OUT" }, + "SYNBIT3": { + "direction": "OUT" + }, + "SYNDROME2": { + "direction": "OUT" + }, + "SYNDROME10": { + "direction": "OUT" + }, + "FAR13": { + "direction": "OUT" + }, + "FAR21": { + "direction": "OUT" + }, + "SYNBIT2": { + "direction": "OUT" + }, + "FAR22": { + "direction": "OUT" + }, + "ECCERROR": { + "direction": "OUT" + }, + "FAR11": { + "direction": "OUT" + }, + "FAR16": { + "direction": "OUT" + }, + "SYNWORD5": { + "direction": "OUT" + }, + "SYNWORD4": { + "direction": "OUT" + }, + "FAR7": { + "direction": "OUT" + }, + "SYNDROME0": { + "direction": "OUT" + }, + "SYNDROME3": { + "direction": "OUT" + }, + "FAR12": { + "direction": "OUT" + }, + "SYNDROME7": { + "direction": "OUT" + }, + "FAR5": { + "direction": "OUT" + }, + "SYNDROME9": { + "direction": "OUT" + }, + "FAR1": { + "direction": "OUT" + }, + "SYNWORD2": { + "direction": "OUT" + }, + "FAR24": { + "direction": "OUT" + }, + "FAR9": { + "direction": "OUT" + }, + "SYNWORD0": { + "direction": "OUT" + }, + "FAR8": { + "direction": "OUT" + }, + "FAR17": { + "direction": "OUT" + }, "SYNBIT0": { "direction": "OUT" }, - "FAR6": { + "FAR25": { + "direction": "OUT" + }, + "SYNDROME6": { + "direction": "OUT" + }, + "SYNDROME4": { + "direction": "OUT" + }, + "FAR4": { + "direction": "OUT" + }, + "SYNDROME11": { + "direction": "OUT" + }, + "ECCERRORSINGLE": { + "direction": "OUT" + }, + "SYNBIT1": { + "direction": "OUT" + }, + "FAR19": { "direction": "OUT" } - }, - "type": "FRAME_ECC", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_GTPE2_CHANNEL.json b/artix7/site_type_GTPE2_CHANNEL.json index ed5b8a3..5f14cdc 100644 --- a/artix7/site_type_GTPE2_CHANNEL.json +++ b/artix7/site_type_GTPE2_CHANNEL.json @@ -1,228 +1,1057 @@ { + "type": "GTPE2_CHANNEL", + "site_pips": { + "RXUSRCLKINV:RXUSRCLK": { + "to_pin": "OUT", + "from_pin": "RXUSRCLK" + }, + "DMONITORCLKINV:DMONITORCLK_B": { + "to_pin": "OUT", + "from_pin": "DMONITORCLK_B" + }, + "TSTCLK0INV:TSTCLK0": { + "to_pin": "OUT", + "from_pin": "TSTCLK0" + }, + "TSTCLK1INV:TSTCLK1_B": { + "to_pin": "OUT", + "from_pin": "TSTCLK1_B" + }, + "TXUSRCLKINV:TXUSRCLK": { + "to_pin": "OUT", + "from_pin": "TXUSRCLK" + }, + "TXUSRCLK2INV:TXUSRCLK2_B": { + "to_pin": "OUT", + "from_pin": "TXUSRCLK2_B" + }, + "CLKRSVD1INV:CLKRSVD1": { + "to_pin": "OUT", + "from_pin": "CLKRSVD1" + }, + "DRPCLKINV:DRPCLK_B": { + "to_pin": "OUT", + "from_pin": "DRPCLK_B" + }, + "DRPCLKINV:DRPCLK": { + "to_pin": "OUT", + "from_pin": "DRPCLK" + }, + "TSTCLK0INV:TSTCLK0_B": { + "to_pin": "OUT", + "from_pin": "TSTCLK0_B" + }, + "RXUSRCLKINV:RXUSRCLK_B": { + "to_pin": "OUT", + "from_pin": "RXUSRCLK_B" + }, + "SIGVALIDCLKINV:SIGVALIDCLK_B": { + "to_pin": "OUT", + "from_pin": "SIGVALIDCLK_B" + }, + "PMASCANCLK3INV:PMASCANCLK3_B": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK3_B" + }, + "RXUSRCLK2INV:RXUSRCLK2_B": { + "to_pin": "OUT", + "from_pin": "RXUSRCLK2_B" + }, + "TXUSRCLK2INV:TXUSRCLK2": { + "to_pin": "OUT", + "from_pin": "TXUSRCLK2" + }, + "PMASCANCLK3INV:PMASCANCLK3": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK3" + }, + "PMASCANCLK1INV:PMASCANCLK1_B": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK1_B" + }, + "SCANCLKINV:SCANCLK": { + "to_pin": "OUT", + "from_pin": "SCANCLK" + }, + "PMASCANCLK0INV:PMASCANCLK0_B": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK0_B" + }, + "SIGVALIDCLKINV:SIGVALIDCLK": { + "to_pin": "OUT", + "from_pin": "SIGVALIDCLK" + }, + "DMONITORCLKINV:DMONITORCLK": { + "to_pin": "OUT", + "from_pin": "DMONITORCLK" + }, + "CLKRSVD0INV:CLKRSVD0": { + "to_pin": "OUT", + "from_pin": "CLKRSVD0" + }, + "CLKRSVD0INV:CLKRSVD0_B": { + "to_pin": "OUT", + "from_pin": "CLKRSVD0_B" + }, + "TXPHDLYTSTCLKINV:TXPHDLYTSTCLK": { + "to_pin": "OUT", + "from_pin": "TXPHDLYTSTCLK" + }, + "PMASCANCLK0INV:PMASCANCLK0": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK0" + }, + "CLKRSVD1INV:CLKRSVD1_B": { + "to_pin": "OUT", + "from_pin": "CLKRSVD1_B" + }, + "TXUSRCLKINV:TXUSRCLK_B": { + "to_pin": "OUT", + "from_pin": "TXUSRCLK_B" + }, + "RXUSRCLK2INV:RXUSRCLK2": { + "to_pin": "OUT", + "from_pin": "RXUSRCLK2" + }, + "SCANCLKINV:SCANCLK_B": { + "to_pin": "OUT", + "from_pin": "SCANCLK_B" + }, + "TSTCLK1INV:TSTCLK1": { + "to_pin": "OUT", + "from_pin": "TSTCLK1" + }, + "TXPHDLYTSTCLKINV:TXPHDLYTSTCLK_B": { + "to_pin": "OUT", + "from_pin": "TXPHDLYTSTCLK_B" + }, + "PMASCANCLK1INV:PMASCANCLK1": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK1" + }, + "PMASCANCLK2INV:PMASCANCLK2": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK2" + }, + "PMASCANCLK2INV:PMASCANCLK2_B": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK2_B" + } + }, "site_pins": { - "TXSYNCALLIN": { + "PCSRSVDIN5": { "direction": "IN" }, - "RXSTARTOFSEQ1": { + "DRPDO6": { "direction": "OUT" }, - "TXPD0": { + "RXCHBONDI0": { "direction": "IN" }, - "GTRSVD11": { + "TXMAINCURSOR4": { "direction": "IN" }, - "TSTIN1": { + "TSTPD3": { "direction": "IN" }, - "TSTIN16": { + "RXHEADER0": { + "direction": "OUT" + }, + "TXDATA0": { "direction": "IN" }, - "TXRUNDISP1": { + "TXOUTCLKSEL1": { + "direction": "IN" + }, + "DRPADDR2": { + "direction": "IN" + }, + "RXOUTCLKFABRIC": { + "direction": "OUT" + }, + "PMARSVDOUT1": { + "direction": "OUT" + }, + "RXCDRFREQRESET": { + "direction": "IN" + }, + "TXPRECURSOR4": { + "direction": "IN" + }, + "RXDATA7": { + "direction": "OUT" + }, + "TXDATA2": { + "direction": "IN" + }, + "RXSTARTOFSEQ0": { + "direction": "OUT" + }, + "RXNOTINTABLE0": { + "direction": "OUT" + }, + "RXADAPTSELTEST2": { + "direction": "IN" + }, + "PCSRSVDOUT6": { + "direction": "OUT" + }, + "EYESCANTRIGGER": { + "direction": "IN" + }, + "RXLPMHFOVRDEN": { + "direction": "IN" + }, + "RXBUFSTATUS0": { + "direction": "OUT" + }, + "TXSYSCLKSEL0": { + "direction": "IN" + }, + "TXCHARISK2": { + "direction": "IN" + }, + "RXHEADERVALID": { "direction": "OUT" }, "TXCOMWAKE": { "direction": "IN" }, - "PMASCANIN3": { + "TXOUTCLKSEL2": { "direction": "IN" }, - "RXCOMMADET": { + "TSTPDOVRDB": { + "direction": "IN" + }, + "TXCHARDISPMODE3": { + "direction": "IN" + }, + "GTRSVD12": { + "direction": "IN" + }, + "DMONITOROUT10": { "direction": "OUT" }, - "RXPHMONITOR2": { + "RXUSERRDY": { + "direction": "IN" + }, + "RXNOTINTABLE3": { "direction": "OUT" }, - "TSTPD3": { + "TXUSRCLK": { "direction": "IN" }, - "RXRATE1": { - "direction": "IN" - }, - "TXSEQUENCE3": { - "direction": "IN" - }, - "SCANOUT5": { + "TXRATEDONE": { "direction": "OUT" }, - "TXBUFDIFFCTRL2": { - "direction": "IN" - }, - "TXRATE1": { - "direction": "IN" - }, - "RXCHBONDO3": { + "RXCLKCORCNT0": { "direction": "OUT" }, - "RXDATA30": { + "RXCDRRESETRSV": { + "direction": "IN" + }, + "GTPTXP": { "direction": "OUT" }, - "TXPIPPMEN": { + "TXCHARISK1": { "direction": "IN" }, - "TSTIN15": { + "RXOUTCLKSEL2": { "direction": "IN" }, - "GTRSVD7": { + "RXOSINTPD": { "direction": "IN" }, - "TSTIN9": { - "direction": "IN" - }, - "RXPRBSSEL0": { - "direction": "IN" - }, - "SCANOUT2": { + "DRPDO2": { "direction": "OUT" }, - "PCSRSVDOUT13": { + "TSTIN1": { + "direction": "IN" + }, + "GTRSVD14": { + "direction": "IN" + }, + "RXADAPTSELTEST3": { + "direction": "IN" + }, + "PCSRSVDOUT4": { "direction": "OUT" }, - "TXPOSTCURSOR2": { + "RXDLYEN": { "direction": "IN" }, - "RXPHSLIPMONITOR3": { + "PMARSVDIN0": { + "direction": "IN" + }, + "TXPDELECIDLEMODE": { + "direction": "IN" + }, + "GTRSVD15": { + "direction": "IN" + }, + "RXPMARESETDONE": { "direction": "OUT" }, - "RXSYNCOUT": { + "TXPHDLYTSTCLK": { + "direction": "IN" + }, + "PCSRSVDOUT11": { "direction": "OUT" }, - "PMASCANIN1": { - "direction": "IN" - }, - "RXCDRRESET": { - "direction": "IN" - }, - "RXDATA24": { + "DMONITOROUT1": { "direction": "OUT" }, - "PCSRSVDIN7": { - "direction": "IN" - }, - "PCSRSVDIN12": { - "direction": "IN" - }, - "RXADAPTSELTEST8": { - "direction": "IN" - }, - "RXOSINTNTRLEN": { - "direction": "IN" - }, - "DRPDI8": { - "direction": "IN" - }, - "PCSRSVDIN1": { - "direction": "IN" - }, - "CFGRESET": { - "direction": "IN" - }, - "RXCHARISK2": { + "GTPTXN": { "direction": "OUT" }, - "TXPRBSSEL0": { - "direction": "IN" - }, - "EYESCANMODE": { - "direction": "IN" - }, - "RXSTATUS0": { + "RXVALID": { "direction": "OUT" }, - "TXDLYBYPASS": { - "direction": "IN" - }, - "TXDATA17": { - "direction": "IN" - }, - "TSTIN6": { - "direction": "IN" - }, - "TXDLYHOLD": { - "direction": "IN" - }, - "DRPDO8": { + "RXSTATUS2": { "direction": "OUT" }, - "TXRATE2": { + "TXPRECURSOR0": { "direction": "IN" }, - "RXOSCALRESET": { + "LOOPBACK1": { "direction": "IN" }, - "DRPDO11": { + "RXNOTINTABLE2": { "direction": "OUT" }, - "RXADAPTSELTEST10": { - "direction": "IN" - }, - "TXRATEMODE": { - "direction": "IN" - }, - "LOOPBACK0": { - "direction": "IN" - }, - "TXDATA18": { - "direction": "IN" - }, - "TXINHIBIT": { - "direction": "IN" - }, - "RXLPMLFOVRDEN": { - "direction": "IN" - }, - "GTRSVD3": { - "direction": "IN" - }, - "RXPRBSSEL1": { - "direction": "IN" - }, - "DRPDI12": { - "direction": "IN" - }, - "PMASCANCLK0": { - "direction": "IN" - }, - "TSTIN13": { - "direction": "IN" - }, - "RXSYSCLKSEL1": { - "direction": "IN" - }, - "TSTIN0": { - "direction": "IN" - }, - "GTPRXP": { - "direction": "IN" - }, - "PCSRSVDIN10": { - "direction": "IN" - }, - "RXPRBSCNTRESET": { - "direction": "IN" - }, - "RXDATA26": { + "PCSRSVDOUT15": { "direction": "OUT" }, - "TXDATA22": { + "DMONITOROUT3": { + "direction": "OUT" + }, + "RXADAPTSELTEST12": { "direction": "IN" }, - "RXBYTEREALIGN": { + "RXCHBONDO0": { + "direction": "OUT" + }, + "TXDIFFCTRL1": { + "direction": "IN" + }, + "TXSYNCMODE": { + "direction": "IN" + }, + "RXRESETDONE": { "direction": "OUT" }, "PMASCANIN5": { "direction": "IN" }, - "TXPHDLYTSTCLK": { + "RXCHBONDLEVEL0": { "direction": "IN" }, + "SCANIN4": { + "direction": "IN" + }, + "PMASCANOUT3": { + "direction": "OUT" + }, + "RXOSINTSTROBESTARTED": { + "direction": "OUT" + }, + "TXDATA16": { + "direction": "IN" + }, + "TXDATA21": { + "direction": "IN" + }, + "RXDLYTESTENB": { + "direction": "IN" + }, + "DMONITOROUT7": { + "direction": "OUT" + }, + "DRPDO9": { + "direction": "OUT" + }, + "RXDATA27": { + "direction": "OUT" + }, + "SCANIN3": { + "direction": "IN" + }, + "PMASCANOUT5": { + "direction": "OUT" + }, + "TXINHIBIT": { + "direction": "IN" + }, + "TXDLYHOLD": { + "direction": "IN" + }, + "RXDATAVALID0": { + "direction": "OUT" + }, + "RXADAPTSELTEST8": { + "direction": "IN" + }, + "TXDATA10": { + "direction": "IN" + }, + "TXDATA9": { + "direction": "IN" + }, + "TXPCSRESET": { + "direction": "IN" + }, + "TX8B10BBYPASS3": { + "direction": "IN" + }, + "DRPDI7": { + "direction": "IN" + }, + "CLKRSVD0": { + "direction": "IN" + }, + "PMASCANCLK0": { + "direction": "IN" + }, + "SETERRSTATUS": { + "direction": "IN" + }, + "TSTCLK1": { + "direction": "IN" + }, + "RXOSCALRESET": { + "direction": "IN" + }, + "RXCHBONDI2": { + "direction": "IN" + }, + "PMASCANOUT6": { + "direction": "OUT" + }, + "TXBUFDIFFCTRL1": { + "direction": "IN" + }, + "DRPADDR4": { + "direction": "IN" + }, + "TXDLYUPDOWN": { + "direction": "IN" + }, + "RXOSINTCFG0": { + "direction": "IN" + }, + "RXPOLARITY": { + "direction": "IN" + }, + "DMONITOROUT11": { + "direction": "OUT" + }, + "DRPWE": { + "direction": "IN" + }, + "GTRSVD6": { + "direction": "IN" + }, + "RXSYNCALLIN": { + "direction": "IN" + }, + "DMONITOROUT8": { + "direction": "OUT" + }, + "RXOUTCLKPCS": { + "direction": "OUT" + }, + "RXSTATUS1": { + "direction": "OUT" + }, + "RXPHALIGN": { + "direction": "IN" + }, + "RXCHBONDLEVEL2": { + "direction": "IN" + }, + "RXUSRCLK": { + "direction": "IN" + }, + "TXDATA12": { + "direction": "IN" + }, + "TXPHINIT": { + "direction": "IN" + }, + "PCSRSVDOUT1": { + "direction": "OUT" + }, + "TXPIPPMSTEPSIZE3": { + "direction": "IN" + }, + "RXDATA5": { + "direction": "OUT" + }, + "PCSRSVDOUT13": { + "direction": "OUT" + }, + "TXPISOPD": { + "direction": "IN" + }, + "TX8B10BBYPASS0": { + "direction": "IN" + }, + "DRPDI0": { + "direction": "IN" + }, + "TXPOSTCURSOR0": { + "direction": "IN" + }, + "RXCHBONDI3": { + "direction": "IN" + }, + "RXHEADER2": { + "direction": "OUT" + }, + "RXELECIDLEMODE0": { + "direction": "IN" + }, + "PLL0CLK": { + "direction": "IN" + }, + "DMONITOROUT5": { + "direction": "OUT" + }, + "CFGRESET": { + "direction": "IN" + }, + "PMARSVDIN1": { + "direction": "IN" + }, + "RXSYNCMODE": { + "direction": "IN" + }, + "SCANOUT3": { + "direction": "OUT" + }, + "TXSYNCDONE": { + "direction": "OUT" + }, + "RXCDRRESET": { + "direction": "IN" + }, + "RXCLKCORCNT1": { + "direction": "OUT" + }, + "SCANOUT5": { + "direction": "OUT" + }, + "TSTIN3": { + "direction": "IN" + }, + "RXOSINTID00": { + "direction": "IN" + }, + "RXDEBUGPULSE": { + "direction": "IN" + }, + "RXDATA21": { + "direction": "OUT" + }, + "DRPDI15": { + "direction": "IN" + }, + "SIGVALIDCLK": { + "direction": "IN" + }, + "TXDATA5": { + "direction": "IN" + }, + "RXCDROVRDEN": { + "direction": "IN" + }, + "PCSRSVDOUT9": { + "direction": "OUT" + }, + "SCANIN1": { + "direction": "IN" + }, + "PCSRSVDOUT3": { + "direction": "OUT" + }, + "TXPRBSFORCEERR": { + "direction": "IN" + }, + "RXCHARISCOMMA0": { + "direction": "OUT" + }, + "GTRSVD10": { + "direction": "IN" + }, + "DRPDO5": { + "direction": "OUT" + }, + "TSTIN13": { + "direction": "IN" + }, + "RXADAPTSELTEST11": { + "direction": "IN" + }, + "TSTIN9": { + "direction": "IN" + }, + "TSTIN11": { + "direction": "IN" + }, + "TXMAINCURSOR2": { + "direction": "IN" + }, + "RXCHBONDEN": { + "direction": "IN" + }, + "TXSYNCOUT": { + "direction": "OUT" + }, + "TXPHALIGN": { + "direction": "IN" + }, + "RXDATA23": { + "direction": "OUT" + }, + "RXOSOVRDEN": { + "direction": "IN" + }, + "TXPOSTCURSORINV": { + "direction": "IN" + }, + "TXCHARDISPVAL3": { + "direction": "IN" + }, + "TXDATA14": { + "direction": "IN" + }, + "DRPDO14": { + "direction": "OUT" + }, + "RXDATA18": { + "direction": "OUT" + }, + "PCSRSVDOUT10": { + "direction": "OUT" + }, + "RXOSINTSTARTED": { + "direction": "OUT" + }, + "RXCHBONDO3": { + "direction": "OUT" + }, + "TXDATA31": { + "direction": "IN" + }, + "TXPOSTCURSOR1": { + "direction": "IN" + }, + "DRPADDR0": { + "direction": "IN" + }, + "SCANOUT1": { + "direction": "OUT" + }, + "RXOSINTCFG2": { + "direction": "IN" + }, + "PMASCANENB": { + "direction": "IN" + }, + "TXPD1": { + "direction": "IN" + }, + "TXCHARDISPVAL0": { + "direction": "IN" + }, + "SCANIN2": { + "direction": "IN" + }, + "TXRUNDISP2": { + "direction": "OUT" + }, + "DMONITOROUT14": { + "direction": "OUT" + }, + "PMASCANOUT1": { + "direction": "OUT" + }, + "RXCHANREALIGN": { + "direction": "OUT" + }, + "TXDIFFCTRL0": { + "direction": "IN" + }, + "RXHEADER1": { + "direction": "OUT" + }, + "RXCHARISCOMMA1": { + "direction": "OUT" + }, + "TXBUFSTATUS1": { + "direction": "OUT" + }, + "TXPIPPMSEL": { + "direction": "IN" + }, + "EYESCANRESET": { + "direction": "IN" + }, + "DRPADDR3": { + "direction": "IN" + }, + "TXPRECURSOR3": { + "direction": "IN" + }, + "RXRATE1": { + "direction": "IN" + }, + "RXDATA17": { + "direction": "OUT" + }, + "PMASCANIN1": { + "direction": "IN" + }, + "TXDATA30": { + "direction": "IN" + }, + "RXGEARBOXSLIP": { + "direction": "IN" + }, + "DRPDO1": { + "direction": "OUT" + }, + "RESETOVRD": { + "direction": "IN" + }, + "GTPRXP": { + "direction": "IN" + }, + "TSTIN10": { + "direction": "IN" + }, + "RXDATA8": { + "direction": "OUT" + }, + "RXOUTCLKSEL1": { + "direction": "IN" + }, + "TXSEQUENCE2": { + "direction": "IN" + }, + "RXOUTCLK": { + "direction": "OUT" + }, + "DRPDI3": { + "direction": "IN" + }, + "TXPRBSSEL0": { + "direction": "IN" + }, + "TSTIN15": { + "direction": "IN" + }, + "SCANIN0": { + "direction": "IN" + }, + "TXSEQUENCE3": { + "direction": "IN" + }, + "RXCHANBONDSEQ": { + "direction": "OUT" + }, + "RXCOMMADET": { + "direction": "OUT" + }, + "DRPDI5": { + "direction": "IN" + }, + "RXOSINTID02": { + "direction": "IN" + }, + "TXPHINITDONE": { + "direction": "OUT" + }, + "RXDATA30": { + "direction": "OUT" + }, + "TXDATA27": { + "direction": "IN" + }, + "RXADAPTSELTEST9": { + "direction": "IN" + }, + "RXDATA2": { + "direction": "OUT" + }, "RXDATA20": { "direction": "OUT" }, - "PCSRSVDOUT6": { + "PMASCANOUT2": { "direction": "OUT" }, - "TXDIFFPD": { + "TXCOMINIT": { + "direction": "IN" + }, + "TXCHARDISPMODE0": { + "direction": "IN" + }, + "DMONITOROUT9": { + "direction": "OUT" + }, + "RXOSINTSTROBE": { + "direction": "IN" + }, + "DMONITOROUT12": { + "direction": "OUT" + }, + "RXPHSLIPMONITOR3": { + "direction": "OUT" + }, + "RXRATE0": { + "direction": "IN" + }, + "PCSRSVDOUT2": { + "direction": "OUT" + }, + "TX8B10BEN": { + "direction": "IN" + }, + "PLL1REFCLK": { + "direction": "IN" + }, + "PCSRSVDOUT5": { + "direction": "OUT" + }, + "RXPRBSERR": { + "direction": "OUT" + }, + "DRPDI12": { + "direction": "IN" + }, + "TXRESETDONE": { + "direction": "OUT" + }, + "TXRATE1": { + "direction": "IN" + }, + "TXPHALIGNEN": { + "direction": "IN" + }, + "RXDATA10": { + "direction": "OUT" + }, + "GTRXRESET": { + "direction": "IN" + }, + "DRPRDY": { + "direction": "OUT" + }, + "RXPHMONITOR1": { + "direction": "OUT" + }, + "PCSRSVDIN6": { + "direction": "IN" + }, + "RXADAPTSELTEST7": { + "direction": "IN" + }, + "RXADAPTSELTEST0": { + "direction": "IN" + }, + "RXPHALIGNEN": { + "direction": "IN" + }, + "DRPEN": { + "direction": "IN" + }, + "RXPRBSSEL2": { + "direction": "IN" + }, + "TXOUTCLKSEL0": { + "direction": "IN" + }, + "RXOSINTOVRDEN": { + "direction": "IN" + }, + "TSTIN12": { + "direction": "IN" + }, + "RXPHOVRDEN": { + "direction": "IN" + }, + "PCSRSVDIN8": { + "direction": "IN" + }, + "GTRSVD8": { + "direction": "IN" + }, + "RXCHBONDI1": { + "direction": "IN" + }, + "RXDATA22": { + "direction": "OUT" + }, + "GTRSVD1": { + "direction": "IN" + }, + "TXDIFFCTRL3": { + "direction": "IN" + }, + "TXDLYBYPASS": { + "direction": "IN" + }, + "TSTIN0": { + "direction": "IN" + }, + "PMASCANRSTEN": { + "direction": "IN" + }, + "PCSRSVDIN14": { + "direction": "IN" + }, + "TSTIN4": { + "direction": "IN" + }, + "TXRUNDISP0": { + "direction": "OUT" + }, + "TXPOSTCURSOR4": { + "direction": "IN" + }, + "DMONITOROUT4": { + "direction": "OUT" + }, + "GTRSVD0": { + "direction": "IN" + }, + "GTRSVD9": { + "direction": "IN" + }, + "TXDATA3": { + "direction": "IN" + }, + "RXADAPTSELTEST5": { + "direction": "IN" + }, + "RXPHSLIPMONITOR0": { + "direction": "OUT" + }, + "RXDLYOVRDEN": { + "direction": "IN" + }, + "TSTIN17": { + "direction": "IN" + }, + "RXOUTCLKSEL0": { + "direction": "IN" + }, + "SCANMODEB": { + "direction": "IN" + }, + "DRPDO0": { + "direction": "OUT" + }, + "PMARSVDOUT0": { + "direction": "OUT" + }, + "TXPHDLYPD": { + "direction": "IN" + }, + "RXRATE2": { + "direction": "IN" + }, + "DRPADDR7": { + "direction": "IN" + }, + "RXLPMLFOVRDEN": { + "direction": "IN" + }, + "TXBUFDIFFCTRL0": { + "direction": "IN" + }, + "TXPHDLYRESET": { + "direction": "IN" + }, + "RXPHDLYPD": { + "direction": "IN" + }, + "PMASCANOUT0": { + "direction": "OUT" + }, + "TXDATA23": { + "direction": "IN" + }, + "TXPRECURSOR2": { + "direction": "IN" + }, + "TXMAINCURSOR6": { + "direction": "IN" + }, + "TXPRBSSEL1": { + "direction": "IN" + }, + "TXPIPPMPD": { + "direction": "IN" + }, + "RXDATA14": { + "direction": "OUT" + }, + "DMONITOROUT6": { + "direction": "OUT" + }, + "RXPD0": { + "direction": "IN" + }, + "RXOSHOLD": { + "direction": "IN" + }, + "TXPHOVRDEN": { + "direction": "IN" + }, + "EYESCANDATAERROR": { + "direction": "OUT" + }, + "TXDATA26": { + "direction": "IN" + }, + "TXSYNCALLIN": { + "direction": "IN" + }, + "RXDATA12": { + "direction": "OUT" + }, + "TSTPD2": { + "direction": "IN" + }, + "GTRSVD4": { + "direction": "IN" + }, + "RXPHDLYRESET": { + "direction": "IN" + }, + "PCSRSVDIN7": { + "direction": "IN" + }, + "RXCHARISCOMMA3": { + "direction": "OUT" + }, + "GTPRXN": { + "direction": "IN" + }, + "TXDATA19": { + "direction": "IN" + }, + "TXPHALIGNDONE": { + "direction": "OUT" + }, + "RXDATA0": { + "direction": "OUT" + }, + "DRPDI13": { + "direction": "IN" + }, + "RXADAPTSELTEST6": { "direction": "IN" }, "TXUSRCLK2": { @@ -231,1644 +1060,815 @@ "TXMAINCURSOR3": { "direction": "IN" }, - "RXOSHOLD": { - "direction": "IN" - }, - "DRPRDY": { - "direction": "OUT" - }, - "SETERRSTATUS": { - "direction": "IN" - }, - "PMARSVDIN1": { - "direction": "IN" - }, - "TXSEQUENCE4": { - "direction": "IN" - }, - "DMONFIFORESET": { - "direction": "IN" - }, - "DRPADDR5": { - "direction": "IN" - }, - "RXDLYOVRDEN": { - "direction": "IN" - }, - "TSTPD4": { - "direction": "IN" - }, - "TXDATA31": { - "direction": "IN" - }, - "RXDLYSRESET": { - "direction": "IN" - }, - "RXOOBRESET": { - "direction": "IN" - }, - "TXDEEMPH": { - "direction": "IN" - }, - "PHYSTATUS": { - "direction": "OUT" - }, - "PCSRSVDIN0": { - "direction": "IN" - }, - "PCSRSVDIN14": { - "direction": "IN" - }, - "TXOUTCLKSEL0": { - "direction": "IN" - }, - "PMASCANIN0": { - "direction": "IN" - }, - "RXOSINTCFG1": { - "direction": "IN" - }, - "SCANCLK": { - "direction": "IN" - }, - "PCSRSVDIN9": { - "direction": "IN" - }, - "TXOUTCLKPCS": { - "direction": "OUT" - }, - "SCANOUT3": { - "direction": "OUT" - }, - "GTTXRESET": { - "direction": "IN" - }, - "LOOPBACK2": { - "direction": "IN" - }, - "TXDLYSRESET": { - "direction": "IN" - }, - "RXPHALIGNDONE": { - "direction": "OUT" - }, - "TXDATA12": { - "direction": "IN" - }, - "RXADAPTSELTEST2": { - "direction": "IN" - }, - "RXOSINTCFG3": { - "direction": "IN" - }, - "TXPOLARITY": { - "direction": "IN" - }, - "TX8B10BBYPASS1": { - "direction": "IN" - }, - "RXSYSCLKSEL0": { - "direction": "IN" - }, - "RXDATA8": { - "direction": "OUT" - }, - "RXBUFSTATUS0": { - "direction": "OUT" - }, - "TXPHINITDONE": { - "direction": "OUT" - }, - "TXDATA21": { - "direction": "IN" - }, - "TXBUFSTATUS0": { - "direction": "OUT" - }, - "RXHEADER2": { - "direction": "OUT" - }, - "RXCDROVRDEN": { - "direction": "IN" - }, - "RXLPMLFHOLD": { - "direction": "IN" - }, - "RXDATA3": { - "direction": "OUT" - }, - "RXDATA31": { - "direction": "OUT" - }, - "TXDLYUPDOWN": { - "direction": "IN" - }, - "RXLPMHFHOLD": { - "direction": "IN" - }, - "RXELECIDLEMODE0": { - "direction": "IN" - }, - "RXVALID": { - "direction": "OUT" - }, - "TXPCSRESET": { - "direction": "IN" - }, - "TXCHARISK1": { - "direction": "IN" - }, - "RXDLYEN": { - "direction": "IN" - }, - "TXCHARISK2": { - "direction": "IN" - }, - "DRPDO13": { - "direction": "OUT" - }, - "RXRESETDONE": { - "direction": "OUT" - }, - "SCANIN2": { - "direction": "IN" - }, - "RXDATA15": { - "direction": "OUT" - }, - "TXMARGIN2": { - "direction": "IN" - }, - "RXOUTCLKSEL2": { - "direction": "IN" - }, - "RXDATA18": { - "direction": "OUT" - }, - "DMONITOROUT0": { - "direction": "OUT" - }, - "RXCHBONDI3": { - "direction": "IN" - }, "PLL0REFCLK": { "direction": "IN" }, - "TXDLYTESTENB": { - "direction": "IN" - }, - "RXSYNCIN": { - "direction": "IN" - }, - "DRPDI9": { - "direction": "IN" - }, - "TXDATA11": { - "direction": "IN" - }, - "TXPOSTCURSOR1": { - "direction": "IN" - }, - "TXCHARDISPVAL1": { - "direction": "IN" - }, - "PMASCANCLK1": { - "direction": "IN" - }, - "TSTIN19": { - "direction": "IN" - }, - "DRPCLK": { - "direction": "IN" - }, - "PMASCANIN4": { - "direction": "IN" - }, - "TXPIPPMPD": { - "direction": "IN" - }, - "TSTPD1": { - "direction": "IN" - }, - "RXBYTEISALIGNED": { - "direction": "OUT" - }, - "RXSTATUS1": { - "direction": "OUT" - }, - "TXDATA30": { - "direction": "IN" - }, - "TXOUTCLKSEL1": { - "direction": "IN" - }, - "RXCHBONDO1": { - "direction": "OUT" - }, - "PMASCANCLK2": { - "direction": "IN" - }, - "DMONITOROUT6": { - "direction": "OUT" - }, - "DRPDO1": { - "direction": "OUT" - }, - "RXCHBONDLEVEL1": { - "direction": "IN" - }, - "RXOSINTSTROBESTARTED": { - "direction": "OUT" - }, - "RXCLKCORCNT1": { - "direction": "OUT" - }, - "DRPADDR4": { - "direction": "IN" - }, - "TXDATA4": { - "direction": "IN" - }, - "RXDISPERR2": { - "direction": "OUT" - }, - "DMONITOROUT3": { - "direction": "OUT" - }, - "DMONITOROUT1": { - "direction": "OUT" - }, - "PCSRSVDOUT4": { - "direction": "OUT" - }, - "DRPDO2": { - "direction": "OUT" - }, - "RXPMARESET": { - "direction": "IN" - }, - "TXOUTCLK": { - "direction": "OUT" - }, - "RXBUFSTATUS2": { - "direction": "OUT" - }, - "TSTIN5": { - "direction": "IN" - }, - "PCSRSVDIN6": { - "direction": "IN" - }, - "PMARSVDIN3": { - "direction": "IN" - }, - "EYESCANDATAERROR": { - "direction": "OUT" - }, - "RXOSINTSTROBEDONE": { - "direction": "OUT" - }, - "TXELECIDLE": { - "direction": "IN" - }, - "RXSTARTOFSEQ0": { - "direction": "OUT" - }, - "TXDATA10": { - "direction": "IN" - }, - "RXPHMONITOR0": { - "direction": "OUT" - }, - "TXRUNDISP3": { - "direction": "OUT" - }, - "RXRATE2": { - "direction": "IN" - }, - "DMONITORCLK": { - "direction": "IN" - }, - "RXRATEMODE": { - "direction": "IN" - }, - "PMARSVDOUT0": { - "direction": "OUT" - }, - "RXGEARBOXSLIP": { - "direction": "IN" - }, - "RXCHARISCOMMA2": { - "direction": "OUT" - }, - "RXDISPERR0": { - "direction": "OUT" - }, - "DMONITOROUT11": { - "direction": "OUT" - }, - "RXDISPERR1": { - "direction": "OUT" - }, - "TXCOMINIT": { - "direction": "IN" - }, - "TXDIFFCTRL3": { - "direction": "IN" - }, - "RXOSINTPD": { - "direction": "IN" - }, - "RXHEADERVALID": { - "direction": "OUT" - }, - "GTPTXN": { - "direction": "OUT" - }, - "RXCOMSASDET": { - "direction": "OUT" - }, - "DRPDI14": { - "direction": "IN" - }, - "RXPHOVRDEN": { - "direction": "IN" - }, - "TXPOSTCURSORINV": { - "direction": "IN" - }, - "RXADAPTSELTEST4": { - "direction": "IN" - }, - "TXDATA8": { - "direction": "IN" - }, - "RXLPMHFOVRDEN": { - "direction": "IN" - }, - "TXSYNCMODE": { - "direction": "IN" - }, - "TXDETECTRX": { - "direction": "IN" - }, - "RXRATEDONE": { - "direction": "OUT" - }, - "TXPIPPMOVRDEN": { - "direction": "IN" - }, - "PMASCANOUT2": { - "direction": "OUT" - }, - "RXDDIEN": { - "direction": "IN" - }, - "TXDLYSRESETDONE": { - "direction": "OUT" - }, - "GTRSVD4": { - "direction": "IN" - }, - "DRPDO4": { - "direction": "OUT" - }, - "TXPIPPMSTEPSIZE1": { - "direction": "IN" - }, - "DRPADDR0": { - "direction": "IN" - }, - "TXCOMSAS": { - "direction": "IN" - }, - "SCANMODEB": { - "direction": "IN" - }, - "TXUSERRDY": { - "direction": "IN" - }, - "PMASCANIN2": { - "direction": "IN" - }, - "PMASCANMODEB": { - "direction": "IN" - }, - "TXSYNCOUT": { - "direction": "OUT" - }, - "RXOSINTEN": { - "direction": "IN" - }, - "SCANIN3": { - "direction": "IN" - }, - "TXPIPPMSTEPSIZE0": { - "direction": "IN" - }, - "PMASCANIN6": { - "direction": "IN" - }, - "RXPHMONITOR1": { - "direction": "OUT" - }, - "TXCHARDISPVAL3": { - "direction": "IN" - }, - "TXPHALIGN": { - "direction": "IN" - }, - "TXDATA24": { - "direction": "IN" - }, - "RXOSINTID03": { - "direction": "IN" - }, - "RXOSINTID00": { - "direction": "IN" - }, - "RXCHARISCOMMA1": { - "direction": "OUT" - }, - "TXDATA1": { - "direction": "IN" - }, - "GTRSVD13": { - "direction": "IN" - }, - "TXBUFDIFFCTRL0": { - "direction": "IN" - }, - "DRPADDR1": { - "direction": "IN" - }, - "PCSRSVDOUT2": { - "direction": "OUT" - }, - "PMASCANENB": { - "direction": "IN" - }, - "RXPCOMMAALIGNEN": { - "direction": "IN" - }, - "PCSRSVDOUT9": { - "direction": "OUT" - }, - "TXDATA16": { - "direction": "IN" - }, - "DRPDI2": { - "direction": "IN" - }, - "TXDATA26": { - "direction": "IN" - }, - "RXSLIDE": { - "direction": "IN" - }, - "RXADAPTSELTEST9": { - "direction": "IN" - }, - "RXOUTCLK": { - "direction": "OUT" - }, - "RXOSINTID01": { - "direction": "IN" - }, - "TXSEQUENCE1": { - "direction": "IN" - }, - "RXPHALIGN": { - "direction": "IN" - }, - "TXDATA9": { - "direction": "IN" - }, - "TXSYSCLKSEL1": { - "direction": "IN" - }, - "TXSYNCDONE": { - "direction": "OUT" - }, - "RXDATA6": { - "direction": "OUT" - }, - "DRPDO12": { - "direction": "OUT" - }, - "TXRUNDISP2": { - "direction": "OUT" - }, - "RXLPMRESET": { - "direction": "IN" - }, - "RXDATA11": { - "direction": "OUT" - }, - "RXDATA29": { - "direction": "OUT" - }, - "TSTIN12": { - "direction": "IN" - }, - "RXPMARESETDONE": { - "direction": "OUT" - }, - "RXADAPTSELTEST12": { - "direction": "IN" - }, - "TXMAINCURSOR2": { - "direction": "IN" - }, - "RXSYNCMODE": { - "direction": "IN" - }, - "RXDATA12": { - "direction": "OUT" - }, - "TXDATA23": { - "direction": "IN" - }, - "PCSRSVDIN15": { - "direction": "IN" - }, - "RXCHBONDO0": { - "direction": "OUT" - }, - "TXPRBSSEL2": { - "direction": "IN" - }, - "RXOSINTSTARTED": { - "direction": "OUT" - }, - "TX8B10BBYPASS2": { - "direction": "IN" - }, - "RXCHBONDI0": { - "direction": "IN" - }, - "TXDATA20": { - "direction": "IN" - }, - "TXHEADER2": { - "direction": "IN" - }, - "RXPHSLIPMONITOR1": { - "direction": "OUT" - }, - "RXPD0": { - "direction": "IN" - }, - "RXOUTCLKSEL0": { - "direction": "IN" - }, - "RXCOMWAKEDET": { - "direction": "OUT" - }, - "DRPDI5": { - "direction": "IN" - }, - "TXMAINCURSOR1": { - "direction": "IN" - }, - "TXRATEDONE": { - "direction": "OUT" - }, - "TXPRECURSORINV": { - "direction": "IN" - }, - "RXOSINTDONE": { - "direction": "OUT" - }, - "DMONITOROUT10": { - "direction": "OUT" - }, - "TXDIFFCTRL0": { - "direction": "IN" - }, - "RXSYNCALLIN": { - "direction": "IN" - }, - "RXOSINTSTROBE": { - "direction": "IN" - }, - "DRPDI0": { - "direction": "IN" - }, - "DMONITOROUT14": { - "direction": "OUT" - }, - "PMARSVDIN4": { - "direction": "IN" - }, - "RXOSINTCFG0": { - "direction": "IN" - }, - "TXSEQUENCE2": { - "direction": "IN" - }, - "RXCHANBONDSEQ": { - "direction": "OUT" - }, - "TSTIN10": { - "direction": "IN" - }, - "DRPADDR7": { - "direction": "IN" - }, - "TXCHARDISPMODE2": { - "direction": "IN" - }, - "DRPEN": { - "direction": "IN" - }, - "TXPD1": { - "direction": "IN" - }, - "RXOSINTID02": { - "direction": "IN" - }, - "RXADAPTSELTEST7": { - "direction": "IN" - }, - "TXPRECURSOR3": { - "direction": "IN" - }, - "RXDATA17": { - "direction": "OUT" - }, - "RXRATE0": { - "direction": "IN" - }, - "EYESCANTRIGGER": { - "direction": "IN" - }, - "DRPDI4": { - "direction": "IN" - }, - "DRPDI7": { - "direction": "IN" - }, - "TXDATA13": { - "direction": "IN" - }, - "PCSRSVDIN4": { - "direction": "IN" - }, - "DMONITOROUT2": { - "direction": "OUT" - }, - "RXCDRRESETRSV": { - "direction": "IN" - }, - "TXRATE0": { - "direction": "IN" - }, - "RXCHARISK3": { - "direction": "OUT" - }, - "GTRSVD8": { - "direction": "IN" - }, - "RXCHBONDO2": { - "direction": "OUT" - }, - "RXPRBSSEL2": { - "direction": "IN" - }, - "DMONITOROUT12": { - "direction": "OUT" - }, - "RXCLKCORCNT0": { - "direction": "OUT" - }, - "RXCDRHOLD": { - "direction": "IN" - }, - "RX8B10BEN": { - "direction": "IN" - }, - "SCANOUT0": { - "direction": "OUT" - }, - "RXPD1": { - "direction": "IN" - }, - "PCSRSVDOUT14": { - "direction": "OUT" - }, - "DRPDI6": { - "direction": "IN" - }, - "GTRSVD9": { - "direction": "IN" - }, - "RXADAPTSELTEST11": { - "direction": "IN" - }, - "RXDATA9": { - "direction": "OUT" - }, - "PLL0CLK": { - "direction": "IN" - }, - "TXBUFSTATUS1": { - "direction": "OUT" - }, - "TXDIFFCTRL1": { - "direction": "IN" - }, - "RXOSINTHOLD": { - "direction": "IN" - }, - "PMASCANRSTEN": { - "direction": "IN" - }, - "DRPDI3": { - "direction": "IN" - }, - "TSTIN4": { - "direction": "IN" - }, - "TXDLYEN": { - "direction": "IN" - }, - "CLKRSVD0": { - "direction": "IN" - }, - "RXELECIDLE": { - "direction": "OUT" - }, - "TSTIN11": { - "direction": "IN" - }, - "RXDATA25": { - "direction": "OUT" - }, - "RXOSINTOVRDEN": { - "direction": "IN" - }, - "TXPHDLYRESET": { - "direction": "IN" - }, - "DRPDO14": { - "direction": "OUT" - }, - "RXUSERRDY": { - "direction": "IN" - }, - "RXCHBONDI2": { - "direction": "IN" - }, - "RXDATA0": { - "direction": "OUT" - }, - "TSTPDOVRDB": { - "direction": "IN" - }, - "TSTIN18": { - "direction": "IN" - }, - "TXDATA7": { - "direction": "IN" - }, - "TXDIFFCTRL2": { - "direction": "IN" - }, - "RXADAPTSELTEST6": { - "direction": "IN" - }, - "TXPMARESETDONE": { - "direction": "OUT" - }, - "RXELECIDLEMODE1": { - "direction": "IN" - }, - "PMASCANOUT6": { - "direction": "OUT" - }, - "RXCHARISK0": { - "direction": "OUT" - }, - "GTRSVD0": { - "direction": "IN" - }, - "TXDATA25": { - "direction": "IN" - }, - "RXPHSLIPMONITOR0": { - "direction": "OUT" - }, - "TXSEQUENCE0": { - "direction": "IN" - }, - "TXCHARDISPVAL0": { - "direction": "IN" - }, - "TXDATA2": { - "direction": "IN" - }, - "RXDATA2": { - "direction": "OUT" - }, - "RXCHANISALIGNED": { - "direction": "OUT" - }, - "RXADAPTSELTEST5": { - "direction": "IN" - }, - "RXDATA27": { - "direction": "OUT" - }, - "RXNOTINTABLE2": { - "direction": "OUT" - }, - "RXOUTCLKSEL1": { - "direction": "IN" - }, - "TXDATA19": { - "direction": "IN" - }, - "RXCHBONDLEVEL0": { - "direction": "IN" - }, - "RXOSINTTESTOVRDEN": { - "direction": "IN" - }, - "DMONITOROUT4": { - "direction": "OUT" - }, - "PMASCANOUT1": { - "direction": "OUT" - }, - "TXSTARTSEQ": { - "direction": "IN" - }, - "RXADAPTSELTEST3": { - "direction": "IN" - }, - "RXDEBUGPULSE": { - "direction": "IN" - }, - "TXPRECURSOR0": { - "direction": "IN" - }, - "RXDATA13": { - "direction": "OUT" - }, - "RXPRBSERR": { - "direction": "OUT" - }, - "TXMAINCURSOR5": { - "direction": "IN" - }, - "RXCHBONDMASTER": { - "direction": "IN" - }, - "RXCHBONDEN": { - "direction": "IN" - }, - "RXDATA23": { - "direction": "OUT" - }, - "RXPHMONITOR3": { - "direction": "OUT" - }, - "DRPDI1": { - "direction": "IN" - }, - "RXCHBONDSLAVE": { - "direction": "IN" - }, - "SCANOUT4": { - "direction": "OUT" - }, - "RXDATAVALID0": { - "direction": "OUT" - }, - "EYESCANRESET": { - "direction": "IN" - }, - "PCSRSVDOUT11": { - "direction": "OUT" - }, - "PCSRSVDOUT15": { - "direction": "OUT" - }, - "TXOUTCLKSEL2": { - "direction": "IN" - }, - "DRPDO9": { - "direction": "OUT" - }, - "TXPOSTCURSOR4": { - "direction": "IN" - }, - "TXPHOVRDEN": { - "direction": "IN" - }, - "TXDATA27": { - "direction": "IN" - }, - "GTRSVD5": { - "direction": "IN" - }, - "RXDLYSRESETDONE": { - "direction": "OUT" - }, - "PMASCANCLK3": { - "direction": "IN" - }, - "RXBUFRESET": { - "direction": "IN" - }, - "PCSRSVDOUT7": { - "direction": "OUT" - }, - "TX8B10BBYPASS3": { - "direction": "IN" - }, - "TXRESETDONE": { - "direction": "OUT" - }, - "RXDATA22": { - "direction": "OUT" - }, - "TXMARGIN0": { - "direction": "IN" - }, - "DRPDO10": { - "direction": "OUT" - }, - "LOOPBACK1": { - "direction": "IN" - }, - "TXPHALIGNEN": { - "direction": "IN" - }, - "DRPDI13": { - "direction": "IN" - }, - "GTRXRESET": { - "direction": "IN" - }, - "PMASCANOUT3": { - "direction": "OUT" - }, - "RXHEADER0": { - "direction": "OUT" - }, - "RXCDRFREQRESET": { - "direction": "IN" - }, - "PCSRSVDOUT12": { - "direction": "OUT" - }, - "PCSRSVDOUT8": { - "direction": "OUT" - }, - "RXDFEXYDEN": { - "direction": "IN" - }, - "TSTIN7": { - "direction": "IN" - }, - "RXOSINTCFG2": { - "direction": "IN" - }, - "TXCHARISK0": { - "direction": "IN" - }, - "TSTPD0": { - "direction": "IN" - }, - "RXPHDLYRESET": { - "direction": "IN" - }, - "CLKRSVD1": { - "direction": "IN" - }, - "TXPHALIGNDONE": { - "direction": "OUT" - }, - "GTRSVD1": { - "direction": "IN" - }, - "TXHEADER0": { - "direction": "IN" - }, - "RXDATA7": { - "direction": "OUT" - }, - "RXDATA10": { - "direction": "OUT" - }, - "RXDATA28": { - "direction": "OUT" - }, - "PMARSVDIN2": { - "direction": "IN" - }, - "TXDLYOVRDEN": { - "direction": "IN" - }, - "GTRSVD10": { - "direction": "IN" - }, - "GTPRXN": { - "direction": "IN" - }, - "RXDATA14": { - "direction": "OUT" - }, - "TXPRECURSOR4": { - "direction": "IN" - }, - "TXPOSTCURSOR3": { - "direction": "IN" - }, - "RESETOVRD": { - "direction": "IN" - }, - "RXPHDLYPD": { - "direction": "IN" - }, - "RXOSOVRDEN": { - "direction": "IN" - }, - "TX8B10BEN": { - "direction": "IN" - }, - "PCSRSVDOUT5": { - "direction": "OUT" - }, - "TXHEADER1": { - "direction": "IN" - }, - "RXOUTCLKPCS": { - "direction": "OUT" - }, - "DRPADDR6": { - "direction": "IN" - }, - "PMARSVDOUT1": { - "direction": "OUT" - }, - "RXCOMMADETEN": { - "direction": "IN" - }, - "PLL1CLK": { - "direction": "IN" - }, - "TXCOMFINISH": { - "direction": "OUT" - }, - "PCSRSVDIN3": { - "direction": "IN" - }, - "DRPDO0": { - "direction": "OUT" - }, - "RXDATA1": { - "direction": "OUT" - }, - "TXPRECURSOR2": { - "direction": "IN" - }, - "DMONITOROUT13": { - "direction": "OUT" - }, - "DRPDI11": { - "direction": "IN" - }, - "SIGVALIDCLK": { - "direction": "IN" - }, - "GTRSVD12": { - "direction": "IN" - }, - "TSTCLK0": { - "direction": "IN" - }, - "RXDLYBYPASS": { - "direction": "IN" - }, - "GTRSVD6": { - "direction": "IN" - }, - "TXPIPPMSTEPSIZE3": { - "direction": "IN" - }, - "DRPDO7": { - "direction": "OUT" - }, - "RXBUFSTATUS1": { - "direction": "OUT" - }, - "TXSYSCLKSEL0": { - "direction": "IN" - }, - "PLL1REFCLK": { - "direction": "IN" - }, - "TXPIPPMSEL": { - "direction": "IN" - }, - "RXCOMINITDET": { - "direction": "OUT" - }, - "TXDATA6": { - "direction": "IN" - }, - "SCANIN4": { - "direction": "IN" - }, - "TXPOSTCURSOR0": { - "direction": "IN" - }, - "PCSRSVDOUT1": { - "direction": "OUT" - }, - "TXMARGIN1": { - "direction": "IN" - }, - "DMONITOROUT7": { - "direction": "OUT" - }, - "DMONITOROUT8": { - "direction": "OUT" - }, - "TXMAINCURSOR6": { - "direction": "IN" - }, - "RXDATA21": { - "direction": "OUT" - }, - "TXPHINIT": { - "direction": "IN" - }, - "TXMAINCURSOR4": { - "direction": "IN" - }, - "RXOUTCLKFABRIC": { - "direction": "OUT" - }, - "TXDATA0": { - "direction": "IN" - }, - "PCSRSVDIN5": { - "direction": "IN" - }, - "TXDATA14": { - "direction": "IN" - }, - "RXPCSRESET": { - "direction": "IN" - }, - "RXMCOMMAALIGNEN": { - "direction": "IN" - }, - "TXOUTCLKFABRIC": { - "direction": "OUT" - }, - "PCSRSVDIN2": { - "direction": "IN" - }, - "TXSWING": { - "direction": "IN" - }, - "RXPHSLIPMONITOR4": { - "direction": "OUT" - }, - "PCSRSVDOUT0": { - "direction": "OUT" - }, - "TXCHARDISPMODE3": { - "direction": "IN" - }, - "TSTIN8": { - "direction": "IN" - }, - "TXPRECURSOR1": { - "direction": "IN" - }, - "TXDATA28": { - "direction": "IN" - }, - "PMASCANOUT4": { - "direction": "OUT" - }, - "TSTPD2": { - "direction": "IN" - }, - "RXDATA16": { - "direction": "OUT" - }, - "RXPHSLIPMONITOR2": { - "direction": "OUT" - }, - "GTPTXP": { - "direction": "OUT" - }, - "RXADAPTSELTEST13": { - "direction": "IN" - }, - "RXDATA19": { - "direction": "OUT" - }, - "SCANIN0": { - "direction": "IN" - }, - "TXPRBSFORCEERR": { - "direction": "IN" - }, - "TX8B10BBYPASS0": { - "direction": "IN" - }, - "TXCHARDISPVAL2": { - "direction": "IN" - }, - "RXCDRLOCK": { - "direction": "OUT" - }, - "GTRSVD2": { - "direction": "IN" - }, - "DRPADDR8": { - "direction": "IN" - }, - "TXDATA29": { - "direction": "IN" - }, - "RXCHARISCOMMA0": { - "direction": "OUT" - }, - "RXDISPERR3": { - "direction": "OUT" - }, - "RXPHALIGNEN": { - "direction": "IN" - }, - "RXCHANREALIGN": { - "direction": "OUT" - }, - "SCANIN1": { - "direction": "IN" - }, - "DRPDO3": { - "direction": "OUT" - }, - "TXPIPPMSTEPSIZE4": { - "direction": "IN" - }, - "TSTCLK1": { - "direction": "IN" - }, - "DRPDO5": { - "direction": "OUT" - }, - "TXCHARISK3": { - "direction": "IN" - }, - "TSTIN2": { - "direction": "IN" - }, - "RXCHARISCOMMA3": { - "direction": "OUT" - }, - "TXPIPPMSTEPSIZE2": { - "direction": "IN" - }, - "TXBUFDIFFCTRL1": { - "direction": "IN" - }, - "SCANIN5": { - "direction": "IN" - }, - "RXNOTINTABLE0": { - "direction": "OUT" - }, - "PCSRSVDIN11": { - "direction": "IN" - }, - "DMONITOROUT5": { - "direction": "OUT" - }, - "DRPWE": { - "direction": "IN" - }, - "RXPOLARITY": { - "direction": "IN" - }, - "RXDATAVALID1": { - "direction": "OUT" - }, - "TXMAINCURSOR0": { - "direction": "IN" - }, - "PMARSVDIN0": { - "direction": "IN" - }, - "DMONITOROUT9": { - "direction": "OUT" - }, - "RXNOTINTABLE3": { - "direction": "OUT" - }, - "TXSEQUENCE6": { - "direction": "IN" - }, - "SCANOUT1": { - "direction": "OUT" - }, - "RXADAPTSELTEST1": { - "direction": "IN" - }, - "TXDATA5": { - "direction": "IN" - }, - "TXRUNDISP0": { - "direction": "OUT" - }, - "GTRSVD14": { - "direction": "IN" - }, - "RXCHARISK1": { - "direction": "OUT" - }, - "TXPDELECIDLEMODE": { - "direction": "IN" - }, - "TXSYNCIN": { - "direction": "IN" - }, - "TXUSRCLK": { - "direction": "IN" - }, - "PCSRSVDIN8": { - "direction": "IN" - }, - "DRPADDR3": { - "direction": "IN" - }, - "PCSRSVDOUT10": { - "direction": "OUT" - }, - "TXCHARDISPMODE1": { - "direction": "IN" - }, - "RXSYNCDONE": { - "direction": "OUT" - }, - "TXPMARESET": { - "direction": "IN" - }, - "RXNOTINTABLE1": { - "direction": "OUT" - }, - "RXCHBONDLEVEL2": { - "direction": "IN" - }, - "PMASCANOUT0": { - "direction": "OUT" - }, - "RXDATA5": { - "direction": "OUT" - }, - "TXCHARDISPMODE0": { - "direction": "IN" - }, - "RXUSRCLK2": { - "direction": "IN" - }, - "DRPADDR2": { - "direction": "IN" - }, "SCANENB": { "direction": "IN" }, - "TXDATA3": { + "DRPADDR6": { + "direction": "IN" + }, + "DRPDI4": { + "direction": "IN" + }, + "TXDATA18": { + "direction": "IN" + }, + "TXELECIDLE": { + "direction": "IN" + }, + "TXHEADER0": { + "direction": "IN" + }, + "RXPCSRESET": { + "direction": "IN" + }, + "TSTIN19": { + "direction": "IN" + }, + "RXDATA11": { + "direction": "OUT" + }, + "TXDATA4": { + "direction": "IN" + }, + "SCANOUT2": { + "direction": "OUT" + }, + "RXSYNCDONE": { + "direction": "OUT" + }, + "RXOSINTHOLD": { + "direction": "IN" + }, + "TXPIPPMSTEPSIZE4": { + "direction": "IN" + }, + "TXDATA25": { + "direction": "IN" + }, + "RXCHARISCOMMA2": { + "direction": "OUT" + }, + "RXCHBONDO2": { + "direction": "OUT" + }, + "GTTXRESET": { + "direction": "IN" + }, + "RXOSINTID03": { + "direction": "IN" + }, + "TXDATA13": { + "direction": "IN" + }, + "RXDATA3": { + "direction": "OUT" + }, + "PMASCANMODEB": { + "direction": "IN" + }, + "RXUSRCLK2": { + "direction": "IN" + }, + "PCSRSVDIN9": { + "direction": "IN" + }, + "TSTIN8": { "direction": "IN" }, "DRPDI10": { "direction": "IN" }, - "RXADAPTSELTEST0": { + "RXOSINTEN": { "direction": "IN" }, - "RXSTATUS2": { + "RXSTARTOFSEQ1": { + "direction": "OUT" + }, + "TXPMARESET": { + "direction": "IN" + }, + "RXPHSLIPMONITOR2": { + "direction": "OUT" + }, + "RXADAPTSELTEST1": { + "direction": "IN" + }, + "RXPMARESET": { + "direction": "IN" + }, + "TSTIN16": { + "direction": "IN" + }, + "TXDIFFCTRL2": { + "direction": "IN" + }, + "DRPDI2": { + "direction": "IN" + }, + "TXBUFDIFFCTRL2": { + "direction": "IN" + }, + "PMASCANIN3": { + "direction": "IN" + }, + "RXPHSLIPMONITOR1": { + "direction": "OUT" + }, + "RXDATA13": { + "direction": "OUT" + }, + "DRPDI9": { + "direction": "IN" + }, + "TXDATA24": { + "direction": "IN" + }, + "TXCHARDISPVAL1": { + "direction": "IN" + }, + "TXOUTCLK": { + "direction": "OUT" + }, + "TXPOSTCURSOR2": { + "direction": "IN" + }, + "RXOOBRESET": { + "direction": "IN" + }, + "RXOSINTID01": { + "direction": "IN" + }, + "DRPDO10": { + "direction": "OUT" + }, + "PMASCANCLK2": { + "direction": "IN" + }, + "RXDLYSRESETDONE": { + "direction": "OUT" + }, + "PCSRSVDIN2": { + "direction": "IN" + }, + "TXDATA11": { + "direction": "IN" + }, + "TXDATA8": { + "direction": "IN" + }, + "DRPDO8": { + "direction": "OUT" + }, + "RXSYNCOUT": { "direction": "OUT" }, "TXDATA15": { "direction": "IN" }, - "RXPHMONITOR4": { + "RXCHARISK2": { "direction": "OUT" }, - "TXGEARBOXREADY": { - "direction": "OUT" - }, - "PCSRSVDIN13": { + "TXCHARISK0": { "direction": "IN" }, - "PMASCANOUT5": { - "direction": "OUT" - }, - "RXLPMOSINTNTRLEN": { + "TXPIPPMSTEPSIZE2": { "direction": "IN" }, - "TSTIN14": { + "TXSYSCLKSEL1": { "direction": "IN" }, - "TXPHDLYPD": { + "DRPADDR1": { "direction": "IN" }, - "TSTIN17": { + "DRPDI14": { "direction": "IN" }, - "TXSEQUENCE5": { + "TXPRBSSEL2": { "direction": "IN" }, - "RXDLYTESTENB": { - "direction": "IN" - }, - "TXPISOPD": { - "direction": "IN" - }, - "TSTIN3": { + "SCANIN5": { "direction": "IN" }, "RXDATA4": { "direction": "OUT" }, - "RXHEADER1": { - "direction": "OUT" - }, - "PCSRSVDOUT3": { - "direction": "OUT" - }, - "DRPDO15": { - "direction": "OUT" - }, - "DRPDI15": { + "TXDIFFPD": { "direction": "IN" }, - "RXCHBONDI1": { + "PLL1CLK": { "direction": "IN" }, - "DRPDO6": { + "RXDATA16": { "direction": "OUT" }, - "TXPRBSSEL1": { + "LOOPBACK0": { "direction": "IN" }, + "TXPD0": { + "direction": "IN" + }, + "RXDISPERR0": { + "direction": "OUT" + }, + "RXBYTEISALIGNED": { + "direction": "OUT" + }, + "RXPRBSSEL1": { + "direction": "IN" + }, + "TXDLYSRESETDONE": { + "direction": "OUT" + }, + "RXCHARISK0": { + "direction": "OUT" + }, + "RXOSINTNTRLEN": { + "direction": "IN" + }, + "PCSRSVDIN10": { + "direction": "IN" + }, + "DRPADDR8": { + "direction": "IN" + }, + "TSTPD4": { + "direction": "IN" + }, + "TXMAINCURSOR0": { + "direction": "IN" + }, + "RXSYSCLKSEL1": { + "direction": "IN" + }, + "TXPOSTCURSOR3": { + "direction": "IN" + }, + "RXLPMLFHOLD": { + "direction": "IN" + }, + "PMASCANIN2": { + "direction": "IN" + }, + "DRPDI8": { + "direction": "IN" + }, + "RXBUFSTATUS2": { + "direction": "OUT" + }, + "TXSEQUENCE6": { + "direction": "IN" + }, + "RXOSINTSTROBEDONE": { + "direction": "OUT" + }, + "GTRSVD5": { + "direction": "IN" + }, + "TXDATA28": { + "direction": "IN" + }, + "RXPRBSSEL0": { + "direction": "IN" + }, + "DMONFIFORESET": { + "direction": "IN" + }, + "RXDATA26": { + "direction": "OUT" + }, + "RXDATA31": { + "direction": "OUT" + }, + "RXCOMMADETEN": { + "direction": "IN" + }, + "TXOUTCLKFABRIC": { + "direction": "OUT" + }, + "PCSRSVDIN13": { + "direction": "IN" + }, + "TXPIPPMOVRDEN": { + "direction": "IN" + }, + "RXPHALIGNDONE": { + "direction": "OUT" + }, + "TXMAINCURSOR1": { + "direction": "IN" + }, + "TXDATA22": { + "direction": "IN" + }, + "RXSLIDE": { + "direction": "IN" + }, + "RXCHBONDMASTER": { + "direction": "IN" + }, + "RXCDRLOCK": { + "direction": "OUT" + }, + "TXDATA17": { + "direction": "IN" + }, + "RXLPMRESET": { + "direction": "IN" + }, + "PMASCANCLK1": { + "direction": "IN" + }, + "TXDATA6": { + "direction": "IN" + }, + "PMASCANCLK3": { + "direction": "IN" + }, + "DRPDO3": { + "direction": "OUT" + }, + "TXDLYTESTENB": { + "direction": "IN" + }, + "TXRATE2": { + "direction": "IN" + }, + "TXSEQUENCE4": { + "direction": "IN" + }, + "TXCHARDISPMODE1": { + "direction": "IN" + }, + "TSTIN2": { + "direction": "IN" + }, + "TSTPD0": { + "direction": "IN" + }, + "TSTIN6": { + "direction": "IN" + }, + "TXBUFSTATUS0": { + "direction": "OUT" + }, + "PMARSVDIN3": { + "direction": "IN" + }, + "RXOSINTCFG1": { + "direction": "IN" + }, + "TXPRECURSOR1": { + "direction": "IN" + }, + "CLKRSVD1": { + "direction": "IN" + }, + "TXMAINCURSOR5": { + "direction": "IN" + }, + "TSTPD1": { + "direction": "IN" + }, + "GTRSVD11": { + "direction": "IN" + }, + "TXHEADER1": { + "direction": "IN" + }, + "TXCHARISK3": { + "direction": "IN" + }, + "TXDLYEN": { + "direction": "IN" + }, + "DMONITOROUT2": { + "direction": "OUT" + }, + "DRPDO4": { + "direction": "OUT" + }, + "PCSRSVDIN3": { + "direction": "IN" + }, + "TXRATE0": { + "direction": "IN" + }, + "RXOSINTTESTOVRDEN": { + "direction": "IN" + }, + "RXDISPERR1": { + "direction": "OUT" + }, + "TXDATA20": { + "direction": "IN" + }, + "RXBYTEREALIGN": { + "direction": "OUT" + }, + "RXCHBONDSLAVE": { + "direction": "IN" + }, + "TX8B10BBYPASS1": { + "direction": "IN" + }, + "RX8B10BEN": { + "direction": "IN" + }, + "PMASCANIN4": { + "direction": "IN" + }, + "DMONITOROUT0": { + "direction": "OUT" + }, + "PMARSVDIN4": { + "direction": "IN" + }, + "RXDATA6": { + "direction": "OUT" + }, + "RXDDIEN": { + "direction": "IN" + }, + "SCANCLK": { + "direction": "IN" + }, + "RXPRBSCNTRESET": { + "direction": "IN" + }, + "TXRUNDISP1": { + "direction": "OUT" + }, + "TSTIN14": { + "direction": "IN" + }, + "PCSRSVDIN11": { + "direction": "IN" + }, + "RXCHANISALIGNED": { + "direction": "OUT" + }, + "PHYSTATUS": { + "direction": "OUT" + }, + "PCSRSVDOUT8": { + "direction": "OUT" + }, + "PCSRSVDIN15": { + "direction": "IN" + }, + "TSTIN5": { + "direction": "IN" + }, + "RXNOTINTABLE1": { + "direction": "OUT" + }, "GTRESETSEL": { "direction": "IN" }, - "RXUSRCLK": { + "RXCHBONDLEVEL1": { "direction": "IN" }, - "GTRSVD15": { + "TXHEADER2": { "direction": "IN" - } - }, - "type": "GTPE2_CHANNEL", - "site_pips": { - "TSTCLK0INV:TSTCLK0": { - "from_pin": "TSTCLK0", - "to_pin": "OUT" }, - "TXUSRCLK2INV:TXUSRCLK2_B": { - "from_pin": "TXUSRCLK2_B", - "to_pin": "OUT" + "PCSRSVDIN1": { + "direction": "IN" }, - "RXUSRCLKINV:RXUSRCLK_B": { - "from_pin": "RXUSRCLK_B", - "to_pin": "OUT" + "RXCOMWAKEDET": { + "direction": "OUT" }, - "SCANCLKINV:SCANCLK_B": { - "from_pin": "SCANCLK_B", - "to_pin": "OUT" + "RXELECIDLEMODE1": { + "direction": "IN" }, - "CLKRSVD1INV:CLKRSVD1": { - "from_pin": "CLKRSVD1", - "to_pin": "OUT" + "TXDLYOVRDEN": { + "direction": "IN" }, - "PMASCANCLK3INV:PMASCANCLK3": { - "from_pin": "PMASCANCLK3", - "to_pin": "OUT" + "RXCHBONDO1": { + "direction": "OUT" }, - "SIGVALIDCLKINV:SIGVALIDCLK": { - "from_pin": "SIGVALIDCLK", - "to_pin": "OUT" + "PCSRSVDIN4": { + "direction": "IN" }, - "DRPCLKINV:DRPCLK": { - "from_pin": "DRPCLK", - "to_pin": "OUT" + "TXMARGIN0": { + "direction": "IN" }, - "PMASCANCLK3INV:PMASCANCLK3_B": { - "from_pin": "PMASCANCLK3_B", - "to_pin": "OUT" + "DRPDO15": { + "direction": "OUT" }, - "DRPCLKINV:DRPCLK_B": { - "from_pin": "DRPCLK_B", - "to_pin": "OUT" + "RXOSINTCFG3": { + "direction": "IN" }, - "TSTCLK1INV:TSTCLK1_B": { - "from_pin": "TSTCLK1_B", - "to_pin": "OUT" + "RXCOMINITDET": { + "direction": "OUT" }, - "PMASCANCLK2INV:PMASCANCLK2_B": { - "from_pin": "PMASCANCLK2_B", - "to_pin": "OUT" + "RXDLYBYPASS": { + "direction": "IN" }, - "TXPHDLYTSTCLKINV:TXPHDLYTSTCLK_B": { - "from_pin": "TXPHDLYTSTCLK_B", - "to_pin": "OUT" + "TXMARGIN1": { + "direction": "IN" }, - "TSTCLK0INV:TSTCLK0_B": { - "from_pin": "TSTCLK0_B", - "to_pin": "OUT" + "RXOSINTDONE": { + "direction": "OUT" }, - "RXUSRCLK2INV:RXUSRCLK2_B": { - "from_pin": "RXUSRCLK2_B", - "to_pin": "OUT" + "PCSRSVDOUT0": { + "direction": "OUT" }, - "PMASCANCLK0INV:PMASCANCLK0": { - "from_pin": "PMASCANCLK0", - "to_pin": "OUT" + "DRPDO11": { + "direction": "OUT" }, - "TXUSRCLKINV:TXUSRCLK": { - "from_pin": "TXUSRCLK", - "to_pin": "OUT" + "RXADAPTSELTEST10": { + "direction": "IN" }, - "DMONITORCLKINV:DMONITORCLK_B": { - "from_pin": "DMONITORCLK_B", - "to_pin": "OUT" + "PCSRSVDIN0": { + "direction": "IN" }, - "PMASCANCLK1INV:PMASCANCLK1": { - "from_pin": "PMASCANCLK1", - "to_pin": "OUT" + "TXDATA7": { + "direction": "IN" }, - "SIGVALIDCLKINV:SIGVALIDCLK_B": { - "from_pin": "SIGVALIDCLK_B", - "to_pin": "OUT" + "TXSYNCIN": { + "direction": "IN" }, - "TXPHDLYTSTCLKINV:TXPHDLYTSTCLK": { - "from_pin": "TXPHDLYTSTCLK", - "to_pin": "OUT" + "RXRATEDONE": { + "direction": "OUT" }, - "PMASCANCLK0INV:PMASCANCLK0_B": { - "from_pin": "PMASCANCLK0_B", - "to_pin": "OUT" + "SCANOUT4": { + "direction": "OUT" }, - "RXUSRCLK2INV:RXUSRCLK2": { - "from_pin": "RXUSRCLK2", - "to_pin": "OUT" + "RXDATAVALID1": { + "direction": "OUT" }, - "CLKRSVD0INV:CLKRSVD0": { - "from_pin": "CLKRSVD0", - "to_pin": "OUT" + "RXDATA29": { + "direction": "OUT" }, - "CLKRSVD0INV:CLKRSVD0_B": { - "from_pin": "CLKRSVD0_B", - "to_pin": "OUT" + "PCSRSVDOUT12": { + "direction": "OUT" }, - "PMASCANCLK1INV:PMASCANCLK1_B": { - "from_pin": "PMASCANCLK1_B", - "to_pin": "OUT" + "RXPHMONITOR4": { + "direction": "OUT" }, - "SCANCLKINV:SCANCLK": { - "from_pin": "SCANCLK", - "to_pin": "OUT" + "TXSEQUENCE5": { + "direction": "IN" }, - "RXUSRCLKINV:RXUSRCLK": { - "from_pin": "RXUSRCLK", - "to_pin": "OUT" + "TXCHARDISPVAL2": { + "direction": "IN" }, - "PMASCANCLK2INV:PMASCANCLK2": { - "from_pin": "PMASCANCLK2", - "to_pin": "OUT" + "PCSRSVDOUT7": { + "direction": "OUT" }, - "DMONITORCLKINV:DMONITORCLK": { - "from_pin": "DMONITORCLK", - "to_pin": "OUT" + "GTRSVD2": { + "direction": "IN" }, - "CLKRSVD1INV:CLKRSVD1_B": { - "from_pin": "CLKRSVD1_B", - "to_pin": "OUT" + "DRPDO12": { + "direction": "OUT" }, - "TSTCLK1INV:TSTCLK1": { - "from_pin": "TSTCLK1", - "to_pin": "OUT" + "RXADAPTSELTEST13": { + "direction": "IN" }, - "TXUSRCLK2INV:TXUSRCLK2": { - "from_pin": "TXUSRCLK2", - "to_pin": "OUT" + "TXSEQUENCE1": { + "direction": "IN" }, - "TXUSRCLKINV:TXUSRCLK_B": { - "from_pin": "TXUSRCLK_B", - "to_pin": "OUT" + "GTRSVD7": { + "direction": "IN" + }, + "RXDATA28": { + "direction": "OUT" + }, + "RXDATA9": { + "direction": "OUT" + }, + "DRPDI11": { + "direction": "IN" + }, + "TX8B10BBYPASS2": { + "direction": "IN" + }, + "TXSEQUENCE0": { + "direction": "IN" + }, + "TSTIN7": { + "direction": "IN" + }, + "RXDATA24": { + "direction": "OUT" + }, + "RXLPMHFHOLD": { + "direction": "IN" + }, + "PMASCANIN6": { + "direction": "IN" + }, + "TXRATEMODE": { + "direction": "IN" + }, + "RXPHMONITOR0": { + "direction": "OUT" + }, + "RXSYSCLKSEL0": { + "direction": "IN" + }, + "DRPDI6": { + "direction": "IN" + }, + "TXDLYSRESET": { + "direction": "IN" + }, + "RXRATEMODE": { + "direction": "IN" + }, + "TXPOLARITY": { + "direction": "IN" + }, + "RXCDRHOLD": { + "direction": "IN" + }, + "TXOUTCLKPCS": { + "direction": "OUT" + }, + "PCSRSVDOUT14": { + "direction": "OUT" + }, + "RXADAPTSELTEST4": { + "direction": "IN" + }, + "TXSTARTSEQ": { + "direction": "IN" + }, + "RXPHSLIPMONITOR4": { + "direction": "OUT" + }, + "DRPDO13": { + "direction": "OUT" + }, + "RXPHMONITOR2": { + "direction": "OUT" + }, + "RXSYNCIN": { + "direction": "IN" + }, + "RXMCOMMAALIGNEN": { + "direction": "IN" + }, + "RXPCOMMAALIGNEN": { + "direction": "IN" + }, + "DMONITOROUT13": { + "direction": "OUT" + }, + "RXCHARISK1": { + "direction": "OUT" + }, + "RXCHARISK3": { + "direction": "OUT" + }, + "RXLPMOSINTNTRLEN": { + "direction": "IN" + }, + "RXCOMSASDET": { + "direction": "OUT" + }, + "RXSTATUS0": { + "direction": "OUT" + }, + "TXGEARBOXREADY": { + "direction": "OUT" + }, + "RXBUFSTATUS1": { + "direction": "OUT" + }, + "GTRSVD3": { + "direction": "IN" + }, + "RXDATA15": { + "direction": "OUT" + }, + "DRPADDR5": { + "direction": "IN" + }, + "TXPIPPMSTEPSIZE0": { + "direction": "IN" + }, + "TXPIPPMEN": { + "direction": "IN" + }, + "TXUSERRDY": { + "direction": "IN" + }, + "RXDATA25": { + "direction": "OUT" + }, + "RXDISPERR3": { + "direction": "OUT" + }, + "EYESCANMODE": { + "direction": "IN" + }, + "RXDISPERR2": { + "direction": "OUT" + }, + "RXDATA19": { + "direction": "OUT" + }, + "TXCOMFINISH": { + "direction": "OUT" + }, + "RXDLYSRESET": { + "direction": "IN" + }, + "TXCHARDISPMODE2": { + "direction": "IN" + }, + "GTRSVD13": { + "direction": "IN" + }, + "TXRUNDISP3": { + "direction": "OUT" + }, + "TXMARGIN2": { + "direction": "IN" + }, + "PMARSVDIN2": { + "direction": "IN" + }, + "TSTCLK0": { + "direction": "IN" + }, + "TXPMARESETDONE": { + "direction": "OUT" + }, + "LOOPBACK2": { + "direction": "IN" + }, + "RXPHMONITOR3": { + "direction": "OUT" + }, + "TXDATA29": { + "direction": "IN" + }, + "DRPDI1": { + "direction": "IN" + }, + "TXPRECURSORINV": { + "direction": "IN" + }, + "RXDFEXYDEN": { + "direction": "IN" + }, + "PMASCANOUT4": { + "direction": "OUT" + }, + "TXPIPPMSTEPSIZE1": { + "direction": "IN" + }, + "RXDATA1": { + "direction": "OUT" + }, + "RXPD1": { + "direction": "IN" + }, + "RXBUFRESET": { + "direction": "IN" + }, + "TXSWING": { + "direction": "IN" + }, + "PMASCANIN0": { + "direction": "IN" + }, + "SCANOUT0": { + "direction": "OUT" + }, + "DRPDO7": { + "direction": "OUT" + }, + "TXDEEMPH": { + "direction": "IN" + }, + "TSTIN18": { + "direction": "IN" + }, + "PCSRSVDIN12": { + "direction": "IN" + }, + "RXELECIDLE": { + "direction": "OUT" + }, + "TXDATA1": { + "direction": "IN" + }, + "DRPCLK": { + "direction": "IN" + }, + "TXCOMSAS": { + "direction": "IN" + }, + "DMONITORCLK": { + "direction": "IN" + }, + "TXDETECTRX": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_GTPE2_COMMON.json b/artix7/site_type_GTPE2_COMMON.json index 8be71d0..3f55a4b 100644 --- a/artix7/site_type_GTPE2_COMMON.json +++ b/artix7/site_type_GTPE2_COMMON.json @@ -1,234 +1,394 @@ { - "site_pins": { - "PLL0OUTCLK": { - "direction": "OUT" + "type": "GTPE2_COMMON", + "site_pips": { + "DRPCLKINV:DRPCLK": { + "to_pin": "OUT", + "from_pin": "DRPCLK" }, + "PLL1LOCKDETCLKINV:PLL1LOCKDETCLK_B": { + "to_pin": "OUT", + "from_pin": "PLL1LOCKDETCLK_B" + }, + "PLL0LOCKDETCLKINV:PLL0LOCKDETCLK_B": { + "to_pin": "OUT", + "from_pin": "PLL0LOCKDETCLK_B" + }, + "PMASCANCLK0INV:PMASCANCLK0_B": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK0_B" + }, + "PLLCLKSPAREINV:PLLCLKSPARE": { + "to_pin": "OUT", + "from_pin": "PLLCLKSPARE" + }, + "DRPCLKINV:DRPCLK_B": { + "to_pin": "OUT", + "from_pin": "DRPCLK_B" + }, + "PLLCLKSPAREINV:PLLCLKSPARE_B": { + "to_pin": "OUT", + "from_pin": "PLLCLKSPARE_B" + }, + "PLL0LOCKDETCLKINV:PLL0LOCKDETCLK": { + "to_pin": "OUT", + "from_pin": "PLL0LOCKDETCLK" + }, + "GTGREFCLK0INV:GTGREFCLK0_B": { + "to_pin": "OUT", + "from_pin": "GTGREFCLK0_B" + }, + "GTGREFCLK0INV:GTGREFCLK0": { + "to_pin": "OUT", + "from_pin": "GTGREFCLK0" + }, + "GTGREFCLK1INV:GTGREFCLK1": { + "to_pin": "OUT", + "from_pin": "GTGREFCLK1" + }, + "PMASCANCLK1INV:PMASCANCLK1_B": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK1_B" + }, + "GTGREFCLK1INV:GTGREFCLK1_B": { + "to_pin": "OUT", + "from_pin": "GTGREFCLK1_B" + }, + "PMASCANCLK0INV:PMASCANCLK0": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK0" + }, + "PMASCANCLK1INV:PMASCANCLK1": { + "to_pin": "OUT", + "from_pin": "PMASCANCLK1" + }, + "PLL1LOCKDETCLKINV:PLL1LOCKDETCLK": { + "to_pin": "OUT", + "from_pin": "PLL1LOCKDETCLK" + } + }, + "site_pins": { "DRPDI5": { "direction": "IN" }, - "PLLRSVD20": { - "direction": "IN" - }, - "DMONITOROUT0": { + "DRPDO6": { "direction": "OUT" }, - "PLL1REFCLKSEL1": { - "direction": "IN" - }, - "DRPDI0": { - "direction": "IN" - }, - "PLL0FBCLKLOST": { + "PMARSVDOUT9": { "direction": "OUT" }, - "GTWESTREFCLK0": { + "DRPDI15": { "direction": "IN" }, - "PMASCANIN3": { - "direction": "IN" - }, - "DRPDI3": { - "direction": "IN" - }, - "PMASCANCLK0": { - "direction": "IN" - }, - "PLLRSVD113": { - "direction": "IN" - }, - "PMARSVDOUT12": { - "direction": "OUT" - }, - "PMARSVD1": { - "direction": "IN" - }, - "PLLRSVD16": { - "direction": "IN" - }, - "PLL0REFCLKSEL2": { - "direction": "IN" - }, - "PMARSVDOUT10": { - "direction": "OUT" - }, - "BGMONITORENB": { - "direction": "IN" - }, - "PLLRSVD111": { - "direction": "IN" - }, - "PLLRSVD10": { - "direction": "IN" - }, - "BGRCALOVRD3": { - "direction": "IN" - }, - "DRPADDR6": { - "direction": "IN" - }, - "PLLCLKSPARE": { - "direction": "IN" - }, - "REFCLKOUTMONITOR0": { - "direction": "OUT" - }, - "DRPDI4": { - "direction": "IN" - }, - "PMARSVD0": { - "direction": "IN" - }, - "DRPDI7": { - "direction": "IN" - }, - "DRPDI6": { - "direction": "IN" - }, - "GTREFCLK1": { - "direction": "IN" - }, - "PLLRSVD19": { - "direction": "IN" - }, - "DMONITOROUT6": { - "direction": "OUT" - }, - "PMARSVDOUT1": { - "direction": "OUT" - }, - "DMONITOROUT2": { - "direction": "OUT" - }, - "DRPDI11": { - "direction": "IN" - }, - "DRPDI12": { - "direction": "IN" - }, - "PLL0REFCLKSEL0": { - "direction": "IN" - }, - "PMARSVD7": { - "direction": "IN" - }, - "PMASCANIN1": { - "direction": "IN" - }, - "PMARSVDOUT4": { - "direction": "OUT" - }, - "PMARSVDOUT5": { - "direction": "OUT" - }, - "DRPADDR4": { - "direction": "IN" - }, - "PLLRSVD24": { - "direction": "IN" - }, - "DRPDO7": { - "direction": "OUT" - }, - "DRPDI8": { - "direction": "IN" - }, - "BGRCALOVRDENB": { - "direction": "IN" - }, - "DMONITOROUT1": { - "direction": "OUT" - }, - "DRPDI13": { - "direction": "IN" - }, - "PLLRSVD15": { - "direction": "IN" - }, - "PLLRSVD17": { - "direction": "IN" - }, - "PLL1REFCLKLOST": { - "direction": "OUT" - }, - "PLL1RESET": { - "direction": "IN" - }, - "DMONITOROUT7": { - "direction": "OUT" - }, - "PLLRSVD114": { - "direction": "IN" - }, - "DRPDO3": { - "direction": "OUT" - }, - "PMARSVDOUT7": { - "direction": "OUT" - }, "PLL0REFCLKLOST": { "direction": "OUT" }, - "PLLRSVD22": { + "DMONITOROUT6": { + "direction": "OUT" + }, + "PLL1REFCLKLOST": { + "direction": "OUT" + }, + "BGRCALOVRDENB": { "direction": "IN" }, - "PLL1OUTCLK": { + "DMONITOROUT2": { "direction": "OUT" }, - "DRPDO8": { + "DRPDO4": { "direction": "OUT" }, - "GTEASTREFCLK1": { + "PLLRSVD21": { "direction": "IN" }, - "DRPDO11": { + "PMARSVDOUT1": { "direction": "OUT" }, - "PLL1FBCLKLOST": { + "PMARSVDOUT2": { "direction": "OUT" }, "BGRCALOVRD2": { "direction": "IN" }, - "DRPRDY": { + "PMARSVDOUT0": { "direction": "OUT" }, - "DRPDO1": { - "direction": "OUT" - }, - "PMASCANCLK1": { + "BGRCALOVRD1": { "direction": "IN" }, + "QDPMASCANRSTEN": { + "direction": "IN" + }, + "DRPDI14": { + "direction": "IN" + }, + "PMARSVD1": { + "direction": "IN" + }, + "DRPDO5": { + "direction": "OUT" + }, + "PMASCANCLK0": { + "direction": "IN" + }, + "PMASCANIN4": { + "direction": "IN" + }, + "PMARSVDOUT10": { + "direction": "OUT" + }, + "DRPDI13": { + "direction": "IN" + }, + "BGPDB": { + "direction": "IN" + }, + "DRPDO12": { + "direction": "OUT" + }, "REFCLKOUTMONITOR1": { "direction": "OUT" }, - "PLL1REFCLKSEL0": { + "PMARSVD5": { "direction": "IN" }, - "DRPDI9": { + "DRPADDR6": { "direction": "IN" }, - "PMARSVDOUT15": { + "PLL1PD": { + "direction": "IN" + }, + "DRPDI4": { + "direction": "IN" + }, + "BGRCALOVRD4": { + "direction": "IN" + }, + "GTREFCLK1": { + "direction": "IN" + }, + "DRPDO14": { "direction": "OUT" }, - "PMARSVDOUT0": { + "PLL0LOCKEN": { + "direction": "IN" + }, + "PLLRSVD24": { + "direction": "IN" + }, + "DRPADDR2": { + "direction": "IN" + }, + "PMARSVDOUT13": { "direction": "OUT" }, + "PMARSVDOUT4": { + "direction": "OUT" + }, + "PLL0REFCLKSEL2": { + "direction": "IN" + }, + "PLLRSVD12": { + "direction": "IN" + }, + "PMASCANENB": { + "direction": "IN" + }, + "PLLRSVD113": { + "direction": "IN" + }, + "PMARSVDOUT7": { + "direction": "OUT" + }, + "BGBYPASSB": { + "direction": "IN" + }, + "PLL0REFCLKSEL1": { + "direction": "IN" + }, + "PLLRSVD20": { + "direction": "IN" + }, "PMARSVDOUT3": { "direction": "OUT" }, - "PLL1LOCKDETCLK": { + "DRPDO8": { + "direction": "OUT" + }, + "PMASCANOUT1": { + "direction": "OUT" + }, + "PMARSVDOUT12": { + "direction": "OUT" + }, + "PMARSVDOUT8": { + "direction": "OUT" + }, + "PMASCANOUT2": { + "direction": "OUT" + }, + "RCALENB": { + "direction": "IN" + }, + "PMARSVD0": { + "direction": "IN" + }, + "DRPDI10": { + "direction": "IN" + }, + "PLLRSVD114": { + "direction": "IN" + }, + "PLL0LOCKDETCLK": { "direction": "IN" }, "PLL1LOCK": { "direction": "OUT" }, + "DRPADDR3": { + "direction": "IN" + }, + "QDPMASCANMODEB": { + "direction": "IN" + }, + "PLL0OUTREFCLK": { + "direction": "OUT" + }, + "DRPDI0": { + "direction": "IN" + }, + "PMASCANIN1": { + "direction": "IN" + }, + "GTGREFCLK1": { + "direction": "IN" + }, + "PMARSVDOUT5": { + "direction": "OUT" + }, + "DRPDO1": { + "direction": "OUT" + }, + "BGMONITORENB": { + "direction": "IN" + }, + "PMARSVD4": { + "direction": "IN" + }, + "PLLRSVD15": { + "direction": "IN" + }, + "PLLRSVD115": { + "direction": "IN" + }, + "PMASCANOUT3": { + "direction": "OUT" + }, + "PLL1REFCLKSEL1": { + "direction": "IN" + }, + "DMONITOROUT1": { + "direction": "OUT" + }, + "PMARSVD7": { + "direction": "IN" + }, + "DRPDI3": { + "direction": "IN" + }, + "GTGREFCLK0": { + "direction": "IN" + }, + "DRPCLK": { + "direction": "IN" + }, + "PMARSVD2": { + "direction": "IN" + }, + "DMONITOROUT3": { + "direction": "OUT" + }, + "DRPDI6": { + "direction": "IN" + }, + "PLL0PD": { + "direction": "IN" + }, + "PLL0REFCLKSEL0": { + "direction": "IN" + }, + "DRPDI9": { + "direction": "IN" + }, + "DRPDI2": { + "direction": "IN" + }, + "DRPEN": { + "direction": "IN" + }, + "PLL0LOCK": { + "direction": "OUT" + }, + "PLLRSVD14": { + "direction": "IN" + }, "DRPDO9": { "direction": "OUT" }, - "DRPDO14": { + "PLLRSVD16": { + "direction": "IN" + }, + "GTEASTREFCLK0": { + "direction": "IN" + }, + "DRPDO11": { "direction": "OUT" }, - "PMARSVDOUT2": { + "PLL1OUTREFCLK": { + "direction": "OUT" + }, + "PLLCLKSPARE": { + "direction": "IN" + }, + "DRPDI11": { + "direction": "IN" + }, + "PLL1OUTCLK": { + "direction": "OUT" + }, + "DMONITOROUT7": { + "direction": "OUT" + }, + "PMARSVD3": { + "direction": "IN" + }, + "DRPADDR0": { + "direction": "IN" + }, + "DRPADDR1": { + "direction": "IN" + }, + "PLLRSVD111": { + "direction": "IN" + }, + "PLL1LOCKDETCLK": { + "direction": "IN" + }, + "PLL1LOCKEN": { + "direction": "IN" + }, + "BGRCALOVRD3": { + "direction": "IN" + }, + "PMASCANIN3": { + "direction": "IN" + }, + "DRPDI12": { + "direction": "IN" + }, + "PMARSVD6": { + "direction": "IN" + }, + "DMONITOROUT0": { "direction": "OUT" }, "PMARSVDOUT14": { @@ -237,306 +397,146 @@ "GTREFCLK0": { "direction": "IN" }, - "PLL1LOCKEN": { + "DRPDI7": { "direction": "IN" }, - "DRPDO10": { - "direction": "OUT" - }, - "GTGREFCLK0": { - "direction": "IN" - }, - "PLLRSVD23": { - "direction": "IN" - }, - "DRPDO4": { - "direction": "OUT" - }, - "PMARSVDOUT11": { - "direction": "OUT" - }, - "PLLRSVD11": { - "direction": "IN" - }, - "PMARSVDOUT9": { - "direction": "OUT" - }, - "DMONITOROUT3": { - "direction": "OUT" - }, - "RCALENB": { - "direction": "IN" - }, - "PMASCANOUT0": { - "direction": "OUT" - }, - "BGRCALOVRD4": { - "direction": "IN" - }, - "DRPDO5": { - "direction": "OUT" - }, - "PLLRSVD14": { - "direction": "IN" - }, - "DRPCLK": { - "direction": "IN" - }, - "PMARSVD5": { - "direction": "IN" - }, - "PMARSVD6": { - "direction": "IN" - }, - "DRPEN": { - "direction": "IN" - }, - "DRPADDR0": { - "direction": "IN" - }, - "DRPADDR7": { - "direction": "IN" - }, - "PMASCANIN2": { - "direction": "IN" - }, - "PMARSVDOUT13": { - "direction": "OUT" - }, - "DMONITOROUT5": { - "direction": "OUT" - }, - "QDPMASCANRSTEN": { - "direction": "IN" - }, - "DMONITOROUT4": { - "direction": "OUT" - }, - "PMASCANOUT1": { - "direction": "OUT" - }, "DRPADDR5": { "direction": "IN" }, - "DRPADDR1": { - "direction": "IN" - }, - "PLL0LOCK": { + "PMARSVDOUT11": { "direction": "OUT" }, - "BGRCALOVRD1": { + "GTEASTREFCLK1": { "direction": "IN" }, - "PMASCANIN0": { + "PLLRSVD19": { "direction": "IN" }, - "PMARSVD3": { - "direction": "IN" - }, - "DRPWE": { - "direction": "IN" - }, - "PLL1REFCLKSEL2": { - "direction": "IN" - }, - "BGBYPASSB": { - "direction": "IN" - }, - "PMARSVDOUT6": { - "direction": "OUT" - }, - "GTEASTREFCLK0": { - "direction": "IN" - }, - "PLL1OUTREFCLK": { - "direction": "OUT" - }, - "DRPDI1": { - "direction": "IN" - }, - "QDPMASCANMODEB": { - "direction": "IN" - }, - "PLLRSVD21": { - "direction": "IN" - }, - "DRPDO2": { - "direction": "OUT" - }, - "DRPDO12": { - "direction": "OUT" - }, - "PMASCANOUT4": { - "direction": "OUT" - }, - "PMASCANENB": { - "direction": "IN" - }, - "PLL0OUTREFCLK": { - "direction": "OUT" - }, - "BGPDB": { - "direction": "IN" - }, - "GTGREFCLK1": { - "direction": "IN" - }, - "PLLRSVD115": { - "direction": "IN" - }, - "DRPDI2": { - "direction": "IN" - }, - "BGRCALOVRD0": { - "direction": "IN" - }, - "DRPADDR2": { - "direction": "IN" - }, - "DRPDI10": { - "direction": "IN" - }, - "PLL0REFCLKSEL1": { - "direction": "IN" - }, - "PMARSVD4": { - "direction": "IN" - }, - "PLLRSVD12": { - "direction": "IN" - }, - "DRPDI14": { - "direction": "IN" - }, - "PLL1PD": { - "direction": "IN" - }, - "PMASCANIN4": { - "direction": "IN" - }, - "DRPDO0": { - "direction": "OUT" - }, - "PLL0PD": { - "direction": "IN" - }, - "PMARSVD2": { - "direction": "IN" - }, - "PLL0LOCKDETCLK": { - "direction": "IN" - }, - "PMASCANOUT3": { - "direction": "OUT" - }, - "PMARSVDOUT8": { - "direction": "OUT" - }, - "DRPDO15": { - "direction": "OUT" - }, - "GTWESTREFCLK1": { - "direction": "IN" - }, - "DRPDI15": { - "direction": "IN" - }, - "PLL0LOCKEN": { - "direction": "IN" - }, - "DRPADDR3": { - "direction": "IN" - }, - "PMASCANOUT2": { - "direction": "OUT" - }, "PLLRSVD13": { "direction": "IN" }, - "DRPDO6": { - "direction": "OUT" - }, - "DRPDO13": { - "direction": "OUT" - }, - "PLLRSVD112": { - "direction": "IN" - }, - "PLLRSVD110": { - "direction": "IN" - }, "PLL0RESET": { "direction": "IN" }, + "BGRCALOVRD0": { + "direction": "IN" + }, + "PLLRSVD23": { + "direction": "IN" + }, + "PLL0OUTCLK": { + "direction": "OUT" + }, + "DRPADDR4": { + "direction": "IN" + }, + "PLL1REFCLKSEL0": { + "direction": "IN" + }, + "PMARSVDOUT15": { + "direction": "OUT" + }, + "PMASCANIN2": { + "direction": "IN" + }, + "DRPWE": { + "direction": "IN" + }, + "PLL1RESET": { + "direction": "IN" + }, + "PLLRSVD17": { + "direction": "IN" + }, + "DRPDI8": { + "direction": "IN" + }, + "DRPDO7": { + "direction": "OUT" + }, + "PLL1REFCLKSEL2": { + "direction": "IN" + }, + "DRPDO3": { + "direction": "OUT" + }, + "GTWESTREFCLK1": { + "direction": "IN" + }, + "DRPDO2": { + "direction": "OUT" + }, + "DRPDO13": { + "direction": "OUT" + }, "PLLRSVD18": { "direction": "IN" - } - }, - "type": "GTPE2_COMMON", - "site_pips": { - "PMASCANCLK0INV:PMASCANCLK0_B": { - "from_pin": "PMASCANCLK0_B", - "to_pin": "OUT" }, - "PLL0LOCKDETCLKINV:PLL0LOCKDETCLK_B": { - "from_pin": "PLL0LOCKDETCLK_B", - "to_pin": "OUT" + "DRPDI1": { + "direction": "IN" }, - "PMASCANCLK0INV:PMASCANCLK0": { - "from_pin": "PMASCANCLK0", - "to_pin": "OUT" + "DMONITOROUT4": { + "direction": "OUT" }, - "GTGREFCLK1INV:GTGREFCLK1_B": { - "from_pin": "GTGREFCLK1_B", - "to_pin": "OUT" + "PMASCANOUT4": { + "direction": "OUT" }, - "PLL1LOCKDETCLKINV:PLL1LOCKDETCLK_B": { - "from_pin": "PLL1LOCKDETCLK_B", - "to_pin": "OUT" + "PLL1FBCLKLOST": { + "direction": "OUT" }, - "PLLCLKSPAREINV:PLLCLKSPARE_B": { - "from_pin": "PLLCLKSPARE_B", - "to_pin": "OUT" + "DRPDO0": { + "direction": "OUT" }, - "DRPCLKINV:DRPCLK": { - "from_pin": "DRPCLK", - "to_pin": "OUT" + "DRPRDY": { + "direction": "OUT" }, - "PMASCANCLK1INV:PMASCANCLK1": { - "from_pin": "PMASCANCLK1", - "to_pin": "OUT" + "PMARSVDOUT6": { + "direction": "OUT" }, - "DRPCLKINV:DRPCLK_B": { - "from_pin": "DRPCLK_B", - "to_pin": "OUT" + "PMASCANIN0": { + "direction": "IN" }, - "PLL1LOCKDETCLKINV:PLL1LOCKDETCLK": { - "from_pin": "PLL1LOCKDETCLK", - "to_pin": "OUT" + "PLLRSVD110": { + "direction": "IN" }, - "GTGREFCLK0INV:GTGREFCLK0_B": { - "from_pin": "GTGREFCLK0_B", - "to_pin": "OUT" + "REFCLKOUTMONITOR0": { + "direction": "OUT" }, - "PLLCLKSPAREINV:PLLCLKSPARE": { - "from_pin": "PLLCLKSPARE", - "to_pin": "OUT" + "DMONITOROUT5": { + "direction": "OUT" }, - "GTGREFCLK1INV:GTGREFCLK1": { - "from_pin": "GTGREFCLK1", - "to_pin": "OUT" + "PMASCANCLK1": { + "direction": "IN" }, - "PLL0LOCKDETCLKINV:PLL0LOCKDETCLK": { - "from_pin": "PLL0LOCKDETCLK", - "to_pin": "OUT" + "PLLRSVD10": { + "direction": "IN" }, - "PMASCANCLK1INV:PMASCANCLK1_B": { - "from_pin": "PMASCANCLK1_B", - "to_pin": "OUT" + "GTWESTREFCLK0": { + "direction": "IN" }, - "GTGREFCLK0INV:GTGREFCLK0": { - "from_pin": "GTGREFCLK0", - "to_pin": "OUT" + "PLLRSVD11": { + "direction": "IN" + }, + "DRPDO10": { + "direction": "OUT" + }, + "DRPADDR7": { + "direction": "IN" + }, + "PLL0FBCLKLOST": { + "direction": "OUT" + }, + "PLLRSVD22": { + "direction": "IN" + }, + "PMASCANOUT0": { + "direction": "OUT" + }, + "DRPDO15": { + "direction": "OUT" + }, + "PLLRSVD112": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_IBUFDS_GTE2.json b/artix7/site_type_IBUFDS_GTE2.json index c21d052..44b5ed1 100644 --- a/artix7/site_type_IBUFDS_GTE2.json +++ b/artix7/site_type_IBUFDS_GTE2.json @@ -1,33 +1,33 @@ { + "type": "IBUFDS_GTE2", + "site_pips": { + "CLKTESTSIGINV:CLKTESTSIG_B": { + "to_pin": "OUT", + "from_pin": "CLKTESTSIG_B" + }, + "CLKTESTSIGINV:CLKTESTSIG": { + "to_pin": "OUT", + "from_pin": "CLKTESTSIG" + } + }, "site_pins": { "O": { "direction": "OUT" }, - "CEB": { - "direction": "IN" - }, - "I": { + "IB": { "direction": "IN" }, "CLKTESTSIG": { "direction": "IN" }, - "IB": { + "I": { + "direction": "IN" + }, + "CEB": { "direction": "IN" }, "ODIV2": { "direction": "OUT" } - }, - "type": "IBUFDS_GTE2", - "site_pips": { - "CLKTESTSIGINV:CLKTESTSIG": { - "from_pin": "CLKTESTSIG", - "to_pin": "OUT" - }, - "CLKTESTSIGINV:CLKTESTSIG_B": { - "from_pin": "CLKTESTSIG_B", - "to_pin": "OUT" - } } } \ No newline at end of file diff --git a/artix7/site_type_ICAP.json b/artix7/site_type_ICAP.json index 011f0b9..149cf56 100644 --- a/artix7/site_type_ICAP.json +++ b/artix7/site_type_ICAP.json @@ -1,123 +1,149 @@ { + "type": "ICAP", + "site_pips": {}, "site_pins": { - "O10": { - "direction": "OUT" - }, - "I1": { - "direction": "IN" - }, - "O31": { - "direction": "OUT" - }, - "I6": { - "direction": "IN" - }, - "O7": { - "direction": "OUT" - }, - "I17": { - "direction": "IN" - }, - "O25": { - "direction": "OUT" - }, - "CLK": { - "direction": "IN" - }, - "I5": { - "direction": "IN" - }, - "I21": { - "direction": "IN" - }, - "I26": { - "direction": "IN" - }, - "I4": { - "direction": "IN" - }, - "O4": { - "direction": "OUT" - }, - "I30": { - "direction": "IN" - }, - "I9": { - "direction": "IN" - }, - "O1": { - "direction": "OUT" - }, - "I16": { - "direction": "IN" - }, - "I18": { - "direction": "IN" - }, - "I7": { - "direction": "IN" - }, - "O27": { - "direction": "OUT" - }, - "O17": { - "direction": "OUT" - }, - "I8": { - "direction": "IN" - }, - "I19": { - "direction": "IN" - }, - "O11": { - "direction": "OUT" - }, - "I23": { - "direction": "IN" - }, - "I28": { - "direction": "IN" - }, - "RDWRB": { - "direction": "IN" - }, - "O2": { - "direction": "OUT" - }, - "O18": { - "direction": "OUT" - }, - "I2": { - "direction": "IN" - }, - "O0": { - "direction": "OUT" - }, - "I13": { - "direction": "IN" - }, - "I31": { - "direction": "IN" - }, - "O8": { - "direction": "OUT" - }, - "I10": { + "CSIB": { "direction": "IN" }, "I0": { "direction": "IN" }, - "O19": { + "O26": { + "direction": "OUT" + }, + "O4": { + "direction": "OUT" + }, + "I3": { + "direction": "IN" + }, + "I22": { + "direction": "IN" + }, + "O16": { + "direction": "OUT" + }, + "I24": { + "direction": "IN" + }, + "O9": { + "direction": "OUT" + }, + "I11": { + "direction": "IN" + }, + "O7": { + "direction": "OUT" + }, + "O3": { "direction": "OUT" }, "O13": { "direction": "OUT" }, + "O23": { + "direction": "OUT" + }, + "O6": { + "direction": "OUT" + }, + "O10": { + "direction": "OUT" + }, + "O11": { + "direction": "OUT" + }, + "RDWRB": { + "direction": "IN" + }, + "I28": { + "direction": "IN" + }, + "I8": { + "direction": "IN" + }, + "O27": { + "direction": "OUT" + }, + "I9": { + "direction": "IN" + }, + "I7": { + "direction": "IN" + }, + "O8": { + "direction": "OUT" + }, + "I12": { + "direction": "IN" + }, + "I29": { + "direction": "IN" + }, "O24": { "direction": "OUT" }, - "O23": { + "O31": { + "direction": "OUT" + }, + "O30": { + "direction": "OUT" + }, + "I21": { + "direction": "IN" + }, + "I20": { + "direction": "IN" + }, + "I31": { + "direction": "IN" + }, + "I30": { + "direction": "IN" + }, + "I1": { + "direction": "IN" + }, + "I23": { + "direction": "IN" + }, + "I26": { + "direction": "IN" + }, + "O1": { + "direction": "OUT" + }, + "O0": { + "direction": "OUT" + }, + "O12": { + "direction": "OUT" + }, + "O5": { + "direction": "OUT" + }, + "O29": { + "direction": "OUT" + }, + "O2": { + "direction": "OUT" + }, + "I19": { + "direction": "IN" + }, + "O25": { + "direction": "OUT" + }, + "I6": { + "direction": "IN" + }, + "I10": { + "direction": "IN" + }, + "O21": { + "direction": "OUT" + }, + "O18": { "direction": "OUT" }, "I15": { @@ -126,82 +152,56 @@ "O20": { "direction": "OUT" }, - "I27": { + "O17": { + "direction": "OUT" + }, + "I18": { "direction": "IN" }, - "O9": { - "direction": "OUT" - }, - "I29": { - "direction": "IN" - }, - "O12": { - "direction": "OUT" - }, - "O14": { - "direction": "OUT" - }, - "I24": { - "direction": "IN" - }, - "O6": { - "direction": "OUT" - }, - "O22": { - "direction": "OUT" - }, - "O5": { - "direction": "OUT" - }, - "I22": { + "I2": { "direction": "IN" }, "O28": { "direction": "OUT" }, - "O21": { - "direction": "OUT" - }, - "O29": { - "direction": "OUT" - }, - "I20": { + "I17": { "direction": "IN" }, - "I12": { + "I5": { "direction": "IN" }, - "O15": { + "O22": { "direction": "OUT" }, - "O26": { - "direction": "OUT" - }, - "I14": { + "I13": { "direction": "IN" }, - "O16": { + "O14": { "direction": "OUT" }, - "O30": { - "direction": "OUT" - }, - "O3": { - "direction": "OUT" - }, - "CSIB": { + "I4": { "direction": "IN" }, "I25": { "direction": "IN" }, - "I11": { + "I16": { "direction": "IN" }, - "I3": { + "O15": { + "direction": "OUT" + }, + "O19": { + "direction": "OUT" + }, + "I27": { + "direction": "IN" + }, + "I14": { + "direction": "IN" + }, + "CLK": { "direction": "IN" } - }, - "type": "ICAP", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_IDELAYCTRL.json b/artix7/site_type_IDELAYCTRL.json index e1205a6..3a9e47e 100644 --- a/artix7/site_type_IDELAYCTRL.json +++ b/artix7/site_type_IDELAYCTRL.json @@ -1,13 +1,15 @@ { + "type": "IDELAYCTRL", + "site_pips": {}, "site_pins": { "UPPULSEOUT": { "direction": "OUT" }, - "OUTN65": { - "direction": "OUT" + "RST": { + "direction": "IN" }, - "OUTN1": { - "direction": "OUT" + "REFCLK": { + "direction": "IN" }, "DNPULSEOUT": { "direction": "OUT" @@ -15,13 +17,11 @@ "RDY": { "direction": "OUT" }, - "REFCLK": { - "direction": "IN" + "OUTN1": { + "direction": "OUT" }, - "RST": { - "direction": "IN" + "OUTN65": { + "direction": "OUT" } - }, - "type": "IDELAYCTRL", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_IDELAYE2.json b/artix7/site_type_IDELAYE2.json index 79edf68..0c63098 100644 --- a/artix7/site_type_IDELAYE2.json +++ b/artix7/site_type_IDELAYE2.json @@ -1,21 +1,48 @@ { + "type": "IDELAYE2", + "site_pips": { + "CINV:C_B": { + "to_pin": "OUT", + "from_pin": "C_B" + }, + "IDATAININV:IDATAIN_B": { + "to_pin": "OUT", + "from_pin": "IDATAIN_B" + }, + "DATAININV:DATAIN": { + "to_pin": "OUT", + "from_pin": "DATAIN" + }, + "IDATAININV:IDATAIN": { + "to_pin": "OUT", + "from_pin": "IDATAIN" + }, + "CINV:C": { + "to_pin": "OUT", + "from_pin": "C" + }, + "DATAININV:DATAIN_B": { + "to_pin": "OUT", + "from_pin": "DATAIN_B" + } + }, "site_pins": { - "CE": { + "LDPIPEEN": { "direction": "IN" }, - "CNTVALUEIN3": { + "CNTVALUEIN4": { "direction": "IN" }, - "CINVCTRL": { + "IDATAIN": { "direction": "IN" }, - "LD": { - "direction": "IN" + "CNTVALUEOUT0": { + "direction": "OUT" }, "DATAOUT": { "direction": "OUT" }, - "IFDLY0": { + "CNTVALUEIN3": { "direction": "IN" }, "REGRST": { @@ -24,77 +51,50 @@ "IFDLY1": { "direction": "IN" }, - "CNTVALUEOUT0": { + "CNTVALUEOUT2": { "direction": "OUT" }, - "IDATAIN": { - "direction": "IN" - }, - "CNTVALUEIN0": { + "CINVCTRL": { "direction": "IN" }, "INC": { "direction": "IN" }, - "CNTVALUEOUT1": { - "direction": "OUT" - }, - "CNTVALUEOUT3": { - "direction": "OUT" - }, - "C": { - "direction": "IN" - }, - "IFDLY2": { - "direction": "IN" - }, - "DATAIN": { - "direction": "IN" - }, - "LDPIPEEN": { + "CE": { "direction": "IN" }, "CNTVALUEIN1": { "direction": "IN" }, - "CNTVALUEIN4": { + "LD": { + "direction": "IN" + }, + "CNTVALUEOUT4": { + "direction": "OUT" + }, + "CNTVALUEOUT3": { + "direction": "OUT" + }, + "DATAIN": { "direction": "IN" }, "CNTVALUEIN2": { "direction": "IN" }, - "CNTVALUEOUT2": { + "C": { + "direction": "IN" + }, + "CNTVALUEOUT1": { "direction": "OUT" }, - "CNTVALUEOUT4": { - "direction": "OUT" - } - }, - "type": "IDELAYE2", - "site_pips": { - "DATAININV:DATAIN_B": { - "from_pin": "DATAIN_B", - "to_pin": "OUT" + "CNTVALUEIN0": { + "direction": "IN" }, - "IDATAININV:IDATAIN_B": { - "from_pin": "IDATAIN_B", - "to_pin": "OUT" + "IFDLY0": { + "direction": "IN" }, - "DATAININV:DATAIN": { - "from_pin": "DATAIN", - "to_pin": "OUT" - }, - "IDATAININV:IDATAIN": { - "from_pin": "IDATAIN", - "to_pin": "OUT" - }, - "CINV:C": { - "from_pin": "C", - "to_pin": "OUT" - }, - "CINV:C_B": { - "from_pin": "C_B", - "to_pin": "OUT" + "IFDLY2": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_ILOGICE3.json b/artix7/site_type_ILOGICE3.json index 5aec317..ad25ddb 100644 --- a/artix7/site_type_ILOGICE3.json +++ b/artix7/site_type_ILOGICE3.json @@ -1,208 +1,208 @@ { + "type": "ILOGICE3", + "site_pips": { + "CLKBINV:CLKB_B": { + "to_pin": "OUT", + "from_pin": "CLKB_B" + }, + "CLKINV:CLK": { + "to_pin": "OUT", + "from_pin": "CLK" + }, + "ZHOLD_IFF_INV:D": { + "to_pin": "OUT", + "from_pin": "D" + }, + "ZHOLD_FABRIC_INV:D_B": { + "to_pin": "OUT", + "from_pin": "D_B" + }, + "D2OBYP_SEL:T": { + "to_pin": "OUT", + "from_pin": "T" + }, + "CLKINV:CLK_B": { + "to_pin": "OUT", + "from_pin": "CLK_B" + }, + "IDELMUXE3:2": { + "to_pin": "OUT", + "from_pin": "2" + }, + "IFFMUX:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "D2OFFBYP_SEL:T": { + "to_pin": "OUT", + "from_pin": "T" + }, + "IFFMUX:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "CLKBINV:CLKB": { + "to_pin": "OUT", + "from_pin": "CLKB" + }, + "IMUX:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "D2OFFBYP_SEL:GND": { + "to_pin": "OUT", + "from_pin": "GND" + }, + "IFFDELMUXE3:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "DINV:D_B": { + "to_pin": "OUT", + "from_pin": "D_B" + }, + "IMUX:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "IFFDELMUXE3:2": { + "to_pin": "OUT", + "from_pin": "2" + }, + "ZHOLD_IFF_INV:D_B": { + "to_pin": "OUT", + "from_pin": "D_B" + }, + "CE1USED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IDELMUXE3:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "DINV:D": { + "to_pin": "OUT", + "from_pin": "D" + }, + "ZHOLD_FABRIC_INV:D": { + "to_pin": "OUT", + "from_pin": "D" + }, + "IFFDELMUXE3:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "REVUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "SRUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IDELMUXE3:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "D2OBYP_SEL:GND": { + "to_pin": "OUT", + "from_pin": "GND" + } + }, "site_pins": { - "REV": { - "direction": "IN" - }, - "CLKDIVP": { - "direction": "IN" - }, - "SHIFTIN2": { - "direction": "IN" - }, - "OCLKB": { - "direction": "IN" - }, - "CE2": { - "direction": "IN" - }, - "OCLK": { - "direction": "IN" - }, - "D": { - "direction": "IN" - }, - "DDLY": { - "direction": "IN" - }, - "DYNCLKSEL": { - "direction": "IN" - }, - "CLK": { - "direction": "IN" - }, - "DYNCLKDIVSEL": { - "direction": "IN" - }, - "O": { - "direction": "OUT" - }, - "Q1": { - "direction": "OUT" - }, - "Q5": { - "direction": "OUT" - }, - "SR": { - "direction": "IN" - }, "Q8": { "direction": "OUT" }, - "CLKDIV": { - "direction": "IN" - }, - "TFB": { - "direction": "IN" - }, "CE1": { "direction": "IN" }, - "SHIFTOUT2": { - "direction": "OUT" - }, - "Q3": { - "direction": "OUT" - }, "Q4": { "direction": "OUT" }, - "SHIFTOUT1": { - "direction": "OUT" - }, "Q2": { "direction": "OUT" }, + "Q3": { + "direction": "OUT" + }, + "OCLKB": { + "direction": "IN" + }, + "CLKDIVP": { + "direction": "IN" + }, "CLKB": { "direction": "IN" }, - "Q6": { + "BITSLIP": { + "direction": "IN" + }, + "DYNCLKSEL": { + "direction": "IN" + }, + "O": { "direction": "OUT" }, - "DYNCLKDIVPSEL": { + "REV": { "direction": "IN" }, "Q7": { "direction": "OUT" }, + "DYNCLKDIVSEL": { + "direction": "IN" + }, + "D": { + "direction": "IN" + }, "SHIFTIN1": { "direction": "IN" }, + "SHIFTOUT1": { + "direction": "OUT" + }, + "TFB": { + "direction": "IN" + }, + "Q5": { + "direction": "OUT" + }, + "OCLK": { + "direction": "IN" + }, + "Q6": { + "direction": "OUT" + }, + "SHIFTOUT2": { + "direction": "OUT" + }, "OFB": { "direction": "IN" }, - "BITSLIP": { + "Q1": { + "direction": "OUT" + }, + "SHIFTIN2": { "direction": "IN" - } - }, - "type": "ILOGICE3", - "site_pips": { - "IDELMUXE3:2": { - "from_pin": "2", - "to_pin": "OUT" }, - "IFFDELMUXE3:0": { - "from_pin": "0", - "to_pin": "OUT" + "SR": { + "direction": "IN" }, - "IMUX:1": { - "from_pin": "1", - "to_pin": "OUT" + "CE2": { + "direction": "IN" }, - "ZHOLD_IFF_INV:D_B": { - "from_pin": "D_B", - "to_pin": "OUT" + "DYNCLKDIVPSEL": { + "direction": "IN" }, - "D2OFFBYP_SEL:T": { - "from_pin": "T", - "to_pin": "OUT" + "DDLY": { + "direction": "IN" }, - "IFFDELMUXE3:2": { - "from_pin": "2", - "to_pin": "OUT" + "CLK": { + "direction": "IN" }, - "ZHOLD_FABRIC_INV:D_B": { - "from_pin": "D_B", - "to_pin": "OUT" - }, - "IFFDELMUXE3:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "IFFMUX:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "ZHOLD_IFF_INV:D": { - "from_pin": "D", - "to_pin": "OUT" - }, - "CLKBINV:CLKB": { - "from_pin": "CLKB", - "to_pin": "OUT" - }, - "ZHOLD_FABRIC_INV:D": { - "from_pin": "D", - "to_pin": "OUT" - }, - "D2OFFBYP_SEL:GND": { - "from_pin": "GND", - "to_pin": "OUT" - }, - "D2OBYP_SEL:T": { - "from_pin": "T", - "to_pin": "OUT" - }, - "REVUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "DINV:D_B": { - "from_pin": "D_B", - "to_pin": "OUT" - }, - "IFFMUX:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "IMUX:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "CLKBINV:CLKB_B": { - "from_pin": "CLKB_B", - "to_pin": "OUT" - }, - "DINV:D": { - "from_pin": "D", - "to_pin": "OUT" - }, - "IDELMUXE3:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "SRUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "D2OBYP_SEL:GND": { - "from_pin": "GND", - "to_pin": "OUT" - }, - "CLKINV:CLK_B": { - "from_pin": "CLK_B", - "to_pin": "OUT" - }, - "CLKINV:CLK": { - "from_pin": "CLK", - "to_pin": "OUT" - }, - "CE1USED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "IDELMUXE3:0": { - "from_pin": "0", - "to_pin": "OUT" + "CLKDIV": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_IN_FIFO.json b/artix7/site_type_IN_FIFO.json index 9881841..58a05d5 100644 --- a/artix7/site_type_IN_FIFO.json +++ b/artix7/site_type_IN_FIFO.json @@ -1,402 +1,230 @@ { + "type": "IN_FIFO", + "site_pips": {}, "site_pins": { - "Q57": { - "direction": "OUT" - }, - "Q90": { - "direction": "OUT" - }, - "Q26": { - "direction": "OUT" - }, - "Q75": { - "direction": "OUT" - }, - "Q15": { - "direction": "OUT" - }, - "Q61": { - "direction": "OUT" - }, - "ALMOSTEMPTY": { - "direction": "OUT" - }, - "Q34": { - "direction": "OUT" - }, - "Q50": { - "direction": "OUT" - }, - "Q07": { - "direction": "OUT" - }, - "D22": { + "SCANIN2": { "direction": "IN" }, - "Q95": { - "direction": "OUT" - }, - "Q65": { - "direction": "OUT" - }, - "Q93": { - "direction": "OUT" - }, - "Q40": { - "direction": "OUT" - }, - "EMPTY": { - "direction": "OUT" - }, - "D13": { - "direction": "IN" - }, - "D54": { - "direction": "IN" - }, - "D64": { - "direction": "IN" - }, - "Q66": { - "direction": "OUT" - }, - "D01": { - "direction": "IN" - }, - "Q27": { - "direction": "OUT" - }, - "D65": { - "direction": "IN" - }, - "D52": { - "direction": "IN" - }, - "D41": { - "direction": "IN" - }, - "Q43": { - "direction": "OUT" - }, - "Q32": { - "direction": "OUT" - }, - "Q20": { - "direction": "OUT" - }, - "D93": { - "direction": "IN" - }, - "D51": { - "direction": "IN" - }, - "Q80": { - "direction": "OUT" - }, - "Q56": { - "direction": "OUT" - }, - "D92": { - "direction": "IN" - }, - "Q11": { - "direction": "OUT" - }, - "Q53": { - "direction": "OUT" - }, - "D82": { - "direction": "IN" - }, - "D00": { - "direction": "IN" - }, - "SCANOUT0": { - "direction": "OUT" - }, - "Q73": { - "direction": "OUT" - }, - "TESTMODEB": { - "direction": "IN" - }, - "RESET": { - "direction": "IN" - }, - "Q25": { - "direction": "OUT" - }, - "D81": { - "direction": "IN" - }, - "FULL": { - "direction": "OUT" - }, - "Q60": { - "direction": "OUT" - }, - "D42": { - "direction": "IN" - }, - "D20": { - "direction": "IN" - }, - "Q47": { - "direction": "OUT" - }, - "D80": { - "direction": "IN" - }, - "D66": { - "direction": "IN" - }, - "Q62": { - "direction": "OUT" - }, - "Q14": { - "direction": "OUT" - }, - "Q63": { - "direction": "OUT" - }, - "D30": { - "direction": "IN" - }, - "Q84": { - "direction": "OUT" - }, - "Q76": { - "direction": "OUT" - }, - "Q74": { - "direction": "OUT" - }, - "Q16": { - "direction": "OUT" - }, - "D55": { - "direction": "IN" - }, - "Q77": { - "direction": "OUT" - }, - "D62": { - "direction": "IN" - }, - "Q55": { - "direction": "OUT" - }, - "Q05": { - "direction": "OUT" - }, - "RDCLK": { - "direction": "IN" - }, - "Q46": { - "direction": "OUT" - }, - "Q23": { - "direction": "OUT" - }, - "Q82": { - "direction": "OUT" - }, - "Q12": { - "direction": "OUT" - }, - "Q30": { - "direction": "OUT" - }, - "D32": { - "direction": "IN" - }, - "D56": { - "direction": "IN" - }, - "Q87": { - "direction": "OUT" - }, - "D03": { - "direction": "IN" - }, - "Q33": { - "direction": "OUT" - }, - "Q42": { - "direction": "OUT" - }, - "D60": { - "direction": "IN" - }, - "D31": { - "direction": "IN" - }, - "ALMOSTFULL": { - "direction": "OUT" - }, - "Q17": { - "direction": "OUT" - }, - "Q44": { - "direction": "OUT" - }, - "Q01": { - "direction": "OUT" - }, - "SCANIN1": { - "direction": "IN" - }, - "D71": { - "direction": "IN" - }, - "Q36": { - "direction": "OUT" - }, - "Q85": { - "direction": "OUT" - }, - "Q97": { - "direction": "OUT" - }, - "Q94": { - "direction": "OUT" - }, - "D67": { - "direction": "IN" - }, - "Q35": { - "direction": "OUT" - }, - "D02": { - "direction": "IN" - }, - "Q06": { - "direction": "OUT" - }, - "Q24": { - "direction": "OUT" - }, - "Q54": { - "direction": "OUT" - }, - "D72": { - "direction": "IN" - }, - "Q51": { - "direction": "OUT" - }, - "Q03": { - "direction": "OUT" - }, - "Q45": { - "direction": "OUT" - }, - "Q92": { - "direction": "OUT" - }, - "SCANOUT1": { + "Q83": { "direction": "OUT" }, "Q67": { "direction": "OUT" }, - "D50": { + "D31": { "direction": "IN" }, - "Q86": { + "Q62": { "direction": "OUT" }, - "Q96": { - "direction": "OUT" - }, - "D83": { + "D12": { "direction": "IN" }, - "Q41": { - "direction": "OUT" - }, - "SCANOUT3": { - "direction": "OUT" - }, - "D23": { + "D67": { "direction": "IN" }, - "D73": { + "Q14": { + "direction": "OUT" + }, + "D81": { + "direction": "IN" + }, + "Q21": { + "direction": "OUT" + }, + "ALMOSTEMPTY": { + "direction": "OUT" + }, + "D13": { + "direction": "IN" + }, + "D72": { + "direction": "IN" + }, + "D61": { "direction": "IN" }, "Q81": { "direction": "OUT" }, - "Q21": { + "D22": { + "direction": "IN" + }, + "Q71": { "direction": "OUT" }, - "Q83": { + "Q05": { "direction": "OUT" }, - "D61": { - "direction": "IN" - }, - "D21": { - "direction": "IN" - }, - "Q00": { - "direction": "OUT" - }, - "SCANOUT2": { - "direction": "OUT" - }, - "D91": { - "direction": "IN" - }, - "D10": { - "direction": "IN" - }, - "D43": { - "direction": "IN" - }, - "Q70": { - "direction": "OUT" - }, - "D57": { - "direction": "IN" - }, - "Q10": { + "Q32": { "direction": "OUT" }, "TESTREADDISB": { "direction": "IN" }, - "TESTWRITEDISB": { - "direction": "IN" - }, - "Q52": { + "Q10": { "direction": "OUT" }, - "RDEN": { + "D20": { "direction": "IN" }, - "WREN": { + "Q70": { + "direction": "OUT" + }, + "SCANIN1": { "direction": "IN" }, - "Q02": { + "SCANENB": { + "direction": "IN" + }, + "D02": { + "direction": "IN" + }, + "D80": { + "direction": "IN" + }, + "ALMOSTFULL": { "direction": "OUT" }, - "Q37": { + "Q84": { "direction": "OUT" }, - "Q71": { + "D73": { + "direction": "IN" + }, + "Q43": { + "direction": "OUT" + }, + "Q55": { + "direction": "OUT" + }, + "Q13": { + "direction": "OUT" + }, + "SCANOUT1": { "direction": "OUT" }, "Q22": { "direction": "OUT" }, + "SCANOUT2": { + "direction": "OUT" + }, + "TESTMODEB": { + "direction": "IN" + }, + "D66": { + "direction": "IN" + }, + "Q65": { + "direction": "OUT" + }, + "Q47": { + "direction": "OUT" + }, + "FULL": { + "direction": "OUT" + }, + "Q15": { + "direction": "OUT" + }, + "Q30": { + "direction": "OUT" + }, + "D21": { + "direction": "IN" + }, + "D92": { + "direction": "IN" + }, + "Q04": { + "direction": "OUT" + }, + "Q51": { + "direction": "OUT" + }, + "D53": { + "direction": "IN" + }, + "Q56": { + "direction": "OUT" + }, + "Q90": { + "direction": "OUT" + }, + "Q96": { + "direction": "OUT" + }, + "D65": { + "direction": "IN" + }, + "RDCLK": { + "direction": "IN" + }, + "Q92": { + "direction": "OUT" + }, + "D32": { + "direction": "IN" + }, + "D60": { + "direction": "IN" + }, + "Q27": { + "direction": "OUT" + }, + "Q02": { + "direction": "OUT" + }, + "Q64": { + "direction": "OUT" + }, + "Q20": { + "direction": "OUT" + }, "D90": { "direction": "IN" }, - "D40": { + "Q00": { + "direction": "OUT" + }, + "Q87": { + "direction": "OUT" + }, + "D42": { "direction": "IN" }, - "Q31": { + "WREN": { + "direction": "IN" + }, + "D51": { + "direction": "IN" + }, + "D10": { + "direction": "IN" + }, + "Q91": { + "direction": "OUT" + }, + "Q61": { + "direction": "OUT" + }, + "D01": { + "direction": "IN" + }, + "D71": { + "direction": "IN" + }, + "Q16": { + "direction": "OUT" + }, + "Q57": { + "direction": "OUT" + }, + "Q74": { + "direction": "OUT" + }, + "Q34": { "direction": "OUT" }, "SCANIN0": { @@ -405,49 +233,221 @@ "D70": { "direction": "IN" }, - "Q13": { + "Q66": { "direction": "OUT" }, - "SCANIN3": { + "Q42": { + "direction": "OUT" + }, + "Q11": { + "direction": "OUT" + }, + "D91": { "direction": "IN" }, - "D12": { - "direction": "IN" - }, - "Q64": { + "Q80": { "direction": "OUT" }, "WRCLK": { "direction": "IN" }, - "D53": { + "Q82": { + "direction": "OUT" + }, + "D03": { "direction": "IN" }, + "Q26": { + "direction": "OUT" + }, + "SCANIN3": { + "direction": "IN" + }, + "Q97": { + "direction": "OUT" + }, + "Q06": { + "direction": "OUT" + }, + "Q01": { + "direction": "OUT" + }, + "D56": { + "direction": "IN" + }, + "Q41": { + "direction": "OUT" + }, + "Q73": { + "direction": "OUT" + }, + "RESET": { + "direction": "IN" + }, + "SCANOUT0": { + "direction": "OUT" + }, + "Q50": { + "direction": "OUT" + }, + "D43": { + "direction": "IN" + }, + "Q95": { + "direction": "OUT" + }, + "Q25": { + "direction": "OUT" + }, "D11": { "direction": "IN" }, + "D54": { + "direction": "IN" + }, + "Q86": { + "direction": "OUT" + }, + "D55": { + "direction": "IN" + }, + "Q53": { + "direction": "OUT" + }, + "Q45": { + "direction": "OUT" + }, + "D93": { + "direction": "IN" + }, + "TESTWRITEDISB": { + "direction": "IN" + }, + "Q63": { + "direction": "OUT" + }, + "Q03": { + "direction": "OUT" + }, + "Q54": { + "direction": "OUT" + }, + "Q94": { + "direction": "OUT" + }, + "D00": { + "direction": "IN" + }, + "Q33": { + "direction": "OUT" + }, + "D30": { + "direction": "IN" + }, + "Q46": { + "direction": "OUT" + }, + "D63": { + "direction": "IN" + }, + "RDEN": { + "direction": "IN" + }, + "EMPTY": { + "direction": "OUT" + }, + "Q07": { + "direction": "OUT" + }, + "D64": { + "direction": "IN" + }, + "Q52": { + "direction": "OUT" + }, + "Q85": { + "direction": "OUT" + }, + "D50": { + "direction": "IN" + }, + "Q44": { + "direction": "OUT" + }, + "D52": { + "direction": "IN" + }, + "Q60": { + "direction": "OUT" + }, + "Q12": { + "direction": "OUT" + }, + "Q93": { + "direction": "OUT" + }, "D33": { "direction": "IN" }, - "SCANENB": { + "Q31": { + "direction": "OUT" + }, + "Q23": { + "direction": "OUT" + }, + "Q76": { + "direction": "OUT" + }, + "D82": { "direction": "IN" }, - "Q04": { + "Q75": { + "direction": "OUT" + }, + "Q35": { + "direction": "OUT" + }, + "Q24": { + "direction": "OUT" + }, + "D57": { + "direction": "IN" + }, + "Q77": { + "direction": "OUT" + }, + "D40": { + "direction": "IN" + }, + "Q40": { + "direction": "OUT" + }, + "Q36": { "direction": "OUT" }, "Q72": { "direction": "OUT" }, - "SCANIN2": { - "direction": "IN" - }, - "D63": { - "direction": "IN" - }, - "Q91": { + "Q37": { "direction": "OUT" + }, + "D62": { + "direction": "IN" + }, + "SCANOUT3": { + "direction": "OUT" + }, + "Q17": { + "direction": "OUT" + }, + "D83": { + "direction": "IN" + }, + "D23": { + "direction": "IN" + }, + "D41": { + "direction": "IN" } - }, - "type": "IN_FIFO", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_IOB33.json b/artix7/site_type_IOB33.json index 1f7206d..e69cce8 100644 --- a/artix7/site_type_IOB33.json +++ b/artix7/site_type_IOB33.json @@ -1,94 +1,94 @@ { + "type": "IOB33", + "site_pips": { + "PADOUTUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IBUFDISABLE_SEL:GND": { + "to_pin": "OUT", + "from_pin": "GND" + }, + "DIFFI_INUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IBUFDISABLE_SEL:I": { + "to_pin": "OUT", + "from_pin": "I" + }, + "INTERMDISABLE_SEL:GND": { + "to_pin": "OUT", + "from_pin": "GND" + }, + "OUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "INTERMDISABLE_SEL:I": { + "to_pin": "OUT", + "from_pin": "I" + }, + "TUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + } + }, "site_pins": { - "KEEPER_INT_EN": { + "T": { "direction": "IN" }, - "T_OUT": { - "direction": "OUT" - }, - "DIFFO_IN": { - "direction": "IN" - }, - "PADOUT": { - "direction": "OUT" - }, "IBUFDISABLE": { "direction": "IN" }, - "INTERMDISABLE": { + "KEEPER_INT_EN": { "direction": "IN" }, "O_IN": { "direction": "IN" }, - "T": { - "direction": "IN" - }, - "PU_INT_EN": { - "direction": "IN" - }, - "DIFFO_OUT": { - "direction": "OUT" - }, - "PD_INT_EN": { - "direction": "IN" - }, - "DIFF_TERM_INT_EN": { - "direction": "IN" - }, "O": { "direction": "IN" }, + "DIFFI_IN": { + "direction": "IN" + }, "T_IN": { "direction": "IN" }, - "I": { - "direction": "OUT" - }, "O_OUT": { "direction": "OUT" }, - "DIFFI_IN": { + "DIFF_TERM_INT_EN": { "direction": "IN" - } - }, - "type": "IOB33", - "site_pips": { - "INTERMDISABLE_SEL:GND": { - "from_pin": "GND", - "to_pin": "OUT" }, - "OUSED:0": { - "from_pin": "0", - "to_pin": "OUT" + "DIFFO_OUT": { + "direction": "OUT" }, - "DIFFI_INUSED:0": { - "from_pin": "0", - "to_pin": "OUT" + "DIFFO_IN": { + "direction": "IN" }, - "IBUFDISABLE_SEL:GND": { - "from_pin": "GND", - "to_pin": "OUT" + "I": { + "direction": "OUT" }, - "IBUFDISABLE_SEL:I": { - "from_pin": "I", - "to_pin": "OUT" + "T_OUT": { + "direction": "OUT" }, - "TUSED:0": { - "from_pin": "0", - "to_pin": "OUT" + "PADOUT": { + "direction": "OUT" }, - "PADOUTUSED:0": { - "from_pin": "0", - "to_pin": "OUT" + "PD_INT_EN": { + "direction": "IN" }, - "IUSED:0": { - "from_pin": "0", - "to_pin": "OUT" + "PU_INT_EN": { + "direction": "IN" }, - "INTERMDISABLE_SEL:I": { - "from_pin": "I", - "to_pin": "OUT" + "INTERMDISABLE": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_IOB33M.json b/artix7/site_type_IOB33M.json index ba17ce1..d931aa1 100644 --- a/artix7/site_type_IOB33M.json +++ b/artix7/site_type_IOB33M.json @@ -1,106 +1,106 @@ { + "type": "IOB33M", + "site_pips": { + "DIFFO_OUTUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "O_OUTUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IBUFDISABLE_SEL:I": { + "to_pin": "OUT", + "from_pin": "I" + }, + "INTERMDISABLE_SEL:GND": { + "to_pin": "OUT", + "from_pin": "GND" + }, + "TUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "PADOUTUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IBUFDISABLE_SEL:GND": { + "to_pin": "OUT", + "from_pin": "GND" + }, + "INTERMDISABLE_SEL:I": { + "to_pin": "OUT", + "from_pin": "I" + }, + "DIFFI_INUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "T_OUTUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "OUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + } + }, "site_pins": { - "KEEPER_INT_EN": { + "T": { "direction": "IN" }, - "T_OUT": { - "direction": "OUT" - }, - "DIFFO_IN": { - "direction": "IN" - }, - "PADOUT": { - "direction": "OUT" - }, "IBUFDISABLE": { "direction": "IN" }, - "INTERMDISABLE": { + "KEEPER_INT_EN": { "direction": "IN" }, "O_IN": { "direction": "IN" }, - "T": { + "DIFFO_OUT": { + "direction": "OUT" + }, + "PD_INT_EN": { "direction": "IN" }, - "PU_INT_EN": { + "DIFFI_IN": { "direction": "IN" }, "T_IN": { "direction": "IN" }, - "PD_INT_EN": { - "direction": "IN" - }, "DIFF_TERM_INT_EN": { "direction": "IN" }, "O": { "direction": "IN" }, - "DIFFO_OUT": { + "T_OUT": { "direction": "OUT" }, + "DIFFO_IN": { + "direction": "IN" + }, "I": { "direction": "OUT" }, "O_OUT": { "direction": "OUT" }, - "DIFFI_IN": { + "PADOUT": { + "direction": "OUT" + }, + "PU_INT_EN": { "direction": "IN" - } - }, - "type": "IOB33M", - "site_pips": { - "INTERMDISABLE_SEL:GND": { - "from_pin": "GND", - "to_pin": "OUT" }, - "DIFFI_INUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "TUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "IBUFDISABLE_SEL:I": { - "from_pin": "I", - "to_pin": "OUT" - }, - "DIFFO_OUTUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "O_OUTUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "OUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "IBUFDISABLE_SEL:GND": { - "from_pin": "GND", - "to_pin": "OUT" - }, - "PADOUTUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "IUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "T_OUTUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "INTERMDISABLE_SEL:I": { - "from_pin": "I", - "to_pin": "OUT" + "INTERMDISABLE": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_IOB33S.json b/artix7/site_type_IOB33S.json index 977fa8d..3dad321 100644 --- a/artix7/site_type_IOB33S.json +++ b/artix7/site_type_IOB33S.json @@ -1,114 +1,114 @@ { + "type": "IOB33S", + "site_pips": { + "DIFFO_INUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "TINMUX:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "IBUFDISABLE_SEL:I": { + "to_pin": "OUT", + "from_pin": "I" + }, + "INTERMDISABLE_SEL:GND": { + "to_pin": "OUT", + "from_pin": "GND" + }, + "OINMUX:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "OUTMUX:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "OINMUX:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "OUTMUX:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "PADOUTUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IBUFDISABLE_SEL:GND": { + "to_pin": "OUT", + "from_pin": "GND" + }, + "DIFFI_INUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "TINMUX:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "IUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "INTERMDISABLE_SEL:I": { + "to_pin": "OUT", + "from_pin": "I" + } + }, "site_pins": { - "KEEPER_INT_EN": { + "T": { "direction": "IN" }, - "T_OUT": { - "direction": "OUT" - }, - "DIFFO_IN": { - "direction": "IN" - }, - "PADOUT": { - "direction": "OUT" - }, "IBUFDISABLE": { "direction": "IN" }, - "INTERMDISABLE": { + "KEEPER_INT_EN": { "direction": "IN" }, "O_IN": { "direction": "IN" }, - "T": { + "DIFFO_OUT": { + "direction": "OUT" + }, + "PD_INT_EN": { "direction": "IN" }, - "PU_INT_EN": { + "DIFFI_IN": { "direction": "IN" }, "T_IN": { "direction": "IN" }, - "PD_INT_EN": { - "direction": "IN" - }, "DIFF_TERM_INT_EN": { "direction": "IN" }, "O": { "direction": "IN" }, - "DIFFO_OUT": { + "T_OUT": { "direction": "OUT" }, + "DIFFO_IN": { + "direction": "IN" + }, "I": { "direction": "OUT" }, "O_OUT": { "direction": "OUT" }, - "DIFFI_IN": { + "PADOUT": { + "direction": "OUT" + }, + "PU_INT_EN": { "direction": "IN" - } - }, - "type": "IOB33S", - "site_pips": { - "DIFFI_INUSED:0": { - "from_pin": "0", - "to_pin": "OUT" }, - "OUTMUX:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "OINMUX:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "PADOUTUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "DIFFO_INUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "TINMUX:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "INTERMDISABLE_SEL:GND": { - "from_pin": "GND", - "to_pin": "OUT" - }, - "OINMUX:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "INTERMDISABLE_SEL:I": { - "from_pin": "I", - "to_pin": "OUT" - }, - "IBUFDISABLE_SEL:I": { - "from_pin": "I", - "to_pin": "OUT" - }, - "IBUFDISABLE_SEL:GND": { - "from_pin": "GND", - "to_pin": "OUT" - }, - "TINMUX:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "OUTMUX:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "IUSED:0": { - "from_pin": "0", - "to_pin": "OUT" + "INTERMDISABLE": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_IPAD.json b/artix7/site_type_IPAD.json index a14eaad..c3d5c12 100644 --- a/artix7/site_type_IPAD.json +++ b/artix7/site_type_IPAD.json @@ -1,9 +1,9 @@ { + "type": "IPAD", + "site_pips": {}, "site_pins": { "O": { "direction": "OUT" } - }, - "type": "IPAD", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_MMCME2_ADV.json b/artix7/site_type_MMCME2_ADV.json index 1f2f43e..ce2e872 100644 --- a/artix7/site_type_MMCME2_ADV.json +++ b/artix7/site_type_MMCME2_ADV.json @@ -1,545 +1,545 @@ { + "type": "MMCME2_ADV", + "site_pips": { + "CLKINSELINV:CLKINSEL": { + "to_pin": "OUT", + "from_pin": "CLKINSEL" + }, + "RSTINV:RST": { + "to_pin": "OUT", + "from_pin": "RST" + }, + "RSTINV:RST_B": { + "to_pin": "OUT", + "from_pin": "RST_B" + }, + "PSENINV:PSEN_B": { + "to_pin": "OUT", + "from_pin": "PSEN_B" + }, + "PSINCDECINV:PSINCDEC_B": { + "to_pin": "OUT", + "from_pin": "PSINCDEC_B" + }, + "PWRDWNINV:PWRDWN_B": { + "to_pin": "OUT", + "from_pin": "PWRDWN_B" + }, + "PSINCDECINV:PSINCDEC": { + "to_pin": "OUT", + "from_pin": "PSINCDEC" + }, + "PSENINV:PSEN": { + "to_pin": "OUT", + "from_pin": "PSEN" + }, + "CLKINSELINV:CLKINSEL_B": { + "to_pin": "OUT", + "from_pin": "CLKINSEL_B" + }, + "PWRDWNINV:PWRDWN": { + "to_pin": "OUT", + "from_pin": "PWRDWN" + } + }, "site_pins": { - "TESTIN17": { - "direction": "IN" - }, - "TESTOUT28": { - "direction": "OUT" - }, - "TESTOUT22": { - "direction": "OUT" - }, - "TESTOUT46": { - "direction": "OUT" - }, - "TESTOUT9": { - "direction": "OUT" - }, - "CLKINSEL": { - "direction": "IN" - }, - "DADDR0": { - "direction": "IN" - }, - "TESTOUT15": { - "direction": "OUT" - }, - "DI3": { - "direction": "IN" - }, - "TESTOUT27": { - "direction": "OUT" - }, - "TESTIN25": { - "direction": "IN" - }, - "DO12": { - "direction": "OUT" - }, - "DI8": { - "direction": "IN" - }, - "CLKOUT0": { - "direction": "OUT" - }, - "CLKOUT3": { - "direction": "OUT" - }, - "TESTIN28": { - "direction": "IN" - }, - "CLKOUT2": { - "direction": "OUT" - }, - "TESTOUT6": { - "direction": "OUT" - }, - "TESTOUT31": { - "direction": "OUT" - }, - "PSINCDEC": { - "direction": "IN" - }, - "TESTIN12": { - "direction": "IN" - }, - "PSCLK": { - "direction": "IN" - }, - "TESTOUT12": { - "direction": "OUT" - }, - "PWRDWN": { - "direction": "IN" - }, - "DO5": { - "direction": "OUT" - }, - "TESTIN26": { - "direction": "IN" - }, - "DI6": { - "direction": "IN" - }, - "PSEN": { - "direction": "IN" - }, - "TESTIN23": { - "direction": "IN" - }, - "DCLK": { - "direction": "IN" - }, - "TESTOUT23": { - "direction": "OUT" - }, - "CLKOUT3B": { - "direction": "OUT" - }, - "DADDR4": { - "direction": "IN" - }, - "TESTIN14": { - "direction": "IN" - }, - "TESTOUT4": { - "direction": "OUT" - }, - "TESTOUT42": { - "direction": "OUT" - }, - "TESTOUT32": { - "direction": "OUT" - }, - "TESTOUT39": { - "direction": "OUT" - }, - "DI10": { - "direction": "IN" - }, - "TESTIN1": { - "direction": "IN" - }, - "TESTOUT5": { - "direction": "OUT" - }, - "DI12": { - "direction": "IN" - }, - "TESTOUT38": { - "direction": "OUT" - }, - "DADDR1": { - "direction": "IN" - }, - "TESTOUT53": { - "direction": "OUT" - }, - "DI5": { - "direction": "IN" - }, - "TESTOUT47": { - "direction": "OUT" - }, - "CLKFBIN": { - "direction": "IN" - }, - "TESTOUT26": { - "direction": "OUT" - }, - "TESTIN31": { - "direction": "IN" - }, - "DO2": { - "direction": "OUT" - }, - "TMUXOUT": { - "direction": "OUT" - }, - "TESTOUT30": { - "direction": "OUT" - }, - "RST": { - "direction": "IN" - }, - "TESTOUT40": { - "direction": "OUT" - }, - "DRDY": { - "direction": "OUT" - }, - "TESTIN16": { - "direction": "IN" - }, - "DEN": { - "direction": "IN" - }, - "TESTOUT52": { - "direction": "OUT" - }, - "CLKOUT1": { - "direction": "OUT" - }, - "TESTIN4": { - "direction": "IN" - }, - "TESTIN2": { - "direction": "IN" - }, - "TESTOUT37": { - "direction": "OUT" - }, - "TESTOUT0": { - "direction": "OUT" - }, - "TESTIN18": { - "direction": "IN" - }, - "DADDR3": { - "direction": "IN" - }, - "TESTOUT57": { - "direction": "OUT" - }, - "TESTIN3": { - "direction": "IN" - }, - "TESTOUT33": { - "direction": "OUT" - }, - "CLKOUT6": { - "direction": "OUT" - }, - "TESTOUT35": { - "direction": "OUT" - }, - "DI9": { - "direction": "IN" - }, - "DO0": { - "direction": "OUT" - }, - "TESTOUT59": { - "direction": "OUT" - }, - "CLKINSTOPPED": { - "direction": "OUT" - }, - "CLKFBSTOPPED": { - "direction": "OUT" - }, - "TESTOUT44": { - "direction": "OUT" - }, - "TESTIN30": { - "direction": "IN" - }, - "DO9": { - "direction": "OUT" - }, - "TESTOUT58": { - "direction": "OUT" - }, - "TESTIN0": { - "direction": "IN" - }, - "DO10": { - "direction": "OUT" - }, - "TESTOUT17": { - "direction": "OUT" - }, - "CLKIN2": { - "direction": "IN" - }, - "CLKIN1": { - "direction": "IN" - }, - "LOCKED": { - "direction": "OUT" - }, - "TESTOUT20": { - "direction": "OUT" - }, - "DO8": { - "direction": "OUT" - }, - "TESTOUT25": { - "direction": "OUT" - }, - "DO6": { - "direction": "OUT" - }, - "TESTOUT51": { - "direction": "OUT" - }, - "TESTOUT34": { - "direction": "OUT" - }, - "TESTOUT55": { - "direction": "OUT" - }, - "TESTIN29": { - "direction": "IN" - }, - "DI13": { - "direction": "IN" - }, - "DADDR6": { - "direction": "IN" - }, - "DI1": { - "direction": "IN" - }, - "TESTIN27": { - "direction": "IN" - }, - "TESTOUT3": { - "direction": "OUT" - }, - "TESTOUT61": { - "direction": "OUT" - }, "TESTIN15": { "direction": "IN" }, - "CLKOUT5": { + "PSDONE": { "direction": "OUT" }, - "DO7": { - "direction": "OUT" - }, - "TESTOUT18": { + "DO9": { "direction": "OUT" }, "DI0": { "direction": "IN" }, - "TESTIN5": { - "direction": "IN" - }, - "TESTOUT43": { + "CLKFBSTOPPED": { "direction": "OUT" }, - "TESTIN21": { - "direction": "IN" - }, - "DO3": { - "direction": "OUT" - }, - "CLKOUT4": { - "direction": "OUT" - }, - "CLKOUT1B": { - "direction": "OUT" - }, - "PSDONE": { - "direction": "OUT" - }, - "TESTIN9": { - "direction": "IN" - }, - "TESTIN13": { - "direction": "IN" - }, - "DO4": { - "direction": "OUT" - }, - "DO11": { - "direction": "OUT" - }, - "TESTIN22": { - "direction": "IN" - }, - "TESTOUT19": { - "direction": "OUT" - }, - "TESTOUT1": { - "direction": "OUT" - }, - "TESTOUT13": { + "TMUXOUT": { "direction": "OUT" }, "DI7": { "direction": "IN" }, - "TESTIN7": { + "DI15": { "direction": "IN" }, - "TESTOUT10": { - "direction": "OUT" - }, - "TESTOUT60": { - "direction": "OUT" - }, - "TESTOUT8": { - "direction": "OUT" - }, - "TESTOUT45": { - "direction": "OUT" - }, - "TESTOUT7": { - "direction": "OUT" - }, - "CLKOUT2B": { - "direction": "OUT" - }, - "DADDR2": { + "DI10": { "direction": "IN" }, - "CLKOUT0B": { + "TESTOUT0": { "direction": "OUT" }, - "TESTOUT50": { - "direction": "OUT" - }, - "DO15": { - "direction": "OUT" - }, - "TESTOUT49": { - "direction": "OUT" + "DADDR0": { + "direction": "IN" }, "TESTOUT21": { "direction": "OUT" }, - "TESTIN19": { - "direction": "IN" - }, - "DI15": { - "direction": "IN" - }, - "CLKFBOUTB": { + "TESTOUT22": { "direction": "OUT" }, - "TESTOUT29": { + "TESTOUT31": { "direction": "OUT" }, - "TESTOUT36": { - "direction": "OUT" - }, - "TESTOUT24": { - "direction": "OUT" - }, - "TESTOUT54": { - "direction": "OUT" - }, - "TESTOUT63": { - "direction": "OUT" - }, - "TESTIN10": { - "direction": "IN" - }, "TESTOUT14": { "direction": "OUT" }, "TESTOUT62": { "direction": "OUT" }, - "TESTOUT11": { - "direction": "OUT" - }, - "DI4": { + "PSINCDEC": { "direction": "IN" }, - "TESTOUT56": { - "direction": "OUT" + "TESTIN17": { + "direction": "IN" }, "TESTIN20": { "direction": "IN" }, - "DI14": { - "direction": "IN" - }, - "TESTOUT16": { + "CLKOUT3": { "direction": "OUT" }, - "TESTOUT2": { + "TESTIN27": { + "direction": "IN" + }, + "DEN": { + "direction": "IN" + }, + "CLKOUT5": { + "direction": "OUT" + }, + "TESTOUT7": { + "direction": "OUT" + }, + "TESTOUT43": { + "direction": "OUT" + }, + "TESTOUT57": { + "direction": "OUT" + }, + "TESTIN14": { + "direction": "IN" + }, + "DRDY": { + "direction": "OUT" + }, + "TESTOUT36": { + "direction": "OUT" + }, + "DO5": { + "direction": "OUT" + }, + "TESTIN25": { + "direction": "IN" + }, + "TESTOUT27": { + "direction": "OUT" + }, + "TESTOUT8": { + "direction": "OUT" + }, + "DADDR6": { + "direction": "IN" + }, + "TESTIN7": { + "direction": "IN" + }, + "TESTIN3": { + "direction": "IN" + }, + "TESTOUT26": { + "direction": "OUT" + }, + "TESTOUT40": { + "direction": "OUT" + }, + "TESTOUT1": { + "direction": "OUT" + }, + "DI3": { + "direction": "IN" + }, + "TESTOUT11": { + "direction": "OUT" + }, + "TESTOUT51": { + "direction": "OUT" + }, + "CLKOUT0B": { + "direction": "OUT" + }, + "DI8": { + "direction": "IN" + }, + "TESTOUT45": { + "direction": "OUT" + }, + "TESTIN8": { + "direction": "IN" + }, + "DO14": { + "direction": "OUT" + }, + "TESTIN22": { + "direction": "IN" + }, + "TESTOUT23": { + "direction": "OUT" + }, + "TESTOUT48": { + "direction": "OUT" + }, + "DADDR1": { + "direction": "IN" + }, + "DO3": { + "direction": "OUT" + }, + "TESTOUT50": { + "direction": "OUT" + }, + "CLKOUT3B": { + "direction": "OUT" + }, + "CLKFBIN": { + "direction": "IN" + }, + "DO8": { + "direction": "OUT" + }, + "TESTIN2": { + "direction": "IN" + }, + "DO1": { + "direction": "OUT" + }, + "TESTIN21": { + "direction": "IN" + }, + "CLKINSTOPPED": { + "direction": "OUT" + }, + "DO12": { + "direction": "OUT" + }, + "TESTOUT33": { + "direction": "OUT" + }, + "DI6": { + "direction": "IN" + }, + "TESTIN26": { + "direction": "IN" + }, + "CLKINSEL": { + "direction": "IN" + }, + "CLKOUT2B": { + "direction": "OUT" + }, + "TESTOUT60": { + "direction": "OUT" + }, + "DADDR4": { + "direction": "IN" + }, + "DADDR2": { + "direction": "IN" + }, + "TESTOUT4": { + "direction": "OUT" + }, + "TESTOUT38": { + "direction": "OUT" + }, + "DO10": { + "direction": "OUT" + }, + "CLKOUT0": { + "direction": "OUT" + }, + "CLKOUT6": { + "direction": "OUT" + }, + "TESTIN30": { + "direction": "IN" + }, + "TESTIN18": { + "direction": "IN" + }, + "TESTOUT6": { + "direction": "OUT" + }, + "TESTOUT58": { + "direction": "OUT" + }, + "TESTOUT53": { "direction": "OUT" }, "CLKFBOUT": { "direction": "OUT" }, + "TESTIN28": { + "direction": "IN" + }, + "TESTOUT19": { + "direction": "OUT" + }, + "TESTOUT20": { + "direction": "OUT" + }, + "TESTIN12": { + "direction": "IN" + }, "DO13": { "direction": "OUT" }, - "TESTOUT41": { - "direction": "OUT" - }, - "DO14": { - "direction": "OUT" - }, - "DWE": { - "direction": "IN" - }, "DI2": { "direction": "IN" }, - "DADDR5": { - "direction": "IN" - }, - "TESTOUT48": { + "DO0": { "direction": "OUT" }, - "DO1": { + "DO11": { + "direction": "OUT" + }, + "TESTIN19": { + "direction": "IN" + }, + "DI12": { + "direction": "IN" + }, + "LOCKED": { + "direction": "OUT" + }, + "TESTIN4": { + "direction": "IN" + }, + "TESTOUT15": { + "direction": "OUT" + }, + "TESTOUT34": { + "direction": "OUT" + }, + "DO6": { + "direction": "OUT" + }, + "DI13": { + "direction": "IN" + }, + "TESTOUT24": { + "direction": "OUT" + }, + "TESTOUT61": { + "direction": "OUT" + }, + "TESTOUT59": { + "direction": "OUT" + }, + "PSCLK": { + "direction": "IN" + }, + "DI1": { + "direction": "IN" + }, + "CLKFBOUTB": { + "direction": "OUT" + }, + "TESTOUT37": { + "direction": "OUT" + }, + "TESTOUT46": { + "direction": "OUT" + }, + "CLKOUT1": { + "direction": "OUT" + }, + "TESTOUT54": { + "direction": "OUT" + }, + "TESTOUT44": { + "direction": "OUT" + }, + "TESTOUT29": { + "direction": "OUT" + }, + "TESTOUT9": { + "direction": "OUT" + }, + "TESTOUT3": { + "direction": "OUT" + }, + "TESTIN23": { + "direction": "IN" + }, + "DO15": { + "direction": "OUT" + }, + "CLKIN2": { + "direction": "IN" + }, + "TESTIN5": { + "direction": "IN" + }, + "CLKOUT1B": { + "direction": "OUT" + }, + "TESTOUT13": { + "direction": "OUT" + }, + "DO7": { + "direction": "OUT" + }, + "TESTIN6": { + "direction": "IN" + }, + "TESTOUT49": { + "direction": "OUT" + }, + "TESTOUT5": { + "direction": "OUT" + }, + "DI4": { + "direction": "IN" + }, + "TESTIN13": { + "direction": "IN" + }, + "TESTOUT28": { + "direction": "OUT" + }, + "TESTIN1": { + "direction": "IN" + }, + "DI5": { + "direction": "IN" + }, + "TESTOUT55": { + "direction": "OUT" + }, + "TESTIN16": { + "direction": "IN" + }, + "TESTOUT56": { "direction": "OUT" }, "DI11": { "direction": "IN" }, - "TESTIN6": { + "TESTOUT10": { + "direction": "OUT" + }, + "TESTOUT47": { + "direction": "OUT" + }, + "TESTIN29": { "direction": "IN" }, - "TESTIN8": { + "DWE": { "direction": "IN" }, - "TESTIN24": { + "TESTOUT16": { + "direction": "OUT" + }, + "TESTOUT35": { + "direction": "OUT" + }, + "TESTIN10": { "direction": "IN" }, "TESTIN11": { "direction": "IN" - } - }, - "type": "MMCME2_ADV", - "site_pips": { - "CLKINSELINV:CLKINSEL": { - "from_pin": "CLKINSEL", - "to_pin": "OUT" }, - "CLKINSELINV:CLKINSEL_B": { - "from_pin": "CLKINSEL_B", - "to_pin": "OUT" + "TESTOUT63": { + "direction": "OUT" }, - "PWRDWNINV:PWRDWN": { - "from_pin": "PWRDWN", - "to_pin": "OUT" + "CLKOUT2": { + "direction": "OUT" }, - "PWRDWNINV:PWRDWN_B": { - "from_pin": "PWRDWN_B", - "to_pin": "OUT" + "CLKIN1": { + "direction": "IN" }, - "PSINCDECINV:PSINCDEC_B": { - "from_pin": "PSINCDEC_B", - "to_pin": "OUT" + "DO4": { + "direction": "OUT" }, - "PSENINV:PSEN_B": { - "from_pin": "PSEN_B", - "to_pin": "OUT" + "DCLK": { + "direction": "IN" }, - "PSINCDECINV:PSINCDEC": { - "from_pin": "PSINCDEC", - "to_pin": "OUT" + "TESTOUT25": { + "direction": "OUT" }, - "PSENINV:PSEN": { - "from_pin": "PSEN", - "to_pin": "OUT" + "DADDR3": { + "direction": "IN" }, - "RSTINV:RST": { - "from_pin": "RST", - "to_pin": "OUT" + "TESTOUT41": { + "direction": "OUT" }, - "RSTINV:RST_B": { - "from_pin": "RST_B", - "to_pin": "OUT" + "RST": { + "direction": "IN" + }, + "TESTOUT42": { + "direction": "OUT" + }, + "TESTOUT52": { + "direction": "OUT" + }, + "TESTOUT39": { + "direction": "OUT" + }, + "TESTOUT32": { + "direction": "OUT" + }, + "DADDR5": { + "direction": "IN" + }, + "TESTOUT17": { + "direction": "OUT" + }, + "DO2": { + "direction": "OUT" + }, + "TESTIN0": { + "direction": "IN" + }, + "TESTOUT12": { + "direction": "OUT" + }, + "TESTOUT30": { + "direction": "OUT" + }, + "TESTIN24": { + "direction": "IN" + }, + "PWRDWN": { + "direction": "IN" + }, + "DI14": { + "direction": "IN" + }, + "TESTIN31": { + "direction": "IN" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "TESTIN9": { + "direction": "IN" + }, + "DI9": { + "direction": "IN" + }, + "PSEN": { + "direction": "IN" + }, + "TESTOUT18": { + "direction": "OUT" + }, + "CLKOUT4": { + "direction": "OUT" } } } \ No newline at end of file diff --git a/artix7/site_type_OLOGICE3.json b/artix7/site_type_OLOGICE3.json index 07a1a78..e41b347 100644 --- a/artix7/site_type_OLOGICE3.json +++ b/artix7/site_type_OLOGICE3.json @@ -1,210 +1,210 @@ { + "type": "OLOGICE3", + "site_pips": { + "T2INV:T2": { + "to_pin": "OUT", + "from_pin": "T2" + }, + "T1INV:T1_B": { + "to_pin": "OUT", + "from_pin": "T1_B" + }, + "OQUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "OFBUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "T1USED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "D1INV:D1_B": { + "to_pin": "OUT", + "from_pin": "D1_B" + }, + "TFBUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "CLKINV:CLK_B": { + "to_pin": "OUT", + "from_pin": "CLK_B" + }, + "OCEUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "D1INV:D1": { + "to_pin": "OUT", + "from_pin": "D1" + }, + "OREVUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "OSRUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "TQUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "D2INV:D2": { + "to_pin": "OUT", + "from_pin": "D2" + }, + "O1USED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "CLKINV:CLK": { + "to_pin": "OUT", + "from_pin": "CLK" + }, + "TMUX:T1": { + "to_pin": "OUT", + "from_pin": "T1" + }, + "TSRUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "TREVUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "TCEUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "TMUX:TFF": { + "to_pin": "OUT", + "from_pin": "TFF" + }, + "OMUX:D1": { + "to_pin": "OUT", + "from_pin": "D1" + }, + "OMUX:OUTFF": { + "to_pin": "OUT", + "from_pin": "OUTFF" + }, + "T1INV:T1": { + "to_pin": "OUT", + "from_pin": "T1" + }, + "D2INV:D2_B": { + "to_pin": "OUT", + "from_pin": "D2_B" + }, + "T2INV:T2_B": { + "to_pin": "OUT", + "from_pin": "T2_B" + } + }, "site_pins": { - "TCE": { - "direction": "IN" - }, - "T3": { - "direction": "IN" - }, - "REV": { - "direction": "IN" - }, - "CLKDIVF": { - "direction": "IN" - }, - "T1": { - "direction": "IN" - }, - "T4": { - "direction": "IN" - }, - "SHIFTIN2": { - "direction": "IN" - }, - "CLK": { - "direction": "IN" - }, - "TBYTEIN": { - "direction": "IN" - }, - "D5": { - "direction": "IN" - }, - "D8": { - "direction": "IN" - }, - "SR": { - "direction": "IN" - }, - "CLKDIVB": { - "direction": "IN" - }, - "TQ": { - "direction": "OUT" - }, - "TFB": { - "direction": "OUT" - }, "T2": { "direction": "IN" }, - "D7": { + "D1": { + "direction": "IN" + }, + "TBYTEOUT": { + "direction": "OUT" + }, + "D6": { "direction": "IN" }, "D3": { "direction": "IN" }, - "OFB": { + "D8": { + "direction": "IN" + }, + "CLKDIVB": { + "direction": "IN" + }, + "CLKB": { + "direction": "IN" + }, + "REV": { + "direction": "IN" + }, + "T1": { + "direction": "IN" + }, + "D5": { + "direction": "IN" + }, + "TFB": { + "direction": "OUT" + }, + "SHIFTIN1": { + "direction": "IN" + }, + "SHIFTOUT1": { + "direction": "OUT" + }, + "T4": { + "direction": "IN" + }, + "D4": { + "direction": "IN" + }, + "TQ": { "direction": "OUT" }, "D2": { "direction": "IN" }, + "T3": { + "direction": "IN" + }, + "OCE": { + "direction": "IN" + }, "SHIFTOUT2": { "direction": "OUT" }, + "OFB": { + "direction": "OUT" + }, + "CLKDIVF": { + "direction": "IN" + }, + "OQ": { + "direction": "OUT" + }, + "SHIFTIN2": { + "direction": "IN" + }, + "SR": { + "direction": "IN" + }, "IOCLKGLITCH": { "direction": "OUT" }, "CLKDIVFB": { "direction": "IN" }, - "TBYTEOUT": { - "direction": "OUT" - }, - "D1": { + "TCE": { "direction": "IN" }, - "D4": { + "TBYTEIN": { "direction": "IN" }, - "D6": { + "D7": { "direction": "IN" }, - "OCE": { - "direction": "IN" - }, - "CLKB": { - "direction": "IN" - }, - "OQ": { - "direction": "OUT" - }, - "SHIFTOUT1": { - "direction": "OUT" - }, - "SHIFTIN1": { + "CLK": { "direction": "IN" }, "CLKDIV": { "direction": "IN" } - }, - "type": "OLOGICE3", - "site_pips": { - "T2INV:T2_B": { - "from_pin": "T2_B", - "to_pin": "OUT" - }, - "OMUX:D1": { - "from_pin": "D1", - "to_pin": "OUT" - }, - "OSRUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "T1INV:T1": { - "from_pin": "T1", - "to_pin": "OUT" - }, - "T1USED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "TMUX:TFF": { - "from_pin": "TFF", - "to_pin": "OUT" - }, - "OMUX:OUTFF": { - "from_pin": "OUTFF", - "to_pin": "OUT" - }, - "D2INV:D2": { - "from_pin": "D2", - "to_pin": "OUT" - }, - "D2INV:D2_B": { - "from_pin": "D2_B", - "to_pin": "OUT" - }, - "OREVUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "T1INV:T1_B": { - "from_pin": "T1_B", - "to_pin": "OUT" - }, - "TMUX:T1": { - "from_pin": "T1", - "to_pin": "OUT" - }, - "TFBUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "OCEUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "TSRUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "OQUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "D1INV:D1_B": { - "from_pin": "D1_B", - "to_pin": "OUT" - }, - "O1USED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "TCEUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "OFBUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "T2INV:T2": { - "from_pin": "T2", - "to_pin": "OUT" - }, - "TQUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "CLKINV:CLK": { - "from_pin": "CLK", - "to_pin": "OUT" - }, - "CLKINV:CLK_B": { - "from_pin": "CLK_B", - "to_pin": "OUT" - }, - "TREVUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "D1INV:D1": { - "from_pin": "D1", - "to_pin": "OUT" - } } } \ No newline at end of file diff --git a/artix7/site_type_OPAD.json b/artix7/site_type_OPAD.json index 58400ed..c671fb7 100644 --- a/artix7/site_type_OPAD.json +++ b/artix7/site_type_OPAD.json @@ -1,9 +1,9 @@ { + "type": "OPAD", + "site_pips": {}, "site_pins": { "I": { "direction": "IN" } - }, - "type": "OPAD", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_OUT_FIFO.json b/artix7/site_type_OUT_FIFO.json index 3f522bf..0a35b01 100644 --- a/artix7/site_type_OUT_FIFO.json +++ b/artix7/site_type_OUT_FIFO.json @@ -1,453 +1,453 @@ { + "type": "OUT_FIFO", + "site_pips": {}, "site_pins": { - "Q57": { - "direction": "OUT" - }, - "Q62": { - "direction": "OUT" - }, - "Q61": { - "direction": "OUT" - }, - "Q50": { - "direction": "OUT" - }, - "Q66": { - "direction": "OUT" - }, - "D46": { - "direction": "IN" - }, - "D22": { - "direction": "IN" - }, - "D41": { - "direction": "IN" - }, - "Q65": { - "direction": "OUT" - }, - "D20": { - "direction": "IN" - }, - "Q93": { - "direction": "OUT" - }, - "Q40": { - "direction": "OUT" - }, - "EMPTY": { - "direction": "OUT" - }, - "D13": { - "direction": "IN" - }, - "D54": { - "direction": "IN" - }, - "D64": { - "direction": "IN" - }, - "D95": { - "direction": "IN" - }, - "D01": { - "direction": "IN" - }, - "Q13": { - "direction": "OUT" - }, - "D52": { + "SCANIN2": { "direction": "IN" }, "Q83": { "direction": "OUT" }, - "Q43": { - "direction": "OUT" - }, - "D51": { - "direction": "IN" - }, - "D36": { - "direction": "IN" - }, - "Q20": { - "direction": "OUT" - }, - "D93": { - "direction": "IN" - }, - "D35": { - "direction": "IN" - }, - "D37": { - "direction": "IN" - }, - "Q80": { - "direction": "OUT" - }, - "Q56": { - "direction": "OUT" - }, - "D92": { - "direction": "IN" - }, - "Q11": { - "direction": "OUT" - }, - "D75": { - "direction": "IN" - }, - "Q53": { - "direction": "OUT" - }, - "D82": { - "direction": "IN" - }, - "D62": { - "direction": "IN" - }, - "SCANOUT0": { - "direction": "OUT" - }, - "Q01": { - "direction": "OUT" - }, - "Q73": { - "direction": "OUT" - }, - "D24": { - "direction": "IN" - }, - "D27": { - "direction": "IN" - }, - "RESET": { - "direction": "IN" - }, - "SCANOUT2": { - "direction": "OUT" - }, - "D06": { - "direction": "IN" - }, - "FULL": { - "direction": "OUT" - }, - "Q60": { - "direction": "OUT" - }, - "D42": { - "direction": "IN" - }, - "D16": { - "direction": "IN" - }, - "D80": { - "direction": "IN" - }, - "D66": { - "direction": "IN" - }, - "D00": { - "direction": "IN" - }, - "D47": { - "direction": "IN" - }, - "Q41": { - "direction": "OUT" - }, - "D30": { - "direction": "IN" - }, - "D55": { - "direction": "IN" - }, - "Q63": { - "direction": "OUT" - }, - "D61": { - "direction": "IN" - }, - "TESTMODEB": { - "direction": "IN" - }, - "D03": { - "direction": "IN" - }, - "Q23": { - "direction": "OUT" - }, - "Q82": { - "direction": "OUT" - }, - "Q12": { - "direction": "OUT" - }, - "Q30": { - "direction": "OUT" - }, - "D05": { - "direction": "IN" - }, - "D32": { - "direction": "IN" - }, - "Q72": { - "direction": "OUT" - }, - "D96": { - "direction": "IN" - }, - "Q90": { - "direction": "OUT" - }, - "Q55": { - "direction": "OUT" - }, - "Q42": { - "direction": "OUT" - }, - "D60": { - "direction": "IN" - }, - "D14": { - "direction": "IN" - }, - "D26": { - "direction": "IN" - }, - "ALMOSTFULL": { - "direction": "OUT" - }, - "Q32": { - "direction": "OUT" - }, - "SCANIN1": { - "direction": "IN" - }, - "D71": { - "direction": "IN" - }, - "D56": { - "direction": "IN" - }, - "D67": { - "direction": "IN" - }, - "D02": { - "direction": "IN" - }, "D07": { "direction": "IN" }, - "SCANOUT1": { - "direction": "OUT" - }, - "Q54": { - "direction": "OUT" - }, - "D25": { - "direction": "IN" - }, - "D72": { - "direction": "IN" - }, - "Q51": { - "direction": "OUT" - }, - "D44": { - "direction": "IN" - }, - "SCANIN3": { - "direction": "IN" - }, - "Q92": { - "direction": "OUT" - }, - "Q33": { - "direction": "OUT" - }, - "Q67": { - "direction": "OUT" - }, - "D50": { - "direction": "IN" - }, - "ALMOSTEMPTY": { - "direction": "OUT" - }, - "D65": { - "direction": "IN" - }, - "D17": { - "direction": "IN" - }, "D31": { "direction": "IN" }, - "SCANOUT3": { + "D75": { + "direction": "IN" + }, + "Q62": { "direction": "OUT" }, - "D87": { + "D12": { "direction": "IN" }, - "D23": { + "D67": { "direction": "IN" }, - "D73": { - "direction": "IN" - }, - "Q81": { - "direction": "OUT" - }, - "Q21": { - "direction": "OUT" - }, - "D91": { - "direction": "IN" - }, - "RDCLK": { - "direction": "IN" - }, - "D74": { - "direction": "IN" - }, - "D21": { - "direction": "IN" - }, - "Q00": { - "direction": "OUT" - }, - "Q64": { - "direction": "OUT" - }, - "D10": { - "direction": "IN" - }, - "D43": { - "direction": "IN" - }, - "Q70": { - "direction": "OUT" - }, - "D57": { - "direction": "IN" - }, - "D81": { - "direction": "IN" - }, - "D15": { - "direction": "IN" - }, - "D04": { - "direction": "IN" - }, - "Q10": { - "direction": "OUT" - }, - "Q03": { - "direction": "OUT" - }, - "TESTREADDISB": { - "direction": "IN" - }, - "TESTWRITEDISB": { - "direction": "IN" - }, - "D85": { - "direction": "IN" - }, - "Q52": { - "direction": "OUT" - }, - "RDEN": { - "direction": "IN" - }, - "WREN": { - "direction": "IN" - }, - "Q02": { - "direction": "OUT" - }, - "D97": { - "direction": "IN" - }, - "D45": { - "direction": "IN" - }, - "Q71": { - "direction": "OUT" - }, - "D83": { - "direction": "IN" - }, - "Q22": { + "Q53": { "direction": "OUT" }, "D90": { "direction": "IN" }, - "D40": { + "ALMOSTEMPTY": { + "direction": "OUT" + }, + "Q67": { + "direction": "OUT" + }, + "D13": { "direction": "IN" }, - "Q31": { + "D72": { + "direction": "IN" + }, + "RDCLK": { + "direction": "IN" + }, + "Q81": { "direction": "OUT" }, + "D22": { + "direction": "IN" + }, + "D46": { + "direction": "IN" + }, + "Q82": { + "direction": "OUT" + }, + "Q03": { + "direction": "OUT" + }, + "D87": { + "direction": "IN" + }, + "Q10": { + "direction": "OUT" + }, + "Q21": { + "direction": "OUT" + }, + "D20": { + "direction": "IN" + }, + "Q70": { + "direction": "OUT" + }, + "SCANIN1": { + "direction": "IN" + }, + "SCANENB": { + "direction": "IN" + }, + "D24": { + "direction": "IN" + }, + "D80": { + "direction": "IN" + }, + "ALMOSTFULL": { + "direction": "OUT" + }, + "D44": { + "direction": "IN" + }, + "D37": { + "direction": "IN" + }, + "Q41": { + "direction": "OUT" + }, + "Q43": { + "direction": "OUT" + }, + "Q55": { + "direction": "OUT" + }, + "Q13": { + "direction": "OUT" + }, + "SCANOUT1": { + "direction": "OUT" + }, + "D73": { + "direction": "IN" + }, + "Q22": { + "direction": "OUT" + }, + "SCANOUT2": { + "direction": "OUT" + }, + "D27": { + "direction": "IN" + }, + "Q42": { + "direction": "OUT" + }, + "D94": { + "direction": "IN" + }, + "D66": { + "direction": "IN" + }, + "Q65": { + "direction": "OUT" + }, + "D36": { + "direction": "IN" + }, + "FULL": { + "direction": "OUT" + }, + "D85": { + "direction": "IN" + }, + "D15": { + "direction": "IN" + }, + "D84": { + "direction": "IN" + }, + "D21": { + "direction": "IN" + }, + "D92": { + "direction": "IN" + }, + "Q51": { + "direction": "OUT" + }, + "D53": { + "direction": "IN" + }, + "Q56": { + "direction": "OUT" + }, + "D34": { + "direction": "IN" + }, + "Q90": { + "direction": "OUT" + }, + "D65": { + "direction": "IN" + }, + "D14": { + "direction": "IN" + }, + "D50": { + "direction": "IN" + }, + "D32": { + "direction": "IN" + }, + "D76": { + "direction": "IN" + }, + "D97": { + "direction": "IN" + }, + "Q64": { + "direction": "OUT" + }, + "Q20": { + "direction": "OUT" + }, + "SCANOUT3": { + "direction": "OUT" + }, + "Q92": { + "direction": "OUT" + }, + "D42": { + "direction": "IN" + }, + "WREN": { + "direction": "IN" + }, + "D51": { + "direction": "IN" + }, + "D10": { + "direction": "IN" + }, + "Q91": { + "direction": "OUT" + }, + "D16": { + "direction": "IN" + }, + "Q61": { + "direction": "OUT" + }, + "D01": { + "direction": "IN" + }, + "D71": { + "direction": "IN" + }, + "Q57": { + "direction": "OUT" + }, + "D45": { + "direction": "IN" + }, + "D96": { + "direction": "IN" + }, + "D81": { + "direction": "IN" + }, "SCANIN0": { "direction": "IN" }, "D70": { "direction": "IN" }, - "D94": { + "Q66": { + "direction": "OUT" + }, + "D05": { + "direction": "IN" + }, + "Q11": { + "direction": "OUT" + }, + "D61": { "direction": "IN" }, "D86": { "direction": "IN" }, - "D12": { - "direction": "IN" - }, - "D84": { + "D91": { "direction": "IN" }, "WRCLK": { "direction": "IN" }, - "D53": { + "D17": { "direction": "IN" }, - "D11": { + "D03": { "direction": "IN" }, - "D33": { + "Q80": { + "direction": "OUT" + }, + "SCANIN3": { "direction": "IN" }, - "SCANENB": { + "D93": { "direction": "IN" }, - "D34": { + "TESTMODEB": { + "direction": "IN" + }, + "Q01": { + "direction": "OUT" + }, + "D56": { + "direction": "IN" + }, + "D60": { + "direction": "IN" + }, + "D06": { "direction": "IN" }, "D77": { "direction": "IN" }, - "D76": { + "D52": { "direction": "IN" }, - "SCANIN2": { + "D04": { "direction": "IN" }, + "RESET": { + "direction": "IN" + }, + "SCANOUT0": { + "direction": "OUT" + }, + "Q50": { + "direction": "OUT" + }, + "D43": { + "direction": "IN" + }, + "D74": { + "direction": "IN" + }, + "D11": { + "direction": "IN" + }, + "D54": { + "direction": "IN" + }, + "D55": { + "direction": "IN" + }, + "D35": { + "direction": "IN" + }, + "Q93": { + "direction": "OUT" + }, + "TESTWRITEDISB": { + "direction": "IN" + }, + "Q63": { + "direction": "OUT" + }, + "Q00": { + "direction": "OUT" + }, + "Q54": { + "direction": "OUT" + }, + "Q30": { + "direction": "OUT" + }, + "D00": { + "direction": "IN" + }, + "Q33": { + "direction": "OUT" + }, + "D30": { + "direction": "IN" + }, + "Q32": { + "direction": "OUT" + }, "D63": { "direction": "IN" }, - "Q91": { + "RDEN": { + "direction": "IN" + }, + "EMPTY": { "direction": "OUT" + }, + "D64": { + "direction": "IN" + }, + "Q52": { + "direction": "OUT" + }, + "D26": { + "direction": "IN" + }, + "Q73": { + "direction": "OUT" + }, + "Q60": { + "direction": "OUT" + }, + "Q12": { + "direction": "OUT" + }, + "D83": { + "direction": "IN" + }, + "TESTREADDISB": { + "direction": "IN" + }, + "D33": { + "direction": "IN" + }, + "Q31": { + "direction": "OUT" + }, + "Q23": { + "direction": "OUT" + }, + "D82": { + "direction": "IN" + }, + "Q02": { + "direction": "OUT" + }, + "D25": { + "direction": "IN" + }, + "D57": { + "direction": "IN" + }, + "D40": { + "direction": "IN" + }, + "Q40": { + "direction": "OUT" + }, + "Q72": { + "direction": "OUT" + }, + "Q71": { + "direction": "OUT" + }, + "D62": { + "direction": "IN" + }, + "D02": { + "direction": "IN" + }, + "D95": { + "direction": "IN" + }, + "D47": { + "direction": "IN" + }, + "D23": { + "direction": "IN" + }, + "D41": { + "direction": "IN" } - }, - "type": "OUT_FIFO", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_PCIE_2_1.json b/artix7/site_type_PCIE_2_1.json index 3f17983..3dbe84a 100644 --- a/artix7/site_type_PCIE_2_1.json +++ b/artix7/site_type_PCIE_2_1.json @@ -1,6753 +1,6753 @@ { + "type": "PCIE_2_1", + "site_pips": {}, "site_pins": { - "CFGERRAERHEADERLOG120": { - "direction": "IN" - }, - "TL2ERRHDR4": { - "direction": "OUT" - }, - "PIPERX6CHARISK1": { - "direction": "IN" - }, - "DBGSCLRI": { - "direction": "OUT" - }, - "TRNTDSTRDY3": { - "direction": "OUT" - }, - "MIMRXWDATA27": { - "direction": "OUT" - }, - "DBGVECB17": { - "direction": "OUT" - }, - "CFGINTERRUPTDO2": { - "direction": "OUT" - }, - "CFGMGMTDI14": { - "direction": "IN" - }, - "DBGVECB46": { - "direction": "OUT" - }, - "TRNRD38": { - "direction": "OUT" - }, - "TRNRDLLPDATA55": { - "direction": "OUT" - }, - "CFGDSN10": { - "direction": "IN" - }, - "TL2ERRHDR14": { - "direction": "OUT" - }, - "MIMTXWDATA4": { - "direction": "OUT" - }, - "PIPERX4DATA2": { - "direction": "IN" - }, - "MIMRXWDATA2": { - "direction": "OUT" - }, - "TRNTD81": { - "direction": "IN" - }, - "PIPERX0DATA6": { - "direction": "IN" - }, - "TRNRD20": { - "direction": "OUT" - }, - "CFGDEVID14": { - "direction": "IN" - }, - "PLINITIALLINKWIDTH1": { - "direction": "OUT" - }, - "LNKCLKEN": { - "direction": "OUT" - }, - "PLLINKGEN2CAP": { - "direction": "OUT" - }, - "DBGVECA11": { - "direction": "OUT" - }, - "PIPERX5STATUS1": { - "direction": "IN" - }, - "MIMTXWDATA10": { - "direction": "OUT" - }, - "DBGVECC11": { - "direction": "OUT" - }, - "CFGERRACSN": { - "direction": "IN" - }, - "PIPERX3DATA8": { - "direction": "IN" - }, - "PLDOWNSTREAMDEEMPHSOURCE": { - "direction": "IN" - }, - "DBGVECB27": { - "direction": "OUT" - }, - "CFGVENDID8": { - "direction": "IN" - }, - "PIPERX7DATA12": { - "direction": "IN" - }, - "PIPERX7POLARITY": { - "direction": "OUT" - }, - "DRPDI8": { - "direction": "IN" - }, - "DBGVECA57": { - "direction": "OUT" - }, - "MIMTXRDATA20": { - "direction": "IN" - }, - "DBGVECA27": { - "direction": "OUT" - }, - "PIPETX2DATA1": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG94": { - "direction": "IN" - }, - "DBGVECB25": { - "direction": "OUT" - }, - "PLRECEIVEDHOTRST": { - "direction": "OUT" - }, - "CFGDEVCONTROLMAXPAYLOAD0": { - "direction": "OUT" - }, - "TRNRDLLPDATA20": { - "direction": "OUT" - }, - "CFGSUBSYSID6": { - "direction": "IN" - }, - "PIPERX1CHARISK0": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG26": { - "direction": "IN" - }, - "CFGDSN12": { - "direction": "IN" - }, - "CFGMGMTDI5": { - "direction": "IN" - }, - "PIPERX0DATA4": { - "direction": "IN" - }, - "TRNTDLLPDATA31": { - "direction": "IN" - }, - "MIMRXWDATA53": { - "direction": "OUT" - }, - "CFGMGMTDO16": { - "direction": "OUT" - }, - "CFGDSN52": { - "direction": "IN" - }, - "TRNRFCPRET": { - "direction": "IN" - }, - "USERCLK2": { - "direction": "IN" - }, - "MIMRXWADDR12": { - "direction": "OUT" - }, - "MIMTXRDATA17": { - "direction": "IN" - }, - "TL2ERRHDR55": { - "direction": "OUT" - }, - "CFGMSGDATA9": { - "direction": "OUT" - }, - "TRNRDLLPDATA36": { - "direction": "OUT" - }, - "DBGVECB33": { - "direction": "OUT" - }, - "TRNTD35": { - "direction": "IN" - }, - "CFGDEVCONTROLPHANTOMEN": { - "direction": "OUT" - }, - "CFGMGMTDI31": { - "direction": "IN" - }, - "CFGMGMTBYTEENN0": { - "direction": "IN" - }, - "MIMTXWDATA17": { - "direction": "OUT" - }, - "DBGMODE1": { - "direction": "IN" - }, - "TRNFCCPLH2": { - "direction": "OUT" - }, - "DBGVECB12": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG108": { - "direction": "IN" - }, - "DRPDO10": { - "direction": "OUT" - }, - "LL2LINKSTATUS3": { - "direction": "OUT" - }, - "PL2RECEIVERERR": { - "direction": "OUT" - }, - "TRNRD90": { - "direction": "OUT" - }, - "MIMRXWDATA24": { - "direction": "OUT" - }, - "MIMRXRDATA52": { - "direction": "IN" - }, - "TRNRD48": { - "direction": "OUT" - }, - "TL2ERRMALFORMED": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG89": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG103": { - "direction": "IN" - }, - "CFGLINKCONTROLASPMCONTROL0": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG0": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG25": { - "direction": "IN" - }, - "DRPADDR5": { - "direction": "IN" - }, - "MIMTXWDATA5": { - "direction": "OUT" - }, - "TRNTD52": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG44": { - "direction": "IN" - }, - "TRNFCNPH3": { - "direction": "OUT" - }, - "CFGINTERRUPTMMENABLE0": { - "direction": "OUT" - }, - "TL2ERRHDR42": { - "direction": "OUT" - }, - "DBGVECB42": { - "direction": "OUT" - }, - "PIPETX4DATA14": { - "direction": "OUT" - }, - "MIMTXWDATA58": { - "direction": "OUT" - }, - "TRNFCNPD0": { - "direction": "OUT" - }, - "TRNRDLLPDATA39": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER38": { - "direction": "IN" - }, - "CFGMSGDATA6": { - "direction": "OUT" - }, - "CFGVENDID10": { - "direction": "IN" - }, - "PIPETX6COMPLIANCE": { - "direction": "OUT" - }, - "DBGVECC7": { - "direction": "OUT" - }, - "DBGVECB45": { - "direction": "OUT" - }, - "PIPETXRATE": { - "direction": "OUT" - }, - "CFGDSDEVICENUMBER2": { - "direction": "IN" - }, - "PIPERX1POLARITY": { - "direction": "OUT" - }, - "CFGDSN29": { - "direction": "IN" - }, - "CFGMSGRECEIVEDPMASNAK": { - "direction": "OUT" - }, - "CFGSUBSYSID7": { - "direction": "IN" - }, - "CFGPMRCVENTERL1N": { - "direction": "OUT" - }, - "TRNTD75": { - "direction": "IN" - }, - "CFGCOMMANDSERREN": { - "direction": "OUT" - }, - "CFGINTERRUPTDI2": { - "direction": "IN" - }, - "CFGMGMTDO28": { - "direction": "OUT" - }, - "MIMTXWDATA36": { - "direction": "OUT" - }, - "TRNTD127": { - "direction": "IN" - }, - "PIPETX4DATA11": { - "direction": "OUT" - }, - "MIMTXWDATA44": { - "direction": "OUT" - }, - "MIMTXRDATA7": { - "direction": "IN" - }, - "MIMTXWDATA61": { - "direction": "OUT" - }, - "DBGVECA36": { - "direction": "OUT" - }, - "TL2ERRHDR50": { - "direction": "OUT" - }, - "PIPERX4ELECIDLE": { - "direction": "IN" - }, - "MIMTXRADDR12": { - "direction": "OUT" - }, - "PIPERX5DATA6": { - "direction": "IN" - }, - "MIMRXRDATA4": { - "direction": "IN" - }, - "TRNTDLLPDATA16": { - "direction": "IN" - }, - "MIMRXWDATA56": { - "direction": "OUT" - }, - "CFGPCIECAPINTERRUPTMSGNUM1": { - "direction": "IN" - }, - "CFGDSN27": { - "direction": "IN" - }, - "TRNRBARHIT0": { - "direction": "OUT" - }, - "CFGMSGRECEIVEDDEASSERTINTA": { - "direction": "OUT" - }, - "MIMRXWDATA16": { - "direction": "OUT" - }, - "TL2ERRHDR61": { - "direction": "OUT" - }, - "PIPERX0DATA14": { - "direction": "IN" - }, - "PIPERX3DATA9": { - "direction": "IN" - }, - "EDTCHANNELSOUT5": { - "direction": "OUT" - }, - "PIPERX5CHANISALIGNED": { - "direction": "IN" - }, - "DBGSCLRD": { - "direction": "OUT" - }, - "CFGERRMCBLOCKEDN": { - "direction": "IN" - }, - "PIPERX3DATA13": { - "direction": "IN" - }, - "MIMRXRDATA24": { - "direction": "IN" - }, - "DBGVECB62": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG27": { - "direction": "IN" - }, - "CFGDSN11": { - "direction": "IN" - }, - "PIPERX4VALID": { - "direction": "IN" - }, - "PIPERX5STATUS0": { - "direction": "IN" - }, - "TRNFCCPLD1": { - "direction": "OUT" - }, - "PIPERX6DATA7": { - "direction": "IN" - }, - "PLSELLNKWIDTH1": { - "direction": "OUT" - }, - "TRNTD67": { - "direction": "IN" - }, - "MIMTXWADDR10": { - "direction": "OUT" - }, - "MIMRXRDATA15": { - "direction": "IN" - }, - "XILUNCONNOUT23": { - "direction": "OUT" - }, - "PIPETX4DATA13": { - "direction": "OUT" - }, - "CFGLINKCONTROLLINKDISABLE": { - "direction": "OUT" - }, - "TRNFCCPLH7": { - "direction": "OUT" - }, - "PIPERX6PHYSTATUS": { - "direction": "IN" - }, - "CFGSUBSYSID9": { - "direction": "IN" - }, - "XILUNCONNOUT3": { - "direction": "OUT" - }, - "PIPETX7CHARISK0": { - "direction": "OUT" - }, - "DBGVECB34": { - "direction": "OUT" - }, - "PIPETX0COMPLIANCE": { - "direction": "OUT" - }, - "PIPERX3DATA7": { - "direction": "IN" - }, - "MIMRXWDATA30": { - "direction": "OUT" - }, - "CFGDSN36": { - "direction": "IN" - }, - "MIMTXRDATA31": { - "direction": "IN" - }, - "CFGLINKCONTROLCOMMONCLOCK": { - "direction": "OUT" - }, - "PIPETX7DATA10": { - "direction": "OUT" - }, - "PLDIRECTEDLTSSMNEW4": { - "direction": "IN" - }, - "CFGERRCORN": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG6": { - "direction": "IN" - }, - "DBGSUBMODE": { - "direction": "IN" - }, - "TRNRSOF": { - "direction": "OUT" - }, - "TL2PPMSUSPENDREQ": { - "direction": "IN" - }, - "MIMRXRDATA44": { - "direction": "IN" - }, - "PIPETX1DATA4": { - "direction": "OUT" - }, - "DBGVECC3": { - "direction": "OUT" - }, - "CFGLINKCONTROLCLOCKPMEN": { - "direction": "OUT" - }, - "PIPERX6POLARITY": { - "direction": "OUT" - }, - "TL2ASPMSUSPENDCREDITCHECKOK": { - "direction": "OUT" - }, - "PIPERX4DATA8": { - "direction": "IN" - }, - "PIPETX4DATA12": { - "direction": "OUT" - }, - "MIMTXWDATA20": { - "direction": "OUT" - }, - "TRNRDLLPDATA54": { - "direction": "OUT" - }, - "FUNCLVLRSTN": { - "direction": "IN" - }, - "DBGVECC9": { - "direction": "OUT" - }, - "MIMRXRDATA43": { - "direction": "IN" - }, - "CFGDEVID10": { - "direction": "IN" - }, "CFGERRAERHEADERLOG97": { "direction": "IN" }, - "CFGDSN18": { - "direction": "IN" - }, - "TRNRD32": { - "direction": "OUT" - }, - "MIMRXWDATA29": { - "direction": "OUT" - }, - "TL2ERRHDR22": { - "direction": "OUT" - }, - "TRNTDLLPDATA3": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER19": { - "direction": "IN" - }, - "CFGMGMTDO20": { - "direction": "OUT" - }, - "PIPERX4DATA13": { - "direction": "IN" - }, - "EDTSINGLEBYPASSCHAIN": { - "direction": "IN" - }, - "PLDBGMODE1": { - "direction": "IN" - }, - "MIMRXRDATA49": { - "direction": "IN" - }, - "MIMTXRDATA48": { - "direction": "IN" - }, - "TRNRDLLPDATA37": { - "direction": "OUT" - }, - "MIMRXRDATA66": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG78": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG72": { - "direction": "IN" - }, - "MIMTXWDATA6": { - "direction": "OUT" - }, - "DRPDI14": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG82": { - "direction": "IN" - }, - "PLINITIALLINKWIDTH0": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER40": { - "direction": "IN" - }, - "EDTCHANNELSOUT4": { - "direction": "OUT" - }, - "DBGVECB35": { - "direction": "OUT" - }, - "PLDBGVEC7": { - "direction": "OUT" - }, - "MIMTXWDATA56": { - "direction": "OUT" - }, - "PIPETX2ELECIDLE": { - "direction": "OUT" - }, - "TRNFCCPLD9": { - "direction": "OUT" - }, - "TRNFCPD5": { - "direction": "OUT" - }, - "MIMRXRDATA16": { - "direction": "IN" - }, - "CFGDEVCONTROLENABLERO": { - "direction": "OUT" - }, - "TRNTD39": { - "direction": "IN" - }, - "PIPERX6DATA15": { - "direction": "IN" - }, - "PIPERX3DATA14": { - "direction": "IN" - }, - "CFGSUBSYSID14": { - "direction": "IN" - }, - "TRNFCNPD9": { - "direction": "OUT" - }, - "CFGDSN39": { - "direction": "IN" - }, - "CFGAERECRCCHECKEN": { - "direction": "OUT" - }, - "DBGVECA48": { - "direction": "OUT" - }, - "PIPETX2COMPLIANCE": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG107": { - "direction": "IN" - }, - "TRNRD35": { - "direction": "OUT" - }, - "MIMTXWADDR9": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER10": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER9": { - "direction": "IN" - }, - "PIPETX3DATA11": { - "direction": "OUT" - }, - "PIPETX0POWERDOWN0": { - "direction": "OUT" - }, - "MIMTXWDATA31": { - "direction": "OUT" - }, - "CFGVCTCVCMAP2": { - "direction": "OUT" - }, - "PIPERX1DATA3": { - "direction": "IN" - }, - "CFGMGMTDI26": { - "direction": "IN" - }, - "TL2ERRHDR45": { - "direction": "OUT" - }, - "TRNRDLLPDATA34": { - "direction": "OUT" - }, - "CFGSUBSYSVENDID8": { - "direction": "IN" - }, - "CFGERRAERHEADERLOGSETN": { - "direction": "OUT" - }, - "MIMRXWDATA45": { - "direction": "OUT" - }, - "TRNTD83": { - "direction": "IN" - }, - "PIPETX3COMPLIANCE": { - "direction": "OUT" - }, - "TRNTBUFAV4": { - "direction": "OUT" - }, - "LL2BADTLPERR": { - "direction": "OUT" - }, - "PLDBGVEC10": { - "direction": "OUT" - }, - "TRNRD36": { - "direction": "OUT" - }, - "PIPETX7CHARISK1": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG106": { - "direction": "IN" - }, - "EDTCHANNELSOUT3": { - "direction": "OUT" - }, - "TRNRD14": { - "direction": "OUT" - }, - "TL2ERRHDR32": { - "direction": "OUT" - }, - "MIMRXWDATA48": { - "direction": "OUT" - }, - "TRNRD18": { - "direction": "OUT" - }, - "TRNTD20": { - "direction": "IN" - }, - "DBGVECB4": { - "direction": "OUT" - }, - "CFGSUBSYSID1": { - "direction": "IN" - }, - "PIPERX4STATUS2": { - "direction": "IN" - }, - "DRPDO0": { - "direction": "OUT" - }, - "PIPETX4DATA10": { - "direction": "OUT" - }, - "TL2ERRHDR36": { - "direction": "OUT" - }, - "TRNRD34": { - "direction": "OUT" - }, - "CFGTRANSACTIONADDR1": { - "direction": "OUT" - }, - "MIMTXWDATA54": { - "direction": "OUT" - }, - "PIPERX2DATA12": { - "direction": "IN" - }, - "CFGPMFORCESTATE1": { - "direction": "IN" - }, - "DBGVECB18": { - "direction": "OUT" - }, - "PLPHYLNKUPN": { - "direction": "OUT" - }, - "MIMTXWDATA41": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG91": { - "direction": "IN" - }, - "TRNRREM0": { - "direction": "OUT" - }, - "DBGVECA9": { - "direction": "OUT" - }, - "DRPADDR3": { - "direction": "IN" - }, - "CFGDSN49": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER25": { - "direction": "IN" - }, - "TRNRD98": { - "direction": "OUT" - }, - "DBGVECA30": { - "direction": "OUT" - }, - "TL2ERRHDR13": { - "direction": "OUT" - }, - "PIPETX4DATA0": { - "direction": "OUT" - }, - "MIMTXWDATA3": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG13": { - "direction": "IN" - }, - "CFGDEVCONTROL2ATOMICREQUESTEREN": { - "direction": "OUT" - }, - "PIPERX7DATA2": { - "direction": "IN" - }, - "MIMRXWDATA6": { - "direction": "OUT" - }, - "PIPETX0DATA5": { - "direction": "OUT" - }, - "DBGVECB41": { - "direction": "OUT" - }, - "PIPERX1STATUS0": { - "direction": "IN" - }, - "PIPERX5DATA15": { - "direction": "IN" - }, - "PIPETX6DATA1": { - "direction": "OUT" - }, - "CFGINTERRUPTMMENABLE1": { - "direction": "OUT" - }, - "DRPEN": { - "direction": "IN" - }, - "PIPETX2DATA10": { - "direction": "OUT" - }, - "MIMTXWDATA62": { - "direction": "OUT" - }, - "TRNFCCPLD0": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG30": { - "direction": "IN" - }, - "TL2ERRHDR25": { - "direction": "OUT" - }, - "MIMRXWDATA41": { - "direction": "OUT" - }, - "CFGAERROOTERRNONFATALERRRECEIVED": { - "direction": "OUT" - }, - "MIMRXWDATA4": { - "direction": "OUT" - }, - "PIPETX0ELECIDLE": { - "direction": "OUT" - }, - "CFGPORTNUMBER4": { - "direction": "IN" - }, - "TRNTDLLPDATA1": { - "direction": "IN" - }, - "CFGDEVSTATUSURDETECTED": { - "direction": "OUT" - }, - "TRNTDLLPDATA12": { - "direction": "IN" - }, - "TRNTD126": { - "direction": "IN" - }, - "CFGDEVCONTROL2ATOMICEGRESSBLOCK": { - "direction": "OUT" - }, - "MIMTXRDATA32": { - "direction": "IN" - }, - "CFGAERROOTERRNONFATALERRREPORTINGEN": { - "direction": "OUT" - }, - "MIMTXRDATA26": { - "direction": "IN" - }, - "PIPETX3POWERDOWN0": { - "direction": "OUT" - }, - "DRPDO11": { - "direction": "OUT" - }, - "DBGVECA38": { - "direction": "OUT" - }, - "CFGPCIECAPINTERRUPTMSGNUM0": { - "direction": "IN" - }, - "MIMTXRDATA53": { - "direction": "IN" - }, - "PIPETX4DATA7": { - "direction": "OUT" - }, - "MIMTXRDATA47": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG8": { - "direction": "IN" - }, - "CFGCOMMANDINTERRUPTDISABLE": { - "direction": "OUT" - }, - "TRNTDLLPDATA13": { - "direction": "IN" - }, - "TRNTD90": { - "direction": "IN" - }, - "TRNFCCPLD5": { - "direction": "OUT" - }, - "PLRSTN": { - "direction": "IN" - }, - "TRNFCPD9": { - "direction": "OUT" - }, - "TL2ERRHDR59": { - "direction": "OUT" - }, - "CFGSUBSYSVENDID1": { - "direction": "IN" - }, - "MIMTXRDATA29": { - "direction": "IN" - }, - "PIPERX6DATA0": { - "direction": "IN" - }, - "PIPERX5DATA0": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER43": { - "direction": "IN" - }, - "MIMRXWDATA10": { - "direction": "OUT" - }, - "PLDBGVEC6": { - "direction": "OUT" - }, - "TL2ERRHDR53": { - "direction": "OUT" - }, - "LL2SENDENTERL1": { - "direction": "IN" - }, - "DBGSCLRK": { - "direction": "OUT" - }, - "MIMRXRDATA57": { - "direction": "IN" - }, - "CFGLINKCONTROLASPMCONTROL1": { - "direction": "OUT" - }, - "TRNRDLLPDATA29": { + "MIMRXWADDR5": { "direction": "OUT" }, - "TRNFCPD0": { + "XILUNCONNOUT6": { "direction": "OUT" }, - "CFGTRNPENDINGN": { + "TRNTSRCDSC": { "direction": "IN" }, - "PIPECLK": { - "direction": "IN" - }, - "DRPDO9": { - "direction": "OUT" - }, - "PIPERX2DATA11": { - "direction": "IN" - }, - "PIPERX7CHARISK0": { - "direction": "IN" - }, - "TRNRD15": { - "direction": "OUT" - }, - "PLDIRECTEDLTSSMSTALL": { - "direction": "IN" - }, - "TRNTD24": { - "direction": "IN" - }, - "TRNRDLLPDATA0": { - "direction": "OUT" - }, - "DBGVECA0": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER3": { - "direction": "IN" - }, - "CFGSUBSYSID10": { - "direction": "IN" - }, - "PIPETX7DATA9": { - "direction": "OUT" - }, - "XILUNCONNOUT39": { - "direction": "OUT" - }, - "MIMRXRADDR0": { - "direction": "OUT" - }, - "TRNTD62": { - "direction": "IN" - }, - "MIMRXWDATA7": { - "direction": "OUT" - }, - "MIMTXRDATA65": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG52": { - "direction": "IN" - }, - "MIMTXWDATA51": { - "direction": "OUT" - }, - "PIPERX1VALID": { - "direction": "IN" - }, - "TRNTD9": { - "direction": "IN" - }, - "MIMRXWDATA38": { - "direction": "OUT" - }, - "TRNTDLLPDATA21": { - "direction": "IN" - }, - "CFGDSN28": { - "direction": "IN" - }, - "TRNTD44": { - "direction": "IN" - }, - "TRNFCNPH4": { - "direction": "OUT" - }, - "PIPERX1DATA11": { - "direction": "IN" - }, - "PLINITIALLINKWIDTH2": { - "direction": "OUT" - }, - "CFGERRMALFORMEDN": { - "direction": "IN" - }, - "CFGVCTCVCMAP3": { - "direction": "OUT" - }, - "TRNTD109": { - "direction": "IN" - }, - "TRNRD72": { - "direction": "OUT" - }, - "CFGLINKSTATUSNEGOTIATEDWIDTH2": { - "direction": "OUT" - }, - "PIPERX7CHARISK1": { - "direction": "IN" - }, - "CFGINTERRUPTDI1": { - "direction": "IN" - }, - "DRPDI1": { - "direction": "IN" - }, - "CFGDEVCONTROLMAXPAYLOAD1": { - "direction": "OUT" - }, - "CFGAERINTERRUPTMSGNUM4": { - "direction": "IN" - }, - "TRNRD0": { - "direction": "OUT" - }, - "TRNTDLLPDATA28": { - "direction": "IN" - }, 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"direction": "OUT" - }, - "PIPETX0DATA4": { - "direction": "OUT" - }, - "DRPADDR6": { - "direction": "IN" - }, - "TRNTD51": { - "direction": "IN" - }, - "TRNFCCPLD11": { - "direction": "OUT" - }, - "TRNRD7": { - "direction": "OUT" - }, - "TRNTD55": { - "direction": "IN" - }, - "CFGREVID1": { - "direction": "IN" - }, - "LL2BADDLLPERR": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG65": { - "direction": "IN" - }, - "CFGDEVID13": { - "direction": "IN" - }, - "TRNFCNPH2": { - "direction": "OUT" - }, - "MIMTXWDATA1": { - "direction": "OUT" - }, - "PIPETX2DATA6": { - "direction": "OUT" - }, - "DBGVECA56": { - "direction": "OUT" - }, - "TRNRD23": { - "direction": "OUT" - }, - "PIPERX0DATA5": { - "direction": "IN" - }, - "DBGVECB52": { - "direction": "OUT" - }, - "XILUNCONNOUT34": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER33": { - "direction": "IN" - }, - "PIPETX3DATA8": { - "direction": "OUT" - }, - "PIPETX2DATA8": { - "direction": "OUT" - }, - "CFGFORCEMPS0": { - "direction": "IN" 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}, - "TRNFCCPLH0": { - "direction": "OUT" - }, - "TRNRDLLPDATA14": { - "direction": "OUT" - }, - "DRPDI11": { - "direction": "IN" - }, - "TL2ERRHDR12": { - "direction": "OUT" - }, - "MIMRXRDATA30": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG46": { - "direction": "IN" - }, - "PIPETX6DATA11": { - "direction": "OUT" - }, - "CFGDSN54": { - "direction": "IN" - }, - "TL2ERRHDR9": { - "direction": "OUT" - }, - "PIPERX1DATA9": { - "direction": "IN" - }, - "CFGDEVCONTROLURERRREPORTINGEN": { - "direction": "OUT" - }, - "TRNRD87": { - "direction": "OUT" - }, - "CFGDSN8": { - "direction": "IN" - }, - "PIPETX1DATA2": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER27": { - "direction": "IN" - }, - "MIMRXWDATA65": { - "direction": "OUT" - }, - "USERRSTN": { - "direction": "OUT" - }, - "PIPERX5DATA10": { - "direction": "IN" - }, - "MIMTXWDATA48": { - "direction": "OUT" - }, - "PMVDIVIDE1": { - "direction": "IN" - }, - "DBGVECB61": { - "direction": "OUT" - }, - "CFGVCTCVCMAP6": { - "direction": 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"direction": "OUT" - }, - "TRNRD109": { - "direction": "OUT" - }, - "TRNFCNPH6": { - "direction": "OUT" - }, - "CFGAERROOTERRFATALERRREPORTINGEN": { - "direction": "OUT" - }, - "TRNRD79": { - "direction": "OUT" - }, - "DBGVECB7": { - "direction": "OUT" - }, - "MIMTXRDATA9": { - "direction": "IN" - }, - "TL2ERRHDR17": { - "direction": "OUT" - }, - "CFGMGMTDWADDR4": { - "direction": "IN" - }, - "DBGVECA51": { - "direction": "OUT" - }, - "CFGVENDID7": { - "direction": "IN" - }, - "TRNRD66": { - "direction": "OUT" - }, - "MIMTXRDATA33": { - "direction": "IN" - }, - "TRNRDLLPDATA18": { - "direction": "OUT" - }, - "CFGDEVID0": { - "direction": "IN" - }, - "PIPETX1DATA9": { - "direction": "OUT" - }, - "MIMTXRDATA55": { - "direction": "IN" - }, - "MIMRXWADDR10": { - "direction": "OUT" - }, - "CFGVENDID11": { - "direction": "IN" - }, - "CFGMGMTDWADDR1": { - "direction": "IN" - }, - "DRPDO6": { - "direction": "OUT" - }, - "EDTCHANNELSIN2": { - "direction": "IN" - }, - "CFGDSN6": { - "direction": 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- }, - "CFGMSGRECEIVEDASSERTINTD": { - "direction": "OUT" - }, - "CFGDEVCONTROL2CPLTIMEOUTVAL1": { - "direction": "OUT" - }, - "TL2ERRHDR29": { - "direction": "OUT" - }, - "TRNTD58": { - "direction": "IN" - }, - "TRNRD29": { - "direction": "OUT" - }, - "PIPERX2DATA2": { - "direction": "IN" - }, - "TRNRDLLPDATA28": { - "direction": "OUT" - }, - "CFGMGMTDO18": { - "direction": "OUT" - }, - "CFGSUBSYSVENDID7": { - "direction": "IN" - }, - "TL2ERRHDR58": { - "direction": "OUT" - }, - "PIPETX4DATA6": { - "direction": "OUT" - }, - "TRNRDLLPDATA53": { - "direction": "OUT" - }, - "CFGDSBUSNUMBER0": { - "direction": "IN" - }, - "MIMRXRDATA50": { - "direction": "IN" - }, - "CFGMGMTDO26": { - "direction": "OUT" - }, - "CFGVENDID14": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG119": { - "direction": "IN" - }, - "DBGSCLRF": { - "direction": "OUT" - }, - "PIPERX4CHARISK1": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG66": { - "direction": "IN" - }, - "PIPETX1DATA5": { - "direction": "OUT" - }, - "PIPERX0STATUS0": { - "direction": "IN" - }, - "CFGINTERRUPTDO4": { - "direction": "OUT" - }, - "MIMRXRDATA17": { - "direction": "IN" - }, - "PIPERX6DATA4": { - "direction": "IN" - }, - "MIMRXWADDR1": { - "direction": "OUT" - }, - "CFGMSGDATA1": { - "direction": "OUT" - }, - "CFGMGMTDI25": { - "direction": "IN" - }, - "DBGVECC6": { - "direction": "OUT" - }, - "TRNRD102": { - "direction": "OUT" - }, - "TRNTSTR": { - "direction": "IN" - }, - "DBGVECA35": { - "direction": "OUT" - }, - "TL2ERRHDR54": { - "direction": "OUT" - }, - "CFGDSN46": { - "direction": "IN" - }, - "TRNTD29": { - "direction": "IN" - }, - "DBGVECA45": { - "direction": "OUT" - }, - "TRNRD112": { - "direction": "OUT" - }, - "MIMTXRDATA67": { - "direction": "IN" - }, - "MIMRXWDATA26": { - "direction": "OUT" - }, - "CFGMSGDATA7": { - "direction": "OUT" - }, - "DRPDI12": { - "direction": "IN" - }, - "CFGMGMTDI0": { - "direction": "IN" - }, - "CFGDSN31": { - "direction": "IN" - }, - "CFGLINKCONTROLAUTOBANDWIDTHINTEN": { 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"direction": "IN" - }, - "TRNTD23": { - "direction": "IN" - }, - "TRNREOF": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG10": { - "direction": "IN" - }, - "TRNTSRCDSC": { - "direction": "IN" - }, - "XILUNCONNOUT17": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER39": { - "direction": "IN" - }, - "CFGTRANSACTIONADDR6": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG121": { - "direction": "IN" - }, - "TRNTDLLPDATA2": { - "direction": "IN" - }, - "PLDIRECTEDLINKWIDTH0": { - "direction": "IN" - }, - "PIPERX1STATUS1": { - "direction": "IN" - }, - "CFGMSGDATA15": { - "direction": "OUT" - }, - "CFGROOTCONTROLPMEINTEN": { - "direction": "OUT" - }, - "DBGVECB57": { - "direction": "OUT" - }, - "CFGDSBUSNUMBER1": { - "direction": "IN" - }, - "TRNRDLLPDATA31": { - "direction": "OUT" - }, - "EDTBYPASS": { - "direction": "IN" - }, - "TRNRD115": { - "direction": "OUT" - }, - "PIPERX3DATA4": { - "direction": "IN" - }, - "DBGVECB53": { - "direction": "OUT" - }, - "TL2ERRHDR15": { - "direction": "OUT" - }, - "CFGMGMTDWADDR6": { - "direction": "IN" - }, - "CFGREVID7": { - "direction": "IN" - }, - "PIPETX3DATA4": { - "direction": "OUT" - }, - "CFGMSGRECEIVEDASSERTINTB": { - "direction": "OUT" - }, - "TRNRD21": { - "direction": "OUT" - }, - "TRNRDLLPDATA51": { - "direction": "OUT" - }, - "TRNTD36": { - "direction": "IN" - }, - "CFGDSN53": { - "direction": "IN" - }, - "PLLTSSMSTATE4": { - "direction": "OUT" - }, - "CFGMGMTDWADDR8": { - "direction": "IN" - }, - "CFGSUBSYSVENDID4": { - "direction": "IN" - }, - "PIPETX2DATA11": { - "direction": "OUT" - }, - "PIPETX4CHARISK0": { - "direction": "OUT" - }, - "TRNRD78": { - "direction": "OUT" - }, - "LL2TXIDLE": { - "direction": "OUT" - }, - "PIPERX5DATA14": { - "direction": "IN" - }, - "CFGVENDID1": { - "direction": "IN" - }, - "DBGVECB16": { - "direction": "OUT" - }, - "TRNRDLLPDATA47": { - "direction": "OUT" - }, - "DBGVECA63": { - "direction": "OUT" - }, - "CFGSUBSYSID3": { - "direction": "IN" - }, - "TRNRD125": { - "direction": "OUT" - }, - "MIMTXRDATA46": { - "direction": "IN" - }, - "TRNTD34": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG112": { - "direction": "IN" - }, - "CFGINTERRUPTDI5": { - "direction": "IN" - }, - "PL2RECOVERY": { - "direction": "OUT" - }, - "TRNRD71": { - "direction": "OUT" - }, - "TRNRDLLPDATA15": { - "direction": "OUT" - }, - "PLUPSTREAMPREFERDEEMPH": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG43": { - "direction": "IN" - }, - "MIMTXWDATA30": { - "direction": "OUT" - }, - "CFGDEVCONTROL2CPLTIMEOUTDIS": { - "direction": "OUT" - }, - "TRNRD97": { - "direction": "OUT" - }, - "PIPERX0DATA15": { - "direction": "IN" - }, - "XILUNCONNOUT38": { - "direction": "OUT" - }, "CFGERRTLPCPLHEADER42": { "direction": "IN" }, - "PIPETX3DATA1": { + "PIPETX6CHARISK0": { "direction": "OUT" }, - "MIMRXRDATA8": { + "DBGVECC6": { + "direction": "OUT" + }, + "PIPETXMARGIN0": { + "direction": "OUT" + }, + "TRNRD1": { + "direction": "OUT" + }, + "CFGPMWAKEN": { "direction": "IN" }, - "PLDIRECTEDLTSSMNEW3": { + "TRNFCNPH0": { + "direction": "OUT" + }, + "DBGVECB18": { + "direction": "OUT" + }, + "CFGINTERRUPTDO0": { + "direction": "OUT" + }, + "TL2ERRHDR7": { + "direction": "OUT" + }, + "TRNRDLLPDATA5": { + "direction": "OUT" + }, + "MIMTXRDATA37": { "direction": "IN" }, - "MIMRXWDATA37": { + "MIMTXWDATA68": { "direction": "OUT" }, - "CFGERRAERHEADERLOG77": { + "MIMTXWDATA20": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG65": { "direction": "IN" }, - "TRNRDLLPDATA12": { + "CFGPMRCVENTERL1N": { "direction": "OUT" }, - "CFGPMCSRPOWERSTATE1": { + "DBGVECB49": { "direction": "OUT" }, - "DBGVECA3": { - "direction": "OUT" - }, - "TRNTD80": { - "direction": "IN" - }, - "TRNRDLLPDATA10": { - "direction": "OUT" - }, - "CFGDEVID5": { - "direction": "IN" - }, - "CFGSUBSYSVENDID13": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG100": { - "direction": "IN" - }, - "PIPERX4STATUS0": { - "direction": "IN" - }, - "CFGMGMTDO24": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG21": { - "direction": "IN" - }, - "PIPETX1DATA7": { - "direction": "OUT" - }, - "CFGINTERRUPTDI0": { - "direction": "IN" - }, - "TRNFCCPLH1": { - "direction": "OUT" - }, - "CFGTRANSACTION": { - "direction": "OUT" - }, - "CFGSUBSYSID4": { - "direction": "IN" - }, - "TRNRD85": { - "direction": "OUT" - }, - "MIMRXWDATA55": { - "direction": "OUT" - }, - "PIPERX1DATA1": { - "direction": "IN" - }, - "MIMTXRDATA18": { - "direction": "IN" - }, - "TL2ERRHDR27": { - "direction": "OUT" - }, - "TRNRD86": { - "direction": "OUT" - }, - "CFGVENDID5": { - "direction": "IN" - }, - "PIPETX1DATA14": { - "direction": "OUT" - }, - "TL2ERRHDR33": { - "direction": "OUT" - }, - "DBGVECB30": { - "direction": "OUT" - }, - "PIPERX2DATA5": { - "direction": "IN" - }, - "TL2ERRHDR46": { - "direction": "OUT" - }, - "CFGERRCPLUNEXPECTN": { - "direction": "IN" - }, - "DBGVECB44": { - "direction": "OUT" - }, - "MIMTXRDATA54": { - "direction": "IN" - }, - "PIPETX1DATA3": { - "direction": "OUT" - }, - "TRNTD86": { - "direction": "IN" - }, - "TL2ERRHDR57": { - "direction": "OUT" - }, - "PIPETX3DATA10": { - "direction": "OUT" - }, - "CFGDEVCONTROL2CPLTIMEOUTVAL0": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER20": { + "LL2SENDENTERL23": { "direction": "IN" }, "PIPERX6DATA13": { "direction": "IN" }, - "PIPERX2DATA13": { - "direction": "IN" - }, - "MIMTXWDATA37": { + "PIPETX5POWERDOWN0": { "direction": "OUT" }, - "CFGERRAERHEADERLOG15": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG117": { - "direction": "IN" - }, - "CFGSUBSYSVENDID6": { - "direction": "IN" - }, - "TRNRDLLPDATA5": { + "TRNFCPH6": { "direction": "OUT" }, - "DRPDI2": { - "direction": "IN" - }, - "PIPERX1DATA8": { - "direction": "IN" - }, - "CFGDSN16": { - "direction": "IN" - }, - "DBGVECA55": { - "direction": "OUT" - }, - "PLDIRECTEDLTSSMNEW0": { - "direction": "IN" - }, - "MIMTXWDATA63": { - "direction": "OUT" - }, - "MIMTXWADDR0": { - "direction": "OUT" - }, - "EDTCHANNELSIN1": { - "direction": "IN" - }, - "TRNRD120": { - "direction": "OUT" - }, - "CFGERRURN": { - "direction": "IN" - }, - "PLLINKUPCFGCAP": { - "direction": "OUT" - }, - "PIPERX0CHARISK0": { - "direction": "IN" - }, - "CFGDEVCONTROLNOSNOOPEN": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER47": { - "direction": "IN" - }, - "CFGVENDID13": { - "direction": "IN" - }, - "XILUNCONNOUT0": { + "TRNTCFGREQ": { "direction": "OUT" }, - "MIMRXRDATA56": { - "direction": "IN" - }, - "MIMRXRDATA21": { - "direction": "IN" - }, - "PLTRANSMITHOTRST": { - "direction": "IN" - }, - "CFGERRATOMICEGRESSBLOCKEDN": { - "direction": "IN" - }, - "PIPETX6DATA4": { - "direction": "OUT" - }, - "MIMTXRDATA35": { - "direction": "IN" - }, - "PIPETX7DATA3": { - "direction": "OUT" - }, - "CFGMGMTWRREADONLYN": { - "direction": "IN" - }, - "CFGDSN60": { - "direction": "IN" - }, - "TRNRDLLPSRCRDY0": { - "direction": "OUT" - }, - "TRNRD74": { - "direction": "OUT" - }, - "PIPETX0DATA15": { - "direction": "OUT" - }, - "DBGVECA43": { - "direction": "OUT" - }, - "TRNTDSTRDY1": { - "direction": "OUT" - }, - "TRNRDLLPDATA1": { - "direction": "OUT" - }, - "CFGDSN3": { - "direction": "IN" - }, - "PIPETX6POWERDOWN0": { - "direction": "OUT" - }, - "PIPERX6CHANISALIGNED": { - "direction": "IN" - }, - "LL2TLPRCV": { - "direction": "IN" - }, - "TRNTD121": { - "direction": "IN" - }, - "PIPERX1DATA14": { - "direction": "IN" - }, - "PIPETX6DATA12": { - "direction": "OUT" - }, - "CFGERRECRCN": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG73": { - "direction": "IN" - }, - "MIMRXRDATA46": { - "direction": "IN" - }, - "TL2ERRHDR30": { - "direction": "OUT" - }, - "CFGLINKCONTROLBANDWIDTHINTEN": { - "direction": "OUT" - }, - "CFGDSN61": { - "direction": "IN" - }, - "TRNTD79": { - "direction": "IN" - }, - "TRNRD25": { - "direction": "OUT" - }, - "TRNFCNPH7": { - "direction": "OUT" - }, - "DBGVECB1": { - "direction": "OUT" - }, - "PIPERX1DATA10": { - "direction": "IN" - }, - "TRNRD41": { - "direction": "OUT" - }, - "PIPETX2DATA3": { - "direction": "OUT" - }, - "PIPETX5CHARISK1": { - "direction": "OUT" - }, - "PIPETX5DATA11": { - "direction": "OUT" - }, - "TRNRD107": { - "direction": "OUT" - }, - "TRNFCCPLD10": { - "direction": "OUT" - }, - "EDTCHANNELSOUT1": { - "direction": "OUT" - }, - "CFGVCTCVCMAP1": { - "direction": "OUT" - }, - "DBGVECA16": { - "direction": "OUT" - }, - "PIPETX5DATA5": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG40": { - "direction": "IN" - }, - "CFGDEVCONTROLNONFATALREPORTINGEN": { - "direction": "OUT" - }, - "TRNTD124": { - "direction": "IN" - }, - "DRPDO13": { - "direction": "OUT" - }, - "MIMRXWADDR9": { - "direction": "OUT" - }, - "TRNRD64": { - "direction": "OUT" - }, - "CFGERRINTERNALUNCORN": { - "direction": "IN" - }, - "TRNTD87": { - "direction": "IN" - }, - "PIPERX6DATA14": { - "direction": "IN" - }, - "PIPETX6DATA0": { - "direction": "OUT" - }, - "MIMTXRDATA0": { - "direction": "IN" - }, - "CFGMGMTDWADDR7": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG17": { - "direction": "IN" - }, - "PLLTSSMSTATE1": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER31": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG87": { - "direction": "IN" - }, - "DBGVECA61": { - "direction": "OUT" - }, - "PIPERX7VALID": { - "direction": "IN" - }, - "TRNTDLLPDATA23": { - "direction": "IN" - }, - "MIMTXRDATA43": { - "direction": "IN" - }, - "PIPETX0DATA2": { - "direction": "OUT" - }, - "MIMRXWDATA0": { - "direction": "OUT" - }, - "TRNRD59": { - "direction": "OUT" - }, - "MIMTXWDATA32": { - "direction": "OUT" - }, - "XILUNCONNOUT14": { - "direction": "OUT" - }, - "CFGPCIELINKSTATE2": { - "direction": "OUT" - }, - "TRNRD42": { - "direction": "OUT" - }, - "CFGMGMTDO31": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG4": { - "direction": "IN" - }, - "CFGLINKSTATUSNEGOTIATEDWIDTH0": { - "direction": "OUT" - }, - "CFGSUBSYSID0": { - "direction": "IN" - }, - "CFGMGMTDO29": { - "direction": "OUT" - }, - "PIPERX1DATA15": { - "direction": "IN" - }, - "PIPETX1POWERDOWN0": { - "direction": "OUT" - }, - "CFGVENDID3": { - "direction": "IN" - }, - "TRNTDLLPDATA25": { - "direction": "IN" - }, - "PIPERX2STATUS2": { - "direction": "IN" - }, - "PIPERX7DATA7": { - "direction": "IN" - }, - "PIPETX7DATA7": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG37": { - "direction": "IN" - }, - "PIPETX6CHARISK1": { - "direction": "OUT" - }, - "PIPERX7DATA8": { - "direction": "IN" - }, - "PIPETX4DATA1": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG42": { - "direction": "IN" - }, - "PIPERX4DATA4": { - "direction": "IN" - }, - "CFGDSN0": { - "direction": "IN" - }, - "XILUNCONNOUT8": { - "direction": "OUT" - }, - "TRNRD92": { - "direction": "OUT" - }, - "TRNFCPD8": { - "direction": "OUT" - }, - "TRNFCNPD5": { - "direction": "OUT" - }, - "PIPERX6STATUS2": { - "direction": "IN" - }, - "PIPERX5DATA13": { - "direction": "IN" - }, - "TL2ERRFCPE": { - "direction": "OUT" - }, - "MIMTXRDATA50": { - "direction": "IN" - }, - "CFGMGMTDO17": { - "direction": "OUT" - }, - "MIMTXWADDR1": { - "direction": "OUT" - }, - "TRNRSRCRDY": { - "direction": "OUT" - }, - "PIPETX3DATA9": { - "direction": "OUT" - }, - "CFGINTERRUPTDI6": { - "direction": "IN" - }, - "TRNTD47": { - "direction": "IN" - }, - "PIPETX1DATA1": { - "direction": "OUT" - }, - "DBGVECA26": { - "direction": "OUT" - }, - "TRNRDLLPDATA11": { - "direction": "OUT" - }, - "CFGMGMTDO10": { - "direction": "OUT" - }, - "PIPERX5STATUS2": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG50": { - "direction": "IN" - }, - "PIPETX6POWERDOWN1": { + "TRNTDSTRDY3": { "direction": "OUT" }, "CFGDSN17": { "direction": "IN" }, - "XILUNCONNOUT30": { - "direction": "OUT" - }, - "LL2TFCINIT1SEQ": { - "direction": "OUT" - }, - "CFGDSN13": { + "LL2SUSPENDNOW": { "direction": "IN" }, - "PMVDIVIDE0": { + "PIPETXRESET": { + "direction": "OUT" + }, + "CFGERRURN": { "direction": "IN" }, - "PIPERX4DATA12": { + "TRNRD16": { + "direction": "OUT" + }, + "MIMTXWDATA16": { + "direction": "OUT" + }, + "CFGDSN26": { "direction": "IN" }, - "MIMTXWDATA34": { + "PIPETX4DATA3": { "direction": "OUT" }, - "CFGERRAERHEADERLOG74": { + "XILUNCONNOUT15": { + "direction": "OUT" + }, + "CFGDEVCONTROLMAXPAYLOAD2": { + "direction": "OUT" + }, + "CFGVENDID9": { "direction": "IN" }, - "MIMTXWDATA33": { + "MIMTXWDATA11": { "direction": "OUT" }, - "TRNTDLLPDATA6": { + "TRNRDLLPDATA16": { + "direction": "OUT" + }, + "MIMRXWDATA38": { + "direction": "OUT" + }, + "PIPERX1DATA15": { "direction": "IN" }, - "EDTCHANNELSOUT8": { + "MIMTXWDATA19": { "direction": "OUT" }, - "TRNTD68": { + "TRNFCCPLD3": { + "direction": "OUT" + }, + "PIPERX7CHARISK1": { "direction": "IN" }, - "DBGVECA33": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG33": { + "CFGMGMTDI28": { "direction": "IN" }, - "TRNTDLLPDATA15": { + "CFGDEVID7": { "direction": "IN" }, - "CFGINTERRUPTMSIXENABLE": { - "direction": "OUT" - }, - "MIMRXRADDR1": { - "direction": "OUT" - }, - "CFGDSN55": { + "PMVDIVIDE1": { "direction": "IN" }, - "TRNFCPH1": { + "DBGSCLRI": { "direction": "OUT" }, - "CFGDSN23": { + "CFGMGMTDWADDR9": { "direction": "IN" }, - "PIPETX3DATA14": { - "direction": "OUT" - }, - "MIMRXWDATA57": { - "direction": "OUT" - }, - "PIPERX0POLARITY": { - "direction": "OUT" - }, - "PIPERX4DATA11": { + "CFGMGMTDWADDR6": { "direction": "IN" }, - "CFGERRAERHEADERLOG92": { + "CFGERRINTERNALCORN": { "direction": "IN" }, - "MIMTXWDATA0": { + "TRNTDSTRDY2": { "direction": "OUT" }, - "XILUNCONNOUT16": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG47": { + "CFGERRAERHEADERLOG125": { "direction": "IN" }, - "PIPETX7DATA1": { - "direction": "OUT" - }, - "TRNRD37": { - "direction": "OUT" - }, - "TRNTD37": { + "CFGPORTNUMBER0": { "direction": "IN" }, - "MIMTXWDATA29": { - "direction": "OUT" - }, - "CFGDEVID6": { + "CFGREVID2": { "direction": "IN" }, - "CFGMGMTDO27": { + "CFGTRANSACTIONTYPE": { "direction": "OUT" }, - "PIPETX6DATA14": { + "TRNFCCPLD11": { "direction": "OUT" }, - "CFGMGMTDI18": { + "PIPERX0DATA7": { "direction": "IN" }, - "MIMTXRDATA10": { - "direction": "IN" - }, - "MIMTXWDATA40": { + "MIMTXRADDR4": { "direction": "OUT" }, - "CFGMGMTDO15": { + "DBGVECA48": { "direction": "OUT" }, - "CFGDSN44": { - "direction": "IN" - }, - "DBGVECA6": { - "direction": "OUT" - }, - "MIMRXREN": { - "direction": "OUT" - }, - "MIMRXWADDR0": { - "direction": "OUT" - }, - "CFGDEVID3": { - "direction": "IN" - }, - "CFGMSGDATA0": { - "direction": "OUT" - }, - "PMVSELECT2": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG102": { - "direction": "IN" - }, - "TL2ERRHDR31": { - "direction": "OUT" - }, - "PIPETX7DATA14": { - "direction": "OUT" - }, - "CFGSLOTCONTROLELECTROMECHILCTLPULSE": { - "direction": "OUT" - }, - "TRNTDLLPDATA18": { - "direction": "IN" - }, - "MIMRXRDATA34": { - "direction": "IN" - }, - "PIPERX2DATA14": { - "direction": "IN" - }, - "MIMRXRDATA33": { - "direction": "IN" - }, - "TRNTD98": { - "direction": "IN" - }, "CFGSUBSYSVENDID5": { "direction": "IN" }, + "TRNTDLLPDATA12": { + "direction": "IN" + }, + "MIMTXRDATA20": { + "direction": "IN" + }, + "DBGVECB50": { + "direction": "OUT" + }, + "PIPERX2DATA7": { + "direction": "IN" + }, + "TRNTDLLPDATA4": { + "direction": "IN" + }, + "CFGMGMTWRREADONLYN": { + "direction": "IN" + }, + "CFGDEVCONTROLURERRREPORTINGEN": { + "direction": "OUT" + }, + "DRPEN": { + "direction": "IN" + }, + "TRNTD102": { + "direction": "IN" + }, + "PIPETX7DATA12": { + "direction": "OUT" + }, + "PIPERX7DATA7": { + "direction": "IN" + }, + "TRNRD106": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG2": { + "direction": "IN" + }, "TRNFCNPH5": { "direction": "OUT" }, - "DBGVECB20": { + "TRNTD41": { + "direction": "IN" + }, + "LNKCLKEN": { "direction": "OUT" }, - "CFGDEVID1": { - "direction": "IN" - }, - "SYSRSTN": { - "direction": "IN" - }, - "TRNRD4": { + "DRPDO9": { "direction": "OUT" }, - "CFGERRAERHEADERLOG96": { - "direction": "IN" - }, - "CFGROOTCONTROLSYSERRFATALERREN": { + "PIPETX1DATA10": { "direction": "OUT" }, - "PIPERX2DATA9": { - "direction": "IN" - }, - "MIMRXWDATA31": { + "PLLTSSMSTATE1": { "direction": "OUT" }, - "CFGMGMTDI3": { - "direction": "IN" - }, - "PIPERX4PHYSTATUS": { - "direction": "IN" - }, - "TRNTERRDROP": { + "CFGINTERRUPTMMENABLE1": { "direction": "OUT" }, - "TRNTD101": { - "direction": "IN" - }, - "PIPERX7CHANISALIGNED": { - "direction": "IN" - }, - "TRNFCNPD3": { + "DBGVECB38": { "direction": "OUT" }, - "CFGERRAERHEADERLOG7": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG84": { - "direction": "IN" - }, - "CFGDSN41": { - "direction": "IN" - }, - "TRNTBUFAV5": { + "DBGVECA49": { "direction": "OUT" }, - "MIMRXWADDR6": { + "XILUNCONNOUT19": { "direction": "OUT" }, - "PIPETX5POWERDOWN1": { + "PIPETX1COMPLIANCE": { "direction": "OUT" }, - "DRPDI3": { + "CFGERRTLPCPLHEADER18": { "direction": "IN" }, - "CFGINTERRUPTSTATN": { + "DBGVECA38": { + "direction": "OUT" + }, + "TRNTDSTRDY0": { + "direction": "OUT" + }, + "TRNTD70": { "direction": "IN" }, - "CFGSUBSYSVENDID11": { + "MIMTXWADDR5": { + "direction": "OUT" + }, + "MIMTXWDATA18": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER6": { "direction": "IN" }, - "MIMTXRDATA42": { + "PIPERX1DATA0": { + "direction": "IN" + }, + "TL2ERRMALFORMED": { + "direction": "OUT" + }, + "PIPERX1STATUS0": { + "direction": "IN" + }, + "CFGDEVCONTROLPHANTOMEN": { + "direction": "OUT" + }, + "PIPETX4DATA1": { + "direction": "OUT" + }, + "PIPERX1VALID": { + "direction": "IN" + }, + "MIMTXRDATA21": { + "direction": "IN" + }, + "PIPETX6DATA1": { + "direction": "OUT" + }, + "TRNRD64": { + "direction": "OUT" + }, + "PLPHYLNKUPN": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG120": { + "direction": "IN" + }, + "XILUNCONNOUT1": { + "direction": "OUT" + }, + "MIMTXRDATA53": { + "direction": "IN" + }, + "MIMRXWDATA55": { + "direction": "OUT" + }, + "PIPERX4DATA7": { + "direction": "IN" + }, + "TL2ERRHDR41": { + "direction": "OUT" + }, + "TRNFCCPLH0": { + "direction": "OUT" + }, + "MIMTXWDATA14": { + "direction": "OUT" + }, + "TRNTD87": { + "direction": "IN" + }, + "TRNTD107": { + "direction": "IN" + }, + "DBGVECA6": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER13": { + "direction": "IN" + }, + "CFGMGMTDO10": { + "direction": "OUT" + }, + "TRNTD93": { + "direction": "IN" + }, + "CFGMGMTDI20": { + "direction": "IN" + }, + "EDTCHANNELSOUT2": { + "direction": "OUT" + }, + "PIPERX2STATUS2": { + "direction": "IN" + }, + "DBGVECC0": { + "direction": "OUT" + }, + "TRNRFCPRET": { + "direction": "IN" + }, + "PIPERX0DATA9": { + "direction": "IN" + }, + "CFGROOTCONTROLPMEINTEN": { + "direction": "OUT" + }, + "PIPERX4CHARISK0": { + "direction": "IN" + }, + "MIMRXRDATA14": { + "direction": "IN" + }, + "DBGVECB39": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG24": { + "direction": "IN" + }, + "DBGVECB22": { + "direction": "OUT" + }, + "CFGAERROOTERRNONFATALERRREPORTINGEN": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG61": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG73": { + "direction": "IN" + }, + "TRNRD117": { + "direction": "OUT" + }, + "TRNRDLLPDATA15": { + "direction": "OUT" + }, + "TRNFCPD8": { + "direction": "OUT" + }, + "PIPETX3POWERDOWN0": { + "direction": "OUT" + }, + "DRPDI5": { + "direction": "IN" + }, + "CFGREVID1": { + "direction": "IN" + }, + "PIPETX1CHARISK0": { + "direction": "OUT" + }, + "PIPERX6CHARISK1": { + "direction": "IN" + }, + "PIPERX0DATA13": { + "direction": "IN" + }, + "TRNTD100": { + "direction": "IN" + }, + "MIMTXWDATA53": { + "direction": "OUT" + }, + "MIMTXRDATA45": { + "direction": "IN" + }, + "TRNRD29": { + "direction": "OUT" + }, + "PIPERX4DATA2": { + "direction": "IN" + }, + "DBGVECA46": { + "direction": "OUT" + }, + "TRNTD104": { + "direction": "IN" + }, + "TRNRD126": { + "direction": "OUT" + }, + "PLRXPMSTATE1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG16": { + "direction": "IN" + }, + "DBGVECB42": { + "direction": "OUT" + }, + "TRNTD108": { + "direction": "IN" + }, + "PIPETX5DATA13": { + "direction": "OUT" + }, + "TRNFCNPD7": { + "direction": "OUT" + }, + "CFGMGMTDO4": { + "direction": "OUT" + }, + "TL2ERRHDR35": { + "direction": "OUT" + }, + "MIMTXRDATA41": { + "direction": "IN" + }, + "PIPERX7DATA0": { + "direction": "IN" + }, + "PIPETX6DATA3": { + "direction": "OUT" + }, + "TRNFCCPLD9": { + "direction": "OUT" + }, + "PIPETX5DATA9": { + "direction": "OUT" + }, + "CFGPMRCVENTERL23N": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID0": { + "direction": "IN" + }, + "TL2ERRHDR2": { + "direction": "OUT" + }, + "PIPETX3DATA9": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG110": { "direction": "IN" }, "CFGPMHALTASPML0SN": { "direction": "IN" }, - "TRNTBUFAV1": { - "direction": "OUT" - }, - "CFGTRANSACTIONADDR3": { - "direction": "OUT" - }, - "MIMRXWDATA36": { - "direction": "OUT" - }, - "MIMTXWDATA12": { - "direction": "OUT" - }, - "PIPERX3ELECIDLE": { + "CFGREVID5": { "direction": "IN" }, - "TL2PPMSUSPENDOK": { + "CFGSUBSYSID5": { + "direction": "IN" + }, + "TRNFCPD11": { "direction": "OUT" }, - "CFGERRAERHEADERLOG95": { - "direction": "IN" - }, - "TRNFCNPD10": { + "PIPETX3DATA0": { "direction": "OUT" }, - "MIMTXRDATA64": { + "CFGERRAERHEADERLOG14": { "direction": "IN" }, - "TRNTD85": { + "PLINITIALLINKWIDTH2": { + "direction": "OUT" + }, + "DBGVECB11": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID8": { "direction": "IN" }, - "MIMTXRDATA16": { + "CFGMGMTDO3": { + "direction": "OUT" + }, + "TRNFCNPD11": { + "direction": "OUT" + }, + "CFGLINKCONTROLCOMMONCLOCK": { + "direction": "OUT" + }, + "TRNRD75": { + "direction": "OUT" + }, + "PLLINKPARTNERGEN2SUPPORTED": { + "direction": "OUT" + }, + "MIMRXWDATA3": { + "direction": "OUT" + }, + "MIMRXRDATA51": { "direction": "IN" }, - "MIMTXREN": { + "TRNRD70": { + "direction": "OUT" + }, + "XILUNCONNOUT21": { + "direction": "OUT" + }, + "PIPERX6DATA1": { + "direction": "IN" + }, + "PIPERX0DATA8": { + "direction": "IN" + }, + "PIPERX7DATA8": { + "direction": "IN" + }, + "MIMRXWDATA18": { + "direction": "OUT" + }, + "TRNRD107": { + "direction": "OUT" + }, + "CFGDEVID6": { + "direction": "IN" + }, + "TRNTD88": { + "direction": "IN" + }, + "TRNTD63": { + "direction": "IN" + }, + "CFGMGMTDO18": { + "direction": "OUT" + }, + "MIMRXRDATA55": { + "direction": "IN" + }, + "TL2ERRHDR23": { + "direction": "OUT" + }, + "PIPECLK": { + "direction": "IN" + }, + "PL2RXPMSTATE0": { "direction": "OUT" }, "TRNTD43": { "direction": "IN" }, - "TRNRD82": { + "PIPERX4POLARITY": { "direction": "OUT" }, - "CFGMGMTDO13": { - "direction": "OUT" - }, - "CFGSUBSYSVENDID10": { + "EDTCLK": { "direction": "IN" }, - "TRNRD52": { + "DBGVECA12": { "direction": "OUT" }, - "CFGMGMTDO2": { + "XILUNCONNOUT5": { "direction": "OUT" }, - "CFGERRAERHEADERLOG85": { + "USERRSTN": { + "direction": "OUT" + }, + "CFGDSDEVICENUMBER0": { "direction": "IN" }, - "TRNRDLLPDATA44": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER8": { + "TRNTD86": { "direction": "IN" }, - "TRNRD31": { + "MIMRXRDATA6": { + "direction": "IN" + }, + "DBGVECB8": { "direction": "OUT" }, - "PLLTSSMSTATE3": { + "TRNRD21": { "direction": "OUT" }, - "CFGDSN51": { + "TRNTD106": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG83": { + "direction": "IN" + }, + "CFGMSGRECEIVEDPMETOACK": { + "direction": "OUT" + }, + "MIMRXWDATA20": { + "direction": "OUT" + }, + "PLTXPMSTATE1": { + "direction": "OUT" + }, + "TRNTD116": { + "direction": "IN" + }, + "MIMTXRDATA48": { + "direction": "IN" + }, + "TRNFCCPLD1": { + "direction": "OUT" + }, + "MIMTXWDATA63": { + "direction": "OUT" + }, + "TRNTERRDROP": { + "direction": "OUT" + }, + "CFGPMCSRPOWERSTATE1": { + "direction": "OUT" + }, + "MIMTXRDATA10": { + "direction": "IN" + }, + "TRNRDLLPDATA7": { + "direction": "OUT" + }, + "TRNTDLLPDATA29": { + "direction": "IN" + }, + "MIMTXRDATA58": { + "direction": "IN" + }, + "DRPDI12": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER5": { + "direction": "IN" + }, + "MIMTXRDATA25": { + "direction": "IN" + }, + "XILUNCONNOUT29": { + "direction": "OUT" + }, + "CFGMGMTDI25": { + "direction": "IN" + }, + "PIPETX6DATA13": { + "direction": "OUT" + }, + "TRNFCCPLD0": { + "direction": "OUT" + }, + "PIPERX7DATA6": { + "direction": "IN" + }, + "CFGERRCPLABORTN": { + "direction": "IN" + }, + "MIMRXWDATA59": { + "direction": "OUT" + }, + "MIMRXRDATA21": { + "direction": "IN" + }, + "PIPETX1DATA12": { + "direction": "OUT" + }, + "MIMTXWDATA23": { + "direction": "OUT" + }, + "PIPETX4DATA7": { + "direction": "OUT" + }, + "CFGAERINTERRUPTMSGNUM2": { + "direction": "IN" + }, + "MIMTXRDATA0": { + "direction": "IN" + }, + "PIPETX2DATA0": { + "direction": "OUT" + }, + "USERCLK": { + "direction": "IN" + }, + "TRNRDLLPDATA38": { + "direction": "OUT" + }, + "TRNRD8": { + "direction": "OUT" + }, + "DBGVECB15": { + "direction": "OUT" + }, + "PIPERX3PHYSTATUS": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG7": { + "direction": "IN" + }, + "TRNRD10": { + "direction": "OUT" + }, + "CFGMGMTDO29": { + "direction": "OUT" + }, + "TRNTDLLPDATA0": { + "direction": "IN" + }, + "PIPETX1DATA2": { + "direction": "OUT" + }, + "MIMTXRDATA26": { + "direction": "IN" + }, + "PIPERX2DATA12": { + "direction": "IN" + }, + "CFGDSN12": { + "direction": "IN" + }, + "CFGMSGDATA2": { + "direction": "OUT" + }, + "TRNRD86": { + "direction": "OUT" + }, + "MIMTXRDATA8": { + "direction": "IN" + }, + "MIMRXWDATA19": { + "direction": "OUT" + }, + "XILUNCONNOUT8": { + "direction": "OUT" + }, + "DBGVECB52": { + "direction": "OUT" + }, + "PIPETX4DATA9": { + "direction": "OUT" + }, + "PIPERX5DATA0": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG6": { + "direction": "IN" + }, + "XILUNCONNOUT14": { + "direction": "OUT" + }, + "PIPERX6DATA7": { + "direction": "IN" + }, + "CFGERRCPLUNEXPECTN": { + "direction": "IN" + }, + "MIMRXRDATA58": { + "direction": "IN" + }, + "DRPADDR7": { + "direction": "IN" + }, + "PIPERX3DATA12": { + "direction": "IN" + }, + "MIMTXWDATA5": { + "direction": "OUT" + }, + "MIMRXWADDR9": { + "direction": "OUT" + }, + "CFGDSN3": { + "direction": "IN" + }, + "CFGMSGRECEIVEDDEASSERTINTA": { + "direction": "OUT" + }, + "CFGMGMTBYTEENN2": { + "direction": "IN" + }, + "CFGDSN50": { + "direction": "IN" + }, + "XILUNCONNOUT17": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER40": { + "direction": "IN" + }, + "TRNRDLLPDATA24": { + "direction": "OUT" + }, + "CFGMGMTDI4": { + "direction": "IN" + }, + "TRNRD71": { + "direction": "OUT" + }, + "CFGREVID4": { + "direction": "IN" + }, + "MIMRXWDATA43": { + "direction": "OUT" + }, + "PIPETX0DATA5": { + "direction": "OUT" + }, + "CFGPORTNUMBER1": { + "direction": "IN" + }, + "PIPETX2POWERDOWN0": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG126": { + "direction": "IN" + }, + "TL2ERRHDR27": { + "direction": "OUT" + }, + "CFGDEVCONTROLFATALERRREPORTINGEN": { + "direction": "OUT" + }, + "CFGDSFUNCTIONNUMBER0": { + "direction": "IN" + }, + "CFGINTERRUPTN": { + "direction": "IN" + }, + "DRPDO2": { + "direction": "OUT" + }, + "PIPERX0CHARISK0": { + "direction": "IN" + }, + "CFGMSGRECEIVEDASSERTINTC": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG96": { + "direction": "IN" + }, + "TRNTEOF": { + "direction": "IN" + }, + "DBGVECB61": { + "direction": "OUT" + }, + "CFGMGMTDO22": { + "direction": "OUT" + }, + "DBGVECC7": { + "direction": "OUT" + }, + "PIPETX6DATA14": { + "direction": "OUT" + }, + "DRPDI4": { + "direction": "IN" + }, + "TRNTD127": { + "direction": "IN" + }, + "MIMTXWDATA46": { + "direction": "OUT" + }, + "MIMTXRADDR12": { + "direction": "OUT" + }, + "DRPDI7": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG64": { + "direction": "IN" + }, + "PLDBGVEC8": { + "direction": "OUT" + }, + "MIMRXWDATA40": { + "direction": "OUT" + }, + "MIMTXRDATA40": { + "direction": "IN" + }, + "MIMTXWADDR3": { + "direction": "OUT" + }, + "TRNTD112": { + "direction": "IN" + }, + "PIPETX4DATA5": { + "direction": "OUT" + }, + "MIMRXWDATA56": { + "direction": "OUT" + }, + "DBGVECB12": { + "direction": "OUT" + }, + "TRNRD73": { + "direction": "OUT" + }, + "TRNTDLLPDATA2": { + "direction": "IN" + }, + "TRNTECRCGEN": { + "direction": "IN" + }, + "TL2ERRHDR62": { + "direction": "OUT" + }, + "PIPETX5DATA10": { + "direction": "OUT" + }, + "TRNTD25": { + "direction": "IN" + }, + "LL2LINKSTATUS1": { + "direction": "OUT" + }, + "EDTCHANNELSOUT1": { + "direction": "OUT" + }, + "TRNRD4": { + "direction": "OUT" + }, + "TRNFCNPD2": { + "direction": "OUT" + }, + "DRPDI10": { + "direction": "IN" + }, + "CFGPMTURNOFFOKN": { + "direction": "IN" + }, + "PIPETX3DATA1": { + "direction": "OUT" + }, + "MIMTXRDATA6": { + "direction": "IN" + }, + "TRNTDLLPDATA28": { + "direction": "IN" + }, + "TRNTD76": { + "direction": "IN" + }, + "PIPETX0DATA12": { + "direction": "OUT" + }, + "PIPETX6COMPLIANCE": { + "direction": "OUT" + }, + "TRNFCCPLD7": { + "direction": "OUT" + }, + "TRNRDLLPDATA52": { + "direction": "OUT" + }, + "DRPDI2": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER46": { + "direction": "IN" + }, + "MIMRXWDATA24": { + "direction": "OUT" + }, + "TRNRD79": { + "direction": "OUT" + }, + "MIMRXWDATA14": { + "direction": "OUT" + }, + "TRNTD61": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG121": { + "direction": "IN" + }, + "CFGMGMTBYTEENN0": { + "direction": "IN" + }, + "CFGTRANSACTIONADDR5": { + "direction": "OUT" + }, + "CFGDSN46": { + "direction": "IN" + }, + "DBGVECB32": { + "direction": "OUT" + }, + "CFGDSN9": { + "direction": "IN" + }, + "PMVOUT": { + "direction": "OUT" + }, + "MIMRXWADDR1": { + "direction": "OUT" + }, + "TRNRDLLPDATA3": { + "direction": "OUT" + }, + "PIPETX6DATA15": { + "direction": "OUT" + }, + "TRNRDLLPDATA32": { + "direction": "OUT" + }, + "MIMTXWDATA2": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER22": { + "direction": "IN" + }, + "CFGMGMTDO20": { + "direction": "OUT" + }, + "MIMRXWDATA5": { + "direction": "OUT" + }, + "TL2ERRFCPE": { + "direction": "OUT" + }, + "MIMRXWDATA30": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDERRCOR": { + "direction": "OUT" + }, + "MIMRXRDATA63": { + "direction": "IN" + }, + "PIPERX6ELECIDLE": { + "direction": "IN" + }, + "MIMRXRDATA25": { + "direction": "IN" + }, + "PIPETX5DATA4": { + "direction": "OUT" + }, + "TRNTD59": { + "direction": "IN" + }, + "TRNRD39": { + "direction": "OUT" + }, + "PIPETX3COMPLIANCE": { + "direction": "OUT" + }, + "CFGMGMTDI6": { + "direction": "IN" + }, + "TRNRD24": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER24": { + "direction": "IN" + }, + "TRNFCNPD10": { + "direction": "OUT" + }, + "PIPERX1STATUS1": { + "direction": "IN" + }, + "PIPERX0STATUS0": { + "direction": "IN" + }, + "DBGSUBMODE": { + "direction": "IN" + }, + "TRNRDLLPDATA25": { + "direction": "OUT" + }, + "LL2LINKSTATUS0": { + "direction": "OUT" + }, + "CFGPMHALTASPML1N": { + "direction": "IN" + }, + "TRNRD22": { + "direction": "OUT" + }, + "CFGINTERRUPTDI2": { + "direction": "IN" + }, + "CFGDEVID1": { + "direction": "IN" + }, + "CFGTRANSACTIONADDR2": { + "direction": "OUT" + }, + "CFGSLOTCONTROLELECTROMECHILCTLPULSE": { + "direction": "OUT" + }, + "CFGMSGDATA9": { + "direction": "OUT" + }, + "MIMTXWDATA58": { + "direction": "OUT" + }, + "PLDBGVEC5": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID3": { + "direction": "IN" + }, + "LL2BADTLPERR": { + "direction": "OUT" + }, + "TRNRNPREQ": { + "direction": "IN" + }, + "PIPERX3STATUS2": { + "direction": "IN" + }, + "MIMRXREN": { + "direction": "OUT" + }, + "PIPERX3DATA7": { + "direction": "IN" + }, + "TL2ERRHDR36": { + "direction": "OUT" + }, + "TL2ERRHDR37": { + "direction": "OUT" + }, + "TRNTD123": { + "direction": "IN" + }, + "CFGVCTCVCMAP0": { + "direction": "OUT" + }, + "CFGDEVCONTROLNONFATALREPORTINGEN": { + "direction": "OUT" + }, + "TRNTERRFWD": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMNEW0": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER12": { + "direction": "IN" + }, + "EDTCHANNELSIN2": { + "direction": "IN" + }, + "PLINITIALLINKWIDTH0": { + "direction": "OUT" + }, + "TRNRD87": { + "direction": "OUT" + }, + "TRNTD23": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG58": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG98": { + "direction": "IN" + }, + "PIPERX5CHARISK0": { + "direction": "IN" + }, + "CFGSUBSYSID4": { + "direction": "IN" + }, + "DBGVECB46": { + "direction": "OUT" + }, + "PIPERX3ELECIDLE": { + "direction": "IN" + }, + "MIMTXWADDR4": { + "direction": "OUT" + }, + "MIMTXRDATA36": { + "direction": "IN" + }, + "TRNRD101": { + "direction": "OUT" + }, + "TRNRD118": { + "direction": "OUT" + }, + "TRNRD32": { + "direction": "OUT" + }, + "PIPERX5DATA5": { + "direction": "IN" + }, + "TRNTD51": { + "direction": "IN" + }, + "MIMRXWADDR4": { + "direction": "OUT" + }, + "TRNRREM0": { + "direction": "OUT" + }, + "DBGVECA36": { + "direction": "OUT" + }, + "TRNRDLLPDATA4": { + "direction": "OUT" + }, + "DBGVECB34": { + "direction": "OUT" + }, + "CFGCOMMANDINTERRUPTDISABLE": { + "direction": "OUT" + }, + "XILUNCONNOUT9": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG91": { + "direction": "IN" + }, + "XILUNCONNOUT38": { + "direction": "OUT" + }, + "MIMRXWDATA27": { + "direction": "OUT" + }, + "PIPERX3DATA1": { + "direction": "IN" + }, + "TL2ERRHDR38": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG109": { + "direction": "IN" + }, + "PIPERX7DATA9": { "direction": "IN" }, "MIMRXWDATA51": { "direction": "OUT" }, - "TRNTDSTRDY2": { + "TRNTD71": { + "direction": "IN" + }, + "CFGINTERRUPTDI6": { + "direction": "IN" + }, + "MIMRXRDATA67": { + "direction": "IN" + }, + "CFGDSN43": { + "direction": "IN" + }, + "CFGMGMTDO26": { "direction": "OUT" }, + "PIPERX3STATUS1": { + "direction": "IN" + }, + "PIPETX2POWERDOWN1": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER1": { + "direction": "IN" + }, + "TRNTD103": { + "direction": "IN" + }, + "TRNRDLLPDATA14": { + "direction": "OUT" + }, + "CFGLINKCONTROLASPMCONTROL1": { + "direction": "OUT" + }, + "TRNFCPH2": { + "direction": "OUT" + }, + "PIPETX2DATA3": { + "direction": "OUT" + }, + "PIPETX0DATA14": { + "direction": "OUT" + }, + "MIMRXRDATA59": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG49": { + "direction": "IN" + }, + "PIPERX7STATUS1": { + "direction": "IN" + }, + "CFGLINKSTATUSDLLACTIVE": { + "direction": "OUT" + }, + "DBGVECC11": { + "direction": "OUT" + }, + "PLDBGVEC9": { + "direction": "OUT" + }, + "TRNFCNPH3": { + "direction": "OUT" + }, + "PIPERX2DATA8": { + "direction": "IN" + }, + "CFGSUBSYSID9": { + "direction": "IN" + }, "CFGMGMTBYTEENN1": { "direction": "IN" }, - "DRPADDR0": { + "TRNTD22": { "direction": "IN" }, - "CFGERRAERHEADERLOG123": { + "TRNTD16": { "direction": "IN" }, - "PIPETX1DATA10": { + "MIMRXRDATA45": { + "direction": "IN" + }, + "PL2DIRECTEDLSTATE1": { + "direction": "IN" + }, + "PIPETX3CHARISK0": { "direction": "OUT" }, - "PIPETX0DATA9": { + "PIPERX1DATA1": { + "direction": "IN" + }, + "DBGVECA19": { "direction": "OUT" }, - "LL2SENDASREQL1": { + "MIMTXWDATA48": { + "direction": "OUT" + }, + "PIPETXMARGIN2": { + "direction": "OUT" + }, + "XILUNCONNOUT37": { + "direction": "OUT" + }, + "PIPERX1STATUS2": { "direction": "IN" }, - "CFGREVID6": { + "PIPERX6VALID": { "direction": "IN" }, - "EDTCONFIGURATION": { + "CFGSUBSYSVENDID9": { "direction": "IN" }, - "EDTCHANNELSIN3": { + "CFGDSN31": { + "direction": "IN" + }, + "PIPERX7DATA15": { + "direction": "IN" + }, + "TRNTD95": { + "direction": "IN" + }, + "MIMTXRDATA3": { + "direction": "IN" + }, + "MIMTXWDATA45": { + "direction": "OUT" + }, + "DBGVECB20": { + "direction": "OUT" + }, + "TRNTD17": { + "direction": "IN" + }, + "PIPERX5DATA4": { + "direction": "IN" + }, + "TRNRD50": { + "direction": "OUT" + }, + "CFGSUBSYSID1": { + "direction": "IN" + }, + "TRNTD54": { + "direction": "IN" + }, + "DBGVECB21": { + "direction": "OUT" + }, + "MIMRXRDATA22": { + "direction": "IN" + }, + "MIMRXWDATA25": { + "direction": "OUT" + }, + "MIMTXWDATA6": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG4": { + "direction": "IN" + }, + "PIPERX2DATA10": { + "direction": "IN" + }, + "PIPETX1DATA15": { + "direction": "OUT" + }, + "PIPERX0DATA14": { + "direction": "IN" + }, + "TRNRDLLPDATA17": { + "direction": "OUT" + }, + "PIPERX1DATA14": { + "direction": "IN" + }, + "PIPETX4DATA13": { + "direction": "OUT" + }, + "DBGVECB59": { + "direction": "OUT" + }, + "TRNTBUFAV1": { + "direction": "OUT" + }, + "CFGDSBUSNUMBER2": { + "direction": "IN" + }, + "TRNTD64": { + "direction": "IN" + }, + "MIMRXRDATA47": { + "direction": "IN" + }, + "CFGMSGDATA11": { + "direction": "OUT" + }, + "PIPETX5DATA2": { + "direction": "OUT" + }, + "MIMRXRDATA0": { + "direction": "IN" + }, + "CFGMGMTDO8": { + "direction": "OUT" + }, + "TRNFCNPH1": { + "direction": "OUT" + }, + "TRNRD61": { + "direction": "OUT" + }, + "TRNRDLLPDATA34": { + "direction": "OUT" + }, + "TL2ERRHDR60": { + "direction": "OUT" + }, + "MIMTXRDATA1": { + "direction": "IN" + }, + "DBGVECA59": { + "direction": "OUT" + }, + "TRNTD121": { + "direction": "IN" + }, + "CFGDEVCONTROL2ATOMICEGRESSBLOCK": { + "direction": "OUT" + }, + "MIMRXRDATA24": { + "direction": "IN" + }, + "CFGINTERRUPTDO6": { + "direction": "OUT" + }, + "TRNTD35": { "direction": "IN" }, "MIMRXWDATA17": { "direction": "OUT" }, - "CFGERRTLPCPLHEADER32": { + "PIPERX1DATA9": { + "direction": "IN" + }, + "PIPERX5STATUS1": { + "direction": "IN" + }, + "CFGPCIECAPINTERRUPTMSGNUM4": { + "direction": "IN" + }, + "TRNRD25": { + "direction": "OUT" + }, + "TRNTD89": { + "direction": "IN" + }, + "PIPERX5DATA13": { + "direction": "IN" + }, + "TRNTD27": { + "direction": "IN" + }, + "CFGPCIECAPINTERRUPTMSGNUM3": { + "direction": "IN" + }, + "CFGDSN25": { + "direction": "IN" + }, + "DBGVECA5": { + "direction": "OUT" + }, + "MIMTXWDATA32": { + "direction": "OUT" + }, + "PIPETX7DATA10": { + "direction": "OUT" + }, + "TRNTD72": { + "direction": "IN" + }, + "TRNTD97": { + "direction": "IN" + }, + "CFGINTERRUPTDI5": { + "direction": "IN" + }, + "CMRSTN": { + "direction": "IN" + }, + "DBGVECA3": { + "direction": "OUT" + }, + "MIMTXWDATA30": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG88": { + "direction": "IN" + }, + "MIMTXWDATA21": { + "direction": "OUT" + }, + "MIMRXWDATA48": { + "direction": "OUT" + }, + "PIPERX6DATA5": { + "direction": "IN" + }, + "MIMRXRDATA2": { + "direction": "IN" + }, + "TRNTD50": { + "direction": "IN" + }, + "CFGLINKCONTROLCLOCKPMEN": { + "direction": "OUT" + }, + "TRNTD1": { + "direction": "IN" + }, + "MIMTXRDATA59": { + "direction": "IN" + }, + "TRNTD115": { + "direction": "IN" + }, + "TL2ERRHDR53": { + "direction": "OUT" + }, + "TRNTD53": { + "direction": "IN" + }, + "TRNRD26": { + "direction": "OUT" + }, + "XILUNCONNOUT30": { + "direction": "OUT" + }, + "TRNRD47": { + "direction": "OUT" + }, + "TRNRD113": { + "direction": "OUT" + }, + "CFGVCTCVCMAP2": { + "direction": "OUT" + }, + "TRNTD36": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER0": { + "direction": "IN" + }, + "DRPCLK": { + "direction": "IN" + }, + "CFGDEVCONTROL2CPLTIMEOUTVAL0": { + "direction": "OUT" + }, + "PLLANEREVERSALMODE1": { + "direction": "OUT" + }, + "TRNFCCPLD6": { + "direction": "OUT" + }, + "TRNRD14": { + "direction": "OUT" + }, + "CFGAERINTERRUPTMSGNUM1": { + "direction": "IN" + }, + "PLDIRECTEDLINKSPEED": { + "direction": "IN" + }, + "LL2SENDPMACK": { "direction": "IN" }, "PIPERX2CHANISALIGNED": { "direction": "IN" }, - "PIPERX4DATA0": { + "PMVSELECT0": { "direction": "IN" }, - "CFGERRAERHEADERLOG28": { + "MIMTXRDATA23": { "direction": "IN" }, - "PIPETX0DATA6": { + "DBGVECA1": { "direction": "OUT" }, - "TRNRD91": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG56": { + "TRNTD32": { "direction": "IN" }, - "CFGAERINTERRUPTMSGNUM2": { + "DBGSCLRF": { + "direction": "OUT" + }, + "CFGMSGRECEIVED": { + "direction": "OUT" + }, + "TRNRDLLPDATA51": { + "direction": "OUT" + }, + "CFGPORTNUMBER7": { "direction": "IN" }, - "MIMRXWADDR3": { + "TRNRDLLPDATA35": { "direction": "OUT" }, - "DBGVECB47": { + "TRNRD85": { "direction": "OUT" }, + "CFGERRAERHEADERLOG86": { + "direction": "IN" + }, + "CFGDSBUSNUMBER1": { + "direction": "IN" + }, + "TRNTDLLPDATA9": { + "direction": "IN" + }, + "TL2ERRHDR25": { + "direction": "OUT" + }, + "TRNTDSTRDY1": { + "direction": "OUT" + }, + "CFGERRCORN": { + "direction": "IN" + }, + "CFGMSGDATA12": { + "direction": "OUT" + }, + "CFGSUBSYSID6": { + "direction": "IN" + }, + "CFGDSFUNCTIONNUMBER2": { + "direction": "IN" + }, + "MIMRXRDATA30": { + "direction": "IN" + }, + "DBGVECA9": { + "direction": "OUT" + }, + "MIMTXRDATA15": { + "direction": "IN" + }, + "TRNRDLLPDATA45": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER43": { + "direction": "IN" + }, + "TRNTREM0": { + "direction": "IN" + }, + "PIPERX0DATA3": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER30": { + "direction": "IN" + }, + "MIMTXRDATA5": { + "direction": "IN" + }, + "PIPETX6POWERDOWN0": { + "direction": "OUT" + }, + "TRNRDSTRDY": { + "direction": "IN" + }, + "TRNFCCPLH1": { + "direction": "OUT" + }, + "CFGMSGDATA14": { + "direction": "OUT" + }, + "TL2ASPMSUSPENDREQ": { + "direction": "OUT" + }, + "CFGINTERRUPTDO1": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDERRFATAL": { + "direction": "OUT" + }, + "CFGVENDID0": { + "direction": "IN" + }, + "CFGDEVCONTROL2IDOCPLEN": { + "direction": "OUT" + }, + "PIPERX6DATA4": { + "direction": "IN" + }, + "CFGLINKSTATUSNEGOTIATEDWIDTH3": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG48": { + "direction": "IN" + }, + "PLDIRECTEDCHANGEDONE": { + "direction": "OUT" + }, + "CFGLINKCONTROLRETRAINLINK": { + "direction": "OUT" + }, + "TL2ERRHDR3": { + "direction": "OUT" + }, + "TRNTD39": { + "direction": "IN" + }, + "DBGVECB41": { + "direction": "OUT" + }, + "MIMTXWDATA61": { + "direction": "OUT" + }, + "MIMRXWDATA58": { + "direction": "OUT" + }, + "MIMTXWDATA15": { + "direction": "OUT" + }, + "CFGPMFORCESTATE1": { + "direction": "IN" + }, + "TRNLNKUP": { + "direction": "OUT" + }, + "PIPERX6DATA3": { + "direction": "IN" + }, + "CFGMGMTDI31": { + "direction": "IN" + }, + "CFGMGMTDI18": { + "direction": "IN" + }, + "TRNTD56": { + "direction": "IN" + }, + "DBGVECA25": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG50": { + "direction": "IN" + }, + "CFGPMCSRPMESTATUS": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG43": { + "direction": "IN" + }, + "DBGVECA14": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG78": { + "direction": "IN" + }, + "PLDIRECTEDLINKWIDTH1": { + "direction": "IN" + }, + "LL2LINKSTATUS3": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG107": { + "direction": "IN" + }, + "MIMTXWDATA33": { + "direction": "OUT" + }, + "CFGCOMMANDIOENABLE": { + "direction": "OUT" + }, + "TRNRD63": { + "direction": "OUT" + }, + "PIPERX4DATA8": { + "direction": "IN" + }, + "DBGSCLRJ": { + "direction": "OUT" + }, + "TRNRDLLPDATA8": { + "direction": "OUT" + }, + "LL2REPLAYTOERR": { + "direction": "OUT" + }, + "XILUNCONNOUT23": { + "direction": "OUT" + }, + "PLDBGVEC11": { + "direction": "OUT" + }, + "TRNFCCPLH3": { + "direction": "OUT" + }, + "CFGVCTCVCMAP3": { + "direction": "OUT" + }, + "MIMTXWDATA8": { + "direction": "OUT" + }, + "PIPETX6DATA5": { + "direction": "OUT" + }, + "PIPETX1POWERDOWN0": { + "direction": "OUT" + }, + "PIPERX6DATA14": { + "direction": "IN" + }, + "CFGDEVCONTROLENABLERO": { + "direction": "OUT" + }, + "TL2ERRHDR49": { + "direction": "OUT" + }, + "PIPETX1DATA9": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG59": { + "direction": "IN" + }, + "TRNRDLLPDATA18": { + "direction": "OUT" + }, + "MIMTXRDATA13": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER15": { + "direction": "IN" + }, + "PIPETX0DATA7": { + "direction": "OUT" + }, + "MIMTXRADDR6": { + "direction": "OUT" + }, + "PIPERX4DATA6": { + "direction": "IN" + }, + "PLSELLNKWIDTH1": { + "direction": "OUT" + }, + "TRNTD52": { + "direction": "IN" + }, + "TL2ERRHDR12": { + "direction": "OUT" + }, + "DBGVECB56": { + "direction": "OUT" + }, + "TRNFCPH0": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER4": { + "direction": "IN" + }, + "MIMTXRADDR3": { + "direction": "OUT" + }, + "DBGVECA21": { + "direction": "OUT" + }, + "TRNRDLLPDATA21": { + "direction": "OUT" + }, + "PIPETX0DATA9": { + "direction": "OUT" + }, + "DBGVECB48": { + "direction": "OUT" + }, + "PIPERX7POLARITY": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER34": { + "direction": "IN" + }, + "MIMRXWDATA49": { + "direction": "OUT" + }, + "PIPERX4STATUS2": { + "direction": "IN" + }, + "TRNRD34": { + "direction": "OUT" + }, + "MIMTXRDATA18": { + "direction": "IN" + }, + "DRPADDR4": { + "direction": "IN" + }, + "DBGSCLRB": { + "direction": "OUT" + }, + "MIMRXRDATA49": { + "direction": "IN" + }, + "PIPETX3POWERDOWN1": { + "direction": "OUT" + }, + "PIPERX4STATUS0": { + "direction": "IN" + }, + "PIPETX0COMPLIANCE": { + "direction": "OUT" + }, + "CFGDEVSTATUSURDETECTED": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG113": { + "direction": "IN" + }, + "PIPETX1DATA14": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG89": { + "direction": "IN" + }, + "TL2ERRHDR8": { + "direction": "OUT" + }, + "MIMRXRDATA8": { + "direction": "IN" + }, + "PIPERX5DATA8": { + "direction": "IN" + }, + "PIPETX5DATA3": { + "direction": "OUT" + }, + "PIPERX4ELECIDLE": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG68": { + "direction": "IN" + }, + "CFGDEVID15": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG8": { + "direction": "IN" + }, + "CFGVCTCVCMAP1": { + "direction": "OUT" + }, + "PIPETX2DATA7": { + "direction": "OUT" + }, + "PIPERX5STATUS0": { + "direction": "IN" + }, + "CFGDSN34": { + "direction": "IN" + }, + "PL2DIRECTEDLSTATE0": { + "direction": "IN" + }, + "PIPERX7DATA11": { + "direction": "IN" + }, + "MIMTXWDATA41": { + "direction": "OUT" + }, + "TRNRD92": { + "direction": "OUT" + }, + "TRNRDLLPDATA30": { + "direction": "OUT" + }, + "TRNRD110": { + "direction": "OUT" + }, + "PL2DIRECTEDLSTATE3": { + "direction": "IN" + }, + "TRNRDLLPDATA57": { + "direction": "OUT" + }, + "MIMTXWDATA26": { + "direction": "OUT" + }, + "CFGDSN51": { + "direction": "IN" + }, + "PIPERX3CHARISK1": { + "direction": "IN" + }, + "PIPERX2VALID": { + "direction": "IN" + }, + "PIPETX5DATA12": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER16": { + "direction": "IN" + }, + "PLDOWNSTREAMDEEMPHSOURCE": { + "direction": "IN" + }, + "MIMTXRDATA60": { + "direction": "IN" + }, + "EDTCHANNELSOUT3": { + "direction": "OUT" + }, + "TRNREOF": { + "direction": "OUT" + }, + "MIMRXRADDR11": { + "direction": "OUT" + }, + "TRNTD114": { + "direction": "IN" + }, + "TRNTD84": { + "direction": "IN" + }, + "LL2RECEIVERERR": { + "direction": "OUT" + }, + "CFGDSN37": { + "direction": "IN" + }, + "DBGVECB33": { + "direction": "OUT" + }, + "TRNTD15": { + "direction": "IN" + }, + "MIMRXRDATA12": { + "direction": "IN" + }, + "MIMRXRDATA4": { + "direction": "IN" + }, + "TRNRD103": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG23": { + "direction": "IN" + }, + "TRNFCNPD4": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER19": { + "direction": "IN" + }, + "PIPERX0DATA12": { + "direction": "IN" + }, + "CFGPCIELINKSTATE1": { + "direction": "OUT" + }, + "CFGSUBSYSID3": { + "direction": "IN" + }, + "PIPERX2DATA1": { + "direction": "IN" + }, + "MIMRXRDATA44": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER10": { + "direction": "IN" + }, + "DBGVECB13": { + "direction": "OUT" + }, + "TRNRD13": { + "direction": "OUT" + }, + "PIPERX5DATA14": { + "direction": "IN" + }, "CFGAERROOTERRCORRERRRECEIVED": { "direction": "OUT" }, "PIPETX2CHARISK0": { "direction": "OUT" }, - "CFGPMHALTASPML1N": { - "direction": "IN" - }, - "CFGMSGRECEIVEDPMETOACK": { + "PL2LINKUP": { "direction": "OUT" }, - "CFGDSBUSNUMBER7": { - "direction": "IN" - }, - "CFGMGMTDI19": { - "direction": "IN" - }, - "CFGINTERRUPTDO1": { + "MIMRXRADDR6": { "direction": "OUT" }, - "MIMRXRDATA55": { + "PIPERX5DATA7": { "direction": "IN" }, - "PIPERX0DATA10": { + "MIMRXWDATA12": { + "direction": "OUT" + }, + "MIMTXWDATA36": { + "direction": "OUT" + }, + "PIPETX4DATA14": { + "direction": "OUT" + }, + "CFGMSGDATA1": { + "direction": "OUT" + }, + "MIMRXWDATA15": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG122": { "direction": "IN" }, - "MIMTXWDATA64": { - "direction": "OUT" - }, - "MIMRXWDATA46": { - "direction": "OUT" - }, - "MIMRXRDATA32": { + "PIPERX7VALID": { "direction": "IN" }, - "TRNRDLLPDATA22": { + "PIPETX4DATA0": { "direction": "OUT" }, - "CFGINTERRUPTDI4": { + "DBGVECB51": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG18": { "direction": "IN" }, - "PIPETX2POWERDOWN0": { - "direction": "OUT" - }, - "TRNTD120": { + "PIPERX5CHARISK1": { "direction": "IN" }, - "TL2ERRHDR56": { + "MIMTXWDATA1": { "direction": "OUT" }, - "CFGERRTLPCPLHEADER26": { + "MIMRXWDATA4": { + "direction": "OUT" + }, + "MIMRXRDATA66": { "direction": "IN" }, - "CFGERRAERHEADERLOG113": { + "PIPERX2CHARISK1": { "direction": "IN" }, - "TRNTD117": { + "TRNTBUFAV0": { + "direction": "OUT" + }, + "MIMTXWADDR0": { + "direction": "OUT" + }, + "DBGVECB0": { + "direction": "OUT" + }, + "MIMTXRDATA63": { "direction": "IN" }, - "CFGERRAERHEADERLOG101": { + "CFGDSN62": { "direction": "IN" }, - "TRNTD0": { + "DBGVECB19": { + "direction": "OUT" + }, + "PIPETX5CHARISK1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG117": { "direction": "IN" }, - "XILUNCONNOUT27": { + "CFGMGMTDI11": { + "direction": "IN" + }, + "CFGLINKCONTROLHWAUTOWIDTHDIS": { "direction": "OUT" }, - "XILUNCONNOUT35": { + "CFGMGMTDO23": { "direction": "OUT" }, - "MIMTXRADDR10": { + "FUNCLVLRSTN": { + "direction": "IN" + }, + "TRNRSRCDSC": { "direction": "OUT" }, - "MIMTXRADDR4": { + "TRNRBARHIT5": { "direction": "OUT" }, - "DBGVECA29": { + "CFGPORTNUMBER5": { + "direction": "IN" + }, + "CFGDEVCONTROLMAXREADREQ1": { "direction": "OUT" }, - "CFGMSGRECEIVEDUNLOCK": { + "CFGTRANSACTION": { + "direction": "OUT" + }, + "MIMRXWDATA32": { + "direction": "OUT" + }, + "TRNTD75": { + "direction": "IN" + }, + "CFGMGMTDI16": { + "direction": "IN" + }, + "MIMTXWADDR11": { + "direction": "OUT" + }, + "DBGVECB47": { + "direction": "OUT" + }, + "MIMRXRDATA10": { + "direction": "IN" + }, + "DBGVECB29": { + "direction": "OUT" + }, + "DRPADDR2": { + "direction": "IN" + }, + "LL2TLPRCV": { + "direction": "IN" + }, + "DBGVECB4": { + "direction": "OUT" + }, + "CFGLINKCONTROLBANDWIDTHINTEN": { + "direction": "OUT" + }, + "PIPETX3DATA11": { + "direction": "OUT" + }, + "PLTXPMSTATE2": { + "direction": "OUT" + }, + "TRNRD100": { + "direction": "OUT" + }, + "TRNTREM1": { + "direction": "IN" + }, + "TRNTDLLPDATA7": { + "direction": "IN" + }, + "DRPDI3": { + "direction": "IN" + }, + "DBGVECB40": { + "direction": "OUT" + }, + "CFGTRANSACTIONADDR3": { + "direction": "OUT" + }, + "CFGMGMTWRRW1CASRWN": { + "direction": "IN" + }, + "PIPETX3DATA3": { + "direction": "OUT" + }, + "MIMTXRDATA7": { + "direction": "IN" + }, + "DRPDI9": { + "direction": "IN" + }, + "CFGDEVCONTROLNOSNOOPEN": { + "direction": "OUT" + }, + "PLTRANSMITHOTRST": { + "direction": "IN" + }, + "CFGMGMTDI29": { + "direction": "IN" + }, + "MIMRXWDATA6": { + "direction": "OUT" + }, + "CFGDSN39": { + "direction": "IN" + }, + "TRNFCPD7": { "direction": "OUT" }, "PIPETX7DATA4": { "direction": "OUT" }, - "TRNTD119": { + "CFGDSDEVICENUMBER1": { "direction": "IN" }, - "MIMRXWDATA40": { + "TRNRBARHIT4": { + "direction": "OUT" + }, + "MIMRXWDATA26": { + "direction": "OUT" + }, + "CFGTRNPENDINGN": { + "direction": "IN" + }, + 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"direction": "OUT" + }, + "TRNRDLLPDATA58": { + "direction": "OUT" + }, + "TRNFCPD3": { + "direction": "OUT" + }, + "TRNTD120": { + "direction": "IN" + }, + "DBGVECA58": { + "direction": "OUT" + }, + "TRNTD49": { + "direction": "IN" + }, + "XILUNCONNOUT39": { + "direction": "OUT" + }, + "TRNTD57": { + "direction": "IN" + }, + "XILUNCONNOUT26": { + "direction": "OUT" + }, + "CFGMGMTDI12": { + "direction": "IN" + }, + "TRNRDLLPDATA47": { + "direction": "OUT" + }, + "TRNRDLLPDATA36": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG77": { + "direction": "IN" + }, + "PIPETX3DATA13": { + "direction": "OUT" + }, + "TRNTD55": { + "direction": "IN" + }, + "DBGVECA7": { + "direction": "OUT" + }, + "PIPERX1DATA3": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER14": { + "direction": "IN" + }, + "CFGMGMTDO0": { + "direction": "OUT" + }, + "TRNFCPD10": { + "direction": "OUT" + }, + "CFGDEVSTATUSNONFATALERRDETECTED": { + "direction": "OUT" + }, + "CFGDEVCONTROLMAXREADREQ2": { + "direction": "OUT" + }, + "TRNRD46": { + "direction": "OUT" + }, + "PIPETX2DATA9": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG104": { + "direction": "IN" + }, + "DBGSCLRC": { + "direction": "OUT" + }, + "DBGVECA52": { + "direction": "OUT" + }, + "TRNRD5": { + "direction": "OUT" + }, + "MIMRXWDATA44": { + "direction": "OUT" + }, + "CFGDSN58": { + "direction": "IN" + }, + "PLDBGMODE0": { + "direction": "IN" + }, + "CFGDSBUSNUMBER5": { + "direction": "IN" + }, + "TL2ERRHDR0": { + "direction": "OUT" + }, + "CFGVENDID14": { + "direction": "IN" + }, + "PIPERX5DATA9": { + "direction": "IN" + }, + "PIPERX4DATA12": { + "direction": "IN" + }, + "DBGVECA10": { + "direction": "OUT" + }, + "MIMRXRDATA29": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG79": { + "direction": "IN" + }, + "MIMTXWDATA25": { + "direction": "OUT" + }, + "CFGDEVID11": { + "direction": "IN" + }, + "TRNTD34": { + "direction": "IN" + }, + "PL2DIRECTEDLSTATE2": { + "direction": "IN" + }, + "TRNRDLLPDATA48": { + "direction": "OUT" + }, + "CFGERRCPLTIMEOUTN": { + "direction": "IN" + }, + "TRNFCNPD1": { + "direction": "OUT" + }, + "CFGAERECRCCHECKEN": { + "direction": "OUT" + }, + "MIMRXRDATA61": { + "direction": "IN" + }, + "CFGSUBSYSID12": { + "direction": "IN" + }, + "MIMTXRADDR2": { + "direction": "OUT" + }, + "LL2BADDLLPERR": { + "direction": "OUT" + }, + "PIPERX0PHYSTATUS": { + "direction": "IN" + }, + "CFGDEVCONTROL2CPLTIMEOUTDIS": { + "direction": "OUT" + }, + "TRNFCCPLD5": { + "direction": "OUT" + }, + "XILUNCONNOUT32": { + "direction": "OUT" + }, + "MIMTXWDATA31": { + "direction": "OUT" + }, + "CFGMGMTDO17": { + "direction": "OUT" + }, + "MIMRXWDATA8": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG56": { + "direction": "IN" + }, + "TRNRD77": { + "direction": "OUT" + }, + "MIMRXWDATA9": { + "direction": "OUT" + }, + "MIMTXRDATA47": { + "direction": "IN" + }, + "CFGMGMTDO14": { + "direction": "OUT" + }, + "TRNRDLLPDATA39": { + "direction": "OUT" + }, + "CFGMGMTDWADDR7": { + "direction": "IN" + }, + "DRPDO15": { + "direction": "OUT" + }, + "PLLTSSMSTATE5": { + "direction": "OUT" + }, + "CFGLINKSTATUSLINKTRAINING": { + "direction": "OUT" + }, + "DBGVECA39": { + "direction": "OUT" + }, + "DBGVECA60": { + "direction": "OUT" + }, + "PIPERX2DATA4": { + "direction": "IN" + }, + "PIPETX6POWERDOWN1": { + "direction": "OUT" + }, + "PLDIRECTEDLTSSMNEW1": { + "direction": "IN" + }, + "CFGDSN29": { + "direction": "IN" + }, "TRNTDLLPSRCRDY": { "direction": "IN" }, "MIMTXWDATA9": { "direction": "OUT" }, - "PIPERX4DATA15": { + "MIMRXRDATA43": { "direction": "IN" }, - "MIMTXRDATA61": { + "TRNTD11": { "direction": "IN" }, - "TRNLNKUP": { + "PIPETX4CHARISK0": { "direction": "OUT" }, - "PIPETX0DATA14": { + "DBGVECA0": { "direction": "OUT" }, - "DBGSCLRC": { - "direction": "OUT" - }, - "DBGVECA41": { - "direction": "OUT" - }, - "CFGMSGRECEIVEDDEASSERTINTD": { - "direction": "OUT" - }, - "PIPERX3CHARISK1": { - "direction": "IN" - }, - "CFGINTERRUPTDO5": { - "direction": "OUT" - }, - "MIMRXRDATA31": { - "direction": "IN" - }, - "PIPERX1DATA13": { - "direction": "IN" - }, - "PIPERX0STATUS2": { - "direction": "IN" - }, - "TRNTDLLPDATA17": { - "direction": "IN" - }, - "MIMRXRDATA67": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER7": { - "direction": "IN" - }, - "LL2LINKSTATUS2": { - "direction": "OUT" - }, - "RECEIVEDFUNCLVLRSTN": { - "direction": "OUT" - }, - "PIPERX6CHARISK0": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG11": { - "direction": "IN" - }, - "CFGMGMTWRRW1CASRWN": { - "direction": "IN" - }, - "DBGMODE0": { - "direction": "IN" - }, - "PIPERX3PHYSTATUS": { - "direction": "IN" - }, - "MIMTXRDATA57": { - "direction": "IN" - }, - "MIMTXWADDR6": { - "direction": "OUT" - }, - "DBGVECA25": { - "direction": "OUT" - }, - "CFGSUBSYSVENDID14": { - "direction": "IN" - }, - "PIPERX2STATUS1": { - "direction": "IN" - }, - "MIMRXRDATA54": { - "direction": "IN" - }, - "CFGDSBUSNUMBER2": { - "direction": "IN" - }, - "TRNTDLLPDATA0": { - "direction": "IN" - }, - "CFGERRCPLRDYN": { - "direction": "OUT" - }, - "CFGSUBSYSID11": { - "direction": "IN" - }, - "PIPERX3DATA0": { - "direction": "IN" - }, - "MIMRXWDATA32": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG45": { - "direction": "IN" - }, - "PLDIRECTEDLTSSMNEW5": { - "direction": "IN" - }, - "DBGVECA49": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG12": { - "direction": "IN" - }, - "PIPERX1DATA0": { - "direction": "IN" - }, - "DBGVECA1": { - "direction": "OUT" - }, - "CFGSUBSYSID12": { - "direction": "IN" - }, - "CFGPMCSRPOWERSTATE0": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG51": { - "direction": "IN" - }, - "CFGDSDEVICENUMBER1": { - "direction": "IN" - }, - "DRPDI13": { - "direction": "IN" - }, - "MIMRXRDATA58": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG57": { - "direction": "IN" - }, - "TRNRDLLPDATA52": { - "direction": "OUT" - }, - "PIPERX5VALID": { - "direction": "IN" - }, - "TRNTD22": { - "direction": "IN" - }, - "TRNTD99": { - "direction": "IN" - }, - "TRNRD47": { - "direction": "OUT" - }, - "PIPETX7POWERDOWN0": { - "direction": "OUT" - }, - "TRNTD56": { - "direction": "IN" - }, - "TRNTBUFAV3": { - "direction": "OUT" - }, - "DBGVECC1": { - "direction": "OUT" - }, - "MIMRXRDATA22": { - "direction": "IN" - }, - "MIMRXRDATA60": { - "direction": "IN" - }, - "DBGVECB3": { - "direction": "OUT" - }, - "TRNRECRCERR": { - "direction": "OUT" - }, - "USERCLK": { - "direction": "IN" - }, - "DBGVECB49": { - "direction": "OUT" - }, - "PMVSELECT1": { - "direction": "IN" - }, - "MIMRXRDATA12": { - "direction": "IN" - }, - "PIPERX0DATA3": { - "direction": "IN" - }, - "DBGVECA28": { - "direction": "OUT" - }, - "TRNTD91": { - "direction": "IN" - }, - "PIPETX3DATA3": { - "direction": "OUT" - }, - "CFGDSN38": { - "direction": "IN" - }, - "DBGVECA19": { - "direction": "OUT" - }, - "CFGSUBSYSVENDID9": { - "direction": "IN" - }, - "MIMRXRDATA36": { - "direction": "IN" - }, - "TRNRD19": { - "direction": "OUT" - }, - "TRNFCCPLD3": { - "direction": "OUT" - }, - "DBGVECA31": { - "direction": "OUT" - }, - "PIPERX4DATA6": { - "direction": "IN" - }, - "XILUNCONNOUT6": { - "direction": "OUT" - }, - "TRNTD59": { - "direction": "IN" - }, - "MIMRXWDATA62": { - "direction": "OUT" - }, - "PIPETX7DATA8": { - "direction": "OUT" - }, - "MIMTXRDATA19": { - "direction": "IN" - }, - "PL2RXPMSTATE0": { - "direction": "OUT" - }, - "PIPERX6DATA12": { - "direction": "IN" - }, - "TRNFCCPLH3": { - "direction": "OUT" - }, - "MIMTXWADDR4": { - "direction": "OUT" - }, - "TRNRDLLPDATA7": { - "direction": "OUT" - }, - "MIMTXRDATA58": { - "direction": "IN" - }, - "TRNTSRCRDY": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG41": { - "direction": "IN" - }, - "MIMTXRDATA41": { - "direction": "IN" - }, - "CFGDSDEVICENUMBER4": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG111": { - "direction": "IN" - }, - "MIMTXRDATA38": { - "direction": "IN" - }, - "TRNRD126": { - "direction": "OUT" - }, - "CFGPMWAKEN": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER5": { - "direction": "IN" - }, - "PLLTSSMSTATE5": { - "direction": "OUT" - }, - "PIPERX0DATA2": { - "direction": "IN" - }, - "PIPERX3DATA10": { - "direction": "IN" - }, - "MIMTXWDATA42": { - "direction": "OUT" - }, - "CFGDSN58": { - "direction": "IN" - }, - "PIPERX0CHANISALIGNED": { - "direction": "IN" - }, - "MIMTXRDATA28": { - "direction": "IN" - }, - "CFGDSN37": { - "direction": "IN" - }, - "MIMRXRDATA59": { - "direction": "IN" - }, - "CFGINTERRUPTRDYN": { - "direction": "OUT" - }, - "TRNTREM1": { - "direction": "IN" - }, - "PIPETX6DATA6": { - "direction": "OUT" - }, - "MIMTXRADDR5": { - "direction": "OUT" - }, - "PIPETXRCVRDET": { - "direction": "OUT" - }, - "XILUNCONNOUT11": { - "direction": "OUT" - }, - "CFGMGMTDI20": { - "direction": "IN" - }, - "CFGDSBUSNUMBER4": { - "direction": "IN" - }, - "DBGVECA34": { - "direction": "OUT" - }, - "PIPERX5PHYSTATUS": { - "direction": "IN" - }, - "LL2SUSPENDNOW": { - "direction": "IN" - }, - "TRNFCCPLD6": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG122": { - "direction": "IN" - }, - "PLDBGVEC9": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER23": { - "direction": "IN" - }, - "TRNTD2": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER15": { - "direction": "IN" - }, - "TRNRD69": { - "direction": "OUT" - }, - "TRNTD92": { - "direction": "IN" - }, - "CFGMSGDATA10": { - "direction": "OUT" - }, - "TRNFCPD1": { - "direction": "OUT" - }, - "PIPERX7DATA13": { - "direction": "IN" - }, - "TRNTD27": { - "direction": "IN" - }, - "MIMRXRDATA27": { - "direction": "IN" - }, - "DBGVECA15": { - "direction": "OUT" - }, - "PIPETXMARGIN2": { - "direction": "OUT" - }, - "PL2DIRECTEDLSTATE1": { - "direction": "IN" - }, - "XILUNCONNOUT37": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG125": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG127": { - "direction": "IN" - }, - "PIPETX7DATA6": { - "direction": "OUT" - }, - "TL2ASPMSUSPENDREQ": { - "direction": "OUT" - }, - "CFGMGMTDI29": { - "direction": "IN" - }, - "TRNFCPH7": { - "direction": "OUT" - }, - "PIPETX3DATA5": { - "direction": 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"CFGPORTNUMBER2": { - "direction": "IN" - }, - "XILUNCONNOUT10": { - "direction": "OUT" - }, - "MIMRXRDATA61": { - "direction": "IN" - }, - "PIPERX6DATA10": { - "direction": "IN" - }, - "CFGDSN4": { - "direction": "IN" - }, - "TRNRDLLPDATA30": { - "direction": "OUT" - }, - "MIMRXRADDR9": { - "direction": "OUT" - }, - "TRNFCPH0": { - "direction": "OUT" - }, - "DBGVECB9": { - "direction": "OUT" - }, - "CFGMGMTDI8": { - "direction": "IN" - }, - "CFGMSGRECEIVEDDEASSERTINTB": { - "direction": "OUT" - }, - "TRNTD15": { - "direction": "IN" - }, - "MIMRXWDATA49": { - "direction": "OUT" - }, - "TRNFCPH2": { - "direction": "OUT" - }, - "PIPERX4POLARITY": { - "direction": "OUT" - }, - "CFGDSN35": { - "direction": "IN" - }, - "PIPETX5DATA7": { - "direction": "OUT" - }, - "TRNTD14": { - "direction": "IN" - }, - "MIMRXWDATA12": { - "direction": "OUT" - }, - "PIPETX5DATA8": { - "direction": "OUT" - }, - "MIMTXRADDR6": { - "direction": "OUT" - }, - "DBGVECC8": { - "direction": "OUT" - }, - "PIPERX7DATA10": { - "direction": "IN" - }, - "TRNRNPREQ": { - "direction": "IN" - }, "TRNRDLLPDATA40": { "direction": "OUT" }, - "DRPDI15": { - "direction": "IN" - }, - "TRNRD121": { - "direction": "OUT" - }, - "PIPETX6DATA7": { - "direction": "OUT" - }, - "MIMRXRDATA37": { - "direction": "IN" - }, - "TRNRDLLPDATA48": { - "direction": "OUT" - }, - "TRNTD33": { - "direction": "IN" - }, - "PIPETX2DATA12": { - "direction": "OUT" - }, - "TRNRD51": { - "direction": "OUT" - }, - "TRNRDLLPDATA62": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER18": { - "direction": "IN" - }, - "XILUNCONNOUT1": { - "direction": "OUT" - }, - "TRNTD6": { - "direction": "IN" - }, - "DBGVECB6": { - "direction": "OUT" - }, - "TRNTD41": { - "direction": "IN" - }, - "TRNTD53": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER11": { - "direction": "IN" - }, - "MIMRXRDATA28": { - "direction": "IN" - }, - "PIPERX3STATUS2": { - "direction": "IN" - }, - "MIMTXRDATA60": { - "direction": "IN" - }, - "CFGDEVCONTROLEXTTAGEN": { - "direction": "OUT" - }, - "MIMTXWDATA67": { - "direction": "OUT" - }, - "TRNFCPD11": { - "direction": "OUT" - }, - "TRNTD72": { - "direction": "IN" - }, - "TRNTD19": { - "direction": "IN" - }, - "TRNTBUFAV0": { - "direction": "OUT" - }, - "TRNFCNPD7": { - "direction": "OUT" - }, - "MIMRXWDATA19": { - "direction": "OUT" - }, - "TRNRDLLPDATA59": { - "direction": "OUT" - }, - "MIMTXRDATA51": { - "direction": "IN" - }, - "TRNFCNPD8": { - "direction": "OUT" - }, - "TRNTD70": { - "direction": "IN" - }, - "PMVENABLEN": { - "direction": "IN" - }, - "CFGDEVSTATUSNONFATALERRDETECTED": { - "direction": "OUT" - }, - "MIMRXWADDR7": { - "direction": "OUT" - }, - "MIMRXWDATA20": { - "direction": "OUT" - }, - "PIPERX3DATA11": { - "direction": "IN" - }, - "MIMTXRDATA59": { - "direction": "IN" - }, - "XILUNCONNOUT20": { - "direction": "OUT" - }, - "TRNRD22": { - "direction": "OUT" - }, - "CFGDEVID12": { - "direction": "IN" - }, - "PIPERX3CHARISK0": { - "direction": "IN" - }, - "PIPERX2DATA4": { - "direction": "IN" - }, - "PIPERX1ELECIDLE": { - "direction": "IN" - }, - "CMRSTN": { - "direction": "IN" - }, - "PIPETX4DATA5": { - "direction": "OUT" - }, - "PIPERX6DATA8": { - "direction": "IN" - }, - "DRPDI0": { - "direction": "IN" - }, - "PIPETX5ELECIDLE": { - "direction": "OUT" - }, - "MIMRXRADDR5": { - "direction": "OUT" - }, - "TRNTCFGGNT": { - "direction": "IN" - }, - "PIPETX1DATA11": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER13": { - "direction": "IN" - }, - "MIMTXRDATA5": { - "direction": "IN" - }, - "CFGDSN15": { - "direction": "IN" - }, - "TRNTD104": { - "direction": "IN" - }, - "DBGVECB15": { - "direction": "OUT" - }, - "TRNRD114": { - "direction": "OUT" - }, - "MIMTXRDATA40": { - "direction": "IN" - }, - "CFGPMRCVASREQL1N": { - "direction": "OUT" - }, - "EDTCHANNELSIN6": { - "direction": "IN" - }, - "PIPERX0DATA13": { - "direction": "IN" - }, - "TRNFCNPD2": { - "direction": "OUT" - }, - "TRNRD116": { - "direction": "OUT" - }, - "PIPERX7DATA11": { - "direction": "IN" - }, - "PIPETX6DATA8": { - "direction": "OUT" - }, - "PIPETX4DATA3": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER29": { - "direction": "IN" - }, - "XILUNCONNOUT9": { - "direction": "OUT" - }, - "CFGPMRCVREQACKN": { - "direction": "OUT" - }, - "CFGMSGDATA11": { - "direction": "OUT" - }, - "CFGDSN42": { - "direction": "IN" - }, - "MIMTXRDATA25": { - "direction": "IN" - }, - "TRNRDLLPDATA9": { - "direction": "OUT" - }, - "TL2ERRHDR41": { - "direction": "OUT" - }, - "TRNRDLLPDATA50": { - "direction": "OUT" - }, - "TRNRD39": { - "direction": "OUT" - }, - "MIMTXRDATA24": { - "direction": "IN" - }, - "CFGSUBSYSID15": { - "direction": "IN" - }, - "CFGMGMTDO25": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER41": { - "direction": "IN" - }, - "CFGMSGRECEIVEDASSERTINTA": { - "direction": "OUT" - }, - "CFGDEVCONTROL2CPLTIMEOUTVAL3": { - "direction": "OUT" - }, - "PIPERX7DATA4": { - "direction": "IN" - }, - "PIPERX1DATA12": { - "direction": "IN" - }, - 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"direction": "OUT" - }, - "TRNFCPD2": { - "direction": "OUT" - }, - "PIPETX1COMPLIANCE": { - "direction": "OUT" - }, - "PIPERX5DATA9": { - "direction": "IN" - }, - "TRNRD88": { - "direction": "OUT" - }, - "XILUNCONNOUT4": { - "direction": "OUT" - }, - "PIPETX2DATA9": { - "direction": "OUT" - }, - "MIMTXWDATA8": { - "direction": "OUT" - }, - "MIMTXWADDR7": { - "direction": "OUT" - }, - "DBGVECB39": { - "direction": "OUT" - }, - "PIPETX5DATA2": { - "direction": "OUT" - }, - "TRNTDLLPDATA30": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG80": { - "direction": "IN" - }, - "CFGMSGRECEIVEDERRNONFATAL": { - "direction": "OUT" - }, - "PIPETX4POWERDOWN0": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER1": { - "direction": "IN" - }, - "PIPERX0ELECIDLE": { - "direction": "IN" - }, - "TRNTD73": { - "direction": "IN" - }, - "MIMRXRADDR11": { - "direction": "OUT" - }, - "CFGDEVCONTROLMAXREADREQ2": { - "direction": "OUT" - }, - "CFGDSN14": { - "direction": "IN" - }, - "CFGDSN59": { - "direction": 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- }, - "DBGVECA40": { - "direction": "OUT" - }, - "PIPERX0DATA12": { - "direction": "IN" - }, - "CFGSUBSYSVENDID3": { - "direction": "IN" - }, - "CFGDSN20": { - "direction": "IN" - }, - "DRPADDR4": { - "direction": "IN" - }, - "CFGAERINTERRUPTMSGNUM1": { - "direction": "IN" - }, - "TRNRD117": { - "direction": "OUT" - }, - "PIPETX3POWERDOWN1": { - "direction": "OUT" - }, - "CFGERRINTERNALCORN": { - "direction": "IN" - }, - "TL2ERRHDR2": { - "direction": "OUT" - }, - "MIMRXRDATA14": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER14": { - "direction": "IN" - }, - "MIMRXRDATA23": { - "direction": "IN" - }, - "CFGVCTCVCMAP4": { - "direction": "OUT" - }, - "DBGVECB21": { - "direction": "OUT" - }, - "MIMRXRDATA7": { - "direction": "IN" - }, - "MIMRXRDATA26": { - "direction": "IN" - }, - "CFGDSN57": { - "direction": "IN" - }, - "DBGVECC10": { - "direction": "OUT" - }, - "DRPDO8": { - "direction": "OUT" - }, - "DRPDO3": { - "direction": "OUT" - }, - "XILUNCONNOUT32": { - "direction": "OUT" - }, - "PIPETX4CHARISK1": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER6": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG71": { - "direction": "IN" - }, - "TRNTDLLPDATA29": { - "direction": "IN" - }, - "LL2SUSPENDOK": { - "direction": "OUT" - }, - "TRNRDLLPDATA41": { - "direction": "OUT" - }, - "CFGVENDID2": { - "direction": "IN" - }, - "PIPERX7DATA14": { - "direction": "IN" - }, - "PIPETX7COMPLIANCE": { - "direction": "OUT" - }, - "TRNTDLLPDATA4": { - "direction": "IN" - }, - "CFGMGMTDI13": { - "direction": "IN" - }, - "MIMRXWDATA59": { - "direction": "OUT" - }, - "CFGDEVID4": { - "direction": "IN" - }, - "TRNRD54": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER30": { - "direction": "IN" - }, - "TRNTD50": { - "direction": "IN" - }, - "DBGVECA22": { - "direction": "OUT" - }, - "PIPERX3DATA15": { - "direction": "IN" - }, - "PLDBGMODE0": { - "direction": "IN" - }, - "PIPETX5POWERDOWN0": { - "direction": "OUT" - }, - "TRNRD8": { - "direction": "OUT" - }, - "TRNFCSEL2": { - "direction": "IN" - }, - "PIPERX7STATUS0": { - "direction": "IN" - }, - "PIPETX5CHARISK0": { - "direction": "OUT" - }, - "CFGDSN34": { - "direction": "IN" - }, - "CFGBRIDGESERREN": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG31": { - "direction": "IN" - }, - "TL2ERRHDR35": { - "direction": "OUT" - }, - "MIMRXWDATA13": { - "direction": "OUT" - }, - "EDTCHANNELSIN5": { - "direction": "IN" - }, - "PIPETX2DATA5": { - "direction": "OUT" - }, - "DBGVECB22": { - "direction": "OUT" - }, - "PIPERX2DATA3": { - "direction": "IN" - }, - "TRNRD65": { - "direction": "OUT" - }, - "MIMRXRDATA63": { - "direction": "IN" - }, - "CFGDSN24": { - "direction": "IN" - }, - "PIPETX5DATA13": { - "direction": "OUT" - }, - "TRNTD100": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG86": { - "direction": "IN" - }, - "TRNRDLLPDATA21": { - "direction": "OUT" - }, - "PIPETX5DATA0": { - "direction": "OUT" - }, - "CFGMSGDATA4": { - "direction": "OUT" - }, - "PIPERX2ELECIDLE": { - "direction": "IN" - }, - "PIPETX2CHARISK1": { - "direction": "OUT" - }, - "PLDBGVEC0": { - "direction": "OUT" - }, - "PIPETX2DATA15": { - "direction": "OUT" - }, - "PIPETX7DATA13": { - "direction": "OUT" - }, - "CFGPORTNUMBER1": { - "direction": "IN" - }, - "PIPETX3DATA7": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER12": { - "direction": "IN" - }, - "DBGVECA39": { - "direction": "OUT" - }, - "TRNRDLLPDATA46": { - "direction": "OUT" - }, - "DRPDO2": { - "direction": "OUT" - }, - "TRNTD25": { - "direction": "IN" - }, - "TRNTD49": { - "direction": "IN" - }, - "PIPERX2DATA0": { - "direction": "IN" - }, - "PIPERX6VALID": { - "direction": "IN" - }, - "PIPERX5CHARISK0": { - "direction": "IN" - }, - "PIPETX0DATA8": { - "direction": "OUT" - }, - "MIMTXWDATA15": { - "direction": "OUT" - }, - "MIMRXRDATA65": { - "direction": "IN" - }, - "TRNRD62": { - "direction": "OUT" - }, - "CFGDEVID11": { - "direction": "IN" - }, - "MIMRXWDATA11": { - "direction": "OUT" - }, - "CFGMGMTDWADDR5": { - "direction": "IN" - }, - "PIPERX5DATA5": { - "direction": "IN" - }, - "TRNRDLLPDATA4": { - "direction": "OUT" - }, - "PIPERX7ELECIDLE": { - "direction": "IN" - }, - "TRNRD28": { - "direction": "OUT" - }, - "MIMTXRDATA37": { - "direction": "IN" - }, - "CFGDSN1": { - "direction": "IN" - }, - "PIPETXMARGIN1": { - "direction": "OUT" - }, - "TL2ERRHDR16": { - "direction": "OUT" - }, - "PIPERX0DATA7": { - "direction": "IN" - }, - "CFGMGMTDO30": { - "direction": "OUT" - }, - "CFGMSGRECEIVEDASSERTINTC": { - "direction": "OUT" - }, - "MIMTXWDATA59": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER36": { - "direction": "IN" - }, - "CFGPCIECAPINTERRUPTMSGNUM4": { - "direction": "IN" - }, - "PIPETX6ELECIDLE": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG60": { - "direction": "IN" - }, - "MIMRXWDATA33": { - "direction": "OUT" - }, - "MIMTXRDATA13": { - "direction": "IN" - }, - "DRPADDR8": { - "direction": "IN" - }, - "DBGVECA14": { - "direction": "OUT" - }, - "TRNRD61": { - "direction": "OUT" - }, - "TRNRD26": { - "direction": "OUT" - }, - "CFGMGMTDWADDR0": { - "direction": "IN" - }, - "EDTUPDATE": { - "direction": "IN" - }, - "DBGVECB31": { - "direction": "OUT" - }, - "PIPETX2DATA14": { - "direction": "OUT" - }, - "CFGMSGDATA5": { - "direction": "OUT" - }, - "CFGMGMTDO14": { - "direction": "OUT" - }, - "CFGDEVCONTROL2TLPPREFIXBLOCK": { - "direction": "OUT" - }, - "MIMRXRDATA53": { - "direction": "IN" - }, - "TRNRD27": { - "direction": "OUT" - }, - "MIMTXWDATA35": { - "direction": "OUT" - }, - "PLLINKPARTNERGEN2SUPPORTED": { - "direction": "OUT" - }, - "PIPETX3DATA12": { - "direction": "OUT" - }, - "PIPERX3CHANISALIGNED": { - "direction": "IN" - }, - "MIMRXWDATA60": { - "direction": "OUT" - }, - "TRNRD9": { - "direction": "OUT" - }, - "TRNTD123": { - "direction": "IN" - }, - "TL2ERRRXOVERFLOW": { - "direction": "OUT" - }, - "PIPETX6DATA2": { - "direction": "OUT" - }, - "TRNRD57": { - "direction": "OUT" - }, - "PLDIRECTEDLTSSMNEW1": { - "direction": "IN" - }, - "PIPETX4DATA8": { - "direction": "OUT" - }, - "PIPERX4DATA14": { - "direction": "IN" - }, - "PIPETX0DATA7": { - "direction": "OUT" - }, - "PIPETX4DATA4": { - "direction": "OUT" - }, - "CFGDSN50": { - "direction": "IN" - }, - "PIPERX7DATA0": { - "direction": "IN" - }, - "CFGSUBSYSID2": { - "direction": "IN" - }, - "TRNRD81": { - "direction": "OUT" - }, - "TRNTD1": { - "direction": "IN" - }, - "CFGDEVCONTROL2LTREN": { - "direction": "OUT" - }, - "TRNTD107": { - "direction": "IN" - }, - "TRNRD50": { - "direction": "OUT" - }, - "TRNTD45": { - "direction": "IN" - }, - "TRNRD55": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER0": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER28": { - "direction": "IN" - }, - "TRNTD38": { - "direction": "IN" - }, - "CFGDSN63": { - "direction": "IN" - }, - "TRNRD5": { - "direction": "OUT" - }, - "MIMTXRDATA39": { - "direction": "IN" - }, - "PIPETX2DATA13": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER45": { - "direction": "IN" - }, - "DBGSCLRH": { - "direction": "OUT" - }, - "TRNTD30": { - "direction": "IN" - }, - "PIPETX7DATA12": { - "direction": "OUT" - }, - "TL2ERRHDR21": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG67": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG9": { - "direction": "IN" - }, - "CFGERRAERHEADERLOG34": { - "direction": "IN" - }, - "TRNRD1": { - "direction": "OUT" - }, - "CFGDEVCONTROL2IDOCPLEN": { - "direction": "OUT" - }, - "CFGINTERRUPTDO3": { - "direction": "OUT" - }, - "PIPETX7DATA2": { - "direction": "OUT" - }, - "PL2DIRECTEDLSTATE4": { - "direction": "IN" - }, - "TRNTD96": { - "direction": "IN" - }, - "MIMRXWDATA18": { - "direction": "OUT" - }, - "DBGVECB10": { - "direction": "OUT" - }, - "PIPERX1DATA6": { - "direction": "IN" - }, - "CFGTRANSACTIONADDR2": { - "direction": "OUT" - }, - "DBGVECB43": { - "direction": "OUT" - }, - "CFGPCIELINKSTATE0": { - "direction": "OUT" - }, - "CFGROOTCONTROLSYSERRCORRERREN": { - "direction": "OUT" - }, - "TRNRBARHIT7": { - "direction": "OUT" - }, - "DBGVECC2": { - "direction": "OUT" - }, - "CFGDEVCONTROLMAXREADREQ0": { - "direction": "OUT" - }, - "TRNRDLLPSRCRDY1": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG88": { - "direction": "IN" - }, - "MIMRXWDATA22": { - "direction": "OUT" - }, - "DRPDO14": { - "direction": "OUT" - }, - "PIPERX0VALID": { - "direction": "IN" - }, - "TRNTDLLPDATA27": { - "direction": "IN" - }, - "TRNTD106": { - "direction": "IN" - }, - "CFGVENDID4": { - "direction": "IN" - }, - "MIMRXWDATA52": { - "direction": "OUT" - }, - "CFGDSN32": { - "direction": "IN" - }, - "USERCLKPREBUFEN": { - "direction": "IN" - }, - "PIPERX1STATUS2": { - "direction": "IN" - }, - "CFGMGMTDO8": { - "direction": "OUT" - }, - "TRNFCNPD4": { - "direction": "OUT" - }, - "TRNRDLLPDATA32": { - "direction": "OUT" - }, - "PIPERX2CHARISK0": { - "direction": "IN" - }, - "TRNTD63": { - "direction": "IN" - }, - "CFGMSGDATA13": { - "direction": "OUT" - }, - "PIPETX4ELECIDLE": { - "direction": "OUT" - }, - "CFGMGMTDI9": { - "direction": "IN" - }, - "PIPERX0STATUS1": { - "direction": "IN" - }, - "PIPERX1CHANISALIGNED": { - "direction": "IN" - }, - "TRNRD83": { - "direction": "OUT" - }, - "TL2ERRHDR0": { - "direction": "OUT" - }, - "PIPERX4DATA1": { - "direction": "IN" - }, - "CFGDSN2": { - "direction": "IN" - }, - "MIMTXRDATA66": { - "direction": "IN" - }, - "PIPERX6DATA2": { - "direction": "IN" - }, - "PIPERX3DATA1": { - "direction": "IN" - }, - "XILUNCONNOUT7": { - "direction": "OUT" - }, - "DRPCLK": { - "direction": "IN" - }, - "PIPERX7STATUS2": { - "direction": "IN" - }, - "MIMTXWDATA24": { - "direction": "OUT" - }, - "CFGERRNORECOVERYN": { - "direction": "IN" - }, - "MIMRXWDATA35": { - "direction": "OUT" - }, - "DBGVECC0": { - "direction": "OUT" - }, - "MIMTXRADDR3": { - "direction": "OUT" - }, - "MIMTXRADDR7": { - "direction": "OUT" - }, - "TL2ERRHDR19": { - "direction": "OUT" - }, - "DBGVECA62": { - "direction": "OUT" - }, - "PIPETX1DATA12": { - "direction": "OUT" - }, - "TRNTD122": { - "direction": "IN" - }, - "CFGLINKSTATUSCURRENTSPEED1": { - "direction": "OUT" - }, - "CFGDSN7": { - "direction": "IN" - }, - "TRNRD119": { - "direction": "OUT" - }, - "TRNRDLLPDATA57": { - "direction": "OUT" - }, - "TRNRD2": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG29": { - "direction": "IN" - }, - "PIPERX6DATA11": { - "direction": "IN" - }, - "DBGVECA18": { - "direction": "OUT" - }, - "TRNRDLLPDATA56": { - "direction": "OUT" - }, - "XILUNCONNOUT24": { - "direction": "OUT" - }, - "PIPETX0DATA10": { - "direction": "OUT" - }, - "PIPERX6DATA1": { - "direction": "IN" - }, - "TRNFCCPLH4": { - "direction": "OUT" - }, - "MIMRXWEN": { - "direction": "OUT" - }, - "MIMRXWADDR5": { + "XILUNCONNOUT25": { "direction": "OUT" }, "PIPERX5DATA2": { "direction": "IN" }, - "PIPERX5DATA1": { - "direction": "IN" - }, - "PIPETX5DATA4": { + "CFGROOTCONTROLSYSERRFATALERREN": { "direction": "OUT" }, - "CFGINTERRUPTDO6": { + "MIMRXRDATA60": { + "direction": "IN" + }, + "PIPERX6CHANISALIGNED": { + "direction": "IN" + }, + "TRNRD59": { "direction": "OUT" }, - "TRNTD66": { - "direction": "IN" - }, - "PL2DIRECTEDLSTATE0": { - "direction": "IN" - }, - "PIPETXRESET": { + "PIPETX0DATA0": { "direction": "OUT" }, - "PIPETX3DATA15": { + "CFGPCIECAPINTERRUPTMSGNUM2": { + "direction": "IN" + }, + "TRNFCNPD8": { "direction": "OUT" }, - "TRNTD103": { + "CFGMGMTDWADDR2": { "direction": "IN" }, - "CFGPMFORCESTATEENN": { - "direction": "IN" - }, - "LL2SENDENTERL23": { - "direction": "IN" - }, - "MIMTXRDATA27": { - "direction": "IN" - }, - "TRNFCSEL1": { - "direction": "IN" - }, - "LL2RECEIVERERR": { - "direction": "OUT" - }, - "PLTXPMSTATE1": { - "direction": "OUT" - }, - "XILUNCONNOUT26": { - "direction": "OUT" - }, - "PIPETXDEEMPH": { - "direction": "OUT" - }, - "CFGERRTLPCPLHEADER34": { - "direction": "IN" - }, - "CFGMGMTDO22": { - "direction": "OUT" - }, - "PIPERX2STATUS0": { - "direction": "IN" - }, - "MIMRXRDATA20": { - "direction": "IN" - }, - "DRPDO12": { - "direction": "OUT" - }, - "TRNTD18": { - "direction": "IN" - }, - "PIPERX5DATA3": { - "direction": "IN" - }, - "CFGMGMTRDWRDONEN": { - "direction": "OUT" - }, - "PIPETX5DATA9": { - "direction": "OUT" - }, - "MIMTXWDATA49": { - "direction": "OUT" - }, - "PLDIRECTEDCHANGEDONE": { - "direction": "OUT" - }, - "PIPERX5ELECIDLE": { - "direction": "IN" - }, - "CFGMSGDATA14": { - "direction": "OUT" - }, - "MIMRXRDATA5": { - "direction": "IN" - }, - "PIPERX5DATA8": { - "direction": "IN" - }, - "MIMRXRDATA18": { - "direction": "IN" - }, - "MIMRXRDATA3": { - "direction": "IN" - }, - "PIPERX2CHARISK1": { - "direction": "IN" - }, - "CFGDSFUNCTIONNUMBER1": { - "direction": "IN" - }, - "CFGDSN19": { - "direction": "IN" - }, - "CFGERRTLPCPLHEADER35": { - "direction": "IN" - }, - "LL2SENDPMACK": { + "CFGMGMTRDENN": { "direction": "IN" }, "TRNRD56": { "direction": "OUT" }, - "CFGERRAERHEADERLOG18": { - "direction": "IN" - }, - "TRNRD53": { - "direction": "OUT" - }, - "CFGDSBUSNUMBER6": { - "direction": "IN" - }, - "CFGSUBSYSVENDID15": { - "direction": "IN" - }, - "TRNRDLLPDATA38": { - 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"direction": "IN" - }, - "MIMTXWDATA46": { - "direction": "OUT" - }, - "PIPETXMARGIN0": { - "direction": "OUT" - }, - "TRNTD8": { - "direction": "IN" - }, - "TRNFCSEL0": { - "direction": "IN" - }, - "DBGVECB28": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG115": { - "direction": "IN" - }, - "CFGMSGRECEIVEDDEASSERTINTC": { - "direction": "OUT" - }, - "DRPDO7": { - "direction": "OUT" - }, - "CFGMSGRECEIVEDPMETO": { - "direction": "OUT" - }, - "PL2SUSPENDOK": { - "direction": "OUT" - }, - "CFGDEVID7": { - "direction": "IN" - }, - "SCANENABLEN": { - "direction": "IN" - }, - "CFGPMSENDPMETON": { - "direction": "IN" - }, - "CFGROOTCONTROLSYSERRNONFATALERREN": { - "direction": "OUT" - }, - "CFGDEVCONTROL2ARIFORWARDEN": { - "direction": "OUT" - }, - "TRNTD125": { - "direction": "IN" - }, - "PIPERX2DATA15": { - "direction": "IN" - }, - "PIPETX1CHARISK1": { - "direction": "OUT" - }, - "DBGVECA12": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG76": { - "direction": "IN" - }, - "DRPDO15": { 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"OUT" + }, + "PIPERX7DATA14": { + "direction": "IN" + }, + "MIMRXWADDR11": { + "direction": "OUT" + }, + "PLDIRECTEDLINKAUTON": { + "direction": "IN" + }, + "CFGSUBSYSVENDID13": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER37": { + "direction": "IN" + }, + "CFGSUBSYSVENDID1": { + "direction": "IN" + }, + "MIMRXRDATA50": { + "direction": "IN" + }, + "MIMRXWDATA67": { + "direction": "OUT" + }, + "CFGTRANSACTIONADDR0": { + "direction": "OUT" + }, + "MIMRXWDATA22": { + "direction": "OUT" + }, + "MIMTXWDATA22": { + "direction": "OUT" + }, + "PIPERX6DATA2": { + "direction": "IN" + }, + "MIMTXWDATA0": { + "direction": "OUT" + }, + "PLDBGVEC0": { + "direction": "OUT" + }, + "EDTCHANNELSIN6": { + "direction": "IN" + }, + "CFGLINKCONTROLAUTOBANDWIDTHINTEN": { + "direction": "OUT" + }, + "TRNRD28": { + "direction": "OUT" + }, + "CFGMGMTDO6": { + "direction": "OUT" + }, + "CFGVENDID4": { + "direction": "IN" + }, + "TRNRD81": { + "direction": "OUT" + }, + "DRPADDR3": { + "direction": "IN" + }, + "TRNRD19": { + "direction": "OUT" + }, + "CFGDEVID0": { + "direction": "IN" + }, + "CFGMGMTDWADDR0": { + "direction": "IN" + }, + "TL2ERRHDR55": { + "direction": "OUT" + }, + "TRNFCPD9": { + "direction": "OUT" + }, + "PIPERX7CHANISALIGNED": { + "direction": "IN" + }, + "CFGSUBSYSVENDID15": { + "direction": "IN" + }, + "XILUNCONNOUT31": { + "direction": "OUT" + }, + "DRPDO1": { + "direction": "OUT" + }, + "PIPETX7DATA14": { + "direction": "OUT" + }, + "PIPERX4STATUS1": { + "direction": "IN" + }, + "MIMTXWEN": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER38": { + "direction": "IN" + }, + "PIPERX0DATA2": { + "direction": "IN" + }, + "TRNRD58": { + "direction": "OUT" + }, + "CFGDSN7": { + "direction": "IN" + }, + "MIMRXRDATA20": { + "direction": "IN" + }, + "PIPERX1ELECIDLE": { + "direction": "IN" + }, + "CFGFORCEMPS1": { + "direction": "IN" + }, + "TRNRDLLPDATA37": { + "direction": "OUT" + }, + "DRPADDR8": { + "direction": "IN" + }, + "XILUNCONNOUT7": { + "direction": "OUT" + }, + "TRNRD12": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG112": { + "direction": "IN" + }, + "CFGSUBSYSID15": { + "direction": "IN" + }, + "MIMTXRDATA65": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER27": { + "direction": "IN" + }, + "MIMTXWDATA66": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG90": { + "direction": "IN" + }, + "MIMTXWDATA17": { + "direction": "OUT" + }, + "XILUNCONNOUT2": { + "direction": "OUT" + }, "DBGVECB60": { "direction": "OUT" }, - "PIPETX5DATA3": { + "TRNRD62": { "direction": "OUT" }, - "CFGPMCSRPMESTATUS": { + "PIPERX4DATA3": { + "direction": "IN" + }, + "MIMRXRDATA64": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER41": { + "direction": "IN" + }, + "TL2ERRHDR31": { "direction": "OUT" }, - "PIPERX7DATA9": { + "CFGINTERRUPTASSERTN": { + "direction": "IN" + }, + "PIPERX0VALID": { + "direction": "IN" + }, + "CFGAERROOTERRFATALERRRECEIVED": { + "direction": "OUT" + }, + "MIMRXRDATA32": { + "direction": "IN" + }, + "PIPETX0DATA11": { + "direction": "OUT" + }, + "CFGFORCECOMMONCLOCKOFF": { + "direction": "IN" + }, + "PIPERX0STATUS2": { + "direction": "IN" + }, + "MIMRXRDATA23": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMNEW2": { + "direction": "IN" + }, + "PIPERX0DATA6": { + "direction": "IN" + }, + "MIMTXWDATA54": { + "direction": "OUT" + }, + "CFGDSN52": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG11": { + "direction": "IN" + }, + "TRNRBARHIT1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG67": { + "direction": "IN" + }, + "PIPERX5DATA6": { + "direction": "IN" + }, + "TRNTD46": { + "direction": "IN" + }, + "CFGDSDEVICENUMBER4": { + "direction": "IN" + }, + "CFGVENDID12": { + "direction": "IN" + }, + "TRNRD91": { + "direction": "OUT" + }, + "CFGDEVCONTROLCORRERRREPORTINGEN": { + "direction": "OUT" + }, + "MIMTXRDATA17": { + "direction": "IN" + }, + "MIMTXRDATA14": { + "direction": "IN" + }, + "CFGDSBUSNUMBER4": { + "direction": "IN" + }, + "TRNRD98": { + "direction": "OUT" + }, + "CFGINTERRUPTDO7": { + "direction": "OUT" + }, + "TL2PPMSUSPENDREQ": { + "direction": "IN" + }, + "CFGDSN10": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG55": { + "direction": "IN" + }, + "MIMRXWDATA34": { + "direction": "OUT" + }, + "MIMRXWDATA29": { + "direction": "OUT" + }, + "TRNRD127": { + "direction": "OUT" + }, + "CFGDEVSTATUSCORRERRDETECTED": { + "direction": "OUT" + }, + "PIPERX1DATA10": { + "direction": "IN" + }, + "TRNRREM1": { + "direction": "OUT" + }, + "TL2ERRHDR61": { + "direction": "OUT" + }, + "CFGMGMTDI5": { + "direction": "IN" + }, + "TRNRD108": { + "direction": "OUT" + }, + "CFGSUBSYSID7": { + "direction": "IN" + }, + "MIMRXRDATA16": { + "direction": "IN" + }, + "TRNFCCPLH4": { + "direction": "OUT" + }, + "TRNRD116": { + "direction": "OUT" + }, + "EDTCHANNELSIN8": { + "direction": "IN" + }, + "MIMRXWDATA61": { + "direction": "OUT" + }, + "EDTCHANNELSIN5": { + "direction": "IN" + }, + "PIPETX7DATA7": { + "direction": "OUT" + }, + "CFGSUBSYSVENDID12": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER17": { + "direction": "IN" + }, + "TL2ERRHDR29": { + "direction": "OUT" + }, + "PIPERX6DATA9": { + "direction": "IN" + }, + "TRNTBUFAV2": { + "direction": "OUT" + }, + "TL2ERRHDR19": { + "direction": "OUT" + }, + "TRNRD69": { + "direction": "OUT" + }, + "MIMTXWDATA40": { + "direction": "OUT" + }, + "PIPETX5DATA14": { + "direction": "OUT" + }, + "MIMTXRDATA30": { + "direction": "IN" + }, + "MIMRXWDATA33": { + "direction": "OUT" + }, + "TRNRDLLPDATA26": { + "direction": "OUT" + }, + "PIPETX0DATA1": { + "direction": "OUT" + }, + "CFGMGMTDI10": { + "direction": "IN" + }, + "PIPERX1DATA4": { + "direction": "IN" + }, + "DBGVECB57": { + "direction": "OUT" + }, + "PLDIRECTEDLTSSMNEW3": { + "direction": "IN" + }, + "PIPERX3DATA8": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG103": { + "direction": "IN" + }, + "MIMRXRDATA53": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMNEW4": { + "direction": "IN" + }, + "CFGMSGDATA10": { + "direction": "OUT" + }, + "TL2ERRHDR15": { + "direction": "OUT" + }, + "MIMRXWDATA39": { + "direction": "OUT" + }, + "DRPDO12": { + "direction": "OUT" + }, + "MIMTXWDATA65": { + "direction": "OUT" + }, + "TRNTD82": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG17": { + "direction": "IN" + }, + "TRNRD114": { + "direction": "OUT" + }, + "TRNTBUFAV5": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG111": { + "direction": "IN" + }, + "PIPETX0CHARISK1": { + "direction": "OUT" + }, + "XILUNCONNOUT33": { + "direction": "OUT" + }, + "CFGMSGDATA8": { + "direction": "OUT" + }, + "MIMRXWDATA63": { + "direction": "OUT" + }, + "TRNRD78": { + "direction": "OUT" + }, + "PIPETX3DATA8": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG5": { + "direction": "IN" + }, + "DBGVECA16": { + "direction": "OUT" + }, + "CFGERRPOISONEDN": { + "direction": "IN" + }, + "TRNRDLLPDATA54": { + "direction": "OUT" + }, + "TRNRSOF": { + "direction": "OUT" + }, + "TRNRD48": { + "direction": "OUT" + }, + "TRNRD84": { + "direction": "OUT" + }, + "MIMRXRADDR3": { + "direction": "OUT" + }, + "MIMRXWDATA10": { + "direction": "OUT" + }, + "TRNTD65": { + "direction": "IN" + }, + "TRNRD83": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG46": { + "direction": "IN" + }, + "CFGAERROOTERRCORRERRREPORTINGEN": { + "direction": "OUT" + }, + "PIPETX3DATA7": { + "direction": "OUT" + }, + "PIPERX1POLARITY": { + "direction": "OUT" + }, + "CFGDSN0": { + "direction": "IN" + }, + "DBGVECB44": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG81": { + "direction": "IN" + }, + "DBGVECB14": { + "direction": "OUT" + }, + "TRNRD123": { + "direction": "OUT" + }, + "MIMTXRDATA52": { + "direction": "IN" + }, + "PIPERX0DATA10": { + "direction": "IN" + }, + "TRNRDLLPDATA29": { + "direction": "OUT" + }, + "TRNTD9": { "direction": "IN" }, "PIPETX4COMPLIANCE": { "direction": "OUT" }, - "MIMTXRADDR1": { - "direction": "OUT" - }, - "CFGERRAERHEADERLOG19": { + "CFGMGMTDI7": { "direction": "IN" }, - "TL2ERRHDR8": { - "direction": "OUT" - }, - "TRNTD116": { + "PIPERX4DATA1": { "direction": "IN" }, - "TRNTD28": { - "direction": "IN" - }, - "TL2ERRHDR11": { + "TRNFCPD1": { "direction": "OUT" }, - "CFGERRAERHEADERLOG1": { + "PIPETX3ELECIDLE": { + "direction": "OUT" + }, + "TL2ERRHDR20": { + "direction": "OUT" + }, + "USERCLKPREBUF": { "direction": "IN" }, - "DBGVECB2": { + "PIPETX7DATA9": { "direction": "OUT" + }, + "DBGVECA20": { + "direction": "OUT" + }, + "EDTCONFIGURATION": { + "direction": "IN" + }, + "CFGDSN19": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG31": { + "direction": "IN" + }, + "MIMRXRDATA18": { + "direction": "IN" + }, + "PIPERX6STATUS2": { + "direction": "IN" + }, + "PIPERX2DATA2": { + "direction": "IN" + }, + "CFGMGMTDI23": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG21": { + "direction": "IN" + }, + "DBGVECB23": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDASSERTINTA": { + "direction": "OUT" + }, + "CFGPMCSRPOWERSTATE0": { + "direction": "OUT" + }, + "PIPETXDEEMPH": { + "direction": "OUT" + }, + "TRNRBARHIT6": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDERRNONFATAL": { + "direction": "OUT" + }, + "CFGLINKCONTROLEXTENDEDSYNC": { + "direction": "OUT" + }, + "DBGVECA15": { + "direction": "OUT" + }, + "PIPETX0CHARISK0": { + "direction": "OUT" + }, + "CFGMSGDATA7": { + "direction": "OUT" + }, + "TRNTDLLPDATA27": { + "direction": "IN" + }, + "PIPETX1POWERDOWN1": { + "direction": "OUT" + }, + "DBGVECB35": { + "direction": "OUT" + }, + "TRNRD36": { + "direction": "OUT" + }, + "MIMRXRDATA48": { + "direction": "IN" + }, + "PIPERX7ELECIDLE": { + "direction": "IN" + }, + "PIPERX3POLARITY": { + "direction": "OUT" + }, + "PL2SUSPENDOK": { + "direction": "OUT" + }, + "CFGPCIELINKSTATE2": { + "direction": "OUT" + }, + "MIMRXWDATA11": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER39": { + "direction": "IN" + }, + "PIPERX7DATA1": { + "direction": "IN" + }, + "TRNRD96": { + "direction": "OUT" + }, + "SCANMODEN": { + "direction": "IN" + }, + "CFGMSGRECEIVEDPMPME": { + "direction": "OUT" + }, + "TRNRDLLPDATA31": { + "direction": "OUT" + }, + "TRNRD23": { + "direction": "OUT" + }, + "PIPETX6DATA7": { + "direction": "OUT" + }, + "CFGDSN23": { + "direction": "IN" + }, + "CFGDSN42": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG94": { + "direction": "IN" + }, + "TL2ERRHDR46": { + "direction": "OUT" + }, + "PIPERX1CHANISALIGNED": { + "direction": "IN" + }, + "PL2RECOVERY": { + "direction": "OUT" + }, + "PLLINKUPCFGCAP": { + "direction": "OUT" + }, + "CFGVCTCVCMAP6": { + "direction": "OUT" + }, + "PIPETX4DATA11": { + "direction": "OUT" + }, + "TRNTD105": { + "direction": "IN" + }, + "MIMTXRDATA11": { + "direction": "IN" + }, + "TL2ERRHDR17": { + "direction": "OUT" + }, + "PLLINKGEN2CAP": { + "direction": "OUT" + }, + "PIPERX2POLARITY": { + "direction": "OUT" + }, + "TRNTD12": { + "direction": "IN" + }, + "TRNFCNPD6": { + "direction": "OUT" + }, + "MIMTXWADDR12": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG84": { + "direction": "IN" + }, + "TRNRD65": { + "direction": "OUT" + }, + "TRNRDLLPDATA10": { + "direction": "OUT" + }, + "PIPERX7DATA12": { + "direction": "IN" + }, + "TRNRD35": { + "direction": "OUT" + }, + "MIMTXWDATA55": { + "direction": "OUT" + }, + "MIMRXRDATA15": { + "direction": "IN" + }, + "MIMTXWDATA35": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG66": { + "direction": "IN" + }, + "TRNTD111": { + "direction": "IN" + }, + "TRNTDLLPDATA30": { + "direction": "IN" + }, + "CFGMGMTDO7": { + "direction": "OUT" + }, + "MIMRXWDATA62": { + "direction": "OUT" + }, + "TL2ERRHDR18": { + "direction": "OUT" + }, + "TRNTD44": { + "direction": "IN" + }, + "MIMRXRDATA46": { + "direction": "IN" + }, + "CFGDSN38": { + "direction": "IN" + }, + "TRNRDLLPDATA9": { + "direction": "OUT" + }, + "TRNTD62": { + "direction": "IN" + }, + "PLDBGVEC1": { + "direction": "OUT" + }, + "TRNRD20": { + "direction": "OUT" + }, + "MIMRXRDATA56": { + "direction": "IN" + }, + "PIPETX4POWERDOWN1": { + "direction": "OUT" + }, + "MIMRXRADDR5": { + "direction": "OUT" + }, + "CFGDSN5": { + "direction": "IN" + }, + "TRNRD33": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG82": { + "direction": "IN" + }, + "CFGVCTCVCMAP4": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG75": { + "direction": "IN" + }, + "MIMRXRDATA52": { + "direction": "IN" + }, + "PL2RECEIVERERR": { + "direction": "OUT" + }, + "DBGVECA50": { + "direction": "OUT" + }, + "CFGMGMTDO13": { + "direction": "OUT" + }, + "MIMRXRDATA11": { + "direction": "IN" + }, + "PIPETX6DATA9": { + "direction": "OUT" + }, + "TL2ERRHDR54": { + "direction": "OUT" + }, + "TRNTDLLPDATA8": { + "direction": "IN" + }, + "TRNRDLLPSRCRDY0": { + "direction": "OUT" + }, + "MIMRXRADDR1": { + "direction": "OUT" + }, + "TRNTDLLPDATA23": { + "direction": "IN" + }, + "DRPDO4": { + "direction": "OUT" + }, + "PIPETX1DATA0": { + "direction": "OUT" + }, + "DBGVECC4": { + "direction": "OUT" + }, + "DBGVECA32": { + "direction": "OUT" + }, + "CFGREVID7": { + "direction": "IN" + }, + "DBGVECA54": { + "direction": "OUT" + }, + "CFGDEVCONTROL2CPLTIMEOUTVAL2": { + "direction": "OUT" + }, + "PIPETX6CHARISK1": { + "direction": "OUT" + }, + "CFGMGMTBYTEENN3": { + "direction": "IN" + }, + "CFGMGMTDWADDR3": { + "direction": "IN" + }, + "CFGAERINTERRUPTMSGNUM3": { + "direction": "IN" + }, + "PLDIRECTEDLTSSMNEW5": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG12": { + "direction": "IN" + }, + "TRNTD30": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG115": { + "direction": "IN" + }, + "CFGMGMTDO25": { + "direction": "OUT" + }, + "DRPDI1": { + "direction": "IN" + }, + "DBGSCLRH": { + "direction": "OUT" + }, + "PIPERX5ELECIDLE": { + "direction": "IN" + }, + "PIPETX0DATA10": { + "direction": "OUT" + }, + "PIPERX3DATA13": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER3": { + "direction": "IN" + }, + "CFGDSN22": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG30": { + "direction": "IN" + }, + "TRNRDLLPDATA43": { + "direction": "OUT" + }, + "CFGVENDID1": { + "direction": "IN" + }, + "MIMRXWDATA66": { + "direction": "OUT" + }, + "PIPETX4CHARISK1": { + "direction": "OUT" + }, + "CFGINTERRUPTRDYN": { + "direction": "OUT" + }, + "CFGINTERRUPTDI0": { + "direction": "IN" + }, + "TRNTD78": { + "direction": "IN" + }, + "DBGVECB54": { + "direction": "OUT" + }, + "MIMRXRDATA13": { + "direction": "IN" + }, + "TL2ERRHDR59": { + "direction": "OUT" + }, + "DBGVECA2": { + "direction": "OUT" + }, + "CFGDSN61": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG10": { + "direction": "IN" + }, + "PL2RXELECIDLE": { + "direction": "OUT" + }, + "CFGERRECRCN": { + "direction": "IN" + }, + "LL2SUSPENDOK": { + "direction": "OUT" + }, + "DBGVECA29": { + "direction": "OUT" + }, + "CFGERRCPLRDYN": { + "direction": "OUT" + }, + "TRNRD67": { + "direction": "OUT" + }, + "LL2TFCINIT2SEQ": { + "direction": "OUT" + }, + "MIMTXWDATA39": { + "direction": "OUT" + }, + "CFGAERECRCGENEN": { + "direction": "OUT" + }, + "TL2ERRHDR5": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG118": { + "direction": "IN" + }, + "CFGERRAERHEADERLOG87": { + "direction": "IN" + }, + "TRNTD99": { + "direction": "IN" + }, + "TRNRD40": { + "direction": "OUT" + }, + "MIMRXWDATA21": { + "direction": "OUT" + }, + "MIMTXRDATA31": { + "direction": "IN" + }, + "CFGMGMTDO11": { + "direction": "OUT" + }, + "TRNTD3": { + "direction": "IN" + }, + "CFGLINKSTATUSNEGOTIATEDWIDTH2": { + "direction": "OUT" + }, + "MIMTXRDATA38": { + "direction": "IN" + }, + "PIPERX4DATA14": { + "direction": "IN" + }, + "CFGMSGRECEIVEDSETSLOTPOWERLIMIT": { + "direction": "OUT" + }, + "DRPDI6": { + "direction": "IN" + }, + "PIPERX1DATA8": { + "direction": "IN" + }, + "TRNTD109": { + "direction": "IN" + }, + "PIPERX1DATA12": { + "direction": "IN" + }, + "PL2RXPMSTATE1": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG63": { + "direction": "IN" + }, + "CFGDEVCONTROLAUXPOWEREN": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER26": { + "direction": "IN" + }, + "PIPETX5COMPLIANCE": { + "direction": "OUT" + }, + "CFGLINKSTATUSCURRENTSPEED0": { + "direction": "OUT" + }, + "CFGDSN14": { + "direction": "IN" + }, + "DBGVECA45": { + "direction": "OUT" + }, + "CFGMSGDATA5": { + "direction": "OUT" + }, + "TRNRD41": { + "direction": "OUT" + }, + "DBGVECA18": { + "direction": "OUT" + }, + "CFGDSN44": { + "direction": "IN" + }, + "PLDBGVEC10": { + "direction": "OUT" + }, + "DBGVECC10": { + "direction": "OUT" + }, + "TRNRD109": { + "direction": "OUT" + }, + "TRNRD72": { + "direction": "OUT" + }, + "CFGDEVID3": { + "direction": "IN" + }, + "TRNRD0": { + "direction": "OUT" + }, + "MIMTXWDATA42": { + "direction": "OUT" + }, + "CFGERRAERHEADERLOG35": { + "direction": "IN" + }, + "CFGMGMTDWADDR1": { + "direction": "IN" + }, + "CFGINTERRUPTMMENABLE2": { + "direction": "OUT" + }, + "MIMTXRDATA2": { + "direction": "IN" + }, + "DRPADDR5": { + "direction": "IN" + }, + "CFGINTERRUPTMSIXENABLE": { + "direction": "OUT" + }, + "TRNRD18": { + "direction": "OUT" + }, + "CFGERRMCBLOCKEDN": { + "direction": "IN" + }, + "MIMRXWDATA50": { + "direction": "OUT" + }, + "DBGVECB36": { + "direction": "OUT" + }, + "CFGMGMTDI0": { + "direction": "IN" + }, + "MIMRXWDATA36": { + "direction": "OUT" + }, + "CFGMGMTDO19": { + "direction": "OUT" + }, + "PIPETX4POWERDOWN0": { + "direction": "OUT" + }, + "PIPETX4ELECIDLE": { + "direction": "OUT" + }, + "CFGVCTCVCMAP5": { + "direction": "OUT" + }, + "MIMTXRDATA54": { + "direction": "IN" + }, + "CFGDSN40": { + "direction": "IN" + }, + "CFGDSDEVICENUMBER2": { + "direction": "IN" + }, + "CFGSUBSYSID8": { + "direction": "IN" + }, + "MIMTXRDATA43": { + "direction": "IN" + }, + "PIPERX6DATA15": { + "direction": "IN" + }, + "DBGVECA53": { + "direction": "OUT" + }, + "MIMTXRDATA22": { + "direction": "IN" + }, + "DRPDO7": { + "direction": "OUT" + }, + "CFGMSGRECEIVEDDEASSERTINTB": { + "direction": "OUT" + }, + "CFGERRTLPCPLHEADER36": { + "direction": "IN" + }, + "PIPETX2DATA12": { + "direction": "OUT" + }, + "PIPETX1DATA3": { + "direction": "OUT" + }, + "TRNFCSEL0": { + "direction": "IN" + }, + "TRNTD81": { + "direction": "IN" + }, + "PIPERX3VALID": { + "direction": "IN" + }, + "MIMRXWADDR2": { + "direction": "OUT" + }, + "CFGDSN36": { + "direction": "IN" + }, + "DBGVECA28": { + "direction": "OUT" + }, + "PIPERX6DATA6": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER33": { + "direction": "IN" + }, + "PIPETX7DATA13": { + "direction": "OUT" + }, + "EDTCHANNELSOUT5": { + "direction": "OUT" + }, + "TL2ERRHDR47": { + "direction": "OUT" + }, + "PIPETX7POWERDOWN1": { + "direction": "OUT" + }, + "DBGVECB7": { + "direction": "OUT" + }, + "CFGDSN63": { + "direction": "IN" + }, + "CFGDSN15": { + "direction": "IN" + }, + "DBGVECA61": { + "direction": "OUT" + }, + "MIMRXRDATA37": { + "direction": "IN" + }, + "PIPETX7DATA6": { + "direction": "OUT" + }, + "CFGAERINTERRUPTMSGNUM4": { + "direction": "IN" + }, + "CFGERRTLPCPLHEADER29": { + "direction": "IN" + }, + "TL2ERRHDR24": { + "direction": "OUT" + }, + "TL2PPMSUSPENDOK": { + "direction": "OUT" + }, + "TRNTD92": { + "direction": "IN" } - }, - "type": "PCIE_2_1", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_PHASER_IN_PHY.json b/artix7/site_type_PHASER_IN_PHY.json index f2183d9..673747d 100644 --- a/artix7/site_type_PHASER_IN_PHY.json +++ b/artix7/site_type_PHASER_IN_PHY.json @@ -1,291 +1,291 @@ { + "type": "PHASER_IN_PHY", + "site_pips": { + "RSTINV:RST": { + "to_pin": "OUT", + "from_pin": "RST" + }, + "RSTINV:RST_B": { + "to_pin": "OUT", + "from_pin": "RST_B" + } + }, "site_pins": { - "RANKSELPHY1": { + "PHASELOCKED": { + "direction": "OUT" + }, + "ICLKDIV": { + "direction": "OUT" + }, + "TESTIN3": { "direction": "IN" }, + "ICLK": { + "direction": "OUT" + }, + "ENCALIB1": { + "direction": "IN" + }, + "COUNTERREADVAL5": { + "direction": "OUT" + }, + "TESTOUT0": { + "direction": "OUT" + }, + "SCANIN": { + "direction": "IN" + }, + "COUNTERREADVAL3": { + "direction": "OUT" + }, + "SELCALORSTG1": { + "direction": "IN" + }, + "COUNTERLOADVAL2": { + "direction": "IN" + }, + "SYSCLK": { + "direction": "IN" + }, + "SCANENB": { + "direction": "IN" + }, + "SCANCLK": { + "direction": "IN" + }, + "COUNTERREADEN": { + "direction": "IN" + }, + "ENCALIB0": { + "direction": "IN" + }, + "ENSTG1ADJUSTB": { + "direction": "IN" + }, + "STG1REGR2": { + "direction": "OUT" + }, + "TESTIN7": { + "direction": "IN" + }, + "RCLK": { + "direction": "OUT" + }, "COUNTERLOADVAL3": { "direction": "IN" }, "COUNTERLOADVAL4": { "direction": "IN" }, - "STG1REGR8": { - "direction": "OUT" - }, - "ICLKDIV": { - "direction": "OUT" - }, - "DQSOUTOFRANGE": { - "direction": "OUT" - }, - "SYSCLK": { + "TESTIN8": { "direction": "IN" }, - "STG1REGL1": { - "direction": "IN" - }, - "TESTIN12": { - "direction": "IN" - }, - "TESTOUT1": { - "direction": "OUT" - }, - "COUNTERREADVAL5": { - "direction": "OUT" - }, - "STG1REGR5": { - "direction": "OUT" - }, - "STG1REGL8": { - "direction": "IN" - }, - "STG1REGL7": { + "MEMREFCLK": { "direction": "IN" }, "STG1REGL0": { "direction": "IN" }, - "STG1REGR7": { - "direction": "OUT" - }, - "TESTIN7": { - "direction": "IN" - }, - "COUNTERREADVAL2": { - "direction": "OUT" - }, - "STG1REGR1": { - "direction": "OUT" - }, - "STG1REGR6": { - "direction": "OUT" - }, - "STG1REGL4": { - "direction": "IN" - }, - "COUNTERREADVAL1": { - "direction": "OUT" - }, - "STG1REGR3": { - "direction": "OUT" - }, - "TESTIN4": { - "direction": "IN" - }, - "TESTIN2": { - "direction": "IN" - }, - "WRENABLE": { - "direction": "OUT" - }, - "TESTOUT0": { - "direction": "OUT" - }, - "FINEOVERFLOW": { - "direction": "OUT" - }, - "MEMREFCLK": { - "direction": "IN" - }, - "TESTIN3": { - "direction": "IN" - }, - "STG1REGR4": { - "direction": "OUT" - }, - "STG1READ": { - "direction": "IN" - }, - "FINEENABLE": { - "direction": "IN" - }, - "ENCALIB0": { - "direction": "IN" - }, - "RANKSEL0": { - "direction": "IN" - }, "FREQREFCLK": { "direction": "IN" }, - "TESTIN1": { - "direction": "IN" - }, - "BURSTPENDING": { - "direction": "IN" - }, - "STG1REGR0": { - "direction": "OUT" - }, - "STG1REGL3": { - "direction": "IN" - }, - "ENSTG1": { - "direction": "IN" - }, - "BURSTPENDINGPHY": { - "direction": "IN" - }, - "DQSFOUND": { - "direction": "OUT" - }, - "RSTDQSFIND": { - "direction": "IN" - }, - "STG1REGR2": { - "direction": "OUT" - }, - "COUNTERREADVAL0": { - "direction": "OUT" - }, - "TESTOUT3": { - "direction": "OUT" - }, - "EDGEADV": { - "direction": "IN" - }, - "SCANMODEB": { - "direction": "IN" - }, - "TESTIN5": { - "direction": "IN" - }, - "COUNTERLOADEN": { - "direction": "IN" - }, - "COUNTERLOADVAL5": { - "direction": "IN" - }, - "RCLK": { - "direction": "OUT" - }, - "STG1LOAD": { - "direction": "IN" - }, - "STG1OVERFLOW": { - "direction": "OUT" - }, - "TESTIN9": { - "direction": "IN" - }, - "STG1REGL6": { - "direction": "IN" - }, - "ENCALIB1": { - "direction": "IN" - }, - "ISERDESRST": { - "direction": "OUT" - }, - "FINEINC": { - "direction": "IN" - }, - "STG1REGL5": { - "direction": "IN" - }, - "SCANIN": { - "direction": "IN" - }, - "SCANOUT": { - "direction": "OUT" - }, - "RANKSEL1": { - "direction": "IN" - }, - "RANKSELPHY0": { - "direction": "IN" - }, - "PHASEREFCLK": { - "direction": "IN" - }, - "COUNTERLOADVAL0": { - "direction": "IN" - }, - "SCANCLK": { - "direction": "IN" - }, - "TESTIN10": { - "direction": "IN" - }, "ENCALIBPHY1": { "direction": "IN" }, - "SELCALORSTG1": { - "direction": "IN" - }, - "COUNTERREADVAL3": { - "direction": "OUT" - }, - "TESTIN6": { - "direction": "IN" - }, - "COUNTERLOADVAL2": { - "direction": "IN" - }, - "COUNTERREADEN": { - "direction": "IN" - }, - "SYNCIN": { + "STG1REGL3": { "direction": "IN" }, "STG1INCDEC": { "direction": "IN" }, - "TESTOUT2": { - "direction": "OUT" - }, "COUNTERREADVAL4": { "direction": "OUT" }, - "TESTIN0": { - "direction": "IN" - }, - "PHASELOCKED": { + "TESTOUT1": { "direction": "OUT" }, - "RST": { + "TESTIN2": { "direction": "IN" }, - "COUNTERLOADVAL1": { + "PHASEREFCLK": { "direction": "IN" }, - "ENCALIBPHY0": { - "direction": "IN" - }, - "ICLK": { + "STG1REGR7": { "direction": "OUT" }, - "STG1REGL2": { + "FINEENABLE": { "direction": "IN" }, - "SCANENB": { + "STG1REGR3": { + "direction": "OUT" + }, + "DQSFOUND": { + "direction": "OUT" + }, + "RANKSEL0": { + "direction": "IN" + }, + "SCANOUT": { + "direction": "OUT" + }, + "STG1REGR1": { + "direction": "OUT" + }, + "RANKSELPHY0": { + "direction": "IN" + }, + "COUNTERLOADEN": { + "direction": "IN" + }, + "RANKSELPHY1": { + "direction": "IN" + }, + "TESTIN9": { + "direction": "IN" + }, + "TESTIN12": { + "direction": "IN" + }, + "STG1REGL8": { "direction": "IN" }, "DIVIDERST": { "direction": "IN" }, - "TESTIN11": { + "STG1REGL5": { "direction": "IN" }, - "TESTIN8": { + "COUNTERLOADVAL1": { + "direction": "IN" + }, + "STG1READ": { + "direction": "IN" + }, + "FINEINC": { + "direction": "IN" + }, + "RANKSEL1": { + "direction": "IN" + }, + "COUNTERREADVAL1": { + "direction": "OUT" + }, + "ISERDESRST": { + "direction": "OUT" + }, + "FINEOVERFLOW": { + "direction": "OUT" + }, + "COUNTERLOADVAL0": { + "direction": "IN" + }, + "RSTDQSFIND": { + "direction": "IN" + }, + "COUNTERREADVAL2": { + "direction": "OUT" + }, + "STG1REGR0": { + "direction": "OUT" + }, + "BURSTPENDING": { + "direction": "IN" + }, + "TESTIN5": { + "direction": "IN" + }, + "TESTIN6": { + "direction": "IN" + }, + "EDGEADV": { + "direction": "IN" + }, + "STG1LOAD": { "direction": "IN" }, "TESTIN13": { "direction": "IN" }, - "ENSTG1ADJUSTB": { + "STG1REGL4": { "direction": "IN" - } - }, - "type": "PHASER_IN_PHY", - "site_pips": { - "RSTINV:RST": { - "from_pin": "RST", - "to_pin": "OUT" }, - "RSTINV:RST_B": { - "from_pin": "RST_B", - "to_pin": "OUT" + "TESTIN1": { + "direction": "IN" + }, + "STG1REGR5": { + "direction": "OUT" + }, + "BURSTPENDINGPHY": { + "direction": "IN" + }, + "TESTOUT3": { + "direction": "OUT" + }, + "COUNTERLOADVAL5": { + "direction": "IN" + }, + "DQSOUTOFRANGE": { + "direction": "OUT" + }, + "WRENABLE": { + "direction": "OUT" + }, + "SYNCIN": { + "direction": "IN" + }, + "TESTIN10": { + "direction": "IN" + }, + "TESTIN11": { + "direction": "IN" + }, + "STG1REGR8": { + "direction": "OUT" + }, + "STG1REGL6": { + "direction": "IN" + }, + "STG1REGR6": { + "direction": "OUT" + }, + "RST": { + "direction": "IN" + }, + "STG1REGL7": { + "direction": "IN" + }, + "SCANMODEB": { + "direction": "IN" + }, + "STG1REGL2": { + "direction": "IN" + }, + "TESTIN0": { + "direction": "IN" + }, + "ENSTG1": { + "direction": "IN" + }, + "STG1REGR4": { + "direction": "OUT" + }, + "STG1OVERFLOW": { + "direction": "OUT" + }, + "TESTIN4": { + "direction": "IN" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "ENCALIBPHY0": { + "direction": "IN" + }, + "COUNTERREADVAL0": { + "direction": "OUT" + }, + "STG1REGL1": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_PHASER_OUT_PHY.json b/artix7/site_type_PHASER_OUT_PHY.json index f036658..d84a596 100644 --- a/artix7/site_type_PHASER_OUT_PHY.json +++ b/artix7/site_type_PHASER_OUT_PHY.json @@ -1,246 +1,246 @@ { + "type": "PHASER_OUT_PHY", + "site_pips": { + "RSTINV:RST": { + "to_pin": "OUT", + "from_pin": "RST" + }, + "RSTINV:RST_B": { + "to_pin": "OUT", + "from_pin": "RST_B" + } + }, "site_pins": { - "BURSTPENDINGPHY": { + "TESTIN15": { "direction": "IN" }, "COUNTERLOADVAL8": { "direction": "IN" }, - "COARSEOVERFLOW": { - "direction": "OUT" - }, - "OCLK": { - "direction": "OUT" - }, - "COUNTERLOADVAL4": { - "direction": "IN" - }, - "SYSCLK": { - "direction": "IN" - }, - "COUNTERREADVAL0": { - "direction": "OUT" - }, - "CTSBUS0": { - "direction": "OUT" - }, - "TESTIN9": { - "direction": "IN" - }, - "COUNTERLOADVAL6": { - "direction": "IN" - }, - "TESTOUT3": { - "direction": "OUT" - }, - "EDGEADV": { - "direction": "IN" - }, - "TESTIN14": { - "direction": "IN" - }, - "TESTIN15": { - "direction": "IN" - }, - "COARSEINC": { - "direction": "IN" - }, - "FINEINC": { - "direction": "IN" - }, - "TESTIN12": { - "direction": "IN" - }, - "TESTOUT1": { - "direction": "OUT" - }, - "RDENABLE": { - "direction": "OUT" - }, - "TESTIN5": { - "direction": "IN" - }, - "COUNTERLOADEN": { - "direction": "IN" - }, - "TESTIN1": { - "direction": "IN" - }, - "COUNTERLOADVAL5": { - "direction": "IN" - }, - "COARSEENABLE": { - "direction": "IN" - }, - "SYNCIN": { - "direction": "IN" - }, - "ENCALIBPHY0": { - "direction": "IN" - }, - "TESTIN7": { - "direction": "IN" - }, - "TESTIN13": { - "direction": "IN" - }, - "ENCALIB1": { - "direction": "IN" - }, - "COUNTERREADVAL7": { - "direction": "OUT" - }, - "SCANCLK": { - "direction": "IN" - }, - "FINEENABLE": { - "direction": "IN" - }, - "COUNTERLOADVAL3": { - "direction": "IN" - }, - "SCANMODEB": { - "direction": "IN" - }, - "DQSBUS0": { - "direction": "OUT" - }, - "DQSBUS1": { - "direction": "OUT" - }, - "TESTOUT0": { - "direction": "OUT" - }, - "SCANOUT": { - "direction": "OUT" - }, - "COUNTERREADVAL6": { - "direction": "OUT" - }, - "SCANIN": { - "direction": "IN" - }, - "COUNTERREADVAL2": { - "direction": "OUT" - }, - "PHASEREFCLK": { - "direction": "IN" - }, - "COUNTERLOADVAL0": { + "DIVIDERST": { "direction": "IN" }, "COUNTERLOADVAL1": { "direction": "IN" }, - "COUNTERLOADVAL2": { - "direction": "IN" - }, - "SELFINEOCLKDELAY": { - "direction": "IN" - }, - "COUNTERREADVAL8": { - "direction": "OUT" - }, - "RST": { - "direction": "IN" - }, - "COUNTERREADVAL1": { - "direction": "OUT" - }, - "TESTIN10": { - "direction": "IN" - }, - "ENCALIBPHY1": { - "direction": "IN" - }, - "OCLKDELAYED": { - "direction": "OUT" - }, - "COUNTERREADVAL3": { - "direction": "OUT" - }, - "TESTIN6": { - "direction": "IN" - }, - "TESTIN4": { - "direction": "IN" - }, - "TESTIN2": { - "direction": "IN" - }, - "COUNTERREADEN": { - "direction": "IN" - }, - "OSERDESRST": { - "direction": "OUT" - }, - "OCLKDIV": { - "direction": "OUT" - }, - "DTSBUS1": { - "direction": "OUT" - }, - "FINEOVERFLOW": { - "direction": "OUT" - }, - "MEMREFCLK": { - "direction": "IN" - }, - "TESTOUT2": { - "direction": "OUT" - }, - "COUNTERREADVAL4": { + "COUNTERREADVAL7": { "direction": "OUT" }, "TESTIN3": { "direction": "IN" }, - "TESTIN0": { + "FINEINC": { "direction": "IN" }, - "COUNTERLOADVAL7": { + "TESTIN4": { "direction": "IN" }, - "ENCALIB0": { + "ENCALIB1": { "direction": "IN" }, - "FREQREFCLK": { + "COUNTERREADVAL4": { + "direction": "OUT" + }, + "COUNTERLOADVAL6": { + "direction": "IN" + }, + "TESTOUT0": { + "direction": "OUT" + }, + "SCANIN": { + "direction": "IN" + }, + "DTSBUS1": { + "direction": "OUT" + }, + "COUNTERREADVAL3": { + "direction": "OUT" + }, + "CTSBUS0": { + "direction": "OUT" + }, + "COUNTERREADVAL1": { + "direction": "OUT" + }, + "FINEOVERFLOW": { + "direction": "OUT" + }, + "COUNTERLOADVAL0": { "direction": "IN" }, "CTSBUS1": { "direction": "OUT" }, - "COUNTERREADVAL5": { + "OSERDESRST": { + "direction": "OUT" + }, + "COARSEENABLE": { + "direction": "IN" + }, + "COUNTERLOADVAL2": { + "direction": "IN" + }, + "RDENABLE": { + "direction": "OUT" + }, + "SYSCLK": { + "direction": "IN" + }, + "OCLK": { "direction": "OUT" }, "BURSTPENDING": { "direction": "IN" }, - "DIVIDERST": { + "SCANCLK": { "direction": "IN" }, - "SCANENB": { + "TESTIN14": { + "direction": "IN" + }, + "TESTIN5": { + "direction": "IN" + }, + "COUNTERREADEN": { + "direction": "IN" + }, + "COUNTERREADVAL8": { + "direction": "OUT" + }, + "ENCALIB0": { + "direction": "IN" + }, + "EDGEADV": { + "direction": "IN" + }, + "TESTIN7": { + "direction": "IN" + }, + "COARSEINC": { + "direction": "IN" + }, + "TESTIN6": { + "direction": "IN" + }, + "TESTIN13": { + "direction": "IN" + }, + "TESTOUT1": { + "direction": "OUT" + }, + "OCLKDIV": { + "direction": "OUT" + }, + "COUNTERLOADVAL3": { + "direction": "IN" + }, + "COARSEOVERFLOW": { + "direction": "OUT" + }, + "TESTIN11": { + "direction": "IN" + }, + "TESTIN8": { + "direction": "IN" + }, + "MEMREFCLK": { + "direction": "IN" + }, + "TESTOUT3": { + "direction": "OUT" + }, + "COUNTERLOADVAL5": { "direction": "IN" }, "DTSBUS0": { "direction": "OUT" }, - "TESTIN8": { + "FREQREFCLK": { "direction": "IN" }, - "TESTIN11": { + "ENCALIBPHY1": { "direction": "IN" - } - }, - "type": "PHASER_OUT_PHY", - "site_pips": { - "RSTINV:RST": { - "from_pin": "RST", - "to_pin": "OUT" }, - "RSTINV:RST_B": { - "from_pin": "RST_B", - "to_pin": "OUT" + "ENCALIBPHY0": { + "direction": "IN" + }, + "DQSBUS1": { + "direction": "OUT" + }, + "COUNTERLOADVAL7": { + "direction": "IN" + }, + "TESTIN10": { + "direction": "IN" + }, + "SELFINEOCLKDELAY": { + "direction": "IN" + }, + "TESTIN2": { + "direction": "IN" + }, + "PHASEREFCLK": { + "direction": "IN" + }, + "TESTIN1": { + "direction": "IN" + }, + "COUNTERREADVAL5": { + "direction": "OUT" + }, + "DQSBUS0": { + "direction": "OUT" + }, + "FINEENABLE": { + "direction": "IN" + }, + "OCLKDELAYED": { + "direction": "OUT" + }, + "RST": { + "direction": "IN" + }, + "SYNCIN": { + "direction": "IN" + }, + "BURSTPENDINGPHY": { + "direction": "IN" + }, + "COUNTERREADVAL0": { + "direction": "OUT" + }, + "COUNTERLOADVAL4": { + "direction": "IN" + }, + "SCANOUT": { + "direction": "OUT" + }, + "SCANMODEB": { + "direction": "IN" + }, + "TESTIN0": { + "direction": "IN" + }, + "SCANENB": { + "direction": "IN" + }, + "COUNTERLOADEN": { + "direction": "IN" + }, + "COUNTERREADVAL2": { + "direction": "OUT" + }, + "COUNTERREADVAL6": { + "direction": "OUT" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "TESTIN9": { + "direction": "IN" + }, + "TESTIN12": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_PHASER_REF.json b/artix7/site_type_PHASER_REF.json index 241fe10..9c7a3d8 100644 --- a/artix7/site_type_PHASER_REF.json +++ b/artix7/site_type_PHASER_REF.json @@ -1,89 +1,89 @@ { - "site_pins": { - "TESTOUT4": { - "direction": "OUT" + "type": "PHASER_REF", + "site_pips": { + "PWRDWNINV:PWRDWN_B": { + "to_pin": "OUT", + "from_pin": "PWRDWN_B" }, - "CLKOUT": { + "RSTINV:RST": { + "to_pin": "OUT", + "from_pin": "RST" + }, + "RSTINV:RST_B": { + "to_pin": "OUT", + "from_pin": "RST_B" + }, + "PWRDWNINV:PWRDWN": { + "to_pin": "OUT", + "from_pin": "PWRDWN" + } + }, + "site_pins": { + "TESTOUT3": { "direction": "OUT" }, "TMUXOUT": { "direction": "OUT" }, - "TESTIN3": { - "direction": "IN" - }, - "RST": { - "direction": "IN" - }, - "TESTOUT3": { - "direction": "OUT" - }, - "PWRDWN": { - "direction": "IN" - }, - "TESTIN6": { - "direction": "IN" - }, "TESTIN4": { "direction": "IN" }, - "TESTIN2": { - "direction": "IN" - }, - "TESTOUT5": { - "direction": "OUT" - }, - "TESTOUT2": { - "direction": "OUT" - }, - "TESTOUT6": { - "direction": "OUT" - }, "TESTIN0": { "direction": "IN" }, - "LOCKED": { - "direction": "OUT" - }, - "CLKIN": { - "direction": "IN" - }, - "TESTOUT7": { - "direction": "OUT" - }, - "TESTOUT1": { - "direction": "OUT" - }, - "TESTIN1": { - "direction": "IN" - }, "TESTOUT0": { "direction": "OUT" }, - "TESTIN7": { + "TESTOUT1": { + "direction": "OUT" + }, + "CLKOUT": { + "direction": "OUT" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "LOCKED": { + "direction": "OUT" + }, + "RST": { "direction": "IN" }, + "TESTOUT7": { + "direction": "OUT" + }, + "TESTOUT4": { + "direction": "OUT" + }, "TESTIN5": { "direction": "IN" - } - }, - "type": "PHASER_REF", - "site_pips": { - "RSTINV:RST": { - "from_pin": "RST", - "to_pin": "OUT" }, - "PWRDWNINV:PWRDWN": { - "from_pin": "PWRDWN", - "to_pin": "OUT" + "TESTIN6": { + "direction": "IN" }, - "PWRDWNINV:PWRDWN_B": { - "from_pin": "PWRDWN_B", - "to_pin": "OUT" + "PWRDWN": { + "direction": "IN" }, - "RSTINV:RST_B": { - "from_pin": "RST_B", - "to_pin": "OUT" + "TESTOUT5": { + "direction": "OUT" + }, + "TESTOUT6": { + "direction": "OUT" + }, + "TESTIN7": { + "direction": "IN" + }, + "TESTIN3": { + "direction": "IN" + }, + "TESTIN2": { + "direction": "IN" + }, + "CLKIN": { + "direction": "IN" + }, + "TESTIN1": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_PHY_CONTROL.json b/artix7/site_type_PHY_CONTROL.json index 036d4a4..1b0347d 100644 --- a/artix7/site_type_PHY_CONTROL.json +++ b/artix7/site_type_PHY_CONTROL.json @@ -1,36 +1,8 @@ { + "type": "PHY_CONTROL", + "site_pips": {}, "site_pins": { - "TESTOUTPUT6": { - "direction": "OUT" - }, - "PHYCTLWD2": { - "direction": "IN" - }, - "READCALIBENABLE": { - "direction": "IN" - }, - "INBURSTPENDING2": { - "direction": "OUT" - }, - "PHYCTLWD9": { - "direction": "IN" - }, - "TESTINPUT4": { - "direction": "IN" - }, - "PHYCTLWD6": { - "direction": "IN" - }, - "TESTOUTPUT5": { - "direction": "OUT" - }, - "PHYCTLWD28": { - "direction": "IN" - }, - "TESTOUTPUT13": { - "direction": "OUT" - }, - "PHYCTLREADY": { + "AUXOUTPUT1": { "direction": "OUT" }, "PHYCTLWD25": { @@ -39,280 +11,308 @@ "INRANKB1": { "direction": "OUT" }, - "TESTOUTPUT10": { - "direction": "OUT" - }, - "TESTOUTPUT4": { - "direction": "OUT" - }, - "PHYCTLWD22": { - "direction": "IN" - }, - "TESTINPUT15": { - "direction": "IN" - }, - "PHYCTLWD5": { - "direction": "IN" - }, - "TESTOUTPUT0": { - "direction": "OUT" - }, - "OUTBURSTPENDING2": { - "direction": "OUT" - }, - "TESTOUTPUT1": { - "direction": "OUT" - }, - "TESTINPUT1": { - "direction": "IN" - }, - "INRANKA1": { - "direction": "OUT" - }, - "PHYCTLWD3": { - "direction": "IN" - }, - "TESTINPUT0": { - "direction": "IN" - }, - "PHYCTLWD24": { - "direction": "IN" - }, - "AUXOUTPUT0": { - "direction": "OUT" - }, - "PHYCTLWD23": { - "direction": "IN" - }, - "PHYCTLWD20": { - "direction": "IN" - }, - "INBURSTPENDING0": { - "direction": "OUT" - }, - "PHYCTLEMPTY": { - "direction": "OUT" - }, - "SCANENABLEN": { - "direction": "IN" - }, - "PHYCLK": { - "direction": "IN" - }, - "PHYCTLWD4": { - "direction": "IN" - }, - "OUTBURSTPENDING3": { - "direction": "OUT" - }, - "TESTSELECT2": { - "direction": "IN" - }, - "PHYCTLWD15": { - "direction": "IN" - }, - "PHYCTLWD11": { - "direction": "IN" - }, - "PHYCTLWD16": { - "direction": "IN" - }, - "RESET": { - "direction": "IN" - }, - "PHYCTLWD29": { - "direction": "IN" - }, - "PHYCTLALMOSTFULL": { - "direction": "OUT" - }, - "TESTOUTPUT11": { - "direction": "OUT" - }, - "PHYCTLWD10": { - "direction": "IN" - }, - "TESTINPUT6": { - "direction": "IN" - }, - "PHYCTLWD14": { - "direction": "IN" - }, - "MEMREFCLK": { - "direction": "IN" - }, - "PHYCTLWD21": { - "direction": "IN" - }, - "INBURSTPENDING1": { - "direction": "OUT" - }, - "TESTOUTPUT7": { - "direction": "OUT" - }, - "TESTOUTPUT15": { - "direction": "OUT" - }, - "TESTINPUT11": { - "direction": "IN" - }, - "PHYCTLWD31": { - "direction": "IN" - }, - "INBURSTPENDING3": { - "direction": "OUT" - }, - "AUXOUTPUT1": { - "direction": "OUT" - }, - "PCENABLECALIB1": { - "direction": "OUT" - }, - "PHYCTLWD0": { - "direction": "IN" - }, - "WRITECALIBENABLE": { - "direction": "IN" - }, - "TESTOUTPUT12": { - "direction": "OUT" - }, - "INRANKB0": { - "direction": "OUT" - }, - "TESTINPUT10": { - "direction": "IN" - }, - "TESTINPUT8": { - "direction": "IN" - }, - "REFDLLLOCK": { - "direction": "IN" - }, - "TESTOUTPUT9": { - "direction": "OUT" - }, - "PHYCTLWD7": { - "direction": "IN" - }, - "TESTOUTPUT14": { - "direction": "OUT" - }, - "OUTBURSTPENDING1": { - "direction": "OUT" - }, - "INRANKA0": { - "direction": "OUT" - }, - "TESTSELECT0": { - "direction": "IN" - }, - "INRANKC1": { - "direction": "OUT" - }, - "PHYCTLWD13": { - "direction": "IN" - }, - "PLLLOCK": { - "direction": "IN" - }, - "TESTINPUT5": { - "direction": "IN" - }, - "TESTOUTPUT8": { - "direction": "OUT" - }, - "PCENABLECALIB0": { - "direction": "OUT" - }, - "PHYCTLWD27": { - "direction": "IN" - }, - "TESTINPUT13": { - "direction": "IN" - }, - "AUXOUTPUT3": { - "direction": "OUT" - }, - "AUXOUTPUT2": { - "direction": "OUT" - }, - "PHYCTLFULL": { - "direction": "OUT" - }, - "PHYCTLWD19": { - "direction": "IN" - }, - "PHYCTLWD1": { - "direction": "IN" - }, - "PHYCTLWD26": { - "direction": "IN" - }, - "INRANKD0": { - "direction": "OUT" - }, "PHYCTLWD30": { "direction": "IN" }, - "TESTINPUT14": { - "direction": "IN" - }, - "TESTOUTPUT3": { - "direction": "OUT" - }, - "PHYCTLWD18": { - "direction": "IN" - }, "TESTOUTPUT2": { "direction": "OUT" }, - "INRANKC0": { + "TESTINPUT7": { + "direction": "IN" + }, + "PHYCTLWD20": { + "direction": "IN" + }, + "TESTINPUT10": { + "direction": "IN" + }, + "TESTOUTPUT12": { "direction": "OUT" }, - "PHYCTLWD8": { + "PHYCTLWD18": { "direction": "IN" }, - "TESTINPUT9": { + "PHYCTLWD14": { "direction": "IN" }, - "SYNCIN": { + "INBURSTPENDING3": { + "direction": "OUT" + }, + "TESTOUTPUT15": { + "direction": "OUT" + }, + "PHYCLK": { + "direction": "IN" + }, + "PHYCTLWD2": { + "direction": "IN" + }, + "TESTINPUT11": { + "direction": "IN" + }, + "OUTBURSTPENDING3": { + "direction": "OUT" + }, + "MEMREFCLK": { "direction": "IN" }, "OUTBURSTPENDING0": { "direction": "OUT" }, - "PHYCTLWD17": { + "PHYCTLMSTREMPTY": { "direction": "IN" }, - "TESTINPUT12": { - "direction": "IN" - }, - "INRANKD1": { + "OUTBURSTPENDING1": { "direction": "OUT" }, - "PHYCTLWD12": { + "PHYCTLWD1": { + "direction": "IN" + }, + "PHYCTLWD19": { + "direction": "IN" + }, + "PHYCTLWD29": { "direction": "IN" }, "TESTINPUT3": { "direction": "IN" }, - "PHYCTLMSTREMPTY": { + "TESTINPUT9": { + "direction": "IN" + }, + "PCENABLECALIB1": { + "direction": "OUT" + }, + "PHYCTLWD26": { + "direction": "IN" + }, + "AUXOUTPUT2": { + "direction": "OUT" + }, + "PHYCTLWD5": { + "direction": "IN" + }, + "TESTINPUT8": { + "direction": "IN" + }, + "READCALIBENABLE": { + "direction": "IN" + }, + "PHYCTLWD11": { + "direction": "IN" + }, + "TESTSELECT2": { + "direction": "IN" + }, + "INBURSTPENDING1": { + "direction": "OUT" + }, + "PHYCTLWD27": { + "direction": "IN" + }, + "TESTINPUT5": { + "direction": "IN" + }, + "TESTOUTPUT10": { + "direction": "OUT" + }, + "PHYCTLWD21": { + "direction": "IN" + }, + "TESTOUTPUT4": { + "direction": "OUT" + }, + "TESTOUTPUT5": { + "direction": "OUT" + }, + "TESTINPUT4": { + "direction": "IN" + }, + "INRANKA0": { + "direction": "OUT" + }, + "TESTOUTPUT8": { + "direction": "OUT" + }, + "PHYCTLWD28": { + "direction": "IN" + }, + "TESTOUTPUT14": { + "direction": "OUT" + }, + "TESTOUTPUT13": { + "direction": "OUT" + }, + "PHYCTLWD9": { + "direction": "IN" + }, + "PHYCTLWD4": { + "direction": "IN" + }, + "INRANKC0": { + "direction": "OUT" + }, + "REFDLLLOCK": { + "direction": "IN" + }, + "WRITECALIBENABLE": { "direction": "IN" }, "PHYCTLWRENABLE": { "direction": "IN" }, - "TESTINPUT7": { + "PHYCTLREADY": { + "direction": "OUT" + }, + "TESTINPUT6": { "direction": "IN" }, + "INRANKC1": { + "direction": "OUT" + }, + "PHYCTLWD8": { + "direction": "IN" + }, + "PHYCTLWD15": { + "direction": "IN" + }, + "PHYCTLWD17": { + "direction": "IN" + }, + "INBURSTPENDING2": { + "direction": "OUT" + }, + "INBURSTPENDING0": { + "direction": "OUT" + }, + "PHYCTLWD13": { + "direction": "IN" + }, + "AUXOUTPUT0": { + "direction": "OUT" + }, + "PHYCTLWD10": { + "direction": "IN" + }, + "PHYCTLWD7": { + "direction": "IN" + }, + "TESTINPUT0": { + "direction": "IN" + }, + "RESET": { + "direction": "IN" + }, + "PHYCTLFULL": { + "direction": "OUT" + }, + "PHYCTLWD24": { + "direction": "IN" + }, + "INRANKA1": { + "direction": "OUT" + }, + "PHYCTLWD6": { + "direction": "IN" + }, + "PHYCTLALMOSTFULL": { + "direction": "OUT" + }, + "INRANKD1": { + "direction": "OUT" + }, + "INRANKD0": { + "direction": "OUT" + }, + "TESTOUTPUT9": { + "direction": "OUT" + }, + "PHYCTLWD23": { + "direction": "IN" + }, + "PLLLOCK": { + "direction": "IN" + }, + "PHYCTLWD12": { + "direction": "IN" + }, + "TESTINPUT12": { + "direction": "IN" + }, + "PCENABLECALIB0": { + "direction": "OUT" + }, + "PHYCTLWD16": { + "direction": "IN" + }, + "AUXOUTPUT3": { + "direction": "OUT" + }, + "TESTOUTPUT3": { + "direction": "OUT" + }, + "PHYCTLWD22": { + "direction": "IN" + }, + "TESTOUTPUT0": { + "direction": "OUT" + }, + "SYNCIN": { + "direction": "IN" + }, + "INRANKB0": { + "direction": "OUT" + }, "TESTSELECT1": { "direction": "IN" }, + "TESTINPUT13": { + "direction": "IN" + }, + "TESTSELECT0": { + "direction": "IN" + }, + "TESTOUTPUT11": { + "direction": "OUT" + }, + "TESTINPUT14": { + "direction": "IN" + }, "TESTINPUT2": { "direction": "IN" + }, + "TESTINPUT1": { + "direction": "IN" + }, + "TESTINPUT15": { + "direction": "IN" + }, + "PHYCTLWD31": { + "direction": "IN" + }, + "TESTOUTPUT7": { + "direction": "OUT" + }, + "PHYCTLEMPTY": { + "direction": "OUT" + }, + "OUTBURSTPENDING2": { + "direction": "OUT" + }, + "TESTOUTPUT6": { + "direction": "OUT" + }, + "PHYCTLWD3": { + "direction": "IN" + }, + "TESTOUTPUT1": { + "direction": "OUT" + }, + "SCANENABLEN": { + "direction": "IN" + }, + "PHYCTLWD0": { + "direction": "IN" } - }, - "type": "PHY_CONTROL", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_PLLE2_ADV.json b/artix7/site_type_PLLE2_ADV.json index cb55bec..816f5a6 100644 --- a/artix7/site_type_PLLE2_ADV.json +++ b/artix7/site_type_PLLE2_ADV.json @@ -1,493 +1,493 @@ { + "type": "PLLE2_ADV", + "site_pips": { + "CLKINSELINV:CLKINSEL": { + "to_pin": "OUT", + "from_pin": "CLKINSEL" + }, + "RSTINV:RST": { + "to_pin": "OUT", + "from_pin": "RST" + }, + "RSTINV:RST_B": { + "to_pin": "OUT", + "from_pin": "RST_B" + }, + "PWRDWNINV:PWRDWN_B": { + "to_pin": "OUT", + "from_pin": "PWRDWN_B" + }, + "CLKINSELINV:CLKINSEL_B": { + "to_pin": "OUT", + "from_pin": "CLKINSEL_B" + }, + "PWRDWNINV:PWRDWN": { + "to_pin": "OUT", + "from_pin": "PWRDWN" + } + }, "site_pins": { - "TESTIN17": { - "direction": "IN" - }, - "TESTOUT28": { - "direction": "OUT" - }, - "TESTOUT22": { - "direction": "OUT" - }, - "TESTOUT46": { - "direction": "OUT" - }, - "TESTOUT4": { - "direction": "OUT" - }, - "CLKOUT2": { - "direction": "OUT" - }, - "DADDR0": { - "direction": "IN" - }, - "TESTOUT15": { - "direction": "OUT" - }, - "DI3": { - "direction": "IN" - }, - "TESTOUT27": { - "direction": "OUT" - }, - "TESTIN25": { - "direction": "IN" - }, - "DO0": { - "direction": "OUT" - }, - "TESTOUT25": { - "direction": "OUT" - }, - "DI8": { - "direction": "IN" - }, - "CLKOUT0": { - "direction": "OUT" - }, - "TESTIN28": { - "direction": "IN" - }, - "TESTOUT6": { - "direction": "OUT" - }, - "TESTOUT31": { - "direction": "OUT" - }, - "DADDR2": { - "direction": "IN" - }, - "TESTIN12": { - "direction": "IN" - }, - "TESTOUT1": { - "direction": "OUT" - }, - "TESTOUT12": { - "direction": "OUT" - }, - "PWRDWN": { - "direction": "IN" - }, - "DO5": { - "direction": "OUT" - }, - "TESTIN26": { - "direction": "IN" - }, - "DI6": { - "direction": "IN" - }, - "TESTIN23": { - "direction": "IN" - }, - "DCLK": { - "direction": "IN" - }, - "TESTOUT23": { - "direction": "OUT" - }, - "CLKINSEL": { - "direction": "IN" - }, - "DADDR4": { - "direction": "IN" - }, - "TESTIN14": { - "direction": "IN" - }, - "TESTOUT9": { - "direction": "OUT" - }, - "TESTOUT42": { - "direction": "OUT" - }, - "TESTOUT32": { - "direction": "OUT" - }, - "TESTOUT39": { - "direction": "OUT" - }, - "DI10": { - "direction": "IN" - }, - "TESTOUT5": { - "direction": "OUT" - }, - "DI12": { - "direction": "IN" - }, - "TESTOUT38": { - "direction": "OUT" - }, - "DADDR1": { - "direction": "IN" - }, - "TESTOUT53": { - "direction": "OUT" - }, - "DI5": { - "direction": "IN" - }, - "TESTOUT47": { - "direction": "OUT" - }, - "CLKFBIN": { - "direction": "IN" - }, - "TESTOUT26": { - "direction": "OUT" - }, - "TESTIN31": { - "direction": "IN" - }, - "DO2": { - "direction": "OUT" - }, - "TMUXOUT": { - "direction": "OUT" - }, - "TESTOUT30": { - "direction": "OUT" - }, - "RST": { - "direction": "IN" - }, - "TESTIN30": { - "direction": "IN" - }, - "DRDY": { - "direction": "OUT" - }, - "TESTIN16": { - "direction": "IN" - }, - "DEN": { - "direction": "IN" - }, - "TESTOUT52": { - "direction": "OUT" - }, - "CLKOUT1": { - "direction": "OUT" - }, - "TESTIN4": { - "direction": "IN" - }, - "TESTIN2": { - "direction": "IN" - }, - "TESTOUT37": { - "direction": "OUT" - }, - "TESTOUT0": { - "direction": "OUT" - }, - "TESTIN18": { - "direction": "IN" - }, - "TESTOUT40": { - "direction": "OUT" - }, - "TESTOUT57": { - "direction": "OUT" - }, - "CLKOUT3": { - "direction": "OUT" - }, - "TESTOUT33": { - "direction": "OUT" - }, - "TESTOUT35": { - "direction": "OUT" - }, - "TESTOUT20": { - "direction": "OUT" - }, - "DO12": { - "direction": "OUT" - }, - "TESTOUT59": { - "direction": "OUT" - }, - "TESTIN1": { - "direction": "IN" - }, - "TESTOUT44": { - "direction": "OUT" - }, - "TESTIN22": { - "direction": "IN" - }, - "TESTIN3": { + "TESTIN15": { "direction": "IN" }, "DO9": { "direction": "OUT" }, - "TESTOUT58": { - "direction": "OUT" - }, - "TESTIN0": { - "direction": "IN" - }, - "DO10": { - "direction": "OUT" - }, - "TESTOUT17": { - "direction": "OUT" - }, - "CLKIN2": { - "direction": "IN" - }, - "CLKIN1": { - "direction": "IN" - }, - "LOCKED": { - "direction": "OUT" - }, - "DO8": { - "direction": "OUT" - }, - "DI9": { - "direction": "IN" - }, - "DO6": { - "direction": "OUT" - }, - "TESTOUT51": { - "direction": "OUT" - }, - "TESTOUT34": { - "direction": "OUT" - }, - "TESTOUT55": { - "direction": "OUT" - }, - "TESTIN29": { - "direction": "IN" - }, - "DI13": { - "direction": "IN" - }, - "DADDR6": { - "direction": "IN" - }, - "DI1": { - "direction": "IN" - }, - "TESTIN27": { - "direction": "IN" - }, - "TESTOUT3": { - "direction": "OUT" - }, - "TESTOUT61": { - "direction": "OUT" - }, - "TESTIN15": { - "direction": "IN" - }, - "CLKOUT5": { - "direction": "OUT" - }, - "DO7": { - "direction": "OUT" - }, - "TESTOUT18": { - "direction": "OUT" - }, "DI0": { "direction": "IN" }, - "TESTIN5": { - "direction": "IN" - }, - "TESTOUT43": { + "TESTOUT57": { "direction": "OUT" }, - "TESTIN21": { - "direction": "IN" - }, - "DO3": { + "TMUXOUT": { "direction": "OUT" }, - "CLKOUT4": { - "direction": "OUT" - }, - "DO14": { - "direction": "OUT" - }, - "TESTIN9": { - "direction": "IN" - }, - "TESTIN13": { - "direction": "IN" - }, - "DO4": { - "direction": "OUT" - }, - "DO11": { - "direction": "OUT" - }, - "TESTIN24": { - "direction": "IN" - }, - "TESTOUT19": { - "direction": "OUT" - }, - "TESTOUT13": { - "direction": "OUT" - }, - "DI7": { - "direction": "IN" - }, - "TESTIN7": { - "direction": "IN" - }, - "TESTOUT10": { - "direction": "OUT" - }, - "TESTOUT60": { - "direction": "OUT" - }, - "TESTOUT8": { - "direction": "OUT" - }, - "TESTOUT45": { - "direction": "OUT" - }, - "TESTOUT7": { - "direction": "OUT" - }, - "TESTOUT50": { - "direction": "OUT" - }, - "DO15": { - "direction": "OUT" - }, - "TESTOUT49": { - "direction": "OUT" - }, - "TESTOUT21": { - "direction": "OUT" - }, - "TESTIN19": { + "CLKIN1": { "direction": "IN" }, "DI15": { "direction": "IN" }, - "TESTOUT29": { - "direction": "OUT" - }, - "TESTOUT36": { - "direction": "OUT" - }, - "TESTOUT24": { - "direction": "OUT" - }, - "TESTOUT54": { - "direction": "OUT" - }, - "TESTOUT63": { - "direction": "OUT" - }, - "TESTIN10": { + "TESTIN5": { "direction": "IN" }, + "TESTOUT0": { + "direction": "OUT" + }, + "DADDR0": { + "direction": "IN" + }, + "TESTOUT21": { + "direction": "OUT" + }, + "TESTOUT22": { + "direction": "OUT" + }, + "TESTOUT31": { + "direction": "OUT" + }, "TESTOUT14": { "direction": "OUT" }, "TESTOUT62": { "direction": "OUT" }, - "TESTOUT11": { - "direction": "OUT" - }, - "DI4": { + "TESTIN17": { "direction": "IN" }, - "TESTOUT56": { - "direction": "OUT" - }, "TESTIN20": { "direction": "IN" }, - "DI14": { - "direction": "IN" - }, - "TESTOUT16": { + "DO14": { "direction": "OUT" }, - "TESTOUT2": { + "TESTIN27": { + "direction": "IN" + }, + "CLKOUT5": { + "direction": "OUT" + }, + "TESTOUT7": { + "direction": "OUT" + }, + "TESTOUT43": { + "direction": "OUT" + }, + "TESTIN14": { + "direction": "IN" + }, + "DRDY": { + "direction": "OUT" + }, + "TESTOUT36": { + "direction": "OUT" + }, + "DO5": { + "direction": "OUT" + }, + "TESTIN25": { + "direction": "IN" + }, + "TESTOUT27": { + "direction": "OUT" + }, + "TESTOUT8": { + "direction": "OUT" + }, + "DADDR6": { + "direction": "IN" + }, + "TESTIN7": { + "direction": "IN" + }, + "TESTIN3": { + "direction": "IN" + }, + "TESTOUT26": { + "direction": "OUT" + }, + "TESTOUT40": { + "direction": "OUT" + }, + "TESTOUT1": { + "direction": "OUT" + }, + "DI3": { + "direction": "IN" + }, + "TESTOUT11": { + "direction": "OUT" + }, + "TESTOUT51": { + "direction": "OUT" + }, + "TESTIN16": { + "direction": "IN" + }, + "TESTOUT45": { + "direction": "OUT" + }, + "TESTIN8": { + "direction": "IN" + }, + "DEN": { + "direction": "IN" + }, + "TESTIN22": { + "direction": "IN" + }, + "TESTOUT23": { + "direction": "OUT" + }, + "TESTOUT48": { + "direction": "OUT" + }, + "DADDR1": { + "direction": "IN" + }, + "DO3": { + "direction": "OUT" + }, + "TESTOUT50": { + "direction": "OUT" + }, + "TESTOUT32": { + "direction": "OUT" + }, + "CLKFBIN": { + "direction": "IN" + }, + "DO8": { + "direction": "OUT" + }, + "TESTIN2": { + "direction": "IN" + }, + "DO1": { + "direction": "OUT" + }, + "TESTIN21": { + "direction": "IN" + }, + "DI13": { + "direction": "IN" + }, + "DO12": { + "direction": "OUT" + }, + "TESTOUT33": { + "direction": "OUT" + }, + "DI6": { + "direction": "IN" + }, + "TESTIN26": { + "direction": "IN" + }, + "CLKINSEL": { + "direction": "IN" + }, + "DI8": { + "direction": "IN" + }, + "TESTOUT55": { + "direction": "OUT" + }, + "TESTOUT60": { + "direction": "OUT" + }, + "DADDR4": { + "direction": "IN" + }, + "DADDR2": { + "direction": "IN" + }, + "TESTOUT4": { + "direction": "OUT" + }, + "TESTOUT38": { + "direction": "OUT" + }, + "DO10": { + "direction": "OUT" + }, + "CLKOUT0": { + "direction": "OUT" + }, + "TESTIN30": { + "direction": "IN" + }, + "TESTIN18": { + "direction": "IN" + }, + "TESTOUT6": { + "direction": "OUT" + }, + "TESTOUT58": { + "direction": "OUT" + }, + "TESTOUT53": { "direction": "OUT" }, "CLKFBOUT": { "direction": "OUT" }, + "TESTIN28": { + "direction": "IN" + }, + "TESTIN9": { + "direction": "IN" + }, + "TESTOUT20": { + "direction": "OUT" + }, + "TESTIN12": { + "direction": "IN" + }, "DO13": { "direction": "OUT" }, - "TESTOUT41": { - "direction": "OUT" - }, - "DADDR3": { - "direction": "IN" - }, - "DWE": { - "direction": "IN" - }, "DI2": { "direction": "IN" }, - "DADDR5": { - "direction": "IN" - }, - "TESTOUT48": { + "DO0": { "direction": "OUT" }, - "DO1": { + "DO11": { + "direction": "OUT" + }, + "TESTIN19": { + "direction": "IN" + }, + "DI12": { + "direction": "IN" + }, + "LOCKED": { + "direction": "OUT" + }, + "TESTIN4": { + "direction": "IN" + }, + "TESTOUT15": { + "direction": "OUT" + }, + "DO6": { + "direction": "OUT" + }, + "TESTOUT19": { + "direction": "OUT" + }, + "TESTOUT24": { + "direction": "OUT" + }, + "TESTOUT61": { + "direction": "OUT" + }, + "TESTOUT59": { + "direction": "OUT" + }, + "DI1": { + "direction": "IN" + }, + "DI14": { + "direction": "IN" + }, + "TESTOUT37": { + "direction": "OUT" + }, + "TESTOUT46": { + "direction": "OUT" + }, + "CLKOUT1": { + "direction": "OUT" + }, + "TESTOUT54": { + "direction": "OUT" + }, + "TESTOUT44": { + "direction": "OUT" + }, + "TESTOUT29": { + "direction": "OUT" + }, + "TESTOUT9": { + "direction": "OUT" + }, + "TESTOUT3": { + "direction": "OUT" + }, + "TESTIN23": { + "direction": "IN" + }, + "DO15": { + "direction": "OUT" + }, + "CLKIN2": { + "direction": "IN" + }, + "DI10": { + "direction": "IN" + }, + "TESTOUT13": { + "direction": "OUT" + }, + "DO7": { + "direction": "OUT" + }, + "TESTIN6": { + "direction": "IN" + }, + "TESTOUT49": { + "direction": "OUT" + }, + "TESTOUT5": { + "direction": "OUT" + }, + "DI4": { + "direction": "IN" + }, + "TESTIN13": { + "direction": "IN" + }, + "TESTOUT28": { + "direction": "OUT" + }, + "TESTIN1": { + "direction": "IN" + }, + "DI5": { + "direction": "IN" + }, + "CLKOUT3": { + "direction": "OUT" + }, + "TESTOUT34": { + "direction": "OUT" + }, + "TESTOUT56": { "direction": "OUT" }, "DI11": { "direction": "IN" }, - "TESTIN6": { + "TESTOUT10": { + "direction": "OUT" + }, + "TESTOUT47": { + "direction": "OUT" + }, + "TESTIN29": { "direction": "IN" }, - "TESTIN8": { + "DWE": { + "direction": "IN" + }, + "TESTOUT16": { + "direction": "OUT" + }, + "TESTOUT35": { + "direction": "OUT" + }, + "TESTIN10": { "direction": "IN" }, "TESTIN11": { "direction": "IN" - } - }, - "type": "PLLE2_ADV", - "site_pips": { - "CLKINSELINV:CLKINSEL_B": { - "from_pin": "CLKINSEL_B", - "to_pin": "OUT" }, - "PWRDWNINV:PWRDWN": { - "from_pin": "PWRDWN", - "to_pin": "OUT" + "TESTOUT63": { + "direction": "OUT" }, - "PWRDWNINV:PWRDWN_B": { - "from_pin": "PWRDWN_B", - "to_pin": "OUT" + "CLKOUT2": { + "direction": "OUT" }, - "RSTINV:RST": { - "from_pin": "RST", - "to_pin": "OUT" + "DI7": { + "direction": "IN" }, - "RSTINV:RST_B": { - "from_pin": "RST_B", - "to_pin": "OUT" + "DO4": { + "direction": "OUT" }, - "CLKINSELINV:CLKINSEL": { - "from_pin": "CLKINSEL", - "to_pin": "OUT" + "DCLK": { + "direction": "IN" + }, + "TESTOUT25": { + "direction": "OUT" + }, + "DADDR3": { + "direction": "IN" + }, + "TESTOUT41": { + "direction": "OUT" + }, + "RST": { + "direction": "IN" + }, + "TESTOUT42": { + "direction": "OUT" + }, + "TESTOUT52": { + "direction": "OUT" + }, + "TESTOUT39": { + "direction": "OUT" + }, + "DADDR5": { + "direction": "IN" + }, + "TESTOUT17": { + "direction": "OUT" + }, + "DO2": { + "direction": "OUT" + }, + "TESTIN0": { + "direction": "IN" + }, + "TESTOUT12": { + "direction": "OUT" + }, + "TESTOUT30": { + "direction": "OUT" + }, + "TESTIN24": { + "direction": "IN" + }, + "PWRDWN": { + "direction": "IN" + }, + "TESTIN31": { + "direction": "IN" + }, + "TESTOUT2": { + "direction": "OUT" + }, + "DI9": { + "direction": "IN" + }, + "TESTOUT18": { + "direction": "OUT" + }, + "CLKOUT4": { + "direction": "OUT" } } } \ No newline at end of file diff --git a/artix7/site_type_PMV2.json b/artix7/site_type_PMV2.json index 3273616..632c056 100644 --- a/artix7/site_type_PMV2.json +++ b/artix7/site_type_PMV2.json @@ -1,27 +1,27 @@ { + "type": "PMV2", + "site_pips": {}, "site_pins": { - "A0": { - "direction": "IN" - }, - "EN": { - "direction": "IN" - }, "O": { "direction": "OUT" }, - "ODIV4": { - "direction": "OUT" + "A1": { + "direction": "IN" }, "A2": { "direction": "IN" }, - "A1": { + "A0": { + "direction": "IN" + }, + "ODIV4": { + "direction": "OUT" + }, + "EN": { "direction": "IN" }, "ODIV2": { "direction": "OUT" } - }, - "type": "PMV2", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_RAMB18E1.json b/artix7/site_type_RAMB18E1.json index 000e56a..52112f4 100644 --- a/artix7/site_type_RAMB18E1.json +++ b/artix7/site_type_RAMB18E1.json @@ -1,561 +1,561 @@ { + "type": "RAMB18E1", + "site_pips": { + "RSTREGARSTREGINV:RSTREGARSTREG": { + "to_pin": "OUT", + "from_pin": "RSTREGARSTREG" + }, + "RSTREGBINV:RSTREGB_B": { + "to_pin": "OUT", + "from_pin": "RSTREGB_B" + }, + "CLKBWRCLKINV:CLKBWRCLK": { + "to_pin": "OUT", + "from_pin": "CLKBWRCLK" + }, + "RSTRAMARSTRAMINV:RSTRAMARSTRAM_B": { + "to_pin": "OUT", + "from_pin": "RSTRAMARSTRAM_B" + }, + "CLKBWRCLKINV:CLKBWRCLK_B": { + "to_pin": "OUT", + "from_pin": "CLKBWRCLK_B" + }, + "CLKARDCLKINV:CLKARDCLK": { + "to_pin": "OUT", + "from_pin": "CLKARDCLK" + }, + "RSTRAMARSTRAMINV:RSTRAMARSTRAM": { + "to_pin": "OUT", + "from_pin": "RSTRAMARSTRAM" + }, + "RSTREGBINV:RSTREGB": { + "to_pin": "OUT", + "from_pin": "RSTREGB" + }, + "REGCLKBINV:REGCLKB_B": { + "to_pin": "OUT", + "from_pin": "REGCLKB_B" + }, + "RSTREGARSTREGINV:RSTREGARSTREG_B": { + "to_pin": "OUT", + "from_pin": "RSTREGARSTREG_B" + }, + "RSTRAMBINV:RSTRAMB_B": { + "to_pin": "OUT", + "from_pin": "RSTRAMB_B" + }, + "ENARDENINV:ENARDEN": { + "to_pin": "OUT", + "from_pin": "ENARDEN" + }, + "RSTRAMBINV:RSTRAMB": { + "to_pin": "OUT", + "from_pin": "RSTRAMB" + }, + "ENBWRENINV:ENBWREN_B": { + "to_pin": "OUT", + "from_pin": "ENBWREN_B" + }, + "CLKARDCLKINV:CLKARDCLK_B": { + "to_pin": "OUT", + "from_pin": "CLKARDCLK_B" + }, + "ENARDENINV:ENARDEN_B": { + "to_pin": "OUT", + "from_pin": "ENARDEN_B" + }, + "ENBWRENINV:ENBWREN": { + "to_pin": "OUT", + "from_pin": "ENBWREN" + }, + "REGCLKARDRCLKINV:REGCLKARDRCLK": { + "to_pin": "OUT", + "from_pin": "REGCLKARDRCLK" + }, + "REGCLKBINV:REGCLKB": { + "to_pin": "OUT", + "from_pin": "REGCLKB" + }, + "REGCLKARDRCLKINV:REGCLKARDRCLK_B": { + "to_pin": "OUT", + "from_pin": "REGCLKARDRCLK_B" + } + }, "site_pins": { - "RDCOUNT4": { - "direction": "OUT" - }, - "WEA0": { - "direction": "IN" - }, - "DIADI0": { - "direction": "IN" - }, - "DIADI1": { - "direction": "IN" - }, - "RDCOUNT3": { - "direction": "OUT" - }, - "ADDRARDADDR4": { - "direction": "IN" - }, - "ADDRARDADDR11": { - "direction": "IN" - }, - "WEBWE7": { - "direction": "IN" - }, - "ADDRBWRADDR1": { - "direction": "IN" - }, - "ADDRBWRADDR3": { - "direction": "IN" - }, - "DOADO2": { - "direction": "OUT" - }, - "DOADO13": { - "direction": "OUT" - }, - "RDCOUNT9": { - "direction": "OUT" - }, - "DOBDO11": { - "direction": "OUT" - }, - "CLKARDCLK": { - "direction": "IN" - }, - "DIADI10": { - "direction": "IN" - }, - "WRCOUNT11": { - "direction": "OUT" - }, - "DOBDO12": { - "direction": "OUT" - }, - "REGCEAREGCE": { - "direction": "IN" - }, - "ADDRARDADDR8": { - "direction": "IN" - }, - "RDERR": { - "direction": "OUT" - }, - "ADDRBTIEHIGH1": { - "direction": "IN" - }, - "ADDRARDADDR7": { - "direction": "IN" - }, - "DIPADIP0": { - "direction": "IN" - }, - "WRCOUNT0": { - "direction": "OUT" - }, - "DIADI6": { - "direction": "IN" - }, - "DIADI7": { - "direction": "IN" - }, - "DOBDO7": { - "direction": "OUT" - }, - "DIADI12": { - "direction": "IN" - }, - "WRCOUNT5": { - "direction": "OUT" - }, - "ADDRBWRADDR4": { - "direction": "IN" - }, - "REGCLKB": { - "direction": "IN" - }, - "ADDRATIEHIGH1": { - "direction": "IN" - }, - "DOADO1": { - "direction": "OUT" - }, - "ADDRBWRADDR5": { - "direction": "IN" - }, - "DIBDI1": { + "DIBDI10": { "direction": "IN" }, "DOBDO15": { "direction": "OUT" }, - "DOBDO10": { - "direction": "OUT" - }, - "RSTRAMB": { - "direction": "IN" - }, - "DOPBDOP0": { - "direction": "OUT" - }, - "ADDRBWRADDR7": { - "direction": "IN" - }, - "DOBDO5": { - "direction": "OUT" - }, - "DOBDO14": { - "direction": "OUT" - }, - "CLKBWRCLK": { - "direction": "IN" - }, - "DOBDO9": { - "direction": "OUT" - }, - "FULL": { - "direction": "OUT" - }, - "ADDRBWRADDR6": { - "direction": "IN" - }, - "WEBWE0": { - "direction": "IN" - }, - "DOADO14": { - "direction": "OUT" - }, - "DIBDI14": { - "direction": "IN" - }, - "DIBDI6": { - "direction": "IN" - }, - "DOPADOP1": { - "direction": "OUT" - }, - "DIPBDIP0": { - "direction": "IN" - }, - "WEBWE2": { - "direction": "IN" - }, - "DOBDO1": { - "direction": "OUT" - }, - "ADDRBWRADDR0": { - "direction": "IN" - }, - "ADDRARDADDR1": { - "direction": "IN" - }, - "DOBDO6": { - "direction": "OUT" - }, - "DIBDI10": { - "direction": "IN" - }, - "DIADI11": { - "direction": "IN" - }, - "DIPBDIP1": { - "direction": "IN" - }, - "ADDRBWRADDR2": { - "direction": "IN" - }, - "ADDRARDADDR13": { - "direction": "IN" - }, - "DOADO3": { - "direction": "OUT" - }, - "WRCOUNT3": { - "direction": "OUT" - }, - "DOBDO3": { - "direction": "OUT" - }, - "ADDRBWRADDR11": { - "direction": "IN" - }, - "WEBWE3": { - "direction": "IN" - }, - "DIBDI5": { - "direction": "IN" - }, - "ADDRBWRADDR8": { - "direction": "IN" - }, - "DOADO7": { - "direction": "OUT" - }, - "WRCOUNT1": { - "direction": "OUT" - }, - "WRERR": { - "direction": "OUT" - }, - "RDCOUNT6": { - "direction": "OUT" - }, - "ADDRARDADDR0": { - "direction": "IN" - }, - "ADDRARDADDR5": { - "direction": "IN" - }, - "DOBDO2": { - "direction": "OUT" - }, - "DIBDI11": { - "direction": "IN" - }, - "RSTREGB": { + "REGCLKARDRCLK": { "direction": "IN" }, "RDCOUNT0": { "direction": "OUT" }, - "DIADI8": { - "direction": "IN" - }, - "ALMOSTFULL": { - "direction": "OUT" - }, - "WEA3": { - "direction": "IN" - }, - "WEBWE5": { - "direction": "IN" - }, - "DOPBDOP1": { - "direction": "OUT" - }, - "RDCOUNT2": { - "direction": "OUT" - }, - "ADDRBWRADDR9": { - "direction": "IN" - }, - "RDCOUNT1": { - "direction": "OUT" - }, - "RSTRAMARSTRAM": { - "direction": "IN" - }, - "WEBWE6": { - "direction": "IN" - }, - "WRCOUNT6": { - "direction": "OUT" - }, - "DIBDI2": { - "direction": "IN" - }, - "RDCOUNT11": { - "direction": "OUT" - }, - "DOADO0": { - "direction": "OUT" - }, - "DIBDI0": { - "direction": "IN" - }, - "ADDRARDADDR9": { - "direction": "IN" - }, - "REGCLKARDRCLK": { - "direction": "IN" - }, - "DIADI2": { - "direction": "IN" - }, - "RDCOUNT8": { - "direction": "OUT" - }, - "ADDRARDADDR3": { - "direction": "IN" - }, - "ADDRBWRADDR12": { - "direction": "IN" - }, - "EMPTY": { - "direction": "OUT" - }, - "RDCOUNT10": { - "direction": "OUT" - }, - "DIPADIP1": { - "direction": "IN" - }, - "WRCOUNT10": { - "direction": "OUT" - }, - "ALMOSTEMPTY": { - "direction": "OUT" - }, - "DIADI13": { - "direction": "IN" - }, - "DOADO6": { - "direction": "OUT" - }, - "DIADI14": { - "direction": "IN" - }, - "ADDRBTIEHIGH0": { - "direction": "IN" - }, - "DOPADOP0": { - "direction": "OUT" - }, - "DOADO11": { - "direction": "OUT" - }, - "ADDRARDADDR2": { + "ADDRBWRADDR1": { "direction": "IN" }, "WRCOUNT2": { "direction": "OUT" }, - "DIADI15": { - "direction": "IN" - }, - "ADDRATIEHIGH0": { - "direction": "IN" - }, - "REGCEB": { - "direction": "IN" - }, - "DOADO5": { - "direction": "OUT" - }, - "DOBDO8": { - "direction": "OUT" - }, - "DOADO4": { - "direction": "OUT" - }, - "DIADI5": { - "direction": "IN" - }, - "DIADI3": { + "WEBWE6": { "direction": "IN" }, "DOBDO0": { "direction": "OUT" }, - "DOADO8": { - "direction": "OUT" - }, - "DIBDI12": { - "direction": "IN" - }, - "ENARDEN": { - "direction": "IN" - }, - "DIBDI4": { - "direction": "IN" - }, - "WEBWE4": { - "direction": "IN" - }, - "WEBWE1": { - "direction": "IN" - }, - "WEA2": { - "direction": "IN" - }, - "RDCOUNT7": { - "direction": "OUT" - }, - "ADDRBWRADDR10": { - "direction": "IN" - }, - "WRCOUNT7": { - "direction": "OUT" - }, - "ADDRARDADDR6": { - "direction": "IN" - }, - "DOBDO4": { - "direction": "OUT" - }, - "WEA1": { - "direction": "IN" - }, - "WRCOUNT9": { - "direction": "OUT" - }, - "WRCOUNT4": { - "direction": "OUT" - }, - "DIBDI13": { - "direction": "IN" - }, - "ADDRBWRADDR13": { - "direction": "IN" - }, - "DIBDI7": { - "direction": "IN" - }, - "DOADO12": { - "direction": "OUT" - }, - "DIADI9": { - "direction": "IN" - }, - "DIBDI8": { - "direction": "IN" - }, - "DOADO10": { + "DOPADOP0": { "direction": "OUT" }, "DOADO15": { "direction": "OUT" }, - "ADDRARDADDR10": { + "DOBDO7": { + "direction": "OUT" + }, + "ADDRARDADDR5": { + "direction": "IN" + }, + "WRCOUNT10": { + "direction": "OUT" + }, + "ADDRARDADDR8": { + "direction": "IN" + }, + "DIADI10": { + "direction": "IN" + }, + "RDCOUNT4": { + "direction": "OUT" + }, + "ADDRARDADDR3": { "direction": "IN" }, "RDCOUNT5": { "direction": "OUT" }, - "RSTREGARSTREG": { + "DIADI14": { "direction": "IN" }, - "WRCOUNT8": { + "RSTRAMB": { + "direction": "IN" + }, + "RDCOUNT2": { "direction": "OUT" }, - "DIBDI9": { + "ADDRARDADDR13": { "direction": "IN" }, - "DIBDI3": { - "direction": "IN" + "DOBDO6": { + "direction": "OUT" }, - "DOADO9": { + "ALMOSTFULL": { "direction": "OUT" }, "ENBWREN": { "direction": "IN" }, + "DOADO8": { + "direction": "OUT" + }, + "ADDRBWRADDR0": { + "direction": "IN" + }, + "WEBWE7": { + "direction": "IN" + }, + "DIADI1": { + "direction": "IN" + }, + "DIADI13": { + "direction": "IN" + }, + "ADDRARDADDR7": { + "direction": "IN" + }, + "ADDRBWRADDR5": { + "direction": "IN" + }, + "DIPBDIP1": { + "direction": "IN" + }, + "DOADO12": { + "direction": "OUT" + }, + "DIADI6": { + "direction": "IN" + }, + "RDCOUNT10": { + "direction": "OUT" + }, + "DIADI5": { + "direction": "IN" + }, + "DIBDI7": { + "direction": "IN" + }, + "FULL": { + "direction": "OUT" + }, + "DIADI2": { + "direction": "IN" + }, + "ENARDEN": { + "direction": "IN" + }, "DIBDI15": { "direction": "IN" }, + "WEBWE4": { + "direction": "IN" + }, + "DOADO1": { + "direction": "OUT" + }, + "WEA3": { + "direction": "IN" + }, + "DOPBDOP0": { + "direction": "OUT" + }, + "DOADO0": { + "direction": "OUT" + }, + "RDCOUNT7": { + "direction": "OUT" + }, + "ADDRBWRADDR8": { + "direction": "IN" + }, + "ADDRARDADDR0": { + "direction": "IN" + }, + "DIADI3": { + "direction": "IN" + }, + "DOBDO11": { + "direction": "OUT" + }, + "DOPBDOP1": { + "direction": "OUT" + }, + "ADDRBWRADDR6": { + "direction": "IN" + }, + "DIBDI0": { + "direction": "IN" + }, + "ADDRBTIEHIGH0": { + "direction": "IN" + }, + "WRCOUNT5": { + "direction": "OUT" + }, + "DIADI12": { + "direction": "IN" + }, + "RSTREGB": { + "direction": "IN" + }, + "DOBDO3": { + "direction": "OUT" + }, + "WRCOUNT1": { + "direction": "OUT" + }, + "DOADO11": { + "direction": "OUT" + }, + "RDCOUNT6": { + "direction": "OUT" + }, + "DIBDI3": { + "direction": "IN" + }, + "DOBDO4": { + "direction": "OUT" + }, + "ADDRBWRADDR12": { + "direction": "IN" + }, + "DIADI15": { + "direction": "IN" + }, + "EMPTY": { + "direction": "OUT" + }, + "DOPADOP1": { + "direction": "OUT" + }, + "DOBDO5": { + "direction": "OUT" + }, + "CLKBWRCLK": { + "direction": "IN" + }, + "DOADO14": { + "direction": "OUT" + }, + "RDCOUNT9": { + "direction": "OUT" + }, + "ADDRBWRADDR9": { + "direction": "IN" + }, + "WEBWE3": { + "direction": "IN" + }, + "WEBWE2": { + "direction": "IN" + }, + "ADDRBWRADDR2": { + "direction": "IN" + }, + "WEBWE1": { + "direction": "IN" + }, + "WEBWE5": { + "direction": "IN" + }, + "DOADO2": { + "direction": "OUT" + }, + "REGCEB": { + "direction": "IN" + }, + "DIPBDIP0": { + "direction": "IN" + }, + "DIADI9": { + "direction": "IN" + }, + "ADDRARDADDR11": { + "direction": "IN" + }, + "RDCOUNT8": { + "direction": "OUT" + }, + "RDCOUNT1": { + "direction": "OUT" + }, + "ADDRBWRADDR3": { + "direction": "IN" + }, + "RSTREGARSTREG": { + "direction": "IN" + }, + "WEA1": { + "direction": "IN" + }, + "ADDRBWRADDR13": { + "direction": "IN" + }, + "DOBDO8": { + "direction": "OUT" + }, + "DIBDI1": { + "direction": "IN" + }, + "DOBDO1": { + "direction": "OUT" + }, + "DIBDI14": { + "direction": "IN" + }, + "ADDRARDADDR10": { + "direction": "IN" + }, + "DIBDI9": { + "direction": "IN" + }, + "REGCLKB": { + "direction": "IN" + }, + "DIBDI12": { + "direction": "IN" + }, + "DOADO9": { + "direction": "OUT" + }, + "WRCOUNT0": { + "direction": "OUT" + }, + "DOADO10": { + "direction": "OUT" + }, + "DOBDO10": { + "direction": "OUT" + }, + "ADDRBWRADDR4": { + "direction": "IN" + }, + "REGCEAREGCE": { + "direction": "IN" + }, + "WRCOUNT4": { + "direction": "OUT" + }, + "DIADI0": { + "direction": "IN" + }, + "WRCOUNT9": { + "direction": "OUT" + }, + "DIADI8": { + "direction": "IN" + }, + "DOBDO9": { + "direction": "OUT" + }, + "RSTRAMARSTRAM": { + "direction": "IN" + }, + "DIADI11": { + "direction": "IN" + }, + "DOADO3": { + "direction": "OUT" + }, + "ADDRARDADDR1": { + "direction": "IN" + }, + "DIBDI4": { + "direction": "IN" + }, + "ADDRATIEHIGH0": { + "direction": "IN" + }, + "WEBWE0": { + "direction": "IN" + }, + "ADDRBWRADDR11": { + "direction": "IN" + }, "ADDRARDADDR12": { "direction": "IN" }, + "DOBDO12": { + "direction": "OUT" + }, + "ADDRARDADDR6": { + "direction": "IN" + }, + "ADDRATIEHIGH1": { + "direction": "IN" + }, "DOBDO13": { "direction": "OUT" }, + "WRCOUNT8": { + "direction": "OUT" + }, + "DOADO13": { + "direction": "OUT" + }, + "DOADO5": { + "direction": "OUT" + }, + "DIPADIP0": { + "direction": "IN" + }, + "WRCOUNT3": { + "direction": "OUT" + }, + "ALMOSTEMPTY": { + "direction": "OUT" + }, + "DIADI7": { + "direction": "IN" + }, + "ADDRBWRADDR7": { + "direction": "IN" + }, + "DIBDI5": { + "direction": "IN" + }, + "WRERR": { + "direction": "OUT" + }, + "WEA0": { + "direction": "IN" + }, + "DIBDI8": { + "direction": "IN" + }, + "WRCOUNT6": { + "direction": "OUT" + }, + "RDCOUNT11": { + "direction": "OUT" + }, + "CLKARDCLK": { + "direction": "IN" + }, + "DIPADIP1": { + "direction": "IN" + }, + "WRCOUNT11": { + "direction": "OUT" + }, + "DOBDO2": { + "direction": "OUT" + }, + "WRCOUNT7": { + "direction": "OUT" + }, + "DIBDI13": { + "direction": "IN" + }, + "WEA2": { + "direction": "IN" + }, "DIADI4": { "direction": "IN" - } - }, - "type": "RAMB18E1", - "site_pips": { - "RSTREGBINV:RSTREGB_B": { - "from_pin": "RSTREGB_B", - "to_pin": "OUT" }, - "CLKBWRCLKINV:CLKBWRCLK": { - "from_pin": "CLKBWRCLK", - "to_pin": "OUT" + "ADDRARDADDR9": { + "direction": "IN" }, - "RSTRAMARSTRAMINV:RSTRAMARSTRAM_B": { - "from_pin": "RSTRAMARSTRAM_B", - "to_pin": "OUT" + "DIBDI2": { + "direction": "IN" }, - "ENARDENINV:ENARDEN": { - "from_pin": "ENARDEN", - "to_pin": "OUT" + "DOBDO14": { + "direction": "OUT" }, - "RSTREGARSTREGINV:RSTREGARSTREG": { - "from_pin": "RSTREGARSTREG", - "to_pin": "OUT" + "RDERR": { + "direction": "OUT" }, - "CLKARDCLKINV:CLKARDCLK_B": { - "from_pin": "CLKARDCLK_B", - "to_pin": "OUT" + "DOADO7": { + "direction": "OUT" }, - "CLKARDCLKINV:CLKARDCLK": { - "from_pin": "CLKARDCLK", - "to_pin": "OUT" + "ADDRARDADDR4": { + "direction": "IN" }, - "ENBWRENINV:ENBWREN_B": { - "from_pin": "ENBWREN_B", - "to_pin": "OUT" + "DIBDI11": { + "direction": "IN" }, - "RSTRAMARSTRAMINV:RSTRAMARSTRAM": { - "from_pin": "RSTRAMARSTRAM", - "to_pin": "OUT" + "RDCOUNT3": { + "direction": "OUT" }, - "CLKBWRCLKINV:CLKBWRCLK_B": { - "from_pin": "CLKBWRCLK_B", - "to_pin": "OUT" + "ADDRBTIEHIGH1": { + "direction": "IN" }, - "REGCLKARDRCLKINV:REGCLKARDRCLK": { - "from_pin": "REGCLKARDRCLK", - "to_pin": "OUT" + "ADDRBWRADDR10": { + "direction": "IN" }, - "RSTREGBINV:RSTREGB": { - "from_pin": "RSTREGB", - "to_pin": "OUT" + "DIBDI6": { + "direction": "IN" }, - "REGCLKBINV:REGCLKB": { - "from_pin": "REGCLKB", - "to_pin": "OUT" + "DOADO6": { + "direction": "OUT" }, - "ENBWRENINV:ENBWREN": { - "from_pin": "ENBWREN", - "to_pin": "OUT" + "DOADO4": { + "direction": "OUT" }, - "RSTRAMBINV:RSTRAMB_B": { - "from_pin": "RSTRAMB_B", - "to_pin": "OUT" - }, - "ENARDENINV:ENARDEN_B": { - "from_pin": "ENARDEN_B", - "to_pin": "OUT" - }, - "REGCLKBINV:REGCLKB_B": { - "from_pin": "REGCLKB_B", - "to_pin": "OUT" - }, - "REGCLKARDRCLKINV:REGCLKARDRCLK_B": { - "from_pin": "REGCLKARDRCLK_B", - "to_pin": "OUT" - }, - "RSTRAMBINV:RSTRAMB": { - "from_pin": "RSTRAMB", - "to_pin": "OUT" - }, - "RSTREGARSTREGINV:RSTREGARSTREG_B": { - "from_pin": "RSTREGARSTREG_B", - "to_pin": "OUT" + "ADDRARDADDR2": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_RAMBFIFO36E1.json b/artix7/site_type_RAMBFIFO36E1.json index 626e08a..7d40be6 100644 --- a/artix7/site_type_RAMBFIFO36E1.json +++ b/artix7/site_type_RAMBFIFO36E1.json @@ -1,528 +1,1003 @@ { + "type": "RAMBFIFO36E1", + "site_pips": { + "RSTREGBUINV:RSTREGBU_B": { + "to_pin": "OUT", + "from_pin": "RSTREGBU_B" + }, + "RSTREGBLINV:RSTREGBL_B": { + "to_pin": "OUT", + "from_pin": "RSTREGBL_B" + }, + "ENBWRENUINV:ENBWRENU_B": { + "to_pin": "OUT", + "from_pin": "ENBWRENU_B" + }, + "ENARDENUINV:ENARDENU": { + "to_pin": "OUT", + "from_pin": "ENARDENU" + }, + "CLKBWRCLKLINV:CLKBWRCLKL": { + "to_pin": "OUT", + "from_pin": "CLKBWRCLKL" + }, + "RSTRAMARSTRAMLRSTINV:RSTRAMARSTRAMLRST_B": { + "to_pin": "OUT", + "from_pin": "RSTRAMARSTRAMLRST_B" + }, + "CLKARDCLKUINV:CLKARDCLKU_B": { + "to_pin": "OUT", + "from_pin": "CLKARDCLKU_B" + }, + "CLKARDCLKLINV:CLKARDCLKL_B": { + "to_pin": "OUT", + "from_pin": "CLKARDCLKL_B" + }, + "RSTREGBLINV:RSTREGBL": { + "to_pin": "OUT", + "from_pin": "RSTREGBL" + }, + "RSTREGARSTREGUINV:RSTREGARSTREGU_B": { + "to_pin": "OUT", + "from_pin": "RSTREGARSTREGU_B" + }, + "RSTRAMBUINV:RSTRAMBU": { + "to_pin": "OUT", + "from_pin": "RSTRAMBU" + }, + "RSTREGBUINV:RSTREGBU": { + "to_pin": "OUT", + "from_pin": "RSTREGBU" + }, + "ENBWRENLINV:ENBWRENL_B": { + "to_pin": "OUT", + "from_pin": "ENBWRENL_B" + }, + "RSTRAMARSTRAMUINV:RSTRAMARSTRAMU": { + "to_pin": "OUT", + "from_pin": "RSTRAMARSTRAMU" + }, + "ENBWRENUINV:ENBWRENU": { + "to_pin": "OUT", + "from_pin": "ENBWRENU" + }, + "ENBWRENLINV:ENBWRENL": { + "to_pin": "OUT", + "from_pin": "ENBWRENL" + }, + "CLKBWRCLKUINV:CLKBWRCLKU": { + "to_pin": "OUT", + "from_pin": "CLKBWRCLKU" + }, + "RSTREGARSTREGUINV:RSTREGARSTREGU": { + "to_pin": "OUT", + "from_pin": "RSTREGARSTREGU" + }, + "REGCLKARDRCLKLINV:REGCLKARDRCLKL_B": { + "to_pin": "OUT", + "from_pin": "REGCLKARDRCLKL_B" + }, + "REGCLKARDRCLKLINV:REGCLKARDRCLKL": { + "to_pin": "OUT", + "from_pin": "REGCLKARDRCLKL" + }, + "CLKBWRCLKLINV:CLKBWRCLKL_B": { + "to_pin": "OUT", + "from_pin": "CLKBWRCLKL_B" + }, + "CLKARDCLKLINV:CLKARDCLKL": { + "to_pin": "OUT", + "from_pin": "CLKARDCLKL" + }, + "ENARDENLINV:ENARDENL_B": { + "to_pin": "OUT", + "from_pin": "ENARDENL_B" + }, + "RSTREGARSTREGLINV:RSTREGARSTREGL": { + "to_pin": "OUT", + "from_pin": "RSTREGARSTREGL" + }, + "RSTREGARSTREGLINV:RSTREGARSTREGL_B": { + "to_pin": "OUT", + "from_pin": "RSTREGARSTREGL_B" + }, + "RSTRAMARSTRAMUINV:RSTRAMARSTRAMU_B": { + "to_pin": "OUT", + "from_pin": "RSTRAMARSTRAMU_B" + }, + "REGCLKBUINV:REGCLKBU": { + "to_pin": "OUT", + "from_pin": "REGCLKBU" + }, + "REGCLKBLINV:REGCLKBL": { + "to_pin": "OUT", + "from_pin": "REGCLKBL" + }, + "CLKARDCLKUINV:CLKARDCLKU": { + "to_pin": "OUT", + "from_pin": "CLKARDCLKU" + }, + "REGCLKBLINV:REGCLKBL_B": { + "to_pin": "OUT", + "from_pin": "REGCLKBL_B" + }, + "REGCLKBUINV:REGCLKBU_B": { + "to_pin": "OUT", + "from_pin": "REGCLKBU_B" + }, + "RSTRAMARSTRAMLRSTINV:RSTRAMARSTRAMLRST": { + "to_pin": "OUT", + "from_pin": "RSTRAMARSTRAMLRST" + }, + "REGCLKARDRCLKUINV:REGCLKARDRCLKU": { + "to_pin": "OUT", + "from_pin": "REGCLKARDRCLKU" + }, + "ENARDENUINV:ENARDENU_B": { + "to_pin": "OUT", + "from_pin": "ENARDENU_B" + }, + "RSTRAMBUINV:RSTRAMBU_B": { + "to_pin": "OUT", + "from_pin": "RSTRAMBU_B" + }, + "RSTRAMBLINV:RSTRAMBL": { + "to_pin": "OUT", + "from_pin": "RSTRAMBL" + }, + "ENARDENLINV:ENARDENL": { + "to_pin": "OUT", + "from_pin": "ENARDENL" + }, + "CLKBWRCLKUINV:CLKBWRCLKU_B": { + "to_pin": "OUT", + "from_pin": "CLKBWRCLKU_B" + }, + "REGCLKARDRCLKUINV:REGCLKARDRCLKU_B": { + "to_pin": "OUT", + "from_pin": "REGCLKARDRCLKU_B" + }, + "RSTRAMBLINV:RSTRAMBL_B": { + "to_pin": "OUT", + "from_pin": "RSTRAMBL_B" + } + }, "site_pins": { - "DOBDO20": { + "DIADI28": { + "direction": "IN" + }, + "DOBDO15": { "direction": "OUT" }, - "DIADI0": { + "DIBDI10": { "direction": "IN" }, - "DIADI1": { - "direction": "IN" - }, - "RDCOUNT3": { + "DOBDO23": { "direction": "OUT" }, - "TSTOUT0": { - "direction": "OUT" - }, - "WRCOUNT10": { - "direction": "OUT" - }, - "TSTRDOS8": { - "direction": "IN" - }, - "TSTRDOS10": { - "direction": "IN" - }, - "ADDRBWRADDRL1": { - "direction": "IN" - }, - "TSTWROS5": { - "direction": "IN" - }, - "SBITERR": { - "direction": "OUT" - }, - "TSTCNT10": { - "direction": "IN" - }, - "DIADI10": { - "direction": "IN" - }, - "ADDRARDADDRL15": { - "direction": "IN" - }, - "ADDRARDADDRL10": { - "direction": "IN" - }, - "ADDRARDADDRL14": { - "direction": "IN" - }, - "DOBDO19": { - "direction": "OUT" - }, - "DOPBDOP2": { - "direction": "OUT" - }, - "RSTREGARSTREGU": { - "direction": "IN" - }, - "TSTCNT3": { - "direction": "IN" - }, - "ADDRARDADDRL4": { - "direction": "IN" - }, - "WEAU2": { - "direction": "IN" - }, - "DIBDI0": { - "direction": "IN" - }, - "TSTWROS3": { - "direction": "IN" - }, - "DOADO14": { - "direction": "OUT" - }, - "REGCLKBL": { - "direction": "IN" - }, - "RSTRAMBU": { - "direction": "IN" - }, - "DOBDO30": { - "direction": "OUT" - }, - "RDERR": { - "direction": "OUT" - }, - "DIBDI21": { - "direction": "IN" - }, "ADDRARDADDRL6": { "direction": "IN" }, - "CASCADEINA": { + "WEBWEU6": { "direction": "IN" }, - "DIADI23": { + "ADDRBWRADDRU10": { "direction": "IN" }, - "ADDRBWRADDRL9": { + "DIADI17": { "direction": "IN" }, - "DBITERR": { - "direction": "OUT" - }, - "DOADO3": { - "direction": "OUT" - }, - "DOBDO22": { - "direction": "OUT" - }, - "WRCOUNT3": { - "direction": "OUT" - }, - "ADDRBWRADDRL15": { + "REGCLKBL": { "direction": "IN" }, - "DOBDO18": { - "direction": "OUT" - }, - "WEBWEU7": { - "direction": "IN" - }, - "ADDRBWRADDRL12": { - "direction": "IN" - }, - "CASCADEOUTB": { - "direction": "OUT" - }, - "ADDRBWRADDRU2": { - "direction": "IN" - }, - "REGCEAREGCEU": { - "direction": "IN" - }, - "WEBWEL3": { - "direction": "IN" - }, - "DIBDI26": { - "direction": "IN" - }, - "ADDRARDADDRL0": { - "direction": "IN" - }, - "ADDRARDADDRL2": { - "direction": "IN" - }, - "WEAU3": { - "direction": "IN" - }, - "ADDRARDADDRU9": { - "direction": "IN" - }, - "ADDRARDADDRU5": { - "direction": "IN" - }, - "RDCOUNT8": { - "direction": "OUT" - }, - "REGCEBU": { - "direction": "IN" - }, - "TSTWROS11": { - "direction": "IN" - }, - "EMPTY": { - "direction": "OUT" - }, - "DOADO2": { - "direction": "OUT" - }, - "WEBWEU5": { - "direction": "IN" - }, - "DOPADOP0": { - "direction": "OUT" - }, - "DIADI20": { - "direction": "IN" - }, - "DIADI29": { - "direction": "IN" - }, - "DIADI28": { - "direction": "IN" - }, - "DIADI30": { - "direction": "IN" - }, - "DIADI5": { - "direction": "IN" - }, - "DOBDO0": { - "direction": "OUT" - }, - "ADDRARDADDRU2": { - "direction": "IN" - }, - "TSTRDOS2": { - "direction": "IN" - }, - "WEBWEU4": { + "DIADI14": { "direction": "IN" }, "DOADO25": { "direction": "OUT" }, - "ECCPARITY5": { - "direction": "OUT" - }, - "ADDRBWRADDRL5": { - "direction": "IN" - }, - "CASCADEINB": { - "direction": "IN" - }, - "ADDRARDADDRU1": { - "direction": "IN" - }, - "WEBWEL2": { - "direction": "IN" - }, - "ADDRBWRADDRU1": { + "TSTRDOS12": { "direction": "IN" }, "DIBDI18": { "direction": "IN" }, - "WRCOUNT4": { - "direction": "OUT" - }, - "DIBDI13": { + "DIADI5": { "direction": "IN" }, - "WEAL0": { + "REGCLKARDRCLKU": { "direction": "IN" }, - "DIBDI17": { - "direction": "IN" - }, - "TSTOUT2": { - "direction": "OUT" - }, - "DOADO10": { - "direction": "OUT" - }, - "TSTFLAGIN": { - "direction": "IN" - }, - "DIBDI15": { - "direction": "IN" - }, - "RSTREGBL": { - "direction": "IN" - }, - "WEBWEL5": { - "direction": "IN" - }, - "TSTRDOS6": { - "direction": "IN" - }, - "DOPADOP2": { - "direction": "OUT" - }, - "WEAL3": { - "direction": "IN" - }, - "DOADO13": { - "direction": "OUT" - }, - "DOBDO11": { - "direction": "OUT" - }, - "DIBDI27": { - "direction": "IN" - }, - "DOPBDOP3": { - "direction": "OUT" - }, - "DIBDI14": { - "direction": "IN" - }, - "DIBDI28": { - "direction": "IN" - }, - "RSTREGARSTREGL": { - "direction": "IN" - }, - "DOBDO4": { - "direction": "OUT" - }, - "ADDRBWRADDRU4": { - "direction": "IN" - }, - "DIPADIP0": { - "direction": "IN" - }, - "DIBDI30": { - "direction": "IN" - }, - "DIADI7": { - "direction": "IN" - }, - "DIADI12": { - "direction": "IN" - }, - "DOADO31": { - "direction": "OUT" - }, "DOADO29": { "direction": "OUT" }, - "DIBDI1": { + "TSTWROS0": { "direction": "IN" }, - "ADDRBWRADDRL0": { - "direction": "IN" - }, - "DOBDO10": { + "WRCOUNT6": { "direction": "OUT" }, - "DOPBDOP0": { + "DIADI2": { + "direction": "IN" + }, + "DOBDO19": { "direction": "OUT" }, - "ADDRBWRADDRL2": { + "WEAL0": { "direction": "IN" }, - "DOBDO14": { - "direction": "OUT" - }, - "FULL": { - "direction": "OUT" - }, - "DOBDO27": { - "direction": "OUT" - }, - "DOBDO1": { - "direction": "OUT" - }, - "ADDRBWRADDRU14": { - "direction": "IN" - }, - "DIPBDIP1": { - "direction": "IN" - }, - "DIADI27": { - "direction": "IN" - }, - "WEBWEL4": { - "direction": "IN" - }, - "TSTCNT11": { - "direction": "IN" - }, - "DOBDO3": { - "direction": "OUT" - }, - "ECCPARITY4": { - "direction": "OUT" - }, - "DOBDO15": { - "direction": "OUT" - }, - "ENARDENL": { - "direction": "IN" - }, - "ADDRBWRADDRU7": { - "direction": "IN" - }, - "WEBWEL6": { - "direction": "IN" - }, - "ADDRARDADDRL8": { - "direction": "IN" - }, - "TSTCNT4": { - "direction": "IN" - }, - "DOADO19": { - "direction": "OUT" - }, - "RSTRAMBL": { - "direction": "IN" - }, - "ADDRARDADDRU6": { - "direction": "IN" - }, - "DOBDO2": { - "direction": "OUT" - }, - "DIBDI11": { - "direction": "IN" - }, - "ADDRBWRADDRU6": { - "direction": "IN" - }, - "ALMOSTFULL": { - "direction": "OUT" - }, - "WEBWEL7": { - "direction": "IN" - }, - "TSTWROS1": { - "direction": "IN" - }, - "TSTBRAMRST": { - "direction": "IN" - }, - "RSTRAMARSTRAMU": { - "direction": "IN" - }, - "DOADO0": { - "direction": "OUT" - }, - "DIPADIP3": { - "direction": "IN" - }, - "ECCPARITY6": { - "direction": "OUT" - }, - "DOBDO21": { - "direction": "OUT" - }, - "TSTOFF": { - "direction": "IN" - }, - "DIADI15": { - "direction": "IN" - }, - "WEAU0": { - "direction": "IN" - }, - "TSTOUT4": { - "direction": "OUT" - }, - "RDCOUNT10": { - "direction": "OUT" - }, - "ADDRARDADDRL12": { - "direction": "IN" - }, - "DIBDI9": { - "direction": "IN" - }, - "DIADI13": { - "direction": "IN" - }, - "DIADI22": { - "direction": "IN" - }, - "ADDRBWRADDRU11": { - "direction": "IN" - }, - "DOADO11": { - "direction": "OUT" - }, - "ECCPARITY7": { - "direction": "OUT" - }, "DIADI26": { "direction": "IN" }, - "TSTRDOS12": { - "direction": "IN" - }, - "TSTWROS12": { - "direction": "IN" - }, "DOPADOP3": { "direction": "OUT" }, - "DOADO18": { - "direction": "OUT" - }, - "DIPADIP2": { + "ADDRBWRADDRL14": { "direction": "IN" }, - "CLKBWRCLKU": { + "DIADI3": { "direction": "IN" }, - "DOADO4": { + "ADDRBWRADDRL0": { + "direction": "IN" + }, + "INJECTSBITERR": { + "direction": "IN" + }, + "ADDRBWRADDRU9": { + "direction": "IN" + }, + "DIADI16": { + "direction": "IN" + }, + "WRCOUNT1": { "direction": "OUT" }, - "ADDRARDADDRL7": { + "DIBDI3": { + "direction": "IN" + }, + "DOBDO4": { + "direction": "OUT" + }, + "EMPTY": { + "direction": "OUT" + }, + "DOBDO14": { + "direction": "OUT" + }, + "DIBDI21": { + "direction": "IN" + }, + "ADDRBWRADDRL6": { + "direction": "IN" + }, + "RSTREGBU": { + "direction": "IN" + }, + "DOBDO25": { + "direction": "OUT" + }, + "DIADI25": { + "direction": "IN" + }, + "DOADO2": { + "direction": "OUT" + }, + "ADDRARDADDRL4": { + "direction": "IN" + }, + "DIADI9": { "direction": "IN" }, "RDCOUNT12": { "direction": "OUT" }, - "WEBWEU6": { + "TSTCNT0": { "direction": "IN" }, - "RDCOUNT7": { + "DIBDI1": { + "direction": "IN" + }, + "DIBDI14": { + "direction": "IN" + }, + "ADDRARDADDRU5": { + "direction": "IN" + }, + "DOPBDOP2": { "direction": "OUT" }, - "WRCOUNT11": { - "direction": "OUT" - }, - "ADDRBWRADDRL6": { + "WEAL2": { "direction": "IN" }, - "DIBDI6": { - "direction": "IN" - }, - "TSTOUT3": { - "direction": "OUT" - }, - "ADDRARDADDRL9": { - "direction": "IN" - }, - "DIBDI19": { + "TSTBRAMRST": { "direction": "IN" }, "ADDRARDADDRU12": { "direction": "IN" }, - "TSTCNT8": { + "REGCLKBU": { "direction": "IN" }, + "REGCLKARDRCLKL": { + "direction": "IN" + }, + "ADDRARDADDRL15": { + "direction": "IN" + }, + "DIADI11": { + "direction": "IN" + }, + "DIPADIP2": { + "direction": "IN" + }, + "DIADI21": { + "direction": "IN" + }, + "CASCADEOUTA": { + "direction": "OUT" + }, + "DIBDI17": { + "direction": "IN" + }, + "ADDRARDADDRL9": { + "direction": "IN" + }, + "TSTRDOS11": { + "direction": "IN" + }, + "DOBDO13": { + "direction": "OUT" + }, + "DOBDO28": { + "direction": "OUT" + }, + "DOADO5": { + "direction": "OUT" + }, + "DOBDO5": { + "direction": "OUT" + }, + "DOBDO29": { + "direction": "OUT" + }, + "DOPBDOP3": { + "direction": "OUT" + }, + "DIADI29": { + "direction": "IN" + }, + "DIADI31": { + "direction": "IN" + }, + "ADDRARDADDRL1": { + "direction": "IN" + }, + "WEBWEL1": { + "direction": "IN" + }, + "DIPBDIP0": { + "direction": "IN" + }, + "DIBDI13": { + "direction": "IN" + }, + "TSTCNT12": { + "direction": "IN" + }, + "DOPADOP2": { + "direction": "OUT" + }, "WRCOUNT12": { "direction": "OUT" }, - "TSTRDOS4": { + "TSTWROS4": { + "direction": "IN" + }, + "WRCOUNT4": { + "direction": "OUT" + }, + "TSTOUT2": { + "direction": "OUT" + }, + "DOADO6": { + "direction": "OUT" + }, + "TSTIN3": { + "direction": "IN" + }, + "RDERR": { + "direction": "OUT" + }, + "DIBDI9": { + "direction": "IN" + }, + "TSTWROS9": { + "direction": "IN" + }, + "INJECTDBITERR": { + "direction": "IN" + }, + "DIPADIP3": { + "direction": "IN" + }, + "DOBDO21": { + "direction": "OUT" + }, + "ADDRARDADDRL10": { + "direction": "IN" + }, + "ECCPARITY2": { + "direction": "OUT" + }, + "WRERR": { + "direction": "OUT" + }, + "TSTWROS3": { + "direction": "IN" + }, + "DIBDI26": { + "direction": "IN" + }, + "CASCADEOUTB": { + "direction": "OUT" + }, + "RDCOUNT2": { + "direction": "OUT" + }, + "WEBWEU7": { + "direction": "IN" + }, + "ENARDENL": { + "direction": "IN" + }, + "TSTCNT5": { + "direction": "IN" + }, + "DIBDI4": { + "direction": "IN" + }, + "DOADO8": { + "direction": "OUT" + }, + "ADDRARDADDRU2": { + "direction": "IN" + }, + "TSTOFF": { + "direction": "IN" + }, + "DIPBDIP1": { + "direction": "IN" + }, + "DOADO12": { + "direction": "OUT" + }, + "ADDRBWRADDRU14": { + "direction": "IN" + }, + "FULL": { + "direction": "OUT" + }, + "ADDRARDADDRU3": { + "direction": "IN" + }, + "ADDRBWRADDRU11": { + "direction": "IN" + }, + "WRCOUNT10": { + "direction": "OUT" + }, + "ADDRARDADDRU11": { + "direction": "IN" + }, + "DOADO19": { + "direction": "OUT" + }, + "DOADO15": { + "direction": "OUT" + }, + "ADDRARDADDRL13": { + "direction": "IN" + }, + "WEBWEL6": { + "direction": "IN" + }, + "ADDRBWRADDRL1": { + "direction": "IN" + }, + "DIBDI20": { + "direction": "IN" + }, + "TSTCNT3": { + "direction": "IN" + }, + "DIADI23": { + "direction": "IN" + }, + "TSTRDOS8": { + "direction": "IN" + }, + "WRCOUNT7": { + "direction": "OUT" + }, + "RDCOUNT1": { + "direction": "OUT" + }, + "RDCOUNT6": { + "direction": "OUT" + }, + "ADDRBWRADDRL12": { + "direction": "IN" + }, + "DIADI12": { + "direction": "IN" + }, + "DBITERR": { + "direction": "OUT" + }, + "DIBDI25": { + "direction": "IN" + }, + "TSTWROS2": { + "direction": "IN" + }, + "RDCOUNT10": { + "direction": "OUT" + }, + "DOBDO8": { + "direction": "OUT" + }, + "DOBDO30": { + "direction": "OUT" + }, + "RSTRAMBU": { + "direction": "IN" + }, + "CLKARDCLKL": { + "direction": "IN" + }, + "DOBDO1": { + "direction": "OUT" + }, + "ECCPARITY0": { + "direction": "OUT" + }, + "TSTCNT8": { + "direction": "IN" + }, + "DIBDI19": { + "direction": "IN" + }, + "ADDRBWRADDRU1": { + "direction": "IN" + }, + "DOADO18": { + "direction": "OUT" + }, + "DOADO10": { + "direction": "OUT" + }, + "ADDRBWRADDRL13": { + "direction": "IN" + }, + "DIADI24": { + "direction": "IN" + }, + "WRCOUNT9": { + "direction": "OUT" + }, + "DIADI30": { + "direction": "IN" + }, + "TSTRDOS1": { + "direction": "IN" + }, + "TSTRDOS3": { + "direction": "IN" + }, + "ADDRARDADDRU7": { + "direction": "IN" + }, + "WEBWEU0": { + "direction": "IN" + }, + "DOADO3": { + "direction": "OUT" + }, + "TSTRDOS5": { + "direction": "IN" + }, + "TSTRDOS0": { + "direction": "IN" + }, + "DIADI20": { + "direction": "IN" + }, + "DOBDO12": { + "direction": "OUT" + }, + "ADDRARDADDRL11": { + "direction": "IN" + }, + "ADDRBWRADDRL8": { + "direction": "IN" + }, + "TSTWROS11": { + "direction": "IN" + }, + "DOADO13": { + "direction": "OUT" + }, + "TSTWRCNTOFF": { + "direction": "IN" + }, + "TSTWROS6": { + "direction": "IN" + }, + "WRCOUNT3": { + "direction": "OUT" + }, + "TSTIN0": { + "direction": "IN" + }, + "TSTIN4": { + "direction": "IN" + }, + "ECCPARITY5": { + "direction": "OUT" + }, + "DOBDO6": { + "direction": "OUT" + }, + "RSTREGARSTREGL": { + "direction": "IN" + }, + "RDCOUNT11": { + "direction": "OUT" + }, + "ENBWRENU": { + "direction": "IN" + }, + "WRCOUNT11": { + "direction": "OUT" + }, + "TSTCNT4": { + "direction": "IN" + }, + "RDCOUNT9": { + "direction": "OUT" + }, + "REGCEAREGCEU": { + "direction": "IN" + }, + "DOADO4": { + "direction": "OUT" + }, + "ADDRBWRADDRL9": { + "direction": "IN" + }, + "DIBDI22": { + "direction": "IN" + }, + "ADDRBWRADDRU5": { + "direction": "IN" + }, + "WEBWEU1": { + "direction": "IN" + }, + "DIBDI6": { + "direction": "IN" + }, + "WEAU0": { + "direction": "IN" + }, + "WEBWEL3": { + "direction": "IN" + }, + "DOBDO27": { + "direction": "OUT" + }, + "ADDRBWRADDRL5": { + "direction": "IN" + }, + "ALMOSTEMPTY": { + "direction": "OUT" + }, + "DIADI10": { + "direction": "IN" + }, + "ADDRBWRADDRU13": { + "direction": "IN" + }, + "WEBWEU2": { + "direction": "IN" + }, + "ALMOSTFULL": { + "direction": "OUT" + }, + "DIADI19": { + "direction": "IN" + }, + "ADDRBWRADDRL3": { + "direction": "IN" + }, + "DOPBDOP1": { + "direction": "OUT" + }, + "TSTCNT9": { + "direction": "IN" + }, + "DIADI1": { + "direction": "IN" + }, + "TSTWROS1": { + "direction": "IN" + }, + "DIBDI7": { + "direction": "IN" + }, + "ECCPARITY6": { + "direction": "OUT" + }, + "DOBDO0": { + "direction": "OUT" + }, + "TSTWROS8": { + "direction": "IN" + }, + "ADDRBWRADDRU7": { + "direction": "IN" + }, + "WEBWEL0": { + "direction": "IN" + }, + "DOADO1": { + "direction": "OUT" + }, + "DOPBDOP0": { + "direction": "OUT" + }, + "ENARDENU": { + "direction": "IN" + }, + "RDCOUNT7": { + "direction": "OUT" + }, + "DOADO23": { + "direction": "OUT" + }, + "CASCADEINA": { + "direction": "IN" + }, + "WEAL3": { + "direction": "IN" + }, + "ADDRARDADDRU8": { + "direction": "IN" + }, + "DIBDI0": { + "direction": "IN" + }, + "CLKBWRCLKL": { + "direction": "IN" + }, + "DIPBDIP2": { + "direction": "IN" + }, + "DOBDO7": { + "direction": "OUT" + }, + "WEBWEU3": { + "direction": "IN" + }, + "DOBDO16": { + "direction": "OUT" + }, + "DIADI15": { + "direction": "IN" + }, + "DOPADOP1": { + "direction": "OUT" + }, + "DOBDO31": { + "direction": "OUT" + }, + "TSTFLAGIN": { + "direction": "IN" + }, + "WRCOUNT0": { + "direction": "OUT" + }, + "TSTOUT0": { + "direction": "OUT" + }, + "TSTRDOS9": { + "direction": "IN" + }, + "ECCPARITY4": { + "direction": "OUT" + }, + "DIBDI23": { + "direction": "IN" + }, + "DOADO21": { + "direction": "OUT" + }, + "ADDRARDADDRU14": { + "direction": "IN" + }, + "RDCOUNT8": { + "direction": "OUT" + }, + "DIBDI29": { + "direction": "IN" + }, + "TSTOUT3": { + "direction": "OUT" + }, + "RSTREGBL": { + "direction": "IN" + }, + "ECCPARITY3": { + "direction": "OUT" + }, + "DOBDO20": { + "direction": "OUT" + }, + "DIBDI12": { + "direction": "IN" + }, + "DIADI7": { + "direction": "IN" + }, + "ADDRBWRADDRL15": { + "direction": "IN" + }, + "WEAL1": { + "direction": "IN" + }, + "DIADI0": { + "direction": "IN" + }, + "ENBWRENL": { + "direction": "IN" + }, + "DOBDO9": { + "direction": "OUT" + }, + "ADDRARDADDRL5": { + "direction": "IN" + }, + "DOBDO22": { + "direction": "OUT" + }, + "TSTOUT1": { + "direction": "OUT" + }, + "ADDRBWRADDRU2": { + "direction": "IN" + }, + "DIBDI30": { + "direction": "IN" + }, + "ADDRARDADDRU0": { + "direction": "IN" + }, + "TSTRDOS2": { + "direction": "IN" + }, + "DIBDI16": { + "direction": "IN" + }, + "DIPBDIP3": { + "direction": "IN" + }, + "ADDRARDADDRL12": { + "direction": "IN" + }, + "ADDRARDADDRU6": { + "direction": "IN" + }, + "ADDRARDADDRU4": { + "direction": "IN" + }, + "WEAU1": { + "direction": "IN" + }, + "REGCEBU": { + "direction": "IN" + }, + "DOADO28": { + "direction": "OUT" + }, + "ADDRARDADDRL7": { + "direction": "IN" + }, + "ADDRBWRADDRL10": { + "direction": "IN" + }, + "CLKBWRCLKU": { + "direction": "IN" + }, + "DIPADIP1": { + "direction": "IN" + }, + "DOBDO2": { + "direction": "OUT" + }, + "ADDRARDADDRU13": { + "direction": "IN" + }, + "DOADO9": { + "direction": "OUT" + }, + "DOBDO10": { + "direction": "OUT" + }, + "DIBDI2": { + "direction": "IN" + }, + "DOADO7": { + "direction": "OUT" + }, + "CLKARDCLKU": { + "direction": "IN" + }, + "DOBDO24": { + "direction": "OUT" + }, + "DIADI18": { + "direction": "IN" + }, + "TSTIN2": { + "direction": "IN" + }, + "DIBDI8": { + "direction": "IN" + }, + "ADDRBWRADDRL2": { + "direction": "IN" + }, + "RSTREGARSTREGU": { + "direction": "IN" + }, + "WEBWEU4": { + "direction": "IN" + }, + "DOPADOP0": { + "direction": "OUT" + }, + "ADDRBWRADDRU3": { + "direction": "IN" + }, + "RDCOUNT0": { + "direction": "OUT" + }, + "WRCOUNT2": { + "direction": "OUT" + }, + "CASCADEINB": { + "direction": "IN" + }, + "TSTCNT1": { + "direction": "IN" + }, + "TSTOUT4": { + "direction": "OUT" + }, + "TSTRDOS7": { + "direction": "IN" + }, + "DOADO24": { + "direction": "OUT" + }, + "RSTRAMBL": { + "direction": "IN" + }, + "RDCOUNT4": { + "direction": "OUT" + }, + "ADDRBWRADDRL4": { "direction": "IN" }, "RDCOUNT5": { @@ -531,705 +1006,230 @@ "WRCOUNT8": { "direction": "OUT" }, - "DIBDI5": { - "direction": "IN" - }, - "DOBDO24": { - "direction": "OUT" - }, - "ADDRBWRADDRL7": { - "direction": "IN" - }, - "TSTWROS7": { - "direction": "IN" - }, - "DIADI18": { - "direction": "IN" - }, - "TSTWROS9": { - "direction": "IN" - }, - "WEAU1": { - "direction": "IN" - }, - "DOADO21": { - "direction": "OUT" - }, - "ADDRBWRADDRL11": { - "direction": "IN" - }, - "ECCPARITY3": { - "direction": "OUT" - }, - "TSTCNT6": { - "direction": "IN" - }, - "DIADI6": { - "direction": "IN" - }, - "DOADO28": { - "direction": "OUT" - }, - "DIPBDIP0": { - "direction": "IN" - }, - "DOADO27": { - "direction": "OUT" - }, - "DOBDO26": { - "direction": "OUT" - }, - "DIBDI10": { - "direction": "IN" - }, - "DOBDO12": { - "direction": "OUT" - }, - "DIBDI20": { - "direction": "IN" - }, - "DOADO22": { - "direction": "OUT" - }, - "DIBDI31": { - "direction": "IN" - }, - "DOADO1": { - "direction": "OUT" - }, - "TSTRDOS5": { - "direction": "IN" - }, - "ECCPARITY1": { - "direction": "OUT" - }, - "TSTCNT1": { - "direction": "IN" - }, - "TSTWROS10": { - "direction": "IN" - }, - "DOBDO16": { - "direction": "OUT" - }, - "DOBDO25": { - "direction": "OUT" - }, - "CLKARDCLKL": { - "direction": "IN" - }, - "RDCOUNT9": { - "direction": "OUT" - }, - "TSTRDOS7": { - "direction": "IN" - }, - "TSTIN4": { - "direction": "IN" - }, - "TSTRDOS9": { - "direction": "IN" - }, - "DOBDO5": { - "direction": "OUT" - }, - "WEBWEU3": { - "direction": "IN" - }, - "ADDRARDADDRL5": { - "direction": "IN" - }, - "INJECTSBITERR": { - "direction": "IN" - }, - "DOADO17": { - "direction": "OUT" - }, - "TSTWROS4": { - "direction": "IN" - }, - "ADDRBWRADDRL14": { - "direction": "IN" - }, - "ECCPARITY0": { - "direction": "OUT" - }, - "DIADI3": { - "direction": "IN" - }, - "DIBDI2": { - "direction": "IN" - }, - "DOADO5": { - "direction": "OUT" - }, - "WRERR": { - "direction": "OUT" - }, - "RDCOUNT6": { - "direction": "OUT" - }, - "DIBDI29": { - "direction": "IN" - }, - "CLKARDCLKU": { - "direction": "IN" - }, - "DIADI8": { - "direction": "IN" - }, - "ADDRARDADDRU7": { - "direction": "IN" - }, - "ECCPARITY2": { - "direction": "OUT" - }, - "INJECTDBITERR": { - "direction": "IN" - }, - "WRCOUNT6": { - "direction": "OUT" - }, - "RDCOUNT11": { - "direction": "OUT" - }, - "WEBWEU2": { - "direction": "IN" - }, - "ADDRARDADDRL11": { - "direction": "IN" - }, - "DIBDI23": { - "direction": "IN" - }, - "DOADO30": { - "direction": "OUT" - }, - "DIADI2": { - "direction": "IN" - }, - "WEBWEL0": { - "direction": "IN" - }, - "WEBWEU0": { - "direction": "IN" - }, - "WEBWEU1": { - "direction": "IN" - }, - "DIPBDIP3": { - "direction": "IN" - }, - "ALMOSTEMPTY": { - "direction": "OUT" - }, - "ADDRARDADDRU4": { - "direction": "IN" - }, - "DOBDO29": { - "direction": "OUT" - }, - "TSTRDOS0": { - "direction": "IN" - }, - "DOBDO23": { - "direction": "OUT" - }, - "REGCEAREGCEL": { - "direction": "IN" - }, - "DIBDI22": { - "direction": "IN" - }, - "REGCLKBU": { - "direction": "IN" - }, - "DOADO8": { - "direction": "OUT" - }, - "DOADO26": { - "direction": "OUT" - }, - "ADDRBWRADDRU9": { - "direction": "IN" - }, - "TSTRDOS1": { - "direction": "IN" - }, - "RSTREGBU": { - "direction": "IN" - }, - "DIPBDIP2": { - "direction": "IN" - }, - "ADDRARDADDRU14": { - "direction": "IN" - }, - "ADDRBWRADDRU0": { - "direction": "IN" - }, - "TSTIN1": { - "direction": "IN" - }, - "WRCOUNT9": { - "direction": "OUT" - }, - "DOBDO6": { - "direction": "OUT" - }, - "ADDRARDADDRU11": { - "direction": "IN" - }, - "DOADO24": { - "direction": "OUT" - }, - "TSTCNT12": { - "direction": "IN" - }, - "DIADI9": { - "direction": "IN" - }, - "ENBWRENL": { - "direction": "IN" - }, - "TSTCNT2": { - "direction": "IN" - }, - "DOADO15": { - "direction": "OUT" - }, - "ADDRBWRADDRL4": { - "direction": "IN" - }, - "ADDRARDADDRL1": { - "direction": "IN" - }, - "TSTRDOS11": { - "direction": "IN" - }, - "ADDRARDADDRL3": { - "direction": "IN" - }, - "RDCOUNT2": { - "direction": "OUT" - }, - "TSTWROS8": { - "direction": "IN" - }, - "RDCOUNT4": { - "direction": "OUT" - }, - "TSTRDOS3": { - "direction": "IN" - }, - "DIADI25": { + "DIADI13": { "direction": "IN" }, "DIBDI24": { "direction": "IN" }, - "DOBDO28": { + "DIBDI31": { + "direction": "IN" + }, + "WEBWEL4": { + "direction": "IN" + }, + "DIADI6": { + "direction": "IN" + }, + "ADDRBWRADDRU8": { + "direction": "IN" + }, + "DOADO30": { "direction": "OUT" }, - "DIADI19": { + "RSTRAMARSTRAMU": { "direction": "IN" }, - "REGCLKARDRCLKL": { - "direction": "IN" - }, - "ADDRBWRADDRU3": { - "direction": "IN" - }, - "DIADI24": { - "direction": "IN" - }, - "DOADO23": { - "direction": "OUT" - }, - "ADDRBWRADDRL13": { - "direction": "IN" - }, - "DOADO20": { - "direction": "OUT" - }, - "WEBWEL1": { - "direction": "IN" - }, - "DIBDI25": { - "direction": "IN" - }, - "DIADI31": { - "direction": "IN" - }, - "ADDRARDADDRL13": { - "direction": "IN" - }, - "ENBWRENU": { - "direction": "IN" - }, - "ADDRBWRADDRL8": { - "direction": "IN" - }, - "REGCLKARDRCLKU": { - "direction": "IN" - }, - "ADDRARDADDRU13": { - "direction": "IN" - }, - "RDCOUNT1": { - "direction": "OUT" - }, - "DOADO16": { - "direction": "OUT" - }, - "ADDRBWRADDRL3": { - "direction": "IN" - }, - "WEAL1": { - "direction": "IN" - }, - "WRCOUNT5": { - "direction": "OUT" - }, - "TSTWROS0": { - "direction": "IN" - }, - "RDCOUNT0": { - "direction": "OUT" - }, - "TSTRDCNTOFF": { - "direction": "IN" - }, - "DOBDO9": { - "direction": "OUT" - }, - "DIBDI16": { - "direction": "IN" - }, - "ENARDENU": { - "direction": "IN" - }, - "ADDRBWRADDRU12": { - "direction": "IN" - }, - "DIADI16": { - "direction": "IN" - }, - "TSTCNT9": { - "direction": "IN" - }, - "TSTCNT0": { - "direction": "IN" - }, - "DOPADOP1": { - "direction": "OUT" - }, - "DIADI14": { - "direction": "IN" - }, - "DIADI11": { - "direction": "IN" - }, - "DIADI21": { - "direction": "IN" - }, - "ADDRARDADDRU3": { - "direction": "IN" - }, - "DIBDI8": { - "direction": "IN" - }, - "DOADO7": { - "direction": "OUT" - }, - "WRCOUNT1": { - "direction": "OUT" - }, - "TSTIN0": { - "direction": "IN" - }, - "CLKBWRCLKL": { - "direction": "IN" - }, - "TSTWROS2": { - "direction": "IN" - }, - "DOPBDOP1": { - "direction": "OUT" - }, - "ADDRBWRADDRL10": { - "direction": "IN" - }, - "TSTIN2": { - "direction": "IN" - }, - "TSTWROS6": { - "direction": "IN" - }, - "ADDRBWRADDRU5": { + "DIPADIP0": { "direction": "IN" }, "RSTRAMARSTRAMLRST": { "direction": "IN" }, - "DOBDO31": { + "ADDRARDADDRL14": { + "direction": "IN" + }, + "TSTCNT10": { + "direction": "IN" + }, + "ADDRARDADDRL8": { + "direction": "IN" + }, + "ADDRBWRADDRU12": { + "direction": "IN" + }, + "DOADO20": { "direction": "OUT" }, - "DIPADIP1": { - "direction": "IN" - }, - "DOADO6": { + "DOBDO11": { "direction": "OUT" }, - "WRCOUNT0": { + "ADDRARDADDRL2": { + "direction": "IN" + }, + "DIBDI5": { + "direction": "IN" + }, + "ADDRARDADDRL0": { + "direction": "IN" + }, + "DIBDI27": { + "direction": "IN" + }, + "DOADO0": { "direction": "OUT" }, - "ADDRBWRADDRU10": { - "direction": "IN" - }, - "REGCEBL": { - "direction": "IN" - }, - "WRCOUNT2": { + "WRCOUNT5": { "direction": "OUT" }, - "ADDRARDADDRU10": { - "direction": "IN" - }, - "DIADI17": { - "direction": "IN" - }, - "DOBDO8": { + "DOBDO26": { "direction": "OUT" }, - "ADDRBWRADDRU8": { + "DIADI22": { "direction": "IN" }, - "DIBDI12": { - "direction": "IN" + "DOADO26": { + "direction": "OUT" }, - "DIBDI4": { - "direction": "IN" + "DOADO16": { + "direction": "OUT" }, - "TSTCNT5": { + "ADDRBWRADDRU6": { "direction": "IN" }, "DOBDO17": { "direction": "OUT" }, - "TSTOUT1": { + "ADDRARDADDRU9": { + "direction": "IN" + }, + "TSTRDOS4": { + "direction": "IN" + }, + "TSTWROS10": { + "direction": "IN" + }, + "DOADO14": { "direction": "OUT" }, - "WRCOUNT7": { + "DIBDI28": { + "direction": "IN" + }, + "ADDRBWRADDRU0": { + "direction": "IN" + }, + "ADDRARDADDRL3": { + "direction": "IN" + }, + "WEBWEL2": { + "direction": "IN" + }, + "TSTWROS7": { + "direction": "IN" + }, + "ECCPARITY7": { "direction": "OUT" }, - "TSTWRCNTOFF": { + "TSTCNT11": { "direction": "IN" }, - "ADDRBWRADDRU13": { + "REGCEBL": { "direction": "IN" }, - "DIBDI7": { - "direction": "IN" - }, - "DOADO12": { + "DOADO22": { "direction": "OUT" }, - "ADDRARDADDRU8": { + "ADDRARDADDRU10": { "direction": "IN" }, - "ADDRARDADDRU0": { + "WEBWEL7": { "direction": "IN" }, - "WEAL2": { + "TSTRDOS6": { "direction": "IN" }, - "CASCADEOUTA": { + "TSTWROS5": { + "direction": "IN" + }, + "ECCPARITY1": { "direction": "OUT" }, - "DOBDO7": { - "direction": "OUT" - }, - "DIBDI3": { + "DIADI8": { "direction": "IN" }, - "DOADO9": { + "TSTCNT6": { + "direction": "IN" + }, + "TSTCNT2": { + "direction": "IN" + }, + "ADDRBWRADDRL7": { + "direction": "IN" + }, + "TSTIN1": { + "direction": "IN" + }, + "WEBWEU5": { + "direction": "IN" + }, + "WEAU3": { + "direction": "IN" + }, + "TSTRDOS10": { + "direction": "IN" + }, + "DOADO11": { "direction": "OUT" }, - "TSTIN3": { + "DOADO27": { + "direction": "OUT" + }, + "WEAU2": { "direction": "IN" }, + "WEBWEL5": { + "direction": "IN" + }, + "ADDRBWRADDRU4": { + "direction": "IN" + }, + "REGCEAREGCEL": { + "direction": "IN" + }, + "DOADO31": { + "direction": "OUT" + }, + "SBITERR": { + "direction": "OUT" + }, + "DIBDI15": { + "direction": "IN" + }, + "ADDRBWRADDRL11": { + "direction": "IN" + }, + "DOBDO3": { + "direction": "OUT" + }, + "TSTRDCNTOFF": { + "direction": "IN" + }, + "DIADI4": { + "direction": "IN" + }, + "DIADI27": { + "direction": "IN" + }, + "ADDRARDADDRU1": { + "direction": "IN" + }, + "DIBDI11": { + "direction": "IN" + }, + "RDCOUNT3": { + "direction": "OUT" + }, + "DOBDO18": { + "direction": "OUT" + }, + "DOADO17": { + "direction": "OUT" + }, "TSTCNT7": { "direction": "IN" }, - "DOBDO13": { - "direction": "OUT" - }, - "DIADI4": { + "TSTWROS12": { "direction": "IN" } - }, - "type": "RAMBFIFO36E1", - "site_pips": { - "RSTREGARSTREGUINV:RSTREGARSTREGU_B": { - "from_pin": "RSTREGARSTREGU_B", - "to_pin": "OUT" - }, - "RSTRAMBUINV:RSTRAMBU": { - "from_pin": "RSTRAMBU", - "to_pin": "OUT" - }, - "REGCLKBUINV:REGCLKBU_B": { - "from_pin": "REGCLKBU_B", - "to_pin": "OUT" - }, - "RSTREGARSTREGLINV:RSTREGARSTREGL_B": { - "from_pin": "RSTREGARSTREGL_B", - "to_pin": "OUT" - }, - "REGCLKBLINV:REGCLKBL_B": { - "from_pin": "REGCLKBL_B", - "to_pin": "OUT" - }, - "CLKBWRCLKLINV:CLKBWRCLKL": { - "from_pin": "CLKBWRCLKL", - "to_pin": "OUT" - }, - "RSTREGBUINV:RSTREGBU": { - "from_pin": "RSTREGBU", - "to_pin": "OUT" - }, - "ENARDENLINV:ENARDENL_B": { - "from_pin": "ENARDENL_B", - "to_pin": "OUT" - }, - "RSTRAMARSTRAMLRSTINV:RSTRAMARSTRAMLRST": { - "from_pin": "RSTRAMARSTRAMLRST", - "to_pin": "OUT" - }, - "ENBWRENUINV:ENBWRENU_B": { - "from_pin": "ENBWRENU_B", - "to_pin": "OUT" - }, - "REGCLKBUINV:REGCLKBU": { - "from_pin": "REGCLKBU", - "to_pin": "OUT" - }, - "CLKARDCLKUINV:CLKARDCLKU_B": { - "from_pin": "CLKARDCLKU_B", - "to_pin": "OUT" - }, - "ENARDENUINV:ENARDENU": { - "from_pin": "ENARDENU", - "to_pin": "OUT" - }, - "ENBWRENLINV:ENBWRENL_B": { - "from_pin": "ENBWRENL_B", - "to_pin": "OUT" - }, - "RSTRAMARSTRAMUINV:RSTRAMARSTRAMU_B": { - "from_pin": "RSTRAMARSTRAMU_B", - "to_pin": "OUT" - }, - "CLKBWRCLKUINV:CLKBWRCLKU_B": { - "from_pin": "CLKBWRCLKU_B", - "to_pin": "OUT" - }, - "REGCLKARDRCLKUINV:REGCLKARDRCLKU_B": { - "from_pin": "REGCLKARDRCLKU_B", - "to_pin": "OUT" - }, - "RSTRAMBUINV:RSTRAMBU_B": { - "from_pin": "RSTRAMBU_B", - "to_pin": "OUT" - }, - "RSTREGBUINV:RSTREGBU_B": { - "from_pin": "RSTREGBU_B", - "to_pin": "OUT" - }, - "CLKARDCLKLINV:CLKARDCLKL": { - "from_pin": "CLKARDCLKL", - "to_pin": "OUT" - }, - "RSTRAMBLINV:RSTRAMBL": { - "from_pin": "RSTRAMBL", - "to_pin": "OUT" - }, - "REGCLKARDRCLKUINV:REGCLKARDRCLKU": { - "from_pin": "REGCLKARDRCLKU", - "to_pin": "OUT" - }, - "RSTRAMBLINV:RSTRAMBL_B": { - "from_pin": "RSTRAMBL_B", - "to_pin": "OUT" - }, - "ENBWRENUINV:ENBWRENU": { - "from_pin": "ENBWRENU", - "to_pin": "OUT" - }, - "RSTRAMARSTRAMUINV:RSTRAMARSTRAMU": { - "from_pin": "RSTRAMARSTRAMU", - "to_pin": "OUT" - }, - "REGCLKARDRCLKLINV:REGCLKARDRCLKL_B": { - "from_pin": "REGCLKARDRCLKL_B", - "to_pin": "OUT" - }, - "CLKBWRCLKLINV:CLKBWRCLKL_B": { - "from_pin": "CLKBWRCLKL_B", - "to_pin": "OUT" - }, - "CLKARDCLKUINV:CLKARDCLKU": { - "from_pin": "CLKARDCLKU", - "to_pin": "OUT" - }, - "RSTREGBLINV:RSTREGBL_B": { - "from_pin": "RSTREGBL_B", - "to_pin": "OUT" - }, - "RSTREGBLINV:RSTREGBL": { - "from_pin": "RSTREGBL", - "to_pin": "OUT" - }, - "RSTRAMARSTRAMLRSTINV:RSTRAMARSTRAMLRST_B": { - "from_pin": "RSTRAMARSTRAMLRST_B", - "to_pin": "OUT" - }, - "REGCLKBLINV:REGCLKBL": { - "from_pin": "REGCLKBL", - "to_pin": "OUT" - }, - "CLKBWRCLKUINV:CLKBWRCLKU": { - "from_pin": "CLKBWRCLKU", - "to_pin": "OUT" - }, - "ENARDENUINV:ENARDENU_B": { - "from_pin": "ENARDENU_B", - "to_pin": "OUT" - }, - "ENARDENLINV:ENARDENL": { - "from_pin": "ENARDENL", - "to_pin": "OUT" - }, - "ENBWRENLINV:ENBWRENL": { - "from_pin": "ENBWRENL", - "to_pin": "OUT" - }, - "RSTREGARSTREGUINV:RSTREGARSTREGU": { - "from_pin": "RSTREGARSTREGU", - "to_pin": "OUT" - }, - "CLKARDCLKLINV:CLKARDCLKL_B": { - "from_pin": "CLKARDCLKL_B", - "to_pin": "OUT" - }, - "REGCLKARDRCLKLINV:REGCLKARDRCLKL": { - "from_pin": "REGCLKARDRCLKL", - "to_pin": "OUT" - }, - "RSTREGARSTREGLINV:RSTREGARSTREGL": { - "from_pin": "RSTREGARSTREGL", - "to_pin": "OUT" - } } } \ No newline at end of file diff --git a/artix7/site_type_SLICEL.json b/artix7/site_type_SLICEL.json index 4f6d0fb..cc48a80 100644 --- a/artix7/site_type_SLICEL.json +++ b/artix7/site_type_SLICEL.json @@ -1,694 +1,694 @@ { + "type": "SLICEL", + "site_pips": { + "B5LUT:A2": { + "to_pin": "O5", + "from_pin": "A2" + }, + "D5LUT:A3": { + "to_pin": "O5", + "from_pin": "A3" + }, + "CCY0:CX": { + "to_pin": "OUT", + "from_pin": "CX" + }, + "C6LUT:A1": { + "to_pin": "O6", + "from_pin": "A1" + }, + "A6LUT:A2": { + "to_pin": "O6", + "from_pin": "A2" + }, + "A5LUT:A5": { + "to_pin": "O5", + "from_pin": "A5" + }, + "CFFMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "D5FFMUX:IN_A": { + "to_pin": "OUT", + "from_pin": "IN_A" + }, + "DOUTMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "C5LUT:A2": { + "to_pin": "O5", + "from_pin": "A2" + }, + "A5LUT:A3": { + "to_pin": "O5", + "from_pin": "A3" + }, + "D5LUT:A2": { + "to_pin": "O5", + "from_pin": "A2" + }, + "DFFMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "BFFMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "ACY0:AX": { + "to_pin": "OUT", + "from_pin": "AX" + }, + "CFFMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "COUTUSED:CARRY4_0": { + "to_pin": "OUT", + "from_pin": "CARRY4_0" + }, + "COUTMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "CLKINV:CLK": { + "to_pin": "OUT", + "from_pin": "CLK" + }, + "CFFMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "AFFMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "B5LUT:A3": { + "to_pin": "O5", + "from_pin": "A3" + }, + "AFFMUX:F7": { + "to_pin": "OUT", + "from_pin": "F7" + }, + "B6LUT:A3": { + "to_pin": "O6", + "from_pin": "A3" + }, + "A5FFMUX:IN_A": { + "to_pin": "OUT", + "from_pin": "IN_A" + }, + "BFFMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "COUTMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "BOUTMUX:F8": { + "to_pin": "OUT", + "from_pin": "F8" + }, + "A6LUT:A3": { + "to_pin": "O6", + "from_pin": "A3" + }, + "BUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "PRECYINIT:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "D6LUT:A3": { + "to_pin": "O6", + "from_pin": "A3" + }, + "COUTMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "D6LUT:A4": { + "to_pin": "O6", + "from_pin": "A4" + }, + "SRUSEDMUX:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "AOUTMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "D5FFMUX:IN_B": { + "to_pin": "OUT", + "from_pin": "IN_B" + }, + "C6LUT:A2": { + "to_pin": "O6", + "from_pin": "A2" + }, + "ACY0:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "AFFMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "DFFMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "DCY0:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "C6LUT:A6": { + "to_pin": "O6", + "from_pin": "A6" + }, + "B5LUT:A4": { + "to_pin": "O5", + "from_pin": "A4" + }, + "B6LUT:A2": { + "to_pin": "O6", + "from_pin": "A2" + }, + "DCY0:DX": { + "to_pin": "OUT", + "from_pin": "DX" + }, + "B6LUT:A6": { + "to_pin": "O6", + "from_pin": "A6" + }, + "C5LUT:A1": { + "to_pin": "O5", + "from_pin": "A1" + }, + "AOUTMUX:F7": { + "to_pin": "OUT", + "from_pin": "F7" + }, + "C5LUT:A4": { + "to_pin": "O5", + "from_pin": "A4" + }, + "COUTMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "AFFMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "CFFMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "BFFMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "AOUTMUX:A5Q": { + "to_pin": "OUT", + "from_pin": "A5Q" + }, + "C6LUT:A3": { + "to_pin": "O6", + "from_pin": "A3" + }, + "PRECYINIT:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "BOUTMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "COUTMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "C5FFMUX:IN_B": { + "to_pin": "OUT", + "from_pin": "IN_B" + }, + "BOUTMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "A5LUT:A2": { + "to_pin": "O5", + "from_pin": "A2" + }, + "CFFMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "BFFMUX:F8": { + "to_pin": "OUT", + "from_pin": "F8" + }, + "A5FFMUX:IN_B": { + "to_pin": "OUT", + "from_pin": "IN_B" + }, + "DOUTMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "DFFMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "CUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "A6LUT:A4": { + "to_pin": "O6", + "from_pin": "A4" + }, + "B5FFMUX:IN_A": { + "to_pin": "OUT", + "from_pin": "IN_A" + }, + "AFFMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "B6LUT:A5": { + "to_pin": "O6", + "from_pin": "A5" + }, + "A6LUT:A6": { + "to_pin": "O6", + "from_pin": "A6" + }, + "AOUTMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "DFFMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "A6LUT:A5": { + "to_pin": "O6", + "from_pin": "A5" + }, + "PRECYINIT:CIN": { + "to_pin": "OUT", + "from_pin": "CIN" + }, + "COUTUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "CFFMUX:F7": { + "to_pin": "OUT", + "from_pin": "F7" + }, + "B6LUT:A4": { + "to_pin": "O6", + "from_pin": "A4" + }, + "BCY0:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "COUTMUX:C5Q": { + "to_pin": "OUT", + "from_pin": "C5Q" + }, + "CFFMUX:CX": { + "to_pin": "OUT", + "from_pin": "CX" + }, + "D6LUT:A2": { + "to_pin": "O6", + "from_pin": "A2" + }, + "AOUTMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "BOUTMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "DFFMUX:DX": { + "to_pin": "OUT", + "from_pin": "DX" + }, + "DOUTMUX:D5Q": { + "to_pin": "OUT", + "from_pin": "D5Q" + }, + "CEUSEDMUX:IN": { + "to_pin": "OUT", + "from_pin": "IN" + }, + "BOUTMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "D5LUT:A5": { + "to_pin": "O5", + "from_pin": "A5" + }, + "A6LUT:A1": { + "to_pin": "O6", + "from_pin": "A1" + }, + "COUTMUX:F7": { + "to_pin": "OUT", + "from_pin": "F7" + }, + "A5LUT:A1": { + "to_pin": "O5", + "from_pin": "A1" + }, + "BOUTMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "AOUTMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "B5LUT:A1": { + "to_pin": "O5", + "from_pin": "A1" + }, + "DUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "D5LUT:A1": { + "to_pin": "O5", + "from_pin": "A1" + }, + "BFFMUX:BX": { + "to_pin": "OUT", + "from_pin": "BX" + }, + "BOUTMUX:B5Q": { + "to_pin": "OUT", + "from_pin": "B5Q" + }, + "AFFMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "C5LUT:A5": { + "to_pin": "O5", + "from_pin": "A5" + }, + "BCY0:BX": { + "to_pin": "OUT", + "from_pin": "BX" + }, + "B5LUT:A5": { + "to_pin": "O5", + "from_pin": "A5" + }, + "D6LUT:A1": { + "to_pin": "O6", + "from_pin": "A1" + }, + "AOUTMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "CCY0:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "AUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "SRUSEDMUX:IN": { + "to_pin": "OUT", + "from_pin": "IN" + }, + "C6LUT:A5": { + "to_pin": "O6", + "from_pin": "A5" + }, + "COUTMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "AFFMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "DOUTMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "BFFMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "C5LUT:A3": { + "to_pin": "O5", + "from_pin": "A3" + }, + "DOUTMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "BFFMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "C6LUT:A4": { + "to_pin": "O6", + "from_pin": "A4" + }, + "DFFMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "AFFMUX:AX": { + "to_pin": "OUT", + "from_pin": "AX" + }, + "CFFMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "DFFMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "DOUTMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "CLKINV:CLK_B": { + "to_pin": "OUT", + "from_pin": "CLK_B" + }, + "D6LUT:A5": { + "to_pin": "O6", + "from_pin": "A5" + }, + "B6LUT:A1": { + "to_pin": "O6", + "from_pin": "A1" + }, + "D6LUT:A6": { + "to_pin": "O6", + "from_pin": "A6" + }, + "CEUSEDMUX:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "AOUTMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "PRECYINIT:AX": { + "to_pin": "OUT", + "from_pin": "AX" + }, + "BOUTMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "C5FFMUX:IN_A": { + "to_pin": "OUT", + "from_pin": "IN_A" + }, + "DOUTMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "A5LUT:A4": { + "to_pin": "O5", + "from_pin": "A4" + }, + "B5FFMUX:IN_B": { + "to_pin": "OUT", + "from_pin": "IN_B" + }, + "D5LUT:A4": { + "to_pin": "O5", + "from_pin": "A4" + }, + "BFFMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + } + }, "site_pins": { - "CE": { - "direction": "IN" - }, - "C4": { - "direction": "IN" - }, - "C3": { - "direction": "IN" - }, - "C6": { - "direction": "IN" - }, - "CLK": { - "direction": "IN" - }, - "C1": { - "direction": "IN" - }, - "AMUX": { - "direction": "OUT" - }, - "A3": { - "direction": "IN" - }, - "D3": { - "direction": "IN" - }, - "A": { - "direction": "OUT" - }, - "SR": { - "direction": "IN" - }, - "CMUX": { - "direction": "OUT" - }, - "CQ": { - "direction": "OUT" - }, - "C": { - "direction": "OUT" - }, - "A2": { - "direction": "IN" - }, - "B2": { - "direction": "IN" - }, "BMUX": { "direction": "OUT" }, - "CIN": { - "direction": "IN" - }, - "COUT": { - "direction": "OUT" - }, - "D6": { - "direction": "IN" - }, - "CX": { - "direction": "IN" - }, - "B5": { - "direction": "IN" - }, - "A4": { + "B1": { "direction": "IN" }, "C5": { "direction": "IN" }, - "B1": { + "D1": { "direction": "IN" }, - "BQ": { - "direction": "OUT" - }, - "DQ": { - "direction": "OUT" - }, - "D": { - "direction": "OUT" - }, - "C2": { - "direction": "IN" - }, - "A1": { - "direction": "IN" - }, - "D5": { - "direction": "IN" - }, - "DMUX": { - "direction": "OUT" - }, - "A6": { + "C1": { "direction": "IN" }, "AQ": { "direction": "OUT" }, - "BX": { + "AMUX": { + "direction": "OUT" + }, + "B4": { "direction": "IN" }, - "A5": { + "A1": { "direction": "IN" }, - "D2": { + "C4": { + "direction": "IN" + }, + "A2": { "direction": "IN" }, "AX": { "direction": "IN" }, - "D1": { + "D": { + "direction": "OUT" + }, + "A5": { + "direction": "IN" + }, + "BX": { "direction": "IN" }, "D4": { "direction": "IN" }, - "DX": { + "DMUX": { + "direction": "OUT" + }, + "C3": { "direction": "IN" }, - "B4": { + "D6": { "direction": "IN" }, - "B6": { - "direction": "IN" - }, - "B3": { + "SR": { "direction": "IN" }, "B": { "direction": "OUT" - } - }, - "type": "SLICEL", - "site_pips": { - "BFFMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" }, - "DCY0:O5": { - "from_pin": "O5", - "to_pin": "OUT" + "COUT": { + "direction": "OUT" }, - "DUSED:0": { - "from_pin": "0", - "to_pin": "OUT" + "B6": { + "direction": "IN" }, - "B5FFMUX:IN_A": { - "from_pin": "IN_A", - "to_pin": "OUT" + "A": { + "direction": "OUT" }, - "AOUTMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" + "CIN": { + "direction": "IN" }, - "COUTMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" + "CE": { + "direction": "IN" }, - "C6LUT:A5": { - "from_pin": "A5", - "to_pin": "O6" + "C2": { + "direction": "IN" }, - "C5FFMUX:IN_A": { - "from_pin": "IN_A", - "to_pin": "OUT" + "D3": { + "direction": "IN" }, - "B6LUT:A4": { - "from_pin": "A4", - "to_pin": "O6" + "DQ": { + "direction": "OUT" }, - "BFFMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" + "D5": { + "direction": "IN" }, - "C5LUT:A1": { - "from_pin": "A1", - "to_pin": "O5" + "C6": { + "direction": "IN" }, - "ACY0:AX": { - "from_pin": "AX", - "to_pin": "OUT" + "BQ": { + "direction": "OUT" }, - "AFFMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" + "D2": { + "direction": "IN" }, - "A6LUT:A6": { - "from_pin": "A6", - "to_pin": "O6" + "CMUX": { + "direction": "OUT" }, - "SRUSEDMUX:0": { - "from_pin": "0", - "to_pin": "OUT" + "A6": { + "direction": "IN" }, - "CFFMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" + "CX": { + "direction": "IN" }, - "A6LUT:A5": { - "from_pin": "A5", - "to_pin": "O6" + "B2": { + "direction": "IN" }, - "DOUTMUX:D5Q": { - "from_pin": "D5Q", - "to_pin": "OUT" + "B5": { + "direction": "IN" }, - "C5LUT:A2": { - "from_pin": "A2", - "to_pin": "O5" + "CQ": { + "direction": "OUT" }, - "C6LUT:A1": { - "from_pin": "A1", - "to_pin": "O6" + "A4": { + "direction": "IN" }, - "B6LUT:A6": { - "from_pin": "A6", - "to_pin": "O6" + "C": { + "direction": "OUT" }, - "AFFMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" + "B3": { + "direction": "IN" }, - "C6LUT:A3": { - "from_pin": "A3", - "to_pin": "O6" + "DX": { + "direction": "IN" }, - "A5FFMUX:IN_B": { - "from_pin": "IN_B", - "to_pin": "OUT" + "A3": { + "direction": "IN" }, - "PRECYINIT:AX": { - "from_pin": "AX", - "to_pin": "OUT" - }, - "BOUTMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "AOUTMUX:A5Q": { - "from_pin": "A5Q", - "to_pin": "OUT" - }, - "AFFMUX:AX": { - "from_pin": "AX", - "to_pin": "OUT" - }, - "COUTUSED:CARRY4_0": { - "from_pin": "CARRY4_0", - "to_pin": "OUT" - }, - "COUTMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "BCY0:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "B6LUT:A3": { - "from_pin": "A3", - "to_pin": "O6" - }, - "CFFMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "A6LUT:A4": { - "from_pin": "A4", - "to_pin": "O6" - }, - "D5LUT:A3": { - "from_pin": "A3", - "to_pin": "O5" - }, - "BOUTMUX:F8": { - "from_pin": "F8", - "to_pin": "OUT" - }, - "COUTMUX:F7": { - "from_pin": "F7", - "to_pin": "OUT" - }, - "SRUSEDMUX:IN": { - "from_pin": "IN", - "to_pin": "OUT" - }, - "A5LUT:A5": { - "from_pin": "A5", - "to_pin": "O5" - }, - "PRECYINIT:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "B6LUT:A1": { - "from_pin": "A1", - "to_pin": "O6" - }, - "DFFMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "BOUTMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" - }, - "CUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "BOUTMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "B6LUT:A5": { - "from_pin": "A5", - "to_pin": "O6" - }, - "DOUTMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "DOUTMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" - }, - "BUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "DOUTMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "BFFMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "AUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "A5LUT:A4": { - "from_pin": "A4", - "to_pin": "O5" - }, - "D6LUT:A1": { - "from_pin": "A1", - "to_pin": "O6" - }, - "D6LUT:A3": { - "from_pin": "A3", - "to_pin": "O6" - }, - "CFFMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "DFFMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "AOUTMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "BOUTMUX:B5Q": { - "from_pin": "B5Q", - "to_pin": "OUT" - }, - "D5LUT:A4": { - "from_pin": "A4", - "to_pin": "O5" - }, - "AOUTMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "BFFMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "DOUTMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "ACY0:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "AFFMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "CFFMUX:F7": { - "from_pin": "F7", - "to_pin": "OUT" - }, - "CFFMUX:CX": { - "from_pin": "CX", - "to_pin": "OUT" - }, - "COUTMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "A5LUT:A1": { - "from_pin": "A1", - "to_pin": "O5" - }, - "BFFMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "DOUTMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "C5LUT:A3": { - "from_pin": "A3", - "to_pin": "O5" - }, - "DFFMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "BOUTMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "B5LUT:A3": { - "from_pin": "A3", - "to_pin": "O5" - }, - "BOUTMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "A5FFMUX:IN_A": { - "from_pin": "IN_A", - "to_pin": "OUT" - }, - "DFFMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "C5LUT:A5": { - "from_pin": "A5", - "to_pin": "O5" - }, - "D5LUT:A1": { - "from_pin": "A1", - "to_pin": "O5" - }, - "BOUTMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "C6LUT:A2": { - "from_pin": "A2", - "to_pin": "O6" - }, - "D5FFMUX:IN_B": { - "from_pin": "IN_B", - "to_pin": "OUT" - }, - "AOUTMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" - }, - "C6LUT:A4": { - "from_pin": "A4", - "to_pin": "O6" - }, - "DCY0:DX": { - "from_pin": "DX", - "to_pin": "OUT" - }, - "C5FFMUX:IN_B": { - "from_pin": "IN_B", - "to_pin": "OUT" - }, - "B5LUT:A4": { - "from_pin": "A4", - "to_pin": "O5" - }, - "DFFMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" - }, - "D6LUT:A6": { - "from_pin": "A6", - "to_pin": "O6" - }, - "CFFMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "COUTMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "PRECYINIT:CIN": { - "from_pin": "CIN", - "to_pin": "OUT" - }, - "BFFMUX:F8": { - "from_pin": "F8", - "to_pin": "OUT" - }, - "A5LUT:A2": { - "from_pin": "A2", - "to_pin": "O5" - }, - "CCY0:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "AFFMUX:F7": { - "from_pin": "F7", - "to_pin": "OUT" - }, - "AFFMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "B6LUT:A2": { - "from_pin": "A2", - "to_pin": "O6" - }, - "D5FFMUX:IN_A": { - "from_pin": "IN_A", - "to_pin": "OUT" - }, - "A6LUT:A2": { - "from_pin": "A2", - "to_pin": "O6" - }, - "BFFMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "AOUTMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "BCY0:BX": { - "from_pin": "BX", - "to_pin": "OUT" - }, - "DFFMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "B5FFMUX:IN_B": { - "from_pin": "IN_B", - "to_pin": "OUT" - }, - "A6LUT:A3": { - "from_pin": "A3", - "to_pin": "O6" - }, - "AFFMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "CEUSEDMUX:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "CCY0:CX": { - "from_pin": "CX", - "to_pin": "OUT" - }, - "D6LUT:A4": { - "from_pin": "A4", - "to_pin": "O6" - }, - "BFFMUX:BX": { - "from_pin": "BX", - "to_pin": "OUT" - }, - "D5LUT:A5": { - "from_pin": "A5", - "to_pin": "O5" - }, - "A5LUT:A3": { - "from_pin": "A3", - "to_pin": "O5" - }, - "D6LUT:A5": { - "from_pin": "A5", - "to_pin": "O6" - }, - "DFFMUX:DX": { - "from_pin": "DX", - "to_pin": "OUT" - }, - "AOUTMUX:F7": { - "from_pin": "F7", - "to_pin": "OUT" - }, - "COUTUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "COUTMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "CFFMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "DOUTMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "CEUSEDMUX:IN": { - "from_pin": "IN", - "to_pin": "OUT" - }, - "B5LUT:A2": { - "from_pin": "A2", - "to_pin": "O5" - }, - "C6LUT:A6": { - "from_pin": "A6", - "to_pin": "O6" - }, - "B5LUT:A5": { - "from_pin": "A5", - "to_pin": "O5" - }, - "PRECYINIT:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "COUTMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "COUTMUX:C5Q": { - "from_pin": "C5Q", - "to_pin": "OUT" - }, - "CLKINV:CLK": { - "from_pin": "CLK", - "to_pin": "OUT" - }, - "C5LUT:A4": { - "from_pin": "A4", - "to_pin": "O5" - }, - "AOUTMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "D5LUT:A2": { - "from_pin": "A2", - "to_pin": "O5" - }, - "A6LUT:A1": { - "from_pin": "A1", - "to_pin": "O6" - }, - "B5LUT:A1": { - "from_pin": "A1", - "to_pin": "O5" - }, - "D6LUT:A2": { - "from_pin": "A2", - "to_pin": "O6" - }, - "AFFMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "CLKINV:CLK_B": { - "from_pin": "CLK_B", - "to_pin": "OUT" - }, - "CFFMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" + "CLK": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_SLICEM.json b/artix7/site_type_SLICEM.json index 381d88b..12dfa78 100644 --- a/artix7/site_type_SLICEM.json +++ b/artix7/site_type_SLICEM.json @@ -1,769 +1,769 @@ { + "type": "SLICEM", + "site_pips": { + "WEMUX:CE": { + "to_pin": "OUT", + "from_pin": "CE" + }, + "B5LUT:A2": { + "to_pin": "O5", + "from_pin": "A2" + }, + "D5LUT:A3": { + "to_pin": "O5", + "from_pin": "A3" + }, + "CCY0:CX": { + "to_pin": "OUT", + "from_pin": "CX" + }, + "C6LUT:A1": { + "to_pin": "O6", + "from_pin": "A1" + }, + "A6LUT:A2": { + "to_pin": "O6", + "from_pin": "A2" + }, + "DFFMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "A5LUT:A5": { + "to_pin": "O5", + "from_pin": "A5" + }, + "CFFMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "D5FFMUX:IN_A": { + "to_pin": "OUT", + "from_pin": "IN_A" + }, + "CDI1MUX:DI": { + "to_pin": "OUT", + "from_pin": "DI" + }, + "DOUTMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "BOUTMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "A5LUT:A3": { + "to_pin": "O5", + "from_pin": "A3" + }, + "D5LUT:A2": { + "to_pin": "O5", + "from_pin": "A2" + }, + "DFFMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "BFFMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "CDI1MUX:DMC31": { + "to_pin": "OUT", + "from_pin": "DMC31" + }, + "ACY0:AX": { + "to_pin": "OUT", + "from_pin": "AX" + }, + "CFFMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "COUTUSED:CARRY4_0": { + "to_pin": "OUT", + "from_pin": "CARRY4_0" + }, + "DFFMUX:MC31": { + "to_pin": "OUT", + "from_pin": "MC31" + }, + "CLKINV:CLK": { + "to_pin": "OUT", + "from_pin": "CLK" + }, + "DOUTMUX:MC31": { + "to_pin": "OUT", + "from_pin": "MC31" + }, + "BDI1MUX:BI": { + "to_pin": "OUT", + "from_pin": "BI" + }, + "B5LUT:A3": { + "to_pin": "O5", + "from_pin": "A3" + }, + "AFFMUX:F7": { + "to_pin": "OUT", + "from_pin": "F7" + }, + "B6LUT:A3": { + "to_pin": "O6", + "from_pin": "A3" + }, + "A5FFMUX:IN_A": { + "to_pin": "OUT", + "from_pin": "IN_A" + }, + "BFFMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "COUTMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "BOUTMUX:F8": { + "to_pin": "OUT", + "from_pin": "F8" + }, + "DCY0:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "BUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "PRECYINIT:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "WEMUX:WE": { + "to_pin": "OUT", + "from_pin": "WE" + }, + "COUTMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "D6LUT:A4": { + "to_pin": "O6", + "from_pin": "A4" + }, + "WA7USED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "AOUTMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "D5FFMUX:IN_B": { + "to_pin": "OUT", + "from_pin": "IN_B" + }, + "C6LUT:A2": { + "to_pin": "O6", + "from_pin": "A2" + }, + "ACY0:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "AFFMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "DFFMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "C5LUT:A5": { + "to_pin": "O5", + "from_pin": "A5" + }, + "C6LUT:A6": { + "to_pin": "O6", + "from_pin": "A6" + }, + "B5LUT:A4": { + "to_pin": "O5", + "from_pin": "A4" + }, + "B6LUT:A2": { + "to_pin": "O6", + "from_pin": "A2" + }, + "DCY0:DX": { + "to_pin": "OUT", + "from_pin": "DX" + }, + "B6LUT:A6": { + "to_pin": "O6", + "from_pin": "A6" + }, + "C5LUT:A1": { + "to_pin": "O5", + "from_pin": "A1" + }, + "AOUTMUX:F7": { + "to_pin": "OUT", + "from_pin": "F7" + }, + "C5LUT:A4": { + "to_pin": "O5", + "from_pin": "A4" + }, + "COUTMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "CDI1MUX:CI": { + "to_pin": "OUT", + "from_pin": "CI" + }, + "AFFMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "C5LUT:A2": { + "to_pin": "O5", + "from_pin": "A2" + }, + "CFFMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "BFFMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "AOUTMUX:A5Q": { + "to_pin": "OUT", + "from_pin": "A5Q" + }, + "C6LUT:A3": { + "to_pin": "O6", + "from_pin": "A3" + }, + "PRECYINIT:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "BOUTMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "COUTMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "C5FFMUX:IN_B": { + "to_pin": "OUT", + "from_pin": "IN_B" + }, + "AFFMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "COUTMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "SRUSEDMUX:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "CFFMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "BFFMUX:F8": { + "to_pin": "OUT", + "from_pin": "F8" + }, + "A5FFMUX:IN_B": { + "to_pin": "OUT", + "from_pin": "IN_B" + }, + "DOUTMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "BFFMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "ADI1MUX:BMC31": { + "to_pin": "OUT", + "from_pin": "BMC31" + }, + "CUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "A6LUT:A4": { + "to_pin": "O6", + "from_pin": "A4" + }, + "WA8USED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "BOUTMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "AFFMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "B6LUT:A5": { + "to_pin": "O6", + "from_pin": "A5" + }, + "A6LUT:A6": { + "to_pin": "O6", + "from_pin": "A6" + }, + "AOUTMUX:XOR": { + "to_pin": "OUT", + "from_pin": "XOR" + }, + "DFFMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "A6LUT:A5": { + "to_pin": "O6", + "from_pin": "A5" + }, + "PRECYINIT:CIN": { + "to_pin": "OUT", + "from_pin": "CIN" + }, + "COUTUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "CFFMUX:F7": { + "to_pin": "OUT", + "from_pin": "F7" + }, + "ADI1MUX:AI": { + "to_pin": "OUT", + "from_pin": "AI" + }, + "B6LUT:A4": { + "to_pin": "O6", + "from_pin": "A4" + }, + "BCY0:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "COUTMUX:C5Q": { + "to_pin": "OUT", + "from_pin": "C5Q" + }, + "CFFMUX:CX": { + "to_pin": "OUT", + "from_pin": "CX" + }, + "D6LUT:A2": { + "to_pin": "O6", + "from_pin": "A2" + }, + "AOUTMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "BOUTMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "DFFMUX:DX": { + "to_pin": "OUT", + "from_pin": "DX" + }, + "DOUTMUX:D5Q": { + "to_pin": "OUT", + "from_pin": "D5Q" + }, + "CEUSEDMUX:IN": { + "to_pin": "OUT", + "from_pin": "IN" + }, + "BOUTMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "D5LUT:A5": { + "to_pin": "O5", + "from_pin": "A5" + }, + "A6LUT:A1": { + "to_pin": "O6", + "from_pin": "A1" + }, + "COUTMUX:F7": { + "to_pin": "OUT", + "from_pin": "F7" + }, + "A5LUT:A1": { + "to_pin": "O5", + "from_pin": "A1" + }, + "BOUTMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "AOUTMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "B5LUT:A1": { + "to_pin": "O5", + "from_pin": "A1" + }, + "DUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "D5LUT:A1": { + "to_pin": "O5", + "from_pin": "A1" + }, + "BFFMUX:BX": { + "to_pin": "OUT", + "from_pin": "BX" + }, + "BDI1MUX:DI": { + "to_pin": "OUT", + "from_pin": "DI" + }, + "D6LUT:A3": { + "to_pin": "O6", + "from_pin": "A3" + }, + "BOUTMUX:B5Q": { + "to_pin": "OUT", + "from_pin": "B5Q" + }, + "AFFMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "BCY0:BX": { + "to_pin": "OUT", + "from_pin": "BX" + }, + "B5LUT:A5": { + "to_pin": "O5", + "from_pin": "A5" + }, + "D6LUT:A1": { + "to_pin": "O6", + "from_pin": "A1" + }, + "AOUTMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "BFFMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "A6LUT:A3": { + "to_pin": "O6", + "from_pin": "A3" + }, + "CFFMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "CCY0:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "AUSED:0": { + "to_pin": "OUT", + "from_pin": "0" + }, + "SRUSEDMUX:IN": { + "to_pin": "OUT", + "from_pin": "IN" + }, + "C6LUT:A5": { + "to_pin": "O6", + "from_pin": "A5" + }, + "COUTMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "AFFMUX:O5": { + "to_pin": "OUT", + "from_pin": "O5" + }, + "DOUTMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "BFFMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "C5LUT:A3": { + "to_pin": "O5", + "from_pin": "A3" + }, + "DOUTMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "A5LUT:A2": { + "to_pin": "O5", + "from_pin": "A2" + }, + "C6LUT:A4": { + "to_pin": "O6", + "from_pin": "A4" + }, + "DFFMUX:O6": { + "to_pin": "OUT", + "from_pin": "O6" + }, + "AFFMUX:AX": { + "to_pin": "OUT", + "from_pin": "AX" + }, + "CFFMUX:CARRY4_XOR": { + "to_pin": "OUT", + "from_pin": "CARRY4_XOR" + }, + "DFFMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "DOUTMUX:CY": { + "to_pin": "OUT", + "from_pin": "CY" + }, + "CLKINV:CLK_B": { + "to_pin": "OUT", + "from_pin": "CLK_B" + }, + "ADI1MUX:BDI1": { + "to_pin": "OUT", + "from_pin": "BDI1" + }, + "D6LUT:A5": { + "to_pin": "O6", + "from_pin": "A5" + }, + "BDI1MUX:CMC31": { + "to_pin": "OUT", + "from_pin": "CMC31" + }, + "B6LUT:A1": { + "to_pin": "O6", + "from_pin": "A1" + }, + "D6LUT:A6": { + "to_pin": "O6", + "from_pin": "A6" + }, + "CEUSEDMUX:1": { + "to_pin": "OUT", + "from_pin": "1" + }, + "AOUTMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "PRECYINIT:AX": { + "to_pin": "OUT", + "from_pin": "AX" + }, + "B5FFMUX:IN_A": { + "to_pin": "OUT", + "from_pin": "IN_A" + }, + "C5FFMUX:IN_A": { + "to_pin": "OUT", + "from_pin": "IN_A" + }, + "DOUTMUX:CARRY4_MUX": { + "to_pin": "OUT", + "from_pin": "CARRY4_MUX" + }, + "A5LUT:A4": { + "to_pin": "O5", + "from_pin": "A4" + }, + "D5LUT:A4": { + "to_pin": "O5", + "from_pin": "A4" + }, + "B5FFMUX:IN_B": { + "to_pin": "OUT", + "from_pin": "IN_B" + } + }, "site_pins": { - "CE": { - "direction": "IN" - }, - "C4": { - "direction": "IN" - }, - "C3": { - "direction": "IN" - }, - "C6": { - "direction": "IN" - }, - "CLK": { - "direction": "IN" - }, - "C1": { - "direction": "IN" - }, - "AMUX": { - "direction": "OUT" - }, - "A3": { - "direction": "IN" - }, - "A": { - "direction": "OUT" - }, - "SR": { - "direction": "IN" - }, - "CMUX": { - "direction": "OUT" - }, - "CQ": { - "direction": "OUT" - }, - "C": { - "direction": "OUT" - }, - "A2": { - "direction": "IN" - }, - "B2": { - "direction": "IN" - }, "BMUX": { "direction": "OUT" }, - "CIN": { - "direction": "IN" - }, - "COUT": { - "direction": "OUT" - }, - "D6": { - "direction": "IN" - }, - "D3": { - "direction": "IN" - }, - "B5": { - "direction": "IN" - }, - "A4": { + "B1": { "direction": "IN" }, "C5": { "direction": "IN" }, - "DI": { - "direction": "IN" - }, - "B1": { - "direction": "IN" - }, - "WE": { - "direction": "IN" - }, - "BQ": { - "direction": "OUT" - }, - "DQ": { - "direction": "OUT" - }, - "D": { - "direction": "OUT" - }, - "C2": { - "direction": "IN" - }, - "A1": { - "direction": "IN" - }, - "AI": { - "direction": "IN" - }, - "D5": { - "direction": "IN" - }, - "CI": { - "direction": "IN" - }, - "DMUX": { - "direction": "OUT" - }, - "CX": { - "direction": "IN" - }, - "A6": { - "direction": "IN" - }, - "AQ": { - "direction": "OUT" - }, - "BX": { - "direction": "IN" - }, - "A5": { - "direction": "IN" - }, - "D2": { - "direction": "IN" - }, - "BI": { - "direction": "IN" - }, - "AX": { - "direction": "IN" - }, "D1": { "direction": "IN" }, - "D4": { - "direction": "IN" - }, - "DX": { - "direction": "IN" - }, - "B4": { - "direction": "IN" - }, - "B6": { - "direction": "IN" - }, "B3": { "direction": "IN" }, + "AQ": { + "direction": "OUT" + }, + "AMUX": { + "direction": "OUT" + }, + "WE": { + "direction": "IN" + }, + "A1": { + "direction": "IN" + }, + "C4": { + "direction": "IN" + }, + "A2": { + "direction": "IN" + }, + "D3": { + "direction": "IN" + }, + "AX": { + "direction": "IN" + }, + "D": { + "direction": "OUT" + }, + "A5": { + "direction": "IN" + }, + "BX": { + "direction": "IN" + }, + "D4": { + "direction": "IN" + }, + "DMUX": { + "direction": "OUT" + }, + "AI": { + "direction": "IN" + }, + "C3": { + "direction": "IN" + }, + "D6": { + "direction": "IN" + }, + "SR": { + "direction": "IN" + }, "B": { "direction": "OUT" - } - }, - "type": "SLICEM", - "site_pips": { - "BFFMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" }, - "DCY0:O5": { - "from_pin": "O5", - "to_pin": "OUT" + "CX": { + "direction": "IN" }, - "DUSED:0": { - "from_pin": "0", - "to_pin": "OUT" + "BI": { + "direction": "IN" }, - "B5FFMUX:IN_A": { - "from_pin": "IN_A", - "to_pin": "OUT" + "B6": { + "direction": "IN" }, - "A5LUT:A4": { - "from_pin": "A4", - "to_pin": "O5" + "CI": { + "direction": "IN" }, - "CLKINV:CLK": { - "from_pin": "CLK", - "to_pin": "OUT" + "A": { + "direction": "OUT" }, - "COUTMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" + "CIN": { + "direction": "IN" }, - "C6LUT:A5": { - "from_pin": "A5", - "to_pin": "O6" + "CE": { + "direction": "IN" }, - "C5FFMUX:IN_A": { - "from_pin": "IN_A", - "to_pin": "OUT" + "C2": { + "direction": "IN" }, - "B6LUT:A4": { - "from_pin": "A4", - "to_pin": "O6" + "C1": { + "direction": "IN" }, - "BFFMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" + "DQ": { + "direction": "OUT" }, - "C5LUT:A1": { - "from_pin": "A1", - "to_pin": "O5" + "B4": { + "direction": "IN" }, - "ACY0:AX": { - "from_pin": "AX", - "to_pin": "OUT" + "D5": { + "direction": "IN" }, - "WEMUX:WE": { - "from_pin": "WE", - "to_pin": "OUT" + "C6": { + "direction": "IN" }, - "A6LUT:A6": { - "from_pin": "A6", - "to_pin": "O6" + "BQ": { + "direction": "OUT" }, - "SRUSEDMUX:0": { - "from_pin": "0", - "to_pin": "OUT" + "D2": { + "direction": "IN" }, - "CFFMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" + "CMUX": { + "direction": "OUT" }, - "A6LUT:A5": { - "from_pin": "A5", - "to_pin": "O6" + "A6": { + "direction": "IN" }, - "DOUTMUX:D5Q": { - "from_pin": "D5Q", - "to_pin": "OUT" + "B2": { + "direction": "IN" }, - "C5LUT:A2": { - "from_pin": "A2", - "to_pin": "O5" + "B5": { + "direction": "IN" }, - "C6LUT:A1": { - "from_pin": "A1", - "to_pin": "O6" + "CQ": { + "direction": "OUT" }, - "B6LUT:A6": { - "from_pin": "A6", - "to_pin": "O6" + "DI": { + "direction": "IN" }, - "AFFMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" + "A4": { + "direction": "IN" }, - "AFFMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" + "C": { + "direction": "OUT" }, - "A5FFMUX:IN_B": { - "from_pin": "IN_B", - "to_pin": "OUT" + "COUT": { + "direction": "OUT" }, - "PRECYINIT:AX": { - "from_pin": "AX", - "to_pin": "OUT" + "DX": { + "direction": "IN" }, - "BOUTMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" + "A3": { + "direction": "IN" }, - "DOUTMUX:MC31": { - "from_pin": "MC31", - "to_pin": "OUT" - }, - "AOUTMUX:A5Q": { - "from_pin": "A5Q", - "to_pin": "OUT" - }, - "AFFMUX:AX": { - "from_pin": "AX", - "to_pin": "OUT" - }, - "COUTUSED:CARRY4_0": { - "from_pin": "CARRY4_0", - "to_pin": "OUT" - }, - "COUTMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "BCY0:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "B6LUT:A3": { - "from_pin": "A3", - "to_pin": "O6" - }, - "CFFMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "A6LUT:A4": { - "from_pin": "A4", - "to_pin": "O6" - }, - "D5LUT:A3": { - "from_pin": "A3", - "to_pin": "O5" - }, - "BOUTMUX:F8": { - "from_pin": "F8", - "to_pin": "OUT" - }, - "COUTMUX:F7": { - "from_pin": "F7", - "to_pin": "OUT" - }, - "SRUSEDMUX:IN": { - "from_pin": "IN", - "to_pin": "OUT" - }, - "A5LUT:A5": { - "from_pin": "A5", - "to_pin": "O5" - }, - "PRECYINIT:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "B6LUT:A1": { - "from_pin": "A1", - "to_pin": "O6" - }, - "DFFMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "BOUTMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" - }, - "CUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "BOUTMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "B6LUT:A5": { - "from_pin": "A5", - "to_pin": "O6" - }, - "DOUTMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "DOUTMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" - }, - "BDI1MUX:DI": { - "from_pin": "DI", - "to_pin": "OUT" - }, - "BUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "BDI1MUX:BI": { - "from_pin": "BI", - "to_pin": "OUT" - }, - "BFFMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "AUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "DFFMUX:MC31": { - "from_pin": "MC31", - "to_pin": "OUT" - }, - "D6LUT:A1": { - "from_pin": "A1", - "to_pin": "O6" - }, - "D6LUT:A3": { - "from_pin": "A3", - "to_pin": "O6" - }, - "WEMUX:CE": { - "from_pin": "CE", - "to_pin": "OUT" - }, - "CFFMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "DFFMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "BOUTMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "BOUTMUX:B5Q": { - "from_pin": "B5Q", - "to_pin": "OUT" - }, - "AOUTMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "A6LUT:A1": { - "from_pin": "A1", - "to_pin": "O6" - }, - "BFFMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "ACY0:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "AFFMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "CFFMUX:F7": { - "from_pin": "F7", - "to_pin": "OUT" - }, - "CFFMUX:CX": { - "from_pin": "CX", - "to_pin": "OUT" - }, - "COUTMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "A5LUT:A1": { - "from_pin": "A1", - "to_pin": "O5" - }, - "BFFMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "DOUTMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "C5LUT:A3": { - "from_pin": "A3", - "to_pin": "O5" - }, - "DFFMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "CDI1MUX:CI": { - "from_pin": "CI", - "to_pin": "OUT" - }, - "BOUTMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "ADI1MUX:AI": { - "from_pin": "AI", - "to_pin": "OUT" - }, - "D5LUT:A1": { - "from_pin": "A1", - "to_pin": "O5" - }, - "A5FFMUX:IN_A": { - "from_pin": "IN_A", - "to_pin": "OUT" - }, - "DFFMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "WA7USED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "C5LUT:A5": { - "from_pin": "A5", - "to_pin": "O5" - }, - "CDI1MUX:DMC31": { - "from_pin": "DMC31", - "to_pin": "OUT" - }, - "DOUTMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "BOUTMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "C6LUT:A2": { - "from_pin": "A2", - "to_pin": "O6" - }, - "D5LUT:A4": { - "from_pin": "A4", - "to_pin": "O5" - }, - "ADI1MUX:BMC31": { - "from_pin": "BMC31", - "to_pin": "OUT" - }, - "AOUTMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" - }, - "C6LUT:A4": { - "from_pin": "A4", - "to_pin": "O6" - }, - "DCY0:DX": { - "from_pin": "DX", - "to_pin": "OUT" - }, - "C5FFMUX:IN_B": { - "from_pin": "IN_B", - "to_pin": "OUT" - }, - "D6LUT:A4": { - "from_pin": "A4", - "to_pin": "O6" - }, - "ADI1MUX:BDI1": { - "from_pin": "BDI1", - "to_pin": "OUT" - }, - "DFFMUX:CY": { - "from_pin": "CY", - "to_pin": "OUT" - }, - "D6LUT:A6": { - "from_pin": "A6", - "to_pin": "O6" - }, - "CFFMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "COUTMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "PRECYINIT:CIN": { - "from_pin": "CIN", - "to_pin": "OUT" - }, - "BFFMUX:F8": { - "from_pin": "F8", - "to_pin": "OUT" - }, - "A5LUT:A2": { - "from_pin": "A2", - "to_pin": "O5" - }, - "AOUTMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "CCY0:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "AFFMUX:F7": { - "from_pin": "F7", - "to_pin": "OUT" - }, - "AFFMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "B6LUT:A2": { - "from_pin": "A2", - "to_pin": "O6" - }, - "AOUTMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "A6LUT:A2": { - "from_pin": "A2", - "to_pin": "O6" - }, - "BFFMUX:BX": { - "from_pin": "BX", - "to_pin": "OUT" - }, - "AOUTMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "BCY0:BX": { - "from_pin": "BX", - "to_pin": "OUT" - }, - "DFFMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "B5FFMUX:IN_B": { - "from_pin": "IN_B", - "to_pin": "OUT" - }, - "A6LUT:A3": { - "from_pin": "A3", - "to_pin": "O6" - }, - "AFFMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "BDI1MUX:CMC31": { - "from_pin": "CMC31", - "to_pin": "OUT" - }, - "CEUSEDMUX:1": { - "from_pin": "1", - "to_pin": "OUT" - }, - "CCY0:CX": { - "from_pin": "CX", - "to_pin": "OUT" - }, - "B5LUT:A4": { - "from_pin": "A4", - "to_pin": "O5" - }, - "BFFMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "D5LUT:A5": { - "from_pin": "A5", - "to_pin": "O5" - }, - "CDI1MUX:DI": { - "from_pin": "DI", - "to_pin": "OUT" - }, - "A5LUT:A3": { - "from_pin": "A3", - "to_pin": "O5" - }, - "D6LUT:A5": { - "from_pin": "A5", - "to_pin": "O6" - }, - "D5FFMUX:IN_A": { - "from_pin": "IN_A", - "to_pin": "OUT" - }, - "WA8USED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "DFFMUX:DX": { - "from_pin": "DX", - "to_pin": "OUT" - }, - "AOUTMUX:F7": { - "from_pin": "F7", - "to_pin": "OUT" - }, - "COUTUSED:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "COUTMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "CFFMUX:CARRY4_XOR": { - "from_pin": "CARRY4_XOR", - "to_pin": "OUT" - }, - "DOUTMUX:O5": { - "from_pin": "O5", - "to_pin": "OUT" - }, - "CEUSEDMUX:IN": { - "from_pin": "IN", - "to_pin": "OUT" - }, - "B5LUT:A3": { - "from_pin": "A3", - "to_pin": "O5" - }, - "C6LUT:A6": { - "from_pin": "A6", - "to_pin": "O6" - }, - "B5LUT:A5": { - "from_pin": "A5", - "to_pin": "O5" - }, - "B5LUT:A2": { - "from_pin": "A2", - "to_pin": "O5" - }, - "PRECYINIT:0": { - "from_pin": "0", - "to_pin": "OUT" - }, - "COUTMUX:O6": { - "from_pin": "O6", - "to_pin": "OUT" - }, - "COUTMUX:C5Q": { - "from_pin": "C5Q", - "to_pin": "OUT" - }, - "C6LUT:A3": { - "from_pin": "A3", - "to_pin": "O6" - }, - "C5LUT:A4": { - "from_pin": "A4", - "to_pin": "O5" - }, - "AOUTMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" - }, - "D5LUT:A2": { - "from_pin": "A2", - "to_pin": "O5" - }, - "D5FFMUX:IN_B": { - "from_pin": "IN_B", - "to_pin": "OUT" - }, - "B5LUT:A1": { - "from_pin": "A1", - "to_pin": "O5" - }, - "D6LUT:A2": { - "from_pin": "A2", - "to_pin": "O6" - }, - "DOUTMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "AFFMUX:CARRY4_MUX": { - "from_pin": "CARRY4_MUX", - "to_pin": "OUT" - }, - "CLKINV:CLK_B": { - "from_pin": "CLK_B", - "to_pin": "OUT" - }, - "CFFMUX:XOR": { - "from_pin": "XOR", - "to_pin": "OUT" + "CLK": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/site_type_STARTUP.json b/artix7/site_type_STARTUP.json index 1aab297..73efe86 100644 --- a/artix7/site_type_STARTUP.json +++ b/artix7/site_type_STARTUP.json @@ -1,45 +1,45 @@ { + "type": "STARTUP", + "site_pips": {}, "site_pins": { - "PREQ": { - "direction": "OUT" - }, - "EOS": { - "direction": "OUT" - }, - "USRDONETS": { - "direction": "IN" - }, - "PACK": { - "direction": "IN" - }, "GTS": { "direction": "IN" }, - "CFGCLK": { - "direction": "OUT" - }, - "CLK": { - "direction": "IN" - }, - "GSR": { - "direction": "IN" - }, - "USRDONEO": { - "direction": "IN" - }, - "USRCCLKTS": { - "direction": "IN" - }, "USRCCLKO": { "direction": "IN" }, - "KEYCLEARB": { + "CFGCLK": { + "direction": "OUT" + }, + "USRCCLKTS": { "direction": "IN" }, + "USRDONETS": { + "direction": "IN" + }, + "PREQ": { + "direction": "OUT" + }, + "CLK": { + "direction": "IN" + }, + "PACK": { + "direction": "IN" + }, + "EOS": { + "direction": "OUT" + }, "CFGMCLK": { "direction": "OUT" + }, + "GSR": { + "direction": "IN" + }, + "KEYCLEARB": { + "direction": "IN" + }, + "USRDONEO": { + "direction": "IN" } - }, - "type": "STARTUP", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_TIEOFF.json b/artix7/site_type_TIEOFF.json index 5a0364d..954593d 100644 --- a/artix7/site_type_TIEOFF.json +++ b/artix7/site_type_TIEOFF.json @@ -1,4 +1,6 @@ { + "type": "TIEOFF", + "site_pips": {}, "site_pins": { "HARD1": { "direction": "OUT" @@ -6,7 +8,5 @@ "HARD0": { "direction": "OUT" } - }, - "type": "TIEOFF", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_USR_ACCESS.json b/artix7/site_type_USR_ACCESS.json index c52f9e6..663eabe 100644 --- a/artix7/site_type_USR_ACCESS.json +++ b/artix7/site_type_USR_ACCESS.json @@ -1,84 +1,62 @@ { + "type": "USR_ACCESS", + "site_pips": {}, "site_pins": { - "DATA5": { - "direction": "OUT" - }, - "DATA16": { - "direction": "OUT" - }, - "DATA1": { - "direction": "OUT" - }, - "DATA26": { - "direction": "OUT" - }, - "DATA7": { - "direction": "OUT" - }, "DATA2": { "direction": "OUT" }, - "DATA12": { - "direction": "OUT" - }, - "DATA11": { - "direction": "OUT" - }, - "DATA19": { - "direction": "OUT" - }, - "DATA0": { - "direction": "OUT" - }, - "DATA15": { - "direction": "OUT" - }, - "DATA31": { - "direction": "OUT" - }, - "DATA28": { - "direction": "OUT" - }, - "DATA10": { - "direction": "OUT" - }, - "DATA24": { - "direction": "OUT" - }, - "DATA3": { - "direction": "OUT" - }, - "DATAVALID": { + "DATA20": { "direction": "OUT" }, "DATA17": { "direction": "OUT" }, - "DATA25": { + "DATA24": { "direction": "OUT" }, "DATA13": { "direction": "OUT" }, + "DATA14": { + "direction": "OUT" + }, + "DATA0": { + "direction": "OUT" + }, + "DATA1": { + "direction": "OUT" + }, "DATA27": { "direction": "OUT" }, - "DATA9": { - "direction": "OUT" - }, - "DATA29": { - "direction": "OUT" - }, - "DATA18": { + "DATA4": { "direction": "OUT" }, "CFGCLK": { "direction": "OUT" }, - "DATA6": { + "DATA11": { "direction": "OUT" }, - "DATA23": { + "DATA9": { + "direction": "OUT" + }, + "DATA30": { + "direction": "OUT" + }, + "DATA10": { + "direction": "OUT" + }, + "DATA29": { + "direction": "OUT" + }, + "DATA31": { + "direction": "OUT" + }, + "DATA15": { + "direction": "OUT" + }, + "DATA18": { "direction": "OUT" }, "DATA8": { @@ -87,22 +65,44 @@ "DATA22": { "direction": "OUT" }, + "DATA23": { + "direction": "OUT" + }, + "DATA6": { + "direction": "OUT" + }, + "DATA25": { + "direction": "OUT" + }, + "DATA5": { + "direction": "OUT" + }, + "DATA3": { + "direction": "OUT" + }, + "DATA16": { + "direction": "OUT" + }, + "DATA12": { + "direction": "OUT" + }, + "DATA19": { + "direction": "OUT" + }, + "DATA26": { + "direction": "OUT" + }, + "DATA7": { + "direction": "OUT" + }, + "DATA28": { + "direction": "OUT" + }, "DATA21": { "direction": "OUT" }, - "DATA14": { - "direction": "OUT" - }, - "DATA30": { - "direction": "OUT" - }, - "DATA4": { - "direction": "OUT" - }, - "DATA20": { + "DATAVALID": { "direction": "OUT" } - }, - "type": "USR_ACCESS", - "site_pips": {} + } } \ No newline at end of file diff --git a/artix7/site_type_XADC.json b/artix7/site_type_XADC.json index dbd9c03..ecf29b6 100644 --- a/artix7/site_type_XADC.json +++ b/artix7/site_type_XADC.json @@ -1,683 +1,683 @@ { + "type": "XADC", + "site_pips": { + "CONVSTCLKINV:CONVSTCLK": { + "to_pin": "OUT", + "from_pin": "CONVSTCLK" + }, + "CONVSTCLKINV:CONVSTCLK_B": { + "to_pin": "OUT", + "from_pin": "CONVSTCLK_B" + }, + "DCLKINV:DCLK_B": { + "to_pin": "OUT", + "from_pin": "DCLK_B" + }, + "DCLKINV:DCLK": { + "to_pin": "OUT", + "from_pin": "DCLK" + } + }, "site_pins": { - "VAUXP6": { - "direction": "IN" - }, - "VAUXP4": { - "direction": "IN" - }, - "TESTADCIN27": { - "direction": "IN" - }, - "TESTDB10": { - "direction": "OUT" - }, - "TESTADCIN211": { - "direction": "IN" - }, - "TESTADCIN24": { - "direction": "IN" - }, - "TESTADCIN10": { - "direction": "IN" - }, - "DO12": { - "direction": "OUT" - }, - "ALM4": { - "direction": "OUT" - }, - "DO7": { - "direction": "OUT" - }, - "DCLK": { - "direction": "IN" - }, - "VAUXN4": { - "direction": "IN" - }, - "CONVST": { - "direction": "IN" - }, - "TESTADCOUT1": { - "direction": "OUT" - }, - "TESTADCIN212": { - "direction": "IN" - }, - "TESTDB1": { - "direction": "OUT" - }, - "TESTADCIN28": { - "direction": "IN" - }, - "TESTADCOUT4": { - "direction": "OUT" - }, - "DADDR1": { - "direction": "IN" - }, - "TESTADCIN8": { - "direction": "IN" - }, - "DI5": { - "direction": "IN" - }, - "CHANNEL4": { - "direction": "OUT" - }, - "ALM3": { - "direction": "OUT" - }, - "VAUXP15": { - "direction": "IN" - }, - "TESTSCANMODE4": { - "direction": "IN" - }, - "TESTADCOUT11": { - "direction": "OUT" - }, - "DO2": { - "direction": "OUT" - }, - "VAUXN15": { - "direction": "IN" - }, - "TESTADCIN9": { - "direction": "IN" - }, - "VAUXN0": { - "direction": "IN" - }, - "DRDY": { - "direction": "OUT" - }, - "DEN": { - "direction": "IN" - }, - "TESTTDI": { - "direction": "IN" - }, - "RESET": { - "direction": "IN" - }, - "CHANNEL3": { - "direction": "OUT" - }, - "TESTDB8": { - "direction": "OUT" - }, - "VAUXP7": { - "direction": "IN" - }, - "TESTADCCLK1": { - "direction": "IN" - }, - "TESTCAPTURE": { - "direction": "IN" - }, - "VAUXP14": { - "direction": "IN" - }, - "VAUXP8": { - "direction": "IN" - }, - "TESTADCIN25": { - "direction": "IN" - }, - "DI9": { - "direction": "IN" - }, - "TESTADCIN29": { - "direction": "IN" - }, - "MUXADDR2": { - "direction": "OUT" - }, - "TESTADCOUT13": { - "direction": "OUT" - }, - "ALM5": { - "direction": "OUT" - }, - "VP": { - "direction": "IN" - }, - "TESTDB12": { - "direction": "OUT" - }, - "DO9": { - "direction": "OUT" - }, - "TESTADCIN11": { - "direction": "IN" - }, - "TESTADCIN12": { - "direction": "IN" - }, - "CHANNEL2": { - "direction": "OUT" - }, - "MUXADDR1": { - "direction": "OUT" - }, - "ALM0": { - "direction": "OUT" - }, - "VAUXN10": { - "direction": "IN" - }, - "DADDR0": { - "direction": "IN" - }, - "TESTADCIN4": { - "direction": "IN" - }, - "TESTADCOUT6": { - "direction": "OUT" - }, - "VAUXP9": { - "direction": "IN" - }, - "VAUXN7": { - "direction": "IN" - }, - "TESTADCOUT12": { - "direction": "OUT" - }, - "VAUXN12": { - "direction": "IN" - }, - "VAUXP1": { - "direction": "IN" - }, - "DADDR6": { - "direction": "IN" - }, - "DI1": { - "direction": "IN" - }, - "TESTADCIN20": { - "direction": "IN" - }, - "VAUXN6": { - "direction": "IN" - }, - "TESTSE3": { - "direction": "IN" - }, - "CHANNEL0": { - "direction": "OUT" - }, - "MUXADDR3": { - "direction": "OUT" - }, - "TESTSCANMODE0": { - "direction": "IN" - }, - "VAUXP11": { - "direction": "IN" - }, - "DO4": { - "direction": "OUT" - }, - "DO11": { - "direction": "OUT" - }, - "TESTADCIN26": { - "direction": "IN" - }, - "TESTADCCLK0": { - "direction": "IN" - }, - "DI7": { - "direction": "IN" - }, - "TESTSCANCLK1": { - "direction": "IN" - }, - "TESTSCANMODE1": { - "direction": "IN" - }, - "TESTADCCLK2": { - "direction": "IN" - }, - "TESTADCIN23": { - "direction": "IN" - }, - "TESTADCIN18": { - "direction": "IN" - }, - "TESTSI0": { - "direction": "IN" - }, - "DO15": { - "direction": "OUT" - }, - "TESTSI1": { - "direction": "IN" - }, - "TESTADCOUT8": { - "direction": "OUT" - }, - "TESTADCIN17": { - "direction": "IN" - }, - "TESTSE2": { - "direction": "IN" - }, - "VAUXN3": { - "direction": "IN" - }, - "TESTDB11": { - "direction": "OUT" - }, - "TESTADCOUT9": { - "direction": "OUT" - }, - "TESTSCANRESET": { - "direction": "IN" - }, - "TESTSCANMODE2": { - "direction": "IN" - }, - "TESTSO2": { - "direction": "OUT" - }, - "TESTADCIN214": { - "direction": "IN" - }, - "TESTADCOUT19": { - "direction": "OUT" - }, - "OT": { - "direction": "OUT" - }, - "DI14": { - "direction": "IN" - }, - "TESTDB13": { - "direction": "OUT" - }, - "VAUXN13": { - "direction": "IN" - }, - "DI2": { - "direction": "IN" - }, - "TESTADCIN19": { - "direction": "IN" - }, - "VAUXN2": { - "direction": "IN" - }, - "CONVSTCLK": { - "direction": "IN" - }, - "TESTSI2": { - "direction": "IN" - }, - "TESTADCIN217": { - "direction": "IN" - }, - "TESTADCIN5": { - "direction": "IN" - }, - "TESTDB0": { - "direction": "OUT" - }, - "TESTADCIN6": { - "direction": "IN" - }, - "DO8": { - "direction": "OUT" - }, - "ALM6": { - "direction": "OUT" - }, - "DI3": { - "direction": "IN" - }, - "VAUXP10": { - "direction": "IN" - }, - "DO0": { - "direction": "OUT" - }, - "DI8": { - "direction": "IN" - }, - "TESTADCIN21": { - "direction": "IN" - }, - "VAUXN8": { - "direction": "IN" - }, - "TESTADCOUT5": { - "direction": "OUT" - }, - "BUSY": { - "direction": "OUT" - }, - "TESTADCIN0": { - "direction": "IN" - }, - "TESTADCIN210": { - "direction": "IN" - }, - "TESTADCIN3": { - "direction": "IN" - }, - "DO5": { - "direction": "OUT" - }, - "JTAGMODIFIED": { - "direction": "OUT" - }, - "ALM7": { - "direction": "OUT" - }, - "DI6": { - "direction": "IN" - }, - "JTAGBUSY": { - "direction": "OUT" - }, - "TESTDB7": { - "direction": "OUT" - }, - "ALM1": { - "direction": "OUT" - }, - "VAUXP5": { - "direction": "IN" - }, - "DADDR4": { - "direction": "IN" - }, - "TESTSE0": { - "direction": "IN" - }, - "TESTSE4": { - "direction": "IN" - }, - "TESTSE1": { - "direction": "IN" - }, - "DI10": { - "direction": "IN" - }, - "TESTSEL": { - "direction": "IN" - }, - "DI12": { - "direction": "IN" - }, - "VAUXN11": { - "direction": "IN" - }, - "TESTADCOUT3": { - "direction": "OUT" - }, - "TESTADCIN1": { - "direction": "IN" - }, - "EOS": { - "direction": "OUT" - }, - "TESTSHIFT": { - "direction": "IN" - }, - "VAUXP13": { - "direction": "IN" - }, - "TESTADCIN16": { - "direction": "IN" - }, - "TESTTDO": { - "direction": "OUT" - }, "TESTADCOUT2": { "direction": "OUT" }, - "TESTADCOUT17": { - "direction": "OUT" - }, - "TESTADCOUT14": { - "direction": "OUT" - }, - "TESTADCIN215": { - "direction": "IN" - }, - "MUXADDR0": { - "direction": "OUT" - }, - "DADDR3": { - "direction": "IN" - }, - "VAUXN1": { - "direction": "IN" - }, - "TESTADCOUT7": { - "direction": "OUT" - }, - "DADDR2": { - "direction": "IN" - }, - "ALM2": { - "direction": "OUT" - }, - "TESTADCIN15": { - "direction": "IN" - }, - "TESTRST": { - "direction": "IN" - }, - "TESTSO0": { - "direction": "OUT" - }, - "TESTSCANMODE3": { - "direction": "IN" - }, - "TESTENJTAG": { - "direction": "IN" - }, - "DO10": { - "direction": "OUT" - }, - "DO13": { - "direction": "OUT" - }, - "TESTADCIN213": { - "direction": "IN" - }, - "TESTADCOUT0": { - "direction": "OUT" - }, - "DO6": { - "direction": "OUT" - }, - "VAUXN9": { - "direction": "IN" - }, - "TESTSCANCLK4": { - "direction": "IN" - }, - "VAUXP2": { - "direction": "IN" - }, - "DI13": { - "direction": "IN" - }, - "TESTDRCK": { - "direction": "IN" - }, - "TESTSI4": { - "direction": "IN" - }, - "TESTADCIN22": { - "direction": "IN" - }, - "TESTADCIN219": { - "direction": "IN" - }, - "TESTDB5": { - "direction": "OUT" - }, - "TESTDB4": { - "direction": "OUT" - }, - "TESTDB3": { - "direction": "OUT" - }, - "MUXADDR4": { - "direction": "OUT" - }, - "JTAGLOCKED": { - "direction": "OUT" - }, - "VAUXN5": { - "direction": "IN" - }, - "CHANNEL1": { - "direction": "OUT" - }, - "DO3": { - "direction": "OUT" - }, - "DO14": { - "direction": "OUT" - }, - "TESTSCANCLK3": { - "direction": "IN" - }, - "TESTDB15": { - "direction": "OUT" - }, - "TESTADCIN7": { - "direction": "IN" - }, - "VAUXP12": { - "direction": "IN" - }, - "TESTSO4": { - "direction": "OUT" - }, - "TESTADCIN2": { - "direction": "IN" - }, - "TESTSI3": { - "direction": "IN" - }, - "TESTADCIN216": { - "direction": "IN" - }, - "DI15": { - "direction": "IN" - }, - "TESTADCOUT15": { - "direction": "OUT" - }, - "TESTADCIN14": { - "direction": "IN" - }, - "VAUXP3": { - "direction": "IN" - }, - "TESTSO3": { - "direction": "OUT" - }, "DI0": { "direction": "IN" }, - "TESTADCOUT10": { + "TESTDB14": { "direction": "OUT" }, - "TESTSCANCLK0": { + "TESTADCIN27": { "direction": "IN" }, - "VAUXP0": { - "direction": "IN" - }, - "EOC": { + "TESTADCOUT17": { "direction": "OUT" }, - "TESTSCANCLK2": { + "TESTADCIN26": { + "direction": "IN" + }, + "DI2": { "direction": "IN" }, "TESTADCOUT16": { "direction": "OUT" }, - "TESTDB9": { + "ALM6": { "direction": "OUT" }, - "VN": { - "direction": "IN" - }, - "DI4": { + "TESTADCIN210": { "direction": "IN" }, "VAUXN14": { "direction": "IN" }, - "TESTSO1": { - "direction": "OUT" - }, - "TESTDB6": { - "direction": "OUT" - }, - "TESTADCIN218": { + "TESTSE0": { "direction": "IN" }, - "TESTDB14": { + "DO14": { "direction": "OUT" }, - "DWE": { + "ALM1": { + "direction": "OUT" + }, + "VAUXP9": { "direction": "IN" }, - "TESTADCIN13": { + "JTAGBUSY": { + "direction": "OUT" + }, + "VAUXN5": { "direction": "IN" }, - "DADDR5": { + "TESTADCOUT7": { + "direction": "OUT" + }, + "TESTADCOUT3": { + "direction": "OUT" + }, + "VAUXN13": { + "direction": "IN" + }, + "TESTADCOUT11": { + "direction": "OUT" + }, + "VAUXP1": { + "direction": "IN" + }, + "TESTDB12": { + "direction": "OUT" + }, + "VAUXN2": { + "direction": "IN" + }, + "TESTSE1": { + "direction": "IN" + }, + "TESTADCIN20": { + "direction": "IN" + }, + "TESTSCANMODE4": { + "direction": "IN" + }, + "DO11": { + "direction": "OUT" + }, + "TESTADCIN214": { + "direction": "IN" + }, + "TESTADCCLK1": { + "direction": "IN" + }, + "VAUXP2": { + "direction": "IN" + }, + "VAUXN0": { + "direction": "IN" + }, + "TESTADCIN16": { + "direction": "IN" + }, + "DI15": { "direction": "IN" }, "DO1": { "direction": "OUT" }, - "DI11": { + "TESTSE3": { "direction": "IN" }, - "TESTADCCLK3": { + "DEN": { + "direction": "IN" + }, + "TESTADCOUT12": { + "direction": "OUT" + }, + "DI4": { + "direction": "IN" + }, + "DI6": { + "direction": "IN" + }, + "CHANNEL0": { + "direction": "OUT" + }, + "DI8": { + "direction": "IN" + }, + "TESTADCOUT15": { + "direction": "OUT" + }, + "MUXADDR3": { + "direction": "OUT" + }, + "DADDR4": { + "direction": "IN" + }, + "OT": { + "direction": "OUT" + }, + "TESTADCOUT4": { + "direction": "OUT" + }, + "ALM3": { + "direction": "OUT" + }, + "DADDR0": { + "direction": "IN" + }, + "VAUXN3": { + "direction": "IN" + }, + "TESTDB7": { + "direction": "OUT" + }, + "MUXADDR1": { + "direction": "OUT" + }, + "ALM4": { + "direction": "OUT" + }, + "TESTSCANCLK2": { + "direction": "IN" + }, + "VAUXP6": { + "direction": "IN" + }, + "TESTADCOUT18": { + "direction": "OUT" + }, + "VAUXN11": { + "direction": "IN" + }, + "TESTSCANMODE1": { + "direction": "IN" + }, + "VAUXN1": { + "direction": "IN" + }, + "VAUXN15": { + "direction": "IN" + }, + "TESTDB13": { + "direction": "OUT" + }, + "TESTSE2": { + "direction": "IN" + }, + "DO6": { + "direction": "OUT" + }, + "CHANNEL2": { + "direction": "OUT" + }, + "TESTSE4": { + "direction": "IN" + }, + "TESTADCIN7": { + "direction": "IN" + }, + "TESTDB3": { + "direction": "OUT" + }, + "TESTSO1": { + "direction": "OUT" + }, + "TESTUPDATE": { + "direction": "IN" + }, + "TESTADCIN18": { + "direction": "IN" + }, + "DADDR6": { + "direction": "IN" + }, + "TESTADCIN10": { + "direction": "IN" + }, + "VAUXP14": { + "direction": "IN" + }, + "VAUXP11": { + "direction": "IN" + }, + "DI10": { + "direction": "IN" + }, + "TESTADCIN6": { + "direction": "IN" + }, + "DO7": { + "direction": "OUT" + }, + "TESTADCIN216": { + "direction": "IN" + }, + "TESTSI2": { + "direction": "IN" + }, + "ALM0": { + "direction": "OUT" + }, + "TESTADCIN217": { + "direction": "IN" + }, + "VAUXP15": { + "direction": "IN" + }, + "TESTDB9": { + "direction": "OUT" + }, + "ALM5": { + "direction": "OUT" + }, + "TESTSCANRESET": { + "direction": "IN" + }, + "DWE": { + "direction": "IN" + }, + "TESTCAPTURE": { + "direction": "IN" + }, + "TESTADCIN22": { + "direction": "IN" + }, + "TESTADCIN17": { + "direction": "IN" + }, + "TESTENJTAG": { + "direction": "IN" + }, + "TESTDB0": { + "direction": "OUT" + }, + "EOS": { + "direction": "OUT" + }, + "TESTADCIN1": { + "direction": "IN" + }, + "TESTADCOUT9": { + "direction": "OUT" + }, + "TESTADCIN3": { + "direction": "IN" + }, + "TESTSO4": { + "direction": "OUT" + }, + "TESTSCANMODE3": { + "direction": "IN" + }, + "VAUXN6": { + "direction": "IN" + }, + "DADDR5": { + "direction": "IN" + }, + "DO2": { + "direction": "OUT" + }, + "JTAGMODIFIED": { + "direction": "OUT" + }, + "TESTTDI": { + "direction": "IN" + }, + "TESTADCIN19": { + "direction": "IN" + }, + "VAUXP7": { + "direction": "IN" + }, + "TESTADCOUT8": { + "direction": "OUT" + }, + "TESTADCCLK0": { + "direction": "IN" + }, + "VAUXN10": { + "direction": "IN" + }, + "CHANNEL3": { + "direction": "OUT" + }, + "DO13": { + "direction": "OUT" + }, + "TESTDB6": { + "direction": "OUT" + }, + "TESTADCIN14": { + "direction": "IN" + }, + "TESTDB11": { + "direction": "OUT" + }, + "VAUXP0": { + "direction": "IN" + }, + "DO9": { + "direction": "OUT" + }, + "TESTRST": { + "direction": "IN" + }, + "TESTSCANMODE0": { + "direction": "IN" + }, + "TESTADCOUT13": { + "direction": "OUT" + }, + "VP": { + "direction": "IN" + }, + "TESTADCIN8": { + "direction": "IN" + }, + "VAUXP4": { + "direction": "IN" + }, + "VAUXP13": { + "direction": "IN" + }, + "TESTSI1": { + "direction": "IN" + }, + "TESTADCOUT14": { + "direction": "OUT" + }, + "TESTADCIN24": { + "direction": "IN" + }, + "TESTSEL": { + "direction": "IN" + }, + "VAUXP12": { + "direction": "IN" + }, + "DO5": { + "direction": "OUT" + }, + "DO15": { + "direction": "OUT" + }, + "TESTSCANCLK0": { + "direction": "IN" + }, + "TESTADCOUT0": { + "direction": "OUT" + }, + "DRDY": { + "direction": "OUT" + }, + "TESTDB1": { + "direction": "OUT" + }, + "TESTADCIN25": { + "direction": "IN" + }, + "ALM2": { + "direction": "OUT" + }, + "VAUXP8": { "direction": "IN" }, "TESTDB2": { "direction": "OUT" }, - "TESTADCOUT18": { + "TESTADCOUT6": { "direction": "OUT" }, - "TESTUPDATE": { + "TESTADCIN15": { "direction": "IN" - } - }, - "type": "XADC", - "site_pips": { - "DCLKINV:DCLK_B": { - "from_pin": "DCLK_B", - "to_pin": "OUT" }, - "DCLKINV:DCLK": { - "from_pin": "DCLK", - "to_pin": "OUT" + "VN": { + "direction": "IN" }, - "CONVSTCLKINV:CONVSTCLK": { - "from_pin": "CONVSTCLK", - "to_pin": "OUT" + "DI3": { + "direction": "IN" }, - "CONVSTCLKINV:CONVSTCLK_B": { - "from_pin": "CONVSTCLK_B", - "to_pin": "OUT" + "JTAGLOCKED": { + "direction": "OUT" + }, + "TESTDB5": { + "direction": "OUT" + }, + "DADDR3": { + "direction": "IN" + }, + "TESTADCIN28": { + "direction": "IN" + }, + "CONVST": { + "direction": "IN" + }, + "TESTADCIN215": { + "direction": "IN" + }, + "TESTADCIN213": { + "direction": "IN" + }, + "TESTADCIN4": { + "direction": "IN" + }, + "DADDR1": { + "direction": "IN" + }, + "TESTADCIN13": { + "direction": "IN" + }, + "TESTADCIN0": { + "direction": "IN" + }, + "TESTSI3": { + "direction": "IN" + }, + "MUXADDR0": { + "direction": "OUT" + }, + "VAUXP10": { + "direction": "IN" + }, + "TESTADCIN212": { + "direction": "IN" + }, + "TESTADCIN21": { + "direction": "IN" + }, + "CONVSTCLK": { + "direction": "IN" + }, + "VAUXP5": { + "direction": "IN" + }, + "DO12": { + "direction": "OUT" + }, + "DADDR2": { + "direction": "IN" + }, + "VAUXN12": { + "direction": "IN" + }, + "TESTADCIN218": { + "direction": "IN" + }, + "DO10": { + "direction": "OUT" + }, + "TESTADCCLK2": { + "direction": "IN" + }, + "TESTDRCK": { + "direction": "IN" + }, + "TESTADCCLK3": { + "direction": "IN" + }, + "TESTDB8": { + "direction": "OUT" + }, + "TESTSI4": { + "direction": "IN" + }, + "TESTSCANCLK1": { + "direction": "IN" + }, + "ALM7": { + "direction": "OUT" + }, + "TESTTDO": { + "direction": "OUT" + }, + "DO0": { + "direction": "OUT" + }, + "DI1": { + "direction": "IN" + }, + "TESTADCOUT1": { + "direction": "OUT" + }, + "DI12": { + "direction": "IN" + }, + "TESTADCIN5": { + "direction": "IN" + }, + "EOC": { + "direction": "OUT" + }, + "TESTADCIN9": { + "direction": "IN" + }, + "DI14": { + "direction": "IN" + }, + "TESTDB10": { + "direction": "OUT" + }, + "MUXADDR2": { + "direction": "OUT" + }, + "TESTADCIN29": { + "direction": "IN" + }, + "TESTADCOUT5": { + "direction": "OUT" + }, + "TESTADCIN11": { + "direction": "IN" + }, + "VAUXP3": { + "direction": "IN" + }, + "TESTADCIN23": { + "direction": "IN" + }, + "RESET": { + "direction": "IN" + }, + "TESTSHIFT": { + "direction": "IN" + }, + "VAUXN8": { + "direction": "IN" + }, + "TESTADCOUT10": { + "direction": "OUT" + }, + "TESTSCANMODE2": { + "direction": "IN" + }, + "TESTSCANCLK3": { + "direction": "IN" + }, + "DI13": { + "direction": "IN" + }, + "TESTADCIN219": { + "direction": "IN" + }, + "MUXADDR4": { + "direction": "OUT" + }, + "VAUXN9": { + "direction": "IN" + }, + "DI5": { + "direction": "IN" + }, + "BUSY": { + "direction": "OUT" + }, + "TESTSCANCLK4": { + "direction": "IN" + }, + "DI11": { + "direction": "IN" + }, + "TESTSO0": { + "direction": "OUT" + }, + "VAUXN7": { + "direction": "IN" + }, + "CHANNEL1": { + "direction": "OUT" + }, + "TESTSO2": { + "direction": "OUT" + }, + "TESTADCIN211": { + "direction": "IN" + }, + "DI7": { + "direction": "IN" + }, + "DO4": { + "direction": "OUT" + }, + "DCLK": { + "direction": "IN" + }, + "DO3": { + "direction": "OUT" + }, + "DI9": { + "direction": "IN" + }, + "TESTSI0": { + "direction": "IN" + }, + "TESTDB4": { + "direction": "OUT" + }, + "TESTADCOUT19": { + "direction": "OUT" + }, + "DO8": { + "direction": "OUT" + }, + "TESTSO3": { + "direction": "OUT" + }, + "VAUXN4": { + "direction": "IN" + }, + "CHANNEL4": { + "direction": "OUT" + }, + "TESTADCIN12": { + "direction": "IN" + }, + "TESTDB15": { + "direction": "OUT" + }, + "TESTADCIN2": { + "direction": "IN" } } } \ No newline at end of file diff --git a/artix7/tile_type_BRAM_INT_INTERFACE_L.json b/artix7/tile_type_BRAM_INT_INTERFACE_L.json index 71bb670..84b63ea 100644 --- a/artix7/tile_type_BRAM_INT_INTERFACE_L.json +++ b/artix7/tile_type_BRAM_INT_INTERFACE_L.json @@ -1,476 +1,476 @@ { - "wires": [ - "INT_INTERFACE_BRAM_IMUX33", - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "INT_INTERFACE_BYP5", - "INT_INTERFACE_BRAM_UTURN_IMUX24", - "INT_INTERFACE_BRAM_IMUX41", - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "INT_INTERFACE_BRAM_IMUX4", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_BRAM_IMUX13", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_BRAM_IMUX38", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "INT_INTERFACE_BRAM_UTURN_IMUX1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_BRAM_UTURN_IMUX29", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_BRAM_IMUX7", - "INT_INTERFACE_LH10", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "INT_INTERFACE_BRAM_IMUX11", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_BRAM_IMUX21", - "INT_INTERFACE_BRAM_UTURN_IMUX34", - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_LOGIC_OUTS_L19", - "INT_INTERFACE_BRAM_UTURN_IMUX35", - "INT_INTERFACE_LH1", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_BRAM_IMUX6", - "INT_INTERFACE_BRAM_UTURN_IMUX25", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_BRAM_UTURN_IMUX23", - "INT_INTERFACE_CLK0", - "INT_INTERFACE_LOGIC_OUTS_L22", - "INT_INTERFACE_BRAM_UTURN_IMUX44", - "INT_INTERFACE_BRAM_IMUX10", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_LOGIC_OUTS_L4", - "INT_INTERFACE_BRAM_UTURN_IMUX30", - "INT_INTERFACE_LH6", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_BRAM_UTURN_IMUX41", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_BRAM_UTURN_IMUX4", - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "INT_INTERFACE_BRAM_IMUX8", - "INT_INTERFACE_BRAM_UTURN_IMUX21", - "INT_INTERFACE_BRAM_IMUX14", - "INT_INTERFACE_LOGIC_OUTS_L13", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_BLOCK_OUTS_L_B2", - "INT_INTERFACE_BRAM_UTURN_IMUX6", - "INT_INTERFACE_BRAM_IMUX24", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_BRAM_IMUX22", - "INT_INTERFACE_LOGIC_OUTS_L1", - "INT_INTERFACE_BRAM_UTURN_IMUX20", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_LOGIC_OUTS_L5", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_LOGIC_OUTS_L3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_LOGIC_OUTS_L7", - "INT_INTERFACE_BRAM_IMUX19", - "INT_INTERFACE_LOGIC_OUTS_L0", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "INT_INTERFACE_BRAM_IMUX17", - "INT_INTERFACE_EE2A0", - "L_INT_INTER_DQS_IOTOPHASER", - "INT_INTERFACE_BRAM_UTURN_IMUX7", - "INT_INTERFACE_BRAM_UTURN_IMUX33", - "INT_INTERFACE_BRAM_IMUX26", - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "INT_INTERFACE_BRAM_IMUX44", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_BRAM_IMUX39", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_BRAM_UTURN_IMUX31", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_LOGIC_OUTS_L21", - "INT_INTERFACE_BRAM_IMUX12", - "INT_INTERFACE_BRAM_UTURN_IMUX32", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_BRAM_IMUX28", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_BRAM_IMUX27", - "INT_INTERFACE_LOGIC_OUTS_L18", - "INT_INTERFACE_BRAM_UTURN_IMUX22", - "INT_INTERFACE_LOGIC_OUTS_L14", - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "INT_INTERFACE_LOGIC_OUTS_L11", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_BRAM_UTURN_IMUX27", - "INT_INTERFACE_BRAM_UTURN_IMUX5", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_BYP1", - "INT_INTERFACE_BRAM_IMUX23", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_LH8", - "INT_INTERFACE_BRAM_UTURN_IMUX46", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_LOGIC_OUTS_L23", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_LOGIC_OUTS_L_B14", - "INT_INTERFACE_BRAM_UTURN_IMUX16", - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "INT_INTERFACE_BRAM_IMUX46", - "INT_INTERFACE_BRAM_IMUX16", - "INT_INTERFACE_LOGIC_OUTS_L8", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_BRAM_UTURN_IMUX15", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_BRAM_UTURN_IMUX37", - "INT_INTERFACE_BRAM_IMUX42", - "INT_INTERFACE_LH7", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_LOGIC_OUTS_L20", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_BRAM_UTURN_IMUX3", - "INT_INTERFACE_BRAM_IMUX18", - "INT_INTERFACE_LH5", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_BRAM_UTURN_IMUX28", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_BRAM_IMUX35", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_BRAM_IMUX20", - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "INT_INTERFACE_LOGIC_OUTS_L2", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_BYP2", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_BRAM_IMUX30", - "INT_INTERFACE_BRAM_UTURN_IMUX38", - "INT_INTERFACE_BRAM_IMUX32", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_BRAM_IMUX5", - "INT_INTERFACE_BRAM_UTURN_IMUX36", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_BRAM_IMUX36", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_BRAM_IMUX9", - "INT_INTERFACE_LOGIC_OUTS_L10", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_LH2", - "INT_INTERFACE_BRAM_UTURN_IMUX18", - "INT_INTERFACE_BRAM_UTURN_IMUX11", - "INT_INTERFACE_BRAM_UTURN_IMUX19", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_BRAM_UTURN_IMUX12", - "INT_INTERFACE_BRAM_UTURN_IMUX39", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_BRAM_IMUX2", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_BRAM_IMUX45", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_BRAM_UTURN_IMUX42", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_BRAM_IMUX40", - "INT_INTERFACE_LH12", - "INT_INTERFACE_BRAM_IMUX0", - "INT_INTERFACE_LH9", - "INT_INTERFACE_BRAM_UTURN_IMUX47", - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "INT_INTERFACE_LOGIC_OUTS_L6", - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_BLOCK_OUTS_L_B0", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_BRAM_UTURN_IMUX43", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_BRAM_IMUX1", - "INT_INTERFACE_BRAM_UTURN_IMUX40", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_LOGIC_OUTS_L12", - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "INT_INTERFACE_BRAM_IMUX31", - "INT_INTERFACE_BRAM_IMUX15", - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW4END3", - "INT_INTERFACE_LH11", - "INT_INTERFACE_BRAM_UTURN_IMUX17", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_BRAM_IMUX3", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_BRAM_IMUX34", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_LOGIC_OUTS_L15", - "INT_INTERFACE_BRAM_UTURN_IMUX13", - "INT_INTERFACE_BLOCK_OUTS_L_B1", - "INT_INTERFACE_BRAM_IMUX47", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_BRAM_UTURN_IMUX0", - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_BRAM_UTURN_IMUX45", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_BRAM_UTURN_IMUX9", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_LOGIC_OUTS_L16", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_BRAM_IMUX29", - "INT_INTERFACE_BRAM_IMUX25", - "INT_INTERFACE_BRAM_UTURN_IMUX14", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_BRAM_UTURN_IMUX26", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_BLOCK_OUTS_L_B3", - "INT_INTERFACE_ER1BEG1", - "INT_INTERFACE_BRAM_UTURN_IMUX8", - "INT_INTERFACE_BRAM_IMUX43", - "INT_INTERFACE_LOGIC_OUTS_L17", - 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"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19" }, "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11", - "is_directional": "1", "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10" + }, + "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8" } }, - "tile_type": "BRAM_INT_INTERFACE_L" + "wires": [ + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "INT_INTERFACE_LOGIC_OUTS_L13", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_LOGIC_OUTS_L19", + "INT_INTERFACE_BRAM_IMUX9", + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_LOGIC_OUTS_L1", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_BRAM_UTURN_IMUX25", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_BRAM_IMUX28", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LH8", + "INT_INTERFACE_BRAM_UTURN_IMUX41", + "INT_INTERFACE_BRAM_IMUX22", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_BLOCK_OUTS_L_B0", + "INT_INTERFACE_BRAM_IMUX16", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "INT_INTERFACE_BRAM_IMUX43", + "INT_INTERFACE_BRAM_IMUX45", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_BRAM_IMUX7", + "INT_INTERFACE_BRAM_UTURN_IMUX14", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_BRAM_IMUX36", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_BRAM_UTURN_IMUX28", + "INT_INTERFACE_LOGIC_OUTS_L8", + "INT_INTERFACE_BRAM_UTURN_IMUX42", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_BRAM_IMUX19", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "INT_INTERFACE_BRAM_IMUX3", + "INT_INTERFACE_LOGIC_OUTS_L5", + "INT_INTERFACE_BRAM_IMUX14", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "INT_INTERFACE_BRAM_IMUX40", + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_BRAM_UTURN_IMUX29", + "INT_INTERFACE_BRAM_UTURN_IMUX8", + "INT_INTERFACE_BRAM_UTURN_IMUX22", + "INT_INTERFACE_BRAM_IMUX12", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_BRAM_UTURN_IMUX7", + "INT_INTERFACE_BLOCK_OUTS_L_B2", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_BRAM_UTURN_IMUX26", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_BRAM_UTURN_IMUX39", + "INT_INTERFACE_BRAM_UTURN_IMUX44", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_BRAM_UTURN_IMUX46", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_BRAM_IMUX18", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_LOGIC_OUTS_L22", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_LOGIC_OUTS_L3", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_BRAM_IMUX5", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_BRAM_UTURN_IMUX19", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_BRAM_IMUX32", + "INT_INTERFACE_BLOCK_OUTS_L_B1", + "INT_INTERFACE_BRAM_IMUX15", + "INT_INTERFACE_LOGIC_OUTS_L23", + "INT_INTERFACE_LOGIC_OUTS_L11", + "INT_INTERFACE_BRAM_IMUX37", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_BRAM_IMUX27", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_LH6", + "INT_INTERFACE_BRAM_UTURN_IMUX38", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_BRAM_UTURN_IMUX3", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_BRAM_IMUX8", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_BRAM_UTURN_IMUX31", + "INT_INTERFACE_BRAM_UTURN_IMUX32", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_BRAM_UTURN_IMUX33", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LH1", + "INT_INTERFACE_BRAM_UTURN_IMUX37", + "INT_INTERFACE_BRAM_IMUX17", + "INT_INTERFACE_BRAM_IMUX13", + "INT_INTERFACE_LH5", + "INT_INTERFACE_BRAM_UTURN_IMUX4", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LH4", + "INT_INTERFACE_LH12", + "INT_INTERFACE_LOGIC_OUTS_L18", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_LOGIC_OUTS_L16", + "INT_INTERFACE_BRAM_IMUX2", + "INT_INTERFACE_BRAM_UTURN_IMUX36", + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "INT_INTERFACE_BRAM_UTURN_IMUX2", + "INT_INTERFACE_LOGIC_OUTS_L2", + "INT_INTERFACE_BRAM_UTURN_IMUX0", + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "INT_INTERFACE_EL1BEG3", + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "INT_INTERFACE_BLOCK_OUTS_L_B3", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_BRAM_IMUX39", + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "INT_INTERFACE_BRAM_IMUX31", + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_BRAM_IMUX29", + "INT_INTERFACE_BRAM_UTURN_IMUX45", + "INT_INTERFACE_BRAM_IMUX21", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_BRAM_IMUX4", + "INT_INTERFACE_BRAM_IMUX0", + "INT_INTERFACE_BRAM_UTURN_IMUX6", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "INT_INTERFACE_BRAM_UTURN_IMUX18", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_BRAM_UTURN_IMUX1", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_BRAM_UTURN_IMUX35", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_LOGIC_OUTS_L10", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_BRAM_IMUX6", + "INT_INTERFACE_BRAM_IMUX33", + "INT_INTERFACE_LH7", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_BRAM_IMUX44", + "INT_INTERFACE_LOGIC_OUTS_L9", + "INT_INTERFACE_BRAM_UTURN_IMUX16", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_BRAM_IMUX11", + "INT_INTERFACE_BRAM_IMUX41", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_BRAM_UTURN_IMUX13", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_BRAM_UTURN_IMUX23", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_BRAM_UTURN_IMUX11", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_BRAM_IMUX42", + "INT_INTERFACE_BRAM_IMUX35", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_BRAM_IMUX10", + "INT_INTERFACE_LOGIC_OUTS_L15", + "INT_INTERFACE_BRAM_UTURN_IMUX43", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_BRAM_UTURN_IMUX40", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_LH2", + "INT_INTERFACE_LOGIC_OUTS_L21", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_BRAM_UTURN_IMUX47", + "INT_INTERFACE_BRAM_IMUX1", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_LOGIC_OUTS_L20", + "INT_INTERFACE_LOGIC_OUTS_L14", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_BRAM_UTURN_IMUX15", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_BRAM_UTURN_IMUX34", + "INT_INTERFACE_BRAM_UTURN_IMUX21", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_BRAM_UTURN_IMUX17", + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_BRAM_UTURN_IMUX20", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_LH9", + "INT_INTERFACE_BRAM_UTURN_IMUX30", + "INT_INTERFACE_LOGIC_OUTS_L17", + "INT_INTERFACE_BRAM_UTURN_IMUX10", + "INT_INTERFACE_BRAM_IMUX46", + "INT_INTERFACE_LOGIC_OUTS_L0", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_BRAM_IMUX25", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_LOGIC_OUTS_L12", + "INT_INTERFACE_BRAM_IMUX20", + "INT_INTERFACE_BRAM_IMUX38", + "INT_INTERFACE_BRAM_UTURN_IMUX24", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_LOGIC_OUTS_L6", + "INT_INTERFACE_BRAM_IMUX34", + "INT_INTERFACE_BRAM_UTURN_IMUX5", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_LH3", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_BRAM_UTURN_IMUX27", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_BRAM_IMUX23", + "INT_INTERFACE_BRAM_IMUX47", + "INT_INTERFACE_BRAM_IMUX26", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_BRAM_IMUX24", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_BRAM_UTURN_IMUX9", + "INT_INTERFACE_BRAM_UTURN_IMUX12", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_LOGIC_OUTS_L4", + "INT_INTERFACE_BRAM_IMUX30", + "INT_INTERFACE_LOGIC_OUTS_L7", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + "tile_type": "BRAM_INT_INTERFACE_L", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRAM_INT_INTERFACE_R.json b/artix7/tile_type_BRAM_INT_INTERFACE_R.json index 82d3587..722afdc 100644 --- a/artix7/tile_type_BRAM_INT_INTERFACE_R.json +++ b/artix7/tile_type_BRAM_INT_INTERFACE_R.json @@ -1,476 +1,476 @@ { - "wires": [ - "INT_INTERFACE_BRAM_IMUX33", - "INT_INTERFACE_BYP5", - "INT_INTERFACE_BRAM_IMUX41", - "INT_INTERFACE_BRAM_IMUX4", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_BRAM_IMUX13", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_BRAM_IMUX38", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_BRAM_UTURN_R_IMUX5", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_LOGIC_OUTS17", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_BRAM_IMUX7", - "INT_INTERFACE_LOGIC_OUTS16", - "INT_INTERFACE_LH10", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_BRAM_UTURN_R_IMUX35", - "INT_INTERFACE_BRAM_UTURN_R_IMUX10", - "INT_INTERFACE_BRAM_IMUX11", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_BRAM_IMUX21", - "INT_INTERFACE_BRAM_UTURN_R_IMUX0", - "INT_INTERFACE_BLOCK_OUTS_B0", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_BRAM_UTURN_R_IMUX8", - "INT_INTERFACE_LH1", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_BRAM_IMUX6", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_BRAM_UTURN_R_IMUX39", - "INT_INTERFACE_BRAM_UTURN_R_IMUX40", - "INT_INTERFACE_BRAM_UTURN_R_IMUX36", - "INT_INTERFACE_LOGIC_OUTS10", - "INT_INTERFACE_CLK0", - "INT_INTERFACE_BRAM_IMUX10", - "INT_INTERFACE_LOGIC_OUTS7", - "INT_INTERFACE_BRAM_UTURN_R_IMUX3", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_LOGIC_OUTS_B1", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_LOGIC_OUTS5", - "INT_INTERFACE_LH6", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_BLOCK_OUTS_B2", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_BRAM_IMUX8", - "INT_INTERFACE_BRAM_UTURN_R_IMUX38", - "INT_INTERFACE_LOGIC_OUTS_B9", - "INT_INTERFACE_BRAM_IMUX14", - "INT_INTERFACE_BRAM_UTURN_R_IMUX1", - "INT_INTERFACE_BRAM_UTURN_R_IMUX7", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_LOGIC_OUTS_B18", - "INT_INTERFACE_BRAM_UTURN_R_IMUX21", - "INT_INTERFACE_BRAM_IMUX24", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_BRAM_UTURN_R_IMUX11", - "INT_INTERFACE_LOGIC_OUTS_B21", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS21", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_BRAM_IMUX22", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_BRAM_UTURN_R_IMUX9", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_BRAM_IMUX19", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_BRAM_UTURN_R_IMUX2", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_BRAM_IMUX17", - "INT_INTERFACE_EE2A0", - "L_INT_INTER_DQS_IOTOPHASER", - "INT_INTERFACE_LOGIC_OUTS1", - "INT_INTERFACE_BRAM_IMUX26", - "INT_INTERFACE_BRAM_IMUX44", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_BRAM_IMUX39", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_LOGIC_OUTS3", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_BRAM_UTURN_R_IMUX24", - "INT_INTERFACE_BRAM_UTURN_R_IMUX34", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_BRAM_IMUX12", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_LOGIC_OUTS_B23", - "INT_INTERFACE_BRAM_IMUX28", - "INT_INTERFACE_BRAM_UTURN_R_IMUX31", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_BRAM_IMUX27", - "INT_INTERFACE_LOGIC_OUTS20", - "INT_INTERFACE_BRAM_UTURN_R_IMUX16", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_BYP1", - "INT_INTERFACE_BRAM_UTURN_R_IMUX28", - "INT_INTERFACE_BRAM_IMUX23", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_LOGIC_OUTS4", - "INT_INTERFACE_LH8", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_LOGIC_OUTS12", - "INT_INTERFACE_BRAM_UTURN_R_IMUX41", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_BRAM_UTURN_R_IMUX15", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_LOGIC_OUTS_B4", - "INT_INTERFACE_BRAM_IMUX46", - "INT_INTERFACE_BRAM_IMUX16", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS_B5", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_BRAM_UTURN_R_IMUX6", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_BRAM_IMUX42", - "INT_INTERFACE_LH7", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_BRAM_UTURN_R_IMUX20", - "INT_INTERFACE_BRAM_UTURN_R_IMUX29", - "INT_INTERFACE_LOGIC_OUTS11", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_BRAM_UTURN_R_IMUX44", - "INT_INTERFACE_BRAM_IMUX18", - "INT_INTERFACE_LH5", - "INT_INTERFACE_BLOCK_OUTS_B3", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_BRAM_UTURN_R_IMUX25", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_BRAM_UTURN_R_IMUX19", - "INT_INTERFACE_BRAM_UTURN_R_IMUX32", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_BRAM_IMUX35", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_BRAM_UTURN_R_IMUX17", - "INT_INTERFACE_BRAM_IMUX20", - "INT_INTERFACE_LOGIC_OUTS18", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_BYP2", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_LOGIC_OUTS_B12", - "INT_INTERFACE_BRAM_IMUX30", - "INT_INTERFACE_LOGIC_OUTS22", - "INT_INTERFACE_BRAM_UTURN_R_IMUX26", - "INT_INTERFACE_BRAM_IMUX32", - "INT_INTERFACE_BRAM_UTURN_R_IMUX42", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_BRAM_IMUX5", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_BRAM_IMUX36", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_BRAM_IMUX9", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_LOGIC_OUTS_B6", - "INT_INTERFACE_BRAM_UTURN_R_IMUX43", - "INT_INTERFACE_LOGIC_OUTS0", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_BRAM_UTURN_R_IMUX46", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_LH2", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_LOGIC_OUTS13", - "INT_INTERFACE_BRAM_UTURN_R_IMUX30", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_LOGIC_OUTS6", - "INT_INTERFACE_BRAM_UTURN_R_IMUX18", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_BRAM_IMUX2", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_BRAM_IMUX45", - "INT_INTERFACE_BRAM_UTURN_R_IMUX33", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_BRAM_UTURN_R_IMUX47", - "INT_INTERFACE_LOGIC_OUTS9", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_BRAM_UTURN_R_IMUX14", - "INT_INTERFACE_BRAM_IMUX40", - "INT_INTERFACE_BRAM_IMUX0", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH9", - "INT_INTERFACE_BRAM_UTURN_R_IMUX45", - "INT_INTERFACE_BRAM_UTURN_R_IMUX12", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_BRAM_IMUX1", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_BRAM_UTURN_R_IMUX37", - "INT_INTERFACE_BRAM_IMUX31", - "INT_INTERFACE_BRAM_IMUX15", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW4END3", - "INT_INTERFACE_LOGIC_OUTS15", - "INT_INTERFACE_LH11", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_BRAM_UTURN_R_IMUX23", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_BRAM_IMUX3", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_LOGIC_OUTS2", - "INT_INTERFACE_BRAM_IMUX34", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_LOGIC_OUTS23", - "INT_INTERFACE_BRAM_IMUX47", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_LOGIC_OUTS14", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_LOGIC_OUTS_B2", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_LOGIC_OUTS19", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_LOGIC_OUTS_B14", - "INT_INTERFACE_LOGIC_OUTS_B11", - "INT_INTERFACE_BRAM_IMUX29", - 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"is_directional": "1", "src_wire": "INT_INTERFACE_LOGIC_OUTS_B6", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS6" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS12" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS4" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS13" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS19" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS0" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS8" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS1" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS11" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS16" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS9" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS15" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS18" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS2" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS21" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS7" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS10" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS22" + }, + "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS17" } }, - "tile_type": "BRAM_INT_INTERFACE_R" + "wires": [ + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_LOGIC_OUTS_B9", + "INT_INTERFACE_LOGIC_OUTS_B12", + "INT_INTERFACE_BRAM_UTURN_R_IMUX46", + "INT_INTERFACE_BLOCK_OUTS_B3", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX43", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_BRAM_IMUX9", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_LOGIC_OUTS_B10", + "INT_INTERFACE_BRAM_UTURN_R_IMUX7", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_BRAM_UTURN_R_IMUX13", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_BRAM_IMUX28", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LH8", + "INT_INTERFACE_LOGIC_OUTS_B22", + "INT_INTERFACE_BRAM_IMUX22", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX35", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_LOGIC_OUTS4", + "INT_INTERFACE_BRAM_IMUX16", + "INT_INTERFACE_LOGIC_OUTS1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX34", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_LOGIC_OUTS0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX9", + "INT_INTERFACE_LOGIC_OUTS_B11", + "INT_INTERFACE_BRAM_UTURN_R_IMUX25", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS20", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX10", + "INT_INTERFACE_BRAM_IMUX43", + "INT_INTERFACE_BRAM_IMUX45", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_BRAM_IMUX7", + "INT_INTERFACE_BRAM_UTURN_R_IMUX31", + "INT_INTERFACE_LOGIC_OUTS18", + "INT_INTERFACE_LOGIC_OUTS_B20", + "INT_INTERFACE_BRAM_UTURN_R_IMUX6", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LOGIC_OUTS3", + "INT_INTERFACE_BRAM_UTURN_R_IMUX28", + "INT_INTERFACE_LH11", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_LOGIC_OUTS_B14", + "INT_INTERFACE_BRAM_UTURN_R_IMUX27", + "INT_INTERFACE_BLOCK_OUTS_B2", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_BRAM_IMUX36", + "INT_INTERFACE_BRAM_UTURN_R_IMUX3", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_LOGIC_OUTS_B1", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_BRAM_UTURN_R_IMUX30", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX26", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_LOGIC_OUTS2", + "INT_INTERFACE_BRAM_IMUX19", + "INT_INTERFACE_BRAM_UTURN_R_IMUX47", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_BRAM_IMUX3", + "INT_INTERFACE_BRAM_IMUX14", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_LOGIC_OUTS_B7", + "INT_INTERFACE_BRAM_IMUX40", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_BRAM_IMUX12", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_LOGIC_OUTS16", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX19", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_LOGIC_OUTS8", + "INT_INTERFACE_BRAM_UTURN_R_IMUX0", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_LOGIC_OUTS9", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "INT_INTERFACE_BRAM_IMUX18", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_BRAM_IMUX5", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_BRAM_IMUX32", + "INT_INTERFACE_BRAM_IMUX15", + "INT_INTERFACE_BRAM_UTURN_R_IMUX42", + "INT_INTERFACE_BRAM_IMUX37", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_BRAM_UTURN_R_IMUX41", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_BRAM_IMUX27", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_LH6", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_LOGIC_OUTS14", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_LOGIC_OUTS11", + "INT_INTERFACE_BRAM_IMUX8", + "INT_INTERFACE_LOGIC_OUTS_B18", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_BRAM_UTURN_R_IMUX36", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_LOGIC_OUTS10", + "INT_INTERFACE_BRAM_UTURN_R_IMUX8", + "INT_INTERFACE_BRAM_UTURN_R_IMUX32", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_BRAM_UTURN_R_IMUX20", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LH1", + "INT_INTERFACE_BRAM_IMUX17", + "INT_INTERFACE_BRAM_IMUX13", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_LH5", + "INT_INTERFACE_LOGIC_OUTS_B3", + "INT_INTERFACE_LH4", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LH12", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_LOGIC_OUTS19", + "INT_INTERFACE_BRAM_IMUX2", + "INT_INTERFACE_LOGIC_OUTS_B5", + "INT_INTERFACE_BRAM_UTURN_R_IMUX12", + "INT_INTERFACE_BRAM_UTURN_R_IMUX23", + "INT_INTERFACE_BRAM_UTURN_R_IMUX38", + "INT_INTERFACE_EL1BEG3", + "INT_INTERFACE_LOGIC_OUTS23", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS_B6", + "INT_INTERFACE_LOGIC_OUTS_B2", + "INT_INTERFACE_LOGIC_OUTS_B19", + "INT_INTERFACE_BRAM_UTURN_R_IMUX15", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_BRAM_IMUX39", + "INT_INTERFACE_BRAM_IMUX31", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_BRAM_IMUX29", + "INT_INTERFACE_BRAM_UTURN_R_IMUX1", + "INT_INTERFACE_BRAM_IMUX21", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_BRAM_IMUX4", + "INT_INTERFACE_BRAM_UTURN_R_IMUX16", + "INT_INTERFACE_BRAM_UTURN_R_IMUX44", + "INT_INTERFACE_BRAM_IMUX0", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_BRAM_UTURN_R_IMUX24", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_LOGIC_OUTS_B13", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX40", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_BRAM_IMUX6", + "INT_INTERFACE_BRAM_IMUX33", + "INT_INTERFACE_BRAM_UTURN_R_IMUX33", + "INT_INTERFACE_LH7", + "INT_INTERFACE_BRAM_UTURN_R_IMUX45", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_BRAM_IMUX44", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_BRAM_IMUX11", + "INT_INTERFACE_BRAM_IMUX41", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_LOGIC_OUTS21", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_BRAM_UTURN_R_IMUX18", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_LOGIC_OUTS12", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_BRAM_IMUX42", + "INT_INTERFACE_BRAM_IMUX35", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_BRAM_IMUX10", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_BRAM_UTURN_R_IMUX39", + "INT_INTERFACE_BRAM_UTURN_R_IMUX21", + "INT_INTERFACE_LH2", + "INT_INTERFACE_BRAM_UTURN_R_IMUX4", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_LOGIC_OUTS_B4", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_BRAM_IMUX1", + "INT_INTERFACE_LOGIC_OUTS_B17", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_LOGIC_OUTS7", + "INT_INTERFACE_BRAM_UTURN_R_IMUX11", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX29", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX2", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS15", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_LH9", + "INT_INTERFACE_LOGIC_OUTS6", + "INT_INTERFACE_BRAM_UTURN_R_IMUX22", + "INT_INTERFACE_BRAM_IMUX46", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_BRAM_IMUX25", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_BRAM_IMUX20", + "INT_INTERFACE_BRAM_UTURN_R_IMUX17", + "INT_INTERFACE_BRAM_IMUX38", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_LOGIC_OUTS_B16", + "INT_INTERFACE_BRAM_UTURN_R_IMUX5", + "INT_INTERFACE_BRAM_IMUX34", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_LH3", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_LOGIC_OUTS22", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_BRAM_UTURN_R_IMUX14", + "INT_INTERFACE_BLOCK_OUTS_B0", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_BRAM_IMUX23", + "INT_INTERFACE_BRAM_IMUX47", + "INT_INTERFACE_BRAM_IMUX26", + "INT_INTERFACE_BLOCK_OUTS_B1", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_BRAM_IMUX24", + "INT_INTERFACE_BRAM_UTURN_R_IMUX37", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_B15", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_BRAM_IMUX30", + "INT_INTERFACE_LOGIC_OUTS13" + ], + "tile_type": "BRAM_INT_INTERFACE_R", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRAM_L.json b/artix7/tile_type_BRAM_L.json index ab82585..2e0bf8f 100644 --- a/artix7/tile_type_BRAM_L.json +++ b/artix7/tile_type_BRAM_L.json @@ -1,9834 +1,9834 @@ { - "wires": [ - "BRAM_FIFO18_DOBDO0", - "BRAM_FIFO18_DIADI15", - "BRAM_FIFO36_TSTBRAMRST", - "BRAM_LOGIC_OUTS_B5_4", - "BRAM_ADDRBWRADDRL3", - "BRAM_IMUX35_4", - "BRAM_FIFO36_ADDRBWRADDRL9", - "BRAM_UTURN_ADDRBWRADDRU10", - "BRAM_FIFO36_DOBDOU8", - "BRAM_ADDRARDADDRU12", - "BRAM_SE4C2_0", - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "BRAM_IMUX41_4", - "BRAM_FIFO36_DOADOU8", - "BRAM_IMUX29_UTURN_4", - "BRAM_IMUX4_0", - "BRAM_FIFO18_RSTREGARSTREG", - "BRAM_FIFO18_DIBDI10", - "BRAM_IMUX34_UTURN_2", - "BRAM_LH4_3", - "BRAM_FIFO36_WRCOUNT12", - "BRAM_EE2BEG3_0", - "BRAM_RAMB18_WRERR", - "BRAM_FIFO18_DIADI9", - "BRAM_FIFO36_ADDRBWRADDRU14", - "BRAM_EE4BEG0_4", - "BRAM_CASCINBOT_ADDRARDADDRU8", - "BRAM_WW4C0_1", - "BRAM_EE2A2_2", - "BRAM_EE4C2_1", - "BRAM_RAMB18_DOADO12", - "BRAM_CLK1_1", - "BRAM_FIFO18_DOADO10", - "BRAM_IMUX_ADDRARDADDRU5", - "BRAM_FIFO36_RDCOUNT5", - "BRAM_FIFO18_DOADO8", - "BRAM_RAMB18_REGCEAREGCE", - "BRAM_LOGIC_OUTS_B8_0", - "BRAM_WW4END1_2", - "BRAM_LH9_0", - "BRAM_WR1END0_2", - "BRAM_WR1END1_2", - "BRAM_SW2A2_3", - "BRAM_ADDRBWRADDRL12", - "BRAM_UTURN_ADDRBWRADDRL4", - "BRAM_FIFO36_DOPADOPL1", - "BRAM_FIFO18_EMPTY", - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "BRAM_IMUX4_UTURN_1", - "BRAM_NW4A2_0", - "BRAM_IMUX_ADDRARDADDRL9", - "BRAM_WW4END2_1", - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "BRAM_IMUX31_0", - "BRAM_IMUX7_UTURN_0", - "BRAM_UTURN_ADDRARDADDRU0", - "BRAM_EE4A0_4", - "BRAM_FIFO36_RDCOUNT6", - "BRAM_WW4A1_2", - "BRAM_IMUX40_1", - "BRAM_FIFO36_WEAU2", - "BRAM_LOGIC_OUTS_B21_4", - "BRAM_ADDRARDADDRU3", - "BRAM_IMUX33_2", - "BRAM_ADDRARDADDRU9", - "BRAM_NE4BEG3_3", - "BRAM_LOGIC_OUTS_B12_3", - "BRAM_FIFO36_DIBDIU10", - "BRAM_EE2A3_2", - "BRAM_FIFO36_TSTIN3", - "BRAM_IMUX37_UTURN_2", - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRAM_WR1END2_4", - "BRAM_FIFO18_DIBDI1", - "BRAM_IMUX42_UTURN_4", - "BRAM_MONITOR_P_2", - "BRAM_IMUX38_3", - "BRAM_SW4END3_4", - "BRAM_RAMB18_DIBDI0", - "BRAM_BYP4_0", - "BRAM_ADDRARDADDRU4", - "BRAM_RAMB18_ADDRBTIEHIGH1", - "BRAM_RAMB18_DIBDI14", - "BRAM_IMUX10_UTURN_3", - "BRAM_ADDRARDADDRL9", - "BRAM_FAN2_3", - "BRAM_WW2END0_4", - "BRAM_FIFO18_ADDRARDADDR10", - "BRAM_UTURN_ADDRBWRADDRL12", - "BRAM_FIFO36_WRCOUNT6", - "BRAM_IMUX29_4", - "BRAM_RAMB18_RSTRAMARSTRAM", - "BRAM_BYP7_2", - "BRAM_FIFO18_DOADO11", - "BRAM_RAMB18_RSTREGB", - "BRAM_UTURN_ADDRBWRADDRL6", - "BRAM_NE4C3_0", - "BRAM_LOGIC_OUTS_B20_2", - "BRAM_FIFO36_WEBWEL5", - "BRAM_FIFO36_DIBDIU5", - "BRAM_SW2A0_4", - "BRAM_UTURN_ADDRARDADDRU7", - "BRAM_FIFO18_WRCOUNT5", - "BRAM_WW2A1_3", - "BRAM_RAMB18_DIADI9", - "BRAM_SE4C1_1", - "BRAM_LOGIC_OUTS_B3_1", - "BRAM_IMUX14_UTURN_3", - "BRAM_CASCOUT_ADDRARDADDRU9", - "BRAM_RAMB18_RDCOUNT7", - "BRAM_FIFO36_ADDRBWRADDRL15", - "BRAM_FIFO36_INJECTDBITERR", - "BRAM_BLOCK_OUTS_L_B1_4", - "BRAM_EE4BEG1_2", - "BRAM_ADDRARDADDRL13", - "BRAM_IMUX23_0", - "BRAM_IMUX30_UTURN_2", - "BRAM_RAMB18_REGCEB", - "BRAM_IMUX22_0", - "BRAM_RAMB18_ADDRATIEHIGH1", - "BRAM_RAMB18_DOADO6", - "BRAM_IMUX_ADDRBWRADDRL3", - "BRAM_SW4END1_4", - "BRAM_FIFO36_DIBDIL3", - "BRAM_EE4C1_0", - "BRAM_FIFO36_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU4", - "BRAM_NE2A2_0", - "BRAM_IMUX21_2", - "BRAM_IMUX2_3", - "BRAM_IMUX45_0", - "BRAM_ER1BEG3_4", - "BRAM_FIFO18_ADDRBWRADDR12", - "BRAM_FAN0_3", - "BRAM_FIFO18_WRCOUNT8", - "BRAM_IMUX32_4", - "BRAM_LOGIC_OUTS_B2_3", - "BRAM_FIFO18_DOBDO3", - "BRAM_IMUX_ADDRARDADDRU7", - "BRAM_RAMB18_RDERR", - "BRAM_IMUX0_0", - "BRAM_IMUX37_3", - "BRAM_FIFO18_ADDRARDADDR5", - "BRAM_IMUX38_UTURN_0", - "BRAM_RAMB18_DOADO1", - "BRAM_LH4_4", - "BRAM_ER1BEG2_3", - "BRAM_ADDRBWRADDRU5", - "BRAM_FIFO36_DIADIU12", - "BRAM_IMUX5_2", - "BRAM_IMUX37_2", - "BRAM_SE2A2_2", - "BRAM_RAMB18_ADDRARDADDR3", - "BRAM_IMUX22_2", - "BRAM_IMUX44_0", - "BRAM_IMUX3_UTURN_4", - "BRAM_IMUX13_4", - "BRAM_FIFO36_RDCOUNT7", - "BRAM_FIFO36_ECCPARITY1", - "BRAM_IMUX19_2", - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "BRAM_FIFO36_ADDRARDADDRU4", - "BRAM_IMUX43_2", - "BRAM_IMUX27_UTURN_0", - "BRAM_FIFO18_WRCOUNT4", - "BRAM_IMUX44_2", - "BRAM_RAMB18_DIBDI2", - "BRAM_LOGIC_OUTS_B19_3", - "BRAM_CASCOUT_ADDRBWRADDRU8", - "BRAM_BYP3_1", - "BRAM_ADDRARDADDRL7", - "BRAM_FIFO18_CLKBWRCLK", - "BRAM_FIFO18_ADDRBWRADDR8", - "BRAM_ADDRBWRADDRU3", - "BRAM_NE4BEG2_2", - "BRAM_UTURN_ADDRARDADDRL6", - "BRAM_IMUX_ADDRARDADDRU14", - "BRAM_IMUX25_UTURN_2", - "BRAM_FIFO36_DIBDIL4", - "BRAM_CASCINBOT_ADDRARDADDRU14", - "BRAM_FIFO18_RDCOUNT7", - "BRAM_EL1BEG0_2", - "BRAM_WW2A0_4", - "BRAM_FIFO36_DIBDIU6", - "BRAM_WW2A0_3", - "BRAM_WW4END0_4", - "BRAM_RAMB18_RDCOUNT6", - "BRAM_UTURN_ADDRARDADDRU14", - "BRAM_LOGIC_OUTS_B20_3", - "BRAM_IMUX3_0", - "BRAM_EE4BEG3_1", - "BRAM_IMUX_ADDRBWRADDRU2", - "BRAM_ADDRARDADDRU0", - "BRAM_IMUX34_2", - "BRAM_IMUX37_UTURN_1", - "BRAM_FAN5_4", - "BRAM_FIFO18_WEBWE4", - "BRAM_SE4BEG2_3", - "BRAM_SE4C3_0", - "BRAM_IMUX16_0", - "BRAM_WR1END2_1", - "BRAM_FIFO36_WRERR", - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRAM_WW4B0_0", - "BRAM_RAMB18_WRCOUNT6", - "BRAM_NW4END2_3", - "BRAM_FIFO18_ADDRARDADDR11", - "BRAM_FAN0_1", - "BRAM_IMUX_ADDRARDADDRL5", - "BRAM_LOGIC_OUTS_B10_3", - "BRAM_IMUX16_1", - "BRAM_IMUX30_4", - "BRAM_LOGIC_OUTS_B13_2", - "BRAM_NE4BEG0_3", - "BRAM_FIFO36_DIADIU8", - "BRAM_FIFO18_WRCOUNT0", - "BRAM_ER1BEG1_3", - "BRAM_FIFO36_DIADIL2", - "BRAM_SE2A0_0", - "BRAM_RAMB18_DIADI10", - "BRAM_FIFO36_DIADIL9", - "BRAM_LH11_4", - "BRAM_NE2A2_2", - "BRAM_LOGIC_OUTS_B21_3", - "BRAM_FIFO18_ADDRBWRADDR0", - "BRAM_FIFO36_TSTCNT9", - "BRAM_RAMB18_RDCOUNT10", - "BRAM_LH2_4", - "BRAM_LOGIC_OUTS_B15_2", - "BRAM_NW4END0_2", - "BRAM_WW2END3_1", - "BRAM_IMUX3_UTURN_3", - "BRAM_FAN4_3", - "BRAM_FIFO36_ADDRARDADDRL12", - "BRAM_FIFO36_DOPADOPU0", - "BRAM_NE4BEG1_3", - "BRAM_IMUX_ADDRARDADDRU4", - "BRAM_UTURN_ADDRARDADDRL8", - "BRAM_FIFO18_DOBDO1", - "BRAM_IMUX28_2", - "BRAM_WW2A0_2", - "BRAM_FIFO36_RSTRAMBU", - "BRAM_WW4A3_1", - "BRAM_IMUX41_2", - "BRAM_SE4BEG3_3", - "BRAM_IMUX23_UTURN_2", - "BRAM_BLOCK_OUTS_L_B3_0", - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRAM_WW4C0_0", - "BRAM_IMUX30_UTURN_1", - "BRAM_RAMB18_WRCOUNT5", - "BRAM_FAN0_2", - "BRAM_SW4END1_3", - "BRAM_IMUX33_UTURN_3", - "BRAM_IMUX36_UTURN_2", - "BRAM_IMUX25_UTURN_4", - "BRAM_LOGIC_OUTS_B18_3", - "BRAM_IMUX1_UTURN_4", - "BRAM_RAMB18_ADDRBWRADDR5", - "BRAM_PMVBRAM_SELECT3", - "BRAM_RAMB18_RDCOUNT11", - "BRAM_IMUX15_4", - "BRAM_NE2A0_3", - "BRAM_LOGIC_OUTS_B21_1", - "BRAM_NE4C2_4", - "BRAM_IMUX17_1", - "BRAM_IMUX_ADDRBWRADDRU13", - "BRAM_LOGIC_OUTS_B9_3", - "BRAM_ER1BEG0_3", - "BRAM_IMUX20_UTURN_1", - "BRAM_RAMB18_DOADO15", - "BRAM_NW2A2_2", - "BRAM_UTURN_ADDRBWRADDRU13", - "BRAM_IMUX_ADDRARDADDRL8", - "BRAM_NW4END3_4", - "BRAM_IMUX38_UTURN_4", - "BRAM_LOGIC_OUTS_B11_4", - "BRAM_IMUX0_UTURN_4", - "BRAM_RAMB18_WRCOUNT7", - "BRAM_NW4A1_4", - "BRAM_LH11_3", - "BRAM_IMUX_ADDRARDADDRL4", - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRAM_FIFO36_DIBDIL2", - "BRAM_NW4A3_4", - "BRAM_FIFO36_DOBDOL1", - "BRAM_FIFO36_WRCOUNT9", - "BRAM_IMUX22_3", - "BRAM_LH10_4", - "BRAM_IMUX3_UTURN_1", - "BRAM_FAN7_0", - "BRAM_SW2A1_0", - "BRAM_IMUX42_UTURN_0", - "BRAM_LOGIC_OUTS_B3_3", - "BRAM_IMUX13_UTURN_1", - "BRAM_FIFO36_DOADOL13", - "BRAM_WL1END0_1", - "BRAM_EE4C3_4", - "BRAM_IMUX43_1", - "BRAM_CASCOUT_ADDRBWRADDRU10", - "BRAM_FIFO36_SBITERR", - "BRAM_FIFO36_DOADOU12", - "BRAM_IMUX29_2", - "BRAM_FAN1_1", - "BRAM_SE4C1_2", - "BRAM_RAMB18_DOADO0", - "BRAM_LH1_2", - "BRAM_FIFO36_DOBDOL3", - "BRAM_WW2A0_0", - "BRAM_IMUX34_UTURN_1", - "BRAM_RAMB18_WRCOUNT9", - "BRAM_NW2A3_4", - "BRAM_IMUX36_UTURN_1", - "BRAM_LOGIC_OUTS_B5_3", - "BRAM_WW2A3_0", - "BRAM_IMUX6_UTURN_4", - "BRAM_IMUX28_UTURN_0", - "BRAM_EE2A3_3", - "BRAM_FIFO36_ADDRARDADDRU10", - "BRAM_RAMB18_EMPTY", - "BRAM_FIFO18_REGCEB", - "BRAM_FIFO36_DIPBDIPL0", - "BRAM_CASCINBOT_ADDRARDADDRU13", - "BRAM_WW2A3_4", - "BRAM_IMUX28_UTURN_3", - "BRAM_SW4END2_1", - "BRAM_LOGIC_OUTS_B21_0", - "BRAM_NE4C2_1", - "BRAM_NE4BEG1_2", - "BRAM_EE4B1_2", - "BRAM_FIFO36_DOADOL9", - "BRAM_WR1END3_2", - "BRAM_IMUX37_4", - "BRAM_LOGIC_OUTS_B15_0", - "BRAM_EE2BEG1_4", - "BRAM_FIFO18_ADDRBWRADDR11", - "BRAM_NW4A3_0", - "BRAM_EE4B2_2", - "BRAM_FIFO36_ADDRARDADDRL3", - "BRAM_FIFO36_WRCOUNT1", - "BRAM_EE4C3_2", - "BRAM_FIFO36_DOADOU7", - "BRAM_IMUX43_4", - "BRAM_LH5_1", - "BRAM_RAMB18_ADDRBWRADDR4", - "BRAM_RAMB18_ADDRBWRADDR8", - "BRAM_SW4A3_2", - "BRAM_CASCOUT_ADDRBWRADDRU12", - "BRAM_UTURN_ADDRBWRADDRU3", - "BRAM_FIFO18_ADDRARDADDR7", - "BRAM_FIFO36_DOADOU10", - "BRAM_FIFO18_WRCOUNT10", - "BRAM_WW4A2_3", - "BRAM_LH10_3", - "BRAM_CASCOUT_ADDRARDADDRU0", - "BRAM_EL1BEG1_3", - "BRAM_RAMB18_DIBDI4", - "BRAM_IMUX18_1", - "BRAM_FIFO18_DIBDI4", - "BRAM_UTURN_ADDRARDADDRL10", - "BRAM_IMUX46_3", - "BRAM_SE4C0_2", - "BRAM_RAMB18_RSTRAMB", - "BRAM_IMUX14_UTURN_2", - "BRAM_FIFO36_DIADIU9", - "BRAM_SE4C1_4", - "BRAM_BYP0_3", - "BRAM_IMUX29_UTURN_0", - "BRAM_RAMB18_DOBDO14", - "BRAM_SE2A2_3", - "BRAM_FIFO18_ADDRARDADDR6", - "BRAM_EE2BEG1_2", - "BRAM_IMUX35_UTURN_0", - "BRAM_IMUX9_UTURN_2", - "BRAM_RAMB18_DIPBDIP1", - "BRAM_IMUX5_UTURN_4", - "BRAM_LOGIC_OUTS_B18_0", - "BRAM_RAMB18_DIADI0", - "BRAM_FIFO18_WEBWE2", - "BRAM_IMUX33_UTURN_0", - "BRAM_WL1END2_0", - "BRAM_FIFO18_RDCOUNT0", - "BRAM_LH1_1", - "BRAM_IMUX26_UTURN_0", - "BRAM_IMUX15_0", - "BRAM_FIFO36_ADDRBWRADDRU5", - "BRAM_FIFO36_DOBDOL15", - "BRAM_IMUX7_UTURN_2", - "BRAM_FIFO36_DOBDOL10", - "BRAM_LH5_3", - "BRAM_ER1BEG0_4", - "BRAM_RAMB18_ADDRARDADDR1", - "BRAM_FIFO36_DOBDOU11", - "BRAM_WW4B3_2", - "BRAM_LH7_3", - "BRAM_FIFO36_DOBDOU5", - "BRAM_WW2END2_2", - "BRAM_FIFO36_ADDRARDADDRU13", - "BRAM_FIFO36_ADDRBWRADDRL13", - "BRAM_FIFO36_TSTIN0", - "BRAM_LH2_0", - "BRAM_NW4END1_2", - "BRAM_IMUX20_1", - "BRAM_FAN4_0", - "BRAM_IMUX36_1", - "BRAM_FIFO36_ADDRARDADDRL8", - "BRAM_BYP2_4", - "BRAM_FIFO36_ENBWRENU", - "BRAM_SW4END3_2", - "BRAM_IMUX25_4", - "BRAM_WW2END1_3", - "BRAM_CASCOUT_ADDRBWRADDRU9", - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRAM_MONITOR_N_0", - "BRAM_BYP7_1", - "BRAM_NE4C0_4", - "BRAM_WW4B3_4", - "BRAM_RAMB18_REGCLKB", - "BRAM_BYP3_2", - "BRAM_IMUX27_4", - "BRAM_FIFO18_DIADI10", - "BRAM_LOGIC_OUTS_B15_4", - "BRAM_SE2A2_1", - "BRAM_EE2BEG3_1", - "BRAM_MONITOR_P_4", - "BRAM_UTURN_ADDRARDADDRL3", - "BRAM_FIFO36_DIBDIU7", - "BRAM_RAMB18_DOADO2", - "BRAM_NW4A2_2", - "BRAM_FIFO36_DOADOL5", - "BRAM_SW4END2_0", - "BRAM_NE4BEG3_0", - "BRAM_LH11_2", - "BRAM_UTURN_ADDRBWRADDRU2", - "BRAM_WR1END1_4", - "BRAM_CTRL0_2", - "BRAM_NE4BEG0_0", - "BRAM_FIFO18_WEA3", - "BRAM_FIFO36_ADDRARDADDRL6", - "BRAM_IMUX3_UTURN_0", - "BRAM_CASCINBOT_ADDRARDADDRU11", - "BRAM_WW4A0_4", - "BRAM_IMUX6_UTURN_2", - "BRAM_SW4A3_0", - "BRAM_WW2END2_4", - "BRAM_RAMB18_WEBWE0", - "BRAM_BYP6_3", - "BRAM_EL1BEG2_4", - "BRAM_NW4A3_2", - "BRAM_IMUX42_UTURN_1", - "BRAM_WW2END3_0", - "BRAM_FIFO36_DIADIU15", - "BRAM_NE4C3_2", - "BRAM_EE2BEG0_1", - "BRAM_CASCOUT_ADDRARDADDRU6", - "BRAM_FIFO36_ADDRBWRADDRL3", - "BRAM_WW4C2_1", - "BRAM_IMUX19_UTURN_3", - "BRAM_BYP7_0", - "BRAM_EE4C1_3", - "BRAM_SE2A3_4", - "BRAM_NW2A1_3", - "BRAM_CTRL0_3", - "BRAM_LOGIC_OUTS_B12_0", - "BRAM_SW4END3_3", - "BRAM_IMUX13_1", - "BRAM_LOGIC_OUTS_B6_4", - "BRAM_FIFO36_ADDRARDADDRU5", - "BRAM_FIFO36_RDERR", - "BRAM_IMUX32_UTURN_3", - "BRAM_SE4BEG0_0", - "BRAM_IMUX22_UTURN_3", - "BRAM_BYP7_3", - "BRAM_IMUX37_1", - "BRAM_IMUX35_UTURN_1", - "BRAM_IMUX_ADDRARDADDRU0", - "BRAM_FIFO18_DOADO3", - "BRAM_IMUX4_2", - "BRAM_SE2A0_3", - "BRAM_FIFO36_TSTWROS12", - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRAM_PMVBRAM_O_2", - "BRAM_EE4B2_1", - "BRAM_UTURN_ADDRARDADDRU1", - "BRAM_IMUX9_UTURN_1", - "BRAM_FIFO18_DIADI12", - "BRAM_LH4_0", - "BRAM_ADDRARDADDRL2", - "BRAM_SW4END0_4", - "BRAM_FIFO36_WEBWEL7", - "BRAM_IMUX4_UTURN_4", - "BRAM_WW2END1_2", - "BRAM_WR1END0_1", - "BRAM_FIFO36_ADDRBWRADDRU6", - "BRAM_SE4C2_2", - "BRAM_IMUX36_2", - "BRAM_BYP4_1", - "BRAM_BLOCK_OUTS_L_B0_3", - "BRAM_UTURN_ADDRBWRADDRL7", - "BRAM_FIFO36_RDCOUNT8", - "BRAM_IMUX42_2", - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "BRAM_SW4END2_4", - "BRAM_FIFO36_DIBDIU3", - "BRAM_FIFO18_DOBDO10", - "BRAM_LOGIC_OUTS_B10_4", - "BRAM_RAMB18_WEBWE1", - "BRAM_RAMB18_RDCOUNT2", - "BRAM_FIFO36_ADDRBWRADDRL14", - "BRAM_IMUX24_1", - "BRAM_IMUX24_4", - "BRAM_EE4B1_3", - "BRAM_BLOCK_OUTS_L_B1_0", - "BRAM_CASCOUT_ADDRARDADDRU11", - "BRAM_IMUX_ADDRARDADDRL3", - "BRAM_LOGIC_OUTS_B22_0", - "BRAM_FIFO36_WEBWEL2", - "BRAM_IMUX33_1", - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRAM_CASCINBOT_ADDRARDADDRU10", - "BRAM_LOGIC_OUTS_B6_2", - "BRAM_EE4C0_2", - "BRAM_FIFO18_DIADI5", - "BRAM_WR1END2_0", - "BRAM_EE4A0_0", - "BRAM_IMUX_ADDRARDADDRL2", - "BRAM_IMUX31_UTURN_2", - "BRAM_IMUX15_UTURN_4", - "BRAM_FIFO36_DOBDOL4", - "BRAM_EE4A2_4", - "BRAM_RAMB18_ADDRBWRADDR11", - "BRAM_IMUX_ADDRARDADDRL14", - "BRAM_FIFO36_WEBWEU5", - "BRAM_UTURN_ADDRBWRADDRL3", - "BRAM_ADDRBWRADDRL0", - "BRAM_WL1END1_3", - "BRAM_BYP5_3", - "BRAM_IMUX23_UTURN_0", - "BRAM_FIFO36_DOADOU6", - "BRAM_LOGIC_OUTS_B2_0", - "BRAM_EE4C3_1", - "BRAM_CASCOUT_ADDRARDADDRU2", - "BRAM_FIFO18_WRERR", - "BRAM_WL1END2_4", - "BRAM_IMUX_ADDRARDADDRU10", - "BRAM_FIFO36_ADDRBWRADDRL7", - "BRAM_ADDRARDADDRU7", - "BRAM_NW4A1_3", - "BRAM_FIFO36_DIBDIL11", - "BRAM_IMUX19_3", - "BRAM_UTURN_ADDRARDADDRL5", - "BRAM_FIFO36_TSTWRCNTOFF", - "BRAM_LOGIC_OUTS_B13_3", - "BRAM_IMUX18_UTURN_4", - "BRAM_FIFO36_ECCPARITY2", - "BRAM_LH12_0", - "BRAM_UTURN_ADDRBWRADDRU0", - "BRAM_FIFO18_DOBDO7", - "BRAM_IMUX_ADDRBWRADDRU6", - "BRAM_LH7_2", - "BRAM_IMUX40_UTURN_2", - "BRAM_EE4A1_1", - "BRAM_IMUX27_2", - "BRAM_NE2A0_0", - "BRAM_WW4B2_1", - "BRAM_LOGIC_OUTS_B18_2", - "BRAM_FIFO18_DOPBDOP1", - "BRAM_IMUX20_UTURN_4", - "BRAM_NW2A1_4", - "BRAM_IMUX6_3", - "BRAM_EE2A2_4", - "BRAM_NW4END1_4", - "BRAM_IMUX36_3", - "BRAM_IMUX34_UTURN_0", - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "BRAM_ADDRBWRADDRU8", - "BRAM_RAMB18_DOADO14", - "BRAM_IMUX22_1", - "BRAM_IMUX44_UTURN_1", - "BRAM_IMUX40_3", - "BRAM_WW4A2_0", - "BRAM_IMUX13_3", - "BRAM_BLOCK_OUTS_L_B2_0", - "BRAM_FIFO36_TSTRDOS5", - "BRAM_IMUX29_1", - "BRAM_FIFO36_TSTCNT5", - "BRAM_FIFO18_DIBDI5", - "BRAM_EE2BEG2_0", - "BRAM_LOGIC_OUTS_B12_4", - "BRAM_NE4BEG0_1", - "BRAM_IMUX8_4", - "BRAM_CASCINBOT_ADDRARDADDRU1", - "BRAM_WW4END0_3", - "BRAM_FIFO18_DOADO2", - "BRAM_IMUX24_UTURN_2", - "BRAM_FIFO36_ADDRARDADDRL0", - "BRAM_IMUX_ADDRBWRADDRL4", - "BRAM_SE2A0_4", - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRAM_FIFO18_ADDRBWRADDR6", - "BRAM_LH5_2", - "BRAM_SW2A0_0", - "BRAM_IMUX7_0", - "BRAM_FIFO36_RDCOUNT2", - "BRAM_RAMB18_WEBWE6", - "BRAM_FAN0_4", - "BRAM_WW4A0_2", - "BRAM_LOGIC_OUTS_B11_3", - "BRAM_FIFO36_TSTOUT1", - "BRAM_CASCINBOT_ADDRARDADDRU7", - "BRAM_BYP1_0", - "BRAM_EE4A1_0", - "BRAM_FIFO36_CASCADEOUTB_1", - "BRAM_NW2A0_0", - "BRAM_LH2_3", - "BRAM_FIFO36_WRCOUNT3", - "BRAM_WW2A3_1", - "BRAM_IMUX7_1", - "BRAM_EE2A0_1", - "BRAM_FIFO36_DIBDIL0", - "BRAM_FIFO18_ADDRARDADDR8", - "BRAM_FIFO36_ADDRBWRADDRL12", - "BRAM_IMUX34_UTURN_4", - "BRAM_IMUX43_UTURN_2", - "BRAM_SW4END3_0", - "BRAM_FIFO18_WRCOUNT7", - "BRAM_NE2A0_2", - "BRAM_IMUX6_UTURN_0", - "BRAM_IMUX46_UTURN_2", - "BRAM_LH4_1", - "BRAM_ADDRARDADDRU5", - "BRAM_IMUX28_1", - "BRAM_FIFO36_TSTCNT8", - "BRAM_FIFO36_ENBWRENL", - "BRAM_FIFO36_RSTREGBU", - "BRAM_FIFO36_ECCPARITY5", - "BRAM_FIFO36_TSTRDOS8", - "BRAM_SW4A2_1", - "BRAM_EE2A1_1", - "BRAM_IMUX12_UTURN_1", - "BRAM_IMUX26_UTURN_1", - "BRAM_IMUX37_UTURN_0", - "BRAM_FIFO36_CLKARDCLKU", - "BRAM_RAMB18_RDCOUNT1", - "BRAM_FIFO36_REGCLKBL", - "BRAM_EE4B0_1", - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRAM_FIFO18_DOADO14", - "BRAM_WW4C2_4", - "BRAM_LH8_0", - "BRAM_IMUX27_UTURN_4", - "BRAM_IMUX45_1", - "BRAM_LOGIC_OUTS_B4_2", - "BRAM_FIFO18_ADDRARDADDR4", - "BRAM_FIFO36_TSTCNT11", - "BRAM_BYP1_3", - "BRAM_EE4A1_2", - "BRAM_FIFO36_DIADIL12", - "BRAM_SW2A3_4", - "BRAM_IMUX0_UTURN_0", - "BRAM_NW2A3_3", - "BRAM_IMUX_ADDRARDADDRU3", - "BRAM_IMUX38_UTURN_1", - "BRAM_ER1BEG2_0", - "BRAM_FIFO36_DOADOL6", - "BRAM_LH6_4", - "BRAM_EE4B2_0", - "BRAM_ER1BEG1_1", - "BRAM_FIFO18_DIADI3", - "BRAM_FIFO18_ADDRARDADDR9", - "BRAM_WW2END0_0", - "BRAM_IMUX26_UTURN_2", - "BRAM_FIFO36_TSTIN1", - "BRAM_FIFO18_ALMOSTEMPTY", - "BRAM_NW4A1_0", - "BRAM_RAMB18_RDCOUNT5", - "BRAM_FIFO36_ADDRBWRADDRL5", - "BRAM_IMUX2_UTURN_1", - "BRAM_FAN2_1", - "BRAM_LOGIC_OUTS_B14_4", - "BRAM_FIFO18_WEA1", - "BRAM_IMUX_ADDRBWRADDRU5", - "BRAM_SE4BEG1_4", - "BRAM_RAMB18_DIADI13", - "BRAM_RAMB18_ADDRARDADDR2", - "BRAM_IMUX30_UTURN_0", - "BRAM_NE4C0_2", - "BRAM_FIFO36_DOADOU14", - "BRAM_WW4A0_1", - "BRAM_MONITOR_N_4", - "BRAM_RAMB18_WEBWE2", - "BRAM_BYP6_2", - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRAM_FIFO36_DOPADOPU1", - "BRAM_RAMB18_ADDRBWRADDR6", - "BRAM_NE4BEG3_1", - "BRAM_FIFO18_RDERR", - "BRAM_LOGIC_OUTS_B4_0", - "BRAM_FIFO36_ADDRBWRADDRL6", - "BRAM_UTURN_ADDRARDADDRL0", - "BRAM_SE2A0_1", - "BRAM_FIFO36_TSTCNT1", - "BRAM_FAN3_2", - "BRAM_FIFO18_ADDRBWRADDR5", - "BRAM_IMUX5_4", - "BRAM_SW2A3_1", - "BRAM_IMUX_ADDRARDADDRU1", - "BRAM_LH12_2", - "BRAM_LOGIC_OUTS_B9_4", - "BRAM_CTRL1_4", - "BRAM_RAMB18_DOADO11", - "BRAM_FIFO36_DOADOL7", - "BRAM_IMUX30_UTURN_4", - "BRAM_EE4BEG1_1", - "BRAM_IMUX36_0", - "BRAM_CLK0_1", - "BRAM_SE4BEG2_2", - "BRAM_ADDRARDADDRU10", - "BRAM_SW2A1_4", - "BRAM_NW2A0_4", - "BRAM_IMUX_ADDRARDADDRU2", - "BRAM_SE4C3_3", - "BRAM_FIFO36_WRCOUNT5", - "BRAM_IMUX24_UTURN_3", - "BRAM_BLOCK_OUTS_L_B2_1", - "BRAM_IMUX32_UTURN_4", - "BRAM_FIFO36_DOADOU5", - "BRAM_LH9_1", - "BRAM_IMUX7_UTURN_4", - "BRAM_CLK1_0", - "BRAM_IMUX43_0", - "BRAM_IMUX8_3", - "BRAM_FIFO36_DIPADIPL0", - "BRAM_EL1BEG1_1", - "BRAM_IMUX45_UTURN_4", - "BRAM_MONITOR_P_1", - "BRAM_WW2A1_2", - "BRAM_FIFO36_DIBDIU1", - "BRAM_BYP0_1", - "BRAM_CASCOUT_ADDRARDADDRU14", - "BRAM_FIFO36_TSTCNT10", - "BRAM_SW2A0_3", - "BRAM_BYP5_2", - "BRAM_LOGIC_OUTS_B7_1", - "BRAM_FIFO36_TSTWROS6", - "BRAM_EL1BEG0_0", - "BRAM_IMUX35_UTURN_4", - "BRAM_CASCINBOT_ADDRARDADDRU2", - "BRAM_ER1BEG3_0", - "BRAM_IMUX24_UTURN_0", - "BRAM_RAMB18_ADDRBWRADDR7", - "BRAM_BYP3_4", - "BRAM_RAMB18_DIBDI7", - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRAM_FIFO36_DIADIL7", - "BRAM_IMUX20_UTURN_0", - "BRAM_IMUX46_1", - "BRAM_NW4END2_4", - "BRAM_SW2A3_0", - "BRAM_FIFO18_DIADI6", - "BRAM_RAMB18_DOBDO13", - "BRAM_SW4A3_1", - "BRAM_RAMB18_DIPADIP1", - "BRAM_FAN2_0", - "BRAM_NE2A1_4", - "BRAM_UTURN_ADDRARDADDRU6", - "BRAM_EL1BEG1_0", - "BRAM_FIFO36_ADDRARDADDRL11", - "BRAM_IMUX30_UTURN_3", - "BRAM_RAMB18_RDCOUNT3", - "BRAM_NE2A0_4", - "BRAM_IMUX32_UTURN_1", - "BRAM_LOGIC_OUTS_B16_0", - "BRAM_FIFO36_RDCOUNT9", - "BRAM_NE4BEG3_2", - "BRAM_NE4C2_2", - "BRAM_IMUX11_UTURN_2", - "BRAM_FIFO36_TSTRDOS7", - "BRAM_BLOCK_OUTS_L_B2_4", - "BRAM_IMUX40_UTURN_1", - "BRAM_WL1END1_2", - "BRAM_UTURN_ADDRARDADDRL11", - "BRAM_FIFO36_WEBWEL0", - "BRAM_FIFO36_DIBDIU15", - "BRAM_RAMB18_DOADO9", - "BRAM_FIFO36_TSTWROS0", - "BRAM_EE2BEG2_3", - "BRAM_SE2A1_2", - "BRAM_FIFO36_WEBWEU1", - "BRAM_IMUX25_2", - "BRAM_EE2BEG1_0", - "BRAM_FIFO36_DOBDOU7", - "BRAM_RAMB18_DIADI12", - "BRAM_FIFO18_RDCOUNT5", - "BRAM_IMUX24_UTURN_4", - "BRAM_FIFO36_FULL", - "BRAM_WW2END1_1", - "BRAM_FIFO18_DOADO12", - "BRAM_IMUX44_4", - "BRAM_IMUX_ADDRBWRADDRL12", - "BRAM_FIFO36_TSTRDOS6", - "BRAM_CLK0_3", - "BRAM_LOGIC_OUTS_B16_3", - "BRAM_IMUX38_4", - "BRAM_WW4END3_1", - "BRAM_ER1BEG1_2", - "BRAM_IMUX18_2", - "BRAM_IMUX46_UTURN_4", - "BRAM_LOGIC_OUTS_B22_3", - "BRAM_RAMB18_DIADI7", - "BRAM_IMUX13_UTURN_2", - "BRAM_IMUX4_1", - "BRAM_NW4END0_1", - "BRAM_IMUX18_4", - "BRAM_IMUX0_UTURN_1", - "BRAM_RAMB18_ADDRARDADDR12", - "BRAM_EE4B1_1", - "BRAM_EE2A3_0", - "BRAM_FIFO36_DIADIU11", - "BRAM_FIFO36_ADDRARDADDRL4", - "BRAM_LOGIC_OUTS_B8_3", - "BRAM_IMUX21_3", - "BRAM_FIFO36_TSTRDOS9", - "BRAM_LOGIC_OUTS_B8_1", - "BRAM_LH9_2", - "BRAM_ER1BEG3_1", - "BRAM_LH2_2", - "BRAM_UTURN_ADDRARDADDRU4", - "BRAM_IMUX4_UTURN_2", - "BRAM_IMUX39_4", - "BRAM_RAMB18_DIBDI9", - "BRAM_LOGIC_OUTS_B21_2", - "BRAM_WW4B2_4", - "BRAM_SW4A0_1", - "BRAM_FIFO36_DIADIU14", - "BRAM_WW2A1_1", - "BRAM_WW4C0_4", - "BRAM_FIFO36_WEAL2", - "BRAM_BYP3_0", - "BRAM_FIFO18_DIADI13", - "BRAM_ADDRARDADDRU14", - "BRAM_EE2A0_4", - "BRAM_EL1BEG1_2", - "BRAM_CTRL1_1", - "BRAM_FIFO36_DIADIU2", - "BRAM_IMUX2_UTURN_0", - "BRAM_EE4BEG0_0", - "BRAM_LOGIC_OUTS_B4_4", - "BRAM_NE4C3_1", - "BRAM_IMUX29_3", - "BRAM_FIFO36_CASCADEINA", - "BRAM_IMUX6_4", - "BRAM_IMUX47_UTURN_4", - "BRAM_FIFO18_DIBDI9", - "BRAM_LH3_2", - "BRAM_CASCOUT_ADDRARDADDRU12", - "BRAM_FIFO36_TSTWROS2", - "BRAM_NE4C0_1", - "BRAM_FIFO18_ADDRARDADDR1", - "BRAM_SE2A3_3", - "BRAM_ADDRARDADDRU13", - "BRAM_FIFO18_DIADI1", - "BRAM_SE4C3_1", - "BRAM_FIFO18_WRCOUNT6", - "BRAM_EL1BEG2_3", - "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "BRAM_IMUX47_2", - "BRAM_FIFO36_DOBDOL2", - "BRAM_FIFO36_DIPADIPU0", - "BRAM_WW4A3_4", - "BRAM_EE4BEG3_2", - "BRAM_LOGIC_OUTS_B17_4", - "BRAM_FAN5_0", - "BRAM_FIFO36_ADDRARDADDRL5", - "BRAM_NW4END1_0", - "BRAM_IMUX37_UTURN_4", - "BRAM_LOGIC_OUTS_B0_4", - "BRAM_IMUX31_UTURN_4", - "BRAM_FIFO36_TSTOFF", - "BRAM_IMUX6_1", - "BRAM_LOGIC_OUTS_B7_0", - "BRAM_EE2BEG1_3", - "BRAM_ADDRBWRADDRL8", - "BRAM_WL1END2_3", - "BRAM_ADDRBWRADDRU6", - "BRAM_IMUX42_0", - "BRAM_EE4B0_2", - "BRAM_FIFO18_ADDRARDADDR12", - "BRAM_LOGIC_OUTS_B5_1", - "BRAM_FIFO36_DOADOU0", - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "BRAM_FIFO18_RSTREGB", - "BRAM_IMUX21_UTURN_1", - "BRAM_IMUX27_0", - "BRAM_SW2A1_3", - "BRAM_PMVBRAM_O_1", - "BRAM_EE2BEG2_4", - "BRAM_WW4C3_0", - "BRAM_NE4BEG0_2", - "BRAM_RAMB18_WEA0", - "BRAM_EE4C1_4", - "BRAM_ADDRBWRADDRU10", - "BRAM_LH11_0", - "BRAM_FIFO18_WRCOUNT2", - "BRAM_FIFO36_DIBDIU14", - "BRAM_IMUX19_UTURN_1", - "BRAM_WW4B2_2", - "BRAM_WW4B3_3", - "BRAM_LOGIC_OUTS_B5_0", - "BRAM_ADDRBWRADDRU14", - "BRAM_SW4A1_1", - "BRAM_IMUX_ADDRARDADDRL13", - "BRAM_UTURN_ADDRBWRADDRL8", - "BRAM_FIFO36_WEAL3", - "BRAM_IMUX_ADDRBWRADDRL15", - "BRAM_FIFO36_REGCEAREGCEU", - "BRAM_IMUX42_UTURN_2", - "BRAM_FIFO36_TSTCNT2", - "BRAM_BYP0_2", - "BRAM_FIFO36_ADDRARDADDRL7", - "BRAM_LOGIC_OUTS_B14_1", - "BRAM_LOGIC_OUTS_B14_2", - "BRAM_EE2A2_1", - "BRAM_FIFO36_ADDRBWRADDRU11", - "BRAM_RAMB18_ADDRBWRADDR0", - "BRAM_IMUX21_4", - "BRAM_UTURN_ADDRARDADDRU3", - "BRAM_IMUX38_2", - "BRAM_LH8_1", - "BRAM_WW2A1_4", - "BRAM_LOGIC_OUTS_B19_1", - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "BRAM_ADDRARDADDRU6", - "BRAM_EE4BEG3_3", - "BRAM_WW4END2_0", - "BRAM_WW4C2_2", - "BRAM_RAMB18_ADDRARDADDR10", - "BRAM_LH12_1", - "BRAM_RAMB18_ADDRBWRADDR13", - "BRAM_LOGIC_OUTS_B1_4", - "BRAM_WW4A2_2", - "BRAM_FAN0_0", - "BRAM_IMUX23_4", - "BRAM_SE4C0_4", - "BRAM_WW2A3_3", - "BRAM_ADDRARDADDRU8", - "BRAM_FIFO18_ALMOSTFULL", - "BRAM_IMUX13_2", - "BRAM_RAMB18_DOBDO15", - "BRAM_EE2A1_3", - "BRAM_WR1END0_4", - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU3", - "BRAM_IMUX15_2", - "BRAM_EE4A2_0", - "BRAM_WL1END0_2", - "BRAM_IMUX32_3", - "BRAM_EE4A1_4", - "BRAM_IMUX14_2", - "BRAM_FIFO36_ECCPARITY3", - "BRAM_FIFO18_DIADI7", - "BRAM_LOGIC_OUTS_B5_2", - "BRAM_FAN3_1", - "BRAM_CASCOUT_ADDRARDADDRU4", - "BRAM_IMUX33_3", - "BRAM_WW4END3_2", - "BRAM_FIFO18_ADDRBWRADDR9", - "BRAM_IMUX32_1", - "BRAM_LH10_0", - "BRAM_RAMB18_ADDRBWRADDR3", - "BRAM_WW4B0_3", - "BRAM_PMVBRAM_ODIV2_1", - "BRAM_LOGIC_OUTS_B15_3", - "BRAM_IMUX29_UTURN_1", - "BRAM_LOGIC_OUTS_B0_1", - "BRAM_IMUX_ADDRBWRADDRL5", - "BRAM_IMUX45_4", - "BRAM_CASCINBOT_ADDRARDADDRU4", - "BRAM_LOGIC_OUTS_B19_0", - "BRAM_IMUX25_UTURN_1", - "BRAM_FIFO36_DIBDIU9", - "BRAM_RAMB18_DIBDI13", - "BRAM_LH6_1", - "BRAM_RAMB18_DIBDI5", - "BRAM_IMUX_ADDRBWRADDRU9", - "BRAM_SW2A0_1", - "BRAM_IMUX2_UTURN_2", - "BRAM_BYP4_3", - "BRAM_FIFO36_WRCOUNT2", - "BRAM_RAMB18_ADDRARDADDR6", - "BRAM_EE4A3_1", - "BRAM_SW2A1_1", - "BRAM_FIFO36_DOBDOU9", - "BRAM_IMUX2_1", - "BRAM_IMUX33_0", - "BRAM_LH7_1", - "BRAM_FIFO18_DIBDI2", - "BRAM_NW4A0_3", - "BRAM_FIFO36_DIADIL11", - "BRAM_SE2A1_3", - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRAM_FIFO36_DOBDOU0", - "BRAM_IMUX13_0", - "BRAM_SE4C2_4", - "BRAM_FIFO36_DBITERR", - "BRAM_FAN3_0", - "BRAM_IMUX40_4", - "BRAM_IMUX9_3", - "BRAM_FIFO18_DIPBDIP0", - "BRAM_WW2END3_3", - "BRAM_IMUX31_UTURN_1", - "BRAM_FIFO36_CLKBWRCLKU", - "BRAM_FIFO18_ADDRBWRADDR7", - "BRAM_NE4C1_3", - "BRAM_EE4BEG3_0", - "BRAM_IMUX12_UTURN_0", - "BRAM_FIFO36_TSTOUT4", - "BRAM_IMUX9_UTURN_3", - "BRAM_FIFO18_DIBDI14", - "BRAM_SW4END1_0", - "BRAM_EL1BEG2_0", - "BRAM_IMUX38_0", - "BRAM_IMUX43_UTURN_4", - "BRAM_RAMB18_WRCOUNT11", - "BRAM_LOGIC_OUTS_B23_2", - "BRAM_FIFO18_DOPADOP1", - "BRAM_FAN7_4", - "BRAM_FIFO18_DOADO5", - "BRAM_IMUX_ADDRARDADDRU6", - "BRAM_SW2A3_2", - "BRAM_NW4END3_3", - "BRAM_RAMB18_DOBDO11", - "BRAM_FIFO18_DIADI11", - "BRAM_FIFO18_DIPADIP0", - "BRAM_LOGIC_OUTS_B17_3", - "BRAM_IMUX18_0", - "BRAM_NE2A2_1", - "BRAM_FIFO18_RDCOUNT4", - "BRAM_UTURN_ADDRARDADDRL7", - "BRAM_IMUX0_UTURN_3", - "BRAM_RAMB18_DOPBDOP0", - "BRAM_RAMB18_WRCOUNT3", - "BRAM_NE2A2_4", - "BRAM_FIFO36_DIBDIL14", - "BRAM_LOGIC_OUTS_B13_1", - "BRAM_EE4BEG2_2", - "BRAM_LOGIC_OUTS_B11_1", - "BRAM_IMUX12_0", - "BRAM_IMUX1_UTURN_3", - "BRAM_FAN4_4", - "BRAM_FIFO36_DOADOL1", - "BRAM_IMUX10_UTURN_1", - "BRAM_IMUX11_3", - "BRAM_RAMB18_DIBDI10", - "BRAM_EE4A3_0", - "BRAM_NE2A3_2", - "BRAM_SW2A3_3", - "BRAM_SE4BEG3_2", - "BRAM_EE4B3_0", - "BRAM_FIFO36_TSTRDOS10", - "BRAM_NE4C1_1", - "BRAM_LH9_3", - "BRAM_RAMB18_ADDRARDADDR9", - "BRAM_ADDRBWRADDRL14", - "BRAM_EE2BEG0_3", - "BRAM_EE4A0_2", - "BRAM_FIFO36_DOADOU9", - "BRAM_RAMB18_ADDRATIEHIGH0", - "BRAM_RAMB18_DOADO4", - "BRAM_UTURN_ADDRARDADDRU9", - "BRAM_WR1END2_3", - "BRAM_IMUX46_2", - "BRAM_ADDRBWRADDRL10", - "BRAM_UTURN_ADDRBWRADDRU12", - "BRAM_WW4A2_4", - "BRAM_RAMB18_DOBDO10", - "BRAM_FIFO36_DOBDOL12", - "BRAM_SW2A2_2", - "BRAM_EL1BEG0_3", - "BRAM_LOGIC_OUTS_B16_4", - "BRAM_NW4END3_0", - "BRAM_IMUX14_4", - "BRAM_CASCINBOT_ADDRARDADDRU6", - "BRAM_SE4C2_1", - "BRAM_IMUX25_3", - "BRAM_IMUX47_4", - "BRAM_WR1END0_0", - "BRAM_NW2A3_1", - "BRAM_FIFO36_ADDRARDADDRU11", - "BRAM_SE4BEG3_0", - "BRAM_ER1BEG2_4", - "BRAM_FIFO36_REGCLKBU", - "BRAM_FIFO18_RSTRAMARSTRAM", - "BRAM_UTURN_ADDRARDADDRL13", - "BRAM_NE2A0_1", - "BRAM_IMUX11_UTURN_1", - "BRAM_FIFO18_WEBWE1", - "BRAM_IMUX16_4", - "BRAM_LOGIC_OUTS_B8_2", - "BRAM_FIFO36_ADDRBWRADDRU2", - "BRAM_IMUX22_UTURN_4", - "BRAM_FIFO36_DIBDIL12", - "BRAM_LOGIC_OUTS_B16_1", - "BRAM_RAMB18_ALMOSTFULL", - "BRAM_WW2A2_4", - "BRAM_IMUX6_2", - "BRAM_LOGIC_OUTS_B16_2", - "BRAM_IMUX32_0", - "BRAM_FIFO36_DIADIL0", - "BRAM_LH10_1", - "BRAM_SW4END3_1", - "BRAM_FIFO36_DIPBDIPL1", - "BRAM_FIFO18_DOADO1", - "BRAM_WW2A1_0", - "BRAM_FIFO36_DOBDOU15", - "BRAM_SW4A2_0", - "BRAM_FIFO36_TSTOUT0", - "BRAM_IMUX14_3", - "BRAM_WW4END3_4", - "BRAM_ER1BEG0_0", - "BRAM_IMUX8_UTURN_1", - "BRAM_FIFO36_DIADIU10", - "BRAM_EE4C0_4", - "BRAM_EE4B3_2", - "BRAM_IMUX29_0", - "BRAM_RAMB18_DIADI3", - "BRAM_IMUX25_1", - "BRAM_FIFO36_RSTREGARSTREGU", - "BRAM_NW2A1_0", - "BRAM_IMUX10_2", - "BRAM_LOGIC_OUTS_B10_2", - "BRAM_LH3_4", - "BRAM_WR1END3_4", - "BRAM_FIFO36_DIBDIU13", - "BRAM_NW4END3_1", - "BRAM_FIFO36_ADDRBWRADDRU8", - "BRAM_WW4A1_3", - "BRAM_WW4B0_1", - "BRAM_IMUX3_UTURN_2", - "BRAM_WW4A0_0", - "BRAM_FIFO36_DIBDIL1", - "BRAM_WW2END1_0", - "BRAM_NW2A1_2", - "BRAM_IMUX17_UTURN_1", - "BRAM_NW4A1_1", - "BRAM_IMUX14_0", - "BRAM_SW4END0_1", - "BRAM_IMUX8_UTURN_3", - "BRAM_IMUX11_2", - "BRAM_WW4B1_4", - "BRAM_FAN7_2", - "BRAM_WW4B3_0", - "BRAM_RAMB18_WRCOUNT1", - "BRAM_LH1_0", - "BRAM_SW4A0_4", - "BRAM_IMUX20_3", - "BRAM_ADDRBWRADDRL6", - "BRAM_FAN1_2", - "BRAM_LOGIC_OUTS_B8_4", - "BRAM_PMVBRAM_ODIV2", - "BRAM_IMUX36_UTURN_3", - "BRAM_IMUX_ADDRARDADDRU12", - "BRAM_FIFO18_RDCOUNT2", - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "BRAM_IMUX11_UTURN_0", - "BRAM_CASCOUT_ADDRBWRADDRU2", - "BRAM_UTURN_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU3", - "BRAM_IMUX10_4", - "BRAM_IMUX7_4", - "BRAM_NE4BEG3_4", - "BRAM_EE2A3_4", - "BRAM_RAMB18_DIADI15", - "BRAM_EL1BEG2_1", - "BRAM_FIFO18_CLKARDCLK", - "BRAM_FIFO36_DOBDOU13", - "BRAM_IMUX34_0", - "BRAM_RAMB18_ADDRBWRADDR9", - "BRAM_FAN3_4", - "BRAM_FIFO36_DOBDOL6", - "BRAM_IMUX26_2", - "BRAM_FIFO18_DIPADIP1", - "BRAM_FIFO18_DOPADOP0", - "BRAM_ADDRARDADDRL3", - "BRAM_RAMB18_DOBDO9", - "BRAM_IMUX1_0", - "BRAM_EE4B3_1", - "BRAM_LOGIC_OUTS_B3_2", - "BRAM_FIFO36_WEAU0", - "BRAM_FIFO36_TSTIN4", - "BRAM_WL1END3_0", - "BRAM_NW4A0_4", - "BRAM_ADDRARDADDRL4", - "BRAM_IMUX_ADDRBWRADDRL2", - "BRAM_IMUX34_3", - "BRAM_NW4END0_3", - "BRAM_SW2A0_2", - "BRAM_WW4B0_2", - "BRAM_IMUX39_UTURN_2", - "BRAM_CASCINBOT_ADDRARDADDRU12", - "BRAM_EL1BEG3_4", - "BRAM_FIFO36_DIPBDIPU0", - "BRAM_NE4C0_3", - "BRAM_UTURN_ADDRARDADDRL14", - "BRAM_IMUX2_2", - "BRAM_FIFO36_REGCLKARDRCLKL", - "BRAM_FIFO36_REGCEBL", - "BRAM_IMUX27_UTURN_1", - "BRAM_FIFO36_REGCEBU", - "BRAM_RAMB18_DIBDI3", - "BRAM_LOGIC_OUTS_B6_1", - "BRAM_RAMB18_DIADI14", - "BRAM_FIFO36_RDCOUNT11", - "BRAM_FIFO36_ADDRARDADDRL9", - "BRAM_FIFO18_DIPBDIP1", - "BRAM_PMVBRAM_SELECT4", - "BRAM_IMUX3_3", - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "BRAM_WW2END2_1", - "BRAM_NW2A3_2", - "BRAM_CASCOUT_ADDRARDADDRU1", - "BRAM_IMUX_ADDRBWRADDRU1", - "BRAM_RAMB18_DIADI4", - "BRAM_FIFO36_DOADOU15", - "BRAM_WW4B2_0", - "BRAM_NE2A1_0", - "BRAM_EE2BEG0_4", - "BRAM_UTURN_ADDRARDADDRL4", - "BRAM_FIFO36_DIADIU0", - "BRAM_IMUX2_0", - "BRAM_IMUX17_2", - "BRAM_ADDRBWRADDRL13", - "BRAM_LOGIC_OUTS_B2_2", - "BRAM_FIFO36_ENARDENL", - "BRAM_NW2A3_0", - "BRAM_LH5_4", - "BRAM_FIFO36_DOADOL3", - "BRAM_LH6_2", - "BRAM_FIFO18_ADDRBWRADDR13", - "BRAM_IMUX_ADDRBWRADDRL13", - "BRAM_IMUX44_3", - "BRAM_IMUX10_UTURN_2", - "BRAM_IMUX31_1", - "BRAM_NW4A2_3", - "BRAM_IMUX40_0", - "BRAM_FIFO36_DIADIL14", - "BRAM_WR1END0_3", - "BRAM_FIFO18_RDCOUNT10", - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRAM_IMUX47_UTURN_0", - "BRAM_IMUX43_UTURN_3", - "BRAM_LOGIC_OUTS_B19_4", - "BRAM_WW4C0_3", - "BRAM_LOGIC_OUTS_B14_3", - "BRAM_FIFO36_DOADOL10", - "BRAM_RAMB18_DOADO5", - "BRAM_RAMB18_RSTREGARSTREG", - "BRAM_ER1BEG1_4", - "BRAM_IMUX7_3", - "BRAM_NW4END3_2", - "BRAM_FIFO36_ECCPARITY6", - "BRAM_FIFO18_DOBDO8", - "BRAM_EE4B2_4", - "BRAM_IMUX4_UTURN_3", - "BRAM_NE4BEG1_1", - "BRAM_IMUX41_UTURN_3", - "BRAM_IMUX17_UTURN_4", - "BRAM_FIFO36_DIPADIPU1", - "BRAM_EE4A2_1", - "BRAM_WW2A2_2", - "BRAM_ADDRARDADDRL1", - "BRAM_WL1END0_4", - "BRAM_BLOCK_OUTS_L_B1_2", - "BRAM_EE4B0_3", - "BRAM_RAMB18_DOBDO7", - "BRAM_IMUX19_UTURN_0", - "BRAM_LH5_0", - "BRAM_IMUX20_4", - "BRAM_FIFO36_ADDRBWRADDRL4", - "BRAM_EE2BEG2_1", - "BRAM_IMUX21_1", - "BRAM_LH10_2", - "BRAM_RAMB18_DOBDO2", - "BRAM_LOGIC_OUTS_B18_1", - "BRAM_SW4END0_3", - "BRAM_CLK0_4", - "BRAM_FIFO36_WRCOUNT0", - "BRAM_WW4END3_0", - "BRAM_EE4B1_4", - "BRAM_FIFO36_ECCPARITY0", - "BRAM_RAMB18_DOPADOP1", - "BRAM_ADDRARDADDRU11", - "BRAM_MONITOR_P_3", - "BRAM_CASCOUT_ADDRBWRADDRU6", - "BRAM_IMUX37_UTURN_3", - "BRAM_UTURN_ADDRBWRADDRU5", - "BRAM_BLOCK_OUTS_L_B2_3", - "BRAM_WW4B1_1", - "BRAM_FIFO18_DOBDO15", - "BRAM_LOGIC_OUTS_B7_4", - "BRAM_IMUX28_UTURN_1", - "BRAM_WW2END3_2", - "BRAM_SW2A2_4", - "BRAM_BLOCK_OUTS_L_B3_4", - "BRAM_LOGIC_OUTS_B22_1", - "BRAM_IMUX8_2", - "BRAM_IMUX15_1", - "BRAM_LOGIC_OUTS_B6_0", - "BRAM_RAMB18_RDCOUNT9", - "BRAM_CTRL0_0", - "BRAM_SE2A3_2", - "BRAM_FIFO36_ADDRBWRADDRU4", - "BRAM_EL1BEG0_1", - "BRAM_FIFO36_RDCOUNT3", - "BRAM_RAMB18_ADDRBTIEHIGH0", - "BRAM_FIFO36_ADDRBWRADDRL2", - "BRAM_EE2BEG3_2", - "BRAM_IMUX35_UTURN_2", - "BRAM_ADDRBWRADDRL5", - "BRAM_FIFO36_DOADOL8", - "BRAM_RAMB18_ADDRARDADDR5", - "BRAM_FIFO36_DIBDIL15", - "BRAM_NW4A0_2", - "BRAM_FIFO36_WEBWEU7", - "BRAM_WW4C1_3", - "BRAM_IMUX36_UTURN_4", - "BRAM_FIFO18_DIBDI13", - "BRAM_RAMB18_CLKBWRCLK", - "BRAM_FIFO36_ADDRARDADDRU7", - "BRAM_UTURN_ADDRARDADDRU12", - "BRAM_FIFO36_ECCPARITY4", - "BRAM_IMUX_ADDRARDADDRL1", - "BRAM_LOGIC_OUTS_B4_3", - "BRAM_SE2A1_4", - "BRAM_SE4C3_2", - "BRAM_WW2END1_4", - "BRAM_IMUX44_UTURN_4", - "BRAM_FIFO36_DIBDIU11", - "BRAM_WW4END2_3", - "BRAM_FIFO36_TSTOUT2", - "BRAM_EE4A3_2", - "BRAM_RAMB18_WEBWE5", - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRAM_FIFO36_DIADIL1", - "BRAM_FIFO36_EMPTY", - "BRAM_RAMB18_DIBDI6", - "BRAM_FIFO36_TSTCNT6", - "BRAM_FIFO36_TSTIN2", - "BRAM_IMUX_ADDRBWRADDRL0", - "BRAM_FIFO36_DOADOU13", - "BRAM_NE4C3_4", - "BRAM_WW4A1_4", - "BRAM_EE4C2_3", - "BRAM_IMUX23_3", - "BRAM_IMUX_ADDRARDADDRL0", - "BRAM_FIFO36_DIBDIL13", - "BRAM_IMUX37_0", - "BRAM_IMUX10_1", - "BRAM_FIFO36_DIADIL5", - "BRAM_EE4C0_1", - "BRAM_FIFO36_WEBWEL1", - "BRAM_LH2_1", - "BRAM_IMUX5_3", - "BRAM_IMUX47_UTURN_3", - "BRAM_IMUX_ADDRARDADDRL12", - "BRAM_WW2END0_1", - "BRAM_FIFO36_ADDRARDADDRL1", - "BRAM_SE4BEG3_1", - "BRAM_FAN2_2", - "BRAM_RAMB18_DIBDI1", - "BRAM_WR1END1_1", - "BRAM_LOGIC_OUTS_B1_0", - "BRAM_IMUX8_1", - "BRAM_LOGIC_OUTS_B22_4", - "BRAM_FIFO36_DIADIU6", - "BRAM_EE4C2_4", - "BRAM_WW4B2_3", - "BRAM_EL1BEG3_3", - "BRAM_WW4B3_1", - "BRAM_FIFO36_DOADOU2", - "BRAM_EE2A1_2", - "BRAM_WR1END3_3", - "BRAM_FIFO36_TSTRDOS2", - "BRAM_NW4A0_1", - "BRAM_IMUX_ADDRARDADDRU9", - "BRAM_CTRL1_2", - "BRAM_IMUX26_0", - "BRAM_FIFO36_DOBDOL14", - "BRAM_EE4B0_0", - "BRAM_IMUX33_UTURN_1", - "BRAM_IMUX15_3", - "BRAM_SE4BEG1_0", - "BRAM_NE4BEG2_3", - "BRAM_RAMB18_WRCOUNT10", - "BRAM_RAMB18_WEBWE3", - "BRAM_EL1BEG3_2", - "BRAM_LOGIC_OUTS_B17_1", - "BRAM_IMUX_ADDRBWRADDRU8", - "BRAM_BYP2_2", - "BRAM_ADDRARDADDRL0", - "BRAM_IMUX5_UTURN_0", - "BRAM_FIFO36_DOBDOU4", - "BRAM_FIFO18_FULL", - "BRAM_FIFO36_WRCOUNT10", - "BRAM_IMUX20_0", - "BRAM_EE4A2_3", - "BRAM_IMUX22_UTURN_2", - "BRAM_RAMB18_ADDRBWRADDR12", - "BRAM_ADDRARDADDRU2", - "BRAM_LOGIC_OUTS_B20_1", - "BRAM_IMUX14_UTURN_1", - "BRAM_EE4B3_3", - "BRAM_IMUX8_0", - "BRAM_EE2BEG0_2", - "BRAM_IMUX38_UTURN_3", - "BRAM_NE4BEG2_0", - "BRAM_FIFO18_DOBDO5", - "BRAM_IMUX21_0", - "BRAM_FIFO36_DIADIU5", - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRAM_IMUX9_UTURN_0", - "BRAM_FIFO36_DOADOU3", - "BRAM_WW4A3_2", - "BRAM_UTURN_ADDRBWRADDRL0", - "BRAM_ER1BEG2_2", - "BRAM_FIFO36_TSTWROS9", - "BRAM_SW4END2_2", - "BRAM_NE2A1_1", - "BRAM_FIFO36_DOBDOU2", - "BRAM_WW4B1_3", - "BRAM_IMUX40_UTURN_0", - "BRAM_IMUX35_1", - "BRAM_CLK1_3", - "BRAM_NW2A2_3", - "BRAM_LOGIC_OUTS_B15_1", - "BRAM_IMUX24_3", - "BRAM_NW4A3_3", - "BRAM_LOGIC_OUTS_B1_2", - "BRAM_IMUX46_4", - "BRAM_EE4C2_0", - "BRAM_BYP3_3", - "BRAM_IMUX24_UTURN_1", - "BRAM_BYP6_1", - "BRAM_UTURN_ADDRBWRADDRL1", - "BRAM_LOGIC_OUTS_B2_1", - "BRAM_IMUX1_4", - "BRAM_FIFO18_DOBDO14", - "BRAM_RAMB18_WRCOUNT8", - "BRAM_IMUX15_UTURN_1", - "BRAM_FIFO36_ADDRBWRADDRL11", - "BRAM_IMUX39_UTURN_4", - "BRAM_FIFO18_DIADI8", - "BRAM_LH7_4", - "BRAM_FIFO36_WEBWEU0", - "BRAM_FIFO36_ADDRARDADDRU1", - "BRAM_FIFO18_DOBDO11", - "BRAM_SE4BEG2_0", - "BRAM_RAMB18_DIPADIP0", - "BRAM_IMUX34_UTURN_3", - "BRAM_EE2BEG2_2", - "BRAM_LOGIC_OUTS_B3_0", - "BRAM_FIFO36_DIADIL13", - "BRAM_ADDRARDADDRL12", - "BRAM_WR1END1_3", - "BRAM_RAMB18_DOADO10", - "BRAM_IMUX23_UTURN_1", - "BRAM_FIFO36_WEAL0", - "BRAM_WW2END2_3", - "BRAM_IMUX47_UTURN_2", - "BRAM_WR1END3_1", - "BRAM_EE4BEG3_4", - "BRAM_IMUX41_0", - "BRAM_WW4A3_0", - "BRAM_IMUX30_2", - "BRAM_FIFO18_REGCEAREGCE", - "BRAM_EE4C1_2", - "BRAM_LH11_1", - "BRAM_IMUX47_UTURN_1", - "BRAM_LOGIC_OUTS_B0_0", - "BRAM_BYP5_0", - "BRAM_FIFO18_REGCLKB", - "BRAM_EE2A0_2", - "BRAM_FIFO36_DIBDIL7", - "BRAM_EE2A2_3", - "BRAM_CASCOUT_ADDRBWRADDRU1", - "BRAM_IMUX15_UTURN_2", - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "BRAM_LOGIC_OUTS_B11_2", - "BRAM_FIFO18_WRCOUNT11", - "BRAM_RAMB18_DIADI5", - "BRAM_WW4A0_3", - "BRAM_LOGIC_OUTS_B19_2", - "BRAM_UTURN_ADDRBWRADDRL14", - "BRAM_IMUX1_UTURN_1", - "BRAM_FIFO36_ADDRARDADDRU6", - "BRAM_FIFO36_WEAU1", - "BRAM_FIFO18_DOADO6", - "BRAM_FIFO36_WEBWEU2", - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRAM_LOGIC_OUTS_B9_1", - "BRAM_FIFO36_DIADIL4", - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "BRAM_SW4END0_0", - "BRAM_CLK0_0", - "BRAM_FIFO36_DOPADOPL0", - "BRAM_RAMB18_ADDRARDADDR7", - "BRAM_CASCINBOT_ADDRARDADDRU5", - "BRAM_FIFO18_ADDRBTIEHIGH1", - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRAM_IMUX16_UTURN_4", - "BRAM_EE4BEG0_1", - "BRAM_FIFO36_RSTREGBL", - "BRAM_EE2BEG1_1", - "BRAM_CTRL1_0", - "BRAM_IMUX4_3", - "BRAM_ADDRBWRADDRU11", - "BRAM_IMUX28_UTURN_4", - "BRAM_IMUX40_UTURN_3", - "BRAM_CASCINBOT_ADDRARDADDRU3", - "BRAM_IMUX12_UTURN_4", - "BRAM_IMUX32_UTURN_2", - "BRAM_CASCOUT_ADDRBWRADDRU14", - "BRAM_RAMB18_DIADI2", - "BRAM_IMUX41_UTURN_2", - "BRAM_IMUX_ADDRBWRADDRL9", - "BRAM_NW4END2_0", - "BRAM_IMUX45_UTURN_2", - "BRAM_LOGIC_OUTS_B20_0", - "BRAM_LOGIC_OUTS_B10_1", - "BRAM_SW4A1_3", - "BRAM_FIFO36_WEBWEL6", - "BRAM_NW4A3_1", - "BRAM_LH6_3", - "BRAM_FIFO36_ADDRBWRADDRL0", - "BRAM_IMUX4_UTURN_0", - "BRAM_EE4BEG0_2", - "BRAM_RAMB18_DOBDO3", - "BRAM_FAN4_1", - "BRAM_BYP1_1", - "BRAM_IMUX39_UTURN_0", - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRAM_NW4END0_0", - "BRAM_WW2A2_0", - "BRAM_FIFO36_DOADOL4", - "BRAM_RAMB18_ENARDEN", - "BRAM_FIFO18_WEBWE7", - "BRAM_IMUX17_UTURN_3", - "BRAM_SE4BEG2_4", - "BRAM_FIFO18_ADDRBWRADDR10", - "BRAM_WL1END3_3", - "BRAM_IMUX17_UTURN_0", - "BRAM_FIFO18_ADDRBWRADDR4", - "BRAM_WW2END0_3", - "BRAM_SE2A1_1", - "BRAM_EE4BEG1_3", - "BRAM_IMUX41_1", - "BRAM_EE4C1_1", - "BRAM_ADDRBWRADDRL1", - "BRAM_NW4END2_1", - "BRAM_IMUX32_2", - "BRAM_RAMB18_ADDRBWRADDR1", - "BRAM_FIFO18_DOADO0", - "BRAM_RAMB18_RDCOUNT0", - "BRAM_IMUX16_UTURN_3", - "BRAM_SW4END1_1", - "BRAM_IMUX16_UTURN_2", - "BRAM_FIFO18_WEBWE0", - "BRAM_FIFO36_WEBWEU3", - "BRAM_CASCOUT_ADDRARDADDRU10", - "BRAM_SE4BEG0_3", - "BRAM_SW4A2_4", - "BRAM_ADDRBWRADDRL9", - "BRAM_IMUX21_UTURN_0", - "BRAM_IMUX3_2", - "BRAM_IMUX30_0", - "BRAM_FIFO36_DIADIU1", - "BRAM_SW2A2_1", - "BRAM_WW4END1_3", - "BRAM_CLK1_2", - "BRAM_NE4C1_0", - "BRAM_RAMB18_ALMOSTEMPTY", - "BRAM_WW2A3_2", - "BRAM_EE4B2_3", - "BRAM_IMUX31_2", - "BRAM_IMUX19_0", - "BRAM_FIFO36_DOBDOL11", - "BRAM_LOGIC_OUTS_B17_0", - "BRAM_FIFO36_ADDRBWRADDRL10", - "BRAM_IMUX12_3", - "BRAM_SE4BEG1_2", - "BRAM_FIFO36_DOADOL11", - "BRAM_LH7_0", - "BRAM_IMUX20_2", - "BRAM_IMUX14_UTURN_0", - "BRAM_FIFO36_TSTWROS8", - "BRAM_LOGIC_OUTS_B4_1", - "BRAM_ADDRBWRADDRL4", - "BRAM_FIFO36_DOADOL15", - "BRAM_FIFO36_DIPBDIPU1", - "BRAM_IMUX26_3", - "BRAM_BLOCK_OUTS_L_B0_0", - "BRAM_WW4END2_4", - "BRAM_IMUX39_UTURN_3", - "BRAM_IMUX2_UTURN_3", - "BRAM_MONITOR_N_2", - "BRAM_UTURN_ADDRARDADDRU13", - "BRAM_FIFO18_DIBDI6", - "BRAM_BYP7_4", - "BRAM_IMUX6_UTURN_3", - "BRAM_IMUX34_4", - "BRAM_IMUX_ADDRBWRADDRU7", - "BRAM_SW4END1_2", - "BRAM_FIFO18_DIBDI8", - "BRAM_FIFO36_TSTRDOS0", - "BRAM_FIFO36_TSTWROS3", - "BRAM_IMUX41_UTURN_1", - "BRAM_FIFO36_REGCEAREGCEL", - "BRAM_EE4A0_3", - "BRAM_IMUX5_UTURN_1", - "BRAM_FIFO18_RDCOUNT9", - "BRAM_BLOCK_OUTS_L_B0_1", - "BRAM_WL1END2_1", - "BRAM_LOGIC_OUTS_B23_1", - "BRAM_WW4A1_0", - "BRAM_FIFO36_ADDRBWRADDRU13", - "BRAM_IMUX0_2", - "BRAM_IMUX_ADDRARDADDRL6", - "BRAM_FAN6_0", - "BRAM_IMUX_ADDRBWRADDRL1", - "BRAM_WW4END1_1", - "BRAM_IMUX47_0", - "BRAM_IMUX31_UTURN_3", - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRAM_IMUX0_1", - "BRAM_ER1BEG1_0", - "BRAM_NW4END1_3", - "BRAM_FIFO36_ADDRARDADDRL2", - "BRAM_EE4BEG2_0", - "BRAM_FIFO36_WEBWEU4", - "BRAM_CLK1_4", - "BRAM_UTURN_ADDRBWRADDRL5", - "BRAM_EE4BEG1_0", - "BRAM_IMUX12_4", - "BRAM_EE4BEG1_4", - "BRAM_EL1BEG3_1", - "BRAM_IMUX11_UTURN_4", - "BRAM_IMUX0_UTURN_2", - "BRAM_FIFO36_TSTRDCNTOFF", - "BRAM_MONITOR_N_3", - "BRAM_IMUX45_UTURN_3", - "BRAM_NE2A1_3", - "BRAM_FIFO18_DIADI14", - "BRAM_SE2A3_1", - "BRAM_UTURN_ADDRARDADDRU10", - "BRAM_IMUX41_UTURN_0", - "BRAM_FIFO36_DIADIL3", - "BRAM_SE2A3_0", - "BRAM_IMUX14_UTURN_4", - "BRAM_SE4BEG0_1", - "BRAM_RAMB18_ADDRBWRADDR2", - "BRAM_EE4C2_2", - "BRAM_EL1BEG0_4", - "BRAM_NW2A2_0", - "BRAM_FIFO36_INJECTSBITERR", - "BRAM_IMUX32_UTURN_0", - "BRAM_CASCINBOT_ADDRARDADDRU9", - "BRAM_FIFO36_DIBDIU12", - "BRAM_IMUX47_3", - "BRAM_CTRL0_4", - "BRAM_RAMB18_DOBDO6", - "BRAM_FIFO18_RDCOUNT6", - "BRAM_IMUX23_1", - "BRAM_IMUX31_4", - "BRAM_FIFO36_REGCLKARDRCLKU", - "BRAM_IMUX28_3", - "BRAM_WW4C0_2", - "BRAM_SW4A0_0", - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRAM_FIFO36_ADDRARDADDRU12", - "BRAM_ADDRBWRADDRL2", - "BRAM_IMUX26_4", - "BRAM_LH3_0", - "BRAM_RAMB18_DIBDI8", - "BRAM_IMUX5_0", - "BRAM_CASCINBOT_ADDRBWRADDRU10", - "BRAM_FIFO36_ADDRBWRADDRU10", - "BRAM_FIFO18_DOADO4", - "BRAM_EE4BEG0_3", - "BRAM_EL1BEG1_4", - "BRAM_FIFO36_ADDRARDADDRU0", - "BRAM_RAMB18_DOBDO1", - "BRAM_RAMB18_WEA1", - "BRAM_WW2A0_1", - "BRAM_FIFO36_DIPADIPL1", - "BRAM_SE4BEG3_4", - "BRAM_EL1BEG3_0", - "BRAM_IMUX39_3", - "BRAM_FAN5_3", - "BRAM_EL1BEG2_2", - "BRAM_FIFO18_ADDRBWRADDR2", - "BRAM_SE4BEG1_3", - "BRAM_IMUX9_2", - "BRAM_WW4B0_4", - "BRAM_IMUX28_UTURN_2", - "BRAM_IMUX23_2", - "BRAM_MONITOR_P_0", - "BRAM_WW4B1_2", - "BRAM_LOGIC_OUTS_B10_0", - "BRAM_FIFO18_RDCOUNT11", - "BRAM_FIFO36_DIADIU13", - "BRAM_IMUX13_UTURN_0", - "BRAM_FIFO36_DOBDOL13", - "BRAM_IMUX28_0", - "BRAM_RAMB18_DIBDI11", - "BRAM_FIFO36_WEBWEL4", - "BRAM_NE2A1_2", - "BRAM_FIFO36_DIADIL8", - "BRAM_FIFO36_TSTWROS10", - "BRAM_NE2A3_1", - "BRAM_IMUX_ADDRARDADDRU11", - "BRAM_FIFO36_TSTRDOS4", - "BRAM_RAMB18_FULL", - "BRAM_IMUX26_UTURN_4", - "BRAM_FIFO18_DIBDI7", - "BRAM_IMUX1_2", - "BRAM_EE4C3_0", - "BRAM_IMUX34_1", - "BRAM_IMUX2_4", - "BRAM_FIFO36_DOBDOL0", - "BRAM_FIFO18_DIBDI0", - "BRAM_FIFO18_ADDRARDADDR0", - "BRAM_ADDRBWRADDRU2", - "BRAM_IMUX33_UTURN_2", - "BRAM_IMUX5_UTURN_2", - "BRAM_CASCOUT_ADDRBWRADDRU11", - "BRAM_IMUX_ADDRARDADDRL11", - "BRAM_IMUX41_UTURN_4", - "BRAM_FIFO36_DOBDOU3", - "BRAM_IMUX42_1", - "BRAM_IMUX21_UTURN_3", - "BRAM_LH9_4", - "BRAM_FIFO36_TSTCNT12", - "BRAM_FIFO36_TSTRDOS1", - "BRAM_IMUX43_UTURN_0", - "BRAM_UTURN_ADDRARDADDRU5", - "BRAM_BYP2_0", - "BRAM_LOGIC_OUTS_B6_3", - "BRAM_FIFO36_DOBDOU1", - "BRAM_IMUX45_2", - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRAM_WW4C1_1", - "BRAM_FIFO36_ADDRARDADDRL14", - "BRAM_FIFO36_ADDRBWRADDRL1", - "BRAM_SW2A2_0", - "BRAM_FIFO18_DIADI4", - "BRAM_FIFO36_WEBWEU6", - "BRAM_FIFO18_ADDRARDADDR3", - "BRAM_FIFO36_DOPBDOPL1", - "BRAM_ADDRARDADDRL8", - "BRAM_NW2A2_4", - "BRAM_IMUX35_0", - "BRAM_NW2A0_1", - "BRAM_SE4C1_3", - "BRAM_FIFO18_WRCOUNT3", - "BRAM_FIFO18_REGCLKARDRCLK", - "BRAM_EE2BEG3_4", - "BRAM_WW4B1_0", - "BRAM_FIFO36_TSTCNT3", - "BRAM_UTURN_ADDRBWRADDRL2", - "BRAM_WW4C2_0", - "BRAM_RAMB18_ADDRBWRADDR10", - "BRAM_CASCOUT_ADDRBWRADDRU7", - "BRAM_FIFO36_WRCOUNT8", - "BRAM_WW4END3_3", - "BRAM_UTURN_ADDRBWRADDRU14", - "BRAM_ADDRBWRADDRU12", - "BRAM_WW4C3_1", - "BRAM_IMUX12_UTURN_3", - "BRAM_NE4C2_3", - "BRAM_RAMB18_DIADI1", - "BRAM_WW2END0_2", - "BRAM_WR1END2_2", - "BRAM_IMUX46_0", - "BRAM_FIFO18_DIBDI15", - "BRAM_IMUX_ADDRBWRADDRU4", - "BRAM_IMUX45_UTURN_1", - "BRAM_FIFO36_CASCADEOUTB", - "BRAM_IMUX15_UTURN_0", - "BRAM_FIFO36_TSTWROS11", - "BRAM_FIFO36_RDCOUNT12", - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRAM_WW4C1_0", - "BRAM_ER1BEG0_2", - "BRAM_FIFO36_WEAL1", - "BRAM_IMUX28_4", - "BRAM_IMUX22_UTURN_1", - "BRAM_SE4C1_0", - "BRAM_NW4A2_1", - "BRAM_FIFO36_RDCOUNT10", - "BRAM_WL1END0_3", - "BRAM_SE4C3_4", - "BRAM_IMUX11_4", - "BRAM_FIFO18_DOADO7", - "BRAM_CASCOUT_ADDRARDADDRU13", - "BRAM_EE4BEG2_4", - "BRAM_EE2BEG0_0", - "BRAM_IMUX_ADDRBWRADDRU11", - "BRAM_RAMB18_DOBDO5", - "BRAM_IMUX7_UTURN_3", - "BRAM_EE4BEG2_3", - "BRAM_EE2A2_0", - "BRAM_IMUX19_4", - "BRAM_SW4A1_0", - "BRAM_FIFO36_CASCADEOUTA_1", - "BRAM_RAMB18_DOBDO0", - "BRAM_IMUX31_UTURN_0", - "BRAM_IMUX29_UTURN_3", - "BRAM_IMUX44_UTURN_2", - "BRAM_IMUX17_4", - "BRAM_IMUX44_1", - "BRAM_WW4C1_2", - "BRAM_SW4END0_2", - "BRAM_EE4C3_3", - "BRAM_RAMB18_DOADO8", - "BRAM_LH12_3", - "BRAM_NW2A0_2", - "BRAM_CTRL1_3", - "BRAM_SW4A2_3", - "BRAM_IMUX17_3", - "BRAM_FIFO36_DOADOL14", - "BRAM_IMUX12_1", - "BRAM_SE4BEG2_1", - "BRAM_FAN6_4", - "BRAM_IMUX7_2", - "BRAM_LOGIC_OUTS_B13_0", - "BRAM_IMUX45_3", - "BRAM_FIFO36_DIADIU3", - "BRAM_UTURN_ADDRBWRADDRU8", - "BRAM_FIFO36_DIBDIU8", - "BRAM_FIFO36_ADDRARDADDRL15", - "BRAM_IMUX8_UTURN_0", - "BRAM_FIFO36_DOBDOU14", - "BRAM_FIFO36_DOBDOL9", - "BRAM_IMUX12_2", - "BRAM_SE4C0_0", - "BRAM_IMUX18_UTURN_3", - "BRAM_RAMB18_RDCOUNT4", - "BRAM_WL1END1_4", - "BRAM_NE4C1_4", - "BRAM_FIFO18_ENBWREN", - "BRAM_IMUX35_UTURN_3", - "BRAM_WW2END3_4", - "BRAM_RAMB18_WRCOUNT2", - "BRAM_BYP2_3", - "BRAM_EE4BEG2_1", - "BRAM_PMVBRAM_O", - "BRAM_NE4BEG1_4", - "BRAM_NE2A2_3", - "BRAM_EE4C0_0", - "BRAM_IMUX21_UTURN_4", - "BRAM_IMUX26_1", - "BRAM_ADDRBWRADDRL11", - "BRAM_IMUX_ADDRBWRADDRU14", - "BRAM_IMUX_ADDRARDADDRL10", - "BRAM_NE4C3_3", - "BRAM_EE2A3_1", - "BRAM_IMUX_ADDRARDADDRU8", - "BRAM_FIFO36_ADDRARDADDRL10", - "BRAM_IMUX_ADDRBWRADDRL11", - "BRAM_FIFO18_DOBDO9", - "BRAM_FIFO36_TSTWROS4", - "BRAM_SE2A2_0", - "BRAM_FIFO36_ENARDENU", - "BRAM_SE4BEG0_4", - "BRAM_IMUX17_UTURN_2", - "BRAM_UTURN_ADDRARDADDRU2", - "BRAM_FIFO18_WEBWE3", - "BRAM_FIFO36_DOADOL12", - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRAM_FIFO36_DOADOU11", - "BRAM_EE4A3_3", - "BRAM_IMUX39_UTURN_1", - "BRAM_IMUX31_3", - "BRAM_FIFO36_DIBDIL8", - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRAM_NW4END0_4", - "BRAM_RAMB18_DOBDO8", - "BRAM_FIFO18_WEBWE6", - "BRAM_FIFO36_DOBDOL7", - "BRAM_ADDRBWRADDRU1", - "BRAM_ER1BEG2_1", - "BRAM_IMUX10_UTURN_4", - "BRAM_EE2A0_3", - "BRAM_NW2A1_1", - "BRAM_PMVBRAM_SELECT2", - "BRAM_WW4END2_2", - "BRAM_RAMB18_DOADO7", - "BRAM_FIFO36_TSTCNT7", - "BRAM_WW4END0_0", - "BRAM_FIFO36_TSTFLAGIN", - "BRAM_IMUX38_1", - "BRAM_IMUX39_1", - "BRAM_RAMB18_WRCOUNT0", - "BRAM_LOGIC_OUTS_B7_2", - "BRAM_UTURN_ADDRBWRADDRU1", - "BRAM_FIFO36_DOBDOU6", - "BRAM_RAMB18_ADDRARDADDR8", - "BRAM_IMUX42_3", - "BRAM_SW4A3_3", - "BRAM_FIFO36_TSTRDOS12", - "BRAM_SE4BEG0_2", - "BRAM_RAMB18_DIBDI15", - "BRAM_LOGIC_OUTS_B2_4", - "BRAM_LH3_3", - "BRAM_IMUX11_UTURN_3", - "BRAM_WW4END1_0", - "BRAM_CASCOUT_ADDRBWRADDRU5", - "BRAM_NE4BEG2_1", - "BRAM_RAMB18_DOPBDOP1", - "BRAM_FIFO36_ADDRARDADDRU8", - "BRAM_SW4A0_2", - "BRAM_FIFO36_WRCOUNT4", - "BRAM_WL1END1_0", - "BRAM_IMUX9_UTURN_4", - "BRAM_UTURN_ADDRBWRADDRL13", - "BRAM_FIFO18_DOBDO12", - "BRAM_IMUX14_1", - "BRAM_IMUX11_0", - "BRAM_IMUX8_UTURN_2", - "BRAM_SE4BEG1_1", - "BRAM_WL1END1_1", - "BRAM_FIFO18_DOADO9", - "BRAM_FIFO18_DOBDO6", - "BRAM_ER1BEG3_3", - "BRAM_FIFO36_ADDRARDADDRL13", - "BRAM_LOGIC_OUTS_B3_4", - "BRAM_IMUX9_1", - "BRAM_WW4A1_1", - "BRAM_WL1END0_0", - "BRAM_FIFO18_WEA2", - "BRAM_IMUX46_UTURN_1", - "BRAM_BLOCK_OUTS_L_B3_2", - "BRAM_WW4A2_1", - "BRAM_FIFO36_DOADOU1", - "BRAM_ADDRARDADDRL14", - "BRAM_FIFO36_TSTWROS7", - "BRAM_FIFO36_ADDRBWRADDRU3", - "BRAM_FIFO18_DOADO13", - "BRAM_FIFO18_WEA0", - "BRAM_BLOCK_OUTS_L_B3_1", - "BRAM_BLOCK_OUTS_L_B2_2", - "BRAM_WW4C1_4", - "BRAM_IMUX40_UTURN_4", - "BRAM_FIFO18_DIADI2", - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRAM_RAMB18_DOPADOP0", - "BRAM_FIFO36_DIADIL10", - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRAM_IMUX_ADDRBWRADDRU12", - "BRAM_LOGIC_OUTS_B20_4", - "BRAM_IMUX44_UTURN_0", - "BRAM_IMUX_ADDRBWRADDRL6", - "BRAM_IMUX25_0", - "BRAM_BYP6_0", - "BRAM_IMUX22_4", - "BRAM_IMUX42_4", - "BRAM_IMUX19_1", - "BRAM_FIFO18_DOBDO4", - "BRAM_EE2A0_0", - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRAM_IMUX35_3", - "BRAM_BYP5_4", - "BRAM_IMUX9_0", - "BRAM_IMUX47_1", - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "BRAM_FIFO36_DIBDIL5", - "BRAM_IMUX3_4", - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRAM_LH6_0", - "BRAM_IMUX12_UTURN_2", - "BRAM_IMUX44_UTURN_3", - "BRAM_IMUX9_4", - "BRAM_IMUX33_UTURN_4", - "BRAM_FIFO18_DIBDI3", - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRAM_EE2A1_4", - "BRAM_IMUX19_UTURN_4", - "BRAM_ADDRARDADDRL11", - "BRAM_IMUX2_UTURN_4", - "BRAM_IMUX_ADDRBWRADDRL14", - "BRAM_RAMB18_WEBWE7", - "BRAM_IMUX36_4", - "BRAM_FIFO36_DOBDOL5", - "BRAM_ADDRBWRADDRU13", - "BRAM_IMUX1_UTURN_2", - "BRAM_IMUX1_1", - "BRAM_FIFO18_ADDRARDADDR2", - "BRAM_FIFO36_ADDRARDADDRU2", - "BRAM_UTURN_ADDRARDADDRL15", - "BRAM_ER1BEG3_2", - "BRAM_UTURN_ADDRBWRADDRL11", - "BRAM_SW4END2_3", - "BRAM_RAMB18_DIADI11", - "BRAM_LOGIC_OUTS_B12_2", - "BRAM_LH4_2", - "BRAM_RAMB18_DOADO13", - "BRAM_IMUX42_UTURN_3", - "BRAM_EE4A3_4", - "BRAM_FIFO36_ADDRARDADDRU3", - "BRAM_IMUX45_UTURN_0", - "BRAM_FIFO18_RSTRAMB", - "BRAM_FIFO18_DIBDI12", - "BRAM_IMUX13_UTURN_4", - "BRAM_LOGIC_OUTS_B0_2", - "BRAM_ADDRBWRADDRU7", - "BRAM_IMUX19_UTURN_2", - "BRAM_FIFO36_DOBDOU10", - "BRAM_IMUX35_2", - "BRAM_LOGIC_OUTS_B11_0", - "BRAM_WW2A2_1", - "BRAM_CASCOUT_ADDRARDADDRU5", - "BRAM_IMUX_ADDRARDADDRL15", - "BRAM_IMUX24_0", - "BRAM_IMUX_ADDRBWRADDRL10", - "BRAM_LH8_4", - "BRAM_ADDRBWRADDRL7", - "BRAM_FIFO36_RSTRAMBL", - "BRAM_RAMB18_ADDRARDADDR4", - "BRAM_WW2END2_0", - "BRAM_IMUX40_2", - "BRAM_FIFO36_WEAU3", - "BRAM_SW4A1_4", - "BRAM_NW4A0_0", - "BRAM_IMUX_ADDRBWRADDRU3", - "BRAM_NE4BEG0_4", - "BRAM_CTRL0_1", - "BRAM_LH12_4", - "BRAM_FIFO36_DIADIL15", - "BRAM_UTURN_ADDRBWRADDRU4", - "BRAM_ADDRARDADDRL5", - "BRAM_IMUX25_UTURN_3", - "BRAM_IMUX18_3", - "BRAM_WR1END1_0", - "BRAM_NE2A3_4", - "BRAM_LOGIC_OUTS_B22_2", - "BRAM_FIFO36_ALMOSTFULL", - "BRAM_RAMB18_ADDRARDADDR13", - "BRAM_FAN1_0", - "BRAM_FIFO18_WRCOUNT1", - "BRAM_NE4C0_0", - "BRAM_FIFO36_ADDRARDADDRU14", - "BRAM_RAMB18_DIPBDIP0", - "BRAM_EE4A2_2", - "BRAM_IMUX46_UTURN_0", - "BRAM_IMUX18_UTURN_2", - "BRAM_FIFO36_TSTCNT4", - "BRAM_LOGIC_OUTS_B13_4", - "BRAM_FIFO36_DIBDIU0", - "BRAM_FIFO36_DIBDIU2", - "BRAM_RAMB18_DIBDI12", - "BRAM_FIFO18_ADDRATIEHIGH0", - "BRAM_IMUX27_1", - "BRAM_NW4A1_2", - "BRAM_FIFO18_ENARDEN", - "BRAM_FIFO36_WRCOUNT7", - "BRAM_IMUX27_3", - "BRAM_LH8_3", - "BRAM_UTURN_ADDRBWRADDRL10", - "BRAM_BLOCK_OUTS_L_B1_1", - "BRAM_ER1BEG0_1", - "BRAM_BYP4_4", - "BRAM_BLOCK_OUTS_L_B0_2", - "BRAM_IMUX20_UTURN_2", - "BRAM_FIFO18_DOPBDOP0", - "BRAM_WW4C3_3", - "BRAM_SW4A2_2", - "BRAM_FIFO36_TSTWROS5", - "BRAM_LOGIC_OUTS_B23_4", - "BRAM_IMUX6_0", - "BRAM_LH8_2", - "BRAM_RAMB18_DIADI6", - "BRAM_IMUX5_1", - "BRAM_IMUX27_UTURN_3", - "BRAM_SE4C0_1", - "BRAM_FAN7_1", - "BRAM_IMUX39_0", - "BRAM_BYP5_1", - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRAM_LH1_3", - "BRAM_UTURN_ADDRARDADDRL12", - "BRAM_LOGIC_OUTS_B12_1", - "BRAM_IMUX27_UTURN_2", - "BRAM_FIFO36_TSTRDOS3", - "BRAM_WW4A3_3", - "BRAM_FIFO36_ADDRBWRADDRU12", - "BRAM_WL1END3_2", - "BRAM_NE4C1_2", - "BRAM_IMUX46_UTURN_3", - "BRAM_EE4C0_3", - "BRAM_IMUX36_UTURN_0", - "BRAM_FIFO36_DIBDIL6", - "BRAM_FIFO36_ALMOSTEMPTY", - "BRAM_SW2A1_2", - "BRAM_RAMB18_WRCOUNT4", - "BRAM_LOGIC_OUTS_B1_1", - "BRAM_IMUX_ADDRBWRADDRU10", - "BRAM_NW4A2_4", - "BRAM_UTURN_ADDRARDADDRL2", - "BRAM_FIFO36_ADDRBWRADDRU9", - "BRAM_EE4A0_1", - "BRAM_IMUX22_UTURN_0", - "BRAM_FIFO18_DIBDI11", - "BRAM_WW4END0_1", - "BRAM_LOGIC_OUTS_B9_0", - "BRAM_UTURN_ADDRARDADDRL9", - "BRAM_FIFO36_DOPBDOPL0", - "BRAM_MONITOR_N_1", - "BRAM_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU13", - "BRAM_FIFO36_DOBDOU12", - "BRAM_FIFO36_DIBDIL10", - "BRAM_RAMB18_WEA2", - "BRAM_BLOCK_OUTS_L_B3_3", - "BRAM_WW4END0_2", - "BRAM_ADDRBWRADDRU4", - "BRAM_FAN3_3", - "BRAM_UTURN_ADDRBWRADDRL9", - "BRAM_IMUX16_UTURN_0", - "BRAM_RAMB18_WEA3", - "BRAM_FIFO36_DOBDOL8", - "BRAM_FIFO36_DOADOL0", - "BRAM_IMUX7_UTURN_1", - "BRAM_IMUX11_1", - "BRAM_BYP1_4", - "BRAM_IMUX29_UTURN_2", - "BRAM_RAMB18_WEBWE4", - "BRAM_FIFO36_WEBWEL3", - "BRAM_FIFO18_RDCOUNT8", - "BRAM_FIFO18_DOBDO13", - "BRAM_RAMB18_RDCOUNT8", - "BRAM_EE4B0_4", - "BRAM_FIFO18_ADDRBWRADDR3", - "BRAM_LOGIC_OUTS_B23_3", - "BRAM_FIFO36_WRCOUNT11", - "BRAM_FAN1_4", - "BRAM_FAN6_3", - "BRAM_EE4A1_3", - "BRAM_BLOCK_OUTS_L_B1_3", - "BRAM_LOGIC_OUTS_B7_3", - "BRAM_LOGIC_OUTS_B1_3", - "BRAM_SE2A1_0", - "BRAM_IMUX6_UTURN_1", - "BRAM_FAN7_3", - "BRAM_FIFO36_DOADOL2", - "BRAM_NE2A3_0", - "BRAM_NE4BEG2_4", - "BRAM_NE2A3_3", - "BRAM_FAN2_4", - "BRAM_UTURN_ADDRBWRADDRU6", - "BRAM_IMUX8_UTURN_4", - "BRAM_IMUX3_1", - "BRAM_ADDRARDADDRL6", - "BRAM_WL1END2_2", - "BRAM_FIFO36_DOPBDOPU1", - "BRAM_SE2A0_2", - "BRAM_SW4A1_2", - "BRAM_BLOCK_OUTS_L_B0_4", - "BRAM_IMUX16_UTURN_1", - "BRAM_FIFO36_RDCOUNT4", - "BRAM_NW2A2_1", - "BRAM_IMUX38_UTURN_2", - "BRAM_IMUX21_UTURN_2", - "BRAM_LH1_4", - "BRAM_IMUX24_2", - "BRAM_FIFO18_DOADO15", - "BRAM_FAN4_2", - "BRAM_RAMB18_ADDRARDADDR11", - "BRAM_LOGIC_OUTS_B23_0", - "BRAM_WW2A2_3", - "BRAM_IMUX43_3", - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "BRAM_LOGIC_OUTS_B9_2", - "BRAM_SW4A3_4", - "BRAM_LOGIC_OUTS_B18_4", - "BRAM_FIFO36_DIADIU4", - "BRAM_EE2A1_0", - "BRAM_CASCOUT_ADDRARDADDRU8", - "BRAM_FIFO36_DIBDIL9", - "BRAM_IMUX0_3", - "BRAM_FIFO18_ADDRARDADDR13", - "BRAM_UTURN_ADDRBWRADDRU7", - "BRAM_IMUX_ADDRBWRADDRL7", - "BRAM_WW4C3_2", - "BRAM_FIFO36_ADDRBWRADDRU7", - "BRAM_RAMB18_ENBWREN", - "BRAM_IMUX15_UTURN_3", - "BRAM_FIFO36_TSTOUT3", - "BRAM_IMUX10_0", - "BRAM_FAN6_1", - "BRAM_FIFO36_DIADIL6", - "BRAM_SE4C0_3", - "BRAM_WW4C2_3", - "BRAM_FIFO36_CASCADEOUTA", - "BRAM_IMUX1_3", - "BRAM_IMUX10_UTURN_0", - "BRAM_FIFO36_ECCPARITY7", - "BRAM_IMUX26_UTURN_3", - "BRAM_FIFO36_TSTCNT0", - "BRAM_UTURN_ADDRBWRADDRL15", - "BRAM_IMUX_ADDRARDADDRL7", - "BRAM_WR1END3_0", - "BRAM_IMUX1_UTURN_0", - "BRAM_RAMB18_DOBDO12", - "BRAM_NW2A0_3", - "BRAM_EE2BEG3_3", - "BRAM_PMVBRAM_ODIV4", - "BRAM_IMUX5_UTURN_3", - "BRAM_FIFO18_WRCOUNT9", - "BRAM_IMUX10_3", - "BRAM_FIFO36_DIBDIU4", - "BRAM_FIFO36_TSTWROS1", - "BRAM_BYP6_4", - "BRAM_SW4A0_3", - "BRAM_CASCINBOT_ADDRARDADDRU0", - "BRAM_IMUX_ADDRBWRADDRL8", - "BRAM_LH3_1", - "BRAM_UTURN_ADDRARDADDRL1", - "BRAM_IMUX33_4", - "BRAM_WL1END3_4", - "BRAM_NW4END1_1", - "BRAM_PMVBRAM_SELECT1", - "BRAM_IMUX13_UTURN_3", - "BRAM_NE4C2_0", - "BRAM_FIFO18_RDCOUNT1", - "BRAM_IMUX30_1", - "BRAM_IMUX4_4", - "BRAM_WW4C3_4", - "BRAM_RAMB18_CLKARDCLK", - "BRAM_IMUX_ADDRARDADDRU13", - "BRAM_IMUX43_UTURN_1", - "BRAM_IMUX23_UTURN_4", - "BRAM_BYP0_4", - "BRAM_FAN1_3", - "BRAM_UTURN_ADDRBWRADDRU11", - "BRAM_SE2A2_4", - "BRAM_FIFO36_RSTREGARSTREGL", - "BRAM_IMUX25_UTURN_0", - "BRAM_FIFO18_ADDRBTIEHIGH0", - "BRAM_SE4C2_3", - "BRAM_FAN6_2", - "BRAM_UTURN_ADDRBWRADDRU9", - "BRAM_FIFO36_DOPBDOPU0", - "BRAM_FIFO18_ADDRATIEHIGH1", - "BRAM_WW4END1_4", - "BRAM_IMUX0_4", - "BRAM_IMUX18_UTURN_1", - "BRAM_FIFO36_ADDRBWRADDRL8", - "BRAM_FAN5_2", - "BRAM_WL1END3_1", - "BRAM_ADDRARDADDRL10", - "BRAM_FIFO36_CLKARDCLKL", - "BRAM_NE4BEG1_0", - "BRAM_FIFO36_RDCOUNT0", - "BRAM_CASCOUT_ADDRBWRADDRU0", - "BRAM_RAMB18_DIADI8", - "BRAM_IMUX23_UTURN_3", - "BRAM_UTURN_ADDRARDADDRU8", - "BRAM_LOGIC_OUTS_B14_0", - "BRAM_IMUX_ADDRBWRADDRU0", - "BRAM_IMUX39_2", - "BRAM_IMUX41_3", - "BRAM_FIFO18_DOBDO2", - "BRAM_BYP4_2", - "BRAM_IMUX18_UTURN_0", - "BRAM_IMUX30_3", - "BRAM_RAMB18_REGCLKARDRCLK", - "BRAM_FIFO36_ADDRBWRADDRU1", - "BRAM_RAMB18_ADDRARDADDR0", - "BRAM_FIFO36_CASCADEINB", - "BRAM_FIFO18_ADDRBWRADDR1", - "BRAM_FIFO36_TSTRDOS11", - "BRAM_BYP0_0", - "BRAM_IMUX17_0", - "BRAM_IMUX20_UTURN_3", - "BRAM_EE4B3_4", - "BRAM_FIFO36_CLKBWRCLKL", - "BRAM_LOGIC_OUTS_B17_2", - "BRAM_FIFO18_RDCOUNT3", - "BRAM_IMUX16_3", - "BRAM_FAN5_1", - "BRAM_LOGIC_OUTS_B0_3", - "BRAM_ADDRBWRADDRU9", - "BRAM_NW4END2_2", - "BRAM_FIFO36_ADDRBWRADDRU0", - "BRAM_FIFO36_DIADIU7", - "BRAM_EE4B1_0", - "BRAM_FIFO36_RDCOUNT1", - "BRAM_RAMB18_DOBDO4", - "BRAM_BYP2_1", - "BRAM_FIFO18_DIADI0", - "BRAM_BYP1_2", - "BRAM_FIFO36_DOADOU4", - "BRAM_RAMB18_DOADO3", - "BRAM_CLK0_2", - "BRAM_FIFO18_WEBWE5", - "BRAM_IMUX16_2", - "BRAM_ADDRARDADDRU1", - "BRAM_FIFO36_RSTRAMARSTRAMU" - ], - "sites": [ - { - "prefix": "RAMB36", - "y_coord": 0, - "type": "RAMBFIFO36E1", - "site_pins": { - "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", - "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", - "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", - "WEBWEL3": "BRAM_FIFO36_WEBWEL3", - "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", - "TSTWROS0": "BRAM_FIFO36_TSTWROS0", - "DOADO22": "BRAM_FIFO36_DOADOL11", - "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", - "DOBDO2": "BRAM_FIFO36_DOBDOL1", - "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", - "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", - "WEAU0": "BRAM_FIFO36_WEAU0", - "DIADI25": "BRAM_FIFO36_DIADIU12", - "DOADO20": "BRAM_FIFO36_DOADOL10", - "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", - "DIBDI26": "BRAM_FIFO36_DIBDIL13", - "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", - "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", - "DOADO15": "BRAM_FIFO36_DOADOU7", - "WEBWEU2": "BRAM_FIFO36_WEBWEU2", - "DBITERR": "BRAM_FIFO36_DBITERR", - "DIBDI15": "BRAM_FIFO36_DIBDIU7", - "DIBDI11": "BRAM_FIFO36_DIBDIU5", - "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", - "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", - "TSTWROS8": "BRAM_FIFO36_TSTWROS8", - "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", - "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", - "DOBDO31": "BRAM_FIFO36_DOBDOU15", - "DIADI20": "BRAM_FIFO36_DIADIL10", - "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", - "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", - "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", - "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", - "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", - "WEAL3": "BRAM_FIFO36_WEAL3", - "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", - "DOBDO20": "BRAM_FIFO36_DOBDOL10", - "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", - "DIADI3": "BRAM_FIFO36_DIADIU1", - "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", - "WEAL1": "BRAM_FIFO36_WEAL1", - "TSTOUT3": "BRAM_FIFO36_TSTOUT3", - "DOBDO24": "BRAM_FIFO36_DOBDOL12", - "DOADO12": "BRAM_FIFO36_DOADOL6", - "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", - "DIBDI27": "BRAM_FIFO36_DIBDIU13", - "TSTWROS9": "BRAM_FIFO36_TSTWROS9", - "ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", - "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", - "DIADI0": "BRAM_FIFO36_DIADIL0", - "DIBDI10": "BRAM_FIFO36_DIBDIL5", - "DIADI15": "BRAM_FIFO36_DIADIU7", - "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", - "DOADO27": "BRAM_FIFO36_DOADOU13", - "DOADO0": "BRAM_FIFO36_DOADOL0", - "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", - "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", - "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", - "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", - "DIADI28": "BRAM_FIFO36_DIADIL14", - "DOBDO25": "BRAM_FIFO36_DOBDOU12", - "DIBDI17": "BRAM_FIFO36_DIBDIU8", - "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", - "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", - "TSTWROS4": "BRAM_FIFO36_TSTWROS4", - "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", - "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", - "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", - "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", - "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", - "WEBWEU3": "BRAM_FIFO36_WEBWEU3", - "WEBWEU1": "BRAM_FIFO36_WEBWEU1", - "WRCOUNT8": "BRAM_FIFO36_WRCOUNT8", - "DOBDO22": "BRAM_FIFO36_DOBDOL11", - "DOBDO12": "BRAM_FIFO36_DOBDOL6", - "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", - "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", - "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", - "WRERR": "BRAM_FIFO36_WRERR", - "DOADO31": "BRAM_FIFO36_DOADOU15", - "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", - "DIBDI28": "BRAM_FIFO36_DIBDIL14", - "TSTCNT7": "BRAM_FIFO36_TSTCNT7", - "REGCEBU": "BRAM_FIFO36_REGCEBU", - "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", - "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", - "TSTCNT10": "BRAM_FIFO36_TSTCNT10", - "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", - "DOBDO1": "BRAM_FIFO36_DOBDOU0", - "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", - "TSTWROS3": "BRAM_FIFO36_TSTWROS3", - "TSTIN3": "BRAM_FIFO36_TSTIN3", - "TSTCNT0": "BRAM_FIFO36_TSTCNT0", - "DIADI18": "BRAM_FIFO36_DIADIL9", - "DIBDI9": "BRAM_FIFO36_DIBDIU4", - "WEBWEL1": "BRAM_FIFO36_WEBWEL1", - "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", - "WEBWEL7": "BRAM_FIFO36_WEBWEL7", - "TSTOFF": "BRAM_FIFO36_TSTOFF", - "DOADO11": "BRAM_FIFO36_DOADOU5", - "TSTIN2": "BRAM_FIFO36_TSTIN2", - "TSTCNT2": "BRAM_FIFO36_TSTCNT2", - "TSTWROS7": "BRAM_FIFO36_TSTWROS7", - "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", - "TSTOUT2": "BRAM_FIFO36_TSTOUT2", - "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", - "WRCOUNT9": "BRAM_FIFO36_WRCOUNT9", - "DIADI31": "BRAM_FIFO36_DIADIU15", - "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", - "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", - "DOADO3": "BRAM_FIFO36_DOADOU1", - "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", - "DOADO14": "BRAM_FIFO36_DOADOL7", - "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", - "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", - "DOADO13": "BRAM_FIFO36_DOADOU6", - "FULL": "BRAM_FIFO36_FULL", - "DOADO7": "BRAM_FIFO36_DOADOU3", - "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", - "TSTCNT4": "BRAM_FIFO36_TSTCNT4", - "DIADI11": "BRAM_FIFO36_DIADIU5", - "TSTWROS2": "BRAM_FIFO36_TSTWROS2", - "ENBWRENU": "BRAM_FIFO36_ENBWRENU", - "DIADI13": "BRAM_FIFO36_DIADIU6", - "DOBDO16": "BRAM_FIFO36_DOBDOL8", - "ENBWRENL": "BRAM_FIFO36_ENBWRENL", - "WEBWEL4": "BRAM_FIFO36_WEBWEL4", - "REGCLKBL": "BRAM_FIFO36_REGCLKBL", - "SBITERR": "BRAM_FIFO36_SBITERR", - "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", - "DIBDI4": "BRAM_FIFO36_DIBDIL2", - "DIADI5": "BRAM_FIFO36_DIADIU2", - "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", - "DOBDO13": "BRAM_FIFO36_DOBDOU6", - "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", - "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", - "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", - "WEAL0": "BRAM_FIFO36_WEAL0", - "TSTCNT12": "BRAM_FIFO36_TSTCNT12", - "DIBDI1": "BRAM_FIFO36_DIBDIU0", - "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", - "DOBDO23": "BRAM_FIFO36_DOBDOU11", - "DIBDI29": "BRAM_FIFO36_DIBDIU14", - "TSTCNT3": "BRAM_FIFO36_TSTCNT3", - "DIBDI31": "BRAM_FIFO36_DIBDIU15", - "DIBDI22": "BRAM_FIFO36_DIBDIL11", - "TSTCNT8": "BRAM_FIFO36_TSTCNT8", - "DOADO16": "BRAM_FIFO36_DOADOL8", - "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", - "DIADI19": "BRAM_FIFO36_DIADIU9", - "DOADO23": "BRAM_FIFO36_DOADOU11", - "ENARDENL": "BRAM_FIFO36_ENARDENL", - "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", - "TSTIN1": "BRAM_FIFO36_TSTIN1", - "DIBDI16": "BRAM_FIFO36_DIBDIL8", - "DOADO9": "BRAM_FIFO36_DOADOU4", - "WEBWEL2": "BRAM_FIFO36_WEBWEL2", - "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", - "DOADO28": "BRAM_FIFO36_DOADOL14", - "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", - "RSTREGBU": "BRAM_FIFO36_RSTREGBU", - "TSTCNT9": "BRAM_FIFO36_TSTCNT9", - "DIADI12": "BRAM_FIFO36_DIADIL6", - "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", - "WEBWEU4": "BRAM_FIFO36_WEBWEU4", - "DOBDO18": "BRAM_FIFO36_DOBDOL9", - "DIADI1": "BRAM_FIFO36_DIADIU0", - "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", - "RSTREGBL": "BRAM_FIFO36_RSTREGBL", - "TSTWROS11": "BRAM_FIFO36_TSTWROS11", - "DOBDO10": "BRAM_FIFO36_DOBDOL5", - "DOADO19": "BRAM_FIFO36_DOADOU9", - "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", - "DOADO5": "BRAM_FIFO36_DOADOU2", - "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", - "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", - "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", - "DIBDI14": "BRAM_FIFO36_DIBDIL7", - "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", - "DIBDI0": "BRAM_FIFO36_DIBDIL0", - "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", - "WEAU1": "BRAM_FIFO36_WEAU1", - "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", - "DOBDO19": "BRAM_FIFO36_DOBDOU9", - "DIBDI23": "BRAM_FIFO36_DIBDIU11", - "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", - "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", - "DIADI6": "BRAM_FIFO36_DIADIL3", - "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", - "DOBDO7": "BRAM_FIFO36_DOBDOU3", - "DIBDI13": "BRAM_FIFO36_DIBDIU6", - "DIBDI5": "BRAM_FIFO36_DIBDIU2", - "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", - "DIADI9": "BRAM_FIFO36_DIADIU4", - "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", - "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", - "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", - "DOADO8": "BRAM_FIFO36_DOADOL4", - "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", - "DOADO24": "BRAM_FIFO36_DOADOL12", - "REGCLKBU": "BRAM_FIFO36_REGCLKBU", - "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", - "WEBWEL0": "BRAM_FIFO36_WEBWEL0", - "TSTOUT0": "BRAM_FIFO36_TSTOUT0", - "DOBDO29": "BRAM_FIFO36_DOBDOU14", - "DOBDO28": "BRAM_FIFO36_DOBDOL14", - "DOBDO17": "BRAM_FIFO36_DOBDOU8", - "DOBDO11": "BRAM_FIFO36_DOBDOU5", - "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU", - "DIADI10": "BRAM_FIFO36_DIADIL5", - "DIBDI30": "BRAM_FIFO36_DIBDIL15", - "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", - "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", - "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", - "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", - "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", - "DIADI17": "BRAM_FIFO36_DIADIU8", - "REGCEBL": "BRAM_FIFO36_REGCEBL", - "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", - "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", - "DIBDI20": "BRAM_FIFO36_DIBDIL10", - "WEBWEL5": "BRAM_FIFO36_WEBWEL5", - "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", - "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", - "TSTCNT1": "BRAM_FIFO36_TSTCNT1", - "TSTWROS5": "BRAM_FIFO36_TSTWROS5", - "DIBDI8": "BRAM_FIFO36_DIBDIL4", - "DOADO18": "BRAM_FIFO36_DOADOL9", - "DOBDO8": "BRAM_FIFO36_DOBDOL4", - "TSTWROS12": "BRAM_FIFO36_TSTWROS12", - "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", - "DIBDI21": "BRAM_FIFO36_DIBDIU10", - "DOADO1": "BRAM_FIFO36_DOADOU0", - "TSTWROS1": "BRAM_FIFO36_TSTWROS1", - "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", - "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", - "DOBDO26": "BRAM_FIFO36_DOBDOL13", - "CASCADEINA": "BRAM_FIFO36_CASCADEINA", - "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTB", - "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", - "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", - "WEAL2": "BRAM_FIFO36_WEAL2", - "DOBDO14": "BRAM_FIFO36_DOBDOL7", - "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", - "DOBDO30": "BRAM_FIFO36_DOBDOL15", - "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", - "DOBDO3": "BRAM_FIFO36_DOBDOU1", - "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", - "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", - "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", - "DIADI21": "BRAM_FIFO36_DIADIU10", - "DOBDO9": "BRAM_FIFO36_DOBDOU4", - "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", - "WEAU2": "BRAM_FIFO36_WEAU2", - "DIBDI19": "BRAM_FIFO36_DIBDIU9", - "RDERR": "BRAM_FIFO36_RDERR", - "DIBDI7": "BRAM_FIFO36_DIBDIU3", - "DIADI26": "BRAM_FIFO36_DIADIL13", - "DOADO6": "BRAM_FIFO36_DOADOL3", - "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", - "DIADI4": "BRAM_FIFO36_DIADIL2", - "DOADO4": "BRAM_FIFO36_DOADOL2", - "DIBDI2": "BRAM_FIFO36_DIBDIL1", - "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "TSTCNT11": "BRAM_FIFO36_TSTCNT11", - "DIADI29": "BRAM_FIFO36_DIADIU14", - "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", - "DIADI23": "BRAM_FIFO36_DIADIU11", - "DIADI22": "BRAM_FIFO36_DIADIL11", - "DIBDI25": "BRAM_FIFO36_DIBDIU12", - "DIBDI18": "BRAM_FIFO36_DIBDIL9", - "TSTOUT4": "BRAM_FIFO36_TSTOUT4", - "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", - "WRCOUNT7": "BRAM_FIFO36_WRCOUNT7", - "ENARDENU": "BRAM_FIFO36_ENARDENU", - "DIADI27": "BRAM_FIFO36_DIADIU13", - "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", - "DOADO29": "BRAM_FIFO36_DOADOU14", - "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", - "WEBWEU7": "BRAM_FIFO36_WEBWEU7", - "DOADO26": "BRAM_FIFO36_DOADOL13", - "DIADI8": "BRAM_FIFO36_DIADIL4", - "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", - "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", - "TSTOUT1": "BRAM_FIFO36_TSTOUT1", - "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", - "DOBDO4": "BRAM_FIFO36_DOBDOL2", - "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", - "DOADO30": "BRAM_FIFO36_DOADOL15", - "WEAU3": "BRAM_FIFO36_WEAU3", - "DOADO25": "BRAM_FIFO36_DOADOU12", - "DIBDI6": "BRAM_FIFO36_DIBDIL3", - "DOBDO27": "BRAM_FIFO36_DOBDOU13", - "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", - "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", - "DOADO21": "BRAM_FIFO36_DOADOU10", - "TSTIN4": "BRAM_FIFO36_TSTIN4", - "DIADI16": "BRAM_FIFO36_DIADIL8", - "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", - "WEBWEU5": "BRAM_FIFO36_WEBWEU5", - "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", - "TSTCNT6": "BRAM_FIFO36_TSTCNT6", - "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", - "WEBWEU0": "BRAM_FIFO36_WEBWEU0", - "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", - "TSTWROS6": "BRAM_FIFO36_TSTWROS6", - "DIBDI24": "BRAM_FIFO36_DIBDIL12", - "DOBDO6": "BRAM_FIFO36_DOBDOL3", - "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTA", - "DOADO17": "BRAM_FIFO36_DOADOU8", - "DOBDO5": "BRAM_FIFO36_DOBDOU2", - "DIADI30": "BRAM_FIFO36_DIADIL15", - "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", - "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", - "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", - "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", - "CASCADEINB": "BRAM_FIFO36_CASCADEINB", - "EMPTY": "BRAM_FIFO36_EMPTY", - "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", - "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", - "DIADI24": "BRAM_FIFO36_DIADIL12", - "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", - "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", - "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", - "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", - "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", - "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", - "DOADO2": "BRAM_FIFO36_DOADOL1", - "DIBDI3": "BRAM_FIFO36_DIBDIU1", - "DOADO10": "BRAM_FIFO36_DOADOL5", - "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", - "DIBDI12": "BRAM_FIFO36_DIBDIL6", - "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", - "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", - "WEBWEL6": "BRAM_FIFO36_WEBWEL6", - "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", - "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", - "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", - "DOBDO0": "BRAM_FIFO36_DOBDOL0", - "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", - "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", - "WEBWEU6": "BRAM_FIFO36_WEBWEU6", - "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", - "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", - "DOBDO21": "BRAM_FIFO36_DOBDOU10", - "TSTCNT5": "BRAM_FIFO36_TSTCNT5", - "DIADI2": "BRAM_FIFO36_DIADIL1", - "DIADI14": "BRAM_FIFO36_DIADIL7", - "DIADI7": "BRAM_FIFO36_DIADIU3", - "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", - "DOBDO15": "BRAM_FIFO36_DOBDOU7", - "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", - "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", - "TSTIN0": "BRAM_FIFO36_TSTIN0", - "TSTWROS10": "BRAM_FIFO36_TSTWROS10" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "RAMB18", - "y_coord": 29, - "type": "FIFO18E1", - "site_pins": { - "WEA1": "BRAM_FIFO18_WEA1", - "DIBDI5": "BRAM_FIFO18_DIBDI5", - "DIBDI9": "BRAM_FIFO18_DIBDI9", - "DIBDI13": "BRAM_FIFO18_DIBDI13", - "DO17": "BRAM_FIFO18_DOBDO1", - "DO0": "BRAM_FIFO18_DOADO0", - "DO23": "BRAM_FIFO18_DOBDO7", - "DIBDI15": "BRAM_FIFO18_DIBDI15", - "DIADI9": "BRAM_FIFO18_DIADI9", - "DO18": "BRAM_FIFO18_DOBDO2", - "DIADI5": "BRAM_FIFO18_DIADI5", - "DOP3": "BRAM_FIFO18_DOPBDOP1", - "DO8": "BRAM_FIFO18_DOADO8", - "DO26": "BRAM_FIFO18_DOBDO10", - "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", - "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", - "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", - "DIADI8": "BRAM_FIFO18_DIADI8", - "RDCLK": "BRAM_FIFO18_CLKARDCLK", - "WRCOUNT9": "BRAM_FIFO18_WRCOUNT9", - "DO25": "BRAM_FIFO18_DOBDO9", - "DO28": "BRAM_FIFO18_DOBDO12", - "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", - "REGCLKB": "BRAM_FIFO18_REGCLKB", - "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", - "DIBDI14": "BRAM_FIFO18_DIBDI14", - "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", - "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", - "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", - "RSTREGB": "BRAM_FIFO18_RSTREGB", - "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", - "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", - "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", - "DIADI7": "BRAM_FIFO18_DIADI7", - "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", - "FULL": "BRAM_FIFO18_FULL", - "DO12": "BRAM_FIFO18_DOADO12", - "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", - "DIBDI6": "BRAM_FIFO18_DIBDI6", - "WEBWE0": "BRAM_FIFO18_WEBWE0", - "DO20": "BRAM_FIFO18_DOBDO4", - "DO15": "BRAM_FIFO18_DOADO15", - "WRCOUNT10": "BRAM_FIFO18_WRCOUNT10", - "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", - "DO5": "BRAM_FIFO18_DOADO5", - "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", - "DIADI11": "BRAM_FIFO18_DIADI11", - "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", - "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", - "DIADI10": "BRAM_FIFO18_DIADI10", - "RDEN": "BRAM_FIFO18_ENARDEN", - "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", - "WRCOUNT11": "BRAM_FIFO18_WRCOUNT11", - "DO24": "BRAM_FIFO18_DOBDO8", - "DIADI1": "BRAM_FIFO18_DIADI1", - "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", - "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", - "DO14": "BRAM_FIFO18_DOADO14", - "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", - "WRCOUNT4": "BRAM_FIFO18_WRCOUNT4", - "WEBWE2": "BRAM_FIFO18_WEBWE2", - "WREN": "BRAM_FIFO18_ENBWREN", - "WEBWE7": "BRAM_FIFO18_WEBWE7", - "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", - "DIPADIP0": "BRAM_FIFO18_DIPADIP0", - "DIADI3": "BRAM_FIFO18_DIADI3", - "WRCOUNT6": "BRAM_FIFO18_WRCOUNT6", - "WEA3": "BRAM_FIFO18_WEA3", - "WEBWE3": "BRAM_FIFO18_WEBWE3", - "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", - "EMPTY": "BRAM_FIFO18_EMPTY", - "WEBWE5": "BRAM_FIFO18_WEBWE5", - "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", - "DIBDI8": "BRAM_FIFO18_DIBDI8", - "DO9": "BRAM_FIFO18_DOADO9", - "REGCE": "BRAM_FIFO18_REGCEAREGCE", - "DIBDI1": "BRAM_FIFO18_DIBDI1", - "WEBWE4": "BRAM_FIFO18_WEBWE4", - "RDERR": "BRAM_FIFO18_RDERR", - "DO4": "BRAM_FIFO18_DOADO4", - "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", - "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", - "DO29": "BRAM_FIFO18_DOBDO13", - "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", - "WRCOUNT0": "BRAM_FIFO18_WRCOUNT0", - "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", - "DO10": "BRAM_FIFO18_DOADO10", - "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", - "DIADI0": "BRAM_FIFO18_DIADI0", - "DIBDI10": "BRAM_FIFO18_DIBDI10", - "DIADI15": "BRAM_FIFO18_DIADI15", - "DIADI13": "BRAM_FIFO18_DIADI13", - "WEA0": "BRAM_FIFO18_WEA0", - "DO11": "BRAM_FIFO18_DOADO11", - "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", - "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", - "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", - "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", - "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", - "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", - "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", - "WEBWE1": "BRAM_FIFO18_WEBWE1", - "DIBDI4": "BRAM_FIFO18_DIBDI4", - "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", - "WRCOUNT5": "BRAM_FIFO18_WRCOUNT5", - "DO6": "BRAM_FIFO18_DOADO6", - "DIBDI12": "BRAM_FIFO18_DIBDI12", - "WEBWE6": "BRAM_FIFO18_WEBWE6", - "DO1": "BRAM_FIFO18_DOADO1", - "DOP2": "BRAM_FIFO18_DOPBDOP0", - "DO16": "BRAM_FIFO18_DOBDO0", - "WRCOUNT2": "BRAM_FIFO18_WRCOUNT2", - "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", - "DO19": "BRAM_FIFO18_DOBDO3", - "DIADI12": "BRAM_FIFO18_DIADI12", - "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", - "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", - "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", - "WRCOUNT1": "BRAM_FIFO18_WRCOUNT1", - "REGCEB": "BRAM_FIFO18_REGCEB", - "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", - "WEA2": "BRAM_FIFO18_WEA2", - "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", - "DO21": "BRAM_FIFO18_DOBDO5", - "WRCOUNT8": "BRAM_FIFO18_WRCOUNT8", - "DO7": "BRAM_FIFO18_DOADO7", - "DO22": "BRAM_FIFO18_DOBDO6", - "DO30": "BRAM_FIFO18_DOBDO14", - "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", - "DIBDI7": "BRAM_FIFO18_DIBDI7", - "ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0", - "DOP0": "BRAM_FIFO18_DOPADOP0", - "DIADI4": "BRAM_FIFO18_DIADI4", - "WRERR": "BRAM_FIFO18_WRERR", - "DIBDI2": "BRAM_FIFO18_DIBDI2", - "DIBDI11": "BRAM_FIFO18_DIBDI11", - "DO2": "BRAM_FIFO18_DOADO2", - "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", - "DO31": "BRAM_FIFO18_DOBDO15", - "DIPADIP1": "BRAM_FIFO18_DIPADIP1", - "DIADI2": "BRAM_FIFO18_DIADI2", - "DIADI14": "BRAM_FIFO18_DIADI14", - "WRCLK": "BRAM_FIFO18_CLKBWRCLK", - "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", - "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", - "DO3": "BRAM_FIFO18_DOADO3", - "DO27": "BRAM_FIFO18_DOBDO11", - "DOP1": "BRAM_FIFO18_DOPADOP1", - "DIADI6": "BRAM_FIFO18_DIADI6", - "DIBDI3": "BRAM_FIFO18_DIBDI3", - "WRCOUNT3": "BRAM_FIFO18_WRCOUNT3", - "RSTRAMB": "BRAM_FIFO18_RSTRAMB", - "DIBDI0": "BRAM_FIFO18_DIBDI0", - "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12", - "DO13": "BRAM_FIFO18_DOADO13", - "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", - "WRCOUNT7": "BRAM_FIFO18_WRCOUNT7", - "RST": "BRAM_FIFO18_RSTRAMARSTRAM" - }, - "x_coord": 0, - "name": "X0Y29" - }, - { - "prefix": "RAMB18", - "y_coord": 30, - "type": "RAMB18E1", - "site_pins": { - "WEA1": "BRAM_RAMB18_WEA1", - "DOBDO7": "BRAM_RAMB18_DOBDO7", - "DIBDI9": "BRAM_RAMB18_DIBDI9", - "DIBDI13": "BRAM_RAMB18_DIBDI13", - "DIBDI5": "BRAM_RAMB18_DIBDI5", - "DIBDI15": "BRAM_RAMB18_DIBDI15", - "DIADI9": "BRAM_RAMB18_DIADI9", - "DOBDO11": "BRAM_RAMB18_DOBDO11", - "DIADI5": "BRAM_RAMB18_DIADI5", - "ADDRBWRADDR0": "BRAM_RAMB18_ADDRBWRADDR0", - "WRCOUNT0": "BRAM_RAMB18_WRCOUNT0", - "DOADO14": "BRAM_RAMB18_DOADO14", - "ADDRBWRADDR11": "BRAM_RAMB18_ADDRBWRADDR11", - "DOBDO2": "BRAM_RAMB18_DOBDO2", - "DIADI8": "BRAM_RAMB18_DIADI8", - "WRCOUNT9": "BRAM_RAMB18_WRCOUNT9", - "DOADO8": "BRAM_RAMB18_DOADO8", - "ADDRARDADDR12": "BRAM_RAMB18_ADDRARDADDR12", - "DOPADOP0": "BRAM_RAMB18_DOPADOP0", - "REGCLKB": "BRAM_RAMB18_REGCLKB", - "RDERR": "BRAM_RAMB18_RDERR", - "DIBDI14": "BRAM_RAMB18_DIBDI14", - "ADDRBTIEHIGH1": "BRAM_RAMB18_ADDRBTIEHIGH1", - "ADDRBWRADDR2": "BRAM_RAMB18_ADDRBWRADDR2", - "RDCOUNT6": "BRAM_RAMB18_RDCOUNT6", - "DOADO15": "BRAM_RAMB18_DOADO15", - "DOADO3": "BRAM_RAMB18_DOADO3", - "ADDRARDADDR7": "BRAM_RAMB18_ADDRARDADDR7", - "EMPTY": "BRAM_RAMB18_EMPTY", - "ADDRBWRADDR13": "BRAM_RAMB18_ADDRBWRADDR13", - "RDCOUNT11": "BRAM_RAMB18_RDCOUNT11", - "DOBDO4": "BRAM_RAMB18_DOBDO4", - "ADDRATIEHIGH1": "BRAM_RAMB18_ADDRATIEHIGH1", - "FULL": "BRAM_RAMB18_FULL", - "DOADO7": "BRAM_RAMB18_DOADO7", - "ADDRBWRADDR3": "BRAM_RAMB18_ADDRBWRADDR3", - "DIBDI6": "BRAM_RAMB18_DIBDI6", - "WEBWE0": "BRAM_RAMB18_WEBWE0", - "DOADO11": "BRAM_RAMB18_DOADO11", - "ADDRARDADDR3": "BRAM_RAMB18_ADDRARDADDR3", - "CLKARDCLK": "BRAM_RAMB18_CLKARDCLK", - "DIADI11": "BRAM_RAMB18_DIADI11", - "ADDRARDADDR5": "BRAM_RAMB18_ADDRARDADDR5", - "DIADI10": "BRAM_RAMB18_DIADI10", - "DIADI15": "BRAM_RAMB18_DIADI15", - "DOBDO10": "BRAM_RAMB18_DOBDO10", - "WRCOUNT11": "BRAM_RAMB18_WRCOUNT11", - "DOADO10": "BRAM_RAMB18_DOADO10", - "ENARDEN": "BRAM_RAMB18_ENARDEN", - "DIADI2": "BRAM_RAMB18_DIADI2", - "DOPBDOP0": "BRAM_RAMB18_DOPBDOP0", - "REGCLKARDRCLK": "BRAM_RAMB18_REGCLKARDRCLK", - "ADDRBWRADDR12": "BRAM_RAMB18_ADDRBWRADDR12", - "RDCOUNT0": "BRAM_RAMB18_RDCOUNT0", - "WRCOUNT4": "BRAM_RAMB18_WRCOUNT4", - "WEBWE2": "BRAM_RAMB18_WEBWE2", - "WEBWE7": "BRAM_RAMB18_WEBWE7", - "ADDRBWRADDR7": "BRAM_RAMB18_ADDRBWRADDR7", - "DIPADIP0": "BRAM_RAMB18_DIPADIP0", - "DIBDI4": "BRAM_RAMB18_DIBDI4", - "DIADI3": "BRAM_RAMB18_DIADI3", - "WRCOUNT6": "BRAM_RAMB18_WRCOUNT6", - "WEA3": "BRAM_RAMB18_WEA3", - "ADDRARDADDR10": "BRAM_RAMB18_ADDRARDADDR10", - "DOBDO13": "BRAM_RAMB18_DOBDO13", - "WEBWE5": "BRAM_RAMB18_WEBWE5", - "ADDRATIEHIGH0": "BRAM_RAMB18_ADDRATIEHIGH0", - "RDCOUNT9": "BRAM_RAMB18_RDCOUNT9", - "DOADO12": "BRAM_RAMB18_DOADO12", - "DOBDO5": "BRAM_RAMB18_DOBDO5", - "WRCOUNT10": "BRAM_RAMB18_WRCOUNT10", - "DOBDO12": "BRAM_RAMB18_DOBDO12", - "WEBWE4": "BRAM_RAMB18_WEBWE4", - "ADDRBTIEHIGH0": "BRAM_RAMB18_ADDRBTIEHIGH0", - "DOBDO9": "BRAM_RAMB18_DOBDO9", - "DOBDO8": "BRAM_RAMB18_DOBDO8", - "ADDRBWRADDR8": "BRAM_RAMB18_ADDRBWRADDR8", - "ADDRARDADDR6": "BRAM_RAMB18_ADDRARDADDR6", - "DIPBDIP0": "BRAM_RAMB18_DIPBDIP0", - "ENBWREN": "BRAM_RAMB18_ENBWREN", - "RDCOUNT2": "BRAM_RAMB18_RDCOUNT2", - "RDCOUNT8": "BRAM_RAMB18_RDCOUNT8", - "ADDRBWRADDR6": "BRAM_RAMB18_ADDRBWRADDR6", - "DOADO13": "BRAM_RAMB18_DOADO13", - "DIADI0": "BRAM_RAMB18_DIADI0", - "DIBDI10": "BRAM_RAMB18_DIBDI10", - "DOADO1": "BRAM_RAMB18_DOADO1", - "DIADI13": "BRAM_RAMB18_DIADI13", - "WEA0": "BRAM_RAMB18_WEA0", - "DOADO0": "BRAM_RAMB18_DOADO0", - "RDCOUNT3": "BRAM_RAMB18_RDCOUNT3", - "ALMOSTFULL": "BRAM_RAMB18_ALMOSTFULL", - "ADDRARDADDR13": "BRAM_RAMB18_ADDRARDADDR13", - "DOPADOP1": "BRAM_RAMB18_DOPADOP1", - "RDCOUNT7": "BRAM_RAMB18_RDCOUNT7", - "RDCOUNT4": "BRAM_RAMB18_RDCOUNT4", - "ALMOSTEMPTY": "BRAM_RAMB18_ALMOSTEMPTY", - "ADDRBWRADDR9": "BRAM_RAMB18_ADDRBWRADDR9", - "WEBWE1": "BRAM_RAMB18_WEBWE1", - "DOADO9": "BRAM_RAMB18_DOADO9", - "ADDRARDADDR11": "BRAM_RAMB18_ADDRARDADDR11", - "WRCOUNT5": "BRAM_RAMB18_WRCOUNT5", - "DOPBDOP1": "BRAM_RAMB18_DOPBDOP1", - "DIBDI12": "BRAM_RAMB18_DIBDI12", - "WEBWE6": "BRAM_RAMB18_WEBWE6", - "ADDRARDADDR9": "BRAM_RAMB18_ADDRARDADDR9", - "ADDRARDADDR2": "BRAM_RAMB18_ADDRARDADDR2", - "DOADO2": "BRAM_RAMB18_DOADO2", - "REGCEAREGCE": "BRAM_RAMB18_REGCEAREGCE", - "DOBDO14": "BRAM_RAMB18_DOBDO14", - "DIBDI8": "BRAM_RAMB18_DIBDI8", - "WRCOUNT2": "BRAM_RAMB18_WRCOUNT2", - "ADDRBWRADDR5": "BRAM_RAMB18_ADDRBWRADDR5", - "CLKBWRCLK": "BRAM_RAMB18_CLKBWRCLK", - "DIADI12": "BRAM_RAMB18_DIADI12", - "RDCOUNT5": "BRAM_RAMB18_RDCOUNT5", - "DOBDO3": "BRAM_RAMB18_DOBDO3", - "WRCOUNT1": "BRAM_RAMB18_WRCOUNT1", - "REGCEB": "BRAM_RAMB18_REGCEB", - "DIADI1": "BRAM_RAMB18_DIADI1", - "WEA2": "BRAM_RAMB18_WEA2", - "ADDRARDADDR8": "BRAM_RAMB18_ADDRARDADDR8", - "WRCOUNT8": "BRAM_RAMB18_WRCOUNT8", - "DIBDI1": "BRAM_RAMB18_DIBDI1", - "DOBDO0": "BRAM_RAMB18_DOBDO0", - "DOBDO6": "BRAM_RAMB18_DOBDO6", - "ADDRBWRADDR1": "BRAM_RAMB18_ADDRBWRADDR1", - "DIBDI7": "BRAM_RAMB18_DIBDI7", - "ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0", - "DOADO5": "BRAM_RAMB18_DOADO5", - "DOADO6": "BRAM_RAMB18_DOADO6", - "DIADI4": "BRAM_RAMB18_DIADI4", - "WRERR": "BRAM_RAMB18_WRERR", - "DOADO4": "BRAM_RAMB18_DOADO4", - "DIBDI2": "BRAM_RAMB18_DIBDI2", - "DIBDI11": "BRAM_RAMB18_DIBDI11", - "DIBDI0": "BRAM_RAMB18_DIBDI0", - "ADDRBWRADDR4": "BRAM_RAMB18_ADDRBWRADDR4", - "DIPBDIP1": "BRAM_RAMB18_DIPBDIP1", - "RDCOUNT10": "BRAM_RAMB18_RDCOUNT10", - "DIPADIP1": "BRAM_RAMB18_DIPADIP1", - "DIADI14": "BRAM_RAMB18_DIADI14", - "RDCOUNT1": "BRAM_RAMB18_RDCOUNT1", - "ADDRARDADDR1": "BRAM_RAMB18_ADDRARDADDR1", - "DIADI7": "BRAM_RAMB18_DIADI7", - "WEBWE3": "BRAM_RAMB18_WEBWE3", - "DOBDO1": "BRAM_RAMB18_DOBDO1", - "RSTRAMARSTRAM": "BRAM_RAMB18_RSTRAMARSTRAM", - "RSTREGARSTREG": "BRAM_RAMB18_RSTREGARSTREG", - "DIBDI3": "BRAM_RAMB18_DIBDI3", - "WRCOUNT3": "BRAM_RAMB18_WRCOUNT3", - "DOBDO15": "BRAM_RAMB18_DOBDO15", - "RSTRAMB": "BRAM_RAMB18_RSTRAMB", - "DIADI6": "BRAM_RAMB18_DIADI6", - "RSTREGB": "BRAM_RAMB18_RSTREGB", - "ADDRBWRADDR10": "BRAM_RAMB18_ADDRBWRADDR10", - "ADDRARDADDR4": "BRAM_RAMB18_ADDRARDADDR4", - "WRCOUNT7": "BRAM_RAMB18_WRCOUNT7" - }, - "x_coord": 0, - "name": "X0Y30" - } - ], "pips": { - "BRAM_L.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_FIFO18_ADDRBWRADDR4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_REGCEAREGCE", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_CASCOUT_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX27_1->BRAM_IMUX_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOPADOP0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_CASCOUT_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL8", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_CASCOUT_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI10", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_CASCOUT_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_REGCEB", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_UTURN_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT5", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_FIFO36_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT9", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI10", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_RAMB18_ADDRARDADDR8": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX28_3->BRAM_IMUX_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI15", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_RAMB18_ADDRBWRADDR12": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_FIFO36_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_RSTRAMB", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPBDIPU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_RAMB18_ADDRARDADDR6": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEA2", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_FIFO36_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CLKBWRCLKU", - "is_directional": "1", - "src_wire": "BRAM_CLK1_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_FIFO18_ADDRBWRADDR12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_FIFO36_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_INJECTSBITERR", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI9", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_FULL", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_FIFO18_ADDRARDADDR1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_FIFO18_ADDRARDADDR5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_FIFO36_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_CASCOUT_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI1", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI11", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_UTURN_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI14", - "is_directional": "1", - "src_wire": "BRAM_IMUX7_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_RAMB18_ADDRBWRADDR5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX17_1->BRAM_IMUX_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI6", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI3", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_CASCOUT_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI1", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_CASCOUT_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX36_2->BRAM_IMUX_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_UTURN_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_RSTRAMB", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTOFF", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX12_3->BRAM_IMUX_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_FIFO18_ADDRBTIEHIGH0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE6", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDERR", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_CASCOUT_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_FIFO18_ADDRARDADDR12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN4", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_RAMB18_ADDRBWRADDR7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX41_4->BRAM_FIFO36_TSTWROS7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS7", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CLKBWRCLKL", - "is_directional": "1", - "src_wire": "BRAM_CLK0_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEA0", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ALMOSTEMPTY", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI6", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX19_1->BRAM_IMUX_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPBDOPL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_UTURN_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_FIFO36_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI0", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_CASCADEOUTB", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_UTURN_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI4", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_FIFO36_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE2", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_RAMB18_ADDRATIEHIGH0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS7", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_FIFO36_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_FIFO36_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_UTURN_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTREGBU", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI10", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_FIFO18_ADDRBWRADDR0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS6", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT3", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_FIFO36_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_CLKARDCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK0_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_FIFO36_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_EMPTY", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX11_3->BRAM_IMUX_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT7", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_RAMB18_ADDRBWRADDR0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX27_3->BRAM_IMUX_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTBRAMRST", - "is_directional": "1", - "src_wire": "BRAM_IMUX0_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_FIFO36_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX21_1->BRAM_IMUX_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_FIFO18_ADDRBWRADDR10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI7", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_RAMB18_ADDRBTIEHIGH0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO36_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_FIFO36_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_UTURN_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_RSTREGB", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_UTURN_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT12", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPADIPL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI8", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_RAMB18_ADDRBWRADDR1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_CASCOUT_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX22_1->BRAM_IMUX_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU", - "is_directional": "1", - "src_wire": "BRAM_CLK1_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_UTURN_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_UTURN_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPBDOPU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_FIFO36_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_FIFO36_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_CASCOUT_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT8", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIPADIP1", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_RAMB18_ADDRARDADDR2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_RAMB18_ADDRARDADDR0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_UTURN_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_FIFO36_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_UTURN_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_RAMB18_ADDRARDADDR7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_CLKBWRCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK0_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_RAMB18_ADDRARDADDR11": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE7", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI15", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI5", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE0", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX20_2->BRAM_IMUX_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCEAREGCEU", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_REGCEB", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_FIFO36_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ENBWREN", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_UTURN_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI5", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS2", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOPBDOP1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_UTURN_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIPBDIP0", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPBDOPU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPADIPU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_BYP3_2->BRAM_FIFO36_WEBWEL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL3", - "is_directional": "1", - "src_wire": "BRAM_BYP3_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_FIFO36_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS10", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX37_1->BRAM_IMUX_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX37_3->BRAM_IMUX_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX14_3->BRAM_IMUX_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI12", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_ALMOSTEMPTY", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI13", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_UTURN_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEA3", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_REGCLKB", - "is_directional": "1", - "src_wire": "BRAM_CLK1_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL", - "is_directional": "1", - "src_wire": "BRAM_CLK0_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS8", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_CASCOUT_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN3", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_FIFO36_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS11", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ENBWREN", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_UTURN_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_CASCOUT_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS1", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIPADIP0", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS1", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_FIFO36_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_RAMB18_ADDRBWRADDR4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU15", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI14", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_UTURN_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_FULL", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX31_3->BRAM_IMUX_ADDRARDADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_FIFO36_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI9", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI8", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_UTURN_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_UTURN_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_FIFO18_ADDRBWRADDR8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_FIFO36_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK1_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DBITERR", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_UTURN_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_FIFO18_ADDRARDADDR2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI6", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_UTURN_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI15", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX23_1->BRAM_IMUX_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_FIFO36_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS0", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_RSTREGARSTREG", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_UTURN_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTREGBL", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX9_3->BRAM_IMUX_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_UTURN_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX29_1->BRAM_IMUX_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ENARDENL", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPADOPL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX17_3->BRAM_IMUX_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_RAMB18_ADDRARDADDR9": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_FIFO36_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE2", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_RAMB18_ADDRBWRADDR8": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_UTURN_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_FIFO18_ADDRBWRADDR6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPBDIPU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX39_3->BRAM_IMUX_ADDRBWRADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_3", - "is_pseudo": "0" - }, "BRAM_L.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_4", - "is_directional": "1", "src_wire": "BRAM_RAMB18_DOBDO4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS10", "is_directional": "1", - "src_wire": "BRAM_IMUX36_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX32_3->BRAM_IMUX_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_FIFO36_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_UTURN_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_UTURN_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX14_1->BRAM_IMUX_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI9", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ENARDENU", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_FIFO36_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX22_3->BRAM_IMUX_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX28_1->BRAM_IMUX_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE5", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI13", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI12", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT4", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX11_1->BRAM_IMUX_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI7", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI0", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_UTURN_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI2", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CLKARDCLKL", - "is_directional": "1", - "src_wire": "BRAM_CLK0_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX13_1->BRAM_IMUX_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_2", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX13_3->BRAM_IMUX_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_CLKARDCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK1_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_FIFO36_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_CASCOUT_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRERR", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_BYP6_2->BRAM_FIFO36_WEBWEL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL7", - "is_directional": "1", - "src_wire": "BRAM_BYP6_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX21_3->BRAM_IMUX_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_RAMB18_ADDRARDADDR12": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_FIFO36_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS5", - "is_directional": "1", - "src_wire": "BRAM_IMUX47_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_CASCOUT_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI5", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX38_3->BRAM_IMUX_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_CASCADEOUTA", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_FIFO18_ADDRARDADDR8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI4", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_FIFO18_ADDRARDADDR4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI0", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_FIFO36_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX15_1->BRAM_IMUX_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ALMOSTFULL", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_RSTREGARSTREG", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_UTURN_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_UTURN_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTRAMBU", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_FIFO18_ADDRBWRADDR9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX10_1->BRAM_IMUX_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX19_3->BRAM_IMUX_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOPBDOP1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX20_3->BRAM_IMUX_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIPBDIP1", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_UTURN_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI4", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_EMPTY", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ENBWRENL", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_UTURN_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX16_3->BRAM_IMUX_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_FIFO36_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX26_3->BRAM_IMUX_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_CASCOUT_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_UTURN_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIPADIP0", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_FIFO18_ADDRBWRADDR1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCEAREGCEL", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_UTURN_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_UTURN_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_FIFO36_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_FIFO18_ADDRARDADDR11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOPADOP1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX38_1->BRAM_IMUX_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_FIFO18_ADDRARDADDR6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN1", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_CASCOUT_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEA0", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_CASCOUT_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX30_3->BRAM_IMUX_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_FIFO36_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_REGCLKB", - "is_directional": "1", - "src_wire": "BRAM_CLK0_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_RAMB18_ADDRBWRADDR6": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU0", - "is_directional": "1", - "src_wire": "BRAM_FAN5_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX28_2->BRAM_IMUX_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI1", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI14", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI14", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_UTURN_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI2", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT1", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT0", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_FIFO36_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_FIFO36_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX39_1->BRAM_IMUX_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_CASCOUT_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_FIFO36_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_FIFO36_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX30_1->BRAM_IMUX_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT2", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_FIFO36_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI13", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_CASCOUT_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_CASCOUT_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_UTURN_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_CASCOUT_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT6", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOPBDOP0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI3", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTFLAGIN", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPADOPU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE4", - "is_directional": "1", - "src_wire": "BRAM_FAN1_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_FIFO18_ADDRBWRADDR11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS2", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS12", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIPBDIP1", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEA3", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_FIFO36_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_UTURN_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_CASCOUT_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_SBITERR", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_RAMB18_ADDRARDADDR5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCLKBL", - "is_directional": "1", - "src_wire": "BRAM_CLK0_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_FIFO18_ADDRARDADDR13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDERR", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_UTURN_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX36_1->BRAM_IMUX_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO18_ADDRARDADDR0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIPBDIP0", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_FIFO36_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI2", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEA1", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_BYP3_2->BRAM_FIFO18_WEBWE3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE3", - "is_directional": "1", - "src_wire": "BRAM_BYP3_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI7", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_UTURN_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCEBU", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_UTURN_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE4", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_UTURN_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ENARDEN", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_CASCOUT_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_CASCOUT_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPADOPL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI12", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_RAMB18_ADDRARDADDR10": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI3", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_RAMB18_ADDRARDADDR1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE1", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT10", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI6", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU9", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX33_1->BRAM_IMUX_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_UTURN_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX9_1->BRAM_IMUX_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX24_3->BRAM_IMUX_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIPADIP1", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX12_1->BRAM_IMUX_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI5", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS12", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPADOPU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_FIFO36_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI13", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_UTURN_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_FIFO36_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX36_3->BRAM_IMUX_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX25_3->BRAM_IMUX_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_ALMOSTFULL", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_UTURN_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE1", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ENARDEN", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_RSTREGB", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX18_1->BRAM_IMUX_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_RAMB18_ADDRBWRADDR2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_UTURN_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE3", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE5", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_FIFO36_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI0", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_FIFO36_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPBDOPL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_UTURN_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_FIFO18_ADDRBWRADDR13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_UTURN_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_CASCOUT_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOPBDOP0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL8", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_FIFO36_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI11", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_INJECTDBITERR", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_CASCOUT_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_UTURN_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_FIFO18_ADDRARDADDR7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_REGCEAREGCE", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX10_3->BRAM_IMUX_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS0", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX8_3->BRAM_IMUX_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_RAMB18_ADDRARDADDR13": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_UTURN_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_CLKBWRCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK1_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ENBWRENU", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX35_1->BRAM_IMUX_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI12", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_CASCOUT_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_4" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU12", - "is_directional": "1", "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS4", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_FIFO18_ADDRARDADDR3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_UTURN_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_UTURN_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI2", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS6", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_FIFO18_ADDRBWRADDR3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS9", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_FIFO36_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CLKARDCLKU", - "is_directional": "1", - "src_wire": "BRAM_CLK1_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_UTURN_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI8", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_FIFO36_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12" }, "BRAM_L.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT11", - "is_directional": "1", "src_wire": "BRAM_IMUX29_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO36_ADDRARDADDRL1": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL1", "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT11" }, - "BRAM_L.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU14", "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14" }, - "BRAM_L.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { + "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_FIFO36_ADDRARDADDRU8": { + "src_wire": "BRAM_ADDRARDADDRU8", "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE0", "is_directional": "1", - "src_wire": "BRAM_FAN5_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU8" }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_RAMB18_ADDRARDADDR13": { + "src_wire": "BRAM_ADDRARDADDRU14", "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR13" }, - "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_FIFO18_ADDRARDADDR9": { + "BRAM_L.BRAM_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL3", "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR9", "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3" }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { + "BRAM_L.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { + "src_wire": "BRAM_IMUX16_4", "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOPADOP1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI1", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEA2", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN2", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_FIFO36_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPADIPL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPBDIPL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_FIFO36_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL9", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_RAMB18_ADDRBWRADDR9": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_FIFO36_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEA1", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_RAMB18_ADDRBWRADDR3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRL5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI4" }, "BRAM_L.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS3", - "is_directional": "1", "src_wire": "BRAM_IMUX45_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS3" }, - "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_UTURN_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_CASCOUT_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX35_3->BRAM_IMUX_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_FIFO36_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI15", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX34_3->BRAM_IMUX_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_RAMB18_ADDRBWRADDR10": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_FIFO36_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI8", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_UTURN_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX33_3->BRAM_IMUX_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX26_1->BRAM_IMUX_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_UTURN_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU9", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_RAMB18_ADDRBWRADDR13": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX29_3->BRAM_IMUX_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS4", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPBDIPL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_FIFO36_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI11", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI10", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_FIFO36_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS8", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL14", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS11", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI11", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_UTURN_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_RAMB18_ADDRARDADDR4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRERR", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL14", - "is_directional": "1", - "src_wire": "BRAM_IMUX7_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS3", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCEBL", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO18_ADDRATIEHIGH0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_FIFO18_ADDRARDADDR10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR10", - "is_directional": "1", + "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_UTURN_ADDRARDADDRL11": { "src_wire": "BRAM_ADDRARDADDRL11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL5", "is_directional": "1", - "src_wire": "BRAM_IMUX22_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX25_1->BRAM_IMUX_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI9", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_FIFO36_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOPADOP0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_FIFO36_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_FIFO18_ADDRBWRADDR2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX18_3->BRAM_IMUX_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_FIFO18_ADDRBWRADDR7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX20_1->BRAM_IMUX_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI4", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK0_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT8", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS5", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO15", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU4", - "is_directional": "1", - "src_wire": "BRAM_FAN1_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_FIFO18_ADDRBWRADDR5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL6", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCLKBU", - "is_directional": "1", - "src_wire": "BRAM_CLK1_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE6", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_RAMB18_ADDRARDADDR3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI3", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN0", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_4", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX12_2->BRAM_IMUX_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX34_1->BRAM_IMUX_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_CASCOUT_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_CASCOUT_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX31_1->BRAM_IMUX_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRL7", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTRAMBL", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI7", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_2", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_UTURN_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_0", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL11" }, "BRAM_L.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_0", - "is_directional": "1", "src_wire": "BRAM_FIFO36_DOADOL3", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS9", "is_directional": "1", - "src_wire": "BRAM_IMUX43_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_0" }, - "BRAM_L.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { + "BRAM_L.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { + "src_wire": "BRAM_IMUX21_4", "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU0", "is_directional": "1", - "src_wire": "BRAM_IMUX24_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI14" }, - "BRAM_L.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { + "BRAM_L.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { + "src_wire": "BRAM_FIFO18_DOADO9", "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL12", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_0" }, - "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { + "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_UTURN_ADDRBWRADDRL3": { + "src_wire": "BRAM_ADDRBWRADDRL3", "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL3" }, - "BRAM_L.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { + "BRAM_L.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { + "src_wire": "BRAM_FIFO18_EMPTY", "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPADIPU1", "is_directional": "1", - "src_wire": "BRAM_IMUX15_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_2" }, - "BRAM_L.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { + "BRAM_L.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { + "src_wire": "BRAM_FIFO36_TSTOUT4", "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_0" }, - "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_FIFO36_ADDRARDADDRL2": { + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL6", "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL2", "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6" }, - "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_UTURN_ADDRBWRADDRL1": { + "BRAM_L.BRAM_IMUX20_2->BRAM_IMUX_ADDRARDADDRL10": { + "src_wire": "BRAM_IMUX20_2", "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL1", "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL10" }, - "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_UTURN_ADDRARDADDRL3": { + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL3", "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9" }, - "BRAM_L.BRAM_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRBWRADDRU1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2" }, - "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_RAMB18_ADDRBWRADDR11": { + "BRAM_L.BRAM_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU8", "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR11", "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU12", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8" }, - "BRAM_L.BRAM_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "BRAM_L.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { + "src_wire": "BRAM_FIFO36_DOBDOU4", "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", - "src_wire": "BRAM_IMUX_ADDRARDADDRU5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_4" }, - "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_FIFO36_ADDRBWRADDRL10": { + "BRAM_L.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { + "src_wire": "BRAM_IMUX24_2", "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL10", "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA1" }, - "BRAM_L.BRAM_BYP6_2->BRAM_FIFO18_WEBWE7": { + "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_UTURN_ADDRBWRADDRU9": { + "src_wire": "BRAM_ADDRBWRADDRU9", "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE7", "is_directional": "1", - "src_wire": "BRAM_BYP6_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU9" }, - "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_UTURN_ADDRBWRADDRL9": { + "BRAM_L.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { + "src_wire": "BRAM_FIFO18_DOBDO14", "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL9", "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_1" + }, + "BRAM_L.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { + "src_wire": "BRAM_IMUX29_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE2" + }, + "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { + "src_wire": "BRAM_IMUX43_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI5" }, "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_FIFO36_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU13", - "is_directional": "1", "src_wire": "BRAM_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL14", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU13" + }, + "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_FIFO18_ADDRARDADDR9": { + "src_wire": "BRAM_ADDRARDADDRL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR9" + }, + "BRAM_L.BRAM_IMUX32_3->BRAM_IMUX_ADDRBWRADDRL6": { + "src_wire": "BRAM_IMUX32_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL6" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_2" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3" + }, + "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { + "src_wire": "BRAM_IMUX3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPADIP0" + }, + "BRAM_L.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { + "src_wire": "BRAM_RAMB18_DOADO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_2" + }, + "BRAM_L.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { + "src_wire": "BRAM_IMUX2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF" + }, + "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { + "src_wire": "BRAM_IMUX37_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL10" + }, + "BRAM_L.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { + "src_wire": "BRAM_IMUX40_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS6" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13" + }, + "BRAM_L.BRAM_IMUX35_3->BRAM_IMUX_ADDRBWRADDRL9": { + "src_wire": "BRAM_IMUX35_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL9" + }, + "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_UTURN_ADDRARDADDRU6": { + "src_wire": "BRAM_ADDRARDADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU6" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10" + }, + "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_UTURN_ADDRBWRADDRU2": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6" + }, + "BRAM_L.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { + "src_wire": "BRAM_FIFO18_DOADO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_0" + }, + "BRAM_L.BRAM_IMUX10_3->BRAM_IMUX_ADDRARDADDRU3": { + "src_wire": "BRAM_IMUX10_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU3" + }, + "BRAM_L.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { + "src_wire": "BRAM_FIFO18_DOBDO10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1" + }, + "BRAM_L.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { + "src_wire": "BRAM_IMUX23_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPU1" + }, + "BRAM_L.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { + "src_wire": "BRAM_FIFO18_WRERR", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_2" + }, + "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_UTURN_ADDRARDADDRL5": { + "src_wire": "BRAM_ADDRARDADDRL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL5" + }, + "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { + "src_wire": "BRAM_CTRL0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGBL" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { + "src_wire": "BRAM_FIFO36_DOBDOL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12" + }, + "BRAM_L.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { + "src_wire": "BRAM_IMUX23_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS5" + }, + "BRAM_L.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { + "src_wire": "BRAM_CLK0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKBL" + }, + "BRAM_L.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { + "src_wire": "BRAM_FIFO36_EMPTY", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_2" + }, + "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_UTURN_ADDRBWRADDRU7": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU7" + }, + "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_UTURN_ADDRBWRADDRU5": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU5" + }, + "BRAM_L.BRAM_IMUX9_1->BRAM_IMUX_ADDRARDADDRU0": { + "src_wire": "BRAM_IMUX9_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU0" + }, + "BRAM_L.BRAM_IMUX36_2->BRAM_IMUX_ADDRBWRADDRL10": { + "src_wire": "BRAM_IMUX36_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL10" + }, + "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { + "src_wire": "BRAM_IMUX2_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL15" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { + "src_wire": "BRAM_FIFO36_DOBDOU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_3" + }, + "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_UTURN_ADDRARDADDRL7": { + "src_wire": "BRAM_ADDRARDADDRL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL7" + }, + "BRAM_L.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { + "src_wire": "BRAM_RAMB18_DOADO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_3" + }, + "BRAM_L.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { + "src_wire": "BRAM_IMUX30_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU6" + }, + "BRAM_L.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { + "src_wire": "BRAM_FIFO36_DOADOU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_4" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5" + }, + "BRAM_L.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { + "src_wire": "BRAM_IMUX46_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE7" + }, + "BRAM_L.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { + "src_wire": "BRAM_IMUX17_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI12" + }, + "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_CASCOUT_ADDRBWRADDRU8": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU8" + }, + "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_UTURN_ADDRBWRADDRL11": { + "src_wire": "BRAM_ADDRBWRADDRL11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL11" + }, + "BRAM_L.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { + "src_wire": "BRAM_CLK0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCLKB" + }, + "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { + "src_wire": "BRAM_IMUX25_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL8" + }, + "BRAM_L.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { + "src_wire": "BRAM_FIFO36_DBITERR", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_2" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { + "src_wire": "BRAM_FIFO36_DOBDOU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_3" + }, + "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { + "src_wire": "BRAM_IMUX34_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL1" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1" + }, + "BRAM_L.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { + "src_wire": "BRAM_IMUX14_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE5" + }, + "BRAM_L.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { + "src_wire": "BRAM_IMUX24_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_UTURN_ADDRBWRADDRL9": { + "src_wire": "BRAM_ADDRBWRADDRL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL9" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { + "src_wire": "BRAM_FIFO36_DOBDOL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { + "src_wire": "BRAM_FIFO36_DOBDOU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_3" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14" + }, + "BRAM_L.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { + "src_wire": "BRAM_IMUX39_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_INJECTSBITERR" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL15" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3" + }, + "BRAM_L.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { + "src_wire": "BRAM_IMUX22_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU7" + }, + "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_CASCOUT_ADDRARDADDRU0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU0" + }, + "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_FIFO36_ADDRARDADDRU3": { + "src_wire": "BRAM_ADDRARDADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU3" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { + "src_wire": "BRAM_FIFO18_WRCOUNT11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_4" + }, + "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_RAMB18_ADDRARDADDR9": { + "src_wire": "BRAM_ADDRARDADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR9" + }, + "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { + "src_wire": "BRAM_CTRL0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST" + }, + "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { + "src_wire": "BRAM_IMUX3_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI12" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0" + }, + "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_FIFO36_ADDRARDADDRL8": { + "src_wire": "BRAM_ADDRARDADDRL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL8" + }, + "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { + "src_wire": "BRAM_IMUX43_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL5" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3" + }, + "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_RAMB18_ADDRBWRADDR5": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR5" + }, + "BRAM_L.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { + "src_wire": "BRAM_FIFO36_DOADOU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_3" + }, + "BRAM_L.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { + "src_wire": "BRAM_IMUX10_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT0" + }, + "BRAM_L.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { + "src_wire": "BRAM_IMUX43_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPBDIP0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9" + }, + "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { + "src_wire": "BRAM_IMUX42_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI12" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { + "src_wire": "BRAM_FIFO36_DOBDOU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_2" + }, + "BRAM_L.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { + "src_wire": "BRAM_FIFO36_DOADOL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_0" + }, + "BRAM_L.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { + "src_wire": "BRAM_IMUX9_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA2" + }, + "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_FIFO18_ADDRARDADDR4": { + "src_wire": "BRAM_ADDRARDADDRL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR4" + }, + "BRAM_L.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { + "src_wire": "BRAM_RAMB18_DOADO13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_4" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { + "src_wire": "BRAM_FIFO36_DOBDOL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_UTURN_ADDRBWRADDRL5": { + "src_wire": "BRAM_ADDRBWRADDRL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL5" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12" + }, + "BRAM_L.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { + "src_wire": "BRAM_CLK0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_CLKARDCLK" + }, + "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { + "src_wire": "BRAM_IMUX45_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL6" + }, + "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_UTURN_ADDRARDADDRL6": { + "src_wire": "BRAM_ADDRARDADDRL6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL6" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8" + }, + "BRAM_L.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { + "src_wire": "BRAM_CTRL1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU" + }, + "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_RAMB18_ADDRBWRADDR12": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR12" + }, + "BRAM_L.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { + "src_wire": "BRAM_IMUX15_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU8" + }, + "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_RAMB18_ADDRBWRADDR10": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR10" + }, + "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { + "src_wire": "BRAM_IMUX31_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL11" + }, + "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_CASCOUT_ADDRBWRADDRU11": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU11" + }, + "BRAM_L.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { + "src_wire": "BRAM_IMUX45_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU11" + }, + "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_CASCOUT_ADDRBWRADDRU7": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU7" + }, + "BRAM_L.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { + "src_wire": "BRAM_FIFO36_DOADOU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_2" + }, + "BRAM_L.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { + "src_wire": "BRAM_RAMB18_DOBDO5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_4" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10" + }, + "BRAM_L.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { + "src_wire": "BRAM_IMUX5_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU3" + }, + "BRAM_L.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { + "src_wire": "BRAM_IMUX40_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI1" + }, + "BRAM_L.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { + "src_wire": "BRAM_IMUX8_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI4" + }, + "BRAM_L.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { + "src_wire": "BRAM_FIFO36_DOADOL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_1" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4" + }, + "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { + "src_wire": "BRAM_IMUX40_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI7" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13" + }, + "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_CASCOUT_ADDRARDADDRU13": { + "src_wire": "BRAM_ADDRARDADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU13" + }, + "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { + "src_wire": "BRAM_IMUX21_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE1" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { + "src_wire": "BRAM_FIFO36_DOBDOL11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_0" + }, + "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_CASCOUT_ADDRARDADDRU14": { + "src_wire": "BRAM_ADDRARDADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU14" + }, + "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_FIFO18_ADDRARDADDR12": { + "src_wire": "BRAM_ADDRARDADDRL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR12" + }, + "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_FIFO36_ADDRBWRADDRL2": { + "src_wire": "BRAM_ADDRBWRADDRL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL2" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11" + }, + "BRAM_L.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { + "src_wire": "BRAM_IMUX16_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU4" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13" + }, + "BRAM_L.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { + "src_wire": "BRAM_IMUX22_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI7" + }, + "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { + "src_wire": "BRAM_IMUX32_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI0" + }, + "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_CASCOUT_ADDRARDADDRU4": { + "src_wire": "BRAM_ADDRARDADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU4" + }, + "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_CASCOUT_ADDRBWRADDRU3": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU3" + }, + "BRAM_L.BRAM_IMUX28_1->BRAM_IMUX_ADDRBWRADDRU8": { + "src_wire": "BRAM_IMUX28_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU8" + }, + "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { + "src_wire": "BRAM_IMUX16_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6" + }, + "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { + "src_wire": "BRAM_IMUX1_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPBDIP1" + }, + "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_UTURN_ADDRBWRADDRL13": { + "src_wire": "BRAM_ADDRBWRADDRL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL13" + }, + "BRAM_L.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { + "src_wire": "BRAM_IMUX11_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU13" + }, + "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_CASCOUT_ADDRARDADDRU2": { + "src_wire": "BRAM_ADDRARDADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1" + }, + "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_FIFO36_ADDRARDADDRU1": { + "src_wire": "BRAM_ADDRARDADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU1" + }, + "BRAM_L.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { + "src_wire": "BRAM_IMUX37_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS11" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1" + }, + "BRAM_L.BRAM_IMUX21_3->BRAM_IMUX_ADDRARDADDRL12": { + "src_wire": "BRAM_IMUX21_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL12" + }, + "BRAM_L.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { + "src_wire": "BRAM_RAMB18_DOBDO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_3" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8" + }, + "BRAM_L.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { + "src_wire": "BRAM_RAMB18_DOADO10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_3" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1" + }, + "BRAM_L.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { + "src_wire": "BRAM_IMUX15_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI8" + }, + "BRAM_L.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { + "src_wire": "BRAM_IMUX26_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ENBWREN" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2" + }, + "BRAM_L.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { + "src_wire": "BRAM_FIFO36_DOPBDOPL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_1" + }, + "BRAM_L.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { + "src_wire": "BRAM_IMUX9_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU2" + }, + "BRAM_L.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { + "src_wire": "BRAM_IMUX10_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENARDENU" + }, + "BRAM_L.BRAM_IMUX37_1->BRAM_IMUX_ADDRBWRADDRL4": { + "src_wire": "BRAM_IMUX37_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL4" + }, + "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_UTURN_ADDRBWRADDRU14": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU14" + }, + "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_UTURN_ADDRARDADDRU3": { + "src_wire": "BRAM_ADDRARDADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU3" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2" + }, + "BRAM_L.BRAM_IMUX12_3->BRAM_IMUX_ADDRARDADDRU5": { + "src_wire": "BRAM_IMUX12_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU5" + }, + "BRAM_L.BRAM_IMUX22_1->BRAM_IMUX_ADDRARDADDRL11": { + "src_wire": "BRAM_IMUX22_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL11" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { + "src_wire": "BRAM_FIFO36_DOBDOU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_4" + }, + "BRAM_L.BRAM_IMUX13_1->BRAM_IMUX_ADDRARDADDRU4": { + "src_wire": "BRAM_IMUX13_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU4" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2" + }, + "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_FIFO36_ADDRBWRADDRL6": { + "src_wire": "BRAM_ADDRBWRADDRL6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL6" + }, + "BRAM_L.BRAM_IMUX8_3->BRAM_IMUX_ADDRARDADDRU6": { + "src_wire": "BRAM_IMUX8_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU6" + }, + "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_UTURN_ADDRBWRADDRL4": { + "src_wire": "BRAM_ADDRBWRADDRL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL4" + }, + "BRAM_L.BRAM_BYP6_2->BRAM_FIFO18_WEBWE7": { + "src_wire": "BRAM_BYP6_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE7" + }, + "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_FIFO36_ADDRARDADDRU5": { + "src_wire": "BRAM_ADDRARDADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU5" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10" + }, + "BRAM_L.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { + "src_wire": "BRAM_FIFO18_DOBDO12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_1" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3" + }, + "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_UTURN_ADDRBWRADDRU4": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU4" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_3" + }, + "BRAM_L.BRAM_IMUX39_1->BRAM_IMUX_ADDRBWRADDRL13": { + "src_wire": "BRAM_IMUX39_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL13" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { + "src_wire": "BRAM_FIFO36_WRCOUNT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_2" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0" + }, + "BRAM_L.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { + "src_wire": "BRAM_FIFO18_DOADO6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_1" + }, + "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { + "src_wire": "BRAM_CTRL0_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMBL" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { + "src_wire": "BRAM_FIFO18_RDCOUNT10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_4" + }, + "BRAM_L.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { + "src_wire": "BRAM_IMUX38_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS12" + }, + "BRAM_L.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { + "src_wire": "BRAM_FIFO36_DOADOL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11" + }, + "BRAM_L.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { + "src_wire": "BRAM_FIFO36_DOADOL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_1" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6" + }, + "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_FIFO18_ADDRARDADDR6": { + "src_wire": "BRAM_ADDRARDADDRL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR6" + }, + "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { + "src_wire": "BRAM_IMUX30_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI3" + }, + "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { + "src_wire": "BRAM_IMUX1_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI7" + }, + "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_UTURN_ADDRARDADDRL2": { + "src_wire": "BRAM_ADDRARDADDRL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL2" + }, + "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_UTURN_ADDRBWRADDRL12": { + "src_wire": "BRAM_ADDRBWRADDRL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL12" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { + "src_wire": "BRAM_FIFO36_RDCOUNT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_1" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7" + }, + "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_RAMB18_ADDRBWRADDR11": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR11" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { + "src_wire": "BRAM_FIFO36_DOBDOL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { + "src_wire": "BRAM_FIFO36_RDCOUNT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_1" + }, + "BRAM_L.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { + "src_wire": "BRAM_FIFO36_CASCADEOUTA", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1" + }, + "BRAM_L.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { + "src_wire": "BRAM_IMUX11_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT1" + }, + "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { + "src_wire": "BRAM_IMUX6_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL4" + }, + "BRAM_L.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { + "src_wire": "BRAM_FIFO18_DOADO4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_1" + }, + "BRAM_L.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { + "src_wire": "BRAM_IMUX3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF" + }, + "BRAM_L.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { + "src_wire": "BRAM_FIFO36_TSTOUT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_4" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { + "src_wire": "BRAM_FIFO36_RDCOUNT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3" + }, + "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_UTURN_ADDRARDADDRL1": { + "src_wire": "BRAM_ADDRARDADDRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL1" + }, + "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { + "src_wire": "BRAM_IMUX35_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCEB" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { + "src_wire": "BRAM_FIFO18_RDCOUNT11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_4" + }, + "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { "src_wire": "BRAM_IMUX46_1", - "is_pseudo": "0" - }, - "BRAM_L.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU15", "is_directional": "1", - "src_wire": "BRAM_IMUX23_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI14" + }, + "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { + "src_wire": "BRAM_CTRL0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { + "src_wire": "BRAM_FIFO36_DOBDOL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_1" + }, + "BRAM_L.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { + "src_wire": "BRAM_RAMB18_DOBDO7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_4" + }, + "BRAM_L.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { + "src_wire": "BRAM_RAMB18_DOADO11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_3" + }, + "BRAM_L.BRAM_IMUX34_3->BRAM_IMUX_ADDRBWRADDRL3": { + "src_wire": "BRAM_IMUX34_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL3" + }, + "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { + "src_wire": "BRAM_IMUX44_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI13" + }, + "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { + "src_wire": "BRAM_IMUX4_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI5" + }, + "BRAM_L.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { + "src_wire": "BRAM_IMUX13_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_CASCOUT_ADDRBWRADDRU10": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU10" + }, + "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_CASCOUT_ADDRBWRADDRU5": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU5" + }, + "BRAM_L.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { + "src_wire": "BRAM_FIFO36_DOADOU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_4" + }, + "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_FIFO18_ADDRBWRADDR2": { + "src_wire": "BRAM_ADDRBWRADDRL3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR2" + }, + "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_UTURN_ADDRARDADDRL3": { + "src_wire": "BRAM_ADDRARDADDRL3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL3" + }, + "BRAM_L.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { + "src_wire": "BRAM_RAMB18_DOPADOP0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_3" + }, + "BRAM_L.BRAM_IMUX11_1->BRAM_IMUX_ADDRARDADDRU2": { + "src_wire": "BRAM_IMUX11_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU2" + }, + "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { + "src_wire": "BRAM_IMUX16_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA0" + }, + "BRAM_L.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { + "src_wire": "BRAM_IMUX19_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU13" + }, + "BRAM_L.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { + "src_wire": "BRAM_CLK1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCLKB" + }, + "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { + "src_wire": "BRAM_IMUX27_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI9" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_2" + }, + "BRAM_L.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { + "src_wire": "BRAM_IMUX24_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU0" + }, + "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { + "src_wire": "BRAM_IMUX2_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI15" + }, + "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_UTURN_ADDRBWRADDRL0": { + "src_wire": "BRAM_ADDRBWRADDRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL0" + }, + "BRAM_L.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { + "src_wire": "BRAM_CLK0_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8" + }, + "BRAM_L.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { + "src_wire": "BRAM_RAMB18_DOBDO11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_3" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11" + }, + "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_FIFO36_ADDRARDADDRL2": { + "src_wire": "BRAM_ADDRARDADDRL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL2" + }, + "BRAM_L.BRAM_IMUX19_1->BRAM_IMUX_ADDRARDADDRL2": { + "src_wire": "BRAM_IMUX19_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL2" + }, + "BRAM_L.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { + "src_wire": "BRAM_IMUX15_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPADIP1" + }, + "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_RAMB18_ADDRARDADDR4": { + "src_wire": "BRAM_ADDRARDADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR4" + }, + "BRAM_L.BRAM_IMUX25_3->BRAM_IMUX_ADDRBWRADDRU7": { + "src_wire": "BRAM_IMUX25_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU7" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1" + }, + "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO36_ADDRARDADDRL0": { + "src_wire": "BRAM_ADDRARDADDRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL0" + }, + "BRAM_L.BRAM_IMUX12_2->BRAM_IMUX_ADDRARDADDRU10": { + "src_wire": "BRAM_IMUX12_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU10" + }, + "BRAM_L.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { + "src_wire": "BRAM_IMUX20_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI6" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { + "src_wire": "BRAM_FIFO36_WRCOUNT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_2" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13" + }, + "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_FIFO36_ADDRARDADDRL7": { + "src_wire": "BRAM_ADDRARDADDRL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL7" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7" + }, + "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_RAMB18_ADDRBWRADDR1": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR1" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2" + }, + "BRAM_L.BRAM_IMUX26_3->BRAM_IMUX_ADDRBWRADDRU3": { + "src_wire": "BRAM_IMUX26_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU3" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13" + }, + "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_FIFO36_ADDRBWRADDRL11": { + "src_wire": "BRAM_ADDRBWRADDRL11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL11" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { + "src_wire": "BRAM_FIFO36_WRCOUNT9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_3" + }, + "BRAM_L.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { + "src_wire": "BRAM_FIFO36_DOPBDOPL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_1" + }, + "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_FIFO18_ADDRARDADDR13": { + "src_wire": "BRAM_ADDRARDADDRL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR13" + }, + "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_FIFO36_ADDRBWRADDRU14": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU14" + }, + "BRAM_L.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { + "src_wire": "BRAM_FIFO36_DOADOU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_3" + }, + "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { + "src_wire": "BRAM_IMUX34_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENBWRENL" + }, + "BRAM_L.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { + "src_wire": "BRAM_IMUX19_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI13" + }, + "BRAM_L.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { + "src_wire": "BRAM_RAMB18_DOADO15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_4" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { + "src_wire": "BRAM_FIFO36_DOBDOL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_1" + }, + "BRAM_L.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { + "src_wire": "BRAM_FIFO18_DOBDO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_0" + }, + "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { + "src_wire": "BRAM_IMUX35_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEBL" + }, + "BRAM_L.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { + "src_wire": "BRAM_FIFO36_DOPBDOPU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_3" + }, + "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_RAMB18_ADDRARDADDR12": { + "src_wire": "BRAM_ADDRARDADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR12" + }, + "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_FIFO36_ADDRBWRADDRU10": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU10" + }, + "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_FIFO36_ADDRBWRADDRL14": { + "src_wire": "BRAM_ADDRBWRADDRL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL14" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { + "src_wire": "BRAM_FIFO36_RDCOUNT11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_4" + }, + "BRAM_L.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { + "src_wire": "BRAM_IMUX13_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU14" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_3" + }, + "BRAM_L.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { + "src_wire": "BRAM_FIFO18_DOADO8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_FIFO36_ADDRBWRADDRL10": { + "src_wire": "BRAM_ADDRBWRADDRL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL10" + }, + "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_FIFO18_ADDRARDADDR8": { + "src_wire": "BRAM_ADDRARDADDRL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR8" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { + "src_wire": "BRAM_FIFO36_WRCOUNT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { + "src_wire": "BRAM_FIFO36_DOBDOU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_4" + }, + "BRAM_L.BRAM_IMUX15_1->BRAM_IMUX_ADDRARDADDRU13": { + "src_wire": "BRAM_IMUX15_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU13" + }, + "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_UTURN_ADDRARDADDRU13": { + "src_wire": "BRAM_ADDRARDADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU13" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4" + }, + "BRAM_L.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { + "src_wire": "BRAM_IMUX26_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENBWRENU" + }, + "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_FIFO18_ADDRARDADDR11": { + "src_wire": "BRAM_ADDRARDADDRL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR11" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { + "src_wire": "BRAM_FIFO18_WRCOUNT8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_3" + }, + "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { + "src_wire": "BRAM_IMUX34_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ENBWREN" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1" + }, + "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_FIFO36_ADDRARDADDRL11": { + "src_wire": "BRAM_ADDRARDADDRL11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL11" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { + "src_wire": "BRAM_FIFO18_RDCOUNT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_UTURN_ADDRBWRADDRL8": { + "src_wire": "BRAM_ADDRBWRADDRL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL8" + }, + "BRAM_L.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { + "src_wire": "BRAM_FIFO36_TSTOUT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_1" + }, + "BRAM_L.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { + "src_wire": "BRAM_IMUX8_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU0" + }, + "BRAM_L.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { + "src_wire": "BRAM_FIFO18_DOADO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_0" + }, + "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { + "src_wire": "BRAM_IMUX31_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI11" + }, + "BRAM_L.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { + "src_wire": "BRAM_IMUX11_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCEAREGCE" + }, + "BRAM_L.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { + "src_wire": "BRAM_IMUX9_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI12" + }, + "BRAM_L.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { + "src_wire": "BRAM_FIFO36_DOADOU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_3" + }, + "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { + "src_wire": "BRAM_IMUX2_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL4" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2" + }, + "BRAM_L.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { + "src_wire": "BRAM_IMUX43_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS9" + }, + "BRAM_L.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { + "src_wire": "BRAM_IMUX41_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU9" + }, + "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_UTURN_ADDRBWRADDRL10": { + "src_wire": "BRAM_ADDRBWRADDRL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL10" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6" + }, + "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { + "src_wire": "BRAM_IMUX27_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL9" + }, + "BRAM_L.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { + "src_wire": "BRAM_IMUX15_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT5" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { + "src_wire": "BRAM_FIFO36_RDCOUNT8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { + "src_wire": "BRAM_FIFO18_RDCOUNT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_FIFO18_ADDRBWRADDR4": { + "src_wire": "BRAM_ADDRBWRADDRL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR4" + }, + "BRAM_L.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { + "src_wire": "BRAM_FIFO36_DOPADOPL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_1" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { + "src_wire": "BRAM_FIFO18_WRCOUNT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_0" + }, + "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_CASCOUT_ADDRARDADDRU1": { + "src_wire": "BRAM_ADDRARDADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_UTURN_ADDRBWRADDRU10": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU10" + }, + "BRAM_L.BRAM_IMUX34_1->BRAM_IMUX_ADDRBWRADDRL1": { + "src_wire": "BRAM_IMUX34_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL1" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { + "src_wire": "BRAM_FIFO36_DOBDOU15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_4" + }, + "BRAM_L.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { + "src_wire": "BRAM_IMUX33_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS7" + }, + "BRAM_L.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { + "src_wire": "BRAM_FIFO36_DOADOU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_2" + }, + "BRAM_L.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { + "src_wire": "BRAM_IMUX0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTBRAMRST" + }, + "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { + "src_wire": "BRAM_IMUX19_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCEAREGCE" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0" + }, + "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { + "src_wire": "BRAM_IMUX41_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI4" + }, + "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { + "src_wire": "BRAM_IMUX17_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7" + }, + "BRAM_L.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { + "src_wire": "BRAM_FIFO18_FULL", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10" + }, + "BRAM_L.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { + "src_wire": "BRAM_IMUX43_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPU0" + }, + "BRAM_L.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { + "src_wire": "BRAM_FIFO36_DOPADOPL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_1" + }, + "BRAM_L.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { + "src_wire": "BRAM_CTRL1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGBU" + }, + "BRAM_L.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { + "src_wire": "BRAM_IMUX11_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI13" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_RAMB18_ADDRBTIEHIGH0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH0" + }, + "BRAM_L.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { + "src_wire": "BRAM_IMUX4_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI10" + }, + "BRAM_L.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { + "src_wire": "BRAM_IMUX42_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS0" + }, + "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_FIFO36_ADDRARDADDRU10": { + "src_wire": "BRAM_ADDRARDADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU10" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5" + }, + "BRAM_L.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { + "src_wire": "BRAM_RAMB18_DOPBDOP0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_3" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { + "src_wire": "BRAM_FIFO18_RDCOUNT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_3" + }, + "BRAM_L.BRAM_IMUX38_3->BRAM_IMUX_ADDRBWRADDRL14": { + "src_wire": "BRAM_IMUX38_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL14" + }, + "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { + "src_wire": "BRAM_IMUX32_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1" + }, + "BRAM_L.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { + "src_wire": "BRAM_FIFO18_DOADO5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_1" + }, + "BRAM_L.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { + "src_wire": "BRAM_CLK1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKARDCLKU" + }, + "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_CASCOUT_ADDRBWRADDRU13": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU13" + }, + "BRAM_L.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { + "src_wire": "BRAM_IMUX4_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTOFF" + }, + "BRAM_L.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { + "src_wire": "BRAM_FIFO36_DOADOL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_2" + }, + "BRAM_L.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { + "src_wire": "BRAM_CTRL1_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTRAMB" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0" + }, + "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { + "src_wire": "BRAM_IMUX41_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI15" + }, + "BRAM_L.BRAM_IMUX17_3->BRAM_IMUX_ADDRARDADDRL7": { + "src_wire": "BRAM_IMUX17_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL7" + }, + "BRAM_L.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { + "src_wire": "BRAM_IMUX8_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA0" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { + "src_wire": "BRAM_FIFO18_RDCOUNT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_0" + }, + "BRAM_L.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { + "src_wire": "BRAM_IMUX10_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ENARDEN" + }, + "BRAM_L.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { + "src_wire": "BRAM_IMUX23_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI8" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_2" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { + "src_wire": "BRAM_FIFO36_DOBDOU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_2" + }, + "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { + "src_wire": "BRAM_IMUX7_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL14" + }, + "BRAM_L.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { + "src_wire": "BRAM_IMUX29_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU2" + }, + "BRAM_L.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { + "src_wire": "BRAM_IMUX34_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS8" + }, + "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { + "src_wire": "BRAM_IMUX38_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL6" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4" + }, + "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_RAMB18_ADDRBWRADDR13": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR13" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { + "src_wire": "BRAM_FIFO36_DOBDOL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_0" + }, + "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_UTURN_ADDRARDADDRU4": { + "src_wire": "BRAM_ADDRARDADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU4" + }, + "BRAM_L.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { + "src_wire": "BRAM_IMUX31_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_INJECTDBITERR" + }, + "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { + "src_wire": "BRAM_IMUX35_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI9" + }, + "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_FIFO36_ADDRBWRADDRU12": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU12" + }, + "BRAM_L.BRAM_IMUX38_1->BRAM_IMUX_ADDRBWRADDRL11": { + "src_wire": "BRAM_IMUX38_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL11" + }, + "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_RAMB18_ADDRBWRADDR0": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR0" + }, + "BRAM_L.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { + "src_wire": "BRAM_FIFO18_DOADO10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_0" + }, + "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_FIFO36_ADDRARDADDRU14": { + "src_wire": "BRAM_ADDRARDADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU14" + }, + "BRAM_L.BRAM_IMUX18_3->BRAM_IMUX_ADDRARDADDRL3": { + "src_wire": "BRAM_IMUX18_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL3" + }, + "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_RAMB18_ADDRARDADDR2": { + "src_wire": "BRAM_ADDRARDADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5" + }, + "BRAM_L.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { + "src_wire": "BRAM_FIFO36_DOADOL11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9" + }, + "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_FIFO18_ADDRBWRADDR11": { + "src_wire": "BRAM_ADDRBWRADDRL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR11" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { + "src_wire": "BRAM_FIFO18_RDCOUNT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_1" + }, + "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_CASCOUT_ADDRARDADDRU6": { + "src_wire": "BRAM_ADDRARDADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU6" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2" + }, + "BRAM_L.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { + "src_wire": "BRAM_FIFO18_DOADO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_0" + }, + "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_RAMB18_ADDRBWRADDR3": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR3" }, "BRAM_L.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_3", - "is_directional": "1", "src_wire": "BRAM_FIFO36_RDCOUNT6", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_3" + }, + "BRAM_L.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { + "src_wire": "BRAM_RAMB18_DOADO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_3" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { + "src_wire": "BRAM_FIFO18_WRCOUNT9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_3" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4" + }, + "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_FIFO36_ADDRARDADDRL10": { + "src_wire": "BRAM_ADDRARDADDRL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL10" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { + "src_wire": "BRAM_FIFO36_RDCOUNT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_FIFO18_ADDRBWRADDR6": { + "src_wire": "BRAM_ADDRBWRADDRL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR6" + }, + "BRAM_L.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { + "src_wire": "BRAM_FAN5_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { + "src_wire": "BRAM_FIFO18_WRCOUNT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_2" + }, + "BRAM_L.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { + "src_wire": "BRAM_CLK0_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_CLKBWRCLK" + }, + "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { + "src_wire": "BRAM_IMUX38_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE6" + }, + "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { + "src_wire": "BRAM_IMUX40_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL7" + }, + "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { + "src_wire": "BRAM_IMUX17_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL2" + }, + "BRAM_L.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { + "src_wire": "BRAM_FIFO18_DOADO11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_0" + }, + "BRAM_L.BRAM_IMUX22_3->BRAM_IMUX_ADDRARDADDRL14": { + "src_wire": "BRAM_IMUX22_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL14" + }, + "BRAM_L.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { + "src_wire": "BRAM_IMUX28_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT10" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { + "src_wire": "BRAM_FIFO36_DOBDOL6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_FIFO36_ADDRBWRADDRU7": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU7" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14" + }, + "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { + "src_wire": "BRAM_IMUX1_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPL1" + }, + "BRAM_L.BRAM_IMUX29_1->BRAM_IMUX_ADDRBWRADDRU4": { + "src_wire": "BRAM_IMUX29_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU4" + }, + "BRAM_L.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { + "src_wire": "BRAM_FIFO36_DOADOU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_4" + }, + "BRAM_L.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { + "src_wire": "BRAM_IMUX45_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS11" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { + "src_wire": "BRAM_FIFO36_DOBDOU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_3" + }, + "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_FIFO36_ADDRARDADDRU0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU0" + }, + "BRAM_L.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { + "src_wire": "BRAM_IMUX3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI2" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7" + }, + "BRAM_L.BRAM_IMUX14_1->BRAM_IMUX_ADDRARDADDRU11": { + "src_wire": "BRAM_IMUX14_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU11" + }, + "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { + "src_wire": "BRAM_IMUX35_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL9" + }, + "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_CASCOUT_ADDRBWRADDRU6": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU6" + }, + "BRAM_L.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { + "src_wire": "BRAM_IMUX26_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT8" + }, + "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_UTURN_ADDRBWRADDRU3": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU3" + }, + "BRAM_L.BRAM_IMUX29_3->BRAM_IMUX_ADDRBWRADDRU12": { + "src_wire": "BRAM_IMUX29_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU12" + }, + "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_UTURN_ADDRBWRADDRL1": { + "src_wire": "BRAM_ADDRBWRADDRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL1" + }, + "BRAM_L.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { + "src_wire": "BRAM_IMUX41_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN4" + }, + "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { + "src_wire": "BRAM_IMUX6_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE4" + }, + "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { + "src_wire": "BRAM_IMUX25_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI8" + }, + "BRAM_L.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { + "src_wire": "BRAM_RAMB18_DOBDO10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_3" + }, + "BRAM_L.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { + "src_wire": "BRAM_FIFO36_DOADOL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_0" + }, + "BRAM_L.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { + "src_wire": "BRAM_IMUX23_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU15" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13" + }, + "BRAM_L.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { + "src_wire": "BRAM_FIFO36_DOPADOPU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_3" + }, + "BRAM_L.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { + "src_wire": "BRAM_FIFO18_DOPADOP0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_1" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { + "src_wire": "BRAM_FIFO18_WRCOUNT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7" + }, + "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO36_ADDRARDADDRL1": { + "src_wire": "BRAM_ADDRARDADDRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL1" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10" + }, + "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_CASCOUT_ADDRARDADDRU12": { + "src_wire": "BRAM_ADDRARDADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU12" + }, + "BRAM_L.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { + "src_wire": "BRAM_RAMB18_DOBDO8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_2" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { + "src_wire": "BRAM_FIFO18_RDCOUNT9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_2" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { + "src_wire": "BRAM_FIFO36_DOBDOL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_0" + }, + "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { + "src_wire": "BRAM_IMUX40_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPADIP1" + }, + "BRAM_L.BRAM_IMUX17_1->BRAM_IMUX_ADDRARDADDRL0": { + "src_wire": "BRAM_IMUX17_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL0" + }, + "BRAM_L.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { + "src_wire": "BRAM_IMUX13_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_CASCOUT_ADDRBWRADDRU9": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU9" + }, + "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_RAMB18_ADDRARDADDR1": { + "src_wire": "BRAM_ADDRARDADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR1" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { + "src_wire": "BRAM_FIFO18_RDCOUNT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_3" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8" + }, + "BRAM_L.BRAM_IMUX11_3->BRAM_IMUX_ADDRARDADDRU9": { + "src_wire": "BRAM_IMUX11_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU9" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2" + }, + "BRAM_L.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { + "src_wire": "BRAM_FIFO18_DOPADOP1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_1" + }, + "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { + "src_wire": "BRAM_IMUX28_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL2" + }, + "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { + "src_wire": "BRAM_IMUX1_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL7" + }, + "BRAM_L.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { + "src_wire": "BRAM_FIFO36_ALMOSTEMPTY", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_2" + }, + "BRAM_L.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { + "src_wire": "BRAM_FIFO18_DOPBDOP1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_1" + }, + "BRAM_L.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { + "src_wire": "BRAM_FIFO18_DOBDO9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_0" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_UTURN_ADDRBWRADDRU6": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU6" + }, + "BRAM_L.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { + "src_wire": "BRAM_IMUX42_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPADIP0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_FIFO18_ADDRBWRADDR8": { + "src_wire": "BRAM_ADDRBWRADDRL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR8" + }, + "BRAM_L.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { + "src_wire": "BRAM_IMUX12_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT2" + }, + "BRAM_L.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { + "src_wire": "BRAM_FIFO36_WRERR", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_2" + }, + "BRAM_L.BRAM_IMUX33_1->BRAM_IMUX_ADDRBWRADDRL0": { + "src_wire": "BRAM_IMUX33_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { + "src_wire": "BRAM_FIFO36_WRCOUNT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_RAMB18_ADDRBWRADDR2": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0" + }, + "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_FIFO36_ADDRBWRADDRL9": { + "src_wire": "BRAM_ADDRBWRADDRL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL9" + }, + "BRAM_L.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { + "src_wire": "BRAM_FIFO36_DOADOU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_4" + }, + "BRAM_L.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { + "src_wire": "BRAM_FIFO18_DOBDO15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_2" + }, + "BRAM_L.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { + "src_wire": "BRAM_IMUX11_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEAREGCEU" + }, + "BRAM_L.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { + "src_wire": "BRAM_IMUX14_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU7" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9" + }, + "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_UTURN_ADDRARDADDRU10": { + "src_wire": "BRAM_ADDRARDADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU10" + }, + "BRAM_L.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { + "src_wire": "BRAM_FIFO36_DOADOL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_0" + }, + "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { + "src_wire": "BRAM_IMUX5_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI13" + }, + "BRAM_L.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { + "src_wire": "BRAM_IMUX44_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI3" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8" + }, + "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { + "src_wire": "BRAM_IMUX16_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL0" + }, + "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_UTURN_ADDRARDADDRL14": { + "src_wire": "BRAM_ADDRARDADDRL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL14" + }, + "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_FIFO36_ADDRARDADDRL12": { + "src_wire": "BRAM_ADDRARDADDRL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL12" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7" + }, + "BRAM_L.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { + "src_wire": "BRAM_FIFO18_DOBDO11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_0" + }, + "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { + "src_wire": "BRAM_IMUX45_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI6" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13" + }, + "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { + "src_wire": "BRAM_IMUX36_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI2" + }, + "BRAM_L.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { + "src_wire": "BRAM_IMUX45_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE3" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11" + }, + "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { + "src_wire": "BRAM_IMUX41_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL15" + }, + "BRAM_L.BRAM_IMUX12_1->BRAM_IMUX_ADDRARDADDRU8": { + "src_wire": "BRAM_IMUX12_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU8" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8" + }, + "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_FIFO36_ADDRBWRADDRU5": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU5" + }, + "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_FIFO18_ADDRBTIEHIGH0": { + "src_wire": "BRAM_ADDRBWRADDRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH0" + }, + "BRAM_L.BRAM_IMUX41_4->BRAM_FIFO36_TSTWROS7": { + "src_wire": "BRAM_IMUX41_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS7" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2" + }, + "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_UTURN_ADDRBWRADDRL14": { + "src_wire": "BRAM_ADDRBWRADDRL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL14" + }, + "BRAM_L.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { + "src_wire": "BRAM_IMUX21_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS3" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10" + }, + "BRAM_L.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { + "src_wire": "BRAM_CLK0_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKBWRCLKL" + }, + "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_CASCOUT_ADDRARDADDRU5": { + "src_wire": "BRAM_ADDRARDADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU5" + }, + "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_FIFO18_ADDRBWRADDR5": { + "src_wire": "BRAM_ADDRBWRADDRL6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR5" + }, + "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { + "src_wire": "BRAM_IMUX4_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL5" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12" + }, + "BRAM_L.BRAM_IMUX37_3->BRAM_IMUX_ADDRBWRADDRL12": { + "src_wire": "BRAM_IMUX37_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL12" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { + "src_wire": "BRAM_FIFO18_WRCOUNT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14" + }, + "BRAM_L.BRAM_IMUX33_3->BRAM_IMUX_ADDRBWRADDRL7": { + "src_wire": "BRAM_IMUX33_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL7" + }, + "BRAM_L.BRAM_IMUX24_3->BRAM_IMUX_ADDRBWRADDRU6": { + "src_wire": "BRAM_IMUX24_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU6" + }, + "BRAM_L.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { + "src_wire": "BRAM_IMUX12_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU6" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { + "src_wire": "BRAM_FIFO36_RDCOUNT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_3" + }, + "BRAM_L.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { + "src_wire": "BRAM_FIFO18_DOBDO6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_1" + }, + "BRAM_L.BRAM_IMUX14_3->BRAM_IMUX_ADDRARDADDRU14": { + "src_wire": "BRAM_IMUX14_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU14" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8" + }, + "BRAM_L.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { + "src_wire": "BRAM_IMUX42_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPU0" + }, + "BRAM_L.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { + "src_wire": "BRAM_IMUX45_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI11" + }, + "BRAM_L.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { + "src_wire": "BRAM_FIFO36_DOPADOPU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_3" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3" + }, + "BRAM_L.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { + "src_wire": "BRAM_FIFO18_DOBDO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14" + }, + "BRAM_L.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { + "src_wire": "BRAM_RAMB18_DOADO6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_4" + }, + "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { + "src_wire": "BRAM_IMUX29_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI10" + }, + "BRAM_L.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { + "src_wire": "BRAM_IMUX2_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU9" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11" + }, + "BRAM_L.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { + "src_wire": "BRAM_FIFO18_DOADO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_0" + }, + "BRAM_L.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { + "src_wire": "BRAM_IMUX22_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS4" + }, + "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_FIFO36_ADDRARDADDRU12": { + "src_wire": "BRAM_ADDRARDADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU12" + }, + "BRAM_L.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { + "src_wire": "BRAM_IMUX19_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS1" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2" + }, + "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { + "src_wire": "BRAM_CTRL0_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { + "src_wire": "BRAM_FIFO36_RDCOUNT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_0" + }, + "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_RAMB18_ADDRARDADDR3": { + "src_wire": "BRAM_ADDRARDADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR3" + }, + "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_FIFO36_ADDRBWRADDRU4": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU4" + }, + "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { + "src_wire": "BRAM_IMUX38_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL3" + }, + "BRAM_L.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { + "src_wire": "BRAM_IMUX36_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS10" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { + "src_wire": "BRAM_FIFO18_RDCOUNT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_1" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { + "src_wire": "BRAM_FIFO36_WRCOUNT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_0" + }, + "BRAM_L.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { + "src_wire": "BRAM_FIFO18_DOBDO7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_2" + }, + "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { + "src_wire": "BRAM_IMUX21_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_FIFO36_ADDRBWRADDRU1": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU1" + }, + "BRAM_L.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { + "src_wire": "BRAM_IMUX24_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT6" + }, + "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_UTURN_ADDRARDADDRU9": { + "src_wire": "BRAM_ADDRARDADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU9" + }, + "BRAM_L.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { + "src_wire": "BRAM_IMUX42_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { + "src_wire": "BRAM_FIFO18_RDCOUNT8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_2" + }, + "BRAM_L.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { + "src_wire": "BRAM_IMUX15_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPU1" + }, + "BRAM_L.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { + "src_wire": "BRAM_IMUX20_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU6" + }, + "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_UTURN_ADDRARDADDRL0": { + "src_wire": "BRAM_ADDRARDADDRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { + "src_wire": "BRAM_FIFO36_RDCOUNT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_1" + }, + "BRAM_L.BRAM_IMUX30_3->BRAM_IMUX_ADDRBWRADDRU14": { + "src_wire": "BRAM_IMUX30_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU14" + }, + "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_FIFO36_ADDRBWRADDRL3": { + "src_wire": "BRAM_ADDRBWRADDRL3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL3" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { + "src_wire": "BRAM_FIFO36_WRCOUNT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_0" + }, + "BRAM_L.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { + "src_wire": "BRAM_IMUX14_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI7" + }, + "BRAM_L.BRAM_IMUX20_1->BRAM_IMUX_ADDRARDADDRL8": { + "src_wire": "BRAM_IMUX20_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL8" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { + "src_wire": "BRAM_FIFO18_WRCOUNT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_FIFO36_ADDRBWRADDRU8": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU8" + }, + "BRAM_L.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { + "src_wire": "BRAM_FIFO36_TSTOUT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_1" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { + "src_wire": "BRAM_FIFO36_DOBDOU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_3" + }, + "BRAM_L.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { + "src_wire": "BRAM_CTRL1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM" + }, + "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_FIFO36_ADDRBWRADDRL7": { + "src_wire": "BRAM_ADDRBWRADDRL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL7" + }, + "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_CASCOUT_ADDRARDADDRU10": { + "src_wire": "BRAM_ADDRARDADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU10" + }, + "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_UTURN_ADDRARDADDRU2": { + "src_wire": "BRAM_ADDRARDADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU2" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { + "src_wire": "BRAM_FIFO18_WRCOUNT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_0" + }, + "BRAM_L.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { + "src_wire": "BRAM_FIFO18_ALMOSTFULL", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_2" + }, + "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_FIFO18_ADDRBWRADDR12": { + "src_wire": "BRAM_ADDRBWRADDRL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR12" + }, + "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_CASCOUT_ADDRBWRADDRU1": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU1" + }, + "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { + "src_wire": "BRAM_IMUX32_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA1" + }, + "BRAM_L.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { + "src_wire": "BRAM_FIFO36_CASCADEOUTB", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1" + }, + "BRAM_L.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { + "src_wire": "BRAM_IMUX6_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU11" + }, + "BRAM_L.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { + "src_wire": "BRAM_RAMB18_DOBDO14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_4" + }, + "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_RAMB18_ADDRBWRADDR6": { + "src_wire": "BRAM_ADDRBWRADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR6" + }, + "BRAM_L.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { + "src_wire": "BRAM_FIFO18_DOBDO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { + "src_wire": "BRAM_FIFO36_DOBDOL3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_0" + }, + "BRAM_L.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { + "src_wire": "BRAM_FIFO36_DOADOL6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_1" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9" + }, + "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_FIFO36_ADDRBWRADDRU11": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU11" + }, + "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_FIFO36_ADDRBWRADDRU3": { + "src_wire": "BRAM_ADDRBWRADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU3" + }, + "BRAM_L.BRAM_IMUX13_3->BRAM_IMUX_ADDRARDADDRU12": { + "src_wire": "BRAM_IMUX13_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU12" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8" + }, + "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO18_ADDRATIEHIGH0": { + "src_wire": "BRAM_ADDRARDADDRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH0" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { + "src_wire": "BRAM_FIFO36_DOBDOU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_4" + }, + "BRAM_L.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { + "src_wire": "BRAM_CLK0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKARDCLKL" + }, + "BRAM_L.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { + "src_wire": "BRAM_IMUX10_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI5" + }, + "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_FIFO36_ADDRARDADDRL9": { + "src_wire": "BRAM_ADDRARDADDRL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL9" + }, + "BRAM_L.BRAM_IMUX28_2->BRAM_IMUX_ADDRBWRADDRU10": { + "src_wire": "BRAM_IMUX28_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU10" + }, + "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_RAMB18_ADDRATIEHIGH0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH0" + }, + "BRAM_L.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { + "src_wire": "BRAM_IMUX42_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS8" + }, + "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_UTURN_ADDRARDADDRU1": { + "src_wire": "BRAM_ADDRARDADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU1" + }, + "BRAM_L.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { + "src_wire": "BRAM_IMUX45_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU3" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3" + }, + "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_FIFO36_ADDRARDADDRU2": { + "src_wire": "BRAM_ADDRARDADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU2" + }, + "BRAM_L.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { + "src_wire": "BRAM_IMUX44_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU3" + }, + "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_RAMB18_ADDRARDADDR7": { + "src_wire": "BRAM_ADDRARDADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR7" + }, + "BRAM_L.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { + "src_wire": "BRAM_IMUX2_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI9" + }, + "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { + "src_wire": "BRAM_IMUX40_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPL1" + }, + "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { + "src_wire": "BRAM_IMUX6_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI6" + }, + "BRAM_L.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { + "src_wire": "BRAM_CTRL1_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMBU" + }, + "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_FIFO18_ADDRARDADDR10": { + "src_wire": "BRAM_ADDRARDADDRL11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR10" + }, + "BRAM_L.BRAM_IMUX27_3->BRAM_IMUX_ADDRBWRADDRU9": { + "src_wire": "BRAM_IMUX27_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU9" + }, + "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_UTURN_ADDRARDADDRU12": { + "src_wire": "BRAM_ADDRARDADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU12" + }, + "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_RAMB18_ADDRARDADDR10": { + "src_wire": "BRAM_ADDRARDADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR10" + }, + "BRAM_L.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { + "src_wire": "BRAM_RAMB18_DOPADOP1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_3" + }, + "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { + "src_wire": "BRAM_IMUX4_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPL0" + }, + "BRAM_L.BRAM_IMUX27_1->BRAM_IMUX_ADDRBWRADDRU2": { + "src_wire": "BRAM_IMUX27_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU2" + }, + "BRAM_L.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { + "src_wire": "BRAM_IMUX14_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU5" + }, + "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_UTURN_ADDRBWRADDRU12": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU12" + }, + "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { + "src_wire": "BRAM_IMUX33_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA3" + }, + "BRAM_L.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { + "src_wire": "BRAM_IMUX40_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU1" + }, + "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { + "src_wire": "BRAM_IMUX44_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL13" + }, + "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { + "src_wire": "BRAM_IMUX5_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4" + }, + "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_UTURN_ADDRARDADDRL10": { + "src_wire": "BRAM_ADDRARDADDRL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL10" + }, + "BRAM_L.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { + "src_wire": "BRAM_RAMB18_DOADO14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_4" + }, + "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { + "src_wire": "BRAM_IMUX38_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI3" + }, + "BRAM_L.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { + "src_wire": "BRAM_FIFO18_RDERR", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_2" + }, + "BRAM_L.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { + "src_wire": "BRAM_CTRL1_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU" + }, + "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_FIFO36_ADDRARDADDRU7": { + "src_wire": "BRAM_ADDRARDADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU7" + }, + "BRAM_L.BRAM_IMUX16_3->BRAM_IMUX_ADDRARDADDRL6": { + "src_wire": "BRAM_IMUX16_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL6" + }, + "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { + "src_wire": "BRAM_IMUX22_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE5" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { + "src_wire": "BRAM_FIFO36_DOBDOU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_3" + }, + "BRAM_L.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { + "src_wire": "BRAM_FIFO18_DOADO12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_1" + }, + "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_FIFO36_ADDRBWRADDRL8": { + "src_wire": "BRAM_ADDRBWRADDRL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL8" + }, + "BRAM_L.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { + "src_wire": "BRAM_FIFO18_DOADO13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_1" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10" + }, + "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_FIFO36_ADDRARDADDRU6": { + "src_wire": "BRAM_ADDRARDADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU6" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5" + }, + "BRAM_L.BRAM_BYP6_2->BRAM_FIFO36_WEBWEL7": { + "src_wire": "BRAM_BYP6_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL7" + }, + "BRAM_L.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { + "src_wire": "BRAM_IMUX18_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS0" + }, + "BRAM_L.BRAM_IMUX9_3->BRAM_IMUX_ADDRARDADDRU7": { + "src_wire": "BRAM_IMUX9_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU7" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1" + }, + "BRAM_L.BRAM_IMUX36_1->BRAM_IMUX_ADDRBWRADDRL8": { + "src_wire": "BRAM_IMUX36_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL8" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { + "src_wire": "BRAM_FIFO36_WRCOUNT11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_4" + }, + "BRAM_L.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { + "src_wire": "BRAM_RAMB18_DOBDO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_3" + }, + "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_RAMB18_ADDRBWRADDR9": { + "src_wire": "BRAM_ADDRBWRADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR9" + }, + "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_UTURN_ADDRARDADDRU11": { + "src_wire": "BRAM_ADDRARDADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU11" + }, + "BRAM_L.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { + "src_wire": "BRAM_CLK1_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK" + }, + "BRAM_L.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { + "src_wire": "BRAM_RAMB18_DOBDO6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_4" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13" + }, + "BRAM_L.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { + "src_wire": "BRAM_RAMB18_DOADO9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_3" + }, + "BRAM_L.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { + "src_wire": "BRAM_CLK1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKBU" + }, + "BRAM_L.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { + "src_wire": "BRAM_IMUX8_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI0" + }, + "BRAM_L.BRAM_IMUX19_3->BRAM_IMUX_ADDRARDADDRL9": { + "src_wire": "BRAM_IMUX19_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL9" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14" + }, + "BRAM_L.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { + "src_wire": "BRAM_IMUX23_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI15" + }, + "BRAM_L.BRAM_IMUX39_3->BRAM_IMUX_ADDRBWRADDRL15": { + "src_wire": "BRAM_IMUX39_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL15" + }, + "BRAM_L.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { + "src_wire": "BRAM_IMUX4_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU10" + }, + "BRAM_L.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { + "src_wire": "BRAM_IMUX9_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU12" + }, + "BRAM_L.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { + "src_wire": "BRAM_FAN1_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE4" + }, + "BRAM_L.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { + "src_wire": "BRAM_IMUX5_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN0" + }, + "BRAM_L.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { + "src_wire": "BRAM_RAMB18_DOADO7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_4" + }, + "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_CASCOUT_ADDRARDADDRU3": { + "src_wire": "BRAM_ADDRARDADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU3" + }, + "BRAM_L.BRAM_BYP3_2->BRAM_FIFO18_WEBWE3": { + "src_wire": "BRAM_BYP3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE3" + }, + "BRAM_L.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { + "src_wire": "BRAM_RAMB18_DOBDO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_3" + }, + "BRAM_L.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { + "src_wire": "BRAM_IMUX47_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS5" + }, + "BRAM_L.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { + "src_wire": "BRAM_IMUX25_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU3" + }, + "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_RAMB18_ADDRBWRADDR8": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR8" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15" + }, + "BRAM_L.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { + "src_wire": "BRAM_IMUX43_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI10" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9" + }, + "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_FIFO18_ADDRARDADDR1": { + "src_wire": "BRAM_ADDRARDADDRL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR1" + }, + "BRAM_L.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { + "src_wire": "BRAM_FIFO18_RDCOUNT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_1" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { + "src_wire": "BRAM_FIFO36_DOBDOU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_4" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10" + }, + "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_FIFO36_ADDRBWRADDRL0": { + "src_wire": "BRAM_ADDRBWRADDRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL0" + }, + "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_CASCOUT_ADDRARDADDRU11": { + "src_wire": "BRAM_ADDRARDADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU11" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8" + }, + "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_RAMB18_ADDRARDADDR8": { + "src_wire": "BRAM_ADDRARDADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR8" + }, + "BRAM_L.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { + "src_wire": "BRAM_IMUX8_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU4" + }, + "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { + "src_wire": "BRAM_IMUX37_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL2" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { + "src_wire": "BRAM_FIFO36_DOBDOU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_4" + }, + "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_FIFO36_ADDRBWRADDRL13": { + "src_wire": "BRAM_ADDRBWRADDRL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL13" + }, + "BRAM_L.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { + "src_wire": "BRAM_FIFO18_DOADO15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_2" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_3" + }, + "BRAM_L.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { + "src_wire": "BRAM_IMUX17_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU12" + }, + "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_UTURN_ADDRBWRADDRU11": { + "src_wire": "BRAM_ADDRBWRADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU11" + }, + "BRAM_L.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { + "src_wire": "BRAM_IMUX23_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPBDIP1" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { + "src_wire": "BRAM_FIFO36_RDCOUNT9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_2" + }, + "BRAM_L.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { + "src_wire": "BRAM_FIFO36_FULL", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_2" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9" + }, + "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_UTURN_ADDRBWRADDRL7": { + "src_wire": "BRAM_ADDRBWRADDRL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL7" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6" + }, + "BRAM_L.BRAM_IMUX10_1->BRAM_IMUX_ADDRARDADDRU1": { + "src_wire": "BRAM_IMUX10_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRU1" + }, + "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_FIFO18_ADDRBWRADDR3": { + "src_wire": "BRAM_ADDRBWRADDRL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR3" + }, + "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_FIFO36_ADDRBWRADDRL4": { + "src_wire": "BRAM_ADDRBWRADDRL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL4" + }, + "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_UTURN_ADDRARDADDRL12": { + "src_wire": "BRAM_ADDRARDADDRL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL12" + }, + "BRAM_L.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { + "src_wire": "BRAM_IMUX12_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI6" + }, + "BRAM_L.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { + "src_wire": "BRAM_IMUX16_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN1" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { + "src_wire": "BRAM_FIFO36_WRCOUNT8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_3" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { + "src_wire": "BRAM_FIFO36_DOBDOL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_2" + }, + "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_FIFO36_ADDRBWRADDRU6": { + "src_wire": "BRAM_ADDRBWRADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU6" + }, + "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_FIFO36_ADDRARDADDRU11": { + "src_wire": "BRAM_ADDRARDADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU11" + }, + "BRAM_L.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { + "src_wire": "BRAM_FIFO18_DOADO7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_2" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14" + }, + "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_FIFO18_ADDRBWRADDR10": { + "src_wire": "BRAM_ADDRBWRADDRL11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR10" + }, + "BRAM_L.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { + "src_wire": "BRAM_IMUX25_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT7" + }, + "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { + "src_wire": "BRAM_IMUX5_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL13" + }, + "BRAM_L.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { + "src_wire": "BRAM_RAMB18_DOBDO12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_4" + }, + "BRAM_L.BRAM_IMUX28_3->BRAM_IMUX_ADDRBWRADDRU5": { + "src_wire": "BRAM_IMUX28_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU5" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { + "src_wire": "BRAM_FIFO36_WRCOUNT12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_4" + }, + "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { + "src_wire": "BRAM_IMUX3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPL0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8" + }, + "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { + "src_wire": "BRAM_IMUX4_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPBDIP0" + }, + "BRAM_L.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { + "src_wire": "BRAM_FIFO36_RDERR", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_2" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2" + }, + "BRAM_L.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { + "src_wire": "BRAM_CLK0_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK" + }, + "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_FIFO18_ADDRBWRADDR0": { + "src_wire": "BRAM_ADDRBWRADDRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR0" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { + "src_wire": "BRAM_FIFO18_WRCOUNT10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_4" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { + "src_wire": "BRAM_FIFO36_DOBDOL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_1" + }, + "BRAM_L.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { + "src_wire": "BRAM_FIFO36_DOADOL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_0" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { + "src_wire": "BRAM_FIFO36_RDCOUNT12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_4" + }, + "BRAM_L.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { + "src_wire": "BRAM_RAMB18_DOADO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_3" + }, + "BRAM_L.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { + "src_wire": "BRAM_IMUX44_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS10" + }, + "BRAM_L.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { + "src_wire": "BRAM_FIFO36_DOADOU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_3" + }, + "BRAM_L.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { + "src_wire": "BRAM_IMUX27_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT9" + }, + "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_CASCOUT_ADDRARDADDRU7": { + "src_wire": "BRAM_ADDRARDADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU7" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12" + }, + "BRAM_L.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { + "src_wire": "BRAM_IMUX1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU1" + }, + "BRAM_L.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { + "src_wire": "BRAM_IMUX46_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS4" + }, + "BRAM_L.BRAM_BYP3_2->BRAM_FIFO36_WEBWEL3": { + "src_wire": "BRAM_BYP3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL3" + }, + "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_RAMB18_ADDRARDADDR5": { + "src_wire": "BRAM_ADDRARDADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR5" + }, + "BRAM_L.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { + "src_wire": "BRAM_FIFO36_SBITERR", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_2" + }, + "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_UTURN_ADDRARDADDRU8": { + "src_wire": "BRAM_ADDRARDADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU8" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11" + }, + "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { + "src_wire": "BRAM_IMUX33_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI8" + }, + "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_FIFO36_ADDRBWRADDRU0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU0" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15" + }, + "BRAM_L.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { + "src_wire": "BRAM_IMUX32_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS6" + }, + "BRAM_L.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { + "src_wire": "BRAM_FIFO36_RDCOUNT10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_4" + }, + "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_UTURN_ADDRBWRADDRL2": { + "src_wire": "BRAM_ADDRBWRADDRL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL2" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12" + }, + "BRAM_L.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { + "src_wire": "BRAM_FIFO36_DOADOL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14" + }, + "BRAM_L.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { + "src_wire": "BRAM_IMUX15_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU15" + }, + "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { + "src_wire": "BRAM_CTRL0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTREGB" + }, + "BRAM_L.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { + "src_wire": "BRAM_IMUX23_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU8" + }, + "BRAM_L.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { + "src_wire": "BRAM_FIFO36_DOADOL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_1" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5" + }, + "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { + "src_wire": "BRAM_IMUX36_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL2" + }, + "BRAM_L.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { + "src_wire": "BRAM_IMUX5_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTFLAGIN" + }, + "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_RAMB18_ADDRARDADDR11": { + "src_wire": "BRAM_ADDRARDADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR11" + }, + "BRAM_L.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { + "src_wire": "BRAM_FIFO36_DOADOU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_4" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9" + }, + "BRAM_L.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { + "src_wire": "BRAM_FIFO36_DOBDOU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_4" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { + "src_wire": "BRAM_FIFO36_DOBDOL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_1" + }, + "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_FIFO18_ADDRBWRADDR1": { + "src_wire": "BRAM_ADDRBWRADDRL2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR1" + }, + "BRAM_L.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { + "src_wire": "BRAM_IMUX46_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU7" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { + "src_wire": "BRAM_FIFO18_WRCOUNT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_1" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3" + }, + "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_UTURN_ADDRARDADDRU7": { + "src_wire": "BRAM_ADDRARDADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU7" + }, + "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_FIFO18_ADDRARDADDR7": { + "src_wire": "BRAM_ADDRARDADDRL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR7" + }, + "BRAM_L.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { + "src_wire": "BRAM_IMUX25_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA3" + }, + "BRAM_L.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { + "src_wire": "BRAM_IMUX14_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT4" + }, + "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { + "src_wire": "BRAM_IMUX3_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL12" + }, + "BRAM_L.BRAM_IMUX35_1->BRAM_IMUX_ADDRBWRADDRL2": { + "src_wire": "BRAM_IMUX35_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL2" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { + "src_wire": "BRAM_FIFO36_ECCPARITY2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_2" + }, + "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_CASCOUT_ADDRBWRADDRU4": { + "src_wire": "BRAM_ADDRBWRADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU4" + }, + "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_UTURN_ADDRARDADDRL4": { + "src_wire": "BRAM_ADDRARDADDRL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL4" + }, + "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_FIFO36_ADDRARDADDRU9": { + "src_wire": "BRAM_ADDRARDADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU9" + }, + "BRAM_L.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { + "src_wire": "BRAM_IMUX1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI1" + }, + "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_FIFO36_ADDRBWRADDRL12": { + "src_wire": "BRAM_ADDRBWRADDRL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL12" + }, + "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_CASCOUT_ADDRARDADDRU9": { + "src_wire": "BRAM_ADDRARDADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU9" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12" + }, + "BRAM_L.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { + "src_wire": "BRAM_IMUX10_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU5" + }, + "BRAM_L.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { + "src_wire": "BRAM_FIFO18_DOBDO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_0" + }, + "BRAM_L.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { + "src_wire": "BRAM_FIFO36_DOADOU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_3" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7" + }, + "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { + "src_wire": "BRAM_IMUX18_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ENARDEN" + }, + "BRAM_L.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { + "src_wire": "BRAM_FIFO18_DOBDO5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_1" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14" + }, + "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_UTURN_ADDRARDADDRL9": { + "src_wire": "BRAM_ADDRARDADDRL9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL9" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11" + }, + "BRAM_L.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { + "src_wire": "BRAM_FIFO18_DOBDO4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_1" + }, + "BRAM_L.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { + "src_wire": "BRAM_CLK1_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKBWRCLKU" + }, + "BRAM_L.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { + "src_wire": "BRAM_FIFO36_DOADOU15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_4" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0" + }, + "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { + "src_wire": "BRAM_IMUX28_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI2" + }, + "BRAM_L.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { + "src_wire": "BRAM_IMUX18_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI5" + }, + "BRAM_L.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { + "src_wire": "BRAM_IMUX6_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI11" + }, + "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_FIFO36_ADDRARDADDRL5": { + "src_wire": "BRAM_ADDRARDADDRL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL5" + }, + "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_FIFO18_ADDRARDADDR3": { + "src_wire": "BRAM_ADDRARDADDRL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR3" + }, + "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_FIFO36_ADDRARDADDRL6": { + "src_wire": "BRAM_ADDRARDADDRL6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL6" + }, + "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_CASCOUT_ADDRARDADDRU8": { + "src_wire": "BRAM_ADDRARDADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU8" + }, + "BRAM_L.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { + "src_wire": "BRAM_IMUX20_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS2" + }, + "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { + "src_wire": "BRAM_IMUX30_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL3" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4" + }, + "BRAM_L.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { + "src_wire": "BRAM_IMUX41_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI9" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3" + }, + "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_RAMB18_ADDRARDADDR6": { + "src_wire": "BRAM_ADDRARDADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR6" + }, + "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { + "src_wire": "BRAM_IMUX26_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI1" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14" + }, + "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_FIFO18_ADDRARDADDR2": { + "src_wire": "BRAM_ADDRARDADDRL3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR2" + }, + "BRAM_L.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { + "src_wire": "BRAM_IMUX21_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU14" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12" + }, + "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_UTURN_ADDRARDADDRL8": { + "src_wire": "BRAM_ADDRARDADDRL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL8" + }, + "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { + "src_wire": "BRAM_IMUX33_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL8" + }, + "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_RAMB18_ADDRARDADDR0": { + "src_wire": "BRAM_ADDRARDADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR0" + }, + "BRAM_L.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { + "src_wire": "BRAM_IMUX8_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN3" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4" + }, + "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { + "src_wire": "BRAM_IMUX29_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL10" + }, + "BRAM_L.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { + "src_wire": "BRAM_FAN5_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9" + }, + "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_FIFO36_ADDRARDADDRL4": { + "src_wire": "BRAM_ADDRARDADDRL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL4" + }, + "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_FIFO18_ADDRBWRADDR13": { + "src_wire": "BRAM_ADDRBWRADDRL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR13" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1" + }, + "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_FIFO36_ADDRBWRADDRL5": { + "src_wire": "BRAM_ADDRBWRADDRL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL5" + }, + "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { + "src_wire": "BRAM_IMUX46_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL14" + }, + "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { + "src_wire": "BRAM_IMUX37_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI10" + }, + "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_UTURN_ADDRBWRADDRU0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU0" + }, + "BRAM_L.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { + "src_wire": "BRAM_FAN1_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU4" + }, + "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { + "src_wire": "BRAM_IMUX39_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL11" + }, + "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_FIFO18_ADDRARDADDR5": { + "src_wire": "BRAM_ADDRARDADDRL6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR5" + }, + "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_FIFO36_ADDRBWRADDRU2": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU2" + }, + "BRAM_L.BRAM_IMUX36_3->BRAM_IMUX_ADDRBWRADDRL5": { + "src_wire": "BRAM_IMUX36_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRL5" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { + "src_wire": "BRAM_FIFO36_WRCOUNT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_1" + }, + "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_CASCOUT_ADDRBWRADDRU12": { + "src_wire": "BRAM_ADDRBWRADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU12" + }, + "BRAM_L.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { + "src_wire": "BRAM_CTRL1_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTREGARSTREG" + }, + "BRAM_L.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { + "src_wire": "BRAM_IMUX3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU2" + }, + "BRAM_L.BRAM_IMUX21_1->BRAM_IMUX_ADDRARDADDRL4": { + "src_wire": "BRAM_IMUX21_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL4" + }, + "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_FIFO18_ADDRBWRADDR7": { + "src_wire": "BRAM_ADDRBWRADDRL8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR7" + }, + "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { + "src_wire": "BRAM_CTRL0_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTREGARSTREG" + }, + "BRAM_L.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { + "src_wire": "BRAM_FIFO36_ECCPARITY7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_3" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7" + }, + "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_FIFO36_ADDRBWRADDRL1": { + "src_wire": "BRAM_ADDRBWRADDRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL1" + }, + "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { + "src_wire": "BRAM_IMUX2_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI4" + }, + "BRAM_L.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { + "src_wire": "BRAM_FIFO36_DOADOL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_1" + }, + "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { + "src_wire": "BRAM_IMUX37_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE2" + }, + "BRAM_L.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { + "src_wire": "BRAM_RAMB18_DOADO4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_4" + }, + "BRAM_L.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { + "src_wire": "BRAM_IMUX46_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS12" + }, + "BRAM_L.BRAM_IMUX30_1->BRAM_IMUX_ADDRBWRADDRU11": { + "src_wire": "BRAM_IMUX30_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU11" + }, + "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { + "src_wire": "BRAM_IMUX42_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL12" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5" + }, + "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_FIFO36_ADDRBWRADDRU13": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU13" + }, + "BRAM_L.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { + "src_wire": "BRAM_FIFO36_TSTOUT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_0" + }, + "BRAM_L.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { + "src_wire": "BRAM_IMUX35_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS9" + }, + "BRAM_L.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { + "src_wire": "BRAM_IMUX24_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU1" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4" + }, + "BRAM_L.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { + "src_wire": "BRAM_IMUX8_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU0" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { + "src_wire": "BRAM_FIFO36_WRCOUNT10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_4" + }, + "BRAM_L.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { + "src_wire": "BRAM_IMUX27_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEBU" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14" + }, + "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_CASCOUT_ADDRBWRADDRU2": { + "src_wire": "BRAM_ADDRBWRADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU2" + }, + "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_UTURN_ADDRBWRADDRU8": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU8" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5" + }, + "BRAM_L.BRAM_IMUX23_1->BRAM_IMUX_ADDRARDADDRL13": { + "src_wire": "BRAM_IMUX23_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL13" + }, + "BRAM_L.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { + "src_wire": "BRAM_CLK1_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU" + }, + "BRAM_L.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { + "src_wire": "BRAM_FIFO18_WRCOUNT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_1" + }, + "BRAM_L.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { + "src_wire": "BRAM_FIFO36_DOADOU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_4" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4" + }, + "BRAM_L.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { + "src_wire": "BRAM_RAMB18_DOBDO13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_4" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4" + }, + "BRAM_L.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { + "src_wire": "BRAM_IMUX27_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCEB" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15" + }, + "BRAM_L.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { + "src_wire": "BRAM_RAMB18_DOADO8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_2" + }, + "BRAM_L.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { + "src_wire": "BRAM_FIFO18_ALMOSTEMPTY", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_2" + }, + "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_FIFO36_ADDRARDADDRL13": { + "src_wire": "BRAM_ADDRARDADDRL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL13" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9" + }, + "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO18_ADDRARDADDR0": { + "src_wire": "BRAM_ADDRARDADDRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR0" + }, + "BRAM_L.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { + "src_wire": "BRAM_CLK1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_CLKARDCLK" + }, + "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { + "src_wire": "BRAM_IMUX32_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL1" + }, + "BRAM_L.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { + "src_wire": "BRAM_CTRL1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTREGB" + }, + "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_CASCOUT_ADDRBWRADDRU14": { + "src_wire": "BRAM_ADDRBWRADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU14" + }, + "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_UTURN_ADDRBWRADDRU1": { + "src_wire": "BRAM_ADDRBWRADDRU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU1" + }, + "BRAM_L.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { + "src_wire": "BRAM_IMUX42_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI2" + }, + "BRAM_L.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { + "src_wire": "BRAM_RAMB18_DOADO5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_4" + }, + "BRAM_L.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { + "src_wire": "BRAM_IMUX43_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU10" + }, + "BRAM_L.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { + "src_wire": "BRAM_IMUX18_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU5" + }, + "BRAM_L.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { + "src_wire": "BRAM_FIFO36_DOADOL4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_1" + }, + "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_FIFO36_ADDRARDADDRL3": { + "src_wire": "BRAM_ADDRARDADDRL3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL3" + }, + "BRAM_L.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { + "src_wire": "BRAM_RAMB18_DOBDO9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_3" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6" + }, + "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_FIFO36_ADDRARDADDRU4": { + "src_wire": "BRAM_ADDRARDADDRU4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU4" + }, + "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { + "src_wire": "BRAM_IMUX19_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEAREGCEL" + }, + "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_UTURN_ADDRARDADDRL13": { + "src_wire": "BRAM_ADDRARDADDRL13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL13" + }, + "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_CASCOUT_ADDRBWRADDRU0": { + "src_wire": "BRAM_ADDRBWRADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU0" + }, + "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_UTURN_ADDRARDADDRU14": { + "src_wire": "BRAM_ADDRARDADDRU14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU14" + }, + "BRAM_L.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { + "src_wire": "BRAM_FIFO18_DOADO14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_1" + }, + "BRAM_L.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { + "src_wire": "BRAM_FIFO36_DOADOU10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_3" + }, + "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_FIFO36_ADDRARDADDRL14": { + "src_wire": "BRAM_ADDRARDADDRL14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL14" + }, + "BRAM_L.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { + "src_wire": "BRAM_IMUX44_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS2" + }, + "BRAM_L.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { + "src_wire": "BRAM_IMUX13_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI14" + }, + "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { + "src_wire": "BRAM_CTRL0_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTRAMB" + }, + "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_RAMB18_ADDRBWRADDR7": { + "src_wire": "BRAM_ADDRBWRADDRU8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR7" + }, + "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { + "src_wire": "BRAM_IMUX6_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL6" + }, + "BRAM_L.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { + "src_wire": "BRAM_IMUX30_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE6" + }, + "BRAM_L.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { + "src_wire": "BRAM_IMUX5_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI3" + }, + "BRAM_L.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { + "src_wire": "BRAM_RAMB18_DOBDO15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_4" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6" + }, + "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { + "src_wire": "BRAM_IMUX18_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENARDENL" + }, + "BRAM_L.BRAM_IMUX20_3->BRAM_IMUX_ADDRARDADDRL5": { + "src_wire": "BRAM_IMUX20_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL5" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "src_wire": "BRAM_IMUX_ADDRARDADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0" + }, + "BRAM_L.BRAM_IMUX18_1->BRAM_IMUX_ADDRARDADDRL1": { + "src_wire": "BRAM_IMUX18_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL1" + }, + "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_UTURN_ADDRARDADDRU0": { + "src_wire": "BRAM_ADDRARDADDRU0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU0" + }, + "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { + "src_wire": "BRAM_IMUX39_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI11" + }, + "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { + "src_wire": "BRAM_IMUX7_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI14" + }, + "BRAM_L.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { + "src_wire": "BRAM_IMUX15_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI15" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRL11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { + "src_wire": "BRAM_FIFO36_DOBDOL12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_1" + }, + "BRAM_L.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { + "src_wire": "BRAM_FIFO18_DOPBDOP0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_1" + }, + "BRAM_L.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { + "src_wire": "BRAM_FIFO18_DOBDO13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_1" + }, + "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { + "src_wire": "BRAM_IMUX34_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI1" + }, + "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_UTURN_ADDRBWRADDRL6": { + "src_wire": "BRAM_ADDRBWRADDRL6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL6" + }, + "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { + "src_wire": "BRAM_IMUX41_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL4" + }, + "BRAM_L.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { + "src_wire": "BRAM_IMUX30_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT12" + }, + "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_FIFO18_ADDRBWRADDR9": { + "src_wire": "BRAM_ADDRBWRADDRL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR9" + }, + "BRAM_L.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { + "src_wire": "BRAM_FIFO36_ALMOSTFULL", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_2" + }, + "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { + "src_wire": "BRAM_IMUX33_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL3" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3" + }, + "BRAM_L.BRAM_IMUX31_3->BRAM_IMUX_ADDRARDADDRL15": { + "src_wire": "BRAM_IMUX31_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRARDADDRL15" + }, + "BRAM_L.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { + "src_wire": "BRAM_FIFO18_DOBDO8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_0" + }, + "BRAM_L.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { + "src_wire": "BRAM_IMUX13_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT3" + }, + "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_UTURN_ADDRARDADDRU5": { + "src_wire": "BRAM_ADDRARDADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU5" + }, + "BRAM_L.BRAM_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { + "src_wire": "BRAM_IMUX_ADDRARDADDRL10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10" + }, + "BRAM_L.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { + "src_wire": "BRAM_FIFO36_DOPBDOPU1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_3" + }, + "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_FIFO36_ADDRBWRADDRU9": { + "src_wire": "BRAM_ADDRBWRADDRU9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU9" + }, + "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_RAMB18_ADDRBWRADDR4": { + "src_wire": "BRAM_ADDRBWRADDRU5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR4" + }, + "BRAM_L.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { + "src_wire": "BRAM_CLK1_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_CLKBWRCLK" + }, + "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { + "src_wire": "BRAM_IMUX5_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL0" + }, + "BRAM_L.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { + "src_wire": "BRAM_RAMB18_DOPBDOP1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_3" + }, + "BRAM_L.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { + "src_wire": "BRAM_FIFO36_DOADOL15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_2" + }, + "BRAM_L.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { + "src_wire": "BRAM_FIFO36_WRCOUNT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_1" + }, + "BRAM_L.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { + "src_wire": "BRAM_RAMB18_DOBDO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_2" + }, + "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { + "src_wire": "BRAM_IMUX16_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI0" + }, + "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2" + }, + "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { + "src_wire": "BRAM_IMUX22_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL5" + }, + "BRAM_L.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { + "src_wire": "BRAM_RAMB18_DOADO12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_4" + }, + "BRAM_L.BRAM_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "src_wire": "BRAM_IMUX_ADDRBWRADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11" + }, + "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { + "src_wire": "BRAM_IMUX26_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL1" + }, + "BRAM_L.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { + "src_wire": "BRAM_FIFO36_DOBDOL7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_2" + }, + "BRAM_L.BRAM_IMUX26_1->BRAM_IMUX_ADDRBWRADDRU1": { + "src_wire": "BRAM_IMUX26_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU1" + }, + "BRAM_L.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { + "src_wire": "BRAM_IMUX43_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS1" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11" + }, + "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13" + }, + "BRAM_L.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { + "src_wire": "BRAM_IMUX4_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN2" + }, + "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_UTURN_ADDRBWRADDRU13": { + "src_wire": "BRAM_ADDRBWRADDRU13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU13" + }, + "BRAM_L.BRAM_IMUX31_1->BRAM_IMUX_ADDRBWRADDRU13": { + "src_wire": "BRAM_IMUX31_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU13" + }, + "BRAM_L.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { + "src_wire": "BRAM_FIFO36_DOADOU12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_4" + }, + "BRAM_L.BRAM_IMUX25_1->BRAM_IMUX_ADDRBWRADDRU0": { + "src_wire": "BRAM_IMUX25_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_ADDRBWRADDRU0" } }, - "tile_type": "BRAM_L" + "wires": [ + "BRAM_SW4A1_4", + "BRAM_BYP7_2", + "BRAM_EE4BEG2_0", + "BRAM_IMUX25_0", + "BRAM_IMUX2_UTURN_0", + "BRAM_FIFO18_DOBDO8", + "BRAM_IMUX25_2", + "BRAM_LOGIC_OUTS_B14_0", + "BRAM_RAMB18_DOBDO10", + "BRAM_FAN0_1", + "BRAM_EE2BEG1_3", + "BRAM_RAMB18_ADDRARDADDR4", + "BRAM_IMUX47_0", + "BRAM_RAMB18_DIBDI4", + "BRAM_IMUX31_UTURN_2", + "BRAM_NE4BEG2_0", + "BRAM_IMUX25_4", + "BRAM_IMUX23_UTURN_3", + "BRAM_FAN6_2", + "BRAM_IMUX_ADDRARDADDRL12", + "BRAM_LOGIC_OUTS_B21_4", + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_NW4END3_2", + "BRAM_IMUX_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRAM_FAN7_1", + "BRAM_UTURN_ADDRBWRADDRL4", + "BRAM_SE4BEG1_1", + "BRAM_FIFO36_DIADIU12", + "BRAM_FIFO36_DIBDIL5", + "BRAM_IMUX1_3", + "BRAM_SE2A1_1", + "BRAM_IMUX3_UTURN_4", + "BRAM_FIFO36_DOADOL10", + "BRAM_ADDRBWRADDRL7", + "BRAM_LOGIC_OUTS_B1_2", + "BRAM_EE2A1_4", + "BRAM_FIFO18_WRCOUNT3", + "BRAM_WW2END1_4", + "BRAM_RAMB18_REGCLKARDRCLK", + "BRAM_IMUX5_UTURN_0", + "BRAM_IMUX35_UTURN_2", + "BRAM_IMUX28_UTURN_4", + "BRAM_UTURN_ADDRARDADDRL4", + "BRAM_IMUX27_0", + "BRAM_IMUX36_UTURN_1", + "BRAM_WW4B2_4", + "BRAM_IMUX2_1", + "BRAM_FAN0_2", + "BRAM_IMUX12_UTURN_3", + "BRAM_EE2A1_1", + "BRAM_WR1END0_0", + "BRAM_IMUX47_UTURN_0", + "BRAM_FIFO36_WEAL3", + "BRAM_FIFO18_RDCOUNT9", + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRAM_RAMB18_DIPADIP1", + "BRAM_IMUX35_4", + "BRAM_FIFO18_ADDRBWRADDR7", + "BRAM_LH6_3", + "BRAM_EL1BEG1_4", + "BRAM_SE4BEG2_4", + "BRAM_LH7_4", + "BRAM_IMUX41_2", + "BRAM_FIFO36_DIADIL10", + "BRAM_FIFO36_DOPADOPU1", + "BRAM_CTRL1_1", + "BRAM_WW4C1_4", + "BRAM_FIFO36_ADDRARDADDRU12", + "BRAM_FIFO36_RSTRAMBL", + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRAM_FIFO36_TSTRDOS6", + "BRAM_FIFO36_REGCEAREGCEL", + "BRAM_IMUX_ADDRARDADDRU12", + "BRAM_IMUX44_UTURN_1", + "BRAM_FIFO36_DOPADOPU0", + "BRAM_FAN5_3", + "BRAM_EE4BEG0_4", + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRAM_WW4C3_0", + "BRAM_EE2A2_0", + "BRAM_IMUX44_4", + "BRAM_FIFO36_DOADOU1", + "BRAM_EE4BEG3_2", + "BRAM_IMUX25_1", + "BRAM_FIFO18_WEBWE7", + "BRAM_IMUX10_2", + "BRAM_IMUX23_0", + "BRAM_FIFO18_ADDRBWRADDR4", + "BRAM_IMUX43_UTURN_4", + "BRAM_FIFO36_TSTCNT1", + "BRAM_LOGIC_OUTS_B9_0", + "BRAM_IMUX5_4", + "BRAM_FIFO36_ADDRBWRADDRL5", + "BRAM_IMUX6_3", + "BRAM_FIFO36_ADDRBWRADDRU0", + "BRAM_FAN2_4", + "BRAM_RAMB18_ENBWREN", + "BRAM_WW4A3_1", + "BRAM_SW2A0_0", + "BRAM_IMUX25_UTURN_3", + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRAM_IMUX_ADDRARDADDRL1", + "BRAM_NE2A2_2", + "BRAM_LOGIC_OUTS_B20_4", + "BRAM_FIFO18_DOBDO5", + "BRAM_WW4C1_0", + "BRAM_BYP2_0", + "BRAM_FIFO18_DIBDI10", + "BRAM_IMUX45_UTURN_3", + "BRAM_FIFO18_ADDRBWRADDR0", + "BRAM_IMUX36_UTURN_2", + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRAM_FIFO18_DIBDI12", + "BRAM_EE2BEG2_4", + "BRAM_PMVBRAM_SELECT2", + "BRAM_IMUX23_UTURN_0", + "BRAM_IMUX25_UTURN_0", + "BRAM_IMUX14_2", + "BRAM_WL1END0_1", + "BRAM_IMUX15_3", + "BRAM_FIFO18_DIBDI3", + "BRAM_RAMB18_DOBDO13", + "BRAM_EE4A1_0", + "BRAM_FIFO36_TSTWROS7", + "BRAM_RAMB18_DOBDO14", + "BRAM_SW4END2_0", + "BRAM_IMUX47_UTURN_1", + "BRAM_RAMB18_RDCOUNT4", + "BRAM_EE4B0_3", + "BRAM_IMUX17_UTURN_1", + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRAM_FIFO36_RDCOUNT12", + "BRAM_FIFO18_ADDRARDADDR5", + "BRAM_FAN6_3", + "BRAM_FIFO36_TSTWROS9", + "BRAM_LOGIC_OUTS_B0_3", + "BRAM_UTURN_ADDRBWRADDRU3", + "BRAM_WL1END0_0", + "BRAM_WW4END1_1", + "BRAM_RAMB18_WRERR", + "BRAM_FIFO36_DOADOU4", + "BRAM_WW2A3_2", + "BRAM_EE4A1_3", + "BRAM_FIFO36_DIADIL5", + "BRAM_FIFO18_ADDRARDADDR10", + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRAM_ADDRBWRADDRU2", + "BRAM_IMUX30_UTURN_2", + "BRAM_WW2A2_4", + "BRAM_IMUX22_2", + "BRAM_IMUX26_UTURN_2", + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRAM_FIFO36_TSTOUT0", + "BRAM_SE4BEG0_4", + "BRAM_IMUX24_UTURN_1", + "BRAM_FIFO36_ADDRARDADDRU2", + "BRAM_UTURN_ADDRARDADDRL12", + "BRAM_BYP0_2", + "BRAM_IMUX34_2", + "BRAM_RAMB18_DIADI5", + "BRAM_FIFO36_WEAL1", + "BRAM_FIFO36_ADDRBWRADDRL3", + "BRAM_ADDRARDADDRU11", + "BRAM_PMVBRAM_SELECT1", + "BRAM_FIFO36_SBITERR", + "BRAM_NW4A0_0", + "BRAM_RAMB18_DOADO10", + "BRAM_UTURN_ADDRARDADDRL15", + "BRAM_RAMB18_EMPTY", + "BRAM_IMUX43_UTURN_1", + "BRAM_IMUX42_1", + "BRAM_NE4C2_2", + "BRAM_NE4BEG0_2", + "BRAM_FIFO36_TSTIN1", + "BRAM_FIFO36_RDCOUNT11", + "BRAM_NE4BEG1_2", + "BRAM_IMUX5_UTURN_1", + "BRAM_NW4A1_1", + "BRAM_UTURN_ADDRARDADDRL2", + "BRAM_FIFO36_DIPADIPU1", + "BRAM_IMUX47_4", + "BRAM_FIFO36_DOBDOU4", + "BRAM_IMUX8_4", + "BRAM_IMUX_ADDRARDADDRL15", + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRAM_RAMB18_DOADO12", + "BRAM_IMUX38_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU14", + "BRAM_FIFO18_RDCOUNT10", + "BRAM_FAN6_1", + "BRAM_EE2A1_2", + "BRAM_FIFO36_DIADIL6", + "BRAM_LH12_2", + "BRAM_NE2A0_4", + "BRAM_FIFO36_WEBWEU2", + "BRAM_IMUX2_UTURN_1", + "BRAM_FIFO36_TSTFLAGIN", + "BRAM_FIFO18_DIADI0", + "BRAM_IMUX20_3", + "BRAM_IMUX18_UTURN_2", + "BRAM_IMUX6_UTURN_1", + "BRAM_FIFO36_WRCOUNT3", + "BRAM_FIFO36_ADDRBWRADDRL11", + "BRAM_WW4A2_1", + "BRAM_SE4C2_3", + "BRAM_NE2A0_0", + "BRAM_RAMB18_WEBWE4", + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRAM_NE2A2_0", + "BRAM_FIFO18_RSTREGB", + "BRAM_FIFO18_DIBDI1", + "BRAM_LOGIC_OUTS_B12_1", + "BRAM_IMUX10_3", + "BRAM_EE4B2_1", + "BRAM_SW2A0_3", + "BRAM_FIFO18_ADDRBWRADDR12", + "BRAM_RAMB18_WRCOUNT4", + "BRAM_EE2BEG0_0", + "BRAM_IMUX2_2", + "BRAM_SW2A2_3", + "BRAM_FIFO36_ADDRARDADDRU8", + "BRAM_IMUX1_0", + "BRAM_RAMB18_WEBWE1", + "BRAM_RAMB18_RDCOUNT11", + "BRAM_FIFO36_ADDRARDADDRU7", + "BRAM_RAMB18_RDCOUNT8", + "BRAM_UTURN_ADDRARDADDRL14", + "BRAM_IMUX_ADDRARDADDRU3", + "BRAM_WL1END2_4", + "BRAM_FIFO18_RDCOUNT1", + "BRAM_EE4C1_1", + "BRAM_IMUX6_4", + "BRAM_IMUX10_4", + "BRAM_IMUX10_0", + "BRAM_FIFO36_DIADIL3", + "BRAM_IMUX14_UTURN_3", + "BRAM_IMUX28_1", + "BRAM_IMUX20_4", + "BRAM_LH2_4", + "BRAM_BYP3_1", + "BRAM_FIFO36_TSTWROS3", + "BRAM_IMUX_ADDRBWRADDRL3", + "BRAM_FIFO36_DIADIU13", + "BRAM_IMUX14_0", + "BRAM_RAMB18_RDCOUNT0", + "BRAM_SW4A3_1", + "BRAM_FIFO36_DOBDOL8", + "BRAM_IMUX29_0", + "BRAM_FIFO36_DIADIU5", + "BRAM_IMUX37_0", + "BRAM_IMUX34_1", + "BRAM_RAMB18_DIBDI13", + "BRAM_LOGIC_OUTS_B2_2", + "BRAM_NW4END1_4", + "BRAM_IMUX36_0", + "BRAM_IMUX_ADDRBWRADDRL11", + "BRAM_SW4A3_4", + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRAM_BYP3_4", + "BRAM_IMUX12_UTURN_2", + "BRAM_WW2END2_2", + "BRAM_IMUX_ADDRBWRADDRL7", + "BRAM_NW4END3_4", + "BRAM_ER1BEG0_3", + "BRAM_IMUX21_UTURN_1", + "BRAM_NW4END1_0", + "BRAM_SE4C3_2", + "BRAM_FIFO36_DIADIL4", + "BRAM_RAMB18_DIBDI11", + "BRAM_BYP2_3", + "BRAM_WL1END1_0", + "BRAM_RAMB18_DOADO7", + "BRAM_EL1BEG2_1", + "BRAM_FIFO18_DIADI7", + "BRAM_NW2A2_0", + "BRAM_RAMB18_WRCOUNT11", + "BRAM_IMUX39_1", + "BRAM_LH9_0", + "BRAM_LOGIC_OUTS_B5_0", + "BRAM_LOGIC_OUTS_B20_1", + "BRAM_IMUX26_UTURN_0", + "BRAM_FIFO36_ADDRBWRADDRU1", + "BRAM_FIFO18_WEBWE6", + "BRAM_IMUX8_2", + "BRAM_FIFO18_DIBDI6", + "BRAM_FIFO36_DOADOU3", + "BRAM_LOGIC_OUTS_B8_2", + "BRAM_FIFO36_ADDRBWRADDRU9", + "BRAM_IMUX22_0", + "BRAM_LOGIC_OUTS_B16_4", + "BRAM_IMUX23_1", + "BRAM_FIFO36_DOADOU13", + "BRAM_WW4END3_4", + "BRAM_IMUX41_UTURN_0", + "BRAM_FIFO18_ADDRBWRADDR11", + "BRAM_LOGIC_OUTS_B7_4", + "BRAM_IMUX15_2", + "BRAM_EE2A2_4", + "BRAM_EE2BEG3_2", + "BRAM_LOGIC_OUTS_B7_2", + "BRAM_IMUX9_2", + "BRAM_FIFO36_DIBDIL6", + "BRAM_IMUX23_4", + "BRAM_LOGIC_OUTS_B0_2", + "BRAM_NW2A2_3", + "BRAM_LH12_0", + "BRAM_WW4A1_3", + "BRAM_FIFO18_RDCOUNT6", + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRAM_FIFO36_DOPBDOPU0", + "BRAM_WW4END3_3", + "BRAM_RAMB18_DIADI11", + "BRAM_NE2A1_1", + "BRAM_BYP5_4", + "BRAM_RAMB18_DIBDI12", + "BRAM_FIFO18_DOADO2", + "BRAM_IMUX40_UTURN_2", + "BRAM_FIFO36_ADDRARDADDRL7", + "BRAM_ADDRARDADDRU14", + "BRAM_WW2A3_1", + "BRAM_IMUX16_UTURN_3", + "BRAM_IMUX38_UTURN_4", + "BRAM_RAMB18_ALMOSTFULL", + "BRAM_RAMB18_RSTREGARSTREG", + "BRAM_FIFO36_ADDRARDADDRL9", + "BRAM_BYP2_1", + "BRAM_NE4C2_1", + "BRAM_LH8_1", + "BRAM_RAMB18_DOPADOP0", + "BRAM_IMUX8_3", + "BRAM_FIFO18_RSTRAMARSTRAM", + "BRAM_RAMB18_DOADO8", + "BRAM_FIFO36_ADDRBWRADDRL4", + "BRAM_RAMB18_RSTRAMB", + "BRAM_IMUX23_UTURN_2", + "BRAM_LH4_0", + "BRAM_FIFO18_DIPBDIP0", + "BRAM_IMUX_ADDRBWRADDRL15", + "BRAM_CLK1_4", + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_IMUX0_3", + "BRAM_WW4A3_3", + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRAM_RAMB18_DIADI10", + "BRAM_FIFO36_DOBDOL0", + "BRAM_NE4C2_3", + "BRAM_IMUX45_UTURN_0", + "BRAM_FIFO36_DOPADOPL1", + "BRAM_RAMB18_REGCEB", + "BRAM_IMUX19_0", + "BRAM_RAMB18_ADDRBWRADDR4", + "BRAM_BLOCK_OUTS_L_B3_0", + "BRAM_FIFO36_TSTWROS8", + "BRAM_IMUX29_UTURN_2", + "BRAM_SE4C0_2", + "BRAM_WW4C3_4", + "BRAM_WW4B0_0", + "BRAM_FAN7_2", + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRAM_FIFO36_DIBDIU8", + "BRAM_IMUX9_0", + "BRAM_FIFO36_INJECTSBITERR", + "BRAM_FIFO36_ADDRARDADDRL6", + "BRAM_FIFO18_DOADO0", + "BRAM_FIFO36_RDCOUNT6", + "BRAM_EE4C3_3", + "BRAM_LH7_0", + "BRAM_FIFO18_DOBDO4", + "BRAM_UTURN_ADDRBWRADDRL10", + "BRAM_IMUX4_UTURN_1", + "BRAM_IMUX13_UTURN_2", + "BRAM_IMUX37_UTURN_1", + "BRAM_SW4A0_2", + "BRAM_EE4B2_2", + "BRAM_FIFO36_ADDRBWRADDRU7", + "BRAM_FIFO36_DIADIU7", + "BRAM_LH10_1", + "BRAM_FAN0_4", + "BRAM_IMUX7_0", + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRAM_IMUX22_4", + "BRAM_IMUX22_UTURN_4", + "BRAM_EE2BEG3_4", + "BRAM_IMUX29_UTURN_1", + "BRAM_EE4A3_4", + "BRAM_IMUX11_2", + "BRAM_WL1END0_3", + "BRAM_IMUX11_4", + "BRAM_FIFO36_DOADOL8", + "BRAM_IMUX3_UTURN_1", + "BRAM_SE4C0_0", + "BRAM_RAMB18_ENARDEN", + "BRAM_RAMB18_ADDRARDADDR6", + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRAM_IMUX24_4", + "BRAM_IMUX38_3", + "BRAM_IMUX31_3", + "BRAM_SE4C3_1", + "BRAM_RAMB18_DIADI1", + "BRAM_RAMB18_ADDRBWRADDR6", + "BRAM_IMUX44_UTURN_2", + "BRAM_ADDRARDADDRU13", + "BRAM_IMUX23_UTURN_1", + "BRAM_FIFO36_DIBDIL1", + "BRAM_FIFO18_WEBWE0", + "BRAM_UTURN_ADDRBWRADDRU4", + "BRAM_IMUX0_4", + "BRAM_EE4BEG3_0", + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRAM_SE4C2_2", + "BRAM_ADDRBWRADDRL12", + "BRAM_ER1BEG1_4", + "BRAM_BYP0_0", + "BRAM_SW4A0_1", + "BRAM_IMUX40_UTURN_0", + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRAM_FIFO36_WRCOUNT7", + "BRAM_SW4A3_2", + "BRAM_FAN6_0", + "BRAM_FIFO36_TSTCNT3", + "BRAM_IMUX46_2", + "BRAM_NW2A3_4", + "BRAM_FIFO36_DIBDIL0", + "BRAM_IMUX21_UTURN_2", + "BRAM_FIFO36_ADDRARDADDRL3", + "BRAM_WW2END1_3", + "BRAM_EE4B3_3", + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRAM_RAMB18_WEBWE3", + "BRAM_IMUX10_UTURN_4", + "BRAM_UTURN_ADDRARDADDRU9", + "BRAM_FIFO36_DOBDOU0", + "BRAM_SE2A0_1", + "BRAM_FAN7_0", + "BRAM_WW4B2_1", + "BRAM_IMUX46_1", + "BRAM_IMUX16_4", + "BRAM_LOGIC_OUTS_B17_2", + "BRAM_WW4A1_1", + "BRAM_ADDRBWRADDRL11", + "BRAM_IMUX37_UTURN_3", + "BRAM_EE4BEG0_2", + "BRAM_FIFO36_DIBDIL8", + "BRAM_WW2END2_3", + "BRAM_NW2A1_4", + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRAM_FIFO36_DIBDIL12", + "BRAM_FIFO18_DOADO6", + "BRAM_IMUX8_1", + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRAM_FIFO36_TSTCNT12", + "BRAM_WR1END0_3", + "BRAM_NW4A2_2", + "BRAM_IMUX46_0", + "BRAM_FIFO36_TSTWROS2", + "BRAM_IMUX26_UTURN_3", + "BRAM_IMUX36_UTURN_3", + "BRAM_FIFO36_RDCOUNT3", + "BRAM_FIFO36_DIBDIU5", + "BRAM_RAMB18_DOADO5", + "BRAM_IMUX1_UTURN_4", + "BRAM_UTURN_ADDRBWRADDRU14", + "BRAM_BYP2_2", + "BRAM_ADDRBWRADDRU13", + "BRAM_FIFO18_WEA3", + "BRAM_CTRL1_0", + "BRAM_WW4END1_2", + "BRAM_FIFO18_DIADI3", + "BRAM_NW4END2_2", + "BRAM_EE2BEG1_0", + "BRAM_IMUX40_2", + "BRAM_EE4A1_2", + "BRAM_NW4A2_0", + "BRAM_RAMB18_WRCOUNT3", + "BRAM_IMUX24_UTURN_2", + "BRAM_FIFO36_ADDRBWRADDRL6", + "BRAM_RAMB18_ADDRARDADDR2", + "BRAM_EE4C0_3", + "BRAM_ER1BEG0_4", + "BRAM_IMUX8_UTURN_2", + "BRAM_FIFO36_DOBDOU10", + "BRAM_FIFO36_DOADOU5", + "BRAM_IMUX46_4", + "BRAM_ADDRBWRADDRL6", + "BRAM_IMUX21_UTURN_4", + "BRAM_SW4A1_0", + "BRAM_LOGIC_OUTS_B6_2", + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRAM_PMVBRAM_SELECT4", + "BRAM_SE2A0_3", + "BRAM_RAMB18_FULL", + "BRAM_FIFO18_DIADI11", + "BRAM_FIFO36_DIADIU14", + "BRAM_ADDRARDADDRL4", + "BRAM_MONITOR_N_3", + "BRAM_IMUX33_UTURN_0", + "BRAM_RAMB18_ADDRARDADDR1", + "BRAM_IMUX42_UTURN_0", + "BRAM_EE2A2_1", + "BRAM_RAMB18_RDCOUNT3", + "BRAM_FIFO36_DIADIL2", + "BRAM_IMUX46_3", + "BRAM_IMUX18_4", + "BRAM_WR1END1_2", + "BRAM_RAMB18_CLKBWRCLK", + "BRAM_EL1BEG3_3", + "BRAM_BYP0_4", + "BRAM_IMUX18_1", + "BRAM_IMUX39_UTURN_4", + "BRAM_FIFO18_DOBDO14", + "BRAM_FIFO36_DOADOU0", + "BRAM_IMUX35_2", + "BRAM_WW2END2_1", + "BRAM_MONITOR_P_4", + "BRAM_UTURN_ADDRBWRADDRU1", + "BRAM_RAMB18_DIADI7", + "BRAM_FIFO36_DIBDIL13", + "BRAM_WW2END1_0", + "BRAM_RAMB18_DOPADOP1", + "BRAM_ADDRBWRADDRL9", + "BRAM_FIFO36_DIBDIL3", + "BRAM_LOGIC_OUTS_B2_0", + "BRAM_LH10_0", + "BRAM_ER1BEG3_3", + "BRAM_IMUX9_UTURN_0", + "BRAM_BLOCK_OUTS_L_B0_0", + "BRAM_FIFO36_ADDRBWRADDRU6", + "BRAM_NW4A0_1", + "BRAM_IMUX42_UTURN_3", + "BRAM_UTURN_ADDRBWRADDRU2", + "BRAM_IMUX1_UTURN_2", + "BRAM_FIFO18_DOADO3", + "BRAM_RAMB18_DIBDI1", + "BRAM_EE2BEG3_1", + "BRAM_FAN4_3", + "BRAM_LOGIC_OUTS_B17_1", + "BRAM_IMUX16_3", + "BRAM_EE2BEG3_3", + "BRAM_FIFO36_DOBDOU14", + "BRAM_FIFO36_ADDRARDADDRU3", + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRAM_NW2A3_2", + "BRAM_IMUX10_UTURN_0", + "BRAM_FIFO18_WEBWE2", + "BRAM_WW2A2_3", + "BRAM_FIFO36_DIADIL1", + "BRAM_FIFO18_ADDRBTIEHIGH0", + "BRAM_RAMB18_ADDRBWRADDR1", + "BRAM_FIFO36_TSTCNT8", + "BRAM_IMUX26_1", + "BRAM_IMUX7_2", + "BRAM_FAN2_1", + "BRAM_FAN1_3", + "BRAM_LOGIC_OUTS_B15_1", + "BRAM_NE4BEG0_3", + "BRAM_ADDRBWRADDRU12", + "BRAM_WW4A2_4", + "BRAM_FIFO36_DOBDOU12", + "BRAM_FIFO36_TSTWROS4", + "BRAM_CLK1_2", + "BRAM_IMUX_ADDRBWRADDRU12", + "BRAM_EL1BEG2_3", + "BRAM_IMUX3_UTURN_0", + "BRAM_NE4BEG3_0", + "BRAM_NW4END2_1", + "BRAM_IMUX33_0", + "BRAM_UTURN_ADDRBWRADDRU5", + "BRAM_FIFO36_ADDRBWRADDRL2", + "BRAM_WW4A2_3", + "BRAM_UTURN_ADDRBWRADDRL2", + "BRAM_WW2A0_2", + "BRAM_EE2A2_3", + "BRAM_FIFO36_ECCPARITY6", + "BRAM_RAMB18_ADDRBWRADDR0", + "BRAM_FIFO18_DIADI1", + "BRAM_NW2A3_1", + "BRAM_FIFO18_DIADI14", + "BRAM_IMUX9_4", + "BRAM_FAN7_3", + "BRAM_EL1BEG0_4", + "BRAM_IMUX10_UTURN_3", + "BRAM_SW2A3_2", + "BRAM_RAMB18_ADDRBWRADDR5", + "BRAM_IMUX2_4", + "BRAM_SE4BEG2_1", + "BRAM_FIFO36_ADDRARDADDRU0", + "BRAM_IMUX_ADDRARDADDRL10", + "BRAM_CTRL0_2", + "BRAM_ADDRBWRADDRU14", + "BRAM_SW4A3_0", + "BRAM_BYP1_0", + "BRAM_FIFO18_DOADO4", + "BRAM_IMUX0_UTURN_4", + "BRAM_FIFO36_DOBDOU13", + "BRAM_BLOCK_OUTS_L_B0_4", + "BRAM_IMUX13_UTURN_4", + "BRAM_FIFO36_ADDRARDADDRL8", + "BRAM_FIFO36_ADDRBWRADDRL15", + "BRAM_RAMB18_DIPBDIP1", + "BRAM_IMUX43_2", + "BRAM_BYP7_3", + "BRAM_NW4END3_0", + "BRAM_IMUX19_UTURN_2", + "BRAM_FIFO36_WEBWEL0", + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRAM_IMUX16_2", + "BRAM_EE4B3_4", + "BRAM_FIFO36_ADDRBWRADDRU3", + "BRAM_FIFO18_ADDRARDADDR1", + "BRAM_UTURN_ADDRARDADDRU0", + "BRAM_FAN0_0", + "BRAM_ADDRARDADDRL9", + "BRAM_IMUX15_UTURN_3", + "BRAM_FIFO36_WEBWEU7", + "BRAM_ADDRBWRADDRU11", + "BRAM_FIFO18_DOBDO12", + "BRAM_LOGIC_OUTS_B7_0", + "BRAM_IMUX_ADDRBWRADDRU1", + "BRAM_IMUX29_1", + "BRAM_CLK0_1", + "BRAM_EE2A0_2", + "BRAM_UTURN_ADDRARDADDRU10", + "BRAM_IMUX10_1", + "BRAM_SW4A1_2", + "BRAM_SW2A2_1", + "BRAM_IMUX17_UTURN_3", + "BRAM_IMUX37_UTURN_2", + "BRAM_FAN2_3", + "BRAM_CLK1_3", + "BRAM_UTURN_ADDRARDADDRU11", + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRAM_SE4BEG3_2", + "BRAM_IMUX30_UTURN_0", + "BRAM_FIFO36_DIPADIPU0", + "BRAM_WW4END3_0", + "BRAM_FIFO36_DOADOU14", + "BRAM_NW2A2_1", + "BRAM_RAMB18_ADDRBWRADDR2", + "BRAM_RAMB18_DOBDO15", + "BRAM_WR1END3_0", + "BRAM_EE4C1_0", + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRAM_LOGIC_OUTS_B11_4", + "BRAM_EE4B0_4", + "BRAM_EE4A2_4", + "BRAM_IMUX32_UTURN_0", + "BRAM_IMUX29_3", + "BRAM_NE4C3_2", + "BRAM_IMUX24_UTURN_0", + "BRAM_NW2A3_0", + "BRAM_EE4BEG1_2", + "BRAM_WL1END3_1", + "BRAM_IMUX24_UTURN_3", + "BRAM_UTURN_ADDRBWRADDRL11", + "BRAM_IMUX_ADDRARDADDRL6", + "BRAM_FIFO36_ADDRARDADDRU6", + "BRAM_FIFO36_DIPADIPL0", + "BRAM_EE4B1_4", + "BRAM_RAMB18_ADDRBWRADDR10", + "BRAM_IMUX22_UTURN_0", + "BRAM_IMUX25_UTURN_1", + "BRAM_IMUX_ADDRARDADDRU5", + "BRAM_FIFO18_RDCOUNT11", + "BRAM_WW4A3_0", + "BRAM_LOGIC_OUTS_B3_0", + "BRAM_IMUX31_4", + "BRAM_FIFO18_RDCOUNT4", + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRAM_FAN4_4", + "BRAM_FIFO36_WEBWEL2", + "BRAM_BLOCK_OUTS_L_B3_3", + "BRAM_IMUX3_UTURN_3", + "BRAM_FIFO36_TSTRDOS3", + "BRAM_FIFO36_DOADOU7", + "BRAM_SE2A3_1", + "BRAM_FIFO36_CASCADEOUTA_1", + "BRAM_FIFO18_RDERR", + "BRAM_RAMB18_WEA1", + "BRAM_IMUX19_3", + "BRAM_FIFO18_RDCOUNT5", + "BRAM_IMUX13_0", + "BRAM_FIFO18_ADDRBWRADDR2", + "BRAM_RAMB18_RDCOUNT10", + "BRAM_RAMB18_DOBDO4", + "BRAM_FIFO18_WRERR", + "BRAM_IMUX39_UTURN_2", + "BRAM_EL1BEG0_0", + "BRAM_LOGIC_OUTS_B18_1", + "BRAM_LH9_2", + "BRAM_ADDRBWRADDRU7", + "BRAM_FIFO36_REGCEBU", + "BRAM_IMUX40_UTURN_3", + "BRAM_FAN4_1", + "BRAM_BLOCK_OUTS_L_B0_1", + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRAM_SE4BEG1_2", + "BRAM_SW4A2_0", + "BRAM_FIFO36_DOBDOU7", + "BRAM_FIFO36_DIBDIL14", + "BRAM_WW4C0_4", + "BRAM_SE4C1_3", + "BRAM_NE4C0_0", + "BRAM_NW2A3_3", + "BRAM_ER1BEG3_1", + "BRAM_ADDRARDADDRL14", + "BRAM_IMUX34_UTURN_2", + "BRAM_IMUX6_UTURN_3", + "BRAM_WW4END1_0", + "BRAM_FIFO36_WEBWEL6", + "BRAM_LOGIC_OUTS_B7_1", + "BRAM_BYP5_3", + "BRAM_CTRL1_3", + "BRAM_FIFO18_DIADI13", + "BRAM_NE4C3_0", + "BRAM_LOGIC_OUTS_B14_2", + "BRAM_RAMB18_DOADO2", + "BRAM_FIFO36_CASCADEINB", + "BRAM_ER1BEG1_2", + "BRAM_ADDRARDADDRL7", + "BRAM_WR1END3_1", + "BRAM_NW4A0_4", + "BRAM_FIFO18_ALMOSTFULL", + "BRAM_IMUX28_4", + "BRAM_FIFO36_DIADIL9", + "BRAM_IMUX21_2", + "BRAM_FIFO36_DOADOU10", + "BRAM_LH7_2", + "BRAM_LH2_1", + "BRAM_FIFO18_WEBWE5", + "BRAM_LOGIC_OUTS_B12_0", + "BRAM_IMUX16_1", + "BRAM_FIFO36_WEBWEU5", + "BRAM_FIFO36_RDCOUNT7", + "BRAM_FIFO36_DIADIL0", + "BRAM_LOGIC_OUTS_B4_1", + "BRAM_FIFO18_DOADO12", + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRAM_RAMB18_DIBDI3", + "BRAM_FIFO36_WRCOUNT5", + "BRAM_IMUX39_UTURN_3", + "BRAM_EE4A2_2", + "BRAM_IMUX_ADDRARDADDRU0", + "BRAM_FIFO36_DIBDIU11", + "BRAM_FIFO18_WEA1", + "BRAM_SW4END0_0", + "BRAM_IMUX37_3", + "BRAM_LOGIC_OUTS_B15_0", + "BRAM_RAMB18_WRCOUNT7", + "BRAM_EE2BEG1_1", + "BRAM_IMUX2_0", + "BRAM_ADDRARDADDRU9", + "BRAM_ER1BEG2_2", + "BRAM_FIFO36_TSTCNT10", + "BRAM_RAMB18_WRCOUNT0", + "BRAM_WW4C0_2", + "BRAM_RAMB18_DOBDO3", + "BRAM_LOGIC_OUTS_B14_1", + "BRAM_LOGIC_OUTS_B20_3", + "BRAM_LOGIC_OUTS_B11_3", + "BRAM_WW4C0_3", + "BRAM_IMUX17_UTURN_0", + "BRAM_IMUX33_UTURN_1", + "BRAM_LH12_1", + "BRAM_FIFO36_TSTWROS1", + "BRAM_LOGIC_OUTS_B2_3", + "BRAM_FIFO18_DOADO8", + "BRAM_NW4END1_1", + "BRAM_FIFO18_DOBDO1", + "BRAM_FIFO36_ADDRBWRADDRU10", + "BRAM_ADDRARDADDRL13", + "BRAM_ADDRBWRADDRU10", + "BRAM_SE4C0_4", + "BRAM_IMUX6_UTURN_0", + "BRAM_IMUX31_1", + "BRAM_WW2A3_3", + "BRAM_IMUX42_4", + "BRAM_FIFO36_DIADIL11", + "BRAM_FIFO18_REGCEB", + "BRAM_CLK0_3", + "BRAM_EE2BEG0_3", + "BRAM_LOGIC_OUTS_B2_1", + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRAM_EE2A3_4", + "BRAM_ER1BEG3_2", + "BRAM_FIFO36_RSTRAMARSTRAMU", + "BRAM_IMUX16_0", + "BRAM_FIFO18_DIPBDIP1", + "BRAM_IMUX40_UTURN_1", + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRAM_IMUX30_1", + "BRAM_IMUX44_2", + "BRAM_RAMB18_ADDRBTIEHIGH0", + "BRAM_FIFO18_DOBDO6", + "BRAM_ADDRARDADDRU12", + "BRAM_BLOCK_OUTS_L_B3_4", + "BRAM_BLOCK_OUTS_L_B2_2", + "BRAM_IMUX34_3", + "BRAM_WL1END3_0", + "BRAM_FIFO36_TSTWROS10", + "BRAM_WW4A1_2", + "BRAM_ADDRARDADDRL10", + "BRAM_NE2A3_0", + "BRAM_IMUX34_4", + "BRAM_IMUX37_UTURN_0", + "BRAM_IMUX29_4", + "BRAM_WW4B3_1", + "BRAM_FIFO18_CLKARDCLK", + "BRAM_WW2END0_2", + "BRAM_SW4END2_1", + "BRAM_IMUX42_UTURN_1", + "BRAM_SW4END1_2", + "BRAM_FIFO36_WRCOUNT2", + "BRAM_RAMB18_DIBDI6", + "BRAM_IMUX34_0", + "BRAM_NW2A0_1", + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRAM_FIFO18_REGCLKARDRCLK", + "BRAM_RAMB18_ADDRARDADDR5", + "BRAM_NW2A1_1", + "BRAM_IMUX24_UTURN_4", + "BRAM_NW4A0_3", + "BRAM_UTURN_ADDRARDADDRL0", + "BRAM_IMUX27_UTURN_3", + "BRAM_IMUX34_UTURN_1", + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_WW2END3_1", + "BRAM_ER1BEG2_4", + "BRAM_FIFO36_DIADIU9", + "BRAM_IMUX32_UTURN_3", + "BRAM_LH4_2", + "BRAM_IMUX45_UTURN_1", + "BRAM_IMUX11_UTURN_3", + "BRAM_ADDRARDADDRU2", + "BRAM_IMUX18_0", + "BRAM_LOGIC_OUTS_B3_4", + "BRAM_IMUX14_UTURN_4", + "BRAM_FIFO18_RDCOUNT2", + "BRAM_ER1BEG0_0", + "BRAM_FIFO36_CLKARDCLKU", + "BRAM_FAN1_1", + "BRAM_LOGIC_OUTS_B18_3", + "BRAM_UTURN_ADDRARDADDRL9", + "BRAM_IMUX22_UTURN_3", + "BRAM_WW4A0_3", + "BRAM_EE4A0_2", + "BRAM_FIFO18_DIPADIP0", + "BRAM_IMUX_ADDRBWRADDRL2", + "BRAM_NW2A0_0", + "BRAM_FIFO36_CLKBWRCLKL", + "BRAM_IMUX45_UTURN_2", + "BRAM_WL1END1_4", + "BRAM_BLOCK_OUTS_L_B3_2", + "BRAM_LOGIC_OUTS_B10_0", + "BRAM_EE2A1_3", + "BRAM_RAMB18_ADDRARDADDR13", + "BRAM_NE2A2_3", + "BRAM_FIFO36_DOBDOL12", + "BRAM_FIFO18_DIADI2", + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRAM_IMUX29_UTURN_3", + "BRAM_IMUX3_UTURN_2", + "BRAM_FIFO36_DOBDOU1", + "BRAM_SE2A1_3", + "BRAM_NE2A2_1", + "BRAM_WW4B2_3", + "BRAM_IMUX35_UTURN_1", + "BRAM_EE4A0_1", + "BRAM_WW2A1_3", + "BRAM_WW4END0_0", + "BRAM_FIFO18_DOADO11", + "BRAM_EE2BEG2_2", + "BRAM_RAMB18_DIADI4", + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRAM_SW2A3_0", + "BRAM_ADDRARDADDRL6", + "BRAM_LOGIC_OUTS_B13_1", + "BRAM_LH8_4", + "BRAM_FIFO36_DOBDOL9", + "BRAM_LH1_1", + "BRAM_FIFO36_WEBWEL5", + "BRAM_EE2BEG2_0", + "BRAM_IMUX3_4", + "BRAM_BLOCK_OUTS_L_B0_3", + "BRAM_UTURN_ADDRBWRADDRL8", + "BRAM_FIFO36_TSTRDOS8", + "BRAM_NE2A0_2", + "BRAM_IMUX4_3", + "BRAM_SW4END2_4", + "BRAM_IMUX12_1", + "BRAM_LOGIC_OUTS_B4_3", + "BRAM_IMUX20_UTURN_2", + "BRAM_FIFO36_DOBDOU11", + "BRAM_IMUX17_UTURN_2", + "BRAM_RAMB18_DIADI6", + "BRAM_FIFO36_TSTBRAMRST", + "BRAM_UTURN_ADDRARDADDRL13", + "BRAM_LH11_2", + "BRAM_IMUX_ADDRBWRADDRL14", + "BRAM_BYP5_1", + "BRAM_BYP0_1", + "BRAM_IMUX43_1", + "BRAM_FIFO36_DIBDIU12", + "BRAM_FIFO18_DOBDO3", + "BRAM_FIFO18_WRCOUNT8", + "BRAM_BLOCK_OUTS_L_B2_3", + "BRAM_FIFO36_ADDRBWRADDRL1", + "BRAM_FIFO36_TSTWROS0", + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRAM_BYP6_2", + "BRAM_IMUX35_1", + "BRAM_NE2A1_0", + "BRAM_IMUX_ADDRARDADDRU4", + "BRAM_NW4END0_2", + "BRAM_EE2A0_4", + "BRAM_FIFO18_DIBDI5", + "BRAM_RAMB18_ADDRBTIEHIGH1", + "BRAM_WR1END2_0", + "BRAM_FAN5_1", + "BRAM_FIFO36_RDCOUNT4", + "BRAM_WW4END3_2", + "BRAM_IMUX19_UTURN_0", + "BRAM_IMUX8_UTURN_4", + "BRAM_RAMB18_ADDRATIEHIGH1", + "BRAM_EE4C1_2", + "BRAM_RAMB18_RSTREGB", + "BRAM_IMUX41_4", + "BRAM_WW2END2_4", + "BRAM_LOGIC_OUTS_B5_1", + "BRAM_WW4A1_0", + "BRAM_LH7_1", + "BRAM_IMUX24_1", + "BRAM_EE4A1_4", + "BRAM_IMUX18_UTURN_3", + "BRAM_FIFO18_WEA0", + "BRAM_IMUX11_0", + "BRAM_EE4C1_3", + "BRAM_FIFO36_DOPBDOPL0", + "BRAM_IMUX_ADDRARDADDRL13", + "BRAM_CLK1_1", + "BRAM_RAMB18_DIBDI9", + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRAM_RAMB18_DIBDI10", + "BRAM_SW2A1_2", + "BRAM_LOGIC_OUTS_B12_4", + "BRAM_FIFO18_DIADI4", + "BRAM_FIFO36_ADDRBWRADDRL10", + "BRAM_FIFO36_RSTREGBL", + "BRAM_SW2A3_1", + "BRAM_BLOCK_OUTS_L_B1_2", + "BRAM_IMUX3_2", + "BRAM_FIFO36_DIADIL14", + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRAM_EL1BEG2_4", + "BRAM_NE4C1_0", + "BRAM_IMUX35_UTURN_0", + "BRAM_FIFO36_CASCADEOUTB", + "BRAM_EL1BEG3_1", + "BRAM_FIFO18_ENBWREN", + "BRAM_UTURN_ADDRARDADDRU3", + "BRAM_SW4END0_1", + "BRAM_IMUX21_3", + "BRAM_RAMB18_WRCOUNT5", + "BRAM_IMUX_ADDRARDADDRU8", + "BRAM_EE2BEG0_4", + "BRAM_NW4A0_2", + "BRAM_IMUX41_3", + "BRAM_ADDRARDADDRL0", + "BRAM_SE4BEG2_2", + "BRAM_NW4END0_1", + "BRAM_FIFO18_DOADO9", + "BRAM_FIFO36_ADDRBWRADDRL0", + "BRAM_SE2A1_4", + "BRAM_SW2A2_2", + "BRAM_FIFO18_ADDRBWRADDR10", + "BRAM_RAMB18_ADDRBWRADDR7", + "BRAM_LOGIC_OUTS_B10_1", + "BRAM_IMUX39_UTURN_0", + "BRAM_FIFO36_ADDRBWRADDRU12", + "BRAM_IMUX17_1", + "BRAM_FIFO18_ADDRBWRADDR3", + "BRAM_RAMB18_DOBDO6", + "BRAM_NE4BEG0_4", + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRAM_IMUX_ADDRARDADDRU9", + "BRAM_FIFO36_ADDRBWRADDRL8", + "BRAM_ADDRARDADDRL12", + "BRAM_UTURN_ADDRBWRADDRU13", + "BRAM_WW2END0_4", + "BRAM_FIFO36_DIADIU11", + "BRAM_RAMB18_DOBDO9", + "BRAM_LH5_0", + "BRAM_RAMB18_DOADO6", + "BRAM_IMUX32_1", + "BRAM_WW4A0_2", + "BRAM_IMUX33_1", + "BRAM_IMUX_ADDRBWRADDRU0", + "BRAM_IMUX21_0", + "BRAM_NW4END1_3", + "BRAM_FIFO18_WEBWE4", + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRAM_FIFO36_DOADOL1", + "BRAM_IMUX5_3", + "BRAM_IMUX14_4", + "BRAM_WW4END1_4", + "BRAM_LOGIC_OUTS_B21_0", + "BRAM_SW4A1_1", + "BRAM_RAMB18_RDERR", + "BRAM_EE4BEG2_4", + "BRAM_FIFO18_WRCOUNT9", + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_IMUX21_UTURN_0", + "BRAM_IMUX21_1", + "BRAM_IMUX42_0", + "BRAM_IMUX_ADDRBWRADDRL1", + "BRAM_IMUX43_4", + "BRAM_SW4A2_4", + "BRAM_IMUX5_UTURN_3", + "BRAM_WL1END1_1", + "BRAM_RAMB18_WEA2", + "BRAM_IMUX13_3", + "BRAM_EE4C0_0", + "BRAM_FIFO36_ADDRARDADDRL5", + "BRAM_FIFO36_DOPBDOPL1", + "BRAM_IMUX23_2", + "BRAM_IMUX_ADDRBWRADDRL13", + "BRAM_RAMB18_WEBWE5", + "BRAM_IMUX16_UTURN_1", + "BRAM_EE4BEG2_3", + "BRAM_FIFO18_DOBDO15", + "BRAM_IMUX33_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU5", + "BRAM_FIFO18_DOADO13", + "BRAM_FIFO36_WEBWEL7", + "BRAM_BYP6_1", + "BRAM_IMUX31_2", + "BRAM_FIFO36_DIADIU8", + "BRAM_RAMB18_ADDRBWRADDR12", + "BRAM_WW2END3_2", + "BRAM_LH11_4", + "BRAM_FIFO36_ENARDENU", + "BRAM_ADDRARDADDRU1", + "BRAM_FIFO36_ENARDENL", + "BRAM_CTRL0_0", + "BRAM_IMUX28_UTURN_1", + "BRAM_IMUX39_3", + "BRAM_NW4A3_1", + "BRAM_EE4BEG3_4", + "BRAM_UTURN_ADDRBWRADDRU7", + "BRAM_SW2A1_1", + "BRAM_IMUX39_2", + "BRAM_SE4C3_4", + "BRAM_FIFO36_DOBDOU5", + "BRAM_FIFO36_DIBDIU6", + "BRAM_LH1_4", + "BRAM_IMUX9_UTURN_3", + "BRAM_IMUX4_4", + "BRAM_WW2END3_3", + "BRAM_SW4END0_4", + "BRAM_NW4A3_4", + "BRAM_IMUX0_UTURN_0", + "BRAM_SW4END1_0", + "BRAM_IMUX11_3", + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRAM_FIFO18_DOADO14", + "BRAM_IMUX38_2", + "BRAM_IMUX_ADDRBWRADDRL12", + "BRAM_FIFO36_FULL", + "BRAM_LH2_3", + "BRAM_WW4B3_2", + "BRAM_FIFO36_REGCLKARDRCLKU", + "BRAM_IMUX28_UTURN_0", + "BRAM_UTURN_ADDRARDADDRU4", + "BRAM_NW4A3_3", + "BRAM_LOGIC_OUTS_B1_4", + "BRAM_ER1BEG1_1", + "BRAM_BYP0_3", + "BRAM_FIFO36_WRCOUNT8", + "BRAM_FIFO18_DOADO1", + "BRAM_IMUX15_UTURN_1", + "BRAM_FIFO18_REGCEAREGCE", + "BRAM_NE4BEG3_2", + "BRAM_RAMB18_ADDRARDADDR3", + "BRAM_LOGIC_OUTS_B14_3", + "BRAM_FIFO18_DIBDI7", + "BRAM_RAMB18_DOADO0", + "BRAM_LOGIC_OUTS_B17_3", + "BRAM_LOGIC_OUTS_B1_1", + "BRAM_LOGIC_OUTS_B22_1", + "BRAM_FIFO36_TSTRDOS12", + "BRAM_FIFO36_TSTCNT2", + "BRAM_IMUX22_1", + "BRAM_IMUX1_1", + "BRAM_IMUX38_1", + "BRAM_FIFO36_ECCPARITY5", + "BRAM_UTURN_ADDRBWRADDRU9", + "BRAM_LOGIC_OUTS_B19_1", + "BRAM_FIFO36_ECCPARITY4", + "BRAM_IMUX11_UTURN_4", + "BRAM_SE4C3_3", + "BRAM_SE4BEG3_4", + "BRAM_IMUX12_UTURN_0", + "BRAM_EE2A0_0", + "BRAM_BYP7_4", + "BRAM_IMUX31_0", + "BRAM_IMUX9_UTURN_4", + "BRAM_FIFO36_DIBDIU3", + "BRAM_IMUX6_0", + "BRAM_FIFO36_DIPADIPL1", + "BRAM_IMUX12_0", + "BRAM_WW2A1_0", + "BRAM_ADDRBWRADDRU3", + "BRAM_LH8_3", + "BRAM_LOGIC_OUTS_B15_4", + "BRAM_IMUX42_2", + "BRAM_FIFO36_TSTCNT5", + "BRAM_LOGIC_OUTS_B16_1", + "BRAM_IMUX38_UTURN_2", + "BRAM_IMUX_ADDRBWRADDRU3", + "BRAM_IMUX47_UTURN_3", + "BRAM_RAMB18_DIBDI0", + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRAM_EE4C3_1", + "BRAM_FIFO36_ADDRBWRADDRU2", + "BRAM_WW4C2_4", + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRAM_WW4B0_3", + "BRAM_NW2A0_3", + "BRAM_IMUX44_UTURN_3", + "BRAM_IMUX_ADDRARDADDRU2", + "BRAM_FIFO18_RDCOUNT7", + "BRAM_FIFO18_DOPADOP1", + "BRAM_IMUX_ADDRARDADDRL2", + "BRAM_IMUX27_UTURN_4", + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRAM_ADDRBWRADDRL4", + "BRAM_BYP6_3", + "BRAM_ADDRARDADDRL11", + "BRAM_RAMB18_DOPBDOP0", + "BRAM_SW4A3_3", + "BRAM_LOGIC_OUTS_B10_2", + "BRAM_FIFO36_DOADOL6", + "BRAM_SE2A0_4", + "BRAM_UTURN_ADDRBWRADDRL14", + "BRAM_RAMB18_DOADO15", + "BRAM_LOGIC_OUTS_B5_3", + "BRAM_IMUX15_UTURN_0", + "BRAM_FIFO36_DIBDIL15", + "BRAM_IMUX3_1", + "BRAM_FIFO36_DIBDIU14", + "BRAM_SE2A2_1", + "BRAM_WW4A1_4", + "BRAM_IMUX28_3", + "BRAM_FIFO36_DIADIU10", + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRAM_EE4B1_1", + "BRAM_FIFO36_TSTCNT7", + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRAM_UTURN_ADDRBWRADDRL5", + "BRAM_RAMB18_RDCOUNT1", + "BRAM_LOGIC_OUTS_B6_0", + "BRAM_FIFO36_EMPTY", + "BRAM_EE4C1_4", + "BRAM_NW4A3_0", + "BRAM_FIFO18_DIADI9", + "BRAM_IMUX37_1", + "BRAM_NE4C0_1", + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRAM_FIFO36_DOADOL11", + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRAM_LOGIC_OUTS_B6_4", + "BRAM_LOGIC_OUTS_B22_2", + "BRAM_FIFO36_WEAU1", + "BRAM_IMUX27_2", + "BRAM_FIFO36_DOBDOL11", + "BRAM_IMUX25_3", + "BRAM_IMUX17_3", + "BRAM_IMUX37_UTURN_4", + "BRAM_IMUX46_UTURN_3", + "BRAM_RAMB18_DIBDI8", + "BRAM_FIFO36_TSTIN4", + "BRAM_WW4END0_3", + "BRAM_FIFO36_ADDRARDADDRL4", + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRAM_WW4B0_4", + "BRAM_IMUX_ADDRBWRADDRU2", + "BRAM_UTURN_ADDRBWRADDRU11", + "BRAM_FIFO36_TSTOUT3", + "BRAM_IMUX45_4", + "BRAM_LH10_2", + "BRAM_LOGIC_OUTS_B23_0", + "BRAM_IMUX39_UTURN_1", + "BRAM_FIFO36_RDERR", + "BRAM_IMUX15_UTURN_4", + "BRAM_FIFO36_DOADOL7", + "BRAM_LOGIC_OUTS_B5_2", + "BRAM_SE2A3_4", + "BRAM_IMUX42_UTURN_4", + "BRAM_IMUX19_UTURN_3", + "BRAM_LOGIC_OUTS_B18_0", + "BRAM_FIFO36_TSTCNT6", + "BRAM_UTURN_ADDRBWRADDRU10", + "BRAM_FIFO18_ADDRARDADDR9", + "BRAM_FIFO36_ADDRARDADDRU5", + "BRAM_IMUX7_1", + "BRAM_FIFO36_ADDRARDADDRL2", + "BRAM_FIFO36_RDCOUNT10", + "BRAM_WW2END1_2", + "BRAM_NE4C1_4", + "BRAM_FIFO36_REGCLKBL", + "BRAM_BYP6_0", + "BRAM_IMUX16_UTURN_2", + "BRAM_IMUX20_2", + "BRAM_NE2A3_2", + "BRAM_WR1END0_4", + "BRAM_FIFO18_ADDRATIEHIGH1", + "BRAM_BYP1_3", + "BRAM_IMUX32_2", + "BRAM_WR1END0_1", + "BRAM_FIFO36_TSTOFF", + "BRAM_EL1BEG2_0", + "BRAM_NE4BEG2_4", + "BRAM_FIFO36_DOADOL13", + "BRAM_LOGIC_OUTS_B15_3", + "BRAM_WW4END1_3", + "BRAM_FAN3_3", + "BRAM_SW4END1_1", + "BRAM_ADDRBWRADDRL13", + "BRAM_FIFO36_ADDRBWRADDRL13", + "BRAM_IMUX31_UTURN_3", + "BRAM_FIFO18_DIBDI0", + "BRAM_EE4A1_1", + "BRAM_EE4B0_1", + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRAM_IMUX_ADDRBWRADDRL5", + "BRAM_IMUX35_UTURN_4", + "BRAM_FIFO18_DIBDI15", + "BRAM_ADDRBWRADDRL3", + "BRAM_FIFO36_DOADOU6", + "BRAM_NW2A1_0", + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRAM_CTRL0_4", + "BRAM_LOGIC_OUTS_B9_1", + "BRAM_FIFO36_TSTWROS11", + "BRAM_FIFO36_INJECTDBITERR", + "BRAM_IMUX_ADDRBWRADDRU11", + "BRAM_IMUX4_UTURN_3", + "BRAM_FIFO36_DIADIU0", + "BRAM_IMUX0_UTURN_2", + "BRAM_FIFO36_DIADIU1", + "BRAM_ADDRBWRADDRU5", + "BRAM_LOGIC_OUTS_B6_1", + "BRAM_SW2A1_3", + "BRAM_IMUX13_UTURN_0", + "BRAM_IMUX32_UTURN_4", + "BRAM_FIFO18_DIPADIP1", + "BRAM_IMUX17_UTURN_4", + "BRAM_SE4BEG0_0", + "BRAM_FIFO18_WEA2", + "BRAM_FIFO36_WRERR", + "BRAM_BLOCK_OUTS_L_B1_4", + "BRAM_ADDRBWRADDRU0", + "BRAM_RAMB18_ADDRARDADDR10", + "BRAM_FIFO36_DIBDIU10", + "BRAM_IMUX5_1", + "BRAM_EL1BEG2_2", + "BRAM_LH9_1", + "BRAM_NE4C1_1", + "BRAM_IMUX27_UTURN_0", + "BRAM_RAMB18_RDCOUNT2", + "BRAM_BYP4_1", + "BRAM_FIFO36_CASCADEINA", + "BRAM_FAN1_0", + "BRAM_IMUX_ADDRARDADDRU14", + "BRAM_RAMB18_WRCOUNT2", + "BRAM_EE4A2_3", + "BRAM_IMUX32_4", + "BRAM_EL1BEG1_1", + "BRAM_FIFO36_ADDRBWRADDRL9", + "BRAM_IMUX32_0", + "BRAM_WW4A3_4", + "BRAM_IMUX0_1", + "BRAM_IMUX7_4", + "BRAM_FIFO36_CLKBWRCLKU", + "BRAM_IMUX32_UTURN_2", + "BRAM_IMUX_ADDRBWRADDRU10", + "BRAM_FIFO36_ADDRARDADDRL10", + "BRAM_PMVBRAM_O_1", + "BRAM_FIFO36_DOBDOL7", + "BRAM_FIFO18_DIADI12", + "BRAM_ADDRBWRADDRU8", + "BRAM_IMUX14_UTURN_1", + "BRAM_WW4C2_3", + "BRAM_IMUX1_UTURN_3", + "BRAM_EE4C0_1", + "BRAM_LOGIC_OUTS_B9_3", + "BRAM_NE4BEG1_1", + "BRAM_FIFO18_ADDRARDADDR12", + "BRAM_IMUX6_1", + "BRAM_FIFO36_WEBWEL4", + "BRAM_FIFO36_RSTREGARSTREGU", + "BRAM_WW4A0_1", + "BRAM_FIFO36_ADDRARDADDRL11", + "BRAM_SE4C0_1", + "BRAM_IMUX1_4", + "BRAM_WW4A2_2", + "BRAM_ER1BEG1_3", + "BRAM_FIFO36_ENBWRENU", + "BRAM_FIFO36_TSTRDOS4", + "BRAM_FIFO36_DOBDOL2", + "BRAM_WW2END0_0", + "BRAM_LH12_3", + "BRAM_UTURN_ADDRARDADDRL5", + "BRAM_FIFO36_DOBDOL15", + "BRAM_SW4END0_2", + "BRAM_LH11_0", + "BRAM_RAMB18_DIPADIP0", + "BRAM_WW4C2_1", + "BRAM_ADDRARDADDRU0", + "BRAM_CTRL1_2", + "BRAM_FIFO36_TSTRDOS5", + "BRAM_IMUX41_1", + "BRAM_IMUX10_UTURN_1", + "BRAM_IMUX8_UTURN_0", + "BRAM_FIFO36_DOADOU12", + "BRAM_IMUX18_UTURN_0", + "BRAM_SE4C1_0", + "BRAM_SE4BEG1_3", + "BRAM_IMUX7_3", + "BRAM_FIFO36_DIBDIU13", + "BRAM_FIFO36_WRCOUNT1", + "BRAM_WL1END2_3", + "BRAM_FIFO36_WRCOUNT10", + "BRAM_IMUX39_0", + "BRAM_ADDRBWRADDRL0", + "BRAM_FAN0_3", + "BRAM_IMUX5_2", + "BRAM_LOGIC_OUTS_B17_0", + "BRAM_FIFO36_WEAU2", + "BRAM_FIFO36_WRCOUNT11", + "BRAM_LH2_2", + "BRAM_FAN1_2", + "BRAM_WR1END1_4", + "BRAM_IMUX_ADDRARDADDRU1", + "BRAM_NE2A3_1", + "BRAM_IMUX19_4", + "BRAM_FIFO18_DOBDO7", + "BRAM_WW4A0_4", + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRAM_WW4B2_2", + "BRAM_NE2A3_3", + "BRAM_RAMB18_RDCOUNT9", + "BRAM_FIFO36_DOBDOL14", + "BRAM_IMUX42_UTURN_2", + "BRAM_FIFO36_DOBDOU8", + "BRAM_FIFO18_ADDRBWRADDR6", + "BRAM_IMUX43_UTURN_0", + "BRAM_LOGIC_OUTS_B15_2", + "BRAM_LH4_1", + "BRAM_IMUX_ADDRARDADDRU6", + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRAM_LOGIC_OUTS_B11_2", + "BRAM_IMUX2_UTURN_4", + "BRAM_FIFO18_ADDRBWRADDR8", + "BRAM_LOGIC_OUTS_B21_3", + "BRAM_EE2BEG0_2", + "BRAM_SW4END3_1", + "BRAM_FIFO18_DOADO15", + "BRAM_IMUX38_4", + "BRAM_IMUX_ADDRARDADDRU11", + "BRAM_LOGIC_OUTS_B22_3", + "BRAM_FIFO36_ADDRBWRADDRL12", + "BRAM_LH5_2", + "BRAM_FIFO36_DOADOL0", + "BRAM_FIFO36_TSTCNT9", + "BRAM_SE2A3_2", + "BRAM_IMUX38_0", + "BRAM_LOGIC_OUTS_B10_4", + "BRAM_FIFO36_ADDRARDADDRL14", + "BRAM_IMUX30_2", + "BRAM_FIFO36_DIBDIL4", + "BRAM_SW2A3_3", + "BRAM_EE2BEG1_4", + "BRAM_EE4BEG1_4", + "BRAM_ER1BEG1_0", + "BRAM_SW4END1_3", + "BRAM_LOGIC_OUTS_B23_2", + "BRAM_FIFO36_ADDRARDADDRU4", + "BRAM_FIFO36_DIADIU3", + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRAM_FAN4_0", + "BRAM_EE2A0_3", + "BRAM_LH8_2", + "BRAM_EE2A1_0", + "BRAM_EE4C2_2", + "BRAM_FIFO36_TSTRDCNTOFF", + "BRAM_IMUX0_2", + "BRAM_IMUX_ADDRBWRADDRU9", + "BRAM_EE4B1_0", + "BRAM_WW4C0_1", + "BRAM_FIFO18_DIBDI2", + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRAM_NW2A2_4", + "BRAM_RAMB18_WRCOUNT8", + "BRAM_SW2A0_4", + "BRAM_FIFO36_WRCOUNT12", + "BRAM_ADDRBWRADDRU1", + "BRAM_IMUX_ADDRBWRADDRL10", + "BRAM_BLOCK_OUTS_L_B1_1", + "BRAM_EE4BEG0_1", + "BRAM_IMUX4_UTURN_4", + "BRAM_ADDRBWRADDRL2", + "BRAM_LOGIC_OUTS_B0_1", + "BRAM_FIFO36_DOADOL9", + "BRAM_FIFO36_RSTREGBU", + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRAM_WW4B1_2", + "BRAM_EE4B3_2", + "BRAM_RAMB18_DOBDO1", + "BRAM_RAMB18_WEBWE0", + "BRAM_EE2BEG0_1", + "BRAM_IMUX33_UTURN_4", + "BRAM_BYP1_4", + "BRAM_FIFO36_TSTOUT1", + "BRAM_IMUX47_UTURN_4", + "BRAM_FAN3_4", + "BRAM_LOGIC_OUTS_B10_3", + "BRAM_FIFO36_DOADOL2", + "BRAM_WL1END0_2", + "BRAM_EE4C3_0", + "BRAM_BYP4_0", + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRAM_LOGIC_OUTS_B3_1", + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRAM_IMUX_ADDRBWRADDRL9", + "BRAM_LH10_4", + "BRAM_RAMB18_DOADO11", + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRAM_FIFO18_ADDRBWRADDR9", + "BRAM_FIFO18_ADDRARDADDR6", + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRAM_WW4B3_0", + "BRAM_LH9_3", + "BRAM_NE2A3_4", + "BRAM_RAMB18_DOBDO7", + "BRAM_EE4B2_0", + "BRAM_FIFO18_WRCOUNT10", + "BRAM_ER1BEG0_1", + "BRAM_IMUX41_UTURN_3", + "BRAM_FIFO18_DOBDO2", + "BRAM_SE4C1_1", + "BRAM_FIFO36_ECCPARITY2", + "BRAM_FIFO36_WRCOUNT9", + "BRAM_SW4A0_0", + "BRAM_FIFO18_ADDRARDADDR0", + "BRAM_BLOCK_OUTS_L_B2_1", + "BRAM_FIFO18_DIADI8", + "BRAM_FIFO36_DOPADOPL0", + "BRAM_UTURN_ADDRBWRADDRU8", + "BRAM_ER1BEG3_4", + "BRAM_FIFO18_DIBDI4", + "BRAM_NE4C3_3", + "BRAM_FAN3_2", + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRAM_LH4_3", + "BRAM_FIFO18_DOBDO13", + "BRAM_RAMB18_WEA0", + "BRAM_FIFO36_ADDRARDADDRU13", + "BRAM_FIFO36_DIPBDIPU1", + "BRAM_RAMB18_RSTRAMARSTRAM", + "BRAM_EE4A2_1", + "BRAM_EE4C3_2", + "BRAM_IMUX11_1", + "BRAM_FIFO36_DOBDOU6", + "BRAM_IMUX18_2", + "BRAM_FIFO36_TSTRDOS9", + "BRAM_IMUX26_4", + "BRAM_IMUX44_1", + "BRAM_IMUX5_UTURN_2", + "BRAM_LOGIC_OUTS_B2_4", + "BRAM_IMUX34_UTURN_4", + "BRAM_RAMB18_WEA3", + "BRAM_IMUX16_UTURN_4", + "BRAM_IMUX13_1", + "BRAM_EE4B1_2", + "BRAM_LOGIC_OUTS_B19_4", + "BRAM_IMUX36_3", + "BRAM_EE4A0_3", + "BRAM_NE4C1_2", + "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "BRAM_SW4A1_3", + "BRAM_IMUX22_UTURN_1", + "BRAM_IMUX45_3", + "BRAM_EE2A3_3", + "BRAM_RAMB18_WEBWE6", + "BRAM_IMUX47_1", + "BRAM_WL1END3_2", + "BRAM_LOGIC_OUTS_B1_0", + "BRAM_LH8_0", + "BRAM_UTURN_ADDRBWRADDRL9", + "BRAM_FAN3_0", + "BRAM_IMUX1_2", + "BRAM_WR1END1_0", + "BRAM_NE4C0_2", + "BRAM_FIFO36_DOBDOL10", + "BRAM_IMUX_ADDRARDADDRU10", + "BRAM_CTRL0_1", + "BRAM_SE4C2_1", + "BRAM_IMUX9_UTURN_1", + "BRAM_IMUX9_1", + "BRAM_ADDRBWRADDRU6", + "BRAM_FIFO36_ADDRBWRADDRL7", + "BRAM_IMUX3_3", + "BRAM_LOGIC_OUTS_B16_0", + "BRAM_IMUX11_UTURN_1", + "BRAM_FIFO36_ADDRBWRADDRU5", + "BRAM_IMUX29_UTURN_0", + "BRAM_SW4END2_3", + "BRAM_FIFO36_ADDRARDADDRU9", + "BRAM_IMUX40_UTURN_4", + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRAM_IMUX44_UTURN_4", + "BRAM_RAMB18_ADDRBWRADDR11", + "BRAM_WW4END0_2", + "BRAM_WW2A3_4", + "BRAM_WR1END2_4", + "BRAM_IMUX18_UTURN_4", + "BRAM_FIFO18_ADDRARDADDR13", + "BRAM_IMUX_ADDRARDADDRL11", + "BRAM_EE2BEG3_0", + "BRAM_WR1END2_3", + "BRAM_RAMB18_DIADI3", + "BRAM_FAN2_0", + "BRAM_ER1BEG3_0", + "BRAM_IMUX40_1", + "BRAM_FIFO36_DOADOL3", + "BRAM_UTURN_ADDRBWRADDRL6", + "BRAM_WW4B1_4", + "BRAM_UTURN_ADDRARDADDRL10", + "BRAM_NE4C3_1", + "BRAM_UTURN_ADDRARDADDRU13", + "BRAM_NE4BEG2_1", + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRAM_RAMB18_CLKARDCLK", + "BRAM_BYP1_2", + "BRAM_FIFO18_ADDRBWRADDR5", + "BRAM_EE4C2_3", + "BRAM_IMUX13_UTURN_3", + "BRAM_IMUX36_2", + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRAM_RAMB18_DOPBDOP1", + "BRAM_LH3_1", + "BRAM_RAMB18_DOADO3", + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRAM_WL1END2_2", + "BRAM_RAMB18_DOBDO8", + "BRAM_NE4BEG3_4", + "BRAM_IMUX_ADDRBWRADDRU4", + "BRAM_FIFO36_DOADOU2", + "BRAM_WW2A0_0", + "BRAM_EE4BEG1_3", + "BRAM_FIFO36_CASCADEOUTB_1", + "BRAM_NE4BEG1_0", + "BRAM_FIFO18_ADDRARDADDR4", + "BRAM_SE4BEG3_0", + "BRAM_FIFO36_DOADOU9", + "BRAM_FIFO36_REGCEAREGCEU", + "BRAM_FIFO18_ADDRBWRADDR1", + "BRAM_EE4B0_0", + "BRAM_SW4END3_2", + "BRAM_NW2A0_4", + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRAM_SE4C1_4", + "BRAM_BYP5_2", + "BRAM_FIFO36_TSTCNT0", + "BRAM_LH6_2", + "BRAM_LH1_3", + "BRAM_IMUX47_3", + "BRAM_FIFO36_WRCOUNT6", + "BRAM_FIFO36_DOBDOL5", + "BRAM_LH3_2", + "BRAM_WR1END0_2", + "BRAM_SW4END0_3", + "BRAM_NW4END0_4", + "BRAM_LOGIC_OUTS_B21_1", + "BRAM_RAMB18_DIBDI15", + "BRAM_FIFO36_RSTRAMBU", + "BRAM_WW2END2_0", + "BRAM_NW4END2_0", + "BRAM_UTURN_ADDRBWRADDRL1", + "BRAM_RAMB18_DIBDI7", + "BRAM_CLK0_4", + "BRAM_FIFO36_DOPBDOPU1", + "BRAM_WW4END0_4", + "BRAM_IMUX43_3", + "BRAM_NW2A1_3", + "BRAM_FIFO18_ADDRARDADDR3", + "BRAM_FIFO18_DIADI6", + "BRAM_NE2A2_4", + "BRAM_FIFO36_DIBDIU1", + "BRAM_FIFO18_RDCOUNT3", + "BRAM_BYP2_4", + "BRAM_RAMB18_DOADO4", + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRAM_IMUX28_UTURN_3", + "BRAM_FIFO36_ADDRBWRADDRU13", + "BRAM_WW4B1_1", + "BRAM_FIFO36_ALMOSTFULL", + "BRAM_FIFO18_RSTREGARSTREG", + "BRAM_IMUX26_UTURN_1", + "BRAM_WW4B0_1", + "BRAM_WW2A2_2", + "BRAM_NE2A1_2", + "BRAM_LOGIC_OUTS_B17_4", + "BRAM_FIFO36_DOADOL12", + "BRAM_FAN7_4", + "BRAM_WW4END2_2", + "BRAM_FIFO36_ECCPARITY3", + "BRAM_IMUX47_2", + "BRAM_NW4A1_0", + "BRAM_NE2A0_1", + "BRAM_SE2A2_2", + "BRAM_IMUX35_3", + "BRAM_UTURN_ADDRBWRADDRL15", + "BRAM_FAN6_4", + "BRAM_SE2A0_0", + "BRAM_WW2END3_0", + "BRAM_ADDRBWRADDRL5", + "BRAM_IMUX20_UTURN_1", + "BRAM_FIFO18_DOBDO11", + "BRAM_RAMB18_DIBDI14", + "BRAM_LH4_4", + "BRAM_IMUX45_1", + "BRAM_FIFO36_DOBDOU15", + "BRAM_FIFO36_WEAU3", + "BRAM_EE2A3_2", + "BRAM_NW4END0_3", + "BRAM_FIFO36_ADDRARDADDRL12", + "BRAM_WW2A0_1", + "BRAM_WW4C3_1", + "BRAM_FIFO36_DOBDOL4", + "BRAM_FIFO36_DIADIL12", + "BRAM_SE4C2_0", + "BRAM_FIFO36_DIADIU4", + "BRAM_IMUX_ADDRBWRADDRU7", + "BRAM_FIFO36_TSTRDOS0", + "BRAM_FIFO36_DIPBDIPL0", + "BRAM_IMUX4_UTURN_2", + "BRAM_FAN4_2", + "BRAM_SW4A0_3", + "BRAM_EE4BEG3_1", + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRAM_SW2A3_4", + "BRAM_EL1BEG1_0", + "BRAM_BYP4_4", + "BRAM_IMUX29_UTURN_4", + "BRAM_LOGIC_OUTS_B13_2", + "BRAM_EL1BEG0_1", + "BRAM_NE4C1_3", + "BRAM_IMUX_ADDRBWRADDRU14", + "BRAM_FIFO18_ADDRARDADDR11", + "BRAM_PMVBRAM_ODIV4", + "BRAM_LH1_2", + "BRAM_IMUX0_UTURN_3", + "BRAM_FIFO36_REGCLKARDRCLKL", + "BRAM_IMUX20_UTURN_0", + "BRAM_WW2A0_4", + "BRAM_NE4C3_4", + "BRAM_FIFO36_TSTIN0", + "BRAM_FIFO36_DIPBDIPU0", + "BRAM_NE4C0_3", + "BRAM_SW2A0_1", + "BRAM_EE2BEG2_3", + "BRAM_SE2A2_0", + "BRAM_BLOCK_OUTS_L_B1_3", + "BRAM_BLOCK_OUTS_L_B1_0", + "BRAM_RAMB18_WRCOUNT6", + "BRAM_FIFO18_DIADI10", + "BRAM_FIFO36_ALMOSTEMPTY", + "BRAM_RAMB18_WEBWE2", + "BRAM_MONITOR_N_2", + "BRAM_UTURN_ADDRBWRADDRU12", + "BRAM_FIFO36_DOBDOU2", + "BRAM_IMUX25_UTURN_4", + "BRAM_FIFO36_DBITERR", + "BRAM_SE4C2_4", + "BRAM_NE4C2_0", + "BRAM_FIFO18_WRCOUNT4", + "BRAM_RAMB18_REGCLKB", + "BRAM_BYP1_1", + "BRAM_IMUX32_UTURN_1", + "BRAM_RAMB18_ADDRBWRADDR9", + "BRAM_IMUX44_3", + "BRAM_FIFO36_RDCOUNT8", + "BRAM_IMUX46_UTURN_4", + "BRAM_WW2A1_4", + "BRAM_FIFO18_DOBDO9", + "BRAM_LOGIC_OUTS_B0_4", + "BRAM_FIFO36_DIBDIL10", + "BRAM_SE4BEG3_3", + "BRAM_ER1BEG2_0", + "BRAM_IMUX_ADDRBWRADDRL4", + "BRAM_EE4BEG3_3", + "BRAM_FIFO36_DOBDOL3", + "BRAM_LOGIC_OUTS_B1_3", + "BRAM_IMUX7_UTURN_0", + "BRAM_IMUX41_UTURN_2", + "BRAM_EE4B1_3", + "BRAM_IMUX14_1", + "BRAM_FIFO18_DIBDI9", + "BRAM_FIFO18_WRCOUNT0", + "BRAM_SE2A2_3", + "BRAM_RAMB18_DIBDI5", + "BRAM_LOGIC_OUTS_B8_1", + "BRAM_WL1END0_4", + "BRAM_RAMB18_DIADI0", + "BRAM_ADDRBWRADDRL10", + "BRAM_BYP3_3", + "BRAM_IMUX26_3", + "BRAM_FIFO36_WEBWEL1", + "BRAM_IMUX5_0", + "BRAM_ADDRBWRADDRU4", + "BRAM_UTURN_ADDRARDADDRU6", + "BRAM_IMUX29_2", + "BRAM_FIFO36_TSTRDOS1", + "BRAM_IMUX12_3", + "BRAM_BYP4_2", + "BRAM_IMUX8_UTURN_3", + "BRAM_LOGIC_OUTS_B9_4", + "BRAM_FIFO36_ECCPARITY0", + "BRAM_RAMB18_DOBDO11", + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRAM_EE4C2_1", + "BRAM_WW4END2_1", + "BRAM_IMUX33_2", + "BRAM_RAMB18_ADDRARDADDR11", + "BRAM_EL1BEG0_3", + "BRAM_LOGIC_OUTS_B22_0", + "BRAM_IMUX_ADDRBWRADDRU8", + "BRAM_IMUX18_3", + "BRAM_LOGIC_OUTS_B16_3", + "BRAM_ADDRARDADDRU7", + "BRAM_LOGIC_OUTS_B11_1", + "BRAM_NW2A2_2", + "BRAM_SW2A0_2", + "BRAM_LOGIC_OUTS_B21_2", + "BRAM_LH12_4", + "BRAM_LH3_4", + "BRAM_ADDRBWRADDRL14", + "BRAM_FIFO36_ECCPARITY1", + "BRAM_FIFO36_CASCADEOUTA", + "BRAM_FIFO18_ADDRARDADDR7", + "BRAM_IMUX15_4", + "BRAM_IMUX46_UTURN_2", + "BRAM_FIFO18_DIBDI8", + "BRAM_RAMB18_DOBDO2", + "BRAM_IMUX34_UTURN_0", + "BRAM_RAMB18_ADDRARDADDR7", + "BRAM_LOGIC_OUTS_B3_2", + "BRAM_MONITOR_N_0", + "BRAM_LOGIC_OUTS_B19_0", + "BRAM_IMUX5_UTURN_4", + "BRAM_EE2BEG1_2", + "BRAM_EE4C2_4", + "BRAM_SE4BEG1_0", + "BRAM_IMUX13_2", + "BRAM_BLOCK_OUTS_L_B2_4", + "BRAM_MONITOR_P_2", + "BRAM_RAMB18_RDCOUNT6", + "BRAM_EE4A0_0", + "BRAM_SE4BEG2_3", + "BRAM_WL1END2_1", + "BRAM_FIFO18_FULL", + "BRAM_UTURN_ADDRARDADDRU8", + "BRAM_IMUX4_1", + "BRAM_IMUX_ADDRARDADDRU7", + "BRAM_IMUX2_UTURN_3", + "BRAM_EE4BEG1_0", + "BRAM_LH11_3", + "BRAM_WW4C2_2", + "BRAM_WW4C1_1", + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRAM_WW4B3_3", + "BRAM_IMUX1_UTURN_0", + "BRAM_FAN5_2", + "BRAM_FIFO18_DOADO7", + "BRAM_FIFO36_ADDRARDADDRU10", + "BRAM_IMUX14_3", + "BRAM_UTURN_ADDRARDADDRU12", + "BRAM_FIFO18_ADDRARDADDR8", + "BRAM_FIFO36_ECCPARITY7", + "BRAM_EE4C0_2", + "BRAM_IMUX30_0", + "BRAM_FIFO36_WEAU0", + "BRAM_FIFO18_ADDRBWRADDR13", + "BRAM_FIFO36_DIBDIL11", + "BRAM_IMUX_ADDRBWRADDRL0", + "BRAM_RAMB18_ADDRBWRADDR13", + "BRAM_FIFO36_TSTCNT4", + "BRAM_IMUX16_UTURN_0", + "BRAM_FIFO36_TSTRDOS11", + "BRAM_EL1BEG3_2", + "BRAM_LH6_4", + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRAM_FIFO36_DOBDOU3", + "BRAM_RAMB18_DOBDO0", + "BRAM_FIFO36_TSTCNT11", + "BRAM_RAMB18_WRCOUNT9", + "BRAM_IMUX36_4", + "BRAM_PMVBRAM_ODIV2", + "BRAM_MONITOR_P_3", + "BRAM_FIFO18_REGCLKB", + "BRAM_SE4BEG0_2", + "BRAM_FIFO36_TSTRDOS7", + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRAM_NE4BEG1_4", + "BRAM_FIFO36_RDCOUNT9", + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRAM_WW4B0_2", + "BRAM_LH10_3", + "BRAM_IMUX13_4", + "BRAM_UTURN_ADDRARDADDRL1", + "BRAM_RAMB18_DOADO1", + "BRAM_RAMB18_DOADO14", + "BRAM_FIFO18_ENARDEN", + "BRAM_NW4END2_4", + "BRAM_FIFO36_ADDRBWRADDRL14", + "BRAM_IMUX12_2", + "BRAM_IMUX12_UTURN_4", + "BRAM_ER1BEG2_3", + "BRAM_EE4BEG1_1", + "BRAM_EE4A3_3", + "BRAM_WW2END3_4", + "BRAM_LOGIC_OUTS_B8_0", + "BRAM_UTURN_ADDRARDADDRU7", + "BRAM_SE4C1_2", + "BRAM_WW4END2_3", + "BRAM_IMUX15_1", + "BRAM_LH5_1", + "BRAM_IMUX30_UTURN_1", + "BRAM_IMUX17_2", + "BRAM_ADDRBWRADDRU9", + "BRAM_EE4C2_0", + "BRAM_IMUX_ADDRBWRADDRU6", + "BRAM_FIFO18_DOBDO10", + "BRAM_IMUX36_UTURN_0", + "BRAM_LOGIC_OUTS_B18_4", + "BRAM_IMUX39_4", + "BRAM_LOGIC_OUTS_B5_4", + "BRAM_WR1END2_1", + "BRAM_FIFO36_ADDRARDADDRL0", + "BRAM_LH7_3", + "BRAM_NE4BEG0_0", + "BRAM_IMUX35_UTURN_3", + "BRAM_WL1END1_2", + "BRAM_SE2A1_0", + "BRAM_IMUX7_UTURN_2", + "BRAM_NE4BEG3_3", + "BRAM_LOGIC_OUTS_B7_3", + "BRAM_IMUX40_3", + "BRAM_LOGIC_OUTS_B19_3", + "BRAM_RAMB18_DOADO13", + "BRAM_FIFO18_DIBDI14", + "BRAM_EE4BEG0_3", + "BRAM_UTURN_ADDRARDADDRL7", + "BRAM_FIFO36_WEAL0", + "BRAM_IMUX2_3", + "BRAM_IMUX7_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU1", + "BRAM_RAMB18_RDCOUNT7", + "BRAM_EE2BEG2_1", + "BRAM_IMUX41_UTURN_4", + "BRAM_IMUX19_UTURN_4", + "BRAM_BYP3_2", + "BRAM_LOGIC_OUTS_B4_0", + "BRAM_IMUX44_UTURN_0", + "BRAM_IMUX43_UTURN_3", + "BRAM_NW4END3_3", + "BRAM_ADDRARDADDRU3", + "BRAM_IMUX22_3", + "BRAM_RAMB18_DOBDO5", + "BRAM_IMUX45_0", + "BRAM_WW4B1_3", + "BRAM_SW2A2_4", + "BRAM_FIFO36_WRCOUNT0", + "BRAM_IMUX7_UTURN_4", + "BRAM_IMUX_ADDRBWRADDRL6", + "BRAM_CTRL1_4", + "BRAM_WW4C0_0", + "BRAM_EE4A3_2", + "BRAM_IMUX31_UTURN_4", + "BRAM_ADDRARDADDRU5", + "BRAM_SE4BEG3_1", + "BRAM_FIFO36_RSTREGARSTREGL", + "BRAM_NE4C2_4", + "BRAM_LH3_3", + "BRAM_SE4BEG1_4", + "BRAM_IMUX24_0", + "BRAM_NW4END1_2", + "BRAM_IMUX26_2", + "BRAM_EE2A3_1", + "BRAM_LOGIC_OUTS_B22_4", + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRAM_EE4A3_1", + "BRAM_ADDRARDADDRL8", + "BRAM_FIFO36_DOBDOL1", + "BRAM_FIFO36_ADDRARDADDRU1", + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRAM_NW2A1_2", + "BRAM_IMUX43_UTURN_2", + "BRAM_MONITOR_N_1", + "BRAM_FAN3_1", + "BRAM_WW4C1_2", + "BRAM_NE2A1_4", + "BRAM_FIFO18_RDCOUNT0", + "BRAM_WL1END2_0", + "BRAM_IMUX38_UTURN_0", + "BRAM_FIFO36_DIBDIU0", + "BRAM_FIFO36_WEBWEU6", + "BRAM_FIFO36_ADDRARDADDRL1", + "BRAM_NW4A1_3", + "BRAM_IMUX6_UTURN_2", + "BRAM_FIFO36_DOBDOU9", + "BRAM_FIFO36_DIADIL7", + "BRAM_NW4A2_3", + "BRAM_RAMB18_DIADI14", + "BRAM_EE4A3_0", + "BRAM_SE4BEG2_0", + "BRAM_IMUX11_UTURN_2", + "BRAM_NE4BEG3_1", + "BRAM_FIFO36_REGCEBL", + "BRAM_FIFO18_ALMOSTEMPTY", + "BRAM_IMUX_ADDRARDADDRL14", + "BRAM_FIFO18_ADDRARDADDR2", + "BRAM_IMUX1_UTURN_1", + "BRAM_EE4B2_4", + "BRAM_FIFO36_DIBDIU7", + "BRAM_SW2A1_0", + "BRAM_FIFO36_TSTRDOS10", + "BRAM_IMUX31_UTURN_1", + "BRAM_IMUX10_UTURN_2", + "BRAM_FIFO18_DIADI15", + "BRAM_FIFO36_RDCOUNT1", + "BRAM_IMUX_ADDRARDADDRL8", + "BRAM_SW4A2_2", + "BRAM_LH2_0", + "BRAM_IMUX20_UTURN_4", + "BRAM_IMUX24_3", + "BRAM_FIFO36_WEAL2", + "BRAM_UTURN_ADDRARDADDRL11", + "BRAM_RAMB18_DIBDI2", + "BRAM_EL1BEG1_3", + "BRAM_NW2A0_2", + "BRAM_FIFO18_WRCOUNT5", + "BRAM_EE4BEG2_2", + "BRAM_RAMB18_WEBWE7", + "BRAM_FIFO36_DOADOL14", + "BRAM_RAMB18_ADDRARDADDR9", + "BRAM_IMUX33_UTURN_2", + "BRAM_IMUX14_UTURN_2", + "BRAM_IMUX46_UTURN_0", + "BRAM_UTURN_ADDRBWRADDRL0", + "BRAM_FIFO18_DOPBDOP1", + "BRAM_FIFO36_DIADIU6", + "BRAM_FIFO18_DIBDI13", + "BRAM_LOGIC_OUTS_B13_4", + "BRAM_IMUX6_2", + "BRAM_FIFO18_RDCOUNT8", + "BRAM_RAMB18_ADDRBWRADDR3", + "BRAM_LOGIC_OUTS_B18_2", + "BRAM_SE4BEG0_3", + "BRAM_LH6_0", + "BRAM_WW4A3_2", + "BRAM_FIFO18_EMPTY", + "BRAM_FIFO18_ADDRATIEHIGH0", + "BRAM_EE4A0_4", + "BRAM_FIFO36_WEBWEU0", + "BRAM_EE2A3_0", + "BRAM_FIFO36_DIBDIL9", + "BRAM_SW4A2_3", + "BRAM_FIFO36_DIPBDIPL1", + "BRAM_FIFO18_DIADI5", + "BRAM_SW4END2_2", + "BRAM_IMUX17_0", + "BRAM_IMUX38_UTURN_1", + "BRAM_UTURN_ADDRARDADDRL6", + "BRAM_IMUX42_3", + "BRAM_FIFO36_DIADIL13", + "BRAM_IMUX_ADDRARDADDRL3", + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRAM_NE4BEG1_3", + "BRAM_EE4B3_0", + "BRAM_ADDRBWRADDRL1", + "BRAM_IMUX34_UTURN_3", + "BRAM_SW4A0_4", + "BRAM_PMVBRAM_O", + "BRAM_FIFO18_WRCOUNT2", + "BRAM_FIFO18_DOPBDOP0", + "BRAM_UTURN_ADDRBWRADDRU0", + "BRAM_UTURN_ADDRBWRADDRL3", + "BRAM_RAMB18_DIADI15", + "BRAM_SE4BEG0_1", + "BRAM_WW2END0_1", + "BRAM_ER1BEG0_2", + "BRAM_LOGIC_OUTS_B0_0", + "BRAM_FIFO36_DIADIU2", + "BRAM_WR1END3_4", + "BRAM_FIFO18_WRCOUNT1", + "BRAM_EL1BEG3_0", + "BRAM_FAN5_4", + "BRAM_FIFO36_WEBWEU3", + "BRAM_WW4A2_0", + "BRAM_FIFO36_DOADOL15", + "BRAM_IMUX30_UTURN_4", + "BRAM_IMUX_ADDRARDADDRL7", + "BRAM_UTURN_ADDRARDADDRL3", + "BRAM_WR1END3_3", + "BRAM_WL1END3_4", + "BRAM_NW4END3_1", + "BRAM_IMUX0_UTURN_1", + "BRAM_LOGIC_OUTS_B16_2", + "BRAM_LH9_4", + "BRAM_WW4B3_4", + "BRAM_FIFO36_ADDRARDADDRL13", + "BRAM_FIFO36_DIBDIU2", + "BRAM_IMUX24_2", + "BRAM_EL1BEG1_2", + "BRAM_IMUX_ADDRARDADDRL9", + "BRAM_FIFO36_TSTRDOS2", + "BRAM_WW4END3_1", + "BRAM_WR1END2_2", + "BRAM_NW4A3_2", + "BRAM_WW4B2_0", + "BRAM_BYP7_0", + "BRAM_IMUX11_UTURN_0", + "BRAM_FIFO36_DOADOU11", + "BRAM_IMUX27_UTURN_2", + "BRAM_RAMB18_WRCOUNT10", + "BRAM_RAMB18_DIADI9", + "BRAM_IMUX_ADDRARDADDRL5", + "BRAM_FIFO36_DIADIU15", + "BRAM_IMUX32_3", + "BRAM_NE4BEG0_1", + "BRAM_WW2A1_1", + "BRAM_EL1BEG3_4", + "BRAM_LOGIC_OUTS_B14_4", + "BRAM_IMUX30_4", + "BRAM_FIFO36_ADDRARDADDRL15", + "BRAM_LOGIC_OUTS_B4_2", + "BRAM_FIFO36_TSTIN3", + "BRAM_LOGIC_OUTS_B23_3", + "BRAM_FIFO36_DIBDIL2", + "BRAM_UTURN_ADDRBWRADDRL12", + "BRAM_RAMB18_DIPBDIP0", + "BRAM_IMUX30_3", + "BRAM_FIFO36_RDCOUNT2", + "BRAM_EE4C0_4", + "BRAM_FIFO18_DOPADOP0", + "BRAM_ADDRARDADDRU8", + "BRAM_FIFO36_DOBDOL6", + "BRAM_CLK0_0", + "BRAM_EL1BEG0_2", + "BRAM_WW4END2_0", + "BRAM_IMUX35_0", + "BRAM_BYP3_0", + "BRAM_UTURN_ADDRARDADDRU2", + "BRAM_FIFO36_TSTOUT4", + "BRAM_FIFO36_WEBWEU4", + "BRAM_IMUX41_UTURN_1", + "BRAM_FIFO36_ENBWRENL", + "BRAM_FIFO36_DIADIL15", + "BRAM_LOGIC_OUTS_B11_0", + "BRAM_ADDRARDADDRU10", + "BRAM_IMUX_ADDRARDADDRL4", + "BRAM_IMUX33_3", + "BRAM_LOGIC_OUTS_B23_4", + "BRAM_IMUX_ADDRARDADDRU13", + "BRAM_FIFO18_DOADO5", + "BRAM_IMUX26_0", + "BRAM_IMUX_ADDRARDADDRL0", + "BRAM_ADDRARDADDRU4", + "BRAM_IMUX4_UTURN_0", + "BRAM_SE2A1_2", + "BRAM_FIFO36_DOADOU15", + "BRAM_BYP6_4", + "BRAM_NE2A1_3", + "BRAM_FIFO36_DIBDIL7", + "BRAM_RAMB18_ADDRARDADDR12", + "BRAM_IMUX15_UTURN_2", + "BRAM_FIFO36_TSTIN2", + "BRAM_PMVBRAM_O_2", + "BRAM_LOGIC_OUTS_B8_3", + "BRAM_NW4END2_3", + "BRAM_IMUX23_3", + "BRAM_FIFO36_REGCLKBU", + "BRAM_FIFO36_ADDRBWRADDRU8", + "BRAM_IMUX12_UTURN_1", + "BRAM_FIFO36_TSTWROS6", + "BRAM_FIFO36_DIBDIU15", + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRAM_FIFO36_TSTWROS5", + "BRAM_RAMB18_ADDRARDADDR8", + "BRAM_SE2A2_4", + "BRAM_LH3_0", + "BRAM_ADDRARDADDRL5", + "BRAM_FIFO36_ADDRBWRADDRU14", + "BRAM_IMUX20_1", + "BRAM_SW4A2_1", + "BRAM_EE2A2_2", + "BRAM_IMUX45_UTURN_4", + "BRAM_FIFO36_DOADOU8", + "BRAM_RAMB18_ADDRBWRADDR8", + "BRAM_IMUX9_UTURN_2", + "BRAM_EE4B2_3", + "BRAM_IMUX19_1", + "BRAM_FIFO36_TSTOUT2", + "BRAM_SE4C0_3", + "BRAM_ADDRARDADDRU6", + "BRAM_NW4A1_2", + "BRAM_ADDRBWRADDRL8", + "BRAM_FIFO36_RDCOUNT5", + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRAM_WW2A1_2", + "BRAM_FAN2_2", + "BRAM_IMUX27_4", + "BRAM_EE4BEG2_1", + "BRAM_LOGIC_OUTS_B12_3", + "BRAM_RAMB18_WRCOUNT1", + "BRAM_FIFO18_CLKBWRCLK", + "BRAM_NW4A2_4", + "BRAM_SW4END1_4", + "BRAM_IMUX12_4", + "BRAM_SE2A3_3", + "BRAM_BYP4_3", + "BRAM_WW4C3_3", + "BRAM_IMUX20_UTURN_3", + "BRAM_IMUX30_UTURN_3", + "BRAM_EE4C3_4", + "BRAM_WW2A2_0", + "BRAM_BYP7_1", + "BRAM_ADDRARDADDRL3", + "BRAM_SE2A3_0", + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRAM_FIFO36_TSTWROS12", + "BRAM_SW4END3_4", + "BRAM_IMUX8_UTURN_1", + "BRAM_FIFO18_DOBDO0", + "BRAM_MONITOR_P_1", + "BRAM_IMUX36_UTURN_4", + "BRAM_IMUX14_UTURN_0", + "BRAM_FIFO36_ADDRARDADDRU11", + "BRAM_FIFO36_DOADOL5", + "BRAM_FIFO36_ADDRBWRADDRU4", + "BRAM_LOGIC_OUTS_B8_4", + "BRAM_UTURN_ADDRARDADDRL8", + "BRAM_ADDRARDADDRL1", + "BRAM_WL1END1_3", + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRAM_IMUX33_4", + "BRAM_SW2A2_0", + "BRAM_SW4END3_3", + "BRAM_IMUX13_UTURN_1", + "BRAM_LH1_0", + "BRAM_LOGIC_OUTS_B3_3", + "BRAM_FIFO36_DIADIL8", + "BRAM_IMUX28_2", + "BRAM_FIFO36_DOBDOL13", + "BRAM_IMUX21_UTURN_3", + "BRAM_FIFO36_DIBDIU4", + "BRAM_LOGIC_OUTS_B20_2", + "BRAM_IMUX40_0", + "BRAM_IMUX31_UTURN_0", + "BRAM_IMUX27_1", + "BRAM_FIFO36_ADDRARDADDRU14", + "BRAM_SW2A1_4", + "BRAM_WR1END1_1", + "BRAM_IMUX37_2", + "BRAM_IMUX37_4", + "BRAM_WW4B1_0", + "BRAM_UTURN_ADDRBWRADDRL7", + "BRAM_RAMB18_DIADI2", + "BRAM_MONITOR_P_0", + "BRAM_IMUX46_UTURN_1", + "BRAM_FIFO36_RDCOUNT0", + "BRAM_IMUX26_UTURN_4", + "BRAM_IMUX3_0", + "BRAM_WR1END1_3", + "BRAM_RAMB18_DOADO9", + "BRAM_IMUX43_0", + "BRAM_LOGIC_OUTS_B19_2", + "BRAM_RAMB18_DIADI8", + "BRAM_FIFO18_RSTRAMB", + "BRAM_BLOCK_OUTS_L_B2_0", + "BRAM_RAMB18_DOBDO12", + "BRAM_EE4A2_0", + "BRAM_EE4BEG0_0", + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRAM_FIFO18_WRCOUNT6", + "BRAM_FIFO18_WEBWE3", + "BRAM_WW2END1_1", + "BRAM_SE4C3_0", + "BRAM_IMUX0_0", + "BRAM_IMUX27_UTURN_1", + "BRAM_IMUX15_0", + "BRAM_SE2A0_2", + "BRAM_UTURN_ADDRBWRADDRU6", + "BRAM_FIFO18_ADDRBTIEHIGH1", + "BRAM_IMUX25_UTURN_2", + "BRAM_IMUX45_2", + "BRAM_RAMB18_ADDRARDADDR0", + "BRAM_IMUX4_2", + "BRAM_WW2END0_3", + "BRAM_IMUX_ADDRBWRADDRU5", + "BRAM_NE4BEG2_3", + "BRAM_LH5_3", + "BRAM_RAMB18_REGCEAREGCE", + "BRAM_IMUX17_4", + "BRAM_WW4A0_0", + "BRAM_NE2A0_3", + "BRAM_WL1END3_3", + "BRAM_RAMB18_DIADI13", + "BRAM_RAMB18_ADDRATIEHIGH0", + "BRAM_LOGIC_OUTS_B4_4", + "BRAM_SW4END3_0", + "BRAM_IMUX18_UTURN_1", + "BRAM_CLK1_0", + "BRAM_WW4C2_0", + "BRAM_IMUX19_2", + "BRAM_ADDRARDADDRL2", + "BRAM_FIFO18_WRCOUNT7", + "BRAM_WR1END3_2", + "BRAM_FAN5_0", + "BRAM_LOGIC_OUTS_B13_0", + "BRAM_FIFO36_WEBWEL3", + "BRAM_NE4C0_4", + "BRAM_LOGIC_OUTS_B9_2", + "BRAM_FIFO36_ADDRBWRADDRU11", + "BRAM_IMUX41_0", + "BRAM_IMUX9_3", + "BRAM_NW4A1_4", + "BRAM_IMUX19_UTURN_1", + "BRAM_LH6_1", + "BRAM_NE4BEG2_2", + "BRAM_FIFO36_WEBWEU1", + "BRAM_FIFO36_WRCOUNT4", + "BRAM_NW4END0_0", + "BRAM_LOGIC_OUTS_B13_3", + "BRAM_IMUX4_0", + "BRAM_IMUX6_UTURN_4", + "BRAM_LH11_1", + "BRAM_CLK0_2", + "BRAM_PMVBRAM_ODIV2_1", + "BRAM_IMUX2_UTURN_2", + "BRAM_NW4A2_1", + "BRAM_LH5_4", + "BRAM_IMUX23_UTURN_4", + "BRAM_EE4B0_2", + "BRAM_RAMB18_DIADI12", + "BRAM_RAMB18_ALMOSTEMPTY", + "BRAM_IMUX28_0", + "BRAM_IMUX21_4", + "BRAM_WW2A0_3", + "BRAM_IMUX7_UTURN_1", + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRAM_WW4C1_3", + "BRAM_WW4END0_1", + "BRAM_IMUX40_4", + "BRAM_IMUX20_0", + "BRAM_EE4B3_1", + "BRAM_PMVBRAM_SELECT3", + "BRAM_LOGIC_OUTS_B23_1", + "BRAM_IMUX22_UTURN_2", + "BRAM_IMUX_ADDRBWRADDRL8", + "BRAM_IMUX36_1", + "BRAM_BYP5_0", + "BRAM_FIFO18_DIBDI11", + "BRAM_FIFO18_WEBWE1", + "BRAM_UTURN_ADDRBWRADDRL13", + "BRAM_WW4END2_4", + "BRAM_WW4C3_2", + "BRAM_WW2A3_0", + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRAM_IMUX28_UTURN_2", + "BRAM_EE2A0_1", + "BRAM_FIFO18_DOADO10", + "BRAM_FIFO36_DIBDIU9", + "BRAM_LOGIC_OUTS_B20_0", + "BRAM_IMUX44_0", + "BRAM_FIFO18_WRCOUNT11", + "BRAM_FIFO36_DOADOL4", + "BRAM_IMUX27_3", + "BRAM_RAMB18_RDCOUNT5", + "BRAM_ER1BEG2_1", + "BRAM_LOGIC_OUTS_B6_3", + "BRAM_BLOCK_OUTS_L_B0_2", + "BRAM_FIFO36_TSTWRCNTOFF", + "BRAM_FIFO36_CLKARDCLKL", + "BRAM_MONITOR_N_4", + "BRAM_IMUX8_0", + "BRAM_CTRL0_3", + "BRAM_LOGIC_OUTS_B12_2", + "BRAM_IMUX47_UTURN_2", + "BRAM_WW2A2_1", + "BRAM_FAN1_4", + "BRAM_BLOCK_OUTS_L_B3_1" + ], + "tile_type": "BRAM_L", + "sites": [ + { + "site_pins": { + "WEBWEL6": "BRAM_FIFO36_WEBWEL6", + "DOBDO3": "BRAM_FIFO36_DOBDOU1", + "DOADO7": "BRAM_FIFO36_DOADOU3", + "DIADI2": "BRAM_FIFO36_DIADIL1", + "TSTWROS11": "BRAM_FIFO36_TSTWROS11", + "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", + "DIADI25": "BRAM_FIFO36_DIADIU12", + "DOADO18": "BRAM_FIFO36_DOADOL9", + "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", + "DOBDO17": "BRAM_FIFO36_DOBDOU8", + "WEBWEU5": "BRAM_FIFO36_WEBWEU5", + "WRCOUNT9": "BRAM_FIFO36_WRCOUNT9", + "WEAU2": "BRAM_FIFO36_WEAU2", + "DIBDI28": "BRAM_FIFO36_DIBDIL14", + "DIBDI6": "BRAM_FIFO36_DIBDIL3", + "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", + "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", + "TSTCNT8": "BRAM_FIFO36_TSTCNT8", + "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", + "EMPTY": "BRAM_FIFO36_EMPTY", + "DIADI5": "BRAM_FIFO36_DIADIU2", + "DOADO21": "BRAM_FIFO36_DOADOU10", + "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", + "DOADO6": "BRAM_FIFO36_DOADOL3", + "REGCLKBU": "BRAM_FIFO36_REGCLKBU", + "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", + "DOADO5": "BRAM_FIFO36_DOADOU2", + "SBITERR": "BRAM_FIFO36_SBITERR", + "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", + "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", + "DOADO1": "BRAM_FIFO36_DOADOU0", + "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", + "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", + "TSTWROS10": "BRAM_FIFO36_TSTWROS10", + "TSTWROS12": "BRAM_FIFO36_TSTWROS12", + "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", + "DIADI20": "BRAM_FIFO36_DIADIL10", + "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", + "TSTCNT11": "BRAM_FIFO36_TSTCNT11", + "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", + "DOBDO22": "BRAM_FIFO36_DOBDOL11", + "WEBWEL4": "BRAM_FIFO36_WEBWEL4", + "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", + "TSTOUT2": "BRAM_FIFO36_TSTOUT2", + "DIADI6": "BRAM_FIFO36_DIADIL3", + "TSTCNT2": "BRAM_FIFO36_TSTCNT2", + "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", + "TSTWROS3": "BRAM_FIFO36_TSTWROS3", + "FULL": "BRAM_FIFO36_FULL", + "ENARDENL": "BRAM_FIFO36_ENARDENL", + "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", + "DIADI10": "BRAM_FIFO36_DIADIL5", + "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", + "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", + "TSTIN4": "BRAM_FIFO36_TSTIN4", + "DIBDI31": "BRAM_FIFO36_DIBDIU15", + "DOBDO18": "BRAM_FIFO36_DOBDOL9", + "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", + "WEBWEU6": "BRAM_FIFO36_WEBWEU6", + "DOADO26": "BRAM_FIFO36_DOADOL13", + "TSTCNT12": "BRAM_FIFO36_TSTCNT12", + "DOADO30": "BRAM_FIFO36_DOADOL15", + "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", + "DOADO31": "BRAM_FIFO36_DOADOU15", + "DIBDI14": "BRAM_FIFO36_DIBDIL7", + "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", + "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", + "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", + "TSTWROS6": "BRAM_FIFO36_TSTWROS6", + "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", + "DIADI7": "BRAM_FIFO36_DIADIU3", + "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", + "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", + "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", + "DOBDO10": "BRAM_FIFO36_DOBDOL5", + "WEBWEL5": "BRAM_FIFO36_WEBWEL5", + "WEBWEU0": "BRAM_FIFO36_WEBWEU0", + "TSTWROS2": "BRAM_FIFO36_TSTWROS2", + "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", + "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", + "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", + "DOBDO21": "BRAM_FIFO36_DOBDOU10", + "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", + "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", + "TSTWROS9": "BRAM_FIFO36_TSTWROS9", + "DOBDO11": "BRAM_FIFO36_DOBDOU5", + "WEBWEU1": "BRAM_FIFO36_WEBWEU1", + "DOADO19": "BRAM_FIFO36_DOADOU9", + "WRCOUNT7": "BRAM_FIFO36_WRCOUNT7", + "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", + "TSTIN2": "BRAM_FIFO36_TSTIN2", + "DOBDO1": "BRAM_FIFO36_DOBDOU0", + "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", + "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", + "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", + "DIBDI9": "BRAM_FIFO36_DIBDIU4", + "DOBDO20": "BRAM_FIFO36_DOBDOL10", + "TSTOUT3": "BRAM_FIFO36_TSTOUT3", + "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", + "DIADI22": "BRAM_FIFO36_DIADIL11", + "DOADO15": "BRAM_FIFO36_DOADOU7", + "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", + "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", + "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", + "DIADI28": "BRAM_FIFO36_DIADIL14", + "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", + "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", + "DIBDI25": "BRAM_FIFO36_DIBDIU12", + "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", + "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", + "DOBDO30": "BRAM_FIFO36_DOBDOL15", + "DOADO2": "BRAM_FIFO36_DOADOL1", + "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", + "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", + "DOBDO23": "BRAM_FIFO36_DOBDOU11", + "TSTCNT10": "BRAM_FIFO36_TSTCNT10", + "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", + "DIBDI7": "BRAM_FIFO36_DIBDIU3", + "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", + "DIADI4": "BRAM_FIFO36_DIADIL2", + "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", + "WEBWEU3": "BRAM_FIFO36_WEBWEU3", + "DIBDI26": "BRAM_FIFO36_DIBDIL13", + "DOADO25": "BRAM_FIFO36_DOADOU12", + "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", + "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", + "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", + "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTA", + "CASCADEINB": "BRAM_FIFO36_CASCADEINB", + "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", + "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", + "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", + "DIADI21": "BRAM_FIFO36_DIADIU10", + "RDERR": "BRAM_FIFO36_RDERR", + "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", + "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", + "DIBDI20": "BRAM_FIFO36_DIBDIL10", + "WEBWEL1": "BRAM_FIFO36_WEBWEL1", + "TSTOFF": "BRAM_FIFO36_TSTOFF", + "DOBDO15": "BRAM_FIFO36_DOBDOU7", + "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", + "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", + "DIBDI30": "BRAM_FIFO36_DIBDIL15", + "DOADO16": "BRAM_FIFO36_DOADOL8", + "DOBDO16": "BRAM_FIFO36_DOBDOL8", + "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", + "RSTREGBU": "BRAM_FIFO36_RSTREGBU", + "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", + "DOADO0": "BRAM_FIFO36_DOADOL0", + "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", + "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", + "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", + "WEBWEU7": "BRAM_FIFO36_WEBWEU7", + "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", + "TSTCNT0": "BRAM_FIFO36_TSTCNT0", + "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", + "TSTWROS0": "BRAM_FIFO36_TSTWROS0", + "ENBWRENU": "BRAM_FIFO36_ENBWRENU", + "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", + "TSTOUT0": "BRAM_FIFO36_TSTOUT0", + "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", + "TSTOUT4": "BRAM_FIFO36_TSTOUT4", + "DIBDI8": "BRAM_FIFO36_DIBDIL4", + "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", + "DOBDO8": "BRAM_FIFO36_DOBDOL4", + "REGCEBU": "BRAM_FIFO36_REGCEBU", + "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", + "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", + "DOBDO0": "BRAM_FIFO36_DOBDOL0", + "DOBDO2": "BRAM_FIFO36_DOBDOL1", + "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", + "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", + "DIADI18": "BRAM_FIFO36_DIADIL9", + "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", + "DOBDO25": "BRAM_FIFO36_DOBDOU12", + "WEBWEL2": "BRAM_FIFO36_WEBWEL2", + "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", + "DOBDO12": "BRAM_FIFO36_DOBDOL6", + "WEAL1": "BRAM_FIFO36_WEAL1", + "TSTCNT6": "BRAM_FIFO36_TSTCNT6", + "DOBDO29": "BRAM_FIFO36_DOBDOU14", + "DOBDO14": "BRAM_FIFO36_DOBDOL7", + "DIADI13": "BRAM_FIFO36_DIADIU6", + "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", + "WEBWEL7": "BRAM_FIFO36_WEBWEL7", + "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", + "DIBDI18": "BRAM_FIFO36_DIBDIL9", + "DIADI30": "BRAM_FIFO36_DIADIL15", + "DIADI3": "BRAM_FIFO36_DIADIU1", + "REGCEBL": "BRAM_FIFO36_REGCEBL", + "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", + "DIADI27": "BRAM_FIFO36_DIADIU13", + "DOADO23": "BRAM_FIFO36_DOADOU11", + "REGCLKBL": "BRAM_FIFO36_REGCLKBL", + "DIBDI17": "BRAM_FIFO36_DIBDIU8", + "TSTIN0": "BRAM_FIFO36_TSTIN0", + "DOADO29": "BRAM_FIFO36_DOADOU14", + "DIADI1": "BRAM_FIFO36_DIADIU0", + "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", + "DIBDI4": "BRAM_FIFO36_DIBDIL2", + "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", + "DOADO28": "BRAM_FIFO36_DOADOL14", + "WEBWEL3": "BRAM_FIFO36_WEBWEL3", + "WEAU3": "BRAM_FIFO36_WEAU3", + "DIBDI12": "BRAM_FIFO36_DIBDIL6", + "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", + "DIADI19": "BRAM_FIFO36_DIADIU9", + "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", + "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", + "TSTCNT7": "BRAM_FIFO36_TSTCNT7", + "DOBDO28": "BRAM_FIFO36_DOBDOL14", + "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", + "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", + "DIADI26": "BRAM_FIFO36_DIADIL13", + "DOADO22": "BRAM_FIFO36_DOADOL11", + "DOADO4": "BRAM_FIFO36_DOADOL2", + "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", + "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", + "WRCOUNT8": "BRAM_FIFO36_WRCOUNT8", + "TSTCNT1": "BRAM_FIFO36_TSTCNT1", + "DIBDI11": "BRAM_FIFO36_DIBDIU5", + "TSTIN3": "BRAM_FIFO36_TSTIN3", + "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", + "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", + "TSTCNT4": "BRAM_FIFO36_TSTCNT4", + "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", + "TSTWROS8": "BRAM_FIFO36_TSTWROS8", + "WEAL3": "BRAM_FIFO36_WEAL3", + "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", + "DOBDO9": "BRAM_FIFO36_DOBDOU4", + "WEBWEU2": "BRAM_FIFO36_WEBWEU2", + "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", + "TSTWROS4": "BRAM_FIFO36_TSTWROS4", + "DOBDO24": "BRAM_FIFO36_DOBDOL12", + "DOADO9": "BRAM_FIFO36_DOADOU4", + "DIBDI3": "BRAM_FIFO36_DIBDIU1", + "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", + "TSTCNT5": "BRAM_FIFO36_TSTCNT5", + "ENBWRENL": "BRAM_FIFO36_ENBWRENL", + "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", + "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", + "ENARDENU": "BRAM_FIFO36_ENARDENU", + "DIBDI2": "BRAM_FIFO36_DIBDIL1", + "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", + "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", + "WEAL0": "BRAM_FIFO36_WEAL0", + "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", + "DIADI16": "BRAM_FIFO36_DIADIL8", + "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", + "DIADI8": "BRAM_FIFO36_DIADIL4", + "TSTOUT1": "BRAM_FIFO36_TSTOUT1", + "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", + "TSTIN1": "BRAM_FIFO36_TSTIN1", + "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", + "WEBWEL0": "BRAM_FIFO36_WEBWEL0", + "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", + "DOADO17": "BRAM_FIFO36_DOADOU8", + "DOADO14": "BRAM_FIFO36_DOADOL7", + "DIADI11": "BRAM_FIFO36_DIADIU5", + "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", + "DIADI9": "BRAM_FIFO36_DIADIU4", + "DIBDI15": "BRAM_FIFO36_DIBDIU7", + "DOBDO26": "BRAM_FIFO36_DOBDOL13", + "WEBWEU4": "BRAM_FIFO36_WEBWEU4", + "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", + "DOBDO13": "BRAM_FIFO36_DOBDOU6", + "DIBDI22": "BRAM_FIFO36_DIBDIL11", + "DOADO11": "BRAM_FIFO36_DOADOU5", + "DIBDI27": "BRAM_FIFO36_DIBDIU13", + "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", + "WEAL2": "BRAM_FIFO36_WEAL2", + "TSTWROS5": "BRAM_FIFO36_TSTWROS5", + "DIADI23": "BRAM_FIFO36_DIADIU11", + "DIBDI29": "BRAM_FIFO36_DIBDIU14", + "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", + "DOBDO19": "BRAM_FIFO36_DOBDOU9", + "DIADI0": "BRAM_FIFO36_DIADIL0", + "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", + "DIADI12": "BRAM_FIFO36_DIADIL6", + "ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", + "WEAU0": "BRAM_FIFO36_WEAU0", + "DIADI31": "BRAM_FIFO36_DIADIU15", + "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", + "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", + "DIBDI13": "BRAM_FIFO36_DIBDIU6", + "TSTCNT3": "BRAM_FIFO36_TSTCNT3", + "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTB", + "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", + "DIBDI1": "BRAM_FIFO36_DIBDIU0", + "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", + "DOBDO5": "BRAM_FIFO36_DOBDOU2", + "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", + "DOADO20": "BRAM_FIFO36_DOADOL10", + "DIBDI5": "BRAM_FIFO36_DIBDIU2", + "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", + "DIBDI0": "BRAM_FIFO36_DIBDIL0", + "DIBDI24": "BRAM_FIFO36_DIBDIL12", + "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", + "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", + "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", + "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", + "DOBDO4": "BRAM_FIFO36_DOBDOL2", + "TSTWROS7": "BRAM_FIFO36_TSTWROS7", + "TSTWROS1": "BRAM_FIFO36_TSTWROS1", + "WRERR": "BRAM_FIFO36_WRERR", + "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", + "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", + "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", + "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", + "DOADO13": "BRAM_FIFO36_DOADOU6", + "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", + "DIADI29": "BRAM_FIFO36_DIADIU14", + "DIADI15": "BRAM_FIFO36_DIADIU7", + "DOBDO7": "BRAM_FIFO36_DOBDOU3", + "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", + "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", + "DOADO12": "BRAM_FIFO36_DOADOL6", + "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", + "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", + "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", + "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", + "DIADI14": "BRAM_FIFO36_DIADIL7", + "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", + "DIBDI10": "BRAM_FIFO36_DIBDIL5", + "RSTREGBL": "BRAM_FIFO36_RSTREGBL", + "DOADO24": "BRAM_FIFO36_DOADOL12", + "DOADO27": "BRAM_FIFO36_DOADOU13", + "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", + "DIADI24": "BRAM_FIFO36_DIADIL12", + "DIBDI23": "BRAM_FIFO36_DIBDIU11", + "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", + "DOBDO31": "BRAM_FIFO36_DOBDOU15", + "DOADO3": "BRAM_FIFO36_DOADOU1", + "DBITERR": "BRAM_FIFO36_DBITERR", + "DOADO8": "BRAM_FIFO36_DOADOL4", + "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", + "DIBDI21": "BRAM_FIFO36_DIBDIU10", + "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", + "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", + "CASCADEINA": "BRAM_FIFO36_CASCADEINA", + "DOADO10": "BRAM_FIFO36_DOADOL5", + "DOBDO6": "BRAM_FIFO36_DOBDOL3", + "DIBDI16": "BRAM_FIFO36_DIBDIL8", + "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", + "DIBDI19": "BRAM_FIFO36_DIBDIU9", + "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", + "TSTCNT9": "BRAM_FIFO36_TSTCNT9", + "DOBDO27": "BRAM_FIFO36_DOBDOU13", + "WEAU1": "BRAM_FIFO36_WEAU1", + "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", + "DIADI17": "BRAM_FIFO36_DIADIU8", + "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", + "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", + "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", + "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU" + }, + "type": "RAMBFIFO36E1", + "prefix": "RAMB36", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", + "DIBDI15": "BRAM_FIFO18_DIBDI15", + "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", + "DIADI13": "BRAM_FIFO18_DIADI13", + "DO21": "BRAM_FIFO18_DOBDO5", + "DIADI4": "BRAM_FIFO18_DIADI4", + "DO4": "BRAM_FIFO18_DOADO4", + "WRCOUNT2": "BRAM_FIFO18_WRCOUNT2", + "RDEN": "BRAM_FIFO18_ENARDEN", + "WRCOUNT10": "BRAM_FIFO18_WRCOUNT10", + "DOP1": "BRAM_FIFO18_DOPADOP1", + "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", + "RSTRAMB": "BRAM_FIFO18_RSTRAMB", + "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", + "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", + "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", + "WEBWE1": "BRAM_FIFO18_WEBWE1", + "FULL": "BRAM_FIFO18_FULL", + "WRCLK": "BRAM_FIFO18_CLKBWRCLK", + "DIBDI2": "BRAM_FIFO18_DIBDI2", + "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", + "DO8": "BRAM_FIFO18_DOADO8", + "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", + "DIADI0": "BRAM_FIFO18_DIADI0", + "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", + "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", + "DO12": "BRAM_FIFO18_DOADO12", + "DIADI12": "BRAM_FIFO18_DIADI12", + "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", + "DIADI1": "BRAM_FIFO18_DIADI1", + "DO17": "BRAM_FIFO18_DOBDO1", + "DO10": "BRAM_FIFO18_DOADO10", + "DIBDI4": "BRAM_FIFO18_DIBDI4", + "EMPTY": "BRAM_FIFO18_EMPTY", + "DIADI5": "BRAM_FIFO18_DIADI5", + "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", + "RDERR": "BRAM_FIFO18_RDERR", + "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", + "WEA0": "BRAM_FIFO18_WEA0", + "WEBWE0": "BRAM_FIFO18_WEBWE0", + "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", + "DO24": "BRAM_FIFO18_DOBDO8", + "DO18": "BRAM_FIFO18_DOBDO2", + "DIBDI13": "BRAM_FIFO18_DIBDI13", + "DIADI14": "BRAM_FIFO18_DIADI14", + "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", + "DOP2": "BRAM_FIFO18_DOPBDOP0", + "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", + "DIADI7": "BRAM_FIFO18_DIADI7", + "DIBDI1": "BRAM_FIFO18_DIBDI1", + "WRCOUNT3": "BRAM_FIFO18_WRCOUNT3", + "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", + "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", + "DO30": "BRAM_FIFO18_DOBDO14", + "DIBDI8": "BRAM_FIFO18_DIBDI8", + "DO15": "BRAM_FIFO18_DOADO15", + "ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0", + "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", + "DIBDI10": "BRAM_FIFO18_DIBDI10", + "DIADI10": "BRAM_FIFO18_DIADI10", + "DO16": "BRAM_FIFO18_DOBDO0", + "WRERR": "BRAM_FIFO18_WRERR", + "DOP0": "BRAM_FIFO18_DOPADOP0", + "RSTREGB": "BRAM_FIFO18_RSTREGB", + "DO0": "BRAM_FIFO18_DOADO0", + "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", + "DO20": "BRAM_FIFO18_DOBDO4", + "DO3": "BRAM_FIFO18_DOADO3", + "WRCOUNT4": "BRAM_FIFO18_WRCOUNT4", + "REGCE": "BRAM_FIFO18_REGCEAREGCE", + "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", + "WRCOUNT11": "BRAM_FIFO18_WRCOUNT11", + "DOP3": "BRAM_FIFO18_DOPBDOP1", + "DIBDI7": "BRAM_FIFO18_DIBDI7", + "DO13": "BRAM_FIFO18_DOADO13", + "DO29": "BRAM_FIFO18_DOBDO13", + "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", + "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", + "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", + "WEBWE2": "BRAM_FIFO18_WEBWE2", + "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", + "DIBDI11": "BRAM_FIFO18_DIBDI11", + "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", + "DO14": "BRAM_FIFO18_DOADO14", + "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", + "DIADI6": "BRAM_FIFO18_DIADI6", + "WEBWE6": "BRAM_FIFO18_WEBWE6", + "DIBDI5": "BRAM_FIFO18_DIBDI5", + "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", + "DO2": "BRAM_FIFO18_DOADO2", + "DIADI15": "BRAM_FIFO18_DIADI15", + "DO1": "BRAM_FIFO18_DOADO1", + "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", + "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", + "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", + "DO5": "BRAM_FIFO18_DOADO5", + "DIBDI0": "BRAM_FIFO18_DIBDI0", + "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", + "WEBWE3": "BRAM_FIFO18_WEBWE3", + "DIBDI6": "BRAM_FIFO18_DIBDI6", + "DO7": "BRAM_FIFO18_DOADO7", + "WEBWE5": "BRAM_FIFO18_WEBWE5", + "DO28": "BRAM_FIFO18_DOBDO12", + "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", + "WEA3": "BRAM_FIFO18_WEA3", + "WEA2": "BRAM_FIFO18_WEA2", + "RDCLK": "BRAM_FIFO18_CLKARDCLK", + "DIADI3": "BRAM_FIFO18_DIADI3", + "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", + "DIBDI3": "BRAM_FIFO18_DIBDI3", + "DIBDI14": "BRAM_FIFO18_DIBDI14", + "DO23": "BRAM_FIFO18_DOBDO7", + "REGCLKB": "BRAM_FIFO18_REGCLKB", + "WRCOUNT5": "BRAM_FIFO18_WRCOUNT5", + "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", + "DO11": "BRAM_FIFO18_DOADO11", + "WREN": "BRAM_FIFO18_ENBWREN", + "WRCOUNT1": "BRAM_FIFO18_WRCOUNT1", + "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", + "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", + "DIBDI12": "BRAM_FIFO18_DIBDI12", + "DIPADIP1": "BRAM_FIFO18_DIPADIP1", + "RST": "BRAM_FIFO18_RSTRAMARSTRAM", + "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", + "DO25": "BRAM_FIFO18_DOBDO9", + "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", + "REGCEB": "BRAM_FIFO18_REGCEB", + "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", + "DIADI2": "BRAM_FIFO18_DIADI2", + "WEBWE7": "BRAM_FIFO18_WEBWE7", + "DO26": "BRAM_FIFO18_DOBDO10", + "DIPADIP0": "BRAM_FIFO18_DIPADIP0", + "DIADI8": "BRAM_FIFO18_DIADI8", + "WRCOUNT9": "BRAM_FIFO18_WRCOUNT9", + "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", + "WEA1": "BRAM_FIFO18_WEA1", + "DO27": "BRAM_FIFO18_DOBDO11", + "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", + "DO31": "BRAM_FIFO18_DOBDO15", + "WRCOUNT0": "BRAM_FIFO18_WRCOUNT0", + "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", + "DIADI9": "BRAM_FIFO18_DIADI9", + "WEBWE4": "BRAM_FIFO18_WEBWE4", + "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", + "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", + "DO19": "BRAM_FIFO18_DOBDO3", + "DO22": "BRAM_FIFO18_DOBDO6", + "WRCOUNT7": "BRAM_FIFO18_WRCOUNT7", + "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", + "DIADI11": "BRAM_FIFO18_DIADI11", + "DO9": "BRAM_FIFO18_DOADO9", + "DO6": "BRAM_FIFO18_DOADO6", + "WRCOUNT8": "BRAM_FIFO18_WRCOUNT8", + "WRCOUNT6": "BRAM_FIFO18_WRCOUNT6", + "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", + "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", + "DIBDI9": "BRAM_FIFO18_DIBDI9", + "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12" + }, + "type": "FIFO18E1", + "prefix": "RAMB18", + "name": "X0Y29", + "x_coord": 0, + "y_coord": 29 + }, + { + "site_pins": { + "DOBDO4": "BRAM_RAMB18_DOBDO4", + "REGCEAREGCE": "BRAM_RAMB18_REGCEAREGCE", + "CLKBWRCLK": "BRAM_RAMB18_CLKBWRCLK", + "DIBDI15": "BRAM_RAMB18_DIBDI15", + "DOADO15": "BRAM_RAMB18_DOADO15", + "DOBDO3": "BRAM_RAMB18_DOBDO3", + "ADDRBWRADDR13": "BRAM_RAMB18_ADDRBWRADDR13", + "DOADO7": "BRAM_RAMB18_DOADO7", + "DIADI13": "BRAM_RAMB18_DIADI13", + "DOBDO13": "BRAM_RAMB18_DOBDO13", + "DOADO2": "BRAM_RAMB18_DOADO2", + "ADDRATIEHIGH1": "BRAM_RAMB18_ADDRATIEHIGH1", + "ENBWREN": "BRAM_RAMB18_ENBWREN", + "DIADI3": "BRAM_RAMB18_DIADI3", + "RDCOUNT9": "BRAM_RAMB18_RDCOUNT9", + "DOADO13": "BRAM_RAMB18_DOADO13", + "ADDRBWRADDR9": "BRAM_RAMB18_ADDRBWRADDR9", + "ADDRBWRADDR8": "BRAM_RAMB18_ADDRBWRADDR8", + "RDCOUNT3": "BRAM_RAMB18_RDCOUNT3", + "WEBWE1": "BRAM_RAMB18_WEBWE1", + "RSTRAMARSTRAM": "BRAM_RAMB18_RSTRAMARSTRAM", + "DIBDI10": "BRAM_RAMB18_DIBDI10", + "ADDRBWRADDR5": "BRAM_RAMB18_ADDRBWRADDR5", + "DIBDI6": "BRAM_RAMB18_DIBDI6", + "ADDRATIEHIGH0": "BRAM_RAMB18_ADDRATIEHIGH0", + "DOBDO14": "BRAM_RAMB18_DOBDO14", + "DIADI0": "BRAM_RAMB18_DIADI0", + "DIPBDIP0": "BRAM_RAMB18_DIPBDIP0", + "DIADI12": "BRAM_RAMB18_DIADI12", + "ADDRBWRADDR4": "BRAM_RAMB18_ADDRBWRADDR4", + "DIADI1": "BRAM_RAMB18_DIADI1", + "RDCOUNT8": "BRAM_RAMB18_RDCOUNT8", + "DIBDI4": "BRAM_RAMB18_DIBDI4", + "EMPTY": "BRAM_RAMB18_EMPTY", + "DIADI5": "BRAM_RAMB18_DIADI5", + "WRCOUNT0": "BRAM_RAMB18_WRCOUNT0", + "RDCOUNT2": "BRAM_RAMB18_RDCOUNT2", + "DOADO6": "BRAM_RAMB18_DOADO6", + "ADDRARDADDR3": "BRAM_RAMB18_ADDRARDADDR3", + "WEA0": "BRAM_RAMB18_WEA0", + "WEBWE0": "BRAM_RAMB18_WEBWE0", + "ADDRBWRADDR1": "BRAM_RAMB18_ADDRBWRADDR1", + "ADDRARDADDR4": "BRAM_RAMB18_ADDRARDADDR4", + "DIBDI13": "BRAM_RAMB18_DIBDI13", + "DOADO5": "BRAM_RAMB18_DOADO5", + "RDCOUNT0": "BRAM_RAMB18_RDCOUNT0", + "ADDRBWRADDR7": "BRAM_RAMB18_ADDRBWRADDR7", + "DOBDO7": "BRAM_RAMB18_DOBDO7", + "DIADI7": "BRAM_RAMB18_DIADI7", + "DIBDI1": "BRAM_RAMB18_DIBDI1", + "WRERR": "BRAM_RAMB18_WRERR", + "WRCOUNT3": "BRAM_RAMB18_WRCOUNT3", + "DOBDO5": "BRAM_RAMB18_DOBDO5", + "DIPBDIP1": "BRAM_RAMB18_DIPBDIP1", + "ADDRARDADDR1": "BRAM_RAMB18_ADDRARDADDR1", + "RSTRAMB": "BRAM_RAMB18_RSTRAMB", + "DOADO1": "BRAM_RAMB18_DOADO1", + "ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0", + "RDCOUNT6": "BRAM_RAMB18_RDCOUNT6", + "DIADI10": "BRAM_RAMB18_DIADI10", + "RSTREGARSTREG": "BRAM_RAMB18_RSTREGARSTREG", + "RSTREGB": "BRAM_RAMB18_RSTREGB", + "WEA1": "BRAM_RAMB18_WEA1", + "ALMOSTFULL": "BRAM_RAMB18_ALMOSTFULL", + "DIADI14": "BRAM_RAMB18_DIADI14", + "DOPADOP0": "BRAM_RAMB18_DOPADOP0", + "DOADO4": "BRAM_RAMB18_DOADO4", + "WEA2": "BRAM_RAMB18_WEA2", + "ADDRBTIEHIGH1": "BRAM_RAMB18_ADDRBTIEHIGH1", + "WEBWE3": "BRAM_RAMB18_WEBWE3", + "DIBDI7": "BRAM_RAMB18_DIBDI7", + "ADDRARDADDR7": "BRAM_RAMB18_ADDRARDADDR7", + "ADDRARDADDR11": "BRAM_RAMB18_ADDRARDADDR11", + "ALMOSTEMPTY": "BRAM_RAMB18_ALMOSTEMPTY", + "WEBWE2": "BRAM_RAMB18_WEBWE2", + "DIBDI11": "BRAM_RAMB18_DIBDI11", + "RDCOUNT7": "BRAM_RAMB18_RDCOUNT7", + "ADDRBWRADDR0": "BRAM_RAMB18_ADDRBWRADDR0", + "DIADI6": "BRAM_RAMB18_DIADI6", + "DIBDI5": "BRAM_RAMB18_DIBDI5", + "ADDRARDADDR10": "BRAM_RAMB18_ADDRARDADDR10", + "DOPBDOP1": "BRAM_RAMB18_DOPBDOP1", + "DIADI11": "BRAM_RAMB18_DIADI11", + "DIADI15": "BRAM_RAMB18_DIADI15", + "FULL": "BRAM_RAMB18_FULL", + "ADDRBWRADDR6": "BRAM_RAMB18_ADDRBWRADDR6", + "ADDRBWRADDR12": "BRAM_RAMB18_ADDRBWRADDR12", + "DIBDI0": "BRAM_RAMB18_DIBDI0", + "RDCOUNT11": "BRAM_RAMB18_RDCOUNT11", + "DOADO8": "BRAM_RAMB18_DOADO8", + "WRCOUNT11": "BRAM_RAMB18_WRCOUNT11", + "DOADO0": "BRAM_RAMB18_DOADO0", + "REGCEB": "BRAM_RAMB18_REGCEB", + "DOBDO9": "BRAM_RAMB18_DOBDO9", + "REGCLKARDRCLK": "BRAM_RAMB18_REGCLKARDRCLK", + "DOBDO2": "BRAM_RAMB18_DOBDO2", + "DIADI4": "BRAM_RAMB18_DIADI4", + "DOPBDOP0": "BRAM_RAMB18_DOPBDOP0", + "DOADO12": "BRAM_RAMB18_DOADO12", + "WEA3": "BRAM_RAMB18_WEA3", + "WRCOUNT4": "BRAM_RAMB18_WRCOUNT4", + "ADDRARDADDR2": "BRAM_RAMB18_ADDRARDADDR2", + "WRCOUNT10": "BRAM_RAMB18_WRCOUNT10", + "DOADO9": "BRAM_RAMB18_DOADO9", + "DIBDI3": "BRAM_RAMB18_DIBDI3", + "DIBDI14": "BRAM_RAMB18_DIBDI14", + "DOPADOP1": "BRAM_RAMB18_DOPADOP1", + "REGCLKB": "BRAM_RAMB18_REGCLKB", + "WRCOUNT5": "BRAM_RAMB18_WRCOUNT5", + "ADDRARDADDR5": "BRAM_RAMB18_ADDRARDADDR5", + "DIBDI2": "BRAM_RAMB18_DIBDI2", + "WRCOUNT1": "BRAM_RAMB18_WRCOUNT1", + "ADDRBWRADDR3": "BRAM_RAMB18_ADDRBWRADDR3", + "ADDRBWRADDR10": "BRAM_RAMB18_ADDRBWRADDR10", + "DIBDI12": "BRAM_RAMB18_DIBDI12", + "DIPADIP1": "BRAM_RAMB18_DIPADIP1", + "ADDRARDADDR9": "BRAM_RAMB18_ADDRARDADDR9", + "RDCOUNT10": "BRAM_RAMB18_RDCOUNT10", + "DOADO3": "BRAM_RAMB18_DOADO3", + "DOBDO1": "BRAM_RAMB18_DOBDO1", + "DOBDO10": "BRAM_RAMB18_DOBDO10", + "ADDRARDADDR8": "BRAM_RAMB18_ADDRARDADDR8", + "RDCOUNT1": "BRAM_RAMB18_RDCOUNT1", + "DOBDO0": "BRAM_RAMB18_DOBDO0", + "ENARDEN": "BRAM_RAMB18_ENARDEN", + "DIADI2": "BRAM_RAMB18_DIADI2", + "WEBWE7": "BRAM_RAMB18_WEBWE7", + "DIBDI8": "BRAM_RAMB18_DIBDI8", + "DIPADIP0": "BRAM_RAMB18_DIPADIP0", + "DIADI8": "BRAM_RAMB18_DIADI8", + "DOBDO8": "BRAM_RAMB18_DOBDO8", + "WRCOUNT9": "BRAM_RAMB18_WRCOUNT9", + "DOADO10": "BRAM_RAMB18_DOADO10", + "RDERR": "BRAM_RAMB18_RDERR", + "DOBDO6": "BRAM_RAMB18_DOBDO6", + "DOADO11": "BRAM_RAMB18_DOADO11", + "WEBWE5": "BRAM_RAMB18_WEBWE5", + "ADDRBWRADDR2": "BRAM_RAMB18_ADDRBWRADDR2", + "ADDRBWRADDR11": "BRAM_RAMB18_ADDRBWRADDR11", + "WRCOUNT2": "BRAM_RAMB18_WRCOUNT2", + "ADDRARDADDR13": "BRAM_RAMB18_ADDRARDADDR13", + "DIADI9": "BRAM_RAMB18_DIADI9", + "WEBWE4": "BRAM_RAMB18_WEBWE4", + "RDCOUNT5": "BRAM_RAMB18_RDCOUNT5", + "DOBDO11": "BRAM_RAMB18_DOBDO11", + "ADDRARDADDR6": "BRAM_RAMB18_ADDRARDADDR6", + "WEBWE6": "BRAM_RAMB18_WEBWE6", + "DOBDO15": "BRAM_RAMB18_DOBDO15", + "WRCOUNT7": "BRAM_RAMB18_WRCOUNT7", + "DOADO14": "BRAM_RAMB18_DOADO14", + "DOBDO12": "BRAM_RAMB18_DOBDO12", + "CLKARDCLK": "BRAM_RAMB18_CLKARDCLK", + "WRCOUNT8": "BRAM_RAMB18_WRCOUNT8", + "WRCOUNT6": "BRAM_RAMB18_WRCOUNT6", + "RDCOUNT4": "BRAM_RAMB18_RDCOUNT4", + "ADDRBTIEHIGH0": "BRAM_RAMB18_ADDRBTIEHIGH0", + "DIBDI9": "BRAM_RAMB18_DIBDI9", + "ADDRARDADDR12": "BRAM_RAMB18_ADDRARDADDR12" + }, + "type": "RAMB18E1", + "prefix": "RAMB18", + "name": "X0Y30", + "x_coord": 0, + "y_coord": 30 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_BRAM_R.json b/artix7/tile_type_BRAM_R.json index f254ecc..e9729e8 100644 --- a/artix7/tile_type_BRAM_R.json +++ b/artix7/tile_type_BRAM_R.json @@ -1,9834 +1,9834 @@ { - "wires": [ - "BRAM_FIFO18_DOBDO0", - "BRAM_FIFO18_DIADI15", - "BRAM_FIFO36_TSTBRAMRST", - "BRAM_LOGIC_OUTS_B5_4", - "BRAM_ADDRBWRADDRL3", - "BRAM_IMUX35_4", - "BRAM_FIFO36_ADDRBWRADDRL9", - "BRAM_UTURN_ADDRBWRADDRU10", - "BRAM_FIFO36_DOBDOU8", - "BRAM_ADDRARDADDRU12", - "BRAM_SE4C2_0", - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "BRAM_IMUX41_4", - "BRAM_FIFO36_DOADOU8", - "BRAM_IMUX29_UTURN_4", - "BRAM_IMUX4_0", - "BRAM_FIFO18_RSTREGARSTREG", - "BRAM_FIFO18_DIBDI10", - "BRAM_IMUX34_UTURN_2", - "BRAM_LH4_3", - "BRAM_FIFO36_WRCOUNT12", - "BRAM_EE2BEG3_0", - "BRAM_RAMB18_WRERR", - "BRAM_FIFO18_DIADI9", - "BRAM_FIFO36_ADDRBWRADDRU14", - "BRAM_EE4BEG0_4", - "BRAM_CASCINBOT_ADDRARDADDRU8", - "BRAM_WW4C0_1", - "BRAM_EE2A2_2", - "BRAM_EE4C2_1", - "BRAM_RAMB18_DOADO12", - "BRAM_CLK1_1", - "BRAM_FIFO18_DOADO10", - "BRAM_FIFO36_RDCOUNT5", - "BRAM_FIFO18_DOADO8", - "BRAM_RAMB18_REGCEAREGCE", - "BRAM_LOGIC_OUTS_B8_0", - "BRAM_WW4END1_2", - "BRAM_LH9_0", - "BRAM_WR1END0_2", - "BRAM_R_IMUX_ADDRBWRADDRL0", - "BRAM_WR1END1_2", - "BRAM_SW2A2_3", - "BRAM_ADDRBWRADDRL12", - "BRAM_UTURN_ADDRBWRADDRL4", - "BRAM_FIFO36_DOPADOPL1", - "BRAM_FIFO18_EMPTY", - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "BRAM_IMUX4_UTURN_1", - "BRAM_NW4A2_0", - "BRAM_WW4END2_1", - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "BRAM_IMUX31_0", - "BRAM_IMUX7_UTURN_0", - "BRAM_UTURN_ADDRARDADDRU0", - "BRAM_EE4A0_4", - "BRAM_FIFO36_RDCOUNT6", - "BRAM_WW4A1_2", - "BRAM_IMUX40_1", - "BRAM_FIFO36_WEAU2", - "BRAM_LOGIC_OUTS_B21_4", - "BRAM_ADDRARDADDRU3", - "BRAM_IMUX33_2", - "BRAM_ADDRARDADDRU9", - "BRAM_NE4BEG3_3", - "BRAM_LOGIC_OUTS_B12_3", - "BRAM_FIFO36_DIBDIU10", - "BRAM_EE2A3_2", - "BRAM_FIFO36_TSTIN3", - "BRAM_IMUX37_UTURN_2", - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRAM_WR1END2_4", - "BRAM_FIFO18_DIBDI1", - "BRAM_IMUX42_UTURN_4", - "BRAM_MONITOR_P_2", - "BRAM_IMUX38_3", - "BRAM_SW4END3_4", - "BRAM_RAMB18_DIBDI0", - "BRAM_BYP4_0", - "BRAM_ADDRARDADDRU4", - "BRAM_RAMB18_ADDRBTIEHIGH1", - "BRAM_RAMB18_DIBDI14", - "BRAM_IMUX10_UTURN_3", - "BRAM_R_IMUX_ADDRBWRADDRU14", - "BRAM_ADDRARDADDRL9", - "BRAM_R_IMUX_ADDRBWRADDRL8", - "BRAM_FAN2_3", - "BRAM_WW2END0_4", - "BRAM_FIFO18_ADDRARDADDR10", - "BRAM_UTURN_ADDRBWRADDRL12", - "BRAM_FIFO36_WRCOUNT6", - "BRAM_IMUX29_4", - "BRAM_RAMB18_RSTRAMARSTRAM", - "BRAM_BYP7_2", - "BRAM_FIFO18_DOADO11", - "BRAM_RAMB18_RSTREGB", - "BRAM_UTURN_ADDRBWRADDRL6", - "BRAM_NE4C3_0", - "BRAM_LOGIC_OUTS_B20_2", - "BRAM_FIFO36_WEBWEL5", - "BRAM_FIFO36_DIBDIU5", - "BRAM_SW2A0_4", - "BRAM_UTURN_ADDRARDADDRU7", - "BRAM_FIFO18_WRCOUNT5", - "BRAM_WW2A1_3", - "BRAM_RAMB18_DIADI9", - "BRAM_SE4C1_1", - "BRAM_LOGIC_OUTS_B3_1", - "BRAM_IMUX14_UTURN_3", - "BRAM_CASCOUT_ADDRARDADDRU9", - "BRAM_RAMB18_RDCOUNT7", - "BRAM_FIFO36_INJECTDBITERR", - "BRAM_FIFO36_ADDRBWRADDRL15", - "BRAM_BLOCK_OUTS_L_B1_4", - "BRAM_EE4BEG1_2", - "BRAM_R_IMUX_ADDRARDADDRL14", - "BRAM_ADDRARDADDRL13", - "BRAM_IMUX23_0", - "BRAM_IMUX30_UTURN_2", - "BRAM_RAMB18_REGCEB", - "BRAM_R_IMUX_ADDRBWRADDRU3", - "BRAM_IMUX22_0", - "BRAM_RAMB18_ADDRATIEHIGH1", - "BRAM_RAMB18_DOADO6", - "BRAM_SW4END1_4", - "BRAM_FIFO36_DIBDIL3", - "BRAM_EE4C1_0", - "BRAM_FIFO36_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU4", - "BRAM_NE2A2_0", - "BRAM_IMUX2_3", - "BRAM_IMUX21_2", - "BRAM_IMUX45_0", - "BRAM_ER1BEG3_4", - "BRAM_FIFO18_ADDRBWRADDR12", - "BRAM_FAN0_3", - "BRAM_FIFO18_WRCOUNT8", - "BRAM_IMUX32_4", - "BRAM_LOGIC_OUTS_B2_3", - "BRAM_FIFO18_DOBDO3", - "BRAM_RAMB18_RDERR", - "BRAM_IMUX0_0", - "BRAM_IMUX37_3", - "BRAM_FIFO18_ADDRARDADDR5", - "BRAM_IMUX38_UTURN_0", - "BRAM_RAMB18_DOADO1", - "BRAM_LH4_4", - "BRAM_ER1BEG2_3", - "BRAM_ADDRBWRADDRU5", - "BRAM_FIFO36_DIADIU12", - "BRAM_IMUX5_2", - "BRAM_IMUX37_2", - "BRAM_SE2A2_2", - "BRAM_RAMB18_ADDRARDADDR3", - "BRAM_IMUX22_2", - "BRAM_IMUX44_0", - "BRAM_IMUX3_UTURN_4", - "BRAM_IMUX13_4", - "BRAM_FIFO36_RDCOUNT7", - "BRAM_FIFO36_ECCPARITY1", - "BRAM_IMUX19_2", - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "BRAM_FIFO36_ADDRARDADDRU4", - "BRAM_IMUX43_2", - "BRAM_IMUX27_UTURN_0", - "BRAM_FIFO18_WRCOUNT4", - "BRAM_IMUX44_2", - "BRAM_RAMB18_DIBDI2", - "BRAM_LOGIC_OUTS_B19_3", - "BRAM_CASCOUT_ADDRBWRADDRU8", - "BRAM_BYP3_1", - "BRAM_ADDRARDADDRL7", - "BRAM_FIFO18_CLKBWRCLK", - "BRAM_FIFO18_ADDRBWRADDR8", - "BRAM_ADDRBWRADDRU3", - "BRAM_NE4BEG2_2", - "BRAM_UTURN_ADDRARDADDRL6", - "BRAM_IMUX25_UTURN_2", - "BRAM_FIFO36_DIBDIL4", - "BRAM_CASCINBOT_ADDRARDADDRU14", - "BRAM_FIFO18_RDCOUNT7", - "BRAM_EL1BEG0_2", - "BRAM_WW2A0_4", - "BRAM_FIFO36_DIBDIU6", - "BRAM_WW2A0_3", - "BRAM_WW4END0_4", - "BRAM_RAMB18_RDCOUNT6", - "BRAM_UTURN_ADDRARDADDRU14", - "BRAM_R_IMUX_ADDRARDADDRU1", - "BRAM_LOGIC_OUTS_B20_3", - "BRAM_IMUX3_0", - "BRAM_EE4BEG3_1", - "BRAM_ADDRARDADDRU0", - "BRAM_IMUX34_2", - "BRAM_IMUX37_UTURN_1", - "BRAM_FAN5_4", - "BRAM_FIFO18_WEBWE4", - "BRAM_SE4BEG2_3", - "BRAM_SE4C3_0", - "BRAM_IMUX16_0", - "BRAM_WR1END2_1", - "BRAM_FIFO36_WRERR", - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRAM_WW4B0_0", - "BRAM_RAMB18_WRCOUNT6", - "BRAM_NW4END2_3", - "BRAM_FIFO18_ADDRARDADDR11", - "BRAM_FAN0_1", - "BRAM_LOGIC_OUTS_B10_3", - "BRAM_IMUX16_1", - "BRAM_IMUX30_4", - "BRAM_LOGIC_OUTS_B13_2", - "BRAM_NE4BEG0_3", - "BRAM_FIFO36_DIADIU8", - "BRAM_FIFO18_WRCOUNT0", - "BRAM_ER1BEG1_3", - "BRAM_FIFO36_DIADIL2", - "BRAM_SE2A0_0", - "BRAM_RAMB18_DIADI10", - "BRAM_FIFO36_DIADIL9", - "BRAM_LH11_4", - "BRAM_NE2A2_2", - "BRAM_LOGIC_OUTS_B21_3", - "BRAM_FIFO18_ADDRBWRADDR0", - "BRAM_FIFO36_TSTCNT9", - "BRAM_RAMB18_RDCOUNT10", - "BRAM_LH2_4", - "BRAM_LOGIC_OUTS_B15_2", - "BRAM_NW4END0_2", - "BRAM_WW2END3_1", - "BRAM_IMUX3_UTURN_3", - "BRAM_FAN4_3", - "BRAM_FIFO36_ADDRARDADDRL12", - "BRAM_FIFO36_DOPADOPU0", - "BRAM_NE4BEG1_3", - "BRAM_UTURN_ADDRARDADDRL8", - "BRAM_FIFO18_DOBDO1", - "BRAM_IMUX28_2", - "BRAM_WW2A0_2", - "BRAM_FIFO36_RSTRAMBU", - "BRAM_WW4A3_1", - "BRAM_IMUX41_2", - "BRAM_SE4BEG3_3", - "BRAM_IMUX23_UTURN_2", - "BRAM_BLOCK_OUTS_L_B3_0", - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRAM_WW4C0_0", - "BRAM_IMUX30_UTURN_1", - "BRAM_RAMB18_WRCOUNT5", - "BRAM_FAN0_2", - "BRAM_SW4END1_3", - "BRAM_IMUX33_UTURN_3", - "BRAM_IMUX36_UTURN_2", - "BRAM_IMUX25_UTURN_4", - "BRAM_LOGIC_OUTS_B18_3", - "BRAM_IMUX1_UTURN_4", - "BRAM_RAMB18_ADDRBWRADDR5", - "BRAM_PMVBRAM_SELECT3", - "BRAM_RAMB18_RDCOUNT11", - "BRAM_IMUX15_4", - "BRAM_NE2A0_3", - "BRAM_LOGIC_OUTS_B21_1", - "BRAM_NE4C2_4", - "BRAM_IMUX17_1", - "BRAM_LOGIC_OUTS_B9_3", - "BRAM_ER1BEG0_3", - "BRAM_IMUX20_UTURN_1", - "BRAM_RAMB18_DOADO15", - "BRAM_NW2A2_2", - "BRAM_UTURN_ADDRBWRADDRU13", - "BRAM_NW4END3_4", - "BRAM_IMUX38_UTURN_4", - "BRAM_LOGIC_OUTS_B11_4", - "BRAM_IMUX0_UTURN_4", - "BRAM_RAMB18_WRCOUNT7", - "BRAM_NW4A1_4", - "BRAM_LH11_3", - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRAM_FIFO36_DIBDIL2", - "BRAM_NW4A3_4", - "BRAM_FIFO36_DOBDOL1", - "BRAM_FIFO36_WRCOUNT9", - "BRAM_IMUX22_3", - "BRAM_LH10_4", - "BRAM_IMUX3_UTURN_1", - "BRAM_FAN7_0", - "BRAM_SW2A1_0", - "BRAM_IMUX42_UTURN_0", - "BRAM_LOGIC_OUTS_B3_3", - "BRAM_IMUX13_UTURN_1", - "BRAM_FIFO36_DOADOL13", - "BRAM_WL1END0_1", - "BRAM_EE4C3_4", - "BRAM_IMUX43_1", - "BRAM_CASCOUT_ADDRBWRADDRU10", - "BRAM_FIFO36_SBITERR", - "BRAM_FIFO36_DOADOU12", - "BRAM_R_IMUX_ADDRBWRADDRU13", - "BRAM_IMUX29_2", - "BRAM_FAN1_1", - "BRAM_SE4C1_2", - "BRAM_RAMB18_DOADO0", - "BRAM_LH1_2", - "BRAM_FIFO36_DOBDOL3", - "BRAM_WW2A0_0", - "BRAM_IMUX34_UTURN_1", - "BRAM_RAMB18_WRCOUNT9", - "BRAM_NW2A3_4", - "BRAM_IMUX36_UTURN_1", - "BRAM_LOGIC_OUTS_B5_3", - "BRAM_WW2A3_0", - "BRAM_IMUX6_UTURN_4", - "BRAM_IMUX28_UTURN_0", - "BRAM_EE2A3_3", - "BRAM_FIFO36_ADDRARDADDRU10", - "BRAM_RAMB18_EMPTY", - "BRAM_FIFO18_REGCEB", - "BRAM_FIFO36_DIPBDIPL0", - "BRAM_CASCINBOT_ADDRARDADDRU13", - "BRAM_WW2A3_4", - "BRAM_IMUX28_UTURN_3", - "BRAM_SW4END2_1", - "BRAM_LOGIC_OUTS_B21_0", - "BRAM_NE4C2_1", - "BRAM_NE4BEG1_2", - "BRAM_EE4B1_2", - "BRAM_FIFO36_DOADOL9", - "BRAM_WR1END3_2", - "BRAM_IMUX37_4", - "BRAM_LOGIC_OUTS_B15_0", - "BRAM_EE2BEG1_4", - "BRAM_FIFO18_ADDRBWRADDR11", - "BRAM_NW4A3_0", - "BRAM_EE4B2_2", - "BRAM_FIFO36_ADDRARDADDRL3", - "BRAM_FIFO36_WRCOUNT1", - "BRAM_EE4C3_2", - "BRAM_FIFO36_DOADOU7", - "BRAM_IMUX43_4", - "BRAM_LH5_1", - "BRAM_RAMB18_ADDRBWRADDR4", - "BRAM_RAMB18_ADDRBWRADDR8", - "BRAM_SW4A3_2", - "BRAM_CASCOUT_ADDRBWRADDRU12", - "BRAM_UTURN_ADDRBWRADDRU3", - "BRAM_FIFO18_ADDRARDADDR7", - "BRAM_FIFO36_DOADOU10", - "BRAM_FIFO18_WRCOUNT10", - "BRAM_WW4A2_3", - "BRAM_LH10_3", - "BRAM_CASCOUT_ADDRARDADDRU0", - "BRAM_EL1BEG1_3", - "BRAM_RAMB18_DIBDI4", - "BRAM_IMUX18_1", - "BRAM_FIFO18_DIBDI4", - "BRAM_UTURN_ADDRARDADDRL10", - "BRAM_IMUX46_3", - "BRAM_R_IMUX_ADDRARDADDRL1", - "BRAM_SE4C0_2", - "BRAM_R_IMUX_ADDRARDADDRL4", - "BRAM_RAMB18_RSTRAMB", - "BRAM_IMUX14_UTURN_2", - "BRAM_FIFO36_DIADIU9", - "BRAM_SE4C1_4", - "BRAM_BYP0_3", - "BRAM_IMUX29_UTURN_0", - "BRAM_RAMB18_DOBDO14", - "BRAM_SE2A2_3", - "BRAM_FIFO18_ADDRARDADDR6", - "BRAM_EE2BEG1_2", - "BRAM_IMUX35_UTURN_0", - "BRAM_IMUX9_UTURN_2", - "BRAM_RAMB18_DIPBDIP1", - "BRAM_IMUX5_UTURN_4", - "BRAM_LOGIC_OUTS_B18_0", - "BRAM_RAMB18_DIADI0", - "BRAM_FIFO18_WEBWE2", - "BRAM_IMUX33_UTURN_0", - "BRAM_WL1END2_0", - "BRAM_FIFO18_RDCOUNT0", - "BRAM_LH1_1", - "BRAM_IMUX26_UTURN_0", - "BRAM_R_IMUX_ADDRBWRADDRU11", - "BRAM_IMUX15_0", - "BRAM_R_IMUX_ADDRARDADDRL3", - "BRAM_FIFO36_ADDRBWRADDRU5", - "BRAM_FIFO36_DOBDOL15", - "BRAM_IMUX7_UTURN_2", - "BRAM_FIFO36_DOBDOL10", - "BRAM_LH5_3", - "BRAM_ER1BEG0_4", - "BRAM_RAMB18_ADDRARDADDR1", - "BRAM_FIFO36_DOBDOU11", - "BRAM_WW4B3_2", - "BRAM_LH7_3", - "BRAM_FIFO36_DOBDOU5", - "BRAM_WW2END2_2", - "BRAM_FIFO36_ADDRARDADDRU13", - "BRAM_R_IMUX_ADDRARDADDRU8", - "BRAM_FIFO36_ADDRBWRADDRL13", - "BRAM_FIFO36_TSTIN0", - "BRAM_LH2_0", - "BRAM_NW4END1_2", - "BRAM_IMUX20_1", - "BRAM_FAN4_0", - "BRAM_IMUX36_1", - "BRAM_FIFO36_ADDRARDADDRL8", - "BRAM_BYP2_4", - "BRAM_FIFO36_ENBWRENU", - "BRAM_SW4END3_2", - "BRAM_IMUX25_4", - "BRAM_WW2END1_3", - "BRAM_CASCOUT_ADDRBWRADDRU9", - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRAM_MONITOR_N_0", - "BRAM_BYP7_1", - "BRAM_NE4C0_4", - "BRAM_WW4B3_4", - "BRAM_RAMB18_REGCLKB", - "BRAM_BYP3_2", - "BRAM_IMUX27_4", - "BRAM_FIFO18_DIADI10", - "BRAM_LOGIC_OUTS_B15_4", - "BRAM_SE2A2_1", - "BRAM_EE2BEG3_1", - "BRAM_MONITOR_P_4", - "BRAM_UTURN_ADDRARDADDRL3", - "BRAM_FIFO36_DIBDIU7", - "BRAM_RAMB18_DOADO2", - "BRAM_NW4A2_2", - "BRAM_FIFO36_DOADOL5", - "BRAM_SW4END2_0", - "BRAM_NE4BEG3_0", - "BRAM_LH11_2", - "BRAM_UTURN_ADDRBWRADDRU2", - "BRAM_WR1END1_4", - "BRAM_CTRL0_2", - "BRAM_NE4BEG0_0", - "BRAM_FIFO18_WEA3", - "BRAM_FIFO36_ADDRARDADDRL6", - "BRAM_IMUX3_UTURN_0", - "BRAM_CASCINBOT_ADDRARDADDRU11", - "BRAM_WW4A0_4", - "BRAM_IMUX6_UTURN_2", - "BRAM_SW4A3_0", - "BRAM_WW2END2_4", - "BRAM_RAMB18_WEBWE0", - "BRAM_BYP6_3", - "BRAM_EL1BEG2_4", - "BRAM_NW4A3_2", - "BRAM_IMUX42_UTURN_1", - "BRAM_WW2END3_0", - "BRAM_FIFO36_DIADIU15", - "BRAM_R_IMUX_ADDRARDADDRU3", - "BRAM_NE4C3_2", - "BRAM_EE2BEG0_1", - "BRAM_CASCOUT_ADDRARDADDRU6", - "BRAM_FIFO36_ADDRBWRADDRL3", - "BRAM_WW4C2_1", - "BRAM_IMUX19_UTURN_3", - "BRAM_BYP7_0", - "BRAM_EE4C1_3", - "BRAM_SE2A3_4", - "BRAM_R_IMUX_ADDRARDADDRU5", - "BRAM_NW2A1_3", - "BRAM_CTRL0_3", - "BRAM_LOGIC_OUTS_B12_0", - "BRAM_SW4END3_3", - "BRAM_IMUX13_1", - "BRAM_LOGIC_OUTS_B6_4", - "BRAM_FIFO36_ADDRARDADDRU5", - "BRAM_FIFO36_RDERR", - "BRAM_IMUX32_UTURN_3", - "BRAM_SE4BEG0_0", - "BRAM_IMUX22_UTURN_3", - "BRAM_BYP7_3", - "BRAM_IMUX37_1", - "BRAM_IMUX35_UTURN_1", - "BRAM_IMUX4_2", - "BRAM_FIFO18_DOADO3", - "BRAM_SE2A0_3", - "BRAM_FIFO36_TSTWROS12", - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRAM_PMVBRAM_O_2", - "BRAM_EE4B2_1", - "BRAM_UTURN_ADDRARDADDRU1", - "BRAM_IMUX9_UTURN_1", - "BRAM_FIFO18_DIADI12", - "BRAM_LH4_0", - "BRAM_ADDRARDADDRL2", - "BRAM_SW4END0_4", - "BRAM_FIFO36_WEBWEL7", - "BRAM_IMUX4_UTURN_4", - "BRAM_WW2END1_2", - "BRAM_WR1END0_1", - "BRAM_FIFO36_ADDRBWRADDRU6", - "BRAM_SE4C2_2", - "BRAM_IMUX36_2", - "BRAM_BLOCK_OUTS_L_B0_3", - "BRAM_BYP4_1", - "BRAM_UTURN_ADDRBWRADDRL7", - "BRAM_FIFO36_RDCOUNT8", - "BRAM_IMUX42_2", - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "BRAM_SW4END2_4", - "BRAM_FIFO36_DIBDIU3", - "BRAM_FIFO18_DOBDO10", - "BRAM_LOGIC_OUTS_B10_4", - "BRAM_RAMB18_WEBWE1", - "BRAM_RAMB18_RDCOUNT2", - "BRAM_FIFO36_ADDRBWRADDRL14", - "BRAM_IMUX24_1", - "BRAM_IMUX24_4", - "BRAM_EE4B1_3", - "BRAM_R_IMUX_ADDRARDADDRL2", - "BRAM_BLOCK_OUTS_L_B1_0", - "BRAM_CASCOUT_ADDRARDADDRU11", - "BRAM_LOGIC_OUTS_B22_0", - "BRAM_FIFO36_WEBWEL2", - "BRAM_IMUX33_1", - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRAM_CASCINBOT_ADDRARDADDRU10", - "BRAM_LOGIC_OUTS_B6_2", - "BRAM_EE4C0_2", - "BRAM_FIFO18_DIADI5", - "BRAM_WR1END2_0", - "BRAM_EE4A0_0", - "BRAM_IMUX31_UTURN_2", - "BRAM_IMUX15_UTURN_4", - "BRAM_FIFO36_DOBDOL4", - "BRAM_EE4A2_4", - "BRAM_RAMB18_ADDRBWRADDR11", - "BRAM_FIFO36_WEBWEU5", - "BRAM_UTURN_ADDRBWRADDRL3", - "BRAM_ADDRBWRADDRL0", - "BRAM_WL1END1_3", - "BRAM_BYP5_3", - "BRAM_IMUX23_UTURN_0", - "BRAM_FIFO36_DOADOU6", - "BRAM_LOGIC_OUTS_B2_0", - "BRAM_EE4C3_1", - "BRAM_CASCOUT_ADDRARDADDRU2", - "BRAM_FIFO18_WRERR", - "BRAM_WL1END2_4", - "BRAM_FIFO36_ADDRBWRADDRL7", - "BRAM_ADDRARDADDRU7", - "BRAM_FIFO36_DIBDIL11", - "BRAM_NW4A1_3", - "BRAM_IMUX19_3", - "BRAM_UTURN_ADDRARDADDRL5", - "BRAM_FIFO36_TSTWRCNTOFF", - "BRAM_LOGIC_OUTS_B13_3", - "BRAM_IMUX18_UTURN_4", - "BRAM_FIFO36_ECCPARITY2", - "BRAM_LH12_0", - "BRAM_UTURN_ADDRBWRADDRU0", - "BRAM_FIFO18_DOBDO7", - "BRAM_LH7_2", - "BRAM_IMUX40_UTURN_2", - "BRAM_EE4A1_1", - "BRAM_IMUX27_2", - "BRAM_NE2A0_0", - "BRAM_WW4B2_1", - "BRAM_LOGIC_OUTS_B18_2", - "BRAM_FIFO18_DOPBDOP1", - "BRAM_IMUX20_UTURN_4", - "BRAM_NW2A1_4", - "BRAM_R_IMUX_ADDRARDADDRL10", - "BRAM_IMUX6_3", - "BRAM_EE2A2_4", - "BRAM_NW4END1_4", - "BRAM_IMUX36_3", - "BRAM_IMUX34_UTURN_0", - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "BRAM_ADDRBWRADDRU8", - "BRAM_RAMB18_DOADO14", - "BRAM_IMUX22_1", - "BRAM_IMUX44_UTURN_1", - "BRAM_IMUX40_3", - "BRAM_WW4A2_0", - "BRAM_IMUX13_3", - "BRAM_BLOCK_OUTS_L_B2_0", - "BRAM_FIFO36_TSTRDOS5", - "BRAM_IMUX29_1", - "BRAM_FIFO36_TSTCNT5", - "BRAM_FIFO18_DIBDI5", - "BRAM_EE2BEG2_0", - "BRAM_LOGIC_OUTS_B12_4", - "BRAM_NE4BEG0_1", - "BRAM_IMUX8_4", - "BRAM_CASCINBOT_ADDRARDADDRU1", - "BRAM_WW4END0_3", - "BRAM_FIFO18_DOADO2", - "BRAM_IMUX24_UTURN_2", - "BRAM_FIFO36_ADDRARDADDRL0", - "BRAM_SE2A0_4", - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRAM_FIFO18_ADDRBWRADDR6", - "BRAM_LH5_2", - "BRAM_R_IMUX_ADDRBWRADDRL3", - "BRAM_SW2A0_0", - "BRAM_IMUX7_0", - "BRAM_FIFO36_RDCOUNT2", - "BRAM_RAMB18_WEBWE6", - "BRAM_FAN0_4", - "BRAM_WW4A0_2", - "BRAM_LOGIC_OUTS_B11_3", - "BRAM_FIFO36_TSTOUT1", - "BRAM_CASCINBOT_ADDRARDADDRU7", - "BRAM_BYP1_0", - "BRAM_EE4A1_0", - "BRAM_FIFO36_CASCADEOUTB_1", - "BRAM_LH2_3", - "BRAM_NW2A0_0", - "BRAM_FIFO36_WRCOUNT3", - "BRAM_WW2A3_1", - "BRAM_IMUX7_1", - "BRAM_EE2A0_1", - "BRAM_FIFO36_DIBDIL0", - "BRAM_FIFO18_ADDRARDADDR8", - "BRAM_FIFO36_ADDRBWRADDRL12", - "BRAM_IMUX34_UTURN_4", - "BRAM_IMUX43_UTURN_2", - "BRAM_SW4END3_0", - "BRAM_FIFO18_WRCOUNT7", - "BRAM_NE2A0_2", - "BRAM_IMUX6_UTURN_0", - "BRAM_IMUX46_UTURN_2", - "BRAM_LH4_1", - "BRAM_ADDRARDADDRU5", - "BRAM_IMUX28_1", - "BRAM_R_IMUX_ADDRARDADDRU9", - "BRAM_FIFO36_TSTCNT8", - "BRAM_FIFO36_ENBWRENL", - "BRAM_FIFO36_RSTREGBU", - "BRAM_FIFO36_ECCPARITY5", - "BRAM_FIFO36_TSTRDOS8", - "BRAM_SW4A2_1", - "BRAM_EE2A1_1", - "BRAM_IMUX12_UTURN_1", - "BRAM_IMUX26_UTURN_1", - "BRAM_IMUX37_UTURN_0", - "BRAM_FIFO36_CLKARDCLKU", - "BRAM_RAMB18_RDCOUNT1", - "BRAM_FIFO36_REGCLKBL", - "BRAM_EE4B0_1", - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRAM_FIFO18_DOADO14", - "BRAM_WW4C2_4", - "BRAM_LH8_0", - "BRAM_IMUX27_UTURN_4", - "BRAM_IMUX45_1", - "BRAM_LOGIC_OUTS_B4_2", - "BRAM_FIFO18_ADDRARDADDR4", - "BRAM_FIFO36_TSTCNT11", - "BRAM_BYP1_3", - "BRAM_EE4A1_2", - "BRAM_FIFO36_DIADIL12", - "BRAM_SW2A3_4", - "BRAM_IMUX0_UTURN_0", - "BRAM_NW2A3_3", - "BRAM_IMUX38_UTURN_1", - "BRAM_ER1BEG2_0", - "BRAM_FIFO36_DOADOL6", - "BRAM_LH6_4", - "BRAM_EE4B2_0", - "BRAM_ER1BEG1_1", - "BRAM_FIFO18_DIADI3", - "BRAM_FIFO18_ADDRARDADDR9", - "BRAM_WW2END0_0", - "BRAM_IMUX26_UTURN_2", - "BRAM_FIFO36_TSTIN1", - "BRAM_FIFO18_ALMOSTEMPTY", - "BRAM_NW4A1_0", - "BRAM_RAMB18_RDCOUNT5", - "BRAM_FIFO36_ADDRBWRADDRL5", - "BRAM_IMUX2_UTURN_1", - "BRAM_FAN2_1", - "BRAM_LOGIC_OUTS_B14_4", - "BRAM_FIFO18_WEA1", - "BRAM_SE4BEG1_4", - "BRAM_RAMB18_DIADI13", - "BRAM_RAMB18_ADDRARDADDR2", - "BRAM_IMUX30_UTURN_0", - "BRAM_NE4C0_2", - "BRAM_FIFO36_DOADOU14", - "BRAM_WW4A0_1", - "BRAM_MONITOR_N_4", - "BRAM_RAMB18_WEBWE2", - "BRAM_BYP6_2", - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRAM_FIFO36_DOPADOPU1", - "BRAM_RAMB18_ADDRBWRADDR6", - "BRAM_NE4BEG3_1", - "BRAM_FIFO18_RDERR", - "BRAM_LOGIC_OUTS_B4_0", - "BRAM_FIFO36_ADDRBWRADDRL6", - "BRAM_UTURN_ADDRARDADDRL0", - "BRAM_SE2A0_1", - "BRAM_FIFO36_TSTCNT1", - "BRAM_FAN3_2", - "BRAM_FIFO18_ADDRBWRADDR5", - "BRAM_IMUX5_4", - "BRAM_SW2A3_1", - "BRAM_R_IMUX_ADDRARDADDRL6", - "BRAM_LH12_2", - "BRAM_LOGIC_OUTS_B9_4", - "BRAM_CTRL1_4", - "BRAM_RAMB18_DOADO11", - "BRAM_FIFO36_DOADOL7", - "BRAM_IMUX30_UTURN_4", - "BRAM_EE4BEG1_1", - "BRAM_IMUX36_0", - "BRAM_CLK0_1", - "BRAM_SE4BEG2_2", - "BRAM_ADDRARDADDRU10", - "BRAM_SW2A1_4", - "BRAM_R_IMUX_ADDRARDADDRU14", - "BRAM_NW2A0_4", - "BRAM_SE4C3_3", - "BRAM_FIFO36_WRCOUNT5", - "BRAM_IMUX24_UTURN_3", - "BRAM_BLOCK_OUTS_L_B2_1", - "BRAM_IMUX32_UTURN_4", - "BRAM_FIFO36_DOADOU5", - "BRAM_LH9_1", - "BRAM_IMUX7_UTURN_4", - "BRAM_CLK1_0", - "BRAM_IMUX43_0", - "BRAM_IMUX8_3", - "BRAM_FIFO36_DIPADIPL0", - "BRAM_EL1BEG1_1", - "BRAM_IMUX45_UTURN_4", - "BRAM_MONITOR_P_1", - "BRAM_WW2A1_2", - "BRAM_FIFO36_DIBDIU1", - "BRAM_BYP0_1", - "BRAM_CASCOUT_ADDRARDADDRU14", - "BRAM_FIFO36_TSTCNT10", - "BRAM_SW2A0_3", - "BRAM_BYP5_2", - "BRAM_LOGIC_OUTS_B7_1", - "BRAM_FIFO36_TSTWROS6", - "BRAM_EL1BEG0_0", - "BRAM_IMUX35_UTURN_4", - "BRAM_CASCINBOT_ADDRARDADDRU2", - "BRAM_ER1BEG3_0", - "BRAM_IMUX24_UTURN_0", - "BRAM_RAMB18_ADDRBWRADDR7", - "BRAM_BYP3_4", - "BRAM_RAMB18_DIBDI7", - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRAM_R_IMUX_ADDRBWRADDRL13", - "BRAM_FIFO36_DIADIL7", - "BRAM_IMUX20_UTURN_0", - "BRAM_IMUX46_1", - "BRAM_NW4END2_4", - "BRAM_SW2A3_0", - "BRAM_FIFO18_DIADI6", - "BRAM_RAMB18_DOBDO13", - "BRAM_SW4A3_1", - "BRAM_RAMB18_DIPADIP1", - "BRAM_FAN2_0", - "BRAM_NE2A1_4", - "BRAM_UTURN_ADDRARDADDRU6", - "BRAM_EL1BEG1_0", - "BRAM_FIFO36_ADDRARDADDRL11", - "BRAM_IMUX30_UTURN_3", - "BRAM_RAMB18_RDCOUNT3", - "BRAM_NE2A0_4", - "BRAM_IMUX32_UTURN_1", - "BRAM_LOGIC_OUTS_B16_0", - "BRAM_FIFO36_RDCOUNT9", - "BRAM_NE4BEG3_2", - "BRAM_R_IMUX_ADDRARDADDRL12", - "BRAM_NE4C2_2", - "BRAM_IMUX11_UTURN_2", - "BRAM_FIFO36_TSTRDOS7", - "BRAM_BLOCK_OUTS_L_B2_4", - "BRAM_IMUX40_UTURN_1", - "BRAM_WL1END1_2", - "BRAM_UTURN_ADDRARDADDRL11", - "BRAM_FIFO36_WEBWEL0", - "BRAM_FIFO36_DIBDIU15", - "BRAM_RAMB18_DOADO9", - "BRAM_FIFO36_TSTWROS0", - "BRAM_R_IMUX_ADDRARDADDRL7", - "BRAM_EE2BEG2_3", - "BRAM_SE2A1_2", - "BRAM_FIFO36_WEBWEU1", - "BRAM_IMUX25_2", - "BRAM_EE2BEG1_0", - "BRAM_R_IMUX_ADDRARDADDRU11", - "BRAM_FIFO36_DOBDOU7", - "BRAM_RAMB18_DIADI12", - "BRAM_FIFO18_RDCOUNT5", - "BRAM_IMUX24_UTURN_4", - "BRAM_FIFO36_FULL", - "BRAM_WW2END1_1", - "BRAM_FIFO18_DOADO12", - "BRAM_IMUX44_4", - "BRAM_FIFO36_TSTRDOS6", - "BRAM_CLK0_3", - "BRAM_LOGIC_OUTS_B16_3", - "BRAM_IMUX38_4", - "BRAM_WW4END3_1", - "BRAM_ER1BEG1_2", - "BRAM_IMUX18_2", - "BRAM_IMUX46_UTURN_4", - "BRAM_LOGIC_OUTS_B22_3", - "BRAM_RAMB18_DIADI7", - "BRAM_IMUX13_UTURN_2", - "BRAM_IMUX4_1", - "BRAM_NW4END0_1", - "BRAM_IMUX18_4", - "BRAM_IMUX0_UTURN_1", - "BRAM_RAMB18_ADDRARDADDR12", - "BRAM_EE4B1_1", - "BRAM_EE2A3_0", - "BRAM_FIFO36_DIADIU11", - "BRAM_FIFO36_ADDRARDADDRL4", - "BRAM_LOGIC_OUTS_B8_3", - "BRAM_IMUX21_3", - "BRAM_FIFO36_TSTRDOS9", - "BRAM_LOGIC_OUTS_B8_1", - "BRAM_LH2_2", - "BRAM_LH9_2", - "BRAM_ER1BEG3_1", - "BRAM_UTURN_ADDRARDADDRU4", - "BRAM_IMUX4_UTURN_2", - "BRAM_IMUX39_4", - "BRAM_RAMB18_DIBDI9", - "BRAM_LOGIC_OUTS_B21_2", - "BRAM_WW4B2_4", - "BRAM_SW4A0_1", - "BRAM_FIFO36_DIADIU14", - "BRAM_WW2A1_1", - "BRAM_WW4C0_4", - "BRAM_FIFO36_WEAL2", - "BRAM_BYP3_0", - "BRAM_FIFO18_DIADI13", - "BRAM_ADDRARDADDRU14", - "BRAM_EE2A0_4", - "BRAM_EL1BEG1_2", - "BRAM_CTRL1_1", - "BRAM_FIFO36_DIADIU2", - "BRAM_IMUX2_UTURN_0", - "BRAM_R_IMUX_ADDRBWRADDRU10", - "BRAM_EE4BEG0_0", - "BRAM_LOGIC_OUTS_B4_4", - "BRAM_NE4C3_1", - "BRAM_IMUX29_3", - "BRAM_FIFO36_CASCADEINA", - "BRAM_IMUX6_4", - "BRAM_IMUX47_UTURN_4", - "BRAM_FIFO18_DIBDI9", - "BRAM_LH3_2", - "BRAM_CASCOUT_ADDRARDADDRU12", - "BRAM_FIFO36_TSTWROS2", - "BRAM_NE4C0_1", - "BRAM_R_IMUX_ADDRARDADDRU12", - "BRAM_FIFO18_ADDRARDADDR1", - "BRAM_SE2A3_3", - "BRAM_ADDRARDADDRU13", - "BRAM_FIFO18_DIADI1", - "BRAM_SE4C3_1", - "BRAM_FIFO18_WRCOUNT6", - "BRAM_EL1BEG2_3", - "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "BRAM_IMUX47_2", - "BRAM_FIFO36_DOBDOL2", - "BRAM_FIFO36_DIPADIPU0", - "BRAM_WW4A3_4", - "BRAM_EE4BEG3_2", - "BRAM_LOGIC_OUTS_B17_4", - "BRAM_FAN5_0", - "BRAM_FIFO36_ADDRARDADDRL5", - "BRAM_NW4END1_0", - "BRAM_IMUX37_UTURN_4", - "BRAM_LOGIC_OUTS_B0_4", - "BRAM_IMUX31_UTURN_4", - "BRAM_FIFO36_TSTOFF", - "BRAM_IMUX6_1", - "BRAM_LOGIC_OUTS_B7_0", - "BRAM_EE2BEG1_3", - "BRAM_ADDRBWRADDRL8", - "BRAM_WL1END2_3", - "BRAM_ADDRBWRADDRU6", - "BRAM_IMUX42_0", - "BRAM_EE4B0_2", - "BRAM_FIFO18_ADDRARDADDR12", - "BRAM_LOGIC_OUTS_B5_1", - "BRAM_FIFO36_DOADOU0", - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "BRAM_FIFO18_RSTREGB", - "BRAM_IMUX21_UTURN_1", - "BRAM_IMUX27_0", - "BRAM_SW2A1_3", - "BRAM_PMVBRAM_O_1", - "BRAM_EE2BEG2_4", - "BRAM_WW4C3_0", - "BRAM_NE4BEG0_2", - "BRAM_RAMB18_WEA0", - "BRAM_EE4C1_4", - "BRAM_ADDRBWRADDRU10", - "BRAM_LH11_0", - "BRAM_FIFO18_WRCOUNT2", - "BRAM_FIFO36_DIBDIU14", - "BRAM_IMUX19_UTURN_1", - "BRAM_WW4B2_2", - "BRAM_WW4B3_3", - "BRAM_LOGIC_OUTS_B5_0", - "BRAM_ADDRBWRADDRU14", - "BRAM_SW4A1_1", - "BRAM_UTURN_ADDRBWRADDRL8", - "BRAM_FIFO36_WEAL3", - "BRAM_FIFO36_REGCEAREGCEU", - "BRAM_IMUX42_UTURN_2", - "BRAM_FIFO36_TSTCNT2", - "BRAM_BYP0_2", - "BRAM_FIFO36_ADDRARDADDRL7", - "BRAM_LOGIC_OUTS_B14_1", - "BRAM_LOGIC_OUTS_B14_2", - "BRAM_EE2A2_1", - "BRAM_FIFO36_ADDRBWRADDRU11", - "BRAM_RAMB18_ADDRBWRADDR0", - "BRAM_IMUX21_4", - "BRAM_UTURN_ADDRARDADDRU3", - "BRAM_IMUX38_2", - "BRAM_LH8_1", - "BRAM_WW2A1_4", - "BRAM_LOGIC_OUTS_B19_1", - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "BRAM_ADDRARDADDRU6", - "BRAM_EE4BEG3_3", - "BRAM_WW4END2_0", - "BRAM_WW4C2_2", - "BRAM_R_IMUX_ADDRBWRADDRL6", - "BRAM_RAMB18_ADDRARDADDR10", - "BRAM_LH12_1", - "BRAM_RAMB18_ADDRBWRADDR13", - "BRAM_LOGIC_OUTS_B1_4", - "BRAM_WW4A2_2", - "BRAM_FAN0_0", - "BRAM_IMUX23_4", - "BRAM_SE4C0_4", - "BRAM_WW2A3_3", - "BRAM_ADDRARDADDRU8", - "BRAM_FIFO18_ALMOSTFULL", - "BRAM_IMUX13_2", - "BRAM_RAMB18_DOBDO15", - "BRAM_EE2A1_3", - "BRAM_WR1END0_4", - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU3", - "BRAM_IMUX15_2", - "BRAM_EE4A2_0", - "BRAM_WL1END0_2", - "BRAM_IMUX32_3", - "BRAM_EE4A1_4", - "BRAM_IMUX14_2", - "BRAM_FIFO36_ECCPARITY3", - "BRAM_FIFO18_DIADI7", - "BRAM_LOGIC_OUTS_B5_2", - "BRAM_FAN3_1", - "BRAM_CASCOUT_ADDRARDADDRU4", - "BRAM_IMUX33_3", - "BRAM_WW4END3_2", - "BRAM_R_IMUX_ADDRBWRADDRU5", - "BRAM_FIFO18_ADDRBWRADDR9", - "BRAM_IMUX32_1", - "BRAM_LH10_0", - "BRAM_RAMB18_ADDRBWRADDR3", - "BRAM_WW4B0_3", - "BRAM_PMVBRAM_ODIV2_1", - "BRAM_LOGIC_OUTS_B15_3", - "BRAM_IMUX29_UTURN_1", - "BRAM_LOGIC_OUTS_B0_1", - "BRAM_IMUX45_4", - "BRAM_CASCINBOT_ADDRARDADDRU4", - "BRAM_LOGIC_OUTS_B19_0", - "BRAM_IMUX25_UTURN_1", - "BRAM_FIFO36_DIBDIU9", - "BRAM_RAMB18_DIBDI13", - "BRAM_LH6_1", - "BRAM_R_IMUX_ADDRBWRADDRU4", - "BRAM_RAMB18_DIBDI5", - "BRAM_SW2A0_1", - "BRAM_R_IMUX_ADDRBWRADDRU7", - "BRAM_IMUX2_UTURN_2", - "BRAM_BYP4_3", - "BRAM_FIFO36_WRCOUNT2", - "BRAM_RAMB18_ADDRARDADDR6", - "BRAM_EE4A3_1", - "BRAM_SW2A1_1", - "BRAM_FIFO36_DOBDOU9", - "BRAM_IMUX2_1", - "BRAM_IMUX33_0", - "BRAM_LH7_1", - "BRAM_FIFO18_DIBDI2", - "BRAM_NW4A0_3", - "BRAM_FIFO36_DIADIL11", - "BRAM_SE2A1_3", - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRAM_FIFO36_DOBDOU0", - "BRAM_IMUX13_0", - "BRAM_SE4C2_4", - "BRAM_FIFO36_DBITERR", - "BRAM_FAN3_0", - "BRAM_IMUX40_4", - "BRAM_R_IMUX_ADDRARDADDRU13", - "BRAM_IMUX9_3", - "BRAM_FIFO18_DIPBDIP0", - "BRAM_WW2END3_3", - "BRAM_IMUX31_UTURN_1", - "BRAM_FIFO36_CLKBWRCLKU", - "BRAM_FIFO18_ADDRBWRADDR7", - "BRAM_NE4C1_3", - "BRAM_EE4BEG3_0", - "BRAM_IMUX12_UTURN_0", - "BRAM_FIFO36_TSTOUT4", - "BRAM_IMUX9_UTURN_3", - "BRAM_FIFO18_DIBDI14", - "BRAM_SW4END1_0", - "BRAM_EL1BEG2_0", - "BRAM_IMUX38_0", - "BRAM_IMUX43_UTURN_4", - "BRAM_RAMB18_WRCOUNT11", - "BRAM_LOGIC_OUTS_B23_2", - "BRAM_FIFO18_DOPADOP1", - "BRAM_FAN7_4", - "BRAM_FIFO18_DOADO5", - "BRAM_SW2A3_2", - "BRAM_NW4END3_3", - "BRAM_R_IMUX_ADDRARDADDRU6", - "BRAM_RAMB18_DOBDO11", - "BRAM_FIFO18_DIPADIP0", - "BRAM_FIFO18_DIADI11", - "BRAM_LOGIC_OUTS_B17_3", - "BRAM_IMUX18_0", - "BRAM_NE2A2_1", - "BRAM_FIFO18_RDCOUNT4", - "BRAM_UTURN_ADDRARDADDRL7", - "BRAM_IMUX0_UTURN_3", - "BRAM_RAMB18_WRCOUNT3", - "BRAM_RAMB18_DOPBDOP0", - "BRAM_NE2A2_4", - "BRAM_FIFO36_DIBDIL14", - "BRAM_LOGIC_OUTS_B13_1", - "BRAM_EE4BEG2_2", - "BRAM_LOGIC_OUTS_B11_1", - "BRAM_IMUX12_0", - "BRAM_IMUX1_UTURN_3", - "BRAM_FAN4_4", - "BRAM_FIFO36_DOADOL1", - "BRAM_IMUX10_UTURN_1", - "BRAM_IMUX11_3", - "BRAM_RAMB18_DIBDI10", - "BRAM_EE4A3_0", - "BRAM_SW2A3_3", - "BRAM_SE4BEG3_2", - "BRAM_LH9_3", - "BRAM_FIFO36_TSTRDOS10", - "BRAM_EE4B3_0", - "BRAM_NE4C1_1", - "BRAM_NE2A3_2", - "BRAM_RAMB18_ADDRARDADDR9", - "BRAM_ADDRBWRADDRL14", - "BRAM_EE2BEG0_3", - "BRAM_EE4A0_2", - "BRAM_FIFO36_DOADOU9", - "BRAM_RAMB18_ADDRATIEHIGH0", - "BRAM_RAMB18_DOADO4", - "BRAM_UTURN_ADDRARDADDRU9", - "BRAM_WR1END2_3", - "BRAM_IMUX46_2", - "BRAM_ADDRBWRADDRL10", - "BRAM_UTURN_ADDRBWRADDRU12", - "BRAM_WW4A2_4", - "BRAM_R_IMUX_ADDRARDADDRL8", - "BRAM_RAMB18_DOBDO10", - "BRAM_FIFO36_DOBDOL12", - "BRAM_SW2A2_2", - "BRAM_EL1BEG0_3", - "BRAM_LOGIC_OUTS_B16_4", - "BRAM_NW4END3_0", - "BRAM_IMUX14_4", - "BRAM_CASCINBOT_ADDRARDADDRU6", - "BRAM_SE4C2_1", - "BRAM_IMUX25_3", - "BRAM_IMUX47_4", - "BRAM_WR1END0_0", - "BRAM_NW2A3_1", - "BRAM_FIFO36_ADDRARDADDRU11", - "BRAM_SE4BEG3_0", - "BRAM_ER1BEG2_4", - "BRAM_FIFO36_REGCLKBU", - "BRAM_FIFO18_RSTRAMARSTRAM", - "BRAM_UTURN_ADDRARDADDRL13", - "BRAM_NE2A0_1", - "BRAM_IMUX11_UTURN_1", - "BRAM_FIFO18_WEBWE1", - "BRAM_IMUX16_4", - "BRAM_LOGIC_OUTS_B8_2", - "BRAM_FIFO36_ADDRBWRADDRU2", - "BRAM_IMUX22_UTURN_4", - "BRAM_FIFO36_DIBDIL12", - "BRAM_LOGIC_OUTS_B16_1", - "BRAM_RAMB18_ALMOSTFULL", - "BRAM_WW2A2_4", - "BRAM_R_IMUX_ADDRBWRADDRL14", - "BRAM_IMUX6_2", - "BRAM_LOGIC_OUTS_B16_2", - "BRAM_IMUX32_0", - "BRAM_FIFO36_DIADIL0", - "BRAM_LH10_1", - "BRAM_SW4END3_1", - "BRAM_FIFO36_DIPBDIPL1", - "BRAM_FIFO18_DOADO1", - "BRAM_WW2A1_0", - "BRAM_FIFO36_DOBDOU15", - "BRAM_SW4A2_0", - "BRAM_FIFO36_TSTOUT0", - "BRAM_IMUX14_3", - "BRAM_WW4END3_4", - "BRAM_ER1BEG0_0", - "BRAM_IMUX8_UTURN_1", - "BRAM_FIFO36_DIADIU10", - "BRAM_EE4C0_4", - "BRAM_EE4B3_2", - "BRAM_IMUX29_0", - "BRAM_RAMB18_DIADI3", - "BRAM_IMUX25_1", - "BRAM_FIFO36_RSTREGARSTREGU", - "BRAM_NW2A1_0", - "BRAM_IMUX10_2", - "BRAM_LOGIC_OUTS_B10_2", - "BRAM_LH3_4", - "BRAM_WR1END3_4", - "BRAM_FIFO36_DIBDIU13", - "BRAM_NW4END3_1", - "BRAM_FIFO36_ADDRBWRADDRU8", - "BRAM_WW4A1_3", - "BRAM_WW4B0_1", - "BRAM_IMUX3_UTURN_2", - "BRAM_WW4A0_0", - "BRAM_FIFO36_DIBDIL1", - "BRAM_WW2END1_0", - "BRAM_NW2A1_2", - "BRAM_IMUX17_UTURN_1", - "BRAM_NW4A1_1", - "BRAM_IMUX14_0", - "BRAM_SW4END0_1", - "BRAM_IMUX8_UTURN_3", - "BRAM_IMUX11_2", - "BRAM_WW4B1_4", - "BRAM_FAN7_2", - "BRAM_WW4B3_0", - "BRAM_RAMB18_WRCOUNT1", - "BRAM_LH1_0", - "BRAM_SW4A0_4", - "BRAM_IMUX20_3", - "BRAM_ADDRBWRADDRL6", - "BRAM_FAN1_2", - "BRAM_LOGIC_OUTS_B8_4", - "BRAM_PMVBRAM_ODIV2", - "BRAM_IMUX36_UTURN_3", - "BRAM_FIFO18_RDCOUNT2", - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "BRAM_IMUX11_UTURN_0", - "BRAM_CASCOUT_ADDRBWRADDRU2", - "BRAM_UTURN_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU3", - "BRAM_IMUX10_4", - "BRAM_IMUX7_4", - "BRAM_NE4BEG3_4", - "BRAM_EL1BEG2_1", - "BRAM_RAMB18_DIADI15", - "BRAM_EE2A3_4", - "BRAM_FIFO18_CLKARDCLK", - "BRAM_FIFO36_DOBDOU13", - "BRAM_IMUX34_0", - "BRAM_RAMB18_ADDRBWRADDR9", - "BRAM_FAN3_4", - "BRAM_FIFO36_DOBDOL6", - "BRAM_IMUX26_2", - "BRAM_FIFO18_DIPADIP1", - "BRAM_FIFO18_DOPADOP0", - "BRAM_ADDRARDADDRL3", - "BRAM_RAMB18_DOBDO9", - "BRAM_IMUX1_0", - "BRAM_EE4B3_1", - "BRAM_LOGIC_OUTS_B3_2", - "BRAM_FIFO36_WEAU0", - "BRAM_FIFO36_TSTIN4", - "BRAM_WL1END3_0", - "BRAM_NW4A0_4", - "BRAM_ADDRARDADDRL4", - "BRAM_IMUX34_3", - "BRAM_NW4END0_3", - "BRAM_SW2A0_2", - "BRAM_WW4B0_2", - "BRAM_IMUX39_UTURN_2", - "BRAM_CASCINBOT_ADDRARDADDRU12", - "BRAM_EL1BEG3_4", - "BRAM_FIFO36_DIPBDIPU0", - "BRAM_NE4C0_3", - "BRAM_UTURN_ADDRARDADDRL14", - "BRAM_IMUX2_2", - "BRAM_FIFO36_REGCLKARDRCLKL", - "BRAM_FIFO36_REGCEBL", - "BRAM_IMUX27_UTURN_1", - "BRAM_FIFO36_REGCEBU", - "BRAM_RAMB18_DIBDI3", - "BRAM_LOGIC_OUTS_B6_1", - "BRAM_RAMB18_DIADI14", - "BRAM_FIFO36_RDCOUNT11", - "BRAM_R_IMUX_ADDRARDADDRL0", - "BRAM_FIFO36_ADDRARDADDRL9", - "BRAM_FIFO18_DIPBDIP1", - "BRAM_PMVBRAM_SELECT4", - "BRAM_IMUX3_3", - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "BRAM_WW2END2_1", - "BRAM_NW2A3_2", - "BRAM_CASCOUT_ADDRARDADDRU1", - "BRAM_RAMB18_DIADI4", - "BRAM_FIFO36_DOADOU15", - "BRAM_WW4B2_0", - "BRAM_NE2A1_0", - "BRAM_EE2BEG0_4", - "BRAM_UTURN_ADDRARDADDRL4", - "BRAM_FIFO36_DIADIU0", - "BRAM_IMUX2_0", - "BRAM_IMUX17_2", - "BRAM_ADDRBWRADDRL13", - "BRAM_LOGIC_OUTS_B2_2", - "BRAM_FIFO36_ENARDENL", - "BRAM_LH5_4", - "BRAM_NW2A3_0", - "BRAM_FIFO36_DOADOL3", - "BRAM_LH6_2", - "BRAM_FIFO18_ADDRBWRADDR13", - "BRAM_IMUX44_3", - "BRAM_IMUX10_UTURN_2", - "BRAM_IMUX31_1", - "BRAM_NW4A2_3", - "BRAM_IMUX40_0", - "BRAM_FIFO36_DIADIL14", - "BRAM_WR1END0_3", - "BRAM_FIFO18_RDCOUNT10", - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRAM_IMUX47_UTURN_0", - "BRAM_IMUX43_UTURN_3", - "BRAM_LOGIC_OUTS_B19_4", - "BRAM_WW4C0_3", - "BRAM_LOGIC_OUTS_B14_3", - "BRAM_FIFO36_DOADOL10", - "BRAM_RAMB18_DOADO5", - "BRAM_RAMB18_RSTREGARSTREG", - "BRAM_ER1BEG1_4", - "BRAM_IMUX7_3", - "BRAM_NW4END3_2", - "BRAM_IMUX_R_ADDRBWRADDRL15", - "BRAM_FIFO36_ECCPARITY6", - "BRAM_FIFO18_DOBDO8", - "BRAM_EE4B2_4", - "BRAM_IMUX4_UTURN_3", - "BRAM_NE4BEG1_1", - "BRAM_IMUX41_UTURN_3", - "BRAM_IMUX17_UTURN_4", - "BRAM_FIFO36_DIPADIPU1", - "BRAM_EE4A2_1", - "BRAM_WW2A2_2", - "BRAM_ADDRARDADDRL1", - "BRAM_BLOCK_OUTS_L_B1_2", - "BRAM_WL1END0_4", - "BRAM_EE4B0_3", - "BRAM_RAMB18_DOBDO7", - "BRAM_R_IMUX_ADDRARDADDRL5", - "BRAM_IMUX19_UTURN_0", - "BRAM_LH5_0", - "BRAM_IMUX20_4", - "BRAM_FIFO36_ADDRBWRADDRL4", - "BRAM_EE2BEG2_1", - "BRAM_IMUX21_1", - "BRAM_LH10_2", - "BRAM_RAMB18_DOBDO2", - "BRAM_LOGIC_OUTS_B18_1", - "BRAM_SW4END0_3", - "BRAM_CLK0_4", - "BRAM_FIFO36_WRCOUNT0", - "BRAM_WW4END3_0", - "BRAM_EE4B1_4", - "BRAM_FIFO36_ECCPARITY0", - "BRAM_RAMB18_DOPADOP1", - "BRAM_ADDRARDADDRU11", - "BRAM_MONITOR_P_3", - "BRAM_CASCOUT_ADDRBWRADDRU6", - "BRAM_IMUX37_UTURN_3", - "BRAM_UTURN_ADDRBWRADDRU5", - "BRAM_BLOCK_OUTS_L_B2_3", - "BRAM_WW4B1_1", - "BRAM_FIFO18_DOBDO15", - "BRAM_LOGIC_OUTS_B7_4", - "BRAM_IMUX28_UTURN_1", - "BRAM_WW2END3_2", - "BRAM_SW2A2_4", - "BRAM_BLOCK_OUTS_L_B3_4", - "BRAM_LOGIC_OUTS_B22_1", - "BRAM_IMUX8_2", - "BRAM_IMUX15_1", - "BRAM_LOGIC_OUTS_B6_0", - "BRAM_RAMB18_RDCOUNT9", - "BRAM_CTRL0_0", - "BRAM_SE2A3_2", - "BRAM_FIFO36_ADDRBWRADDRU4", - "BRAM_EL1BEG0_1", - "BRAM_FIFO36_RDCOUNT3", - "BRAM_RAMB18_ADDRBTIEHIGH0", - "BRAM_FIFO36_ADDRBWRADDRL2", - "BRAM_EE2BEG3_2", - "BRAM_IMUX35_UTURN_2", - "BRAM_ADDRBWRADDRL5", - "BRAM_FIFO36_DOADOL8", - "BRAM_RAMB18_ADDRARDADDR5", - "BRAM_FIFO36_DIBDIL15", - "BRAM_NW4A0_2", - "BRAM_FIFO36_WEBWEU7", - "BRAM_R_IMUX_ADDRARDADDRU2", - "BRAM_WW4C1_3", - "BRAM_R_IMUX_ADDRARDADDRL11", - "BRAM_IMUX36_UTURN_4", - "BRAM_FIFO18_DIBDI13", - "BRAM_RAMB18_CLKBWRCLK", - "BRAM_FIFO36_ADDRARDADDRU7", - "BRAM_UTURN_ADDRARDADDRU12", - "BRAM_FIFO36_ECCPARITY4", - "BRAM_R_IMUX_ADDRBWRADDRU12", - "BRAM_LOGIC_OUTS_B4_3", - "BRAM_SE2A1_4", - "BRAM_SE4C3_2", - "BRAM_WW2END1_4", - "BRAM_IMUX44_UTURN_4", - "BRAM_FIFO36_DIBDIU11", - "BRAM_WW4END2_3", - "BRAM_FIFO36_TSTOUT2", - "BRAM_EE4A3_2", - "BRAM_RAMB18_WEBWE5", - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRAM_FIFO36_DIADIL1", - "BRAM_FIFO36_EMPTY", - "BRAM_RAMB18_DIBDI6", - "BRAM_FIFO36_TSTCNT6", - "BRAM_FIFO36_TSTIN2", - "BRAM_FIFO36_DOADOU13", - "BRAM_NE4C3_4", - "BRAM_WW4A1_4", - "BRAM_EE4C2_3", - "BRAM_IMUX23_3", - "BRAM_FIFO36_DIBDIL13", - "BRAM_IMUX37_0", - "BRAM_IMUX10_1", - "BRAM_FIFO36_DIADIL5", - "BRAM_EE4C0_1", - "BRAM_FIFO36_WEBWEL1", - "BRAM_LH2_1", - "BRAM_IMUX5_3", - "BRAM_IMUX47_UTURN_3", - "BRAM_WW2END0_1", - "BRAM_FIFO36_ADDRARDADDRL1", - "BRAM_SE4BEG3_1", - "BRAM_FAN2_2", - "BRAM_RAMB18_DIBDI1", - "BRAM_WR1END1_1", - "BRAM_LOGIC_OUTS_B1_0", - "BRAM_IMUX8_1", - "BRAM_LOGIC_OUTS_B22_4", - "BRAM_FIFO36_DIADIU6", - "BRAM_EE4C2_4", - "BRAM_WW4B2_3", - "BRAM_EL1BEG3_3", - "BRAM_WW4B3_1", - "BRAM_FIFO36_DOADOU2", - "BRAM_EE2A1_2", - "BRAM_WR1END3_3", - "BRAM_FIFO36_TSTRDOS2", - "BRAM_NW4A0_1", - "BRAM_CTRL1_2", - "BRAM_IMUX26_0", - "BRAM_FIFO36_DOBDOL14", - "BRAM_EE4B0_0", - "BRAM_IMUX33_UTURN_1", - "BRAM_IMUX15_3", - "BRAM_R_IMUX_ADDRBWRADDRU0", - "BRAM_SE4BEG1_0", - "BRAM_NE4BEG2_3", - "BRAM_RAMB18_WRCOUNT10", - "BRAM_RAMB18_WEBWE3", - "BRAM_EL1BEG3_2", - "BRAM_LOGIC_OUTS_B17_1", - "BRAM_BYP2_2", - "BRAM_ADDRARDADDRL0", - "BRAM_R_IMUX_ADDRARDADDRU0", - "BRAM_IMUX5_UTURN_0", - "BRAM_FIFO36_DOBDOU4", - "BRAM_FIFO18_FULL", - "BRAM_FIFO36_WRCOUNT10", - "BRAM_IMUX20_0", - "BRAM_EE4A2_3", - "BRAM_IMUX22_UTURN_2", - "BRAM_RAMB18_ADDRBWRADDR12", - "BRAM_ADDRARDADDRU2", - "BRAM_LOGIC_OUTS_B20_1", - "BRAM_IMUX14_UTURN_1", - "BRAM_EE4B3_3", - "BRAM_IMUX8_0", - "BRAM_EE2BEG0_2", - "BRAM_R_IMUX_ADDRBWRADDRL12", - "BRAM_IMUX38_UTURN_3", - "BRAM_NE4BEG2_0", - "BRAM_FIFO18_DOBDO5", - "BRAM_IMUX21_0", - "BRAM_FIFO36_DIADIU5", - "BRAM_R_IMUX_ADDRARDADDRU7", - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRAM_IMUX9_UTURN_0", - "BRAM_FIFO36_DOADOU3", - "BRAM_WW4A3_2", - "BRAM_UTURN_ADDRBWRADDRL0", - "BRAM_R_IMUX_ADDRARDADDRL13", - "BRAM_ER1BEG2_2", - "BRAM_FIFO36_TSTWROS9", - "BRAM_SW4END2_2", - "BRAM_NE2A1_1", - "BRAM_FIFO36_DOBDOU2", - "BRAM_WW4B1_3", - "BRAM_IMUX40_UTURN_0", - "BRAM_IMUX35_1", - "BRAM_CLK1_3", - "BRAM_NW2A2_3", - "BRAM_LOGIC_OUTS_B15_1", - "BRAM_IMUX24_3", - "BRAM_NW4A3_3", - "BRAM_LOGIC_OUTS_B1_2", - "BRAM_IMUX46_4", - "BRAM_EE4C2_0", - "BRAM_BYP3_3", - "BRAM_IMUX24_UTURN_1", - "BRAM_BYP6_1", - "BRAM_UTURN_ADDRBWRADDRL1", - "BRAM_LOGIC_OUTS_B2_1", - "BRAM_IMUX1_4", - "BRAM_FIFO18_DOBDO14", - "BRAM_RAMB18_WRCOUNT8", - "BRAM_IMUX15_UTURN_1", - "BRAM_FIFO36_ADDRBWRADDRL11", - "BRAM_IMUX39_UTURN_4", - "BRAM_FIFO18_DIADI8", - "BRAM_LH7_4", - "BRAM_FIFO36_WEBWEU0", - "BRAM_FIFO36_ADDRARDADDRU1", - "BRAM_FIFO18_DOBDO11", - "BRAM_SE4BEG2_0", - "BRAM_RAMB18_DIPADIP0", - "BRAM_IMUX34_UTURN_3", - "BRAM_EE2BEG2_2", - "BRAM_LOGIC_OUTS_B3_0", - "BRAM_FIFO36_DIADIL13", - "BRAM_ADDRARDADDRL12", - "BRAM_WR1END1_3", - "BRAM_RAMB18_DOADO10", - "BRAM_IMUX23_UTURN_1", - "BRAM_FIFO36_WEAL0", - "BRAM_WW2END2_3", - "BRAM_IMUX47_UTURN_2", - "BRAM_WR1END3_1", - "BRAM_EE4BEG3_4", - "BRAM_IMUX41_0", - "BRAM_WW4A3_0", - "BRAM_IMUX30_2", - "BRAM_FIFO18_REGCEAREGCE", - "BRAM_EE4C1_2", - "BRAM_LH11_1", - "BRAM_IMUX47_UTURN_1", - "BRAM_LOGIC_OUTS_B0_0", - "BRAM_BYP5_0", - "BRAM_FIFO18_REGCLKB", - "BRAM_EE2A0_2", - "BRAM_FIFO36_DIBDIL7", - "BRAM_EE2A2_3", - "BRAM_CASCOUT_ADDRBWRADDRU1", - "BRAM_IMUX15_UTURN_2", - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "BRAM_LOGIC_OUTS_B11_2", - "BRAM_FIFO18_WRCOUNT11", - "BRAM_RAMB18_DIADI5", - "BRAM_WW4A0_3", - "BRAM_LOGIC_OUTS_B19_2", - "BRAM_UTURN_ADDRBWRADDRL14", - "BRAM_IMUX1_UTURN_1", - "BRAM_FIFO36_ADDRARDADDRU6", - "BRAM_FIFO36_WEAU1", - "BRAM_FIFO18_DOADO6", - "BRAM_FIFO36_WEBWEU2", - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRAM_LOGIC_OUTS_B9_1", - "BRAM_FIFO36_DIADIL4", - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "BRAM_SW4END0_0", - "BRAM_CLK0_0", - "BRAM_FIFO36_DOPADOPL0", - "BRAM_RAMB18_ADDRARDADDR7", - "BRAM_R_IMUX_ADDRBWRADDRL11", - "BRAM_FIFO18_ADDRBTIEHIGH1", - "BRAM_CASCINBOT_ADDRARDADDRU5", - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRAM_IMUX16_UTURN_4", - "BRAM_EE4BEG0_1", - "BRAM_FIFO36_RSTREGBL", - "BRAM_EE2BEG1_1", - "BRAM_CTRL1_0", - "BRAM_IMUX4_3", - "BRAM_ADDRBWRADDRU11", - "BRAM_IMUX28_UTURN_4", - "BRAM_IMUX40_UTURN_3", - "BRAM_CASCINBOT_ADDRARDADDRU3", - "BRAM_IMUX12_UTURN_4", - "BRAM_IMUX32_UTURN_2", - "BRAM_CASCOUT_ADDRBWRADDRU14", - "BRAM_RAMB18_DIADI2", - "BRAM_IMUX41_UTURN_2", - "BRAM_NW4END2_0", - "BRAM_IMUX45_UTURN_2", - "BRAM_LOGIC_OUTS_B20_0", - "BRAM_LOGIC_OUTS_B10_1", - "BRAM_SW4A1_3", - "BRAM_FIFO36_WEBWEL6", - "BRAM_LH6_3", - "BRAM_NW4A3_1", - "BRAM_FIFO36_ADDRBWRADDRL0", - "BRAM_IMUX4_UTURN_0", - "BRAM_EE4BEG0_2", - "BRAM_RAMB18_DOBDO3", - "BRAM_FAN4_1", - "BRAM_BYP1_1", - "BRAM_IMUX39_UTURN_0", - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRAM_NW4END0_0", - "BRAM_WW2A2_0", - "BRAM_FIFO36_DOADOL4", - "BRAM_RAMB18_ENARDEN", - "BRAM_FIFO18_WEBWE7", - "BRAM_IMUX17_UTURN_3", - "BRAM_SE4BEG2_4", - "BRAM_FIFO18_ADDRBWRADDR10", - "BRAM_WL1END3_3", - "BRAM_IMUX17_UTURN_0", - "BRAM_FIFO18_ADDRBWRADDR4", - "BRAM_WW2END0_3", - "BRAM_SE2A1_1", - "BRAM_EE4BEG1_3", - "BRAM_IMUX41_1", - "BRAM_EE4C1_1", - "BRAM_ADDRBWRADDRL1", - "BRAM_NW4END2_1", - "BRAM_IMUX32_2", - "BRAM_RAMB18_ADDRBWRADDR1", - "BRAM_FIFO18_DOADO0", - "BRAM_RAMB18_RDCOUNT0", - "BRAM_IMUX16_UTURN_3", - "BRAM_SW4END1_1", - "BRAM_IMUX16_UTURN_2", - "BRAM_FIFO18_WEBWE0", - "BRAM_FIFO36_WEBWEU3", - "BRAM_CASCOUT_ADDRARDADDRU10", - "BRAM_SE4BEG0_3", - "BRAM_SW4A2_4", - "BRAM_ADDRBWRADDRL9", - "BRAM_IMUX21_UTURN_0", - "BRAM_IMUX3_2", - "BRAM_IMUX30_0", - "BRAM_FIFO36_DIADIU1", - "BRAM_SW2A2_1", - "BRAM_R_IMUX_ADDRARDADDRU4", - "BRAM_WW4END1_3", - "BRAM_CLK1_2", - "BRAM_NE4C1_0", - "BRAM_RAMB18_ALMOSTEMPTY", - "BRAM_WW2A3_2", - "BRAM_EE4B2_3", - "BRAM_IMUX19_0", - "BRAM_IMUX31_2", - "BRAM_FIFO36_DOBDOL11", - "BRAM_LOGIC_OUTS_B17_0", - "BRAM_FIFO36_ADDRBWRADDRL10", - "BRAM_IMUX12_3", - "BRAM_SE4BEG1_2", - "BRAM_FIFO36_DOADOL11", - "BRAM_LH7_0", - "BRAM_IMUX20_2", - "BRAM_IMUX14_UTURN_0", - "BRAM_FIFO36_TSTWROS8", - "BRAM_LOGIC_OUTS_B4_1", - "BRAM_ADDRBWRADDRL4", - "BRAM_FIFO36_DOADOL15", - "BRAM_FIFO36_DIPBDIPU1", - "BRAM_IMUX26_3", - "BRAM_BLOCK_OUTS_L_B0_0", - "BRAM_WW4END2_4", - "BRAM_IMUX39_UTURN_3", - "BRAM_IMUX2_UTURN_3", - "BRAM_MONITOR_N_2", - "BRAM_UTURN_ADDRARDADDRU13", - "BRAM_FIFO18_DIBDI6", - "BRAM_BYP7_4", - "BRAM_IMUX6_UTURN_3", - "BRAM_IMUX34_4", - "BRAM_SW4END1_2", - "BRAM_FIFO18_DIBDI8", - "BRAM_FIFO36_TSTRDOS0", - "BRAM_FIFO36_TSTWROS3", - "BRAM_IMUX41_UTURN_1", - "BRAM_FIFO36_REGCEAREGCEL", - "BRAM_EE4A0_3", - "BRAM_IMUX5_UTURN_1", - "BRAM_FIFO18_RDCOUNT9", - "BRAM_BLOCK_OUTS_L_B0_1", - "BRAM_WL1END2_1", - "BRAM_LOGIC_OUTS_B23_1", - "BRAM_WW4A1_0", - "BRAM_FIFO36_ADDRBWRADDRU13", - "BRAM_IMUX0_2", - "BRAM_FAN6_0", - "BRAM_WW4END1_1", - "BRAM_IMUX47_0", - "BRAM_IMUX31_UTURN_3", - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRAM_IMUX0_1", - "BRAM_ER1BEG1_0", - "BRAM_NW4END1_3", - "BRAM_FIFO36_ADDRARDADDRL2", - "BRAM_EE4BEG2_0", - "BRAM_FIFO36_WEBWEU4", - "BRAM_CLK1_4", - "BRAM_UTURN_ADDRBWRADDRL5", - "BRAM_EE4BEG1_0", - "BRAM_IMUX12_4", - "BRAM_EE4BEG1_4", - "BRAM_EL1BEG3_1", - "BRAM_IMUX11_UTURN_4", - "BRAM_IMUX0_UTURN_2", - "BRAM_FIFO36_TSTRDCNTOFF", - "BRAM_MONITOR_N_3", - "BRAM_IMUX45_UTURN_3", - "BRAM_NE2A1_3", - "BRAM_FIFO18_DIADI14", - "BRAM_SE2A3_1", - "BRAM_UTURN_ADDRARDADDRU10", - "BRAM_IMUX41_UTURN_0", - "BRAM_FIFO36_DIADIL3", - "BRAM_SE2A3_0", - "BRAM_IMUX14_UTURN_4", - "BRAM_SE4BEG0_1", - "BRAM_RAMB18_ADDRBWRADDR2", - "BRAM_EE4C2_2", - "BRAM_EL1BEG0_4", - "BRAM_NW2A2_0", - "BRAM_FIFO36_INJECTSBITERR", - "BRAM_IMUX32_UTURN_0", - "BRAM_CASCINBOT_ADDRARDADDRU9", - "BRAM_FIFO36_DIBDIU12", - "BRAM_IMUX47_3", - "BRAM_CTRL0_4", - "BRAM_RAMB18_DOBDO6", - "BRAM_FIFO18_RDCOUNT6", - "BRAM_IMUX23_1", - "BRAM_IMUX31_4", - "BRAM_FIFO36_REGCLKARDRCLKU", - "BRAM_IMUX28_3", - "BRAM_WW4C0_2", - "BRAM_SW4A0_0", - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRAM_FIFO36_ADDRARDADDRU12", - "BRAM_ADDRBWRADDRL2", - "BRAM_IMUX26_4", - "BRAM_LH3_0", - "BRAM_RAMB18_DIBDI8", - "BRAM_IMUX5_0", - "BRAM_CASCINBOT_ADDRBWRADDRU10", - "BRAM_FIFO36_ADDRBWRADDRU10", - "BRAM_FIFO18_DOADO4", - "BRAM_EE4BEG0_3", - "BRAM_EL1BEG1_4", - "BRAM_FIFO36_ADDRARDADDRU0", - "BRAM_RAMB18_DOBDO1", - "BRAM_RAMB18_WEA1", - "BRAM_WW2A0_1", - "BRAM_FIFO36_DIPADIPL1", - "BRAM_SE4BEG3_4", - "BRAM_EL1BEG3_0", - "BRAM_IMUX39_3", - "BRAM_FAN5_3", - "BRAM_EL1BEG2_2", - "BRAM_FIFO18_ADDRBWRADDR2", - "BRAM_SE4BEG1_3", - "BRAM_IMUX9_2", - "BRAM_WW4B0_4", - "BRAM_IMUX28_UTURN_2", - "BRAM_IMUX23_2", - "BRAM_MONITOR_P_0", - "BRAM_WW4B1_2", - "BRAM_LOGIC_OUTS_B10_0", - "BRAM_FIFO18_RDCOUNT11", - "BRAM_FIFO36_DIADIU13", - "BRAM_IMUX13_UTURN_0", - "BRAM_FIFO36_DOBDOL13", - "BRAM_IMUX28_0", - "BRAM_RAMB18_DIBDI11", - "BRAM_FIFO36_WEBWEL4", - "BRAM_NE2A1_2", - "BRAM_FIFO36_DIADIL8", - "BRAM_FIFO36_TSTWROS10", - "BRAM_NE2A3_1", - "BRAM_FIFO36_TSTRDOS4", - "BRAM_RAMB18_FULL", - "BRAM_IMUX26_UTURN_4", - "BRAM_FIFO18_DIBDI7", - "BRAM_IMUX1_2", - "BRAM_EE4C3_0", - "BRAM_IMUX34_1", - "BRAM_IMUX2_4", - "BRAM_FIFO36_DOBDOL0", - "BRAM_FIFO18_DIBDI0", - "BRAM_FIFO18_ADDRARDADDR0", - "BRAM_ADDRBWRADDRU2", - "BRAM_IMUX33_UTURN_2", - "BRAM_IMUX5_UTURN_2", - "BRAM_CASCOUT_ADDRBWRADDRU11", - "BRAM_IMUX41_UTURN_4", - "BRAM_FIFO36_DOBDOU3", - "BRAM_IMUX42_1", - "BRAM_IMUX21_UTURN_3", - "BRAM_LH9_4", - "BRAM_FIFO36_TSTCNT12", - "BRAM_FIFO36_TSTRDOS1", - "BRAM_IMUX43_UTURN_0", - "BRAM_UTURN_ADDRARDADDRU5", - "BRAM_BYP2_0", - "BRAM_LOGIC_OUTS_B6_3", - "BRAM_FIFO36_DOBDOU1", - "BRAM_IMUX45_2", - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRAM_WW4C1_1", - "BRAM_FIFO36_ADDRARDADDRL14", - "BRAM_FIFO36_ADDRBWRADDRL1", - "BRAM_SW2A2_0", - "BRAM_FIFO18_DIADI4", - "BRAM_FIFO36_WEBWEU6", - "BRAM_FIFO18_ADDRARDADDR3", - "BRAM_FIFO36_DOPBDOPL1", - "BRAM_ADDRARDADDRL8", - "BRAM_NW2A2_4", - "BRAM_IMUX35_0", - "BRAM_NW2A0_1", - "BRAM_SE4C1_3", - "BRAM_FIFO18_WRCOUNT3", - "BRAM_FIFO18_REGCLKARDRCLK", - "BRAM_EE2BEG3_4", - "BRAM_WW4B1_0", - "BRAM_FIFO36_TSTCNT3", - "BRAM_UTURN_ADDRBWRADDRL2", - "BRAM_WW4C2_0", - "BRAM_RAMB18_ADDRBWRADDR10", - "BRAM_CASCOUT_ADDRBWRADDRU7", - "BRAM_FIFO36_WRCOUNT8", - "BRAM_WW4END3_3", - "BRAM_UTURN_ADDRBWRADDRU14", - "BRAM_ADDRBWRADDRU12", - "BRAM_WW4C3_1", - "BRAM_IMUX12_UTURN_3", - "BRAM_NE4C2_3", - "BRAM_RAMB18_DIADI1", - "BRAM_WW2END0_2", - "BRAM_WR1END2_2", - "BRAM_IMUX46_0", - "BRAM_FIFO18_DIBDI15", - "BRAM_IMUX45_UTURN_1", - "BRAM_FIFO36_CASCADEOUTB", - "BRAM_IMUX15_UTURN_0", - "BRAM_FIFO36_TSTWROS11", - "BRAM_FIFO36_RDCOUNT12", - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRAM_WW4C1_0", - "BRAM_ER1BEG0_2", - "BRAM_FIFO36_WEAL1", - "BRAM_IMUX28_4", - "BRAM_IMUX22_UTURN_1", - "BRAM_SE4C1_0", - "BRAM_NW4A2_1", - "BRAM_FIFO36_RDCOUNT10", - "BRAM_WL1END0_3", - "BRAM_SE4C3_4", - "BRAM_IMUX11_4", - "BRAM_FIFO18_DOADO7", - "BRAM_CASCOUT_ADDRARDADDRU13", - "BRAM_EE4BEG2_4", - "BRAM_EE2BEG0_0", - "BRAM_RAMB18_DOBDO5", - "BRAM_IMUX7_UTURN_3", - "BRAM_EE4BEG2_3", - "BRAM_EE2A2_0", - "BRAM_IMUX19_4", - "BRAM_SW4A1_0", - "BRAM_FIFO36_CASCADEOUTA_1", - "BRAM_RAMB18_DOBDO0", - "BRAM_IMUX31_UTURN_0", - "BRAM_IMUX29_UTURN_3", - "BRAM_R_IMUX_ADDRBWRADDRU1", - "BRAM_IMUX44_UTURN_2", - "BRAM_IMUX17_4", - "BRAM_IMUX44_1", - "BRAM_WW4C1_2", - "BRAM_SW4END0_2", - "BRAM_EE4C3_3", - "BRAM_RAMB18_DOADO8", - "BRAM_LH12_3", - "BRAM_NW2A0_2", - "BRAM_CTRL1_3", - "BRAM_SW4A2_3", - "BRAM_IMUX17_3", - "BRAM_FIFO36_DOADOL14", - "BRAM_IMUX12_1", - "BRAM_SE4BEG2_1", - "BRAM_FAN6_4", - "BRAM_IMUX7_2", - "BRAM_LOGIC_OUTS_B13_0", - "BRAM_IMUX45_3", - "BRAM_FIFO36_DIADIU3", - "BRAM_UTURN_ADDRBWRADDRU8", - "BRAM_FIFO36_DIBDIU8", - "BRAM_FIFO36_ADDRARDADDRL15", - "BRAM_IMUX8_UTURN_0", - "BRAM_FIFO36_DOBDOU14", - "BRAM_FIFO36_DOBDOL9", - "BRAM_IMUX12_2", - "BRAM_SE4C0_0", - "BRAM_R_IMUX_ADDRARDADDRL9", - "BRAM_IMUX18_UTURN_3", - "BRAM_RAMB18_RDCOUNT4", - "BRAM_WL1END1_4", - "BRAM_NE4C1_4", - "BRAM_FIFO18_ENBWREN", - "BRAM_IMUX35_UTURN_3", - "BRAM_WW2END3_4", - "BRAM_RAMB18_WRCOUNT2", - "BRAM_BYP2_3", - "BRAM_EE4BEG2_1", - "BRAM_PMVBRAM_O", - "BRAM_NE4BEG1_4", - "BRAM_NE2A2_3", - "BRAM_EE4C0_0", - "BRAM_IMUX21_UTURN_4", - "BRAM_IMUX26_1", - "BRAM_ADDRBWRADDRL11", - "BRAM_NE4C3_3", - "BRAM_EE2A3_1", - "BRAM_FIFO36_ADDRARDADDRL10", - "BRAM_FIFO18_DOBDO9", - "BRAM_FIFO36_TSTWROS4", - "BRAM_SE2A2_0", - "BRAM_FIFO36_ENARDENU", - "BRAM_SE4BEG0_4", - "BRAM_IMUX17_UTURN_2", - "BRAM_UTURN_ADDRARDADDRU2", - "BRAM_FIFO18_WEBWE3", - "BRAM_FIFO36_DOADOL12", - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRAM_FIFO36_DOADOU11", - "BRAM_EE4A3_3", - "BRAM_IMUX39_UTURN_1", - "BRAM_IMUX31_3", - "BRAM_FIFO36_DIBDIL8", - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRAM_NW4END0_4", - "BRAM_RAMB18_DOBDO8", - "BRAM_FIFO18_WEBWE6", - "BRAM_FIFO36_DOBDOL7", - "BRAM_ADDRBWRADDRU1", - "BRAM_ER1BEG2_1", - "BRAM_IMUX10_UTURN_4", - "BRAM_EE2A0_3", - "BRAM_NW2A1_1", - "BRAM_PMVBRAM_SELECT2", - "BRAM_WW4END2_2", - "BRAM_RAMB18_DOADO7", - "BRAM_FIFO36_TSTCNT7", - "BRAM_WW4END0_0", - "BRAM_FIFO36_TSTFLAGIN", - "BRAM_IMUX38_1", - "BRAM_IMUX39_1", - "BRAM_RAMB18_WRCOUNT0", - "BRAM_LOGIC_OUTS_B7_2", - "BRAM_UTURN_ADDRBWRADDRU1", - "BRAM_FIFO36_DOBDOU6", - "BRAM_RAMB18_ADDRARDADDR8", - "BRAM_IMUX42_3", - "BRAM_SW4A3_3", - "BRAM_FIFO36_TSTRDOS12", - "BRAM_SE4BEG0_2", - "BRAM_RAMB18_DIBDI15", - "BRAM_LOGIC_OUTS_B2_4", - "BRAM_LH3_3", - "BRAM_IMUX11_UTURN_3", - "BRAM_WW4END1_0", - "BRAM_CASCOUT_ADDRBWRADDRU5", - "BRAM_NE4BEG2_1", - "BRAM_RAMB18_DOPBDOP1", - "BRAM_FIFO36_ADDRARDADDRU8", - "BRAM_SW4A0_2", - "BRAM_FIFO36_WRCOUNT4", - "BRAM_WL1END1_0", - "BRAM_IMUX9_UTURN_4", - "BRAM_UTURN_ADDRBWRADDRL13", - "BRAM_FIFO18_DOBDO12", - "BRAM_IMUX14_1", - "BRAM_IMUX11_0", - "BRAM_IMUX8_UTURN_2", - "BRAM_SE4BEG1_1", - "BRAM_WL1END1_1", - "BRAM_FIFO18_DOADO9", - "BRAM_FIFO18_DOBDO6", - "BRAM_ER1BEG3_3", - "BRAM_FIFO36_ADDRARDADDRL13", - "BRAM_LOGIC_OUTS_B3_4", - "BRAM_IMUX9_1", - "BRAM_WW4A1_1", - "BRAM_WL1END0_0", - "BRAM_FIFO18_WEA2", - "BRAM_IMUX46_UTURN_1", - "BRAM_BLOCK_OUTS_L_B3_2", - "BRAM_WW4A2_1", - "BRAM_FIFO36_DOADOU1", - "BRAM_ADDRARDADDRL14", - "BRAM_FIFO36_TSTWROS7", - "BRAM_FIFO36_ADDRBWRADDRU3", - "BRAM_R_IMUX_ADDRBWRADDRU6", - "BRAM_FIFO18_DOADO13", - "BRAM_FIFO18_WEA0", - "BRAM_BLOCK_OUTS_L_B2_2", - "BRAM_BLOCK_OUTS_L_B3_1", - "BRAM_WW4C1_4", - "BRAM_IMUX40_UTURN_4", - "BRAM_FIFO18_DIADI2", - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRAM_RAMB18_DOPADOP0", - "BRAM_FIFO36_DIADIL10", - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRAM_LOGIC_OUTS_B20_4", - "BRAM_IMUX44_UTURN_0", - "BRAM_IMUX25_0", - "BRAM_BYP6_0", - "BRAM_IMUX22_4", - "BRAM_IMUX42_4", - "BRAM_IMUX19_1", - "BRAM_FIFO18_DOBDO4", - "BRAM_EE2A0_0", - "BRAM_R_IMUX_ADDRBWRADDRU8", - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRAM_IMUX35_3", - "BRAM_BYP5_4", - "BRAM_IMUX9_0", - "BRAM_IMUX47_1", - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "BRAM_FIFO36_DIBDIL5", - "BRAM_IMUX3_4", - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRAM_LH6_0", - "BRAM_IMUX12_UTURN_2", - "BRAM_IMUX44_UTURN_3", - "BRAM_IMUX9_4", - "BRAM_IMUX33_UTURN_4", - "BRAM_FIFO18_DIBDI3", - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRAM_EE2A1_4", - "BRAM_IMUX19_UTURN_4", - "BRAM_ADDRARDADDRL11", - "BRAM_IMUX2_UTURN_4", - "BRAM_RAMB18_WEBWE7", - "BRAM_IMUX36_4", - "BRAM_FIFO36_DOBDOL5", - "BRAM_ADDRBWRADDRU13", - "BRAM_IMUX1_UTURN_2", - "BRAM_IMUX1_1", - "BRAM_FIFO18_ADDRARDADDR2", - "BRAM_FIFO36_ADDRARDADDRU2", - "BRAM_UTURN_ADDRARDADDRL15", - "BRAM_ER1BEG3_2", - "BRAM_UTURN_ADDRBWRADDRL11", - "BRAM_R_IMUX_ADDRARDADDRU10", - "BRAM_SW4END2_3", - "BRAM_RAMB18_DIADI11", - "BRAM_LOGIC_OUTS_B12_2", - "BRAM_LH4_2", - "BRAM_RAMB18_DOADO13", - "BRAM_IMUX42_UTURN_3", - "BRAM_EE4A3_4", - "BRAM_FIFO36_ADDRARDADDRU3", - "BRAM_IMUX45_UTURN_0", - "BRAM_FIFO18_RSTRAMB", - "BRAM_FIFO18_DIBDI12", - "BRAM_IMUX13_UTURN_4", - "BRAM_LOGIC_OUTS_B0_2", - "BRAM_ADDRBWRADDRU7", - "BRAM_IMUX19_UTURN_2", - "BRAM_FIFO36_DOBDOU10", - "BRAM_IMUX35_2", - "BRAM_LOGIC_OUTS_B11_0", - "BRAM_WW2A2_1", - "BRAM_CASCOUT_ADDRARDADDRU5", - "BRAM_IMUX24_0", - "BRAM_LH8_4", - "BRAM_ADDRBWRADDRL7", - "BRAM_FIFO36_RSTRAMBL", - "BRAM_RAMB18_ADDRARDADDR4", - "BRAM_WW2END2_0", - "BRAM_IMUX40_2", - "BRAM_FIFO36_WEAU3", - "BRAM_SW4A1_4", - "BRAM_NW4A0_0", - "BRAM_NE4BEG0_4", - "BRAM_CTRL0_1", - "BRAM_LH12_4", - "BRAM_FIFO36_DIADIL15", - "BRAM_UTURN_ADDRBWRADDRU4", - "BRAM_ADDRARDADDRL5", - "BRAM_IMUX25_UTURN_3", - "BRAM_IMUX18_3", - "BRAM_WR1END1_0", - "BRAM_NE2A3_4", - "BRAM_LOGIC_OUTS_B22_2", - "BRAM_FIFO36_ALMOSTFULL", - "BRAM_RAMB18_ADDRARDADDR13", - "BRAM_FAN1_0", - "BRAM_FIFO18_WRCOUNT1", - "BRAM_NE4C0_0", - "BRAM_FIFO36_ADDRARDADDRU14", - "BRAM_RAMB18_DIPBDIP0", - "BRAM_EE4A2_2", - "BRAM_IMUX46_UTURN_0", - "BRAM_IMUX18_UTURN_2", - "BRAM_FIFO36_TSTCNT4", - "BRAM_LOGIC_OUTS_B13_4", - "BRAM_FIFO36_DIBDIU0", - "BRAM_FIFO36_DIBDIU2", - "BRAM_RAMB18_DIBDI12", - "BRAM_FIFO18_ADDRATIEHIGH0", - "BRAM_IMUX27_1", - "BRAM_R_IMUX_ADDRBWRADDRL4", - "BRAM_NW4A1_2", - "BRAM_FIFO18_ENARDEN", - "BRAM_FIFO36_WRCOUNT7", - "BRAM_IMUX27_3", - "BRAM_LH8_3", - "BRAM_UTURN_ADDRBWRADDRL10", - "BRAM_BLOCK_OUTS_L_B1_1", - "BRAM_ER1BEG0_1", - "BRAM_BYP4_4", - "BRAM_BLOCK_OUTS_L_B0_2", - "BRAM_IMUX20_UTURN_2", - "BRAM_FIFO18_DOPBDOP0", - "BRAM_WW4C3_3", - "BRAM_SW4A2_2", - "BRAM_FIFO36_TSTWROS5", - "BRAM_LOGIC_OUTS_B23_4", - "BRAM_IMUX6_0", - "BRAM_LH8_2", - "BRAM_RAMB18_DIADI6", - "BRAM_IMUX5_1", - "BRAM_IMUX27_UTURN_3", - "BRAM_SE4C0_1", - "BRAM_FAN7_1", - "BRAM_IMUX39_0", - "BRAM_BYP5_1", - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRAM_LH1_3", - "BRAM_UTURN_ADDRARDADDRL12", - "BRAM_LOGIC_OUTS_B12_1", - "BRAM_IMUX27_UTURN_2", - "BRAM_FIFO36_TSTRDOS3", - "BRAM_WW4A3_3", - "BRAM_FIFO36_ADDRBWRADDRU12", - "BRAM_WL1END3_2", - "BRAM_NE4C1_2", - "BRAM_IMUX46_UTURN_3", - "BRAM_EE4C0_3", - "BRAM_IMUX36_UTURN_0", - "BRAM_FIFO36_DIBDIL6", - "BRAM_FIFO36_ALMOSTEMPTY", - "BRAM_SW2A1_2", - "BRAM_RAMB18_WRCOUNT4", - "BRAM_LOGIC_OUTS_B1_1", - "BRAM_NW4A2_4", - "BRAM_UTURN_ADDRARDADDRL2", - "BRAM_FIFO36_ADDRBWRADDRU9", - "BRAM_EE4A0_1", - "BRAM_IMUX22_UTURN_0", - "BRAM_R_IMUX_ADDRBWRADDRL10", - "BRAM_FIFO18_DIBDI11", - "BRAM_WW4END0_1", - "BRAM_LOGIC_OUTS_B9_0", - "BRAM_UTURN_ADDRARDADDRL9", - "BRAM_FIFO36_DOPBDOPL0", - "BRAM_MONITOR_N_1", - "BRAM_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU13", - "BRAM_FIFO36_DOBDOU12", - "BRAM_FIFO36_DIBDIL10", - "BRAM_RAMB18_WEA2", - "BRAM_BLOCK_OUTS_L_B3_3", - "BRAM_WW4END0_2", - "BRAM_ADDRBWRADDRU4", - "BRAM_FAN3_3", - "BRAM_UTURN_ADDRBWRADDRL9", - "BRAM_IMUX16_UTURN_0", - "BRAM_RAMB18_WEA3", - "BRAM_FIFO36_DOBDOL8", - "BRAM_FIFO36_DOADOL0", - "BRAM_IMUX7_UTURN_1", - "BRAM_IMUX11_1", - "BRAM_R_IMUX_ADDRBWRADDRU9", - "BRAM_BYP1_4", - "BRAM_IMUX29_UTURN_2", - "BRAM_RAMB18_WEBWE4", - "BRAM_FIFO36_WEBWEL3", - "BRAM_FIFO18_RDCOUNT8", - "BRAM_FIFO18_DOBDO13", - "BRAM_RAMB18_RDCOUNT8", - "BRAM_EE4B0_4", - "BRAM_FIFO18_ADDRBWRADDR3", - "BRAM_LOGIC_OUTS_B23_3", - "BRAM_FIFO36_WRCOUNT11", - "BRAM_FAN1_4", - "BRAM_FAN6_3", - "BRAM_EE4A1_3", - "BRAM_BLOCK_OUTS_L_B1_3", - "BRAM_LOGIC_OUTS_B1_3", - "BRAM_LOGIC_OUTS_B7_3", - "BRAM_R_IMUX_ADDRBWRADDRL2", - "BRAM_SE2A1_0", - "BRAM_IMUX6_UTURN_1", - "BRAM_FAN7_3", - "BRAM_FIFO36_DOADOL2", - "BRAM_NE2A3_0", - "BRAM_NE4BEG2_4", - "BRAM_NE2A3_3", - "BRAM_FAN2_4", - "BRAM_UTURN_ADDRBWRADDRU6", - "BRAM_IMUX8_UTURN_4", - "BRAM_IMUX3_1", - "BRAM_ADDRARDADDRL6", - "BRAM_WL1END2_2", - "BRAM_FIFO36_DOPBDOPU1", - "BRAM_SE2A0_2", - "BRAM_SW4A1_2", - "BRAM_BLOCK_OUTS_L_B0_4", - "BRAM_IMUX16_UTURN_1", - "BRAM_FIFO36_RDCOUNT4", - "BRAM_NW2A2_1", - "BRAM_IMUX38_UTURN_2", - "BRAM_R_IMUX_ADDRBWRADDRL7", - "BRAM_IMUX21_UTURN_2", - "BRAM_LH1_4", - "BRAM_IMUX24_2", - "BRAM_R_IMUX_ADDRBWRADDRL5", - "BRAM_FIFO18_DOADO15", - "BRAM_FAN4_2", - "BRAM_RAMB18_ADDRARDADDR11", - "BRAM_LOGIC_OUTS_B23_0", - "BRAM_WW2A2_3", - "BRAM_IMUX43_3", - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "BRAM_LOGIC_OUTS_B9_2", - "BRAM_SW4A3_4", - "BRAM_LOGIC_OUTS_B18_4", - "BRAM_FIFO36_DIADIU4", - "BRAM_EE2A1_0", - "BRAM_CASCOUT_ADDRARDADDRU8", - "BRAM_FIFO36_DIBDIL9", - "BRAM_IMUX0_3", - "BRAM_FIFO18_ADDRARDADDR13", - "BRAM_UTURN_ADDRBWRADDRU7", - "BRAM_WW4C3_2", - "BRAM_FIFO36_ADDRBWRADDRU7", - "BRAM_RAMB18_ENBWREN", - "BRAM_IMUX15_UTURN_3", - "BRAM_FIFO36_TSTOUT3", - "BRAM_IMUX10_0", - "BRAM_FAN6_1", - "BRAM_FIFO36_DIADIL6", - "BRAM_SE4C0_3", - "BRAM_WW4C2_3", - "BRAM_FIFO36_CASCADEOUTA", - "BRAM_IMUX1_3", - "BRAM_IMUX10_UTURN_0", - "BRAM_FIFO36_ECCPARITY7", - "BRAM_IMUX26_UTURN_3", - "BRAM_FIFO36_TSTCNT0", - "BRAM_UTURN_ADDRBWRADDRL15", - "BRAM_WR1END3_0", - "BRAM_IMUX1_UTURN_0", - "BRAM_RAMB18_DOBDO12", - "BRAM_NW2A0_3", - "BRAM_EE2BEG3_3", - "BRAM_PMVBRAM_ODIV4", - "BRAM_IMUX5_UTURN_3", - "BRAM_FIFO18_WRCOUNT9", - "BRAM_IMUX10_3", - "BRAM_FIFO36_DIBDIU4", - "BRAM_FIFO36_TSTWROS1", - "BRAM_BYP6_4", - "BRAM_SW4A0_3", - "BRAM_CASCINBOT_ADDRARDADDRU0", - "BRAM_LH3_1", - "BRAM_UTURN_ADDRARDADDRL1", - "BRAM_IMUX33_4", - "BRAM_WL1END3_4", - "BRAM_NW4END1_1", - "BRAM_R_IMUX_ADDRBWRADDRL9", - "BRAM_R_IMUX_ADDRBWRADDRU2", - "BRAM_PMVBRAM_SELECT1", - "BRAM_IMUX13_UTURN_3", - "BRAM_NE4C2_0", - "BRAM_FIFO18_RDCOUNT1", - "BRAM_IMUX30_1", - "BRAM_IMUX4_4", - "BRAM_WW4C3_4", - "BRAM_RAMB18_CLKARDCLK", - "BRAM_IMUX_R_ADDRARDADDRL15", - "BRAM_IMUX43_UTURN_1", - "BRAM_IMUX23_UTURN_4", - "BRAM_BYP0_4", - "BRAM_FAN1_3", - "BRAM_UTURN_ADDRBWRADDRU11", - "BRAM_SE2A2_4", - "BRAM_FIFO36_RSTREGARSTREGL", - "BRAM_IMUX25_UTURN_0", - "BRAM_FIFO18_ADDRBTIEHIGH0", - "BRAM_SE4C2_3", - "BRAM_FAN6_2", - "BRAM_UTURN_ADDRBWRADDRU9", - "BRAM_FIFO36_DOPBDOPU0", - "BRAM_FIFO18_ADDRATIEHIGH1", - "BRAM_WW4END1_4", - "BRAM_IMUX0_4", - "BRAM_IMUX18_UTURN_1", - "BRAM_FIFO36_ADDRBWRADDRL8", - "BRAM_FAN5_2", - "BRAM_WL1END3_1", - "BRAM_ADDRARDADDRL10", - "BRAM_FIFO36_CLKARDCLKL", - "BRAM_NE4BEG1_0", - "BRAM_R_IMUX_ADDRBWRADDRL1", - "BRAM_FIFO36_RDCOUNT0", - "BRAM_CASCOUT_ADDRBWRADDRU0", - "BRAM_RAMB18_DIADI8", - "BRAM_IMUX23_UTURN_3", - "BRAM_UTURN_ADDRARDADDRU8", - "BRAM_LOGIC_OUTS_B14_0", - "BRAM_IMUX39_2", - "BRAM_IMUX41_3", - "BRAM_FIFO18_DOBDO2", - "BRAM_BYP4_2", - "BRAM_IMUX18_UTURN_0", - "BRAM_IMUX30_3", - "BRAM_RAMB18_REGCLKARDRCLK", - "BRAM_FIFO36_ADDRBWRADDRU1", - "BRAM_RAMB18_ADDRARDADDR0", - "BRAM_FIFO36_CASCADEINB", - "BRAM_FIFO18_ADDRBWRADDR1", - "BRAM_FIFO36_TSTRDOS11", - "BRAM_BYP0_0", - "BRAM_IMUX17_0", - "BRAM_IMUX20_UTURN_3", - "BRAM_EE4B3_4", - "BRAM_FIFO36_CLKBWRCLKL", - "BRAM_LOGIC_OUTS_B17_2", - "BRAM_FIFO18_RDCOUNT3", - "BRAM_IMUX16_3", - "BRAM_FAN5_1", - "BRAM_LOGIC_OUTS_B0_3", - "BRAM_ADDRBWRADDRU9", - "BRAM_NW4END2_2", - "BRAM_FIFO36_ADDRBWRADDRU0", - "BRAM_FIFO36_DIADIU7", - "BRAM_EE4B1_0", - "BRAM_FIFO36_RDCOUNT1", - "BRAM_RAMB18_DOBDO4", - "BRAM_BYP1_2", - "BRAM_FIFO18_DIADI0", - "BRAM_BYP2_1", - "BRAM_FIFO36_DOADOU4", - "BRAM_RAMB18_DOADO3", - "BRAM_CLK0_2", - "BRAM_FIFO18_WEBWE5", - "BRAM_IMUX16_2", - "BRAM_ADDRARDADDRU1", - "BRAM_FIFO36_RSTRAMARSTRAMU" - ], - "sites": [ - { - "prefix": "RAMB18", - "y_coord": 19, - "type": "FIFO18E1", - "site_pins": { - "DIBDI13": "BRAM_FIFO18_DIBDI13", - "DO17": "BRAM_FIFO18_DOBDO1", - "DIBDI5": "BRAM_FIFO18_DIBDI5", - "DIBDI15": "BRAM_FIFO18_DIBDI15", - "DIADI9": "BRAM_FIFO18_DIADI9", - "DO8": "BRAM_FIFO18_DOADO8", - "DO26": "BRAM_FIFO18_DOBDO10", - "RDCLK": "BRAM_FIFO18_CLKARDCLK", - "REGCLKB": "BRAM_FIFO18_REGCLKB", - "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", - "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", - "DO15": "BRAM_FIFO18_DOADO15", - "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", - "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", - "DIADI10": "BRAM_FIFO18_DIADI10", - "REGCEB": "BRAM_FIFO18_REGCEB", - "WRCOUNT11": "BRAM_FIFO18_WRCOUNT11", - "DIADI1": "BRAM_FIFO18_DIADI1", - "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", - "WEBWE7": "BRAM_FIFO18_WEBWE7", - "WEA2": "BRAM_FIFO18_WEA2", - "DIADI3": "BRAM_FIFO18_DIADI3", - "WRCOUNT6": "BRAM_FIFO18_WRCOUNT6", - "WEBWE3": "BRAM_FIFO18_WEBWE3", - "WEBWE5": "BRAM_FIFO18_WEBWE5", - "DIBDI8": "BRAM_FIFO18_DIBDI8", - "DO9": "BRAM_FIFO18_DOADO9", - "WEBWE4": "BRAM_FIFO18_WEBWE4", - "DO4": "BRAM_FIFO18_DOADO4", - "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", - "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", - "WRCOUNT0": "BRAM_FIFO18_WRCOUNT0", - "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", - "DO10": "BRAM_FIFO18_DOADO10", - "DIADI0": "BRAM_FIFO18_DIADI0", - "DIBDI10": "BRAM_FIFO18_DIBDI10", - "DIADI15": "BRAM_FIFO18_DIADI15", - "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", - "WEA0": "BRAM_FIFO18_WEA0", - "DO11": "BRAM_FIFO18_DOADO11", - "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", - "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", - "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", - "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", - "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", - "WRCOUNT5": "BRAM_FIFO18_WRCOUNT5", - "DO6": "BRAM_FIFO18_DOADO6", - "WEBWE6": "BRAM_FIFO18_WEBWE6", - "DOP2": "BRAM_FIFO18_DOPBDOP0", - "DO16": "BRAM_FIFO18_DOBDO0", - "WRCOUNT2": "BRAM_FIFO18_WRCOUNT2", - "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", - "DO19": "BRAM_FIFO18_DOBDO3", - "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", - "DO23": "BRAM_FIFO18_DOBDO7", - "WRCOUNT1": "BRAM_FIFO18_WRCOUNT1", - "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", - "DIPADIP0": "BRAM_FIFO18_DIPADIP0", - "WRCOUNT8": "BRAM_FIFO18_WRCOUNT8", - "DO7": "BRAM_FIFO18_DOADO7", - "DO22": "BRAM_FIFO18_DOBDO6", - "DO30": "BRAM_FIFO18_DOBDO14", - "ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0", - "DIADI4": "BRAM_FIFO18_DIADI4", - "WRERR": "BRAM_FIFO18_WRERR", - "DIBDI2": "BRAM_FIFO18_DIBDI2", - "DIBDI11": "BRAM_FIFO18_DIBDI11", - "DO2": "BRAM_FIFO18_DOADO2", - "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", - "DIPADIP1": "BRAM_FIFO18_DIPADIP1", - "WRCLK": "BRAM_FIFO18_CLKBWRCLK", - "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", - "DO3": "BRAM_FIFO18_DOADO3", - "DO27": "BRAM_FIFO18_DOBDO11", - "DOP1": "BRAM_FIFO18_DOPADOP1", - "WRCOUNT3": "BRAM_FIFO18_WRCOUNT3", - "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", - "WRCOUNT7": "BRAM_FIFO18_WRCOUNT7", - "RST": "BRAM_FIFO18_RSTRAMARSTRAM", - "WEA1": "BRAM_FIFO18_WEA1", - "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", - "DIBDI9": "BRAM_FIFO18_DIBDI9", - "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", - "DO0": "BRAM_FIFO18_DOADO0", - "DOP3": "BRAM_FIFO18_DOPBDOP1", - "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", - "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", - "DIADI8": "BRAM_FIFO18_DIADI8", - "WRCOUNT9": "BRAM_FIFO18_WRCOUNT9", - "DO25": "BRAM_FIFO18_DOBDO9", - "DO28": "BRAM_FIFO18_DOBDO12", - "RDERR": "BRAM_FIFO18_RDERR", - "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", - "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", - "RDEN": "BRAM_FIFO18_ENARDEN", - "RSTREGB": "BRAM_FIFO18_RSTREGB", - "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", - "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", - "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", - "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", - "FULL": "BRAM_FIFO18_FULL", - "DIBDI6": "BRAM_FIFO18_DIBDI6", - "WEBWE0": "BRAM_FIFO18_WEBWE0", - "DO20": "BRAM_FIFO18_DOBDO4", - "DO1": "BRAM_FIFO18_DOADO1", - "DO5": "BRAM_FIFO18_DOADO5", - "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", - "DIADI11": "BRAM_FIFO18_DIADI11", - "DIADI2": "BRAM_FIFO18_DIADI2", - "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", - "WRCOUNT4": "BRAM_FIFO18_WRCOUNT4", - "WREN": "BRAM_FIFO18_ENBWREN", - "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", - "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", - "DIADI5": "BRAM_FIFO18_DIADI5", - "WEA3": "BRAM_FIFO18_WEA3", - "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", - "DIBDI1": "BRAM_FIFO18_DIBDI1", - "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", - "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", - "DO12": "BRAM_FIFO18_DOADO12", - "EMPTY": "BRAM_FIFO18_EMPTY", - "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", - "DIADI13": "BRAM_FIFO18_DIADI13", - "WEBWE2": "BRAM_FIFO18_WEBWE2", - "DO14": "BRAM_FIFO18_DOADO14", - "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", - "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", - "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", - "WEBWE1": "BRAM_FIFO18_WEBWE1", - "DIBDI4": "BRAM_FIFO18_DIBDI4", - "DOP0": "BRAM_FIFO18_DOPADOP0", - "DIBDI12": "BRAM_FIFO18_DIBDI12", - "DO21": "BRAM_FIFO18_DOBDO5", - "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", - "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", - "DIADI12": "BRAM_FIFO18_DIADI12", - "DO29": "BRAM_FIFO18_DOBDO13", - "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", - "REGCE": "BRAM_FIFO18_REGCEAREGCE", - "DO18": "BRAM_FIFO18_DOBDO2", - "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12", - "DO31": "BRAM_FIFO18_DOBDO15", - "DIBDI7": "BRAM_FIFO18_DIBDI7", - "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", - "WRCOUNT10": "BRAM_FIFO18_WRCOUNT10", - "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", - "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", - "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", - "DIBDI14": "BRAM_FIFO18_DIBDI14", - "DIBDI0": "BRAM_FIFO18_DIBDI0", - "DO24": "BRAM_FIFO18_DOBDO8", - "DIADI14": "BRAM_FIFO18_DIADI14", - "DIADI7": "BRAM_FIFO18_DIADI7", - "DIBDI3": "BRAM_FIFO18_DIBDI3", - "RSTRAMB": "BRAM_FIFO18_RSTRAMB", - "DO13": "BRAM_FIFO18_DOADO13", - "DIADI6": "BRAM_FIFO18_DIADI6" - }, - "x_coord": 0, - "name": "X0Y19" - }, - { - "prefix": "RAMB18", - "y_coord": 20, - "type": "RAMB18E1", - "site_pins": { - "DOBDO7": "BRAM_RAMB18_DOBDO7", - "DIBDI13": "BRAM_RAMB18_DIBDI13", - "DIBDI5": "BRAM_RAMB18_DIBDI5", - "DIBDI15": "BRAM_RAMB18_DIBDI15", - "DIADI9": "BRAM_RAMB18_DIADI9", - "DOBDO2": "BRAM_RAMB18_DOBDO2", - "DOADO8": "BRAM_RAMB18_DOADO8", - "DOPADOP0": "BRAM_RAMB18_DOPADOP0", - "REGCLKB": "BRAM_RAMB18_REGCLKB", - "RDCOUNT6": "BRAM_RAMB18_RDCOUNT6", - "DOADO15": "BRAM_RAMB18_DOADO15", - "DIBDI11": "BRAM_RAMB18_DIBDI11", - "ADDRBWRADDR3": "BRAM_RAMB18_ADDRBWRADDR3", - "DOBDO11": "BRAM_RAMB18_DOBDO11", - "ADDRARDADDR5": "BRAM_RAMB18_ADDRARDADDR5", - "DIADI10": "BRAM_RAMB18_DIADI10", - "DOBDO10": "BRAM_RAMB18_DOBDO10", - "WRCOUNT11": "BRAM_RAMB18_WRCOUNT11", - "ENARDEN": "BRAM_RAMB18_ENARDEN", - "DIADI1": "BRAM_RAMB18_DIADI1", - "DOPBDOP0": "BRAM_RAMB18_DOPBDOP0", - "REGCLKARDRCLK": "BRAM_RAMB18_REGCLKARDRCLK", - "RDCOUNT0": "BRAM_RAMB18_RDCOUNT0", - "WEBWE7": "BRAM_RAMB18_WEBWE7", - "WEA2": "BRAM_RAMB18_WEA2", - "DIADI3": "BRAM_RAMB18_DIADI3", - "WRCOUNT6": "BRAM_RAMB18_WRCOUNT6", - "WEBWE5": "BRAM_RAMB18_WEBWE5", - "DIBDI8": "BRAM_RAMB18_DIBDI8", - "WEBWE4": "BRAM_RAMB18_WEBWE4", - "DOBDO8": "BRAM_RAMB18_DOBDO8", - "ADDRBWRADDR8": "BRAM_RAMB18_ADDRBWRADDR8", - "ADDRARDADDR6": "BRAM_RAMB18_ADDRARDADDR6", - "ENBWREN": "BRAM_RAMB18_ENBWREN", - "RDCOUNT2": "BRAM_RAMB18_RDCOUNT2", - "RDCOUNT8": "BRAM_RAMB18_RDCOUNT8", - "DIADI0": "BRAM_RAMB18_DIADI0", - "DIBDI10": "BRAM_RAMB18_DIBDI10", - "DOADO1": "BRAM_RAMB18_DOADO1", - "WEA0": "BRAM_RAMB18_WEA0", - "DOADO0": "BRAM_RAMB18_DOADO0", - "RDCOUNT3": "BRAM_RAMB18_RDCOUNT3", - "RDCOUNT7": "BRAM_RAMB18_RDCOUNT7", - "ALMOSTEMPTY": "BRAM_RAMB18_ALMOSTEMPTY", - "ADDRBWRADDR9": "BRAM_RAMB18_ADDRBWRADDR9", - "ADDRARDADDR11": "BRAM_RAMB18_ADDRARDADDR11", - "WRCOUNT5": "BRAM_RAMB18_WRCOUNT5", - "WEBWE6": "BRAM_RAMB18_WEBWE6", - "DOBDO14": "BRAM_RAMB18_DOBDO14", - "DOADO12": "BRAM_RAMB18_DOADO12", - "WRCOUNT2": "BRAM_RAMB18_WRCOUNT2", - "ADDRBWRADDR5": "BRAM_RAMB18_ADDRBWRADDR5", - "CLKBWRCLK": "BRAM_RAMB18_CLKBWRCLK", - "RDCOUNT5": "BRAM_RAMB18_RDCOUNT5", - "DOBDO3": "BRAM_RAMB18_DOBDO3", - "WRCOUNT1": "BRAM_RAMB18_WRCOUNT1", - "RDCOUNT9": "BRAM_RAMB18_RDCOUNT9", - "DIPADIP0": "BRAM_RAMB18_DIPADIP0", - "WRCOUNT8": "BRAM_RAMB18_WRCOUNT8", - "DOBDO12": "BRAM_RAMB18_DOBDO12", - "ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0", - "DOADO6": "BRAM_RAMB18_DOADO6", - "DIADI4": "BRAM_RAMB18_DIADI4", - "WRERR": "BRAM_RAMB18_WRERR", - "DOADO4": "BRAM_RAMB18_DOADO4", - "DIBDI2": "BRAM_RAMB18_DIBDI2", - "REGCEB": "BRAM_RAMB18_REGCEB", - "DIPADIP1": "BRAM_RAMB18_DIPADIP1", - "WEBWE3": "BRAM_RAMB18_WEBWE3", - "DOBDO1": "BRAM_RAMB18_DOBDO1", - "RSTRAMARSTRAM": "BRAM_RAMB18_RSTRAMARSTRAM", - "RSTREGARSTREG": "BRAM_RAMB18_RSTREGARSTREG", - "WRCOUNT3": "BRAM_RAMB18_WRCOUNT3", - "ADDRBWRADDR10": "BRAM_RAMB18_ADDRBWRADDR10", - "WRCOUNT7": "BRAM_RAMB18_WRCOUNT7", - "WEA1": "BRAM_RAMB18_WEA1", - "ADDRARDADDR8": "BRAM_RAMB18_ADDRARDADDR8", - "DIBDI9": "BRAM_RAMB18_DIBDI9", - "ADDRARDADDR4": "BRAM_RAMB18_ADDRARDADDR4", - "DOADO11": "BRAM_RAMB18_DOADO11", - "ADDRBWRADDR0": "BRAM_RAMB18_ADDRBWRADDR0", - "WRCOUNT0": "BRAM_RAMB18_WRCOUNT0", - "ADDRBWRADDR13": "BRAM_RAMB18_ADDRBWRADDR13", - "ADDRBWRADDR11": "BRAM_RAMB18_ADDRBWRADDR11", - "DIADI8": "BRAM_RAMB18_DIADI8", - "WRCOUNT9": "BRAM_RAMB18_WRCOUNT9", - "RDERR": "BRAM_RAMB18_RDERR", - "ADDRBTIEHIGH1": "BRAM_RAMB18_ADDRBTIEHIGH1", - "ADDRBWRADDR2": "BRAM_RAMB18_ADDRBWRADDR2", - "ADDRARDADDR1": "BRAM_RAMB18_ADDRARDADDR1", - "RSTREGB": "BRAM_RAMB18_RSTREGB", - "DOADO3": "BRAM_RAMB18_DOADO3", - "ADDRARDADDR7": "BRAM_RAMB18_ADDRARDADDR7", - "DOADO14": "BRAM_RAMB18_DOADO14", - "RDCOUNT11": "BRAM_RAMB18_RDCOUNT11", - "DOBDO4": "BRAM_RAMB18_DOBDO4", - "ADDRATIEHIGH1": "BRAM_RAMB18_ADDRATIEHIGH1", - "FULL": "BRAM_RAMB18_FULL", - "DOADO7": "BRAM_RAMB18_DOADO7", - "DIBDI6": "BRAM_RAMB18_DIBDI6", - "WEBWE0": "BRAM_RAMB18_WEBWE0", - "CLKARDCLK": "BRAM_RAMB18_CLKARDCLK", - "DIADI11": "BRAM_RAMB18_DIADI11", - "DIADI15": "BRAM_RAMB18_DIADI15", - "DIADI2": "BRAM_RAMB18_DIADI2", - "ADDRBWRADDR12": "BRAM_RAMB18_ADDRBWRADDR12", - "WRCOUNT4": "BRAM_RAMB18_WRCOUNT4", - "ADDRBWRADDR7": "BRAM_RAMB18_ADDRBWRADDR7", - "ADDRBTIEHIGH0": "BRAM_RAMB18_ADDRBTIEHIGH0", - "DIADI5": "BRAM_RAMB18_DIADI5", - "WEA3": "BRAM_RAMB18_WEA3", - "ADDRARDADDR10": "BRAM_RAMB18_ADDRARDADDR10", - "DOBDO13": "BRAM_RAMB18_DOBDO13", - "DOBDO6": "BRAM_RAMB18_DOBDO6", - "DOBDO5": "BRAM_RAMB18_DOBDO5", - "DIBDI1": "BRAM_RAMB18_DIBDI1", - "DIPBDIP0": "BRAM_RAMB18_DIPBDIP0", - "ADDRBWRADDR6": "BRAM_RAMB18_ADDRBWRADDR6", - "DOADO13": "BRAM_RAMB18_DOADO13", - "EMPTY": "BRAM_RAMB18_EMPTY", - "RDCOUNT1": "BRAM_RAMB18_RDCOUNT1", - "DIADI13": "BRAM_RAMB18_DIADI13", - "WEBWE2": "BRAM_RAMB18_WEBWE2", - "ALMOSTFULL": "BRAM_RAMB18_ALMOSTFULL", - "ADDRARDADDR13": "BRAM_RAMB18_ADDRARDADDR13", - "DOPADOP1": "BRAM_RAMB18_DOPADOP1", - "RDCOUNT4": "BRAM_RAMB18_RDCOUNT4", - "DIPBDIP1": "BRAM_RAMB18_DIPBDIP1", - "WEBWE1": "BRAM_RAMB18_WEBWE1", - "DOADO9": "BRAM_RAMB18_DOADO9", - "DOPBDOP1": "BRAM_RAMB18_DOPBDOP1", - "DIBDI12": "BRAM_RAMB18_DIBDI12", - "ADDRARDADDR9": "BRAM_RAMB18_ADDRARDADDR9", - "DOADO2": "BRAM_RAMB18_DOADO2", - "REGCEAREGCE": "BRAM_RAMB18_REGCEAREGCE", - "DOADO10": "BRAM_RAMB18_DOADO10", - "DIADI12": "BRAM_RAMB18_DIADI12", - "ADDRARDADDR3": "BRAM_RAMB18_ADDRARDADDR3", - "RDCOUNT10": "BRAM_RAMB18_RDCOUNT10", - "DIBDI4": "BRAM_RAMB18_DIBDI4", - "DOBDO0": "BRAM_RAMB18_DOBDO0", - "DIBDI7": "BRAM_RAMB18_DIBDI7", - "ADDRBWRADDR1": "BRAM_RAMB18_ADDRBWRADDR1", - "WRCOUNT10": "BRAM_RAMB18_WRCOUNT10", - "ADDRBWRADDR4": "BRAM_RAMB18_ADDRBWRADDR4", - "DOADO5": "BRAM_RAMB18_DOADO5", - "ADDRATIEHIGH0": "BRAM_RAMB18_ADDRATIEHIGH0", - "ADDRARDADDR2": "BRAM_RAMB18_ADDRARDADDR2", - "DIBDI14": "BRAM_RAMB18_DIBDI14", - "DIBDI0": "BRAM_RAMB18_DIBDI0", - "DIADI14": "BRAM_RAMB18_DIADI14", - "DIADI7": "BRAM_RAMB18_DIADI7", - "DOBDO15": "BRAM_RAMB18_DOBDO15", - "DIBDI3": "BRAM_RAMB18_DIBDI3", - "DOBDO9": "BRAM_RAMB18_DOBDO9", - "RSTRAMB": "BRAM_RAMB18_RSTRAMB", - "ADDRARDADDR12": "BRAM_RAMB18_ADDRARDADDR12", - "DIADI6": "BRAM_RAMB18_DIADI6" - }, - "x_coord": 0, - "name": "X0Y20" - }, - { - "prefix": "RAMB36", - "y_coord": 0, - "type": "RAMBFIFO36E1", - "site_pins": { - "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", - "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", - "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", - "WEBWEL3": "BRAM_FIFO36_WEBWEL3", - "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", - "TSTWROS0": "BRAM_FIFO36_TSTWROS0", - "DIBDI17": "BRAM_FIFO36_DIBDIU8", - "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", - "DOBDO2": "BRAM_FIFO36_DOBDOL1", - "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", - "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", - "DIADI25": "BRAM_FIFO36_DIADIU12", - "DOADO20": "BRAM_FIFO36_DOADOL10", - "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", - "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", - "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", - "DOADO15": "BRAM_FIFO36_DOADOU7", - "DIBDI26": "BRAM_FIFO36_DIBDIL13", - "DBITERR": "BRAM_FIFO36_DBITERR", - "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", - "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", - "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", - "TSTWROS8": "BRAM_FIFO36_TSTWROS8", - "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", - "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", - "DOBDO31": "BRAM_FIFO36_DOBDOU15", - "DIADI20": "BRAM_FIFO36_DIADIL10", - "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", - "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", - "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", - "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", - "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", - "WEAL3": "BRAM_FIFO36_WEAL3", - "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", - "DOBDO17": "BRAM_FIFO36_DOBDOU8", - "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", - "DIADI3": "BRAM_FIFO36_DIADIU1", - "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", - "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", - "TSTOUT3": "BRAM_FIFO36_TSTOUT3", - "DOBDO24": "BRAM_FIFO36_DOBDOL12", - "DOADO12": "BRAM_FIFO36_DOADOL6", - "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", - "DIBDI27": "BRAM_FIFO36_DIBDIU13", - "TSTWROS9": "BRAM_FIFO36_TSTWROS9", - "ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", - "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", - "DIADI0": "BRAM_FIFO36_DIADIL0", - "DIBDI10": "BRAM_FIFO36_DIBDIL5", - "DIADI15": "BRAM_FIFO36_DIADIU7", - "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", - "DOBDO6": "BRAM_FIFO36_DOBDOL3", - "DOADO0": "BRAM_FIFO36_DOADOL0", - "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", - "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", - "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", - "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", - "DIADI28": "BRAM_FIFO36_DIADIL14", - "DOBDO25": "BRAM_FIFO36_DOBDOU12", - "DOADO22": "BRAM_FIFO36_DOADOL11", - "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", - "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", - "TSTWROS4": "BRAM_FIFO36_TSTWROS4", - "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", - "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", - "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", - "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", - "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", - "WEBWEU3": "BRAM_FIFO36_WEBWEU3", - "DIBDI3": "BRAM_FIFO36_DIBDIU1", - "WEBWEU1": "BRAM_FIFO36_WEBWEU1", - "WRCOUNT8": "BRAM_FIFO36_WRCOUNT8", - "DOADO24": "BRAM_FIFO36_DOADOL12", - "DOBDO12": "BRAM_FIFO36_DOBDOL6", - "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", - "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", - "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", - "WRERR": "BRAM_FIFO36_WRERR", - "DOADO31": "BRAM_FIFO36_DOADOU15", - "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", - "DIBDI11": "BRAM_FIFO36_DIBDIU5", - "TSTCNT7": "BRAM_FIFO36_TSTCNT7", - "REGCEBU": "BRAM_FIFO36_REGCEBU", - "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", - "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", - "TSTCNT10": "BRAM_FIFO36_TSTCNT10", - "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", - "TSTIN1": "BRAM_FIFO36_TSTIN1", - "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", - "TSTWROS3": "BRAM_FIFO36_TSTWROS3", - "TSTIN3": "BRAM_FIFO36_TSTIN3", - "TSTCNT0": "BRAM_FIFO36_TSTCNT0", - "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", - "DIBDI9": "BRAM_FIFO36_DIBDIU4", - "WEBWEL1": "BRAM_FIFO36_WEBWEL1", - "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", - "WEBWEL7": "BRAM_FIFO36_WEBWEL7", - "WEBWEU2": "BRAM_FIFO36_WEBWEU2", - "DOBDO11": "BRAM_FIFO36_DOBDOU5", - "TSTIN2": "BRAM_FIFO36_TSTIN2", - "TSTCNT2": "BRAM_FIFO36_TSTCNT2", - "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", - "TSTOUT2": "BRAM_FIFO36_TSTOUT2", - "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", - "WRCOUNT9": "BRAM_FIFO36_WRCOUNT9", - "DIADI31": "BRAM_FIFO36_DIADIU15", - "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", - "DIBDI2": "BRAM_FIFO36_DIBDIL1", - "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", - "DOADO3": "BRAM_FIFO36_DOADOU1", - "DOADO14": "BRAM_FIFO36_DOADOL7", - "DIBDI28": "BRAM_FIFO36_DIBDIL14", - "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", - "DOADO13": "BRAM_FIFO36_DOADOU6", - "FULL": "BRAM_FIFO36_FULL", - "DOADO7": "BRAM_FIFO36_DOADOU3", - "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", - "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", - "DIADI11": "BRAM_FIFO36_DIADIU5", - "TSTWROS2": "BRAM_FIFO36_TSTWROS2", - "ENBWRENU": "BRAM_FIFO36_ENBWRENU", - "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", - "DOBDO16": "BRAM_FIFO36_DOBDOL8", - "ENBWRENL": "BRAM_FIFO36_ENBWRENL", - "WEBWEL4": "BRAM_FIFO36_WEBWEL4", - "REGCLKBL": "BRAM_FIFO36_REGCLKBL", - "SBITERR": "BRAM_FIFO36_SBITERR", - "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", - "DIADI5": "BRAM_FIFO36_DIADIU2", - "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", - "DOBDO13": "BRAM_FIFO36_DOBDOU6", - "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", - "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", - "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", - "WEAL0": "BRAM_FIFO36_WEAL0", - "TSTCNT12": "BRAM_FIFO36_TSTCNT12", - "DIBDI1": "BRAM_FIFO36_DIBDIU0", - "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", - "DOBDO23": "BRAM_FIFO36_DOBDOU11", - "DIBDI29": "BRAM_FIFO36_DIBDIU14", - "TSTCNT3": "BRAM_FIFO36_TSTCNT3", - "DIBDI31": "BRAM_FIFO36_DIBDIU15", - "DIBDI22": "BRAM_FIFO36_DIBDIL11", - "TSTCNT8": "BRAM_FIFO36_TSTCNT8", - "DOADO16": "BRAM_FIFO36_DOADOL8", - "DIADI13": "BRAM_FIFO36_DIADIU6", - "DIADI19": "BRAM_FIFO36_DIADIU9", - "DOADO23": "BRAM_FIFO36_DOADOU11", - "ENARDENL": "BRAM_FIFO36_ENARDENL", - "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", - "DOBDO1": "BRAM_FIFO36_DOBDOU0", - "DIBDI16": "BRAM_FIFO36_DIBDIL8", - "DOADO9": "BRAM_FIFO36_DOADOU4", - "WEBWEL2": "BRAM_FIFO36_WEBWEL2", - "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", - "DOADO28": "BRAM_FIFO36_DOADOL14", - "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", - "RSTREGBU": "BRAM_FIFO36_RSTREGBU", - "TSTCNT9": "BRAM_FIFO36_TSTCNT9", - "DIADI12": "BRAM_FIFO36_DIADIL6", - "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", - "WEBWEU4": "BRAM_FIFO36_WEBWEU4", - "DOBDO18": "BRAM_FIFO36_DOBDOL9", - "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", - "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", - "RSTREGBL": "BRAM_FIFO36_RSTREGBL", - "TSTWROS11": "BRAM_FIFO36_TSTWROS11", - "DOBDO26": "BRAM_FIFO36_DOBDOL13", - "DOADO19": "BRAM_FIFO36_DOADOU9", - "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", - "DOADO5": "BRAM_FIFO36_DOADOU2", - "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", - "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", - "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", - "DIBDI14": "BRAM_FIFO36_DIBDIL7", - "DIBDI12": "BRAM_FIFO36_DIBDIL6", - "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", - "TSTWROS7": "BRAM_FIFO36_TSTWROS7", - "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", - "DOBDO19": "BRAM_FIFO36_DOBDOU9", - "DIBDI23": "BRAM_FIFO36_DIBDIU11", - "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", - "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", - "DIADI6": "BRAM_FIFO36_DIADIL3", - "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", - "DOBDO7": "BRAM_FIFO36_DOBDOU3", - "DIBDI13": "BRAM_FIFO36_DIBDIU6", - "ENARDENU": "BRAM_FIFO36_ENARDENU", - "DIBDI15": "BRAM_FIFO36_DIBDIU7", - "DIADI9": "BRAM_FIFO36_DIADIU4", - "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", - "DOBDO0": "BRAM_FIFO36_DOBDOL0", - "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", - "WEAL1": "BRAM_FIFO36_WEAL1", - "DOADO8": "BRAM_FIFO36_DOADOL4", - "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", - "DOBDO22": "BRAM_FIFO36_DOBDOL11", - "REGCLKBU": "BRAM_FIFO36_REGCLKBU", - "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", - "WEBWEL0": "BRAM_FIFO36_WEBWEL0", - "DIADI2": "BRAM_FIFO36_DIADIL1", - "TSTOUT0": "BRAM_FIFO36_TSTOUT0", - "DOBDO29": "BRAM_FIFO36_DOBDOU14", - "TSTOFF": "BRAM_FIFO36_TSTOFF", - "DOBDO28": "BRAM_FIFO36_DOBDOL14", - "DOBDO20": "BRAM_FIFO36_DOBDOL10", - "DOADO11": "BRAM_FIFO36_DOADOU5", - "DIADI10": "BRAM_FIFO36_DIADIL5", - "DIBDI30": "BRAM_FIFO36_DIBDIL15", - "DIADI1": "BRAM_FIFO36_DIADIU0", - "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", - "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", - "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", - "DIADI17": "BRAM_FIFO36_DIADIU8", - "REGCEBL": "BRAM_FIFO36_REGCEBL", - "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", - "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", - "DIBDI20": "BRAM_FIFO36_DIBDIL10", - "WEBWEL5": "BRAM_FIFO36_WEBWEL5", - "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", - "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", - "TSTCNT1": "BRAM_FIFO36_TSTCNT1", - "TSTWROS5": "BRAM_FIFO36_TSTWROS5", - "DIBDI8": "BRAM_FIFO36_DIBDIL4", - "DOADO18": "BRAM_FIFO36_DOADOL9", - "DOBDO8": "BRAM_FIFO36_DOBDOL4", - "TSTWROS12": "BRAM_FIFO36_TSTWROS12", - "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", - "DIBDI21": "BRAM_FIFO36_DIBDIU10", - "DOADO1": "BRAM_FIFO36_DOADOU0", - "TSTWROS1": "BRAM_FIFO36_TSTWROS1", - "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", - "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", - "CASCADEINA": "BRAM_FIFO36_CASCADEINB", - "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTA", - "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", - "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", - "WEAL2": "BRAM_FIFO36_WEAL2", - "DOBDO14": "BRAM_FIFO36_DOBDOL7", - "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", - "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", - "DOBDO30": "BRAM_FIFO36_DOBDOL15", - "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", - "DOBDO3": "BRAM_FIFO36_DOBDOU1", - "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", - "DOADO27": "BRAM_FIFO36_DOADOU13", - "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", - "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", - "DIADI21": "BRAM_FIFO36_DIADIU10", - "DOBDO9": "BRAM_FIFO36_DOBDOU4", - "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", - "WEAU2": "BRAM_FIFO36_WEAU2", - "DIBDI19": "BRAM_FIFO36_DIBDIU9", - "RDERR": "BRAM_FIFO36_RDERR", - "DIBDI7": "BRAM_FIFO36_DIBDIU3", - "DIADI26": "BRAM_FIFO36_DIADIL13", - "DOADO6": "BRAM_FIFO36_DOADOL3", - "DIADI18": "BRAM_FIFO36_DIADIL9", - "DIADI4": "BRAM_FIFO36_DIADIL2", - "DOADO4": "BRAM_FIFO36_DOADOL2", - "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", - "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "TSTCNT11": "BRAM_FIFO36_TSTCNT11", - "DIADI29": "BRAM_FIFO36_DIADIU14", - "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", - "DIADI23": "BRAM_FIFO36_DIADIU11", - "DIADI22": "BRAM_FIFO36_DIADIL11", - "DIBDI25": "BRAM_FIFO36_DIBDIU12", - "DIBDI18": "BRAM_FIFO36_DIBDIL9", - "TSTOUT4": "BRAM_FIFO36_TSTOUT4", - "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", - "WRCOUNT7": "BRAM_FIFO36_WRCOUNT7", - "DIBDI5": "BRAM_FIFO36_DIBDIU2", - "DIADI27": "BRAM_FIFO36_DIADIU13", - "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", - "DOADO29": "BRAM_FIFO36_DOADOU14", - "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", - "WEBWEU7": "BRAM_FIFO36_WEBWEU7", - "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", - "DIADI8": "BRAM_FIFO36_DIADIL4", - "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", - "WEAU1": "BRAM_FIFO36_WEAU1", - "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", - "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", - "TSTOUT1": "BRAM_FIFO36_TSTOUT1", - "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", - "DOBDO4": "BRAM_FIFO36_DOBDOL2", - "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", - "DOBDO27": "BRAM_FIFO36_DOBDOU13", - "WEAU3": "BRAM_FIFO36_WEAU3", - "DOADO25": "BRAM_FIFO36_DOADOU12", - "DIBDI6": "BRAM_FIFO36_DIBDIL3", - "DIBDI0": "BRAM_FIFO36_DIBDIL0", - "DOADO30": "BRAM_FIFO36_DOADOL15", - "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", - "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", - "DOADO21": "BRAM_FIFO36_DOADOU10", - "TSTIN4": "BRAM_FIFO36_TSTIN4", - "DOADO26": "BRAM_FIFO36_DOADOL13", - "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", - "WEBWEU5": "BRAM_FIFO36_WEBWEU5", - "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", - "TSTCNT6": "BRAM_FIFO36_TSTCNT6", - "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", - "WEBWEU0": "BRAM_FIFO36_WEBWEU0", - "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", - "TSTWROS6": "BRAM_FIFO36_TSTWROS6", - "DIBDI24": "BRAM_FIFO36_DIBDIL12", - "TSTCNT4": "BRAM_FIFO36_TSTCNT4", - "DOADO17": "BRAM_FIFO36_DOADOU8", - "DOBDO5": "BRAM_FIFO36_DOBDOU2", - "DIADI30": "BRAM_FIFO36_DIADIL15", - "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", - "WEAU0": "BRAM_FIFO36_WEAU0", - "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", - "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", - "CASCADEINB": "BRAM_FIFO36_CASCADEINA", - "EMPTY": "BRAM_FIFO36_EMPTY", - "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", - "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", - "DOBDO10": "BRAM_FIFO36_DOBDOL5", - "DIADI24": "BRAM_FIFO36_DIADIL12", - "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", - "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", - "DIBDI4": "BRAM_FIFO36_DIBDIL2", - "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", - "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", - "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", - "DOADO2": "BRAM_FIFO36_DOADOL1", - "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", - "DOADO10": "BRAM_FIFO36_DOADOL5", - "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", - "DIADI16": "BRAM_FIFO36_DIADIL8", - "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", - "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", - "WEBWEL6": "BRAM_FIFO36_WEBWEL6", - "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", - "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", - "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", - "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", - "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", - "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", - "WEBWEU6": "BRAM_FIFO36_WEBWEU6", - "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", - "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", - "DOBDO21": "BRAM_FIFO36_DOBDOU10", - "TSTCNT5": "BRAM_FIFO36_TSTCNT5", - "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", - "DIADI14": "BRAM_FIFO36_DIADIL7", - "DIADI7": "BRAM_FIFO36_DIADIU3", - "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", - "DOBDO15": "BRAM_FIFO36_DOBDOU7", - "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU", - "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTB", - "TSTIN0": "BRAM_FIFO36_TSTIN0", - "TSTWROS10": "BRAM_FIFO36_TSTWROS10" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "BRAM_R.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL14->>BRAM_FIFO18_ADDRARDADDR13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_FULL", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT12", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_REGCEB", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI6", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL3->>BRAM_FIFO36_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX28_2->BRAM_R_IMUX_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_FIFO36_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEA1", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI11", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL14->>BRAM_FIFO36_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_CASCOUT_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_UTURN_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI3", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_RAMB18_ADDRBTIEHIGH0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCEAREGCEL", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI13", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL6->>BRAM_FIFO36_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_RAMB18_ADDRBWRADDR5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_CASCOUT_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS1", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL8->>BRAM_FIFO36_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTREGBU", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL10->>BRAM_FIFO18_ADDRARDADDR9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE2", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI6", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI9", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRERR", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI1", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL14->>BRAM_FIFO18_ADDRBWRADDR13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_ALMOSTEMPTY", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN0", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_CASCOUT_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI1", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS3", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI4", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL5->>BRAM_UTURN_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL13->>BRAM_FIFO18_ADDRARDADDR12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX27_3->BRAM_R_IMUX_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_UTURN_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL3->>BRAM_FIFO18_ADDRARDADDR2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE6", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPADOPU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_FIFO36_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_CASCOUT_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL6->>BRAM_FIFO18_ADDRBWRADDR5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS4", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT10", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL1->>BRAM_FIFO36_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL7->>BRAM_FIFO18_ADDRARDADDR6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_EMPTY", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOPADOP0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTREGBL", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT8", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDERR", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL3->>BRAM_UTURN_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEA3", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS0", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE1", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI7", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL12->>BRAM_FIFO18_ADDRARDADDR11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX21_1->BRAM_R_IMUX_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTRAMBU", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_FIFO36_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS12", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX8_3->BRAM_R_IMUX_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPADOPL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX30_3->BRAM_R_IMUX_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_REGCEAREGCE", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL8->>BRAM_FIFO18_ADDRARDADDR7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX35_1->BRAM_R_IMUX_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL1->>BRAM_FIFO18_ADDRBWRADDR0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_UTURN_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX14_3->BRAM_R_IMUX_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_UTURN_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL1->>BRAM_UTURN_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_RAMB18_ADDRBWRADDR11": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_BYP6_2->BRAM_FIFO18_WEBWE7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE7", - "is_directional": "1", - "src_wire": "BRAM_BYP6_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_FIFO36_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_UTURN_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX17_3->BRAM_R_IMUX_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_RAMB18_ADDRARDADDR5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_BYP3_2->BRAM_FIFO18_WEBWE3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE3", - "is_directional": "1", - "src_wire": "BRAM_BYP3_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_RSTREGB", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL11->>BRAM_FIFO36_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_UTURN_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ENBWRENL", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX18_3->BRAM_R_IMUX_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL8->>BRAM_UTURN_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL11->>BRAM_FIFO18_ADDRARDADDR10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_RAMB18_ADDRARDADDR3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPADIPL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI12", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX38_3->BRAM_R_IMUX_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL9->>BRAM_FIFO18_ADDRARDADDR8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_RAMB18_ADDRBWRADDR1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_UTURN_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL5->>BRAM_UTURN_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_RSTREGARSTREG", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_FIFO36_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI4", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN2", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL9->>BRAM_UTURN_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS7", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL13->>BRAM_FIFO18_ADDRBWRADDR12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_CASCOUT_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_CASCOUT_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS9", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL5->>BRAM_FIFO18_ADDRARDADDR4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX25_1->BRAM_R_IMUX_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS5", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_INJECTSBITERR", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_SBITERR", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_CLKARDCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK1_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL4->>BRAM_UTURN_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI2", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS9", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_FIFO36_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_FIFO36_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_UTURN_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX35_3->BRAM_R_IMUX_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL7->>BRAM_FIFO36_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_FIFO36_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI0", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX13_1->BRAM_R_IMUX_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL9->>BRAM_FIFO36_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOPBDOP1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_CASCOUT_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU0", - "is_directional": "1", - "src_wire": "BRAM_FAN5_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI7", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_UTURN_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_CASCOUT_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL10->>BRAM_UTURN_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL9->>BRAM_FIFO36_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI1", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU9", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX10_1->BRAM_R_IMUX_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI6", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX11_1->BRAM_R_IMUX_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI7", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT4", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_CASCOUT_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CLKARDCLKU", - "is_directional": "1", - "src_wire": "BRAM_CLK1_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIPADIP1", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL1->>BRAM_FIFO18_ADDRARDADDR0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_FIFO36_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL6->>BRAM_UTURN_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL10->>BRAM_FIFO36_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI0", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_EMPTY", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_UTURN_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE4", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTOFF", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE0", - "is_directional": "1", - "src_wire": "BRAM_FAN5_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI5", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS8", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_RSTRAMB", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL4->>BRAM_UTURN_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU15", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX12_3->BRAM_R_IMUX_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPBDOPL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN4", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT2", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI3", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_RAMB18_ADDRARDADDR11": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_RAMB18_ADDRBWRADDR9": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL5->>BRAM_FIFO36_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_FIFO36_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_RAMB18_ADDRARDADDR12": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX18_1->BRAM_R_IMUX_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT0", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI14", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS12", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_FIFO36_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI15", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS1", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL10->>BRAM_FIFO36_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CLKBWRCLKL", - "is_directional": "1", - "src_wire": "BRAM_CLK0_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX41_4->BRAM_FIFO36_TSTWROS7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS7", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX33_3->BRAM_R_IMUX_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI13", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL5->>BRAM_FIFO18_ADDRBWRADDR4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI10", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_RAMB18_ADDRARDADDR9": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL8->>BRAM_FIFO36_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPADIPU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX21_3->BRAM_R_IMUX_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL9->>BRAM_FIFO18_ADDRBWRADDR8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_UTURN_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL6->>BRAM_FIFO36_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX33_1->BRAM_R_IMUX_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOPBDOP0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI8", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL0->>BRAM_FIFO36_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI14", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS0", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE2", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI12", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ENARDENL", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL10->>BRAM_UTURN_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL2->>BRAM_UTURN_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX36_1->BRAM_R_IMUX_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCEAREGCEU", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_RAMB18_ADDRBWRADDR7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL0->>BRAM_UTURN_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL1->>BRAM_UTURN_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_2", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIPBDIP1", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI5", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL12->>BRAM_FIFO36_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_CASCADEOUTA", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_CASCOUT_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_CASCOUT_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI8", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_RAMB18_ADDRBWRADDR12": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI14", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL2->>BRAM_FIFO36_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX39_3->BRAM_IMUX_R_ADDRBWRADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI8", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRERR", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI15", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_FIFO36_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI4", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE5", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CLKARDCLKL", - "is_directional": "1", - "src_wire": "BRAM_CLK0_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT3", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPBDIPL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDERR", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL1->>BRAM_FIFO36_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPADOPU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_RSTRAMB", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_CASCOUT_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_RAMB18_ADDRBWRADDR4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL8", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIPADIP1", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE4", - "is_directional": "1", - "src_wire": "BRAM_FAN1_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_CASCOUT_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPBDIPU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_FULL", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX13_3->BRAM_R_IMUX_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL14->>BRAM_FIFO36_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI2", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI3", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL13->>BRAM_FIFO36_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI15", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_CLKBWRCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK0_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_RAMB18_ADDRBWRADDR2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX29_1->BRAM_R_IMUX_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX37_3->BRAM_R_IMUX_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI10", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_UTURN_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_CASCOUT_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL3->>BRAM_FIFO36_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT9", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_UTURN_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_UTURN_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPBDOPU0", - "is_pseudo": "0" - }, "BRAM_R.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_3", - "is_directional": "1", "src_wire": "BRAM_RAMB18_DOBDO11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTRAMBL", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL12->>BRAM_UTURN_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL8", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_RSTREGARSTREG", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL14->>BRAM_UTURN_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL4->>BRAM_FIFO36_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT5", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_REGCLKB", - "is_directional": "1", - "src_wire": "BRAM_CLK1_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI12", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX27_1->BRAM_R_IMUX_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_FIFO36_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX10_3->BRAM_R_IMUX_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DBITERR", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX19_3->BRAM_R_IMUX_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_UTURN_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_FIFO36_ADDRARDADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS3", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL0->>BRAM_FIFO18_ADDRBTIEHIGH0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL4->>BRAM_FIFO18_ADDRARDADDR3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_FIFO36_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX11_3->BRAM_R_IMUX_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE6", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_UTURN_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPBDIPL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX31_1->BRAM_R_IMUX_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS4", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS11", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_UTURN_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI11", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_RAMB18_ADDRARDADDR0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS11", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT11", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL14", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL", - "is_directional": "1", - "src_wire": "BRAM_CLK0_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX26_1->BRAM_R_IMUX_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX12_1->BRAM_R_IMUX_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX38_1->BRAM_R_IMUX_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_BYP3_2->BRAM_FIFO36_WEBWEL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL3", - "is_directional": "1", - "src_wire": "BRAM_BYP3_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_CLKARDCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK0_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL7->>BRAM_UTURN_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_CASCADEOUTB", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ENBWRENU", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS2", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_CASCOUT_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS8", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX20_3->BRAM_R_IMUX_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI1", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX9_3->BRAM_R_IMUX_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX12_2->BRAM_R_IMUX_ADDRARDADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_CASCOUT_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B21_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX25_3->BRAM_R_IMUX_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_CASCOUT_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_FIFO36_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_RAMB18_ADDRARDADDR8": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_FIFO36_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX30_1->BRAM_R_IMUX_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX30_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI9", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_UTURN_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL8->>BRAM_UTURN_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL8->>BRAM_FIFO18_ADDRBWRADDR7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_RAMB18_ADDRBWRADDR6": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_CLKBWRCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK1_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_UTURN_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_CASCOUT_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL6->>BRAM_FIFO18_ADDRARDADDR5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR5", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_UTURN_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_UTURN_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL5", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPADOPL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_FIFO36_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPBDOPU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN3", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_CASCOUT_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_RAMB18_ADDRBWRADDR13": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL4->>BRAM_FIFO18_ADDRBWRADDR3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX33_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU4", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCEBU", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL5->>BRAM_FIFO36_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX28_1->BRAM_R_IMUX_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOPADOP1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ALMOSTEMPTY", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_FIFO36_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX24_3->BRAM_R_IMUX_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU14", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL11->>BRAM_FIFO18_ADDRBWRADDR10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTIN1", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_RAMB18_ADDRARDADDR7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI3", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI4", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX38_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL9->>BRAM_UTURN_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPADIPL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_CASCOUT_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_UTURN_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOPADOP0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS6", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_FIFO36_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1", - "is_directional": "1", - "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_FIFO36_ADDRARDADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX28_3->BRAM_R_IMUX_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTFLAGIN", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL2->>BRAM_FIFO18_ADDRARDADDR1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRARDADDR1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL14", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL11->>BRAM_FIFO36_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ENBWREN", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL6->>BRAM_UTURN_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL11->>BRAM_UTURN_ADDRBWRADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX22_1->BRAM_R_IMUX_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_CASCOUT_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEA1", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_FIFO36_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL2->>BRAM_UTURN_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX26_3->BRAM_R_IMUX_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_IMUX26_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL14->>BRAM_UTURN_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK1_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL9", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL12->>BRAM_FIFO36_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL7->>BRAM_FIFO36_ADDRBWRADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI11", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_RAMB18_ADDRATIEHIGH0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX32_3->BRAM_R_IMUX_ADDRBWRADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPADIPU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL7->>BRAM_UTURN_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL12->>BRAM_FIFO18_ADDRBWRADDR11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL3->>BRAM_UTURN_ADDRARDADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCLKBU", - "is_directional": "1", - "src_wire": "BRAM_CLK1_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT6", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU6", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL0->>BRAM_FIFO18_ADDRATIEHIGH0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX37_1->BRAM_R_IMUX_ADDRBWRADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX37_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL12", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_TSTOUT1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B11_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ECCPARITY7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOPBDOP1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI9", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL8", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU7", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCEBL", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX39_1->BRAM_R_IMUX_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX39_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX36_2->BRAM_R_IMUX_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_RDCOUNT0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI5", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_RAMB18_ADDRBWRADDR3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL9", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_CASCOUT_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL1", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_REGCEB", - "is_directional": "1", - "src_wire": "BRAM_IMUX27_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B20_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_CASCOUT_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL7", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIPBDIP1", - "is_directional": "1", - "src_wire": "BRAM_IMUX1_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL7->>BRAM_FIFO18_ADDRBWRADDR6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_RAMB18_ADDRARDADDR13": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU15", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_CASCOUT_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU8", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_REGCLKB", - "is_directional": "1", - "src_wire": "BRAM_CLK0_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX34_3->BRAM_R_IMUX_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOPBDOPL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL0->>BRAM_UTURN_ADDRBWRADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE0", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL2->>BRAM_FIFO18_ADDRBWRADDR1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI0", - "is_directional": "1", - "src_wire": "BRAM_IMUX24_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX36_3->BRAM_R_IMUX_ADDRBWRADDRL5": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL5", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_FIFO36_ADDRBWRADDRU6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU6", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B4_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL4", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU8", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS10", - "is_directional": "1", - "src_wire": "BRAM_IMUX44_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX17_1->BRAM_R_IMUX_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_CASCOUT_ADDRBWRADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU9", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_UTURN_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_FIFO36_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIL0", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI8", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIPBDIP0", - "is_directional": "1", - "src_wire": "BRAM_IMUX4_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_RAMB18_ADDRBWRADDR10": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR10", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU4", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL4->>BRAM_FIFO36_ADDRARDADDRL4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX19_1->BRAM_R_IMUX_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL2", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIPBDIP0", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_UTURN_ADDRBWRADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU5", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEA0", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS5", - "is_directional": "1", - "src_wire": "BRAM_IMUX47_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE5", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI2", - "is_directional": "1", - "src_wire": "BRAM_IMUX28_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_CASCOUT_ADDRBWRADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU11", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_UTURN_ADDRARDADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOPADOP1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL0->>BRAM_FIFO36_ADDRARDADDRL0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_ALMOSTFULL", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS10", - "is_directional": "1", - "src_wire": "BRAM_IMUX36_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU10", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_FIFO36_ADDRARDADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU", - "is_directional": "1", - "src_wire": "BRAM_CLK1_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOBDO3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI11", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX22_3->BRAM_R_IMUX_ADDRARDADDRL14": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL14", - "is_directional": "1", - "src_wire": "BRAM_IMUX22_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI14", - "is_directional": "1", - "src_wire": "BRAM_IMUX7_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_BYP6_2->BRAM_FIFO36_WEBWEL7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEL7", - "is_directional": "1", - "src_wire": "BRAM_BYP6_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_WRCOUNT9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_RAMB18_ADDRARDADDR4": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL9", - "is_directional": "1", - "src_wire": "BRAM_IMUX35_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_UTURN_ADDRARDADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_FIFO36_ADDRARDADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_REGCLKBL", - "is_directional": "1", - "src_wire": "BRAM_CLK0_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL10", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_UTURN_ADDRBWRADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIPBDIPU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_ALMOSTFULL", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_CASCOUT_ADDRBWRADDRU3": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU3", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL13->>BRAM_UTURN_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI0", - "is_directional": "1", - "src_wire": "BRAM_IMUX8_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ENARDEN", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX20_1->BRAM_R_IMUX_ADDRARDADDRL8": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL8", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_RAMB18_ADDRARDADDR2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR2", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX29_3->BRAM_R_IMUX_ADDRBWRADDRU12": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX29_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_CASCOUT_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIADIU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_RSTREGB", - "is_directional": "1", - "src_wire": "BRAM_CTRL1_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_CASCOUT_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX14_1->BRAM_R_IMUX_ADDRARDADDRU11": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX14_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU1", - "is_directional": "1", - "src_wire": "BRAM_IMUX13_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDOS6", - "is_directional": "1", - "src_wire": "BRAM_IMUX32_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_FIFO36_ADDRARDADDRU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU4", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE3", - "is_directional": "1", - "src_wire": "BRAM_IMUX45_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIBDI13", - "is_directional": "1", - "src_wire": "BRAM_IMUX5_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B5_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B8_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRU5", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_RAMB18_ADDRBWRADDR8": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR8", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI6", - "is_directional": "1", - "src_wire": "BRAM_IMUX12_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT7", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK", - "is_directional": "1", - "src_wire": "BRAM_CLK0_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX16_3->BRAM_R_IMUX_ADDRARDADDRL6": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL6", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIL14", - "is_directional": "1", - "src_wire": "BRAM_IMUX7_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL11->>BRAM_UTURN_ADDRARDADDRL11": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL11", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU2", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU11", - "is_directional": "1", - "src_wire": "BRAM_IMUX6_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIPADIP0", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_REGCEAREGCE", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_RDCOUNT6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_UTURN_ADDRARDADDRU14": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU14", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ENARDEN", - "is_directional": "1", - "src_wire": "BRAM_IMUX18_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF", - "is_directional": "1", - "src_wire": "BRAM_IMUX2_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRL12->>BRAM_UTURN_ADDRARDADDRL12": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRL12", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRL12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_FIFO36_ADDRARDADDRU9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU9", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_CASCOUT_ADDRBWRADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIADI7", - "is_directional": "1", - "src_wire": "BRAM_IMUX40_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL2", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOPBDOP0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL7", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRARDADDRL7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOBDO6", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEBWEU4", - "is_directional": "1", - "src_wire": "BRAM_FAN1_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEBWE7", - "is_directional": "1", - "src_wire": "BRAM_IMUX46_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI9", - "is_directional": "1", - "src_wire": "BRAM_IMUX41_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEA2", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL13->>BRAM_UTURN_ADDRBWRADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRL13", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_UTURN_ADDRBWRADDRU1": { - "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRBWRADDRU1", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_WEAU2", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B2_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEA0", - "is_directional": "1", - "src_wire": "BRAM_IMUX16_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_FIFO36_ADDRBWRADDRU7": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU7", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOADOU9", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_RAMB18_ADDRBWRADDR0": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRBWRADDR0", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRU1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX9_1->BRAM_R_IMUX_ADDRARDADDRU0": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU0", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEA3", - "is_directional": "1", - "src_wire": "BRAM_IMUX25_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL3->>BRAM_FIFO18_ADDRBWRADDR2": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR2", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_RAMB18_ADDRARDADDR1": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR1", - "is_directional": "1", - "src_wire": "BRAM_ADDRARDADDRU2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_0", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX31_3->BRAM_IMUX_R_ADDRARDADDRL15": { - "can_invert": "0", - "dst_wire": "BRAM_IMUX_R_ADDRARDADDRL15", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_DIPADIP0", - "is_directional": "1", - "src_wire": "BRAM_IMUX3_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_WEA2", - "is_directional": "1", - "src_wire": "BRAM_IMUX9_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_INJECTDBITERR", - "is_directional": "1", - "src_wire": "BRAM_IMUX31_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_WEBWE1", - "is_directional": "1", - "src_wire": "BRAM_IMUX21_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI2", - "is_directional": "1", - "src_wire": "BRAM_IMUX42_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX34_1->BRAM_R_IMUX_ADDRBWRADDRL1": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL1", - "is_directional": "1", - "src_wire": "BRAM_IMUX34_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_ADDRBWRADDRL10->>BRAM_FIFO18_ADDRBWRADDR9": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO18_ADDRBWRADDR9", - "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX15_1->BRAM_R_IMUX_ADDRARDADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU13", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "is_directional": "1", - "src_wire": "BRAM_CTRL0_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI10", - "is_directional": "1", - "src_wire": "BRAM_IMUX43_3", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B23_3", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_WRCOUNT8", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU10", - "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ENARDENU", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI5", - "is_directional": "1", - "src_wire": "BRAM_IMUX10_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_DIBDIU12", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI13", - "is_directional": "1", - "src_wire": "BRAM_IMUX19_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOL14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { - "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTCNT1", - "is_directional": "1", - "src_wire": "BRAM_IMUX11_0", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI12", - "is_directional": "1", - "src_wire": "BRAM_IMUX17_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "BRAM_RAMB18_DOADO12", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIADI15", - "is_directional": "1", - "src_wire": "BRAM_IMUX15_4", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX20_2->BRAM_R_IMUX_ADDRARDADDRL10": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL10", - "is_directional": "1", - "src_wire": "BRAM_IMUX20_2", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX23_1->BRAM_R_IMUX_ADDRARDADDRL13": { - "can_invert": "0", - "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL13", - "is_directional": "1", - "src_wire": "BRAM_IMUX23_1", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRU13", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU13", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { - "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B7_1", - "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO14", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL3", - "is_directional": "1", - "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_3" }, "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_FIFO36_ADDRARDADDRU3": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRU3", - "is_directional": "1", "src_wire": "BRAM_ADDRARDADDRU3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU3" + }, + "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL8" + }, + "BRAM_R.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOPBDOP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_1" + }, + "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_UTURN_ADDRARDADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU10" + }, + "BRAM_R.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX43_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI10" + }, + "BRAM_R.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_2" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_1" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0" + }, + "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL4" + }, + "BRAM_R.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { + "can_invert": "0", + "src_wire": "BRAM_CLK0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_CLKARDCLK" + }, + "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL6" + }, + "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_CASCOUT_ADDRBWRADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU0" + }, + "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8" + }, + "BRAM_R.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX13_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU1" + }, + "BRAM_R.BRAM_ADDRARDADDRL12->>BRAM_FIFO36_ADDRARDADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL12" + }, + "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_CASCOUT_ADDRBWRADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU14" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_3" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11" + }, + "BRAM_R.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS4" + }, + "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_CASCOUT_ADDRARDADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU3" + }, + "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_UTURN_ADDRARDADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU2" + }, + "BRAM_R.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX9_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU2" + }, + "BRAM_R.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU6" + }, + "BRAM_R.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX11_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI13" + }, + "BRAM_R.BRAM_IMUX25_3->BRAM_R_IMUX_ADDRBWRADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX25_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU7" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_0" + }, + "BRAM_R.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX10_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU5" + }, + "BRAM_R.BRAM_ADDRBWRADDRL4->>BRAM_UTURN_ADDRBWRADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL4" + }, + "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL14" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ECCPARITY0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_3" + }, + "BRAM_R.BRAM_ADDRARDADDRL5->>BRAM_FIFO36_ADDRARDADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL5" + }, + "BRAM_R.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX41_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU9" + }, + "BRAM_R.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU2" + }, + "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_RAMB18_ADDRBWRADDR13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR13" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7" + }, + "BRAM_R.BRAM_ADDRARDADDRL10->>BRAM_UTURN_ADDRARDADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL10" + }, + "BRAM_R.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_0" + }, + "BRAM_R.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_1" + }, + "BRAM_R.BRAM_ADDRARDADDRL9->>BRAM_FIFO36_ADDRARDADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL9" + }, + "BRAM_R.BRAM_IMUX9_3->BRAM_R_IMUX_ADDRARDADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX9_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU7" + }, + "BRAM_R.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { + "can_invert": "0", + "src_wire": "BRAM_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTREGB" + }, + "BRAM_R.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX30_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT12" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6" + }, + "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPBDIP1" + }, + "BRAM_R.BRAM_ADDRBWRADDRL2->>BRAM_UTURN_ADDRBWRADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL2" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7" + }, + "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_FIFO36_ADDRARDADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU5" + }, + "BRAM_R.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX43_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU10" + }, + "BRAM_R.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_0" + }, + "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL8" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5" + }, + "BRAM_R.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_0" + }, + "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { + "can_invert": "0", + "src_wire": "BRAM_CTRL0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9" + }, + "BRAM_R.BRAM_IMUX20_3->BRAM_R_IMUX_ADDRARDADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX20_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL5" + }, + "BRAM_R.BRAM_ADDRARDADDRL10->>BRAM_FIFO36_ADDRARDADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL10" + }, + "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL1" + }, + "BRAM_R.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { + "can_invert": "0", + "src_wire": "BRAM_CLK0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK" + }, + "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_CASCOUT_ADDRARDADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU5" + }, + "BRAM_R.BRAM_ADDRARDADDRL2->>BRAM_UTURN_ADDRARDADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL2" + }, + "BRAM_R.BRAM_BYP6_2->BRAM_FIFO18_WEBWE7": { + "can_invert": "0", + "src_wire": "BRAM_BYP6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE7" + }, + "BRAM_R.BRAM_ADDRBWRADDRL1->>BRAM_FIFO18_ADDRBWRADDR0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR0" + }, + "BRAM_R.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPBDIP1" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8" + }, + "BRAM_R.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { + "can_invert": "0", + "src_wire": "BRAM_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTFLAGIN" + }, + "BRAM_R.BRAM_ADDRARDADDRL4->>BRAM_UTURN_ADDRARDADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL4" + }, + "BRAM_R.BRAM_ADDRARDADDRL6->>BRAM_UTURN_ADDRARDADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL6" + }, + "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_UTURN_ADDRBWRADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU10" + }, + "BRAM_R.BRAM_IMUX28_2->BRAM_R_IMUX_ADDRBWRADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX28_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU10" + }, + "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL9" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10" + }, + "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_FIFO36_ADDRARDADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU10" + }, + "BRAM_R.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_4" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_1" + }, + "BRAM_R.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU2" + }, + "BRAM_R.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_1" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11" + }, + "BRAM_R.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_CASCADEOUTB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1" + }, + "BRAM_R.BRAM_ADDRARDADDRL12->>BRAM_FIFO18_ADDRARDADDR11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR11" + }, + "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI14" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1" + }, + "BRAM_R.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_3" + }, + "BRAM_R.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI11" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1" + }, + "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL7" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_1" + }, + "BRAM_R.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN1" + }, + "BRAM_R.BRAM_IMUX14_1->BRAM_R_IMUX_ADDRARDADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU11" + }, + "BRAM_R.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { + "can_invert": "0", + "src_wire": "BRAM_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCLKB" + }, + "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE6" + }, + "BRAM_R.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_1" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_3" + }, + "BRAM_R.BRAM_IMUX17_3->BRAM_R_IMUX_ADDRARDADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX17_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL7" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8" + }, + "BRAM_R.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX24_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT6" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ECCPARITY5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_2" + }, + "BRAM_R.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_1" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12" + }, + "BRAM_R.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE2" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_CASCOUT_ADDRBWRADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU13" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1" + }, + "BRAM_R.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_0" }, "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_UTURN_ADDRARDADDRU5": { "can_invert": "0", - "dst_wire": "BRAM_UTURN_ADDRARDADDRU5", - "is_directional": "1", "src_wire": "BRAM_ADDRARDADDRU5", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { - "can_invert": "0", - "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU5" + }, + "BRAM_R.BRAM_ADDRARDADDRL8->>BRAM_UTURN_ADDRARDADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL8" + }, + "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_UTURN_ADDRBWRADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU13" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_4" + }, + "BRAM_R.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_0" + }, + "BRAM_R.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX18_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS0" + }, + "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_0" + }, + "BRAM_R.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { + "can_invert": "0", + "src_wire": "BRAM_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKBL" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14" + }, + "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_UTURN_ADDRARDADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU12" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_1" + }, + "BRAM_R.BRAM_IMUX37_3->BRAM_R_IMUX_ADDRBWRADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX37_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL12" + }, + "BRAM_R.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { + "can_invert": "0", + "src_wire": "BRAM_CTRL1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTRAMB" + }, + "BRAM_R.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX41_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI9" + }, + "BRAM_R.BRAM_ADDRBWRADDRL5->>BRAM_FIFO36_ADDRBWRADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL5" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10" + }, + "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15" + }, + "BRAM_R.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_3" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_3" + }, + "BRAM_R.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5" + }, + "BRAM_R.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX8_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14" + }, + "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL11" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_4" + }, + "BRAM_R.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU10" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_3" + }, + "BRAM_R.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX23_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI15" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_2" + }, + "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_UTURN_ADDRBWRADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU14" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_TSTOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_1" + }, + "BRAM_R.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX46_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU7" + }, + "BRAM_R.BRAM_BYP3_2->BRAM_FIFO18_WEBWE3": { + "can_invert": "0", + "src_wire": "BRAM_BYP3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE3" + }, + "BRAM_R.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI3" + }, + "BRAM_R.BRAM_ADDRARDADDRL3->>BRAM_UTURN_ADDRARDADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL3" + }, + "BRAM_R.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOPADOP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_3" + }, + "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI9" + }, + "BRAM_R.BRAM_ADDRARDADDRL8->>BRAM_FIFO36_ADDRARDADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL8" + }, + "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_UTURN_ADDRARDADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU4" + }, + "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX22_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE5" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_1" + }, + "BRAM_R.BRAM_IMUX31_3->BRAM_IMUX_R_ADDRARDADDRL15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_R_ADDRARDADDRL15" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_4" + }, + "BRAM_R.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_3" + }, + "BRAM_R.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOPBDOPU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_3" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_1" + }, + "BRAM_R.BRAM_IMUX18_1->BRAM_R_IMUX_ADDRARDADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX18_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL1" + }, + "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX33_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1" + }, + "BRAM_R.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX16_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU4" + }, + "BRAM_R.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX45_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS11" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_4" + }, + "BRAM_R.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_3" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4" + }, + "BRAM_R.BRAM_ADDRARDADDRL1->>BRAM_FIFO18_ADDRARDADDR0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_4" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_TSTOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_1" + }, + "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { + "can_invert": "0", + "src_wire": "BRAM_CTRL0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTRAMB" + }, + "BRAM_R.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_4" + }, + "BRAM_R.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOPADOP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_1" + }, + "BRAM_R.BRAM_BYP3_2->BRAM_FIFO36_WEBWEL3": { + "can_invert": "0", + "src_wire": "BRAM_BYP3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL3" + }, + "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_FIFO36_ADDRBWRADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU8" + }, + "BRAM_R.BRAM_IMUX22_1->BRAM_R_IMUX_ADDRARDADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL11" + }, + "BRAM_R.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_2" + }, + "BRAM_R.BRAM_ADDRBWRADDRL12->>BRAM_FIFO36_ADDRBWRADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL12" + }, + "BRAM_R.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOPBDOP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12" + }, + "BRAM_R.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX45_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE3" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_4" + }, + "BRAM_R.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX9_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA2" + }, + "BRAM_R.BRAM_ADDRBWRADDRL8->>BRAM_FIFO36_ADDRBWRADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL8" + }, + "BRAM_R.BRAM_IMUX34_3->BRAM_R_IMUX_ADDRBWRADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX34_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL3" + }, + "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL2" + }, + "BRAM_R.BRAM_IMUX33_1->BRAM_R_IMUX_ADDRBWRADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX33_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_0" + }, + "BRAM_R.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA1" + }, + "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_FIFO36_ADDRBWRADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU2" + }, + "BRAM_R.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT4" + }, + "BRAM_R.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPADIP1" + }, + "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_RAMB18_ADDRARDADDR5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR5" + }, + "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI12" + }, + "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_CASCOUT_ADDRARDADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU14" + }, + "BRAM_R.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX13_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE1" + }, + "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL0" + }, + "BRAM_R.BRAM_IMUX11_3->BRAM_R_IMUX_ADDRARDADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU9" + }, + "BRAM_R.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_2" + }, + "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_FIFO36_ADDRBWRADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU6" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5" + }, + "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_CASCOUT_ADDRBWRADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU5" + }, + "BRAM_R.BRAM_ADDRARDADDRL1->>BRAM_UTURN_ADDRARDADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL1" + }, + "BRAM_R.BRAM_ADDRBWRADDRL14->>BRAM_FIFO18_ADDRBWRADDR13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR13" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_1" + }, + "BRAM_R.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_4" + }, + "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_RAMB18_ADDRBWRADDR10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR10" }, "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_RAMB18_ADDRARDADDR10": { "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR10", - "is_directional": "1", "src_wire": "BRAM_ADDRARDADDRU11", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ENBWREN", "is_directional": "1", - "src_wire": "BRAM_IMUX26_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR10" }, - "BRAM_R.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_CLKBWRCLKU", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8", "is_directional": "1", - "src_wire": "BRAM_CLK1_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8" }, - "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_RAMB18_ADDRARDADDR6": { + "BRAM_R.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", - "dst_wire": "BRAM_RAMB18_ADDRARDADDR6", + "src_wire": "BRAM_FIFO36_RDCOUNT3", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_1" + }, + "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_UTURN_ADDRARDADDRU7": { + "can_invert": "0", "src_wire": "BRAM_ADDRARDADDRU7", - "is_pseudo": "0" - }, - "BRAM_R.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { - "can_invert": "0", - "dst_wire": "BRAM_RAMB18_DIBDI10", "is_directional": "1", - "src_wire": "BRAM_IMUX4_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU7" }, - "BRAM_R.BRAM_ADDRBWRADDRL2->>BRAM_FIFO36_ADDRBWRADDRL2": { + "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_RAMB18_ADDRBWRADDR1": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL2", + "src_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", - "src_wire": "BRAM_ADDRBWRADDRL2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR1" }, - "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { + "BRAM_R.BRAM_IMUX13_3->BRAM_R_IMUX_ADDRARDADDRU12": { "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL4", + "src_wire": "BRAM_IMUX13_3", "is_directional": "1", - "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU12" }, - "BRAM_R.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTWROS2", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", "is_directional": "1", - "src_wire": "BRAM_IMUX44_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9" }, - "BRAM_R.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { + "BRAM_R.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B1_3", + "src_wire": "BRAM_IMUX13_4", "is_directional": "1", - "src_wire": "BRAM_FIFO36_DOBDOU2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU14" }, - "BRAM_R.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { + "BRAM_R.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B15_1", + "src_wire": "BRAM_RAMB18_DOBDO8", "is_directional": "1", - "src_wire": "BRAM_FIFO18_DOADO6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_2" }, - "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { + "BRAM_R.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { "can_invert": "0", - "dst_wire": "BRAM_ADDRBWRADDRL3", + "src_wire": "BRAM_IMUX14_4", "is_directional": "1", - "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU7" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10" + }, + "BRAM_R.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX45_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU3" + }, + "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_CASCOUT_ADDRBWRADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU6" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14" + }, + "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_UTURN_ADDRBWRADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU6" + }, + "BRAM_R.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU11" + }, + "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_RAMB18_ADDRARDADDR2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR2" + }, + "BRAM_R.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_2" + }, + "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI15" + }, + "BRAM_R.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { + "can_invert": "0", + "src_wire": "BRAM_IMUX31_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_INJECTDBITERR" + }, + "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_UTURN_ADDRARDADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU1" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3" + }, + "BRAM_R.BRAM_ADDRBWRADDRL6->>BRAM_FIFO36_ADDRBWRADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL6" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_0" + }, + "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_FIFO36_ADDRARDADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU1" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11" + }, + "BRAM_R.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS12" + }, + "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_UTURN_ADDRBWRADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU4" + }, + "BRAM_R.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { + "can_invert": "0", + "src_wire": "BRAM_IMUX39_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_INJECTSBITERR" + }, + "BRAM_R.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_ALMOSTEMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_2" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12" + }, + "BRAM_R.BRAM_IMUX8_3->BRAM_R_IMUX_ADDRARDADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU6" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11" + }, + "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_UTURN_ADDRARDADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU13" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_0" + }, + "BRAM_R.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DBITERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_2" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_3" + }, + "BRAM_R.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEA3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3" + }, + "BRAM_R.BRAM_IMUX10_1->BRAM_R_IMUX_ADDRARDADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU1" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8" + }, + "BRAM_R.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_3" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13" + }, + "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE4" + }, + "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10" + }, + "BRAM_R.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ALMOSTFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_2" + }, + "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_RAMB18_ADDRBWRADDR0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL1->>BRAM_UTURN_ADDRBWRADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL1" + }, + "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI5" + }, + "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_UTURN_ADDRBWRADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU0" + }, + "BRAM_R.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT3" + }, + "BRAM_R.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_2" + }, + "BRAM_R.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_0" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_1" + }, + "BRAM_R.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS3" + }, + "BRAM_R.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX37_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS11" + }, + "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX41_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI15" + }, + "BRAM_R.BRAM_ADDRBWRADDRL3->>BRAM_FIFO36_ADDRBWRADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL3" + }, + "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL4" + }, + "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_FIFO36_ADDRARDADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU2" + }, + "BRAM_R.BRAM_IMUX34_1->BRAM_R_IMUX_ADDRBWRADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL1" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13" + }, + "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL13" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_0" + }, + "BRAM_R.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_3" + }, + "BRAM_R.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX14_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI7" + }, + "BRAM_R.BRAM_IMUX38_3->BRAM_R_IMUX_ADDRBWRADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL14" + }, + "BRAM_R.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX14_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE5" + }, + "BRAM_R.BRAM_ADDRARDADDRU3->>BRAM_UTURN_ADDRARDADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU3" + }, + "BRAM_R.BRAM_ADDRARDADDRL0->>BRAM_FIFO18_ADDRATIEHIGH0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL7->>BRAM_UTURN_ADDRBWRADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL7" + }, + "BRAM_R.BRAM_ADDRARDADDRL7->>BRAM_FIFO36_ADDRARDADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL7" + }, + "BRAM_R.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPU1" + }, + "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI1" + }, + "BRAM_R.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_0" + }, + "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { + "can_invert": "0", + "src_wire": "BRAM_CTRL0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_2" + }, + "BRAM_R.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_0" + }, + "BRAM_R.BRAM_IMUX41_4->BRAM_FIFO36_TSTWROS7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX41_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS7" + }, + "BRAM_R.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL8->>BRAM_UTURN_ADDRBWRADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL8" + }, + "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_CASCOUT_ADDRARDADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU7" + }, + "BRAM_R.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX18_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU5" + }, + "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_CASCOUT_ADDRBWRADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU8" + }, + "BRAM_R.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU12" + }, + "BRAM_R.BRAM_IMUX31_1->BRAM_R_IMUX_ADDRBWRADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU13" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_1" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_4" + }, + "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI6" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0" + }, + "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_CASCOUT_ADDRARDADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU6" + }, + "BRAM_R.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN4" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4" + }, + "BRAM_R.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { + "can_invert": "0", + "src_wire": "BRAM_CLK1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_CLKBWRCLK" + }, + "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL10" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13" + }, + "BRAM_R.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_1" + }, + "BRAM_R.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_1" + }, + "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_RAMB18_ADDRBWRADDR4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR4" + }, + "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_CASCOUT_ADDRARDADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU9" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_2" + }, + "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL5" + }, + "BRAM_R.BRAM_ADDRBWRADDRL11->>BRAM_FIFO36_ADDRBWRADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL11" + }, + "BRAM_R.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_FULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_2" + }, + "BRAM_R.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { + "can_invert": "0", + "src_wire": "BRAM_CTRL1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMBU" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL4->>BRAM_FIFO18_ADDRBWRADDR3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR3" + }, + "BRAM_R.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU11" + }, + "BRAM_R.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_0" + }, + "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { + "can_invert": "0", + "src_wire": "BRAM_IMUX18_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENARDENL" + }, + "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_FIFO36_ADDRARDADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU4" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_3" + }, + "BRAM_R.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI0" + }, + "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPL0" + }, + "BRAM_R.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX24_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU0" + }, + "BRAM_R.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_1" + }, + "BRAM_R.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL9->>BRAM_UTURN_ADDRBWRADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL9" + }, + "BRAM_R.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOPADOPL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_1" + }, + "BRAM_R.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_1" + }, + "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_FIFO36_ADDRARDADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU11" + }, + "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL9" + }, + "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_RAMB18_ADDRBWRADDR3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR3" + }, + "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_CASCOUT_ADDRARDADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU4" + }, + "BRAM_R.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_2" + }, + "BRAM_R.BRAM_IMUX30_1->BRAM_R_IMUX_ADDRBWRADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU11" + }, + "BRAM_R.BRAM_ADDRARDADDRL4->>BRAM_FIFO36_ADDRARDADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL4" + }, + "BRAM_R.BRAM_ADDRBWRADDRL10->>BRAM_FIFO18_ADDRBWRADDR9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR9" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_3" + }, + "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPBDIP0" + }, + "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX43_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL5" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL13" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_3" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_0" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_3" + }, + "BRAM_R.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX19_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS1" }, "BRAM_R.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", - "dst_wire": "BRAM_LOGIC_OUTS_B0_3", - "is_directional": "1", "src_wire": "BRAM_RAMB18_DOADO9", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3" + }, + "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_RAMB18_ADDRBWRADDR8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR8" + }, + "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { + "can_invert": "0", + "src_wire": "BRAM_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEAREGCEL" + }, + "BRAM_R.BRAM_ADDRARDADDRL6->>BRAM_FIFO18_ADDRARDADDR5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR5" + }, + "BRAM_R.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX15_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU8" + }, + "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPADIP1" + }, + "BRAM_R.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { + "can_invert": "0", + "src_wire": "BRAM_IMUX10_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ENARDEN" + }, + "BRAM_R.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX23_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS5" + }, + "BRAM_R.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_FIFO36_ADDRBWRADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU4" + }, + "BRAM_R.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { + "can_invert": "0", + "src_wire": "BRAM_IMUX10_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENARDENU" + }, + "BRAM_R.BRAM_IMUX28_1->BRAM_R_IMUX_ADDRBWRADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX28_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU8" + }, + "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_RAMB18_ADDRARDADDR0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR0" + }, + "BRAM_R.BRAM_IMUX39_1->BRAM_R_IMUX_ADDRBWRADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL13" + }, + "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_CASCOUT_ADDRBWRADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU12" + }, + "BRAM_R.BRAM_IMUX27_3->BRAM_R_IMUX_ADDRBWRADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU9" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_0" + }, + "BRAM_R.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI1" + }, + "BRAM_R.BRAM_IMUX20_1->BRAM_R_IMUX_ADDRARDADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL8" + }, + "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_RAMB18_ADDRBWRADDR7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR7" + }, + "BRAM_R.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ALMOSTEMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_2" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_1" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7" + }, + "BRAM_R.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_0" + }, + "BRAM_R.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { + "can_invert": "0", + "src_wire": "BRAM_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_CLKBWRCLK" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_2" + }, + "BRAM_R.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX23_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU15" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12" + }, + "BRAM_R.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_2" + }, + "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_FIFO36_ADDRARDADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU9" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12" + }, + "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_FIFO36_ADDRARDADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU14" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7" + }, + "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_FIFO36_ADDRARDADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU12" + }, + "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_FIFO36_ADDRBWRADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU0" + }, + "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_RAMB18_ADDRARDADDR8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR8" + }, + "BRAM_R.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_0" + }, + "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE1" + }, + "BRAM_R.BRAM_IMUX16_3->BRAM_R_IMUX_ADDRARDADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX16_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL6" + }, + "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL1" + }, + "BRAM_R.BRAM_ADDRARDADDRL14->>BRAM_FIFO36_ADDRARDADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL14" + }, + "BRAM_R.BRAM_IMUX39_3->BRAM_IMUX_R_ADDRBWRADDRL15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX39_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_IMUX_R_ADDRBWRADDRL15" + }, + "BRAM_R.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS2" + }, + "BRAM_R.BRAM_BYP6_2->BRAM_FIFO36_WEBWEL7": { + "can_invert": "0", + "src_wire": "BRAM_BYP6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL7" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_3" + }, + "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX37_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE2" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2" + }, + "BRAM_R.BRAM_ADDRBWRADDRL6->>BRAM_FIFO18_ADDRBWRADDR5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR5" + }, + "BRAM_R.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX10_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI5" + }, + "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_CASCOUT_ADDRARDADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU11" + }, + "BRAM_R.BRAM_IMUX21_3->BRAM_R_IMUX_ADDRARDADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX21_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL12" + }, + "BRAM_R.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { + "can_invert": "0", + "src_wire": "BRAM_CLK1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKBWRCLKU" + }, + "BRAM_R.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI14" + }, + "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX33_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA3" + }, + "BRAM_R.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_3" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_0" + }, + "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { + "can_invert": "0", + "src_wire": "BRAM_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ENBWREN" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL6" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL4" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_4" + }, + "BRAM_R.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5" + }, + "BRAM_R.BRAM_ADDRARDADDRL4->>BRAM_FIFO18_ADDRARDADDR3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR3" + }, + "BRAM_R.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_1" + }, + "BRAM_R.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { + "can_invert": "0", + "src_wire": "BRAM_IMUX11_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEAREGCEU" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11" + }, + "BRAM_R.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_4" + }, + "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_CASCOUT_ADDRBWRADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU2" + }, + "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_CASCOUT_ADDRARDADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL3->>BRAM_UTURN_ADDRBWRADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL3" + }, + "BRAM_R.BRAM_ADDRBWRADDRU4->>BRAM_CASCOUT_ADDRBWRADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU4" + }, + "BRAM_R.BRAM_ADDRARDADDRL0->>BRAM_UTURN_ADDRARDADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_2" + }, + "BRAM_R.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_1" + }, + "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL7" + }, + "BRAM_R.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_FIFO36_ADDRBWRADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU9" + }, + "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { + "can_invert": "0", + "src_wire": "BRAM_IMUX35_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCEB" + }, + "BRAM_R.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { + "can_invert": "0", + "src_wire": "BRAM_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEBU" + }, + "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIPADIP0" + }, + "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL3" + }, + "BRAM_R.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_4" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3" + }, + "BRAM_R.BRAM_IMUX24_3->BRAM_R_IMUX_ADDRBWRADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU6" + }, + "BRAM_R.BRAM_IMUX26_1->BRAM_R_IMUX_ADDRBWRADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU1" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_3" + }, + "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { + "can_invert": "0", + "src_wire": "BRAM_IMUX35_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCEBL" + }, + "BRAM_R.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_2" + }, + "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI12" + }, + "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPL1" + }, + "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_UTURN_ADDRBWRADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU12" + }, + "BRAM_R.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU4" + }, + "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_UTURN_ADDRARDADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU14" + }, + "BRAM_R.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX26_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT8" + }, + "BRAM_R.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX15_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI15" + }, + "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_RAMB18_ADDRARDADDR12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR12" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_1" + }, + "BRAM_R.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI2" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14" }, "BRAM_R.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_TSTBRAMRST", - "is_directional": "1", "src_wire": "BRAM_IMUX0_0", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTBRAMRST" + }, + "BRAM_R.BRAM_ADDRBWRADDRL12->>BRAM_UTURN_ADDRBWRADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL12" + }, + "BRAM_R.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX42_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPU0" + }, + "BRAM_R.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { + "can_invert": "0", + "src_wire": "BRAM_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCLKB" + }, + "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_RAMB18_ADDRARDADDR6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR6" + }, + "BRAM_R.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { + "can_invert": "0", + "src_wire": "BRAM_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTOFF" + }, + "BRAM_R.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI4" + }, + "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEBWE0" + }, + "BRAM_R.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOPBDOPL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_1" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL7" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_4" + }, + "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_FIFO36_ADDRARDADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU13" + }, + "BRAM_R.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX35_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS9" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8" + }, + "BRAM_R.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX19_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU13" + }, + "BRAM_R.BRAM_ADDRARDADDRL11->>BRAM_FIFO36_ADDRARDADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL11" + }, + "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { + "can_invert": "0", + "src_wire": "BRAM_CTRL0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL" + }, + "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_FIFO36_ADDRBWRADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU12" + }, + "BRAM_R.BRAM_ADDRARDADDRL2->>BRAM_FIFO18_ADDRARDADDR1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR1" + }, + "BRAM_R.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT10" + }, + "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { + "can_invert": "0", + "src_wire": "BRAM_IMUX18_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ENARDEN" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9" + }, + "BRAM_R.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_CASCADEOUTA", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0" + }, + "BRAM_R.BRAM_ADDRARDADDRU9->>BRAM_UTURN_ADDRARDADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU9" + }, + "BRAM_R.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_4" + }, + "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1" + }, + "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1" + }, + "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPL1" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_3" + }, + "BRAM_R.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI1" + }, + "BRAM_R.BRAM_ADDRBWRADDRL11->>BRAM_FIFO18_ADDRBWRADDR10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR10" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_1" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_3" + }, + "BRAM_R.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU3" + }, + "BRAM_R.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_4" + }, + "BRAM_R.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS1" + }, + "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI7" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11" + }, + "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI8" + }, + "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI8" + }, + "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_FIFO36_ADDRBWRADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU11" + }, + "BRAM_R.BRAM_ADDRBWRADDRL3->>BRAM_FIFO18_ADDRBWRADDR2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR2" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL1" + }, + "BRAM_R.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX43_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS9" + }, + "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_RAMB18_ADDRBWRADDR12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR12" + }, + "BRAM_R.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX30_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE6" + }, + "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_RAMB18_ADDRBWRADDR2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR2" + }, + "BRAM_R.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { + "can_invert": "0", + "src_wire": "BRAM_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKBU" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU12" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9" + }, + "BRAM_R.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_2" + }, + "BRAM_R.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX25_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT7" + }, + "BRAM_R.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_1" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_0" + }, + "BRAM_R.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPU1" + }, + "BRAM_R.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX23_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU8" + }, + "BRAM_R.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_1" + }, + "BRAM_R.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_4" + }, + "BRAM_R.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX22_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI7" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU0" + }, + "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL15" + }, + "BRAM_R.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_1" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL9" + }, + "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { + "can_invert": "0", + "src_wire": "BRAM_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENBWRENL" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL11" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL5" + }, + "BRAM_R.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { + "can_invert": "0", + "src_wire": "BRAM_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCEB" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4" + }, + "BRAM_R.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS5" + }, + "BRAM_R.BRAM_IMUX11_1->BRAM_R_IMUX_ADDRARDADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX11_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU2" + }, + "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_UTURN_ADDRBWRADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU11" + }, + "BRAM_R.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_4" + }, + "BRAM_R.BRAM_IMUX38_1->BRAM_R_IMUX_ADDRBWRADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL11" + }, + "BRAM_R.BRAM_IMUX25_1->BRAM_R_IMUX_ADDRBWRADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL13" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL8" + }, + "BRAM_R.BRAM_ADDRBWRADDRL8->>BRAM_FIFO18_ADDRBWRADDR7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR7" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8" + }, + "BRAM_R.BRAM_ADDRBWRADDRL5->>BRAM_UTURN_ADDRBWRADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL5" + }, + "BRAM_R.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_3" + }, + "BRAM_R.BRAM_ADDRARDADDRL1->>BRAM_FIFO36_ADDRARDADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL1" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2" + }, + "BRAM_R.BRAM_ADDRBWRADDRL2->>BRAM_FIFO36_ADDRBWRADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL2" + }, + "BRAM_R.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU2->>BRAM_UTURN_ADDRBWRADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU2" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_2" + }, + "BRAM_R.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI3" + }, + "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_CASCOUT_ADDRARDADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU10" + }, + "BRAM_R.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_3" + }, + "BRAM_R.BRAM_ADDRARDADDRU11->>BRAM_UTURN_ADDRARDADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU11" + }, + "BRAM_R.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU1" + }, + "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_UTURN_ADDRBWRADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU1" + }, + "BRAM_R.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { + "can_invert": "0", + "src_wire": "BRAM_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKBWRCLKL" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7" + }, + "BRAM_R.BRAM_ADDRARDADDRL3->>BRAM_FIFO36_ADDRARDADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL3" + }, + "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_FIFO36_ADDRBWRADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU1" + }, + "BRAM_R.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_4" + }, + "BRAM_R.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_2" + }, + "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_FIFO36_ADDRBWRADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU3" + }, + "BRAM_R.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { + "can_invert": "0", + "src_wire": "BRAM_CLK1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_CLKARDCLK" + }, + "BRAM_R.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_3" + }, + "BRAM_R.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOPADOP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_1" + }, + "BRAM_R.BRAM_ADDRBWRADDRL14->>BRAM_UTURN_ADDRBWRADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL14" + }, + "BRAM_R.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_3" + }, + "BRAM_R.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_1" + }, + "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_CASCOUT_ADDRBWRADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU3" + }, + "BRAM_R.BRAM_ADDRARDADDRL8->>BRAM_FIFO18_ADDRARDADDR7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR7" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3" + }, + "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_RAMB18_ADDRBWRADDR9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR9" + }, + "BRAM_R.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_4" + }, + "BRAM_R.BRAM_ADDRARDADDRL11->>BRAM_UTURN_ADDRARDADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL11" + }, + "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI2" + }, + "BRAM_R.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX46_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS12" + }, + "BRAM_R.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4" + }, + "BRAM_R.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_2" + }, + "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI13" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ECCPARITY1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_3" + }, + "BRAM_R.BRAM_IMUX37_1->BRAM_R_IMUX_ADDRBWRADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX37_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL4" + }, + "BRAM_R.BRAM_ADDRARDADDRL3->>BRAM_FIFO18_ADDRARDADDR2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR2" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_4" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_2" + }, + "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL4" + }, + "BRAM_R.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_2" + }, + "BRAM_R.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU3" + }, + "BRAM_R.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX36_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS10" + }, + "BRAM_R.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { + "can_invert": "0", + "src_wire": "BRAM_CTRL1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM" + }, + "BRAM_R.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_EMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_2" + }, + "BRAM_R.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_2" + }, + "BRAM_R.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_SBITERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_2" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6" + }, + "BRAM_R.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX8_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU0" + }, + "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { + "can_invert": "0", + "src_wire": "BRAM_CTRL0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMBL" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_4" + }, + "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_UTURN_ADDRARDADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU0" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_0" + }, + "BRAM_R.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { + "can_invert": "0", + "src_wire": "BRAM_CLK1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B14_1" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU14" + }, + "BRAM_R.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS8" + }, + "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_CASCOUT_ADDRARDADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU8" + }, + "BRAM_R.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOPADOPL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_1" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14" + }, + "BRAM_R.BRAM_ADDRBWRADDRL12->>BRAM_FIFO18_ADDRBWRADDR11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR11" + }, + "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA1" + }, + "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_FIFO36_ADDRBWRADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU7" + }, + "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_CASCOUT_ADDRBWRADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU7" + }, + "BRAM_R.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10" + }, + "BRAM_R.BRAM_ADDRBWRADDRU14->>BRAM_FIFO36_ADDRBWRADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU14" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10" + }, + "BRAM_R.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX11_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU13" + }, + "BRAM_R.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { + "can_invert": "0", + "src_wire": "BRAM_CLK1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK" + }, + "BRAM_R.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { + "can_invert": "0", + "src_wire": "BRAM_IMUX11_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_REGCEAREGCE" + }, + "BRAM_R.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_4" + }, + "BRAM_R.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOPADOPU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_3" + }, + "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL3" + }, + "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL1" + }, + "BRAM_R.BRAM_IMUX30_3->BRAM_R_IMUX_ADDRBWRADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU14" + }, + "BRAM_R.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_0" + }, + "BRAM_R.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX23_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI8" + }, + "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2" + }, + "BRAM_R.BRAM_IMUX23_1->BRAM_R_IMUX_ADDRARDADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX23_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL13" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU3" + }, + "BRAM_R.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS8" + }, + "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_FIFO36_ADDRARDADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU0" + }, + "BRAM_R.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { + "can_invert": "0", + "src_wire": "BRAM_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGBU" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0" + }, + "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_CASCOUT_ADDRARDADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU2" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU13" + }, + "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12" + }, + "BRAM_R.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS3" + }, + "BRAM_R.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX14_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU5" + }, + "BRAM_R.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_0" + }, + "BRAM_R.BRAM_ADDRARDADDRL13->>BRAM_UTURN_ADDRARDADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL13" + }, + "BRAM_R.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_4" + }, + "BRAM_R.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOPBDOPU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_3" + }, + "BRAM_R.BRAM_ADDRBWRADDRL14->>BRAM_FIFO36_ADDRBWRADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL14" + }, + "BRAM_R.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX46_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE7" + }, + "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { + "can_invert": "0", + "src_wire": "BRAM_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGBL" + }, + "BRAM_R.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX13_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI14" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0" + }, + "BRAM_R.BRAM_IMUX12_2->BRAM_R_IMUX_ADDRARDADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX12_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU10" + }, + "BRAM_R.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_3" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ECCPARITY2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_2" + }, + "BRAM_R.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU3" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2" + }, + "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL12" + }, + "BRAM_R.BRAM_ADDRBWRADDRU6->>BRAM_RAMB18_ADDRBWRADDR5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR5" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6" + }, + "BRAM_R.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN3" + }, + "BRAM_R.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { + "can_invert": "0", + "src_wire": "BRAM_IMUX3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF" + }, + "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_RAMB18_ADDRARDADDR11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR11" + }, + "BRAM_R.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX22_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU7" + }, + "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI7" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU6" + }, + "BRAM_R.BRAM_IMUX36_2->BRAM_R_IMUX_ADDRBWRADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX36_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL10" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_TSTOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_0" + }, + "BRAM_R.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI9" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12" + }, + "BRAM_R.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { + "can_invert": "0", + "src_wire": "BRAM_CLK0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKARDCLKL" + }, + "BRAM_R.BRAM_ADDRARDADDRU10->>BRAM_RAMB18_ADDRARDADDR9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR9" + }, + "BRAM_R.BRAM_IMUX14_3->BRAM_R_IMUX_ADDRARDADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX14_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU14" + }, + "BRAM_R.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_4" + }, + "BRAM_R.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU2" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_4" + }, + "BRAM_R.BRAM_ADDRBWRADDRL7->>BRAM_FIFO36_ADDRBWRADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL7" + }, + "BRAM_R.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX17_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI12" + }, + "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { + "can_invert": "0", + "src_wire": "BRAM_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTREGB" + }, + "BRAM_R.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI11" + }, + "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_FIFO36_ADDRBWRADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU10" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU9" + }, + "BRAM_R.BRAM_IMUX13_1->BRAM_R_IMUX_ADDRARDADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU4" }, "BRAM_R.BRAM_ADDRARDADDRL13->>BRAM_FIFO36_ADDRARDADDRL13": { "can_invert": "0", - "dst_wire": "BRAM_FIFO36_ADDRARDADDRL13", - "is_directional": "1", "src_wire": "BRAM_ADDRARDADDRL13", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL13" + }, + "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI1" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL7" + }, + "BRAM_R.BRAM_ADDRBWRADDRU1->>BRAM_CASCOUT_ADDRBWRADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU1" + }, + "BRAM_R.BRAM_ADDRARDADDRL12->>BRAM_UTURN_ADDRARDADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL12" + }, + "BRAM_R.BRAM_ADDRBWRADDRL0->>BRAM_FIFO18_ADDRBTIEHIGH0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ECCPARITY7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_3" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5" + }, + "BRAM_R.BRAM_ADDRARDADDRU12->>BRAM_CASCOUT_ADDRARDADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU12" + }, + "BRAM_R.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU14" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL4" + }, + "BRAM_R.BRAM_ADDRARDADDRL5->>BRAM_FIFO18_ADDRARDADDR4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR4" + }, + "BRAM_R.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { + "can_invert": "0", + "src_wire": "BRAM_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ENBWREN" + }, + "BRAM_R.BRAM_ADDRBWRADDRL9->>BRAM_FIFO18_ADDRBWRADDR8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR8" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1" + }, + "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPADIPL0" + }, + "BRAM_R.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX42_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPADIP0" + }, + "BRAM_R.BRAM_ADDRBWRADDRL13->>BRAM_FIFO36_ADDRBWRADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL13" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_2" + }, + "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI2" + }, + "BRAM_R.BRAM_IMUX21_1->BRAM_R_IMUX_ADDRARDADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL4" + }, + "BRAM_R.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { + "can_invert": "0", + "src_wire": "BRAM_FAN1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU4" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL12" + }, + "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15" + }, + "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI4" + }, + "BRAM_R.BRAM_ADDRARDADDRL6->>BRAM_FIFO36_ADDRARDADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL6" + }, + "BRAM_R.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX16_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI4" + }, + "BRAM_R.BRAM_IMUX26_3->BRAM_R_IMUX_ADDRBWRADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU3" + }, + "BRAM_R.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI12" + }, + "BRAM_R.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX24_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI0" + }, + "BRAM_R.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX11_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT1" + }, + "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI10" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU6" + }, + "BRAM_R.BRAM_IMUX18_3->BRAM_R_IMUX_ADDRARDADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX18_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL3" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_1" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU2" + }, + "BRAM_R.BRAM_ADDRBWRADDRL4->>BRAM_FIFO36_ADDRBWRADDRL4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL4" + }, + "BRAM_R.BRAM_IMUX36_1->BRAM_R_IMUX_ADDRBWRADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL8" + }, + "BRAM_R.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX18_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI5" + }, + "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_CASCOUT_ADDRBWRADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU9" + }, + "BRAM_R.BRAM_ADDRBWRADDRL1->>BRAM_FIFO36_ADDRBWRADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL1" + }, + "BRAM_R.BRAM_ADDRARDADDRL9->>BRAM_FIFO18_ADDRARDADDR8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR8" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9" + }, + "BRAM_R.BRAM_ADDRBWRADDRU10->>BRAM_CASCOUT_ADDRBWRADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU10" + }, + "BRAM_R.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX15_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU15" + }, + "BRAM_R.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_2" + }, + "BRAM_R.BRAM_IMUX15_1->BRAM_R_IMUX_ADDRARDADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU13" + }, + "BRAM_R.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { + "can_invert": "0", + "src_wire": "BRAM_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ENBWRENU" + }, + "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX43_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI5" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5" + }, + "BRAM_R.BRAM_ADDRBWRADDRL13->>BRAM_FIFO18_ADDRBWRADDR12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR12" + }, + "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL10" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_2" + }, + "BRAM_R.BRAM_ADDRBWRADDRL10->>BRAM_FIFO36_ADDRBWRADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL10" + }, + "BRAM_R.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { + "can_invert": "0", + "src_wire": "BRAM_CLK0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU1" + }, + "BRAM_R.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_4" + }, + "BRAM_R.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_1" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU10" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU11" + }, + "BRAM_R.BRAM_ADDRARDADDRL7->>BRAM_UTURN_ADDRARDADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL7" + }, + "BRAM_R.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX12_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU6" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13" + }, + "BRAM_R.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_FULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_2" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU9" + }, + "BRAM_R.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX32_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS6" + }, + "BRAM_R.BRAM_ADDRBWRADDRL13->>BRAM_UTURN_ADDRBWRADDRL13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL13" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_2" + }, + "BRAM_R.BRAM_ADDRARDADDRL11->>BRAM_FIFO18_ADDRARDADDR10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR10" + }, + "BRAM_R.BRAM_ADDRBWRADDRL10->>BRAM_UTURN_ADDRBWRADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL10" + }, + "BRAM_R.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI10" + }, + "BRAM_R.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_4" + }, + "BRAM_R.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_ALMOSTFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B1_2" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU2" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL14" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6" + }, + "BRAM_R.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { + "can_invert": "0", + "src_wire": "BRAM_FAN1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE4" + }, + "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { + "can_invert": "0", + "src_wire": "BRAM_CTRL0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_RSTREGARSTREG" + }, + "BRAM_R.BRAM_ADDRBWRADDRU11->>BRAM_CASCOUT_ADDRBWRADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU11" + }, + "BRAM_R.BRAM_ADDRARDADDRL10->>BRAM_FIFO18_ADDRARDADDR9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR9" + }, + "BRAM_R.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { + "can_invert": "0", + "src_wire": "BRAM_CTRL1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_RSTREGARSTREG" + }, + "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL1" + }, + "BRAM_R.BRAM_ADDRARDADDRU14->>BRAM_RAMB18_ADDRARDADDR13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR13" + }, + "BRAM_R.BRAM_IMUX12_3->BRAM_R_IMUX_ADDRARDADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU5" + }, + "BRAM_R.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX44_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS10" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11" + }, + "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI4" + }, + "BRAM_R.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_EMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_2" + }, + "BRAM_R.BRAM_ADDRBWRADDRL0->>BRAM_UTURN_ADDRBWRADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL0" + }, + "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI0" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ECCPARITY6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B21_3" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9" + }, + "BRAM_R.BRAM_ADDRARDADDRU5->>BRAM_RAMB18_ADDRARDADDR4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR4" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_1" + }, + "BRAM_R.BRAM_ADDRBWRADDRU13->>BRAM_FIFO36_ADDRBWRADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU13" + }, + "BRAM_R.BRAM_IMUX10_3->BRAM_R_IMUX_ADDRARDADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU3" + }, + "BRAM_R.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT5" + }, + "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL6" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3" + }, + "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI11" + }, + "BRAM_R.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_4" + }, + "BRAM_R.BRAM_ADDRARDADDRU4->>BRAM_RAMB18_ADDRARDADDR3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR3" + }, + "BRAM_R.BRAM_ADDRBWRADDRL11->>BRAM_UTURN_ADDRBWRADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL11" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_2" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ECCPARITY3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_2" + }, + "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_UTURN_ADDRARDADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU6" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL0" + }, + "BRAM_R.BRAM_IMUX28_3->BRAM_R_IMUX_ADDRBWRADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU5" + }, + "BRAM_R.BRAM_ADDRARDADDRL14->>BRAM_FIFO18_ADDRARDADDR13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR13" + }, + "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX37_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL2" + }, + "BRAM_R.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_1" + }, + "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL2" + }, + "BRAM_R.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX43_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIPBDIP0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2" + }, + "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAL2" + }, + "BRAM_R.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX17_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU12" + }, + "BRAM_R.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_2" + }, + "BRAM_R.BRAM_ADDRARDADDRL7->>BRAM_FIFO18_ADDRARDADDR6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR6" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_0" + }, + "BRAM_R.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { + "can_invert": "0", + "src_wire": "BRAM_CTRL1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU" + }, + "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA0" + }, + "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX41_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIL15" + }, + "BRAM_R.BRAM_ADDRARDADDRU1->>BRAM_CASCOUT_ADDRARDADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU1" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL10" + }, + "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_WEA2" + }, + "BRAM_R.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { + "can_invert": "0", + "src_wire": "BRAM_FAN5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU0" + }, + "BRAM_R.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU5" + }, + "BRAM_R.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_0" + }, + "BRAM_R.BRAM_ADDRBWRADDRU12->>BRAM_RAMB18_ADDRBWRADDR11": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR11" + }, + "BRAM_R.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU1" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU7" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_4" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14" + }, + "BRAM_R.BRAM_ADDRBWRADDRL9->>BRAM_FIFO36_ADDRBWRADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL9" + }, + "BRAM_R.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOL10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_0" + }, + "BRAM_R.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOPADOP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_3" + }, + "BRAM_R.BRAM_ADDRBWRADDRL6->>BRAM_UTURN_ADDRBWRADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL6" + }, + "BRAM_R.BRAM_IMUX22_3->BRAM_R_IMUX_ADDRARDADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL14" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU1" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL12" + }, + "BRAM_R.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX12_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI6" + }, + "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_UTURN_ADDRBWRADDRU9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU9" + }, + "BRAM_R.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX19_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI13" + }, + "BRAM_R.BRAM_ADDRARDADDRL5->>BRAM_UTURN_ADDRARDADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL5" + }, + "BRAM_R.BRAM_IMUX36_3->BRAM_R_IMUX_ADDRBWRADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX36_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL5" + }, + "BRAM_R.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS2" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL8" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU13" + }, + "BRAM_R.BRAM_IMUX19_1->BRAM_R_IMUX_ADDRARDADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX19_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL2" + }, + "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_UTURN_ADDRBWRADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU7" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU8" + }, + "BRAM_R.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTIN2" + }, + "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI11" + }, + "BRAM_R.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_4" + }, + "BRAM_R.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX29_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT11" + }, + "BRAM_R.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOBDO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3" + }, + "BRAM_R.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU11" + }, + "BRAM_R.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOPADOPU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B15_3" + }, + "BRAM_R.BRAM_ADDRBWRADDRL7->>BRAM_FIFO18_ADDRBWRADDR6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR6" + }, + "BRAM_R.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT2" + }, + "BRAM_R.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOPBDOP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_3" + }, + "BRAM_R.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX27_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTCNT9" + }, + "BRAM_R.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOPBDOPL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B22_1" + }, + "BRAM_R.BRAM_ADDRBWRADDRU0->>BRAM_RAMB18_ADDRBTIEHIGH0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH0" + }, + "BRAM_R.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEAU1" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL2" + }, + "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL15" + }, + "BRAM_R.BRAM_ADDRARDADDRL13->>BRAM_FIFO18_ADDRARDADDR12": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRARDADDR12" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU0" + }, + "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI6" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B16_4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL2" + }, + "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { + "can_invert": "0", + "src_wire": "BRAM_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL11" + }, + "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL14" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5" + }, + "BRAM_R.BRAM_ADDRARDADDRL9->>BRAM_UTURN_ADDRARDADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL9" + }, + "BRAM_R.BRAM_ADDRBWRADDRL5->>BRAM_FIFO18_ADDRBWRADDR4": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR4" + }, + "BRAM_R.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B17_0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU14" + }, + "BRAM_R.BRAM_IMUX9_1->BRAM_R_IMUX_ADDRARDADDRU0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU0" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10" + }, + "BRAM_R.BRAM_ADDRBWRADDRU7->>BRAM_RAMB18_ADDRBWRADDR6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRBWRADDR6" + }, + "BRAM_R.BRAM_ADDRBWRADDRL2->>BRAM_FIFO18_ADDRBWRADDR1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBWRADDR1" + }, + "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { + "can_invert": "0", + "src_wire": "BRAM_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI3" + }, + "BRAM_R.BRAM_ADDRARDADDRL14->>BRAM_UTURN_ADDRARDADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRL14" + }, + "BRAM_R.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_WRCOUNT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B9_3" + }, + "BRAM_R.BRAM_IMUX35_1->BRAM_R_IMUX_ADDRBWRADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL2" + }, + "BRAM_R.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B8_0" + }, + "BRAM_R.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI2" + }, + "BRAM_R.BRAM_ADDRARDADDRU0->>BRAM_RAMB18_ADDRATIEHIGH0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH0" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU12" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL11" + }, + "BRAM_R.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIADIU0" + }, + "BRAM_R.BRAM_IMUX29_3->BRAM_R_IMUX_ADDRBWRADDRU12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU12" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL9" + }, + "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI9" + }, + "BRAM_R.BRAM_IMUX35_3->BRAM_R_IMUX_ADDRBWRADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX35_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL9" + }, + "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_UTURN_ADDRBWRADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU5" + }, + "BRAM_R.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B2_4" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B12_0" + }, + "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { + "can_invert": "0", + "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15" + }, + "BRAM_R.BRAM_ADDRARDADDRL2->>BRAM_FIFO36_ADDRARDADDRL2": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL2" + }, + "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI10" + }, + "BRAM_R.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOADO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B7_0" + }, + "BRAM_R.BRAM_IMUX17_1->BRAM_R_IMUX_ADDRARDADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX17_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL0" + }, + "BRAM_R.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B20_1" + }, + "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_UTURN_ADDRARDADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRARDADDRU8" + }, + "BRAM_R.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B6_1" + }, + "BRAM_R.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX43_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIPBDIPU0" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL5" + }, + "BRAM_R.BRAM_ADDRBWRADDRU5->>BRAM_FIFO36_ADDRBWRADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU5" + }, + "BRAM_R.BRAM_IMUX20_2->BRAM_R_IMUX_ADDRARDADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL10" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL10" + }, + "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_UTURN_ADDRBWRADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU8" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU7" + }, + "BRAM_R.BRAM_IMUX32_3->BRAM_R_IMUX_ADDRBWRADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX32_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL6" + }, + "BRAM_R.BRAM_IMUX12_1->BRAM_R_IMUX_ADDRARDADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU8" + }, + "BRAM_R.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { + "can_invert": "0", + "src_wire": "BRAM_FAN5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_WEBWE0" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_TSTOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B18_0" + }, + "BRAM_R.BRAM_ADDRARDADDRU2->>BRAM_RAMB18_ADDRARDADDR1": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR1" + }, + "BRAM_R.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIBDI6" + }, + "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { + "can_invert": "0", + "src_wire": "BRAM_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_REGCEAREGCE" + }, + "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { + "can_invert": "0", + "src_wire": "BRAM_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIBDI14" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL0" + }, + "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL13" + }, + "BRAM_R.BRAM_ADDRARDADDRL0->>BRAM_FIFO36_ADDRARDADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRL0" + }, + "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_FIFO36_ADDRARDADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU8" + }, + "BRAM_R.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIU9" + }, + "BRAM_R.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B0_3" + }, + "BRAM_R.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { + "can_invert": "0", + "src_wire": "BRAM_IMUX15_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_DIADI8" + }, + "BRAM_R.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B19_4" + }, + "BRAM_R.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOBDO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_2" + }, + "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { + "can_invert": "0", + "src_wire": "BRAM_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_DIBDIL12" + }, + "BRAM_R.BRAM_ADDRARDADDRU7->>BRAM_FIFO36_ADDRARDADDRU7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU7" + }, + "BRAM_R.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_DOPBDOP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_1" + }, + "BRAM_R.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_ECCPARITY4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B10_2" + }, + "BRAM_R.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO18_RDCOUNT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B3_1" + }, + "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { + "can_invert": "0", + "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1" + }, + "BRAM_R.BRAM_IMUX33_3->BRAM_R_IMUX_ADDRBWRADDRL7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX33_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL7" + }, + "BRAM_R.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { + "can_invert": "0", + "src_wire": "BRAM_CLK1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_CLKARDCLKU" + }, + "BRAM_R.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { + "can_invert": "0", + "src_wire": "BRAM_CTRL1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU" + }, + "BRAM_R.BRAM_ADDRARDADDRU8->>BRAM_RAMB18_ADDRARDADDR7": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_RAMB18_ADDRARDADDR7" + }, + "BRAM_R.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTWROS6" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL6" + }, + "BRAM_R.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_RDCOUNT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_1" + }, + "BRAM_R.BRAM_ADDRBWRADDRU3->>BRAM_UTURN_ADDRBWRADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_UTURN_ADDRBWRADDRU3" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU5" + }, + "BRAM_R.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B13_4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU10" + }, + "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { + "can_invert": "0", + "src_wire": "BRAM_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL0" + }, + "BRAM_R.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOBDOL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B4_0" + }, + "BRAM_R.BRAM_IMUX27_1->BRAM_R_IMUX_ADDRBWRADDRU2": { + "can_invert": "0", + "src_wire": "BRAM_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU2" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRL14" + }, + "BRAM_R.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { + "can_invert": "0", + "src_wire": "BRAM_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF" + }, + "BRAM_R.BRAM_IMUX29_1->BRAM_R_IMUX_ADDRBWRADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU4" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU8" + }, + "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { + "can_invert": "0", + "src_wire": "BRAM_IMUX22_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL5" + }, + "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { + "can_invert": "0", + "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU3" + }, + "BRAM_R.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { + "can_invert": "0", + "src_wire": "BRAM_IMUX33_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_TSTRDOS7" + }, + "BRAM_R.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_DOADOU10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_3" + }, + "BRAM_R.BRAM_ADDRARDADDRU13->>BRAM_CASCOUT_ADDRARDADDRU13": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU13" + }, + "BRAM_R.BRAM_IMUX19_3->BRAM_R_IMUX_ADDRARDADDRL9": { + "can_invert": "0", + "src_wire": "BRAM_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL9" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL3" + }, + "BRAM_R.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX30_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEU6" + }, + "BRAM_R.BRAM_ADDRBWRADDRL0->>BRAM_FIFO36_ADDRBWRADDRL0": { + "can_invert": "0", + "src_wire": "BRAM_ADDRBWRADDRL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL0" + }, + "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { + "can_invert": "0", + "src_wire": "BRAM_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO18_DIADI13" + }, + "BRAM_R.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_WRCOUNT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B23_4" + }, + "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRU4" + }, + "BRAM_R.BRAM_ADDRARDADDRU6->>BRAM_FIFO36_ADDRARDADDRU6": { + "can_invert": "0", + "src_wire": "BRAM_ADDRARDADDRU6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_ADDRARDADDRU6" + }, + "BRAM_R.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { + "can_invert": "0", + "src_wire": "BRAM_RAMB18_DOADO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B5_4" + }, + "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { + "can_invert": "0", + "src_wire": "BRAM_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_FIFO36_WEBWEL6" + }, + "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { + "can_invert": "0", + "src_wire": "BRAM_R_IMUX_ADDRARDADDRU4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRARDADDRU4" + }, + "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { + "can_invert": "0", + "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_ADDRBWRADDRL1" + }, + "BRAM_R.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { + "can_invert": "0", + "src_wire": "BRAM_FIFO36_TSTOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRAM_LOGIC_OUTS_B11_4" } }, - "tile_type": "BRAM_R" + "wires": [ + "BRAM_SW4A1_4", + "BRAM_BYP7_2", + "BRAM_EE4BEG2_0", + "BRAM_IMUX25_0", + "BRAM_IMUX2_UTURN_0", + "BRAM_FIFO18_DOBDO8", + "BRAM_IMUX25_2", + "BRAM_LOGIC_OUTS_B14_0", + "BRAM_RAMB18_DOBDO10", + "BRAM_FAN0_1", + "BRAM_EE2BEG1_3", + "BRAM_RAMB18_ADDRARDADDR4", + "BRAM_IMUX47_0", + "BRAM_RAMB18_DIBDI4", + "BRAM_R_IMUX_ADDRARDADDRU2", + "BRAM_IMUX31_UTURN_2", + "BRAM_NE4BEG2_0", + "BRAM_IMUX25_4", + "BRAM_R_IMUX_ADDRBWRADDRL8", + "BRAM_IMUX23_UTURN_3", + "BRAM_R_IMUX_ADDRBWRADDRL1", + "BRAM_FAN6_2", + "BRAM_LOGIC_OUTS_B21_4", + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_NW4END3_2", + "BRAM_CASCOUT_ADDRBWRADDRU11", + "BRAM_FAN7_1", + "BRAM_UTURN_ADDRBWRADDRL4", + "BRAM_SE4BEG1_1", + "BRAM_FIFO36_DIADIU12", + "BRAM_FIFO36_DIBDIL5", + "BRAM_IMUX1_3", + "BRAM_IMUX3_UTURN_4", + "BRAM_SE2A1_1", + "BRAM_ADDRBWRADDRL7", + "BRAM_FIFO36_DOADOL10", + "BRAM_LOGIC_OUTS_B1_2", + "BRAM_EE2A1_4", + "BRAM_FIFO18_WRCOUNT3", + "BRAM_WW2END1_4", + "BRAM_RAMB18_REGCLKARDRCLK", + "BRAM_IMUX5_UTURN_0", + "BRAM_IMUX35_UTURN_2", + "BRAM_IMUX28_UTURN_4", + "BRAM_UTURN_ADDRARDADDRL4", + "BRAM_IMUX27_0", + "BRAM_IMUX36_UTURN_1", + "BRAM_WW4B2_4", + "BRAM_IMUX2_1", + "BRAM_FAN0_2", + "BRAM_IMUX12_UTURN_3", + "BRAM_EE2A1_1", + "BRAM_WR1END0_0", + "BRAM_IMUX47_UTURN_0", + "BRAM_FIFO36_WEAL3", + "BRAM_FIFO18_RDCOUNT9", + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRAM_RAMB18_DIPADIP1", + "BRAM_IMUX35_4", + "BRAM_FIFO18_ADDRBWRADDR7", + "BRAM_LH6_3", + "BRAM_EL1BEG1_4", + "BRAM_SE4BEG2_4", + "BRAM_LH7_4", + "BRAM_IMUX41_2", + "BRAM_FIFO36_DIADIL10", + "BRAM_FIFO36_DOPADOPU1", + "BRAM_CTRL1_1", + "BRAM_WW4C1_4", + "BRAM_FIFO36_RSTRAMBL", + "BRAM_FIFO36_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU2", + "BRAM_FIFO36_TSTRDOS6", + "BRAM_FIFO36_REGCEAREGCEL", + "BRAM_IMUX44_UTURN_1", + "BRAM_FIFO36_DOPADOPU0", + "BRAM_FAN5_3", + "BRAM_EE4BEG0_4", + "BRAM_CASCOUT_ADDRBWRADDRU14", + "BRAM_WW4C3_0", + "BRAM_EE2A2_0", + "BRAM_IMUX44_4", + "BRAM_FIFO36_DOADOU1", + "BRAM_EE4BEG3_2", + "BRAM_IMUX25_1", + "BRAM_FIFO18_WEBWE7", + "BRAM_IMUX10_2", + "BRAM_IMUX23_0", + "BRAM_FIFO18_ADDRBWRADDR4", + "BRAM_R_IMUX_ADDRBWRADDRL9", + "BRAM_IMUX43_UTURN_4", + "BRAM_FIFO36_TSTCNT1", + "BRAM_LOGIC_OUTS_B9_0", + "BRAM_IMUX5_4", + "BRAM_FIFO36_ADDRBWRADDRL5", + "BRAM_IMUX6_3", + "BRAM_FIFO36_ADDRBWRADDRU0", + "BRAM_FAN2_4", + "BRAM_RAMB18_ENBWREN", + "BRAM_WW4A3_1", + "BRAM_SW2A0_0", + "BRAM_IMUX25_UTURN_3", + "BRAM_R_IMUX_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU5", + "BRAM_NE2A2_2", + "BRAM_LOGIC_OUTS_B20_4", + "BRAM_FIFO18_DOBDO5", + "BRAM_WW4C1_0", + "BRAM_BYP2_0", + "BRAM_FIFO18_DIBDI10", + "BRAM_IMUX45_UTURN_3", + "BRAM_FIFO18_ADDRBWRADDR0", + "BRAM_IMUX36_UTURN_2", + "BRAM_CASCOUT_ADDRARDADDRU6", + "BRAM_FIFO18_DIBDI12", + "BRAM_EE2BEG2_4", + "BRAM_PMVBRAM_SELECT2", + "BRAM_IMUX23_UTURN_0", + "BRAM_IMUX25_UTURN_0", + "BRAM_IMUX14_2", + "BRAM_WL1END0_1", + "BRAM_IMUX15_3", + "BRAM_FIFO18_DIBDI3", + "BRAM_RAMB18_DOBDO13", + "BRAM_EE4A1_0", + "BRAM_FIFO36_TSTWROS7", + "BRAM_RAMB18_DOBDO14", + "BRAM_SW4END2_0", + "BRAM_IMUX47_UTURN_1", + "BRAM_RAMB18_RDCOUNT4", + "BRAM_EE4B0_3", + "BRAM_IMUX17_UTURN_1", + "BRAM_CASCOUT_ADDRBWRADDRU1", + "BRAM_FIFO36_RDCOUNT12", + "BRAM_FIFO18_ADDRARDADDR5", + "BRAM_FAN6_3", + "BRAM_FIFO36_TSTWROS9", + "BRAM_LOGIC_OUTS_B0_3", + "BRAM_UTURN_ADDRBWRADDRU3", + "BRAM_WL1END0_0", + "BRAM_WW4END1_1", + "BRAM_RAMB18_WRERR", + "BRAM_FIFO36_DOADOU4", + "BRAM_WW2A3_2", + "BRAM_EE4A1_3", + "BRAM_FIFO36_DIADIL5", + "BRAM_FIFO18_ADDRARDADDR10", + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRAM_ADDRBWRADDRU2", + "BRAM_IMUX30_UTURN_2", + "BRAM_WW2A2_4", + "BRAM_IMUX22_2", + "BRAM_IMUX26_UTURN_2", + "BRAM_CASCOUT_ADDRARDADDRU9", + "BRAM_FIFO36_TSTOUT0", + "BRAM_SE4BEG0_4", + "BRAM_IMUX24_UTURN_1", + "BRAM_FIFO36_ADDRARDADDRU2", + "BRAM_UTURN_ADDRARDADDRL12", + "BRAM_IMUX34_2", + "BRAM_R_IMUX_ADDRARDADDRU10", + "BRAM_RAMB18_DIADI5", + "BRAM_BYP0_2", + "BRAM_FIFO36_WEAL1", + "BRAM_FIFO36_ADDRBWRADDRL3", + "BRAM_ADDRARDADDRU11", + "BRAM_PMVBRAM_SELECT1", + "BRAM_FIFO36_SBITERR", + "BRAM_NW4A0_0", + "BRAM_RAMB18_DOADO10", + "BRAM_UTURN_ADDRARDADDRL15", + "BRAM_RAMB18_EMPTY", + "BRAM_IMUX43_UTURN_1", + "BRAM_IMUX42_1", + "BRAM_NE4C2_2", + "BRAM_NE4BEG0_2", + "BRAM_FIFO36_TSTIN1", + "BRAM_FIFO36_RDCOUNT11", + "BRAM_NE4BEG1_2", + "BRAM_IMUX5_UTURN_1", + "BRAM_NW4A1_1", + "BRAM_UTURN_ADDRARDADDRL2", + "BRAM_FIFO36_DIPADIPU1", + "BRAM_IMUX47_4", + "BRAM_FIFO36_DOBDOU4", + "BRAM_IMUX8_4", + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRAM_RAMB18_DOADO12", + "BRAM_IMUX38_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU14", + "BRAM_FIFO18_RDCOUNT10", + "BRAM_FAN6_1", + "BRAM_FIFO36_DIADIL6", + "BRAM_LH12_2", + "BRAM_NE2A0_4", + "BRAM_FIFO36_WEBWEU2", + "BRAM_EE2A1_2", + "BRAM_IMUX2_UTURN_1", + "BRAM_FIFO36_TSTFLAGIN", + "BRAM_FIFO18_DIADI0", + "BRAM_IMUX20_3", + "BRAM_IMUX18_UTURN_2", + "BRAM_IMUX6_UTURN_1", + "BRAM_FIFO36_WRCOUNT3", + "BRAM_FIFO36_ADDRBWRADDRL11", + "BRAM_WW4A2_1", + "BRAM_SE4C2_3", + "BRAM_NE2A0_0", + "BRAM_RAMB18_WEBWE4", + "BRAM_CASCINBOT_ADDRARDADDRU11", + "BRAM_NE2A2_0", + "BRAM_FIFO18_RSTREGB", + "BRAM_FIFO18_DIBDI1", + "BRAM_LOGIC_OUTS_B12_1", + "BRAM_IMUX10_3", + "BRAM_EE4B2_1", + "BRAM_SW2A0_3", + "BRAM_FIFO18_ADDRBWRADDR12", + "BRAM_RAMB18_WRCOUNT4", + "BRAM_EE2BEG0_0", + "BRAM_IMUX2_2", + "BRAM_SW2A2_3", + "BRAM_FIFO36_ADDRARDADDRU8", + "BRAM_IMUX1_0", + "BRAM_RAMB18_WEBWE1", + "BRAM_RAMB18_RDCOUNT11", + "BRAM_FIFO36_ADDRARDADDRU7", + "BRAM_RAMB18_RDCOUNT8", + "BRAM_UTURN_ADDRARDADDRL14", + "BRAM_WL1END2_4", + "BRAM_FIFO18_RDCOUNT1", + "BRAM_EE4C1_1", + "BRAM_IMUX6_4", + "BRAM_IMUX10_4", + "BRAM_IMUX10_0", + "BRAM_FIFO36_DIADIL3", + "BRAM_IMUX14_UTURN_3", + "BRAM_IMUX28_1", + "BRAM_IMUX20_4", + "BRAM_LH2_4", + "BRAM_BYP3_1", + "BRAM_FIFO36_TSTWROS3", + "BRAM_FIFO36_DIADIU13", + "BRAM_IMUX14_0", + "BRAM_RAMB18_RDCOUNT0", + "BRAM_SW4A3_1", + "BRAM_FIFO36_DOBDOL8", + "BRAM_IMUX29_0", + "BRAM_FIFO36_DIADIU5", + "BRAM_IMUX37_0", + "BRAM_IMUX34_1", + "BRAM_RAMB18_DIBDI13", + "BRAM_LOGIC_OUTS_B2_2", + "BRAM_NW4END1_4", + "BRAM_IMUX36_0", + "BRAM_SW4A3_4", + "BRAM_CASCINBOT_ADDRARDADDRU7", + "BRAM_BYP3_4", + "BRAM_IMUX12_UTURN_2", + "BRAM_WW2END2_2", + "BRAM_NW4END3_4", + "BRAM_ER1BEG0_3", + "BRAM_IMUX21_UTURN_1", + "BRAM_NW4END1_0", + "BRAM_SE4C3_2", + "BRAM_FIFO36_DIADIL4", + "BRAM_RAMB18_DIBDI11", + "BRAM_BYP2_3", + "BRAM_WL1END1_0", + "BRAM_RAMB18_DOADO7", + "BRAM_EL1BEG2_1", + "BRAM_FIFO18_DIADI7", + "BRAM_NW2A2_0", + "BRAM_RAMB18_WRCOUNT11", + "BRAM_IMUX39_1", + "BRAM_LH9_0", + "BRAM_LOGIC_OUTS_B5_0", + "BRAM_LOGIC_OUTS_B20_1", + "BRAM_IMUX26_UTURN_0", + "BRAM_FIFO18_WEBWE6", + "BRAM_FIFO36_ADDRBWRADDRU1", + "BRAM_IMUX8_2", + "BRAM_FIFO18_DIBDI6", + "BRAM_FIFO36_DOADOU3", + "BRAM_LOGIC_OUTS_B8_2", + "BRAM_FIFO36_ADDRBWRADDRU9", + "BRAM_R_IMUX_ADDRARDADDRL7", + "BRAM_IMUX22_0", + "BRAM_LOGIC_OUTS_B16_4", + "BRAM_IMUX23_1", + "BRAM_FIFO36_DOADOU13", + "BRAM_WW4END3_4", + "BRAM_IMUX41_UTURN_0", + "BRAM_FIFO18_ADDRBWRADDR11", + "BRAM_LOGIC_OUTS_B7_4", + "BRAM_IMUX15_2", + "BRAM_EE2A2_4", + "BRAM_EE2BEG3_2", + "BRAM_LOGIC_OUTS_B7_2", + "BRAM_IMUX9_2", + "BRAM_FIFO36_DIBDIL6", + "BRAM_IMUX23_4", + "BRAM_LOGIC_OUTS_B0_2", + "BRAM_NW2A2_3", + "BRAM_LH12_0", + "BRAM_WW4A1_3", + "BRAM_FIFO18_RDCOUNT6", + "BRAM_CASCINBOT_ADDRBWRADDRU2", + "BRAM_FIFO36_DOPBDOPU0", + "BRAM_WW4END3_3", + "BRAM_RAMB18_DIADI11", + "BRAM_NE2A1_1", + "BRAM_BYP5_4", + "BRAM_RAMB18_DIBDI12", + "BRAM_FIFO18_DOADO2", + "BRAM_IMUX40_UTURN_2", + "BRAM_FIFO36_ADDRARDADDRL7", + "BRAM_ADDRARDADDRU14", + "BRAM_WW2A3_1", + "BRAM_IMUX16_UTURN_3", + "BRAM_IMUX38_UTURN_4", + "BRAM_RAMB18_ALMOSTFULL", + "BRAM_RAMB18_RSTREGARSTREG", + "BRAM_FIFO36_ADDRARDADDRL9", + "BRAM_BYP2_1", + "BRAM_NE4C2_1", + "BRAM_LH8_1", + "BRAM_RAMB18_DOPADOP0", + "BRAM_FIFO18_RSTRAMARSTRAM", + "BRAM_IMUX8_3", + "BRAM_RAMB18_DOADO8", + "BRAM_FIFO36_ADDRBWRADDRL4", + "BRAM_RAMB18_RSTRAMB", + "BRAM_IMUX23_UTURN_2", + "BRAM_LH4_0", + "BRAM_FIFO18_DIPBDIP0", + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRAM_CLK1_4", + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_IMUX0_3", + "BRAM_WW4A3_3", + "BRAM_CASCOUT_ADDRBWRADDRU2", + "BRAM_RAMB18_DIADI10", + "BRAM_FIFO36_DOBDOL0", + "BRAM_NE4C2_3", + "BRAM_IMUX45_UTURN_0", + "BRAM_FIFO36_DOPADOPL1", + "BRAM_RAMB18_REGCEB", + "BRAM_IMUX19_0", + "BRAM_RAMB18_ADDRBWRADDR4", + "BRAM_BLOCK_OUTS_L_B3_0", + "BRAM_FIFO36_TSTWROS8", + "BRAM_IMUX29_UTURN_2", + "BRAM_SE4C0_2", + "BRAM_WW4C3_4", + "BRAM_WW4B0_0", + "BRAM_FAN7_2", + "BRAM_CASCOUT_ADDRBWRADDRU7", + "BRAM_FIFO36_DIBDIU8", + "BRAM_IMUX9_0", + "BRAM_FIFO36_INJECTSBITERR", + "BRAM_FIFO36_ADDRARDADDRL6", + "BRAM_FIFO18_DOADO0", + "BRAM_FIFO36_RDCOUNT6", + "BRAM_EE4C3_3", + "BRAM_LH7_0", + "BRAM_FIFO18_DOBDO4", + "BRAM_UTURN_ADDRBWRADDRL10", + "BRAM_IMUX4_UTURN_1", + "BRAM_IMUX13_UTURN_2", + "BRAM_IMUX37_UTURN_1", + "BRAM_SW4A0_2", + "BRAM_EE4B2_2", + "BRAM_FIFO36_ADDRBWRADDRU7", + "BRAM_FIFO36_DIADIU7", + "BRAM_LH10_1", + "BRAM_FAN0_4", + "BRAM_IMUX7_0", + "BRAM_CASCOUT_ADDRARDADDRU4", + "BRAM_IMUX22_4", + "BRAM_IMUX22_UTURN_4", + "BRAM_EE2BEG3_4", + "BRAM_IMUX29_UTURN_1", + "BRAM_EE4A3_4", + "BRAM_IMUX11_2", + "BRAM_WL1END0_3", + "BRAM_IMUX11_4", + "BRAM_R_IMUX_ADDRARDADDRL6", + "BRAM_FIFO36_DOADOL8", + "BRAM_IMUX3_UTURN_1", + "BRAM_SE4C0_0", + "BRAM_RAMB18_ENARDEN", + "BRAM_RAMB18_ADDRARDADDR6", + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRAM_IMUX24_4", + "BRAM_IMUX38_3", + "BRAM_IMUX31_3", + "BRAM_SE4C3_1", + "BRAM_RAMB18_DIADI1", + "BRAM_RAMB18_ADDRBWRADDR6", + "BRAM_IMUX44_UTURN_2", + "BRAM_ADDRARDADDRU13", + "BRAM_IMUX23_UTURN_1", + "BRAM_FIFO36_DIBDIL1", + "BRAM_FIFO18_WEBWE0", + "BRAM_UTURN_ADDRBWRADDRU4", + "BRAM_IMUX0_4", + "BRAM_EE4BEG3_0", + "BRAM_CASCINBOT_ADDRARDADDRU12", + "BRAM_SE4C2_2", + "BRAM_ADDRBWRADDRL12", + "BRAM_ER1BEG1_4", + "BRAM_BYP0_0", + "BRAM_SW4A0_1", + "BRAM_IMUX40_UTURN_0", + "BRAM_CASCOUT_ADDRARDADDRU1", + "BRAM_FIFO36_WRCOUNT7", + "BRAM_SW4A3_2", + "BRAM_FAN6_0", + "BRAM_FIFO36_TSTCNT3", + "BRAM_IMUX46_2", + "BRAM_NW2A3_4", + "BRAM_FIFO36_DIBDIL0", + "BRAM_IMUX21_UTURN_2", + "BRAM_FIFO36_ADDRARDADDRL3", + "BRAM_WW2END1_3", + "BRAM_EE4B3_3", + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRAM_RAMB18_WEBWE3", + "BRAM_IMUX10_UTURN_4", + "BRAM_UTURN_ADDRARDADDRU9", + "BRAM_FIFO36_DOBDOU0", + "BRAM_SE2A0_1", + "BRAM_FAN7_0", + "BRAM_WW4B2_1", + "BRAM_IMUX46_1", + "BRAM_IMUX16_4", + "BRAM_LOGIC_OUTS_B17_2", + "BRAM_WW4A1_1", + "BRAM_ADDRBWRADDRL11", + "BRAM_IMUX37_UTURN_3", + "BRAM_EE4BEG0_2", + "BRAM_FIFO36_DIBDIL8", + "BRAM_WW2END2_3", + "BRAM_NW2A1_4", + "BRAM_CASCINBOT_ADDRARDADDRU14", + "BRAM_FIFO36_DIBDIL12", + "BRAM_FIFO18_DOADO6", + "BRAM_IMUX8_1", + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRAM_FIFO36_TSTCNT12", + "BRAM_WR1END0_3", + "BRAM_NW4A2_2", + "BRAM_IMUX46_0", + "BRAM_FIFO36_TSTWROS2", + "BRAM_IMUX26_UTURN_3", + "BRAM_IMUX36_UTURN_3", + "BRAM_FIFO36_RDCOUNT3", + "BRAM_FIFO36_DIBDIU5", + "BRAM_RAMB18_DOADO5", + "BRAM_IMUX1_UTURN_4", + "BRAM_UTURN_ADDRBWRADDRU14", + "BRAM_R_IMUX_ADDRARDADDRU4", + "BRAM_BYP2_2", + "BRAM_ADDRBWRADDRU13", + "BRAM_FIFO18_WEA3", + "BRAM_CTRL1_0", + "BRAM_WW4END1_2", + "BRAM_FIFO18_DIADI3", + "BRAM_NW4END2_2", + "BRAM_EE2BEG1_0", + "BRAM_IMUX40_2", + "BRAM_EE4A1_2", + "BRAM_NW4A2_0", + "BRAM_RAMB18_WRCOUNT3", + "BRAM_IMUX24_UTURN_2", + "BRAM_FIFO36_ADDRBWRADDRL6", + "BRAM_RAMB18_ADDRARDADDR2", + "BRAM_EE4C0_3", + "BRAM_ER1BEG0_4", + "BRAM_IMUX8_UTURN_2", + "BRAM_FIFO36_DOBDOU10", + "BRAM_FIFO36_DOADOU5", + "BRAM_IMUX46_4", + "BRAM_ADDRBWRADDRL6", + "BRAM_IMUX21_UTURN_4", + "BRAM_R_IMUX_ADDRBWRADDRU1", + "BRAM_SW4A1_0", + "BRAM_LOGIC_OUTS_B6_2", + "BRAM_R_IMUX_ADDRARDADDRL0", + "BRAM_CASCINBOT_ADDRBWRADDRU7", + "BRAM_PMVBRAM_SELECT4", + "BRAM_SE2A0_3", + "BRAM_RAMB18_FULL", + "BRAM_FIFO18_DIADI11", + "BRAM_FIFO36_DIADIU14", + "BRAM_ADDRARDADDRL4", + "BRAM_MONITOR_N_3", + "BRAM_IMUX33_UTURN_0", + "BRAM_RAMB18_ADDRARDADDR1", + "BRAM_IMUX42_UTURN_0", + "BRAM_EE2A2_1", + "BRAM_RAMB18_RDCOUNT3", + "BRAM_FIFO36_DIADIL2", + "BRAM_IMUX46_3", + "BRAM_IMUX18_4", + "BRAM_WR1END1_2", + "BRAM_RAMB18_CLKBWRCLK", + "BRAM_EL1BEG3_3", + "BRAM_BYP0_4", + "BRAM_IMUX18_1", + "BRAM_IMUX39_UTURN_4", + "BRAM_FIFO18_DOBDO14", + "BRAM_FIFO36_DOADOU0", + "BRAM_IMUX35_2", + "BRAM_WW2END2_1", + "BRAM_MONITOR_P_4", + "BRAM_UTURN_ADDRBWRADDRU1", + "BRAM_RAMB18_DIADI7", + "BRAM_FIFO36_DIBDIL13", + "BRAM_WW2END1_0", + "BRAM_RAMB18_DOPADOP1", + "BRAM_ADDRBWRADDRL9", + "BRAM_FIFO36_DIBDIL3", + "BRAM_LOGIC_OUTS_B2_0", + "BRAM_LH10_0", + "BRAM_ER1BEG3_3", + "BRAM_IMUX9_UTURN_0", + "BRAM_BLOCK_OUTS_L_B0_0", + "BRAM_FIFO36_ADDRBWRADDRU6", + "BRAM_NW4A0_1", + "BRAM_IMUX42_UTURN_3", + "BRAM_UTURN_ADDRBWRADDRU2", + "BRAM_IMUX1_UTURN_2", + "BRAM_FIFO18_DOADO3", + "BRAM_RAMB18_DIBDI1", + "BRAM_FAN4_3", + "BRAM_EE2BEG3_1", + "BRAM_LOGIC_OUTS_B17_1", + "BRAM_IMUX16_3", + "BRAM_EE2BEG3_3", + "BRAM_R_IMUX_ADDRBWRADDRU10", + "BRAM_FIFO36_DOBDOU14", + "BRAM_FIFO36_ADDRARDADDRU3", + "BRAM_CASCINBOT_ADDRARDADDRU10", + "BRAM_NW2A3_2", + "BRAM_IMUX10_UTURN_0", + "BRAM_FIFO18_WEBWE2", + "BRAM_WW2A2_3", + "BRAM_FIFO36_DIADIL1", + "BRAM_FIFO18_ADDRBTIEHIGH0", + "BRAM_RAMB18_ADDRBWRADDR1", + "BRAM_FIFO36_TSTCNT8", + "BRAM_IMUX26_1", + "BRAM_IMUX7_2", + "BRAM_FAN2_1", + "BRAM_FAN1_3", + "BRAM_LOGIC_OUTS_B15_1", + "BRAM_NE4BEG0_3", + "BRAM_R_IMUX_ADDRBWRADDRL4", + "BRAM_ADDRBWRADDRU12", + "BRAM_WW4A2_4", + "BRAM_FIFO36_DOBDOU12", + "BRAM_FIFO36_TSTWROS4", + "BRAM_CLK1_2", + "BRAM_EL1BEG2_3", + "BRAM_IMUX3_UTURN_0", + "BRAM_NE4BEG3_0", + "BRAM_NW4END2_1", + "BRAM_FIFO36_ADDRBWRADDRL2", + "BRAM_UTURN_ADDRBWRADDRU5", + "BRAM_IMUX33_0", + "BRAM_WW4A2_3", + "BRAM_UTURN_ADDRBWRADDRL2", + "BRAM_WW2A0_2", + "BRAM_EE2A2_3", + "BRAM_FIFO36_ECCPARITY6", + "BRAM_RAMB18_ADDRBWRADDR0", + "BRAM_FIFO18_DIADI1", + "BRAM_NW2A3_1", + "BRAM_FIFO18_DIADI14", + "BRAM_IMUX9_4", + "BRAM_FAN7_3", + "BRAM_EL1BEG0_4", + "BRAM_IMUX10_UTURN_3", + "BRAM_SW2A3_2", + "BRAM_RAMB18_ADDRBWRADDR5", + "BRAM_IMUX2_4", + "BRAM_SE4BEG2_1", + "BRAM_FIFO36_ADDRARDADDRU0", + "BRAM_CTRL0_2", + "BRAM_ADDRBWRADDRU14", + "BRAM_SW4A3_0", + "BRAM_BYP1_0", + "BRAM_FIFO18_DOADO4", + "BRAM_IMUX0_UTURN_4", + "BRAM_FIFO36_DOBDOU13", + "BRAM_BLOCK_OUTS_L_B0_4", + "BRAM_IMUX13_UTURN_4", + "BRAM_FIFO36_ADDRARDADDRL8", + "BRAM_FIFO36_ADDRBWRADDRL15", + "BRAM_RAMB18_DIPBDIP1", + "BRAM_IMUX43_2", + "BRAM_BYP7_3", + "BRAM_NW4END3_0", + "BRAM_IMUX19_UTURN_2", + "BRAM_FIFO36_WEBWEL0", + "BRAM_CASCINBOT_ADDRBWRADDRU4", + "BRAM_IMUX16_2", + "BRAM_EE4B3_4", + "BRAM_FIFO36_ADDRBWRADDRU3", + "BRAM_FIFO18_ADDRARDADDR1", + "BRAM_UTURN_ADDRARDADDRU0", + "BRAM_FAN0_0", + "BRAM_ADDRARDADDRL9", + "BRAM_IMUX15_UTURN_3", + "BRAM_FIFO36_WEBWEU7", + "BRAM_ADDRBWRADDRU11", + "BRAM_FIFO18_DOBDO12", + "BRAM_LOGIC_OUTS_B7_0", + "BRAM_IMUX29_1", + "BRAM_CLK0_1", + "BRAM_EE2A0_2", + "BRAM_UTURN_ADDRARDADDRU10", + "BRAM_IMUX10_1", + "BRAM_SW4A1_2", + "BRAM_SW2A2_1", + "BRAM_IMUX17_UTURN_3", + "BRAM_IMUX37_UTURN_2", + "BRAM_FAN2_3", + "BRAM_CLK1_3", + "BRAM_UTURN_ADDRARDADDRU11", + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRAM_SE4BEG3_2", + "BRAM_IMUX30_UTURN_0", + "BRAM_FIFO36_DIPADIPU0", + "BRAM_WW4END3_0", + "BRAM_FIFO36_DOADOU14", + "BRAM_NW2A2_1", + "BRAM_RAMB18_ADDRBWRADDR2", + "BRAM_RAMB18_DOBDO15", + "BRAM_WR1END3_0", + "BRAM_EE4C1_0", + "BRAM_CASCINBOT_ADDRARDADDRU0", + "BRAM_LOGIC_OUTS_B11_4", + "BRAM_EE4B0_4", + "BRAM_EE4A2_4", + "BRAM_IMUX32_UTURN_0", + "BRAM_IMUX29_3", + "BRAM_R_IMUX_ADDRBWRADDRL11", + "BRAM_NE4C3_2", + "BRAM_IMUX24_UTURN_0", + "BRAM_NW2A3_0", + "BRAM_EE4BEG1_2", + "BRAM_WL1END3_1", + "BRAM_IMUX24_UTURN_3", + "BRAM_UTURN_ADDRBWRADDRL11", + "BRAM_FIFO36_ADDRARDADDRU6", + "BRAM_FIFO36_DIPADIPL0", + "BRAM_EE4B1_4", + "BRAM_RAMB18_ADDRBWRADDR10", + "BRAM_IMUX22_UTURN_0", + "BRAM_IMUX25_UTURN_1", + "BRAM_R_IMUX_ADDRBWRADDRL7", + "BRAM_FIFO18_RDCOUNT11", + "BRAM_WW4A3_0", + "BRAM_LOGIC_OUTS_B3_0", + "BRAM_IMUX31_4", + "BRAM_FIFO18_RDCOUNT4", + "BRAM_CASCINBOT_ADDRBWRADDRU1", + "BRAM_FAN4_4", + "BRAM_FIFO36_WEBWEL2", + "BRAM_BLOCK_OUTS_L_B3_3", + "BRAM_IMUX3_UTURN_3", + "BRAM_FIFO36_TSTRDOS3", + "BRAM_FIFO36_DOADOU7", + "BRAM_SE2A3_1", + "BRAM_FIFO36_CASCADEOUTA_1", + "BRAM_FIFO18_RDERR", + "BRAM_RAMB18_WEA1", + "BRAM_IMUX19_3", + "BRAM_FIFO18_RDCOUNT5", + "BRAM_IMUX13_0", + "BRAM_FIFO18_ADDRBWRADDR2", + "BRAM_RAMB18_DOBDO4", + "BRAM_FIFO18_WRERR", + "BRAM_RAMB18_RDCOUNT10", + "BRAM_IMUX39_UTURN_2", + "BRAM_EL1BEG0_0", + "BRAM_LOGIC_OUTS_B18_1", + "BRAM_LH9_2", + "BRAM_ADDRBWRADDRU7", + "BRAM_FIFO36_REGCEBU", + "BRAM_IMUX40_UTURN_3", + "BRAM_FAN4_1", + "BRAM_BLOCK_OUTS_L_B0_1", + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRAM_SE4BEG1_2", + "BRAM_SW4A2_0", + "BRAM_FIFO36_DOBDOU7", + "BRAM_FIFO36_DIBDIL14", + "BRAM_WW4C0_4", + "BRAM_SE4C1_3", + "BRAM_NE4C0_0", + "BRAM_NW2A3_3", + "BRAM_ER1BEG3_1", + "BRAM_ADDRARDADDRL14", + "BRAM_IMUX34_UTURN_2", + "BRAM_IMUX6_UTURN_3", + "BRAM_WW4END1_0", + "BRAM_FIFO36_WEBWEL6", + "BRAM_LOGIC_OUTS_B7_1", + "BRAM_BYP5_3", + "BRAM_CTRL1_3", + "BRAM_FIFO18_DIADI13", + "BRAM_NE4C3_0", + "BRAM_LOGIC_OUTS_B14_2", + "BRAM_RAMB18_DOADO2", + "BRAM_FIFO36_CASCADEINB", + "BRAM_ER1BEG1_2", + "BRAM_ADDRARDADDRL7", + "BRAM_WR1END3_1", + "BRAM_NW4A0_4", + "BRAM_FIFO18_ALMOSTFULL", + "BRAM_IMUX28_4", + "BRAM_FIFO36_DIADIL9", + "BRAM_IMUX21_2", + "BRAM_FIFO36_DOADOU10", + "BRAM_LH7_2", + "BRAM_LH2_1", + "BRAM_FIFO18_WEBWE5", + "BRAM_LOGIC_OUTS_B12_0", + "BRAM_IMUX16_1", + "BRAM_FIFO36_WEBWEU5", + "BRAM_FIFO36_RDCOUNT7", + "BRAM_FIFO36_DIADIL0", + "BRAM_LOGIC_OUTS_B4_1", + "BRAM_FIFO18_DOADO12", + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRAM_RAMB18_DIBDI3", + "BRAM_FIFO36_WRCOUNT5", + "BRAM_IMUX39_UTURN_3", + "BRAM_EE4A2_2", + "BRAM_FIFO36_DIBDIU11", + "BRAM_FIFO18_WEA1", + "BRAM_SW4END0_0", + "BRAM_IMUX37_3", + "BRAM_LOGIC_OUTS_B15_0", + "BRAM_RAMB18_WRCOUNT7", + "BRAM_EE2BEG1_1", + "BRAM_IMUX2_0", + "BRAM_ADDRARDADDRU9", + "BRAM_ER1BEG2_2", + "BRAM_FIFO36_TSTCNT10", + "BRAM_RAMB18_WRCOUNT0", + "BRAM_WW4C0_2", + "BRAM_RAMB18_DOBDO3", + "BRAM_LOGIC_OUTS_B14_1", + "BRAM_LOGIC_OUTS_B20_3", + "BRAM_LOGIC_OUTS_B11_3", + "BRAM_WW4C0_3", + "BRAM_IMUX17_UTURN_0", + "BRAM_IMUX33_UTURN_1", + "BRAM_LH12_1", + "BRAM_IMUX_R_ADDRBWRADDRL15", + "BRAM_FIFO36_TSTWROS1", + "BRAM_LOGIC_OUTS_B2_3", + "BRAM_FIFO18_DOADO8", + "BRAM_NW4END1_1", + "BRAM_FIFO18_DOBDO1", + "BRAM_FIFO36_ADDRBWRADDRU10", + "BRAM_ADDRARDADDRL13", + "BRAM_ADDRBWRADDRU10", + "BRAM_SE4C0_4", + "BRAM_IMUX6_UTURN_0", + "BRAM_IMUX31_1", + "BRAM_WW2A3_3", + "BRAM_IMUX42_4", + "BRAM_FIFO36_DIADIL11", + "BRAM_FIFO18_REGCEB", + "BRAM_CLK0_3", + "BRAM_EE2BEG0_3", + "BRAM_LOGIC_OUTS_B2_1", + "BRAM_CASCINBOT_ADDRARDADDRU5", + "BRAM_ER1BEG3_2", + "BRAM_EE2A3_4", + "BRAM_FIFO36_RSTRAMARSTRAMU", + "BRAM_IMUX16_0", + "BRAM_FIFO18_DIPBDIP1", + "BRAM_IMUX40_UTURN_1", + "BRAM_CASCINBOT_ADDRBWRADDRU12", + "BRAM_IMUX30_1", + "BRAM_IMUX44_2", + "BRAM_RAMB18_ADDRBTIEHIGH0", + "BRAM_FIFO18_DOBDO6", + "BRAM_ADDRARDADDRU12", + "BRAM_BLOCK_OUTS_L_B3_4", + "BRAM_BLOCK_OUTS_L_B2_2", + "BRAM_IMUX34_3", + "BRAM_WL1END3_0", + "BRAM_FIFO36_TSTWROS10", + "BRAM_WW4A1_2", + "BRAM_ADDRARDADDRL10", + "BRAM_NE2A3_0", + "BRAM_IMUX34_4", + "BRAM_IMUX37_UTURN_0", + "BRAM_IMUX29_4", + "BRAM_WW4B3_1", + "BRAM_FIFO18_CLKARDCLK", + "BRAM_WW2END0_2", + "BRAM_SW4END2_1", + "BRAM_IMUX42_UTURN_1", + "BRAM_SW4END1_2", + "BRAM_FIFO36_WRCOUNT2", + "BRAM_RAMB18_DIBDI6", + "BRAM_IMUX34_0", + "BRAM_NW2A0_1", + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRAM_FIFO18_REGCLKARDRCLK", + "BRAM_RAMB18_ADDRARDADDR5", + "BRAM_NW2A1_1", + "BRAM_IMUX24_UTURN_4", + "BRAM_NW4A0_3", + "BRAM_UTURN_ADDRARDADDRL0", + "BRAM_IMUX27_UTURN_3", + "BRAM_IMUX34_UTURN_1", + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_WW2END3_1", + "BRAM_LH4_2", + "BRAM_FIFO36_DIADIU9", + "BRAM_IMUX32_UTURN_3", + "BRAM_ER1BEG2_4", + "BRAM_IMUX45_UTURN_1", + "BRAM_IMUX11_UTURN_3", + "BRAM_ADDRARDADDRU2", + "BRAM_IMUX18_0", + "BRAM_LOGIC_OUTS_B3_4", + "BRAM_IMUX14_UTURN_4", + "BRAM_FIFO18_RDCOUNT2", + "BRAM_ER1BEG0_0", + "BRAM_FIFO36_CLKARDCLKU", + "BRAM_FAN1_1", + "BRAM_LOGIC_OUTS_B18_3", + "BRAM_UTURN_ADDRARDADDRL9", + "BRAM_R_IMUX_ADDRBWRADDRL6", + "BRAM_IMUX22_UTURN_3", + "BRAM_WW4A0_3", + "BRAM_EE4A0_2", + "BRAM_FIFO18_DIPADIP0", + "BRAM_NW2A0_0", + "BRAM_FIFO36_CLKBWRCLKL", + "BRAM_IMUX45_UTURN_2", + "BRAM_WL1END1_4", + "BRAM_BLOCK_OUTS_L_B3_2", + "BRAM_LOGIC_OUTS_B10_0", + "BRAM_EE2A1_3", + "BRAM_RAMB18_ADDRARDADDR13", + "BRAM_NE2A2_3", + "BRAM_FIFO36_DOBDOL12", + "BRAM_FIFO18_DIADI2", + "BRAM_CASCOUT_ADDRARDADDRU11", + "BRAM_IMUX29_UTURN_3", + "BRAM_IMUX3_UTURN_2", + "BRAM_FIFO36_DOBDOU1", + "BRAM_SE2A1_3", + "BRAM_NE2A2_1", + "BRAM_WW4B2_3", + "BRAM_IMUX35_UTURN_1", + "BRAM_EE4A0_1", + "BRAM_WW2A1_3", + "BRAM_WW4END0_0", + "BRAM_FIFO18_DOADO11", + "BRAM_EE2BEG2_2", + "BRAM_RAMB18_DIADI4", + "BRAM_CASCINBOT_ADDRBWRADDRU5", + "BRAM_SW2A3_0", + "BRAM_ADDRARDADDRL6", + "BRAM_LOGIC_OUTS_B13_1", + "BRAM_LH8_4", + "BRAM_FIFO36_DOBDOL9", + "BRAM_LH1_1", + "BRAM_FIFO36_WEBWEL5", + "BRAM_EE2BEG2_0", + "BRAM_IMUX3_4", + "BRAM_BLOCK_OUTS_L_B0_3", + "BRAM_UTURN_ADDRBWRADDRL8", + "BRAM_FIFO36_TSTRDOS8", + "BRAM_NE2A0_2", + "BRAM_IMUX4_3", + "BRAM_SW4END2_4", + "BRAM_IMUX12_1", + "BRAM_IMUX20_UTURN_2", + "BRAM_LOGIC_OUTS_B4_3", + "BRAM_FIFO36_DOBDOU11", + "BRAM_IMUX17_UTURN_2", + "BRAM_RAMB18_DIADI6", + "BRAM_FIFO36_TSTBRAMRST", + "BRAM_UTURN_ADDRARDADDRL13", + "BRAM_LH11_2", + "BRAM_BYP5_1", + "BRAM_BYP0_1", + "BRAM_IMUX43_1", + "BRAM_FIFO36_DIBDIU12", + "BRAM_FIFO18_DOBDO3", + "BRAM_FIFO18_WRCOUNT8", + "BRAM_BLOCK_OUTS_L_B2_3", + "BRAM_FIFO36_ADDRBWRADDRL1", + "BRAM_FIFO36_TSTWROS0", + "BRAM_CASCINBOT_ADDRARDADDRU4", + "BRAM_CASCINBOT_ADDRARDADDRU1", + "BRAM_BYP6_2", + "BRAM_IMUX35_1", + "BRAM_NE2A1_0", + "BRAM_NW4END0_2", + "BRAM_EE2A0_4", + "BRAM_FIFO18_DIBDI5", + "BRAM_RAMB18_ADDRBTIEHIGH1", + "BRAM_WR1END2_0", + "BRAM_FAN5_1", + "BRAM_FIFO36_RDCOUNT4", + "BRAM_WW4END3_2", + "BRAM_IMUX19_UTURN_0", + "BRAM_IMUX8_UTURN_4", + "BRAM_RAMB18_ADDRATIEHIGH1", + "BRAM_EE4C1_2", + "BRAM_RAMB18_RSTREGB", + "BRAM_IMUX41_4", + "BRAM_WW2END2_4", + "BRAM_LOGIC_OUTS_B5_1", + "BRAM_WW4A1_0", + "BRAM_LH7_1", + "BRAM_IMUX24_1", + "BRAM_EE4A1_4", + "BRAM_IMUX18_UTURN_3", + "BRAM_FIFO18_WEA0", + "BRAM_IMUX11_0", + "BRAM_EE4C1_3", + "BRAM_FIFO36_DOPBDOPL0", + "BRAM_CLK1_1", + "BRAM_RAMB18_DIBDI9", + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRAM_RAMB18_DIBDI10", + "BRAM_SW2A1_2", + "BRAM_LOGIC_OUTS_B12_4", + "BRAM_FIFO18_DIADI4", + "BRAM_FIFO36_ADDRBWRADDRL10", + "BRAM_FIFO36_RSTREGBL", + "BRAM_SW2A3_1", + "BRAM_BLOCK_OUTS_L_B1_2", + "BRAM_IMUX3_2", + "BRAM_FIFO36_DIADIL14", + "BRAM_CASCINBOT_ADDRBWRADDRU0", + "BRAM_EL1BEG2_4", + "BRAM_NE4C1_0", + "BRAM_IMUX35_UTURN_0", + "BRAM_FIFO36_CASCADEOUTB", + "BRAM_EL1BEG3_1", + "BRAM_FIFO18_ENBWREN", + "BRAM_UTURN_ADDRARDADDRU3", + "BRAM_SW4END0_1", + "BRAM_IMUX21_3", + "BRAM_RAMB18_WRCOUNT5", + "BRAM_EE2BEG0_4", + "BRAM_NW4A0_2", + "BRAM_IMUX41_3", + "BRAM_ADDRARDADDRL0", + "BRAM_SE4BEG2_2", + "BRAM_NW4END0_1", + "BRAM_R_IMUX_ADDRARDADDRU5", + "BRAM_FIFO18_DOADO9", + "BRAM_FIFO36_ADDRBWRADDRL0", + "BRAM_SE2A1_4", + "BRAM_R_IMUX_ADDRBWRADDRL10", + "BRAM_SW2A2_2", + "BRAM_FIFO18_ADDRBWRADDR10", + "BRAM_RAMB18_ADDRBWRADDR7", + "BRAM_LOGIC_OUTS_B10_1", + "BRAM_IMUX39_UTURN_0", + "BRAM_FIFO36_ADDRBWRADDRU12", + "BRAM_IMUX17_1", + "BRAM_FIFO18_ADDRBWRADDR3", + "BRAM_RAMB18_DOBDO6", + "BRAM_NE4BEG0_4", + "BRAM_R_IMUX_ADDRBWRADDRL5", + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRAM_FIFO36_ADDRBWRADDRL8", + "BRAM_ADDRARDADDRL12", + "BRAM_UTURN_ADDRBWRADDRU13", + "BRAM_WW2END0_4", + "BRAM_FIFO36_DIADIU11", + "BRAM_RAMB18_DOBDO9", + "BRAM_LH5_0", + "BRAM_RAMB18_DOADO6", + "BRAM_IMUX32_1", + "BRAM_WW4A0_2", + "BRAM_IMUX33_1", + "BRAM_IMUX21_0", + "BRAM_NW4END1_3", + "BRAM_FIFO18_WEBWE4", + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRAM_FIFO36_DOADOL1", + "BRAM_IMUX5_3", + "BRAM_IMUX14_4", + "BRAM_WW4END1_4", + "BRAM_LOGIC_OUTS_B21_0", + "BRAM_SW4A1_1", + "BRAM_RAMB18_RDERR", + "BRAM_EE4BEG2_4", + "BRAM_FIFO18_WRCOUNT9", + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_IMUX21_UTURN_0", + "BRAM_IMUX21_1", + "BRAM_IMUX42_0", + "BRAM_IMUX43_4", + "BRAM_SW4A2_4", + "BRAM_IMUX5_UTURN_3", + "BRAM_WL1END1_1", + "BRAM_R_IMUX_ADDRARDADDRL8", + "BRAM_RAMB18_WEA2", + "BRAM_IMUX13_3", + "BRAM_EE4C0_0", + "BRAM_FIFO36_ADDRARDADDRL5", + "BRAM_FIFO36_DOPBDOPL1", + "BRAM_IMUX23_2", + "BRAM_RAMB18_WEBWE5", + "BRAM_IMUX16_UTURN_1", + "BRAM_EE4BEG2_3", + "BRAM_FIFO18_DOBDO15", + "BRAM_IMUX33_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU5", + "BRAM_FIFO18_DOADO13", + "BRAM_FIFO36_WEBWEL7", + "BRAM_BYP6_1", + "BRAM_IMUX31_2", + "BRAM_FIFO36_DIADIU8", + "BRAM_RAMB18_ADDRBWRADDR12", + "BRAM_WW2END3_2", + "BRAM_LH11_4", + "BRAM_FIFO36_ENARDENU", + "BRAM_ADDRARDADDRU1", + "BRAM_FIFO36_ENARDENL", + "BRAM_CTRL0_0", + "BRAM_IMUX28_UTURN_1", + "BRAM_IMUX39_3", + "BRAM_NW4A3_1", + "BRAM_EE4BEG3_4", + "BRAM_UTURN_ADDRBWRADDRU7", + "BRAM_SW2A1_1", + "BRAM_IMUX39_2", + "BRAM_SE4C3_4", + "BRAM_FIFO36_DOBDOU5", + "BRAM_FIFO36_DIBDIU6", + "BRAM_LH1_4", + "BRAM_IMUX9_UTURN_3", + "BRAM_IMUX4_4", + "BRAM_WW2END3_3", + "BRAM_SW4END0_4", + "BRAM_NW4A3_4", + "BRAM_IMUX0_UTURN_0", + "BRAM_SW4END1_0", + "BRAM_IMUX11_3", + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRAM_FIFO18_DOADO14", + "BRAM_IMUX38_2", + "BRAM_FIFO36_FULL", + "BRAM_LH2_3", + "BRAM_WW4B3_2", + "BRAM_FIFO36_REGCLKARDRCLKU", + "BRAM_IMUX28_UTURN_0", + "BRAM_UTURN_ADDRARDADDRU4", + "BRAM_NW4A3_3", + "BRAM_LOGIC_OUTS_B1_4", + "BRAM_ER1BEG1_1", + "BRAM_BYP0_3", + "BRAM_FIFO36_WRCOUNT8", + "BRAM_FIFO18_DOADO1", + "BRAM_IMUX15_UTURN_1", + "BRAM_FIFO18_REGCEAREGCE", + "BRAM_NE4BEG3_2", + "BRAM_RAMB18_ADDRARDADDR3", + "BRAM_LOGIC_OUTS_B14_3", + "BRAM_FIFO18_DIBDI7", + "BRAM_RAMB18_DOADO0", + "BRAM_LOGIC_OUTS_B17_3", + "BRAM_LOGIC_OUTS_B1_1", + "BRAM_LOGIC_OUTS_B22_1", + "BRAM_FIFO36_TSTRDOS12", + "BRAM_FIFO36_TSTCNT2", + "BRAM_IMUX22_1", + "BRAM_IMUX1_1", + "BRAM_IMUX38_1", + "BRAM_FIFO36_ECCPARITY5", + "BRAM_UTURN_ADDRBWRADDRU9", + "BRAM_LOGIC_OUTS_B19_1", + "BRAM_FIFO36_ECCPARITY4", + "BRAM_IMUX11_UTURN_4", + "BRAM_SE4C3_3", + "BRAM_SE4BEG3_4", + "BRAM_IMUX12_UTURN_0", + "BRAM_EE2A0_0", + "BRAM_BYP7_4", + "BRAM_R_IMUX_ADDRARDADDRL11", + "BRAM_IMUX31_0", + "BRAM_IMUX9_UTURN_4", + "BRAM_FIFO36_DIBDIU3", + "BRAM_IMUX6_0", + "BRAM_FIFO36_DIPADIPL1", + "BRAM_IMUX12_0", + "BRAM_WW2A1_0", + "BRAM_ADDRBWRADDRU3", + "BRAM_LH8_3", + "BRAM_LOGIC_OUTS_B15_4", + "BRAM_R_IMUX_ADDRARDADDRL9", + "BRAM_IMUX42_2", + "BRAM_FIFO36_TSTCNT5", + "BRAM_R_IMUX_ADDRARDADDRU1", + "BRAM_LOGIC_OUTS_B16_1", + "BRAM_IMUX38_UTURN_2", + "BRAM_IMUX47_UTURN_3", + "BRAM_RAMB18_DIBDI0", + "BRAM_CASCINBOT_ADDRBWRADDRU13", + "BRAM_EE4C3_1", + "BRAM_FIFO36_ADDRBWRADDRU2", + "BRAM_WW4C2_4", + "BRAM_CASCINBOT_ADDRBWRADDRU9", + "BRAM_WW4B0_3", + "BRAM_NW2A0_3", + "BRAM_IMUX44_UTURN_3", + "BRAM_R_IMUX_ADDRBWRADDRU11", + "BRAM_FIFO18_RDCOUNT7", + "BRAM_FIFO18_DOPADOP1", + "BRAM_IMUX27_UTURN_4", + "BRAM_CASCOUT_ADDRBWRADDRU10", + "BRAM_ADDRBWRADDRL4", + "BRAM_BYP6_3", + "BRAM_ADDRARDADDRL11", + "BRAM_R_IMUX_ADDRARDADDRU6", + "BRAM_RAMB18_DOPBDOP0", + "BRAM_SW4A3_3", + "BRAM_LOGIC_OUTS_B10_2", + "BRAM_FIFO36_DOADOL6", + "BRAM_SE2A0_4", + "BRAM_UTURN_ADDRBWRADDRL14", + "BRAM_RAMB18_DOADO15", + "BRAM_LOGIC_OUTS_B5_3", + "BRAM_IMUX15_UTURN_0", + "BRAM_FIFO36_DIBDIL15", + "BRAM_IMUX3_1", + "BRAM_R_IMUX_ADDRBWRADDRU14", + "BRAM_FIFO36_DIBDIU14", + "BRAM_SE2A2_1", + "BRAM_WW4A1_4", + "BRAM_IMUX28_3", + "BRAM_FIFO36_DIADIU10", + "BRAM_CASCINBOT_ADDRARDADDRU9", + "BRAM_EE4B1_1", + "BRAM_FIFO36_TSTCNT7", + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRAM_R_IMUX_ADDRARDADDRL2", + "BRAM_UTURN_ADDRBWRADDRL5", + "BRAM_RAMB18_RDCOUNT1", + "BRAM_LOGIC_OUTS_B6_0", + "BRAM_FIFO36_EMPTY", + "BRAM_EE4C1_4", + "BRAM_NW4A3_0", + "BRAM_FIFO18_DIADI9", + "BRAM_IMUX37_1", + "BRAM_NE4C0_1", + "BRAM_CASCOUT_ADDRARDADDRU8", + "BRAM_FIFO36_DOADOL11", + "BRAM_CASCOUT_ADDRARDADDRU14", + "BRAM_LOGIC_OUTS_B22_2", + "BRAM_LOGIC_OUTS_B6_4", + "BRAM_IMUX27_2", + "BRAM_FIFO36_DOBDOL11", + "BRAM_FIFO36_WEAU1", + "BRAM_IMUX17_3", + "BRAM_IMUX25_3", + "BRAM_IMUX37_UTURN_4", + "BRAM_IMUX46_UTURN_3", + "BRAM_RAMB18_DIBDI8", + "BRAM_FIFO36_TSTIN4", + "BRAM_WW4END0_3", + "BRAM_FIFO36_ADDRARDADDRL4", + "BRAM_R_IMUX_ADDRARDADDRU3", + "BRAM_CASCINBOT_ADDRARDADDRU8", + "BRAM_WW4B0_4", + "BRAM_UTURN_ADDRBWRADDRU11", + "BRAM_FIFO36_TSTOUT3", + "BRAM_IMUX45_4", + "BRAM_LH10_2", + "BRAM_LOGIC_OUTS_B23_0", + "BRAM_IMUX39_UTURN_1", + "BRAM_FIFO36_RDERR", + "BRAM_IMUX15_UTURN_4", + "BRAM_FIFO36_DOADOL7", + "BRAM_LOGIC_OUTS_B5_2", + "BRAM_SE2A3_4", + "BRAM_IMUX42_UTURN_4", + "BRAM_IMUX19_UTURN_3", + "BRAM_LOGIC_OUTS_B18_0", + "BRAM_FIFO36_TSTCNT6", + "BRAM_UTURN_ADDRBWRADDRU10", + "BRAM_FIFO18_ADDRARDADDR9", + "BRAM_FIFO36_ADDRARDADDRU5", + "BRAM_IMUX7_1", + "BRAM_FIFO36_ADDRARDADDRL2", + "BRAM_R_IMUX_ADDRARDADDRU0", + "BRAM_FIFO36_RDCOUNT10", + "BRAM_WW2END1_2", + "BRAM_NE4C1_4", + "BRAM_FIFO36_REGCLKBL", + "BRAM_BYP6_0", + "BRAM_IMUX16_UTURN_2", + "BRAM_IMUX20_2", + "BRAM_NE2A3_2", + "BRAM_WR1END0_4", + "BRAM_FIFO18_ADDRATIEHIGH1", + "BRAM_BYP1_3", + "BRAM_IMUX32_2", + "BRAM_WR1END0_1", + "BRAM_FIFO36_TSTOFF", + "BRAM_EL1BEG2_0", + "BRAM_NE4BEG2_4", + "BRAM_FIFO36_DOADOL13", + "BRAM_LOGIC_OUTS_B15_3", + "BRAM_WW4END1_3", + "BRAM_FAN3_3", + "BRAM_SW4END1_1", + "BRAM_ADDRBWRADDRL13", + "BRAM_FIFO36_ADDRBWRADDRL13", + "BRAM_IMUX31_UTURN_3", + "BRAM_FIFO18_DIBDI0", + "BRAM_EE4A1_1", + "BRAM_EE4B0_1", + "BRAM_R_IMUX_ADDRARDADDRL13", + "BRAM_CASCOUT_ADDRBWRADDRU4", + "BRAM_FIFO18_DIBDI15", + "BRAM_IMUX35_UTURN_4", + "BRAM_ADDRBWRADDRL3", + "BRAM_FIFO36_DOADOU6", + "BRAM_NW2A1_0", + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRAM_CTRL0_4", + "BRAM_LOGIC_OUTS_B9_1", + "BRAM_FIFO36_TSTWROS11", + "BRAM_FIFO36_INJECTDBITERR", + "BRAM_IMUX4_UTURN_3", + "BRAM_FIFO36_DIADIU0", + "BRAM_IMUX0_UTURN_2", + "BRAM_FIFO36_DIADIU1", + "BRAM_ADDRBWRADDRU5", + "BRAM_LOGIC_OUTS_B6_1", + "BRAM_SW2A1_3", + "BRAM_IMUX13_UTURN_0", + "BRAM_IMUX32_UTURN_4", + "BRAM_FIFO18_DIPADIP1", + "BRAM_IMUX17_UTURN_4", + "BRAM_SE4BEG0_0", + "BRAM_FIFO18_WEA2", + "BRAM_FIFO36_WRERR", + "BRAM_BLOCK_OUTS_L_B1_4", + "BRAM_ADDRBWRADDRU0", + "BRAM_RAMB18_ADDRARDADDR10", + "BRAM_FIFO36_DIBDIU10", + "BRAM_IMUX5_1", + "BRAM_EL1BEG2_2", + "BRAM_LH9_1", + "BRAM_NE4C1_1", + "BRAM_IMUX27_UTURN_0", + "BRAM_RAMB18_RDCOUNT2", + "BRAM_BYP4_1", + "BRAM_FIFO36_CASCADEINA", + "BRAM_FAN1_0", + "BRAM_RAMB18_WRCOUNT2", + "BRAM_EE4A2_3", + "BRAM_IMUX32_4", + "BRAM_EL1BEG1_1", + "BRAM_FIFO36_ADDRBWRADDRL9", + "BRAM_IMUX32_0", + "BRAM_WW4A3_4", + "BRAM_IMUX7_4", + "BRAM_IMUX0_1", + "BRAM_FIFO36_CLKBWRCLKU", + "BRAM_IMUX32_UTURN_2", + "BRAM_FIFO36_ADDRARDADDRL10", + "BRAM_PMVBRAM_O_1", + "BRAM_FIFO36_DOBDOL7", + "BRAM_FIFO18_DIADI12", + "BRAM_ADDRBWRADDRU8", + "BRAM_IMUX14_UTURN_1", + "BRAM_WW4C2_3", + "BRAM_IMUX1_UTURN_3", + "BRAM_EE4C0_1", + "BRAM_LOGIC_OUTS_B9_3", + "BRAM_NE4BEG1_1", + "BRAM_FIFO18_ADDRARDADDR12", + "BRAM_IMUX6_1", + "BRAM_FIFO36_WEBWEL4", + "BRAM_FIFO36_RSTREGARSTREGU", + "BRAM_WW4A0_1", + "BRAM_FIFO36_ADDRARDADDRL11", + "BRAM_SE4C0_1", + "BRAM_IMUX1_4", + "BRAM_WW4A2_2", + "BRAM_ER1BEG1_3", + "BRAM_FIFO36_ENBWRENU", + "BRAM_FIFO36_TSTRDOS4", + "BRAM_FIFO36_DOBDOL2", + "BRAM_R_IMUX_ADDRBWRADDRL0", + "BRAM_WW2END0_0", + "BRAM_LH12_3", + "BRAM_UTURN_ADDRARDADDRL5", + "BRAM_FIFO36_DOBDOL15", + "BRAM_SW4END0_2", + "BRAM_LH11_0", + "BRAM_RAMB18_DIPADIP0", + "BRAM_WW4C2_1", + "BRAM_ADDRARDADDRU0", + "BRAM_CTRL1_2", + "BRAM_FIFO36_TSTRDOS5", + "BRAM_IMUX41_1", + "BRAM_IMUX10_UTURN_1", + "BRAM_IMUX8_UTURN_0", + "BRAM_FIFO36_DOADOU12", + "BRAM_IMUX18_UTURN_0", + "BRAM_R_IMUX_ADDRBWRADDRU2", + "BRAM_SE4C1_0", + "BRAM_SE4BEG1_3", + "BRAM_IMUX7_3", + "BRAM_FIFO36_DIBDIU13", + "BRAM_FIFO36_WRCOUNT1", + "BRAM_WL1END2_3", + "BRAM_FIFO36_WRCOUNT10", + "BRAM_IMUX39_0", + "BRAM_ADDRBWRADDRL0", + "BRAM_FAN0_3", + "BRAM_IMUX5_2", + "BRAM_LOGIC_OUTS_B17_0", + "BRAM_FIFO36_WEAU2", + "BRAM_FIFO36_WRCOUNT11", + "BRAM_LH2_2", + "BRAM_FAN1_2", + "BRAM_WR1END1_4", + "BRAM_NE2A3_1", + "BRAM_IMUX19_4", + "BRAM_FIFO18_DOBDO7", + "BRAM_WW4A0_4", + "BRAM_CASCINBOT_ADDRARDADDRU6", + "BRAM_WW4B2_2", + "BRAM_NE2A3_3", + "BRAM_RAMB18_RDCOUNT9", + "BRAM_FIFO36_DOBDOL14", + "BRAM_IMUX42_UTURN_2", + "BRAM_FIFO36_DOBDOU8", + "BRAM_FIFO18_ADDRBWRADDR6", + "BRAM_IMUX43_UTURN_0", + "BRAM_LOGIC_OUTS_B15_2", + "BRAM_LH4_1", + "BRAM_CASCINBOT_ADDRBWRADDRU11", + "BRAM_LOGIC_OUTS_B11_2", + "BRAM_IMUX2_UTURN_4", + "BRAM_FIFO18_ADDRBWRADDR8", + "BRAM_LOGIC_OUTS_B21_3", + "BRAM_EE2BEG0_2", + "BRAM_SW4END3_1", + "BRAM_FIFO18_DOADO15", + "BRAM_IMUX38_4", + "BRAM_LOGIC_OUTS_B22_3", + "BRAM_FIFO36_ADDRBWRADDRL12", + "BRAM_LH5_2", + "BRAM_FIFO36_DOADOL0", + "BRAM_FIFO36_TSTCNT9", + "BRAM_SE2A3_2", + "BRAM_IMUX38_0", + "BRAM_LOGIC_OUTS_B10_4", + "BRAM_FIFO36_ADDRARDADDRL14", + "BRAM_IMUX30_2", + "BRAM_FIFO36_DIBDIL4", + "BRAM_SW2A3_3", + "BRAM_EE2BEG1_4", + "BRAM_EE4BEG1_4", + "BRAM_ER1BEG1_0", + "BRAM_SW4END1_3", + "BRAM_LOGIC_OUTS_B23_2", + "BRAM_FIFO36_ADDRARDADDRU4", + "BRAM_FIFO36_DIADIU3", + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRAM_FAN4_0", + "BRAM_EE2A0_3", + "BRAM_LH8_2", + "BRAM_EE2A1_0", + "BRAM_EE4C2_2", + "BRAM_FIFO36_TSTRDCNTOFF", + "BRAM_IMUX0_2", + "BRAM_EE4B1_0", + "BRAM_WW4C0_1", + "BRAM_FIFO18_DIBDI2", + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRAM_NW2A2_4", + "BRAM_RAMB18_WRCOUNT8", + "BRAM_SW2A0_4", + "BRAM_FIFO36_WRCOUNT12", + "BRAM_ADDRBWRADDRU1", + "BRAM_BLOCK_OUTS_L_B1_1", + "BRAM_EE4BEG0_1", + "BRAM_IMUX4_UTURN_4", + "BRAM_ADDRBWRADDRL2", + "BRAM_LOGIC_OUTS_B0_1", + "BRAM_FIFO36_DOADOL9", + "BRAM_FIFO36_RSTREGBU", + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRAM_WW4B1_2", + "BRAM_EE4B3_2", + "BRAM_RAMB18_DOBDO1", + "BRAM_RAMB18_WEBWE0", + "BRAM_EE2BEG0_1", + "BRAM_IMUX33_UTURN_4", + "BRAM_BYP1_4", + "BRAM_FIFO36_TSTOUT1", + "BRAM_IMUX47_UTURN_4", + "BRAM_FAN3_4", + "BRAM_LOGIC_OUTS_B10_3", + "BRAM_FIFO36_DOADOL2", + "BRAM_WL1END0_2", + "BRAM_EE4C3_0", + "BRAM_R_IMUX_ADDRARDADDRU7", + "BRAM_BYP4_0", + "BRAM_R_IMUX_ADDRBWRADDRU13", + "BRAM_CASCINBOT_ADDRBWRADDRU8", + "BRAM_LOGIC_OUTS_B3_1", + "BRAM_CASCOUT_ADDRBWRADDRU9", + "BRAM_LH10_4", + "BRAM_RAMB18_DOADO11", + "BRAM_CASCOUT_ADDRARDADDRU13", + "BRAM_FIFO18_ADDRBWRADDR9", + "BRAM_FIFO18_ADDRARDADDR6", + "BRAM_CASCINBOT_ADDRBWRADDRU10", + "BRAM_R_IMUX_ADDRARDADDRL14", + "BRAM_WW4B3_0", + "BRAM_LH9_3", + "BRAM_NE2A3_4", + "BRAM_RAMB18_DOBDO7", + "BRAM_EE4B2_0", + "BRAM_FIFO18_WRCOUNT10", + "BRAM_ER1BEG0_1", + "BRAM_IMUX41_UTURN_3", + "BRAM_FIFO18_DOBDO2", + "BRAM_SE4C1_1", + "BRAM_FIFO36_ECCPARITY2", + "BRAM_FIFO36_WRCOUNT9", + "BRAM_SW4A0_0", + "BRAM_FIFO18_ADDRARDADDR0", + "BRAM_BLOCK_OUTS_L_B2_1", + "BRAM_FIFO18_DIADI8", + "BRAM_FIFO36_DOPADOPL0", + "BRAM_UTURN_ADDRBWRADDRU8", + "BRAM_ER1BEG3_4", + "BRAM_FIFO18_DIBDI4", + "BRAM_NE4C3_3", + "BRAM_FAN3_2", + "BRAM_CASCINBOT_ADDRARDADDRU3", + "BRAM_LH4_3", + "BRAM_FIFO18_DOBDO13", + "BRAM_RAMB18_WEA0", + "BRAM_FIFO36_ADDRARDADDRU13", + "BRAM_FIFO36_DIPBDIPU1", + "BRAM_RAMB18_RSTRAMARSTRAM", + "BRAM_EE4A2_1", + "BRAM_EE4C3_2", + "BRAM_IMUX11_1", + "BRAM_FIFO36_DOBDOU6", + "BRAM_R_IMUX_ADDRBWRADDRL13", + "BRAM_R_IMUX_ADDRBWRADDRL3", + "BRAM_IMUX18_2", + "BRAM_FIFO36_TSTRDOS9", + "BRAM_IMUX26_4", + "BRAM_IMUX44_1", + "BRAM_IMUX5_UTURN_2", + "BRAM_LOGIC_OUTS_B2_4", + "BRAM_IMUX34_UTURN_4", + "BRAM_RAMB18_WEA3", + "BRAM_IMUX16_UTURN_4", + "BRAM_IMUX13_1", + "BRAM_EE4B1_2", + "BRAM_LOGIC_OUTS_B19_4", + "BRAM_IMUX36_3", + "BRAM_EE4A0_3", + "BRAM_NE4C1_2", + "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "BRAM_SW4A1_3", + "BRAM_IMUX22_UTURN_1", + "BRAM_IMUX45_3", + "BRAM_EE2A3_3", + "BRAM_RAMB18_WEBWE6", + "BRAM_IMUX47_1", + "BRAM_WL1END3_2", + "BRAM_LOGIC_OUTS_B1_0", + "BRAM_LH8_0", + "BRAM_UTURN_ADDRBWRADDRL9", + "BRAM_FAN3_0", + "BRAM_IMUX1_2", + "BRAM_WR1END1_0", + "BRAM_NE4C0_2", + "BRAM_FIFO36_DOBDOL10", + "BRAM_CTRL0_1", + "BRAM_SE4C2_1", + "BRAM_IMUX9_UTURN_1", + "BRAM_R_IMUX_ADDRARDADDRU8", + "BRAM_IMUX9_1", + "BRAM_ADDRBWRADDRU6", + "BRAM_FIFO36_ADDRBWRADDRL7", + "BRAM_IMUX3_3", + "BRAM_LOGIC_OUTS_B16_0", + "BRAM_FIFO36_ADDRBWRADDRU5", + "BRAM_IMUX11_UTURN_1", + "BRAM_IMUX29_UTURN_0", + "BRAM_SW4END2_3", + "BRAM_FIFO36_ADDRARDADDRU9", + "BRAM_IMUX40_UTURN_4", + "BRAM_CASCOUT_ADDRARDADDRU10", + "BRAM_IMUX44_UTURN_4", + "BRAM_RAMB18_ADDRBWRADDR11", + "BRAM_WW4END0_2", + "BRAM_WW2A3_4", + "BRAM_WR1END2_4", + "BRAM_IMUX18_UTURN_4", + "BRAM_FIFO18_ADDRARDADDR13", + "BRAM_EE2BEG3_0", + "BRAM_WR1END2_3", + "BRAM_RAMB18_DIADI3", + "BRAM_FAN2_0", + "BRAM_ER1BEG3_0", + "BRAM_IMUX40_1", + "BRAM_FIFO36_DOADOL3", + "BRAM_UTURN_ADDRBWRADDRL6", + "BRAM_WW4B1_4", + "BRAM_UTURN_ADDRARDADDRL10", + "BRAM_NE4C3_1", + "BRAM_UTURN_ADDRARDADDRU13", + "BRAM_NE4BEG2_1", + "BRAM_CASCINBOT_ADDRBWRADDRU3", + "BRAM_RAMB18_CLKARDCLK", + "BRAM_BYP1_2", + "BRAM_FIFO18_ADDRBWRADDR5", + "BRAM_EE4C2_3", + "BRAM_IMUX13_UTURN_3", + "BRAM_IMUX36_2", + "BRAM_CASCOUT_ADDRBWRADDRU0", + "BRAM_RAMB18_DOPBDOP1", + "BRAM_LH3_1", + "BRAM_RAMB18_DOADO3", + "BRAM_CASCOUT_ADDRARDADDRU7", + "BRAM_WL1END2_2", + "BRAM_RAMB18_DOBDO8", + "BRAM_NE4BEG3_4", + "BRAM_FIFO36_DOADOU2", + "BRAM_WW2A0_0", + "BRAM_EE4BEG1_3", + "BRAM_FIFO36_CASCADEOUTB_1", + "BRAM_NE4BEG1_0", + "BRAM_FIFO18_ADDRARDADDR4", + "BRAM_SE4BEG3_0", + "BRAM_FIFO36_DOADOU9", + "BRAM_FIFO36_REGCEAREGCEU", + "BRAM_FIFO18_ADDRBWRADDR1", + "BRAM_EE4B0_0", + "BRAM_SW4END3_2", + "BRAM_NW2A0_4", + "BRAM_CASCOUT_ADDRBWRADDRU12", + "BRAM_SE4C1_4", + "BRAM_BYP5_2", + "BRAM_FIFO36_TSTCNT0", + "BRAM_LH1_3", + "BRAM_LH6_2", + "BRAM_IMUX47_3", + "BRAM_FIFO36_WRCOUNT6", + "BRAM_FIFO36_DOBDOL5", + "BRAM_R_IMUX_ADDRBWRADDRU0", + "BRAM_LH3_2", + "BRAM_WR1END0_2", + "BRAM_SW4END0_3", + "BRAM_NW4END0_4", + "BRAM_LOGIC_OUTS_B21_1", + "BRAM_R_IMUX_ADDRBWRADDRU5", + "BRAM_RAMB18_DIBDI15", + "BRAM_FIFO36_RSTRAMBU", + "BRAM_WW2END2_0", + "BRAM_NW4END2_0", + "BRAM_UTURN_ADDRBWRADDRL1", + "BRAM_RAMB18_DIBDI7", + "BRAM_CLK0_4", + "BRAM_FIFO36_DOPBDOPU1", + "BRAM_WW4END0_4", + "BRAM_IMUX43_3", + "BRAM_NW2A1_3", + "BRAM_FIFO18_ADDRARDADDR3", + "BRAM_FIFO18_DIADI6", + "BRAM_NE2A2_4", + "BRAM_FIFO36_DIBDIU1", + "BRAM_FIFO18_RDCOUNT3", + "BRAM_BYP2_4", + "BRAM_RAMB18_DOADO4", + "BRAM_CASCOUT_ADDRARDADDRU12", + "BRAM_IMUX28_UTURN_3", + "BRAM_FIFO36_ADDRBWRADDRU13", + "BRAM_WW4B1_1", + "BRAM_FIFO36_ALMOSTFULL", + "BRAM_FIFO18_RSTREGARSTREG", + "BRAM_IMUX26_UTURN_1", + "BRAM_WW4B0_1", + "BRAM_WW2A2_2", + "BRAM_NE2A1_2", + "BRAM_LOGIC_OUTS_B17_4", + "BRAM_FIFO36_DOADOL12", + "BRAM_FAN7_4", + "BRAM_WW4END2_2", + "BRAM_FIFO36_ECCPARITY3", + "BRAM_IMUX47_2", + "BRAM_NW4A1_0", + "BRAM_NE2A0_1", + "BRAM_SE2A2_2", + "BRAM_IMUX35_3", + "BRAM_UTURN_ADDRBWRADDRL15", + "BRAM_FAN6_4", + "BRAM_SE2A0_0", + "BRAM_WW2END3_0", + "BRAM_ADDRBWRADDRL5", + "BRAM_IMUX20_UTURN_1", + "BRAM_FIFO18_DOBDO11", + "BRAM_RAMB18_DIBDI14", + "BRAM_LH4_4", + "BRAM_IMUX45_1", + "BRAM_FIFO36_DOBDOU15", + "BRAM_FIFO36_WEAU3", + "BRAM_EE2A3_2", + "BRAM_NW4END0_3", + "BRAM_FIFO36_ADDRARDADDRL12", + "BRAM_WW2A0_1", + "BRAM_WW4C3_1", + "BRAM_FIFO36_DOBDOL4", + "BRAM_R_IMUX_ADDRARDADDRL10", + "BRAM_FIFO36_DIADIL12", + "BRAM_SE4C2_0", + "BRAM_FIFO36_DIADIU4", + "BRAM_FIFO36_TSTRDOS0", + "BRAM_FIFO36_DIPBDIPL0", + "BRAM_IMUX4_UTURN_2", + "BRAM_FAN4_2", + "BRAM_SW4A0_3", + "BRAM_EE4BEG3_1", + "BRAM_CASCOUT_ADDRARDADDRU3", + "BRAM_SW2A3_4", + "BRAM_EL1BEG1_0", + "BRAM_BYP4_4", + "BRAM_IMUX29_UTURN_4", + "BRAM_LOGIC_OUTS_B13_2", + "BRAM_EL1BEG0_1", + "BRAM_R_IMUX_ADDRBWRADDRU4", + "BRAM_NE4C1_3", + "BRAM_FIFO18_ADDRARDADDR11", + "BRAM_PMVBRAM_ODIV4", + "BRAM_R_IMUX_ADDRARDADDRU9", + "BRAM_LH1_2", + "BRAM_IMUX0_UTURN_3", + "BRAM_FIFO36_REGCLKARDRCLKL", + "BRAM_IMUX20_UTURN_0", + "BRAM_R_IMUX_ADDRBWRADDRU12", + "BRAM_WW2A0_4", + "BRAM_NE4C3_4", + "BRAM_FIFO36_TSTIN0", + "BRAM_FIFO36_DIPBDIPU0", + "BRAM_NE4C0_3", + "BRAM_SW2A0_1", + "BRAM_EE2BEG2_3", + "BRAM_SE2A2_0", + "BRAM_BLOCK_OUTS_L_B1_0", + "BRAM_BLOCK_OUTS_L_B1_3", + "BRAM_RAMB18_WRCOUNT6", + "BRAM_FIFO18_DIADI10", + "BRAM_FIFO36_ALMOSTEMPTY", + "BRAM_RAMB18_WEBWE2", + "BRAM_MONITOR_N_2", + "BRAM_UTURN_ADDRBWRADDRU12", + "BRAM_FIFO36_DOBDOU2", + "BRAM_IMUX25_UTURN_4", + "BRAM_R_IMUX_ADDRBWRADDRU7", + "BRAM_FIFO36_DBITERR", + "BRAM_SE4C2_4", + "BRAM_NE4C2_0", + "BRAM_FIFO18_WRCOUNT4", + "BRAM_RAMB18_REGCLKB", + "BRAM_BYP1_1", + "BRAM_IMUX32_UTURN_1", + "BRAM_RAMB18_ADDRBWRADDR9", + "BRAM_IMUX44_3", + "BRAM_FIFO36_RDCOUNT8", + "BRAM_IMUX46_UTURN_4", + "BRAM_WW2A1_4", + "BRAM_FIFO18_DOBDO9", + "BRAM_LOGIC_OUTS_B0_4", + "BRAM_FIFO36_DIBDIL10", + "BRAM_SE4BEG3_3", + "BRAM_ER1BEG2_0", + "BRAM_EE4BEG3_3", + "BRAM_FIFO36_DOBDOL3", + "BRAM_LOGIC_OUTS_B1_3", + "BRAM_IMUX7_UTURN_0", + "BRAM_IMUX41_UTURN_2", + "BRAM_EE4B1_3", + "BRAM_IMUX14_1", + "BRAM_FIFO18_DIBDI9", + "BRAM_FIFO18_WRCOUNT0", + "BRAM_SE2A2_3", + "BRAM_RAMB18_DIBDI5", + "BRAM_LOGIC_OUTS_B8_1", + "BRAM_WL1END0_4", + "BRAM_RAMB18_DIADI0", + "BRAM_ADDRBWRADDRL10", + "BRAM_BYP3_3", + "BRAM_IMUX26_3", + "BRAM_FIFO36_WEBWEL1", + "BRAM_IMUX5_0", + "BRAM_ADDRBWRADDRU4", + "BRAM_UTURN_ADDRARDADDRU6", + "BRAM_R_IMUX_ADDRARDADDRL4", + "BRAM_IMUX29_2", + "BRAM_R_IMUX_ADDRARDADDRU12", + "BRAM_FIFO36_TSTRDOS1", + "BRAM_IMUX12_3", + "BRAM_BYP4_2", + "BRAM_IMUX8_UTURN_3", + "BRAM_LOGIC_OUTS_B9_4", + "BRAM_FIFO36_ECCPARITY0", + "BRAM_RAMB18_DOBDO11", + "BRAM_CASCOUT_ADDRARDADDRU0", + "BRAM_EE4C2_1", + "BRAM_WW4END2_1", + "BRAM_IMUX33_2", + "BRAM_RAMB18_ADDRARDADDR11", + "BRAM_EL1BEG0_3", + "BRAM_LOGIC_OUTS_B22_0", + "BRAM_IMUX18_3", + "BRAM_LOGIC_OUTS_B16_3", + "BRAM_ADDRARDADDRU7", + "BRAM_LOGIC_OUTS_B11_1", + "BRAM_NW2A2_2", + "BRAM_SW2A0_2", + "BRAM_LOGIC_OUTS_B21_2", + "BRAM_LH12_4", + "BRAM_LH3_4", + "BRAM_ADDRBWRADDRL14", + "BRAM_FIFO36_ECCPARITY1", + "BRAM_FIFO36_CASCADEOUTA", + "BRAM_FIFO18_ADDRARDADDR7", + "BRAM_R_IMUX_ADDRARDADDRU14", + "BRAM_IMUX15_4", + "BRAM_IMUX46_UTURN_2", + "BRAM_FIFO18_DIBDI8", + "BRAM_RAMB18_DOBDO2", + "BRAM_IMUX34_UTURN_0", + "BRAM_RAMB18_ADDRARDADDR7", + "BRAM_LOGIC_OUTS_B3_2", + "BRAM_MONITOR_N_0", + "BRAM_LOGIC_OUTS_B19_0", + "BRAM_IMUX5_UTURN_4", + "BRAM_EE2BEG1_2", + "BRAM_EE4C2_4", + "BRAM_SE4BEG1_0", + "BRAM_IMUX13_2", + "BRAM_BLOCK_OUTS_L_B2_4", + "BRAM_MONITOR_P_2", + "BRAM_RAMB18_RDCOUNT6", + "BRAM_EE4A0_0", + "BRAM_SE4BEG2_3", + "BRAM_WL1END2_1", + "BRAM_FIFO18_FULL", + "BRAM_UTURN_ADDRARDADDRU8", + "BRAM_IMUX4_1", + "BRAM_IMUX2_UTURN_3", + "BRAM_EE4BEG1_0", + "BRAM_LH11_3", + "BRAM_WW4C2_2", + "BRAM_WW4C1_1", + "BRAM_CASCOUT_ADDRARDADDRU5", + "BRAM_WW4B3_3", + "BRAM_IMUX1_UTURN_0", + "BRAM_FAN5_2", + "BRAM_FIFO18_DOADO7", + "BRAM_FIFO36_ADDRARDADDRU10", + "BRAM_IMUX14_3", + "BRAM_UTURN_ADDRARDADDRU12", + "BRAM_FIFO18_ADDRARDADDR8", + "BRAM_FIFO36_ECCPARITY7", + "BRAM_EE4C0_2", + "BRAM_IMUX30_0", + "BRAM_FIFO36_WEAU0", + "BRAM_FIFO18_ADDRBWRADDR13", + "BRAM_FIFO36_DIBDIL11", + "BRAM_RAMB18_ADDRBWRADDR13", + "BRAM_FIFO36_TSTCNT4", + "BRAM_IMUX16_UTURN_0", + "BRAM_FIFO36_TSTRDOS11", + "BRAM_EL1BEG3_2", + "BRAM_LH6_4", + "BRAM_CASCOUT_ADDRBWRADDRU13", + "BRAM_FIFO36_DOBDOU3", + "BRAM_RAMB18_DOBDO0", + "BRAM_FIFO36_TSTCNT11", + "BRAM_RAMB18_WRCOUNT9", + "BRAM_IMUX36_4", + "BRAM_PMVBRAM_ODIV2", + "BRAM_MONITOR_P_3", + "BRAM_FIFO18_REGCLKB", + "BRAM_SE4BEG0_2", + "BRAM_FIFO36_TSTRDOS7", + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRAM_NE4BEG1_4", + "BRAM_FIFO36_RDCOUNT9", + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRAM_WW4B0_2", + "BRAM_LH10_3", + "BRAM_IMUX13_4", + "BRAM_UTURN_ADDRARDADDRL1", + "BRAM_RAMB18_DOADO1", + "BRAM_RAMB18_DOADO14", + "BRAM_FIFO18_ENARDEN", + "BRAM_NW4END2_4", + "BRAM_R_IMUX_ADDRARDADDRL1", + "BRAM_FIFO36_ADDRBWRADDRL14", + "BRAM_IMUX12_2", + "BRAM_IMUX12_UTURN_4", + "BRAM_ER1BEG2_3", + "BRAM_EE4BEG1_1", + "BRAM_EE4A3_3", + "BRAM_WW2END3_4", + "BRAM_LOGIC_OUTS_B8_0", + "BRAM_UTURN_ADDRARDADDRU7", + "BRAM_SE4C1_2", + "BRAM_WW4END2_3", + "BRAM_IMUX15_1", + "BRAM_LH5_1", + "BRAM_IMUX30_UTURN_1", + "BRAM_IMUX17_2", + "BRAM_ADDRBWRADDRU9", + "BRAM_EE4C2_0", + "BRAM_FIFO18_DOBDO10", + "BRAM_IMUX36_UTURN_0", + "BRAM_LOGIC_OUTS_B18_4", + "BRAM_IMUX39_4", + "BRAM_LOGIC_OUTS_B5_4", + "BRAM_WR1END2_1", + "BRAM_FIFO36_ADDRARDADDRL0", + "BRAM_LH7_3", + "BRAM_NE4BEG0_0", + "BRAM_IMUX35_UTURN_3", + "BRAM_WL1END1_2", + "BRAM_SE2A1_0", + "BRAM_IMUX7_UTURN_2", + "BRAM_NE4BEG3_3", + "BRAM_LOGIC_OUTS_B7_3", + "BRAM_IMUX40_3", + "BRAM_LOGIC_OUTS_B19_3", + "BRAM_RAMB18_DOADO13", + "BRAM_FIFO18_DIBDI14", + "BRAM_EE4BEG0_3", + "BRAM_UTURN_ADDRARDADDRL7", + "BRAM_FIFO36_WEAL0", + "BRAM_IMUX2_3", + "BRAM_IMUX7_UTURN_3", + "BRAM_UTURN_ADDRARDADDRU1", + "BRAM_RAMB18_RDCOUNT7", + "BRAM_EE2BEG2_1", + "BRAM_IMUX41_UTURN_4", + "BRAM_IMUX19_UTURN_4", + "BRAM_BYP3_2", + "BRAM_LOGIC_OUTS_B4_0", + "BRAM_IMUX44_UTURN_0", + "BRAM_IMUX43_UTURN_3", + "BRAM_NW4END3_3", + "BRAM_ADDRARDADDRU3", + "BRAM_R_IMUX_ADDRARDADDRU11", + "BRAM_IMUX22_3", + "BRAM_RAMB18_DOBDO5", + "BRAM_IMUX45_0", + "BRAM_WW4B1_3", + "BRAM_SW2A2_4", + "BRAM_FIFO36_WRCOUNT0", + "BRAM_IMUX7_UTURN_4", + "BRAM_CTRL1_4", + "BRAM_R_IMUX_ADDRARDADDRU13", + "BRAM_WW4C0_0", + "BRAM_EE4A3_2", + "BRAM_IMUX31_UTURN_4", + "BRAM_ADDRARDADDRU5", + "BRAM_SE4BEG3_1", + "BRAM_FIFO36_RSTREGARSTREGL", + "BRAM_NE4C2_4", + "BRAM_LH3_3", + "BRAM_SE4BEG1_4", + "BRAM_IMUX24_0", + "BRAM_NW4END1_2", + "BRAM_IMUX26_2", + "BRAM_EE2A3_1", + "BRAM_LOGIC_OUTS_B22_4", + "BRAM_CASCOUT_ADDRBWRADDRU8", + "BRAM_EE4A3_1", + "BRAM_ADDRARDADDRL8", + "BRAM_FIFO36_DOBDOL1", + "BRAM_FIFO36_ADDRARDADDRU1", + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRAM_NW2A1_2", + "BRAM_IMUX43_UTURN_2", + "BRAM_MONITOR_N_1", + "BRAM_FAN3_1", + "BRAM_WW4C1_2", + "BRAM_NE2A1_4", + "BRAM_FIFO18_RDCOUNT0", + "BRAM_WL1END2_0", + "BRAM_IMUX38_UTURN_0", + "BRAM_FIFO36_DIBDIU0", + "BRAM_FIFO36_WEBWEU6", + "BRAM_FIFO36_ADDRARDADDRL1", + "BRAM_NW4A1_3", + "BRAM_IMUX6_UTURN_2", + "BRAM_FIFO36_DOBDOU9", + "BRAM_FIFO36_DIADIL7", + "BRAM_NW4A2_3", + "BRAM_RAMB18_DIADI14", + "BRAM_EE4A3_0", + "BRAM_SE4BEG2_0", + "BRAM_IMUX11_UTURN_2", + "BRAM_NE4BEG3_1", + "BRAM_FIFO36_REGCEBL", + "BRAM_FIFO18_ALMOSTEMPTY", + "BRAM_FIFO18_ADDRARDADDR2", + "BRAM_IMUX1_UTURN_1", + "BRAM_EE4B2_4", + "BRAM_FIFO36_DIBDIU7", + "BRAM_SW2A1_0", + "BRAM_R_IMUX_ADDRBWRADDRL2", + "BRAM_FIFO36_TSTRDOS10", + "BRAM_IMUX31_UTURN_1", + "BRAM_IMUX10_UTURN_2", + "BRAM_FIFO18_DIADI15", + "BRAM_FIFO36_RDCOUNT1", + "BRAM_SW4A2_2", + "BRAM_LH2_0", + "BRAM_IMUX20_UTURN_4", + "BRAM_IMUX24_3", + "BRAM_FIFO36_WEAL2", + "BRAM_UTURN_ADDRARDADDRL11", + "BRAM_RAMB18_DIBDI2", + "BRAM_EL1BEG1_3", + "BRAM_NW2A0_2", + "BRAM_FIFO18_WRCOUNT5", + "BRAM_EE4BEG2_2", + "BRAM_RAMB18_WEBWE7", + "BRAM_FIFO36_DOADOL14", + "BRAM_RAMB18_ADDRARDADDR9", + "BRAM_IMUX33_UTURN_2", + "BRAM_IMUX14_UTURN_2", + "BRAM_IMUX46_UTURN_0", + "BRAM_R_IMUX_ADDRARDADDRL12", + "BRAM_UTURN_ADDRBWRADDRL0", + "BRAM_FIFO18_DOPBDOP1", + "BRAM_FIFO36_DIADIU6", + "BRAM_FIFO18_DIBDI13", + "BRAM_LOGIC_OUTS_B13_4", + "BRAM_IMUX6_2", + "BRAM_FIFO18_RDCOUNT8", + "BRAM_RAMB18_ADDRBWRADDR3", + "BRAM_LOGIC_OUTS_B18_2", + "BRAM_SE4BEG0_3", + "BRAM_LH6_0", + "BRAM_WW4A3_2", + "BRAM_FIFO18_EMPTY", + "BRAM_FIFO18_ADDRATIEHIGH0", + "BRAM_EE4A0_4", + "BRAM_FIFO36_WEBWEU0", + "BRAM_EE2A3_0", + "BRAM_FIFO36_DIBDIL9", + "BRAM_SW4A2_3", + "BRAM_FIFO36_DIPBDIPL1", + "BRAM_FIFO18_DIADI5", + "BRAM_SW4END2_2", + "BRAM_IMUX17_0", + "BRAM_IMUX38_UTURN_1", + "BRAM_UTURN_ADDRARDADDRL6", + "BRAM_IMUX42_3", + "BRAM_FIFO36_DIADIL13", + "BRAM_CASCINBOT_ADDRBWRADDRU6", + "BRAM_NE4BEG1_3", + "BRAM_EE4B3_0", + "BRAM_ADDRBWRADDRL1", + "BRAM_IMUX34_UTURN_3", + "BRAM_SW4A0_4", + "BRAM_PMVBRAM_O", + "BRAM_FIFO18_WRCOUNT2", + "BRAM_FIFO18_DOPBDOP0", + "BRAM_UTURN_ADDRBWRADDRU0", + "BRAM_IMUX_R_ADDRARDADDRL15", + "BRAM_UTURN_ADDRBWRADDRL3", + "BRAM_RAMB18_DIADI15", + "BRAM_SE4BEG0_1", + "BRAM_WW2END0_1", + "BRAM_ER1BEG0_2", + "BRAM_LOGIC_OUTS_B0_0", + "BRAM_FIFO36_DIADIU2", + "BRAM_WR1END3_4", + "BRAM_FIFO18_WRCOUNT1", + "BRAM_EL1BEG3_0", + "BRAM_FAN5_4", + "BRAM_FIFO36_WEBWEU3", + "BRAM_WW4A2_0", + "BRAM_FIFO36_DOADOL15", + "BRAM_IMUX30_UTURN_4", + "BRAM_UTURN_ADDRARDADDRL3", + "BRAM_WR1END3_3", + "BRAM_WL1END3_4", + "BRAM_NW4END3_1", + "BRAM_IMUX0_UTURN_1", + "BRAM_LOGIC_OUTS_B16_2", + "BRAM_LH9_4", + "BRAM_WW4B3_4", + "BRAM_FIFO36_DIBDIU2", + "BRAM_FIFO36_ADDRARDADDRL13", + "BRAM_IMUX24_2", + "BRAM_EL1BEG1_2", + "BRAM_FIFO36_TSTRDOS2", + "BRAM_WW4END3_1", + "BRAM_WR1END2_2", + "BRAM_NW4A3_2", + "BRAM_WW4B2_0", + "BRAM_BYP7_0", + "BRAM_IMUX11_UTURN_0", + "BRAM_FIFO36_DOADOU11", + "BRAM_IMUX27_UTURN_2", + "BRAM_RAMB18_WRCOUNT10", + "BRAM_RAMB18_DIADI9", + "BRAM_FIFO36_DIADIU15", + "BRAM_IMUX32_3", + "BRAM_NE4BEG0_1", + "BRAM_WW2A1_1", + "BRAM_EL1BEG3_4", + "BRAM_LOGIC_OUTS_B14_4", + "BRAM_IMUX30_4", + "BRAM_FIFO36_ADDRARDADDRL15", + "BRAM_LOGIC_OUTS_B4_2", + "BRAM_R_IMUX_ADDRARDADDRL5", + "BRAM_FIFO36_TSTIN3", + "BRAM_LOGIC_OUTS_B23_3", + "BRAM_FIFO36_DIBDIL2", + "BRAM_UTURN_ADDRBWRADDRL12", + "BRAM_RAMB18_DIPBDIP0", + "BRAM_IMUX30_3", + "BRAM_FIFO36_RDCOUNT2", + "BRAM_R_IMUX_ADDRBWRADDRL12", + "BRAM_EE4C0_4", + "BRAM_FIFO18_DOPADOP0", + "BRAM_ADDRARDADDRU8", + "BRAM_FIFO36_DOBDOL6", + "BRAM_CLK0_0", + "BRAM_EL1BEG0_2", + "BRAM_WW4END2_0", + "BRAM_IMUX35_0", + "BRAM_BYP3_0", + "BRAM_UTURN_ADDRARDADDRU2", + "BRAM_FIFO36_TSTOUT4", + "BRAM_FIFO36_WEBWEU4", + "BRAM_IMUX41_UTURN_1", + "BRAM_FIFO36_ENBWRENL", + "BRAM_FIFO36_DIADIL15", + "BRAM_LOGIC_OUTS_B11_0", + "BRAM_ADDRARDADDRU10", + "BRAM_IMUX33_3", + "BRAM_LOGIC_OUTS_B23_4", + "BRAM_R_IMUX_ADDRBWRADDRU6", + "BRAM_FIFO18_DOADO5", + "BRAM_IMUX26_0", + "BRAM_ADDRARDADDRU4", + "BRAM_IMUX4_UTURN_0", + "BRAM_SE2A1_2", + "BRAM_FIFO36_DOADOU15", + "BRAM_BYP6_4", + "BRAM_NE2A1_3", + "BRAM_FIFO36_DIBDIL7", + "BRAM_RAMB18_ADDRARDADDR12", + "BRAM_IMUX15_UTURN_2", + "BRAM_FIFO36_TSTIN2", + "BRAM_PMVBRAM_O_2", + "BRAM_LOGIC_OUTS_B8_3", + "BRAM_NW4END2_3", + "BRAM_IMUX23_3", + "BRAM_FIFO36_REGCLKBU", + "BRAM_FIFO36_ADDRBWRADDRU8", + "BRAM_IMUX12_UTURN_1", + "BRAM_FIFO36_DIBDIU15", + "BRAM_FIFO36_TSTWROS6", + "BRAM_CASCINBOT_ADDRBWRADDRU14", + "BRAM_FIFO36_TSTWROS5", + "BRAM_R_IMUX_ADDRBWRADDRU9", + "BRAM_RAMB18_ADDRARDADDR8", + "BRAM_SE2A2_4", + "BRAM_LH3_0", + "BRAM_ADDRARDADDRL5", + "BRAM_FIFO36_ADDRBWRADDRU14", + "BRAM_IMUX20_1", + "BRAM_SW4A2_1", + "BRAM_EE2A2_2", + "BRAM_IMUX45_UTURN_4", + "BRAM_FIFO36_DOADOU8", + "BRAM_RAMB18_ADDRBWRADDR8", + "BRAM_IMUX9_UTURN_2", + "BRAM_EE4B2_3", + "BRAM_IMUX19_1", + "BRAM_FIFO36_TSTOUT2", + "BRAM_SE4C0_3", + "BRAM_ADDRARDADDRU6", + "BRAM_NW4A1_2", + "BRAM_ADDRBWRADDRL8", + "BRAM_FIFO36_RDCOUNT5", + "BRAM_R_IMUX_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3", + "BRAM_WW2A1_2", + "BRAM_FAN2_2", + "BRAM_IMUX27_4", + "BRAM_EE4BEG2_1", + "BRAM_LOGIC_OUTS_B12_3", + "BRAM_RAMB18_WRCOUNT1", + "BRAM_FIFO18_CLKBWRCLK", + "BRAM_NW4A2_4", + "BRAM_SW4END1_4", + "BRAM_IMUX12_4", + "BRAM_SE2A3_3", + "BRAM_BYP4_3", + "BRAM_WW4C3_3", + "BRAM_IMUX20_UTURN_3", + "BRAM_IMUX30_UTURN_3", + "BRAM_EE4C3_4", + "BRAM_WW2A2_0", + "BRAM_BYP7_1", + "BRAM_ADDRARDADDRL3", + "BRAM_SE2A3_0", + "BRAM_CASCINBOT_ADDRARDADDRU13", + "BRAM_FIFO36_TSTWROS12", + "BRAM_SW4END3_4", + "BRAM_IMUX8_UTURN_1", + "BRAM_FIFO18_DOBDO0", + "BRAM_MONITOR_P_1", + "BRAM_IMUX36_UTURN_4", + "BRAM_IMUX14_UTURN_0", + "BRAM_FIFO36_ADDRARDADDRU11", + "BRAM_FIFO36_DOADOL5", + "BRAM_FIFO36_ADDRBWRADDRU4", + "BRAM_LOGIC_OUTS_B8_4", + "BRAM_UTURN_ADDRARDADDRL8", + "BRAM_ADDRARDADDRL1", + "BRAM_WL1END1_3", + "BRAM_CASCINBOT_ADDRARDADDRU2", + "BRAM_IMUX33_4", + "BRAM_SW2A2_0", + "BRAM_SW4END3_3", + "BRAM_IMUX13_UTURN_1", + "BRAM_LH1_0", + "BRAM_LOGIC_OUTS_B3_3", + "BRAM_R_IMUX_ADDRARDADDRL3", + "BRAM_FIFO36_DIADIL8", + "BRAM_IMUX28_2", + "BRAM_FIFO36_DOBDOL13", + "BRAM_IMUX21_UTURN_3", + "BRAM_FIFO36_DIBDIU4", + "BRAM_LOGIC_OUTS_B20_2", + "BRAM_IMUX40_0", + "BRAM_IMUX31_UTURN_0", + "BRAM_IMUX27_1", + "BRAM_FIFO36_ADDRARDADDRU14", + "BRAM_SW2A1_4", + "BRAM_WR1END1_1", + "BRAM_IMUX37_2", + "BRAM_IMUX37_4", + "BRAM_WW4B1_0", + "BRAM_UTURN_ADDRBWRADDRL7", + "BRAM_RAMB18_DIADI2", + "BRAM_MONITOR_P_0", + "BRAM_IMUX46_UTURN_1", + "BRAM_FIFO36_RDCOUNT0", + "BRAM_IMUX26_UTURN_4", + "BRAM_IMUX3_0", + "BRAM_WR1END1_3", + "BRAM_RAMB18_DOADO9", + "BRAM_IMUX43_0", + "BRAM_LOGIC_OUTS_B19_2", + "BRAM_RAMB18_DIADI8", + "BRAM_FIFO18_RSTRAMB", + "BRAM_BLOCK_OUTS_L_B2_0", + "BRAM_RAMB18_DOBDO12", + "BRAM_EE4A2_0", + "BRAM_EE4BEG0_0", + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRAM_FIFO18_WRCOUNT6", + "BRAM_FIFO18_WEBWE3", + "BRAM_WW2END1_1", + "BRAM_SE4C3_0", + "BRAM_IMUX0_0", + "BRAM_IMUX27_UTURN_1", + "BRAM_IMUX15_0", + "BRAM_SE2A0_2", + "BRAM_UTURN_ADDRBWRADDRU6", + "BRAM_FIFO18_ADDRBTIEHIGH1", + "BRAM_IMUX25_UTURN_2", + "BRAM_IMUX45_2", + "BRAM_RAMB18_ADDRARDADDR0", + "BRAM_IMUX4_2", + "BRAM_WW2END0_3", + "BRAM_NE4BEG2_3", + "BRAM_LH5_3", + "BRAM_RAMB18_REGCEAREGCE", + "BRAM_IMUX17_4", + "BRAM_WW4A0_0", + "BRAM_NE2A0_3", + "BRAM_WL1END3_3", + "BRAM_RAMB18_DIADI13", + "BRAM_RAMB18_ADDRATIEHIGH0", + "BRAM_LOGIC_OUTS_B4_4", + "BRAM_SW4END3_0", + "BRAM_R_IMUX_ADDRBWRADDRL14", + "BRAM_IMUX18_UTURN_1", + "BRAM_CLK1_0", + "BRAM_WW4C2_0", + "BRAM_IMUX19_2", + "BRAM_ADDRARDADDRL2", + "BRAM_FIFO18_WRCOUNT7", + "BRAM_WR1END3_2", + "BRAM_FAN5_0", + "BRAM_LOGIC_OUTS_B13_0", + "BRAM_FIFO36_WEBWEL3", + "BRAM_NE4C0_4", + "BRAM_LOGIC_OUTS_B9_2", + "BRAM_FIFO36_ADDRBWRADDRU11", + "BRAM_IMUX41_0", + "BRAM_IMUX9_3", + "BRAM_NW4A1_4", + "BRAM_IMUX19_UTURN_1", + "BRAM_LH6_1", + "BRAM_NE4BEG2_2", + "BRAM_FIFO36_WEBWEU1", + "BRAM_FIFO36_WRCOUNT4", + "BRAM_NW4END0_0", + "BRAM_LOGIC_OUTS_B13_3", + "BRAM_IMUX4_0", + "BRAM_IMUX6_UTURN_4", + "BRAM_LH11_1", + "BRAM_CLK0_2", + "BRAM_PMVBRAM_ODIV2_1", + "BRAM_IMUX2_UTURN_2", + "BRAM_NW4A2_1", + "BRAM_LH5_4", + "BRAM_IMUX23_UTURN_4", + "BRAM_EE4B0_2", + "BRAM_RAMB18_DIADI12", + "BRAM_RAMB18_ALMOSTEMPTY", + "BRAM_IMUX28_0", + "BRAM_IMUX21_4", + "BRAM_WW2A0_3", + "BRAM_IMUX7_UTURN_1", + "BRAM_CASCOUT_ADDRBWRADDRU6", + "BRAM_WW4C1_3", + "BRAM_WW4END0_1", + "BRAM_IMUX40_4", + "BRAM_IMUX20_0", + "BRAM_EE4B3_1", + "BRAM_PMVBRAM_SELECT3", + "BRAM_LOGIC_OUTS_B23_1", + "BRAM_IMUX22_UTURN_2", + "BRAM_IMUX36_1", + "BRAM_BYP5_0", + "BRAM_FIFO18_DIBDI11", + "BRAM_FIFO18_WEBWE1", + "BRAM_UTURN_ADDRBWRADDRL13", + "BRAM_WW4END2_4", + "BRAM_WW4C3_2", + "BRAM_WW2A3_0", + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRAM_IMUX28_UTURN_2", + "BRAM_EE2A0_1", + "BRAM_FIFO18_DOADO10", + "BRAM_FIFO36_DIBDIU9", + "BRAM_LOGIC_OUTS_B20_0", + "BRAM_IMUX44_0", + "BRAM_FIFO18_WRCOUNT11", + "BRAM_FIFO36_DOADOL4", + "BRAM_IMUX27_3", + "BRAM_RAMB18_RDCOUNT5", + "BRAM_ER1BEG2_1", + "BRAM_LOGIC_OUTS_B6_3", + "BRAM_BLOCK_OUTS_L_B0_2", + "BRAM_FIFO36_TSTWRCNTOFF", + "BRAM_FIFO36_CLKARDCLKL", + "BRAM_MONITOR_N_4", + "BRAM_IMUX8_0", + "BRAM_CTRL0_3", + "BRAM_LOGIC_OUTS_B12_2", + "BRAM_IMUX47_UTURN_2", + "BRAM_WW2A2_1", + "BRAM_FAN1_4", + "BRAM_BLOCK_OUTS_L_B3_1" + ], + "tile_type": "BRAM_R", + "sites": [ + { + "site_pins": { + "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", + "DIADI2": "BRAM_FIFO18_DIADI2", + "DO4": "BRAM_FIFO18_DOADO4", + "DIADI3": "BRAM_FIFO18_DIADI3", + "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", + "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", + "WEBWE1": "BRAM_FIFO18_WEBWE1", + "DIBDI2": "BRAM_FIFO18_DIBDI2", + "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", + "DIBDI6": "BRAM_FIFO18_DIBDI6", + "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", + "DO12": "BRAM_FIFO18_DOADO12", + "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", + "DIADI1": "BRAM_FIFO18_DIADI1", + "DO17": "BRAM_FIFO18_DOBDO1", + "DO10": "BRAM_FIFO18_DOADO10", + "DIBDI4": "BRAM_FIFO18_DIBDI4", + "EMPTY": "BRAM_FIFO18_EMPTY", + "DIADI5": "BRAM_FIFO18_DIADI5", + "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", + "RDERR": "BRAM_FIFO18_RDERR", + "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", + "DIADI13": "BRAM_FIFO18_DIADI13", + "WEBWE0": "BRAM_FIFO18_WEBWE0", + "DO24": "BRAM_FIFO18_DOBDO8", + "DO18": "BRAM_FIFO18_DOBDO2", + "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", + "DIBDI12": "BRAM_FIFO18_DIBDI12", + "DIBDI13": "BRAM_FIFO18_DIBDI13", + "DIADI7": "BRAM_FIFO18_DIADI7", + "DO30": "BRAM_FIFO18_DOBDO14", + "ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0", + "DO16": "BRAM_FIFO18_DOBDO0", + "DOP0": "BRAM_FIFO18_DOPADOP0", + "RSTREGB": "BRAM_FIFO18_RSTREGB", + "REGCE": "BRAM_FIFO18_REGCEAREGCE", + "DO20": "BRAM_FIFO18_DOBDO4", + "DO3": "BRAM_FIFO18_DOADO3", + "WRCOUNT4": "BRAM_FIFO18_WRCOUNT4", + "DO0": "BRAM_FIFO18_DOADO0", + "WRCOUNT8": "BRAM_FIFO18_WRCOUNT8", + "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", + "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", + "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", + "DIBDI11": "BRAM_FIFO18_DIBDI11", + "DO14": "BRAM_FIFO18_DOADO14", + "DIADI6": "BRAM_FIFO18_DIADI6", + "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", + "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", + "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", + "DIBDI0": "BRAM_FIFO18_DIBDI0", + "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", + "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", + "WEA3": "BRAM_FIFO18_WEA3", + "DO26": "BRAM_FIFO18_DOBDO10", + "DIBDI14": "BRAM_FIFO18_DIBDI14", + "DO23": "BRAM_FIFO18_DOBDO7", + "REGCLKB": "BRAM_FIFO18_REGCLKB", + "WREN": "BRAM_FIFO18_ENBWREN", + "WRCOUNT1": "BRAM_FIFO18_WRCOUNT1", + "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", + "DIPADIP1": "BRAM_FIFO18_DIPADIP1", + "RST": "BRAM_FIFO18_RSTRAMARSTRAM", + "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", + "DIPADIP0": "BRAM_FIFO18_DIPADIP0", + "DIADI8": "BRAM_FIFO18_DIADI8", + "WRCOUNT9": "BRAM_FIFO18_WRCOUNT9", + "DO27": "BRAM_FIFO18_DOBDO11", + "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", + "DO31": "BRAM_FIFO18_DOBDO15", + "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", + "DO22": "BRAM_FIFO18_DOBDO6", + "WRCOUNT7": "BRAM_FIFO18_WRCOUNT7", + "DIADI11": "BRAM_FIFO18_DIADI11", + "DO8": "BRAM_FIFO18_DOADO8", + "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", + "DIBDI9": "BRAM_FIFO18_DIBDI9", + "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12", + "DIBDI15": "BRAM_FIFO18_DIBDI15", + "WEA0": "BRAM_FIFO18_WEA0", + "RDCLK": "BRAM_FIFO18_CLKARDCLK", + "WRCOUNT10": "BRAM_FIFO18_WRCOUNT10", + "DOP1": "BRAM_FIFO18_DOPADOP1", + "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", + "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", + "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", + "WRCLK": "BRAM_FIFO18_CLKBWRCLK", + "DO19": "BRAM_FIFO18_DOBDO3", + "DO9": "BRAM_FIFO18_DOADO9", + "DIADI0": "BRAM_FIFO18_DIADI0", + "DIADI12": "BRAM_FIFO18_DIADI12", + "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", + "WRCOUNT0": "BRAM_FIFO18_WRCOUNT0", + "DIBDI7": "BRAM_FIFO18_DIBDI7", + "WEBWE2": "BRAM_FIFO18_WEBWE2", + "DIADI4": "BRAM_FIFO18_DIADI4", + "FULL": "BRAM_FIFO18_FULL", + "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", + "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", + "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", + "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", + "DIBDI1": "BRAM_FIFO18_DIBDI1", + "WRCOUNT3": "BRAM_FIFO18_WRCOUNT3", + "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", + "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", + "DIBDI5": "BRAM_FIFO18_DIBDI5", + "DIADI10": "BRAM_FIFO18_DIADI10", + "WRERR": "BRAM_FIFO18_WRERR", + "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", + "DO29": "BRAM_FIFO18_DOBDO13", + "WEA2": "BRAM_FIFO18_WEA2", + "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", + "WEBWE3": "BRAM_FIFO18_WEBWE3", + "DOP3": "BRAM_FIFO18_DOPBDOP1", + "DO13": "BRAM_FIFO18_DOADO13", + "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", + "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", + "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", + "RDEN": "BRAM_FIFO18_ENARDEN", + "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", + "DIADI15": "BRAM_FIFO18_DIADI15", + "DO1": "BRAM_FIFO18_DOADO1", + "DO15": "BRAM_FIFO18_DOADO15", + "WEBWE4": "BRAM_FIFO18_WEBWE4", + "DO5": "BRAM_FIFO18_DOADO5", + "WRCOUNT11": "BRAM_FIFO18_WRCOUNT11", + "DIBDI3": "BRAM_FIFO18_DIBDI3", + "DO7": "BRAM_FIFO18_DOADO7", + "WEBWE5": "BRAM_FIFO18_WEBWE5", + "DO28": "BRAM_FIFO18_DOBDO12", + "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", + "WRCOUNT2": "BRAM_FIFO18_WRCOUNT2", + "WRCOUNT5": "BRAM_FIFO18_WRCOUNT5", + "DIADI14": "BRAM_FIFO18_DIADI14", + "DO11": "BRAM_FIFO18_DOADO11", + "DIBDI10": "BRAM_FIFO18_DIBDI10", + "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", + "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", + "DOP2": "BRAM_FIFO18_DOPBDOP0", + "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", + "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", + "DO25": "BRAM_FIFO18_DOBDO9", + "REGCEB": "BRAM_FIFO18_REGCEB", + "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", + "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", + "WEBWE7": "BRAM_FIFO18_WEBWE7", + "DIBDI8": "BRAM_FIFO18_DIBDI8", + "DO2": "BRAM_FIFO18_DOADO2", + "DO21": "BRAM_FIFO18_DOBDO5", + "DIADI9": "BRAM_FIFO18_DIADI9", + "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", + "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", + "WEBWE6": "BRAM_FIFO18_WEBWE6", + "RSTRAMB": "BRAM_FIFO18_RSTRAMB", + "WEA1": "BRAM_FIFO18_WEA1", + "WRCOUNT6": "BRAM_FIFO18_WRCOUNT6", + "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", + "DO6": "BRAM_FIFO18_DOADO6" + }, + "type": "FIFO18E1", + "prefix": "RAMB18", + "name": "X0Y19", + "x_coord": 0, + "y_coord": 19 + }, + { + "site_pins": { + "DOBDO3": "BRAM_RAMB18_DOBDO3", + "ADDRBWRADDR13": "BRAM_RAMB18_ADDRBWRADDR13", + "DOADO7": "BRAM_RAMB18_DOADO7", + "DIADI2": "BRAM_RAMB18_DIADI2", + "ENBWREN": "BRAM_RAMB18_ENBWREN", + "DIADI3": "BRAM_RAMB18_DIADI3", + "RDCOUNT3": "BRAM_RAMB18_RDCOUNT3", + "WEBWE1": "BRAM_RAMB18_WEBWE1", + "RSTRAMARSTRAM": "BRAM_RAMB18_RSTRAMARSTRAM", + "ADDRBWRADDR5": "BRAM_RAMB18_ADDRBWRADDR5", + "DIBDI6": "BRAM_RAMB18_DIBDI6", + "ADDRATIEHIGH0": "BRAM_RAMB18_ADDRATIEHIGH0", + "DOBDO14": "BRAM_RAMB18_DOBDO14", + "DIPBDIP0": "BRAM_RAMB18_DIPBDIP0", + "DIADI1": "BRAM_RAMB18_DIADI1", + "RDCOUNT8": "BRAM_RAMB18_RDCOUNT8", + "DIBDI4": "BRAM_RAMB18_DIBDI4", + "EMPTY": "BRAM_RAMB18_EMPTY", + "DIADI5": "BRAM_RAMB18_DIADI5", + "RDCOUNT2": "BRAM_RAMB18_RDCOUNT2", + "DOADO6": "BRAM_RAMB18_DOADO6", + "ADDRARDADDR3": "BRAM_RAMB18_ADDRARDADDR3", + "DIADI13": "BRAM_RAMB18_DIADI13", + "WEBWE0": "BRAM_RAMB18_WEBWE0", + "DOADO5": "BRAM_RAMB18_DOADO5", + "RDCOUNT0": "BRAM_RAMB18_RDCOUNT0", + "DIBDI13": "BRAM_RAMB18_DIBDI13", + "DIADI7": "BRAM_RAMB18_DIADI7", + "ADDRARDADDR1": "BRAM_RAMB18_ADDRARDADDR1", + "DOADO1": "BRAM_RAMB18_DOADO1", + "ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0", + "RSTREGARSTREG": "BRAM_RAMB18_RSTREGARSTREG", + "RSTREGB": "BRAM_RAMB18_RSTREGB", + "DOADO3": "BRAM_RAMB18_DOADO3", + "DOBDO0": "BRAM_RAMB18_DOBDO0", + "DIBDI11": "BRAM_RAMB18_DIBDI11", + "DIADI6": "BRAM_RAMB18_DIADI6", + "DOPBDOP1": "BRAM_RAMB18_DOPBDOP1", + "FULL": "BRAM_RAMB18_FULL", + "ADDRBWRADDR6": "BRAM_RAMB18_ADDRBWRADDR6", + "ADDRBWRADDR12": "BRAM_RAMB18_ADDRBWRADDR12", + "DIBDI0": "BRAM_RAMB18_DIBDI0", + "RDCOUNT11": "BRAM_RAMB18_RDCOUNT11", + "DOBDO9": "BRAM_RAMB18_DOBDO9", + "WRCOUNT11": "BRAM_RAMB18_WRCOUNT11", + "WEA3": "BRAM_RAMB18_WEA3", + "WEA2": "BRAM_RAMB18_WEA2", + "DOADO9": "BRAM_RAMB18_DOADO9", + "DIBDI14": "BRAM_RAMB18_DIBDI14", + "DOPADOP1": "BRAM_RAMB18_DOPADOP1", + "REGCLKB": "BRAM_RAMB18_REGCLKB", + "DIBDI2": "BRAM_RAMB18_DIBDI2", + "WRCOUNT1": "BRAM_RAMB18_WRCOUNT1", + "ADDRBWRADDR10": "BRAM_RAMB18_ADDRBWRADDR10", + "DIPADIP1": "BRAM_RAMB18_DIPADIP1", + "DOBDO10": "BRAM_RAMB18_DOBDO10", + "ADDRARDADDR8": "BRAM_RAMB18_ADDRARDADDR8", + "ENARDEN": "BRAM_RAMB18_ENARDEN", + "DIPADIP0": "BRAM_RAMB18_DIPADIP0", + "DIADI8": "BRAM_RAMB18_DIADI8", + "WRCOUNT9": "BRAM_RAMB18_WRCOUNT9", + "ADDRBWRADDR2": "BRAM_RAMB18_ADDRBWRADDR2", + "ALMOSTEMPTY": "BRAM_RAMB18_ALMOSTEMPTY", + "ADDRARDADDR13": "BRAM_RAMB18_ADDRARDADDR13", + "WEBWE4": "BRAM_RAMB18_WEBWE4", + "DOBDO11": "BRAM_RAMB18_DOBDO11", + "WRCOUNT7": "BRAM_RAMB18_WRCOUNT7", + "DOADO14": "BRAM_RAMB18_DOADO14", + "DOBDO12": "BRAM_RAMB18_DOBDO12", + "WRCOUNT8": "BRAM_RAMB18_WRCOUNT8", + "WRCOUNT4": "BRAM_RAMB18_WRCOUNT4", + "RDCOUNT4": "BRAM_RAMB18_RDCOUNT4", + "DIBDI9": "BRAM_RAMB18_DIBDI9", + "ADDRARDADDR12": "BRAM_RAMB18_ADDRARDADDR12", + "REGCEAREGCE": "BRAM_RAMB18_REGCEAREGCE", + "CLKBWRCLK": "BRAM_RAMB18_CLKBWRCLK", + "DIBDI15": "BRAM_RAMB18_DIBDI15", + "DOADO15": "BRAM_RAMB18_DOADO15", + "WEA0": "BRAM_RAMB18_WEA0", + "DOBDO13": "BRAM_RAMB18_DOBDO13", + "WRCOUNT10": "BRAM_RAMB18_WRCOUNT10", + "RDCOUNT9": "BRAM_RAMB18_RDCOUNT9", + "ADDRBWRADDR9": "BRAM_RAMB18_ADDRBWRADDR9", + "ADDRBWRADDR8": "BRAM_RAMB18_ADDRBWRADDR8", + "CLKARDCLK": "BRAM_RAMB18_CLKARDCLK", + "ADDRBWRADDR4": "BRAM_RAMB18_ADDRBWRADDR4", + "DIADI12": "BRAM_RAMB18_DIADI12", + "DIADI0": "BRAM_RAMB18_DIADI0", + "DIBDI7": "BRAM_RAMB18_DIBDI7", + "WEBWE2": "BRAM_RAMB18_WEBWE2", + "DIADI4": "BRAM_RAMB18_DIADI4", + "RDCOUNT10": "BRAM_RAMB18_RDCOUNT10", + "ADDRBWRADDR1": "BRAM_RAMB18_ADDRBWRADDR1", + "ADDRARDADDR4": "BRAM_RAMB18_ADDRARDADDR4", + "ADDRBWRADDR0": "BRAM_RAMB18_ADDRBWRADDR0", + "ADDRBWRADDR7": "BRAM_RAMB18_ADDRBWRADDR7", + "DIBDI1": "BRAM_RAMB18_DIBDI1", + "WRCOUNT3": "BRAM_RAMB18_WRCOUNT3", + "DOBDO5": "BRAM_RAMB18_DOBDO5", + "DIPBDIP1": "BRAM_RAMB18_DIPBDIP1", + "ADDRATIEHIGH1": "BRAM_RAMB18_ADDRATIEHIGH1", + "DIBDI5": "BRAM_RAMB18_DIBDI5", + "DIADI10": "BRAM_RAMB18_DIADI10", + "WRERR": "BRAM_RAMB18_WRERR", + "RDCOUNT6": "BRAM_RAMB18_RDCOUNT6", + "ALMOSTFULL": "BRAM_RAMB18_ALMOSTFULL", + "DOPADOP0": "BRAM_RAMB18_DOPADOP0", + "DOBDO4": "BRAM_RAMB18_DOBDO4", + "ADDRBTIEHIGH1": "BRAM_RAMB18_ADDRBTIEHIGH1", + "WEBWE3": "BRAM_RAMB18_WEBWE3", + "ADDRARDADDR7": "BRAM_RAMB18_ADDRARDADDR7", + "ADDRARDADDR11": "BRAM_RAMB18_ADDRARDADDR11", + "ADDRBWRADDR11": "BRAM_RAMB18_ADDRBWRADDR11", + "RDERR": "BRAM_RAMB18_RDERR", + "DOADO13": "BRAM_RAMB18_DOADO13", + "ADDRARDADDR10": "BRAM_RAMB18_ADDRARDADDR10", + "DIADI15": "BRAM_RAMB18_DIADI15", + "DOBDO7": "BRAM_RAMB18_DOBDO7", + "DOPBDOP0": "BRAM_RAMB18_DOPBDOP0", + "DOADO0": "BRAM_RAMB18_DOADO0", + "REGCEB": "BRAM_RAMB18_REGCEB", + "WEBWE5": "BRAM_RAMB18_WEBWE5", + "REGCLKARDRCLK": "BRAM_RAMB18_REGCLKARDRCLK", + "DOADO12": "BRAM_RAMB18_DOADO12", + "DIADI11": "BRAM_RAMB18_DIADI11", + "ADDRARDADDR2": "BRAM_RAMB18_ADDRARDADDR2", + "WRCOUNT2": "BRAM_RAMB18_WRCOUNT2", + "WRCOUNT5": "BRAM_RAMB18_WRCOUNT5", + "DIADI14": "BRAM_RAMB18_DIADI14", + "DIBDI10": "BRAM_RAMB18_DIBDI10", + "DOADO2": "BRAM_RAMB18_DOADO2", + "ADDRBWRADDR3": "BRAM_RAMB18_ADDRBWRADDR3", + "ADDRARDADDR5": "BRAM_RAMB18_ADDRARDADDR5", + "DIBDI12": "BRAM_RAMB18_DIBDI12", + "ADDRARDADDR9": "BRAM_RAMB18_ADDRARDADDR9", + "RDCOUNT7": "BRAM_RAMB18_RDCOUNT7", + "DOADO4": "BRAM_RAMB18_DOADO4", + "RDCOUNT1": "BRAM_RAMB18_RDCOUNT1", + "DOADO8": "BRAM_RAMB18_DOADO8", + "DOBDO1": "BRAM_RAMB18_DOBDO1", + "WEBWE7": "BRAM_RAMB18_WEBWE7", + "DIBDI8": "BRAM_RAMB18_DIBDI8", + "DOBDO8": "BRAM_RAMB18_DOBDO8", + "DOADO10": "BRAM_RAMB18_DOADO10", + "DOBDO6": "BRAM_RAMB18_DOBDO6", + "DOADO11": "BRAM_RAMB18_DOADO11", + "WRCOUNT0": "BRAM_RAMB18_WRCOUNT0", + "DIADI9": "BRAM_RAMB18_DIADI9", + "DOBDO2": "BRAM_RAMB18_DOBDO2", + "RDCOUNT5": "BRAM_RAMB18_RDCOUNT5", + "ADDRARDADDR6": "BRAM_RAMB18_ADDRARDADDR6", + "WEBWE6": "BRAM_RAMB18_WEBWE6", + "DOBDO15": "BRAM_RAMB18_DOBDO15", + "RSTRAMB": "BRAM_RAMB18_RSTRAMB", + "DIBDI3": "BRAM_RAMB18_DIBDI3", + "WEA1": "BRAM_RAMB18_WEA1", + "WRCOUNT6": "BRAM_RAMB18_WRCOUNT6", + "ADDRBTIEHIGH0": "BRAM_RAMB18_ADDRBTIEHIGH0" + }, + "type": "RAMB18E1", + "prefix": "RAMB18", + "name": "X0Y20", + "x_coord": 0, + "y_coord": 20 + }, + { + "site_pins": { + "WEBWEL6": "BRAM_FIFO36_WEBWEL6", + "DOBDO3": "BRAM_FIFO36_DOBDOU1", + "DOADO7": "BRAM_FIFO36_DOADOU3", + "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", + "TSTWROS11": "BRAM_FIFO36_TSTWROS11", + "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", + "DIADI25": "BRAM_FIFO36_DIADIU12", + "TSTIN4": "BRAM_FIFO36_TSTIN4", + "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", + "DOBDO17": "BRAM_FIFO36_DOBDOU8", + "WEBWEU5": "BRAM_FIFO36_WEBWEU5", + "WRCOUNT9": "BRAM_FIFO36_WRCOUNT9", + "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", + "WEAU2": "BRAM_FIFO36_WEAU2", + "DIBDI28": "BRAM_FIFO36_DIBDIL14", + "DIBDI6": "BRAM_FIFO36_DIBDIL3", + "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", + "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", + "TSTCNT8": "BRAM_FIFO36_TSTCNT8", + "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", + "EMPTY": "BRAM_FIFO36_EMPTY", + "DIADI5": "BRAM_FIFO36_DIADIU2", + "DOADO21": "BRAM_FIFO36_DOADOU10", + "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", + "DOADO6": "BRAM_FIFO36_DOADOL3", + "REGCLKBU": "BRAM_FIFO36_REGCLKBU", + "DIADI2": "BRAM_FIFO36_DIADIL1", + "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", + "DOADO5": "BRAM_FIFO36_DOADOU2", + "SBITERR": "BRAM_FIFO36_SBITERR", + "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", + "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", + "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", + "DOADO1": "BRAM_FIFO36_DOADOU0", + "DOADO16": "BRAM_FIFO36_DOADOL8", + "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", + "TSTWROS10": "BRAM_FIFO36_TSTWROS10", + "TSTWROS12": "BRAM_FIFO36_TSTWROS12", + "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", + "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", + "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", + "TSTCNT11": "BRAM_FIFO36_TSTCNT11", + "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", + "DOBDO22": "BRAM_FIFO36_DOBDOL11", + "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", + "WEBWEL4": "BRAM_FIFO36_WEBWEL4", + "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", + "TSTOUT2": "BRAM_FIFO36_TSTOUT2", + "DIADI6": "BRAM_FIFO36_DIADIL3", + "TSTCNT2": "BRAM_FIFO36_TSTCNT2", + "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", + "TSTWROS3": "BRAM_FIFO36_TSTWROS3", + "FULL": "BRAM_FIFO36_FULL", + "ENARDENL": "BRAM_FIFO36_ENARDENL", + "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", + "DIADI10": "BRAM_FIFO36_DIADIL5", + "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", + "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", + "DOADO18": "BRAM_FIFO36_DOADOL9", + "DIBDI31": "BRAM_FIFO36_DIBDIU15", + "DOBDO18": "BRAM_FIFO36_DOBDOL9", + "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", + "WEBWEU6": "BRAM_FIFO36_WEBWEU6", + "DOADO26": "BRAM_FIFO36_DOADOL13", + "TSTCNT12": "BRAM_FIFO36_TSTCNT12", + "DOADO30": "BRAM_FIFO36_DOADOL15", + "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", + "DOADO31": "BRAM_FIFO36_DOADOU15", + "DIBDI14": "BRAM_FIFO36_DIBDIL7", + "REGCEBL": "BRAM_FIFO36_REGCEBL", + "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", + "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", + "TSTWROS6": "BRAM_FIFO36_TSTWROS6", + "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", + "DIADI7": "BRAM_FIFO36_DIADIU3", + "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", + "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", + "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", + "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", + "DOBDO10": "BRAM_FIFO36_DOBDOL5", + "WEBWEL5": "BRAM_FIFO36_WEBWEL5", + "WEBWEU0": "BRAM_FIFO36_WEBWEU0", + "TSTWROS2": "BRAM_FIFO36_TSTWROS2", + "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", + "DOADO23": "BRAM_FIFO36_DOADOU11", + "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", + "DOBDO21": "BRAM_FIFO36_DOBDOU10", + "DIADI22": "BRAM_FIFO36_DIADIL11", + "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", + "TSTWROS9": "BRAM_FIFO36_TSTWROS9", + "DOBDO11": "BRAM_FIFO36_DOBDOU5", + "WEBWEU1": "BRAM_FIFO36_WEBWEU1", + "DOADO19": "BRAM_FIFO36_DOADOU9", + "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", + "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", + "TSTIN2": "BRAM_FIFO36_TSTIN2", + "DOBDO1": "BRAM_FIFO36_DOBDOU0", + "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", + "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", + "DIBDI9": "BRAM_FIFO36_DIBDIU4", + "DOBDO20": "BRAM_FIFO36_DOBDOL10", + "TSTOUT3": "BRAM_FIFO36_TSTOUT3", + "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", + "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", + "DOADO15": "BRAM_FIFO36_DOADOU7", + "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", + "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", + "DIBDI20": "BRAM_FIFO36_DIBDIL10", + "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", + "DIADI28": "BRAM_FIFO36_DIADIL14", + "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", + "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", + "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", + "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", + "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", + "DOBDO30": "BRAM_FIFO36_DOBDOL15", + "DOADO2": "BRAM_FIFO36_DOADOL1", + "DIADI0": "BRAM_FIFO36_DIADIL0", + "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", + "DOBDO23": "BRAM_FIFO36_DOBDOU11", + "TSTCNT10": "BRAM_FIFO36_TSTCNT10", + "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", + "DIBDI7": "BRAM_FIFO36_DIBDIU3", + "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", + "DIADI4": "BRAM_FIFO36_DIADIL2", + "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", + "WEBWEU3": "BRAM_FIFO36_WEBWEU3", + "DIBDI26": "BRAM_FIFO36_DIBDIL13", + "DOADO25": "BRAM_FIFO36_DOADOU12", + "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", + "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", + "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", + "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTB", + "CASCADEINB": "BRAM_FIFO36_CASCADEINA", + "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", + "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", + "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", + "DIADI21": "BRAM_FIFO36_DIADIU10", + "RDERR": "BRAM_FIFO36_RDERR", + "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", + "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", + "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", + "WEBWEL1": "BRAM_FIFO36_WEBWEL1", + "TSTOFF": "BRAM_FIFO36_TSTOFF", + "DOBDO15": "BRAM_FIFO36_DOBDOU7", + "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", + "DOADO0": "BRAM_FIFO36_DOADOL0", + "DIBDI30": "BRAM_FIFO36_DIBDIL15", + "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", + "DIADI11": "BRAM_FIFO36_DIADIU5", + "RSTREGBU": "BRAM_FIFO36_RSTREGBU", + "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", + "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", + "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", + "WEBWEU7": "BRAM_FIFO36_WEBWEU7", + "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", + "TSTCNT0": "BRAM_FIFO36_TSTCNT0", + "WEAU3": "BRAM_FIFO36_WEAU3", + "TSTWROS0": "BRAM_FIFO36_TSTWROS0", + "ENBWRENU": "BRAM_FIFO36_ENBWRENU", + "WEAL3": "BRAM_FIFO36_WEAL3", + "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", + "TSTOUT4": "BRAM_FIFO36_TSTOUT4", + "DIBDI8": "BRAM_FIFO36_DIBDIL4", + "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", + "DOBDO8": "BRAM_FIFO36_DOBDOL4", + "REGCEBU": "BRAM_FIFO36_REGCEBU", + "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", + "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", + "DOBDO2": "BRAM_FIFO36_DOBDOL1", + "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", + "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", + "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", + "DIADI19": "BRAM_FIFO36_DIADIU9", + "DOBDO25": "BRAM_FIFO36_DOBDOU12", + "DIBDI3": "BRAM_FIFO36_DIBDIU1", + "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", + "DOBDO12": "BRAM_FIFO36_DOBDOL6", + "WEAL1": "BRAM_FIFO36_WEAL1", + "TSTCNT6": "BRAM_FIFO36_TSTCNT6", + "DOBDO29": "BRAM_FIFO36_DOBDOU14", + "DOBDO14": "BRAM_FIFO36_DOBDOL7", + "DIADI13": "BRAM_FIFO36_DIADIU6", + "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", + "WEBWEL7": "BRAM_FIFO36_WEBWEL7", + "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", + "DIBDI18": "BRAM_FIFO36_DIBDIL9", + "DIADI30": "BRAM_FIFO36_DIADIL15", + "DIADI3": "BRAM_FIFO36_DIADIU1", + "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", + "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", + "DIADI27": "BRAM_FIFO36_DIADIU13", + "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", + "REGCLKBL": "BRAM_FIFO36_REGCLKBL", + "DIBDI17": "BRAM_FIFO36_DIBDIU8", + "TSTIN0": "BRAM_FIFO36_TSTIN0", + "DOADO29": "BRAM_FIFO36_DOADOU14", + "DIADI1": "BRAM_FIFO36_DIADIU0", + "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", + "DIBDI4": "BRAM_FIFO36_DIBDIL2", + "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", + "DOADO28": "BRAM_FIFO36_DOADOL14", + "WEBWEL3": "BRAM_FIFO36_WEBWEL3", + "TSTWROS4": "BRAM_FIFO36_TSTWROS4", + "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", + "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", + "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", + "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", + "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", + "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", + "TSTCNT7": "BRAM_FIFO36_TSTCNT7", + "DIBDI23": "BRAM_FIFO36_DIBDIU11", + "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", + "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", + "DIADI26": "BRAM_FIFO36_DIADIL13", + "DOADO22": "BRAM_FIFO36_DOADOL11", + "DOADO4": "BRAM_FIFO36_DOADOL2", + "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", + "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", + "WRCOUNT8": "BRAM_FIFO36_WRCOUNT8", + "TSTCNT1": "BRAM_FIFO36_TSTCNT1", + "DIBDI11": "BRAM_FIFO36_DIBDIU5", + "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", + "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", + "DIBDI0": "BRAM_FIFO36_DIBDIL0", + "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", + "TSTWROS8": "BRAM_FIFO36_TSTWROS8", + "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", + "DOBDO9": "BRAM_FIFO36_DOBDOU4", + "WEBWEU2": "BRAM_FIFO36_WEBWEU2", + "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", + "DOBDO0": "BRAM_FIFO36_DOBDOL0", + "DOADO9": "BRAM_FIFO36_DOADOU4", + "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", + "TSTCNT5": "BRAM_FIFO36_TSTCNT5", + "ENBWRENL": "BRAM_FIFO36_ENBWRENL", + "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", + "DIBDI25": "BRAM_FIFO36_DIBDIU12", + "ENARDENU": "BRAM_FIFO36_ENARDENU", + "DIBDI2": "BRAM_FIFO36_DIBDIL1", + "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", + "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", + "WEAL0": "BRAM_FIFO36_WEAL0", + "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", + "DIADI16": "BRAM_FIFO36_DIADIL8", + "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", + "DIADI8": "BRAM_FIFO36_DIADIL4", + "TSTOUT1": "BRAM_FIFO36_TSTOUT1", + "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", + "TSTIN1": "BRAM_FIFO36_TSTIN1", + "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", + "WEBWEL0": "BRAM_FIFO36_WEBWEL0", + "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", + "DOADO17": "BRAM_FIFO36_DOADOU8", + "DOADO14": "BRAM_FIFO36_DOADOL7", + "DOBDO16": "BRAM_FIFO36_DOBDOL8", + "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", + "DIADI9": "BRAM_FIFO36_DIADIU4", + "DIBDI15": "BRAM_FIFO36_DIBDIU7", + "DOBDO26": "BRAM_FIFO36_DOBDOL13", + "WEBWEU4": "BRAM_FIFO36_WEBWEU4", + "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", + "DOBDO13": "BRAM_FIFO36_DOBDOU6", + "DIBDI22": "BRAM_FIFO36_DIBDIL11", + "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", + "DOBDO5": "BRAM_FIFO36_DOBDOU2", + "DIBDI27": "BRAM_FIFO36_DIBDIU13", + "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", + "WEAL2": "BRAM_FIFO36_WEAL2", + "TSTWROS5": "BRAM_FIFO36_TSTWROS5", + "DIADI23": "BRAM_FIFO36_DIADIU11", + "DIBDI29": "BRAM_FIFO36_DIBDIU14", + "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", + "DOBDO19": "BRAM_FIFO36_DOBDOU9", + "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", + "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", + "DIADI12": "BRAM_FIFO36_DIADIL6", + "ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", + "WRCOUNT7": "BRAM_FIFO36_WRCOUNT7", + "WEAU0": "BRAM_FIFO36_WEAU0", + "DIADI31": "BRAM_FIFO36_DIADIU15", + "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", + "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", + "DIBDI13": "BRAM_FIFO36_DIBDIU6", + "TSTCNT3": "BRAM_FIFO36_TSTCNT3", + "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTA", + "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", + "DIBDI1": "BRAM_FIFO36_DIBDIU0", + "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", + "TSTIN3": "BRAM_FIFO36_TSTIN3", + "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", + "DOADO20": "BRAM_FIFO36_DOADOL10", + "DIBDI5": "BRAM_FIFO36_DIBDIU2", + "TSTOUT0": "BRAM_FIFO36_TSTOUT0", + "TSTCNT4": "BRAM_FIFO36_TSTCNT4", + "WRERR": "BRAM_FIFO36_WRERR", + "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", + "DIADI20": "BRAM_FIFO36_DIADIL10", + "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", + "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", + "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", + "DOBDO4": "BRAM_FIFO36_DOBDOL2", + "WEAU1": "BRAM_FIFO36_WEAU1", + "TSTWROS1": "BRAM_FIFO36_TSTWROS1", + "DIBDI24": "BRAM_FIFO36_DIBDIL12", + "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", + "DOBDO24": "BRAM_FIFO36_DOBDOL12", + "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", + "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", + "DOADO13": "BRAM_FIFO36_DOADOU6", + "DIADI18": "BRAM_FIFO36_DIADIL9", + "DIADI29": "BRAM_FIFO36_DIADIU14", + "DIADI15": "BRAM_FIFO36_DIADIU7", + "DOBDO7": "BRAM_FIFO36_DOBDOU3", + "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", + "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", + "DOADO12": "BRAM_FIFO36_DOADOL6", + "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", + "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", + "WEBWEL2": "BRAM_FIFO36_WEBWEL2", + "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", + "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", + "DIADI14": "BRAM_FIFO36_DIADIL7", + "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", + "DIBDI10": "BRAM_FIFO36_DIBDIL5", + "RSTREGBL": "BRAM_FIFO36_RSTREGBL", + "DOADO24": "BRAM_FIFO36_DOADOL12", + "DOADO27": "BRAM_FIFO36_DOADOU13", + "DIBDI12": "BRAM_FIFO36_DIBDIL6", + "DIADI24": "BRAM_FIFO36_DIADIL12", + "DOBDO28": "BRAM_FIFO36_DOBDOL14", + "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", + "DOBDO31": "BRAM_FIFO36_DOBDOU15", + "DOADO3": "BRAM_FIFO36_DOADOU1", + "DBITERR": "BRAM_FIFO36_DBITERR", + "DOADO8": "BRAM_FIFO36_DOADOL4", + "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", + "DIBDI21": "BRAM_FIFO36_DIBDIU10", + "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", + "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", + "CASCADEINA": "BRAM_FIFO36_CASCADEINB", + "DOADO10": "BRAM_FIFO36_DOADOL5", + "DOBDO6": "BRAM_FIFO36_DOBDOL3", + "DIBDI16": "BRAM_FIFO36_DIBDIL8", + "DOADO11": "BRAM_FIFO36_DOADOU5", + "DIBDI19": "BRAM_FIFO36_DIBDIU9", + "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", + "TSTCNT9": "BRAM_FIFO36_TSTCNT9", + "DOBDO27": "BRAM_FIFO36_DOBDOU13", + "TSTWROS7": "BRAM_FIFO36_TSTWROS7", + "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", + "DIADI17": "BRAM_FIFO36_DIADIU8", + "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", + "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", + "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", + "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU" + }, + "type": "RAMBFIFO36E1", + "prefix": "RAMB36", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_BRAM.json b/artix7/tile_type_BRKH_BRAM.json index 7777417..25462f3 100644 --- a/artix7/tile_type_BRKH_BRAM.json +++ b/artix7/tile_type_BRKH_BRAM.json @@ -1,71 +1,71 @@ { + "pips": {}, "wires": [ - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0", - "BRKH_BRAM_CASCADEA_R", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11", - "BRKH_BRAM_CASCADEA_L", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1", - "BRKH_BRAM_CASCADEB_L", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5", - "BRKH_BRAM_CASCADEB_R", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1", + "BRKH_BRAM_CASCADEA_R", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12", + "BRKH_BRAM_CASCADEB_R", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5", + "BRKH_BRAM_CASCADEB_L", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14", + "BRKH_BRAM_CASCADEA_L", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10", + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6", + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1", + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14", + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" ], - "sites": [], - "pips": {}, - "tile_type": "BRKH_BRAM" + "tile_type": "BRKH_BRAM", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_B_TERM_INT.json b/artix7/tile_type_BRKH_B_TERM_INT.json index d7491e1..8d1b793 100644 --- a/artix7/tile_type_BRKH_B_TERM_INT.json +++ b/artix7/tile_type_BRKH_B_TERM_INT.json @@ -1,125 +1,125 @@ { + "pips": {}, "wires": [ - "B_TERM_UTURN_INT_WR1BEG0", - "B_TERM_UTURN_INT_ER1END_N3_3", - "B_TERM_UTURN_INT_LV_L6", - "B_TERM_UTURN_INT_LVB4", - "B_TERM_UTURN_INT_SW6A2", + "B_TERM_UTURN_INT_SW6C0", + "B_TERM_UTURN_INT_LVB_L0", + "B_TERM_UTURN_INT_LVB5", + "B_TERM_UTURN_INT_SE6D3", "B_TERM_UTURN_INT_LV4", - "B_TERM_UTURN_INT_SS2A1", - "B_TERM_UTURN_INT_LV3", - "B_TERM_UTURN_INT_SS6D3", + "B_TERM_UTURN_INT_SS2BEG3", + "B_TERM_UTURN_INT_SS6B1", + "B_TERM_UTURN_INT_SE2BEG0", + "B_TERM_UTURN_INT_LV_L5", + "B_TERM_UTURN_INT_SE6D1", "B_TERM_UTURN_INT_LV2", - "B_TERM_UTURN_INT_LV_L3", + "B_TERM_UTURN_INT_LVB_L2", + "B_TERM_UTURN_INT_SS6BEG3", + "B_TERM_UTURN_INT_LVB1", + "B_TERM_UTURN_INT_SL1BEG2", + "B_TERM_UTURN_INT_SL1BEG1", + "B_TERM_UTURN_INT_SS6BEG1", + "B_TERM_UTURN_INT_LVB2", + "B_TERM_UTURN_INT_SE6A2", + "B_TERM_UTURN_INT_SS6D3", + "B_TERM_UTURN_INT_SS6BEG0", + "B_TERM_UTURN_INT_LV9", + "B_TERM_UTURN_INT_SE2BEG2", + "B_TERM_UTURN_INT_LV_L2", + "B_TERM_UTURN_INT_SE6B2", + "B_TERM_UTURN_INT_LVB_L3", + "B_TERM_UTURN_INT_LV7", + "B_TERM_UTURN_INT_SS6D2", + "B_TERM_UTURN_INT_LVB_L4", + "B_TERM_UTURN_INT_SW6C2", "B_TERM_UTURN_INT_SS6B3", + "B_TERM_UTURN_INT_SS2A1", + "B_TERM_UTURN_INT_SE2BEG1", + "B_TERM_UTURN_INT_SS6A2", + "B_TERM_UTURN_INT_SE6A0", + "B_TERM_UTURN_INT_LV6", + "B_TERM_UTURN_INT_LV_L6", + "B_TERM_UTURN_INT_SS2A2", + "B_TERM_UTURN_INT_WR1BEG0", + "B_TERM_UTURN_INT_SE6B0", + "B_TERM_UTURN_INT_SL1BEG0", + "B_TERM_UTURN_INT_SW6A3", + "B_TERM_UTURN_INT_LVB0", + "B_TERM_UTURN_INT_LVB_L1", + "B_TERM_UTURN_INT_SE6C0", + "B_TERM_UTURN_INT_LV_L9", + "B_TERM_UTURN_INT_SW6B2", + "B_TERM_UTURN_INT_LVB3", + "B_TERM_UTURN_INT_SW2BEG0", + "B_TERM_UTURN_INT_SW6A1", + "B_TERM_UTURN_INT_SE6D2", + "B_TERM_UTURN_INT_LV_L3", + "B_TERM_UTURN_INT_SR1BEG3", + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "B_TERM_UTURN_INT_SW6END_N0_3", + "B_TERM_UTURN_INT_SE6B1", + "B_TERM_UTURN_INT_LV5", + "B_TERM_UTURN_INT_SR1BEG2", + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "B_TERM_UTURN_INT_SW6A2", + "B_TERM_UTURN_INT_SS2BEG2", + "B_TERM_UTURN_INT_SS6D0", + "B_TERM_UTURN_INT_SE6A1", + "B_TERM_UTURN_INT_SS6A0", + "B_TERM_UTURN_INT_SS2BEG1", + "B_TERM_UTURN_INT_SE6C3", + "B_TERM_UTURN_INT_SS6C2", + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "B_TERM_UTURN_INT_SS6A3", + "B_TERM_UTURN_INT_SW6D2", + "B_TERM_UTURN_INT_SS6E3", + "B_TERM_UTURN_INT_SW2BEG2", + "B_TERM_UTURN_INT_LV_L8", + "B_TERM_UTURN_INT_SW6B3", + "B_TERM_UTURN_INT_SW6B1", + "B_TERM_UTURN_INT_SW2BEG1", + "B_TERM_UTURN_INT_LVB4", + "B_TERM_UTURN_INT_SS2BEG0", + "B_TERM_UTURN_INT_SR1BEG1", + "B_TERM_UTURN_INT_SE6C2", + "B_TERM_UTURN_INT_SW2BEG3", + "B_TERM_UTURN_INT_WR1END0", + "B_TERM_UTURN_INT_LV_L7", + "B_TERM_UTURN_INT_SW6D1", + "B_TERM_UTURN_INT_LVB_L5", + "B_TERM_UTURN_INT_SE6C1", + "B_TERM_UTURN_INT_LV18", + "B_TERM_UTURN_INT_SW6D3", + "B_TERM_UTURN_INT_SL1BEG3", + "B_TERM_UTURN_INT_SS6E1", + "B_TERM_UTURN_INT_SW6C3", + "B_TERM_UTURN_INT_SS2A3", + "B_TERM_UTURN_INT_SS6E0", + "B_TERM_UTURN_INT_ER1BEG0", + "B_TERM_UTURN_INT_ER1END_N3_3", + "B_TERM_UTURN_INT_SE6B3", + "B_TERM_UTURN_INT_SS6B2", + "B_TERM_UTURN_INT_SW6B0", + "B_TERM_UTURN_INT_SW6A0", + "B_TERM_UTURN_INT_LV3", + "B_TERM_UTURN_INT_SS6C3", + "B_TERM_UTURN_INT_LV8", + "B_TERM_UTURN_INT_SE6A3", + "B_TERM_UTURN_INT_SS6C1", + "B_TERM_UTURN_INT_SS6B0", + "B_TERM_UTURN_INT_SS6C0", + "B_TERM_UTURN_INT_SW6C1", "B_TERM_UTURN_INT_SS6D1", "B_TERM_UTURN_INT_LV_L4", - "B_TERM_UTURN_INT_SS6C1", - "B_TERM_UTURN_INT_SW6B3", - "B_TERM_UTURN_INT_SS6A3", - "B_TERM_UTURN_INT_ER1BEG0", - "B_TERM_UTURN_INT_SW6D2", - "B_TERM_UTURN_INT_LVB_L5", - "B_TERM_UTURN_INT_SW6D3", - "B_TERM_UTURN_INT_SL1BEG1", - "B_TERM_UTURN_INT_SE6D0", - "B_TERM_UTURN_INT_SE2BEG2", - "B_TERM_UTURN_INT_SS6B0", - "B_TERM_UTURN_INT_SW6A3", - "B_TERM_UTURN_INT_LVB5", - "B_TERM_UTURN_INT_SS6C3", - "B_TERM_UTURN_INT_LV_L5", - "B_TERM_UTURN_INT_SE6A1", - "B_TERM_UTURN_INT_LV_L18", - "B_TERM_UTURN_INT_SS6A0", - "B_TERM_UTURN_INT_SS6C0", - "B_TERM_UTURN_INT_SW6C0", - "B_TERM_UTURN_INT_SS6B1", - "B_TERM_UTURN_INT_SW6B1", - "B_TERM_UTURN_INT_SW6D1", - "B_TERM_UTURN_INT_SS6E0", - "B_TERM_UTURN_INT_LVB3", - "B_TERM_UTURN_INT_SS6BEG0", - "B_TERM_UTURN_INT_SW6A1", - "B_TERM_UTURN_INT_FAN_BOUNCE0", "B_TERM_UTURN_INT_SS2A0", - "B_TERM_UTURN_INT_LV_L8", - "B_TERM_UTURN_INT_SW6C3", - "B_TERM_UTURN_INT_SW2BEG0", - "B_TERM_UTURN_INT_SS2BEG3", - "B_TERM_UTURN_INT_SE6D2", - "B_TERM_UTURN_INT_SE6B1", - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "B_TERM_UTURN_INT_SE2BEG0", - "B_TERM_UTURN_INT_SS6C2", - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "B_TERM_UTURN_INT_SW6B2", - "B_TERM_UTURN_INT_WR1END0", - "B_TERM_UTURN_INT_SS6B2", - "B_TERM_UTURN_INT_SE6C0", - "B_TERM_UTURN_INT_SE6B3", - "B_TERM_UTURN_INT_SE6A0", - "B_TERM_UTURN_INT_SW2BEG3", - "B_TERM_UTURN_INT_LV8", - "B_TERM_UTURN_INT_SS6BEG2", - "B_TERM_UTURN_INT_SW2BEG1", - "B_TERM_UTURN_INT_SS6E3", - "B_TERM_UTURN_INT_SS6E1", - "B_TERM_UTURN_INT_SL1BEG2", - "B_TERM_UTURN_INT_SS6BEG3", - "B_TERM_UTURN_INT_SS6BEG1", - "B_TERM_UTURN_INT_SE2BEG1", - "B_TERM_UTURN_INT_SS2A2", - "B_TERM_UTURN_INT_SS6E2", - "B_TERM_UTURN_INT_LV_L9", - "B_TERM_UTURN_INT_SW6A0", - "B_TERM_UTURN_INT_SW6END_N0_3", - "B_TERM_UTURN_INT_SE6A3", - "B_TERM_UTURN_INT_SE6B2", - "B_TERM_UTURN_INT_SE6D1", - "B_TERM_UTURN_INT_SW6B0", - "B_TERM_UTURN_INT_SR1BEG2", - "B_TERM_UTURN_INT_SE6A2", - "B_TERM_UTURN_INT_LV7", - "B_TERM_UTURN_INT_SW6C2", - "B_TERM_UTURN_INT_SS2BEG1", - "B_TERM_UTURN_INT_LVB_L4", - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "B_TERM_UTURN_INT_LVB_L3", - "B_TERM_UTURN_INT_SE6D3", - "B_TERM_UTURN_INT_LV9", - "B_TERM_UTURN_INT_LV_L7", - "B_TERM_UTURN_INT_SE6C3", - "B_TERM_UTURN_INT_SW6C1", - "B_TERM_UTURN_INT_SE2BEG3", "B_TERM_UTURN_INT_SS6A1", - "B_TERM_UTURN_INT_LV_L2", - "B_TERM_UTURN_INT_LVB_L0", - "B_TERM_UTURN_INT_SS2BEG2", - "B_TERM_UTURN_INT_SR1BEG1", - "B_TERM_UTURN_INT_LVB1", - "B_TERM_UTURN_INT_LVB_L1", - "B_TERM_UTURN_INT_SE6B0", - "B_TERM_UTURN_INT_SS6D0", - "B_TERM_UTURN_INT_LVB2", - "B_TERM_UTURN_INT_SS2BEG0", - "B_TERM_UTURN_INT_LVB0", - "B_TERM_UTURN_INT_SS6D2", - "B_TERM_UTURN_INT_SE6C1", + "B_TERM_UTURN_INT_SS6BEG2", + "B_TERM_UTURN_INT_SS6E2", "B_TERM_UTURN_INT_SW6D0", - "B_TERM_UTURN_INT_SL1BEG0", - "B_TERM_UTURN_INT_LV18", - "B_TERM_UTURN_INT_LV6", - "B_TERM_UTURN_INT_LV5", - "B_TERM_UTURN_INT_SR1BEG3", - "B_TERM_UTURN_INT_LVB_L2", - "B_TERM_UTURN_INT_SL1BEG3", - "B_TERM_UTURN_INT_SW2BEG2", - "B_TERM_UTURN_INT_SS6A2", - "B_TERM_UTURN_INT_SS2A3", - "B_TERM_UTURN_INT_SE6C2" + "B_TERM_UTURN_INT_SE6D0", + "B_TERM_UTURN_INT_LV_L18", + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "B_TERM_UTURN_INT_SE2BEG3" ], - "sites": [], - "pips": {}, - "tile_type": "BRKH_B_TERM_INT" + "tile_type": "BRKH_B_TERM_INT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_CLB.json b/artix7/tile_type_BRKH_CLB.json index 08e6d1f..d9f96f1 100644 --- a/artix7/tile_type_BRKH_CLB.json +++ b/artix7/tile_type_BRKH_CLB.json @@ -1,11 +1,11 @@ { + "pips": {}, "wires": [ - "BRKH_CLB_COUT1_R", - "BRKH_CLB_COUT1_L", "BRKH_CLB_COUT0_L", + "BRKH_CLB_COUT1_L", + "BRKH_CLB_COUT1_R", "BRKH_CLB_COUT0_R" ], - "sites": [], - "pips": {}, - "tile_type": "BRKH_CLB" + "tile_type": "BRKH_CLB", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_CLK.json b/artix7/tile_type_BRKH_CLK.json index 74c8118..64718a4 100644 --- a/artix7/tile_type_BRKH_CLK.json +++ b/artix7/tile_type_BRKH_CLK.json @@ -1,135 +1,135 @@ { + "pips": {}, "wires": [ - "BRKH_CLK_CK_BUFG_CASC23", - "BRKH_CLK_R_CK_GCLK27", - "BRKH_CLK_CK_GCLK4", - "BRKH_CLK_R_CK_BUFG_CASC20", - "BRKH_CLK_CK_GCLK15", - "BRKH_CLK_CK_BUFG_CASC31", - "BRKH_CLK_R_CK_GCLK14", - "BRKH_CLK_CK_GCLK25", - "BRKH_CLK_R_CK_BUFG_CASC14", - "BRKH_CLK_R_CK_GCLK20", - "BRKH_CLK_R_CK_GCLK15", - "BRKH_CLK_R_CK_GCLK3", - "BRKH_CLK_CK_BUFG_CASC17", - "BRKH_CLK_CK_GCLK20", - "BRKH_CLK_R_CK_GCLK25", - "BRKH_CLK_R_CK_GCLK0", - "BRKH_CLK_R_CK_GCLK12", - "BRKH_CLK_R_CK_BUFG_CASC8", - "BRKH_CLK_CK_GCLK28", - "BRKH_CLK_CK_BUFG_CASC20", - "BRKH_CLK_R_CK_BUFG_CASC26", - "BRKH_CLK_CK_BUFG_CASC0", - "BRKH_CLK_R_CK_GCLK16", - "BRKH_CLK_R_CK_GCLK19", - "BRKH_CLK_R_CK_GCLK8", - "BRKH_CLK_CK_GCLK16", - "BRKH_CLK_CK_GCLK29", - "BRKH_CLK_R_CK_GCLK28", - "BRKH_CLK_CK_GCLK17", - "BRKH_CLK_R_CK_GCLK4", "BRKH_CLK_R_CK_BUFG_CASC28", - "BRKH_CLK_R_CK_BUFG_CASC0", - "BRKH_CLK_R_CK_GCLK29", - "BRKH_CLK_R_CK_GCLK17", - "BRKH_CLK_CK_GCLK13", - "BRKH_CLK_R_CK_GCLK21", - "BRKH_CLK_CK_BUFG_CASC12", - "BRKH_CLK_CK_GCLK30", - "BRKH_CLK_R_CK_GCLK22", - "BRKH_CLK_CK_GCLK12", - "BRKH_CLK_CK_BUFG_CASC29", - "BRKH_CLK_CK_BUFG_CASC22", - "BRKH_CLK_R_CK_BUFG_CASC25", - "BRKH_CLK_CK_GCLK6", - "BRKH_CLK_CK_GCLK19", - "BRKH_CLK_R_CK_GCLK13", - "BRKH_CLK_R_CK_BUFG_CASC3", - "BRKH_CLK_R_CK_GCLK30", - "BRKH_CLK_R_CK_GCLK11", - "BRKH_CLK_R_CK_BUFG_CASC27", - "BRKH_CLK_R_CK_BUFG_CASC23", - "BRKH_CLK_R_CK_BUFG_CASC12", - "BRKH_CLK_R_CK_GCLK10", - "BRKH_CLK_CK_GCLK0", - "BRKH_CLK_CK_GCLK11", - "BRKH_CLK_CK_BUFG_CASC6", - "BRKH_CLK_CK_GCLK5", - "BRKH_CLK_CK_GCLK27", - "BRKH_CLK_CK_GCLK23", - "BRKH_CLK_CK_GCLK14", - "BRKH_CLK_CK_BUFG_CASC13", - "BRKH_CLK_CK_BUFG_CASC18", - "BRKH_CLK_CK_BUFG_CASC19", - "BRKH_CLK_CK_GCLK7", - "BRKH_CLK_R_CK_GCLK1", - "BRKH_CLK_R_CK_BUFG_CASC18", - "BRKH_CLK_CK_GCLK1", - "BRKH_CLK_CK_BUFG_CASC30", - "BRKH_CLK_R_CK_GCLK6", - "BRKH_CLK_R_CK_GCLK26", - "BRKH_CLK_CK_GCLK31", - "BRKH_CLK_CK_GCLK24", - "BRKH_CLK_CK_BUFG_CASC14", - "BRKH_CLK_CK_BUFG_CASC8", - "BRKH_CLK_R_CK_BUFG_CASC30", - "BRKH_CLK_CK_BUFG_CASC7", - "BRKH_CLK_R_CK_BUFG_CASC15", - "BRKH_CLK_CK_GCLK26", - "BRKH_CLK_R_CK_BUFG_CASC31", - "BRKH_CLK_CK_BUFG_CASC21", "BRKH_CLK_CK_BUFG_CASC25", - "BRKH_CLK_R_CK_BUFG_CASC29", - "BRKH_CLK_R_CK_BUFG_CASC13", - "BRKH_CLK_CK_GCLK10", - "BRKH_CLK_R_CK_GCLK5", - "BRKH_CLK_R_CK_GCLK18", - "BRKH_CLK_CK_GCLK9", + "BRKH_CLK_CK_BUFG_CASC22", + "BRKH_CLK_R_CK_BUFG_CASC11", + "BRKH_CLK_R_CK_GCLK16", + "BRKH_CLK_CK_BUFG_CASC2", + "BRKH_CLK_R_CK_BUFG_CASC30", + "BRKH_CLK_CK_BUFG_CASC31", "BRKH_CLK_CK_BUFG_CASC5", - "BRKH_CLK_R_CK_BUFG_CASC22", + "BRKH_CLK_CK_GCLK18", + "BRKH_CLK_R_CK_BUFG_CASC18", + "BRKH_CLK_R_CK_GCLK22", + "BRKH_CLK_CK_GCLK0", + "BRKH_CLK_CK_BUFG_CASC7", + "BRKH_CLK_CK_BUFG_CASC16", + "BRKH_CLK_CK_GCLK1", + "BRKH_CLK_CK_GCLK30", + "BRKH_CLK_CK_BUFG_CASC18", + "BRKH_CLK_CK_GCLK6", + "BRKH_CLK_CK_GCLK10", + "BRKH_CLK_R_CK_BUFG_CASC21", + "BRKH_CLK_R_CK_GCLK31", + "BRKH_CLK_CK_BUFG_CASC14", + "BRKH_CLK_R_CK_BUFG_CASC4", "BRKH_CLK_CK_BUFG_CASC11", "BRKH_CLK_CK_GCLK8", - "BRKH_CLK_CK_BUFG_CASC27", - "BRKH_CLK_R_CK_BUFG_CASC21", - "BRKH_CLK_CK_GCLK3", - "BRKH_CLK_R_CK_BUFG_CASC11", - "BRKH_CLK_R_CK_BUFG_CASC7", - "BRKH_CLK_R_CK_BUFG_CASC16", - "BRKH_CLK_R_CK_GCLK23", - "BRKH_CLK_R_CK_GCLK7", - "BRKH_CLK_R_CK_BUFG_CASC24", - "BRKH_CLK_R_CK_BUFG_CASC9", - "BRKH_CLK_R_CK_BUFG_CASC6", - "BRKH_CLK_R_CK_BUFG_CASC17", - "BRKH_CLK_CK_BUFG_CASC24", - "BRKH_CLK_R_CK_BUFG_CASC1", - "BRKH_CLK_CK_BUFG_CASC16", - "BRKH_CLK_CK_BUFG_CASC9", - "BRKH_CLK_CK_BUFG_CASC26", - "BRKH_CLK_CK_BUFG_CASC15", - "BRKH_CLK_R_CK_BUFG_CASC5", - "BRKH_CLK_CK_GCLK22", - "BRKH_CLK_R_CK_GCLK24", - "BRKH_CLK_CK_GCLK21", - "BRKH_CLK_CK_BUFG_CASC28", - "BRKH_CLK_R_CK_GCLK2", - "BRKH_CLK_CK_BUFG_CASC1", - "BRKH_CLK_CK_BUFG_CASC4", - "BRKH_CLK_CK_GCLK18", - "BRKH_CLK_CK_BUFG_CASC2", - "BRKH_CLK_R_CK_GCLK31", - "BRKH_CLK_CK_BUFG_CASC3", - "BRKH_CLK_CK_GCLK2", - "BRKH_CLK_R_CK_BUFG_CASC2", - "BRKH_CLK_CK_BUFG_CASC10", "BRKH_CLK_R_CK_BUFG_CASC10", - "BRKH_CLK_R_CK_BUFG_CASC4", + "BRKH_CLK_R_CK_BUFG_CASC0", + "BRKH_CLK_R_CK_GCLK28", + "BRKH_CLK_CK_GCLK14", + "BRKH_CLK_CK_BUFG_CASC24", + "BRKH_CLK_R_CK_BUFG_CASC24", + "BRKH_CLK_CK_BUFG_CASC0", + "BRKH_CLK_CK_GCLK3", + "BRKH_CLK_R_CK_GCLK8", + "BRKH_CLK_R_CK_GCLK27", + "BRKH_CLK_R_CK_BUFG_CASC9", + "BRKH_CLK_CK_BUFG_CASC9", + "BRKH_CLK_R_CK_BUFG_CASC6", + "BRKH_CLK_R_CK_GCLK18", + "BRKH_CLK_CK_GCLK19", + "BRKH_CLK_CK_GCLK21", + "BRKH_CLK_CK_BUFG_CASC27", + "BRKH_CLK_CK_GCLK2", + "BRKH_CLK_R_CK_BUFG_CASC29", + "BRKH_CLK_R_CK_GCLK3", + "BRKH_CLK_R_CK_BUFG_CASC17", + "BRKH_CLK_R_CK_GCLK12", + "BRKH_CLK_CK_BUFG_CASC28", + "BRKH_CLK_R_CK_GCLK10", + "BRKH_CLK_R_CK_BUFG_CASC26", + "BRKH_CLK_R_CK_GCLK19", + "BRKH_CLK_CK_BUFG_CASC4", + "BRKH_CLK_R_CK_BUFG_CASC13", + "BRKH_CLK_CK_BUFG_CASC17", + "BRKH_CLK_CK_BUFG_CASC1", + "BRKH_CLK_CK_GCLK24", + "BRKH_CLK_CK_GCLK12", + "BRKH_CLK_CK_GCLK9", + "BRKH_CLK_R_CK_GCLK17", + "BRKH_CLK_R_CK_BUFG_CASC8", + "BRKH_CLK_CK_GCLK11", + "BRKH_CLK_R_CK_BUFG_CASC31", + "BRKH_CLK_R_CK_BUFG_CASC27", + "BRKH_CLK_CK_GCLK28", + "BRKH_CLK_CK_BUFG_CASC13", + "BRKH_CLK_CK_BUFG_CASC20", "BRKH_CLK_R_CK_BUFG_CASC19", - "BRKH_CLK_R_CK_GCLK9" + "BRKH_CLK_R_CK_GCLK29", + "BRKH_CLK_CK_GCLK7", + "BRKH_CLK_R_CK_GCLK23", + "BRKH_CLK_R_CK_BUFG_CASC20", + "BRKH_CLK_CK_BUFG_CASC21", + "BRKH_CLK_CK_BUFG_CASC30", + "BRKH_CLK_CK_BUFG_CASC19", + "BRKH_CLK_R_CK_BUFG_CASC2", + "BRKH_CLK_R_CK_BUFG_CASC23", + "BRKH_CLK_R_CK_BUFG_CASC7", + "BRKH_CLK_R_CK_BUFG_CASC1", + "BRKH_CLK_CK_BUFG_CASC3", + "BRKH_CLK_CK_BUFG_CASC29", + "BRKH_CLK_R_CK_GCLK21", + "BRKH_CLK_R_CK_BUFG_CASC25", + "BRKH_CLK_R_CK_GCLK9", + "BRKH_CLK_CK_GCLK16", + "BRKH_CLK_R_CK_GCLK20", + "BRKH_CLK_R_CK_GCLK14", + "BRKH_CLK_R_CK_GCLK5", + "BRKH_CLK_R_CK_GCLK25", + "BRKH_CLK_CK_BUFG_CASC12", + "BRKH_CLK_CK_GCLK22", + "BRKH_CLK_CK_GCLK15", + "BRKH_CLK_CK_GCLK5", + "BRKH_CLK_R_CK_GCLK26", + "BRKH_CLK_R_CK_BUFG_CASC5", + "BRKH_CLK_CK_GCLK13", + "BRKH_CLK_R_CK_GCLK2", + "BRKH_CLK_CK_GCLK20", + "BRKH_CLK_R_CK_BUFG_CASC12", + "BRKH_CLK_CK_GCLK29", + "BRKH_CLK_R_CK_BUFG_CASC16", + "BRKH_CLK_CK_GCLK31", + "BRKH_CLK_R_CK_GCLK7", + "BRKH_CLK_CK_GCLK27", + "BRKH_CLK_R_CK_GCLK30", + "BRKH_CLK_R_CK_GCLK24", + "BRKH_CLK_R_CK_GCLK0", + "BRKH_CLK_CK_GCLK17", + "BRKH_CLK_CK_BUFG_CASC10", + "BRKH_CLK_CK_BUFG_CASC8", + "BRKH_CLK_R_CK_BUFG_CASC15", + "BRKH_CLK_CK_GCLK23", + "BRKH_CLK_CK_GCLK25", + "BRKH_CLK_CK_BUFG_CASC6", + "BRKH_CLK_R_CK_GCLK11", + "BRKH_CLK_R_CK_GCLK1", + "BRKH_CLK_R_CK_BUFG_CASC22", + "BRKH_CLK_R_CK_GCLK6", + "BRKH_CLK_R_CK_GCLK15", + "BRKH_CLK_CK_GCLK26", + "BRKH_CLK_R_CK_GCLK13", + "BRKH_CLK_R_CK_BUFG_CASC14", + "BRKH_CLK_R_CK_GCLK4", + "BRKH_CLK_R_CK_BUFG_CASC3", + "BRKH_CLK_CK_BUFG_CASC23", + "BRKH_CLK_CK_BUFG_CASC15", + "BRKH_CLK_CK_BUFG_CASC26", + "BRKH_CLK_CK_GCLK4" ], - "sites": [], - "pips": {}, - "tile_type": "BRKH_CLK" + "tile_type": "BRKH_CLK", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_CMT.json b/artix7/tile_type_BRKH_CMT.json index 6f9cd36..56b0408 100644 --- a/artix7/tile_type_BRKH_CMT.json +++ b/artix7/tile_type_BRKH_CMT.json @@ -1,16 +1,16 @@ { + "pips": {}, "wires": [ - "BRKH_CMT_PHASEREF1", "BRKH_CMT_FREQ_REF_NS1", - "BRKH_CMT_FREQ_REF_NS0", - "BRKH_CMT_PHASEREF_BELOW0", - "BRKH_CMT_FREQ_REF_NS2", + "BRKH_CMT_PHYCTRL_SYNC_BB", + "BRKH_CMT_PHASEREF1", "BRKH_CMT_FREQ_REF_NS3", "BRKH_CMT_PHASEREF0", + "BRKH_CMT_FREQ_REF_NS2", "BRKH_CMT_PHASEREF_BELOW1", - "BRKH_CMT_PHYCTRL_SYNC_BB" + "BRKH_CMT_FREQ_REF_NS0", + "BRKH_CMT_PHASEREF_BELOW0" ], - "sites": [], - "pips": {}, - "tile_type": "BRKH_CMT" + "tile_type": "BRKH_CMT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_DSP_L.json b/artix7/tile_type_BRKH_DSP_L.json index 737ad12..15823fb 100644 --- a/artix7/tile_type_BRKH_DSP_L.json +++ b/artix7/tile_type_BRKH_DSP_L.json @@ -1,105 +1,105 @@ { + "pips": {}, "wires": [ - "BRKH_DSP_PCIN45", - "BRKH_DSP_ACIN28", - "BRKH_DSP_BCIN9", - "BRKH_DSP_PCIN12", - "BRKH_DSP_PCIN35", + "BRKH_DSP_PCIN15", + "BRKH_DSP_BCIN12", + "BRKH_DSP_PCIN6", + "BRKH_DSP_PCIN31", + "BRKH_DSP_PCIN37", + "BRKH_DSP_PCIN29", + "BRKH_DSP_ACIN15", + "BRKH_DSP_ACIN8", + "BRKH_DSP_ACIN2", + "BRKH_DSP_PCIN36", + "BRKH_DSP_PCIN46", + "BRKH_DSP_PCIN43", + "BRKH_DSP_BCIN8", + "BRKH_DSP_BCIN7", + "BRKH_DSP_BCIN11", + "BRKH_DSP_BCIN13", + "BRKH_DSP_ACIN13", + "BRKH_DSP_ACIN9", + "BRKH_DSP_PCIN19", + "BRKH_DSP_BCIN17", + "BRKH_DSP_PCIN44", + "BRKH_DSP_PCIN8", + "BRKH_DSP_PCIN24", + "BRKH_DSP_PCIN13", + "BRKH_DSP_PCIN18", "BRKH_DSP_ACIN27", + "BRKH_DSP_PCIN17", + "BRKH_DSP_BCIN0", + "BRKH_DSP_ACIN1", + "BRKH_DSP_PCIN35", + "BRKH_DSP_BCIN15", + "BRKH_DSP_ACIN28", + "BRKH_DSP_PCIN21", + "BRKH_DSP_PCIN42", + "BRKH_DSP_BCIN5", + "BRKH_DSP_BCIN10", + "BRKH_DSP_ACIN29", + "BRKH_DSP_ACIN26", + "BRKH_DSP_PCIN16", + "BRKH_DSP_ACIN6", + "BRKH_DSP_BCIN2", + "BRKH_DSP_ACIN11", + "BRKH_DSP_MULTSIGNIN", + "BRKH_DSP_PCIN2", + "BRKH_DSP_PCIN12", + "BRKH_DSP_PCIN10", + "BRKH_DSP_CARRYCASCIN", + "BRKH_DSP_PCIN26", + "BRKH_DSP_PCIN4", + "BRKH_DSP_PCIN20", + "BRKH_DSP_ACIN0", + "BRKH_DSP_ACIN5", + "BRKH_DSP_PCIN5", + "BRKH_DSP_PCIN3", + "BRKH_DSP_PCIN39", + "BRKH_DSP_PCIN30", + "BRKH_DSP_ACIN25", "BRKH_DSP_PCIN40", + "BRKH_DSP_PCIN22", + "BRKH_DSP_PCIN1", + "BRKH_DSP_ACIN7", + "BRKH_DSP_BCIN3", + "BRKH_DSP_PCIN34", + "BRKH_DSP_BCIN9", + "BRKH_DSP_ACIN10", "BRKH_DSP_ACIN17", "BRKH_DSP_ACIN14", - "BRKH_DSP_CARRYCASCIN", - "BRKH_DSP_BCIN5", - "BRKH_DSP_PCIN16", - "BRKH_DSP_PCIN19", - "BRKH_DSP_BCIN10", - "BRKH_DSP_PCIN25", - "BRKH_DSP_BCIN6", - "BRKH_DSP_ACIN4", - "BRKH_DSP_PCIN41", - "BRKH_DSP_BCIN0", - "BRKH_DSP_PCIN38", - "BRKH_DSP_ACIN23", - "BRKH_DSP_BCIN4", - "BRKH_DSP_MULTSIGNIN", - "BRKH_DSP_PCIN30", - "BRKH_DSP_PCIN9", - "BRKH_DSP_ACIN20", - "BRKH_DSP_PCIN39", - "BRKH_DSP_PCIN26", - "BRKH_DSP_BCIN12", - "BRKH_DSP_ACIN15", - "BRKH_DSP_PCIN17", - "BRKH_DSP_BCIN14", - "BRKH_DSP_PCIN4", - "BRKH_DSP_PCIN33", - "BRKH_DSP_PCIN13", - "BRKH_DSP_PCIN23", - "BRKH_DSP_PCIN24", - "BRKH_DSP_PCIN34", - "BRKH_DSP_PCIN5", - "BRKH_DSP_ACIN25", - "BRKH_DSP_PCIN21", - "BRKH_DSP_PCIN11", - "BRKH_DSP_PCIN22", - "BRKH_DSP_ACIN1", - "BRKH_DSP_PCIN8", - "BRKH_DSP_ACIN6", "BRKH_DSP_ACIN3", - "BRKH_DSP_ACIN5", - "BRKH_DSP_PCIN3", - "BRKH_DSP_BCIN17", - "BRKH_DSP_PCIN37", - "BRKH_DSP_BCIN8", - "BRKH_DSP_PCIN31", - "BRKH_DSP_BCIN16", - "BRKH_DSP_PCIN18", - "BRKH_DSP_ACIN26", - "BRKH_DSP_ACIN18", - "BRKH_DSP_ACIN16", - "BRKH_DSP_ACIN9", - "BRKH_DSP_BCIN13", - "BRKH_DSP_PCIN7", - "BRKH_DSP_PCIN36", - "BRKH_DSP_ACIN13", + "BRKH_DSP_ACIN20", "BRKH_DSP_BCIN1", - "BRKH_DSP_PCIN2", - "BRKH_DSP_PCIN10", + "BRKH_DSP_PCIN11", "BRKH_DSP_ACIN12", - "BRKH_DSP_BCIN11", - "BRKH_DSP_ACIN0", - "BRKH_DSP_PCIN29", - "BRKH_DSP_PCIN27", - "BRKH_DSP_ACIN21", - "BRKH_DSP_BCIN7", - "BRKH_DSP_ACIN2", - "BRKH_DSP_ACIN29", - "BRKH_DSP_PCIN42", - "BRKH_DSP_BCIN3", - "BRKH_DSP_PCIN46", - "BRKH_DSP_ACIN11", - "BRKH_DSP_BCIN2", - "BRKH_DSP_PCIN20", - "BRKH_DSP_ACIN10", - "BRKH_DSP_PCIN6", - "BRKH_DSP_ACIN8", - "BRKH_DSP_ACIN22", - "BRKH_DSP_PCIN14", - "BRKH_DSP_BCIN15", - "BRKH_DSP_ACIN7", - "BRKH_DSP_PCIN43", - "BRKH_DSP_ACIN24", - "BRKH_DSP_PCIN44", - "BRKH_DSP_PCIN32", - "BRKH_DSP_ACIN19", - "BRKH_DSP_PCIN1", - "BRKH_DSP_PCIN15", - "BRKH_DSP_PCIN0", "BRKH_DSP_PCIN28", - "BRKH_DSP_PCIN47" + "BRKH_DSP_PCIN47", + "BRKH_DSP_PCIN7", + "BRKH_DSP_PCIN41", + "BRKH_DSP_BCIN16", + "BRKH_DSP_ACIN24", + "BRKH_DSP_ACIN19", + "BRKH_DSP_ACIN22", + "BRKH_DSP_BCIN4", + "BRKH_DSP_PCIN33", + "BRKH_DSP_PCIN9", + "BRKH_DSP_PCIN14", + "BRKH_DSP_PCIN38", + "BRKH_DSP_ACIN16", + "BRKH_DSP_ACIN23", + "BRKH_DSP_BCIN14", + "BRKH_DSP_PCIN25", + "BRKH_DSP_ACIN4", + "BRKH_DSP_ACIN21", + "BRKH_DSP_PCIN23", + "BRKH_DSP_PCIN0", + "BRKH_DSP_PCIN27", + "BRKH_DSP_PCIN45", + "BRKH_DSP_ACIN18", + "BRKH_DSP_BCIN6", + "BRKH_DSP_PCIN32" ], - "sites": [], - "pips": {}, - "tile_type": "BRKH_DSP_L" + "tile_type": "BRKH_DSP_L", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_DSP_R.json b/artix7/tile_type_BRKH_DSP_R.json index 61da9bc..f3a5985 100644 --- a/artix7/tile_type_BRKH_DSP_R.json +++ b/artix7/tile_type_BRKH_DSP_R.json @@ -1,105 +1,105 @@ { + "pips": {}, "wires": [ - "BRKH_DSP_PCIN45", - "BRKH_DSP_ACIN28", - "BRKH_DSP_BCIN9", - "BRKH_DSP_PCIN12", - "BRKH_DSP_PCIN35", + "BRKH_DSP_PCIN15", + "BRKH_DSP_BCIN12", + "BRKH_DSP_PCIN6", + "BRKH_DSP_PCIN31", + "BRKH_DSP_PCIN37", + "BRKH_DSP_PCIN29", + "BRKH_DSP_ACIN15", + "BRKH_DSP_ACIN8", + "BRKH_DSP_ACIN2", + "BRKH_DSP_PCIN36", + "BRKH_DSP_PCIN46", + "BRKH_DSP_PCIN43", + "BRKH_DSP_BCIN8", + "BRKH_DSP_BCIN7", + "BRKH_DSP_BCIN11", + "BRKH_DSP_BCIN13", + "BRKH_DSP_ACIN13", + "BRKH_DSP_ACIN9", + "BRKH_DSP_PCIN19", + "BRKH_DSP_BCIN17", + "BRKH_DSP_PCIN44", + "BRKH_DSP_PCIN8", + "BRKH_DSP_PCIN24", + "BRKH_DSP_PCIN13", + "BRKH_DSP_PCIN18", "BRKH_DSP_ACIN27", + "BRKH_DSP_PCIN17", + "BRKH_DSP_BCIN0", + "BRKH_DSP_ACIN1", + "BRKH_DSP_PCIN35", + "BRKH_DSP_BCIN15", + "BRKH_DSP_ACIN28", + "BRKH_DSP_PCIN21", + "BRKH_DSP_PCIN42", + "BRKH_DSP_BCIN5", + "BRKH_DSP_BCIN10", + "BRKH_DSP_ACIN29", + "BRKH_DSP_ACIN26", + "BRKH_DSP_PCIN16", + "BRKH_DSP_ACIN6", + "BRKH_DSP_BCIN2", + "BRKH_DSP_ACIN11", + "BRKH_DSP_MULTSIGNIN", + "BRKH_DSP_PCIN2", + "BRKH_DSP_PCIN12", + "BRKH_DSP_PCIN10", + "BRKH_DSP_CARRYCASCIN", + "BRKH_DSP_PCIN26", + "BRKH_DSP_PCIN4", + "BRKH_DSP_PCIN20", + "BRKH_DSP_ACIN0", + "BRKH_DSP_ACIN5", + "BRKH_DSP_PCIN5", + "BRKH_DSP_PCIN3", + "BRKH_DSP_PCIN39", + "BRKH_DSP_PCIN30", + "BRKH_DSP_ACIN25", "BRKH_DSP_PCIN40", + "BRKH_DSP_PCIN22", + "BRKH_DSP_PCIN1", + "BRKH_DSP_ACIN7", + "BRKH_DSP_BCIN3", + "BRKH_DSP_PCIN34", + "BRKH_DSP_BCIN9", + "BRKH_DSP_ACIN10", "BRKH_DSP_ACIN17", "BRKH_DSP_ACIN14", - "BRKH_DSP_CARRYCASCIN", - "BRKH_DSP_BCIN5", - "BRKH_DSP_PCIN16", - "BRKH_DSP_PCIN19", - "BRKH_DSP_BCIN10", - "BRKH_DSP_PCIN25", - "BRKH_DSP_BCIN6", - "BRKH_DSP_ACIN4", - "BRKH_DSP_PCIN41", - "BRKH_DSP_BCIN0", - "BRKH_DSP_PCIN38", - "BRKH_DSP_ACIN23", - "BRKH_DSP_BCIN4", - "BRKH_DSP_MULTSIGNIN", - "BRKH_DSP_PCIN30", - "BRKH_DSP_PCIN9", - "BRKH_DSP_ACIN20", - "BRKH_DSP_PCIN39", - "BRKH_DSP_PCIN26", - "BRKH_DSP_BCIN12", - "BRKH_DSP_ACIN15", - "BRKH_DSP_PCIN17", - "BRKH_DSP_BCIN14", - "BRKH_DSP_PCIN4", - "BRKH_DSP_PCIN33", - "BRKH_DSP_PCIN13", - "BRKH_DSP_PCIN23", - "BRKH_DSP_PCIN24", - "BRKH_DSP_PCIN34", - "BRKH_DSP_PCIN5", - "BRKH_DSP_ACIN25", - "BRKH_DSP_PCIN21", - "BRKH_DSP_PCIN11", - "BRKH_DSP_PCIN22", - "BRKH_DSP_ACIN1", - "BRKH_DSP_PCIN8", - "BRKH_DSP_ACIN6", "BRKH_DSP_ACIN3", - "BRKH_DSP_ACIN5", - "BRKH_DSP_PCIN3", - "BRKH_DSP_BCIN17", - "BRKH_DSP_PCIN37", - "BRKH_DSP_BCIN8", - "BRKH_DSP_PCIN31", - "BRKH_DSP_BCIN16", - "BRKH_DSP_PCIN18", - "BRKH_DSP_ACIN26", - "BRKH_DSP_ACIN18", - "BRKH_DSP_ACIN16", - "BRKH_DSP_ACIN9", - "BRKH_DSP_BCIN13", - "BRKH_DSP_PCIN7", - "BRKH_DSP_PCIN36", - "BRKH_DSP_ACIN13", + "BRKH_DSP_ACIN20", "BRKH_DSP_BCIN1", - "BRKH_DSP_PCIN2", - "BRKH_DSP_PCIN10", + "BRKH_DSP_PCIN11", "BRKH_DSP_ACIN12", - "BRKH_DSP_BCIN11", - "BRKH_DSP_ACIN0", - "BRKH_DSP_PCIN29", - "BRKH_DSP_PCIN27", - "BRKH_DSP_ACIN21", - "BRKH_DSP_BCIN7", - "BRKH_DSP_ACIN2", - "BRKH_DSP_ACIN29", - "BRKH_DSP_PCIN42", - "BRKH_DSP_BCIN3", - "BRKH_DSP_PCIN46", - "BRKH_DSP_ACIN11", - "BRKH_DSP_BCIN2", - "BRKH_DSP_PCIN20", - "BRKH_DSP_ACIN10", - "BRKH_DSP_PCIN6", - "BRKH_DSP_ACIN8", - "BRKH_DSP_ACIN22", - "BRKH_DSP_PCIN14", - "BRKH_DSP_BCIN15", - "BRKH_DSP_ACIN7", - "BRKH_DSP_PCIN43", - "BRKH_DSP_ACIN24", - "BRKH_DSP_PCIN44", - "BRKH_DSP_PCIN32", - "BRKH_DSP_ACIN19", - "BRKH_DSP_PCIN1", - "BRKH_DSP_PCIN15", - "BRKH_DSP_PCIN0", "BRKH_DSP_PCIN28", - "BRKH_DSP_PCIN47" + "BRKH_DSP_PCIN47", + "BRKH_DSP_PCIN7", + "BRKH_DSP_PCIN41", + "BRKH_DSP_BCIN16", + "BRKH_DSP_ACIN24", + "BRKH_DSP_ACIN19", + "BRKH_DSP_ACIN22", + "BRKH_DSP_BCIN4", + "BRKH_DSP_PCIN33", + "BRKH_DSP_PCIN9", + "BRKH_DSP_PCIN14", + "BRKH_DSP_PCIN38", + "BRKH_DSP_ACIN16", + "BRKH_DSP_ACIN23", + "BRKH_DSP_BCIN14", + "BRKH_DSP_PCIN25", + "BRKH_DSP_ACIN4", + "BRKH_DSP_ACIN21", + "BRKH_DSP_PCIN23", + "BRKH_DSP_PCIN0", + "BRKH_DSP_PCIN27", + "BRKH_DSP_PCIN45", + "BRKH_DSP_ACIN18", + "BRKH_DSP_BCIN6", + "BRKH_DSP_PCIN32" ], - "sites": [], - "pips": {}, - "tile_type": "BRKH_DSP_R" + "tile_type": "BRKH_DSP_R", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_GTX.json b/artix7/tile_type_BRKH_GTX.json index 6aa50e4..a4408a5 100644 --- a/artix7/tile_type_BRKH_GTX.json +++ b/artix7/tile_type_BRKH_GTX.json @@ -1,104 +1,104 @@ { - "wires": [ - "BRKH_GTX_SOUTHREFCLK0_LOWER", - "BRKH_GTX_NORTHREFCLK1_UPPER", - "BRKH_GTX_REFCLK0_LOWER", - "BRKH_GTX_NORTHREFCLK0_UPPER", - "BRKH_GTX_REFCLK1_LOWER", - "BRKH_GTX_REFCLK0_UPPER", - "BRKH_GTX_SOUTHREFCLK0_UPPER", - "BRKH_GTX_SOUTHREFCLK1_UPPER", - "BRKH_GTX_NORTHREFCLK0_LOWER", - "BRKH_GTX_SOUTHREFCLK1_LOWER", - "BRKH_GTX_NORTHREFCLK1_LOWER", - "BRKH_GTX_REFCLK1_UPPER" - ], - "sites": [], "pips": { - "BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { + "BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { "can_invert": "0", - "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER", + "src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER", "is_directional": "1", - "src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER", - "is_pseudo": "0" - }, - "BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { - "can_invert": "0", - "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER", - "is_directional": "1", - "src_wire": "BRKH_GTX_REFCLK0_LOWER", - "is_pseudo": "0" - }, - "BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { - "can_invert": "0", - "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER", - "is_directional": "1", - "src_wire": "BRKH_GTX_REFCLK0_UPPER", - "is_pseudo": "0" - }, - "BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { - "can_invert": "0", - "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER", - "is_directional": "1", - "src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER", - "is_pseudo": "0" - }, - "BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { - "can_invert": "0", - "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER", - "is_directional": "1", - "src_wire": "BRKH_GTX_REFCLK1_LOWER", - "is_pseudo": "0" - }, - "BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { - "can_invert": "0", - "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER", - "is_directional": "1", - "src_wire": "BRKH_GTX_REFCLK1_LOWER", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER" }, "BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { "can_invert": "0", - "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER", - "is_directional": "1", "src_wire": "BRKH_GTX_REFCLK1_UPPER", - "is_pseudo": "0" - }, - "BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { - "can_invert": "0", - "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER", "is_directional": "1", - "src_wire": "BRKH_GTX_REFCLK0_LOWER", - "is_pseudo": "0" - }, - "BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { - "can_invert": "0", - "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER", - "is_directional": "1", - "src_wire": "BRKH_GTX_REFCLK1_UPPER", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER" }, "BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { "can_invert": "0", - "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER", - "is_directional": "1", "src_wire": "BRKH_GTX_REFCLK0_UPPER", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER" + }, + "BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { + "can_invert": "0", + "src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER" + }, + "BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { + "can_invert": "0", + "src_wire": "BRKH_GTX_REFCLK0_UPPER", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER" + }, + "BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { + "can_invert": "0", + "src_wire": "BRKH_GTX_REFCLK1_UPPER", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER" + }, + "BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { + "can_invert": "0", + "src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER" }, "BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { "can_invert": "0", - "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER", - "is_directional": "1", "src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER", - "is_pseudo": "0" - }, - "BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { - "can_invert": "0", - "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER", "is_directional": "1", - "src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER" + }, + "BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { + "can_invert": "0", + "src_wire": "BRKH_GTX_REFCLK0_LOWER", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER" + }, + "BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { + "can_invert": "0", + "src_wire": "BRKH_GTX_REFCLK0_LOWER", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER" + }, + "BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { + "can_invert": "0", + "src_wire": "BRKH_GTX_REFCLK1_LOWER", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER" + }, + "BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { + "can_invert": "0", + "src_wire": "BRKH_GTX_REFCLK1_LOWER", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER" } }, - "tile_type": "BRKH_GTX" + "wires": [ + "BRKH_GTX_SOUTHREFCLK0_UPPER", + "BRKH_GTX_REFCLK0_UPPER", + "BRKH_GTX_NORTHREFCLK0_LOWER", + "BRKH_GTX_REFCLK1_LOWER", + "BRKH_GTX_NORTHREFCLK1_LOWER", + "BRKH_GTX_SOUTHREFCLK1_LOWER", + "BRKH_GTX_NORTHREFCLK0_UPPER", + "BRKH_GTX_NORTHREFCLK1_UPPER", + "BRKH_GTX_REFCLK0_LOWER", + "BRKH_GTX_REFCLK1_UPPER", + "BRKH_GTX_SOUTHREFCLK1_UPPER", + "BRKH_GTX_SOUTHREFCLK0_LOWER" + ], + "tile_type": "BRKH_GTX", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_INT.json b/artix7/tile_type_BRKH_INT.json index 8e030d0..da541f1 100644 --- a/artix7/tile_type_BRKH_INT.json +++ b/artix7/tile_type_BRKH_INT.json @@ -1,367 +1,367 @@ { - "wires": [ - "BRKH_INT_SE6B1", - "BRKH_INT_L_LV6", - "BRKH_INT_SE6C2", - "BRKH_INT_NE6D1", - "BRKH_INT_LVB10", - "BRKH_INT_LVB5", - "BRKH_INT_SL1END2", - "BRKH_INT_LV9", - "BRKH_INT_SS6C2", - "BRKH_INT_NL1BEG2", - "BRKH_INT_SR1END1_SLOW", - "BRKH_INT_NN6C0", - "BRKH_INT_L_LV3", - "BRKH_INT_SE6E2", - "BRKH_INT_NN2BEG0", - "BRKH_INT_NN6A3", - "BRKH_INT_NW6C2", - "BRKH_INT_NR1BEG2_SLOW", - "BRKH_INT_NW6B0", - "BRKH_INT_SW6C3", - "BRKH_INT_NR1BEG3", - "BRKH_INT_NW6D1", - "BRKH_INT_ER1END3", - "BRKH_INT_NL1BEG0_SLOW", - "BRKH_INT_NW6D0", - "BRKH_INT_NW2BEG1", - "BRKH_INT_SS6END1", - "BRKH_INT_NN6BEG1", - "BRKH_INT_NW6END_S0_0", - "BRKH_INT_SE6B2", - "BRKH_INT_SS2A3", - "BRKH_INT_LVB_L10", - "BRKH_INT_NE6A1", - "BRKH_INT_L_LV1", - "BRKH_INT_SW2A3", - "BRKH_INT_SS6D3", - "BRKH_INT_NN2A2", - "BRKH_INT_SR1END3", - "BRKH_INT_NL1END_S3_0", - "BRKH_INT_SL1END2_SLOW", - "BRKH_INT_SE2A2", - "BRKH_INT_SE2A0", - "BRKH_INT_NL1BEG1_SLOW", - "BRKH_INT_SW6E1", - "BRKH_INT_NE2BEG1", - "BRKH_INT_SS2A1", - "BRKH_INT_SS6A0", - "BRKH_INT_LV10", - "BRKH_INT_SE6D0", - "BRKH_INT_NW2END_S0_0", - "BRKH_INT_SS6C1", - "BRKH_INT_LVB3", - "BRKH_INT_SW2A0", - "BRKH_INT_SW6B0", - "BRKH_INT_SW6E2", - "BRKH_INT_NN6C1", - "BRKH_INT_SW6D3", - "BRKH_INT_NL1BEG2_SLOW", - "BRKH_INT_LV3", - "BRKH_INT_LV13", - "BRKH_INT_NW6C3", - "BRKH_INT_NE2END_S3_0", - "BRKH_INT_SS2END3", - "BRKH_INT_SS6C3", - "BRKH_INT_SS2END2", - "BRKH_INT_NW2BEG2", - "BRKH_INT_SW6B1", - "BRKH_INT_NN6A1", - "BRKH_INT_SS6END0", - "BRKH_INT_NR1BEG1", - "BRKH_INT_SS6D2", - "BRKH_INT_SW6E3", - "BRKH_INT_SE6D1", - "BRKH_INT_BYP_BOUNCE2", - "BRKH_INT_BYP_BOUNCE6", - "BRKH_INT_SL1END1_SLOW", - "BRKH_INT_NE6B0", - "BRKH_INT_NW2BEG0", - "BRKH_INT_SE6B3", - "BRKH_INT_NN2A0", - "BRKH_INT_LV17", - "BRKH_INT_NN2BEG1", - "BRKH_INT_SL1END3_SLOW", - "BRKH_INT_SS6A3", - "BRKH_INT_ER1BEG_S0", - "BRKH_INT_NN6E0", - "BRKH_INT_NN2A3", - "BRKH_INT_SS6E2", - "BRKH_INT_SS6B0", - "BRKH_INT_NW2BEG3", - "BRKH_INT_NR1BEG2", - "BRKH_INT_SE6B0", - "BRKH_INT_SS2END_N0_3", - "BRKH_INT_SS6C0", - "BRKH_INT_NE6A2", - "BRKH_INT_NW6A0", - "BRKH_INT_SE6D3", - "BRKH_INT_LV8", - "BRKH_INT_NW6A2", - "BRKH_INT_NN6BEG3", - "BRKH_INT_NN2BEG2", - "BRKH_INT_NN6A2", - "BRKH_INT_SW6D2", - "BRKH_INT_LV5", - "BRKH_INT_EL1BEG3", - "BRKH_INT_L_LV14", - "BRKH_INT_SR1END_N3_3", - "BRKH_INT_NE6B1", - "BRKH_INT_LVB_L2", - "BRKH_INT_LVB_L7", - "BRKH_INT_SS6E3", - "BRKH_INT_NN6A0", - "BRKH_INT_NE6B2", - "BRKH_INT_NN6B3", - "BRKH_INT_SS6B2", - "BRKH_INT_NE2BEG0", - "BRKH_INT_SE6E0", - "BRKH_INT_SS6B1", - "BRKH_INT_SW6C2", - "BRKH_INT_SW2END3", - "BRKH_INT_LV1", - "BRKH_INT_SR1END2_SLOW", - "BRKH_INT_NE6D2", - "BRKH_INT_NN6BEG0", - "BRKH_INT_L_LV10", - "BRKH_INT_SE2A1", - "BRKH_INT_SS6END2", - "BRKH_INT_L_LV17", - "BRKH_INT_NR1BEG0_SLOW", - "BRKH_INT_LV12", - "BRKH_INT_NR1BEG0", - "BRKH_INT_SW6C0", - "BRKH_INT_NE2BEG2", - "BRKH_INT_SR1END3_SLOW", - "BRKH_INT_SS6END3", - "BRKH_INT_WW2END3", - "BRKH_INT_LVB7", - "BRKH_INT_NW6A3", - "BRKH_INT_NE6B3", - "BRKH_INT_LVB2", - "BRKH_INT_LVB_L5", - "BRKH_INT_SE6E1", - "BRKH_INT_SW6B3", - "BRKH_INT_NW6D2", - "BRKH_INT_WW4END_S0_0", - "BRKH_INT_SL1END0_SLOW", - "BRKH_INT_NL1BEG1", - "BRKH_INT_L_LV9", - "BRKH_INT_L_LV0", - "BRKH_INT_WL1BEG3", - "BRKH_INT_LVB12", - "BRKH_INT_LVB_L8", - "BRKH_INT_NE6A3", - "BRKH_INT_NE6C1", - "BRKH_INT_NN2BEG3", - "BRKH_INT_SW2A1", - "BRKH_INT_LVB_L6", - "BRKH_INT_NE6C3", - "BRKH_INT_SR1END1", - "BRKH_INT_SW6C1", - "BRKH_INT_LV0", - "BRKH_INT_L_LV2", - "BRKH_INT_NW6B2", - "BRKH_INT_SS6D0", - "BRKH_INT_SS6B3", - "BRKH_INT_NE2BEG3", - "BRKH_INT_LV7", - "BRKH_INT_SE6C3", - "BRKH_INT_NN6E3", - "BRKH_INT_NN6D0", - "BRKH_INT_NN6D1", - "BRKH_INT_SS6A2", - "BRKH_INT_LVB1", - "BRKH_INT_LV6", - "BRKH_INT_NN6END_S1_0", - "BRKH_INT_LVB8", - "BRKH_INT_NN6C2", - "BRKH_INT_NN6B1", - "BRKH_INT_LV15", - "BRKH_INT_NW6C0", - "BRKH_INT_LV11", - "BRKH_INT_LVB_L4", - "BRKH_INT_LV16", - "BRKH_INT_NN6C3", - "BRKH_INT_SS2END0", - "BRKH_INT_WR1END_S1_0", - "BRKH_INT_SS6A1", - "BRKH_INT_NE6C0", - "BRKH_INT_SW6D1", - "BRKH_INT_LV4", - "BRKH_INT_SR1END2", - "BRKH_INT_FAN_BOUNCE_S3_6", - "BRKH_INT_SS6END_N0_3", - "BRKH_INT_LV2", - "BRKH_INT_NR1BEG1_SLOW", - "BRKH_INT_SE6E3", - "BRKH_INT_NN2A1", - "BRKH_INT_NE6C2", - "BRKH_INT_NN6D3", - "BRKH_INT_WR1BEG_S0", - "BRKH_INT_LVB_L1", - "BRKH_INT_L_LV5", - "BRKH_INT_EL1END_S3_0", - "BRKH_INT_FAN_BOUNCE_S3_0", - "BRKH_INT_LVB4", - "BRKH_INT_L_LV8", - "BRKH_INT_SW2A2", - "BRKH_INT_NE6A0", - "BRKH_INT_BYP_BOUNCE3", - "BRKH_INT_SW6B2", - "BRKH_INT_NW6D3", - "BRKH_INT_LVB11", - "BRKH_INT_LVB_L9", - "BRKH_INT_SL1END0", - "BRKH_INT_NE6D3", - "BRKH_INT_NW6B1", - "BRKH_INT_L_LV13", - "BRKH_INT_L_LV7", - "BRKH_INT_NL1BEG0", - "BRKH_INT_NN6E2", - "BRKH_INT_L_LV12", - "BRKH_INT_BYP_BOUNCE7", - "BRKH_INT_SL1END1", - "BRKH_INT_SE6D2", - "BRKH_INT_NE6D0", - "BRKH_INT_L_LV4", - "BRKH_INT_WL1END3", - "BRKH_INT_FAN_BOUNCE_S3_2", - "BRKH_INT_NW6A1", - "BRKH_INT_LVB9", - "BRKH_INT_SL1END3", - "BRKH_INT_SE6C1", - "BRKH_INT_LVB_L3", - "BRKH_INT_NN6B2", - "BRKH_INT_SS2END1", - "BRKH_INT_NW6B3", - "BRKH_INT_SW6E0", - "BRKH_INT_SS2A0", - "BRKH_INT_LVB_L11", - "BRKH_INT_NW6C1", - "BRKH_INT_SW6END3", - "BRKH_INT_SS2A2", - "BRKH_INT_L_LV15", - "BRKH_INT_LVB_L12", - "BRKH_INT_L_LV11", - "BRKH_INT_NN2END_S2_0", - "BRKH_INT_SE2A3", - "BRKH_INT_SS6E1", - "BRKH_INT_SS6D1", - "BRKH_INT_SE6C0", - "BRKH_INT_SS6E0", - "BRKH_INT_NR1BEG3_SLOW", - "BRKH_INT_FAN_BOUNCE_S3_4", - "BRKH_INT_NN6E1", - "BRKH_INT_NN6D2", - "BRKH_INT_L_LV16", - "BRKH_INT_SW6D0", - "BRKH_INT_NN6B0", - "BRKH_INT_LVB6", - "BRKH_INT_NN6BEG2", - "BRKH_INT_LV14" - ], - "sites": [], "pips": { - "BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": { - "can_invert": "0", - "dst_wire": "BRKH_INT_NL1BEG2_SLOW", - "is_directional": "1", - "src_wire": "BRKH_INT_NL1BEG2", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": { - "can_invert": "0", - "dst_wire": "BRKH_INT_SL1END2", - "is_directional": "1", - "src_wire": "BRKH_INT_SL1END2_SLOW", - "is_pseudo": "0" - }, "BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": { - "can_invert": "0", - "dst_wire": "BRKH_INT_NL1BEG0_SLOW", - "is_directional": "1", "src_wire": "BRKH_INT_NL1BEG0", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": { "can_invert": "0", - "dst_wire": "BRKH_INT_NR1BEG2_SLOW", "is_directional": "1", - "src_wire": "BRKH_INT_NR1BEG2", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": { - "can_invert": "0", - "dst_wire": "BRKH_INT_NL1BEG1_SLOW", - "is_directional": "1", - "src_wire": "BRKH_INT_NL1BEG1", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": { - "can_invert": "0", - "dst_wire": "BRKH_INT_SR1END2", - "is_directional": "1", - "src_wire": "BRKH_INT_SR1END2_SLOW", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": { - "can_invert": "0", - "dst_wire": "BRKH_INT_NR1BEG3_SLOW", - "is_directional": "1", - "src_wire": "BRKH_INT_NR1BEG3", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": { - "can_invert": "0", - "dst_wire": "BRKH_INT_NR1BEG0_SLOW", - "is_directional": "1", - "src_wire": "BRKH_INT_NR1BEG0", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": { - "can_invert": "0", - "dst_wire": "BRKH_INT_SR1END3", - "is_directional": "1", - "src_wire": "BRKH_INT_SR1END3_SLOW", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": { - "can_invert": "0", - "dst_wire": "BRKH_INT_SR1END1", - "is_directional": "1", - "src_wire": "BRKH_INT_SR1END1_SLOW", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": { - "can_invert": "0", - "dst_wire": "BRKH_INT_SL1END0", - "is_directional": "1", - "src_wire": "BRKH_INT_SL1END0_SLOW", - "is_pseudo": "0" - }, - "BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": { - "can_invert": "0", - "dst_wire": "BRKH_INT_NR1BEG1_SLOW", - "is_directional": "1", - "src_wire": "BRKH_INT_NR1BEG1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NL1BEG0_SLOW" }, "BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": { - "can_invert": "0", - "dst_wire": "BRKH_INT_SL1END3", - "is_directional": "1", "src_wire": "BRKH_INT_SL1END3_SLOW", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SL1END3" + }, + "BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": { + "src_wire": "BRKH_INT_SL1END2_SLOW", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SL1END2" + }, + "BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": { + "src_wire": "BRKH_INT_NR1BEG3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NR1BEG3_SLOW" + }, + "BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": { + "src_wire": "BRKH_INT_NR1BEG1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NR1BEG1_SLOW" }, "BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": { - "can_invert": "0", - "dst_wire": "BRKH_INT_SL1END1", - "is_directional": "1", "src_wire": "BRKH_INT_SL1END1_SLOW", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SL1END1" + }, + "BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": { + "src_wire": "BRKH_INT_NL1BEG1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NL1BEG1_SLOW" + }, + "BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": { + "src_wire": "BRKH_INT_SR1END1_SLOW", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SR1END1" + }, + "BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": { + "src_wire": "BRKH_INT_NL1BEG2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NL1BEG2_SLOW" + }, + "BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": { + "src_wire": "BRKH_INT_NR1BEG2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NR1BEG2_SLOW" + }, + "BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": { + "src_wire": "BRKH_INT_SR1END3_SLOW", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SR1END3" + }, + "BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": { + "src_wire": "BRKH_INT_SR1END2_SLOW", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SR1END2" + }, + "BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": { + "src_wire": "BRKH_INT_NR1BEG0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_NR1BEG0_SLOW" + }, + "BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": { + "src_wire": "BRKH_INT_SL1END0_SLOW", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BRKH_INT_SL1END0" } }, - "tile_type": "BRKH_INT" + "wires": [ + "BRKH_INT_SS6C0", + "BRKH_INT_SS6B2", + "BRKH_INT_SE6E1", + "BRKH_INT_NW2BEG1", + "BRKH_INT_NL1END_S3_0", + "BRKH_INT_NR1BEG0", + "BRKH_INT_NR1BEG3", + "BRKH_INT_LVB8", + "BRKH_INT_BYP_BOUNCE7", + "BRKH_INT_EL1END_S3_0", + "BRKH_INT_NE6D2", + "BRKH_INT_LVB_L10", + "BRKH_INT_NN6E1", + "BRKH_INT_LV8", + "BRKH_INT_L_LV15", + "BRKH_INT_LV15", + "BRKH_INT_NE6B1", + "BRKH_INT_SW6C3", + "BRKH_INT_NW6A0", + "BRKH_INT_NL1BEG1", + "BRKH_INT_NE2BEG2", + "BRKH_INT_NN6BEG0", + "BRKH_INT_LVB2", + "BRKH_INT_L_LV17", + "BRKH_INT_SS6END0", + "BRKH_INT_NN6C1", + "BRKH_INT_SS6C2", + "BRKH_INT_SS2END2", + "BRKH_INT_SR1END_N3_3", + "BRKH_INT_LVB10", + "BRKH_INT_L_LV8", + "BRKH_INT_LV14", + "BRKH_INT_NN6C0", + "BRKH_INT_LV10", + "BRKH_INT_NW6D3", + "BRKH_INT_NE6C1", + "BRKH_INT_NE6A2", + "BRKH_INT_LVB3", + "BRKH_INT_NN6D1", + "BRKH_INT_NN6B2", + "BRKH_INT_NW6C1", + "BRKH_INT_SE6D1", + "BRKH_INT_SL1END1", + "BRKH_INT_SR1END1_SLOW", + "BRKH_INT_LV3", + "BRKH_INT_SS2A0", + "BRKH_INT_SS6A1", + "BRKH_INT_SS6B0", + "BRKH_INT_NE6B2", + "BRKH_INT_L_LV14", + "BRKH_INT_LVB_L8", + "BRKH_INT_NN2A1", + "BRKH_INT_LVB12", + "BRKH_INT_L_LV6", + "BRKH_INT_NN6B0", + "BRKH_INT_LVB_L5", + "BRKH_INT_LVB11", + "BRKH_INT_LV7", + "BRKH_INT_SL1END0", + "BRKH_INT_SE6E0", + "BRKH_INT_NW6C3", + "BRKH_INT_NE2BEG1", + "BRKH_INT_NN2END_S2_0", + "BRKH_INT_LVB_L12", + "BRKH_INT_LV13", + "BRKH_INT_SS6B3", + "BRKH_INT_NN6A2", + "BRKH_INT_NR1BEG2", + "BRKH_INT_L_LV0", + "BRKH_INT_NW6B2", + "BRKH_INT_NL1BEG2", + "BRKH_INT_SS6A3", + "BRKH_INT_LV17", + "BRKH_INT_L_LV12", + "BRKH_INT_NE6B0", + "BRKH_INT_WW2END3", + "BRKH_INT_SR1END1", + "BRKH_INT_NW6A2", + "BRKH_INT_SW2A3", + "BRKH_INT_NN6A3", + "BRKH_INT_NW2BEG0", + "BRKH_INT_NN2BEG3", + "BRKH_INT_LV9", + "BRKH_INT_NN6E2", + "BRKH_INT_SE6D0", + "BRKH_INT_NW2BEG3", + "BRKH_INT_SS6E2", + "BRKH_INT_NN6E0", + "BRKH_INT_NL1BEG0", + "BRKH_INT_NE6D3", + "BRKH_INT_LV4", + "BRKH_INT_NE6D1", + "BRKH_INT_L_LV9", + "BRKH_INT_EL1BEG3", + "BRKH_INT_NN6END_S1_0", + "BRKH_INT_SE2A2", + "BRKH_INT_SW6D2", + "BRKH_INT_SW6C1", + "BRKH_INT_SW6D1", + "BRKH_INT_L_LV7", + "BRKH_INT_SS6END1", + "BRKH_INT_NR1BEG0_SLOW", + "BRKH_INT_L_LV4", + "BRKH_INT_SW6B1", + "BRKH_INT_LVB5", + "BRKH_INT_SL1END3_SLOW", + "BRKH_INT_LV16", + "BRKH_INT_SS6A0", + "BRKH_INT_NN6A1", + "BRKH_INT_SL1END1_SLOW", + "BRKH_INT_SE6C2", + "BRKH_INT_SS2END3", + "BRKH_INT_NN6BEG2", + "BRKH_INT_NW6B0", + "BRKH_INT_SS2A1", + "BRKH_INT_SS6END_N0_3", + "BRKH_INT_NE2BEG0", + "BRKH_INT_WL1END3", + "BRKH_INT_SS6D1", + "BRKH_INT_BYP_BOUNCE3", + "BRKH_INT_SS6A2", + "BRKH_INT_SR1END3_SLOW", + "BRKH_INT_SW2A1", + "BRKH_INT_NE6C2", + "BRKH_INT_SR1END2_SLOW", + "BRKH_INT_SS6END3", + "BRKH_INT_SS6D3", + "BRKH_INT_FAN_BOUNCE_S3_0", + "BRKH_INT_FAN_BOUNCE_S3_2", + "BRKH_INT_NN6D0", + "BRKH_INT_NW2END_S0_0", + "BRKH_INT_SS6B1", + "BRKH_INT_NN2A0", + "BRKH_INT_LVB_L11", + "BRKH_INT_SL1END0_SLOW", + "BRKH_INT_SS2END_N0_3", + "BRKH_INT_SS2END1", + "BRKH_INT_NW6B1", + "BRKH_INT_SE6C3", + "BRKH_INT_NW2BEG2", + "BRKH_INT_WW4END_S0_0", + "BRKH_INT_SE6B1", + "BRKH_INT_SE6B2", + "BRKH_INT_WR1END_S1_0", + "BRKH_INT_LVB6", + "BRKH_INT_LVB4", + "BRKH_INT_NN6B1", + "BRKH_INT_SR1END2", + "BRKH_INT_NE6A1", + "BRKH_INT_SE6B3", + "BRKH_INT_NN2A2", + "BRKH_INT_L_LV2", + "BRKH_INT_SW6B0", + "BRKH_INT_SE2A3", + "BRKH_INT_LVB7", + "BRKH_INT_SE6D2", + "BRKH_INT_NW6D0", + "BRKH_INT_NN2BEG2", + "BRKH_INT_NE6D0", + "BRKH_INT_NN6C3", + "BRKH_INT_SS6E3", + "BRKH_INT_SE6C1", + "BRKH_INT_SS6E1", + "BRKH_INT_NN2BEG1", + "BRKH_INT_ER1END3", + "BRKH_INT_NE2BEG3", + "BRKH_INT_SS6END2", + "BRKH_INT_L_LV5", + "BRKH_INT_SL1END2", + "BRKH_INT_SS2A2", + "BRKH_INT_L_LV13", + "BRKH_INT_SW2END3", + "BRKH_INT_LVB_L1", + "BRKH_INT_SE6E3", + "BRKH_INT_SW6C0", + "BRKH_INT_NR1BEG1", + "BRKH_INT_LV11", + "BRKH_INT_L_LV3", + "BRKH_INT_NL1BEG1_SLOW", + "BRKH_INT_NL1BEG0_SLOW", + "BRKH_INT_LVB_L2", + "BRKH_INT_SE6B0", + "BRKH_INT_SW6C2", + "BRKH_INT_NN6D3", + "BRKH_INT_NE6A0", + "BRKH_INT_L_LV1", + "BRKH_INT_NW6D2", + "BRKH_INT_SW2A2", + "BRKH_INT_NN6BEG1", + "BRKH_INT_SW6D0", + "BRKH_INT_LVB_L6", + "BRKH_INT_SW6E2", + "BRKH_INT_SR1END3", + "BRKH_INT_L_LV10", + "BRKH_INT_NW6D1", + "BRKH_INT_NW6A1", + "BRKH_INT_NR1BEG3_SLOW", + "BRKH_INT_SW6END3", + "BRKH_INT_NN2A3", + "BRKH_INT_NN6C2", + "BRKH_INT_L_LV16", + "BRKH_INT_NW6C0", + "BRKH_INT_LV5", + "BRKH_INT_LVB_L7", + "BRKH_INT_SS2END0", + "BRKH_INT_LV12", + "BRKH_INT_SL1END2_SLOW", + "BRKH_INT_SE6D3", + "BRKH_INT_BYP_BOUNCE6", + "BRKH_INT_SW6B2", + "BRKH_INT_BYP_BOUNCE2", + "BRKH_INT_LV0", + "BRKH_INT_NW6B3", + "BRKH_INT_SW6D3", + "BRKH_INT_NN6BEG3", + "BRKH_INT_NN2BEG0", + "BRKH_INT_LVB1", + "BRKH_INT_NW6A3", + "BRKH_INT_NE2END_S3_0", + "BRKH_INT_LV2", + "BRKH_INT_NE6C3", + "BRKH_INT_LVB_L4", + "BRKH_INT_WL1BEG3", + "BRKH_INT_NR1BEG1_SLOW", + "BRKH_INT_SE6E2", + "BRKH_INT_SS2A3", + "BRKH_INT_SW6B3", + "BRKH_INT_NE6C0", + "BRKH_INT_L_LV11", + "BRKH_INT_LVB_L3", + "BRKH_INT_LVB9", + "BRKH_INT_NW6C2", + "BRKH_INT_NE6B3", + "BRKH_INT_FAN_BOUNCE_S3_4", + "BRKH_INT_SS6C3", + "BRKH_INT_LV6", + "BRKH_INT_ER1BEG_S0", + "BRKH_INT_FAN_BOUNCE_S3_6", + "BRKH_INT_SS6D2", + "BRKH_INT_WR1BEG_S0", + "BRKH_INT_SE6C0", + "BRKH_INT_NR1BEG2_SLOW", + "BRKH_INT_LV1", + "BRKH_INT_SL1END3", + "BRKH_INT_SE2A1", + "BRKH_INT_SW2A0", + "BRKH_INT_SW6E1", + "BRKH_INT_NW6END_S0_0", + "BRKH_INT_SW6E0", + "BRKH_INT_NN6D2", + "BRKH_INT_SS6C1", + "BRKH_INT_LVB_L9", + "BRKH_INT_NN6A0", + "BRKH_INT_SE2A0", + "BRKH_INT_NL1BEG2_SLOW", + "BRKH_INT_SW6E3", + "BRKH_INT_SS6E0", + "BRKH_INT_NE6A3", + "BRKH_INT_NN6B3", + "BRKH_INT_NN6E3", + "BRKH_INT_SS6D0" + ], + "tile_type": "BRKH_INT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_BRKH_TERM_INT.json b/artix7/tile_type_BRKH_TERM_INT.json index 36967b8..fa3a202 100644 --- a/artix7/tile_type_BRKH_TERM_INT.json +++ b/artix7/tile_type_BRKH_TERM_INT.json @@ -1,124 +1,124 @@ { + "pips": {}, "wires": [ - "T_TERM_UTURN_INT_LVB5", - "T_TERM_UTURN_INT_SE6C3", - "T_TERM_UTURN_INT_SW6D3", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", - "T_TERM_UTURN_INT_SE6E3", - "T_TERM_UTURN_INT_SS2A1", - "T_TERM_UTURN_INT_SW6C3", - "T_TERM_UTURN_INT_LV_L16", - "T_TERM_UTURN_INT_SS6B0", - "T_TERM_INT_UTURN_LV_R2", - "T_TERM_UTURN_INT_SS2A2", - "T_TERM_UTURN_INT_SW2A3", - "T_TERM_UTURN_INT_SS6END3", - "T_TERM_UTURN_INT_LVB1", - "T_TERM_INT_UTURN_LV_R5", - "T_TERM_UTURN_INT_SE6E1", - "T_TERM_INT_UTURN_LV_R17", - "T_TERM_UTURN_INT_SE6D3", - "T_TERM_UTURN_INT_SW6D1", - "T_TERM_UTURN_INT_SW2A1", - "T_TERM_UTURN_INT_SS6B2", - "T_TERM_UTURN_INT_LV_L4", - "T_TERM_UTURN_INT_SW6E3", - "T_TERM_UTURN_INT_SS6A3", - "T_TERM_UTURN_INT_LV_L17", - "T_TERM_UTURN_INT_SW2A0", - "T_TERM_UTURN_INT_LV_L6", - "T_TERM_INT_UTURN_LV_R9", - "T_TERM_UTURN_INT_SE2A3", - "T_TERM_UTURN_INT_SS6C0", - "T_TERM_UTURN_INT_SE6D0", - "T_TERM_UTURN_INT_SW6E1", - "T_TERM_UTURN_INT_LV_L2", - "T_TERM_UTURN_INT_SE2A0", - "T_TERM_UTURN_INT_SL1END2_SLOW", - "T_TERM_UTURN_INT_SW6D0", - "T_TERM_UTURN_INT_LVB0", - "T_TERM_UTURN_INT_SS6END1", - "T_TERM_UTURN_INT_SR1END3_SLOW", - "T_TERM_UTURN_INT_SW6C1", - "T_TERM_UTURN_INT_SS6E1", - "T_TERM_UTURN_INT_SW6B0", - "T_TERM_UTURN_INT_LVB2", - "T_TERM_UTURN_INT_SS2END0", - "T_TERM_UTURN_INT_SS6D3", - "T_TERM_UTURN_INT_SS6E2", - "T_TERM_INT_UTURN_LV_R4", - "T_TERM_INT_UTURN_LV_R6", - "T_TERM_UTURN_INT_SS6D1", - "T_TERM_UTURN_INT_SS6A0", - "T_TERM_UTURN_INT_SS2END1", "T_TERM_UTURN_INT_SE6D1", - "T_TERM_UTURN_INT_SS6A1", - "T_TERM_UTURN_INT_LVB_L5", - "T_TERM_UTURN_INT_SW2A2", - "T_TERM_UTURN_INT_LVB_L2", - "T_TERM_UTURN_INT_LVB_L3", - "T_TERM_UTURN_INT_SS6C2", - "T_TERM_UTURN_INT_SS6D0", - "T_TERM_UTURN_INT_SS2A0", - "T_TERM_UTURN_INT_LV_L9", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", - "T_TERM_UTURN_INT_SS6B1", - "T_TERM_UTURN_INT_SW6E2", - "T_TERM_UTURN_INT_SW6B2", - "T_TERM_UTURN_INT_SE2A1", - "T_TERM_UTURN_INT_SR1END2_SLOW", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "T_TERM_UTURN_INT_SE6B2", - "T_TERM_UTURN_INT_SE6D2", - "T_TERM_UTURN_INT_SE6B3", - "T_TERM_UTURN_INT_LVB3", - "T_TERM_UTURN_INT_SL1END3_SLOW", - "T_TERM_UTURN_INT_WR1BEG_S0", + "T_TERM_UTURN_INT_LVB1", + "T_TERM_UTURN_INT_SE6B0", + "T_TERM_UTURN_INT_SL1END1_SLOW", + "T_TERM_UTURN_INT_WR1END_S1_0", "T_TERM_UTURN_INT_SW6B1", + "T_TERM_INT_UTURN_LV_R6", + "T_TERM_UTURN_INT_SS2A3", + "T_TERM_UTURN_INT_SS6E3", + "T_TERM_UTURN_INT_SW6B0", + "T_TERM_UTURN_INT_SW6B3", + "T_TERM_INT_UTURN_LV_R16", + "T_TERM_INT_UTURN_LV_R2", + "T_TERM_UTURN_INT_SE6D2", + "T_TERM_UTURN_INT_SL1END3_SLOW", + "T_TERM_UTURN_INT_LV_L16", + "T_TERM_UTURN_INT_SE6C3", + "T_TERM_UTURN_INT_SE6B1", + "T_TERM_UTURN_INT_SE2A0", + "T_TERM_UTURN_INT_LV_L17", + "T_TERM_UTURN_INT_SS6END2", + "T_TERM_UTURN_INT_SW6D0", + "T_TERM_UTURN_INT_SS2END2", + "T_TERM_UTURN_INT_SW6E1", + "T_TERM_UTURN_INT_SS6D2", + "T_TERM_UTURN_INT_SR1END2_SLOW", + "T_TERM_UTURN_INT_SW6D2", + "T_TERM_UTURN_INT_SE6E2", + "T_TERM_UTURN_INT_LVB2", + "T_TERM_UTURN_INT_SE6C1", + "T_TERM_UTURN_INT_LVB_L0", + "T_TERM_UTURN_INT_SW6D3", "T_TERM_UTURN_INT_LV_L7", "T_TERM_UTURN_INT_LV_L3", - "T_TERM_UTURN_INT_SS6END2", + "T_TERM_UTURN_INT_SS6C2", + "T_TERM_UTURN_INT_SW2A2", "T_TERM_UTURN_INT_LVB_L4", - "T_TERM_UTURN_INT_SE6C1", - "T_TERM_UTURN_INT_SS6C1", - "T_TERM_UTURN_INT_SW6E0", - "T_TERM_UTURN_INT_SL1END1_SLOW", "T_TERM_UTURN_INT_SS6END0", - "T_TERM_UTURN_INT_SE6B1", - "T_TERM_UTURN_INT_SS6E0", - "T_TERM_UTURN_INT_LVB_L1", - "T_TERM_UTURN_INT_SS2END3", - "T_TERM_UTURN_INT_SS2END2", - "T_TERM_UTURN_INT_SS6A2", - "T_TERM_UTURN_INT_SR1END1_SLOW", - "T_TERM_UTURN_INT_LVB_L0", - "T_TERM_UTURN_INT_ER1END3", - "T_TERM_INT_UTURN_LV_R16", - "T_TERM_UTURN_INT_SE6C2", - "T_TERM_UTURN_INT_SE2A2", - "T_TERM_UTURN_INT_SS6C3", - "T_TERM_INT_UTURN_LV_R7", - "T_TERM_UTURN_INT_SE6E0", - "T_TERM_UTURN_INT_SE6E2", - "T_TERM_UTURN_INT_SW6B3", - "T_TERM_UTURN_INT_LVB4", - "T_TERM_UTURN_INT_SL1END0_SLOW", - "T_TERM_UTURN_INT_SS6D2", + "T_TERM_INT_UTURN_LV_R9", "T_TERM_UTURN_INT_SW6C2", - "T_TERM_UTURN_INT_SS6E3", - "T_TERM_UTURN_INT_WR1END_S1_0", - "T_TERM_UTURN_INT_SE6B0", - "T_TERM_UTURN_INT_SS6B3", - "T_TERM_UTURN_INT_SW6C0", - "T_TERM_UTURN_INT_LV_L5", - "T_TERM_UTURN_INT_SE6C0", - "T_TERM_UTURN_INT_SS2A3", - "T_TERM_UTURN_INT_SW6D2", + "T_TERM_UTURN_INT_WR1BEG_S0", + "T_TERM_UTURN_INT_SS6C0", + "T_TERM_UTURN_INT_SS6D1", + "T_TERM_UTURN_INT_SE6D0", + "T_TERM_UTURN_INT_SS2A0", "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", + "T_TERM_UTURN_INT_SS6E1", + "T_TERM_UTURN_INT_SS6A2", + "T_TERM_UTURN_INT_SW6E3", + "T_TERM_UTURN_INT_SE6C2", + "T_TERM_UTURN_INT_SW6B2", + "T_TERM_UTURN_INT_SS6B0", + "T_TERM_UTURN_INT_SS6C1", + "T_TERM_UTURN_INT_SS6A0", + "T_TERM_UTURN_INT_LVB_L2", + "T_TERM_INT_UTURN_LV_R5", + "T_TERM_UTURN_INT_SE6E3", + "T_TERM_UTURN_INT_SE2A2", + "T_TERM_UTURN_INT_LV_L6", + "T_TERM_UTURN_INT_SS2A1", + "T_TERM_UTURN_INT_SR1END3_SLOW", + "T_TERM_UTURN_INT_LVB_L5", + "T_TERM_UTURN_INT_SE2A3", + "T_TERM_UTURN_INT_SL1END2_SLOW", + "T_TERM_UTURN_INT_SS2END0", + "T_TERM_UTURN_INT_ER1END3", + "T_TERM_UTURN_INT_SS2A2", + "T_TERM_UTURN_INT_LV_L4", + "T_TERM_UTURN_INT_SW6C1", + "T_TERM_INT_UTURN_LV_R7", + "T_TERM_UTURN_INT_SW6C3", + "T_TERM_UTURN_INT_SW2A1", + "T_TERM_UTURN_INT_SS2END3", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", + "T_TERM_UTURN_INT_SS6C3", + "T_TERM_UTURN_INT_LVB_L3", + "T_TERM_UTURN_INT_SW6E0", + "T_TERM_UTURN_INT_SW2A0", "T_TERM_INT_UTURN_LV_R3", + "T_TERM_UTURN_INT_SE6C0", + "T_TERM_UTURN_INT_SS2END1", + "T_TERM_INT_UTURN_LV_R4", + "T_TERM_UTURN_INT_SE6B2", + "T_TERM_UTURN_INT_SL1END0_SLOW", + "T_TERM_UTURN_INT_LVB4", + "T_TERM_UTURN_INT_LV_L2", + "T_TERM_UTURN_INT_SW6C0", + "T_TERM_UTURN_INT_LVB_L1", + "T_TERM_UTURN_INT_SS6E2", + "T_TERM_UTURN_INT_SS6B2", + "T_TERM_UTURN_INT_SW2A3", + "T_TERM_UTURN_INT_SE6D3", + "T_TERM_UTURN_INT_SS6D3", + "T_TERM_UTURN_INT_SR1END1_SLOW", + "T_TERM_UTURN_INT_LVB3", + "T_TERM_UTURN_INT_SE6E0", + "T_TERM_UTURN_INT_SS6A3", + "T_TERM_UTURN_INT_LVB5", + "T_TERM_UTURN_INT_LV_L9", + "T_TERM_UTURN_INT_SS6B1", + "T_TERM_UTURN_INT_SS6E0", + "T_TERM_UTURN_INT_SS6D0", + "T_TERM_UTURN_INT_SW6D1", + "T_TERM_UTURN_INT_SE6B3", + "T_TERM_UTURN_INT_SS6END1", + "T_TERM_UTURN_INT_LV_L5", + "T_TERM_UTURN_INT_LVB0", + "T_TERM_UTURN_INT_SE6E1", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", + "T_TERM_UTURN_INT_SE2A1", + "T_TERM_UTURN_INT_SS6B3", + "T_TERM_INT_UTURN_LV_R17", + "T_TERM_UTURN_INT_SS6END3", + "T_TERM_UTURN_INT_SS6A1", + "T_TERM_UTURN_INT_SW6E2", "T_TERM_UTURN_INT_ER1BEG_S0" ], - "sites": [], - "pips": {}, - "tile_type": "BRKH_TERM_INT" + "tile_type": "BRKH_TERM_INT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_B_TERM_INT.json b/artix7/tile_type_B_TERM_INT.json index 00691fd..debc73e 100644 --- a/artix7/tile_type_B_TERM_INT.json +++ b/artix7/tile_type_B_TERM_INT.json @@ -1,125 +1,125 @@ { + "pips": {}, "wires": [ - "B_TERM_UTURN_INT_WR1BEG0", - "B_TERM_UTURN_INT_ER1END_N3_3", - "B_TERM_UTURN_INT_LV_L6", - "B_TERM_UTURN_INT_LVB4", - "B_TERM_UTURN_INT_SW6A2", + "B_TERM_UTURN_INT_SW6C0", + "B_TERM_UTURN_INT_LVB_L0", + "B_TERM_UTURN_INT_LVB5", + "B_TERM_UTURN_INT_SE6D3", "B_TERM_UTURN_INT_LV4", - "B_TERM_UTURN_INT_SS2A1", - "B_TERM_UTURN_INT_LV3", - "B_TERM_UTURN_INT_SS6D3", + "B_TERM_UTURN_INT_SS2BEG3", + "B_TERM_UTURN_INT_SS6B1", + "B_TERM_UTURN_INT_SE2BEG0", + "B_TERM_UTURN_INT_LV_L5", + "B_TERM_UTURN_INT_SE6D1", "B_TERM_UTURN_INT_LV2", - "B_TERM_UTURN_INT_LV_L3", + "B_TERM_UTURN_INT_LVB_L2", + "B_TERM_UTURN_INT_SS6BEG3", + "B_TERM_UTURN_INT_LVB1", + "B_TERM_UTURN_INT_SL1BEG2", + "B_TERM_UTURN_INT_SL1BEG1", + "B_TERM_UTURN_INT_SS6BEG1", + "B_TERM_UTURN_INT_LVB2", + "B_TERM_UTURN_INT_SE6A2", + "B_TERM_UTURN_INT_SS6D3", + "B_TERM_UTURN_INT_SS6BEG0", + "B_TERM_UTURN_INT_LV9", + "B_TERM_UTURN_INT_SE2BEG2", + "B_TERM_UTURN_INT_LV_L2", + "B_TERM_UTURN_INT_SE6B2", + "B_TERM_UTURN_INT_LVB_L3", + "B_TERM_UTURN_INT_LV7", + "B_TERM_UTURN_INT_SS6D2", + "B_TERM_UTURN_INT_LVB_L4", + "B_TERM_UTURN_INT_SW6C2", "B_TERM_UTURN_INT_SS6B3", + "B_TERM_UTURN_INT_SS2A1", + "B_TERM_UTURN_INT_SE2BEG1", + "B_TERM_UTURN_INT_SS6A2", + "B_TERM_UTURN_INT_SE6A0", + "B_TERM_UTURN_INT_LV6", + "B_TERM_UTURN_INT_LV_L6", + "B_TERM_UTURN_INT_SS2A2", + "B_TERM_UTURN_INT_WR1BEG0", + "B_TERM_UTURN_INT_SE6B0", + "B_TERM_UTURN_INT_SL1BEG0", + "B_TERM_UTURN_INT_SW6A3", + "B_TERM_UTURN_INT_LVB0", + "B_TERM_UTURN_INT_LVB_L1", + "B_TERM_UTURN_INT_SE6C0", + "B_TERM_UTURN_INT_LV_L9", + "B_TERM_UTURN_INT_SW6B2", + "B_TERM_UTURN_INT_LVB3", + "B_TERM_UTURN_INT_SW2BEG0", + "B_TERM_UTURN_INT_SW6A1", + "B_TERM_UTURN_INT_SE6D2", + "B_TERM_UTURN_INT_LV_L3", + "B_TERM_UTURN_INT_SR1BEG3", + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "B_TERM_UTURN_INT_SW6END_N0_3", + "B_TERM_UTURN_INT_SE6B1", + "B_TERM_UTURN_INT_LV5", + "B_TERM_UTURN_INT_SR1BEG2", + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "B_TERM_UTURN_INT_SW6A2", + "B_TERM_UTURN_INT_SS2BEG2", + "B_TERM_UTURN_INT_SS6D0", + "B_TERM_UTURN_INT_SE6A1", + "B_TERM_UTURN_INT_SS6A0", + "B_TERM_UTURN_INT_SS2BEG1", + "B_TERM_UTURN_INT_SE6C3", + "B_TERM_UTURN_INT_SS6C2", + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "B_TERM_UTURN_INT_SS6A3", + "B_TERM_UTURN_INT_SW6D2", + "B_TERM_UTURN_INT_SS6E3", + "B_TERM_UTURN_INT_SW2BEG2", + "B_TERM_UTURN_INT_LV_L8", + "B_TERM_UTURN_INT_SW6B3", + "B_TERM_UTURN_INT_SW6B1", + "B_TERM_UTURN_INT_SW2BEG1", + "B_TERM_UTURN_INT_LVB4", + "B_TERM_UTURN_INT_SS2BEG0", + "B_TERM_UTURN_INT_SR1BEG1", + "B_TERM_UTURN_INT_SE6C2", + "B_TERM_UTURN_INT_SW2BEG3", + "B_TERM_UTURN_INT_WR1END0", + "B_TERM_UTURN_INT_LV_L7", + "B_TERM_UTURN_INT_SW6D1", + "B_TERM_UTURN_INT_LVB_L5", + "B_TERM_UTURN_INT_SE6C1", + "B_TERM_UTURN_INT_LV18", + "B_TERM_UTURN_INT_SW6D3", + "B_TERM_UTURN_INT_SL1BEG3", + "B_TERM_UTURN_INT_SS6E1", + "B_TERM_UTURN_INT_SW6C3", + "B_TERM_UTURN_INT_SS2A3", + "B_TERM_UTURN_INT_SS6E0", + "B_TERM_UTURN_INT_ER1BEG0", + "B_TERM_UTURN_INT_ER1END_N3_3", + "B_TERM_UTURN_INT_SE6B3", + "B_TERM_UTURN_INT_SS6B2", + "B_TERM_UTURN_INT_SW6B0", + "B_TERM_UTURN_INT_SW6A0", + "B_TERM_UTURN_INT_LV3", + "B_TERM_UTURN_INT_SS6C3", + "B_TERM_UTURN_INT_LV8", + "B_TERM_UTURN_INT_SE6A3", + "B_TERM_UTURN_INT_SS6C1", + "B_TERM_UTURN_INT_SS6B0", + "B_TERM_UTURN_INT_SS6C0", + "B_TERM_UTURN_INT_SW6C1", "B_TERM_UTURN_INT_SS6D1", "B_TERM_UTURN_INT_LV_L4", - "B_TERM_UTURN_INT_SS6C1", - "B_TERM_UTURN_INT_SW6B3", - "B_TERM_UTURN_INT_SS6A3", - "B_TERM_UTURN_INT_ER1BEG0", - "B_TERM_UTURN_INT_SW6D2", - "B_TERM_UTURN_INT_LVB_L5", - "B_TERM_UTURN_INT_SW6D3", - "B_TERM_UTURN_INT_SL1BEG1", - "B_TERM_UTURN_INT_SE6D0", - "B_TERM_UTURN_INT_SE2BEG2", - "B_TERM_UTURN_INT_SS6B0", - "B_TERM_UTURN_INT_SW6A3", - "B_TERM_UTURN_INT_LVB5", - "B_TERM_UTURN_INT_SS6C3", - "B_TERM_UTURN_INT_LV_L5", - "B_TERM_UTURN_INT_SE6A1", - "B_TERM_UTURN_INT_LV_L18", - "B_TERM_UTURN_INT_SS6A0", - "B_TERM_UTURN_INT_SS6C0", - "B_TERM_UTURN_INT_SW6C0", - "B_TERM_UTURN_INT_SS6B1", - "B_TERM_UTURN_INT_SW6B1", - "B_TERM_UTURN_INT_SW6D1", - "B_TERM_UTURN_INT_SS6E0", - "B_TERM_UTURN_INT_LVB3", - "B_TERM_UTURN_INT_SS6BEG0", - "B_TERM_UTURN_INT_SW6A1", - "B_TERM_UTURN_INT_FAN_BOUNCE0", "B_TERM_UTURN_INT_SS2A0", - "B_TERM_UTURN_INT_LV_L8", - "B_TERM_UTURN_INT_SW6C3", - "B_TERM_UTURN_INT_SW2BEG0", - "B_TERM_UTURN_INT_SS2BEG3", - "B_TERM_UTURN_INT_SE6D2", - "B_TERM_UTURN_INT_SE6B1", - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "B_TERM_UTURN_INT_SE2BEG0", - "B_TERM_UTURN_INT_SS6C2", - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "B_TERM_UTURN_INT_SW6B2", - "B_TERM_UTURN_INT_WR1END0", - "B_TERM_UTURN_INT_SS6B2", - "B_TERM_UTURN_INT_SE6C0", - "B_TERM_UTURN_INT_SE6B3", - "B_TERM_UTURN_INT_SE6A0", - "B_TERM_UTURN_INT_SW2BEG3", - "B_TERM_UTURN_INT_LV8", - "B_TERM_UTURN_INT_SS6BEG2", - "B_TERM_UTURN_INT_SW2BEG1", - "B_TERM_UTURN_INT_SS6E3", - "B_TERM_UTURN_INT_SS6E1", - "B_TERM_UTURN_INT_SL1BEG2", - "B_TERM_UTURN_INT_SS6BEG3", - "B_TERM_UTURN_INT_SS6BEG1", - "B_TERM_UTURN_INT_SE2BEG1", - "B_TERM_UTURN_INT_SS2A2", - "B_TERM_UTURN_INT_SS6E2", - "B_TERM_UTURN_INT_LV_L9", - "B_TERM_UTURN_INT_SW6A0", - "B_TERM_UTURN_INT_SW6END_N0_3", - "B_TERM_UTURN_INT_SE6A3", - "B_TERM_UTURN_INT_SE6B2", - "B_TERM_UTURN_INT_SE6D1", - "B_TERM_UTURN_INT_SW6B0", - "B_TERM_UTURN_INT_SR1BEG2", - "B_TERM_UTURN_INT_SE6A2", - "B_TERM_UTURN_INT_LV7", - "B_TERM_UTURN_INT_SW6C2", - "B_TERM_UTURN_INT_SS2BEG1", - "B_TERM_UTURN_INT_LVB_L4", - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "B_TERM_UTURN_INT_LVB_L3", - "B_TERM_UTURN_INT_SE6D3", - "B_TERM_UTURN_INT_LV9", - "B_TERM_UTURN_INT_LV_L7", - "B_TERM_UTURN_INT_SE6C3", - "B_TERM_UTURN_INT_SW6C1", - "B_TERM_UTURN_INT_SE2BEG3", "B_TERM_UTURN_INT_SS6A1", - "B_TERM_UTURN_INT_LV_L2", - "B_TERM_UTURN_INT_LVB_L0", - "B_TERM_UTURN_INT_SS2BEG2", - "B_TERM_UTURN_INT_SR1BEG1", - "B_TERM_UTURN_INT_LVB1", - "B_TERM_UTURN_INT_LVB_L1", - "B_TERM_UTURN_INT_SE6B0", - "B_TERM_UTURN_INT_SS6D0", - "B_TERM_UTURN_INT_LVB2", - "B_TERM_UTURN_INT_SS2BEG0", - "B_TERM_UTURN_INT_LVB0", - "B_TERM_UTURN_INT_SS6D2", - "B_TERM_UTURN_INT_SE6C1", + "B_TERM_UTURN_INT_SS6BEG2", + "B_TERM_UTURN_INT_SS6E2", "B_TERM_UTURN_INT_SW6D0", - "B_TERM_UTURN_INT_SL1BEG0", - "B_TERM_UTURN_INT_LV18", - "B_TERM_UTURN_INT_LV6", - "B_TERM_UTURN_INT_LV5", - "B_TERM_UTURN_INT_SR1BEG3", - "B_TERM_UTURN_INT_LVB_L2", - "B_TERM_UTURN_INT_SL1BEG3", - "B_TERM_UTURN_INT_SW2BEG2", - "B_TERM_UTURN_INT_SS6A2", - "B_TERM_UTURN_INT_SS2A3", - "B_TERM_UTURN_INT_SE6C2" + "B_TERM_UTURN_INT_SE6D0", + "B_TERM_UTURN_INT_LV_L18", + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "B_TERM_UTURN_INT_SE2BEG3" ], - "sites": [], - "pips": {}, - "tile_type": "B_TERM_INT" + "tile_type": "B_TERM_INT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CFG_CENTER_BOT.json b/artix7/tile_type_CFG_CENTER_BOT.json index c991c77..fc1e4ca 100644 --- a/artix7/tile_type_CFG_CENTER_BOT.json +++ b/artix7/tile_type_CFG_CENTER_BOT.json @@ -1,4513 +1,4513 @@ { - "wires": [ - "CFG_CENTER_IMUX6_18", - "CFG_CENTER_LOGIC_OUTS_B0_0", - "CFG_CENTER_FAN2_11", - "CFG_CENTER_WW2END2_0", - "CFG_CENTER_NW2A1_17", - "CFG_CENTER_IMUX17_6", - "CFG_CENTER_WW4C0_5", - "CFG_CENTER_NE4BEG0_10", - "CFG_CENTER_WL1END3_0", - "CFG_CENTER_EE4BEG0_1", - "CFG_CENTER_IMUX5_16", - "CFG_CENTER_EE2A2_1", - "CFG_CENTER_NW4END3_11", - "CFG_CENTER_LOGIC_OUTS_B22_2", - "CFG_CENTER_NW4A3_0", - "CFG_CENTER_WW4END3_14", - "CFG_CENTER_WW4END1_3", - "CFG_CENTER_LH11_4", - "CFG_CENTER_WR1END3_3", - "CFG_CENTER_IMUX40_17", - "CFG_CENTER_NW4A3_10", - "CFG_CENTER_WW4B3_9", - "CFG_CENTER_WW4B1_4", - "CFG_CENTER_LOGIC_OUTS_B7_9", - "CFG_CENTER_LH1_7", - "CFG_CENTER_LH5_0", - "CFG_CENTER_NW4A3_4", - "CFG_CENTER_SW4A0_2", - "CFG_CENTER_EE2A0_15", - "CFG_CENTER_FAN2_9", - "CFG_CENTER_NE2A0_7", - "CFG_CENTER_SE2A2_16", - "CFG_CENTER_WR1END2_15", - "CFG_CENTER_IMUX44_13", - "CFG_CENTER_CTRL0_10", - "CFG_CENTER_WW2END2_9", - "CFG_CENTER_IMUX17_4", - "CFG_CENTER_FAN7_16", - "CFG_CENTER_SW4END2_6", - "CFG_CENTER_EE4A3_10", - "CFG_CENTER_LOGIC_OUTS_B19_14", - "CFG_CENTER_FAN3_15", - "CFG_CENTER_WR1END2_5", - "CFG_CENTER_SW2A2_15", - "CFG_CENTER_EE4A0_8", - "CFG_CENTER_IMUX5_9", - "CFG_CENTER_LOGIC_OUTS_B12_11", - "CFG_CENTER_NW4END1_0", - "CFG_CENTER_BOT_USR_ACCESS_DATA4", - "CFG_CENTER_EE2A3_18", - "CFG_CENTER_NW2A1_9", - "CFG_CENTER_EL1BEG1_5", - "CFG_CENTER_IMUX24_19", - "CFG_CENTER_WW4B1_0", - "CFG_CENTER_LOGIC_OUTS_B6_3", - "CFG_CENTER_EE4B0_12", - "CFG_CENTER_NE4C2_12", - "CFG_CENTER_BYP1_5", - "CFG_CENTER_WW4A0_14", - "CFG_CENTER_SE4BEG1_7", - "CFG_CENTER_NW2A1_10", - "CFG_CENTER_EE4B0_19", - "CFG_CENTER_NE4C2_16", - "CFG_CENTER_IMUX29_2", - "CFG_CENTER_BOT_USR_ACCESS_DATA9", - "CFG_CENTER_FAN2_7", - "CFG_CENTER_EE4C2_5", - "CFG_CENTER_WW4C1_4", - "CFG_CENTER_IMUX21_1", - "CFG_CENTER_CTRL0_8", - "CFG_CENTER_EE4A3_4", - "CFG_CENTER_SW4END2_7", - "CFG_CENTER_IMUX9_3", - "CFG_CENTER_NE2A2_3", - "CFG_CENTER_BYP4_16", - "CFG_CENTER_WW4A3_19", - "CFG_CENTER_LH9_18", - "CFG_CENTER_WW4A2_2", - "CFG_CENTER_IMUX38_1", - "CFG_CENTER_IMUX42_4", - "CFG_CENTER_NW4END0_14", - "CFG_CENTER_LOGIC_OUTS_B16_15", - "CFG_CENTER_WW2A0_7", - "CFG_CENTER_NW4END0_9", - "CFG_CENTER_NE2A0_3", - "CFG_CENTER_IMUX45_2", - "CFG_CENTER_SE4BEG3_10", - "CFG_CENTER_NE4BEG3_3", - "CFG_CENTER_SW2A2_19", - "CFG_CENTER_ER1BEG2_7", - "CFG_CENTER_IMUX11_6", - "CFG_CENTER_IMUX34_5", - "CFG_CENTER_IMUX45_4", - "CFG_CENTER_LOGIC_OUTS_B18_14", - "CFG_CENTER_EE2A2_19", - "CFG_CENTER_IMUX11_10", - "CFG_CENTER_IMUX8_16", - "CFG_CENTER_EE4BEG1_8", - "CFG_CENTER_LOGIC_OUTS_B4_1", - "CFG_CENTER_WW2END3_19", - "CFG_CENTER_WW4END1_5", - "CFG_CENTER_EE4BEG0_8", - "CFG_CENTER_WW4A0_6", - "CFG_CENTER_WW4A0_12", - "CFG_CENTER_IMUX26_12", - "CFG_CENTER_IMUX6_2", - "CFG_CENTER_WW4END0_8", - "CFG_CENTER_WW4B3_10", - "CFG_CENTER_LOGIC_OUTS_B19_12", - "CFG_CENTER_SW4A2_4", - "CFG_CENTER_IMUX10_16", - "CFG_CENTER_WR1END1_3", - "CFG_CENTER_SW4A0_9", - "CFG_CENTER_IMUX43_11", - "CFG_CENTER_SE2A1_7", - "CFG_CENTER_CTRL0_6", - "CFG_CENTER_WW4B2_14", - "CFG_CENTER_WW2END2_10", - "CFG_CENTER_EE4BEG1_19", - "CFG_CENTER_EE4A0_14", - "CFG_CENTER_LOGIC_OUTS_B10_9", - "CFG_CENTER_LOGIC_OUTS_B19_10", - "CFG_CENTER_SE4C0_13", - "CFG_CENTER_SW2A0_7", - "CFG_CENTER_LOGIC_OUTS_B0_19", - "CFG_CENTER_LOGIC_OUTS_B23_1", - "CFG_CENTER_IMUX37_6", - "CFG_CENTER_SW4A0_5", - "CFG_CENTER_EE2BEG0_0", - "CFG_CENTER_WW4C1_11", - "CFG_CENTER_EE2A3_17", - "CFG_CENTER_LH9_7", - "CFG_CENTER_CLK0_13", - "CFG_CENTER_WW2A2_12", - "CFG_CENTER_LOGIC_OUTS_B10_10", - "CFG_CENTER_LOGIC_OUTS_B7_19", - "CFG_CENTER_IMUX37_8", - "CFG_CENTER_SE2A2_6", - "CFG_CENTER_NE4BEG1_19", - "CFG_CENTER_EE2BEG0_5", - "CFG_CENTER_LOGIC_OUTS_B12_18", - "CFG_CENTER_IMUX21_15", - "CFG_CENTER_LOGIC_OUTS_B9_5", - "CFG_CENTER_EE4B3_7", - "CFG_CENTER_SW4END0_4", - "CFG_CENTER_BYP4_19", - "CFG_CENTER_CLK1_6", - "CFG_CENTER_FAN1_19", - "CFG_CENTER_WW4C0_0", - "CFG_CENTER_EE4A1_8", - "CFG_CENTER_IMUX30_6", - "CFG_CENTER_BYP2_16", - "CFG_CENTER_IMUX47_5", - "CFG_CENTER_WR1END3_13", - "CFG_CENTER_IMUX14_13", - "CFG_CENTER_EE4BEG1_12", - "CFG_CENTER_IMUX22_15", - "CFG_CENTER_EE4C3_8", - "CFG_CENTER_IMUX20_0", - "CFG_CENTER_SW2A0_1", - "CFG_CENTER_SW4END2_15", - "CFG_CENTER_LOGIC_OUTS_B13_7", - "CFG_CENTER_NW2A2_13", - "CFG_CENTER_IMUX19_6", - "CFG_CENTER_EL1BEG3_0", - "CFG_CENTER_LOGIC_OUTS_B7_1", - "CFG_CENTER_WL1END1_12", - "CFG_CENTER_LH4_8", - "CFG_CENTER_IMUX10_18", - "CFG_CENTER_EE4A1_0", - "CFG_CENTER_NE4BEG3_8", - "CFG_CENTER_LOGIC_OUTS_B14_9", - "CFG_CENTER_IMUX6_4", - "CFG_CENTER_BYP2_6", - "CFG_CENTER_SW2A0_5", - "CFG_CENTER_LH1_1", - "CFG_CENTER_LOGIC_OUTS_B10_7", - "CFG_CENTER_IMUX24_2", - "CFG_CENTER_SW4A2_7", - "CFG_CENTER_LH8_17", - "CFG_CENTER_EE4BEG1_13", - "CFG_CENTER_IMUX16_15", - "CFG_CENTER_FAN6_19", - "CFG_CENTER_LOGIC_OUTS_B12_7", - "CFG_CENTER_IMUX37_3", - "CFG_CENTER_IMUX15_17", - "CFG_CENTER_EE4A3_9", - "CFG_CENTER_EE4A1_15", - "CFG_CENTER_NE4BEG2_10", - "CFG_CENTER_SE2A1_9", - "CFG_CENTER_EE4B1_0", - "CFG_CENTER_LOGIC_OUTS_B4_3", - "CFG_CENTER_IMUX47_1", - "CFG_CENTER_WW2END1_5", - "CFG_CENTER_BYP2_7", - "CFG_CENTER_WW4B2_16", - "CFG_CENTER_SW4A2_5", - "CFG_CENTER_LOGIC_OUTS_B2_15", - "CFG_CENTER_WW4A0_7", - "CFG_CENTER_BYP2_19", - "CFG_CENTER_SW4A2_15", - "CFG_CENTER_SW4END1_7", - "CFG_CENTER_NW2A0_18", - "CFG_CENTER_LOGIC_OUTS_B6_10", - "CFG_CENTER_WW4C2_6", - "CFG_CENTER_SW2A0_12", - "CFG_CENTER_FAN1_6", - "CFG_CENTER_IMUX22_13", - "CFG_CENTER_IMUX4_9", - "CFG_CENTER_IMUX16_0", - "CFG_CENTER_IMUX16_17", - "CFG_CENTER_WW4END2_14", - "CFG_CENTER_SE2A0_17", - "CFG_CENTER_IMUX32_7", - "CFG_CENTER_IMUX7_15", - "CFG_CENTER_SW4END3_5", - "CFG_CENTER_WW4A1_0", - "CFG_CENTER_LOGIC_OUTS_B0_18", - "CFG_CENTER_WW4A2_0", - "CFG_CENTER_WW2A0_0", - "CFG_CENTER_EE4C3_17", - "CFG_CENTER_FAN4_2", - "CFG_CENTER_BLOCK_OUTS_B1_18", - "CFG_CENTER_IMUX17_12", - "CFG_CENTER_IMUX19_1", - "CFG_CENTER_WW2END1_7", - "CFG_CENTER_IMUX37_12", - "CFG_CENTER_IMUX33_9", - "CFG_CENTER_FAN7_10", - "CFG_CENTER_IMUX47_0", - "CFG_CENTER_SE2A0_14", - "CFG_CENTER_IMUX44_11", - "CFG_CENTER_FAN0_8", - "CFG_CENTER_NW4A1_14", - "CFG_CENTER_NW2A2_12", - "CFG_CENTER_FAN3_17", - "CFG_CENTER_NE4BEG0_13", - "CFG_CENTER_EE4B3_14", - "CFG_CENTER_WL1END2_15", - "CFG_CENTER_LOGIC_OUTS_B23_10", - "CFG_CENTER_LOGIC_OUTS_B20_19", - "CFG_CENTER_FAN5_19", - "CFG_CENTER_EE4C0_11", - "CFG_CENTER_NE2A0_15", - "CFG_CENTER_IMUX5_14", - "CFG_CENTER_SW4A1_19", - "CFG_CENTER_EE4BEG3_9", - "CFG_CENTER_EE2BEG2_17", - "CFG_CENTER_EE4C1_12", - "CFG_CENTER_EE4B2_6", - "CFG_CENTER_EL1BEG1_16", - "CFG_CENTER_WW2A0_12", - "CFG_CENTER_SW4END1_14", - "CFG_CENTER_SE4BEG2_3", - "CFG_CENTER_EE4BEG1_5", - "CFG_CENTER_IMUX7_10", - "CFG_CENTER_SE4BEG3_18", - "CFG_CENTER_NW4END3_16", - "CFG_CENTER_LOGIC_OUTS_B8_7", - "CFG_CENTER_IMUX41_14", - "CFG_CENTER_FAN1_7", - "CFG_CENTER_SW2A1_14", - "CFG_CENTER_BYP0_9", - "CFG_CENTER_NW4END0_0", - "CFG_CENTER_IMUX41_2", - "CFG_CENTER_IMUX20_3", - "CFG_CENTER_EE4BEG1_4", - "CFG_CENTER_SE4C1_7", - "CFG_CENTER_LH3_14", - "CFG_CENTER_SW4A3_10", - "CFG_CENTER_SE2A2_3", - "CFG_CENTER_LOGIC_OUTS_B20_16", - "CFG_CENTER_LOGIC_OUTS_B17_8", - "CFG_CENTER_EL1BEG1_2", - "CFG_CENTER_EE4C1_17", - "CFG_CENTER_EE4B3_11", - "CFG_CENTER_IMUX38_16", - "CFG_CENTER_NE4BEG3_18", - "CFG_CENTER_WW2END1_11", - "CFG_CENTER_LOGIC_OUTS_B12_3", - "CFG_CENTER_NW2A2_8", - "CFG_CENTER_SW4A3_17", - "CFG_CENTER_FAN5_10", - "CFG_CENTER_SE2A0_4", - "CFG_CENTER_LOGIC_OUTS_B12_12", - "CFG_CENTER_CLK0_11", - "CFG_CENTER_WW4END1_12", - "CFG_CENTER_EE4C3_3", - "CFG_CENTER_LOGIC_OUTS_B16_8", - "CFG_CENTER_WW4A1_1", - "CFG_CENTER_IMUX25_10", - "CFG_CENTER_EE2BEG0_4", - "CFG_CENTER_SE4C3_4", - "CFG_CENTER_LOGIC_OUTS_B18_12", - "CFG_CENTER_EE4A1_14", - "CFG_CENTER_NE4C3_6", - "CFG_CENTER_IMUX14_0", - "CFG_CENTER_SE4C2_16", - "CFG_CENTER_EE4A0_0", - "CFG_CENTER_EE4B2_8", - "CFG_CENTER_WW2END3_0", - "CFG_CENTER_ER1BEG2_19", - "CFG_CENTER_LOGIC_OUTS_B11_2", - "CFG_CENTER_EL1BEG1_6", - "CFG_CENTER_IMUX5_3", - "CFG_CENTER_NE2A3_7", - "CFG_CENTER_IMUX40_5", - "CFG_CENTER_IMUX37_0", - "CFG_CENTER_IMUX24_10", - "CFG_CENTER_WR1END3_6", - "CFG_CENTER_BLOCK_OUTS_B1_15", - "CFG_CENTER_BLOCK_OUTS_B2_13", - "CFG_CENTER_EE2A0_10", - "CFG_CENTER_IMUX18_7", - "CFG_CENTER_IMUX0_17", - "CFG_CENTER_LOGIC_OUTS_B0_3", - "CFG_CENTER_LH5_11", - "CFG_CENTER_BLOCK_OUTS_B3_18", - "CFG_CENTER_IMUX17_0", - "CFG_CENTER_IMUX38_0", - "CFG_CENTER_BLOCK_OUTS_B1_13", - "CFG_CENTER_NW4END0_4", - "CFG_CENTER_LOGIC_OUTS_B12_1", - "CFG_CENTER_LOGIC_OUTS_B6_6", - "CFG_CENTER_WW2END0_18", - "CFG_CENTER_WW4C2_5", - "CFG_CENTER_EE2BEG1_4", - "CFG_CENTER_LOGIC_OUTS_B20_5", - "CFG_CENTER_WW4B3_7", - "CFG_CENTER_NE4C3_13", - "CFG_CENTER_SW4END3_0", - "CFG_CENTER_BYP7_19", - "CFG_CENTER_LOGIC_OUTS_B3_17", - "CFG_CENTER_SE2A3_4", - "CFG_CENTER_LOGIC_OUTS_B16_1", - "CFG_CENTER_CTRL1_6", - "CFG_CENTER_NW4A0_11", - "CFG_CENTER_WW4C1_9", - "CFG_CENTER_SE2A0_10", - "CFG_CENTER_WW4C1_18", - "CFG_CENTER_LH2_11", - "CFG_CENTER_NE2A3_11", - "CFG_CENTER_NE4BEG3_9", - "CFG_CENTER_LOGIC_OUTS_B10_12", - "CFG_CENTER_EE2BEG2_12", - "CFG_CENTER_WR1END2_16", - "CFG_CENTER_LH2_3", - "CFG_CENTER_IMUX47_4", - "CFG_CENTER_ER1BEG2_18", - "CFG_CENTER_LOGIC_OUTS_B8_12", - "CFG_CENTER_CLK0_1", - "CFG_CENTER_IMUX31_9", - "CFG_CENTER_IMUX29_4", - "CFG_CENTER_FAN0_14", - "CFG_CENTER_BYP1_8", - "CFG_CENTER_SE4C2_19", - "CFG_CENTER_NE4BEG0_1", - "CFG_CENTER_LOGIC_OUTS_B3_4", - "CFG_CENTER_SE2A3_8", - "CFG_CENTER_EE4A2_13", - "CFG_CENTER_LH1_18", - "CFG_CENTER_NE4BEG2_0", - "CFG_CENTER_FAN6_7", - "CFG_CENTER_EE4BEG0_17", - "CFG_CENTER_IMUX27_5", - "CFG_CENTER_IMUX22_6", - "CFG_CENTER_EE2A2_6", - "CFG_CENTER_IMUX27_19", - "CFG_CENTER_SW2A1_12", - "CFG_CENTER_FAN6_4", - "CFG_CENTER_SW4END0_9", - "CFG_CENTER_IMUX8_9", - "CFG_CENTER_BOT_USR_ACCESS_DATA12", - "CFG_CENTER_LOGIC_OUTS_B3_6", - "CFG_CENTER_IMUX2_0", - "CFG_CENTER_SW4A2_13", - "CFG_CENTER_IMUX17_19", - "CFG_CENTER_IMUX11_9", - "CFG_CENTER_SE2A3_5", - "CFG_CENTER_BYP0_0", - "CFG_CENTER_WL1END1_18", - "CFG_CENTER_LH1_14", - "CFG_CENTER_IMUX46_1", - "CFG_CENTER_ER1BEG2_5", - "CFG_CENTER_FAN5_5", - "CFG_CENTER_IMUX0_4", - "CFG_CENTER_LOGIC_OUTS_B12_19", - "CFG_CENTER_EE4C1_0", - "CFG_CENTER_NW2A0_0", - "CFG_CENTER_WL1END2_0", - "CFG_CENTER_WW4C2_13", - "CFG_CENTER_SE4C0_9", - "CFG_CENTER_FAN5_4", - "CFG_CENTER_SW2A2_9", - "CFG_CENTER_EE4B1_8", - "CFG_CENTER_EE2BEG0_3", - "CFG_CENTER_SW4A2_14", - "CFG_CENTER_NE4C3_9", - "CFG_CENTER_CTRL1_16", - "CFG_CENTER_FAN2_12", - "CFG_CENTER_IMUX30_5", - "CFG_CENTER_FAN4_13", - "CFG_CENTER_LH5_8", - "CFG_CENTER_WW4B3_17", - "CFG_CENTER_BYP1_0", - "CFG_CENTER_SW4END1_3", - "CFG_CENTER_BYP6_7", - "CFG_CENTER_IMUX13_3", - "CFG_CENTER_LOGIC_OUTS_B17_5", - "CFG_CENTER_WW4END3_3", - "CFG_CENTER_NE4BEG1_0", - "CFG_CENTER_LOGIC_OUTS_B9_19", - "CFG_CENTER_IMUX20_14", - "CFG_CENTER_WW4END2_7", - "CFG_CENTER_WW4END1_0", - "CFG_CENTER_NW2A0_14", - "CFG_CENTER_IMUX38_9", - "CFG_CENTER_IMUX12_18", - "CFG_CENTER_WW4B3_4", - "CFG_CENTER_LH2_19", - "CFG_CENTER_IMUX5_8", - "CFG_CENTER_SW4END2_10", - "CFG_CENTER_WW4C3_1", - "CFG_CENTER_EE4B0_0", - "CFG_CENTER_LOGIC_OUTS_B1_18", - "CFG_CENTER_EE4BEG0_15", - "CFG_CENTER_WW4C0_17", - "CFG_CENTER_EE4B3_3", - "CFG_CENTER_IMUX23_1", - "CFG_CENTER_BYP0_15", - "CFG_CENTER_WW4A0_13", - "CFG_CENTER_FAN5_12", - "CFG_CENTER_IMUX1_5", - "CFG_CENTER_BYP3_3", - "CFG_CENTER_IMUX23_16", - "CFG_CENTER_IMUX1_11", - "CFG_CENTER_WL1END2_16", - "CFG_CENTER_IMUX21_10", - "CFG_CENTER_LOGIC_OUTS_B12_0", - "CFG_CENTER_IMUX14_9", - "CFG_CENTER_IMUX13_11", - "CFG_CENTER_NE4C1_19", - "CFG_CENTER_SW4A3_4", - "CFG_CENTER_LH10_12", - "CFG_CENTER_LOGIC_OUTS_B13_17", - "CFG_CENTER_IMUX24_5", - "CFG_CENTER_WW4A0_11", - "CFG_CENTER_FAN0_6", - "CFG_CENTER_ER1BEG3_10", - "CFG_CENTER_FAN7_18", - "CFG_CENTER_IMUX24_4", - "CFG_CENTER_EE4A1_7", - "CFG_CENTER_IMUX42_0", - "CFG_CENTER_LOGIC_OUTS_B3_1", - "CFG_CENTER_WL1END1_7", - "CFG_CENTER_LH10_5", - "CFG_CENTER_CTRL0_17", - "CFG_CENTER_LH5_15", - "CFG_CENTER_FAN1_18", - "CFG_CENTER_LOGIC_OUTS_B22_6", - "CFG_CENTER_WW2END0_1", - "CFG_CENTER_BYP5_3", - "CFG_CENTER_WW2A2_0", - "CFG_CENTER_LOGIC_OUTS_B21_3", - "CFG_CENTER_LOGIC_OUTS_B11_5", - "CFG_CENTER_BLOCK_OUTS_B3_15", - "CFG_CENTER_WW4END2_15", - "CFG_CENTER_SE2A1_14", - "CFG_CENTER_IMUX0_11", - "CFG_CENTER_EE4B2_12", - "CFG_CENTER_FAN3_9", - "CFG_CENTER_NE4BEG1_2", - "CFG_CENTER_IMUX18_2", - "CFG_CENTER_EE4B0_2", - "CFG_CENTER_EL1BEG3_15", - "CFG_CENTER_WW4B2_18", - "CFG_CENTER_BYP0_2", - "CFG_CENTER_NE4C0_8", - "CFG_CENTER_SW4A3_12", - "CFG_CENTER_IMUX30_12", - "CFG_CENTER_LOGIC_OUTS_B2_4", - "CFG_CENTER_SW4END0_2", - "CFG_CENTER_NW4A0_19", - "CFG_CENTER_LH12_5", - "CFG_CENTER_IMUX18_5", - "CFG_CENTER_NE4BEG0_4", - "CFG_CENTER_NW4A1_19", - "CFG_CENTER_LH5_9", - "CFG_CENTER_ER1BEG0_6", - "CFG_CENTER_NE2A2_11", - "CFG_CENTER_IMUX41_18", - "CFG_CENTER_NW2A0_9", - "CFG_CENTER_LOGIC_OUTS_B6_19", - "CFG_CENTER_EE4C1_14", - "CFG_CENTER_NE4C2_9", - "CFG_CENTER_IMUX14_11", - "CFG_CENTER_LOGIC_OUTS_B15_9", - "CFG_CENTER_IMUX28_7", - "CFG_CENTER_FAN1_15", - "CFG_CENTER_WW2END0_9", - "CFG_CENTER_BYP2_13", - "CFG_CENTER_NE4BEG1_9", - "CFG_CENTER_IMUX28_19", - "CFG_CENTER_EE4C3_14", - "CFG_CENTER_LH10_10", - "CFG_CENTER_NW2A2_10", - "CFG_CENTER_NE4C2_2", - "CFG_CENTER_LH4_7", - "CFG_CENTER_WW4END3_15", - "CFG_CENTER_IMUX45_13", - "CFG_CENTER_WL1END3_2", - "CFG_CENTER_IMUX13_9", - "CFG_CENTER_WL1END0_14", - "CFG_CENTER_EL1BEG1_12", - "CFG_CENTER_EE4B0_16", - "CFG_CENTER_WW4B2_13", - "CFG_CENTER_FAN3_16", - "CFG_CENTER_LH10_2", - "CFG_CENTER_SE4C3_18", - "CFG_CENTER_NW2A2_16", - "CFG_CENTER_EE2A0_8", - "CFG_CENTER_WW4END0_13", - "CFG_CENTER_WW4END2_11", - "CFG_CENTER_SE4BEG1_16", - "CFG_CENTER_WW2A0_6", - "CFG_CENTER_SE4C2_9", - "CFG_CENTER_FAN5_6", - "CFG_CENTER_LOGIC_OUTS_B5_1", - "CFG_CENTER_WW2A2_11", - "CFG_CENTER_BLOCK_OUTS_B0_6", - "CFG_CENTER_EE4B1_5", - "CFG_CENTER_WW4B1_7", - "CFG_CENTER_BLOCK_OUTS_B3_12", - "CFG_CENTER_SW2A3_15", - "CFG_CENTER_ER1BEG0_12", - "CFG_CENTER_LOGIC_OUTS_B15_10", - "CFG_CENTER_WW4A0_2", - "CFG_CENTER_IMUX38_17", - "CFG_CENTER_LOGIC_OUTS_B20_12", - "CFG_CENTER_IMUX6_3", - "CFG_CENTER_IMUX37_2", - "CFG_CENTER_IMUX35_1", - "CFG_CENTER_SW4A2_3", - "CFG_CENTER_SE4C2_12", - "CFG_CENTER_FAN0_15", - "CFG_CENTER_IMUX1_16", - "CFG_CENTER_EE4BEG2_3", - "CFG_CENTER_SW4A2_17", - "CFG_CENTER_LOGIC_OUTS_B7_14", - "CFG_CENTER_NE4C2_19", - "CFG_CENTER_SE4BEG1_11", - "CFG_CENTER_SW4A1_7", - "CFG_CENTER_WW2END3_9", - "CFG_CENTER_SW2A2_17", - "CFG_CENTER_LH6_11", - "CFG_CENTER_EE2BEG3_9", - "CFG_CENTER_NE2A1_10", - "CFG_CENTER_WW4END1_14", - "CFG_CENTER_EE4C0_6", - "CFG_CENTER_IMUX31_7", - "CFG_CENTER_LH10_13", - "CFG_CENTER_IMUX18_19", - "CFG_CENTER_LOGIC_OUTS_B5_14", - "CFG_CENTER_IMUX43_1", - "CFG_CENTER_EE4C0_4", - "CFG_CENTER_ER1BEG0_0", - "CFG_CENTER_WW4END2_6", - "CFG_CENTER_LOGIC_OUTS_B22_16", - "CFG_CENTER_WW2END2_1", - "CFG_CENTER_WW4C1_14", - "CFG_CENTER_SW2A2_6", - "CFG_CENTER_SW2A3_17", - "CFG_CENTER_EE2BEG2_7", - "CFG_CENTER_EL1BEG0_17", - "CFG_CENTER_WW2A1_6", - "CFG_CENTER_EE4BEG1_11", - "CFG_CENTER_FAN6_16", - "CFG_CENTER_LOGIC_OUTS_B0_11", - "CFG_CENTER_IMUX4_12", - "CFG_CENTER_SW2A1_15", - "CFG_CENTER_SW2A3_8", - "CFG_CENTER_CTRL1_13", - "CFG_CENTER_LOGIC_OUTS_B20_6", - "CFG_CENTER_EE2BEG2_19", - "CFG_CENTER_WW4B3_12", - "CFG_CENTER_BLOCK_OUTS_B2_18", - "CFG_CENTER_WL1END0_3", - "CFG_CENTER_WL1END0_12", - "CFG_CENTER_SW4END0_6", - "CFG_CENTER_EE2BEG1_12", - "CFG_CENTER_SE4BEG0_4", - "CFG_CENTER_CTRL0_16", - "CFG_CENTER_ER1BEG2_1", - "CFG_CENTER_IMUX42_15", - "CFG_CENTER_LH1_19", - "CFG_CENTER_EE4C1_1", - "CFG_CENTER_IMUX15_3", - "CFG_CENTER_EE4C3_12", - "CFG_CENTER_BYP1_19", - "CFG_CENTER_LOGIC_OUTS_B17_4", - "CFG_CENTER_LH3_5", - "CFG_CENTER_NW4A3_13", - "CFG_CENTER_WW2END3_5", - "CFG_CENTER_WW4A3_12", - "CFG_CENTER_WW4A3_8", - "CFG_CENTER_WL1END1_19", - "CFG_CENTER_IMUX24_15", - "CFG_CENTER_CTRL1_17", - "CFG_CENTER_EE2BEG1_7", - "CFG_CENTER_LH7_7", - "CFG_CENTER_LOGIC_OUTS_B12_8", - "CFG_CENTER_EL1BEG1_15", - "CFG_CENTER_FAN7_9", - "CFG_CENTER_LOGIC_OUTS_B7_2", - "CFG_CENTER_SW4A0_7", - "CFG_CENTER_WW4C1_12", - "CFG_CENTER_LOGIC_OUTS_B14_5", - "CFG_CENTER_EE4BEG3_1", - "CFG_CENTER_LOGIC_OUTS_B7_17", - "CFG_CENTER_NW2A2_14", - "CFG_CENTER_EL1BEG1_4", - "CFG_CENTER_IMUX25_2", - "CFG_CENTER_LOGIC_OUTS_B1_9", - "CFG_CENTER_CTRL1_15", - "CFG_CENTER_LOGIC_OUTS_B3_8", - "CFG_CENTER_NE4C3_4", - "CFG_CENTER_CLK1_4", - "CFG_CENTER_IMUX15_9", - "CFG_CENTER_IMUX33_0", - "CFG_CENTER_NW4A1_8", - "CFG_CENTER_EE4A3_7", - "CFG_CENTER_WW4END1_13", - "CFG_CENTER_WW4C3_14", - "CFG_CENTER_IMUX1_8", - "CFG_CENTER_LOGIC_OUTS_B16_6", - "CFG_CENTER_NE4C3_0", - "CFG_CENTER_LOGIC_OUTS_B2_1", - "CFG_CENTER_ER1BEG1_16", - "CFG_CENTER_IMUX25_16", - "CFG_CENTER_IMUX22_14", - "CFG_CENTER_IMUX7_5", - "CFG_CENTER_SW2A2_0", - "CFG_CENTER_EL1BEG3_11", - "CFG_CENTER_EE4C0_15", - "CFG_CENTER_LOGIC_OUTS_B11_7", - "CFG_CENTER_WW4C2_2", - "CFG_CENTER_EE2BEG0_7", - "CFG_CENTER_WW4C2_18", - "CFG_CENTER_IMUX14_5", - "CFG_CENTER_SE4BEG1_4", - "CFG_CENTER_EE4B0_5", - "CFG_CENTER_IMUX16_8", - "CFG_CENTER_LH7_0", - "CFG_CENTER_IMUX26_17", - "CFG_CENTER_LOGIC_OUTS_B0_17", - "CFG_CENTER_IMUX2_4", - "CFG_CENTER_LOGIC_OUTS_B5_4", - "CFG_CENTER_EE2BEG1_14", - "CFG_CENTER_IMUX26_0", - "CFG_CENTER_IMUX19_2", - "CFG_CENTER_NW4A2_3", - "CFG_CENTER_SE4C0_1", - "CFG_CENTER_EE2BEG2_0", - "CFG_CENTER_EE4C2_17", - "CFG_CENTER_SW4A0_16", - "CFG_CENTER_BLOCK_OUTS_B1_17", - "CFG_CENTER_EE2A1_9", - "CFG_CENTER_IMUX1_2", - "CFG_CENTER_EE2A1_2", - "CFG_CENTER_IMUX32_16", - "CFG_CENTER_NE2A0_19", - "CFG_CENTER_IMUX2_15", - "CFG_CENTER_ER1BEG3_9", - "CFG_CENTER_EE4C0_10", - "CFG_CENTER_IMUX3_7", - "CFG_CENTER_IMUX23_2", - "CFG_CENTER_IMUX45_9", - "CFG_CENTER_EE4C0_12", - "CFG_CENTER_IMUX17_15", - "CFG_CENTER_IMUX0_15", - "CFG_CENTER_WW4END3_0", - "CFG_CENTER_WL1END2_2", - "CFG_CENTER_EL1BEG2_4", - "CFG_CENTER_EE4A3_11", - "CFG_CENTER_LOGIC_OUTS_B17_19", - "CFG_CENTER_IMUX15_1", - "CFG_CENTER_EE4BEG3_13", - "CFG_CENTER_LOGIC_OUTS_B1_11", - "CFG_CENTER_IMUX23_14", - "CFG_CENTER_EE2A1_16", - "CFG_CENTER_LH11_2", - "CFG_CENTER_WW4END3_10", - "CFG_CENTER_LOGIC_OUTS_B14_7", - "CFG_CENTER_IMUX28_0", - "CFG_CENTER_EE4B2_3", - "CFG_CENTER_NE4C1_2", - "CFG_CENTER_IMUX13_2", - "CFG_CENTER_FAN5_2", - "CFG_CENTER_EE4B1_16", - "CFG_CENTER_IMUX5_15", - "CFG_CENTER_IMUX37_15", - "CFG_CENTER_IMUX46_18", - "CFG_CENTER_EE4A3_17", - "CFG_CENTER_IMUX22_10", - "CFG_CENTER_WR1END0_19", - "CFG_CENTER_IMUX24_12", - "CFG_CENTER_IMUX40_9", - "CFG_CENTER_NW4END1_11", - "CFG_CENTER_IMUX22_16", - "CFG_CENTER_EE4BEG3_7", - "CFG_CENTER_WW4C0_6", - "CFG_CENTER_WW4C0_1", - "CFG_CENTER_BLOCK_OUTS_B1_0", - "CFG_CENTER_SW4A3_8", - "CFG_CENTER_EE4B2_17", - "CFG_CENTER_WL1END3_13", - "CFG_CENTER_EE4B1_15", - "CFG_CENTER_IMUX41_19", - "CFG_CENTER_NE2A1_9", - "CFG_CENTER_EE4BEG3_5", - "CFG_CENTER_BOT_USR_ACCESS_DATA10", - "CFG_CENTER_IMUX6_11", - "CFG_CENTER_LOGIC_OUTS_B22_4", - "CFG_CENTER_IMUX42_7", - "CFG_CENTER_IMUX21_18", - "CFG_CENTER_WL1END3_16", - "CFG_CENTER_EE2BEG1_0", - "CFG_CENTER_CTRL1_19", - "CFG_CENTER_NE4C1_17", - "CFG_CENTER_SW2A2_5", - "CFG_CENTER_SE2A2_12", - "CFG_CENTER_WW2A3_12", - "CFG_CENTER_LH8_5", - "CFG_CENTER_IMUX8_1", - "CFG_CENTER_LOGIC_OUTS_B13_15", - "CFG_CENTER_WL1END3_12", - "CFG_CENTER_EE4BEG2_18", - "CFG_CENTER_IMUX0_12", - "CFG_CENTER_EL1BEG2_9", - "CFG_CENTER_NE4BEG0_0", - "CFG_CENTER_SE4BEG1_14", - "CFG_CENTER_CLK1_8", - "CFG_CENTER_WW2END2_7", - "CFG_CENTER_NW4A0_4", - "CFG_CENTER_LOGIC_OUTS_B14_0", - "CFG_CENTER_FAN4_12", - "CFG_CENTER_LH10_8", - "CFG_CENTER_LOGIC_OUTS_B5_17", - "CFG_CENTER_FAN3_12", - "CFG_CENTER_WR1END0_6", - "CFG_CENTER_SW4A3_6", - "CFG_CENTER_EE2BEG3_0", - "CFG_CENTER_LOGIC_OUTS_B23_4", - "CFG_CENTER_EE4C1_4", - "CFG_CENTER_WW2A1_7", - "CFG_CENTER_BLOCK_OUTS_B3_17", - "CFG_CENTER_IMUX36_2", - "CFG_CENTER_SE4C3_1", - "CFG_CENTER_NW2A2_2", - "CFG_CENTER_WW4END3_16", - "CFG_CENTER_SW4END1_0", - "CFG_CENTER_IMUX30_16", - "CFG_CENTER_EE2A2_11", - "CFG_CENTER_NE4BEG2_11", - "CFG_CENTER_CLK1_15", - "CFG_CENTER_IMUX38_12", - "CFG_CENTER_BOT_USR_ACCESS_DATA13", - "CFG_CENTER_IMUX15_0", - "CFG_CENTER_LOGIC_OUTS_B13_4", - "CFG_CENTER_EL1BEG0_4", - "CFG_CENTER_LH8_13", - "CFG_CENTER_IMUX34_19", - "CFG_CENTER_SE4BEG0_9", - "CFG_CENTER_FAN5_8", - "CFG_CENTER_IMUX28_13", - "CFG_CENTER_IMUX9_15", - "CFG_CENTER_LOGIC_OUTS_B7_0", - "CFG_CENTER_BYP0_6", - "CFG_CENTER_EE4B1_11", - "CFG_CENTER_WW4B1_19", - "CFG_CENTER_NE2A0_11", - "CFG_CENTER_SW4END2_12", - "CFG_CENTER_NE4C1_6", - "CFG_CENTER_EE2BEG0_19", - "CFG_CENTER_IMUX25_17", - "CFG_CENTER_SE4BEG0_6", - "CFG_CENTER_SE4C0_14", - "CFG_CENTER_NE4BEG2_6", - "CFG_CENTER_LOGIC_OUTS_B21_16", - "CFG_CENTER_FAN5_13", - "CFG_CENTER_EE4BEG3_16", - "CFG_CENTER_IMUX21_14", - "CFG_CENTER_EL1BEG2_1", - "CFG_CENTER_WW2END0_16", - "CFG_CENTER_WW4A1_10", - "CFG_CENTER_NE4C1_4", - "CFG_CENTER_LH11_15", - "CFG_CENTER_EE2BEG1_13", - "CFG_CENTER_LH3_16", - "CFG_CENTER_LOGIC_OUTS_B18_3", - "CFG_CENTER_IMUX37_1", - "CFG_CENTER_IMUX46_7", - "CFG_CENTER_BYP7_13", - "CFG_CENTER_IMUX19_4", - "CFG_CENTER_IMUX46_12", - "CFG_CENTER_LOGIC_OUTS_B3_2", - "CFG_CENTER_LOGIC_OUTS_B11_3", - "CFG_CENTER_IMUX42_14", - "CFG_CENTER_SW4A0_10", - "CFG_CENTER_EE2A0_16", - "CFG_CENTER_SE4BEG2_0", - "CFG_CENTER_WW2A1_9", - "CFG_CENTER_SE4BEG3_8", - "CFG_CENTER_IMUX35_18", - "CFG_CENTER_WW4END1_7", - "CFG_CENTER_SW4END2_18", - "CFG_CENTER_IMUX6_5", - "CFG_CENTER_LOGIC_OUTS_B8_4", - "CFG_CENTER_WW4A2_9", - "CFG_CENTER_LH9_9", - "CFG_CENTER_WW4A3_2", - "CFG_CENTER_IMUX41_5", - "CFG_CENTER_FAN0_7", - "CFG_CENTER_BYP4_3", - "CFG_CENTER_WW4B1_3", - "CFG_CENTER_LH2_16", - "CFG_CENTER_EE4BEG2_10", - "CFG_CENTER_SW2A1_17", - "CFG_CENTER_IMUX17_16", - "CFG_CENTER_IMUX9_5", - "CFG_CENTER_NE4BEG2_2", - "CFG_CENTER_WW2A3_2", - "CFG_CENTER_NW2A2_18", - "CFG_CENTER_LH5_6", - "CFG_CENTER_EE2BEG0_17", - "CFG_CENTER_IMUX47_9", - "CFG_CENTER_IMUX16_9", - "CFG_CENTER_WR1END0_17", - "CFG_CENTER_LH9_16", - "CFG_CENTER_BLOCK_OUTS_B0_0", - "CFG_CENTER_IMUX27_12", - "CFG_CENTER_BLOCK_OUTS_B3_11", - "CFG_CENTER_EE4BEG1_0", - "CFG_CENTER_BYP1_7", - "CFG_CENTER_NW4END2_14", - "CFG_CENTER_IMUX4_18", - "CFG_CENTER_EL1BEG3_10", - "CFG_CENTER_NW4END0_3", - "CFG_CENTER_BYP2_15", - "CFG_CENTER_LOGIC_OUTS_B11_9", - "CFG_CENTER_WW4C0_2", - "CFG_CENTER_LH9_19", - "CFG_CENTER_BYP0_7", - "CFG_CENTER_IMUX46_15", - "CFG_CENTER_BYP2_5", - "CFG_CENTER_SW4END0_13", - "CFG_CENTER_SE4BEG3_11", - "CFG_CENTER_SE4BEG0_8", - "CFG_CENTER_LH4_13", - "CFG_CENTER_LOGIC_OUTS_B3_19", - "CFG_CENTER_SE4BEG0_13", - "CFG_CENTER_CLK1_14", - "CFG_CENTER_BLOCK_OUTS_B3_13", - "CFG_CENTER_IMUX35_19", - "CFG_CENTER_IMUX3_15", - "CFG_CENTER_LOGIC_OUTS_B10_15", - "CFG_CENTER_EE4C1_2", - "CFG_CENTER_NE4C2_1", - "CFG_CENTER_WW2END2_15", - "CFG_CENTER_SW4END2_2", - "CFG_CENTER_EE4C1_9", - "CFG_CENTER_IMUX25_7", - "CFG_CENTER_NE2A3_12", - "CFG_CENTER_WW2END0_0", - "CFG_CENTER_LOGIC_OUTS_B11_0", - "CFG_CENTER_WL1END3_15", - "CFG_CENTER_SE2A3_6", - "CFG_CENTER_NE2A2_12", - "CFG_CENTER_EE4A2_0", - "CFG_CENTER_IMUX30_19", - "CFG_CENTER_EE4A3_3", - "CFG_CENTER_EL1BEG2_19", - "CFG_CENTER_WR1END3_19", - "CFG_CENTER_NW4END1_19", - "CFG_CENTER_LH9_1", - "CFG_CENTER_CTRL0_15", - "CFG_CENTER_BYP4_5", - "CFG_CENTER_NE4C3_12", - "CFG_CENTER_IMUX39_3", - "CFG_CENTER_WW2END0_3", - "CFG_CENTER_EE2A1_14", - "CFG_CENTER_BYP6_17", - "CFG_CENTER_IMUX29_9", - "CFG_CENTER_SW4END0_3", - "CFG_CENTER_EE2A0_3", - "CFG_CENTER_IMUX10_0", - "CFG_CENTER_WL1END1_6", - "CFG_CENTER_IMUX35_16", - "CFG_CENTER_EE4B1_18", - "CFG_CENTER_EE2A0_11", - "CFG_CENTER_WL1END1_8", - "CFG_CENTER_EE2A2_17", - "CFG_CENTER_IMUX11_5", - "CFG_CENTER_SE4BEG3_13", - "CFG_CENTER_NE2A1_11", - "CFG_CENTER_LOGIC_OUTS_B17_13", - "CFG_CENTER_NE4C0_13", - "CFG_CENTER_FAN3_3", - "CFG_CENTER_IMUX22_4", - "CFG_CENTER_WL1END3_6", - "CFG_CENTER_NW4END1_8", - "CFG_CENTER_SW4A3_5", - "CFG_CENTER_FAN6_8", - "CFG_CENTER_IMUX21_2", - "CFG_CENTER_IMUX1_19", - "CFG_CENTER_NE4BEG1_13", - "CFG_CENTER_NE4C0_11", - "CFG_CENTER_NE4BEG0_3", - "CFG_CENTER_LH4_3", - "CFG_CENTER_IMUX46_8", - "CFG_CENTER_IMUX40_12", - "CFG_CENTER_EE4BEG3_12", - "CFG_CENTER_LOGIC_OUTS_B4_4", - "CFG_CENTER_IMUX17_11", - "CFG_CENTER_LOGIC_OUTS_B20_4", - "CFG_CENTER_IMUX47_17", - "CFG_CENTER_IMUX28_17", - "CFG_CENTER_WW4A3_11", - "CFG_CENTER_LH11_12", - "CFG_CENTER_WW2END2_12", - "CFG_CENTER_NW2A1_3", - "CFG_CENTER_IMUX17_2", - "CFG_CENTER_IMUX25_4", - "CFG_CENTER_WW2A0_2", - "CFG_CENTER_BLOCK_OUTS_B3_3", - "CFG_CENTER_SW4END0_11", - "CFG_CENTER_EE4BEG3_2", - "CFG_CENTER_LH9_8", - "CFG_CENTER_SE4BEG1_5", - "CFG_CENTER_IMUX18_3", - "CFG_CENTER_IMUX45_17", - "CFG_CENTER_EE4B3_16", - "CFG_CENTER_WW4A0_5", - "CFG_CENTER_EE4A3_18", - "CFG_CENTER_LOGIC_OUTS_B17_1", - "CFG_CENTER_SW2A0_16", - "CFG_CENTER_FAN0_5", - "CFG_CENTER_SE4C0_12", - "CFG_CENTER_FAN4_4", - "CFG_CENTER_WW2END3_7", - "CFG_CENTER_SE4C3_15", - "CFG_CENTER_SW2A0_6", - "CFG_CENTER_EE4B0_8", - "CFG_CENTER_IMUX36_10", - "CFG_CENTER_WW4C3_8", - "CFG_CENTER_SE2A1_18", - "CFG_CENTER_IMUX1_7", - "CFG_CENTER_SW2A1_16", - "CFG_CENTER_NE2A3_14", - "CFG_CENTER_BLOCK_OUTS_B1_8", - "CFG_CENTER_EE2A3_6", - "CFG_CENTER_EL1BEG0_5", - "CFG_CENTER_LOGIC_OUTS_B18_5", - "CFG_CENTER_ER1BEG2_6", - "CFG_CENTER_WW4END3_12", - "CFG_CENTER_IMUX13_6", - "CFG_CENTER_IMUX31_1", - "CFG_CENTER_IMUX42_17", - "CFG_CENTER_LH11_5", - "CFG_CENTER_EE4A2_12", - "CFG_CENTER_WW4END0_0", - "CFG_CENTER_IMUX27_17", - "CFG_CENTER_IMUX0_8", - "CFG_CENTER_WW4C2_14", - "CFG_CENTER_IMUX30_1", - "CFG_CENTER_SE4C2_17", - "CFG_CENTER_IMUX9_17", - "CFG_CENTER_NE4BEG0_11", - "CFG_CENTER_WW4END1_16", - "CFG_CENTER_LOGIC_OUTS_B16_17", - "CFG_CENTER_FAN2_18", - "CFG_CENTER_IMUX29_6", - "CFG_CENTER_EE2A1_15", - "CFG_CENTER_WW2A0_4", - "CFG_CENTER_EE4B3_15", - "CFG_CENTER_LOGIC_OUTS_B8_14", - "CFG_CENTER_FAN2_0", - "CFG_CENTER_EL1BEG2_2", - "CFG_CENTER_WL1END1_4", - "CFG_CENTER_EE2A1_19", - "CFG_CENTER_WR1END2_7", - "CFG_CENTER_BYP0_19", - "CFG_CENTER_NE4C3_16", - "CFG_CENTER_SE4C2_7", - "CFG_CENTER_EL1BEG2_13", - "CFG_CENTER_WW2END2_11", - "CFG_CENTER_IMUX5_1", - "CFG_CENTER_IMUX31_10", - "CFG_CENTER_LH5_19", - "CFG_CENTER_LOGIC_OUTS_B23_6", - "CFG_CENTER_SW2A3_7", - "CFG_CENTER_NW2A1_0", - "CFG_CENTER_IMUX47_18", - "CFG_CENTER_EE4A2_1", - "CFG_CENTER_FAN2_5", - "CFG_CENTER_BYP2_0", - "CFG_CENTER_WL1END0_16", - "CFG_CENTER_LH12_0", - "CFG_CENTER_NW4END3_9", - "CFG_CENTER_SW4END0_0", - "CFG_CENTER_EL1BEG1_0", - "CFG_CENTER_IMUX45_8", - "CFG_CENTER_IMUX2_17", - "CFG_CENTER_NW2A0_17", - "CFG_CENTER_FAN7_5", - "CFG_CENTER_LOGIC_OUTS_B15_0", - "CFG_CENTER_WW4C3_6", - "CFG_CENTER_IMUX11_16", - "CFG_CENTER_IMUX20_11", - "CFG_CENTER_WL1END3_10", - "CFG_CENTER_IMUX10_10", - "CFG_CENTER_NW4END3_3", - "CFG_CENTER_NE4C3_2", - "CFG_CENTER_ER1BEG2_16", - "CFG_CENTER_SW4A0_18", - "CFG_CENTER_NE4BEG3_11", - "CFG_CENTER_SW4A0_19", - "CFG_CENTER_NE4C0_7", - "CFG_CENTER_BYP4_8", - "CFG_CENTER_IMUX1_18", - "CFG_CENTER_BYP3_7", - "CFG_CENTER_IMUX43_5", - "CFG_CENTER_EE2A1_5", - "CFG_CENTER_NW4END1_3", - "CFG_CENTER_WR1END1_5", - "CFG_CENTER_EE4BEG0_4", - "CFG_CENTER_NW4END0_16", - "CFG_CENTER_NW4A0_10", - "CFG_CENTER_NE4BEG0_14", - "CFG_CENTER_SE4BEG3_6", - "CFG_CENTER_IMUX41_6", - "CFG_CENTER_IMUX32_14", - "CFG_CENTER_NW2A0_11", - "CFG_CENTER_SE4BEG3_4", - "CFG_CENTER_ER1BEG1_1", - "CFG_CENTER_SE4C0_7", - "CFG_CENTER_EE4C2_8", - "CFG_CENTER_IMUX26_10", - "CFG_CENTER_IMUX36_5", - "CFG_CENTER_WW2END3_17", - "CFG_CENTER_SW4A3_13", - "CFG_CENTER_LOGIC_OUTS_B19_7", - "CFG_CENTER_WW4B2_8", - "CFG_CENTER_BYP1_4", - "CFG_CENTER_EL1BEG1_19", - "CFG_CENTER_IMUX39_4", - "CFG_CENTER_WW4B1_5", - "CFG_CENTER_NE2A2_8", - "CFG_CENTER_IMUX42_8", - "CFG_CENTER_LOGIC_OUTS_B20_9", - "CFG_CENTER_NE2A3_10", - "CFG_CENTER_BYP6_12", - "CFG_CENTER_NW4END2_2", - "CFG_CENTER_WW4A1_8", - "CFG_CENTER_IMUX3_5", - "CFG_CENTER_WW2END1_6", - "CFG_CENTER_SE2A0_8", - "CFG_CENTER_LOGIC_OUTS_B21_14", - "CFG_CENTER_FAN3_6", - "CFG_CENTER_WR1END2_17", - "CFG_CENTER_NE2A0_16", - "CFG_CENTER_IMUX10_19", - "CFG_CENTER_LOGIC_OUTS_B16_9", - "CFG_CENTER_NW4END3_12", - "CFG_CENTER_LOGIC_OUTS_B8_1", - "CFG_CENTER_IMUX32_10", - "CFG_CENTER_IMUX22_8", - "CFG_CENTER_FAN6_18", - "CFG_CENTER_FAN3_0", - "CFG_CENTER_IMUX33_7", - "CFG_CENTER_WW4A0_17", - "CFG_CENTER_IMUX0_1", - "CFG_CENTER_IMUX1_6", - "CFG_CENTER_FAN2_14", - "CFG_CENTER_EE4C2_9", - "CFG_CENTER_ER1BEG0_14", - "CFG_CENTER_SW4END3_11", - "CFG_CENTER_SW4END1_2", - "CFG_CENTER_LOGIC_OUTS_B9_17", - "CFG_CENTER_SE4C2_11", - "CFG_CENTER_BYP5_2", - "CFG_CENTER_SE4BEG2_2", - "CFG_CENTER_LOGIC_OUTS_B22_9", - "CFG_CENTER_IMUX47_3", - "CFG_CENTER_IMUX25_8", - "CFG_CENTER_SW2A0_2", - "CFG_CENTER_LOGIC_OUTS_B6_0", - "CFG_CENTER_WW2END2_18", - "CFG_CENTER_EE2BEG3_13", - "CFG_CENTER_IMUX23_19", - "CFG_CENTER_SE4C1_16", - "CFG_CENTER_IMUX28_9", - "CFG_CENTER_BLOCK_OUTS_B3_1", - "CFG_CENTER_LOGIC_OUTS_B18_10", - "CFG_CENTER_IMUX36_9", - "CFG_CENTER_LH3_9", - "CFG_CENTER_IMUX17_13", - "CFG_CENTER_CTRL1_11", - "CFG_CENTER_SE2A1_12", - "CFG_CENTER_FAN4_1", - "CFG_CENTER_LOGIC_OUTS_B13_19", - "CFG_CENTER_WW4C0_14", - "CFG_CENTER_EE4A0_10", - "CFG_CENTER_FAN0_10", - "CFG_CENTER_SE4C1_2", - "CFG_CENTER_IMUX44_17", - "CFG_CENTER_LOGIC_OUTS_B10_13", - "CFG_CENTER_NE4BEG0_6", - "CFG_CENTER_IMUX27_15", - "CFG_CENTER_FAN4_6", - "CFG_CENTER_IMUX27_18", - "CFG_CENTER_EE4B3_2", - "CFG_CENTER_LOGIC_OUTS_B8_11", - "CFG_CENTER_SW2A3_10", - "CFG_CENTER_NW2A3_16", - "CFG_CENTER_IMUX4_3", - "CFG_CENTER_IMUX30_2", - "CFG_CENTER_WL1END3_17", - "CFG_CENTER_WW4END0_14", - "CFG_CENTER_SW2A2_10", - "CFG_CENTER_WR1END2_10", - "CFG_CENTER_EE4BEG3_18", - "CFG_CENTER_BYP5_8", - "CFG_CENTER_SE2A1_1", - "CFG_CENTER_EE2A1_7", - "CFG_CENTER_LH9_14", - "CFG_CENTER_IMUX8_7", - "CFG_CENTER_SW4END0_15", - "CFG_CENTER_FAN1_4", - "CFG_CENTER_LOGIC_OUTS_B3_18", - "CFG_CENTER_EL1BEG0_7", - "CFG_CENTER_SW2A1_7", - "CFG_CENTER_IMUX18_13", - "CFG_CENTER_SE4C0_3", - "CFG_CENTER_EE4BEG0_10", - "CFG_CENTER_NW4A3_7", - "CFG_CENTER_LH1_17", - "CFG_CENTER_ER1BEG2_17", - "CFG_CENTER_IMUX6_0", - "CFG_CENTER_EL1BEG2_16", - "CFG_CENTER_EE4A1_2", - "CFG_CENTER_LH3_19", - "CFG_CENTER_BYP0_13", - "CFG_CENTER_IMUX28_6", - "CFG_CENTER_WW2END1_4", - "CFG_CENTER_NW4END3_14", - "CFG_CENTER_NW2A1_14", - "CFG_CENTER_EE2A3_19", - "CFG_CENTER_LOGIC_OUTS_B19_1", - "CFG_CENTER_SE2A3_13", - "CFG_CENTER_WW2END3_11", - "CFG_CENTER_EL1BEG2_18", - "CFG_CENTER_IMUX16_12", - "CFG_CENTER_IMUX15_7", - "CFG_CENTER_WW2A0_13", - "CFG_CENTER_SW2A1_4", - "CFG_CENTER_SE4BEG1_9", - "CFG_CENTER_IMUX21_16", - "CFG_CENTER_SW4A0_4", - "CFG_CENTER_BLOCK_OUTS_B2_8", - "CFG_CENTER_LOGIC_OUTS_B6_13", - "CFG_CENTER_BLOCK_OUTS_B2_6", - "CFG_CENTER_WL1END0_0", - "CFG_CENTER_IMUX47_8", - "CFG_CENTER_IMUX40_1", - "CFG_CENTER_IMUX10_17", - "CFG_CENTER_EE4C0_3", - "CFG_CENTER_LH5_10", - "CFG_CENTER_IMUX31_3", - "CFG_CENTER_LOGIC_OUTS_B4_7", - "CFG_CENTER_WR1END1_19", - "CFG_CENTER_ER1BEG1_10", - "CFG_CENTER_EE2BEG3_1", - "CFG_CENTER_SW2A3_6", - "CFG_CENTER_SW4A1_0", - "CFG_CENTER_WW4END0_18", - "CFG_CENTER_SW2A1_19", - "CFG_CENTER_EL1BEG2_15", - "CFG_CENTER_BYP3_6", - "CFG_CENTER_NW4A0_1", - "CFG_CENTER_IMUX14_12", - "CFG_CENTER_NE4C2_17", - "CFG_CENTER_NE4BEG1_11", - "CFG_CENTER_NW2A3_3", - "CFG_CENTER_WW2END3_1", - "CFG_CENTER_ER1BEG3_8", - "CFG_CENTER_WW2A0_9", - "CFG_CENTER_EE4BEG3_3", - "CFG_CENTER_EE2BEG0_11", - "CFG_CENTER_WW4B3_6", - "CFG_CENTER_SW4END2_13", - "CFG_CENTER_CTRL1_4", - "CFG_CENTER_IMUX8_10", - "CFG_CENTER_BLOCK_OUTS_B2_19", - "CFG_CENTER_WW4B2_19", - "CFG_CENTER_LOGIC_OUTS_B10_16", - "CFG_CENTER_WW4END3_5", - "CFG_CENTER_LOGIC_OUTS_B9_15", - "CFG_CENTER_FAN1_13", - "CFG_CENTER_NW4A2_10", - "CFG_CENTER_WL1END1_13", - "CFG_CENTER_EE2A2_4", - "CFG_CENTER_NW4A0_3", - "CFG_CENTER_IMUX10_15", - "CFG_CENTER_FAN5_15", - "CFG_CENTER_LH6_7", - "CFG_CENTER_EE2BEG0_13", - "CFG_CENTER_IMUX7_13", - "CFG_CENTER_BYP6_14", - "CFG_CENTER_NE4BEG2_1", - "CFG_CENTER_LH6_14", - "CFG_CENTER_IMUX3_14", - "CFG_CENTER_SW4A1_14", - "CFG_CENTER_NW4A3_19", - "CFG_CENTER_ER1BEG1_18", - "CFG_CENTER_NE4C0_1", - "CFG_CENTER_SE4BEG3_14", - "CFG_CENTER_SW2A0_3", - "CFG_CENTER_FAN6_11", - "CFG_CENTER_SW4A3_0", - "CFG_CENTER_IMUX3_9", - "CFG_CENTER_NE2A2_17", - "CFG_CENTER_WR1END3_12", - "CFG_CENTER_ER1BEG0_3", - "CFG_CENTER_LH4_18", - "CFG_CENTER_IMUX8_6", - "CFG_CENTER_EE4BEG1_3", - "CFG_CENTER_EE4B1_3", - "CFG_CENTER_WW4C2_1", - "CFG_CENTER_WW2A2_19", - "CFG_CENTER_NW4A2_9", - "CFG_CENTER_SW2A0_18", - "CFG_CENTER_LOGIC_OUTS_B14_1", - "CFG_CENTER_IMUX42_11", - "CFG_CENTER_WW4END0_6", - "CFG_CENTER_LH2_15", - "CFG_CENTER_IMUX3_0", - "CFG_CENTER_WR1END0_1", - "CFG_CENTER_BYP2_8", - "CFG_CENTER_ER1BEG1_4", - "CFG_CENTER_SE4BEG0_1", - "CFG_CENTER_EL1BEG3_6", - "CFG_CENTER_SW4A0_15", - "CFG_CENTER_SW4A1_9", - "CFG_CENTER_EE2A0_0", - "CFG_CENTER_WL1END0_4", - "CFG_CENTER_BLOCK_OUTS_B2_9", - "CFG_CENTER_LOGIC_OUTS_B17_2", - "CFG_CENTER_NE4C1_0", - "CFG_CENTER_IMUX45_0", - "CFG_CENTER_LOGIC_OUTS_B12_4", - "CFG_CENTER_LH4_5", - "CFG_CENTER_WW2A1_18", - "CFG_CENTER_EE2BEG2_11", - "CFG_CENTER_IMUX7_11", - "CFG_CENTER_IMUX17_7", - "CFG_CENTER_EE4B0_18", - "CFG_CENTER_BYP4_4", - "CFG_CENTER_LH10_0", - "CFG_CENTER_IMUX22_12", - "CFG_CENTER_CTRL0_14", - "CFG_CENTER_NW4A3_14", - "CFG_CENTER_LH9_13", - "CFG_CENTER_LH7_19", - "CFG_CENTER_EE4BEG1_6", - "CFG_CENTER_IMUX33_1", - "CFG_CENTER_FAN7_1", - "CFG_CENTER_WW4C2_15", - "CFG_CENTER_IMUX41_17", - "CFG_CENTER_IMUX13_17", - "CFG_CENTER_LOGIC_OUTS_B2_5", - "CFG_CENTER_SW4END1_19", - "CFG_CENTER_LH12_10", - "CFG_CENTER_IMUX4_15", - "CFG_CENTER_IMUX13_18", - "CFG_CENTER_EE2BEG1_2", - "CFG_CENTER_LOGIC_OUTS_B21_18", - "CFG_CENTER_BLOCK_OUTS_B0_18", - "CFG_CENTER_WW4C0_19", - "CFG_CENTER_IMUX18_14", - "CFG_CENTER_EE4A2_11", - "CFG_CENTER_BYP0_16", - "CFG_CENTER_IMUX44_0", - "CFG_CENTER_NW2A0_15", - "CFG_CENTER_BYP3_11", - "CFG_CENTER_IMUX5_11", - "CFG_CENTER_SE4BEG2_19", - "CFG_CENTER_ER1BEG1_15", - "CFG_CENTER_BYP7_14", - "CFG_CENTER_IMUX36_7", - "CFG_CENTER_IMUX39_13", - "CFG_CENTER_IMUX46_5", - "CFG_CENTER_EE4B2_16", - "CFG_CENTER_WW4C0_16", - "CFG_CENTER_EL1BEG2_7", - "CFG_CENTER_SE2A0_7", - "CFG_CENTER_SE4C0_19", - "CFG_CENTER_IMUX28_14", - "CFG_CENTER_LH5_3", - "CFG_CENTER_CLK0_12", - "CFG_CENTER_IMUX10_6", - "CFG_CENTER_WW4B1_13", - "CFG_CENTER_WW4END1_18", - "CFG_CENTER_EE2BEG3_16", - "CFG_CENTER_WW4C3_16", - "CFG_CENTER_IMUX9_2", - "CFG_CENTER_BYP2_3", - "CFG_CENTER_BYP4_1", - "CFG_CENTER_IMUX40_2", - "CFG_CENTER_EE4A3_8", - "CFG_CENTER_WW2A1_10", - "CFG_CENTER_CTRL0_1", - "CFG_CENTER_SE4BEG0_16", - "CFG_CENTER_SE2A1_15", - "CFG_CENTER_IMUX32_18", - "CFG_CENTER_NE2A1_5", - "CFG_CENTER_IMUX29_1", - "CFG_CENTER_LH12_9", - "CFG_CENTER_IMUX39_18", - "CFG_CENTER_SE4BEG2_13", - "CFG_CENTER_IMUX36_17", - "CFG_CENTER_IMUX3_6", - "CFG_CENTER_IMUX5_7", - "CFG_CENTER_LH12_14", - "CFG_CENTER_EE4BEG0_12", - "CFG_CENTER_CTRL1_18", - "CFG_CENTER_IMUX12_11", - "CFG_CENTER_WR1END0_10", - "CFG_CENTER_LOGIC_OUTS_B14_2", - "CFG_CENTER_BLOCK_OUTS_B0_11", - "CFG_CENTER_IMUX42_13", - "CFG_CENTER_FAN1_14", - "CFG_CENTER_NE2A3_4", - "CFG_CENTER_FAN3_2", - "CFG_CENTER_FAN1_9", - "CFG_CENTER_CLK1_3", - "CFG_CENTER_EE2A1_1", - "CFG_CENTER_NE2A2_2", - "CFG_CENTER_IMUX30_14", - "CFG_CENTER_NW4A3_8", - "CFG_CENTER_LH10_11", - "CFG_CENTER_LOGIC_OUTS_B5_2", - "CFG_CENTER_SW4END3_8", - "CFG_CENTER_LOGIC_OUTS_B1_19", - "CFG_CENTER_LOGIC_OUTS_B17_17", - "CFG_CENTER_NW4A0_12", - "CFG_CENTER_LOGIC_OUTS_B11_8", - "CFG_CENTER_IMUX19_3", - "CFG_CENTER_IMUX12_17", - "CFG_CENTER_IMUX36_13", - "CFG_CENTER_NE4BEG3_10", - "CFG_CENTER_IMUX11_7", - "CFG_CENTER_LOGIC_OUTS_B6_17", - "CFG_CENTER_IMUX8_13", - "CFG_CENTER_FAN4_16", - "CFG_CENTER_IMUX17_8", - "CFG_CENTER_IMUX34_16", - "CFG_CENTER_LOGIC_OUTS_B9_11", - "CFG_CENTER_LOGIC_OUTS_B4_10", - "CFG_CENTER_BYP2_10", - "CFG_CENTER_SE2A3_14", - "CFG_CENTER_FAN4_8", - "CFG_CENTER_LOGIC_OUTS_B4_16", - "CFG_CENTER_WW4B2_17", - "CFG_CENTER_WW2A0_14", - "CFG_CENTER_IMUX17_10", - "CFG_CENTER_IMUX27_14", - "CFG_CENTER_LH9_10", - "CFG_CENTER_EE2A0_18", - "CFG_CENTER_IMUX38_7", - "CFG_CENTER_NE4C2_8", - "CFG_CENTER_SE2A1_16", - "CFG_CENTER_IMUX8_8", - "CFG_CENTER_IMUX12_0", - "CFG_CENTER_IMUX3_4", - "CFG_CENTER_EE2BEG1_18", - "CFG_CENTER_WR1END3_7", - "CFG_CENTER_LOGIC_OUTS_B6_2", - "CFG_CENTER_WW4A0_18", - "CFG_CENTER_LOGIC_OUTS_B19_4", - "CFG_CENTER_NE4C3_17", - "CFG_CENTER_SE2A2_4", - "CFG_CENTER_LH10_15", - "CFG_CENTER_WW4B2_9", - "CFG_CENTER_LOGIC_OUTS_B3_9", - "CFG_CENTER_SW4A3_16", - "CFG_CENTER_NW4A0_15", - "CFG_CENTER_EE2A2_15", - "CFG_CENTER_IMUX26_5", - "CFG_CENTER_WW4A0_15", - "CFG_CENTER_LOGIC_OUTS_B19_13", - "CFG_CENTER_IMUX25_9", - "CFG_CENTER_LOGIC_OUTS_B6_16", - "CFG_CENTER_EE4C0_0", - "CFG_CENTER_LOGIC_OUTS_B19_5", - "CFG_CENTER_IMUX15_6", - "CFG_CENTER_BYP4_13", - "CFG_CENTER_NW4A2_4", - "CFG_CENTER_WL1END1_3", - "CFG_CENTER_LOGIC_OUTS_B13_13", - "CFG_CENTER_IMUX42_19", - "CFG_CENTER_LOGIC_OUTS_B3_11", - "CFG_CENTER_EE4B2_9", - "CFG_CENTER_CLK0_4", - "CFG_CENTER_EE4BEG1_10", - "CFG_CENTER_ER1BEG2_12", - "CFG_CENTER_LH9_12", - "CFG_CENTER_SW4A1_10", - "CFG_CENTER_LOGIC_OUTS_B15_14", - "CFG_CENTER_IMUX10_14", - "CFG_CENTER_EE4BEG3_0", - "CFG_CENTER_CTRL1_14", - "CFG_CENTER_EE4A0_15", - "CFG_CENTER_EE4B2_7", - "CFG_CENTER_IMUX36_3", - "CFG_CENTER_LOGIC_OUTS_B3_15", - "CFG_CENTER_WW4B3_15", - "CFG_CENTER_LOGIC_OUTS_B5_0", - "CFG_CENTER_IMUX46_6", - "CFG_CENTER_LOGIC_OUTS_B20_15", - "CFG_CENTER_WW4A2_16", - "CFG_CENTER_EE4B2_19", - "CFG_CENTER_LOGIC_OUTS_B9_14", - "CFG_CENTER_IMUX46_16", - "CFG_CENTER_SW4A2_18", - "CFG_CENTER_SW4A3_3", - "CFG_CENTER_LH5_12", - "CFG_CENTER_NE4BEG3_19", - "CFG_CENTER_EE4B1_13", - "CFG_CENTER_NE2A1_13", - "CFG_CENTER_WW4C2_7", - "CFG_CENTER_BYP2_14", - "CFG_CENTER_LH10_4", - "CFG_CENTER_LOGIC_OUTS_B17_18", - "CFG_CENTER_NW2A0_12", - "CFG_CENTER_WW2A1_3", - "CFG_CENTER_IMUX34_1", - "CFG_CENTER_LOGIC_OUTS_B18_9", - "CFG_CENTER_NE4BEG1_15", - "CFG_CENTER_SW4END2_16", - "CFG_CENTER_IMUX8_17", - "CFG_CENTER_LH2_9", - "CFG_CENTER_WW4C1_0", - "CFG_CENTER_NW4A0_6", - "CFG_CENTER_IMUX27_16", - "CFG_CENTER_LOGIC_OUTS_B3_16", - "CFG_CENTER_LOGIC_OUTS_B3_3", - "CFG_CENTER_LH11_17", - "CFG_CENTER_NE2A3_19", - "CFG_CENTER_NW4END1_7", - "CFG_CENTER_IMUX18_10", - "CFG_CENTER_IMUX30_10", - "CFG_CENTER_CTRL0_11", - "CFG_CENTER_BLOCK_OUTS_B0_8", - "CFG_CENTER_NW4END3_7", - "CFG_CENTER_SW4A0_13", - "CFG_CENTER_NW4END3_2", - "CFG_CENTER_WW2END0_13", - "CFG_CENTER_EE2A3_1", - "CFG_CENTER_WW4END1_10", - "CFG_CENTER_SE4BEG1_15", - "CFG_CENTER_CLK0_7", - "CFG_CENTER_LOGIC_OUTS_B23_19", - "CFG_CENTER_IMUX32_15", - "CFG_CENTER_SW4A0_1", - "CFG_CENTER_IMUX0_19", - "CFG_CENTER_LOGIC_OUTS_B20_0", - "CFG_CENTER_SW2A0_4", - "CFG_CENTER_IMUX2_13", - "CFG_CENTER_BYP5_18", - "CFG_CENTER_WW4B1_16", - "CFG_CENTER_IMUX44_7", - "CFG_CENTER_FAN7_14", - "CFG_CENTER_LOGIC_OUTS_B7_11", - "CFG_CENTER_WR1END3_8", - "CFG_CENTER_BYP7_2", - "CFG_CENTER_EE4C2_12", - "CFG_CENTER_NW4A1_15", - "CFG_CENTER_NE4C1_13", - "CFG_CENTER_EL1BEG0_18", - "CFG_CENTER_WR1END0_9", - "CFG_CENTER_IMUX4_10", - "CFG_CENTER_SE4BEG0_5", - "CFG_CENTER_NE4BEG2_4", - "CFG_CENTER_IMUX33_18", - "CFG_CENTER_ER1BEG0_11", - "CFG_CENTER_ER1BEG0_1", - "CFG_CENTER_EE4BEG1_15", - "CFG_CENTER_LH12_6", - "CFG_CENTER_LOGIC_OUTS_B4_14", - "CFG_CENTER_NE4C0_2", - "CFG_CENTER_LOGIC_OUTS_B9_10", - "CFG_CENTER_NE4BEG0_19", - "CFG_CENTER_IMUX32_1", - "CFG_CENTER_LH5_17", - "CFG_CENTER_IMUX41_12", - "CFG_CENTER_NE2A1_17", - "CFG_CENTER_SE4BEG0_10", - "CFG_CENTER_SW2A1_8", - "CFG_CENTER_NW4END2_6", - "CFG_CENTER_WW2A3_3", - "CFG_CENTER_FAN5_18", - "CFG_CENTER_EE2BEG2_15", - "CFG_CENTER_FAN2_13", - "CFG_CENTER_EE2BEG2_18", - "CFG_CENTER_NE2A2_14", - "CFG_CENTER_EE4BEG2_6", - "CFG_CENTER_IMUX22_5", - "CFG_CENTER_SE2A0_11", - "CFG_CENTER_WW4END0_17", - "CFG_CENTER_IMUX7_9", - "CFG_CENTER_LOGIC_OUTS_B22_13", - "CFG_CENTER_EL1BEG0_1", - "CFG_CENTER_IMUX22_3", - "CFG_CENTER_BLOCK_OUTS_B0_19", - "CFG_CENTER_IMUX7_3", - "CFG_CENTER_LOGIC_OUTS_B10_1", - "CFG_CENTER_WW4END3_9", - "CFG_CENTER_LH3_18", - "CFG_CENTER_IMUX44_16", - "CFG_CENTER_SW4END1_17", - "CFG_CENTER_NW2A0_19", - "CFG_CENTER_WL1END2_11", - "CFG_CENTER_NW4END0_18", - "CFG_CENTER_LH7_1", - "CFG_CENTER_BLOCK_OUTS_B3_9", - "CFG_CENTER_EE4A1_3", - "CFG_CENTER_IMUX46_0", - "CFG_CENTER_LOGIC_OUTS_B6_4", - "CFG_CENTER_LH2_5", - "CFG_CENTER_NW2A3_15", - "CFG_CENTER_WW4B0_2", - "CFG_CENTER_CTRL0_0", - "CFG_CENTER_IMUX30_11", - "CFG_CENTER_IMUX18_4", - "CFG_CENTER_NE4C1_9", - "CFG_CENTER_WW2END3_14", - "CFG_CENTER_IMUX41_8", - "CFG_CENTER_FAN5_11", - "CFG_CENTER_IMUX11_13", - "CFG_CENTER_WR1END3_11", - "CFG_CENTER_LH8_10", - "CFG_CENTER_LH5_7", - "CFG_CENTER_LH2_13", - "CFG_CENTER_WW4END2_13", - "CFG_CENTER_EE2BEG0_12", - "CFG_CENTER_EE2A2_16", - "CFG_CENTER_IMUX13_4", - "CFG_CENTER_WL1END0_11", - "CFG_CENTER_NW2A3_2", - "CFG_CENTER_BLOCK_OUTS_B1_2", - "CFG_CENTER_WL1END1_5", - "CFG_CENTER_EE4B1_14", - "CFG_CENTER_EE2BEG0_16", - "CFG_CENTER_BYP7_12", - "CFG_CENTER_EE4C3_9", - "CFG_CENTER_EE4C1_5", - "CFG_CENTER_IMUX17_14", - "CFG_CENTER_WW4B0_5", - "CFG_CENTER_EE4A2_3", - "CFG_CENTER_WW4B0_1", - "CFG_CENTER_BYP6_4", - "CFG_CENTER_SE4C2_2", - "CFG_CENTER_LH2_14", - "CFG_CENTER_IMUX44_12", - "CFG_CENTER_EL1BEG2_14", - "CFG_CENTER_LH12_13", - "CFG_CENTER_EE4BEG2_13", - "CFG_CENTER_EE2A3_2", - "CFG_CENTER_NW4END1_9", - "CFG_CENTER_EE4C2_11", - "CFG_CENTER_SW4END1_10", - "CFG_CENTER_WW4B2_11", - "CFG_CENTER_IMUX2_3", - "CFG_CENTER_WW4C3_17", - "CFG_CENTER_EE4BEG0_7", - "CFG_CENTER_IMUX16_5", - "CFG_CENTER_LOGIC_OUTS_B1_17", - "CFG_CENTER_FAN3_1", - "CFG_CENTER_FAN6_1", - "CFG_CENTER_NE4BEG2_15", - "CFG_CENTER_WW4END0_19", - "CFG_CENTER_SE2A2_9", - "CFG_CENTER_EE4B3_12", - "CFG_CENTER_FAN2_19", - "CFG_CENTER_IMUX9_9", - "CFG_CENTER_IMUX15_13", - "CFG_CENTER_IMUX46_13", - "CFG_CENTER_IMUX28_11", - "CFG_CENTER_NE2A2_16", - "CFG_CENTER_LOGIC_OUTS_B7_5", - "CFG_CENTER_NW4END2_7", - "CFG_CENTER_LOGIC_OUTS_B10_14", - "CFG_CENTER_IMUX37_13", - "CFG_CENTER_WW4A2_5", - "CFG_CENTER_IMUX29_13", - "CFG_CENTER_IMUX16_4", - "CFG_CENTER_SE2A2_0", - "CFG_CENTER_LOGIC_OUTS_B16_0", - "CFG_CENTER_WL1END3_1", - "CFG_CENTER_SW2A3_1", - "CFG_CENTER_SW4A2_19", - "CFG_CENTER_IMUX4_5", - "CFG_CENTER_WR1END0_4", - "CFG_CENTER_SW2A3_12", - "CFG_CENTER_LH4_14", - "CFG_CENTER_ER1BEG3_0", - "CFG_CENTER_IMUX36_11", - "CFG_CENTER_NW4A2_16", - "CFG_CENTER_ER1BEG3_15", - "CFG_CENTER_IMUX32_19", - "CFG_CENTER_WW4C3_0", - "CFG_CENTER_IMUX9_6", - "CFG_CENTER_SW2A2_4", - "CFG_CENTER_NE2A2_0", - "CFG_CENTER_WW4C1_1", - "CFG_CENTER_IMUX16_18", - "CFG_CENTER_EE2A0_4", - "CFG_CENTER_BYP4_14", - "CFG_CENTER_NW2A0_8", - "CFG_CENTER_LH4_12", - "CFG_CENTER_IMUX33_10", - "CFG_CENTER_LOGIC_OUTS_B23_2", - "CFG_CENTER_NW4END1_12", - "CFG_CENTER_IMUX10_11", - "CFG_CENTER_NE4C3_3", - "CFG_CENTER_EE4C0_16", - "CFG_CENTER_FAN4_15", - "CFG_CENTER_ER1BEG3_17", - "CFG_CENTER_WL1END3_18", - "CFG_CENTER_CTRL0_5", - "CFG_CENTER_SE4BEG2_15", - "CFG_CENTER_WW2END0_2", - "CFG_CENTER_EE4B0_17", - "CFG_CENTER_SE4BEG1_1", - "CFG_CENTER_FAN7_3", - "CFG_CENTER_LOGIC_OUTS_B14_15", - "CFG_CENTER_IMUX44_5", - "CFG_CENTER_IMUX24_16", - "CFG_CENTER_WW4B1_18", - "CFG_CENTER_LOGIC_OUTS_B11_6", - "CFG_CENTER_EE2A1_13", - "CFG_CENTER_IMUX2_5", - "CFG_CENTER_SE2A0_18", - "CFG_CENTER_EE4A3_13", - "CFG_CENTER_IMUX8_14", - "CFG_CENTER_IMUX34_17", - "CFG_CENTER_CTRL1_8", - "CFG_CENTER_IMUX45_1", - "CFG_CENTER_IMUX10_1", - "CFG_CENTER_WW2END2_8", - "CFG_CENTER_NW4END0_7", - "CFG_CENTER_FAN0_0", - "CFG_CENTER_LOGIC_OUTS_B14_16", - "CFG_CENTER_IMUX19_7", - "CFG_CENTER_WW2A2_6", - "CFG_CENTER_WW4A3_17", - "CFG_CENTER_BOT_USR_ACCESS_DATA5", - "CFG_CENTER_LOGIC_OUTS_B2_8", - "CFG_CENTER_BYP5_0", - "CFG_CENTER_IMUX28_10", - "CFG_CENTER_EE4B1_10", - "CFG_CENTER_IMUX37_11", - "CFG_CENTER_NW4END1_14", - "CFG_CENTER_LOGIC_OUTS_B11_11", - "CFG_CENTER_LH3_11", - "CFG_CENTER_IMUX31_19", - "CFG_CENTER_NW4A1_11", - "CFG_CENTER_IMUX20_1", - "CFG_CENTER_WW4A1_9", - "CFG_CENTER_EE2BEG2_4", - "CFG_CENTER_LH4_19", - "CFG_CENTER_WW2A3_1", - "CFG_CENTER_IMUX10_9", - "CFG_CENTER_EL1BEG3_12", - "CFG_CENTER_WW2END0_14", - "CFG_CENTER_WW4A2_15", - "CFG_CENTER_LOGIC_OUTS_B0_15", - "CFG_CENTER_WL1END1_9", - "CFG_CENTER_LOGIC_OUTS_B20_10", - "CFG_CENTER_NE4BEG0_16", - "CFG_CENTER_SE4C2_6", - "CFG_CENTER_LH1_6", - "CFG_CENTER_EE4A0_19", - "CFG_CENTER_LH2_2", - "CFG_CENTER_NW4A3_15", - "CFG_CENTER_IMUX37_5", - "CFG_CENTER_NE4C2_14", - "CFG_CENTER_IMUX28_12", - "CFG_CENTER_LOGIC_OUTS_B1_1", - "CFG_CENTER_IMUX41_15", - "CFG_CENTER_IMUX46_19", - "CFG_CENTER_WW4A2_6", - "CFG_CENTER_SE4BEG1_8", - "CFG_CENTER_LOGIC_OUTS_B8_8", - "CFG_CENTER_SE2A2_14", - "CFG_CENTER_WW4C0_13", - "CFG_CENTER_IMUX31_12", - "CFG_CENTER_LOGIC_OUTS_B23_8", - "CFG_CENTER_LOGIC_OUTS_B17_6", - "CFG_CENTER_FAN1_17", - "CFG_CENTER_FAN2_6", - "CFG_CENTER_WW2END1_3", - "CFG_CENTER_IMUX20_18", - "CFG_CENTER_FAN4_0", - "CFG_CENTER_SW2A2_7", - "CFG_CENTER_IMUX2_10", - "CFG_CENTER_IMUX15_5", - "CFG_CENTER_EE4A3_2", - "CFG_CENTER_SE4BEG3_5", - "CFG_CENTER_SE4C3_10", - "CFG_CENTER_SE4C3_2", - "CFG_CENTER_LH2_6", - "CFG_CENTER_BLOCK_OUTS_B2_15", - "CFG_CENTER_BYP4_11", - "CFG_CENTER_LOGIC_OUTS_B3_14", - "CFG_CENTER_SE2A3_2", - "CFG_CENTER_IMUX11_4", - "CFG_CENTER_WW2A3_10", - "CFG_CENTER_IMUX7_16", - "CFG_CENTER_NW4END1_17", - "CFG_CENTER_IMUX18_8", - "CFG_CENTER_EL1BEG3_16", - "CFG_CENTER_IMUX25_6", - "CFG_CENTER_LOGIC_OUTS_B21_4", - "CFG_CENTER_EE2BEG3_19", - "CFG_CENTER_NE4BEG3_4", - "CFG_CENTER_EE4B2_14", - "CFG_CENTER_WW2A1_12", - "CFG_CENTER_IMUX25_11", - "CFG_CENTER_WW2A2_3", - "CFG_CENTER_EL1BEG1_17", - "CFG_CENTER_IMUX28_15", - "CFG_CENTER_CLK1_13", - "CFG_CENTER_SW4END2_17", - "CFG_CENTER_WW4C3_15", - "CFG_CENTER_BYP6_16", - "CFG_CENTER_WW4END2_17", - "CFG_CENTER_WW4A1_7", - "CFG_CENTER_WW2END1_17", - "CFG_CENTER_LOGIC_OUTS_B10_5", - "CFG_CENTER_WL1END1_1", - "CFG_CENTER_IMUX41_16", - "CFG_CENTER_IMUX12_6", - "CFG_CENTER_IMUX21_13", - "CFG_CENTER_FAN2_10", - "CFG_CENTER_LOGIC_OUTS_B8_16", - "CFG_CENTER_WW4B3_3", - "CFG_CENTER_WW2A1_0", - "CFG_CENTER_IMUX22_19", - "CFG_CENTER_CLK1_12", - "CFG_CENTER_LOGIC_OUTS_B21_0", - "CFG_CENTER_LOGIC_OUTS_B4_8", - "CFG_CENTER_SE4C0_15", - "CFG_CENTER_EE4B2_4", - "CFG_CENTER_LH4_17", - "CFG_CENTER_SE4BEG3_12", - "CFG_CENTER_LOGIC_OUTS_B16_18", - "CFG_CENTER_IMUX35_6", - "CFG_CENTER_IMUX8_19", - "CFG_CENTER_SW4A0_14", - "CFG_CENTER_WR1END1_16", - "CFG_CENTER_IMUX38_3", - "CFG_CENTER_EL1BEG0_12", - "CFG_CENTER_NW2A2_0", - "CFG_CENTER_WL1END3_7", - "CFG_CENTER_LH11_19", - "CFG_CENTER_EE4B3_4", - "CFG_CENTER_LOGIC_OUTS_B14_4", - "CFG_CENTER_LOGIC_OUTS_B6_1", - "CFG_CENTER_IMUX19_11", - "CFG_CENTER_WW4B3_0", - "CFG_CENTER_LOGIC_OUTS_B15_2", - "CFG_CENTER_LOGIC_OUTS_B15_8", - "CFG_CENTER_SW4END2_9", - "CFG_CENTER_SW2A2_12", - "CFG_CENTER_IMUX44_6", - "CFG_CENTER_NW4END0_11", - "CFG_CENTER_IMUX29_18", - "CFG_CENTER_NE4BEG2_19", - "CFG_CENTER_SW4END0_1", - "CFG_CENTER_CTRL0_3", - "CFG_CENTER_IMUX11_1", - "CFG_CENTER_NW2A1_7", - "CFG_CENTER_SW4END2_3", - "CFG_CENTER_IMUX43_10", - "CFG_CENTER_LOGIC_OUTS_B21_12", - "CFG_CENTER_CLK0_17", - "CFG_CENTER_SE2A0_0", - "CFG_CENTER_CTRL0_4", - "CFG_CENTER_NE2A0_1", - "CFG_CENTER_IMUX45_3", - "CFG_CENTER_LH11_0", - "CFG_CENTER_NE4C0_18", - "CFG_CENTER_LOGIC_OUTS_B16_11", - "CFG_CENTER_FAN0_3", - "CFG_CENTER_IMUX43_2", - "CFG_CENTER_FAN7_4", - "CFG_CENTER_LOGIC_OUTS_B1_13", - "CFG_CENTER_WR1END1_4", - "CFG_CENTER_ER1BEG2_4", - "CFG_CENTER_FAN6_2", - "CFG_CENTER_LH1_13", - "CFG_CENTER_LOGIC_OUTS_B20_13", - "CFG_CENTER_LOGIC_OUTS_B11_14", - "CFG_CENTER_LOGIC_OUTS_B4_0", - "CFG_CENTER_EL1BEG2_3", - "CFG_CENTER_NE4C3_5", - "CFG_CENTER_IMUX23_12", - "CFG_CENTER_EE2BEG1_15", - "CFG_CENTER_SE4BEG2_7", - "CFG_CENTER_EE2A1_12", - "CFG_CENTER_IMUX4_19", - "CFG_CENTER_WW4C0_8", - "CFG_CENTER_NE2A2_6", - "CFG_CENTER_NE4BEG1_12", - "CFG_CENTER_SE4C1_17", - "CFG_CENTER_IMUX40_7", - "CFG_CENTER_WW4A3_7", - "CFG_CENTER_IMUX39_1", - "CFG_CENTER_SW2A3_9", - "CFG_CENTER_NW4END2_15", - "CFG_CENTER_WW4B0_0", - "CFG_CENTER_SE4BEG1_19", - "CFG_CENTER_EL1BEG1_11", - "CFG_CENTER_NW2A2_19", - "CFG_CENTER_BYP6_6", - "CFG_CENTER_IMUX33_3", - "CFG_CENTER_WL1END2_5", - "CFG_CENTER_NE4C2_4", - "CFG_CENTER_BYP3_14", - "CFG_CENTER_NW2A1_19", - "CFG_CENTER_LH11_16", - "CFG_CENTER_LOGIC_OUTS_B21_10", - "CFG_CENTER_NE4BEG1_5", - "CFG_CENTER_LOGIC_OUTS_B2_11", - "CFG_CENTER_WW4A3_16", - "CFG_CENTER_WW2A2_13", - "CFG_CENTER_WW4B1_17", - "CFG_CENTER_NE4C1_7", - "CFG_CENTER_EE4C1_10", - "CFG_CENTER_IMUX25_15", - "CFG_CENTER_LOGIC_OUTS_B4_6", - "CFG_CENTER_EE4C3_11", - "CFG_CENTER_IMUX8_18", - "CFG_CENTER_LH8_11", - "CFG_CENTER_LOGIC_OUTS_B6_8", - "CFG_CENTER_WW4C3_13", - "CFG_CENTER_SW2A2_3", - "CFG_CENTER_SW4A0_12", - "CFG_CENTER_EE4C3_13", - "CFG_CENTER_BYP6_11", - "CFG_CENTER_EE4B1_7", - "CFG_CENTER_IMUX19_17", - "CFG_CENTER_LOGIC_OUTS_B8_19", - "CFG_CENTER_EE4A1_13", - "CFG_CENTER_LH6_9", - "CFG_CENTER_BYP7_15", - "CFG_CENTER_IMUX16_11", - "CFG_CENTER_LH7_10", - "CFG_CENTER_ER1BEG3_5", - "CFG_CENTER_WR1END2_0", - "CFG_CENTER_NE4BEG1_6", - "CFG_CENTER_LOGIC_OUTS_B4_9", - "CFG_CENTER_IMUX26_6", - "CFG_CENTER_SW2A3_19", - "CFG_CENTER_IMUX27_3", - "CFG_CENTER_LOGIC_OUTS_B4_11", - "CFG_CENTER_EL1BEG3_2", - "CFG_CENTER_FAN5_0", - "CFG_CENTER_ER1BEG2_9", - "CFG_CENTER_NE4C1_5", - "CFG_CENTER_FAN1_11", - "CFG_CENTER_IMUX6_8", - "CFG_CENTER_NE4C0_19", - "CFG_CENTER_EE4A2_14", - "CFG_CENTER_NE4C3_15", - "CFG_CENTER_EL1BEG0_0", - "CFG_CENTER_SE4BEG3_15", - "CFG_CENTER_IMUX21_5", - "CFG_CENTER_WW4END0_12", - "CFG_CENTER_LOGIC_OUTS_B19_9", - "CFG_CENTER_LH12_1", - "CFG_CENTER_SW2A1_3", - "CFG_CENTER_WW4END0_10", - "CFG_CENTER_IMUX9_4", - "CFG_CENTER_ER1BEG2_13", - "CFG_CENTER_LOGIC_OUTS_B8_0", - "CFG_CENTER_LOGIC_OUTS_B2_17", - "CFG_CENTER_WW4C3_19", - "CFG_CENTER_EE4BEG0_18", - "CFG_CENTER_FAN3_8", - "CFG_CENTER_EE2BEG2_1", - "CFG_CENTER_WW2END0_19", - "CFG_CENTER_SE4C0_17", - "CFG_CENTER_BOT_USR_ACCESS_DATA7", - "CFG_CENTER_NW4A0_0", - "CFG_CENTER_SE4BEG0_11", - "CFG_CENTER_IMUX15_12", - "CFG_CENTER_FAN7_19", - "CFG_CENTER_EE2BEG3_11", - "CFG_CENTER_IMUX5_0", - "CFG_CENTER_IMUX13_5", - "CFG_CENTER_EE2BEG0_15", - "CFG_CENTER_IMUX9_8", - "CFG_CENTER_ER1BEG2_15", - "CFG_CENTER_EE2A3_14", - "CFG_CENTER_WW4C3_12", - "CFG_CENTER_LOGIC_OUTS_B21_19", - "CFG_CENTER_BYP1_10", - "CFG_CENTER_EE4B2_2", - "CFG_CENTER_NW4END3_10", - "CFG_CENTER_ER1BEG2_8", - "CFG_CENTER_IMUX40_13", - "CFG_CENTER_NE2A1_19", - "CFG_CENTER_SW4A3_15", - "CFG_CENTER_EL1BEG1_14", - "CFG_CENTER_IMUX18_15", - "CFG_CENTER_WR1END2_12", - "CFG_CENTER_IMUX20_15", - "CFG_CENTER_LH6_18", - "CFG_CENTER_NE4BEG0_12", - "CFG_CENTER_LOGIC_OUTS_B0_8", - "CFG_CENTER_SW4A2_16", - "CFG_CENTER_NE4C0_4", - "CFG_CENTER_NE4C2_10", - "CFG_CENTER_NW2A0_13", - "CFG_CENTER_EE4BEG0_16", - "CFG_CENTER_FAN0_2", - "CFG_CENTER_EE4A3_1", - "CFG_CENTER_NE4BEG1_7", - "CFG_CENTER_EE4BEG0_11", - "CFG_CENTER_IMUX12_15", - "CFG_CENTER_EE2BEG1_9", - "CFG_CENTER_LOGIC_OUTS_B2_6", - "CFG_CENTER_EE2BEG1_6", - "CFG_CENTER_EE4BEG1_1", - "CFG_CENTER_NE2A3_16", - "CFG_CENTER_LH12_17", - "CFG_CENTER_SW2A0_11", - "CFG_CENTER_IMUX11_3", - "CFG_CENTER_IMUX43_14", - "CFG_CENTER_NW2A3_6", - "CFG_CENTER_WW4C3_2", - "CFG_CENTER_SE2A2_11", - "CFG_CENTER_LOGIC_OUTS_B18_16", - "CFG_CENTER_WW2A3_19", - "CFG_CENTER_EE4BEG2_19", - "CFG_CENTER_NW4END3_4", - "CFG_CENTER_NE4BEG1_1", - "CFG_CENTER_EE4BEG3_17", - "CFG_CENTER_NE4BEG0_9", - "CFG_CENTER_LOGIC_OUTS_B15_16", - "CFG_CENTER_LOGIC_OUTS_B4_12", - "CFG_CENTER_WW4B0_11", - "CFG_CENTER_BLOCK_OUTS_B1_4", - "CFG_CENTER_IMUX27_2", - "CFG_CENTER_WW4B0_19", - "CFG_CENTER_LOGIC_OUTS_B7_6", - "CFG_CENTER_SW4END3_16", - "CFG_CENTER_WW4END0_3", - "CFG_CENTER_IMUX3_2", - "CFG_CENTER_LOGIC_OUTS_B4_5", - "CFG_CENTER_ER1BEG1_8", - "CFG_CENTER_NW2A1_15", - "CFG_CENTER_FAN0_16", - "CFG_CENTER_NW4A0_14", - "CFG_CENTER_IMUX43_18", - "CFG_CENTER_SE2A2_10", - "CFG_CENTER_IMUX44_18", - "CFG_CENTER_BYP7_1", - "CFG_CENTER_LOGIC_OUTS_B9_7", - "CFG_CENTER_IMUX8_11", - "CFG_CENTER_BLOCK_OUTS_B1_14", - "CFG_CENTER_LH5_1", - "CFG_CENTER_IMUX26_18", - "CFG_CENTER_SW2A3_16", - "CFG_CENTER_LOGIC_OUTS_B9_8", - "CFG_CENTER_BYP1_9", - "CFG_CENTER_SW2A3_3", - "CFG_CENTER_CTRL1_5", - "CFG_CENTER_LOGIC_OUTS_B5_9", - "CFG_CENTER_BLOCK_OUTS_B1_16", - "CFG_CENTER_LOGIC_OUTS_B13_14", - "CFG_CENTER_SE4C1_8", - "CFG_CENTER_LOGIC_OUTS_B16_5", - "CFG_CENTER_IMUX3_19", - "CFG_CENTER_IMUX25_5", - "CFG_CENTER_IMUX24_1", - "CFG_CENTER_IMUX25_1", - "CFG_CENTER_ER1BEG1_6", - "CFG_CENTER_IMUX0_18", - "CFG_CENTER_SE4C3_6", - "CFG_CENTER_WW4END0_9", - "CFG_CENTER_WW2END3_18", - "CFG_CENTER_LOGIC_OUTS_B20_11", - "CFG_CENTER_IMUX1_3", - "CFG_CENTER_EE2BEG0_6", - "CFG_CENTER_LOGIC_OUTS_B3_5", - "CFG_CENTER_SE2A0_3", - "CFG_CENTER_LOGIC_OUTS_B22_19", - "CFG_CENTER_NE4BEG1_3", - "CFG_CENTER_SW4END1_15", - "CFG_CENTER_WW2END0_5", - "CFG_CENTER_SW4A0_0", - "CFG_CENTER_NE2A0_12", - "CFG_CENTER_NW2A0_5", - "CFG_CENTER_IMUX13_15", - "CFG_CENTER_IMUX27_4", - "CFG_CENTER_LOGIC_OUTS_B2_2", - "CFG_CENTER_IMUX20_13", - "CFG_CENTER_NW2A2_5", - "CFG_CENTER_WW4A1_5", - "CFG_CENTER_BLOCK_OUTS_B2_7", - "CFG_CENTER_IMUX1_15", - "CFG_CENTER_SE2A3_10", - "CFG_CENTER_EE4B0_15", - "CFG_CENTER_LOGIC_OUTS_B8_17", - "CFG_CENTER_IMUX36_15", - "CFG_CENTER_IMUX40_0", - "CFG_CENTER_IMUX12_1", - "CFG_CENTER_LOGIC_OUTS_B10_17", - "CFG_CENTER_WW4END2_19", - "CFG_CENTER_WW4B0_8", - "CFG_CENTER_SW4END1_13", - "CFG_CENTER_LOGIC_OUTS_B10_4", - "CFG_CENTER_WL1END2_6", - "CFG_CENTER_LOGIC_OUTS_B2_3", - "CFG_CENTER_IMUX10_3", - "CFG_CENTER_FAN4_18", - "CFG_CENTER_NW2A3_5", - "CFG_CENTER_IMUX25_19", - "CFG_CENTER_SE2A3_1", - "CFG_CENTER_WW4C2_19", - "CFG_CENTER_ER1BEG0_15", - "CFG_CENTER_IMUX24_17", - "CFG_CENTER_CLK0_10", - "CFG_CENTER_NE4C3_18", - "CFG_CENTER_EL1BEG0_2", - "CFG_CENTER_NW4A3_9", - "CFG_CENTER_IMUX28_1", - "CFG_CENTER_LOGIC_OUTS_B10_11", - "CFG_CENTER_WW4C1_13", - "CFG_CENTER_LOGIC_OUTS_B21_5", - "CFG_CENTER_NE2A3_18", - "CFG_CENTER_EE2BEG3_6", - "CFG_CENTER_EE4C1_15", - "CFG_CENTER_SE4BEG2_10", - "CFG_CENTER_LH4_6", - "CFG_CENTER_EE4C3_1", - "CFG_CENTER_LOGIC_OUTS_B5_18", - "CFG_CENTER_NW4END1_18", - "CFG_CENTER_WW4C0_9", - "CFG_CENTER_IMUX2_16", - "CFG_CENTER_LOGIC_OUTS_B22_7", - "CFG_CENTER_NW4A1_4", - "CFG_CENTER_IMUX47_2", - "CFG_CENTER_IMUX22_17", - "CFG_CENTER_SW4END2_0", - "CFG_CENTER_LOGIC_OUTS_B12_2", - "CFG_CENTER_LH5_13", - "CFG_CENTER_WR1END2_11", - "CFG_CENTER_IMUX14_14", - "CFG_CENTER_SW2A2_1", - "CFG_CENTER_BYP7_5", - "CFG_CENTER_NW4END3_18", - "CFG_CENTER_LH3_1", - "CFG_CENTER_BYP5_15", - "CFG_CENTER_LH3_12", - "CFG_CENTER_SW4A1_12", - "CFG_CENTER_WW2END0_10", - "CFG_CENTER_LOGIC_OUTS_B15_12", - "CFG_CENTER_WL1END1_10", - "CFG_CENTER_IMUX11_2", - "CFG_CENTER_SW4END3_19", - "CFG_CENTER_BYP5_10", - "CFG_CENTER_IMUX24_18", - "CFG_CENTER_NE4C2_7", - "CFG_CENTER_LH7_11", - "CFG_CENTER_IMUX21_8", - "CFG_CENTER_SW4A1_6", - "CFG_CENTER_IMUX11_19", - "CFG_CENTER_IMUX46_17", - "CFG_CENTER_SW2A0_14", - "CFG_CENTER_LH12_7", - "CFG_CENTER_ER1BEG1_7", - "CFG_CENTER_IMUX0_16", - "CFG_CENTER_SE2A1_4", - "CFG_CENTER_WW4B0_14", - "CFG_CENTER_WL1END3_14", - "CFG_CENTER_LOGIC_OUTS_B23_17", - "CFG_CENTER_EE4C2_1", - "CFG_CENTER_IMUX32_5", - "CFG_CENTER_EL1BEG1_13", - "CFG_CENTER_LH11_6", - "CFG_CENTER_EE4BEG3_4", - "CFG_CENTER_SW2A0_17", - "CFG_CENTER_LOGIC_OUTS_B8_18", - "CFG_CENTER_NE2A1_16", - "CFG_CENTER_SW2A3_14", - "CFG_CENTER_SE4C2_15", - "CFG_CENTER_SW4A1_15", - "CFG_CENTER_FAN2_17", - "CFG_CENTER_NE2A0_0", - "CFG_CENTER_IMUX18_9", - "CFG_CENTER_LOGIC_OUTS_B0_12", - "CFG_CENTER_IMUX14_2", - "CFG_CENTER_EE2BEG1_10", - "CFG_CENTER_SE2A3_18", - "CFG_CENTER_BYP7_18", - "CFG_CENTER_SE4BEG2_8", - "CFG_CENTER_SE4BEG0_14", - "CFG_CENTER_IMUX43_6", - "CFG_CENTER_WW4END3_2", - "CFG_CENTER_EE4BEG1_17", - "CFG_CENTER_IMUX39_8", - "CFG_CENTER_NE4BEG1_8", - "CFG_CENTER_SE4C0_18", - "CFG_CENTER_WW2A1_16", - "CFG_CENTER_EE4B2_11", - "CFG_CENTER_IMUX30_0", - "CFG_CENTER_LOGIC_OUTS_B8_3", - "CFG_CENTER_IMUX33_6", - "CFG_CENTER_SE4BEG2_4", - "CFG_CENTER_WW4C0_3", - "CFG_CENTER_NW4A1_12", - "CFG_CENTER_WR1END0_8", - "CFG_CENTER_SW2A0_8", - "CFG_CENTER_IMUX30_15", - "CFG_CENTER_IMUX46_11", - "CFG_CENTER_WR1END3_4", - "CFG_CENTER_WW2END0_12", - "CFG_CENTER_BOT_USR_ACCESS_DATA3", - "CFG_CENTER_IMUX0_14", - "CFG_CENTER_EE4B0_11", - "CFG_CENTER_WW4END0_16", - "CFG_CENTER_FAN6_6", - "CFG_CENTER_NW4A3_3", - "CFG_CENTER_EL1BEG3_9", - "CFG_CENTER_WW4B1_15", - "CFG_CENTER_EL1BEG0_16", - "CFG_CENTER_BLOCK_OUTS_B0_7", - "CFG_CENTER_WW2A3_6", - "CFG_CENTER_IMUX44_1", - "CFG_CENTER_SE2A2_18", - "CFG_CENTER_LH7_15", - "CFG_CENTER_IMUX35_7", - "CFG_CENTER_IMUX19_10", - "CFG_CENTER_NW4A1_7", - "CFG_CENTER_NE2A2_18", - "CFG_CENTER_SE2A3_16", - "CFG_CENTER_EE2A2_0", - "CFG_CENTER_EE4B0_10", - "CFG_CENTER_IMUX7_2", - "CFG_CENTER_IMUX12_2", - "CFG_CENTER_IMUX41_1", - "CFG_CENTER_WW2END1_9", - "CFG_CENTER_ER1BEG1_19", - "CFG_CENTER_EE4C3_18", - "CFG_CENTER_IMUX29_0", - "CFG_CENTER_WW2END2_17", - "CFG_CENTER_NE2A0_8", - "CFG_CENTER_EE4C3_10", - "CFG_CENTER_IMUX33_11", - "CFG_CENTER_CLK0_2", - "CFG_CENTER_LOGIC_OUTS_B15_1", - "CFG_CENTER_EE4BEG2_17", - "CFG_CENTER_WW4END1_2", - "CFG_CENTER_FAN4_3", - "CFG_CENTER_WW4END0_15", - "CFG_CENTER_EE4BEG2_8", - "CFG_CENTER_SW2A3_2", - "CFG_CENTER_IMUX18_12", - "CFG_CENTER_FAN5_14", - "CFG_CENTER_BLOCK_OUTS_B2_16", - "CFG_CENTER_LOGIC_OUTS_B8_13", - "CFG_CENTER_EE2BEG1_1", - "CFG_CENTER_NE4BEG2_3", - "CFG_CENTER_ER1BEG0_13", - "CFG_CENTER_BLOCK_OUTS_B1_3", - "CFG_CENTER_WW4A3_1", - "CFG_CENTER_SW4A2_2", - "CFG_CENTER_IMUX23_8", - "CFG_CENTER_IMUX26_16", - "CFG_CENTER_LOGIC_OUTS_B11_4", - "CFG_CENTER_WW4B2_7", - "CFG_CENTER_EE4A1_10", - "CFG_CENTER_LOGIC_OUTS_B23_5", - "CFG_CENTER_WW4A0_8", - "CFG_CENTER_IMUX13_12", - "CFG_CENTER_WW4END2_5", - "CFG_CENTER_SE2A3_12", - "CFG_CENTER_FAN3_10", - "CFG_CENTER_SW4A1_4", - "CFG_CENTER_IMUX35_11", - "CFG_CENTER_LOGIC_OUTS_B9_9", - "CFG_CENTER_WR1END3_0", - "CFG_CENTER_WR1END1_12", - "CFG_CENTER_BYP6_15", - "CFG_CENTER_IMUX33_2", - "CFG_CENTER_BLOCK_OUTS_B0_1", - "CFG_CENTER_IMUX33_16", - "CFG_CENTER_FAN5_17", - "CFG_CENTER_IMUX44_19", - "CFG_CENTER_SE4C2_0", - "CFG_CENTER_IMUX32_4", - "CFG_CENTER_EE2A1_6", - "CFG_CENTER_SE4BEG0_2", - "CFG_CENTER_IMUX2_2", - "CFG_CENTER_WW4END3_7", - "CFG_CENTER_IMUX0_10", - "CFG_CENTER_LH6_12", - "CFG_CENTER_LOGIC_OUTS_B3_12", - "CFG_CENTER_EE2BEG2_2", - "CFG_CENTER_IMUX14_6", - "CFG_CENTER_EL1BEG2_8", - "CFG_CENTER_IMUX3_8", - "CFG_CENTER_IMUX21_11", - "CFG_CENTER_NW2A2_11", - "CFG_CENTER_EE4C0_7", - "CFG_CENTER_EE4B0_3", - "CFG_CENTER_SW2A1_2", - "CFG_CENTER_NE2A3_3", - "CFG_CENTER_LOGIC_OUTS_B19_3", - "CFG_CENTER_IMUX20_9", - "CFG_CENTER_SE4BEG1_13", - "CFG_CENTER_SW4END3_7", - "CFG_CENTER_SW4END2_1", - "CFG_CENTER_LOGIC_OUTS_B7_7", - "CFG_CENTER_LOGIC_OUTS_B19_17", - "CFG_CENTER_IMUX43_0", - "CFG_CENTER_LH10_3", - "CFG_CENTER_WR1END3_14", - "CFG_CENTER_LOGIC_OUTS_B3_13", - "CFG_CENTER_NW4A2_5", - "CFG_CENTER_IMUX37_18", - "CFG_CENTER_IMUX23_4", - "CFG_CENTER_WW4B0_17", - "CFG_CENTER_IMUX7_7", - "CFG_CENTER_NW2A2_1", - "CFG_CENTER_BLOCK_OUTS_B0_14", - "CFG_CENTER_IMUX3_12", - "CFG_CENTER_EE4B2_5", - "CFG_CENTER_LH12_15", - "CFG_CENTER_BOT_CFG_IO_ACCESS_VGGCOMPOUT", - "CFG_CENTER_WW4C3_11", - "CFG_CENTER_EL1BEG3_19", - "CFG_CENTER_WW2A3_8", - "CFG_CENTER_NE2A0_13", - "CFG_CENTER_SW4A0_8", - "CFG_CENTER_IMUX36_12", - "CFG_CENTER_EE2A3_10", - "CFG_CENTER_EE4A0_1", - "CFG_CENTER_IMUX43_15", - "CFG_CENTER_EL1BEG0_9", - "CFG_CENTER_EE4BEG1_7", - "CFG_CENTER_BYP7_11", - "CFG_CENTER_FAN7_13", - "CFG_CENTER_SE4C0_4", - "CFG_CENTER_LOGIC_OUTS_B9_6", - "CFG_CENTER_EE2A0_9", - "CFG_CENTER_WW4END2_9", - "CFG_CENTER_IMUX29_17", - "CFG_CENTER_NW4END3_1", - "CFG_CENTER_WW2A1_11", - "CFG_CENTER_NW4A2_12", - "CFG_CENTER_LOGIC_OUTS_B14_3", - "CFG_CENTER_WR1END1_10", - "CFG_CENTER_CLK1_17", - "CFG_CENTER_SW4END1_16", - "CFG_CENTER_IMUX1_12", - "CFG_CENTER_NW2A0_16", - "CFG_CENTER_WL1END2_17", - "CFG_CENTER_IMUX37_10", - "CFG_CENTER_LOGIC_OUTS_B21_1", - "CFG_CENTER_ER1BEG0_9", - "CFG_CENTER_NW4A1_2", - "CFG_CENTER_NE4C2_13", - "CFG_CENTER_LH7_12", - "CFG_CENTER_EL1BEG2_12", - "CFG_CENTER_WR1END2_14", - "CFG_CENTER_IMUX20_2", - "CFG_CENTER_WL1END0_1", - "CFG_CENTER_ER1BEG3_19", - "CFG_CENTER_LOGIC_OUTS_B22_17", - "CFG_CENTER_SE2A2_19", - "CFG_CENTER_LH3_2", - "CFG_CENTER_IMUX4_11", - "CFG_CENTER_EE4BEG2_4", - "CFG_CENTER_LOGIC_OUTS_B9_3", - "CFG_CENTER_EE2BEG2_3", - "CFG_CENTER_WR1END2_18", - "CFG_CENTER_LOGIC_OUTS_B22_12", - "CFG_CENTER_SE4C3_0", - "CFG_CENTER_FAN6_0", - "CFG_CENTER_IMUX23_9", - "CFG_CENTER_IMUX34_8", - "CFG_CENTER_WR1END3_17", - "CFG_CENTER_EE4BEG2_14", - "CFG_CENTER_FAN0_11", - "CFG_CENTER_EE2BEG3_8", - "CFG_CENTER_WW4C2_11", - "CFG_CENTER_EE4C0_5", - "CFG_CENTER_SW4END0_19", - "CFG_CENTER_NW2A3_19", - "CFG_CENTER_WR1END3_18", - "CFG_CENTER_NW2A1_5", - "CFG_CENTER_WW4B3_5", - "CFG_CENTER_IMUX4_8", - "CFG_CENTER_ER1BEG3_2", - "CFG_CENTER_WW4END2_18", - "CFG_CENTER_IMUX4_2", - "CFG_CENTER_BYP7_10", - "CFG_CENTER_LOGIC_OUTS_B19_0", - "CFG_CENTER_WR1END1_15", - "CFG_CENTER_LOGIC_OUTS_B17_10", - "CFG_CENTER_IMUX45_7", - "CFG_CENTER_IMUX6_19", - "CFG_CENTER_IMUX45_6", - "CFG_CENTER_NE2A3_1", - "CFG_CENTER_WW4END0_1", - "CFG_CENTER_LH7_5", - "CFG_CENTER_SW2A0_0", - "CFG_CENTER_EE4BEG0_14", - "CFG_CENTER_LOGIC_OUTS_B7_4", - "CFG_CENTER_EE4BEG3_10", - "CFG_CENTER_BYP6_0", - "CFG_CENTER_LOGIC_OUTS_B11_16", - "CFG_CENTER_IMUX42_3", - "CFG_CENTER_WL1END0_19", - "CFG_CENTER_WL1END2_4", - "CFG_CENTER_WL1END1_11", - "CFG_CENTER_WW4B2_2", - "CFG_CENTER_BOT_USR_ACCESS_DATA8", - "CFG_CENTER_BYP5_12", - "CFG_CENTER_EE4A1_6", - "CFG_CENTER_SE2A3_7", - "CFG_CENTER_IMUX1_13", - "CFG_CENTER_EE4B3_18", - "CFG_CENTER_ER1BEG1_3", - "CFG_CENTER_LOGIC_OUTS_B10_6", - "CFG_CENTER_IMUX20_5", - "CFG_CENTER_BYP2_1", - "CFG_CENTER_EE2BEG3_4", - "CFG_CENTER_IMUX38_19", - "CFG_CENTER_EL1BEG3_17", - "CFG_CENTER_NW4END1_10", - "CFG_CENTER_LOGIC_OUTS_B22_8", - "CFG_CENTER_IMUX18_1", - "CFG_CENTER_SW4END3_3", - "CFG_CENTER_IMUX32_9", - "CFG_CENTER_NW4A0_9", - "CFG_CENTER_NE2A1_15", - "CFG_CENTER_WR1END0_15", - "CFG_CENTER_EE2A2_18", - "CFG_CENTER_BYP4_15", - "CFG_CENTER_IMUX18_11", - "CFG_CENTER_WW2A3_16", - "CFG_CENTER_NW2A3_0", - "CFG_CENTER_LH6_0", - "CFG_CENTER_SE4C1_11", - "CFG_CENTER_WW4END2_4", - "CFG_CENTER_NE4BEG2_7", - "CFG_CENTER_BYP0_10", - "CFG_CENTER_LH7_4", - "CFG_CENTER_BYP5_7", - "CFG_CENTER_LOGIC_OUTS_B15_5", - "CFG_CENTER_FAN4_14", - "CFG_CENTER_WW4C0_15", - "CFG_CENTER_IMUX2_11", - "CFG_CENTER_WW4A3_18", - "CFG_CENTER_LOGIC_OUTS_B1_7", - "CFG_CENTER_BYP5_1", - "CFG_CENTER_NE2A2_4", - "CFG_CENTER_IMUX8_15", - "CFG_CENTER_WW2END0_11", - "CFG_CENTER_LOGIC_OUTS_B18_8", - "CFG_CENTER_IMUX34_18", - "CFG_CENTER_WW2A0_5", - "CFG_CENTER_SE4BEG1_3", - "CFG_CENTER_WW4B2_3", - "CFG_CENTER_BYP3_18", - "CFG_CENTER_IMUX38_8", - "CFG_CENTER_BYP1_18", - "CFG_CENTER_IMUX34_7", - "CFG_CENTER_LH4_2", - "CFG_CENTER_BYP4_17", - "CFG_CENTER_BYP7_4", - "CFG_CENTER_EL1BEG2_17", - "CFG_CENTER_LH1_3", - "CFG_CENTER_EE4A3_19", - "CFG_CENTER_WL1END1_17", - "CFG_CENTER_NE4BEG1_17", - "CFG_CENTER_NE4C1_18", - "CFG_CENTER_NE2A1_2", - "CFG_CENTER_IMUX14_4", - "CFG_CENTER_EE4BEG2_12", - "CFG_CENTER_WW2END2_3", - "CFG_CENTER_WW2A2_1", - "CFG_CENTER_EE4B0_6", - "CFG_CENTER_EE4B3_1", - "CFG_CENTER_LOGIC_OUTS_B10_0", - "CFG_CENTER_NW4A2_19", - "CFG_CENTER_IMUX39_5", - "CFG_CENTER_SW4END0_7", - "CFG_CENTER_BYP3_4", - "CFG_CENTER_EE4A1_4", - "CFG_CENTER_LOGIC_OUTS_B16_13", - "CFG_CENTER_LOGIC_OUTS_B18_1", - "CFG_CENTER_EE4C0_9", - "CFG_CENTER_LH3_0", - "CFG_CENTER_LH2_17", - "CFG_CENTER_IMUX17_3", - "CFG_CENTER_EE4BEG2_1", - "CFG_CENTER_NE4C3_10", - "CFG_CENTER_FAN5_7", - "CFG_CENTER_NE4BEG3_1", - "CFG_CENTER_WW2END0_8", - "CFG_CENTER_WW2END1_15", - "CFG_CENTER_WW4A0_1", - "CFG_CENTER_EE2BEG2_16", - "CFG_CENTER_LH9_0", - "CFG_CENTER_LH6_2", - "CFG_CENTER_IMUX34_13", - "CFG_CENTER_WW2END1_8", - "CFG_CENTER_EE2BEG2_8", - "CFG_CENTER_WW4A2_19", - "CFG_CENTER_BYP1_1", - "CFG_CENTER_NW4END1_16", - "CFG_CENTER_LOGIC_OUTS_B8_9", - "CFG_CENTER_BYP3_16", - "CFG_CENTER_EE2A0_2", - "CFG_CENTER_IMUX36_14", - "CFG_CENTER_WL1END2_1", - "CFG_CENTER_EE2A1_4", - "CFG_CENTER_IMUX40_15", - "CFG_CENTER_WW2A3_7", - "CFG_CENTER_EE2A0_12", - "CFG_CENTER_EE4A0_5", - "CFG_CENTER_IMUX39_10", - "CFG_CENTER_LH6_15", - "CFG_CENTER_FAN1_5", - "CFG_CENTER_NE4C2_15", - "CFG_CENTER_LH12_12", - "CFG_CENTER_IMUX9_14", - "CFG_CENTER_LOGIC_OUTS_B5_13", - "CFG_CENTER_LOGIC_OUTS_B13_3", - "CFG_CENTER_IMUX32_12", - "CFG_CENTER_IMUX19_18", - "CFG_CENTER_LH9_11", - "CFG_CENTER_SE2A3_19", - "CFG_CENTER_BYP4_12", - "CFG_CENTER_IMUX38_15", - "CFG_CENTER_WW2A1_4", - "CFG_CENTER_EE4A3_14", - "CFG_CENTER_WW4C2_16", - "CFG_CENTER_IMUX40_18", - "CFG_CENTER_SE4C0_11", - "CFG_CENTER_IMUX9_16", - "CFG_CENTER_WR1END3_5", - "CFG_CENTER_FAN7_6", - "CFG_CENTER_LOGIC_OUTS_B0_6", - "CFG_CENTER_NW4A0_18", - "CFG_CENTER_IMUX3_16", - "CFG_CENTER_SE4BEG3_19", - "CFG_CENTER_EE2A3_7", - "CFG_CENTER_IMUX35_4", - "CFG_CENTER_WW2A3_11", - "CFG_CENTER_WR1END0_14", - "CFG_CENTER_LH6_13", - "CFG_CENTER_EE4C1_16", - "CFG_CENTER_BYP1_15", - "CFG_CENTER_WW2END2_16", - "CFG_CENTER_SE4C2_14", - "CFG_CENTER_IMUX34_12", - "CFG_CENTER_NE4C2_11", - "CFG_CENTER_LH3_7", - "CFG_CENTER_IMUX24_6", - "CFG_CENTER_LOGIC_OUTS_B5_5", - "CFG_CENTER_WW4END2_1", - "CFG_CENTER_WW4B1_1", - "CFG_CENTER_LOGIC_OUTS_B18_7", - "CFG_CENTER_CTRL0_2", - "CFG_CENTER_IMUX39_2", - "CFG_CENTER_NE2A0_4", - "CFG_CENTER_WW4C1_17", - "CFG_CENTER_WW2END1_16", - "CFG_CENTER_LOGIC_OUTS_B10_19", - "CFG_CENTER_EE4C3_4", - "CFG_CENTER_IMUX43_17", - "CFG_CENTER_WR1END1_6", - "CFG_CENTER_EE4B2_1", - "CFG_CENTER_BLOCK_OUTS_B2_1", - "CFG_CENTER_IMUX31_0", - "CFG_CENTER_IMUX41_13", - "CFG_CENTER_LH1_8", - "CFG_CENTER_IMUX37_7", - "CFG_CENTER_LOGIC_OUTS_B1_3", - "CFG_CENTER_SE4C3_9", - "CFG_CENTER_EE2BEG0_18", - "CFG_CENTER_LOGIC_OUTS_B0_2", - "CFG_CENTER_WW2END2_4", - "CFG_CENTER_BLOCK_OUTS_B3_19", - "CFG_CENTER_IMUX42_6", - "CFG_CENTER_IMUX42_10", - "CFG_CENTER_WW4C0_7", - "CFG_CENTER_BLOCK_OUTS_B2_3", - "CFG_CENTER_IMUX33_19", - "CFG_CENTER_LOGIC_OUTS_B2_18", - "CFG_CENTER_NW2A2_7", - "CFG_CENTER_IMUX28_8", - "CFG_CENTER_EE4C2_13", - "CFG_CENTER_SE4BEG1_6", - "CFG_CENTER_IMUX32_17", - "CFG_CENTER_IMUX26_7", - "CFG_CENTER_LOGIC_OUTS_B11_10", - "CFG_CENTER_WW4B0_9", - "CFG_CENTER_EE2BEG1_8", - "CFG_CENTER_EE4A2_2", - "CFG_CENTER_BYP6_9", - "CFG_CENTER_EE2A3_11", - "CFG_CENTER_SE4C3_13", - "CFG_CENTER_NE2A3_8", - "CFG_CENTER_LOGIC_OUTS_B3_0", - "CFG_CENTER_WW2END1_1", - "CFG_CENTER_WW4END1_19", - "CFG_CENTER_IMUX18_18", - "CFG_CENTER_IMUX28_3", - "CFG_CENTER_SE2A3_3", - "CFG_CENTER_WL1END3_8", - "CFG_CENTER_BLOCK_OUTS_B1_9", - "CFG_CENTER_WL1END3_4", - "CFG_CENTER_NE4C1_12", - "CFG_CENTER_WW4END3_17", - "CFG_CENTER_LOGIC_OUTS_B5_6", - "CFG_CENTER_CTRL0_13", - "CFG_CENTER_BYP6_1", - "CFG_CENTER_LOGIC_OUTS_B22_10", - "CFG_CENTER_SW4A1_13", - "CFG_CENTER_WL1END3_5", - "CFG_CENTER_BLOCK_OUTS_B3_7", - "CFG_CENTER_EE4B2_15", - "CFG_CENTER_NW4END0_19", - "CFG_CENTER_EE4BEG2_2", - "CFG_CENTER_WW4A0_19", - "CFG_CENTER_NE2A0_10", - "CFG_CENTER_LH11_10", - "CFG_CENTER_NW4END0_10", - "CFG_CENTER_LOGIC_OUTS_B22_3", - "CFG_CENTER_LOGIC_OUTS_B16_2", - "CFG_CENTER_WL1END0_5", - "CFG_CENTER_SE4C1_9", - "CFG_CENTER_LOGIC_OUTS_B18_19", - "CFG_CENTER_NE4BEG3_15", - "CFG_CENTER_LH7_17", - "CFG_CENTER_LH5_18", - "CFG_CENTER_WL1END0_18", - "CFG_CENTER_LOGIC_OUTS_B0_1", - "CFG_CENTER_NE2A3_13", - "CFG_CENTER_WR1END0_12", - "CFG_CENTER_EE4B0_14", - "CFG_CENTER_NE4BEG2_9", - "CFG_CENTER_LH7_16", - "CFG_CENTER_FAN7_11", - "CFG_CENTER_LH8_14", - "CFG_CENTER_EE2A1_0", - "CFG_CENTER_LH10_6", - "CFG_CENTER_WW4A1_18", - "CFG_CENTER_LOGIC_OUTS_B13_9", - "CFG_CENTER_IMUX10_12", - "CFG_CENTER_LOGIC_OUTS_B14_10", - "CFG_CENTER_WW2A0_19", - "CFG_CENTER_LH5_16", - "CFG_CENTER_LH9_5", - "CFG_CENTER_IMUX38_6", - "CFG_CENTER_NW4END2_17", - "CFG_CENTER_FAN5_1", - "CFG_CENTER_IMUX9_0", - "CFG_CENTER_WW2A1_2", - "CFG_CENTER_WW4B3_18", - "CFG_CENTER_WW2A1_15", - "CFG_CENTER_IMUX30_4", - "CFG_CENTER_NW4END0_8", - "CFG_CENTER_BLOCK_OUTS_B3_16", - "CFG_CENTER_SW4A2_9", - "CFG_CENTER_LOGIC_OUTS_B21_7", - "CFG_CENTER_BYP2_12", - "CFG_CENTER_CTRL0_12", - "CFG_CENTER_IMUX22_18", - "CFG_CENTER_LOGIC_OUTS_B21_13", - "CFG_CENTER_WW4C1_6", - "CFG_CENTER_NW4END1_13", - "CFG_CENTER_IMUX7_0", - "CFG_CENTER_SE4BEG2_6", - "CFG_CENTER_LOGIC_OUTS_B15_17", - "CFG_CENTER_IMUX40_10", - "CFG_CENTER_IMUX6_7", - "CFG_CENTER_IMUX32_2", - "CFG_CENTER_FAN2_16", - "CFG_CENTER_EE2A2_7", - "CFG_CENTER_NE4BEG0_17", - "CFG_CENTER_BLOCK_OUTS_B0_12", - "CFG_CENTER_NW4END2_12", - "CFG_CENTER_ER1BEG3_18", - "CFG_CENTER_IMUX33_4", - "CFG_CENTER_BYP7_6", - "CFG_CENTER_IMUX40_11", - "CFG_CENTER_WW4A2_17", - "CFG_CENTER_WL1END0_6", - "CFG_CENTER_EE4BEG2_0", - "CFG_CENTER_WR1END0_2", - "CFG_CENTER_FAN1_3", - "CFG_CENTER_LH11_14", - "CFG_CENTER_IMUX34_9", - "CFG_CENTER_IMUX15_14", - "CFG_CENTER_WL1END2_7", - "CFG_CENTER_LOGIC_OUTS_B18_0", - "CFG_CENTER_EL1BEG1_10", - "CFG_CENTER_IMUX6_9", - "CFG_CENTER_LOGIC_OUTS_B11_13", - "CFG_CENTER_EE2A0_17", - "CFG_CENTER_IMUX47_14", - "CFG_CENTER_IMUX30_9", - "CFG_CENTER_SW4A3_1", - "CFG_CENTER_EE4A0_3", - "CFG_CENTER_WW2A0_11", - "CFG_CENTER_SW4A2_6", - "CFG_CENTER_BYP3_0", - "CFG_CENTER_LOGIC_OUTS_B0_16", - "CFG_CENTER_SE4C1_10", - "CFG_CENTER_SW2A2_11", - "CFG_CENTER_EE2BEG3_14", - "CFG_CENTER_LOGIC_OUTS_B12_5", - "CFG_CENTER_LOGIC_OUTS_B11_17", - "CFG_CENTER_NE2A1_18", - "CFG_CENTER_LH8_0", - "CFG_CENTER_IMUX22_9", - "CFG_CENTER_IMUX21_19", - "CFG_CENTER_SE4BEG3_7", - "CFG_CENTER_IMUX20_6", - "CFG_CENTER_FAN2_1", - "CFG_CENTER_WW4A2_4", - "CFG_CENTER_SE4BEG2_9", - "CFG_CENTER_LOGIC_OUTS_B23_9", - "CFG_CENTER_WW4END1_11", - "CFG_CENTER_SE4C2_1", - "CFG_CENTER_EE4B3_8", - "CFG_CENTER_LOGIC_OUTS_B9_1", - "CFG_CENTER_IMUX9_10", - "CFG_CENTER_EE4BEG3_14", - "CFG_CENTER_EE4A1_11", - "CFG_CENTER_IMUX11_8", - "CFG_CENTER_BYP0_3", - "CFG_CENTER_BYP3_8", - "CFG_CENTER_NE4BEG0_18", - "CFG_CENTER_IMUX3_1", - "CFG_CENTER_NW4END3_19", - "CFG_CENTER_WW4END2_3", - "CFG_CENTER_SE2A1_19", - "CFG_CENTER_NE2A3_5", - "CFG_CENTER_WW4B3_2", - "CFG_CENTER_SW4END1_8", - "CFG_CENTER_EE4A3_15", - "CFG_CENTER_NW2A2_15", - "CFG_CENTER_LH6_4", - "CFG_CENTER_EE4B1_9", - "CFG_CENTER_IMUX39_12", - "CFG_CENTER_IMUX36_18", - "CFG_CENTER_NE4C1_11", - "CFG_CENTER_EE2A3_12", - "CFG_CENTER_IMUX12_10", - "CFG_CENTER_LOGIC_OUTS_B16_4", - "CFG_CENTER_WL1END1_15", - "CFG_CENTER_LH10_16", - "CFG_CENTER_SE4C0_2", - "CFG_CENTER_WW4A3_3", - "CFG_CENTER_NW4A0_17", - "CFG_CENTER_LH4_16", - "CFG_CENTER_SW2A3_0", - "CFG_CENTER_IMUX5_2", - "CFG_CENTER_EE2A2_8", - "CFG_CENTER_IMUX25_14", - "CFG_CENTER_NE2A2_1", - "CFG_CENTER_EE4A0_2", - "CFG_CENTER_NW4A2_18", - "CFG_CENTER_LH12_2", - "CFG_CENTER_IMUX22_1", - "CFG_CENTER_IMUX39_15", - "CFG_CENTER_WW2END2_2", - "CFG_CENTER_SE2A2_7", - "CFG_CENTER_IMUX47_19", - "CFG_CENTER_EE4B3_5", - "CFG_CENTER_NE4BEG3_16", - "CFG_CENTER_NE4BEG2_5", - "CFG_CENTER_IMUX38_4", - "CFG_CENTER_WW2END2_19", - "CFG_CENTER_IMUX42_1", - "CFG_CENTER_LOGIC_OUTS_B20_18", - "CFG_CENTER_LOGIC_OUTS_B9_13", - "CFG_CENTER_SE4BEG2_11", - "CFG_CENTER_EE4B0_7", - "CFG_CENTER_IMUX15_15", - "CFG_CENTER_IMUX35_9", - "CFG_CENTER_IMUX11_11", - "CFG_CENTER_EE2A2_14", - "CFG_CENTER_BYP5_4", - "CFG_CENTER_WW4B1_2", - "CFG_CENTER_WW4C3_18", - "CFG_CENTER_CLK1_5", - "CFG_CENTER_IMUX35_15", - "CFG_CENTER_IMUX24_7", - "CFG_CENTER_LOGIC_OUTS_B17_7", - "CFG_CENTER_IMUX17_18", - "CFG_CENTER_WW4A1_19", - "CFG_CENTER_BOT_USR_ACCESS_DATA2", - "CFG_CENTER_EE2BEG0_9", - "CFG_CENTER_LOGIC_OUTS_B9_16", - "CFG_CENTER_IMUX45_19", - "CFG_CENTER_WR1END1_11", - "CFG_CENTER_WW4A1_15", - "CFG_CENTER_EE2BEG1_16", - "CFG_CENTER_NW4END0_6", - "CFG_CENTER_LOGIC_OUTS_B17_11", - "CFG_CENTER_NE4C3_8", - "CFG_CENTER_NE4BEG0_15", - "CFG_CENTER_ER1BEG3_16", - "CFG_CENTER_WW4A2_3", - "CFG_CENTER_IMUX15_4", - "CFG_CENTER_IMUX16_10", - "CFG_CENTER_WW4B3_14", - "CFG_CENTER_LOGIC_OUTS_B8_15", - "CFG_CENTER_IMUX7_8", - "CFG_CENTER_NE4BEG3_14", - "CFG_CENTER_NE4C0_10", - "CFG_CENTER_IMUX1_17", - "CFG_CENTER_CLK0_5", - "CFG_CENTER_IMUX34_15", - "CFG_CENTER_SE4BEG1_17", - "CFG_CENTER_BLOCK_OUTS_B3_8", - "CFG_CENTER_NW2A0_7", - "CFG_CENTER_WW4A0_10", - "CFG_CENTER_IMUX14_3", - "CFG_CENTER_NW4A1_10", - "CFG_CENTER_EE4C2_10", - "CFG_CENTER_NE2A0_17", - "CFG_CENTER_LH6_17", - "CFG_CENTER_EE2BEG2_10", - "CFG_CENTER_IMUX38_5", - "CFG_CENTER_WW4A2_8", - "CFG_CENTER_NW2A0_2", - "CFG_CENTER_SE2A1_8", - "CFG_CENTER_FAN3_7", - "CFG_CENTER_IMUX34_10", - "CFG_CENTER_NE4BEG1_4", - "CFG_CENTER_LOGIC_OUTS_B16_10", - "CFG_CENTER_SE4BEG2_18", - "CFG_CENTER_ER1BEG0_10", - "CFG_CENTER_WW2END3_6", - "CFG_CENTER_EL1BEG3_14", - "CFG_CENTER_IMUX45_15", - "CFG_CENTER_EE2BEG0_10", - "CFG_CENTER_SW2A3_18", - "CFG_CENTER_WW4C3_5", - "CFG_CENTER_SE4BEG0_17", - "CFG_CENTER_IMUX15_2", - "CFG_CENTER_WW4B3_11", - "CFG_CENTER_IMUX42_18", - "CFG_CENTER_NW4END0_12", - "CFG_CENTER_SW2A0_15", - "CFG_CENTER_BYP1_2", - "CFG_CENTER_IMUX38_10", - "CFG_CENTER_IMUX31_18", - "CFG_CENTER_ER1BEG0_16", - "CFG_CENTER_BYP7_3", - "CFG_CENTER_WW2A0_1", - "CFG_CENTER_LOGIC_OUTS_B9_0", - "CFG_CENTER_SE4C2_4", - "CFG_CENTER_NE4C0_12", - "CFG_CENTER_WW2A2_7", - "CFG_CENTER_SW2A1_9", - "CFG_CENTER_WL1END1_0", - "CFG_CENTER_NW4END2_16", - "CFG_CENTER_IMUX7_4", - "CFG_CENTER_SW4END3_4", - "CFG_CENTER_LOGIC_OUTS_B15_7", - "CFG_CENTER_BYP2_17", - "CFG_CENTER_BLOCK_OUTS_B2_5", - "CFG_CENTER_LH8_12", - "CFG_CENTER_WR1END0_5", - "CFG_CENTER_WL1END0_17", - "CFG_CENTER_EE4C3_5", - "CFG_CENTER_IMUX36_16", - "CFG_CENTER_BYP3_13", - "CFG_CENTER_BYP0_1", - "CFG_CENTER_EE4C2_15", - "CFG_CENTER_IMUX3_11", - "CFG_CENTER_CLK0_9", - "CFG_CENTER_IMUX10_4", - "CFG_CENTER_IMUX30_7", - "CFG_CENTER_IMUX23_7", - "CFG_CENTER_IMUX0_3", - "CFG_CENTER_IMUX36_0", - "CFG_CENTER_IMUX43_19", - "CFG_CENTER_EE4A3_5", - "CFG_CENTER_CLK0_18", - "CFG_CENTER_IMUX27_7", - "CFG_CENTER_LH10_19", - "CFG_CENTER_LH12_11", - "CFG_CENTER_EE4A3_12", - "CFG_CENTER_BYP0_14", - "CFG_CENTER_IMUX1_0", - "CFG_CENTER_LOGIC_OUTS_B7_15", - "CFG_CENTER_WW2A0_10", - "CFG_CENTER_EE4BEG2_16", - "CFG_CENTER_EE4A0_11", - "CFG_CENTER_IMUX12_8", - "CFG_CENTER_IMUX41_0", - "CFG_CENTER_BYP5_6", - "CFG_CENTER_IMUX11_15", - "CFG_CENTER_IMUX4_13", - "CFG_CENTER_EE4C2_3", - "CFG_CENTER_SW2A2_8", - "CFG_CENTER_IMUX11_14", - "CFG_CENTER_IMUX15_16", - "CFG_CENTER_LH1_15", - "CFG_CENTER_WR1END3_9", - "CFG_CENTER_WL1END2_14", - "CFG_CENTER_LOGIC_OUTS_B15_11", - "CFG_CENTER_SW4END1_18", - "CFG_CENTER_NW4A0_8", - "CFG_CENTER_NE4C1_10", - "CFG_CENTER_IMUX22_2", - "CFG_CENTER_BYP3_1", - "CFG_CENTER_WW2END1_18", - "CFG_CENTER_BLOCK_OUTS_B3_0", - "CFG_CENTER_WW2A3_9", - "CFG_CENTER_LOGIC_OUTS_B0_13", - "CFG_CENTER_LH8_7", - "CFG_CENTER_LH6_1", - "CFG_CENTER_LOGIC_OUTS_B5_3", - "CFG_CENTER_WW2A2_18", - "CFG_CENTER_WW4C2_12", - "CFG_CENTER_WW4END3_18", - "CFG_CENTER_IMUX29_7", - "CFG_CENTER_NE2A1_4", - "CFG_CENTER_LH10_1", - "CFG_CENTER_IMUX2_1", - "CFG_CENTER_IMUX28_18", - "CFG_CENTER_NE2A0_18", - "CFG_CENTER_SE4C1_6", - "CFG_CENTER_LOGIC_OUTS_B18_11", - "CFG_CENTER_WW4END0_7", - "CFG_CENTER_CTRL0_18", - "CFG_CENTER_WW2A3_4", - "CFG_CENTER_BYP6_5", - "CFG_CENTER_LH3_13", - "CFG_CENTER_IMUX43_16", - "CFG_CENTER_SW2A0_9", - "CFG_CENTER_IMUX12_5", - "CFG_CENTER_WW4C1_19", - "CFG_CENTER_LH4_0", - "CFG_CENTER_EE2A3_0", - "CFG_CENTER_BYP1_12", - "CFG_CENTER_EL1BEG1_3", - "CFG_CENTER_EE4A1_16", - "CFG_CENTER_LOGIC_OUTS_B7_12", - "CFG_CENTER_IMUX34_0", - "CFG_CENTER_IMUX38_2", - "CFG_CENTER_SW4END2_14", - "CFG_CENTER_LH12_19", - "CFG_CENTER_IMUX7_1", - "CFG_CENTER_NE4C0_6", - "CFG_CENTER_NW4END1_5", - "CFG_CENTER_EE4A3_16", - "CFG_CENTER_SW2A0_13", - "CFG_CENTER_IMUX19_19", - "CFG_CENTER_WR1END2_4", - "CFG_CENTER_IMUX16_6", - "CFG_CENTER_IMUX24_0", - "CFG_CENTER_WL1END0_8", - "CFG_CENTER_BLOCK_OUTS_B2_10", - "CFG_CENTER_LH1_16", - "CFG_CENTER_IMUX16_13", - "CFG_CENTER_IMUX44_4", - "CFG_CENTER_WL1END2_8", - "CFG_CENTER_SE4BEG1_18", - "CFG_CENTER_EL1BEG2_6", - "CFG_CENTER_EE2A3_15", - "CFG_CENTER_IMUX23_11", - "CFG_CENTER_SE2A0_1", - "CFG_CENTER_IMUX31_6", - "CFG_CENTER_SE4BEG0_3", - "CFG_CENTER_ER1BEG0_5", - "CFG_CENTER_EE2BEG3_10", - "CFG_CENTER_IMUX1_9", - "CFG_CENTER_LOGIC_OUTS_B8_5", - "CFG_CENTER_WR1END0_11", - "CFG_CENTER_NE4BEG0_8", - "CFG_CENTER_IMUX7_14", - "CFG_CENTER_LH7_6", - "CFG_CENTER_LH8_2", - "CFG_CENTER_ER1BEG1_11", - "CFG_CENTER_WW4C3_9", - "CFG_CENTER_WW2END2_6", - "CFG_CENTER_NW4END2_5", - "CFG_CENTER_WL1END3_3", - "CFG_CENTER_EE4A0_17", - "CFG_CENTER_WW2END0_7", - "CFG_CENTER_NW4END0_15", - "CFG_CENTER_CTRL0_9", - "CFG_CENTER_NW4A3_18", - "CFG_CENTER_IMUX20_4", - "CFG_CENTER_EL1BEG3_18", - "CFG_CENTER_LOGIC_OUTS_B7_10", - "CFG_CENTER_LOGIC_OUTS_B20_8", - "CFG_CENTER_IMUX27_8", - "CFG_CENTER_NE2A1_12", - "CFG_CENTER_IMUX14_7", - "CFG_CENTER_CLK0_8", - "CFG_CENTER_BLOCK_OUTS_B3_4", - "CFG_CENTER_EE4C3_0", - "CFG_CENTER_LOGIC_OUTS_B17_9", - "CFG_CENTER_WW4B0_18", - "CFG_CENTER_NE4C0_9", - "CFG_CENTER_NW2A0_1", - "CFG_CENTER_LH6_8", - "CFG_CENTER_NE4C1_3", - "CFG_CENTER_IMUX45_12", - "CFG_CENTER_IMUX1_14", - "CFG_CENTER_BLOCK_OUTS_B2_12", - "CFG_CENTER_LOGIC_OUTS_B9_18", - "CFG_CENTER_BYP2_4", - "CFG_CENTER_NE2A3_6", - "CFG_CENTER_SE4C1_0", - "CFG_CENTER_EE4A2_15", - "CFG_CENTER_LH6_6", - "CFG_CENTER_NW2A1_11", - "CFG_CENTER_LOGIC_OUTS_B10_8", - "CFG_CENTER_WL1END2_13", - "CFG_CENTER_BYP7_17", - "CFG_CENTER_CLK1_2", - "CFG_CENTER_IMUX33_8", - "CFG_CENTER_IMUX30_3", - "CFG_CENTER_LOGIC_OUTS_B12_14", - "CFG_CENTER_EE4BEG1_16", - "CFG_CENTER_IMUX28_2", - "CFG_CENTER_NW4A2_6", - "CFG_CENTER_LOGIC_OUTS_B16_14", - "CFG_CENTER_WL1END2_3", - "CFG_CENTER_IMUX15_19", - "CFG_CENTER_IMUX19_8", - "CFG_CENTER_LH5_2", - "CFG_CENTER_WW4END1_9", - "CFG_CENTER_LOGIC_OUTS_B1_6", - "CFG_CENTER_EE4A1_17", - "CFG_CENTER_IMUX40_4", - "CFG_CENTER_LOGIC_OUTS_B8_2", - "CFG_CENTER_WW2A2_9", - "CFG_CENTER_NE4BEG1_18", - "CFG_CENTER_NW4A2_7", - "CFG_CENTER_IMUX4_4", - "CFG_CENTER_FAN4_19", - "CFG_CENTER_WR1END0_13", - "CFG_CENTER_NE4BEG0_2", - "CFG_CENTER_LOGIC_OUTS_B21_17", - "CFG_CENTER_SE4BEG2_5", - "CFG_CENTER_LH1_5", - "CFG_CENTER_NW2A1_4", - "CFG_CENTER_IMUX42_2", - "CFG_CENTER_EE4B2_10", - "CFG_CENTER_SW4END3_17", - "CFG_CENTER_LH1_4", - "CFG_CENTER_IMUX6_16", - "CFG_CENTER_LOGIC_OUTS_B15_19", - "CFG_CENTER_IMUX13_0", - "CFG_CENTER_IMUX40_19", - "CFG_CENTER_WW4B2_6", - "CFG_CENTER_FAN5_9", - "CFG_CENTER_IMUX25_3", - "CFG_CENTER_SE4BEG3_3", - "CFG_CENTER_WW2A0_18", - "CFG_CENTER_NE4BEG3_12", - "CFG_CENTER_SW4A1_1", - "CFG_CENTER_FAN0_9", - "CFG_CENTER_WW4A3_6", - "CFG_CENTER_IMUX23_6", - "CFG_CENTER_EE4B3_19", - "CFG_CENTER_LOGIC_OUTS_B14_14", - "CFG_CENTER_FAN1_8", - "CFG_CENTER_NW4A2_1", - "CFG_CENTER_SE4C2_10", - "CFG_CENTER_LH1_9", - "CFG_CENTER_IMUX41_3", - "CFG_CENTER_IMUX44_3", - "CFG_CENTER_WW4C1_8", - "CFG_CENTER_NW4END1_6", - "CFG_CENTER_IMUX13_1", - "CFG_CENTER_WW4B2_12", - "CFG_CENTER_SE4C0_5", - "CFG_CENTER_IMUX20_8", - "CFG_CENTER_LOGIC_OUTS_B6_9", - "CFG_CENTER_SE4C3_11", - "CFG_CENTER_NE2A3_9", - "CFG_CENTER_IMUX31_5", - "CFG_CENTER_SE2A3_11", - "CFG_CENTER_LH2_18", - "CFG_CENTER_BYP3_2", - "CFG_CENTER_LOGIC_OUTS_B5_8", - "CFG_CENTER_NE4C0_0", - "CFG_CENTER_LOGIC_OUTS_B17_14", - "CFG_CENTER_SE4BEG1_12", - "CFG_CENTER_IMUX46_3", - "CFG_CENTER_LH8_3", - "CFG_CENTER_LOGIC_OUTS_B16_7", - "CFG_CENTER_FAN2_3", - "CFG_CENTER_LH11_7", - "CFG_CENTER_WR1END1_8", - "CFG_CENTER_BYP4_6", - "CFG_CENTER_EE4BEG1_2", - "CFG_CENTER_WR1END3_16", - "CFG_CENTER_SW4A2_12", - "CFG_CENTER_LOGIC_OUTS_B6_18", - "CFG_CENTER_BYP7_0", - "CFG_CENTER_IMUX11_0", - "CFG_CENTER_NE4BEG2_12", - "CFG_CENTER_BYP3_9", - "CFG_CENTER_SE4C3_7", - "CFG_CENTER_WW2A3_14", - "CFG_CENTER_SW4A1_3", - "CFG_CENTER_IMUX42_5", - "CFG_CENTER_WW4A3_14", - "CFG_CENTER_LOGIC_OUTS_B12_6", - "CFG_CENTER_SE4BEG2_16", - "CFG_CENTER_IMUX24_13", - "CFG_CENTER_FAN6_5", - "CFG_CENTER_SE2A0_15", - "CFG_CENTER_WW4B2_4", - "CFG_CENTER_NE2A2_13", - "CFG_CENTER_EE4B3_10", - "CFG_CENTER_LOGIC_OUTS_B2_14", - "CFG_CENTER_NE4C1_15", - "CFG_CENTER_SE4C3_8", - "CFG_CENTER_BYP0_18", - "CFG_CENTER_IMUX37_4", - "CFG_CENTER_LOGIC_OUTS_B17_15", - "CFG_CENTER_NW2A3_9", - "CFG_CENTER_IMUX16_16", - "CFG_CENTER_WW4C1_7", - "CFG_CENTER_LOGIC_OUTS_B14_6", - "CFG_CENTER_LOGIC_OUTS_B13_1", - "CFG_CENTER_WL1END0_10", - "CFG_CENTER_IMUX30_13", - "CFG_CENTER_EL1BEG1_8", - "CFG_CENTER_WW2A1_8", - "CFG_CENTER_IMUX34_4", - "CFG_CENTER_IMUX11_12", - "CFG_CENTER_WW2A2_16", - "CFG_CENTER_EL1BEG2_0", - "CFG_CENTER_LH10_18", - "CFG_CENTER_SE4C1_4", - "CFG_CENTER_IMUX43_7", - "CFG_CENTER_WW4A1_11", - "CFG_CENTER_WR1END2_3", - "CFG_CENTER_EE4A2_16", - "CFG_CENTER_IMUX26_2", - "CFG_CENTER_ER1BEG1_12", - "CFG_CENTER_IMUX6_13", - "CFG_CENTER_LH3_15", - "CFG_CENTER_BYP1_6", - "CFG_CENTER_FAN2_4", - "CFG_CENTER_LH11_8", - "CFG_CENTER_NW4END1_15", - "CFG_CENTER_LOGIC_OUTS_B11_18", - "CFG_CENTER_WW2END1_13", - "CFG_CENTER_LH4_4", - "CFG_CENTER_LOGIC_OUTS_B1_15", - "CFG_CENTER_LOGIC_OUTS_B1_5", - "CFG_CENTER_LOGIC_OUTS_B14_11", - "CFG_CENTER_LOGIC_OUTS_B7_16", - "CFG_CENTER_BYP1_3", - "CFG_CENTER_LOGIC_OUTS_B14_19", - "CFG_CENTER_NE4C3_7", - "CFG_CENTER_EE4BEG1_9", - "CFG_CENTER_FAN1_0", - "CFG_CENTER_SE2A1_0", - "CFG_CENTER_EE4C2_6", - "CFG_CENTER_BYP4_9", - "CFG_CENTER_LOGIC_OUTS_B15_6", - "CFG_CENTER_FAN6_10", - "CFG_CENTER_IMUX6_17", - "CFG_CENTER_WW2END3_10", - "CFG_CENTER_EE4A3_6", - "CFG_CENTER_WW2A1_19", - "CFG_CENTER_EE4BEG3_6", - "CFG_CENTER_WR1END2_8", - "CFG_CENTER_BLOCK_OUTS_B2_2", - "CFG_CENTER_NW4A2_11", - "CFG_CENTER_CLK1_10", - "CFG_CENTER_SE4BEG1_0", - "CFG_CENTER_CTRL1_3", - "CFG_CENTER_LH11_13", - "CFG_CENTER_NW4END3_15", - "CFG_CENTER_BLOCK_OUTS_B0_10", - "CFG_CENTER_LH7_18", - "CFG_CENTER_LOGIC_OUTS_B23_16", - "CFG_CENTER_SE2A1_6", - "CFG_CENTER_BYP5_5", - "CFG_CENTER_BLOCK_OUTS_B1_1", - "CFG_CENTER_IMUX39_16", - "CFG_CENTER_EE4A3_0", - "CFG_CENTER_SW4END1_6", - "CFG_CENTER_WW4A3_4", - "CFG_CENTER_EE4C0_13", - "CFG_CENTER_NW4END0_2", - "CFG_CENTER_WW4C3_3", - "CFG_CENTER_SW2A1_6", - "CFG_CENTER_LH11_11", - "CFG_CENTER_EE2A0_6", - "CFG_CENTER_BLOCK_OUTS_B2_14", - "CFG_CENTER_WW4C1_5", - "CFG_CENTER_LH8_1", - "CFG_CENTER_BYP0_17", - "CFG_CENTER_SW4A1_8", - "CFG_CENTER_BYP7_7", - "CFG_CENTER_NE4C2_5", - "CFG_CENTER_WW4A1_4", - "CFG_CENTER_SE4BEG3_9", - "CFG_CENTER_FAN4_17", - "CFG_CENTER_IMUX14_19", - "CFG_CENTER_NW4A2_13", - "CFG_CENTER_WL1END3_11", - "CFG_CENTER_BYP1_17", - "CFG_CENTER_WR1END1_0", - "CFG_CENTER_EE4B1_12", - "CFG_CENTER_IMUX12_16", - "CFG_CENTER_IMUX6_12", - "CFG_CENTER_LH4_10", - "CFG_CENTER_NW2A2_9", - "CFG_CENTER_IMUX21_6", - "CFG_CENTER_LOGIC_OUTS_B23_14", - "CFG_CENTER_IMUX32_6", - "CFG_CENTER_LH2_4", - "CFG_CENTER_EE4B0_4", - "CFG_CENTER_IMUX43_8", - "CFG_CENTER_ER1BEG2_0", - "CFG_CENTER_IMUX5_18", - "CFG_CENTER_IMUX17_17", - "CFG_CENTER_CLK0_14", - "CFG_CENTER_LH9_2", - "CFG_CENTER_ER1BEG0_8", - "CFG_CENTER_CTRL1_2", - "CFG_CENTER_WW4C2_9", - "CFG_CENTER_LOGIC_OUTS_B18_17", - "CFG_CENTER_FAN7_8", - "CFG_CENTER_WW4B3_13", - "CFG_CENTER_EE4C2_4", - "CFG_CENTER_EL1BEG3_3", - "CFG_CENTER_SE2A0_13", - "CFG_CENTER_IMUX13_7", - "CFG_CENTER_IMUX38_18", - "CFG_CENTER_NW2A0_10", - "CFG_CENTER_LOGIC_OUTS_B18_6", - "CFG_CENTER_SE4C0_10", - "CFG_CENTER_IMUX36_1", - "CFG_CENTER_EE2A0_5", - "CFG_CENTER_IMUX26_15", - "CFG_CENTER_FAN6_14", - "CFG_CENTER_IMUX44_10", - "CFG_CENTER_WW4C3_7", - "CFG_CENTER_IMUX23_17", - "CFG_CENTER_WW2END0_4", - "CFG_CENTER_SW2A0_10", - "CFG_CENTER_LH9_15", - "CFG_CENTER_IMUX28_16", - "CFG_CENTER_IMUX14_1", - "CFG_CENTER_IMUX21_4", - "CFG_CENTER_IMUX19_0", - "CFG_CENTER_WW4B0_13", - "CFG_CENTER_LH6_16", - "CFG_CENTER_WW2END1_12", - "CFG_CENTER_LOGIC_OUTS_B1_10", - "CFG_CENTER_NW4END2_18", - "CFG_CENTER_IMUX16_2", - "CFG_CENTER_EL1BEG1_1", - "CFG_CENTER_LH3_3", - "CFG_CENTER_BLOCK_OUTS_B3_6", - "CFG_CENTER_BYP2_9", - "CFG_CENTER_IMUX44_14", - "CFG_CENTER_BLOCK_OUTS_B1_11", - "CFG_CENTER_WL1END3_19", - "CFG_CENTER_ER1BEG0_4", - "CFG_CENTER_IMUX21_17", - "CFG_CENTER_IMUX35_5", - "CFG_CENTER_LOGIC_OUTS_B12_17", - "CFG_CENTER_IMUX4_7", - "CFG_CENTER_WW4A2_10", - "CFG_CENTER_EE4C2_16", - "CFG_CENTER_IMUX12_4", - "CFG_CENTER_SE2A1_17", - "CFG_CENTER_WW2END3_3", - "CFG_CENTER_WW4A3_10", - "CFG_CENTER_EE4A0_13", - "CFG_CENTER_NW2A3_13", - "CFG_CENTER_NW2A1_18", - "CFG_CENTER_SE4C3_16", - "CFG_CENTER_IMUX1_4", - "CFG_CENTER_IMUX13_13", - "CFG_CENTER_WW4C0_11", - "CFG_CENTER_EE4BEG2_15", - "CFG_CENTER_SE4C1_18", - "CFG_CENTER_WR1END3_10", - "CFG_CENTER_ER1BEG0_18", - "CFG_CENTER_NW4END2_13", - "CFG_CENTER_BYP0_5", - "CFG_CENTER_NW4END2_9", - "CFG_CENTER_LH3_6", - "CFG_CENTER_NW2A2_6", - "CFG_CENTER_NW2A0_3", - "CFG_CENTER_EE4B3_17", - "CFG_CENTER_NW2A3_10", - "CFG_CENTER_IMUX21_9", - "CFG_CENTER_SW4END0_18", - "CFG_CENTER_LOGIC_OUTS_B11_1", - "CFG_CENTER_IMUX41_7", - "CFG_CENTER_EE4A0_16", - "CFG_CENTER_EE2BEG2_14", - "CFG_CENTER_NW4A0_16", - "CFG_CENTER_BLOCK_OUTS_B2_17", - "CFG_CENTER_LOGIC_OUTS_B12_15", - "CFG_CENTER_LH6_5", - "CFG_CENTER_BLOCK_OUTS_B0_4", - "CFG_CENTER_EE4A1_5", - "CFG_CENTER_LH12_16", - "CFG_CENTER_NW4A3_12", - "CFG_CENTER_WL1END2_12", - "CFG_CENTER_LH9_6", - "CFG_CENTER_NW4END2_1", - "CFG_CENTER_WW2END1_0", - "CFG_CENTER_WW4A2_7", - "CFG_CENTER_LH7_9", - "CFG_CENTER_WR1END2_19", - "CFG_CENTER_LOGIC_OUTS_B1_12", - "CFG_CENTER_NW4END3_17", - "CFG_CENTER_LH11_9", - "CFG_CENTER_LH11_18", - "CFG_CENTER_FAN3_5", - "CFG_CENTER_IMUX2_12", - "CFG_CENTER_NW2A3_17", - "CFG_CENTER_SW2A2_2", - "CFG_CENTER_NW2A3_14", - "CFG_CENTER_IMUX13_8", - "CFG_CENTER_EE2A0_13", - "CFG_CENTER_IMUX41_11", - "CFG_CENTER_NW4A1_16", - "CFG_CENTER_IMUX45_16", - "CFG_CENTER_WR1END2_13", - "CFG_CENTER_SW4A2_8", - "CFG_CENTER_NW2A1_2", - "CFG_CENTER_SE2A0_6", - "CFG_CENTER_LOGIC_OUTS_B15_15", - "CFG_CENTER_SW4A0_6", - "CFG_CENTER_IMUX29_15", - "CFG_CENTER_IMUX27_0", - "CFG_CENTER_IMUX32_8", - "CFG_CENTER_WW4END3_8", - "CFG_CENTER_LOGIC_OUTS_B0_5", - "CFG_CENTER_IMUX30_8", - "CFG_CENTER_EL1BEG0_13", - "CFG_CENTER_IMUX16_3", - "CFG_CENTER_SE2A2_5", - "CFG_CENTER_IMUX5_6", - "CFG_CENTER_IMUX21_3", - "CFG_CENTER_ER1BEG3_14", - "CFG_CENTER_LH8_18", - "CFG_CENTER_WW4A3_0", - "CFG_CENTER_SE2A2_2", - "CFG_CENTER_LOGIC_OUTS_B14_17", - "CFG_CENTER_FAN1_10", - "CFG_CENTER_BYP0_12", - "CFG_CENTER_WW4A2_12", - "CFG_CENTER_WW2A3_5", - "CFG_CENTER_IMUX2_14", - "CFG_CENTER_IMUX26_3", - "CFG_CENTER_WW4B2_1", - "CFG_CENTER_IMUX3_3", - "CFG_CENTER_IMUX3_17", - "CFG_CENTER_WL1END1_2", - "CFG_CENTER_SW2A0_19", - "CFG_CENTER_FAN6_13", - "CFG_CENTER_IMUX12_19", - "CFG_CENTER_WW4A3_5", - "CFG_CENTER_IMUX24_11", - "CFG_CENTER_LOGIC_OUTS_B14_13", - "CFG_CENTER_NW4A2_2", - "CFG_CENTER_IMUX41_4", - "CFG_CENTER_IMUX8_2", - "CFG_CENTER_IMUX32_11", - "CFG_CENTER_FAN0_19", - "CFG_CENTER_IMUX8_3", - "CFG_CENTER_IMUX8_12", - "CFG_CENTER_EE4C3_16", - "CFG_CENTER_EE4BEG0_19", - "CFG_CENTER_SE2A2_17", - "CFG_CENTER_IMUX35_10", - "CFG_CENTER_WW4A1_17", - "CFG_CENTER_EE2BEG0_1", - "CFG_CENTER_LH8_9", - "CFG_CENTER_FAN0_4", - "CFG_CENTER_NW2A3_7", - "CFG_CENTER_EL1BEG0_8", - "CFG_CENTER_EE4BEG3_15", - "CFG_CENTER_EE2BEG2_6", - "CFG_CENTER_IMUX14_16", - "CFG_CENTER_LOGIC_OUTS_B2_16", - "CFG_CENTER_LOGIC_OUTS_B23_15", - "CFG_CENTER_LOGIC_OUTS_B2_13", - "CFG_CENTER_WW2A0_15", - "CFG_CENTER_IMUX39_9", - "CFG_CENTER_LOGIC_OUTS_B20_2", - "CFG_CENTER_LOGIC_OUTS_B9_2", - "CFG_CENTER_EE4A1_12", - "CFG_CENTER_WW2END1_19", - "CFG_CENTER_IMUX36_8", - "CFG_CENTER_EE2A2_3", - "CFG_CENTER_NW4A2_15", - "CFG_CENTER_LOGIC_OUTS_B15_13", - "CFG_CENTER_LH6_3", - "CFG_CENTER_CLK1_16", - "CFG_CENTER_LOGIC_OUTS_B14_18", - "CFG_CENTER_EE4BEG0_0", - "CFG_CENTER_WW2A3_13", - "CFG_CENTER_FAN4_11", - "CFG_CENTER_LH12_3", - "CFG_CENTER_WW4A3_9", - "CFG_CENTER_NE2A3_2", - "CFG_CENTER_LOGIC_OUTS_B17_0", - "CFG_CENTER_FAN1_1", - "CFG_CENTER_IMUX28_4", - "CFG_CENTER_SW4A2_0", - "CFG_CENTER_WL1END0_15", - "CFG_CENTER_SE4C2_18", - "CFG_CENTER_NE2A1_0", - "CFG_CENTER_LOGIC_OUTS_B20_1", - "CFG_CENTER_IMUX12_7", - "CFG_CENTER_IMUX32_3", - "CFG_CENTER_EE4B3_9", - "CFG_CENTER_WW2END2_13", - "CFG_CENTER_LOGIC_OUTS_B18_2", - "CFG_CENTER_NE4BEG3_13", - "CFG_CENTER_BYP0_8", - "CFG_CENTER_EE2A1_3", - "CFG_CENTER_NE2A2_15", - "CFG_CENTER_SW4END0_5", - "CFG_CENTER_WW4A3_13", - "CFG_CENTER_EE4BEG2_9", - "CFG_CENTER_FAN3_4", - "CFG_CENTER_WL1END0_13", - "CFG_CENTER_BLOCK_OUTS_B0_9", - "CFG_CENTER_IMUX13_14", - "CFG_CENTER_IMUX3_18", - "CFG_CENTER_WW4END0_11", - "CFG_CENTER_WW4B0_7", - "CFG_CENTER_IMUX16_7", - "CFG_CENTER_SW2A3_5", - "CFG_CENTER_WW4END3_19", - "CFG_CENTER_IMUX7_18", - "CFG_CENTER_SE4C1_5", - "CFG_CENTER_WR1END1_7", - "CFG_CENTER_IMUX35_12", - "CFG_CENTER_IMUX36_19", - "CFG_CENTER_LH6_19", - "CFG_CENTER_ER1BEG1_13", - "CFG_CENTER_EE4A2_7", - "CFG_CENTER_LOGIC_OUTS_B1_8", - "CFG_CENTER_BYP2_2", - "CFG_CENTER_NW4END0_5", - "CFG_CENTER_LOGIC_OUTS_B22_0", - "CFG_CENTER_LOGIC_OUTS_B13_0", - "CFG_CENTER_SE2A1_2", - "CFG_CENTER_IMUX14_18", - "CFG_CENTER_IMUX29_14", - "CFG_CENTER_SW4A1_17", - "CFG_CENTER_IMUX27_1", - "CFG_CENTER_SW4A0_11", - "CFG_CENTER_IMUX29_8", - "CFG_CENTER_SE2A0_2", - "CFG_CENTER_FAN5_3", - "CFG_CENTER_IMUX37_9", - "CFG_CENTER_FAN7_12", - "CFG_CENTER_LH2_10", - "CFG_CENTER_IMUX25_0", - "CFG_CENTER_IMUX19_9", - "CFG_CENTER_NE4BEG1_10", - "CFG_CENTER_EE4A2_6", - "CFG_CENTER_IMUX9_13", - "CFG_CENTER_ER1BEG3_3", - "CFG_CENTER_SW4END1_11", - "CFG_CENTER_IMUX29_10", - "CFG_CENTER_IMUX24_3", - "CFG_CENTER_LOGIC_OUTS_B15_18", - "CFG_CENTER_WW2END3_4", - "CFG_CENTER_WW2A2_4", - "CFG_CENTER_EE2BEG3_3", - "CFG_CENTER_NW4END2_19", - "CFG_CENTER_WW4B0_4", - "CFG_CENTER_EE2A1_8", - "CFG_CENTER_IMUX13_16", - "CFG_CENTER_FAN0_18", - "CFG_CENTER_WW4B1_8", - "CFG_CENTER_ER1BEG2_10", - "CFG_CENTER_IMUX47_11", - "CFG_CENTER_BYP7_16", - "CFG_CENTER_LH1_12", - "CFG_CENTER_LOGIC_OUTS_B23_3", - "CFG_CENTER_NW4A0_7", - "CFG_CENTER_SW4A0_17", - "CFG_CENTER_ER1BEG0_2", - "CFG_CENTER_BYP1_13", - "CFG_CENTER_EE4BEG2_7", - "CFG_CENTER_WW4A2_1", - "CFG_CENTER_NE2A2_7", - "CFG_CENTER_EE2BEG0_8", - "CFG_CENTER_SW2A3_13", - "CFG_CENTER_LOGIC_OUTS_B17_3", - "CFG_CENTER_CLK1_0", - "CFG_CENTER_IMUX6_6", - "CFG_CENTER_WR1END2_6", - "CFG_CENTER_FAN1_12", - "CFG_CENTER_EE2A2_12", - "CFG_CENTER_IMUX41_9", - "CFG_CENTER_IMUX16_19", - "CFG_CENTER_NE2A1_6", - "CFG_CENTER_LOGIC_OUTS_B0_4", - "CFG_CENTER_WL1END2_9", - "CFG_CENTER_ER1BEG0_7", - "CFG_CENTER_LOGIC_OUTS_B5_19", - "CFG_CENTER_NW4A1_9", - "CFG_CENTER_LOGIC_OUTS_B19_16", - "CFG_CENTER_LH4_15", - "CFG_CENTER_EL1BEG0_19", - "CFG_CENTER_WW2A3_17", - "CFG_CENTER_BYP2_11", - "CFG_CENTER_IMUX17_9", - "CFG_CENTER_EE4B1_2", - "CFG_CENTER_IMUX45_11", - "CFG_CENTER_NW4END2_4", - "CFG_CENTER_BLOCK_OUTS_B1_7", - "CFG_CENTER_LH11_1", - "CFG_CENTER_IMUX31_4", - "CFG_CENTER_IMUX0_5", - "CFG_CENTER_IMUX4_17", - "CFG_CENTER_SW4A2_10", - "CFG_CENTER_SE2A1_11", - "CFG_CENTER_SE4BEG3_0", - "CFG_CENTER_EE4B1_1", - "CFG_CENTER_LH10_9", - "CFG_CENTER_BYP5_19", - "CFG_CENTER_SW4END2_4", - "CFG_CENTER_BLOCK_OUTS_B0_5", - "CFG_CENTER_NW4A3_2", - "CFG_CENTER_IMUX31_15", - "CFG_CENTER_LOGIC_OUTS_B0_7", - "CFG_CENTER_LOGIC_OUTS_B22_15", - "CFG_CENTER_WW4B0_12", - "CFG_CENTER_NE2A3_17", - "CFG_CENTER_IMUX2_19", - "CFG_CENTER_WL1END0_9", - "CFG_CENTER_IMUX45_10", - "CFG_CENTER_SW4END1_12", - "CFG_CENTER_EL1BEG0_15", - "CFG_CENTER_IMUX21_0", - "CFG_CENTER_SE2A0_12", - "CFG_CENTER_LOGIC_OUTS_B1_0", - "CFG_CENTER_NW4A2_0", - "CFG_CENTER_NE2A2_9", - "CFG_CENTER_SE4C2_13", - "CFG_CENTER_WW2END3_16", - "CFG_CENTER_WW2A0_3", - "CFG_CENTER_NE4BEG2_18", - "CFG_CENTER_WW2END1_2", - "CFG_CENTER_SE4C1_14", - "CFG_CENTER_IMUX21_12", - "CFG_CENTER_IMUX29_3", - "CFG_CENTER_LOGIC_OUTS_B14_8", - "CFG_CENTER_ER1BEG0_17", - "CFG_CENTER_LOGIC_OUTS_B7_13", - "CFG_CENTER_LOGIC_OUTS_B18_15", - "CFG_CENTER_SE4BEG2_17", - "CFG_CENTER_EE4B2_13", - "CFG_CENTER_EE4BEG0_2", - "CFG_CENTER_LOGIC_OUTS_B4_13", - "CFG_CENTER_CLK1_9", - "CFG_CENTER_CTRL1_9", - "CFG_CENTER_NE4C1_14", - "CFG_CENTER_SW4END3_1", - "CFG_CENTER_WW2END1_10", - "CFG_CENTER_LH5_5", - "CFG_CENTER_EE4A2_5", - "CFG_CENTER_NW4END3_0", - "CFG_CENTER_IMUX47_7", - "CFG_CENTER_IMUX19_13", - "CFG_CENTER_WR1END2_1", - "CFG_CENTER_IMUX7_6", - "CFG_CENTER_LOGIC_OUTS_B9_4", - "CFG_CENTER_WW4A1_14", - "CFG_CENTER_LOGIC_OUTS_B0_9", - "CFG_CENTER_LOGIC_OUTS_B8_10", - "CFG_CENTER_WR1END2_9", - "CFG_CENTER_SW4A1_16", - "CFG_CENTER_EE2A0_7", - "CFG_CENTER_LOGIC_OUTS_B23_12", - "CFG_CENTER_EE2BEG3_12", - "CFG_CENTER_SW4END2_8", - "CFG_CENTER_IMUX23_3", - "CFG_CENTER_LOGIC_OUTS_B16_3", - "CFG_CENTER_LOGIC_OUTS_B21_2", - "CFG_CENTER_FAN3_18", - "CFG_CENTER_IMUX10_8", - "CFG_CENTER_IMUX22_11", - "CFG_CENTER_EL1BEG0_6", - "CFG_CENTER_IMUX8_5", - "CFG_CENTER_NE4C3_1", - "CFG_CENTER_IMUX46_4", - "CFG_CENTER_IMUX43_12", - "CFG_CENTER_NW4A0_13", - "CFG_CENTER_LOGIC_OUTS_B13_8", - "CFG_CENTER_NE2A0_9", - "CFG_CENTER_LOGIC_OUTS_B21_6", - "CFG_CENTER_EE4C1_3", - "CFG_CENTER_WW4B1_12", - "CFG_CENTER_WW2A0_17", - "CFG_CENTER_LOGIC_OUTS_B16_16", - "CFG_CENTER_EE4B2_0", - "CFG_CENTER_BLOCK_OUTS_B1_10", - "CFG_CENTER_EE4B0_9", - "CFG_CENTER_LOGIC_OUTS_B22_18", - "CFG_CENTER_NE4BEG1_14", - "CFG_CENTER_LH9_3", - "CFG_CENTER_WW4C0_12", - "CFG_CENTER_NE2A1_7", - "CFG_CENTER_LH12_8", - "CFG_CENTER_LOGIC_OUTS_B21_11", - "CFG_CENTER_BOT_USR_ACCESS_DATA14", - "CFG_CENTER_WW4C2_8", - "CFG_CENTER_FAN1_16", - "CFG_CENTER_EE4C1_18", - "CFG_CENTER_LOGIC_OUTS_B4_15", - "CFG_CENTER_EE4A0_12", - "CFG_CENTER_ER1BEG3_6", - "CFG_CENTER_CLK1_19", - "CFG_CENTER_IMUX43_4", - "CFG_CENTER_FAN0_1", - "CFG_CENTER_NE4C2_18", - "CFG_CENTER_BYP5_13", - "CFG_CENTER_NE4BEG3_6", - "CFG_CENTER_NW4END3_5", - "CFG_CENTER_LH6_10", - "CFG_CENTER_EE4C2_2", - "CFG_CENTER_BLOCK_OUTS_B3_5", - "CFG_CENTER_IMUX42_9", - "CFG_CENTER_NW2A1_1", - "CFG_CENTER_LOGIC_OUTS_B19_11", - "CFG_CENTER_WL1END3_9", - "CFG_CENTER_LOGIC_OUTS_B10_18", - "CFG_CENTER_SE2A0_19", - "CFG_CENTER_LOGIC_OUTS_B13_5", - "CFG_CENTER_EE2BEG1_3", - "CFG_CENTER_IMUX43_13", - "CFG_CENTER_LOGIC_OUTS_B2_9", - "CFG_CENTER_WW4END1_8", - "CFG_CENTER_EE2A0_14", - "CFG_CENTER_LOGIC_OUTS_B11_12", - "CFG_CENTER_CTRL1_7", - "CFG_CENTER_WR1END1_9", - "CFG_CENTER_LOGIC_OUTS_B16_19", - "CFG_CENTER_WW4B3_1", - "CFG_CENTER_EE2A3_9", - "CFG_CENTER_WW2A2_10", - "CFG_CENTER_BLOCK_OUTS_B3_2", - "CFG_CENTER_IMUX19_16", - "CFG_CENTER_NE4C0_14", - "CFG_CENTER_LOGIC_OUTS_B17_12", - "CFG_CENTER_IMUX15_18", - "CFG_CENTER_EE2BEG2_9", - "CFG_CENTER_WW2END0_6", - "CFG_CENTER_LOGIC_OUTS_B6_11", - "CFG_CENTER_ER1BEG0_19", - "CFG_CENTER_IMUX30_17", - "CFG_CENTER_WW4C2_10", - "CFG_CENTER_WW4B2_5", - "CFG_CENTER_EE4BEG3_19", - "CFG_CENTER_WW4A2_14", - "CFG_CENTER_LOGIC_OUTS_B14_12", - "CFG_CENTER_EE4B3_0", - "CFG_CENTER_EE4BEG0_5", - "CFG_CENTER_EE2A3_4", - "CFG_CENTER_IMUX5_17", - "CFG_CENTER_NE2A0_5", - "CFG_CENTER_IMUX40_8", - "CFG_CENTER_LOGIC_OUTS_B20_14", - "CFG_CENTER_LOGIC_OUTS_B5_11", - "CFG_CENTER_EE2BEG3_2", - "CFG_CENTER_IMUX47_10", - "CFG_CENTER_LOGIC_OUTS_B18_18", - "CFG_CENTER_SE4C1_1", - "CFG_CENTER_BYP3_10", - "CFG_CENTER_IMUX39_0", - "CFG_CENTER_CLK1_1", - "CFG_CENTER_IMUX35_0", - "CFG_CENTER_ER1BEG1_17", - "CFG_CENTER_CLK1_18", - "CFG_CENTER_EE4A1_9", - "CFG_CENTER_WL1END1_16", - "CFG_CENTER_WW4B1_6", - "CFG_CENTER_LOGIC_OUTS_B19_19", - "CFG_CENTER_EE2BEG1_11", - "CFG_CENTER_LH11_3", - "CFG_CENTER_IMUX6_14", - "CFG_CENTER_NE2A2_5", - "CFG_CENTER_IMUX47_16", - "CFG_CENTER_FAN7_17", - "CFG_CENTER_SE2A3_9", - "CFG_CENTER_EE4C1_11", - "CFG_CENTER_NW4A3_5", - "CFG_CENTER_IMUX23_10", - "CFG_CENTER_LOGIC_OUTS_B15_4", - "CFG_CENTER_WW2A3_15", - "CFG_CENTER_FAN6_12", - "CFG_CENTER_LOGIC_OUTS_B12_10", - "CFG_CENTER_LOGIC_OUTS_B17_16", - "CFG_CENTER_NE4BEG1_16", - "CFG_CENTER_LH7_2", - "CFG_CENTER_WW4C0_10", - "CFG_CENTER_NE4BEG3_5", - "CFG_CENTER_NE2A0_6", - "CFG_CENTER_LH2_1", - "CFG_CENTER_SW2A1_0", - "CFG_CENTER_SW2A1_10", - "CFG_CENTER_EE2BEG3_7", - "CFG_CENTER_LOGIC_OUTS_B23_18", - "CFG_CENTER_NE4C3_19", - "CFG_CENTER_SW4A3_19", - "CFG_CENTER_IMUX19_12", - "CFG_CENTER_EE4B0_13", - "CFG_CENTER_IMUX21_7", - "CFG_CENTER_FAN1_2", - "CFG_CENTER_WW2A1_17", - "CFG_CENTER_SW4END3_6", - "CFG_CENTER_SE4BEG2_1", - "CFG_CENTER_IMUX4_0", - "CFG_CENTER_LOGIC_OUTS_B19_15", - "CFG_CENTER_WW2A2_14", - "CFG_CENTER_NW2A2_3", - "CFG_CENTER_LH7_8", - "CFG_CENTER_IMUX10_13", - "CFG_CENTER_IMUX40_16", - "CFG_CENTER_IMUX36_4", - "CFG_CENTER_WR1END0_18", - "CFG_CENTER_SW2A1_5", - "CFG_CENTER_IMUX40_6", - "CFG_CENTER_LOGIC_OUTS_B5_15", - "CFG_CENTER_NW4A1_17", - "CFG_CENTER_LOGIC_OUTS_B6_12", - "CFG_CENTER_EE2A0_1", - "CFG_CENTER_EE2A1_18", - "CFG_CENTER_NW4END0_13", - "CFG_CENTER_IMUX26_14", - "CFG_CENTER_SW2A2_13", - "CFG_CENTER_WW4END2_10", - "CFG_CENTER_WW4B0_15", - "CFG_CENTER_WW4A1_12", - "CFG_CENTER_IMUX9_18", - "CFG_CENTER_IMUX36_6", - "CFG_CENTER_IMUX44_15", - "CFG_CENTER_WW4END1_1", - "CFG_CENTER_IMUX14_8", - "CFG_CENTER_EE2BEG0_14", - "CFG_CENTER_SE4BEG3_2", - "CFG_CENTER_LOGIC_OUTS_B7_18", - "CFG_CENTER_WW4A0_4", - "CFG_CENTER_SE4C1_13", - "CFG_CENTER_WW2END0_17", - "CFG_CENTER_WW2END2_5", - "CFG_CENTER_IMUX26_19", - "CFG_CENTER_SW4END0_12", - "CFG_CENTER_LOGIC_OUTS_B4_17", - "CFG_CENTER_WW2A2_5", - "CFG_CENTER_SW2A1_18", - "CFG_CENTER_CLK1_7", - "CFG_CENTER_WW4C3_10", - "CFG_CENTER_LH8_16", - "CFG_CENTER_ER1BEG2_11", - "CFG_CENTER_EE2BEG3_5", - "CFG_CENTER_IMUX17_5", - "CFG_CENTER_SW2A3_11", - "CFG_CENTER_FAN3_11", - "CFG_CENTER_FAN0_13", - "CFG_CENTER_IMUX18_16", - "CFG_CENTER_NW2A2_17", - "CFG_CENTER_SE4BEG1_10", - "CFG_CENTER_ER1BEG1_2", - "CFG_CENTER_IMUX1_10", - "CFG_CENTER_WW4END3_13", - "CFG_CENTER_SW4END1_9", - "CFG_CENTER_BYP1_14", - "CFG_CENTER_LOGIC_OUTS_B11_15", - "CFG_CENTER_IMUX27_11", - "CFG_CENTER_IMUX31_11", - "CFG_CENTER_IMUX5_4", - "CFG_CENTER_NW4A3_17", - "CFG_CENTER_SW4END1_4", - "CFG_CENTER_FAN7_2", - "CFG_CENTER_IMUX19_14", - "CFG_CENTER_EE4C2_19", - "CFG_CENTER_IMUX12_9", - "CFG_CENTER_EE4A2_17", - "CFG_CENTER_SW4A1_2", - "CFG_CENTER_CLK0_16", - "CFG_CENTER_BLOCK_OUTS_B0_16", - "CFG_CENTER_CLK0_6", - "CFG_CENTER_LH8_8", - "CFG_CENTER_IMUX9_7", - "CFG_CENTER_WW2END3_2", - "CFG_CENTER_NW4A3_11", - "CFG_CENTER_EE2A3_3", - "CFG_CENTER_IMUX39_7", - "CFG_CENTER_NW4END1_1", - "CFG_CENTER_EE4C0_19", - "CFG_CENTER_EE4C1_7", - "CFG_CENTER_EE2A2_10", - "CFG_CENTER_NW4END2_11", - "CFG_CENTER_WW4A1_2", - "CFG_CENTER_LOGIC_OUTS_B3_10", - "CFG_CENTER_SE4BEG1_2", - "CFG_CENTER_FAN0_17", - "CFG_CENTER_SE4C2_8", - "CFG_CENTER_LH1_10", - "CFG_CENTER_SE4C2_5", - "CFG_CENTER_WW4C1_10", - "CFG_CENTER_LOGIC_OUTS_B1_16", - "CFG_CENTER_BYP4_2", - "CFG_CENTER_LOGIC_OUTS_B21_8", - "CFG_CENTER_FAN6_3", - "CFG_CENTER_NW4A0_5", - "CFG_CENTER_SW4END0_14", - "CFG_CENTER_LOGIC_OUTS_B13_12", - "CFG_CENTER_CLK1_11", - "CFG_CENTER_FAN6_9", - "CFG_CENTER_IMUX30_18", - "CFG_CENTER_ER1BEG1_0", - "CFG_CENTER_IMUX11_17", - "CFG_CENTER_IMUX1_1", - "CFG_CENTER_CTRL1_1", - "CFG_CENTER_IMUX3_13", - "CFG_CENTER_BLOCK_OUTS_B3_14", - "CFG_CENTER_LOGIC_OUTS_B11_19", - "CFG_CENTER_EL1BEG0_11", - "CFG_CENTER_IMUX37_19", - "CFG_CENTER_BLOCK_OUTS_B2_4", - "CFG_CENTER_EE4BEG2_11", - "CFG_CENTER_EE4A0_6", - "CFG_CENTER_WR1END2_2", - "CFG_CENTER_WW2A1_5", - "CFG_CENTER_SW2A1_11", - "CFG_CENTER_IMUX10_2", - "CFG_CENTER_SE4BEG3_1", - "CFG_CENTER_LOGIC_OUTS_B21_9", - "CFG_CENTER_NW2A1_16", - "CFG_CENTER_WR1END0_3", - "CFG_CENTER_NE4C2_0", - "CFG_CENTER_IMUX4_6", - "CFG_CENTER_SE4C3_17", - "CFG_CENTER_LH10_7", - "CFG_CENTER_EE2BEG3_15", - "CFG_CENTER_BYP7_8", - "CFG_CENTER_EE4C2_18", - "CFG_CENTER_IMUX45_14", - "CFG_CENTER_FAN4_9", - "CFG_CENTER_IMUX24_8", - "CFG_CENTER_FAN7_7", - "CFG_CENTER_NW4END3_13", - "CFG_CENTER_IMUX39_17", - "CFG_CENTER_IMUX25_12", - "CFG_CENTER_LH3_4", - "CFG_CENTER_FAN2_15", - "CFG_CENTER_IMUX26_9", - "CFG_CENTER_WW4C1_16", - "CFG_CENTER_IMUX6_15", - "CFG_CENTER_IMUX37_17", - "CFG_CENTER_NW4A1_13", - "CFG_CENTER_IMUX15_8", - "CFG_CENTER_BLOCK_OUTS_B1_19", - "CFG_CENTER_NW2A2_4", - "CFG_CENTER_EE2BEG3_18", - "CFG_CENTER_NE2A0_14", - "CFG_CENTER_IMUX10_5", - "CFG_CENTER_FAN6_15", - "CFG_CENTER_NE4C0_5", - "CFG_CENTER_LOGIC_OUTS_B22_14", - "CFG_CENTER_SE4C0_16", - "CFG_CENTER_WW2END0_15", - "CFG_CENTER_BYP1_16", - "CFG_CENTER_NW4END2_10", - "CFG_CENTER_EE4B3_6", - "CFG_CENTER_LH1_0", - "CFG_CENTER_WW4B3_16", - "CFG_CENTER_WW4B1_10", - "CFG_CENTER_LOGIC_OUTS_B5_10", - "CFG_CENTER_SW4END3_2", - "CFG_CENTER_IMUX37_16", - "CFG_CENTER_NW2A0_6", - "CFG_CENTER_LOGIC_OUTS_B1_14", - "CFG_CENTER_WW4A2_18", - "CFG_CENTER_EE2BEG3_17", - "CFG_CENTER_BYP6_13", - "CFG_CENTER_IMUX14_10", - "CFG_CENTER_LH7_3", - "CFG_CENTER_NE4C2_3", - "CFG_CENTER_IMUX35_2", - "CFG_CENTER_SW2A2_18", - "CFG_CENTER_WW2END3_15", - "CFG_CENTER_IMUX12_3", - "CFG_CENTER_FAN4_5", - "CFG_CENTER_SE2A1_5", - "CFG_CENTER_NW2A3_4", - "CFG_CENTER_WR1END1_18", - "CFG_CENTER_IMUX43_3", - "CFG_CENTER_SW4END3_14", - "CFG_CENTER_IMUX42_16", - "CFG_CENTER_SE2A1_13", - "CFG_CENTER_EE4A0_7", - "CFG_CENTER_IMUX11_18", - "CFG_CENTER_WW4END0_4", - "CFG_CENTER_SW4END3_9", - "CFG_CENTER_NW2A3_11", - "CFG_CENTER_IMUX46_14", - "CFG_CENTER_EE4B1_4", - "CFG_CENTER_IMUX10_7", - "CFG_CENTER_SW4A2_11", - "CFG_CENTER_IMUX32_0", - "CFG_CENTER_WW4A0_16", - "CFG_CENTER_SW4END3_15", - "CFG_CENTER_CTRL1_12", - "CFG_CENTER_ER1BEG2_2", - "CFG_CENTER_IMUX27_6", - "CFG_CENTER_WW4A2_11", - "CFG_CENTER_SE4BEG2_12", - "CFG_CENTER_ER1BEG3_11", - "CFG_CENTER_BLOCK_OUTS_B1_12", - "CFG_CENTER_SW4END1_5", - "CFG_CENTER_SW4END1_1", - "CFG_CENTER_NE4BEG3_17", - "CFG_CENTER_IMUX23_5", - "CFG_CENTER_NE4C3_14", - "CFG_CENTER_NE4C1_16", - "CFG_CENTER_LOGIC_OUTS_B6_14", - "CFG_CENTER_CTRL1_10", - "CFG_CENTER_IMUX2_6", - "CFG_CENTER_IMUX39_19", - "CFG_CENTER_SE4C0_6", - "CFG_CENTER_LH9_4", - "CFG_CENTER_NW2A1_6", - "CFG_CENTER_IMUX33_5", - "CFG_CENTER_IMUX9_1", - "CFG_CENTER_WW2END2_14", - "CFG_CENTER_IMUX26_13", - "CFG_CENTER_WW4C1_15", - "CFG_CENTER_EE2A3_8", - "CFG_CENTER_BOT_USR_ACCESS_DATA11", - "CFG_CENTER_LOGIC_OUTS_B2_19", - "CFG_CENTER_SW4END2_11", - "CFG_CENTER_IMUX45_5", - "CFG_CENTER_IMUX28_5", - "CFG_CENTER_WW4END3_11", - "CFG_CENTER_NE4C1_1", - "CFG_CENTER_WW4C0_18", - "CFG_CENTER_EL1BEG3_4", - "CFG_CENTER_WW4A1_6", - "CFG_CENTER_IMUX8_4", - "CFG_CENTER_ER1BEG3_1", - "CFG_CENTER_ER1BEG1_14", - "CFG_CENTER_EL1BEG0_14", - "CFG_CENTER_EE4B1_19", - "CFG_CENTER_WW2A3_18", - "CFG_CENTER_IMUX31_8", - "CFG_CENTER_NW4A1_18", - "CFG_CENTER_LOGIC_OUTS_B1_4", - "CFG_CENTER_BYP4_7", - "CFG_CENTER_WL1END1_14", - "CFG_CENTER_SE2A0_5", - "CFG_CENTER_SE2A3_15", - "CFG_CENTER_SE4C1_12", - "CFG_CENTER_IMUX35_13", - "CFG_CENTER_LOGIC_OUTS_B0_10", - "CFG_CENTER_LOGIC_OUTS_B4_18", - "CFG_CENTER_SE4BEG0_7", - "CFG_CENTER_IMUX16_1", - "CFG_CENTER_SE2A1_3", - "CFG_CENTER_WW4B1_14", - "CFG_CENTER_EL1BEG2_10", - "CFG_CENTER_LH7_13", - "CFG_CENTER_SW4A3_11", - "CFG_CENTER_LOGIC_OUTS_B22_11", - "CFG_CENTER_NW2A3_1", - "CFG_CENTER_EL1BEG0_10", - "CFG_CENTER_EE4A2_9", - "CFG_CENTER_NW4END3_6", - "CFG_CENTER_IMUX2_7", - "CFG_CENTER_LOGIC_OUTS_B2_7", - "CFG_CENTER_SE4BEG0_0", - "CFG_CENTER_LH1_2", - "CFG_CENTER_WW4END1_4", - "CFG_CENTER_BYP3_15", - "CFG_CENTER_WW4END2_12", - "CFG_CENTER_LOGIC_OUTS_B12_16", - "CFG_CENTER_SE4C3_3", - "CFG_CENTER_EE4C1_19", - "CFG_CENTER_EE4A1_19", - "CFG_CENTER_BYP5_17", - "CFG_CENTER_WW2END3_8", - "CFG_CENTER_NW4END0_1", - "CFG_CENTER_LH9_17", - "CFG_CENTER_LOGIC_OUTS_B8_6", - "CFG_CENTER_SE4C0_8", - "CFG_CENTER_IMUX9_11", - "CFG_CENTER_BYP6_3", - "CFG_CENTER_NE4C1_8", - "CFG_CENTER_IMUX15_10", - "CFG_CENTER_BLOCK_OUTS_B0_13", - "CFG_CENTER_IMUX35_3", - "CFG_CENTER_BYP0_11", - "CFG_CENTER_BYP5_16", - "CFG_CENTER_IMUX47_6", - "CFG_CENTER_LOGIC_OUTS_B18_4", - "CFG_CENTER_EL1BEG3_7", - "CFG_CENTER_EE4C0_1", - "CFG_CENTER_BYP6_10", - "CFG_CENTER_SW4A1_18", - "CFG_CENTER_LH3_8", - "CFG_CENTER_LOGIC_OUTS_B5_7", - "CFG_CENTER_SW4A0_3", - "CFG_CENTER_WR1END3_2", - "CFG_CENTER_BYP3_19", - "CFG_CENTER_IMUX45_18", - "CFG_CENTER_BLOCK_OUTS_B0_17", - "CFG_CENTER_SE2A2_13", - "CFG_CENTER_WW4B0_16", - "CFG_CENTER_EL1BEG1_18", - "CFG_CENTER_WL1END2_18", - "CFG_CENTER_ER1BEG2_3", - "CFG_CENTER_SE2A2_1", - "CFG_CENTER_WW4B0_10", - "CFG_CENTER_EL1BEG1_7", - "CFG_CENTER_IMUX31_16", - "CFG_CENTER_LOGIC_OUTS_B23_11", - "CFG_CENTER_NE2A3_0", - "CFG_CENTER_WW4A1_13", - "CFG_CENTER_LOGIC_OUTS_B21_15", - "CFG_CENTER_EL1BEG0_3", - "CFG_CENTER_WW2A1_1", - "CFG_CENTER_SE2A2_15", - "CFG_CENTER_WW4END1_17", - "CFG_CENTER_WW2END1_14", - "CFG_CENTER_EE4A1_18", - "CFG_CENTER_IMUX39_11", - "CFG_CENTER_EE4A0_18", - "CFG_CENTER_NW2A1_12", - "CFG_CENTER_IMUX9_12", - "CFG_CENTER_IMUX41_10", - "CFG_CENTER_WW4B1_11", - "CFG_CENTER_WW2A1_14", - "CFG_CENTER_SW4A3_14", - "CFG_CENTER_LOGIC_OUTS_B20_3", - "CFG_CENTER_IMUX39_6", - "CFG_CENTER_SE2A3_0", - "CFG_CENTER_LOGIC_OUTS_B2_10", - "CFG_CENTER_LH10_17", - "CFG_CENTER_LH5_4", - "CFG_CENTER_IMUX35_14", - "CFG_CENTER_CTRL1_0", - "CFG_CENTER_IMUX20_16", - "CFG_CENTER_WW2A0_8", - "CFG_CENTER_NW4A2_14", - "CFG_CENTER_EL1BEG2_11", - "CFG_CENTER_WW4C0_4", - "CFG_CENTER_EE4BEG0_9", - "CFG_CENTER_LOGIC_OUTS_B20_7", - "CFG_CENTER_WW4A1_3", - "CFG_CENTER_SW4END3_12", - "CFG_CENTER_IMUX29_16", - "CFG_CENTER_EE2A3_13", - "CFG_CENTER_EE4A0_4", - "CFG_CENTER_LOGIC_OUTS_B13_18", - "CFG_CENTER_IMUX35_8", - "CFG_CENTER_SW4END0_10", - "CFG_CENTER_LOGIC_OUTS_B22_5", - "CFG_CENTER_IMUX44_9", - "CFG_CENTER_SW4A2_1", - "CFG_CENTER_ER1BEG1_9", - "CFG_CENTER_WW4A0_0", - "CFG_CENTER_LOGIC_OUTS_B13_10", - "CFG_CENTER_LOGIC_OUTS_B3_7", - "CFG_CENTER_LH3_17", - "CFG_CENTER_IMUX23_13", - "CFG_CENTER_NE4BEG0_5", - "CFG_CENTER_BYP3_12", - "CFG_CENTER_SE4BEG2_14", - "CFG_CENTER_WW2A1_13", - "CFG_CENTER_EE4C3_19", - "CFG_CENTER_SW4END2_5", - "CFG_CENTER_EL1BEG3_8", - "CFG_CENTER_IMUX40_14", - "CFG_CENTER_WW4B2_0", - "CFG_CENTER_IMUX46_10", - "CFG_CENTER_IMUX6_1", - "CFG_CENTER_SE4C1_15", - "CFG_CENTER_EE2A1_11", - "CFG_CENTER_BLOCK_OUTS_B1_5", - "CFG_CENTER_NW4A1_5", - "CFG_CENTER_EE4C0_8", - "CFG_CENTER_SW2A1_1", - "CFG_CENTER_NE2A1_8", - "CFG_CENTER_LOGIC_OUTS_B19_8", - "CFG_CENTER_LH2_7", - "CFG_CENTER_NW4END3_8", - "CFG_CENTER_NE4BEG2_14", - "CFG_CENTER_SW2A2_14", - "CFG_CENTER_EE4C3_6", - "CFG_CENTER_IMUX34_11", - "CFG_CENTER_FAN6_17", - "CFG_CENTER_SE4C0_0", - "CFG_CENTER_NW4END0_17", - "CFG_CENTER_EE4B3_13", - "CFG_CENTER_SE4BEG0_15", - "CFG_CENTER_NE4C0_17", - "CFG_CENTER_LOGIC_OUTS_B7_3", - "CFG_CENTER_EE2BEG1_5", - "CFG_CENTER_IMUX0_13", - "CFG_CENTER_SW4A1_5", - "CFG_CENTER_LOGIC_OUTS_B4_19", - "CFG_CENTER_WW4A2_13", - "CFG_CENTER_EE2BEG0_2", - "CFG_CENTER_IMUX40_3", - "CFG_CENTER_LH1_11", - "CFG_CENTER_NE2A1_3", - "CFG_CENTER_NE4BEG3_0", - "CFG_CENTER_EE4C2_7", - "CFG_CENTER_EE2A2_9", - "CFG_CENTER_IMUX0_6", - "CFG_CENTER_WW4C3_4", - "CFG_CENTER_ER1BEG2_14", - "CFG_CENTER_IMUX34_14", - "CFG_CENTER_NW2A1_13", - "CFG_CENTER_CLK0_3", - "CFG_CENTER_IMUX39_14", - "CFG_CENTER_WW4B2_10", - "CFG_CENTER_FAN4_10", - "CFG_CENTER_EE2A2_2", - "CFG_CENTER_IMUX26_8", - "CFG_CENTER_FAN5_16", - "CFG_CENTER_SE2A0_9", - "CFG_CENTER_WW4C2_0", - "CFG_CENTER_LOGIC_OUTS_B10_2", - "CFG_CENTER_LOGIC_OUTS_B18_13", - "CFG_CENTER_LH2_0", - "CFG_CENTER_IMUX47_13", - "CFG_CENTER_EE4BEG0_6", - "CFG_CENTER_IMUX47_12", - "CFG_CENTER_LH12_4", - "CFG_CENTER_LOGIC_OUTS_B20_17", - "CFG_CENTER_WW4B1_9", - "CFG_CENTER_IMUX46_9", - "CFG_CENTER_NE4BEG0_7", - "CFG_CENTER_EE4A1_1", - "CFG_CENTER_IMUX12_12", - "CFG_CENTER_WW4A3_15", - "CFG_CENTER_IMUX24_14", - "CFG_CENTER_EE4A2_4", - "CFG_CENTER_WW2A2_17", - "CFG_CENTER_IMUX37_14", - "CFG_CENTER_LH10_14", - "CFG_CENTER_WW4END2_2", - "CFG_CENTER_IMUX26_11", - "CFG_CENTER_IMUX26_1", - "CFG_CENTER_WR1END0_0", - "CFG_CENTER_IMUX19_5", - "CFG_CENTER_IMUX27_9", - "CFG_CENTER_BYP5_9", - "CFG_CENTER_EL1BEG1_9", - "CFG_CENTER_IMUX12_13", - "CFG_CENTER_WR1END3_1", - "CFG_CENTER_SW4END2_19", - "CFG_CENTER_FAN2_8", - "CFG_CENTER_IMUX44_8", - "CFG_CENTER_WW4END2_16", - "CFG_CENTER_IMUX18_6", - "CFG_CENTER_IMUX13_10", - "CFG_CENTER_EE4C0_14", - "CFG_CENTER_NW2A3_12", - "CFG_CENTER_SE4BEG0_18", - "CFG_CENTER_IMUX29_11", - "CFG_CENTER_IMUX23_15", - "CFG_CENTER_IMUX22_0", - "CFG_CENTER_NW4END2_0", - "CFG_CENTER_LOGIC_OUTS_B13_2", - "CFG_CENTER_EE4B1_6", - "CFG_CENTER_SW4END3_10", - "CFG_CENTER_NE2A0_2", - "CFG_CENTER_IMUX24_9", - "CFG_CENTER_NE4BEG2_13", - "CFG_CENTER_LH8_4", - "CFG_CENTER_WW4B3_19", - "CFG_CENTER_IMUX14_15", - "CFG_CENTER_BYP3_5", - "CFG_CENTER_BLOCK_OUTS_B3_10", - "CFG_CENTER_BLOCK_OUTS_B0_2", - "CFG_CENTER_IMUX35_17", - "CFG_CENTER_LOGIC_OUTS_B6_5", - "CFG_CENTER_BLOCK_OUTS_B1_6", - "CFG_CENTER_EE4C1_8", - "CFG_CENTER_SE4C3_19", - "CFG_CENTER_IMUX20_17", - "CFG_CENTER_FAN0_12", - "CFG_CENTER_IMUX23_18", - "CFG_CENTER_WW4END2_0", - "CFG_CENTER_EE2BEG2_5", - "CFG_CENTER_NW4A2_17", - "CFG_CENTER_ER1BEG3_7", - "CFG_CENTER_IMUX20_19", - "CFG_CENTER_WW2A2_15", - "CFG_CENTER_IMUX14_17", - "CFG_CENTER_EE4A2_10", - "CFG_CENTER_SW2A3_4", - "CFG_CENTER_IMUX4_1", - "CFG_CENTER_IMUX38_14", - "CFG_CENTER_LH8_6", - "CFG_CENTER_IMUX20_10", - "CFG_CENTER_LOGIC_OUTS_B23_0", - "CFG_CENTER_WL1END2_10", - "CFG_CENTER_LOGIC_OUTS_B6_15", - "CFG_CENTER_EE4A0_9", - "CFG_CENTER_IMUX4_16", - "CFG_CENTER_NW4END1_2", - "CFG_CENTER_SE2A2_8", - "CFG_CENTER_EE4B0_1", - "CFG_CENTER_ER1BEG1_5", - "CFG_CENTER_NW2A3_8", - "CFG_CENTER_EE4BEG3_11", - "CFG_CENTER_IMUX2_18", - "CFG_CENTER_EE4C0_18", - "CFG_CENTER_WW4A0_3", - "CFG_CENTER_LOGIC_OUTS_B12_9", - "CFG_CENTER_EE4C1_13", - "CFG_CENTER_BYP6_2", - "CFG_CENTER_BLOCK_OUTS_B2_11", - "CFG_CENTER_WR1END3_15", - "CFG_CENTER_IMUX9_19", - "CFG_CENTER_LOGIC_OUTS_B9_12", - "CFG_CENTER_IMUX29_19", - "CFG_CENTER_NW4A0_2", - "CFG_CENTER_SW4A3_2", - "CFG_CENTER_IMUX17_1", - "CFG_CENTER_WW2A2_8", - "CFG_CENTER_EL1BEG2_5", - "CFG_CENTER_NW4A3_1", - "CFG_CENTER_LOGIC_OUTS_B6_7", - "CFG_CENTER_IMUX0_2", - "CFG_CENTER_SE2A0_16", - "CFG_CENTER_CLK0_0", - "CFG_CENTER_FAN4_7", - "CFG_CENTER_IMUX23_0", - "CFG_CENTER_LH4_1", - "CFG_CENTER_LOGIC_OUTS_B13_11", - "CFG_CENTER_LH7_14", - "CFG_CENTER_EE4A2_18", - "CFG_CENTER_EE4BEG2_5", - "CFG_CENTER_FAN3_14", - "CFG_CENTER_NE2A1_14", - "CFG_CENTER_IMUX34_3", - "CFG_CENTER_WW4END1_6", - "CFG_CENTER_IMUX31_14", - "CFG_CENTER_EE2A3_16", - "CFG_CENTER_NW4A3_16", - "CFG_CENTER_LH8_19", - "CFG_CENTER_IMUX25_13", - "CFG_CENTER_IMUX15_11", - "CFG_CENTER_SE2A3_17", - "CFG_CENTER_EE4C3_15", - "CFG_CENTER_FAN3_13", - "CFG_CENTER_IMUX44_2", - "CFG_CENTER_WW4C1_3", - "CFG_CENTER_SW4END0_17", - "CFG_CENTER_SW2A1_13", - "CFG_CENTER_EE4C0_17", - "CFG_CENTER_EE2BEG1_17", - "CFG_CENTER_NW4A2_8", - "CFG_CENTER_IMUX0_0", - "CFG_CENTER_LH5_14", - "CFG_CENTER_NE4BEG2_16", - "CFG_CENTER_WW2A3_0", - "CFG_CENTER_IMUX20_12", - "CFG_CENTER_IMUX0_9", - "CFG_CENTER_BLOCK_OUTS_B2_0", - "CFG_CENTER_EE2BEG2_13", - "CFG_CENTER_NW4END2_3", - "CFG_CENTER_IMUX16_14", - "CFG_CENTER_EE4C2_0", - "CFG_CENTER_SW4END0_16", - "CFG_CENTER_LH12_18", - "CFG_CENTER_LOGIC_OUTS_B19_2", - "CFG_CENTER_IMUX19_15", - "CFG_CENTER_LOGIC_OUTS_B19_6", - "CFG_CENTER_IMUX38_13", - "CFG_CENTER_LH3_10", - "CFG_CENTER_LOGIC_OUTS_B10_3", - "CFG_CENTER_WR1END1_2", - "CFG_CENTER_EE4BEG1_14", - "CFG_CENTER_IMUX7_19", - "CFG_CENTER_WR1END0_16", - "CFG_CENTER_LH8_15", - "CFG_CENTER_SE4BEG0_12", - "CFG_CENTER_IMUX5_19", - "CFG_CENTER_LH2_12", - "CFG_CENTER_EE2A2_13", - "CFG_CENTER_ER1BEG3_13", - "CFG_CENTER_IMUX3_10", - "CFG_CENTER_IMUX31_13", - "CFG_CENTER_NE2A3_15", - "CFG_CENTER_SW2A2_16", - "CFG_CENTER_IMUX25_18", - "CFG_CENTER_NE4BEG3_2", - "CFG_CENTER_LOGIC_OUTS_B23_13", - "CFG_CENTER_WW4END0_5", - "CFG_CENTER_SW4A3_18", - "CFG_CENTER_FAN2_2", - "CFG_CENTER_IMUX6_10", - "CFG_CENTER_EE4A2_19", - "CFG_CENTER_SE4C3_12", - "CFG_CENTER_WW4C2_4", - "CFG_CENTER_IMUX46_2", - "CFG_CENTER_EE4BEG1_18", - "CFG_CENTER_SE4BEG3_17", - "CFG_CENTER_LOGIC_OUTS_B4_2", - "CFG_CENTER_NE4BEG2_8", - "CFG_CENTER_LH4_11", - "CFG_CENTER_SW4END3_18", - "CFG_CENTER_IMUX13_19", - "CFG_CENTER_IMUX5_10", - "CFG_CENTER_IMUX18_17", - "CFG_CENTER_EE4C2_14", - "CFG_CENTER_WW2A2_2", - "CFG_CENTER_NW4A3_6", - "CFG_CENTER_WW4END1_15", - "CFG_CENTER_IMUX34_2", - "CFG_CENTER_IMUX18_0", - "CFG_CENTER_IMUX26_4", - "CFG_CENTER_IMUX27_13", - "CFG_CENTER_IMUX27_10", - "CFG_CENTER_SW4A3_9", - "CFG_CENTER_EE4BEG0_3", - "CFG_CENTER_BYP3_17", - "CFG_CENTER_EE4B2_18", - "CFG_CENTER_NW4A1_6", - "CFG_CENTER_EE2A0_19", - "CFG_CENTER_IMUX7_17", - "CFG_CENTER_WW4B0_6", - "CFG_CENTER_SW4A3_7", - "CFG_CENTER_NW4A1_3", - "CFG_CENTER_ER1BEG3_4", - "CFG_CENTER_BYP4_10", - "CFG_CENTER_SE4C1_3", - "CFG_CENTER_WR1END1_14", - "CFG_CENTER_NE4C3_11", - "CFG_CENTER_IMUX33_13", - "CFG_CENTER_WL1END2_19", - "CFG_CENTER_WW4END3_6", - "CFG_CENTER_BLOCK_OUTS_B0_15", - "CFG_CENTER_IMUX42_12", - "CFG_CENTER_CTRL0_7", - "CFG_CENTER_IMUX33_12", - "CFG_CENTER_IMUX5_12", - "CFG_CENTER_NE2A2_10", - "CFG_CENTER_NW4A1_1", - "CFG_CENTER_LOGIC_OUTS_B22_1", - "CFG_CENTER_FAN3_19", - "CFG_CENTER_CLK0_15", - "CFG_CENTER_LOGIC_OUTS_B5_12", - "CFG_CENTER_SW4END0_8", - "CFG_CENTER_SW4END3_13", - "CFG_CENTER_WW4C1_2", - "CFG_CENTER_WW2A0_16", - "CFG_CENTER_EE4B1_17", - "CFG_CENTER_LOGIC_OUTS_B2_12", - "CFG_CENTER_IMUX33_17", - "CFG_CENTER_WR1END1_17", - "CFG_CENTER_NW4END1_4", - "CFG_CENTER_EE4A2_8", - "CFG_CENTER_NW4END2_8", - "CFG_CENTER_LH2_8", - "CFG_CENTER_LOGIC_OUTS_B12_13", - "CFG_CENTER_BYP6_8", - "CFG_CENTER_IMUX32_13", - "CFG_CENTER_BYP1_11", - "CFG_CENTER_LOGIC_OUTS_B5_16", - "CFG_CENTER_IMUX43_9", - "CFG_CENTER_NW4A1_0", - "CFG_CENTER_LOGIC_OUTS_B7_8", - "CFG_CENTER_SW4A1_11", - "CFG_CENTER_CLK0_19", - "CFG_CENTER_LH4_9", - "CFG_CENTER_WW4A1_16", - "CFG_CENTER_SE4C1_19", - "CFG_CENTER_FAN7_15", - "CFG_CENTER_IMUX5_5", - "CFG_CENTER_IMUX20_7", - "CFG_CENTER_NW2A3_18", - "CFG_CENTER_LOGIC_OUTS_B13_6", - "CFG_CENTER_FAN7_0", - "CFG_CENTER_IMUX47_15", - "CFG_CENTER_NE4C0_16", - "CFG_CENTER_BLOCK_OUTS_B0_3", - "CFG_CENTER_IMUX2_8", - "CFG_CENTER_IMUX22_7", - "CFG_CENTER_BYP4_18", - "CFG_CENTER_EE2BEG1_19", - "CFG_CENTER_LOGIC_OUTS_B2_0", - "CFG_CENTER_WW4B2_15", - "CFG_CENTER_EE2A2_5", - "CFG_CENTER_WW4END0_2", - "CFG_CENTER_IMUX38_11", - "CFG_CENTER_EE4C0_2", - "CFG_CENTER_NW2A0_4", - "CFG_CENTER_WL1END0_2", - "CFG_CENTER_BYP2_18", - "CFG_CENTER_IMUX34_6", - "CFG_CENTER_WW4END3_4", - "CFG_CENTER_EL1BEG3_1", - "CFG_CENTER_IMUX12_14", - "CFG_CENTER_WW2END3_12", - "CFG_CENTER_SE4C3_5", - "CFG_CENTER_EE4C3_2", - "CFG_CENTER_BOT_USR_ACCESS_DATA6", - "CFG_CENTER_WR1END1_1", - "CFG_CENTER_NE2A1_1", - "CFG_CENTER_BYP6_19", - "CFG_CENTER_SE4BEG0_19", - "CFG_CENTER_SE2A1_10", - "CFG_CENTER_EE4C3_7", - "CFG_CENTER_WW4B3_8", - "CFG_CENTER_NE4C0_15", - "CFG_CENTER_IMUX33_15", - "CFG_CENTER_IMUX29_5", - "CFG_CENTER_WR1END0_7", - "CFG_CENTER_CTRL0_19", - "CFG_CENTER_NE4BEG3_7", - "CFG_CENTER_ER1BEG3_12", - "CFG_CENTER_EE2A1_17", - "CFG_CENTER_IMUX31_17", - "CFG_CENTER_WW4C2_17", - "CFG_CENTER_LOGIC_OUTS_B16_12", - "CFG_CENTER_WW2END3_13", - "CFG_CENTER_BYP5_11", - "CFG_CENTER_WW4C2_3", - "CFG_CENTER_EE2A1_10", - "CFG_CENTER_EL1BEG3_13", - "CFG_CENTER_WW4END2_8", - "CFG_CENTER_LOGIC_OUTS_B15_3", - "CFG_CENTER_IMUX2_9", - "CFG_CENTER_IMUX0_7", - "CFG_CENTER_EE2A3_5", - "CFG_CENTER_NE4C0_3", - "CFG_CENTER_BYP5_14", - "CFG_CENTER_BYP4_0", - "CFG_CENTER_WW4A0_9", - "CFG_CENTER_SE4C2_3", - "CFG_CENTER_BYP0_4", - "CFG_CENTER_IMUX33_14", - "CFG_CENTER_LOGIC_OUTS_B19_18", - "CFG_CENTER_SE4C3_14", - "CFG_CENTER_EL1BEG3_5", - "CFG_CENTER_NW2A1_8", - "CFG_CENTER_LOGIC_OUTS_B13_16", - "CFG_CENTER_WL1END0_7", - "CFG_CENTER_BYP7_9", - "CFG_CENTER_IMUX8_0", - "CFG_CENTER_EE4C1_6", - "CFG_CENTER_EE4BEG3_8", - "CFG_CENTER_IMUX31_2", - "CFG_CENTER_LOGIC_OUTS_B23_7", - "CFG_CENTER_WW4END3_1", - "CFG_CENTER_IMUX29_12", - "CFG_CENTER_LOGIC_OUTS_B1_2", - "CFG_CENTER_WR1END1_13", - "CFG_CENTER_BYP6_18", - "CFG_CENTER_NE4BEG2_17", - "CFG_CENTER_WW4B0_3", - "CFG_CENTER_IMUX7_12", - "CFG_CENTER_NE4C2_6", - "CFG_CENTER_IMUX4_14", - "CFG_CENTER_IMUX5_13", - "CFG_CENTER_EE4BEG0_13", - "CFG_CENTER_LOGIC_OUTS_B0_14", - "CFG_CENTER_NE2A2_19", - "CFG_CENTER_SE4BEG3_16" - ], - "sites": [], "pips": { - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA11->CFG_CENTER_LOGIC_OUTS_B22_19": { + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA14->CFG_CENTER_LOGIC_OUTS_B11_19": { "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_19", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA14", "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA11", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA10->CFG_CENTER_LOGIC_OUTS_B21_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_19", - "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_19" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA3->CFG_CENTER_LOGIC_OUTS_B14_19": { "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_19", - "is_directional": "1", "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA3", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA4->CFG_CENTER_LOGIC_OUTS_B15_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_19", "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA4", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA7->CFG_CENTER_LOGIC_OUTS_B18_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_19", - "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA7", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA13->CFG_CENTER_LOGIC_OUTS_B10_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_19", - "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA13", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA5->CFG_CENTER_LOGIC_OUTS_B16_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_19", - "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA5", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA9->CFG_CENTER_LOGIC_OUTS_B20_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_19", - "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA9", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA14->CFG_CENTER_LOGIC_OUTS_B11_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_19", - "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA14", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA12->CFG_CENTER_LOGIC_OUTS_B23_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_19", - "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA12", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA2->CFG_CENTER_LOGIC_OUTS_B13_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_19", - "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA2", - "is_pseudo": "0" - }, - "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA8->CFG_CENTER_LOGIC_OUTS_B19_19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_19", - "is_directional": "1", - "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_19" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA6->CFG_CENTER_LOGIC_OUTS_B17_19": { "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_19", - "is_directional": "1", "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA6", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA11->CFG_CENTER_LOGIC_OUTS_B22_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA12->CFG_CENTER_LOGIC_OUTS_B23_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA8->CFG_CENTER_LOGIC_OUTS_B19_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA7->CFG_CENTER_LOGIC_OUTS_B18_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA5->CFG_CENTER_LOGIC_OUTS_B16_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA4->CFG_CENTER_LOGIC_OUTS_B15_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA13->CFG_CENTER_LOGIC_OUTS_B10_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA9->CFG_CENTER_LOGIC_OUTS_B20_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA2->CFG_CENTER_LOGIC_OUTS_B13_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_19" + }, + "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA10->CFG_CENTER_LOGIC_OUTS_B21_19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_19" } }, - "tile_type": "CFG_CENTER_BOT" + "wires": [ + "CFG_CENTER_SW2A3_13", + "CFG_CENTER_LH7_7", + "CFG_CENTER_EE4A1_16", + "CFG_CENTER_FAN2_8", + "CFG_CENTER_IMUX14_7", + "CFG_CENTER_NW4A0_2", + "CFG_CENTER_IMUX8_17", + "CFG_CENTER_FAN6_15", + "CFG_CENTER_FAN3_16", + "CFG_CENTER_NE4C0_3", + "CFG_CENTER_LOGIC_OUTS_B5_13", + "CFG_CENTER_EE4B2_0", + "CFG_CENTER_IMUX17_11", + "CFG_CENTER_NW4A3_0", + "CFG_CENTER_IMUX12_5", + "CFG_CENTER_LOGIC_OUTS_B22_0", + "CFG_CENTER_WR1END1_6", + "CFG_CENTER_ER1BEG3_5", + "CFG_CENTER_FAN3_17", + "CFG_CENTER_EE4A3_9", + "CFG_CENTER_IMUX18_6", + "CFG_CENTER_IMUX34_5", + "CFG_CENTER_NE4BEG3_9", + "CFG_CENTER_IMUX37_19", + "CFG_CENTER_EE2BEG2_14", + "CFG_CENTER_LH5_14", + "CFG_CENTER_SW4END3_4", + "CFG_CENTER_EE4A3_16", + "CFG_CENTER_NE2A1_9", + "CFG_CENTER_WR1END2_4", + "CFG_CENTER_SW4A3_17", + "CFG_CENTER_IMUX13_0", + "CFG_CENTER_SW4END0_16", + "CFG_CENTER_WR1END1_11", + "CFG_CENTER_EE2A3_14", + "CFG_CENTER_EE2BEG0_1", + "CFG_CENTER_IMUX1_1", + "CFG_CENTER_EE4A0_16", + "CFG_CENTER_WR1END0_0", + "CFG_CENTER_IMUX34_13", + "CFG_CENTER_FAN5_14", + "CFG_CENTER_SW2A0_19", + "CFG_CENTER_CLK1_5", + "CFG_CENTER_WW2END2_8", + "CFG_CENTER_SE4BEG2_5", + "CFG_CENTER_WW2A2_14", + "CFG_CENTER_EE4A2_14", + "CFG_CENTER_NW4END2_6", + "CFG_CENTER_IMUX45_18", + "CFG_CENTER_FAN2_16", + "CFG_CENTER_ER1BEG3_12", + "CFG_CENTER_EE4BEG0_6", + "CFG_CENTER_NE4BEG2_19", + "CFG_CENTER_WW4C0_6", + "CFG_CENTER_FAN2_11", + "CFG_CENTER_ER1BEG1_16", + "CFG_CENTER_SE4BEG2_17", + "CFG_CENTER_ER1BEG1_18", + "CFG_CENTER_NE4C0_14", + "CFG_CENTER_CTRL1_0", + "CFG_CENTER_ER1BEG2_8", + "CFG_CENTER_WR1END0_18", + "CFG_CENTER_EE2BEG1_0", + "CFG_CENTER_IMUX41_3", + "CFG_CENTER_LH11_0", + "CFG_CENTER_IMUX36_14", + "CFG_CENTER_SE4C3_4", + "CFG_CENTER_WW2END0_5", + "CFG_CENTER_IMUX6_1", + "CFG_CENTER_WW2END3_7", + "CFG_CENTER_SE4C0_1", + "CFG_CENTER_WR1END3_0", + "CFG_CENTER_WW4END2_15", + "CFG_CENTER_NE2A1_18", + "CFG_CENTER_WW4C1_12", + "CFG_CENTER_BLOCK_OUTS_B1_11", + "CFG_CENTER_NW2A1_10", + "CFG_CENTER_WW2A3_14", + "CFG_CENTER_IMUX45_17", + "CFG_CENTER_NW4END1_7", + "CFG_CENTER_IMUX0_7", + "CFG_CENTER_WW4A2_3", + "CFG_CENTER_EE4B0_2", + "CFG_CENTER_SW4END2_14", + "CFG_CENTER_IMUX39_10", + "CFG_CENTER_LOGIC_OUTS_B0_17", + "CFG_CENTER_EE4C1_16", + "CFG_CENTER_LH7_6", + "CFG_CENTER_EE4B3_16", + "CFG_CENTER_FAN0_9", + "CFG_CENTER_BYP2_11", + "CFG_CENTER_IMUX15_15", + "CFG_CENTER_NE4C1_14", + "CFG_CENTER_EE2A0_1", + "CFG_CENTER_BYP3_5", + "CFG_CENTER_CTRL0_18", + "CFG_CENTER_WW4B2_5", + "CFG_CENTER_LH8_1", + "CFG_CENTER_EE4B3_15", + "CFG_CENTER_BYP5_12", + "CFG_CENTER_IMUX43_18", + "CFG_CENTER_NW4A3_16", + "CFG_CENTER_BLOCK_OUTS_B3_3", + "CFG_CENTER_EE4BEG0_5", + "CFG_CENTER_LOGIC_OUTS_B4_2", + "CFG_CENTER_WW2A0_12", + "CFG_CENTER_WL1END0_18", + "CFG_CENTER_LH11_19", + "CFG_CENTER_IMUX32_13", + "CFG_CENTER_BYP3_0", + "CFG_CENTER_IMUX31_8", + "CFG_CENTER_LOGIC_OUTS_B11_13", + "CFG_CENTER_IMUX46_17", + "CFG_CENTER_CTRL0_13", + "CFG_CENTER_LOGIC_OUTS_B22_18", + "CFG_CENTER_LOGIC_OUTS_B18_5", + "CFG_CENTER_LH6_0", + "CFG_CENTER_SW4END2_1", + "CFG_CENTER_EL1BEG0_11", + "CFG_CENTER_EE4A3_10", + "CFG_CENTER_LOGIC_OUTS_B10_16", + "CFG_CENTER_WW4A2_11", + "CFG_CENTER_WW4A2_17", + "CFG_CENTER_WL1END0_15", + "CFG_CENTER_NW2A0_10", + "CFG_CENTER_WW2END1_17", + "CFG_CENTER_FAN0_17", + "CFG_CENTER_LH10_10", + "CFG_CENTER_NE4C1_2", + "CFG_CENTER_ER1BEG0_9", + "CFG_CENTER_IMUX14_19", + "CFG_CENTER_SW2A1_11", + "CFG_CENTER_EE4C3_2", + "CFG_CENTER_WW2END0_2", + "CFG_CENTER_NE2A2_14", + "CFG_CENTER_WW4END0_7", + "CFG_CENTER_SE4C2_17", + "CFG_CENTER_NE2A1_16", + "CFG_CENTER_SE4BEG1_1", + "CFG_CENTER_SW4END0_9", + "CFG_CENTER_LH10_19", + "CFG_CENTER_WR1END1_4", + "CFG_CENTER_LH11_15", + "CFG_CENTER_WR1END3_15", + "CFG_CENTER_NW4END1_1", + "CFG_CENTER_SE2A3_19", + "CFG_CENTER_SE4C3_6", + "CFG_CENTER_BYP6_17", + "CFG_CENTER_NE2A0_14", + "CFG_CENTER_LH6_5", + "CFG_CENTER_LH6_4", + "CFG_CENTER_BYP5_16", + "CFG_CENTER_WW4B2_4", + "CFG_CENTER_LH5_10", + "CFG_CENTER_BYP1_0", + "CFG_CENTER_WW4END0_12", + "CFG_CENTER_EE4A1_2", + "CFG_CENTER_LH10_18", + "CFG_CENTER_WW4END2_6", + "CFG_CENTER_NE4BEG2_12", + "CFG_CENTER_WL1END2_2", + "CFG_CENTER_IMUX5_3", + "CFG_CENTER_LOGIC_OUTS_B20_11", + "CFG_CENTER_EE4C1_18", + "CFG_CENTER_SW4A1_0", + "CFG_CENTER_LH9_14", + "CFG_CENTER_WW4A1_8", + "CFG_CENTER_SE4C3_19", + "CFG_CENTER_LH8_5", + "CFG_CENTER_IMUX37_1", + "CFG_CENTER_LH2_4", + "CFG_CENTER_IMUX42_12", + "CFG_CENTER_IMUX28_19", + "CFG_CENTER_EE4A1_13", + "CFG_CENTER_WW4A1_15", + "CFG_CENTER_IMUX40_5", + "CFG_CENTER_WW4END0_0", + "CFG_CENTER_IMUX9_13", + "CFG_CENTER_CLK1_2", + "CFG_CENTER_WW4B3_10", + "CFG_CENTER_NE4BEG1_11", + "CFG_CENTER_LH7_16", + "CFG_CENTER_IMUX36_16", + "CFG_CENTER_BLOCK_OUTS_B0_9", + "CFG_CENTER_IMUX6_7", + "CFG_CENTER_IMUX20_5", + "CFG_CENTER_WW2END2_17", + "CFG_CENTER_WL1END2_3", + "CFG_CENTER_FAN4_10", + "CFG_CENTER_NW4A3_10", + "CFG_CENTER_LH4_6", + "CFG_CENTER_WL1END2_7", + "CFG_CENTER_LOGIC_OUTS_B10_19", + "CFG_CENTER_LOGIC_OUTS_B10_10", + "CFG_CENTER_SW2A0_3", + "CFG_CENTER_LH8_7", + "CFG_CENTER_IMUX32_0", + "CFG_CENTER_LOGIC_OUTS_B0_5", + "CFG_CENTER_BYP4_16", + "CFG_CENTER_WW2A1_19", + "CFG_CENTER_SE4C3_1", + "CFG_CENTER_IMUX5_18", + "CFG_CENTER_LOGIC_OUTS_B19_18", + "CFG_CENTER_BYP5_1", + "CFG_CENTER_EE4B1_11", + "CFG_CENTER_LOGIC_OUTS_B18_14", + "CFG_CENTER_LOGIC_OUTS_B2_12", + "CFG_CENTER_WW4B2_9", + "CFG_CENTER_BOT_USR_ACCESS_DATA3", + "CFG_CENTER_LH3_6", + "CFG_CENTER_LOGIC_OUTS_B6_0", + "CFG_CENTER_IMUX41_17", + "CFG_CENTER_EE2A2_12", + "CFG_CENTER_EE4A0_7", + "CFG_CENTER_IMUX13_17", + "CFG_CENTER_SE4BEG1_14", + "CFG_CENTER_WW4END1_3", + "CFG_CENTER_BOT_USR_ACCESS_DATA12", + "CFG_CENTER_SW4A3_3", + "CFG_CENTER_IMUX34_1", + "CFG_CENTER_ER1BEG2_1", + "CFG_CENTER_IMUX39_8", + "CFG_CENTER_EE2BEG0_6", + "CFG_CENTER_LH3_8", + "CFG_CENTER_WW2END0_15", + "CFG_CENTER_EE2A1_0", + "CFG_CENTER_IMUX17_0", + "CFG_CENTER_LOGIC_OUTS_B5_12", + "CFG_CENTER_WL1END2_0", + "CFG_CENTER_NW4END2_4", + "CFG_CENTER_IMUX29_12", + "CFG_CENTER_ER1BEG2_14", + "CFG_CENTER_SW4A3_4", + "CFG_CENTER_WW2A2_8", + "CFG_CENTER_EE4A2_6", + "CFG_CENTER_FAN0_12", + "CFG_CENTER_LOGIC_OUTS_B5_0", + "CFG_CENTER_EE2BEG0_11", + "CFG_CENTER_IMUX41_9", + "CFG_CENTER_IMUX22_14", + "CFG_CENTER_SW2A2_13", + "CFG_CENTER_IMUX12_2", + "CFG_CENTER_IMUX30_6", + "CFG_CENTER_IMUX19_13", + "CFG_CENTER_LH8_10", + "CFG_CENTER_NW2A0_17", + "CFG_CENTER_EL1BEG2_4", + "CFG_CENTER_WW2A2_5", + "CFG_CENTER_WW2A3_9", + "CFG_CENTER_IMUX35_3", + "CFG_CENTER_IMUX29_0", + "CFG_CENTER_SW4A1_7", + "CFG_CENTER_LOGIC_OUTS_B9_2", + "CFG_CENTER_IMUX3_12", + "CFG_CENTER_EE2BEG1_1", + "CFG_CENTER_EE4A2_11", + "CFG_CENTER_SE4C3_8", + "CFG_CENTER_LH1_7", + "CFG_CENTER_WW4C1_11", + "CFG_CENTER_SW2A0_12", + "CFG_CENTER_SE4C2_18", + "CFG_CENTER_LOGIC_OUTS_B15_8", + "CFG_CENTER_IMUX11_9", + "CFG_CENTER_IMUX19_19", + "CFG_CENTER_BYP5_19", + "CFG_CENTER_BLOCK_OUTS_B1_10", + "CFG_CENTER_LOGIC_OUTS_B19_3", + "CFG_CENTER_NE4C1_15", + "CFG_CENTER_LOGIC_OUTS_B2_14", + "CFG_CENTER_SE4C0_19", + "CFG_CENTER_SE2A3_4", + "CFG_CENTER_IMUX29_11", + "CFG_CENTER_EE4BEG2_1", + "CFG_CENTER_SW2A2_12", + "CFG_CENTER_SE4C0_3", + "CFG_CENTER_EE2A3_16", + "CFG_CENTER_IMUX6_10", + "CFG_CENTER_BYP6_11", + "CFG_CENTER_IMUX36_11", + "CFG_CENTER_NW4END1_9", + "CFG_CENTER_SW4A0_9", + "CFG_CENTER_NW4END2_19", + "CFG_CENTER_EE4C0_19", + "CFG_CENTER_EE4C3_13", + "CFG_CENTER_SE4C2_7", + "CFG_CENTER_SW4END2_10", + "CFG_CENTER_WW4C0_9", + "CFG_CENTER_WW4B0_11", + "CFG_CENTER_BOT_USR_ACCESS_DATA4", + "CFG_CENTER_EE2BEG3_3", + "CFG_CENTER_LOGIC_OUTS_B7_16", + "CFG_CENTER_WW4B0_15", + "CFG_CENTER_SE4C0_12", + "CFG_CENTER_FAN7_0", + "CFG_CENTER_WW4A3_9", + "CFG_CENTER_WW4C1_1", + "CFG_CENTER_FAN3_19", + "CFG_CENTER_WW4C2_1", + "CFG_CENTER_LOGIC_OUTS_B19_15", + "CFG_CENTER_SE2A1_15", + "CFG_CENTER_LOGIC_OUTS_B9_8", + "CFG_CENTER_WR1END3_11", + "CFG_CENTER_FAN2_4", + "CFG_CENTER_FAN5_5", + "CFG_CENTER_NE2A3_7", + "CFG_CENTER_EE4C3_7", + "CFG_CENTER_IMUX1_2", + "CFG_CENTER_IMUX6_2", + "CFG_CENTER_EE2A0_14", + "CFG_CENTER_EE4C3_11", + "CFG_CENTER_NE2A0_5", + "CFG_CENTER_SE4BEG0_5", + "CFG_CENTER_EE4C1_6", + "CFG_CENTER_FAN7_5", + "CFG_CENTER_BLOCK_OUTS_B1_9", + "CFG_CENTER_CTRL1_18", + "CFG_CENTER_EE2A0_2", + "CFG_CENTER_IMUX15_2", + "CFG_CENTER_NE2A1_14", + "CFG_CENTER_NE4C3_11", + "CFG_CENTER_FAN7_6", + "CFG_CENTER_IMUX39_19", + "CFG_CENTER_EE4B1_7", + "CFG_CENTER_CLK0_11", + "CFG_CENTER_LOGIC_OUTS_B15_17", + "CFG_CENTER_NE2A3_16", + "CFG_CENTER_LOGIC_OUTS_B22_7", + "CFG_CENTER_EE4C3_14", + "CFG_CENTER_WL1END3_0", + "CFG_CENTER_WW2END2_10", + "CFG_CENTER_WW4B3_15", + "CFG_CENTER_CTRL1_14", + "CFG_CENTER_LOGIC_OUTS_B7_15", + "CFG_CENTER_WL1END1_18", + "CFG_CENTER_NE2A1_4", + "CFG_CENTER_WR1END3_16", + "CFG_CENTER_IMUX46_7", + "CFG_CENTER_IMUX19_17", + "CFG_CENTER_WL1END2_17", + "CFG_CENTER_IMUX47_7", + "CFG_CENTER_CTRL1_12", + "CFG_CENTER_NE2A3_19", + "CFG_CENTER_EL1BEG2_14", + "CFG_CENTER_SE2A2_14", + "CFG_CENTER_NW4END0_19", + "CFG_CENTER_NW4END1_14", + "CFG_CENTER_SW4END2_9", + "CFG_CENTER_IMUX0_6", + "CFG_CENTER_EE4B1_16", + "CFG_CENTER_EE4A0_18", + "CFG_CENTER_SE2A1_19", + "CFG_CENTER_FAN6_18", + "CFG_CENTER_IMUX31_3", + "CFG_CENTER_LH4_7", + "CFG_CENTER_EE2BEG1_19", + "CFG_CENTER_SE4C2_8", + "CFG_CENTER_SW4END1_17", + "CFG_CENTER_NW4END3_1", + "CFG_CENTER_IMUX23_13", + "CFG_CENTER_LOGIC_OUTS_B13_11", + "CFG_CENTER_LH9_17", + "CFG_CENTER_EE4B3_0", + "CFG_CENTER_NE4C0_2", + "CFG_CENTER_IMUX37_15", + "CFG_CENTER_SE4BEG1_3", + "CFG_CENTER_IMUX7_18", + "CFG_CENTER_IMUX15_18", + "CFG_CENTER_IMUX43_13", + "CFG_CENTER_IMUX21_19", + "CFG_CENTER_SE4C1_15", + "CFG_CENTER_SW4END1_18", + "CFG_CENTER_IMUX43_16", + "CFG_CENTER_EE4BEG3_0", + "CFG_CENTER_LOGIC_OUTS_B19_7", + "CFG_CENTER_IMUX42_14", + "CFG_CENTER_NW4END1_15", + "CFG_CENTER_ER1BEG3_11", + "CFG_CENTER_EE4BEG1_5", + "CFG_CENTER_IMUX25_10", + "CFG_CENTER_BYP2_19", + "CFG_CENTER_NW2A1_19", + "CFG_CENTER_EE2BEG3_13", + "CFG_CENTER_NW2A3_16", + "CFG_CENTER_IMUX25_2", + "CFG_CENTER_IMUX4_1", + "CFG_CENTER_LH9_2", + "CFG_CENTER_SW2A2_3", + "CFG_CENTER_WW4A3_18", + "CFG_CENTER_LOGIC_OUTS_B8_10", + "CFG_CENTER_SE4C1_19", + "CFG_CENTER_IMUX26_7", + "CFG_CENTER_IMUX35_18", + "CFG_CENTER_LOGIC_OUTS_B15_1", + "CFG_CENTER_LOGIC_OUTS_B21_0", + "CFG_CENTER_IMUX10_6", + "CFG_CENTER_BYP5_2", + "CFG_CENTER_IMUX41_11", + "CFG_CENTER_WW4B0_0", + "CFG_CENTER_IMUX29_5", + "CFG_CENTER_NE4BEG0_19", + "CFG_CENTER_LH4_11", + "CFG_CENTER_SW2A2_18", + "CFG_CENTER_WR1END0_3", + "CFG_CENTER_LOGIC_OUTS_B16_4", + "CFG_CENTER_NW2A3_13", + "CFG_CENTER_WW4A1_16", + "CFG_CENTER_EE2BEG2_19", + "CFG_CENTER_SE2A1_9", + "CFG_CENTER_LOGIC_OUTS_B5_5", + "CFG_CENTER_WL1END1_6", + "CFG_CENTER_FAN7_3", + "CFG_CENTER_WW2A2_7", + "CFG_CENTER_SE4BEG2_14", + "CFG_CENTER_LOGIC_OUTS_B0_10", + "CFG_CENTER_IMUX4_2", + "CFG_CENTER_EL1BEG3_2", + "CFG_CENTER_BLOCK_OUTS_B3_6", + "CFG_CENTER_LOGIC_OUTS_B0_14", + "CFG_CENTER_IMUX13_16", + "CFG_CENTER_IMUX15_19", + "CFG_CENTER_WW2A3_4", + "CFG_CENTER_IMUX10_15", + "CFG_CENTER_NE2A1_2", + "CFG_CENTER_WW4B0_5", + "CFG_CENTER_IMUX7_1", + "CFG_CENTER_IMUX26_15", + "CFG_CENTER_WW2A3_15", + "CFG_CENTER_WW4A3_5", + "CFG_CENTER_BYP5_6", + "CFG_CENTER_IMUX0_16", + "CFG_CENTER_LOGIC_OUTS_B10_7", + "CFG_CENTER_NE4BEG1_7", + "CFG_CENTER_IMUX18_8", + "CFG_CENTER_EE4A0_3", + "CFG_CENTER_BLOCK_OUTS_B2_3", + "CFG_CENTER_SW4END3_14", + "CFG_CENTER_WW4C2_7", + "CFG_CENTER_LOGIC_OUTS_B22_6", + "CFG_CENTER_WL1END2_16", + "CFG_CENTER_IMUX25_5", + "CFG_CENTER_NW4END2_12", + "CFG_CENTER_SE4C1_3", + "CFG_CENTER_LOGIC_OUTS_B9_1", + "CFG_CENTER_NE4BEG1_12", + "CFG_CENTER_LOGIC_OUTS_B1_10", + "CFG_CENTER_IMUX29_15", + "CFG_CENTER_SW2A2_10", + "CFG_CENTER_SE4C2_12", + "CFG_CENTER_IMUX24_7", + "CFG_CENTER_IMUX35_1", + "CFG_CENTER_IMUX23_18", + "CFG_CENTER_EE4C0_2", + "CFG_CENTER_WW4B1_0", + "CFG_CENTER_WR1END2_5", + "CFG_CENTER_FAN1_19", + "CFG_CENTER_BYP2_6", + "CFG_CENTER_NW2A3_9", + "CFG_CENTER_LOGIC_OUTS_B20_6", + "CFG_CENTER_WW2A2_18", + "CFG_CENTER_FAN1_16", + "CFG_CENTER_IMUX20_0", + "CFG_CENTER_IMUX15_3", + "CFG_CENTER_WW4B2_6", + "CFG_CENTER_EE4BEG3_18", + "CFG_CENTER_SE2A2_7", + "CFG_CENTER_NE4C1_6", + "CFG_CENTER_IMUX46_16", + "CFG_CENTER_LOGIC_OUTS_B21_3", + "CFG_CENTER_LH3_7", + "CFG_CENTER_IMUX12_3", + "CFG_CENTER_LOGIC_OUTS_B5_14", + "CFG_CENTER_WW2A1_4", + "CFG_CENTER_LH10_7", + "CFG_CENTER_EE2A2_4", + "CFG_CENTER_NW4A2_12", + "CFG_CENTER_NW2A3_7", + "CFG_CENTER_IMUX18_19", + "CFG_CENTER_NW2A0_14", + "CFG_CENTER_BYP4_7", + "CFG_CENTER_WW2END2_12", + "CFG_CENTER_LH11_18", + "CFG_CENTER_EL1BEG0_1", + "CFG_CENTER_EL1BEG0_14", + "CFG_CENTER_SE4BEG0_19", + "CFG_CENTER_SW2A1_19", + "CFG_CENTER_FAN7_16", + "CFG_CENTER_NE4C0_4", + "CFG_CENTER_WL1END3_13", + "CFG_CENTER_NE4BEG3_12", + "CFG_CENTER_CTRL1_2", + "CFG_CENTER_LOGIC_OUTS_B23_7", + "CFG_CENTER_BLOCK_OUTS_B3_13", + "CFG_CENTER_FAN4_18", + "CFG_CENTER_EL1BEG2_18", + "CFG_CENTER_LOGIC_OUTS_B7_10", + "CFG_CENTER_IMUX31_0", + "CFG_CENTER_IMUX26_10", + "CFG_CENTER_IMUX21_16", + "CFG_CENTER_WW4C1_8", + "CFG_CENTER_LOGIC_OUTS_B13_2", + "CFG_CENTER_SW4A0_2", + "CFG_CENTER_WW4C0_0", + "CFG_CENTER_IMUX17_14", + "CFG_CENTER_LOGIC_OUTS_B15_10", + "CFG_CENTER_IMUX38_10", + "CFG_CENTER_BOT_USR_ACCESS_DATA13", + "CFG_CENTER_IMUX41_1", + "CFG_CENTER_EE4A2_15", + "CFG_CENTER_IMUX16_1", + "CFG_CENTER_IMUX14_1", + "CFG_CENTER_IMUX30_7", + "CFG_CENTER_LOGIC_OUTS_B11_18", + "CFG_CENTER_NE4C2_19", + "CFG_CENTER_WW2A0_16", + "CFG_CENTER_LH4_1", + "CFG_CENTER_SW4A1_8", + "CFG_CENTER_WW2A3_18", + "CFG_CENTER_FAN0_10", + "CFG_CENTER_EE4C2_7", + "CFG_CENTER_FAN1_0", + "CFG_CENTER_BLOCK_OUTS_B2_16", + "CFG_CENTER_WW4A0_13", + "CFG_CENTER_EE4B2_18", + "CFG_CENTER_LOGIC_OUTS_B9_6", + "CFG_CENTER_SE4C0_8", + "CFG_CENTER_SE4BEG3_8", + "CFG_CENTER_EE4B3_11", + "CFG_CENTER_ER1BEG3_0", + "CFG_CENTER_IMUX37_8", + "CFG_CENTER_WW4C3_3", + "CFG_CENTER_NW2A2_0", + "CFG_CENTER_IMUX3_19", + "CFG_CENTER_EE4A1_1", + "CFG_CENTER_WW4B3_5", + "CFG_CENTER_WL1END2_4", + "CFG_CENTER_WW2END0_6", + "CFG_CENTER_WW4END2_10", + "CFG_CENTER_BYP6_9", + "CFG_CENTER_LH10_6", + "CFG_CENTER_LH2_0", + "CFG_CENTER_IMUX35_6", + "CFG_CENTER_SW2A1_16", + "CFG_CENTER_IMUX46_2", + "CFG_CENTER_BYP6_6", + "CFG_CENTER_WW4END2_7", + "CFG_CENTER_WW4END3_10", + "CFG_CENTER_WR1END0_4", + "CFG_CENTER_IMUX46_12", + "CFG_CENTER_EE4C0_1", + "CFG_CENTER_NW4A2_3", + "CFG_CENTER_WW2END1_14", + "CFG_CENTER_IMUX44_14", + "CFG_CENTER_SW2A2_9", + "CFG_CENTER_NW4A1_6", + "CFG_CENTER_WW4C0_8", + "CFG_CENTER_LOGIC_OUTS_B23_16", + "CFG_CENTER_SE2A1_6", + "CFG_CENTER_IMUX13_7", + "CFG_CENTER_IMUX39_18", + "CFG_CENTER_LOGIC_OUTS_B19_8", + "CFG_CENTER_IMUX14_10", + "CFG_CENTER_SE2A0_8", + "CFG_CENTER_NE4C0_16", + "CFG_CENTER_LOGIC_OUTS_B11_12", + "CFG_CENTER_WW4A3_19", + "CFG_CENTER_WW4B1_7", + "CFG_CENTER_FAN5_0", + "CFG_CENTER_CLK0_9", + "CFG_CENTER_IMUX45_1", + "CFG_CENTER_WW2END2_14", + "CFG_CENTER_IMUX42_7", + "CFG_CENTER_LOGIC_OUTS_B12_14", + "CFG_CENTER_WW2END0_8", + "CFG_CENTER_WL1END2_13", + "CFG_CENTER_IMUX38_1", + "CFG_CENTER_NE4C3_13", + "CFG_CENTER_WL1END1_7", + "CFG_CENTER_FAN7_8", + "CFG_CENTER_NW2A2_4", + "CFG_CENTER_WW2END0_16", + "CFG_CENTER_SE4C1_18", + "CFG_CENTER_LOGIC_OUTS_B4_9", + "CFG_CENTER_EE4BEG3_11", + "CFG_CENTER_IMUX2_16", + "CFG_CENTER_IMUX27_19", + "CFG_CENTER_WW4A2_1", + "CFG_CENTER_EE2BEG1_18", + "CFG_CENTER_NW4END3_12", + "CFG_CENTER_SE2A2_2", + "CFG_CENTER_ER1BEG2_13", + "CFG_CENTER_NE2A3_13", + "CFG_CENTER_SW2A2_11", + "CFG_CENTER_NE4BEG3_7", + "CFG_CENTER_SE2A0_5", + "CFG_CENTER_NE2A2_19", + "CFG_CENTER_IMUX37_13", + "CFG_CENTER_LH8_8", + "CFG_CENTER_WW4B1_3", + "CFG_CENTER_SE2A2_1", + "CFG_CENTER_EE2A0_5", + "CFG_CENTER_EE2A1_2", + "CFG_CENTER_IMUX4_16", + "CFG_CENTER_SW2A1_4", + "CFG_CENTER_FAN6_8", + "CFG_CENTER_IMUX25_9", + "CFG_CENTER_WW4A2_19", + "CFG_CENTER_WL1END0_2", + "CFG_CENTER_WW4B3_6", + "CFG_CENTER_EL1BEG0_3", + "CFG_CENTER_FAN3_0", + "CFG_CENTER_WW4B0_12", + "CFG_CENTER_NW4END0_10", + "CFG_CENTER_WW4B2_14", + "CFG_CENTER_FAN2_6", + "CFG_CENTER_WL1END0_7", + "CFG_CENTER_FAN6_5", + "CFG_CENTER_IMUX19_0", + "CFG_CENTER_BOT_USR_ACCESS_DATA9", + "CFG_CENTER_SW2A3_1", + "CFG_CENTER_EE2A1_14", + "CFG_CENTER_BLOCK_OUTS_B0_4", + "CFG_CENTER_EE4BEG0_8", + "CFG_CENTER_NE4BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B18_16", + "CFG_CENTER_IMUX31_7", + "CFG_CENTER_NW4END3_6", + "CFG_CENTER_SE4BEG3_0", + "CFG_CENTER_IMUX12_18", + "CFG_CENTER_WW2A0_0", + "CFG_CENTER_IMUX46_15", + "CFG_CENTER_LOGIC_OUTS_B0_11", + "CFG_CENTER_LOGIC_OUTS_B11_8", + "CFG_CENTER_LH7_13", + "CFG_CENTER_SW2A2_8", + "CFG_CENTER_BYP5_8", + "CFG_CENTER_IMUX40_3", + "CFG_CENTER_IMUX34_16", + "CFG_CENTER_LOGIC_OUTS_B1_3", + "CFG_CENTER_NW4A3_11", + "CFG_CENTER_EE4B3_3", + "CFG_CENTER_IMUX25_7", + "CFG_CENTER_FAN7_18", + "CFG_CENTER_NE4C0_12", + "CFG_CENTER_IMUX21_3", + "CFG_CENTER_EE4BEG1_3", + "CFG_CENTER_BYP6_19", + "CFG_CENTER_SW2A1_18", + "CFG_CENTER_LH6_9", + "CFG_CENTER_WW2A2_19", + "CFG_CENTER_EE4C3_16", + "CFG_CENTER_LH4_12", + "CFG_CENTER_SW4A0_8", + "CFG_CENTER_WW2END0_10", + "CFG_CENTER_SW4END2_16", + "CFG_CENTER_SW4END1_14", + "CFG_CENTER_EE4B0_6", + "CFG_CENTER_SW2A3_17", + "CFG_CENTER_SW4END0_8", + "CFG_CENTER_ER1BEG0_17", + "CFG_CENTER_EE4C1_10", + "CFG_CENTER_IMUX14_6", + "CFG_CENTER_SE4C0_13", + "CFG_CENTER_SE4BEG2_7", + "CFG_CENTER_LH1_0", + "CFG_CENTER_IMUX29_4", + "CFG_CENTER_WR1END1_1", + "CFG_CENTER_WW2A3_6", + "CFG_CENTER_NE4BEG0_10", + "CFG_CENTER_LOGIC_OUTS_B17_6", + "CFG_CENTER_EE4C2_3", + "CFG_CENTER_NW2A0_16", + "CFG_CENTER_LOGIC_OUTS_B20_0", + "CFG_CENTER_NW4A0_14", + "CFG_CENTER_IMUX6_0", + "CFG_CENTER_IMUX34_0", + "CFG_CENTER_NE4BEG3_14", + "CFG_CENTER_SW4END3_7", + "CFG_CENTER_BYP7_15", + "CFG_CENTER_SW2A0_6", + "CFG_CENTER_EE4B2_4", + "CFG_CENTER_SE4C1_4", + "CFG_CENTER_NE4C3_3", + "CFG_CENTER_LH3_10", + "CFG_CENTER_SE4C2_9", + "CFG_CENTER_ER1BEG2_15", + "CFG_CENTER_EE2A3_7", + "CFG_CENTER_IMUX10_5", + "CFG_CENTER_NW4END2_9", + "CFG_CENTER_WW4C1_19", + "CFG_CENTER_SE4BEG0_18", + "CFG_CENTER_LOGIC_OUTS_B8_3", + "CFG_CENTER_IMUX26_19", + "CFG_CENTER_EE2BEG0_19", + "CFG_CENTER_LOGIC_OUTS_B16_10", + "CFG_CENTER_EE4C1_8", + "CFG_CENTER_EE4B1_18", + "CFG_CENTER_LOGIC_OUTS_B10_13", + "CFG_CENTER_NW4A0_12", + "CFG_CENTER_BYP2_18", + "CFG_CENTER_BLOCK_OUTS_B0_6", + "CFG_CENTER_WL1END3_5", + "CFG_CENTER_IMUX10_3", + "CFG_CENTER_LH11_6", + "CFG_CENTER_WW4A3_0", + "CFG_CENTER_NE2A0_13", + "CFG_CENTER_EE4BEG3_1", + "CFG_CENTER_SW4END3_15", + "CFG_CENTER_IMUX7_12", + "CFG_CENTER_WW2END0_19", + "CFG_CENTER_LOGIC_OUTS_B5_16", + "CFG_CENTER_WW4B2_13", + "CFG_CENTER_FAN1_11", + "CFG_CENTER_IMUX0_2", + "CFG_CENTER_IMUX33_4", + "CFG_CENTER_LH10_5", + "CFG_CENTER_EE2BEG1_14", + "CFG_CENTER_SE4BEG2_9", + "CFG_CENTER_LOGIC_OUTS_B16_3", + "CFG_CENTER_FAN2_19", + "CFG_CENTER_EE2BEG1_7", + "CFG_CENTER_IMUX9_11", + "CFG_CENTER_IMUX20_3", + "CFG_CENTER_SE2A3_14", + "CFG_CENTER_SE4C1_2", + "CFG_CENTER_LOGIC_OUTS_B15_3", + "CFG_CENTER_BYP2_14", + "CFG_CENTER_IMUX26_3", + "CFG_CENTER_LH7_9", + "CFG_CENTER_LOGIC_OUTS_B19_1", + "CFG_CENTER_LH2_17", + "CFG_CENTER_EE4BEG0_7", + "CFG_CENTER_ER1BEG2_9", + "CFG_CENTER_EE4C3_9", + "CFG_CENTER_BYP4_6", + "CFG_CENTER_LH8_16", + "CFG_CENTER_NE2A0_3", + "CFG_CENTER_WW2END0_14", + "CFG_CENTER_BLOCK_OUTS_B2_10", + "CFG_CENTER_EE4A0_14", + "CFG_CENTER_ER1BEG2_6", + "CFG_CENTER_NE2A2_10", + "CFG_CENTER_SE4BEG3_9", + "CFG_CENTER_LH6_19", + "CFG_CENTER_IMUX11_14", + "CFG_CENTER_IMUX5_14", + "CFG_CENTER_EE4A2_16", + "CFG_CENTER_IMUX23_4", + "CFG_CENTER_IMUX15_11", + "CFG_CENTER_SW2A0_1", + "CFG_CENTER_NW2A1_13", + "CFG_CENTER_WW4END0_13", + "CFG_CENTER_WW4END1_0", + "CFG_CENTER_SW4END0_18", + "CFG_CENTER_BYP7_10", + "CFG_CENTER_FAN3_10", + "CFG_CENTER_EE2BEG3_0", + "CFG_CENTER_WR1END2_18", + "CFG_CENTER_EE4C2_15", + "CFG_CENTER_IMUX8_3", + "CFG_CENTER_WR1END3_7", + "CFG_CENTER_IMUX27_15", + "CFG_CENTER_NE4BEG3_8", + "CFG_CENTER_NW4A3_7", + "CFG_CENTER_EL1BEG3_15", + "CFG_CENTER_WW2END3_8", + "CFG_CENTER_WR1END1_16", + "CFG_CENTER_IMUX11_17", + "CFG_CENTER_WW4C2_3", + "CFG_CENTER_BLOCK_OUTS_B2_19", + "CFG_CENTER_LOGIC_OUTS_B13_8", + "CFG_CENTER_NE4BEG3_18", + "CFG_CENTER_NW4END1_8", + "CFG_CENTER_WW4A1_0", + "CFG_CENTER_WW4A0_8", + "CFG_CENTER_IMUX40_6", + "CFG_CENTER_EE2BEG0_4", + "CFG_CENTER_LOGIC_OUTS_B3_7", + "CFG_CENTER_SW4A2_12", + "CFG_CENTER_CLK0_2", + "CFG_CENTER_WW4A0_11", + "CFG_CENTER_BYP1_3", + "CFG_CENTER_ER1BEG0_15", + "CFG_CENTER_EL1BEG0_6", + "CFG_CENTER_SW2A0_14", + "CFG_CENTER_WL1END1_0", + "CFG_CENTER_CLK1_15", + "CFG_CENTER_NW2A1_4", + "CFG_CENTER_LOGIC_OUTS_B14_10", + "CFG_CENTER_WW4B2_3", + "CFG_CENTER_EL1BEG1_1", + "CFG_CENTER_LOGIC_OUTS_B11_1", + "CFG_CENTER_WW2END3_10", + "CFG_CENTER_BYP2_4", + "CFG_CENTER_IMUX6_18", + "CFG_CENTER_IMUX37_6", + "CFG_CENTER_BLOCK_OUTS_B3_11", + "CFG_CENTER_LOGIC_OUTS_B3_8", + "CFG_CENTER_BYP3_6", + "CFG_CENTER_NE4BEG3_11", + "CFG_CENTER_EL1BEG3_12", + "CFG_CENTER_EE2A1_6", + "CFG_CENTER_IMUX12_8", + "CFG_CENTER_WW4END1_14", + "CFG_CENTER_IMUX44_8", + "CFG_CENTER_BLOCK_OUTS_B2_2", + "CFG_CENTER_NE4BEG3_13", + "CFG_CENTER_IMUX11_3", + "CFG_CENTER_SE2A3_3", + "CFG_CENTER_EL1BEG1_8", + "CFG_CENTER_BLOCK_OUTS_B2_9", + "CFG_CENTER_CTRL1_9", + "CFG_CENTER_IMUX39_1", + "CFG_CENTER_LOGIC_OUTS_B2_9", + "CFG_CENTER_WR1END1_14", + "CFG_CENTER_ER1BEG1_3", + "CFG_CENTER_IMUX1_15", + "CFG_CENTER_SW4A1_5", + "CFG_CENTER_IMUX4_10", + "CFG_CENTER_NE2A0_17", + "CFG_CENTER_WW4B0_18", + "CFG_CENTER_WW2END3_0", + "CFG_CENTER_EE2BEG0_9", + "CFG_CENTER_FAN5_10", + "CFG_CENTER_IMUX11_15", + "CFG_CENTER_FAN1_2", + "CFG_CENTER_IMUX17_5", + "CFG_CENTER_WW4A0_16", + "CFG_CENTER_NW4A2_17", + "CFG_CENTER_IMUX3_2", + "CFG_CENTER_WR1END1_13", + "CFG_CENTER_EE4C3_5", + "CFG_CENTER_EE2BEG2_18", + "CFG_CENTER_IMUX36_19", + "CFG_CENTER_EE2BEG1_12", + "CFG_CENTER_IMUX10_7", + "CFG_CENTER_WL1END3_9", + "CFG_CENTER_IMUX46_8", + "CFG_CENTER_LOGIC_OUTS_B16_11", + "CFG_CENTER_SE4C1_11", + "CFG_CENTER_IMUX4_18", + "CFG_CENTER_SW4END0_1", + "CFG_CENTER_EE2BEG1_11", + "CFG_CENTER_SW4END1_4", + "CFG_CENTER_WR1END2_7", + "CFG_CENTER_NE4C1_1", + "CFG_CENTER_WW2A1_8", + "CFG_CENTER_WL1END2_14", + "CFG_CENTER_IMUX2_14", + "CFG_CENTER_EE4B3_2", + "CFG_CENTER_LOGIC_OUTS_B21_1", + "CFG_CENTER_SE4C1_5", + "CFG_CENTER_WW2END0_13", + "CFG_CENTER_EE4A1_11", + "CFG_CENTER_LH1_8", + "CFG_CENTER_SE2A2_11", + "CFG_CENTER_WW4END1_17", + "CFG_CENTER_LOGIC_OUTS_B9_3", + "CFG_CENTER_NW4A3_9", + "CFG_CENTER_NE4C2_18", + "CFG_CENTER_WW4END2_19", + "CFG_CENTER_SE2A1_18", + "CFG_CENTER_WW2A3_16", + "CFG_CENTER_IMUX24_0", + "CFG_CENTER_CTRL0_19", + "CFG_CENTER_NW4END1_0", + "CFG_CENTER_IMUX44_11", + "CFG_CENTER_LOGIC_OUTS_B6_19", + "CFG_CENTER_LOGIC_OUTS_B1_13", + "CFG_CENTER_NE4C1_19", + "CFG_CENTER_EE2A3_2", + "CFG_CENTER_FAN6_13", + "CFG_CENTER_ER1BEG2_11", + "CFG_CENTER_IMUX9_18", + "CFG_CENTER_LOGIC_OUTS_B18_17", + "CFG_CENTER_NW4END0_0", + "CFG_CENTER_FAN5_8", + "CFG_CENTER_WW2END3_6", + "CFG_CENTER_EE4C1_11", + "CFG_CENTER_LOGIC_OUTS_B4_16", + "CFG_CENTER_LOGIC_OUTS_B23_6", + "CFG_CENTER_NW4A3_2", + "CFG_CENTER_LOGIC_OUTS_B6_12", + "CFG_CENTER_IMUX20_11", + "CFG_CENTER_IMUX4_7", + "CFG_CENTER_WW2A1_5", + "CFG_CENTER_NE2A1_0", + "CFG_CENTER_WW2END1_4", + "CFG_CENTER_LOGIC_OUTS_B6_17", + "CFG_CENTER_SW2A3_10", + "CFG_CENTER_LOGIC_OUTS_B13_14", + "CFG_CENTER_FAN0_8", + "CFG_CENTER_LOGIC_OUTS_B17_7", + "CFG_CENTER_LH4_16", + "CFG_CENTER_LH10_11", + "CFG_CENTER_LH8_2", + "CFG_CENTER_IMUX17_12", + "CFG_CENTER_LOGIC_OUTS_B2_13", + "CFG_CENTER_LOGIC_OUTS_B17_0", + "CFG_CENTER_LOGIC_OUTS_B9_14", + "CFG_CENTER_SW4A3_15", + "CFG_CENTER_NW4END3_5", + "CFG_CENTER_WR1END3_6", + "CFG_CENTER_IMUX10_13", + "CFG_CENTER_WW4C1_2", + "CFG_CENTER_IMUX5_13", + "CFG_CENTER_LH12_4", + "CFG_CENTER_IMUX31_6", + "CFG_CENTER_LH10_3", + "CFG_CENTER_IMUX22_3", + "CFG_CENTER_WL1END1_4", + "CFG_CENTER_IMUX8_12", + "CFG_CENTER_SW2A3_2", + "CFG_CENTER_WW4B0_14", + "CFG_CENTER_IMUX38_16", + "CFG_CENTER_LOGIC_OUTS_B3_2", + "CFG_CENTER_LOGIC_OUTS_B6_9", + "CFG_CENTER_EL1BEG0_4", + "CFG_CENTER_SE4C3_5", + "CFG_CENTER_ER1BEG3_3", + "CFG_CENTER_EE4C0_9", + "CFG_CENTER_EE4B3_14", + "CFG_CENTER_NW4END1_4", + "CFG_CENTER_IMUX16_9", + "CFG_CENTER_LOGIC_OUTS_B5_7", + "CFG_CENTER_IMUX25_16", + "CFG_CENTER_LOGIC_OUTS_B22_5", + "CFG_CENTER_IMUX32_19", + "CFG_CENTER_NW4A2_5", + "CFG_CENTER_IMUX42_4", + "CFG_CENTER_IMUX31_12", + "CFG_CENTER_IMUX25_14", + "CFG_CENTER_LOGIC_OUTS_B11_11", + "CFG_CENTER_LH10_2", + "CFG_CENTER_NW2A0_9", + "CFG_CENTER_EE2BEG0_8", + "CFG_CENTER_SE4BEG3_10", + "CFG_CENTER_ER1BEG1_5", + "CFG_CENTER_LOGIC_OUTS_B2_18", + "CFG_CENTER_EE4C3_3", + "CFG_CENTER_SE4C1_8", + "CFG_CENTER_WL1END2_9", + "CFG_CENTER_SE4C1_14", + "CFG_CENTER_EL1BEG3_8", + "CFG_CENTER_IMUX40_14", + "CFG_CENTER_LH10_1", + "CFG_CENTER_NE4BEG2_17", + "CFG_CENTER_SW2A0_13", + "CFG_CENTER_WR1END3_5", + "CFG_CENTER_BYP5_9", + "CFG_CENTER_WL1END1_3", + "CFG_CENTER_EE4B1_19", + "CFG_CENTER_BLOCK_OUTS_B2_14", + "CFG_CENTER_SW2A0_7", + "CFG_CENTER_LOGIC_OUTS_B12_18", + "CFG_CENTER_CTRL0_12", + "CFG_CENTER_BYP6_16", + "CFG_CENTER_IMUX42_2", + "CFG_CENTER_IMUX2_7", + "CFG_CENTER_EE4BEG0_12", + "CFG_CENTER_ER1BEG3_17", + "CFG_CENTER_LOGIC_OUTS_B5_1", + "CFG_CENTER_IMUX31_1", + "CFG_CENTER_SW4END2_13", + "CFG_CENTER_WW2END1_16", + "CFG_CENTER_NE2A3_0", + "CFG_CENTER_BYP1_9", + "CFG_CENTER_WW2END2_5", + "CFG_CENTER_SE4C0_9", + "CFG_CENTER_EE2A2_5", + "CFG_CENTER_IMUX2_1", + "CFG_CENTER_WR1END0_7", + "CFG_CENTER_WL1END1_1", + "CFG_CENTER_LOGIC_OUTS_B18_0", + "CFG_CENTER_IMUX21_1", + "CFG_CENTER_SE2A1_17", + "CFG_CENTER_LOGIC_OUTS_B11_5", + "CFG_CENTER_FAN4_19", + "CFG_CENTER_WW4A0_14", + "CFG_CENTER_IMUX17_18", + "CFG_CENTER_BYP4_12", + "CFG_CENTER_SW2A1_13", + "CFG_CENTER_LOGIC_OUTS_B16_14", + "CFG_CENTER_SW4END2_11", + "CFG_CENTER_WW4END2_1", + "CFG_CENTER_SW2A2_15", + "CFG_CENTER_IMUX13_9", + "CFG_CENTER_IMUX2_10", + "CFG_CENTER_LOGIC_OUTS_B7_4", + "CFG_CENTER_SW2A0_2", + "CFG_CENTER_IMUX3_7", + "CFG_CENTER_EE4A1_4", + "CFG_CENTER_BYP2_15", + "CFG_CENTER_IMUX44_15", + "CFG_CENTER_SE4BEG0_1", + "CFG_CENTER_EE4B3_6", + "CFG_CENTER_NE4C2_3", + "CFG_CENTER_LH8_6", + "CFG_CENTER_IMUX12_11", + "CFG_CENTER_IMUX47_4", + "CFG_CENTER_EE4C3_0", + "CFG_CENTER_NE4C1_3", + "CFG_CENTER_IMUX29_9", + "CFG_CENTER_IMUX29_6", + "CFG_CENTER_WW2END0_0", + "CFG_CENTER_FAN2_2", + "CFG_CENTER_FAN3_14", + "CFG_CENTER_WW4A1_13", + "CFG_CENTER_LOGIC_OUTS_B16_15", + "CFG_CENTER_EE4B3_17", + "CFG_CENTER_IMUX47_6", + "CFG_CENTER_NE4BEG1_5", + "CFG_CENTER_IMUX47_3", + "CFG_CENTER_LH11_13", + "CFG_CENTER_NW4END1_5", + "CFG_CENTER_WW4END2_13", + "CFG_CENTER_LH5_8", + "CFG_CENTER_IMUX40_19", + "CFG_CENTER_LOGIC_OUTS_B6_16", + "CFG_CENTER_EE2A3_10", + "CFG_CENTER_NE4BEG3_10", + "CFG_CENTER_SW4END1_7", + "CFG_CENTER_BYP1_16", + "CFG_CENTER_NW4END3_7", + "CFG_CENTER_EE4BEG0_0", + "CFG_CENTER_IMUX35_14", + "CFG_CENTER_NW2A0_6", + "CFG_CENTER_WW4C2_5", + "CFG_CENTER_IMUX14_16", + "CFG_CENTER_IMUX11_0", + "CFG_CENTER_IMUX28_10", + "CFG_CENTER_IMUX44_7", + "CFG_CENTER_IMUX30_1", + "CFG_CENTER_NE2A2_12", + "CFG_CENTER_NW2A2_16", + "CFG_CENTER_EE4BEG0_13", + "CFG_CENTER_IMUX46_10", + "CFG_CENTER_WW4A1_19", + "CFG_CENTER_IMUX17_7", + "CFG_CENTER_BLOCK_OUTS_B2_5", + "CFG_CENTER_SW4END1_2", + "CFG_CENTER_BYP1_7", + "CFG_CENTER_BYP0_7", + "CFG_CENTER_SW2A0_17", + "CFG_CENTER_IMUX1_11", + "CFG_CENTER_WW4C3_17", + "CFG_CENTER_LOGIC_OUTS_B15_19", + "CFG_CENTER_BLOCK_OUTS_B2_13", + "CFG_CENTER_SW2A1_8", + "CFG_CENTER_WW4END2_9", + "CFG_CENTER_EL1BEG3_7", + "CFG_CENTER_WW4END1_2", + "CFG_CENTER_WW4B3_4", + "CFG_CENTER_IMUX7_17", + "CFG_CENTER_SW2A1_2", + "CFG_CENTER_IMUX4_14", + "CFG_CENTER_SE2A0_19", + "CFG_CENTER_EE4B3_18", + "CFG_CENTER_CTRL0_17", + "CFG_CENTER_BYP0_6", + "CFG_CENTER_WW4A1_11", + "CFG_CENTER_WW4A2_10", + "CFG_CENTER_SW4END3_13", + "CFG_CENTER_BLOCK_OUTS_B1_16", + "CFG_CENTER_WW4END3_9", + "CFG_CENTER_LOGIC_OUTS_B7_2", + "CFG_CENTER_LOGIC_OUTS_B18_11", + "CFG_CENTER_IMUX32_4", + "CFG_CENTER_WW2A0_8", + "CFG_CENTER_IMUX20_6", + "CFG_CENTER_SE2A0_18", + "CFG_CENTER_SW2A2_1", + "CFG_CENTER_WL1END0_8", + "CFG_CENTER_LOGIC_OUTS_B1_2", + "CFG_CENTER_EL1BEG2_6", + "CFG_CENTER_EE4C1_17", + "CFG_CENTER_LOGIC_OUTS_B11_4", + "CFG_CENTER_IMUX9_0", + "CFG_CENTER_WR1END0_13", + "CFG_CENTER_BYP6_5", + "CFG_CENTER_FAN0_7", + "CFG_CENTER_WW4C1_17", + "CFG_CENTER_EE2BEG2_12", + "CFG_CENTER_EE4A1_8", + "CFG_CENTER_SE2A2_6", + "CFG_CENTER_LOGIC_OUTS_B7_3", + "CFG_CENTER_LOGIC_OUTS_B5_17", + "CFG_CENTER_BYP6_1", + "CFG_CENTER_IMUX21_6", + "CFG_CENTER_IMUX22_5", + "CFG_CENTER_IMUX28_14", + "CFG_CENTER_IMUX36_8", + "CFG_CENTER_LOGIC_OUTS_B9_0", + "CFG_CENTER_NE2A0_0", + "CFG_CENTER_LOGIC_OUTS_B3_3", + "CFG_CENTER_IMUX7_9", + "CFG_CENTER_FAN1_15", + "CFG_CENTER_FAN4_2", + "CFG_CENTER_LH5_0", + "CFG_CENTER_EE4C1_12", + "CFG_CENTER_EE4B1_12", + "CFG_CENTER_IMUX16_6", + "CFG_CENTER_ER1BEG3_8", + "CFG_CENTER_LOGIC_OUTS_B17_5", + "CFG_CENTER_FAN5_19", + "CFG_CENTER_WW2A3_17", + "CFG_CENTER_IMUX34_3", + "CFG_CENTER_NE4C3_4", + "CFG_CENTER_NW4END3_0", + "CFG_CENTER_IMUX7_5", + "CFG_CENTER_EE2BEG3_15", + "CFG_CENTER_LOGIC_OUTS_B14_8", + "CFG_CENTER_IMUX24_10", + "CFG_CENTER_SE2A1_11", + "CFG_CENTER_FAN5_17", + "CFG_CENTER_EE4BEG1_4", + "CFG_CENTER_IMUX14_9", + "CFG_CENTER_NE4BEG0_8", + "CFG_CENTER_NW4END1_16", + "CFG_CENTER_IMUX21_0", + "CFG_CENTER_LOGIC_OUTS_B11_15", + "CFG_CENTER_LOGIC_OUTS_B18_6", + "CFG_CENTER_IMUX12_4", + "CFG_CENTER_EL1BEG3_18", + "CFG_CENTER_EE2A2_18", + "CFG_CENTER_LOGIC_OUTS_B4_15", + "CFG_CENTER_NE4C2_8", + "CFG_CENTER_EE4C1_19", + "CFG_CENTER_SE4BEG2_12", + "CFG_CENTER_IMUX7_6", + "CFG_CENTER_WW4B3_19", + "CFG_CENTER_LOGIC_OUTS_B8_14", + "CFG_CENTER_IMUX31_17", + "CFG_CENTER_LOGIC_OUTS_B16_18", + "CFG_CENTER_EE4B1_5", + "CFG_CENTER_NE2A1_7", + "CFG_CENTER_LOGIC_OUTS_B4_10", + "CFG_CENTER_NW2A2_7", + "CFG_CENTER_IMUX0_0", + "CFG_CENTER_NE2A0_1", + "CFG_CENTER_LH4_15", + "CFG_CENTER_LH5_9", + "CFG_CENTER_WW4C1_6", + "CFG_CENTER_NW4END2_8", + "CFG_CENTER_IMUX0_15", + "CFG_CENTER_IMUX26_13", + "CFG_CENTER_SW4A1_16", + "CFG_CENTER_SE4C0_0", + "CFG_CENTER_IMUX29_3", + "CFG_CENTER_SW4END0_15", + "CFG_CENTER_IMUX39_9", + "CFG_CENTER_WW4C0_18", + "CFG_CENTER_IMUX38_4", + "CFG_CENTER_LOGIC_OUTS_B14_12", + "CFG_CENTER_CTRL1_7", + "CFG_CENTER_IMUX16_17", + "CFG_CENTER_LOGIC_OUTS_B6_13", + "CFG_CENTER_SE4C3_2", + "CFG_CENTER_WR1END3_1", + "CFG_CENTER_EE2BEG0_14", + "CFG_CENTER_BYP4_13", + "CFG_CENTER_WL1END0_0", + "CFG_CENTER_IMUX4_11", + "CFG_CENTER_IMUX40_13", + "CFG_CENTER_SW4A2_14", + "CFG_CENTER_NW4A0_10", + "CFG_CENTER_SW2A3_3", + "CFG_CENTER_ER1BEG1_12", + "CFG_CENTER_WR1END0_6", + "CFG_CENTER_WR1END2_17", + "CFG_CENTER_ER1BEG1_4", + "CFG_CENTER_EE4A2_13", + "CFG_CENTER_IMUX47_13", + "CFG_CENTER_WW2END3_5", + "CFG_CENTER_IMUX42_5", + "CFG_CENTER_FAN2_17", + "CFG_CENTER_LOGIC_OUTS_B10_15", + "CFG_CENTER_IMUX10_0", + "CFG_CENTER_EE2A3_5", + "CFG_CENTER_NW4END3_3", + "CFG_CENTER_IMUX8_18", + "CFG_CENTER_IMUX46_3", + "CFG_CENTER_NE4BEG2_2", + "CFG_CENTER_EE4A1_5", + "CFG_CENTER_LOGIC_OUTS_B20_2", + "CFG_CENTER_NE4BEG0_2", + "CFG_CENTER_LOGIC_OUTS_B6_15", + "CFG_CENTER_NW4A0_13", + "CFG_CENTER_WW4C2_19", + "CFG_CENTER_WW4C2_4", + "CFG_CENTER_IMUX12_19", + "CFG_CENTER_WW4END1_10", + "CFG_CENTER_LOGIC_OUTS_B0_3", + "CFG_CENTER_CTRL1_6", + "CFG_CENTER_ER1BEG0_8", + "CFG_CENTER_EE4BEG2_11", + "CFG_CENTER_SE2A1_5", + "CFG_CENTER_SW4A2_10", + "CFG_CENTER_FAN5_7", + "CFG_CENTER_NE4C0_7", + "CFG_CENTER_SW4A0_16", + "CFG_CENTER_LOGIC_OUTS_B3_5", + "CFG_CENTER_IMUX3_18", + "CFG_CENTER_SW2A2_4", + "CFG_CENTER_IMUX12_15", + "CFG_CENTER_WW4A1_10", + "CFG_CENTER_SW4END2_4", + "CFG_CENTER_LOGIC_OUTS_B13_6", + "CFG_CENTER_WR1END0_10", + "CFG_CENTER_NE2A2_6", + "CFG_CENTER_IMUX4_12", + "CFG_CENTER_NW4END0_17", + "CFG_CENTER_LOGIC_OUTS_B3_13", + "CFG_CENTER_LOGIC_OUTS_B17_4", + "CFG_CENTER_SE4BEG0_2", + "CFG_CENTER_BLOCK_OUTS_B0_7", + "CFG_CENTER_EE4C0_14", + "CFG_CENTER_BLOCK_OUTS_B0_13", + "CFG_CENTER_EE4C3_12", + "CFG_CENTER_BYP7_5", + "CFG_CENTER_NE4BEG3_1", + "CFG_CENTER_FAN0_6", + "CFG_CENTER_NE4BEG2_9", + "CFG_CENTER_IMUX7_14", + "CFG_CENTER_FAN4_16", + "CFG_CENTER_LOGIC_OUTS_B22_17", + "CFG_CENTER_NE4C3_8", + "CFG_CENTER_IMUX28_16", + "CFG_CENTER_LOGIC_OUTS_B22_16", + "CFG_CENTER_LH2_1", + "CFG_CENTER_EE4C0_10", + "CFG_CENTER_FAN2_14", + "CFG_CENTER_WW4B3_13", + "CFG_CENTER_EL1BEG2_0", + "CFG_CENTER_LH1_12", + "CFG_CENTER_WW4END3_6", + "CFG_CENTER_NE4BEG0_1", + "CFG_CENTER_NE2A3_1", + "CFG_CENTER_NW4END2_0", + "CFG_CENTER_WR1END2_11", + "CFG_CENTER_EL1BEG1_19", + "CFG_CENTER_WW4A3_6", + "CFG_CENTER_IMUX24_11", + "CFG_CENTER_WL1END3_17", + "CFG_CENTER_LOGIC_OUTS_B20_13", + "CFG_CENTER_IMUX33_10", + "CFG_CENTER_IMUX22_9", + "CFG_CENTER_EE4B0_7", + "CFG_CENTER_IMUX26_17", + "CFG_CENTER_EE4BEG2_13", + "CFG_CENTER_BLOCK_OUTS_B0_12", + "CFG_CENTER_IMUX17_4", + "CFG_CENTER_NW2A0_1", + "CFG_CENTER_NE4BEG1_0", + "CFG_CENTER_NE4C2_2", + "CFG_CENTER_IMUX41_10", + "CFG_CENTER_IMUX7_2", + "CFG_CENTER_WW4B1_14", + "CFG_CENTER_SE2A1_14", + "CFG_CENTER_LH12_5", + "CFG_CENTER_WW4END1_6", + "CFG_CENTER_IMUX39_13", + "CFG_CENTER_EE4A1_19", + "CFG_CENTER_WL1END0_10", + "CFG_CENTER_SE4C2_10", + "CFG_CENTER_IMUX9_6", + "CFG_CENTER_WW2A2_15", + "CFG_CENTER_IMUX23_12", + "CFG_CENTER_LOGIC_OUTS_B10_12", + "CFG_CENTER_LOGIC_OUTS_B19_16", + "CFG_CENTER_LOGIC_OUTS_B5_2", + "CFG_CENTER_IMUX8_2", + "CFG_CENTER_NW4A2_8", + "CFG_CENTER_WW2A0_17", + "CFG_CENTER_FAN0_5", + "CFG_CENTER_FAN7_1", + "CFG_CENTER_WW2A3_2", + "CFG_CENTER_EE2BEG1_5", + "CFG_CENTER_NE4BEG2_15", + "CFG_CENTER_BYP7_7", + "CFG_CENTER_IMUX23_6", + "CFG_CENTER_NW2A3_17", + "CFG_CENTER_WW4A2_18", + "CFG_CENTER_NW4A2_19", + "CFG_CENTER_IMUX24_9", + "CFG_CENTER_LOGIC_OUTS_B19_12", + "CFG_CENTER_FAN2_12", + "CFG_CENTER_EL1BEG2_10", + "CFG_CENTER_IMUX46_13", + "CFG_CENTER_WL1END1_8", + "CFG_CENTER_LOGIC_OUTS_B4_3", + "CFG_CENTER_SE2A0_16", + "CFG_CENTER_SW4END1_0", + "CFG_CENTER_LH3_0", + "CFG_CENTER_SE4C2_15", + "CFG_CENTER_LH2_2", + "CFG_CENTER_LOGIC_OUTS_B6_2", + "CFG_CENTER_IMUX4_8", + "CFG_CENTER_NE2A3_17", + "CFG_CENTER_FAN1_14", + "CFG_CENTER_IMUX13_1", + "CFG_CENTER_LOGIC_OUTS_B2_19", + "CFG_CENTER_WR1END1_18", + "CFG_CENTER_WW4C1_3", + "CFG_CENTER_SE2A3_11", + "CFG_CENTER_IMUX5_8", + "CFG_CENTER_IMUX40_11", + "CFG_CENTER_SE4C0_5", + "CFG_CENTER_SE2A3_6", + "CFG_CENTER_SE4C2_4", + "CFG_CENTER_WW2A2_17", + "CFG_CENTER_WW2END0_17", + "CFG_CENTER_LH8_4", + "CFG_CENTER_NW4A0_17", + "CFG_CENTER_SW2A3_9", + "CFG_CENTER_EE2A0_19", + "CFG_CENTER_LOGIC_OUTS_B16_8", + "CFG_CENTER_EE4A0_10", + "CFG_CENTER_LOGIC_OUTS_B2_10", + "CFG_CENTER_LH9_7", + "CFG_CENTER_LOGIC_OUTS_B11_7", + "CFG_CENTER_CLK1_16", + "CFG_CENTER_SW4END3_5", + "CFG_CENTER_LH4_17", + "CFG_CENTER_LOGIC_OUTS_B17_10", + "CFG_CENTER_IMUX1_7", + "CFG_CENTER_LOGIC_OUTS_B17_18", + "CFG_CENTER_IMUX23_3", + "CFG_CENTER_EE4C0_5", + "CFG_CENTER_NE4C2_9", + "CFG_CENTER_EL1BEG3_17", + "CFG_CENTER_IMUX35_12", + "CFG_CENTER_LOGIC_OUTS_B11_19", + "CFG_CENTER_NW4END2_2", + "CFG_CENTER_BYP3_12", + "CFG_CENTER_IMUX3_14", + "CFG_CENTER_LOGIC_OUTS_B22_15", + "CFG_CENTER_EE4A3_18", + "CFG_CENTER_BYP5_17", + "CFG_CENTER_IMUX17_8", + "CFG_CENTER_LOGIC_OUTS_B15_5", + "CFG_CENTER_NE4BEG1_8", + "CFG_CENTER_IMUX35_4", + "CFG_CENTER_NE4BEG0_7", + "CFG_CENTER_BLOCK_OUTS_B3_8", + "CFG_CENTER_EE2BEG2_4", + "CFG_CENTER_IMUX1_5", + "CFG_CENTER_NE4BEG2_14", + "CFG_CENTER_WW4END3_4", + "CFG_CENTER_IMUX2_9", + "CFG_CENTER_FAN7_7", + "CFG_CENTER_EE4BEG3_3", + "CFG_CENTER_EE4B2_6", + "CFG_CENTER_FAN6_6", + "CFG_CENTER_SW4END0_0", + "CFG_CENTER_WW4B3_1", + "CFG_CENTER_EE4A3_13", + "CFG_CENTER_EE4A0_5", + "CFG_CENTER_BYP6_10", + "CFG_CENTER_WL1END1_16", + "CFG_CENTER_NE4BEG0_4", + "CFG_CENTER_NW4A0_4", + "CFG_CENTER_IMUX13_10", + "CFG_CENTER_EE4BEG1_14", + "CFG_CENTER_LOGIC_OUTS_B13_10", + "CFG_CENTER_BYP4_5", + "CFG_CENTER_EE2A1_13", + "CFG_CENTER_EL1BEG0_9", + "CFG_CENTER_IMUX2_5", + "CFG_CENTER_IMUX35_5", + "CFG_CENTER_IMUX23_10", + "CFG_CENTER_NW2A3_14", + "CFG_CENTER_IMUX40_0", + "CFG_CENTER_NW4END3_11", + "CFG_CENTER_NE2A1_6", + "CFG_CENTER_WW4A2_7", + "CFG_CENTER_LOGIC_OUTS_B1_18", + "CFG_CENTER_LOGIC_OUTS_B21_14", + "CFG_CENTER_EE4C0_11", + "CFG_CENTER_SE4BEG0_10", + "CFG_CENTER_ER1BEG3_13", + "CFG_CENTER_EE2BEG0_10", + "CFG_CENTER_IMUX40_9", + "CFG_CENTER_IMUX9_7", + "CFG_CENTER_LOGIC_OUTS_B13_12", + "CFG_CENTER_EE2BEG1_3", + "CFG_CENTER_NE4C2_16", + "CFG_CENTER_WW4A0_18", + "CFG_CENTER_IMUX27_13", + "CFG_CENTER_LOGIC_OUTS_B5_19", + "CFG_CENTER_WR1END3_4", + "CFG_CENTER_NE4BEG2_13", + "CFG_CENTER_IMUX11_10", + "CFG_CENTER_IMUX39_15", + "CFG_CENTER_EE2A2_15", + "CFG_CENTER_IMUX36_15", + "CFG_CENTER_IMUX25_13", + "CFG_CENTER_EE4A3_0", + "CFG_CENTER_EE4A1_14", + "CFG_CENTER_WW4A0_2", + "CFG_CENTER_LOGIC_OUTS_B10_17", + "CFG_CENTER_LOGIC_OUTS_B20_9", + "CFG_CENTER_LH5_4", + "CFG_CENTER_EL1BEG3_16", + "CFG_CENTER_EE2BEG3_18", + "CFG_CENTER_BYP1_2", + "CFG_CENTER_LH5_16", + "CFG_CENTER_LH12_14", + "CFG_CENTER_IMUX9_16", + "CFG_CENTER_EL1BEG2_2", + "CFG_CENTER_WW4A2_2", + "CFG_CENTER_SE4BEG3_2", + "CFG_CENTER_LOGIC_OUTS_B15_18", + "CFG_CENTER_LOGIC_OUTS_B20_1", + "CFG_CENTER_ER1BEG0_10", + "CFG_CENTER_NW4A1_0", + "CFG_CENTER_WW4C1_14", + "CFG_CENTER_LH2_3", + "CFG_CENTER_WW2END0_7", + "CFG_CENTER_SE4C1_16", + "CFG_CENTER_CLK1_9", + "CFG_CENTER_WW2END1_3", + "CFG_CENTER_FAN5_12", + "CFG_CENTER_LOGIC_OUTS_B21_13", + "CFG_CENTER_WW4B0_10", + "CFG_CENTER_EE4B3_7", + "CFG_CENTER_LOGIC_OUTS_B23_2", + "CFG_CENTER_SW2A3_4", + "CFG_CENTER_ER1BEG1_1", + "CFG_CENTER_BYP3_18", + "CFG_CENTER_IMUX33_17", + "CFG_CENTER_EE4A3_3", + "CFG_CENTER_LH6_15", + "CFG_CENTER_SE4BEG3_11", + "CFG_CENTER_IMUX7_4", + "CFG_CENTER_BYP2_1", + "CFG_CENTER_SW4END2_17", + "CFG_CENTER_IMUX8_6", + "CFG_CENTER_NE2A0_11", + "CFG_CENTER_LOGIC_OUTS_B13_0", + "CFG_CENTER_IMUX4_6", + "CFG_CENTER_EL1BEG0_0", + "CFG_CENTER_NW4A3_18", + "CFG_CENTER_IMUX3_8", + "CFG_CENTER_CLK0_8", + "CFG_CENTER_WW2A2_9", + "CFG_CENTER_LH2_9", + "CFG_CENTER_SW4END3_0", + "CFG_CENTER_IMUX13_18", + "CFG_CENTER_LH4_0", + "CFG_CENTER_NW4A0_0", + "CFG_CENTER_BLOCK_OUTS_B0_17", + "CFG_CENTER_WW4END3_17", + "CFG_CENTER_IMUX42_6", + "CFG_CENTER_IMUX37_12", + "CFG_CENTER_EE2BEG3_12", + "CFG_CENTER_IMUX13_2", + "CFG_CENTER_NE2A1_10", + "CFG_CENTER_LOGIC_OUTS_B21_11", + "CFG_CENTER_EE4B2_7", + "CFG_CENTER_IMUX21_7", + "CFG_CENTER_EE4BEG1_8", + "CFG_CENTER_IMUX1_6", + "CFG_CENTER_WR1END3_13", + "CFG_CENTER_NW4END2_3", + "CFG_CENTER_SE4C0_6", + "CFG_CENTER_IMUX14_8", + "CFG_CENTER_WW4B2_7", + "CFG_CENTER_IMUX16_7", + "CFG_CENTER_FAN4_4", + "CFG_CENTER_IMUX9_3", + "CFG_CENTER_WW2END2_18", + "CFG_CENTER_IMUX43_6", + "CFG_CENTER_LH6_6", + "CFG_CENTER_ER1BEG1_14", + "CFG_CENTER_EL1BEG3_1", + "CFG_CENTER_NW4A3_15", + "CFG_CENTER_BLOCK_OUTS_B0_10", + "CFG_CENTER_IMUX18_12", + "CFG_CENTER_LOGIC_OUTS_B7_0", + "CFG_CENTER_NW2A2_9", + "CFG_CENTER_LOGIC_OUTS_B5_4", + "CFG_CENTER_LOGIC_OUTS_B7_13", + "CFG_CENTER_NE4BEG0_17", + "CFG_CENTER_IMUX33_5", + "CFG_CENTER_BYP3_13", + "CFG_CENTER_LH12_18", + "CFG_CENTER_EL1BEG2_15", + "CFG_CENTER_IMUX7_16", + "CFG_CENTER_NW4END0_9", + "CFG_CENTER_LOGIC_OUTS_B23_12", + "CFG_CENTER_SE4BEG0_0", + "CFG_CENTER_NE4C3_19", + "CFG_CENTER_SW2A0_8", + "CFG_CENTER_SW4A2_0", + "CFG_CENTER_NW4END1_18", + "CFG_CENTER_LOGIC_OUTS_B23_0", + "CFG_CENTER_NW4A3_19", + "CFG_CENTER_BLOCK_OUTS_B3_5", + "CFG_CENTER_LH9_10", + "CFG_CENTER_EE4A3_6", + "CFG_CENTER_IMUX30_8", + "CFG_CENTER_BLOCK_OUTS_B1_3", + "CFG_CENTER_IMUX27_16", + "CFG_CENTER_IMUX12_10", + "CFG_CENTER_NE4BEG3_2", + "CFG_CENTER_EE4C1_7", + "CFG_CENTER_SW4END0_13", + "CFG_CENTER_FAN3_15", + "CFG_CENTER_CTRL1_15", + "CFG_CENTER_EE4A0_0", + "CFG_CENTER_WW4A3_10", + "CFG_CENTER_WW2A0_10", + "CFG_CENTER_WW4C2_16", + "CFG_CENTER_NE2A0_2", + "CFG_CENTER_LH11_4", + "CFG_CENTER_EE4C1_9", + "CFG_CENTER_SE4C0_17", + "CFG_CENTER_LOGIC_OUTS_B9_19", + "CFG_CENTER_IMUX10_17", + "CFG_CENTER_BYP3_15", + "CFG_CENTER_IMUX10_12", + "CFG_CENTER_LOGIC_OUTS_B6_1", + "CFG_CENTER_NW2A2_3", + "CFG_CENTER_BYP3_8", + "CFG_CENTER_NW4END1_19", + "CFG_CENTER_NW2A0_3", + "CFG_CENTER_EE4BEG3_9", + "CFG_CENTER_BLOCK_OUTS_B1_7", + "CFG_CENTER_NW2A1_15", + "CFG_CENTER_EE4BEG1_2", + "CFG_CENTER_FAN6_7", + "CFG_CENTER_WW4A1_14", + "CFG_CENTER_IMUX40_16", + "CFG_CENTER_NW2A0_11", + "CFG_CENTER_IMUX6_6", + "CFG_CENTER_IMUX27_0", + "CFG_CENTER_WR1END2_8", + "CFG_CENTER_SW2A0_9", + "CFG_CENTER_LOGIC_OUTS_B20_7", + "CFG_CENTER_NE2A2_0", + "CFG_CENTER_EE4BEG1_16", + "CFG_CENTER_IMUX12_17", + "CFG_CENTER_IMUX2_12", + "CFG_CENTER_SW4A0_3", + "CFG_CENTER_EE4BEG2_14", + "CFG_CENTER_NW4A3_6", + "CFG_CENTER_WL1END2_12", + "CFG_CENTER_LOGIC_OUTS_B4_0", + "CFG_CENTER_WR1END1_17", + "CFG_CENTER_BLOCK_OUTS_B3_12", + "CFG_CENTER_EE4A3_19", + "CFG_CENTER_LH11_12", + "CFG_CENTER_NW4END0_1", + "CFG_CENTER_IMUX43_2", + "CFG_CENTER_WW4A3_1", + "CFG_CENTER_WW4END3_8", + "CFG_CENTER_BLOCK_OUTS_B2_1", + "CFG_CENTER_LOGIC_OUTS_B0_7", + "CFG_CENTER_LH5_17", + "CFG_CENTER_IMUX3_13", + "CFG_CENTER_IMUX9_19", + "CFG_CENTER_IMUX45_16", + "CFG_CENTER_LOGIC_OUTS_B13_4", + "CFG_CENTER_EE4A1_18", + "CFG_CENTER_EE4B2_15", + "CFG_CENTER_IMUX37_17", + "CFG_CENTER_EE4B0_1", + "CFG_CENTER_IMUX15_4", + "CFG_CENTER_EE2A2_16", + "CFG_CENTER_EE4BEG2_9", + "CFG_CENTER_IMUX9_5", + "CFG_CENTER_BLOCK_OUTS_B3_2", + "CFG_CENTER_IMUX47_9", + "CFG_CENTER_NW4A2_10", + "CFG_CENTER_SE4BEG3_19", + "CFG_CENTER_EE4A1_0", + "CFG_CENTER_EE2A2_11", + "CFG_CENTER_SW4END0_2", + "CFG_CENTER_IMUX11_1", + "CFG_CENTER_IMUX24_4", + "CFG_CENTER_SE4C2_5", + "CFG_CENTER_ER1BEG0_14", + "CFG_CENTER_EL1BEG0_13", + "CFG_CENTER_IMUX42_18", + "CFG_CENTER_BYP3_7", + "CFG_CENTER_NW4A3_5", + "CFG_CENTER_IMUX0_18", + "CFG_CENTER_EL1BEG0_17", + "CFG_CENTER_LH12_9", + "CFG_CENTER_LOGIC_OUTS_B3_19", + "CFG_CENTER_IMUX26_12", + "CFG_CENTER_LH6_14", + "CFG_CENTER_EE4A0_15", + "CFG_CENTER_IMUX17_10", + "CFG_CENTER_NW4END0_16", + "CFG_CENTER_BYP3_4", + "CFG_CENTER_WW2A3_10", + "CFG_CENTER_IMUX25_18", + "CFG_CENTER_NE2A0_6", + "CFG_CENTER_NE2A1_3", + "CFG_CENTER_LOGIC_OUTS_B5_10", + "CFG_CENTER_IMUX40_12", + "CFG_CENTER_SE4BEG3_18", + "CFG_CENTER_SW4A2_15", + "CFG_CENTER_NE4C2_5", + "CFG_CENTER_LOGIC_OUTS_B13_3", + "CFG_CENTER_EE4BEG0_10", + "CFG_CENTER_SE2A0_6", + "CFG_CENTER_NW4A0_8", + "CFG_CENTER_WL1END3_11", + "CFG_CENTER_WW2END1_5", + "CFG_CENTER_LOGIC_OUTS_B15_7", + "CFG_CENTER_CLK0_1", + "CFG_CENTER_WW4A3_16", + "CFG_CENTER_LOGIC_OUTS_B19_19", + "CFG_CENTER_IMUX13_19", + "CFG_CENTER_LOGIC_OUTS_B20_19", + "CFG_CENTER_LOGIC_OUTS_B15_0", + "CFG_CENTER_LOGIC_OUTS_B0_2", + "CFG_CENTER_NE2A1_8", + "CFG_CENTER_EE4B3_8", + "CFG_CENTER_EL1BEG1_15", + "CFG_CENTER_WW2A2_13", + "CFG_CENTER_NE2A2_4", + "CFG_CENTER_SE2A1_2", + "CFG_CENTER_IMUX22_2", + "CFG_CENTER_NW2A1_1", + "CFG_CENTER_IMUX36_0", + "CFG_CENTER_NW4A0_1", + "CFG_CENTER_IMUX16_12", + "CFG_CENTER_NW2A1_14", + "CFG_CENTER_EE4B0_16", + "CFG_CENTER_LH4_4", + "CFG_CENTER_ER1BEG0_0", + "CFG_CENTER_EE4BEG3_5", + "CFG_CENTER_NE4C2_14", + "CFG_CENTER_IMUX19_1", + "CFG_CENTER_BLOCK_OUTS_B2_7", + "CFG_CENTER_CTRL1_4", + "CFG_CENTER_WW2A1_6", + "CFG_CENTER_FAN4_8", + "CFG_CENTER_IMUX37_3", + "CFG_CENTER_LH1_16", + "CFG_CENTER_LOGIC_OUTS_B20_3", + "CFG_CENTER_IMUX10_14", + "CFG_CENTER_WW4C0_2", + "CFG_CENTER_NW2A1_17", + "CFG_CENTER_LOGIC_OUTS_B1_19", + "CFG_CENTER_LOGIC_OUTS_B21_9", + "CFG_CENTER_WL1END2_6", + "CFG_CENTER_EL1BEG1_16", + "CFG_CENTER_WW2END1_19", + "CFG_CENTER_EE4A2_10", + "CFG_CENTER_BYP6_0", + "CFG_CENTER_WW2END1_13", + "CFG_CENTER_SE4BEG2_2", + "CFG_CENTER_IMUX1_14", + "CFG_CENTER_IMUX15_9", + "CFG_CENTER_EL1BEG0_10", + "CFG_CENTER_LOGIC_OUTS_B5_18", + "CFG_CENTER_SW4A3_19", + "CFG_CENTER_LOGIC_OUTS_B18_7", + "CFG_CENTER_LH2_8", + "CFG_CENTER_LOGIC_OUTS_B23_8", + "CFG_CENTER_IMUX1_0", + "CFG_CENTER_LOGIC_OUTS_B21_16", + "CFG_CENTER_EE4B0_17", + "CFG_CENTER_IMUX30_15", + "CFG_CENTER_WR1END2_6", + "CFG_CENTER_WW4A3_13", + "CFG_CENTER_SW4A2_9", + "CFG_CENTER_WW4B2_11", + "CFG_CENTER_EE4BEG1_10", + "CFG_CENTER_FAN6_10", + "CFG_CENTER_WW2END1_1", + "CFG_CENTER_IMUX25_0", + "CFG_CENTER_IMUX40_17", + "CFG_CENTER_EE2A3_18", + "CFG_CENTER_WW4END0_11", + "CFG_CENTER_LOGIC_OUTS_B3_12", + "CFG_CENTER_NW4END0_11", + "CFG_CENTER_LOGIC_OUTS_B10_11", + "CFG_CENTER_BLOCK_OUTS_B3_9", + "CFG_CENTER_SW4END3_6", + "CFG_CENTER_LOGIC_OUTS_B20_8", + "CFG_CENTER_SW4END1_10", + "CFG_CENTER_IMUX45_13", + "CFG_CENTER_LOGIC_OUTS_B12_3", + "CFG_CENTER_SW4END2_0", + "CFG_CENTER_SE4BEG2_16", + "CFG_CENTER_WR1END2_1", + "CFG_CENTER_IMUX15_6", + "CFG_CENTER_SE4BEG0_8", + "CFG_CENTER_NW4END0_4", + "CFG_CENTER_EE4C3_6", + "CFG_CENTER_WR1END1_15", + "CFG_CENTER_SW2A0_0", + "CFG_CENTER_ER1BEG1_6", + "CFG_CENTER_IMUX26_11", + "CFG_CENTER_IMUX4_15", + "CFG_CENTER_WR1END0_15", + "CFG_CENTER_IMUX13_3", + "CFG_CENTER_EE4A0_19", + "CFG_CENTER_WW2A2_10", + "CFG_CENTER_EE4B0_18", + "CFG_CENTER_WL1END0_1", + "CFG_CENTER_WW2END3_13", + "CFG_CENTER_EE2A0_0", + "CFG_CENTER_LOGIC_OUTS_B17_1", + "CFG_CENTER_LOGIC_OUTS_B9_18", + "CFG_CENTER_BYP7_9", + "CFG_CENTER_IMUX30_16", + "CFG_CENTER_EE4B2_5", + "CFG_CENTER_SW4A1_3", + "CFG_CENTER_BLOCK_OUTS_B2_15", + "CFG_CENTER_IMUX3_0", + "CFG_CENTER_IMUX9_15", + "CFG_CENTER_IMUX47_11", + "CFG_CENTER_SW4A3_6", + "CFG_CENTER_BYP7_2", + "CFG_CENTER_LOGIC_OUTS_B14_0", + "CFG_CENTER_SW2A0_5", + "CFG_CENTER_LOGIC_OUTS_B2_8", + "CFG_CENTER_LH8_0", + "CFG_CENTER_LH11_11", + "CFG_CENTER_IMUX1_12", + "CFG_CENTER_NW2A2_19", + "CFG_CENTER_EE4A2_18", + "CFG_CENTER_EE4C1_14", + "CFG_CENTER_NE2A2_18", + "CFG_CENTER_IMUX3_1", + "CFG_CENTER_ER1BEG1_13", + "CFG_CENTER_WW4B0_9", + "CFG_CENTER_NE2A2_9", + "CFG_CENTER_SW4A1_12", + "CFG_CENTER_WW4B2_15", + "CFG_CENTER_BLOCK_OUTS_B1_13", + "CFG_CENTER_NW2A3_12", + "CFG_CENTER_SW4END0_11", + "CFG_CENTER_NE4C3_17", + "CFG_CENTER_EL1BEG0_5", + "CFG_CENTER_EE2BEG3_16", + "CFG_CENTER_SE4C1_12", + "CFG_CENTER_LH4_2", + "CFG_CENTER_ER1BEG3_6", + "CFG_CENTER_ER1BEG1_2", + "CFG_CENTER_EE2A1_5", + "CFG_CENTER_EE4A1_7", + "CFG_CENTER_SE2A1_13", + "CFG_CENTER_LOGIC_OUTS_B19_2", + "CFG_CENTER_CTRL1_5", + "CFG_CENTER_IMUX44_12", + "CFG_CENTER_ER1BEG1_7", + "CFG_CENTER_IMUX42_11", + "CFG_CENTER_WR1END0_5", + "CFG_CENTER_EE2A2_9", + "CFG_CENTER_IMUX37_10", + "CFG_CENTER_EE4B2_17", + "CFG_CENTER_EE2BEG0_0", + "CFG_CENTER_LOGIC_OUTS_B13_18", + "CFG_CENTER_EE4B2_14", + "CFG_CENTER_WW4END1_18", + "CFG_CENTER_CTRL1_3", + "CFG_CENTER_ER1BEG3_7", + "CFG_CENTER_IMUX47_16", + "CFG_CENTER_EE2A0_4", + "CFG_CENTER_NW2A1_11", + "CFG_CENTER_WW4B1_13", + "CFG_CENTER_WW4A0_1", + "CFG_CENTER_IMUX40_2", + "CFG_CENTER_IMUX43_4", + "CFG_CENTER_WW4C2_13", + "CFG_CENTER_LOGIC_OUTS_B21_10", + "CFG_CENTER_IMUX29_1", + "CFG_CENTER_IMUX34_14", + "CFG_CENTER_SE4C3_14", + "CFG_CENTER_IMUX20_19", + "CFG_CENTER_NE4C2_6", + "CFG_CENTER_LH3_17", + "CFG_CENTER_LOGIC_OUTS_B2_16", + "CFG_CENTER_WW4A0_17", + "CFG_CENTER_NE2A0_8", + "CFG_CENTER_EE4C1_13", + "CFG_CENTER_FAN5_4", + "CFG_CENTER_EE4A2_7", + "CFG_CENTER_IMUX45_9", + "CFG_CENTER_FAN2_10", + "CFG_CENTER_BLOCK_OUTS_B1_15", + "CFG_CENTER_IMUX27_2", + "CFG_CENTER_EE4B2_10", + "CFG_CENTER_EE2BEG0_12", + "CFG_CENTER_WW2A2_11", + "CFG_CENTER_SE4BEG1_2", + "CFG_CENTER_LOGIC_OUTS_B17_17", + "CFG_CENTER_WR1END2_19", + "CFG_CENTER_WW4B1_1", + "CFG_CENTER_LH12_15", + "CFG_CENTER_IMUX42_8", + "CFG_CENTER_NW4END2_1", + "CFG_CENTER_SW4A1_9", + "CFG_CENTER_IMUX27_6", + "CFG_CENTER_IMUX18_5", + "CFG_CENTER_IMUX9_12", + "CFG_CENTER_IMUX17_3", + "CFG_CENTER_EE4C1_15", + "CFG_CENTER_BLOCK_OUTS_B3_4", + "CFG_CENTER_NW4A0_3", + "CFG_CENTER_EE4A3_15", + "CFG_CENTER_IMUX16_19", + "CFG_CENTER_NE4BEG2_0", + "CFG_CENTER_SE4BEG0_13", + "CFG_CENTER_CTRL0_10", + "CFG_CENTER_SW4A1_14", + "CFG_CENTER_NE2A1_13", + "CFG_CENTER_EE4A0_12", + "CFG_CENTER_IMUX29_8", + "CFG_CENTER_EE4B0_15", + "CFG_CENTER_IMUX24_1", + "CFG_CENTER_LOGIC_OUTS_B20_12", + "CFG_CENTER_LH8_15", + "CFG_CENTER_NE2A1_5", + "CFG_CENTER_LH2_10", + "CFG_CENTER_NE4C0_15", + "CFG_CENTER_IMUX41_7", + "CFG_CENTER_LOGIC_OUTS_B5_9", + "CFG_CENTER_IMUX47_15", + "CFG_CENTER_SW2A1_12", + "CFG_CENTER_IMUX14_4", + "CFG_CENTER_EE2BEG1_17", + "CFG_CENTER_NE4C0_9", + "CFG_CENTER_LOGIC_OUTS_B0_8", + "CFG_CENTER_LOGIC_OUTS_B15_4", + "CFG_CENTER_NW4END1_10", + "CFG_CENTER_NE4BEG2_11", + "CFG_CENTER_FAN1_17", + "CFG_CENTER_EL1BEG1_4", + "CFG_CENTER_NE4C2_4", + "CFG_CENTER_NW2A0_15", + "CFG_CENTER_IMUX20_18", + "CFG_CENTER_SE4C2_11", + "CFG_CENTER_NW4END2_18", + "CFG_CENTER_CTRL1_16", + "CFG_CENTER_NW4END1_6", + "CFG_CENTER_EE4A0_11", + "CFG_CENTER_IMUX26_9", + "CFG_CENTER_FAN0_2", + "CFG_CENTER_WW4A2_5", + "CFG_CENTER_IMUX45_8", + "CFG_CENTER_LOGIC_OUTS_B2_5", + "CFG_CENTER_IMUX13_12", + "CFG_CENTER_SE2A2_19", + "CFG_CENTER_WW4A1_3", + "CFG_CENTER_CTRL1_8", + "CFG_CENTER_IMUX38_11", + "CFG_CENTER_SE2A3_13", + "CFG_CENTER_WW2END2_13", + "CFG_CENTER_WW4B1_8", + "CFG_CENTER_EE4BEG2_18", + "CFG_CENTER_BYP2_9", + "CFG_CENTER_IMUX41_15", + "CFG_CENTER_WR1END0_19", + "CFG_CENTER_LOGIC_OUTS_B3_4", + "CFG_CENTER_SW4A2_3", + "CFG_CENTER_IMUX3_17", + "CFG_CENTER_LH7_8", + "CFG_CENTER_NE4BEG2_4", + "CFG_CENTER_LH7_15", + "CFG_CENTER_IMUX22_15", + "CFG_CENTER_EE2BEG2_15", + "CFG_CENTER_LH3_13", + "CFG_CENTER_SW4A1_15", + "CFG_CENTER_LOGIC_OUTS_B15_2", + "CFG_CENTER_BYP7_4", + "CFG_CENTER_EE4A2_5", + "CFG_CENTER_IMUX0_10", + "CFG_CENTER_EE2A0_17", + "CFG_CENTER_IMUX38_7", + "CFG_CENTER_IMUX2_17", + "CFG_CENTER_WW4END3_14", + "CFG_CENTER_IMUX13_11", + "CFG_CENTER_IMUX18_9", + "CFG_CENTER_WW4C3_19", + "CFG_CENTER_SW4A0_11", + "CFG_CENTER_WW4END3_12", + "CFG_CENTER_NE4BEG3_16", + "CFG_CENTER_EL1BEG3_9", + "CFG_CENTER_EE4A0_17", + "CFG_CENTER_SE2A0_2", + "CFG_CENTER_WW4END0_10", + "CFG_CENTER_ER1BEG1_9", + "CFG_CENTER_NW4END1_12", + "CFG_CENTER_NE4BEG1_16", + "CFG_CENTER_SW2A0_4", + "CFG_CENTER_FAN1_4", + "CFG_CENTER_LH8_9", + "CFG_CENTER_WW4B3_11", + "CFG_CENTER_LOGIC_OUTS_B12_16", + "CFG_CENTER_LH9_4", + "CFG_CENTER_IMUX13_13", + "CFG_CENTER_LOGIC_OUTS_B1_15", + "CFG_CENTER_LH6_7", + "CFG_CENTER_NE4BEG1_15", + "CFG_CENTER_WW2END3_11", + "CFG_CENTER_SE4BEG1_8", + "CFG_CENTER_CLK1_17", + "CFG_CENTER_LH2_5", + "CFG_CENTER_IMUX31_15", + "CFG_CENTER_WW4END2_5", + "CFG_CENTER_IMUX14_11", + "CFG_CENTER_NW4END1_3", + "CFG_CENTER_WW2A3_13", + "CFG_CENTER_IMUX19_5", + "CFG_CENTER_NW2A2_2", + "CFG_CENTER_WW2END2_15", + "CFG_CENTER_SW4END3_19", + "CFG_CENTER_EL1BEG1_17", + "CFG_CENTER_WW4A0_15", + "CFG_CENTER_IMUX24_8", + "CFG_CENTER_IMUX45_0", + "CFG_CENTER_BYP1_5", + "CFG_CENTER_LH4_18", + "CFG_CENTER_SE2A0_13", + "CFG_CENTER_EE4B2_2", + "CFG_CENTER_NW4A2_7", + "CFG_CENTER_EL1BEG2_13", + "CFG_CENTER_LOGIC_OUTS_B14_5", + "CFG_CENTER_IMUX7_8", + "CFG_CENTER_LOGIC_OUTS_B12_12", + "CFG_CENTER_LOGIC_OUTS_B22_11", + "CFG_CENTER_LOGIC_OUTS_B19_5", + "CFG_CENTER_IMUX39_17", + "CFG_CENTER_ER1BEG3_1", + "CFG_CENTER_EE2BEG1_13", + "CFG_CENTER_LOGIC_OUTS_B17_15", + "CFG_CENTER_LOGIC_OUTS_B11_0", + "CFG_CENTER_FAN2_9", + "CFG_CENTER_NW4A0_19", + "CFG_CENTER_FAN3_1", + "CFG_CENTER_IMUX24_14", + "CFG_CENTER_IMUX10_9", + "CFG_CENTER_IMUX2_8", + "CFG_CENTER_IMUX39_5", + "CFG_CENTER_LOGIC_OUTS_B14_17", + "CFG_CENTER_SW4A2_6", + "CFG_CENTER_LOGIC_OUTS_B20_15", + "CFG_CENTER_EE4B0_4", + "CFG_CENTER_LOGIC_OUTS_B15_11", + "CFG_CENTER_NW4END1_11", + "CFG_CENTER_EE4B0_0", + "CFG_CENTER_EE2BEG2_9", + "CFG_CENTER_IMUX16_16", + "CFG_CENTER_IMUX11_6", + "CFG_CENTER_WR1END2_9", + "CFG_CENTER_NW2A0_8", + "CFG_CENTER_EE4BEG1_6", + "CFG_CENTER_NE4C1_9", + "CFG_CENTER_IMUX6_17", + "CFG_CENTER_NE4BEG0_0", + "CFG_CENTER_IMUX38_12", + "CFG_CENTER_NW4END0_18", + "CFG_CENTER_EE4BEG3_12", + "CFG_CENTER_LH10_14", + "CFG_CENTER_LOGIC_OUTS_B12_19", + "CFG_CENTER_WW4END0_4", + "CFG_CENTER_SW2A2_6", + "CFG_CENTER_WW2END0_12", + "CFG_CENTER_IMUX12_16", + "CFG_CENTER_EE2A1_7", + "CFG_CENTER_WW4C3_5", + "CFG_CENTER_EE2BEG2_2", + "CFG_CENTER_LH1_1", + "CFG_CENTER_LH11_9", + "CFG_CENTER_BYP1_12", + "CFG_CENTER_WW4END0_9", + "CFG_CENTER_LOGIC_OUTS_B3_18", + "CFG_CENTER_EE4BEG2_5", + "CFG_CENTER_WW4END3_0", + "CFG_CENTER_LOGIC_OUTS_B11_3", + "CFG_CENTER_SW4A0_4", + "CFG_CENTER_IMUX22_0", + "CFG_CENTER_EE4A1_17", + "CFG_CENTER_BOT_CFG_IO_ACCESS_VGGCOMPOUT", + "CFG_CENTER_WW4A2_6", + "CFG_CENTER_EE4B2_11", + "CFG_CENTER_SE2A0_3", + "CFG_CENTER_WR1END0_9", + "CFG_CENTER_ER1BEG0_12", + "CFG_CENTER_SW4A1_19", + "CFG_CENTER_IMUX34_11", + "CFG_CENTER_SW4END2_2", + "CFG_CENTER_EE2BEG1_8", + "CFG_CENTER_NE2A2_5", + "CFG_CENTER_IMUX35_17", + "CFG_CENTER_LOGIC_OUTS_B0_18", + "CFG_CENTER_LH10_12", + "CFG_CENTER_SE4C1_0", + "CFG_CENTER_SE2A2_8", + "CFG_CENTER_EE4A0_6", + "CFG_CENTER_EE4C0_6", + "CFG_CENTER_IMUX7_13", + "CFG_CENTER_WW4C2_14", + "CFG_CENTER_EE4B1_3", + "CFG_CENTER_EE4BEG2_0", + "CFG_CENTER_EE2BEG2_10", + "CFG_CENTER_LOGIC_OUTS_B16_19", + "CFG_CENTER_EE4C3_18", + "CFG_CENTER_IMUX16_10", + "CFG_CENTER_WW4A3_14", + "CFG_CENTER_FAN0_4", + "CFG_CENTER_EE4BEG3_13", + "CFG_CENTER_WW4END0_14", + "CFG_CENTER_FAN0_15", + "CFG_CENTER_LH6_13", + "CFG_CENTER_IMUX1_19", + "CFG_CENTER_WR1END1_0", + "CFG_CENTER_LOGIC_OUTS_B4_1", + "CFG_CENTER_BYP7_11", + "CFG_CENTER_FAN4_6", + "CFG_CENTER_IMUX47_5", + "CFG_CENTER_BYP1_17", + "CFG_CENTER_IMUX35_19", + "CFG_CENTER_WW2A1_14", + "CFG_CENTER_LOGIC_OUTS_B17_2", + "CFG_CENTER_IMUX10_16", + "CFG_CENTER_IMUX23_8", + "CFG_CENTER_IMUX32_2", + "CFG_CENTER_SE4C1_1", + "CFG_CENTER_WW4B1_11", + "CFG_CENTER_EE4B0_5", + "CFG_CENTER_EE2BEG0_17", + "CFG_CENTER_LOGIC_OUTS_B1_14", + "CFG_CENTER_NE4BEG0_18", + "CFG_CENTER_LH5_7", + "CFG_CENTER_SE2A3_10", + "CFG_CENTER_SE4BEG1_15", + "CFG_CENTER_WW4A2_14", + "CFG_CENTER_IMUX23_1", + "CFG_CENTER_SW4END3_8", + "CFG_CENTER_NW4A1_10", + "CFG_CENTER_IMUX41_0", + "CFG_CENTER_IMUX22_17", + "CFG_CENTER_BYP3_3", + "CFG_CENTER_WW4A2_16", + "CFG_CENTER_IMUX8_11", + "CFG_CENTER_NE4C1_13", + "CFG_CENTER_EE4C2_12", + "CFG_CENTER_IMUX20_14", + "CFG_CENTER_WR1END1_12", + "CFG_CENTER_WW4END2_12", + "CFG_CENTER_IMUX11_18", + "CFG_CENTER_WW4END0_19", + "CFG_CENTER_SW2A3_15", + "CFG_CENTER_BYP3_17", + "CFG_CENTER_SE2A0_4", + "CFG_CENTER_LOGIC_OUTS_B0_15", + "CFG_CENTER_LOGIC_OUTS_B21_15", + "CFG_CENTER_SE4C0_2", + "CFG_CENTER_LOGIC_OUTS_B16_9", + "CFG_CENTER_NE4C0_8", + "CFG_CENTER_IMUX26_16", + "CFG_CENTER_WR1END3_3", + "CFG_CENTER_LOGIC_OUTS_B21_4", + "CFG_CENTER_SW4A1_17", + "CFG_CENTER_SW2A3_19", + "CFG_CENTER_SE2A2_15", + "CFG_CENTER_IMUX40_4", + "CFG_CENTER_LOGIC_OUTS_B1_8", + "CFG_CENTER_IMUX5_6", + "CFG_CENTER_CLK0_6", + "CFG_CENTER_IMUX4_5", + "CFG_CENTER_NE4BEG1_17", + "CFG_CENTER_WW2END1_15", + "CFG_CENTER_WL1END2_1", + "CFG_CENTER_ER1BEG2_12", + "CFG_CENTER_IMUX7_3", + "CFG_CENTER_BYP3_10", + "CFG_CENTER_LOGIC_OUTS_B23_17", + "CFG_CENTER_CTRL0_0", + "CFG_CENTER_LOGIC_OUTS_B10_1", + "CFG_CENTER_LOGIC_OUTS_B8_11", + "CFG_CENTER_EL1BEG3_4", + "CFG_CENTER_EE2BEG2_7", + "CFG_CENTER_IMUX4_9", + "CFG_CENTER_LOGIC_OUTS_B5_15", + "CFG_CENTER_IMUX22_6", + "CFG_CENTER_SW4A0_6", + "CFG_CENTER_FAN2_3", + "CFG_CENTER_NE4BEG3_4", + "CFG_CENTER_EE2A2_17", + "CFG_CENTER_WW4C3_4", + "CFG_CENTER_WW4END2_16", + "CFG_CENTER_IMUX18_16", + "CFG_CENTER_SW4END0_14", + "CFG_CENTER_NW4A0_5", + "CFG_CENTER_LH6_3", + "CFG_CENTER_LOGIC_OUTS_B22_3", + "CFG_CENTER_EE4C1_3", + "CFG_CENTER_FAN4_7", + "CFG_CENTER_IMUX38_2", + "CFG_CENTER_LH11_2", + "CFG_CENTER_LOGIC_OUTS_B15_16", + "CFG_CENTER_SE4BEG2_0", + "CFG_CENTER_SE2A3_8", + "CFG_CENTER_IMUX43_3", + "CFG_CENTER_IMUX3_4", + "CFG_CENTER_EE4B0_14", + "CFG_CENTER_LOGIC_OUTS_B4_12", + "CFG_CENTER_SW4END2_6", + "CFG_CENTER_NE4BEG0_14", + "CFG_CENTER_BOT_USR_ACCESS_DATA5", + "CFG_CENTER_LOGIC_OUTS_B14_18", + "CFG_CENTER_IMUX5_9", + "CFG_CENTER_IMUX12_9", + "CFG_CENTER_WL1END2_8", + "CFG_CENTER_WW2A3_5", + "CFG_CENTER_IMUX20_17", + "CFG_CENTER_IMUX42_19", + "CFG_CENTER_EE4A3_2", + "CFG_CENTER_LOGIC_OUTS_B21_2", + "CFG_CENTER_IMUX19_10", + "CFG_CENTER_SE4C1_10", + "CFG_CENTER_IMUX24_17", + "CFG_CENTER_IMUX39_4", + "CFG_CENTER_LH5_3", + "CFG_CENTER_FAN1_12", + "CFG_CENTER_BLOCK_OUTS_B0_1", + "CFG_CENTER_IMUX46_1", + "CFG_CENTER_IMUX43_7", + "CFG_CENTER_LOGIC_OUTS_B17_14", + "CFG_CENTER_WW2A0_9", + "CFG_CENTER_SE4BEG2_18", + "CFG_CENTER_FAN3_6", + "CFG_CENTER_EE4BEG0_4", + "CFG_CENTER_WW4END2_8", + "CFG_CENTER_LH1_18", + "CFG_CENTER_SE4BEG0_6", + "CFG_CENTER_EE4B1_10", + "CFG_CENTER_BOT_USR_ACCESS_DATA6", + "CFG_CENTER_WW2END2_16", + "CFG_CENTER_NW2A1_7", + "CFG_CENTER_IMUX4_0", + "CFG_CENTER_NW4END2_5", + "CFG_CENTER_WW4END0_3", + "CFG_CENTER_SW4A2_5", + "CFG_CENTER_IMUX19_3", + "CFG_CENTER_LH9_19", + "CFG_CENTER_IMUX43_1", + "CFG_CENTER_LOGIC_OUTS_B4_17", + "CFG_CENTER_WW2END2_4", + "CFG_CENTER_EE4C2_19", + "CFG_CENTER_EE2BEG0_7", + "CFG_CENTER_WW2END3_1", + "CFG_CENTER_SE4C3_7", + "CFG_CENTER_IMUX39_11", + "CFG_CENTER_NW4END3_10", + "CFG_CENTER_LOGIC_OUTS_B10_0", + "CFG_CENTER_WW2END2_7", + "CFG_CENTER_WW4B2_17", + "CFG_CENTER_IMUX26_4", + "CFG_CENTER_EE2A3_8", + "CFG_CENTER_LH10_16", + "CFG_CENTER_LOGIC_OUTS_B16_7", + "CFG_CENTER_WW2END1_6", + "CFG_CENTER_WR1END2_13", + "CFG_CENTER_EE2BEG3_4", + "CFG_CENTER_EE4B2_12", + "CFG_CENTER_IMUX44_5", + "CFG_CENTER_WW4END3_11", + "CFG_CENTER_NE4C2_1", + "CFG_CENTER_FAN0_11", + "CFG_CENTER_IMUX19_9", + "CFG_CENTER_FAN5_11", + "CFG_CENTER_NW4END0_15", + "CFG_CENTER_EE4C1_1", + "CFG_CENTER_WW2END3_3", + "CFG_CENTER_WW2END1_10", + "CFG_CENTER_LOGIC_OUTS_B14_19", + "CFG_CENTER_WW4C1_15", + "CFG_CENTER_SE4C1_9", + "CFG_CENTER_WL1END3_4", + "CFG_CENTER_NE4C1_0", + "CFG_CENTER_SE4C2_6", + "CFG_CENTER_LH2_6", + "CFG_CENTER_WW4B3_8", + "CFG_CENTER_IMUX33_2", + "CFG_CENTER_IMUX34_17", + "CFG_CENTER_EL1BEG1_2", + "CFG_CENTER_LOGIC_OUTS_B4_13", + "CFG_CENTER_LOGIC_OUTS_B22_19", + "CFG_CENTER_IMUX19_8", + "CFG_CENTER_IMUX42_13", + "CFG_CENTER_NW4A3_8", + "CFG_CENTER_IMUX42_15", + "CFG_CENTER_IMUX27_4", + "CFG_CENTER_SW4END3_10", + "CFG_CENTER_WW4C0_16", + "CFG_CENTER_IMUX38_6", + "CFG_CENTER_IMUX7_11", + "CFG_CENTER_EE2A2_3", + "CFG_CENTER_SW4END0_12", + "CFG_CENTER_EE4B0_13", + "CFG_CENTER_BYP6_15", + "CFG_CENTER_EE4A2_19", + "CFG_CENTER_IMUX36_5", + "CFG_CENTER_EE4B1_14", + "CFG_CENTER_BLOCK_OUTS_B0_19", + "CFG_CENTER_EE4BEG3_6", + "CFG_CENTER_IMUX39_7", + "CFG_CENTER_IMUX40_8", + "CFG_CENTER_WL1END0_3", + "CFG_CENTER_FAN6_16", + "CFG_CENTER_EL1BEG2_12", + "CFG_CENTER_WR1END1_10", + "CFG_CENTER_WW2A1_9", + "CFG_CENTER_FAN5_16", + "CFG_CENTER_LH3_3", + "CFG_CENTER_IMUX16_4", + "CFG_CENTER_IMUX23_19", + "CFG_CENTER_LOGIC_OUTS_B14_2", + "CFG_CENTER_LH11_14", + "CFG_CENTER_IMUX11_2", + "CFG_CENTER_EL1BEG3_14", + "CFG_CENTER_EL1BEG2_3", + "CFG_CENTER_FAN4_15", + "CFG_CENTER_IMUX27_7", + "CFG_CENTER_EE4B0_3", + "CFG_CENTER_WL1END3_16", + "CFG_CENTER_EL1BEG1_7", + "CFG_CENTER_LH3_19", + "CFG_CENTER_IMUX15_17", + "CFG_CENTER_EE4A0_9", + "CFG_CENTER_WW2END3_14", + "CFG_CENTER_BYP6_18", + "CFG_CENTER_BYP0_5", + "CFG_CENTER_NE4C1_4", + "CFG_CENTER_FAN5_2", + "CFG_CENTER_NE4C1_18", + "CFG_CENTER_LOGIC_OUTS_B2_3", + "CFG_CENTER_WW2A3_11", + "CFG_CENTER_ER1BEG0_3", + "CFG_CENTER_LOGIC_OUTS_B19_11", + "CFG_CENTER_NE4C0_11", + "CFG_CENTER_WW4A0_0", + "CFG_CENTER_WW4C2_11", + "CFG_CENTER_SE4C3_9", + "CFG_CENTER_WW4END1_11", + "CFG_CENTER_EE4BEG3_15", + "CFG_CENTER_IMUX24_6", + "CFG_CENTER_IMUX34_6", + "CFG_CENTER_EE4B1_2", + "CFG_CENTER_IMUX38_13", + "CFG_CENTER_BLOCK_OUTS_B2_4", + "CFG_CENTER_LH1_3", + "CFG_CENTER_SW4END1_11", + "CFG_CENTER_EL1BEG1_6", + "CFG_CENTER_IMUX19_12", + "CFG_CENTER_LOGIC_OUTS_B6_7", + "CFG_CENTER_LOGIC_OUTS_B3_0", + "CFG_CENTER_SE4BEG2_11", + "CFG_CENTER_SE4C2_14", + "CFG_CENTER_IMUX20_10", + "CFG_CENTER_LOGIC_OUTS_B23_3", + "CFG_CENTER_CTRL1_11", + "CFG_CENTER_IMUX0_4", + "CFG_CENTER_FAN3_4", + "CFG_CENTER_NW4A1_17", + "CFG_CENTER_EE4B2_16", + "CFG_CENTER_NE2A3_11", + "CFG_CENTER_EE4B1_17", + "CFG_CENTER_SE4BEG2_3", + "CFG_CENTER_EE2A0_13", + "CFG_CENTER_LOGIC_OUTS_B19_17", + "CFG_CENTER_EE4C3_4", + "CFG_CENTER_WW2A3_7", + "CFG_CENTER_LH3_2", + "CFG_CENTER_IMUX12_0", + "CFG_CENTER_IMUX3_9", + "CFG_CENTER_WL1END3_18", + "CFG_CENTER_SW4END1_5", + "CFG_CENTER_WW2END2_6", + "CFG_CENTER_IMUX42_0", + "CFG_CENTER_LOGIC_OUTS_B8_1", + "CFG_CENTER_LOGIC_OUTS_B13_9", + "CFG_CENTER_SE4C3_13", + "CFG_CENTER_SE4BEG0_15", + "CFG_CENTER_LH11_16", + "CFG_CENTER_SW4END2_12", + "CFG_CENTER_IMUX17_17", + "CFG_CENTER_WL1END3_12", + "CFG_CENTER_IMUX33_9", + "CFG_CENTER_LOGIC_OUTS_B18_13", + "CFG_CENTER_LH9_0", + "CFG_CENTER_NW4END2_10", + "CFG_CENTER_NW2A3_10", + "CFG_CENTER_IMUX15_0", + "CFG_CENTER_LOGIC_OUTS_B7_6", + "CFG_CENTER_CTRL0_16", + "CFG_CENTER_NW4A1_5", + "CFG_CENTER_IMUX21_12", + "CFG_CENTER_LH7_0", + "CFG_CENTER_EL1BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B19_9", + "CFG_CENTER_LH4_10", + "CFG_CENTER_CTRL1_13", + "CFG_CENTER_IMUX2_0", + "CFG_CENTER_EL1BEG2_7", + "CFG_CENTER_LOGIC_OUTS_B15_14", + "CFG_CENTER_LOGIC_OUTS_B23_18", + "CFG_CENTER_EE2A1_16", + "CFG_CENTER_IMUX8_14", + "CFG_CENTER_EE4C0_18", + "CFG_CENTER_SW2A1_10", + "CFG_CENTER_WW4A1_9", + "CFG_CENTER_CTRL1_19", + "CFG_CENTER_ER1BEG0_7", + "CFG_CENTER_IMUX22_1", + "CFG_CENTER_NE4C1_11", + "CFG_CENTER_EE4A1_15", + "CFG_CENTER_WW2A2_3", + "CFG_CENTER_LOGIC_OUTS_B23_15", + "CFG_CENTER_EL1BEG0_15", + "CFG_CENTER_IMUX7_19", + "CFG_CENTER_SE4BEG0_17", + "CFG_CENTER_WL1END2_11", + "CFG_CENTER_WW4C1_13", + "CFG_CENTER_LOGIC_OUTS_B22_13", + "CFG_CENTER_EE4C0_13", + "CFG_CENTER_IMUX43_5", + "CFG_CENTER_IMUX31_4", + "CFG_CENTER_EE4B1_13", + "CFG_CENTER_WW2A1_12", + "CFG_CENTER_SE2A3_2", + "CFG_CENTER_IMUX30_18", + "CFG_CENTER_SW4A1_2", + "CFG_CENTER_IMUX22_18", + "CFG_CENTER_NW4A2_13", + "CFG_CENTER_FAN7_2", + "CFG_CENTER_ER1BEG1_0", + "CFG_CENTER_IMUX46_5", + "CFG_CENTER_IMUX37_9", + "CFG_CENTER_IMUX13_15", + "CFG_CENTER_WW2END0_3", + "CFG_CENTER_WL1END0_5", + "CFG_CENTER_EL1BEG3_10", + "CFG_CENTER_WW4C0_5", + "CFG_CENTER_NE4C0_18", + "CFG_CENTER_WW4C0_19", + "CFG_CENTER_IMUX41_18", + "CFG_CENTER_LH11_8", + "CFG_CENTER_SE4C3_15", + "CFG_CENTER_LOGIC_OUTS_B23_1", + "CFG_CENTER_WW4A1_7", + "CFG_CENTER_WW4A2_12", + "CFG_CENTER_NW4END2_13", + "CFG_CENTER_LOGIC_OUTS_B16_12", + "CFG_CENTER_EE4B1_4", + "CFG_CENTER_IMUX21_18", + "CFG_CENTER_IMUX8_13", + "CFG_CENTER_FAN0_19", + "CFG_CENTER_BOT_USR_ACCESS_DATA7", + "CFG_CENTER_BYP0_0", + "CFG_CENTER_NE4C0_6", + "CFG_CENTER_SW4A2_11", + "CFG_CENTER_WW4B0_16", + "CFG_CENTER_EE4BEG0_3", + "CFG_CENTER_SW2A1_9", + "CFG_CENTER_BLOCK_OUTS_B2_12", + "CFG_CENTER_SW2A1_6", + "CFG_CENTER_IMUX33_11", + "CFG_CENTER_EE2BEG0_5", + "CFG_CENTER_IMUX6_13", + "CFG_CENTER_NW4END3_16", + "CFG_CENTER_EE4A0_13", + "CFG_CENTER_WW2END1_2", + "CFG_CENTER_WW4B3_7", + "CFG_CENTER_SE2A0_15", + "CFG_CENTER_NW2A0_19", + "CFG_CENTER_FAN5_13", + "CFG_CENTER_WW4C3_9", + "CFG_CENTER_WW2A0_14", + "CFG_CENTER_NW2A2_8", + "CFG_CENTER_WW2A0_11", + "CFG_CENTER_ER1BEG3_2", + "CFG_CENTER_FAN3_11", + "CFG_CENTER_IMUX33_7", + "CFG_CENTER_ER1BEG2_0", + "CFG_CENTER_LOGIC_OUTS_B12_15", + "CFG_CENTER_LH9_15", + "CFG_CENTER_CTRL0_14", + "CFG_CENTER_LOGIC_OUTS_B10_3", + "CFG_CENTER_IMUX8_16", + "CFG_CENTER_WL1END0_14", + "CFG_CENTER_CLK0_15", + "CFG_CENTER_LH9_6", + "CFG_CENTER_IMUX19_7", + "CFG_CENTER_SE4BEG1_6", + "CFG_CENTER_SW4A1_6", + "CFG_CENTER_NE4C1_7", + "CFG_CENTER_IMUX39_12", + "CFG_CENTER_IMUX46_19", + "CFG_CENTER_LOGIC_OUTS_B16_13", + "CFG_CENTER_LOGIC_OUTS_B5_8", + "CFG_CENTER_FAN5_3", + "CFG_CENTER_IMUX10_11", + "CFG_CENTER_EE2A3_13", + "CFG_CENTER_WW2A3_19", + "CFG_CENTER_IMUX21_4", + "CFG_CENTER_NE4BEG0_15", + "CFG_CENTER_NE4C3_2", + "CFG_CENTER_IMUX17_2", + "CFG_CENTER_IMUX46_18", + "CFG_CENTER_LOGIC_OUTS_B14_15", + "CFG_CENTER_IMUX23_2", + "CFG_CENTER_FAN2_13", + "CFG_CENTER_SE4C0_18", + "CFG_CENTER_SE2A0_14", + "CFG_CENTER_IMUX30_10", + "CFG_CENTER_NW4END1_2", + "CFG_CENTER_BLOCK_OUTS_B0_5", + "CFG_CENTER_LOGIC_OUTS_B1_7", + "CFG_CENTER_NE4C2_0", + "CFG_CENTER_BYP2_5", + "CFG_CENTER_ER1BEG1_19", + "CFG_CENTER_IMUX5_17", + "CFG_CENTER_IMUX0_3", + "CFG_CENTER_NE4C1_5", + "CFG_CENTER_IMUX31_2", + "CFG_CENTER_WW4C1_10", + "CFG_CENTER_LOGIC_OUTS_B3_15", + "CFG_CENTER_BLOCK_OUTS_B3_1", + "CFG_CENTER_FAN5_6", + "CFG_CENTER_WW4A3_2", + "CFG_CENTER_BLOCK_OUTS_B2_8", + "CFG_CENTER_LOGIC_OUTS_B23_9", + "CFG_CENTER_WW4C2_15", + "CFG_CENTER_WL1END1_12", + "CFG_CENTER_SW4END2_15", + "CFG_CENTER_IMUX8_0", + "CFG_CENTER_WW4B0_4", + "CFG_CENTER_BYP2_3", + "CFG_CENTER_IMUX13_8", + "CFG_CENTER_WR1END0_1", + "CFG_CENTER_LOGIC_OUTS_B16_17", + "CFG_CENTER_CTRL0_3", + "CFG_CENTER_IMUX5_11", + "CFG_CENTER_LOGIC_OUTS_B20_5", + "CFG_CENTER_FAN3_9", + "CFG_CENTER_SE4BEG3_6", + "CFG_CENTER_SE4BEG1_9", + "CFG_CENTER_IMUX41_16", + "CFG_CENTER_IMUX15_12", + "CFG_CENTER_EE4B0_11", + "CFG_CENTER_SW4END1_8", + "CFG_CENTER_FAN5_18", + "CFG_CENTER_LH11_3", + "CFG_CENTER_IMUX6_11", + "CFG_CENTER_NW2A3_11", + "CFG_CENTER_SW4END1_3", + "CFG_CENTER_EE4C2_11", + "CFG_CENTER_EE4BEG1_7", + "CFG_CENTER_IMUX28_9", + "CFG_CENTER_NE4C0_10", + "CFG_CENTER_WW4B1_9", + "CFG_CENTER_IMUX38_15", + "CFG_CENTER_SE4BEG3_5", + "CFG_CENTER_NW4A1_9", + "CFG_CENTER_WW4END3_18", + "CFG_CENTER_EE2A2_2", + "CFG_CENTER_NW4A2_1", + "CFG_CENTER_SE4BEG1_0", + "CFG_CENTER_IMUX34_10", + "CFG_CENTER_BYP7_19", + "CFG_CENTER_NE2A0_9", + "CFG_CENTER_SE4BEG0_12", + "CFG_CENTER_EE4A2_4", + "CFG_CENTER_FAN2_7", + "CFG_CENTER_EE4A2_3", + "CFG_CENTER_SE2A0_17", + "CFG_CENTER_NE4C0_17", + "CFG_CENTER_WW4A3_12", + "CFG_CENTER_WW2END0_9", + "CFG_CENTER_SW4A3_2", + "CFG_CENTER_WW4C3_11", + "CFG_CENTER_ER1BEG1_17", + "CFG_CENTER_SW2A1_7", + "CFG_CENTER_IMUX28_3", + "CFG_CENTER_IMUX18_17", + "CFG_CENTER_NE2A0_4", + "CFG_CENTER_WW4C2_9", + "CFG_CENTER_BLOCK_OUTS_B2_17", + "CFG_CENTER_NW2A0_13", + "CFG_CENTER_EL1BEG3_0", + "CFG_CENTER_IMUX34_7", + "CFG_CENTER_NE4C3_9", + "CFG_CENTER_NW4A0_16", + "CFG_CENTER_FAN4_5", + "CFG_CENTER_WW4C0_7", + "CFG_CENTER_LOGIC_OUTS_B14_11", + "CFG_CENTER_FAN1_18", + "CFG_CENTER_EL1BEG1_12", + "CFG_CENTER_NE2A2_3", + "CFG_CENTER_IMUX30_19", + "CFG_CENTER_LH1_14", + "CFG_CENTER_LOGIC_OUTS_B18_15", + "CFG_CENTER_IMUX25_15", + "CFG_CENTER_IMUX23_14", + "CFG_CENTER_BLOCK_OUTS_B1_19", + "CFG_CENTER_WW4B0_19", + "CFG_CENTER_LOGIC_OUTS_B20_18", + "CFG_CENTER_SE4C0_16", + "CFG_CENTER_FAN7_13", + "CFG_CENTER_EE4BEG3_2", + "CFG_CENTER_IMUX28_11", + "CFG_CENTER_EE4BEG3_14", + "CFG_CENTER_CLK0_10", + "CFG_CENTER_NE4C2_15", + "CFG_CENTER_BOT_USR_ACCESS_DATA11", + "CFG_CENTER_WW4C2_12", + "CFG_CENTER_FAN6_4", + "CFG_CENTER_WW2A2_1", + "CFG_CENTER_LOGIC_OUTS_B12_6", + "CFG_CENTER_LOGIC_OUTS_B12_5", + "CFG_CENTER_CLK1_7", + "CFG_CENTER_SE4C0_4", + "CFG_CENTER_WL1END0_13", + "CFG_CENTER_BYP3_16", + "CFG_CENTER_IMUX7_7", + "CFG_CENTER_LH12_16", + "CFG_CENTER_NW4A1_8", + "CFG_CENTER_LOGIC_OUTS_B11_6", + "CFG_CENTER_IMUX30_9", + "CFG_CENTER_IMUX6_5", + "CFG_CENTER_EE2A3_4", + "CFG_CENTER_EE2A2_14", + "CFG_CENTER_SE2A2_9", + "CFG_CENTER_BOT_USR_ACCESS_DATA8", + "CFG_CENTER_IMUX32_11", + "CFG_CENTER_LOGIC_OUTS_B12_4", + "CFG_CENTER_NE4C1_17", + "CFG_CENTER_IMUX10_18", + "CFG_CENTER_CTRL0_11", + "CFG_CENTER_LOGIC_OUTS_B9_15", + "CFG_CENTER_IMUX22_11", + "CFG_CENTER_NW4A0_11", + "CFG_CENTER_EE4BEG1_9", + "CFG_CENTER_EE4A1_10", + "CFG_CENTER_WW4B2_19", + "CFG_CENTER_NE4BEG0_9", + "CFG_CENTER_IMUX33_13", + "CFG_CENTER_WW4A1_5", + "CFG_CENTER_BLOCK_OUTS_B3_15", + "CFG_CENTER_LH3_4", + "CFG_CENTER_SE4BEG3_13", + "CFG_CENTER_WW4END1_19", + "CFG_CENTER_WW2END2_0", + "CFG_CENTER_IMUX9_14", + "CFG_CENTER_LOGIC_OUTS_B10_6", + "CFG_CENTER_IMUX20_7", + "CFG_CENTER_LOGIC_OUTS_B16_2", + "CFG_CENTER_LOGIC_OUTS_B12_0", + "CFG_CENTER_BYP1_6", + "CFG_CENTER_SE2A0_12", + "CFG_CENTER_EL1BEG1_18", + "CFG_CENTER_NE4BEG3_17", + "CFG_CENTER_BLOCK_OUTS_B3_16", + "CFG_CENTER_WL1END1_2", + "CFG_CENTER_SW4END0_17", + "CFG_CENTER_ER1BEG0_11", + "CFG_CENTER_WL1END0_4", + "CFG_CENTER_EL1BEG3_5", + "CFG_CENTER_IMUX35_15", + "CFG_CENTER_SW4A0_17", + "CFG_CENTER_NW2A0_5", + "CFG_CENTER_LOGIC_OUTS_B17_12", + "CFG_CENTER_SW4A0_18", + "CFG_CENTER_NE4BEG2_3", + "CFG_CENTER_WW2A0_4", + "CFG_CENTER_SW4A1_13", + "CFG_CENTER_IMUX15_16", + "CFG_CENTER_WW2END3_15", + "CFG_CENTER_NE2A3_12", + "CFG_CENTER_LOGIC_OUTS_B6_14", + "CFG_CENTER_BYP4_10", + "CFG_CENTER_IMUX36_2", + "CFG_CENTER_NW4A2_0", + "CFG_CENTER_BYP0_4", + "CFG_CENTER_NE4BEG1_1", + "CFG_CENTER_IMUX44_6", + "CFG_CENTER_IMUX0_17", + "CFG_CENTER_EE4BEG3_16", + "CFG_CENTER_EE2A2_1", + "CFG_CENTER_SW4END0_3", + "CFG_CENTER_WL1END0_6", + "CFG_CENTER_WL1END0_17", + "CFG_CENTER_EE2A2_7", + "CFG_CENTER_IMUX0_9", + "CFG_CENTER_SW4END1_15", + "CFG_CENTER_WW2END0_18", + "CFG_CENTER_SE4BEG1_10", + "CFG_CENTER_LOGIC_OUTS_B15_15", + "CFG_CENTER_LOGIC_OUTS_B18_8", + "CFG_CENTER_WW2END1_8", + "CFG_CENTER_BLOCK_OUTS_B1_14", + "CFG_CENTER_LOGIC_OUTS_B12_9", + "CFG_CENTER_EE4BEG1_18", + "CFG_CENTER_SE4BEG3_12", + "CFG_CENTER_IMUX6_4", + "CFG_CENTER_IMUX20_1", + "CFG_CENTER_LH11_5", + "CFG_CENTER_IMUX29_10", + "CFG_CENTER_LOGIC_OUTS_B2_0", + "CFG_CENTER_EL1BEG0_12", + "CFG_CENTER_NE4C1_10", + "CFG_CENTER_SE2A0_0", + "CFG_CENTER_SE4C3_3", + "CFG_CENTER_WW4C1_7", + "CFG_CENTER_LH8_13", + "CFG_CENTER_SE4BEG0_9", + "CFG_CENTER_LH9_18", + "CFG_CENTER_IMUX47_19", + "CFG_CENTER_IMUX28_0", + "CFG_CENTER_WW4END2_11", + "CFG_CENTER_EE2BEG3_1", + "CFG_CENTER_EE4C1_0", + "CFG_CENTER_WW4C0_1", + "CFG_CENTER_IMUX5_10", + "CFG_CENTER_LOGIC_OUTS_B16_6", + "CFG_CENTER_IMUX45_6", + "CFG_CENTER_EE4C1_4", + "CFG_CENTER_SE4BEG2_19", + "CFG_CENTER_BLOCK_OUTS_B1_18", + "CFG_CENTER_NE4BEG2_16", + "CFG_CENTER_IMUX27_8", + "CFG_CENTER_SW4A2_4", + "CFG_CENTER_FAN6_11", + "CFG_CENTER_IMUX32_10", + "CFG_CENTER_EE2A3_3", + "CFG_CENTER_WW4B3_18", + "CFG_CENTER_WL1END0_19", + "CFG_CENTER_BYP4_2", + "CFG_CENTER_EE2A3_19", + "CFG_CENTER_BYP1_4", + "CFG_CENTER_BYP4_3", + "CFG_CENTER_FAN7_10", + "CFG_CENTER_ER1BEG2_3", + "CFG_CENTER_NW2A2_18", + "CFG_CENTER_BYP0_2", + "CFG_CENTER_WW2END2_19", + "CFG_CENTER_SW4END3_11", + "CFG_CENTER_CLK1_18", + "CFG_CENTER_LH1_5", + "CFG_CENTER_NW2A2_1", + "CFG_CENTER_WW4A3_8", + "CFG_CENTER_WR1END2_16", + "CFG_CENTER_IMUX5_5", + "CFG_CENTER_IMUX12_12", + "CFG_CENTER_IMUX30_11", + "CFG_CENTER_IMUX2_13", + "CFG_CENTER_IMUX16_5", + "CFG_CENTER_LOGIC_OUTS_B12_2", + "CFG_CENTER_SW2A1_3", + "CFG_CENTER_EE4A2_0", + "CFG_CENTER_LOGIC_OUTS_B12_8", + "CFG_CENTER_NE4C2_7", + "CFG_CENTER_SW4A1_1", + "CFG_CENTER_SE2A3_17", + "CFG_CENTER_CLK0_7", + "CFG_CENTER_SE4BEG3_3", + "CFG_CENTER_ER1BEG1_8", + "CFG_CENTER_IMUX45_5", + "CFG_CENTER_LOGIC_OUTS_B7_7", + "CFG_CENTER_WW2A1_16", + "CFG_CENTER_NE2A3_8", + "CFG_CENTER_SE4BEG2_13", + "CFG_CENTER_WW2A3_8", + "CFG_CENTER_SW2A3_6", + "CFG_CENTER_EE4BEG2_12", + "CFG_CENTER_FAN1_5", + "CFG_CENTER_IMUX24_13", + "CFG_CENTER_LOGIC_OUTS_B10_5", + "CFG_CENTER_FAN6_12", + "CFG_CENTER_IMUX8_8", + "CFG_CENTER_WW4C3_14", + "CFG_CENTER_BYP2_7", + "CFG_CENTER_ER1BEG3_4", + "CFG_CENTER_WW4B3_16", + "CFG_CENTER_EE4B3_1", + "CFG_CENTER_WW2A0_18", + "CFG_CENTER_WW2A1_13", + "CFG_CENTER_NE4BEG1_19", + "CFG_CENTER_LOGIC_OUTS_B8_15", + "CFG_CENTER_LH7_10", + "CFG_CENTER_LOGIC_OUTS_B14_6", + "CFG_CENTER_WW4C3_16", + "CFG_CENTER_EE2BEG2_1", + "CFG_CENTER_WW4END3_2", + "CFG_CENTER_BYP4_0", + "CFG_CENTER_IMUX43_17", + "CFG_CENTER_IMUX18_18", + "CFG_CENTER_CLK0_18", + "CFG_CENTER_NW2A3_15", + "CFG_CENTER_LOGIC_OUTS_B22_10", + "CFG_CENTER_SW4END2_19", + "CFG_CENTER_WW4END3_1", + "CFG_CENTER_SE4C2_13", + "CFG_CENTER_NW2A0_18", + "CFG_CENTER_EE4C3_10", + "CFG_CENTER_IMUX33_15", + "CFG_CENTER_EE4A0_4", + "CFG_CENTER_NW4A2_15", + "CFG_CENTER_SW4A3_10", + "CFG_CENTER_EE2A1_8", + "CFG_CENTER_EE4BEG1_17", + "CFG_CENTER_FAN6_9", + "CFG_CENTER_LH7_11", + "CFG_CENTER_IMUX27_17", + "CFG_CENTER_NE4BEG3_5", + "CFG_CENTER_SW2A1_1", + "CFG_CENTER_EE4A2_9", + "CFG_CENTER_NW2A1_18", + "CFG_CENTER_WL1END3_7", + "CFG_CENTER_EE4BEG3_8", + "CFG_CENTER_LOGIC_OUTS_B10_18", + "CFG_CENTER_SW2A1_0", + "CFG_CENTER_LOGIC_OUTS_B23_13", + "CFG_CENTER_EL1BEG1_10", + "CFG_CENTER_LOGIC_OUTS_B23_19", + "CFG_CENTER_LOGIC_OUTS_B1_4", + "CFG_CENTER_IMUX20_15", + "CFG_CENTER_NE2A1_1", + "CFG_CENTER_EE4C3_19", + "CFG_CENTER_NW2A3_8", + "CFG_CENTER_BLOCK_OUTS_B1_12", + "CFG_CENTER_IMUX32_16", + "CFG_CENTER_LOGIC_OUTS_B17_11", + "CFG_CENTER_LH9_13", + "CFG_CENTER_EE4C2_16", + "CFG_CENTER_EE4C3_17", + "CFG_CENTER_FAN7_15", + "CFG_CENTER_SE4C0_7", + "CFG_CENTER_EE4B1_1", + "CFG_CENTER_EE4BEG3_19", + "CFG_CENTER_ER1BEG2_4", + "CFG_CENTER_NE2A2_13", + "CFG_CENTER_NW4A0_7", + "CFG_CENTER_IMUX9_8", + "CFG_CENTER_SW4END0_10", + "CFG_CENTER_WW4C1_9", + "CFG_CENTER_BOT_USR_ACCESS_DATA14", + "CFG_CENTER_IMUX10_1", + "CFG_CENTER_LOGIC_OUTS_B19_13", + "CFG_CENTER_IMUX35_16", + "CFG_CENTER_SE2A3_16", + "CFG_CENTER_EE4A3_12", + "CFG_CENTER_IMUX22_10", + "CFG_CENTER_ER1BEG3_9", + "CFG_CENTER_LOGIC_OUTS_B18_3", + "CFG_CENTER_SW4END2_3", + "CFG_CENTER_IMUX13_14", + "CFG_CENTER_WW2A0_2", + "CFG_CENTER_LH5_12", + "CFG_CENTER_LH5_15", + "CFG_CENTER_SW2A3_16", + "CFG_CENTER_LOGIC_OUTS_B7_5", + "CFG_CENTER_NE2A2_2", + "CFG_CENTER_SE2A3_0", + "CFG_CENTER_BYP1_11", + "CFG_CENTER_WW4B3_3", + "CFG_CENTER_NW4A1_13", + "CFG_CENTER_NW4END2_11", + "CFG_CENTER_SE4BEG3_1", + "CFG_CENTER_LOGIC_OUTS_B14_1", + "CFG_CENTER_IMUX39_16", + "CFG_CENTER_FAN6_14", + "CFG_CENTER_BYP0_8", + "CFG_CENTER_EE2A1_17", + "CFG_CENTER_IMUX4_13", + "CFG_CENTER_WL1END3_1", + "CFG_CENTER_SW4A3_16", + "CFG_CENTER_LOGIC_OUTS_B20_17", + "CFG_CENTER_NE4C2_12", + "CFG_CENTER_SE2A2_13", + "CFG_CENTER_WR1END1_5", + "CFG_CENTER_WW4B1_18", + "CFG_CENTER_NE2A3_14", + "CFG_CENTER_NE4BEG2_10", + "CFG_CENTER_BYP4_18", + "CFG_CENTER_IMUX11_7", + "CFG_CENTER_IMUX43_12", + "CFG_CENTER_EE4BEG1_12", + "CFG_CENTER_LH3_1", + "CFG_CENTER_LH3_9", + "CFG_CENTER_IMUX46_9", + "CFG_CENTER_IMUX14_18", + "CFG_CENTER_WL1END0_16", + "CFG_CENTER_LH6_11", + "CFG_CENTER_LOGIC_OUTS_B9_11", + "CFG_CENTER_LOGIC_OUTS_B6_18", + "CFG_CENTER_LH12_10", + "CFG_CENTER_LOGIC_OUTS_B16_1", + "CFG_CENTER_EE2BEG2_3", + "CFG_CENTER_LH3_14", + "CFG_CENTER_IMUX1_13", + "CFG_CENTER_ER1BEG3_14", + "CFG_CENTER_IMUX16_15", + "CFG_CENTER_LOGIC_OUTS_B4_6", + "CFG_CENTER_EE4BEG3_7", + "CFG_CENTER_SE4BEG1_7", + "CFG_CENTER_CLK1_3", + "CFG_CENTER_IMUX40_1", + "CFG_CENTER_SE4BEG2_10", + "CFG_CENTER_SW2A2_19", + "CFG_CENTER_LH1_17", + "CFG_CENTER_IMUX17_16", + "CFG_CENTER_NW4END0_3", + "CFG_CENTER_LOGIC_OUTS_B3_17", + "CFG_CENTER_WL1END3_15", + "CFG_CENTER_ER1BEG3_10", + "CFG_CENTER_LH9_3", + "CFG_CENTER_WW4B0_17", + "CFG_CENTER_EE2A0_12", + "CFG_CENTER_NW4END3_2", + "CFG_CENTER_BOT_USR_ACCESS_DATA2", + "CFG_CENTER_IMUX9_10", + "CFG_CENTER_NW4A2_9", + "CFG_CENTER_IMUX8_4", + "CFG_CENTER_LOGIC_OUTS_B12_1", + "CFG_CENTER_WW4C3_10", + "CFG_CENTER_LOGIC_OUTS_B20_10", + "CFG_CENTER_BYP2_2", + "CFG_CENTER_WW4A2_15", + "CFG_CENTER_SW4A1_4", + "CFG_CENTER_FAN4_14", + "CFG_CENTER_WW4A1_1", + "CFG_CENTER_NW4A1_16", + "CFG_CENTER_EE2BEG1_16", + "CFG_CENTER_FAN1_10", + "CFG_CENTER_IMUX1_10", + "CFG_CENTER_BLOCK_OUTS_B3_10", + "CFG_CENTER_LOGIC_OUTS_B11_17", + "CFG_CENTER_IMUX14_2", + "CFG_CENTER_WW2A2_0", + "CFG_CENTER_WW2A1_17", + "CFG_CENTER_NW4END2_17", + "CFG_CENTER_IMUX0_11", + "CFG_CENTER_IMUX45_2", + "CFG_CENTER_IMUX19_11", + "CFG_CENTER_CLK0_4", + "CFG_CENTER_LOGIC_OUTS_B14_16", + "CFG_CENTER_SE4C2_0", + "CFG_CENTER_IMUX24_15", + "CFG_CENTER_LOGIC_OUTS_B6_6", + "CFG_CENTER_LOGIC_OUTS_B8_5", + "CFG_CENTER_NE4BEG1_14", + "CFG_CENTER_NE2A1_15", + "CFG_CENTER_IMUX25_8", + "CFG_CENTER_BYP6_3", + "CFG_CENTER_WW4C1_16", + "CFG_CENTER_IMUX37_2", + "CFG_CENTER_LH9_12", + "CFG_CENTER_IMUX37_14", + "CFG_CENTER_IMUX23_7", + "CFG_CENTER_NW2A3_3", + "CFG_CENTER_BLOCK_OUTS_B0_2", + "CFG_CENTER_NE2A3_2", + "CFG_CENTER_WR1END2_2", + "CFG_CENTER_WW2A0_7", + "CFG_CENTER_BYP5_10", + "CFG_CENTER_EE2BEG2_16", + "CFG_CENTER_IMUX39_14", + "CFG_CENTER_WW2END2_1", + "CFG_CENTER_EE4BEG1_0", + "CFG_CENTER_WW4END2_2", + "CFG_CENTER_BLOCK_OUTS_B3_17", + "CFG_CENTER_IMUX18_11", + "CFG_CENTER_IMUX28_12", + "CFG_CENTER_SW2A2_14", + "CFG_CENTER_WW4A1_6", + "CFG_CENTER_SW4A2_17", + "CFG_CENTER_NE4C3_14", + "CFG_CENTER_LH7_12", + "CFG_CENTER_WW2A1_10", + "CFG_CENTER_WR1END3_2", + "CFG_CENTER_WW4END3_7", + "CFG_CENTER_BYP7_0", + "CFG_CENTER_BYP6_14", + "CFG_CENTER_EE4C2_5", + "CFG_CENTER_IMUX10_2", + "CFG_CENTER_EE2BEG3_2", + "CFG_CENTER_LOGIC_OUTS_B20_4", + "CFG_CENTER_WL1END1_11", + "CFG_CENTER_EE2A0_6", + "CFG_CENTER_LH5_6", + "CFG_CENTER_IMUX46_6", + "CFG_CENTER_EE2A1_18", + "CFG_CENTER_IMUX6_19", + "CFG_CENTER_IMUX6_12", + "CFG_CENTER_SE4BEG1_19", + "CFG_CENTER_EE4BEG0_1", + "CFG_CENTER_SE2A2_0", + "CFG_CENTER_SW4END1_12", + "CFG_CENTER_IMUX1_17", + "CFG_CENTER_EE4BEG2_2", + "CFG_CENTER_IMUX43_8", + "CFG_CENTER_IMUX22_4", + "CFG_CENTER_WW4END0_5", + "CFG_CENTER_SW4END1_19", + "CFG_CENTER_SW4END1_13", + "CFG_CENTER_WW4B0_13", + "CFG_CENTER_EE4B1_15", + "CFG_CENTER_WW4B2_10", + "CFG_CENTER_IMUX46_0", + "CFG_CENTER_SW4END2_7", + "CFG_CENTER_WW4A1_4", + "CFG_CENTER_SW4A2_18", + "CFG_CENTER_FAN3_3", + "CFG_CENTER_NW2A2_15", + "CFG_CENTER_LOGIC_OUTS_B17_13", + "CFG_CENTER_SE2A2_3", + "CFG_CENTER_IMUX31_9", + "CFG_CENTER_LH7_14", + "CFG_CENTER_EE4B3_9", + "CFG_CENTER_NE4BEG2_8", + "CFG_CENTER_LOGIC_OUTS_B8_17", + "CFG_CENTER_SW4A3_11", + "CFG_CENTER_SE4BEG2_8", + "CFG_CENTER_BYP0_18", + "CFG_CENTER_IMUX16_2", + "CFG_CENTER_SW4END1_1", + "CFG_CENTER_SW4A2_2", + "CFG_CENTER_BYP4_9", + "CFG_CENTER_WW2END2_2", + "CFG_CENTER_BYP2_13", + "CFG_CENTER_IMUX3_10", + "CFG_CENTER_SW2A2_5", + "CFG_CENTER_LOGIC_OUTS_B20_16", + "CFG_CENTER_LOGIC_OUTS_B0_13", + "CFG_CENTER_IMUX8_19", + "CFG_CENTER_LH1_13", + "CFG_CENTER_SE4BEG0_3", + "CFG_CENTER_NW4END1_13", + "CFG_CENTER_LOGIC_OUTS_B1_0", + "CFG_CENTER_SW4END2_8", + "CFG_CENTER_IMUX6_14", + "CFG_CENTER_CTRL1_1", + "CFG_CENTER_EL1BEG2_8", + "CFG_CENTER_NE4BEG0_11", + "CFG_CENTER_SE2A0_10", + "CFG_CENTER_BLOCK_OUTS_B0_11", + "CFG_CENTER_BYP2_0", + "CFG_CENTER_LH7_5", + "CFG_CENTER_IMUX11_8", + "CFG_CENTER_EE4B2_13", + "CFG_CENTER_IMUX41_6", + "CFG_CENTER_LH12_17", + "CFG_CENTER_WW4A3_4", + "CFG_CENTER_WR1END0_2", + "CFG_CENTER_EE2BEG3_17", + "CFG_CENTER_CTRL0_4", + "CFG_CENTER_SW4A2_16", + "CFG_CENTER_IMUX41_12", + "CFG_CENTER_LOGIC_OUTS_B10_9", + "CFG_CENTER_SE4BEG2_15", + "CFG_CENTER_EE4BEG0_19", + "CFG_CENTER_IMUX34_18", + "CFG_CENTER_IMUX28_4", + "CFG_CENTER_NE4BEG1_4", + "CFG_CENTER_IMUX44_17", + "CFG_CENTER_EE4BEG1_15", + "CFG_CENTER_IMUX22_19", + "CFG_CENTER_NE4C3_18", + "CFG_CENTER_EE4B0_12", + "CFG_CENTER_CLK1_0", + "CFG_CENTER_IMUX16_18", + "CFG_CENTER_IMUX45_15", + "CFG_CENTER_IMUX2_4", + "CFG_CENTER_LOGIC_OUTS_B9_10", + "CFG_CENTER_SE4BEG1_17", + "CFG_CENTER_NE2A3_5", + "CFG_CENTER_SE4BEG1_4", + "CFG_CENTER_WL1END3_2", + "CFG_CENTER_ER1BEG2_2", + "CFG_CENTER_SW4A3_18", + "CFG_CENTER_LOGIC_OUTS_B9_7", + "CFG_CENTER_NE2A0_10", + "CFG_CENTER_SE4BEG3_14", + "CFG_CENTER_LOGIC_OUTS_B5_6", + "CFG_CENTER_EL1BEG3_3", + "CFG_CENTER_EE4A1_6", + "CFG_CENTER_WW4B0_3", + "CFG_CENTER_LH1_15", + "CFG_CENTER_BYP1_19", + "CFG_CENTER_LH8_3", + "CFG_CENTER_NW2A0_4", + "CFG_CENTER_IMUX5_2", + "CFG_CENTER_EE2A0_3", + "CFG_CENTER_IMUX14_15", + "CFG_CENTER_WL1END3_8", + "CFG_CENTER_BYP1_8", + "CFG_CENTER_IMUX16_0", + "CFG_CENTER_WW2END3_17", + "CFG_CENTER_BLOCK_OUTS_B3_0", + "CFG_CENTER_IMUX6_3", + "CFG_CENTER_WW4END0_2", + "CFG_CENTER_EE4BEG0_2", + "CFG_CENTER_EE2BEG3_11", + "CFG_CENTER_EE2BEG3_19", + "CFG_CENTER_SW4END2_5", + "CFG_CENTER_EE4A3_4", + "CFG_CENTER_LH8_12", + "CFG_CENTER_WW4END1_9", + "CFG_CENTER_IMUX42_3", + "CFG_CENTER_LOGIC_OUTS_B2_1", + "CFG_CENTER_CLK0_5", + "CFG_CENTER_EL1BEG0_18", + "CFG_CENTER_IMUX1_3", + "CFG_CENTER_WW4A3_3", + "CFG_CENTER_IMUX3_6", + "CFG_CENTER_IMUX32_1", + "CFG_CENTER_SE4BEG3_7", + "CFG_CENTER_WW4C0_11", + "CFG_CENTER_BYP7_8", + "CFG_CENTER_IMUX33_3", + "CFG_CENTER_LH12_12", + "CFG_CENTER_NW2A2_10", + "CFG_CENTER_FAN2_0", + "CFG_CENTER_IMUX1_8", + "CFG_CENTER_ER1BEG2_5", + "CFG_CENTER_WW4END1_1", + "CFG_CENTER_LOGIC_OUTS_B9_12", + "CFG_CENTER_IMUX22_13", + "CFG_CENTER_NW4END3_14", + "CFG_CENTER_LH5_2", + "CFG_CENTER_LOGIC_OUTS_B8_4", + "CFG_CENTER_IMUX29_16", + "CFG_CENTER_SW2A0_15", + "CFG_CENTER_IMUX31_11", + "CFG_CENTER_LH6_12", + "CFG_CENTER_WW4A0_9", + "CFG_CENTER_IMUX24_3", + "CFG_CENTER_EE4C2_13", + "CFG_CENTER_NE2A2_1", + "CFG_CENTER_WW4END0_8", + "CFG_CENTER_SW4END3_9", + "CFG_CENTER_WW4END3_3", + "CFG_CENTER_EL1BEG2_9", + "CFG_CENTER_SW4A1_18", + "CFG_CENTER_IMUX38_19", + "CFG_CENTER_IMUX34_12", + "CFG_CENTER_IMUX44_10", + "CFG_CENTER_IMUX36_12", + "CFG_CENTER_NE2A1_17", + "CFG_CENTER_BYP3_11", + "CFG_CENTER_WW4C3_6", + "CFG_CENTER_WR1END3_12", + "CFG_CENTER_WL1END3_10", + "CFG_CENTER_BLOCK_OUTS_B0_14", + "CFG_CENTER_LOGIC_OUTS_B19_14", + "CFG_CENTER_WL1END3_6", + "CFG_CENTER_IMUX10_10", + "CFG_CENTER_WW2A0_19", + "CFG_CENTER_EE2A0_18", + "CFG_CENTER_IMUX0_1", + "CFG_CENTER_WR1END1_2", + "CFG_CENTER_IMUX4_3", + "CFG_CENTER_FAN4_9", + "CFG_CENTER_BYP0_12", + "CFG_CENTER_NE2A0_12", + "CFG_CENTER_LH5_1", + "CFG_CENTER_NE2A2_17", + "CFG_CENTER_WW2A3_1", + "CFG_CENTER_EE4C2_17", + "CFG_CENTER_IMUX10_19", + "CFG_CENTER_WW2A1_0", + "CFG_CENTER_IMUX9_9", + "CFG_CENTER_BYP5_4", + "CFG_CENTER_NW4END2_7", + "CFG_CENTER_IMUX35_10", + "CFG_CENTER_SE4BEG0_4", + "CFG_CENTER_FAN4_17", + "CFG_CENTER_EE4BEG2_17", + "CFG_CENTER_LH2_11", + "CFG_CENTER_IMUX34_15", + "CFG_CENTER_WL1END2_5", + "CFG_CENTER_IMUX47_2", + "CFG_CENTER_LOGIC_OUTS_B1_5", + "CFG_CENTER_NE4BEG1_9", + "CFG_CENTER_SW4END3_3", + "CFG_CENTER_NE2A3_9", + "CFG_CENTER_LH3_16", + "CFG_CENTER_NE4BEG3_0", + "CFG_CENTER_SW4END3_1", + "CFG_CENTER_LOGIC_OUTS_B4_4", + "CFG_CENTER_NW4A3_17", + "CFG_CENTER_IMUX32_7", + "CFG_CENTER_IMUX27_11", + "CFG_CENTER_IMUX47_10", + "CFG_CENTER_EE4A0_8", + "CFG_CENTER_LOGIC_OUTS_B14_4", + "CFG_CENTER_SW4END0_4", + "CFG_CENTER_NW4END3_19", + "CFG_CENTER_IMUX23_17", + "CFG_CENTER_LOGIC_OUTS_B14_3", + "CFG_CENTER_LOGIC_OUTS_B7_11", + "CFG_CENTER_WW4END0_6", + "CFG_CENTER_LOGIC_OUTS_B2_17", + "CFG_CENTER_SE4C0_14", + "CFG_CENTER_NW2A2_14", + "CFG_CENTER_FAN3_7", + "CFG_CENTER_WW4B0_8", + "CFG_CENTER_WW4A0_5", + "CFG_CENTER_NW2A3_6", + "CFG_CENTER_EE2A1_3", + "CFG_CENTER_NW4A1_1", + "CFG_CENTER_IMUX6_15", + "CFG_CENTER_LH10_0", + "CFG_CENTER_IMUX18_13", + "CFG_CENTER_FAN4_13", + "CFG_CENTER_IMUX32_6", + "CFG_CENTER_NE4BEG0_5", + "CFG_CENTER_WW2A0_13", + "CFG_CENTER_FAN1_3", + "CFG_CENTER_IMUX13_6", + "CFG_CENTER_IMUX47_8", + "CFG_CENTER_LOGIC_OUTS_B6_11", + "CFG_CENTER_NW4A1_15", + "CFG_CENTER_NW4END3_8", + "CFG_CENTER_NW2A2_13", + "CFG_CENTER_BLOCK_OUTS_B1_17", + "CFG_CENTER_BYP7_6", + "CFG_CENTER_NW4A0_6", + "CFG_CENTER_WW2A3_0", + "CFG_CENTER_LOGIC_OUTS_B4_14", + "CFG_CENTER_WW2END1_0", + "CFG_CENTER_BYP1_14", + "CFG_CENTER_LOGIC_OUTS_B1_9", + "CFG_CENTER_LH5_19", + "CFG_CENTER_IMUX33_8", + "CFG_CENTER_IMUX19_4", + "CFG_CENTER_WR1END0_11", + "CFG_CENTER_SW4A3_13", + "CFG_CENTER_ER1BEG2_16", + "CFG_CENTER_FAN0_16", + "CFG_CENTER_ER1BEG1_11", + "CFG_CENTER_NW2A1_3", + "CFG_CENTER_NW2A1_5", + "CFG_CENTER_LOGIC_OUTS_B19_6", + "CFG_CENTER_SE2A0_11", + "CFG_CENTER_WW4B0_1", + "CFG_CENTER_LOGIC_OUTS_B1_11", + "CFG_CENTER_LH3_5", + "CFG_CENTER_EE4A3_8", + "CFG_CENTER_WW4C3_1", + "CFG_CENTER_WW2END0_4", + "CFG_CENTER_IMUX18_10", + "CFG_CENTER_IMUX35_13", + "CFG_CENTER_LH12_11", + "CFG_CENTER_EE2A2_10", + "CFG_CENTER_NW4A1_19", + "CFG_CENTER_IMUX18_7", + "CFG_CENTER_EE2A1_11", + "CFG_CENTER_IMUX11_19", + "CFG_CENTER_IMUX28_15", + "CFG_CENTER_EE4BEG3_17", + "CFG_CENTER_NE4BEG0_6", + "CFG_CENTER_LH6_1", + "CFG_CENTER_SW4END0_7", + "CFG_CENTER_IMUX45_3", + "CFG_CENTER_EL1BEG2_1", + "CFG_CENTER_SW2A0_18", + "CFG_CENTER_WW4A1_17", + "CFG_CENTER_WW4END2_4", + "CFG_CENTER_BLOCK_OUTS_B1_1", + "CFG_CENTER_CTRL0_9", + "CFG_CENTER_NE4BEG2_1", + "CFG_CENTER_BYP0_14", + "CFG_CENTER_BLOCK_OUTS_B2_6", + "CFG_CENTER_WR1END3_14", + "CFG_CENTER_LOGIC_OUTS_B6_3", + "CFG_CENTER_LOGIC_OUTS_B13_16", + "CFG_CENTER_FAN7_14", + "CFG_CENTER_ER1BEG0_19", + "CFG_CENTER_IMUX0_12", + "CFG_CENTER_IMUX13_5", + "CFG_CENTER_EE2BEG1_10", + "CFG_CENTER_WW2END2_3", + "CFG_CENTER_LOGIC_OUTS_B8_16", + "CFG_CENTER_IMUX44_13", + "CFG_CENTER_WL1END1_13", + "CFG_CENTER_IMUX45_7", + "CFG_CENTER_IMUX25_6", + "CFG_CENTER_NW4A2_6", + "CFG_CENTER_LH8_11", + "CFG_CENTER_LH4_13", + "CFG_CENTER_NW4A2_14", + "CFG_CENTER_FAN6_3", + "CFG_CENTER_FAN5_1", + "CFG_CENTER_SW2A1_14", + "CFG_CENTER_ER1BEG0_2", + "CFG_CENTER_CLK0_13", + "CFG_CENTER_BYP5_0", + "CFG_CENTER_WR1END3_18", + "CFG_CENTER_NW4END2_16", + "CFG_CENTER_WW4A0_10", + "CFG_CENTER_LOGIC_OUTS_B6_10", + "CFG_CENTER_SE4BEG1_13", + "CFG_CENTER_LH6_16", + "CFG_CENTER_LH12_1", + "CFG_CENTER_IMUX27_14", + "CFG_CENTER_SW2A1_5", + "CFG_CENTER_BLOCK_OUTS_B1_6", + "CFG_CENTER_LOGIC_OUTS_B9_13", + "CFG_CENTER_WR1END0_12", + "CFG_CENTER_LH1_4", + "CFG_CENTER_IMUX16_3", + "CFG_CENTER_EE4BEG2_16", + "CFG_CENTER_WW4C1_0", + "CFG_CENTER_LOGIC_OUTS_B7_8", + "CFG_CENTER_WW4A3_7", + "CFG_CENTER_SE4C3_10", + "CFG_CENTER_SE2A1_0", + "CFG_CENTER_NW2A2_17", + "CFG_CENTER_WW2END3_12", + "CFG_CENTER_WW2A1_7", + "CFG_CENTER_LOGIC_OUTS_B7_9", + "CFG_CENTER_LH2_18", + "CFG_CENTER_BYP2_17", + "CFG_CENTER_LH2_13", + "CFG_CENTER_IMUX7_0", + "CFG_CENTER_EE4C0_8", + "CFG_CENTER_IMUX43_14", + "CFG_CENTER_WL1END1_15", + "CFG_CENTER_LOGIC_OUTS_B8_18", + "CFG_CENTER_SE4BEG0_11", + "CFG_CENTER_LOGIC_OUTS_B10_4", + "CFG_CENTER_WW4END0_17", + "CFG_CENTER_SE2A1_1", + "CFG_CENTER_IMUX11_12", + "CFG_CENTER_IMUX36_18", + "CFG_CENTER_LH7_17", + "CFG_CENTER_SE2A2_12", + "CFG_CENTER_FAN6_19", + "CFG_CENTER_EE2A3_9", + "CFG_CENTER_IMUX33_14", + "CFG_CENTER_NW4A2_2", + "CFG_CENTER_NW2A3_19", + "CFG_CENTER_LOGIC_OUTS_B6_4", + "CFG_CENTER_SE2A1_16", + "CFG_CENTER_NW2A1_12", + "CFG_CENTER_EE4A3_17", + "CFG_CENTER_WW4C3_15", + "CFG_CENTER_SE4BEG1_5", + "CFG_CENTER_EE4C2_10", + "CFG_CENTER_WW4A0_19", + "CFG_CENTER_LOGIC_OUTS_B12_10", + "CFG_CENTER_WW2A0_3", + "CFG_CENTER_SW2A2_17", + "CFG_CENTER_WW4END0_15", + "CFG_CENTER_LH1_6", + "CFG_CENTER_SW4A0_10", + "CFG_CENTER_NE4C3_16", + "CFG_CENTER_LH12_13", + "CFG_CENTER_SE4BEG0_14", + "CFG_CENTER_EE2BEG3_8", + "CFG_CENTER_BYP4_19", + "CFG_CENTER_IMUX5_15", + "CFG_CENTER_IMUX23_15", + "CFG_CENTER_NE2A3_18", + "CFG_CENTER_LOGIC_OUTS_B0_16", + "CFG_CENTER_ER1BEG0_16", + "CFG_CENTER_LOGIC_OUTS_B13_13", + "CFG_CENTER_SW4A2_8", + "CFG_CENTER_LOGIC_OUTS_B13_19", + "CFG_CENTER_WL1END1_9", + "CFG_CENTER_BYP0_3", + "CFG_CENTER_IMUX21_5", + "CFG_CENTER_BYP0_1", + "CFG_CENTER_IMUX19_15", + "CFG_CENTER_SE4C0_11", + "CFG_CENTER_WW4B2_18", + "CFG_CENTER_IMUX17_9", + "CFG_CENTER_IMUX23_5", + "CFG_CENTER_EE4BEG0_16", + "CFG_CENTER_LH2_19", + "CFG_CENTER_IMUX41_4", + "CFG_CENTER_LH12_6", + "CFG_CENTER_LOGIC_OUTS_B15_6", + "CFG_CENTER_EE4C2_2", + "CFG_CENTER_EE4BEG1_19", + "CFG_CENTER_LOGIC_OUTS_B9_17", + "CFG_CENTER_NE2A0_7", + "CFG_CENTER_LOGIC_OUTS_B3_10", + "CFG_CENTER_WW4C0_4", + "CFG_CENTER_WR1END3_9", + "CFG_CENTER_IMUX21_15", + "CFG_CENTER_EE2A2_0", + "CFG_CENTER_IMUX11_5", + "CFG_CENTER_WW4END1_15", + "CFG_CENTER_FAN0_14", + "CFG_CENTER_BYP0_15", + "CFG_CENTER_IMUX21_8", + "CFG_CENTER_LOGIC_OUTS_B12_11", + "CFG_CENTER_WW4END1_7", + "CFG_CENTER_LOGIC_OUTS_B8_19", + "CFG_CENTER_EE4BEG3_10", + "CFG_CENTER_LH1_19", + "CFG_CENTER_IMUX40_10", + "CFG_CENTER_LH6_10", + "CFG_CENTER_FAN1_13", + "CFG_CENTER_EE2A3_6", + "CFG_CENTER_NE2A3_10", + "CFG_CENTER_LH11_17", + "CFG_CENTER_IMUX41_2", + "CFG_CENTER_LOGIC_OUTS_B16_0", + "CFG_CENTER_LH4_14", + "CFG_CENTER_IMUX6_16", + "CFG_CENTER_SW4END0_5", + "CFG_CENTER_IMUX6_9", + "CFG_CENTER_EE2A3_1", + "CFG_CENTER_EE4A2_2", + "CFG_CENTER_LOGIC_OUTS_B10_8", + "CFG_CENTER_LH9_1", + "CFG_CENTER_IMUX44_18", + "CFG_CENTER_BYP7_18", + "CFG_CENTER_ER1BEG3_15", + "CFG_CENTER_FAN1_7", + "CFG_CENTER_NW4A3_1", + "CFG_CENTER_WW4END3_5", + "CFG_CENTER_WW4B1_15", + "CFG_CENTER_NE4C3_15", + "CFG_CENTER_LOGIC_OUTS_B9_5", + "CFG_CENTER_LOGIC_OUTS_B23_4", + "CFG_CENTER_IMUX20_2", + "CFG_CENTER_EE4B2_1", + "CFG_CENTER_EL1BEG2_5", + "CFG_CENTER_LOGIC_OUTS_B4_18", + "CFG_CENTER_LH1_11", + "CFG_CENTER_BYP3_1", + "CFG_CENTER_WR1END2_12", + "CFG_CENTER_FAN1_8", + "CFG_CENTER_WR1END2_14", + "CFG_CENTER_EL1BEG2_17", + "CFG_CENTER_SW4A3_12", + "CFG_CENTER_SW2A3_8", + "CFG_CENTER_LOGIC_OUTS_B18_9", + "CFG_CENTER_EL1BEG1_9", + "CFG_CENTER_NE4BEG1_3", + "CFG_CENTER_IMUX37_11", + "CFG_CENTER_IMUX19_18", + "CFG_CENTER_SE4C3_18", + "CFG_CENTER_BYP0_9", + "CFG_CENTER_IMUX44_2", + "CFG_CENTER_EE4BEG0_11", + "CFG_CENTER_EE2BEG3_14", + "CFG_CENTER_NE2A2_8", + "CFG_CENTER_WW4A3_17", + "CFG_CENTER_LOGIC_OUTS_B7_19", + "CFG_CENTER_IMUX42_10", + "CFG_CENTER_EE4A2_17", + "CFG_CENTER_IMUX36_17", + "CFG_CENTER_BYP6_8", + "CFG_CENTER_IMUX31_5", + "CFG_CENTER_IMUX25_17", + "CFG_CENTER_IMUX25_1", + "CFG_CENTER_FAN6_2", + "CFG_CENTER_LH2_16", + "CFG_CENTER_LOGIC_OUTS_B15_13", + "CFG_CENTER_WW2A2_12", + "CFG_CENTER_FAN4_3", + "CFG_CENTER_IMUX20_13", + "CFG_CENTER_IMUX1_9", + "CFG_CENTER_EE4B2_8", + "CFG_CENTER_LOGIC_OUTS_B21_12", + "CFG_CENTER_CTRL0_7", + "CFG_CENTER_NE4BEG3_19", + "CFG_CENTER_IMUX12_7", + "CFG_CENTER_LOGIC_OUTS_B18_12", + "CFG_CENTER_LH11_7", + "CFG_CENTER_LOGIC_OUTS_B2_7", + "CFG_CENTER_IMUX1_18", + "CFG_CENTER_WR1END0_14", + "CFG_CENTER_LH6_18", + "CFG_CENTER_LH9_11", + "CFG_CENTER_EE4C0_4", + "CFG_CENTER_NW2A0_7", + "CFG_CENTER_BYP4_1", + "CFG_CENTER_WR1END1_9", + "CFG_CENTER_NE2A3_6", + "CFG_CENTER_FAN3_5", + "CFG_CENTER_NW4A1_3", + "CFG_CENTER_NE4C3_10", + "CFG_CENTER_WW4END1_4", + "CFG_CENTER_WL1END1_19", + "CFG_CENTER_SE2A2_10", + "CFG_CENTER_FAN3_18", + "CFG_CENTER_NE2A0_16", + "CFG_CENTER_NE2A0_18", + "CFG_CENTER_LOGIC_OUTS_B3_16", + "CFG_CENTER_EE4C2_8", + "CFG_CENTER_FAN0_0", + "CFG_CENTER_NE4C2_13", + "CFG_CENTER_IMUX33_18", + "CFG_CENTER_WW2A2_4", + "CFG_CENTER_CTRL0_2", + "CFG_CENTER_LOGIC_OUTS_B1_6", + "CFG_CENTER_WW4C2_6", + "CFG_CENTER_IMUX44_3", + "CFG_CENTER_IMUX30_13", + "CFG_CENTER_EE4BEG0_17", + "CFG_CENTER_WW2END3_18", + "CFG_CENTER_EE4BEG2_15", + "CFG_CENTER_LOGIC_OUTS_B2_4", + "CFG_CENTER_CTRL0_8", + "CFG_CENTER_IMUX22_8", + "CFG_CENTER_NE4C1_12", + "CFG_CENTER_EE4B0_9", + "CFG_CENTER_IMUX19_6", + "CFG_CENTER_IMUX20_8", + "CFG_CENTER_IMUX31_13", + "CFG_CENTER_IMUX23_9", + "CFG_CENTER_SW2A2_0", + "CFG_CENTER_WW2END1_11", + "CFG_CENTER_IMUX37_7", + "CFG_CENTER_NW4A2_16", + "CFG_CENTER_WW4B2_0", + "CFG_CENTER_IMUX21_17", + "CFG_CENTER_BOT_USR_ACCESS_DATA10", + "CFG_CENTER_NE2A1_12", + "CFG_CENTER_IMUX32_3", + "CFG_CENTER_LOGIC_OUTS_B15_12", + "CFG_CENTER_LOGIC_OUTS_B10_14", + "CFG_CENTER_SE4BEG2_4", + "CFG_CENTER_FAN0_18", + "CFG_CENTER_EE2A0_16", + "CFG_CENTER_IMUX39_3", + "CFG_CENTER_SE2A1_7", + "CFG_CENTER_EE2BEG0_16", + "CFG_CENTER_WW4B0_6", + "CFG_CENTER_SW4END0_6", + "CFG_CENTER_SW4A0_5", + "CFG_CENTER_IMUX36_9", + "CFG_CENTER_FAN2_18", + "CFG_CENTER_BLOCK_OUTS_B3_19", + "CFG_CENTER_BYP7_13", + "CFG_CENTER_SE4C2_19", + "CFG_CENTER_IMUX11_16", + "CFG_CENTER_WW2END2_9", + "CFG_CENTER_EE4A2_8", + "CFG_CENTER_LOGIC_OUTS_B9_16", + "CFG_CENTER_NE4C2_10", + "CFG_CENTER_WW4B1_10", + "CFG_CENTER_EE4BEG0_14", + "CFG_CENTER_IMUX35_11", + "CFG_CENTER_WW4C0_15", + "CFG_CENTER_EE2A2_13", + "CFG_CENTER_BYP3_2", + "CFG_CENTER_ER1BEG2_18", + "CFG_CENTER_IMUX40_7", + "CFG_CENTER_NW2A1_8", + "CFG_CENTER_IMUX11_11", + "CFG_CENTER_LOGIC_OUTS_B23_5", + "CFG_CENTER_WL1END0_11", + "CFG_CENTER_EE4BEG2_10", + "CFG_CENTER_WL1END2_19", + "CFG_CENTER_LOGIC_OUTS_B0_12", + "CFG_CENTER_SW2A2_7", + "CFG_CENTER_SW4END1_6", + "CFG_CENTER_IMUX37_4", + "CFG_CENTER_LH4_8", + "CFG_CENTER_WW4C3_0", + "CFG_CENTER_EE2A1_9", + "CFG_CENTER_IMUX32_9", + "CFG_CENTER_WW4A1_2", + "CFG_CENTER_SE4BEG3_16", + "CFG_CENTER_CLK0_14", + "CFG_CENTER_IMUX28_5", + "CFG_CENTER_WW2A2_16", + "CFG_CENTER_IMUX25_12", + "CFG_CENTER_NE2A1_19", + "CFG_CENTER_BLOCK_OUTS_B0_8", + "CFG_CENTER_NW2A0_2", + "CFG_CENTER_IMUX9_4", + "CFG_CENTER_NW2A3_2", + "CFG_CENTER_NE4C3_0", + "CFG_CENTER_NE4BEG0_16", + "CFG_CENTER_LH3_18", + "CFG_CENTER_WW4END3_13", + "CFG_CENTER_NW4A0_18", + "CFG_CENTER_NW2A3_1", + "CFG_CENTER_IMUX47_1", + "CFG_CENTER_IMUX30_0", + "CFG_CENTER_NE2A0_15", + "CFG_CENTER_IMUX0_8", + "CFG_CENTER_LOGIC_OUTS_B8_12", + "CFG_CENTER_BYP6_12", + "CFG_CENTER_IMUX32_15", + "CFG_CENTER_LH8_14", + "CFG_CENTER_IMUX5_4", + "CFG_CENTER_IMUX27_3", + "CFG_CENTER_BYP0_19", + "CFG_CENTER_IMUX17_6", + "CFG_CENTER_LOGIC_OUTS_B18_10", + "CFG_CENTER_WW4B1_12", + "CFG_CENTER_IMUX0_5", + "CFG_CENTER_WW4A2_8", + "CFG_CENTER_IMUX28_18", + "CFG_CENTER_NW4A3_14", + "CFG_CENTER_LOGIC_OUTS_B18_19", + "CFG_CENTER_WW2END3_19", + "CFG_CENTER_ER1BEG0_6", + "CFG_CENTER_LOGIC_OUTS_B11_9", + "CFG_CENTER_IMUX8_7", + "CFG_CENTER_EL1BEG2_16", + "CFG_CENTER_NW2A3_5", + "CFG_CENTER_ER1BEG1_15", + "CFG_CENTER_IMUX8_1", + "CFG_CENTER_IMUX38_14", + "CFG_CENTER_BYP5_11", + "CFG_CENTER_EE4A2_1", + "CFG_CENTER_IMUX33_19", + "CFG_CENTER_LH10_15", + "CFG_CENTER_LH2_12", + "CFG_CENTER_IMUX27_5", + "CFG_CENTER_EE2BEG3_5", + "CFG_CENTER_BYP3_19", + "CFG_CENTER_WR1END0_8", + "CFG_CENTER_WW2END2_11", + "CFG_CENTER_LH3_12", + "CFG_CENTER_BYP3_9", + "CFG_CENTER_WW4B1_19", + "CFG_CENTER_SE4C3_11", + "CFG_CENTER_EE2BEG3_7", + "CFG_CENTER_WW4C0_14", + "CFG_CENTER_EE4A0_1", + "CFG_CENTER_EE2BEG2_11", + "CFG_CENTER_EE4C2_14", + "CFG_CENTER_LOGIC_OUTS_B1_16", + "CFG_CENTER_NE4BEG2_7", + "CFG_CENTER_LOGIC_OUTS_B17_16", + "CFG_CENTER_LOGIC_OUTS_B21_6", + "CFG_CENTER_CTRL0_5", + "CFG_CENTER_BYP6_7", + "CFG_CENTER_NW4A0_9", + "CFG_CENTER_IMUX26_8", + "CFG_CENTER_IMUX5_16", + "CFG_CENTER_EL1BEG2_19", + "CFG_CENTER_BLOCK_OUTS_B1_8", + "CFG_CENTER_EE4A1_9", + "CFG_CENTER_LH2_15", + "CFG_CENTER_IMUX11_13", + "CFG_CENTER_LOGIC_OUTS_B3_11", + "CFG_CENTER_LH12_3", + "CFG_CENTER_LOGIC_OUTS_B8_9", + "CFG_CENTER_IMUX9_17", + "CFG_CENTER_BYP2_10", + "CFG_CENTER_EE2A1_15", + "CFG_CENTER_LOGIC_OUTS_B16_5", + "CFG_CENTER_EL1BEG0_2", + "CFG_CENTER_WW4B2_16", + "CFG_CENTER_IMUX35_8", + "CFG_CENTER_BYP5_13", + "CFG_CENTER_WR1END1_19", + "CFG_CENTER_IMUX2_6", + "CFG_CENTER_LOGIC_OUTS_B19_10", + "CFG_CENTER_IMUX20_9", + "CFG_CENTER_IMUX46_11", + "CFG_CENTER_IMUX44_16", + "CFG_CENTER_LOGIC_OUTS_B18_2", + "CFG_CENTER_EE4C3_15", + "CFG_CENTER_BYP4_17", + "CFG_CENTER_WW2END1_9", + "CFG_CENTER_EE2A1_12", + "CFG_CENTER_LOGIC_OUTS_B3_14", + "CFG_CENTER_SW4A3_7", + "CFG_CENTER_IMUX0_19", + "CFG_CENTER_FAN0_3", + "CFG_CENTER_WL1END0_12", + "CFG_CENTER_IMUX6_8", + "CFG_CENTER_EE2BEG2_17", + "CFG_CENTER_WW4B0_2", + "CFG_CENTER_IMUX46_4", + "CFG_CENTER_EE4A1_3", + "CFG_CENTER_BYP6_4", + "CFG_CENTER_IMUX7_15", + "CFG_CENTER_SE4C1_6", + "CFG_CENTER_WW4C3_18", + "CFG_CENTER_IMUX30_17", + "CFG_CENTER_LOGIC_OUTS_B21_8", + "CFG_CENTER_EE2A3_17", + "CFG_CENTER_ER1BEG1_10", + "CFG_CENTER_NW4END0_7", + "CFG_CENTER_LOGIC_OUTS_B4_8", + "CFG_CENTER_WW4A3_15", + "CFG_CENTER_EE2A3_0", + "CFG_CENTER_LH2_7", + "CFG_CENTER_IMUX37_16", + "CFG_CENTER_SE4C1_7", + "CFG_CENTER_SE2A3_5", + "CFG_CENTER_IMUX38_9", + "CFG_CENTER_IMUX14_13", + "CFG_CENTER_WW4B2_12", + "CFG_CENTER_IMUX32_8", + "CFG_CENTER_FAN7_19", + "CFG_CENTER_EE2BEG2_5", + "CFG_CENTER_EL1BEG3_19", + "CFG_CENTER_IMUX32_12", + "CFG_CENTER_WW4A1_12", + "CFG_CENTER_SE4BEG1_16", + "CFG_CENTER_LOGIC_OUTS_B8_8", + "CFG_CENTER_LOGIC_OUTS_B5_11", + "CFG_CENTER_LOGIC_OUTS_B18_1", + "CFG_CENTER_WL1END2_15", + "CFG_CENTER_LOGIC_OUTS_B0_1", + "CFG_CENTER_IMUX42_1", + "CFG_CENTER_SE2A2_18", + "CFG_CENTER_WW2A1_11", + "CFG_CENTER_LOGIC_OUTS_B7_18", + "CFG_CENTER_LH12_19", + "CFG_CENTER_WW2A1_15", + "CFG_CENTER_SE4BEG1_11", + "CFG_CENTER_FAN7_11", + "CFG_CENTER_FAN6_0", + "CFG_CENTER_NE2A3_4", + "CFG_CENTER_LOGIC_OUTS_B7_17", + "CFG_CENTER_LH10_8", + "CFG_CENTER_FAN3_13", + "CFG_CENTER_WW4B1_6", + "CFG_CENTER_LH6_8", + "CFG_CENTER_LH9_8", + "CFG_CENTER_CLK0_3", + "CFG_CENTER_FAN7_12", + "CFG_CENTER_EE4B3_13", + "CFG_CENTER_IMUX13_4", + "CFG_CENTER_BYP4_15", + "CFG_CENTER_NE2A2_11", + "CFG_CENTER_LH7_3", + "CFG_CENTER_LOGIC_OUTS_B22_4", + "CFG_CENTER_EE4B3_10", + "CFG_CENTER_WW4C2_0", + "CFG_CENTER_IMUX1_4", + "CFG_CENTER_WW4B0_7", + "CFG_CENTER_EE2BEG1_6", + "CFG_CENTER_IMUX2_18", + "CFG_CENTER_EE4C2_0", + "CFG_CENTER_LOGIC_OUTS_B9_9", + "CFG_CENTER_SW2A0_11", + "CFG_CENTER_CLK0_17", + "CFG_CENTER_WW2END1_18", + "CFG_CENTER_WW4A0_6", + "CFG_CENTER_EE4C2_18", + "CFG_CENTER_LH4_19", + "CFG_CENTER_IMUX2_19", + "CFG_CENTER_SE4C0_10", + "CFG_CENTER_NE4C3_6", + "CFG_CENTER_EE2A0_11", + "CFG_CENTER_ER1BEG0_5", + "CFG_CENTER_SE2A3_1", + "CFG_CENTER_WW4END3_19", + "CFG_CENTER_IMUX4_4", + "CFG_CENTER_EE4BEG1_1", + "CFG_CENTER_EL1BEG1_11", + "CFG_CENTER_IMUX37_5", + "CFG_CENTER_BLOCK_OUTS_B0_16", + "CFG_CENTER_SW4A3_5", + "CFG_CENTER_EE4A3_14", + "CFG_CENTER_WW4C2_2", + "CFG_CENTER_LOGIC_OUTS_B14_9", + "CFG_CENTER_EE2A1_19", + "CFG_CENTER_EE2BEG0_2", + "CFG_CENTER_LH1_2", + "CFG_CENTER_IMUX29_17", + "CFG_CENTER_WW4END1_12", + "CFG_CENTER_SW4A0_14", + "CFG_CENTER_IMUX31_10", + "CFG_CENTER_CTRL0_1", + "CFG_CENTER_IMUX26_6", + "CFG_CENTER_LOGIC_OUTS_B18_18", + "CFG_CENTER_SW4A1_11", + "CFG_CENTER_BYP0_11", + "CFG_CENTER_BLOCK_OUTS_B3_7", + "CFG_CENTER_ER1BEG0_1", + "CFG_CENTER_NW4A1_14", + "CFG_CENTER_LOGIC_OUTS_B15_9", + "CFG_CENTER_LOGIC_OUTS_B1_17", + "CFG_CENTER_LOGIC_OUTS_B14_7", + "CFG_CENTER_WW4A2_9", + "CFG_CENTER_EE4C0_7", + "CFG_CENTER_BYP7_16", + "CFG_CENTER_LOGIC_OUTS_B22_14", + "CFG_CENTER_NE2A2_7", + "CFG_CENTER_LH12_8", + "CFG_CENTER_IMUX25_19", + "CFG_CENTER_LOGIC_OUTS_B4_11", + "CFG_CENTER_WR1END1_7", + "CFG_CENTER_EE4B3_12", + "CFG_CENTER_LOGIC_OUTS_B12_13", + "CFG_CENTER_BYP1_10", + "CFG_CENTER_NE4BEG1_2", + "CFG_CENTER_NE2A3_15", + "CFG_CENTER_IMUX43_9", + "CFG_CENTER_IMUX5_0", + "CFG_CENTER_EE4A1_12", + "CFG_CENTER_LOGIC_OUTS_B7_14", + "CFG_CENTER_NE4BEG2_18", + "CFG_CENTER_IMUX23_0", + "CFG_CENTER_SE4C0_15", + "CFG_CENTER_IMUX2_15", + "CFG_CENTER_NE4BEG0_13", + "CFG_CENTER_SE2A0_7", + "CFG_CENTER_BYP1_13", + "CFG_CENTER_NW4END0_2", + "CFG_CENTER_WW2A0_5", + "CFG_CENTER_ER1BEG0_18", + "CFG_CENTER_IMUX18_0", + "CFG_CENTER_LOGIC_OUTS_B23_14", + "CFG_CENTER_SE2A1_4", + "CFG_CENTER_LH9_9", + "CFG_CENTER_IMUX42_9", + "CFG_CENTER_FAN7_17", + "CFG_CENTER_SW2A2_16", + "CFG_CENTER_NE4BEG2_6", + "CFG_CENTER_IMUX45_19", + "CFG_CENTER_SW4A2_7", + "CFG_CENTER_WL1END2_10", + "CFG_CENTER_LOGIC_OUTS_B2_11", + "CFG_CENTER_NE4BEG3_3", + "CFG_CENTER_IMUX9_1", + "CFG_CENTER_IMUX17_19", + "CFG_CENTER_WW4A1_18", + "CFG_CENTER_WW4B2_1", + "CFG_CENTER_WR1END3_10", + "CFG_CENTER_LOGIC_OUTS_B23_10", + "CFG_CENTER_WW2A0_1", + "CFG_CENTER_NW4A1_7", + "CFG_CENTER_LOGIC_OUTS_B10_2", + "CFG_CENTER_LOGIC_OUTS_B22_1", + "CFG_CENTER_WW2A1_1", + "CFG_CENTER_SE4BEG3_4", + "CFG_CENTER_SE2A1_10", + "CFG_CENTER_IMUX7_10", + "CFG_CENTER_WR1END2_15", + "CFG_CENTER_LOGIC_OUTS_B14_14", + "CFG_CENTER_WW2END3_4", + "CFG_CENTER_BYP3_14", + "CFG_CENTER_SW4A0_0", + "CFG_CENTER_LH3_11", + "CFG_CENTER_WW4C1_18", + "CFG_CENTER_NW4A0_15", + "CFG_CENTER_NW4END3_15", + "CFG_CENTER_IMUX16_14", + "CFG_CENTER_WW4C2_17", + "CFG_CENTER_IMUX8_9", + "CFG_CENTER_LH5_5", + "CFG_CENTER_SW4A0_19", + "CFG_CENTER_SW2A1_17", + "CFG_CENTER_FAN7_9", + "CFG_CENTER_IMUX38_3", + "CFG_CENTER_EE2BEG0_15", + "CFG_CENTER_IMUX26_18", + "CFG_CENTER_NW4END0_5", + "CFG_CENTER_IMUX29_19", + "CFG_CENTER_EE4C0_0", + "CFG_CENTER_NW4A1_11", + "CFG_CENTER_IMUX36_3", + "CFG_CENTER_NE2A0_19", + "CFG_CENTER_CLK1_12", + "CFG_CENTER_EE4BEG0_9", + "CFG_CENTER_IMUX16_13", + "CFG_CENTER_ER1BEG3_18", + "CFG_CENTER_IMUX4_17", + "CFG_CENTER_IMUX36_13", + "CFG_CENTER_LH10_13", + "CFG_CENTER_LOGIC_OUTS_B2_6", + "CFG_CENTER_WL1END1_5", + "CFG_CENTER_EE4C1_5", + "CFG_CENTER_WW4C3_12", + "CFG_CENTER_WR1END2_10", + "CFG_CENTER_BYP7_3", + "CFG_CENTER_EE4C2_6", + "CFG_CENTER_BLOCK_OUTS_B3_18", + "CFG_CENTER_LOGIC_OUTS_B18_4", + "CFG_CENTER_IMUX36_6", + "CFG_CENTER_IMUX5_1", + "CFG_CENTER_FAN7_4", + "CFG_CENTER_IMUX34_4", + "CFG_CENTER_WL1END3_19", + "CFG_CENTER_IMUX3_15", + "CFG_CENTER_IMUX18_15", + "CFG_CENTER_EE2BEG2_13", + "CFG_CENTER_WW4C3_8", + "CFG_CENTER_ER1BEG3_16", + "CFG_CENTER_EE4C0_3", + "CFG_CENTER_EE2A0_9", + "CFG_CENTER_IMUX30_5", + "CFG_CENTER_LH6_17", + "CFG_CENTER_LH8_18", + "CFG_CENTER_EE4A3_5", + "CFG_CENTER_IMUX28_1", + "CFG_CENTER_IMUX18_4", + "CFG_CENTER_LOGIC_OUTS_B3_1", + "CFG_CENTER_FAN1_9", + "CFG_CENTER_NW2A0_0", + "CFG_CENTER_IMUX20_4", + "CFG_CENTER_BLOCK_OUTS_B2_18", + "CFG_CENTER_WR1END0_16", + "CFG_CENTER_FAN1_6", + "CFG_CENTER_FAN0_13", + "CFG_CENTER_IMUX29_18", + "CFG_CENTER_SE4C3_16", + "CFG_CENTER_IMUX21_9", + "CFG_CENTER_IMUX2_3", + "CFG_CENTER_SE2A2_5", + "CFG_CENTER_EE2A1_4", + "CFG_CENTER_EE4C2_4", + "CFG_CENTER_IMUX43_10", + "CFG_CENTER_FAN0_1", + "CFG_CENTER_LOGIC_OUTS_B22_12", + "CFG_CENTER_IMUX43_19", + "CFG_CENTER_EE4C3_8", + "CFG_CENTER_LOGIC_OUTS_B21_7", + "CFG_CENTER_EE2BEG3_6", + "CFG_CENTER_LH12_2", + "CFG_CENTER_IMUX15_13", + "CFG_CENTER_SE2A3_12", + "CFG_CENTER_IMUX44_1", + "CFG_CENTER_WL1END1_14", + "CFG_CENTER_IMUX35_0", + "CFG_CENTER_LH11_1", + "CFG_CENTER_NW4END0_14", + "CFG_CENTER_EE2A3_12", + "CFG_CENTER_EE2BEG0_18", + "CFG_CENTER_SE2A2_16", + "CFG_CENTER_IMUX28_8", + "CFG_CENTER_IMUX31_18", + "CFG_CENTER_EE4BEG2_19", + "CFG_CENTER_NW4END1_17", + "CFG_CENTER_IMUX0_13", + "CFG_CENTER_SW4A0_13", + "CFG_CENTER_FAN2_15", + "CFG_CENTER_NW4A3_3", + "CFG_CENTER_NE4C0_19", + "CFG_CENTER_LOGIC_OUTS_B17_19", + "CFG_CENTER_CLK0_16", + "CFG_CENTER_LOGIC_OUTS_B0_6", + "CFG_CENTER_NE4BEG3_15", + "CFG_CENTER_IMUX10_4", + "CFG_CENTER_FAN3_12", + "CFG_CENTER_EL1BEG0_19", + "CFG_CENTER_IMUX3_16", + "CFG_CENTER_IMUX44_4", + "CFG_CENTER_SE2A0_1", + "CFG_CENTER_EE4BEG1_13", + "CFG_CENTER_SE4C2_2", + "CFG_CENTER_IMUX45_10", + "CFG_CENTER_EE2BEG2_6", + "CFG_CENTER_IMUX28_2", + "CFG_CENTER_LOGIC_OUTS_B14_13", + "CFG_CENTER_EE2BEG1_15", + "CFG_CENTER_IMUX46_14", + "CFG_CENTER_SE4BEG1_12", + "CFG_CENTER_IMUX43_15", + "CFG_CENTER_WW2A0_6", + "CFG_CENTER_IMUX34_9", + "CFG_CENTER_WR1END2_0", + "CFG_CENTER_WW4B3_9", + "CFG_CENTER_IMUX35_2", + "CFG_CENTER_SE4BEG0_16", + "CFG_CENTER_LH4_9", + "CFG_CENTER_FAN1_1", + "CFG_CENTER_IMUX9_2", + "CFG_CENTER_EE4B2_9", + "CFG_CENTER_IMUX26_1", + "CFG_CENTER_FAN5_15", + "CFG_CENTER_IMUX21_2", + "CFG_CENTER_LOGIC_OUTS_B13_1", + "CFG_CENTER_LOGIC_OUTS_B3_9", + "CFG_CENTER_BYP5_15", + "CFG_CENTER_LOGIC_OUTS_B17_3", + "CFG_CENTER_LOGIC_OUTS_B20_14", + "CFG_CENTER_LOGIC_OUTS_B13_17", + "CFG_CENTER_SE2A3_7", + "CFG_CENTER_SW4A0_12", + "CFG_CENTER_IMUX8_10", + "CFG_CENTER_EE4BEG2_8", + "CFG_CENTER_ER1BEG0_13", + "CFG_CENTER_CTRL1_17", + "CFG_CENTER_FAN2_5", + "CFG_CENTER_SW2A3_12", + "CFG_CENTER_IMUX12_1", + "CFG_CENTER_EE2BEG1_2", + "CFG_CENTER_WW4A0_3", + "CFG_CENTER_BYP4_8", + "CFG_CENTER_CLK0_12", + "CFG_CENTER_BYP5_3", + "CFG_CENTER_CTRL0_15", + "CFG_CENTER_LOGIC_OUTS_B0_19", + "CFG_CENTER_WR1END3_19", + "CFG_CENTER_SW2A3_0", + "CFG_CENTER_LH7_18", + "CFG_CENTER_CLK1_4", + "CFG_CENTER_LOGIC_OUTS_B0_4", + "CFG_CENTER_SE4BEG2_1", + "CFG_CENTER_EE4C1_2", + "CFG_CENTER_LOGIC_OUTS_B21_18", + "CFG_CENTER_NE4BEG1_6", + "CFG_CENTER_WW4A3_11", + "CFG_CENTER_WW4B3_14", + "CFG_CENTER_WW4END3_15", + "CFG_CENTER_LOGIC_OUTS_B21_19", + "CFG_CENTER_WW4END1_13", + "CFG_CENTER_WW2END3_9", + "CFG_CENTER_SW2A0_10", + "CFG_CENTER_NW4A1_18", + "CFG_CENTER_LOGIC_OUTS_B11_10", + "CFG_CENTER_BYP5_14", + "CFG_CENTER_NW2A1_9", + "CFG_CENTER_WW4A0_4", + "CFG_CENTER_IMUX34_19", + "CFG_CENTER_IMUX30_12", + "CFG_CENTER_IMUX5_12", + "CFG_CENTER_LH7_4", + "CFG_CENTER_NE2A1_11", + "CFG_CENTER_NE4BEG1_13", + "CFG_CENTER_SE2A3_9", + "CFG_CENTER_BYP4_14", + "CFG_CENTER_LOGIC_OUTS_B4_7", + "CFG_CENTER_IMUX33_0", + "CFG_CENTER_IMUX36_10", + "CFG_CENTER_IMUX33_16", + "CFG_CENTER_IMUX35_9", + "CFG_CENTER_WW2A3_12", + "CFG_CENTER_WW2A3_3", + "CFG_CENTER_LH10_4", + "CFG_CENTER_SW2A3_7", + "CFG_CENTER_EL1BEG3_13", + "CFG_CENTER_SW4A3_9", + "CFG_CENTER_IMUX16_8", + "CFG_CENTER_WW2A1_2", + "CFG_CENTER_LH5_18", + "CFG_CENTER_SW4END0_19", + "CFG_CENTER_IMUX45_11", + "CFG_CENTER_ER1BEG2_7", + "CFG_CENTER_WW4A2_0", + "CFG_CENTER_SW4END3_2", + "CFG_CENTER_LH4_3", + "CFG_CENTER_NE4C0_1", + "CFG_CENTER_SW2A3_18", + "CFG_CENTER_EL1BEG1_13", + "CFG_CENTER_SE2A3_15", + "CFG_CENTER_IMUX27_10", + "CFG_CENTER_EE4B2_3", + "CFG_CENTER_IMUX47_0", + "CFG_CENTER_WW4B1_4", + "CFG_CENTER_SW4A1_10", + "CFG_CENTER_BYP7_1", + "CFG_CENTER_LH11_10", + "CFG_CENTER_IMUX41_14", + "CFG_CENTER_IMUX27_9", + "CFG_CENTER_IMUX47_18", + "CFG_CENTER_LOGIC_OUTS_B4_5", + "CFG_CENTER_BLOCK_OUTS_B3_14", + "CFG_CENTER_IMUX45_12", + "CFG_CENTER_EE4B3_5", + "CFG_CENTER_LH7_2", + "CFG_CENTER_EE2A1_10", + "CFG_CENTER_SW4END1_9", + "CFG_CENTER_EE4B1_0", + "CFG_CENTER_BYP7_14", + "CFG_CENTER_LH10_9", + "CFG_CENTER_IMUX21_13", + "CFG_CENTER_WW4C2_10", + "CFG_CENTER_WW4A2_13", + "CFG_CENTER_EL1BEG2_11", + "CFG_CENTER_LOGIC_OUTS_B19_0", + "CFG_CENTER_EL1BEG0_16", + "CFG_CENTER_LOGIC_OUTS_B22_9", + "CFG_CENTER_WR1END1_3", + "CFG_CENTER_FAN2_1", + "CFG_CENTER_IMUX18_1", + "CFG_CENTER_IMUX38_0", + "CFG_CENTER_SW4A3_0", + "CFG_CENTER_SE4C1_17", + "CFG_CENTER_EE2A3_11", + "CFG_CENTER_WL1END3_14", + "CFG_CENTER_EE4BEG0_18", + "CFG_CENTER_IMUX22_12", + "CFG_CENTER_WW4B3_0", + "CFG_CENTER_WL1END1_17", + "CFG_CENTER_LOGIC_OUTS_B19_4", + "CFG_CENTER_WL1END2_18", + "CFG_CENTER_IMUX4_19", + "CFG_CENTER_EE4B3_4", + "CFG_CENTER_IMUX24_18", + "CFG_CENTER_NE4C1_16", + "CFG_CENTER_NW4END3_18", + "CFG_CENTER_IMUX24_2", + "CFG_CENTER_SW4END2_18", + "CFG_CENTER_EE4B0_19", + "CFG_CENTER_SE4BEG3_15", + "CFG_CENTER_LOGIC_OUTS_B12_7", + "CFG_CENTER_LOGIC_OUTS_B17_8", + "CFG_CENTER_IMUX2_2", + "CFG_CENTER_SW4A0_1", + "CFG_CENTER_EE2BEG2_8", + "CFG_CENTER_BYP4_11", + "CFG_CENTER_CLK1_8", + "CFG_CENTER_EE4BEG2_4", + "CFG_CENTER_LOGIC_OUTS_B17_9", + "CFG_CENTER_LH9_5", + "CFG_CENTER_WW4B2_8", + "CFG_CENTER_IMUX39_0", + "CFG_CENTER_WW2END1_7", + "CFG_CENTER_BYP0_13", + "CFG_CENTER_IMUX41_8", + "CFG_CENTER_LOGIC_OUTS_B8_6", + "CFG_CENTER_EL1BEG0_8", + "CFG_CENTER_IMUX22_7", + "CFG_CENTER_IMUX37_18", + "CFG_CENTER_EL1BEG1_5", + "CFG_CENTER_IMUX32_18", + "CFG_CENTER_LOGIC_OUTS_B8_7", + "CFG_CENTER_WW4B1_16", + "CFG_CENTER_IMUX45_4", + "CFG_CENTER_IMUX20_16", + "CFG_CENTER_LOGIC_OUTS_B8_13", + "CFG_CENTER_IMUX21_14", + "CFG_CENTER_IMUX39_6", + "CFG_CENTER_LOGIC_OUTS_B1_12", + "CFG_CENTER_SW4A3_1", + "CFG_CENTER_WW2END3_16", + "CFG_CENTER_NE4C3_5", + "CFG_CENTER_NE4BEG1_10", + "CFG_CENTER_IMUX41_13", + "CFG_CENTER_IMUX31_14", + "CFG_CENTER_SE2A2_4", + "CFG_CENTER_LOGIC_OUTS_B22_2", + "CFG_CENTER_IMUX3_11", + "CFG_CENTER_NE4BEG2_5", + "CFG_CENTER_WW2A2_2", + "CFG_CENTER_LH1_9", + "CFG_CENTER_LOGIC_OUTS_B2_15", + "CFG_CENTER_WW4C3_7", + "CFG_CENTER_WW4END2_17", + "CFG_CENTER_IMUX45_14", + "CFG_CENTER_IMUX28_13", + "CFG_CENTER_EE2BEG3_9", + "CFG_CENTER_IMUX14_0", + "CFG_CENTER_IMUX24_12", + "CFG_CENTER_NE4C2_17", + "CFG_CENTER_EE4BEG2_3", + "CFG_CENTER_EE4A0_2", + "CFG_CENTER_EE4B1_6", + "CFG_CENTER_NW4END0_8", + "CFG_CENTER_SW4END3_16", + "CFG_CENTER_EE2BEG3_10", + "CFG_CENTER_IMUX17_15", + "CFG_CENTER_NE4BEG0_12", + "CFG_CENTER_IMUX41_19", + "CFG_CENTER_BLOCK_OUTS_B1_4", + "CFG_CENTER_CTRL1_10", + "CFG_CENTER_LH7_1", + "CFG_CENTER_IMUX38_8", + "CFG_CENTER_IMUX23_11", + "CFG_CENTER_WL1END1_10", + "CFG_CENTER_LOGIC_OUTS_B7_12", + "CFG_CENTER_SW2A1_15", + "CFG_CENTER_SW4A0_7", + "CFG_CENTER_EE4C3_1", + "CFG_CENTER_IMUX14_14", + "CFG_CENTER_NW4END0_6", + "CFG_CENTER_NW4END2_15", + "CFG_CENTER_IMUX30_3", + "CFG_CENTER_NE4C0_13", + "CFG_CENTER_EE2A3_15", + "CFG_CENTER_WW4C1_4", + "CFG_CENTER_WW4C2_8", + "CFG_CENTER_IMUX21_10", + "CFG_CENTER_NW2A3_4", + "CFG_CENTER_IMUX26_5", + "CFG_CENTER_WW4C0_10", + "CFG_CENTER_EE4A2_12", + "CFG_CENTER_IMUX42_16", + "CFG_CENTER_LOGIC_OUTS_B13_7", + "CFG_CENTER_NW2A1_6", + "CFG_CENTER_IMUX36_7", + "CFG_CENTER_LOGIC_OUTS_B0_0", + "CFG_CENTER_IMUX38_5", + "CFG_CENTER_EE2A0_7", + "CFG_CENTER_NW4A2_18", + "CFG_CENTER_LH3_15", + "CFG_CENTER_NW4A3_12", + "CFG_CENTER_WW2A1_18", + "CFG_CENTER_IMUX25_11", + "CFG_CENTER_IMUX15_1", + "CFG_CENTER_BYP0_10", + "CFG_CENTER_SW4END3_17", + "CFG_CENTER_EE4BEG0_15", + "CFG_CENTER_SE2A1_8", + "CFG_CENTER_LH12_0", + "CFG_CENTER_SE4C3_12", + "CFG_CENTER_NE2A3_3", + "CFG_CENTER_LOGIC_OUTS_B8_0", + "CFG_CENTER_BYP5_18", + "CFG_CENTER_NE4C3_7", + "CFG_CENTER_WW4C2_18", + "CFG_CENTER_WW4END0_16", + "CFG_CENTER_IMUX8_5", + "CFG_CENTER_IMUX26_0", + "CFG_CENTER_NW2A2_5", + "CFG_CENTER_NW4A1_4", + "CFG_CENTER_WW4END1_16", + "CFG_CENTER_IMUX29_7", + "CFG_CENTER_IMUX40_18", + "CFG_CENTER_BLOCK_OUTS_B1_0", + "CFG_CENTER_LOGIC_OUTS_B1_1", + "CFG_CENTER_IMUX27_1", + "CFG_CENTER_EL1BEG3_11", + "CFG_CENTER_IMUX37_0", + "CFG_CENTER_IMUX14_12", + "CFG_CENTER_LH2_14", + "CFG_CENTER_LOGIC_OUTS_B13_5", + "CFG_CENTER_IMUX8_15", + "CFG_CENTER_IMUX17_13", + "CFG_CENTER_EE4C2_9", + "CFG_CENTER_IMUX15_8", + "CFG_CENTER_IMUX0_14", + "CFG_CENTER_SE4C1_13", + "CFG_CENTER_NE4C0_0", + "CFG_CENTER_IMUX24_5", + "CFG_CENTER_BLOCK_OUTS_B0_0", + "CFG_CENTER_IMUX20_12", + "CFG_CENTER_SE4C2_16", + "CFG_CENTER_ER1BEG2_19", + "CFG_CENTER_IMUX14_3", + "CFG_CENTER_WR1END3_17", + "CFG_CENTER_SW4A0_15", + "CFG_CENTER_NW4END3_17", + "CFG_CENTER_EE4BEG3_4", + "CFG_CENTER_NW4A1_12", + "CFG_CENTER_WL1END3_3", + "CFG_CENTER_WW4END0_18", + "CFG_CENTER_IMUX11_4", + "CFG_CENTER_LOGIC_OUTS_B6_5", + "CFG_CENTER_EE4A3_7", + "CFG_CENTER_FAN4_1", + "CFG_CENTER_IMUX1_16", + "CFG_CENTER_IMUX22_16", + "CFG_CENTER_WW4END1_8", + "CFG_CENTER_IMUX33_1", + "CFG_CENTER_CTRL0_6", + "CFG_CENTER_IMUX43_0", + "CFG_CENTER_IMUX33_6", + "CFG_CENTER_FAN4_12", + "CFG_CENTER_WW4B2_2", + "CFG_CENTER_LOGIC_OUTS_B11_2", + "CFG_CENTER_IMUX23_16", + "CFG_CENTER_SE4BEG3_17", + "CFG_CENTER_LOGIC_OUTS_B6_8", + "CFG_CENTER_IMUX40_15", + "CFG_CENTER_EE4BEG1_11", + "CFG_CENTER_NW2A0_12", + "CFG_CENTER_CLK1_14", + "CFG_CENTER_CLK1_13", + "CFG_CENTER_WW2END1_12", + "CFG_CENTER_IMUX30_2", + "CFG_CENTER_EE4C0_12", + "CFG_CENTER_EE4C0_15", + "CFG_CENTER_SE2A0_9", + "CFG_CENTER_LOGIC_OUTS_B16_16", + "CFG_CENTER_WW4B1_2", + "CFG_CENTER_IMUX25_4", + "CFG_CENTER_SW4END3_18", + "CFG_CENTER_IMUX38_17", + "CFG_CENTER_SW4END1_16", + "CFG_CENTER_IMUX47_12", + "CFG_CENTER_WW4B3_12", + "CFG_CENTER_IMUX5_19", + "CFG_CENTER_NW4END3_13", + "CFG_CENTER_LOGIC_OUTS_B13_15", + "CFG_CENTER_SW4END3_12", + "CFG_CENTER_IMUX26_14", + "CFG_CENTER_IMUX19_2", + "CFG_CENTER_WW4END2_18", + "CFG_CENTER_IMUX41_5", + "CFG_CENTER_BLOCK_OUTS_B2_11", + "CFG_CENTER_IMUX12_6", + "CFG_CENTER_LOGIC_OUTS_B22_8", + "CFG_CENTER_IMUX21_11", + "CFG_CENTER_NW2A3_18", + "CFG_CENTER_IMUX16_11", + "CFG_CENTER_EE4BEG2_6", + "CFG_CENTER_NW2A1_16", + "CFG_CENTER_BYP2_8", + "CFG_CENTER_SE2A2_17", + "CFG_CENTER_WW4A0_7", + "CFG_CENTER_EE2A0_15", + "CFG_CENTER_NW4A2_4", + "CFG_CENTER_IMUX29_13", + "CFG_CENTER_IMUX19_16", + "CFG_CENTER_EE2BEG1_9", + "CFG_CENTER_IMUX44_19", + "CFG_CENTER_LH4_5", + "CFG_CENTER_CLK1_19", + "CFG_CENTER_WW4END2_0", + "CFG_CENTER_IMUX29_14", + "CFG_CENTER_WW4C0_12", + "CFG_CENTER_BLOCK_OUTS_B1_5", + "CFG_CENTER_EL1BEG1_0", + "CFG_CENTER_NW2A1_0", + "CFG_CENTER_CLK0_0", + "CFG_CENTER_NW4END3_9", + "CFG_CENTER_WW4C3_2", + "CFG_CENTER_WR1END1_8", + "CFG_CENTER_CLK1_11", + "CFG_CENTER_WR1END2_3", + "CFG_CENTER_IMUX25_3", + "CFG_CENTER_SW4A3_14", + "CFG_CENTER_WW4END2_3", + "CFG_CENTER_EE2A2_19", + "CFG_CENTER_EE2BEG0_13", + "CFG_CENTER_IMUX30_4", + "CFG_CENTER_WW2END3_2", + "CFG_CENTER_SE4BEG1_18", + "CFG_CENTER_SE2A1_12", + "CFG_CENTER_SW4A2_19", + "CFG_CENTER_NW2A2_12", + "CFG_CENTER_ER1BEG3_19", + "CFG_CENTER_IMUX32_5", + "CFG_CENTER_WW4C3_13", + "CFG_CENTER_EE4C0_17", + "CFG_CENTER_NW4A2_11", + "CFG_CENTER_EE4A3_1", + "CFG_CENTER_LOGIC_OUTS_B11_16", + "CFG_CENTER_NW4A3_13", + "CFG_CENTER_ER1BEG2_10", + "CFG_CENTER_BYP6_2", + "CFG_CENTER_LH5_11", + "CFG_CENTER_BLOCK_OUTS_B2_0", + "CFG_CENTER_EE4B2_19", + "CFG_CENTER_IMUX3_3", + "CFG_CENTER_SE4C3_0", + "CFG_CENTER_WR1END0_17", + "CFG_CENTER_WW2END0_11", + "CFG_CENTER_SW2A3_14", + "CFG_CENTER_WW4END2_14", + "CFG_CENTER_FAN4_11", + "CFG_CENTER_BYP2_12", + "CFG_CENTER_BYP0_17", + "CFG_CENTER_IMUX15_10", + "CFG_CENTER_LOGIC_OUTS_B11_14", + "CFG_CENTER_NW2A1_2", + "CFG_CENTER_FAN3_2", + "CFG_CENTER_EE4B3_19", + "CFG_CENTER_NW2A2_6", + "CFG_CENTER_IMUX15_5", + "CFG_CENTER_IMUX34_8", + "CFG_CENTER_SE4C3_17", + "CFG_CENTER_NE4BEG0_3", + "CFG_CENTER_WW4A0_12", + "CFG_CENTER_IMUX30_14", + "CFG_CENTER_IMUX17_1", + "CFG_CENTER_FAN5_9", + "CFG_CENTER_SE2A3_18", + "CFG_CENTER_CLK0_19", + "CFG_CENTER_IMUX44_0", + "CFG_CENTER_FAN3_8", + "CFG_CENTER_ER1BEG2_17", + "CFG_CENTER_LH9_16", + "CFG_CENTER_IMUX12_13", + "CFG_CENTER_EE4B1_9", + "CFG_CENTER_LOGIC_OUTS_B12_17", + "CFG_CENTER_EE4C2_1", + "CFG_CENTER_BLOCK_OUTS_B0_3", + "CFG_CENTER_ER1BEG0_4", + "CFG_CENTER_NE4C1_8", + "CFG_CENTER_SW2A0_16", + "CFG_CENTER_WW4B1_17", + "CFG_CENTER_LH8_19", + "CFG_CENTER_LH5_13", + "CFG_CENTER_SE2A1_3", + "CFG_CENTER_IMUX18_14", + "CFG_CENTER_LOGIC_OUTS_B4_19", + "CFG_CENTER_NE2A2_16", + "CFG_CENTER_WW2A1_3", + "CFG_CENTER_BYP7_12", + "CFG_CENTER_NE2A2_15", + "CFG_CENTER_FAN6_1", + "CFG_CENTER_BYP0_16", + "CFG_CENTER_EE2BEG0_3", + "CFG_CENTER_IMUX42_17", + "CFG_CENTER_NE4BEG1_18", + "CFG_CENTER_EL1BEG1_3", + "CFG_CENTER_LH8_17", + "CFG_CENTER_IMUX36_1", + "CFG_CENTER_LOGIC_OUTS_B5_3", + "CFG_CENTER_IMUX35_7", + "CFG_CENTER_SW2A3_5", + "CFG_CENTER_IMUX24_16", + "CFG_CENTER_EE4B0_10", + "CFG_CENTER_WW4C0_13", + "CFG_CENTER_IMUX33_12", + "CFG_CENTER_EE2BEG2_0", + "CFG_CENTER_NE4C3_1", + "CFG_CENTER_BLOCK_OUTS_B0_18", + "CFG_CENTER_EE4B0_8", + "CFG_CENTER_IMUX24_19", + "CFG_CENTER_WW4END0_1", + "CFG_CENTER_EL1BEG0_7", + "CFG_CENTER_IMUX14_17", + "CFG_CENTER_BLOCK_OUTS_B0_15", + "CFG_CENTER_LOGIC_OUTS_B9_4", + "CFG_CENTER_IMUX27_12", + "CFG_CENTER_BYP1_15", + "CFG_CENTER_LOGIC_OUTS_B21_5", + "CFG_CENTER_WW2A0_15", + "CFG_CENTER_LH12_7", + "CFG_CENTER_EE4B1_8", + "CFG_CENTER_CLK1_6", + "CFG_CENTER_LH10_17", + "CFG_CENTER_IMUX28_17", + "CFG_CENTER_LOGIC_OUTS_B0_9", + "CFG_CENTER_IMUX28_7", + "CFG_CENTER_EE4A3_11", + "CFG_CENTER_NW4END0_13", + "CFG_CENTER_IMUX38_18", + "CFG_CENTER_LOGIC_OUTS_B7_1", + "CFG_CENTER_IMUX31_16", + "CFG_CENTER_SW2A2_2", + "CFG_CENTER_LOGIC_OUTS_B3_6", + "CFG_CENTER_WW4C0_3", + "CFG_CENTER_LH1_10", + "CFG_CENTER_IMUX43_11", + "CFG_CENTER_IMUX32_14", + "CFG_CENTER_BYP1_1", + "CFG_CENTER_WL1END0_9", + "CFG_CENTER_IMUX5_7", + "CFG_CENTER_EE2A0_8", + "CFG_CENTER_WW4END1_5", + "CFG_CENTER_IMUX27_18", + "CFG_CENTER_WW4B1_5", + "CFG_CENTER_BYP6_13", + "CFG_CENTER_LH7_19", + "CFG_CENTER_LOGIC_OUTS_B2_2", + "CFG_CENTER_NW4END3_4", + "CFG_CENTER_WW4C0_17", + "CFG_CENTER_FAN4_0", + "CFG_CENTER_EE2A2_8", + "CFG_CENTER_LOGIC_OUTS_B23_11", + "CFG_CENTER_SW4A2_13", + "CFG_CENTER_BYP4_4", + "CFG_CENTER_IMUX31_19", + "CFG_CENTER_BYP1_18", + "CFG_CENTER_EE4C0_16", + "CFG_CENTER_IMUX47_14", + "CFG_CENTER_IMUX2_11", + "CFG_CENTER_BLOCK_OUTS_B1_2", + "CFG_CENTER_NW4A1_2", + "CFG_CENTER_SW4A2_1", + "CFG_CENTER_IMUX19_14", + "CFG_CENTER_WW4C1_5", + "CFG_CENTER_NW4END2_14", + "CFG_CENTER_WW4A2_4", + "CFG_CENTER_CLK1_10", + "CFG_CENTER_EE2BEG1_4", + "CFG_CENTER_EL1BEG1_14", + "CFG_CENTER_IMUX12_14", + "CFG_CENTER_SW4A3_8", + "CFG_CENTER_IMUX47_17", + "CFG_CENTER_IMUX29_2", + "CFG_CENTER_WR1END3_8", + "CFG_CENTER_WW2END0_1", + "CFG_CENTER_NE4C3_12", + "CFG_CENTER_IMUX3_5", + "CFG_CENTER_IMUX34_2", + "CFG_CENTER_IMUX10_8", + "CFG_CENTER_IMUX14_5", + "CFG_CENTER_EE2A1_1", + "CFG_CENTER_FAN6_17", + "CFG_CENTER_EE4BEG2_7", + "CFG_CENTER_CLK1_1", + "CFG_CENTER_IMUX18_2", + "CFG_CENTER_SW2A3_11", + "CFG_CENTER_LOGIC_OUTS_B21_17", + "CFG_CENTER_IMUX36_4", + "CFG_CENTER_IMUX18_3", + "CFG_CENTER_IMUX28_6", + "CFG_CENTER_WW2A2_6", + "CFG_CENTER_IMUX39_2", + "CFG_CENTER_NW2A2_11", + "CFG_CENTER_IMUX15_7", + "CFG_CENTER_IMUX44_9", + "CFG_CENTER_NE4C2_11", + "CFG_CENTER_LOGIC_OUTS_B8_2", + "CFG_CENTER_BYP2_16", + "CFG_CENTER_BYP5_7", + "CFG_CENTER_LH6_2", + "CFG_CENTER_NE4C0_5", + "CFG_CENTER_NW4A3_4", + "CFG_CENTER_SE4C2_3", + "CFG_CENTER_NW4END0_12", + "CFG_CENTER_SE4BEG0_7", + "CFG_CENTER_BYP5_5", + "CFG_CENTER_WW4B3_17", + "CFG_CENTER_EE2A2_6", + "CFG_CENTER_IMUX32_17", + "CFG_CENTER_WW4B3_2", + "CFG_CENTER_SE4BEG2_6", + "CFG_CENTER_EE2A0_10", + "CFG_CENTER_BYP7_17", + "CFG_CENTER_IMUX26_2", + "CFG_CENTER_SE4C2_1", + "CFG_CENTER_NW2A3_0", + "CFG_CENTER_WW4END3_16", + "CFG_CENTER_IMUX15_14" + ], + "tile_type": "CFG_CENTER_BOT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CFG_CENTER_MID.json b/artix7/tile_type_CFG_CENTER_MID.json index 36af45e..7ce6a2b 100644 --- a/artix7/tile_type_CFG_CENTER_MID.json +++ b/artix7/tile_type_CFG_CENTER_MID.json @@ -1,7187 +1,7187 @@ { + "pips": { + "CFG_CENTER_MID.CFG_CENTER_IMUX39_11->CFG_CENTER_BSCAN4_TDO": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX39_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_BSCAN4_TDO" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD5->CFG_CENTER_LOGIC_OUTS_B9_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_7" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_12->CFG_CENTER_ICAP1_I12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX40_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I12" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA21->CFG_CENTER_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O26->CFG_CENTER_LOGIC_OUTS_B11_14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_14" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_CAPTURE->CFG_CENTER_LOGIC_OUTS_B23_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_CAPTURE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_2" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O28->CFG_CENTER_LOGIC_OUTS_B12_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_5" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR15->CFG_CENTER_LOGIC_OUTS_B9_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_6" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA26->CFG_CENTER_LOGIC_OUTS_B21_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_11->CFG_CENTER_BSCAN3_TDO": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX38_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_BSCAN3_TDO" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA25->CFG_CENTER_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_13->CFG_CENTER_ICAP1_I23": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX35_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I23" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_11->CFG_CENTER_ICAP1_CSIB": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX43_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_CSIB" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_5->CFG_CENTER_ICAP0_I29": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX40_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I29" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_5->CFG_CENTER_ICAP0_I23": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX34_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I23" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_5->CFG_CENTER_ICAP0_I24": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX35_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I24" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O24->CFG_CENTER_LOGIC_OUTS_B23_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_13" + }, + "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGCLK->CFG_CENTER_LOGIC_OUTS_B14_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_STARTUP_CFGCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_10" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_DRCK->CFG_CENTER_LOGIC_OUTS_B21_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_DRCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_2" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_CAPTURE->CFG_CENTER_LOGIC_OUTS_B22_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_CAPTURE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_2" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O16->CFG_CENTER_LOGIC_OUTS_B15_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_13" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME1->CFG_CENTER_LOGIC_OUTS_B15_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_1" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA9->CFG_CENTER_MID_USR_ACCESS_DATA9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA9" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR17->CFG_CENTER_LOGIC_OUTS_B11_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_7" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT4->CFG_CENTER_LOGIC_OUTS_B22_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME10->CFG_CENTER_LOGIC_OUTS_B10_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_2" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O12->CFG_CENTER_LOGIC_OUTS_B12_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_4" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR25->CFG_CENTER_LOGIC_OUTS_B19_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TDI->CFG_CENTER_LOGIC_OUTS_B17_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_TDI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_11" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O12->CFG_CENTER_LOGIC_OUTS_B23_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_12" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O27->CFG_CENTER_LOGIC_OUTS_B11_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_5" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TCK->CFG_CENTER_LOGIC_OUTS_B19_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_TCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_11" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O25->CFG_CENTER_LOGIC_OUTS_B9_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_4" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA22->CFG_CENTER_LOGIC_OUTS_B17_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_CRCERROR->CFG_CENTER_LOGIC_OUTS_B15_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_CRCERROR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_10" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O8->CFG_CENTER_LOGIC_OUTS_B19_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_12" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_5->CFG_CENTER_ICAP0_I31": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX42_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I31" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX28_13->CFG_CENTER_ICAP1_I16": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX28_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I16" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD2->CFG_CENTER_LOGIC_OUTS_B22_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR0->CFG_CENTER_LOGIC_OUTS_B10_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_6" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_12->CFG_CENTER_ICAP1_I8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX36_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I8" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERROR->CFG_CENTER_LOGIC_OUTS_B20_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_ECCERROR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA16->CFG_CENTER_LOGIC_OUTS_B11_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_1" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O14->CFG_CENTER_LOGIC_OUTS_B13_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_13" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O15->CFG_CENTER_LOGIC_OUTS_B15_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_4" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_8->CFG_CENTER_STARTUP_GSR": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX40_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_GSR" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_5->CFG_CENTER_ICAP0_I28": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX39_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I28" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_5->CFG_CENTER_ICAP0_I25": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX36_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I25" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA11->CFG_CENTER_MID_USR_ACCESS_DATA11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA11" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O22->CFG_CENTER_LOGIC_OUTS_B22_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_4" + }, + "CFG_CENTER_MID.CFG_CENTER_STARTUP_EOS->CFG_CENTER_LOGIC_OUTS_B23_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_STARTUP_EOS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O31->CFG_CENTER_LOGIC_OUTS_B16_14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_14" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_4->CFG_CENTER_ICAP0_I8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX36_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I8" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_UPDATE->CFG_CENTER_LOGIC_OUTS_B19_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_UPDATE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_10" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_5->CFG_CENTER_ICAP0_I22": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX33_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I22" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME0->CFG_CENTER_LOGIC_OUTS_B14_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_1" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O1->CFG_CENTER_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_4" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_5->CFG_CENTER_ICAP0_I30": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX41_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I30" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RUNTEST->CFG_CENTER_LOGIC_OUTS_B8_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_RUNTEST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_2" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX30_4->CFG_CENTER_ICAP0_I2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX30_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I2" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O10->CFG_CENTER_LOGIC_OUTS_B10_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_4" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O29->CFG_CENTER_LOGIC_OUTS_B13_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_5" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O20->CFG_CENTER_LOGIC_OUTS_B19_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_13" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT1->CFG_CENTER_LOGIC_OUTS_B19_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_5->CFG_CENTER_ICAP0_I27": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX38_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I27" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA23->CFG_CENTER_LOGIC_OUTS_B18_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_0" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME2->CFG_CENTER_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_1" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O0->CFG_CENTER_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_4" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX28_5->CFG_CENTER_ICAP0_I17": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX28_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I17" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR9->CFG_CENTER_LOGIC_OUTS_B19_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RUNTEST->CFG_CENTER_LOGIC_OUTS_B9_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_RUNTEST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_2" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATAVALID->CFG_CENTER_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATAVALID", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_1" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA1->CFG_CENTER_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O9->CFG_CENTER_LOGIC_OUTS_B9_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_3" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX29_13->CFG_CENTER_ICAP1_I17": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX29_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I17" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX32_13->CFG_CENTER_ICAP1_I20": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX32_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I20" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_4->CFG_CENTER_ICAP0_I10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I10" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O18->CFG_CENTER_LOGIC_OUTS_B17_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_13" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_4->CFG_CENTER_ICAP0_I13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX41_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I13" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA7->CFG_CENTER_MID_USR_ACCESS_DATA7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA7" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX31_5->CFG_CENTER_ICAP0_I20": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX31_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I20" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR13->CFG_CENTER_LOGIC_OUTS_B23_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD6->CFG_CENTER_LOGIC_OUTS_B17_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_7->CFG_CENTER_STARTUP_USRCCLKO": { + "can_invert": "0", + "src_wire": "CFG_CENTER_CLK1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_USRCCLKO" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O30->CFG_CENTER_LOGIC_OUTS_B15_14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_14" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RESET->CFG_CENTER_LOGIC_OUTS_B18_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_RESET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_2" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR5->CFG_CENTER_LOGIC_OUTS_B15_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_6" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_8->CFG_CENTER_STARTUP_USRCCLKTS": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX38_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_USRCCLKTS" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT0->CFG_CENTER_LOGIC_OUTS_B18_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O3->CFG_CENTER_LOGIC_OUTS_B14_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_12" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TMS->CFG_CENTER_LOGIC_OUTS_B15_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_TMS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_11" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_5->CFG_CENTER_ICAP0_I26": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX37_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I26" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_4->CFG_CENTER_ICAP0_I5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX33_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I5" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O11->CFG_CENTER_LOGIC_OUTS_B11_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_4" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_4->CFG_CENTER_ICAP0_I12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I12" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA15->CFG_CENTER_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_0" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_6->CFG_CENTER_ICAP0_CLK": { + "can_invert": "0", + "src_wire": "CFG_CENTER_CLK1_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_CLK" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_4->CFG_CENTER_ICAP0_I7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX35_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I7" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O26->CFG_CENTER_LOGIC_OUTS_B10_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_5" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_13->CFG_CENTER_ICAP1_I29": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX41_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I29" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RUNTEST->CFG_CENTER_LOGIC_OUTS_B14_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_RUNTEST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_11" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O25->CFG_CENTER_LOGIC_OUTS_B10_14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_14" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA3->CFG_CENTER_MID_USR_ACCESS_DATA3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA3" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME12->CFG_CENTER_LOGIC_OUTS_B12_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_2" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA19->CFG_CENTER_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA0->CFG_CENTER_LOGIC_OUTS_B11_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SHIFT->CFG_CENTER_LOGIC_OUTS_B22_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_SHIFT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_11" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_CFGCLK->CFG_CENTER_LOGIC_OUTS_B9_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_CFGCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_5" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR20->CFG_CENTER_LOGIC_OUTS_B14_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_7" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_8->CFG_CENTER_STARTUP_PACK": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX43_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_PACK" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O30->CFG_CENTER_LOGIC_OUTS_B14_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_5" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_3->CFG_CENTER_BSCAN2_TDO": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX34_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_BSCAN2_TDO" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O7->CFG_CENTER_LOGIC_OUTS_B18_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_12" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O28->CFG_CENTER_LOGIC_OUTS_B13_14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_14" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_12->CFG_CENTER_ICAP1_I11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX39_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I11" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_4->CFG_CENTER_ICAP0_I9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX37_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I9" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_13->CFG_CENTER_ICAP1_I31": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX43_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I31" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX32_5->CFG_CENTER_ICAP0_I21": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX32_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I21" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT3->CFG_CENTER_LOGIC_OUTS_B21_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR8->CFG_CENTER_LOGIC_OUTS_B18_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD3->CFG_CENTER_LOGIC_OUTS_B23_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_DRCK->CFG_CENTER_LOGIC_OUTS_B20_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_DRCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_2" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_UPDATE->CFG_CENTER_LOGIC_OUTS_B18_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_UPDATE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_10" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RESET->CFG_CENTER_LOGIC_OUTS_B21_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_RESET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_10" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_3->CFG_CENTER_BSCAN1_TDO": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX33_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_BSCAN1_TDO" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX32_4->CFG_CENTER_ICAP0_I4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX32_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I4" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_UPDATE->CFG_CENTER_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_UPDATE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_2" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O16->CFG_CENTER_LOGIC_OUTS_B16_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_5" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR14->CFG_CENTER_LOGIC_OUTS_B8_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_6" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O5->CFG_CENTER_LOGIC_OUTS_B16_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_12" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME6->CFG_CENTER_LOGIC_OUTS_B20_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_1" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O5->CFG_CENTER_LOGIC_OUTS_B21_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_3" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX29_4->CFG_CENTER_ICAP0_I1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX29_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I1" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_13->CFG_CENTER_ICAP1_I22": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX34_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I22" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_4->CFG_CENTER_ICAP0_I15": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX43_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I15" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_12->CFG_CENTER_ICAP1_I9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX37_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I9" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RESET->CFG_CENTER_LOGIC_OUTS_B20_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_RESET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_10" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O23->CFG_CENTER_LOGIC_OUTS_B23_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_4" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA10->CFG_CENTER_MID_USR_ACCESS_DATA10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA10" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR7->CFG_CENTER_LOGIC_OUTS_B17_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR23->CFG_CENTER_LOGIC_OUTS_B17_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_8->CFG_CENTER_DCIRESET_RST": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX35_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DCIRESET_RST" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR2->CFG_CENTER_LOGIC_OUTS_B12_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_6" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O6->CFG_CENTER_LOGIC_OUTS_B17_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_12" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_8->CFG_CENTER_STARTUP_KEYCLEARB": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX36_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_KEYCLEARB" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_12->CFG_CENTER_ICAP1_I14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX42_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I14" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA13->CFG_CENTER_MID_USR_ACCESS_DATA13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA13" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_4->CFG_CENTER_ICAP0_I14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I14" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TMS->CFG_CENTER_LOGIC_OUTS_B16_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_TMS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_11" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_8->CFG_CENTER_STARTUP_USRDONEO": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX42_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_USRDONEO" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_UPDATE->CFG_CENTER_LOGIC_OUTS_B16_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_UPDATE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_2" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_5->CFG_CENTER_STARTUP_CLK": { + "can_invert": "0", + "src_wire": "CFG_CENTER_CLK1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_CLK" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_13->CFG_CENTER_ICAP1_I27": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX39_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I27" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TMS->CFG_CENTER_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_TMS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_3" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O22->CFG_CENTER_LOGIC_OUTS_B21_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_13" + }, + "CFG_CENTER_MID.CFG_CENTER_STARTUP_PREQ->CFG_CENTER_LOGIC_OUTS_B22_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_STARTUP_PREQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_13->CFG_CENTER_ICAP1_I25": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX37_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I25" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA18->CFG_CENTER_LOGIC_OUTS_B13_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_0" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_8->CFG_CENTER_MID_DNA_PORT_CLK": { + "can_invert": "0", + "src_wire": "CFG_CENTER_CLK1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_DNA_PORT_CLK" + }, + "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGMCLK->CFG_CENTER_LOGIC_OUTS_B18_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_STARTUP_CFGMCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_5" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX36_13->CFG_CENTER_ICAP1_I24": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX36_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I24" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_13->CFG_CENTER_ICAP1_I21": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX33_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I21" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_12->CFG_CENTER_ICAP1_I6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX34_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I6" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O1->CFG_CENTER_LOGIC_OUTS_B12_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_12" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O8->CFG_CENTER_LOGIC_OUTS_B8_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_3" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O24->CFG_CENTER_LOGIC_OUTS_B8_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_4" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA31->CFG_CENTER_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_1" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O0->CFG_CENTER_LOGIC_OUTS_B23_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_11" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_13->CFG_CENTER_ICAP1_I30": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX42_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I30" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR18->CFG_CENTER_LOGIC_OUTS_B12_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_7" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O21->CFG_CENTER_LOGIC_OUTS_B21_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_4" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TCK->CFG_CENTER_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_TCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_3" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX29_5->CFG_CENTER_ICAP0_I18": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX29_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I18" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O20->CFG_CENTER_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_4" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX37_8->CFG_CENTER_CAPTURE_CAP": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX37_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_CAPTURE_CAP" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_12->CFG_CENTER_ICAP1_I10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX38_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I10" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX30_12->CFG_CENTER_ICAP1_I2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX30_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I2" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME3->CFG_CENTER_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_1" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O17->CFG_CENTER_LOGIC_OUTS_B17_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_5" + }, + "CFG_CENTER_MID.CFG_CENTER_CLK1_9->CFG_CENTER_CAPTURE_CLK": { + "can_invert": "0", + "src_wire": "CFG_CENTER_CLK1_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_CAPTURE_CLK" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR6->CFG_CENTER_LOGIC_OUTS_B16_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SHIFT->CFG_CENTER_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_SHIFT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_3" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TDI->CFG_CENTER_LOGIC_OUTS_B18_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_TDI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_11" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_CAPTURE->CFG_CENTER_LOGIC_OUTS_B12_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_CAPTURE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_11" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O15->CFG_CENTER_LOGIC_OUTS_B14_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_13" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD4->CFG_CENTER_LOGIC_OUTS_B8_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_7" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA6->CFG_CENTER_MID_USR_ACCESS_DATA6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA6" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_4->CFG_CENTER_ICAP0_I11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I11" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TCK->CFG_CENTER_LOGIC_OUTS_B20_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_TCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_11" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX32_12->CFG_CENTER_ICAP1_I4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX32_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I4" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX31_4->CFG_CENTER_ICAP0_I3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX31_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I3" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_11->CFG_CENTER_ICAP0_RDWRB": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX41_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_RDWRB" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR21->CFG_CENTER_LOGIC_OUTS_B15_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_7" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O13->CFG_CENTER_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_4" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX28_4->CFG_CENTER_ICAP0_I0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX30_5->CFG_CENTER_ICAP0_I19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX30_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I19" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_13->CFG_CENTER_ICAP1_I28": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX40_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I28" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME8->CFG_CENTER_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_1" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX29_12->CFG_CENTER_ICAP1_I1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX29_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I1" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_DRCK->CFG_CENTER_LOGIC_OUTS_B22_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_DRCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_10" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA2->CFG_CENTER_MID_USR_ACCESS_DATA2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA2" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O13->CFG_CENTER_LOGIC_OUTS_B12_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_13" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA29->CFG_CENTER_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O23->CFG_CENTER_LOGIC_OUTS_B22_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_13" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA8->CFG_CENTER_MID_USR_ACCESS_DATA8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA8" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERRORSINGLE->CFG_CENTER_LOGIC_OUTS_B23_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O19->CFG_CENTER_LOGIC_OUTS_B18_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_13" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX31_12->CFG_CENTER_ICAP1_I3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX31_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I3" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX31_13->CFG_CENTER_ICAP1_I19": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX31_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I19" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX40_11->CFG_CENTER_ICAP0_CSIB": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX40_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_CSIB" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME11->CFG_CENTER_LOGIC_OUTS_B11_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_2" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O27->CFG_CENTER_LOGIC_OUTS_B12_14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_14" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RESET->CFG_CENTER_LOGIC_OUTS_B19_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_RESET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_2" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_DRCK->CFG_CENTER_LOGIC_OUTS_B23_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_DRCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_10" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA14->CFG_CENTER_MID_USR_ACCESS_DATA14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA14" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME4->CFG_CENTER_LOGIC_OUTS_B18_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_1" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA20->CFG_CENTER_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SEL->CFG_CENTER_LOGIC_OUTS_B15_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_SEL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_2" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR3->CFG_CENTER_LOGIC_OUTS_B13_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_6" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O7->CFG_CENTER_LOGIC_OUTS_B23_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_3" + }, + "CFG_CENTER_MID.CFG_CENTER_MID_ICAP1_CLK->CFG_CENTER_ICAP1_CLK": { + "can_invert": "0", + "src_wire": "CFG_CENTER_MID_ICAP1_CLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_CLK" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SHIFT->CFG_CENTER_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_SHIFT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_3" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SEL->CFG_CENTER_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_SEL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_2" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_8->CFG_CENTER_STARTUP_USRDONETS": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX41_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_USRDONETS" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX34_4->CFG_CENTER_ICAP0_I6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I6" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O17->CFG_CENTER_LOGIC_OUTS_B16_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_13" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX38_13->CFG_CENTER_ICAP1_I26": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX38_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I26" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O14->CFG_CENTER_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_4" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR22->CFG_CENTER_LOGIC_OUTS_B16_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR16->CFG_CENTER_LOGIC_OUTS_B10_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_7" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR4->CFG_CENTER_LOGIC_OUTS_B14_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_6" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O21->CFG_CENTER_LOGIC_OUTS_B20_13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_13" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TCK->CFG_CENTER_LOGIC_OUTS_B15_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_TCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_3" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SEL->CFG_CENTER_LOGIC_OUTS_B16_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_SEL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_10" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RUNTEST->CFG_CENTER_LOGIC_OUTS_B13_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_RUNTEST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_11" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROMEVALID->CFG_CENTER_LOGIC_OUTS_B13_2": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_2" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O18->CFG_CENTER_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_4" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT2->CFG_CENTER_LOGIC_OUTS_B20_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8" + }, + "CFG_CENTER_MID.CFG_CENTER_DCIRESET_LOCKED->CFG_CENTER_LOGIC_OUTS_B21_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_DCIRESET_LOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA17->CFG_CENTER_LOGIC_OUTS_B12_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_1" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR1->CFG_CENTER_LOGIC_OUTS_B11_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_6" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR11->CFG_CENTER_LOGIC_OUTS_B21_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME7->CFG_CENTER_LOGIC_OUTS_B21_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_1" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O6->CFG_CENTER_LOGIC_OUTS_B22_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_3" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TDI->CFG_CENTER_LOGIC_OUTS_B13_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_TDI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_3" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_CAPTURE->CFG_CENTER_LOGIC_OUTS_B11_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_CAPTURE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_11" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O29->CFG_CENTER_LOGIC_OUTS_B14_14": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_14" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR10->CFG_CENTER_LOGIC_OUTS_B20_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR24->CFG_CENTER_LOGIC_OUTS_B18_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TDI->CFG_CENTER_LOGIC_OUTS_B12_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN1_TDI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_3" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O19->CFG_CENTER_LOGIC_OUTS_B19_4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_4" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX33_12->CFG_CENTER_ICAP1_I5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX33_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I5" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O31->CFG_CENTER_LOGIC_OUTS_B15_5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_5" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX30_13->CFG_CENTER_ICAP1_I18": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX30_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I18" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA30->CFG_CENTER_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_0" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA12->CFG_CENTER_MID_USR_ACCESS_DATA12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA12" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX27_5->CFG_CENTER_ICAP0_I16": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX27_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP0_I16" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD0->CFG_CENTER_LOGIC_OUTS_B20_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX35_12->CFG_CENTER_ICAP1_I7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX35_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I7" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O4->CFG_CENTER_LOGIC_OUTS_B20_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_3" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA4->CFG_CENTER_MID_USR_ACCESS_DATA4": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA4" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SEL->CFG_CENTER_LOGIC_OUTS_B17_10": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN4_SEL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_10" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX41_12->CFG_CENTER_ICAP1_I13": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX41_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I13" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME9->CFG_CENTER_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_1" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME5->CFG_CENTER_LOGIC_OUTS_B19_1": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_1" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX43_12->CFG_CENTER_ICAP1_I15": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX43_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I15" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA5->CFG_CENTER_MID_USR_ACCESS_DATA5": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA5" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O2->CFG_CENTER_LOGIC_OUTS_B18_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_3" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX39_8->CFG_CENTER_STARTUP_GTS": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX39_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_STARTUP_GTS" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA27->CFG_CENTER_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_0" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O9->CFG_CENTER_LOGIC_OUTS_B20_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_12" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX28_12->CFG_CENTER_ICAP1_I0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX28_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_I0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SHIFT->CFG_CENTER_LOGIC_OUTS_B21_11": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN3_SHIFT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_11" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR19->CFG_CENTER_LOGIC_OUTS_B13_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_7" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR12->CFG_CENTER_LOGIC_OUTS_B22_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_FAR12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O10->CFG_CENTER_LOGIC_OUTS_B21_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_12" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O4->CFG_CENTER_LOGIC_OUTS_B15_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_12" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA24->CFG_CENTER_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_0" + }, + "CFG_CENTER_MID.CFG_CENTER_IMUX42_11->CFG_CENTER_ICAP1_RDWRB": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX42_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_ICAP1_RDWRB" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O11->CFG_CENTER_LOGIC_OUTS_B22_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_12" + }, + "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD1->CFG_CENTER_LOGIC_OUTS_B21_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP1_O2->CFG_CENTER_LOGIC_OUTS_B13_12": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP1_O2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_12" + }, + "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA28->CFG_CENTER_LOGIC_OUTS_B23_0": { + "can_invert": "0", + "src_wire": "CFG_CENTER_USR_ACCESS_DATA28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_0" + }, + "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TMS->CFG_CENTER_LOGIC_OUTS_B11_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_BSCAN2_TMS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_3" + }, + "CFG_CENTER_MID.CFG_CENTER_ICAP0_O3->CFG_CENTER_LOGIC_OUTS_B19_3": { + "can_invert": "0", + "src_wire": "CFG_CENTER_ICAP0_O3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_3" + } + }, "wires": [ - "CFG_CENTER_IMUX6_18", - "CFG_CENTER_LOGIC_OUTS_B0_0", - "CFG_CENTER_FAN2_11", - "CFG_CENTER_WW2END2_0", - "CFG_CENTER_NW2A1_17", - "CFG_CENTER_IMUX17_6", - "CFG_CENTER_WW4C0_5", - "CFG_CENTER_NE4BEG0_10", - "CFG_CENTER_WL1END3_0", - "CFG_CENTER_EE4BEG0_1", - "CFG_CENTER_IMUX5_16", - "CFG_CENTER_EE2A2_1", - "CFG_CENTER_NW4END3_11", - "CFG_CENTER_LOGIC_OUTS_B22_2", - "CFG_CENTER_NW4A3_0", - "CFG_CENTER_WW4END3_14", - "CFG_CENTER_WW4END1_3", - "CFG_CENTER_LH11_4", - "CFG_CENTER_FRAME_ECC_SYNBIT0", - "CFG_CENTER_WR1END3_3", - "CFG_CENTER_IMUX40_17", - "CFG_CENTER_NW4A3_10", - "CFG_CENTER_WW4B3_9", - "CFG_CENTER_WW4B1_4", - "CFG_CENTER_LOGIC_OUTS_B7_9", - "CFG_CENTER_LH1_7", - "CFG_CENTER_LH5_0", - "CFG_CENTER_NW4A3_4", - "CFG_CENTER_SW4A0_2", - "CFG_CENTER_EE2A0_15", - "CFG_CENTER_FAN2_9", - "CFG_CENTER_NE2A0_7", - "CFG_CENTER_SE2A2_16", - "CFG_CENTER_WR1END2_15", - "CFG_CENTER_IMUX44_13", - "CFG_CENTER_CTRL0_10", - "CFG_CENTER_WW2END2_9", - "CFG_CENTER_IMUX17_4", - "CFG_CENTER_FAN7_16", - "CFG_CENTER_SW4END2_6", - "CFG_CENTER_EE4A3_10", - "CFG_CENTER_LOGIC_OUTS_B19_14", - "CFG_CENTER_FAN3_15", - "CFG_CENTER_WR1END2_5", - "CFG_CENTER_SW2A2_15", - "CFG_CENTER_EE4A0_8", - "CFG_CENTER_IMUX5_9", - "CFG_CENTER_LOGIC_OUTS_B12_11", - "CFG_CENTER_ICAP0_I14", - "CFG_CENTER_NW4END1_0", - "CFG_CENTER_EE2A3_18", - "CFG_CENTER_NW2A1_9", - "CFG_CENTER_EL1BEG1_5", - "CFG_CENTER_IMUX24_19", - "CFG_CENTER_WW4B1_0", - "CFG_CENTER_LOGIC_OUTS_B6_3", - "CFG_CENTER_EE4B0_12", - "CFG_CENTER_NE4C2_12", - "CFG_CENTER_BYP1_5", - "CFG_CENTER_ICAP0_O21", - "CFG_CENTER_WW4A0_14", - "CFG_CENTER_SE4BEG1_7", - "CFG_CENTER_NW2A1_10", - "CFG_CENTER_EE4B0_19", - "CFG_CENTER_NE4C2_16", - "CFG_CENTER_IMUX29_2", - "CFG_CENTER_FAN2_7", - "CFG_CENTER_EE4C2_5", - "CFG_CENTER_WW4C1_4", - "CFG_CENTER_IMUX21_1", - "CFG_CENTER_CTRL0_8", - "CFG_CENTER_EE4A3_4", - "CFG_CENTER_SW4END2_7", - "CFG_CENTER_IMUX9_3", - "CFG_CENTER_NE2A2_3", - "CFG_CENTER_BYP4_16", - "CFG_CENTER_WW4A3_19", - "CFG_CENTER_LH9_18", - "CFG_CENTER_WW4A2_2", - "CFG_CENTER_IMUX38_1", - "CFG_CENTER_IMUX42_4", - "CFG_CENTER_NW4END0_14", - "CFG_CENTER_LOGIC_OUTS_B16_15", - "CFG_CENTER_WW2A0_7", - "CFG_CENTER_NW4END0_9", - "CFG_CENTER_NE2A0_3", - "CFG_CENTER_IMUX45_2", - "CFG_CENTER_SE4BEG3_10", - "CFG_CENTER_NE4BEG3_3", - "CFG_CENTER_SW2A2_19", - "CFG_CENTER_ER1BEG2_7", - "CFG_CENTER_IMUX11_6", - "CFG_CENTER_IMUX34_5", - "CFG_CENTER_IMUX45_4", - "CFG_CENTER_LOGIC_OUTS_B18_14", - "CFG_CENTER_EE2A2_19", - "CFG_CENTER_IMUX11_10", - "CFG_CENTER_IMUX8_16", - "CFG_CENTER_EE4BEG1_8", - "CFG_CENTER_LOGIC_OUTS_B4_1", - "CFG_CENTER_WW2END3_19", - "CFG_CENTER_WW4END1_5", - "CFG_CENTER_EE4BEG0_8", - "CFG_CENTER_WW4A0_6", - "CFG_CENTER_WW4A0_12", - "CFG_CENTER_IMUX26_12", - "CFG_CENTER_IMUX6_2", - "CFG_CENTER_WW4END0_8", - "CFG_CENTER_ICAP0_I23", - "CFG_CENTER_WW4B3_10", - "CFG_CENTER_LOGIC_OUTS_B19_12", - "CFG_CENTER_SW4A2_4", - "CFG_CENTER_IMUX10_16", - "CFG_CENTER_WR1END1_3", - "CFG_CENTER_SW4A0_9", - "CFG_CENTER_IMUX43_11", - "CFG_CENTER_SE2A1_7", - "CFG_CENTER_CTRL0_6", - "CFG_CENTER_WW4B2_14", - "CFG_CENTER_WW2END2_10", - "CFG_CENTER_EE4BEG1_19", - "CFG_CENTER_EE4A0_14", - "CFG_CENTER_LOGIC_OUTS_B10_9", - "CFG_CENTER_LOGIC_OUTS_B19_10", - "CFG_CENTER_SE4C0_13", - "CFG_CENTER_SW2A0_7", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_LOGIC_OUTS_B23_1", - "CFG_CENTER_LOGIC_OUTS_B0_19", - "CFG_CENTER_IMUX37_6", - "CFG_CENTER_SW4A0_5", - "CFG_CENTER_EE2BEG0_0", - "CFG_CENTER_WW4C1_11", - "CFG_CENTER_EE2A3_17", - "CFG_CENTER_LH9_7", - "CFG_CENTER_IMUX37_8", - "CFG_CENTER_LOGIC_OUTS_B10_10", - "CFG_CENTER_LOGIC_OUTS_B7_19", - "CFG_CENTER_WW2A2_12", - "CFG_CENTER_CLK0_13", - "CFG_CENTER_SE2A2_6", - "CFG_CENTER_NE4BEG1_19", - "CFG_CENTER_EE2BEG0_5", - "CFG_CENTER_BSCAN2_TCK", - "CFG_CENTER_LOGIC_OUTS_B12_18", - "CFG_CENTER_CK_BUFHCLK3", - "CFG_CENTER_IMUX21_15", - "CFG_CENTER_LOGIC_OUTS_B9_5", - "CFG_CENTER_EE4B3_7", - "CFG_CENTER_SW4END0_4", - "CFG_CENTER_BYP4_19", - "CFG_CENTER_CLK1_6", - "CFG_CENTER_FAN1_19", - "CFG_CENTER_WW4C0_0", - "CFG_CENTER_EE4A1_8", - "CFG_CENTER_IMUX30_6", - "CFG_CENTER_BYP2_16", - "CFG_CENTER_CK_BUFHCLK6", - "CFG_CENTER_IMUX47_5", - "CFG_CENTER_WR1END3_13", - "CFG_CENTER_IMUX14_13", - "CFG_CENTER_EE4BEG1_12", - "CFG_CENTER_IMUX22_15", - "CFG_CENTER_EE4C3_8", - "CFG_CENTER_IMUX20_0", - "CFG_CENTER_SW2A0_1", - "CFG_CENTER_SW4END2_15", - "CFG_CENTER_LOGIC_OUTS_B13_7", - "CFG_CENTER_FRAME_ECC_SYNDROME0", - "CFG_CENTER_NW2A2_13", - "CFG_CENTER_IMUX19_6", - "CFG_CENTER_EL1BEG3_0", - "CFG_CENTER_LOGIC_OUTS_B7_1", - "CFG_CENTER_WL1END1_12", - "CFG_CENTER_LH4_8", - "CFG_CENTER_IMUX10_18", - "CFG_CENTER_EE4A1_0", - "CFG_CENTER_NE4BEG3_8", - "CFG_CENTER_LOGIC_OUTS_B14_9", - "CFG_CENTER_IMUX6_4", - "CFG_CENTER_BYP2_6", - "CFG_CENTER_SW2A0_5", - "CFG_CENTER_LH1_1", - "CFG_CENTER_LOGIC_OUTS_B10_7", - "CFG_CENTER_IMUX24_2", - "CFG_CENTER_SW4A2_7", - "CFG_CENTER_LH8_17", - "CFG_CENTER_EE4BEG1_13", - "CFG_CENTER_ICAP1_I28", - "CFG_CENTER_IMUX16_15", - "CFG_CENTER_FAN6_19", - "CFG_CENTER_LOGIC_OUTS_B12_7", - "CFG_CENTER_IMUX37_3", - "CFG_CENTER_IMUX15_17", - "CFG_CENTER_EE4A3_9", - "CFG_CENTER_EE4A1_15", - "CFG_CENTER_NE4BEG2_10", - "CFG_CENTER_SE2A1_9", - "CFG_CENTER_EE4B1_0", - "CFG_CENTER_LOGIC_OUTS_B4_3", - "CFG_CENTER_IMUX47_1", - "CFG_CENTER_WW2END1_5", - "CFG_CENTER_BYP2_7", - "CFG_CENTER_WW4B2_16", - "CFG_CENTER_SW4A2_5", - "CFG_CENTER_FRAME_ECC_FAR16", - "CFG_CENTER_LOGIC_OUTS_B2_15", - "CFG_CENTER_ICAP1_O9", - "CFG_CENTER_WW4A0_7", - "CFG_CENTER_BYP2_19", - "CFG_CENTER_SW4A2_15", - "CFG_CENTER_SW4END1_7", - "CFG_CENTER_NW2A0_18", - "CFG_CENTER_LOGIC_OUTS_B6_10", - "CFG_CENTER_WW4C2_6", - "CFG_CENTER_SW2A0_12", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_FAN1_6", - "CFG_CENTER_IMUX22_13", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_IMUX4_9", - "CFG_CENTER_IMUX16_0", - "CFG_CENTER_IMUX16_17", - "CFG_CENTER_WW4END2_14", - "CFG_CENTER_SE2A0_17", - "CFG_CENTER_IMUX32_7", - "CFG_CENTER_IMUX7_15", - "CFG_CENTER_ICAP1_O11", - "CFG_CENTER_SW4END3_5", - "CFG_CENTER_WW4A1_0", - "CFG_CENTER_LOGIC_OUTS_B0_18", - "CFG_CENTER_WW4A2_0", - "CFG_CENTER_WW2A0_0", - "CFG_CENTER_EE4C3_17", - "CFG_CENTER_FAN4_2", - "CFG_CENTER_BLOCK_OUTS_B1_18", - "CFG_CENTER_IMUX17_12", - "CFG_CENTER_IMUX19_1", - "CFG_CENTER_WW2END1_7", - "CFG_CENTER_IMUX37_12", - "CFG_CENTER_IMUX33_9", - "CFG_CENTER_FAN7_10", - "CFG_CENTER_IMUX47_0", - "CFG_CENTER_SE2A0_14", - "CFG_CENTER_IMUX44_11", - "CFG_CENTER_FAN0_8", - "CFG_CENTER_NW4A1_14", - "CFG_CENTER_NW2A2_12", - "CFG_CENTER_BSCAN4_DRCK", - "CFG_CENTER_FAN3_17", - "CFG_CENTER_NE4BEG0_13", - "CFG_CENTER_EE4B3_14", - "CFG_CENTER_WL1END2_15", - "CFG_CENTER_LOGIC_OUTS_B23_10", - "CFG_CENTER_LOGIC_OUTS_B20_19", - "CFG_CENTER_FAN5_19", - "CFG_CENTER_STARTUP_CFGCLK", - "CFG_CENTER_EE4C0_11", - "CFG_CENTER_NE2A0_15", - "CFG_CENTER_IMUX5_14", - "CFG_CENTER_SW4A1_19", - "CFG_CENTER_EE4BEG3_9", - "CFG_CENTER_EE2BEG2_17", - "CFG_CENTER_EE4C1_12", - "CFG_CENTER_EE4B2_6", - "CFG_CENTER_EL1BEG1_16", - "CFG_CENTER_WW2A0_12", - "CFG_CENTER_SW4END1_14", - "CFG_CENTER_SE4BEG2_3", - "CFG_CENTER_EE4BEG1_5", - "CFG_CENTER_IMUX7_10", - "CFG_CENTER_SE4BEG3_18", - "CFG_CENTER_NW4END3_16", - "CFG_CENTER_LOGIC_OUTS_B8_7", - "CFG_CENTER_IMUX41_14", - "CFG_CENTER_FAN1_7", - "CFG_CENTER_SW2A1_14", - "CFG_CENTER_BYP0_9", - "CFG_CENTER_NW4END0_0", - "CFG_CENTER_IMUX41_2", - "CFG_CENTER_IMUX20_3", - "CFG_CENTER_EE4BEG1_4", - "CFG_CENTER_SE4C1_7", - "CFG_CENTER_LH3_14", - "CFG_CENTER_SW4A3_10", - "CFG_CENTER_BSCAN4_UPDATE", - "CFG_CENTER_SE2A2_3", - "CFG_CENTER_LOGIC_OUTS_B20_16", - "CFG_CENTER_LOGIC_OUTS_B17_8", - "CFG_CENTER_CFG_IO_ACCESS_MASTER", - "CFG_CENTER_EL1BEG1_2", - "CFG_CENTER_EE4C1_17", - "CFG_CENTER_EE4B3_11", - "CFG_CENTER_IMUX38_16", - "CFG_CENTER_NE4BEG3_18", - "CFG_CENTER_ICAP0_O24", - "CFG_CENTER_WW2END1_11", - "CFG_CENTER_LOGIC_OUTS_B12_3", - "CFG_CENTER_NW2A2_8", - "CFG_CENTER_SW4A3_17", - "CFG_CENTER_FAN5_10", - "CFG_CENTER_SE2A0_4", - "CFG_CENTER_LOGIC_OUTS_B12_12", - "CFG_CENTER_CLK0_11", - "CFG_CENTER_WW4END1_12", - "CFG_CENTER_EE4C3_3", - "CFG_CENTER_LOGIC_OUTS_B16_8", - "CFG_CENTER_WW4A1_1", - "CFG_CENTER_IMUX25_10", - "CFG_CENTER_EE2BEG0_4", - "CFG_CENTER_SE4C3_4", - "CFG_CENTER_LOGIC_OUTS_B18_12", - "CFG_CENTER_EE4A1_14", - "CFG_CENTER_PMVIOB_ODIV4", - "CFG_CENTER_NE4C3_6", - "CFG_CENTER_IMUX14_0", - "CFG_CENTER_SE4C2_16", - "CFG_CENTER_EE4A0_0", - "CFG_CENTER_EE4B2_8", - "CFG_CENTER_WW2END3_0", - "CFG_CENTER_ER1BEG2_19", - "CFG_CENTER_LOGIC_OUTS_B11_2", - "CFG_CENTER_EL1BEG1_6", - "CFG_CENTER_IMUX5_3", - "CFG_CENTER_USR_ACCESS_DATA31", - "CFG_CENTER_NE2A3_7", - "CFG_CENTER_IMUX40_5", - "CFG_CENTER_IMUX37_0", - "CFG_CENTER_IMUX24_10", - "CFG_CENTER_ICAP0_I15", - "CFG_CENTER_WR1END3_6", - "CFG_CENTER_BLOCK_OUTS_B1_15", - "CFG_CENTER_BLOCK_OUTS_B2_13", - "CFG_CENTER_EE2A0_10", - "CFG_CENTER_IMUX18_7", - "CFG_CENTER_IMUX0_17", - "CFG_CENTER_LOGIC_OUTS_B0_3", - "CFG_CENTER_LH5_11", - "CFG_CENTER_BLOCK_OUTS_B3_18", - "CFG_CENTER_MID_DNA_PORT_CLK", - "CFG_CENTER_IMUX17_0", - "CFG_CENTER_IMUX38_0", - "CFG_CENTER_BLOCK_OUTS_B1_13", - "CFG_CENTER_NW4END0_4", - "CFG_CENTER_LOGIC_OUTS_B12_1", - "CFG_CENTER_LOGIC_OUTS_B6_6", - "CFG_CENTER_WW2END0_18", - "CFG_CENTER_WW4C2_5", - "CFG_CENTER_CK_IN11", - "CFG_CENTER_FRAME_ECC_ECCERROR", - "CFG_CENTER_FRAME_ECC_FAR13", - "CFG_CENTER_EE2BEG1_4", - "CFG_CENTER_LOGIC_OUTS_B20_5", - "CFG_CENTER_ICAP1_O10", - "CFG_CENTER_WW4B3_7", - "CFG_CENTER_NE4C3_13", - "CFG_CENTER_SW4END3_0", - "CFG_CENTER_BYP7_19", - "CFG_CENTER_LOGIC_OUTS_B3_17", - "CFG_CENTER_SE2A3_4", - "CFG_CENTER_LOGIC_OUTS_B16_1", - "CFG_CENTER_CTRL1_6", - "CFG_CENTER_NW4A0_11", - "CFG_CENTER_WW4C1_9", - "CFG_CENTER_SE2A0_10", - "CFG_CENTER_WW4C1_18", - "CFG_CENTER_ICAP1_I30", - "CFG_CENTER_LH2_11", - "CFG_CENTER_NE2A3_11", - "CFG_CENTER_NE4BEG3_9", - "CFG_CENTER_LOGIC_OUTS_B10_12", - "CFG_CENTER_EE2BEG2_12", - "CFG_CENTER_WR1END2_16", - "CFG_CENTER_LH2_3", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_IMUX47_4", - "CFG_CENTER_ER1BEG2_18", - "CFG_CENTER_LOGIC_OUTS_B8_12", - "CFG_CENTER_CLK0_1", - "CFG_CENTER_IMUX31_9", - "CFG_CENTER_MID_ICAP1_CLK", - "CFG_CENTER_IMUX29_4", - "CFG_CENTER_FAN0_14", - "CFG_CENTER_BYP1_8", - "CFG_CENTER_SE4C2_19", - "CFG_CENTER_NE4BEG0_1", - "CFG_CENTER_LOGIC_OUTS_B3_4", - "CFG_CENTER_SE2A3_8", - "CFG_CENTER_EE4A2_13", - "CFG_CENTER_LH1_18", - "CFG_CENTER_NE4BEG2_0", - "CFG_CENTER_FAN6_7", - "CFG_CENTER_IMUX27_5", - "CFG_CENTER_EE4BEG0_17", - "CFG_CENTER_ICAP1_O31", - "CFG_CENTER_IMUX22_6", - "CFG_CENTER_ICAP1_O0", - "CFG_CENTER_EE2A2_6", - "CFG_CENTER_IMUX27_19", - "CFG_CENTER_SW2A1_12", - "CFG_CENTER_FAN6_4", - "CFG_CENTER_SW4END0_9", - "CFG_CENTER_IMUX8_9", - "CFG_CENTER_LOGIC_OUTS_B3_6", - "CFG_CENTER_IMUX2_0", - "CFG_CENTER_SW4A2_13", - "CFG_CENTER_IMUX17_19", - "CFG_CENTER_IMUX11_9", - "CFG_CENTER_SE2A3_5", - "CFG_CENTER_BYP0_0", - "CFG_CENTER_WL1END1_18", - "CFG_CENTER_LH1_14", - "CFG_CENTER_IMUX46_1", - "CFG_CENTER_ER1BEG2_5", - "CFG_CENTER_FAN5_5", - "CFG_CENTER_IMUX0_4", - "CFG_CENTER_LOGIC_OUTS_B12_19", - "CFG_CENTER_EE4C1_0", - "CFG_CENTER_ICAP1_RDWRB", - "CFG_CENTER_NW2A0_0", - "CFG_CENTER_WL1END2_0", - "CFG_CENTER_WW4C2_13", - "CFG_CENTER_SE4C0_9", - "CFG_CENTER_USR_ACCESS_DATA17", - "CFG_CENTER_FAN5_4", - "CFG_CENTER_SW2A2_9", - "CFG_CENTER_EE4B1_8", - "CFG_CENTER_EE2BEG0_3", - "CFG_CENTER_SW4A2_14", - "CFG_CENTER_NE4C3_9", - "CFG_CENTER_CTRL1_16", - "CFG_CENTER_FAN2_12", - "CFG_CENTER_IMUX30_5", - "CFG_CENTER_FAN4_13", - "CFG_CENTER_LH5_8", - "CFG_CENTER_WW4B3_17", - "CFG_CENTER_BYP1_0", - "CFG_CENTER_SW4END1_3", - "CFG_CENTER_BYP6_7", - "CFG_CENTER_ICAP1_I23", - "CFG_CENTER_LOGIC_OUTS_B17_5", - "CFG_CENTER_IMUX13_3", - "CFG_CENTER_WW4END3_3", - "CFG_CENTER_NE4BEG1_0", - "CFG_CENTER_LOGIC_OUTS_B9_19", - "CFG_CENTER_IMUX20_14", - "CFG_CENTER_USR_ACCESS_DATA10", - "CFG_CENTER_WW4END2_7", - "CFG_CENTER_FRAME_ECC_SYNDROME9", - "CFG_CENTER_NW2A0_14", - "CFG_CENTER_WW4END1_0", - "CFG_CENTER_IMUX38_9", - "CFG_CENTER_IMUX12_18", - "CFG_CENTER_WW4B3_4", - "CFG_CENTER_LH2_19", - "CFG_CENTER_IMUX5_8", - "CFG_CENTER_SW4END2_10", - "CFG_CENTER_WW4C3_1", - "CFG_CENTER_EE4B0_0", - "CFG_CENTER_LOGIC_OUTS_B1_18", - "CFG_CENTER_EE4BEG0_15", - "CFG_CENTER_WW4C0_17", - "CFG_CENTER_EE4B3_3", - "CFG_CENTER_IMUX23_1", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_BYP0_15", - "CFG_CENTER_BSCAN1_CAPTURE", - "CFG_CENTER_WW4A0_13", - "CFG_CENTER_FAN5_12", - "CFG_CENTER_IMUX1_5", - "CFG_CENTER_BYP3_3", - "CFG_CENTER_IMUX23_16", - "CFG_CENTER_IMUX1_11", - "CFG_CENTER_WL1END2_16", - "CFG_CENTER_IMUX21_10", - "CFG_CENTER_LOGIC_OUTS_B12_0", - "CFG_CENTER_IMUX14_9", - "CFG_CENTER_IMUX13_11", - "CFG_CENTER_NE4C1_19", - "CFG_CENTER_SW4A3_4", - "CFG_CENTER_LH10_12", - "CFG_CENTER_LOGIC_OUTS_B13_17", - "CFG_CENTER_IMUX24_5", - "CFG_CENTER_WW4A0_11", - "CFG_CENTER_FAN0_6", - "CFG_CENTER_ER1BEG3_10", - "CFG_CENTER_FAN7_18", - "CFG_CENTER_IMUX24_4", - "CFG_CENTER_EE4A1_7", - "CFG_CENTER_IMUX42_0", - "CFG_CENTER_LOGIC_OUTS_B3_1", - "CFG_CENTER_WL1END1_7", - "CFG_CENTER_LH10_5", - "CFG_CENTER_CTRL0_17", - "CFG_CENTER_ICAP0_I18", - "CFG_CENTER_LH5_15", - "CFG_CENTER_FAN1_18", - "CFG_CENTER_LOGIC_OUTS_B22_6", - "CFG_CENTER_WW2END0_1", - "CFG_CENTER_BYP5_3", - "CFG_CENTER_WW2A2_0", - "CFG_CENTER_LOGIC_OUTS_B21_3", - "CFG_CENTER_BSCAN1_TCK", - "CFG_CENTER_LOGIC_OUTS_B11_5", - "CFG_CENTER_BLOCK_OUTS_B3_15", - "CFG_CENTER_WW4END2_15", - "CFG_CENTER_SE2A1_14", - "CFG_CENTER_IMUX0_11", - "CFG_CENTER_EE4B2_12", - "CFG_CENTER_FAN3_9", - "CFG_CENTER_NE4BEG1_2", - "CFG_CENTER_IMUX18_2", - "CFG_CENTER_EE4B0_2", - "CFG_CENTER_EL1BEG3_15", - "CFG_CENTER_WW4B2_18", - "CFG_CENTER_BYP0_2", - "CFG_CENTER_NE4C0_8", - "CFG_CENTER_IMUX30_12", - "CFG_CENTER_SW4A3_12", - "CFG_CENTER_LOGIC_OUTS_B2_4", - "CFG_CENTER_SW4END0_2", - "CFG_CENTER_NW4A0_19", - "CFG_CENTER_LH12_5", - "CFG_CENTER_IMUX18_5", - "CFG_CENTER_NE4BEG0_4", - "CFG_CENTER_CFG_IO_ACCESS_CCLK", - "CFG_CENTER_NW4A1_19", - "CFG_CENTER_LH5_9", - "CFG_CENTER_ER1BEG0_6", - "CFG_CENTER_NE2A2_11", - "CFG_CENTER_IMUX41_18", - "CFG_CENTER_USR_ACCESS_DATA28", - "CFG_CENTER_NW2A0_9", - "CFG_CENTER_LOGIC_OUTS_B6_19", - "CFG_CENTER_EE4C1_14", - "CFG_CENTER_NE4C2_9", - "CFG_CENTER_IMUX14_11", - "CFG_CENTER_LOGIC_OUTS_B15_9", - "CFG_CENTER_IMUX28_7", - "CFG_CENTER_FAN1_15", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA2", - "CFG_CENTER_WW2END0_9", - "CFG_CENTER_BYP2_13", - "CFG_CENTER_NE4BEG1_9", - "CFG_CENTER_IMUX28_19", - "CFG_CENTER_EE4C3_14", - "CFG_CENTER_LH10_10", - "CFG_CENTER_NW2A2_10", - "CFG_CENTER_NE4C2_2", - "CFG_CENTER_WW4END3_15", - "CFG_CENTER_IMUX45_13", - "CFG_CENTER_LH4_7", - "CFG_CENTER_WL1END3_2", - "CFG_CENTER_IMUX13_9", - "CFG_CENTER_WL1END0_14", - "CFG_CENTER_EL1BEG1_12", - "CFG_CENTER_EE4B0_16", - "CFG_CENTER_WW4B2_13", - "CFG_CENTER_FAN3_16", - "CFG_CENTER_LH10_2", - "CFG_CENTER_SE4C3_18", - "CFG_CENTER_BSCAN4_RUNTEST", - "CFG_CENTER_NW2A2_16", - "CFG_CENTER_EE2A0_8", - "CFG_CENTER_WW4END0_13", - "CFG_CENTER_WW4END2_11", - "CFG_CENTER_SE4BEG1_16", - "CFG_CENTER_WW2A0_6", - "CFG_CENTER_SE4C2_9", - "CFG_CENTER_FAN5_6", - "CFG_CENTER_LOGIC_OUTS_B5_1", - "CFG_CENTER_WW2A2_11", - "CFG_CENTER_USR_ACCESS_DATA29", - "CFG_CENTER_BLOCK_OUTS_B0_6", - "CFG_CENTER_EE4B1_5", - "CFG_CENTER_WW4B1_7", - "CFG_CENTER_BLOCK_OUTS_B3_12", - "CFG_CENTER_SW2A3_15", - "CFG_CENTER_ER1BEG0_12", - "CFG_CENTER_LOGIC_OUTS_B15_10", - "CFG_CENTER_WW4A0_2", - "CFG_CENTER_IMUX38_17", - "CFG_CENTER_LOGIC_OUTS_B20_12", - "CFG_CENTER_CK_IN9", - "CFG_CENTER_IMUX6_3", - "CFG_CENTER_CK_BUFHCLK10", - "CFG_CENTER_IMUX37_2", - "CFG_CENTER_IMUX35_1", - "CFG_CENTER_SW4A2_3", - "CFG_CENTER_SE4C2_12", - "CFG_CENTER_FAN0_15", - "CFG_CENTER_IMUX1_16", - "CFG_CENTER_EE4BEG2_3", - "CFG_CENTER_SW4A2_17", - "CFG_CENTER_LOGIC_OUTS_B7_14", - "CFG_CENTER_NE4C2_19", - "CFG_CENTER_ICAP1_O25", - "CFG_CENTER_SE4BEG1_11", - "CFG_CENTER_SW4A1_7", - "CFG_CENTER_WW2END3_9", - "CFG_CENTER_SW2A2_17", - "CFG_CENTER_ICAP0_I13", - "CFG_CENTER_EE2BEG3_9", - "CFG_CENTER_LH6_11", - "CFG_CENTER_NE2A1_10", - "CFG_CENTER_WW4END1_14", - "CFG_CENTER_EE4C0_6", - "CFG_CENTER_IMUX31_7", - "CFG_CENTER_LH10_13", - "CFG_CENTER_IMUX18_19", - "CFG_CENTER_LOGIC_OUTS_B5_14", - "CFG_CENTER_IMUX43_1", - "CFG_CENTER_EE4C0_4", - "CFG_CENTER_ER1BEG0_0", - "CFG_CENTER_WW4END2_6", - "CFG_CENTER_LOGIC_OUTS_B22_16", - "CFG_CENTER_WW2END2_1", - "CFG_CENTER_WW4C1_14", - "CFG_CENTER_SW2A2_6", - "CFG_CENTER_SW2A3_17", - "CFG_CENTER_EE2BEG2_7", - "CFG_CENTER_EL1BEG0_17", - "CFG_CENTER_BSCAN2_TDO", - "CFG_CENTER_WW2A1_6", - "CFG_CENTER_BSCAN1_SHIFT", - "CFG_CENTER_EE4BEG1_11", - "CFG_CENTER_IMUX4_12", - "CFG_CENTER_LOGIC_OUTS_B0_11", - "CFG_CENTER_FAN6_16", - "CFG_CENTER_SW2A1_15", - "CFG_CENTER_SW2A3_8", - "CFG_CENTER_CTRL1_13", - "CFG_CENTER_LOGIC_OUTS_B20_6", - "CFG_CENTER_EE2BEG2_19", - "CFG_CENTER_WW4B3_12", - "CFG_CENTER_BLOCK_OUTS_B2_18", - "CFG_CENTER_WL1END0_3", - "CFG_CENTER_WL1END0_12", - "CFG_CENTER_SW4END0_6", - "CFG_CENTER_EE2BEG1_12", - "CFG_CENTER_SE4BEG0_4", - "CFG_CENTER_CTRL0_16", - "CFG_CENTER_ER1BEG2_1", - "CFG_CENTER_IMUX42_15", - "CFG_CENTER_LH1_19", - "CFG_CENTER_ICAP1_O23", - "CFG_CENTER_EE4C1_1", - "CFG_CENTER_IMUX15_3", - "CFG_CENTER_EE4C3_12", - "CFG_CENTER_FRAME_ECC_FAR4", - "CFG_CENTER_BYP1_19", - "CFG_CENTER_LOGIC_OUTS_B17_4", - "CFG_CENTER_LH3_5", - "CFG_CENTER_NW4A3_13", - "CFG_CENTER_WW2END3_5", - "CFG_CENTER_WW4A3_12", - "CFG_CENTER_WW4A3_8", - "CFG_CENTER_WL1END1_19", - "CFG_CENTER_IMUX24_15", - "CFG_CENTER_CTRL1_17", - "CFG_CENTER_EE2BEG1_7", + "CFG_CENTER_SW2A3_13", "CFG_CENTER_LH7_7", - "CFG_CENTER_LOGIC_OUTS_B12_8", - "CFG_CENTER_EL1BEG1_15", - "CFG_CENTER_FRAME_ECC_FAR22", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA9", - "CFG_CENTER_FAN7_9", - "CFG_CENTER_LOGIC_OUTS_B7_2", - "CFG_CENTER_SW4A0_7", - "CFG_CENTER_BSCAN2_SEL", - "CFG_CENTER_WW4C1_12", - "CFG_CENTER_LOGIC_OUTS_B14_5", - "CFG_CENTER_EE4BEG3_1", - "CFG_CENTER_LOGIC_OUTS_B7_17", - "CFG_CENTER_ICAP0_O28", - "CFG_CENTER_NW2A2_14", - "CFG_CENTER_EL1BEG1_4", - "CFG_CENTER_IMUX25_2", - "CFG_CENTER_LOGIC_OUTS_B1_9", - "CFG_CENTER_CTRL1_15", - "CFG_CENTER_LOGIC_OUTS_B3_8", - "CFG_CENTER_NE4C3_4", - "CFG_CENTER_CLK1_4", - "CFG_CENTER_IMUX15_9", - "CFG_CENTER_IMUX33_0", - "CFG_CENTER_NW4A1_8", - "CFG_CENTER_EE4A3_7", - "CFG_CENTER_WW4END1_13", - "CFG_CENTER_WW4C3_14", - "CFG_CENTER_IMUX1_8", - "CFG_CENTER_LOGIC_OUTS_B16_6", - "CFG_CENTER_NE4C3_0", - "CFG_CENTER_LOGIC_OUTS_B2_1", - "CFG_CENTER_ER1BEG1_16", - "CFG_CENTER_IMUX25_16", - "CFG_CENTER_IMUX22_14", - "CFG_CENTER_IMUX7_5", - "CFG_CENTER_SW2A2_0", - "CFG_CENTER_EL1BEG3_11", - "CFG_CENTER_EE4C0_15", - "CFG_CENTER_LOGIC_OUTS_B11_7", - "CFG_CENTER_FRAME_ECC_FAR25", - "CFG_CENTER_WW4C2_2", - "CFG_CENTER_BSCAN3_RESET", - "CFG_CENTER_EE2BEG0_7", - "CFG_CENTER_WW4C2_18", - "CFG_CENTER_IMUX14_5", - "CFG_CENTER_SE4BEG1_4", - "CFG_CENTER_EE4B0_5", - "CFG_CENTER_IMUX16_8", - "CFG_CENTER_LH7_0", - "CFG_CENTER_IMUX26_17", - "CFG_CENTER_LOGIC_OUTS_B0_17", - "CFG_CENTER_IMUX2_4", - "CFG_CENTER_LOGIC_OUTS_B5_4", - "CFG_CENTER_EE2BEG1_14", - "CFG_CENTER_IMUX26_0", - "CFG_CENTER_IMUX19_2", - "CFG_CENTER_NW4A2_3", - "CFG_CENTER_SE4C0_1", - "CFG_CENTER_EE2BEG2_0", - "CFG_CENTER_EE4C2_17", - "CFG_CENTER_SW4A0_16", - "CFG_CENTER_BLOCK_OUTS_B1_17", - "CFG_CENTER_EE2A1_9", - "CFG_CENTER_IMUX1_2", - "CFG_CENTER_EE2A1_2", - "CFG_CENTER_IMUX32_16", - "CFG_CENTER_NE2A0_19", - "CFG_CENTER_IMUX2_15", - "CFG_CENTER_ER1BEG3_9", - "CFG_CENTER_EE4C0_10", - "CFG_CENTER_IMUX3_7", - "CFG_CENTER_IMUX23_2", - "CFG_CENTER_IMUX45_9", - "CFG_CENTER_EE4C0_12", - "CFG_CENTER_ICAP0_O26", - "CFG_CENTER_IMUX17_15", - "CFG_CENTER_IMUX0_15", - "CFG_CENTER_WW4END3_0", - "CFG_CENTER_WL1END2_2", - "CFG_CENTER_EL1BEG2_4", - "CFG_CENTER_EE4A3_11", - "CFG_CENTER_LOGIC_OUTS_B17_19", - "CFG_CENTER_IMUX15_1", - "CFG_CENTER_EE4BEG3_13", - "CFG_CENTER_LOGIC_OUTS_B1_11", - "CFG_CENTER_IMUX23_14", - "CFG_CENTER_EE2A1_16", - "CFG_CENTER_LH11_2", - "CFG_CENTER_WW4END3_10", - "CFG_CENTER_LOGIC_OUTS_B14_7", - "CFG_CENTER_IMUX28_0", - "CFG_CENTER_EE4B2_3", - "CFG_CENTER_NE4C1_2", - "CFG_CENTER_IMUX13_2", - "CFG_CENTER_FAN5_2", - "CFG_CENTER_EE4B1_16", - "CFG_CENTER_IMUX5_15", - "CFG_CENTER_IMUX37_15", - "CFG_CENTER_IMUX46_18", - "CFG_CENTER_EE4A3_17", - "CFG_CENTER_IMUX22_10", - "CFG_CENTER_WR1END0_19", - "CFG_CENTER_FRAME_ECC_FAR3", - "CFG_CENTER_IMUX40_9", - "CFG_CENTER_IMUX24_12", - "CFG_CENTER_NW4END1_11", - "CFG_CENTER_IMUX22_16", - "CFG_CENTER_EE4BEG3_7", - "CFG_CENTER_WW4C0_6", - "CFG_CENTER_WW4C0_1", - "CFG_CENTER_BLOCK_OUTS_B1_0", - "CFG_CENTER_SW4A3_8", - "CFG_CENTER_EE4B2_17", - "CFG_CENTER_WL1END3_13", - "CFG_CENTER_EE4B1_15", - "CFG_CENTER_IMUX41_19", - "CFG_CENTER_NE2A1_9", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA6", - "CFG_CENTER_EE4BEG3_5", - "CFG_CENTER_IMUX6_11", - "CFG_CENTER_LOGIC_OUTS_B22_4", - "CFG_CENTER_IMUX42_7", - "CFG_CENTER_IMUX21_18", - "CFG_CENTER_WL1END3_16", - "CFG_CENTER_EE2BEG1_0", - "CFG_CENTER_CTRL1_19", - "CFG_CENTER_NE4C1_17", - "CFG_CENTER_SW2A2_5", - "CFG_CENTER_SE2A2_12", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA10", - "CFG_CENTER_WW2A3_12", - "CFG_CENTER_LH8_5", - "CFG_CENTER_IMUX8_1", - "CFG_CENTER_LOGIC_OUTS_B13_15", - "CFG_CENTER_WL1END3_12", - "CFG_CENTER_EE4BEG2_18", - "CFG_CENTER_IMUX0_12", - "CFG_CENTER_EL1BEG2_9", - "CFG_CENTER_NE4BEG0_0", - "CFG_CENTER_SE4BEG1_14", - "CFG_CENTER_CLK1_8", - "CFG_CENTER_WW2END2_7", - "CFG_CENTER_NW4A0_4", - "CFG_CENTER_LOGIC_OUTS_B14_0", - "CFG_CENTER_FAN4_12", - "CFG_CENTER_LH10_8", - "CFG_CENTER_LOGIC_OUTS_B5_17", - "CFG_CENTER_FAN3_12", - "CFG_CENTER_WR1END0_6", - "CFG_CENTER_SW4A3_6", - "CFG_CENTER_EE2BEG3_0", - "CFG_CENTER_LOGIC_OUTS_B23_4", - "CFG_CENTER_EE4C1_4", - "CFG_CENTER_WW2A1_7", - "CFG_CENTER_BLOCK_OUTS_B3_17", - "CFG_CENTER_IMUX36_2", - "CFG_CENTER_SE4C3_1", - "CFG_CENTER_NW2A2_2", - "CFG_CENTER_WW4END3_16", - "CFG_CENTER_SW4END1_0", - "CFG_CENTER_IMUX30_16", - "CFG_CENTER_EE2A2_11", - "CFG_CENTER_NE4BEG2_11", - "CFG_CENTER_CLK1_15", - "CFG_CENTER_IMUX38_12", - "CFG_CENTER_IMUX15_0", - "CFG_CENTER_LOGIC_OUTS_B13_4", - "CFG_CENTER_EL1BEG0_4", - "CFG_CENTER_LH8_13", - "CFG_CENTER_IMUX34_19", - "CFG_CENTER_SE4BEG0_9", - "CFG_CENTER_FAN5_8", - "CFG_CENTER_CFG_IO_ACCESS_INITBO", - "CFG_CENTER_IMUX28_13", - "CFG_CENTER_IMUX9_15", - "CFG_CENTER_CK_BUFHCLK9", - "CFG_CENTER_LOGIC_OUTS_B7_0", - "CFG_CENTER_BYP0_6", - "CFG_CENTER_ICAP1_O21", - "CFG_CENTER_EE4B1_11", - "CFG_CENTER_ICAP0_O27", - "CFG_CENTER_WW4B1_19", - "CFG_CENTER_NE2A0_11", - "CFG_CENTER_SW4END2_12", - "CFG_CENTER_NE4C1_6", - "CFG_CENTER_EE2BEG0_19", - "CFG_CENTER_IMUX25_17", - "CFG_CENTER_SE4BEG0_6", - "CFG_CENTER_SE4C0_14", - "CFG_CENTER_NE4BEG2_6", - "CFG_CENTER_LOGIC_OUTS_B21_16", - "CFG_CENTER_FAN5_13", - "CFG_CENTER_EE4BEG3_16", - "CFG_CENTER_CK_IN7", - "CFG_CENTER_IMUX21_14", - "CFG_CENTER_EL1BEG2_1", - "CFG_CENTER_WW2END0_16", - "CFG_CENTER_WW4A1_10", - "CFG_CENTER_BSCAN3_CAPTURE", - "CFG_CENTER_NE4C1_4", - "CFG_CENTER_LH11_15", - "CFG_CENTER_EE2BEG1_13", - "CFG_CENTER_LH3_16", - "CFG_CENTER_LOGIC_OUTS_B18_3", - "CFG_CENTER_IMUX46_7", - "CFG_CENTER_IMUX37_1", - "CFG_CENTER_BYP7_13", - "CFG_CENTER_IMUX19_4", - "CFG_CENTER_IMUX46_12", - "CFG_CENTER_LOGIC_OUTS_B3_2", - "CFG_CENTER_LOGIC_OUTS_B11_3", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_IMUX42_14", - "CFG_CENTER_SW4A0_10", - "CFG_CENTER_EE2A0_16", - "CFG_CENTER_SE4BEG2_0", - "CFG_CENTER_WW2A1_9", - "CFG_CENTER_SE4BEG3_8", - "CFG_CENTER_IMUX35_18", - "CFG_CENTER_WW4END1_7", - "CFG_CENTER_SW4END2_18", - "CFG_CENTER_IMUX6_5", - "CFG_CENTER_LOGIC_OUTS_B8_4", - "CFG_CENTER_WW4A2_9", - "CFG_CENTER_LH9_9", - "CFG_CENTER_WW4A3_2", - "CFG_CENTER_IMUX41_5", - "CFG_CENTER_FAN0_7", - "CFG_CENTER_BYP4_3", - "CFG_CENTER_WW4B1_3", - "CFG_CENTER_LH2_16", - "CFG_CENTER_EE4BEG2_10", - "CFG_CENTER_SW2A1_17", - "CFG_CENTER_IMUX17_16", - "CFG_CENTER_IMUX9_5", - "CFG_CENTER_NE4BEG2_2", - "CFG_CENTER_FRAME_ECC_SYNWORD4", - "CFG_CENTER_WW2A3_2", - "CFG_CENTER_NW2A2_18", - "CFG_CENTER_EE2BEG0_17", - "CFG_CENTER_LH5_6", - "CFG_CENTER_IMUX47_9", - "CFG_CENTER_IMUX16_9", - "CFG_CENTER_WR1END0_17", - "CFG_CENTER_LH9_16", - "CFG_CENTER_BLOCK_OUTS_B0_0", - "CFG_CENTER_IMUX27_12", - "CFG_CENTER_BLOCK_OUTS_B3_11", - "CFG_CENTER_EE4BEG1_0", - "CFG_CENTER_BYP1_7", - "CFG_CENTER_NW4END2_14", - "CFG_CENTER_IMUX4_18", - "CFG_CENTER_EL1BEG3_10", - "CFG_CENTER_BSCAN4_TDO", - "CFG_CENTER_NW4END0_3", - "CFG_CENTER_LOGIC_OUTS_B11_9", - "CFG_CENTER_BYP2_15", - "CFG_CENTER_WW4C0_2", - "CFG_CENTER_LH9_19", - "CFG_CENTER_BYP0_7", - "CFG_CENTER_IMUX46_15", - "CFG_CENTER_BYP2_5", - "CFG_CENTER_SW4END0_13", - "CFG_CENTER_SE4BEG3_11", - "CFG_CENTER_SE4BEG0_8", - "CFG_CENTER_LH4_13", - "CFG_CENTER_LOGIC_OUTS_B3_19", - "CFG_CENTER_FRAME_ECC_SYNWORD0", - "CFG_CENTER_SE4BEG0_13", - "CFG_CENTER_CLK1_14", - "CFG_CENTER_BLOCK_OUTS_B3_13", - "CFG_CENTER_IMUX35_19", - "CFG_CENTER_IMUX3_15", - "CFG_CENTER_LOGIC_OUTS_B10_15", - "CFG_CENTER_EE4C1_2", - "CFG_CENTER_ICAP0_I2", - "CFG_CENTER_NE4C2_1", - "CFG_CENTER_WW2END2_15", - "CFG_CENTER_SW4END2_2", - "CFG_CENTER_EE4C1_9", - "CFG_CENTER_IMUX25_7", - "CFG_CENTER_NE2A3_12", - "CFG_CENTER_BSCAN3_TCK", - "CFG_CENTER_WW2END0_0", - "CFG_CENTER_LOGIC_OUTS_B11_0", - "CFG_CENTER_WL1END3_15", - "CFG_CENTER_SE2A3_6", - "CFG_CENTER_NE2A2_12", - "CFG_CENTER_EE4A2_0", - "CFG_CENTER_IMUX30_19", - "CFG_CENTER_EE4A3_3", - "CFG_CENTER_EL1BEG2_19", - "CFG_CENTER_WR1END3_19", - "CFG_CENTER_BSCAN3_DRCK", - "CFG_CENTER_NW4END1_19", - "CFG_CENTER_LH9_1", - "CFG_CENTER_CTRL0_15", - "CFG_CENTER_BYP4_5", - "CFG_CENTER_NE4C3_12", - "CFG_CENTER_IMUX39_3", - "CFG_CENTER_WW2END0_3", - "CFG_CENTER_EE2A1_14", - "CFG_CENTER_BYP6_17", - "CFG_CENTER_IMUX29_9", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_SW4END0_3", - "CFG_CENTER_EE2A0_3", - "CFG_CENTER_IMUX10_0", - "CFG_CENTER_WL1END1_6", - "CFG_CENTER_IMUX35_16", - "CFG_CENTER_EE4B1_18", - "CFG_CENTER_EE2A0_11", - "CFG_CENTER_WL1END1_8", - "CFG_CENTER_EE2A2_17", - "CFG_CENTER_IMUX11_5", - "CFG_CENTER_SE4BEG3_13", - "CFG_CENTER_LOGIC_OUTS_B17_13", - "CFG_CENTER_ICAP0_O20", - "CFG_CENTER_BSCAN2_UPDATE", - "CFG_CENTER_NE4C0_13", - "CFG_CENTER_NE2A1_11", - "CFG_CENTER_FAN3_3", - "CFG_CENTER_IMUX22_4", - "CFG_CENTER_WL1END3_6", - "CFG_CENTER_NW4END1_8", - "CFG_CENTER_SW4A3_5", - "CFG_CENTER_FAN6_8", - "CFG_CENTER_BSCAN1_TMS", - "CFG_CENTER_IMUX21_2", - "CFG_CENTER_ICAP0_O15", - "CFG_CENTER_IMUX1_19", - "CFG_CENTER_NE4BEG1_13", - "CFG_CENTER_NE4C0_11", - "CFG_CENTER_NE4BEG0_3", - "CFG_CENTER_LH4_3", - "CFG_CENTER_PMVIOB_EN", - "CFG_CENTER_IMUX46_8", - "CFG_CENTER_IMUX40_12", - "CFG_CENTER_EE4BEG3_12", - "CFG_CENTER_LOGIC_OUTS_B4_4", - "CFG_CENTER_IMUX17_11", - "CFG_CENTER_LOGIC_OUTS_B20_4", - "CFG_CENTER_IMUX47_17", - "CFG_CENTER_ICAP1_I6", - "CFG_CENTER_IMUX28_17", - "CFG_CENTER_WW4A3_11", - "CFG_CENTER_LH11_12", - "CFG_CENTER_WW2END2_12", - "CFG_CENTER_NW2A1_3", - "CFG_CENTER_IMUX17_2", - "CFG_CENTER_STARTUP_PREQ", - "CFG_CENTER_IMUX25_4", - "CFG_CENTER_WW2A0_2", - "CFG_CENTER_BLOCK_OUTS_B3_3", - "CFG_CENTER_SW4END0_11", - "CFG_CENTER_EE4BEG3_2", - "CFG_CENTER_LH9_8", - "CFG_CENTER_SE4BEG1_5", - "CFG_CENTER_IMUX18_3", - "CFG_CENTER_IMUX45_17", - "CFG_CENTER_EE4B3_16", - "CFG_CENTER_USR_ACCESS_DATA11", - "CFG_CENTER_WW4A0_5", - "CFG_CENTER_EE4A3_18", - "CFG_CENTER_LOGIC_OUTS_B17_1", - "CFG_CENTER_SW2A0_16", - "CFG_CENTER_FAN0_5", - "CFG_CENTER_SE4C0_12", - "CFG_CENTER_FAN4_4", - "CFG_CENTER_WW2END3_7", - "CFG_CENTER_SE4C3_15", - "CFG_CENTER_CK_IN2", - "CFG_CENTER_SW2A0_6", - "CFG_CENTER_EE4B0_8", - "CFG_CENTER_IMUX36_10", - "CFG_CENTER_WW4C3_8", - "CFG_CENTER_SE2A1_18", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA7", - "CFG_CENTER_IMUX1_7", - "CFG_CENTER_SW2A1_16", - "CFG_CENTER_NE2A3_14", - "CFG_CENTER_BLOCK_OUTS_B1_8", - "CFG_CENTER_EE2A3_6", - "CFG_CENTER_EL1BEG0_5", - "CFG_CENTER_LOGIC_OUTS_B18_5", - "CFG_CENTER_ER1BEG2_6", - "CFG_CENTER_WW4END3_12", - "CFG_CENTER_IMUX13_6", - "CFG_CENTER_IMUX31_1", - "CFG_CENTER_IMUX42_17", - "CFG_CENTER_LH11_5", - "CFG_CENTER_EE4A2_12", - "CFG_CENTER_WW4END0_0", - "CFG_CENTER_IMUX27_17", - "CFG_CENTER_IMUX0_8", - "CFG_CENTER_WW4C2_14", - "CFG_CENTER_IMUX30_1", - "CFG_CENTER_ICAP0_I0", - "CFG_CENTER_SE4C2_17", - "CFG_CENTER_IMUX9_17", - "CFG_CENTER_NE4BEG0_11", - "CFG_CENTER_WW4END1_16", - "CFG_CENTER_LOGIC_OUTS_B16_17", - "CFG_CENTER_FAN2_18", - "CFG_CENTER_IMUX29_6", - "CFG_CENTER_EE2A1_15", - "CFG_CENTER_ICAP0_I31", - "CFG_CENTER_WW2A0_4", - "CFG_CENTER_EE4B3_15", - "CFG_CENTER_FRAME_ECC_SYNDROME11", - "CFG_CENTER_LOGIC_OUTS_B8_14", - "CFG_CENTER_FAN2_0", - "CFG_CENTER_EL1BEG2_2", - "CFG_CENTER_WL1END1_4", - "CFG_CENTER_EE2A1_19", - "CFG_CENTER_WR1END2_7", - "CFG_CENTER_BYP0_19", - "CFG_CENTER_NE4C3_16", - "CFG_CENTER_MID_CFG_IO_ACCESS_VGGCOMPOUT", - "CFG_CENTER_SE4C2_7", - "CFG_CENTER_EL1BEG2_13", - "CFG_CENTER_WW2END2_11", - "CFG_CENTER_IMUX5_1", - "CFG_CENTER_IMUX31_10", - "CFG_CENTER_LOGIC_OUTS_B23_6", - "CFG_CENTER_LH5_19", - "CFG_CENTER_SW2A3_7", - "CFG_CENTER_NW2A1_0", - "CFG_CENTER_IMUX47_18", - "CFG_CENTER_EE4A2_1", - "CFG_CENTER_FAN2_5", - "CFG_CENTER_BYP2_0", - "CFG_CENTER_WL1END0_16", - "CFG_CENTER_LH12_0", - "CFG_CENTER_NW4END3_9", - "CFG_CENTER_SW4END0_0", - "CFG_CENTER_EL1BEG1_0", - "CFG_CENTER_IMUX45_8", - "CFG_CENTER_IMUX2_17", - "CFG_CENTER_NW2A0_17", - "CFG_CENTER_FAN7_5", - "CFG_CENTER_LOGIC_OUTS_B15_0", - "CFG_CENTER_WW4C3_6", - "CFG_CENTER_IMUX11_16", - "CFG_CENTER_IMUX20_11", - "CFG_CENTER_WL1END3_10", - "CFG_CENTER_IMUX10_10", - "CFG_CENTER_NW4END3_3", - "CFG_CENTER_FRAME_ECC_FAR24", - "CFG_CENTER_NE4C3_2", - "CFG_CENTER_ER1BEG2_16", - "CFG_CENTER_SW4A0_18", - "CFG_CENTER_NE4BEG3_11", - "CFG_CENTER_SW4A0_19", - "CFG_CENTER_NE4C0_7", - "CFG_CENTER_BYP4_8", - "CFG_CENTER_IMUX1_18", - "CFG_CENTER_BYP3_7", - "CFG_CENTER_IMUX43_5", - "CFG_CENTER_EE2A1_5", - "CFG_CENTER_NW4END1_3", - "CFG_CENTER_WR1END1_5", - "CFG_CENTER_EE4BEG0_4", - "CFG_CENTER_NW4END0_16", - "CFG_CENTER_NW4A0_10", - "CFG_CENTER_NE4BEG0_14", - "CFG_CENTER_SE4BEG3_6", - "CFG_CENTER_CK_BUFHCLK8", - "CFG_CENTER_IMUX41_6", - "CFG_CENTER_IMUX32_14", - "CFG_CENTER_NW2A0_11", - "CFG_CENTER_SE4BEG3_4", - "CFG_CENTER_ER1BEG1_1", - "CFG_CENTER_SE4C0_7", - "CFG_CENTER_EE4C2_8", - "CFG_CENTER_IMUX26_10", - "CFG_CENTER_IMUX36_5", - "CFG_CENTER_WW2END3_17", - "CFG_CENTER_SW4A3_13", - "CFG_CENTER_LOGIC_OUTS_B19_7", - "CFG_CENTER_WW4B2_8", - "CFG_CENTER_BYP1_4", - "CFG_CENTER_EL1BEG1_19", - "CFG_CENTER_IMUX39_4", - "CFG_CENTER_WW4B1_5", - "CFG_CENTER_NE2A2_8", - "CFG_CENTER_BSCAN1_SEL", - "CFG_CENTER_IMUX42_8", - "CFG_CENTER_LOGIC_OUTS_B20_9", - "CFG_CENTER_NE2A3_10", - "CFG_CENTER_BYP6_12", - "CFG_CENTER_ICAP0_I11", - "CFG_CENTER_ICAP1_O8", - "CFG_CENTER_NW4END2_2", - "CFG_CENTER_WW4A1_8", - "CFG_CENTER_IMUX3_5", - "CFG_CENTER_WW2END1_6", - "CFG_CENTER_CK_BUFRCLK3", - "CFG_CENTER_SE2A0_8", - "CFG_CENTER_LOGIC_OUTS_B21_14", - "CFG_CENTER_FAN3_6", - "CFG_CENTER_WR1END2_17", - "CFG_CENTER_NE2A0_16", - "CFG_CENTER_IMUX10_19", - "CFG_CENTER_LOGIC_OUTS_B16_9", - "CFG_CENTER_NW4END3_12", - "CFG_CENTER_LOGIC_OUTS_B8_1", - "CFG_CENTER_IMUX32_10", - "CFG_CENTER_IMUX22_8", - "CFG_CENTER_ICAP1_O6", - "CFG_CENTER_MID_USR_ACCESS_DATA11", - "CFG_CENTER_ICAP1_I25", - "CFG_CENTER_FAN3_0", - "CFG_CENTER_FAN6_18", - "CFG_CENTER_IMUX33_7", - "CFG_CENTER_WW4A0_17", - "CFG_CENTER_IMUX0_1", - "CFG_CENTER_IMUX1_6", - "CFG_CENTER_FAN2_14", - "CFG_CENTER_EE4C2_9", - "CFG_CENTER_ER1BEG0_14", - "CFG_CENTER_SW4END3_11", - "CFG_CENTER_SW4END1_2", - "CFG_CENTER_LOGIC_OUTS_B9_17", - "CFG_CENTER_SE4C2_11", - "CFG_CENTER_BYP5_2", - "CFG_CENTER_SE4BEG2_2", - "CFG_CENTER_LOGIC_OUTS_B22_9", - "CFG_CENTER_IMUX47_3", - "CFG_CENTER_IMUX25_8", - "CFG_CENTER_SW2A0_2", - "CFG_CENTER_LOGIC_OUTS_B6_0", - "CFG_CENTER_WW2END2_18", - "CFG_CENTER_EE2BEG3_13", - "CFG_CENTER_IMUX23_19", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_SE4C1_16", - "CFG_CENTER_IMUX28_9", - "CFG_CENTER_BLOCK_OUTS_B3_1", - "CFG_CENTER_LOGIC_OUTS_B18_10", - "CFG_CENTER_IMUX36_9", - "CFG_CENTER_LH3_9", - "CFG_CENTER_IMUX17_13", - "CFG_CENTER_CTRL1_11", - "CFG_CENTER_SE2A1_12", - "CFG_CENTER_FAN4_1", - "CFG_CENTER_LOGIC_OUTS_B13_19", - "CFG_CENTER_WW4C0_14", - "CFG_CENTER_EE4A0_10", - "CFG_CENTER_FAN0_10", - "CFG_CENTER_SE4C1_2", - "CFG_CENTER_FRAME_ECC_SYNBIT3", - "CFG_CENTER_IMUX44_17", - "CFG_CENTER_LOGIC_OUTS_B10_13", - "CFG_CENTER_NE4BEG0_6", - "CFG_CENTER_IMUX27_15", - "CFG_CENTER_FAN4_6", - "CFG_CENTER_ICAP1_O20", - "CFG_CENTER_IMUX27_18", - "CFG_CENTER_EE4B3_2", - "CFG_CENTER_LOGIC_OUTS_B8_11", - "CFG_CENTER_ICAP0_O17", - "CFG_CENTER_SW2A3_10", - "CFG_CENTER_NW2A3_16", - "CFG_CENTER_IMUX4_3", - "CFG_CENTER_IMUX30_2", - "CFG_CENTER_WL1END3_17", - "CFG_CENTER_WW4END0_14", - "CFG_CENTER_SW2A2_10", - "CFG_CENTER_WR1END2_10", - "CFG_CENTER_EE4BEG3_18", - "CFG_CENTER_BYP5_8", - "CFG_CENTER_USR_ACCESS_DATA20", - "CFG_CENTER_SE2A1_1", - "CFG_CENTER_EE2A1_7", - "CFG_CENTER_LH9_14", - "CFG_CENTER_IMUX8_7", - "CFG_CENTER_SW4END0_15", - "CFG_CENTER_FAN1_4", - "CFG_CENTER_LOGIC_OUTS_B3_18", - "CFG_CENTER_EL1BEG0_7", - "CFG_CENTER_SW2A1_7", - "CFG_CENTER_IMUX18_13", - "CFG_CENTER_SE4C0_3", - "CFG_CENTER_EE4BEG0_10", - "CFG_CENTER_NW4A3_7", - "CFG_CENTER_LH1_17", - "CFG_CENTER_ER1BEG2_17", - "CFG_CENTER_IMUX6_0", - "CFG_CENTER_EL1BEG2_16", - "CFG_CENTER_EE4A1_2", - "CFG_CENTER_LH3_19", - "CFG_CENTER_BYP0_13", - "CFG_CENTER_IMUX28_6", - "CFG_CENTER_CK_BUFHCLK0", - "CFG_CENTER_WW2END1_4", - "CFG_CENTER_NW4END3_14", - "CFG_CENTER_NW2A1_14", - "CFG_CENTER_EE2A3_19", - "CFG_CENTER_LOGIC_OUTS_B19_1", - "CFG_CENTER_SE2A3_13", - "CFG_CENTER_WW2END3_11", - "CFG_CENTER_EL1BEG2_18", - "CFG_CENTER_IMUX16_12", - "CFG_CENTER_IMUX15_7", - "CFG_CENTER_WW2A0_13", - "CFG_CENTER_SW2A1_4", - "CFG_CENTER_SE4BEG1_9", - "CFG_CENTER_IMUX21_16", - "CFG_CENTER_SW4A0_4", - "CFG_CENTER_BLOCK_OUTS_B2_8", - "CFG_CENTER_LOGIC_OUTS_B6_13", - "CFG_CENTER_BLOCK_OUTS_B2_6", - "CFG_CENTER_WL1END0_0", - "CFG_CENTER_IMUX47_8", - "CFG_CENTER_IMUX40_1", - "CFG_CENTER_IMUX10_17", - "CFG_CENTER_ICAP1_O30", - "CFG_CENTER_EE4C0_3", - "CFG_CENTER_BSCAN4_SHIFT", - "CFG_CENTER_LH5_10", - "CFG_CENTER_IMUX31_3", - "CFG_CENTER_LOGIC_OUTS_B4_7", - "CFG_CENTER_WR1END1_19", - "CFG_CENTER_ER1BEG1_10", - "CFG_CENTER_EE2BEG3_1", - "CFG_CENTER_SW2A3_6", - "CFG_CENTER_SW4A1_0", - "CFG_CENTER_WW4END0_18", - "CFG_CENTER_SW2A1_19", - "CFG_CENTER_EL1BEG2_15", - "CFG_CENTER_BYP3_6", - "CFG_CENTER_NW4A0_1", - "CFG_CENTER_IMUX14_12", - "CFG_CENTER_NE4C2_17", - "CFG_CENTER_NE4BEG1_11", - "CFG_CENTER_BSCAN2_SHIFT", - "CFG_CENTER_NW2A3_3", - "CFG_CENTER_WW2END3_1", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA5", - "CFG_CENTER_ER1BEG3_8", - "CFG_CENTER_WW2A0_9", - "CFG_CENTER_EE4BEG3_3", - "CFG_CENTER_EE2BEG0_11", - "CFG_CENTER_WW4B3_6", - "CFG_CENTER_SW4END2_13", - "CFG_CENTER_CTRL1_4", - "CFG_CENTER_IMUX8_10", - "CFG_CENTER_BLOCK_OUTS_B2_19", - "CFG_CENTER_WW4B2_19", - "CFG_CENTER_LOGIC_OUTS_B10_16", - "CFG_CENTER_WW4END3_5", - "CFG_CENTER_LOGIC_OUTS_B9_15", - "CFG_CENTER_FAN1_13", - "CFG_CENTER_NW4A2_10", - "CFG_CENTER_WL1END1_13", - "CFG_CENTER_EE2A2_4", - "CFG_CENTER_NW4A0_3", - "CFG_CENTER_IMUX10_15", - "CFG_CENTER_FAN5_15", - "CFG_CENTER_EE2BEG0_13", - "CFG_CENTER_LH6_7", - "CFG_CENTER_IMUX7_13", - "CFG_CENTER_BYP6_14", - "CFG_CENTER_NE4BEG2_1", - "CFG_CENTER_LH6_14", - "CFG_CENTER_IMUX3_14", - "CFG_CENTER_SW4A1_14", - "CFG_CENTER_NW4A3_19", - "CFG_CENTER_ER1BEG1_18", - "CFG_CENTER_NE4C0_1", - "CFG_CENTER_SE4BEG3_14", - "CFG_CENTER_SW2A0_3", - "CFG_CENTER_FAN6_11", - "CFG_CENTER_SW4A3_0", - "CFG_CENTER_IMUX3_9", - "CFG_CENTER_NE2A2_17", - "CFG_CENTER_WR1END3_12", - "CFG_CENTER_ER1BEG0_3", - "CFG_CENTER_LH4_18", - "CFG_CENTER_IMUX8_6", - "CFG_CENTER_EE4BEG1_3", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_EE4B1_3", - "CFG_CENTER_WW4C2_1", - "CFG_CENTER_WW2A2_19", - "CFG_CENTER_NW4A2_9", - "CFG_CENTER_SW2A0_18", - "CFG_CENTER_LOGIC_OUTS_B14_1", - "CFG_CENTER_IMUX42_11", - "CFG_CENTER_WW4END0_6", - "CFG_CENTER_LH2_15", - "CFG_CENTER_IMUX3_0", - "CFG_CENTER_WR1END0_1", - "CFG_CENTER_BYP2_8", - "CFG_CENTER_ER1BEG1_4", - "CFG_CENTER_SE4BEG0_1", - "CFG_CENTER_EL1BEG3_6", - "CFG_CENTER_SW4A0_15", - "CFG_CENTER_SW4A1_9", - "CFG_CENTER_EE2A0_0", - "CFG_CENTER_WL1END0_4", - "CFG_CENTER_BLOCK_OUTS_B2_9", - "CFG_CENTER_LOGIC_OUTS_B17_2", - "CFG_CENTER_NE4C1_0", - "CFG_CENTER_IMUX45_0", - "CFG_CENTER_LOGIC_OUTS_B12_4", - "CFG_CENTER_LH4_5", - "CFG_CENTER_WW2A1_18", - "CFG_CENTER_EE2BEG2_11", - "CFG_CENTER_IMUX7_11", - "CFG_CENTER_IMUX17_7", - "CFG_CENTER_EE4B0_18", - "CFG_CENTER_BYP4_4", - "CFG_CENTER_LH10_0", - "CFG_CENTER_IMUX22_12", - "CFG_CENTER_CTRL0_14", - "CFG_CENTER_ICAP1_I31", - "CFG_CENTER_NW4A3_14", - "CFG_CENTER_LH9_13", - "CFG_CENTER_LH7_19", - "CFG_CENTER_EE4BEG1_6", - "CFG_CENTER_STARTUP_GSR", - "CFG_CENTER_IMUX33_1", - "CFG_CENTER_FAN7_1", - "CFG_CENTER_WW4C2_15", - "CFG_CENTER_IMUX41_17", - "CFG_CENTER_IMUX13_17", - "CFG_CENTER_LOGIC_OUTS_B2_5", - "CFG_CENTER_SW4END1_19", - "CFG_CENTER_LH12_10", - "CFG_CENTER_IMUX4_15", - "CFG_CENTER_IMUX13_18", - "CFG_CENTER_EE2BEG1_2", - "CFG_CENTER_LOGIC_OUTS_B21_18", - "CFG_CENTER_BLOCK_OUTS_B0_18", - "CFG_CENTER_WW4C0_19", - "CFG_CENTER_IMUX18_14", - "CFG_CENTER_EE4A2_11", - "CFG_CENTER_BYP0_16", - "CFG_CENTER_IMUX44_0", - "CFG_CENTER_NW2A0_15", - "CFG_CENTER_BYP3_11", - "CFG_CENTER_IMUX5_11", - "CFG_CENTER_SE4BEG2_19", - "CFG_CENTER_ER1BEG1_15", - "CFG_CENTER_BYP7_14", - "CFG_CENTER_IMUX39_13", - "CFG_CENTER_IMUX36_7", - "CFG_CENTER_IMUX46_5", - "CFG_CENTER_EE4B2_16", - "CFG_CENTER_WW4C0_16", - "CFG_CENTER_EL1BEG2_7", - "CFG_CENTER_SE4C0_19", - "CFG_CENTER_SE2A0_7", - "CFG_CENTER_IMUX28_14", - "CFG_CENTER_LH5_3", - "CFG_CENTER_CLK0_12", - "CFG_CENTER_IMUX10_6", - "CFG_CENTER_WW4B1_13", - "CFG_CENTER_WW4END1_18", - "CFG_CENTER_EE2BEG3_16", - "CFG_CENTER_WW4C3_16", - "CFG_CENTER_IMUX9_2", - "CFG_CENTER_BYP2_3", - "CFG_CENTER_BYP4_1", - "CFG_CENTER_IMUX40_2", - "CFG_CENTER_EE4A3_8", - "CFG_CENTER_WW2A1_10", - "CFG_CENTER_CTRL0_1", - "CFG_CENTER_SE4BEG0_16", - "CFG_CENTER_SE2A1_15", - "CFG_CENTER_IMUX32_18", - "CFG_CENTER_NE2A1_5", - "CFG_CENTER_IMUX29_1", - "CFG_CENTER_LH12_9", - "CFG_CENTER_IMUX39_18", - "CFG_CENTER_SE4BEG2_13", - "CFG_CENTER_IMUX36_17", - "CFG_CENTER_IMUX3_6", - "CFG_CENTER_IMUX5_7", - "CFG_CENTER_LH12_14", - "CFG_CENTER_EE4BEG0_12", - "CFG_CENTER_USR_ACCESS_DATA8", - "CFG_CENTER_CTRL1_18", - "CFG_CENTER_IMUX12_11", - "CFG_CENTER_WR1END0_10", - "CFG_CENTER_LOGIC_OUTS_B14_2", - "CFG_CENTER_IMUX42_13", - "CFG_CENTER_BLOCK_OUTS_B0_11", - "CFG_CENTER_FAN1_14", - "CFG_CENTER_NE2A3_4", - "CFG_CENTER_FAN3_2", - "CFG_CENTER_FAN1_9", - "CFG_CENTER_CLK1_3", - "CFG_CENTER_EE2A1_1", - "CFG_CENTER_NE2A2_2", - "CFG_CENTER_IMUX30_14", - "CFG_CENTER_NW4A3_8", - "CFG_CENTER_LH10_11", - "CFG_CENTER_LOGIC_OUTS_B5_2", - "CFG_CENTER_SW4END3_8", - "CFG_CENTER_LOGIC_OUTS_B1_19", - "CFG_CENTER_LOGIC_OUTS_B17_17", - "CFG_CENTER_NW4A0_12", - "CFG_CENTER_LOGIC_OUTS_B11_8", - "CFG_CENTER_IMUX19_3", - "CFG_CENTER_IMUX12_17", - "CFG_CENTER_IMUX36_13", - "CFG_CENTER_NE4BEG3_10", - "CFG_CENTER_IMUX11_7", - "CFG_CENTER_LOGIC_OUTS_B6_17", - "CFG_CENTER_IMUX8_13", - "CFG_CENTER_ICAP1_O5", - "CFG_CENTER_FAN4_16", - "CFG_CENTER_IMUX17_8", - "CFG_CENTER_IMUX34_16", - "CFG_CENTER_LOGIC_OUTS_B9_11", - "CFG_CENTER_LOGIC_OUTS_B4_10", - "CFG_CENTER_BYP2_10", - "CFG_CENTER_SE2A3_14", - "CFG_CENTER_FAN4_8", - "CFG_CENTER_LOGIC_OUTS_B4_16", - "CFG_CENTER_WW4B2_17", - "CFG_CENTER_WW2A0_14", - "CFG_CENTER_ICAP0_O14", - "CFG_CENTER_IMUX17_10", - "CFG_CENTER_IMUX27_14", - "CFG_CENTER_LH9_10", - "CFG_CENTER_EE2A0_18", - "CFG_CENTER_IMUX38_7", - "CFG_CENTER_NE4C2_8", - "CFG_CENTER_SE2A1_16", - "CFG_CENTER_IMUX8_8", - "CFG_CENTER_IMUX12_0", - "CFG_CENTER_IMUX3_4", - "CFG_CENTER_EE2BEG1_18", - "CFG_CENTER_WR1END3_7", - "CFG_CENTER_LOGIC_OUTS_B6_2", - "CFG_CENTER_WW4A0_18", - "CFG_CENTER_LOGIC_OUTS_B19_4", - "CFG_CENTER_NE4C3_17", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_SE2A2_4", - "CFG_CENTER_LH10_15", - "CFG_CENTER_WW4B2_9", - "CFG_CENTER_FRAME_ECC_SYNWORD2", - "CFG_CENTER_LOGIC_OUTS_B3_9", - "CFG_CENTER_SW4A3_16", - "CFG_CENTER_NW4A0_15", - "CFG_CENTER_ICAP1_O26", - "CFG_CENTER_EE2A2_15", - "CFG_CENTER_IMUX26_5", - "CFG_CENTER_WW4A0_15", - "CFG_CENTER_LOGIC_OUTS_B19_13", - "CFG_CENTER_IMUX25_9", - "CFG_CENTER_CK_BUFRCLK1", - "CFG_CENTER_LOGIC_OUTS_B6_16", - "CFG_CENTER_EE4C0_0", - "CFG_CENTER_LOGIC_OUTS_B19_5", - "CFG_CENTER_ICAP0_I17", - "CFG_CENTER_IMUX15_6", - "CFG_CENTER_BYP4_13", - "CFG_CENTER_NW4A2_4", - "CFG_CENTER_ICAP0_O0", - "CFG_CENTER_LOGIC_OUTS_B13_13", - "CFG_CENTER_WL1END1_3", - "CFG_CENTER_IMUX42_19", - "CFG_CENTER_LOGIC_OUTS_B3_11", - "CFG_CENTER_EE4B2_9", - "CFG_CENTER_CLK0_4", - "CFG_CENTER_EE4BEG1_10", - "CFG_CENTER_ER1BEG2_12", - "CFG_CENTER_LH9_12", - "CFG_CENTER_SW4A1_10", - "CFG_CENTER_LOGIC_OUTS_B15_14", - "CFG_CENTER_IMUX10_14", - "CFG_CENTER_EE4BEG3_0", - "CFG_CENTER_CTRL1_14", - "CFG_CENTER_EE4A0_15", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA0", - "CFG_CENTER_EE4B2_7", - "CFG_CENTER_PMVIOB_ODIV2", - "CFG_CENTER_IMUX36_3", - "CFG_CENTER_LOGIC_OUTS_B3_15", - "CFG_CENTER_WW4B3_15", - "CFG_CENTER_LOGIC_OUTS_B5_0", - "CFG_CENTER_IMUX46_6", - "CFG_CENTER_LOGIC_OUTS_B20_15", - "CFG_CENTER_WW4A2_16", - "CFG_CENTER_EE4B2_19", - "CFG_CENTER_LOGIC_OUTS_B9_14", - "CFG_CENTER_IMUX46_16", - "CFG_CENTER_SW4A2_18", - "CFG_CENTER_SW4A3_3", - "CFG_CENTER_LH5_12", - "CFG_CENTER_NE4BEG3_19", - "CFG_CENTER_EE4B1_13", - "CFG_CENTER_NE2A1_13", - "CFG_CENTER_WW4C2_7", - "CFG_CENTER_BYP2_14", - "CFG_CENTER_LH10_4", - "CFG_CENTER_LOGIC_OUTS_B17_18", - "CFG_CENTER_NW2A0_12", - "CFG_CENTER_WW2A1_3", - "CFG_CENTER_IMUX34_1", - "CFG_CENTER_LOGIC_OUTS_B18_9", - "CFG_CENTER_NE4BEG1_15", - "CFG_CENTER_SW4END2_16", - "CFG_CENTER_IMUX8_17", - "CFG_CENTER_LH2_9", - "CFG_CENTER_WW4C1_0", - "CFG_CENTER_NW4A0_6", - "CFG_CENTER_IMUX27_16", - "CFG_CENTER_LOGIC_OUTS_B3_16", - "CFG_CENTER_LOGIC_OUTS_B3_3", - "CFG_CENTER_LH11_17", - "CFG_CENTER_NE2A3_19", - "CFG_CENTER_NW4END1_7", - "CFG_CENTER_IMUX18_10", - "CFG_CENTER_IMUX30_10", - "CFG_CENTER_CTRL0_11", - "CFG_CENTER_BLOCK_OUTS_B0_8", - "CFG_CENTER_NW4END3_7", - "CFG_CENTER_SW4A0_13", - "CFG_CENTER_NW4END3_2", - "CFG_CENTER_WW2END0_13", - "CFG_CENTER_EE2A3_1", - "CFG_CENTER_WW4END1_10", - "CFG_CENTER_SE4BEG1_15", - "CFG_CENTER_CLK0_7", - "CFG_CENTER_LOGIC_OUTS_B23_19", - "CFG_CENTER_IMUX32_15", - "CFG_CENTER_SW4A0_1", - "CFG_CENTER_IMUX0_19", - "CFG_CENTER_LOGIC_OUTS_B20_0", - "CFG_CENTER_SW2A0_4", - "CFG_CENTER_IMUX2_13", - "CFG_CENTER_BYP5_18", - "CFG_CENTER_WW4B1_16", - "CFG_CENTER_IMUX44_7", - "CFG_CENTER_FAN7_14", - "CFG_CENTER_LOGIC_OUTS_B7_11", - "CFG_CENTER_WR1END3_8", - "CFG_CENTER_BYP7_2", - "CFG_CENTER_EE4C2_12", - "CFG_CENTER_NW4A1_15", - "CFG_CENTER_NE4C1_13", - "CFG_CENTER_EL1BEG0_18", - "CFG_CENTER_WR1END0_9", - "CFG_CENTER_ICAP0_O22", - "CFG_CENTER_IMUX4_10", - "CFG_CENTER_SE4BEG0_5", - "CFG_CENTER_NE4BEG2_4", - "CFG_CENTER_IMUX33_18", - "CFG_CENTER_ER1BEG0_11", - "CFG_CENTER_ER1BEG0_1", - "CFG_CENTER_EE4BEG1_15", - "CFG_CENTER_MID_USR_ACCESS_DATA5", - "CFG_CENTER_LH12_6", - "CFG_CENTER_LOGIC_OUTS_B4_14", - "CFG_CENTER_NE4C0_2", - "CFG_CENTER_LOGIC_OUTS_B9_10", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_NE4BEG0_19", - "CFG_CENTER_LH5_17", - "CFG_CENTER_IMUX32_1", - "CFG_CENTER_IMUX41_12", - "CFG_CENTER_NE2A1_17", - "CFG_CENTER_SE4BEG0_10", - "CFG_CENTER_SW2A1_8", - "CFG_CENTER_NW4END2_6", - "CFG_CENTER_BSCAN2_TMS", - "CFG_CENTER_WW2A3_3", - "CFG_CENTER_FAN5_18", - "CFG_CENTER_EE2BEG2_15", - "CFG_CENTER_FAN2_13", - "CFG_CENTER_EE2BEG2_18", - "CFG_CENTER_NE2A2_14", - "CFG_CENTER_EE4BEG2_6", - "CFG_CENTER_ICAP0_I22", - "CFG_CENTER_IMUX22_5", - "CFG_CENTER_SE2A0_11", - "CFG_CENTER_WW4END0_17", - "CFG_CENTER_IMUX7_9", - "CFG_CENTER_LOGIC_OUTS_B22_13", - "CFG_CENTER_FRAME_ECC_SYNDROME5", - "CFG_CENTER_EL1BEG0_1", - "CFG_CENTER_IMUX22_3", - "CFG_CENTER_BLOCK_OUTS_B0_19", - "CFG_CENTER_IMUX7_3", - "CFG_CENTER_LOGIC_OUTS_B10_1", - "CFG_CENTER_WW4END3_9", - "CFG_CENTER_LH3_18", - "CFG_CENTER_IMUX44_16", - "CFG_CENTER_SW4END1_17", - "CFG_CENTER_NW2A0_19", - "CFG_CENTER_WL1END2_11", - "CFG_CENTER_NW4END0_18", - "CFG_CENTER_BLOCK_OUTS_B3_9", - "CFG_CENTER_LH7_1", - "CFG_CENTER_EE4A1_3", - "CFG_CENTER_IMUX46_0", - "CFG_CENTER_LOGIC_OUTS_B6_4", - "CFG_CENTER_LH2_5", - "CFG_CENTER_NW2A3_15", - "CFG_CENTER_WW4B0_2", - "CFG_CENTER_CTRL0_0", - "CFG_CENTER_IMUX30_11", - "CFG_CENTER_IMUX18_4", - "CFG_CENTER_NE4C1_9", - "CFG_CENTER_WW2END3_14", - "CFG_CENTER_IMUX41_8", - "CFG_CENTER_FAN5_11", - "CFG_CENTER_IMUX11_13", - "CFG_CENTER_FRAME_ECC_FAR9", - "CFG_CENTER_LH8_10", - "CFG_CENTER_WR1END3_11", - "CFG_CENTER_LH2_13", - "CFG_CENTER_LH5_7", - "CFG_CENTER_WW4END2_13", - "CFG_CENTER_EE2BEG0_12", - "CFG_CENTER_EE2A2_16", - "CFG_CENTER_IMUX13_4", - "CFG_CENTER_WL1END0_11", - "CFG_CENTER_NW2A3_2", - "CFG_CENTER_BLOCK_OUTS_B1_2", - "CFG_CENTER_WL1END1_5", - "CFG_CENTER_EE4B1_14", - "CFG_CENTER_EE2BEG0_16", - "CFG_CENTER_BYP7_12", - "CFG_CENTER_EE4C3_9", - "CFG_CENTER_EE4C1_5", - "CFG_CENTER_STARTUP_CFGMCLK", - "CFG_CENTER_IMUX17_14", - "CFG_CENTER_WW4B0_5", - "CFG_CENTER_EE4A2_3", - "CFG_CENTER_WW4B0_1", - "CFG_CENTER_BYP6_4", - "CFG_CENTER_SE4C2_2", - "CFG_CENTER_LH2_14", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA4", - "CFG_CENTER_IMUX44_12", - "CFG_CENTER_EL1BEG2_14", - "CFG_CENTER_LH12_13", - "CFG_CENTER_ICAP1_O22", - "CFG_CENTER_EE4BEG2_13", - "CFG_CENTER_EE2A3_2", - "CFG_CENTER_NW4END1_9", - "CFG_CENTER_EE4C2_11", - "CFG_CENTER_SW4END1_10", - "CFG_CENTER_WW4B2_11", - "CFG_CENTER_IMUX2_3", - "CFG_CENTER_ICAP1_CSIB", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_WW4C3_17", - "CFG_CENTER_EE4BEG0_7", - "CFG_CENTER_IMUX16_5", - "CFG_CENTER_LOGIC_OUTS_B1_17", - "CFG_CENTER_FAN3_1", - "CFG_CENTER_ICAP1_O27", - "CFG_CENTER_ICAP0_O10", - "CFG_CENTER_FAN6_1", - "CFG_CENTER_NE4BEG2_15", - "CFG_CENTER_WW4END0_19", - "CFG_CENTER_SE2A2_9", - "CFG_CENTER_EE4B3_12", - "CFG_CENTER_FAN2_19", - "CFG_CENTER_IMUX9_9", - "CFG_CENTER_IMUX15_13", - "CFG_CENTER_IMUX46_13", - "CFG_CENTER_IMUX28_11", - "CFG_CENTER_NE2A2_16", - "CFG_CENTER_LOGIC_OUTS_B7_5", - "CFG_CENTER_NW4END2_7", - "CFG_CENTER_LOGIC_OUTS_B10_14", - "CFG_CENTER_IMUX37_13", - "CFG_CENTER_WW4A2_5", - "CFG_CENTER_IMUX29_13", - "CFG_CENTER_IMUX16_4", - "CFG_CENTER_SE2A2_0", - "CFG_CENTER_LOGIC_OUTS_B16_0", - "CFG_CENTER_MID_USR_ACCESS_DATA6", - "CFG_CENTER_WL1END3_1", - "CFG_CENTER_SW2A3_1", - "CFG_CENTER_SW4A2_19", - "CFG_CENTER_IMUX4_5", - "CFG_CENTER_WR1END0_4", - "CFG_CENTER_SW2A3_12", - "CFG_CENTER_USR_ACCESS_DATA21", - "CFG_CENTER_ER1BEG3_0", - "CFG_CENTER_LH4_14", - "CFG_CENTER_IMUX36_11", - "CFG_CENTER_NW4A2_16", - "CFG_CENTER_ER1BEG3_15", - "CFG_CENTER_IMUX32_19", - "CFG_CENTER_WW4C3_0", - "CFG_CENTER_IMUX9_6", - "CFG_CENTER_SW2A2_4", - "CFG_CENTER_NE2A2_0", - "CFG_CENTER_WW4C1_1", - "CFG_CENTER_IMUX16_18", - "CFG_CENTER_EE2A0_4", - "CFG_CENTER_ICAP1_I13", - "CFG_CENTER_BYP4_14", - "CFG_CENTER_NW2A0_8", - "CFG_CENTER_LH4_12", - "CFG_CENTER_IMUX33_10", - "CFG_CENTER_CK_BUFHCLK4", - "CFG_CENTER_LOGIC_OUTS_B23_2", - "CFG_CENTER_ICAP0_RDWRB", - "CFG_CENTER_CK_IN1", - "CFG_CENTER_BSCAN1_RESET", - "CFG_CENTER_NW4END1_12", - "CFG_CENTER_IMUX10_11", - "CFG_CENTER_NE4C3_3", - "CFG_CENTER_EE4C0_16", - "CFG_CENTER_FAN4_15", - "CFG_CENTER_ER1BEG3_17", - "CFG_CENTER_WL1END3_18", - "CFG_CENTER_CTRL0_5", - "CFG_CENTER_SE4BEG2_15", - "CFG_CENTER_CK_IN5", - "CFG_CENTER_WW2END0_2", - "CFG_CENTER_EE4B0_17", - "CFG_CENTER_SE4BEG1_1", - "CFG_CENTER_FAN7_3", - "CFG_CENTER_LOGIC_OUTS_B14_15", - "CFG_CENTER_IMUX44_5", - "CFG_CENTER_IMUX24_16", - "CFG_CENTER_WW4B1_18", - "CFG_CENTER_LOGIC_OUTS_B11_6", - "CFG_CENTER_EE2A1_13", - "CFG_CENTER_IMUX2_5", - "CFG_CENTER_SE2A0_18", - "CFG_CENTER_EE4A3_13", - "CFG_CENTER_IMUX8_14", - "CFG_CENTER_IMUX34_17", - "CFG_CENTER_CTRL1_8", - "CFG_CENTER_IMUX45_1", - "CFG_CENTER_IMUX10_1", - "CFG_CENTER_WW2END2_8", - "CFG_CENTER_NW4END0_7", - "CFG_CENTER_FAN0_0", - "CFG_CENTER_LOGIC_OUTS_B14_16", - "CFG_CENTER_IMUX19_7", - "CFG_CENTER_WW2A2_6", - "CFG_CENTER_WW4A3_17", - "CFG_CENTER_ICAP1_I29", - "CFG_CENTER_LOGIC_OUTS_B2_8", - "CFG_CENTER_BYP5_0", - "CFG_CENTER_IMUX28_10", - "CFG_CENTER_EE4B1_10", - "CFG_CENTER_IMUX37_11", - "CFG_CENTER_NW4END1_14", - "CFG_CENTER_LOGIC_OUTS_B11_11", - "CFG_CENTER_ICAP1_O4", - "CFG_CENTER_LH3_11", - "CFG_CENTER_IMUX31_19", - "CFG_CENTER_NW4A1_11", - "CFG_CENTER_IMUX20_1", - "CFG_CENTER_WW4A1_9", - "CFG_CENTER_EE2BEG2_4", - "CFG_CENTER_LH4_19", - "CFG_CENTER_IMUX10_9", - "CFG_CENTER_ICAP0_O12", - "CFG_CENTER_WW2A3_1", - "CFG_CENTER_EL1BEG3_12", - "CFG_CENTER_ICAP0_O3", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_WW2END0_14", - "CFG_CENTER_WW4A2_15", - "CFG_CENTER_LOGIC_OUTS_B0_15", - "CFG_CENTER_WL1END1_9", - "CFG_CENTER_LOGIC_OUTS_B20_10", - "CFG_CENTER_NE4BEG0_16", - "CFG_CENTER_USR_ACCESS_DATA19", - "CFG_CENTER_SE4C2_6", - "CFG_CENTER_LH1_6", - "CFG_CENTER_EE4A0_19", - "CFG_CENTER_LH2_2", - "CFG_CENTER_NW4A3_15", - "CFG_CENTER_IMUX37_5", - "CFG_CENTER_NE4C2_14", - "CFG_CENTER_IMUX28_12", - "CFG_CENTER_LOGIC_OUTS_B1_1", - "CFG_CENTER_IMUX46_19", - "CFG_CENTER_IMUX41_15", - "CFG_CENTER_WW4A2_6", - "CFG_CENTER_SE4BEG1_8", - "CFG_CENTER_LOGIC_OUTS_B8_8", - "CFG_CENTER_ICAP1_O17", - "CFG_CENTER_SE2A2_14", - "CFG_CENTER_WW4C0_13", - "CFG_CENTER_IMUX31_12", - "CFG_CENTER_LOGIC_OUTS_B23_8", - "CFG_CENTER_LOGIC_OUTS_B17_6", - "CFG_CENTER_FAN1_17", - "CFG_CENTER_FAN2_6", - "CFG_CENTER_WW2END1_3", - "CFG_CENTER_IMUX20_18", - "CFG_CENTER_FAN4_0", - "CFG_CENTER_SW2A2_7", - "CFG_CENTER_IMUX2_10", - "CFG_CENTER_IMUX15_5", - "CFG_CENTER_EE4A3_2", - "CFG_CENTER_SE4BEG3_5", - "CFG_CENTER_SE4C3_10", - "CFG_CENTER_SE4C3_2", - "CFG_CENTER_LH2_6", - "CFG_CENTER_BLOCK_OUTS_B2_15", - "CFG_CENTER_BYP4_11", - "CFG_CENTER_LOGIC_OUTS_B3_14", - "CFG_CENTER_SE2A3_2", - "CFG_CENTER_IMUX11_4", - "CFG_CENTER_WW2A3_10", - "CFG_CENTER_IMUX7_16", - "CFG_CENTER_NW4END1_17", - "CFG_CENTER_IMUX18_8", - "CFG_CENTER_EL1BEG3_16", - "CFG_CENTER_IMUX25_6", - "CFG_CENTER_LOGIC_OUTS_B21_4", - "CFG_CENTER_EE2BEG3_19", - "CFG_CENTER_NE4BEG3_4", - "CFG_CENTER_EE4B2_14", - "CFG_CENTER_WW2A1_12", - "CFG_CENTER_IMUX25_11", - "CFG_CENTER_WW2A2_3", - "CFG_CENTER_EL1BEG1_17", - "CFG_CENTER_IMUX28_15", - "CFG_CENTER_CLK1_13", - "CFG_CENTER_SW4END2_17", - "CFG_CENTER_WW4C3_15", - "CFG_CENTER_BYP6_16", - "CFG_CENTER_MID_USR_ACCESS_DATA8", - "CFG_CENTER_WW4END2_17", - "CFG_CENTER_WW4A1_7", - "CFG_CENTER_WW2END1_17", - "CFG_CENTER_LOGIC_OUTS_B10_5", - "CFG_CENTER_WL1END1_1", - "CFG_CENTER_IMUX41_16", - "CFG_CENTER_IMUX12_6", - "CFG_CENTER_IMUX21_13", - "CFG_CENTER_FAN2_10", - "CFG_CENTER_LOGIC_OUTS_B8_16", - "CFG_CENTER_WW4B3_3", - "CFG_CENTER_WW2A1_0", - "CFG_CENTER_IMUX22_19", - "CFG_CENTER_CLK1_12", - "CFG_CENTER_LOGIC_OUTS_B21_0", - "CFG_CENTER_LOGIC_OUTS_B4_8", - "CFG_CENTER_SE4C0_15", - "CFG_CENTER_EE4B2_4", - "CFG_CENTER_LH4_17", - "CFG_CENTER_SE4BEG3_12", - "CFG_CENTER_LOGIC_OUTS_B16_18", - "CFG_CENTER_IMUX35_6", - "CFG_CENTER_IMUX8_19", - "CFG_CENTER_SW4A0_14", - "CFG_CENTER_WR1END1_16", - "CFG_CENTER_IMUX38_3", - "CFG_CENTER_EL1BEG0_12", - "CFG_CENTER_NW2A2_0", - "CFG_CENTER_WL1END3_7", - "CFG_CENTER_LH11_19", - "CFG_CENTER_EE4B3_4", - "CFG_CENTER_LOGIC_OUTS_B14_4", - "CFG_CENTER_LOGIC_OUTS_B6_1", - "CFG_CENTER_IMUX19_11", - "CFG_CENTER_WW4B3_0", - "CFG_CENTER_LOGIC_OUTS_B15_2", - "CFG_CENTER_LOGIC_OUTS_B15_8", - "CFG_CENTER_SW4END2_9", - "CFG_CENTER_SW2A2_12", - "CFG_CENTER_IMUX44_6", - "CFG_CENTER_NW4END0_11", - "CFG_CENTER_IMUX29_18", - "CFG_CENTER_NE4BEG2_19", - "CFG_CENTER_SW4END0_1", - "CFG_CENTER_CTRL0_3", - "CFG_CENTER_IMUX11_1", - "CFG_CENTER_NW2A1_7", - "CFG_CENTER_SW4END2_3", - "CFG_CENTER_IMUX43_10", - "CFG_CENTER_ICAP1_I19", - "CFG_CENTER_LOGIC_OUTS_B21_12", - "CFG_CENTER_CLK0_17", - "CFG_CENTER_SE2A0_0", - "CFG_CENTER_CTRL0_4", - "CFG_CENTER_NE2A0_1", - "CFG_CENTER_IMUX45_3", - "CFG_CENTER_ICAP0_I25", - "CFG_CENTER_LH11_0", - "CFG_CENTER_NE4C0_18", - "CFG_CENTER_ICAP0_CLK", - "CFG_CENTER_LOGIC_OUTS_B16_11", - "CFG_CENTER_FAN0_3", - "CFG_CENTER_IMUX43_2", - "CFG_CENTER_FAN7_4", - "CFG_CENTER_LOGIC_OUTS_B1_13", - "CFG_CENTER_WR1END1_4", - "CFG_CENTER_ER1BEG2_4", - "CFG_CENTER_FAN6_2", - "CFG_CENTER_FRAME_ECC_FAR6", - "CFG_CENTER_LH1_13", - "CFG_CENTER_LOGIC_OUTS_B20_13", - "CFG_CENTER_LOGIC_OUTS_B11_14", - "CFG_CENTER_LOGIC_OUTS_B4_0", - "CFG_CENTER_EL1BEG2_3", - "CFG_CENTER_NE4C3_5", - "CFG_CENTER_IMUX23_12", - "CFG_CENTER_EE2BEG1_15", - "CFG_CENTER_SE4BEG2_7", - "CFG_CENTER_EE2A1_12", - "CFG_CENTER_IMUX4_19", - "CFG_CENTER_WW4C0_8", - "CFG_CENTER_NE2A2_6", - "CFG_CENTER_NE4BEG1_12", - "CFG_CENTER_SE4C1_17", - "CFG_CENTER_IMUX40_7", - "CFG_CENTER_WW4A3_7", - "CFG_CENTER_FRAME_ECC_FAR17", - "CFG_CENTER_IMUX39_1", - "CFG_CENTER_SW2A3_9", - "CFG_CENTER_NW4END2_15", - "CFG_CENTER_WW4B0_0", - "CFG_CENTER_CAPTURE_CLK", - "CFG_CENTER_ICAP1_I16", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_SE4BEG1_19", - "CFG_CENTER_EL1BEG1_11", - "CFG_CENTER_NW2A2_19", - "CFG_CENTER_BYP6_6", - "CFG_CENTER_IMUX33_3", - "CFG_CENTER_WL1END2_5", - "CFG_CENTER_NE4C2_4", - "CFG_CENTER_BYP3_14", - "CFG_CENTER_NW2A1_19", - "CFG_CENTER_LH11_16", - "CFG_CENTER_LOGIC_OUTS_B21_10", - "CFG_CENTER_NE4BEG1_5", - "CFG_CENTER_LOGIC_OUTS_B2_11", - "CFG_CENTER_WW4A3_16", - "CFG_CENTER_MID_USR_ACCESS_DATA10", - "CFG_CENTER_WW2A2_13", - "CFG_CENTER_WW4B1_17", - "CFG_CENTER_NE4C1_7", - "CFG_CENTER_EE4C1_10", - "CFG_CENTER_IMUX25_15", - "CFG_CENTER_LOGIC_OUTS_B4_6", - "CFG_CENTER_ICAP0_O8", - "CFG_CENTER_EE4C3_11", - "CFG_CENTER_IMUX8_18", - "CFG_CENTER_LH8_11", - "CFG_CENTER_LOGIC_OUTS_B6_8", - "CFG_CENTER_WW4C3_13", - "CFG_CENTER_SW2A2_3", - "CFG_CENTER_SW4A0_12", - "CFG_CENTER_EE4C3_13", - "CFG_CENTER_BYP6_11", - "CFG_CENTER_EE4B1_7", - "CFG_CENTER_IMUX19_17", - "CFG_CENTER_LOGIC_OUTS_B8_19", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_EE4A1_13", - "CFG_CENTER_LH6_9", - "CFG_CENTER_BYP7_15", - "CFG_CENTER_IMUX16_11", - "CFG_CENTER_LH7_10", - "CFG_CENTER_ER1BEG3_5", - "CFG_CENTER_WR1END2_0", - "CFG_CENTER_NE4BEG1_6", - "CFG_CENTER_LOGIC_OUTS_B4_9", - "CFG_CENTER_IMUX26_6", - "CFG_CENTER_SW2A3_19", - "CFG_CENTER_IMUX27_3", - "CFG_CENTER_LOGIC_OUTS_B4_11", - "CFG_CENTER_EL1BEG3_2", - "CFG_CENTER_FAN5_0", - "CFG_CENTER_ER1BEG2_9", - "CFG_CENTER_NE4C1_5", - "CFG_CENTER_FAN1_11", - "CFG_CENTER_IMUX6_8", - "CFG_CENTER_NE4C0_19", - "CFG_CENTER_ICAP1_I26", - "CFG_CENTER_EE4A2_14", - "CFG_CENTER_NE4C3_15", - "CFG_CENTER_EL1BEG0_0", - "CFG_CENTER_SE4BEG3_15", - "CFG_CENTER_IMUX21_5", - "CFG_CENTER_WW4END0_12", - "CFG_CENTER_LOGIC_OUTS_B19_9", - "CFG_CENTER_LH12_1", - "CFG_CENTER_SW2A1_3", - "CFG_CENTER_WW4END0_10", - "CFG_CENTER_ICAP1_I15", - "CFG_CENTER_IMUX9_4", - "CFG_CENTER_ER1BEG2_13", - "CFG_CENTER_LOGIC_OUTS_B8_0", - "CFG_CENTER_LOGIC_OUTS_B2_17", - "CFG_CENTER_WW4C3_19", - "CFG_CENTER_EE4BEG0_18", - "CFG_CENTER_FAN3_8", - "CFG_CENTER_EE2BEG2_1", - "CFG_CENTER_WW2END0_19", - "CFG_CENTER_SE4C0_17", - "CFG_CENTER_NW4A0_0", - "CFG_CENTER_SE4BEG0_11", - "CFG_CENTER_USR_ACCESS_DATA25", - "CFG_CENTER_IMUX15_12", - "CFG_CENTER_FAN7_19", - "CFG_CENTER_EE2BEG3_11", - "CFG_CENTER_IMUX5_0", - "CFG_CENTER_IMUX13_5", - "CFG_CENTER_ICAP0_I4", - "CFG_CENTER_EE2BEG0_15", - "CFG_CENTER_IMUX9_8", - "CFG_CENTER_ER1BEG2_15", - "CFG_CENTER_EE2A3_14", - "CFG_CENTER_WW4C3_12", - "CFG_CENTER_LOGIC_OUTS_B21_19", - "CFG_CENTER_BYP1_10", - "CFG_CENTER_EE4B2_2", - "CFG_CENTER_NW4END3_10", - "CFG_CENTER_ER1BEG2_8", - "CFG_CENTER_IMUX40_13", - "CFG_CENTER_NE2A1_19", - "CFG_CENTER_SW4A3_15", - "CFG_CENTER_EL1BEG1_14", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_ICAP1_I14", - "CFG_CENTER_IMUX18_15", - "CFG_CENTER_WR1END2_12", - "CFG_CENTER_IMUX20_15", - "CFG_CENTER_LH6_18", - "CFG_CENTER_LOGIC_OUTS_B0_8", - "CFG_CENTER_ICAP1_O24", - "CFG_CENTER_NE4BEG0_12", - "CFG_CENTER_SW4A2_16", - "CFG_CENTER_NE4C0_4", - "CFG_CENTER_NW2A0_13", - "CFG_CENTER_NE4C2_10", - "CFG_CENTER_EE4BEG0_16", - "CFG_CENTER_FAN0_2", - "CFG_CENTER_EE4A3_1", - "CFG_CENTER_NE4BEG1_7", - "CFG_CENTER_EE4BEG0_11", - "CFG_CENTER_IMUX12_15", - "CFG_CENTER_EE2BEG1_9", - "CFG_CENTER_LOGIC_OUTS_B2_6", - "CFG_CENTER_EE2BEG1_6", - "CFG_CENTER_EE4BEG1_1", - "CFG_CENTER_NE2A3_16", - "CFG_CENTER_LH12_17", - "CFG_CENTER_SW2A0_11", - "CFG_CENTER_IMUX11_3", - "CFG_CENTER_IMUX43_14", - "CFG_CENTER_NW2A3_6", - "CFG_CENTER_WW4C3_2", - "CFG_CENTER_SE2A2_11", - "CFG_CENTER_LOGIC_OUTS_B18_16", - "CFG_CENTER_WW2A3_19", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_EE4BEG2_19", - "CFG_CENTER_NW4END3_4", - "CFG_CENTER_NE4BEG1_1", - "CFG_CENTER_EE4BEG3_17", - "CFG_CENTER_LOGIC_OUTS_B15_16", - "CFG_CENTER_NE4BEG0_9", - "CFG_CENTER_LOGIC_OUTS_B4_12", - "CFG_CENTER_WW4B0_11", - "CFG_CENTER_BLOCK_OUTS_B1_4", - "CFG_CENTER_IMUX27_2", - "CFG_CENTER_FRAME_ECC_SYNDROME7", - "CFG_CENTER_WW4B0_19", - "CFG_CENTER_LOGIC_OUTS_B7_6", - "CFG_CENTER_SW4END3_16", - "CFG_CENTER_WW4END0_3", - "CFG_CENTER_IMUX3_2", - "CFG_CENTER_LOGIC_OUTS_B4_5", - "CFG_CENTER_ER1BEG1_8", - "CFG_CENTER_NW2A1_15", - "CFG_CENTER_FAN0_16", - "CFG_CENTER_NW4A0_14", - "CFG_CENTER_IMUX43_18", - "CFG_CENTER_SE2A2_10", - "CFG_CENTER_IMUX44_18", - "CFG_CENTER_BYP7_1", - "CFG_CENTER_LOGIC_OUTS_B9_7", - "CFG_CENTER_IMUX8_11", - "CFG_CENTER_BLOCK_OUTS_B1_14", - "CFG_CENTER_LH5_1", - "CFG_CENTER_IMUX26_18", - "CFG_CENTER_SW2A3_16", - "CFG_CENTER_LOGIC_OUTS_B9_8", - "CFG_CENTER_BYP1_9", - "CFG_CENTER_SW2A3_3", - "CFG_CENTER_CTRL1_5", - "CFG_CENTER_LOGIC_OUTS_B5_9", - "CFG_CENTER_USR_ACCESS_DATA2", - "CFG_CENTER_BLOCK_OUTS_B1_16", - "CFG_CENTER_LOGIC_OUTS_B13_14", - "CFG_CENTER_STARTUP_USRDONEO", - "CFG_CENTER_SE4C1_8", - "CFG_CENTER_LOGIC_OUTS_B16_5", - "CFG_CENTER_IMUX3_19", - "CFG_CENTER_IMUX25_5", - "CFG_CENTER_IMUX24_1", - "CFG_CENTER_IMUX25_1", - "CFG_CENTER_ER1BEG1_6", - "CFG_CENTER_IMUX0_18", - "CFG_CENTER_SE4C3_6", - "CFG_CENTER_WW4END0_9", - "CFG_CENTER_WW2END3_18", - "CFG_CENTER_LOGIC_OUTS_B20_11", - "CFG_CENTER_IMUX1_3", - "CFG_CENTER_EE2BEG0_6", - "CFG_CENTER_LOGIC_OUTS_B3_5", - "CFG_CENTER_SE2A0_3", - "CFG_CENTER_LOGIC_OUTS_B22_19", - "CFG_CENTER_NE4BEG1_3", - "CFG_CENTER_SW4END1_15", - "CFG_CENTER_WW2END0_5", - "CFG_CENTER_SW4A0_0", - "CFG_CENTER_BSCAN3_UPDATE", - "CFG_CENTER_NE2A0_12", - "CFG_CENTER_NW2A0_5", - "CFG_CENTER_IMUX13_15", - "CFG_CENTER_IMUX27_4", - "CFG_CENTER_LOGIC_OUTS_B2_2", - "CFG_CENTER_IMUX20_13", - "CFG_CENTER_NW2A2_5", - "CFG_CENTER_WW4A1_5", - "CFG_CENTER_BLOCK_OUTS_B2_7", - "CFG_CENTER_IMUX1_15", - "CFG_CENTER_SE2A3_10", - "CFG_CENTER_EE4B0_15", - "CFG_CENTER_LOGIC_OUTS_B8_17", - "CFG_CENTER_IMUX36_15", - "CFG_CENTER_IMUX40_0", - "CFG_CENTER_IMUX12_1", - "CFG_CENTER_LOGIC_OUTS_B10_17", - "CFG_CENTER_WW4END2_19", - "CFG_CENTER_WW4B0_8", - "CFG_CENTER_SW4END1_13", - "CFG_CENTER_LOGIC_OUTS_B10_4", - "CFG_CENTER_ICAP1_O7", - "CFG_CENTER_WL1END2_6", - "CFG_CENTER_LOGIC_OUTS_B2_3", - "CFG_CENTER_IMUX10_3", - "CFG_CENTER_FAN4_18", - "CFG_CENTER_NW2A3_5", - "CFG_CENTER_IMUX25_19", - "CFG_CENTER_SE2A3_1", - "CFG_CENTER_WW4C2_19", - "CFG_CENTER_ER1BEG0_15", - "CFG_CENTER_IMUX24_17", - "CFG_CENTER_CLK0_10", - "CFG_CENTER_NE4C3_18", - "CFG_CENTER_ICAP0_I30", - "CFG_CENTER_EL1BEG0_2", - "CFG_CENTER_NW4A3_9", - "CFG_CENTER_IMUX28_1", - "CFG_CENTER_LOGIC_OUTS_B10_11", - "CFG_CENTER_WW4C1_13", - "CFG_CENTER_LOGIC_OUTS_B21_5", - "CFG_CENTER_NE2A3_18", - "CFG_CENTER_EE2BEG3_6", - "CFG_CENTER_EE4C1_15", - "CFG_CENTER_USR_ACCESS_DATA22", - "CFG_CENTER_SE4BEG2_10", - "CFG_CENTER_LH4_6", - "CFG_CENTER_EE4C3_1", - "CFG_CENTER_LOGIC_OUTS_B5_18", - "CFG_CENTER_NW4END1_18", - "CFG_CENTER_WW4C0_9", - "CFG_CENTER_IMUX2_16", - "CFG_CENTER_LOGIC_OUTS_B22_7", - "CFG_CENTER_NW4A1_4", - "CFG_CENTER_IMUX47_2", - "CFG_CENTER_IMUX22_17", - "CFG_CENTER_SW4END2_0", - "CFG_CENTER_LOGIC_OUTS_B12_2", - "CFG_CENTER_LH5_13", - "CFG_CENTER_WR1END2_11", - "CFG_CENTER_IMUX14_14", - "CFG_CENTER_BSCAN4_TCK", - "CFG_CENTER_SW2A2_1", - "CFG_CENTER_BYP7_5", - "CFG_CENTER_NW4END3_18", - "CFG_CENTER_LH3_1", - "CFG_CENTER_BYP5_15", - "CFG_CENTER_LH3_12", - "CFG_CENTER_BSCAN4_CAPTURE", - "CFG_CENTER_SW4A1_12", - "CFG_CENTER_WW2END0_10", - "CFG_CENTER_LOGIC_OUTS_B15_12", - "CFG_CENTER_WL1END1_10", - "CFG_CENTER_IMUX11_2", - "CFG_CENTER_SW4END3_19", - "CFG_CENTER_BYP5_10", - "CFG_CENTER_IMUX24_18", - "CFG_CENTER_NE4C2_7", - "CFG_CENTER_LH7_11", - "CFG_CENTER_IMUX21_8", - "CFG_CENTER_SW4A1_6", - "CFG_CENTER_IMUX11_19", - "CFG_CENTER_IMUX46_17", - "CFG_CENTER_SW2A0_14", - "CFG_CENTER_LH12_7", - "CFG_CENTER_USR_ACCESS_DATA9", - "CFG_CENTER_ER1BEG1_7", - "CFG_CENTER_IMUX0_16", - "CFG_CENTER_SE2A1_4", - "CFG_CENTER_WW4B0_14", - "CFG_CENTER_WL1END3_14", - "CFG_CENTER_LOGIC_OUTS_B23_17", - "CFG_CENTER_EE4C2_1", - "CFG_CENTER_IMUX32_5", - "CFG_CENTER_EL1BEG1_13", - "CFG_CENTER_LH11_6", - "CFG_CENTER_EE4BEG3_4", - "CFG_CENTER_SW2A0_17", - "CFG_CENTER_LOGIC_OUTS_B8_18", - "CFG_CENTER_NE2A1_16", - "CFG_CENTER_SW2A3_14", - "CFG_CENTER_SE4C2_15", - "CFG_CENTER_SW4A1_15", - "CFG_CENTER_FAN2_17", - "CFG_CENTER_NE2A0_0", - "CFG_CENTER_IMUX18_9", - "CFG_CENTER_LOGIC_OUTS_B0_12", - "CFG_CENTER_IMUX14_2", - "CFG_CENTER_EE2BEG1_10", - "CFG_CENTER_SE2A3_18", - "CFG_CENTER_BYP7_18", - "CFG_CENTER_SE4BEG2_8", - "CFG_CENTER_SE4BEG0_14", - "CFG_CENTER_IMUX43_6", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_FRAME_ECC_SYNWORD6", - "CFG_CENTER_WW4END3_2", - "CFG_CENTER_FRAME_ECC_SYNWORD5", - "CFG_CENTER_EE4BEG1_17", - "CFG_CENTER_IMUX39_8", - "CFG_CENTER_NE4BEG1_8", - "CFG_CENTER_SE4C0_18", - "CFG_CENTER_WW2A1_16", - "CFG_CENTER_EE4B2_11", - "CFG_CENTER_USR_ACCESS_DATA14", - "CFG_CENTER_IMUX30_0", - "CFG_CENTER_LOGIC_OUTS_B8_3", - "CFG_CENTER_IMUX33_6", - "CFG_CENTER_SE4BEG2_4", - "CFG_CENTER_FRAME_ECC_FAR5", - "CFG_CENTER_WW4C0_3", - "CFG_CENTER_NW4A1_12", - "CFG_CENTER_WR1END0_8", - "CFG_CENTER_SW2A0_8", - "CFG_CENTER_IMUX30_15", - "CFG_CENTER_IMUX46_11", - "CFG_CENTER_WW2END0_12", - "CFG_CENTER_WR1END3_4", - "CFG_CENTER_EE4B0_11", - "CFG_CENTER_FAN6_6", - "CFG_CENTER_WW4END0_16", - "CFG_CENTER_EL1BEG3_9", - "CFG_CENTER_NW4A3_3", - "CFG_CENTER_IMUX0_14", - "CFG_CENTER_WW4B1_15", - "CFG_CENTER_EL1BEG0_16", - "CFG_CENTER_BLOCK_OUTS_B0_7", - "CFG_CENTER_WW2A3_6", - "CFG_CENTER_IMUX44_1", - "CFG_CENTER_SE2A2_18", - "CFG_CENTER_LH7_15", - "CFG_CENTER_IMUX35_7", - "CFG_CENTER_IMUX19_10", - "CFG_CENTER_NW4A1_7", - "CFG_CENTER_NE2A2_18", - "CFG_CENTER_SE2A3_16", - "CFG_CENTER_EE2A2_0", - "CFG_CENTER_EE4B0_10", - "CFG_CENTER_IMUX7_2", - "CFG_CENTER_IMUX12_2", - "CFG_CENTER_IMUX41_1", - "CFG_CENTER_WW2END1_9", - "CFG_CENTER_ER1BEG1_19", - "CFG_CENTER_EE4C3_18", - "CFG_CENTER_IMUX29_0", - "CFG_CENTER_WW2END2_17", - "CFG_CENTER_FRAME_ECC_SYNBIT4", - "CFG_CENTER_NE2A0_8", - "CFG_CENTER_EE4C3_10", - "CFG_CENTER_IMUX33_11", - "CFG_CENTER_CLK0_2", - "CFG_CENTER_LOGIC_OUTS_B15_1", - "CFG_CENTER_EE4BEG2_17", - "CFG_CENTER_WW4END1_2", - "CFG_CENTER_FAN4_3", - "CFG_CENTER_WW4END0_15", - "CFG_CENTER_EE4BEG2_8", - "CFG_CENTER_SW2A3_2", - "CFG_CENTER_IMUX18_12", - "CFG_CENTER_FAN5_14", - "CFG_CENTER_CK_BUFRCLK0", - "CFG_CENTER_BLOCK_OUTS_B2_16", - "CFG_CENTER_LOGIC_OUTS_B8_13", - "CFG_CENTER_EE2BEG1_1", - "CFG_CENTER_NE4BEG2_3", - "CFG_CENTER_ER1BEG0_13", - "CFG_CENTER_BLOCK_OUTS_B1_3", - "CFG_CENTER_WW4A3_1", - "CFG_CENTER_SW4A2_2", - "CFG_CENTER_IMUX23_8", - "CFG_CENTER_IMUX26_16", - "CFG_CENTER_LOGIC_OUTS_B11_4", - "CFG_CENTER_WW4B2_7", - "CFG_CENTER_EE4A1_10", - "CFG_CENTER_LOGIC_OUTS_B23_5", - "CFG_CENTER_WW4A0_8", - "CFG_CENTER_IMUX13_12", - "CFG_CENTER_WW4END2_5", - "CFG_CENTER_SE2A3_12", - "CFG_CENTER_FAN3_10", - "CFG_CENTER_SW4A1_4", - "CFG_CENTER_IMUX35_11", - "CFG_CENTER_LOGIC_OUTS_B9_9", - "CFG_CENTER_WR1END3_0", - "CFG_CENTER_WR1END1_12", - "CFG_CENTER_BYP6_15", - "CFG_CENTER_IMUX33_2", - "CFG_CENTER_BLOCK_OUTS_B0_1", - "CFG_CENTER_IMUX33_16", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_FAN5_17", - "CFG_CENTER_IMUX44_19", - "CFG_CENTER_SE4C2_0", - "CFG_CENTER_IMUX32_4", - "CFG_CENTER_EE2A1_6", - "CFG_CENTER_SE4BEG0_2", - "CFG_CENTER_IMUX2_2", - "CFG_CENTER_WW4END3_7", - "CFG_CENTER_PMVIOB_O", - "CFG_CENTER_IMUX0_10", - "CFG_CENTER_LH6_12", - "CFG_CENTER_LOGIC_OUTS_B3_12", - "CFG_CENTER_EE2BEG2_2", - "CFG_CENTER_IMUX14_6", - "CFG_CENTER_EL1BEG2_8", - "CFG_CENTER_IMUX3_8", - "CFG_CENTER_IMUX21_11", - "CFG_CENTER_NW2A2_11", - "CFG_CENTER_EE4C0_7", - "CFG_CENTER_EE4B0_3", - "CFG_CENTER_SW2A1_2", - "CFG_CENTER_NE2A3_3", - "CFG_CENTER_LOGIC_OUTS_B19_3", - "CFG_CENTER_IMUX20_9", - "CFG_CENTER_SE4BEG1_13", - "CFG_CENTER_CK_BUFHCLK5", - "CFG_CENTER_SW4END3_7", - "CFG_CENTER_SW4END2_1", - "CFG_CENTER_LOGIC_OUTS_B7_7", - "CFG_CENTER_LOGIC_OUTS_B19_17", - "CFG_CENTER_IMUX43_0", - "CFG_CENTER_LH10_3", - "CFG_CENTER_WR1END3_14", - "CFG_CENTER_LOGIC_OUTS_B3_13", - "CFG_CENTER_NW4A2_5", - "CFG_CENTER_IMUX37_18", - "CFG_CENTER_IMUX23_4", - "CFG_CENTER_WW4B0_17", - "CFG_CENTER_IMUX7_7", - "CFG_CENTER_NW2A2_1", - "CFG_CENTER_BLOCK_OUTS_B0_14", - "CFG_CENTER_IMUX3_12", - "CFG_CENTER_EE4B2_5", - "CFG_CENTER_LH12_15", - "CFG_CENTER_WW4C3_11", - "CFG_CENTER_EL1BEG3_19", - "CFG_CENTER_WW2A3_8", - "CFG_CENTER_IMUX36_12", - "CFG_CENTER_NE2A0_13", - "CFG_CENTER_SW4A0_8", - "CFG_CENTER_EE2A3_10", - "CFG_CENTER_EE4A0_1", - "CFG_CENTER_ICAP0_I19", - "CFG_CENTER_IMUX43_15", - "CFG_CENTER_EL1BEG0_9", - "CFG_CENTER_EE4BEG1_7", - "CFG_CENTER_BYP7_11", - "CFG_CENTER_FAN7_13", - "CFG_CENTER_SE4C0_4", - "CFG_CENTER_LOGIC_OUTS_B9_6", - "CFG_CENTER_EE2A0_9", - "CFG_CENTER_WW4END2_9", - "CFG_CENTER_IMUX29_17", - "CFG_CENTER_NW4END3_1", - "CFG_CENTER_WW2A1_11", - "CFG_CENTER_ICAP1_I1", - "CFG_CENTER_NW4A2_12", - "CFG_CENTER_LOGIC_OUTS_B14_3", - "CFG_CENTER_WR1END1_10", - "CFG_CENTER_CLK1_17", - "CFG_CENTER_SW4END1_16", - "CFG_CENTER_IMUX1_12", - "CFG_CENTER_NW2A0_16", - "CFG_CENTER_WL1END2_17", - "CFG_CENTER_IMUX37_10", - "CFG_CENTER_LOGIC_OUTS_B21_1", - "CFG_CENTER_ER1BEG0_9", - "CFG_CENTER_NW4A1_2", - "CFG_CENTER_NE4C2_13", - "CFG_CENTER_LH7_12", - "CFG_CENTER_EL1BEG2_12", - "CFG_CENTER_WR1END2_14", - "CFG_CENTER_IMUX20_2", - "CFG_CENTER_WL1END0_1", - "CFG_CENTER_ER1BEG3_19", - "CFG_CENTER_LOGIC_OUTS_B22_17", - "CFG_CENTER_SE2A2_19", - "CFG_CENTER_LH3_2", - "CFG_CENTER_IMUX4_11", - "CFG_CENTER_EE4BEG2_4", - "CFG_CENTER_LOGIC_OUTS_B9_3", - "CFG_CENTER_EE2BEG2_3", - "CFG_CENTER_WR1END2_18", - "CFG_CENTER_LOGIC_OUTS_B22_12", - "CFG_CENTER_SE4C3_0", - "CFG_CENTER_FAN6_0", - "CFG_CENTER_IMUX23_9", - "CFG_CENTER_IMUX34_8", - "CFG_CENTER_WR1END3_17", - "CFG_CENTER_EE4BEG2_14", - "CFG_CENTER_FAN0_11", - "CFG_CENTER_BSCAN3_TDI", - "CFG_CENTER_USR_ACCESS_DATA30", - "CFG_CENTER_EE2BEG3_8", - "CFG_CENTER_WW4C2_11", - "CFG_CENTER_EE4C0_5", - "CFG_CENTER_SW4END0_19", - "CFG_CENTER_NW2A3_19", - "CFG_CENTER_WR1END3_18", - "CFG_CENTER_NW2A1_5", - "CFG_CENTER_WW4B3_5", - "CFG_CENTER_ICAP0_I28", - "CFG_CENTER_IMUX4_8", - "CFG_CENTER_ER1BEG3_2", - "CFG_CENTER_CFG_IO_ACCESS_MODE2", - "CFG_CENTER_WW4END2_18", - "CFG_CENTER_IMUX4_2", - "CFG_CENTER_BYP7_10", - "CFG_CENTER_LOGIC_OUTS_B19_0", - "CFG_CENTER_WR1END1_15", - "CFG_CENTER_LOGIC_OUTS_B17_10", - "CFG_CENTER_MID_USR_ACCESS_DATA14", - "CFG_CENTER_IMUX45_7", - "CFG_CENTER_IMUX6_19", - "CFG_CENTER_ICAP1_O18", - "CFG_CENTER_IMUX45_6", - "CFG_CENTER_NE2A3_1", - "CFG_CENTER_WW4END0_1", - "CFG_CENTER_SW2A0_0", - "CFG_CENTER_LH7_5", - "CFG_CENTER_EE4BEG0_14", - "CFG_CENTER_LOGIC_OUTS_B7_4", - "CFG_CENTER_EE4BEG3_10", - "CFG_CENTER_CK_IN0", - "CFG_CENTER_BYP6_0", - "CFG_CENTER_LOGIC_OUTS_B11_16", - "CFG_CENTER_IMUX42_3", - "CFG_CENTER_ICAP1_I7", - "CFG_CENTER_WL1END0_19", - "CFG_CENTER_WL1END2_4", - "CFG_CENTER_WL1END1_11", - "CFG_CENTER_WW4B2_2", - "CFG_CENTER_BYP5_12", - "CFG_CENTER_EE4A1_6", - "CFG_CENTER_SE2A3_7", - "CFG_CENTER_IMUX1_13", - "CFG_CENTER_EE4B3_18", - "CFG_CENTER_ER1BEG1_3", - "CFG_CENTER_LOGIC_OUTS_B10_6", - "CFG_CENTER_IMUX20_5", - "CFG_CENTER_BYP2_1", - "CFG_CENTER_EE2BEG3_4", - "CFG_CENTER_IMUX38_19", - "CFG_CENTER_ICAP1_I0", - "CFG_CENTER_EL1BEG3_17", - "CFG_CENTER_NW4END1_10", - "CFG_CENTER_LOGIC_OUTS_B22_8", - "CFG_CENTER_IMUX18_1", - "CFG_CENTER_CK_IN3", - "CFG_CENTER_SW4END3_3", - "CFG_CENTER_IMUX32_9", - "CFG_CENTER_NW4A0_9", - "CFG_CENTER_NE2A1_15", - "CFG_CENTER_WR1END0_15", - "CFG_CENTER_EE2A2_18", - "CFG_CENTER_BYP4_15", - "CFG_CENTER_IMUX18_11", - "CFG_CENTER_WW2A3_16", - "CFG_CENTER_NW2A3_0", - "CFG_CENTER_LH6_0", - "CFG_CENTER_SE4C1_11", - "CFG_CENTER_WW4END2_4", - "CFG_CENTER_PMVIOB_A1", - "CFG_CENTER_NE4BEG2_7", - "CFG_CENTER_BYP0_10", - "CFG_CENTER_LH7_4", - "CFG_CENTER_BYP5_7", - "CFG_CENTER_LOGIC_OUTS_B15_5", - "CFG_CENTER_FAN4_14", - "CFG_CENTER_WW4C0_15", - "CFG_CENTER_IMUX2_11", - "CFG_CENTER_WW4A3_18", - "CFG_CENTER_LOGIC_OUTS_B1_7", - "CFG_CENTER_BYP5_1", - "CFG_CENTER_NE2A2_4", - "CFG_CENTER_IMUX8_15", - "CFG_CENTER_WW2END0_11", - "CFG_CENTER_LOGIC_OUTS_B18_8", - "CFG_CENTER_IMUX34_18", - "CFG_CENTER_WW2A0_5", - "CFG_CENTER_BSCAN3_RUNTEST", - "CFG_CENTER_SE4BEG1_3", - "CFG_CENTER_WW4B2_3", - "CFG_CENTER_BYP3_18", - "CFG_CENTER_IMUX38_8", - "CFG_CENTER_BYP1_18", - "CFG_CENTER_IMUX34_7", - "CFG_CENTER_BYP4_17", - "CFG_CENTER_LH4_2", - "CFG_CENTER_BYP7_4", - "CFG_CENTER_USR_ACCESS_DATA3", - "CFG_CENTER_FRAME_ECC_SYNBIT1", - "CFG_CENTER_EL1BEG2_17", - "CFG_CENTER_LH1_3", - "CFG_CENTER_EE4A3_19", - "CFG_CENTER_ICAP0_I8", - "CFG_CENTER_WL1END1_17", - "CFG_CENTER_NE4BEG1_17", - "CFG_CENTER_NE4C1_18", - "CFG_CENTER_NE2A1_2", - "CFG_CENTER_IMUX14_4", - "CFG_CENTER_EE4BEG2_12", - "CFG_CENTER_WW2END2_3", - "CFG_CENTER_WW2A2_1", - "CFG_CENTER_EE4B0_6", - "CFG_CENTER_EE4B3_1", - "CFG_CENTER_LOGIC_OUTS_B10_0", - "CFG_CENTER_NW4A2_19", - "CFG_CENTER_IMUX39_5", - "CFG_CENTER_SW4END0_7", - "CFG_CENTER_BYP3_4", - "CFG_CENTER_EE4A1_4", - "CFG_CENTER_LOGIC_OUTS_B16_13", - "CFG_CENTER_LOGIC_OUTS_B18_1", - "CFG_CENTER_EE4C0_9", - "CFG_CENTER_LH3_0", - "CFG_CENTER_LH2_17", - "CFG_CENTER_IMUX17_3", - "CFG_CENTER_EE4BEG2_1", - "CFG_CENTER_NE4C3_10", - "CFG_CENTER_FAN5_7", - "CFG_CENTER_NE4BEG3_1", - "CFG_CENTER_WW2END0_8", - "CFG_CENTER_WW2END1_15", - "CFG_CENTER_WW4A0_1", - "CFG_CENTER_EE2BEG2_16", - "CFG_CENTER_LH9_0", - "CFG_CENTER_LH6_2", - "CFG_CENTER_IMUX34_13", - "CFG_CENTER_WW2END1_8", - "CFG_CENTER_EE2BEG2_8", - "CFG_CENTER_WW4A2_19", - "CFG_CENTER_BYP1_1", - "CFG_CENTER_NW4END1_16", - "CFG_CENTER_LOGIC_OUTS_B8_9", - "CFG_CENTER_BYP3_16", - "CFG_CENTER_EE2A0_2", - "CFG_CENTER_IMUX36_14", - "CFG_CENTER_WL1END2_1", - "CFG_CENTER_EE2A1_4", - "CFG_CENTER_IMUX40_15", - "CFG_CENTER_WW2A3_7", - "CFG_CENTER_EE2A0_12", - "CFG_CENTER_EE4A0_5", - "CFG_CENTER_IMUX39_10", - "CFG_CENTER_LH6_15", - "CFG_CENTER_FAN1_5", - "CFG_CENTER_NE4C2_15", - "CFG_CENTER_LH12_12", - "CFG_CENTER_IMUX9_14", - "CFG_CENTER_LOGIC_OUTS_B5_13", - "CFG_CENTER_LOGIC_OUTS_B13_3", - "CFG_CENTER_STARTUP_KEYCLEARB", - "CFG_CENTER_IMUX32_12", - "CFG_CENTER_IMUX19_18", - "CFG_CENTER_LH9_11", - "CFG_CENTER_ICAP1_O3", - "CFG_CENTER_SE2A3_19", - "CFG_CENTER_BYP4_12", - "CFG_CENTER_IMUX38_15", - "CFG_CENTER_WW2A1_4", - "CFG_CENTER_FRAME_ECC_FAR23", - "CFG_CENTER_EE4A3_14", - "CFG_CENTER_WW4C2_16", - "CFG_CENTER_IMUX40_18", - "CFG_CENTER_SE4C0_11", - "CFG_CENTER_IMUX9_16", - "CFG_CENTER_WR1END3_5", - "CFG_CENTER_FAN7_6", - "CFG_CENTER_LOGIC_OUTS_B0_6", - "CFG_CENTER_NW4A0_18", - "CFG_CENTER_IMUX3_16", - "CFG_CENTER_SE4BEG3_19", - "CFG_CENTER_EE2A3_7", - "CFG_CENTER_IMUX35_4", - "CFG_CENTER_ICAP1_I21", - "CFG_CENTER_WW2A3_11", - "CFG_CENTER_WR1END0_14", - "CFG_CENTER_LH6_13", - "CFG_CENTER_EE4C1_16", - "CFG_CENTER_BYP1_15", - "CFG_CENTER_WW2END2_16", - "CFG_CENTER_SE4C2_14", - "CFG_CENTER_IMUX34_12", - "CFG_CENTER_NE4C2_11", - "CFG_CENTER_USR_ACCESS_DATA0", - "CFG_CENTER_LH3_7", - "CFG_CENTER_IMUX24_6", - "CFG_CENTER_LOGIC_OUTS_B5_5", - "CFG_CENTER_WW4END2_1", - "CFG_CENTER_WW4B1_1", - "CFG_CENTER_LOGIC_OUTS_B18_7", - "CFG_CENTER_USR_ACCESS_DATA26", - "CFG_CENTER_CTRL0_2", - "CFG_CENTER_IMUX39_2", - "CFG_CENTER_NE2A0_4", - "CFG_CENTER_WW4C1_17", - "CFG_CENTER_BSCAN3_TDO", - "CFG_CENTER_WW2END1_16", - "CFG_CENTER_LOGIC_OUTS_B10_19", - "CFG_CENTER_EE4C3_4", - "CFG_CENTER_IMUX43_17", - "CFG_CENTER_WR1END1_6", - "CFG_CENTER_EE4B2_1", - "CFG_CENTER_ICAP0_O11", - "CFG_CENTER_BSCAN4_RESET", - "CFG_CENTER_BLOCK_OUTS_B2_1", - "CFG_CENTER_IMUX31_0", - "CFG_CENTER_IMUX41_13", - "CFG_CENTER_LH1_8", - "CFG_CENTER_FRAME_ECC_FAR21", - "CFG_CENTER_IMUX37_7", - "CFG_CENTER_LOGIC_OUTS_B1_3", - "CFG_CENTER_SE4C3_9", - "CFG_CENTER_EE2BEG0_18", - "CFG_CENTER_LOGIC_OUTS_B0_2", - "CFG_CENTER_WW2END2_4", - "CFG_CENTER_BLOCK_OUTS_B3_19", - "CFG_CENTER_IMUX42_6", - "CFG_CENTER_IMUX42_10", - "CFG_CENTER_WW4C0_7", - "CFG_CENTER_FRAME_ECC_FAR14", - "CFG_CENTER_BLOCK_OUTS_B2_3", - "CFG_CENTER_IMUX33_19", - "CFG_CENTER_LOGIC_OUTS_B2_18", - "CFG_CENTER_BSCAN1_DRCK", - "CFG_CENTER_NW2A2_7", - "CFG_CENTER_IMUX28_8", - "CFG_CENTER_EE4C2_13", - "CFG_CENTER_SE4BEG1_6", - "CFG_CENTER_ICAP1_O13", - "CFG_CENTER_IMUX32_17", - "CFG_CENTER_IMUX26_7", - "CFG_CENTER_LOGIC_OUTS_B11_10", - "CFG_CENTER_WW4B0_9", - "CFG_CENTER_EE2BEG1_8", - "CFG_CENTER_EE4A2_2", - "CFG_CENTER_BYP6_9", - "CFG_CENTER_EE2A3_11", - "CFG_CENTER_BSCAN1_RUNTEST", - "CFG_CENTER_ICAP1_I8", - "CFG_CENTER_SE4C3_13", - "CFG_CENTER_NE2A3_8", - "CFG_CENTER_LOGIC_OUTS_B3_0", - "CFG_CENTER_WW2END1_1", - "CFG_CENTER_WW4END1_19", - "CFG_CENTER_IMUX18_18", - "CFG_CENTER_IMUX28_3", - "CFG_CENTER_SE2A3_3", - "CFG_CENTER_WL1END3_8", - "CFG_CENTER_BLOCK_OUTS_B1_9", - "CFG_CENTER_WL1END3_4", - "CFG_CENTER_NE4C1_12", - "CFG_CENTER_WW4END3_17", - "CFG_CENTER_LOGIC_OUTS_B5_6", - "CFG_CENTER_CTRL0_13", - "CFG_CENTER_BSCAN3_SHIFT", - "CFG_CENTER_BYP6_1", - "CFG_CENTER_LOGIC_OUTS_B22_10", - "CFG_CENTER_SW4A1_13", - "CFG_CENTER_WL1END3_5", - "CFG_CENTER_BLOCK_OUTS_B3_7", - "CFG_CENTER_EE4B2_15", - "CFG_CENTER_NW4END0_19", - "CFG_CENTER_EE4BEG2_2", - "CFG_CENTER_WW4A0_19", - "CFG_CENTER_NE2A0_10", - "CFG_CENTER_LH11_10", - "CFG_CENTER_NW4END0_10", - "CFG_CENTER_LOGIC_OUTS_B22_3", - "CFG_CENTER_LOGIC_OUTS_B16_2", - "CFG_CENTER_STARTUP_GTS", - "CFG_CENTER_WL1END0_5", - "CFG_CENTER_BSCAN2_DRCK", - "CFG_CENTER_LOGIC_OUTS_B18_19", - "CFG_CENTER_SE4C1_9", - "CFG_CENTER_NE4BEG3_15", - "CFG_CENTER_LH7_17", - "CFG_CENTER_LH5_18", - "CFG_CENTER_WL1END0_18", - "CFG_CENTER_LOGIC_OUTS_B0_1", - "CFG_CENTER_NE2A3_13", - "CFG_CENTER_WR1END0_12", - "CFG_CENTER_MID_USR_ACCESS_DATA13", - "CFG_CENTER_EE4B0_14", - "CFG_CENTER_NE4BEG2_9", - "CFG_CENTER_ICAP1_I4", - "CFG_CENTER_FRAME_ECC_SYNDROME4", - "CFG_CENTER_LH7_16", - "CFG_CENTER_FAN7_11", - "CFG_CENTER_LH8_14", - "CFG_CENTER_EE2A1_0", - "CFG_CENTER_LH10_6", - "CFG_CENTER_WW4A1_18", - "CFG_CENTER_LOGIC_OUTS_B13_9", - "CFG_CENTER_IMUX10_12", - "CFG_CENTER_LOGIC_OUTS_B14_10", - "CFG_CENTER_ICAP1_O14", - "CFG_CENTER_WW2A0_19", - "CFG_CENTER_LH5_16", - "CFG_CENTER_LH9_5", - "CFG_CENTER_IMUX38_6", - "CFG_CENTER_NW4END2_17", - "CFG_CENTER_FAN5_1", - "CFG_CENTER_IMUX9_0", - "CFG_CENTER_WW2A1_2", - "CFG_CENTER_IMUX30_4", - "CFG_CENTER_WW2A1_15", - "CFG_CENTER_WW4B3_18", - "CFG_CENTER_NW4END0_8", - "CFG_CENTER_BLOCK_OUTS_B3_16", - "CFG_CENTER_SW4A2_9", - "CFG_CENTER_STARTUP_EOS", - "CFG_CENTER_LOGIC_OUTS_B21_7", - "CFG_CENTER_BYP2_12", - "CFG_CENTER_CTRL0_12", - "CFG_CENTER_IMUX22_18", - "CFG_CENTER_LOGIC_OUTS_B21_13", - "CFG_CENTER_WW4C1_6", - "CFG_CENTER_NW4END1_13", - "CFG_CENTER_IMUX7_0", - "CFG_CENTER_SE4BEG2_6", - "CFG_CENTER_LOGIC_OUTS_B15_17", - "CFG_CENTER_IMUX40_10", - "CFG_CENTER_IMUX6_7", - "CFG_CENTER_IMUX32_2", - "CFG_CENTER_FAN2_16", - "CFG_CENTER_EE2A2_7", - "CFG_CENTER_DCIRESET_LOCKED", - "CFG_CENTER_NE4BEG0_17", - "CFG_CENTER_BLOCK_OUTS_B0_12", - "CFG_CENTER_NW4END2_12", - "CFG_CENTER_ER1BEG3_18", - "CFG_CENTER_IMUX33_4", - "CFG_CENTER_BYP7_6", - "CFG_CENTER_IMUX40_11", - "CFG_CENTER_WW4A2_17", - "CFG_CENTER_WL1END0_6", - "CFG_CENTER_USR_ACCESS_DATA18", - "CFG_CENTER_EE4BEG2_0", - "CFG_CENTER_WR1END0_2", - "CFG_CENTER_FAN1_3", - "CFG_CENTER_CK_BUFHCLK2", - "CFG_CENTER_LH11_14", - "CFG_CENTER_IMUX34_9", - "CFG_CENTER_IMUX15_14", - "CFG_CENTER_WL1END2_7", - "CFG_CENTER_LOGIC_OUTS_B18_0", - "CFG_CENTER_EL1BEG1_10", - "CFG_CENTER_ICAP1_I20", - "CFG_CENTER_IMUX6_9", - "CFG_CENTER_LOGIC_OUTS_B11_13", - "CFG_CENTER_EE2A0_17", - "CFG_CENTER_IMUX47_14", - "CFG_CENTER_IMUX30_9", - "CFG_CENTER_ICAP0_O31", - "CFG_CENTER_SW4A3_1", - "CFG_CENTER_EE4A0_3", - "CFG_CENTER_WW2A0_11", - "CFG_CENTER_SW4A2_6", - "CFG_CENTER_BYP3_0", - "CFG_CENTER_LOGIC_OUTS_B0_16", - "CFG_CENTER_SE4C1_10", - "CFG_CENTER_CFG_IO_ACCESS_VGGCOMPOUT", - "CFG_CENTER_SW2A2_11", - "CFG_CENTER_EE2BEG3_14", - "CFG_CENTER_LOGIC_OUTS_B11_17", - "CFG_CENTER_LOGIC_OUTS_B12_5", - "CFG_CENTER_NE2A1_18", - "CFG_CENTER_LH8_0", - "CFG_CENTER_IMUX22_9", - "CFG_CENTER_IMUX21_19", - "CFG_CENTER_SE4BEG3_7", - "CFG_CENTER_IMUX20_6", - "CFG_CENTER_FAN2_1", - "CFG_CENTER_FRAME_ECC_FAR18", - "CFG_CENTER_WW4A2_4", - "CFG_CENTER_SE4BEG2_9", - "CFG_CENTER_LOGIC_OUTS_B23_9", - "CFG_CENTER_WW4END1_11", - "CFG_CENTER_SE4C2_1", - "CFG_CENTER_EE4B3_8", - "CFG_CENTER_LOGIC_OUTS_B9_1", - "CFG_CENTER_IMUX9_10", - "CFG_CENTER_EE4BEG3_14", - "CFG_CENTER_EE4A1_11", - "CFG_CENTER_IMUX11_8", - "CFG_CENTER_BYP0_3", - "CFG_CENTER_BYP3_8", - "CFG_CENTER_NE4BEG0_18", - "CFG_CENTER_IMUX3_1", - "CFG_CENTER_WW4END2_3", - "CFG_CENTER_SE2A1_19", - "CFG_CENTER_NW4END3_19", - "CFG_CENTER_NE2A3_5", - "CFG_CENTER_WW4B3_2", - "CFG_CENTER_CK_BUFHCLK11", - "CFG_CENTER_SW4END1_8", - "CFG_CENTER_EE4A3_15", - "CFG_CENTER_FRAME_ECC_FAR11", - "CFG_CENTER_ICAP1_I27", - "CFG_CENTER_NW2A2_15", - "CFG_CENTER_LH6_4", - "CFG_CENTER_EE4B1_9", - "CFG_CENTER_IMUX39_12", - "CFG_CENTER_IMUX36_18", - "CFG_CENTER_NE4C1_11", - "CFG_CENTER_EE2A3_12", - "CFG_CENTER_IMUX12_10", - "CFG_CENTER_LOGIC_OUTS_B16_4", - "CFG_CENTER_WL1END1_15", - "CFG_CENTER_LH10_16", - "CFG_CENTER_SE4C0_2", - "CFG_CENTER_WW4A3_3", - "CFG_CENTER_NW4A0_17", - "CFG_CENTER_LH4_16", - "CFG_CENTER_SW2A3_0", - "CFG_CENTER_IMUX5_2", - "CFG_CENTER_EE2A2_8", - "CFG_CENTER_IMUX25_14", - "CFG_CENTER_NE2A2_1", - "CFG_CENTER_EE4A0_2", - "CFG_CENTER_NW4A2_18", - "CFG_CENTER_LH12_2", - "CFG_CENTER_IMUX22_1", - "CFG_CENTER_IMUX39_15", - "CFG_CENTER_CFG_IO_ACCESS_TDO", - "CFG_CENTER_WW2END2_2", - "CFG_CENTER_SE2A2_7", - "CFG_CENTER_IMUX47_19", - "CFG_CENTER_EE4B3_5", - "CFG_CENTER_NE4BEG3_16", - "CFG_CENTER_NE4BEG2_5", - "CFG_CENTER_IMUX38_4", - "CFG_CENTER_WW2END2_19", - "CFG_CENTER_IMUX42_1", - "CFG_CENTER_LOGIC_OUTS_B20_18", - "CFG_CENTER_LOGIC_OUTS_B9_13", - "CFG_CENTER_SE4BEG2_11", - "CFG_CENTER_EE4B0_7", - "CFG_CENTER_IMUX15_15", - "CFG_CENTER_IMUX35_9", - "CFG_CENTER_IMUX11_11", - "CFG_CENTER_EE2A2_14", - "CFG_CENTER_BYP5_4", - "CFG_CENTER_WW4B1_2", - "CFG_CENTER_WW4C3_18", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_CLK1_5", - "CFG_CENTER_IMUX35_15", - "CFG_CENTER_IMUX24_7", - "CFG_CENTER_STARTUP_PACK", - "CFG_CENTER_LOGIC_OUTS_B17_7", - "CFG_CENTER_IMUX17_18", - "CFG_CENTER_WW4A1_19", - "CFG_CENTER_EE2BEG0_9", - "CFG_CENTER_LOGIC_OUTS_B9_16", - "CFG_CENTER_IMUX45_19", - "CFG_CENTER_WR1END1_11", - "CFG_CENTER_WW4A1_15", - "CFG_CENTER_EE2BEG1_16", - "CFG_CENTER_NW4END0_6", - "CFG_CENTER_LOGIC_OUTS_B17_11", - "CFG_CENTER_NE4C3_8", - "CFG_CENTER_NE4BEG0_15", - "CFG_CENTER_ER1BEG3_16", - "CFG_CENTER_WW4A2_3", - "CFG_CENTER_IMUX15_4", - "CFG_CENTER_IMUX16_10", - "CFG_CENTER_WW4B3_14", - "CFG_CENTER_LOGIC_OUTS_B8_15", - "CFG_CENTER_IMUX7_8", - "CFG_CENTER_NE4BEG3_14", - "CFG_CENTER_NE4C0_10", - "CFG_CENTER_IMUX1_17", - "CFG_CENTER_CLK0_5", - "CFG_CENTER_IMUX34_15", - "CFG_CENTER_SE4BEG1_17", - "CFG_CENTER_BLOCK_OUTS_B3_8", - "CFG_CENTER_NW2A0_7", - "CFG_CENTER_WW4A0_10", - "CFG_CENTER_IMUX14_3", - "CFG_CENTER_NW4A1_10", - "CFG_CENTER_EE4C2_10", - "CFG_CENTER_NE2A0_17", - "CFG_CENTER_EE2BEG2_10", - "CFG_CENTER_IMUX38_5", - "CFG_CENTER_LH6_17", - "CFG_CENTER_WW4A2_8", - "CFG_CENTER_NW2A0_2", - "CFG_CENTER_SE2A1_8", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_FAN3_7", - "CFG_CENTER_BSCAN4_SEL", - "CFG_CENTER_IMUX34_10", - "CFG_CENTER_NE4BEG1_4", - "CFG_CENTER_LOGIC_OUTS_B16_10", - "CFG_CENTER_SE4BEG2_18", - "CFG_CENTER_ER1BEG0_10", - "CFG_CENTER_WW2END3_6", - "CFG_CENTER_EL1BEG3_14", - "CFG_CENTER_IMUX45_15", - "CFG_CENTER_EE2BEG0_10", - "CFG_CENTER_SW2A3_18", - "CFG_CENTER_WW4C3_5", - "CFG_CENTER_SE4BEG0_17", - "CFG_CENTER_IMUX15_2", - "CFG_CENTER_WW4B3_11", - "CFG_CENTER_IMUX42_18", - "CFG_CENTER_FRAME_ECC_CRCERROR", - "CFG_CENTER_NW4END0_12", - "CFG_CENTER_SW2A0_15", - "CFG_CENTER_BYP1_2", - "CFG_CENTER_IMUX38_10", - "CFG_CENTER_IMUX31_18", - "CFG_CENTER_ER1BEG0_16", - "CFG_CENTER_BYP7_3", - "CFG_CENTER_WW2A0_1", - "CFG_CENTER_LOGIC_OUTS_B9_0", - "CFG_CENTER_SE4C2_4", - "CFG_CENTER_NE4C0_12", - "CFG_CENTER_WW2A2_7", - "CFG_CENTER_SW2A1_9", - "CFG_CENTER_WL1END1_0", - "CFG_CENTER_NW4END2_16", - "CFG_CENTER_IMUX7_4", - "CFG_CENTER_SW4END3_4", - "CFG_CENTER_LOGIC_OUTS_B15_7", - "CFG_CENTER_BYP2_17", - "CFG_CENTER_BLOCK_OUTS_B2_5", - "CFG_CENTER_LH8_12", - "CFG_CENTER_WR1END0_5", - "CFG_CENTER_WL1END0_17", - "CFG_CENTER_EE4C3_5", - "CFG_CENTER_IMUX36_16", - "CFG_CENTER_BYP3_13", - "CFG_CENTER_FRAME_ECC_SYNWORD3", - "CFG_CENTER_BYP0_1", - "CFG_CENTER_EE4C2_15", - "CFG_CENTER_IMUX3_11", - "CFG_CENTER_CLK0_9", - "CFG_CENTER_MID_USR_ACCESS_DATA12", - "CFG_CENTER_IMUX10_4", - "CFG_CENTER_IMUX30_7", - "CFG_CENTER_IMUX23_7", - "CFG_CENTER_IMUX0_3", - "CFG_CENTER_IMUX36_0", - "CFG_CENTER_IMUX43_19", - "CFG_CENTER_EE4A3_5", - "CFG_CENTER_CLK0_18", - "CFG_CENTER_IMUX27_7", - "CFG_CENTER_LH12_11", - "CFG_CENTER_LH10_19", - "CFG_CENTER_EE4A3_12", - "CFG_CENTER_BYP0_14", - "CFG_CENTER_IMUX1_0", - "CFG_CENTER_LOGIC_OUTS_B7_15", - "CFG_CENTER_WW2A0_10", - "CFG_CENTER_EE4BEG2_16", - "CFG_CENTER_EE4A0_11", - "CFG_CENTER_IMUX12_8", - "CFG_CENTER_IMUX41_0", - "CFG_CENTER_BYP5_6", - "CFG_CENTER_IMUX11_15", - "CFG_CENTER_IMUX4_13", - "CFG_CENTER_EE4C2_3", - "CFG_CENTER_SW2A2_8", - "CFG_CENTER_IMUX11_14", - "CFG_CENTER_IMUX15_16", - "CFG_CENTER_LH1_15", - "CFG_CENTER_WR1END3_9", - "CFG_CENTER_USR_ACCESS_DATA4", - "CFG_CENTER_WL1END2_14", - "CFG_CENTER_LOGIC_OUTS_B15_11", - "CFG_CENTER_SW4END1_18", - "CFG_CENTER_FRAME_ECC_SYNDROME10", - "CFG_CENTER_NW4A0_8", - "CFG_CENTER_NE4C1_10", - "CFG_CENTER_IMUX22_2", - "CFG_CENTER_BYP3_1", - "CFG_CENTER_WW2END1_18", - "CFG_CENTER_BLOCK_OUTS_B3_0", - "CFG_CENTER_WW2A3_9", - "CFG_CENTER_LOGIC_OUTS_B0_13", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_LOGIC_OUTS_B5_3", - "CFG_CENTER_LH8_7", - "CFG_CENTER_WW2A2_18", - "CFG_CENTER_WW4C2_12", - "CFG_CENTER_LH6_1", - "CFG_CENTER_WW4END3_18", - "CFG_CENTER_IMUX29_7", - "CFG_CENTER_NE2A1_4", - "CFG_CENTER_LH10_1", - "CFG_CENTER_IMUX2_1", - "CFG_CENTER_IMUX28_18", - "CFG_CENTER_NE2A0_18", - "CFG_CENTER_SE4C1_6", - "CFG_CENTER_LOGIC_OUTS_B18_11", - "CFG_CENTER_WW4END0_7", - "CFG_CENTER_BSCAN2_RUNTEST", - "CFG_CENTER_CTRL0_18", - "CFG_CENTER_WW2A3_4", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_BYP6_5", - "CFG_CENTER_LH3_13", - "CFG_CENTER_IMUX43_16", - "CFG_CENTER_SW2A0_9", - "CFG_CENTER_IMUX12_5", - "CFG_CENTER_WW4C1_19", - "CFG_CENTER_LH4_0", - "CFG_CENTER_EE2A3_0", - "CFG_CENTER_BYP1_12", - "CFG_CENTER_EL1BEG1_3", "CFG_CENTER_EE4A1_16", - "CFG_CENTER_LOGIC_OUTS_B7_12", - "CFG_CENTER_IMUX34_0", - "CFG_CENTER_ICAP0_I3", - "CFG_CENTER_IMUX38_2", - "CFG_CENTER_SW4END2_14", - "CFG_CENTER_LH12_19", - "CFG_CENTER_IMUX7_1", - "CFG_CENTER_NE4C0_6", - "CFG_CENTER_NW4END1_5", - "CFG_CENTER_EE4A3_16", - "CFG_CENTER_SW2A0_13", - "CFG_CENTER_IMUX19_19", - "CFG_CENTER_WR1END2_4", - "CFG_CENTER_IMUX16_6", - "CFG_CENTER_IMUX24_0", - "CFG_CENTER_WL1END0_8", - "CFG_CENTER_BLOCK_OUTS_B2_10", - "CFG_CENTER_LH1_16", - "CFG_CENTER_IMUX16_13", - "CFG_CENTER_IMUX44_4", - "CFG_CENTER_WL1END2_8", - "CFG_CENTER_SE4BEG1_18", - "CFG_CENTER_USR_ACCESS_DATA27", - "CFG_CENTER_EL1BEG2_6", - "CFG_CENTER_MID_USR_ACCESS_DATA2", - "CFG_CENTER_USR_ACCESS_DATA1", - "CFG_CENTER_EE2A3_15", - "CFG_CENTER_IMUX23_11", - "CFG_CENTER_SE2A0_1", - "CFG_CENTER_IMUX31_6", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_SE4BEG0_3", - "CFG_CENTER_ER1BEG0_5", - "CFG_CENTER_EE2BEG3_10", - "CFG_CENTER_IMUX1_9", - "CFG_CENTER_LOGIC_OUTS_B8_5", - "CFG_CENTER_WR1END0_11", - "CFG_CENTER_NE4BEG0_8", - "CFG_CENTER_IMUX7_14", - "CFG_CENTER_LH7_6", - "CFG_CENTER_LH8_2", - "CFG_CENTER_ER1BEG1_11", - "CFG_CENTER_WW4C3_9", - "CFG_CENTER_WW2END2_6", - "CFG_CENTER_NW4END2_5", - "CFG_CENTER_WL1END3_3", - "CFG_CENTER_EE4A0_17", - "CFG_CENTER_CK_IN13", - "CFG_CENTER_WW2END0_7", - "CFG_CENTER_NW4END0_15", - "CFG_CENTER_CTRL0_9", - "CFG_CENTER_NW4A3_18", - "CFG_CENTER_IMUX20_4", - "CFG_CENTER_EL1BEG3_18", - "CFG_CENTER_LOGIC_OUTS_B7_10", - "CFG_CENTER_LOGIC_OUTS_B20_8", - "CFG_CENTER_FRAME_ECC_FAR15", - "CFG_CENTER_IMUX27_8", - "CFG_CENTER_NE2A1_12", - "CFG_CENTER_ICAP0_O30", + "CFG_CENTER_FAN2_8", "CFG_CENTER_IMUX14_7", - "CFG_CENTER_CLK0_8", - "CFG_CENTER_BLOCK_OUTS_B3_4", - "CFG_CENTER_EE4C3_0", - "CFG_CENTER_LOGIC_OUTS_B17_9", - "CFG_CENTER_STARTUP_USRCCLKO", - "CFG_CENTER_WW4B0_18", - "CFG_CENTER_NE4C0_9", - "CFG_CENTER_NW2A0_1", - "CFG_CENTER_LH6_8", - "CFG_CENTER_NE4C1_3", - "CFG_CENTER_IMUX45_12", - "CFG_CENTER_IMUX1_14", - "CFG_CENTER_BLOCK_OUTS_B2_12", - "CFG_CENTER_LOGIC_OUTS_B9_18", - "CFG_CENTER_BYP2_4", - "CFG_CENTER_NE2A3_6", - "CFG_CENTER_SE4C1_0", - "CFG_CENTER_EE4A2_15", - "CFG_CENTER_LH6_6", - "CFG_CENTER_NW2A1_11", - "CFG_CENTER_LOGIC_OUTS_B10_8", - "CFG_CENTER_WL1END2_13", - "CFG_CENTER_BYP7_17", - "CFG_CENTER_CLK1_2", - "CFG_CENTER_IMUX33_8", - "CFG_CENTER_IMUX30_3", - "CFG_CENTER_LOGIC_OUTS_B12_14", - "CFG_CENTER_EE4BEG1_16", - "CFG_CENTER_IMUX28_2", - "CFG_CENTER_NW4A2_6", - "CFG_CENTER_LOGIC_OUTS_B16_14", - "CFG_CENTER_WL1END2_3", - "CFG_CENTER_IMUX15_19", - "CFG_CENTER_IMUX19_8", - "CFG_CENTER_LH5_2", - "CFG_CENTER_WW4END1_9", - "CFG_CENTER_LOGIC_OUTS_B1_6", - "CFG_CENTER_EE4A1_17", - "CFG_CENTER_IMUX40_4", - "CFG_CENTER_LOGIC_OUTS_B8_2", - "CFG_CENTER_WW2A2_9", - "CFG_CENTER_ICAP1_O19", - "CFG_CENTER_NW4A2_7", - "CFG_CENTER_NE4BEG1_18", - "CFG_CENTER_IMUX4_4", - "CFG_CENTER_FAN4_19", - "CFG_CENTER_WR1END0_13", - "CFG_CENTER_NE4BEG0_2", - "CFG_CENTER_LOGIC_OUTS_B21_17", - "CFG_CENTER_SE4BEG2_5", - "CFG_CENTER_LH1_5", - "CFG_CENTER_NW2A1_4", - "CFG_CENTER_IMUX42_2", - "CFG_CENTER_EE4B2_10", - "CFG_CENTER_SW4END3_17", - "CFG_CENTER_LH1_4", - "CFG_CENTER_IMUX6_16", - "CFG_CENTER_LOGIC_OUTS_B15_19", + "CFG_CENTER_NW4A0_2", + "CFG_CENTER_IMUX8_17", + "CFG_CENTER_FAN6_15", + "CFG_CENTER_FAN3_16", + "CFG_CENTER_LOGIC_OUTS_B5_13", + "CFG_CENTER_NE4C0_3", + "CFG_CENTER_EE4B2_0", + "CFG_CENTER_IMUX17_11", + "CFG_CENTER_NW4A3_0", + "CFG_CENTER_IMUX12_5", + "CFG_CENTER_LOGIC_OUTS_B22_0", + "CFG_CENTER_WR1END1_6", + "CFG_CENTER_ER1BEG3_5", + "CFG_CENTER_FAN3_17", + "CFG_CENTER_EE4A3_9", + "CFG_CENTER_IMUX18_6", + "CFG_CENTER_IMUX34_5", + "CFG_CENTER_NE4BEG3_9", + "CFG_CENTER_IMUX37_19", + "CFG_CENTER_EE2BEG2_14", + "CFG_CENTER_LH5_14", + "CFG_CENTER_BSCAN3_TCK", + "CFG_CENTER_SW4END3_4", + "CFG_CENTER_EE4A3_16", + "CFG_CENTER_NE2A1_9", + "CFG_CENTER_WR1END2_4", + "CFG_CENTER_SW4A3_17", "CFG_CENTER_IMUX13_0", - "CFG_CENTER_IMUX40_19", - "CFG_CENTER_WW4B2_6", - "CFG_CENTER_FAN5_9", - "CFG_CENTER_IMUX25_3", - "CFG_CENTER_SE4BEG3_3", - "CFG_CENTER_WW2A0_18", - "CFG_CENTER_NE4BEG3_12", - "CFG_CENTER_SW4A1_1", - "CFG_CENTER_FAN0_9", - "CFG_CENTER_WW4A3_6", - "CFG_CENTER_IMUX23_6", - "CFG_CENTER_BSCAN2_TDI", - "CFG_CENTER_EE4B3_19", - "CFG_CENTER_LOGIC_OUTS_B14_14", - "CFG_CENTER_FAN1_8", - "CFG_CENTER_NW4A2_1", - "CFG_CENTER_CK_IN6", - "CFG_CENTER_SE4C2_10", - "CFG_CENTER_LH1_9", + "CFG_CENTER_SW4END0_16", + "CFG_CENTER_WR1END1_11", + "CFG_CENTER_EE2A3_14", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA31", + "CFG_CENTER_EE2BEG0_1", + "CFG_CENTER_IMUX1_1", + "CFG_CENTER_EE4A0_16", + "CFG_CENTER_WR1END0_0", + "CFG_CENTER_USR_ACCESS_DATA2", + "CFG_CENTER_IMUX34_13", + "CFG_CENTER_FAN5_14", + "CFG_CENTER_SW2A0_19", + "CFG_CENTER_CLK1_5", + "CFG_CENTER_WW2END2_8", + "CFG_CENTER_SE4BEG2_5", + "CFG_CENTER_WW2A2_14", + "CFG_CENTER_EE4A2_14", + "CFG_CENTER_NW4END2_6", + "CFG_CENTER_IMUX45_18", + "CFG_CENTER_FAN2_16", + "CFG_CENTER_ER1BEG3_12", + "CFG_CENTER_EE4BEG0_6", + "CFG_CENTER_NE4BEG2_19", + "CFG_CENTER_WW4C0_6", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA26", + "CFG_CENTER_FAN2_11", + "CFG_CENTER_FRAME_ECC_SYNWORD4", + "CFG_CENTER_ER1BEG1_16", + "CFG_CENTER_SE4BEG2_17", + "CFG_CENTER_ER1BEG1_18", + "CFG_CENTER_NE4C0_14", + "CFG_CENTER_ICAP1_I3", + "CFG_CENTER_CTRL1_0", + "CFG_CENTER_ER1BEG2_8", + "CFG_CENTER_WR1END0_18", + "CFG_CENTER_EE2BEG1_0", "CFG_CENTER_IMUX41_3", - "CFG_CENTER_IMUX44_3", - "CFG_CENTER_WW4C1_8", - "CFG_CENTER_NW4END1_6", - "CFG_CENTER_IMUX13_1", - "CFG_CENTER_WW4B2_12", - "CFG_CENTER_SE4C0_5", - "CFG_CENTER_IMUX20_8", - "CFG_CENTER_LOGIC_OUTS_B6_9", - "CFG_CENTER_SE4C3_11", - "CFG_CENTER_IMUX31_5", - "CFG_CENTER_NE2A3_9", - "CFG_CENTER_SE2A3_11", - "CFG_CENTER_LH2_18", - "CFG_CENTER_BYP3_2", - "CFG_CENTER_USR_ACCESS_DATAVALID", - "CFG_CENTER_LOGIC_OUTS_B5_8", - "CFG_CENTER_BSCAN1_UPDATE", - "CFG_CENTER_NE4C0_0", - "CFG_CENTER_LOGIC_OUTS_B17_14", - "CFG_CENTER_SE4BEG1_12", - "CFG_CENTER_IMUX46_3", - "CFG_CENTER_LH8_3", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_ICAP0_O2", - "CFG_CENTER_LOGIC_OUTS_B16_7", - "CFG_CENTER_FAN2_3", - "CFG_CENTER_LH11_7", - "CFG_CENTER_WR1END1_8", - "CFG_CENTER_BYP4_6", - "CFG_CENTER_EE4BEG1_2", - "CFG_CENTER_WR1END3_16", - "CFG_CENTER_SW4A2_12", - "CFG_CENTER_LOGIC_OUTS_B6_18", - "CFG_CENTER_BYP7_0", - "CFG_CENTER_IMUX11_0", - "CFG_CENTER_NE4BEG2_12", - "CFG_CENTER_BYP3_9", - "CFG_CENTER_SE4C3_7", + "CFG_CENTER_LH11_0", + "CFG_CENTER_IMUX36_14", + "CFG_CENTER_SE4C3_4", + "CFG_CENTER_WW2END0_5", + "CFG_CENTER_IMUX6_1", + "CFG_CENTER_WW2END3_7", + "CFG_CENTER_SE4C0_1", + "CFG_CENTER_WR1END3_0", + "CFG_CENTER_WW4END2_15", + "CFG_CENTER_NE2A1_18", + "CFG_CENTER_WW4C1_12", + "CFG_CENTER_BLOCK_OUTS_B1_11", + "CFG_CENTER_NW2A1_10", "CFG_CENTER_WW2A3_14", - "CFG_CENTER_SW4A1_3", - "CFG_CENTER_IMUX42_5", - "CFG_CENTER_WW4A3_14", - "CFG_CENTER_LOGIC_OUTS_B12_6", - "CFG_CENTER_SE4BEG2_16", - "CFG_CENTER_IMUX24_13", - "CFG_CENTER_FAN6_5", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_SE2A0_15", + "CFG_CENTER_IMUX45_17", + "CFG_CENTER_NW4END1_7", + "CFG_CENTER_IMUX0_7", + "CFG_CENTER_WW4A2_3", + "CFG_CENTER_EE4B0_2", + "CFG_CENTER_SW4END2_14", + "CFG_CENTER_IMUX39_10", + "CFG_CENTER_LOGIC_OUTS_B0_17", + "CFG_CENTER_EE4C1_16", + "CFG_CENTER_LH7_6", + "CFG_CENTER_EE4B3_16", + "CFG_CENTER_FAN0_9", + "CFG_CENTER_BYP2_11", + "CFG_CENTER_IMUX15_15", + "CFG_CENTER_NE4C1_14", + "CFG_CENTER_EE2A0_1", + "CFG_CENTER_BYP3_5", + "CFG_CENTER_CTRL0_18", + "CFG_CENTER_WW4B2_5", + "CFG_CENTER_LH8_1", + "CFG_CENTER_EE4B3_15", + "CFG_CENTER_BYP5_12", + "CFG_CENTER_IMUX43_18", + "CFG_CENTER_NW4A3_16", + "CFG_CENTER_BLOCK_OUTS_B3_3", + "CFG_CENTER_EE4BEG0_5", + "CFG_CENTER_LOGIC_OUTS_B4_2", + "CFG_CENTER_WW2A0_12", + "CFG_CENTER_WL1END0_18", + "CFG_CENTER_LH11_19", + "CFG_CENTER_IMUX32_13", + "CFG_CENTER_BYP3_0", + "CFG_CENTER_IMUX31_8", + "CFG_CENTER_LOGIC_OUTS_B11_13", + "CFG_CENTER_IMUX46_17", + "CFG_CENTER_CTRL0_13", + "CFG_CENTER_LOGIC_OUTS_B22_18", + "CFG_CENTER_LOGIC_OUTS_B18_5", + "CFG_CENTER_SW4END2_1", + "CFG_CENTER_LH6_0", + "CFG_CENTER_EL1BEG0_11", + "CFG_CENTER_EE4A3_10", + "CFG_CENTER_LOGIC_OUTS_B10_16", + "CFG_CENTER_WW4A2_11", + "CFG_CENTER_FRAME_ECC_FAR16", + "CFG_CENTER_WW4A2_17", + "CFG_CENTER_WL1END0_15", + "CFG_CENTER_NW2A0_10", + "CFG_CENTER_WW2END1_17", + "CFG_CENTER_FAN0_17", + "CFG_CENTER_LH10_10", + "CFG_CENTER_NE4C1_2", + "CFG_CENTER_ER1BEG0_9", + "CFG_CENTER_IMUX14_19", + "CFG_CENTER_SW2A1_11", + "CFG_CENTER_EE4C3_2", + "CFG_CENTER_WW2END0_2", + "CFG_CENTER_NE2A2_14", + "CFG_CENTER_WW4END0_7", + "CFG_CENTER_SE4C2_17", + "CFG_CENTER_NE2A1_16", + "CFG_CENTER_SE4BEG1_1", + "CFG_CENTER_SW4END0_9", + "CFG_CENTER_LH11_15", + "CFG_CENTER_WR1END1_4", + "CFG_CENTER_LH10_19", + "CFG_CENTER_WR1END3_15", + "CFG_CENTER_NW4END1_1", + "CFG_CENTER_SE2A3_19", + "CFG_CENTER_SE4C3_6", + "CFG_CENTER_ICAP0_O2", + "CFG_CENTER_BYP6_17", + "CFG_CENTER_NE2A0_14", + "CFG_CENTER_BYP5_16", + "CFG_CENTER_LH6_5", + "CFG_CENTER_LH6_4", "CFG_CENTER_WW4B2_4", - "CFG_CENTER_NE2A2_13", - "CFG_CENTER_EE4B3_10", - "CFG_CENTER_LOGIC_OUTS_B2_14", - "CFG_CENTER_NE4C1_15", - "CFG_CENTER_SE4C3_8", - "CFG_CENTER_BYP0_18", - "CFG_CENTER_IMUX37_4", - "CFG_CENTER_LOGIC_OUTS_B17_15", - "CFG_CENTER_NW2A3_9", - "CFG_CENTER_CFG_IO_ACCESS_MODE0", - "CFG_CENTER_IMUX16_16", - "CFG_CENTER_WW4C1_7", - "CFG_CENTER_LOGIC_OUTS_B14_6", - "CFG_CENTER_LOGIC_OUTS_B13_1", - "CFG_CENTER_WL1END0_10", - "CFG_CENTER_IMUX30_13", - "CFG_CENTER_EL1BEG1_8", - "CFG_CENTER_WW2A1_8", - "CFG_CENTER_IMUX34_4", - "CFG_CENTER_IMUX11_12", - "CFG_CENTER_WW2A2_16", - "CFG_CENTER_EL1BEG2_0", + "CFG_CENTER_BYP1_0", + "CFG_CENTER_LH5_10", + "CFG_CENTER_WW4END0_12", + "CFG_CENTER_EE4A1_2", "CFG_CENTER_LH10_18", - "CFG_CENTER_SE4C1_4", - "CFG_CENTER_IMUX43_7", - "CFG_CENTER_WW4A1_11", - "CFG_CENTER_WR1END2_3", - "CFG_CENTER_EE4A2_16", - "CFG_CENTER_IMUX26_2", - "CFG_CENTER_ER1BEG1_12", - "CFG_CENTER_IMUX6_13", - "CFG_CENTER_LH3_15", - "CFG_CENTER_BYP1_6", - "CFG_CENTER_FAN2_4", - "CFG_CENTER_LH11_8", - "CFG_CENTER_NW4END1_15", - "CFG_CENTER_LOGIC_OUTS_B11_18", - "CFG_CENTER_WW2END1_13", - "CFG_CENTER_LH4_4", - "CFG_CENTER_LOGIC_OUTS_B1_15", - "CFG_CENTER_LOGIC_OUTS_B1_5", - "CFG_CENTER_LOGIC_OUTS_B14_11", - "CFG_CENTER_LOGIC_OUTS_B7_16", - "CFG_CENTER_BYP1_3", - "CFG_CENTER_LOGIC_OUTS_B14_19", - "CFG_CENTER_NE4C3_7", - "CFG_CENTER_EE4BEG1_9", - "CFG_CENTER_FAN1_0", - "CFG_CENTER_DCIRESET_RST", - "CFG_CENTER_SE2A1_0", - "CFG_CENTER_EE4C2_6", - "CFG_CENTER_BYP4_9", - "CFG_CENTER_LOGIC_OUTS_B15_6", - "CFG_CENTER_IMUX6_17", - "CFG_CENTER_FAN6_10", - "CFG_CENTER_WW2END3_10", - "CFG_CENTER_EE4A3_6", + "CFG_CENTER_WW4END2_6", + "CFG_CENTER_NE4BEG2_12", + "CFG_CENTER_WL1END2_2", + "CFG_CENTER_IMUX5_3", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA4", + "CFG_CENTER_LOGIC_OUTS_B20_11", + "CFG_CENTER_EE4C1_18", + "CFG_CENTER_SW4A1_0", + "CFG_CENTER_LH9_14", + "CFG_CENTER_WW4A1_8", + "CFG_CENTER_SE4C3_19", + "CFG_CENTER_LH8_5", + "CFG_CENTER_IMUX37_1", + "CFG_CENTER_LH2_4", + "CFG_CENTER_IMUX42_12", + "CFG_CENTER_IMUX28_19", + "CFG_CENTER_EE4A1_13", + "CFG_CENTER_WW4A1_15", + "CFG_CENTER_IMUX40_5", + "CFG_CENTER_WW4END0_0", + "CFG_CENTER_IMUX9_13", + "CFG_CENTER_CLK1_2", + "CFG_CENTER_WW4B3_10", + "CFG_CENTER_NE4BEG1_11", + "CFG_CENTER_LH7_16", + "CFG_CENTER_IMUX36_16", + "CFG_CENTER_BLOCK_OUTS_B0_9", + "CFG_CENTER_MID_DNA_PORT_CLK", + "CFG_CENTER_ICAP0_I15", + "CFG_CENTER_IMUX6_7", + "CFG_CENTER_IMUX20_5", + "CFG_CENTER_WW2END2_17", + "CFG_CENTER_WL1END2_3", + "CFG_CENTER_FAN4_10", + "CFG_CENTER_NW4A3_10", + "CFG_CENTER_LH4_6", + "CFG_CENTER_WL1END2_7", + "CFG_CENTER_LOGIC_OUTS_B10_19", + "CFG_CENTER_LOGIC_OUTS_B10_10", + "CFG_CENTER_SW2A0_3", + "CFG_CENTER_LH8_7", + "CFG_CENTER_IMUX32_0", + "CFG_CENTER_LOGIC_OUTS_B0_5", + "CFG_CENTER_BYP4_16", "CFG_CENTER_WW2A1_19", - "CFG_CENTER_EE4BEG3_6", - "CFG_CENTER_WR1END2_8", - "CFG_CENTER_BLOCK_OUTS_B2_2", - "CFG_CENTER_NW4A2_11", - "CFG_CENTER_CTRL1_3", - "CFG_CENTER_SE4BEG1_0", - "CFG_CENTER_CLK1_10", - "CFG_CENTER_LH11_13", - "CFG_CENTER_NW4END3_15", - "CFG_CENTER_BLOCK_OUTS_B0_10", - "CFG_CENTER_LH7_18", + "CFG_CENTER_SE4C3_1", + "CFG_CENTER_IMUX5_18", + "CFG_CENTER_LOGIC_OUTS_B19_18", + "CFG_CENTER_BYP5_1", + "CFG_CENTER_EE4B1_11", + "CFG_CENTER_LOGIC_OUTS_B18_14", + "CFG_CENTER_LOGIC_OUTS_B2_12", + "CFG_CENTER_WW4B2_9", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA5", + "CFG_CENTER_LH3_6", + "CFG_CENTER_LOGIC_OUTS_B6_0", + "CFG_CENTER_IMUX41_17", + "CFG_CENTER_EE2A2_12", + "CFG_CENTER_EE4A0_7", + "CFG_CENTER_IMUX13_17", + "CFG_CENTER_SE4BEG1_14", + "CFG_CENTER_WW4END1_3", + "CFG_CENTER_SW4A3_3", + "CFG_CENTER_IMUX34_1", + "CFG_CENTER_ER1BEG2_1", + "CFG_CENTER_IMUX39_8", + "CFG_CENTER_EE2BEG0_6", + "CFG_CENTER_LH3_8", + "CFG_CENTER_ICAP1_I11", + "CFG_CENTER_WW2END0_15", + "CFG_CENTER_EE2A1_0", + "CFG_CENTER_IMUX17_0", + "CFG_CENTER_LOGIC_OUTS_B5_12", + "CFG_CENTER_WL1END2_0", + "CFG_CENTER_NW4END2_4", + "CFG_CENTER_IMUX29_12", + "CFG_CENTER_ER1BEG2_14", + "CFG_CENTER_SW4A3_4", + "CFG_CENTER_WW2A2_8", + "CFG_CENTER_EE4A2_6", + "CFG_CENTER_STARTUP_GTS", + "CFG_CENTER_FAN0_12", + "CFG_CENTER_LOGIC_OUTS_B5_0", + "CFG_CENTER_EE2BEG0_11", + "CFG_CENTER_IMUX41_9", + "CFG_CENTER_IMUX22_14", + "CFG_CENTER_SW2A2_13", + "CFG_CENTER_ICAP0_O19", + "CFG_CENTER_IMUX12_2", + "CFG_CENTER_IMUX30_6", + "CFG_CENTER_IMUX19_13", + "CFG_CENTER_LH8_10", + "CFG_CENTER_NW2A0_17", + "CFG_CENTER_EL1BEG2_4", + "CFG_CENTER_WW2A2_5", + "CFG_CENTER_WW2A3_9", + "CFG_CENTER_IMUX35_3", + "CFG_CENTER_IMUX29_0", + "CFG_CENTER_SW4A1_7", + "CFG_CENTER_LOGIC_OUTS_B9_2", + "CFG_CENTER_IMUX3_12", + "CFG_CENTER_EE4A2_11", + "CFG_CENTER_EE2BEG1_1", + "CFG_CENTER_SE4C3_8", + "CFG_CENTER_LH1_7", + "CFG_CENTER_WW4C1_11", + "CFG_CENTER_SW2A0_12", + "CFG_CENTER_SE4C2_18", + "CFG_CENTER_LOGIC_OUTS_B15_8", + "CFG_CENTER_IMUX11_9", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA27", + "CFG_CENTER_IMUX19_19", + "CFG_CENTER_BYP5_19", + "CFG_CENTER_BLOCK_OUTS_B1_10", + "CFG_CENTER_LOGIC_OUTS_B19_3", + "CFG_CENTER_NE4C1_15", + "CFG_CENTER_LOGIC_OUTS_B2_14", + "CFG_CENTER_SE4C0_19", + "CFG_CENTER_SE2A3_4", + "CFG_CENTER_IMUX29_11", + "CFG_CENTER_EE4BEG2_1", + "CFG_CENTER_SW2A2_12", + "CFG_CENTER_SE4C0_3", + "CFG_CENTER_EE2A3_16", + "CFG_CENTER_IMUX6_10", + "CFG_CENTER_BYP6_11", + "CFG_CENTER_IMUX36_11", + "CFG_CENTER_NW4END1_9", + "CFG_CENTER_SW4A0_9", + "CFG_CENTER_NW4END2_19", + "CFG_CENTER_EE4C3_13", + "CFG_CENTER_EE4C0_19", + "CFG_CENTER_SE4C2_7", + "CFG_CENTER_SW4END2_10", + "CFG_CENTER_WW4C0_9", + "CFG_CENTER_WW4B0_11", + "CFG_CENTER_EE2BEG3_3", + "CFG_CENTER_CFG_IO_ACCESS_PUDCB", + "CFG_CENTER_LOGIC_OUTS_B7_16", + "CFG_CENTER_BSCAN3_RESET", + "CFG_CENTER_WW4B0_15", + "CFG_CENTER_SE4C0_12", + "CFG_CENTER_FAN7_0", + "CFG_CENTER_WW4A3_9", + "CFG_CENTER_WW4C1_1", + "CFG_CENTER_FAN3_19", + "CFG_CENTER_WW4C2_1", + "CFG_CENTER_LOGIC_OUTS_B19_15", + "CFG_CENTER_SE2A1_15", + "CFG_CENTER_LOGIC_OUTS_B9_8", + "CFG_CENTER_WR1END3_11", + "CFG_CENTER_FAN2_4", + "CFG_CENTER_FAN5_5", + "CFG_CENTER_NE2A3_7", + "CFG_CENTER_EE4C3_7", + "CFG_CENTER_IMUX1_2", + "CFG_CENTER_IMUX6_2", + "CFG_CENTER_EE2A0_14", + "CFG_CENTER_EE4C3_11", + "CFG_CENTER_NE2A0_5", + "CFG_CENTER_SE4BEG0_5", + "CFG_CENTER_EE4C1_6", + "CFG_CENTER_FAN7_5", + "CFG_CENTER_BLOCK_OUTS_B1_9", + "CFG_CENTER_CTRL1_18", + "CFG_CENTER_EE2A0_2", + "CFG_CENTER_IMUX15_2", + "CFG_CENTER_NE2A1_14", + "CFG_CENTER_NE4C3_11", + "CFG_CENTER_FAN7_6", + "CFG_CENTER_IMUX39_19", + "CFG_CENTER_EE4B1_7", + "CFG_CENTER_CLK0_11", + "CFG_CENTER_LOGIC_OUTS_B15_17", + "CFG_CENTER_CK_BUFHCLK1", + "CFG_CENTER_NE2A3_16", + "CFG_CENTER_LOGIC_OUTS_B22_7", + "CFG_CENTER_EE4C3_14", + "CFG_CENTER_ICAP1_I27", + "CFG_CENTER_WL1END3_0", + "CFG_CENTER_WW2END2_10", + "CFG_CENTER_WW4B3_15", + "CFG_CENTER_CTRL1_14", + "CFG_CENTER_ICAP1_I30", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA28", + "CFG_CENTER_LOGIC_OUTS_B7_15", + "CFG_CENTER_WL1END1_18", + "CFG_CENTER_NE2A1_4", + "CFG_CENTER_ICAP1_O10", + "CFG_CENTER_MID_USR_ACCESS_DATA9", + "CFG_CENTER_WR1END3_16", + "CFG_CENTER_IMUX46_7", + "CFG_CENTER_IMUX19_17", + "CFG_CENTER_WL1END2_17", + "CFG_CENTER_IMUX47_7", + "CFG_CENTER_CTRL1_12", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA7", + "CFG_CENTER_ICAP0_I0", + "CFG_CENTER_NE2A3_19", + "CFG_CENTER_EL1BEG2_14", + "CFG_CENTER_SE2A2_14", + "CFG_CENTER_NW4END0_19", + "CFG_CENTER_NW4END1_14", + "CFG_CENTER_SW4END2_9", + "CFG_CENTER_IMUX0_6", + "CFG_CENTER_EE4B1_16", + "CFG_CENTER_EE4A0_18", + "CFG_CENTER_BSCAN2_SEL", + "CFG_CENTER_SE2A1_19", + "CFG_CENTER_FAN6_18", + "CFG_CENTER_LH4_7", + "CFG_CENTER_EE2BEG1_19", + "CFG_CENTER_IMUX31_3", + "CFG_CENTER_ICAP1_I9", + "CFG_CENTER_SE4C2_8", + "CFG_CENTER_SW4END1_17", + "CFG_CENTER_NW4END3_1", + "CFG_CENTER_IMUX23_13", + "CFG_CENTER_LOGIC_OUTS_B13_11", + "CFG_CENTER_LH9_17", + "CFG_CENTER_EE4B3_0", + "CFG_CENTER_NE4C0_2", + "CFG_CENTER_IMUX37_15", + "CFG_CENTER_SE4BEG1_3", + "CFG_CENTER_IMUX7_18", + "CFG_CENTER_IMUX15_18", + "CFG_CENTER_IMUX43_13", + "CFG_CENTER_IMUX21_19", + "CFG_CENTER_SE4C1_15", + "CFG_CENTER_SW4END1_18", + "CFG_CENTER_ICAP0_I21", + "CFG_CENTER_IMUX43_16", + "CFG_CENTER_EE4BEG3_0", + "CFG_CENTER_LOGIC_OUTS_B19_7", + "CFG_CENTER_IMUX42_14", + "CFG_CENTER_NW4END1_15", + "CFG_CENTER_ER1BEG3_11", + "CFG_CENTER_EE4BEG1_5", + "CFG_CENTER_IMUX25_10", + "CFG_CENTER_BYP2_19", + "CFG_CENTER_NW2A1_19", + "CFG_CENTER_EE2BEG3_13", + "CFG_CENTER_ICAP0_I13", + "CFG_CENTER_NW2A3_16", + "CFG_CENTER_IMUX25_2", + "CFG_CENTER_IMUX4_1", + "CFG_CENTER_LH9_2", + "CFG_CENTER_SW2A2_3", + "CFG_CENTER_WW4A3_18", + "CFG_CENTER_LOGIC_OUTS_B8_10", + "CFG_CENTER_SE4C1_19", + "CFG_CENTER_IMUX26_7", + "CFG_CENTER_IMUX35_18", + "CFG_CENTER_LOGIC_OUTS_B15_1", + "CFG_CENTER_LOGIC_OUTS_B21_0", + "CFG_CENTER_IMUX10_6", + "CFG_CENTER_BYP5_2", + "CFG_CENTER_IMUX41_11", + "CFG_CENTER_ICAP1_O1", + "CFG_CENTER_WW4B0_0", + "CFG_CENTER_IMUX29_5", + "CFG_CENTER_NE4BEG0_19", + "CFG_CENTER_SW2A2_18", + "CFG_CENTER_LH4_11", + "CFG_CENTER_WR1END0_3", + "CFG_CENTER_LOGIC_OUTS_B16_4", + "CFG_CENTER_NW2A3_13", + "CFG_CENTER_WW4A1_16", + "CFG_CENTER_EE2BEG2_19", + "CFG_CENTER_CFG_IO_ACCESS_CCLK", + "CFG_CENTER_SE2A1_9", + "CFG_CENTER_LOGIC_OUTS_B5_5", + "CFG_CENTER_WL1END1_6", + "CFG_CENTER_FAN7_3", + "CFG_CENTER_WW2A2_7", + "CFG_CENTER_MID_USR_ACCESS_DATA4", + "CFG_CENTER_SE4BEG2_14", + "CFG_CENTER_LOGIC_OUTS_B0_10", + "CFG_CENTER_IMUX4_2", + "CFG_CENTER_EL1BEG3_2", + "CFG_CENTER_BLOCK_OUTS_B3_6", + "CFG_CENTER_USR_ACCESS_DATA3", + "CFG_CENTER_LOGIC_OUTS_B0_14", + "CFG_CENTER_IMUX13_16", + "CFG_CENTER_IMUX15_19", + "CFG_CENTER_WW2A3_4", + "CFG_CENTER_IMUX10_15", + "CFG_CENTER_NE2A1_2", + "CFG_CENTER_WW4B0_5", + "CFG_CENTER_IMUX7_1", + "CFG_CENTER_IMUX26_15", + "CFG_CENTER_WW2A3_15", + "CFG_CENTER_WW4A3_5", + "CFG_CENTER_BYP5_6", + "CFG_CENTER_IMUX0_16", + "CFG_CENTER_LOGIC_OUTS_B10_7", "CFG_CENTER_USR_ACCESS_DATA7", + "CFG_CENTER_NE4BEG1_7", + "CFG_CENTER_IMUX18_8", + "CFG_CENTER_EE4A0_3", + "CFG_CENTER_BLOCK_OUTS_B2_3", + "CFG_CENTER_SW4END3_14", + "CFG_CENTER_WW4C2_7", + "CFG_CENTER_LOGIC_OUTS_B22_6", + "CFG_CENTER_IMUX25_5", + "CFG_CENTER_WL1END2_16", + "CFG_CENTER_NW4END2_12", + "CFG_CENTER_SE4C1_3", + "CFG_CENTER_LOGIC_OUTS_B9_1", + "CFG_CENTER_NE4BEG1_12", + "CFG_CENTER_LOGIC_OUTS_B1_10", + "CFG_CENTER_ICAP0_O15", + "CFG_CENTER_IMUX29_15", + "CFG_CENTER_SW2A2_10", + "CFG_CENTER_SE4C2_12", + "CFG_CENTER_IMUX24_7", + "CFG_CENTER_IMUX35_1", + "CFG_CENTER_IMUX23_18", + "CFG_CENTER_EE4C0_2", + "CFG_CENTER_WW4B1_0", + "CFG_CENTER_WR1END2_5", + "CFG_CENTER_FAN1_19", + "CFG_CENTER_BYP2_6", + "CFG_CENTER_NW2A3_9", + "CFG_CENTER_LOGIC_OUTS_B20_6", + "CFG_CENTER_WW2A2_18", + "CFG_CENTER_FAN1_16", + "CFG_CENTER_IMUX20_0", + "CFG_CENTER_IMUX15_3", + "CFG_CENTER_WW4B2_6", + "CFG_CENTER_EE4BEG3_18", + "CFG_CENTER_FRAME_ECC_FAR25", + "CFG_CENTER_SE2A2_7", + "CFG_CENTER_NE4C1_6", + "CFG_CENTER_IMUX46_16", + "CFG_CENTER_LOGIC_OUTS_B21_3", + "CFG_CENTER_LH3_7", + "CFG_CENTER_IMUX12_3", + "CFG_CENTER_LOGIC_OUTS_B5_14", + "CFG_CENTER_WW2A1_4", + "CFG_CENTER_LH10_7", + "CFG_CENTER_EE2A2_4", + "CFG_CENTER_NW4A2_12", + "CFG_CENTER_NW2A3_7", + "CFG_CENTER_IMUX18_19", + "CFG_CENTER_NW2A0_14", + "CFG_CENTER_BYP4_7", + "CFG_CENTER_WW2END2_12", + "CFG_CENTER_LH11_18", + "CFG_CENTER_EL1BEG0_1", + "CFG_CENTER_EL1BEG0_14", + "CFG_CENTER_SE4BEG0_19", + "CFG_CENTER_SW2A1_19", + "CFG_CENTER_FAN7_16", + "CFG_CENTER_NE4C0_4", + "CFG_CENTER_WL1END3_13", + "CFG_CENTER_NE4BEG3_12", + "CFG_CENTER_CTRL1_2", + "CFG_CENTER_LOGIC_OUTS_B23_7", + "CFG_CENTER_BLOCK_OUTS_B3_13", + "CFG_CENTER_FAN4_18", + "CFG_CENTER_EL1BEG2_18", + "CFG_CENTER_LOGIC_OUTS_B7_10", + "CFG_CENTER_IMUX31_0", + "CFG_CENTER_IMUX26_10", + "CFG_CENTER_IMUX21_16", + "CFG_CENTER_WW4C1_8", + "CFG_CENTER_LOGIC_OUTS_B13_2", + "CFG_CENTER_SW4A0_2", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA11", + "CFG_CENTER_ICAP0_O1", + "CFG_CENTER_WW4C0_0", + "CFG_CENTER_IMUX17_14", + "CFG_CENTER_LOGIC_OUTS_B15_10", + "CFG_CENTER_IMUX38_10", + "CFG_CENTER_FRAME_ECC_FAR6", + "CFG_CENTER_IMUX41_1", + "CFG_CENTER_EE4A2_15", + "CFG_CENTER_STARTUP_PACK", + "CFG_CENTER_IMUX16_1", + "CFG_CENTER_IMUX14_1", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA25", + "CFG_CENTER_IMUX30_7", + "CFG_CENTER_LOGIC_OUTS_B11_18", + "CFG_CENTER_NE4C2_19", + "CFG_CENTER_WW2A0_16", + "CFG_CENTER_LH4_1", + "CFG_CENTER_SW4A1_8", + "CFG_CENTER_WW2A3_18", + "CFG_CENTER_FAN0_10", + "CFG_CENTER_EE4C2_7", + "CFG_CENTER_FAN1_0", + "CFG_CENTER_BLOCK_OUTS_B2_16", + "CFG_CENTER_WW4A0_13", + "CFG_CENTER_EE4B2_18", + "CFG_CENTER_LOGIC_OUTS_B9_6", + "CFG_CENTER_SE4C0_8", + "CFG_CENTER_SE4BEG3_8", + "CFG_CENTER_EE4B3_11", + "CFG_CENTER_ER1BEG3_0", + "CFG_CENTER_IMUX37_8", + "CFG_CENTER_FRAME_ECC_SYNDROME8", + "CFG_CENTER_WW4C3_3", + "CFG_CENTER_NW2A2_0", + "CFG_CENTER_IMUX3_19", + "CFG_CENTER_BSCAN1_RESET", + "CFG_CENTER_EE4A1_1", + "CFG_CENTER_WW4B3_5", + "CFG_CENTER_WL1END2_4", + "CFG_CENTER_WW2END0_6", + "CFG_CENTER_WW4END2_10", + "CFG_CENTER_BYP6_9", + "CFG_CENTER_LH10_6", + "CFG_CENTER_LH2_0", + "CFG_CENTER_IMUX35_6", + "CFG_CENTER_SW2A1_16", + "CFG_CENTER_IMUX46_2", + "CFG_CENTER_BYP6_6", + "CFG_CENTER_WW4END2_7", + "CFG_CENTER_WW4END3_10", + "CFG_CENTER_WR1END0_4", + "CFG_CENTER_IMUX46_12", + "CFG_CENTER_EE4C0_1", + "CFG_CENTER_NW4A2_3", + "CFG_CENTER_WW2END1_14", + "CFG_CENTER_IMUX44_14", + "CFG_CENTER_USR_ACCESS_DATA14", + "CFG_CENTER_SW2A2_9", + "CFG_CENTER_NW4A1_6", + "CFG_CENTER_WW4C0_8", "CFG_CENTER_LOGIC_OUTS_B23_16", "CFG_CENTER_SE2A1_6", - "CFG_CENTER_BYP5_5", - "CFG_CENTER_BLOCK_OUTS_B1_1", - "CFG_CENTER_ICAP1_I5", - "CFG_CENTER_IMUX39_16", - "CFG_CENTER_EE4A3_0", - "CFG_CENTER_SW4END1_6", - "CFG_CENTER_STARTUP_USRCCLKTS", - "CFG_CENTER_WW4A3_4", - "CFG_CENTER_EE4C0_13", - "CFG_CENTER_NW4END0_2", - "CFG_CENTER_WW4C3_3", - "CFG_CENTER_SW2A1_6", - "CFG_CENTER_LH11_11", - "CFG_CENTER_EE2A0_6", - "CFG_CENTER_BLOCK_OUTS_B2_14", - "CFG_CENTER_WW4C1_5", - "CFG_CENTER_LH8_1", - "CFG_CENTER_BYP0_17", - "CFG_CENTER_SW4A1_8", - "CFG_CENTER_BYP7_7", - "CFG_CENTER_NE4C2_5", - "CFG_CENTER_WW4A1_4", - "CFG_CENTER_SE4BEG3_9", - "CFG_CENTER_FAN4_17", - "CFG_CENTER_IMUX14_19", - "CFG_CENTER_NW4A2_13", - "CFG_CENTER_WL1END3_11", - "CFG_CENTER_ICAP0_O18", - "CFG_CENTER_BYP1_17", - "CFG_CENTER_WR1END1_0", - "CFG_CENTER_EE4B1_12", - "CFG_CENTER_IMUX12_16", - "CFG_CENTER_IMUX6_12", - "CFG_CENTER_LH4_10", - "CFG_CENTER_NW2A2_9", - "CFG_CENTER_IMUX21_6", - "CFG_CENTER_LOGIC_OUTS_B23_14", - "CFG_CENTER_IMUX32_6", - "CFG_CENTER_LH2_4", - "CFG_CENTER_EE4B0_4", - "CFG_CENTER_IMUX43_8", - "CFG_CENTER_ER1BEG2_0", - "CFG_CENTER_IMUX5_18", - "CFG_CENTER_ICAP1_I12", - "CFG_CENTER_IMUX17_17", - "CFG_CENTER_CLK0_14", - "CFG_CENTER_LH9_2", - "CFG_CENTER_ER1BEG0_8", - "CFG_CENTER_ICAP1_I2", - "CFG_CENTER_CTRL1_2", - "CFG_CENTER_WW4C2_9", - "CFG_CENTER_LOGIC_OUTS_B18_17", - "CFG_CENTER_FAN7_8", - "CFG_CENTER_WW4B3_13", - "CFG_CENTER_EE4C2_4", - "CFG_CENTER_EL1BEG3_3", - "CFG_CENTER_SE2A0_13", "CFG_CENTER_IMUX13_7", - "CFG_CENTER_IMUX38_18", - "CFG_CENTER_NW2A0_10", - "CFG_CENTER_LOGIC_OUTS_B18_6", - "CFG_CENTER_SE4C0_10", - "CFG_CENTER_IMUX36_1", - "CFG_CENTER_EE2A0_5", - "CFG_CENTER_IMUX26_15", - "CFG_CENTER_FAN6_14", - "CFG_CENTER_IMUX44_10", - "CFG_CENTER_WW4C3_7", - "CFG_CENTER_IMUX23_17", - "CFG_CENTER_WW2END0_4", - "CFG_CENTER_SW2A0_10", - "CFG_CENTER_LH9_15", - "CFG_CENTER_IMUX28_16", - "CFG_CENTER_IMUX14_1", - "CFG_CENTER_IMUX21_4", - "CFG_CENTER_ICAP1_O15", - "CFG_CENTER_BSCAN2_RESET", - "CFG_CENTER_IMUX19_0", - "CFG_CENTER_WW4B0_13", - "CFG_CENTER_LH6_16", - "CFG_CENTER_WW2END1_12", - "CFG_CENTER_LOGIC_OUTS_B1_10", - "CFG_CENTER_NW4END2_18", - "CFG_CENTER_IMUX16_2", - "CFG_CENTER_USR_ACCESS_DATA6", - "CFG_CENTER_ICAP0_O19", - "CFG_CENTER_EL1BEG1_1", - "CFG_CENTER_LH3_3", - "CFG_CENTER_BLOCK_OUTS_B3_6", - "CFG_CENTER_BYP2_9", - "CFG_CENTER_IMUX44_14", - "CFG_CENTER_BLOCK_OUTS_B1_11", - "CFG_CENTER_WL1END3_19", - "CFG_CENTER_ER1BEG0_4", - "CFG_CENTER_IMUX21_17", - "CFG_CENTER_BSCAN1_TDI", - "CFG_CENTER_IMUX35_5", - "CFG_CENTER_LOGIC_OUTS_B12_17", - "CFG_CENTER_IMUX4_7", - "CFG_CENTER_WW4A2_10", - "CFG_CENTER_EE4C2_16", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_IMUX12_4", - "CFG_CENTER_SE2A1_17", - "CFG_CENTER_WW2END3_3", - "CFG_CENTER_WW4A3_10", - "CFG_CENTER_EE4A0_13", - "CFG_CENTER_NW2A3_13", - "CFG_CENTER_NW2A1_18", - "CFG_CENTER_SE4C3_16", - "CFG_CENTER_IMUX1_4", - "CFG_CENTER_IMUX13_13", - "CFG_CENTER_WW4C0_11", - "CFG_CENTER_EE4BEG2_15", - "CFG_CENTER_SE4C1_18", - "CFG_CENTER_WR1END3_10", - "CFG_CENTER_ER1BEG0_18", - "CFG_CENTER_NW4END2_13", - "CFG_CENTER_BYP0_5", - "CFG_CENTER_NW4END2_9", - "CFG_CENTER_LH3_6", - "CFG_CENTER_NW2A2_6", - "CFG_CENTER_NW2A0_3", - "CFG_CENTER_CFG_IO_ACCESS_INITBI", - "CFG_CENTER_EE4B3_17", - "CFG_CENTER_NW2A3_10", - "CFG_CENTER_IMUX21_9", - "CFG_CENTER_SW4END0_18", - "CFG_CENTER_LOGIC_OUTS_B11_1", - "CFG_CENTER_IMUX41_7", - "CFG_CENTER_EE4A0_16", - "CFG_CENTER_EE2BEG2_14", - "CFG_CENTER_NW4A0_16", - "CFG_CENTER_BLOCK_OUTS_B2_17", - "CFG_CENTER_LOGIC_OUTS_B12_15", - "CFG_CENTER_LH6_5", - "CFG_CENTER_BLOCK_OUTS_B0_4", - "CFG_CENTER_EE4A1_5", - "CFG_CENTER_LH12_16", - "CFG_CENTER_NW4A3_12", - "CFG_CENTER_WL1END2_12", - "CFG_CENTER_LH9_6", - "CFG_CENTER_NW4END2_1", - "CFG_CENTER_WW2END1_0", - "CFG_CENTER_WW4A2_7", - "CFG_CENTER_LH7_9", - "CFG_CENTER_LOGIC_OUTS_B1_12", - "CFG_CENTER_WR1END2_19", - "CFG_CENTER_NW4END3_17", - "CFG_CENTER_LH11_9", - "CFG_CENTER_LH11_18", - "CFG_CENTER_FAN3_5", - "CFG_CENTER_IMUX2_12", - "CFG_CENTER_NW2A3_17", - "CFG_CENTER_SW2A2_2", - "CFG_CENTER_NW2A3_14", - "CFG_CENTER_IMUX13_8", - "CFG_CENTER_EE2A0_13", - "CFG_CENTER_IMUX41_11", - "CFG_CENTER_NW4A1_16", - "CFG_CENTER_IMUX45_16", - "CFG_CENTER_WR1END2_13", - "CFG_CENTER_SW4A2_8", - "CFG_CENTER_NW2A1_2", - "CFG_CENTER_SE2A0_6", - "CFG_CENTER_LOGIC_OUTS_B15_15", - "CFG_CENTER_SW4A0_6", - "CFG_CENTER_STARTUP_USRDONETS", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_IMUX29_15", - "CFG_CENTER_IMUX27_0", - "CFG_CENTER_IMUX32_8", - "CFG_CENTER_WW4END3_8", - "CFG_CENTER_LOGIC_OUTS_B0_5", - "CFG_CENTER_IMUX30_8", - "CFG_CENTER_EL1BEG0_13", - "CFG_CENTER_IMUX16_3", - "CFG_CENTER_SE2A2_5", - "CFG_CENTER_IMUX5_6", - "CFG_CENTER_IMUX21_3", - "CFG_CENTER_ER1BEG3_14", - "CFG_CENTER_LH8_18", - "CFG_CENTER_WW4A3_0", - "CFG_CENTER_SE2A2_2", - "CFG_CENTER_LOGIC_OUTS_B14_17", - "CFG_CENTER_FAN1_10", - "CFG_CENTER_BYP0_12", - "CFG_CENTER_WW4A2_12", - "CFG_CENTER_WW2A3_5", - "CFG_CENTER_IMUX2_14", - "CFG_CENTER_IMUX26_3", - "CFG_CENTER_WW4B2_1", - "CFG_CENTER_IMUX3_3", - "CFG_CENTER_IMUX3_17", - "CFG_CENTER_WL1END1_2", - "CFG_CENTER_SW2A0_19", - "CFG_CENTER_CFG_IO_ACCESS_MODE1", - "CFG_CENTER_FAN6_13", - "CFG_CENTER_CK_IN10", - "CFG_CENTER_FRAME_ECC_FAR1", - "CFG_CENTER_WW4A3_5", - "CFG_CENTER_IMUX12_19", - "CFG_CENTER_LOGIC_OUTS_B14_13", - "CFG_CENTER_ICAP1_I24", - "CFG_CENTER_IMUX24_11", - "CFG_CENTER_ICAP0_I16", - "CFG_CENTER_NW4A2_2", - "CFG_CENTER_IMUX41_4", - "CFG_CENTER_IMUX8_2", - "CFG_CENTER_STARTUP_CLK", - "CFG_CENTER_IMUX32_11", - "CFG_CENTER_FAN0_19", - "CFG_CENTER_IMUX8_3", - "CFG_CENTER_IMUX8_12", - "CFG_CENTER_EE4C3_16", - "CFG_CENTER_EE4BEG0_19", - "CFG_CENTER_SE2A2_17", - "CFG_CENTER_IMUX35_10", - "CFG_CENTER_WW4A1_17", - "CFG_CENTER_EE2BEG0_1", - "CFG_CENTER_LH8_9", - "CFG_CENTER_FAN0_4", - "CFG_CENTER_CK_IN8", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_NW2A3_7", - "CFG_CENTER_EL1BEG0_8", - "CFG_CENTER_EE4BEG3_15", - "CFG_CENTER_EE2BEG2_6", - "CFG_CENTER_IMUX14_16", - "CFG_CENTER_LOGIC_OUTS_B2_16", - "CFG_CENTER_LOGIC_OUTS_B23_15", - "CFG_CENTER_LOGIC_OUTS_B2_13", - "CFG_CENTER_WW2A0_15", - "CFG_CENTER_ICAP1_I11", - "CFG_CENTER_IMUX39_9", - "CFG_CENTER_LOGIC_OUTS_B20_2", - "CFG_CENTER_LOGIC_OUTS_B9_2", - "CFG_CENTER_EE4A1_12", - "CFG_CENTER_WW2END1_19", - "CFG_CENTER_IMUX36_8", - "CFG_CENTER_EE2A2_3", - "CFG_CENTER_NW4A2_15", - "CFG_CENTER_LOGIC_OUTS_B15_13", - "CFG_CENTER_LH6_3", - "CFG_CENTER_CLK1_16", - "CFG_CENTER_LOGIC_OUTS_B14_18", - "CFG_CENTER_EE4BEG0_0", - "CFG_CENTER_WW2A3_13", - "CFG_CENTER_FRAME_ECC_SYNDROME3", - "CFG_CENTER_FAN4_11", - "CFG_CENTER_LH12_3", - "CFG_CENTER_WW4A3_9", - "CFG_CENTER_ICAP0_I5", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_NE2A3_2", - "CFG_CENTER_LOGIC_OUTS_B17_0", - "CFG_CENTER_FAN1_1", - "CFG_CENTER_IMUX28_4", - "CFG_CENTER_SW4A2_0", - "CFG_CENTER_WL1END0_15", - "CFG_CENTER_SE4C2_18", - "CFG_CENTER_NE2A1_0", - "CFG_CENTER_LOGIC_OUTS_B20_1", - "CFG_CENTER_IMUX12_7", - "CFG_CENTER_IMUX32_3", - "CFG_CENTER_EE4B3_9", - "CFG_CENTER_WW2END2_13", - "CFG_CENTER_LOGIC_OUTS_B18_2", - "CFG_CENTER_NE4BEG3_13", - "CFG_CENTER_BYP0_8", - "CFG_CENTER_EE2A1_3", - "CFG_CENTER_NE2A2_15", - "CFG_CENTER_SW4END0_5", - "CFG_CENTER_WW4A3_13", - "CFG_CENTER_EE4BEG2_9", - "CFG_CENTER_FAN3_4", - "CFG_CENTER_WL1END0_13", - "CFG_CENTER_BLOCK_OUTS_B0_9", - "CFG_CENTER_IMUX13_14", - "CFG_CENTER_IMUX3_18", - "CFG_CENTER_WW4END0_11", - "CFG_CENTER_WW4B0_7", - "CFG_CENTER_MID_USR_ACCESS_DATA3", - "CFG_CENTER_USR_ACCESS_DATA13", - "CFG_CENTER_IMUX16_7", - "CFG_CENTER_SW2A3_5", - "CFG_CENTER_WW4END3_19", - "CFG_CENTER_IMUX7_18", - "CFG_CENTER_SE4C1_5", - "CFG_CENTER_WR1END1_7", - "CFG_CENTER_IMUX35_12", - "CFG_CENTER_IMUX36_19", - "CFG_CENTER_ER1BEG1_13", - "CFG_CENTER_EE4A2_7", - "CFG_CENTER_LH6_19", - "CFG_CENTER_LOGIC_OUTS_B1_8", - "CFG_CENTER_BYP2_2", - "CFG_CENTER_ICAP0_O9", - "CFG_CENTER_NW4END0_5", - "CFG_CENTER_LOGIC_OUTS_B22_0", - "CFG_CENTER_LOGIC_OUTS_B13_0", - "CFG_CENTER_SE2A1_2", - "CFG_CENTER_IMUX14_18", - "CFG_CENTER_IMUX29_14", - "CFG_CENTER_SW4A1_17", - "CFG_CENTER_FRAME_ECC_SYNDROME2", - "CFG_CENTER_IMUX27_1", - "CFG_CENTER_SW4A0_11", - "CFG_CENTER_CK_IN12", - "CFG_CENTER_BSCAN3_TMS", - "CFG_CENTER_SE2A0_2", - "CFG_CENTER_IMUX29_8", - "CFG_CENTER_FAN5_3", - "CFG_CENTER_IMUX37_9", - "CFG_CENTER_FAN7_12", - "CFG_CENTER_LH2_10", - "CFG_CENTER_IMUX25_0", - "CFG_CENTER_IMUX19_9", - "CFG_CENTER_NE4BEG1_10", - "CFG_CENTER_EE4A2_6", - "CFG_CENTER_IMUX9_13", - "CFG_CENTER_ER1BEG3_3", - "CFG_CENTER_SW4END1_11", - "CFG_CENTER_IMUX29_10", - "CFG_CENTER_IMUX24_3", - "CFG_CENTER_LOGIC_OUTS_B15_18", - "CFG_CENTER_WW2END3_4", - "CFG_CENTER_WW2A2_4", - "CFG_CENTER_EE2BEG3_3", - "CFG_CENTER_NW4END2_19", - "CFG_CENTER_WW4B0_4", - "CFG_CENTER_EE2A1_8", - "CFG_CENTER_IMUX13_16", - "CFG_CENTER_FAN0_18", - "CFG_CENTER_WW4B1_8", - "CFG_CENTER_ER1BEG2_10", - "CFG_CENTER_IMUX47_11", - "CFG_CENTER_BYP7_16", - "CFG_CENTER_LH1_12", - "CFG_CENTER_LOGIC_OUTS_B23_3", - "CFG_CENTER_NW4A0_7", - "CFG_CENTER_SW4A0_17", - "CFG_CENTER_ER1BEG0_2", - "CFG_CENTER_BYP1_13", - "CFG_CENTER_EE4BEG2_7", - "CFG_CENTER_WW4A2_1", - "CFG_CENTER_NE2A2_7", - "CFG_CENTER_EE2BEG0_8", - "CFG_CENTER_SW2A3_13", - "CFG_CENTER_LOGIC_OUTS_B17_3", - "CFG_CENTER_CLK1_0", - "CFG_CENTER_IMUX6_6", - "CFG_CENTER_WR1END2_6", - "CFG_CENTER_FAN1_12", - "CFG_CENTER_EE2A2_12", - "CFG_CENTER_IMUX41_9", - "CFG_CENTER_IMUX16_19", - "CFG_CENTER_NE2A1_6", - "CFG_CENTER_LOGIC_OUTS_B0_4", - "CFG_CENTER_WL1END2_9", - "CFG_CENTER_ER1BEG0_7", - "CFG_CENTER_LOGIC_OUTS_B5_19", - "CFG_CENTER_NW4A1_9", - "CFG_CENTER_LOGIC_OUTS_B19_16", - "CFG_CENTER_LH4_15", - "CFG_CENTER_EL1BEG0_19", - "CFG_CENTER_WW2A3_17", - "CFG_CENTER_BYP2_11", - "CFG_CENTER_IMUX17_9", - "CFG_CENTER_EE4B1_2", - "CFG_CENTER_IMUX45_11", - "CFG_CENTER_NW4END2_4", - "CFG_CENTER_ICAP1_I10", - "CFG_CENTER_BLOCK_OUTS_B1_7", - "CFG_CENTER_LH11_1", - "CFG_CENTER_IMUX31_4", - "CFG_CENTER_IMUX0_5", - "CFG_CENTER_SW4A2_10", - "CFG_CENTER_SE4BEG3_0", - "CFG_CENTER_SE2A1_11", - "CFG_CENTER_EE4B1_1", - "CFG_CENTER_IMUX4_17", - "CFG_CENTER_LH10_9", - "CFG_CENTER_FRAME_ECC_SYNDROME12", - "CFG_CENTER_BYP5_19", - "CFG_CENTER_SW4END2_4", - "CFG_CENTER_BLOCK_OUTS_B0_5", - "CFG_CENTER_NW4A3_2", - "CFG_CENTER_IMUX31_15", - "CFG_CENTER_LOGIC_OUTS_B0_7", - "CFG_CENTER_LOGIC_OUTS_B22_15", - "CFG_CENTER_WW4B0_12", - "CFG_CENTER_NE2A3_17", - "CFG_CENTER_IMUX2_19", - "CFG_CENTER_WL1END0_9", - "CFG_CENTER_IMUX45_10", - "CFG_CENTER_SW4END1_12", - "CFG_CENTER_EL1BEG0_15", - "CFG_CENTER_IMUX21_0", - "CFG_CENTER_SE2A0_12", - "CFG_CENTER_LOGIC_OUTS_B1_0", - "CFG_CENTER_NW4A2_0", - "CFG_CENTER_NE2A2_9", - "CFG_CENTER_SE4C2_13", - "CFG_CENTER_WW2END3_16", - "CFG_CENTER_WW2A0_3", - "CFG_CENTER_NE4BEG2_18", - "CFG_CENTER_WW2END1_2", - "CFG_CENTER_SE4C1_14", - "CFG_CENTER_IMUX21_12", - "CFG_CENTER_ICAP1_I3", - "CFG_CENTER_IMUX29_3", - "CFG_CENTER_LOGIC_OUTS_B14_8", - "CFG_CENTER_ER1BEG0_17", - "CFG_CENTER_LOGIC_OUTS_B18_15", - "CFG_CENTER_LOGIC_OUTS_B7_13", - "CFG_CENTER_SE4BEG2_17", - "CFG_CENTER_EE4BEG0_2", - "CFG_CENTER_CLK1_9", - "CFG_CENTER_ICAP0_O16", - "CFG_CENTER_LOGIC_OUTS_B4_13", - "CFG_CENTER_EE4B2_13", - "CFG_CENTER_CTRL1_9", - "CFG_CENTER_NE4C1_14", - "CFG_CENTER_SW4END3_1", - "CFG_CENTER_WW2END1_10", - "CFG_CENTER_LH5_5", - "CFG_CENTER_EE4A2_5", - "CFG_CENTER_NW4END3_0", - "CFG_CENTER_IMUX47_7", - "CFG_CENTER_IMUX19_13", - "CFG_CENTER_WR1END2_1", - "CFG_CENTER_IMUX7_6", - "CFG_CENTER_ICAP1_I22", - "CFG_CENTER_LOGIC_OUTS_B9_4", - "CFG_CENTER_WW4A1_14", - "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", - "CFG_CENTER_LOGIC_OUTS_B0_9", - "CFG_CENTER_LOGIC_OUTS_B8_10", - "CFG_CENTER_ICAP0_I12", - "CFG_CENTER_WR1END2_9", - "CFG_CENTER_SW4A1_16", - "CFG_CENTER_EE2A0_7", - "CFG_CENTER_ICAP1_CLK", - "CFG_CENTER_LOGIC_OUTS_B23_12", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_SW4END2_8", - "CFG_CENTER_EE2BEG3_12", - "CFG_CENTER_IMUX23_3", - "CFG_CENTER_LOGIC_OUTS_B16_3", - "CFG_CENTER_LOGIC_OUTS_B21_2", - "CFG_CENTER_ICAP0_I10", - "CFG_CENTER_FAN3_18", - "CFG_CENTER_IMUX10_8", - "CFG_CENTER_IMUX22_11", - "CFG_CENTER_EL1BEG0_6", - "CFG_CENTER_IMUX8_5", - "CFG_CENTER_IMUX43_12", - "CFG_CENTER_NE4C3_1", - "CFG_CENTER_IMUX46_4", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_NW4A0_13", - "CFG_CENTER_LOGIC_OUTS_B13_8", - "CFG_CENTER_NE2A0_9", - "CFG_CENTER_ICAP1_O12", - "CFG_CENTER_LOGIC_OUTS_B21_6", - "CFG_CENTER_EE4C1_3", - "CFG_CENTER_WW4B1_12", - "CFG_CENTER_WW2A0_17", - "CFG_CENTER_LOGIC_OUTS_B16_16", - "CFG_CENTER_EE4B2_0", - "CFG_CENTER_BLOCK_OUTS_B1_10", - "CFG_CENTER_EE4B0_9", - "CFG_CENTER_LOGIC_OUTS_B22_18", - "CFG_CENTER_LH9_3", - "CFG_CENTER_NE4BEG1_14", - "CFG_CENTER_WW4C0_12", - "CFG_CENTER_NE2A1_7", - "CFG_CENTER_LH12_8", - "CFG_CENTER_LOGIC_OUTS_B21_11", - "CFG_CENTER_WW4C2_8", - "CFG_CENTER_ICAP0_I6", - "CFG_CENTER_FAN1_16", - "CFG_CENTER_ICAP0_I1", - "CFG_CENTER_EE4C1_18", - "CFG_CENTER_LOGIC_OUTS_B4_15", - "CFG_CENTER_EE4A0_12", - "CFG_CENTER_FRAME_ECC_SYNBIT2", - "CFG_CENTER_ER1BEG3_6", - "CFG_CENTER_IMUX43_4", - "CFG_CENTER_CLK1_19", - "CFG_CENTER_BSCAN3_SEL", - "CFG_CENTER_FAN0_1", - "CFG_CENTER_NE4C2_18", - "CFG_CENTER_BYP5_13", - "CFG_CENTER_NE4BEG3_6", - "CFG_CENTER_NW4END3_5", - "CFG_CENTER_LH6_10", - "CFG_CENTER_EE4C2_2", - "CFG_CENTER_ICAP1_O2", - "CFG_CENTER_BLOCK_OUTS_B3_5", - "CFG_CENTER_IMUX42_9", - "CFG_CENTER_NW2A1_1", - "CFG_CENTER_LOGIC_OUTS_B19_11", - "CFG_CENTER_WL1END3_9", - "CFG_CENTER_LOGIC_OUTS_B10_18", - "CFG_CENTER_SE2A0_19", - "CFG_CENTER_LOGIC_OUTS_B13_5", - "CFG_CENTER_EE2BEG1_3", - "CFG_CENTER_IMUX43_13", - "CFG_CENTER_LOGIC_OUTS_B2_9", - "CFG_CENTER_WW4END1_8", - "CFG_CENTER_EE2A0_14", - "CFG_CENTER_PMVIOB_A0", - "CFG_CENTER_LOGIC_OUTS_B11_12", - "CFG_CENTER_USR_ACCESS_CFGCLK", - "CFG_CENTER_CTRL1_7", - "CFG_CENTER_LOGIC_OUTS_B16_19", - "CFG_CENTER_WR1END1_9", - "CFG_CENTER_WW4B3_1", - "CFG_CENTER_EE2A3_9", - "CFG_CENTER_WW2A2_10", - "CFG_CENTER_FRAME_ECC_FAR20", - "CFG_CENTER_BLOCK_OUTS_B3_2", - "CFG_CENTER_IMUX19_16", - "CFG_CENTER_NE4C0_14", - "CFG_CENTER_LOGIC_OUTS_B17_12", - "CFG_CENTER_IMUX15_18", - "CFG_CENTER_EE2BEG2_9", - "CFG_CENTER_WW2END0_6", - "CFG_CENTER_FRAME_ECC_FAR12", - "CFG_CENTER_LOGIC_OUTS_B6_11", - "CFG_CENTER_ER1BEG0_19", - "CFG_CENTER_IMUX30_17", - "CFG_CENTER_WW4C2_10", - "CFG_CENTER_WW4B2_5", - "CFG_CENTER_EE4BEG3_19", - "CFG_CENTER_WW4A2_14", - "CFG_CENTER_LOGIC_OUTS_B14_12", - "CFG_CENTER_EE4B3_0", - "CFG_CENTER_EE4BEG0_5", - "CFG_CENTER_EE2A3_4", - "CFG_CENTER_IMUX5_17", - "CFG_CENTER_NE2A0_5", - "CFG_CENTER_CK_BUFHCLK7", - "CFG_CENTER_IMUX40_8", - "CFG_CENTER_LOGIC_OUTS_B20_14", - "CFG_CENTER_LOGIC_OUTS_B5_11", - "CFG_CENTER_EE2BEG3_2", - "CFG_CENTER_MID_USR_ACCESS_DATA9", - "CFG_CENTER_IMUX47_10", - "CFG_CENTER_LOGIC_OUTS_B18_18", - "CFG_CENTER_SE4C1_1", - "CFG_CENTER_BYP3_10", - "CFG_CENTER_IMUX39_0", - "CFG_CENTER_CLK1_1", - "CFG_CENTER_IMUX35_0", - "CFG_CENTER_ER1BEG1_17", - "CFG_CENTER_CLK1_18", - "CFG_CENTER_EE4A1_9", - "CFG_CENTER_WL1END1_16", - "CFG_CENTER_WW4B1_6", - "CFG_CENTER_LOGIC_OUTS_B19_19", - "CFG_CENTER_EE2BEG1_11", - "CFG_CENTER_LH11_3", - "CFG_CENTER_IMUX6_14", - "CFG_CENTER_NE2A2_5", - "CFG_CENTER_IMUX47_16", - "CFG_CENTER_FAN7_17", - "CFG_CENTER_SE2A3_9", - "CFG_CENTER_EE4C1_11", - "CFG_CENTER_NW4A3_5", - "CFG_CENTER_IMUX23_10", - "CFG_CENTER_LOGIC_OUTS_B15_4", - "CFG_CENTER_WW2A3_15", - "CFG_CENTER_FAN6_12", - "CFG_CENTER_LOGIC_OUTS_B17_16", - "CFG_CENTER_LOGIC_OUTS_B12_10", - "CFG_CENTER_NE4BEG1_16", - "CFG_CENTER_LH7_2", - "CFG_CENTER_WW4C0_10", - "CFG_CENTER_NE4BEG3_5", - "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", - "CFG_CENTER_NE2A0_6", - "CFG_CENTER_LH2_1", - "CFG_CENTER_SW2A1_0", - "CFG_CENTER_SW2A1_10", - "CFG_CENTER_EE2BEG3_7", - "CFG_CENTER_LOGIC_OUTS_B23_18", - "CFG_CENTER_NE4C3_19", - "CFG_CENTER_SW4A3_19", - "CFG_CENTER_IMUX19_12", - "CFG_CENTER_EE4B0_13", - "CFG_CENTER_IMUX21_7", - "CFG_CENTER_FAN1_2", - "CFG_CENTER_ICAP0_I20", - "CFG_CENTER_WW2A1_17", - "CFG_CENTER_SW4END3_6", - "CFG_CENTER_SE4BEG2_1", - "CFG_CENTER_ICAP0_O25", - "CFG_CENTER_IMUX4_0", - "CFG_CENTER_LOGIC_OUTS_B19_15", - "CFG_CENTER_WW2A2_14", - "CFG_CENTER_NW2A2_3", - "CFG_CENTER_LH7_8", - "CFG_CENTER_IMUX10_13", - "CFG_CENTER_IMUX36_4", - "CFG_CENTER_IMUX40_16", - "CFG_CENTER_WR1END0_18", - "CFG_CENTER_SW2A1_5", - "CFG_CENTER_IMUX40_6", - "CFG_CENTER_LOGIC_OUTS_B5_15", - "CFG_CENTER_NW4A1_17", - "CFG_CENTER_LOGIC_OUTS_B6_12", - "CFG_CENTER_ICAP0_O29", - "CFG_CENTER_EE2A0_1", - "CFG_CENTER_EE2A1_18", - "CFG_CENTER_NW4END0_13", - "CFG_CENTER_IMUX26_14", - "CFG_CENTER_SW2A2_13", - "CFG_CENTER_WW4END2_10", - "CFG_CENTER_CK_BUFHCLK1", - "CFG_CENTER_WW4B0_15", - "CFG_CENTER_WW4A1_12", - "CFG_CENTER_IMUX9_18", - "CFG_CENTER_IMUX36_6", - "CFG_CENTER_IMUX44_15", - "CFG_CENTER_WW4END1_1", - "CFG_CENTER_IMUX14_8", - "CFG_CENTER_EE2BEG0_14", - "CFG_CENTER_SE4BEG3_2", - "CFG_CENTER_LOGIC_OUTS_B7_18", - "CFG_CENTER_WW4A0_4", - "CFG_CENTER_SE4C1_13", - "CFG_CENTER_WW2END0_17", - "CFG_CENTER_WW2END2_5", - "CFG_CENTER_IMUX26_19", - "CFG_CENTER_SW4END0_12", - "CFG_CENTER_LOGIC_OUTS_B4_17", - "CFG_CENTER_WW2A2_5", - "CFG_CENTER_SW2A1_18", - "CFG_CENTER_CLK1_7", - "CFG_CENTER_WW4C3_10", - "CFG_CENTER_LH8_16", - "CFG_CENTER_ER1BEG2_11", - "CFG_CENTER_EE2BEG3_5", - "CFG_CENTER_IMUX17_5", - "CFG_CENTER_SW2A3_11", - "CFG_CENTER_FAN3_11", - "CFG_CENTER_FAN0_13", - "CFG_CENTER_IMUX18_16", - "CFG_CENTER_NW2A2_17", - "CFG_CENTER_SE4BEG1_10", - "CFG_CENTER_CK_IN4", - "CFG_CENTER_ER1BEG1_2", - "CFG_CENTER_IMUX1_10", - "CFG_CENTER_WW4END3_13", - "CFG_CENTER_SW4END1_9", - "CFG_CENTER_BYP1_14", - "CFG_CENTER_LOGIC_OUTS_B11_15", - "CFG_CENTER_IMUX27_11", - "CFG_CENTER_IMUX31_11", - "CFG_CENTER_IMUX5_4", - "CFG_CENTER_NW4A3_17", - "CFG_CENTER_SW4END1_4", - "CFG_CENTER_BSCAN4_TDI", - "CFG_CENTER_FAN7_2", - "CFG_CENTER_IMUX19_14", - "CFG_CENTER_EE4C2_19", - "CFG_CENTER_IMUX12_9", - "CFG_CENTER_EE4A2_17", - "CFG_CENTER_SW4A1_2", - "CFG_CENTER_CLK0_16", - "CFG_CENTER_BLOCK_OUTS_B0_16", - "CFG_CENTER_CLK0_6", - "CFG_CENTER_LH8_8", - "CFG_CENTER_IMUX9_7", - "CFG_CENTER_WW2END3_2", - "CFG_CENTER_NW4A3_11", - "CFG_CENTER_EE2A3_3", - "CFG_CENTER_IMUX39_7", - "CFG_CENTER_NW4END1_1", - "CFG_CENTER_EE4C1_7", - "CFG_CENTER_EE4C0_19", - "CFG_CENTER_EE2A2_10", - "CFG_CENTER_USR_ACCESS_DATA15", - "CFG_CENTER_NW4END2_11", - "CFG_CENTER_WW4A1_2", - "CFG_CENTER_LOGIC_OUTS_B3_10", - "CFG_CENTER_SE4BEG1_2", - "CFG_CENTER_FAN0_17", - "CFG_CENTER_SE4C2_8", - "CFG_CENTER_LH1_10", - "CFG_CENTER_SE4C2_5", - "CFG_CENTER_WW4C1_10", - "CFG_CENTER_ICAP0_I26", - "CFG_CENTER_LOGIC_OUTS_B1_16", - "CFG_CENTER_BYP4_2", - "CFG_CENTER_LOGIC_OUTS_B21_8", - "CFG_CENTER_FAN6_3", - "CFG_CENTER_NW4A0_5", - "CFG_CENTER_SW4END0_14", - "CFG_CENTER_LOGIC_OUTS_B13_12", - "CFG_CENTER_CLK1_11", - "CFG_CENTER_FAN6_9", - "CFG_CENTER_IMUX30_18", - "CFG_CENTER_ER1BEG1_0", - "CFG_CENTER_IMUX11_17", - "CFG_CENTER_IMUX1_1", - "CFG_CENTER_ICAP1_O28", - "CFG_CENTER_CTRL1_1", - "CFG_CENTER_IMUX3_13", - "CFG_CENTER_BLOCK_OUTS_B3_14", - "CFG_CENTER_ICAP1_O16", - "CFG_CENTER_LOGIC_OUTS_B11_19", - "CFG_CENTER_EL1BEG0_11", - "CFG_CENTER_IMUX37_19", - "CFG_CENTER_BLOCK_OUTS_B2_4", - "CFG_CENTER_EE4BEG2_11", - "CFG_CENTER_EE4A0_6", - "CFG_CENTER_WR1END2_2", - "CFG_CENTER_ICAP1_I17", - "CFG_CENTER_WW2A1_5", - "CFG_CENTER_SW2A1_11", - "CFG_CENTER_IMUX10_2", - "CFG_CENTER_SE4BEG3_1", - "CFG_CENTER_LOGIC_OUTS_B21_9", - "CFG_CENTER_NW2A1_16", - "CFG_CENTER_WR1END0_3", - "CFG_CENTER_NE4C2_0", - "CFG_CENTER_IMUX4_6", - "CFG_CENTER_SE4C3_17", - "CFG_CENTER_LH10_7", - "CFG_CENTER_EE2BEG3_15", - "CFG_CENTER_BYP7_8", - "CFG_CENTER_EE4C2_18", - "CFG_CENTER_IMUX45_14", - "CFG_CENTER_FAN4_9", - "CFG_CENTER_IMUX24_8", - "CFG_CENTER_ICAP0_O7", - "CFG_CENTER_FAN7_7", - "CFG_CENTER_NW4END3_13", - "CFG_CENTER_IMUX39_17", - "CFG_CENTER_IMUX25_12", - "CFG_CENTER_LH3_4", - "CFG_CENTER_FAN2_15", - "CFG_CENTER_IMUX26_9", - "CFG_CENTER_WW4C1_16", - "CFG_CENTER_IMUX6_15", - "CFG_CENTER_IMUX37_17", - "CFG_CENTER_NW4A1_13", - "CFG_CENTER_IMUX15_8", - "CFG_CENTER_BLOCK_OUTS_B1_19", - "CFG_CENTER_NW2A2_4", - "CFG_CENTER_EE2BEG3_18", - "CFG_CENTER_NE2A0_14", - "CFG_CENTER_IMUX10_5", - "CFG_CENTER_FAN6_15", - "CFG_CENTER_NE4C0_5", - "CFG_CENTER_LOGIC_OUTS_B22_14", - "CFG_CENTER_SE4C0_16", - "CFG_CENTER_WW2END0_15", - "CFG_CENTER_BYP1_16", - "CFG_CENTER_NW4END2_10", - "CFG_CENTER_EE4B3_6", - "CFG_CENTER_LH1_0", - "CFG_CENTER_WW4B3_16", - "CFG_CENTER_WW4B1_10", - "CFG_CENTER_LOGIC_OUTS_B5_10", - "CFG_CENTER_SW4END3_2", - "CFG_CENTER_IMUX37_16", - "CFG_CENTER_NW2A0_6", - "CFG_CENTER_LOGIC_OUTS_B1_14", - "CFG_CENTER_WW4A2_18", - "CFG_CENTER_EE2BEG3_17", - "CFG_CENTER_BYP6_13", + "CFG_CENTER_IMUX39_18", + "CFG_CENTER_LOGIC_OUTS_B19_8", + "CFG_CENTER_CK_BUFHCLK2", "CFG_CENTER_IMUX14_10", - "CFG_CENTER_LH7_3", - "CFG_CENTER_NE4C2_3", - "CFG_CENTER_IMUX35_2", - "CFG_CENTER_SW2A2_18", - "CFG_CENTER_WW2END3_15", - "CFG_CENTER_IMUX12_3", - "CFG_CENTER_FAN4_5", - "CFG_CENTER_SE2A1_5", - "CFG_CENTER_NW2A3_4", - "CFG_CENTER_WR1END1_18", - "CFG_CENTER_ICAP0_I29", - "CFG_CENTER_IMUX43_3", - "CFG_CENTER_SW4END3_14", - "CFG_CENTER_IMUX42_16", - "CFG_CENTER_SE2A1_13", - "CFG_CENTER_EE4A0_7", - "CFG_CENTER_IMUX11_18", - "CFG_CENTER_WW4END0_4", - "CFG_CENTER_FRAME_ECC_FAR19", - "CFG_CENTER_SW4END3_9", - "CFG_CENTER_ICAP0_O1", - "CFG_CENTER_NW2A3_11", - "CFG_CENTER_IMUX46_14", - "CFG_CENTER_FRAME_ECC_FAR2", - "CFG_CENTER_MID_USR_ACCESS_DATA4", - "CFG_CENTER_EE4B1_4", - "CFG_CENTER_IMUX10_7", - "CFG_CENTER_SW4A2_11", - "CFG_CENTER_IMUX32_0", - "CFG_CENTER_WW4A0_16", - "CFG_CENTER_SW4END3_15", - "CFG_CENTER_CTRL1_12", - "CFG_CENTER_ER1BEG2_2", - "CFG_CENTER_IMUX27_6", - "CFG_CENTER_FRAME_ECC_FAR10", - "CFG_CENTER_WW4A2_11", - "CFG_CENTER_SE4BEG2_12", - "CFG_CENTER_ER1BEG3_11", - "CFG_CENTER_BLOCK_OUTS_B1_12", - "CFG_CENTER_FRAME_ECC_SYNWORD1", - "CFG_CENTER_SW4END1_5", - "CFG_CENTER_SW4END1_1", - "CFG_CENTER_NE4BEG3_17", - "CFG_CENTER_IMUX23_5", - "CFG_CENTER_NE4C3_14", - "CFG_CENTER_NE4C1_16", - "CFG_CENTER_LOGIC_OUTS_B6_14", - "CFG_CENTER_CTRL1_10", - "CFG_CENTER_IMUX2_6", - "CFG_CENTER_IMUX39_19", - "CFG_CENTER_SE4C0_6", - "CFG_CENTER_IMUX33_5", - "CFG_CENTER_NW2A1_6", - "CFG_CENTER_LH9_4", - "CFG_CENTER_IMUX9_1", + "CFG_CENTER_SE2A0_8", + "CFG_CENTER_LOGIC_OUTS_B11_12", + "CFG_CENTER_NE4C0_16", + "CFG_CENTER_WW4A3_19", + "CFG_CENTER_WW4B1_7", + "CFG_CENTER_ICAP1_O4", + "CFG_CENTER_FAN5_0", + "CFG_CENTER_CLK0_9", + "CFG_CENTER_IMUX45_1", + "CFG_CENTER_USR_ACCESS_CFGCLK", "CFG_CENTER_WW2END2_14", - "CFG_CENTER_IMUX26_13", - "CFG_CENTER_WW4C1_15", - "CFG_CENTER_EE2A3_8", - "CFG_CENTER_LOGIC_OUTS_B2_19", - "CFG_CENTER_SW4END2_11", - "CFG_CENTER_IMUX45_5", - "CFG_CENTER_IMUX28_5", - "CFG_CENTER_WW4END3_11", - "CFG_CENTER_NE4C1_1", - "CFG_CENTER_WW4C0_18", - "CFG_CENTER_EL1BEG3_4", - "CFG_CENTER_WW4A1_6", - "CFG_CENTER_IMUX8_4", - "CFG_CENTER_ER1BEG1_14", - "CFG_CENTER_ER1BEG3_1", - "CFG_CENTER_EL1BEG0_14", - "CFG_CENTER_EE4B1_19", - "CFG_CENTER_WW2A3_18", - "CFG_CENTER_IMUX31_8", - "CFG_CENTER_NW4A1_18", - "CFG_CENTER_LOGIC_OUTS_B1_4", - "CFG_CENTER_BYP4_7", - "CFG_CENTER_WL1END1_14", + "CFG_CENTER_IMUX42_7", + "CFG_CENTER_LOGIC_OUTS_B12_14", + "CFG_CENTER_WW2END0_8", + "CFG_CENTER_WL1END2_13", + "CFG_CENTER_IMUX38_1", + "CFG_CENTER_NE4C3_13", + "CFG_CENTER_WL1END1_7", + "CFG_CENTER_ICAP1_I20", + "CFG_CENTER_FAN7_8", + "CFG_CENTER_NW2A2_4", + "CFG_CENTER_WW2END0_16", + "CFG_CENTER_SE4C1_18", + "CFG_CENTER_FRAME_ECC_CRCERROR", + "CFG_CENTER_LOGIC_OUTS_B4_9", + "CFG_CENTER_ICAP0_I12", + "CFG_CENTER_EE4BEG3_11", + "CFG_CENTER_IMUX2_16", + "CFG_CENTER_IMUX27_19", + "CFG_CENTER_WW4A2_1", + "CFG_CENTER_EE2BEG1_18", + "CFG_CENTER_NW4END3_12", + "CFG_CENTER_SE2A2_2", + "CFG_CENTER_ER1BEG2_13", + "CFG_CENTER_NE2A3_13", + "CFG_CENTER_SW2A2_11", + "CFG_CENTER_NE4BEG3_7", "CFG_CENTER_SE2A0_5", - "CFG_CENTER_SE2A3_15", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_SE4C1_12", - "CFG_CENTER_IMUX35_13", - "CFG_CENTER_LOGIC_OUTS_B4_18", - "CFG_CENTER_LOGIC_OUTS_B0_10", - "CFG_CENTER_SE4BEG0_7", - "CFG_CENTER_IMUX16_1", - "CFG_CENTER_SE2A1_3", - "CFG_CENTER_WW4B1_14", - "CFG_CENTER_EL1BEG2_10", - "CFG_CENTER_SW4A3_11", - "CFG_CENTER_LH7_13", - "CFG_CENTER_LOGIC_OUTS_B22_11", - "CFG_CENTER_ICAP0_O4", - "CFG_CENTER_ICAP1_O29", - "CFG_CENTER_NW2A3_1", - "CFG_CENTER_EL1BEG0_10", - "CFG_CENTER_EE4A2_9", - "CFG_CENTER_NW4END3_6", - "CFG_CENTER_IMUX2_7", - "CFG_CENTER_LOGIC_OUTS_B2_7", - "CFG_CENTER_SE4BEG0_0", - "CFG_CENTER_LH1_2", - "CFG_CENTER_WW4END1_4", - "CFG_CENTER_BYP3_15", - "CFG_CENTER_WW4END2_12", - "CFG_CENTER_LOGIC_OUTS_B12_16", - "CFG_CENTER_SE4C3_3", - "CFG_CENTER_EE4C1_19", - "CFG_CENTER_EE4A1_19", - "CFG_CENTER_BYP5_17", - "CFG_CENTER_WW2END3_8", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_NW4END0_1", - "CFG_CENTER_LH9_17", - "CFG_CENTER_LOGIC_OUTS_B8_6", - "CFG_CENTER_SE4C0_8", - "CFG_CENTER_IMUX9_11", - "CFG_CENTER_BYP6_3", - "CFG_CENTER_NE4C1_8", - "CFG_CENTER_IMUX15_10", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_FRAME_ECC_SYNDROME8", - "CFG_CENTER_BLOCK_OUTS_B0_13", - "CFG_CENTER_IMUX35_3", - "CFG_CENTER_BYP0_11", - "CFG_CENTER_BYP5_16", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_IMUX47_6", - "CFG_CENTER_LOGIC_OUTS_B18_4", - "CFG_CENTER_EL1BEG3_7", - "CFG_CENTER_EE4C0_1", - "CFG_CENTER_BYP6_10", - "CFG_CENTER_SW4A1_18", - "CFG_CENTER_LH3_8", - "CFG_CENTER_LOGIC_OUTS_B5_7", - "CFG_CENTER_SW4A0_3", - "CFG_CENTER_WR1END3_2", - "CFG_CENTER_BYP3_19", - "CFG_CENTER_IMUX45_18", - "CFG_CENTER_BLOCK_OUTS_B0_17", - "CFG_CENTER_SE2A2_13", - "CFG_CENTER_WW4B0_16", - "CFG_CENTER_EL1BEG1_18", - "CFG_CENTER_ICAP0_O5", - "CFG_CENTER_WL1END2_18", - "CFG_CENTER_ER1BEG2_3", + "CFG_CENTER_NE2A2_19", + "CFG_CENTER_IMUX37_13", + "CFG_CENTER_LH8_8", + "CFG_CENTER_WW4B1_3", + "CFG_CENTER_ICAP1_O9", "CFG_CENTER_SE2A2_1", - "CFG_CENTER_ICAP1_I18", - "CFG_CENTER_WW4B0_10", - "CFG_CENTER_EL1BEG1_7", - "CFG_CENTER_IMUX31_16", - "CFG_CENTER_LOGIC_OUTS_B23_11", - "CFG_CENTER_NE2A3_0", - "CFG_CENTER_WW4A1_13", - "CFG_CENTER_LOGIC_OUTS_B21_15", + "CFG_CENTER_EE2A0_5", + "CFG_CENTER_EE2A1_2", + "CFG_CENTER_IMUX4_16", + "CFG_CENTER_FRAME_ECC_SYNBIT0", + "CFG_CENTER_MID_USR_ACCESS_DATA8", + "CFG_CENTER_SW2A1_4", + "CFG_CENTER_FAN6_8", + "CFG_CENTER_IMUX25_9", + "CFG_CENTER_WW4A2_19", + "CFG_CENTER_WL1END0_2", + "CFG_CENTER_WW4B3_6", "CFG_CENTER_EL1BEG0_3", - "CFG_CENTER_WW2A1_1", - "CFG_CENTER_SE2A2_15", - "CFG_CENTER_WW4END1_17", - "CFG_CENTER_WW2END1_14", - "CFG_CENTER_EE4A1_18", - "CFG_CENTER_IMUX39_11", - "CFG_CENTER_EE4A0_18", - "CFG_CENTER_NW2A1_12", - "CFG_CENTER_IMUX9_12", - "CFG_CENTER_IMUX41_10", - "CFG_CENTER_WW4B1_11", - "CFG_CENTER_ICAP0_I9", - "CFG_CENTER_WW2A1_14", - "CFG_CENTER_SW4A3_14", - "CFG_CENTER_LOGIC_OUTS_B20_3", - "CFG_CENTER_IMUX39_6", - "CFG_CENTER_SE2A3_0", - "CFG_CENTER_LOGIC_OUTS_B2_10", - "CFG_CENTER_LH10_17", - "CFG_CENTER_IMUX35_14", - "CFG_CENTER_LH5_4", - "CFG_CENTER_CTRL1_0", - "CFG_CENTER_IMUX20_16", - "CFG_CENTER_WW2A0_8", - "CFG_CENTER_NW4A2_14", - "CFG_CENTER_EL1BEG2_11", - "CFG_CENTER_WW4C0_4", - "CFG_CENTER_EE4BEG0_9", - "CFG_CENTER_LOGIC_OUTS_B20_7", - "CFG_CENTER_WW4A1_3", - "CFG_CENTER_SW4END3_12", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_IMUX29_16", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_EE2A3_13", - "CFG_CENTER_EE4A0_4", - "CFG_CENTER_ICAP0_O13", - "CFG_CENTER_LOGIC_OUTS_B13_18", - "CFG_CENTER_IMUX35_8", - "CFG_CENTER_SW4END0_10", - "CFG_CENTER_LOGIC_OUTS_B22_5", - "CFG_CENTER_IMUX44_9", - "CFG_CENTER_SW4A2_1", - "CFG_CENTER_ER1BEG1_9", - "CFG_CENTER_WW4A0_0", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_LOGIC_OUTS_B13_10", + "CFG_CENTER_FAN3_0", + "CFG_CENTER_WW4B0_12", + "CFG_CENTER_NW4END0_10", + "CFG_CENTER_WW4B2_14", + "CFG_CENTER_FAN2_6", + "CFG_CENTER_CK_IN9", + "CFG_CENTER_WL1END0_7", + "CFG_CENTER_FAN6_5", + "CFG_CENTER_IMUX19_0", + "CFG_CENTER_SW2A3_1", + "CFG_CENTER_EE2A1_14", + "CFG_CENTER_BLOCK_OUTS_B0_4", + "CFG_CENTER_USR_ACCESS_DATA15", + "CFG_CENTER_EE4BEG0_8", + "CFG_CENTER_NE4BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B18_16", + "CFG_CENTER_ICAP0_I23", + "CFG_CENTER_IMUX31_7", + "CFG_CENTER_NW4END3_6", + "CFG_CENTER_SE4BEG3_0", + "CFG_CENTER_IMUX12_18", + "CFG_CENTER_WW2A0_0", + "CFG_CENTER_IMUX46_15", + "CFG_CENTER_LOGIC_OUTS_B0_11", + "CFG_CENTER_LOGIC_OUTS_B11_8", + "CFG_CENTER_LH7_13", + "CFG_CENTER_ICAP0_O16", + "CFG_CENTER_SW2A2_8", + "CFG_CENTER_BYP5_8", + "CFG_CENTER_IMUX34_16", + "CFG_CENTER_IMUX40_3", + "CFG_CENTER_LOGIC_OUTS_B1_3", + "CFG_CENTER_NW4A3_11", + "CFG_CENTER_FRAME_ECC_SYNDROME5", + "CFG_CENTER_EE4B3_3", + "CFG_CENTER_IMUX25_7", + "CFG_CENTER_FAN7_18", + "CFG_CENTER_ICAP1_O25", + "CFG_CENTER_BSCAN3_DRCK", + "CFG_CENTER_NE4C0_12", + "CFG_CENTER_IMUX21_3", + "CFG_CENTER_EE4BEG1_3", + "CFG_CENTER_BYP6_19", + "CFG_CENTER_MID_ICAP1_CLK", + "CFG_CENTER_SW2A1_18", + "CFG_CENTER_LH6_9", + "CFG_CENTER_WW2A2_19", + "CFG_CENTER_EE4C3_16", + "CFG_CENTER_SW4A0_8", + "CFG_CENTER_LH4_12", + "CFG_CENTER_WW2END0_10", + "CFG_CENTER_SW4END2_16", + "CFG_CENTER_SW4END1_14", + "CFG_CENTER_EE4B0_6", + "CFG_CENTER_SW2A3_17", + "CFG_CENTER_CK_IN4", + "CFG_CENTER_CFG_IO_ACCESS_VGGCOMPOUT", + "CFG_CENTER_SW4END0_8", + "CFG_CENTER_ER1BEG0_17", + "CFG_CENTER_EE4C1_10", + "CFG_CENTER_IMUX14_6", + "CFG_CENTER_SE4C0_13", + "CFG_CENTER_SE4BEG2_7", + "CFG_CENTER_LH1_0", + "CFG_CENTER_IMUX29_4", + "CFG_CENTER_WR1END1_1", + "CFG_CENTER_WW2A3_6", + "CFG_CENTER_NE4BEG0_10", + "CFG_CENTER_LOGIC_OUTS_B17_6", + "CFG_CENTER_EE4C2_3", + "CFG_CENTER_LOGIC_OUTS_B20_0", + "CFG_CENTER_NW2A0_16", + "CFG_CENTER_NW4A0_14", + "CFG_CENTER_MID_USR_ACCESS_DATA3", + "CFG_CENTER_IMUX6_0", + "CFG_CENTER_IMUX34_0", + "CFG_CENTER_ICAP1_O0", + "CFG_CENTER_NE4BEG3_14", + "CFG_CENTER_SW4END3_7", + "CFG_CENTER_BYP7_15", + "CFG_CENTER_SW2A0_6", + "CFG_CENTER_EE4B2_4", + "CFG_CENTER_SE4C1_4", + "CFG_CENTER_NE4C3_3", + "CFG_CENTER_LH3_10", + "CFG_CENTER_SE4C2_9", + "CFG_CENTER_ER1BEG2_15", + "CFG_CENTER_EE2A3_7", + "CFG_CENTER_IMUX10_5", + "CFG_CENTER_NW4END2_9", + "CFG_CENTER_WW4C1_19", + "CFG_CENTER_SE4BEG0_18", + "CFG_CENTER_LOGIC_OUTS_B8_3", + "CFG_CENTER_IMUX26_19", + "CFG_CENTER_EE2BEG0_19", + "CFG_CENTER_LOGIC_OUTS_B16_10", + "CFG_CENTER_EE4C1_8", + "CFG_CENTER_EE4B1_18", + "CFG_CENTER_LOGIC_OUTS_B10_13", + "CFG_CENTER_NW4A0_12", + "CFG_CENTER_BYP2_18", + "CFG_CENTER_FRAME_ECC_FAR10", + "CFG_CENTER_WL1END3_5", + "CFG_CENTER_BLOCK_OUTS_B0_6", + "CFG_CENTER_IMUX10_3", + "CFG_CENTER_LH11_6", + "CFG_CENTER_USR_ACCESS_DATA30", + "CFG_CENTER_WW4A3_0", + "CFG_CENTER_NE2A0_13", + "CFG_CENTER_EE4BEG3_1", + "CFG_CENTER_SW4END3_15", + "CFG_CENTER_IMUX7_12", + "CFG_CENTER_WW2END0_19", + "CFG_CENTER_LOGIC_OUTS_B5_16", + "CFG_CENTER_WW4B2_13", + "CFG_CENTER_FAN1_11", + "CFG_CENTER_IMUX0_2", + "CFG_CENTER_IMUX33_4", + "CFG_CENTER_LH10_5", + "CFG_CENTER_EE2BEG1_14", + "CFG_CENTER_SE4BEG2_9", + "CFG_CENTER_LOGIC_OUTS_B16_3", + "CFG_CENTER_FAN2_19", + "CFG_CENTER_EE2BEG1_7", + "CFG_CENTER_IMUX9_11", + "CFG_CENTER_IMUX20_3", + "CFG_CENTER_SE2A3_14", + "CFG_CENTER_SE4C1_2", + "CFG_CENTER_LOGIC_OUTS_B15_3", + "CFG_CENTER_BYP2_14", + "CFG_CENTER_IMUX26_3", + "CFG_CENTER_LH7_9", + "CFG_CENTER_LOGIC_OUTS_B19_1", + "CFG_CENTER_LH2_17", + "CFG_CENTER_EE4BEG0_7", + "CFG_CENTER_ER1BEG2_9", + "CFG_CENTER_EE4C3_9", + "CFG_CENTER_BYP4_6", + "CFG_CENTER_LH8_16", + "CFG_CENTER_NE2A0_3", + "CFG_CENTER_WW2END0_14", + "CFG_CENTER_BLOCK_OUTS_B2_10", + "CFG_CENTER_EE4A0_14", + "CFG_CENTER_ER1BEG2_6", + "CFG_CENTER_NE2A2_10", + "CFG_CENTER_SE4BEG3_9", + "CFG_CENTER_LH6_19", + "CFG_CENTER_PMVIOB_A0", + "CFG_CENTER_IMUX11_14", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA20", + "CFG_CENTER_IMUX5_14", + "CFG_CENTER_EE4A2_16", + "CFG_CENTER_IMUX23_4", + "CFG_CENTER_IMUX15_11", + "CFG_CENTER_SW2A0_1", + "CFG_CENTER_NW2A1_13", + "CFG_CENTER_WW4END0_13", + "CFG_CENTER_WW4END1_0", + "CFG_CENTER_SW4END0_18", + "CFG_CENTER_BYP7_10", + "CFG_CENTER_FAN3_10", + "CFG_CENTER_EE2BEG3_0", + "CFG_CENTER_WR1END2_18", + "CFG_CENTER_EE4C2_15", + "CFG_CENTER_IMUX8_3", + "CFG_CENTER_WR1END3_7", + "CFG_CENTER_ICAP0_O21", + "CFG_CENTER_IMUX27_15", + "CFG_CENTER_NE4BEG3_8", + "CFG_CENTER_NW4A3_7", + "CFG_CENTER_EL1BEG3_15", + "CFG_CENTER_WW2END3_8", + "CFG_CENTER_WR1END1_16", + "CFG_CENTER_IMUX11_17", + "CFG_CENTER_ICAP0_O23", + "CFG_CENTER_WW4C2_3", + "CFG_CENTER_BLOCK_OUTS_B2_19", + "CFG_CENTER_LOGIC_OUTS_B13_8", + "CFG_CENTER_NE4BEG3_18", + "CFG_CENTER_NW4END1_8", + "CFG_CENTER_WW4A1_0", + "CFG_CENTER_WW4A0_8", + "CFG_CENTER_IMUX40_6", + "CFG_CENTER_EE2BEG0_4", "CFG_CENTER_LOGIC_OUTS_B3_7", - "CFG_CENTER_CK_BUFRCLK2", - "CFG_CENTER_LH3_17", - "CFG_CENTER_IMUX23_13", - "CFG_CENTER_FRAME_ECC_SYNDROME1", - "CFG_CENTER_NE4BEG0_5", - "CFG_CENTER_BYP3_12", - "CFG_CENTER_SE4BEG2_14", - "CFG_CENTER_WW2A1_13", - "CFG_CENTER_EE4C3_19", - "CFG_CENTER_SW4END2_5", + "CFG_CENTER_SW4A2_12", + "CFG_CENTER_CLK0_2", + "CFG_CENTER_WW4A0_11", + "CFG_CENTER_BYP1_3", + "CFG_CENTER_ER1BEG0_15", + "CFG_CENTER_EL1BEG0_6", + "CFG_CENTER_SW2A0_14", + "CFG_CENTER_WL1END1_0", + "CFG_CENTER_CLK1_15", + "CFG_CENTER_NW2A1_4", + "CFG_CENTER_LOGIC_OUTS_B14_10", + "CFG_CENTER_WW4B2_3", + "CFG_CENTER_EL1BEG1_1", + "CFG_CENTER_LOGIC_OUTS_B11_1", + "CFG_CENTER_WW2END3_10", + "CFG_CENTER_BYP2_4", + "CFG_CENTER_IMUX6_18", + "CFG_CENTER_IMUX37_6", + "CFG_CENTER_BLOCK_OUTS_B3_11", + "CFG_CENTER_LOGIC_OUTS_B3_8", + "CFG_CENTER_BYP3_6", + "CFG_CENTER_NE4BEG3_11", + "CFG_CENTER_EL1BEG3_12", + "CFG_CENTER_EE2A1_6", + "CFG_CENTER_IMUX12_8", + "CFG_CENTER_WW4END1_14", + "CFG_CENTER_IMUX44_8", + "CFG_CENTER_BLOCK_OUTS_B2_2", + "CFG_CENTER_NE4BEG3_13", + "CFG_CENTER_MID_USR_ACCESS_DATA14", + "CFG_CENTER_SE2A3_3", + "CFG_CENTER_EL1BEG1_8", + "CFG_CENTER_IMUX11_3", + "CFG_CENTER_ICAP0_I7", + "CFG_CENTER_BLOCK_OUTS_B2_9", + "CFG_CENTER_CTRL1_9", + "CFG_CENTER_IMUX39_1", + "CFG_CENTER_LOGIC_OUTS_B2_9", + "CFG_CENTER_WR1END1_14", + "CFG_CENTER_ER1BEG1_3", + "CFG_CENTER_IMUX1_15", + "CFG_CENTER_SW4A1_5", + "CFG_CENTER_IMUX4_10", + "CFG_CENTER_NE2A0_17", + "CFG_CENTER_WW4B0_18", + "CFG_CENTER_WW2END3_0", + "CFG_CENTER_EE2BEG0_9", + "CFG_CENTER_FAN5_10", + "CFG_CENTER_IMUX11_15", + "CFG_CENTER_FAN1_2", + "CFG_CENTER_IMUX17_5", + "CFG_CENTER_WW4A0_16", + "CFG_CENTER_NW4A2_17", + "CFG_CENTER_ICAP0_I11", + "CFG_CENTER_IMUX3_2", + "CFG_CENTER_WR1END1_13", + "CFG_CENTER_EE4C3_5", + "CFG_CENTER_EE2BEG2_18", + "CFG_CENTER_IMUX36_19", + "CFG_CENTER_EE2BEG1_12", + "CFG_CENTER_IMUX10_7", + "CFG_CENTER_WL1END3_9", + "CFG_CENTER_IMUX46_8", + "CFG_CENTER_LOGIC_OUTS_B16_11", + "CFG_CENTER_SE4C1_11", + "CFG_CENTER_IMUX4_18", + "CFG_CENTER_SW4END0_1", + "CFG_CENTER_EE2BEG1_11", + "CFG_CENTER_SW4END1_4", + "CFG_CENTER_WR1END2_7", + "CFG_CENTER_NE4C1_1", + "CFG_CENTER_WW2A1_8", + "CFG_CENTER_WL1END2_14", + "CFG_CENTER_IMUX2_14", + "CFG_CENTER_EE4B3_2", + "CFG_CENTER_LOGIC_OUTS_B21_1", + "CFG_CENTER_SE4C1_5", + "CFG_CENTER_BSCAN4_SEL", + "CFG_CENTER_WW2END0_13", + "CFG_CENTER_EE4A1_11", + "CFG_CENTER_LH1_8", + "CFG_CENTER_SE2A2_11", + "CFG_CENTER_WW4END1_17", + "CFG_CENTER_LOGIC_OUTS_B9_3", + "CFG_CENTER_NW4A3_9", + "CFG_CENTER_NE4C2_18", + "CFG_CENTER_WW4END2_19", + "CFG_CENTER_SE2A1_18", + "CFG_CENTER_WW2A3_16", + "CFG_CENTER_IMUX24_0", + "CFG_CENTER_CTRL0_19", + "CFG_CENTER_NW4END1_0", + "CFG_CENTER_IMUX44_11", + "CFG_CENTER_LOGIC_OUTS_B6_19", + "CFG_CENTER_LOGIC_OUTS_B1_13", + "CFG_CENTER_NE4C1_19", + "CFG_CENTER_EE2A3_2", + "CFG_CENTER_FAN6_13", + "CFG_CENTER_ER1BEG2_11", + "CFG_CENTER_IMUX9_18", + "CFG_CENTER_LOGIC_OUTS_B18_17", + "CFG_CENTER_NW4END0_0", + "CFG_CENTER_FAN5_8", + "CFG_CENTER_WW2END3_6", + "CFG_CENTER_EE4C1_11", + "CFG_CENTER_LOGIC_OUTS_B4_16", + "CFG_CENTER_LOGIC_OUTS_B23_6", + "CFG_CENTER_NW4A3_2", + "CFG_CENTER_LOGIC_OUTS_B6_12", + "CFG_CENTER_IMUX20_11", + "CFG_CENTER_IMUX4_7", + "CFG_CENTER_WW2A1_5", + "CFG_CENTER_NE2A1_0", + "CFG_CENTER_WW2END1_4", + "CFG_CENTER_LOGIC_OUTS_B6_17", + "CFG_CENTER_SW2A3_10", + "CFG_CENTER_LOGIC_OUTS_B13_14", + "CFG_CENTER_FAN0_8", + "CFG_CENTER_LOGIC_OUTS_B17_7", + "CFG_CENTER_LH4_16", + "CFG_CENTER_LH10_11", + "CFG_CENTER_LH8_2", + "CFG_CENTER_IMUX17_12", + "CFG_CENTER_LOGIC_OUTS_B2_13", + "CFG_CENTER_LOGIC_OUTS_B17_0", + "CFG_CENTER_LOGIC_OUTS_B9_14", + "CFG_CENTER_SW4A3_15", + "CFG_CENTER_NW4END3_5", + "CFG_CENTER_WR1END3_6", + "CFG_CENTER_IMUX10_13", + "CFG_CENTER_WW4C1_2", + "CFG_CENTER_IMUX5_13", + "CFG_CENTER_LH12_4", + "CFG_CENTER_IMUX31_6", + "CFG_CENTER_LH10_3", + "CFG_CENTER_IMUX22_3", + "CFG_CENTER_WL1END1_4", + "CFG_CENTER_IMUX8_12", + "CFG_CENTER_USR_ACCESS_DATA11", + "CFG_CENTER_SW2A3_2", + "CFG_CENTER_WW4B0_14", + "CFG_CENTER_IMUX38_16", + "CFG_CENTER_LOGIC_OUTS_B3_2", + "CFG_CENTER_LOGIC_OUTS_B6_9", + "CFG_CENTER_EL1BEG0_4", + "CFG_CENTER_SE4C3_5", + "CFG_CENTER_ER1BEG3_3", + "CFG_CENTER_EE4C0_9", + "CFG_CENTER_EE4B3_14", + "CFG_CENTER_FRAME_ECC_SYNDROME2", + "CFG_CENTER_ICAP0_I4", + "CFG_CENTER_NW4END1_4", + "CFG_CENTER_IMUX16_9", + "CFG_CENTER_LOGIC_OUTS_B5_7", + "CFG_CENTER_IMUX25_16", + "CFG_CENTER_LOGIC_OUTS_B22_5", + "CFG_CENTER_IMUX32_19", + "CFG_CENTER_NW4A2_5", + "CFG_CENTER_IMUX31_12", + "CFG_CENTER_IMUX42_4", + "CFG_CENTER_IMUX25_14", + "CFG_CENTER_LOGIC_OUTS_B11_11", + "CFG_CENTER_LH10_2", + "CFG_CENTER_NW2A0_9", + "CFG_CENTER_EE2BEG0_8", + "CFG_CENTER_SE4BEG3_10", + "CFG_CENTER_ER1BEG1_5", + "CFG_CENTER_LOGIC_OUTS_B2_18", + "CFG_CENTER_EE4C3_3", + "CFG_CENTER_SE4C1_8", + "CFG_CENTER_WL1END2_9", + "CFG_CENTER_SE4C1_14", "CFG_CENTER_EL1BEG3_8", "CFG_CENTER_IMUX40_14", - "CFG_CENTER_WW4B2_0", - "CFG_CENTER_IMUX46_10", - "CFG_CENTER_IMUX6_1", - "CFG_CENTER_SE4C1_15", - "CFG_CENTER_EE2A1_11", - "CFG_CENTER_BLOCK_OUTS_B1_5", - "CFG_CENTER_NW4A1_5", - "CFG_CENTER_EE4C0_8", - "CFG_CENTER_SW2A1_1", - "CFG_CENTER_NE2A1_8", - "CFG_CENTER_LOGIC_OUTS_B19_8", - "CFG_CENTER_LH2_7", - "CFG_CENTER_NW4END3_8", - "CFG_CENTER_NE4BEG2_14", - "CFG_CENTER_SW2A2_14", - "CFG_CENTER_MID_USR_ACCESS_DATA7", - "CFG_CENTER_EE4C3_6", - "CFG_CENTER_IMUX34_11", - "CFG_CENTER_FAN6_17", - "CFG_CENTER_SE4C0_0", - "CFG_CENTER_NW4END0_17", - "CFG_CENTER_EE4B3_13", - "CFG_CENTER_SE4BEG0_15", - "CFG_CENTER_NE4C0_17", - "CFG_CENTER_LOGIC_OUTS_B7_3", - "CFG_CENTER_EE2BEG1_5", - "CFG_CENTER_IMUX0_13", - "CFG_CENTER_SW4A1_5", - "CFG_CENTER_LOGIC_OUTS_B4_19", - "CFG_CENTER_WW4A2_13", - "CFG_CENTER_EE2BEG0_2", - "CFG_CENTER_IMUX40_3", - "CFG_CENTER_LH1_11", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_NE2A1_3", - "CFG_CENTER_NE4BEG3_0", - "CFG_CENTER_EE4C2_7", - "CFG_CENTER_EE2A2_9", - "CFG_CENTER_IMUX0_6", - "CFG_CENTER_WW4C3_4", - "CFG_CENTER_ER1BEG2_14", - "CFG_CENTER_USR_ACCESS_DATA12", - "CFG_CENTER_IMUX34_14", - "CFG_CENTER_BSCAN1_TDO", - "CFG_CENTER_NW2A1_13", - "CFG_CENTER_CLK0_3", - "CFG_CENTER_IMUX39_14", - "CFG_CENTER_WW4B2_10", - "CFG_CENTER_FAN4_10", - "CFG_CENTER_EE2A2_2", - "CFG_CENTER_IMUX26_8", - "CFG_CENTER_FAN5_16", - "CFG_CENTER_SE2A0_9", - "CFG_CENTER_WW4C2_0", - "CFG_CENTER_USR_ACCESS_DATA24", - "CFG_CENTER_LOGIC_OUTS_B18_13", - "CFG_CENTER_LOGIC_OUTS_B10_2", - "CFG_CENTER_IMUX47_13", - "CFG_CENTER_LH2_0", - "CFG_CENTER_EE4BEG0_6", - "CFG_CENTER_IMUX47_12", - "CFG_CENTER_LH12_4", - "CFG_CENTER_LOGIC_OUTS_B20_17", - "CFG_CENTER_WW4B1_9", - "CFG_CENTER_IMUX46_9", - "CFG_CENTER_NE4BEG0_7", - "CFG_CENTER_EE4A1_1", - "CFG_CENTER_IMUX12_12", - "CFG_CENTER_WW4A3_15", - "CFG_CENTER_IMUX24_14", - "CFG_CENTER_EE4A2_4", - "CFG_CENTER_WW2A2_17", - "CFG_CENTER_IMUX37_14", - "CFG_CENTER_LH10_14", - "CFG_CENTER_WW4END2_2", - "CFG_CENTER_IMUX27_9", - "CFG_CENTER_IMUX26_1", - "CFG_CENTER_WR1END0_0", - "CFG_CENTER_IMUX19_5", - "CFG_CENTER_IMUX26_11", - "CFG_CENTER_BYP5_9", - "CFG_CENTER_EL1BEG1_9", - "CFG_CENTER_IMUX12_13", - "CFG_CENTER_WR1END3_1", - "CFG_CENTER_SW4END2_19", - "CFG_CENTER_FAN2_8", - "CFG_CENTER_IMUX44_8", - "CFG_CENTER_WW4END2_16", - "CFG_CENTER_IMUX18_6", - "CFG_CENTER_IMUX13_10", - "CFG_CENTER_EE4C0_14", - "CFG_CENTER_NW2A3_12", - "CFG_CENTER_SE4BEG0_18", - "CFG_CENTER_IMUX29_11", - "CFG_CENTER_IMUX23_15", - "CFG_CENTER_IMUX22_0", - "CFG_CENTER_NW4END2_0", - "CFG_CENTER_LOGIC_OUTS_B13_2", - "CFG_CENTER_EE4B1_6", - "CFG_CENTER_SW4END3_10", - "CFG_CENTER_NE2A0_2", - "CFG_CENTER_IMUX24_9", - "CFG_CENTER_NE4BEG2_13", - "CFG_CENTER_LH8_4", - "CFG_CENTER_WW4B3_19", - "CFG_CENTER_ICAP0_I27", - "CFG_CENTER_IMUX14_15", - "CFG_CENTER_BYP3_5", - "CFG_CENTER_BLOCK_OUTS_B3_10", - "CFG_CENTER_BLOCK_OUTS_B0_2", - "CFG_CENTER_IMUX35_17", - "CFG_CENTER_LOGIC_OUTS_B6_5", - "CFG_CENTER_BLOCK_OUTS_B1_6", - "CFG_CENTER_EE4C1_8", - "CFG_CENTER_SE4C3_19", - "CFG_CENTER_IMUX20_17", - "CFG_CENTER_FAN0_12", - "CFG_CENTER_IMUX23_18", - "CFG_CENTER_WW4END2_0", - "CFG_CENTER_EE2BEG2_5", - "CFG_CENTER_NW4A2_17", - "CFG_CENTER_ER1BEG3_7", - "CFG_CENTER_IMUX20_19", - "CFG_CENTER_WW2A2_15", - "CFG_CENTER_IMUX14_17", - "CFG_CENTER_EE4A2_10", - "CFG_CENTER_SW2A3_4", - "CFG_CENTER_IMUX4_1", - "CFG_CENTER_IMUX38_14", - "CFG_CENTER_LH8_6", - "CFG_CENTER_FRAME_ECC_FAR7", - "CFG_CENTER_IMUX20_10", - "CFG_CENTER_ICAP0_CSIB", - "CFG_CENTER_USR_ACCESS_DATA16", - "CFG_CENTER_LOGIC_OUTS_B23_0", - "CFG_CENTER_WL1END2_10", - "CFG_CENTER_LOGIC_OUTS_B6_15", - "CFG_CENTER_EE4A0_9", - "CFG_CENTER_IMUX4_16", - "CFG_CENTER_NW4END1_2", - "CFG_CENTER_SE2A2_8", - "CFG_CENTER_EE4B0_1", - "CFG_CENTER_ER1BEG1_5", - "CFG_CENTER_NW2A3_8", - "CFG_CENTER_EE4BEG3_11", - "CFG_CENTER_IMUX2_18", - "CFG_CENTER_EE4C0_18", - "CFG_CENTER_WW4A0_3", - "CFG_CENTER_LOGIC_OUTS_B12_9", - "CFG_CENTER_EE4C1_13", - "CFG_CENTER_BYP6_2", - "CFG_CENTER_BLOCK_OUTS_B2_11", - "CFG_CENTER_WR1END3_15", - "CFG_CENTER_IMUX9_19", - "CFG_CENTER_LOGIC_OUTS_B9_12", - "CFG_CENTER_IMUX29_19", - "CFG_CENTER_NW4A0_2", - "CFG_CENTER_SW4A3_2", - "CFG_CENTER_IMUX17_1", - "CFG_CENTER_WW2A2_8", - "CFG_CENTER_EL1BEG2_5", - "CFG_CENTER_NW4A3_1", - "CFG_CENTER_LOGIC_OUTS_B6_7", - "CFG_CENTER_IMUX0_2", - "CFG_CENTER_SE2A0_16", - "CFG_CENTER_CLK0_0", - "CFG_CENTER_FAN4_7", - "CFG_CENTER_IMUX23_0", - "CFG_CENTER_LH4_1", - "CFG_CENTER_LOGIC_OUTS_B13_11", - "CFG_CENTER_EE4A2_18", - "CFG_CENTER_LH7_14", - "CFG_CENTER_EE4BEG2_5", - "CFG_CENTER_FAN3_14", - "CFG_CENTER_NE2A1_14", - "CFG_CENTER_IMUX34_3", - "CFG_CENTER_WW4END1_6", - "CFG_CENTER_IMUX31_14", - "CFG_CENTER_EE2A3_16", - "CFG_CENTER_NW4A3_16", - "CFG_CENTER_LH8_19", - "CFG_CENTER_IMUX25_13", - "CFG_CENTER_CAPTURE_CAP", - "CFG_CENTER_IMUX15_11", - "CFG_CENTER_SE2A3_17", - "CFG_CENTER_EE4C3_15", - "CFG_CENTER_FAN3_13", - "CFG_CENTER_IMUX44_2", - "CFG_CENTER_ICAP0_I7", - "CFG_CENTER_WW4C1_3", - "CFG_CENTER_SW4END0_17", - "CFG_CENTER_SW2A1_13", - "CFG_CENTER_EE4C0_17", - "CFG_CENTER_EE2BEG1_17", - "CFG_CENTER_NW4A2_8", - "CFG_CENTER_IMUX0_0", - "CFG_CENTER_LH5_14", - "CFG_CENTER_NE4BEG2_16", - "CFG_CENTER_WW2A3_0", - "CFG_CENTER_IMUX20_12", - "CFG_CENTER_IMUX0_9", - "CFG_CENTER_BLOCK_OUTS_B2_0", - "CFG_CENTER_EE2BEG2_13", - "CFG_CENTER_NW4END2_3", - "CFG_CENTER_IMUX16_14", - "CFG_CENTER_EE4C2_0", - "CFG_CENTER_SW4END0_16", - "CFG_CENTER_LH12_18", - "CFG_CENTER_LOGIC_OUTS_B19_2", - "CFG_CENTER_IMUX19_15", - "CFG_CENTER_LOGIC_OUTS_B19_6", - "CFG_CENTER_IMUX38_13", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA1", - "CFG_CENTER_LH3_10", - "CFG_CENTER_LOGIC_OUTS_B10_3", - "CFG_CENTER_WR1END1_2", - "CFG_CENTER_EE4BEG1_14", - "CFG_CENTER_IMUX7_19", - "CFG_CENTER_ICAP1_I9", - "CFG_CENTER_WR1END0_16", - "CFG_CENTER_LH8_15", - "CFG_CENTER_SE4BEG0_12", - "CFG_CENTER_IMUX5_19", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA8", - "CFG_CENTER_LH2_12", - "CFG_CENTER_EE2A2_13", - "CFG_CENTER_ER1BEG3_13", - "CFG_CENTER_IMUX3_10", - "CFG_CENTER_IMUX31_13", - "CFG_CENTER_NE2A3_15", - "CFG_CENTER_SW2A2_16", - "CFG_CENTER_IMUX25_18", - "CFG_CENTER_NE4BEG3_2", - "CFG_CENTER_LOGIC_OUTS_B23_13", - "CFG_CENTER_WW4END0_5", - "CFG_CENTER_SW4A3_18", - "CFG_CENTER_FAN2_2", - "CFG_CENTER_IMUX6_10", - "CFG_CENTER_CFG_IO_ACCESS_RDWRB", - "CFG_CENTER_EE4A2_19", - "CFG_CENTER_SE4C3_12", - "CFG_CENTER_WW4C2_4", - "CFG_CENTER_IMUX46_2", - "CFG_CENTER_EE4BEG1_18", - "CFG_CENTER_SE4BEG3_17", - "CFG_CENTER_LOGIC_OUTS_B4_2", - "CFG_CENTER_NE4BEG2_8", - "CFG_CENTER_SW4END3_18", - "CFG_CENTER_LH4_11", - "CFG_CENTER_IMUX13_19", - "CFG_CENTER_IMUX5_10", - "CFG_CENTER_IMUX18_17", - "CFG_CENTER_EE4C2_14", - "CFG_CENTER_WW2A2_2", - "CFG_CENTER_NW4A3_6", - "CFG_CENTER_WW4END1_15", - "CFG_CENTER_IMUX34_2", - "CFG_CENTER_IMUX18_0", - "CFG_CENTER_IMUX26_4", - "CFG_CENTER_IMUX27_13", - "CFG_CENTER_IMUX27_10", - "CFG_CENTER_SW4A3_9", - "CFG_CENTER_EE4BEG0_3", - "CFG_CENTER_BYP3_17", - "CFG_CENTER_FRAME_ECC_SYNDROME6", - "CFG_CENTER_EE4B2_18", - "CFG_CENTER_ICAP1_O1", - "CFG_CENTER_NW4A1_6", - "CFG_CENTER_EE2A0_19", - "CFG_CENTER_IMUX7_17", - "CFG_CENTER_WW4B0_6", - "CFG_CENTER_FRAME_ECC_FAR8", - "CFG_CENTER_SW4A3_7", - "CFG_CENTER_NW4A1_3", - "CFG_CENTER_ER1BEG3_4", - "CFG_CENTER_BYP4_10", - "CFG_CENTER_SE4C1_3", - "CFG_CENTER_WR1END1_14", - "CFG_CENTER_NE4C3_11", - "CFG_CENTER_IMUX33_13", - "CFG_CENTER_WL1END2_19", - "CFG_CENTER_IMUX42_12", - "CFG_CENTER_WW4END3_6", - "CFG_CENTER_BLOCK_OUTS_B0_15", - "CFG_CENTER_BSCAN2_CAPTURE", - "CFG_CENTER_CTRL0_7", - "CFG_CENTER_ICAP0_I21", - "CFG_CENTER_IMUX33_12", - "CFG_CENTER_IMUX5_12", - "CFG_CENTER_NE2A2_10", - "CFG_CENTER_NW4A1_1", - "CFG_CENTER_LOGIC_OUTS_B22_1", - "CFG_CENTER_FAN3_19", - "CFG_CENTER_CLK0_15", - "CFG_CENTER_LOGIC_OUTS_B5_12", - "CFG_CENTER_SW4END0_8", - "CFG_CENTER_SW4END3_13", - "CFG_CENTER_WW4C1_2", - "CFG_CENTER_WW2A0_16", - "CFG_CENTER_EE4B1_17", - "CFG_CENTER_LOGIC_OUTS_B2_12", - "CFG_CENTER_IMUX33_17", - "CFG_CENTER_WR1END1_17", - "CFG_CENTER_NW4END1_4", - "CFG_CENTER_EE4A2_8", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA3", - "CFG_CENTER_NW4END2_8", - "CFG_CENTER_LH2_8", - "CFG_CENTER_LOGIC_OUTS_B12_13", - "CFG_CENTER_BYP6_8", - "CFG_CENTER_IMUX32_13", - "CFG_CENTER_BYP1_11", - "CFG_CENTER_LOGIC_OUTS_B5_16", - "CFG_CENTER_IMUX43_9", - "CFG_CENTER_NW4A1_0", - "CFG_CENTER_LOGIC_OUTS_B7_8", - "CFG_CENTER_SW4A1_11", - "CFG_CENTER_CLK0_19", - "CFG_CENTER_LH4_9", - "CFG_CENTER_WW4A1_16", - "CFG_CENTER_SE4C1_19", - "CFG_CENTER_FAN7_15", - "CFG_CENTER_IMUX5_5", - "CFG_CENTER_IMUX20_7", - "CFG_CENTER_USR_ACCESS_DATA5", - "CFG_CENTER_USR_ACCESS_DATA23", - "CFG_CENTER_NW2A3_18", - "CFG_CENTER_LOGIC_OUTS_B13_6", - "CFG_CENTER_IMUX47_15", - "CFG_CENTER_FAN7_0", - "CFG_CENTER_NE4C0_16", - "CFG_CENTER_BLOCK_OUTS_B0_3", - "CFG_CENTER_IMUX2_8", - "CFG_CENTER_IMUX22_7", - "CFG_CENTER_BYP4_18", - "CFG_CENTER_FRAME_ECC_FAR0", - "CFG_CENTER_EE2BEG1_19", - "CFG_CENTER_LOGIC_OUTS_B2_0", - "CFG_CENTER_WW4B2_15", - "CFG_CENTER_EE2A2_5", - "CFG_CENTER_IMUX38_11", - "CFG_CENTER_WW4END0_2", - "CFG_CENTER_EE4C0_2", - "CFG_CENTER_NW2A0_4", - "CFG_CENTER_WL1END0_2", - "CFG_CENTER_BYP2_18", - "CFG_CENTER_IMUX34_6", - "CFG_CENTER_WW4END3_4", - "CFG_CENTER_EL1BEG3_1", - "CFG_CENTER_IMUX12_14", - "CFG_CENTER_WW2END3_12", - "CFG_CENTER_SE4C3_5", - "CFG_CENTER_BSCAN4_TMS", - "CFG_CENTER_EE4C3_2", - "CFG_CENTER_ICAP0_I24", - "CFG_CENTER_WR1END1_1", - "CFG_CENTER_NE2A1_1", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_BYP6_19", - "CFG_CENTER_SE4BEG0_19", - "CFG_CENTER_SE2A1_10", - "CFG_CENTER_EE4C3_7", - "CFG_CENTER_WW4B3_8", - "CFG_CENTER_ICAP0_O6", - "CFG_CENTER_NE4C0_15", - "CFG_CENTER_IMUX33_15", - "CFG_CENTER_IMUX29_5", - "CFG_CENTER_WR1END0_7", - "CFG_CENTER_CTRL0_19", - "CFG_CENTER_NE4BEG3_7", - "CFG_CENTER_ER1BEG3_12", - "CFG_CENTER_EE2A1_17", - "CFG_CENTER_IMUX31_17", - "CFG_CENTER_WW4C2_17", - "CFG_CENTER_LOGIC_OUTS_B16_12", - "CFG_CENTER_WW2END3_13", - "CFG_CENTER_BYP5_11", - "CFG_CENTER_WW4C2_3", - "CFG_CENTER_EE2A1_10", - "CFG_CENTER_EL1BEG3_13", - "CFG_CENTER_WW4END2_8", - "CFG_CENTER_LOGIC_OUTS_B15_3", - "CFG_CENTER_IMUX2_9", - "CFG_CENTER_IMUX0_7", - "CFG_CENTER_EE2A3_5", - "CFG_CENTER_NE4C0_3", - "CFG_CENTER_BYP5_14", - "CFG_CENTER_BYP4_0", - "CFG_CENTER_WW4A0_9", - "CFG_CENTER_SE4C2_3", - "CFG_CENTER_BYP0_4", - "CFG_CENTER_IMUX33_14", - "CFG_CENTER_LOGIC_OUTS_B19_18", - "CFG_CENTER_SE4C3_14", - "CFG_CENTER_EL1BEG3_5", - "CFG_CENTER_NW2A1_8", - "CFG_CENTER_LOGIC_OUTS_B13_16", - "CFG_CENTER_WL1END0_7", - "CFG_CENTER_BYP7_9", - "CFG_CENTER_IMUX8_0", - "CFG_CENTER_EE4C1_6", - "CFG_CENTER_EE4BEG3_8", - "CFG_CENTER_IMUX31_2", - "CFG_CENTER_LOGIC_OUTS_B23_7", - "CFG_CENTER_WW4END3_1", - "CFG_CENTER_IMUX29_12", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_LOGIC_OUTS_B1_2", - "CFG_CENTER_WR1END1_13", - "CFG_CENTER_ICAP0_O23", - "CFG_CENTER_BYP6_18", + "CFG_CENTER_LH10_1", "CFG_CENTER_NE4BEG2_17", - "CFG_CENTER_WW4B0_3", - "CFG_CENTER_IMUX7_12", - "CFG_CENTER_NE4C2_6", - "CFG_CENTER_IMUX4_14", - "CFG_CENTER_IMUX5_13", + "CFG_CENTER_SW2A0_13", + "CFG_CENTER_WR1END3_5", + "CFG_CENTER_BYP5_9", + "CFG_CENTER_WL1END1_3", + "CFG_CENTER_EE4B1_19", + "CFG_CENTER_BLOCK_OUTS_B2_14", + "CFG_CENTER_SW2A0_7", + "CFG_CENTER_LOGIC_OUTS_B12_18", + "CFG_CENTER_CTRL0_12", + "CFG_CENTER_BYP6_16", + "CFG_CENTER_IMUX42_2", + "CFG_CENTER_IMUX2_7", + "CFG_CENTER_EE4BEG0_12", + "CFG_CENTER_ER1BEG3_17", + "CFG_CENTER_LOGIC_OUTS_B5_1", + "CFG_CENTER_IMUX31_1", + "CFG_CENTER_SW4END2_13", + "CFG_CENTER_WW2END1_16", + "CFG_CENTER_NE2A3_0", + "CFG_CENTER_ICAP0_O8", + "CFG_CENTER_BYP1_9", + "CFG_CENTER_WW2END2_5", + "CFG_CENTER_SE4C0_9", + "CFG_CENTER_EE2A2_5", + "CFG_CENTER_IMUX2_1", + "CFG_CENTER_WR1END0_7", + "CFG_CENTER_WL1END1_1", + "CFG_CENTER_IMUX21_1", + "CFG_CENTER_LOGIC_OUTS_B18_0", + "CFG_CENTER_SE2A1_17", + "CFG_CENTER_LOGIC_OUTS_B11_5", + "CFG_CENTER_FAN4_19", + "CFG_CENTER_WW4A0_14", + "CFG_CENTER_IMUX17_18", + "CFG_CENTER_ICAP1_I14", + "CFG_CENTER_BYP4_12", + "CFG_CENTER_SW2A1_13", + "CFG_CENTER_LOGIC_OUTS_B16_14", + "CFG_CENTER_SW4END2_11", + "CFG_CENTER_WW4END2_1", + "CFG_CENTER_SW2A2_15", + "CFG_CENTER_IMUX13_9", + "CFG_CENTER_IMUX2_10", + "CFG_CENTER_LOGIC_OUTS_B7_4", + "CFG_CENTER_SW2A0_2", + "CFG_CENTER_IMUX3_7", + "CFG_CENTER_EE4A1_4", + "CFG_CENTER_BYP2_15", + "CFG_CENTER_IMUX44_15", + "CFG_CENTER_SE4BEG0_1", + "CFG_CENTER_EE4B3_6", + "CFG_CENTER_NE4C2_3", + "CFG_CENTER_LH8_6", + "CFG_CENTER_IMUX12_11", + "CFG_CENTER_IMUX47_4", + "CFG_CENTER_EE4C3_0", + "CFG_CENTER_NE4C1_3", + "CFG_CENTER_IMUX29_9", + "CFG_CENTER_IMUX29_6", + "CFG_CENTER_WW2END0_0", + "CFG_CENTER_FAN2_2", + "CFG_CENTER_FAN3_14", + "CFG_CENTER_WW4A1_13", + "CFG_CENTER_BSCAN1_UPDATE", + "CFG_CENTER_LOGIC_OUTS_B16_15", + "CFG_CENTER_EE4B3_17", + "CFG_CENTER_IMUX47_6", + "CFG_CENTER_FRAME_ECC_FAR21", + "CFG_CENTER_NE4BEG1_5", + "CFG_CENTER_IMUX47_3", + "CFG_CENTER_CK_IN7", + "CFG_CENTER_LH11_13", + "CFG_CENTER_NW4END1_5", + "CFG_CENTER_WW4END2_13", + "CFG_CENTER_LH5_8", + "CFG_CENTER_IMUX40_19", + "CFG_CENTER_LOGIC_OUTS_B6_16", + "CFG_CENTER_EE2A3_10", + "CFG_CENTER_NE4BEG3_10", + "CFG_CENTER_SW4END1_7", + "CFG_CENTER_BYP1_16", + "CFG_CENTER_NW4END3_7", + "CFG_CENTER_EE4BEG0_0", + "CFG_CENTER_IMUX35_14", + "CFG_CENTER_NW2A0_6", + "CFG_CENTER_WW4C2_5", + "CFG_CENTER_IMUX14_16", + "CFG_CENTER_IMUX11_0", + "CFG_CENTER_IMUX28_10", + "CFG_CENTER_IMUX44_7", + "CFG_CENTER_IMUX30_1", + "CFG_CENTER_NE2A2_12", + "CFG_CENTER_NW2A2_16", "CFG_CENTER_EE4BEG0_13", - "CFG_CENTER_LOGIC_OUTS_B0_14", - "CFG_CENTER_NE2A2_19", + "CFG_CENTER_IMUX46_10", + "CFG_CENTER_WW4A1_19", + "CFG_CENTER_IMUX17_7", + "CFG_CENTER_BLOCK_OUTS_B2_5", + "CFG_CENTER_SW4END1_2", + "CFG_CENTER_BYP1_7", + "CFG_CENTER_BYP0_7", + "CFG_CENTER_SW2A0_17", + "CFG_CENTER_IMUX1_11", + "CFG_CENTER_WW4C3_17", + "CFG_CENTER_LOGIC_OUTS_B15_19", + "CFG_CENTER_BLOCK_OUTS_B2_13", + "CFG_CENTER_SW2A1_8", + "CFG_CENTER_WW4END2_9", + "CFG_CENTER_EL1BEG3_7", + "CFG_CENTER_WW4END1_2", + "CFG_CENTER_WW4B3_4", + "CFG_CENTER_IMUX7_17", + "CFG_CENTER_SW2A1_2", + "CFG_CENTER_IMUX4_14", + "CFG_CENTER_SE2A0_19", + "CFG_CENTER_EE4B3_18", + "CFG_CENTER_CTRL0_17", + "CFG_CENTER_BYP0_6", + "CFG_CENTER_WW4A1_11", + "CFG_CENTER_WW4A2_10", + "CFG_CENTER_SW4END3_13", + "CFG_CENTER_BLOCK_OUTS_B1_16", + "CFG_CENTER_WW4END3_9", + "CFG_CENTER_LOGIC_OUTS_B7_2", + "CFG_CENTER_LOGIC_OUTS_B18_11", + "CFG_CENTER_IMUX32_4", + "CFG_CENTER_WW2A0_8", + "CFG_CENTER_IMUX20_6", + "CFG_CENTER_SE2A0_18", + "CFG_CENTER_SW2A2_1", + "CFG_CENTER_WL1END0_8", + "CFG_CENTER_LOGIC_OUTS_B1_2", + "CFG_CENTER_EL1BEG2_6", + "CFG_CENTER_EE4C1_17", + "CFG_CENTER_LOGIC_OUTS_B11_4", + "CFG_CENTER_IMUX9_0", + "CFG_CENTER_WR1END0_13", + "CFG_CENTER_BYP6_5", + "CFG_CENTER_FAN0_7", + "CFG_CENTER_WW4C1_17", + "CFG_CENTER_EE2BEG2_12", + "CFG_CENTER_EE4A1_8", + "CFG_CENTER_SE2A2_6", + "CFG_CENTER_LOGIC_OUTS_B7_3", + "CFG_CENTER_ICAP1_I5", + "CFG_CENTER_LOGIC_OUTS_B5_17", + "CFG_CENTER_BYP6_1", + "CFG_CENTER_IMUX21_6", + "CFG_CENTER_IMUX22_5", + "CFG_CENTER_IMUX28_14", + "CFG_CENTER_IMUX36_8", + "CFG_CENTER_LOGIC_OUTS_B9_0", + "CFG_CENTER_NE2A0_0", + "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", + "CFG_CENTER_LOGIC_OUTS_B3_3", + "CFG_CENTER_IMUX7_9", + "CFG_CENTER_FAN1_15", + "CFG_CENTER_FAN4_2", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA1", + "CFG_CENTER_LH5_0", + "CFG_CENTER_EE4C1_12", + "CFG_CENTER_EE4B1_12", + "CFG_CENTER_IMUX16_6", + "CFG_CENTER_ER1BEG3_8", + "CFG_CENTER_LOGIC_OUTS_B17_5", + "CFG_CENTER_FAN5_19", + "CFG_CENTER_WW2A3_17", + "CFG_CENTER_IMUX34_3", + "CFG_CENTER_NE4C3_4", + "CFG_CENTER_NW4END3_0", + "CFG_CENTER_IMUX7_5", + "CFG_CENTER_ICAP1_I7", + "CFG_CENTER_EE2BEG3_15", + "CFG_CENTER_LOGIC_OUTS_B14_8", + "CFG_CENTER_IMUX24_10", + "CFG_CENTER_SE2A1_11", + "CFG_CENTER_FAN5_17", + "CFG_CENTER_EE4BEG1_4", + "CFG_CENTER_IMUX14_9", + "CFG_CENTER_NW4END1_16", + "CFG_CENTER_NE4BEG0_8", + "CFG_CENTER_IMUX21_0", + "CFG_CENTER_LOGIC_OUTS_B11_15", + "CFG_CENTER_LOGIC_OUTS_B18_6", + "CFG_CENTER_IMUX12_4", + "CFG_CENTER_EL1BEG3_18", + "CFG_CENTER_EE2A2_18", + "CFG_CENTER_LOGIC_OUTS_B4_15", + "CFG_CENTER_NE4C2_8", + "CFG_CENTER_EE4C1_19", + "CFG_CENTER_SE4BEG2_12", + "CFG_CENTER_CK_IN6", + "CFG_CENTER_ICAP1_O17", + "CFG_CENTER_IMUX7_6", + "CFG_CENTER_WW4B3_19", + "CFG_CENTER_LOGIC_OUTS_B8_14", + "CFG_CENTER_IMUX31_17", + "CFG_CENTER_LOGIC_OUTS_B16_18", + "CFG_CENTER_EE4B1_5", + "CFG_CENTER_NE2A1_7", + "CFG_CENTER_LOGIC_OUTS_B4_10", + "CFG_CENTER_NW2A2_7", + "CFG_CENTER_IMUX0_0", + "CFG_CENTER_ICAP1_I26", + "CFG_CENTER_NE2A0_1", + "CFG_CENTER_WW4C1_6", + "CFG_CENTER_LH4_15", + "CFG_CENTER_LH5_9", + "CFG_CENTER_NW4END2_8", + "CFG_CENTER_IMUX0_15", + "CFG_CENTER_IMUX26_13", + "CFG_CENTER_SW4A1_16", + "CFG_CENTER_SE4C0_0", + "CFG_CENTER_IMUX29_3", + "CFG_CENTER_SW4END0_15", + "CFG_CENTER_IMUX39_9", + "CFG_CENTER_WW4C0_18", + "CFG_CENTER_IMUX38_4", + "CFG_CENTER_LOGIC_OUTS_B14_12", + "CFG_CENTER_CTRL1_7", + "CFG_CENTER_IMUX16_17", + "CFG_CENTER_LOGIC_OUTS_B6_13", + "CFG_CENTER_FRAME_ECC_SYNBIT2", + "CFG_CENTER_SE4C3_2", + "CFG_CENTER_WR1END3_1", + "CFG_CENTER_ICAP1_I0", + "CFG_CENTER_EE2BEG0_14", + "CFG_CENTER_BYP4_13", + "CFG_CENTER_WL1END0_0", + "CFG_CENTER_IMUX4_11", + "CFG_CENTER_IMUX40_13", + "CFG_CENTER_SW4A2_14", + "CFG_CENTER_NW4A0_10", + "CFG_CENTER_SW2A3_3", + "CFG_CENTER_ER1BEG1_12", + "CFG_CENTER_WR1END0_6", + "CFG_CENTER_WR1END2_17", + "CFG_CENTER_ER1BEG1_4", + "CFG_CENTER_ICAP0_I5", + "CFG_CENTER_EE4A2_13", + "CFG_CENTER_IMUX47_13", + "CFG_CENTER_IMUX42_5", + "CFG_CENTER_WW2END3_5", + "CFG_CENTER_FAN2_17", + "CFG_CENTER_LOGIC_OUTS_B10_15", + "CFG_CENTER_IMUX10_0", + "CFG_CENTER_EE2A3_5", + "CFG_CENTER_NW4END3_3", + "CFG_CENTER_IMUX8_18", + "CFG_CENTER_IMUX46_3", + "CFG_CENTER_NE4BEG2_2", + "CFG_CENTER_EE4A1_5", + "CFG_CENTER_LOGIC_OUTS_B20_2", + "CFG_CENTER_NE4BEG0_2", + "CFG_CENTER_CFG_IO_ACCESS_TDO", + "CFG_CENTER_LOGIC_OUTS_B6_15", + "CFG_CENTER_NW4A0_13", + "CFG_CENTER_WW4C2_19", + "CFG_CENTER_WW4C2_4", + "CFG_CENTER_IMUX12_19", + "CFG_CENTER_BSCAN1_TDI", + "CFG_CENTER_WW4END1_10", + "CFG_CENTER_LOGIC_OUTS_B0_3", + "CFG_CENTER_CTRL1_6", + "CFG_CENTER_ER1BEG0_8", + "CFG_CENTER_ICAP1_I25", + "CFG_CENTER_EE4BEG2_11", + "CFG_CENTER_SE2A1_5", + "CFG_CENTER_SW4A2_10", + "CFG_CENTER_FAN5_7", + "CFG_CENTER_NE4C0_7", + "CFG_CENTER_SW4A0_16", + "CFG_CENTER_LOGIC_OUTS_B3_5", + "CFG_CENTER_IMUX3_18", + "CFG_CENTER_SW2A2_4", + "CFG_CENTER_IMUX12_15", + "CFG_CENTER_WW4A1_10", + "CFG_CENTER_SW4END2_4", + "CFG_CENTER_LOGIC_OUTS_B13_6", + "CFG_CENTER_WR1END0_10", + "CFG_CENTER_NE2A2_6", + "CFG_CENTER_IMUX4_12", + "CFG_CENTER_NW4END0_17", + "CFG_CENTER_LOGIC_OUTS_B17_4", + "CFG_CENTER_LOGIC_OUTS_B3_13", + "CFG_CENTER_SE4BEG0_2", + "CFG_CENTER_BLOCK_OUTS_B0_7", + "CFG_CENTER_EE4C0_14", + "CFG_CENTER_BLOCK_OUTS_B0_13", + "CFG_CENTER_EE4C3_12", + "CFG_CENTER_BYP7_5", + "CFG_CENTER_NE4BEG3_1", + "CFG_CENTER_FAN0_6", + "CFG_CENTER_NE4BEG2_9", + "CFG_CENTER_IMUX7_14", + "CFG_CENTER_FAN4_16", + "CFG_CENTER_LOGIC_OUTS_B22_17", + "CFG_CENTER_NE4C3_8", + "CFG_CENTER_IMUX28_16", + "CFG_CENTER_LOGIC_OUTS_B22_16", + "CFG_CENTER_LH2_1", + "CFG_CENTER_EE4C0_10", + "CFG_CENTER_FAN2_14", + "CFG_CENTER_WW4B3_13", + "CFG_CENTER_EL1BEG2_0", + "CFG_CENTER_LH1_12", + "CFG_CENTER_WW4END3_6", + "CFG_CENTER_CAPTURE_CLK", + "CFG_CENTER_NE2A3_1", + "CFG_CENTER_NE4BEG0_1", + "CFG_CENTER_NW4END2_0", + "CFG_CENTER_WR1END2_11", + "CFG_CENTER_EL1BEG1_19", + "CFG_CENTER_WW4A3_6", + "CFG_CENTER_IMUX24_11", + "CFG_CENTER_WL1END3_17", + "CFG_CENTER_LOGIC_OUTS_B20_13", + "CFG_CENTER_IMUX33_10", + "CFG_CENTER_IMUX22_9", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA31", + "CFG_CENTER_ICAP1_I17", + "CFG_CENTER_EE4B0_7", + "CFG_CENTER_IMUX26_17", + "CFG_CENTER_EE4BEG2_13", + "CFG_CENTER_BLOCK_OUTS_B0_12", + "CFG_CENTER_IMUX17_4", + "CFG_CENTER_NW2A0_1", + "CFG_CENTER_NE4BEG1_0", + "CFG_CENTER_NE4C2_2", + "CFG_CENTER_ICAP1_O22", + "CFG_CENTER_IMUX41_10", + "CFG_CENTER_IMUX7_2", + "CFG_CENTER_WW4B1_14", + "CFG_CENTER_SE2A1_14", + "CFG_CENTER_LH12_5", + "CFG_CENTER_WW4END1_6", + "CFG_CENTER_IMUX39_13", + "CFG_CENTER_EE4A1_19", + "CFG_CENTER_WL1END0_10", + "CFG_CENTER_SE4C2_10", + "CFG_CENTER_IMUX9_6", + "CFG_CENTER_WW2A2_15", + "CFG_CENTER_IMUX23_12", + "CFG_CENTER_LOGIC_OUTS_B10_12", + "CFG_CENTER_LOGIC_OUTS_B19_16", + "CFG_CENTER_LOGIC_OUTS_B5_2", + "CFG_CENTER_IMUX8_2", + "CFG_CENTER_NW4A2_8", + "CFG_CENTER_WW2A0_17", + "CFG_CENTER_FAN0_5", + "CFG_CENTER_FAN7_1", + "CFG_CENTER_CK_BUFRCLK2", + "CFG_CENTER_WW2A3_2", + "CFG_CENTER_EE2BEG1_5", + "CFG_CENTER_NE4BEG2_15", + "CFG_CENTER_BYP7_7", + "CFG_CENTER_IMUX23_6", + "CFG_CENTER_NW2A3_17", + "CFG_CENTER_WW4A2_18", + "CFG_CENTER_NW4A2_19", + "CFG_CENTER_IMUX24_9", + "CFG_CENTER_LOGIC_OUTS_B19_12", + "CFG_CENTER_FAN2_12", + "CFG_CENTER_EL1BEG2_10", + "CFG_CENTER_IMUX46_13", + "CFG_CENTER_WL1END1_8", + "CFG_CENTER_LOGIC_OUTS_B4_3", + "CFG_CENTER_SE2A0_16", + "CFG_CENTER_SW4END1_0", + "CFG_CENTER_LH3_0", + "CFG_CENTER_SE4C2_15", + "CFG_CENTER_LH2_2", + "CFG_CENTER_LOGIC_OUTS_B6_2", + "CFG_CENTER_IMUX4_8", + "CFG_CENTER_NE2A3_17", + "CFG_CENTER_FAN1_14", + "CFG_CENTER_IMUX13_1", + "CFG_CENTER_LOGIC_OUTS_B2_19", + "CFG_CENTER_WR1END1_18", + "CFG_CENTER_WW4C1_3", + "CFG_CENTER_SE2A3_11", + "CFG_CENTER_IMUX5_8", + "CFG_CENTER_IMUX40_11", + "CFG_CENTER_SE4C0_5", + "CFG_CENTER_SE2A3_6", + "CFG_CENTER_SE4C2_4", + "CFG_CENTER_WW2A2_17", + "CFG_CENTER_WW2END0_17", + "CFG_CENTER_LH8_4", + "CFG_CENTER_NW4A0_17", + "CFG_CENTER_SW2A3_9", + "CFG_CENTER_EE2A0_19", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA22", + "CFG_CENTER_FRAME_ECC_SYNDROME0", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA2", + "CFG_CENTER_LOGIC_OUTS_B16_8", + "CFG_CENTER_EE4A0_10", + "CFG_CENTER_LOGIC_OUTS_B2_10", + "CFG_CENTER_MID_USR_ACCESS_DATA5", + "CFG_CENTER_LH9_7", + "CFG_CENTER_LOGIC_OUTS_B11_7", + "CFG_CENTER_CLK1_16", + "CFG_CENTER_SW4END3_5", + "CFG_CENTER_ICAP0_I9", + "CFG_CENTER_LH4_17", + "CFG_CENTER_LOGIC_OUTS_B17_10", + "CFG_CENTER_IMUX1_7", + "CFG_CENTER_LOGIC_OUTS_B17_18", + "CFG_CENTER_IMUX23_3", + "CFG_CENTER_EE4C0_5", + "CFG_CENTER_NE4C2_9", + "CFG_CENTER_EL1BEG3_17", + "CFG_CENTER_IMUX35_12", + "CFG_CENTER_LOGIC_OUTS_B11_19", + "CFG_CENTER_NW4END2_2", + "CFG_CENTER_BYP3_12", + "CFG_CENTER_IMUX3_14", + "CFG_CENTER_LOGIC_OUTS_B22_15", + "CFG_CENTER_EE4A3_18", + "CFG_CENTER_BYP5_17", + "CFG_CENTER_IMUX17_8", + "CFG_CENTER_LOGIC_OUTS_B15_5", + "CFG_CENTER_NE4BEG1_8", + "CFG_CENTER_IMUX35_4", + "CFG_CENTER_NE4BEG0_7", + "CFG_CENTER_BLOCK_OUTS_B3_8", + "CFG_CENTER_EE2BEG2_4", + "CFG_CENTER_IMUX1_5", + "CFG_CENTER_NE4BEG2_14", + "CFG_CENTER_WW4END3_4", + "CFG_CENTER_IMUX2_9", + "CFG_CENTER_FAN7_7", + "CFG_CENTER_EE4BEG3_3", + "CFG_CENTER_EE4B2_6", + "CFG_CENTER_FAN6_6", + "CFG_CENTER_SW4END0_0", + "CFG_CENTER_WW4B3_1", + "CFG_CENTER_EE4A3_13", + "CFG_CENTER_EE4A0_5", + "CFG_CENTER_BYP6_10", + "CFG_CENTER_WL1END1_16", + "CFG_CENTER_NW4A0_4", + "CFG_CENTER_NE4BEG0_4", + "CFG_CENTER_IMUX13_10", + "CFG_CENTER_EE4BEG1_14", + "CFG_CENTER_LOGIC_OUTS_B13_10", + "CFG_CENTER_BYP4_5", + "CFG_CENTER_EE2A1_13", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA16", + "CFG_CENTER_EL1BEG0_9", + "CFG_CENTER_IMUX2_5", + "CFG_CENTER_CK_IN3", + "CFG_CENTER_BSCAN2_TDO", + "CFG_CENTER_IMUX35_5", + "CFG_CENTER_IMUX23_10", + "CFG_CENTER_NW2A3_14", + "CFG_CENTER_IMUX40_0", + "CFG_CENTER_NW4END3_11", + "CFG_CENTER_NE2A1_6", + "CFG_CENTER_WW4A2_7", + "CFG_CENTER_ICAP0_O29", + "CFG_CENTER_LOGIC_OUTS_B1_18", + "CFG_CENTER_LOGIC_OUTS_B21_14", + "CFG_CENTER_EE4C0_11", + "CFG_CENTER_SE4BEG0_10", + "CFG_CENTER_ER1BEG3_13", + "CFG_CENTER_EE2BEG0_10", + "CFG_CENTER_IMUX40_9", + "CFG_CENTER_IMUX9_7", + "CFG_CENTER_LOGIC_OUTS_B13_12", + "CFG_CENTER_EE2BEG1_3", + "CFG_CENTER_NE4C2_16", + "CFG_CENTER_WW4A0_18", + "CFG_CENTER_IMUX27_13", + "CFG_CENTER_BSCAN1_CAPTURE", + "CFG_CENTER_LOGIC_OUTS_B5_19", + "CFG_CENTER_WR1END3_4", + "CFG_CENTER_NE4BEG2_13", + "CFG_CENTER_IMUX11_10", + "CFG_CENTER_IMUX39_15", + "CFG_CENTER_EE2A2_15", + "CFG_CENTER_IMUX36_15", + "CFG_CENTER_IMUX25_13", + "CFG_CENTER_CK_IN5", + "CFG_CENTER_EE4A3_0", + "CFG_CENTER_EE4A1_14", + "CFG_CENTER_ICAP1_I1", + "CFG_CENTER_WW4A0_2", + "CFG_CENTER_LOGIC_OUTS_B10_17", + "CFG_CENTER_LOGIC_OUTS_B20_9", + "CFG_CENTER_ICAP0_O4", + "CFG_CENTER_EL1BEG3_16", + "CFG_CENTER_EE2BEG3_18", + "CFG_CENTER_LH5_4", + "CFG_CENTER_BYP1_2", + "CFG_CENTER_ICAP1_I31", + "CFG_CENTER_LH5_16", + "CFG_CENTER_LH12_14", + "CFG_CENTER_IMUX9_16", + "CFG_CENTER_BSCAN1_TCK", + "CFG_CENTER_EL1BEG2_2", + "CFG_CENTER_WW4A2_2", + "CFG_CENTER_SE4BEG3_2", + "CFG_CENTER_LOGIC_OUTS_B15_18", + "CFG_CENTER_LOGIC_OUTS_B20_1", + "CFG_CENTER_ER1BEG0_10", + "CFG_CENTER_NW4A1_0", + "CFG_CENTER_WW4C1_14", + "CFG_CENTER_LH2_3", + "CFG_CENTER_CLK1_9", + "CFG_CENTER_WW2END0_7", + "CFG_CENTER_SE4C1_16", + "CFG_CENTER_WW2END1_3", + "CFG_CENTER_FAN5_12", + "CFG_CENTER_LOGIC_OUTS_B21_13", + "CFG_CENTER_WW4B0_10", + "CFG_CENTER_EE4B3_7", + "CFG_CENTER_LOGIC_OUTS_B23_2", + "CFG_CENTER_SW2A3_4", + "CFG_CENTER_ER1BEG1_1", + "CFG_CENTER_BYP3_18", + "CFG_CENTER_IMUX33_17", + "CFG_CENTER_EE4A3_3", + "CFG_CENTER_ICAP0_O30", + "CFG_CENTER_LH6_15", + "CFG_CENTER_SE4BEG3_11", + "CFG_CENTER_IMUX7_4", + "CFG_CENTER_BYP2_1", + "CFG_CENTER_SW4END2_17", + "CFG_CENTER_IMUX8_6", + "CFG_CENTER_NE2A0_11", + "CFG_CENTER_LOGIC_OUTS_B13_0", + "CFG_CENTER_IMUX4_6", + "CFG_CENTER_EL1BEG0_0", + "CFG_CENTER_NW4A3_18", + "CFG_CENTER_IMUX3_8", + "CFG_CENTER_CLK0_8", + "CFG_CENTER_WW2A2_9", + "CFG_CENTER_LH4_0", + "CFG_CENTER_SW4END3_0", + "CFG_CENTER_LH2_9", + "CFG_CENTER_IMUX13_18", + "CFG_CENTER_NW4A0_0", + "CFG_CENTER_BLOCK_OUTS_B0_17", + "CFG_CENTER_WW4END3_17", + "CFG_CENTER_IMUX42_6", + "CFG_CENTER_FRAME_ECC_FAR3", + "CFG_CENTER_ICAP0_O27", + "CFG_CENTER_IMUX37_12", + "CFG_CENTER_EE2BEG3_12", + "CFG_CENTER_ICAP1_O31", + "CFG_CENTER_NE2A1_10", + "CFG_CENTER_IMUX13_2", + "CFG_CENTER_LOGIC_OUTS_B21_11", + "CFG_CENTER_CFG_IO_ACCESS_MODE1", + "CFG_CENTER_EE4B2_7", + "CFG_CENTER_IMUX21_7", + "CFG_CENTER_EE4BEG1_8", + "CFG_CENTER_IMUX1_6", + "CFG_CENTER_BSCAN4_DRCK", + "CFG_CENTER_WR1END3_13", + "CFG_CENTER_NW4END2_3", + "CFG_CENTER_SE4C0_6", + "CFG_CENTER_IMUX14_8", + "CFG_CENTER_BSCAN3_SEL", + "CFG_CENTER_WW4B2_7", + "CFG_CENTER_IMUX16_7", + "CFG_CENTER_FAN4_4", + "CFG_CENTER_IMUX9_3", + "CFG_CENTER_WW2END2_18", + "CFG_CENTER_IMUX43_6", + "CFG_CENTER_LH6_6", + "CFG_CENTER_ER1BEG1_14", + "CFG_CENTER_EL1BEG3_1", + "CFG_CENTER_NW4A3_15", + "CFG_CENTER_BLOCK_OUTS_B0_10", + "CFG_CENTER_IMUX18_12", + "CFG_CENTER_LOGIC_OUTS_B7_0", + "CFG_CENTER_NW2A2_9", + "CFG_CENTER_LOGIC_OUTS_B5_4", + "CFG_CENTER_LOGIC_OUTS_B7_13", + "CFG_CENTER_IMUX33_5", + "CFG_CENTER_NE4BEG0_17", + "CFG_CENTER_BYP3_13", + "CFG_CENTER_LH12_18", + "CFG_CENTER_EL1BEG2_15", + "CFG_CENTER_IMUX7_16", + "CFG_CENTER_LOGIC_OUTS_B23_12", + "CFG_CENTER_NW4END0_9", + "CFG_CENTER_SE4BEG0_0", + "CFG_CENTER_BSCAN4_TDO", + "CFG_CENTER_NE4C3_19", + "CFG_CENTER_SW2A0_8", + "CFG_CENTER_SW4A2_0", + "CFG_CENTER_NW4END1_18", + "CFG_CENTER_LOGIC_OUTS_B23_0", + "CFG_CENTER_NW4A3_19", + "CFG_CENTER_BLOCK_OUTS_B3_5", + "CFG_CENTER_LH9_10", + "CFG_CENTER_EE4A3_6", + "CFG_CENTER_IMUX30_8", + "CFG_CENTER_BLOCK_OUTS_B1_3", + "CFG_CENTER_IMUX27_16", + "CFG_CENTER_IMUX12_10", + "CFG_CENTER_NE4BEG3_2", + "CFG_CENTER_EE4C1_7", + "CFG_CENTER_SW4END0_13", + "CFG_CENTER_FAN3_15", + "CFG_CENTER_CTRL1_15", + "CFG_CENTER_EE4A0_0", + "CFG_CENTER_WW4A3_10", + "CFG_CENTER_WW2A0_10", + "CFG_CENTER_WW4C2_16", + "CFG_CENTER_NE2A0_2", + "CFG_CENTER_LH11_4", + "CFG_CENTER_EE4C1_9", + "CFG_CENTER_SE4C0_17", + "CFG_CENTER_LOGIC_OUTS_B9_19", + "CFG_CENTER_IMUX10_17", + "CFG_CENTER_BYP3_15", + "CFG_CENTER_IMUX10_12", + "CFG_CENTER_LOGIC_OUTS_B6_1", + "CFG_CENTER_NW2A2_3", + "CFG_CENTER_BYP3_8", + "CFG_CENTER_NW4END1_19", + "CFG_CENTER_NW2A0_3", + "CFG_CENTER_EE4BEG3_9", + "CFG_CENTER_BLOCK_OUTS_B1_7", + "CFG_CENTER_FAN6_7", + "CFG_CENTER_NW2A1_15", + "CFG_CENTER_EE4BEG1_2", + "CFG_CENTER_WW4A1_14", + "CFG_CENTER_IMUX40_16", + "CFG_CENTER_NW2A0_11", + "CFG_CENTER_IMUX6_6", + "CFG_CENTER_IMUX27_0", + "CFG_CENTER_WR1END2_8", + "CFG_CENTER_SW2A0_9", + "CFG_CENTER_LOGIC_OUTS_B20_7", + "CFG_CENTER_NE2A2_0", + "CFG_CENTER_EE4BEG1_16", + "CFG_CENTER_IMUX12_17", + "CFG_CENTER_IMUX2_12", + "CFG_CENTER_SW4A0_3", + "CFG_CENTER_EE4BEG2_14", + "CFG_CENTER_NW4A3_6", + "CFG_CENTER_WL1END2_12", + "CFG_CENTER_LOGIC_OUTS_B4_0", + "CFG_CENTER_WR1END1_17", + "CFG_CENTER_BLOCK_OUTS_B3_12", + "CFG_CENTER_EE4A3_19", + "CFG_CENTER_LH11_12", + "CFG_CENTER_NW4END0_1", + "CFG_CENTER_IMUX43_2", + "CFG_CENTER_WW4A3_1", + "CFG_CENTER_WW4END3_8", + "CFG_CENTER_BLOCK_OUTS_B2_1", + "CFG_CENTER_LOGIC_OUTS_B0_7", + "CFG_CENTER_IMUX3_13", + "CFG_CENTER_LH5_17", + "CFG_CENTER_ICAP1_O6", + "CFG_CENTER_IMUX9_19", + "CFG_CENTER_IMUX45_16", + "CFG_CENTER_LOGIC_OUTS_B13_4", + "CFG_CENTER_EE4A1_18", + "CFG_CENTER_EE4B2_15", + "CFG_CENTER_IMUX37_17", + "CFG_CENTER_EE4B0_1", + "CFG_CENTER_IMUX15_4", + "CFG_CENTER_EE2A2_16", + "CFG_CENTER_USR_ACCESS_DATA17", + "CFG_CENTER_EE4BEG2_9", + "CFG_CENTER_IMUX9_5", + "CFG_CENTER_BLOCK_OUTS_B3_2", + "CFG_CENTER_IMUX47_9", + "CFG_CENTER_NW4A2_10", + "CFG_CENTER_SE4BEG3_19", + "CFG_CENTER_EE4A1_0", + "CFG_CENTER_EE2A2_11", + "CFG_CENTER_SW4END0_2", + "CFG_CENTER_IMUX11_1", + "CFG_CENTER_IMUX24_4", + "CFG_CENTER_SE4C2_5", + "CFG_CENTER_FRAME_ECC_FAR4", + "CFG_CENTER_ER1BEG0_14", + "CFG_CENTER_EL1BEG0_13", + "CFG_CENTER_IMUX42_18", + "CFG_CENTER_BYP3_7", + "CFG_CENTER_NW4A3_5", + "CFG_CENTER_IMUX0_18", + "CFG_CENTER_EL1BEG0_17", + "CFG_CENTER_LH12_9", + "CFG_CENTER_CK_IN0", + "CFG_CENTER_LOGIC_OUTS_B3_19", + "CFG_CENTER_IMUX26_12", + "CFG_CENTER_EE4A0_15", + "CFG_CENTER_LH6_14", + "CFG_CENTER_IMUX17_10", + "CFG_CENTER_NW4END0_16", + "CFG_CENTER_BYP3_4", + "CFG_CENTER_FRAME_ECC_FAR15", + "CFG_CENTER_WW2A3_10", + "CFG_CENTER_ICAP0_I18", + "CFG_CENTER_IMUX25_18", + "CFG_CENTER_NE2A0_6", + "CFG_CENTER_LOGIC_OUTS_B5_10", + "CFG_CENTER_IMUX40_12", + "CFG_CENTER_NE2A1_3", + "CFG_CENTER_SE4BEG3_18", + "CFG_CENTER_SW4A2_15", + "CFG_CENTER_NE4C2_5", + "CFG_CENTER_LOGIC_OUTS_B13_3", + "CFG_CENTER_EE4BEG0_10", + "CFG_CENTER_SE2A0_6", + "CFG_CENTER_NW4A0_8", + "CFG_CENTER_WL1END3_11", + "CFG_CENTER_BSCAN4_TMS", + "CFG_CENTER_WW2END1_5", + "CFG_CENTER_LOGIC_OUTS_B15_7", + "CFG_CENTER_CLK0_1", + "CFG_CENTER_WW4A3_16", + "CFG_CENTER_LOGIC_OUTS_B19_19", + "CFG_CENTER_IMUX13_19", + "CFG_CENTER_STARTUP_CLK", + "CFG_CENTER_LOGIC_OUTS_B20_19", + "CFG_CENTER_LOGIC_OUTS_B15_0", + "CFG_CENTER_LOGIC_OUTS_B0_2", + "CFG_CENTER_NE2A1_8", + "CFG_CENTER_EE4B3_8", + "CFG_CENTER_EL1BEG1_15", + "CFG_CENTER_WW2A2_13", + "CFG_CENTER_NE2A2_4", + "CFG_CENTER_SE2A1_2", + "CFG_CENTER_IMUX22_2", + "CFG_CENTER_NW2A1_1", + "CFG_CENTER_IMUX36_0", + "CFG_CENTER_ICAP1_O19", + "CFG_CENTER_NW4A0_1", + "CFG_CENTER_IMUX16_12", + "CFG_CENTER_NW2A1_14", + "CFG_CENTER_EE4B0_16", + "CFG_CENTER_LH4_4", + "CFG_CENTER_ER1BEG0_0", + "CFG_CENTER_EE4BEG3_5", + "CFG_CENTER_NE4C2_14", + "CFG_CENTER_IMUX19_1", + "CFG_CENTER_BLOCK_OUTS_B2_7", + "CFG_CENTER_CTRL1_4", + "CFG_CENTER_ICAP1_O14", + "CFG_CENTER_WW2A1_6", + "CFG_CENTER_ICAP1_O20", + "CFG_CENTER_FAN4_8", + "CFG_CENTER_IMUX37_3", + "CFG_CENTER_LH1_16", + "CFG_CENTER_LOGIC_OUTS_B20_3", + "CFG_CENTER_IMUX10_14", + "CFG_CENTER_FRAME_ECC_SYNDROME11", + "CFG_CENTER_WW4C0_2", + "CFG_CENTER_NW2A1_17", + "CFG_CENTER_LOGIC_OUTS_B1_19", + "CFG_CENTER_LOGIC_OUTS_B21_9", + "CFG_CENTER_WL1END2_6", + "CFG_CENTER_CFG_IO_ACCESS_MODE2", + "CFG_CENTER_EL1BEG1_16", + "CFG_CENTER_WW2END1_19", + "CFG_CENTER_EE4A2_10", + "CFG_CENTER_BYP6_0", + "CFG_CENTER_WW2END1_13", + "CFG_CENTER_SE4BEG2_2", + "CFG_CENTER_IMUX1_14", + "CFG_CENTER_IMUX15_9", + "CFG_CENTER_MID_USR_ACCESS_DATA6", + "CFG_CENTER_LOGIC_OUTS_B5_18", + "CFG_CENTER_SW4A3_19", + "CFG_CENTER_EL1BEG0_10", + "CFG_CENTER_LOGIC_OUTS_B18_7", + "CFG_CENTER_LH2_8", + "CFG_CENTER_LOGIC_OUTS_B23_8", + "CFG_CENTER_IMUX1_0", + "CFG_CENTER_LOGIC_OUTS_B21_16", + "CFG_CENTER_EE4B0_17", + "CFG_CENTER_IMUX30_15", + "CFG_CENTER_WR1END2_6", + "CFG_CENTER_WW4A3_13", + "CFG_CENTER_SW4A2_9", + "CFG_CENTER_WW4B2_11", + "CFG_CENTER_EE4BEG1_10", + "CFG_CENTER_FAN6_10", + "CFG_CENTER_WW2END1_1", + "CFG_CENTER_IMUX25_0", + "CFG_CENTER_IMUX40_17", + "CFG_CENTER_EE2A3_18", + "CFG_CENTER_WW4END0_11", + "CFG_CENTER_LOGIC_OUTS_B3_12", + "CFG_CENTER_NW4END0_11", + "CFG_CENTER_LOGIC_OUTS_B10_11", + "CFG_CENTER_BLOCK_OUTS_B3_9", + "CFG_CENTER_USR_ACCESS_DATA26", + "CFG_CENTER_SW4END3_6", + "CFG_CENTER_LOGIC_OUTS_B20_8", + "CFG_CENTER_FRAME_ECC_FAR20", + "CFG_CENTER_SW4END1_10", + "CFG_CENTER_IMUX45_13", + "CFG_CENTER_LOGIC_OUTS_B12_3", + "CFG_CENTER_SW4END2_0", + "CFG_CENTER_SE4BEG2_16", + "CFG_CENTER_WR1END2_1", + "CFG_CENTER_IMUX15_6", + "CFG_CENTER_SE4BEG0_8", + "CFG_CENTER_NW4END0_4", + "CFG_CENTER_EE4C3_6", + "CFG_CENTER_WR1END1_15", + "CFG_CENTER_SW2A0_0", + "CFG_CENTER_ER1BEG1_6", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA0", + "CFG_CENTER_IMUX26_11", + "CFG_CENTER_IMUX4_15", + "CFG_CENTER_WR1END0_15", + "CFG_CENTER_IMUX13_3", + "CFG_CENTER_EE4A0_19", + "CFG_CENTER_WW2A2_10", + "CFG_CENTER_BSCAN1_RUNTEST", + "CFG_CENTER_EE4B0_18", + "CFG_CENTER_WL1END0_1", + "CFG_CENTER_WW2END3_13", + "CFG_CENTER_EE2A0_0", + "CFG_CENTER_BSCAN2_CAPTURE", + "CFG_CENTER_LOGIC_OUTS_B17_1", + "CFG_CENTER_LOGIC_OUTS_B9_18", + "CFG_CENTER_BYP7_9", + "CFG_CENTER_IMUX30_16", + "CFG_CENTER_EE4B2_5", + "CFG_CENTER_SW4A1_3", + "CFG_CENTER_BLOCK_OUTS_B2_15", + "CFG_CENTER_IMUX3_0", + "CFG_CENTER_IMUX9_15", + "CFG_CENTER_IMUX47_11", + "CFG_CENTER_SW4A3_6", + "CFG_CENTER_BYP7_2", + "CFG_CENTER_LOGIC_OUTS_B14_0", + "CFG_CENTER_SW2A0_5", + "CFG_CENTER_LOGIC_OUTS_B2_8", + "CFG_CENTER_LH8_0", + "CFG_CENTER_LH11_11", + "CFG_CENTER_IMUX1_12", + "CFG_CENTER_NW2A2_19", + "CFG_CENTER_EE4A2_18", + "CFG_CENTER_EE4C1_14", + "CFG_CENTER_USR_ACCESS_DATA5", + "CFG_CENTER_NE2A2_18", + "CFG_CENTER_ICAP1_O12", + "CFG_CENTER_IMUX3_1", + "CFG_CENTER_CFG_IO_ACCESS_MASTER", + "CFG_CENTER_ER1BEG1_13", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA21", + "CFG_CENTER_WW4B0_9", + "CFG_CENTER_NE2A2_9", + "CFG_CENTER_SW4A1_12", + "CFG_CENTER_WW4B2_15", + "CFG_CENTER_BLOCK_OUTS_B1_13", + "CFG_CENTER_NW2A3_12", + "CFG_CENTER_SW4END0_11", + "CFG_CENTER_NE4C3_17", + "CFG_CENTER_EL1BEG0_5", + "CFG_CENTER_EE2BEG3_16", + "CFG_CENTER_SE4C1_12", + "CFG_CENTER_LH4_2", + "CFG_CENTER_ER1BEG3_6", + "CFG_CENTER_ER1BEG1_2", + "CFG_CENTER_EE2A1_5", + "CFG_CENTER_EE4A1_7", + "CFG_CENTER_SE2A1_13", + "CFG_CENTER_LOGIC_OUTS_B19_2", + "CFG_CENTER_CTRL1_5", + "CFG_CENTER_IMUX44_12", + "CFG_CENTER_ER1BEG1_7", + "CFG_CENTER_IMUX42_11", + "CFG_CENTER_WR1END0_5", + "CFG_CENTER_EE2A2_9", + "CFG_CENTER_IMUX37_10", + "CFG_CENTER_EE4B2_17", + "CFG_CENTER_EE2BEG0_0", + "CFG_CENTER_LOGIC_OUTS_B13_18", + "CFG_CENTER_EE4B2_14", + "CFG_CENTER_WW4END1_18", + "CFG_CENTER_CTRL1_3", + "CFG_CENTER_ER1BEG3_7", + "CFG_CENTER_IMUX47_16", + "CFG_CENTER_EE2A0_4", + "CFG_CENTER_NW2A1_11", + "CFG_CENTER_WW4B1_13", + "CFG_CENTER_WW4A0_1", + "CFG_CENTER_IMUX40_2", + "CFG_CENTER_IMUX43_4", + "CFG_CENTER_WW4C2_13", + "CFG_CENTER_LOGIC_OUTS_B21_10", + "CFG_CENTER_IMUX29_1", + "CFG_CENTER_IMUX34_14", + "CFG_CENTER_SE4C3_14", + "CFG_CENTER_IMUX20_19", + "CFG_CENTER_NE4C2_6", + "CFG_CENTER_LH3_17", + "CFG_CENTER_LOGIC_OUTS_B2_16", + "CFG_CENTER_WW4A0_17", + "CFG_CENTER_NE2A0_8", + "CFG_CENTER_EE4C1_13", + "CFG_CENTER_FAN5_4", + "CFG_CENTER_EE4A2_7", + "CFG_CENTER_IMUX45_9", + "CFG_CENTER_FAN2_10", + "CFG_CENTER_BLOCK_OUTS_B1_15", + "CFG_CENTER_IMUX27_2", + "CFG_CENTER_EE4B2_10", + "CFG_CENTER_EE2BEG0_12", + "CFG_CENTER_CK_IN11", + "CFG_CENTER_WW2A2_11", + "CFG_CENTER_SE4BEG1_2", + "CFG_CENTER_LOGIC_OUTS_B17_17", + "CFG_CENTER_WR1END2_19", + "CFG_CENTER_WW4B1_1", + "CFG_CENTER_LH12_15", + "CFG_CENTER_IMUX42_8", + "CFG_CENTER_NW4END2_1", + "CFG_CENTER_SW4A1_9", + "CFG_CENTER_IMUX27_6", + "CFG_CENTER_IMUX18_5", + "CFG_CENTER_IMUX9_12", + "CFG_CENTER_IMUX17_3", + "CFG_CENTER_EE4C1_15", + "CFG_CENTER_BLOCK_OUTS_B3_4", + "CFG_CENTER_NW4A0_3", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA24", + "CFG_CENTER_EE4A3_15", + "CFG_CENTER_IMUX16_19", + "CFG_CENTER_NE4BEG2_0", + "CFG_CENTER_SE4BEG0_13", + "CFG_CENTER_CTRL0_10", + "CFG_CENTER_SW4A1_14", + "CFG_CENTER_NE2A1_13", + "CFG_CENTER_EE4A0_12", + "CFG_CENTER_IMUX29_8", + "CFG_CENTER_EE4B0_15", + "CFG_CENTER_IMUX24_1", + "CFG_CENTER_LOGIC_OUTS_B20_12", + "CFG_CENTER_LH8_15", + "CFG_CENTER_NE2A1_5", + "CFG_CENTER_LH2_10", + "CFG_CENTER_NE4C0_15", + "CFG_CENTER_IMUX41_7", + "CFG_CENTER_LOGIC_OUTS_B5_9", + "CFG_CENTER_IMUX47_15", + "CFG_CENTER_BSCAN4_RUNTEST", + "CFG_CENTER_FRAME_ECC_FAR12", + "CFG_CENTER_SW2A1_12", + "CFG_CENTER_ICAP1_I19", + "CFG_CENTER_IMUX14_4", + "CFG_CENTER_EE2BEG1_17", + "CFG_CENTER_LOGIC_OUTS_B0_8", + "CFG_CENTER_NE4C0_9", + "CFG_CENTER_LOGIC_OUTS_B15_4", + "CFG_CENTER_NW4END1_10", + "CFG_CENTER_NE4BEG2_11", + "CFG_CENTER_FAN1_17", + "CFG_CENTER_EL1BEG1_4", + "CFG_CENTER_NW2A0_15", + "CFG_CENTER_NE4C2_4", + "CFG_CENTER_IMUX20_18", + "CFG_CENTER_SE4C2_11", + "CFG_CENTER_NW4END2_18", + "CFG_CENTER_CTRL1_16", + "CFG_CENTER_USR_ACCESS_DATA20", + "CFG_CENTER_NW4END1_6", + "CFG_CENTER_EE4A0_11", + "CFG_CENTER_IMUX26_9", + "CFG_CENTER_FAN0_2", + "CFG_CENTER_WW4A2_5", + "CFG_CENTER_IMUX45_8", + "CFG_CENTER_LOGIC_OUTS_B2_5", + "CFG_CENTER_IMUX13_12", + "CFG_CENTER_SE2A2_19", + "CFG_CENTER_USR_ACCESS_DATA22", + "CFG_CENTER_WW4A1_3", + "CFG_CENTER_IMUX38_11", + "CFG_CENTER_CTRL1_8", + "CFG_CENTER_SE2A3_13", + "CFG_CENTER_WW2END2_13", + "CFG_CENTER_WW4B1_8", + "CFG_CENTER_EE4BEG2_18", + "CFG_CENTER_BYP2_9", + "CFG_CENTER_IMUX41_15", + "CFG_CENTER_WR1END0_19", + "CFG_CENTER_LOGIC_OUTS_B3_4", + "CFG_CENTER_SW4A2_3", + "CFG_CENTER_IMUX3_17", + "CFG_CENTER_LH7_8", + "CFG_CENTER_NE4BEG2_4", + "CFG_CENTER_LH7_15", + "CFG_CENTER_IMUX22_15", + "CFG_CENTER_EE2BEG2_15", + "CFG_CENTER_LH3_13", + "CFG_CENTER_SW4A1_15", + "CFG_CENTER_LOGIC_OUTS_B15_2", + "CFG_CENTER_BYP7_4", + "CFG_CENTER_EE4A2_5", + "CFG_CENTER_USR_ACCESS_DATA16", + "CFG_CENTER_BSCAN4_UPDATE", + "CFG_CENTER_IMUX0_10", + "CFG_CENTER_EE2A0_17", + "CFG_CENTER_IMUX38_7", + "CFG_CENTER_IMUX2_17", + "CFG_CENTER_WW4END3_14", + "CFG_CENTER_IMUX13_11", + "CFG_CENTER_IMUX18_9", + "CFG_CENTER_WW4C3_19", + "CFG_CENTER_SW4A0_11", + "CFG_CENTER_WW4END3_12", + "CFG_CENTER_NE4BEG3_16", + "CFG_CENTER_EL1BEG3_9", + "CFG_CENTER_EE4A0_17", + "CFG_CENTER_SE2A0_2", + "CFG_CENTER_WW4END0_10", + "CFG_CENTER_ER1BEG1_9", + "CFG_CENTER_NW4END1_12", + "CFG_CENTER_NE4BEG1_16", + "CFG_CENTER_SW2A0_4", + "CFG_CENTER_ICAP1_O30", + "CFG_CENTER_FAN1_4", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA20", + "CFG_CENTER_FRAME_ECC_SYNDROME6", + "CFG_CENTER_LH8_9", + "CFG_CENTER_LH9_4", + "CFG_CENTER_LOGIC_OUTS_B12_16", + "CFG_CENTER_WW4B3_11", + "CFG_CENTER_IMUX13_13", + "CFG_CENTER_LOGIC_OUTS_B1_15", + "CFG_CENTER_LH6_7", + "CFG_CENTER_NE4BEG1_15", + "CFG_CENTER_WW2END3_11", + "CFG_CENTER_SE4BEG1_8", + "CFG_CENTER_CLK1_17", + "CFG_CENTER_LH2_5", + "CFG_CENTER_IMUX31_15", + "CFG_CENTER_WW4END2_5", + "CFG_CENTER_IMUX14_11", + "CFG_CENTER_NW4END1_3", + "CFG_CENTER_WW2A3_13", + "CFG_CENTER_IMUX19_5", + "CFG_CENTER_NW2A2_2", + "CFG_CENTER_WW2END2_15", + "CFG_CENTER_SW4END3_19", + "CFG_CENTER_EL1BEG1_17", + "CFG_CENTER_ICAP0_I24", + "CFG_CENTER_WW4A0_15", + "CFG_CENTER_IMUX24_8", + "CFG_CENTER_IMUX45_0", + "CFG_CENTER_BYP1_5", + "CFG_CENTER_LH4_18", + "CFG_CENTER_SE2A0_13", + "CFG_CENTER_EE4B2_2", + "CFG_CENTER_NW4A2_7", + "CFG_CENTER_EL1BEG2_13", + "CFG_CENTER_LOGIC_OUTS_B14_5", + "CFG_CENTER_USR_ACCESS_DATA0", + "CFG_CENTER_IMUX7_8", + "CFG_CENTER_LOGIC_OUTS_B12_12", + "CFG_CENTER_LOGIC_OUTS_B22_11", + "CFG_CENTER_LOGIC_OUTS_B19_5", + "CFG_CENTER_IMUX39_17", + "CFG_CENTER_ER1BEG3_1", + "CFG_CENTER_EE2BEG1_13", + "CFG_CENTER_LOGIC_OUTS_B17_15", + "CFG_CENTER_LOGIC_OUTS_B11_0", + "CFG_CENTER_FAN2_9", + "CFG_CENTER_NW4A0_19", + "CFG_CENTER_FAN3_1", + "CFG_CENTER_IMUX24_14", + "CFG_CENTER_IMUX10_9", + "CFG_CENTER_IMUX2_8", + "CFG_CENTER_IMUX39_5", + "CFG_CENTER_LOGIC_OUTS_B14_17", + "CFG_CENTER_ICAP1_O26", + "CFG_CENTER_SW4A2_6", + "CFG_CENTER_LOGIC_OUTS_B20_15", + "CFG_CENTER_EE4B0_4", + "CFG_CENTER_LOGIC_OUTS_B15_11", + "CFG_CENTER_ICAP1_O7", + "CFG_CENTER_NW4END1_11", + "CFG_CENTER_EE4B0_0", + "CFG_CENTER_EE2BEG2_9", + "CFG_CENTER_IMUX16_16", + "CFG_CENTER_IMUX11_6", + "CFG_CENTER_WR1END2_9", + "CFG_CENTER_NW2A0_8", + "CFG_CENTER_EE4BEG1_6", + "CFG_CENTER_NE4C1_9", + "CFG_CENTER_IMUX6_17", + "CFG_CENTER_NE4BEG0_0", + "CFG_CENTER_IMUX38_12", + "CFG_CENTER_NW4END0_18", + "CFG_CENTER_EE4BEG3_12", + "CFG_CENTER_LH10_14", + "CFG_CENTER_LOGIC_OUTS_B12_19", + "CFG_CENTER_WW4END0_4", + "CFG_CENTER_SW2A2_6", + "CFG_CENTER_WW2END0_12", + "CFG_CENTER_IMUX12_16", + "CFG_CENTER_EE2A1_7", + "CFG_CENTER_WW4C3_5", + "CFG_CENTER_EE2BEG2_2", + "CFG_CENTER_LH1_1", + "CFG_CENTER_LH11_9", + "CFG_CENTER_BYP1_12", + "CFG_CENTER_WW4END0_9", + "CFG_CENTER_LOGIC_OUTS_B3_18", + "CFG_CENTER_EE4BEG2_5", + "CFG_CENTER_WW4END3_0", + "CFG_CENTER_LOGIC_OUTS_B11_3", + "CFG_CENTER_SW4A0_4", + "CFG_CENTER_IMUX22_0", + "CFG_CENTER_EE4A1_17", + "CFG_CENTER_WW4A2_6", + "CFG_CENTER_EE4B2_11", + "CFG_CENTER_SE2A0_3", + "CFG_CENTER_WR1END0_9", + "CFG_CENTER_ER1BEG0_12", + "CFG_CENTER_ICAP1_O18", + "CFG_CENTER_SW4A1_19", + "CFG_CENTER_IMUX34_11", + "CFG_CENTER_SW4END2_2", + "CFG_CENTER_EE2BEG1_8", + "CFG_CENTER_NE2A2_5", + "CFG_CENTER_IMUX35_17", + "CFG_CENTER_STARTUP_PREQ", + "CFG_CENTER_LOGIC_OUTS_B0_18", + "CFG_CENTER_LH10_12", + "CFG_CENTER_SE4C1_0", + "CFG_CENTER_SE2A2_8", + "CFG_CENTER_EE4A0_6", + "CFG_CENTER_ICAP1_I13", + "CFG_CENTER_EE4C0_6", + "CFG_CENTER_IMUX7_13", + "CFG_CENTER_WW4C2_14", + "CFG_CENTER_EE4BEG2_0", + "CFG_CENTER_EE4B1_3", + "CFG_CENTER_EE2BEG2_10", + "CFG_CENTER_LOGIC_OUTS_B16_19", + "CFG_CENTER_EE4C3_18", + "CFG_CENTER_IMUX16_10", + "CFG_CENTER_ICAP1_I8", + "CFG_CENTER_WW4A3_14", + "CFG_CENTER_FAN0_4", + "CFG_CENTER_EE4BEG3_13", + "CFG_CENTER_WW4END0_14", + "CFG_CENTER_FAN0_15", + "CFG_CENTER_LH6_13", + "CFG_CENTER_IMUX1_19", + "CFG_CENTER_LOGIC_OUTS_B4_1", + "CFG_CENTER_WR1END1_0", + "CFG_CENTER_BYP7_11", + "CFG_CENTER_FAN4_6", + "CFG_CENTER_IMUX47_5", + "CFG_CENTER_CK_IN8", + "CFG_CENTER_BYP1_17", + "CFG_CENTER_IMUX35_19", + "CFG_CENTER_WW2A1_14", + "CFG_CENTER_LOGIC_OUTS_B17_2", + "CFG_CENTER_IMUX10_16", + "CFG_CENTER_IMUX23_8", + "CFG_CENTER_IMUX32_2", + "CFG_CENTER_SE4C1_1", + "CFG_CENTER_WW4B1_11", + "CFG_CENTER_EE4B0_5", + "CFG_CENTER_EE2BEG0_17", + "CFG_CENTER_STARTUP_USRCCLKTS", + "CFG_CENTER_LOGIC_OUTS_B1_14", + "CFG_CENTER_NE4BEG0_18", + "CFG_CENTER_SE2A3_10", + "CFG_CENTER_LH5_7", + "CFG_CENTER_SE4BEG1_15", + "CFG_CENTER_WW4A2_14", + "CFG_CENTER_IMUX23_1", + "CFG_CENTER_SW4END3_8", + "CFG_CENTER_NW4A1_10", + "CFG_CENTER_IMUX41_0", + "CFG_CENTER_IMUX22_17", + "CFG_CENTER_BYP3_3", + "CFG_CENTER_WW4A2_16", + "CFG_CENTER_IMUX8_11", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA6", + "CFG_CENTER_NE4C1_13", + "CFG_CENTER_EE4C2_12", + "CFG_CENTER_IMUX20_14", + "CFG_CENTER_WR1END1_12", + "CFG_CENTER_WW4END2_12", + "CFG_CENTER_IMUX11_18", + "CFG_CENTER_WW4END0_19", + "CFG_CENTER_SW2A3_15", + "CFG_CENTER_BYP3_17", + "CFG_CENTER_LOGIC_OUTS_B0_15", + "CFG_CENTER_SE2A0_4", + "CFG_CENTER_LOGIC_OUTS_B21_15", + "CFG_CENTER_SE4C0_2", + "CFG_CENTER_LOGIC_OUTS_B16_9", + "CFG_CENTER_NE4C0_8", + "CFG_CENTER_IMUX26_16", + "CFG_CENTER_WR1END3_3", + "CFG_CENTER_LOGIC_OUTS_B21_4", + "CFG_CENTER_SW2A3_19", + "CFG_CENTER_SW4A1_17", + "CFG_CENTER_SE2A2_15", + "CFG_CENTER_IMUX40_4", + "CFG_CENTER_LOGIC_OUTS_B1_8", + "CFG_CENTER_IMUX5_6", + "CFG_CENTER_CLK0_6", + "CFG_CENTER_IMUX4_5", + "CFG_CENTER_NE4BEG1_17", + "CFG_CENTER_WW2END1_15", + "CFG_CENTER_WL1END2_1", + "CFG_CENTER_ER1BEG2_12", + "CFG_CENTER_IMUX7_3", + "CFG_CENTER_MID_USR_ACCESS_DATA10", + "CFG_CENTER_BYP3_10", + "CFG_CENTER_LOGIC_OUTS_B23_17", + "CFG_CENTER_USR_ACCESS_DATA6", + "CFG_CENTER_CTRL0_0", + "CFG_CENTER_LOGIC_OUTS_B10_1", + "CFG_CENTER_ICAP0_I16", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA16", + "CFG_CENTER_LOGIC_OUTS_B8_11", + "CFG_CENTER_EL1BEG3_4", + "CFG_CENTER_EE2BEG2_7", + "CFG_CENTER_MID_USR_ACCESS_DATA7", + "CFG_CENTER_IMUX4_9", + "CFG_CENTER_LOGIC_OUTS_B5_15", + "CFG_CENTER_IMUX22_6", + "CFG_CENTER_SW4A0_6", + "CFG_CENTER_FAN2_3", + "CFG_CENTER_NE4BEG3_4", + "CFG_CENTER_EE2A2_17", + "CFG_CENTER_WW4C3_4", + "CFG_CENTER_WW4END2_16", + "CFG_CENTER_IMUX18_16", + "CFG_CENTER_SW4END0_14", + "CFG_CENTER_NW4A0_5", + "CFG_CENTER_LOGIC_OUTS_B22_3", + "CFG_CENTER_FAN4_7", + "CFG_CENTER_EE4C1_3", + "CFG_CENTER_IMUX38_2", + "CFG_CENTER_LH6_3", + "CFG_CENTER_LH11_2", + "CFG_CENTER_LOGIC_OUTS_B15_16", + "CFG_CENTER_SE4BEG2_0", + "CFG_CENTER_SE2A3_8", + "CFG_CENTER_IMUX43_3", + "CFG_CENTER_IMUX3_4", + "CFG_CENTER_EE4B0_14", + "CFG_CENTER_LOGIC_OUTS_B4_12", + "CFG_CENTER_SW4END2_6", + "CFG_CENTER_NE4BEG0_14", + "CFG_CENTER_IMUX5_9", + "CFG_CENTER_LOGIC_OUTS_B14_18", + "CFG_CENTER_IMUX12_9", + "CFG_CENTER_WL1END2_8", + "CFG_CENTER_WW2A3_5", + "CFG_CENTER_IMUX20_17", + "CFG_CENTER_IMUX42_19", + "CFG_CENTER_EE4A3_2", + "CFG_CENTER_ICAP1_O11", + "CFG_CENTER_LOGIC_OUTS_B21_2", + "CFG_CENTER_IMUX19_10", + "CFG_CENTER_SE4C1_10", + "CFG_CENTER_ICAP0_O9", + "CFG_CENTER_IMUX24_17", + "CFG_CENTER_IMUX39_4", + "CFG_CENTER_BLOCK_OUTS_B0_1", + "CFG_CENTER_FAN1_12", + "CFG_CENTER_IMUX46_1", + "CFG_CENTER_LH5_3", + "CFG_CENTER_IMUX43_7", + "CFG_CENTER_ICAP1_O15", + "CFG_CENTER_LOGIC_OUTS_B17_14", + "CFG_CENTER_WW2A0_9", + "CFG_CENTER_SE4BEG2_18", + "CFG_CENTER_FAN3_6", + "CFG_CENTER_EE4BEG0_4", + "CFG_CENTER_WW4END2_8", + "CFG_CENTER_LH1_18", + "CFG_CENTER_SE4BEG0_6", + "CFG_CENTER_EE4B1_10", + "CFG_CENTER_WW2END2_16", + "CFG_CENTER_NW2A1_7", + "CFG_CENTER_IMUX4_0", + "CFG_CENTER_NW4END2_5", + "CFG_CENTER_WW4END0_3", + "CFG_CENTER_SW4A2_5", + "CFG_CENTER_IMUX19_3", + "CFG_CENTER_LH9_19", + "CFG_CENTER_IMUX43_1", + "CFG_CENTER_LOGIC_OUTS_B4_17", + "CFG_CENTER_WW2END2_4", + "CFG_CENTER_EE4C2_19", + "CFG_CENTER_EE2BEG0_7", + "CFG_CENTER_WW2END3_1", + "CFG_CENTER_SE4C3_7", + "CFG_CENTER_IMUX39_11", + "CFG_CENTER_NW4END3_10", + "CFG_CENTER_LOGIC_OUTS_B10_0", + "CFG_CENTER_WW2END2_7", + "CFG_CENTER_WW4B2_17", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA15", + "CFG_CENTER_IMUX26_4", + "CFG_CENTER_EE2A3_8", + "CFG_CENTER_LH10_16", + "CFG_CENTER_LOGIC_OUTS_B16_7", + "CFG_CENTER_WW2END1_6", + "CFG_CENTER_WR1END2_13", + "CFG_CENTER_EE2BEG3_4", + "CFG_CENTER_EE4B2_12", + "CFG_CENTER_IMUX44_5", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA21", + "CFG_CENTER_WW4END3_11", + "CFG_CENTER_NE4C2_1", + "CFG_CENTER_FAN0_11", + "CFG_CENTER_IMUX19_9", + "CFG_CENTER_FAN5_11", + "CFG_CENTER_NW4END0_15", + "CFG_CENTER_EE4C1_1", + "CFG_CENTER_WW2END3_3", + "CFG_CENTER_WW2END1_10", + "CFG_CENTER_LOGIC_OUTS_B14_19", + "CFG_CENTER_WW4C1_15", + "CFG_CENTER_SE4C1_9", + "CFG_CENTER_WL1END3_4", + "CFG_CENTER_NE4C1_0", + "CFG_CENTER_LH2_6", + "CFG_CENTER_SE4C2_6", + "CFG_CENTER_WW4B3_8", + "CFG_CENTER_IMUX33_2", + "CFG_CENTER_CK_BUFRCLK3", + "CFG_CENTER_EL1BEG1_2", + "CFG_CENTER_IMUX34_17", + "CFG_CENTER_LOGIC_OUTS_B4_13", + "CFG_CENTER_LOGIC_OUTS_B22_19", + "CFG_CENTER_IMUX19_8", + "CFG_CENTER_IMUX42_13", + "CFG_CENTER_NW4A3_8", + "CFG_CENTER_IMUX42_15", + "CFG_CENTER_ICAP0_I27", + "CFG_CENTER_IMUX27_4", + "CFG_CENTER_SW4END3_10", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA11", + "CFG_CENTER_WW4C0_16", + "CFG_CENTER_IMUX38_6", + "CFG_CENTER_IMUX7_11", + "CFG_CENTER_EE2A2_3", + "CFG_CENTER_SW4END0_12", + "CFG_CENTER_EE4B0_13", + "CFG_CENTER_EE4A2_19", + "CFG_CENTER_BYP6_15", + "CFG_CENTER_IMUX36_5", + "CFG_CENTER_EE4B1_14", + "CFG_CENTER_ICAP0_O12", + "CFG_CENTER_BLOCK_OUTS_B0_19", + "CFG_CENTER_EE4BEG3_6", + "CFG_CENTER_IMUX39_7", + "CFG_CENTER_IMUX40_8", + "CFG_CENTER_WL1END0_3", + "CFG_CENTER_EL1BEG2_12", + "CFG_CENTER_FAN6_16", + "CFG_CENTER_WR1END1_10", + "CFG_CENTER_WW2A1_9", + "CFG_CENTER_FAN5_16", + "CFG_CENTER_LH3_3", + "CFG_CENTER_IMUX16_4", + "CFG_CENTER_IMUX23_19", + "CFG_CENTER_LOGIC_OUTS_B14_2", + "CFG_CENTER_LH11_14", + "CFG_CENTER_IMUX11_2", + "CFG_CENTER_EL1BEG3_14", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA29", + "CFG_CENTER_EL1BEG2_3", + "CFG_CENTER_FAN4_15", + "CFG_CENTER_IMUX27_7", + "CFG_CENTER_EE4B0_3", + "CFG_CENTER_WL1END3_16", + "CFG_CENTER_EL1BEG1_7", + "CFG_CENTER_LH3_19", + "CFG_CENTER_IMUX15_17", + "CFG_CENTER_EE4A0_9", + "CFG_CENTER_WW2END3_14", + "CFG_CENTER_BYP6_18", + "CFG_CENTER_BYP0_5", + "CFG_CENTER_NE4C1_4", + "CFG_CENTER_FAN5_2", + "CFG_CENTER_NE4C1_18", + "CFG_CENTER_FRAME_ECC_SYNWORD2", + "CFG_CENTER_LOGIC_OUTS_B2_3", + "CFG_CENTER_WW2A3_11", + "CFG_CENTER_ER1BEG0_3", + "CFG_CENTER_LOGIC_OUTS_B19_11", + "CFG_CENTER_NE4C0_11", + "CFG_CENTER_WW4A0_0", + "CFG_CENTER_WW4C2_11", + "CFG_CENTER_SE4C3_9", + "CFG_CENTER_WW4END1_11", + "CFG_CENTER_EE4BEG3_15", + "CFG_CENTER_IMUX24_6", + "CFG_CENTER_IMUX34_6", + "CFG_CENTER_EE4B1_2", + "CFG_CENTER_IMUX38_13", + "CFG_CENTER_BLOCK_OUTS_B2_4", + "CFG_CENTER_LH1_3", + "CFG_CENTER_SW4END1_11", + "CFG_CENTER_EL1BEG1_6", + "CFG_CENTER_IMUX19_12", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA15", + "CFG_CENTER_LOGIC_OUTS_B6_7", + "CFG_CENTER_LOGIC_OUTS_B3_0", + "CFG_CENTER_SE4BEG2_11", + "CFG_CENTER_SE4C2_14", + "CFG_CENTER_IMUX20_10", + "CFG_CENTER_LOGIC_OUTS_B23_3", + "CFG_CENTER_CTRL1_11", + "CFG_CENTER_IMUX0_4", + "CFG_CENTER_FAN3_4", + "CFG_CENTER_NW4A1_17", + "CFG_CENTER_EE4B2_16", + "CFG_CENTER_NE2A3_11", + "CFG_CENTER_EE4B1_17", + "CFG_CENTER_SE4BEG2_3", + "CFG_CENTER_EE2A0_13", + "CFG_CENTER_LOGIC_OUTS_B19_17", + "CFG_CENTER_EE4C3_4", + "CFG_CENTER_WW2A3_7", + "CFG_CENTER_LH3_2", + "CFG_CENTER_IMUX12_0", + "CFG_CENTER_IMUX3_9", + "CFG_CENTER_WL1END3_18", + "CFG_CENTER_SW4END1_5", + "CFG_CENTER_WW2END2_6", + "CFG_CENTER_IMUX42_0", + "CFG_CENTER_LOGIC_OUTS_B8_1", + "CFG_CENTER_LOGIC_OUTS_B13_9", + "CFG_CENTER_SE4C3_13", + "CFG_CENTER_SE4BEG0_15", + "CFG_CENTER_LH11_16", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA25", + "CFG_CENTER_FRAME_ECC_FAR19", + "CFG_CENTER_SW4END2_12", + "CFG_CENTER_USR_ACCESS_DATA10", + "CFG_CENTER_IMUX17_17", + "CFG_CENTER_WL1END3_12", + "CFG_CENTER_IMUX33_9", + "CFG_CENTER_LOGIC_OUTS_B18_13", + "CFG_CENTER_LH9_0", + "CFG_CENTER_NW4END2_10", + "CFG_CENTER_NW2A3_10", + "CFG_CENTER_IMUX15_0", + "CFG_CENTER_FRAME_ECC_SYNDROME7", + "CFG_CENTER_LOGIC_OUTS_B7_6", + "CFG_CENTER_CTRL0_16", + "CFG_CENTER_NW4A1_5", + "CFG_CENTER_IMUX21_12", + "CFG_CENTER_LH7_0", + "CFG_CENTER_EL1BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B19_9", + "CFG_CENTER_CTRL1_13", + "CFG_CENTER_LH4_10", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA13", + "CFG_CENTER_IMUX2_0", + "CFG_CENTER_USR_ACCESS_DATA8", + "CFG_CENTER_CK_BUFHCLK8", + "CFG_CENTER_EL1BEG2_7", + "CFG_CENTER_LOGIC_OUTS_B15_14", + "CFG_CENTER_BSCAN1_TDO", + "CFG_CENTER_LOGIC_OUTS_B23_18", + "CFG_CENTER_EE2A1_16", + "CFG_CENTER_IMUX8_14", + "CFG_CENTER_EE4C0_18", + "CFG_CENTER_SW2A1_10", + "CFG_CENTER_WW4A1_9", + "CFG_CENTER_CTRL1_19", + "CFG_CENTER_ER1BEG0_7", + "CFG_CENTER_IMUX22_1", + "CFG_CENTER_NE4C1_11", + "CFG_CENTER_EE4A1_15", + "CFG_CENTER_WW2A2_3", + "CFG_CENTER_LOGIC_OUTS_B23_15", + "CFG_CENTER_EL1BEG0_15", + "CFG_CENTER_IMUX7_19", + "CFG_CENTER_SE4BEG0_17", + "CFG_CENTER_WL1END2_11", + "CFG_CENTER_WW4C1_13", + "CFG_CENTER_LOGIC_OUTS_B22_13", + "CFG_CENTER_BSCAN3_CAPTURE", + "CFG_CENTER_EE4C0_13", + "CFG_CENTER_IMUX43_5", + "CFG_CENTER_IMUX31_4", + "CFG_CENTER_EE4B1_13", + "CFG_CENTER_WW2A1_12", + "CFG_CENTER_SE2A3_2", + "CFG_CENTER_IMUX30_18", + "CFG_CENTER_SW4A1_2", + "CFG_CENTER_IMUX22_18", + "CFG_CENTER_NW4A2_13", + "CFG_CENTER_FAN7_2", + "CFG_CENTER_ER1BEG1_0", + "CFG_CENTER_IMUX46_5", + "CFG_CENTER_IMUX37_9", + "CFG_CENTER_IMUX13_15", + "CFG_CENTER_WW2END0_3", + "CFG_CENTER_WL1END0_5", + "CFG_CENTER_EL1BEG3_10", + "CFG_CENTER_WW4C0_5", + "CFG_CENTER_FRAME_ECC_SYNDROME10", + "CFG_CENTER_NE4C0_18", + "CFG_CENTER_WW4C0_19", + "CFG_CENTER_IMUX41_18", + "CFG_CENTER_LH11_8", + "CFG_CENTER_SE4C3_15", + "CFG_CENTER_STARTUP_GSR", + "CFG_CENTER_LOGIC_OUTS_B23_1", + "CFG_CENTER_WW4A1_7", + "CFG_CENTER_WW4A2_12", + "CFG_CENTER_LOGIC_OUTS_B16_12", + "CFG_CENTER_NW4END2_13", + "CFG_CENTER_EE4B1_4", + "CFG_CENTER_IMUX21_18", + "CFG_CENTER_IMUX8_13", + "CFG_CENTER_FAN0_19", + "CFG_CENTER_BYP0_0", + "CFG_CENTER_NE4C0_6", + "CFG_CENTER_SW4A2_11", + "CFG_CENTER_WW4B0_16", + "CFG_CENTER_EE4BEG0_3", + "CFG_CENTER_SW2A1_9", + "CFG_CENTER_BLOCK_OUTS_B2_12", + "CFG_CENTER_SW2A1_6", + "CFG_CENTER_IMUX33_11", + "CFG_CENTER_EE2BEG0_5", + "CFG_CENTER_IMUX6_13", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA18", + "CFG_CENTER_NW4END3_16", + "CFG_CENTER_EE4A0_13", + "CFG_CENTER_WW2END1_2", + "CFG_CENTER_WW4B3_7", + "CFG_CENTER_SE2A0_15", + "CFG_CENTER_NW2A0_19", + "CFG_CENTER_FRAME_ECC_FAR7", + "CFG_CENTER_FRAME_ECC_SYNWORD5", + "CFG_CENTER_FAN5_13", + "CFG_CENTER_WW4C3_9", + "CFG_CENTER_WW2A0_14", + "CFG_CENTER_NW2A2_8", + "CFG_CENTER_WW2A0_11", + "CFG_CENTER_ER1BEG3_2", + "CFG_CENTER_FAN3_11", + "CFG_CENTER_IMUX33_7", + "CFG_CENTER_CK_IN1", + "CFG_CENTER_ER1BEG2_0", + "CFG_CENTER_LOGIC_OUTS_B12_15", + "CFG_CENTER_LH9_15", + "CFG_CENTER_CTRL0_14", + "CFG_CENTER_LOGIC_OUTS_B10_3", + "CFG_CENTER_IMUX8_16", + "CFG_CENTER_WL1END0_14", + "CFG_CENTER_CLK0_15", + "CFG_CENTER_LH9_6", + "CFG_CENTER_IMUX19_7", + "CFG_CENTER_SE4BEG1_6", + "CFG_CENTER_SW4A1_6", + "CFG_CENTER_NE4C1_7", + "CFG_CENTER_IMUX39_12", + "CFG_CENTER_IMUX46_19", + "CFG_CENTER_ICAP0_O31", + "CFG_CENTER_LOGIC_OUTS_B16_13", + "CFG_CENTER_LOGIC_OUTS_B5_8", + "CFG_CENTER_FAN5_3", + "CFG_CENTER_IMUX10_11", + "CFG_CENTER_EE2A3_13", + "CFG_CENTER_WW2A3_19", + "CFG_CENTER_BSCAN2_DRCK", + "CFG_CENTER_IMUX21_4", + "CFG_CENTER_NE4BEG0_15", + "CFG_CENTER_NE4C3_2", + "CFG_CENTER_IMUX17_2", + "CFG_CENTER_IMUX46_18", + "CFG_CENTER_LOGIC_OUTS_B14_15", + "CFG_CENTER_IMUX23_2", + "CFG_CENTER_FAN2_13", + "CFG_CENTER_SE4C0_18", + "CFG_CENTER_SE2A0_14", + "CFG_CENTER_IMUX30_10", + "CFG_CENTER_NW4END1_2", + "CFG_CENTER_BLOCK_OUTS_B0_5", + "CFG_CENTER_LOGIC_OUTS_B1_7", + "CFG_CENTER_NE4C2_0", + "CFG_CENTER_BYP2_5", + "CFG_CENTER_ER1BEG1_19", + "CFG_CENTER_IMUX5_17", + "CFG_CENTER_IMUX0_3", + "CFG_CENTER_NE4C1_5", + "CFG_CENTER_IMUX31_2", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA19", + "CFG_CENTER_WW4C1_10", + "CFG_CENTER_LOGIC_OUTS_B3_15", + "CFG_CENTER_FRAME_ECC_FAR1", + "CFG_CENTER_BLOCK_OUTS_B3_1", + "CFG_CENTER_FAN5_6", + "CFG_CENTER_WW4A3_2", + "CFG_CENTER_ICAP0_I29", + "CFG_CENTER_BLOCK_OUTS_B2_8", + "CFG_CENTER_LOGIC_OUTS_B23_9", + "CFG_CENTER_WW4C2_15", + "CFG_CENTER_WL1END1_12", + "CFG_CENTER_SW4END2_15", + "CFG_CENTER_IMUX8_0", + "CFG_CENTER_WW4B0_4", + "CFG_CENTER_BYP2_3", + "CFG_CENTER_IMUX13_8", + "CFG_CENTER_WR1END0_1", + "CFG_CENTER_DCIRESET_RST", + "CFG_CENTER_LOGIC_OUTS_B16_17", + "CFG_CENTER_CTRL0_3", + "CFG_CENTER_IMUX5_11", + "CFG_CENTER_LOGIC_OUTS_B20_5", + "CFG_CENTER_FAN3_9", + "CFG_CENTER_SE4BEG3_6", + "CFG_CENTER_SE4BEG1_9", + "CFG_CENTER_IMUX41_16", + "CFG_CENTER_IMUX15_12", + "CFG_CENTER_EE4B0_11", + "CFG_CENTER_SW4END1_8", + "CFG_CENTER_FAN5_18", + "CFG_CENTER_IMUX6_11", + "CFG_CENTER_LH11_3", + "CFG_CENTER_NW2A3_11", + "CFG_CENTER_SW4END1_3", + "CFG_CENTER_EE4C2_11", + "CFG_CENTER_EE4BEG1_7", + "CFG_CENTER_IMUX28_9", + "CFG_CENTER_NE4C0_10", + "CFG_CENTER_FRAME_ECC_SYNWORD0", + "CFG_CENTER_WW4B1_9", + "CFG_CENTER_ICAP0_I8", + "CFG_CENTER_IMUX38_15", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA22", + "CFG_CENTER_SE4BEG3_5", + "CFG_CENTER_NW4A1_9", + "CFG_CENTER_WW4END3_18", + "CFG_CENTER_EE2A2_2", + "CFG_CENTER_NW4A2_1", + "CFG_CENTER_SE4BEG1_0", + "CFG_CENTER_IMUX34_10", + "CFG_CENTER_BYP7_19", + "CFG_CENTER_NE2A0_9", + "CFG_CENTER_SE4BEG0_12", + "CFG_CENTER_EE4A2_4", + "CFG_CENTER_ICAP0_O25", + "CFG_CENTER_FAN2_7", + "CFG_CENTER_EE4A2_3", + "CFG_CENTER_SE2A0_17", + "CFG_CENTER_NE4C0_17", + "CFG_CENTER_WW4A3_12", + "CFG_CENTER_WW2END0_9", + "CFG_CENTER_SW4A3_2", + "CFG_CENTER_WW4C3_11", + "CFG_CENTER_ER1BEG1_17", + "CFG_CENTER_SW2A1_7", + "CFG_CENTER_ICAP0_I31", + "CFG_CENTER_IMUX28_3", + "CFG_CENTER_BSCAN2_RESET", + "CFG_CENTER_IMUX18_17", + "CFG_CENTER_NE2A0_4", + "CFG_CENTER_WW4C2_9", + "CFG_CENTER_BLOCK_OUTS_B2_17", + "CFG_CENTER_NW2A0_13", + "CFG_CENTER_EL1BEG3_0", + "CFG_CENTER_IMUX34_7", + "CFG_CENTER_NE4C3_9", + "CFG_CENTER_NW4A0_16", + "CFG_CENTER_FAN4_5", + "CFG_CENTER_WW4C0_7", + "CFG_CENTER_LOGIC_OUTS_B14_11", + "CFG_CENTER_FAN1_18", + "CFG_CENTER_EL1BEG1_12", + "CFG_CENTER_NE2A2_3", + "CFG_CENTER_IMUX30_19", + "CFG_CENTER_LH1_14", + "CFG_CENTER_LOGIC_OUTS_B18_15", + "CFG_CENTER_IMUX25_15", + "CFG_CENTER_IMUX23_14", + "CFG_CENTER_BLOCK_OUTS_B1_19", + "CFG_CENTER_WW4B0_19", + "CFG_CENTER_LOGIC_OUTS_B20_18", + "CFG_CENTER_SE4C0_16", + "CFG_CENTER_FAN7_13", + "CFG_CENTER_EE4BEG3_2", + "CFG_CENTER_IMUX28_11", + "CFG_CENTER_EE4BEG3_14", + "CFG_CENTER_CLK0_10", + "CFG_CENTER_NE4C2_15", + "CFG_CENTER_WW4C2_12", + "CFG_CENTER_FAN6_4", + "CFG_CENTER_WW2A2_1", + "CFG_CENTER_LOGIC_OUTS_B12_6", + "CFG_CENTER_LOGIC_OUTS_B12_5", + "CFG_CENTER_CLK1_7", + "CFG_CENTER_SE4C0_4", + "CFG_CENTER_ICAP0_I25", + "CFG_CENTER_WL1END0_13", + "CFG_CENTER_BYP3_16", + "CFG_CENTER_IMUX7_7", + "CFG_CENTER_LH12_16", + "CFG_CENTER_NW4A1_8", + "CFG_CENTER_LOGIC_OUTS_B11_6", + "CFG_CENTER_IMUX30_9", + "CFG_CENTER_IMUX6_5", + "CFG_CENTER_ICAP1_O16", + "CFG_CENTER_EE2A3_4", + "CFG_CENTER_EE2A2_14", + "CFG_CENTER_SE2A2_9", + "CFG_CENTER_CK_BUFHCLK7", + "CFG_CENTER_IMUX32_11", + "CFG_CENTER_LOGIC_OUTS_B12_4", + "CFG_CENTER_NE4C1_17", + "CFG_CENTER_IMUX10_18", + "CFG_CENTER_CTRL0_11", + "CFG_CENTER_LOGIC_OUTS_B9_15", + "CFG_CENTER_IMUX22_11", + "CFG_CENTER_NW4A0_11", + "CFG_CENTER_EE4BEG1_9", + "CFG_CENTER_EE4A1_10", + "CFG_CENTER_WW4B2_19", + "CFG_CENTER_NE4BEG0_9", + "CFG_CENTER_IMUX33_13", + "CFG_CENTER_WW4A1_5", + "CFG_CENTER_BLOCK_OUTS_B3_15", + "CFG_CENTER_LH3_4", + "CFG_CENTER_SE4BEG3_13", + "CFG_CENTER_WW4END1_19", + "CFG_CENTER_CK_IN10", + "CFG_CENTER_WW2END2_0", + "CFG_CENTER_IMUX9_14", + "CFG_CENTER_LOGIC_OUTS_B10_6", + "CFG_CENTER_IMUX20_7", + "CFG_CENTER_LOGIC_OUTS_B16_2", + "CFG_CENTER_LOGIC_OUTS_B12_0", + "CFG_CENTER_BYP1_6", + "CFG_CENTER_SE2A0_12", + "CFG_CENTER_USR_ACCESS_DATA21", + "CFG_CENTER_EL1BEG1_18", + "CFG_CENTER_NE4BEG3_17", + "CFG_CENTER_BLOCK_OUTS_B3_16", + "CFG_CENTER_WL1END1_2", + "CFG_CENTER_CK_BUFHCLK0", + "CFG_CENTER_SW4END0_17", + "CFG_CENTER_ER1BEG0_11", + "CFG_CENTER_WL1END0_4", + "CFG_CENTER_EL1BEG3_5", + "CFG_CENTER_IMUX35_15", + "CFG_CENTER_SW4A0_17", + "CFG_CENTER_NW2A0_5", + "CFG_CENTER_LOGIC_OUTS_B17_12", + "CFG_CENTER_SW4A0_18", + "CFG_CENTER_NE4BEG2_3", + "CFG_CENTER_WW2A0_4", + "CFG_CENTER_SW4A1_13", + "CFG_CENTER_IMUX15_16", + "CFG_CENTER_WW2END3_15", + "CFG_CENTER_NE2A3_12", + "CFG_CENTER_LOGIC_OUTS_B6_14", + "CFG_CENTER_BYP4_10", + "CFG_CENTER_IMUX36_2", + "CFG_CENTER_NW4A2_0", + "CFG_CENTER_BYP0_4", + "CFG_CENTER_NE4BEG1_1", + "CFG_CENTER_IMUX44_6", + "CFG_CENTER_IMUX0_17", + "CFG_CENTER_EE4BEG3_16", + "CFG_CENTER_EE2A2_1", + "CFG_CENTER_SW4END0_3", + "CFG_CENTER_WL1END0_6", + "CFG_CENTER_WL1END0_17", + "CFG_CENTER_EE2A2_7", + "CFG_CENTER_IMUX0_9", + "CFG_CENTER_SW4END1_15", + "CFG_CENTER_WW2END0_18", + "CFG_CENTER_SE4BEG1_10", + "CFG_CENTER_FRAME_ECC_FAR0", + "CFG_CENTER_LOGIC_OUTS_B15_15", + "CFG_CENTER_LOGIC_OUTS_B18_8", + "CFG_CENTER_WW2END1_8", + "CFG_CENTER_BLOCK_OUTS_B1_14", + "CFG_CENTER_LOGIC_OUTS_B12_9", + "CFG_CENTER_EE4BEG1_18", + "CFG_CENTER_SE4BEG3_12", + "CFG_CENTER_IMUX6_4", + "CFG_CENTER_IMUX20_1", + "CFG_CENTER_LH11_5", + "CFG_CENTER_IMUX29_10", + "CFG_CENTER_LOGIC_OUTS_B2_0", + "CFG_CENTER_EL1BEG0_12", + "CFG_CENTER_NE4C1_10", + "CFG_CENTER_SE2A0_0", + "CFG_CENTER_SE4C3_3", + "CFG_CENTER_WW4C1_7", + "CFG_CENTER_LH8_13", + "CFG_CENTER_SE4BEG0_9", + "CFG_CENTER_LH9_18", + "CFG_CENTER_IMUX47_19", + "CFG_CENTER_IMUX28_0", + "CFG_CENTER_WW4END2_11", + "CFG_CENTER_EE2BEG3_1", + "CFG_CENTER_EE4C1_0", + "CFG_CENTER_WW4C0_1", + "CFG_CENTER_IMUX5_10", + "CFG_CENTER_LOGIC_OUTS_B16_6", + "CFG_CENTER_IMUX45_6", + "CFG_CENTER_EE4C1_4", + "CFG_CENTER_SE4BEG2_19", + "CFG_CENTER_BLOCK_OUTS_B1_18", + "CFG_CENTER_NE4BEG2_16", + "CFG_CENTER_IMUX27_8", + "CFG_CENTER_SW4A2_4", + "CFG_CENTER_FAN6_11", + "CFG_CENTER_IMUX32_10", + "CFG_CENTER_EE2A3_3", + "CFG_CENTER_WW4B3_18", + "CFG_CENTER_WL1END0_19", + "CFG_CENTER_BYP4_2", + "CFG_CENTER_EE2A3_19", + "CFG_CENTER_BYP1_4", + "CFG_CENTER_BYP4_3", + "CFG_CENTER_FAN7_10", + "CFG_CENTER_ER1BEG2_3", + "CFG_CENTER_ICAP0_RDWRB", + "CFG_CENTER_NW2A2_18", + "CFG_CENTER_BYP0_2", + "CFG_CENTER_WW2END2_19", + "CFG_CENTER_SW4END3_11", + "CFG_CENTER_CLK1_18", + "CFG_CENTER_LH1_5", + "CFG_CENTER_NW2A2_1", + "CFG_CENTER_WW4A3_8", + "CFG_CENTER_WR1END2_16", + "CFG_CENTER_IMUX5_5", + "CFG_CENTER_IMUX12_12", + "CFG_CENTER_IMUX30_11", + "CFG_CENTER_IMUX2_13", + "CFG_CENTER_BSCAN4_TCK", + "CFG_CENTER_IMUX16_5", + "CFG_CENTER_LOGIC_OUTS_B12_2", + "CFG_CENTER_SW2A1_3", + "CFG_CENTER_STARTUP_USRCCLKO", + "CFG_CENTER_EE4A2_0", + "CFG_CENTER_LOGIC_OUTS_B12_8", + "CFG_CENTER_NE4C2_7", + "CFG_CENTER_SW4A1_1", + "CFG_CENTER_SE2A3_17", + "CFG_CENTER_CLK0_7", + "CFG_CENTER_SE4BEG3_3", + "CFG_CENTER_ER1BEG1_8", + "CFG_CENTER_IMUX45_5", + "CFG_CENTER_LOGIC_OUTS_B7_7", + "CFG_CENTER_WW2A1_16", + "CFG_CENTER_NE2A3_8", + "CFG_CENTER_SE4BEG2_13", + "CFG_CENTER_WW2A3_8", + "CFG_CENTER_SW2A3_6", + "CFG_CENTER_EE4BEG2_12", + "CFG_CENTER_FAN1_5", + "CFG_CENTER_IMUX24_13", + "CFG_CENTER_LOGIC_OUTS_B10_5", + "CFG_CENTER_FAN6_12", + "CFG_CENTER_IMUX8_8", + "CFG_CENTER_WW4C3_14", + "CFG_CENTER_BYP2_7", + "CFG_CENTER_ER1BEG3_4", + "CFG_CENTER_WW4B3_16", + "CFG_CENTER_EE4B3_1", + "CFG_CENTER_WW2A0_18", + "CFG_CENTER_WW2A1_13", + "CFG_CENTER_NE4BEG1_19", + "CFG_CENTER_LOGIC_OUTS_B8_15", + "CFG_CENTER_LH7_10", + "CFG_CENTER_LOGIC_OUTS_B14_6", + "CFG_CENTER_WW4C3_16", + "CFG_CENTER_EE2BEG2_1", + "CFG_CENTER_WW4END3_2", + "CFG_CENTER_BYP4_0", + "CFG_CENTER_IMUX43_17", + "CFG_CENTER_IMUX18_18", + "CFG_CENTER_CLK0_18", + "CFG_CENTER_NW2A3_15", + "CFG_CENTER_LOGIC_OUTS_B22_10", + "CFG_CENTER_SW4END2_19", + "CFG_CENTER_WW4END3_1", + "CFG_CENTER_ICAP0_O18", + "CFG_CENTER_SE4C2_13", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA17", + "CFG_CENTER_NW2A0_18", + "CFG_CENTER_EE4C3_10", + "CFG_CENTER_FRAME_ECC_FAR13", + "CFG_CENTER_IMUX33_15", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA10", + "CFG_CENTER_EE4A0_4", + "CFG_CENTER_NW4A2_15", + "CFG_CENTER_SW4A3_10", + "CFG_CENTER_EE2A1_8", + "CFG_CENTER_EE4BEG1_17", + "CFG_CENTER_FAN6_9", + "CFG_CENTER_LH7_11", + "CFG_CENTER_IMUX27_17", + "CFG_CENTER_NE4BEG3_5", + "CFG_CENTER_SW2A1_1", + "CFG_CENTER_ICAP0_O10", + "CFG_CENTER_EE4A2_9", + "CFG_CENTER_NW2A1_18", + "CFG_CENTER_WL1END3_7", + "CFG_CENTER_EE4BEG3_8", + "CFG_CENTER_LOGIC_OUTS_B10_18", + "CFG_CENTER_SW2A1_0", + "CFG_CENTER_LOGIC_OUTS_B23_13", + "CFG_CENTER_EL1BEG1_10", + "CFG_CENTER_ICAP1_O13", + "CFG_CENTER_LOGIC_OUTS_B23_19", + "CFG_CENTER_FRAME_ECC_SYNBIT1", + "CFG_CENTER_LOGIC_OUTS_B1_4", + "CFG_CENTER_IMUX20_15", + "CFG_CENTER_NE2A1_1", + "CFG_CENTER_EE4C3_19", + "CFG_CENTER_NW2A3_8", + "CFG_CENTER_BLOCK_OUTS_B1_12", + "CFG_CENTER_IMUX32_16", + "CFG_CENTER_LOGIC_OUTS_B17_11", + "CFG_CENTER_LH9_13", + "CFG_CENTER_EE4C2_16", + "CFG_CENTER_EE4C3_17", + "CFG_CENTER_FAN7_15", + "CFG_CENTER_SE4C0_7", + "CFG_CENTER_EE4B1_1", + "CFG_CENTER_EE4BEG3_19", + "CFG_CENTER_ER1BEG2_4", + "CFG_CENTER_NE2A2_13", + "CFG_CENTER_NW4A0_7", + "CFG_CENTER_IMUX9_8", + "CFG_CENTER_SW4END0_10", + "CFG_CENTER_WW4C1_9", + "CFG_CENTER_USR_ACCESS_DATA4", + "CFG_CENTER_LOGIC_OUTS_B19_13", + "CFG_CENTER_IMUX10_1", + "CFG_CENTER_IMUX35_16", + "CFG_CENTER_SE2A3_16", + "CFG_CENTER_EE4A3_12", + "CFG_CENTER_IMUX22_10", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA24", + "CFG_CENTER_ER1BEG3_9", + "CFG_CENTER_LOGIC_OUTS_B18_3", + "CFG_CENTER_SW4END2_3", + "CFG_CENTER_IMUX13_14", + "CFG_CENTER_WW2A0_2", + "CFG_CENTER_ICAP0_O13", + "CFG_CENTER_BSCAN1_TMS", + "CFG_CENTER_LH5_12", + "CFG_CENTER_LH5_15", + "CFG_CENTER_SW2A3_16", + "CFG_CENTER_LOGIC_OUTS_B7_5", + "CFG_CENTER_NE2A2_2", + "CFG_CENTER_SE2A3_0", + "CFG_CENTER_BYP1_11", + "CFG_CENTER_WW4B3_3", + "CFG_CENTER_NW4A1_13", + "CFG_CENTER_NW4END2_11", + "CFG_CENTER_SE4BEG3_1", + "CFG_CENTER_LOGIC_OUTS_B14_1", + "CFG_CENTER_IMUX39_16", + "CFG_CENTER_IMUX4_13", + "CFG_CENTER_BYP0_8", + "CFG_CENTER_EE2A1_17", + "CFG_CENTER_FAN6_14", + "CFG_CENTER_WL1END3_1", + "CFG_CENTER_FRAME_ECC_SYNWORD6", + "CFG_CENTER_ICAP1_O21", + "CFG_CENTER_SW4A3_16", + "CFG_CENTER_LOGIC_OUTS_B20_17", + "CFG_CENTER_NE4C2_12", + "CFG_CENTER_ICAP1_O29", + "CFG_CENTER_SE2A2_13", + "CFG_CENTER_WR1END1_5", + "CFG_CENTER_WW4B1_18", + "CFG_CENTER_NE2A3_14", + "CFG_CENTER_NE4BEG2_10", + "CFG_CENTER_BYP4_18", + "CFG_CENTER_IMUX11_7", + "CFG_CENTER_IMUX43_12", + "CFG_CENTER_EE4BEG1_12", + "CFG_CENTER_LH3_1", + "CFG_CENTER_LH3_9", + "CFG_CENTER_IMUX46_9", + "CFG_CENTER_IMUX14_18", + "CFG_CENTER_WL1END0_16", + "CFG_CENTER_LH6_11", + "CFG_CENTER_LOGIC_OUTS_B9_11", + "CFG_CENTER_LOGIC_OUTS_B6_18", + "CFG_CENTER_LH12_10", + "CFG_CENTER_ICAP0_O28", + "CFG_CENTER_LOGIC_OUTS_B16_1", + "CFG_CENTER_EE2BEG2_3", + "CFG_CENTER_LH3_14", + "CFG_CENTER_IMUX1_13", + "CFG_CENTER_ER1BEG3_14", + "CFG_CENTER_ICAP0_O3", + "CFG_CENTER_IMUX16_15", + "CFG_CENTER_LOGIC_OUTS_B4_6", + "CFG_CENTER_EE4BEG3_7", + "CFG_CENTER_SE4BEG1_7", + "CFG_CENTER_CLK1_3", + "CFG_CENTER_IMUX40_1", + "CFG_CENTER_SE4BEG2_10", + "CFG_CENTER_SW2A2_19", + "CFG_CENTER_LH1_17", + "CFG_CENTER_IMUX17_16", + "CFG_CENTER_NW4END0_3", + "CFG_CENTER_LOGIC_OUTS_B3_17", + "CFG_CENTER_WL1END3_15", + "CFG_CENTER_ER1BEG3_10", + "CFG_CENTER_LH9_3", + "CFG_CENTER_WW4B0_17", + "CFG_CENTER_EE2A0_12", + "CFG_CENTER_NW4END3_2", + "CFG_CENTER_IMUX9_10", + "CFG_CENTER_NW4A2_9", + "CFG_CENTER_IMUX8_4", + "CFG_CENTER_LOGIC_OUTS_B12_1", + "CFG_CENTER_WW4C3_10", + "CFG_CENTER_LOGIC_OUTS_B20_10", + "CFG_CENTER_BYP2_2", + "CFG_CENTER_EE2BEG1_16", + "CFG_CENTER_WW4A2_15", + "CFG_CENTER_SW4A1_4", + "CFG_CENTER_WW4A1_1", + "CFG_CENTER_NW4A1_16", + "CFG_CENTER_FAN4_14", + "CFG_CENTER_FAN1_10", + "CFG_CENTER_IMUX1_10", + "CFG_CENTER_BLOCK_OUTS_B3_10", + "CFG_CENTER_LOGIC_OUTS_B11_17", + "CFG_CENTER_IMUX14_2", + "CFG_CENTER_WW2A2_0", + "CFG_CENTER_WW2A1_17", + "CFG_CENTER_NW4END2_17", + "CFG_CENTER_BSCAN3_TDO", + "CFG_CENTER_IMUX0_11", + "CFG_CENTER_IMUX45_2", + "CFG_CENTER_IMUX19_11", + "CFG_CENTER_CLK0_4", + "CFG_CENTER_LOGIC_OUTS_B14_16", + "CFG_CENTER_SE4C2_0", + "CFG_CENTER_IMUX24_15", + "CFG_CENTER_LOGIC_OUTS_B6_6", + "CFG_CENTER_MID_USR_ACCESS_DATA2", + "CFG_CENTER_LOGIC_OUTS_B8_5", + "CFG_CENTER_NE4BEG1_14", + "CFG_CENTER_NE2A1_15", + "CFG_CENTER_IMUX25_8", + "CFG_CENTER_BYP6_3", + "CFG_CENTER_WW4C1_16", + "CFG_CENTER_IMUX37_2", + "CFG_CENTER_LH9_12", + "CFG_CENTER_IMUX37_14", + "CFG_CENTER_IMUX23_7", + "CFG_CENTER_NW2A3_3", + "CFG_CENTER_BLOCK_OUTS_B0_2", + "CFG_CENTER_NE2A3_2", + "CFG_CENTER_WR1END2_2", + "CFG_CENTER_WW2A0_7", + "CFG_CENTER_BYP5_10", + "CFG_CENTER_EE2BEG2_16", + "CFG_CENTER_BSCAN3_TDI", + "CFG_CENTER_IMUX39_14", + "CFG_CENTER_WW2END2_1", + "CFG_CENTER_EE4BEG1_0", + "CFG_CENTER_WW4END2_2", + "CFG_CENTER_BLOCK_OUTS_B3_17", + "CFG_CENTER_IMUX28_12", + "CFG_CENTER_IMUX18_11", + "CFG_CENTER_SW2A2_14", + "CFG_CENTER_WW4A1_6", + "CFG_CENTER_SW4A2_17", + "CFG_CENTER_PMVIOB_A1", + "CFG_CENTER_NE4C3_14", + "CFG_CENTER_WW2A1_10", + "CFG_CENTER_LH7_12", + "CFG_CENTER_WR1END3_2", + "CFG_CENTER_WW4END3_7", + "CFG_CENTER_BYP7_0", + "CFG_CENTER_BYP6_14", + "CFG_CENTER_EE4C2_5", + "CFG_CENTER_IMUX10_2", + "CFG_CENTER_EE2BEG3_2", + "CFG_CENTER_LOGIC_OUTS_B20_4", + "CFG_CENTER_WL1END1_11", + "CFG_CENTER_EE2A0_6", + "CFG_CENTER_LH5_6", + "CFG_CENTER_BSCAN2_SHIFT", + "CFG_CENTER_IMUX46_6", + "CFG_CENTER_EE2A1_18", + "CFG_CENTER_IMUX6_12", + "CFG_CENTER_IMUX6_19", + "CFG_CENTER_SE4BEG1_19", + "CFG_CENTER_EE4BEG0_1", + "CFG_CENTER_SE2A2_0", + "CFG_CENTER_SW4END1_12", + "CFG_CENTER_IMUX1_17", + "CFG_CENTER_EE4BEG2_2", + "CFG_CENTER_IMUX43_8", + "CFG_CENTER_IMUX22_4", + "CFG_CENTER_BSCAN2_TCK", + "CFG_CENTER_WW4END0_5", + "CFG_CENTER_SW4END1_19", + "CFG_CENTER_SW4END1_13", + "CFG_CENTER_WW4B0_13", + "CFG_CENTER_EE4B1_15", + "CFG_CENTER_WW4B2_10", + "CFG_CENTER_IMUX46_0", + "CFG_CENTER_USR_ACCESS_DATA1", + "CFG_CENTER_SW4END2_7", + "CFG_CENTER_WW4A1_4", + "CFG_CENTER_SW4A2_18", + "CFG_CENTER_FAN3_3", + "CFG_CENTER_NW2A2_15", + "CFG_CENTER_LOGIC_OUTS_B17_13", + "CFG_CENTER_SE2A2_3", + "CFG_CENTER_IMUX31_9", + "CFG_CENTER_EE4B3_9", + "CFG_CENTER_LH7_14", + "CFG_CENTER_NE4BEG2_8", + "CFG_CENTER_LOGIC_OUTS_B8_17", + "CFG_CENTER_SW4A3_11", + "CFG_CENTER_SE4BEG2_8", + "CFG_CENTER_ICAP0_I3", + "CFG_CENTER_BYP0_18", + "CFG_CENTER_IMUX16_2", + "CFG_CENTER_SW4END1_1", + "CFG_CENTER_SW4A2_2", + "CFG_CENTER_BYP4_9", + "CFG_CENTER_WW2END2_2", + "CFG_CENTER_BYP2_13", + "CFG_CENTER_IMUX3_10", + "CFG_CENTER_SW2A2_5", + "CFG_CENTER_LOGIC_OUTS_B20_16", + "CFG_CENTER_LOGIC_OUTS_B0_13", + "CFG_CENTER_IMUX8_19", + "CFG_CENTER_LH1_13", + "CFG_CENTER_SE4BEG0_3", + "CFG_CENTER_NW4END1_13", + "CFG_CENTER_LOGIC_OUTS_B1_0", + "CFG_CENTER_SW4END2_8", + "CFG_CENTER_IMUX6_14", + "CFG_CENTER_CTRL1_1", + "CFG_CENTER_EL1BEG2_8", + "CFG_CENTER_NE4BEG0_11", + "CFG_CENTER_SE2A0_10", + "CFG_CENTER_BLOCK_OUTS_B0_11", + "CFG_CENTER_BYP2_0", + "CFG_CENTER_LH7_5", + "CFG_CENTER_IMUX11_8", + "CFG_CENTER_EE4B2_13", + "CFG_CENTER_IMUX41_6", + "CFG_CENTER_LH12_17", + "CFG_CENTER_WR1END0_2", + "CFG_CENTER_WW4A3_4", + "CFG_CENTER_EE2BEG3_17", + "CFG_CENTER_CTRL0_4", + "CFG_CENTER_IMUX41_12", + "CFG_CENTER_SW4A2_16", + "CFG_CENTER_ICAP1_I16", + "CFG_CENTER_LOGIC_OUTS_B10_9", + "CFG_CENTER_SE4BEG2_15", + "CFG_CENTER_EE4BEG0_19", + "CFG_CENTER_IMUX34_18", + "CFG_CENTER_IMUX28_4", + "CFG_CENTER_NE4BEG1_4", + "CFG_CENTER_FRAME_ECC_SYNDROME9", + "CFG_CENTER_IMUX44_17", + "CFG_CENTER_EE4BEG1_15", + "CFG_CENTER_ICAP0_I10", + "CFG_CENTER_IMUX22_19", + "CFG_CENTER_NE4C3_18", + "CFG_CENTER_EE4B0_12", + "CFG_CENTER_CLK1_0", + "CFG_CENTER_CK_IN13", + "CFG_CENTER_IMUX45_15", + "CFG_CENTER_IMUX16_18", + "CFG_CENTER_IMUX2_4", + "CFG_CENTER_LOGIC_OUTS_B9_10", + "CFG_CENTER_SE4BEG1_17", + "CFG_CENTER_NE2A3_5", + "CFG_CENTER_SE4BEG1_4", + "CFG_CENTER_WL1END3_2", + "CFG_CENTER_ER1BEG2_2", + "CFG_CENTER_SW4A3_18", + "CFG_CENTER_LOGIC_OUTS_B9_7", + "CFG_CENTER_ICAP1_I10", + "CFG_CENTER_NE2A0_10", + "CFG_CENTER_SE4BEG3_14", + "CFG_CENTER_LOGIC_OUTS_B5_6", + "CFG_CENTER_EL1BEG3_3", + "CFG_CENTER_EE4A1_6", + "CFG_CENTER_WW4B0_3", + "CFG_CENTER_LH1_15", + "CFG_CENTER_BYP1_19", + "CFG_CENTER_LH8_3", + "CFG_CENTER_NW2A0_4", + "CFG_CENTER_IMUX5_2", + "CFG_CENTER_EE2A0_3", + "CFG_CENTER_IMUX14_15", + "CFG_CENTER_WL1END3_8", + "CFG_CENTER_BYP1_8", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA18", + "CFG_CENTER_IMUX16_0", + "CFG_CENTER_WW2END3_17", + "CFG_CENTER_BLOCK_OUTS_B3_0", + "CFG_CENTER_IMUX6_3", + "CFG_CENTER_WW4END0_2", + "CFG_CENTER_EE4BEG0_2", + "CFG_CENTER_EE2BEG3_11", + "CFG_CENTER_EE2BEG3_19", + "CFG_CENTER_SW4END2_5", + "CFG_CENTER_EE4A3_4", + "CFG_CENTER_LH8_12", + "CFG_CENTER_WW4END1_9", + "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", + "CFG_CENTER_STARTUP_USRDONETS", + "CFG_CENTER_IMUX42_3", + "CFG_CENTER_ICAP1_I18", + "CFG_CENTER_LOGIC_OUTS_B2_1", + "CFG_CENTER_CLK0_5", + "CFG_CENTER_EL1BEG0_18", + "CFG_CENTER_IMUX1_3", + "CFG_CENTER_WW4A3_3", + "CFG_CENTER_IMUX3_6", + "CFG_CENTER_IMUX32_1", + "CFG_CENTER_CFG_IO_ACCESS_INITBO", + "CFG_CENTER_SE4BEG3_7", + "CFG_CENTER_WW4C0_11", + "CFG_CENTER_BYP7_8", + "CFG_CENTER_IMUX33_3", + "CFG_CENTER_LH12_12", + "CFG_CENTER_NW2A2_10", + "CFG_CENTER_FAN2_0", + "CFG_CENTER_IMUX1_8", + "CFG_CENTER_BSCAN1_SHIFT", + "CFG_CENTER_ER1BEG2_5", + "CFG_CENTER_WW4END1_1", + "CFG_CENTER_LOGIC_OUTS_B9_12", + "CFG_CENTER_IMUX22_13", + "CFG_CENTER_NW4END3_14", + "CFG_CENTER_LH5_2", + "CFG_CENTER_LOGIC_OUTS_B8_4", + "CFG_CENTER_IMUX29_16", + "CFG_CENTER_SW2A0_15", + "CFG_CENTER_IMUX31_11", + "CFG_CENTER_LH6_12", + "CFG_CENTER_WW4A0_9", + "CFG_CENTER_IMUX24_3", + "CFG_CENTER_EE4C2_13", + "CFG_CENTER_NE2A2_1", + "CFG_CENTER_WW4END0_8", + "CFG_CENTER_SW4END3_9", + "CFG_CENTER_WW4END3_3", + "CFG_CENTER_EL1BEG2_9", + "CFG_CENTER_SW4A1_18", + "CFG_CENTER_IMUX38_19", + "CFG_CENTER_IMUX34_12", + "CFG_CENTER_IMUX44_10", + "CFG_CENTER_IMUX36_12", + "CFG_CENTER_NE2A1_17", + "CFG_CENTER_BYP3_11", + "CFG_CENTER_WW4C3_6", + "CFG_CENTER_WR1END3_12", + "CFG_CENTER_WL1END3_10", + "CFG_CENTER_BLOCK_OUTS_B0_14", + "CFG_CENTER_LOGIC_OUTS_B19_14", + "CFG_CENTER_WL1END3_6", + "CFG_CENTER_IMUX10_10", + "CFG_CENTER_CK_BUFHCLK10", + "CFG_CENTER_WW2A0_19", + "CFG_CENTER_USR_ACCESS_DATA28", + "CFG_CENTER_EE2A0_18", + "CFG_CENTER_ICAP0_I22", + "CFG_CENTER_IMUX0_1", + "CFG_CENTER_CK_BUFRCLK1", + "CFG_CENTER_WR1END1_2", + "CFG_CENTER_CK_IN2", + "CFG_CENTER_IMUX4_3", + "CFG_CENTER_FRAME_ECC_SYNDROME4", + "CFG_CENTER_FAN4_9", + "CFG_CENTER_BYP0_12", + "CFG_CENTER_NE2A0_12", + "CFG_CENTER_LH5_1", + "CFG_CENTER_NE2A2_17", + "CFG_CENTER_WW2A3_1", + "CFG_CENTER_USR_ACCESS_DATA31", + "CFG_CENTER_EE4C2_17", + "CFG_CENTER_IMUX10_19", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA23", + "CFG_CENTER_WW2A1_0", + "CFG_CENTER_IMUX9_9", + "CFG_CENTER_FRAME_ECC_FAR24", + "CFG_CENTER_BYP5_4", + "CFG_CENTER_NW4END2_7", + "CFG_CENTER_PMVIOB_ODIV4", + "CFG_CENTER_IMUX35_10", + "CFG_CENTER_SE4BEG0_4", + "CFG_CENTER_STARTUP_KEYCLEARB", + "CFG_CENTER_EE4BEG2_17", + "CFG_CENTER_FAN4_17", + "CFG_CENTER_LH2_11", + "CFG_CENTER_ICAP1_O23", + "CFG_CENTER_IMUX34_15", + "CFG_CENTER_WL1END2_5", + "CFG_CENTER_IMUX47_2", + "CFG_CENTER_LOGIC_OUTS_B1_5", + "CFG_CENTER_NE4BEG1_9", + "CFG_CENTER_SW4END3_3", + "CFG_CENTER_NE2A3_9", + "CFG_CENTER_LH3_16", + "CFG_CENTER_NE4BEG3_0", + "CFG_CENTER_SW4END3_1", + "CFG_CENTER_STARTUP_CFGCLK", + "CFG_CENTER_LOGIC_OUTS_B4_4", + "CFG_CENTER_ICAP0_I19", + "CFG_CENTER_NW4A3_17", + "CFG_CENTER_IMUX32_7", + "CFG_CENTER_IMUX27_11", + "CFG_CENTER_IMUX47_10", + "CFG_CENTER_EE4A0_8", + "CFG_CENTER_USR_ACCESS_DATA23", + "CFG_CENTER_LOGIC_OUTS_B14_4", + "CFG_CENTER_SW4END0_4", + "CFG_CENTER_BSCAN4_SHIFT", + "CFG_CENTER_NW4END3_19", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA30", + "CFG_CENTER_IMUX23_17", + "CFG_CENTER_LOGIC_OUTS_B14_3", + "CFG_CENTER_LOGIC_OUTS_B7_11", + "CFG_CENTER_WW4END0_6", + "CFG_CENTER_LOGIC_OUTS_B2_17", + "CFG_CENTER_SE4C0_14", + "CFG_CENTER_NW2A2_14", + "CFG_CENTER_FAN3_7", + "CFG_CENTER_WW4B0_8", + "CFG_CENTER_WW4A0_5", + "CFG_CENTER_NW2A3_6", + "CFG_CENTER_EE2A1_3", + "CFG_CENTER_NW4A1_1", + "CFG_CENTER_IMUX6_15", + "CFG_CENTER_LH10_0", + "CFG_CENTER_IMUX18_13", + "CFG_CENTER_FAN4_13", + "CFG_CENTER_IMUX32_6", + "CFG_CENTER_NE4BEG0_5", + "CFG_CENTER_WW2A0_13", + "CFG_CENTER_FAN1_3", + "CFG_CENTER_IMUX13_6", + "CFG_CENTER_IMUX47_8", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA26", + "CFG_CENTER_CK_IN12", + "CFG_CENTER_LOGIC_OUTS_B6_11", + "CFG_CENTER_NW4A1_15", + "CFG_CENTER_NW4END3_8", + "CFG_CENTER_NW2A2_13", + "CFG_CENTER_BLOCK_OUTS_B1_17", + "CFG_CENTER_BYP7_6", + "CFG_CENTER_NW4A0_6", + "CFG_CENTER_WW2A3_0", + "CFG_CENTER_ICAP0_CLK", + "CFG_CENTER_LOGIC_OUTS_B4_14", + "CFG_CENTER_WW2END1_0", + "CFG_CENTER_BYP1_14", + "CFG_CENTER_LOGIC_OUTS_B1_9", + "CFG_CENTER_LH5_19", + "CFG_CENTER_IMUX33_8", + "CFG_CENTER_IMUX19_4", + "CFG_CENTER_WR1END0_11", + "CFG_CENTER_SW4A3_13", + "CFG_CENTER_ER1BEG2_16", + "CFG_CENTER_BSCAN3_SHIFT", + "CFG_CENTER_FAN0_16", + "CFG_CENTER_ICAP0_I6", + "CFG_CENTER_ER1BEG1_11", + "CFG_CENTER_ICAP1_I6", + "CFG_CENTER_NW2A1_3", + "CFG_CENTER_NW2A1_5", + "CFG_CENTER_LOGIC_OUTS_B19_6", + "CFG_CENTER_WW4B0_1", + "CFG_CENTER_SE2A0_11", + "CFG_CENTER_LOGIC_OUTS_B1_11", + "CFG_CENTER_LH3_5", + "CFG_CENTER_EE4A3_8", + "CFG_CENTER_WW4C3_1", + "CFG_CENTER_WW2END0_4", + "CFG_CENTER_IMUX18_10", + "CFG_CENTER_IMUX35_13", + "CFG_CENTER_LH12_11", + "CFG_CENTER_EE2A2_10", + "CFG_CENTER_NW4A1_19", + "CFG_CENTER_FRAME_ECC_SYNBIT3", + "CFG_CENTER_IMUX18_7", + "CFG_CENTER_EE2A1_11", + "CFG_CENTER_IMUX11_19", + "CFG_CENTER_IMUX28_15", + "CFG_CENTER_EE4BEG3_17", + "CFG_CENTER_NE4BEG0_6", + "CFG_CENTER_LH6_1", + "CFG_CENTER_SW4END0_7", + "CFG_CENTER_FRAME_ECC_FAR9", + "CFG_CENTER_IMUX45_3", + "CFG_CENTER_EL1BEG2_1", + "CFG_CENTER_SW2A0_18", + "CFG_CENTER_WW4A1_17", + "CFG_CENTER_WW4END2_4", + "CFG_CENTER_BLOCK_OUTS_B1_1", + "CFG_CENTER_CTRL0_9", + "CFG_CENTER_NE4BEG2_1", + "CFG_CENTER_BYP0_14", + "CFG_CENTER_BLOCK_OUTS_B2_6", + "CFG_CENTER_WR1END3_14", + "CFG_CENTER_LOGIC_OUTS_B6_3", + "CFG_CENTER_LOGIC_OUTS_B13_16", + "CFG_CENTER_FAN7_14", + "CFG_CENTER_ER1BEG0_19", + "CFG_CENTER_IMUX0_12", + "CFG_CENTER_IMUX13_5", + "CFG_CENTER_STARTUP_CFGMCLK", + "CFG_CENTER_EE2BEG1_10", + "CFG_CENTER_WW2END2_3", + "CFG_CENTER_LOGIC_OUTS_B8_16", + "CFG_CENTER_IMUX44_13", + "CFG_CENTER_WL1END1_13", + "CFG_CENTER_IMUX45_7", + "CFG_CENTER_IMUX25_6", + "CFG_CENTER_NW4A2_6", + "CFG_CENTER_LH8_11", + "CFG_CENTER_LH4_13", + "CFG_CENTER_NW4A2_14", + "CFG_CENTER_FAN5_1", + "CFG_CENTER_FAN6_3", + "CFG_CENTER_SW2A1_14", + "CFG_CENTER_ER1BEG0_2", + "CFG_CENTER_CLK0_13", + "CFG_CENTER_BYP5_0", + "CFG_CENTER_WR1END3_18", + "CFG_CENTER_NW4END2_16", + "CFG_CENTER_WW4A0_10", + "CFG_CENTER_LOGIC_OUTS_B6_10", + "CFG_CENTER_SE4BEG1_13", + "CFG_CENTER_LH6_16", + "CFG_CENTER_LH12_1", + "CFG_CENTER_IMUX27_14", + "CFG_CENTER_SW2A1_5", + "CFG_CENTER_BLOCK_OUTS_B1_6", + "CFG_CENTER_LOGIC_OUTS_B9_13", + "CFG_CENTER_WR1END0_12", + "CFG_CENTER_LH1_4", + "CFG_CENTER_IMUX16_3", + "CFG_CENTER_CK_BUFRCLK0", + "CFG_CENTER_EE4BEG2_16", + "CFG_CENTER_WW4C1_0", + "CFG_CENTER_LOGIC_OUTS_B7_8", + "CFG_CENTER_WW4A3_7", + "CFG_CENTER_SE4C3_10", + "CFG_CENTER_SE2A1_0", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA8", + "CFG_CENTER_NW2A2_17", + "CFG_CENTER_ICAP0_O26", + "CFG_CENTER_WW2END3_12", + "CFG_CENTER_LOGIC_OUTS_B7_9", + "CFG_CENTER_WW2A1_7", + "CFG_CENTER_LH2_18", + "CFG_CENTER_BYP2_17", + "CFG_CENTER_LH2_13", + "CFG_CENTER_CAPTURE_CAP", + "CFG_CENTER_IMUX7_0", + "CFG_CENTER_EE4C0_8", + "CFG_CENTER_ICAP1_I15", + "CFG_CENTER_IMUX43_14", + "CFG_CENTER_WL1END1_15", + "CFG_CENTER_BSCAN3_RUNTEST", + "CFG_CENTER_LOGIC_OUTS_B8_18", + "CFG_CENTER_FRAME_ECC_FAR14", + "CFG_CENTER_STARTUP_EOS", + "CFG_CENTER_ICAP1_I4", + "CFG_CENTER_SE4BEG0_11", + "CFG_CENTER_LOGIC_OUTS_B10_4", + "CFG_CENTER_WW4END0_17", + "CFG_CENTER_SE2A1_1", + "CFG_CENTER_IMUX11_12", + "CFG_CENTER_IMUX36_18", + "CFG_CENTER_LH7_17", + "CFG_CENTER_SE2A2_12", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA9", + "CFG_CENTER_FAN6_19", + "CFG_CENTER_EE2A3_9", + "CFG_CENTER_IMUX33_14", + "CFG_CENTER_NW4A2_2", + "CFG_CENTER_NW2A3_19", + "CFG_CENTER_USR_ACCESS_DATA19", + "CFG_CENTER_LOGIC_OUTS_B6_4", + "CFG_CENTER_SE2A1_16", + "CFG_CENTER_NW2A1_12", + "CFG_CENTER_EE4A3_17", + "CFG_CENTER_WW4C3_15", + "CFG_CENTER_SE4BEG1_5", + "CFG_CENTER_ICAP0_O17", + "CFG_CENTER_EE4C2_10", + "CFG_CENTER_WW4A0_19", + "CFG_CENTER_LOGIC_OUTS_B12_10", + "CFG_CENTER_WW2A0_3", + "CFG_CENTER_SW2A2_17", + "CFG_CENTER_WW4END0_15", + "CFG_CENTER_LH1_6", + "CFG_CENTER_SW4A0_10", + "CFG_CENTER_NE4C3_16", + "CFG_CENTER_LH12_13", + "CFG_CENTER_SE4BEG0_14", + "CFG_CENTER_EE2BEG3_8", + "CFG_CENTER_BYP4_19", + "CFG_CENTER_IMUX5_15", + "CFG_CENTER_IMUX23_15", + "CFG_CENTER_NE2A3_18", + "CFG_CENTER_LOGIC_OUTS_B0_16", + "CFG_CENTER_ER1BEG0_16", + "CFG_CENTER_LOGIC_OUTS_B13_13", + "CFG_CENTER_SW4A2_8", + "CFG_CENTER_LOGIC_OUTS_B13_19", + "CFG_CENTER_WL1END1_9", + "CFG_CENTER_BYP0_3", + "CFG_CENTER_IMUX21_5", + "CFG_CENTER_BYP0_1", + "CFG_CENTER_IMUX19_15", + "CFG_CENTER_SE4C0_11", + "CFG_CENTER_WW4B2_18", + "CFG_CENTER_IMUX17_9", + "CFG_CENTER_IMUX23_5", + "CFG_CENTER_EE4BEG0_16", + "CFG_CENTER_LH2_19", + "CFG_CENTER_ICAP1_O8", + "CFG_CENTER_IMUX41_4", + "CFG_CENTER_LH12_6", + "CFG_CENTER_LOGIC_OUTS_B15_6", + "CFG_CENTER_EE4C2_2", + "CFG_CENTER_EE4BEG1_19", + "CFG_CENTER_LOGIC_OUTS_B9_17", + "CFG_CENTER_NE2A0_7", + "CFG_CENTER_LOGIC_OUTS_B3_10", + "CFG_CENTER_WW4C0_4", + "CFG_CENTER_WR1END3_9", + "CFG_CENTER_IMUX21_15", + "CFG_CENTER_EE2A2_0", + "CFG_CENTER_IMUX11_5", + "CFG_CENTER_WW4END1_15", + "CFG_CENTER_FAN0_14", + "CFG_CENTER_ICAP1_O3", + "CFG_CENTER_BYP0_15", + "CFG_CENTER_IMUX21_8", + "CFG_CENTER_LOGIC_OUTS_B12_11", + "CFG_CENTER_WW4END1_7", + "CFG_CENTER_LOGIC_OUTS_B8_19", + "CFG_CENTER_EE4BEG3_10", + "CFG_CENTER_LH1_19", + "CFG_CENTER_IMUX40_10", + "CFG_CENTER_EE2A3_6", + "CFG_CENTER_FAN1_13", + "CFG_CENTER_LH6_10", + "CFG_CENTER_NE2A3_10", + "CFG_CENTER_LH11_17", + "CFG_CENTER_IMUX41_2", + "CFG_CENTER_LOGIC_OUTS_B16_0", + "CFG_CENTER_USR_ACCESS_DATA12", + "CFG_CENTER_LH4_14", + "CFG_CENTER_SW4END0_5", + "CFG_CENTER_IMUX6_16", + "CFG_CENTER_IMUX6_9", + "CFG_CENTER_EE2A3_1", + "CFG_CENTER_EE4A2_2", + "CFG_CENTER_LOGIC_OUTS_B10_8", + "CFG_CENTER_LH9_1", + "CFG_CENTER_IMUX44_18", + "CFG_CENTER_BYP7_18", + "CFG_CENTER_ER1BEG3_15", + "CFG_CENTER_FAN1_7", + "CFG_CENTER_NW4A3_1", + "CFG_CENTER_WW4END3_5", + "CFG_CENTER_WW4B1_15", + "CFG_CENTER_NE4C3_15", + "CFG_CENTER_LOGIC_OUTS_B9_5", + "CFG_CENTER_LOGIC_OUTS_B23_4", + "CFG_CENTER_IMUX20_2", + "CFG_CENTER_EE4B2_1", + "CFG_CENTER_EL1BEG2_5", + "CFG_CENTER_LOGIC_OUTS_B4_18", + "CFG_CENTER_LH1_11", + "CFG_CENTER_BYP3_1", + "CFG_CENTER_WR1END2_12", + "CFG_CENTER_ICAP0_I17", + "CFG_CENTER_FAN1_8", + "CFG_CENTER_WR1END2_14", + "CFG_CENTER_EL1BEG2_17", + "CFG_CENTER_SW4A3_12", + "CFG_CENTER_SW2A3_8", + "CFG_CENTER_LOGIC_OUTS_B18_9", + "CFG_CENTER_EL1BEG1_9", + "CFG_CENTER_NE4BEG1_3", + "CFG_CENTER_USR_ACCESS_DATA13", + "CFG_CENTER_IMUX37_11", + "CFG_CENTER_IMUX19_18", + "CFG_CENTER_SE4C3_18", + "CFG_CENTER_BYP0_9", + "CFG_CENTER_IMUX44_2", + "CFG_CENTER_EE4BEG0_11", + "CFG_CENTER_EE2BEG3_14", + "CFG_CENTER_NE2A2_8", + "CFG_CENTER_WW4A3_17", + "CFG_CENTER_LOGIC_OUTS_B7_19", + "CFG_CENTER_IMUX42_10", + "CFG_CENTER_EE4A2_17", + "CFG_CENTER_IMUX36_17", + "CFG_CENTER_BYP6_8", + "CFG_CENTER_IMUX31_5", + "CFG_CENTER_IMUX25_17", + "CFG_CENTER_IMUX25_1", + "CFG_CENTER_FAN6_2", + "CFG_CENTER_LH2_16", + "CFG_CENTER_LOGIC_OUTS_B15_13", + "CFG_CENTER_FRAME_ECC_FAR8", + "CFG_CENTER_WW2A2_12", + "CFG_CENTER_FAN4_3", + "CFG_CENTER_IMUX20_13", + "CFG_CENTER_IMUX1_9", + "CFG_CENTER_EE4B2_8", + "CFG_CENTER_LOGIC_OUTS_B21_12", + "CFG_CENTER_CTRL0_7", + "CFG_CENTER_CK_BUFHCLK4", + "CFG_CENTER_NE4BEG3_19", + "CFG_CENTER_IMUX12_7", + "CFG_CENTER_LOGIC_OUTS_B18_12", + "CFG_CENTER_LH11_7", + "CFG_CENTER_LOGIC_OUTS_B2_7", + "CFG_CENTER_IMUX1_18", + "CFG_CENTER_ICAP0_I1", + "CFG_CENTER_WR1END0_14", + "CFG_CENTER_LH6_18", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA12", + "CFG_CENTER_LH9_11", + "CFG_CENTER_EE4C0_4", + "CFG_CENTER_NW2A0_7", + "CFG_CENTER_BYP4_1", + "CFG_CENTER_WR1END1_9", + "CFG_CENTER_NE2A3_6", + "CFG_CENTER_FAN3_5", + "CFG_CENTER_NW4A1_3", + "CFG_CENTER_NE4C3_10", + "CFG_CENTER_WW4END1_4", + "CFG_CENTER_WL1END1_19", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA19", + "CFG_CENTER_SE2A2_10", + "CFG_CENTER_FAN3_18", + "CFG_CENTER_NE2A0_16", + "CFG_CENTER_LOGIC_OUTS_B3_16", + "CFG_CENTER_NE2A0_18", + "CFG_CENTER_EE4C2_8", + "CFG_CENTER_FAN0_0", + "CFG_CENTER_NE4C2_13", + "CFG_CENTER_IMUX33_18", + "CFG_CENTER_WW2A2_4", + "CFG_CENTER_CTRL0_2", + "CFG_CENTER_LOGIC_OUTS_B1_6", + "CFG_CENTER_WW4C2_6", + "CFG_CENTER_IMUX44_3", + "CFG_CENTER_IMUX30_13", + "CFG_CENTER_EE4BEG0_17", + "CFG_CENTER_WW2END3_18", + "CFG_CENTER_EE4BEG2_15", + "CFG_CENTER_LOGIC_OUTS_B2_4", + "CFG_CENTER_CTRL0_8", + "CFG_CENTER_IMUX22_8", + "CFG_CENTER_NE4C1_12", + "CFG_CENTER_EE4B0_9", + "CFG_CENTER_IMUX19_6", + "CFG_CENTER_IMUX20_8", + "CFG_CENTER_IMUX31_13", + "CFG_CENTER_IMUX23_9", + "CFG_CENTER_SW2A2_0", + "CFG_CENTER_WW2END1_11", + "CFG_CENTER_IMUX37_7", + "CFG_CENTER_NW4A2_16", + "CFG_CENTER_WW4B2_0", + "CFG_CENTER_IMUX21_17", + "CFG_CENTER_CK_BUFHCLK6", + "CFG_CENTER_IMUX32_3", + "CFG_CENTER_NE2A1_12", + "CFG_CENTER_LOGIC_OUTS_B15_12", + "CFG_CENTER_LOGIC_OUTS_B10_14", + "CFG_CENTER_SE4BEG2_4", + "CFG_CENTER_FAN0_18", + "CFG_CENTER_EE2A0_16", + "CFG_CENTER_IMUX39_3", + "CFG_CENTER_SE2A1_7", + "CFG_CENTER_EE2BEG0_16", + "CFG_CENTER_WW4B0_6", + "CFG_CENTER_SW4END0_6", + "CFG_CENTER_SW4A0_5", + "CFG_CENTER_IMUX36_9", + "CFG_CENTER_FAN2_18", + "CFG_CENTER_BLOCK_OUTS_B3_19", + "CFG_CENTER_BYP7_13", + "CFG_CENTER_SE4C2_19", + "CFG_CENTER_IMUX11_16", + "CFG_CENTER_WW2END2_9", + "CFG_CENTER_EE4A2_8", + "CFG_CENTER_LOGIC_OUTS_B9_16", + "CFG_CENTER_NE4C2_10", + "CFG_CENTER_WW4B1_10", + "CFG_CENTER_EE4BEG0_14", + "CFG_CENTER_IMUX35_11", + "CFG_CENTER_WW4C0_15", + "CFG_CENTER_EE2A2_13", + "CFG_CENTER_BYP3_2", + "CFG_CENTER_ER1BEG2_18", + "CFG_CENTER_IMUX40_7", + "CFG_CENTER_NW2A1_8", + "CFG_CENTER_IMUX11_11", + "CFG_CENTER_LOGIC_OUTS_B23_5", + "CFG_CENTER_WL1END0_11", + "CFG_CENTER_EE4BEG2_10", + "CFG_CENTER_SW4END1_6", + "CFG_CENTER_LOGIC_OUTS_B0_12", + "CFG_CENTER_WL1END2_19", + "CFG_CENTER_SW2A2_7", + "CFG_CENTER_CK_BUFHCLK11", + "CFG_CENTER_IMUX37_4", + "CFG_CENTER_LH4_8", + "CFG_CENTER_MID_CFG_IO_ACCESS_VGGCOMPOUT", + "CFG_CENTER_WW4C3_0", + "CFG_CENTER_EE2A1_9", + "CFG_CENTER_IMUX32_9", + "CFG_CENTER_BSCAN2_TDI", + "CFG_CENTER_WW4A1_2", "CFG_CENTER_SE4BEG3_16", - "CFG_CENTER_CFG_IO_ACCESS_PUDCB" + "CFG_CENTER_IMUX28_5", + "CFG_CENTER_CLK0_14", + "CFG_CENTER_WW2A2_16", + "CFG_CENTER_IMUX25_12", + "CFG_CENTER_NE2A1_19", + "CFG_CENTER_BLOCK_OUTS_B0_8", + "CFG_CENTER_NW2A0_2", + "CFG_CENTER_IMUX9_4", + "CFG_CENTER_FRAME_ECC_SYNDROME12", + "CFG_CENTER_NW2A3_2", + "CFG_CENTER_NE4C3_0", + "CFG_CENTER_NE4BEG0_16", + "CFG_CENTER_LH3_18", + "CFG_CENTER_WW4END3_13", + "CFG_CENTER_NW4A0_18", + "CFG_CENTER_NW2A3_1", + "CFG_CENTER_IMUX47_1", + "CFG_CENTER_IMUX30_0", + "CFG_CENTER_NE2A0_15", + "CFG_CENTER_IMUX0_8", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA23", + "CFG_CENTER_LOGIC_OUTS_B8_12", + "CFG_CENTER_BSCAN2_UPDATE", + "CFG_CENTER_BYP6_12", + "CFG_CENTER_IMUX32_15", + "CFG_CENTER_LH8_14", + "CFG_CENTER_IMUX5_4", + "CFG_CENTER_IMUX27_3", + "CFG_CENTER_BYP0_19", + "CFG_CENTER_IMUX17_6", + "CFG_CENTER_LOGIC_OUTS_B18_10", + "CFG_CENTER_WW4B1_12", + "CFG_CENTER_IMUX0_5", + "CFG_CENTER_WW4A2_8", + "CFG_CENTER_IMUX28_18", + "CFG_CENTER_NW4A3_14", + "CFG_CENTER_LOGIC_OUTS_B18_19", + "CFG_CENTER_WW2END3_19", + "CFG_CENTER_ER1BEG0_6", + "CFG_CENTER_LOGIC_OUTS_B11_9", + "CFG_CENTER_IMUX8_7", + "CFG_CENTER_MID_USR_ACCESS_DATA13", + "CFG_CENTER_EL1BEG2_16", + "CFG_CENTER_NW2A3_5", + "CFG_CENTER_FRAME_ECC_SYNDROME3", + "CFG_CENTER_ER1BEG1_15", + "CFG_CENTER_IMUX8_1", + "CFG_CENTER_IMUX38_14", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA12", + "CFG_CENTER_BYP5_11", + "CFG_CENTER_EE4A2_1", + "CFG_CENTER_IMUX33_19", + "CFG_CENTER_LH2_12", + "CFG_CENTER_LH10_15", + "CFG_CENTER_IMUX27_5", + "CFG_CENTER_EE2BEG3_5", + "CFG_CENTER_BYP3_19", + "CFG_CENTER_WR1END0_8", + "CFG_CENTER_DCIRESET_LOCKED", + "CFG_CENTER_WW2END2_11", + "CFG_CENTER_LH3_12", + "CFG_CENTER_BYP3_9", + "CFG_CENTER_WW4B1_19", + "CFG_CENTER_SE4C3_11", + "CFG_CENTER_EE2BEG3_7", + "CFG_CENTER_WW4C0_14", + "CFG_CENTER_EE4A0_1", + "CFG_CENTER_EE2BEG2_11", + "CFG_CENTER_EE4C2_14", + "CFG_CENTER_LOGIC_OUTS_B1_16", + "CFG_CENTER_LOGIC_OUTS_B17_16", + "CFG_CENTER_NE4BEG2_7", + "CFG_CENTER_LOGIC_OUTS_B21_6", + "CFG_CENTER_CTRL0_5", + "CFG_CENTER_BYP6_7", + "CFG_CENTER_NW4A0_9", + "CFG_CENTER_IMUX26_8", + "CFG_CENTER_IMUX5_16", + "CFG_CENTER_EL1BEG2_19", + "CFG_CENTER_BLOCK_OUTS_B1_8", + "CFG_CENTER_CFG_IO_ACCESS_MODE0", + "CFG_CENTER_EE4A1_9", + "CFG_CENTER_LH2_15", + "CFG_CENTER_IMUX11_13", + "CFG_CENTER_LH12_3", + "CFG_CENTER_ICAP0_I20", + "CFG_CENTER_LOGIC_OUTS_B3_11", + "CFG_CENTER_LOGIC_OUTS_B8_9", + "CFG_CENTER_IMUX9_17", + "CFG_CENTER_BYP2_10", + "CFG_CENTER_EE2A1_15", + "CFG_CENTER_LOGIC_OUTS_B16_5", + "CFG_CENTER_EL1BEG0_2", + "CFG_CENTER_WW4B2_16", + "CFG_CENTER_IMUX35_8", + "CFG_CENTER_BYP5_13", + "CFG_CENTER_WR1END1_19", + "CFG_CENTER_IMUX2_6", + "CFG_CENTER_CFG_IO_ACCESS_RDWRB", + "CFG_CENTER_LOGIC_OUTS_B19_10", + "CFG_CENTER_IMUX20_9", + "CFG_CENTER_IMUX46_11", + "CFG_CENTER_IMUX44_16", + "CFG_CENTER_LOGIC_OUTS_B18_2", + "CFG_CENTER_EE4C3_15", + "CFG_CENTER_BYP4_17", + "CFG_CENTER_WW2END1_9", + "CFG_CENTER_EE2A1_12", + "CFG_CENTER_BSCAN2_TMS", + "CFG_CENTER_LOGIC_OUTS_B3_14", + "CFG_CENTER_SW4A3_7", + "CFG_CENTER_IMUX0_19", + "CFG_CENTER_FAN0_3", + "CFG_CENTER_WL1END0_12", + "CFG_CENTER_IMUX6_8", + "CFG_CENTER_EE2BEG2_17", + "CFG_CENTER_WW4B0_2", + "CFG_CENTER_IMUX46_4", + "CFG_CENTER_EE4A1_3", + "CFG_CENTER_BYP6_4", + "CFG_CENTER_IMUX7_15", + "CFG_CENTER_SE4C1_6", + "CFG_CENTER_WW4C3_18", + "CFG_CENTER_IMUX30_17", + "CFG_CENTER_LOGIC_OUTS_B21_8", + "CFG_CENTER_EE2A3_17", + "CFG_CENTER_ER1BEG1_10", + "CFG_CENTER_NW4END0_7", + "CFG_CENTER_LOGIC_OUTS_B4_8", + "CFG_CENTER_WW4A3_15", + "CFG_CENTER_EE2A3_0", + "CFG_CENTER_LH2_7", + "CFG_CENTER_IMUX37_16", + "CFG_CENTER_SE4C1_7", + "CFG_CENTER_SE2A3_5", + "CFG_CENTER_IMUX38_9", + "CFG_CENTER_IMUX14_13", + "CFG_CENTER_WW4B2_12", + "CFG_CENTER_IMUX32_8", + "CFG_CENTER_FAN7_19", + "CFG_CENTER_EE2BEG2_5", + "CFG_CENTER_EL1BEG3_19", + "CFG_CENTER_IMUX32_12", + "CFG_CENTER_WW4A1_12", + "CFG_CENTER_SE4BEG1_16", + "CFG_CENTER_LOGIC_OUTS_B5_11", + "CFG_CENTER_LOGIC_OUTS_B18_1", + "CFG_CENTER_LOGIC_OUTS_B8_8", + "CFG_CENTER_WL1END2_15", + "CFG_CENTER_LOGIC_OUTS_B0_1", + "CFG_CENTER_IMUX42_1", + "CFG_CENTER_SE2A2_18", + "CFG_CENTER_WW2A1_11", + "CFG_CENTER_LOGIC_OUTS_B7_18", + "CFG_CENTER_FRAME_ECC_SYNDROME1", + "CFG_CENTER_LH12_19", + "CFG_CENTER_WW2A1_15", + "CFG_CENTER_SE4BEG1_11", + "CFG_CENTER_FAN7_11", + "CFG_CENTER_FAN6_0", + "CFG_CENTER_NE2A3_4", + "CFG_CENTER_LOGIC_OUTS_B7_17", + "CFG_CENTER_LH10_8", + "CFG_CENTER_FAN3_13", + "CFG_CENTER_BSCAN4_TDI", + "CFG_CENTER_WW4B1_6", + "CFG_CENTER_LH9_8", + "CFG_CENTER_LH6_8", + "CFG_CENTER_CLK0_3", + "CFG_CENTER_FAN7_12", + "CFG_CENTER_EE4B3_13", + "CFG_CENTER_IMUX13_4", + "CFG_CENTER_BYP4_15", + "CFG_CENTER_ICAP1_O28", + "CFG_CENTER_NE2A2_11", + "CFG_CENTER_LH7_3", + "CFG_CENTER_LOGIC_OUTS_B22_4", + "CFG_CENTER_EE4B3_10", + "CFG_CENTER_WW4C2_0", + "CFG_CENTER_IMUX1_4", + "CFG_CENTER_WW4B0_7", + "CFG_CENTER_PMVIOB_EN", + "CFG_CENTER_EE2BEG1_6", + "CFG_CENTER_IMUX2_18", + "CFG_CENTER_EE4C2_0", + "CFG_CENTER_LOGIC_OUTS_B9_9", + "CFG_CENTER_SW2A0_11", + "CFG_CENTER_CLK0_17", + "CFG_CENTER_WW2END1_18", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA13", + "CFG_CENTER_WW4A0_6", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA29", + "CFG_CENTER_EE4C2_18", + "CFG_CENTER_LH4_19", + "CFG_CENTER_SE4C0_10", + "CFG_CENTER_IMUX2_19", + "CFG_CENTER_NE4C3_6", + "CFG_CENTER_EE2A0_11", + "CFG_CENTER_ER1BEG0_5", + "CFG_CENTER_SE2A3_1", + "CFG_CENTER_WW4END3_19", + "CFG_CENTER_IMUX4_4", + "CFG_CENTER_EE4BEG1_1", + "CFG_CENTER_EL1BEG1_11", + "CFG_CENTER_IMUX37_5", + "CFG_CENTER_BLOCK_OUTS_B0_16", + "CFG_CENTER_SW4A3_5", + "CFG_CENTER_EE4A3_14", + "CFG_CENTER_CK_BUFHCLK5", + "CFG_CENTER_WW4C2_2", + "CFG_CENTER_LOGIC_OUTS_B14_9", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA30", + "CFG_CENTER_EE2A1_19", + "CFG_CENTER_EE2BEG0_2", + "CFG_CENTER_LH1_2", + "CFG_CENTER_IMUX29_17", + "CFG_CENTER_WW4END1_12", + "CFG_CENTER_SW4A0_14", + "CFG_CENTER_IMUX31_10", + "CFG_CENTER_CTRL0_1", + "CFG_CENTER_IMUX26_6", + "CFG_CENTER_LOGIC_OUTS_B18_18", + "CFG_CENTER_SW4A1_11", + "CFG_CENTER_BYP0_11", + "CFG_CENTER_BLOCK_OUTS_B3_7", + "CFG_CENTER_ER1BEG0_1", + "CFG_CENTER_NW4A1_14", + "CFG_CENTER_LOGIC_OUTS_B15_9", + "CFG_CENTER_LOGIC_OUTS_B1_17", + "CFG_CENTER_LOGIC_OUTS_B14_7", + "CFG_CENTER_WW4A2_9", + "CFG_CENTER_EE4C0_7", + "CFG_CENTER_BYP7_16", + "CFG_CENTER_LOGIC_OUTS_B22_14", + "CFG_CENTER_ICAP1_CLK", + "CFG_CENTER_NE2A2_7", + "CFG_CENTER_LH12_8", + "CFG_CENTER_IMUX25_19", + "CFG_CENTER_LOGIC_OUTS_B4_11", + "CFG_CENTER_WR1END1_7", + "CFG_CENTER_EE4B3_12", + "CFG_CENTER_LOGIC_OUTS_B12_13", + "CFG_CENTER_BYP1_10", + "CFG_CENTER_ICAP0_CSIB", + "CFG_CENTER_NE4BEG1_2", + "CFG_CENTER_NE2A3_15", + "CFG_CENTER_IMUX43_9", + "CFG_CENTER_IMUX5_0", + "CFG_CENTER_EE4A1_12", + "CFG_CENTER_LOGIC_OUTS_B7_14", + "CFG_CENTER_NE4BEG2_18", + "CFG_CENTER_IMUX23_0", + "CFG_CENTER_SE4C0_15", + "CFG_CENTER_IMUX2_15", + "CFG_CENTER_ICAP0_I30", + "CFG_CENTER_NE4BEG0_13", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA17", + "CFG_CENTER_BSCAN4_CAPTURE", + "CFG_CENTER_SE2A0_7", + "CFG_CENTER_BYP1_13", + "CFG_CENTER_NW4END0_2", + "CFG_CENTER_WW2A0_5", + "CFG_CENTER_ER1BEG0_18", + "CFG_CENTER_IMUX18_0", + "CFG_CENTER_LOGIC_OUTS_B23_14", + "CFG_CENTER_SE2A1_4", + "CFG_CENTER_ICAP0_O24", + "CFG_CENTER_LH9_9", + "CFG_CENTER_IMUX42_9", + "CFG_CENTER_FAN7_17", + "CFG_CENTER_SW2A2_16", + "CFG_CENTER_NE4BEG2_6", + "CFG_CENTER_IMUX45_19", + "CFG_CENTER_SW4A2_7", + "CFG_CENTER_WL1END2_10", + "CFG_CENTER_LOGIC_OUTS_B2_11", + "CFG_CENTER_NE4BEG3_3", + "CFG_CENTER_IMUX9_1", + "CFG_CENTER_IMUX17_19", + "CFG_CENTER_WW4A1_18", + "CFG_CENTER_WW4B2_1", + "CFG_CENTER_WR1END3_10", + "CFG_CENTER_LOGIC_OUTS_B23_10", + "CFG_CENTER_ICAP0_O11", + "CFG_CENTER_FRAME_ECC_ECCERROR", + "CFG_CENTER_WW2A0_1", + "CFG_CENTER_NW4A1_7", + "CFG_CENTER_LOGIC_OUTS_B10_2", + "CFG_CENTER_LOGIC_OUTS_B22_1", + "CFG_CENTER_WW2A1_1", + "CFG_CENTER_SE4BEG3_4", + "CFG_CENTER_SE2A1_10", + "CFG_CENTER_IMUX7_10", + "CFG_CENTER_WR1END2_15", + "CFG_CENTER_LOGIC_OUTS_B14_14", + "CFG_CENTER_WW2END3_4", + "CFG_CENTER_BYP3_14", + "CFG_CENTER_SW4A0_0", + "CFG_CENTER_LH3_11", + "CFG_CENTER_WW4C1_18", + "CFG_CENTER_NW4A0_15", + "CFG_CENTER_NW4END3_15", + "CFG_CENTER_IMUX16_14", + "CFG_CENTER_WW4C2_17", + "CFG_CENTER_IMUX8_9", + "CFG_CENTER_LH5_5", + "CFG_CENTER_SW4A0_19", + "CFG_CENTER_ICAP1_O5", + "CFG_CENTER_SW2A1_17", + "CFG_CENTER_FAN7_9", + "CFG_CENTER_IMUX38_3", + "CFG_CENTER_EE2BEG0_15", + "CFG_CENTER_IMUX26_18", + "CFG_CENTER_NW4END0_5", + "CFG_CENTER_IMUX29_19", + "CFG_CENTER_EE4C0_0", + "CFG_CENTER_NW4A1_11", + "CFG_CENTER_IMUX36_3", + "CFG_CENTER_NE2A0_19", + "CFG_CENTER_CLK1_12", + "CFG_CENTER_EE4BEG0_9", + "CFG_CENTER_IMUX16_13", + "CFG_CENTER_ER1BEG3_18", + "CFG_CENTER_IMUX4_17", + "CFG_CENTER_IMUX36_13", + "CFG_CENTER_LH10_13", + "CFG_CENTER_LOGIC_OUTS_B2_6", + "CFG_CENTER_ICAP0_O6", + "CFG_CENTER_WL1END1_5", + "CFG_CENTER_EE4C1_5", + "CFG_CENTER_WW4C3_12", + "CFG_CENTER_WR1END2_10", + "CFG_CENTER_BYP7_3", + "CFG_CENTER_EE4C2_6", + "CFG_CENTER_BLOCK_OUTS_B3_18", + "CFG_CENTER_LOGIC_OUTS_B18_4", + "CFG_CENTER_IMUX36_6", + "CFG_CENTER_ICAP1_I24", + "CFG_CENTER_IMUX5_1", + "CFG_CENTER_ICAP0_I2", + "CFG_CENTER_FAN7_4", + "CFG_CENTER_IMUX34_4", + "CFG_CENTER_WL1END3_19", + "CFG_CENTER_IMUX3_15", + "CFG_CENTER_IMUX18_15", + "CFG_CENTER_EE2BEG2_13", + "CFG_CENTER_ICAP0_I14", + "CFG_CENTER_WW4C3_8", + "CFG_CENTER_ER1BEG3_16", + "CFG_CENTER_EE4C0_3", + "CFG_CENTER_IMUX30_5", + "CFG_CENTER_EE2A0_9", + "CFG_CENTER_LH6_17", + "CFG_CENTER_LH8_18", + "CFG_CENTER_EE4A3_5", + "CFG_CENTER_IMUX28_1", + "CFG_CENTER_IMUX18_4", + "CFG_CENTER_LOGIC_OUTS_B3_1", + "CFG_CENTER_FAN1_9", + "CFG_CENTER_NW2A0_0", + "CFG_CENTER_IMUX20_4", + "CFG_CENTER_BLOCK_OUTS_B2_18", + "CFG_CENTER_FRAME_ECC_FAR2", + "CFG_CENTER_USR_ACCESS_DATAVALID", + "CFG_CENTER_WR1END0_16", + "CFG_CENTER_FAN1_6", + "CFG_CENTER_FAN0_13", + "CFG_CENTER_IMUX29_18", + "CFG_CENTER_SE4C3_16", + "CFG_CENTER_IMUX21_9", + "CFG_CENTER_IMUX2_3", + "CFG_CENTER_SE2A2_5", + "CFG_CENTER_EE2A1_4", + "CFG_CENTER_EE4C2_4", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA27", + "CFG_CENTER_IMUX43_10", + "CFG_CENTER_FAN0_1", + "CFG_CENTER_LOGIC_OUTS_B22_12", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA28", + "CFG_CENTER_IMUX43_19", + "CFG_CENTER_EE4C3_8", + "CFG_CENTER_LOGIC_OUTS_B21_7", + "CFG_CENTER_EE2BEG3_6", + "CFG_CENTER_LH12_2", + "CFG_CENTER_IMUX15_13", + "CFG_CENTER_ICAP1_RDWRB", + "CFG_CENTER_SE2A3_12", + "CFG_CENTER_IMUX44_1", + "CFG_CENTER_WL1END1_14", + "CFG_CENTER_ICAP0_O0", + "CFG_CENTER_IMUX35_0", + "CFG_CENTER_LH11_1", + "CFG_CENTER_NW4END0_14", + "CFG_CENTER_EE2A3_12", + "CFG_CENTER_EE2BEG0_18", + "CFG_CENTER_SE2A2_16", + "CFG_CENTER_IMUX28_8", + "CFG_CENTER_IMUX31_18", + "CFG_CENTER_EE4BEG2_19", + "CFG_CENTER_NW4END1_17", + "CFG_CENTER_IMUX0_13", + "CFG_CENTER_SW4A0_13", + "CFG_CENTER_ICAP0_I28", + "CFG_CENTER_FAN2_15", + "CFG_CENTER_NW4A3_3", + "CFG_CENTER_NE4C0_19", + "CFG_CENTER_LOGIC_OUTS_B17_19", + "CFG_CENTER_CLK0_16", + "CFG_CENTER_LOGIC_OUTS_B0_6", + "CFG_CENTER_NE4BEG3_15", + "CFG_CENTER_PMVIOB_O", + "CFG_CENTER_IMUX10_4", + "CFG_CENTER_FAN3_12", + "CFG_CENTER_EL1BEG0_19", + "CFG_CENTER_IMUX3_16", + "CFG_CENTER_USR_ACCESS_DATA29", + "CFG_CENTER_IMUX44_4", + "CFG_CENTER_SE2A0_1", + "CFG_CENTER_EE4BEG1_13", + "CFG_CENTER_SE4C2_2", + "CFG_CENTER_IMUX45_10", + "CFG_CENTER_EE2BEG2_6", + "CFG_CENTER_IMUX28_2", + "CFG_CENTER_LOGIC_OUTS_B14_13", + "CFG_CENTER_EE2BEG1_15", + "CFG_CENTER_IMUX46_14", + "CFG_CENTER_SE4BEG1_12", + "CFG_CENTER_IMUX43_15", + "CFG_CENTER_WW2A0_6", + "CFG_CENTER_IMUX34_9", + "CFG_CENTER_WR1END2_0", + "CFG_CENTER_WW4B3_9", + "CFG_CENTER_IMUX35_2", + "CFG_CENTER_SE4BEG0_16", + "CFG_CENTER_FAN1_1", + "CFG_CENTER_LH4_9", + "CFG_CENTER_IMUX9_2", + "CFG_CENTER_EE4B2_9", + "CFG_CENTER_IMUX26_1", + "CFG_CENTER_FAN5_15", + "CFG_CENTER_IMUX21_2", + "CFG_CENTER_USR_ACCESS_DATA9", + "CFG_CENTER_LOGIC_OUTS_B13_1", + "CFG_CENTER_LOGIC_OUTS_B3_9", + "CFG_CENTER_BYP5_15", + "CFG_CENTER_LOGIC_OUTS_B17_3", + "CFG_CENTER_LOGIC_OUTS_B20_14", + "CFG_CENTER_LOGIC_OUTS_B13_17", + "CFG_CENTER_SE2A3_7", + "CFG_CENTER_SW4A0_12", + "CFG_CENTER_IMUX8_10", + "CFG_CENTER_EE4BEG2_8", + "CFG_CENTER_ICAP1_I12", + "CFG_CENTER_ER1BEG0_13", + "CFG_CENTER_CTRL1_17", + "CFG_CENTER_FAN2_5", + "CFG_CENTER_SW2A3_12", + "CFG_CENTER_IMUX12_1", + "CFG_CENTER_EE2BEG1_2", + "CFG_CENTER_WW4A0_3", + "CFG_CENTER_BYP4_8", + "CFG_CENTER_CLK0_12", + "CFG_CENTER_BYP5_3", + "CFG_CENTER_CTRL0_15", + "CFG_CENTER_LOGIC_OUTS_B0_19", + "CFG_CENTER_WR1END3_19", + "CFG_CENTER_SW2A3_0", + "CFG_CENTER_LH7_18", + "CFG_CENTER_ICAP1_O27", + "CFG_CENTER_CLK1_4", + "CFG_CENTER_LOGIC_OUTS_B0_4", + "CFG_CENTER_BSCAN3_UPDATE", + "CFG_CENTER_SE4BEG2_1", + "CFG_CENTER_EE4C1_2", + "CFG_CENTER_LOGIC_OUTS_B21_18", + "CFG_CENTER_NE4BEG1_6", + "CFG_CENTER_WW4A3_11", + "CFG_CENTER_WW4B3_14", + "CFG_CENTER_WW4END3_15", + "CFG_CENTER_ICAP1_O2", + "CFG_CENTER_FRAME_ECC_FAR23", + "CFG_CENTER_LOGIC_OUTS_B21_19", + "CFG_CENTER_WW4END1_13", + "CFG_CENTER_WW2END3_9", + "CFG_CENTER_SW2A0_10", + "CFG_CENTER_NW4A1_18", + "CFG_CENTER_LOGIC_OUTS_B11_10", + "CFG_CENTER_BYP5_14", + "CFG_CENTER_NW2A1_9", + "CFG_CENTER_WW4A0_4", + "CFG_CENTER_IMUX34_19", + "CFG_CENTER_IMUX30_12", + "CFG_CENTER_IMUX5_12", + "CFG_CENTER_LH7_4", + "CFG_CENTER_NE2A1_11", + "CFG_CENTER_NE4BEG1_13", + "CFG_CENTER_SE2A3_9", + "CFG_CENTER_BYP4_14", + "CFG_CENTER_LOGIC_OUTS_B4_7", + "CFG_CENTER_IMUX33_0", + "CFG_CENTER_STARTUP_USRDONEO", + "CFG_CENTER_IMUX36_10", + "CFG_CENTER_IMUX33_16", + "CFG_CENTER_IMUX35_9", + "CFG_CENTER_WW2A3_12", + "CFG_CENTER_WW2A3_3", + "CFG_CENTER_LH10_4", + "CFG_CENTER_ICAP0_O7", + "CFG_CENTER_SW2A3_7", + "CFG_CENTER_BSCAN1_DRCK", + "CFG_CENTER_EL1BEG3_13", + "CFG_CENTER_ICAP1_O24", + "CFG_CENTER_SW4A3_9", + "CFG_CENTER_IMUX16_8", + "CFG_CENTER_WW2A1_2", + "CFG_CENTER_IMUX45_11", + "CFG_CENTER_SW4END0_19", + "CFG_CENTER_LH5_18", + "CFG_CENTER_ER1BEG2_7", + "CFG_CENTER_WW4A2_0", + "CFG_CENTER_SW4END3_2", + "CFG_CENTER_LH4_3", + "CFG_CENTER_NE4C0_1", + "CFG_CENTER_SW2A3_18", + "CFG_CENTER_EL1BEG1_13", + "CFG_CENTER_SE2A3_15", + "CFG_CENTER_IMUX27_10", + "CFG_CENTER_EE4B2_3", + "CFG_CENTER_IMUX47_0", + "CFG_CENTER_WW4B1_4", + "CFG_CENTER_SW4A1_10", + "CFG_CENTER_BYP7_1", + "CFG_CENTER_LH11_10", + "CFG_CENTER_IMUX41_14", + "CFG_CENTER_ICAP1_I21", + "CFG_CENTER_IMUX27_9", + "CFG_CENTER_IMUX47_18", + "CFG_CENTER_LOGIC_OUTS_B4_5", + "CFG_CENTER_BLOCK_OUTS_B3_14", + "CFG_CENTER_IMUX45_12", + "CFG_CENTER_EE4B3_5", + "CFG_CENTER_EE2A1_10", + "CFG_CENTER_LH7_2", + "CFG_CENTER_SW4END1_9", + "CFG_CENTER_EE4B1_0", + "CFG_CENTER_BYP7_14", + "CFG_CENTER_LH10_9", + "CFG_CENTER_IMUX21_13", + "CFG_CENTER_WW4C2_10", + "CFG_CENTER_WW4A2_13", + "CFG_CENTER_EL1BEG2_11", + "CFG_CENTER_LOGIC_OUTS_B19_0", + "CFG_CENTER_EL1BEG0_16", + "CFG_CENTER_LOGIC_OUTS_B22_9", + "CFG_CENTER_WR1END1_3", + "CFG_CENTER_FAN2_1", + "CFG_CENTER_IMUX18_1", + "CFG_CENTER_IMUX38_0", + "CFG_CENTER_SW4A3_0", + "CFG_CENTER_SE4C1_17", + "CFG_CENTER_EE2A3_11", + "CFG_CENTER_WL1END3_14", + "CFG_CENTER_EE4BEG0_18", + "CFG_CENTER_IMUX22_12", + "CFG_CENTER_WW4B3_0", + "CFG_CENTER_WL1END1_17", + "CFG_CENTER_LOGIC_OUTS_B19_4", + "CFG_CENTER_FRAME_ECC_SYNBIT4", + "CFG_CENTER_WL1END2_18", + "CFG_CENTER_FRAME_ECC_FAR22", + "CFG_CENTER_IMUX4_19", + "CFG_CENTER_EE4B3_4", + "CFG_CENTER_IMUX24_18", + "CFG_CENTER_NE4C1_16", + "CFG_CENTER_NW4END3_18", + "CFG_CENTER_IMUX24_2", + "CFG_CENTER_SW4END2_18", + "CFG_CENTER_EE4B0_19", + "CFG_CENTER_SE4BEG3_15", + "CFG_CENTER_LOGIC_OUTS_B12_7", + "CFG_CENTER_LOGIC_OUTS_B17_8", + "CFG_CENTER_IMUX2_2", + "CFG_CENTER_ICAP1_CSIB", + "CFG_CENTER_SW4A0_1", + "CFG_CENTER_EE2BEG2_8", + "CFG_CENTER_ICAP0_O14", + "CFG_CENTER_CLK1_8", + "CFG_CENTER_EE4BEG2_4", + "CFG_CENTER_LOGIC_OUTS_B17_9", + "CFG_CENTER_LH9_5", + "CFG_CENTER_WW4B2_8", + "CFG_CENTER_BYP4_11", + "CFG_CENTER_IMUX39_0", + "CFG_CENTER_WW2END1_7", + "CFG_CENTER_BYP0_13", + "CFG_CENTER_IMUX41_8", + "CFG_CENTER_LOGIC_OUTS_B8_6", + "CFG_CENTER_EL1BEG0_8", + "CFG_CENTER_IMUX22_7", + "CFG_CENTER_IMUX37_18", + "CFG_CENTER_EL1BEG1_5", + "CFG_CENTER_IMUX32_18", + "CFG_CENTER_LOGIC_OUTS_B8_7", + "CFG_CENTER_WW4B1_16", + "CFG_CENTER_IMUX45_4", + "CFG_CENTER_IMUX20_16", + "CFG_CENTER_LOGIC_OUTS_B8_13", + "CFG_CENTER_IMUX21_14", + "CFG_CENTER_IMUX39_6", + "CFG_CENTER_LOGIC_OUTS_B1_12", + "CFG_CENTER_SW4A3_1", + "CFG_CENTER_IMUX41_13", + "CFG_CENTER_NE4C3_5", + "CFG_CENTER_NE4BEG1_10", + "CFG_CENTER_WW2END3_16", + "CFG_CENTER_IMUX31_14", + "CFG_CENTER_SE2A2_4", + "CFG_CENTER_LOGIC_OUTS_B22_2", + "CFG_CENTER_IMUX3_11", + "CFG_CENTER_NE4BEG2_5", + "CFG_CENTER_WW2A2_2", + "CFG_CENTER_LH1_9", + "CFG_CENTER_LOGIC_OUTS_B2_15", + "CFG_CENTER_WW4C3_7", + "CFG_CENTER_CK_BUFHCLK9", + "CFG_CENTER_WW4END2_17", + "CFG_CENTER_IMUX45_14", + "CFG_CENTER_BSCAN3_TMS", + "CFG_CENTER_IMUX28_13", + "CFG_CENTER_EE2BEG3_9", + "CFG_CENTER_IMUX14_0", + "CFG_CENTER_IMUX24_12", + "CFG_CENTER_NE4C2_17", + "CFG_CENTER_EE4BEG2_3", + "CFG_CENTER_EE4A0_2", + "CFG_CENTER_EE4B1_6", + "CFG_CENTER_NW4END0_8", + "CFG_CENTER_SW4END3_16", + "CFG_CENTER_EE2BEG3_10", + "CFG_CENTER_IMUX17_15", + "CFG_CENTER_NE4BEG0_12", + "CFG_CENTER_FRAME_ECC_FAR5", + "CFG_CENTER_IMUX41_19", + "CFG_CENTER_BLOCK_OUTS_B1_4", + "CFG_CENTER_CTRL1_10", + "CFG_CENTER_LH7_1", + "CFG_CENTER_IMUX38_8", + "CFG_CENTER_IMUX23_11", + "CFG_CENTER_WL1END1_10", + "CFG_CENTER_LOGIC_OUTS_B7_12", + "CFG_CENTER_SW2A1_15", + "CFG_CENTER_SW4A0_7", + "CFG_CENTER_EE4C3_1", + "CFG_CENTER_IMUX14_14", + "CFG_CENTER_NW4END0_6", + "CFG_CENTER_NW4END2_15", + "CFG_CENTER_IMUX30_3", + "CFG_CENTER_NE4C0_13", + "CFG_CENTER_EE2A3_15", + "CFG_CENTER_WW4C1_4", + "CFG_CENTER_WW4C2_8", + "CFG_CENTER_IMUX26_5", + "CFG_CENTER_NW2A3_4", + "CFG_CENTER_IMUX21_10", + "CFG_CENTER_WW4C0_10", + "CFG_CENTER_EE4A2_12", + "CFG_CENTER_IMUX42_16", + "CFG_CENTER_LOGIC_OUTS_B13_7", + "CFG_CENTER_NW2A1_6", + "CFG_CENTER_IMUX36_7", + "CFG_CENTER_LOGIC_OUTS_B0_0", + "CFG_CENTER_IMUX38_5", + "CFG_CENTER_EE2A0_7", + "CFG_CENTER_NW4A2_18", + "CFG_CENTER_LH3_15", + "CFG_CENTER_NW4A3_12", + "CFG_CENTER_WW2A1_18", + "CFG_CENTER_USR_ACCESS_DATA18", + "CFG_CENTER_IMUX25_11", + "CFG_CENTER_IMUX15_1", + "CFG_CENTER_FRAME_ECC_SYNWORD3", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA14", + "CFG_CENTER_BYP0_10", + "CFG_CENTER_SW4END3_17", + "CFG_CENTER_EE4BEG0_15", + "CFG_CENTER_SE2A1_8", + "CFG_CENTER_USR_ACCESS_DATA27", + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA3", + "CFG_CENTER_LH12_0", + "CFG_CENTER_SE4C3_12", + "CFG_CENTER_NE2A3_3", + "CFG_CENTER_LOGIC_OUTS_B8_0", + "CFG_CENTER_BYP5_18", + "CFG_CENTER_NE4C3_7", + "CFG_CENTER_WW4C2_18", + "CFG_CENTER_WW4END0_16", + "CFG_CENTER_IMUX8_5", + "CFG_CENTER_IMUX26_0", + "CFG_CENTER_NW2A2_5", + "CFG_CENTER_NW4A1_4", + "CFG_CENTER_WW4END1_16", + "CFG_CENTER_IMUX29_7", + "CFG_CENTER_IMUX40_18", + "CFG_CENTER_FRAME_ECC_SYNWORD1", + "CFG_CENTER_BLOCK_OUTS_B1_0", + "CFG_CENTER_PMVIOB_ODIV2", + "CFG_CENTER_LOGIC_OUTS_B1_1", + "CFG_CENTER_IMUX27_1", + "CFG_CENTER_EL1BEG3_11", + "CFG_CENTER_IMUX37_0", + "CFG_CENTER_IMUX14_12", + "CFG_CENTER_LH2_14", + "CFG_CENTER_LOGIC_OUTS_B13_5", + "CFG_CENTER_IMUX8_15", + "CFG_CENTER_IMUX17_13", + "CFG_CENTER_EE4C2_9", + "CFG_CENTER_IMUX15_8", + "CFG_CENTER_IMUX0_14", + "CFG_CENTER_ICAP1_I23", + "CFG_CENTER_SE4C1_13", + "CFG_CENTER_NE4C0_0", + "CFG_CENTER_IMUX24_5", + "CFG_CENTER_BLOCK_OUTS_B0_0", + "CFG_CENTER_CFG_IO_ACCESS_INITBI", + "CFG_CENTER_IMUX20_12", + "CFG_CENTER_SE4C2_16", + "CFG_CENTER_ER1BEG2_19", + "CFG_CENTER_IMUX14_3", + "CFG_CENTER_WR1END3_17", + "CFG_CENTER_SW4A0_15", + "CFG_CENTER_NW4END3_17", + "CFG_CENTER_EE4BEG3_4", + "CFG_CENTER_NW4A1_12", + "CFG_CENTER_WL1END3_3", + "CFG_CENTER_WW4END0_18", + "CFG_CENTER_IMUX11_4", + "CFG_CENTER_LOGIC_OUTS_B6_5", + "CFG_CENTER_EE4A3_7", + "CFG_CENTER_FAN4_1", + "CFG_CENTER_IMUX1_16", + "CFG_CENTER_IMUX22_16", + "CFG_CENTER_WW4END1_8", + "CFG_CENTER_BSCAN4_RESET", + "CFG_CENTER_IMUX33_1", + "CFG_CENTER_USR_ACCESS_DATA24", + "CFG_CENTER_CTRL0_6", + "CFG_CENTER_IMUX43_0", + "CFG_CENTER_IMUX33_6", + "CFG_CENTER_FAN4_12", + "CFG_CENTER_WW4B2_2", + "CFG_CENTER_LOGIC_OUTS_B11_2", + "CFG_CENTER_IMUX23_16", + "CFG_CENTER_SE4BEG3_17", + "CFG_CENTER_LOGIC_OUTS_B6_8", + "CFG_CENTER_IMUX40_15", + "CFG_CENTER_EE4BEG1_11", + "CFG_CENTER_NW2A0_12", + "CFG_CENTER_CLK1_14", + "CFG_CENTER_CLK1_13", + "CFG_CENTER_WW2END1_12", + "CFG_CENTER_IMUX30_2", + "CFG_CENTER_EE4C0_12", + "CFG_CENTER_EE4C0_15", + "CFG_CENTER_SE2A0_9", + "CFG_CENTER_LOGIC_OUTS_B16_16", + "CFG_CENTER_WW4B1_2", + "CFG_CENTER_IMUX25_4", + "CFG_CENTER_SW4END3_18", + "CFG_CENTER_IMUX38_17", + "CFG_CENTER_SW4END1_16", + "CFG_CENTER_IMUX47_12", + "CFG_CENTER_WW4B3_12", + "CFG_CENTER_IMUX5_19", + "CFG_CENTER_NW4END3_13", + "CFG_CENTER_LOGIC_OUTS_B13_15", + "CFG_CENTER_SW4END3_12", + "CFG_CENTER_IMUX26_14", + "CFG_CENTER_IMUX19_2", + "CFG_CENTER_WW4END2_18", + "CFG_CENTER_IMUX41_5", + "CFG_CENTER_MID_USR_ACCESS_DATA12", + "CFG_CENTER_BLOCK_OUTS_B2_11", + "CFG_CENTER_LOGIC_OUTS_B22_8", + "CFG_CENTER_IMUX12_6", + "CFG_CENTER_IMUX21_11", + "CFG_CENTER_NW2A3_18", + "CFG_CENTER_IMUX16_11", + "CFG_CENTER_EE4BEG2_6", + "CFG_CENTER_NW2A1_16", + "CFG_CENTER_BYP2_8", + "CFG_CENTER_SE2A2_17", + "CFG_CENTER_WW4A0_7", + "CFG_CENTER_EE2A0_15", + "CFG_CENTER_IMUX29_13", + "CFG_CENTER_NW4A2_4", + "CFG_CENTER_IMUX19_16", + "CFG_CENTER_EE2BEG1_9", + "CFG_CENTER_IMUX44_19", + "CFG_CENTER_LH4_5", + "CFG_CENTER_CLK1_19", + "CFG_CENTER_WW4END2_0", + "CFG_CENTER_IMUX29_14", + "CFG_CENTER_WW4C0_12", + "CFG_CENTER_BLOCK_OUTS_B1_5", + "CFG_CENTER_EL1BEG1_0", + "CFG_CENTER_NW2A1_0", + "CFG_CENTER_CLK0_0", + "CFG_CENTER_NW4END3_9", + "CFG_CENTER_WW4C3_2", + "CFG_CENTER_WR1END1_8", + "CFG_CENTER_CLK1_11", + "CFG_CENTER_WR1END2_3", + "CFG_CENTER_IMUX25_3", + "CFG_CENTER_SW4A3_14", + "CFG_CENTER_WW4END2_3", + "CFG_CENTER_EE2A2_19", + "CFG_CENTER_EE2BEG0_13", + "CFG_CENTER_IMUX30_4", + "CFG_CENTER_WW2END3_2", + "CFG_CENTER_ICAP0_O5", + "CFG_CENTER_ICAP0_O22", + "CFG_CENTER_ICAP1_I28", + "CFG_CENTER_SE4BEG1_18", + "CFG_CENTER_SE2A1_12", + "CFG_CENTER_SW4A2_19", + "CFG_CENTER_NW2A2_12", + "CFG_CENTER_ER1BEG3_19", + "CFG_CENTER_IMUX32_5", + "CFG_CENTER_WW4C3_13", + "CFG_CENTER_EE4C0_17", + "CFG_CENTER_BSCAN2_RUNTEST", + "CFG_CENTER_NW4A2_11", + "CFG_CENTER_EE4A3_1", + "CFG_CENTER_LOGIC_OUTS_B11_16", + "CFG_CENTER_NW4A3_13", + "CFG_CENTER_ER1BEG2_10", + "CFG_CENTER_BYP6_2", + "CFG_CENTER_LH5_11", + "CFG_CENTER_BLOCK_OUTS_B2_0", + "CFG_CENTER_EE4B2_19", + "CFG_CENTER_IMUX3_3", + "CFG_CENTER_SE4C3_0", + "CFG_CENTER_WR1END0_17", + "CFG_CENTER_WW2END0_11", + "CFG_CENTER_SW2A3_14", + "CFG_CENTER_WW4END2_14", + "CFG_CENTER_FAN4_11", + "CFG_CENTER_BYP2_12", + "CFG_CENTER_BYP0_17", + "CFG_CENTER_IMUX15_10", + "CFG_CENTER_LOGIC_OUTS_B11_14", + "CFG_CENTER_NW2A1_2", + "CFG_CENTER_FAN3_2", + "CFG_CENTER_EE4B3_19", + "CFG_CENTER_USR_ACCESS_DATA25", + "CFG_CENTER_NW2A2_6", + "CFG_CENTER_IMUX15_5", + "CFG_CENTER_IMUX34_8", + "CFG_CENTER_SE4C3_17", + "CFG_CENTER_NE4BEG0_3", + "CFG_CENTER_WW4A0_12", + "CFG_CENTER_IMUX30_14", + "CFG_CENTER_IMUX17_1", + "CFG_CENTER_FAN5_9", + "CFG_CENTER_SE2A3_18", + "CFG_CENTER_CLK0_19", + "CFG_CENTER_IMUX44_0", + "CFG_CENTER_FAN3_8", + "CFG_CENTER_ER1BEG2_17", + "CFG_CENTER_LH9_16", + "CFG_CENTER_IMUX12_13", + "CFG_CENTER_EE4B1_9", + "CFG_CENTER_LOGIC_OUTS_B12_17", + "CFG_CENTER_EE4C2_1", + "CFG_CENTER_BLOCK_OUTS_B0_3", + "CFG_CENTER_ER1BEG0_4", + "CFG_CENTER_NE4C1_8", + "CFG_CENTER_SW2A0_16", + "CFG_CENTER_WW4B1_17", + "CFG_CENTER_LH8_19", + "CFG_CENTER_LH5_13", + "CFG_CENTER_SE2A1_3", + "CFG_CENTER_IMUX18_14", + "CFG_CENTER_LOGIC_OUTS_B4_19", + "CFG_CENTER_NE2A2_16", + "CFG_CENTER_WW2A1_3", + "CFG_CENTER_BYP7_12", + "CFG_CENTER_NE2A2_15", + "CFG_CENTER_FAN6_1", + "CFG_CENTER_BYP0_16", + "CFG_CENTER_EE2BEG0_3", + "CFG_CENTER_IMUX42_17", + "CFG_CENTER_NE4BEG1_18", + "CFG_CENTER_EL1BEG1_3", + "CFG_CENTER_LH8_17", + "CFG_CENTER_IMUX36_1", + "CFG_CENTER_LOGIC_OUTS_B5_3", + "CFG_CENTER_IMUX35_7", + "CFG_CENTER_SW2A3_5", + "CFG_CENTER_IMUX24_16", + "CFG_CENTER_EE4B0_10", + "CFG_CENTER_WW4C0_13", + "CFG_CENTER_IMUX33_12", + "CFG_CENTER_EE2BEG2_0", + "CFG_CENTER_NE4C3_1", + "CFG_CENTER_BLOCK_OUTS_B0_18", + "CFG_CENTER_EE4B0_8", + "CFG_CENTER_IMUX24_19", + "CFG_CENTER_WW4END0_1", + "CFG_CENTER_EL1BEG0_7", + "CFG_CENTER_IMUX14_17", + "CFG_CENTER_BLOCK_OUTS_B0_15", + "CFG_CENTER_LOGIC_OUTS_B9_4", + "CFG_CENTER_IMUX27_12", + "CFG_CENTER_BYP1_15", + "CFG_CENTER_LOGIC_OUTS_B21_5", + "CFG_CENTER_MID_USR_ACCESS_DATA11", + "CFG_CENTER_WW2A0_15", + "CFG_CENTER_LH12_7", + "CFG_CENTER_EE4B1_8", + "CFG_CENTER_CLK1_6", + "CFG_CENTER_LH10_17", + "CFG_CENTER_ICAP1_I2", + "CFG_CENTER_IMUX28_17", + "CFG_CENTER_LOGIC_OUTS_B0_9", + "CFG_CENTER_IMUX28_7", + "CFG_CENTER_EE4A3_11", + "CFG_CENTER_NW4END0_13", + "CFG_CENTER_IMUX38_18", + "CFG_CENTER_LOGIC_OUTS_B7_1", + "CFG_CENTER_IMUX31_16", + "CFG_CENTER_ICAP0_I26", + "CFG_CENTER_SW2A2_2", + "CFG_CENTER_LOGIC_OUTS_B3_6", + "CFG_CENTER_WW4C0_3", + "CFG_CENTER_LH1_10", + "CFG_CENTER_IMUX43_11", + "CFG_CENTER_IMUX32_14", + "CFG_CENTER_BYP1_1", + "CFG_CENTER_WL1END0_9", + "CFG_CENTER_IMUX5_7", + "CFG_CENTER_EE2A0_8", + "CFG_CENTER_WW4END1_5", + "CFG_CENTER_IMUX27_18", + "CFG_CENTER_WW4B1_5", + "CFG_CENTER_BYP6_13", + "CFG_CENTER_LOGIC_OUTS_B2_2", + "CFG_CENTER_LH7_19", + "CFG_CENTER_FRAME_ECC_FAR17", + "CFG_CENTER_NW4END3_4", + "CFG_CENTER_WW4C0_17", + "CFG_CENTER_FRAME_ECC_FAR11", + "CFG_CENTER_FAN4_0", + "CFG_CENTER_ICAP1_I29", + "CFG_CENTER_EE2A2_8", + "CFG_CENTER_LOGIC_OUTS_B23_11", + "CFG_CENTER_SW4A2_13", + "CFG_CENTER_BYP4_4", + "CFG_CENTER_IMUX31_19", + "CFG_CENTER_BYP1_18", + "CFG_CENTER_EE4C0_16", + "CFG_CENTER_IMUX47_14", + "CFG_CENTER_IMUX2_11", + "CFG_CENTER_BLOCK_OUTS_B1_2", + "CFG_CENTER_NW4A1_2", + "CFG_CENTER_SW4A2_1", + "CFG_CENTER_IMUX19_14", + "CFG_CENTER_WW4C1_5", + "CFG_CENTER_NW4END2_14", + "CFG_CENTER_WW4A2_4", + "CFG_CENTER_EE2BEG1_4", + "CFG_CENTER_CLK1_10", + "CFG_CENTER_EL1BEG1_14", + "CFG_CENTER_IMUX12_14", + "CFG_CENTER_SW4A3_8", + "CFG_CENTER_IMUX47_17", + "CFG_CENTER_IMUX29_2", + "CFG_CENTER_WR1END3_8", + "CFG_CENTER_WW2END0_1", + "CFG_CENTER_NE4C3_12", + "CFG_CENTER_IMUX3_5", + "CFG_CENTER_IMUX34_2", + "CFG_CENTER_IMUX10_8", + "CFG_CENTER_IMUX14_5", + "CFG_CENTER_EE2A1_1", + "CFG_CENTER_FAN6_17", + "CFG_CENTER_EE4BEG2_7", + "CFG_CENTER_CLK1_1", + "CFG_CENTER_BSCAN1_SEL", + "CFG_CENTER_IMUX18_2", + "CFG_CENTER_IMUX36_4", + "CFG_CENTER_LOGIC_OUTS_B21_17", + "CFG_CENTER_SW2A3_11", + "CFG_CENTER_IMUX18_3", + "CFG_CENTER_IMUX28_6", + "CFG_CENTER_WW2A2_6", + "CFG_CENTER_IMUX39_2", + "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA14", + "CFG_CENTER_NW2A2_11", + "CFG_CENTER_IMUX15_7", + "CFG_CENTER_IMUX44_9", + "CFG_CENTER_NE4C2_11", + "CFG_CENTER_LOGIC_OUTS_B8_2", + "CFG_CENTER_BYP2_16", + "CFG_CENTER_BYP5_7", + "CFG_CENTER_ICAP0_O20", + "CFG_CENTER_LH6_2", + "CFG_CENTER_NE4C0_5", + "CFG_CENTER_CK_BUFHCLK3", + "CFG_CENTER_FRAME_ECC_FAR18", + "CFG_CENTER_NW4A3_4", + "CFG_CENTER_SE4C2_3", + "CFG_CENTER_NW4END0_12", + "CFG_CENTER_SE4BEG0_7", + "CFG_CENTER_BYP5_5", + "CFG_CENTER_WW4B3_17", + "CFG_CENTER_ICAP1_I22", + "CFG_CENTER_EE2A2_6", + "CFG_CENTER_IMUX32_17", + "CFG_CENTER_WW4B3_2", + "CFG_CENTER_SE4BEG2_6", + "CFG_CENTER_EE2A0_10", + "CFG_CENTER_BYP7_17", + "CFG_CENTER_IMUX26_2", + "CFG_CENTER_SE4C2_1", + "CFG_CENTER_NW2A3_0", + "CFG_CENTER_WW4END3_16", + "CFG_CENTER_IMUX15_14" ], + "tile_type": "CFG_CENTER_MID", "sites": [ { - "prefix": "USR_ACCESS", - "y_coord": 0, - "type": "USR_ACCESS", "site_pins": { - "DATA3": "CFG_CENTER_USR_ACCESS_DATA3", - "DATA23": "CFG_CENTER_USR_ACCESS_DATA23", - "DATA4": "CFG_CENTER_USR_ACCESS_DATA4", - "DATA17": "CFG_CENTER_USR_ACCESS_DATA17", - "DATA16": "CFG_CENTER_USR_ACCESS_DATA16", - "DATA11": "CFG_CENTER_USR_ACCESS_DATA11", - "DATA8": "CFG_CENTER_USR_ACCESS_DATA8", - "DATA5": "CFG_CENTER_USR_ACCESS_DATA5", - "DATA2": "CFG_CENTER_USR_ACCESS_DATA2", - "DATA18": "CFG_CENTER_USR_ACCESS_DATA18", - "CFGCLK": "CFG_CENTER_USR_ACCESS_CFGCLK", - "DATA31": "CFG_CENTER_USR_ACCESS_DATA31", - "DATA19": "CFG_CENTER_USR_ACCESS_DATA19", - "DATA1": "CFG_CENTER_USR_ACCESS_DATA1", - "DATA10": "CFG_CENTER_USR_ACCESS_DATA10", - "DATA25": "CFG_CENTER_USR_ACCESS_DATA25", - "DATA7": "CFG_CENTER_USR_ACCESS_DATA7", - "DATA22": "CFG_CENTER_USR_ACCESS_DATA22", - "DATAVALID": "CFG_CENTER_USR_ACCESS_DATAVALID", - "DATA29": "CFG_CENTER_USR_ACCESS_DATA29", - "DATA27": "CFG_CENTER_USR_ACCESS_DATA27", - "DATA12": "CFG_CENTER_USR_ACCESS_DATA12", - "DATA30": "CFG_CENTER_USR_ACCESS_DATA30", - "DATA26": "CFG_CENTER_USR_ACCESS_DATA26", - "DATA6": "CFG_CENTER_USR_ACCESS_DATA6", - "DATA14": "CFG_CENTER_USR_ACCESS_DATA14", - "DATA9": "CFG_CENTER_USR_ACCESS_DATA9", - "DATA21": "CFG_CENTER_USR_ACCESS_DATA21", "DATA15": "CFG_CENTER_USR_ACCESS_DATA15", - "DATA28": "CFG_CENTER_USR_ACCESS_DATA28", - "DATA0": "CFG_CENTER_USR_ACCESS_DATA0", - "DATA20": "CFG_CENTER_USR_ACCESS_DATA20", + "DATA4": "CFG_CENTER_USR_ACCESS_DATA4", + "DATA7": "CFG_CENTER_USR_ACCESS_DATA7", + "DATA5": "CFG_CENTER_USR_ACCESS_DATA5", + "DATA14": "CFG_CENTER_USR_ACCESS_DATA14", + "DATA21": "CFG_CENTER_USR_ACCESS_DATA21", "DATA24": "CFG_CENTER_USR_ACCESS_DATA24", - "DATA13": "CFG_CENTER_USR_ACCESS_DATA13" + "DATA31": "CFG_CENTER_USR_ACCESS_DATA31", + "DATA6": "CFG_CENTER_USR_ACCESS_DATA6", + "DATA1": "CFG_CENTER_USR_ACCESS_DATA1", + "DATA30": "CFG_CENTER_USR_ACCESS_DATA30", + "DATA22": "CFG_CENTER_USR_ACCESS_DATA22", + "DATA11": "CFG_CENTER_USR_ACCESS_DATA11", + "DATA0": "CFG_CENTER_USR_ACCESS_DATA0", + "DATA29": "CFG_CENTER_USR_ACCESS_DATA29", + "DATA13": "CFG_CENTER_USR_ACCESS_DATA13", + "DATA3": "CFG_CENTER_USR_ACCESS_DATA3", + "DATA25": "CFG_CENTER_USR_ACCESS_DATA25", + "DATA28": "CFG_CENTER_USR_ACCESS_DATA28", + "DATA23": "CFG_CENTER_USR_ACCESS_DATA23", + "DATA17": "CFG_CENTER_USR_ACCESS_DATA17", + "DATA12": "CFG_CENTER_USR_ACCESS_DATA12", + "DATA8": "CFG_CENTER_USR_ACCESS_DATA8", + "DATA26": "CFG_CENTER_USR_ACCESS_DATA26", + "DATA10": "CFG_CENTER_USR_ACCESS_DATA10", + "DATA19": "CFG_CENTER_USR_ACCESS_DATA19", + "DATA18": "CFG_CENTER_USR_ACCESS_DATA18", + "DATA2": "CFG_CENTER_USR_ACCESS_DATA2", + "DATA27": "CFG_CENTER_USR_ACCESS_DATA27", + "CFGCLK": "CFG_CENTER_USR_ACCESS_CFGCLK", + "DATA20": "CFG_CENTER_USR_ACCESS_DATA20", + "DATA16": "CFG_CENTER_USR_ACCESS_DATA16", + "DATAVALID": "CFG_CENTER_USR_ACCESS_DATAVALID", + "DATA9": "CFG_CENTER_USR_ACCESS_DATA9" }, + "type": "USR_ACCESS", + "prefix": "USR_ACCESS", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 }, { - "prefix": "BSCAN", - "y_coord": 0, - "type": "BSCAN", "site_pins": { "TDI": "CFG_CENTER_BSCAN1_TDI", - "SHIFT": "CFG_CENTER_BSCAN1_SHIFT", - "SEL": "CFG_CENTER_BSCAN1_SEL", - "DRCK": "CFG_CENTER_BSCAN1_DRCK", + "UPDATE": "CFG_CENTER_BSCAN1_UPDATE", + "TMS": "CFG_CENTER_BSCAN1_TMS", "TDO": "CFG_CENTER_BSCAN1_TDO", "CAPTURE": "CFG_CENTER_BSCAN1_CAPTURE", - "TMS": "CFG_CENTER_BSCAN1_TMS", - "TCK": "CFG_CENTER_BSCAN1_TCK", - "UPDATE": "CFG_CENTER_BSCAN1_UPDATE", + "DRCK": "CFG_CENTER_BSCAN1_DRCK", "RUNTEST": "CFG_CENTER_BSCAN1_RUNTEST", - "RESET": "CFG_CENTER_BSCAN1_RESET" + "RESET": "CFG_CENTER_BSCAN1_RESET", + "TCK": "CFG_CENTER_BSCAN1_TCK", + "SEL": "CFG_CENTER_BSCAN1_SEL", + "SHIFT": "CFG_CENTER_BSCAN1_SHIFT" }, + "type": "BSCAN", + "prefix": "BSCAN", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 }, { - "prefix": "BSCAN", - "y_coord": 1, - "type": "BSCAN", "site_pins": { "TDI": "CFG_CENTER_BSCAN2_TDI", - "SHIFT": "CFG_CENTER_BSCAN2_SHIFT", - "SEL": "CFG_CENTER_BSCAN2_SEL", - "DRCK": "CFG_CENTER_BSCAN2_DRCK", + "UPDATE": "CFG_CENTER_BSCAN2_UPDATE", + "TMS": "CFG_CENTER_BSCAN2_TMS", "TDO": "CFG_CENTER_BSCAN2_TDO", "CAPTURE": "CFG_CENTER_BSCAN2_CAPTURE", - "TMS": "CFG_CENTER_BSCAN2_TMS", - "TCK": "CFG_CENTER_BSCAN2_TCK", - "UPDATE": "CFG_CENTER_BSCAN2_UPDATE", + "DRCK": "CFG_CENTER_BSCAN2_DRCK", "RUNTEST": "CFG_CENTER_BSCAN2_RUNTEST", - "RESET": "CFG_CENTER_BSCAN2_RESET" + "RESET": "CFG_CENTER_BSCAN2_RESET", + "TCK": "CFG_CENTER_BSCAN2_TCK", + "SEL": "CFG_CENTER_BSCAN2_SEL", + "SHIFT": "CFG_CENTER_BSCAN2_SHIFT" }, + "type": "BSCAN", + "prefix": "BSCAN", + "name": "X0Y1", "x_coord": 0, - "name": "X0Y1" + "y_coord": 1 }, { - "prefix": "ICAP", - "y_coord": 0, - "type": "ICAP", "site_pins": { - "I26": "CFG_CENTER_ICAP0_I26", + "I24": "CFG_CENTER_ICAP0_I24", + "O12": "CFG_CENTER_ICAP0_O12", "O23": "CFG_CENTER_ICAP0_O23", - "O13": "CFG_CENTER_ICAP0_O13", "O31": "CFG_CENTER_ICAP0_O31", - "O15": "CFG_CENTER_ICAP0_O15", + "I16": "CFG_CENTER_ICAP0_I16", + "I11": "CFG_CENTER_ICAP0_I11", + "I2": "CFG_CENTER_ICAP0_I2", + "O29": "CFG_CENTER_ICAP0_O29", + "I26": "CFG_CENTER_ICAP0_I26", + "O11": "CFG_CENTER_ICAP0_O11", + "O9": "CFG_CENTER_ICAP0_O9", + "I4": "CFG_CENTER_ICAP0_I4", + "O20": "CFG_CENTER_ICAP0_O20", + "O24": "CFG_CENTER_ICAP0_O24", + "O7": "CFG_CENTER_ICAP0_O7", + "I22": "CFG_CENTER_ICAP0_I22", + "O1": "CFG_CENTER_ICAP0_O1", + "O25": "CFG_CENTER_ICAP0_O25", + "I8": "CFG_CENTER_ICAP0_I8", + "CLK": "CFG_CENTER_ICAP0_CLK", + "O5": "CFG_CENTER_ICAP0_O5", + "O18": "CFG_CENTER_ICAP0_O18", + "I5": "CFG_CENTER_ICAP0_I5", + "I6": "CFG_CENTER_ICAP0_I6", + "I31": "CFG_CENTER_ICAP0_I31", + "I25": "CFG_CENTER_ICAP0_I25", + "O28": "CFG_CENTER_ICAP0_O28", + "I3": "CFG_CENTER_ICAP0_I3", + "I30": "CFG_CENTER_ICAP0_I30", + "I7": "CFG_CENTER_ICAP0_I7", + "O2": "CFG_CENTER_ICAP0_O2", + "I20": "CFG_CENTER_ICAP0_I20", + "I21": "CFG_CENTER_ICAP0_I21", + "I23": "CFG_CENTER_ICAP0_I23", + "I9": "CFG_CENTER_ICAP0_I9", + "O19": "CFG_CENTER_ICAP0_O19", + "I0": "CFG_CENTER_ICAP0_I0", + "O22": "CFG_CENTER_ICAP0_O22", + "I19": "CFG_CENTER_ICAP0_I19", + "I13": "CFG_CENTER_ICAP0_I13", + "I28": "CFG_CENTER_ICAP0_I28", + "O6": "CFG_CENTER_ICAP0_O6", + "I1": "CFG_CENTER_ICAP0_I1", + "I17": "CFG_CENTER_ICAP0_I17", + "I10": "CFG_CENTER_ICAP0_I10", + "O10": "CFG_CENTER_ICAP0_O10", + "O16": "CFG_CENTER_ICAP0_O16", + "O3": "CFG_CENTER_ICAP0_O3", + "O13": "CFG_CENTER_ICAP0_O13", "O8": "CFG_CENTER_ICAP0_O8", "I27": "CFG_CENTER_ICAP0_I27", - "O12": "CFG_CENTER_ICAP0_O12", - "I18": "CFG_CENTER_ICAP0_I18", - "I6": "CFG_CENTER_ICAP0_I6", - "I3": "CFG_CENTER_ICAP0_I3", - "O2": "CFG_CENTER_ICAP0_O2", - "RDWRB": "CFG_CENTER_ICAP0_RDWRB", - "I31": "CFG_CENTER_ICAP0_I31", - "I1": "CFG_CENTER_ICAP0_I1", - "CSIB": "CFG_CENTER_ICAP0_CSIB", - "O24": "CFG_CENTER_ICAP0_O24", - "O20": "CFG_CENTER_ICAP0_O20", - "O22": "CFG_CENTER_ICAP0_O22", - "I29": "CFG_CENTER_ICAP0_I29", - "O27": "CFG_CENTER_ICAP0_O27", - "I9": "CFG_CENTER_ICAP0_I9", - "O4": "CFG_CENTER_ICAP0_O4", - "O26": "CFG_CENTER_ICAP0_O26", - "I10": "CFG_CENTER_ICAP0_I10", - "I21": "CFG_CENTER_ICAP0_I21", - "I20": "CFG_CENTER_ICAP0_I20", - "O9": "CFG_CENTER_ICAP0_O9", - "I22": "CFG_CENTER_ICAP0_I22", - "I28": "CFG_CENTER_ICAP0_I28", - "O11": "CFG_CENTER_ICAP0_O11", "O14": "CFG_CENTER_ICAP0_O14", - "O25": "CFG_CENTER_ICAP0_O25", "I15": "CFG_CENTER_ICAP0_I15", - "O10": "CFG_CENTER_ICAP0_O10", - "O7": "CFG_CENTER_ICAP0_O7", - "I4": "CFG_CENTER_ICAP0_I4", - "O6": "CFG_CENTER_ICAP0_O6", - "I5": "CFG_CENTER_ICAP0_I5", - "I23": "CFG_CENTER_ICAP0_I23", - "I0": "CFG_CENTER_ICAP0_I0", - "O30": "CFG_CENTER_ICAP0_O30", - "O29": "CFG_CENTER_ICAP0_O29", - "O3": "CFG_CENTER_ICAP0_O3", - "CLK": "CFG_CENTER_ICAP0_CLK", - "O0": "CFG_CENTER_ICAP0_O0", + "O26": "CFG_CENTER_ICAP0_O26", + "O27": "CFG_CENTER_ICAP0_O27", + "CSIB": "CFG_CENTER_ICAP0_CSIB", + "I29": "CFG_CENTER_ICAP0_I29", + "RDWRB": "CFG_CENTER_ICAP0_RDWRB", "I12": "CFG_CENTER_ICAP0_I12", - "O5": "CFG_CENTER_ICAP0_O5", - "I11": "CFG_CENTER_ICAP0_I11", - "I8": "CFG_CENTER_ICAP0_I8", - "I16": "CFG_CENTER_ICAP0_I16", - "O1": "CFG_CENTER_ICAP0_O1", - "I2": "CFG_CENTER_ICAP0_I2", - "O28": "CFG_CENTER_ICAP0_O28", + "O30": "CFG_CENTER_ICAP0_O30", + "O4": "CFG_CENTER_ICAP0_O4", + "O0": "CFG_CENTER_ICAP0_O0", "I14": "CFG_CENTER_ICAP0_I14", - "O16": "CFG_CENTER_ICAP0_O16", - "O18": "CFG_CENTER_ICAP0_O18", - "O17": "CFG_CENTER_ICAP0_O17", - "I19": "CFG_CENTER_ICAP0_I19", - "I25": "CFG_CENTER_ICAP0_I25", "O21": "CFG_CENTER_ICAP0_O21", - "I7": "CFG_CENTER_ICAP0_I7", - "I30": "CFG_CENTER_ICAP0_I30", - "O19": "CFG_CENTER_ICAP0_O19", - "I17": "CFG_CENTER_ICAP0_I17", - "I13": "CFG_CENTER_ICAP0_I13", - "I24": "CFG_CENTER_ICAP0_I24" + "O15": "CFG_CENTER_ICAP0_O15", + "I18": "CFG_CENTER_ICAP0_I18", + "O17": "CFG_CENTER_ICAP0_O17" }, + "type": "ICAP", + "prefix": "ICAP", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 }, { - "prefix": "FRAME_ECC", - "y_coord": 0, - "type": "FRAME_ECC", "site_pins": { - "SYNDROME9": "CFG_CENTER_FRAME_ECC_SYNDROME9", - "SYNDROME4": "CFG_CENTER_FRAME_ECC_SYNDROME4", - "FAR10": "CFG_CENTER_FRAME_ECC_FAR10", - "SYNDROME5": "CFG_CENTER_FRAME_ECC_SYNDROME5", - "FAR14": "CFG_CENTER_FRAME_ECC_FAR14", - "ECCERRORSINGLE": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", - "FAR17": "CFG_CENTER_FRAME_ECC_FAR17", - "FAR24": "CFG_CENTER_FRAME_ECC_FAR24", - "SYNWORD3": "CFG_CENTER_FRAME_ECC_SYNWORD3", - "SYNDROME10": "CFG_CENTER_FRAME_ECC_SYNDROME10", - "SYNDROME11": "CFG_CENTER_FRAME_ECC_SYNDROME11", "FAR15": "CFG_CENTER_FRAME_ECC_FAR15", - "SYNDROME7": "CFG_CENTER_FRAME_ECC_SYNDROME7", - "ECCERROR": "CFG_CENTER_FRAME_ECC_ECCERROR", - "SYNWORD6": "CFG_CENTER_FRAME_ECC_SYNWORD6", - "SYNDROME3": "CFG_CENTER_FRAME_ECC_SYNDROME3", - "FAR5": "CFG_CENTER_FRAME_ECC_FAR5", - "SYNBIT2": "CFG_CENTER_FRAME_ECC_SYNBIT2", - "SYNDROME2": "CFG_CENTER_FRAME_ECC_SYNDROME2", - "FAR2": "CFG_CENTER_FRAME_ECC_FAR2", + "FAR0": "CFG_CENTER_FRAME_ECC_FAR0", + "SYNDROME6": "CFG_CENTER_FRAME_ECC_SYNDROME6", + "FAR7": "CFG_CENTER_FRAME_ECC_FAR7", + "SYNDROME4": "CFG_CENTER_FRAME_ECC_SYNDROME4", + "FAR1": "CFG_CENTER_FRAME_ECC_FAR1", "SYNDROME0": "CFG_CENTER_FRAME_ECC_SYNDROME0", + "FAR9": "CFG_CENTER_FRAME_ECC_FAR9", + "SYNDROME10": "CFG_CENTER_FRAME_ECC_SYNDROME10", + "SYNBIT1": "CFG_CENTER_FRAME_ECC_SYNBIT1", + "FAR21": "CFG_CENTER_FRAME_ECC_FAR21", + "SYNWORD0": "CFG_CENTER_FRAME_ECC_SYNWORD0", + "SYNDROME9": "CFG_CENTER_FRAME_ECC_SYNDROME9", + "FAR14": "CFG_CENTER_FRAME_ECC_FAR14", + "FAR24": "CFG_CENTER_FRAME_ECC_FAR24", + "ECCERROR": "CFG_CENTER_FRAME_ECC_ECCERROR", "SYNWORD1": "CFG_CENTER_FRAME_ECC_SYNWORD1", - "FAR16": "CFG_CENTER_FRAME_ECC_FAR16", + "FAR12": "CFG_CENTER_FRAME_ECC_FAR12", + "ECCERRORSINGLE": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", + "SYNWORD3": "CFG_CENTER_FRAME_ECC_SYNWORD3", + "SYNDROME12": "CFG_CENTER_FRAME_ECC_SYNDROME12", + "SYNWORD6": "CFG_CENTER_FRAME_ECC_SYNWORD6", + "SYNBIT4": "CFG_CENTER_FRAME_ECC_SYNBIT4", + "FAR2": "CFG_CENTER_FRAME_ECC_FAR2", + "SYNDROME8": "CFG_CENTER_FRAME_ECC_SYNDROME8", + "FAR10": "CFG_CENTER_FRAME_ECC_FAR10", + "SYNBIT3": "CFG_CENTER_FRAME_ECC_SYNBIT3", + "FAR3": "CFG_CENTER_FRAME_ECC_FAR3", + "FAR25": "CFG_CENTER_FRAME_ECC_FAR25", "SYNWORD5": "CFG_CENTER_FRAME_ECC_SYNWORD5", "FAR22": "CFG_CENTER_FRAME_ECC_FAR22", - "SYNBIT3": "CFG_CENTER_FRAME_ECC_SYNBIT3", - "FAR12": "CFG_CENTER_FRAME_ECC_FAR12", - "FAR13": "CFG_CENTER_FRAME_ECC_FAR13", - "SYNWORD4": "CFG_CENTER_FRAME_ECC_SYNWORD4", + "FAR17": "CFG_CENTER_FRAME_ECC_FAR17", + "FAR5": "CFG_CENTER_FRAME_ECC_FAR5", + "SYNDROME7": "CFG_CENTER_FRAME_ECC_SYNDROME7", + "FAR20": "CFG_CENTER_FRAME_ECC_FAR20", "SYNDROMEVALID": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", - "FAR6": "CFG_CENTER_FRAME_ECC_FAR6", - "SYNBIT0": "CFG_CENTER_FRAME_ECC_SYNBIT0", - "SYNDROME8": "CFG_CENTER_FRAME_ECC_SYNDROME8", - "SYNWORD0": "CFG_CENTER_FRAME_ECC_SYNWORD0", - "FAR7": "CFG_CENTER_FRAME_ECC_FAR7", - "FAR9": "CFG_CENTER_FRAME_ECC_FAR9", - "FAR23": "CFG_CENTER_FRAME_ECC_FAR23", - "FAR4": "CFG_CENTER_FRAME_ECC_FAR4", - "FAR21": "CFG_CENTER_FRAME_ECC_FAR21", + "FAR16": "CFG_CENTER_FRAME_ECC_FAR16", + "SYNDROME5": "CFG_CENTER_FRAME_ECC_SYNDROME5", + "SYNDROME3": "CFG_CENTER_FRAME_ECC_SYNDROME3", + "FAR13": "CFG_CENTER_FRAME_ECC_FAR13", "FAR8": "CFG_CENTER_FRAME_ECC_FAR8", - "SYNDROME1": "CFG_CENTER_FRAME_ECC_SYNDROME1", - "FAR25": "CFG_CENTER_FRAME_ECC_FAR25", - "FAR18": "CFG_CENTER_FRAME_ECC_FAR18", - "SYNBIT1": "CFG_CENTER_FRAME_ECC_SYNBIT1", - "FAR0": "CFG_CENTER_FRAME_ECC_FAR0", + "FAR23": "CFG_CENTER_FRAME_ECC_FAR23", + "SYNDROME11": "CFG_CENTER_FRAME_ECC_SYNDROME11", "FAR11": "CFG_CENTER_FRAME_ECC_FAR11", "SYNWORD2": "CFG_CENTER_FRAME_ECC_SYNWORD2", - "SYNBIT4": "CFG_CENTER_FRAME_ECC_SYNBIT4", - "FAR1": "CFG_CENTER_FRAME_ECC_FAR1", - "CRCERROR": "CFG_CENTER_FRAME_ECC_CRCERROR", - "SYNDROME12": "CFG_CENTER_FRAME_ECC_SYNDROME12", + "SYNDROME1": "CFG_CENTER_FRAME_ECC_SYNDROME1", + "SYNBIT0": "CFG_CENTER_FRAME_ECC_SYNBIT0", + "FAR6": "CFG_CENTER_FRAME_ECC_FAR6", + "SYNBIT2": "CFG_CENTER_FRAME_ECC_SYNBIT2", "FAR19": "CFG_CENTER_FRAME_ECC_FAR19", - "SYNDROME6": "CFG_CENTER_FRAME_ECC_SYNDROME6", - "FAR3": "CFG_CENTER_FRAME_ECC_FAR3", - "FAR20": "CFG_CENTER_FRAME_ECC_FAR20" + "FAR18": "CFG_CENTER_FRAME_ECC_FAR18", + "CRCERROR": "CFG_CENTER_FRAME_ECC_CRCERROR", + "SYNDROME2": "CFG_CENTER_FRAME_ECC_SYNDROME2", + "SYNWORD4": "CFG_CENTER_FRAME_ECC_SYNWORD4", + "FAR4": "CFG_CENTER_FRAME_ECC_FAR4" }, + "type": "FRAME_ECC", + "prefix": "FRAME_ECC", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 }, { - "prefix": "STARTUP", - "y_coord": 0, - "type": "STARTUP", "site_pins": { - "PACK": "CFG_CENTER_STARTUP_PACK", - "CLK": "CFG_CENTER_STARTUP_CLK", - "USRCCLKTS": "CFG_CENTER_STARTUP_USRCCLKTS", - "USRDONETS": "CFG_CENTER_STARTUP_USRDONETS", - "GSR": "CFG_CENTER_STARTUP_GSR", - "KEYCLEARB": "CFG_CENTER_STARTUP_KEYCLEARB", - "CFGMCLK": "CFG_CENTER_STARTUP_CFGMCLK", - "GTS": "CFG_CENTER_STARTUP_GTS", "USRCCLKO": "CFG_CENTER_STARTUP_USRCCLKO", + "CFGMCLK": "CFG_CENTER_STARTUP_CFGMCLK", + "USRCCLKTS": "CFG_CENTER_STARTUP_USRCCLKTS", "CFGCLK": "CFG_CENTER_STARTUP_CFGCLK", - "EOS": "CFG_CENTER_STARTUP_EOS", + "PREQ": "CFG_CENTER_STARTUP_PREQ", + "KEYCLEARB": "CFG_CENTER_STARTUP_KEYCLEARB", + "CLK": "CFG_CENTER_STARTUP_CLK", + "GSR": "CFG_CENTER_STARTUP_GSR", + "USRDONETS": "CFG_CENTER_STARTUP_USRDONETS", + "PACK": "CFG_CENTER_STARTUP_PACK", + "GTS": "CFG_CENTER_STARTUP_GTS", "USRDONEO": "CFG_CENTER_STARTUP_USRDONEO", - "PREQ": "CFG_CENTER_STARTUP_PREQ" + "EOS": "CFG_CENTER_STARTUP_EOS" }, + "type": "STARTUP", + "prefix": "STARTUP", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 }, { - "prefix": "CAPTURE", - "y_coord": 0, - "type": "CAPTURE", "site_pins": { - "CLK": "CFG_CENTER_CAPTURE_CLK", - "CAP": "CFG_CENTER_CAPTURE_CAP" + "CAP": "CFG_CENTER_CAPTURE_CAP", + "CLK": "CFG_CENTER_CAPTURE_CLK" }, + "type": "CAPTURE", + "prefix": "CAPTURE", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 }, { - "prefix": "DCIRESET", - "y_coord": 0, - "type": "DCIRESET", "site_pins": { "LOCKED": "CFG_CENTER_DCIRESET_LOCKED", "RST": "CFG_CENTER_DCIRESET_RST" }, + "type": "DCIRESET", + "prefix": "DCIRESET", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 }, { - "prefix": "BSCAN", - "y_coord": 2, - "type": "BSCAN", "site_pins": { "TDI": "CFG_CENTER_BSCAN3_TDI", - "SHIFT": "CFG_CENTER_BSCAN3_SHIFT", - "SEL": "CFG_CENTER_BSCAN3_SEL", - "DRCK": "CFG_CENTER_BSCAN3_DRCK", + "UPDATE": "CFG_CENTER_BSCAN3_UPDATE", + "TMS": "CFG_CENTER_BSCAN3_TMS", "TDO": "CFG_CENTER_BSCAN3_TDO", "CAPTURE": "CFG_CENTER_BSCAN3_CAPTURE", - "TMS": "CFG_CENTER_BSCAN3_TMS", - "TCK": "CFG_CENTER_BSCAN3_TCK", - "UPDATE": "CFG_CENTER_BSCAN3_UPDATE", + "DRCK": "CFG_CENTER_BSCAN3_DRCK", "RUNTEST": "CFG_CENTER_BSCAN3_RUNTEST", - "RESET": "CFG_CENTER_BSCAN3_RESET" + "RESET": "CFG_CENTER_BSCAN3_RESET", + "TCK": "CFG_CENTER_BSCAN3_TCK", + "SEL": "CFG_CENTER_BSCAN3_SEL", + "SHIFT": "CFG_CENTER_BSCAN3_SHIFT" }, + "type": "BSCAN", + "prefix": "BSCAN", + "name": "X0Y2", "x_coord": 0, - "name": "X0Y2" + "y_coord": 2 }, { - "prefix": "BSCAN", - "y_coord": 3, - "type": "BSCAN", "site_pins": { "TDI": "CFG_CENTER_BSCAN4_TDI", - "SHIFT": "CFG_CENTER_BSCAN4_SHIFT", - "SEL": "CFG_CENTER_BSCAN4_SEL", - "DRCK": "CFG_CENTER_BSCAN4_DRCK", + "UPDATE": "CFG_CENTER_BSCAN4_UPDATE", + "TMS": "CFG_CENTER_BSCAN4_TMS", "TDO": "CFG_CENTER_BSCAN4_TDO", "CAPTURE": "CFG_CENTER_BSCAN4_CAPTURE", - "TMS": "CFG_CENTER_BSCAN4_TMS", - "TCK": "CFG_CENTER_BSCAN4_TCK", - "UPDATE": "CFG_CENTER_BSCAN4_UPDATE", + "DRCK": "CFG_CENTER_BSCAN4_DRCK", "RUNTEST": "CFG_CENTER_BSCAN4_RUNTEST", - "RESET": "CFG_CENTER_BSCAN4_RESET" + "RESET": "CFG_CENTER_BSCAN4_RESET", + "TCK": "CFG_CENTER_BSCAN4_TCK", + "SEL": "CFG_CENTER_BSCAN4_SEL", + "SHIFT": "CFG_CENTER_BSCAN4_SHIFT" }, + "type": "BSCAN", + "prefix": "BSCAN", + "name": "X0Y3", "x_coord": 0, - "name": "X0Y3" + "y_coord": 3 }, { - "prefix": "ICAP", - "y_coord": 1, - "type": "ICAP", "site_pins": { - "I26": "CFG_CENTER_ICAP1_I26", + "I24": "CFG_CENTER_ICAP1_I24", + "O12": "CFG_CENTER_ICAP1_O12", "O23": "CFG_CENTER_ICAP1_O23", - "O13": "CFG_CENTER_ICAP1_O13", "O31": "CFG_CENTER_ICAP1_O31", - "O15": "CFG_CENTER_ICAP1_O15", + "I16": "CFG_CENTER_ICAP1_I16", + "I11": "CFG_CENTER_ICAP1_I11", + "I2": "CFG_CENTER_ICAP1_I2", + "O29": "CFG_CENTER_ICAP1_O29", + "I26": "CFG_CENTER_ICAP1_I26", + "O11": "CFG_CENTER_ICAP1_O11", + "O9": "CFG_CENTER_ICAP1_O9", + "I4": "CFG_CENTER_ICAP1_I4", + "O20": "CFG_CENTER_ICAP1_O20", + "O24": "CFG_CENTER_ICAP1_O24", + "O7": "CFG_CENTER_ICAP1_O7", + "I22": "CFG_CENTER_ICAP1_I22", + "O1": "CFG_CENTER_ICAP1_O1", + "O25": "CFG_CENTER_ICAP1_O25", + "I8": "CFG_CENTER_ICAP1_I8", + "CLK": "CFG_CENTER_ICAP1_CLK", + "O5": "CFG_CENTER_ICAP1_O5", + "O18": "CFG_CENTER_ICAP1_O18", + "I5": "CFG_CENTER_ICAP1_I5", + "I6": "CFG_CENTER_ICAP1_I6", + "I31": "CFG_CENTER_ICAP1_I31", + "I25": "CFG_CENTER_ICAP1_I25", + "O28": "CFG_CENTER_ICAP1_O28", + "I3": "CFG_CENTER_ICAP1_I3", + "I30": "CFG_CENTER_ICAP1_I30", + "I7": "CFG_CENTER_ICAP1_I7", + "O2": "CFG_CENTER_ICAP1_O2", + "I20": "CFG_CENTER_ICAP1_I20", + "I21": "CFG_CENTER_ICAP1_I21", + "I23": "CFG_CENTER_ICAP1_I23", + "I9": "CFG_CENTER_ICAP1_I9", + "O19": "CFG_CENTER_ICAP1_O19", + "I0": "CFG_CENTER_ICAP1_I0", + "O22": "CFG_CENTER_ICAP1_O22", + "I19": "CFG_CENTER_ICAP1_I19", + "I13": "CFG_CENTER_ICAP1_I13", + "I28": "CFG_CENTER_ICAP1_I28", + "O6": "CFG_CENTER_ICAP1_O6", + "I1": "CFG_CENTER_ICAP1_I1", + "I17": "CFG_CENTER_ICAP1_I17", + "I10": "CFG_CENTER_ICAP1_I10", + "O10": "CFG_CENTER_ICAP1_O10", + "O16": "CFG_CENTER_ICAP1_O16", + "O3": "CFG_CENTER_ICAP1_O3", + "O13": "CFG_CENTER_ICAP1_O13", "O8": "CFG_CENTER_ICAP1_O8", "I27": "CFG_CENTER_ICAP1_I27", - "O12": "CFG_CENTER_ICAP1_O12", - "I18": "CFG_CENTER_ICAP1_I18", - "I6": "CFG_CENTER_ICAP1_I6", - "I3": "CFG_CENTER_ICAP1_I3", - "O2": "CFG_CENTER_ICAP1_O2", - "RDWRB": "CFG_CENTER_ICAP1_RDWRB", - "I31": "CFG_CENTER_ICAP1_I31", - "I1": "CFG_CENTER_ICAP1_I1", - "CSIB": "CFG_CENTER_ICAP1_CSIB", - "O24": "CFG_CENTER_ICAP1_O24", - "O20": "CFG_CENTER_ICAP1_O20", - "O22": "CFG_CENTER_ICAP1_O22", - "I29": "CFG_CENTER_ICAP1_I29", - "O27": "CFG_CENTER_ICAP1_O27", - "I9": "CFG_CENTER_ICAP1_I9", - "O4": "CFG_CENTER_ICAP1_O4", - "O26": "CFG_CENTER_ICAP1_O26", - "I10": "CFG_CENTER_ICAP1_I10", - "I21": "CFG_CENTER_ICAP1_I21", - "I20": "CFG_CENTER_ICAP1_I20", - "O9": "CFG_CENTER_ICAP1_O9", - "I22": "CFG_CENTER_ICAP1_I22", - "I28": "CFG_CENTER_ICAP1_I28", - "O11": "CFG_CENTER_ICAP1_O11", "O14": "CFG_CENTER_ICAP1_O14", - "O25": "CFG_CENTER_ICAP1_O25", "I15": "CFG_CENTER_ICAP1_I15", - "O10": "CFG_CENTER_ICAP1_O10", - "O7": "CFG_CENTER_ICAP1_O7", - "I4": "CFG_CENTER_ICAP1_I4", - "O6": "CFG_CENTER_ICAP1_O6", - "I5": "CFG_CENTER_ICAP1_I5", - "I23": "CFG_CENTER_ICAP1_I23", - "I0": "CFG_CENTER_ICAP1_I0", - "O30": "CFG_CENTER_ICAP1_O30", - "O29": "CFG_CENTER_ICAP1_O29", - "O3": "CFG_CENTER_ICAP1_O3", - "CLK": "CFG_CENTER_ICAP1_CLK", - "O0": "CFG_CENTER_ICAP1_O0", + "O26": "CFG_CENTER_ICAP1_O26", + "O27": "CFG_CENTER_ICAP1_O27", + "CSIB": "CFG_CENTER_ICAP1_CSIB", + "I29": "CFG_CENTER_ICAP1_I29", + "RDWRB": "CFG_CENTER_ICAP1_RDWRB", "I12": "CFG_CENTER_ICAP1_I12", - "O5": "CFG_CENTER_ICAP1_O5", - "I11": "CFG_CENTER_ICAP1_I11", - "I8": "CFG_CENTER_ICAP1_I8", - "I16": "CFG_CENTER_ICAP1_I16", - "O1": "CFG_CENTER_ICAP1_O1", - "I2": "CFG_CENTER_ICAP1_I2", - "O28": "CFG_CENTER_ICAP1_O28", + "O30": "CFG_CENTER_ICAP1_O30", + "O4": "CFG_CENTER_ICAP1_O4", + "O0": "CFG_CENTER_ICAP1_O0", "I14": "CFG_CENTER_ICAP1_I14", - "O16": "CFG_CENTER_ICAP1_O16", - "O18": "CFG_CENTER_ICAP1_O18", - "O17": "CFG_CENTER_ICAP1_O17", - "I19": "CFG_CENTER_ICAP1_I19", - "I25": "CFG_CENTER_ICAP1_I25", "O21": "CFG_CENTER_ICAP1_O21", - "I7": "CFG_CENTER_ICAP1_I7", - "I30": "CFG_CENTER_ICAP1_I30", - "O19": "CFG_CENTER_ICAP1_O19", - "I17": "CFG_CENTER_ICAP1_I17", - "I13": "CFG_CENTER_ICAP1_I13", - "I24": "CFG_CENTER_ICAP1_I24" + "O15": "CFG_CENTER_ICAP1_O15", + "I18": "CFG_CENTER_ICAP1_I18", + "O17": "CFG_CENTER_ICAP1_O17" }, + "type": "ICAP", + "prefix": "ICAP", + "name": "X0Y1", "x_coord": 0, - "name": "X0Y1" + "y_coord": 1 } - ], - "pips": { - "CFG_CENTER_MID.CFG_CENTER_IMUX39_11->CFG_CENTER_BSCAN4_TDO": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_BSCAN4_TDO", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX39_11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX40_5->CFG_CENTER_ICAP0_I29": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I29", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX40_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RUNTEST->CFG_CENTER_LOGIC_OUTS_B8_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_RUNTEST", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX35_8->CFG_CENTER_DCIRESET_RST": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_DCIRESET_RST", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX35_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA25->CFG_CENTER_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA25", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR19->CFG_CENTER_LOGIC_OUTS_B13_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR19", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME3->CFG_CENTER_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME3", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME8->CFG_CENTER_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERRORSINGLE->CFG_CENTER_LOGIC_OUTS_B23_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX38_4->CFG_CENTER_ICAP0_I10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I10", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX38_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_DRCK->CFG_CENTER_LOGIC_OUTS_B22_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_DRCK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O24->CFG_CENTER_LOGIC_OUTS_B23_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O24", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O9->CFG_CENTER_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O9", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR20->CFG_CENTER_LOGIC_OUTS_B14_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR20", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA27->CFG_CENTER_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA27", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O1->CFG_CENTER_LOGIC_OUTS_B12_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O1", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RUNTEST->CFG_CENTER_LOGIC_OUTS_B14_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_RUNTEST", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O3->CFG_CENTER_LOGIC_OUTS_B19_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O3", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SHIFT->CFG_CENTER_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_SHIFT", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O31->CFG_CENTER_LOGIC_OUTS_B15_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O31", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_UPDATE->CFG_CENTER_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_UPDATE", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD1->CFG_CENTER_LOGIC_OUTS_B21_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD1", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_CAPTURE->CFG_CENTER_LOGIC_OUTS_B12_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_CAPTURE", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX30_13->CFG_CENTER_ICAP1_I18": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I18", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX30_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O24->CFG_CENTER_LOGIC_OUTS_B8_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O24", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD0->CFG_CENTER_LOGIC_OUTS_B20_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD0", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA29->CFG_CENTER_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA29", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O8->CFG_CENTER_LOGIC_OUTS_B19_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX36_5->CFG_CENTER_ICAP0_I25": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I25", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX36_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O15->CFG_CENTER_LOGIC_OUTS_B14_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O15", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATAVALID->CFG_CENTER_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATAVALID", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR0->CFG_CENTER_LOGIC_OUTS_B10_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR0", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O6->CFG_CENTER_LOGIC_OUTS_B17_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O6", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD4->CFG_CENTER_LOGIC_OUTS_B8_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR13->CFG_CENTER_LOGIC_OUTS_B23_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX42_11->CFG_CENTER_ICAP1_RDWRB": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_RDWRB", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX42_11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA20->CFG_CENTER_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA20", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SHIFT->CFG_CENTER_LOGIC_OUTS_B21_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_SHIFT", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_UPDATE->CFG_CENTER_LOGIC_OUTS_B19_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_UPDATE", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX37_4->CFG_CENTER_ICAP0_I9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I9", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX37_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGCLK->CFG_CENTER_LOGIC_OUTS_B14_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_STARTUP_CFGCLK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O13->CFG_CENTER_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O20->CFG_CENTER_LOGIC_OUTS_B19_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O20", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_UPDATE->CFG_CENTER_LOGIC_OUTS_B16_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_UPDATE", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA24->CFG_CENTER_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA24", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX42_12->CFG_CENTER_ICAP1_I14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I14", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX42_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME6->CFG_CENTER_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME6", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O29->CFG_CENTER_LOGIC_OUTS_B13_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O29", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX36_4->CFG_CENTER_ICAP0_I8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I8", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX36_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TMS->CFG_CENTER_LOGIC_OUTS_B11_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_TMS", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX34_12->CFG_CENTER_ICAP1_I6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I6", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX34_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX37_13->CFG_CENTER_ICAP1_I25": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I25", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX37_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TMS->CFG_CENTER_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_TMS", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX32_12->CFG_CENTER_ICAP1_I4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I4", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX32_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O6->CFG_CENTER_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O6", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR4->CFG_CENTER_LOGIC_OUTS_B14_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_DRCK->CFG_CENTER_LOGIC_OUTS_B23_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_DRCK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA23->CFG_CENTER_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA23", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT3->CFG_CENTER_LOGIC_OUTS_B21_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT3", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX39_12->CFG_CENTER_ICAP1_I11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I11", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX39_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O2->CFG_CENTER_LOGIC_OUTS_B13_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O2", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TMS->CFG_CENTER_LOGIC_OUTS_B16_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_TMS", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RUNTEST->CFG_CENTER_LOGIC_OUTS_B13_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_RUNTEST", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O13->CFG_CENTER_LOGIC_OUTS_B12_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX43_8->CFG_CENTER_STARTUP_PACK": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_STARTUP_PACK", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX43_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX36_13->CFG_CENTER_ICAP1_I24": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I24", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX36_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX41_5->CFG_CENTER_ICAP0_I30": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I30", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX41_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RESET->CFG_CENTER_LOGIC_OUTS_B21_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_RESET", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O27->CFG_CENTER_LOGIC_OUTS_B12_14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_14", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O27", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_CLK1_5->CFG_CENTER_STARTUP_CLK": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_STARTUP_CLK", - "is_directional": "1", - "src_wire": "CFG_CENTER_CLK1_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA28->CFG_CENTER_LOGIC_OUTS_B23_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA28", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RESET->CFG_CENTER_LOGIC_OUTS_B20_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_RESET", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME7->CFG_CENTER_LOGIC_OUTS_B21_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME7", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD6->CFG_CENTER_LOGIC_OUTS_B17_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD6", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX31_5->CFG_CENTER_ICAP0_I20": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I20", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX31_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR7->CFG_CENTER_LOGIC_OUTS_B17_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR7", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA3->CFG_CENTER_MID_USR_ACCESS_DATA3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA3", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA3", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O18->CFG_CENTER_LOGIC_OUTS_B17_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O18", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR6->CFG_CENTER_LOGIC_OUTS_B16_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR6", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O25->CFG_CENTER_LOGIC_OUTS_B10_14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_14", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O25", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR24->CFG_CENTER_LOGIC_OUTS_B18_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR24", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SEL->CFG_CENTER_LOGIC_OUTS_B16_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_SEL", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA14->CFG_CENTER_MID_USR_ACCESS_DATA14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA14", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA14", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR17->CFG_CENTER_LOGIC_OUTS_B11_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR17", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_STARTUP_EOS->CFG_CENTER_LOGIC_OUTS_B23_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_STARTUP_EOS", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA11->CFG_CENTER_MID_USR_ACCESS_DATA11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA11", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR14->CFG_CENTER_LOGIC_OUTS_B8_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR14", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O1->CFG_CENTER_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O1", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX28_13->CFG_CENTER_ICAP1_I16": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I16", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX28_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME11->CFG_CENTER_LOGIC_OUTS_B11_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O25->CFG_CENTER_LOGIC_OUTS_B9_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O25", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O19->CFG_CENTER_LOGIC_OUTS_B19_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O19", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_MID_ICAP1_CLK->CFG_CENTER_ICAP1_CLK": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_CLK", - "is_directional": "1", - "src_wire": "CFG_CENTER_MID_ICAP1_CLK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX41_4->CFG_CENTER_ICAP0_I13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I13", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX41_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR21->CFG_CENTER_LOGIC_OUTS_B15_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR21", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA19->CFG_CENTER_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA19", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX39_4->CFG_CENTER_ICAP0_I11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I11", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX39_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGMCLK->CFG_CENTER_LOGIC_OUTS_B18_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_STARTUP_CFGMCLK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O3->CFG_CENTER_LOGIC_OUTS_B14_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O3", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR9->CFG_CENTER_LOGIC_OUTS_B19_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR9", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX27_5->CFG_CENTER_ICAP0_I16": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I16", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX27_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O28->CFG_CENTER_LOGIC_OUTS_B13_14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_14", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O28", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA13->CFG_CENTER_MID_USR_ACCESS_DATA13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA13", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SEL->CFG_CENTER_LOGIC_OUTS_B17_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_SEL", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX29_12->CFG_CENTER_ICAP1_I1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I1", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX29_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX43_13->CFG_CENTER_ICAP1_I31": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I31", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX43_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_CLK1_9->CFG_CENTER_CAPTURE_CLK": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_CAPTURE_CLK", - "is_directional": "1", - "src_wire": "CFG_CENTER_CLK1_9", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O15->CFG_CENTER_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O15", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX37_12->CFG_CENTER_ICAP1_I9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I9", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX37_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX42_8->CFG_CENTER_STARTUP_USRDONEO": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_STARTUP_USRDONEO", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX42_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O20->CFG_CENTER_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O20", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O9->CFG_CENTER_LOGIC_OUTS_B20_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O9", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX34_3->CFG_CENTER_BSCAN2_TDO": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_BSCAN2_TDO", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX34_3", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX29_5->CFG_CENTER_ICAP0_I18": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I18", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX29_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME1->CFG_CENTER_LOGIC_OUTS_B15_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME1", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SHIFT->CFG_CENTER_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_SHIFT", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O21->CFG_CENTER_LOGIC_OUTS_B21_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O21", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TCK->CFG_CENTER_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_TCK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_CLK1_6->CFG_CENTER_ICAP0_CLK": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_CLK", - "is_directional": "1", - "src_wire": "CFG_CENTER_CLK1_6", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX31_13->CFG_CENTER_ICAP1_I19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I19", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX31_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SEL->CFG_CENTER_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_SEL", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX41_11->CFG_CENTER_ICAP0_RDWRB": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_RDWRB", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX41_11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_UPDATE->CFG_CENTER_LOGIC_OUTS_B18_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_UPDATE", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX33_12->CFG_CENTER_ICAP1_I5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I5", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX33_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX35_13->CFG_CENTER_ICAP1_I23": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I23", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX35_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O10->CFG_CENTER_LOGIC_OUTS_B21_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O10", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O4->CFG_CENTER_LOGIC_OUTS_B20_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA7->CFG_CENTER_MID_USR_ACCESS_DATA7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA7", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA7", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA2->CFG_CENTER_MID_USR_ACCESS_DATA2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA2", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA2", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O16->CFG_CENTER_LOGIC_OUTS_B16_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O16", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_CLK1_8->CFG_CENTER_MID_DNA_PORT_CLK": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_DNA_PORT_CLK", - "is_directional": "1", - "src_wire": "CFG_CENTER_CLK1_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O22->CFG_CENTER_LOGIC_OUTS_B21_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O22", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O8->CFG_CENTER_LOGIC_OUTS_B8_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O28->CFG_CENTER_LOGIC_OUTS_B12_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O28", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX42_13->CFG_CENTER_ICAP1_I30": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I30", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX42_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O0->CFG_CENTER_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O0", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX34_5->CFG_CENTER_ICAP0_I23": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I23", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX34_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RUNTEST->CFG_CENTER_LOGIC_OUTS_B9_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_RUNTEST", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O11->CFG_CENTER_LOGIC_OUTS_B22_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA10->CFG_CENTER_MID_USR_ACCESS_DATA10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA10", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA10", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX40_12->CFG_CENTER_ICAP1_I12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I12", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX40_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR3->CFG_CENTER_LOGIC_OUTS_B13_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR3", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_DCIRESET_LOCKED->CFG_CENTER_LOGIC_OUTS_B21_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_DCIRESET_LOCKED", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX36_8->CFG_CENTER_STARTUP_KEYCLEARB": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_STARTUP_KEYCLEARB", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX36_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR18->CFG_CENTER_LOGIC_OUTS_B12_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR18", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O23->CFG_CENTER_LOGIC_OUTS_B22_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O23", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX41_8->CFG_CENTER_STARTUP_USRDONETS": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_STARTUP_USRDONETS", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX41_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME5->CFG_CENTER_LOGIC_OUTS_B19_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TDI->CFG_CENTER_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_TDI", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX33_4->CFG_CENTER_ICAP0_I5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I5", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX33_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA30->CFG_CENTER_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA30", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_DRCK->CFG_CENTER_LOGIC_OUTS_B21_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_DRCK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR16->CFG_CENTER_LOGIC_OUTS_B10_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR16", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA1->CFG_CENTER_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA1", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA26->CFG_CENTER_LOGIC_OUTS_B21_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA26", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA22->CFG_CENTER_LOGIC_OUTS_B17_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA22", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT1->CFG_CENTER_LOGIC_OUTS_B19_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT1", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX33_5->CFG_CENTER_ICAP0_I22": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I22", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX33_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR25->CFG_CENTER_LOGIC_OUTS_B19_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR25", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX40_4->CFG_CENTER_ICAP0_I12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I12", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX40_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX40_11->CFG_CENTER_ICAP0_CSIB": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_CSIB", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX40_11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA31->CFG_CENTER_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA31", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX40_8->CFG_CENTER_STARTUP_GSR": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_STARTUP_GSR", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX40_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX31_12->CFG_CENTER_ICAP1_I3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I3", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX31_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX43_11->CFG_CENTER_ICAP1_CSIB": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_CSIB", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX43_11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O2->CFG_CENTER_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O2", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SEL->CFG_CENTER_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_SEL", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O27->CFG_CENTER_LOGIC_OUTS_B11_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O27", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O22->CFG_CENTER_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O22", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O29->CFG_CENTER_LOGIC_OUTS_B14_14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_14", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O29", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX40_13->CFG_CENTER_ICAP1_I28": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I28", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX40_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX33_3->CFG_CENTER_BSCAN1_TDO": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_BSCAN1_TDO", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX33_3", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX28_12->CFG_CENTER_ICAP1_I0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I0", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX28_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_DRCK->CFG_CENTER_LOGIC_OUTS_B20_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_DRCK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O12->CFG_CENTER_LOGIC_OUTS_B23_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX36_12->CFG_CENTER_ICAP1_I8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I8", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX36_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O19->CFG_CENTER_LOGIC_OUTS_B18_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O19", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD2->CFG_CENTER_LOGIC_OUTS_B22_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD2", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SHIFT->CFG_CENTER_LOGIC_OUTS_B22_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_SHIFT", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR23->CFG_CENTER_LOGIC_OUTS_B17_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR23", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA18->CFG_CENTER_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA18", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O26->CFG_CENTER_LOGIC_OUTS_B10_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O26", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA5->CFG_CENTER_MID_USR_ACCESS_DATA5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA5", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O7->CFG_CENTER_LOGIC_OUTS_B18_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O7", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_STARTUP_PREQ->CFG_CENTER_LOGIC_OUTS_B22_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_STARTUP_PREQ", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_CAPTURE->CFG_CENTER_LOGIC_OUTS_B23_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_CAPTURE", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX42_5->CFG_CENTER_ICAP0_I31": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I31", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX42_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_CAPTURE->CFG_CENTER_LOGIC_OUTS_B11_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_CAPTURE", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RESET->CFG_CENTER_LOGIC_OUTS_B19_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN2_RESET", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_CRCERROR->CFG_CENTER_LOGIC_OUTS_B15_10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_10", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_CRCERROR", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA12->CFG_CENTER_MID_USR_ACCESS_DATA12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA12", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O30->CFG_CENTER_LOGIC_OUTS_B15_14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_14", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O30", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX41_13->CFG_CENTER_ICAP1_I29": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I29", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX41_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TCK->CFG_CENTER_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_TCK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O21->CFG_CENTER_LOGIC_OUTS_B20_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O21", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX33_13->CFG_CENTER_ICAP1_I21": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I21", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX33_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME4->CFG_CENTER_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O12->CFG_CENTER_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RESET->CFG_CENTER_LOGIC_OUTS_B18_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_RESET", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O10->CFG_CENTER_LOGIC_OUTS_B10_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O10", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX43_4->CFG_CENTER_ICAP0_I15": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I15", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX43_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX35_4->CFG_CENTER_ICAP0_I7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I7", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX35_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX43_12->CFG_CENTER_ICAP1_I15": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I15", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX43_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME0->CFG_CENTER_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME0", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME2->CFG_CENTER_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME2", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROMEVALID->CFG_CENTER_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_CLK1_7->CFG_CENTER_STARTUP_USRCCLKO": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_STARTUP_USRCCLKO", - "is_directional": "1", - "src_wire": "CFG_CENTER_CLK1_7", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O18->CFG_CENTER_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O18", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX29_13->CFG_CENTER_ICAP1_I17": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I17", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX29_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O23->CFG_CENTER_LOGIC_OUTS_B23_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O23", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERROR->CFG_CENTER_LOGIC_OUTS_B20_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_ECCERROR", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX34_13->CFG_CENTER_ICAP1_I22": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I22", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX34_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX32_13->CFG_CENTER_ICAP1_I20": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I20", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX32_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX37_8->CFG_CENTER_CAPTURE_CAP": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_CAPTURE_CAP", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX37_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O14->CFG_CENTER_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O14", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TCK->CFG_CENTER_LOGIC_OUTS_B20_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_TCK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX38_12->CFG_CENTER_ICAP1_I10": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I10", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX38_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O4->CFG_CENTER_LOGIC_OUTS_B15_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR2->CFG_CENTER_LOGIC_OUTS_B12_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR2", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA21->CFG_CENTER_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA21", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX30_5->CFG_CENTER_ICAP0_I19": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I19", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX30_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX32_4->CFG_CENTER_ICAP0_I4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I4", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX32_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT0->CFG_CENTER_LOGIC_OUTS_B18_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT0", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA8->CFG_CENTER_MID_USR_ACCESS_DATA8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA8", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT2->CFG_CENTER_LOGIC_OUTS_B20_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT2", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX38_5->CFG_CENTER_ICAP0_I27": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I27", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX38_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O5->CFG_CENTER_LOGIC_OUTS_B21_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX31_4->CFG_CENTER_ICAP0_I3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I3", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX31_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT4->CFG_CENTER_LOGIC_OUTS_B22_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR8->CFG_CENTER_LOGIC_OUTS_B18_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR11->CFG_CENTER_LOGIC_OUTS_B21_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR12->CFG_CENTER_LOGIC_OUTS_B22_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX29_4->CFG_CENTER_ICAP0_I1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I1", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX29_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA6->CFG_CENTER_MID_USR_ACCESS_DATA6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA6", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA6", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX41_12->CFG_CENTER_ICAP1_I13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I13", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX41_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX34_4->CFG_CENTER_ICAP0_I6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I6", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX34_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA4->CFG_CENTER_MID_USR_ACCESS_DATA4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA4", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX39_8->CFG_CENTER_STARTUP_GTS": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_STARTUP_GTS", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX39_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD3->CFG_CENTER_LOGIC_OUTS_B23_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD3", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TCK->CFG_CENTER_LOGIC_OUTS_B19_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_TCK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA17->CFG_CENTER_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA17", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD5->CFG_CENTER_LOGIC_OUTS_B9_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_CFGCLK->CFG_CENTER_LOGIC_OUTS_B9_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_CFGCLK", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O14->CFG_CENTER_LOGIC_OUTS_B13_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O14", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX38_11->CFG_CENTER_BSCAN3_TDO": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_BSCAN3_TDO", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX38_11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX37_5->CFG_CENTER_ICAP0_I26": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I26", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX37_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_CAPTURE->CFG_CENTER_LOGIC_OUTS_B22_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_CAPTURE", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX28_5->CFG_CENTER_ICAP0_I17": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I17", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX28_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX28_4->CFG_CENTER_ICAP0_I0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I0", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX28_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX42_4->CFG_CENTER_ICAP0_I14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I14", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX42_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O30->CFG_CENTER_LOGIC_OUTS_B14_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O30", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX38_13->CFG_CENTER_ICAP1_I26": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I26", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX38_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX38_8->CFG_CENTER_STARTUP_USRCCLKTS": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_STARTUP_USRCCLKTS", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX38_8", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR1->CFG_CENTER_LOGIC_OUTS_B11_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR1", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX30_4->CFG_CENTER_ICAP0_I2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I2", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX30_4", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O17->CFG_CENTER_LOGIC_OUTS_B17_5": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_5", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O17", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TDI->CFG_CENTER_LOGIC_OUTS_B18_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN4_TDI", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR15->CFG_CENTER_LOGIC_OUTS_B9_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR15", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR22->CFG_CENTER_LOGIC_OUTS_B16_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR22", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA16->CFG_CENTER_LOGIC_OUTS_B11_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA16", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX39_5->CFG_CENTER_ICAP0_I28": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I28", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX39_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TDI->CFG_CENTER_LOGIC_OUTS_B17_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_TDI", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA15->CFG_CENTER_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA15", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA0->CFG_CENTER_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA0", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O31->CFG_CENTER_LOGIC_OUTS_B16_14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_14", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O31", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME10->CFG_CENTER_LOGIC_OUTS_B10_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME10", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX39_13->CFG_CENTER_ICAP1_I27": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I27", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX39_13", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O5->CFG_CENTER_LOGIC_OUTS_B16_12": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_12", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O17->CFG_CENTER_LOGIC_OUTS_B16_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O17", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O26->CFG_CENTER_LOGIC_OUTS_B11_14": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_14", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O26", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O11->CFG_CENTER_LOGIC_OUTS_B11_4": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_4", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O11", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX30_12->CFG_CENTER_ICAP1_I2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I2", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX30_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX35_5->CFG_CENTER_ICAP0_I24": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I24", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX35_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX32_5->CFG_CENTER_ICAP0_I21": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP0_I21", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX32_5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA9->CFG_CENTER_MID_USR_ACCESS_DATA9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA9", - "is_directional": "1", - "src_wire": "CFG_CENTER_USR_ACCESS_DATA9", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O16->CFG_CENTER_LOGIC_OUTS_B15_13": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_13", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O16", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME9->CFG_CENTER_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME9", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_IMUX35_12->CFG_CENTER_ICAP1_I7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_ICAP1_I7", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX35_12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TMS->CFG_CENTER_LOGIC_OUTS_B15_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN3_TMS", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TDI->CFG_CENTER_LOGIC_OUTS_B12_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_BSCAN1_TDI", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR5->CFG_CENTER_LOGIC_OUTS_B15_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR5", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME12->CFG_CENTER_LOGIC_OUTS_B12_2": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_2", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME12", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP0_O7->CFG_CENTER_LOGIC_OUTS_B23_3": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_3", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP0_O7", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR10->CFG_CENTER_LOGIC_OUTS_B20_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_FRAME_ECC_FAR10", - "is_pseudo": "0" - }, - "CFG_CENTER_MID.CFG_CENTER_ICAP1_O0->CFG_CENTER_LOGIC_OUTS_B23_11": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_11", - "is_directional": "1", - "src_wire": "CFG_CENTER_ICAP1_O0", - "is_pseudo": "0" - } - }, - "tile_type": "CFG_CENTER_MID" + ] } \ No newline at end of file diff --git a/artix7/tile_type_CFG_CENTER_TOP.json b/artix7/tile_type_CFG_CENTER_TOP.json index 2e30cd4..30f8c05 100644 --- a/artix7/tile_type_CFG_CENTER_TOP.json +++ b/artix7/tile_type_CFG_CENTER_TOP.json @@ -1,2590 +1,2590 @@ { - "wires": [ - "CFG_CENTER_LOGIC_OUTS_B0_0", - "CFG_CENTER_SE4C2_0", - "CFG_CENTER_WW2END2_0", - "CFG_CENTER_IMUX32_4", - "CFG_CENTER_IMUX17_6", - "CFG_CENTER_WW4C0_5", - "CFG_CENTER_EE2A1_6", - "CFG_CENTER_SE4BEG0_2", - "CFG_CENTER_WL1END3_0", - "CFG_CENTER_IMUX2_2", - "CFG_CENTER_WW4END3_7", - "CFG_CENTER_EE4BEG0_1", - "CFG_CENTER_EE2A2_1", - "CFG_CENTER_LOGIC_OUTS_B22_2", - "CFG_CENTER_NW4A3_0", - "CFG_CENTER_WW4END1_3", - "CFG_CENTER_EE2BEG2_2", - "CFG_CENTER_IMUX14_6", - "CFG_CENTER_LH11_4", - "CFG_CENTER_EL1BEG2_8", - "CFG_CENTER_WR1END3_3", - "CFG_CENTER_IMUX3_8", - "CFG_CENTER_WW4B3_9", - "CFG_CENTER_WW4B1_4", - "CFG_CENTER_LOGIC_OUTS_B7_9", - "CFG_CENTER_EE4C0_7", - "CFG_CENTER_EE4B0_3", - "CFG_CENTER_LH1_7", - "CFG_CENTER_SW2A1_2", - "CFG_CENTER_NE2A3_3", - "CFG_CENTER_LH5_0", - "CFG_CENTER_NW4A3_4", - "CFG_CENTER_SW4A0_2", - "CFG_CENTER_FAN2_9", - "CFG_CENTER_LOGIC_OUTS_B19_3", - "CFG_CENTER_NE2A0_7", - "CFG_CENTER_IMUX20_9", - "CFG_CENTER_SW4END3_7", - "CFG_CENTER_WW2END2_9", - "CFG_CENTER_SW4END2_1", - "CFG_CENTER_LOGIC_OUTS_B7_7", - "CFG_CENTER_IMUX17_4", - "CFG_CENTER_SW4END2_6", - "CFG_CENTER_IMUX43_0", - "CFG_CENTER_LH10_3", - "CFG_CENTER_NW4A2_5", - "CFG_CENTER_WR1END2_5", - "CFG_CENTER_EE4A0_8", - "CFG_CENTER_IMUX23_4", - "CFG_CENTER_IMUX7_7", - "CFG_CENTER_IMUX5_9", - "CFG_CENTER_NW2A2_1", - "CFG_CENTER_EE4B2_5", - "CFG_CENTER_NW4END1_0", - "CFG_CENTER_WW2A3_8", - "CFG_CENTER_SW4A0_8", - "CFG_CENTER_NW2A1_9", - "CFG_CENTER_EE4A0_1", - "CFG_CENTER_EL1BEG1_5", - "CFG_CENTER_WW4B1_0", - "CFG_CENTER_EL1BEG0_9", - "CFG_CENTER_EFUSE_USR_EFUSEUSR13", - "CFG_CENTER_LOGIC_OUTS_B6_3", - "CFG_CENTER_EE4BEG1_7", - "CFG_CENTER_BYP1_5", - "CFG_CENTER_SE4C0_4", - "CFG_CENTER_LOGIC_OUTS_B9_6", - "CFG_CENTER_SE4BEG1_7", - "CFG_CENTER_EE2A0_9", - "CFG_CENTER_WW4END2_9", - "CFG_CENTER_IMUX29_2", - "CFG_CENTER_FAN2_7", - "CFG_CENTER_NW4END3_1", - "CFG_CENTER_EE4C2_5", - "CFG_CENTER_WW4C1_4", - "CFG_CENTER_IMUX21_1", - "CFG_CENTER_CTRL0_8", - "CFG_CENTER_EE4A3_4", - "CFG_CENTER_SW4END2_7", - "CFG_CENTER_LOGIC_OUTS_B14_3", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_IMUX9_3", - "CFG_CENTER_NE2A2_3", - "CFG_CENTER_WW4A2_2", - "CFG_CENTER_IMUX38_1", - "CFG_CENTER_LOGIC_OUTS_B21_1", - "CFG_CENTER_ER1BEG0_9", - "CFG_CENTER_IMUX42_4", - "CFG_CENTER_NW4A1_2", - "CFG_CENTER_WW2A0_7", - "CFG_CENTER_NW4END0_9", - "CFG_CENTER_NE2A0_3", - "CFG_CENTER_IMUX45_2", - "CFG_CENTER_ER1BEG2_7", - "CFG_CENTER_NE4BEG3_3", - "CFG_CENTER_IMUX20_2", - "CFG_CENTER_WL1END0_1", - "CFG_CENTER_IMUX11_6", - "CFG_CENTER_IMUX34_5", - "CFG_CENTER_IMUX45_4", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_LH3_2", - "CFG_CENTER_EE4BEG2_4", - "CFG_CENTER_EE4BEG1_8", - "CFG_CENTER_LOGIC_OUTS_B9_3", - "CFG_CENTER_EE2BEG2_3", - "CFG_CENTER_SE4C3_0", - "CFG_CENTER_FAN6_0", - "CFG_CENTER_LOGIC_OUTS_B4_1", - "CFG_CENTER_WW4END1_5", - "CFG_CENTER_IMUX34_8", - "CFG_CENTER_EE4BEG0_8", - "CFG_CENTER_IMUX23_9", - "CFG_CENTER_WW4A0_6", - "CFG_CENTER_IMUX6_2", - "CFG_CENTER_WW4END0_8", - "CFG_CENTER_SW4A2_4", - "CFG_CENTER_EE2BEG3_8", - "CFG_CENTER_WR1END1_3", - "CFG_CENTER_SW4A0_9", - "CFG_CENTER_EE4C0_5", - "CFG_CENTER_SE2A1_7", - "CFG_CENTER_CTRL0_6", - "CFG_CENTER_NW2A1_5", - "CFG_CENTER_LOGIC_OUTS_B10_9", - "CFG_CENTER_WW4B3_5", - "CFG_CENTER_IMUX4_8", - "CFG_CENTER_SW2A0_7", - "CFG_CENTER_ER1BEG3_2", - "CFG_CENTER_LOGIC_OUTS_B23_1", - "CFG_CENTER_IMUX37_6", - "CFG_CENTER_SW4A0_5", - "CFG_CENTER_IMUX4_2", - "CFG_CENTER_LOGIC_OUTS_B19_0", - "CFG_CENTER_EE2BEG0_0", - "CFG_CENTER_LH9_7", - "CFG_CENTER_IMUX37_8", - "CFG_CENTER_IMUX45_7", - "CFG_CENTER_SE2A2_6", - "CFG_CENTER_IMUX45_6", - "CFG_CENTER_NE2A3_1", - "CFG_CENTER_EE2BEG0_5", - "CFG_CENTER_WW4END0_1", - "CFG_CENTER_LH7_5", - "CFG_CENTER_SW2A0_0", - "CFG_CENTER_LOGIC_OUTS_B7_4", - "CFG_CENTER_LOGIC_OUTS_B9_5", - "CFG_CENTER_EE4B3_7", - "CFG_CENTER_SW4END0_4", - "CFG_CENTER_BYP6_0", - "CFG_CENTER_CLK1_6", - "CFG_CENTER_IMUX42_3", - "CFG_CENTER_WW4C0_0", - "CFG_CENTER_WL1END2_4", - "CFG_CENTER_WW4B2_2", - "CFG_CENTER_EE4A1_8", - "CFG_CENTER_IMUX30_6", - "CFG_CENTER_IMUX47_5", - "CFG_CENTER_EE4A1_6", - "CFG_CENTER_SE2A3_7", - "CFG_CENTER_EE4C3_8", - "CFG_CENTER_IMUX20_0", - "CFG_CENTER_SW2A0_1", - "CFG_CENTER_LOGIC_OUTS_B13_7", - "CFG_CENTER_LOGIC_OUTS_B10_6", - "CFG_CENTER_ER1BEG1_3", - "CFG_CENTER_IMUX20_5", - "CFG_CENTER_BYP2_1", - "CFG_CENTER_EE2BEG3_4", - "CFG_CENTER_IMUX19_6", - "CFG_CENTER_EL1BEG3_0", - "CFG_CENTER_LOGIC_OUTS_B7_1", - "CFG_CENTER_LOGIC_OUTS_B22_8", - "CFG_CENTER_IMUX18_1", - "CFG_CENTER_LH4_8", - "CFG_CENTER_SW4END3_3", - "CFG_CENTER_EE4A1_0", - "CFG_CENTER_IMUX32_9", - "CFG_CENTER_NE4BEG3_8", - "CFG_CENTER_LOGIC_OUTS_B14_9", - "CFG_CENTER_NW4A0_9", - "CFG_CENTER_BYP2_6", - "CFG_CENTER_IMUX6_4", - "CFG_CENTER_SW2A0_5", - "CFG_CENTER_LH1_1", - "CFG_CENTER_LOGIC_OUTS_B10_7", - "CFG_CENTER_IMUX24_2", - "CFG_CENTER_SW4A2_7", - "CFG_CENTER_LOGIC_OUTS_B12_7", - "CFG_CENTER_IMUX37_3", - "CFG_CENTER_NW2A3_0", - "CFG_CENTER_LH6_0", - "CFG_CENTER_EE4A3_9", - "CFG_CENTER_SE2A1_9", - "CFG_CENTER_EE4B1_0", - "CFG_CENTER_LOGIC_OUTS_B4_3", - "CFG_CENTER_WW4END2_4", - "CFG_CENTER_IMUX47_1", - "CFG_CENTER_NE4BEG2_7", - "CFG_CENTER_WW2END1_5", - "CFG_CENTER_BYP2_7", - "CFG_CENTER_LH7_4", - "CFG_CENTER_SW4A2_5", - "CFG_CENTER_BYP5_7", - "CFG_CENTER_LOGIC_OUTS_B15_5", - "CFG_CENTER_WW4A0_7", - "CFG_CENTER_SW4END1_7", - "CFG_CENTER_WW4C2_6", - "CFG_CENTER_LOGIC_OUTS_B1_7", - "CFG_CENTER_BYP5_1", - "CFG_CENTER_NE2A2_4", - "CFG_CENTER_FAN1_6", - "CFG_CENTER_LOGIC_OUTS_B18_8", - "CFG_CENTER_IMUX4_9", - "CFG_CENTER_WW2A0_5", - "CFG_CENTER_IMUX16_0", - "CFG_CENTER_IMUX32_7", - "CFG_CENTER_SW4END3_5", - "CFG_CENTER_WW4A1_0", - "CFG_CENTER_SE4BEG1_3", - "CFG_CENTER_WW4A2_0", - "CFG_CENTER_WW2A0_0", - "CFG_CENTER_FAN4_2", - "CFG_CENTER_WW4B2_3", - "CFG_CENTER_IMUX38_8", - "CFG_CENTER_IMUX19_1", - "CFG_CENTER_WW2END1_7", - "CFG_CENTER_IMUX34_7", - "CFG_CENTER_LH4_2", - "CFG_CENTER_IMUX33_9", - "CFG_CENTER_BYP7_4", - "CFG_CENTER_IMUX47_0", - "CFG_CENTER_LH1_3", - "CFG_CENTER_FAN0_8", - "CFG_CENTER_NE2A1_2", - "CFG_CENTER_IMUX14_4", - "CFG_CENTER_WW2END2_3", - "CFG_CENTER_WW2A2_1", - "CFG_CENTER_EE4B3_1", - "CFG_CENTER_EE4B0_6", - "CFG_CENTER_LOGIC_OUTS_B10_0", - "CFG_CENTER_IMUX39_5", - "CFG_CENTER_SW4END0_7", - "CFG_CENTER_BYP3_4", - "CFG_CENTER_EE4A1_4", - "CFG_CENTER_LOGIC_OUTS_B18_1", - "CFG_CENTER_EE4C0_9", - "CFG_CENTER_EE4BEG3_9", - "CFG_CENTER_LH3_0", - "CFG_CENTER_EE4B2_6", - "CFG_CENTER_IMUX17_3", - "CFG_CENTER_EE4BEG2_1", - "CFG_CENTER_FAN5_7", - "CFG_CENTER_EE4BEG1_5", - "CFG_CENTER_NE4BEG3_1", - "CFG_CENTER_WW2END0_8", - "CFG_CENTER_SE4BEG2_3", - "CFG_CENTER_WW4A0_1", - "CFG_CENTER_LH9_0", - "CFG_CENTER_LOGIC_OUTS_B8_7", - "CFG_CENTER_FAN1_7", - "CFG_CENTER_LH6_2", - "CFG_CENTER_BYP0_9", - "CFG_CENTER_NW4END0_0", - "CFG_CENTER_WW2END1_8", - "CFG_CENTER_IMUX41_2", - "CFG_CENTER_IMUX20_3", - "CFG_CENTER_EE2BEG2_8", - "CFG_CENTER_EE4BEG1_4", - "CFG_CENTER_BYP1_1", - "CFG_CENTER_SE4C1_7", - "CFG_CENTER_LOGIC_OUTS_B8_9", - "CFG_CENTER_EE2A0_2", - "CFG_CENTER_SE2A2_3", - "CFG_CENTER_WL1END2_1", - "CFG_CENTER_EE2A1_4", - "CFG_CENTER_WW2A3_7", - "CFG_CENTER_LOGIC_OUTS_B17_8", - "CFG_CENTER_EE4A0_5", - "CFG_CENTER_EL1BEG1_2", - "CFG_CENTER_FAN1_5", - "CFG_CENTER_LOGIC_OUTS_B12_3", - "CFG_CENTER_NW2A2_8", - "CFG_CENTER_LOGIC_OUTS_B13_3", - "CFG_CENTER_SE2A0_4", - "CFG_CENTER_WW2A1_4", - "CFG_CENTER_EE4C3_3", - "CFG_CENTER_LOGIC_OUTS_B16_8", - "CFG_CENTER_WW4A1_1", - "CFG_CENTER_EE2BEG0_4", - "CFG_CENTER_SE4C3_4", - "CFG_CENTER_IMUX14_0", - "CFG_CENTER_NE4C3_6", - "CFG_CENTER_EE4A0_0", - "CFG_CENTER_WR1END3_5", - "CFG_CENTER_FAN7_6", - "CFG_CENTER_EE4B2_8", - "CFG_CENTER_WW2END3_0", - "CFG_CENTER_LOGIC_OUTS_B0_6", - "CFG_CENTER_LOGIC_OUTS_B11_2", - "CFG_CENTER_EL1BEG1_6", - "CFG_CENTER_IMUX5_3", - "CFG_CENTER_NE2A3_7", - "CFG_CENTER_IMUX40_5", - "CFG_CENTER_EE2A3_7", - "CFG_CENTER_IMUX37_0", - "CFG_CENTER_WR1END3_6", - "CFG_CENTER_IMUX35_4", - "CFG_CENTER_IMUX18_7", - "CFG_CENTER_LOGIC_OUTS_B0_3", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_IMUX17_0", - "CFG_CENTER_IMUX38_0", - "CFG_CENTER_NW4END0_4", - "CFG_CENTER_LOGIC_OUTS_B12_1", - "CFG_CENTER_LOGIC_OUTS_B6_6", - "CFG_CENTER_WW4C2_5", - "CFG_CENTER_EE2BEG1_4", - "CFG_CENTER_LOGIC_OUTS_B20_5", - "CFG_CENTER_WW4B3_7", - "CFG_CENTER_SW4END3_0", - "CFG_CENTER_LH3_7", - "CFG_CENTER_IMUX24_6", - "CFG_CENTER_LOGIC_OUTS_B5_5", - "CFG_CENTER_WW4END2_1", - "CFG_CENTER_WW4B1_1", - "CFG_CENTER_LOGIC_OUTS_B18_7", - "CFG_CENTER_CTRL0_2", - "CFG_CENTER_SE2A3_4", - "CFG_CENTER_IMUX39_2", - "CFG_CENTER_NE2A0_4", - "CFG_CENTER_LOGIC_OUTS_B16_1", - "CFG_CENTER_CTRL1_6", - "CFG_CENTER_EE4C3_4", - "CFG_CENTER_WW4C1_9", - "CFG_CENTER_WR1END1_6", - "CFG_CENTER_EE4B2_1", - "CFG_CENTER_BLOCK_OUTS_B2_1", - "CFG_CENTER_IMUX31_0", - "CFG_CENTER_LH1_8", - "CFG_CENTER_NE4BEG3_9", - "CFG_CENTER_IMUX37_7", - "CFG_CENTER_LOGIC_OUTS_B1_3", - "CFG_CENTER_SE4C3_9", - "CFG_CENTER_LOGIC_OUTS_B0_2", - "CFG_CENTER_WW2END2_4", - "CFG_CENTER_IMUX42_6", - "CFG_CENTER_LH2_3", - "CFG_CENTER_WW4C0_7", - "CFG_CENTER_IMUX47_4", - "CFG_CENTER_BLOCK_OUTS_B2_3", - "CFG_CENTER_CLK0_1", - "CFG_CENTER_IMUX31_9", - "CFG_CENTER_IMUX29_4", - "CFG_CENTER_BYP1_8", - "CFG_CENTER_NE4BEG0_1", - "CFG_CENTER_LOGIC_OUTS_B3_4", - "CFG_CENTER_SE2A3_8", - "CFG_CENTER_NE4BEG2_0", - "CFG_CENTER_NW2A2_7", - "CFG_CENTER_FAN6_7", - "CFG_CENTER_IMUX27_5", - "CFG_CENTER_IMUX22_6", - "CFG_CENTER_IMUX28_8", - "CFG_CENTER_EE2A2_6", - "CFG_CENTER_FAN6_4", - "CFG_CENTER_SW4END0_9", - "CFG_CENTER_SE4BEG1_6", - "CFG_CENTER_IMUX26_7", - "CFG_CENTER_IMUX8_9", - "CFG_CENTER_WW4B0_9", - "CFG_CENTER_LOGIC_OUTS_B3_6", - "CFG_CENTER_EE2BEG1_8", - "CFG_CENTER_EE4A2_2", - "CFG_CENTER_IMUX2_0", - "CFG_CENTER_IMUX11_9", - "CFG_CENTER_BYP6_9", - "CFG_CENTER_SE2A3_5", - "CFG_CENTER_BYP0_0", - "CFG_CENTER_IMUX46_1", - "CFG_CENTER_ER1BEG2_5", - "CFG_CENTER_NE2A3_8", - "CFG_CENTER_LOGIC_OUTS_B3_0", - "CFG_CENTER_FAN5_5", - "CFG_CENTER_WW2END1_1", - "CFG_CENTER_IMUX0_4", - "CFG_CENTER_IMUX28_3", - "CFG_CENTER_SE2A3_3", - "CFG_CENTER_WL1END3_8", - "CFG_CENTER_BLOCK_OUTS_B1_9", - "CFG_CENTER_EE4C1_0", - "CFG_CENTER_WL1END3_4", - "CFG_CENTER_NW2A0_0", - "CFG_CENTER_WL1END2_0", - "CFG_CENTER_SE4C0_9", - "CFG_CENTER_LOGIC_OUTS_B5_6", - "CFG_CENTER_FAN5_4", - "CFG_CENTER_SW2A2_9", - "CFG_CENTER_BYP6_1", - "CFG_CENTER_WL1END3_5", - "CFG_CENTER_BLOCK_OUTS_B3_7", - "CFG_CENTER_EE4B1_8", - "CFG_CENTER_EE2BEG0_3", - "CFG_CENTER_EE4BEG2_2", - "CFG_CENTER_LOGIC_OUTS_B22_3", - "CFG_CENTER_LOGIC_OUTS_B16_2", - "CFG_CENTER_WL1END0_5", - "CFG_CENTER_NE4C3_9", - "CFG_CENTER_SE4C1_9", - "CFG_CENTER_IMUX30_5", - "CFG_CENTER_LOGIC_OUTS_B0_1", - "CFG_CENTER_LH5_8", - "CFG_CENTER_BYP1_0", - "CFG_CENTER_NE4BEG2_9", - "CFG_CENTER_SW4END1_3", - "CFG_CENTER_BYP6_7", - "CFG_CENTER_IMUX13_3", - "CFG_CENTER_LOGIC_OUTS_B17_5", - "CFG_CENTER_WW4END3_3", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_NE4BEG1_0", - "CFG_CENTER_EE2A1_0", - "CFG_CENTER_LH10_6", - "CFG_CENTER_LOGIC_OUTS_B13_9", - "CFG_CENTER_WW4END2_7", - "CFG_CENTER_WW4END1_0", - "CFG_CENTER_IMUX38_9", - "CFG_CENTER_WW4B3_4", - "CFG_CENTER_IMUX5_8", - "CFG_CENTER_WW4C3_1", - "CFG_CENTER_EE4B0_0", - "CFG_CENTER_EE4B3_3", - "CFG_CENTER_LH9_5", - "CFG_CENTER_IMUX38_6", - "CFG_CENTER_IMUX23_1", - "CFG_CENTER_FAN5_1", - "CFG_CENTER_IMUX9_0", - "CFG_CENTER_WW2A1_2", - "CFG_CENTER_IMUX30_4", - "CFG_CENTER_NW4END0_8", - "CFG_CENTER_SW4A2_9", - "CFG_CENTER_LOGIC_OUTS_B21_7", - "CFG_CENTER_WW4C1_6", - "CFG_CENTER_IMUX1_5", - "CFG_CENTER_IMUX7_0", - "CFG_CENTER_BYP3_3", - "CFG_CENTER_SE4BEG2_6", - "CFG_CENTER_IMUX6_7", - "CFG_CENTER_IMUX32_2", - "CFG_CENTER_EE2A2_7", - "CFG_CENTER_LOGIC_OUTS_B12_0", - "CFG_CENTER_IMUX14_9", - "CFG_CENTER_SW4A3_4", - "CFG_CENTER_IMUX33_4", - "CFG_CENTER_BYP7_6", - "CFG_CENTER_IMUX24_5", - "CFG_CENTER_FAN0_6", - "CFG_CENTER_IMUX24_4", - "CFG_CENTER_WL1END0_6", - "CFG_CENTER_EE4A1_7", - "CFG_CENTER_IMUX42_0", - "CFG_CENTER_LOGIC_OUTS_B3_1", - "CFG_CENTER_WL1END1_7", - "CFG_CENTER_LH10_5", - "CFG_CENTER_EE4BEG2_0", - "CFG_CENTER_WR1END0_2", - "CFG_CENTER_FAN1_3", - "CFG_CENTER_LOGIC_OUTS_B22_6", - "CFG_CENTER_WW2END0_1", - "CFG_CENTER_BYP5_3", - "CFG_CENTER_WW2A2_0", - "CFG_CENTER_LOGIC_OUTS_B21_3", - "CFG_CENTER_LOGIC_OUTS_B11_5", - "CFG_CENTER_IMUX34_9", - "CFG_CENTER_FAN3_9", - "CFG_CENTER_WL1END2_7", - "CFG_CENTER_NE4BEG1_2", - "CFG_CENTER_LOGIC_OUTS_B18_0", - "CFG_CENTER_IMUX18_2", - "CFG_CENTER_EE4B0_2", - "CFG_CENTER_IMUX6_9", - "CFG_CENTER_IMUX30_9", - "CFG_CENTER_SW4A3_1", - "CFG_CENTER_EE4A0_3", - "CFG_CENTER_BYP0_2", - "CFG_CENTER_SW4A2_6", - "CFG_CENTER_NE4C0_8", - "CFG_CENTER_BYP3_0", - "CFG_CENTER_LOGIC_OUTS_B2_4", - "CFG_CENTER_SW4END0_2", - "CFG_CENTER_LOGIC_OUTS_B12_5", - "CFG_CENTER_LH8_0", - "CFG_CENTER_IMUX22_9", - "CFG_CENTER_LH12_5", - "CFG_CENTER_SE4BEG3_7", - "CFG_CENTER_IMUX18_5", - "CFG_CENTER_IMUX20_6", - "CFG_CENTER_NE4BEG0_4", - "CFG_CENTER_FAN2_1", - "CFG_CENTER_WW4A2_4", - "CFG_CENTER_SE4BEG2_9", - "CFG_CENTER_LOGIC_OUTS_B23_9", - "CFG_CENTER_LH5_9", - "CFG_CENTER_EFUSE_USR_EFUSEUSR9", - "CFG_CENTER_ER1BEG0_6", - "CFG_CENTER_SE4C2_1", - "CFG_CENTER_EE4B3_8", - "CFG_CENTER_LOGIC_OUTS_B9_1", - "CFG_CENTER_NW2A0_9", - "CFG_CENTER_NE4C2_9", - "CFG_CENTER_IMUX11_8", - "CFG_CENTER_BYP0_3", - "CFG_CENTER_BYP3_8", - "CFG_CENTER_EFUSE_USR_EFUSEUSR23", - "CFG_CENTER_IMUX3_1", - "CFG_CENTER_LOGIC_OUTS_B15_9", - "CFG_CENTER_WW4END2_3", - "CFG_CENTER_NE2A3_5", - "CFG_CENTER_IMUX28_7", - "CFG_CENTER_WW2END0_9", - "CFG_CENTER_NE4BEG1_9", - "CFG_CENTER_WW4B3_2", - "CFG_CENTER_NE4C2_2", - "CFG_CENTER_LH4_7", - "CFG_CENTER_SW4END1_8", - "CFG_CENTER_WL1END3_2", - "CFG_CENTER_IMUX13_9", - "CFG_CENTER_EFUSE_USR_EFUSEUSR4", - "CFG_CENTER_LH6_4", - "CFG_CENTER_LH10_2", - "CFG_CENTER_EE4B1_9", - "CFG_CENTER_EE2A0_8", - "CFG_CENTER_WW2A0_6", - "CFG_CENTER_LOGIC_OUTS_B16_4", - "CFG_CENTER_SE4C2_9", - "CFG_CENTER_FAN5_6", - "CFG_CENTER_LOGIC_OUTS_B5_1", - "CFG_CENTER_SE4C0_2", - "CFG_CENTER_WW4A3_3", - "CFG_CENTER_BLOCK_OUTS_B0_6", - "CFG_CENTER_EE4B1_5", - "CFG_CENTER_SW2A3_0", - "CFG_CENTER_IMUX5_2", - "CFG_CENTER_EE2A2_8", - "CFG_CENTER_WW4B1_7", - "CFG_CENTER_NE2A2_1", - "CFG_CENTER_EE4A0_2", - "CFG_CENTER_LH12_2", - "CFG_CENTER_IMUX22_1", - "CFG_CENTER_WW4A0_2", - "CFG_CENTER_WW2END2_2", - "CFG_CENTER_SE2A2_7", - "CFG_CENTER_IMUX6_3", - "CFG_CENTER_EE4B3_5", - "CFG_CENTER_IMUX37_2", - "CFG_CENTER_IMUX35_1", - "CFG_CENTER_SW4A2_3", - "CFG_CENTER_NE4BEG2_5", - "CFG_CENTER_IMUX38_4", - "CFG_CENTER_IMUX42_1", - "CFG_CENTER_EE4BEG2_3", - "CFG_CENTER_EE4B0_7", - "CFG_CENTER_IMUX35_9", - "CFG_CENTER_SW4A1_7", - "CFG_CENTER_BYP5_4", - "CFG_CENTER_WW2END3_9", - "CFG_CENTER_WW4B1_2", - "CFG_CENTER_EE2BEG3_9", - "CFG_CENTER_CLK1_5", - "CFG_CENTER_IMUX24_7", - "CFG_CENTER_EE4C0_6", - "CFG_CENTER_IMUX31_7", - "CFG_CENTER_LOGIC_OUTS_B17_7", - "CFG_CENTER_EE2BEG0_9", - "CFG_CENTER_IMUX43_1", - "CFG_CENTER_EE4C0_4", - "CFG_CENTER_ER1BEG0_0", - "CFG_CENTER_WW4END2_6", - "CFG_CENTER_WW2END2_1", - "CFG_CENTER_SW2A2_6", - "CFG_CENTER_NW4END0_6", - "CFG_CENTER_EE2BEG2_7", - "CFG_CENTER_NE4C3_8", - "CFG_CENTER_WW2A1_6", - "CFG_CENTER_SW2A3_8", - "CFG_CENTER_LOGIC_OUTS_B20_6", - "CFG_CENTER_WW4A2_3", - "CFG_CENTER_IMUX15_4", - "CFG_CENTER_WL1END0_3", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_SW4END0_6", - "CFG_CENTER_SE4BEG0_4", - "CFG_CENTER_IMUX7_8", - "CFG_CENTER_ER1BEG2_1", - "CFG_CENTER_CLK0_5", - "CFG_CENTER_EE4C1_1", - "CFG_CENTER_BLOCK_OUTS_B3_8", - "CFG_CENTER_NW2A0_7", - "CFG_CENTER_IMUX15_3", - "CFG_CENTER_LOGIC_OUTS_B17_4", - "CFG_CENTER_LH3_5", - "CFG_CENTER_WW4A3_8", - "CFG_CENTER_WW2END3_5", - "CFG_CENTER_IMUX14_3", - "CFG_CENTER_EE2BEG1_7", - "CFG_CENTER_IMUX38_5", - "CFG_CENTER_LH7_7", - "CFG_CENTER_WW4A2_8", - "CFG_CENTER_NW2A0_2", - "CFG_CENTER_SE2A1_8", - "CFG_CENTER_LOGIC_OUTS_B12_8", - "CFG_CENTER_FAN3_7", - "CFG_CENTER_NE4BEG1_4", - "CFG_CENTER_FAN7_9", - "CFG_CENTER_LOGIC_OUTS_B7_2", - "CFG_CENTER_SW4A0_7", - "CFG_CENTER_WW2END3_6", - "CFG_CENTER_LOGIC_OUTS_B14_5", - "CFG_CENTER_EE4BEG3_1", - "CFG_CENTER_EL1BEG1_4", - "CFG_CENTER_IMUX25_2", - "CFG_CENTER_LOGIC_OUTS_B1_9", - "CFG_CENTER_WW4C3_5", - "CFG_CENTER_IMUX15_2", - "CFG_CENTER_LOGIC_OUTS_B3_8", - "CFG_CENTER_BYP1_2", - "CFG_CENTER_NE4C3_4", - "CFG_CENTER_CLK1_4", - "CFG_CENTER_IMUX15_9", - "CFG_CENTER_IMUX33_0", - "CFG_CENTER_NW4A1_8", - "CFG_CENTER_BYP7_3", - "CFG_CENTER_WW2A0_1", - "CFG_CENTER_EE4A3_7", - "CFG_CENTER_LOGIC_OUTS_B9_0", - "CFG_CENTER_SE4C2_4", - "CFG_CENTER_WW2A2_7", - "CFG_CENTER_SW2A1_9", - "CFG_CENTER_WL1END1_0", - "CFG_CENTER_IMUX7_4", - "CFG_CENTER_SW4END3_4", - "CFG_CENTER_LOGIC_OUTS_B15_7", - "CFG_CENTER_IMUX1_8", - "CFG_CENTER_LOGIC_OUTS_B16_6", - "CFG_CENTER_NE4C3_0", - "CFG_CENTER_LOGIC_OUTS_B2_1", - "CFG_CENTER_BLOCK_OUTS_B2_5", - "CFG_CENTER_WR1END0_5", - "CFG_CENTER_IMUX7_5", - "CFG_CENTER_SW2A2_0", - "CFG_CENTER_EE4C3_5", - "CFG_CENTER_LOGIC_OUTS_B11_7", - "CFG_CENTER_WW4C2_2", - "CFG_CENTER_BYP0_1", - "CFG_CENTER_CLK0_9", - "CFG_CENTER_EE2BEG0_7", - "CFG_CENTER_IMUX10_4", - "CFG_CENTER_IMUX14_5", - "CFG_CENTER_IMUX30_7", - "CFG_CENTER_IMUX23_7", - "CFG_CENTER_IMUX0_3", - "CFG_CENTER_IMUX36_0", - "CFG_CENTER_SE4BEG1_4", - "CFG_CENTER_EE4B0_5", - "CFG_CENTER_IMUX16_8", - "CFG_CENTER_EE4A3_5", - "CFG_CENTER_LH7_0", - "CFG_CENTER_IMUX2_4", - "CFG_CENTER_IMUX27_7", - "CFG_CENTER_LOGIC_OUTS_B5_4", - "CFG_CENTER_IMUX1_0", - "CFG_CENTER_IMUX26_0", - "CFG_CENTER_IMUX19_2", - "CFG_CENTER_NW4A2_3", - "CFG_CENTER_IMUX12_8", - "CFG_CENTER_IMUX41_0", - "CFG_CENTER_SE4C0_1", - "CFG_CENTER_BYP5_6", - "CFG_CENTER_EE4C2_3", - "CFG_CENTER_SW2A2_8", - "CFG_CENTER_EE2BEG2_0", - "CFG_CENTER_EFUSE_USR_EFUSEUSR12", - "CFG_CENTER_EE2A1_9", - "CFG_CENTER_IMUX1_2", - "CFG_CENTER_WR1END3_9", - "CFG_CENTER_EFUSE_USR_EFUSEUSR22", - "CFG_CENTER_EE2A1_2", - "CFG_CENTER_NW4A0_8", - "CFG_CENTER_ER1BEG3_9", - "CFG_CENTER_IMUX3_7", - "CFG_CENTER_IMUX23_2", - "CFG_CENTER_IMUX22_2", - "CFG_CENTER_IMUX45_9", - "CFG_CENTER_BYP3_1", - "CFG_CENTER_WW4END3_0", - "CFG_CENTER_WL1END2_2", - "CFG_CENTER_BLOCK_OUTS_B3_0", - "CFG_CENTER_WW2A3_9", - "CFG_CENTER_LH8_7", - "CFG_CENTER_LH6_1", - "CFG_CENTER_LOGIC_OUTS_B5_3", - "CFG_CENTER_EL1BEG2_4", - "CFG_CENTER_IMUX29_7", - "CFG_CENTER_NE2A1_4", - "CFG_CENTER_LH10_1", - "CFG_CENTER_IMUX2_1", - "CFG_CENTER_IMUX15_1", - "CFG_CENTER_SE4C1_6", - "CFG_CENTER_WW4END0_7", - "CFG_CENTER_WW2A3_4", - "CFG_CENTER_BYP6_5", - "CFG_CENTER_LH11_2", - "CFG_CENTER_LOGIC_OUTS_B14_7", - "CFG_CENTER_IMUX28_0", - "CFG_CENTER_EE4B2_3", - "CFG_CENTER_NE4C1_2", - "CFG_CENTER_SW2A0_9", - "CFG_CENTER_IMUX13_2", - "CFG_CENTER_FAN5_2", - "CFG_CENTER_IMUX12_5", - "CFG_CENTER_LH4_0", - "CFG_CENTER_IMUX40_9", - "CFG_CENTER_EE2A3_0", - "CFG_CENTER_EE4BEG3_7", - "CFG_CENTER_WW4C0_6", - "CFG_CENTER_EL1BEG1_3", - "CFG_CENTER_WW4C0_1", - "CFG_CENTER_BLOCK_OUTS_B1_0", - "CFG_CENTER_IMUX34_0", - "CFG_CENTER_SW4A3_8", - "CFG_CENTER_IMUX38_2", - "CFG_CENTER_IMUX7_1", - "CFG_CENTER_NE2A1_9", - "CFG_CENTER_NE4C0_6", - "CFG_CENTER_NW4END1_5", - "CFG_CENTER_EE4BEG3_5", - "CFG_CENTER_EFUSE_USR_EFUSEUSR19", - "CFG_CENTER_LOGIC_OUTS_B22_4", - "CFG_CENTER_WR1END2_4", - "CFG_CENTER_IMUX42_7", - "CFG_CENTER_IMUX16_6", - "CFG_CENTER_IMUX24_0", - "CFG_CENTER_WL1END0_8", - "CFG_CENTER_EE2BEG1_0", - "CFG_CENTER_IMUX44_4", - "CFG_CENTER_SW2A2_5", - "CFG_CENTER_WL1END2_8", - "CFG_CENTER_EL1BEG2_6", - "CFG_CENTER_LH8_5", - "CFG_CENTER_IMUX8_1", - "CFG_CENTER_EL1BEG2_9", - "CFG_CENTER_NE4BEG0_0", - "CFG_CENTER_SE2A0_1", - "CFG_CENTER_CLK1_8", - "CFG_CENTER_WW2END2_7", - "CFG_CENTER_IMUX31_6", - "CFG_CENTER_SE4BEG0_3", - "CFG_CENTER_NW4A0_4", - "CFG_CENTER_LOGIC_OUTS_B14_0", - "CFG_CENTER_ER1BEG0_5", - "CFG_CENTER_IMUX1_9", - "CFG_CENTER_LOGIC_OUTS_B8_5", - "CFG_CENTER_NE4BEG0_8", - "CFG_CENTER_LH7_6", - "CFG_CENTER_LH10_8", - "CFG_CENTER_LH8_2", - "CFG_CENTER_WW4C3_9", - "CFG_CENTER_WW2END2_6", - "CFG_CENTER_WR1END0_6", - "CFG_CENTER_SW4A3_6", - "CFG_CENTER_NW4END2_5", - "CFG_CENTER_EE2BEG3_0", - "CFG_CENTER_LOGIC_OUTS_B23_4", - "CFG_CENTER_WL1END3_3", - "CFG_CENTER_EE4C1_4", - "CFG_CENTER_WW2END0_7", - "CFG_CENTER_WW2A1_7", - "CFG_CENTER_EFUSE_USR_EFUSEUSR31", - "CFG_CENTER_CTRL0_9", - "CFG_CENTER_SE4C3_1", - "CFG_CENTER_IMUX36_2", - "CFG_CENTER_NW2A2_2", - "CFG_CENTER_SW4END1_0", - "CFG_CENTER_IMUX20_4", - "CFG_CENTER_LOGIC_OUTS_B20_8", - "CFG_CENTER_IMUX15_0", - "CFG_CENTER_LOGIC_OUTS_B13_4", - "CFG_CENTER_IMUX27_8", - "CFG_CENTER_EL1BEG0_4", - "CFG_CENTER_IMUX14_7", - "CFG_CENTER_CLK0_8", - "CFG_CENTER_EFUSE_USR_EFUSEUSR30", - "CFG_CENTER_SE4BEG0_9", - "CFG_CENTER_FAN5_8", - "CFG_CENTER_BLOCK_OUTS_B3_4", - "CFG_CENTER_EE4C3_0", - "CFG_CENTER_LOGIC_OUTS_B17_9", - "CFG_CENTER_LOGIC_OUTS_B7_0", - "CFG_CENTER_BYP0_6", - "CFG_CENTER_NE4C0_9", - "CFG_CENTER_NW2A0_1", - "CFG_CENTER_LH6_8", - "CFG_CENTER_NE4C1_3", - "CFG_CENTER_DNA_PORT_SHIFT", - "CFG_CENTER_BYP2_4", - "CFG_CENTER_NE2A3_6", - "CFG_CENTER_SE4C1_0", - "CFG_CENTER_NE4C1_6", - "CFG_CENTER_LH6_6", - "CFG_CENTER_SE4BEG0_6", - "CFG_CENTER_LOGIC_OUTS_B10_8", - "CFG_CENTER_CLK1_2", - "CFG_CENTER_IMUX33_8", - "CFG_CENTER_NE4BEG2_6", - "CFG_CENTER_IMUX30_3", - "CFG_CENTER_IMUX28_2", - "CFG_CENTER_EFUSE_USR_EFUSEUSR10", - "CFG_CENTER_NW4A2_6", - "CFG_CENTER_EL1BEG2_1", - "CFG_CENTER_WL1END2_3", - "CFG_CENTER_IMUX19_8", - "CFG_CENTER_NE4C1_4", - "CFG_CENTER_LH5_2", - "CFG_CENTER_WW4END1_9", - "CFG_CENTER_LOGIC_OUTS_B1_6", - "CFG_CENTER_IMUX40_4", - "CFG_CENTER_LOGIC_OUTS_B18_3", - "CFG_CENTER_LOGIC_OUTS_B8_2", - "CFG_CENTER_WW2A2_9", - "CFG_CENTER_IMUX46_7", - "CFG_CENTER_IMUX37_1", - "CFG_CENTER_NW4A2_7", - "CFG_CENTER_IMUX4_4", - "CFG_CENTER_IMUX19_4", - "CFG_CENTER_NE4BEG0_2", - "CFG_CENTER_LOGIC_OUTS_B3_2", - "CFG_CENTER_LOGIC_OUTS_B11_3", - "CFG_CENTER_SE4BEG2_5", - "CFG_CENTER_LH1_5", - "CFG_CENTER_NW2A1_4", - "CFG_CENTER_IMUX42_2", - "CFG_CENTER_SE4BEG2_0", - "CFG_CENTER_WW2A1_9", - "CFG_CENTER_SE4BEG3_8", - "CFG_CENTER_WW4END1_7", - "CFG_CENTER_LH1_4", - "CFG_CENTER_IMUX6_5", - "CFG_CENTER_LOGIC_OUTS_B8_4", - "CFG_CENTER_WW4A2_9", - "CFG_CENTER_LH9_9", - "CFG_CENTER_WW4A3_2", - "CFG_CENTER_IMUX13_0", - "CFG_CENTER_FAN5_9", - "CFG_CENTER_WW4B2_6", - "CFG_CENTER_IMUX25_3", - "CFG_CENTER_SE4BEG3_3", - "CFG_CENTER_IMUX41_5", - "CFG_CENTER_FAN0_7", - "CFG_CENTER_BYP4_3", - "CFG_CENTER_WW4B1_3", - "CFG_CENTER_SW4A1_1", - "CFG_CENTER_FAN0_9", - "CFG_CENTER_IMUX9_5", - "CFG_CENTER_NE4BEG2_2", - "CFG_CENTER_WW4A3_6", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_WW2A3_2", - "CFG_CENTER_LH5_6", - "CFG_CENTER_IMUX23_6", - "CFG_CENTER_IMUX47_9", - "CFG_CENTER_FAN1_8", - "CFG_CENTER_IMUX16_9", - "CFG_CENTER_NW4A2_1", - "CFG_CENTER_BLOCK_OUTS_B0_0", - "CFG_CENTER_EE4BEG1_0", - "CFG_CENTER_LH1_9", - "CFG_CENTER_BYP1_7", - "CFG_CENTER_IMUX41_3", - "CFG_CENTER_WW4C1_8", - "CFG_CENTER_NW4END0_3", - "CFG_CENTER_NW4END1_6", - "CFG_CENTER_LOGIC_OUTS_B11_9", - "CFG_CENTER_IMUX44_3", - "CFG_CENTER_WW4C0_2", - "CFG_CENTER_IMUX13_1", - "CFG_CENTER_BYP0_7", - "CFG_CENTER_SE4C0_5", - "CFG_CENTER_IMUX20_8", - "CFG_CENTER_BYP2_5", - "CFG_CENTER_LOGIC_OUTS_B6_9", - "CFG_CENTER_NE2A3_9", - "CFG_CENTER_IMUX31_5", - "CFG_CENTER_SE4BEG0_8", - "CFG_CENTER_EFUSE_USR_EFUSEUSR2", - "CFG_CENTER_BYP3_2", - "CFG_CENTER_LOGIC_OUTS_B5_8", - "CFG_CENTER_NE4C0_0", - "CFG_CENTER_IMUX46_3", - "CFG_CENTER_LH8_3", - "CFG_CENTER_EE4C1_2", - "CFG_CENTER_LOGIC_OUTS_B16_7", - "CFG_CENTER_FAN2_3", - "CFG_CENTER_EFUSE_USR_EFUSEUSR20", - "CFG_CENTER_NE4C2_1", - "CFG_CENTER_SW4END2_2", - "CFG_CENTER_WR1END1_8", - "CFG_CENTER_EE4C1_9", - "CFG_CENTER_BYP4_6", - "CFG_CENTER_LH11_7", - "CFG_CENTER_EE4BEG1_2", - "CFG_CENTER_IMUX25_7", - "CFG_CENTER_WW2END0_0", - "CFG_CENTER_BYP7_0", - "CFG_CENTER_LOGIC_OUTS_B11_0", - "CFG_CENTER_IMUX11_0", - "CFG_CENTER_SE2A3_6", - "CFG_CENTER_BYP3_9", - "CFG_CENTER_EE4A2_0", - "CFG_CENTER_SE4C3_7", - "CFG_CENTER_EE4A3_3", - "CFG_CENTER_SW4A1_3", - "CFG_CENTER_IMUX42_5", - "CFG_CENTER_LOGIC_OUTS_B12_6", - "CFG_CENTER_LH9_1", - "CFG_CENTER_FAN6_5", - "CFG_CENTER_BYP4_5", - "CFG_CENTER_IMUX39_3", - "CFG_CENTER_WW4B2_4", - "CFG_CENTER_WW2END0_3", - "CFG_CENTER_SE4C3_8", - "CFG_CENTER_IMUX37_4", - "CFG_CENTER_IMUX29_9", - "CFG_CENTER_SW4END0_3", - "CFG_CENTER_EE2A0_3", - "CFG_CENTER_NW2A3_9", - "CFG_CENTER_WL1END1_6", - "CFG_CENTER_IMUX10_0", - "CFG_CENTER_WL1END1_8", - "CFG_CENTER_WW4C1_7", - "CFG_CENTER_LOGIC_OUTS_B14_6", - "CFG_CENTER_LOGIC_OUTS_B13_1", - "CFG_CENTER_IMUX11_5", - "CFG_CENTER_EL1BEG1_8", - "CFG_CENTER_WW2A1_8", - "CFG_CENTER_FAN3_3", - "CFG_CENTER_IMUX22_4", - "CFG_CENTER_IMUX34_4", - "CFG_CENTER_WL1END3_6", - "CFG_CENTER_NW4END1_8", - "CFG_CENTER_EL1BEG2_0", - "CFG_CENTER_SW4A3_5", - "CFG_CENTER_FAN6_8", - "CFG_CENTER_SE4C1_4", - "CFG_CENTER_IMUX43_7", - "CFG_CENTER_WR1END2_3", - "CFG_CENTER_IMUX21_2", - "CFG_CENTER_IMUX26_2", - "CFG_CENTER_BYP1_6", - "CFG_CENTER_NE4BEG0_3", - "CFG_CENTER_FAN2_4", - "CFG_CENTER_LH4_3", - "CFG_CENTER_LH11_8", - "CFG_CENTER_IMUX46_8", - "CFG_CENTER_LOGIC_OUTS_B4_4", - "CFG_CENTER_LH4_4", - "CFG_CENTER_LOGIC_OUTS_B1_5", - "CFG_CENTER_LOGIC_OUTS_B20_4", - "CFG_CENTER_BYP1_3", - "CFG_CENTER_NE4C3_7", - "CFG_CENTER_EE4BEG1_9", - "CFG_CENTER_FAN1_0", - "CFG_CENTER_NW2A1_3", - "CFG_CENTER_SE2A1_0", - "CFG_CENTER_EE4C2_6", - "CFG_CENTER_IMUX17_2", - "CFG_CENTER_BYP4_9", - "CFG_CENTER_IMUX25_4", - "CFG_CENTER_LOGIC_OUTS_B15_6", - "CFG_CENTER_WW2A0_2", - "CFG_CENTER_BLOCK_OUTS_B3_3", - "CFG_CENTER_EE4BEG3_2", - "CFG_CENTER_LH9_8", - "CFG_CENTER_SE4BEG1_5", - "CFG_CENTER_EE4A3_6", - "CFG_CENTER_IMUX18_3", - "CFG_CENTER_EE4BEG3_6", - "CFG_CENTER_WR1END2_8", - "CFG_CENTER_BLOCK_OUTS_B2_2", - "CFG_CENTER_WW4A0_5", - "CFG_CENTER_CTRL1_3", - "CFG_CENTER_SE4BEG1_0", - "CFG_CENTER_LOGIC_OUTS_B17_1", - "CFG_CENTER_FAN0_5", - "CFG_CENTER_FAN4_4", - "CFG_CENTER_WW2END3_7", - "CFG_CENTER_SW2A0_6", - "CFG_CENTER_EE4B0_8", - "CFG_CENTER_WW4C3_8", - "CFG_CENTER_IMUX1_7", - "CFG_CENTER_SE2A1_6", - "CFG_CENTER_BYP5_5", - "CFG_CENTER_BLOCK_OUTS_B1_1", - "CFG_CENTER_BLOCK_OUTS_B1_8", - "CFG_CENTER_EE2A3_6", - "CFG_CENTER_EL1BEG0_5", - "CFG_CENTER_LOGIC_OUTS_B18_5", - "CFG_CENTER_ER1BEG2_6", - "CFG_CENTER_IMUX13_6", - "CFG_CENTER_IMUX31_1", - "CFG_CENTER_EE4A3_0", - "CFG_CENTER_LH11_5", - "CFG_CENTER_EFUSE_USR_EFUSEUSR1", - "CFG_CENTER_SW4END1_6", - "CFG_CENTER_WW4END0_0", - "CFG_CENTER_WW4A3_4", - "CFG_CENTER_IMUX0_8", - "CFG_CENTER_IMUX30_1", - "CFG_CENTER_NW4END0_2", - "CFG_CENTER_WW4C3_3", - "CFG_CENTER_SW2A1_6", - "CFG_CENTER_EE2A0_6", - "CFG_CENTER_WW4C1_5", - "CFG_CENTER_LH8_1", - "CFG_CENTER_SW4A1_8", - "CFG_CENTER_BYP7_7", - "CFG_CENTER_NE4C2_5", - "CFG_CENTER_WW4A1_4", - "CFG_CENTER_SE4BEG3_9", - "CFG_CENTER_IMUX29_6", - "CFG_CENTER_WW2A0_4", - "CFG_CENTER_WR1END1_0", - "CFG_CENTER_FAN2_0", - "CFG_CENTER_EL1BEG2_2", - "CFG_CENTER_NW2A2_9", - "CFG_CENTER_WL1END1_4", - "CFG_CENTER_WR1END2_7", - "CFG_CENTER_IMUX21_6", - "CFG_CENTER_IMUX32_6", - "CFG_CENTER_SE4C2_7", - "CFG_CENTER_LH2_4", - "CFG_CENTER_IMUX5_1", - "CFG_CENTER_LOGIC_OUTS_B23_6", - "CFG_CENTER_EE4B0_4", - "CFG_CENTER_IMUX43_8", - "CFG_CENTER_SW2A3_7", - "CFG_CENTER_ER1BEG2_0", - "CFG_CENTER_NW2A1_0", - "CFG_CENTER_LH9_2", - "CFG_CENTER_ER1BEG0_8", - "CFG_CENTER_CTRL1_2", - "CFG_CENTER_WW4C2_9", - "CFG_CENTER_EE4A2_1", - "CFG_CENTER_FAN2_5", - "CFG_CENTER_BYP2_0", - "CFG_CENTER_FAN7_8", - "CFG_CENTER_LH12_0", - "CFG_CENTER_NW4END3_9", - "CFG_CENTER_EL1BEG1_0", - "CFG_CENTER_SW4END0_0", - "CFG_CENTER_EE4C2_4", - "CFG_CENTER_IMUX45_8", - "CFG_CENTER_EL1BEG3_3", - "CFG_CENTER_IMUX13_7", - "CFG_CENTER_FAN7_5", - "CFG_CENTER_LOGIC_OUTS_B15_0", - "CFG_CENTER_WW4C3_6", - "CFG_CENTER_LOGIC_OUTS_B18_6", - "CFG_CENTER_IMUX36_1", - "CFG_CENTER_NW4END3_3", - "CFG_CENTER_EE2A0_5", - "CFG_CENTER_NE4C3_2", - "CFG_CENTER_WW4C3_7", - "CFG_CENTER_NE4C0_7", - "CFG_CENTER_WW2END0_4", - "CFG_CENTER_BYP4_8", - "CFG_CENTER_BYP3_7", - "CFG_CENTER_IMUX14_1", - "CFG_CENTER_IMUX43_5", - "CFG_CENTER_IMUX21_4", - "CFG_CENTER_EE2A1_5", - "CFG_CENTER_NW4END1_3", - "CFG_CENTER_WR1END1_5", - "CFG_CENTER_EE4BEG0_4", - "CFG_CENTER_SE4BEG3_6", - "CFG_CENTER_IMUX19_0", - "CFG_CENTER_IMUX41_6", - "CFG_CENTER_IMUX16_2", - "CFG_CENTER_EL1BEG1_1", - "CFG_CENTER_LH3_3", - "CFG_CENTER_SE4BEG3_4", - "CFG_CENTER_ER1BEG1_1", - "CFG_CENTER_SE4C0_7", - "CFG_CENTER_BYP2_9", - "CFG_CENTER_BLOCK_OUTS_B3_6", - "CFG_CENTER_EE4C2_8", - "CFG_CENTER_ER1BEG0_4", - "CFG_CENTER_IMUX36_5", - "CFG_CENTER_IMUX35_5", - "CFG_CENTER_IMUX4_7", - "CFG_CENTER_IMUX12_4", - "CFG_CENTER_LOGIC_OUTS_B19_7", - "CFG_CENTER_WW2END3_3", - "CFG_CENTER_WW4B2_8", - "CFG_CENTER_BYP1_4", - "CFG_CENTER_IMUX1_4", - "CFG_CENTER_IMUX39_4", - "CFG_CENTER_WW4B1_5", - "CFG_CENTER_BYP0_5", - "CFG_CENTER_NE2A2_8", - "CFG_CENTER_IMUX42_8", - "CFG_CENTER_LOGIC_OUTS_B20_9", - "CFG_CENTER_NW4END2_9", - "CFG_CENTER_LH3_6", - "CFG_CENTER_NW2A2_6", - "CFG_CENTER_NW2A0_3", - "CFG_CENTER_EFUSE_USR_EFUSEUSR3", - "CFG_CENTER_NW4END2_2", - "CFG_CENTER_IMUX21_9", - "CFG_CENTER_WW4A1_8", - "CFG_CENTER_IMUX3_5", - "CFG_CENTER_WW2END1_6", - "CFG_CENTER_LOGIC_OUTS_B11_1", - "CFG_CENTER_IMUX41_7", - "CFG_CENTER_SE2A0_8", - "CFG_CENTER_FAN3_6", - "CFG_CENTER_LOGIC_OUTS_B16_9", - "CFG_CENTER_LOGIC_OUTS_B8_1", - "CFG_CENTER_EFUSE_USR_EFUSEUSR27", - "CFG_CENTER_IMUX22_8", - "CFG_CENTER_LH6_5", - "CFG_CENTER_FAN3_0", - "CFG_CENTER_BLOCK_OUTS_B0_4", - "CFG_CENTER_EE4A1_5", - "CFG_CENTER_IMUX33_7", - "CFG_CENTER_IMUX0_1", - "CFG_CENTER_IMUX1_6", - "CFG_CENTER_LH9_6", - "CFG_CENTER_NW4END2_1", - "CFG_CENTER_WW2END1_0", - "CFG_CENTER_WW4A2_7", - "CFG_CENTER_LH7_9", - "CFG_CENTER_EE4C2_9", - "CFG_CENTER_SW4END1_2", - "CFG_CENTER_LH11_9", - "CFG_CENTER_FAN3_5", - "CFG_CENTER_SW2A2_2", - "CFG_CENTER_BYP5_2", - "CFG_CENTER_SE4BEG2_2", - "CFG_CENTER_IMUX13_8", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_LOGIC_OUTS_B22_9", - "CFG_CENTER_IMUX47_3", - "CFG_CENTER_IMUX25_8", - "CFG_CENTER_SW4A2_8", - "CFG_CENTER_NW2A1_2", - "CFG_CENTER_SW2A0_2", - "CFG_CENTER_SE2A0_6", - "CFG_CENTER_LOGIC_OUTS_B6_0", - "CFG_CENTER_SW4A0_6", - "CFG_CENTER_IMUX28_9", - "CFG_CENTER_BLOCK_OUTS_B3_1", - "CFG_CENTER_IMUX36_9", - "CFG_CENTER_WW4END3_8", - "CFG_CENTER_LOGIC_OUTS_B0_5", - "CFG_CENTER_LH3_9", - "CFG_CENTER_IMUX32_8", - "CFG_CENTER_IMUX30_8", - "CFG_CENTER_FAN4_1", - "CFG_CENTER_IMUX27_0", - "CFG_CENTER_EFUSE_USR_EFUSEUSR7", - "CFG_CENTER_IMUX16_3", - "CFG_CENTER_SE4C1_2", - "CFG_CENTER_SE2A2_5", - "CFG_CENTER_NE4BEG0_6", - "CFG_CENTER_IMUX5_6", - "CFG_CENTER_IMUX21_3", - "CFG_CENTER_EFUSE_USR_EFUSEUSR6", - "CFG_CENTER_WW4A3_0", - "CFG_CENTER_SE2A2_2", - "CFG_CENTER_FAN4_6", - "CFG_CENTER_WW2A3_5", - "CFG_CENTER_IMUX26_3", - "CFG_CENTER_DNA_PORT_DOUT", - "CFG_CENTER_WW4B2_1", - "CFG_CENTER_EE4B3_2", - "CFG_CENTER_IMUX3_3", - "CFG_CENTER_WL1END1_2", - "CFG_CENTER_WW4A3_5", - "CFG_CENTER_IMUX4_3", - "CFG_CENTER_IMUX30_2", - "CFG_CENTER_NW4A2_2", - "CFG_CENTER_IMUX41_4", - "CFG_CENTER_IMUX8_2", - "CFG_CENTER_BYP5_8", - "CFG_CENTER_IMUX8_3", - "CFG_CENTER_SE2A1_1", - "CFG_CENTER_EE2A1_7", - "CFG_CENTER_IMUX8_7", - "CFG_CENTER_FAN1_4", - "CFG_CENTER_EE2BEG0_1", - "CFG_CENTER_LH8_9", - "CFG_CENTER_EL1BEG0_7", - "CFG_CENTER_FAN0_4", - "CFG_CENTER_SW2A1_7", - "CFG_CENTER_NW2A3_7", - "CFG_CENTER_SE4C0_3", - "CFG_CENTER_EL1BEG0_8", - "CFG_CENTER_NW4A3_7", - "CFG_CENTER_EE2BEG2_6", - "CFG_CENTER_IMUX6_0", - "CFG_CENTER_EE4A1_2", - "CFG_CENTER_IMUX28_6", - "CFG_CENTER_WW2END1_4", - "CFG_CENTER_IMUX39_9", - "CFG_CENTER_LOGIC_OUTS_B20_2", - "CFG_CENTER_LOGIC_OUTS_B9_2", - "CFG_CENTER_LOGIC_OUTS_B19_1", - "CFG_CENTER_IMUX36_8", - "CFG_CENTER_EE2A2_3", - "CFG_CENTER_IMUX15_7", - "CFG_CENTER_SW2A1_4", - "CFG_CENTER_SE4BEG1_9", - "CFG_CENTER_LH6_3", - "CFG_CENTER_SW4A0_4", - "CFG_CENTER_BLOCK_OUTS_B2_8", - "CFG_CENTER_EE4BEG0_0", - "CFG_CENTER_BLOCK_OUTS_B2_6", - "CFG_CENTER_WL1END0_0", - "CFG_CENTER_LH12_3", - "CFG_CENTER_IMUX47_8", - "CFG_CENTER_WW4A3_9", - "CFG_CENTER_IMUX40_1", - "CFG_CENTER_NE2A3_2", - "CFG_CENTER_EE4C0_3", - "CFG_CENTER_IMUX31_3", - "CFG_CENTER_LOGIC_OUTS_B17_0", - "CFG_CENTER_LOGIC_OUTS_B4_7", - "CFG_CENTER_FAN1_1", - "CFG_CENTER_EE2BEG3_1", - "CFG_CENTER_IMUX28_4", - "CFG_CENTER_SW2A3_6", - "CFG_CENTER_SW4A1_0", - "CFG_CENTER_SW4A2_0", - "CFG_CENTER_BYP3_6", - "CFG_CENTER_NE2A1_0", - "CFG_CENTER_LOGIC_OUTS_B20_1", - "CFG_CENTER_NW4A0_1", - "CFG_CENTER_IMUX12_7", - "CFG_CENTER_IMUX32_3", - "CFG_CENTER_NW2A3_3", - "CFG_CENTER_WW2END3_1", - "CFG_CENTER_EE4B3_9", - "CFG_CENTER_ER1BEG3_8", - "CFG_CENTER_LOGIC_OUTS_B18_2", - "CFG_CENTER_WW2A0_9", - "CFG_CENTER_EE4BEG3_3", - "CFG_CENTER_WW4B3_6", - "CFG_CENTER_BYP0_8", - "CFG_CENTER_EE2A1_3", - "CFG_CENTER_CTRL1_4", - "CFG_CENTER_SW4END0_5", - "CFG_CENTER_EE4BEG2_9", - "CFG_CENTER_FAN3_4", - "CFG_CENTER_WW4END3_5", - "CFG_CENTER_BLOCK_OUTS_B0_9", - "CFG_CENTER_EE2A2_4", - "CFG_CENTER_WW4B0_7", - "CFG_CENTER_IMUX16_7", - "CFG_CENTER_SW2A3_5", - "CFG_CENTER_NW4A0_3", - "CFG_CENTER_SE4C1_5", - "CFG_CENTER_WR1END1_7", - "CFG_CENTER_EE4A2_7", - "CFG_CENTER_LOGIC_OUTS_B1_8", - "CFG_CENTER_BYP2_2", - "CFG_CENTER_LH6_7", - "CFG_CENTER_NW4END0_5", - "CFG_CENTER_LOGIC_OUTS_B22_0", - "CFG_CENTER_SE2A1_2", - "CFG_CENTER_LOGIC_OUTS_B13_0", - "CFG_CENTER_NE4BEG2_1", - "CFG_CENTER_IMUX27_1", - "CFG_CENTER_NE4C0_1", - "CFG_CENTER_IMUX29_8", - "CFG_CENTER_SE2A0_2", - "CFG_CENTER_FAN5_3", - "CFG_CENTER_IMUX37_9", - "CFG_CENTER_SW2A0_3", - "CFG_CENTER_SW4A3_0", - "CFG_CENTER_IMUX3_9", - "CFG_CENTER_IMUX25_0", - "CFG_CENTER_ER1BEG0_3", - "CFG_CENTER_IMUX8_6", - "CFG_CENTER_IMUX19_9", - "CFG_CENTER_EE4BEG1_3", - "CFG_CENTER_EE4B1_3", - "CFG_CENTER_EE4A2_6", - "CFG_CENTER_ER1BEG3_3", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_WW4C2_1", - "CFG_CENTER_IMUX24_3", - "CFG_CENTER_WW2END3_4", - "CFG_CENTER_NW4A2_9", - "CFG_CENTER_WW2A2_4", - "CFG_CENTER_EE2BEG3_3", - "CFG_CENTER_WW4B0_4", - "CFG_CENTER_LOGIC_OUTS_B14_1", - "CFG_CENTER_EE2A1_8", - "CFG_CENTER_WW4END0_6", - "CFG_CENTER_WW4B1_8", - "CFG_CENTER_IMUX3_0", - "CFG_CENTER_WR1END0_1", - "CFG_CENTER_BYP2_8", - "CFG_CENTER_ER1BEG1_4", - "CFG_CENTER_SE4BEG0_1", - "CFG_CENTER_EL1BEG3_6", - "CFG_CENTER_LOGIC_OUTS_B23_3", - "CFG_CENTER_SW4A1_9", - "CFG_CENTER_NW4A0_7", - "CFG_CENTER_EE2A0_0", - "CFG_CENTER_WL1END0_4", - "CFG_CENTER_ER1BEG0_2", - "CFG_CENTER_EE4BEG2_7", - "CFG_CENTER_WW4A2_1", - "CFG_CENTER_BLOCK_OUTS_B2_9", - "CFG_CENTER_NE2A2_7", - "CFG_CENTER_EE2BEG0_8", - "CFG_CENTER_LOGIC_OUTS_B17_3", - "CFG_CENTER_LOGIC_OUTS_B17_2", - "CFG_CENTER_NE4C1_0", - "CFG_CENTER_IMUX45_0", - "CFG_CENTER_LOGIC_OUTS_B12_4", - "CFG_CENTER_CLK1_0", - "CFG_CENTER_LH4_5", - "CFG_CENTER_IMUX6_6", - "CFG_CENTER_WR1END2_6", - "CFG_CENTER_IMUX41_9", - "CFG_CENTER_NE2A1_6", - "CFG_CENTER_LOGIC_OUTS_B0_4", - "CFG_CENTER_IMUX17_7", - "CFG_CENTER_WL1END2_9", - "CFG_CENTER_ER1BEG0_7", - "CFG_CENTER_BYP4_4", - "CFG_CENTER_LH10_0", - "CFG_CENTER_NW4A1_9", - "CFG_CENTER_IMUX17_9", - "CFG_CENTER_EE4B1_2", - "CFG_CENTER_EE4BEG1_6", - "CFG_CENTER_IMUX33_1", - "CFG_CENTER_NW4END2_4", - "CFG_CENTER_FAN7_1", - "CFG_CENTER_BLOCK_OUTS_B1_7", - "CFG_CENTER_LH11_1", - "CFG_CENTER_IMUX31_4", - "CFG_CENTER_IMUX0_5", - "CFG_CENTER_LH10_9", - "CFG_CENTER_SE4BEG3_0", - "CFG_CENTER_EE4B1_1", - "CFG_CENTER_LOGIC_OUTS_B2_5", - "CFG_CENTER_SW4END2_4", - "CFG_CENTER_BLOCK_OUTS_B0_5", - "CFG_CENTER_EE2BEG1_2", - "CFG_CENTER_NW4A3_2", - "CFG_CENTER_LOGIC_OUTS_B0_7", - "CFG_CENTER_IMUX44_0", - "CFG_CENTER_WL1END0_9", - "CFG_CENTER_IMUX21_0", - "CFG_CENTER_IMUX36_7", - "CFG_CENTER_LOGIC_OUTS_B1_0", - "CFG_CENTER_IMUX46_5", - "CFG_CENTER_EL1BEG2_7", - "CFG_CENTER_SE2A0_7", - "CFG_CENTER_LH5_3", - "CFG_CENTER_NW4A2_0", - "CFG_CENTER_EFUSE_USR_EFUSEUSR8", - "CFG_CENTER_NE2A2_9", - "CFG_CENTER_IMUX10_6", - "CFG_CENTER_IMUX9_2", - "CFG_CENTER_BYP2_3", - "CFG_CENTER_BYP4_1", - "CFG_CENTER_IMUX40_2", - "CFG_CENTER_WW2A0_3", - "CFG_CENTER_EE4A3_8", - "CFG_CENTER_WW2END1_2", - "CFG_CENTER_IMUX29_3", - "CFG_CENTER_CTRL0_1", - "CFG_CENTER_LOGIC_OUTS_B14_8", - "CFG_CENTER_EE4BEG0_2", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_NE2A1_5", - "CFG_CENTER_CLK1_9", - "CFG_CENTER_CTRL1_9", - "CFG_CENTER_SW4END3_1", - "CFG_CENTER_IMUX29_1", - "CFG_CENTER_LH5_5", - "CFG_CENTER_EE4A2_5", - "CFG_CENTER_LH12_9", - "CFG_CENTER_NW4END3_0", - "CFG_CENTER_IMUX47_7", - "CFG_CENTER_WR1END2_1", - "CFG_CENTER_IMUX7_6", - "CFG_CENTER_LOGIC_OUTS_B9_4", - "CFG_CENTER_LOGIC_OUTS_B0_9", - "CFG_CENTER_WR1END2_9", - "CFG_CENTER_EE2A0_7", - "CFG_CENTER_IMUX3_6", - "CFG_CENTER_IMUX5_7", - "CFG_CENTER_SW4END2_8", - "CFG_CENTER_IMUX23_3", - "CFG_CENTER_LOGIC_OUTS_B16_3", - "CFG_CENTER_LOGIC_OUTS_B21_2", - "CFG_CENTER_IMUX10_8", - "CFG_CENTER_EL1BEG0_6", - "CFG_CENTER_IMUX8_5", - "CFG_CENTER_NE4C3_1", - "CFG_CENTER_IMUX46_4", - "CFG_CENTER_LOGIC_OUTS_B13_8", - "CFG_CENTER_NE2A0_9", - "CFG_CENTER_LOGIC_OUTS_B14_2", - "CFG_CENTER_LOGIC_OUTS_B21_6", - "CFG_CENTER_EE4C1_3", - "CFG_CENTER_NE2A3_4", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_EE4B2_0", - "CFG_CENTER_FAN3_2", - "CFG_CENTER_FAN1_9", - "CFG_CENTER_CLK1_3", - "CFG_CENTER_EE2A1_1", - "CFG_CENTER_NE2A2_2", - "CFG_CENTER_NW4A3_8", - "CFG_CENTER_EE4B0_9", - "CFG_CENTER_LH9_3", - "CFG_CENTER_LOGIC_OUTS_B5_2", - "CFG_CENTER_SW4END3_8", - "CFG_CENTER_NE2A1_7", - "CFG_CENTER_LH12_8", - "CFG_CENTER_WW4C2_8", - "CFG_CENTER_LOGIC_OUTS_B11_8", - "CFG_CENTER_IMUX19_3", - "CFG_CENTER_IMUX11_7", - "CFG_CENTER_IMUX17_8", - "CFG_CENTER_FAN4_8", - "CFG_CENTER_ER1BEG3_6", - "CFG_CENTER_IMUX43_4", - "CFG_CENTER_FAN0_1", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_NE4BEG3_6", - "CFG_CENTER_NW4END3_5", - "CFG_CENTER_EE4C2_2", - "CFG_CENTER_BLOCK_OUTS_B3_5", - "CFG_CENTER_IMUX42_9", - "CFG_CENTER_NW2A1_1", - "CFG_CENTER_WL1END3_9", - "CFG_CENTER_IMUX38_7", - "CFG_CENTER_NE4C2_8", - "CFG_CENTER_IMUX12_0", - "CFG_CENTER_IMUX8_8", - "CFG_CENTER_LOGIC_OUTS_B13_5", - "CFG_CENTER_EE2BEG1_3", - "CFG_CENTER_IMUX3_4", - "CFG_CENTER_LOGIC_OUTS_B2_9", - "CFG_CENTER_WR1END3_7", - "CFG_CENTER_WW4END1_8", - "CFG_CENTER_LOGIC_OUTS_B6_2", - "CFG_CENTER_LOGIC_OUTS_B19_4", - "CFG_CENTER_SE2A2_4", - "CFG_CENTER_CTRL1_7", - "CFG_CENTER_WW4B2_9", - "CFG_CENTER_LOGIC_OUTS_B3_9", - "CFG_CENTER_WR1END1_9", - "CFG_CENTER_WW4B3_1", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_EE2A3_9", - "CFG_CENTER_IMUX26_5", - "CFG_CENTER_EFUSE_USR_EFUSEUSR21", - "CFG_CENTER_BLOCK_OUTS_B3_2", - "CFG_CENTER_IMUX25_9", - "CFG_CENTER_EE4C0_0", - "CFG_CENTER_LOGIC_OUTS_B19_5", - "CFG_CENTER_EFUSE_USR_EFUSEUSR16", - "CFG_CENTER_IMUX15_6", - "CFG_CENTER_EE2BEG2_9", - "CFG_CENTER_NW4A2_4", - "CFG_CENTER_WW2END0_6", - "CFG_CENTER_WL1END1_3", - "CFG_CENTER_EE4B2_9", - "CFG_CENTER_CLK0_4", - "CFG_CENTER_WW4B2_5", - "CFG_CENTER_EE4BEG3_0", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_EE4B2_7", - "CFG_CENTER_EFUSE_USR_EFUSEUSR18", - "CFG_CENTER_EE4B3_0", - "CFG_CENTER_IMUX36_3", - "CFG_CENTER_EE4BEG0_5", - "CFG_CENTER_EE2A3_4", - "CFG_CENTER_NE2A0_5", - "CFG_CENTER_LOGIC_OUTS_B5_0", - "CFG_CENTER_IMUX40_8", - "CFG_CENTER_IMUX46_6", - "CFG_CENTER_EE2BEG3_2", - "CFG_CENTER_SE4C1_1", - "CFG_CENTER_IMUX39_0", - "CFG_CENTER_CLK1_1", - "CFG_CENTER_IMUX35_0", - "CFG_CENTER_SW4A3_3", - "CFG_CENTER_EE4A1_9", - "CFG_CENTER_WW4C2_7", - "CFG_CENTER_WW4B1_6", - "CFG_CENTER_LH10_4", - "CFG_CENTER_LH11_3", - "CFG_CENTER_NE2A2_5", - "CFG_CENTER_SE2A3_9", - "CFG_CENTER_WW2A1_3", - "CFG_CENTER_IMUX34_1", - "CFG_CENTER_LOGIC_OUTS_B18_9", - "CFG_CENTER_NW4A3_5", - "CFG_CENTER_LOGIC_OUTS_B15_4", - "CFG_CENTER_WW4C1_0", - "CFG_CENTER_NW4A0_6", - "CFG_CENTER_LH2_9", - "CFG_CENTER_LOGIC_OUTS_B3_3", - "CFG_CENTER_NW4END1_7", - "CFG_CENTER_BLOCK_OUTS_B0_8", - "CFG_CENTER_NW4END3_7", - "CFG_CENTER_LH7_2", - "CFG_CENTER_NW4END3_2", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_NE4BEG3_5", - "CFG_CENTER_NE2A0_6", - "CFG_CENTER_EE2A3_1", - "CFG_CENTER_CLK0_7", - "CFG_CENTER_LH2_1", - "CFG_CENTER_SW2A1_0", - "CFG_CENTER_SW4A0_1", - "CFG_CENTER_EE2BEG3_7", - "CFG_CENTER_LOGIC_OUTS_B20_0", - "CFG_CENTER_SW2A0_4", - "CFG_CENTER_IMUX44_7", - "CFG_CENTER_IMUX21_7", - "CFG_CENTER_FAN1_2", - "CFG_CENTER_SW4END3_6", - "CFG_CENTER_WR1END3_8", - "CFG_CENTER_SE4BEG2_1", - "CFG_CENTER_BYP7_2", - "CFG_CENTER_IMUX4_0", - "CFG_CENTER_WR1END0_9", - "CFG_CENTER_NW2A2_3", - "CFG_CENTER_LH7_8", - "CFG_CENTER_SE4BEG0_5", - "CFG_CENTER_NE4BEG2_4", - "CFG_CENTER_ER1BEG0_1", - "CFG_CENTER_LH12_6", - "CFG_CENTER_NE4C0_2", - "CFG_CENTER_IMUX36_4", - "CFG_CENTER_SW2A1_5", - "CFG_CENTER_IMUX32_1", - "CFG_CENTER_IMUX40_6", - "CFG_CENTER_EE2A0_1", - "CFG_CENTER_SW2A1_8", - "CFG_CENTER_NW4END2_6", - "CFG_CENTER_WW2A3_3", - "CFG_CENTER_IMUX36_6", - "CFG_CENTER_WW4END1_1", - "CFG_CENTER_IMUX14_8", - "CFG_CENTER_SE4BEG3_2", - "CFG_CENTER_EE4BEG2_6", - "CFG_CENTER_IMUX22_5", - "CFG_CENTER_WW4A0_4", - "CFG_CENTER_EFUSE_USR_EFUSEUSR26", - "CFG_CENTER_WW2END2_5", - "CFG_CENTER_IMUX7_9", - "CFG_CENTER_WW2A2_5", - "CFG_CENTER_EL1BEG0_1", - "CFG_CENTER_IMUX22_3", - "CFG_CENTER_IMUX7_3", - "CFG_CENTER_LOGIC_OUTS_B10_1", - "CFG_CENTER_WW4END3_9", - "CFG_CENTER_CLK1_7", - "CFG_CENTER_LH7_1", - "CFG_CENTER_BLOCK_OUTS_B3_9", - "CFG_CENTER_EE4A1_3", - "CFG_CENTER_EE2BEG3_5", - "CFG_CENTER_IMUX46_0", - "CFG_CENTER_IMUX17_5", - "CFG_CENTER_LOGIC_OUTS_B6_4", - "CFG_CENTER_LH2_5", - "CFG_CENTER_WW4B0_2", - "CFG_CENTER_ER1BEG1_2", - "CFG_CENTER_CTRL0_0", - "CFG_CENTER_IMUX18_4", - "CFG_CENTER_NE4C1_9", - "CFG_CENTER_SW4END1_9", - "CFG_CENTER_IMUX41_8", - "CFG_CENTER_IMUX5_4", - "CFG_CENTER_LH5_7", - "CFG_CENTER_SW4END1_4", - "CFG_CENTER_FAN7_2", - "CFG_CENTER_IMUX13_4", - "CFG_CENTER_NW2A3_2", - "CFG_CENTER_BLOCK_OUTS_B1_2", - "CFG_CENTER_IMUX12_9", - "CFG_CENTER_SW4A1_2", - "CFG_CENTER_WL1END1_5", - "CFG_CENTER_CLK0_6", - "CFG_CENTER_LH8_8", - "CFG_CENTER_IMUX9_7", - "CFG_CENTER_WW2END3_2", - "CFG_CENTER_EE2A3_3", - "CFG_CENTER_IMUX39_7", - "CFG_CENTER_EE4C3_9", - "CFG_CENTER_NW4END1_1", - "CFG_CENTER_EE4C1_7", - "CFG_CENTER_EE4C1_5", - "CFG_CENTER_WW4A1_2", - "CFG_CENTER_SE4BEG1_2", - "CFG_CENTER_WW4B0_5", - "CFG_CENTER_SE4C2_8", - "CFG_CENTER_EE4A2_3", - "CFG_CENTER_WW4B0_1", - "CFG_CENTER_SE4C2_5", - "CFG_CENTER_BYP6_4", - "CFG_CENTER_SE4C2_2", - "CFG_CENTER_BYP4_2", - "CFG_CENTER_LOGIC_OUTS_B21_8", - "CFG_CENTER_FAN6_3", - "CFG_CENTER_NW4A0_5", - "CFG_CENTER_FAN6_9", - "CFG_CENTER_ER1BEG1_0", - "CFG_CENTER_IMUX1_1", - "CFG_CENTER_EE2A3_2", - "CFG_CENTER_CTRL1_1", - "CFG_CENTER_NW4END1_9", - "CFG_CENTER_IMUX2_3", - "CFG_CENTER_BLOCK_OUTS_B2_4", - "CFG_CENTER_EE4A0_6", - "CFG_CENTER_WR1END2_2", - "CFG_CENTER_WW2A1_5", - "CFG_CENTER_IMUX10_2", - "CFG_CENTER_SE4BEG3_1", - "CFG_CENTER_LOGIC_OUTS_B21_9", - "CFG_CENTER_EE4BEG0_7", - "CFG_CENTER_IMUX16_5", - "CFG_CENTER_FAN3_1", - "CFG_CENTER_WR1END0_3", - "CFG_CENTER_NE4C2_0", - "CFG_CENTER_IMUX4_6", - "CFG_CENTER_FAN6_1", - "CFG_CENTER_LH10_7", - "CFG_CENTER_SE2A2_9", - "CFG_CENTER_BYP7_8", - "CFG_CENTER_IMUX9_9", - "CFG_CENTER_FAN4_9", - "CFG_CENTER_LOGIC_OUTS_B7_5", - "CFG_CENTER_IMUX24_8", - "CFG_CENTER_NW4END2_7", - "CFG_CENTER_WW4A2_5", - "CFG_CENTER_IMUX16_4", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_FAN7_7", - "CFG_CENTER_SE2A2_0", - "CFG_CENTER_LOGIC_OUTS_B16_0", - "CFG_CENTER_WL1END3_1", - "CFG_CENTER_EFUSE_USR_EFUSEUSR29", - "CFG_CENTER_SW2A3_1", - "CFG_CENTER_LH3_4", - "CFG_CENTER_IMUX26_9", - "CFG_CENTER_IMUX4_5", - "CFG_CENTER_IMUX15_8", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_NW2A2_4", - "CFG_CENTER_WR1END0_4", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_ER1BEG3_0", - "CFG_CENTER_IMUX10_5", - "CFG_CENTER_NE4C0_5", - "CFG_CENTER_WW4C3_0", - "CFG_CENTER_IMUX9_6", - "CFG_CENTER_SW2A2_4", - "CFG_CENTER_NE2A2_0", - "CFG_CENTER_EE4B3_6", - "CFG_CENTER_LH1_0", - "CFG_CENTER_WW4C1_1", - "CFG_CENTER_EE2A0_4", - "CFG_CENTER_NW2A0_8", - "CFG_CENTER_SW4END3_2", - "CFG_CENTER_NW2A0_6", - "CFG_CENTER_LOGIC_OUTS_B23_2", - "CFG_CENTER_LH7_3", - "CFG_CENTER_NE4C3_3", - "CFG_CENTER_NE4C2_3", - "CFG_CENTER_IMUX35_2", - "CFG_CENTER_IMUX12_3", - "CFG_CENTER_FAN4_5", - "CFG_CENTER_SE2A1_5", - "CFG_CENTER_NW2A3_4", - "CFG_CENTER_IMUX43_3", - "CFG_CENTER_CTRL0_5", - "CFG_CENTER_WW2END0_2", - "CFG_CENTER_FAN7_3", - "CFG_CENTER_SE4BEG1_1", - "CFG_CENTER_EE4A0_7", - "CFG_CENTER_WW4END0_4", - "CFG_CENTER_IMUX44_5", - "CFG_CENTER_SW4END3_9", - "CFG_CENTER_LOGIC_OUTS_B11_6", - "CFG_CENTER_IMUX2_5", - "CFG_CENTER_EE4B1_4", - "CFG_CENTER_IMUX10_7", - "CFG_CENTER_CTRL1_8", - "CFG_CENTER_IMUX45_1", - "CFG_CENTER_IMUX10_1", - "CFG_CENTER_IMUX32_0", - "CFG_CENTER_WW2END2_8", - "CFG_CENTER_NW4END0_7", - "CFG_CENTER_FAN0_0", - "CFG_CENTER_ER1BEG2_2", - "CFG_CENTER_IMUX27_6", - "CFG_CENTER_IMUX19_7", - "CFG_CENTER_WW2A2_6", - "CFG_CENTER_LOGIC_OUTS_B2_8", - "CFG_CENTER_BYP5_0", - "CFG_CENTER_SW4END1_5", - "CFG_CENTER_SW4END1_1", - "CFG_CENTER_IMUX23_5", - "CFG_CENTER_IMUX2_6", - "CFG_CENTER_SE4C0_6", - "CFG_CENTER_LH9_4", - "CFG_CENTER_NW2A1_6", - "CFG_CENTER_IMUX33_5", - "CFG_CENTER_IMUX9_1", - "CFG_CENTER_EE2A3_8", - "CFG_CENTER_IMUX20_1", - "CFG_CENTER_WW4A1_9", - "CFG_CENTER_EFUSE_USR_EFUSEUSR25", - "CFG_CENTER_EE2BEG2_4", - "CFG_CENTER_IMUX45_5", - "CFG_CENTER_IMUX28_5", - "CFG_CENTER_NE4C1_1", - "CFG_CENTER_EL1BEG3_4", - "CFG_CENTER_IMUX8_4", - "CFG_CENTER_WW4A1_6", - "CFG_CENTER_WW2A3_1", - "CFG_CENTER_ER1BEG3_1", - "CFG_CENTER_IMUX10_9", - "CFG_CENTER_IMUX31_8", - "CFG_CENTER_WL1END1_9", - "CFG_CENTER_LOGIC_OUTS_B1_4", - "CFG_CENTER_SE4C2_6", - "CFG_CENTER_BYP4_7", - "CFG_CENTER_LH1_6", - "CFG_CENTER_SE2A0_5", - "CFG_CENTER_LH2_2", - "CFG_CENTER_IMUX37_5", - "CFG_CENTER_LOGIC_OUTS_B1_1", - "CFG_CENTER_WW4A2_6", - "CFG_CENTER_EFUSE_USR_EFUSEUSR14", - "CFG_CENTER_SE4BEG0_7", - "CFG_CENTER_SE4BEG1_8", - "CFG_CENTER_LOGIC_OUTS_B8_8", - "CFG_CENTER_IMUX16_1", - "CFG_CENTER_SE2A1_3", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_LOGIC_OUTS_B23_8", - "CFG_CENTER_LOGIC_OUTS_B17_6", - "CFG_CENTER_NW2A3_1", - "CFG_CENTER_FAN2_6", - "CFG_CENTER_IMUX2_7", - "CFG_CENTER_EE4A2_9", - "CFG_CENTER_NW4END3_6", - "CFG_CENTER_LOGIC_OUTS_B2_7", - "CFG_CENTER_WW2END1_3", - "CFG_CENTER_SE4BEG0_0", - "CFG_CENTER_LH1_2", - "CFG_CENTER_FAN4_0", - "CFG_CENTER_SW2A2_7", - "CFG_CENTER_WW4END1_4", - "CFG_CENTER_IMUX15_5", - "CFG_CENTER_SE4C3_3", - "CFG_CENTER_EE4A3_2", - "CFG_CENTER_SE4BEG3_5", - "CFG_CENTER_WW2END3_8", - "CFG_CENTER_SE4C3_2", - "CFG_CENTER_NW4END0_1", - "CFG_CENTER_LH2_6", - "CFG_CENTER_LOGIC_OUTS_B8_6", - "CFG_CENTER_SE2A3_2", - "CFG_CENTER_SE4C0_8", - "CFG_CENTER_IMUX11_4", - "CFG_CENTER_IMUX18_8", - "CFG_CENTER_IMUX25_6", - "CFG_CENTER_LOGIC_OUTS_B21_4", - "CFG_CENTER_NE4BEG3_4", - "CFG_CENTER_BYP6_3", - "CFG_CENTER_NE4C1_8", - "CFG_CENTER_WW2A2_3", - "CFG_CENTER_IMUX35_3", - "CFG_CENTER_IMUX47_6", - "CFG_CENTER_LOGIC_OUTS_B18_4", - "CFG_CENTER_EL1BEG3_7", - "CFG_CENTER_EE4C0_1", - "CFG_CENTER_LH3_8", - "CFG_CENTER_WW4A1_7", - "CFG_CENTER_LOGIC_OUTS_B5_7", - "CFG_CENTER_LOGIC_OUTS_B10_5", - "CFG_CENTER_WR1END3_2", - "CFG_CENTER_WL1END1_1", - "CFG_CENTER_SW4A0_3", - "CFG_CENTER_EFUSE_USR_EFUSEUSR0", - "CFG_CENTER_IMUX12_6", - "CFG_CENTER_ER1BEG2_3", - "CFG_CENTER_WW4B3_3", - "CFG_CENTER_SE2A2_1", - "CFG_CENTER_WW2A1_0", - "CFG_CENTER_LOGIC_OUTS_B21_0", - "CFG_CENTER_LOGIC_OUTS_B4_8", - "CFG_CENTER_EL1BEG1_7", - "CFG_CENTER_NE2A3_0", - "CFG_CENTER_EL1BEG0_3", - "CFG_CENTER_WW2A1_1", - "CFG_CENTER_EE4B2_4", - "CFG_CENTER_IMUX35_6", - "CFG_CENTER_IMUX38_3", - "CFG_CENTER_NW2A2_0", - "CFG_CENTER_WL1END3_7", - "CFG_CENTER_EFUSE_USR_EFUSEUSR11", - "CFG_CENTER_EE4B3_4", - "CFG_CENTER_LOGIC_OUTS_B14_4", - "CFG_CENTER_TOP_DNA_PORT_CLK", - "CFG_CENTER_LOGIC_OUTS_B6_1", - "CFG_CENTER_LOGIC_OUTS_B20_3", - "CFG_CENTER_IMUX39_6", - "CFG_CENTER_WW4B3_0", - "CFG_CENTER_LOGIC_OUTS_B15_2", - "CFG_CENTER_LOGIC_OUTS_B15_8", - "CFG_CENTER_SE2A3_0", - "CFG_CENTER_SW4END2_9", - "CFG_CENTER_IMUX44_6", - "CFG_CENTER_SW4END0_1", - "CFG_CENTER_CTRL0_3", - "CFG_CENTER_IMUX11_1", - "CFG_CENTER_NW2A1_7", - "CFG_CENTER_SW4END2_3", - "CFG_CENTER_SE2A0_0", - "CFG_CENTER_TOP_ICAP1_CLK", - "CFG_CENTER_CTRL0_4", - "CFG_CENTER_NE2A0_1", - "CFG_CENTER_LH5_4", - "CFG_CENTER_CTRL1_0", - "CFG_CENTER_WW2A0_8", - "CFG_CENTER_IMUX45_3", - "CFG_CENTER_LH11_0", - "CFG_CENTER_FAN0_3", - "CFG_CENTER_WW4C0_4", - "CFG_CENTER_EE4BEG0_9", - "CFG_CENTER_LOGIC_OUTS_B20_7", - "CFG_CENTER_IMUX43_2", - "CFG_CENTER_FAN7_4", - "CFG_CENTER_WR1END1_4", - "CFG_CENTER_WW4A1_3", - "CFG_CENTER_ER1BEG2_4", - "CFG_CENTER_FAN6_2", - "CFG_CENTER_EE4A0_4", - "CFG_CENTER_LOGIC_OUTS_B4_0", - "CFG_CENTER_EL1BEG2_3", - "CFG_CENTER_IMUX35_8", - "CFG_CENTER_NE4C3_5", - "CFG_CENTER_LOGIC_OUTS_B22_5", - "CFG_CENTER_SE4BEG2_7", - "CFG_CENTER_IMUX44_9", - "CFG_CENTER_WW4C0_8", - "CFG_CENTER_SW4A2_1", - "CFG_CENTER_ER1BEG1_9", - "CFG_CENTER_WW4A0_0", - "CFG_CENTER_NE2A2_6", - "CFG_CENTER_LOGIC_OUTS_B3_7", - "CFG_CENTER_IMUX40_7", - "CFG_CENTER_NE4BEG0_5", - "CFG_CENTER_EL1BEG3_8", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_WW4A3_7", - "CFG_CENTER_SW4END2_5", - "CFG_CENTER_WW4B2_0", - "CFG_CENTER_IMUX39_1", - "CFG_CENTER_IMUX6_1", - "CFG_CENTER_SW2A3_9", - "CFG_CENTER_BLOCK_OUTS_B1_5", - "CFG_CENTER_NW4A1_5", - "CFG_CENTER_EE4C0_8", - "CFG_CENTER_WW4B0_0", - "CFG_CENTER_BYP6_6", - "CFG_CENTER_SW2A1_1", - "CFG_CENTER_NE2A1_8", - "CFG_CENTER_LOGIC_OUTS_B19_8", - "CFG_CENTER_WL1END2_5", - "CFG_CENTER_IMUX33_3", - "CFG_CENTER_LH2_7", - "CFG_CENTER_NE4C2_4", - "CFG_CENTER_NW4END3_8", - "CFG_CENTER_NE4BEG1_5", - "CFG_CENTER_NE4C1_7", - "CFG_CENTER_LOGIC_OUTS_B4_6", - "CFG_CENTER_EE4C3_6", - "CFG_CENTER_EFUSE_USR_EFUSEUSR24", - "CFG_CENTER_SE4C0_0", - "CFG_CENTER_LOGIC_OUTS_B6_8", - "CFG_CENTER_SW2A2_3", - "CFG_CENTER_EE2BEG1_5", - "CFG_CENTER_LOGIC_OUTS_B7_3", - "CFG_CENTER_SW4A1_5", - "CFG_CENTER_IMUX40_3", - "CFG_CENTER_EE2BEG0_2", - "CFG_CENTER_EE4B1_7", - "CFG_CENTER_NE2A1_3", - "CFG_CENTER_NE4BEG3_0", - "CFG_CENTER_EE4C2_7", - "CFG_CENTER_EE2A2_9", - "CFG_CENTER_IMUX0_6", - "CFG_CENTER_WW4C3_4", - "CFG_CENTER_LH6_9", - "CFG_CENTER_CLK0_3", - "CFG_CENTER_EE2A2_2", - "CFG_CENTER_IMUX26_8", - "CFG_CENTER_EFUSE_USR_EFUSEUSR17", - "CFG_CENTER_SE2A0_9", - "CFG_CENTER_ER1BEG3_5", - "CFG_CENTER_WW4C2_0", - "CFG_CENTER_WR1END2_0", - "CFG_CENTER_NE4BEG1_6", - "CFG_CENTER_LOGIC_OUTS_B4_9", - "CFG_CENTER_LOGIC_OUTS_B10_2", - "CFG_CENTER_IMUX26_6", - "CFG_CENTER_LH2_0", - "CFG_CENTER_EE4BEG0_6", - "CFG_CENTER_IMUX27_3", - "CFG_CENTER_LH12_4", - "CFG_CENTER_EL1BEG3_2", - "CFG_CENTER_FAN5_0", - "CFG_CENTER_ER1BEG2_9", - "CFG_CENTER_NE4C1_5", - "CFG_CENTER_IMUX6_8", - "CFG_CENTER_WW4B1_9", - "CFG_CENTER_EL1BEG0_0", - "CFG_CENTER_IMUX46_9", - "CFG_CENTER_NE4BEG0_7", - "CFG_CENTER_EE4A1_1", - "CFG_CENTER_IMUX21_5", - "CFG_CENTER_LOGIC_OUTS_B19_9", - "CFG_CENTER_EE4A2_4", - "CFG_CENTER_LH12_1", - "CFG_CENTER_SW2A1_3", - "CFG_CENTER_WW4END2_2", - "CFG_CENTER_IMUX27_9", - "CFG_CENTER_IMUX26_1", - "CFG_CENTER_WR1END0_0", - "CFG_CENTER_IMUX19_5", - "CFG_CENTER_BYP5_9", - "CFG_CENTER_EL1BEG1_9", - "CFG_CENTER_WR1END3_1", - "CFG_CENTER_FAN2_8", - "CFG_CENTER_IMUX9_4", - "CFG_CENTER_IMUX44_8", - "CFG_CENTER_LOGIC_OUTS_B8_0", - "CFG_CENTER_DNA_PORT_READ", - "CFG_CENTER_IMUX18_6", - "CFG_CENTER_FAN3_8", - "CFG_CENTER_EE2BEG2_1", - "CFG_CENTER_IMUX22_0", - "CFG_CENTER_NW4A0_0", - "CFG_CENTER_NW4END2_0", - "CFG_CENTER_LOGIC_OUTS_B13_2", - "CFG_CENTER_IMUX5_0", - "CFG_CENTER_EE4B1_6", - "CFG_CENTER_IMUX13_5", - "CFG_CENTER_NE2A0_2", - "CFG_CENTER_IMUX24_9", - "CFG_CENTER_IMUX9_8", - "CFG_CENTER_LH8_4", - "CFG_CENTER_BYP3_5", - "CFG_CENTER_BLOCK_OUTS_B0_2", - "CFG_CENTER_LOGIC_OUTS_B6_5", - "CFG_CENTER_BLOCK_OUTS_B1_6", - "CFG_CENTER_EE4C1_8", - "CFG_CENTER_EE4B2_2", - "CFG_CENTER_ER1BEG2_8", - "CFG_CENTER_WW4END2_0", - "CFG_CENTER_EE2BEG2_5", - "CFG_CENTER_ER1BEG3_7", - "CFG_CENTER_SW2A3_4", - "CFG_CENTER_IMUX4_1", - "CFG_CENTER_LH8_6", - "CFG_CENTER_LOGIC_OUTS_B0_8", - "CFG_CENTER_LOGIC_OUTS_B23_0", - "CFG_CENTER_NE4C0_4", - "CFG_CENTER_FAN0_2", - "CFG_CENTER_EE4A3_1", - "CFG_CENTER_NE4BEG1_7", - "CFG_CENTER_EE2BEG1_9", - "CFG_CENTER_LOGIC_OUTS_B2_6", - "CFG_CENTER_EE2BEG1_6", - "CFG_CENTER_EE4A0_9", - "CFG_CENTER_NW4END1_2", - "CFG_CENTER_SE2A2_8", - "CFG_CENTER_EE4BEG1_1", - "CFG_CENTER_EE4B0_1", - "CFG_CENTER_ER1BEG1_5", - "CFG_CENTER_NW2A3_8", - "CFG_CENTER_IMUX11_3", - "CFG_CENTER_NW2A3_6", - "CFG_CENTER_WW4A0_3", - "CFG_CENTER_WW4C3_2", - "CFG_CENTER_LOGIC_OUTS_B12_9", - "CFG_CENTER_BYP6_2", - "CFG_CENTER_NW4END3_4", - "CFG_CENTER_NE4BEG1_1", - "CFG_CENTER_EFUSE_USR_EFUSEUSR5", - "CFG_CENTER_NE4BEG0_9", - "CFG_CENTER_NW4A0_2", - "CFG_CENTER_SW4A3_2", - "CFG_CENTER_IMUX17_1", - "CFG_CENTER_WW2A2_8", - "CFG_CENTER_EL1BEG2_5", - "CFG_CENTER_NW4A3_1", - "CFG_CENTER_BLOCK_OUTS_B1_4", - "CFG_CENTER_IMUX27_2", - "CFG_CENTER_LOGIC_OUTS_B6_7", - "CFG_CENTER_LOGIC_OUTS_B7_6", - "CFG_CENTER_WW4END0_3", - "CFG_CENTER_IMUX3_2", - "CFG_CENTER_LOGIC_OUTS_B4_5", - "CFG_CENTER_ER1BEG1_8", - "CFG_CENTER_IMUX0_2", - "CFG_CENTER_CLK0_0", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_FAN4_7", - "CFG_CENTER_IMUX23_0", - "CFG_CENTER_LH4_1", - "CFG_CENTER_EE4BEG2_5", - "CFG_CENTER_BYP7_1", - "CFG_CENTER_LOGIC_OUTS_B9_7", - "CFG_CENTER_IMUX34_3", - "CFG_CENTER_WW4END1_6", - "CFG_CENTER_LH5_1", - "CFG_CENTER_LOGIC_OUTS_B9_8", - "CFG_CENTER_BYP1_9", - "CFG_CENTER_IMUX44_2", - "CFG_CENTER_WW4C1_3", - "CFG_CENTER_SW2A3_3", - "CFG_CENTER_CTRL1_5", - "CFG_CENTER_LOGIC_OUTS_B5_9", - "CFG_CENTER_SE4C1_8", - "CFG_CENTER_NW4A2_8", - "CFG_CENTER_LOGIC_OUTS_B16_5", - "CFG_CENTER_IMUX0_0", - "CFG_CENTER_IMUX25_5", - "CFG_CENTER_IMUX24_1", - "CFG_CENTER_WW2A3_0", - "CFG_CENTER_IMUX25_1", - "CFG_CENTER_ER1BEG1_6", - "CFG_CENTER_SE4C3_6", - "CFG_CENTER_IMUX0_9", - "CFG_CENTER_BLOCK_OUTS_B2_0", - "CFG_CENTER_WW4END0_9", - "CFG_CENTER_IMUX1_3", - "CFG_CENTER_NW4END2_3", - "CFG_CENTER_EE2BEG0_6", - "CFG_CENTER_EE4C2_0", - "CFG_CENTER_LOGIC_OUTS_B19_2", - "CFG_CENTER_LOGIC_OUTS_B3_5", - "CFG_CENTER_SE2A0_3", - "CFG_CENTER_LOGIC_OUTS_B19_6", - "CFG_CENTER_NE4BEG1_3", - "CFG_CENTER_SW4A0_0", - "CFG_CENTER_WW2END0_5", - "CFG_CENTER_LOGIC_OUTS_B10_3", - "CFG_CENTER_WR1END1_2", - "CFG_CENTER_NW2A0_5", - "CFG_CENTER_IMUX27_4", - "CFG_CENTER_LOGIC_OUTS_B2_2", - "CFG_CENTER_NW2A2_5", - "CFG_CENTER_WW4A1_5", - "CFG_CENTER_BLOCK_OUTS_B2_7", - "CFG_CENTER_IMUX40_0", - "CFG_CENTER_IMUX12_1", - "CFG_CENTER_WW4B0_8", - "CFG_CENTER_LOGIC_OUTS_B10_4", - "CFG_CENTER_WL1END2_6", - "CFG_CENTER_LOGIC_OUTS_B2_3", - "CFG_CENTER_IMUX10_3", - "CFG_CENTER_NW2A3_5", - "CFG_CENTER_SE2A3_1", - "CFG_CENTER_NE4BEG3_2", - "CFG_CENTER_WW4END0_5", - "CFG_CENTER_FAN2_2", - "CFG_CENTER_EL1BEG0_2", - "CFG_CENTER_WW4C2_4", - "CFG_CENTER_IMUX46_2", - "CFG_CENTER_NW4A3_9", - "CFG_CENTER_IMUX28_1", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_LOGIC_OUTS_B21_5", - "CFG_CENTER_LOGIC_OUTS_B4_2", - "CFG_CENTER_EE2BEG3_6", - "CFG_CENTER_NE4BEG2_8", - "CFG_CENTER_LH4_6", - "CFG_CENTER_WW2A2_2", - "CFG_CENTER_NW4A3_6", - "CFG_CENTER_EE4C3_1", - "CFG_CENTER_IMUX34_2", - "CFG_CENTER_IMUX18_0", - "CFG_CENTER_WW4C0_9", - "CFG_CENTER_LOGIC_OUTS_B22_7", - "CFG_CENTER_IMUX26_4", - "CFG_CENTER_NW4A1_4", - "CFG_CENTER_IMUX47_2", - "CFG_CENTER_SW4END2_0", - "CFG_CENTER_SW4A3_9", - "CFG_CENTER_EE4BEG0_3", - "CFG_CENTER_LOGIC_OUTS_B12_2", - "CFG_CENTER_SW2A2_1", - "CFG_CENTER_NW4A1_6", - "CFG_CENTER_BYP7_5", - "CFG_CENTER_LH3_1", - "CFG_CENTER_WW4B0_6", - "CFG_CENTER_SW4A3_7", - "CFG_CENTER_NW4A1_3", - "CFG_CENTER_EFUSE_USR_EFUSEUSR28", - "CFG_CENTER_ER1BEG3_4", - "CFG_CENTER_SE4C1_3", - "CFG_CENTER_IMUX11_2", - "CFG_CENTER_WW4END3_6", - "CFG_CENTER_CTRL0_7", - "CFG_CENTER_NW4A1_1", - "CFG_CENTER_EFUSE_USR_EFUSEUSR15", - "CFG_CENTER_LOGIC_OUTS_B22_1", - "CFG_CENTER_NE4C2_7", - "CFG_CENTER_SW4END0_8", - "CFG_CENTER_WW4C1_2", - "CFG_CENTER_IMUX21_8", - "CFG_CENTER_DNA_PORT_DIN", - "CFG_CENTER_SW4A1_6", - "CFG_CENTER_NW4END1_4", - "CFG_CENTER_LH12_7", - "CFG_CENTER_EE4A2_8", - "CFG_CENTER_NW4END2_8", - "CFG_CENTER_LH2_8", - "CFG_CENTER_BYP6_8", - "CFG_CENTER_ER1BEG1_7", - "CFG_CENTER_SE2A1_4", - "CFG_CENTER_IMUX43_9", - "CFG_CENTER_EE4C2_1", - "CFG_CENTER_IMUX32_5", - "CFG_CENTER_LH11_6", - "CFG_CENTER_EE4BEG3_4", - "CFG_CENTER_NW4A1_0", - "CFG_CENTER_LOGIC_OUTS_B7_8", - "CFG_CENTER_LH4_9", - "CFG_CENTER_NE2A0_0", - "CFG_CENTER_IMUX18_9", - "CFG_CENTER_IMUX14_2", - "CFG_CENTER_IMUX5_5", - "CFG_CENTER_IMUX20_7", - "CFG_CENTER_SE4BEG2_8", - "CFG_CENTER_IMUX43_6", - "CFG_CENTER_LOGIC_OUTS_B13_6", - "CFG_CENTER_FAN7_0", - "CFG_CENTER_BLOCK_OUTS_B0_3", - "CFG_CENTER_WW4END3_2", - "CFG_CENTER_IMUX2_8", - "CFG_CENTER_IMUX22_7", - "CFG_CENTER_LOGIC_OUTS_B2_0", - "CFG_CENTER_IMUX39_8", - "CFG_CENTER_EE2A2_5", - "CFG_CENTER_NE4BEG1_8", - "CFG_CENTER_WW4END0_2", - "CFG_CENTER_DNA_PORT_CLK", - "CFG_CENTER_IMUX30_0", - "CFG_CENTER_EE4C0_2", - "CFG_CENTER_LOGIC_OUTS_B8_3", - "CFG_CENTER_IMUX33_6", - "CFG_CENTER_NW2A0_4", - "CFG_CENTER_SE4BEG2_4", - "CFG_CENTER_WL1END0_2", - "CFG_CENTER_WW4C0_3", - "CFG_CENTER_WR1END0_8", - "CFG_CENTER_SW2A0_8", - "CFG_CENTER_IMUX34_6", - "CFG_CENTER_WW4END3_4", - "CFG_CENTER_EL1BEG3_1", - "CFG_CENTER_WR1END3_4", - "CFG_CENTER_FAN6_6", - "CFG_CENTER_EL1BEG3_9", - "CFG_CENTER_SE4C3_5", - "CFG_CENTER_NW4A3_3", - "CFG_CENTER_EE4C3_2", - "CFG_CENTER_WR1END1_1", - "CFG_CENTER_BLOCK_OUTS_B0_7", - "CFG_CENTER_NE2A1_1", - "CFG_CENTER_WW2A3_6", - "CFG_CENTER_IMUX44_1", - "CFG_CENTER_IMUX35_7", - "CFG_CENTER_EE4C3_7", - "CFG_CENTER_WW4B3_8", - "CFG_CENTER_NW4A1_7", - "CFG_CENTER_EE2A2_0", - "CFG_CENTER_IMUX29_5", - "CFG_CENTER_IMUX7_2", - "CFG_CENTER_WR1END0_7", - "CFG_CENTER_IMUX12_2", - "CFG_CENTER_NE4BEG3_7", - "CFG_CENTER_IMUX41_1", - "CFG_CENTER_WW2END1_9", - "CFG_CENTER_IMUX29_0", - "CFG_CENTER_NE2A0_8", - "CFG_CENTER_WW4C2_3", - "CFG_CENTER_CLK0_2", - "CFG_CENTER_LOGIC_OUTS_B15_1", - "CFG_CENTER_WW4END2_8", - "CFG_CENTER_WW4END1_2", - "CFG_CENTER_FAN4_3", - "CFG_CENTER_LOGIC_OUTS_B15_3", - "CFG_CENTER_EE4BEG2_8", - "CFG_CENTER_IMUX2_9", - "CFG_CENTER_IMUX0_7", - "CFG_CENTER_SW2A3_2", - "CFG_CENTER_EE2A3_5", - "CFG_CENTER_NE4C0_3", - "CFG_CENTER_BYP4_0", - "CFG_CENTER_WW4A0_9", - "CFG_CENTER_SE4C2_3", - "CFG_CENTER_BYP0_4", - "CFG_CENTER_EE2BEG1_1", - "CFG_CENTER_NE4BEG2_3", - "CFG_CENTER_EL1BEG3_5", - "CFG_CENTER_BLOCK_OUTS_B1_3", - "CFG_CENTER_WW4A3_1", - "CFG_CENTER_NW2A1_8", - "CFG_CENTER_WL1END0_7", - "CFG_CENTER_SW4A2_2", - "CFG_CENTER_IMUX23_8", - "CFG_CENTER_BYP7_9", - "CFG_CENTER_LOGIC_OUTS_B11_4", - "CFG_CENTER_IMUX8_0", - "CFG_CENTER_EE4C1_6", - "CFG_CENTER_WW4B2_7", - "CFG_CENTER_EE4BEG3_8", - "CFG_CENTER_LOGIC_OUTS_B23_7", - "CFG_CENTER_IMUX31_2", - "CFG_CENTER_LOGIC_OUTS_B23_5", - "CFG_CENTER_WW4END3_1", - "CFG_CENTER_LOGIC_OUTS_B1_2", - "CFG_CENTER_WW4A0_8", - "CFG_CENTER_WW4END2_5", - "CFG_CENTER_WW4B0_3", - "CFG_CENTER_SW4A1_4", - "CFG_CENTER_NE4C2_6", - "CFG_CENTER_LOGIC_OUTS_B9_9", - "CFG_CENTER_WR1END3_0", - "CFG_CENTER_IMUX33_2", - "CFG_CENTER_BLOCK_OUTS_B0_1" - ], - "sites": [ - { - "prefix": "DNA_PORT", - "y_coord": 0, - "type": "DNA_PORT", - "site_pins": { - "DOUT": "CFG_CENTER_DNA_PORT_DOUT", - "CLK": "CFG_CENTER_DNA_PORT_CLK", - "READ": "CFG_CENTER_DNA_PORT_READ", - "SHIFT": "CFG_CENTER_DNA_PORT_SHIFT", - "DIN": "CFG_CENTER_DNA_PORT_DIN" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "EFUSE_USR", - "y_coord": 0, - "type": "EFUSE_USR", - "site_pins": { - "EFUSEUSR27": "CFG_CENTER_EFUSE_USR_EFUSEUSR27", - "EFUSEUSR17": "CFG_CENTER_EFUSE_USR_EFUSEUSR17", - "EFUSEUSR16": "CFG_CENTER_EFUSE_USR_EFUSEUSR16", - "EFUSEUSR14": "CFG_CENTER_EFUSE_USR_EFUSEUSR14", - "EFUSEUSR18": "CFG_CENTER_EFUSE_USR_EFUSEUSR18", - "EFUSEUSR10": "CFG_CENTER_EFUSE_USR_EFUSEUSR10", - "EFUSEUSR25": "CFG_CENTER_EFUSE_USR_EFUSEUSR25", - "EFUSEUSR12": "CFG_CENTER_EFUSE_USR_EFUSEUSR12", - "EFUSEUSR11": "CFG_CENTER_EFUSE_USR_EFUSEUSR11", - "EFUSEUSR31": "CFG_CENTER_EFUSE_USR_EFUSEUSR31", - "EFUSEUSR1": "CFG_CENTER_EFUSE_USR_EFUSEUSR1", - "EFUSEUSR30": "CFG_CENTER_EFUSE_USR_EFUSEUSR30", - "EFUSEUSR0": "CFG_CENTER_EFUSE_USR_EFUSEUSR0", - "EFUSEUSR9": "CFG_CENTER_EFUSE_USR_EFUSEUSR9", - "EFUSEUSR2": "CFG_CENTER_EFUSE_USR_EFUSEUSR2", - "EFUSEUSR13": "CFG_CENTER_EFUSE_USR_EFUSEUSR13", - "EFUSEUSR6": "CFG_CENTER_EFUSE_USR_EFUSEUSR6", - "EFUSEUSR23": "CFG_CENTER_EFUSE_USR_EFUSEUSR23", - "EFUSEUSR29": "CFG_CENTER_EFUSE_USR_EFUSEUSR29", - "EFUSEUSR24": "CFG_CENTER_EFUSE_USR_EFUSEUSR24", - "EFUSEUSR19": "CFG_CENTER_EFUSE_USR_EFUSEUSR19", - "EFUSEUSR20": "CFG_CENTER_EFUSE_USR_EFUSEUSR20", - "EFUSEUSR22": "CFG_CENTER_EFUSE_USR_EFUSEUSR22", - "EFUSEUSR21": "CFG_CENTER_EFUSE_USR_EFUSEUSR21", - "EFUSEUSR3": "CFG_CENTER_EFUSE_USR_EFUSEUSR3", - "EFUSEUSR8": "CFG_CENTER_EFUSE_USR_EFUSEUSR8", - "EFUSEUSR4": "CFG_CENTER_EFUSE_USR_EFUSEUSR4", - "EFUSEUSR28": "CFG_CENTER_EFUSE_USR_EFUSEUSR28", - "EFUSEUSR7": "CFG_CENTER_EFUSE_USR_EFUSEUSR7", - "EFUSEUSR15": "CFG_CENTER_EFUSE_USR_EFUSEUSR15", - "EFUSEUSR26": "CFG_CENTER_EFUSE_USR_EFUSEUSR26", - "EFUSEUSR5": "CFG_CENTER_EFUSE_USR_EFUSEUSR5" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR24->CFG_CENTER_LOGIC_OUTS_B16_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR24", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR1->CFG_CENTER_LOGIC_OUTS_B17_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR1", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR2->CFG_CENTER_LOGIC_OUTS_B18_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR2", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR11->CFG_CENTER_LOGIC_OUTS_B19_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR11", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR12->CFG_CENTER_LOGIC_OUTS_B20_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR12", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR15->CFG_CENTER_LOGIC_OUTS_B23_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR15", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR30->CFG_CENTER_LOGIC_OUTS_B22_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR30", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR17->CFG_CENTER_LOGIC_OUTS_B17_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR17", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR14->CFG_CENTER_LOGIC_OUTS_B22_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR14", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_CLK1_0->CFG_CENTER_TOP_ICAP1_CLK": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_TOP_ICAP1_CLK", - "is_directional": "1", - "src_wire": "CFG_CENTER_CLK1_0", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR3->CFG_CENTER_LOGIC_OUTS_B19_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR3", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR20->CFG_CENTER_LOGIC_OUTS_B20_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR20", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR8->CFG_CENTER_LOGIC_OUTS_B16_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR8", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR26->CFG_CENTER_LOGIC_OUTS_B18_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR26", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_IMUX41_5->CFG_CENTER_DNA_PORT_READ": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_DNA_PORT_READ", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX41_5", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR18->CFG_CENTER_LOGIC_OUTS_B18_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR18", - "is_pseudo": "0" - }, "CFG_CENTER_TOP.CFG_CENTER_DNA_PORT_DOUT->CFG_CENTER_LOGIC_OUTS_B23_5": { "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_5", - "is_directional": "1", "src_wire": "CFG_CENTER_DNA_PORT_DOUT", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR19->CFG_CENTER_LOGIC_OUTS_B19_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8", "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR19", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR31->CFG_CENTER_LOGIC_OUTS_B23_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR31", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR7->CFG_CENTER_LOGIC_OUTS_B23_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR7", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR0->CFG_CENTER_LOGIC_OUTS_B16_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR0", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR27->CFG_CENTER_LOGIC_OUTS_B19_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR27", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR21->CFG_CENTER_LOGIC_OUTS_B21_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR21", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR16->CFG_CENTER_LOGIC_OUTS_B16_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR16", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR10->CFG_CENTER_LOGIC_OUTS_B18_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR10", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR13->CFG_CENTER_LOGIC_OUTS_B21_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR13", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR28->CFG_CENTER_LOGIC_OUTS_B20_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR28", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_IMUX43_5->CFG_CENTER_DNA_PORT_DIN": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_DNA_PORT_DIN", - "is_directional": "1", - "src_wire": "CFG_CENTER_IMUX43_5", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR9->CFG_CENTER_LOGIC_OUTS_B17_7": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR9", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR6->CFG_CENTER_LOGIC_OUTS_B22_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR6", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR29->CFG_CENTER_LOGIC_OUTS_B21_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR29", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_TOP_DNA_PORT_CLK->CFG_CENTER_DNA_PORT_CLK": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_DNA_PORT_CLK", - "is_directional": "1", - "src_wire": "CFG_CENTER_TOP_DNA_PORT_CLK", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR25->CFG_CENTER_LOGIC_OUTS_B17_9": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_9", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR25", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR4->CFG_CENTER_LOGIC_OUTS_B20_6": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR4", - "is_pseudo": "0" - }, - "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR22->CFG_CENTER_LOGIC_OUTS_B22_8": { - "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8", - "is_directional": "1", - "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR22", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_5" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR23->CFG_CENTER_LOGIC_OUTS_B23_8": { "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8", - "is_directional": "1", "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR23", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR16->CFG_CENTER_LOGIC_OUTS_B16_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_8" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR11->CFG_CENTER_LOGIC_OUTS_B19_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR7->CFG_CENTER_LOGIC_OUTS_B23_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR2->CFG_CENTER_LOGIC_OUTS_B18_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR21->CFG_CENTER_LOGIC_OUTS_B21_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR22->CFG_CENTER_LOGIC_OUTS_B22_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR17->CFG_CENTER_LOGIC_OUTS_B17_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR14->CFG_CENTER_LOGIC_OUTS_B22_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR3->CFG_CENTER_LOGIC_OUTS_B19_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR18->CFG_CENTER_LOGIC_OUTS_B18_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8" + }, + "CFG_CENTER_TOP.CFG_CENTER_IMUX41_5->CFG_CENTER_DNA_PORT_READ": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX41_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DNA_PORT_READ" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR30->CFG_CENTER_LOGIC_OUTS_B22_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9" }, "CFG_CENTER_TOP.CFG_CENTER_IMUX42_5->CFG_CENTER_DNA_PORT_SHIFT": { "can_invert": "0", - "dst_wire": "CFG_CENTER_DNA_PORT_SHIFT", - "is_directional": "1", "src_wire": "CFG_CENTER_IMUX42_5", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DNA_PORT_SHIFT" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR15->CFG_CENTER_LOGIC_OUTS_B23_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR4->CFG_CENTER_LOGIC_OUTS_B20_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR5->CFG_CENTER_LOGIC_OUTS_B21_6": { "can_invert": "0", - "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6", - "is_directional": "1", "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR5", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR27->CFG_CENTER_LOGIC_OUTS_B19_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_9" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR28->CFG_CENTER_LOGIC_OUTS_B20_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR8->CFG_CENTER_LOGIC_OUTS_B16_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR25->CFG_CENTER_LOGIC_OUTS_B17_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_9" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR6->CFG_CENTER_LOGIC_OUTS_B22_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR0->CFG_CENTER_LOGIC_OUTS_B16_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR13->CFG_CENTER_LOGIC_OUTS_B21_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR9->CFG_CENTER_LOGIC_OUTS_B17_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR10->CFG_CENTER_LOGIC_OUTS_B18_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR29->CFG_CENTER_LOGIC_OUTS_B21_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR12->CFG_CENTER_LOGIC_OUTS_B20_7": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR26->CFG_CENTER_LOGIC_OUTS_B18_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_9" + }, + "CFG_CENTER_TOP.CFG_CENTER_IMUX43_5->CFG_CENTER_DNA_PORT_DIN": { + "can_invert": "0", + "src_wire": "CFG_CENTER_IMUX43_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DNA_PORT_DIN" + }, + "CFG_CENTER_TOP.CFG_CENTER_CLK1_0->CFG_CENTER_TOP_ICAP1_CLK": { + "can_invert": "0", + "src_wire": "CFG_CENTER_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_TOP_ICAP1_CLK" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR19->CFG_CENTER_LOGIC_OUTS_B19_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR1->CFG_CENTER_LOGIC_OUTS_B17_6": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6" + }, + "CFG_CENTER_TOP.CFG_CENTER_TOP_DNA_PORT_CLK->CFG_CENTER_DNA_PORT_CLK": { + "can_invert": "0", + "src_wire": "CFG_CENTER_TOP_DNA_PORT_CLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_DNA_PORT_CLK" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR24->CFG_CENTER_LOGIC_OUTS_B16_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_9" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR31->CFG_CENTER_LOGIC_OUTS_B23_9": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9" + }, + "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR20->CFG_CENTER_LOGIC_OUTS_B20_8": { + "can_invert": "0", + "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8" } }, - "tile_type": "CFG_CENTER_TOP" + "wires": [ + "CFG_CENTER_LH7_7", + "CFG_CENTER_EE4BEG3_6", + "CFG_CENTER_IMUX39_7", + "CFG_CENTER_FAN2_8", + "CFG_CENTER_IMUX14_7", + "CFG_CENTER_NW4A0_2", + "CFG_CENTER_WL1END0_3", + "CFG_CENTER_IMUX40_8", + "CFG_CENTER_WW2A1_9", + "CFG_CENTER_LH3_3", + "CFG_CENTER_DNA_PORT_DIN", + "CFG_CENTER_NE4C0_3", + "CFG_CENTER_IMUX16_4", + "CFG_CENTER_EE4B2_0", + "CFG_CENTER_LOGIC_OUTS_B14_2", + "CFG_CENTER_IMUX11_2", + "CFG_CENTER_NW4A3_0", + "CFG_CENTER_IMUX12_5", + "CFG_CENTER_EL1BEG2_3", + "CFG_CENTER_IMUX27_7", + "CFG_CENTER_LOGIC_OUTS_B22_0", + "CFG_CENTER_EE4B0_3", + "CFG_CENTER_WR1END1_6", + "CFG_CENTER_ER1BEG3_5", + "CFG_CENTER_EL1BEG1_7", + "CFG_CENTER_EE4A3_9", + "CFG_CENTER_IMUX18_6", + "CFG_CENTER_IMUX34_5", + "CFG_CENTER_EE4A0_9", + "CFG_CENTER_NE4BEG3_9", + "CFG_CENTER_BYP0_5", + "CFG_CENTER_NE4C1_4", + "CFG_CENTER_FAN5_2", + "CFG_CENTER_ER1BEG0_3", + "CFG_CENTER_LOGIC_OUTS_B2_3", + "CFG_CENTER_SW4END3_4", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA27", + "CFG_CENTER_NE2A1_9", + "CFG_CENTER_WW4A0_0", + "CFG_CENTER_WR1END2_4", + "CFG_CENTER_SE4C3_9", + "CFG_CENTER_IMUX13_0", + "CFG_CENTER_IMUX24_6", + "CFG_CENTER_IMUX34_6", + "CFG_CENTER_EE4B1_2", + "CFG_CENTER_BLOCK_OUTS_B2_4", + "CFG_CENTER_LH1_3", + "CFG_CENTER_EL1BEG1_6", + "CFG_CENTER_EE2BEG0_1", + "CFG_CENTER_IMUX1_1", + "CFG_CENTER_WR1END0_0", + "CFG_CENTER_LOGIC_OUTS_B6_7", + "CFG_CENTER_LOGIC_OUTS_B3_0", + "CFG_CENTER_CLK1_5", + "CFG_CENTER_WW2END2_8", + "CFG_CENTER_SE4BEG2_5", + "CFG_CENTER_LOGIC_OUTS_B23_3", + "CFG_CENTER_IMUX0_4", + "CFG_CENTER_FAN3_4", + "CFG_CENTER_EFUSE_USR_EFUSEUSR15", + "CFG_CENTER_NW4END2_6", + "CFG_CENTER_SE4BEG2_3", + "CFG_CENTER_EE4C3_4", + "CFG_CENTER_EE4BEG0_6", + "CFG_CENTER_WW2A3_7", + "CFG_CENTER_WW4C0_6", + "CFG_CENTER_LH3_2", + "CFG_CENTER_IMUX12_0", + "CFG_CENTER_IMUX3_9", + "CFG_CENTER_SW4END1_5", + "CFG_CENTER_WW2END2_6", + "CFG_CENTER_IMUX42_0", + "CFG_CENTER_LOGIC_OUTS_B8_1", + "CFG_CENTER_LOGIC_OUTS_B13_9", + "CFG_CENTER_CTRL1_0", + "CFG_CENTER_ER1BEG2_8", + "CFG_CENTER_EE2BEG1_0", + "CFG_CENTER_IMUX41_3", + "CFG_CENTER_IMUX33_9", + "CFG_CENTER_LH11_0", + "CFG_CENTER_SE4C3_4", + "CFG_CENTER_LH9_0", + "CFG_CENTER_IMUX15_0", + "CFG_CENTER_WW2END0_5", + "CFG_CENTER_IMUX6_1", + "CFG_CENTER_WW2END3_7", + "CFG_CENTER_LOGIC_OUTS_B7_6", + "CFG_CENTER_SE4C0_1", + "CFG_CENTER_NW4A1_5", + "CFG_CENTER_WR1END3_0", + "CFG_CENTER_LH7_0", + "CFG_CENTER_EL1BEG3_6", + "CFG_CENTER_LOGIC_OUTS_B19_9", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA14", + "CFG_CENTER_IMUX2_0", + "CFG_CENTER_EL1BEG2_7", + "CFG_CENTER_NW4END1_7", + "CFG_CENTER_IMUX0_7", + "CFG_CENTER_WW4A2_3", + "CFG_CENTER_EE4B0_2", + "CFG_CENTER_LH7_6", + "CFG_CENTER_WW4A1_9", + "CFG_CENTER_FAN0_9", + "CFG_CENTER_ER1BEG0_7", + "CFG_CENTER_IMUX22_1", + "CFG_CENTER_EE2A0_1", + "CFG_CENTER_BYP3_5", + "CFG_CENTER_WW2A2_3", + "CFG_CENTER_WW4B2_5", + "CFG_CENTER_LH8_1", + "CFG_CENTER_IMUX43_5", + "CFG_CENTER_BLOCK_OUTS_B3_3", + "CFG_CENTER_EE4BEG0_5", + "CFG_CENTER_IMUX31_4", + "CFG_CENTER_LOGIC_OUTS_B4_2", + "CFG_CENTER_SE2A3_2", + "CFG_CENTER_SW4A1_2", + "CFG_CENTER_FAN7_2", + "CFG_CENTER_ER1BEG1_0", + "CFG_CENTER_IMUX46_5", + "CFG_CENTER_IMUX37_9", + "CFG_CENTER_BYP3_0", + "CFG_CENTER_IMUX31_8", + "CFG_CENTER_WW2END0_3", + "CFG_CENTER_WL1END0_5", + "CFG_CENTER_WW4C0_5", + "CFG_CENTER_LOGIC_OUTS_B18_5", + "CFG_CENTER_LH6_0", + "CFG_CENTER_SW4END2_1", + "CFG_CENTER_LH11_8", + "CFG_CENTER_LOGIC_OUTS_B23_1", + "CFG_CENTER_WW4A1_7", + "CFG_CENTER_EE4B1_4", + "CFG_CENTER_NE4C1_2", + "CFG_CENTER_BYP0_0", + "CFG_CENTER_ER1BEG0_9", + "CFG_CENTER_NE4C0_6", + "CFG_CENTER_EE4C3_2", + "CFG_CENTER_WW2END0_2", + "CFG_CENTER_EE4BEG0_3", + "CFG_CENTER_SW2A1_9", + "CFG_CENTER_WW4END0_7", + "CFG_CENTER_SW2A1_6", + "CFG_CENTER_EE2BEG0_5", + "CFG_CENTER_SE4BEG1_1", + "CFG_CENTER_EFUSE_USR_EFUSEUSR26", + "CFG_CENTER_WW2END1_2", + "CFG_CENTER_WW4B3_7", + "CFG_CENTER_SW4END0_9", + "CFG_CENTER_WR1END1_4", + "CFG_CENTER_NW4END1_1", + "CFG_CENTER_WW4C3_9", + "CFG_CENTER_NW2A2_8", + "CFG_CENTER_SE4C3_6", + "CFG_CENTER_EFUSE_USR_EFUSEUSR20", + "CFG_CENTER_ER1BEG3_2", + "CFG_CENTER_LH6_5", + "CFG_CENTER_LH6_4", + "CFG_CENTER_WW4B2_4", + "CFG_CENTER_IMUX33_7", + "CFG_CENTER_BYP1_0", + "CFG_CENTER_ER1BEG2_0", + "CFG_CENTER_EE4A1_2", + "CFG_CENTER_WW4END2_6", + "CFG_CENTER_LOGIC_OUTS_B10_3", + "CFG_CENTER_WL1END2_2", + "CFG_CENTER_IMUX5_3", + "CFG_CENTER_LH9_6", + "CFG_CENTER_IMUX19_7", + "CFG_CENTER_SE4BEG1_6", + "CFG_CENTER_SW4A1_6", + "CFG_CENTER_SW4A1_0", + "CFG_CENTER_NE4C1_7", + "CFG_CENTER_WW4A1_8", + "CFG_CENTER_LH8_5", + "CFG_CENTER_IMUX37_1", + "CFG_CENTER_LH2_4", + "CFG_CENTER_LOGIC_OUTS_B5_8", + "CFG_CENTER_FAN5_3", + "CFG_CENTER_IMUX40_5", + "CFG_CENTER_WW4END0_0", + "CFG_CENTER_CLK1_2", + "CFG_CENTER_IMUX21_4", + "CFG_CENTER_NE4C3_2", + "CFG_CENTER_BLOCK_OUTS_B0_9", + "CFG_CENTER_IMUX17_2", + "CFG_CENTER_IMUX23_2", + "CFG_CENTER_IMUX6_7", + "CFG_CENTER_IMUX20_5", + "CFG_CENTER_WL1END2_3", + "CFG_CENTER_LH4_6", + "CFG_CENTER_WL1END2_7", + "CFG_CENTER_EFUSE_USR_EFUSEUSR24", + "CFG_CENTER_NW4END1_2", + "CFG_CENTER_SW2A0_3", + "CFG_CENTER_BLOCK_OUTS_B0_5", + "CFG_CENTER_LH8_7", + "CFG_CENTER_LOGIC_OUTS_B1_7", + "CFG_CENTER_IMUX32_0", + "CFG_CENTER_NE4C2_0", + "CFG_CENTER_BYP2_5", + "CFG_CENTER_IMUX0_3", + "CFG_CENTER_LOGIC_OUTS_B0_5", + "CFG_CENTER_NE4C1_5", + "CFG_CENTER_IMUX31_2", + "CFG_CENTER_SE4C3_1", + "CFG_CENTER_BLOCK_OUTS_B3_1", + "CFG_CENTER_FAN5_6", + "CFG_CENTER_WW4A3_2", + "CFG_CENTER_BYP5_1", + "CFG_CENTER_WW4B2_9", + "CFG_CENTER_BLOCK_OUTS_B2_8", + "CFG_CENTER_LOGIC_OUTS_B23_9", + "CFG_CENTER_LH3_6", + "CFG_CENTER_LOGIC_OUTS_B6_0", + "CFG_CENTER_IMUX8_0", + "CFG_CENTER_EE4A0_7", + "CFG_CENTER_WW4B0_4", + "CFG_CENTER_BYP2_3", + "CFG_CENTER_IMUX13_8", + "CFG_CENTER_WW4END1_3", + "CFG_CENTER_WR1END0_1", + "CFG_CENTER_SW4A3_3", + "CFG_CENTER_EFUSE_USR_EFUSEUSR19", + "CFG_CENTER_IMUX34_1", + "CFG_CENTER_ER1BEG2_1", + "CFG_CENTER_CTRL0_3", + "CFG_CENTER_IMUX39_8", + "CFG_CENTER_EE2BEG0_6", + "CFG_CENTER_LOGIC_OUTS_B20_5", + "CFG_CENTER_LH3_8", + "CFG_CENTER_FAN3_9", + "CFG_CENTER_SE4BEG3_6", + "CFG_CENTER_EE2A1_0", + "CFG_CENTER_SE4BEG1_9", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA15", + "CFG_CENTER_IMUX17_0", + "CFG_CENTER_SW4END1_8", + "CFG_CENTER_LH11_3", + "CFG_CENTER_SW4END1_3", + "CFG_CENTER_WL1END2_0", + "CFG_CENTER_EE4BEG1_7", + "CFG_CENTER_IMUX28_9", + "CFG_CENTER_NW4END2_4", + "CFG_CENTER_WW4B1_9", + "CFG_CENTER_SE4BEG3_5", + "CFG_CENTER_NW4A1_9", + "CFG_CENTER_WW2A2_8", + "CFG_CENTER_SW4A3_4", + "CFG_CENTER_EE4A2_6", + "CFG_CENTER_EE2A2_2", + "CFG_CENTER_LOGIC_OUTS_B5_0", + "CFG_CENTER_NW4A2_1", + "CFG_CENTER_SE4BEG1_0", + "CFG_CENTER_NE2A0_9", + "CFG_CENTER_IMUX41_9", + "CFG_CENTER_EE4A2_4", + "CFG_CENTER_IMUX12_2", + "CFG_CENTER_IMUX30_6", + "CFG_CENTER_FAN2_7", + "CFG_CENTER_EE4A2_3", + "CFG_CENTER_EL1BEG2_4", + "CFG_CENTER_WW2A2_5", + "CFG_CENTER_WW2A3_9", + "CFG_CENTER_WW2END0_9", + "CFG_CENTER_IMUX35_3", + "CFG_CENTER_IMUX29_0", + "CFG_CENTER_SW4A1_7", + "CFG_CENTER_LOGIC_OUTS_B9_2", + "CFG_CENTER_SW4A3_2", + "CFG_CENTER_EE2BEG1_1", + "CFG_CENTER_SE4C3_8", + "CFG_CENTER_LH1_7", + "CFG_CENTER_LOGIC_OUTS_B15_8", + "CFG_CENTER_SW2A1_7", + "CFG_CENTER_IMUX11_9", + "CFG_CENTER_EFUSE_USR_EFUSEUSR6", + "CFG_CENTER_IMUX28_3", + "CFG_CENTER_LOGIC_OUTS_B19_3", + "CFG_CENTER_SE2A3_4", + "CFG_CENTER_NE2A0_4", + "CFG_CENTER_WW4C2_9", + "CFG_CENTER_EE4BEG2_1", + "CFG_CENTER_SE4C0_3", + "CFG_CENTER_NW4END1_9", + "CFG_CENTER_SW4A0_9", + "CFG_CENTER_EFUSE_USR_EFUSEUSR28", + "CFG_CENTER_SE4C2_7", + "CFG_CENTER_WW4C0_9", + "CFG_CENTER_EL1BEG3_0", + "CFG_CENTER_EE2BEG3_3", + "CFG_CENTER_IMUX34_7", + "CFG_CENTER_NE4C3_9", + "CFG_CENTER_FAN4_5", + "CFG_CENTER_WW4C0_7", + "CFG_CENTER_NE2A2_3", + "CFG_CENTER_TOP_ICAP1_CLK", + "CFG_CENTER_FAN7_0", + "CFG_CENTER_WW4A3_9", + "CFG_CENTER_WW4C1_1", + "CFG_CENTER_EE4BEG3_2", + "CFG_CENTER_WW4C2_1", + "CFG_CENTER_LOGIC_OUTS_B9_8", + "CFG_CENTER_FAN2_4", + "CFG_CENTER_FAN5_5", + "CFG_CENTER_FAN6_4", + "CFG_CENTER_NE2A3_7", + "CFG_CENTER_EE4C3_7", + "CFG_CENTER_WW2A2_1", + "CFG_CENTER_LOGIC_OUTS_B12_6", + "CFG_CENTER_IMUX1_2", + "CFG_CENTER_LOGIC_OUTS_B12_5", + "CFG_CENTER_IMUX6_2", + "CFG_CENTER_CLK1_7", + "CFG_CENTER_SE4C0_4", + "CFG_CENTER_IMUX7_7", + "CFG_CENTER_NW4A1_8", + "CFG_CENTER_LOGIC_OUTS_B11_6", + "CFG_CENTER_NE2A0_5", + "CFG_CENTER_IMUX30_9", + "CFG_CENTER_SE4BEG0_5", + "CFG_CENTER_EE4C1_6", + "CFG_CENTER_IMUX6_5", + "CFG_CENTER_EE2A3_4", + "CFG_CENTER_FAN7_5", + "CFG_CENTER_SE2A2_9", + "CFG_CENTER_LOGIC_OUTS_B12_4", + "CFG_CENTER_BLOCK_OUTS_B1_9", + "CFG_CENTER_EE2A0_2", + "CFG_CENTER_IMUX15_2", + "CFG_CENTER_EE4BEG1_9", + "CFG_CENTER_FAN7_6", + "CFG_CENTER_NE4BEG0_9", + "CFG_CENTER_EE4B1_7", + "CFG_CENTER_WW4A1_5", + "CFG_CENTER_LH3_4", + "CFG_CENTER_WW2END2_0", + "CFG_CENTER_LOGIC_OUTS_B22_7", + "CFG_CENTER_LOGIC_OUTS_B10_6", + "CFG_CENTER_IMUX20_7", + "CFG_CENTER_LOGIC_OUTS_B16_2", + "CFG_CENTER_WL1END3_0", + "CFG_CENTER_LOGIC_OUTS_B12_0", + "CFG_CENTER_BYP1_6", + "CFG_CENTER_NE2A1_4", + "CFG_CENTER_WL1END1_2", + "CFG_CENTER_WL1END0_4", + "CFG_CENTER_EL1BEG3_5", + "CFG_CENTER_NW2A0_5", + "CFG_CENTER_NE4BEG2_3", + "CFG_CENTER_IMUX46_7", + "CFG_CENTER_WW2A0_4", + "CFG_CENTER_IMUX47_7", + "CFG_CENTER_IMUX36_2", + "CFG_CENTER_NW4A2_0", + "CFG_CENTER_BYP0_4", + "CFG_CENTER_NE4BEG1_1", + "CFG_CENTER_IMUX44_6", + "CFG_CENTER_SW4END2_9", + "CFG_CENTER_IMUX0_6", + "CFG_CENTER_EE2A2_1", + "CFG_CENTER_SW4END0_3", + "CFG_CENTER_WL1END0_6", + "CFG_CENTER_EE2A2_7", + "CFG_CENTER_IMUX31_3", + "CFG_CENTER_LH4_7", + "CFG_CENTER_IMUX0_9", + "CFG_CENTER_SE4C2_8", + "CFG_CENTER_LOGIC_OUTS_B18_8", + "CFG_CENTER_WW2END1_8", + "CFG_CENTER_IMUX6_4", + "CFG_CENTER_LOGIC_OUTS_B12_9", + "CFG_CENTER_IMUX20_1", + "CFG_CENTER_NW4END3_1", + "CFG_CENTER_LH11_5", + "CFG_CENTER_LOGIC_OUTS_B2_0", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA18", + "CFG_CENTER_SE2A0_0", + "CFG_CENTER_SE4C3_3", + "CFG_CENTER_WW4C1_7", + "CFG_CENTER_SE4BEG0_9", + "CFG_CENTER_EE4B3_0", + "CFG_CENTER_NE4C0_2", + "CFG_CENTER_IMUX28_0", + "CFG_CENTER_SE4BEG1_3", + "CFG_CENTER_EE2BEG3_1", + "CFG_CENTER_EE4C1_0", + "CFG_CENTER_WW4C0_1", + "CFG_CENTER_LOGIC_OUTS_B16_6", + "CFG_CENTER_IMUX45_6", + "CFG_CENTER_EE4C1_4", + "CFG_CENTER_IMUX27_8", + "CFG_CENTER_SW4A2_4", + "CFG_CENTER_EE4BEG3_0", + "CFG_CENTER_LOGIC_OUTS_B19_7", + "CFG_CENTER_EE2A3_3", + "CFG_CENTER_EE4BEG1_5", + "CFG_CENTER_BYP4_2", + "CFG_CENTER_BYP1_4", + "CFG_CENTER_BYP4_3", + "CFG_CENTER_ER1BEG2_3", + "CFG_CENTER_IMUX25_2", + "CFG_CENTER_IMUX4_1", + "CFG_CENTER_LH9_2", + "CFG_CENTER_SW2A2_3", + "CFG_CENTER_IMUX26_7", + "CFG_CENTER_BYP0_2", + "CFG_CENTER_LOGIC_OUTS_B15_1", + "CFG_CENTER_LOGIC_OUTS_B21_0", + "CFG_CENTER_IMUX10_6", + "CFG_CENTER_BYP5_2", + "CFG_CENTER_LH1_5", + "CFG_CENTER_NW2A2_1", + "CFG_CENTER_WW4A3_8", + "CFG_CENTER_WW4B0_0", + "CFG_CENTER_IMUX5_5", + "CFG_CENTER_IMUX29_5", + "CFG_CENTER_WR1END0_3", + "CFG_CENTER_LOGIC_OUTS_B16_4", + "CFG_CENTER_IMUX16_5", + "CFG_CENTER_LOGIC_OUTS_B12_2", + "CFG_CENTER_SW2A1_3", + "CFG_CENTER_SE2A1_9", + "CFG_CENTER_LOGIC_OUTS_B5_5", + "CFG_CENTER_EE4A2_0", + "CFG_CENTER_WL1END1_6", + "CFG_CENTER_LOGIC_OUTS_B12_8", + "CFG_CENTER_NE4C2_7", + "CFG_CENTER_SW4A1_1", + "CFG_CENTER_FAN7_3", + "CFG_CENTER_EFUSE_USR_EFUSEUSR25", + "CFG_CENTER_WW2A2_7", + "CFG_CENTER_CLK0_7", + "CFG_CENTER_SE4BEG3_3", + "CFG_CENTER_ER1BEG1_8", + "CFG_CENTER_IMUX45_5", + "CFG_CENTER_LOGIC_OUTS_B7_7", + "CFG_CENTER_NE2A3_8", + "CFG_CENTER_IMUX4_2", + "CFG_CENTER_WW2A3_8", + "CFG_CENTER_SW2A3_6", + "CFG_CENTER_EL1BEG3_2", + "CFG_CENTER_BLOCK_OUTS_B3_6", + "CFG_CENTER_FAN1_5", + "CFG_CENTER_LOGIC_OUTS_B10_5", + "CFG_CENTER_IMUX8_8", + "CFG_CENTER_WW2A3_4", + "CFG_CENTER_NE2A1_2", + "CFG_CENTER_WW4B0_5", + "CFG_CENTER_BYP2_7", + "CFG_CENTER_IMUX7_1", + "CFG_CENTER_WW4A3_5", + "CFG_CENTER_ER1BEG3_4", + "CFG_CENTER_BYP5_6", + "CFG_CENTER_EE4B3_1", + "CFG_CENTER_LOGIC_OUTS_B10_7", + "CFG_CENTER_NE4BEG1_7", + "CFG_CENTER_IMUX18_8", + "CFG_CENTER_EE4A0_3", + "CFG_CENTER_BLOCK_OUTS_B2_3", + "CFG_CENTER_WW4C2_7", + "CFG_CENTER_LOGIC_OUTS_B22_6", + "CFG_CENTER_IMUX25_5", + "CFG_CENTER_LOGIC_OUTS_B14_6", + "CFG_CENTER_SE4C1_3", + "CFG_CENTER_LOGIC_OUTS_B9_1", + "CFG_CENTER_EE2BEG2_1", + "CFG_CENTER_WW4END3_2", + "CFG_CENTER_BYP4_0", + "CFG_CENTER_IMUX24_7", + "CFG_CENTER_IMUX35_1", + "CFG_CENTER_EE4C0_2", + "CFG_CENTER_WW4B1_0", + "CFG_CENTER_WR1END2_5", + "CFG_CENTER_BYP2_6", + "CFG_CENTER_WW4END3_1", + "CFG_CENTER_NW2A3_9", + "CFG_CENTER_LOGIC_OUTS_B20_6", + "CFG_CENTER_IMUX20_0", + "CFG_CENTER_IMUX15_3", + "CFG_CENTER_WW4B2_6", + "CFG_CENTER_EE4A0_4", + "CFG_CENTER_EE2A1_8", + "CFG_CENTER_SE2A2_7", + "CFG_CENTER_NE4C1_6", + "CFG_CENTER_FAN6_9", + "CFG_CENTER_NE4BEG3_5", + "CFG_CENTER_LOGIC_OUTS_B21_3", + "CFG_CENTER_SW2A1_1", + "CFG_CENTER_LH3_7", + "CFG_CENTER_IMUX12_3", + "CFG_CENTER_WW2A1_4", + "CFG_CENTER_LH10_7", + "CFG_CENTER_EE2A2_4", + "CFG_CENTER_EE4A2_9", + "CFG_CENTER_WL1END3_7", + "CFG_CENTER_NW2A3_7", + "CFG_CENTER_EE4BEG3_8", + "CFG_CENTER_SW2A1_0", + "CFG_CENTER_EFUSE_USR_EFUSEUSR1", + "CFG_CENTER_LOGIC_OUTS_B1_4", + "CFG_CENTER_BYP4_7", + "CFG_CENTER_NE2A1_1", + "CFG_CENTER_NW2A3_8", + "CFG_CENTER_EL1BEG0_1", + "CFG_CENTER_SE4C0_7", + "CFG_CENTER_EE4B1_1", + "CFG_CENTER_ER1BEG2_4", + "CFG_CENTER_NE4C0_4", + "CFG_CENTER_NW4A0_7", + "CFG_CENTER_IMUX9_8", + "CFG_CENTER_WW4C1_9", + "CFG_CENTER_LOGIC_OUTS_B23_7", + "CFG_CENTER_CTRL1_2", + "CFG_CENTER_IMUX10_1", + "CFG_CENTER_IMUX31_0", + "CFG_CENTER_ER1BEG3_9", + "CFG_CENTER_LOGIC_OUTS_B18_3", + "CFG_CENTER_SW4END2_3", + "CFG_CENTER_WW4C1_8", + "CFG_CENTER_LOGIC_OUTS_B13_2", + "CFG_CENTER_SW4A0_2", + "CFG_CENTER_WW2A0_2", + "CFG_CENTER_WW4C0_0", + "CFG_CENTER_LOGIC_OUTS_B7_5", + "CFG_CENTER_IMUX41_1", + "CFG_CENTER_IMUX16_1", + "CFG_CENTER_NE2A2_2", + "CFG_CENTER_SE2A3_0", + "CFG_CENTER_IMUX14_1", + "CFG_CENTER_WW4B3_3", + "CFG_CENTER_IMUX30_7", + "CFG_CENTER_SE4BEG3_1", + "CFG_CENTER_LOGIC_OUTS_B14_1", + "CFG_CENTER_SW4A1_8", + "CFG_CENTER_LH4_1", + "CFG_CENTER_BYP0_8", + "CFG_CENTER_WL1END3_1", + "CFG_CENTER_EE4C2_7", + "CFG_CENTER_FAN1_0", + "CFG_CENTER_LOGIC_OUTS_B9_6", + "CFG_CENTER_SE4C0_8", + "CFG_CENTER_WR1END1_5", + "CFG_CENTER_SE4BEG3_8", + "CFG_CENTER_ER1BEG3_0", + "CFG_CENTER_IMUX37_8", + "CFG_CENTER_WW4C3_3", + "CFG_CENTER_NW2A2_0", + "CFG_CENTER_IMUX11_7", + "CFG_CENTER_LH3_1", + "CFG_CENTER_EE4A1_1", + "CFG_CENTER_LH3_9", + "CFG_CENTER_WW4B3_5", + "CFG_CENTER_IMUX46_9", + "CFG_CENTER_WL1END2_4", + "CFG_CENTER_WW2END0_6", + "CFG_CENTER_BYP6_9", + "CFG_CENTER_LH10_6", + "CFG_CENTER_LH2_0", + "CFG_CENTER_IMUX35_6", + "CFG_CENTER_IMUX46_2", + "CFG_CENTER_BYP6_6", + "CFG_CENTER_WW4END2_7", + "CFG_CENTER_LOGIC_OUTS_B16_1", + "CFG_CENTER_WR1END0_4", + "CFG_CENTER_EE2BEG2_3", + "CFG_CENTER_EE4C0_1", + "CFG_CENTER_NW4A2_3", + "CFG_CENTER_LOGIC_OUTS_B4_6", + "CFG_CENTER_EE4BEG3_7", + "CFG_CENTER_SW2A2_9", + "CFG_CENTER_SE4BEG1_7", + "CFG_CENTER_CLK1_3", + "CFG_CENTER_IMUX40_1", + "CFG_CENTER_NW4A1_6", + "CFG_CENTER_WW4C0_8", + "CFG_CENTER_SE2A1_6", + "CFG_CENTER_IMUX13_7", + "CFG_CENTER_LOGIC_OUTS_B19_8", + "CFG_CENTER_SE2A0_8", + "CFG_CENTER_NW4END0_3", + "CFG_CENTER_WW4B1_7", + "CFG_CENTER_LH9_3", + "CFG_CENTER_NW4END3_2", + "CFG_CENTER_FAN5_0", + "CFG_CENTER_CLK0_9", + "CFG_CENTER_IMUX45_1", + "CFG_CENTER_NW4A2_9", + "CFG_CENTER_IMUX42_7", + "CFG_CENTER_IMUX8_4", + "CFG_CENTER_WW2END0_8", + "CFG_CENTER_LOGIC_OUTS_B12_1", + "CFG_CENTER_IMUX38_1", + "CFG_CENTER_WL1END1_7", + "CFG_CENTER_BYP2_2", + "CFG_CENTER_SW4A1_4", + "CFG_CENTER_WW4A1_1", + "CFG_CENTER_FAN7_8", + "CFG_CENTER_NW2A2_4", + "CFG_CENTER_IMUX14_2", + "CFG_CENTER_LOGIC_OUTS_B4_9", + "CFG_CENTER_WW2A2_0", + "CFG_CENTER_IMUX45_2", + "CFG_CENTER_WW4A2_1", + "CFG_CENTER_SE2A2_2", + "CFG_CENTER_CLK0_4", + "CFG_CENTER_SE4C2_0", + "CFG_CENTER_LOGIC_OUTS_B6_6", + "CFG_CENTER_LOGIC_OUTS_B8_5", + "CFG_CENTER_NE4BEG3_7", + "CFG_CENTER_SE2A0_5", + "CFG_CENTER_LH8_8", + "CFG_CENTER_WW4B1_3", + "CFG_CENTER_SE2A2_1", + "CFG_CENTER_EE2A0_5", + "CFG_CENTER_IMUX25_8", + "CFG_CENTER_EE2A1_2", + "CFG_CENTER_BYP6_3", + "CFG_CENTER_IMUX37_2", + "CFG_CENTER_SW2A1_4", + "CFG_CENTER_IMUX23_7", + "CFG_CENTER_FAN6_8", + "CFG_CENTER_NW2A3_3", + "CFG_CENTER_IMUX25_9", + "CFG_CENTER_WL1END0_2", + "CFG_CENTER_WW4B3_6", + "CFG_CENTER_EL1BEG0_3", + "CFG_CENTER_BLOCK_OUTS_B0_2", + "CFG_CENTER_NE2A3_2", + "CFG_CENTER_WR1END2_2", + "CFG_CENTER_WW2A0_7", + "CFG_CENTER_FAN3_0", + "CFG_CENTER_WW2END2_1", + "CFG_CENTER_EE4BEG1_0", + "CFG_CENTER_FAN2_6", + "CFG_CENTER_WL1END0_7", + "CFG_CENTER_FAN6_5", + "CFG_CENTER_WW4END2_2", + "CFG_CENTER_IMUX19_0", + "CFG_CENTER_SW2A3_1", + "CFG_CENTER_BLOCK_OUTS_B0_4", + "CFG_CENTER_EE4BEG0_8", + "CFG_CENTER_NE4BEG3_6", + "CFG_CENTER_WW4A1_6", + "CFG_CENTER_IMUX31_7", + "CFG_CENTER_NW4END3_6", + "CFG_CENTER_SE4BEG3_0", + "CFG_CENTER_WW2A0_0", + "CFG_CENTER_LOGIC_OUTS_B11_8", + "CFG_CENTER_EFUSE_USR_EFUSEUSR29", + "CFG_CENTER_SW2A2_8", + "CFG_CENTER_BYP5_8", + "CFG_CENTER_IMUX40_3", + "CFG_CENTER_WR1END3_2", + "CFG_CENTER_WW4END3_7", + "CFG_CENTER_BYP7_0", + "CFG_CENTER_EE4C2_5", + "CFG_CENTER_LOGIC_OUTS_B1_3", + "CFG_CENTER_IMUX10_2", + "CFG_CENTER_EE2BEG3_2", + "CFG_CENTER_LOGIC_OUTS_B20_4", + "CFG_CENTER_EE4B3_3", + "CFG_CENTER_EE2A0_6", + "CFG_CENTER_IMUX25_7", + "CFG_CENTER_LH5_6", + "CFG_CENTER_IMUX46_6", + "CFG_CENTER_IMUX21_3", + "CFG_CENTER_EFUSE_USR_EFUSEUSR18", + "CFG_CENTER_EE4BEG0_1", + "CFG_CENTER_SE2A2_0", + "CFG_CENTER_EE4BEG1_3", + "CFG_CENTER_EE4BEG2_2", + "CFG_CENTER_IMUX43_8", + "CFG_CENTER_LH6_9", + "CFG_CENTER_IMUX22_4", + "CFG_CENTER_SW4A0_8", + "CFG_CENTER_WW4END0_5", + "CFG_CENTER_EE4B0_6", + "CFG_CENTER_IMUX46_0", + "CFG_CENTER_SW4END2_7", + "CFG_CENTER_WW4A1_4", + "CFG_CENTER_SW4END0_8", + "CFG_CENTER_FAN3_3", + "CFG_CENTER_SE2A2_3", + "CFG_CENTER_IMUX14_6", + "CFG_CENTER_IMUX31_9", + "CFG_CENTER_SE4BEG2_7", + "CFG_CENTER_LH1_0", + "CFG_CENTER_EE4B3_9", + "CFG_CENTER_IMUX29_4", + "CFG_CENTER_NE4BEG2_8", + "CFG_CENTER_WR1END1_1", + "CFG_CENTER_WW2A3_6", + "CFG_CENTER_SE4BEG2_8", + "CFG_CENTER_IMUX16_2", + "CFG_CENTER_LOGIC_OUTS_B17_6", + "CFG_CENTER_EE4C2_3", + "CFG_CENTER_LOGIC_OUTS_B20_0", + "CFG_CENTER_SW4END1_1", + "CFG_CENTER_IMUX6_0", + "CFG_CENTER_SW4A2_2", + "CFG_CENTER_BYP4_9", + "CFG_CENTER_IMUX34_0", + "CFG_CENTER_SW4END3_7", + "CFG_CENTER_WW2END2_2", + "CFG_CENTER_SW2A0_6", + "CFG_CENTER_EE4B2_4", + "CFG_CENTER_SE4C1_4", + "CFG_CENTER_SW2A2_5", + "CFG_CENTER_NE4C3_3", + "CFG_CENTER_SE4C2_9", + "CFG_CENTER_SE4BEG0_3", + "CFG_CENTER_LOGIC_OUTS_B1_0", + "CFG_CENTER_SW4END2_8", + "CFG_CENTER_EE2A3_7", + "CFG_CENTER_IMUX10_5", + "CFG_CENTER_NW4END2_9", + "CFG_CENTER_CTRL1_1", + "CFG_CENTER_LOGIC_OUTS_B8_3", + "CFG_CENTER_EL1BEG2_8", + "CFG_CENTER_EE4C1_8", + "CFG_CENTER_BLOCK_OUTS_B0_6", + "CFG_CENTER_WL1END3_5", + "CFG_CENTER_BYP2_0", + "CFG_CENTER_IMUX10_3", + "CFG_CENTER_LH7_5", + "CFG_CENTER_LH11_6", + "CFG_CENTER_WW4A3_0", + "CFG_CENTER_IMUX11_8", + "CFG_CENTER_EE4BEG3_1", + "CFG_CENTER_IMUX41_6", + "CFG_CENTER_WW4A3_4", + "CFG_CENTER_WR1END0_2", + "CFG_CENTER_CTRL0_4", + "CFG_CENTER_IMUX0_2", + "CFG_CENTER_IMUX33_4", + "CFG_CENTER_LH10_5", + "CFG_CENTER_LOGIC_OUTS_B10_9", + "CFG_CENTER_SE4BEG2_9", + "CFG_CENTER_LOGIC_OUTS_B16_3", + "CFG_CENTER_EE2BEG1_7", + "CFG_CENTER_IMUX20_3", + "CFG_CENTER_IMUX28_4", + "CFG_CENTER_NE4BEG1_4", + "CFG_CENTER_SE4C1_2", + "CFG_CENTER_LOGIC_OUTS_B15_3", + "CFG_CENTER_IMUX26_3", + "CFG_CENTER_LH7_9", + "CFG_CENTER_LOGIC_OUTS_B19_1", + "CFG_CENTER_CLK1_0", + "CFG_CENTER_EE4BEG0_7", + "CFG_CENTER_ER1BEG2_9", + "CFG_CENTER_EE4C3_9", + "CFG_CENTER_BYP4_6", + "CFG_CENTER_NE2A0_3", + "CFG_CENTER_IMUX2_4", + "CFG_CENTER_ER1BEG2_6", + "CFG_CENTER_SE4BEG3_9", + "CFG_CENTER_NE2A3_5", + "CFG_CENTER_WL1END3_2", + "CFG_CENTER_SE4BEG1_4", + "CFG_CENTER_ER1BEG2_2", + "CFG_CENTER_LOGIC_OUTS_B9_7", + "CFG_CENTER_IMUX23_4", + "CFG_CENTER_LOGIC_OUTS_B5_6", + "CFG_CENTER_EL1BEG3_3", + "CFG_CENTER_EE4A1_6", + "CFG_CENTER_WW4B0_3", + "CFG_CENTER_LH8_3", + "CFG_CENTER_NW2A0_4", + "CFG_CENTER_SW2A0_1", + "CFG_CENTER_IMUX5_2", + "CFG_CENTER_EE2A0_3", + "CFG_CENTER_WW4END1_0", + "CFG_CENTER_WL1END3_8", + "CFG_CENTER_BYP1_8", + "CFG_CENTER_IMUX16_0", + "CFG_CENTER_BLOCK_OUTS_B3_0", + "CFG_CENTER_IMUX6_3", + "CFG_CENTER_EE2BEG3_0", + "CFG_CENTER_WW4END0_2", + "CFG_CENTER_EE4BEG0_2", + "CFG_CENTER_IMUX8_3", + "CFG_CENTER_WR1END3_7", + "CFG_CENTER_SW4END2_5", + "CFG_CENTER_NE4BEG3_8", + "CFG_CENTER_NW4A3_7", + "CFG_CENTER_EE4A3_4", + "CFG_CENTER_WW2END3_8", + "CFG_CENTER_WW4END1_9", + "CFG_CENTER_WW4C2_3", + "CFG_CENTER_IMUX42_3", + "CFG_CENTER_LOGIC_OUTS_B13_8", + "CFG_CENTER_NW4END1_8", + "CFG_CENTER_WW4A1_0", + "CFG_CENTER_WW4A0_8", + "CFG_CENTER_LOGIC_OUTS_B2_1", + "CFG_CENTER_IMUX40_6", + "CFG_CENTER_EE2BEG0_4", + "CFG_CENTER_LOGIC_OUTS_B3_7", + "CFG_CENTER_CLK0_5", + "CFG_CENTER_CLK0_2", + "CFG_CENTER_WW4A3_3", + "CFG_CENTER_IMUX1_3", + "CFG_CENTER_IMUX3_6", + "CFG_CENTER_IMUX32_1", + "CFG_CENTER_BYP1_3", + "CFG_CENTER_SE4BEG3_7", + "CFG_CENTER_EL1BEG0_6", + "CFG_CENTER_WL1END1_0", + "CFG_CENTER_BYP7_8", + "CFG_CENTER_IMUX33_3", + "CFG_CENTER_NW2A1_4", + "CFG_CENTER_WW4B2_3", + "CFG_CENTER_EL1BEG1_1", + "CFG_CENTER_LOGIC_OUTS_B11_1", + "CFG_CENTER_BYP2_4", + "CFG_CENTER_IMUX37_6", + "CFG_CENTER_FAN2_0", + "CFG_CENTER_IMUX1_8", + "CFG_CENTER_ER1BEG2_5", + "CFG_CENTER_LOGIC_OUTS_B3_8", + "CFG_CENTER_WW4END1_1", + "CFG_CENTER_BYP3_6", + "CFG_CENTER_EE2A1_6", + "CFG_CENTER_IMUX12_8", + "CFG_CENTER_LH5_2", + "CFG_CENTER_LOGIC_OUTS_B8_4", + "CFG_CENTER_IMUX44_8", + "CFG_CENTER_BLOCK_OUTS_B2_2", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA25", + "CFG_CENTER_IMUX11_3", + "CFG_CENTER_SE2A3_3", + "CFG_CENTER_EL1BEG1_8", + "CFG_CENTER_WW4A0_9", + "CFG_CENTER_IMUX24_3", + "CFG_CENTER_BLOCK_OUTS_B2_9", + "CFG_CENTER_CTRL1_9", + "CFG_CENTER_IMUX39_1", + "CFG_CENTER_NE2A2_1", + "CFG_CENTER_LOGIC_OUTS_B2_9", + "CFG_CENTER_ER1BEG1_3", + "CFG_CENTER_WW4END0_8", + "CFG_CENTER_SW4END3_9", + "CFG_CENTER_WW4END3_3", + "CFG_CENTER_EL1BEG2_9", + "CFG_CENTER_SW4A1_5", + "CFG_CENTER_WW4C3_6", + "CFG_CENTER_WL1END3_6", + "CFG_CENTER_IMUX0_1", + "CFG_CENTER_WR1END1_2", + "CFG_CENTER_WW2END3_0", + "CFG_CENTER_EE2BEG0_9", + "CFG_CENTER_IMUX4_3", + "CFG_CENTER_FAN1_2", + "CFG_CENTER_FAN4_9", + "CFG_CENTER_IMUX17_5", + "CFG_CENTER_LH5_1", + "CFG_CENTER_IMUX3_2", + "CFG_CENTER_EE4C3_5", + "CFG_CENTER_WW2A3_1", + "CFG_CENTER_IMUX10_7", + "CFG_CENTER_WW2A1_0", + "CFG_CENTER_IMUX9_9", + "CFG_CENTER_BYP5_4", + "CFG_CENTER_NW4END2_7", + "CFG_CENTER_WL1END3_9", + "CFG_CENTER_IMUX46_8", + "CFG_CENTER_SE4BEG0_4", + "CFG_CENTER_SW4END0_1", + "CFG_CENTER_SW4END1_4", + "CFG_CENTER_WR1END2_7", + "CFG_CENTER_WL1END2_5", + "CFG_CENTER_NE4C1_1", + "CFG_CENTER_WW2A1_8", + "CFG_CENTER_DNA_PORT_DOUT", + "CFG_CENTER_LOGIC_OUTS_B1_5", + "CFG_CENTER_NE4BEG1_9", + "CFG_CENTER_SW4END3_3", + "CFG_CENTER_NE2A3_9", + "CFG_CENTER_IMUX47_2", + "CFG_CENTER_NE4BEG3_0", + "CFG_CENTER_SW4END3_1", + "CFG_CENTER_EE4B3_2", + "CFG_CENTER_LOGIC_OUTS_B4_4", + "CFG_CENTER_LOGIC_OUTS_B21_1", + "CFG_CENTER_SE4C1_5", + "CFG_CENTER_LH1_8", + "CFG_CENTER_IMUX32_7", + "CFG_CENTER_LOGIC_OUTS_B9_3", + "CFG_CENTER_EE4A0_8", + "CFG_CENTER_NW4A3_9", + "CFG_CENTER_LOGIC_OUTS_B14_4", + "CFG_CENTER_SW4END0_4", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA13", + "CFG_CENTER_IMUX24_0", + "CFG_CENTER_NW4END1_0", + "CFG_CENTER_DNA_PORT_CLK", + "CFG_CENTER_LOGIC_OUTS_B14_3", + "CFG_CENTER_WW4END0_6", + "CFG_CENTER_FAN3_7", + "CFG_CENTER_WW4B0_8", + "CFG_CENTER_WW4A0_5", + "CFG_CENTER_NW2A3_6", + "CFG_CENTER_EE2A3_2", + "CFG_CENTER_EE2A1_3", + "CFG_CENTER_NW4A1_1", + "CFG_CENTER_LH10_0", + "CFG_CENTER_IMUX32_6", + "CFG_CENTER_NE4BEG0_5", + "CFG_CENTER_FAN1_3", + "CFG_CENTER_IMUX13_6", + "CFG_CENTER_NW4END0_0", + "CFG_CENTER_IMUX47_8", + "CFG_CENTER_FAN5_8", + "CFG_CENTER_WW2END3_6", + "CFG_CENTER_LOGIC_OUTS_B23_6", + "CFG_CENTER_NW4A3_2", + "CFG_CENTER_IMUX4_7", + "CFG_CENTER_WW2A1_5", + "CFG_CENTER_NW4END3_8", + "CFG_CENTER_NE2A1_0", + "CFG_CENTER_WW2END1_4", + "CFG_CENTER_BYP7_6", + "CFG_CENTER_NW4A0_6", + "CFG_CENTER_WW2A3_0", + "CFG_CENTER_FAN0_8", + "CFG_CENTER_LOGIC_OUTS_B17_7", + "CFG_CENTER_WW2END1_0", + "CFG_CENTER_LH8_2", + "CFG_CENTER_LOGIC_OUTS_B1_9", + "CFG_CENTER_IMUX33_8", + "CFG_CENTER_LOGIC_OUTS_B17_0", + "CFG_CENTER_IMUX19_4", + "CFG_CENTER_NW4END3_5", + "CFG_CENTER_WR1END3_6", + "CFG_CENTER_NW2A1_3", + "CFG_CENTER_WW4C1_2", + "CFG_CENTER_NW2A1_5", + "CFG_CENTER_EFUSE_USR_EFUSEUSR7", + "CFG_CENTER_LOGIC_OUTS_B19_6", + "CFG_CENTER_LH12_4", + "CFG_CENTER_IMUX31_6", + "CFG_CENTER_WW4B0_1", + "CFG_CENTER_LH10_3", + "CFG_CENTER_IMUX22_3", + "CFG_CENTER_WL1END1_4", + "CFG_CENTER_SW2A3_2", + "CFG_CENTER_LH3_5", + "CFG_CENTER_EE4A3_8", + "CFG_CENTER_WW4C3_1", + "CFG_CENTER_WW2END0_4", + "CFG_CENTER_LOGIC_OUTS_B3_2", + "CFG_CENTER_LOGIC_OUTS_B6_9", + "CFG_CENTER_EL1BEG0_4", + "CFG_CENTER_IMUX18_7", + "CFG_CENTER_SE4C3_5", + "CFG_CENTER_ER1BEG3_3", + "CFG_CENTER_EE4C0_9", + "CFG_CENTER_NW4END1_4", + "CFG_CENTER_NE4BEG0_6", + "CFG_CENTER_IMUX16_9", + "CFG_CENTER_LH6_1", + "CFG_CENTER_LOGIC_OUTS_B5_7", + "CFG_CENTER_EFUSE_USR_EFUSEUSR31", + "CFG_CENTER_LOGIC_OUTS_B22_5", + "CFG_CENTER_SW4END0_7", + "CFG_CENTER_IMUX45_3", + "CFG_CENTER_NW4A2_5", + "CFG_CENTER_EL1BEG2_1", + "CFG_CENTER_IMUX42_4", + "CFG_CENTER_WW4END2_4", + "CFG_CENTER_LH10_2", + "CFG_CENTER_BLOCK_OUTS_B1_1", + "CFG_CENTER_CTRL0_9", + "CFG_CENTER_NE4BEG2_1", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA31", + "CFG_CENTER_NW2A0_9", + "CFG_CENTER_BLOCK_OUTS_B2_6", + "CFG_CENTER_LOGIC_OUTS_B6_3", + "CFG_CENTER_EE2BEG0_8", + "CFG_CENTER_ER1BEG1_5", + "CFG_CENTER_EE4C3_3", + "CFG_CENTER_SE4C1_8", + "CFG_CENTER_WL1END2_9", + "CFG_CENTER_EL1BEG3_8", + "CFG_CENTER_IMUX13_5", + "CFG_CENTER_LH10_1", + "CFG_CENTER_WW2END2_3", + "CFG_CENTER_WR1END3_5", + "CFG_CENTER_BYP5_9", + "CFG_CENTER_WL1END1_3", + "CFG_CENTER_IMUX45_7", + "CFG_CENTER_SW2A0_7", + "CFG_CENTER_IMUX25_6", + "CFG_CENTER_NW4A2_6", + "CFG_CENTER_FAN6_3", + "CFG_CENTER_FAN5_1", + "CFG_CENTER_IMUX42_2", + "CFG_CENTER_ER1BEG0_2", + "CFG_CENTER_BYP5_0", + "CFG_CENTER_IMUX2_7", + "CFG_CENTER_LOGIC_OUTS_B5_1", + "CFG_CENTER_IMUX31_1", + "CFG_CENTER_LH12_1", + "CFG_CENTER_SW2A1_5", + "CFG_CENTER_BLOCK_OUTS_B1_6", + "CFG_CENTER_LH1_4", + "CFG_CENTER_NE2A3_0", + "CFG_CENTER_IMUX16_3", + "CFG_CENTER_BYP1_9", + "CFG_CENTER_WW2END2_5", + "CFG_CENTER_SE4C0_9", + "CFG_CENTER_WW4C1_0", + "CFG_CENTER_EE2A2_5", + "CFG_CENTER_LOGIC_OUTS_B7_8", + "CFG_CENTER_WW4A3_7", + "CFG_CENTER_SE2A1_0", + "CFG_CENTER_IMUX2_1", + "CFG_CENTER_WR1END0_7", + "CFG_CENTER_WW2A1_7", + "CFG_CENTER_LOGIC_OUTS_B7_9", + "CFG_CENTER_LOGIC_OUTS_B18_0", + "CFG_CENTER_WL1END1_1", + "CFG_CENTER_IMUX21_1", + "CFG_CENTER_LOGIC_OUTS_B11_5", + "CFG_CENTER_IMUX7_0", + "CFG_CENTER_EE4C0_8", + "CFG_CENTER_WW4END2_1", + "CFG_CENTER_IMUX13_9", + "CFG_CENTER_LOGIC_OUTS_B7_4", + "CFG_CENTER_SW2A0_2", + "CFG_CENTER_IMUX3_7", + "CFG_CENTER_LOGIC_OUTS_B10_4", + "CFG_CENTER_EE4A1_4", + "CFG_CENTER_SE2A1_1", + "CFG_CENTER_SE4BEG0_1", + "CFG_CENTER_EE4B3_6", + "CFG_CENTER_NE4C2_3", + "CFG_CENTER_LH8_6", + "CFG_CENTER_IMUX47_4", + "CFG_CENTER_EE4C3_0", + "CFG_CENTER_NE4C1_3", + "CFG_CENTER_IMUX29_6", + "CFG_CENTER_IMUX29_9", + "CFG_CENTER_WW2END0_0", + "CFG_CENTER_FAN2_2", + "CFG_CENTER_EE2A3_9", + "CFG_CENTER_IMUX47_6", + "CFG_CENTER_NW4A2_2", + "CFG_CENTER_NE4BEG1_5", + "CFG_CENTER_IMUX47_3", + "CFG_CENTER_LOGIC_OUTS_B6_4", + "CFG_CENTER_NW4END1_5", + "CFG_CENTER_SE4BEG1_5", + "CFG_CENTER_LH5_8", + "CFG_CENTER_SW4END1_7", + "CFG_CENTER_NW4END3_7", + "CFG_CENTER_EE4BEG0_0", + "CFG_CENTER_WW2A0_3", + "CFG_CENTER_NW2A0_6", + "CFG_CENTER_WW4C2_5", + "CFG_CENTER_LH1_6", + "CFG_CENTER_IMUX11_0", + "CFG_CENTER_IMUX44_7", + "CFG_CENTER_IMUX30_1", + "CFG_CENTER_EE2BEG3_8", + "CFG_CENTER_IMUX17_7", + "CFG_CENTER_BLOCK_OUTS_B2_5", + "CFG_CENTER_SW4A2_8", + "CFG_CENTER_SW4END1_2", + "CFG_CENTER_BYP1_7", + "CFG_CENTER_BYP0_7", + "CFG_CENTER_WL1END1_9", + "CFG_CENTER_BYP0_3", + "CFG_CENTER_IMUX21_5", + "CFG_CENTER_SW2A1_8", + "CFG_CENTER_BYP0_1", + "CFG_CENTER_WW4END2_9", + "CFG_CENTER_EL1BEG3_7", + "CFG_CENTER_IMUX17_9", + "CFG_CENTER_WW4END1_2", + "CFG_CENTER_WW4B3_4", + "CFG_CENTER_IMUX23_5", + "CFG_CENTER_SW2A1_2", + "CFG_CENTER_IMUX41_4", + "CFG_CENTER_LH12_6", + "CFG_CENTER_LOGIC_OUTS_B15_6", + "CFG_CENTER_BYP0_6", + "CFG_CENTER_EE4C2_2", + "CFG_CENTER_WW4END3_9", + "CFG_CENTER_NE2A0_7", + "CFG_CENTER_LOGIC_OUTS_B7_2", + "CFG_CENTER_IMUX32_4", + "CFG_CENTER_WW2A0_8", + "CFG_CENTER_WW4C0_4", + "CFG_CENTER_IMUX20_6", + "CFG_CENTER_WR1END3_9", + "CFG_CENTER_SW2A2_1", + "CFG_CENTER_WL1END0_8", + "CFG_CENTER_EE2A2_0", + "CFG_CENTER_IMUX11_5", + "CFG_CENTER_LOGIC_OUTS_B1_2", + "CFG_CENTER_EL1BEG2_6", + "CFG_CENTER_LOGIC_OUTS_B11_4", + "CFG_CENTER_IMUX21_8", + "CFG_CENTER_IMUX9_0", + "CFG_CENTER_BYP6_5", + "CFG_CENTER_WW4END1_7", + "CFG_CENTER_FAN0_7", + "CFG_CENTER_EE4A1_8", + "CFG_CENTER_EE2A3_6", + "CFG_CENTER_SE2A2_6", + "CFG_CENTER_LOGIC_OUTS_B7_3", + "CFG_CENTER_IMUX41_2", + "CFG_CENTER_LOGIC_OUTS_B16_0", + "CFG_CENTER_SW4END0_5", + "CFG_CENTER_IMUX6_9", + "CFG_CENTER_EE2A3_1", + "CFG_CENTER_BYP6_1", + "CFG_CENTER_EE4A2_2", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA19", + "CFG_CENTER_IMUX21_6", + "CFG_CENTER_LOGIC_OUTS_B10_8", + "CFG_CENTER_IMUX22_5", + "CFG_CENTER_LH9_1", + "CFG_CENTER_IMUX36_8", + "CFG_CENTER_LOGIC_OUTS_B9_0", + "CFG_CENTER_NE2A0_0", + "CFG_CENTER_LOGIC_OUTS_B3_3", + "CFG_CENTER_IMUX7_9", + "CFG_CENTER_FAN4_2", + "CFG_CENTER_FAN1_7", + "CFG_CENTER_NW4A3_1", + "CFG_CENTER_LH5_0", + "CFG_CENTER_WW4END3_5", + "CFG_CENTER_IMUX16_6", + "CFG_CENTER_LOGIC_OUTS_B9_5", + "CFG_CENTER_LOGIC_OUTS_B23_4", + "CFG_CENTER_IMUX20_2", + "CFG_CENTER_ER1BEG3_8", + "CFG_CENTER_LOGIC_OUTS_B17_5", + "CFG_CENTER_EE4B2_1", + "CFG_CENTER_IMUX34_3", + "CFG_CENTER_NE4C3_4", + "CFG_CENTER_EL1BEG2_5", + "CFG_CENTER_NW4END3_0", + "CFG_CENTER_IMUX7_5", + "CFG_CENTER_BYP3_1", + "CFG_CENTER_LOGIC_OUTS_B14_8", + "CFG_CENTER_FAN1_8", + "CFG_CENTER_EE4BEG1_4", + "CFG_CENTER_SW2A3_8", + "CFG_CENTER_LOGIC_OUTS_B18_9", + "CFG_CENTER_IMUX14_9", + "CFG_CENTER_EL1BEG1_9", + "CFG_CENTER_NE4BEG1_3", + "CFG_CENTER_NE4BEG0_8", + "CFG_CENTER_BYP0_9", + "CFG_CENTER_IMUX21_0", + "CFG_CENTER_IMUX44_2", + "CFG_CENTER_LOGIC_OUTS_B18_6", + "CFG_CENTER_NE2A2_8", + "CFG_CENTER_IMUX12_4", + "CFG_CENTER_NE4C2_8", + "CFG_CENTER_BYP6_8", + "CFG_CENTER_IMUX31_5", + "CFG_CENTER_IMUX7_6", + "CFG_CENTER_IMUX25_1", + "CFG_CENTER_FAN6_2", + "CFG_CENTER_EE4B1_5", + "CFG_CENTER_NE2A1_7", + "CFG_CENTER_NW2A2_7", + "CFG_CENTER_IMUX0_0", + "CFG_CENTER_EFUSE_USR_EFUSEUSR22", + "CFG_CENTER_NE2A0_1", + "CFG_CENTER_WW4C1_6", + "CFG_CENTER_LH5_9", + "CFG_CENTER_FAN4_3", + "CFG_CENTER_IMUX1_9", + "CFG_CENTER_NW4END2_8", + "CFG_CENTER_EE4B2_8", + "CFG_CENTER_CTRL0_7", + "CFG_CENTER_IMUX12_7", + "CFG_CENTER_SE4C0_0", + "CFG_CENTER_LH11_7", + "CFG_CENTER_LOGIC_OUTS_B2_7", + "CFG_CENTER_IMUX29_3", + "CFG_CENTER_EE4C0_4", + "CFG_CENTER_NW2A0_7", + "CFG_CENTER_BYP4_1", + "CFG_CENTER_WR1END1_9", + "CFG_CENTER_NE2A3_6", + "CFG_CENTER_FAN3_5", + "CFG_CENTER_NW4A1_3", + "CFG_CENTER_IMUX39_9", + "CFG_CENTER_IMUX38_4", + "CFG_CENTER_WW4END1_4", + "CFG_CENTER_CTRL1_7", + "CFG_CENTER_EE4C2_8", + "CFG_CENTER_FAN0_0", + "CFG_CENTER_SE4C3_2", + "CFG_CENTER_WR1END3_1", + "CFG_CENTER_WW2A2_4", + "CFG_CENTER_CTRL0_2", + "CFG_CENTER_LOGIC_OUTS_B1_6", + "CFG_CENTER_WW4C2_6", + "CFG_CENTER_WL1END0_0", + "CFG_CENTER_IMUX44_3", + "CFG_CENTER_LOGIC_OUTS_B2_4", + "CFG_CENTER_CTRL0_8", + "CFG_CENTER_IMUX22_8", + "CFG_CENTER_SW2A3_3", + "CFG_CENTER_WR1END0_6", + "CFG_CENTER_EE4B0_9", + "CFG_CENTER_IMUX19_6", + "CFG_CENTER_IMUX20_8", + "CFG_CENTER_ER1BEG1_4", + "CFG_CENTER_IMUX23_9", + "CFG_CENTER_SW2A2_0", + "CFG_CENTER_IMUX37_7", + "CFG_CENTER_IMUX42_5", + "CFG_CENTER_WW2END3_5", + "CFG_CENTER_WW4B2_0", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA28", + "CFG_CENTER_EE2A3_5", + "CFG_CENTER_NW4END3_3", + "CFG_CENTER_IMUX10_0", + "CFG_CENTER_IMUX32_3", + "CFG_CENTER_IMUX46_3", + "CFG_CENTER_SE4BEG2_4", + "CFG_CENTER_NE4BEG2_2", + "CFG_CENTER_EE4A1_5", + "CFG_CENTER_LOGIC_OUTS_B20_2", + "CFG_CENTER_IMUX39_3", + "CFG_CENTER_NE4BEG0_2", + "CFG_CENTER_SE2A1_7", + "CFG_CENTER_WW4B0_6", + "CFG_CENTER_SW4END0_6", + "CFG_CENTER_SW4A0_5", + "CFG_CENTER_IMUX36_9", + "CFG_CENTER_WW4C2_4", + "CFG_CENTER_WW2END2_9", + "CFG_CENTER_EE4A2_8", + "CFG_CENTER_EFUSE_USR_EFUSEUSR2", + "CFG_CENTER_LOGIC_OUTS_B0_3", + "CFG_CENTER_CTRL1_6", + "CFG_CENTER_ER1BEG0_8", + "CFG_CENTER_SE2A1_5", + "CFG_CENTER_BYP3_2", + "CFG_CENTER_FAN5_7", + "CFG_CENTER_NW2A1_8", + "CFG_CENTER_IMUX40_7", + "CFG_CENTER_LOGIC_OUTS_B23_5", + "CFG_CENTER_NE4C0_7", + "CFG_CENTER_LOGIC_OUTS_B3_5", + "CFG_CENTER_SW4END1_6", + "CFG_CENTER_SW2A2_4", + "CFG_CENTER_SW2A2_7", + "CFG_CENTER_IMUX37_4", + "CFG_CENTER_SW4END2_4", + "CFG_CENTER_LOGIC_OUTS_B13_6", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA30", + "CFG_CENTER_NE2A2_6", + "CFG_CENTER_SE4BEG0_2", + "CFG_CENTER_LOGIC_OUTS_B17_4", + "CFG_CENTER_BLOCK_OUTS_B0_7", + "CFG_CENTER_WW4C3_0", + "CFG_CENTER_EE2A1_9", + "CFG_CENTER_LH4_8", + "CFG_CENTER_IMUX32_9", + "CFG_CENTER_WW4A1_2", + "CFG_CENTER_NE4BEG3_1", + "CFG_CENTER_BYP7_5", + "CFG_CENTER_IMUX28_5", + "CFG_CENTER_FAN0_6", + "CFG_CENTER_BLOCK_OUTS_B0_8", + "CFG_CENTER_NE4BEG2_9", + "CFG_CENTER_NW2A0_2", + "CFG_CENTER_IMUX9_4", + "CFG_CENTER_NW2A3_2", + "CFG_CENTER_NE4C3_0", + "CFG_CENTER_NE4C3_8", + "CFG_CENTER_LH2_1", + "CFG_CENTER_NW2A3_1", + "CFG_CENTER_IMUX47_1", + "CFG_CENTER_IMUX30_0", + "CFG_CENTER_EL1BEG2_0", + "CFG_CENTER_WW4END3_6", + "CFG_CENTER_NE2A3_1", + "CFG_CENTER_NE4BEG0_1", + "CFG_CENTER_NW4END2_0", + "CFG_CENTER_IMUX0_8", + "CFG_CENTER_WW4A3_6", + "CFG_CENTER_IMUX5_4", + "CFG_CENTER_IMUX22_9", + "CFG_CENTER_IMUX27_3", + "CFG_CENTER_IMUX17_6", + "CFG_CENTER_IMUX0_5", + "CFG_CENTER_WW4A2_8", + "CFG_CENTER_EE4B0_7", + "CFG_CENTER_ER1BEG0_6", + "CFG_CENTER_LOGIC_OUTS_B11_9", + "CFG_CENTER_IMUX8_7", + "CFG_CENTER_IMUX17_4", + "CFG_CENTER_NW2A0_1", + "CFG_CENTER_NW2A3_5", + "CFG_CENTER_NE4BEG1_0", + "CFG_CENTER_IMUX8_1", + "CFG_CENTER_NE4C2_2", + "CFG_CENTER_EE4A2_1", + "CFG_CENTER_IMUX7_2", + "CFG_CENTER_IMUX27_5", + "CFG_CENTER_EE2BEG3_5", + "CFG_CENTER_WW4END1_6", + "CFG_CENTER_LH12_5", + "CFG_CENTER_WR1END0_8", + "CFG_CENTER_BYP3_9", + "CFG_CENTER_IMUX9_6", + "CFG_CENTER_EE2BEG3_7", + "CFG_CENTER_EE4A0_1", + "CFG_CENTER_LOGIC_OUTS_B5_2", + "CFG_CENTER_IMUX8_2", + "CFG_CENTER_NE4BEG2_7", + "CFG_CENTER_NW4A2_8", + "CFG_CENTER_LOGIC_OUTS_B21_6", + "CFG_CENTER_FAN0_5", + "CFG_CENTER_FAN7_1", + "CFG_CENTER_CTRL0_5", + "CFG_CENTER_BYP6_7", + "CFG_CENTER_WW2A3_2", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA29", + "CFG_CENTER_NW4A0_9", + "CFG_CENTER_EE2BEG1_5", + "CFG_CENTER_IMUX26_8", + "CFG_CENTER_BYP7_7", + "CFG_CENTER_IMUX23_6", + "CFG_CENTER_BLOCK_OUTS_B1_8", + "CFG_CENTER_EE4A1_9", + "CFG_CENTER_LH12_3", + "CFG_CENTER_LOGIC_OUTS_B8_9", + "CFG_CENTER_IMUX24_9", + "CFG_CENTER_LOGIC_OUTS_B16_5", + "CFG_CENTER_WL1END1_8", + "CFG_CENTER_EL1BEG0_2", + "CFG_CENTER_LOGIC_OUTS_B4_3", + "CFG_CENTER_IMUX35_8", + "CFG_CENTER_SW4END1_0", + "CFG_CENTER_IMUX2_6", + "CFG_CENTER_LH3_0", + "CFG_CENTER_LH2_2", + "CFG_CENTER_LOGIC_OUTS_B6_2", + "CFG_CENTER_IMUX4_8", + "CFG_CENTER_IMUX13_1", + "CFG_CENTER_IMUX20_9", + "CFG_CENTER_LOGIC_OUTS_B18_2", + "CFG_CENTER_WW2END1_9", + "CFG_CENTER_WW4C1_3", + "CFG_CENTER_SW4A3_7", + "CFG_CENTER_IMUX5_8", + "CFG_CENTER_SE4C0_5", + "CFG_CENTER_FAN0_3", + "CFG_CENTER_IMUX6_8", + "CFG_CENTER_SE2A3_6", + "CFG_CENTER_SE4C2_4", + "CFG_CENTER_LH8_4", + "CFG_CENTER_WW4B0_2", + "CFG_CENTER_IMUX46_4", + "CFG_CENTER_EE4A1_3", + "CFG_CENTER_BYP6_4", + "CFG_CENTER_SE4C1_6", + "CFG_CENTER_SW2A3_9", + "CFG_CENTER_LOGIC_OUTS_B16_8", + "CFG_CENTER_LOGIC_OUTS_B21_8", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA20", + "CFG_CENTER_NW4END0_7", + "CFG_CENTER_LH9_7", + "CFG_CENTER_LOGIC_OUTS_B11_7", + "CFG_CENTER_SW4END3_5", + "CFG_CENTER_LOGIC_OUTS_B4_8", + "CFG_CENTER_IMUX1_7", + "CFG_CENTER_EE2A3_0", + "CFG_CENTER_IMUX23_3", + "CFG_CENTER_EE4C0_5", + "CFG_CENTER_LH2_7", + "CFG_CENTER_NE4C2_9", + "CFG_CENTER_SE4C1_7", + "CFG_CENTER_NW4END2_2", + "CFG_CENTER_SE2A3_5", + "CFG_CENTER_IMUX38_9", + "CFG_CENTER_IMUX17_8", + "CFG_CENTER_IMUX32_8", + "CFG_CENTER_LOGIC_OUTS_B15_5", + "CFG_CENTER_NE4BEG1_8", + "CFG_CENTER_IMUX35_4", + "CFG_CENTER_EE2BEG2_5", + "CFG_CENTER_NE4BEG0_7", + "CFG_CENTER_BLOCK_OUTS_B3_8", + "CFG_CENTER_EE2BEG2_4", + "CFG_CENTER_IMUX1_5", + "CFG_CENTER_WW4END3_4", + "CFG_CENTER_IMUX2_9", + "CFG_CENTER_FAN7_7", + "CFG_CENTER_EE4BEG3_3", + "CFG_CENTER_EE4B2_6", + "CFG_CENTER_FAN6_6", + "CFG_CENTER_SW4END0_0", + "CFG_CENTER_WW4B3_1", + "CFG_CENTER_LOGIC_OUTS_B8_8", + "CFG_CENTER_LOGIC_OUTS_B18_1", + "CFG_CENTER_EE4A0_5", + "CFG_CENTER_LOGIC_OUTS_B0_1", + "CFG_CENTER_IMUX42_1", + "CFG_CENTER_NE4BEG0_4", + "CFG_CENTER_NW4A0_4", + "CFG_CENTER_FAN6_0", + "CFG_CENTER_NE2A3_4", + "CFG_CENTER_LH10_8", + "CFG_CENTER_BYP4_5", + "CFG_CENTER_WW4B1_6", + "CFG_CENTER_LH6_8", + "CFG_CENTER_LH9_8", + "CFG_CENTER_EL1BEG0_9", + "CFG_CENTER_IMUX2_5", + "CFG_CENTER_CLK0_3", + "CFG_CENTER_IMUX13_4", + "CFG_CENTER_IMUX35_5", + "CFG_CENTER_LH7_3", + "CFG_CENTER_IMUX40_0", + "CFG_CENTER_NE2A1_6", + "CFG_CENTER_LOGIC_OUTS_B22_4", + "CFG_CENTER_WW4A2_7", + "CFG_CENTER_IMUX1_4", + "CFG_CENTER_WW4C2_0", + "CFG_CENTER_WW4B0_7", + "CFG_CENTER_EE2BEG1_6", + "CFG_CENTER_IMUX9_7", + "CFG_CENTER_IMUX40_9", + "CFG_CENTER_EE4C2_0", + "CFG_CENTER_LOGIC_OUTS_B9_9", + "CFG_CENTER_EE2BEG1_3", + "CFG_CENTER_WR1END3_4", + "CFG_CENTER_WW4A0_6", + "CFG_CENTER_EE4A3_0", + "CFG_CENTER_NE4C3_6", + "CFG_CENTER_WW4A0_2", + "CFG_CENTER_LOGIC_OUTS_B20_9", + "CFG_CENTER_ER1BEG0_5", + "CFG_CENTER_SE2A3_1", + "CFG_CENTER_LH5_4", + "CFG_CENTER_IMUX4_4", + "CFG_CENTER_EE4BEG1_1", + "CFG_CENTER_BYP1_2", + "CFG_CENTER_IMUX37_5", + "CFG_CENTER_EL1BEG2_2", + "CFG_CENTER_SW4A3_5", + "CFG_CENTER_WW4A2_2", + "CFG_CENTER_WW4C2_2", + "CFG_CENTER_SE4BEG3_2", + "CFG_CENTER_LOGIC_OUTS_B20_1", + "CFG_CENTER_LH2_3", + "CFG_CENTER_NW4A1_0", + "CFG_CENTER_LOGIC_OUTS_B14_9", + "CFG_CENTER_WW2END0_7", + "CFG_CENTER_CLK1_9", + "CFG_CENTER_WW2END1_3", + "CFG_CENTER_EE2BEG0_2", + "CFG_CENTER_LH1_2", + "CFG_CENTER_EE4B3_7", + "CFG_CENTER_LOGIC_OUTS_B23_2", + "CFG_CENTER_SW2A3_4", + "CFG_CENTER_ER1BEG1_1", + "CFG_CENTER_EFUSE_USR_EFUSEUSR17", + "CFG_CENTER_EE4A3_3", + "CFG_CENTER_CTRL0_1", + "CFG_CENTER_IMUX7_4", + "CFG_CENTER_IMUX26_6", + "CFG_CENTER_BYP2_1", + "CFG_CENTER_IMUX8_6", + "CFG_CENTER_BLOCK_OUTS_B3_7", + "CFG_CENTER_LOGIC_OUTS_B13_0", + "CFG_CENTER_ER1BEG0_1", + "CFG_CENTER_IMUX4_6", + "CFG_CENTER_EL1BEG0_0", + "CFG_CENTER_EE4C0_7", + "CFG_CENTER_LOGIC_OUTS_B15_9", + "CFG_CENTER_WW4A2_9", + "CFG_CENTER_LOGIC_OUTS_B14_7", + "CFG_CENTER_WW2A2_9", + "CFG_CENTER_CLK0_8", + "CFG_CENTER_IMUX3_8", + "CFG_CENTER_SW4END3_0", + "CFG_CENTER_LH4_0", + "CFG_CENTER_LH2_9", + "CFG_CENTER_NW4A0_0", + "CFG_CENTER_NE2A2_7", + "CFG_CENTER_IMUX42_6", + "CFG_CENTER_LH12_8", + "CFG_CENTER_WR1END1_7", + "CFG_CENTER_IMUX13_2", + "CFG_CENTER_NE4BEG1_2", + "CFG_CENTER_EFUSE_USR_EFUSEUSR14", + "CFG_CENTER_IMUX43_9", + "CFG_CENTER_IMUX5_0", + "CFG_CENTER_IMUX23_0", + "CFG_CENTER_EE4B2_7", + "CFG_CENTER_IMUX21_7", + "CFG_CENTER_SE2A0_7", + "CFG_CENTER_EE4BEG1_8", + "CFG_CENTER_IMUX1_6", + "CFG_CENTER_NW4END0_2", + "CFG_CENTER_WW2A0_5", + "CFG_CENTER_IMUX18_0", + "CFG_CENTER_NW4END2_3", + "CFG_CENTER_SE2A1_4", + "CFG_CENTER_LH9_9", + "CFG_CENTER_SE4C0_6", + "CFG_CENTER_IMUX42_9", + "CFG_CENTER_IMUX14_8", + "CFG_CENTER_WW4B2_7", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA11", + "CFG_CENTER_IMUX16_7", + "CFG_CENTER_FAN4_4", + "CFG_CENTER_NE4BEG2_6", + "CFG_CENTER_IMUX9_3", + "CFG_CENTER_IMUX43_6", + "CFG_CENTER_LH6_6", + "CFG_CENTER_SW4A2_7", + "CFG_CENTER_NE4BEG3_3", + "CFG_CENTER_EL1BEG3_1", + "CFG_CENTER_IMUX9_1", + "CFG_CENTER_EFUSE_USR_EFUSEUSR27", + "CFG_CENTER_LOGIC_OUTS_B7_0", + "CFG_CENTER_NW2A2_9", + "CFG_CENTER_LOGIC_OUTS_B5_4", + "CFG_CENTER_WW4B2_1", + "CFG_CENTER_IMUX33_5", + "CFG_CENTER_WW2A0_1", + "CFG_CENTER_NW4A1_7", + "CFG_CENTER_LOGIC_OUTS_B10_2", + "CFG_CENTER_LOGIC_OUTS_B22_1", + "CFG_CENTER_NW4END0_9", + "CFG_CENTER_WW2A1_1", + "CFG_CENTER_SE4BEG3_4", + "CFG_CENTER_SE4BEG0_0", + "CFG_CENTER_SW2A0_8", + "CFG_CENTER_SW4A2_0", + "CFG_CENTER_WW2END3_4", + "CFG_CENTER_SW4A0_0", + "CFG_CENTER_LOGIC_OUTS_B23_0", + "CFG_CENTER_BLOCK_OUTS_B3_5", + "CFG_CENTER_EE4A3_6", + "CFG_CENTER_IMUX30_8", + "CFG_CENTER_IMUX8_9", + "CFG_CENTER_LH5_5", + "CFG_CENTER_BLOCK_OUTS_B1_3", + "CFG_CENTER_FAN7_9", + "CFG_CENTER_IMUX38_3", + "CFG_CENTER_NE4BEG3_2", + "CFG_CENTER_NW4END0_5", + "CFG_CENTER_EE4C1_7", + "CFG_CENTER_EE4C0_0", + "CFG_CENTER_EE4A0_0", + "CFG_CENTER_IMUX36_3", + "CFG_CENTER_NE2A0_2", + "CFG_CENTER_EE4BEG0_9", + "CFG_CENTER_LH11_4", + "CFG_CENTER_EE4C1_9", + "CFG_CENTER_LOGIC_OUTS_B2_6", + "CFG_CENTER_WL1END1_5", + "CFG_CENTER_EE4C1_5", + "CFG_CENTER_LOGIC_OUTS_B6_1", + "CFG_CENTER_NW2A2_3", + "CFG_CENTER_BYP3_8", + "CFG_CENTER_EE4BEG3_9", + "CFG_CENTER_NW2A0_3", + "CFG_CENTER_BYP7_3", + "CFG_CENTER_BLOCK_OUTS_B1_7", + "CFG_CENTER_EE4BEG1_2", + "CFG_CENTER_FAN6_7", + "CFG_CENTER_EE4C2_6", + "CFG_CENTER_LOGIC_OUTS_B18_4", + "CFG_CENTER_IMUX36_6", + "CFG_CENTER_IMUX6_6", + "CFG_CENTER_IMUX5_1", + "CFG_CENTER_IMUX27_0", + "CFG_CENTER_WR1END2_8", + "CFG_CENTER_SW2A0_9", + "CFG_CENTER_LOGIC_OUTS_B20_7", + "CFG_CENTER_NE2A2_0", + "CFG_CENTER_FAN7_4", + "CFG_CENTER_IMUX34_4", + "CFG_CENTER_WW4C3_8", + "CFG_CENTER_SW4A0_3", + "CFG_CENTER_EE4C0_3", + "CFG_CENTER_EE2A0_9", + "CFG_CENTER_IMUX30_5", + "CFG_CENTER_NW4A3_6", + "CFG_CENTER_LOGIC_OUTS_B4_0", + "CFG_CENTER_EE4A3_5", + "CFG_CENTER_IMUX28_1", + "CFG_CENTER_IMUX18_4", + "CFG_CENTER_FAN1_9", + "CFG_CENTER_LOGIC_OUTS_B3_1", + "CFG_CENTER_NW2A0_0", + "CFG_CENTER_IMUX20_4", + "CFG_CENTER_NW4END0_1", + "CFG_CENTER_IMUX43_2", + "CFG_CENTER_WW4A3_1", + "CFG_CENTER_WW4END3_8", + "CFG_CENTER_BLOCK_OUTS_B2_1", + "CFG_CENTER_LOGIC_OUTS_B0_7", + "CFG_CENTER_FAN1_6", + "CFG_CENTER_EFUSE_USR_EFUSEUSR21", + "CFG_CENTER_EFUSE_USR_EFUSEUSR13", + "CFG_CENTER_IMUX21_9", + "CFG_CENTER_IMUX2_3", + "CFG_CENTER_SE2A2_5", + "CFG_CENTER_EE2A1_4", + "CFG_CENTER_EFUSE_USR_EFUSEUSR3", + "CFG_CENTER_EE4C2_4", + "CFG_CENTER_LOGIC_OUTS_B13_4", + "CFG_CENTER_FAN0_1", + "CFG_CENTER_EE4B0_1", + "CFG_CENTER_IMUX15_4", + "CFG_CENTER_EE4C3_8", + "CFG_CENTER_LOGIC_OUTS_B21_7", + "CFG_CENTER_EE2BEG3_6", + "CFG_CENTER_LH12_2", + "CFG_CENTER_EE4BEG2_9", + "CFG_CENTER_IMUX9_5", + "CFG_CENTER_BLOCK_OUTS_B3_2", + "CFG_CENTER_IMUX44_1", + "CFG_CENTER_IMUX47_9", + "CFG_CENTER_EE4A1_0", + "CFG_CENTER_SW4END0_2", + "CFG_CENTER_IMUX11_1", + "CFG_CENTER_IMUX24_4", + "CFG_CENTER_SE4C2_5", + "CFG_CENTER_IMUX35_0", + "CFG_CENTER_LH11_1", + "CFG_CENTER_BYP3_7", + "CFG_CENTER_IMUX28_8", + "CFG_CENTER_NW4A3_5", + "CFG_CENTER_LH12_9", + "CFG_CENTER_NW4A3_3", + "CFG_CENTER_LOGIC_OUTS_B0_6", + "CFG_CENTER_IMUX10_4", + "CFG_CENTER_BYP3_4", + "CFG_CENTER_IMUX44_4", + "CFG_CENTER_NE2A0_6", + "CFG_CENTER_NE2A1_3", + "CFG_CENTER_SE2A0_1", + "CFG_CENTER_SE4C2_2", + "CFG_CENTER_NE4C2_5", + "CFG_CENTER_LOGIC_OUTS_B13_3", + "CFG_CENTER_EE2BEG2_6", + "CFG_CENTER_IMUX28_2", + "CFG_CENTER_SE2A0_6", + "CFG_CENTER_EFUSE_USR_EFUSEUSR11", + "CFG_CENTER_NW4A0_8", + "CFG_CENTER_WW2A0_6", + "CFG_CENTER_IMUX34_9", + "CFG_CENTER_WR1END2_0", + "CFG_CENTER_WW2END1_5", + "CFG_CENTER_LOGIC_OUTS_B15_7", + "CFG_CENTER_WW4B3_9", + "CFG_CENTER_IMUX35_2", + "CFG_CENTER_CLK0_1", + "CFG_CENTER_FAN1_1", + "CFG_CENTER_LH4_9", + "CFG_CENTER_IMUX9_2", + "CFG_CENTER_EE4B2_9", + "CFG_CENTER_IMUX26_1", + "CFG_CENTER_LOGIC_OUTS_B15_0", + "CFG_CENTER_LOGIC_OUTS_B0_2", + "CFG_CENTER_NE2A1_8", + "CFG_CENTER_EE4B3_8", + "CFG_CENTER_IMUX21_2", + "CFG_CENTER_NE2A2_4", + "CFG_CENTER_SE2A1_2", + "CFG_CENTER_LOGIC_OUTS_B13_1", + "CFG_CENTER_LOGIC_OUTS_B3_9", + "CFG_CENTER_IMUX22_2", + "CFG_CENTER_NW2A1_1", + "CFG_CENTER_IMUX36_0", + "CFG_CENTER_NW4A0_1", + "CFG_CENTER_LOGIC_OUTS_B17_3", + "CFG_CENTER_SE2A3_7", + "CFG_CENTER_EE4BEG2_8", + "CFG_CENTER_LH4_4", + "CFG_CENTER_FAN2_5", + "CFG_CENTER_EE4BEG3_5", + "CFG_CENTER_ER1BEG0_0", + "CFG_CENTER_IMUX12_1", + "CFG_CENTER_IMUX19_1", + "CFG_CENTER_EE2BEG1_2", + "CFG_CENTER_BLOCK_OUTS_B2_7", + "CFG_CENTER_CTRL1_4", + "CFG_CENTER_WW4A0_3", + "CFG_CENTER_BYP4_8", + "CFG_CENTER_WW2A1_6", + "CFG_CENTER_BYP5_3", + "CFG_CENTER_FAN4_8", + "CFG_CENTER_IMUX37_3", + "CFG_CENTER_LOGIC_OUTS_B20_3", + "CFG_CENTER_EFUSE_USR_EFUSEUSR5", + "CFG_CENTER_SW2A3_0", + "CFG_CENTER_EFUSE_USR_EFUSEUSR10", + "CFG_CENTER_WW4C0_2", + "CFG_CENTER_CLK1_4", + "CFG_CENTER_LOGIC_OUTS_B0_4", + "CFG_CENTER_LOGIC_OUTS_B21_9", + "CFG_CENTER_WL1END2_6", + "CFG_CENTER_SE4BEG2_1", + "CFG_CENTER_EE4C1_2", + "CFG_CENTER_NE4BEG1_6", + "CFG_CENTER_BYP6_0", + "CFG_CENTER_SE4BEG2_2", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA22", + "CFG_CENTER_IMUX15_9", + "CFG_CENTER_LOGIC_OUTS_B18_7", + "CFG_CENTER_LH2_8", + "CFG_CENTER_LOGIC_OUTS_B23_8", + "CFG_CENTER_IMUX1_0", + "CFG_CENTER_WW2END3_9", + "CFG_CENTER_WR1END2_6", + "CFG_CENTER_SW4A2_9", + "CFG_CENTER_NW2A1_9", + "CFG_CENTER_WW4A0_4", + "CFG_CENTER_LH7_4", + "CFG_CENTER_WW2END1_1", + "CFG_CENTER_IMUX25_0", + "CFG_CENTER_SE2A3_9", + "CFG_CENTER_IMUX33_0", + "CFG_CENTER_LOGIC_OUTS_B4_7", + "CFG_CENTER_IMUX35_9", + "CFG_CENTER_BLOCK_OUTS_B3_9", + "CFG_CENTER_SW4END3_6", + "CFG_CENTER_LOGIC_OUTS_B20_8", + "CFG_CENTER_WW2A3_3", + "CFG_CENTER_LH10_4", + "CFG_CENTER_SW2A3_7", + "CFG_CENTER_LOGIC_OUTS_B12_3", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA24", + "CFG_CENTER_SW4END2_0", + "CFG_CENTER_SW4A3_9", + "CFG_CENTER_IMUX16_8", + "CFG_CENTER_WW2A1_2", + "CFG_CENTER_WR1END2_1", + "CFG_CENTER_IMUX15_6", + "CFG_CENTER_ER1BEG2_7", + "CFG_CENTER_SE4BEG0_8", + "CFG_CENTER_NW4END0_4", + "CFG_CENTER_EE4C3_6", + "CFG_CENTER_WW4A2_0", + "CFG_CENTER_SW4END3_2", + "CFG_CENTER_SW2A0_0", + "CFG_CENTER_ER1BEG1_6", + "CFG_CENTER_LH4_3", + "CFG_CENTER_NE4C0_1", + "CFG_CENTER_IMUX13_3", + "CFG_CENTER_EE4B2_3", + "CFG_CENTER_IMUX47_0", + "CFG_CENTER_WW4B1_4", + "CFG_CENTER_WL1END0_1", + "CFG_CENTER_BYP7_1", + "CFG_CENTER_EE2A0_0", + "CFG_CENTER_IMUX27_9", + "CFG_CENTER_LOGIC_OUTS_B17_1", + "CFG_CENTER_LOGIC_OUTS_B4_5", + "CFG_CENTER_BYP7_9", + "CFG_CENTER_EE4B3_5", + "CFG_CENTER_LH7_2", + "CFG_CENTER_SW4END1_9", + "CFG_CENTER_EE4B2_5", + "CFG_CENTER_EE4B1_0", + "CFG_CENTER_SW4A1_3", + "CFG_CENTER_IMUX3_0", + "CFG_CENTER_LH10_9", + "CFG_CENTER_SW4A3_6", + "CFG_CENTER_BYP7_2", + "CFG_CENTER_LOGIC_OUTS_B14_0", + "CFG_CENTER_SW2A0_5", + "CFG_CENTER_LOGIC_OUTS_B2_8", + "CFG_CENTER_LH8_0", + "CFG_CENTER_LOGIC_OUTS_B19_0", + "CFG_CENTER_LOGIC_OUTS_B22_9", + "CFG_CENTER_WR1END1_3", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA23", + "CFG_CENTER_FAN2_1", + "CFG_CENTER_IMUX18_1", + "CFG_CENTER_IMUX38_0", + "CFG_CENTER_SW4A3_0", + "CFG_CENTER_IMUX3_1", + "CFG_CENTER_WW4B3_0", + "CFG_CENTER_WW4B0_9", + "CFG_CENTER_NE2A2_9", + "CFG_CENTER_LOGIC_OUTS_B19_4", + "CFG_CENTER_EE4B3_4", + "CFG_CENTER_EL1BEG0_5", + "CFG_CENTER_LH4_2", + "CFG_CENTER_IMUX24_2", + "CFG_CENTER_ER1BEG3_6", + "CFG_CENTER_ER1BEG1_2", + "CFG_CENTER_EE2A1_5", + "CFG_CENTER_LOGIC_OUTS_B12_7", + "CFG_CENTER_EE4A1_7", + "CFG_CENTER_LOGIC_OUTS_B17_8", + "CFG_CENTER_LOGIC_OUTS_B19_2", + "CFG_CENTER_CTRL1_5", + "CFG_CENTER_IMUX2_2", + "CFG_CENTER_ER1BEG1_7", + "CFG_CENTER_SW4A0_1", + "CFG_CENTER_EE2BEG2_8", + "CFG_CENTER_WR1END0_5", + "CFG_CENTER_CLK1_8", + "CFG_CENTER_EE2A2_9", + "CFG_CENTER_EE4BEG2_4", + "CFG_CENTER_LOGIC_OUTS_B17_9", + "CFG_CENTER_LH9_5", + "CFG_CENTER_WW4B2_8", + "CFG_CENTER_IMUX39_0", + "CFG_CENTER_WW2END1_7", + "CFG_CENTER_EE2BEG0_0", + "CFG_CENTER_IMUX41_8", + "CFG_CENTER_CTRL1_3", + "CFG_CENTER_ER1BEG3_7", + "CFG_CENTER_LOGIC_OUTS_B8_6", + "CFG_CENTER_EL1BEG0_8", + "CFG_CENTER_EE2A0_4", + "CFG_CENTER_WW4A0_1", + "CFG_CENTER_IMUX40_2", + "CFG_CENTER_IMUX22_7", + "CFG_CENTER_IMUX43_4", + "CFG_CENTER_IMUX29_1", + "CFG_CENTER_EL1BEG1_5", + "CFG_CENTER_NE4C2_6", + "CFG_CENTER_LOGIC_OUTS_B8_7", + "CFG_CENTER_IMUX45_4", + "CFG_CENTER_NE2A0_8", + "CFG_CENTER_IMUX39_6", + "CFG_CENTER_FAN5_4", + "CFG_CENTER_EE4A2_7", + "CFG_CENTER_IMUX45_9", + "CFG_CENTER_SW4A3_1", + "CFG_CENTER_IMUX27_2", + "CFG_CENTER_NE4C3_5", + "CFG_CENTER_SE2A2_4", + "CFG_CENTER_LOGIC_OUTS_B22_2", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA26", + "CFG_CENTER_NE4BEG2_5", + "CFG_CENTER_WW2A2_2", + "CFG_CENTER_LH1_9", + "CFG_CENTER_SE4BEG1_2", + "CFG_CENTER_WW4B1_1", + "CFG_CENTER_IMUX42_8", + "CFG_CENTER_WW4C3_7", + "CFG_CENTER_NW4END2_1", + "CFG_CENTER_SW4A1_9", + "CFG_CENTER_IMUX27_6", + "CFG_CENTER_IMUX18_5", + "CFG_CENTER_IMUX17_3", + "CFG_CENTER_EE2BEG3_9", + "CFG_CENTER_IMUX14_0", + "CFG_CENTER_EE4BEG2_3", + "CFG_CENTER_BLOCK_OUTS_B3_4", + "CFG_CENTER_EE4A0_2", + "CFG_CENTER_NW4A0_3", + "CFG_CENTER_EE4B1_6", + "CFG_CENTER_NW4END0_8", + "CFG_CENTER_NE4BEG2_0", + "CFG_CENTER_BLOCK_OUTS_B1_4", + "CFG_CENTER_EFUSE_USR_EFUSEUSR23", + "CFG_CENTER_LH7_1", + "CFG_CENTER_IMUX38_8", + "CFG_CENTER_IMUX29_8", + "CFG_CENTER_IMUX24_1", + "CFG_CENTER_SW4A0_7", + "CFG_CENTER_EE4C3_1", + "CFG_CENTER_NE2A1_5", + "CFG_CENTER_IMUX41_7", + "CFG_CENTER_LOGIC_OUTS_B5_9", + "CFG_CENTER_NW4END0_6", + "CFG_CENTER_IMUX30_3", + "CFG_CENTER_WW4C1_4", + "CFG_CENTER_WW4C2_8", + "CFG_CENTER_IMUX26_5", + "CFG_CENTER_NW2A3_4", + "CFG_CENTER_IMUX14_4", + "CFG_CENTER_EFUSE_USR_EFUSEUSR8", + "CFG_CENTER_LOGIC_OUTS_B13_7", + "CFG_CENTER_NE4C0_9", + "CFG_CENTER_NW2A1_6", + "CFG_CENTER_LOGIC_OUTS_B0_8", + "CFG_CENTER_LOGIC_OUTS_B0_0", + "CFG_CENTER_IMUX36_7", + "CFG_CENTER_IMUX38_5", + "CFG_CENTER_LOGIC_OUTS_B15_4", + "CFG_CENTER_EE2A0_7", + "CFG_CENTER_EL1BEG1_4", + "CFG_CENTER_NE4C2_4", + "CFG_CENTER_NW4END1_6", + "CFG_CENTER_IMUX15_1", + "CFG_CENTER_SE2A1_8", + "CFG_CENTER_IMUX26_9", + "CFG_CENTER_EFUSE_USR_EFUSEUSR30", + "CFG_CENTER_FAN0_2", + "CFG_CENTER_WW4A2_5", + "CFG_CENTER_IMUX45_8", + "CFG_CENTER_LOGIC_OUTS_B2_5", + "CFG_CENTER_WW4A1_3", + "CFG_CENTER_CTRL1_8", + "CFG_CENTER_EFUSE_USR_EFUSEUSR16", + "CFG_CENTER_LH12_0", + "CFG_CENTER_WW4B1_8", + "CFG_CENTER_BYP2_9", + "CFG_CENTER_NE2A3_3", + "CFG_CENTER_LOGIC_OUTS_B8_0", + "CFG_CENTER_NE4C3_7", + "CFG_CENTER_LOGIC_OUTS_B3_4", + "CFG_CENTER_SW4A2_3", + "CFG_CENTER_LH7_8", + "CFG_CENTER_NE4BEG2_4", + "CFG_CENTER_IMUX8_5", + "CFG_CENTER_IMUX26_0", + "CFG_CENTER_NW2A2_5", + "CFG_CENTER_NW4A1_4", + "CFG_CENTER_IMUX29_7", + "CFG_CENTER_LOGIC_OUTS_B15_2", + "CFG_CENTER_BYP7_4", + "CFG_CENTER_EE4A2_5", + "CFG_CENTER_BLOCK_OUTS_B1_0", + "CFG_CENTER_LOGIC_OUTS_B1_1", + "CFG_CENTER_IMUX38_7", + "CFG_CENTER_IMUX27_1", + "CFG_CENTER_EFUSE_USR_EFUSEUSR4", + "CFG_CENTER_IMUX37_0", + "CFG_CENTER_IMUX18_9", + "CFG_CENTER_LOGIC_OUTS_B13_5", + "CFG_CENTER_EE4C2_9", + "CFG_CENTER_EL1BEG3_9", + "CFG_CENTER_IMUX15_8", + "CFG_CENTER_SE2A0_2", + "CFG_CENTER_ER1BEG1_9", + "CFG_CENTER_SW2A0_4", + "CFG_CENTER_NE4C0_0", + "CFG_CENTER_FAN1_4", + "CFG_CENTER_LH8_9", + "CFG_CENTER_LH9_4", + "CFG_CENTER_IMUX24_5", + "CFG_CENTER_BLOCK_OUTS_B0_0", + "CFG_CENTER_LH6_7", + "CFG_CENTER_SE4BEG1_8", + "CFG_CENTER_IMUX14_3", + "CFG_CENTER_LH2_5", + "CFG_CENTER_EE4BEG3_4", + "CFG_CENTER_WW4END2_5", + "CFG_CENTER_NW4END1_3", + "CFG_CENTER_WL1END3_3", + "CFG_CENTER_IMUX11_4", + "CFG_CENTER_IMUX19_5", + "CFG_CENTER_LOGIC_OUTS_B6_5", + "CFG_CENTER_EE4A3_7", + "CFG_CENTER_FAN4_1", + "CFG_CENTER_NW2A2_2", + "CFG_CENTER_WW4END1_8", + "CFG_CENTER_IMUX24_8", + "CFG_CENTER_IMUX45_0", + "CFG_CENTER_IMUX33_1", + "CFG_CENTER_CTRL0_6", + "CFG_CENTER_BYP1_5", + "CFG_CENTER_IMUX43_0", + "CFG_CENTER_IMUX33_6", + "CFG_CENTER_WW4B2_2", + "CFG_CENTER_LOGIC_OUTS_B11_2", + "CFG_CENTER_LOGIC_OUTS_B6_8", + "CFG_CENTER_EE4B2_2", + "CFG_CENTER_NW4A2_7", + "CFG_CENTER_IMUX30_2", + "CFG_CENTER_LOGIC_OUTS_B14_5", + "CFG_CENTER_IMUX7_8", + "CFG_CENTER_LOGIC_OUTS_B19_5", + "CFG_CENTER_ER1BEG3_1", + "CFG_CENTER_LOGIC_OUTS_B11_0", + "CFG_CENTER_FAN2_9", + "CFG_CENTER_SE2A0_9", + "CFG_CENTER_WW4B1_2", + "CFG_CENTER_IMUX25_4", + "CFG_CENTER_FAN3_1", + "CFG_CENTER_IMUX10_9", + "CFG_CENTER_IMUX2_8", + "CFG_CENTER_DNA_PORT_SHIFT", + "CFG_CENTER_IMUX39_5", + "CFG_CENTER_IMUX19_2", + "CFG_CENTER_IMUX41_5", + "CFG_CENTER_SW4A2_6", + "CFG_CENTER_IMUX12_6", + "CFG_CENTER_LOGIC_OUTS_B22_8", + "CFG_CENTER_EE4B0_4", + "CFG_CENTER_EE2BEG2_9", + "CFG_CENTER_EE4B0_0", + "CFG_CENTER_EE4BEG2_6", + "CFG_CENTER_IMUX11_6", + "CFG_CENTER_WR1END2_9", + "CFG_CENTER_NW2A0_8", + "CFG_CENTER_EE4BEG1_6", + "CFG_CENTER_DNA_PORT_READ", + "CFG_CENTER_BYP2_8", + "CFG_CENTER_NE4C1_9", + "CFG_CENTER_NE4BEG0_0", + "CFG_CENTER_WW4A0_7", + "CFG_CENTER_NW4A2_4", + "CFG_CENTER_EE2BEG1_9", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA12", + "CFG_CENTER_WW4END0_4", + "CFG_CENTER_SW2A2_6", + "CFG_CENTER_LH4_5", + "CFG_CENTER_WW4END2_0", + "CFG_CENTER_EFUSE_USR_EFUSEUSR12", + "CFG_CENTER_EE2A1_7", + "CFG_CENTER_WW4C3_5", + "CFG_CENTER_BLOCK_OUTS_B1_5", + "CFG_CENTER_EE2BEG2_2", + "CFG_CENTER_LH1_1", + "CFG_CENTER_EL1BEG1_0", + "CFG_CENTER_NW2A1_0", + "CFG_CENTER_CLK0_0", + "CFG_CENTER_LH11_9", + "CFG_CENTER_WW4END0_9", + "CFG_CENTER_EE4BEG2_5", + "CFG_CENTER_WW4END3_0", + "CFG_CENTER_LOGIC_OUTS_B11_3", + "CFG_CENTER_NW4END3_9", + "CFG_CENTER_SW4A0_4", + "CFG_CENTER_IMUX22_0", + "CFG_CENTER_EFUSE_USR_EFUSEUSR0", + "CFG_CENTER_WW4C3_2", + "CFG_CENTER_WR1END1_8", + "CFG_CENTER_WR1END2_3", + "CFG_CENTER_IMUX25_3", + "CFG_CENTER_WW4END2_3", + "CFG_CENTER_WW4A2_6", + "CFG_CENTER_IMUX30_4", + "CFG_CENTER_WW2END3_2", + "CFG_CENTER_SE2A0_3", + "CFG_CENTER_WR1END0_9", + "CFG_CENTER_IMUX32_5", + "CFG_CENTER_SW4END2_2", + "CFG_CENTER_EE2BEG1_8", + "CFG_CENTER_NE2A2_5", + "CFG_CENTER_EE4A3_1", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA16", + "CFG_CENTER_SE4C1_0", + "CFG_CENTER_SE2A2_8", + "CFG_CENTER_EE4A0_6", + "CFG_CENTER_EE4C0_6", + "CFG_CENTER_BYP6_2", + "CFG_CENTER_BLOCK_OUTS_B2_0", + "CFG_CENTER_EE4B1_3", + "CFG_CENTER_EE4BEG2_0", + "CFG_CENTER_SE4C3_0", + "CFG_CENTER_IMUX3_3", + "CFG_CENTER_NW2A1_2", + "CFG_CENTER_FAN3_2", + "CFG_CENTER_FAN0_4", + "CFG_CENTER_NW2A2_6", + "CFG_CENTER_IMUX15_5", + "CFG_CENTER_IMUX34_8", + "CFG_CENTER_NE4BEG0_3", + "CFG_CENTER_IMUX17_1", + "CFG_CENTER_FAN5_9", + "CFG_CENTER_IMUX44_0", + "CFG_CENTER_LOGIC_OUTS_B4_1", + "CFG_CENTER_WR1END1_0", + "CFG_CENTER_IMUX47_5", + "CFG_CENTER_FAN4_6", + "CFG_CENTER_FAN3_8", + "CFG_CENTER_EE4B1_9", + "CFG_CENTER_LOGIC_OUTS_B17_2", + "CFG_CENTER_IMUX23_8", + "CFG_CENTER_IMUX32_2", + "CFG_CENTER_SE4C1_1", + "CFG_CENTER_EE4B0_5", + "CFG_CENTER_EE4C2_1", + "CFG_CENTER_BLOCK_OUTS_B0_3", + "CFG_CENTER_ER1BEG0_4", + "CFG_CENTER_NE4C1_8", + "CFG_CENTER_LH5_7", + "CFG_CENTER_IMUX23_1", + "CFG_CENTER_SE2A1_3", + "CFG_CENTER_SW4END3_8", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA21", + "CFG_CENTER_IMUX41_0", + "CFG_CENTER_WW2A1_3", + "CFG_CENTER_BYP3_3", + "CFG_CENTER_FAN6_1", + "CFG_CENTER_EE2BEG0_3", + "CFG_CENTER_EL1BEG1_3", + "CFG_CENTER_SE2A0_4", + "CFG_CENTER_IMUX36_1", + "CFG_CENTER_LOGIC_OUTS_B5_3", + "CFG_CENTER_IMUX35_7", + "CFG_CENTER_SE4C0_2", + "CFG_CENTER_LOGIC_OUTS_B16_9", + "CFG_CENTER_NE4C0_8", + "CFG_CENTER_SW2A3_5", + "CFG_CENTER_WR1END3_3", + "CFG_CENTER_LOGIC_OUTS_B21_4", + "CFG_CENTER_EE2BEG2_0", + "CFG_CENTER_NE4C3_1", + "CFG_CENTER_EE4B0_8", + "CFG_CENTER_IMUX40_4", + "CFG_CENTER_LOGIC_OUTS_B1_8", + "CFG_CENTER_IMUX5_6", + "CFG_CENTER_CLK0_6", + "CFG_CENTER_IMUX4_5", + "CFG_CENTER_WW4END0_1", + "CFG_CENTER_EL1BEG0_7", + "CFG_CENTER_WL1END2_1", + "CFG_CENTER_IMUX7_3", + "CFG_CENTER_LOGIC_OUTS_B9_4", + "CFG_CENTER_CTRL0_0", + "CFG_CENTER_LOGIC_OUTS_B10_1", + "CFG_CENTER_LOGIC_OUTS_B21_5", + "CFG_CENTER_EL1BEG3_4", + "CFG_CENTER_EE2BEG2_7", + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA17", + "CFG_CENTER_IMUX4_9", + "CFG_CENTER_LH12_7", + "CFG_CENTER_IMUX22_6", + "CFG_CENTER_EE4B1_8", + "CFG_CENTER_FAN2_3", + "CFG_CENTER_SW4A0_6", + "CFG_CENTER_CLK1_6", + "CFG_CENTER_NE4BEG3_4", + "CFG_CENTER_WW4C3_4", + "CFG_CENTER_LOGIC_OUTS_B22_3", + "CFG_CENTER_NW4A0_5", + "CFG_CENTER_FAN4_7", + "CFG_CENTER_EE4C1_3", + "CFG_CENTER_LH6_3", + "CFG_CENTER_LOGIC_OUTS_B0_9", + "CFG_CENTER_IMUX38_2", + "CFG_CENTER_LH11_2", + "CFG_CENTER_IMUX28_7", + "CFG_CENTER_SE4BEG2_0", + "CFG_CENTER_SE2A3_8", + "CFG_CENTER_IMUX43_3", + "CFG_CENTER_IMUX3_4", + "CFG_CENTER_SW4END2_6", + "CFG_CENTER_IMUX5_9", + "CFG_CENTER_LOGIC_OUTS_B7_1", + "CFG_CENTER_SW2A2_2", + "CFG_CENTER_IMUX12_9", + "CFG_CENTER_WL1END2_8", + "CFG_CENTER_WW2A3_5", + "CFG_CENTER_LOGIC_OUTS_B3_6", + "CFG_CENTER_WW4C0_3", + "CFG_CENTER_EE4A3_2", + "CFG_CENTER_LOGIC_OUTS_B21_2", + "CFG_CENTER_BYP1_1", + "CFG_CENTER_WL1END0_9", + "CFG_CENTER_IMUX5_7", + "CFG_CENTER_EE2A0_8", + "CFG_CENTER_WW4END1_5", + "CFG_CENTER_WW4B1_5", + "CFG_CENTER_LOGIC_OUTS_B2_2", + "CFG_CENTER_NW4END3_4", + "CFG_CENTER_IMUX39_4", + "CFG_CENTER_BLOCK_OUTS_B0_1", + "CFG_CENTER_IMUX46_1", + "CFG_CENTER_FAN4_0", + "CFG_CENTER_LH5_3", + "CFG_CENTER_EE2A2_8", + "CFG_CENTER_BYP4_4", + "CFG_CENTER_IMUX43_7", + "CFG_CENTER_BLOCK_OUTS_B1_2", + "CFG_CENTER_NW4A1_2", + "CFG_CENTER_WW2A0_9", + "CFG_CENTER_SW4A2_1", + "CFG_CENTER_FAN3_6", + "CFG_CENTER_EE4BEG0_4", + "CFG_CENTER_WW4END2_8", + "CFG_CENTER_SE4BEG0_6", + "CFG_CENTER_WW4C1_5", + "CFG_CENTER_WW4A2_4", + "CFG_CENTER_EE2BEG1_4", + "CFG_CENTER_SW4A3_8", + "CFG_CENTER_NW2A1_7", + "CFG_CENTER_WR1END3_8", + "CFG_CENTER_IMUX4_0", + "CFG_CENTER_NW4END2_5", + "CFG_CENTER_WW2END0_1", + "CFG_CENTER_WW4END0_3", + "CFG_CENTER_SW4A2_5", + "CFG_CENTER_IMUX19_3", + "CFG_CENTER_IMUX29_2", + "CFG_CENTER_IMUX3_5", + "CFG_CENTER_IMUX43_1", + "CFG_CENTER_WW2END2_4", + "CFG_CENTER_IMUX34_2", + "CFG_CENTER_IMUX10_8", + "CFG_CENTER_EE2BEG0_7", + "CFG_CENTER_IMUX14_5", + "CFG_CENTER_EE2A1_1", + "CFG_CENTER_EFUSE_USR_EFUSEUSR9", + "CFG_CENTER_EE4BEG2_7", + "CFG_CENTER_WW2END3_1", + "CFG_CENTER_CLK1_1", + "CFG_CENTER_SE4C3_7", + "CFG_CENTER_IMUX18_2", + "CFG_CENTER_IMUX36_4", + "CFG_CENTER_LOGIC_OUTS_B10_0", + "CFG_CENTER_WW2END2_7", + "CFG_CENTER_IMUX18_3", + "CFG_CENTER_IMUX26_4", + "CFG_CENTER_EE2A3_8", + "CFG_CENTER_IMUX28_6", + "CFG_CENTER_WW2A2_6", + "CFG_CENTER_IMUX39_2", + "CFG_CENTER_LOGIC_OUTS_B16_7", + "CFG_CENTER_WW2END1_6", + "CFG_CENTER_EE2BEG3_4", + "CFG_CENTER_IMUX44_5", + "CFG_CENTER_IMUX15_7", + "CFG_CENTER_IMUX44_9", + "CFG_CENTER_LOGIC_OUTS_B8_2", + "CFG_CENTER_NE4C2_1", + "CFG_CENTER_BYP5_7", + "CFG_CENTER_IMUX19_9", + "CFG_CENTER_LH6_2", + "CFG_CENTER_TOP_DNA_PORT_CLK", + "CFG_CENTER_NE4C0_5", + "CFG_CENTER_EE4C1_1", + "CFG_CENTER_WW2END3_3", + "CFG_CENTER_NW4A3_4", + "CFG_CENTER_SE4C1_9", + "CFG_CENTER_WL1END3_4", + "CFG_CENTER_SE4C2_3", + "CFG_CENTER_NE4C1_0", + "CFG_CENTER_SE4C2_6", + "CFG_CENTER_WW4B3_8", + "CFG_CENTER_SE4BEG0_7", + "CFG_CENTER_BYP5_5", + "CFG_CENTER_EL1BEG1_2", + "CFG_CENTER_LH2_6", + "CFG_CENTER_IMUX33_2", + "CFG_CENTER_EE2A2_6", + "CFG_CENTER_IMUX19_8", + "CFG_CENTER_NW4A3_8", + "CFG_CENTER_WW4B3_2", + "CFG_CENTER_SE4BEG2_6", + "CFG_CENTER_IMUX27_4", + "CFG_CENTER_IMUX38_6", + "CFG_CENTER_EE2A2_3", + "CFG_CENTER_IMUX26_2", + "CFG_CENTER_SE4C2_1", + "CFG_CENTER_NW2A3_0", + "CFG_CENTER_IMUX36_5" + ], + "tile_type": "CFG_CENTER_TOP", + "sites": [ + { + "site_pins": { + "DIN": "CFG_CENTER_DNA_PORT_DIN", + "CLK": "CFG_CENTER_DNA_PORT_CLK", + "SHIFT": "CFG_CENTER_DNA_PORT_SHIFT", + "DOUT": "CFG_CENTER_DNA_PORT_DOUT", + "READ": "CFG_CENTER_DNA_PORT_READ" + }, + "type": "DNA_PORT", + "prefix": "DNA_PORT", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "EFUSEUSR31": "CFG_CENTER_EFUSE_USR_EFUSEUSR31", + "EFUSEUSR10": "CFG_CENTER_EFUSE_USR_EFUSEUSR10", + "EFUSEUSR6": "CFG_CENTER_EFUSE_USR_EFUSEUSR6", + "EFUSEUSR8": "CFG_CENTER_EFUSE_USR_EFUSEUSR8", + "EFUSEUSR2": "CFG_CENTER_EFUSE_USR_EFUSEUSR2", + "EFUSEUSR1": "CFG_CENTER_EFUSE_USR_EFUSEUSR1", + "EFUSEUSR5": "CFG_CENTER_EFUSE_USR_EFUSEUSR5", + "EFUSEUSR24": "CFG_CENTER_EFUSE_USR_EFUSEUSR24", + "EFUSEUSR29": "CFG_CENTER_EFUSE_USR_EFUSEUSR29", + "EFUSEUSR21": "CFG_CENTER_EFUSE_USR_EFUSEUSR21", + "EFUSEUSR7": "CFG_CENTER_EFUSE_USR_EFUSEUSR7", + "EFUSEUSR28": "CFG_CENTER_EFUSE_USR_EFUSEUSR28", + "EFUSEUSR30": "CFG_CENTER_EFUSE_USR_EFUSEUSR30", + "EFUSEUSR22": "CFG_CENTER_EFUSE_USR_EFUSEUSR22", + "EFUSEUSR13": "CFG_CENTER_EFUSE_USR_EFUSEUSR13", + "EFUSEUSR4": "CFG_CENTER_EFUSE_USR_EFUSEUSR4", + "EFUSEUSR18": "CFG_CENTER_EFUSE_USR_EFUSEUSR18", + "EFUSEUSR11": "CFG_CENTER_EFUSE_USR_EFUSEUSR11", + "EFUSEUSR23": "CFG_CENTER_EFUSE_USR_EFUSEUSR23", + "EFUSEUSR26": "CFG_CENTER_EFUSE_USR_EFUSEUSR26", + "EFUSEUSR27": "CFG_CENTER_EFUSE_USR_EFUSEUSR27", + "EFUSEUSR12": "CFG_CENTER_EFUSE_USR_EFUSEUSR12", + "EFUSEUSR0": "CFG_CENTER_EFUSE_USR_EFUSEUSR0", + "EFUSEUSR16": "CFG_CENTER_EFUSE_USR_EFUSEUSR16", + "EFUSEUSR19": "CFG_CENTER_EFUSE_USR_EFUSEUSR19", + "EFUSEUSR17": "CFG_CENTER_EFUSE_USR_EFUSEUSR17", + "EFUSEUSR20": "CFG_CENTER_EFUSE_USR_EFUSEUSR20", + "EFUSEUSR3": "CFG_CENTER_EFUSE_USR_EFUSEUSR3", + "EFUSEUSR14": "CFG_CENTER_EFUSE_USR_EFUSEUSR14", + "EFUSEUSR9": "CFG_CENTER_EFUSE_USR_EFUSEUSR9", + "EFUSEUSR15": "CFG_CENTER_EFUSE_USR_EFUSEUSR15", + "EFUSEUSR25": "CFG_CENTER_EFUSE_USR_EFUSEUSR25" + }, + "type": "EFUSE_USR", + "prefix": "EFUSE_USR", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLBLL_L.json b/artix7/tile_type_CLBLL_L.json index de8493f..928b670 100644 --- a/artix7/tile_type_CLBLL_L.json +++ b/artix7/tile_type_CLBLL_L.json @@ -1,1449 +1,1449 @@ { - "wires": [ - "CLBLL_SE4BEG2", - "CLBLL_EE2BEG0", - "CLBLL_WW4END0", - "CLBLL_LOGIC_OUTS7", - "CLBLL_LL_A2", - "CLBLL_IMUX19", - "CLBLL_SW4END1", - "CLBLL_IMUX2", - "CLBLL_EE2A2", - "CLBLL_L_B6", - "CLBLL_WW2END2", - "CLBLL_IMUX34", - "CLBLL_IMUX21", - "CLBLL_EE4BEG2", - "CLBLL_EE4A1", - "CLBLL_IMUX18", - "CLBLL_L_DMUX", - "CLBLL_ER1BEG1", - "CLBLL_IMUX25", - "CLBLL_LL_B", - "CLBLL_SE2A2", - "CLBLL_NW4A3", - "CLBLL_L_C5", - "CLBLL_L_C2", - "CLBLL_IMUX44", - "CLBLL_L_CQ", - "CLBLL_BYP6", - "CLBLL_WW4A0", - "CLBLL_LL_C6", - "CLBLL_SE2A1", - "CLBLL_L_D4", - "CLBLL_L_B", - "CLBLL_NE2A1", - "CLBLL_L_A3", - "CLBLL_WW4END1", - "CLBLL_NE4BEG0", - "CLBLL_SE4C3", - "CLBLL_IMUX46", - "CLBLL_IMUX35", - "CLBLL_FAN5", - "CLBLL_ER1BEG2", - "CLBLL_BYP7", - "CLBLL_L_B3", - "CLBLL_SW4END0", - "CLBLL_SE4C2", - "CLBLL_L_B4", - "CLBLL_EE2A0", - "CLBLL_LL_CE", - "CLBLL_NW4A0", - "CLBLL_LOGIC_OUTS13", - "CLBLL_IMUX5", - "CLBLL_SE4BEG1", - "CLBLL_WL1END1", - "CLBLL_MONITOR_P", - "CLBLL_LOGIC_OUTS20", - "CLBLL_EE4B2", - "CLBLL_CTRL0", - "CLBLL_LL_CQ", - "CLBLL_LL_DQ", - "CLBLL_EE4C2", - "CLBLL_LL_COUT", - "CLBLL_BYP5", - "CLBLL_WW4C0", - "CLBLL_IMUX31", - "CLBLL_SE2A0", - "CLBLL_LH6", - "CLBLL_L_CLK", - "CLBLL_NE4C0", - "CLBLL_IMUX11", - "CLBLL_L_C", - "CLBLL_IMUX22", - "CLBLL_FAN6", - "CLBLL_WW4B0", - "CLBLL_FAN3", - "CLBLL_NE4BEG3", - "CLBLL_BYP0", - "CLBLL_L_C6", - "CLBLL_IMUX32", - "CLBLL_LOGIC_OUTS11", - "CLBLL_L_B2", - "CLBLL_IMUX17", - "CLBLL_IMUX41", - "CLBLL_LL_COUT_N", - "CLBLL_EE4A2", - "CLBLL_L_D", - "CLBLL_L_CE", - "CLBLL_LL_BMUX", - "CLBLL_LL_C4", - "CLBLL_IMUX9", - "CLBLL_ER1BEG0", - "CLBLL_LL_AQ", - "CLBLL_NW4END1", - "CLBLL_L_C4", - "CLBLL_LH12", - "CLBLL_NE4C2", - "CLBLL_LL_AX", - "CLBLL_IMUX30", - "CLBLL_EE4A0", - "CLBLL_SE4C1", - "CLBLL_WW2A2", - "CLBLL_LL_DMUX", - "CLBLL_IMUX45", - "CLBLL_IMUX47", - "CLBLL_LL_BQ", - "CLBLL_LL_B5", - "CLBLL_IMUX13", - "CLBLL_LOGIC_OUTS10", - "CLBLL_LL_C3", - "CLBLL_WR1END2", - "CLBLL_WW4A3", - "CLBLL_EE2BEG2", - "CLBLL_LL_C1", - "CLBLL_LOGIC_OUTS22", - "CLBLL_WW4END3", - "CLBLL_L_C1", - "CLBLL_LL_A", - "CLBLL_LL_A1", - "CLBLL_L_BX", - "CLBLL_EE2BEG3", - "CLBLL_FAN4", - "CLBLL_NW4END3", - "CLBLL_WR1END0", - "CLBLL_L_A", - "CLBLL_SE4C0", - "CLBLL_LH7", - "CLBLL_WW4A1", - "CLBLL_SW4END2", - "CLBLL_LL_AMUX", - "CLBLL_BYP4", - "CLBLL_LOGIC_OUTS6", - "CLBLL_IMUX8", - "CLBLL_SW4A1", - "CLBLL_L_D1", - "CLBLL_SW2A2", - "CLBLL_LH10", - "CLBLL_LOGIC_OUTS14", - "CLBLL_FAN7", - "CLBLL_BYP2", - "CLBLL_LL_C2", - "CLBLL_IMUX7", - "CLBLL_LL_D4", - "CLBLL_LL_C", - "CLBLL_ER1BEG3", - "CLBLL_EE4A3", - "CLBLL_LOGIC_OUTS15", - "CLBLL_WR1END1", - "CLBLL_LH5", - "CLBLL_IMUX6", - "CLBLL_LL_D3", - "CLBLL_NW2A1", - "CLBLL_SE4BEG0", - "CLBLL_NE4C1", - "CLBLL_IMUX15", - "CLBLL_LL_A4", - "CLBLL_LL_B4", - "CLBLL_NW4END2", - "CLBLL_CLK1", - "CLBLL_NW4END0", - "CLBLL_IMUX14", - "CLBLL_L_CIN", - "CLBLL_WL1END3", - "CLBLL_IMUX43", - "CLBLL_EL1BEG3", - "CLBLL_LOGIC_OUTS16", - "CLBLL_LL_CLK", - "CLBLL_IMUX33", - "CLBLL_LOGIC_OUTS2", - "CLBLL_L_B1", - "CLBLL_LOGIC_OUTS18", - "CLBLL_IMUX1", - "CLBLL_SW2A1", - "CLBLL_SW4END3", - "CLBLL_NE4C3", - "CLBLL_WW4END2", - "CLBLL_EE4BEG3", - "CLBLL_EE4BEG1", - "CLBLL_CLK0", - "CLBLL_LL_D1", - "CLBLL_NW2A3", - "CLBLL_L_D3", - "CLBLL_LOGIC_OUTS12", - "CLBLL_WW4A2", - "CLBLL_NE4BEG2", - "CLBLL_IMUX10", - "CLBLL_LL_CIN", - "CLBLL_EE4C0", - "CLBLL_LOGIC_OUTS19", - "CLBLL_L_B5", - "CLBLL_IMUX4", - "CLBLL_SW2A0", - "CLBLL_NE2A0", - "CLBLL_L_SR", - "CLBLL_LH4", - "CLBLL_EL1BEG1", - "CLBLL_WW4C3", - "CLBLL_LOGIC_OUTS3", - "CLBLL_IMUX42", - "CLBLL_NW2A0", - "CLBLL_EE2A3", - "CLBLL_WW2A3", - "CLBLL_FAN1", - "CLBLL_L_D2", - "CLBLL_IMUX26", - "CLBLL_SE2A3", - "CLBLL_NW4A1", - "CLBLL_EE2A1", - "CLBLL_MONITOR_N", - "CLBLL_IMUX24", - "CLBLL_LL_B2", - "CLBLL_SW4A3", - "CLBLL_NE4BEG1", - "CLBLL_IMUX16", - "CLBLL_LL_B1", - "CLBLL_LOGIC_OUTS21", - "CLBLL_L_COUT_N", - "CLBLL_LL_CMUX", - "CLBLL_LH8", - "CLBLL_L_BQ", - "CLBLL_LL_D", - "CLBLL_SW4A0", - "CLBLL_LL_A5", - "CLBLL_L_A2", - "CLBLL_L_A5", - "CLBLL_LH3", - "CLBLL_L_AQ", - "CLBLL_L_CMUX", - "CLBLL_LOGIC_OUTS5", - "CLBLL_NW4A2", - "CLBLL_LL_B3", - "CLBLL_LOGIC_OUTS23", - "CLBLL_LL_SR", - "CLBLL_SE4BEG3", - "CLBLL_BYP3", - "CLBLL_IMUX37", - "CLBLL_IMUX39", - "CLBLL_IMUX29", - "CLBLL_L_DQ", - "CLBLL_LL_D2", - "CLBLL_WR1END3", - "CLBLL_NE2A2", - "CLBLL_LL_D5", - "CLBLL_LL_CX", - "CLBLL_WL1END0", - "CLBLL_BYP1", - "CLBLL_LOGIC_OUTS0", - "CLBLL_CTRL1", - "CLBLL_LH11", - "CLBLL_EE4B0", - "CLBLL_LL_DX", - "CLBLL_WW2END0", - "CLBLL_LOGIC_OUTS1", - "CLBLL_EE4C1", - "CLBLL_NE2A3", - "CLBLL_EE4B3", - "CLBLL_LH2", - "CLBLL_WW2END1", - "CLBLL_LH9", - "CLBLL_IMUX0", - "CLBLL_EE4BEG0", - "CLBLL_IMUX23", - "CLBLL_EL1BEG2", - "CLBLL_FAN2", - "CLBLL_LOGIC_OUTS8", - "CLBLL_WW2END3", - "CLBLL_EE2BEG1", - "CLBLL_EE4B1", - "CLBLL_WW4C2", - "CLBLL_IMUX27", - "CLBLL_LL_A3", - "CLBLL_IMUX36", - "CLBLL_L_AMUX", - "CLBLL_LOGIC_OUTS17", - "CLBLL_EE4C3", - "CLBLL_LL_C5", - "CLBLL_SW4A2", - "CLBLL_L_CX", - "CLBLL_NW2A2", - "CLBLL_EL1BEG0", - "CLBLL_LH1", - "CLBLL_WW2A0", - "CLBLL_L_BMUX", - "CLBLL_IMUX3", - "CLBLL_LL_BX", - "CLBLL_L_AX", - "CLBLL_WL1END2", - "CLBLL_LOGIC_OUTS9", - "CLBLL_FAN0", - "CLBLL_L_DX", - "CLBLL_WW4B1", - "CLBLL_LL_B6", - "CLBLL_WW2A1", - "CLBLL_LL_A6", - "CLBLL_IMUX38", - "CLBLL_L_A1", - "CLBLL_SW2A3", - "CLBLL_L_C3", - "CLBLL_L_D6", - "CLBLL_IMUX28", - "CLBLL_L_A4", - "CLBLL_L_A6", - "CLBLL_LOGIC_OUTS4", - "CLBLL_L_COUT", - "CLBLL_WW4B3", - "CLBLL_WW4C1", - "CLBLL_IMUX12", - "CLBLL_LL_D6", - "CLBLL_WW4B2", - "CLBLL_L_D5", - "CLBLL_IMUX20", - "CLBLL_IMUX40" - ], - "sites": [ - { - "prefix": "SLICE", - "y_coord": 0, - "type": "SLICEL", - "site_pins": { - "CX": "CLBLL_L_CX", - "CMUX": "CLBLL_L_CMUX", - "D1": "CLBLL_L_D1", - "CE": "CLBLL_L_CE", - "C5": "CLBLL_L_C5", - "D": "CLBLL_L_D", - "B1": "CLBLL_L_B1", - "C2": "CLBLL_L_C2", - "A2": "CLBLL_L_A2", - "CQ": "CLBLL_L_CQ", - "AMUX": "CLBLL_L_AMUX", - "BQ": "CLBLL_L_BQ", - "D3": "CLBLL_L_D3", - "B6": "CLBLL_L_B6", - "CLK": "CLBLL_L_CLK", - "SR": "CLBLL_L_SR", - "C6": "CLBLL_L_C6", - "AQ": "CLBLL_L_AQ", - "A": "CLBLL_L_A", - "B5": "CLBLL_L_B5", - "C1": "CLBLL_L_C1", - "D5": "CLBLL_L_D5", - "DMUX": "CLBLL_L_DMUX", - "DQ": "CLBLL_L_DQ", - "A6": "CLBLL_L_A6", - "D4": "CLBLL_L_D4", - "D6": "CLBLL_L_D6", - "C3": "CLBLL_L_C3", - "D2": "CLBLL_L_D2", - "B2": "CLBLL_L_B2", - "BX": "CLBLL_L_BX", - "BMUX": "CLBLL_L_BMUX", - "AX": "CLBLL_L_AX", - "C4": "CLBLL_L_C4", - "B": "CLBLL_L_B", - "A3": "CLBLL_L_A3", - "C": "CLBLL_L_C", - "COUT": "CLBLL_L_COUT", - "B4": "CLBLL_L_B4", - "A5": "CLBLL_L_A5", - "CIN": "CLBLL_L_CIN", - "DX": "CLBLL_L_DX", - "A4": "CLBLL_L_A4", - "A1": "CLBLL_L_A1", - "B3": "CLBLL_L_B3" - }, - "x_coord": 1, - "name": "X1Y0" - }, - { - "prefix": "SLICE", - "y_coord": 0, - "type": "SLICEL", - "site_pins": { - "CX": "CLBLL_LL_CX", - "CMUX": "CLBLL_LL_CMUX", - "D1": "CLBLL_LL_D1", - "CE": "CLBLL_LL_CE", - "C5": "CLBLL_LL_C5", - "D": "CLBLL_LL_D", - "B1": "CLBLL_LL_B1", - "C2": "CLBLL_LL_C2", - "A2": "CLBLL_LL_A2", - "CQ": "CLBLL_LL_CQ", - "AMUX": "CLBLL_LL_AMUX", - "BQ": "CLBLL_LL_BQ", - "D3": "CLBLL_LL_D3", - "B6": "CLBLL_LL_B6", - "CLK": "CLBLL_LL_CLK", - "SR": "CLBLL_LL_SR", - "C6": "CLBLL_LL_C6", - "AQ": "CLBLL_LL_AQ", - "A": "CLBLL_LL_A", - "B5": "CLBLL_LL_B5", - "C1": "CLBLL_LL_C1", - "D5": "CLBLL_LL_D5", - "DMUX": "CLBLL_LL_DMUX", - "DQ": "CLBLL_LL_DQ", - "A6": "CLBLL_LL_A6", - "D4": "CLBLL_LL_D4", - "D6": "CLBLL_LL_D6", - "C3": "CLBLL_LL_C3", - "D2": "CLBLL_LL_D2", - "B2": "CLBLL_LL_B2", - "BX": "CLBLL_LL_BX", - "BMUX": "CLBLL_LL_BMUX", - "AX": "CLBLL_LL_AX", - "C4": "CLBLL_LL_C4", - "B": "CLBLL_LL_B", - "A3": "CLBLL_LL_A3", - "C": "CLBLL_LL_C", - "COUT": "CLBLL_LL_COUT", - "B4": "CLBLL_LL_B4", - "A5": "CLBLL_LL_A5", - "CIN": "CLBLL_LL_CIN", - "DX": "CLBLL_LL_DX", - "A4": "CLBLL_LL_A4", - "A1": "CLBLL_LL_A1", - "B3": "CLBLL_LL_B3" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0": { + "CLBLL_L.CLBLL_IMUX0->CLBLL_L_A3": { + "src_wire": "CLBLL_IMUX0", "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS0", "is_directional": "1", - "src_wire": "CLBLL_L_AQ", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_C5->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C5", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX4->CLBLL_LL_A6": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX4", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_A4->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A4", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_BYP6->CLBLL_LL_DX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_DX", - "is_directional": "1", - "src_wire": "CLBLL_BYP6", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX32->CLBLL_LL_C1": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX32", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX24->CLBLL_LL_B5": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B5", - "is_directional": "1", - "src_wire": "CLBLL_IMUX24", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX35->CLBLL_LL_C6": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX35", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX12->CLBLL_LL_B6": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX12", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX44->CLBLL_LL_D4": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX44", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_A3->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A3", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX34->CLBLL_L_C6": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX34", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_D1->>CLBLL_LL_D": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D", - "is_directional": "1", - "src_wire": "CLBLL_LL_D1", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_D->>CLBLL_L_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_DMUX", - "is_directional": "1", - "src_wire": "CLBLL_L_D", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_B->CLBLL_LOGIC_OUTS9": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS9", - "is_directional": "1", - "src_wire": "CLBLL_L_B", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_B6->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B6", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX46->CLBLL_L_D5": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D5", - "is_directional": "1", - "src_wire": "CLBLL_IMUX46", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_A4->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A4", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX10->CLBLL_L_A4": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX10", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_C2->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C2", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_D->>CLBLL_LL_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_DMUX", - "is_directional": "1", - "src_wire": "CLBLL_LL_D", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_C->>CLBLL_LL_CMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_CMUX", - "is_directional": "1", - "src_wire": "CLBLL_LL_C", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX27->CLBLL_LL_B4": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX27", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_BQ->CLBLL_LOGIC_OUTS5": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS5", - "is_directional": "1", - "src_wire": "CLBLL_LL_BQ", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_COUT->>CLBLL_L_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_DMUX", - "is_directional": "1", - "src_wire": "CLBLL_L_COUT", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_BYP3->CLBLL_LL_CX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_CX", - "is_directional": "1", - "src_wire": "CLBLL_BYP3", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_B5->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B5", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_DMUX->CLBLL_LOGIC_OUTS19": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS19", - "is_directional": "1", - "src_wire": "CLBLL_L_DMUX", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_CMUX->CLBLL_LOGIC_OUTS18": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS18", - "is_directional": "1", - "src_wire": "CLBLL_L_CMUX", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX19->CLBLL_L_B2": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX19", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_C6->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C6", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_DQ->CLBLL_LOGIC_OUTS3": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS3", - "is_directional": "1", - "src_wire": "CLBLL_L_DQ", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX20->CLBLL_L_C2": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX20", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_B->>CLBLL_L_BMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_BMUX", - "is_directional": "1", - "src_wire": "CLBLL_L_B", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_B1->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B1", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX38->CLBLL_LL_D3": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX38", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_C->CLBLL_LOGIC_OUTS14": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS14", - "is_directional": "1", - "src_wire": "CLBLL_LL_C", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX43->CLBLL_LL_D6": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX43", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX45->CLBLL_LL_D2": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX45", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX5->CLBLL_L_A6": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX5", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_B3->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B3", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX14->CLBLL_L_B1": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX14", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX40->CLBLL_LL_D1": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX40", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_C3->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C3", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_D4->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D4", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_BMUX->CLBLL_LOGIC_OUTS21": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS21", - "is_directional": "1", - "src_wire": "CLBLL_LL_BMUX", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_DQ->CLBLL_LOGIC_OUTS7": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS7", - "is_directional": "1", - "src_wire": "CLBLL_LL_DQ", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_CQ->CLBLL_LOGIC_OUTS6": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS6", - "is_directional": "1", - "src_wire": "CLBLL_LL_CQ", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_D->CLBLL_LOGIC_OUTS11": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS11", - "is_directional": "1", - "src_wire": "CLBLL_L_D", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_C5->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C5", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX16->CLBLL_L_B3": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX16", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_A->>CLBLL_L_AMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_AMUX", - "is_directional": "1", - "src_wire": "CLBLL_L_A", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX25->CLBLL_L_B5": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B5", - "is_directional": "1", - "src_wire": "CLBLL_IMUX25", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_C6->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C6", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_B3->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", - "src_wire": "CLBLL_L_B3", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_COUT->CLBLL_L_COUT_N": { - "can_invert": "0", - "dst_wire": "CLBLL_L_COUT_N", - "is_directional": "1", - "src_wire": "CLBLL_L_COUT", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_A1->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A1", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX21->CLBLL_L_C4": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX21", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX41->CLBLL_L_D1": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX41", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX3->CLBLL_L_A2": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX3", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_B1->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", - "src_wire": "CLBLL_L_B1", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX11->CLBLL_LL_A4": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A3" }, "CLBLL_L.CLBLL_CTRL0->CLBLL_L_SR": { - "can_invert": "0", - "dst_wire": "CLBLL_L_SR", - "is_directional": "1", "src_wire": "CLBLL_CTRL0", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_A->>CLBLL_LL_AMUX": { "can_invert": "0", - "dst_wire": "CLBLL_LL_AMUX", "is_directional": "1", - "src_wire": "CLBLL_LL_A", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_C->CLBLL_LOGIC_OUTS10": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS10", - "is_directional": "1", - "src_wire": "CLBLL_L_C", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_A6->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A6", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX8->CLBLL_LL_A5": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A5", - "is_directional": "1", - "src_wire": "CLBLL_IMUX8", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_A2->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A2", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_CTRL1->CLBLL_LL_SR": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_SR", - "is_directional": "1", - "src_wire": "CLBLL_CTRL1", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_CQ->CLBLL_LOGIC_OUTS2": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS2", - "is_directional": "1", - "src_wire": "CLBLL_L_CQ", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_D2->>CLBLL_LL_D": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D", - "is_directional": "1", - "src_wire": "CLBLL_LL_D2", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_C1->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C1", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_D4->>CLBLL_LL_D": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D", - "is_directional": "1", - "src_wire": "CLBLL_LL_D4", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_D1->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D1", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_BQ->CLBLL_LOGIC_OUTS1": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS1", - "is_directional": "1", - "src_wire": "CLBLL_L_BQ", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX1->CLBLL_LL_A3": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX1", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX31->CLBLL_LL_C5": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C5", - "is_directional": "1", - "src_wire": "CLBLL_IMUX31", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_FAN7->CLBLL_LL_CE": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_CE", - "is_directional": "1", - "src_wire": "CLBLL_FAN7", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX29->CLBLL_LL_C2": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX29", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_COUT->CLBLL_LL_COUT_N": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_COUT_N", - "is_directional": "1", - "src_wire": "CLBLL_LL_COUT", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_D6->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D6", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_BYP0->CLBLL_L_AX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_AX", - "is_directional": "1", - "src_wire": "CLBLL_BYP0", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX0->CLBLL_L_A3": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX0", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_C4->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C4", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX33->CLBLL_L_C1": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX33", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_A5->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A5", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_A6->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A6", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS20", - "is_directional": "1", - "src_wire": "CLBLL_LL_AMUX", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_A3->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A3", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_B2->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B2", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_CLK1->CLBLL_LL_CLK": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_CLK", - "is_directional": "1", - "src_wire": "CLBLL_CLK1", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_A1->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A1", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_B4->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", - "src_wire": "CLBLL_L_B4", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_B->>CLBLL_LL_BMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_BMUX", - "is_directional": "1", - "src_wire": "CLBLL_LL_B", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_C1->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C1", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX42->CLBLL_L_D6": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX42", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX2->CLBLL_LL_A2": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX2", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_AMUX->CLBLL_LOGIC_OUTS16": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS16", - "is_directional": "1", - "src_wire": "CLBLL_L_AMUX", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_D5->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D5", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_B6->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", - "src_wire": "CLBLL_L_B6", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX26->CLBLL_L_B4": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX26", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_C4->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C4", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLL_L_SR" }, "CLBLL_L.CLBLL_L_C3->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", "src_wire": "CLBLL_L_C3", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_BYP4->CLBLL_LL_BX": { "can_invert": "0", - "dst_wire": "CLBLL_LL_BX", "is_directional": "1", - "src_wire": "CLBLL_BYP4", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" }, - "CLBLL_L.CLBLL_IMUX47->CLBLL_LL_D5": { + "CLBLL_L.CLBLL_L_DQ->CLBLL_LOGIC_OUTS3": { + "src_wire": "CLBLL_L_DQ", "can_invert": "0", - "dst_wire": "CLBLL_LL_D5", "is_directional": "1", - "src_wire": "CLBLL_IMUX47", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_BYP7->CLBLL_L_DX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_DX", - "is_directional": "1", - "src_wire": "CLBLL_BYP7", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_A2->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A2", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS3" }, "CLBLL_L.CLBLL_BYP1->CLBLL_LL_AX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_AX", - "is_directional": "1", "src_wire": "CLBLL_BYP1", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_C->>CLBLL_L_CMUX": { "can_invert": "0", - "dst_wire": "CLBLL_L_CMUX", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_AX" + }, + "CLBLL_L.CLBLL_L_C->CLBLL_LOGIC_OUTS10": { "src_wire": "CLBLL_L_C", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_DMUX->CLBLL_LOGIC_OUTS23": { "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS23", "is_directional": "1", - "src_wire": "CLBLL_LL_DMUX", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS10" }, - "CLBLL_L.CLBLL_IMUX22->CLBLL_LL_C3": { + "CLBLL_L.CLBLL_L_D->CLBLL_LOGIC_OUTS11": { + "src_wire": "CLBLL_L_D", "can_invert": "0", - "dst_wire": "CLBLL_LL_C3", "is_directional": "1", - "src_wire": "CLBLL_IMUX22", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS11" }, - "CLBLL_L.CLBLL_IMUX9->CLBLL_L_A5": { + "CLBLL_L.CLBLL_LL_B1->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B1", "can_invert": "0", - "dst_wire": "CLBLL_L_A5", "is_directional": "1", - "src_wire": "CLBLL_IMUX9", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" }, - "CLBLL_L.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { + "CLBLL_L.CLBLL_IMUX25->CLBLL_L_B5": { + "src_wire": "CLBLL_IMUX25", "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS12", "is_directional": "1", - "src_wire": "CLBLL_LL_A", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_B4->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B4", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_L_D3->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D3", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX7->CLBLL_LL_A1": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX7", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_C2->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C2", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX18->CLBLL_LL_B2": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX18", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_D2->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D2", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_LL_COUT->>CLBLL_LL_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_DMUX", - "is_directional": "1", - "src_wire": "CLBLL_LL_COUT", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_FAN6->CLBLL_L_CE": { - "can_invert": "0", - "dst_wire": "CLBLL_L_CE", - "is_directional": "1", - "src_wire": "CLBLL_FAN6", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX36->CLBLL_L_D2": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX36", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_CMUX->CLBLL_LOGIC_OUTS22": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS22", - "is_directional": "1", - "src_wire": "CLBLL_LL_CMUX", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_BMUX->CLBLL_LOGIC_OUTS17": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS17", - "is_directional": "1", - "src_wire": "CLBLL_L_BMUX", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_B5->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", - "src_wire": "CLBLL_L_B5", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX17->CLBLL_LL_B3": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX17", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_CLK0->CLBLL_L_CLK": { - "can_invert": "0", - "dst_wire": "CLBLL_L_CLK", - "is_directional": "1", - "src_wire": "CLBLL_CLK0", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX39->CLBLL_L_D3": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX39", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_LL_D3->>CLBLL_LL_D": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D", - "is_directional": "1", - "src_wire": "CLBLL_LL_D3", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX23->CLBLL_L_C3": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX23", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_L_A->CLBLL_LOGIC_OUTS8": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS8", - "is_directional": "1", - "src_wire": "CLBLL_L_A", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B5" }, "CLBLL_L.CLBLL_LL_A5->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", "src_wire": "CLBLL_LL_A5", - "is_pseudo": "1" - }, - "CLBLL_L.CLBLL_IMUX37->CLBLL_L_D4": { "can_invert": "0", - "dst_wire": "CLBLL_L_D4", "is_directional": "1", - "src_wire": "CLBLL_IMUX37", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" }, - "CLBLL_L.CLBLL_IMUX13->CLBLL_L_B6": { + "CLBLL_L.CLBLL_IMUX26->CLBLL_L_B4": { + "src_wire": "CLBLL_IMUX26", "can_invert": "0", - "dst_wire": "CLBLL_L_B6", "is_directional": "1", - "src_wire": "CLBLL_IMUX13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B4" }, - "CLBLL_L.CLBLL_LL_D6->>CLBLL_LL_D": { + "CLBLL_L.CLBLL_LL_C1->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C1", "can_invert": "0", - "dst_wire": "CLBLL_LL_D", "is_directional": "1", - "src_wire": "CLBLL_LL_D6", - "is_pseudo": "1" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" }, - "CLBLL_L.CLBLL_IMUX28->CLBLL_LL_C4": { + "CLBLL_L.CLBLL_IMUX20->CLBLL_L_C2": { + "src_wire": "CLBLL_IMUX20", "can_invert": "0", - "dst_wire": "CLBLL_LL_C4", "is_directional": "1", - "src_wire": "CLBLL_IMUX28", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C2" + }, + "CLBLL_L.CLBLL_IMUX29->CLBLL_LL_C2": { + "src_wire": "CLBLL_IMUX29", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C2" + }, + "CLBLL_L.CLBLL_L_CQ->CLBLL_LOGIC_OUTS2": { + "src_wire": "CLBLL_L_CQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS2" + }, + "CLBLL_L.CLBLL_LL_D4->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_L.CLBLL_IMUX3->CLBLL_L_A2": { + "src_wire": "CLBLL_IMUX3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A2" + }, + "CLBLL_L.CLBLL_IMUX1->CLBLL_LL_A3": { + "src_wire": "CLBLL_IMUX1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A3" + }, + "CLBLL_L.CLBLL_FAN6->CLBLL_L_CE": { + "src_wire": "CLBLL_FAN6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CE" + }, + "CLBLL_L.CLBLL_LL_B3->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" + }, + "CLBLL_L.CLBLL_IMUX10->CLBLL_L_A4": { + "src_wire": "CLBLL_IMUX10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A4" + }, + "CLBLL_L.CLBLL_L_B5->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_L.CLBLL_IMUX18->CLBLL_LL_B2": { + "src_wire": "CLBLL_IMUX18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B2" + }, + "CLBLL_L.CLBLL_CLK0->CLBLL_L_CLK": { + "src_wire": "CLBLL_CLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CLK" }, "CLBLL_L.CLBLL_IMUX6->CLBLL_L_A1": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A1", - "is_directional": "1", "src_wire": "CLBLL_IMUX6", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A1" }, "CLBLL_L.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS4", - "is_directional": "1", "src_wire": "CLBLL_LL_AQ", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX30->CLBLL_L_C5": { "can_invert": "0", - "dst_wire": "CLBLL_L_C5", "is_directional": "1", - "src_wire": "CLBLL_IMUX30", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS4" }, - "CLBLL_L.CLBLL_L_B2->>CLBLL_L_B": { + "CLBLL_L.CLBLL_IMUX36->CLBLL_L_D2": { + "src_wire": "CLBLL_IMUX36", "can_invert": "0", - "dst_wire": "CLBLL_L_B", "is_directional": "1", - "src_wire": "CLBLL_L_B2", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D2" }, - "CLBLL_L.CLBLL_LL_D->CLBLL_LOGIC_OUTS15": { + "CLBLL_L.CLBLL_IMUX33->CLBLL_L_C1": { + "src_wire": "CLBLL_IMUX33", "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS15", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C1" + }, + "CLBLL_L.CLBLL_L_A->>CLBLL_L_AMUX": { + "src_wire": "CLBLL_L_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_AMUX" + }, + "CLBLL_L.CLBLL_LL_D->>CLBLL_LL_DMUX": { "src_wire": "CLBLL_LL_D", - "is_pseudo": "0" - }, - "CLBLL_L.CLBLL_IMUX15->CLBLL_LL_B1": { "can_invert": "0", - "dst_wire": "CLBLL_LL_B1", "is_directional": "1", - "src_wire": "CLBLL_IMUX15", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_DMUX" }, - "CLBLL_L.CLBLL_LL_B->CLBLL_LOGIC_OUTS13": { + "CLBLL_L.CLBLL_IMUX38->CLBLL_LL_D3": { + "src_wire": "CLBLL_IMUX38", "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS13", "is_directional": "1", - "src_wire": "CLBLL_LL_B", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D3" }, - "CLBLL_L.CLBLL_LL_D5->>CLBLL_LL_D": { + "CLBLL_L.CLBLL_BYP4->CLBLL_LL_BX": { + "src_wire": "CLBLL_BYP4", "can_invert": "0", - "dst_wire": "CLBLL_LL_D", "is_directional": "1", - "src_wire": "CLBLL_LL_D5", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_BX" }, - "CLBLL_L.CLBLL_BYP2->CLBLL_L_CX": { + "CLBLL_L.CLBLL_LL_A4->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A4", "can_invert": "0", - "dst_wire": "CLBLL_L_CX", "is_directional": "1", - "src_wire": "CLBLL_BYP2", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" + }, + "CLBLL_L.CLBLL_IMUX8->CLBLL_LL_A5": { + "src_wire": "CLBLL_IMUX8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A5" + }, + "CLBLL_L.CLBLL_L_COUT->>CLBLL_L_DMUX": { + "src_wire": "CLBLL_L_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_DMUX" + }, + "CLBLL_L.CLBLL_CTRL1->CLBLL_LL_SR": { + "src_wire": "CLBLL_CTRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_SR" + }, + "CLBLL_L.CLBLL_L_C4->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_L.CLBLL_L_D5->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_L.CLBLL_IMUX44->CLBLL_LL_D4": { + "src_wire": "CLBLL_IMUX44", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D4" + }, + "CLBLL_L.CLBLL_LL_D3->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_L.CLBLL_L_D3->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_L.CLBLL_IMUX41->CLBLL_L_D1": { + "src_wire": "CLBLL_IMUX41", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D1" + }, + "CLBLL_L.CLBLL_BYP7->CLBLL_L_DX": { + "src_wire": "CLBLL_BYP7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_DX" + }, + "CLBLL_L.CLBLL_LL_C3->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_L.CLBLL_LL_C->>CLBLL_LL_CMUX": { + "src_wire": "CLBLL_LL_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_CMUX" + }, + "CLBLL_L.CLBLL_IMUX34->CLBLL_L_C6": { + "src_wire": "CLBLL_IMUX34", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C6" + }, + "CLBLL_L.CLBLL_IMUX4->CLBLL_LL_A6": { + "src_wire": "CLBLL_IMUX4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A6" + }, + "CLBLL_L.CLBLL_LL_B2->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" + }, + "CLBLL_L.CLBLL_L_B3->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" }, "CLBLL_L.CLBLL_BYP5->CLBLL_L_BX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_BX", - "is_directional": "1", "src_wire": "CLBLL_BYP5", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_BX" + }, + "CLBLL_L.CLBLL_BYP0->CLBLL_L_AX": { + "src_wire": "CLBLL_BYP0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_AX" + }, + "CLBLL_L.CLBLL_LL_COUT->>CLBLL_LL_DMUX": { + "src_wire": "CLBLL_LL_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_DMUX" + }, + "CLBLL_L.CLBLL_LL_BMUX->CLBLL_LOGIC_OUTS21": { + "src_wire": "CLBLL_LL_BMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS21" + }, + "CLBLL_L.CLBLL_IMUX24->CLBLL_LL_B5": { + "src_wire": "CLBLL_IMUX24", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B5" + }, + "CLBLL_L.CLBLL_IMUX14->CLBLL_L_B1": { + "src_wire": "CLBLL_IMUX14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B1" + }, + "CLBLL_L.CLBLL_L_C6->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_L.CLBLL_L_CMUX->CLBLL_LOGIC_OUTS18": { + "src_wire": "CLBLL_L_CMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS18" + }, + "CLBLL_L.CLBLL_LL_B6->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" + }, + "CLBLL_L.CLBLL_LL_COUT->CLBLL_LL_COUT_N": { + "src_wire": "CLBLL_LL_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_COUT_N" + }, + "CLBLL_L.CLBLL_IMUX19->CLBLL_L_B2": { + "src_wire": "CLBLL_IMUX19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B2" + }, + "CLBLL_L.CLBLL_BYP3->CLBLL_LL_CX": { + "src_wire": "CLBLL_BYP3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CX" + }, + "CLBLL_L.CLBLL_IMUX13->CLBLL_L_B6": { + "src_wire": "CLBLL_IMUX13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B6" + }, + "CLBLL_L.CLBLL_IMUX30->CLBLL_L_C5": { + "src_wire": "CLBLL_IMUX30", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C5" + }, + "CLBLL_L.CLBLL_IMUX37->CLBLL_L_D4": { + "src_wire": "CLBLL_IMUX37", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D4" + }, + "CLBLL_L.CLBLL_L_COUT->CLBLL_L_COUT_N": { + "src_wire": "CLBLL_L_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_COUT_N" + }, + "CLBLL_L.CLBLL_IMUX42->CLBLL_L_D6": { + "src_wire": "CLBLL_IMUX42", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D6" + }, + "CLBLL_L.CLBLL_IMUX22->CLBLL_LL_C3": { + "src_wire": "CLBLL_IMUX22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C3" + }, + "CLBLL_L.CLBLL_IMUX21->CLBLL_L_C4": { + "src_wire": "CLBLL_IMUX21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C4" + }, + "CLBLL_L.CLBLL_LL_B4->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" + }, + "CLBLL_L.CLBLL_CLK1->CLBLL_LL_CLK": { + "src_wire": "CLBLL_CLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CLK" + }, + "CLBLL_L.CLBLL_L_B->CLBLL_LOGIC_OUTS9": { + "src_wire": "CLBLL_L_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS9" + }, + "CLBLL_L.CLBLL_L_A2->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_L.CLBLL_IMUX43->CLBLL_LL_D6": { + "src_wire": "CLBLL_IMUX43", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D6" + }, + "CLBLL_L.CLBLL_L_A6->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_L.CLBLL_LL_A1->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" + }, + "CLBLL_L.CLBLL_L_A1->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_L.CLBLL_LL_C6->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_L.CLBLL_LL_C2->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_L.CLBLL_L_A5->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_L.CLBLL_L_D2->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_L.CLBLL_LL_CQ->CLBLL_LOGIC_OUTS6": { + "src_wire": "CLBLL_LL_CQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS6" + }, + "CLBLL_L.CLBLL_FAN7->CLBLL_LL_CE": { + "src_wire": "CLBLL_FAN7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CE" + }, + "CLBLL_L.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { + "src_wire": "CLBLL_LL_AMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS20" + }, + "CLBLL_L.CLBLL_IMUX9->CLBLL_L_A5": { + "src_wire": "CLBLL_IMUX9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A5" + }, + "CLBLL_L.CLBLL_LL_A->>CLBLL_LL_AMUX": { + "src_wire": "CLBLL_LL_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_AMUX" + }, + "CLBLL_L.CLBLL_IMUX28->CLBLL_LL_C4": { + "src_wire": "CLBLL_IMUX28", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C4" + }, + "CLBLL_L.CLBLL_BYP2->CLBLL_L_CX": { + "src_wire": "CLBLL_BYP2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CX" + }, + "CLBLL_L.CLBLL_L_A4->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_L.CLBLL_IMUX39->CLBLL_L_D3": { + "src_wire": "CLBLL_IMUX39", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D3" + }, + "CLBLL_L.CLBLL_IMUX45->CLBLL_LL_D2": { + "src_wire": "CLBLL_IMUX45", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D2" + }, + "CLBLL_L.CLBLL_L_A3->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_L.CLBLL_IMUX31->CLBLL_LL_C5": { + "src_wire": "CLBLL_IMUX31", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C5" + }, + "CLBLL_L.CLBLL_IMUX5->CLBLL_L_A6": { + "src_wire": "CLBLL_IMUX5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A6" + }, + "CLBLL_L.CLBLL_LL_C->CLBLL_LOGIC_OUTS14": { + "src_wire": "CLBLL_LL_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS14" + }, + "CLBLL_L.CLBLL_L_AMUX->CLBLL_LOGIC_OUTS16": { + "src_wire": "CLBLL_L_AMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS16" + }, + "CLBLL_L.CLBLL_IMUX40->CLBLL_LL_D1": { + "src_wire": "CLBLL_IMUX40", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D1" + }, + "CLBLL_L.CLBLL_L_BQ->CLBLL_LOGIC_OUTS1": { + "src_wire": "CLBLL_L_BQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS1" + }, + "CLBLL_L.CLBLL_L_DMUX->CLBLL_LOGIC_OUTS19": { + "src_wire": "CLBLL_L_DMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS19" + }, + "CLBLL_L.CLBLL_L_B2->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_L.CLBLL_L_D1->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_L.CLBLL_LL_B->CLBLL_LOGIC_OUTS13": { + "src_wire": "CLBLL_LL_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS13" + }, + "CLBLL_L.CLBLL_LL_A2->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" + }, + "CLBLL_L.CLBLL_IMUX17->CLBLL_LL_B3": { + "src_wire": "CLBLL_IMUX17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B3" + }, + "CLBLL_L.CLBLL_LL_D->CLBLL_LOGIC_OUTS15": { + "src_wire": "CLBLL_LL_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS15" + }, + "CLBLL_L.CLBLL_LL_DMUX->CLBLL_LOGIC_OUTS23": { + "src_wire": "CLBLL_LL_DMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS23" + }, + "CLBLL_L.CLBLL_L_B1->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0": { + "src_wire": "CLBLL_L_AQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS0" + }, + "CLBLL_L.CLBLL_L_C5->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_L.CLBLL_IMUX46->CLBLL_L_D5": { + "src_wire": "CLBLL_IMUX46", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D5" + }, + "CLBLL_L.CLBLL_L_B4->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_L.CLBLL_L_B6->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_L.CLBLL_LL_D5->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_L.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { + "src_wire": "CLBLL_LL_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS12" + }, + "CLBLL_L.CLBLL_LL_D1->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_L.CLBLL_IMUX35->CLBLL_LL_C6": { + "src_wire": "CLBLL_IMUX35", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C6" + }, + "CLBLL_L.CLBLL_LL_DQ->CLBLL_LOGIC_OUTS7": { + "src_wire": "CLBLL_LL_DQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS7" + }, + "CLBLL_L.CLBLL_L_C1->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_L.CLBLL_BYP6->CLBLL_LL_DX": { + "src_wire": "CLBLL_BYP6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_DX" + }, + "CLBLL_L.CLBLL_L_D6->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_L.CLBLL_LL_A3->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" + }, + "CLBLL_L.CLBLL_LL_C5->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_L.CLBLL_LL_B->>CLBLL_LL_BMUX": { + "src_wire": "CLBLL_LL_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_BMUX" + }, + "CLBLL_L.CLBLL_L_C2->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_L.CLBLL_LL_A6->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" + }, + "CLBLL_L.CLBLL_LL_D6->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_L.CLBLL_IMUX7->CLBLL_LL_A1": { + "src_wire": "CLBLL_IMUX7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A1" + }, + "CLBLL_L.CLBLL_L_A->CLBLL_LOGIC_OUTS8": { + "src_wire": "CLBLL_L_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS8" + }, + "CLBLL_L.CLBLL_IMUX12->CLBLL_LL_B6": { + "src_wire": "CLBLL_IMUX12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B6" + }, + "CLBLL_L.CLBLL_LL_C4->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_L.CLBLL_IMUX16->CLBLL_L_B3": { + "src_wire": "CLBLL_IMUX16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B3" + }, + "CLBLL_L.CLBLL_IMUX23->CLBLL_L_C3": { + "src_wire": "CLBLL_IMUX23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C3" + }, + "CLBLL_L.CLBLL_LL_B5->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" + }, + "CLBLL_L.CLBLL_L_D4->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_L.CLBLL_L_D->>CLBLL_L_DMUX": { + "src_wire": "CLBLL_L_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_DMUX" + }, + "CLBLL_L.CLBLL_L_C->>CLBLL_L_CMUX": { + "src_wire": "CLBLL_L_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_CMUX" + }, + "CLBLL_L.CLBLL_L_B->>CLBLL_L_BMUX": { + "src_wire": "CLBLL_L_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_BMUX" + }, + "CLBLL_L.CLBLL_IMUX15->CLBLL_LL_B1": { + "src_wire": "CLBLL_IMUX15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B1" + }, + "CLBLL_L.CLBLL_LL_BQ->CLBLL_LOGIC_OUTS5": { + "src_wire": "CLBLL_LL_BQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS5" + }, + "CLBLL_L.CLBLL_L_BMUX->CLBLL_LOGIC_OUTS17": { + "src_wire": "CLBLL_L_BMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS17" + }, + "CLBLL_L.CLBLL_IMUX11->CLBLL_LL_A4": { + "src_wire": "CLBLL_IMUX11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A4" + }, + "CLBLL_L.CLBLL_IMUX27->CLBLL_LL_B4": { + "src_wire": "CLBLL_IMUX27", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B4" + }, + "CLBLL_L.CLBLL_LL_CMUX->CLBLL_LOGIC_OUTS22": { + "src_wire": "CLBLL_LL_CMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS22" + }, + "CLBLL_L.CLBLL_IMUX47->CLBLL_LL_D5": { + "src_wire": "CLBLL_IMUX47", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D5" + }, + "CLBLL_L.CLBLL_LL_D2->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_L.CLBLL_IMUX32->CLBLL_LL_C1": { + "src_wire": "CLBLL_IMUX32", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C1" + }, + "CLBLL_L.CLBLL_IMUX2->CLBLL_LL_A2": { + "src_wire": "CLBLL_IMUX2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A2" } }, - "tile_type": "CLBLL_L" + "wires": [ + "CLBLL_EL1BEG2", + "CLBLL_IMUX24", + "CLBLL_LOGIC_OUTS10", + "CLBLL_LL_B", + "CLBLL_LH8", + "CLBLL_NW4END1", + "CLBLL_WR1END2", + "CLBLL_NE4BEG1", + "CLBLL_NE4BEG2", + "CLBLL_L_D5", + "CLBLL_LOGIC_OUTS2", + "CLBLL_EE4BEG3", + "CLBLL_WW4END3", + "CLBLL_L_CLK", + "CLBLL_CTRL1", + "CLBLL_IMUX8", + "CLBLL_WW4B1", + "CLBLL_IMUX43", + "CLBLL_L_D4", + "CLBLL_IMUX20", + "CLBLL_SW4END2", + "CLBLL_IMUX41", + "CLBLL_SE4C0", + "CLBLL_EE2BEG1", + "CLBLL_BYP1", + "CLBLL_WW4C1", + "CLBLL_EE2BEG0", + "CLBLL_LL_BMUX", + "CLBLL_WL1END2", + "CLBLL_IMUX12", + "CLBLL_LL_D4", + "CLBLL_BYP2", + "CLBLL_EE2A3", + "CLBLL_LOGIC_OUTS6", + "CLBLL_SE2A0", + "CLBLL_ER1BEG2", + "CLBLL_IMUX21", + "CLBLL_LOGIC_OUTS18", + "CLBLL_LL_CX", + "CLBLL_LL_D6", + "CLBLL_L_SR", + "CLBLL_IMUX45", + "CLBLL_IMUX25", + "CLBLL_LOGIC_OUTS19", + "CLBLL_LL_CLK", + "CLBLL_L_DX", + "CLBLL_SE2A1", + "CLBLL_EL1BEG1", + "CLBLL_IMUX9", + "CLBLL_NW2A3", + "CLBLL_MONITOR_N", + "CLBLL_WW2A0", + "CLBLL_LOGIC_OUTS22", + "CLBLL_NE2A1", + "CLBLL_LL_A5", + "CLBLL_WW2A3", + "CLBLL_FAN7", + "CLBLL_WW2END0", + "CLBLL_LOGIC_OUTS4", + "CLBLL_LOGIC_OUTS12", + "CLBLL_LL_CIN", + "CLBLL_L_AX", + "CLBLL_WW4A1", + "CLBLL_L_D2", + "CLBLL_SW4A1", + "CLBLL_LL_CMUX", + "CLBLL_WR1END0", + "CLBLL_LL_A3", + "CLBLL_LL_BQ", + "CLBLL_NW2A1", + "CLBLL_LL_DX", + "CLBLL_LOGIC_OUTS0", + "CLBLL_SE4BEG2", + "CLBLL_IMUX39", + "CLBLL_LH7", + "CLBLL_WW2A1", + "CLBLL_IMUX3", + "CLBLL_EE4C0", + "CLBLL_EE4C2", + "CLBLL_L_B4", + "CLBLL_L_DQ", + "CLBLL_LOGIC_OUTS9", + "CLBLL_NW4A2", + "CLBLL_WW2END2", + "CLBLL_L_C", + "CLBLL_BYP3", + "CLBLL_NE2A0", + "CLBLL_L_A3", + "CLBLL_IMUX31", + "CLBLL_IMUX32", + "CLBLL_WW2END1", + "CLBLL_NW4A3", + "CLBLL_FAN4", + "CLBLL_IMUX14", + "CLBLL_EE4B2", + "CLBLL_LL_D5", + "CLBLL_L_A2", + "CLBLL_IMUX47", + "CLBLL_EE4BEG1", + "CLBLL_NE4C2", + "CLBLL_IMUX29", + "CLBLL_NW4END0", + "CLBLL_L_B5", + "CLBLL_LL_D1", + "CLBLL_EL1BEG3", + "CLBLL_LH1", + "CLBLL_LL_C", + "CLBLL_LOGIC_OUTS13", + "CLBLL_SE4C3", + "CLBLL_NW2A2", + "CLBLL_L_DMUX", + "CLBLL_IMUX35", + "CLBLL_NE2A2", + "CLBLL_LL_C3", + "CLBLL_IMUX42", + "CLBLL_EE4A0", + "CLBLL_IMUX26", + "CLBLL_WL1END3", + "CLBLL_IMUX10", + "CLBLL_WL1END1", + "CLBLL_WW4B3", + "CLBLL_LL_C4", + "CLBLL_L_C3", + "CLBLL_BYP7", + "CLBLL_IMUX33", + "CLBLL_SE2A3", + "CLBLL_LOGIC_OUTS23", + "CLBLL_WR1END3", + "CLBLL_LH11", + "CLBLL_FAN1", + "CLBLL_IMUX23", + "CLBLL_IMUX36", + "CLBLL_WW4END0", + "CLBLL_IMUX1", + "CLBLL_SW4A3", + "CLBLL_MONITOR_P", + "CLBLL_LL_CQ", + "CLBLL_L_A5", + "CLBLL_EE4BEG2", + "CLBLL_EE4A2", + "CLBLL_WW4END1", + "CLBLL_LL_AMUX", + "CLBLL_LL_A6", + "CLBLL_L_B6", + "CLBLL_NW4END2", + "CLBLL_EE2BEG2", + "CLBLL_L_B2", + "CLBLL_NW4A1", + "CLBLL_SW4A2", + "CLBLL_IMUX11", + "CLBLL_IMUX27", + "CLBLL_WW4A0", + "CLBLL_IMUX28", + "CLBLL_LH5", + "CLBLL_LL_A1", + "CLBLL_NE4BEG0", + "CLBLL_NE4C1", + "CLBLL_EE4A3", + "CLBLL_LL_A4", + "CLBLL_LL_C5", + "CLBLL_ER1BEG0", + "CLBLL_WL1END0", + "CLBLL_BYP4", + "CLBLL_IMUX4", + "CLBLL_WW4A2", + "CLBLL_SW2A1", + "CLBLL_FAN3", + "CLBLL_NE4C0", + "CLBLL_L_COUT_N", + "CLBLL_SW2A2", + "CLBLL_L_CQ", + "CLBLL_BYP6", + "CLBLL_BYP5", + "CLBLL_L_D3", + "CLBLL_L_C6", + "CLBLL_LOGIC_OUTS1", + "CLBLL_IMUX37", + "CLBLL_WW4C2", + "CLBLL_SW4END3", + "CLBLL_LL_COUT_N", + "CLBLL_EE4B1", + "CLBLL_SW4END0", + "CLBLL_LL_B5", + "CLBLL_LOGIC_OUTS17", + "CLBLL_IMUX5", + "CLBLL_WW4A3", + "CLBLL_EE2BEG3", + "CLBLL_L_CE", + "CLBLL_EE2A2", + "CLBLL_L_C5", + "CLBLL_L_D6", + "CLBLL_IMUX13", + "CLBLL_L_BQ", + "CLBLL_L_C4", + "CLBLL_LOGIC_OUTS14", + "CLBLL_L_A4", + "CLBLL_FAN5", + "CLBLL_IMUX15", + "CLBLL_LOGIC_OUTS20", + "CLBLL_SE4C2", + "CLBLL_LH10", + "CLBLL_LL_BX", + "CLBLL_LH2", + "CLBLL_LH6", + "CLBLL_NE4BEG3", + "CLBLL_L_A", + "CLBLL_NE2A3", + "CLBLL_EE2A0", + "CLBLL_EE4C1", + "CLBLL_ER1BEG1", + "CLBLL_NW2A0", + "CLBLL_L_D", + "CLBLL_EE4C3", + "CLBLL_LH12", + "CLBLL_L_CMUX", + "CLBLL_IMUX0", + "CLBLL_LOGIC_OUTS15", + "CLBLL_LL_A", + "CLBLL_L_CX", + "CLBLL_IMUX44", + "CLBLL_IMUX30", + "CLBLL_ER1BEG3", + "CLBLL_EE4A1", + "CLBLL_LOGIC_OUTS5", + "CLBLL_L_BX", + "CLBLL_LL_AX", + "CLBLL_EL1BEG0", + "CLBLL_WW2A2", + "CLBLL_SW2A0", + "CLBLL_SE4C1", + "CLBLL_CTRL0", + "CLBLL_CLK1", + "CLBLL_NE4C3", + "CLBLL_WW4END2", + "CLBLL_LL_DQ", + "CLBLL_FAN6", + "CLBLL_WW4B2", + "CLBLL_WW4C3", + "CLBLL_IMUX40", + "CLBLL_LOGIC_OUTS8", + "CLBLL_LL_COUT", + "CLBLL_LL_D2", + "CLBLL_BYP0", + "CLBLL_LH4", + "CLBLL_L_AQ", + "CLBLL_IMUX19", + "CLBLL_WW4C0", + "CLBLL_SE4BEG3", + "CLBLL_IMUX18", + "CLBLL_FAN0", + "CLBLL_IMUX38", + "CLBLL_IMUX6", + "CLBLL_L_COUT", + "CLBLL_LL_B6", + "CLBLL_LL_A2", + "CLBLL_L_B", + "CLBLL_L_C2", + "CLBLL_EE4B3", + "CLBLL_LL_B4", + "CLBLL_LOGIC_OUTS16", + "CLBLL_L_A6", + "CLBLL_SW4A0", + "CLBLL_LL_B2", + "CLBLL_LL_C1", + "CLBLL_L_A1", + "CLBLL_LL_CE", + "CLBLL_L_D1", + "CLBLL_NW4A0", + "CLBLL_SW2A3", + "CLBLL_L_B3", + "CLBLL_L_BMUX", + "CLBLL_L_AMUX", + "CLBLL_WW2END3", + "CLBLL_EE2A1", + "CLBLL_LOGIC_OUTS21", + "CLBLL_SW4END1", + "CLBLL_LL_D", + "CLBLL_L_C1", + "CLBLL_L_CIN", + "CLBLL_LL_DMUX", + "CLBLL_LL_B3", + "CLBLL_IMUX7", + "CLBLL_IMUX34", + "CLBLL_IMUX22", + "CLBLL_CLK0", + "CLBLL_SE4BEG1", + "CLBLL_LL_C6", + "CLBLL_FAN2", + "CLBLL_IMUX46", + "CLBLL_L_B1", + "CLBLL_LOGIC_OUTS7", + "CLBLL_LOGIC_OUTS11", + "CLBLL_WW4B0", + "CLBLL_LH9", + "CLBLL_LL_B1", + "CLBLL_LL_AQ", + "CLBLL_LL_D3", + "CLBLL_LL_C2", + "CLBLL_SE2A2", + "CLBLL_SE4BEG0", + "CLBLL_IMUX16", + "CLBLL_EE4BEG0", + "CLBLL_WR1END1", + "CLBLL_LH3", + "CLBLL_EE4B0", + "CLBLL_LOGIC_OUTS3", + "CLBLL_LL_SR", + "CLBLL_NW4END3", + "CLBLL_IMUX17", + "CLBLL_IMUX2" + ], + "tile_type": "CLBLL_L", + "sites": [ + { + "site_pins": { + "BQ": "CLBLL_L_BQ", + "CX": "CLBLL_L_CX", + "C1": "CLBLL_L_C1", + "B6": "CLBLL_L_B6", + "DMUX": "CLBLL_L_DMUX", + "SR": "CLBLL_L_SR", + "B": "CLBLL_L_B", + "D6": "CLBLL_L_D6", + "D5": "CLBLL_L_D5", + "A5": "CLBLL_L_A5", + "AMUX": "CLBLL_L_AMUX", + "C6": "CLBLL_L_C6", + "AQ": "CLBLL_L_AQ", + "B5": "CLBLL_L_B5", + "B3": "CLBLL_L_B3", + "DQ": "CLBLL_L_DQ", + "D3": "CLBLL_L_D3", + "C": "CLBLL_L_C", + "DX": "CLBLL_L_DX", + "C4": "CLBLL_L_C4", + "A4": "CLBLL_L_A4", + "A1": "CLBLL_L_A1", + "D1": "CLBLL_L_D1", + "BX": "CLBLL_L_BX", + "COUT": "CLBLL_L_COUT", + "CLK": "CLBLL_L_CLK", + "D": "CLBLL_L_D", + "A2": "CLBLL_L_A2", + "CQ": "CLBLL_L_CQ", + "D4": "CLBLL_L_D4", + "C5": "CLBLL_L_C5", + "CIN": "CLBLL_L_CIN", + "D2": "CLBLL_L_D2", + "B2": "CLBLL_L_B2", + "A6": "CLBLL_L_A6", + "CMUX": "CLBLL_L_CMUX", + "A3": "CLBLL_L_A3", + "C3": "CLBLL_L_C3", + "AX": "CLBLL_L_AX", + "B1": "CLBLL_L_B1", + "B4": "CLBLL_L_B4", + "A": "CLBLL_L_A", + "BMUX": "CLBLL_L_BMUX", + "CE": "CLBLL_L_CE", + "C2": "CLBLL_L_C2" + }, + "type": "SLICEL", + "prefix": "SLICE", + "name": "X1Y0", + "x_coord": 1, + "y_coord": 0 + }, + { + "site_pins": { + "BQ": "CLBLL_LL_BQ", + "CX": "CLBLL_LL_CX", + "C1": "CLBLL_LL_C1", + "B6": "CLBLL_LL_B6", + "DMUX": "CLBLL_LL_DMUX", + "SR": "CLBLL_LL_SR", + "B": "CLBLL_LL_B", + "D6": "CLBLL_LL_D6", + "D5": "CLBLL_LL_D5", + "A5": "CLBLL_LL_A5", + "AMUX": "CLBLL_LL_AMUX", + "C6": "CLBLL_LL_C6", + "AQ": "CLBLL_LL_AQ", + "B5": "CLBLL_LL_B5", + "B3": "CLBLL_LL_B3", + "DQ": "CLBLL_LL_DQ", + "D3": "CLBLL_LL_D3", + "C": "CLBLL_LL_C", + "DX": "CLBLL_LL_DX", + "C4": "CLBLL_LL_C4", + "A4": "CLBLL_LL_A4", + "A1": "CLBLL_LL_A1", + "D1": "CLBLL_LL_D1", + "BX": "CLBLL_LL_BX", + "COUT": "CLBLL_LL_COUT", + "CLK": "CLBLL_LL_CLK", + "D": "CLBLL_LL_D", + "A2": "CLBLL_LL_A2", + "CQ": "CLBLL_LL_CQ", + "D4": "CLBLL_LL_D4", + "C5": "CLBLL_LL_C5", + "CIN": "CLBLL_LL_CIN", + "D2": "CLBLL_LL_D2", + "B2": "CLBLL_LL_B2", + "A6": "CLBLL_LL_A6", + "CMUX": "CLBLL_LL_CMUX", + "A3": "CLBLL_LL_A3", + "C3": "CLBLL_LL_C3", + "AX": "CLBLL_LL_AX", + "B1": "CLBLL_LL_B1", + "B4": "CLBLL_LL_B4", + "A": "CLBLL_LL_A", + "BMUX": "CLBLL_LL_BMUX", + "CE": "CLBLL_LL_CE", + "C2": "CLBLL_LL_C2" + }, + "type": "SLICEL", + "prefix": "SLICE", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLBLL_R.json b/artix7/tile_type_CLBLL_R.json index 9f04b5f..785e0e1 100644 --- a/artix7/tile_type_CLBLL_R.json +++ b/artix7/tile_type_CLBLL_R.json @@ -1,1449 +1,1449 @@ { - "wires": [ - "CLBLL_SE4BEG2", - "CLBLL_EE2BEG0", - "CLBLL_WW4END0", - "CLBLL_LOGIC_OUTS7", - "CLBLL_LL_A2", - "CLBLL_IMUX19", - "CLBLL_SW4END1", - "CLBLL_IMUX2", - "CLBLL_EE2A2", - "CLBLL_L_B6", - "CLBLL_WW2END2", - "CLBLL_IMUX34", - "CLBLL_IMUX21", - "CLBLL_EE4BEG2", - "CLBLL_EE4A1", - "CLBLL_IMUX18", - "CLBLL_L_DMUX", - "CLBLL_ER1BEG1", - "CLBLL_IMUX25", - "CLBLL_LL_B", - "CLBLL_SE2A2", - "CLBLL_NW4A3", - "CLBLL_L_C5", - "CLBLL_L_C2", - "CLBLL_IMUX44", - "CLBLL_L_CQ", - "CLBLL_BYP6", - "CLBLL_WW4A0", - "CLBLL_LL_C6", - "CLBLL_SE2A1", - "CLBLL_L_D4", - "CLBLL_L_B", - "CLBLL_NE2A1", - "CLBLL_L_A3", - "CLBLL_WW4END1", - "CLBLL_NE4BEG0", - "CLBLL_SE4C3", - "CLBLL_IMUX46", - "CLBLL_IMUX35", - "CLBLL_FAN5", - "CLBLL_ER1BEG2", - "CLBLL_BYP7", - "CLBLL_L_B3", - "CLBLL_SW4END0", - "CLBLL_SE4C2", - "CLBLL_L_B4", - "CLBLL_EE2A0", - "CLBLL_LL_CE", - "CLBLL_NW4A0", - "CLBLL_LOGIC_OUTS13", - "CLBLL_IMUX5", - "CLBLL_SE4BEG1", - "CLBLL_WL1END1", - "CLBLL_MONITOR_P", - "CLBLL_LOGIC_OUTS20", - "CLBLL_EE4B2", - "CLBLL_CTRL0", - "CLBLL_LL_CQ", - "CLBLL_LL_DQ", - "CLBLL_EE4C2", - "CLBLL_LL_COUT", - "CLBLL_BYP5", - "CLBLL_WW4C0", - "CLBLL_IMUX31", - "CLBLL_SE2A0", - "CLBLL_LH6", - "CLBLL_L_CLK", - "CLBLL_NE4C0", - "CLBLL_IMUX11", - "CLBLL_L_C", - "CLBLL_IMUX22", - "CLBLL_FAN6", - "CLBLL_WW4B0", - "CLBLL_FAN3", - "CLBLL_NE4BEG3", - "CLBLL_BYP0", - "CLBLL_L_C6", - "CLBLL_IMUX32", - "CLBLL_LOGIC_OUTS11", - "CLBLL_L_B2", - "CLBLL_IMUX17", - "CLBLL_IMUX41", - "CLBLL_LL_COUT_N", - "CLBLL_EE4A2", - "CLBLL_L_D", - "CLBLL_L_CE", - "CLBLL_LL_BMUX", - "CLBLL_LL_C4", - "CLBLL_IMUX9", - "CLBLL_ER1BEG0", - "CLBLL_LL_AQ", - "CLBLL_NW4END1", - "CLBLL_L_C4", - "CLBLL_LH12", - "CLBLL_NE4C2", - "CLBLL_LL_AX", - "CLBLL_IMUX30", - "CLBLL_EE4A0", - "CLBLL_SE4C1", - "CLBLL_WW2A2", - "CLBLL_LL_DMUX", - "CLBLL_IMUX45", - "CLBLL_IMUX47", - "CLBLL_LL_BQ", - "CLBLL_LL_B5", - "CLBLL_IMUX13", - "CLBLL_LOGIC_OUTS10", - "CLBLL_LL_C3", - "CLBLL_WR1END2", - "CLBLL_WW4A3", - "CLBLL_EE2BEG2", - "CLBLL_LL_C1", - "CLBLL_LOGIC_OUTS22", - "CLBLL_WW4END3", - "CLBLL_L_C1", - "CLBLL_LL_A", - "CLBLL_LL_A1", - "CLBLL_L_BX", - "CLBLL_EE2BEG3", - "CLBLL_FAN4", - "CLBLL_NW4END3", - "CLBLL_WR1END0", - "CLBLL_L_A", - "CLBLL_SE4C0", - "CLBLL_LH7", - "CLBLL_WW4A1", - "CLBLL_SW4END2", - "CLBLL_LL_AMUX", - "CLBLL_BYP4", - "CLBLL_LOGIC_OUTS6", - "CLBLL_IMUX8", - "CLBLL_SW4A1", - "CLBLL_L_D1", - "CLBLL_SW2A2", - "CLBLL_LH10", - "CLBLL_LOGIC_OUTS14", - "CLBLL_FAN7", - "CLBLL_BYP2", - "CLBLL_LL_C2", - "CLBLL_IMUX7", - "CLBLL_LL_D4", - "CLBLL_LL_C", - "CLBLL_ER1BEG3", - "CLBLL_EE4A3", - "CLBLL_LOGIC_OUTS15", - "CLBLL_WR1END1", - "CLBLL_LH5", - "CLBLL_IMUX6", - "CLBLL_LL_D3", - "CLBLL_NW2A1", - "CLBLL_SE4BEG0", - "CLBLL_NE4C1", - "CLBLL_IMUX15", - "CLBLL_LL_A4", - "CLBLL_LL_B4", - "CLBLL_NW4END2", - "CLBLL_CLK1", - "CLBLL_NW4END0", - "CLBLL_IMUX14", - "CLBLL_L_CIN", - "CLBLL_WL1END3", - "CLBLL_IMUX43", - "CLBLL_EL1BEG3", - "CLBLL_LOGIC_OUTS16", - "CLBLL_LL_CLK", - "CLBLL_IMUX33", - "CLBLL_LOGIC_OUTS2", - "CLBLL_L_B1", - "CLBLL_LOGIC_OUTS18", - "CLBLL_IMUX1", - "CLBLL_SW2A1", - "CLBLL_SW4END3", - "CLBLL_NE4C3", - "CLBLL_WW4END2", - "CLBLL_EE4BEG3", - "CLBLL_EE4BEG1", - "CLBLL_CLK0", - "CLBLL_LL_D1", - "CLBLL_NW2A3", - "CLBLL_L_D3", - "CLBLL_LOGIC_OUTS12", - "CLBLL_WW4A2", - "CLBLL_NE4BEG2", - "CLBLL_IMUX10", - "CLBLL_LL_CIN", - "CLBLL_EE4C0", - "CLBLL_LOGIC_OUTS19", - "CLBLL_L_B5", - "CLBLL_IMUX4", - "CLBLL_SW2A0", - "CLBLL_NE2A0", - "CLBLL_L_SR", - "CLBLL_LH4", - "CLBLL_EL1BEG1", - "CLBLL_WW4C3", - "CLBLL_LOGIC_OUTS3", - "CLBLL_IMUX42", - "CLBLL_NW2A0", - "CLBLL_EE2A3", - "CLBLL_WW2A3", - "CLBLL_FAN1", - "CLBLL_L_D2", - "CLBLL_IMUX26", - "CLBLL_SE2A3", - "CLBLL_NW4A1", - "CLBLL_EE2A1", - "CLBLL_MONITOR_N", - "CLBLL_IMUX24", - "CLBLL_LL_B2", - "CLBLL_SW4A3", - "CLBLL_NE4BEG1", - "CLBLL_IMUX16", - "CLBLL_LL_B1", - "CLBLL_LOGIC_OUTS21", - "CLBLL_L_COUT_N", - "CLBLL_LL_CMUX", - "CLBLL_LH8", - "CLBLL_L_BQ", - "CLBLL_LL_D", - "CLBLL_SW4A0", - "CLBLL_LL_A5", - "CLBLL_L_A2", - "CLBLL_L_A5", - "CLBLL_LH3", - "CLBLL_L_AQ", - "CLBLL_L_CMUX", - "CLBLL_LOGIC_OUTS5", - "CLBLL_NW4A2", - "CLBLL_LL_B3", - "CLBLL_LOGIC_OUTS23", - "CLBLL_LL_SR", - "CLBLL_SE4BEG3", - "CLBLL_BYP3", - "CLBLL_IMUX37", - "CLBLL_IMUX39", - "CLBLL_IMUX29", - "CLBLL_L_DQ", - "CLBLL_LL_D2", - "CLBLL_WR1END3", - "CLBLL_NE2A2", - "CLBLL_LL_D5", - "CLBLL_LL_CX", - "CLBLL_WL1END0", - "CLBLL_BYP1", - "CLBLL_LOGIC_OUTS0", - "CLBLL_CTRL1", - "CLBLL_LH11", - "CLBLL_EE4B0", - "CLBLL_LL_DX", - "CLBLL_WW2END0", - "CLBLL_LOGIC_OUTS1", - "CLBLL_EE4C1", - "CLBLL_NE2A3", - "CLBLL_EE4B3", - "CLBLL_LH2", - "CLBLL_WW2END1", - "CLBLL_LH9", - "CLBLL_IMUX0", - "CLBLL_EE4BEG0", - "CLBLL_IMUX23", - "CLBLL_EL1BEG2", - "CLBLL_FAN2", - "CLBLL_LOGIC_OUTS8", - "CLBLL_WW2END3", - "CLBLL_EE2BEG1", - "CLBLL_EE4B1", - "CLBLL_WW4C2", - "CLBLL_IMUX27", - "CLBLL_LL_A3", - "CLBLL_IMUX36", - "CLBLL_L_AMUX", - "CLBLL_LOGIC_OUTS17", - "CLBLL_EE4C3", - "CLBLL_LL_C5", - "CLBLL_SW4A2", - "CLBLL_L_CX", - "CLBLL_NW2A2", - "CLBLL_EL1BEG0", - "CLBLL_LH1", - "CLBLL_WW2A0", - "CLBLL_L_BMUX", - "CLBLL_IMUX3", - "CLBLL_LL_BX", - "CLBLL_L_AX", - "CLBLL_WL1END2", - "CLBLL_LOGIC_OUTS9", - "CLBLL_FAN0", - "CLBLL_L_DX", - "CLBLL_WW4B1", - "CLBLL_LL_B6", - "CLBLL_WW2A1", - "CLBLL_LL_A6", - "CLBLL_IMUX38", - "CLBLL_L_A1", - "CLBLL_SW2A3", - "CLBLL_L_C3", - "CLBLL_L_D6", - "CLBLL_IMUX28", - "CLBLL_L_A4", - "CLBLL_L_A6", - "CLBLL_LOGIC_OUTS4", - "CLBLL_L_COUT", - "CLBLL_WW4B3", - "CLBLL_WW4C1", - "CLBLL_IMUX12", - "CLBLL_LL_D6", - "CLBLL_WW4B2", - "CLBLL_L_D5", - "CLBLL_IMUX20", - "CLBLL_IMUX40" - ], - "sites": [ - { - "prefix": "SLICE", - "y_coord": 0, - "type": "SLICEL", - "site_pins": { - "CX": "CLBLL_LL_CX", - "CMUX": "CLBLL_LL_CMUX", - "D1": "CLBLL_LL_D1", - "CE": "CLBLL_LL_CE", - "C5": "CLBLL_LL_C5", - "D": "CLBLL_LL_D", - "B1": "CLBLL_LL_B1", - "C2": "CLBLL_LL_C2", - "A2": "CLBLL_LL_A2", - "CQ": "CLBLL_LL_CQ", - "AMUX": "CLBLL_LL_AMUX", - "BQ": "CLBLL_LL_BQ", - "D3": "CLBLL_LL_D3", - "B6": "CLBLL_LL_B6", - "CLK": "CLBLL_LL_CLK", - "SR": "CLBLL_LL_SR", - "C6": "CLBLL_LL_C6", - "AQ": "CLBLL_LL_AQ", - "A": "CLBLL_LL_A", - "B5": "CLBLL_LL_B5", - "C1": "CLBLL_LL_C1", - "D5": "CLBLL_LL_D5", - "DMUX": "CLBLL_LL_DMUX", - "DQ": "CLBLL_LL_DQ", - "A6": "CLBLL_LL_A6", - "D4": "CLBLL_LL_D4", - "D6": "CLBLL_LL_D6", - "C3": "CLBLL_LL_C3", - "D2": "CLBLL_LL_D2", - "B2": "CLBLL_LL_B2", - "BX": "CLBLL_LL_BX", - "BMUX": "CLBLL_LL_BMUX", - "AX": "CLBLL_LL_AX", - "C4": "CLBLL_LL_C4", - "B": "CLBLL_LL_B", - "A3": "CLBLL_LL_A3", - "C": "CLBLL_LL_C", - "COUT": "CLBLL_LL_COUT", - "B4": "CLBLL_LL_B4", - "A5": "CLBLL_LL_A5", - "CIN": "CLBLL_LL_CIN", - "DX": "CLBLL_LL_DX", - "A4": "CLBLL_LL_A4", - "A1": "CLBLL_LL_A1", - "B3": "CLBLL_LL_B3" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "SLICE", - "y_coord": 0, - "type": "SLICEL", - "site_pins": { - "CX": "CLBLL_L_CX", - "CMUX": "CLBLL_L_CMUX", - "D1": "CLBLL_L_D1", - "CE": "CLBLL_L_CE", - "C5": "CLBLL_L_C5", - "D": "CLBLL_L_D", - "B1": "CLBLL_L_B1", - "C2": "CLBLL_L_C2", - "A2": "CLBLL_L_A2", - "CQ": "CLBLL_L_CQ", - "AMUX": "CLBLL_L_AMUX", - "BQ": "CLBLL_L_BQ", - "D3": "CLBLL_L_D3", - "B6": "CLBLL_L_B6", - "CLK": "CLBLL_L_CLK", - "SR": "CLBLL_L_SR", - "C6": "CLBLL_L_C6", - "AQ": "CLBLL_L_AQ", - "A": "CLBLL_L_A", - "B5": "CLBLL_L_B5", - "C1": "CLBLL_L_C1", - "D5": "CLBLL_L_D5", - "DMUX": "CLBLL_L_DMUX", - "DQ": "CLBLL_L_DQ", - "A6": "CLBLL_L_A6", - "D4": "CLBLL_L_D4", - "D6": "CLBLL_L_D6", - "C3": "CLBLL_L_C3", - "D2": "CLBLL_L_D2", - "B2": "CLBLL_L_B2", - "BX": "CLBLL_L_BX", - "BMUX": "CLBLL_L_BMUX", - "AX": "CLBLL_L_AX", - "C4": "CLBLL_L_C4", - "B": "CLBLL_L_B", - "A3": "CLBLL_L_A3", - "C": "CLBLL_L_C", - "COUT": "CLBLL_L_COUT", - "B4": "CLBLL_L_B4", - "A5": "CLBLL_L_A5", - "CIN": "CLBLL_L_CIN", - "DX": "CLBLL_L_DX", - "A4": "CLBLL_L_A4", - "A1": "CLBLL_L_A1", - "B3": "CLBLL_L_B3" - }, - "x_coord": 1, - "name": "X1Y0" - } - ], "pips": { - "CLBLL_R.CLBLL_IMUX4->CLBLL_LL_A6": { + "CLBLL_R.CLBLL_LL_D->CLBLL_LOGIC_OUTS15": { + "src_wire": "CLBLL_LL_D", "can_invert": "0", - "dst_wire": "CLBLL_LL_A6", "is_directional": "1", - "src_wire": "CLBLL_IMUX4", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_A->>CLBLL_L_AMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_AMUX", - "is_directional": "1", - "src_wire": "CLBLL_L_A", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_B1->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B1", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_A3->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A3", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_COUT->CLBLL_LL_COUT_N": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_COUT_N", - "is_directional": "1", - "src_wire": "CLBLL_LL_COUT", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_D1->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D1", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX43->CLBLL_LL_D6": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX43", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX44->CLBLL_LL_D4": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX44", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX32->CLBLL_LL_C1": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX32", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX26->CLBLL_L_B4": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX26", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS20", - "is_directional": "1", - "src_wire": "CLBLL_LL_AMUX", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX19->CLBLL_L_B2": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX19", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_C6->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C6", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_CLK1->CLBLL_LL_CLK": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_CLK", - "is_directional": "1", - "src_wire": "CLBLL_CLK1", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX21->CLBLL_L_C4": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX21", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX33->CLBLL_L_C1": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX33", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_A2->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A2", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX34->CLBLL_L_C6": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX34", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_CMUX->CLBLL_LOGIC_OUTS18": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS18", - "is_directional": "1", - "src_wire": "CLBLL_L_CMUX", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX40->CLBLL_LL_D1": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX40", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX22->CLBLL_LL_C3": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX22", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_D2->>CLBLL_LL_D": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D", - "is_directional": "1", - "src_wire": "CLBLL_LL_D2", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_A4->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A4", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_BYP4->CLBLL_LL_BX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_BX", - "is_directional": "1", - "src_wire": "CLBLL_BYP4", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_CMUX->CLBLL_LOGIC_OUTS22": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS22", - "is_directional": "1", - "src_wire": "CLBLL_LL_CMUX", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_D1->>CLBLL_LL_D": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D", - "is_directional": "1", - "src_wire": "CLBLL_LL_D1", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX37->CLBLL_L_D4": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX37", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_B->>CLBLL_L_BMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_BMUX", - "is_directional": "1", - "src_wire": "CLBLL_L_B", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX35->CLBLL_LL_C6": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX35", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX6->CLBLL_L_A1": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX6", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_C6->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C6", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS4", - "is_directional": "1", - "src_wire": "CLBLL_LL_AQ", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_C1->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C1", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX45->CLBLL_LL_D2": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX45", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_C4->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C4", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_FAN7->CLBLL_LL_CE": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_CE", - "is_directional": "1", - "src_wire": "CLBLL_FAN7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS15" }, "CLBLL_R.CLBLL_LL_A5->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", "src_wire": "CLBLL_LL_A5", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX8->CLBLL_LL_A5": { "can_invert": "0", - "dst_wire": "CLBLL_LL_A5", "is_directional": "1", - "src_wire": "CLBLL_IMUX8", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_B3->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B3", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX15->CLBLL_LL_B1": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX15", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_BYP0->CLBLL_L_AX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_AX", - "is_directional": "1", - "src_wire": "CLBLL_BYP0", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_BYP7->CLBLL_L_DX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_DX", - "is_directional": "1", - "src_wire": "CLBLL_BYP7", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX27->CLBLL_LL_B4": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX27", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_D3->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D3", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_D5->>CLBLL_LL_D": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D", - "is_directional": "1", - "src_wire": "CLBLL_LL_D5", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX46->CLBLL_L_D5": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D5", - "is_directional": "1", - "src_wire": "CLBLL_IMUX46", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_CLK0->CLBLL_L_CLK": { - "can_invert": "0", - "dst_wire": "CLBLL_L_CLK", - "is_directional": "1", - "src_wire": "CLBLL_CLK0", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_B2->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", - "src_wire": "CLBLL_L_B2", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX11->CLBLL_LL_A4": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX11", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX12->CLBLL_LL_B6": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX12", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_D6->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D6", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_A->>CLBLL_LL_AMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_AMUX", - "is_directional": "1", - "src_wire": "CLBLL_LL_A", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX13->CLBLL_L_B6": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX13", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX2->CLBLL_LL_A2": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX2", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_COUT->>CLBLL_LL_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_DMUX", - "is_directional": "1", - "src_wire": "CLBLL_LL_COUT", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_CTRL1->CLBLL_LL_SR": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_SR", - "is_directional": "1", - "src_wire": "CLBLL_CTRL1", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS0", - "is_directional": "1", - "src_wire": "CLBLL_L_AQ", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_BYP1->CLBLL_LL_AX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_AX", - "is_directional": "1", - "src_wire": "CLBLL_BYP1", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX36->CLBLL_L_D2": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX36", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX18->CLBLL_LL_B2": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX18", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_BMUX->CLBLL_LOGIC_OUTS17": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS17", - "is_directional": "1", - "src_wire": "CLBLL_L_BMUX", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_B2->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B2", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_FAN6->CLBLL_L_CE": { - "can_invert": "0", - "dst_wire": "CLBLL_L_CE", - "is_directional": "1", - "src_wire": "CLBLL_FAN6", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_A4->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A4", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX1->CLBLL_LL_A3": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX1", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS12", - "is_directional": "1", - "src_wire": "CLBLL_LL_A", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_D4->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D4", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_B->>CLBLL_LL_BMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_BMUX", - "is_directional": "1", - "src_wire": "CLBLL_LL_B", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX7->CLBLL_LL_A1": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX7", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_A1->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A1", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_B4->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B4", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_COUT->>CLBLL_L_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_DMUX", - "is_directional": "1", - "src_wire": "CLBLL_L_COUT", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX42->CLBLL_L_D6": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX42", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_D2->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D2", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_C2->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C2", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_BQ->CLBLL_LOGIC_OUTS1": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS1", - "is_directional": "1", - "src_wire": "CLBLL_L_BQ", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_C->>CLBLL_L_CMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_CMUX", - "is_directional": "1", - "src_wire": "CLBLL_L_C", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX28->CLBLL_LL_C4": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX28", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_D6->>CLBLL_LL_D": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D", - "is_directional": "1", - "src_wire": "CLBLL_LL_D6", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_D->>CLBLL_L_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_DMUX", - "is_directional": "1", - "src_wire": "CLBLL_L_D", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_C1->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C1", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_A5->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A5", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_DMUX->CLBLL_LOGIC_OUTS23": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS23", - "is_directional": "1", - "src_wire": "CLBLL_LL_DMUX", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_CQ->CLBLL_LOGIC_OUTS6": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS6", - "is_directional": "1", - "src_wire": "CLBLL_LL_CQ", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_BYP6->CLBLL_LL_DX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_DX", - "is_directional": "1", - "src_wire": "CLBLL_BYP6", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_C->>CLBLL_LL_CMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_CMUX", - "is_directional": "1", - "src_wire": "CLBLL_LL_C", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_AMUX->CLBLL_LOGIC_OUTS16": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS16", - "is_directional": "1", - "src_wire": "CLBLL_L_AMUX", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_B6->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", - "src_wire": "CLBLL_LL_B6", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX38->CLBLL_LL_D3": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX38", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_BYP3->CLBLL_LL_CX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_CX", - "is_directional": "1", - "src_wire": "CLBLL_BYP3", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX3->CLBLL_L_A2": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX3", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_C2->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C2", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_D3->>CLBLL_LL_D": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_D", - "is_directional": "1", - "src_wire": "CLBLL_LL_D3", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_IMUX23->CLBLL_L_C3": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX23", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_B1->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", - "src_wire": "CLBLL_L_B1", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_CQ->CLBLL_LOGIC_OUTS2": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS2", - "is_directional": "1", - "src_wire": "CLBLL_L_CQ", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_B->CLBLL_LOGIC_OUTS13": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS13", - "is_directional": "1", - "src_wire": "CLBLL_LL_B", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX25->CLBLL_L_B5": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B5", - "is_directional": "1", - "src_wire": "CLBLL_IMUX25", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_DQ->CLBLL_LOGIC_OUTS7": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS7", - "is_directional": "1", - "src_wire": "CLBLL_LL_DQ", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_C4->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C4", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_C3->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C3", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_B6->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", - "src_wire": "CLBLL_L_B6", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_D5->>CLBLL_L_D": { - "can_invert": "0", - "dst_wire": "CLBLL_L_D", - "is_directional": "1", - "src_wire": "CLBLL_L_D5", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_A6->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A6", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_D->>CLBLL_LL_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_DMUX", - "is_directional": "1", - "src_wire": "CLBLL_LL_D", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_B5->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", - "src_wire": "CLBLL_L_B5", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_A3->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A3", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_A1->>CLBLL_LL_A": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_A", - "is_directional": "1", - "src_wire": "CLBLL_LL_A1", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_LL_BMUX->CLBLL_LOGIC_OUTS21": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS21", - "is_directional": "1", - "src_wire": "CLBLL_LL_BMUX", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX5->CLBLL_L_A6": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A6", - "is_directional": "1", - "src_wire": "CLBLL_IMUX5", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_C->CLBLL_LOGIC_OUTS14": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS14", - "is_directional": "1", - "src_wire": "CLBLL_LL_C", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_CTRL0->CLBLL_L_SR": { - "can_invert": "0", - "dst_wire": "CLBLL_L_SR", - "is_directional": "1", - "src_wire": "CLBLL_CTRL0", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX0->CLBLL_L_A3": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A3", - "is_directional": "1", - "src_wire": "CLBLL_IMUX0", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_D->CLBLL_LOGIC_OUTS11": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS11", - "is_directional": "1", - "src_wire": "CLBLL_L_D", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_BQ->CLBLL_LOGIC_OUTS5": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS5", - "is_directional": "1", - "src_wire": "CLBLL_LL_BQ", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX14->CLBLL_L_B1": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B1", - "is_directional": "1", - "src_wire": "CLBLL_IMUX14", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX20->CLBLL_L_C2": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C2", - "is_directional": "1", - "src_wire": "CLBLL_IMUX20", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_C->CLBLL_LOGIC_OUTS10": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS10", - "is_directional": "1", - "src_wire": "CLBLL_L_C", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX31->CLBLL_LL_C5": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C5", - "is_directional": "1", - "src_wire": "CLBLL_IMUX31", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_A2->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A2", - "is_pseudo": "1" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" }, "CLBLL_R.CLBLL_L_B4->>CLBLL_L_B": { - "can_invert": "0", - "dst_wire": "CLBLL_L_B", - "is_directional": "1", "src_wire": "CLBLL_L_B4", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_COUT->CLBLL_L_COUT_N": { "can_invert": "0", - "dst_wire": "CLBLL_L_COUT_N", "is_directional": "1", - "src_wire": "CLBLL_L_COUT", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" }, - "CLBLL_R.CLBLL_L_DQ->CLBLL_LOGIC_OUTS3": { + "CLBLL_R.CLBLL_IMUX3->CLBLL_L_A2": { + "src_wire": "CLBLL_IMUX3", "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS3", "is_directional": "1", - "src_wire": "CLBLL_L_DQ", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_C5->>CLBLL_LL_C": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_C", - "is_directional": "1", - "src_wire": "CLBLL_LL_C5", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_A->CLBLL_LOGIC_OUTS8": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS8", - "is_directional": "1", - "src_wire": "CLBLL_L_A", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX10->CLBLL_L_A4": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A4", - "is_directional": "1", - "src_wire": "CLBLL_IMUX10", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_DMUX->CLBLL_LOGIC_OUTS19": { - "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS19", - "is_directional": "1", - "src_wire": "CLBLL_L_DMUX", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_BYP2->CLBLL_L_CX": { - "can_invert": "0", - "dst_wire": "CLBLL_L_CX", - "is_directional": "1", - "src_wire": "CLBLL_BYP2", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_C5->>CLBLL_L_C": { - "can_invert": "0", - "dst_wire": "CLBLL_L_C", - "is_directional": "1", - "src_wire": "CLBLL_L_C5", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A2" }, "CLBLL_R.CLBLL_LL_B5->>CLBLL_LL_B": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B", - "is_directional": "1", "src_wire": "CLBLL_LL_B5", - "is_pseudo": "1" - }, - "CLBLL_R.CLBLL_L_B->CLBLL_LOGIC_OUTS9": { "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS9", "is_directional": "1", - "src_wire": "CLBLL_L_B", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" }, - "CLBLL_R.CLBLL_L_B3->>CLBLL_L_B": { + "CLBLL_R.CLBLL_L_COUT->>CLBLL_L_DMUX": { + "src_wire": "CLBLL_L_COUT", "can_invert": "0", - "dst_wire": "CLBLL_L_B", "is_directional": "1", - "src_wire": "CLBLL_L_B3", - "is_pseudo": "1" + "is_pseudo": "1", + "dst_wire": "CLBLL_L_DMUX" }, - "CLBLL_R.CLBLL_IMUX29->CLBLL_LL_C2": { + "CLBLL_R.CLBLL_LL_D6->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D6", "can_invert": "0", - "dst_wire": "CLBLL_LL_C2", "is_directional": "1", - "src_wire": "CLBLL_IMUX29", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" }, - "CLBLL_R.CLBLL_LL_D->CLBLL_LOGIC_OUTS15": { + "CLBLL_R.CLBLL_CLK0->CLBLL_L_CLK": { + "src_wire": "CLBLL_CLK0", "can_invert": "0", - "dst_wire": "CLBLL_LOGIC_OUTS15", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CLK" + }, + "CLBLL_R.CLBLL_IMUX35->CLBLL_LL_C6": { + "src_wire": "CLBLL_IMUX35", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C6" + }, + "CLBLL_R.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { + "src_wire": "CLBLL_LL_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS12" + }, + "CLBLL_R.CLBLL_L_AMUX->CLBLL_LOGIC_OUTS16": { + "src_wire": "CLBLL_L_AMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS16" + }, + "CLBLL_R.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { + "src_wire": "CLBLL_LL_AMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS20" + }, + "CLBLL_R.CLBLL_CLK1->CLBLL_LL_CLK": { + "src_wire": "CLBLL_CLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CLK" + }, + "CLBLL_R.CLBLL_IMUX1->CLBLL_LL_A3": { + "src_wire": "CLBLL_IMUX1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A3" + }, + "CLBLL_R.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { + "src_wire": "CLBLL_LL_AQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS4" + }, + "CLBLL_R.CLBLL_IMUX2->CLBLL_LL_A2": { + "src_wire": "CLBLL_IMUX2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A2" + }, + "CLBLL_R.CLBLL_L_C5->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_R.CLBLL_LL_D->>CLBLL_LL_DMUX": { "src_wire": "CLBLL_LL_D", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_LL_D4->>CLBLL_LL_D": { "can_invert": "0", - "dst_wire": "CLBLL_LL_D", "is_directional": "1", - "src_wire": "CLBLL_LL_D4", - "is_pseudo": "1" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_DMUX" }, - "CLBLL_R.CLBLL_IMUX17->CLBLL_LL_B3": { + "CLBLL_R.CLBLL_LL_C4->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C4", "can_invert": "0", - "dst_wire": "CLBLL_LL_B3", "is_directional": "1", - "src_wire": "CLBLL_IMUX17", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" }, - "CLBLL_R.CLBLL_IMUX16->CLBLL_L_B3": { + "CLBLL_R.CLBLL_L_BMUX->CLBLL_LOGIC_OUTS17": { + "src_wire": "CLBLL_L_BMUX", "can_invert": "0", - "dst_wire": "CLBLL_L_B3", "is_directional": "1", - "src_wire": "CLBLL_IMUX16", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS17" }, - "CLBLL_R.CLBLL_L_C3->>CLBLL_L_C": { + "CLBLL_R.CLBLL_IMUX11->CLBLL_LL_A4": { + "src_wire": "CLBLL_IMUX11", "can_invert": "0", - "dst_wire": "CLBLL_L_C", "is_directional": "1", - "src_wire": "CLBLL_L_C3", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A4" }, - "CLBLL_R.CLBLL_IMUX39->CLBLL_L_D3": { + "CLBLL_R.CLBLL_IMUX33->CLBLL_L_C1": { + "src_wire": "CLBLL_IMUX33", "can_invert": "0", - "dst_wire": "CLBLL_L_D3", "is_directional": "1", - "src_wire": "CLBLL_IMUX39", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C1" }, - "CLBLL_R.CLBLL_IMUX30->CLBLL_L_C5": { + "CLBLL_R.CLBLL_IMUX4->CLBLL_LL_A6": { + "src_wire": "CLBLL_IMUX4", "can_invert": "0", - "dst_wire": "CLBLL_L_C5", "is_directional": "1", - "src_wire": "CLBLL_IMUX30", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A6" }, - "CLBLL_R.CLBLL_IMUX47->CLBLL_LL_D5": { + "CLBLL_R.CLBLL_IMUX25->CLBLL_L_B5": { + "src_wire": "CLBLL_IMUX25", "can_invert": "0", - "dst_wire": "CLBLL_LL_D5", "is_directional": "1", - "src_wire": "CLBLL_IMUX47", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B5" }, - "CLBLL_R.CLBLL_IMUX41->CLBLL_L_D1": { + "CLBLL_R.CLBLL_LL_B1->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B1", "can_invert": "0", - "dst_wire": "CLBLL_L_D1", "is_directional": "1", - "src_wire": "CLBLL_IMUX41", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" }, - "CLBLL_R.CLBLL_BYP5->CLBLL_L_BX": { + "CLBLL_R.CLBLL_LL_A1->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A1", "can_invert": "0", - "dst_wire": "CLBLL_L_BX", "is_directional": "1", - "src_wire": "CLBLL_BYP5", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_IMUX9->CLBLL_L_A5": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A5", - "is_directional": "1", - "src_wire": "CLBLL_IMUX9", - "is_pseudo": "0" - }, - "CLBLL_R.CLBLL_L_A6->>CLBLL_L_A": { - "can_invert": "0", - "dst_wire": "CLBLL_L_A", - "is_directional": "1", - "src_wire": "CLBLL_L_A6", - "is_pseudo": "1" + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" }, "CLBLL_R.CLBLL_IMUX24->CLBLL_LL_B5": { - "can_invert": "0", - "dst_wire": "CLBLL_LL_B5", - "is_directional": "1", "src_wire": "CLBLL_IMUX24", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B5" + }, + "CLBLL_R.CLBLL_FAN7->CLBLL_LL_CE": { + "src_wire": "CLBLL_FAN7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CE" + }, + "CLBLL_R.CLBLL_L_C6->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_R.CLBLL_IMUX40->CLBLL_LL_D1": { + "src_wire": "CLBLL_IMUX40", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D1" + }, + "CLBLL_R.CLBLL_L_A->CLBLL_LOGIC_OUTS8": { + "src_wire": "CLBLL_L_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS8" + }, + "CLBLL_R.CLBLL_L_A5->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_R.CLBLL_IMUX23->CLBLL_L_C3": { + "src_wire": "CLBLL_IMUX23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C3" + }, + "CLBLL_R.CLBLL_IMUX21->CLBLL_L_C4": { + "src_wire": "CLBLL_IMUX21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C4" + }, + "CLBLL_R.CLBLL_IMUX31->CLBLL_LL_C5": { + "src_wire": "CLBLL_IMUX31", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C5" + }, + "CLBLL_R.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0": { + "src_wire": "CLBLL_L_AQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS0" + }, + "CLBLL_R.CLBLL_LL_BMUX->CLBLL_LOGIC_OUTS21": { + "src_wire": "CLBLL_LL_BMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS21" + }, + "CLBLL_R.CLBLL_IMUX26->CLBLL_L_B4": { + "src_wire": "CLBLL_IMUX26", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B4" + }, + "CLBLL_R.CLBLL_LL_C->CLBLL_LOGIC_OUTS14": { + "src_wire": "CLBLL_LL_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS14" + }, + "CLBLL_R.CLBLL_L_B->CLBLL_LOGIC_OUTS9": { + "src_wire": "CLBLL_L_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS9" + }, + "CLBLL_R.CLBLL_L_C4->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_R.CLBLL_L_DMUX->CLBLL_LOGIC_OUTS19": { + "src_wire": "CLBLL_L_DMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS19" + }, + "CLBLL_R.CLBLL_IMUX36->CLBLL_L_D2": { + "src_wire": "CLBLL_IMUX36", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D2" + }, + "CLBLL_R.CLBLL_IMUX17->CLBLL_LL_B3": { + "src_wire": "CLBLL_IMUX17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B3" + }, + "CLBLL_R.CLBLL_L_BQ->CLBLL_LOGIC_OUTS1": { + "src_wire": "CLBLL_L_BQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS1" + }, + "CLBLL_R.CLBLL_LL_A6->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" + }, + "CLBLL_R.CLBLL_IMUX45->CLBLL_LL_D2": { + "src_wire": "CLBLL_IMUX45", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D2" + }, + "CLBLL_R.CLBLL_LL_B4->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" + }, + "CLBLL_R.CLBLL_IMUX44->CLBLL_LL_D4": { + "src_wire": "CLBLL_IMUX44", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D4" + }, + "CLBLL_R.CLBLL_LL_D1->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_R.CLBLL_BYP3->CLBLL_LL_CX": { + "src_wire": "CLBLL_BYP3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_CX" + }, + "CLBLL_R.CLBLL_LL_C->>CLBLL_LL_CMUX": { + "src_wire": "CLBLL_LL_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_CMUX" + }, + "CLBLL_R.CLBLL_IMUX42->CLBLL_L_D6": { + "src_wire": "CLBLL_IMUX42", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D6" + }, + "CLBLL_R.CLBLL_IMUX12->CLBLL_LL_B6": { + "src_wire": "CLBLL_IMUX12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B6" + }, + "CLBLL_R.CLBLL_IMUX18->CLBLL_LL_B2": { + "src_wire": "CLBLL_IMUX18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B2" + }, + "CLBLL_R.CLBLL_IMUX37->CLBLL_L_D4": { + "src_wire": "CLBLL_IMUX37", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D4" + }, + "CLBLL_R.CLBLL_L_CQ->CLBLL_LOGIC_OUTS2": { + "src_wire": "CLBLL_L_CQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS2" + }, + "CLBLL_R.CLBLL_IMUX13->CLBLL_L_B6": { + "src_wire": "CLBLL_IMUX13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B6" + }, + "CLBLL_R.CLBLL_L_B1->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_R.CLBLL_IMUX15->CLBLL_LL_B1": { + "src_wire": "CLBLL_IMUX15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B1" + }, + "CLBLL_R.CLBLL_LL_B3->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" + }, + "CLBLL_R.CLBLL_L_A2->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_R.CLBLL_LL_A->>CLBLL_LL_AMUX": { + "src_wire": "CLBLL_LL_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_AMUX" + }, + "CLBLL_R.CLBLL_IMUX10->CLBLL_L_A4": { + "src_wire": "CLBLL_IMUX10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A4" + }, + "CLBLL_R.CLBLL_LL_DMUX->CLBLL_LOGIC_OUTS23": { + "src_wire": "CLBLL_LL_DMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS23" + }, + "CLBLL_R.CLBLL_IMUX32->CLBLL_LL_C1": { + "src_wire": "CLBLL_IMUX32", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C1" + }, + "CLBLL_R.CLBLL_LL_COUT->CLBLL_LL_COUT_N": { + "src_wire": "CLBLL_LL_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_COUT_N" + }, + "CLBLL_R.CLBLL_IMUX6->CLBLL_L_A1": { + "src_wire": "CLBLL_IMUX6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A1" + }, + "CLBLL_R.CLBLL_CTRL0->CLBLL_L_SR": { + "src_wire": "CLBLL_CTRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_SR" + }, + "CLBLL_R.CLBLL_IMUX8->CLBLL_LL_A5": { + "src_wire": "CLBLL_IMUX8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A5" + }, + "CLBLL_R.CLBLL_FAN6->CLBLL_L_CE": { + "src_wire": "CLBLL_FAN6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CE" + }, + "CLBLL_R.CLBLL_LL_A3->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" + }, + "CLBLL_R.CLBLL_BYP2->CLBLL_L_CX": { + "src_wire": "CLBLL_BYP2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_CX" + }, + "CLBLL_R.CLBLL_BYP6->CLBLL_LL_DX": { + "src_wire": "CLBLL_BYP6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_DX" + }, + "CLBLL_R.CLBLL_BYP0->CLBLL_L_AX": { + "src_wire": "CLBLL_BYP0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_AX" + }, + "CLBLL_R.CLBLL_L_D->CLBLL_LOGIC_OUTS11": { + "src_wire": "CLBLL_L_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS11" + }, + "CLBLL_R.CLBLL_L_C2->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_R.CLBLL_LL_B->CLBLL_LOGIC_OUTS13": { + "src_wire": "CLBLL_LL_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS13" + }, + "CLBLL_R.CLBLL_LL_A4->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" + }, + "CLBLL_R.CLBLL_LL_COUT->>CLBLL_LL_DMUX": { + "src_wire": "CLBLL_LL_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_DMUX" + }, + "CLBLL_R.CLBLL_IMUX22->CLBLL_LL_C3": { + "src_wire": "CLBLL_IMUX22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C3" + }, + "CLBLL_R.CLBLL_LL_B->>CLBLL_LL_BMUX": { + "src_wire": "CLBLL_LL_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_BMUX" + }, + "CLBLL_R.CLBLL_L_D->>CLBLL_L_DMUX": { + "src_wire": "CLBLL_L_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_DMUX" + }, + "CLBLL_R.CLBLL_IMUX16->CLBLL_L_B3": { + "src_wire": "CLBLL_IMUX16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B3" + }, + "CLBLL_R.CLBLL_IMUX43->CLBLL_LL_D6": { + "src_wire": "CLBLL_IMUX43", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D6" + }, + "CLBLL_R.CLBLL_IMUX46->CLBLL_L_D5": { + "src_wire": "CLBLL_IMUX46", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D5" + }, + "CLBLL_R.CLBLL_LL_C1->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_R.CLBLL_L_C1->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_R.CLBLL_BYP5->CLBLL_L_BX": { + "src_wire": "CLBLL_BYP5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_BX" + }, + "CLBLL_R.CLBLL_LL_CMUX->CLBLL_LOGIC_OUTS22": { + "src_wire": "CLBLL_LL_CMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS22" + }, + "CLBLL_R.CLBLL_LL_C2->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_R.CLBLL_L_C->CLBLL_LOGIC_OUTS10": { + "src_wire": "CLBLL_L_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS10" + }, + "CLBLL_R.CLBLL_IMUX41->CLBLL_L_D1": { + "src_wire": "CLBLL_IMUX41", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D1" + }, + "CLBLL_R.CLBLL_LL_C3->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_R.CLBLL_L_C->>CLBLL_L_CMUX": { + "src_wire": "CLBLL_L_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_CMUX" + }, + "CLBLL_R.CLBLL_IMUX28->CLBLL_LL_C4": { + "src_wire": "CLBLL_IMUX28", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C4" + }, + "CLBLL_R.CLBLL_IMUX39->CLBLL_L_D3": { + "src_wire": "CLBLL_IMUX39", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_D3" + }, + "CLBLL_R.CLBLL_LL_C6->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_R.CLBLL_L_B6->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_R.CLBLL_LL_A2->>CLBLL_LL_A": { + "src_wire": "CLBLL_LL_A2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_A" + }, + "CLBLL_R.CLBLL_L_D3->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_R.CLBLL_LL_C5->>CLBLL_LL_C": { + "src_wire": "CLBLL_LL_C5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_C" + }, + "CLBLL_R.CLBLL_L_A1->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_R.CLBLL_BYP1->CLBLL_LL_AX": { + "src_wire": "CLBLL_BYP1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_AX" + }, + "CLBLL_R.CLBLL_L_C3->>CLBLL_L_C": { + "src_wire": "CLBLL_L_C3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_C" + }, + "CLBLL_R.CLBLL_IMUX30->CLBLL_L_C5": { + "src_wire": "CLBLL_IMUX30", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C5" + }, + "CLBLL_R.CLBLL_L_B->>CLBLL_L_BMUX": { + "src_wire": "CLBLL_L_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_BMUX" + }, + "CLBLL_R.CLBLL_IMUX19->CLBLL_L_B2": { + "src_wire": "CLBLL_IMUX19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B2" + }, + "CLBLL_R.CLBLL_L_B5->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_R.CLBLL_BYP4->CLBLL_LL_BX": { + "src_wire": "CLBLL_BYP4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_BX" + }, + "CLBLL_R.CLBLL_LL_CQ->CLBLL_LOGIC_OUTS6": { + "src_wire": "CLBLL_LL_CQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS6" + }, + "CLBLL_R.CLBLL_LL_D2->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_R.CLBLL_IMUX34->CLBLL_L_C6": { + "src_wire": "CLBLL_IMUX34", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C6" + }, + "CLBLL_R.CLBLL_IMUX7->CLBLL_LL_A1": { + "src_wire": "CLBLL_IMUX7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_A1" + }, + "CLBLL_R.CLBLL_IMUX38->CLBLL_LL_D3": { + "src_wire": "CLBLL_IMUX38", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D3" + }, + "CLBLL_R.CLBLL_L_A4->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_R.CLBLL_L_D2->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_R.CLBLL_IMUX14->CLBLL_L_B1": { + "src_wire": "CLBLL_IMUX14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_B1" + }, + "CLBLL_R.CLBLL_IMUX47->CLBLL_LL_D5": { + "src_wire": "CLBLL_IMUX47", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_D5" + }, + "CLBLL_R.CLBLL_L_COUT->CLBLL_L_COUT_N": { + "src_wire": "CLBLL_L_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_COUT_N" + }, + "CLBLL_R.CLBLL_L_A3->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_R.CLBLL_IMUX9->CLBLL_L_A5": { + "src_wire": "CLBLL_IMUX9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A5" + }, + "CLBLL_R.CLBLL_L_CMUX->CLBLL_LOGIC_OUTS18": { + "src_wire": "CLBLL_L_CMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS18" + }, + "CLBLL_R.CLBLL_LL_D4->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_R.CLBLL_LL_D5->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_R.CLBLL_L_A->>CLBLL_L_AMUX": { + "src_wire": "CLBLL_L_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_AMUX" + }, + "CLBLL_R.CLBLL_IMUX20->CLBLL_L_C2": { + "src_wire": "CLBLL_IMUX20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_C2" + }, + "CLBLL_R.CLBLL_LL_DQ->CLBLL_LOGIC_OUTS7": { + "src_wire": "CLBLL_LL_DQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS7" + }, + "CLBLL_R.CLBLL_IMUX0->CLBLL_L_A3": { + "src_wire": "CLBLL_IMUX0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A3" + }, + "CLBLL_R.CLBLL_IMUX5->CLBLL_L_A6": { + "src_wire": "CLBLL_IMUX5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_A6" + }, + "CLBLL_R.CLBLL_LL_B2->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" + }, + "CLBLL_R.CLBLL_L_A6->>CLBLL_L_A": { + "src_wire": "CLBLL_L_A6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_A" + }, + "CLBLL_R.CLBLL_L_D5->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_R.CLBLL_IMUX27->CLBLL_LL_B4": { + "src_wire": "CLBLL_IMUX27", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_B4" + }, + "CLBLL_R.CLBLL_LL_D3->>CLBLL_LL_D": { + "src_wire": "CLBLL_LL_D3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_D" + }, + "CLBLL_R.CLBLL_L_DQ->CLBLL_LOGIC_OUTS3": { + "src_wire": "CLBLL_L_DQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS3" + }, + "CLBLL_R.CLBLL_L_B2->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_R.CLBLL_BYP7->CLBLL_L_DX": { + "src_wire": "CLBLL_BYP7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_L_DX" + }, + "CLBLL_R.CLBLL_L_D1->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_R.CLBLL_L_B3->>CLBLL_L_B": { + "src_wire": "CLBLL_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_B" + }, + "CLBLL_R.CLBLL_CTRL1->CLBLL_LL_SR": { + "src_wire": "CLBLL_CTRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_SR" + }, + "CLBLL_R.CLBLL_IMUX29->CLBLL_LL_C2": { + "src_wire": "CLBLL_IMUX29", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LL_C2" + }, + "CLBLL_R.CLBLL_L_D4->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_R.CLBLL_LL_B6->>CLBLL_LL_B": { + "src_wire": "CLBLL_LL_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_LL_B" + }, + "CLBLL_R.CLBLL_L_D6->>CLBLL_L_D": { + "src_wire": "CLBLL_L_D6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLL_L_D" + }, + "CLBLL_R.CLBLL_LL_BQ->CLBLL_LOGIC_OUTS5": { + "src_wire": "CLBLL_LL_BQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLL_LOGIC_OUTS5" } }, - "tile_type": "CLBLL_R" + "wires": [ + "CLBLL_EL1BEG2", + "CLBLL_IMUX24", + "CLBLL_LOGIC_OUTS10", + "CLBLL_LL_B", + "CLBLL_LH8", + "CLBLL_NW4END1", + "CLBLL_WR1END2", + "CLBLL_NE4BEG1", + "CLBLL_NE4BEG2", + "CLBLL_L_D5", + "CLBLL_LOGIC_OUTS2", + "CLBLL_EE4BEG3", + "CLBLL_WW4END3", + "CLBLL_L_CLK", + "CLBLL_CTRL1", + "CLBLL_IMUX8", + "CLBLL_WW4B1", + "CLBLL_IMUX43", + "CLBLL_L_D4", + "CLBLL_IMUX20", + "CLBLL_SW4END2", + "CLBLL_IMUX41", + "CLBLL_SE4C0", + "CLBLL_EE2BEG1", + "CLBLL_BYP1", + "CLBLL_WW4C1", + "CLBLL_EE2BEG0", + "CLBLL_LL_BMUX", + "CLBLL_WL1END2", + "CLBLL_IMUX12", + "CLBLL_LL_D4", + "CLBLL_BYP2", + "CLBLL_EE2A3", + "CLBLL_LOGIC_OUTS6", + "CLBLL_SE2A0", + "CLBLL_ER1BEG2", + "CLBLL_IMUX21", + "CLBLL_LOGIC_OUTS18", + "CLBLL_LL_CX", + "CLBLL_LL_D6", + "CLBLL_L_SR", + "CLBLL_IMUX45", + "CLBLL_IMUX25", + "CLBLL_LOGIC_OUTS19", + "CLBLL_LL_CLK", + "CLBLL_L_DX", + "CLBLL_SE2A1", + "CLBLL_EL1BEG1", + "CLBLL_IMUX9", + "CLBLL_NW2A3", + "CLBLL_MONITOR_N", + "CLBLL_WW2A0", + "CLBLL_LOGIC_OUTS22", + "CLBLL_NE2A1", + "CLBLL_LL_A5", + "CLBLL_WW2A3", + "CLBLL_FAN7", + "CLBLL_WW2END0", + "CLBLL_LOGIC_OUTS4", + "CLBLL_LOGIC_OUTS12", + "CLBLL_LL_CIN", + "CLBLL_L_AX", + "CLBLL_WW4A1", + "CLBLL_L_D2", + "CLBLL_SW4A1", + "CLBLL_LL_CMUX", + "CLBLL_WR1END0", + "CLBLL_LL_A3", + "CLBLL_LL_BQ", + "CLBLL_NW2A1", + "CLBLL_LL_DX", + "CLBLL_LOGIC_OUTS0", + "CLBLL_SE4BEG2", + "CLBLL_IMUX39", + "CLBLL_LH7", + "CLBLL_WW2A1", + "CLBLL_IMUX3", + "CLBLL_EE4C0", + "CLBLL_EE4C2", + "CLBLL_L_B4", + "CLBLL_L_DQ", + "CLBLL_LOGIC_OUTS9", + "CLBLL_NW4A2", + "CLBLL_WW2END2", + "CLBLL_L_C", + "CLBLL_BYP3", + "CLBLL_NE2A0", + "CLBLL_L_A3", + "CLBLL_IMUX31", + "CLBLL_IMUX32", + "CLBLL_WW2END1", + "CLBLL_NW4A3", + "CLBLL_FAN4", + "CLBLL_IMUX14", + "CLBLL_EE4B2", + "CLBLL_LL_D5", + "CLBLL_L_A2", + "CLBLL_IMUX47", + "CLBLL_EE4BEG1", + "CLBLL_NE4C2", + "CLBLL_IMUX29", + "CLBLL_NW4END0", + "CLBLL_L_B5", + "CLBLL_LL_D1", + "CLBLL_EL1BEG3", + "CLBLL_LH1", + "CLBLL_LL_C", + "CLBLL_LOGIC_OUTS13", + "CLBLL_SE4C3", + "CLBLL_NW2A2", + "CLBLL_L_DMUX", + "CLBLL_IMUX35", + "CLBLL_NE2A2", + "CLBLL_LL_C3", + "CLBLL_IMUX42", + "CLBLL_EE4A0", + "CLBLL_IMUX26", + "CLBLL_WL1END3", + "CLBLL_IMUX10", + "CLBLL_WL1END1", + "CLBLL_WW4B3", + "CLBLL_LL_C4", + "CLBLL_L_C3", + "CLBLL_BYP7", + "CLBLL_IMUX33", + "CLBLL_SE2A3", + "CLBLL_LOGIC_OUTS23", + "CLBLL_WR1END3", + "CLBLL_LH11", + "CLBLL_FAN1", + "CLBLL_IMUX23", + "CLBLL_IMUX36", + "CLBLL_WW4END0", + "CLBLL_IMUX1", + "CLBLL_SW4A3", + "CLBLL_MONITOR_P", + "CLBLL_LL_CQ", + "CLBLL_L_A5", + "CLBLL_EE4BEG2", + "CLBLL_EE4A2", + "CLBLL_WW4END1", + "CLBLL_LL_AMUX", + "CLBLL_LL_A6", + "CLBLL_L_B6", + "CLBLL_NW4END2", + "CLBLL_EE2BEG2", + "CLBLL_L_B2", + "CLBLL_NW4A1", + "CLBLL_SW4A2", + "CLBLL_IMUX11", + "CLBLL_IMUX27", + "CLBLL_WW4A0", + "CLBLL_IMUX28", + "CLBLL_LH5", + "CLBLL_LL_A1", + "CLBLL_NE4BEG0", + "CLBLL_NE4C1", + "CLBLL_EE4A3", + "CLBLL_LL_A4", + "CLBLL_LL_C5", + "CLBLL_ER1BEG0", + "CLBLL_WL1END0", + "CLBLL_BYP4", + "CLBLL_IMUX4", + "CLBLL_WW4A2", + "CLBLL_SW2A1", + "CLBLL_FAN3", + "CLBLL_NE4C0", + "CLBLL_L_COUT_N", + "CLBLL_SW2A2", + "CLBLL_L_CQ", + "CLBLL_BYP6", + "CLBLL_BYP5", + "CLBLL_L_D3", + "CLBLL_L_C6", + "CLBLL_LOGIC_OUTS1", + "CLBLL_IMUX37", + "CLBLL_WW4C2", + "CLBLL_SW4END3", + "CLBLL_LL_COUT_N", + "CLBLL_EE4B1", + "CLBLL_SW4END0", + "CLBLL_LL_B5", + "CLBLL_LOGIC_OUTS17", + "CLBLL_IMUX5", + "CLBLL_WW4A3", + "CLBLL_EE2BEG3", + "CLBLL_L_CE", + "CLBLL_EE2A2", + "CLBLL_L_C5", + "CLBLL_L_D6", + "CLBLL_IMUX13", + "CLBLL_L_BQ", + "CLBLL_L_C4", + "CLBLL_LOGIC_OUTS14", + "CLBLL_L_A4", + "CLBLL_FAN5", + "CLBLL_IMUX15", + "CLBLL_LOGIC_OUTS20", + "CLBLL_SE4C2", + "CLBLL_LH10", + "CLBLL_LL_BX", + "CLBLL_LH2", + "CLBLL_LH6", + "CLBLL_NE4BEG3", + "CLBLL_L_A", + "CLBLL_NE2A3", + "CLBLL_EE2A0", + "CLBLL_EE4C1", + "CLBLL_ER1BEG1", + "CLBLL_NW2A0", + "CLBLL_L_D", + "CLBLL_EE4C3", + "CLBLL_LH12", + "CLBLL_L_CMUX", + "CLBLL_IMUX0", + "CLBLL_LOGIC_OUTS15", + "CLBLL_LL_A", + "CLBLL_L_CX", + "CLBLL_IMUX44", + "CLBLL_IMUX30", + "CLBLL_ER1BEG3", + "CLBLL_EE4A1", + "CLBLL_LOGIC_OUTS5", + "CLBLL_L_BX", + "CLBLL_LL_AX", + "CLBLL_EL1BEG0", + "CLBLL_WW2A2", + "CLBLL_SW2A0", + "CLBLL_SE4C1", + "CLBLL_CTRL0", + "CLBLL_CLK1", + "CLBLL_NE4C3", + "CLBLL_WW4END2", + "CLBLL_LL_DQ", + "CLBLL_FAN6", + "CLBLL_WW4B2", + "CLBLL_WW4C3", + "CLBLL_IMUX40", + "CLBLL_LOGIC_OUTS8", + "CLBLL_LL_COUT", + "CLBLL_LL_D2", + "CLBLL_BYP0", + "CLBLL_LH4", + "CLBLL_L_AQ", + "CLBLL_IMUX19", + "CLBLL_WW4C0", + "CLBLL_SE4BEG3", + "CLBLL_IMUX18", + "CLBLL_FAN0", + "CLBLL_IMUX38", + "CLBLL_IMUX6", + "CLBLL_L_COUT", + "CLBLL_LL_B6", + "CLBLL_LL_A2", + "CLBLL_L_B", + "CLBLL_L_C2", + "CLBLL_EE4B3", + "CLBLL_LL_B4", + "CLBLL_LOGIC_OUTS16", + "CLBLL_L_A6", + "CLBLL_SW4A0", + "CLBLL_LL_B2", + "CLBLL_LL_C1", + "CLBLL_L_A1", + "CLBLL_LL_CE", + "CLBLL_L_D1", + "CLBLL_NW4A0", + "CLBLL_SW2A3", + "CLBLL_L_B3", + "CLBLL_L_BMUX", + "CLBLL_L_AMUX", + "CLBLL_WW2END3", + "CLBLL_EE2A1", + "CLBLL_LOGIC_OUTS21", + "CLBLL_SW4END1", + "CLBLL_LL_D", + "CLBLL_L_C1", + "CLBLL_L_CIN", + "CLBLL_LL_DMUX", + "CLBLL_LL_B3", + "CLBLL_IMUX7", + "CLBLL_IMUX34", + "CLBLL_IMUX22", + "CLBLL_CLK0", + "CLBLL_SE4BEG1", + "CLBLL_LL_C6", + "CLBLL_FAN2", + "CLBLL_IMUX46", + "CLBLL_L_B1", + "CLBLL_LOGIC_OUTS7", + "CLBLL_LOGIC_OUTS11", + "CLBLL_WW4B0", + "CLBLL_LH9", + "CLBLL_LL_B1", + "CLBLL_LL_AQ", + "CLBLL_LL_D3", + "CLBLL_LL_C2", + "CLBLL_SE2A2", + "CLBLL_SE4BEG0", + "CLBLL_IMUX16", + "CLBLL_EE4BEG0", + "CLBLL_WR1END1", + "CLBLL_LH3", + "CLBLL_EE4B0", + "CLBLL_LOGIC_OUTS3", + "CLBLL_LL_SR", + "CLBLL_NW4END3", + "CLBLL_IMUX17", + "CLBLL_IMUX2" + ], + "tile_type": "CLBLL_R", + "sites": [ + { + "site_pins": { + "BQ": "CLBLL_LL_BQ", + "CX": "CLBLL_LL_CX", + "C1": "CLBLL_LL_C1", + "B6": "CLBLL_LL_B6", + "DMUX": "CLBLL_LL_DMUX", + "SR": "CLBLL_LL_SR", + "B": "CLBLL_LL_B", + "D6": "CLBLL_LL_D6", + "D5": "CLBLL_LL_D5", + "A5": "CLBLL_LL_A5", + "AMUX": "CLBLL_LL_AMUX", + "C6": "CLBLL_LL_C6", + "AQ": "CLBLL_LL_AQ", + "B5": "CLBLL_LL_B5", + "B3": "CLBLL_LL_B3", + "DQ": "CLBLL_LL_DQ", + "D3": "CLBLL_LL_D3", + "C": "CLBLL_LL_C", + "DX": "CLBLL_LL_DX", + "C4": "CLBLL_LL_C4", + "A4": "CLBLL_LL_A4", + "A1": "CLBLL_LL_A1", + "D1": "CLBLL_LL_D1", + "BX": "CLBLL_LL_BX", + "COUT": "CLBLL_LL_COUT", + "CLK": "CLBLL_LL_CLK", + "D": "CLBLL_LL_D", + "A2": "CLBLL_LL_A2", + "CQ": "CLBLL_LL_CQ", + "D4": "CLBLL_LL_D4", + "C5": "CLBLL_LL_C5", + "CIN": "CLBLL_LL_CIN", + "D2": "CLBLL_LL_D2", + "B2": "CLBLL_LL_B2", + "A6": "CLBLL_LL_A6", + "CMUX": "CLBLL_LL_CMUX", + "A3": "CLBLL_LL_A3", + "C3": "CLBLL_LL_C3", + "AX": "CLBLL_LL_AX", + "B1": "CLBLL_LL_B1", + "B4": "CLBLL_LL_B4", + "A": "CLBLL_LL_A", + "BMUX": "CLBLL_LL_BMUX", + "CE": "CLBLL_LL_CE", + "C2": "CLBLL_LL_C2" + }, + "type": "SLICEL", + "prefix": "SLICE", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BQ": "CLBLL_L_BQ", + "CX": "CLBLL_L_CX", + "C1": "CLBLL_L_C1", + "B6": "CLBLL_L_B6", + "DMUX": "CLBLL_L_DMUX", + "SR": "CLBLL_L_SR", + "B": "CLBLL_L_B", + "D6": "CLBLL_L_D6", + "D5": "CLBLL_L_D5", + "A5": "CLBLL_L_A5", + "AMUX": "CLBLL_L_AMUX", + "C6": "CLBLL_L_C6", + "AQ": "CLBLL_L_AQ", + "B5": "CLBLL_L_B5", + "B3": "CLBLL_L_B3", + "DQ": "CLBLL_L_DQ", + "D3": "CLBLL_L_D3", + "C": "CLBLL_L_C", + "DX": "CLBLL_L_DX", + "C4": "CLBLL_L_C4", + "A4": "CLBLL_L_A4", + "A1": "CLBLL_L_A1", + "D1": "CLBLL_L_D1", + "BX": "CLBLL_L_BX", + "COUT": "CLBLL_L_COUT", + "CLK": "CLBLL_L_CLK", + "D": "CLBLL_L_D", + "A2": "CLBLL_L_A2", + "CQ": "CLBLL_L_CQ", + "D4": "CLBLL_L_D4", + "C5": "CLBLL_L_C5", + "CIN": "CLBLL_L_CIN", + "D2": "CLBLL_L_D2", + "B2": "CLBLL_L_B2", + "A6": "CLBLL_L_A6", + "CMUX": "CLBLL_L_CMUX", + "A3": "CLBLL_L_A3", + "C3": "CLBLL_L_C3", + "AX": "CLBLL_L_AX", + "B1": "CLBLL_L_B1", + "B4": "CLBLL_L_B4", + "A": "CLBLL_L_A", + "BMUX": "CLBLL_L_BMUX", + "CE": "CLBLL_L_CE", + "C2": "CLBLL_L_C2" + }, + "type": "SLICEL", + "prefix": "SLICE", + "name": "X1Y0", + "x_coord": 1, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLBLM_L.json b/artix7/tile_type_CLBLM_L.json index 63f4a12..da97672 100644 --- a/artix7/tile_type_CLBLM_L.json +++ b/artix7/tile_type_CLBLM_L.json @@ -1,1494 +1,1494 @@ { - "wires": [ - "CLBLM_NE2A0", - "CLBLM_NW4END1", - "CLBLM_ER1BEG1", - "CLBLM_L_A3", - "CLBLM_M_BQ", - "CLBLM_WW4B2", - "CLBLM_WR1END3", - "CLBLM_NW4A1", - "CLBLM_IMUX7", - "CLBLM_L_D4", - "CLBLM_LOGIC_OUTS17", - "CLBLM_FAN3", - "CLBLM_L_A1", - "CLBLM_M_D2", - "CLBLM_L_C6", - "CLBLM_SW2A2", - "CLBLM_EE4B0", - "CLBLM_LOGIC_OUTS14", - "CLBLM_L_AQ", - "CLBLM_M_B1", - "CLBLM_SE2A3", - "CLBLM_L_A4", - "CLBLM_M_D6", - "CLBLM_IMUX39", - "CLBLM_NW4A0", - "CLBLM_M_B5", - "CLBLM_SW4END1", - "CLBLM_NW2A3", - "CLBLM_NE4C3", - "CLBLM_LH11", - "CLBLM_WW4END1", - "CLBLM_M_A2", - "CLBLM_SE4BEG2", - "CLBLM_EE2BEG1", - "CLBLM_L_A", - "CLBLM_M_BX", - "CLBLM_IMUX16", - "CLBLM_IMUX9", - "CLBLM_M_AI", - "CLBLM_M_C6", - "CLBLM_IMUX32", - "CLBLM_L_B", - "CLBLM_IMUX17", - "CLBLM_BYP7", - "CLBLM_NW4END2", - "CLBLM_IMUX26", - "CLBLM_L_B5", - "CLBLM_IMUX22", - "CLBLM_M_BMUX", - "CLBLM_L_D5", - "CLBLM_LH6", - "CLBLM_SW4A2", - "CLBLM_WR1END2", - "CLBLM_L_DQ", - "CLBLM_WW4A1", - "CLBLM_IMUX28", - "CLBLM_LOGIC_OUTS23", - "CLBLM_WW4A0", - "CLBLM_L_BQ", - "CLBLM_L_SR", - "CLBLM_LOGIC_OUTS11", - "CLBLM_EE4C2", - "CLBLM_L_B2", - "CLBLM_L_A5", - "CLBLM_NE4BEG0", - "CLBLM_M_CQ", - "CLBLM_MONITOR_P", - "CLBLM_M_B2", - "CLBLM_IMUX19", - "CLBLM_L_D", - "CLBLM_WW2END1", - "CLBLM_LOGIC_OUTS10", - "CLBLM_BYP3", - "CLBLM_FAN4", - "CLBLM_IMUX1", - "CLBLM_LOGIC_OUTS8", - "CLBLM_L_BMUX", - "CLBLM_NE2A1", - "CLBLM_EE4B1", - "CLBLM_IMUX13", - "CLBLM_L_CX", - "CLBLM_EE4C0", - "CLBLM_LOGIC_OUTS22", - "CLBLM_M_A4", - "CLBLM_IMUX23", - "CLBLM_WW2A3", - "CLBLM_EE4A0", - "CLBLM_M_CX", - "CLBLM_IMUX29", - "CLBLM_EE4A2", - "CLBLM_ER1BEG3", - "CLBLM_LH7", - "CLBLM_L_C1", - "CLBLM_EL1BEG1", - "CLBLM_LH12", - "CLBLM_SE4C0", - "CLBLM_NE4C1", - "CLBLM_CTRL0", - "CLBLM_M_C", - "CLBLM_IMUX36", - "CLBLM_EE2BEG2", - "CLBLM_IMUX44", - "CLBLM_WW4A3", - "CLBLM_L_CIN", - "CLBLM_M_CLK", - "CLBLM_IMUX27", - "CLBLM_EL1BEG3", - "CLBLM_SW2A3", - "CLBLM_SE2A2", - "CLBLM_LOGIC_OUTS3", - "CLBLM_LH9", - "CLBLM_SW4A0", - "CLBLM_M_C3", - "CLBLM_NE4BEG2", - "CLBLM_EE2A1", - "CLBLM_CLK1", - "CLBLM_NE4C0", - "CLBLM_L_C4", - "CLBLM_EE2A0", - "CLBLM_M_BI", - "CLBLM_LOGIC_OUTS20", - "CLBLM_EE2A3", - "CLBLM_LOGIC_OUTS21", - "CLBLM_BYP4", - "CLBLM_IMUX20", - "CLBLM_L_C5", - "CLBLM_M_C2", - "CLBLM_WW4B1", - "CLBLM_IMUX11", - "CLBLM_L_C2", - "CLBLM_BYP2", - "CLBLM_IMUX25", - "CLBLM_M_COUT", - "CLBLM_L_B3", - "CLBLM_M_DQ", - "CLBLM_IMUX40", - "CLBLM_WW4B0", - "CLBLM_EE4B2", - "CLBLM_L_BX", - "CLBLM_SW2A1", - "CLBLM_LOGIC_OUTS0", - "CLBLM_WW4END3", - "CLBLM_LH8", - "CLBLM_SW4END3", - "CLBLM_LH2", - "CLBLM_M_D1", - "CLBLM_M_A3", - "CLBLM_LOGIC_OUTS19", - "CLBLM_L_CQ", - "CLBLM_M_C1", - "CLBLM_WW2END3", - "CLBLM_WR1END0", - "CLBLM_WL1END0", - "CLBLM_M_B", - "CLBLM_L_B4", - "CLBLM_ER1BEG0", - "CLBLM_WW4END2", - "CLBLM_M_AQ", - "CLBLM_M_CIN", - "CLBLM_FAN0", - "CLBLM_L_AX", - "CLBLM_EE4A3", - "CLBLM_SW4END0", - "CLBLM_WL1END3", - "CLBLM_IMUX3", - "CLBLM_LOGIC_OUTS15", - "CLBLM_LOGIC_OUTS5", - "CLBLM_M_D3", - "CLBLM_FAN5", - "CLBLM_WW4A2", - "CLBLM_EE2A2", - "CLBLM_SW4A1", - "CLBLM_WL1END1", - "CLBLM_NW4A2", - "CLBLM_NE2A3", - "CLBLM_WL1END2", - "CLBLM_LH5", - "CLBLM_M_CE", - "CLBLM_IMUX5", - "CLBLM_LOGIC_OUTS9", - "CLBLM_M_D", - "CLBLM_BYP1", - "CLBLM_SE4BEG1", - "CLBLM_CTRL1", - "CLBLM_ER1BEG2", - "CLBLM_M_A5", - "CLBLM_IMUX12", - "CLBLM_SE2A1", - "CLBLM_L_DMUX", - "CLBLM_IMUX14", - "CLBLM_M_A6", - "CLBLM_L_D1", - "CLBLM_M_B4", - "CLBLM_L_AMUX", - "CLBLM_NW4A3", - "CLBLM_L_COUT", - "CLBLM_WW4C2", - "CLBLM_MONITOR_N", - "CLBLM_SE4BEG3", - "CLBLM_WW4B3", - "CLBLM_M_D4", - "CLBLM_M_DX", - "CLBLM_IMUX30", - "CLBLM_SW2A0", - "CLBLM_NW2A0", - "CLBLM_IMUX31", - "CLBLM_SE4BEG0", - "CLBLM_IMUX37", - "CLBLM_NW2A1", - "CLBLM_M_C4", - "CLBLM_M_A", - "CLBLM_EE4BEG3", - "CLBLM_BYP0", - "CLBLM_FAN1", - "CLBLM_IMUX46", - "CLBLM_FAN2", - "CLBLM_LOGIC_OUTS12", - "CLBLM_L_CE", - "CLBLM_WW2A1", - "CLBLM_FAN7", - "CLBLM_LH3", - "CLBLM_LOGIC_OUTS7", - "CLBLM_M_B3", - "CLBLM_NW4END0", - "CLBLM_IMUX47", - "CLBLM_NE4BEG1", - "CLBLM_EE4BEG1", - "CLBLM_IMUX8", - "CLBLM_LOGIC_OUTS18", - "CLBLM_IMUX2", - "CLBLM_IMUX21", - "CLBLM_IMUX41", - "CLBLM_IMUX42", - "CLBLM_IMUX35", - "CLBLM_IMUX4", - "CLBLM_L_A6", - "CLBLM_M_B6", - "CLBLM_IMUX43", - "CLBLM_SE4C3", - "CLBLM_WW2END0", - "CLBLM_FAN6", - "CLBLM_L_A2", - "CLBLM_WW4C3", - "CLBLM_IMUX6", - "CLBLM_L_D2", - "CLBLM_EL1BEG0", - "CLBLM_M_AMUX", - "CLBLM_SE2A0", - "CLBLM_LH4", - "CLBLM_IMUX38", - "CLBLM_LH10", - "CLBLM_EE4BEG0", - "CLBLM_NW2A2", - "CLBLM_EE2BEG3", - "CLBLM_NE4C2", - "CLBLM_L_COUT_N", - "CLBLM_WR1END1", - "CLBLM_LOGIC_OUTS6", - "CLBLM_L_C", - "CLBLM_IMUX0", - "CLBLM_M_CMUX", - "CLBLM_WW4END0", - "CLBLM_SE4C1", - "CLBLM_M_COUT_N", - "CLBLM_M_C5", - "CLBLM_IMUX34", - "CLBLM_EE4B3", - "CLBLM_LH1", - "CLBLM_LOGIC_OUTS13", - "CLBLM_M_A1", - "CLBLM_IMUX33", - "CLBLM_NE2A2", - "CLBLM_EE4C3", - "CLBLM_IMUX24", - "CLBLM_LOGIC_OUTS4", - "CLBLM_WW2END2", - "CLBLM_EL1BEG2", - "CLBLM_M_DMUX", - "CLBLM_IMUX18", - "CLBLM_EE4BEG2", - "CLBLM_BYP6", - "CLBLM_L_D3", - "CLBLM_WW2A0", - "CLBLM_L_B1", - "CLBLM_LOGIC_OUTS16", - "CLBLM_IMUX15", - "CLBLM_L_CMUX", - "CLBLM_WW2A2", - "CLBLM_L_C3", - "CLBLM_LOGIC_OUTS1", - "CLBLM_SE4C2", - "CLBLM_IMUX10", - "CLBLM_NW4END3", - "CLBLM_SW4A3", - "CLBLM_WW4C1", - "CLBLM_EE2BEG0", - "CLBLM_M_WE", - "CLBLM_L_CLK", - "CLBLM_EE4C1", - "CLBLM_BYP5", - "CLBLM_EE4A1", - "CLBLM_L_DX", - "CLBLM_IMUX45", - "CLBLM_L_D6", - "CLBLM_M_AX", - "CLBLM_M_CI", - "CLBLM_LOGIC_OUTS2", - "CLBLM_L_B6", - "CLBLM_WW4C0", - "CLBLM_M_D5", - "CLBLM_NE4BEG3", - "CLBLM_M_DI", - "CLBLM_M_SR", - "CLBLM_SW4END2", - "CLBLM_CLK0" - ], - "sites": [ - { - "prefix": "SLICE", - "y_coord": 0, - "type": "SLICEL", - "site_pins": { - "CX": "CLBLM_L_CX", - "CMUX": "CLBLM_L_CMUX", - "D1": "CLBLM_L_D1", - "CE": "CLBLM_L_CE", - "C5": "CLBLM_L_C5", - "D": "CLBLM_L_D", - "B1": "CLBLM_L_B1", - "C2": "CLBLM_L_C2", - "A2": "CLBLM_L_A2", - "CQ": "CLBLM_L_CQ", - "AMUX": "CLBLM_L_AMUX", - "BQ": "CLBLM_L_BQ", - "D3": "CLBLM_L_D3", - "B6": "CLBLM_L_B6", - "CLK": "CLBLM_L_CLK", - "SR": "CLBLM_L_SR", - "C6": "CLBLM_L_C6", - "AQ": "CLBLM_L_AQ", - "A": "CLBLM_L_A", - "B5": "CLBLM_L_B5", - "C1": "CLBLM_L_C1", - "D5": "CLBLM_L_D5", - "DMUX": "CLBLM_L_DMUX", - "DQ": "CLBLM_L_DQ", - "A6": "CLBLM_L_A6", - "D4": "CLBLM_L_D4", - "D6": "CLBLM_L_D6", - "C3": "CLBLM_L_C3", - "D2": "CLBLM_L_D2", - "B2": "CLBLM_L_B2", - "BX": "CLBLM_L_BX", - "BMUX": "CLBLM_L_BMUX", - "AX": "CLBLM_L_AX", - "C4": "CLBLM_L_C4", - "B": "CLBLM_L_B", - "A3": "CLBLM_L_A3", - "C": "CLBLM_L_C", - "COUT": "CLBLM_L_COUT", - "B4": "CLBLM_L_B4", - "A5": "CLBLM_L_A5", - "CIN": "CLBLM_L_CIN", - "DX": "CLBLM_L_DX", - "A4": "CLBLM_L_A4", - "A1": "CLBLM_L_A1", - "B3": "CLBLM_L_B3" - }, - "x_coord": 1, - "name": "X1Y0" - }, - { - "prefix": "SLICE", - "y_coord": 0, - "type": "SLICEM", - "site_pins": { - "CX": "CLBLM_M_CX", - "CMUX": "CLBLM_M_CMUX", - "D1": "CLBLM_M_D1", - "CE": "CLBLM_M_CE", - "C5": "CLBLM_M_C5", - "D": "CLBLM_M_D", - "B1": "CLBLM_M_B1", - "C2": "CLBLM_M_C2", - "A2": "CLBLM_M_A2", - "CQ": "CLBLM_M_CQ", - "CI": "CLBLM_M_CI", - "DI": "CLBLM_M_DI", - "AMUX": "CLBLM_M_AMUX", - "BQ": "CLBLM_M_BQ", - "D3": "CLBLM_M_D3", - "B6": "CLBLM_M_B6", - "CLK": "CLBLM_M_CLK", - "SR": "CLBLM_M_SR", - "C6": "CLBLM_M_C6", - "BI": "CLBLM_M_BI", - "AQ": "CLBLM_M_AQ", - "A": "CLBLM_M_A", - "B5": "CLBLM_M_B5", - "WE": "CLBLM_M_WE", - "C1": "CLBLM_M_C1", - "D5": "CLBLM_M_D5", - "DMUX": "CLBLM_M_DMUX", - "DQ": "CLBLM_M_DQ", - "A6": "CLBLM_M_A6", - "D4": "CLBLM_M_D4", - "D6": "CLBLM_M_D6", - "C3": "CLBLM_M_C3", - "D2": "CLBLM_M_D2", - "B2": "CLBLM_M_B2", - "BX": "CLBLM_M_BX", - "BMUX": "CLBLM_M_BMUX", - "AX": "CLBLM_M_AX", - "C4": "CLBLM_M_C4", - "B": "CLBLM_M_B", - "A3": "CLBLM_M_A3", - "C": "CLBLM_M_C", - "COUT": "CLBLM_M_COUT", - "B4": "CLBLM_M_B4", - "A5": "CLBLM_M_A5", - "CIN": "CLBLM_M_CIN", - "AI": "CLBLM_M_AI", - "DX": "CLBLM_M_DX", - "A4": "CLBLM_M_A4", - "A1": "CLBLM_M_A1", - "B3": "CLBLM_M_B3" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "CLBLM_L.CLBLM_IMUX3->CLBLM_L_A2": { + "CLBLM_L.CLBLM_L_AQ->CLBLM_LOGIC_OUTS0": { + "src_wire": "CLBLM_L_AQ", "can_invert": "0", - "dst_wire": "CLBLM_L_A2", "is_directional": "1", - "src_wire": "CLBLM_IMUX3", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_FAN6->CLBLM_L_CE": { - "can_invert": "0", - "dst_wire": "CLBLM_L_CE", - "is_directional": "1", - "src_wire": "CLBLM_FAN6", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_CTRL0->CLBLM_L_SR": { - "can_invert": "0", - "dst_wire": "CLBLM_L_SR", - "is_directional": "1", - "src_wire": "CLBLM_CTRL0", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_A->>CLBLM_L_AMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_AMUX", - "is_directional": "1", - "src_wire": "CLBLM_L_A", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_A->CLBLM_LOGIC_OUTS8": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS8", - "is_directional": "1", - "src_wire": "CLBLM_L_A", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_CLK0->CLBLM_L_CLK": { - "can_invert": "0", - "dst_wire": "CLBLM_L_CLK", - "is_directional": "1", - "src_wire": "CLBLM_CLK0", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_AMUX->CLBLM_LOGIC_OUTS16": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS16", - "is_directional": "1", - "src_wire": "CLBLM_L_AMUX", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_FAN2->CLBLM_M_BI": { - "can_invert": "0", - "dst_wire": "CLBLM_M_BI", - "is_directional": "1", - "src_wire": "CLBLM_FAN2", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_A6->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A6", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX2->CLBLM_M_A2": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX2", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX24->CLBLM_M_B5": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX24", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_FAN3->CLBLM_M_DI": { - "can_invert": "0", - "dst_wire": "CLBLM_M_DI", - "is_directional": "1", - "src_wire": "CLBLM_FAN3", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_B4->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B4", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX10->CLBLM_L_A4": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX10", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_BYP1->CLBLM_M_AX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_AX", - "is_directional": "1", - "src_wire": "CLBLM_BYP1", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS6", - "is_directional": "1", - "src_wire": "CLBLM_M_CQ", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX15->CLBLM_M_B1": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX15", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_D2->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D2", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX22->CLBLM_M_C3": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX22", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_DMUX->CLBLM_LOGIC_OUTS19": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS19", - "is_directional": "1", - "src_wire": "CLBLM_L_DMUX", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_CLK1->CLBLM_M_CLK": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CLK", - "is_directional": "1", - "src_wire": "CLBLM_CLK1", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_COUT->>CLBLM_L_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_DMUX", - "is_directional": "1", - "src_wire": "CLBLM_L_COUT", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_D5->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D5", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_A3->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A3", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX16->CLBLM_L_B3": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX16", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX45->CLBLM_M_D2": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX45", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_A->CLBLM_LOGIC_OUTS12": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS12", - "is_directional": "1", - "src_wire": "CLBLM_M_A", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_B3->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B3", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX13->CLBLM_L_B6": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX13", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX5->CLBLM_L_A6": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX5", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX40->CLBLM_M_D1": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX40", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_A->>CLBLM_M_AMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_AMUX", - "is_directional": "1", - "src_wire": "CLBLM_M_A", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_COUT->>CLBLM_M_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_DMUX", - "is_directional": "1", - "src_wire": "CLBLM_M_COUT", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX42->CLBLM_L_D6": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX42", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS7", - "is_directional": "1", - "src_wire": "CLBLM_M_DQ", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX37->CLBLM_L_D4": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX37", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX38->CLBLM_M_D3": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX38", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS0" }, "CLBLM_L.CLBLM_IMUX43->CLBLM_M_D6": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D6", - "is_directional": "1", "src_wire": "CLBLM_IMUX43", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_B->CLBLM_LOGIC_OUTS13": { "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS13", "is_directional": "1", - "src_wire": "CLBLM_M_B", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D6" }, - "CLBLM_L.CLBLM_IMUX19->CLBLM_L_B2": { + "CLBLM_L.CLBLM_FAN6->CLBLM_L_CE": { + "src_wire": "CLBLM_FAN6", "can_invert": "0", - "dst_wire": "CLBLM_L_B2", "is_directional": "1", - "src_wire": "CLBLM_IMUX19", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX28->CLBLM_M_C4": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX28", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CE" }, "CLBLM_L.CLBLM_L_C->>CLBLM_L_CMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_CMUX", - "is_directional": "1", "src_wire": "CLBLM_L_C", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX46->CLBLM_L_D5": { "can_invert": "0", - "dst_wire": "CLBLM_L_D5", "is_directional": "1", - "src_wire": "CLBLM_IMUX46", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX25->CLBLM_L_B5": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX25", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_A6->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A6", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_D6->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D6", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_BYP0->CLBLM_L_AX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_AX", - "is_directional": "1", - "src_wire": "CLBLM_BYP0", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_C4->>CLBLM_M_C": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C", - "is_directional": "1", - "src_wire": "CLBLM_M_C4", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX36->CLBLM_L_D2": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX36", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS15", - "is_directional": "1", - "src_wire": "CLBLM_M_D", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_C5->>CLBLM_M_C": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C", - "is_directional": "1", - "src_wire": "CLBLM_M_C5", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX4->CLBLM_M_A6": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX4", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX14->CLBLM_L_B1": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX14", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_BYP3->CLBLM_M_CX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CX", - "is_directional": "1", - "src_wire": "CLBLM_BYP3", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_A5->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A5", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX1->CLBLM_M_A3": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX1", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_FAN4->CLBLM_M_WE": { - "can_invert": "0", - "dst_wire": "CLBLM_M_WE", - "is_directional": "1", - "src_wire": "CLBLM_FAN4", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_C4->>CLBLM_L_C": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C", - "is_directional": "1", - "src_wire": "CLBLM_L_C4", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_BYP7->CLBLM_L_DX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_DX", - "is_directional": "1", - "src_wire": "CLBLM_BYP7", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_D2->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D2", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_CTRL1->CLBLM_M_SR": { - "can_invert": "0", - "dst_wire": "CLBLM_M_SR", - "is_directional": "1", - "src_wire": "CLBLM_CTRL1", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_C1->>CLBLM_L_C": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C", - "is_directional": "1", - "src_wire": "CLBLM_L_C1", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_A4->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A4", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_BQ->CLBLM_LOGIC_OUTS5": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS5", - "is_directional": "1", - "src_wire": "CLBLM_M_BQ", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_CMUX->CLBLM_LOGIC_OUTS22": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS22", - "is_directional": "1", - "src_wire": "CLBLM_M_CMUX", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_BYP4->CLBLM_M_BX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_BX", - "is_directional": "1", - "src_wire": "CLBLM_BYP4", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS17", - "is_directional": "1", - "src_wire": "CLBLM_L_BMUX", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_D6->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D6", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX17->CLBLM_M_B3": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX17", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX6->CLBLM_L_A1": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX6", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_A4->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A4", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_B->>CLBLM_M_BMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_BMUX", - "is_directional": "1", - "src_wire": "CLBLM_M_B", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_A3->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A3", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX32->CLBLM_M_C1": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX32", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX21->CLBLM_L_C4": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX21", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX18->CLBLM_M_B2": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX18", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX29->CLBLM_M_C2": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX29", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_COUT->CLBLM_M_COUT_N": { - "can_invert": "0", - "dst_wire": "CLBLM_M_COUT_N", - "is_directional": "1", - "src_wire": "CLBLM_M_COUT", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX34->CLBLM_L_C6": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX34", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_B3->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B3", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_BYP6->CLBLM_M_DX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_DX", - "is_directional": "1", - "src_wire": "CLBLM_BYP6", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_A1->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A1", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_D4->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D4", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS1", - "is_directional": "1", - "src_wire": "CLBLM_L_BQ", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_B6->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B6", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_C6->>CLBLM_M_C": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C", - "is_directional": "1", - "src_wire": "CLBLM_M_C6", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX27->CLBLM_M_B4": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX27", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_CMUX->CLBLM_LOGIC_OUTS18": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS18", - "is_directional": "1", - "src_wire": "CLBLM_L_CMUX", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_BYP5->CLBLM_L_BX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_BX", - "is_directional": "1", - "src_wire": "CLBLM_BYP5", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_FAN5->CLBLM_M_CI": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CI", - "is_directional": "1", - "src_wire": "CLBLM_FAN5", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_D->>CLBLM_L_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_DMUX", - "is_directional": "1", - "src_wire": "CLBLM_L_D", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX11->CLBLM_M_A4": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX11", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_B2->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B2", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_BYP2->CLBLM_L_CX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_CX", - "is_directional": "1", - "src_wire": "CLBLM_BYP2", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX44->CLBLM_M_D4": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX44", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_B6->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B6", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_D1->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D1", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_A2->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A2", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_C->>CLBLM_M_CMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CMUX", - "is_directional": "1", - "src_wire": "CLBLM_M_C", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX23->CLBLM_L_C3": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX23", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_FAN7->CLBLM_M_CE": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CE", - "is_directional": "1", - "src_wire": "CLBLM_FAN7", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_D->CLBLM_LOGIC_OUTS11": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS11", - "is_directional": "1", - "src_wire": "CLBLM_L_D", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_C6->>CLBLM_L_C": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C", - "is_directional": "1", - "src_wire": "CLBLM_L_C6", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_A1->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A1", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_B5->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B5", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX12->CLBLM_M_B6": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX12", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_D3->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D3", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_AQ->CLBLM_LOGIC_OUTS0": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS0", - "is_directional": "1", - "src_wire": "CLBLM_L_AQ", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_B1->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B1", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX39->CLBLM_L_D3": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX39", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_AMUX->CLBLM_LOGIC_OUTS20": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS20", - "is_directional": "1", - "src_wire": "CLBLM_M_AMUX", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_D5->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D5", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX26->CLBLM_L_B4": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX26", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_FAN0->CLBLM_M_AI": { - "can_invert": "0", - "dst_wire": "CLBLM_M_AI", - "is_directional": "1", - "src_wire": "CLBLM_FAN0", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX47->CLBLM_M_D5": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX47", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_D->>CLBLM_M_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_DMUX", - "is_directional": "1", - "src_wire": "CLBLM_M_D", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_C5->>CLBLM_L_C": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C", - "is_directional": "1", - "src_wire": "CLBLM_L_C5", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_CQ->CLBLM_LOGIC_OUTS2": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS2", - "is_directional": "1", - "src_wire": "CLBLM_L_CQ", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX31->CLBLM_M_C5": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX31", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_A2->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A2", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_A5->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A5", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX20->CLBLM_L_C2": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX20", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_B2->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B2", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_DQ->CLBLM_LOGIC_OUTS3": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS3", - "is_directional": "1", - "src_wire": "CLBLM_L_DQ", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX30->CLBLM_L_C5": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX30", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_D3->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D3", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_D1->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D1", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_C->CLBLM_LOGIC_OUTS10": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS10", - "is_directional": "1", - "src_wire": "CLBLM_L_C", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_B5->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B5", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_C3->>CLBLM_M_C": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C", - "is_directional": "1", - "src_wire": "CLBLM_M_C3", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_AQ->CLBLM_LOGIC_OUTS4": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS4", - "is_directional": "1", - "src_wire": "CLBLM_M_AQ", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_BMUX->CLBLM_LOGIC_OUTS21": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS21", - "is_directional": "1", - "src_wire": "CLBLM_M_BMUX", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_B->CLBLM_LOGIC_OUTS9": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS9", - "is_directional": "1", - "src_wire": "CLBLM_L_B", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_B1->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B1", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_L_D4->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D4", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_IMUX8->CLBLM_M_A5": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX8", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX33->CLBLM_L_C1": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX33", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX35->CLBLM_M_C6": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX35", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_C1->>CLBLM_M_C": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C", - "is_directional": "1", - "src_wire": "CLBLM_M_C1", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS23", - "is_directional": "1", - "src_wire": "CLBLM_M_DMUX", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_M_C2->>CLBLM_M_C": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C", - "is_directional": "1", - "src_wire": "CLBLM_M_C2", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_B4->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B4", - "is_pseudo": "1" - }, - "CLBLM_L.CLBLM_M_C->CLBLM_LOGIC_OUTS14": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS14", - "is_directional": "1", - "src_wire": "CLBLM_M_C", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_IMUX7->CLBLM_M_A1": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX7", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLM_L_CMUX" }, "CLBLM_L.CLBLM_L_COUT->CLBLM_L_COUT_N": { - "can_invert": "0", - "dst_wire": "CLBLM_L_COUT_N", - "is_directional": "1", "src_wire": "CLBLM_L_COUT", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_B->>CLBLM_L_BMUX": { "can_invert": "0", - "dst_wire": "CLBLM_L_BMUX", "is_directional": "1", - "src_wire": "CLBLM_L_B", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_L_COUT_N" }, - "CLBLM_L.CLBLM_L_C3->>CLBLM_L_C": { + "CLBLM_L.CLBLM_CLK1->CLBLM_M_CLK": { + "src_wire": "CLBLM_CLK1", "can_invert": "0", - "dst_wire": "CLBLM_L_C", "is_directional": "1", - "src_wire": "CLBLM_L_C3", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CLK" }, - "CLBLM_L.CLBLM_IMUX0->CLBLM_L_A3": { + "CLBLM_L.CLBLM_L_A->CLBLM_LOGIC_OUTS8": { + "src_wire": "CLBLM_L_A", "can_invert": "0", - "dst_wire": "CLBLM_L_A3", "is_directional": "1", - "src_wire": "CLBLM_IMUX0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS8" + }, + "CLBLM_L.CLBLM_IMUX2->CLBLM_M_A2": { + "src_wire": "CLBLM_IMUX2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A2" + }, + "CLBLM_L.CLBLM_BYP2->CLBLM_L_CX": { + "src_wire": "CLBLM_BYP2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CX" + }, + "CLBLM_L.CLBLM_IMUX37->CLBLM_L_D4": { + "src_wire": "CLBLM_IMUX37", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D4" + }, + "CLBLM_L.CLBLM_BYP3->CLBLM_M_CX": { + "src_wire": "CLBLM_BYP3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CX" + }, + "CLBLM_L.CLBLM_M_D5->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_L.CLBLM_L_A->>CLBLM_L_AMUX": { + "src_wire": "CLBLM_L_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_AMUX" + }, + "CLBLM_L.CLBLM_IMUX6->CLBLM_L_A1": { + "src_wire": "CLBLM_IMUX6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A1" + }, + "CLBLM_L.CLBLM_L_B1->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_L.CLBLM_BYP6->CLBLM_M_DX": { + "src_wire": "CLBLM_BYP6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_DX" + }, + "CLBLM_L.CLBLM_IMUX38->CLBLM_M_D3": { + "src_wire": "CLBLM_IMUX38", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D3" + }, + "CLBLM_L.CLBLM_M_D2->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_L.CLBLM_L_D->CLBLM_LOGIC_OUTS11": { + "src_wire": "CLBLM_L_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS11" + }, + "CLBLM_L.CLBLM_M_B3->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_L.CLBLM_M_B1->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_L.CLBLM_L_CMUX->CLBLM_LOGIC_OUTS18": { + "src_wire": "CLBLM_L_CMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS18" + }, + "CLBLM_L.CLBLM_IMUX17->CLBLM_M_B3": { + "src_wire": "CLBLM_IMUX17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B3" + }, + "CLBLM_L.CLBLM_M_A->CLBLM_LOGIC_OUTS12": { + "src_wire": "CLBLM_M_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS12" + }, + "CLBLM_L.CLBLM_IMUX44->CLBLM_M_D4": { + "src_wire": "CLBLM_IMUX44", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D4" }, "CLBLM_L.CLBLM_IMUX9->CLBLM_L_A5": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A5", - "is_directional": "1", "src_wire": "CLBLM_IMUX9", - "is_pseudo": "0" - }, - "CLBLM_L.CLBLM_L_C2->>CLBLM_L_C": { "can_invert": "0", - "dst_wire": "CLBLM_L_C", "is_directional": "1", - "src_wire": "CLBLM_L_C2", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A5" + }, + "CLBLM_L.CLBLM_L_B->CLBLM_LOGIC_OUTS9": { + "src_wire": "CLBLM_L_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS9" + }, + "CLBLM_L.CLBLM_BYP5->CLBLM_L_BX": { + "src_wire": "CLBLM_BYP5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_BX" + }, + "CLBLM_L.CLBLM_FAN3->CLBLM_M_DI": { + "src_wire": "CLBLM_FAN3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_DI" + }, + "CLBLM_L.CLBLM_M_A5->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_L.CLBLM_L_D2->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_L.CLBLM_L_AMUX->CLBLM_LOGIC_OUTS16": { + "src_wire": "CLBLM_L_AMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS16" + }, + "CLBLM_L.CLBLM_FAN0->CLBLM_M_AI": { + "src_wire": "CLBLM_FAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_AI" + }, + "CLBLM_L.CLBLM_L_A1->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_L.CLBLM_IMUX7->CLBLM_M_A1": { + "src_wire": "CLBLM_IMUX7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A1" + }, + "CLBLM_L.CLBLM_M_B->CLBLM_LOGIC_OUTS13": { + "src_wire": "CLBLM_M_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS13" + }, + "CLBLM_L.CLBLM_IMUX0->CLBLM_L_A3": { + "src_wire": "CLBLM_IMUX0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A3" + }, + "CLBLM_L.CLBLM_L_D4->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_L.CLBLM_M_A4->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_L.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { + "src_wire": "CLBLM_M_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS15" + }, + "CLBLM_L.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { + "src_wire": "CLBLM_L_BMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS17" + }, + "CLBLM_L.CLBLM_L_DMUX->CLBLM_LOGIC_OUTS19": { + "src_wire": "CLBLM_L_DMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS19" + }, + "CLBLM_L.CLBLM_CTRL0->CLBLM_L_SR": { + "src_wire": "CLBLM_CTRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_SR" + }, + "CLBLM_L.CLBLM_M_C->CLBLM_LOGIC_OUTS14": { + "src_wire": "CLBLM_M_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS14" }, "CLBLM_L.CLBLM_IMUX41->CLBLM_L_D1": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D1", - "is_directional": "1", "src_wire": "CLBLM_IMUX41", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D1" + }, + "CLBLM_L.CLBLM_L_D6->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_L.CLBLM_M_C6->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_L.CLBLM_IMUX5->CLBLM_L_A6": { + "src_wire": "CLBLM_IMUX5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A6" + }, + "CLBLM_L.CLBLM_L_C6->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_L.CLBLM_IMUX14->CLBLM_L_B1": { + "src_wire": "CLBLM_IMUX14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B1" + }, + "CLBLM_L.CLBLM_M_B2->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_L.CLBLM_L_B4->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_L.CLBLM_M_C2->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_L.CLBLM_M_AQ->CLBLM_LOGIC_OUTS4": { + "src_wire": "CLBLM_M_AQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS4" + }, + "CLBLM_L.CLBLM_IMUX11->CLBLM_M_A4": { + "src_wire": "CLBLM_IMUX11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A4" + }, + "CLBLM_L.CLBLM_BYP1->CLBLM_M_AX": { + "src_wire": "CLBLM_BYP1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_AX" + }, + "CLBLM_L.CLBLM_M_C5->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_L.CLBLM_IMUX27->CLBLM_M_B4": { + "src_wire": "CLBLM_IMUX27", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B4" + }, + "CLBLM_L.CLBLM_IMUX13->CLBLM_L_B6": { + "src_wire": "CLBLM_IMUX13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B6" + }, + "CLBLM_L.CLBLM_M_COUT->>CLBLM_M_DMUX": { + "src_wire": "CLBLM_M_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_DMUX" + }, + "CLBLM_L.CLBLM_IMUX25->CLBLM_L_B5": { + "src_wire": "CLBLM_IMUX25", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B5" + }, + "CLBLM_L.CLBLM_IMUX15->CLBLM_M_B1": { + "src_wire": "CLBLM_IMUX15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B1" + }, + "CLBLM_L.CLBLM_L_B2->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_L.CLBLM_CTRL1->CLBLM_M_SR": { + "src_wire": "CLBLM_CTRL1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_SR" + }, + "CLBLM_L.CLBLM_IMUX30->CLBLM_L_C5": { + "src_wire": "CLBLM_IMUX30", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C5" + }, + "CLBLM_L.CLBLM_L_A2->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_L.CLBLM_M_A1->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_L.CLBLM_L_A6->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_L.CLBLM_IMUX24->CLBLM_M_B5": { + "src_wire": "CLBLM_IMUX24", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B5" + }, + "CLBLM_L.CLBLM_BYP7->CLBLM_L_DX": { + "src_wire": "CLBLM_BYP7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_DX" + }, + "CLBLM_L.CLBLM_IMUX40->CLBLM_M_D1": { + "src_wire": "CLBLM_IMUX40", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D1" + }, + "CLBLM_L.CLBLM_L_B3->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_L.CLBLM_IMUX16->CLBLM_L_B3": { + "src_wire": "CLBLM_IMUX16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B3" + }, + "CLBLM_L.CLBLM_IMUX47->CLBLM_M_D5": { + "src_wire": "CLBLM_IMUX47", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D5" + }, + "CLBLM_L.CLBLM_IMUX22->CLBLM_M_C3": { + "src_wire": "CLBLM_IMUX22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C3" + }, + "CLBLM_L.CLBLM_M_A6->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_L.CLBLM_L_D1->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_L.CLBLM_IMUX34->CLBLM_L_C6": { + "src_wire": "CLBLM_IMUX34", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C6" + }, + "CLBLM_L.CLBLM_IMUX8->CLBLM_M_A5": { + "src_wire": "CLBLM_IMUX8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A5" + }, + "CLBLM_L.CLBLM_L_B5->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_L.CLBLM_IMUX33->CLBLM_L_C1": { + "src_wire": "CLBLM_IMUX33", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C1" + }, + "CLBLM_L.CLBLM_IMUX35->CLBLM_M_C6": { + "src_wire": "CLBLM_IMUX35", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C6" + }, + "CLBLM_L.CLBLM_M_A3->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_L.CLBLM_M_D6->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_L.CLBLM_IMUX4->CLBLM_M_A6": { + "src_wire": "CLBLM_IMUX4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A6" + }, + "CLBLM_L.CLBLM_IMUX23->CLBLM_L_C3": { + "src_wire": "CLBLM_IMUX23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C3" + }, + "CLBLM_L.CLBLM_CLK0->CLBLM_L_CLK": { + "src_wire": "CLBLM_CLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CLK" + }, + "CLBLM_L.CLBLM_IMUX1->CLBLM_M_A3": { + "src_wire": "CLBLM_IMUX1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A3" + }, + "CLBLM_L.CLBLM_M_A->>CLBLM_M_AMUX": { + "src_wire": "CLBLM_M_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_AMUX" + }, + "CLBLM_L.CLBLM_M_B->>CLBLM_M_BMUX": { + "src_wire": "CLBLM_M_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_BMUX" + }, + "CLBLM_L.CLBLM_BYP0->CLBLM_L_AX": { + "src_wire": "CLBLM_BYP0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_AX" + }, + "CLBLM_L.CLBLM_L_C->CLBLM_LOGIC_OUTS10": { + "src_wire": "CLBLM_L_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS10" + }, + "CLBLM_L.CLBLM_L_A3->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_L.CLBLM_M_D3->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_L.CLBLM_M_CMUX->CLBLM_LOGIC_OUTS22": { + "src_wire": "CLBLM_M_CMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS22" + }, + "CLBLM_L.CLBLM_L_D5->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_L.CLBLM_IMUX36->CLBLM_L_D2": { + "src_wire": "CLBLM_IMUX36", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D2" + }, + "CLBLM_L.CLBLM_L_D->>CLBLM_L_DMUX": { + "src_wire": "CLBLM_L_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_DMUX" + }, + "CLBLM_L.CLBLM_M_D4->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_L.CLBLM_IMUX42->CLBLM_L_D6": { + "src_wire": "CLBLM_IMUX42", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D6" + }, + "CLBLM_L.CLBLM_L_CQ->CLBLM_LOGIC_OUTS2": { + "src_wire": "CLBLM_L_CQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS2" + }, + "CLBLM_L.CLBLM_IMUX26->CLBLM_L_B4": { + "src_wire": "CLBLM_IMUX26", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B4" + }, + "CLBLM_L.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { + "src_wire": "CLBLM_M_DQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS7" + }, + "CLBLM_L.CLBLM_IMUX29->CLBLM_M_C2": { + "src_wire": "CLBLM_IMUX29", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C2" + }, + "CLBLM_L.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { + "src_wire": "CLBLM_M_CQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS6" + }, + "CLBLM_L.CLBLM_M_D->>CLBLM_M_DMUX": { + "src_wire": "CLBLM_M_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_DMUX" + }, + "CLBLM_L.CLBLM_FAN4->CLBLM_M_WE": { + "src_wire": "CLBLM_FAN4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_WE" + }, + "CLBLM_L.CLBLM_FAN5->CLBLM_M_CI": { + "src_wire": "CLBLM_FAN5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CI" + }, + "CLBLM_L.CLBLM_IMUX28->CLBLM_M_C4": { + "src_wire": "CLBLM_IMUX28", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C4" + }, + "CLBLM_L.CLBLM_IMUX39->CLBLM_L_D3": { + "src_wire": "CLBLM_IMUX39", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D3" + }, + "CLBLM_L.CLBLM_M_B6->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_L.CLBLM_L_C1->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_L.CLBLM_M_C1->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_L.CLBLM_L_C3->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_L.CLBLM_M_B4->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_L.CLBLM_L_B->>CLBLM_L_BMUX": { + "src_wire": "CLBLM_L_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_BMUX" + }, + "CLBLM_L.CLBLM_M_AMUX->CLBLM_LOGIC_OUTS20": { + "src_wire": "CLBLM_M_AMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS20" + }, + "CLBLM_L.CLBLM_M_C3->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_L.CLBLM_M_C4->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_L.CLBLM_FAN7->CLBLM_M_CE": { + "src_wire": "CLBLM_FAN7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CE" + }, + "CLBLM_L.CLBLM_IMUX46->CLBLM_L_D5": { + "src_wire": "CLBLM_IMUX46", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D5" + }, + "CLBLM_L.CLBLM_IMUX31->CLBLM_M_C5": { + "src_wire": "CLBLM_IMUX31", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C5" + }, + "CLBLM_L.CLBLM_IMUX3->CLBLM_L_A2": { + "src_wire": "CLBLM_IMUX3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A2" + }, + "CLBLM_L.CLBLM_L_D3->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_L.CLBLM_IMUX21->CLBLM_L_C4": { + "src_wire": "CLBLM_IMUX21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C4" + }, + "CLBLM_L.CLBLM_M_BQ->CLBLM_LOGIC_OUTS5": { + "src_wire": "CLBLM_M_BQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS5" + }, + "CLBLM_L.CLBLM_IMUX32->CLBLM_M_C1": { + "src_wire": "CLBLM_IMUX32", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C1" + }, + "CLBLM_L.CLBLM_L_C4->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_L.CLBLM_FAN2->CLBLM_M_BI": { + "src_wire": "CLBLM_FAN2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_BI" + }, + "CLBLM_L.CLBLM_L_A5->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_L.CLBLM_IMUX18->CLBLM_M_B2": { + "src_wire": "CLBLM_IMUX18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B2" + }, + "CLBLM_L.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { + "src_wire": "CLBLM_L_BQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS1" + }, + "CLBLM_L.CLBLM_IMUX19->CLBLM_L_B2": { + "src_wire": "CLBLM_IMUX19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B2" + }, + "CLBLM_L.CLBLM_IMUX12->CLBLM_M_B6": { + "src_wire": "CLBLM_IMUX12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B6" + }, + "CLBLM_L.CLBLM_M_B5->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_L.CLBLM_L_DQ->CLBLM_LOGIC_OUTS3": { + "src_wire": "CLBLM_L_DQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS3" + }, + "CLBLM_L.CLBLM_BYP4->CLBLM_M_BX": { + "src_wire": "CLBLM_BYP4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_BX" + }, + "CLBLM_L.CLBLM_M_A2->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_L.CLBLM_L_C2->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_L.CLBLM_IMUX10->CLBLM_L_A4": { + "src_wire": "CLBLM_IMUX10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A4" + }, + "CLBLM_L.CLBLM_L_A4->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_L.CLBLM_IMUX20->CLBLM_L_C2": { + "src_wire": "CLBLM_IMUX20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C2" + }, + "CLBLM_L.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { + "src_wire": "CLBLM_M_DMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS23" + }, + "CLBLM_L.CLBLM_M_COUT->CLBLM_M_COUT_N": { + "src_wire": "CLBLM_M_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_COUT_N" + }, + "CLBLM_L.CLBLM_L_COUT->>CLBLM_L_DMUX": { + "src_wire": "CLBLM_L_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_DMUX" + }, + "CLBLM_L.CLBLM_L_B6->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_L.CLBLM_M_C->>CLBLM_M_CMUX": { + "src_wire": "CLBLM_M_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_CMUX" + }, + "CLBLM_L.CLBLM_M_D1->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_L.CLBLM_IMUX45->CLBLM_M_D2": { + "src_wire": "CLBLM_IMUX45", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D2" + }, + "CLBLM_L.CLBLM_L_C5->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_L.CLBLM_M_BMUX->CLBLM_LOGIC_OUTS21": { + "src_wire": "CLBLM_M_BMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS21" } }, - "tile_type": "CLBLM_L" + "wires": [ + "CLBLM_EE4A1", + "CLBLM_M_BMUX", + "CLBLM_LOGIC_OUTS18", + "CLBLM_SW2A0", + "CLBLM_EE4C1", + "CLBLM_M_AI", + "CLBLM_L_A", + "CLBLM_EE2BEG2", + "CLBLM_WW2END3", + "CLBLM_LOGIC_OUTS14", + "CLBLM_SW4A1", + "CLBLM_L_A4", + "CLBLM_CLK0", + "CLBLM_EE2A2", + "CLBLM_LH11", + "CLBLM_M_CX", + "CLBLM_LH2", + "CLBLM_ER1BEG2", + "CLBLM_IMUX29", + "CLBLM_IMUX41", + "CLBLM_SE2A1", + "CLBLM_EE4C2", + "CLBLM_CTRL0", + "CLBLM_L_C4", + "CLBLM_IMUX4", + "CLBLM_M_B3", + "CLBLM_LOGIC_OUTS8", + "CLBLM_L_B1", + "CLBLM_LH10", + "CLBLM_WL1END1", + "CLBLM_WR1END2", + "CLBLM_L_D5", + "CLBLM_M_B5", + "CLBLM_LOGIC_OUTS17", + "CLBLM_M_AMUX", + "CLBLM_WR1END3", + "CLBLM_WW4C0", + "CLBLM_L_DMUX", + "CLBLM_WW4C3", + "CLBLM_SE2A2", + "CLBLM_NE4C3", + "CLBLM_FAN2", + "CLBLM_IMUX37", + "CLBLM_WR1END1", + "CLBLM_LH1", + "CLBLM_M_SR", + "CLBLM_M_A1", + "CLBLM_FAN7", + "CLBLM_LOGIC_OUTS4", + "CLBLM_IMUX21", + "CLBLM_M_D5", + "CLBLM_SE2A0", + "CLBLM_M_DI", + "CLBLM_SW2A2", + "CLBLM_L_D", + "CLBLM_EE4A0", + "CLBLM_M_C1", + "CLBLM_L_C5", + "CLBLM_M_CLK", + "CLBLM_EE2BEG3", + "CLBLM_M_A", + "CLBLM_SW4END2", + "CLBLM_M_AX", + "CLBLM_IMUX30", + "CLBLM_IMUX5", + "CLBLM_NE4BEG2", + "CLBLM_NE2A0", + "CLBLM_NE4C0", + "CLBLM_IMUX31", + "CLBLM_IMUX27", + "CLBLM_NE4BEG0", + "CLBLM_IMUX7", + "CLBLM_M_A6", + "CLBLM_LH7", + "CLBLM_L_C", + "CLBLM_ER1BEG3", + "CLBLM_EL1BEG2", + "CLBLM_L_B6", + "CLBLM_L_A6", + "CLBLM_L_CE", + "CLBLM_M_CI", + "CLBLM_EE4BEG2", + "CLBLM_M_D2", + "CLBLM_LOGIC_OUTS0", + "CLBLM_WW4END2", + "CLBLM_SE4BEG1", + "CLBLM_LOGIC_OUTS15", + "CLBLM_LOGIC_OUTS3", + "CLBLM_LOGIC_OUTS2", + "CLBLM_WW4B0", + "CLBLM_M_B2", + "CLBLM_L_C3", + "CLBLM_IMUX22", + "CLBLM_SE4C3", + "CLBLM_WL1END0", + "CLBLM_M_D4", + "CLBLM_LOGIC_OUTS10", + "CLBLM_L_A2", + "CLBLM_WW2END1", + "CLBLM_WW4B2", + "CLBLM_EE2A1", + "CLBLM_WW4B3", + "CLBLM_L_B3", + "CLBLM_IMUX47", + "CLBLM_IMUX9", + "CLBLM_L_AQ", + "CLBLM_SW4A2", + "CLBLM_LH9", + "CLBLM_SE2A3", + "CLBLM_CTRL1", + "CLBLM_SW4END1", + "CLBLM_L_D3", + "CLBLM_EE4A2", + "CLBLM_NW4A0", + "CLBLM_NE2A2", + "CLBLM_FAN5", + "CLBLM_SW2A3", + "CLBLM_IMUX8", + "CLBLM_M_D", + "CLBLM_IMUX24", + "CLBLM_WW2END0", + "CLBLM_MONITOR_N", + "CLBLM_M_C6", + "CLBLM_SE4C0", + "CLBLM_EE4B1", + "CLBLM_LOGIC_OUTS6", + "CLBLM_IMUX26", + "CLBLM_WW4C1", + "CLBLM_WW2A2", + "CLBLM_M_DX", + "CLBLM_LOGIC_OUTS1", + "CLBLM_WL1END2", + "CLBLM_IMUX20", + "CLBLM_EE4BEG0", + "CLBLM_IMUX34", + "CLBLM_EE4B2", + "CLBLM_IMUX18", + "CLBLM_WW4END1", + "CLBLM_IMUX33", + "CLBLM_EE2A0", + "CLBLM_L_COUT", + "CLBLM_WW4A1", + "CLBLM_WW2A3", + "CLBLM_IMUX13", + "CLBLM_LH4", + "CLBLM_L_AX", + "CLBLM_M_A2", + "CLBLM_IMUX17", + "CLBLM_EE4A3", + "CLBLM_WW2END2", + "CLBLM_BYP2", + "CLBLM_SW4END3", + "CLBLM_L_A1", + "CLBLM_BYP0", + "CLBLM_NW4A3", + "CLBLM_NW4A1", + "CLBLM_SE4C1", + "CLBLM_L_DX", + "CLBLM_LOGIC_OUTS20", + "CLBLM_L_DQ", + "CLBLM_EE4B3", + "CLBLM_M_C5", + "CLBLM_EL1BEG0", + "CLBLM_IMUX23", + "CLBLM_L_D4", + "CLBLM_NW4END1", + "CLBLM_L_CLK", + "CLBLM_NW2A1", + "CLBLM_L_B2", + "CLBLM_IMUX36", + "CLBLM_WR1END0", + "CLBLM_IMUX0", + "CLBLM_IMUX2", + "CLBLM_M_CMUX", + "CLBLM_IMUX15", + "CLBLM_FAN1", + "CLBLM_IMUX43", + "CLBLM_SE4C2", + "CLBLM_EE4B0", + "CLBLM_LOGIC_OUTS12", + "CLBLM_SW4END0", + "CLBLM_IMUX10", + "CLBLM_IMUX42", + "CLBLM_M_BX", + "CLBLM_NE4C2", + "CLBLM_L_AMUX", + "CLBLM_NE2A1", + "CLBLM_LOGIC_OUTS22", + "CLBLM_IMUX6", + "CLBLM_M_COUT", + "CLBLM_WW4C2", + "CLBLM_BYP4", + "CLBLM_IMUX44", + "CLBLM_SE4BEG0", + "CLBLM_NE2A3", + "CLBLM_M_AQ", + "CLBLM_WW4END0", + "CLBLM_SE4BEG2", + "CLBLM_NW4END2", + "CLBLM_IMUX46", + "CLBLM_WW4A3", + "CLBLM_M_D1", + "CLBLM_NW4END0", + "CLBLM_LOGIC_OUTS23", + "CLBLM_FAN0", + "CLBLM_L_C6", + "CLBLM_IMUX40", + "CLBLM_M_BI", + "CLBLM_LOGIC_OUTS13", + "CLBLM_M_CIN", + "CLBLM_NW4A2", + "CLBLM_EE4BEG1", + "CLBLM_SW2A1", + "CLBLM_MONITOR_P", + "CLBLM_NW2A2", + "CLBLM_M_D6", + "CLBLM_L_A3", + "CLBLM_BYP5", + "CLBLM_IMUX39", + "CLBLM_BYP6", + "CLBLM_EE2BEG0", + "CLBLM_L_C1", + "CLBLM_IMUX11", + "CLBLM_M_B", + "CLBLM_LH5", + "CLBLM_LH8", + "CLBLM_IMUX16", + "CLBLM_M_DMUX", + "CLBLM_EE4C0", + "CLBLM_IMUX1", + "CLBLM_WL1END3", + "CLBLM_L_B5", + "CLBLM_IMUX38", + "CLBLM_EE4C3", + "CLBLM_LH12", + "CLBLM_FAN3", + "CLBLM_L_BMUX", + "CLBLM_M_C", + "CLBLM_ER1BEG1", + "CLBLM_SW4A0", + "CLBLM_M_COUT_N", + "CLBLM_L_CIN", + "CLBLM_IMUX35", + "CLBLM_WW4A2", + "CLBLM_WW4B1", + "CLBLM_LOGIC_OUTS11", + "CLBLM_L_CMUX", + "CLBLM_L_BQ", + "CLBLM_M_WE", + "CLBLM_BYP7", + "CLBLM_M_A5", + "CLBLM_BYP3", + "CLBLM_EE2BEG1", + "CLBLM_EE2A3", + "CLBLM_M_D3", + "CLBLM_WW2A1", + "CLBLM_FAN6", + "CLBLM_NW2A3", + "CLBLM_LOGIC_OUTS5", + "CLBLM_SE4BEG3", + "CLBLM_L_D1", + "CLBLM_L_C2", + "CLBLM_IMUX3", + "CLBLM_L_B4", + "CLBLM_M_C2", + "CLBLM_LH6", + "CLBLM_NE4C1", + "CLBLM_M_C4", + "CLBLM_LOGIC_OUTS16", + "CLBLM_L_COUT_N", + "CLBLM_IMUX14", + "CLBLM_EE4BEG3", + "CLBLM_EL1BEG1", + "CLBLM_M_CQ", + "CLBLM_M_A4", + "CLBLM_LOGIC_OUTS21", + "CLBLM_L_D2", + "CLBLM_WW2A0", + "CLBLM_L_SR", + "CLBLM_IMUX12", + "CLBLM_ER1BEG0", + "CLBLM_NE4BEG3", + "CLBLM_LOGIC_OUTS7", + "CLBLM_L_B", + "CLBLM_M_A3", + "CLBLM_L_BX", + "CLBLM_CLK1", + "CLBLM_NW4END3", + "CLBLM_L_CX", + "CLBLM_L_A5", + "CLBLM_NE4BEG1", + "CLBLM_LOGIC_OUTS9", + "CLBLM_LH3", + "CLBLM_WW4A0", + "CLBLM_M_B4", + "CLBLM_L_D6", + "CLBLM_M_C3", + "CLBLM_NW2A0", + "CLBLM_M_CE", + "CLBLM_M_B1", + "CLBLM_M_B6", + "CLBLM_M_DQ", + "CLBLM_LOGIC_OUTS19", + "CLBLM_IMUX32", + "CLBLM_IMUX28", + "CLBLM_IMUX45", + "CLBLM_SW4A3", + "CLBLM_BYP1", + "CLBLM_FAN4", + "CLBLM_IMUX25", + "CLBLM_IMUX19", + "CLBLM_WW4END3", + "CLBLM_M_BQ", + "CLBLM_L_CQ", + "CLBLM_EL1BEG3" + ], + "tile_type": "CLBLM_L", + "sites": [ + { + "site_pins": { + "BQ": "CLBLM_L_BQ", + "CX": "CLBLM_L_CX", + "C1": "CLBLM_L_C1", + "B6": "CLBLM_L_B6", + "DMUX": "CLBLM_L_DMUX", + "SR": "CLBLM_L_SR", + "B": "CLBLM_L_B", + "D6": "CLBLM_L_D6", + "D5": "CLBLM_L_D5", + "A5": "CLBLM_L_A5", + "AMUX": "CLBLM_L_AMUX", + "C6": "CLBLM_L_C6", + "AQ": "CLBLM_L_AQ", + "B5": "CLBLM_L_B5", + "B3": "CLBLM_L_B3", + "DQ": "CLBLM_L_DQ", + "D3": "CLBLM_L_D3", + "C": "CLBLM_L_C", + "DX": "CLBLM_L_DX", + "C4": "CLBLM_L_C4", + "A4": "CLBLM_L_A4", + "A1": "CLBLM_L_A1", + "D1": "CLBLM_L_D1", + "BX": "CLBLM_L_BX", + "COUT": "CLBLM_L_COUT", + "CLK": "CLBLM_L_CLK", + "D": "CLBLM_L_D", + "A2": "CLBLM_L_A2", + "CQ": "CLBLM_L_CQ", + "D4": "CLBLM_L_D4", + "C5": "CLBLM_L_C5", + "CIN": "CLBLM_L_CIN", + "D2": "CLBLM_L_D2", + "B2": "CLBLM_L_B2", + "A6": "CLBLM_L_A6", + "CMUX": "CLBLM_L_CMUX", + "A3": "CLBLM_L_A3", + "C3": "CLBLM_L_C3", + "AX": "CLBLM_L_AX", + "B1": "CLBLM_L_B1", + "B4": "CLBLM_L_B4", + "A": "CLBLM_L_A", + "BMUX": "CLBLM_L_BMUX", + "CE": "CLBLM_L_CE", + "C2": "CLBLM_L_C2" + }, + "type": "SLICEL", + "prefix": "SLICE", + "name": "X1Y0", + "x_coord": 1, + "y_coord": 0 + }, + { + "site_pins": { + "BQ": "CLBLM_M_BQ", + "CX": "CLBLM_M_CX", + "C1": "CLBLM_M_C1", + "B6": "CLBLM_M_B6", + "DMUX": "CLBLM_M_DMUX", + "SR": "CLBLM_M_SR", + "B": "CLBLM_M_B", + "D6": "CLBLM_M_D6", + "D5": "CLBLM_M_D5", + "A5": "CLBLM_M_A5", + "AMUX": "CLBLM_M_AMUX", + "WE": "CLBLM_M_WE", + "C6": "CLBLM_M_C6", + "AQ": "CLBLM_M_AQ", + "B5": "CLBLM_M_B5", + "B3": "CLBLM_M_B3", + "DQ": "CLBLM_M_DQ", + "D3": "CLBLM_M_D3", + "C": "CLBLM_M_C", + "DX": "CLBLM_M_DX", + "C4": "CLBLM_M_C4", + "A4": "CLBLM_M_A4", + "DI": "CLBLM_M_DI", + "A1": "CLBLM_M_A1", + "D1": "CLBLM_M_D1", + "BX": "CLBLM_M_BX", + "COUT": "CLBLM_M_COUT", + "CLK": "CLBLM_M_CLK", + "D": "CLBLM_M_D", + "A2": "CLBLM_M_A2", + "AI": "CLBLM_M_AI", + "CQ": "CLBLM_M_CQ", + "D4": "CLBLM_M_D4", + "C5": "CLBLM_M_C5", + "CIN": "CLBLM_M_CIN", + "D2": "CLBLM_M_D2", + "B2": "CLBLM_M_B2", + "BI": "CLBLM_M_BI", + "A6": "CLBLM_M_A6", + "CMUX": "CLBLM_M_CMUX", + "A3": "CLBLM_M_A3", + "C3": "CLBLM_M_C3", + "AX": "CLBLM_M_AX", + "B1": "CLBLM_M_B1", + "CI": "CLBLM_M_CI", + "B4": "CLBLM_M_B4", + "A": "CLBLM_M_A", + "BMUX": "CLBLM_M_BMUX", + "CE": "CLBLM_M_CE", + "C2": "CLBLM_M_C2" + }, + "type": "SLICEM", + "prefix": "SLICE", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLBLM_R.json b/artix7/tile_type_CLBLM_R.json index 42be48a..6cf35c4 100644 --- a/artix7/tile_type_CLBLM_R.json +++ b/artix7/tile_type_CLBLM_R.json @@ -1,1494 +1,1494 @@ { - "wires": [ - "CLBLM_NE2A0", - "CLBLM_NW4END1", - "CLBLM_ER1BEG1", - "CLBLM_L_A3", - "CLBLM_M_BQ", - "CLBLM_WW4B2", - "CLBLM_WR1END3", - "CLBLM_NW4A1", - "CLBLM_IMUX7", - "CLBLM_L_D4", - "CLBLM_LOGIC_OUTS17", - "CLBLM_FAN3", - "CLBLM_L_A1", - "CLBLM_M_D2", - "CLBLM_L_C6", - "CLBLM_SW2A2", - "CLBLM_EE4B0", - "CLBLM_LOGIC_OUTS14", - "CLBLM_L_AQ", - "CLBLM_M_B1", - "CLBLM_SE2A3", - "CLBLM_L_A4", - "CLBLM_M_D6", - "CLBLM_IMUX39", - "CLBLM_NW4A0", - "CLBLM_M_B5", - "CLBLM_SW4END1", - "CLBLM_NW2A3", - "CLBLM_NE4C3", - "CLBLM_LH11", - "CLBLM_WW4END1", - "CLBLM_M_A2", - "CLBLM_SE4BEG2", - "CLBLM_EE2BEG1", - "CLBLM_L_A", - "CLBLM_M_BX", - "CLBLM_IMUX16", - "CLBLM_IMUX9", - "CLBLM_M_AI", - "CLBLM_M_C6", - "CLBLM_IMUX32", - "CLBLM_L_B", - "CLBLM_IMUX17", - "CLBLM_BYP7", - "CLBLM_NW4END2", - "CLBLM_IMUX26", - "CLBLM_L_B5", - "CLBLM_IMUX22", - "CLBLM_M_BMUX", - "CLBLM_L_D5", - "CLBLM_LH6", - "CLBLM_SW4A2", - "CLBLM_WR1END2", - "CLBLM_L_DQ", - "CLBLM_WW4A1", - "CLBLM_IMUX28", - "CLBLM_LOGIC_OUTS23", - "CLBLM_WW4A0", - "CLBLM_L_BQ", - "CLBLM_L_SR", - "CLBLM_LOGIC_OUTS11", - "CLBLM_EE4C2", - "CLBLM_L_B2", - "CLBLM_L_A5", - "CLBLM_NE4BEG0", - "CLBLM_M_CQ", - "CLBLM_MONITOR_P", - "CLBLM_M_B2", - "CLBLM_IMUX19", - "CLBLM_L_D", - "CLBLM_WW2END1", - "CLBLM_LOGIC_OUTS10", - "CLBLM_BYP3", - "CLBLM_FAN4", - "CLBLM_IMUX1", - "CLBLM_LOGIC_OUTS8", - "CLBLM_L_BMUX", - "CLBLM_NE2A1", - "CLBLM_EE4B1", - "CLBLM_IMUX13", - "CLBLM_L_CX", - "CLBLM_EE4C0", - "CLBLM_LOGIC_OUTS22", - "CLBLM_M_A4", - "CLBLM_IMUX23", - "CLBLM_WW2A3", - "CLBLM_EE4A0", - "CLBLM_M_CX", - "CLBLM_IMUX29", - "CLBLM_EE4A2", - "CLBLM_ER1BEG3", - "CLBLM_LH7", - "CLBLM_L_C1", - "CLBLM_EL1BEG1", - "CLBLM_LH12", - "CLBLM_SE4C0", - "CLBLM_NE4C1", - "CLBLM_CTRL0", - "CLBLM_M_C", - "CLBLM_IMUX36", - "CLBLM_EE2BEG2", - "CLBLM_IMUX44", - "CLBLM_WW4A3", - "CLBLM_L_CIN", - "CLBLM_M_CLK", - "CLBLM_IMUX27", - "CLBLM_EL1BEG3", - "CLBLM_SW2A3", - "CLBLM_SE2A2", - "CLBLM_LOGIC_OUTS3", - "CLBLM_LH9", - "CLBLM_SW4A0", - "CLBLM_M_C3", - "CLBLM_NE4BEG2", - "CLBLM_EE2A1", - "CLBLM_CLK1", - "CLBLM_NE4C0", - "CLBLM_L_C4", - "CLBLM_EE2A0", - "CLBLM_M_BI", - "CLBLM_LOGIC_OUTS20", - "CLBLM_EE2A3", - "CLBLM_LOGIC_OUTS21", - "CLBLM_BYP4", - "CLBLM_IMUX20", - "CLBLM_L_C5", - "CLBLM_M_C2", - "CLBLM_WW4B1", - "CLBLM_IMUX11", - "CLBLM_L_C2", - "CLBLM_BYP2", - "CLBLM_IMUX25", - "CLBLM_M_COUT", - "CLBLM_L_B3", - "CLBLM_M_DQ", - "CLBLM_IMUX40", - "CLBLM_WW4B0", - "CLBLM_EE4B2", - "CLBLM_L_BX", - "CLBLM_SW2A1", - "CLBLM_LOGIC_OUTS0", - "CLBLM_WW4END3", - "CLBLM_LH8", - "CLBLM_SW4END3", - "CLBLM_LH2", - "CLBLM_M_D1", - "CLBLM_M_A3", - "CLBLM_LOGIC_OUTS19", - "CLBLM_L_CQ", - "CLBLM_M_C1", - "CLBLM_WW2END3", - "CLBLM_WR1END0", - "CLBLM_WL1END0", - "CLBLM_M_B", - "CLBLM_L_B4", - "CLBLM_ER1BEG0", - "CLBLM_WW4END2", - "CLBLM_M_AQ", - "CLBLM_M_CIN", - "CLBLM_FAN0", - "CLBLM_L_AX", - "CLBLM_EE4A3", - "CLBLM_SW4END0", - "CLBLM_WL1END3", - "CLBLM_IMUX3", - "CLBLM_LOGIC_OUTS15", - "CLBLM_LOGIC_OUTS5", - "CLBLM_M_D3", - "CLBLM_FAN5", - "CLBLM_WW4A2", - "CLBLM_EE2A2", - "CLBLM_SW4A1", - "CLBLM_WL1END1", - "CLBLM_NW4A2", - "CLBLM_NE2A3", - "CLBLM_WL1END2", - "CLBLM_LH5", - "CLBLM_M_CE", - "CLBLM_IMUX5", - "CLBLM_LOGIC_OUTS9", - "CLBLM_M_D", - "CLBLM_BYP1", - "CLBLM_SE4BEG1", - "CLBLM_CTRL1", - "CLBLM_ER1BEG2", - "CLBLM_M_A5", - "CLBLM_IMUX12", - "CLBLM_SE2A1", - "CLBLM_L_DMUX", - "CLBLM_IMUX14", - "CLBLM_M_A6", - "CLBLM_L_D1", - "CLBLM_M_B4", - "CLBLM_L_AMUX", - "CLBLM_NW4A3", - "CLBLM_L_COUT", - "CLBLM_WW4C2", - "CLBLM_MONITOR_N", - "CLBLM_SE4BEG3", - "CLBLM_WW4B3", - "CLBLM_M_D4", - "CLBLM_M_DX", - "CLBLM_IMUX30", - "CLBLM_SW2A0", - "CLBLM_NW2A0", - "CLBLM_IMUX31", - "CLBLM_SE4BEG0", - "CLBLM_IMUX37", - "CLBLM_NW2A1", - "CLBLM_M_C4", - "CLBLM_M_A", - "CLBLM_EE4BEG3", - "CLBLM_BYP0", - "CLBLM_FAN1", - "CLBLM_IMUX46", - "CLBLM_FAN2", - "CLBLM_LOGIC_OUTS12", - "CLBLM_L_CE", - "CLBLM_WW2A1", - "CLBLM_FAN7", - "CLBLM_LH3", - "CLBLM_LOGIC_OUTS7", - "CLBLM_M_B3", - "CLBLM_NW4END0", - "CLBLM_IMUX47", - "CLBLM_NE4BEG1", - "CLBLM_EE4BEG1", - "CLBLM_IMUX8", - "CLBLM_LOGIC_OUTS18", - "CLBLM_IMUX2", - "CLBLM_IMUX21", - "CLBLM_IMUX41", - "CLBLM_IMUX42", - "CLBLM_IMUX35", - "CLBLM_IMUX4", - "CLBLM_L_A6", - "CLBLM_M_B6", - "CLBLM_IMUX43", - "CLBLM_SE4C3", - "CLBLM_WW2END0", - "CLBLM_FAN6", - "CLBLM_L_A2", - "CLBLM_WW4C3", - "CLBLM_IMUX6", - "CLBLM_L_D2", - "CLBLM_EL1BEG0", - "CLBLM_M_AMUX", - "CLBLM_SE2A0", - "CLBLM_LH4", - "CLBLM_IMUX38", - "CLBLM_LH10", - "CLBLM_EE4BEG0", - "CLBLM_NW2A2", - "CLBLM_EE2BEG3", - "CLBLM_NE4C2", - "CLBLM_L_COUT_N", - "CLBLM_WR1END1", - "CLBLM_LOGIC_OUTS6", - "CLBLM_L_C", - "CLBLM_IMUX0", - "CLBLM_M_CMUX", - "CLBLM_WW4END0", - "CLBLM_SE4C1", - "CLBLM_M_COUT_N", - "CLBLM_M_C5", - "CLBLM_IMUX34", - "CLBLM_EE4B3", - "CLBLM_LH1", - "CLBLM_LOGIC_OUTS13", - "CLBLM_M_A1", - "CLBLM_IMUX33", - "CLBLM_NE2A2", - "CLBLM_EE4C3", - "CLBLM_IMUX24", - "CLBLM_LOGIC_OUTS4", - "CLBLM_WW2END2", - "CLBLM_EL1BEG2", - "CLBLM_M_DMUX", - "CLBLM_IMUX18", - "CLBLM_EE4BEG2", - "CLBLM_BYP6", - "CLBLM_L_D3", - "CLBLM_WW2A0", - "CLBLM_L_B1", - "CLBLM_LOGIC_OUTS16", - "CLBLM_IMUX15", - "CLBLM_L_CMUX", - "CLBLM_WW2A2", - "CLBLM_L_C3", - "CLBLM_LOGIC_OUTS1", - "CLBLM_SE4C2", - "CLBLM_IMUX10", - "CLBLM_NW4END3", - "CLBLM_SW4A3", - "CLBLM_WW4C1", - "CLBLM_EE2BEG0", - "CLBLM_M_WE", - "CLBLM_L_CLK", - "CLBLM_EE4C1", - "CLBLM_BYP5", - "CLBLM_EE4A1", - "CLBLM_L_DX", - "CLBLM_IMUX45", - "CLBLM_L_D6", - "CLBLM_M_AX", - "CLBLM_M_CI", - "CLBLM_LOGIC_OUTS2", - "CLBLM_L_B6", - "CLBLM_WW4C0", - "CLBLM_M_D5", - "CLBLM_NE4BEG3", - "CLBLM_M_DI", - "CLBLM_M_SR", - "CLBLM_SW4END2", - "CLBLM_CLK0" - ], - "sites": [ - { - "prefix": "SLICE", - "y_coord": 0, - "type": "SLICEM", - "site_pins": { - "CX": "CLBLM_M_CX", - "CMUX": "CLBLM_M_CMUX", - "D1": "CLBLM_M_D1", - "CE": "CLBLM_M_CE", - "C5": "CLBLM_M_C5", - "D": "CLBLM_M_D", - "B1": "CLBLM_M_B1", - "C2": "CLBLM_M_C2", - "A2": "CLBLM_M_A2", - "CQ": "CLBLM_M_CQ", - "CI": "CLBLM_M_CI", - "DI": "CLBLM_M_DI", - "AMUX": "CLBLM_M_AMUX", - "BQ": "CLBLM_M_BQ", - "D3": "CLBLM_M_D3", - "B6": "CLBLM_M_B6", - "CLK": "CLBLM_M_CLK", - "SR": "CLBLM_M_SR", - "C6": "CLBLM_M_C6", - "BI": "CLBLM_M_BI", - "AQ": "CLBLM_M_AQ", - "A": "CLBLM_M_A", - "B5": "CLBLM_M_B5", - "WE": "CLBLM_M_WE", - "C1": "CLBLM_M_C1", - "D5": "CLBLM_M_D5", - "DMUX": "CLBLM_M_DMUX", - "DQ": "CLBLM_M_DQ", - "A6": "CLBLM_M_A6", - "D4": "CLBLM_M_D4", - "D6": "CLBLM_M_D6", - "C3": "CLBLM_M_C3", - "D2": "CLBLM_M_D2", - "B2": "CLBLM_M_B2", - "BX": "CLBLM_M_BX", - "BMUX": "CLBLM_M_BMUX", - "AX": "CLBLM_M_AX", - "C4": "CLBLM_M_C4", - "B": "CLBLM_M_B", - "A3": "CLBLM_M_A3", - "C": "CLBLM_M_C", - "COUT": "CLBLM_M_COUT", - "B4": "CLBLM_M_B4", - "A5": "CLBLM_M_A5", - "CIN": "CLBLM_M_CIN", - "AI": "CLBLM_M_AI", - "DX": "CLBLM_M_DX", - "A4": "CLBLM_M_A4", - "A1": "CLBLM_M_A1", - "B3": "CLBLM_M_B3" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "SLICE", - "y_coord": 0, - "type": "SLICEL", - "site_pins": { - "CX": "CLBLM_L_CX", - "CMUX": "CLBLM_L_CMUX", - "D1": "CLBLM_L_D1", - "CE": "CLBLM_L_CE", - "C5": "CLBLM_L_C5", - "D": "CLBLM_L_D", - "B1": "CLBLM_L_B1", - "C2": "CLBLM_L_C2", - "A2": "CLBLM_L_A2", - "CQ": "CLBLM_L_CQ", - "AMUX": "CLBLM_L_AMUX", - "BQ": "CLBLM_L_BQ", - "D3": "CLBLM_L_D3", - "B6": "CLBLM_L_B6", - "CLK": "CLBLM_L_CLK", - "SR": "CLBLM_L_SR", - "C6": "CLBLM_L_C6", - "AQ": "CLBLM_L_AQ", - "A": "CLBLM_L_A", - "B5": "CLBLM_L_B5", - "C1": "CLBLM_L_C1", - "D5": "CLBLM_L_D5", - "DMUX": "CLBLM_L_DMUX", - "DQ": "CLBLM_L_DQ", - "A6": "CLBLM_L_A6", - "D4": "CLBLM_L_D4", - "D6": "CLBLM_L_D6", - "C3": "CLBLM_L_C3", - "D2": "CLBLM_L_D2", - "B2": "CLBLM_L_B2", - "BX": "CLBLM_L_BX", - "BMUX": "CLBLM_L_BMUX", - "AX": "CLBLM_L_AX", - "C4": "CLBLM_L_C4", - "B": "CLBLM_L_B", - "A3": "CLBLM_L_A3", - "C": "CLBLM_L_C", - "COUT": "CLBLM_L_COUT", - "B4": "CLBLM_L_B4", - "A5": "CLBLM_L_A5", - "CIN": "CLBLM_L_CIN", - "DX": "CLBLM_L_DX", - "A4": "CLBLM_L_A4", - "A1": "CLBLM_L_A1", - "B3": "CLBLM_L_B3" - }, - "x_coord": 1, - "name": "X1Y0" - } - ], "pips": { - "CLBLM_R.CLBLM_IMUX22->CLBLM_M_C3": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX22", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_B4->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B4", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX35->CLBLM_M_C6": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX35", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX43->CLBLM_M_D6": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX43", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX11->CLBLM_M_A4": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX11", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_C->>CLBLM_L_CMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_CMUX", - "is_directional": "1", - "src_wire": "CLBLM_L_C", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX24->CLBLM_M_B5": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX24", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_D->>CLBLM_M_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_DMUX", - "is_directional": "1", - "src_wire": "CLBLM_M_D", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_C->CLBLM_LOGIC_OUTS14": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS14", - "is_directional": "1", - "src_wire": "CLBLM_M_C", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_A4->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A4", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX16->CLBLM_L_B3": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX16", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_BYP7->CLBLM_L_DX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_DX", - "is_directional": "1", - "src_wire": "CLBLM_BYP7", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS6", - "is_directional": "1", - "src_wire": "CLBLM_M_CQ", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX6->CLBLM_L_A1": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX6", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS15", - "is_directional": "1", - "src_wire": "CLBLM_M_D", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_D2->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D2", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_AMUX->CLBLM_LOGIC_OUTS16": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS16", - "is_directional": "1", - "src_wire": "CLBLM_L_AMUX", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX10->CLBLM_L_A4": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX10", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX42->CLBLM_L_D6": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX42", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX18->CLBLM_M_B2": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX18", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_FAN7->CLBLM_M_CE": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CE", - "is_directional": "1", - "src_wire": "CLBLM_FAN7", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX8->CLBLM_M_A5": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX8", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX15->CLBLM_M_B1": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX15", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_B4->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B4", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_AMUX->CLBLM_LOGIC_OUTS20": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS20", - "is_directional": "1", - "src_wire": "CLBLM_M_AMUX", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_BMUX->CLBLM_LOGIC_OUTS21": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS21", - "is_directional": "1", - "src_wire": "CLBLM_M_BMUX", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_BYP0->CLBLM_L_AX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_AX", - "is_directional": "1", - "src_wire": "CLBLM_BYP0", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_D6->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D6", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX27->CLBLM_M_B4": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX27", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_B->CLBLM_LOGIC_OUTS9": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS9", - "is_directional": "1", - "src_wire": "CLBLM_L_B", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX39->CLBLM_L_D3": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX39", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_C4->>CLBLM_L_C": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C", - "is_directional": "1", - "src_wire": "CLBLM_L_C4", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX32->CLBLM_M_C1": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX32", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_C2->>CLBLM_M_C": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C", - "is_directional": "1", - "src_wire": "CLBLM_M_C2", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_CMUX->CLBLM_LOGIC_OUTS18": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS18", - "is_directional": "1", - "src_wire": "CLBLM_L_CMUX", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX12->CLBLM_M_B6": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX12", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_CTRL0->CLBLM_L_SR": { - "can_invert": "0", - "dst_wire": "CLBLM_L_SR", - "is_directional": "1", - "src_wire": "CLBLM_CTRL0", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX0->CLBLM_L_A3": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX0", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_A->>CLBLM_L_AMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_AMUX", - "is_directional": "1", - "src_wire": "CLBLM_L_A", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_C->>CLBLM_M_CMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CMUX", - "is_directional": "1", - "src_wire": "CLBLM_M_C", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX34->CLBLM_L_C6": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX34", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_BYP6->CLBLM_M_DX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_DX", - "is_directional": "1", - "src_wire": "CLBLM_BYP6", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX2->CLBLM_M_A2": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX2", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_B->CLBLM_LOGIC_OUTS13": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS13", - "is_directional": "1", - "src_wire": "CLBLM_M_B", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_B3->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B3", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_B1->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B1", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS23", - "is_directional": "1", - "src_wire": "CLBLM_M_DMUX", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_CLK0->CLBLM_L_CLK": { - "can_invert": "0", - "dst_wire": "CLBLM_L_CLK", - "is_directional": "1", - "src_wire": "CLBLM_CLK0", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_COUT->CLBLM_M_COUT_N": { - "can_invert": "0", - "dst_wire": "CLBLM_M_COUT_N", - "is_directional": "1", - "src_wire": "CLBLM_M_COUT", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_C1->>CLBLM_L_C": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C", - "is_directional": "1", - "src_wire": "CLBLM_L_C1", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_A6->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A6", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_A5->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A5", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX30->CLBLM_L_C5": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX30", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_A4->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A4", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX5->CLBLM_L_A6": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX5", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_D6->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D6", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_A3->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A3", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS1", - "is_directional": "1", - "src_wire": "CLBLM_L_BQ", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX47->CLBLM_M_D5": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX47", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX29->CLBLM_M_C2": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX29", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_CQ->CLBLM_LOGIC_OUTS2": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS2", - "is_directional": "1", - "src_wire": "CLBLM_L_CQ", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_A->CLBLM_LOGIC_OUTS8": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS8", - "is_directional": "1", - "src_wire": "CLBLM_L_A", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX20->CLBLM_L_C2": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX20", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_AQ->CLBLM_LOGIC_OUTS4": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS4", - "is_directional": "1", - "src_wire": "CLBLM_M_AQ", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_B2->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B2", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS7", - "is_directional": "1", - "src_wire": "CLBLM_M_DQ", - "is_pseudo": "0" - }, "CLBLM_R.CLBLM_BYP1->CLBLM_M_AX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_AX", - "is_directional": "1", "src_wire": "CLBLM_BYP1", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX23->CLBLM_L_C3": { "can_invert": "0", - "dst_wire": "CLBLM_L_C3", "is_directional": "1", - "src_wire": "CLBLM_IMUX23", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX44->CLBLM_M_D4": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX44", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_COUT->>CLBLM_L_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_DMUX", - "is_directional": "1", - "src_wire": "CLBLM_L_COUT", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_CMUX->CLBLM_LOGIC_OUTS22": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS22", - "is_directional": "1", - "src_wire": "CLBLM_M_CMUX", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_BYP4->CLBLM_M_BX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_BX", - "is_directional": "1", - "src_wire": "CLBLM_BYP4", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX38->CLBLM_M_D3": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX38", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX13->CLBLM_L_B6": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX13", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_CLK1->CLBLM_M_CLK": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CLK", - "is_directional": "1", - "src_wire": "CLBLM_CLK1", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX46->CLBLM_L_D5": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX46", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_FAN5->CLBLM_M_CI": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CI", - "is_directional": "1", - "src_wire": "CLBLM_FAN5", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX3->CLBLM_L_A2": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX3", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_D5->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D5", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX41->CLBLM_L_D1": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX41", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_D3->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D3", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX17->CLBLM_M_B3": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX17", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_A2->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A2", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_FAN2->CLBLM_M_BI": { - "can_invert": "0", - "dst_wire": "CLBLM_M_BI", - "is_directional": "1", - "src_wire": "CLBLM_FAN2", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_D->>CLBLM_L_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_DMUX", - "is_directional": "1", - "src_wire": "CLBLM_L_D", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_A2->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A2", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_D1->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D1", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_D1->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D1", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_B->>CLBLM_L_BMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_BMUX", - "is_directional": "1", - "src_wire": "CLBLM_L_B", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX4->CLBLM_M_A6": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A6", - "is_directional": "1", - "src_wire": "CLBLM_IMUX4", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX21->CLBLM_L_C4": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX21", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_COUT->>CLBLM_M_DMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_DMUX", - "is_directional": "1", - "src_wire": "CLBLM_M_COUT", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_C->CLBLM_LOGIC_OUTS10": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS10", - "is_directional": "1", - "src_wire": "CLBLM_L_C", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_C3->>CLBLM_L_C": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C", - "is_directional": "1", - "src_wire": "CLBLM_L_C3", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX37->CLBLM_L_D4": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX37", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX45->CLBLM_M_D2": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX45", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX36->CLBLM_L_D2": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D2", - "is_directional": "1", - "src_wire": "CLBLM_IMUX36", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_BQ->CLBLM_LOGIC_OUTS5": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS5", - "is_directional": "1", - "src_wire": "CLBLM_M_BQ", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX14->CLBLM_L_B1": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX14", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_FAN3->CLBLM_M_DI": { - "can_invert": "0", - "dst_wire": "CLBLM_M_DI", - "is_directional": "1", - "src_wire": "CLBLM_FAN3", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_A1->>CLBLM_M_A": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A", - "is_directional": "1", - "src_wire": "CLBLM_M_A1", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_FAN4->CLBLM_M_WE": { - "can_invert": "0", - "dst_wire": "CLBLM_M_WE", - "is_directional": "1", - "src_wire": "CLBLM_FAN4", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_D4->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D4", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_B6->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B6", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_C6->>CLBLM_M_C": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C", - "is_directional": "1", - "src_wire": "CLBLM_M_C6", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_B6->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B6", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_B5->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B5", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_BYP2->CLBLM_L_CX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_CX", - "is_directional": "1", - "src_wire": "CLBLM_BYP2", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_B1->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B1", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_A->CLBLM_LOGIC_OUTS12": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS12", - "is_directional": "1", - "src_wire": "CLBLM_M_A", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_AX" }, "CLBLM_R.CLBLM_IMUX7->CLBLM_M_A1": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A1", - "is_directional": "1", "src_wire": "CLBLM_IMUX7", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_C6->>CLBLM_L_C": { "can_invert": "0", - "dst_wire": "CLBLM_L_C", "is_directional": "1", - "src_wire": "CLBLM_L_C6", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A1" + }, + "CLBLM_R.CLBLM_M_D2->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_R.CLBLM_IMUX39->CLBLM_L_D3": { + "src_wire": "CLBLM_IMUX39", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D3" + }, + "CLBLM_R.CLBLM_BYP2->CLBLM_L_CX": { + "src_wire": "CLBLM_BYP2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CX" }, "CLBLM_R.CLBLM_IMUX33->CLBLM_L_C1": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C1", - "is_directional": "1", "src_wire": "CLBLM_IMUX33", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX19->CLBLM_L_B2": { "can_invert": "0", - "dst_wire": "CLBLM_L_B2", "is_directional": "1", - "src_wire": "CLBLM_IMUX19", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C1" }, - "CLBLM_R.CLBLM_L_D5->>CLBLM_L_D": { + "CLBLM_R.CLBLM_IMUX22->CLBLM_M_C3": { + "src_wire": "CLBLM_IMUX22", "can_invert": "0", - "dst_wire": "CLBLM_L_D", "is_directional": "1", - "src_wire": "CLBLM_L_D5", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C3" }, - "CLBLM_R.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { + "CLBLM_R.CLBLM_IMUX38->CLBLM_M_D3": { + "src_wire": "CLBLM_IMUX38", "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS17", "is_directional": "1", - "src_wire": "CLBLM_L_BMUX", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D3" }, - "CLBLM_R.CLBLM_M_C3->>CLBLM_M_C": { + "CLBLM_R.CLBLM_M_B5->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B5", "can_invert": "0", - "dst_wire": "CLBLM_M_C", "is_directional": "1", - "src_wire": "CLBLM_M_C3", - "is_pseudo": "1" + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" }, - "CLBLM_R.CLBLM_L_AQ->CLBLM_LOGIC_OUTS0": { + "CLBLM_R.CLBLM_FAN2->CLBLM_M_BI": { + "src_wire": "CLBLM_FAN2", "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS0", "is_directional": "1", - "src_wire": "CLBLM_L_AQ", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_D3->>CLBLM_L_D": { - "can_invert": "0", - "dst_wire": "CLBLM_L_D", - "is_directional": "1", - "src_wire": "CLBLM_L_D3", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_B2->>CLBLM_M_B": { - "can_invert": "0", - "dst_wire": "CLBLM_M_B", - "is_directional": "1", - "src_wire": "CLBLM_M_B2", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX1->CLBLM_M_A3": { - "can_invert": "0", - "dst_wire": "CLBLM_M_A3", - "is_directional": "1", - "src_wire": "CLBLM_IMUX1", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_DMUX->CLBLM_LOGIC_OUTS19": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS19", - "is_directional": "1", - "src_wire": "CLBLM_L_DMUX", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_B5->>CLBLM_L_B": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B", - "is_directional": "1", - "src_wire": "CLBLM_L_B5", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_C1->>CLBLM_M_C": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C", - "is_directional": "1", - "src_wire": "CLBLM_M_C1", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_FAN6->CLBLM_L_CE": { - "can_invert": "0", - "dst_wire": "CLBLM_L_CE", - "is_directional": "1", - "src_wire": "CLBLM_FAN6", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_A6->>CLBLM_L_A": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A", - "is_directional": "1", - "src_wire": "CLBLM_L_A6", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_L_C5->>CLBLM_L_C": { - "can_invert": "0", - "dst_wire": "CLBLM_L_C", - "is_directional": "1", - "src_wire": "CLBLM_L_C5", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX31->CLBLM_M_C5": { - "can_invert": "0", - "dst_wire": "CLBLM_M_C5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX31", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX25->CLBLM_L_B5": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B5", - "is_directional": "1", - "src_wire": "CLBLM_IMUX25", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_BYP3->CLBLM_M_CX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_CX", - "is_directional": "1", - "src_wire": "CLBLM_BYP3", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_BYP5->CLBLM_L_BX": { - "can_invert": "0", - "dst_wire": "CLBLM_L_BX", - "is_directional": "1", - "src_wire": "CLBLM_BYP5", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_IMUX26->CLBLM_L_B4": { - "can_invert": "0", - "dst_wire": "CLBLM_L_B4", - "is_directional": "1", - "src_wire": "CLBLM_IMUX26", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_BI" }, "CLBLM_R.CLBLM_IMUX9->CLBLM_L_A5": { - "can_invert": "0", - "dst_wire": "CLBLM_L_A5", - "is_directional": "1", "src_wire": "CLBLM_IMUX9", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_COUT->CLBLM_L_COUT_N": { "can_invert": "0", - "dst_wire": "CLBLM_L_COUT_N", "is_directional": "1", - "src_wire": "CLBLM_L_COUT", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A5" }, - "CLBLM_R.CLBLM_M_B->>CLBLM_M_BMUX": { + "CLBLM_R.CLBLM_IMUX8->CLBLM_M_A5": { + "src_wire": "CLBLM_IMUX8", "can_invert": "0", - "dst_wire": "CLBLM_M_BMUX", "is_directional": "1", - "src_wire": "CLBLM_M_B", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A5" }, - "CLBLM_R.CLBLM_L_A1->>CLBLM_L_A": { + "CLBLM_R.CLBLM_IMUX37->CLBLM_L_D4": { + "src_wire": "CLBLM_IMUX37", "can_invert": "0", - "dst_wire": "CLBLM_L_A", "is_directional": "1", - "src_wire": "CLBLM_L_A1", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D4" }, - "CLBLM_R.CLBLM_L_A3->>CLBLM_L_A": { + "CLBLM_R.CLBLM_L_A4->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A4", "can_invert": "0", - "dst_wire": "CLBLM_L_A", "is_directional": "1", - "src_wire": "CLBLM_L_A3", - "is_pseudo": "1" + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" }, - "CLBLM_R.CLBLM_L_D->CLBLM_LOGIC_OUTS11": { + "CLBLM_R.CLBLM_IMUX4->CLBLM_M_A6": { + "src_wire": "CLBLM_IMUX4", "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS11", "is_directional": "1", - "src_wire": "CLBLM_L_D", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A6" }, - "CLBLM_R.CLBLM_IMUX28->CLBLM_M_C4": { + "CLBLM_R.CLBLM_IMUX10->CLBLM_L_A4": { + "src_wire": "CLBLM_IMUX10", "can_invert": "0", - "dst_wire": "CLBLM_M_C4", "is_directional": "1", - "src_wire": "CLBLM_IMUX28", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A4" }, - "CLBLM_R.CLBLM_FAN0->CLBLM_M_AI": { + "CLBLM_R.CLBLM_L_B->>CLBLM_L_BMUX": { + "src_wire": "CLBLM_L_B", "can_invert": "0", - "dst_wire": "CLBLM_M_AI", "is_directional": "1", - "src_wire": "CLBLM_FAN0", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "CLBLM_L_BMUX" }, - "CLBLM_R.CLBLM_L_B3->>CLBLM_L_B": { + "CLBLM_R.CLBLM_CLK0->CLBLM_L_CLK": { + "src_wire": "CLBLM_CLK0", "can_invert": "0", - "dst_wire": "CLBLM_L_B", "is_directional": "1", - "src_wire": "CLBLM_L_B3", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CLK" }, - "CLBLM_R.CLBLM_M_C5->>CLBLM_M_C": { + "CLBLM_R.CLBLM_BYP4->CLBLM_M_BX": { + "src_wire": "CLBLM_BYP4", "can_invert": "0", - "dst_wire": "CLBLM_M_C", "is_directional": "1", - "src_wire": "CLBLM_M_C5", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_M_D4->>CLBLM_M_D": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D", - "is_directional": "1", - "src_wire": "CLBLM_M_D4", - "is_pseudo": "1" - }, - "CLBLM_R.CLBLM_IMUX40->CLBLM_M_D1": { - "can_invert": "0", - "dst_wire": "CLBLM_M_D1", - "is_directional": "1", - "src_wire": "CLBLM_IMUX40", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_M_A->>CLBLM_M_AMUX": { - "can_invert": "0", - "dst_wire": "CLBLM_M_AMUX", - "is_directional": "1", - "src_wire": "CLBLM_M_A", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_BX" }, "CLBLM_R.CLBLM_L_DQ->CLBLM_LOGIC_OUTS3": { - "can_invert": "0", - "dst_wire": "CLBLM_LOGIC_OUTS3", - "is_directional": "1", "src_wire": "CLBLM_L_DQ", - "is_pseudo": "0" - }, - "CLBLM_R.CLBLM_L_C2->>CLBLM_L_C": { "can_invert": "0", - "dst_wire": "CLBLM_L_C", "is_directional": "1", - "src_wire": "CLBLM_L_C2", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS3" }, - "CLBLM_R.CLBLM_M_C4->>CLBLM_M_C": { + "CLBLM_R.CLBLM_FAN0->CLBLM_M_AI": { + "src_wire": "CLBLM_FAN0", "can_invert": "0", - "dst_wire": "CLBLM_M_C", "is_directional": "1", - "src_wire": "CLBLM_M_C4", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_M_AI" }, - "CLBLM_R.CLBLM_L_D2->>CLBLM_L_D": { + "CLBLM_R.CLBLM_IMUX30->CLBLM_L_C5": { + "src_wire": "CLBLM_IMUX30", "can_invert": "0", - "dst_wire": "CLBLM_L_D", "is_directional": "1", - "src_wire": "CLBLM_L_D2", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C5" }, - "CLBLM_R.CLBLM_M_A5->>CLBLM_M_A": { + "CLBLM_R.CLBLM_L_B->CLBLM_LOGIC_OUTS9": { + "src_wire": "CLBLM_L_B", "can_invert": "0", - "dst_wire": "CLBLM_M_A", "is_directional": "1", - "src_wire": "CLBLM_M_A5", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS9" + }, + "CLBLM_R.CLBLM_FAN5->CLBLM_M_CI": { + "src_wire": "CLBLM_FAN5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CI" + }, + "CLBLM_R.CLBLM_L_A6->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_R.CLBLM_L_COUT->>CLBLM_L_DMUX": { + "src_wire": "CLBLM_L_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_DMUX" + }, + "CLBLM_R.CLBLM_M_D5->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" }, "CLBLM_R.CLBLM_CTRL1->CLBLM_M_SR": { - "can_invert": "0", - "dst_wire": "CLBLM_M_SR", - "is_directional": "1", "src_wire": "CLBLM_CTRL1", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_SR" + }, + "CLBLM_R.CLBLM_CTRL0->CLBLM_L_SR": { + "src_wire": "CLBLM_CTRL0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_SR" + }, + "CLBLM_R.CLBLM_L_B1->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_R.CLBLM_M_C4->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_R.CLBLM_IMUX34->CLBLM_L_C6": { + "src_wire": "CLBLM_IMUX34", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C6" + }, + "CLBLM_R.CLBLM_M_C->CLBLM_LOGIC_OUTS14": { + "src_wire": "CLBLM_M_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS14" + }, + "CLBLM_R.CLBLM_L_D->CLBLM_LOGIC_OUTS11": { + "src_wire": "CLBLM_L_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS11" + }, + "CLBLM_R.CLBLM_L_A2->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_R.CLBLM_L_D3->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_R.CLBLM_IMUX40->CLBLM_M_D1": { + "src_wire": "CLBLM_IMUX40", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D1" + }, + "CLBLM_R.CLBLM_IMUX6->CLBLM_L_A1": { + "src_wire": "CLBLM_IMUX6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A1" + }, + "CLBLM_R.CLBLM_L_C->CLBLM_LOGIC_OUTS10": { + "src_wire": "CLBLM_L_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS10" + }, + "CLBLM_R.CLBLM_IMUX29->CLBLM_M_C2": { + "src_wire": "CLBLM_IMUX29", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C2" + }, + "CLBLM_R.CLBLM_L_B2->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_R.CLBLM_BYP3->CLBLM_M_CX": { + "src_wire": "CLBLM_BYP3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CX" + }, + "CLBLM_R.CLBLM_L_COUT->CLBLM_L_COUT_N": { + "src_wire": "CLBLM_L_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_COUT_N" + }, + "CLBLM_R.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { + "src_wire": "CLBLM_M_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS15" + }, + "CLBLM_R.CLBLM_IMUX2->CLBLM_M_A2": { + "src_wire": "CLBLM_IMUX2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A2" + }, + "CLBLM_R.CLBLM_L_D->>CLBLM_L_DMUX": { + "src_wire": "CLBLM_L_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_DMUX" + }, + "CLBLM_R.CLBLM_M_C5->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_R.CLBLM_M_C6->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_R.CLBLM_L_B4->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_R.CLBLM_L_A1->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_R.CLBLM_L_A->>CLBLM_L_AMUX": { + "src_wire": "CLBLM_L_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_AMUX" + }, + "CLBLM_R.CLBLM_IMUX41->CLBLM_L_D1": { + "src_wire": "CLBLM_IMUX41", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D1" + }, + "CLBLM_R.CLBLM_IMUX32->CLBLM_M_C1": { + "src_wire": "CLBLM_IMUX32", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C1" + }, + "CLBLM_R.CLBLM_L_C3->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_R.CLBLM_IMUX3->CLBLM_L_A2": { + "src_wire": "CLBLM_IMUX3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A2" + }, + "CLBLM_R.CLBLM_IMUX27->CLBLM_M_B4": { + "src_wire": "CLBLM_IMUX27", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B4" + }, + "CLBLM_R.CLBLM_L_A3->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_R.CLBLM_L_C4->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_R.CLBLM_L_B6->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_R.CLBLM_M_BMUX->CLBLM_LOGIC_OUTS21": { + "src_wire": "CLBLM_M_BMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS21" + }, + "CLBLM_R.CLBLM_IMUX12->CLBLM_M_B6": { + "src_wire": "CLBLM_IMUX12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B6" + }, + "CLBLM_R.CLBLM_IMUX5->CLBLM_L_A6": { + "src_wire": "CLBLM_IMUX5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A6" + }, + "CLBLM_R.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { + "src_wire": "CLBLM_M_CQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS6" + }, + "CLBLM_R.CLBLM_IMUX43->CLBLM_M_D6": { + "src_wire": "CLBLM_IMUX43", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D6" + }, + "CLBLM_R.CLBLM_L_D5->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_R.CLBLM_IMUX16->CLBLM_L_B3": { + "src_wire": "CLBLM_IMUX16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B3" + }, + "CLBLM_R.CLBLM_IMUX14->CLBLM_L_B1": { + "src_wire": "CLBLM_IMUX14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B1" + }, + "CLBLM_R.CLBLM_IMUX23->CLBLM_L_C3": { + "src_wire": "CLBLM_IMUX23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C3" + }, + "CLBLM_R.CLBLM_L_A5->>CLBLM_L_A": { + "src_wire": "CLBLM_L_A5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_A" + }, + "CLBLM_R.CLBLM_M_AQ->CLBLM_LOGIC_OUTS4": { + "src_wire": "CLBLM_M_AQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS4" + }, + "CLBLM_R.CLBLM_IMUX45->CLBLM_M_D2": { + "src_wire": "CLBLM_IMUX45", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D2" + }, + "CLBLM_R.CLBLM_M_A->>CLBLM_M_AMUX": { + "src_wire": "CLBLM_M_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_AMUX" + }, + "CLBLM_R.CLBLM_BYP0->CLBLM_L_AX": { + "src_wire": "CLBLM_BYP0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_AX" + }, + "CLBLM_R.CLBLM_M_B2->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_R.CLBLM_IMUX1->CLBLM_M_A3": { + "src_wire": "CLBLM_IMUX1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A3" + }, + "CLBLM_R.CLBLM_IMUX26->CLBLM_L_B4": { + "src_wire": "CLBLM_IMUX26", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B4" + }, + "CLBLM_R.CLBLM_L_CMUX->CLBLM_LOGIC_OUTS18": { + "src_wire": "CLBLM_L_CMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS18" + }, + "CLBLM_R.CLBLM_IMUX19->CLBLM_L_B2": { + "src_wire": "CLBLM_IMUX19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B2" + }, + "CLBLM_R.CLBLM_M_B->>CLBLM_M_BMUX": { + "src_wire": "CLBLM_M_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_BMUX" + }, + "CLBLM_R.CLBLM_L_C6->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_R.CLBLM_M_C2->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_R.CLBLM_BYP7->CLBLM_L_DX": { + "src_wire": "CLBLM_BYP7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_DX" + }, + "CLBLM_R.CLBLM_L_CQ->CLBLM_LOGIC_OUTS2": { + "src_wire": "CLBLM_L_CQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS2" + }, + "CLBLM_R.CLBLM_M_B1->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_R.CLBLM_IMUX44->CLBLM_M_D4": { + "src_wire": "CLBLM_IMUX44", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D4" + }, + "CLBLM_R.CLBLM_BYP6->CLBLM_M_DX": { + "src_wire": "CLBLM_BYP6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_DX" + }, + "CLBLM_R.CLBLM_IMUX47->CLBLM_M_D5": { + "src_wire": "CLBLM_IMUX47", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_D5" + }, + "CLBLM_R.CLBLM_L_DMUX->CLBLM_LOGIC_OUTS19": { + "src_wire": "CLBLM_L_DMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS19" + }, + "CLBLM_R.CLBLM_M_A5->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_R.CLBLM_IMUX0->CLBLM_L_A3": { + "src_wire": "CLBLM_IMUX0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_A3" + }, + "CLBLM_R.CLBLM_M_D->>CLBLM_M_DMUX": { + "src_wire": "CLBLM_M_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_DMUX" + }, + "CLBLM_R.CLBLM_IMUX25->CLBLM_L_B5": { + "src_wire": "CLBLM_IMUX25", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B5" + }, + "CLBLM_R.CLBLM_M_CMUX->CLBLM_LOGIC_OUTS22": { + "src_wire": "CLBLM_M_CMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS22" + }, + "CLBLM_R.CLBLM_IMUX11->CLBLM_M_A4": { + "src_wire": "CLBLM_IMUX11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_A4" + }, + "CLBLM_R.CLBLM_M_B6->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_R.CLBLM_L_A->CLBLM_LOGIC_OUTS8": { + "src_wire": "CLBLM_L_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS8" + }, + "CLBLM_R.CLBLM_IMUX17->CLBLM_M_B3": { + "src_wire": "CLBLM_IMUX17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B3" + }, + "CLBLM_R.CLBLM_L_B5->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_R.CLBLM_IMUX13->CLBLM_L_B6": { + "src_wire": "CLBLM_IMUX13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_B6" + }, + "CLBLM_R.CLBLM_IMUX18->CLBLM_M_B2": { + "src_wire": "CLBLM_IMUX18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B2" + }, + "CLBLM_R.CLBLM_L_D2->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_R.CLBLM_M_A6->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_R.CLBLM_IMUX20->CLBLM_L_C2": { + "src_wire": "CLBLM_IMUX20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C2" + }, + "CLBLM_R.CLBLM_M_C1->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_R.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { + "src_wire": "CLBLM_L_BMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS17" + }, + "CLBLM_R.CLBLM_M_C->>CLBLM_M_CMUX": { + "src_wire": "CLBLM_M_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_CMUX" + }, + "CLBLM_R.CLBLM_IMUX36->CLBLM_L_D2": { + "src_wire": "CLBLM_IMUX36", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D2" + }, + "CLBLM_R.CLBLM_L_D1->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_R.CLBLM_L_C->>CLBLM_L_CMUX": { + "src_wire": "CLBLM_L_C", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_CMUX" + }, + "CLBLM_R.CLBLM_M_BQ->CLBLM_LOGIC_OUTS5": { + "src_wire": "CLBLM_M_BQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS5" + }, + "CLBLM_R.CLBLM_CLK1->CLBLM_M_CLK": { + "src_wire": "CLBLM_CLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CLK" + }, + "CLBLM_R.CLBLM_BYP5->CLBLM_L_BX": { + "src_wire": "CLBLM_BYP5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_BX" + }, + "CLBLM_R.CLBLM_FAN7->CLBLM_M_CE": { + "src_wire": "CLBLM_FAN7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_CE" + }, + "CLBLM_R.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { + "src_wire": "CLBLM_M_DMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS23" + }, + "CLBLM_R.CLBLM_IMUX35->CLBLM_M_C6": { + "src_wire": "CLBLM_IMUX35", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C6" + }, + "CLBLM_R.CLBLM_L_B3->>CLBLM_L_B": { + "src_wire": "CLBLM_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_B" + }, + "CLBLM_R.CLBLM_M_D4->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_R.CLBLM_FAN3->CLBLM_M_DI": { + "src_wire": "CLBLM_FAN3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_DI" + }, + "CLBLM_R.CLBLM_M_B3->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_R.CLBLM_FAN6->CLBLM_L_CE": { + "src_wire": "CLBLM_FAN6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_CE" + }, + "CLBLM_R.CLBLM_M_D3->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_R.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { + "src_wire": "CLBLM_M_DQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS7" + }, + "CLBLM_R.CLBLM_M_D6->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_R.CLBLM_M_COUT->>CLBLM_M_DMUX": { + "src_wire": "CLBLM_M_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_DMUX" + }, + "CLBLM_R.CLBLM_IMUX28->CLBLM_M_C4": { + "src_wire": "CLBLM_IMUX28", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C4" + }, + "CLBLM_R.CLBLM_M_B4->>CLBLM_M_B": { + "src_wire": "CLBLM_M_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_B" + }, + "CLBLM_R.CLBLM_IMUX21->CLBLM_L_C4": { + "src_wire": "CLBLM_IMUX21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_C4" + }, + "CLBLM_R.CLBLM_L_AQ->CLBLM_LOGIC_OUTS0": { + "src_wire": "CLBLM_L_AQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS0" + }, + "CLBLM_R.CLBLM_M_AMUX->CLBLM_LOGIC_OUTS20": { + "src_wire": "CLBLM_M_AMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS20" + }, + "CLBLM_R.CLBLM_M_A4->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_R.CLBLM_M_B->CLBLM_LOGIC_OUTS13": { + "src_wire": "CLBLM_M_B", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS13" + }, + "CLBLM_R.CLBLM_M_A->CLBLM_LOGIC_OUTS12": { + "src_wire": "CLBLM_M_A", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS12" + }, + "CLBLM_R.CLBLM_L_C2->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_R.CLBLM_IMUX15->CLBLM_M_B1": { + "src_wire": "CLBLM_IMUX15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B1" + }, + "CLBLM_R.CLBLM_IMUX46->CLBLM_L_D5": { + "src_wire": "CLBLM_IMUX46", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D5" + }, + "CLBLM_R.CLBLM_IMUX42->CLBLM_L_D6": { + "src_wire": "CLBLM_IMUX42", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_L_D6" + }, + "CLBLM_R.CLBLM_M_A3->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_R.CLBLM_L_D6->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_R.CLBLM_L_AMUX->CLBLM_LOGIC_OUTS16": { + "src_wire": "CLBLM_L_AMUX", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS16" + }, + "CLBLM_R.CLBLM_M_A2->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_R.CLBLM_M_A1->>CLBLM_M_A": { + "src_wire": "CLBLM_M_A1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_A" + }, + "CLBLM_R.CLBLM_IMUX31->CLBLM_M_C5": { + "src_wire": "CLBLM_IMUX31", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_C5" + }, + "CLBLM_R.CLBLM_FAN4->CLBLM_M_WE": { + "src_wire": "CLBLM_FAN4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_WE" + }, + "CLBLM_R.CLBLM_L_D4->>CLBLM_L_D": { + "src_wire": "CLBLM_L_D4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_D" + }, + "CLBLM_R.CLBLM_M_COUT->CLBLM_M_COUT_N": { + "src_wire": "CLBLM_M_COUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_COUT_N" + }, + "CLBLM_R.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { + "src_wire": "CLBLM_L_BQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_LOGIC_OUTS1" + }, + "CLBLM_R.CLBLM_M_C3->>CLBLM_M_C": { + "src_wire": "CLBLM_M_C3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_C" + }, + "CLBLM_R.CLBLM_L_C1->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_R.CLBLM_M_D1->>CLBLM_M_D": { + "src_wire": "CLBLM_M_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_M_D" + }, + "CLBLM_R.CLBLM_L_C5->>CLBLM_L_C": { + "src_wire": "CLBLM_L_C5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLBLM_L_C" + }, + "CLBLM_R.CLBLM_IMUX24->CLBLM_M_B5": { + "src_wire": "CLBLM_IMUX24", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLBLM_M_B5" } }, - "tile_type": "CLBLM_R" + "wires": [ + "CLBLM_EE4A1", + "CLBLM_M_BMUX", + "CLBLM_LOGIC_OUTS18", + "CLBLM_SW2A0", + "CLBLM_EE4C1", + "CLBLM_M_AI", + "CLBLM_L_A", + "CLBLM_EE2BEG2", + "CLBLM_WW2END3", + "CLBLM_LOGIC_OUTS14", + "CLBLM_SW4A1", + "CLBLM_L_A4", + "CLBLM_CLK0", + "CLBLM_EE2A2", + "CLBLM_LH11", + "CLBLM_M_CX", + "CLBLM_LH2", + "CLBLM_ER1BEG2", + "CLBLM_IMUX29", + "CLBLM_IMUX41", + "CLBLM_SE2A1", + "CLBLM_EE4C2", + "CLBLM_CTRL0", + "CLBLM_L_C4", + "CLBLM_IMUX4", + "CLBLM_M_B3", + "CLBLM_LOGIC_OUTS8", + "CLBLM_L_B1", + "CLBLM_LH10", + "CLBLM_WL1END1", + "CLBLM_WR1END2", + "CLBLM_L_D5", + "CLBLM_M_B5", + "CLBLM_LOGIC_OUTS17", + "CLBLM_M_AMUX", + "CLBLM_WR1END3", + "CLBLM_WW4C0", + "CLBLM_L_DMUX", + "CLBLM_WW4C3", + "CLBLM_SE2A2", + "CLBLM_NE4C3", + "CLBLM_FAN2", + "CLBLM_IMUX37", + "CLBLM_WR1END1", + "CLBLM_LH1", + "CLBLM_M_SR", + "CLBLM_M_A1", + "CLBLM_FAN7", + "CLBLM_LOGIC_OUTS4", + "CLBLM_IMUX21", + "CLBLM_M_D5", + "CLBLM_SE2A0", + "CLBLM_M_DI", + "CLBLM_SW2A2", + "CLBLM_L_D", + "CLBLM_EE4A0", + "CLBLM_M_C1", + "CLBLM_L_C5", + "CLBLM_M_CLK", + "CLBLM_EE2BEG3", + "CLBLM_M_A", + "CLBLM_SW4END2", + "CLBLM_M_AX", + "CLBLM_IMUX30", + "CLBLM_IMUX5", + "CLBLM_NE4BEG2", + "CLBLM_NE2A0", + "CLBLM_NE4C0", + "CLBLM_IMUX31", + "CLBLM_IMUX27", + "CLBLM_NE4BEG0", + "CLBLM_IMUX7", + "CLBLM_M_A6", + "CLBLM_LH7", + "CLBLM_L_C", + "CLBLM_ER1BEG3", + "CLBLM_EL1BEG2", + "CLBLM_L_B6", + "CLBLM_L_A6", + "CLBLM_L_CE", + "CLBLM_M_CI", + "CLBLM_EE4BEG2", + "CLBLM_M_D2", + "CLBLM_LOGIC_OUTS0", + "CLBLM_WW4END2", + "CLBLM_SE4BEG1", + "CLBLM_LOGIC_OUTS15", + "CLBLM_LOGIC_OUTS3", + "CLBLM_LOGIC_OUTS2", + "CLBLM_WW4B0", + "CLBLM_M_B2", + "CLBLM_L_C3", + "CLBLM_IMUX22", + "CLBLM_SE4C3", + "CLBLM_WL1END0", + "CLBLM_M_D4", + "CLBLM_LOGIC_OUTS10", + "CLBLM_L_A2", + "CLBLM_WW2END1", + "CLBLM_WW4B2", + "CLBLM_EE2A1", + "CLBLM_WW4B3", + "CLBLM_L_B3", + "CLBLM_IMUX47", + "CLBLM_IMUX9", + "CLBLM_L_AQ", + "CLBLM_SW4A2", + "CLBLM_LH9", + "CLBLM_SE2A3", + "CLBLM_CTRL1", + "CLBLM_SW4END1", + "CLBLM_L_D3", + "CLBLM_EE4A2", + "CLBLM_NW4A0", + "CLBLM_NE2A2", + "CLBLM_FAN5", + "CLBLM_SW2A3", + "CLBLM_IMUX8", + "CLBLM_M_D", + "CLBLM_IMUX24", + "CLBLM_WW2END0", + "CLBLM_MONITOR_N", + "CLBLM_M_C6", + "CLBLM_SE4C0", + "CLBLM_EE4B1", + "CLBLM_LOGIC_OUTS6", + "CLBLM_IMUX26", + "CLBLM_WW4C1", + "CLBLM_WW2A2", + "CLBLM_M_DX", + "CLBLM_LOGIC_OUTS1", + "CLBLM_WL1END2", + "CLBLM_IMUX20", + "CLBLM_EE4BEG0", + "CLBLM_IMUX34", + "CLBLM_EE4B2", + "CLBLM_IMUX18", + "CLBLM_WW4END1", + "CLBLM_IMUX33", + "CLBLM_EE2A0", + "CLBLM_L_COUT", + "CLBLM_WW4A1", + "CLBLM_WW2A3", + "CLBLM_IMUX13", + "CLBLM_LH4", + "CLBLM_L_AX", + "CLBLM_M_A2", + "CLBLM_IMUX17", + "CLBLM_EE4A3", + "CLBLM_WW2END2", + "CLBLM_BYP2", + "CLBLM_SW4END3", + "CLBLM_L_A1", + "CLBLM_BYP0", + "CLBLM_NW4A3", + "CLBLM_NW4A1", + "CLBLM_SE4C1", + "CLBLM_L_DX", + "CLBLM_LOGIC_OUTS20", + "CLBLM_L_DQ", + "CLBLM_EE4B3", + "CLBLM_M_C5", + "CLBLM_EL1BEG0", + "CLBLM_IMUX23", + "CLBLM_L_D4", + "CLBLM_NW4END1", + "CLBLM_L_CLK", + "CLBLM_NW2A1", + "CLBLM_L_B2", + "CLBLM_IMUX36", + "CLBLM_WR1END0", + "CLBLM_IMUX0", + "CLBLM_IMUX2", + "CLBLM_M_CMUX", + "CLBLM_IMUX15", + "CLBLM_FAN1", + "CLBLM_IMUX43", + "CLBLM_SE4C2", + "CLBLM_EE4B0", + "CLBLM_LOGIC_OUTS12", + "CLBLM_SW4END0", + "CLBLM_IMUX10", + "CLBLM_IMUX42", + "CLBLM_M_BX", + "CLBLM_NE4C2", + "CLBLM_L_AMUX", + "CLBLM_NE2A1", + "CLBLM_LOGIC_OUTS22", + "CLBLM_IMUX6", + "CLBLM_M_COUT", + "CLBLM_WW4C2", + "CLBLM_BYP4", + "CLBLM_IMUX44", + "CLBLM_SE4BEG0", + "CLBLM_NE2A3", + "CLBLM_M_AQ", + "CLBLM_WW4END0", + "CLBLM_SE4BEG2", + "CLBLM_NW4END2", + "CLBLM_IMUX46", + "CLBLM_WW4A3", + "CLBLM_M_D1", + "CLBLM_NW4END0", + "CLBLM_LOGIC_OUTS23", + "CLBLM_FAN0", + "CLBLM_L_C6", + "CLBLM_IMUX40", + "CLBLM_M_BI", + "CLBLM_LOGIC_OUTS13", + "CLBLM_M_CIN", + "CLBLM_NW4A2", + "CLBLM_EE4BEG1", + "CLBLM_SW2A1", + "CLBLM_MONITOR_P", + "CLBLM_NW2A2", + "CLBLM_M_D6", + "CLBLM_L_A3", + "CLBLM_BYP5", + "CLBLM_IMUX39", + "CLBLM_BYP6", + "CLBLM_EE2BEG0", + "CLBLM_L_C1", + "CLBLM_IMUX11", + "CLBLM_M_B", + "CLBLM_LH5", + "CLBLM_LH8", + "CLBLM_IMUX16", + "CLBLM_M_DMUX", + "CLBLM_EE4C0", + "CLBLM_IMUX1", + "CLBLM_WL1END3", + "CLBLM_L_B5", + "CLBLM_IMUX38", + "CLBLM_EE4C3", + "CLBLM_LH12", + "CLBLM_FAN3", + "CLBLM_L_BMUX", + "CLBLM_M_C", + "CLBLM_ER1BEG1", + "CLBLM_SW4A0", + "CLBLM_M_COUT_N", + "CLBLM_L_CIN", + "CLBLM_IMUX35", + "CLBLM_WW4A2", + "CLBLM_WW4B1", + "CLBLM_LOGIC_OUTS11", + "CLBLM_L_CMUX", + "CLBLM_L_BQ", + "CLBLM_M_WE", + "CLBLM_BYP7", + "CLBLM_M_A5", + "CLBLM_BYP3", + "CLBLM_EE2BEG1", + "CLBLM_EE2A3", + "CLBLM_M_D3", + "CLBLM_WW2A1", + "CLBLM_FAN6", + "CLBLM_NW2A3", + "CLBLM_LOGIC_OUTS5", + "CLBLM_SE4BEG3", + "CLBLM_L_D1", + "CLBLM_L_C2", + "CLBLM_IMUX3", + "CLBLM_L_B4", + "CLBLM_M_C2", + "CLBLM_LH6", + "CLBLM_NE4C1", + "CLBLM_M_C4", + "CLBLM_LOGIC_OUTS16", + "CLBLM_L_COUT_N", + "CLBLM_IMUX14", + "CLBLM_EE4BEG3", + "CLBLM_EL1BEG1", + "CLBLM_M_CQ", + "CLBLM_M_A4", + "CLBLM_LOGIC_OUTS21", + "CLBLM_L_D2", + "CLBLM_WW2A0", + "CLBLM_L_SR", + "CLBLM_IMUX12", + "CLBLM_ER1BEG0", + "CLBLM_NE4BEG3", + "CLBLM_LOGIC_OUTS7", + "CLBLM_L_B", + "CLBLM_M_A3", + "CLBLM_L_BX", + "CLBLM_CLK1", + "CLBLM_NW4END3", + "CLBLM_L_CX", + "CLBLM_L_A5", + "CLBLM_NE4BEG1", + "CLBLM_LOGIC_OUTS9", + "CLBLM_LH3", + "CLBLM_WW4A0", + "CLBLM_M_B4", + "CLBLM_L_D6", + "CLBLM_M_C3", + "CLBLM_NW2A0", + "CLBLM_M_CE", + "CLBLM_M_B1", + "CLBLM_M_B6", + "CLBLM_M_DQ", + "CLBLM_LOGIC_OUTS19", + "CLBLM_IMUX32", + "CLBLM_IMUX28", + "CLBLM_IMUX45", + "CLBLM_SW4A3", + "CLBLM_BYP1", + "CLBLM_FAN4", + "CLBLM_IMUX25", + "CLBLM_IMUX19", + "CLBLM_WW4END3", + "CLBLM_M_BQ", + "CLBLM_L_CQ", + "CLBLM_EL1BEG3" + ], + "tile_type": "CLBLM_R", + "sites": [ + { + "site_pins": { + "BQ": "CLBLM_M_BQ", + "CX": "CLBLM_M_CX", + "C1": "CLBLM_M_C1", + "B6": "CLBLM_M_B6", + "DMUX": "CLBLM_M_DMUX", + "SR": "CLBLM_M_SR", + "B": "CLBLM_M_B", + "D6": "CLBLM_M_D6", + "D5": "CLBLM_M_D5", + "A5": "CLBLM_M_A5", + "AMUX": "CLBLM_M_AMUX", + "WE": "CLBLM_M_WE", + "C6": "CLBLM_M_C6", + "AQ": "CLBLM_M_AQ", + "B5": "CLBLM_M_B5", + "B3": "CLBLM_M_B3", + "DQ": "CLBLM_M_DQ", + "D3": "CLBLM_M_D3", + "C": "CLBLM_M_C", + "DX": "CLBLM_M_DX", + "C4": "CLBLM_M_C4", + "A4": "CLBLM_M_A4", + "DI": "CLBLM_M_DI", + "A1": "CLBLM_M_A1", + "D1": "CLBLM_M_D1", + "BX": "CLBLM_M_BX", + "COUT": "CLBLM_M_COUT", + "CLK": "CLBLM_M_CLK", + "D": "CLBLM_M_D", + "A2": "CLBLM_M_A2", + "AI": "CLBLM_M_AI", + "CQ": "CLBLM_M_CQ", + "D4": "CLBLM_M_D4", + "C5": "CLBLM_M_C5", + "CIN": "CLBLM_M_CIN", + "D2": "CLBLM_M_D2", + "B2": "CLBLM_M_B2", + "BI": "CLBLM_M_BI", + "A6": "CLBLM_M_A6", + "CMUX": "CLBLM_M_CMUX", + "A3": "CLBLM_M_A3", + "C3": "CLBLM_M_C3", + "AX": "CLBLM_M_AX", + "B1": "CLBLM_M_B1", + "CI": "CLBLM_M_CI", + "B4": "CLBLM_M_B4", + "A": "CLBLM_M_A", + "BMUX": "CLBLM_M_BMUX", + "CE": "CLBLM_M_CE", + "C2": "CLBLM_M_C2" + }, + "type": "SLICEM", + "prefix": "SLICE", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BQ": "CLBLM_L_BQ", + "CX": "CLBLM_L_CX", + "C1": "CLBLM_L_C1", + "B6": "CLBLM_L_B6", + "DMUX": "CLBLM_L_DMUX", + "SR": "CLBLM_L_SR", + "B": "CLBLM_L_B", + "D6": "CLBLM_L_D6", + "D5": "CLBLM_L_D5", + "A5": "CLBLM_L_A5", + "AMUX": "CLBLM_L_AMUX", + "C6": "CLBLM_L_C6", + "AQ": "CLBLM_L_AQ", + "B5": "CLBLM_L_B5", + "B3": "CLBLM_L_B3", + "DQ": "CLBLM_L_DQ", + "D3": "CLBLM_L_D3", + "C": "CLBLM_L_C", + "DX": "CLBLM_L_DX", + "C4": "CLBLM_L_C4", + "A4": "CLBLM_L_A4", + "A1": "CLBLM_L_A1", + "D1": "CLBLM_L_D1", + "BX": "CLBLM_L_BX", + "COUT": "CLBLM_L_COUT", + "CLK": "CLBLM_L_CLK", + "D": "CLBLM_L_D", + "A2": "CLBLM_L_A2", + "CQ": "CLBLM_L_CQ", + "D4": "CLBLM_L_D4", + "C5": "CLBLM_L_C5", + "CIN": "CLBLM_L_CIN", + "D2": "CLBLM_L_D2", + "B2": "CLBLM_L_B2", + "A6": "CLBLM_L_A6", + "CMUX": "CLBLM_L_CMUX", + "A3": "CLBLM_L_A3", + "C3": "CLBLM_L_C3", + "AX": "CLBLM_L_AX", + "B1": "CLBLM_L_B1", + "B4": "CLBLM_L_B4", + "A": "CLBLM_L_A", + "BMUX": "CLBLM_L_BMUX", + "CE": "CLBLM_L_CE", + "C2": "CLBLM_L_C2" + }, + "type": "SLICEL", + "prefix": "SLICE", + "name": "X1Y0", + "x_coord": 1, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_BUFG_BOT_R.json b/artix7/tile_type_CLK_BUFG_BOT_R.json index a08e7ca..7632596 100644 --- a/artix7/tile_type_CLK_BUFG_BOT_R.json +++ b/artix7/tile_type_CLK_BUFG_BOT_R.json @@ -1,3569 +1,3569 @@ { - "wires": [ - "CLK_BUFG_R_BUFGCTRL7_CE1", - "CLK_BUFG_LOGIC_OUTS_B5_2", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW4END2_1", - "CLK_BUFG_BUFGCTRL11_I1", - "CLK_HROW_SW4END0_2", - "CLK_BUFG_BOT_R_CK_MUXED31", - "CLK_HROW_EE4B1_2", - "CLK_BUFG_IMUX22_3", - "CLK_HROW_WW2END2_0", - "CLK_BUFG_BUFGCTRL9_O", - "CLK_BUFG_CK_GCLK16", - "CLK_HROW_EE2A3_2", - "CLK_HROW_EE4B3_0", - "CLK_BUFG_CK_GCLK0", - "CLK_BUFG_BUFGCTRL0_I0", - "CLK_BUFG_R_CK_FB_TEST1_7", - "CLK_BUFG_IMUX30_0", - "CLK_HROW_SW4END1_0", - "CLK_BUFG_R_BUFGCTRL2_S1", - "CLK_HROW_NW4END2_2", - "CLK_BUFG_BOT_R_CK_MUXED4", - "CLK_HROW_BYP6_2", - "CLK_HROW_NE2A2_2", - "CLK_HROW_EE2A1_0", - "CLK_HROW_WW4C3_2", - "CLK_BUFG_BUFGCTRL8_I0", - "CLK_HROW_WW4A2_0", - "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "CLK_BUFG_LOGIC_OUTS_B3_0", - "CLK_BUFG_BUFGCTRL15_I0", - "CLK_BUFG_IMUX23_3", - "CLK_HROW_NW4A2_1", - "CLK_BUFG_IMUX16_2", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_WW4END0_0", - "CLK_HROW_EE2A3_1", - "CLK_BUFG_IMUX27_2", - "CLK_BUFG_IMUX9_0", - "CLK_BUFG_BUFGCTRL14_I0", - "CLK_BUFG_IMUX28_0", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WW4END2_3", - "CLK_BUFG_R_BUFGCTRL13_CE1", - "CLK_BUFG_IMUX44_3", - "CLK_BUFG_R_BUFGCTRL3_S1", - "CLK_BUFG_BUFGCTRL5_I0", - "CLK_HROW_BYP7_3", - "CLK_HROW_WR1END3_3", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE2A2_3", - "CLK_BUFG_LOGIC_OUTS_B16_0", - "CLK_BUFG_IMUX7_3", - "CLK_BUFG_BUFGCTRL13_I1", - "CLK_HROW_WW4END0_3", - "CLK_BUFG_LOGIC_OUTS_B10_2", - "CLK_BUFG_IMUX5_3", - "CLK_HROW_NE4C2_0", - "CLK_BUFG_R_CK_FB_TEST0_5", - "CLK_BUFG_IMUX12_3", - "CLK_BUFG_LOGIC_OUTS_B13_3", - "CLK_BUFG_IMUX16_3", - "CLK_HROW_NE4BEG1_2", - "CLK_BUFG_IMUX41_1", - "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "CLK_HROW_SE4BEG0_0", - "CLK_BUFG_R_CK_FB_TEST1_14", - "CLK_BUFG_IMUX46_2", - "CLK_HROW_ER1BEG3_1", - "CLK_BUFG_IMUX16_0", - "CLK_HROW_CLK1_3", - "CLK_BUFG_R_FBG_OUT2", - "CLK_HROW_WW2A1_3", - "CLK_BUFG_R_BUFGCTRL12_S0", - "CLK_BUFG_R_BUFGCTRL15_CE1", - "CLK_BUFG_R_BUFGCTRL0_S1", - "CLK_BUFG_BOT_R_CK_MUXED6", - "CLK_BUFG_IMUX9_3", - "CLK_BUFG_IMUX6_1", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_2", - "CLK_HROW_NW4END1_1", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_WW4B3_1", - "CLK_BUFG_R_FBG_OUT7", - "CLK_BUFG_CK_GCLK19", - "CLK_BUFG_IMUX25_0", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_BUFG_R_BUFGCTRL6_S0", - "CLK_HROW_LH11_0", - "CLK_BUFG_CK_GCLK17", - "CLK_BUFG_R_BUFGCTRL6_CE0", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW4B0_1", - "CLK_HROW_NW4A2_2", - "CLK_BUFG_IMUX11_3", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WW4B1_0", - "CLK_BUFG_BUFGCTRL0_I1", - "CLK_HROW_BYP1_1", - "CLK_HROW_WW4END1_1", - "CLK_HROW_NW4A0_2", - "CLK_BUFG_IMUX7_0", - "CLK_HROW_WW4END1_3", - "CLK_BUFG_BOT_R_CK_MUXED30", - "CLK_HROW_WW4C2_3", - "CLK_BUFG_R_CK_FB_TEST0_14", - "CLK_BUFG_R_BUFGCTRL10_CE0", - "CLK_HROW_FAN1_1", - "CLK_HROW_BYP5_0", - "CLK_HROW_SE4BEG2_3", - "CLK_BUFG_R_CK_FB_TEST0_8", - "CLK_HROW_NW4END0_0", - "CLK_HROW_LH1_3", - "CLK_HROW_WW2END1_2", - "CLK_HROW_SE4C2_1", - "CLK_HROW_LH5_1", - "CLK_HROW_NE4C0_1", - "CLK_HROW_WL1END0_1", - "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "CLK_HROW_SW4END2_0", - "CLK_BUFG_IMUX33_3", - "CLK_HROW_EE4BEG2_1", - "CLK_BUFG_BOT_R_CK_MUXED9", - "CLK_HROW_EE4B3_3", - "CLK_BUFG_LOGIC_OUTS_B9_0", - "CLK_HROW_WW4B3_3", - "CLK_HROW_LH4_1", - "CLK_BUFG_IMUX8_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_EE4B1_3", - "CLK_BUFG_IMUX27_0", - "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "CLK_BUFG_IMUX33_1", - "CLK_BUFG_IMUX26_3", - "CLK_HROW_NW2A2_2", - "CLK_HROW_FAN0_3", - "CLK_BUFG_R_CK_FB_TEST0_6", - "CLK_HROW_WW4B1_3", - "CLK_HROW_SE2A0_3", - "CLK_HROW_NW4END3_1", - "CLK_HROW_LH5_0", - "CLK_BUFG_IMUX3_1", - "CLK_BUFG_CK_GCLK2", - "CLK_HROW_SW4END3_0", - "CLK_BUFG_R_FBG_OUT4", - "CLK_HROW_NW4A1_3", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_WW4B1_2", - "CLK_BUFG_IMUX9_1", - "CLK_HROW_EE4BEG2_0", - "CLK_BUFG_IMUX23_1", - "CLK_BUFG_IMUX1_3", - "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "CLK_HROW_WW4A1_1", - "CLK_BUFG_R_CK_FB_TEST0_1", - "CLK_BUFG_IMUX19_3", - "CLK_HROW_NE2A0_3", - "CLK_HROW_SE4BEG2_1", - "CLK_BUFG_BUFGCTRL13_I0", - "CLK_HROW_FAN5_1", - "CLK_BUFG_LOGIC_OUTS_B4_1", - "CLK_BUFG_R_BUFGCTRL4_CE1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_SW4END1_3", - "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "CLK_BUFG_CK_GCLK3", - "CLK_BUFG_LOGIC_OUTS_B17_3", - "CLK_HROW_LH3_0", - "CLK_BUFG_CK_GCLK9", - "CLK_HROW_EE4A1_3", - "CLK_HROW_FAN6_1", - "CLK_BUFG_R_BUFGCTRL13_CE0", - "CLK_HROW_WW4END3_2", - "CLK_BUFG_BOT_R_CK_MUXED1", - "CLK_HROW_EE4C3_0", - "CLK_HROW_BYP1_0", - "CLK_HROW_NE4C3_0", - "CLK_HROW_EL1BEG3_0", - "CLK_BUFG_LOGIC_OUTS_B7_0", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_EE4A3_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "CLK_BUFG_R_CK_FB_TEST1_11", - "CLK_HROW_MONITOR_P_2", - "CLK_BUFG_IMUX4_2", - "CLK_HROW_MONITOR_P_1", - "CLK_BUFG_IMUX39_0", - "CLK_BUFG_BUFGCTRL7_I0", - "CLK_HROW_NE2A1_2", - "CLK_BUFG_LOGIC_OUTS_B23_0", - "CLK_BUFG_BUFGCTRL15_I1", - "CLK_BUFG_IMUX19_1", - "CLK_BUFG_R_FBG_OUT6", - "CLK_HROW_CTRL1_1", - "CLK_BUFG_CK_GCLK5", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_NE4C2_3", - "CLK_HROW_FAN5_2", - "CLK_BUFG_LOGIC_OUTS_B1_3", - "CLK_BUFG_R_CK_FB_TEST1_15", - "CLK_BUFG_R_BUFGCTRL8_S1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_WW4B3_0", - "CLK_HROW_NE4C0_2", - "CLK_BUFG_IMUX29_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_FAN6_3", - "CLK_HROW_BYP5_1", - "CLK_HROW_CLK1_2", - "CLK_BUFG_R_FBG_OUT1", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_FAN7_3", - "CLK_HROW_CLK1_1", - "CLK_BUFG_IMUX29_3", - "CLK_BUFG_LOGIC_OUTS_B7_2", - "CLK_BUFG_R_BUFGCTRL7_S1", - "CLK_BUFG_LOGIC_OUTS_B2_3", - "CLK_HROW_EE4A0_3", - "CLK_BUFG_LOGIC_OUTS_B12_3", - "CLK_HROW_WW4B0_0", - "CLK_BUFG_BUFGCTRL10_I0", - "CLK_HROW_NW2A0_3", - "CLK_BUFG_IMUX9_2", - "CLK_HROW_NE2A0_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_SE4C3_3", - "CLK_BUFG_IMUX0_3", - "CLK_HROW_BYP6_1", - "CLK_HROW_SW4END2_3", - "CLK_HROW_EE2A3_3", - "CLK_HROW_LH1_1", - "CLK_BUFG_IMUX34_2", - "CLK_BUFG_BOT_R_CK_MUXED11", - "CLK_HROW_FAN3_1", - "CLK_BUFG_IMUX43_2", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WW4A2_3", - "CLK_BUFG_LOGIC_OUTS_B0_0", - "CLK_HROW_WW4C1_0", - "CLK_BUFG_BUFGCTRL6_I1", - "CLK_BUFG_R_BUFGCTRL2_S0", - "CLK_BUFG_R_BUFGCTRL14_S1", - "CLK_HROW_WW2END2_3", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4A1_0", - "CLK_BUFG_IMUX41_2", - "CLK_BUFG_IMUX32_3", - "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "CLK_HROW_WW2A3_3", - "CLK_BUFG_LOGIC_OUTS_B23_1", - "CLK_BUFG_LOGIC_OUTS_B5_1", - "CLK_HROW_WR1END1_1", - "CLK_BUFG_BUFGCTRL12_I0", - "CLK_BUFG_LOGIC_OUTS_B18_1", - "CLK_BUFG_R_BUFGCTRL12_CE0", - "CLK_BUFG_R_BUFGCTRL1_S0", - "CLK_HROW_EE4BEG1_3", - "CLK_BUFG_IMUX7_2", - "CLK_HROW_LH6_3", - "CLK_HROW_WW4A1_3", - "CLK_HROW_NE4BEG0_0", - "CLK_BUFG_R_FBG_OUT11", - "CLK_HROW_SW4A0_0", - "CLK_BUFG_IMUX47_3", - "CLK_BUFG_LOGIC_OUTS_B18_3", - "CLK_BUFG_LOGIC_OUTS_B17_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH1_2", - "CLK_HROW_NE4BEG3_2", - "CLK_BUFG_IMUX34_0", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_NW2A1_1", - "CLK_HROW_WW4B2_0", - "CLK_BUFG_CK_GCLK26", - "CLK_BUFG_BUFGCTRL1_I0", - "CLK_HROW_WR1END2_3", - "CLK_HROW_NW4A1_1", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SE4BEG2_2", - "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "CLK_BUFG_IMUX36_3", - "CLK_BUFG_R_CK_FB_TEST0_15", - "CLK_BUFG_R_BUFGCTRL14_S0", - "CLK_HROW_SW2A3_3", - "CLK_HROW_EE2A1_1", - "CLK_HROW_SE4BEG2_0", - "CLK_BUFG_IMUX46_3", - "CLK_HROW_ER1BEG1_2", - "CLK_BUFG_LOGIC_OUTS_B1_1", - "CLK_BUFG_R_BUFGCTRL7_S0", - "CLK_BUFG_BOT_R_CK_MUXED0", - "CLK_BUFG_BOT_R_CK_MUXED10", - "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "CLK_HROW_FAN0_2", - "CLK_HROW_NE4C0_3", - "CLK_BUFG_R_BUFGCTRL5_S0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_CLK0_2", - "CLK_BUFG_R_BUFGCTRL6_S1", - "CLK_HROW_NE2A2_0", - "CLK_HROW_EL1BEG3_3", - "CLK_BUFG_IMUX0_2", - "CLK_HROW_WW4C1_1", - "CLK_HROW_ER1BEG2_1", - "CLK_BUFG_IMUX37_3", - "CLK_BUFG_IMUX41_0", - "CLK_BUFG_BUFGCTRL9_I1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_BUFG_IMUX15_0", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SW4A1_0", - "CLK_BUFG_IMUX36_2", - "CLK_BUFG_IMUX32_1", - "CLK_BUFG_R_CK_FB_TEST0_9", - "CLK_BUFG_IMUX18_0", - "CLK_HROW_SE4BEG1_1", - "CLK_BUFG_BUFGCTRL11_O", - "CLK_BUFG_CK_GCLK7", - "CLK_BUFG_CK_GCLK12", - "CLK_BUFG_IMUX22_1", - "CLK_BUFG_CK_GCLK4", - "CLK_BUFG_R_BUFGCTRL1_CE0", - "CLK_HROW_EE4A1_1", - "CLK_BUFG_LOGIC_OUTS_B9_1", - "CLK_BUFG_BOT_R_CK_MUXED5", - "CLK_BUFG_CK_GCLK25", - "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "CLK_HROW_SW4A3_3", - "CLK_BUFG_IMUX14_2", - "CLK_BUFG_LOGIC_OUTS_B7_1", - "CLK_BUFG_IMUX43_3", - "CLK_HROW_CTRL0_3", - "CLK_BUFG_IMUX21_1", - "CLK_BUFG_R_CK_FB_TEST0_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_LH3_2", - "CLK_BUFG_LOGIC_OUTS_B14_0", - "CLK_HROW_EE4B2_3", - "CLK_HROW_SW4A3_0", - "CLK_HROW_BYP7_2", - "CLK_BUFG_LOGIC_OUTS_B8_2", - "CLK_BUFG_CK_GCLK14", - "CLK_BUFG_LOGIC_OUTS_B0_3", - "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "CLK_HROW_LH5_3", - "CLK_BUFG_LOGIC_OUTS_B15_2", - "CLK_HROW_WR1END1_0", - "CLK_HROW_CTRL0_1", - "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "CLK_HROW_NW4END3_3", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A1_2", - "CLK_HROW_NE4BEG2_1", - "CLK_BUFG_LOGIC_OUTS_B23_2", - "CLK_BUFG_R_BUFGCTRL13_S1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_LH1_0", - "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "CLK_BUFG_IMUX6_2", - "CLK_HROW_WW4C1_2", - "CLK_BUFG_CK_GCLK23", - "CLK_BUFG_IMUX2_1", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_WW4END2_2", - "CLK_BUFG_IMUX39_3", - "CLK_BUFG_IMUX47_0", - "CLK_HROW_EE4A1_2", - "CLK_BUFG_BUFGCTRL4_O", - "CLK_BUFG_BOT_R_CK_MUXED16", - "CLK_HROW_WW2A2_2", - "CLK_HROW_LH10_3", - "CLK_BUFG_IMUX47_1", - "CLK_HROW_FAN4_0", - "CLK_BUFG_IMUX46_1", - "CLK_HROW_LH8_0", - "CLK_HROW_WW2END3_2", - "CLK_HROW_LH12_3", - "CLK_BUFG_IMUX8_3", - "CLK_BUFG_BUFGCTRL2_O", - "CLK_HROW_EE4A3_0", - "CLK_HROW_LH4_2", - "CLK_HROW_NE4BEG0_3", - "CLK_BUFG_LOGIC_OUTS_B0_1", - "CLK_HROW_EE4BEG0_0", - "CLK_BUFG_IMUX2_0", - "CLK_HROW_SW2A0_3", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_LH6_0", - "CLK_BUFG_LOGIC_OUTS_B5_0", - "CLK_HROW_WW4END0_2", - "CLK_BUFG_IMUX27_1", - "CLK_BUFG_R_BUFGCTRL0_CE0", - "CLK_HROW_NW2A3_0", - "CLK_BUFG_IMUX2_3", - "CLK_BUFG_R_BUFGCTRL5_CE1", - "CLK_HROW_FAN3_0", - "CLK_BUFG_LOGIC_OUTS_B20_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_NE2A2_1", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_NW2A3_3", - "CLK_HROW_FAN6_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW2A1_1", - "CLK_HROW_SW4END3_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_WW2END3_0", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_NE4C3_1", - "CLK_BUFG_BUFGCTRL7_O", - "CLK_BUFG_BUFGCTRL10_O", - "CLK_HROW_NW4END1_0", - "CLK_HROW_EE4B0_3", - "CLK_HROW_CLK0_3", - "CLK_HROW_SW2A3_0", - "CLK_BUFG_BUFGCTRL15_O", - "CLK_BUFG_LOGIC_OUTS_B4_2", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_WW4END1_2", - "CLK_BUFG_IMUX28_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_ER1BEG3_2", - "CLK_BUFG_IMUX4_0", - "CLK_BUFG_BUFGCTRL12_I1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_EE4C1_1", - "CLK_HROW_NE2A3_3", - "CLK_HROW_WW4A3_1", - "CLK_HROW_BYP3_1", - "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "CLK_HROW_SE2A3_2", - "CLK_BUFG_IMUX33_2", - "CLK_HROW_EE2A2_2", - "CLK_HROW_LH11_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_BYP5_2", - "CLK_HROW_EE4B3_1", - "CLK_BUFG_BUFGCTRL9_I0", - "CLK_BUFG_LOGIC_OUTS_B19_2", - "CLK_BUFG_IMUX1_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_FAN2_3", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_LH9_3", - "CLK_HROW_EE2BEG1_2", - "CLK_BUFG_IMUX22_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_FAN2_2", - "CLK_BUFG_R_BUFGCTRL2_CE1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_WW4B2_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_SW2A0_2", - "CLK_BUFG_R_BUFGCTRL5_CE0", - "CLK_HROW_WL1END0_3", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_LH7_1", - "CLK_BUFG_LOGIC_OUTS_B2_2", - "CLK_HROW_EL1BEG1_1", - "CLK_BUFG_IMUX5_1", - "CLK_BUFG_R_BUFGCTRL4_S0", - "CLK_HROW_WW4END1_0", - "CLK_BUFG_IMUX34_3", - "CLK_BUFG_LOGIC_OUTS_B3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_EE2BEG0_3", - "CLK_BUFG_LOGIC_OUTS_B13_1", - "CLK_HROW_BYP1_3", - "CLK_HROW_BYP0_2", - "CLK_HROW_NE2A0_0", - "CLK_BUFG_IMUX30_1", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NW2A2_3", - "CLK_BUFG_IMUX18_3", - "CLK_BUFG_LOGIC_OUTS_B2_1", - "CLK_HROW_SW4A3_1", - "CLK_BUFG_R_CK_FB_TEST0_13", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_SE2A1_1", - "CLK_BUFG_IMUX15_1", - "CLK_HROW_WW2A3_1", - "CLK_BUFG_IMUX10_3", - "CLK_HROW_WR1END0_3", - "CLK_BUFG_R_FBG_OUT0", - "CLK_BUFG_LOGIC_OUTS_B1_0", - "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "CLK_HROW_NW4A3_0", - "CLK_BUFG_IMUX44_1", - "CLK_HROW_BYP4_1", - "CLK_HROW_NE2A3_1", - "CLK_BUFG_IMUX42_0", - "CLK_BUFG_IMUX46_0", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SW2A1_0", - "CLK_HROW_BYP2_3", - "CLK_HROW_EE2BEG3_3", - "CLK_BUFG_R_CK_FB_TEST1_4", - "CLK_HROW_ER1BEG3_3", - "CLK_BUFG_BOT_R_CK_MUXED17", - "CLK_HROW_SW4END0_1", - "CLK_BUFG_BOT_R_CK_MUXED13", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_BUFG_BUFGCTRL11_I0", - "CLK_HROW_BYP3_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_FAN2_1", - "CLK_HROW_BYP0_0", - "CLK_HROW_LH12_1", - "CLK_HROW_NE4BEG1_3", - "CLK_BUFG_IMUX4_1", - "CLK_HROW_EE4A2_2", - "CLK_BUFG_IMUX37_2", - "CLK_BUFG_BUFGCTRL8_I1", - "CLK_HROW_WR1END0_2", - "CLK_BUFG_IMUX8_2", - "CLK_BUFG_LOGIC_OUTS_B16_1", - "CLK_BUFG_R_BUFGCTRL14_CE1", - "CLK_BUFG_R_BUFGCTRL8_S0", - "CLK_BUFG_CK_GCLK8", - "CLK_BUFG_IMUX36_1", - "CLK_HROW_SW2A0_1", - "CLK_HROW_ER1BEG3_0", - "CLK_BUFG_IMUX45_0", - "CLK_BUFG_LOGIC_OUTS_B20_0", - "CLK_BUFG_IMUX1_1", - "CLK_BUFG_IMUX4_3", - "CLK_HROW_WL1END1_1", - "CLK_BUFG_CK_GCLK21", - "CLK_BUFG_LOGIC_OUTS_B19_0", - "CLK_BUFG_IMUX36_0", - "CLK_BUFG_R_BUFGCTRL15_S0", - "CLK_HROW_SW4END2_2", - "CLK_BUFG_IMUX15_3", - "CLK_BUFG_LOGIC_OUTS_B15_0", - "CLK_BUFG_IMUX25_1", - "CLK_HROW_LH11_3", - "CLK_BUFG_IMUX14_1", - "CLK_BUFG_IMUX39_1", - "CLK_BUFG_R_CK_FB_TEST0_12", - "CLK_BUFG_IMUX41_3", - "CLK_HROW_LH2_1", - "CLK_BUFG_LOGIC_OUTS_B8_1", - "CLK_HROW_SW2A0_0", - "CLK_BUFG_IMUX20_2", - "CLK_BUFG_IMUX45_2", - "CLK_BUFG_IMUX40_0", - "CLK_BUFG_IMUX3_0", - "CLK_BUFG_CK_GCLK10", - "CLK_BUFG_BUFGCTRL14_O", - "CLK_BUFG_BUFGCTRL6_O", - "CLK_HROW_WW4C0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EL1BEG1_3", - "CLK_BUFG_BOT_R_CK_MUXED21", - "CLK_HROW_LH9_0", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_WW4C0_0", - "CLK_BUFG_R_FBG_OUT8", - "CLK_BUFG_IMUX21_0", - "CLK_HROW_EE2BEG1_3", - "CLK_BUFG_IMUX12_1", - "CLK_BUFG_IMUX26_2", - "CLK_HROW_SW2A2_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NE4C2_2", - "CLK_BUFG_CK_GCLK1", - "CLK_BUFG_LOGIC_OUTS_B0_2", - "CLK_HROW_WW4A1_0", - "CLK_HROW_MONITOR_P_3", - "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "CLK_BUFG_IMUX40_2", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_EE4C0_3", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_WW4END3_0", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4C3_3", - "CLK_HROW_NW4A3_2", - "CLK_BUFG_IMUX40_3", - "CLK_BUFG_R_BUFGCTRL3_CE1", - "CLK_HROW_WW4A1_2", - "CLK_BUFG_LOGIC_OUTS_B22_0", - "CLK_BUFG_R_BUFGCTRL3_S0", - "CLK_BUFG_R_CK_FB_TEST1_2", - "CLK_BUFG_R_BUFGCTRL9_S1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_SE4BEG1_0", - "CLK_BUFG_R_BUFGCTRL10_S1", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_WR1END0_0", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NW2A0_2", - "CLK_BUFG_LOGIC_OUTS_B13_2", - "CLK_BUFG_IMUX0_0", - "CLK_BUFG_LOGIC_OUTS_B12_0", - "CLK_HROW_EE4C2_2", - "CLK_BUFG_IMUX38_1", - "CLK_HROW_FAN4_3", - "CLK_HROW_CLK0_0", - "CLK_BUFG_BOT_R_CK_MUXED12", - "CLK_BUFG_IMUX12_2", - "CLK_BUFG_IMUX34_1", - "CLK_BUFG_CK_GCLK28", - "CLK_HROW_WW4END3_1", - "CLK_HROW_BYP0_1", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A0_0", - "CLK_BUFG_IMUX40_1", - "CLK_HROW_BYP3_2", - "CLK_BUFG_IMUX10_0", - "CLK_HROW_EE4B1_0", - "CLK_HROW_NE4C3_3", - "CLK_BUFG_LOGIC_OUTS_B11_1", - "CLK_HROW_NE2A1_3", - "CLK_BUFG_IMUX37_0", - "CLK_BUFG_R_BUFGCTRL9_CE0", - "CLK_BUFG_IMUX29_1", - "CLK_BUFG_BUFGCTRL2_I1", - "CLK_HROW_WW4A0_0", - "CLK_HROW_EL1BEG2_1", - "CLK_BUFG_BUFGCTRL14_I1", - "CLK_HROW_NE2A2_3", - "CLK_BUFG_R_BUFGCTRL9_S0", - "CLK_BUFG_LOGIC_OUTS_B18_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_NW4END3_2", - "CLK_BUFG_R_BUFGCTRL0_CE1", - "CLK_HROW_NE4C1_0", - "CLK_BUFG_R_CK_FB_TEST1_5", - "CLK_BUFG_LOGIC_OUTS_B20_1", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_WW2A0_0", - "CLK_BUFG_IMUX6_0", - "CLK_HROW_SE4BEG1_2", - "CLK_BUFG_LOGIC_OUTS_B19_1", - "CLK_BUFG_R_FBG_OUT10", - "CLK_HROW_BYP7_0", - "CLK_HROW_LH8_1", - "CLK_HROW_NW4END2_3", - "CLK_HROW_ER1BEG0_2", - "CLK_BUFG_BOT_R_CK_MUXED23", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_BYP2_1", - "CLK_HROW_EE2A2_1", - "CLK_HROW_WW2A2_1", - "CLK_BUFG_LOGIC_OUTS_B16_3", - "CLK_BUFG_CK_GCLK30", - "CLK_HROW_NW2A1_2", - "CLK_BUFG_LOGIC_OUTS_B11_2", - "CLK_HROW_WW2A3_0", - "CLK_BUFG_BUFGCTRL7_I1", - "CLK_HROW_ER1BEG1_0", - "CLK_BUFG_LOGIC_OUTS_B1_2", - "CLK_BUFG_IMUX28_1", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_BUFG_IMUX31_0", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_BUFG_IMUX42_1", - "CLK_HROW_LH4_3", - "CLK_HROW_FAN1_2", - "CLK_BUFG_BOT_R_CK_MUXED25", - "CLK_BUFG_IMUX5_0", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_CTRL0_0", - "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "CLK_BUFG_IMUX33_0", - "CLK_HROW_SE2A1_2", - "CLK_BUFG_IMUX35_3", - "CLK_HROW_CTRL1_3", - "CLK_BUFG_BUFGCTRL8_O", - "CLK_HROW_SE2A3_3", - "CLK_BUFG_R_BUFGCTRL3_CE0", - "CLK_BUFG_R_BUFGCTRL4_S1", - "CLK_HROW_EE4B1_1", - "CLK_HROW_LH5_2", - "CLK_BUFG_CK_GCLK29", - "CLK_HROW_NE4BEG1_0", - "CLK_BUFG_BOT_R_CK_MUXED22", - "CLK_BUFG_IMUX42_3", - "CLK_HROW_WW4B2_3", - "CLK_BUFG_LOGIC_OUTS_B10_3", - "CLK_BUFG_R_CK_FB_TEST1_1", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_WW4END3_3", - "CLK_BUFG_BUFGCTRL2_I0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_EE4A0_0", - "CLK_HROW_WW4B0_3", - "CLK_BUFG_IMUX47_2", - "CLK_BUFG_IMUX30_3", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SE2A2_2", - "CLK_BUFG_R_BUFGCTRL5_S1", - "CLK_HROW_FAN1_3", - "CLK_HROW_SW2A1_3", - "CLK_HROW_FAN3_2", - "CLK_BUFG_R_CK_FB_TEST1_3", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_BUFG_IMUX11_2", - "CLK_BUFG_IMUX16_1", - "CLK_HROW_LH8_2", - "CLK_BUFG_IMUX27_3", - "CLK_HROW_NE4BEG1_1", - "CLK_BUFG_R_BUFGCTRL10_S0", - "CLK_HROW_WW2A0_2", - "CLK_BUFG_LOGIC_OUTS_B2_0", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_SW4A2_2", - "CLK_BUFG_BUFGCTRL3_I0", - "CLK_BUFG_R_BUFGCTRL11_S0", - "CLK_HROW_EE4C0_0", - "CLK_BUFG_LOGIC_OUTS_B6_1", - "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_FAN0_1", - "CLK_BUFG_LOGIC_OUTS_B23_3", - "CLK_HROW_EE2A2_0", - "CLK_BUFG_LOGIC_OUTS_B18_0", - "CLK_BUFG_R_FBG_OUT15", - "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "CLK_BUFG_IMUX14_0", - "CLK_BUFG_LOGIC_OUTS_B15_1", - "CLK_BUFG_CK_GCLK11", - "CLK_HROW_NE2A1_0", - "CLK_BUFG_IMUX35_2", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW4B1_1", - "CLK_BUFG_R_BUFGCTRL13_S0", - "CLK_HROW_MONITOR_N_3", - "CLK_BUFG_IMUX35_0", - "CLK_HROW_LH6_2", - "CLK_BUFG_BOT_R_CK_MUXED19", - "CLK_HROW_NW4END1_3", - "CLK_HROW_WR1END1_3", - "CLK_BUFG_LOGIC_OUTS_B12_2", - "CLK_HROW_FAN7_0", - "CLK_HROW_LH4_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_FAN2_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_NW4END0_2", - "CLK_BUFG_LOGIC_OUTS_B21_2", - "CLK_BUFG_R_CK_FB_TEST1_8", - "CLK_HROW_SE2A0_0", - "CLK_HROW_NW4END0_1", - "CLK_BUFG_BOT_R_CK_MUXED26", - "CLK_HROW_NW2A0_1", - "CLK_BUFG_IMUX28_3", - "CLK_HROW_NE4BEG2_3", - "CLK_BUFG_IMUX32_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_NE4C0_0", - "CLK_BUFG_LOGIC_OUTS_B3_1", - "CLK_HROW_NW2A2_0", - "CLK_BUFG_R_CK_FB_TEST1_13", - "CLK_HROW_CLK0_1", - "CLK_HROW_SE2A1_3", - "CLK_HROW_WW2END3_3", - "CLK_HROW_SW4END2_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_EE4C1_0", - "CLK_BUFG_IMUX19_2", - "CLK_BUFG_IMUX20_0", - "CLK_HROW_BYP6_3", - "CLK_HROW_SE4C2_3", - "CLK_BUFG_LOGIC_OUTS_B10_0", - "CLK_BUFG_R_BUFGCTRL1_CE1", - "CLK_BUFG_LOGIC_OUTS_B6_0", - "CLK_BUFG_CK_GCLK22", - "CLK_HROW_WW4C2_1", - "CLK_BUFG_BOT_R_CK_MUXED7", - "CLK_BUFG_LOGIC_OUTS_B12_1", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_NE4BEG3_3", - "CLK_BUFG_BUFGCTRL10_I1", - "CLK_HROW_LH12_2", - "CLK_BUFG_BOT_R_CK_MUXED14", - "CLK_HROW_WW4B2_2", - "CLK_HROW_EE4A0_2", - "CLK_HROW_SE2A3_0", - "CLK_HROW_EE4B2_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_EL1BEG0_3", - "CLK_BUFG_IMUX13_0", - "CLK_BUFG_R_CK_FB_TEST0_11", - "CLK_BUFG_CK_GCLK15", - "CLK_HROW_LH7_3", - "CLK_BUFG_IMUX24_1", - "CLK_HROW_EE4B0_1", - "CLK_HROW_SW2A3_2", - "CLK_BUFG_LOGIC_OUTS_B21_3", - "CLK_BUFG_IMUX21_3", - "CLK_HROW_FAN6_2", - "CLK_BUFG_R_FBG_OUT14", - "CLK_BUFG_LOGIC_OUTS_B14_1", - "CLK_BUFG_LOGIC_OUTS_B7_3", - "CLK_HROW_WW2A3_2", - "CLK_HROW_LH10_1", - "CLK_HROW_BYP6_0", - "CLK_HROW_FAN7_1", - "CLK_BUFG_IMUX3_3", - "CLK_BUFG_IMUX10_2", - "CLK_BUFG_R_BUFGCTRL6_CE1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_WW4A2_1", - "CLK_BUFG_LOGIC_OUTS_B9_2", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP5_3", - "CLK_BUFG_LOGIC_OUTS_B21_1", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_BUFG_CK_GCLK31", - "CLK_HROW_NW4A0_1", - "CLK_HROW_WW2END0_1", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_WW4A3_2", - "CLK_HROW_EE4C1_2", - "CLK_HROW_SE4C0_1", - "CLK_BUFG_BUFGCTRL4_I0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_CLK1_0", - "CLK_HROW_EE4BEG1_2", - "CLK_BUFG_IMUX35_1", - "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "CLK_HROW_NW4END3_0", - "CLK_HROW_EE2BEG1_1", - "CLK_BUFG_IMUX29_0", - "CLK_HROW_SE2A2_3", - "CLK_HROW_NW4A1_0", - "CLK_HROW_WR1END3_2", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE4A2_1", - "CLK_BUFG_LOGIC_OUTS_B17_2", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SW4A0_3", - "CLK_BUFG_IMUX26_0", - "CLK_BUFG_BOT_R_CK_MUXED29", - "CLK_BUFG_R_BUFGCTRL7_CE0", - "CLK_HROW_FAN5_0", - "CLK_BUFG_R_BUFGCTRL8_CE1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_SE2A2_0", - "CLK_BUFG_R_BUFGCTRL4_CE0", - "CLK_BUFG_IMUX8_0", - "CLK_BUFG_R_FBG_OUT3", - "CLK_HROW_WW4C2_0", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_SW4A3_2", - "CLK_HROW_LH7_2", - "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "CLK_BUFG_IMUX2_2", - "CLK_HROW_NW4A3_1", - "CLK_BUFG_LOGIC_OUTS_B21_0", - "CLK_HROW_SE4C1_1", - "CLK_BUFG_LOGIC_OUTS_B15_3", - "CLK_BUFG_LOGIC_OUTS_B8_0", - "CLK_BUFG_R_BUFGCTRL11_CE0", - "CLK_HROW_LH3_1", - "CLK_HROW_SW4A2_3", - "CLK_HROW_NW4A0_3", - "CLK_BUFG_LOGIC_OUTS_B14_2", - "CLK_HROW_BYP4_0", - "CLK_BUFG_LOGIC_OUTS_B14_3", - "CLK_HROW_WW2A0_1", - "CLK_BUFG_IMUX6_3", - "CLK_BUFG_R_BUFGCTRL9_CE1", - "CLK_BUFG_LOGIC_OUTS_B22_1", - "CLK_BUFG_IMUX14_3", - "CLK_HROW_EE2BEG2_1", - "CLK_BUFG_IMUX45_3", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_2", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WL1END3_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_WW4END2_0", - "CLK_HROW_LH7_0", - "CLK_BUFG_IMUX23_2", - "CLK_BUFG_IMUX31_1", - "CLK_HROW_FAN0_0", - "CLK_BUFG_LOGIC_OUTS_B11_0", - "CLK_BUFG_IMUX13_2", - "CLK_HROW_ER1BEG2_0", - "CLK_BUFG_BOT_R_CK_MUXED18", - "CLK_BUFG_IMUX44_2", - "CLK_BUFG_BUFGCTRL3_I1", - "CLK_BUFG_IMUX25_3", - "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "CLK_HROW_SW4A2_0", - "CLK_BUFG_CK_GCLK27", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_BUFG_BUFGCTRL5_I1", - "CLK_BUFG_CK_GCLK20", - "CLK_HROW_EE2BEG3_0", - "CLK_BUFG_IMUX30_2", - "CLK_BUFG_IMUX11_0", - "CLK_BUFG_IMUX25_2", - "CLK_BUFG_BOT_R_CK_MUXED20", - "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "CLK_HROW_SE4C2_0", - "CLK_HROW_WW4A0_3", - "CLK_BUFG_IMUX38_3", - "CLK_BUFG_IMUX21_2", - "CLK_HROW_LH6_1", - "CLK_HROW_EE4B0_2", - "CLK_BUFG_BUFGCTRL0_O", - "CLK_BUFG_IMUX18_2", - "CLK_BUFG_R_CK_FB_TEST0_3", - "CLK_BUFG_BUFGCTRL13_O", - "CLK_HROW_WW4C3_0", - "CLK_BUFG_BUFGCTRL12_O", - "CLK_HROW_BYP7_1", - "CLK_BUFG_R_BUFGCTRL12_S1", - "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "CLK_HROW_CTRL1_0", - "CLK_BUFG_LOGIC_OUTS_B16_2", - "CLK_BUFG_R_CK_FB_TEST1_6", - "CLK_HROW_EL1BEG0_0", - "CLK_BUFG_IMUX19_0", - "CLK_BUFG_R_BUFGCTRL0_S0", - "CLK_HROW_EE2A0_0", - "CLK_HROW_WL1END2_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_FAN7_2", - "CLK_BUFG_IMUX20_3", - "CLK_BUFG_LOGIC_OUTS_B11_3", - "CLK_HROW_WR1END1_2", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_WR1END3_1", - "CLK_BUFG_LOGIC_OUTS_B10_1", - "CLK_HROW_SE4C1_2", - "CLK_BUFG_LOGIC_OUTS_B3_3", - "CLK_BUFG_R_BUFGCTRL8_CE0", - "CLK_HROW_WW2A2_0", - "CLK_BUFG_IMUX18_1", - "CLK_HROW_NE4C1_3", - "CLK_HROW_EE4C2_3", - "CLK_BUFG_IMUX1_2", - "CLK_HROW_CTRL0_2", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE2BEG3_1", - "CLK_BUFG_IMUX32_2", - "CLK_HROW_LH2_3", - "CLK_HROW_LH10_0", - "CLK_BUFG_BOT_R_CK_MUXED3", - "CLK_BUFG_IMUX31_2", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_EE2A0_3", - "CLK_BUFG_LOGIC_OUTS_B22_3", - "CLK_BUFG_R_CK_FB_TEST1_9", - "CLK_BUFG_IMUX43_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_NW4END2_0", - "CLK_BUFG_LOGIC_OUTS_B6_3", - "CLK_BUFG_BUFGCTRL4_I1", - "CLK_BUFG_IMUX11_1", - "CLK_BUFG_BOT_R_CK_MUXED8", - "CLK_BUFG_IMUX44_0", - "CLK_BUFG_CK_GCLK6", - "CLK_HROW_EE4C1_3", - "CLK_HROW_NE4C2_1", - "CLK_HROW_EE4C0_1", - "CLK_BUFG_CK_GCLK18", - "CLK_HROW_WR1END0_1", - "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "CLK_HROW_BYP0_3", - "CLK_HROW_NW4END1_2", - "CLK_BUFG_IMUX17_3", - "CLK_BUFG_BUFGCTRL1_I1", - "CLK_HROW_EE2A1_3", - "CLK_HROW_SW2A2_2", - "CLK_BUFG_IMUX0_1", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_WW2END0_0", - "CLK_BUFG_IMUX3_2", - "CLK_BUFG_R_FBG_OUT13", - "CLK_BUFG_R_FBG_OUT12", - "CLK_HROW_EE2A3_0", - "CLK_BUFG_R_CK_FB_TEST0_4", - "CLK_BUFG_IMUX13_3", - "CLK_HROW_SE2A2_1", - "CLK_BUFG_IMUX13_1", - "CLK_HROW_SW2A2_0", - "CLK_HROW_WW4A2_2", - "CLK_HROW_LH3_3", - "CLK_HROW_CTRL1_2", - "CLK_BUFG_IMUX17_2", - "CLK_HROW_WW2A2_3", - "CLK_BUFG_IMUX24_0", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4BEG0_3", - "CLK_BUFG_R_BUFGCTRL2_CE0", - "CLK_BUFG_R_BUFGCTRL14_CE0", - "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "CLK_BUFG_LOGIC_OUTS_B22_2", - "CLK_HROW_NE2A3_2", - "CLK_HROW_WW4B0_2", - "CLK_HROW_BYP1_2", - "CLK_HROW_LH11_2", - "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "CLK_HROW_EE4BEG3_2", - "CLK_BUFG_IMUX38_2", - "CLK_HROW_WW2END2_1", - "CLK_HROW_SE4C3_0", - "CLK_BUFG_R_BUFGCTRL15_CE0", - "CLK_HROW_NW2A3_2", - "CLK_BUFG_IMUX45_1", - "CLK_HROW_NW4A2_3", - "CLK_BUFG_IMUX15_2", - "CLK_HROW_NW4A0_0", - "CLK_BUFG_IMUX26_1", - "CLK_HROW_SE2A0_1", - "CLK_BUFG_LOGIC_OUTS_B6_2", - "CLK_HROW_EE2BEG0_1", - "CLK_BUFG_IMUX24_2", - "CLK_BUFG_BUFGCTRL1_O", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4C0_3", - "CLK_HROW_FAN5_3", - "CLK_BUFG_LOGIC_OUTS_B5_3", - "CLK_BUFG_LOGIC_OUTS_B13_0", - "CLK_BUFG_IMUX23_0", - "CLK_BUFG_BUFGCTRL3_O", - "CLK_HROW_SW4A2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_1", - "CLK_HROW_SW2A3_1", - "CLK_HROW_LH8_3", - "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "CLK_HROW_LH9_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_EE2A1_2", - "CLK_HROW_LH2_2", - "CLK_HROW_SW4END1_2", - "CLK_BUFG_IMUX24_3", - "CLK_HROW_SE4C0_0", - "CLK_BUFG_R_BUFGCTRL12_CE1", - "CLK_HROW_WW2END1_0", - "CLK_BUFG_R_FBG_OUT9", - "CLK_HROW_EE4B2_1", - "CLK_HROW_WW2END0_2", - "CLK_BUFG_R_BUFGCTRL11_CE1", - "CLK_BUFG_R_FBG_OUT5", - "CLK_HROW_WR1END2_2", - "CLK_HROW_EE4A2_0", - "CLK_BUFG_LOGIC_OUTS_B4_0", - "CLK_BUFG_IMUX12_0", - "CLK_BUFG_IMUX38_0", - "CLK_BUFG_R_CK_FB_TEST1_12", - "CLK_BUFG_IMUX43_0", - "CLK_BUFG_LOGIC_OUTS_B4_3", - "CLK_HROW_NW4END0_3", - "CLK_HROW_LH10_2", - "CLK_BUFG_R_BUFGCTRL10_CE1", - "CLK_HROW_SE4C0_2", - "CLK_BUFG_R_CK_FB_TEST1_0", - "CLK_HROW_WW4A3_0", - "CLK_BUFG_BOT_R_CK_MUXED28", - "CLK_BUFG_LOGIC_OUTS_B9_3", - "CLK_BUFG_IMUX20_1", - "CLK_BUFG_IMUX42_2", - "CLK_BUFG_R_CK_FB_TEST0_7", - "CLK_BUFG_R_CK_FB_TEST1_10", - "CLK_HROW_WW2END0_3", - "CLK_BUFG_IMUX37_1", - "CLK_HROW_WR1END2_1", - "CLK_BUFG_BOT_R_CK_MUXED2", - "CLK_HROW_EE4C3_2", - "CLK_BUFG_IMUX17_0", - "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "CLK_BUFG_R_BUFGCTRL11_S1", - "CLK_HROW_NE4BEG2_2", - "CLK_BUFG_LOGIC_OUTS_B19_3", - "CLK_BUFG_LOGIC_OUTS_B17_1", - "CLK_HROW_WW4A0_2", - "CLK_BUFG_R_BUFGCTRL15_S1", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_FAN3_3", - "CLK_BUFG_R_BUFGCTRL1_S1", - "CLK_BUFG_IMUX5_2", - "CLK_BUFG_CK_GCLK24", - "CLK_HROW_EE4B0_0", - "CLK_BUFG_IMUX10_1", - "CLK_BUFG_BUFGCTRL5_O", - "CLK_HROW_MONITOR_N_0", - "CLK_BUFG_IMUX31_3", - "CLK_HROW_LH12_0", - "CLK_BUFG_IMUX39_2", - "CLK_BUFG_CK_GCLK13", - "CLK_BUFG_LOGIC_OUTS_B20_3", - "CLK_BUFG_IMUX7_1", - "CLK_HROW_WL1END3_0", - "CLK_BUFG_BOT_R_CK_MUXED24", - "CLK_HROW_WW4A3_3", - "CLK_BUFG_R_CK_FB_TEST0_10", - "CLK_HROW_SE4C1_3", - "CLK_BUFG_BOT_R_CK_MUXED15", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_NW4A2_0", - "CLK_BUFG_BUFGCTRL6_I0", - "CLK_HROW_SW4END0_0", - "CLK_HROW_LH2_0", - "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "CLK_HROW_NW4A3_3", - "CLK_HROW_EE4C2_0", - "CLK_HROW_SE2A1_0", - "CLK_HROW_WL1END1_0", - "CLK_BUFG_R_CK_FB_TEST0_2", - "CLK_BUFG_LOGIC_OUTS_B8_3", - "CLK_BUFG_BOT_R_CK_MUXED27", - "CLK_BUFG_IMUX17_1", - "CLK_BUFG_IMUX22_2", - "CLK_HROW_SE4C3_1", - "CLK_HROW_FAN1_0" - ], - "sites": [ - { - "prefix": "BUFGCTRL", - "y_coord": 0, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", - "O": "CLK_BUFG_BUFGCTRL0_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL0_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL0_S1", - "I1": "CLK_BUFG_BUFGCTRL0_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", - "I0": "CLK_BUFG_BUFGCTRL0_I0" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 1, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", - "O": "CLK_BUFG_BUFGCTRL1_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL1_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL1_S1", - "I1": "CLK_BUFG_BUFGCTRL1_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", - "I0": "CLK_BUFG_BUFGCTRL1_I0" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 2, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", - "O": "CLK_BUFG_BUFGCTRL2_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL2_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL2_S1", - "I1": "CLK_BUFG_BUFGCTRL2_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", - "I0": "CLK_BUFG_BUFGCTRL2_I0" - }, - "x_coord": 0, - "name": "X0Y2" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 3, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", - "O": "CLK_BUFG_BUFGCTRL3_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL3_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL3_S1", - "I1": "CLK_BUFG_BUFGCTRL3_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", - "I0": "CLK_BUFG_BUFGCTRL3_I0" - }, - "x_coord": 0, - "name": "X0Y3" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 4, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", - "O": "CLK_BUFG_BUFGCTRL4_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL4_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL4_S1", - "I1": "CLK_BUFG_BUFGCTRL4_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", - "I0": "CLK_BUFG_BUFGCTRL4_I0" - }, - "x_coord": 0, - "name": "X0Y4" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 5, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", - "O": "CLK_BUFG_BUFGCTRL5_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL5_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL5_S1", - "I1": "CLK_BUFG_BUFGCTRL5_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", - "I0": "CLK_BUFG_BUFGCTRL5_I0" - }, - "x_coord": 0, - "name": "X0Y5" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 6, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", - "O": "CLK_BUFG_BUFGCTRL6_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL6_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL6_S1", - "I1": "CLK_BUFG_BUFGCTRL6_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", - "I0": "CLK_BUFG_BUFGCTRL6_I0" - }, - "x_coord": 0, - "name": "X0Y6" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 7, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", - "O": "CLK_BUFG_BUFGCTRL7_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL7_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL7_S1", - "I1": "CLK_BUFG_BUFGCTRL7_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", - "I0": "CLK_BUFG_BUFGCTRL7_I0" - }, - "x_coord": 0, - "name": "X0Y7" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 8, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", - "O": "CLK_BUFG_BUFGCTRL8_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL8_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL8_S1", - "I1": "CLK_BUFG_BUFGCTRL8_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", - "I0": "CLK_BUFG_BUFGCTRL8_I0" - }, - "x_coord": 0, - "name": "X0Y8" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 9, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", - "O": "CLK_BUFG_BUFGCTRL9_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL9_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL9_S1", - "I1": "CLK_BUFG_BUFGCTRL9_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", - "I0": "CLK_BUFG_BUFGCTRL9_I0" - }, - "x_coord": 0, - "name": "X0Y9" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 10, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", - "O": "CLK_BUFG_BUFGCTRL10_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL10_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL10_S1", - "I1": "CLK_BUFG_BUFGCTRL10_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", - "I0": "CLK_BUFG_BUFGCTRL10_I0" - }, - "x_coord": 0, - "name": "X0Y10" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 11, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", - "O": "CLK_BUFG_BUFGCTRL11_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL11_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL11_S1", - "I1": "CLK_BUFG_BUFGCTRL11_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", - "I0": "CLK_BUFG_BUFGCTRL11_I0" - }, - "x_coord": 0, - "name": "X0Y11" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 12, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", - "O": "CLK_BUFG_BUFGCTRL12_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL12_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL12_S1", - "I1": "CLK_BUFG_BUFGCTRL12_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", - "I0": "CLK_BUFG_BUFGCTRL12_I0" - }, - "x_coord": 0, - "name": "X0Y12" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 13, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", - "O": "CLK_BUFG_BUFGCTRL13_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL13_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL13_S1", - "I1": "CLK_BUFG_BUFGCTRL13_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", - "I0": "CLK_BUFG_BUFGCTRL13_I0" - }, - "x_coord": 0, - "name": "X0Y13" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 14, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", - "O": "CLK_BUFG_BUFGCTRL14_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL14_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL14_S1", - "I1": "CLK_BUFG_BUFGCTRL14_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", - "I0": "CLK_BUFG_BUFGCTRL14_I0" - }, - "x_coord": 0, - "name": "X0Y14" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 15, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", - "O": "CLK_BUFG_BUFGCTRL15_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL15_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL15_S1", - "I1": "CLK_BUFG_BUFGCTRL15_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", - "I0": "CLK_BUFG_BUFGCTRL15_I0" - }, - "x_coord": 0, - "name": "X0Y15" - } - ], "pips": { - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0", + "src_wire": "CLK_BUFG_R_FBG_OUT10", "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX21_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX5_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT11", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX7_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX10_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_0->>CLK_BUFG_R_BUFGCTRL3_S1": { "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1", - "is_directional": "1", "src_wire": "CLK_BUFG_IMUX3_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX15_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT7", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT13", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL13_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX12_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED25", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX4_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX11_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX0_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT4", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT8", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX10_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX13_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED9", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX9_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT5", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT12", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK12": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK12", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL12_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT9", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX0_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT14", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL14_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX8_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX19_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX11_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT8", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX1_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT12", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX7_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX14_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX6_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL1_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT10", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX14_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX6_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX6_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED21", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED16", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED28", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT11", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX0_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX10_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK5": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK5", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL5_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX18_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX13_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT14", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT15", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX17_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX15_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED7", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT7", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX11_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX4_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX22_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT4", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX23_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX2_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL1_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX19_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT6", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT10", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK11": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK11", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL11_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK14": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK14", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL14_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX19_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX9_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED24", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX10_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX5_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED18", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT11", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT10", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX13_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX9_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK2": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK2", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL2_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX17_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX17_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX21_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX15_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED4", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX2_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX1_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX3_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX18_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT7", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX15_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK13": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK13", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL13_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK10": { "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK10", - "is_directional": "1", "src_wire": "CLK_BUFG_BUFGCTRL10_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED14", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX23_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX6_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED19", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT3", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL3_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED8", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED17", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL0_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX9_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED31", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT4", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT7", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX16_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT9", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX1_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT8", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX20_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX23_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX13_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX16_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT9", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED22", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX8_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX16_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK9": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK9", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL9_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK4": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK4", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL4_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED30", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX23_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK6": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK6", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL6_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT4", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX5_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX20_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED23", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED29", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT15", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT15", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL0_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT6", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX3_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX1_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX20_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT14", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX8_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED26", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT12", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED20", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT5", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL5_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX19_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX17_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX22_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT10", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX11_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX4_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX2_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX18_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT12", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT9", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX12_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED27", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT14", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX8_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED15", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX16_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK8": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK8", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL8_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT11", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL11_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT6", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL6_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED12", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT13", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX0_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT7", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL7_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED6", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT4", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL4_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX5_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT5", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX22_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT6", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT12", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL12_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX21_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX2_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT13", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK7": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK7", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL7_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT6", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX21_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT15", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX7_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT13", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT8", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL8_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX14_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED11", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED13", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX20_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_2", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT11", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT13", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT5", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT5", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT14", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT15", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL15_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT10", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL10_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED5", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK15": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK15", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL15_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX3_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT8", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX18_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX22_1", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT2", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL2_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX14_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK3": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK3", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL3_O", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX12_0", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BOT_R_CK_MUXED10", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX7_3", - "is_pseudo": "0" - }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0", "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX4_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK10" }, - "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "src_wire": "CLK_BUFG_IMUX9_2", "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX12_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT9", - "is_directional": "1", "src_wire": "CLK_BUFG_BUFGCTRL9_O", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT9" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT3" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK15": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK15" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL14_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT14" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX22_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK11": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK11" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL2_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL3_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX8_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL12_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX23_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX18_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX12_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL5_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL6_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK7": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK7" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL4_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK4": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK4" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT5" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT15" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL14_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL13_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX17_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT11" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK12": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK12" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX23_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL8_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL10_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT10" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL15_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL11_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK3": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK3" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX11_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX14_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK8": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK8" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX9_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX19_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX17_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT6" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL7_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX18_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL10_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX20_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT2" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK6": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK6" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT8" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX19_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL9_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX11_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK13": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK13" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX13_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX17_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX18_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX10_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT12" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX11_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX15_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL1_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK2": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK2" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX13_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX14_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT13" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL0_O" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK9": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL9_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK9" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK5": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK5" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX21_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK14": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL14_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK14" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT7" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX18_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT4" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX16_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX23_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BOT_R_CK_MUXED20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" } }, - "tile_type": "CLK_BUFG_BOT_R" + "wires": [ + "CLK_HROW_SW4END1_2", + "CLK_BUFG_LOGIC_OUTS_B21_2", + "CLK_BUFG_IMUX20_1", + "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "CLK_HROW_WW2END3_2", + "CLK_BUFG_R_BUFGCTRL5_S1", + "CLK_BUFG_IMUX12_0", + "CLK_BUFG_IMUX24_1", + "CLK_HROW_SE4C2_1", + "CLK_HROW_BYP4_0", + "CLK_BUFG_IMUX12_1", + "CLK_BUFG_R_FBG_OUT13", + "CLK_HROW_WW4END1_1", + "CLK_HROW_BYP1_0", + "CLK_BUFG_R_FBG_OUT7", + "CLK_HROW_FAN2_2", + "CLK_BUFG_IMUX11_0", + "CLK_BUFG_BOT_R_CK_MUXED6", + "CLK_BUFG_R_CK_FB_TEST1_0", + "CLK_BUFG_R_CK_FB_TEST0_12", + "CLK_HROW_EL1BEG0_0", + "CLK_HROW_SW2A1_2", + "CLK_BUFG_IMUX15_3", + "CLK_HROW_NW2A1_3", + "CLK_BUFG_IMUX46_1", + "CLK_HROW_NW2A3_1", + "CLK_HROW_EE2BEG2_3", + "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "CLK_HROW_WW4C1_0", + "CLK_HROW_SW4A2_1", + "CLK_BUFG_IMUX15_1", + "CLK_HROW_LH1_0", + "CLK_HROW_WW4B0_2", + "CLK_HROW_WW4C2_0", + "CLK_BUFG_LOGIC_OUTS_B14_2", + "CLK_BUFG_IMUX46_2", + "CLK_BUFG_R_BUFGCTRL4_CE1", + "CLK_HROW_BYP7_2", + "CLK_HROW_BYP2_2", + "CLK_HROW_CLK1_3", + "CLK_HROW_WW4C0_2", + "CLK_HROW_EE2A3_1", + "CLK_HROW_WW2A0_0", + "CLK_HROW_SE2A0_1", + "CLK_HROW_WW4C2_2", + "CLK_BUFG_LOGIC_OUTS_B2_3", + "CLK_HROW_SE4C0_1", + "CLK_HROW_SW4A1_1", + "CLK_BUFG_LOGIC_OUTS_B16_1", + "CLK_BUFG_IMUX35_2", + "CLK_HROW_BYP5_1", + "CLK_BUFG_CK_GCLK27", + "CLK_HROW_WW4C3_2", + "CLK_BUFG_BUFGCTRL11_O", + "CLK_BUFG_R_BUFGCTRL1_CE1", + "CLK_BUFG_R_BUFGCTRL1_CE0", + "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "CLK_BUFG_CK_GCLK1", + "CLK_BUFG_LOGIC_OUTS_B4_1", + "CLK_HROW_WR1END3_2", + "CLK_BUFG_LOGIC_OUTS_B21_1", + "CLK_BUFG_BUFGCTRL7_I0", + "CLK_BUFG_R_BUFGCTRL1_S1", + "CLK_BUFG_CK_GCLK15", + "CLK_HROW_WW2END2_0", + "CLK_BUFG_IMUX7_1", + "CLK_BUFG_LOGIC_OUTS_B6_3", + "CLK_BUFG_BOT_R_CK_MUXED14", + "CLK_BUFG_IMUX20_0", + "CLK_HROW_FAN2_0", + "CLK_HROW_NW4A3_0", + "CLK_HROW_WL1END0_0", + "CLK_BUFG_LOGIC_OUTS_B22_0", + "CLK_HROW_EE4A0_1", + "CLK_BUFG_IMUX3_2", + "CLK_HROW_SW2A2_2", + "CLK_BUFG_R_BUFGCTRL12_CE0", + "CLK_BUFG_IMUX15_0", + "CLK_BUFG_R_BUFGCTRL4_CE0", + "CLK_BUFG_R_BUFGCTRL4_S0", + "CLK_HROW_BYP6_0", + "CLK_HROW_EE4A3_0", + "CLK_BUFG_IMUX23_1", + "CLK_HROW_WW4END3_0", + "CLK_BUFG_BUFGCTRL10_I1", + "CLK_BUFG_LOGIC_OUTS_B12_1", + "CLK_HROW_NW4END0_0", + "CLK_BUFG_IMUX7_2", + "CLK_BUFG_BOT_R_CK_MUXED23", + "CLK_BUFG_IMUX18_0", + "CLK_BUFG_IMUX9_0", + "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "CLK_HROW_BYP5_0", + "CLK_BUFG_IMUX46_0", + "CLK_BUFG_R_FBG_OUT2", + "CLK_BUFG_BUFGCTRL12_I0", + "CLK_HROW_FAN4_1", + "CLK_HROW_LH7_2", + "CLK_BUFG_IMUX37_0", + "CLK_BUFG_R_BUFGCTRL15_CE0", + "CLK_BUFG_LOGIC_OUTS_B9_1", + "CLK_BUFG_CK_GCLK7", + "CLK_HROW_ER1BEG3_0", + "CLK_BUFG_R_BUFGCTRL6_CE1", + "CLK_HROW_WW4END1_3", + "CLK_HROW_NW4A0_3", + "CLK_BUFG_R_BUFGCTRL9_S1", + "CLK_HROW_LH3_1", + "CLK_BUFG_CK_GCLK22", + "CLK_HROW_SW2A1_1", + "CLK_BUFG_R_BUFGCTRL8_CE0", + "CLK_BUFG_LOGIC_OUTS_B8_2", + "CLK_BUFG_IMUX30_2", + "CLK_HROW_LH10_2", + "CLK_HROW_CTRL1_3", + "CLK_BUFG_IMUX43_0", + "CLK_HROW_NW4END1_1", + "CLK_HROW_WW4C2_3", + "CLK_BUFG_IMUX34_0", + "CLK_HROW_WW2END0_0", + "CLK_HROW_ER1BEG2_1", + "CLK_HROW_SE4BEG0_3", + "CLK_BUFG_IMUX6_3", + "CLK_BUFG_R_BUFGCTRL6_S1", + "CLK_HROW_LH2_1", + "CLK_HROW_LH4_0", + "CLK_HROW_EE4B2_1", + "CLK_BUFG_R_BUFGCTRL13_S1", + "CLK_BUFG_CK_GCLK9", + "CLK_BUFG_IMUX31_0", + "CLK_HROW_MONITOR_N_3", + "CLK_HROW_NW2A3_2", + "CLK_HROW_MONITOR_P_3", + "CLK_BUFG_IMUX3_0", + "CLK_HROW_NE4C0_0", + "CLK_HROW_LH1_1", + "CLK_BUFG_BOT_R_CK_MUXED20", + "CLK_HROW_MONITOR_P_1", + "CLK_BUFG_LOGIC_OUTS_B15_0", + "CLK_BUFG_R_BUFGCTRL15_S0", + "CLK_HROW_EE4BEG3_2", + "CLK_BUFG_R_FBG_OUT14", + "CLK_BUFG_IMUX28_0", + "CLK_BUFG_BOT_R_CK_MUXED26", + "CLK_HROW_WL1END3_3", + "CLK_BUFG_LOGIC_OUTS_B9_2", + "CLK_HROW_NW4END3_2", + "CLK_BUFG_LOGIC_OUTS_B4_0", + "CLK_HROW_EE4BEG3_3", + "CLK_HROW_WR1END3_0", + "CLK_BUFG_LOGIC_OUTS_B23_2", + "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "CLK_BUFG_IMUX39_3", + "CLK_HROW_EL1BEG3_3", + "CLK_BUFG_IMUX14_1", + "CLK_HROW_EE4A0_3", + "CLK_BUFG_LOGIC_OUTS_B13_1", + "CLK_BUFG_BOT_R_CK_MUXED29", + "CLK_BUFG_LOGIC_OUTS_B3_0", + "CLK_BUFG_CK_GCLK6", + "CLK_HROW_WW4END1_0", + "CLK_BUFG_BOT_R_CK_MUXED24", + "CLK_HROW_BLOCK_OUTS_B1_0", + "CLK_BUFG_IMUX10_1", + "CLK_HROW_FAN0_3", + "CLK_BUFG_R_BUFGCTRL12_CE1", + "CLK_HROW_BLOCK_OUTS_B2_1", + "CLK_BUFG_IMUX13_3", + "CLK_HROW_SW4A3_2", + "CLK_BUFG_IMUX25_1", + "CLK_HROW_SW4A2_2", + "CLK_HROW_SE4C2_0", + "CLK_BUFG_IMUX16_2", + "CLK_HROW_EE2A0_2", + "CLK_BUFG_BOT_R_CK_MUXED31", + "CLK_BUFG_LOGIC_OUTS_B10_1", + "CLK_HROW_BLOCK_OUTS_B3_1", + "CLK_BUFG_R_CK_FB_TEST1_4", + "CLK_HROW_SE4BEG2_3", + "CLK_BUFG_R_BUFGCTRL5_CE1", + "CLK_HROW_LH8_2", + "CLK_HROW_EE2A1_0", + "CLK_HROW_WW4END3_3", + "CLK_HROW_SW4END0_2", + "CLK_HROW_WW4A1_1", + "CLK_BUFG_IMUX12_2", + "CLK_HROW_NW2A2_1", + "CLK_HROW_NE4C0_3", + "CLK_HROW_BYP7_0", + "CLK_HROW_EL1BEG3_2", + "CLK_BUFG_LOGIC_OUTS_B6_2", + "CLK_HROW_CTRL0_3", + "CLK_HROW_EE4B3_3", + "CLK_BUFG_BOT_R_CK_MUXED8", + "CLK_BUFG_IMUX35_0", + "CLK_BUFG_R_BUFGCTRL0_CE1", + "CLK_HROW_SW4END2_2", + "CLK_HROW_BYP1_2", + "CLK_HROW_BYP2_0", + "CLK_HROW_EE2BEG2_0", + "CLK_HROW_WW4C1_1", + "CLK_BUFG_R_CK_FB_TEST0_0", + "CLK_HROW_NW2A1_1", + "CLK_BUFG_BOT_R_CK_MUXED10", + "CLK_BUFG_IMUX41_2", + "CLK_HROW_FAN1_0", + "CLK_HROW_BYP4_1", + "CLK_BUFG_R_BUFGCTRL13_CE1", + "CLK_HROW_CLK0_3", + "CLK_BUFG_R_BUFGCTRL3_S0", + "CLK_HROW_LH10_3", + "CLK_BUFG_LOGIC_OUTS_B8_3", + "CLK_BUFG_IMUX4_2", + "CLK_BUFG_IMUX24_0", + "CLK_HROW_NE4C2_3", + "CLK_HROW_WW4B0_1", + "CLK_HROW_BLOCK_OUTS_B2_2", + "CLK_BUFG_BOT_R_CK_MUXED3", + "CLK_BUFG_LOGIC_OUTS_B5_1", + "CLK_BUFG_R_BUFGCTRL10_S1", + "CLK_BUFG_CK_GCLK23", + "CLK_BUFG_IMUX25_0", + "CLK_HROW_EE2BEG0_2", + "CLK_BUFG_R_FBG_OUT5", + "CLK_BUFG_IMUX4_3", + "CLK_BUFG_IMUX31_3", + "CLK_BUFG_BOT_R_CK_MUXED13", + "CLK_HROW_CLK1_2", + "CLK_BUFG_BOT_R_CK_MUXED17", + "CLK_HROW_WR1END2_0", + "CLK_BUFG_IMUX43_3", + "CLK_BUFG_LOGIC_OUTS_B4_2", + "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "CLK_HROW_LH2_2", + "CLK_HROW_SW2A0_0", + "CLK_BUFG_BUFGCTRL1_O", + "CLK_BUFG_IMUX17_2", + "CLK_HROW_WW4END3_2", + "CLK_HROW_WW4B2_1", + "CLK_HROW_SE4C2_2", + "CLK_HROW_SW4END3_3", + "CLK_HROW_SE4BEG1_2", + "CLK_BUFG_IMUX16_3", + "CLK_HROW_WW4END0_3", + "CLK_BUFG_IMUX26_3", + "CLK_HROW_NE4BEG0_3", + "CLK_HROW_WW4C1_2", + "CLK_HROW_ER1BEG3_3", + "CLK_BUFG_CK_GCLK16", + "CLK_HROW_NE2A2_1", + "CLK_BUFG_IMUX5_3", + "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "CLK_BUFG_BUFGCTRL13_I0", + "CLK_BUFG_R_CK_FB_TEST1_7", + "CLK_HROW_WW4A3_0", + "CLK_HROW_BYP6_1", + "CLK_BUFG_IMUX38_3", + "CLK_HROW_WW2A3_2", + "CLK_HROW_WR1END3_3", + "CLK_BUFG_IMUX40_0", + "CLK_BUFG_LOGIC_OUTS_B23_0", + "CLK_HROW_SE4C0_3", + "CLK_BUFG_BUFGCTRL9_I1", + "CLK_HROW_WW4B1_1", + "CLK_BUFG_BUFGCTRL14_I0", + "CLK_BUFG_LOGIC_OUTS_B21_3", + "CLK_BUFG_LOGIC_OUTS_B0_1", + "CLK_BUFG_IMUX8_0", + "CLK_BUFG_IMUX17_0", + "CLK_HROW_EE4BEG1_0", + "CLK_BUFG_LOGIC_OUTS_B16_3", + "CLK_BUFG_R_BUFGCTRL2_S1", + "CLK_BUFG_LOGIC_OUTS_B17_3", + "CLK_BUFG_IMUX6_2", + "CLK_BUFG_BOT_R_CK_MUXED30", + "CLK_HROW_EE4B0_3", + "CLK_HROW_CTRL1_0", + "CLK_HROW_NW4A3_1", + "CLK_BUFG_IMUX26_0", + "CLK_BUFG_BUFGCTRL15_I1", + "CLK_HROW_WW2END1_0", + "CLK_HROW_NW4END2_3", + "CLK_HROW_NE2A2_0", + "CLK_BUFG_IMUX41_3", + "CLK_HROW_SE4C3_3", + "CLK_HROW_NW2A2_2", + "CLK_HROW_BLOCK_OUTS_B3_0", + "CLK_HROW_SE2A1_2", + "CLK_HROW_FAN4_2", + "CLK_HROW_WL1END1_1", + "CLK_BUFG_LOGIC_OUTS_B10_0", + "CLK_HROW_CLK0_1", + "CLK_BUFG_R_BUFGCTRL2_S0", + "CLK_HROW_SE4BEG2_0", + "CLK_BUFG_IMUX11_2", + "CLK_BUFG_IMUX22_0", + "CLK_HROW_NE4C2_2", + "CLK_HROW_FAN3_2", + "CLK_BUFG_LOGIC_OUTS_B11_0", + "CLK_HROW_EE4C2_0", + "CLK_BUFG_IMUX22_3", + "CLK_HROW_SE4BEG3_3", + "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "CLK_HROW_NW2A0_1", + "CLK_BUFG_LOGIC_OUTS_B17_1", + "CLK_BUFG_IMUX35_3", + "CLK_HROW_NE4BEG3_3", + "CLK_BUFG_BUFGCTRL13_I1", + "CLK_BUFG_IMUX5_2", + "CLK_HROW_WL1END2_0", + "CLK_HROW_NW4A0_1", + "CLK_HROW_EE4B2_0", + "CLK_HROW_WW4B1_0", + "CLK_HROW_EE4BEG0_2", + "CLK_HROW_EE4A2_2", + "CLK_HROW_FAN5_1", + "CLK_BUFG_LOGIC_OUTS_B7_2", + "CLK_BUFG_LOGIC_OUTS_B2_2", + "CLK_BUFG_R_BUFGCTRL3_S1", + "CLK_HROW_WL1END1_0", + "CLK_HROW_WW4B3_0", + "CLK_HROW_LH9_1", + "CLK_BUFG_BUFGCTRL11_I0", + "CLK_HROW_EE2A0_1", + "CLK_BUFG_BUFGCTRL5_I1", + "CLK_HROW_NW4END1_3", + "CLK_HROW_BYP0_0", + "CLK_HROW_WW4A1_0", + "CLK_HROW_WW2A2_2", + "CLK_HROW_LH2_0", + "CLK_BUFG_LOGIC_OUTS_B18_1", + "CLK_BUFG_IMUX0_1", + "CLK_HROW_WW4A3_1", + "CLK_HROW_NW2A2_3", + "CLK_HROW_FAN7_3", + "CLK_BUFG_LOGIC_OUTS_B18_0", + "CLK_HROW_NE2A0_0", + "CLK_HROW_EE4A2_3", + "CLK_BUFG_IMUX10_3", + "CLK_HROW_FAN7_2", + "CLK_BUFG_IMUX5_1", + "CLK_HROW_FAN0_1", + "CLK_BUFG_LOGIC_OUTS_B1_3", + "CLK_HROW_SE2A1_3", + "CLK_BUFG_LOGIC_OUTS_B13_3", + "CLK_HROW_WW4END0_1", + "CLK_BUFG_R_BUFGCTRL10_CE0", + "CLK_BUFG_IMUX9_2", + "CLK_HROW_LH5_2", + "CLK_HROW_WW2END3_3", + "CLK_HROW_EL1BEG0_1", + "CLK_HROW_SW2A1_0", + "CLK_HROW_WL1END3_2", + "CLK_HROW_SE4BEG3_1", + "CLK_BUFG_IMUX44_0", + "CLK_BUFG_R_BUFGCTRL8_CE1", + "CLK_HROW_NW2A0_2", + "CLK_BUFG_CK_GCLK5", + "CLK_HROW_NW4A1_3", + "CLK_BUFG_IMUX23_3", + "CLK_HROW_NE2A3_1", + "CLK_HROW_BYP2_1", + "CLK_BUFG_IMUX21_2", + "CLK_HROW_NW4A1_1", + "CLK_HROW_WW2END1_3", + "CLK_HROW_WL1END2_1", + "CLK_BUFG_R_BUFGCTRL6_CE0", + "CLK_HROW_WW2END2_2", + "CLK_BUFG_R_FBG_OUT0", + "CLK_BUFG_R_CK_FB_TEST0_4", + "CLK_BUFG_IMUX3_1", + "CLK_HROW_WW4B1_3", + "CLK_BUFG_LOGIC_OUTS_B7_3", + "CLK_BUFG_LOGIC_OUTS_B1_2", + "CLK_HROW_SE2A1_1", + "CLK_BUFG_IMUX8_3", + "CLK_HROW_EL1BEG1_2", + "CLK_BUFG_IMUX29_0", + "CLK_HROW_WW4C0_3", + "CLK_HROW_EL1BEG0_3", + "CLK_BUFG_BUFGCTRL9_I0", + "CLK_BUFG_LOGIC_OUTS_B9_0", + "CLK_HROW_EE4B1_2", + "CLK_BUFG_R_BUFGCTRL15_S1", + "CLK_HROW_BLOCK_OUTS_B0_2", + "CLK_BUFG_BUFGCTRL7_O", + "CLK_BUFG_IMUX3_3", + "CLK_HROW_EE2A3_0", + "CLK_BUFG_BUFGCTRL1_I0", + "CLK_HROW_NE2A0_3", + "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "CLK_HROW_CLK1_0", + "CLK_HROW_LH4_2", + "CLK_BUFG_LOGIC_OUTS_B8_1", + "CLK_HROW_WR1END2_3", + "CLK_HROW_WW4B0_0", + "CLK_BUFG_BUFGCTRL11_I1", + "CLK_HROW_CTRL0_1", + "CLK_BUFG_CK_GCLK0", + "CLK_BUFG_R_BUFGCTRL12_S1", + "CLK_BUFG_R_FBG_OUT1", + "CLK_BUFG_BUFGCTRL15_O", + "CLK_BUFG_IMUX47_0", + "CLK_HROW_SW4A1_0", + "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "CLK_BUFG_R_BUFGCTRL15_CE1", + "CLK_HROW_BYP3_1", + "CLK_HROW_BLOCK_OUTS_B3_2", + "CLK_BUFG_BOT_R_CK_MUXED19", + "CLK_BUFG_R_CK_FB_TEST1_9", + "CLK_BUFG_BUFGCTRL3_O", + "CLK_HROW_EL1BEG2_3", + "CLK_BUFG_LOGIC_OUTS_B7_1", + "CLK_HROW_EE2BEG1_3", + "CLK_BUFG_IMUX13_0", + "CLK_HROW_LH1_3", + "CLK_HROW_FAN1_3", + "CLK_HROW_WW2END2_1", + "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "CLK_BUFG_IMUX2_3", + "CLK_HROW_NE2A2_3", + "CLK_BUFG_R_BUFGCTRL8_S1", + "CLK_HROW_NW4A0_2", + "CLK_BUFG_IMUX30_0", + "CLK_BUFG_R_BUFGCTRL0_S1", + "CLK_BUFG_BUFGCTRL2_I0", + "CLK_BUFG_LOGIC_OUTS_B14_1", + "CLK_HROW_WW4A0_0", + "CLK_HROW_NE4C3_2", + "CLK_HROW_EE4BEG3_1", + "CLK_HROW_NE2A1_0", + "CLK_BUFG_LOGIC_OUTS_B3_2", + "CLK_HROW_NW4A2_2", + "CLK_HROW_SE4BEG0_1", + "CLK_HROW_SW4A1_3", + "CLK_BUFG_R_CK_FB_TEST0_2", + "CLK_BUFG_IMUX13_1", + "CLK_HROW_WW2A0_2", + "CLK_BUFG_BUFGCTRL6_I1", + "CLK_BUFG_BUFGCTRL6_O", + "CLK_BUFG_IMUX22_2", + "CLK_HROW_BYP7_1", + "CLK_BUFG_IMUX43_2", + "CLK_HROW_CTRL0_0", + "CLK_HROW_EE4C0_3", + "CLK_BUFG_R_BUFGCTRL6_S0", + "CLK_BUFG_IMUX11_1", + "CLK_BUFG_BOT_R_CK_MUXED2", + "CLK_BUFG_R_FBG_OUT12", + "CLK_BUFG_IMUX11_3", + "CLK_BUFG_BUFGCTRL14_O", + "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "CLK_HROW_CLK0_2", + "CLK_HROW_NW4END3_0", + "CLK_HROW_BLOCK_OUTS_B0_0", + "CLK_BUFG_IMUX32_0", + "CLK_HROW_EE4C0_1", + "CLK_HROW_SE2A3_1", + "CLK_HROW_SW2A3_3", + "CLK_HROW_FAN7_0", + "CLK_HROW_EE4A2_1", + "CLK_HROW_EE4BEG1_1", + "CLK_BUFG_BOT_R_CK_MUXED5", + "CLK_HROW_SE2A3_0", + "CLK_HROW_SE4C3_1", + "CLK_HROW_EE2A1_3", + "CLK_HROW_WR1END1_3", + "CLK_HROW_EE4BEG2_1", + "CLK_BUFG_R_BUFGCTRL9_CE0", + "CLK_HROW_SW2A3_1", + "CLK_HROW_SE2A2_1", + "CLK_HROW_WW4END2_2", + "CLK_HROW_WR1END0_2", + "CLK_BUFG_IMUX28_3", + "CLK_HROW_WW2A3_0", + "CLK_BUFG_R_FBG_OUT9", + "CLK_BUFG_BUFGCTRL0_I1", + "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "CLK_HROW_EE4B2_2", + "CLK_BUFG_IMUX7_3", + "CLK_BUFG_LOGIC_OUTS_B5_2", + "CLK_HROW_WW4END1_2", + "CLK_HROW_WW4B3_3", + "CLK_BUFG_LOGIC_OUTS_B22_2", + "CLK_HROW_SW4END1_0", + "CLK_BUFG_BUFGCTRL1_I1", + "CLK_BUFG_LOGIC_OUTS_B20_2", + "CLK_BUFG_IMUX12_3", + "CLK_BUFG_IMUX42_3", + "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "CLK_BUFG_IMUX4_0", + "CLK_HROW_EE2A3_2", + "CLK_HROW_SW4A0_3", + "CLK_BUFG_IMUX16_1", + "CLK_HROW_WW2A3_1", + "CLK_HROW_WW4B3_1", + "CLK_BUFG_IMUX18_2", + "CLK_HROW_NW4END3_3", + "CLK_BUFG_BOT_R_CK_MUXED27", + "CLK_HROW_WW4END3_1", + "CLK_BUFG_BOT_R_CK_MUXED28", + "CLK_BUFG_IMUX38_1", + "CLK_HROW_EE2BEG3_1", + "CLK_BUFG_IMUX31_1", + "CLK_HROW_NW4END1_0", + "CLK_HROW_WW4A0_2", + "CLK_HROW_NW4A2_3", + "CLK_HROW_NE4C1_3", + "CLK_HROW_EE4B2_3", + "CLK_BUFG_LOGIC_OUTS_B22_3", + "CLK_HROW_FAN3_1", + "CLK_HROW_NW4END1_2", + "CLK_HROW_FAN4_3", + "CLK_HROW_CLK1_1", + "CLK_HROW_WR1END2_2", + "CLK_BUFG_IMUX45_2", + "CLK_BUFG_CK_GCLK13", + "CLK_BUFG_R_BUFGCTRL10_S0", + "CLK_BUFG_IMUX36_2", + "CLK_HROW_EE4C0_0", + "CLK_BUFG_LOGIC_OUTS_B1_1", + "CLK_HROW_SE2A0_0", + "CLK_BUFG_BOT_R_CK_MUXED22", + "CLK_BUFG_R_BUFGCTRL9_S0", + "CLK_HROW_NE4C1_0", + "CLK_BUFG_LOGIC_OUTS_B8_0", + "CLK_HROW_EE2BEG1_1", + "CLK_BUFG_IMUX40_1", + "CLK_BUFG_CK_GCLK10", + "CLK_BUFG_IMUX8_2", + "CLK_HROW_EE4C3_0", + "CLK_BUFG_R_FBG_OUT6", + "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "CLK_HROW_SW4END3_0", + "CLK_BUFG_IMUX19_0", + "CLK_BUFG_IMUX27_3", + "CLK_HROW_NW4A2_1", + "CLK_BUFG_IMUX23_2", + "CLK_BUFG_LOGIC_OUTS_B12_3", + "CLK_BUFG_IMUX1_2", + "CLK_HROW_SW4END0_0", + "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "CLK_HROW_EE2BEG3_3", + "CLK_BUFG_IMUX8_1", + "CLK_HROW_EE4B0_2", + "CLK_BUFG_IMUX25_3", + "CLK_HROW_WL1END2_3", + "CLK_HROW_EE4C1_0", + "CLK_HROW_WW2END3_0", + "CLK_BUFG_LOGIC_OUTS_B19_2", + "CLK_HROW_WR1END2_1", + "CLK_BUFG_LOGIC_OUTS_B19_0", + "CLK_HROW_LH8_3", + "CLK_HROW_FAN7_1", + "CLK_BUFG_IMUX47_2", + "CLK_BUFG_LOGIC_OUTS_B1_0", + "CLK_BUFG_R_CK_FB_TEST1_6", + "CLK_HROW_SE4BEG1_3", + "CLK_BUFG_LOGIC_OUTS_B10_3", + "CLK_BUFG_IMUX25_2", + "CLK_HROW_LH6_0", + "CLK_HROW_LH7_0", + "CLK_BUFG_IMUX24_2", + "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "CLK_BUFG_IMUX18_3", + "CLK_HROW_LH12_2", + "CLK_BUFG_IMUX0_2", + "CLK_BUFG_R_CK_FB_TEST0_9", + "CLK_BUFG_LOGIC_OUTS_B14_0", + "CLK_HROW_EE2BEG1_2", + "CLK_HROW_WW2END2_3", + "CLK_BUFG_IMUX31_2", + "CLK_HROW_EE4B1_1", + "CLK_HROW_NE4BEG2_2", + "CLK_BUFG_IMUX40_3", + "CLK_HROW_NE2A2_2", + "CLK_HROW_SE4C1_1", + "CLK_HROW_BLOCK_OUTS_B1_3", + "CLK_HROW_SE4C1_2", + "CLK_HROW_EE4C3_1", + "CLK_HROW_SW2A2_1", + "CLK_HROW_EE2BEG0_0", + "CLK_BUFG_BUFGCTRL8_I1", + "CLK_BUFG_IMUX45_3", + "CLK_HROW_BLOCK_OUTS_B0_1", + "CLK_BUFG_LOGIC_OUTS_B13_2", + "CLK_BUFG_R_BUFGCTRL0_S0", + "CLK_HROW_WW2A1_3", + "CLK_BUFG_IMUX42_0", + "CLK_BUFG_BUFGCTRL3_I1", + "CLK_HROW_EE4A1_2", + "CLK_HROW_MONITOR_P_0", + "CLK_HROW_NE4BEG1_2", + "CLK_HROW_NW2A2_0", + "CLK_BUFG_LOGIC_OUTS_B23_1", + "CLK_HROW_NE2A3_3", + "CLK_BUFG_R_BUFGCTRL11_S1", + "CLK_BUFG_CK_GCLK3", + "CLK_BUFG_LOGIC_OUTS_B22_1", + "CLK_BUFG_LOGIC_OUTS_B16_2", + "CLK_BUFG_IMUX23_0", + "CLK_BUFG_IMUX44_2", + "CLK_BUFG_R_BUFGCTRL5_S0", + "CLK_HROW_EE2A3_3", + "CLK_BUFG_IMUX37_3", + "CLK_HROW_SW4END2_1", + "CLK_BUFG_IMUX32_2", + "CLK_BUFG_CK_GCLK21", + "CLK_BUFG_R_FBG_OUT8", + "CLK_BUFG_BUFGCTRL9_O", + "CLK_HROW_SE2A3_3", + "CLK_HROW_NE4C0_1", + "CLK_HROW_EE4C3_2", + "CLK_HROW_NW4A1_0", + "CLK_BUFG_LOGIC_OUTS_B18_2", + "CLK_BUFG_LOGIC_OUTS_B11_1", + "CLK_HROW_ER1BEG1_0", + "CLK_BUFG_LOGIC_OUTS_B16_0", + "CLK_HROW_EE2A2_1", + "CLK_HROW_EE4BEG1_2", + "CLK_BUFG_CK_GCLK17", + "CLK_BUFG_IMUX10_2", + "CLK_BUFG_R_CK_FB_TEST0_5", + "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "CLK_HROW_WW4A0_1", + "CLK_HROW_ER1BEG3_2", + "CLK_HROW_EE2BEG2_1", + "CLK_HROW_SE4BEG1_0", + "CLK_HROW_NE4BEG2_1", + "CLK_BUFG_IMUX30_3", + "CLK_HROW_EE4A1_1", + "CLK_BUFG_R_CK_FB_TEST0_3", + "CLK_HROW_NW4END0_3", + "CLK_HROW_CTRL1_1", + "CLK_BUFG_LOGIC_OUTS_B13_0", + "CLK_BUFG_R_CK_FB_TEST0_15", + "CLK_HROW_SW4A1_2", + "CLK_BUFG_R_CK_FB_TEST0_1", + "CLK_HROW_EE4A1_3", + "CLK_HROW_FAN6_3", + "CLK_HROW_SW2A2_0", + "CLK_HROW_LH11_2", + "CLK_BUFG_IMUX20_2", + "CLK_BUFG_R_CK_FB_TEST1_13", + "CLK_HROW_LH12_3", + "CLK_HROW_SW2A2_3", + "CLK_BUFG_BUFGCTRL4_I1", + "CLK_BUFG_IMUX44_3", + "CLK_BUFG_LOGIC_OUTS_B5_0", + "CLK_HROW_SE2A0_2", + "CLK_HROW_NE2A1_1", + "CLK_BUFG_IMUX46_3", + "CLK_HROW_EE4B0_0", + "CLK_HROW_FAN6_0", + "CLK_HROW_EE2BEG0_1", + "CLK_BUFG_BOT_R_CK_MUXED15", + "CLK_HROW_EE4A3_3", + "CLK_HROW_NE4C1_1", + "CLK_BUFG_BUFGCTRL5_I0", + "CLK_HROW_LH10_1", + "CLK_HROW_BYP0_3", + "CLK_HROW_EE4C1_3", + "CLK_HROW_CTRL1_2", + "CLK_BUFG_IMUX30_1", + "CLK_HROW_NW2A3_3", + "CLK_BUFG_R_BUFGCTRL11_CE1", + "CLK_HROW_SE4BEG0_0", + "CLK_HROW_LH5_3", + "CLK_BUFG_BUFGCTRL10_I0", + "CLK_BUFG_R_CK_FB_TEST1_3", + "CLK_BUFG_LOGIC_OUTS_B2_0", + "CLK_HROW_SE2A2_0", + "CLK_HROW_SW4END3_1", + "CLK_BUFG_R_CK_FB_TEST1_5", + "CLK_HROW_NE2A0_1", + "CLK_BUFG_LOGIC_OUTS_B15_1", + "CLK_BUFG_R_CK_FB_TEST1_10", + "CLK_BUFG_IMUX18_1", + "CLK_HROW_WR1END1_1", + "CLK_HROW_SW2A3_0", + "CLK_HROW_LH3_0", + "CLK_HROW_BLOCK_OUTS_B1_2", + "CLK_HROW_EE4A0_0", + "CLK_HROW_WR1END0_1", + "CLK_BUFG_LOGIC_OUTS_B0_3", + "CLK_BUFG_LOGIC_OUTS_B4_3", + "CLK_HROW_SW4A2_0", + "CLK_HROW_EE2A0_3", + "CLK_HROW_NW4A3_3", + "CLK_BUFG_LOGIC_OUTS_B7_0", + "CLK_HROW_WW2A1_1", + "CLK_BUFG_CK_GCLK2", + "CLK_BUFG_LOGIC_OUTS_B18_3", + "CLK_BUFG_BUFGCTRL0_I0", + "CLK_HROW_NW4END3_1", + "CLK_HROW_LH9_2", + "CLK_BUFG_IMUX9_1", + "CLK_HROW_FAN2_1", + "CLK_BUFG_R_CK_FB_TEST0_11", + "CLK_HROW_LH10_0", + "CLK_HROW_ER1BEG0_1", + "CLK_BUFG_IMUX9_3", + "CLK_HROW_EE2BEG3_0", + "CLK_HROW_WW2A0_1", + "CLK_HROW_ER1BEG1_1", + "CLK_HROW_MONITOR_P_2", + "CLK_HROW_WW2A2_3", + "CLK_HROW_NE4BEG0_1", + "CLK_BUFG_LOGIC_OUTS_B15_2", + "CLK_BUFG_BUFGCTRL10_O", + "CLK_HROW_WL1END3_0", + "CLK_HROW_LH6_1", + "CLK_HROW_SE4C1_0", + "CLK_BUFG_CK_GCLK25", + "CLK_HROW_EE4B3_2", + "CLK_HROW_BLOCK_OUTS_B3_3", + "CLK_HROW_SW2A0_1", + "CLK_BUFG_CK_GCLK18", + "CLK_HROW_LH3_3", + "CLK_BUFG_IMUX24_3", + "CLK_HROW_NW4END0_2", + "CLK_HROW_WW2END0_2", + "CLK_BUFG_CK_GCLK11", + "CLK_BUFG_IMUX33_0", + "CLK_HROW_WW4A1_2", + "CLK_BUFG_LOGIC_OUTS_B11_2", + "CLK_BUFG_R_FBG_OUT11", + "CLK_BUFG_R_FBG_OUT10", + "CLK_HROW_WW4A2_3", + "CLK_HROW_BYP5_3", + "CLK_HROW_EE4BEG0_3", + "CLK_BUFG_LOGIC_OUTS_B23_3", + "CLK_HROW_LH1_2", + "CLK_BUFG_BOT_R_CK_MUXED9", + "CLK_BUFG_LOGIC_OUTS_B9_3", + "CLK_HROW_WW4END0_2", + "CLK_HROW_BYP1_3", + "CLK_BUFG_CK_GCLK30", + "CLK_BUFG_CK_GCLK28", + "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "CLK_HROW_LH7_1", + "CLK_HROW_BLOCK_OUTS_B1_1", + "CLK_HROW_EL1BEG2_1", + "CLK_BUFG_IMUX20_3", + "CLK_HROW_EE4C2_3", + "CLK_BUFG_BUFGCTRL2_I1", + "CLK_HROW_ER1BEG1_2", + "CLK_BUFG_IMUX22_1", + "CLK_HROW_WW4END0_0", + "CLK_BUFG_LOGIC_OUTS_B19_3", + "CLK_BUFG_IMUX0_0", + "CLK_HROW_BYP4_3", + "CLK_HROW_WW2END0_1", + "CLK_BUFG_R_CK_FB_TEST0_8", + "CLK_HROW_SW4A0_0", + "CLK_HROW_WW4END2_1", + "CLK_HROW_SW4END1_3", + "CLK_BUFG_IMUX34_2", + "CLK_BUFG_IMUX1_1", + "CLK_BUFG_BUFGCTRL15_I0", + "CLK_HROW_BYP3_0", + "CLK_HROW_EE4A1_0", + "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B21_0", + "CLK_HROW_EL1BEG0_2", + "CLK_BUFG_R_BUFGCTRL0_CE0", + "CLK_BUFG_LOGIC_OUTS_B6_0", + "CLK_HROW_WW4C3_3", + "CLK_HROW_NE4BEG2_3", + "CLK_HROW_SE4BEG3_0", + "CLK_BUFG_IMUX40_2", + "CLK_BUFG_R_BUFGCTRL7_CE1", + "CLK_BUFG_CK_GCLK8", + "CLK_HROW_ER1BEG2_2", + "CLK_HROW_EL1BEG1_3", + "CLK_BUFG_R_CK_FB_TEST1_12", + "CLK_HROW_WL1END1_2", + "CLK_BUFG_R_BUFGCTRL13_S0", + "CLK_BUFG_LOGIC_OUTS_B19_1", + "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "CLK_HROW_FAN0_0", + "CLK_HROW_SW4A3_1", + "CLK_BUFG_IMUX21_3", + "CLK_HROW_NW4A2_0", + "CLK_HROW_NE4C2_0", + "CLK_HROW_WW2A0_3", + "CLK_HROW_WW2END1_2", + "CLK_HROW_LH12_0", + "CLK_BUFG_CK_GCLK14", + "CLK_HROW_NW2A1_2", + "CLK_BUFG_IMUX6_1", + "CLK_BUFG_LOGIC_OUTS_B12_2", + "CLK_BUFG_IMUX43_1", + "CLK_BUFG_IMUX32_1", + "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "CLK_BUFG_BUFGCTRL0_O", + "CLK_BUFG_BOT_R_CK_MUXED18", + "CLK_BUFG_LOGIC_OUTS_B12_0", + "CLK_HROW_EE4A3_1", + "CLK_HROW_WW4C0_1", + "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "CLK_BUFG_BUFGCTRL2_O", + "CLK_BUFG_CK_GCLK31", + "CLK_HROW_BYP5_2", + "CLK_BUFG_BOT_R_CK_MUXED12", + "CLK_BUFG_R_BUFGCTRL9_CE1", + "CLK_HROW_LH5_0", + "CLK_BUFG_LOGIC_OUTS_B20_3", + "CLK_BUFG_R_BUFGCTRL3_CE1", + "CLK_HROW_WR1END0_3", + "CLK_BUFG_R_CK_FB_TEST0_14", + "CLK_BUFG_LOGIC_OUTS_B3_1", + "CLK_HROW_LH6_2", + "CLK_BUFG_IMUX19_1", + "CLK_HROW_NW4A1_2", + "CLK_HROW_EL1BEG1_1", + "CLK_HROW_EE4C2_1", + "CLK_HROW_SW4END2_3", + "CLK_HROW_SE2A2_3", + "CLK_HROW_BYP3_2", + "CLK_BUFG_BOT_R_CK_MUXED1", + "CLK_HROW_LH11_0", + "CLK_BUFG_LOGIC_OUTS_B20_0", + "CLK_HROW_NE4C2_1", + "CLK_BUFG_IMUX28_2", + "CLK_HROW_WW2A3_3", + "CLK_HROW_LH7_3", + "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "CLK_HROW_NW2A0_3", + "CLK_HROW_WW4B2_2", + "CLK_BUFG_IMUX41_1", + "CLK_BUFG_R_CK_FB_TEST1_14", + "CLK_HROW_EE4BEG2_2", + "CLK_BUFG_CK_GCLK29", + "CLK_BUFG_BUFGCTRL5_O", + "CLK_BUFG_R_BUFGCTRL11_S0", + "CLK_HROW_SE4BEG3_2", + "CLK_BUFG_R_BUFGCTRL13_CE0", + "CLK_HROW_ER1BEG2_3", + "CLK_HROW_BYP4_2", + "CLK_HROW_WW4B0_3", + "CLK_HROW_LH8_1", + "CLK_HROW_NW4END0_1", + "CLK_BUFG_IMUX39_2", + "CLK_BUFG_IMUX29_1", + "CLK_HROW_BYP6_3", + "CLK_HROW_EE4A2_0", + "CLK_HROW_FAN2_3", + "CLK_BUFG_IMUX27_0", + "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "CLK_BUFG_CK_GCLK24", + "CLK_HROW_CLK0_0", + "CLK_BUFG_IMUX5_0", + "CLK_BUFG_CK_GCLK4", + "CLK_BUFG_IMUX34_1", + "CLK_HROW_NW2A3_0", + "CLK_HROW_NE4C3_0", + "CLK_HROW_LH6_3", + "CLK_HROW_BYP0_2", + "CLK_BUFG_BUFGCTRL12_O", + "CLK_BUFG_BUFGCTRL8_O", + "CLK_HROW_EE4A0_2", + "CLK_HROW_NE2A1_2", + "CLK_HROW_EE2A0_0", + "CLK_BUFG_IMUX26_1", + "CLK_BUFG_BOT_R_CK_MUXED4", + "CLK_HROW_WW4C2_1", + "CLK_HROW_SE4C1_3", + "CLK_HROW_WW4B2_3", + "CLK_HROW_FAN6_2", + "CLK_BUFG_R_BUFGCTRL14_S0", + "CLK_HROW_LH12_1", + "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "CLK_HROW_WR1END1_2", + "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B0_0", + "CLK_BUFG_R_FBG_OUT3", + "CLK_HROW_LH5_1", + "CLK_BUFG_IMUX38_2", + "CLK_BUFG_LOGIC_OUTS_B2_1", + "CLK_HROW_SE4C0_2", + "CLK_HROW_WW4C0_0", + "CLK_BUFG_BUFGCTRL4_O", + "CLK_HROW_NE4BEG0_0", + "CLK_HROW_WW4A3_3", + "CLK_HROW_WR1END0_0", + "CLK_HROW_SW2A0_3", + "CLK_HROW_LH9_3", + "CLK_BUFG_BOT_R_CK_MUXED16", + "CLK_HROW_WW2END3_1", + "CLK_BUFG_BUFGCTRL4_I0", + "CLK_HROW_WW4A2_0", + "CLK_BUFG_LOGIC_OUTS_B0_2", + "CLK_HROW_WW2A1_2", + "CLK_HROW_EE4B3_1", + "CLK_BUFG_IMUX26_2", + "CLK_HROW_NE4C0_2", + "CLK_HROW_WL1END1_3", + "CLK_HROW_SW2A3_2", + "CLK_HROW_MONITOR_N_0", + "CLK_BUFG_LOGIC_OUTS_B3_3", + "CLK_HROW_EE2A2_0", + "CLK_HROW_MONITOR_N_1", + "CLK_BUFG_R_BUFGCTRL4_S1", + "CLK_BUFG_IMUX39_0", + "CLK_BUFG_CK_GCLK26", + "CLK_BUFG_IMUX21_1", + "CLK_BUFG_IMUX29_2", + "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "CLK_HROW_SE4BEG2_2", + "CLK_HROW_EE4B3_0", + "CLK_BUFG_IMUX29_3", + "CLK_BUFG_IMUX42_1", + "CLK_HROW_BYP1_1", + "CLK_HROW_SW4END1_1", + "CLK_BUFG_IMUX16_0", + "CLK_HROW_SE4BEG1_1", + "CLK_BUFG_R_BUFGCTRL7_S0", + "CLK_HROW_BYP2_3", + "CLK_HROW_EE4C0_2", + "CLK_HROW_LH9_0", + "CLK_HROW_WL1END2_2", + "CLK_BUFG_IMUX0_3", + "CLK_BUFG_IMUX33_1", + "CLK_HROW_WW2A1_0", + "CLK_HROW_FAN5_2", + "CLK_HROW_WW4B2_0", + "CLK_HROW_WW4B3_2", + "CLK_HROW_EE2BEG3_2", + "CLK_HROW_ER1BEG0_3", + "CLK_HROW_NW4A3_2", + "CLK_HROW_WW4A2_1", + "CLK_HROW_LH11_3", + "CLK_HROW_FAN6_1", + "CLK_BUFG_IMUX37_1", + "CLK_BUFG_R_CK_FB_TEST1_2", + "CLK_HROW_EE4BEG0_1", + "CLK_BUFG_R_BUFGCTRL14_CE0", + "CLK_BUFG_BUFGCTRL12_I1", + "CLK_HROW_SE2A2_2", + "CLK_HROW_EE4C3_3", + "CLK_HROW_BLOCK_OUTS_B0_3", + "CLK_BUFG_BOT_R_CK_MUXED7", + "CLK_HROW_EE2BEG1_0", + "CLK_HROW_SE2A3_2", + "CLK_HROW_NE4BEG1_3", + "CLK_HROW_WW4C3_1", + "CLK_HROW_SW4A3_0", + "CLK_BUFG_BOT_R_CK_MUXED21", + "CLK_BUFG_IMUX13_2", + "CLK_HROW_LH11_1", + "CLK_BUFG_IMUX21_0", + "CLK_HROW_NW2A0_0", + "CLK_BUFG_R_BUFGCTRL7_CE0", + "CLK_HROW_NE4BEG0_2", + "CLK_BUFG_IMUX34_3", + "CLK_HROW_ER1BEG2_0", + "CLK_HROW_EE2A1_2", + "CLK_BUFG_R_FBG_OUT4", + "CLK_HROW_WW4C3_0", + "CLK_BUFG_BOT_R_CK_MUXED0", + "CLK_HROW_EL1BEG2_2", + "CLK_BUFG_R_BUFGCTRL8_S0", + "CLK_HROW_LH2_3", + "CLK_HROW_EE4BEG0_0", + "CLK_BUFG_LOGIC_OUTS_B15_3", + "CLK_BUFG_IMUX38_0", + "CLK_BUFG_IMUX1_0", + "CLK_BUFG_IMUX10_0", + "CLK_HROW_EE4BEG2_3", + "CLK_HROW_WW2END1_1", + "CLK_BUFG_LOGIC_OUTS_B17_0", + "CLK_BUFG_IMUX47_1", + "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "CLK_HROW_SW2A1_3", + "CLK_BUFG_IMUX28_1", + "CLK_BUFG_IMUX2_2", + "CLK_HROW_SE4BEG0_2", + "CLK_HROW_NE4C1_2", + "CLK_BUFG_R_CK_FB_TEST0_10", + "CLK_BUFG_IMUX45_0", + "CLK_HROW_SW4A2_3", + "CLK_HROW_NE2A3_0", + "CLK_HROW_WW4A1_3", + "CLK_BUFG_BUFGCTRL8_I0", + "CLK_HROW_SE2A1_0", + "CLK_HROW_SW4A3_3", + "CLK_BUFG_R_BUFGCTRL12_S0", + "CLK_HROW_SE4C2_3", + "CLK_HROW_WW4C1_3", + "CLK_HROW_WR1END3_1", + "CLK_BUFG_R_BUFGCTRL3_CE0", + "CLK_BUFG_IMUX41_0", + "CLK_HROW_NW2A1_0", + "CLK_HROW_NE4BEG1_0", + "CLK_HROW_EE4C1_1", + "CLK_BUFG_BUFGCTRL13_O", + "CLK_BUFG_IMUX36_0", + "CLK_HROW_WL1END0_1", + "CLK_BUFG_IMUX37_2", + "CLK_HROW_LH3_2", + "CLK_BUFG_IMUX44_1", + "CLK_HROW_WL1END0_3", + "CLK_BUFG_IMUX42_2", + "CLK_BUFG_LOGIC_OUTS_B14_3", + "CLK_HROW_EE4B0_1", + "CLK_BUFG_R_BUFGCTRL14_CE1", + "CLK_BUFG_LOGIC_OUTS_B20_1", + "CLK_BUFG_IMUX17_3", + "CLK_BUFG_IMUX4_1", + "CLK_HROW_SW4A0_1", + "CLK_HROW_EE2BEG0_3", + "CLK_BUFG_R_BUFGCTRL2_CE0", + "CLK_HROW_EL1BEG1_0", + "CLK_HROW_BLOCK_OUTS_B2_3", + "CLK_HROW_EL1BEG3_1", + "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "CLK_HROW_SE4C0_0", + "CLK_HROW_EE4A3_2", + "CLK_BUFG_IMUX14_3", + "CLK_BUFG_IMUX33_2", + "CLK_BUFG_IMUX1_3", + "CLK_BUFG_BOT_R_CK_MUXED11", + "CLK_HROW_ER1BEG0_2", + "CLK_BUFG_CK_GCLK19", + "CLK_BUFG_IMUX14_0", + "CLK_BUFG_R_CK_FB_TEST1_15", + "CLK_BUFG_LOGIC_OUTS_B10_2", + "CLK_HROW_BYP0_1", + "CLK_HROW_NE4BEG3_1", + "CLK_HROW_EE4C2_2", + "CLK_BUFG_R_CK_FB_TEST1_11", + "CLK_BUFG_R_BUFGCTRL1_S0", + "CLK_BUFG_IMUX27_2", + "CLK_BUFG_LOGIC_OUTS_B11_3", + "CLK_HROW_EE2BEG2_2", + "CLK_HROW_WW4A0_3", + "CLK_HROW_WL1END0_2", + "CLK_HROW_SW4END0_3", + "CLK_BUFG_IMUX2_1", + "CLK_BUFG_IMUX32_3", + "CLK_HROW_BLOCK_OUTS_B2_0", + "CLK_BUFG_R_CK_FB_TEST0_6", + "CLK_BUFG_IMUX19_3", + "CLK_BUFG_IMUX19_2", + "CLK_HROW_SW2A0_2", + "CLK_HROW_FAN0_2", + "CLK_HROW_EL1BEG3_0", + "CLK_HROW_WR1END1_0", + "CLK_BUFG_BUFGCTRL14_I1", + "CLK_HROW_WL1END3_1", + "CLK_HROW_WW2END0_3", + "CLK_HROW_BYP6_2", + "CLK_HROW_WW4A3_2", + "CLK_BUFG_R_BUFGCTRL7_S1", + "CLK_BUFG_BUFGCTRL3_I0", + "CLK_BUFG_BOT_R_CK_MUXED25", + "CLK_HROW_SE4C3_0", + "CLK_BUFG_IMUX33_3", + "CLK_HROW_EE4B1_3", + "CLK_HROW_FAN3_0", + "CLK_HROW_NE2A1_3", + "CLK_HROW_SE4C3_2", + "CLK_HROW_SW4END0_1", + "CLK_HROW_LH8_0", + "CLK_HROW_NE4BEG3_0", + "CLK_HROW_FAN1_2", + "CLK_HROW_WW2A2_0", + "CLK_HROW_NE4C3_3", + "CLK_HROW_NW4A0_0", + "CLK_BUFG_R_BUFGCTRL10_CE1", + "CLK_BUFG_R_CK_FB_TEST1_1", + "CLK_HROW_NE4C3_1", + "CLK_HROW_NE2A3_2", + "CLK_HROW_ER1BEG1_3", + "CLK_HROW_BYP3_3", + "CLK_BUFG_IMUX6_0", + "CLK_HROW_WW2A2_1", + "CLK_BUFG_R_CK_FB_TEST0_7", + "CLK_BUFG_BUFGCTRL7_I1", + "CLK_BUFG_IMUX27_1", + "CLK_HROW_MONITOR_N_2", + "CLK_HROW_EE4BEG1_3", + "CLK_BUFG_IMUX14_2", + "CLK_HROW_FAN5_3", + "CLK_BUFG_IMUX47_3", + "CLK_HROW_SW4END2_0", + "CLK_BUFG_R_BUFGCTRL14_S1", + "CLK_HROW_LH4_1", + "CLK_HROW_EL1BEG2_0", + "CLK_HROW_SE2A0_3", + "CLK_BUFG_LOGIC_OUTS_B6_1", + "CLK_HROW_EE4BEG3_0", + "CLK_HROW_ER1BEG3_1", + "CLK_BUFG_IMUX7_0", + "CLK_BUFG_R_BUFGCTRL11_CE0", + "CLK_HROW_NW4END2_0", + "CLK_BUFG_R_CK_FB_TEST0_13", + "CLK_HROW_SW4A0_2", + "CLK_HROW_SW4END3_2", + "CLK_BUFG_IMUX45_1", + "CLK_HROW_NE4BEG2_0", + "CLK_BUFG_R_FBG_OUT15", + "CLK_BUFG_R_BUFGCTRL2_CE1", + "CLK_BUFG_IMUX35_1", + "CLK_HROW_SE4BEG2_1", + "CLK_HROW_CTRL0_2", + "CLK_HROW_NE4BEG1_1", + "CLK_BUFG_IMUX36_3", + "CLK_HROW_FAN3_3", + "CLK_HROW_FAN1_1", + "CLK_BUFG_BUFGCTRL6_I0", + "CLK_BUFG_IMUX17_1", + "CLK_HROW_EE4C1_2", + "CLK_BUFG_CK_GCLK20", + "CLK_HROW_NE4BEG3_2", + "CLK_HROW_EE2A1_1", + "CLK_HROW_EE2A2_3", + "CLK_HROW_NW4END2_2", + "CLK_HROW_WW4END2_3", + "CLK_BUFG_IMUX15_2", + "CLK_BUFG_IMUX2_0", + "CLK_HROW_FAN5_0", + "CLK_HROW_ER1BEG0_0", + "CLK_BUFG_IMUX36_1", + "CLK_HROW_WW4END2_0", + "CLK_BUFG_CK_GCLK12", + "CLK_HROW_EE4B1_0", + "CLK_HROW_NW4END2_1", + "CLK_BUFG_LOGIC_OUTS_B17_2", + "CLK_HROW_EE2A2_2", + "CLK_BUFG_R_CK_FB_TEST1_8", + "CLK_HROW_WW4A2_2", + "CLK_HROW_EE4BEG2_0", + "CLK_HROW_FAN4_0", + "CLK_BUFG_IMUX39_1", + "CLK_HROW_BYP7_3", + "CLK_HROW_WW4B1_2", + "CLK_BUFG_LOGIC_OUTS_B5_3", + "CLK_HROW_NE2A0_2", + "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "CLK_BUFG_R_BUFGCTRL5_CE0", + "CLK_HROW_LH4_3" + ], + "tile_type": "CLK_BUFG_BOT_R", + "sites": [ + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL0_I1", + "S1": "CLK_BUFG_R_BUFGCTRL0_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", + "I0": "CLK_BUFG_BUFGCTRL0_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL0_S0", + "O": "CLK_BUFG_BUFGCTRL0_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL1_I1", + "S1": "CLK_BUFG_R_BUFGCTRL1_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", + "I0": "CLK_BUFG_BUFGCTRL1_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL1_S0", + "O": "CLK_BUFG_BUFGCTRL1_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL2_I1", + "S1": "CLK_BUFG_R_BUFGCTRL2_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", + "I0": "CLK_BUFG_BUFGCTRL2_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL2_S0", + "O": "CLK_BUFG_BUFGCTRL2_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y2", + "x_coord": 0, + "y_coord": 2 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL3_I1", + "S1": "CLK_BUFG_R_BUFGCTRL3_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", + "I0": "CLK_BUFG_BUFGCTRL3_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL3_S0", + "O": "CLK_BUFG_BUFGCTRL3_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y3", + "x_coord": 0, + "y_coord": 3 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL4_I1", + "S1": "CLK_BUFG_R_BUFGCTRL4_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", + "I0": "CLK_BUFG_BUFGCTRL4_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL4_S0", + "O": "CLK_BUFG_BUFGCTRL4_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y4", + "x_coord": 0, + "y_coord": 4 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL5_I1", + "S1": "CLK_BUFG_R_BUFGCTRL5_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", + "I0": "CLK_BUFG_BUFGCTRL5_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL5_S0", + "O": "CLK_BUFG_BUFGCTRL5_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y5", + "x_coord": 0, + "y_coord": 5 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL6_I1", + "S1": "CLK_BUFG_R_BUFGCTRL6_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", + "I0": "CLK_BUFG_BUFGCTRL6_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL6_S0", + "O": "CLK_BUFG_BUFGCTRL6_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y6", + "x_coord": 0, + "y_coord": 6 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL7_I1", + "S1": "CLK_BUFG_R_BUFGCTRL7_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", + "I0": "CLK_BUFG_BUFGCTRL7_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL7_S0", + "O": "CLK_BUFG_BUFGCTRL7_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y7", + "x_coord": 0, + "y_coord": 7 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL8_I1", + "S1": "CLK_BUFG_R_BUFGCTRL8_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", + "I0": "CLK_BUFG_BUFGCTRL8_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL8_S0", + "O": "CLK_BUFG_BUFGCTRL8_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y8", + "x_coord": 0, + "y_coord": 8 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL9_I1", + "S1": "CLK_BUFG_R_BUFGCTRL9_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", + "I0": "CLK_BUFG_BUFGCTRL9_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL9_S0", + "O": "CLK_BUFG_BUFGCTRL9_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y9", + "x_coord": 0, + "y_coord": 9 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL10_I1", + "S1": "CLK_BUFG_R_BUFGCTRL10_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", + "I0": "CLK_BUFG_BUFGCTRL10_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL10_S0", + "O": "CLK_BUFG_BUFGCTRL10_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y10", + "x_coord": 0, + "y_coord": 10 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL11_I1", + "S1": "CLK_BUFG_R_BUFGCTRL11_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", + "I0": "CLK_BUFG_BUFGCTRL11_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL11_S0", + "O": "CLK_BUFG_BUFGCTRL11_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y11", + "x_coord": 0, + "y_coord": 11 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL12_I1", + "S1": "CLK_BUFG_R_BUFGCTRL12_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", + "I0": "CLK_BUFG_BUFGCTRL12_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL12_S0", + "O": "CLK_BUFG_BUFGCTRL12_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y12", + "x_coord": 0, + "y_coord": 12 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL13_I1", + "S1": "CLK_BUFG_R_BUFGCTRL13_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", + "I0": "CLK_BUFG_BUFGCTRL13_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL13_S0", + "O": "CLK_BUFG_BUFGCTRL13_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y13", + "x_coord": 0, + "y_coord": 13 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL14_I1", + "S1": "CLK_BUFG_R_BUFGCTRL14_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", + "I0": "CLK_BUFG_BUFGCTRL14_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL14_S0", + "O": "CLK_BUFG_BUFGCTRL14_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y14", + "x_coord": 0, + "y_coord": 14 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL15_I1", + "S1": "CLK_BUFG_R_BUFGCTRL15_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", + "I0": "CLK_BUFG_BUFGCTRL15_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL15_S0", + "O": "CLK_BUFG_BUFGCTRL15_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y15", + "x_coord": 0, + "y_coord": 15 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_BUFG_REBUF.json b/artix7/tile_type_CLK_BUFG_REBUF.json index dd5b203..ea36356 100644 --- a/artix7/tile_type_CLK_BUFG_REBUF.json +++ b/artix7/tile_type_CLK_BUFG_REBUF.json @@ -1,1188 +1,1188 @@ { - "wires": [ - "CLK_BUFG_REBUF_SE4BEG2_1", - "CLK_BUFG_REBUF_EE2A2_0", - "GCLK21_20_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_CK_GCLK14_BOT", - "CLK_BUFG_REBUF_WR1END0_1", - "GCLK10_11_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", - "CLK_BUFG_REBUF_CK_GCLK6_BOT", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", - "CLK_BUFG_REBUF_CK_GCLK14_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", - "CLK_BUFG_REBUF_CK_BUFG_CASC21", - "GCLK4_5_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_WW2END1_0", - "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", - "CLK_BUFG_REBUF_CK_GCLK1_TOP", - "CLK_BUFG_REBUF_LH7_0", - "CLK_BUFG_REBUF_SW4A1_1", - "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", - "CLK_BUFG_REBUF_WW4B2_0", - "GCLK26_27_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_CK_BUFG_CASC31", - "CLK_BUFG_REBUF_NE4BEG0_1", - "CLK_BUFG_REBUF_CK_GCLK30_BOT", - "GCLK6_7_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_NW4A0_0", - "CLK_BUFG_REBUF_EE4BEG0_0", - "CLK_BUFG_REBUF_CK_BUFG_CASC25", - "CLK_BUFG_REBUF_SW4END1_1", - "CLK_BUFG_REBUF_CK_GCLK0_TOP", - "CLK_BUFG_REBUF_LH2_1", - "CLK_BUFG_REBUF_LH9_0", - "CLK_BUFG_REBUF_CK_GCLK9_BOT", - "CLK_BUFG_REBUF_CK_GCLK12_BOT", - "CLK_BUFG_REBUF_NE4BEG2_0", - "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", - "GCLK22_23_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_SE2A0_1", - "CLK_BUFG_REBUF_EE4A1_1", - "CLK_BUFG_REBUF_SE4C1_1", - "CLK_BUFG_REBUF_WW2END0_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC17", - "CLK_BUFG_REBUF_NW4END3_1", - "CLK_BUFG_REBUF_EL1BEG1_0", - "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", - "GCLK9_8_UP_TEST_RING_OUT", - "GCLK12_13_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_EE2BEG3_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC18", - "CLK_BUFG_REBUF_LH5_1", - "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", - "CLK_BUFG_REBUF_SW4A3_1", - "CLK_BUFG_REBUF_WW4B1_0", - "CLK_BUFG_REBUF_NE4BEG2_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC27", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", - "CLK_BUFG_REBUF_WW4END1_0", - "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", - "CLK_BUFG_REBUF_CK_GCLK24_BOT", - "CLK_BUFG_REBUF_EE4A3_0", - "GCLK1_0_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_EE4C0_0", - "CLK_BUFG_REBUF_LH1_0", - "CLK_BUFG_REBUF_EL1BEG3_1", - "CLK_BUFG_REBUF_NW2A0_1", - "CLK_BUFG_REBUF_CK_GCLK13_TOP", - "CLK_BUFG_REBUF_ER1BEG0_0", - "CLK_BUFG_REBUF_WW4A0_1", - "CLK_BUFG_REBUF_CK_GCLK27_TOP", - "CLK_BUFG_REBUF_LH4_0", - "CLK_BUFG_REBUF_CK_GCLK22_BOT", - "CLK_BUFG_REBUF_SW2A1_1", - "CLK_BUFG_REBUF_CK_GCLK2_BOT", - "GCLK6_7_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_WL1END1_0", - "CLK_BUFG_REBUF_NE4C3_0", - "CLK_BUFG_REBUF_NE2A0_0", - "GCLK25_24_UP_TEST_RING_OUT", - "GCLK18_19_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_SE2A2_1", - "CLK_BUFG_REBUF_LH3_1", - "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", - "GCLK19_18_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_WW4A2_1", - "CLK_BUFG_REBUF_WR1END1_1", - "GCLK28_29_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_WW2A0_1", - "CLK_BUFG_REBUF_WW2END2_1", - "CLK_BUFG_REBUF_NE2A1_0", - "CLK_BUFG_REBUF_EE4C0_1", - "CLK_BUFG_REBUF_WW4B1_1", - "CLK_BUFG_REBUF_CK_GCLK24_TOP", - "CLK_BUFG_REBUF_CK_GCLK20_BOT", - "CLK_BUFG_REBUF_EE4C3_0", - "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", - "CLK_BUFG_REBUF_CK_GCLK28_BOT", - "GCLK19_18_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_CK_BUFG_CASC14", - "CLK_BUFG_REBUF_ER1BEG2_1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", - "CLK_BUFG_REBUF_LH10_0", - "CLK_BUFG_REBUF_CK_GCLK18_BOT", - "CLK_BUFG_REBUF_CK_GCLK4_BOT", - "CLK_BUFG_REBUF_LH5_0", - "GCLK20_21_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_EL1BEG1_1", - "CLK_BUFG_REBUF_NW2A1_1", - "CLK_BUFG_REBUF_SW2A2_1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", - "CLK_BUFG_REBUF_ER1BEG0_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC9", - "GCLK16_17_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_EE4A1_0", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", - "CLK_BUFG_REBUF_CK_BUFG_CASC19", - "CLK_BUFG_REBUF_NW4END3_0", - "CLK_BUFG_REBUF_SW2A0_0", - "CLK_BUFG_REBUF_WW4END3_0", - "CLK_BUFG_REBUF_SW4A1_0", - "CLK_BUFG_REBUF_WW4END0_1", - "GCLK30_31_DN_TEST_RING_IN", - "GCLK2_3_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", - "CLK_BUFG_REBUF_CK_BUFG_CASC20", - "GCLK23_22_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", - "CLK_BUFG_REBUF_WW2END2_0", - "CLK_BUFG_REBUF_WW2END0_0", - "CLK_BUFG_REBUF_EE4A0_1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", - "CLK_BUFG_REBUF_NE2A3_0", - "CLK_BUFG_REBUF_WR1END1_0", - "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", - "CLK_BUFG_REBUF_EE4B2_1", - "CLK_BUFG_REBUF_CK_GCLK13_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", - "CLK_BUFG_REBUF_LH12_1", - "CLK_BUFG_REBUF_WW2A2_0", - "CLK_BUFG_REBUF_SE2A1_1", - "CLK_BUFG_REBUF_EE4A2_0", - "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", - "CLK_BUFG_REBUF_EE4C3_1", - "CLK_BUFG_REBUF_WW4B3_0", - "CLK_BUFG_REBUF_SW4END0_1", - "CLK_BUFG_REBUF_WW4END1_1", - "CLK_BUFG_REBUF_NE4C0_1", - "CLK_BUFG_REBUF_NE4BEG1_0", - "GCLK14_15_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_EE4B1_0", - "CLK_BUFG_REBUF_NE4C0_0", - "GCLK0_1_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_WW4B3_1", - "CLK_BUFG_REBUF_EE4B3_1", - "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", - "CLK_BUFG_REBUF_NW4A3_0", - "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", - "GCLK24_25_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_MONITOR_P_1", - "GCLK14_15_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_WL1END3_1", - "CLK_BUFG_REBUF_SE4C0_1", - "CLK_BUFG_REBUF_WW4B0_1", - "CLK_BUFG_REBUF_CK_GCLK7_BOT", - "CLK_BUFG_REBUF_WL1END0_1", - "CLK_BUFG_REBUF_NW4END2_1", - "GCLK9_8_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_CK_GCLK5_TOP", - "CLK_BUFG_REBUF_CK_GCLK21_BOT", - "GCLK21_20_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", - "CLK_BUFG_REBUF_NE4C1_1", - "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", - "CLK_BUFG_REBUF_EE4C1_0", - "CLK_BUFG_REBUF_LH11_1", - "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", - "GCLK0_1_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_WL1END2_1", - "CLK_BUFG_REBUF_ER1BEG3_0", - "CLK_BUFG_REBUF_EE2BEG1_1", - "CLK_BUFG_REBUF_EE2BEG3_0", - "CLK_BUFG_REBUF_WW2END3_0", - "CLK_BUFG_REBUF_LH2_0", - "CLK_BUFG_REBUF_EE2BEG1_0", - "CLK_BUFG_REBUF_WL1END1_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC30", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", - "CLK_BUFG_REBUF_NE2A2_1", - "CLK_BUFG_REBUF_CK_GCLK27_BOT", - "CLK_BUFG_REBUF_EE2A3_1", - "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", - "CLK_BUFG_REBUF_EE4B2_0", - "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", - "GCLK15_14_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_LH9_1", - "GCLK17_16_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_CK_GCLK28_TOP", - "CLK_BUFG_REBUF_EE4BEG1_0", - "CLK_BUFG_REBUF_NW4END2_0", - "GCLK24_25_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_CK_BUFG_CASC0", - "CLK_BUFG_REBUF_LH11_0", - "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", - "CLK_BUFG_REBUF_WW4B0_0", - "CLK_BUFG_REBUF_NE4C3_1", - "CLK_BUFG_REBUF_MONITOR_P_0", - "CLK_BUFG_REBUF_EL1BEG2_1", - "CLK_BUFG_REBUF_WW2A1_0", - "CLK_BUFG_REBUF_EE4B0_1", - "CLK_BUFG_REBUF_CK_GCLK6_TOP", - "CLK_BUFG_REBUF_CK_GCLK1_BOT", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", - "CLK_BUFG_REBUF_NE4C1_0", - "CLK_BUFG_REBUF_WW4END2_1", - "CLK_BUFG_REBUF_SW2A3_1", - "CLK_BUFG_REBUF_EE4C1_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC23", - "CLK_BUFG_REBUF_CK_GCLK17_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", - "GCLK1_0_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_CK_GCLK9_TOP", - "CLK_BUFG_REBUF_SW4A0_0", - "CLK_BUFG_REBUF_EE2A1_0", - "CLK_BUFG_REBUF_SE4BEG3_0", - "CLK_BUFG_REBUF_SW2A2_0", - "CLK_BUFG_REBUF_EE4B3_0", - "CLK_BUFG_REBUF_SW2A3_0", - "CLK_BUFG_REBUF_NW2A3_1", - "CLK_BUFG_REBUF_NE4C2_0", - "CLK_BUFG_REBUF_EL1BEG0_1", - "CLK_BUFG_REBUF_CK_GCLK19_BOT", - "CLK_BUFG_REBUF_EE2A0_1", - "GCLK8_9_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_WW4C2_1", - "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", - "CLK_BUFG_REBUF_MONITOR_N_1", - "CLK_BUFG_REBUF_NW4A0_1", - "CLK_BUFG_REBUF_SE4C3_1", - "CLK_BUFG_REBUF_CK_GCLK31_TOP", - "CLK_BUFG_REBUF_CK_BUFG_CASC13", - "GCLK8_9_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", - "CLK_BUFG_REBUF_NW4A2_1", - "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", - "GCLK15_14_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_WW4B2_1", - "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", - "CLK_BUFG_REBUF_WL1END0_0", - "GCLK28_29_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_NW2A1_0", - "CLK_BUFG_REBUF_EE2A1_1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", - "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", - "CLK_BUFG_REBUF_EE4A3_1", - "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", - "GCLK22_23_DN_TEST_RING_OUT", - "GCLK18_19_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_WW4A1_0", - "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", - "CLK_BUFG_REBUF_NE2A2_0", - "CLK_BUFG_REBUF_CK_BUFG_CASC7", - "CLK_BUFG_REBUF_LH4_1", - "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", - "CLK_BUFG_REBUF_WW2A0_0", - "CLK_BUFG_REBUF_CK_GCLK3_BOT", - "CLK_BUFG_REBUF_CK_GCLK23_TOP", - "CLK_BUFG_REBUF_CK_GCLK11_BOT", - "CLK_BUFG_REBUF_WW4C3_0", - "CLK_BUFG_REBUF_NW4END0_0", - "CLK_BUFG_REBUF_SW4END2_0", - "CLK_BUFG_REBUF_NE4BEG1_1", - "CLK_BUFG_REBUF_EE4BEG2_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC28", - "CLK_BUFG_REBUF_CK_GCLK25_BOT", - "CLK_BUFG_REBUF_EL1BEG2_0", - "CLK_BUFG_REBUF_EE4C2_0", - "CLK_BUFG_REBUF_MONITOR_N_0", - "CLK_BUFG_REBUF_CK_GCLK12_TOP", - "CLK_BUFG_REBUF_CK_BUFG_CASC15", - "CLK_BUFG_REBUF_SW4A2_1", - "CLK_BUFG_REBUF_CK_GCLK21_TOP", - "CLK_BUFG_REBUF_NW4A2_0", - "CLK_BUFG_REBUF_SE4C0_0", - "CLK_BUFG_REBUF_EE4A0_0", - "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", - "CLK_BUFG_REBUF_NW4END1_1", - "CLK_BUFG_REBUF_WW2A1_1", - "CLK_BUFG_REBUF_CK_GCLK8_TOP", - "CLK_BUFG_REBUF_EE2A2_1", - "CLK_BUFG_REBUF_CK_GCLK15_TOP", - "CLK_BUFG_REBUF_EL1BEG3_0", - "GCLK23_22_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_CK_BUFG_CASC4", - "GCLK27_26_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_CK_BUFG_CASC2", - "CLK_BUFG_REBUF_ER1BEG3_1", - "CLK_BUFG_REBUF_SW4END0_0", - "CLK_BUFG_REBUF_EE4A2_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC5", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", - "CLK_BUFG_REBUF_SE4C3_0", - "CLK_BUFG_REBUF_SW4A2_0", - "CLK_BUFG_REBUF_SE4BEG1_1", - "CLK_BUFG_REBUF_SW4A3_0", - "CLK_BUFG_REBUF_WW4A3_1", - "CLK_BUFG_REBUF_EE2BEG0_0", - "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", - "CLK_BUFG_REBUF_WW4END3_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC24", - "GCLK29_28_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_CK_GCLK4_TOP", - "CLK_BUFG_REBUF_EE4B1_1", - "CLK_BUFG_REBUF_NE4BEG3_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC1", - "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", - "CLK_BUFG_REBUF_ER1BEG2_0", - "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", - "CLK_BUFG_REBUF_CK_GCLK19_TOP", - "CLK_BUFG_REBUF_SW4END2_1", - "GCLK13_12_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_NE4BEG0_0", - "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", - "GCLK4_5_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", - "GCLK20_21_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_WR1END2_0", - "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", - "CLK_BUFG_REBUF_NW2A3_0", - "GCLK3_2_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_CK_BUFG_CASC16", - "CLK_BUFG_REBUF_WR1END2_1", - "GCLK17_16_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_NE2A1_1", - "CLK_BUFG_REBUF_SE2A3_1", - "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", - "CLK_BUFG_REBUF_WW4END0_0", - "CLK_BUFG_REBUF_EE2BEG0_1", - "CLK_BUFG_REBUF_CK_GCLK20_TOP", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", - "CLK_BUFG_REBUF_CK_GCLK16_BOT", - "CLK_BUFG_REBUF_WW4C2_0", - "CLK_BUFG_REBUF_EE4BEG0_1", - "CLK_BUFG_REBUF_NE2A0_1", - "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", - "CLK_BUFG_REBUF_SE4C1_0", - "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", - "CLK_BUFG_REBUF_WW4A1_1", - "CLK_BUFG_REBUF_SW4END3_1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", - "CLK_BUFG_REBUF_CK_GCLK29_TOP", - "GCLK7_6_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_SE2A1_0", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", - "CLK_BUFG_REBUF_CK_GCLK30_TOP", - "CLK_BUFG_REBUF_NW4END0_1", - "GCLK13_12_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", - "GCLK11_10_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_NE4C2_1", - "CLK_BUFG_REBUF_NW4A1_0", - "CLK_BUFG_REBUF_EE2BEG2_0", - "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", - "CLK_BUFG_REBUF_LH1_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC10", - "GCLK10_11_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_SW2A0_1", - "CLK_BUFG_REBUF_WW2A2_1", - "CLK_BUFG_REBUF_CK_GCLK22_TOP", - "CLK_BUFG_REBUF_CK_BUFG_CASC6", - "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", - "CLK_BUFG_REBUF_WW4C0_1", - "CLK_BUFG_REBUF_ER1BEG1_0", - "CLK_BUFG_REBUF_SE4BEG3_1", - "CLK_BUFG_REBUF_WW4END2_0", - "CLK_BUFG_REBUF_CK_GCLK5_BOT", - "CLK_BUFG_REBUF_NW2A0_0", - "CLK_BUFG_REBUF_CK_GCLK0_BOT", - "CLK_BUFG_REBUF_NW4A1_1", - "CLK_BUFG_REBUF_WW4A2_0", - "CLK_BUFG_REBUF_CK_GCLK8_BOT", - "GCLK16_17_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", - "GCLK11_10_UP_TEST_RING_OUT", - "GCLK5_4_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", - "CLK_BUFG_REBUF_NW4A3_1", - "CLK_BUFG_REBUF_SW4A0_1", - "CLK_BUFG_REBUF_SW4END1_0", - "CLK_BUFG_REBUF_CK_GCLK10_BOT", - "CLK_BUFG_REBUF_NW4END1_0", - "CLK_BUFG_REBUF_CK_GCLK26_TOP", - "GCLK7_6_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_NE2A3_1", - "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", - "CLK_BUFG_REBUF_CK_BUFG_CASC11", - "CLK_BUFG_REBUF_EE4BEG2_0", - "CLK_BUFG_REBUF_SE2A3_0", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", - "CLK_BUFG_REBUF_LH10_1", - "GCLK30_31_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_SE4BEG1_0", - "CLK_BUFG_REBUF_LH8_0", - "CLK_BUFG_REBUF_LH3_0", - "GCLK31_30_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_NW2A2_0", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", - "CLK_BUFG_REBUF_CK_GCLK25_TOP", - "CLK_BUFG_REBUF_CK_GCLK18_TOP", - "CLK_BUFG_REBUF_CK_GCLK23_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", - "CLK_BUFG_REBUF_CK_BUFG_CASC12", - "CLK_BUFG_REBUF_EE4BEG3_0", - "GCLK27_26_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_SW2A1_0", - "CLK_BUFG_REBUF_SE4BEG0_1", - "CLK_BUFG_REBUF_LH7_1", - "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", - "CLK_BUFG_REBUF_SE4BEG2_0", - "CLK_BUFG_REBUF_WW2A3_0", - "CLK_BUFG_REBUF_WW2A3_1", - "CLK_BUFG_REBUF_EE2A0_0", - "CLK_BUFG_REBUF_CK_BUFG_CASC22", - "CLK_BUFG_REBUF_NW2A2_1", - "GCLK3_2_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", - "CLK_BUFG_REBUF_EE2A3_0", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", - "CLK_BUFG_REBUF_CK_BUFG_CASC26", - "CLK_BUFG_REBUF_CK_GCLK7_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", - "GCLK12_13_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_WW4A3_0", - "CLK_BUFG_REBUF_WW4C0_0", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", - "CLK_BUFG_REBUF_WW4A0_0", - "CLK_BUFG_REBUF_WR1END3_0", - "CLK_BUFG_REBUF_LH8_1", - "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", - "GCLK2_3_DN_TEST_RING_OUT", - "CLK_BUFG_REBUF_WW2END3_1", - "CLK_BUFG_REBUF_SE4BEG0_0", - "GCLK26_27_DN_TEST_RING_IN", - "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", - "CLK_BUFG_REBUF_CK_BUFG_CASC29", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", - "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", - "CLK_BUFG_REBUF_CK_GCLK17_TOP", - "CLK_BUFG_REBUF_SE2A2_0", - "CLK_BUFG_REBUF_WL1END2_0", - "CLK_BUFG_REBUF_SE2A0_0", - "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", - "GCLK29_28_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_CK_GCLK29_BOT", - "CLK_BUFG_REBUF_NE4BEG3_0", - "CLK_BUFG_REBUF_CK_GCLK26_BOT", - "CLK_BUFG_REBUF_WW2END1_1", - "CLK_BUFG_REBUF_EE2BEG2_1", - "CLK_BUFG_REBUF_EE4BEG3_1", - "CLK_BUFG_REBUF_WW4C1_1", - "CLK_BUFG_REBUF_CK_GCLK10_TOP", - "CLK_BUFG_REBUF_EE4C2_1", - "CLK_BUFG_REBUF_SW4END3_0", - "CLK_BUFG_REBUF_LH12_0", - "CLK_BUFG_REBUF_EL1BEG0_0", - "CLK_BUFG_REBUF_CK_GCLK15_BOT", - "CLK_BUFG_REBUF_CK_GCLK16_TOP", - "GCLK25_24_UP_TEST_RING_IN", - "GCLK5_4_UP_TEST_RING_IN", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", - "CLK_BUFG_REBUF_CK_BUFG_CASC8", - "CLK_BUFG_REBUF_ER1BEG1_1", - "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", - "CLK_BUFG_REBUF_CK_GCLK31_BOT", - "CLK_BUFG_REBUF_LH6_0", - "CLK_BUFG_REBUF_SE4C2_0", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", - "CLK_BUFG_REBUF_WR1END0_0", - "GCLK31_30_UP_TEST_RING_OUT", - "CLK_BUFG_REBUF_EE4B0_0", - "CLK_BUFG_REBUF_WL1END3_0", - "CLK_BUFG_REBUF_WW4C3_1", - "CLK_BUFG_REBUF_LH6_1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", - "CLK_BUFG_REBUF_WW4C1_0", - "CLK_BUFG_REBUF_SE4C2_1", - "CLK_BUFG_REBUF_WR1END3_1", - "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", - "CLK_BUFG_REBUF_EE4BEG1_1", - "CLK_BUFG_REBUF_CK_BUFG_CASC3", - "CLK_BUFG_REBUF_CK_GCLK3_TOP", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", - "CLK_BUFG_REBUF_CK_GCLK2_TOP", - "CLK_BUFG_REBUF_CK_GCLK11_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK21_TOP" - ], - "sites": [], "pips": { - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { + "CLK_BUFG_REBUF.GCLK0_1_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK1_BOT": { "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK19_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP->>GCLK29_28_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK29_28_UP_TEST_RING_IN", + "src_wire": "GCLK0_1_DN_TEST_RING_OUT", "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK14_15_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK15_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", - "is_directional": "1", - "src_wire": "GCLK14_15_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP->>GCLK31_30_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK31_30_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK17_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT->>GCLK28_29_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK28_29_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK7_6_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", - "is_directional": "1", - "src_wire": "GCLK7_6_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK13_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK20_21_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK21_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", - "is_directional": "1", - "src_wire": "GCLK20_21_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT->>GCLK22_23_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK22_23_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT->>GCLK10_11_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK10_11_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK3_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK1_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT->>GCLK0_1_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK0_1_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT->>GCLK2_3_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK2_3_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_TOP->>GCLK25_24_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK25_24_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_TOP->>GCLK15_14_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK15_14_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK15_14_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", - "is_directional": "1", - "src_wire": "GCLK15_14_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK4_5_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK5_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", - "is_directional": "1", - "src_wire": "GCLK4_5_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT->>GCLK20_21_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK20_21_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK13_12_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", - "is_directional": "1", - "src_wire": "GCLK13_12_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK18_19_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK19_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", - "is_directional": "1", - "src_wire": "GCLK18_19_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT->>GCLK30_31_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK30_31_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK12_13_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK13_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", - "is_directional": "1", - "src_wire": "GCLK12_13_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT->>GCLK4_5_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK4_5_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK16_17_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK17_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", - "is_directional": "1", - "src_wire": "GCLK16_17_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK29_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT->>GCLK6_7_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK6_7_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK10_11_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK11_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", - "is_directional": "1", - "src_wire": "GCLK10_11_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK9_8_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", - "is_directional": "1", - "src_wire": "GCLK9_8_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK27_26_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", - "is_directional": "1", - "src_wire": "GCLK27_26_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK30_31_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK31_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", - "is_directional": "1", - "src_wire": "GCLK30_31_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK11_10_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", - "is_directional": "1", - "src_wire": "GCLK11_10_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT->>GCLK16_17_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK16_17_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT" }, "CLK_BUFG_REBUF.GCLK24_25_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK25_BOT": { "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", - "is_directional": "1", "src_wire": "GCLK24_25_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK21_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT->>GCLK14_15_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK14_15_DN_TEST_RING_IN", "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK9_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK25_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK15_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP->>GCLK5_4_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK5_4_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT->>GCLK24_25_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK24_25_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK0_1_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK1_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", - "is_directional": "1", - "src_wire": "GCLK0_1_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP->>GCLK7_6_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK7_6_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP->>GCLK19_18_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK19_18_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_TOP->>GCLK27_26_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK27_26_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK5_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK22_23_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK23_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", - "is_directional": "1", - "src_wire": "GCLK22_23_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_TOP->>GCLK11_10_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK11_10_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK2_3_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK3_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", - "is_directional": "1", - "src_wire": "GCLK2_3_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_TOP->>GCLK23_22_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK23_22_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT->>GCLK26_27_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK26_27_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP->>GCLK3_2_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK3_2_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_TOP->>GCLK21_20_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK21_20_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK27_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP->>GCLK9_8_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK9_8_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK17_16_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", - "is_directional": "1", - "src_wire": "GCLK17_16_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK23_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK29_28_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", - "is_directional": "1", - "src_wire": "GCLK29_28_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK28_29_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK29_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", - "is_directional": "1", - "src_wire": "GCLK28_29_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT->>GCLK18_19_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK18_19_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK1_0_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", - "is_directional": "1", - "src_wire": "GCLK1_0_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK11_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK23_22_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", - "is_directional": "1", - "src_wire": "GCLK23_22_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK18_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK6_7_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK7_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", - "is_directional": "1", - "src_wire": "GCLK6_7_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK7_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK21_20_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", - "is_directional": "1", - "src_wire": "GCLK21_20_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK8_9_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK9_BOT": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", - "is_directional": "1", - "src_wire": "GCLK8_9_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT->>GCLK8_9_DN_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK8_9_DN_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK31_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK3_2_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", - "is_directional": "1", - "src_wire": "GCLK3_2_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_TOP->>GCLK17_16_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK17_16_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP->>GCLK1_0_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK1_0_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", - "is_directional": "0", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_TOP->>GCLK13_12_UP_TEST_RING_IN": { - "can_invert": "0", - "dst_wire": "GCLK13_12_UP_TEST_RING_IN", - "is_directional": "1", - "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK25_24_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", - "is_directional": "1", - "src_wire": "GCLK25_24_UP_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK5_4_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", - "is_directional": "1", - "src_wire": "GCLK5_4_UP_TEST_RING_OUT", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT->>GCLK12_13_DN_TEST_RING_IN": { "can_invert": "0", - "dst_wire": "GCLK12_13_DN_TEST_RING_IN", - "is_directional": "1", "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK12_13_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK16_17_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK17_BOT": { + "can_invert": "0", + "src_wire": "GCLK16_17_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT" }, "CLK_BUFG_REBUF.GCLK26_27_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK27_BOT": { "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", - "is_directional": "1", "src_wire": "GCLK26_27_DN_TEST_RING_OUT", - "is_pseudo": "0" - }, - "CLK_BUFG_REBUF.GCLK31_30_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", "is_directional": "1", - "src_wire": "GCLK31_30_UP_TEST_RING_OUT", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT->>GCLK24_25_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK24_25_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK29_28_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { + "can_invert": "0", + "src_wire": "GCLK29_28_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT->>GCLK26_27_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK26_27_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT->>GCLK4_5_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK4_5_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP" + }, + "CLK_BUFG_REBUF.GCLK18_19_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK19_BOT": { + "can_invert": "0", + "src_wire": "GCLK18_19_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT" + }, + "CLK_BUFG_REBUF.GCLK8_9_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK9_BOT": { + "can_invert": "0", + "src_wire": "GCLK8_9_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP" + }, + "CLK_BUFG_REBUF.GCLK17_16_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { + "can_invert": "0", + "src_wire": "GCLK17_16_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP" + }, + "CLK_BUFG_REBUF.GCLK10_11_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK11_BOT": { + "can_invert": "0", + "src_wire": "GCLK10_11_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT->>GCLK18_19_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK18_19_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK5_4_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { + "can_invert": "0", + "src_wire": "GCLK5_4_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK18_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP" + }, + "CLK_BUFG_REBUF.GCLK28_29_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK29_BOT": { + "can_invert": "0", + "src_wire": "GCLK28_29_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_TOP->>GCLK11_10_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK11_10_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT->>GCLK8_9_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK8_9_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK14_15_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK15_BOT": { + "can_invert": "0", + "src_wire": "GCLK14_15_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT->>GCLK30_31_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK30_31_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_TOP->>GCLK23_22_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK23_22_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK13_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT->>GCLK14_15_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK14_15_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK4_5_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK5_BOT": { + "can_invert": "0", + "src_wire": "GCLK4_5_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK5_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT->>GCLK10_11_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK10_11_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT->>GCLK16_17_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK16_17_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_TOP->>GCLK27_26_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK27_26_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK23_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP" + }, + "CLK_BUFG_REBUF.GCLK13_12_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { + "can_invert": "0", + "src_wire": "GCLK13_12_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP" + }, + "CLK_BUFG_REBUF.GCLK9_8_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { + "can_invert": "0", + "src_wire": "GCLK9_8_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK21_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP->>GCLK5_4_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK5_4_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK1_0_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { + "can_invert": "0", + "src_wire": "GCLK1_0_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT->>GCLK2_3_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK2_3_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT->>GCLK0_1_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK0_1_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK25_24_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { + "can_invert": "0", + "src_wire": "GCLK25_24_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP->>GCLK19_18_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK19_18_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_TOP->>GCLK13_12_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK13_12_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK20_21_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK21_BOT": { + "can_invert": "0", + "src_wire": "GCLK20_21_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT" + }, + "CLK_BUFG_REBUF.GCLK3_2_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { + "can_invert": "0", + "src_wire": "GCLK3_2_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP->>GCLK3_2_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK3_2_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP->>GCLK7_6_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK7_6_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_TOP->>GCLK17_16_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK17_16_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP->>GCLK29_28_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK29_28_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK11_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK31_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP" }, "CLK_BUFG_REBUF.GCLK19_18_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK18_TOP": { "can_invert": "0", - "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", - "is_directional": "1", "src_wire": "GCLK19_18_UP_TEST_RING_OUT", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT->>GCLK22_23_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK22_23_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP->>GCLK31_30_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK31_30_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT->>GCLK6_7_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK6_7_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK22_23_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK23_BOT": { + "can_invert": "0", + "src_wire": "GCLK22_23_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK29_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_TOP->>GCLK15_14_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK15_14_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT->>GCLK20_21_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK20_21_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK25_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK27_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP" + }, + "CLK_BUFG_REBUF.GCLK6_7_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK7_BOT": { + "can_invert": "0", + "src_wire": "GCLK6_7_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT->>GCLK28_29_DN_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK28_29_DN_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK2_3_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK3_BOT": { + "can_invert": "0", + "src_wire": "GCLK2_3_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK3_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP" + }, + "CLK_BUFG_REBUF.GCLK21_20_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { + "can_invert": "0", + "src_wire": "GCLK21_20_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP" + }, + "CLK_BUFG_REBUF.GCLK12_13_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK13_BOT": { + "can_invert": "0", + "src_wire": "GCLK12_13_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK15_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK9_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP" + }, + "CLK_BUFG_REBUF.GCLK23_22_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { + "can_invert": "0", + "src_wire": "GCLK23_22_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP" + }, + "CLK_BUFG_REBUF.GCLK15_14_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { + "can_invert": "0", + "src_wire": "GCLK15_14_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_TOP->>GCLK25_24_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK25_24_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP" + }, + "CLK_BUFG_REBUF.GCLK30_31_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK31_BOT": { + "can_invert": "0", + "src_wire": "GCLK30_31_DN_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP->>GCLK9_8_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK9_8_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP" + }, + "CLK_BUFG_REBUF.GCLK27_26_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { + "can_invert": "0", + "src_wire": "GCLK27_26_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK17_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_TOP->>GCLK21_20_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK21_20_UP_TEST_RING_IN" + }, + "CLK_BUFG_REBUF.GCLK7_6_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { + "can_invert": "0", + "src_wire": "GCLK7_6_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK19_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK1_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP" + }, + "CLK_BUFG_REBUF.GCLK31_30_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { + "can_invert": "0", + "src_wire": "GCLK31_30_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP" + }, + "CLK_BUFG_REBUF.GCLK11_10_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { + "can_invert": "0", + "src_wire": "GCLK11_10_UP_TEST_RING_OUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK7_TOP": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP" + }, + "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP->>GCLK1_0_UP_TEST_RING_IN": { + "can_invert": "0", + "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK1_0_UP_TEST_RING_IN" } }, - "tile_type": "CLK_BUFG_REBUF" + "wires": [ + "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", + "CLK_BUFG_REBUF_CK_GCLK0_TOP", + "CLK_BUFG_REBUF_CK_GCLK5_BOT", + "CLK_BUFG_REBUF_LH4_0", + "GCLK10_11_DN_TEST_RING_OUT", + "GCLK27_26_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", + "GCLK25_24_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_GCLK25_BOT", + "CLK_BUFG_REBUF_NE2A3_0", + "CLK_BUFG_REBUF_SW4END0_1", + "CLK_BUFG_REBUF_CK_GCLK26_BOT", + "CLK_BUFG_REBUF_EE4A2_0", + "CLK_BUFG_REBUF_EE4A1_0", + "GCLK23_22_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_EE2BEG2_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC6", + "CLK_BUFG_REBUF_CK_GCLK13_BOT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", + "CLK_BUFG_REBUF_CK_BUFG_CASC30", + "CLK_BUFG_REBUF_CK_GCLK19_BOT", + "CLK_BUFG_REBUF_SE2A1_0", + "CLK_BUFG_REBUF_NE2A0_0", + "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", + "CLK_BUFG_REBUF_WL1END2_0", + "CLK_BUFG_REBUF_WW4END0_0", + "CLK_BUFG_REBUF_CK_GCLK15_TOP", + "CLK_BUFG_REBUF_SE4C1_0", + "CLK_BUFG_REBUF_SE4BEG1_0", + "GCLK25_24_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_SW2A0_0", + "CLK_BUFG_REBUF_SW2A0_1", + "CLK_BUFG_REBUF_LH1_0", + "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", + "CLK_BUFG_REBUF_NE4C0_1", + "CLK_BUFG_REBUF_LH5_0", + "CLK_BUFG_REBUF_CK_GCLK2_TOP", + "CLK_BUFG_REBUF_WW2A3_0", + "CLK_BUFG_REBUF_EE2BEG3_0", + "CLK_BUFG_REBUF_WL1END1_0", + "CLK_BUFG_REBUF_CK_GCLK27_BOT", + "CLK_BUFG_REBUF_LH3_1", + "CLK_BUFG_REBUF_WR1END1_1", + "CLK_BUFG_REBUF_SE4BEG3_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", + "CLK_BUFG_REBUF_NE4C0_0", + "CLK_BUFG_REBUF_CK_BUFG_CASC4", + "CLK_BUFG_REBUF_WW4C1_0", + "CLK_BUFG_REBUF_SW4END1_1", + "CLK_BUFG_REBUF_CK_GCLK11_TOP", + "CLK_BUFG_REBUF_WW4B3_0", + "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", + "CLK_BUFG_REBUF_NW4END1_1", + "CLK_BUFG_REBUF_WR1END1_0", + "CLK_BUFG_REBUF_CK_GCLK13_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", + "CLK_BUFG_REBUF_CK_GCLK10_TOP", + "CLK_BUFG_REBUF_ER1BEG1_1", + "CLK_BUFG_REBUF_ER1BEG3_1", + "CLK_BUFG_REBUF_LH3_0", + "CLK_BUFG_REBUF_WW4A0_1", + "GCLK17_16_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_GCLK22_BOT", + "CLK_BUFG_REBUF_CK_GCLK12_BOT", + "CLK_BUFG_REBUF_NE4BEG1_1", + "CLK_BUFG_REBUF_EE4A1_1", + "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", + "GCLK16_17_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_EE2BEG0_1", + "CLK_BUFG_REBUF_WR1END2_0", + "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", + "CLK_BUFG_REBUF_CK_BUFG_CASC15", + "CLK_BUFG_REBUF_CK_GCLK11_BOT", + "CLK_BUFG_REBUF_WW4END3_1", + "CLK_BUFG_REBUF_ER1BEG2_1", + "CLK_BUFG_REBUF_EE2A0_1", + "CLK_BUFG_REBUF_EE4BEG3_0", + "CLK_BUFG_REBUF_NW4END3_0", + "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", + "CLK_BUFG_REBUF_EE4BEG1_1", + "CLK_BUFG_REBUF_CK_GCLK18_TOP", + "CLK_BUFG_REBUF_WW2A1_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC31", + "CLK_BUFG_REBUF_MONITOR_N_0", + "CLK_BUFG_REBUF_NE4C2_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC18", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", + "GCLK31_30_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_BUFG_CASC7", + "CLK_BUFG_REBUF_CK_GCLK8_TOP", + "GCLK7_6_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_EE2A0_0", + "CLK_BUFG_REBUF_WL1END0_1", + "GCLK8_9_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_GCLK30_TOP", + "CLK_BUFG_REBUF_SW4END0_0", + "CLK_BUFG_REBUF_EE2BEG0_0", + "CLK_BUFG_REBUF_ER1BEG2_0", + "GCLK6_7_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_NE4C2_0", + "CLK_BUFG_REBUF_WW2END1_1", + "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", + "CLK_BUFG_REBUF_CK_GCLK14_TOP", + "CLK_BUFG_REBUF_CK_GCLK17_TOP", + "CLK_BUFG_REBUF_NE4BEG2_0", + "CLK_BUFG_REBUF_NW2A1_1", + "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", + "CLK_BUFG_REBUF_WW4A3_1", + "CLK_BUFG_REBUF_CK_GCLK23_TOP", + "CLK_BUFG_REBUF_NW2A3_1", + "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", + "CLK_BUFG_REBUF_SE4BEG2_1", + "GCLK29_28_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", + "CLK_BUFG_REBUF_SW4END3_1", + "CLK_BUFG_REBUF_EE4C3_1", + "GCLK11_10_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_WW4A1_1", + "CLK_BUFG_REBUF_EE4B0_1", + "CLK_BUFG_REBUF_SE2A3_1", + "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", + "CLK_BUFG_REBUF_NE4BEG3_1", + "CLK_BUFG_REBUF_LH9_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", + "CLK_BUFG_REBUF_CK_GCLK25_TOP", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", + "CLK_BUFG_REBUF_EE2A2_0", + "CLK_BUFG_REBUF_WW2A2_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", + "GCLK2_3_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_SW4END2_1", + "CLK_BUFG_REBUF_EE4BEG3_1", + "GCLK22_23_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_WW4B0_1", + "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", + "GCLK5_4_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_GCLK4_BOT", + "CLK_BUFG_REBUF_EE4A0_0", + "CLK_BUFG_REBUF_NE4BEG0_0", + "CLK_BUFG_REBUF_EE2BEG1_0", + "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", + "CLK_BUFG_REBUF_NE4C3_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", + "CLK_BUFG_REBUF_CK_GCLK22_TOP", + "GCLK27_26_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_SW4A2_0", + "CLK_BUFG_REBUF_SW4END3_0", + "CLK_BUFG_REBUF_WR1END3_1", + "CLK_BUFG_REBUF_LH6_1", + "GCLK8_9_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_NW4A2_0", + "CLK_BUFG_REBUF_WW4C2_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC0", + "CLK_BUFG_REBUF_EE4C0_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC23", + "GCLK1_0_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_WW4END2_1", + "CLK_BUFG_REBUF_WR1END3_0", + "CLK_BUFG_REBUF_CK_GCLK2_BOT", + "CLK_BUFG_REBUF_EL1BEG1_1", + "CLK_BUFG_REBUF_SW2A1_1", + "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", + "GCLK1_0_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", + "CLK_BUFG_REBUF_WW4A3_0", + "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", + "CLK_BUFG_REBUF_NW4A0_0", + "GCLK18_19_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", + "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", + "CLK_BUFG_REBUF_NE2A2_1", + "CLK_BUFG_REBUF_WW4C3_1", + "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", + "GCLK15_14_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_GCLK3_TOP", + "CLK_BUFG_REBUF_NW2A2_1", + "GCLK28_29_DN_TEST_RING_OUT", + "GCLK29_28_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_EE4BEG0_0", + "CLK_BUFG_REBUF_WW4C1_1", + "CLK_BUFG_REBUF_SE4C2_1", + "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", + "CLK_BUFG_REBUF_NW4A2_1", + "CLK_BUFG_REBUF_EL1BEG0_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", + "GCLK14_15_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_WW2END0_0", + "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", + "CLK_BUFG_REBUF_CK_GCLK20_TOP", + "CLK_BUFG_REBUF_EE4C1_0", + "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", + "CLK_BUFG_REBUF_LH10_0", + "CLK_BUFG_REBUF_CK_GCLK20_BOT", + "GCLK24_25_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_WW4C0_0", + "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", + "CLK_BUFG_REBUF_WW4B3_1", + "CLK_BUFG_REBUF_WW4A2_0", + "CLK_BUFG_REBUF_NW2A2_0", + "CLK_BUFG_REBUF_SE2A3_0", + "CLK_BUFG_REBUF_WW4C0_1", + "CLK_BUFG_REBUF_EL1BEG3_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", + "CLK_BUFG_REBUF_NE4BEG3_0", + "CLK_BUFG_REBUF_SW4A0_1", + "CLK_BUFG_REBUF_WW4END1_1", + "CLK_BUFG_REBUF_CK_GCLK16_BOT", + "CLK_BUFG_REBUF_NW4END2_1", + "CLK_BUFG_REBUF_CK_GCLK18_BOT", + "GCLK20_21_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", + "CLK_BUFG_REBUF_NE4BEG1_0", + "CLK_BUFG_REBUF_EL1BEG3_0", + "CLK_BUFG_REBUF_SW4A3_1", + "CLK_BUFG_REBUF_WR1END0_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", + "CLK_BUFG_REBUF_WL1END3_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", + "GCLK17_16_UP_TEST_RING_IN", + "GCLK0_1_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_WW4END0_1", + "CLK_BUFG_REBUF_CK_GCLK26_TOP", + "GCLK21_20_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_GCLK12_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", + "CLK_BUFG_REBUF_WR1END0_1", + "CLK_BUFG_REBUF_EE4BEG1_0", + "CLK_BUFG_REBUF_WW4B1_0", + "CLK_BUFG_REBUF_CK_GCLK14_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", + "CLK_BUFG_REBUF_EE2BEG3_1", + "CLK_BUFG_REBUF_NE4BEG2_1", + "CLK_BUFG_REBUF_SW4A1_1", + "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", + "GCLK13_12_UP_TEST_RING_OUT", + "GCLK23_22_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_WW4B2_0", + "CLK_BUFG_REBUF_WW2END2_1", + "CLK_BUFG_REBUF_EE2A1_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC9", + "CLK_BUFG_REBUF_SE4C3_1", + "CLK_BUFG_REBUF_WW4END2_0", + "CLK_BUFG_REBUF_CK_GCLK29_TOP", + "CLK_BUFG_REBUF_CK_GCLK28_BOT", + "CLK_BUFG_REBUF_CK_BUFG_CASC24", + "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", + "CLK_BUFG_REBUF_CK_GCLK30_BOT", + "CLK_BUFG_REBUF_CK_GCLK3_BOT", + "GCLK6_7_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_WW2A0_1", + "CLK_BUFG_REBUF_WW4C2_0", + "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", + "GCLK13_12_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_BUFG_CASC28", + "CLK_BUFG_REBUF_LH7_0", + "CLK_BUFG_REBUF_NW2A1_0", + "CLK_BUFG_REBUF_LH9_1", + "CLK_BUFG_REBUF_EE4B0_0", + "CLK_BUFG_REBUF_EE4C2_0", + "CLK_BUFG_REBUF_CK_GCLK27_TOP", + "CLK_BUFG_REBUF_CK_BUFG_CASC27", + "CLK_BUFG_REBUF_NW4A3_1", + "GCLK9_8_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_EE4B2_1", + "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", + "CLK_BUFG_REBUF_SE4BEG2_0", + "GCLK7_6_UP_TEST_RING_OUT", + "GCLK30_31_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_EE4A3_0", + "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", + "GCLK15_14_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_SW2A2_0", + "CLK_BUFG_REBUF_SW2A3_1", + "GCLK20_21_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_EE4BEG2_0", + "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", + "GCLK0_1_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_SW4A1_0", + "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", + "CLK_BUFG_REBUF_NE2A1_1", + "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", + "CLK_BUFG_REBUF_SW4END1_0", + "CLK_BUFG_REBUF_CK_GCLK8_BOT", + "CLK_BUFG_REBUF_CK_GCLK17_BOT", + "CLK_BUFG_REBUF_CK_GCLK7_BOT", + "CLK_BUFG_REBUF_CK_GCLK31_BOT", + "CLK_BUFG_REBUF_EE4B3_0", + "CLK_BUFG_REBUF_WW2A3_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC17", + "CLK_BUFG_REBUF_CK_BUFG_CASC14", + "CLK_BUFG_REBUF_CK_GCLK9_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", + "CLK_BUFG_REBUF_WW4END1_0", + "CLK_BUFG_REBUF_EE2A3_1", + "CLK_BUFG_REBUF_EE2BEG1_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", + "CLK_BUFG_REBUF_WW4A0_0", + "CLK_BUFG_REBUF_WL1END3_0", + "CLK_BUFG_REBUF_NW4END2_0", + "GCLK10_11_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_ER1BEG1_0", + "GCLK16_17_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_NE4C1_1", + "CLK_BUFG_REBUF_WW4A2_1", + "CLK_BUFG_REBUF_NW2A0_1", + "CLK_BUFG_REBUF_LH11_0", + "CLK_BUFG_REBUF_MONITOR_P_0", + "CLK_BUFG_REBUF_SE4BEG3_0", + "CLK_BUFG_REBUF_EE2A1_0", + "CLK_BUFG_REBUF_MONITOR_N_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", + "CLK_BUFG_REBUF_CK_GCLK19_TOP", + "CLK_BUFG_REBUF_CK_BUFG_CASC10", + "CLK_BUFG_REBUF_CK_GCLK1_BOT", + "CLK_BUFG_REBUF_SE2A2_0", + "CLK_BUFG_REBUF_SE4BEG0_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", + "CLK_BUFG_REBUF_LH8_1", + "CLK_BUFG_REBUF_CK_GCLK21_BOT", + "CLK_BUFG_REBUF_ER1BEG0_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", + "GCLK28_29_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_GCLK5_TOP", + "GCLK9_8_UP_TEST_RING_OUT", + "GCLK31_30_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_BUFG_CASC21", + "CLK_BUFG_REBUF_NE2A1_0", + "CLK_BUFG_REBUF_LH7_1", + "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", + "CLK_BUFG_REBUF_WW4B1_1", + "CLK_BUFG_REBUF_EE4A0_1", + "CLK_BUFG_REBUF_LH2_1", + "CLK_BUFG_REBUF_EE4B2_0", + "CLK_BUFG_REBUF_NE2A0_1", + "CLK_BUFG_REBUF_EE4B3_1", + "CLK_BUFG_REBUF_CK_GCLK29_BOT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", + "CLK_BUFG_REBUF_EE2BEG2_0", + "CLK_BUFG_REBUF_CK_BUFG_CASC20", + "CLK_BUFG_REBUF_SW4A0_0", + "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", + "CLK_BUFG_REBUF_WW4A1_0", + "GCLK4_5_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_BUFG_CASC12", + "CLK_BUFG_REBUF_SE2A1_1", + "GCLK2_3_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_GCLK10_BOT", + "CLK_BUFG_REBUF_WW4B0_0", + "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", + "CLK_BUFG_REBUF_SE4C0_0", + "CLK_BUFG_REBUF_WW4C3_0", + "CLK_BUFG_REBUF_CK_GCLK21_TOP", + "CLK_BUFG_REBUF_CK_GCLK24_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", + "CLK_BUFG_REBUF_NE2A3_1", + "CLK_BUFG_REBUF_LH12_1", + "CLK_BUFG_REBUF_SE4BEG1_1", + "CLK_BUFG_REBUF_NE2A2_0", + "CLK_BUFG_REBUF_EL1BEG0_1", + "CLK_BUFG_REBUF_NW2A3_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", + "CLK_BUFG_REBUF_WL1END2_1", + "GCLK19_18_UP_TEST_RING_IN", + "GCLK30_31_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_LH4_1", + "CLK_BUFG_REBUF_SE2A2_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC3", + "CLK_BUFG_REBUF_CK_GCLK15_BOT", + "GCLK5_4_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_WW2END2_0", + "CLK_BUFG_REBUF_NW4END3_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", + "CLK_BUFG_REBUF_NW4END1_0", + "CLK_BUFG_REBUF_WW2END0_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC11", + "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", + "CLK_BUFG_REBUF_CK_BUFG_CASC8", + "CLK_BUFG_REBUF_EE4B1_0", + "CLK_BUFG_REBUF_CK_GCLK1_TOP", + "GCLK21_20_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_SE4C0_1", + "CLK_BUFG_REBUF_MONITOR_P_1", + "CLK_BUFG_REBUF_CK_GCLK9_TOP", + "GCLK3_2_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", + "CLK_BUFG_REBUF_LH5_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC13", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", + "GCLK24_25_DN_TEST_RING_OUT", + "GCLK26_27_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", + "CLK_BUFG_REBUF_EE4BEG2_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", + "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", + "CLK_BUFG_REBUF_EL1BEG1_0", + "CLK_BUFG_REBUF_WW2A2_1", + "CLK_BUFG_REBUF_SW4A3_0", + "GCLK12_13_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", + "CLK_BUFG_REBUF_CK_BUFG_CASC25", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", + "CLK_BUFG_REBUF_LH8_0", + "CLK_BUFG_REBUF_CK_BUFG_CASC16", + "CLK_BUFG_REBUF_WL1END0_0", + "CLK_BUFG_REBUF_EE4C3_0", + "CLK_BUFG_REBUF_CK_GCLK6_TOP", + "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", + "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", + "GCLK14_15_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_CK_BUFG_CASC26", + "CLK_BUFG_REBUF_WW2END1_0", + "CLK_BUFG_REBUF_EE2A2_1", + "CLK_BUFG_REBUF_LH12_0", + "CLK_BUFG_REBUF_CK_GCLK16_TOP", + "CLK_BUFG_REBUF_SE4C1_1", + "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", + "CLK_BUFG_REBUF_NW4END0_1", + "GCLK19_18_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_SW4A2_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", + "CLK_BUFG_REBUF_CK_BUFG_CASC2", + "CLK_BUFG_REBUF_EE4C2_1", + "GCLK26_27_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_SE4C2_0", + "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", + "CLK_BUFG_REBUF_LH6_0", + "CLK_BUFG_REBUF_WW2A0_0", + "CLK_BUFG_REBUF_SE2A0_1", + "CLK_BUFG_REBUF_NE4C1_0", + "CLK_BUFG_REBUF_WW2END3_1", + "CLK_BUFG_REBUF_EE4BEG0_1", + "CLK_BUFG_REBUF_CK_GCLK28_TOP", + "CLK_BUFG_REBUF_EE4A2_1", + "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", + "CLK_BUFG_REBUF_ER1BEG0_0", + "CLK_BUFG_REBUF_ER1BEG3_0", + "CLK_BUFG_REBUF_LH10_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", + "CLK_BUFG_REBUF_CK_GCLK31_TOP", + "CLK_BUFG_REBUF_CK_BUFG_CASC22", + "CLK_BUFG_REBUF_SE4C3_0", + "CLK_BUFG_REBUF_WW4END3_0", + "CLK_BUFG_REBUF_LH2_0", + "CLK_BUFG_REBUF_SW4END2_0", + "CLK_BUFG_REBUF_NW4A3_0", + "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", + "CLK_BUFG_REBUF_CK_BUFG_CASC1", + "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", + "CLK_BUFG_REBUF_CK_GCLK4_TOP", + "CLK_BUFG_REBUF_WW4B2_1", + "CLK_BUFG_REBUF_CK_BUFG_CASC5", + "CLK_BUFG_REBUF_CK_GCLK6_BOT", + "CLK_BUFG_REBUF_EL1BEG2_1", + "CLK_BUFG_REBUF_EE4C0_0", + "CLK_BUFG_REBUF_NW2A0_0", + "CLK_BUFG_REBUF_NE4BEG0_1", + "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", + "CLK_BUFG_REBUF_WR1END2_1", + "CLK_BUFG_REBUF_CK_GCLK7_TOP", + "CLK_BUFG_REBUF_WW2END3_0", + "CLK_BUFG_REBUF_EE2A3_0", + "CLK_BUFG_REBUF_NW4A1_1", + "CLK_BUFG_REBUF_NE4C3_1", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", + "CLK_BUFG_REBUF_LH11_1", + "CLK_BUFG_REBUF_NW4A1_0", + "CLK_BUFG_REBUF_CK_GCLK24_BOT", + "GCLK4_5_DN_TEST_RING_IN", + "GCLK12_13_DN_TEST_RING_OUT", + "CLK_BUFG_REBUF_CK_GCLK23_BOT", + "CLK_BUFG_REBUF_CK_BUFG_CASC29", + "GCLK18_19_DN_TEST_RING_OUT", + "GCLK3_2_UP_TEST_RING_IN", + "CLK_BUFG_REBUF_SE2A0_0", + "GCLK11_10_UP_TEST_RING_OUT", + "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", + "CLK_BUFG_REBUF_WW2A1_0", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", + "CLK_BUFG_REBUF_CK_BUFG_CASC19", + "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", + "CLK_BUFG_REBUF_SW2A2_1", + "CLK_BUFG_REBUF_EE4C1_1", + "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", + "CLK_BUFG_REBUF_NW4A0_1", + "CLK_BUFG_REBUF_NW4END0_0", + "CLK_BUFG_REBUF_EL1BEG2_0", + "CLK_BUFG_REBUF_SW2A1_0", + "CLK_BUFG_REBUF_WL1END1_1", + "GCLK22_23_DN_TEST_RING_IN", + "CLK_BUFG_REBUF_EE4B1_1", + "CLK_BUFG_REBUF_SW2A3_0", + "CLK_BUFG_REBUF_EE4A3_1", + "CLK_BUFG_REBUF_LH1_1", + "CLK_BUFG_REBUF_SE4BEG0_0", + "CLK_BUFG_REBUF_CK_GCLK0_BOT", + "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", + "CLK_BUFG_REBUF_R_CK_GCLK29_TOP" + ], + "tile_type": "CLK_BUFG_REBUF", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_BUFG_TOP_R.json b/artix7/tile_type_CLK_BUFG_TOP_R.json index be9986d..76ef1e9 100644 --- a/artix7/tile_type_CLK_BUFG_TOP_R.json +++ b/artix7/tile_type_CLK_BUFG_TOP_R.json @@ -1,3569 +1,3569 @@ { - "wires": [ - "CLK_BUFG_R_BUFGCTRL7_CE1", - "CLK_BUFG_LOGIC_OUTS_B5_2", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW4END2_1", - "CLK_BUFG_BUFGCTRL11_I1", - "CLK_HROW_SW4END0_2", - "CLK_HROW_EE4B1_2", - "CLK_BUFG_IMUX22_3", - "CLK_HROW_WW2END2_0", - "CLK_BUFG_BUFGCTRL9_O", - "CLK_BUFG_CK_GCLK16", - "CLK_HROW_EE2A3_2", - "CLK_BUFG_TOP_R_CK_MUXED11", - "CLK_HROW_EE4B3_0", - "CLK_BUFG_CK_GCLK0", - "CLK_BUFG_BUFGCTRL0_I0", - "CLK_BUFG_R_CK_FB_TEST1_7", - "CLK_BUFG_IMUX30_0", - "CLK_HROW_SW4END1_0", - "CLK_BUFG_R_BUFGCTRL2_S1", - "CLK_HROW_NW4END2_2", - "CLK_HROW_BYP6_2", - "CLK_HROW_NE2A2_2", - "CLK_HROW_EE2A1_0", - "CLK_HROW_WW4C3_2", - "CLK_BUFG_BUFGCTRL8_I0", - "CLK_HROW_WW4A2_0", - "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "CLK_BUFG_LOGIC_OUTS_B3_0", - "CLK_BUFG_BUFGCTRL15_I0", - "CLK_BUFG_IMUX23_3", - "CLK_HROW_NW4A2_1", - "CLK_BUFG_IMUX16_2", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_WW4END0_0", - "CLK_HROW_EE2A3_1", - "CLK_BUFG_IMUX27_2", - "CLK_BUFG_IMUX9_0", - "CLK_BUFG_BUFGCTRL14_I0", - "CLK_BUFG_IMUX28_0", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WW4END2_3", - "CLK_BUFG_R_BUFGCTRL13_CE1", - "CLK_BUFG_IMUX44_3", - "CLK_BUFG_R_BUFGCTRL3_S1", - "CLK_BUFG_BUFGCTRL5_I0", - "CLK_HROW_BYP7_3", - "CLK_HROW_WR1END3_3", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE2A2_3", - "CLK_BUFG_LOGIC_OUTS_B16_0", - "CLK_BUFG_IMUX7_3", - "CLK_BUFG_BUFGCTRL13_I1", - "CLK_HROW_WW4END0_3", - "CLK_BUFG_LOGIC_OUTS_B10_2", - "CLK_BUFG_IMUX5_3", - "CLK_HROW_NE4C2_0", - "CLK_BUFG_R_CK_FB_TEST0_5", - "CLK_BUFG_IMUX12_3", - "CLK_BUFG_LOGIC_OUTS_B13_3", - "CLK_BUFG_TOP_R_CK_MUXED6", - "CLK_BUFG_IMUX16_3", - "CLK_HROW_NE4BEG1_2", - "CLK_BUFG_IMUX41_1", - "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "CLK_HROW_SE4BEG0_0", - "CLK_BUFG_R_CK_FB_TEST1_14", - "CLK_BUFG_IMUX46_2", - "CLK_HROW_ER1BEG3_1", - "CLK_BUFG_IMUX16_0", - "CLK_HROW_CLK1_3", - "CLK_BUFG_R_FBG_OUT2", - "CLK_HROW_WW2A1_3", - "CLK_BUFG_R_BUFGCTRL12_S0", - "CLK_BUFG_R_BUFGCTRL15_CE1", - "CLK_BUFG_R_BUFGCTRL0_S1", - "CLK_BUFG_IMUX9_3", - "CLK_BUFG_IMUX6_1", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_2", - "CLK_HROW_NW4END1_1", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_WW4B3_1", - "CLK_BUFG_CK_GCLK19", - "CLK_BUFG_R_FBG_OUT7", - "CLK_BUFG_IMUX25_0", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_BUFG_R_BUFGCTRL6_S0", - "CLK_HROW_LH11_0", - "CLK_BUFG_CK_GCLK17", - "CLK_BUFG_R_BUFGCTRL6_CE0", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW4B0_1", - "CLK_HROW_NW4A2_2", - "CLK_BUFG_IMUX11_3", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WW4B1_0", - "CLK_BUFG_BUFGCTRL0_I1", - "CLK_HROW_BYP1_1", - "CLK_HROW_WW4END1_1", - "CLK_HROW_NW4A0_2", - "CLK_BUFG_IMUX7_0", - "CLK_HROW_WW4END1_3", - "CLK_HROW_WW4C2_3", - "CLK_BUFG_R_CK_FB_TEST0_14", - "CLK_BUFG_R_BUFGCTRL10_CE0", - "CLK_HROW_FAN1_1", - "CLK_HROW_BYP5_0", - "CLK_HROW_SE4BEG2_3", - "CLK_BUFG_R_CK_FB_TEST0_8", - "CLK_HROW_NW4END0_0", - "CLK_HROW_LH1_3", - "CLK_HROW_WW2END1_2", - "CLK_HROW_SE4C2_1", - "CLK_HROW_LH5_1", - "CLK_HROW_NE4C0_1", - "CLK_HROW_WL1END0_1", - "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "CLK_HROW_SW4END2_0", - "CLK_BUFG_IMUX33_3", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_EE4B3_3", - "CLK_BUFG_LOGIC_OUTS_B9_0", - "CLK_HROW_WW4B3_3", - "CLK_HROW_LH4_1", - "CLK_BUFG_IMUX8_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_EE4B1_3", - "CLK_BUFG_IMUX27_0", - "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "CLK_BUFG_TOP_R_CK_MUXED28", - "CLK_BUFG_IMUX33_1", - "CLK_BUFG_IMUX26_3", - "CLK_HROW_NW2A2_2", - "CLK_HROW_FAN0_3", - "CLK_BUFG_R_CK_FB_TEST0_6", - "CLK_HROW_WW4B1_3", - "CLK_HROW_SE2A0_3", - "CLK_HROW_NW4END3_1", - "CLK_HROW_LH5_0", - "CLK_BUFG_IMUX3_1", - "CLK_BUFG_CK_GCLK2", - "CLK_HROW_SW4END3_0", - "CLK_BUFG_R_FBG_OUT4", - "CLK_BUFG_TOP_R_CK_MUXED0", - "CLK_HROW_NW4A1_3", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_WW4B1_2", - "CLK_BUFG_IMUX9_1", - "CLK_HROW_EE4BEG2_0", - "CLK_BUFG_IMUX23_1", - "CLK_BUFG_IMUX1_3", - "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "CLK_HROW_WW4A1_1", - "CLK_BUFG_R_CK_FB_TEST0_1", - "CLK_BUFG_IMUX19_3", - "CLK_HROW_NE2A0_3", - "CLK_HROW_SE4BEG2_1", - "CLK_BUFG_BUFGCTRL13_I0", - "CLK_HROW_FAN5_1", - "CLK_BUFG_LOGIC_OUTS_B4_1", - "CLK_BUFG_R_BUFGCTRL4_CE1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_SW4END1_3", - "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "CLK_BUFG_CK_GCLK3", - "CLK_BUFG_LOGIC_OUTS_B17_3", - "CLK_HROW_LH3_0", - "CLK_BUFG_CK_GCLK9", - "CLK_HROW_EE4A1_3", - "CLK_HROW_FAN6_1", - "CLK_BUFG_R_BUFGCTRL13_CE0", - "CLK_HROW_WW4END3_2", - "CLK_HROW_EE4C3_0", - "CLK_HROW_BYP1_0", - "CLK_HROW_NE4C3_0", - "CLK_HROW_EL1BEG3_0", - "CLK_BUFG_LOGIC_OUTS_B7_0", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_EE4A3_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "CLK_BUFG_R_CK_FB_TEST1_11", - "CLK_HROW_MONITOR_P_2", - "CLK_BUFG_IMUX4_2", - "CLK_HROW_MONITOR_P_1", - "CLK_BUFG_IMUX39_0", - "CLK_BUFG_BUFGCTRL7_I0", - "CLK_HROW_NE2A1_2", - "CLK_BUFG_LOGIC_OUTS_B23_0", - "CLK_BUFG_IMUX19_1", - "CLK_BUFG_BUFGCTRL15_I1", - "CLK_BUFG_R_FBG_OUT6", - "CLK_HROW_CTRL1_1", - "CLK_BUFG_CK_GCLK5", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_NE4C2_3", - "CLK_HROW_FAN5_2", - "CLK_BUFG_LOGIC_OUTS_B1_3", - "CLK_BUFG_R_CK_FB_TEST1_15", - "CLK_BUFG_R_BUFGCTRL8_S1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_WW4B3_0", - "CLK_HROW_NE4C0_2", - "CLK_BUFG_IMUX29_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_FAN6_3", - "CLK_HROW_BYP5_1", - "CLK_HROW_CLK1_2", - "CLK_BUFG_R_FBG_OUT1", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_FAN7_3", - "CLK_HROW_CLK1_1", - "CLK_BUFG_IMUX29_3", - "CLK_BUFG_LOGIC_OUTS_B7_2", - "CLK_BUFG_R_BUFGCTRL7_S1", - "CLK_BUFG_LOGIC_OUTS_B2_3", - "CLK_HROW_EE4A0_3", - "CLK_BUFG_LOGIC_OUTS_B12_3", - "CLK_BUFG_TOP_R_CK_MUXED23", - "CLK_HROW_WW4B0_0", - "CLK_BUFG_BUFGCTRL10_I0", - "CLK_HROW_NW2A0_3", - "CLK_BUFG_IMUX9_2", - "CLK_HROW_NE2A0_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_SE4C3_3", - "CLK_BUFG_IMUX0_3", - "CLK_HROW_BYP6_1", - "CLK_HROW_SW4END2_3", - "CLK_HROW_EE2A3_3", - "CLK_HROW_LH1_1", - "CLK_BUFG_IMUX34_2", - "CLK_HROW_FAN3_1", - "CLK_BUFG_IMUX43_2", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WW4A2_3", - "CLK_BUFG_LOGIC_OUTS_B0_0", - "CLK_HROW_WW4C1_0", - "CLK_BUFG_BUFGCTRL6_I1", - "CLK_BUFG_R_BUFGCTRL2_S0", - "CLK_BUFG_R_BUFGCTRL14_S1", - "CLK_BUFG_TOP_R_CK_MUXED15", - "CLK_HROW_WW2END2_3", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4A1_0", - "CLK_BUFG_IMUX41_2", - "CLK_BUFG_IMUX32_3", - "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "CLK_HROW_WW2A3_3", - "CLK_BUFG_LOGIC_OUTS_B23_1", - "CLK_BUFG_LOGIC_OUTS_B5_1", - "CLK_HROW_WR1END1_1", - "CLK_BUFG_BUFGCTRL12_I0", - "CLK_BUFG_LOGIC_OUTS_B18_1", - "CLK_BUFG_R_BUFGCTRL12_CE0", - "CLK_BUFG_R_BUFGCTRL1_S0", - "CLK_HROW_EE4BEG1_3", - "CLK_BUFG_IMUX7_2", - "CLK_HROW_LH6_3", - "CLK_HROW_WW4A1_3", - "CLK_HROW_NE4BEG0_0", - "CLK_BUFG_R_FBG_OUT11", - "CLK_HROW_SW4A0_0", - "CLK_BUFG_IMUX47_3", - "CLK_BUFG_LOGIC_OUTS_B18_3", - "CLK_BUFG_LOGIC_OUTS_B17_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH1_2", - "CLK_HROW_NE4BEG3_2", - "CLK_BUFG_IMUX34_0", - "CLK_HROW_NE4BEG3_1", - "CLK_BUFG_CK_GCLK26", - "CLK_HROW_NW2A1_1", - "CLK_HROW_WW4B2_0", - "CLK_BUFG_BUFGCTRL1_I0", - "CLK_HROW_WR1END2_3", - "CLK_HROW_NW4A1_1", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SE4BEG2_2", - "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "CLK_BUFG_IMUX36_3", - "CLK_BUFG_R_CK_FB_TEST0_15", - "CLK_BUFG_R_BUFGCTRL14_S0", - "CLK_HROW_SW2A3_3", - "CLK_HROW_EE2A1_1", - "CLK_HROW_SE4BEG2_0", - "CLK_BUFG_IMUX46_3", - "CLK_HROW_ER1BEG1_2", - "CLK_BUFG_LOGIC_OUTS_B1_1", - "CLK_BUFG_R_BUFGCTRL7_S0", - "CLK_BUFG_TOP_R_CK_MUXED21", - "CLK_HROW_FAN0_2", - "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "CLK_HROW_NE4C0_3", - "CLK_BUFG_R_BUFGCTRL5_S0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_CLK0_2", - "CLK_BUFG_R_BUFGCTRL6_S1", - "CLK_HROW_NE2A2_0", - "CLK_HROW_EL1BEG3_3", - "CLK_BUFG_IMUX0_2", - "CLK_HROW_WW4C1_1", - "CLK_HROW_ER1BEG2_1", - "CLK_BUFG_IMUX37_3", - "CLK_BUFG_IMUX41_0", - "CLK_BUFG_BUFGCTRL9_I1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_BUFG_IMUX15_0", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SW4A1_0", - "CLK_BUFG_IMUX36_2", - "CLK_BUFG_IMUX32_1", - "CLK_BUFG_R_CK_FB_TEST0_9", - "CLK_BUFG_IMUX18_0", - "CLK_HROW_SE4BEG1_1", - "CLK_BUFG_BUFGCTRL11_O", - "CLK_BUFG_CK_GCLK7", - "CLK_BUFG_CK_GCLK12", - "CLK_BUFG_IMUX22_1", - "CLK_BUFG_CK_GCLK4", - "CLK_BUFG_R_BUFGCTRL1_CE0", - "CLK_HROW_EE4A1_1", - "CLK_BUFG_LOGIC_OUTS_B9_1", - "CLK_BUFG_CK_GCLK25", - "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "CLK_HROW_SW4A3_3", - "CLK_BUFG_IMUX14_2", - "CLK_BUFG_LOGIC_OUTS_B7_1", - "CLK_BUFG_IMUX43_3", - "CLK_HROW_CTRL0_3", - "CLK_BUFG_IMUX21_1", - "CLK_BUFG_R_CK_FB_TEST0_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_LH3_2", - "CLK_BUFG_LOGIC_OUTS_B14_0", - "CLK_HROW_EE4B2_3", - "CLK_HROW_SW4A3_0", - "CLK_HROW_BYP7_2", - "CLK_BUFG_LOGIC_OUTS_B8_2", - "CLK_BUFG_CK_GCLK14", - "CLK_BUFG_TOP_R_CK_MUXED24", - "CLK_BUFG_LOGIC_OUTS_B0_3", - "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "CLK_HROW_LH5_3", - "CLK_BUFG_LOGIC_OUTS_B15_2", - "CLK_HROW_WR1END1_0", - "CLK_HROW_CTRL0_1", - "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "CLK_HROW_NW4END3_3", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A1_2", - "CLK_HROW_NE4BEG2_1", - "CLK_BUFG_LOGIC_OUTS_B23_2", - "CLK_BUFG_R_BUFGCTRL13_S1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_LH1_0", - "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "CLK_BUFG_CK_GCLK23", - "CLK_BUFG_IMUX6_2", - "CLK_HROW_WW4C1_2", - "CLK_BUFG_IMUX2_1", - "CLK_BUFG_TOP_R_CK_MUXED16", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_WW4END2_2", - "CLK_BUFG_IMUX39_3", - "CLK_BUFG_IMUX47_0", - "CLK_HROW_EE4A1_2", - "CLK_BUFG_BUFGCTRL4_O", - "CLK_BUFG_TOP_R_CK_MUXED4", - "CLK_BUFG_TOP_R_CK_MUXED17", - "CLK_HROW_WW2A2_2", - "CLK_HROW_LH10_3", - "CLK_BUFG_IMUX47_1", - "CLK_HROW_FAN4_0", - "CLK_BUFG_IMUX46_1", - "CLK_HROW_LH8_0", - "CLK_HROW_WW2END3_2", - "CLK_HROW_LH12_3", - "CLK_BUFG_IMUX8_3", - "CLK_HROW_EE4A3_0", - "CLK_BUFG_BUFGCTRL2_O", - "CLK_HROW_LH4_2", - "CLK_HROW_NE4BEG0_3", - "CLK_BUFG_LOGIC_OUTS_B0_1", - "CLK_HROW_EE4BEG0_0", - "CLK_BUFG_IMUX2_0", - "CLK_HROW_SW2A0_3", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_LH6_0", - "CLK_BUFG_LOGIC_OUTS_B5_0", - "CLK_HROW_WW4END0_2", - "CLK_BUFG_IMUX27_1", - "CLK_BUFG_R_BUFGCTRL0_CE0", - "CLK_HROW_NW2A3_0", - "CLK_BUFG_IMUX2_3", - "CLK_BUFG_R_BUFGCTRL5_CE1", - "CLK_HROW_FAN3_0", - "CLK_BUFG_LOGIC_OUTS_B20_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_NE2A2_1", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_NW2A3_3", - "CLK_HROW_FAN6_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW2A1_1", - "CLK_HROW_SW4END3_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_WW2END3_0", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_NE4C3_1", - "CLK_BUFG_BUFGCTRL7_O", - "CLK_BUFG_BUFGCTRL10_O", - "CLK_HROW_NW4END1_0", - "CLK_HROW_EE4B0_3", - "CLK_HROW_CLK0_3", - "CLK_HROW_SW2A3_0", - "CLK_BUFG_BUFGCTRL15_O", - "CLK_BUFG_LOGIC_OUTS_B4_2", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_WW4END1_2", - "CLK_BUFG_IMUX28_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_ER1BEG3_2", - "CLK_BUFG_IMUX4_0", - "CLK_BUFG_BUFGCTRL12_I1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_EE4C1_1", - "CLK_HROW_NE2A3_3", - "CLK_HROW_WW4A3_1", - "CLK_HROW_BYP3_1", - "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "CLK_HROW_SE2A3_2", - "CLK_BUFG_IMUX33_2", - "CLK_HROW_EE2A2_2", - "CLK_BUFG_TOP_R_CK_MUXED8", - "CLK_HROW_LH11_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_BYP5_2", - "CLK_HROW_EE4B3_1", - "CLK_BUFG_BUFGCTRL9_I0", - "CLK_BUFG_LOGIC_OUTS_B19_2", - "CLK_BUFG_IMUX1_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_FAN2_3", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_LH9_3", - "CLK_HROW_EE2BEG1_2", - "CLK_BUFG_IMUX22_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_FAN2_2", - "CLK_BUFG_R_BUFGCTRL2_CE1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_WW4B2_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_SW2A0_2", - "CLK_BUFG_R_BUFGCTRL5_CE0", - "CLK_HROW_WL1END0_3", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_LH7_1", - "CLK_BUFG_LOGIC_OUTS_B2_2", - "CLK_HROW_EL1BEG1_1", - "CLK_BUFG_IMUX5_1", - "CLK_BUFG_R_BUFGCTRL4_S0", - "CLK_HROW_WW4END1_0", - "CLK_BUFG_IMUX34_3", - "CLK_BUFG_LOGIC_OUTS_B3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_EE2BEG0_3", - "CLK_BUFG_LOGIC_OUTS_B13_1", - "CLK_HROW_BYP1_3", - "CLK_BUFG_TOP_R_CK_MUXED5", - "CLK_HROW_BYP0_2", - "CLK_HROW_NE2A0_0", - "CLK_BUFG_IMUX30_1", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NW2A2_3", - "CLK_BUFG_IMUX18_3", - "CLK_BUFG_LOGIC_OUTS_B2_1", - "CLK_HROW_SW4A3_1", - "CLK_BUFG_R_CK_FB_TEST0_13", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_SE2A1_1", - "CLK_BUFG_IMUX15_1", - "CLK_HROW_WW2A3_1", - "CLK_BUFG_IMUX10_3", - "CLK_HROW_WR1END0_3", - "CLK_BUFG_R_FBG_OUT0", - "CLK_BUFG_LOGIC_OUTS_B1_0", - "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "CLK_HROW_NW4A3_0", - "CLK_BUFG_IMUX44_1", - "CLK_HROW_BYP4_1", - "CLK_HROW_NE2A3_1", - "CLK_BUFG_IMUX42_0", - "CLK_BUFG_IMUX46_0", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SW2A1_0", - "CLK_HROW_BYP2_3", - "CLK_HROW_EE2BEG3_3", - "CLK_BUFG_R_CK_FB_TEST1_4", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_SW4END0_1", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_BUFG_BUFGCTRL11_I0", - "CLK_BUFG_TOP_R_CK_MUXED29", - "CLK_HROW_BYP3_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_FAN2_1", - "CLK_HROW_BYP0_0", - "CLK_HROW_LH12_1", - "CLK_HROW_NE4BEG1_3", - "CLK_BUFG_IMUX4_1", - "CLK_HROW_EE4A2_2", - "CLK_BUFG_IMUX37_2", - "CLK_BUFG_BUFGCTRL8_I1", - "CLK_HROW_WR1END0_2", - "CLK_BUFG_IMUX8_2", - "CLK_BUFG_LOGIC_OUTS_B16_1", - "CLK_BUFG_R_BUFGCTRL14_CE1", - "CLK_BUFG_R_BUFGCTRL8_S0", - "CLK_BUFG_CK_GCLK8", - "CLK_BUFG_IMUX36_1", - "CLK_HROW_SW2A0_1", - "CLK_HROW_ER1BEG3_0", - "CLK_BUFG_IMUX45_0", - "CLK_BUFG_LOGIC_OUTS_B20_0", - "CLK_BUFG_IMUX1_1", - "CLK_BUFG_IMUX4_3", - "CLK_BUFG_CK_GCLK21", - "CLK_HROW_WL1END1_1", - "CLK_BUFG_LOGIC_OUTS_B19_0", - "CLK_BUFG_IMUX36_0", - "CLK_BUFG_R_BUFGCTRL15_S0", - "CLK_HROW_SW4END2_2", - "CLK_BUFG_IMUX15_3", - "CLK_BUFG_LOGIC_OUTS_B15_0", - "CLK_BUFG_IMUX25_1", - "CLK_HROW_LH11_3", - "CLK_BUFG_IMUX14_1", - "CLK_BUFG_IMUX39_1", - "CLK_BUFG_R_CK_FB_TEST0_12", - "CLK_BUFG_IMUX41_3", - "CLK_HROW_LH2_1", - "CLK_BUFG_LOGIC_OUTS_B8_1", - "CLK_HROW_SW2A0_0", - "CLK_BUFG_IMUX20_2", - "CLK_BUFG_IMUX45_2", - "CLK_BUFG_IMUX40_0", - "CLK_BUFG_IMUX3_0", - "CLK_BUFG_CK_GCLK10", - "CLK_BUFG_BUFGCTRL14_O", - "CLK_BUFG_BUFGCTRL6_O", - "CLK_HROW_WW4C0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_LH9_0", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_WW4C0_0", - "CLK_BUFG_R_FBG_OUT8", - "CLK_BUFG_IMUX21_0", - "CLK_HROW_EE2BEG1_3", - "CLK_BUFG_IMUX12_1", - "CLK_BUFG_IMUX26_2", - "CLK_HROW_SW2A2_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NE4C2_2", - "CLK_BUFG_LOGIC_OUTS_B0_2", - "CLK_BUFG_TOP_R_CK_MUXED26", - "CLK_BUFG_TOP_R_CK_MUXED9", - "CLK_HROW_MONITOR_P_3", - "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "CLK_HROW_WW4A1_0", - "CLK_HROW_NE4BEG0_2", - "CLK_BUFG_IMUX40_2", - "CLK_BUFG_CK_GCLK1", - "CLK_BUFG_TOP_R_CK_MUXED3", - "CLK_HROW_EE4C0_3", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_WW4END3_0", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4C3_3", - "CLK_HROW_NW4A3_2", - "CLK_BUFG_IMUX40_3", - "CLK_BUFG_R_BUFGCTRL3_CE1", - "CLK_HROW_WW4A1_2", - "CLK_BUFG_LOGIC_OUTS_B22_0", - "CLK_BUFG_R_BUFGCTRL3_S0", - "CLK_BUFG_R_CK_FB_TEST1_2", - "CLK_BUFG_R_BUFGCTRL9_S1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_SE4BEG1_0", - "CLK_BUFG_R_BUFGCTRL10_S1", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_WR1END0_0", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NW2A0_2", - "CLK_BUFG_LOGIC_OUTS_B13_2", - "CLK_BUFG_IMUX0_0", - "CLK_BUFG_LOGIC_OUTS_B12_0", - "CLK_HROW_EE4C2_2", - "CLK_BUFG_IMUX38_1", - "CLK_HROW_FAN4_3", - "CLK_HROW_CLK0_0", - "CLK_BUFG_IMUX12_2", - "CLK_BUFG_IMUX34_1", - "CLK_BUFG_CK_GCLK28", - "CLK_HROW_WW4END3_1", - "CLK_HROW_BYP0_1", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A0_0", - "CLK_BUFG_IMUX40_1", - "CLK_HROW_BYP3_2", - "CLK_BUFG_IMUX10_0", - "CLK_HROW_EE4B1_0", - "CLK_HROW_NE4C3_3", - "CLK_BUFG_LOGIC_OUTS_B11_1", - "CLK_HROW_NE2A1_3", - "CLK_BUFG_IMUX37_0", - "CLK_BUFG_R_BUFGCTRL9_CE0", - "CLK_BUFG_IMUX29_1", - "CLK_BUFG_BUFGCTRL2_I1", - "CLK_HROW_WW4A0_0", - "CLK_HROW_EL1BEG2_1", - "CLK_BUFG_BUFGCTRL14_I1", - "CLK_HROW_NE2A2_3", - "CLK_BUFG_R_BUFGCTRL9_S0", - "CLK_BUFG_LOGIC_OUTS_B18_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_NW4END3_2", - "CLK_BUFG_R_BUFGCTRL0_CE1", - "CLK_HROW_NE4C1_0", - "CLK_BUFG_R_CK_FB_TEST1_5", - "CLK_BUFG_LOGIC_OUTS_B20_1", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_WW2A0_0", - "CLK_BUFG_IMUX6_0", - "CLK_HROW_SE4BEG1_2", - "CLK_BUFG_LOGIC_OUTS_B19_1", - "CLK_BUFG_R_FBG_OUT10", - "CLK_HROW_BYP7_0", - "CLK_HROW_LH8_1", - "CLK_HROW_NW4END2_3", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_BYP2_1", - "CLK_HROW_EE2A2_1", - "CLK_HROW_WW2A2_1", - "CLK_BUFG_LOGIC_OUTS_B16_3", - "CLK_BUFG_CK_GCLK30", - "CLK_HROW_NW2A1_2", - "CLK_BUFG_LOGIC_OUTS_B11_2", - "CLK_HROW_WW2A3_0", - "CLK_BUFG_BUFGCTRL7_I1", - "CLK_HROW_ER1BEG1_0", - "CLK_BUFG_LOGIC_OUTS_B1_2", - "CLK_BUFG_TOP_R_CK_MUXED18", - "CLK_BUFG_IMUX28_1", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_BUFG_IMUX31_0", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_BUFG_IMUX42_1", - "CLK_HROW_LH4_3", - "CLK_HROW_FAN1_2", - "CLK_BUFG_IMUX5_0", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_CTRL0_0", - "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "CLK_BUFG_IMUX33_0", - "CLK_HROW_SE2A1_2", - "CLK_BUFG_IMUX35_3", - "CLK_HROW_CTRL1_3", - "CLK_BUFG_BUFGCTRL8_O", - "CLK_HROW_SE2A3_3", - "CLK_BUFG_R_BUFGCTRL4_S1", - "CLK_BUFG_R_BUFGCTRL3_CE0", - "CLK_HROW_EE4B1_1", - "CLK_HROW_LH5_2", - "CLK_BUFG_CK_GCLK29", - "CLK_HROW_NE4BEG1_0", - "CLK_BUFG_IMUX42_3", - "CLK_HROW_WW4B2_3", - "CLK_BUFG_LOGIC_OUTS_B10_3", - "CLK_BUFG_R_CK_FB_TEST1_1", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_WW4END3_3", - "CLK_BUFG_BUFGCTRL2_I0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_EE4A0_0", - "CLK_HROW_WW4B0_3", - "CLK_BUFG_IMUX47_2", - "CLK_BUFG_IMUX30_3", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SE2A2_2", - "CLK_BUFG_R_BUFGCTRL5_S1", - "CLK_HROW_FAN1_3", - "CLK_HROW_SW2A1_3", - "CLK_HROW_FAN3_2", - "CLK_BUFG_R_CK_FB_TEST1_3", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_BUFG_IMUX11_2", - "CLK_BUFG_IMUX16_1", - "CLK_HROW_LH8_2", - "CLK_BUFG_IMUX27_3", - "CLK_HROW_NE4BEG1_1", - "CLK_BUFG_R_BUFGCTRL10_S0", - "CLK_HROW_WW2A0_2", - "CLK_BUFG_LOGIC_OUTS_B2_0", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_SW4A2_2", - "CLK_BUFG_BUFGCTRL3_I0", - "CLK_BUFG_R_BUFGCTRL11_S0", - "CLK_HROW_EE4C0_0", - "CLK_BUFG_LOGIC_OUTS_B6_1", - "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_FAN0_1", - "CLK_BUFG_LOGIC_OUTS_B23_3", - "CLK_HROW_EE2A2_0", - "CLK_BUFG_LOGIC_OUTS_B18_0", - "CLK_BUFG_R_FBG_OUT15", - "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "CLK_BUFG_IMUX14_0", - "CLK_BUFG_LOGIC_OUTS_B15_1", - "CLK_HROW_NE2A1_0", - "CLK_BUFG_CK_GCLK11", - "CLK_BUFG_IMUX35_2", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW4B1_1", - "CLK_BUFG_R_BUFGCTRL13_S0", - "CLK_HROW_MONITOR_N_3", - "CLK_BUFG_IMUX35_0", - "CLK_HROW_LH6_2", - "CLK_HROW_NW4END1_3", - "CLK_HROW_WR1END1_3", - "CLK_BUFG_LOGIC_OUTS_B12_2", - "CLK_HROW_FAN7_0", - "CLK_HROW_LH4_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_FAN2_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_NW4END0_2", - "CLK_BUFG_LOGIC_OUTS_B21_2", - "CLK_BUFG_R_CK_FB_TEST1_8", - "CLK_HROW_SE2A0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_NW2A0_1", - "CLK_BUFG_IMUX28_3", - "CLK_HROW_NE4BEG2_3", - "CLK_BUFG_IMUX32_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_NE4C0_0", - "CLK_BUFG_LOGIC_OUTS_B3_1", - "CLK_HROW_NW2A2_0", - "CLK_BUFG_R_CK_FB_TEST1_13", - "CLK_HROW_CLK0_1", - "CLK_HROW_SE2A1_3", - "CLK_HROW_WW2END3_3", - "CLK_HROW_SW4END2_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_EE4C1_0", - "CLK_BUFG_IMUX19_2", - "CLK_BUFG_IMUX20_0", - "CLK_HROW_BYP6_3", - "CLK_HROW_SE4C2_3", - "CLK_BUFG_LOGIC_OUTS_B10_0", - "CLK_BUFG_R_BUFGCTRL1_CE1", - "CLK_BUFG_CK_GCLK22", - "CLK_BUFG_LOGIC_OUTS_B6_0", - "CLK_HROW_WW4C2_1", - "CLK_BUFG_TOP_R_CK_MUXED22", - "CLK_BUFG_LOGIC_OUTS_B12_1", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_NE4BEG3_3", - "CLK_BUFG_BUFGCTRL10_I1", - "CLK_HROW_LH12_2", - "CLK_HROW_WW4B2_2", - "CLK_HROW_EE4A0_2", - "CLK_HROW_SE2A3_0", - "CLK_HROW_EE4B2_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_EL1BEG0_3", - "CLK_BUFG_IMUX13_0", - "CLK_BUFG_R_CK_FB_TEST0_11", - "CLK_HROW_LH7_3", - "CLK_BUFG_CK_GCLK15", - "CLK_BUFG_IMUX24_1", - "CLK_HROW_EE4B0_1", - "CLK_HROW_SW2A3_2", - "CLK_BUFG_LOGIC_OUTS_B21_3", - "CLK_BUFG_IMUX21_3", - "CLK_HROW_FAN6_2", - "CLK_BUFG_R_FBG_OUT14", - "CLK_BUFG_LOGIC_OUTS_B14_1", - "CLK_BUFG_LOGIC_OUTS_B7_3", - "CLK_HROW_WW2A3_2", - "CLK_HROW_LH10_1", - "CLK_HROW_BYP6_0", - "CLK_HROW_FAN7_1", - "CLK_BUFG_IMUX3_3", - "CLK_BUFG_IMUX10_2", - "CLK_BUFG_R_BUFGCTRL6_CE1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_WW4A2_1", - "CLK_BUFG_LOGIC_OUTS_B9_2", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP5_3", - "CLK_BUFG_LOGIC_OUTS_B21_1", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_BUFG_CK_GCLK31", - "CLK_HROW_NW4A0_1", - "CLK_HROW_WW2END0_1", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_WW4A3_2", - "CLK_HROW_EE4C1_2", - "CLK_HROW_SE4C0_1", - "CLK_BUFG_BUFGCTRL4_I0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_CLK1_0", - "CLK_HROW_EE4BEG1_2", - "CLK_BUFG_IMUX35_1", - "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "CLK_HROW_NW4END3_0", - "CLK_HROW_EE2BEG1_1", - "CLK_BUFG_IMUX29_0", - "CLK_HROW_SE2A2_3", - "CLK_HROW_NW4A1_0", - "CLK_HROW_WR1END3_2", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE4A2_1", - "CLK_BUFG_LOGIC_OUTS_B17_2", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SW4A0_3", - "CLK_BUFG_IMUX26_0", - "CLK_BUFG_R_BUFGCTRL7_CE0", - "CLK_HROW_FAN5_0", - "CLK_BUFG_R_BUFGCTRL8_CE1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_SE2A2_0", - "CLK_BUFG_R_BUFGCTRL4_CE0", - "CLK_BUFG_IMUX8_0", - "CLK_BUFG_R_FBG_OUT3", - "CLK_HROW_WW4C2_0", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_SW4A3_2", - "CLK_HROW_LH7_2", - "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "CLK_BUFG_TOP_R_CK_MUXED27", - "CLK_BUFG_IMUX2_2", - "CLK_HROW_NW4A3_1", - "CLK_BUFG_LOGIC_OUTS_B21_0", - "CLK_HROW_SE4C1_1", - "CLK_BUFG_LOGIC_OUTS_B15_3", - "CLK_BUFG_LOGIC_OUTS_B8_0", - "CLK_BUFG_R_BUFGCTRL11_CE0", - "CLK_HROW_LH3_1", - "CLK_HROW_SW4A2_3", - "CLK_HROW_NW4A0_3", - "CLK_BUFG_LOGIC_OUTS_B14_2", - "CLK_HROW_BYP4_0", - "CLK_BUFG_LOGIC_OUTS_B14_3", - "CLK_HROW_WW2A0_1", - "CLK_BUFG_IMUX6_3", - "CLK_BUFG_R_BUFGCTRL9_CE1", - "CLK_BUFG_LOGIC_OUTS_B22_1", - "CLK_BUFG_IMUX14_3", - "CLK_HROW_EE2BEG2_1", - "CLK_BUFG_IMUX45_3", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_2", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WL1END3_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_WW4END2_0", - "CLK_HROW_LH7_0", - "CLK_BUFG_IMUX23_2", - "CLK_BUFG_IMUX31_1", - "CLK_HROW_FAN0_0", - "CLK_BUFG_LOGIC_OUTS_B11_0", - "CLK_BUFG_IMUX13_2", - "CLK_HROW_ER1BEG2_0", - "CLK_BUFG_IMUX44_2", - "CLK_BUFG_BUFGCTRL3_I1", - "CLK_BUFG_IMUX25_3", - "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "CLK_HROW_SW4A2_0", - "CLK_BUFG_CK_GCLK27", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_BUFG_BUFGCTRL5_I1", - "CLK_BUFG_CK_GCLK20", - "CLK_HROW_EE2BEG3_0", - "CLK_BUFG_IMUX30_2", - "CLK_BUFG_IMUX11_0", - "CLK_BUFG_IMUX25_2", - "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "CLK_HROW_SE4C2_0", - "CLK_HROW_WW4A0_3", - "CLK_BUFG_IMUX38_3", - "CLK_BUFG_IMUX21_2", - "CLK_HROW_LH6_1", - "CLK_HROW_EE4B0_2", - "CLK_BUFG_BUFGCTRL0_O", - "CLK_BUFG_IMUX18_2", - "CLK_BUFG_R_CK_FB_TEST0_3", - "CLK_BUFG_BUFGCTRL13_O", - "CLK_HROW_WW4C3_0", - "CLK_BUFG_BUFGCTRL12_O", - "CLK_HROW_BYP7_1", - "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "CLK_BUFG_R_BUFGCTRL12_S1", - "CLK_HROW_CTRL1_0", - "CLK_BUFG_LOGIC_OUTS_B16_2", - "CLK_BUFG_R_CK_FB_TEST1_6", - "CLK_BUFG_TOP_R_CK_MUXED12", - "CLK_HROW_EL1BEG0_0", - "CLK_BUFG_IMUX19_0", - "CLK_BUFG_R_BUFGCTRL0_S0", - "CLK_HROW_EE2A0_0", - "CLK_HROW_WL1END2_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_FAN7_2", - "CLK_BUFG_IMUX20_3", - "CLK_BUFG_LOGIC_OUTS_B11_3", - "CLK_HROW_WR1END1_2", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_WR1END3_1", - "CLK_BUFG_LOGIC_OUTS_B10_1", - "CLK_HROW_SE4C1_2", - "CLK_BUFG_LOGIC_OUTS_B3_3", - "CLK_BUFG_R_BUFGCTRL8_CE0", - "CLK_HROW_WW2A2_0", - "CLK_BUFG_IMUX18_1", - "CLK_HROW_NE4C1_3", - "CLK_HROW_EE4C2_3", - "CLK_BUFG_IMUX1_2", - "CLK_HROW_CTRL0_2", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE2BEG3_1", - "CLK_BUFG_IMUX32_2", - "CLK_BUFG_TOP_R_CK_MUXED14", - "CLK_HROW_LH2_3", - "CLK_HROW_LH10_0", - "CLK_BUFG_IMUX31_2", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_EE2A0_3", - "CLK_BUFG_LOGIC_OUTS_B22_3", - "CLK_BUFG_TOP_R_CK_MUXED7", - "CLK_BUFG_R_CK_FB_TEST1_9", - "CLK_BUFG_IMUX43_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_NW4END2_0", - "CLK_BUFG_TOP_R_CK_MUXED25", - "CLK_BUFG_LOGIC_OUTS_B6_3", - "CLK_BUFG_BUFGCTRL4_I1", - "CLK_BUFG_IMUX11_1", - "CLK_BUFG_TOP_R_CK_MUXED31", - "CLK_BUFG_IMUX44_0", - "CLK_BUFG_CK_GCLK6", - "CLK_HROW_EE4C1_3", - "CLK_HROW_NE4C2_1", - "CLK_HROW_EE4C0_1", - "CLK_BUFG_CK_GCLK18", - "CLK_HROW_WR1END0_1", - "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "CLK_BUFG_TOP_R_CK_MUXED2", - "CLK_HROW_BYP0_3", - "CLK_HROW_NW4END1_2", - "CLK_BUFG_IMUX17_3", - "CLK_BUFG_BUFGCTRL1_I1", - "CLK_HROW_EE2A1_3", - "CLK_HROW_SW2A2_2", - "CLK_BUFG_IMUX0_1", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_WW2END0_0", - "CLK_BUFG_IMUX3_2", - "CLK_BUFG_R_FBG_OUT13", - "CLK_BUFG_R_FBG_OUT12", - "CLK_HROW_EE2A3_0", - "CLK_BUFG_R_CK_FB_TEST0_4", - "CLK_BUFG_IMUX13_3", - "CLK_HROW_SE2A2_1", - "CLK_BUFG_IMUX13_1", - "CLK_HROW_SW2A2_0", - "CLK_HROW_WW4A2_2", - "CLK_HROW_LH3_3", - "CLK_HROW_CTRL1_2", - "CLK_BUFG_IMUX17_2", - "CLK_HROW_WW2A2_3", - "CLK_BUFG_IMUX24_0", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4BEG0_3", - "CLK_BUFG_R_BUFGCTRL2_CE0", - "CLK_BUFG_R_BUFGCTRL14_CE0", - "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "CLK_BUFG_TOP_R_CK_MUXED19", - "CLK_BUFG_LOGIC_OUTS_B22_2", - "CLK_HROW_NE2A3_2", - "CLK_HROW_WW4B0_2", - "CLK_HROW_BYP1_2", - "CLK_HROW_LH11_2", - "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "CLK_HROW_EE4BEG3_2", - "CLK_BUFG_IMUX38_2", - "CLK_HROW_WW2END2_1", - "CLK_HROW_SE4C3_0", - "CLK_BUFG_R_BUFGCTRL15_CE0", - "CLK_HROW_NW2A3_2", - "CLK_BUFG_IMUX45_1", - "CLK_HROW_NW4A2_3", - "CLK_BUFG_IMUX15_2", - "CLK_BUFG_TOP_R_CK_MUXED1", - "CLK_HROW_NW4A0_0", - "CLK_BUFG_IMUX26_1", - "CLK_HROW_SE2A0_1", - "CLK_BUFG_LOGIC_OUTS_B6_2", - "CLK_HROW_EE2BEG0_1", - "CLK_BUFG_IMUX24_2", - "CLK_BUFG_BUFGCTRL1_O", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4C0_3", - "CLK_HROW_FAN5_3", - "CLK_BUFG_LOGIC_OUTS_B5_3", - "CLK_BUFG_TOP_R_CK_MUXED30", - "CLK_BUFG_TOP_R_CK_MUXED20", - "CLK_BUFG_LOGIC_OUTS_B13_0", - "CLK_BUFG_IMUX23_0", - "CLK_BUFG_BUFGCTRL3_O", - "CLK_HROW_SW4A2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_1", - "CLK_HROW_SW2A3_1", - "CLK_HROW_LH8_3", - "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "CLK_HROW_LH9_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_EE2A1_2", - "CLK_HROW_LH2_2", - "CLK_HROW_SW4END1_2", - "CLK_BUFG_IMUX24_3", - "CLK_HROW_SE4C0_0", - "CLK_BUFG_R_BUFGCTRL12_CE1", - "CLK_HROW_WW2END1_0", - "CLK_BUFG_R_FBG_OUT9", - "CLK_HROW_EE4B2_1", - "CLK_HROW_WW2END0_2", - "CLK_BUFG_R_BUFGCTRL11_CE1", - "CLK_BUFG_R_FBG_OUT5", - "CLK_HROW_WR1END2_2", - "CLK_HROW_EE4A2_0", - "CLK_BUFG_LOGIC_OUTS_B4_0", - "CLK_BUFG_IMUX12_0", - "CLK_BUFG_IMUX38_0", - "CLK_BUFG_R_CK_FB_TEST1_12", - "CLK_BUFG_IMUX43_0", - "CLK_BUFG_LOGIC_OUTS_B4_3", - "CLK_HROW_NW4END0_3", - "CLK_HROW_LH10_2", - "CLK_BUFG_R_BUFGCTRL10_CE1", - "CLK_HROW_SE4C0_2", - "CLK_BUFG_R_CK_FB_TEST1_0", - "CLK_HROW_WW4A3_0", - "CLK_BUFG_LOGIC_OUTS_B9_3", - "CLK_BUFG_IMUX20_1", - "CLK_BUFG_IMUX42_2", - "CLK_BUFG_R_CK_FB_TEST0_7", - "CLK_BUFG_R_CK_FB_TEST1_10", - "CLK_HROW_WW2END0_3", - "CLK_BUFG_IMUX37_1", - "CLK_HROW_WR1END2_1", - "CLK_HROW_EE4C3_2", - "CLK_BUFG_IMUX17_0", - "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "CLK_BUFG_R_BUFGCTRL11_S1", - "CLK_HROW_NE4BEG2_2", - "CLK_BUFG_LOGIC_OUTS_B19_3", - "CLK_BUFG_LOGIC_OUTS_B17_1", - "CLK_HROW_WW4A0_2", - "CLK_BUFG_R_BUFGCTRL15_S1", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_FAN3_3", - "CLK_BUFG_R_BUFGCTRL1_S1", - "CLK_BUFG_IMUX5_2", - "CLK_BUFG_CK_GCLK24", - "CLK_HROW_EE4B0_0", - "CLK_BUFG_IMUX10_1", - "CLK_BUFG_BUFGCTRL5_O", - "CLK_HROW_MONITOR_N_0", - "CLK_BUFG_IMUX31_3", - "CLK_BUFG_TOP_R_CK_MUXED10", - "CLK_HROW_LH12_0", - "CLK_BUFG_IMUX39_2", - "CLK_BUFG_CK_GCLK13", - "CLK_BUFG_LOGIC_OUTS_B20_3", - "CLK_BUFG_IMUX7_1", - "CLK_HROW_WL1END3_0", - "CLK_HROW_WW4A3_3", - "CLK_BUFG_R_CK_FB_TEST0_10", - "CLK_HROW_SE4C1_3", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_NW4A2_0", - "CLK_BUFG_BUFGCTRL6_I0", - "CLK_HROW_SW4END0_0", - "CLK_HROW_LH2_0", - "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "CLK_HROW_NW4A3_3", - "CLK_HROW_EE4C2_0", - "CLK_HROW_SE2A1_0", - "CLK_BUFG_TOP_R_CK_MUXED13", - "CLK_HROW_WL1END1_0", - "CLK_BUFG_R_CK_FB_TEST0_2", - "CLK_BUFG_LOGIC_OUTS_B8_3", - "CLK_BUFG_IMUX17_1", - "CLK_BUFG_IMUX22_2", - "CLK_HROW_SE4C3_1", - "CLK_HROW_FAN1_0" - ], - "sites": [ - { - "prefix": "BUFGCTRL", - "y_coord": 0, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", - "O": "CLK_BUFG_BUFGCTRL0_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL0_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL0_S1", - "I1": "CLK_BUFG_BUFGCTRL0_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", - "I0": "CLK_BUFG_BUFGCTRL0_I0" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 1, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", - "O": "CLK_BUFG_BUFGCTRL1_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL1_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL1_S1", - "I1": "CLK_BUFG_BUFGCTRL1_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", - "I0": "CLK_BUFG_BUFGCTRL1_I0" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 2, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", - "O": "CLK_BUFG_BUFGCTRL2_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL2_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL2_S1", - "I1": "CLK_BUFG_BUFGCTRL2_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", - "I0": "CLK_BUFG_BUFGCTRL2_I0" - }, - "x_coord": 0, - "name": "X0Y2" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 3, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", - "O": "CLK_BUFG_BUFGCTRL3_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL3_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL3_S1", - "I1": "CLK_BUFG_BUFGCTRL3_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", - "I0": "CLK_BUFG_BUFGCTRL3_I0" - }, - "x_coord": 0, - "name": "X0Y3" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 4, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", - "O": "CLK_BUFG_BUFGCTRL4_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL4_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL4_S1", - "I1": "CLK_BUFG_BUFGCTRL4_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", - "I0": "CLK_BUFG_BUFGCTRL4_I0" - }, - "x_coord": 0, - "name": "X0Y4" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 5, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", - "O": "CLK_BUFG_BUFGCTRL5_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL5_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL5_S1", - "I1": "CLK_BUFG_BUFGCTRL5_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", - "I0": "CLK_BUFG_BUFGCTRL5_I0" - }, - "x_coord": 0, - "name": "X0Y5" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 6, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", - "O": "CLK_BUFG_BUFGCTRL6_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL6_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL6_S1", - "I1": "CLK_BUFG_BUFGCTRL6_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", - "I0": "CLK_BUFG_BUFGCTRL6_I0" - }, - "x_coord": 0, - "name": "X0Y6" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 7, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", - "O": "CLK_BUFG_BUFGCTRL7_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL7_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL7_S1", - "I1": "CLK_BUFG_BUFGCTRL7_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", - "I0": "CLK_BUFG_BUFGCTRL7_I0" - }, - "x_coord": 0, - "name": "X0Y7" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 8, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", - "O": "CLK_BUFG_BUFGCTRL8_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL8_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL8_S1", - "I1": "CLK_BUFG_BUFGCTRL8_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", - "I0": "CLK_BUFG_BUFGCTRL8_I0" - }, - "x_coord": 0, - "name": "X0Y8" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 9, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", - "O": "CLK_BUFG_BUFGCTRL9_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL9_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL9_S1", - "I1": "CLK_BUFG_BUFGCTRL9_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", - "I0": "CLK_BUFG_BUFGCTRL9_I0" - }, - "x_coord": 0, - "name": "X0Y9" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 10, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", - "O": "CLK_BUFG_BUFGCTRL10_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL10_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL10_S1", - "I1": "CLK_BUFG_BUFGCTRL10_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", - "I0": "CLK_BUFG_BUFGCTRL10_I0" - }, - "x_coord": 0, - "name": "X0Y10" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 11, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", - "O": "CLK_BUFG_BUFGCTRL11_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL11_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL11_S1", - "I1": "CLK_BUFG_BUFGCTRL11_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", - "I0": "CLK_BUFG_BUFGCTRL11_I0" - }, - "x_coord": 0, - "name": "X0Y11" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 12, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", - "O": "CLK_BUFG_BUFGCTRL12_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL12_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL12_S1", - "I1": "CLK_BUFG_BUFGCTRL12_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", - "I0": "CLK_BUFG_BUFGCTRL12_I0" - }, - "x_coord": 0, - "name": "X0Y12" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 13, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", - "O": "CLK_BUFG_BUFGCTRL13_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL13_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL13_S1", - "I1": "CLK_BUFG_BUFGCTRL13_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", - "I0": "CLK_BUFG_BUFGCTRL13_I0" - }, - "x_coord": 0, - "name": "X0Y13" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 14, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", - "O": "CLK_BUFG_BUFGCTRL14_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL14_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL14_S1", - "I1": "CLK_BUFG_BUFGCTRL14_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", - "I0": "CLK_BUFG_BUFGCTRL14_I0" - }, - "x_coord": 0, - "name": "X0Y14" - }, - { - "prefix": "BUFGCTRL", - "y_coord": 15, - "type": "BUFGCTRL", - "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", - "O": "CLK_BUFG_BUFGCTRL15_O", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "S0": "CLK_BUFG_R_BUFGCTRL15_S0", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "S1": "CLK_BUFG_R_BUFGCTRL15_S1", - "I1": "CLK_BUFG_BUFGCTRL15_I1", - "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", - "I0": "CLK_BUFG_BUFGCTRL15_I0" - }, - "x_coord": 0, - "name": "X0Y15" - } - ], "pips": { - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT12", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX7_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT5", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED4", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX15_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX1_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX17_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX5_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX20_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX10_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT13", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX22_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX5_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX16_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX23_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT7", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX22_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT8", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT13", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL13_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT6", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED19", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT9", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED16", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK28": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK28", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL12_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT6", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX14_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX8_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT9", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX19_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX3_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED30", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED7", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX15_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT11", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL11_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED29", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT4", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT6", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED18", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX20_2", - "is_pseudo": "0" - }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", - "is_directional": "1", "src_wire": "CLK_BUFG_IMUX28_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1", "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX1_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT5", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT8", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT4", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL4_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX21_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX11_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", "src_wire": "CLK_BUFG_R_FBG_OUT12", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT5", "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL5_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK18": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK18", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL2_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT9", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX10_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX18_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX8_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX2_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX0_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK31": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK31", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL15_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED27", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED26", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED28", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED13", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX12_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", "src_wire": "CLK_BUFG_TOP_R_CK_MUXED25", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0", "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX23_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX20_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT7", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX13_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX18_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX13_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX22_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT15", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED31", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX12_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX5_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0", - "is_directional": "1", "src_wire": "CLK_BUFG_IMUX6_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX12_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED10", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT4", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX12_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT4", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX1_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX2_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK16": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK16", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL0_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX0_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED22", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT5", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT11", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX21_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_0->>CLK_BUFG_R_BUFGCTRL3_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX3_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT15", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT15", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX18_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT11", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX9_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX23_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT14", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX13_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX4_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT10", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX7_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT15", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX16_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX9_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT12", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX14_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX15_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED12", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK22": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK22", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL6_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK19": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK19", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL3_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX2_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX22_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX16_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX21_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK23": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK23", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL7_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT9", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT9", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL9_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX9_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT0", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL0_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL2_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX11_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED9", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT15", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL15_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX17_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX7_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT10", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK26": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK26", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL10_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX11_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX3_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX16_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX2_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED14", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK25": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK25", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL9_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX10_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT11", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX0_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT5", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX17_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX4_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED15", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED23", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT11", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX6_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT14", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX4_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT8", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL8_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED5", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED21", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT14", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX19_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK17": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK17", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL1_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT12", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK27": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK27", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL11_O", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT14", - "is_directional": "1", "src_wire": "CLK_BUFG_BUFGCTRL14_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK21": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK21", "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL5_O", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT14" }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT1", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL1_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX6_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX20_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX8_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED8", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK29": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK29", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL13_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT14", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX14_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED20", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT13", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED6", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX17_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT2", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL2_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT6", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT6", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL6_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT10", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL10_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX23_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX18_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT4", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX5_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED24", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED17", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX10_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX1_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX7_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK30": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK30", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL14_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT3", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL3_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX3_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK24": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK24", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL8_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX0_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX30_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT7", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL7_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT13", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX21_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX31_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_directional": "1", "src_wire": "CLK_BUFG_R_FBG_OUT7", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED12", "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", + "src_wire": "CLK_BUFG_IMUX27_2", "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX4_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX11_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK20": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_CK_GCLK20", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL4_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX28_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX19_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX25_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX19_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX14_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_R_FBG_OUT8", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX26_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX13_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX15_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL8_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL8_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", - "is_directional": "1", "src_wire": "CLK_BUFG_R_FBG_OUT10", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_FBG_OUT12", "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL12_O", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED11", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_3", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL4_O", - "is_directional": "1", - "src_wire": "CLK_BUFG_BUFGCTRL4_I0", - "is_pseudo": "1" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX6_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX9_2", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX24_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_TOP_R_CK_MUXED1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX8_0", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX27_1", - "is_pseudo": "0" - }, - "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { - "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", - "is_directional": "1", - "src_wire": "CLK_BUFG_IMUX29_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", - "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", - "is_directional": "1", "src_wire": "CLK_BUFG_R_FBG_OUT13", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX23_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK29": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK29" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX12_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL10_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL10_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK22": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK22" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX8_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX18_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX9_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL13_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL13_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK16": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK16" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX18_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT2" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX17_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX11_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX14_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL0_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL0_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL7_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL7_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL11_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL11_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL6_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT6" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL4_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL4_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT3" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK30": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL14_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK30" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK20": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK20" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL9_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL9_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL3_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL3_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL13_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT13" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK28": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK28" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT7" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX16_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX23_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX13_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_0->>CLK_BUFG_R_BUFGCTRL3_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX19_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK31": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK31" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL4_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT4" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL9_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT9" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT11" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX18_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK17": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK17" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK23": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL7_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK23" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX18_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK21": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK21" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX11_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL5_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT5" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL10_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT10" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL12_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL12_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL6_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL6_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL15_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL15_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX13_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX22_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL5_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL5_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK19": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL3_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK19" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL14_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL14_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX17_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX14_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX11_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX19_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX21_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK24": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK24" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK26": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL10_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK26" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK25": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL9_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK25" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL8_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT8" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX23_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL2_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL2_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL8_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL8_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX9_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX24_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX10_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK18": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL2_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK18" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL15_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT15" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL1_I0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_BUFG_BUFGCTRL1_O" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_TOP_R_CK_MUXED30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX20_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK27": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL11_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_CK_GCLK27" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_R_FBG_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { + "can_invert": "0", + "src_wire": "CLK_BUFG_BUFGCTRL12_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_FBG_OUT12" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX15_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { + "can_invert": "0", + "src_wire": "CLK_BUFG_IMUX17_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1" } }, - "tile_type": "CLK_BUFG_TOP_R" + "wires": [ + "CLK_HROW_SW4END1_2", + "CLK_BUFG_LOGIC_OUTS_B21_2", + "CLK_BUFG_IMUX20_1", + "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "CLK_HROW_WW2END3_2", + "CLK_BUFG_R_BUFGCTRL5_S1", + "CLK_BUFG_IMUX12_0", + "CLK_BUFG_IMUX24_1", + "CLK_HROW_SE4C2_1", + "CLK_HROW_BYP4_0", + "CLK_BUFG_IMUX12_1", + "CLK_BUFG_R_FBG_OUT13", + "CLK_HROW_WW4END1_1", + "CLK_HROW_BYP1_0", + "CLK_BUFG_R_FBG_OUT7", + "CLK_HROW_FAN2_2", + "CLK_BUFG_IMUX11_0", + "CLK_BUFG_R_CK_FB_TEST1_0", + "CLK_BUFG_R_CK_FB_TEST0_12", + "CLK_BUFG_TOP_R_CK_MUXED3", + "CLK_HROW_SW2A1_2", + "CLK_HROW_EL1BEG0_0", + "CLK_BUFG_IMUX15_3", + "CLK_HROW_NW2A1_3", + "CLK_BUFG_IMUX46_1", + "CLK_HROW_NW2A3_1", + "CLK_HROW_EE2BEG2_3", + "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "CLK_HROW_WW4C1_0", + "CLK_HROW_SW4A2_1", + "CLK_BUFG_IMUX15_1", + "CLK_HROW_LH1_0", + "CLK_HROW_WW4B0_2", + "CLK_HROW_WW4C2_0", + "CLK_BUFG_LOGIC_OUTS_B14_2", + "CLK_BUFG_IMUX46_2", + "CLK_BUFG_R_BUFGCTRL4_CE1", + "CLK_HROW_BYP7_2", + "CLK_HROW_BYP2_2", + "CLK_HROW_CLK1_3", + "CLK_BUFG_TOP_R_CK_MUXED16", + "CLK_HROW_WW4C0_2", + "CLK_HROW_EE2A3_1", + "CLK_HROW_WW2A0_0", + "CLK_BUFG_TOP_R_CK_MUXED14", + "CLK_HROW_SE2A0_1", + "CLK_HROW_WW4C2_2", + "CLK_BUFG_LOGIC_OUTS_B2_3", + "CLK_HROW_SE4C0_1", + "CLK_HROW_SW4A1_1", + "CLK_BUFG_LOGIC_OUTS_B16_1", + "CLK_BUFG_IMUX35_2", + "CLK_HROW_BYP5_1", + "CLK_BUFG_TOP_R_CK_MUXED15", + "CLK_BUFG_CK_GCLK27", + "CLK_HROW_WW4C3_2", + "CLK_BUFG_BUFGCTRL11_O", + "CLK_BUFG_R_BUFGCTRL1_CE1", + "CLK_BUFG_R_BUFGCTRL1_CE0", + "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "CLK_BUFG_CK_GCLK1", + "CLK_BUFG_LOGIC_OUTS_B4_1", + "CLK_HROW_WR1END3_2", + "CLK_BUFG_LOGIC_OUTS_B21_1", + "CLK_BUFG_BUFGCTRL7_I0", + "CLK_BUFG_R_BUFGCTRL1_S1", + "CLK_BUFG_CK_GCLK15", + "CLK_HROW_WW2END2_0", + "CLK_BUFG_IMUX7_1", + "CLK_BUFG_LOGIC_OUTS_B6_3", + "CLK_BUFG_IMUX20_0", + "CLK_HROW_FAN2_0", + "CLK_HROW_NW4A3_0", + "CLK_HROW_WL1END0_0", + "CLK_BUFG_LOGIC_OUTS_B22_0", + "CLK_HROW_EE4A0_1", + "CLK_BUFG_IMUX3_2", + "CLK_HROW_SW2A2_2", + "CLK_BUFG_R_BUFGCTRL12_CE0", + "CLK_BUFG_IMUX15_0", + "CLK_BUFG_R_BUFGCTRL4_CE0", + "CLK_BUFG_R_BUFGCTRL4_S0", + "CLK_HROW_BYP6_0", + "CLK_HROW_EE4A3_0", + "CLK_BUFG_IMUX23_1", + "CLK_HROW_WW4END3_0", + "CLK_BUFG_BUFGCTRL10_I1", + "CLK_BUFG_LOGIC_OUTS_B12_1", + "CLK_HROW_NW4END0_0", + "CLK_BUFG_IMUX7_2", + "CLK_BUFG_IMUX18_0", + "CLK_BUFG_IMUX9_0", + "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "CLK_HROW_BYP5_0", + "CLK_BUFG_IMUX46_0", + "CLK_BUFG_R_FBG_OUT2", + "CLK_BUFG_BUFGCTRL12_I0", + "CLK_HROW_FAN4_1", + "CLK_HROW_LH7_2", + "CLK_BUFG_IMUX37_0", + "CLK_BUFG_R_BUFGCTRL15_CE0", + "CLK_BUFG_LOGIC_OUTS_B9_1", + "CLK_BUFG_CK_GCLK7", + "CLK_HROW_ER1BEG3_0", + "CLK_BUFG_R_BUFGCTRL6_CE1", + "CLK_HROW_WW4END1_3", + "CLK_HROW_NW4A0_3", + "CLK_BUFG_R_BUFGCTRL9_S1", + "CLK_BUFG_CK_GCLK22", + "CLK_HROW_LH3_1", + "CLK_HROW_SW2A1_1", + "CLK_BUFG_R_BUFGCTRL8_CE0", + "CLK_BUFG_LOGIC_OUTS_B8_2", + "CLK_BUFG_IMUX30_2", + "CLK_HROW_LH10_2", + "CLK_HROW_CTRL1_3", + "CLK_BUFG_IMUX43_0", + "CLK_HROW_NW4END1_1", + "CLK_HROW_WW4C2_3", + "CLK_BUFG_IMUX34_0", + "CLK_HROW_WW2END0_0", + "CLK_HROW_ER1BEG2_1", + "CLK_BUFG_TOP_R_CK_MUXED20", + "CLK_HROW_SE4BEG0_3", + "CLK_BUFG_IMUX6_3", + "CLK_BUFG_R_BUFGCTRL6_S1", + "CLK_HROW_LH2_1", + "CLK_HROW_LH4_0", + "CLK_BUFG_TOP_R_CK_MUXED23", + "CLK_HROW_EE4B2_1", + "CLK_BUFG_R_BUFGCTRL13_S1", + "CLK_BUFG_CK_GCLK9", + "CLK_BUFG_IMUX31_0", + "CLK_HROW_MONITOR_N_3", + "CLK_HROW_NW2A3_2", + "CLK_HROW_MONITOR_P_3", + "CLK_BUFG_IMUX3_0", + "CLK_HROW_NE4C0_0", + "CLK_HROW_LH1_1", + "CLK_HROW_MONITOR_P_1", + "CLK_BUFG_LOGIC_OUTS_B15_0", + "CLK_BUFG_R_BUFGCTRL15_S0", + "CLK_HROW_EE4BEG3_2", + "CLK_BUFG_R_FBG_OUT14", + "CLK_BUFG_IMUX28_0", + "CLK_HROW_WL1END3_3", + "CLK_BUFG_LOGIC_OUTS_B9_2", + "CLK_HROW_NW4END3_2", + "CLK_BUFG_LOGIC_OUTS_B4_0", + "CLK_HROW_EE4BEG3_3", + "CLK_HROW_WR1END3_0", + "CLK_BUFG_LOGIC_OUTS_B23_2", + "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "CLK_BUFG_IMUX39_3", + "CLK_HROW_EL1BEG3_3", + "CLK_BUFG_IMUX14_1", + "CLK_HROW_EE4A0_3", + "CLK_BUFG_LOGIC_OUTS_B13_1", + "CLK_BUFG_LOGIC_OUTS_B3_0", + "CLK_BUFG_CK_GCLK6", + "CLK_HROW_WW4END1_0", + "CLK_HROW_BLOCK_OUTS_B1_0", + "CLK_HROW_FAN0_3", + "CLK_BUFG_IMUX10_1", + "CLK_BUFG_R_BUFGCTRL12_CE1", + "CLK_HROW_BLOCK_OUTS_B2_1", + "CLK_BUFG_TOP_R_CK_MUXED27", + "CLK_BUFG_IMUX13_3", + "CLK_HROW_SW4A3_2", + "CLK_BUFG_IMUX25_1", + "CLK_HROW_SW4A2_2", + "CLK_HROW_SE4C2_0", + "CLK_BUFG_IMUX16_2", + "CLK_HROW_EE2A0_2", + "CLK_BUFG_LOGIC_OUTS_B10_1", + "CLK_HROW_BLOCK_OUTS_B3_1", + "CLK_BUFG_R_CK_FB_TEST1_4", + "CLK_HROW_SE4BEG2_3", + "CLK_BUFG_R_BUFGCTRL5_CE1", + "CLK_HROW_LH8_2", + "CLK_HROW_EE2A1_0", + "CLK_HROW_WW4END3_3", + "CLK_HROW_SW4END0_2", + "CLK_HROW_WW4A1_1", + "CLK_BUFG_IMUX12_2", + "CLK_HROW_NW2A2_1", + "CLK_HROW_NE4C0_3", + "CLK_HROW_BYP7_0", + "CLK_HROW_EL1BEG3_2", + "CLK_BUFG_LOGIC_OUTS_B6_2", + "CLK_HROW_CTRL0_3", + "CLK_HROW_EE4B3_3", + "CLK_BUFG_IMUX35_0", + "CLK_BUFG_R_BUFGCTRL0_CE1", + "CLK_HROW_SW4END2_2", + "CLK_HROW_BYP1_2", + "CLK_BUFG_TOP_R_CK_MUXED18", + "CLK_HROW_BYP2_0", + "CLK_HROW_EE2BEG2_0", + "CLK_HROW_WW4C1_1", + "CLK_BUFG_R_CK_FB_TEST0_0", + "CLK_HROW_NW2A1_1", + "CLK_BUFG_IMUX41_2", + "CLK_HROW_FAN1_0", + "CLK_HROW_BYP4_1", + "CLK_BUFG_R_BUFGCTRL13_CE1", + "CLK_HROW_CLK0_3", + "CLK_BUFG_R_BUFGCTRL3_S0", + "CLK_HROW_LH10_3", + "CLK_BUFG_LOGIC_OUTS_B8_3", + "CLK_BUFG_IMUX4_2", + "CLK_BUFG_IMUX24_0", + "CLK_BUFG_TOP_R_CK_MUXED1", + "CLK_HROW_NE4C2_3", + "CLK_HROW_WW4B0_1", + "CLK_HROW_BLOCK_OUTS_B2_2", + "CLK_BUFG_LOGIC_OUTS_B5_1", + "CLK_BUFG_CK_GCLK23", + "CLK_BUFG_R_BUFGCTRL10_S1", + "CLK_BUFG_IMUX25_0", + "CLK_HROW_EE2BEG0_2", + "CLK_BUFG_R_FBG_OUT5", + "CLK_BUFG_IMUX4_3", + "CLK_BUFG_IMUX31_3", + "CLK_HROW_CLK1_2", + "CLK_HROW_WR1END2_0", + "CLK_BUFG_IMUX43_3", + "CLK_BUFG_LOGIC_OUTS_B4_2", + "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "CLK_HROW_LH2_2", + "CLK_HROW_SW2A0_0", + "CLK_BUFG_BUFGCTRL1_O", + "CLK_BUFG_IMUX17_2", + "CLK_HROW_WW4END3_2", + "CLK_HROW_WW4B2_1", + "CLK_HROW_SE4C2_2", + "CLK_HROW_SW4END3_3", + "CLK_HROW_SE4BEG1_2", + "CLK_BUFG_IMUX16_3", + "CLK_HROW_WW4END0_3", + "CLK_BUFG_IMUX26_3", + "CLK_HROW_WW4C1_2", + "CLK_HROW_NE4BEG0_3", + "CLK_HROW_ER1BEG3_3", + "CLK_BUFG_CK_GCLK16", + "CLK_HROW_NE2A2_1", + "CLK_BUFG_IMUX5_3", + "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "CLK_BUFG_BUFGCTRL13_I0", + "CLK_BUFG_R_CK_FB_TEST1_7", + "CLK_HROW_WW4A3_0", + "CLK_HROW_BYP6_1", + "CLK_BUFG_IMUX38_3", + "CLK_HROW_WW2A3_2", + "CLK_HROW_WR1END3_3", + "CLK_BUFG_IMUX40_0", + "CLK_BUFG_LOGIC_OUTS_B23_0", + "CLK_HROW_SE4C0_3", + "CLK_BUFG_BUFGCTRL9_I1", + "CLK_HROW_WW4B1_1", + "CLK_BUFG_BUFGCTRL14_I0", + "CLK_BUFG_LOGIC_OUTS_B21_3", + "CLK_BUFG_LOGIC_OUTS_B0_1", + "CLK_BUFG_IMUX17_0", + "CLK_BUFG_IMUX8_0", + "CLK_HROW_EE4BEG1_0", + "CLK_BUFG_LOGIC_OUTS_B16_3", + "CLK_BUFG_R_BUFGCTRL2_S1", + "CLK_BUFG_LOGIC_OUTS_B17_3", + "CLK_BUFG_IMUX6_2", + "CLK_HROW_EE4B0_3", + "CLK_HROW_CTRL1_0", + "CLK_HROW_NW4A3_1", + "CLK_BUFG_IMUX26_0", + "CLK_BUFG_TOP_R_CK_MUXED2", + "CLK_BUFG_BUFGCTRL15_I1", + "CLK_HROW_WW2END1_0", + "CLK_HROW_NW4END2_3", + "CLK_HROW_NE2A2_0", + "CLK_BUFG_IMUX41_3", + "CLK_HROW_SE4C3_3", + "CLK_HROW_NW2A2_2", + "CLK_HROW_BLOCK_OUTS_B3_0", + "CLK_HROW_SE2A1_2", + "CLK_HROW_FAN4_2", + "CLK_HROW_WL1END1_1", + "CLK_BUFG_LOGIC_OUTS_B10_0", + "CLK_HROW_CLK0_1", + "CLK_BUFG_TOP_R_CK_MUXED0", + "CLK_BUFG_R_BUFGCTRL2_S0", + "CLK_HROW_SE4BEG2_0", + "CLK_BUFG_TOP_R_CK_MUXED19", + "CLK_BUFG_IMUX11_2", + "CLK_BUFG_IMUX22_0", + "CLK_HROW_NE4C2_2", + "CLK_HROW_FAN3_2", + "CLK_BUFG_LOGIC_OUTS_B11_0", + "CLK_HROW_EE4C2_0", + "CLK_BUFG_IMUX22_3", + "CLK_HROW_SE4BEG3_3", + "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "CLK_HROW_NW2A0_1", + "CLK_BUFG_LOGIC_OUTS_B17_1", + "CLK_BUFG_IMUX35_3", + "CLK_HROW_NE4BEG3_3", + "CLK_BUFG_BUFGCTRL13_I1", + "CLK_BUFG_IMUX5_2", + "CLK_HROW_WL1END2_0", + "CLK_HROW_NW4A0_1", + "CLK_HROW_EE4B2_0", + "CLK_HROW_WW4B1_0", + "CLK_HROW_EE4BEG0_2", + "CLK_HROW_EE4A2_2", + "CLK_HROW_FAN5_1", + "CLK_BUFG_LOGIC_OUTS_B7_2", + "CLK_BUFG_LOGIC_OUTS_B2_2", + "CLK_BUFG_R_BUFGCTRL3_S1", + "CLK_HROW_WL1END1_0", + "CLK_HROW_WW4B3_0", + "CLK_HROW_LH9_1", + "CLK_BUFG_BUFGCTRL11_I0", + "CLK_HROW_EE2A0_1", + "CLK_BUFG_BUFGCTRL5_I1", + "CLK_HROW_NW4END1_3", + "CLK_HROW_BYP0_0", + "CLK_HROW_WW4A1_0", + "CLK_HROW_WW2A2_2", + "CLK_HROW_LH2_0", + "CLK_BUFG_LOGIC_OUTS_B18_1", + "CLK_BUFG_IMUX0_1", + "CLK_HROW_WW4A3_1", + "CLK_HROW_NW2A2_3", + "CLK_HROW_FAN7_3", + "CLK_BUFG_LOGIC_OUTS_B18_0", + "CLK_HROW_NE2A0_0", + "CLK_HROW_EE4A2_3", + "CLK_BUFG_IMUX10_3", + "CLK_HROW_FAN7_2", + "CLK_BUFG_IMUX5_1", + "CLK_HROW_FAN0_1", + "CLK_BUFG_LOGIC_OUTS_B1_3", + "CLK_HROW_SE2A1_3", + "CLK_BUFG_LOGIC_OUTS_B13_3", + "CLK_HROW_WW4END0_1", + "CLK_BUFG_R_BUFGCTRL10_CE0", + "CLK_BUFG_IMUX9_2", + "CLK_HROW_LH5_2", + "CLK_HROW_WW2END3_3", + "CLK_HROW_EL1BEG0_1", + "CLK_HROW_SW2A1_0", + "CLK_HROW_WL1END3_2", + "CLK_HROW_SE4BEG3_1", + "CLK_BUFG_IMUX44_0", + "CLK_BUFG_R_BUFGCTRL8_CE1", + "CLK_HROW_NW2A0_2", + "CLK_HROW_NW4A1_3", + "CLK_BUFG_CK_GCLK5", + "CLK_BUFG_IMUX23_3", + "CLK_HROW_NE2A3_1", + "CLK_HROW_BYP2_1", + "CLK_BUFG_IMUX21_2", + "CLK_HROW_NW4A1_1", + "CLK_HROW_WW2END1_3", + "CLK_HROW_WL1END2_1", + "CLK_BUFG_R_BUFGCTRL6_CE0", + "CLK_HROW_WW2END2_2", + "CLK_BUFG_TOP_R_CK_MUXED21", + "CLK_BUFG_R_FBG_OUT0", + "CLK_BUFG_R_CK_FB_TEST0_4", + "CLK_BUFG_IMUX3_1", + "CLK_HROW_WW4B1_3", + "CLK_BUFG_LOGIC_OUTS_B7_3", + "CLK_BUFG_LOGIC_OUTS_B1_2", + "CLK_HROW_SE2A1_1", + "CLK_BUFG_IMUX8_3", + "CLK_HROW_EL1BEG1_2", + "CLK_BUFG_IMUX29_0", + "CLK_HROW_WW4C0_3", + "CLK_HROW_EL1BEG0_3", + "CLK_BUFG_BUFGCTRL9_I0", + "CLK_BUFG_LOGIC_OUTS_B9_0", + "CLK_HROW_EE4B1_2", + "CLK_BUFG_R_BUFGCTRL15_S1", + "CLK_HROW_BLOCK_OUTS_B0_2", + "CLK_BUFG_BUFGCTRL7_O", + "CLK_BUFG_IMUX3_3", + "CLK_HROW_EE2A3_0", + "CLK_BUFG_BUFGCTRL1_I0", + "CLK_HROW_NE2A0_3", + "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "CLK_HROW_CLK1_0", + "CLK_HROW_LH4_2", + "CLK_BUFG_LOGIC_OUTS_B8_1", + "CLK_HROW_WR1END2_3", + "CLK_HROW_WW4B0_0", + "CLK_BUFG_BUFGCTRL11_I1", + "CLK_HROW_CTRL0_1", + "CLK_BUFG_R_BUFGCTRL12_S1", + "CLK_BUFG_CK_GCLK0", + "CLK_BUFG_R_FBG_OUT1", + "CLK_BUFG_BUFGCTRL15_O", + "CLK_BUFG_IMUX47_0", + "CLK_HROW_SW4A1_0", + "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "CLK_BUFG_R_BUFGCTRL15_CE1", + "CLK_HROW_BYP3_1", + "CLK_HROW_BLOCK_OUTS_B3_2", + "CLK_BUFG_R_CK_FB_TEST1_9", + "CLK_BUFG_BUFGCTRL3_O", + "CLK_HROW_EL1BEG2_3", + "CLK_BUFG_LOGIC_OUTS_B7_1", + "CLK_HROW_EE2BEG1_3", + "CLK_BUFG_IMUX13_0", + "CLK_HROW_LH1_3", + "CLK_HROW_FAN1_3", + "CLK_HROW_WW2END2_1", + "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "CLK_BUFG_IMUX2_3", + "CLK_HROW_NE2A2_3", + "CLK_BUFG_R_BUFGCTRL8_S1", + "CLK_HROW_NW4A0_2", + "CLK_BUFG_IMUX30_0", + "CLK_BUFG_R_BUFGCTRL0_S1", + "CLK_BUFG_BUFGCTRL2_I0", + "CLK_BUFG_TOP_R_CK_MUXED7", + "CLK_BUFG_LOGIC_OUTS_B14_1", + "CLK_HROW_WW4A0_0", + "CLK_HROW_NE4C3_2", + "CLK_HROW_EE4BEG3_1", + "CLK_BUFG_TOP_R_CK_MUXED6", + "CLK_HROW_NE2A1_0", + "CLK_BUFG_LOGIC_OUTS_B3_2", + "CLK_HROW_NW4A2_2", + "CLK_HROW_SE4BEG0_1", + "CLK_HROW_SW4A1_3", + "CLK_BUFG_R_CK_FB_TEST0_2", + "CLK_BUFG_IMUX13_1", + "CLK_HROW_WW2A0_2", + "CLK_BUFG_BUFGCTRL6_I1", + "CLK_BUFG_BUFGCTRL6_O", + "CLK_BUFG_IMUX22_2", + "CLK_HROW_BYP7_1", + "CLK_BUFG_IMUX43_2", + "CLK_HROW_CTRL0_0", + "CLK_HROW_EE4C0_3", + "CLK_BUFG_R_BUFGCTRL6_S0", + "CLK_BUFG_IMUX11_1", + "CLK_BUFG_R_FBG_OUT12", + "CLK_BUFG_IMUX11_3", + "CLK_BUFG_BUFGCTRL14_O", + "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "CLK_HROW_CLK0_2", + "CLK_HROW_NW4END3_0", + "CLK_HROW_BLOCK_OUTS_B0_0", + "CLK_BUFG_IMUX32_0", + "CLK_HROW_EE4C0_1", + "CLK_HROW_SE2A3_1", + "CLK_HROW_SW2A3_3", + "CLK_HROW_FAN7_0", + "CLK_HROW_EE4A2_1", + "CLK_HROW_EE4BEG1_1", + "CLK_HROW_SE2A3_0", + "CLK_HROW_SE4C3_1", + "CLK_HROW_EE2A1_3", + "CLK_HROW_WR1END1_3", + "CLK_HROW_EE4BEG2_1", + "CLK_BUFG_R_BUFGCTRL9_CE0", + "CLK_HROW_SW2A3_1", + "CLK_HROW_SE2A2_1", + "CLK_HROW_WW4END2_2", + "CLK_HROW_WR1END0_2", + "CLK_BUFG_IMUX28_3", + "CLK_HROW_WW2A3_0", + "CLK_BUFG_R_FBG_OUT9", + "CLK_BUFG_BUFGCTRL0_I1", + "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "CLK_HROW_EE4B2_2", + "CLK_BUFG_IMUX7_3", + "CLK_BUFG_LOGIC_OUTS_B5_2", + "CLK_HROW_WW4END1_2", + "CLK_HROW_WW4B3_3", + "CLK_BUFG_LOGIC_OUTS_B22_2", + "CLK_HROW_SW4END1_0", + "CLK_BUFG_BUFGCTRL1_I1", + "CLK_BUFG_LOGIC_OUTS_B20_2", + "CLK_BUFG_IMUX12_3", + "CLK_BUFG_IMUX42_3", + "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "CLK_BUFG_IMUX4_0", + "CLK_HROW_EE2A3_2", + "CLK_HROW_SW4A0_3", + "CLK_BUFG_IMUX16_1", + "CLK_HROW_WW2A3_1", + "CLK_HROW_WW4B3_1", + "CLK_BUFG_IMUX18_2", + "CLK_HROW_NW4END3_3", + "CLK_HROW_WW4END3_1", + "CLK_BUFG_IMUX38_1", + "CLK_HROW_EE2BEG3_1", + "CLK_BUFG_IMUX31_1", + "CLK_HROW_NW4END1_0", + "CLK_HROW_WW4A0_2", + "CLK_HROW_NW4A2_3", + "CLK_HROW_NE4C1_3", + "CLK_HROW_EE4B2_3", + "CLK_BUFG_LOGIC_OUTS_B22_3", + "CLK_HROW_FAN3_1", + "CLK_HROW_NW4END1_2", + "CLK_HROW_FAN4_3", + "CLK_HROW_CLK1_1", + "CLK_HROW_WR1END2_2", + "CLK_BUFG_IMUX45_2", + "CLK_BUFG_CK_GCLK13", + "CLK_BUFG_R_BUFGCTRL10_S0", + "CLK_BUFG_IMUX36_2", + "CLK_HROW_EE4C0_0", + "CLK_BUFG_LOGIC_OUTS_B1_1", + "CLK_HROW_SE2A0_0", + "CLK_BUFG_R_BUFGCTRL9_S0", + "CLK_HROW_NE4C1_0", + "CLK_BUFG_LOGIC_OUTS_B8_0", + "CLK_HROW_EE2BEG1_1", + "CLK_BUFG_IMUX40_1", + "CLK_BUFG_CK_GCLK10", + "CLK_BUFG_IMUX8_2", + "CLK_HROW_EE4C3_0", + "CLK_BUFG_R_FBG_OUT6", + "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "CLK_HROW_SW4END3_0", + "CLK_BUFG_IMUX19_0", + "CLK_BUFG_IMUX27_3", + "CLK_HROW_NW4A2_1", + "CLK_BUFG_IMUX23_2", + "CLK_BUFG_LOGIC_OUTS_B12_3", + "CLK_BUFG_IMUX1_2", + "CLK_HROW_SW4END0_0", + "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "CLK_HROW_EE2BEG3_3", + "CLK_BUFG_IMUX8_1", + "CLK_HROW_EE4B0_2", + "CLK_BUFG_IMUX25_3", + "CLK_HROW_WL1END2_3", + "CLK_HROW_EE4C1_0", + "CLK_HROW_WW2END3_0", + "CLK_BUFG_LOGIC_OUTS_B19_2", + "CLK_HROW_WR1END2_1", + "CLK_BUFG_LOGIC_OUTS_B19_0", + "CLK_HROW_LH8_3", + "CLK_HROW_FAN7_1", + "CLK_BUFG_IMUX47_2", + "CLK_BUFG_LOGIC_OUTS_B1_0", + "CLK_BUFG_R_CK_FB_TEST1_6", + "CLK_HROW_SE4BEG1_3", + "CLK_BUFG_LOGIC_OUTS_B10_3", + "CLK_BUFG_IMUX25_2", + "CLK_HROW_LH6_0", + "CLK_HROW_LH7_0", + "CLK_BUFG_IMUX24_2", + "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "CLK_BUFG_IMUX18_3", + "CLK_HROW_LH12_2", + "CLK_BUFG_IMUX0_2", + "CLK_BUFG_R_CK_FB_TEST0_9", + "CLK_BUFG_LOGIC_OUTS_B14_0", + "CLK_HROW_EE2BEG1_2", + "CLK_HROW_WW2END2_3", + "CLK_BUFG_IMUX31_2", + "CLK_HROW_EE4B1_1", + "CLK_HROW_NE4BEG2_2", + "CLK_BUFG_IMUX40_3", + "CLK_HROW_NE2A2_2", + "CLK_HROW_SE4C1_1", + "CLK_HROW_BLOCK_OUTS_B1_3", + "CLK_HROW_SE4C1_2", + "CLK_HROW_EE4C3_1", + "CLK_HROW_SW2A2_1", + "CLK_HROW_EE2BEG0_0", + "CLK_BUFG_BUFGCTRL8_I1", + "CLK_BUFG_IMUX45_3", + "CLK_HROW_BLOCK_OUTS_B0_1", + "CLK_BUFG_LOGIC_OUTS_B13_2", + "CLK_BUFG_R_BUFGCTRL0_S0", + "CLK_HROW_WW2A1_3", + "CLK_BUFG_IMUX42_0", + "CLK_BUFG_BUFGCTRL3_I1", + "CLK_HROW_EE4A1_2", + "CLK_HROW_MONITOR_P_0", + "CLK_HROW_NE4BEG1_2", + "CLK_HROW_NW2A2_0", + "CLK_BUFG_LOGIC_OUTS_B23_1", + "CLK_HROW_NE2A3_3", + "CLK_BUFG_R_BUFGCTRL11_S1", + "CLK_BUFG_CK_GCLK3", + "CLK_BUFG_LOGIC_OUTS_B22_1", + "CLK_BUFG_LOGIC_OUTS_B16_2", + "CLK_BUFG_IMUX23_0", + "CLK_BUFG_IMUX44_2", + "CLK_BUFG_R_BUFGCTRL5_S0", + "CLK_HROW_EE2A3_3", + "CLK_BUFG_IMUX37_3", + "CLK_HROW_SW4END2_1", + "CLK_BUFG_IMUX32_2", + "CLK_BUFG_CK_GCLK21", + "CLK_BUFG_R_FBG_OUT8", + "CLK_BUFG_BUFGCTRL9_O", + "CLK_HROW_SE2A3_3", + "CLK_HROW_NE4C0_1", + "CLK_HROW_EE4C3_2", + "CLK_HROW_NW4A1_0", + "CLK_BUFG_LOGIC_OUTS_B18_2", + "CLK_BUFG_LOGIC_OUTS_B11_1", + "CLK_HROW_ER1BEG1_0", + "CLK_BUFG_LOGIC_OUTS_B16_0", + "CLK_HROW_EE2A2_1", + "CLK_HROW_EE4BEG1_2", + "CLK_BUFG_CK_GCLK17", + "CLK_BUFG_IMUX10_2", + "CLK_BUFG_R_CK_FB_TEST0_5", + "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "CLK_HROW_WW4A0_1", + "CLK_HROW_ER1BEG3_2", + "CLK_HROW_EE2BEG2_1", + "CLK_HROW_SE4BEG1_0", + "CLK_HROW_NE4BEG2_1", + "CLK_BUFG_IMUX30_3", + "CLK_HROW_EE4A1_1", + "CLK_BUFG_R_CK_FB_TEST0_3", + "CLK_HROW_NW4END0_3", + "CLK_HROW_CTRL1_1", + "CLK_BUFG_LOGIC_OUTS_B13_0", + "CLK_BUFG_R_CK_FB_TEST0_15", + "CLK_HROW_SW4A1_2", + "CLK_BUFG_R_CK_FB_TEST0_1", + "CLK_HROW_EE4A1_3", + "CLK_HROW_FAN6_3", + "CLK_HROW_SW2A2_0", + "CLK_HROW_LH11_2", + "CLK_BUFG_IMUX20_2", + "CLK_BUFG_R_CK_FB_TEST1_13", + "CLK_HROW_LH12_3", + "CLK_HROW_SW2A2_3", + "CLK_BUFG_BUFGCTRL4_I1", + "CLK_BUFG_IMUX44_3", + "CLK_BUFG_LOGIC_OUTS_B5_0", + "CLK_HROW_SE2A0_2", + "CLK_HROW_NE2A1_1", + "CLK_BUFG_IMUX46_3", + "CLK_HROW_EE4B0_0", + "CLK_HROW_FAN6_0", + "CLK_HROW_EE2BEG0_1", + "CLK_HROW_EE4A3_3", + "CLK_HROW_NE4C1_1", + "CLK_BUFG_BUFGCTRL5_I0", + "CLK_HROW_LH10_1", + "CLK_HROW_BYP0_3", + "CLK_HROW_EE4C1_3", + "CLK_HROW_CTRL1_2", + "CLK_BUFG_IMUX30_1", + "CLK_HROW_NW2A3_3", + "CLK_BUFG_R_BUFGCTRL11_CE1", + "CLK_HROW_SE4BEG0_0", + "CLK_HROW_LH5_3", + "CLK_BUFG_BUFGCTRL10_I0", + "CLK_BUFG_R_CK_FB_TEST1_3", + "CLK_BUFG_LOGIC_OUTS_B2_0", + "CLK_HROW_SE2A2_0", + "CLK_HROW_SW4END3_1", + "CLK_BUFG_R_CK_FB_TEST1_5", + "CLK_HROW_NE2A0_1", + "CLK_BUFG_LOGIC_OUTS_B15_1", + "CLK_BUFG_R_CK_FB_TEST1_10", + "CLK_BUFG_IMUX18_1", + "CLK_HROW_WR1END1_1", + "CLK_HROW_SW2A3_0", + "CLK_HROW_LH3_0", + "CLK_HROW_BLOCK_OUTS_B1_2", + "CLK_HROW_EE4A0_0", + "CLK_HROW_WR1END0_1", + "CLK_BUFG_LOGIC_OUTS_B0_3", + "CLK_BUFG_LOGIC_OUTS_B4_3", + "CLK_HROW_SW4A2_0", + "CLK_HROW_EE2A0_3", + "CLK_HROW_NW4A3_3", + "CLK_BUFG_LOGIC_OUTS_B7_0", + "CLK_HROW_WW2A1_1", + "CLK_BUFG_CK_GCLK2", + "CLK_BUFG_LOGIC_OUTS_B18_3", + "CLK_BUFG_BUFGCTRL0_I0", + "CLK_HROW_NW4END3_1", + "CLK_BUFG_TOP_R_CK_MUXED22", + "CLK_HROW_LH9_2", + "CLK_BUFG_IMUX9_1", + "CLK_HROW_FAN2_1", + "CLK_BUFG_R_CK_FB_TEST0_11", + "CLK_HROW_LH10_0", + "CLK_HROW_ER1BEG0_1", + "CLK_BUFG_IMUX9_3", + "CLK_HROW_EE2BEG3_0", + "CLK_HROW_WW2A0_1", + "CLK_HROW_ER1BEG1_1", + "CLK_HROW_MONITOR_P_2", + "CLK_HROW_WW2A2_3", + "CLK_HROW_NE4BEG0_1", + "CLK_BUFG_LOGIC_OUTS_B15_2", + "CLK_BUFG_BUFGCTRL10_O", + "CLK_HROW_WL1END3_0", + "CLK_HROW_LH6_1", + "CLK_HROW_SE4C1_0", + "CLK_BUFG_CK_GCLK25", + "CLK_HROW_EE4B3_2", + "CLK_HROW_BLOCK_OUTS_B3_3", + "CLK_HROW_SW2A0_1", + "CLK_BUFG_CK_GCLK18", + "CLK_HROW_LH3_3", + "CLK_BUFG_IMUX24_3", + "CLK_HROW_NW4END0_2", + "CLK_HROW_WW2END0_2", + "CLK_BUFG_CK_GCLK11", + "CLK_BUFG_IMUX33_0", + "CLK_HROW_WW4A1_2", + "CLK_BUFG_LOGIC_OUTS_B11_2", + "CLK_BUFG_R_FBG_OUT11", + "CLK_BUFG_R_FBG_OUT10", + "CLK_HROW_WW4A2_3", + "CLK_HROW_BYP5_3", + "CLK_HROW_EE4BEG0_3", + "CLK_BUFG_LOGIC_OUTS_B23_3", + "CLK_HROW_LH1_2", + "CLK_BUFG_LOGIC_OUTS_B9_3", + "CLK_HROW_WW4END0_2", + "CLK_HROW_BYP1_3", + "CLK_BUFG_CK_GCLK30", + "CLK_BUFG_CK_GCLK28", + "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "CLK_HROW_LH7_1", + "CLK_HROW_BLOCK_OUTS_B1_1", + "CLK_HROW_EL1BEG2_1", + "CLK_BUFG_IMUX20_3", + "CLK_HROW_EE4C2_3", + "CLK_BUFG_BUFGCTRL2_I1", + "CLK_HROW_ER1BEG1_2", + "CLK_BUFG_IMUX22_1", + "CLK_HROW_WW4END0_0", + "CLK_BUFG_LOGIC_OUTS_B19_3", + "CLK_BUFG_IMUX0_0", + "CLK_HROW_BYP4_3", + "CLK_HROW_WW2END0_1", + "CLK_BUFG_R_CK_FB_TEST0_8", + "CLK_HROW_SW4A0_0", + "CLK_BUFG_TOP_R_CK_MUXED13", + "CLK_HROW_WW4END2_1", + "CLK_HROW_SW4END1_3", + "CLK_BUFG_IMUX34_2", + "CLK_BUFG_IMUX1_1", + "CLK_BUFG_BUFGCTRL15_I0", + "CLK_HROW_BYP3_0", + "CLK_HROW_EE4A1_0", + "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B21_0", + "CLK_HROW_EL1BEG0_2", + "CLK_BUFG_R_BUFGCTRL0_CE0", + "CLK_BUFG_LOGIC_OUTS_B6_0", + "CLK_HROW_WW4C3_3", + "CLK_HROW_NE4BEG2_3", + "CLK_HROW_SE4BEG3_0", + "CLK_BUFG_IMUX40_2", + "CLK_BUFG_R_BUFGCTRL7_CE1", + "CLK_BUFG_CK_GCLK8", + "CLK_HROW_ER1BEG2_2", + "CLK_HROW_EL1BEG1_3", + "CLK_BUFG_R_CK_FB_TEST1_12", + "CLK_HROW_WL1END1_2", + "CLK_BUFG_R_BUFGCTRL13_S0", + "CLK_BUFG_LOGIC_OUTS_B19_1", + "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "CLK_HROW_FAN0_0", + "CLK_HROW_SW4A3_1", + "CLK_BUFG_IMUX21_3", + "CLK_HROW_NW4A2_0", + "CLK_HROW_NE4C2_0", + "CLK_HROW_WW2A0_3", + "CLK_HROW_WW2END1_2", + "CLK_HROW_LH12_0", + "CLK_BUFG_CK_GCLK14", + "CLK_HROW_NW2A1_2", + "CLK_BUFG_IMUX6_1", + "CLK_BUFG_LOGIC_OUTS_B12_2", + "CLK_BUFG_IMUX43_1", + "CLK_BUFG_IMUX32_1", + "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "CLK_BUFG_BUFGCTRL0_O", + "CLK_BUFG_LOGIC_OUTS_B12_0", + "CLK_HROW_EE4A3_1", + "CLK_HROW_WW4C0_1", + "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "CLK_BUFG_CK_GCLK31", + "CLK_BUFG_BUFGCTRL2_O", + "CLK_HROW_BYP5_2", + "CLK_BUFG_R_BUFGCTRL9_CE1", + "CLK_HROW_LH5_0", + "CLK_BUFG_LOGIC_OUTS_B20_3", + "CLK_BUFG_R_BUFGCTRL3_CE1", + "CLK_BUFG_TOP_R_CK_MUXED31", + "CLK_BUFG_R_CK_FB_TEST0_14", + "CLK_HROW_WR1END0_3", + "CLK_BUFG_LOGIC_OUTS_B3_1", + "CLK_HROW_LH6_2", + "CLK_BUFG_IMUX19_1", + "CLK_HROW_NW4A1_2", + "CLK_HROW_EL1BEG1_1", + "CLK_HROW_EE4C2_1", + "CLK_HROW_SW4END2_3", + "CLK_HROW_SE2A2_3", + "CLK_HROW_BYP3_2", + "CLK_HROW_LH11_0", + "CLK_BUFG_LOGIC_OUTS_B20_0", + "CLK_HROW_NE4C2_1", + "CLK_BUFG_IMUX28_2", + "CLK_HROW_WW2A3_3", + "CLK_HROW_LH7_3", + "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "CLK_HROW_NW2A0_3", + "CLK_HROW_WW4B2_2", + "CLK_BUFG_IMUX41_1", + "CLK_BUFG_R_CK_FB_TEST1_14", + "CLK_BUFG_TOP_R_CK_MUXED10", + "CLK_HROW_EE4BEG2_2", + "CLK_BUFG_CK_GCLK29", + "CLK_BUFG_BUFGCTRL5_O", + "CLK_BUFG_R_BUFGCTRL11_S0", + "CLK_HROW_SE4BEG3_2", + "CLK_BUFG_R_BUFGCTRL13_CE0", + "CLK_HROW_ER1BEG2_3", + "CLK_HROW_BYP4_2", + "CLK_HROW_WW4B0_3", + "CLK_BUFG_TOP_R_CK_MUXED28", + "CLK_HROW_LH8_1", + "CLK_HROW_NW4END0_1", + "CLK_BUFG_IMUX29_1", + "CLK_BUFG_IMUX39_2", + "CLK_HROW_BYP6_3", + "CLK_HROW_EE4A2_0", + "CLK_HROW_FAN2_3", + "CLK_BUFG_IMUX27_0", + "CLK_BUFG_TOP_R_CK_MUXED12", + "CLK_BUFG_TOP_R_CK_MUXED11", + "CLK_BUFG_CK_GCLK24", + "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "CLK_HROW_CLK0_0", + "CLK_BUFG_IMUX5_0", + "CLK_BUFG_CK_GCLK4", + "CLK_BUFG_TOP_R_CK_MUXED8", + "CLK_BUFG_IMUX34_1", + "CLK_HROW_NW2A3_0", + "CLK_HROW_NE4C3_0", + "CLK_HROW_LH6_3", + "CLK_HROW_BYP0_2", + "CLK_BUFG_BUFGCTRL12_O", + "CLK_BUFG_BUFGCTRL8_O", + "CLK_BUFG_TOP_R_CK_MUXED24", + "CLK_HROW_NE2A1_2", + "CLK_HROW_EE4A0_2", + "CLK_HROW_EE2A0_0", + "CLK_BUFG_IMUX26_1", + "CLK_HROW_WW4C2_1", + "CLK_BUFG_TOP_R_CK_MUXED25", + "CLK_HROW_SE4C1_3", + "CLK_HROW_WW4B2_3", + "CLK_BUFG_TOP_R_CK_MUXED17", + "CLK_HROW_FAN6_2", + "CLK_BUFG_R_BUFGCTRL14_S0", + "CLK_HROW_LH12_1", + "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "CLK_HROW_WR1END1_2", + "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "CLK_BUFG_LOGIC_OUTS_B0_0", + "CLK_BUFG_R_FBG_OUT3", + "CLK_HROW_LH5_1", + "CLK_BUFG_IMUX38_2", + "CLK_BUFG_LOGIC_OUTS_B2_1", + "CLK_HROW_SE4C0_2", + "CLK_HROW_WW4C0_0", + "CLK_BUFG_BUFGCTRL4_O", + "CLK_HROW_NE4BEG0_0", + "CLK_HROW_WW4A3_3", + "CLK_HROW_WR1END0_0", + "CLK_HROW_SW2A0_3", + "CLK_HROW_LH9_3", + "CLK_HROW_WW2END3_1", + "CLK_BUFG_BUFGCTRL4_I0", + "CLK_HROW_WW4A2_0", + "CLK_BUFG_LOGIC_OUTS_B0_2", + "CLK_HROW_WW2A1_2", + "CLK_HROW_EE4B3_1", + "CLK_BUFG_IMUX26_2", + "CLK_BUFG_TOP_R_CK_MUXED5", + "CLK_BUFG_TOP_R_CK_MUXED29", + "CLK_HROW_NE4C0_2", + "CLK_HROW_WL1END1_3", + "CLK_HROW_SW2A3_2", + "CLK_HROW_MONITOR_N_0", + "CLK_BUFG_LOGIC_OUTS_B3_3", + "CLK_HROW_EE2A2_0", + "CLK_HROW_MONITOR_N_1", + "CLK_BUFG_R_BUFGCTRL4_S1", + "CLK_BUFG_IMUX39_0", + "CLK_BUFG_CK_GCLK26", + "CLK_BUFG_IMUX21_1", + "CLK_BUFG_IMUX29_2", + "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "CLK_HROW_SE4BEG2_2", + "CLK_HROW_EE4B3_0", + "CLK_BUFG_IMUX29_3", + "CLK_BUFG_IMUX42_1", + "CLK_HROW_BYP1_1", + "CLK_HROW_SW4END1_1", + "CLK_BUFG_IMUX16_0", + "CLK_HROW_SE4BEG1_1", + "CLK_BUFG_R_BUFGCTRL7_S0", + "CLK_HROW_BYP2_3", + "CLK_BUFG_TOP_R_CK_MUXED9", + "CLK_HROW_EE4C0_2", + "CLK_HROW_LH9_0", + "CLK_HROW_WL1END2_2", + "CLK_BUFG_IMUX0_3", + "CLK_BUFG_IMUX33_1", + "CLK_HROW_WW2A1_0", + "CLK_HROW_FAN5_2", + "CLK_HROW_WW4B2_0", + "CLK_HROW_WW4B3_2", + "CLK_HROW_EE2BEG3_2", + "CLK_HROW_ER1BEG0_3", + "CLK_HROW_NW4A3_2", + "CLK_HROW_WW4A2_1", + "CLK_HROW_LH11_3", + "CLK_HROW_FAN6_1", + "CLK_BUFG_IMUX37_1", + "CLK_BUFG_R_CK_FB_TEST1_2", + "CLK_HROW_EE4BEG0_1", + "CLK_BUFG_R_BUFGCTRL14_CE0", + "CLK_BUFG_BUFGCTRL12_I1", + "CLK_HROW_SE2A2_2", + "CLK_HROW_EE4C3_3", + "CLK_HROW_BLOCK_OUTS_B0_3", + "CLK_HROW_EE2BEG1_0", + "CLK_HROW_SE2A3_2", + "CLK_BUFG_TOP_R_CK_MUXED26", + "CLK_HROW_NE4BEG1_3", + "CLK_HROW_WW4C3_1", + "CLK_HROW_SW4A3_0", + "CLK_BUFG_IMUX13_2", + "CLK_HROW_LH11_1", + "CLK_BUFG_IMUX21_0", + "CLK_HROW_NW2A0_0", + "CLK_BUFG_R_BUFGCTRL7_CE0", + "CLK_HROW_NE4BEG0_2", + "CLK_BUFG_IMUX34_3", + "CLK_HROW_ER1BEG2_0", + "CLK_HROW_EE2A1_2", + "CLK_BUFG_R_FBG_OUT4", + "CLK_HROW_WW4C3_0", + "CLK_HROW_EL1BEG2_2", + "CLK_BUFG_R_BUFGCTRL8_S0", + "CLK_HROW_LH2_3", + "CLK_HROW_EE4BEG0_0", + "CLK_BUFG_LOGIC_OUTS_B15_3", + "CLK_BUFG_IMUX38_0", + "CLK_BUFG_IMUX1_0", + "CLK_BUFG_IMUX10_0", + "CLK_HROW_EE4BEG2_3", + "CLK_HROW_WW2END1_1", + "CLK_BUFG_LOGIC_OUTS_B17_0", + "CLK_BUFG_IMUX47_1", + "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "CLK_HROW_SW2A1_3", + "CLK_BUFG_IMUX28_1", + "CLK_BUFG_IMUX2_2", + "CLK_HROW_SE4BEG0_2", + "CLK_HROW_NE4C1_2", + "CLK_BUFG_R_CK_FB_TEST0_10", + "CLK_BUFG_IMUX45_0", + "CLK_HROW_SW4A2_3", + "CLK_HROW_NE2A3_0", + "CLK_HROW_WW4A1_3", + "CLK_BUFG_BUFGCTRL8_I0", + "CLK_HROW_SE2A1_0", + "CLK_HROW_SW4A3_3", + "CLK_BUFG_R_BUFGCTRL12_S0", + "CLK_HROW_SE4C2_3", + "CLK_HROW_WW4C1_3", + "CLK_HROW_WR1END3_1", + "CLK_BUFG_R_BUFGCTRL3_CE0", + "CLK_BUFG_IMUX41_0", + "CLK_HROW_NW2A1_0", + "CLK_HROW_NE4BEG1_0", + "CLK_HROW_EE4C1_1", + "CLK_BUFG_BUFGCTRL13_O", + "CLK_BUFG_IMUX36_0", + "CLK_HROW_WL1END0_1", + "CLK_BUFG_IMUX37_2", + "CLK_HROW_LH3_2", + "CLK_BUFG_IMUX44_1", + "CLK_BUFG_TOP_R_CK_MUXED30", + "CLK_HROW_WL1END0_3", + "CLK_BUFG_IMUX42_2", + "CLK_BUFG_LOGIC_OUTS_B14_3", + "CLK_HROW_EE4B0_1", + "CLK_BUFG_R_BUFGCTRL14_CE1", + "CLK_BUFG_LOGIC_OUTS_B20_1", + "CLK_BUFG_IMUX17_3", + "CLK_BUFG_IMUX4_1", + "CLK_HROW_SW4A0_1", + "CLK_HROW_EE2BEG0_3", + "CLK_BUFG_R_BUFGCTRL2_CE0", + "CLK_HROW_EL1BEG1_0", + "CLK_HROW_BLOCK_OUTS_B2_3", + "CLK_HROW_EL1BEG3_1", + "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "CLK_HROW_SE4C0_0", + "CLK_HROW_EE4A3_2", + "CLK_BUFG_IMUX14_3", + "CLK_BUFG_IMUX33_2", + "CLK_BUFG_IMUX1_3", + "CLK_HROW_ER1BEG0_2", + "CLK_BUFG_CK_GCLK19", + "CLK_BUFG_IMUX14_0", + "CLK_BUFG_R_CK_FB_TEST1_15", + "CLK_BUFG_LOGIC_OUTS_B10_2", + "CLK_HROW_BYP0_1", + "CLK_HROW_NE4BEG3_1", + "CLK_HROW_EE4C2_2", + "CLK_BUFG_R_CK_FB_TEST1_11", + "CLK_BUFG_R_BUFGCTRL1_S0", + "CLK_BUFG_IMUX27_2", + "CLK_BUFG_LOGIC_OUTS_B11_3", + "CLK_HROW_EE2BEG2_2", + "CLK_HROW_WW4A0_3", + "CLK_HROW_WL1END0_2", + "CLK_HROW_SW4END0_3", + "CLK_BUFG_IMUX2_1", + "CLK_BUFG_IMUX32_3", + "CLK_HROW_BLOCK_OUTS_B2_0", + "CLK_BUFG_R_CK_FB_TEST0_6", + "CLK_BUFG_IMUX19_3", + "CLK_BUFG_IMUX19_2", + "CLK_HROW_SW2A0_2", + "CLK_HROW_FAN0_2", + "CLK_HROW_EL1BEG3_0", + "CLK_HROW_WR1END1_0", + "CLK_BUFG_BUFGCTRL14_I1", + "CLK_HROW_WL1END3_1", + "CLK_HROW_WW2END0_3", + "CLK_HROW_BYP6_2", + "CLK_HROW_WW4A3_2", + "CLK_BUFG_R_BUFGCTRL7_S1", + "CLK_BUFG_BUFGCTRL3_I0", + "CLK_BUFG_IMUX33_3", + "CLK_HROW_SE4C3_0", + "CLK_HROW_EE4B1_3", + "CLK_HROW_FAN3_0", + "CLK_HROW_NE2A1_3", + "CLK_HROW_SE4C3_2", + "CLK_HROW_SW4END0_1", + "CLK_HROW_LH8_0", + "CLK_HROW_NE4BEG3_0", + "CLK_HROW_FAN1_2", + "CLK_HROW_WW2A2_0", + "CLK_HROW_NE4C3_3", + "CLK_HROW_NW4A0_0", + "CLK_BUFG_R_BUFGCTRL10_CE1", + "CLK_BUFG_R_CK_FB_TEST1_1", + "CLK_HROW_NE4C3_1", + "CLK_HROW_NE2A3_2", + "CLK_HROW_ER1BEG1_3", + "CLK_HROW_BYP3_3", + "CLK_BUFG_IMUX6_0", + "CLK_HROW_WW2A2_1", + "CLK_BUFG_R_CK_FB_TEST0_7", + "CLK_BUFG_BUFGCTRL7_I1", + "CLK_BUFG_IMUX27_1", + "CLK_HROW_MONITOR_N_2", + "CLK_HROW_EE4BEG1_3", + "CLK_BUFG_IMUX14_2", + "CLK_HROW_FAN5_3", + "CLK_BUFG_IMUX47_3", + "CLK_HROW_SW4END2_0", + "CLK_BUFG_R_BUFGCTRL14_S1", + "CLK_HROW_LH4_1", + "CLK_HROW_EL1BEG2_0", + "CLK_HROW_SE2A0_3", + "CLK_BUFG_LOGIC_OUTS_B6_1", + "CLK_HROW_EE4BEG3_0", + "CLK_HROW_ER1BEG3_1", + "CLK_BUFG_IMUX7_0", + "CLK_BUFG_R_BUFGCTRL11_CE0", + "CLK_HROW_NW4END2_0", + "CLK_BUFG_R_CK_FB_TEST0_13", + "CLK_HROW_SW4A0_2", + "CLK_HROW_SW4END3_2", + "CLK_BUFG_IMUX45_1", + "CLK_HROW_NE4BEG2_0", + "CLK_BUFG_R_FBG_OUT15", + "CLK_BUFG_R_BUFGCTRL2_CE1", + "CLK_BUFG_IMUX35_1", + "CLK_BUFG_TOP_R_CK_MUXED4", + "CLK_HROW_SE4BEG2_1", + "CLK_HROW_CTRL0_2", + "CLK_HROW_NE4BEG1_1", + "CLK_BUFG_IMUX36_3", + "CLK_HROW_FAN3_3", + "CLK_HROW_FAN1_1", + "CLK_BUFG_BUFGCTRL6_I0", + "CLK_BUFG_IMUX17_1", + "CLK_HROW_EE4C1_2", + "CLK_BUFG_CK_GCLK20", + "CLK_HROW_NE4BEG3_2", + "CLK_HROW_EE2A1_1", + "CLK_HROW_EE2A2_3", + "CLK_HROW_NW4END2_2", + "CLK_HROW_WW4END2_3", + "CLK_BUFG_IMUX15_2", + "CLK_BUFG_IMUX2_0", + "CLK_HROW_FAN5_0", + "CLK_HROW_ER1BEG0_0", + "CLK_BUFG_IMUX36_1", + "CLK_HROW_WW4END2_0", + "CLK_BUFG_CK_GCLK12", + "CLK_HROW_EE4B1_0", + "CLK_HROW_NW4END2_1", + "CLK_BUFG_LOGIC_OUTS_B17_2", + "CLK_HROW_EE2A2_2", + "CLK_BUFG_R_CK_FB_TEST1_8", + "CLK_HROW_WW4A2_2", + "CLK_HROW_EE4BEG2_0", + "CLK_HROW_FAN4_0", + "CLK_BUFG_IMUX39_1", + "CLK_HROW_BYP7_3", + "CLK_HROW_WW4B1_2", + "CLK_BUFG_LOGIC_OUTS_B5_3", + "CLK_HROW_NE2A0_2", + "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "CLK_BUFG_R_BUFGCTRL5_CE0", + "CLK_HROW_LH4_3" + ], + "tile_type": "CLK_BUFG_TOP_R", + "sites": [ + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL0_I1", + "S1": "CLK_BUFG_R_BUFGCTRL0_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", + "I0": "CLK_BUFG_BUFGCTRL0_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL0_S0", + "O": "CLK_BUFG_BUFGCTRL0_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL1_I1", + "S1": "CLK_BUFG_R_BUFGCTRL1_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", + "I0": "CLK_BUFG_BUFGCTRL1_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL1_S0", + "O": "CLK_BUFG_BUFGCTRL1_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL2_I1", + "S1": "CLK_BUFG_R_BUFGCTRL2_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", + "I0": "CLK_BUFG_BUFGCTRL2_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL2_S0", + "O": "CLK_BUFG_BUFGCTRL2_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y2", + "x_coord": 0, + "y_coord": 2 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL3_I1", + "S1": "CLK_BUFG_R_BUFGCTRL3_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", + "I0": "CLK_BUFG_BUFGCTRL3_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL3_S0", + "O": "CLK_BUFG_BUFGCTRL3_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y3", + "x_coord": 0, + "y_coord": 3 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL4_I1", + "S1": "CLK_BUFG_R_BUFGCTRL4_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", + "I0": "CLK_BUFG_BUFGCTRL4_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL4_S0", + "O": "CLK_BUFG_BUFGCTRL4_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y4", + "x_coord": 0, + "y_coord": 4 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL5_I1", + "S1": "CLK_BUFG_R_BUFGCTRL5_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", + "I0": "CLK_BUFG_BUFGCTRL5_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL5_S0", + "O": "CLK_BUFG_BUFGCTRL5_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y5", + "x_coord": 0, + "y_coord": 5 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL6_I1", + "S1": "CLK_BUFG_R_BUFGCTRL6_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", + "I0": "CLK_BUFG_BUFGCTRL6_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL6_S0", + "O": "CLK_BUFG_BUFGCTRL6_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y6", + "x_coord": 0, + "y_coord": 6 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL7_I1", + "S1": "CLK_BUFG_R_BUFGCTRL7_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", + "I0": "CLK_BUFG_BUFGCTRL7_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL7_S0", + "O": "CLK_BUFG_BUFGCTRL7_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y7", + "x_coord": 0, + "y_coord": 7 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL8_I1", + "S1": "CLK_BUFG_R_BUFGCTRL8_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", + "I0": "CLK_BUFG_BUFGCTRL8_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL8_S0", + "O": "CLK_BUFG_BUFGCTRL8_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y8", + "x_coord": 0, + "y_coord": 8 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL9_I1", + "S1": "CLK_BUFG_R_BUFGCTRL9_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", + "I0": "CLK_BUFG_BUFGCTRL9_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL9_S0", + "O": "CLK_BUFG_BUFGCTRL9_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y9", + "x_coord": 0, + "y_coord": 9 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL10_I1", + "S1": "CLK_BUFG_R_BUFGCTRL10_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", + "I0": "CLK_BUFG_BUFGCTRL10_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL10_S0", + "O": "CLK_BUFG_BUFGCTRL10_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y10", + "x_coord": 0, + "y_coord": 10 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL11_I1", + "S1": "CLK_BUFG_R_BUFGCTRL11_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", + "I0": "CLK_BUFG_BUFGCTRL11_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL11_S0", + "O": "CLK_BUFG_BUFGCTRL11_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y11", + "x_coord": 0, + "y_coord": 11 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL12_I1", + "S1": "CLK_BUFG_R_BUFGCTRL12_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", + "I0": "CLK_BUFG_BUFGCTRL12_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL12_S0", + "O": "CLK_BUFG_BUFGCTRL12_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y12", + "x_coord": 0, + "y_coord": 12 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL13_I1", + "S1": "CLK_BUFG_R_BUFGCTRL13_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", + "I0": "CLK_BUFG_BUFGCTRL13_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL13_S0", + "O": "CLK_BUFG_BUFGCTRL13_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y13", + "x_coord": 0, + "y_coord": 13 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL14_I1", + "S1": "CLK_BUFG_R_BUFGCTRL14_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", + "I0": "CLK_BUFG_BUFGCTRL14_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL14_S0", + "O": "CLK_BUFG_BUFGCTRL14_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y14", + "x_coord": 0, + "y_coord": 14 + }, + { + "site_pins": { + "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", + "I1": "CLK_BUFG_BUFGCTRL15_I1", + "S1": "CLK_BUFG_R_BUFGCTRL15_S1", + "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", + "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", + "I0": "CLK_BUFG_BUFGCTRL15_I0", + "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", + "S0": "CLK_BUFG_R_BUFGCTRL15_S0", + "O": "CLK_BUFG_BUFGCTRL15_O" + }, + "type": "BUFGCTRL", + "prefix": "BUFGCTRL", + "name": "X0Y15", + "x_coord": 0, + "y_coord": 15 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_FEED.json b/artix7/tile_type_CLK_FEED.json index 2c7c3b5..84707b7 100644 --- a/artix7/tile_type_CLK_FEED.json +++ b/artix7/tile_type_CLK_FEED.json @@ -1,261 +1,261 @@ { + "pips": {}, "wires": [ - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_WR1END0", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_EE4BEG0", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2END3", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_EE4A2", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_WW4C1", - "CLK_FEED_NW4A0", - "CLK_FEED_LH6", - "CLK_FEED_EL1BEG0", - "CLK_FEED_WW4B1", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_WR1END1", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_EE4A1", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_EL1BEG1", - "CLK_FEED_WW4END1", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_EL1BEG2", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_WW4A1", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_EE2A0", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_LH8", - "CLK_FEED_SW4A0", - "CLK_FEED_NE4C3", - "CLK_FEED_SE2A1", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_NE4BEG0", - "CLK_FEED_SE4C0", - "CLK_FEED_EE2A2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_WW4END2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_NE4BEG2", - "CLK_FEED_WR1END3", - "CLK_FEED_EL1BEG3", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_SW2A2", - "CLK_FEED_LH9", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_WW4A2", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_NW4END2", - "CLK_FEED_SE2A0", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_WW2A0", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_LH3", - "CLK_FEED_MONITOR_N", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_NW4END0", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_EE4B0", - "CLK_FEED_LH11", - "CLK_FEED_NW2A0", - "CLK_FEED_SW4A2", - "CLK_FEED_NW4A2", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_WW4END0", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_WW2END2", - "CLK_FEED_NE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_EE4A3", - "CLK_FEED_LH12", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_EE2BEG3", - "CLK_FEED_SE4BEG2", - "CLK_FEED_LH7", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_EE4C0", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE4BEG1", - "CLK_FEED_LH2", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_WW4A0", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_SW4END1", - "CLK_FEED_WW2A3", - "CLK_FEED_SE2A2", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_SE4C1", - "CLK_FEED_SW2A0", - "CLK_FEED_EE2A3", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_WW4END3", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_SW4END0", - "CLK_FEED_EE4C2", - "CLK_FEED_LH10", - "CLK_FEED_NE4C1", - "CLK_FEED_ER1BEG0", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_SE4BEG1", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_LH1", - "CLK_FEED_WL1END0", - "CLK_FEED_SW4A3", "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_LH4", - "CLK_FEED_NE4C0", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_NE2A2", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_NE4BEG1", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4C3", - "CLK_FEED_EE4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_ER1BEG2", - "CLK_FEED_WL1END3", - "CLK_FEED_SE2A3", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_EE4BEG2", - "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_CK_BUFG_CASC3", "CLK_FEED_WW4B2", - "CLK_FEED_SE4C2", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_ER1BEG1", - "CLK_FEED_SE4C3", + "CLK_FEED_EE4B2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_WW2A0", + "CLK_FEED_EE4A2", + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_FEED_EE4BEG1", + "CLK_FEED_CK_GCLK29", + "CLK_FEED_WW4C0", + "CLK_FEED_EE4BEG2", "CLK_FEED_CK_GCLK19", - "CLK_FEED_R_CK_GCLK9", "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_NW2A1", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_NW2A2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_FEED_SW4END1", + "CLK_FEED_LH12", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_FEED_WW4END3", + "CLK_FEED_SE4C1", "CLK_FEED_CK_GCLK9", + "CLK_FEED_EE4C3", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_WW2END0", + "CLK_FEED_CK_GCLK2", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_CK_GCLK15", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_FEED_NE4BEG0", + "CLK_FEED_SE4BEG3", + "CLK_FEED_WW4A2", + "CLK_FEED_SE4BEG1", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_WW2A2", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_EE4BEG0", + "CLK_FEED_CK_GCLK11", + "CLK_FEED_CK_GCLK27", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_FEED_LH10", + "CLK_FEED_SE4C0", + "CLK_FEED_LH3", + "CLK_FEED_WW2A3", + "CLK_FEED_NW4A1", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_LH5", + "CLK_FEED_NW4A2", + "CLK_FEED_WW4END1", + "CLK_FEED_EE2BEG2", + "CLK_FEED_WL1END0", + "CLK_FEED_NE4BEG3", + "CLK_FEED_WL1END1", "CLK_FEED_SW2A1", "CLK_FEED_EE2BEG0", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A3", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_LH5", - "CLK_FEED_EE4C3", - "CLK_FEED_WR1END2", - "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_CK_GCLK7", "CLK_FEED_CK_GCLK22", - "CLK_FEED_SW4A1", - "CLK_FEED_NE4C2", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_WL1END2", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_WW4C0", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_SW2A3", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_WW4A3", - "CLK_FEED_WW2END1", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_NW2A3", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_WW2A1", - "CLK_FEED_WW4B3", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4A1", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_EE4B1", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_NE2A1", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_EE4A0", - "CLK_FEED_WL1END1", + "CLK_FEED_EE4A1", + "CLK_FEED_EE4BEG3", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_CK_BUFG_CASC8", "CLK_FEED_EE2BEG1", - "CLK_FEED_WW2END0", + "CLK_FEED_SW4END0", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_SE4BEG2", + "CLK_FEED_NE2A3", + "CLK_FEED_LH8", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_WW4END2", + "CLK_FEED_SW4A3", + "CLK_FEED_LH11", + "CLK_FEED_EE4C1", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_NE4C0", + "CLK_FEED_CK_GCLK24", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_SE4C2", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_ER1BEG1", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_MONITOR_P", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_WW4C3", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_WW2END2", + "CLK_FEED_SE2A1", + "CLK_FEED_WW4A3", + "CLK_FEED_CK_GCLK8", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_EL1BEG1", + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_EE2BEG3", + "CLK_FEED_LH7", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_FEED_SW4A0", + "CLK_FEED_LH9", + "CLK_FEED_SW4A2", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK28", + "CLK_FEED_MONITOR_N", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_EE4B3", + "CLK_FEED_NE2A1", + "CLK_FEED_CK_GCLK25", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_SW4END2", + "CLK_FEED_EE2A1", + "CLK_FEED_SE2A3", + "CLK_FEED_SW2A0", + "CLK_FEED_NE2A2", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_FEED_WW4C2", + "CLK_FEED_NE4BEG1", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_NW2A1", + "CLK_FEED_EE4B0", + "CLK_FEED_NE4C2", + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_WW4B0", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_GCLK20", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_FEED_WW2END1", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_WR1END0", + "CLK_FEED_EE4A3", + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_NW2A2", + "CLK_FEED_LH4", + "CLK_FEED_EE2A0", + "CLK_FEED_ER1BEG2", + "CLK_FEED_ER1BEG3", + "CLK_FEED_WW4A0", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_WR1END3", + "CLK_FEED_LH1", + "CLK_FEED_EE2A3", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2END3", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_SE4C3", + "CLK_FEED_NW4END2", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_EE4C0", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_WL1END3", + "CLK_FEED_NW2A0", + "CLK_FEED_NW4A0", + "CLK_FEED_ER1BEG0", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_WW4A1", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_FEED_LH2", + "CLK_FEED_SW2A2", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_FEED_CK_GCLK18", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_LH6", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_GCLK2", + "CLK_FEED_NW4END3", + "CLK_FEED_NE4C1", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WW2A1", + "CLK_FEED_R_CK_GCLK16", + "CLK_FEED_SE4BEG0", + "CLK_FEED_NW4END1", + "CLK_FEED_WL1END2", + "CLK_FEED_NW4END0", + "CLK_FEED_SE2A0", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_WR1END2", + "CLK_FEED_SW4END3", + "CLK_FEED_WW4END0", + "CLK_FEED_EE4B1", + "CLK_FEED_SW4A1", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_NE4C3", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_CK_GCLK23", "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_EE2A2", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_FEED_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_SE4BEG0" + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_FEED_NE2A0", + "CLK_FEED_SE2A2", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_SW2A3", + "CLK_FEED_EE4A0", + "CLK_FEED_CK_GCLK30", + "CLK_FEED_EL1BEG3", + "CLK_FEED_WW4C1", + "CLK_FEED_R_CK_GCLK26", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_FEED_EL1BEG0", + "CLK_FEED_R_CK_GCLK31", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_EE4C2", + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_FEED_WW4B3", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_FEED_EL1BEG2", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_WW4B1" ], - "sites": [], - "pips": {}, - "tile_type": "CLK_FEED" + "tile_type": "CLK_FEED", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_HROW_BOT_R.json b/artix7/tile_type_CLK_HROW_BOT_R.json index 6cb286c..495c3da 100644 --- a/artix7/tile_type_CLK_HROW_BOT_R.json +++ b/artix7/tile_type_CLK_HROW_BOT_R.json @@ -1,22381 +1,22381 @@ { - "wires": [ - "CLK_HROW_NW4END0_6", - "CLK_HROW_IMUX37_7", - "CLK_HROW_IMUX14_1", - "CLK_HROW_WR1END3_6", - "CLK_HROW_SW4END0_2", - "CLK_HROW_EE4B1_2", - "CLK_HROW_NW4END3_4", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN6", - "CLK_HROW_WW2END2_0", - "CLK_HROW_CK_GCLK_IN_TEST14", - "CLK_HROW_LOGIC_OUTS_B4_1", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN3", - "CLK_HROW_MONITOR_P_4", - "CLK_HROW_LOGIC_OUTS_B4_4", - "CLK_HROW_LH10_6", - "CLK_HROW_CK_GCLK_OUT_TEST25", - "CLK_HROW_BYP6_2", - "CLK_HROW_R_CK_GCLK18", - "CLK_HROW_NE2A2_2", - "CLK_HROW_EE2A1_0", - "CLK_HROW_IMUX22_1", - "CLK_HROW_LOGIC_OUTS_B1_7", - "CLK_HROW_IMUX24_7", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN13", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN25", - "CLK_HROW_NE4BEG2_4", - "CLK_HROW_SW4A3_6", - "CLK_HROW_WW4A2_0", - "CLK_HROW_EE4B3_7", - "CLK_HROW_CK_GCLK_OUT_TEST31", - "CLK_HROW_BUFHCE_CE_L10", - "CLK_HROW_LOGIC_OUTS_B16_6", - "CLK_HROW_CK_BUFHCLK_R10", - "CLK_HROW_NW4A2_1", - "CLK_HROW_BLOCK_OUTS_B3_4", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_WW4END0_0", - "CLK_HROW_IMUX25_4", - "CLK_HROW_IMUX27_3", - "CLK_HROW_LH11_4", - "CLK_HROW_IMUX14_0", - "CLK_HROW_LOGIC_OUTS_B20_3", - "CLK_HROW_EE2A3_1", - "CLK_HROW_BUFHCE_CE_R0", - "CLK_HROW_SW2A2_7", - "CLK_HROW_LH12_5", - "CLK_HROW_IMUX25_2", - "CLK_HROW_CK_GCLK_TEST_OUT4", - "CLK_HROW_WW4END2_3", - "CLK_HROW_LOGIC_OUTS_B12_3", - "CLK_HROW_BYP7_3", - "CLK_HROW_IMUX13_2", - "CLK_HROW_EE2BEG1_7", - "CLK_HROW_WR1END3_3", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE2A2_3", - "CLK_HROW_SE4C0_5", - "CLK_HROW_IMUX20_3", - "CLK_HROW_CE_INT_BOT6", - "CLK_HROW_IMUX19_4", - "CLK_HROW_ER1BEG0_7", - "CLK_HROW_IMUX40_1", - "CLK_HROW_LOGIC_OUTS_B12_5", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_WW4C0_7", - "CLK_HROW_CK_GCLK_IN_TEST11", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_EE2BEG2_5", - "CLK_HROW_CK_IN_R_OUT_TEST", - "CLK_HROW_CLK1_3", - "CLK_HROW_IMUX22_4", - "CLK_HROW_CK_GCLK_TEST_IN29", - "CLK_HROW_IMUX9_0", - "CLK_HROW_WW2A1_3", - "CLK_HROW_IMUX43_6", - "CLK_HROW_BYP3_4", - "CLK_HROW_EE4C1_7", - "CLK_HROW_WL1END0_0", - "CLK_HROW_IMUX38_7", - "CLK_HROW_NW4END1_1", - "CLK_HROW_IMUX19_1", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_WW4B3_1", - "CLK_HROW_CK_BUFHCLK_R6", - "CLK_HROW_EE4BEG3_5", - "CLK_HROW_LOGIC_OUTS_B7_6", - "CLK_HROW_CK_GCLK_OUT_TEST18", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_FAN1_5", - "CLK_HROW_LH11_0", - "CLK_HROW_WL1END0_6", - "CLK_HROW_IMUX8_0", - "CLK_HROW_IMUX15_3", - "CLK_HROW_BUFHCE_CE_R11", - "CLK_HROW_NE4BEG3_5", - "CLK_HROW_CK_BUFHCLK_L6", - "CLK_HROW_LOGIC_OUTS_B11_5", - "CLK_HROW_CK_GCLK_IN_TEST0", - "CLK_HROW_NW4A2_2", - "CLK_HROW_BLOCK_OUTS_B2_4", - "CLK_HROW_BUFHCE_CE_L6", - "CLK_HROW_MONITOR_N_4", - "CLK_HROW_WW4B1_0", - "CLK_HROW_IMUX34_2", - "CLK_HROW_WW4END1_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_IMUX6_5", - "CLK_HROW_BUFHCE_CE_L4", - "CLK_HROW_WW4END1_3", - "CLK_HROW_IMUX9_3", - "CLK_HROW_IMUX6_1", - "CLK_HROW_FAN1_1", - "CLK_HROW_BYP5_0", - "CLK_HROW_EE2A3_7", - "CLK_HROW_SE2A3_5", - "CLK_HROW_NW4END0_0", - "CLK_HROW_IMUX44_6", - "CLK_HROW_IMUX41_1", - "CLK_HROW_LH1_3", - "CLK_HROW_IMUX41_6", - "CLK_HROW_NE4C0_1", - "CLK_HROW_LH5_1", - "CLK_HROW_CE_INT_TOP5", - "CLK_HROW_SE4BEG2_5", - "CLK_HROW_CK_GCLK_TEST_OUT17", - "CLK_HROW_BUFHCE_CE_L0", - "CLK_HROW_LOGIC_OUTS_B15_1", - "CLK_HROW_SW2A3_4", - "CLK_HROW_CK_BUFHCLK_L2", - "CLK_HROW_SE2A2_7", - "CLK_HROW_WW2A0_7", - "CLK_HROW_IMUX14_5", - "CLK_HROW_LOGIC_OUTS_B13_4", - "CLK_HROW_SW2A1_4", - "CLK_HROW_IMUX28_6", - "CLK_HROW_LOGIC_OUTS_B12_4", - "CLK_HROW_WW4C2_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_IMUX25_7", - "CLK_HROW_LOGIC_OUTS_B18_6", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW4A1_7", - "CLK_HROW_SW2A0_4", - "CLK_HROW_IMUX26_4", - "CLK_HROW_WW4B1_3", - "CLK_HROW_SE2A0_3", - "CLK_HROW_NW4END3_1", - "CLK_HROW_LH5_0", - "CLK_HROW_FAN5_5", - "CLK_HROW_SE4BEG0_5", - "CLK_HROW_EL1BEG0_6", - "CLK_HROW_CK_GCLK_OUT_TEST20", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_SE4BEG1_6", - "CLK_HROW_IMUX26_1", - "CLK_HROW_IMUX14_2", - "CLK_HROW_SE4BEG2_7", - "CLK_HROW_CK_MUX_OUT_R2", - "CLK_HROW_WW4A1_1", - "CLK_HROW_IMUX2_1", - "CLK_HROW_NE2A0_3", - "CLK_HROW_LOGIC_OUTS_B23_7", - "CLK_HROW_CK_MUX_OUT_L7", - "CLK_HROW_IMUX2_7", - "CLK_HROW_NE4C3_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_IMUX29_7", - "CLK_HROW_WW4B3_6", - "CLK_HROW_CK_HCLK_OUT_L6", - "CLK_HROW_SE4BEG0_7", - "CLK_HROW_LH3_0", - "CLK_HROW_WW4END3_2", - "CLK_HROW_CK_MUX_OUT_L0", - "CLK_HROW_CK_GCLK_OUT_TEST22", - "CLK_HROW_NE4C3_0", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN11", - "CLK_HROW_LOGIC_OUTS_B1_1", - "CLK_HROW_CK_GCLK_OUT_TEST4", - "CLK_HROW_BUFHCE_CE_L11", - "CLK_HROW_IMUX11_0", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_LOGIC_OUTS_B8_7", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_IMUX3_3", - "CLK_HROW_NE4C3_5", - "CLK_HROW_EE4BEG2_4", - "CLK_HROW_IMUX5_3", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_NE4BEG1_7", - "CLK_HROW_IMUX8_1", - "CLK_HROW_LOGIC_OUTS_B16_7", - "CLK_HROW_NE2A1_2", - "CLK_HROW_LOGIC_OUTS_B7_2", - "CLK_HROW_CK_GCLK_IN_TEST31", - "CLK_HROW_LOGIC_OUTS_B20_1", - "CLK_HROW_EE4C3_5", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN26", - "CLK_HROW_BYP7_4", - "CLK_HROW_CK_GCLK_IN_TEST1", - "CLK_HROW_WW4END3_4", - "CLK_HROW_CTRL1_1", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_NE4C2_3", - "CLK_HROW_FAN5_2", - "CLK_HROW_WW4END1_7", - "CLK_HROW_CK_GCLK_TEST_OUT29", - "CLK_HROW_CE_INT_BOT1", - "CLK_HROW_CK_INT_1_1", - "CLK_HROW_EE2A3_6", - "CLK_HROW_WW4B3_0", - "CLK_HROW_NE4C0_2", - "CLK_HROW_IMUX18_5", - "CLK_HROW_IMUX44_0", - "CLK_HROW_CK_GCLK_TEST_OUT25", - "CLK_HROW_CK_GCLK_OUT_TEST16", - "CLK_HROW_FAN6_3", - "CLK_HROW_BYP5_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_IMUX36_4", - "CLK_HROW_LOGIC_OUTS_B16_5", - "CLK_HROW_NW4END1_4", - "CLK_HROW_CLK1_1", - "CLK_HROW_EE4BEG3_6", - "CLK_HROW_FAN0_5", - "CLK_HROW_LOGIC_OUTS_B10_3", - "CLK_HROW_CTRL0_6", - "CLK_HROW_EE2BEG1_4", - "CLK_HROW_EE4A0_3", - "CLK_HROW_LOGIC_OUTS_B4_6", - "CLK_HROW_LOGIC_OUTS_B2_4", - "CLK_HROW_R_CK_GCLK28", - "CLK_HROW_LOGIC_OUTS_B10_4", - "CLK_HROW_LOGIC_OUTS_B3_7", - "CLK_HROW_CK_IN_L3", - "CLK_HROW_CK_BUFRCLK_L1", - "CLK_HROW_EE4A2_7", - "CLK_HROW_BYP6_1", - "CLK_HROW_LOGIC_OUTS_B6_5", - "CLK_HROW_FAN3_1", - "CLK_HROW_WW4A2_3", - "CLK_HROW_ER1BEG2_5", - "CLK_HROW_IMUX34_0", - "CLK_HROW_LH2_7", - "CLK_HROW_WW2A1_7", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW4A1_6", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE2A3_5", - "CLK_HROW_LOGIC_OUTS_B3_2", - "CLK_HROW_IMUX40_7", - "CLK_HROW_FAN5_6", - "CLK_HROW_IMUX36_2", - "CLK_HROW_IMUX47_7", - "CLK_HROW_WR1END1_1", - "CLK_HROW_IMUX46_1", - "CLK_HROW_IMUX21_1", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN15", - "CLK_HROW_LH1_5", - "CLK_HROW_LOGIC_OUTS_B3_5", - "CLK_HROW_FAN4_6", - "CLK_HROW_LH6_3", - "CLK_HROW_WW4A1_3", - "CLK_HROW_IMUX47_1", - "CLK_HROW_IMUX35_0", - "CLK_HROW_SE2A3_7", - "CLK_HROW_IMUX2_4", - "CLK_HROW_IMUX17_1", - "CLK_HROW_CE_INT_BOT5", - "CLK_HROW_WW4B1_4", - "CLK_HROW_LOGIC_OUTS_B21_4", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_IMUX39_1", - "CLK_HROW_IMUX16_6", - "CLK_HROW_LOGIC_OUTS_B23_6", - "CLK_HROW_IMUX18_3", - "CLK_HROW_NW4A1_1", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_LH8_5", - "CLK_HROW_NW4A0_4", - "CLK_HROW_EL1BEG2_4", - "CLK_HROW_EL1BEG2_5", - "CLK_HROW_LOGIC_OUTS_B20_0", - "CLK_HROW_BLOCK_OUTS_B3_7", - "CLK_HROW_CK_GCLK_TEST_IN5", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE4B0_5", - "CLK_HROW_NW2A3_6", - "CLK_HROW_LOGIC_OUTS_B18_7", - "CLK_HROW_WW2A3_7", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN30", - "CLK_HROW_BYP6_6", - "CLK_HROW_EE4C3_1", - "CLK_HROW_CK_BUFRCLK_L2", - "CLK_HROW_NE2A2_0", - "CLK_HROW_CK_HCLK_OUT_R1", - "CLK_HROW_IMUX18_2", - "CLK_HROW_EL1BEG0_7", - "CLK_HROW_EE4A1_6", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_BYP1_5", - "CLK_HROW_EL1BEG0_4", - "CLK_HROW_BYP1_6", - "CLK_HROW_LOGIC_OUTS_B6_3", - "CLK_HROW_SE2A0_2", - "CLK_HROW_FAN4_7", - "CLK_HROW_IMUX37_1", - "CLK_HROW_LOGIC_OUTS_B9_3", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SW4A1_0", - "CLK_HROW_WW4B0_7", - "CLK_HROW_CE_INT_BOT2", - "CLK_HROW_BYP0_4", - "CLK_HROW_CK_GCLK_TEST_OUT28", - "CLK_HROW_FAN5_4", - "CLK_HROW_BUFHCE_CE_R9", - "CLK_HROW_IMUX5_0", - "CLK_HROW_WL1END3_7", - "CLK_HROW_EE4A3_4", - "CLK_HROW_WR1END1_7", - "CLK_HROW_R_CK_GCLK15", - "CLK_HROW_LOGIC_OUTS_B13_5", - "CLK_HROW_LOGIC_OUTS_B1_2", - "CLK_HROW_SW4END0_7", - "CLK_HROW_CTRL0_3", - "CLK_HROW_LH4_5", - "CLK_HROW_WL1END2_1", - "CLK_HROW_EE2A2_7", - "CLK_HROW_EE4B3_4", - "CLK_HROW_NE4BEG0_7", - "CLK_HROW_LOGIC_OUTS_B0_5", - "CLK_HROW_SW4A3_0", - "CLK_HROW_BYP7_2", - "CLK_HROW_CK_GCLK_IN_TEST20", - "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "CLK_HROW_WW4B2_7", - "CLK_HROW_WW4C1_6", - "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "CLK_HROW_IMUX42_2", - "CLK_HROW_BYP4_6", - "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "CLK_HROW_LOGIC_OUTS_B5_1", - "CLK_HROW_LOGIC_OUTS_B8_1", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CK_GCLK_TEST_OUT6", - "CLK_HROW_CK_GCLK_TEST_IN8", - "CLK_HROW_WL1END3_6", - "CLK_HROW_LH4_4", - "CLK_HROW_NW4END3_3", - "CLK_HROW_SW4A1_2", - "CLK_HROW_CK_GCLK_TEST11", - "CLK_HROW_EE4C2_4", - "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "CLK_HROW_LH1_0", - "CLK_HROW_IMUX37_4", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN31", - "CLK_HROW_IMUX43_7", - "CLK_HROW_CK_GCLK_TEST1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_CK_GCLK_IN_TEST2", - "CLK_HROW_SE4C3_4", - "CLK_HROW_R_CK_GCLK19", - "CLK_HROW_CK_GCLK_TEST_IN2", - "CLK_HROW_WW2A3_5", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN14", - "CLK_HROW_WR1END0_7", - "CLK_HROW_LH10_3", - "CLK_HROW_IMUX24_5", - "CLK_HROW_CK_GCLK_OUT_TEST30", - "CLK_HROW_CK_GCLK_IN_TEST21", - "CLK_HROW_WW2END0_6", - "CLK_HROW_FAN4_0", - "CLK_HROW_IMUX40_2", - "CLK_HROW_IMUX28_7", - "CLK_HROW_SE2A2_6", - "CLK_HROW_CK_BUFRCLK_R0", - "CLK_HROW_WW2END3_2", - "CLK_HROW_LH4_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_R_CK_GCLK0", - "CLK_HROW_SW2A0_3", - "CLK_HROW_LH6_0", - "CLK_HROW_IMUX31_5", - "CLK_HROW_LOGIC_OUTS_B17_1", - "CLK_HROW_WW4END1_6", - "CLK_HROW_SW2A3_5", - "CLK_HROW_NW2A3_0", - "CLK_HROW_FAN3_0", - "CLK_HROW_WW4C1_3", - "CLK_HROW_NE2A2_1", - "CLK_HROW_CK_GCLK_TEST6", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_WW2END2_7", - "CLK_HROW_NW2A3_3", - "CLK_HROW_IMUX11_6", - "CLK_HROW_WL1END2_4", - "CLK_HROW_IMUX19_7", - "CLK_HROW_IMUX15_7", - "CLK_HROW_WW2A1_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_CLK1_7", - "CLK_HROW_CLK0_4", - "CLK_HROW_IMUX11_3", - "CLK_HROW_LOGIC_OUTS_B13_6", - "CLK_HROW_CK_IN_R6", - "CLK_HROW_SE4BEG0_6", - "CLK_HROW_EE4B0_3", - "CLK_HROW_CK_BUFHCLK_R1", - "CLK_HROW_CLK0_3", - "CLK_HROW_LH3_5", - "CLK_HROW_BUFHCE_CE_L3", - "CLK_HROW_SW2A3_0", - "CLK_HROW_IMUX27_1", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_CK_GCLK_OUT_TEST21", - "CLK_HROW_LH9_5", - "CLK_HROW_LOGIC_OUTS_B3_0", - "CLK_HROW_CK_MUX_OUT_R1", - "CLK_HROW_LOGIC_OUTS_B3_1", - "CLK_HROW_SE4BEG3_7", - "CLK_HROW_BYP5_5", - "CLK_HROW_IMUX30_1", - "CLK_HROW_EE4C1_1", - "CLK_HROW_CK_BUFHCLK_R9", - "CLK_HROW_BYP3_1", - "CLK_HROW_WW4C3_7", - "CLK_HROW_SE2A3_2", - "CLK_HROW_EE2A2_2", - "CLK_HROW_CK_IN_L2", - "CLK_HROW_LH11_1", - "CLK_HROW_IMUX35_7", - "CLK_HROW_NE4C1_2", - "CLK_HROW_EE4B0_7", - "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "CLK_HROW_EE4B3_1", - "CLK_HROW_WW2A0_5", - "CLK_HROW_WW4C3_5", - "CLK_HROW_IMUX28_4", - "CLK_HROW_LH10_5", - "CLK_HROW_EE4B2_6", - "CLK_HROW_IMUX12_4", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_LH9_3", - "CLK_HROW_CK_GCLK_TEST_IN15", - "CLK_HROW_IMUX32_7", - "CLK_HROW_IMUX4_1", - "CLK_HROW_WW4C1_4", - "CLK_HROW_IMUX36_0", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "CLK_HROW_IMUX26_2", - "CLK_HROW_WW4END1_5", - "CLK_HROW_FAN3_5", - "CLK_HROW_CK_INT_0_1", - "CLK_HROW_SW2A0_6", - "CLK_HROW_SW4END3_5", - "CLK_HROW_NE2A0_6", - "CLK_HROW_CK_GCLK_IN_TEST5", - "CLK_HROW_CK_BUFHCLK_L5", - "CLK_HROW_IMUX32_6", - "CLK_HROW_IMUX40_5", - "CLK_HROW_CK_GCLK_IN_TEST10", - "CLK_HROW_EE4B2_7", - "CLK_HROW_SE4C3_6", - "CLK_HROW_LOGIC_OUTS_B4_2", - "CLK_HROW_NW4A3_0", - "CLK_HROW_LOGIC_OUTS_B15_5", - "CLK_HROW_BYP4_1", - "CLK_HROW_NE2A3_1", - "CLK_HROW_R_CK_GCLK14", - "CLK_HROW_IMUX47_6", - "CLK_HROW_LOGIC_OUTS_B12_1", - "CLK_HROW_IMUX19_6", - "CLK_HROW_IMUX33_5", - "CLK_HROW_EE4A1_4", - "CLK_HROW_CK_GCLK_TEST_IN7", - "CLK_HROW_NW4END2_6", - "CLK_HROW_SW4END0_4", - "CLK_HROW_CK_BUFRCLK_L0", - "CLK_HROW_IMUX1_3", - "CLK_HROW_NW2A0_4", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_NE4BEG1_5", - "CLK_HROW_SW4END0_1", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN20", - "CLK_HROW_CK_GCLK_OUT_TEST29", - "CLK_HROW_CK_MUX_OUT_L3", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_R_CK_GCLK29", - "CLK_HROW_BYP3_0", - "CLK_HROW_CK_MUX_OUT_L10", - "CLK_HROW_CK_GCLK_TEST_IN3", - "CLK_HROW_BYP0_0", - "CLK_HROW_LH12_1", - "CLK_HROW_BUFHCE_CE_L7", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG0_5", - "CLK_HROW_SE4C1_4", - "CLK_HROW_BLOCK_OUTS_B0_7", - "CLK_HROW_BLOCK_OUTS_B3_5", - "CLK_HROW_SW4A1_5", - "CLK_HROW_EE4C1_5", - "CLK_HROW_IMUX13_1", - "CLK_HROW_IMUX38_2", - "CLK_HROW_R_CK_GCLK3", - "CLK_HROW_LH8_7", - "CLK_HROW_NW2A1_5", - "CLK_HROW_CK_GCLK_TEST_OUT19", - "CLK_HROW_IMUX36_6", - "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "CLK_HROW_LH7_6", - "CLK_HROW_NW2A3_7", - "CLK_HROW_ER1BEG2_6", - "CLK_HROW_NE4BEG3_7", - "CLK_HROW_WW2END1_6", - "CLK_HROW_IMUX27_4", - "CLK_HROW_SW4END2_2", - "CLK_HROW_NE2A1_4", - "CLK_HROW_LH8_6", - "CLK_HROW_CLK0_5", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN1", - "CLK_HROW_BYP2_7", - "CLK_HROW_CK_GCLK_TEST_OUT5", - "CLK_HROW_LH2_1", - "CLK_HROW_SW2A0_0", - "CLK_HROW_IMUX46_3", - "CLK_HROW_IMUX46_0", - "CLK_HROW_IMUX32_0", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_NW2A0_6", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_LH5_6", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_NE4C2_4", - "CLK_HROW_WL1END1_2", - "CLK_HROW_NW2A2_1", - "CLK_HROW_IMUX22_7", - "CLK_HROW_NE4C2_2", - "CLK_HROW_CK_GCLK_TEST_IN20", - "CLK_HROW_WR1END0_6", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_BYP2_4", - "CLK_HROW_IMUX18_0", - "CLK_HROW_IMUX11_5", - "CLK_HROW_LH6_4", - "CLK_HROW_SW4END2_4", - "CLK_HROW_CK_GCLK_TEST_IN18", - "CLK_HROW_IMUX28_1", - "CLK_HROW_CK_GCLK_TEST10", - "CLK_HROW_CK_MUX_OUT_R7", - "CLK_HROW_SW4A0_2", - "CLK_HROW_IMUX24_4", - "CLK_HROW_IMUX23_5", - "CLK_HROW_LOGIC_OUTS_B1_3", - "CLK_HROW_IMUX7_3", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_LOGIC_OUTS_B10_5", - "CLK_HROW_NE2A3_0", - "CLK_HROW_EE4C2_2", - "CLK_HROW_LOGIC_OUTS_B13_7", - "CLK_HROW_IMUX32_3", - "CLK_HROW_LOGIC_OUTS_B1_5", - "CLK_HROW_WL1END1_4", - "CLK_HROW_CLK0_0", - "CLK_HROW_IMUX4_6", - "CLK_HROW_NE4C1_6", - "CLK_HROW_IMUX31_1", - "CLK_HROW_LOGIC_OUTS_B14_0", - "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "CLK_HROW_WW4END3_1", - "CLK_HROW_BYP0_1", - "CLK_HROW_IMUX29_5", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A0_0", - "CLK_HROW_CE_INT_TOP10", - "CLK_HROW_IMUX22_2", - "CLK_HROW_BUFHCE_CE_R2", - "CLK_HROW_CK_GCLK_TEST4", - "CLK_HROW_CK_MUX_OUT_L9", - "CLK_HROW_NE2A1_3", - "CLK_HROW_LOGIC_OUTS_B7_4", - "CLK_HROW_IMUX6_2", - "CLK_HROW_WW4A0_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_IMUX24_0", - "CLK_HROW_LOGIC_OUTS_B15_6", - "CLK_HROW_IMUX21_4", - "CLK_HROW_BUFHCE_CE_L1", - "CLK_HROW_IMUX17_4", - "CLK_HROW_WW4C3_3", - "CLK_HROW_BLOCK_OUTS_B3_6", - "CLK_HROW_SE4BEG2_4", - "CLK_HROW_IMUX28_3", - "CLK_HROW_CK_MUX_OUT_R8", - "CLK_HROW_NE4C1_7", - "CLK_HROW_IMUX41_4", - "CLK_HROW_EL1BEG3_5", - "CLK_HROW_NE4C1_0", - "CLK_HROW_EL1BEG1_6", - "CLK_HROW_LOGIC_OUTS_B0_1", - "CLK_HROW_WW2A0_0", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN16", - "CLK_HROW_IMUX37_0", - "CLK_HROW_BYP7_0", - "CLK_HROW_SE4BEG3_4", - "CLK_HROW_WW4B0_4", - "CLK_HROW_CE_INT_BOT7", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_IMUX27_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_BLOCK_OUTS_B1_7", - "CLK_HROW_EE2A2_1", - "CLK_HROW_LOGIC_OUTS_B18_2", - "CLK_HROW_CK_GCLK_TEST_OUT18", - "CLK_HROW_NW2A1_2", - "CLK_HROW_LOGIC_OUTS_B23_1", - "CLK_HROW_WW2A3_0", - "CLK_HROW_IMUX39_4", - "CLK_HROW_SW4A1_4", - "CLK_HROW_CK_GCLK_TEST17", - "CLK_HROW_NE4C3_4", - "CLK_HROW_IMUX7_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LOGIC_OUTS_B23_3", - "CLK_HROW_CK_HCLK_OUT_L1", - "CLK_HROW_CK_GCLK_TEST_OUT3", - "CLK_HROW_CK_HCLK_OUT_L9", - "CLK_HROW_WW2A0_6", - "CLK_HROW_IMUX14_4", - "CLK_HROW_CK_BUFHCLK_R8", - "CLK_HROW_FAN2_5", - "CLK_HROW_SE2A1_2", - "CLK_HROW_WL1END3_5", - "CLK_HROW_NW4END1_7", - "CLK_HROW_BYP3_7", - "CLK_HROW_LH4_7", - "CLK_HROW_CTRL1_3", - "CLK_HROW_WW4A0_4", - "CLK_HROW_LH5_2", - "CLK_HROW_IMUX10_4", - "CLK_HROW_IMUX3_7", - "CLK_HROW_LOGIC_OUTS_B16_3", - "CLK_HROW_CTRL1_4", - "CLK_HROW_CTRL1_6", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_IMUX17_0", - "CLK_HROW_IMUX9_6", - "CLK_HROW_CK_HCLK_OUT_L11", - "CLK_HROW_WW4A2_4", - "CLK_HROW_IMUX3_1", - "CLK_HROW_EE4A0_0", - "CLK_HROW_IMUX13_0", - "CLK_HROW_LOGIC_OUTS_B18_1", - "CLK_HROW_WW4B0_3", - "CLK_HROW_LOGIC_OUTS_B9_7", - "CLK_HROW_WW2A2_5", - "CLK_HROW_SW4END0_3", - "CLK_HROW_R_CK_GCLK31", - "CLK_HROW_WW2A1_5", - "CLK_HROW_WW2END0_5", - "CLK_HROW_SE2A2_2", - "CLK_HROW_EE4C2_6", - "CLK_HROW_CK_GCLK_TEST14", - "CLK_HROW_CK_GCLK_IN_TEST16", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN7_4", - "CLK_HROW_IMUX40_4", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_IMUX10_6", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_LH8_2", - "CLK_HROW_ER1BEG1_7", - "CLK_HROW_CK_IN_R1", - "CLK_HROW_IMUX31_3", - "CLK_HROW_CK_GCLK_TEST16", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4C0_0", - "CLK_HROW_CK_BUFHCLK_R2", - "CLK_HROW_CK_GCLK_IN_TEST9", - "CLK_HROW_WW2END3_6", - "CLK_HROW_CK_GCLK_TEST_IN6", - "CLK_HROW_IMUX46_4", - "CLK_HROW_CK_MUX_OUT_L8", - "CLK_HROW_WW4B3_2", - "CLK_HROW_FAN0_1", - "CLK_HROW_IMUX25_1", - "CLK_HROW_IMUX42_7", - "CLK_HROW_EE2A2_0", - "CLK_HROW_NE4BEG3_4", - "CLK_HROW_NW2A1_7", - "CLK_HROW_CK_GCLK_OUT_TEST5", - "CLK_HROW_LOGIC_OUTS_B18_5", - "CLK_HROW_WW4B3_4", - "CLK_HROW_LOGIC_OUTS_B20_4", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW4B1_1", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_IMUX15_0", - "CLK_HROW_EE4BEG2_7", - "CLK_HROW_WW4END3_7", - "CLK_HROW_NW4END1_3", - "CLK_HROW_WR1END1_3", - "CLK_HROW_CK_IN_R3", - "CLK_HROW_FAN7_0", - "CLK_HROW_NW4END0_5", - "CLK_HROW_WW4C3_1", - "CLK_HROW_FAN2_0", - "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "CLK_HROW_EE2BEG3_5", - "CLK_HROW_CE_INT_TOP8", - "CLK_HROW_SE2A0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_CK_GCLK_OUT_TEST3", - "CLK_HROW_R_CK_GCLK9", - "CLK_HROW_NW2A0_1", - "CLK_HROW_CK_GCLK_TEST25", - "CLK_HROW_WW4A0_7", - "CLK_HROW_BYP1_7", - "CLK_HROW_SW2A1_1", - "CLK_HROW_CK_GCLK_TEST_IN0", - "CLK_HROW_NW2A2_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_FAN4_4", - "CLK_HROW_SE2A1_3", - "CLK_HROW_BUFHCE_CE_R7", - "CLK_HROW_SW4END2_1", - "CLK_HROW_IMUX24_2", - "CLK_HROW_IMUX44_5", - "CLK_HROW_CK_IN_R5", - "CLK_HROW_LOGIC_OUTS_B9_6", - "CLK_HROW_SE4C2_3", - "CLK_HROW_IMUX35_5", - "CLK_HROW_IMUX42_1", - "CLK_HROW_IMUX18_1", - "CLK_HROW_LOGIC_OUTS_B4_7", - "CLK_HROW_EE4BEG2_5", - "CLK_HROW_WW4C2_1", - "CLK_HROW_SW4END1_7", - "CLK_HROW_FAN0_4", - "CLK_HROW_LOGIC_OUTS_B1_0", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_SW4A0_7", - "CLK_HROW_LOGIC_OUTS_B16_4", - "CLK_HROW_WW4B2_2", - "CLK_HROW_ER1BEG3_4", - "CLK_HROW_EE4A0_2", - "CLK_HROW_NE4C3_7", - "CLK_HROW_LH12_2", - "CLK_HROW_IMUX23_6", - "CLK_HROW_EE4B2_0", - "CLK_HROW_CK_INT_0_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_NE4BEG1_6", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_LH7_3", - "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "CLK_HROW_CK_IN_L11", - "CLK_HROW_FAN7_7", - "CLK_HROW_EE4BEG3_7", - "CLK_HROW_FAN6_2", - "CLK_HROW_BYP0_5", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN2", - "CLK_HROW_WW4C2_7", - "CLK_HROW_LH10_1", - "CLK_HROW_NE4C2_5", - "CLK_HROW_LOGIC_OUTS_B0_6", - "CLK_HROW_FAN7_1", - "CLK_HROW_BYP6_0", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_NE2A3_5", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP0_6", - "CLK_HROW_SW4END1_1", - "CLK_HROW_WL1END3_3", - "CLK_HROW_CK_GCLK_TEST19", - "CLK_HROW_IMUX29_1", - "CLK_HROW_WW2END0_1", - "CLK_HROW_IMUX17_6", - "CLK_HROW_EE4C2_5", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE2BEG0_5", - "CLK_HROW_CK_GCLK_OUT_TEST12", - "CLK_HROW_EE2BEG3_7", - "CLK_HROW_CK_GCLK_TEST_OUT20", - "CLK_HROW_EE2A0_2", - "CLK_HROW_EE4A2_4", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_IMUX46_7", - "CLK_HROW_IMUX38_1", - "CLK_HROW_CK_IN_R9", - "CLK_HROW_CLK1_6", - "CLK_HROW_CK_IN_L13", - "CLK_HROW_R_CK_GCLK17", - "CLK_HROW_IMUX39_2", - "CLK_HROW_WR1END3_2", - "CLK_HROW_NE4BEG0_6", - "CLK_HROW_CK_GCLK_TEST18", - "CLK_HROW_SE2A2_3", - "CLK_HROW_WR1END1_6", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_LOGIC_OUTS_B19_4", - "CLK_HROW_LOGIC_OUTS_B6_6", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_IMUX30_2", - "CLK_HROW_SW4END0_6", - "CLK_HROW_FAN5_0", - "CLK_HROW_CE_INT_TOP9", - "CLK_HROW_SW4A1_7", - "CLK_HROW_CK_GCLK_TEST_OUT13", - "CLK_HROW_SE2A2_0", - "CLK_HROW_IMUX12_7", - "CLK_HROW_CK_GCLK_TEST30", - "CLK_HROW_LOGIC_OUTS_B14_7", - "CLK_HROW_EE4BEG1_4", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_SW4A3_2", - "CLK_HROW_IMUX7_5", - "CLK_HROW_CK_MUX_OUT_R0", - "CLK_HROW_IMUX33_6", - "CLK_HROW_WR1END0_5", - "CLK_HROW_NW4A3_1", - "CLK_HROW_SE4C1_1", - "CLK_HROW_EE2A2_6", - "CLK_HROW_IMUX42_4", - "CLK_HROW_IMUX23_4", - "CLK_HROW_NE4C0_6", - "CLK_HROW_LH3_1", - "CLK_HROW_NW4A0_3", - "CLK_HROW_LOGIC_OUTS_B2_2", - "CLK_HROW_CK_GCLK_TEST_IN10", - "CLK_HROW_WW4A0_5", - "CLK_HROW_SW4END1_5", - "CLK_HROW_MONITOR_P_7", - "CLK_HROW_IMUX26_0", - "CLK_HROW_WW4C3_6", - "CLK_HROW_IMUX16_0", - "CLK_HROW_IMUX42_6", - "CLK_HROW_IMUX19_3", - "CLK_HROW_LOGIC_OUTS_B19_2", - "CLK_HROW_CTRL1_5", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW2END0_7", - "CLK_HROW_LH7_0", - "CLK_HROW_FAN0_0", - "CLK_HROW_WL1END1_5", - "CLK_HROW_R_CK_GCLK2", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN10", - "CLK_HROW_LOGIC_OUTS_B6_0", - "CLK_HROW_EE4B1_5", - "CLK_HROW_LOGIC_OUTS_B12_0", - "CLK_HROW_IMUX2_6", - "CLK_HROW_ER1BEG2_7", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_7", - "CLK_HROW_NW4END0_4", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_SE4C2_0", - "CLK_HROW_NE4BEG2_7", - "CLK_HROW_WW4A0_3", - "CLK_HROW_ER1BEG1_6", - "CLK_HROW_EE4B0_2", - "CLK_HROW_LH6_1", - "CLK_HROW_EL1BEG3_7", - "CLK_HROW_FAN3_4", - "CLK_HROW_NE4C3_6", - "CLK_HROW_BYP7_1", - "CLK_HROW_CK_MUX_OUT_L1", - "CLK_HROW_EE4BEG3_4", - "CLK_HROW_CK_GCLK_TEST20", - "CLK_HROW_IMUX21_7", - "CLK_HROW_LOGIC_OUTS_B7_1", - "CLK_HROW_LH3_4", - "CLK_HROW_CK_GCLK_TEST_OUT7", - "CLK_HROW_IMUX7_7", - "CLK_HROW_CK_HCLK_OUT_L7", - "CLK_HROW_EE2A0_0", - "CLK_HROW_WL1END2_0", - "CLK_HROW_IMUX20_5", - "CLK_HROW_LOGIC_OUTS_B8_3", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_IMUX28_5", - "CLK_HROW_LH12_4", - "CLK_HROW_WR1END3_4", - "CLK_HROW_WW4C1_7", - "CLK_HROW_LOGIC_OUTS_B21_2", - "CLK_HROW_CK_GCLK_TEST_OUT9", - "CLK_HROW_NE4C1_3", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4A3_3", - "CLK_HROW_NE2A1_7", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_SW2A3_7", - "CLK_HROW_CK_GCLK_TEST_OUT11", - "CLK_HROW_LH2_3", - "CLK_HROW_IMUX5_7", - "CLK_HROW_LH10_0", - "CLK_HROW_IMUX30_5", - "CLK_HROW_LOGIC_OUTS_B18_3", - "CLK_HROW_IMUX32_4", - "CLK_HROW_CK_MUX_OUT_R5", - "CLK_HROW_SW2A1_2", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_NW4END2_0", - "CLK_HROW_WW2A1_4", - "CLK_HROW_IMUX45_1", - "CLK_HROW_CK_HCLK_OUT_R5", - "CLK_HROW_EE4C0_1", - "CLK_HROW_WR1END2_4", - "CLK_HROW_WR1END0_1", - "CLK_HROW_SE2A2_4", - "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "CLK_HROW_SE4C1_7", - "CLK_HROW_NW4END1_2", - "CLK_HROW_LOGIC_OUTS_B11_0", - "CLK_HROW_R_CK_GCLK25", - "CLK_HROW_SW2A2_2", - "CLK_HROW_WW2END0_0", - "CLK_HROW_SE4C0_7", - "CLK_HROW_LOGIC_OUTS_B2_0", - "CLK_HROW_IMUX26_3", - "CLK_HROW_BUFHCE_CE_R1", - "CLK_HROW_NE4C1_4", - "CLK_HROW_LOGIC_OUTS_B23_0", - "CLK_HROW_NE2A2_5", - "CLK_HROW_IMUX35_4", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW2END1_7", - "CLK_HROW_LH3_3", - "CLK_HROW_CTRL1_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_LOGIC_OUTS_B19_0", - "CLK_HROW_NE2A2_6", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_CK_GCLK_TEST9", - "CLK_HROW_NE2A3_2", - "CLK_HROW_WW4B0_2", - "CLK_HROW_IMUX8_2", - "CLK_HROW_LH11_2", - "CLK_HROW_NE4BEG2_5", - "CLK_HROW_NW4END3_5", - "CLK_HROW_BLOCK_OUTS_B1_5", - "CLK_HROW_LOGIC_OUTS_B21_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_SE4C3_0", - "CLK_HROW_IMUX21_2", - "CLK_HROW_SE4C1_5", - "CLK_HROW_CK_GCLK_IN_TEST29", - "CLK_HROW_EE2A0_5", - "CLK_HROW_LOGIC_OUTS_B21_3", - "CLK_HROW_REFCK_EASTCLK1", - "CLK_HROW_IMUX6_4", - "CLK_HROW_CK_GCLK_TEST_IN1", - "CLK_HROW_NE2A3_6", - "CLK_HROW_NW4A0_0", - "CLK_HROW_CE_INT_TOP2", - "CLK_HROW_IMUX29_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_IMUX11_7", - "CLK_HROW_IMUX22_6", - "CLK_HROW_SE4C0_6", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_IMUX38_6", - "CLK_HROW_SE2A1_6", - "CLK_HROW_REFCK_EASTCLK0", - "CLK_HROW_CK_MUX_OUT_L6", - "CLK_HROW_WW4C0_3", - "CLK_HROW_IMUX8_6", - "CLK_HROW_IMUX34_1", - "CLK_HROW_WR1END3_5", - "CLK_HROW_LOGIC_OUTS_B9_5", - "CLK_HROW_CK_GCLK_TEST12", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_1", - "CLK_HROW_MONITOR_N_7", - "CLK_HROW_SW2A3_1", - "CLK_HROW_LH8_3", - "CLK_HROW_IMUX9_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "CLK_HROW_CK_GCLK_IN_TEST3", - "CLK_HROW_LH9_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_EE2A1_2", - "CLK_HROW_CK_GCLK_IN_TEST24", - "CLK_HROW_BYP4_7", - "CLK_HROW_LH2_2", - "CLK_HROW_IMUX2_2", - "CLK_HROW_SW4END1_2", - "CLK_HROW_NW2A1_4", - "CLK_HROW_IMUX2_5", - "CLK_HROW_IMUX10_1", - "CLK_HROW_EE4B2_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_FAN5_7", - "CLK_HROW_IMUX38_4", - "CLK_HROW_LOGIC_OUTS_B16_2", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WW4B1_6", - "CLK_HROW_BLOCK_OUTS_B0_5", - "CLK_HROW_EE4A2_0", - "CLK_HROW_IMUX16_7", - "CLK_HROW_WW4B1_7", - "CLK_HROW_WL1END2_7", - "CLK_HROW_EE4BEG1_5", - "CLK_HROW_SW4A0_5", - "CLK_HROW_EE4C2_7", - "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "CLK_HROW_IMUX39_0", - "CLK_HROW_CLK0_6", - "CLK_HROW_CK_GCLK_TEST0", - "CLK_HROW_CK_HCLK_OUT_L2", - "CLK_HROW_LH10_2", - "CLK_HROW_CK_BUFRCLK_R1", - "CLK_HROW_WW4A3_0", - "CLK_HROW_CE_INT_TOP11", - "CLK_HROW_IMUX22_3", - "CLK_HROW_CK_IN_L12", - "CLK_HROW_WW4B0_5", - "CLK_HROW_CK_GCLK_TEST_OUT22", - "CLK_HROW_CK_BUFHCLK_L4", - "CLK_HROW_IMUX10_3", - "CLK_HROW_WW4A1_7", - "CLK_HROW_CK_HCLK_OUT_L5", - "CLK_HROW_IMUX1_4", - "CLK_HROW_LH11_7", - "CLK_HROW_LOGIC_OUTS_B22_4", - "CLK_HROW_CTRL0_7", - "CLK_HROW_EE4C3_2", - "CLK_HROW_CE_INT_TOP6", - "CLK_HROW_CK_MUX_OUT_R11", - "CLK_HROW_NE4BEG0_4", - "CLK_HROW_SW2A2_4", - "CLK_HROW_IMUX6_0", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_BLOCK_OUTS_B2_7", - "CLK_HROW_BLOCK_OUTS_B0_6", - "CLK_HROW_IMUX23_0", - "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "CLK_HROW_CK_GCLK_IN_TEST8", - "CLK_HROW_BYP7_7", - "CLK_HROW_IMUX25_3", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN22", - "CLK_HROW_SE4C1_6", - "CLK_HROW_LOGIC_OUTS_B6_1", - "CLK_HROW_CK_GCLK_OUT_TEST19", - "CLK_HROW_IMUX25_6", - "CLK_HROW_IMUX5_4", - "CLK_HROW_EE2A2_4", - "CLK_HROW_IMUX13_6", - "CLK_HROW_R_CK_GCLK30", - "CLK_HROW_CK_IN_L_OUT_TEST", - "CLK_HROW_SE4C1_3", - "CLK_HROW_LOGIC_OUTS_B4_3", - "CLK_HROW_R_CK_GCLK4", - "CLK_HROW_ER1BEG1_4", - "CLK_HROW_SE2A3_1", - "CLK_HROW_IMUX15_2", - "CLK_HROW_IMUX31_6", - "CLK_HROW_IMUX4_2", - "CLK_HROW_IMUX30_0", - "CLK_HROW_LOGIC_OUTS_B21_7", - "CLK_HROW_LOGIC_OUTS_B11_3", - "CLK_HROW_LOGIC_OUTS_B12_2", - "CLK_HROW_IMUX14_7", - "CLK_HROW_NW4A3_3", - "CLK_HROW_LOGIC_OUTS_B14_3", - "CLK_HROW_SE2A1_0", - "CLK_HROW_EE4C2_0", - "CLK_HROW_IMUX45_7", - "CLK_HROW_WL1END1_0", - "CLK_HROW_IMUX19_2", - "CLK_HROW_CK_GCLK_TEST_IN13", - "CLK_HROW_WW4C2_6", - "CLK_HROW_CK_BUFHCLK_R5", - "CLK_HROW_CK_GCLK_TEST_OUT1", - "CLK_HROW_NW2A1_0", - "CLK_HROW_IMUX29_2", - "CLK_HROW_CK_GCLK_TEST_OUT0", - "CLK_HROW_IMUX11_4", - "CLK_HROW_NW4END2_1", - "CLK_HROW_CK_BUFHCLK_R0", - "CLK_HROW_LOGIC_OUTS_B22_6", - "CLK_HROW_SE2A0_7", - "CLK_HROW_SE4BEG1_5", - "CLK_HROW_IMUX13_7", - "CLK_HROW_LOGIC_OUTS_B17_3", - "CLK_HROW_CK_BUFHCLK_L8", - "CLK_HROW_EE2A3_2", - "CLK_HROW_CK_BUFHCLK_L1", - "CLK_HROW_IMUX1_6", - "CLK_HROW_LOGIC_OUTS_B22_3", - "CLK_HROW_LOGIC_OUTS_B5_2", - "CLK_HROW_CK_GCLK_TEST_OUT31", - "CLK_HROW_CK_IN_R13", - "CLK_HROW_CE_INT_BOT0", - "CLK_HROW_EE4B3_0", - "CLK_HROW_LOGIC_OUTS_B5_7", - "CLK_HROW_NW4A1_6", - "CLK_HROW_SE2A2_5", - "CLK_HROW_SW4END1_0", - "CLK_HROW_LOGIC_OUTS_B20_5", - "CLK_HROW_SE2A1_7", - "CLK_HROW_NW4END2_2", - "CLK_HROW_IMUX3_5", - "CLK_HROW_CK_GCLK_TEST_IN19", - "CLK_HROW_WW4C3_2", - "CLK_HROW_IMUX34_7", - "CLK_HROW_IMUX31_0", - "CLK_HROW_IMUX36_7", - "CLK_HROW_IMUX42_5", - "CLK_HROW_LOGIC_OUTS_B8_2", - "CLK_HROW_IMUX34_6", - "CLK_HROW_IMUX47_3", - "CLK_HROW_IMUX41_7", - "CLK_HROW_LOGIC_OUTS_B21_6", - "CLK_HROW_LOGIC_OUTS_B14_4", - "CLK_HROW_LOGIC_OUTS_B17_0", - "CLK_HROW_CK_GCLK_OUT_TEST23", - "CLK_HROW_SE2A3_6", - "CLK_HROW_LOGIC_OUTS_B14_2", - "CLK_HROW_IMUX43_0", - "CLK_HROW_BYP2_5", - "CLK_HROW_WL1END2_2", - "CLK_HROW_IMUX29_4", - "CLK_HROW_EE2A0_6", - "CLK_HROW_CK_GCLK_TEST_IN23", - "CLK_HROW_IMUX29_6", - "CLK_HROW_CK_GCLK_TEST_IN4", - "CLK_HROW_IMUX2_0", - "CLK_HROW_LOGIC_OUTS_B7_7", - "CLK_HROW_NE2A1_6", - "CLK_HROW_LH6_7", - "CLK_HROW_WW4END0_3", - "CLK_HROW_IMUX22_5", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN7", - "CLK_HROW_IMUX9_5", - "CLK_HROW_IMUX32_5", - "CLK_HROW_NE4C2_0", - "CLK_HROW_CK_HCLK_OUT_R8", - "CLK_HROW_EE4BEG0_5", - "CLK_HROW_SW4A2_5", - "CLK_HROW_EE4C3_7", - "CLK_HROW_BYP7_6", - "CLK_HROW_EE4B1_7", - "CLK_HROW_WW4C2_4", - "CLK_HROW_WW4END0_7", - "CLK_HROW_CK_GCLK_IN_TEST6", - "CLK_HROW_LOGIC_OUTS_B20_7", - "CLK_HROW_CK_GCLK_OUT_TEST8", - "CLK_HROW_FAN1_7", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_CK_GCLK_TEST28", - "CLK_HROW_NW4END1_5", - "CLK_HROW_IMUX19_0", - "CLK_HROW_CK_GCLK_OUT_TEST27", - "CLK_HROW_WL1END0_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN4", - "CLK_HROW_EL1BEG3_6", - "CLK_HROW_IMUX6_6", - "CLK_HROW_IMUX43_4", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_IMUX27_0", - "CLK_HROW_LOGIC_OUTS_B13_3", - "CLK_HROW_LOGIC_OUTS_B2_5", - "CLK_HROW_WW2END1_3", - "CLK_HROW_LOGIC_OUTS_B4_5", - "CLK_HROW_LOGIC_OUTS_B8_4", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4A2_6", - "CLK_HROW_IMUX7_1", - "CLK_HROW_IMUX42_3", - "CLK_HROW_LOGIC_OUTS_B2_6", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WR1END2_0", - "CLK_HROW_IMUX16_2", - "CLK_HROW_BYP1_1", - "CLK_HROW_LOGIC_OUTS_B9_0", - "CLK_HROW_IMUX10_7", - "CLK_HROW_R_CK_GCLK5", - "CLK_HROW_WW4C2_3", - "CLK_HROW_IMUX17_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN12", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_WL1END3_4", - "CLK_HROW_LOGIC_OUTS_B23_5", - "CLK_HROW_WW2END1_2", - "CLK_HROW_SE4C2_1", - "CLK_HROW_WL1END0_1", - "CLK_HROW_IMUX0_7", - "CLK_HROW_IMUX33_7", - "CLK_HROW_IMUX20_0", - "CLK_HROW_SW4END2_0", - "CLK_HROW_EE4A2_6", - "CLK_HROW_CK_MUX_OUT_R6", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_IMUX15_4", - "CLK_HROW_LOGIC_OUTS_B17_6", - "CLK_HROW_WW4B3_3", - "CLK_HROW_LOGIC_OUTS_B15_2", - "CLK_HROW_LH4_1", - "CLK_HROW_CK_GCLK_IN_TEST4", - "CLK_HROW_SW4A1_6", - "CLK_HROW_WW2A2_6", - "CLK_HROW_SE4BEG2_6", - "CLK_HROW_WW4A2_5", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN1_4", - "CLK_HROW_LH12_6", - "CLK_HROW_CK_IN_R4", - "CLK_HROW_NE4C0_5", - "CLK_HROW_IMUX41_2", - "CLK_HROW_NW2A0_5", - "CLK_HROW_IMUX46_5", - "CLK_HROW_SW4A3_4", - "CLK_HROW_SW4END3_0", - "CLK_HROW_CTRL0_4", - "CLK_HROW_LOGIC_OUTS_B15_7", - "CLK_HROW_NW4A1_3", - "CLK_HROW_LH11_5", - "CLK_HROW_CK_HCLK_OUT_R11", - "CLK_HROW_IMUX0_0", - "CLK_HROW_LOGIC_OUTS_B7_0", - "CLK_HROW_LOGIC_OUTS_B17_7", - "CLK_HROW_R_CK_GCLK8", - "CLK_HROW_NW4END3_6", - "CLK_HROW_SE4BEG1_7", - "CLK_HROW_SW2A2_6", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_EL1BEG1_4", - "CLK_HROW_NW4A0_7", - "CLK_HROW_LOGIC_OUTS_B19_6", - "CLK_HROW_FAN5_1", - "CLK_HROW_ER1BEG0_5", - "CLK_HROW_SW4A0_4", - "CLK_HROW_CK_IN_L_TEST_OUT", - "CLK_HROW_SW4END1_3", - "CLK_HROW_CK_INT_1_0", - "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "CLK_HROW_BLOCK_OUTS_B2_5", - "CLK_HROW_NE4C0_4", - "CLK_HROW_WW4B2_4", - "CLK_HROW_EE4A1_3", - "CLK_HROW_FAN6_1", - "CLK_HROW_EE4C3_0", - "CLK_HROW_BYP1_0", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_BYP1_4", - "CLK_HROW_BUFHCE_CE_R6", - "CLK_HROW_EE4A3_1", - "CLK_HROW_NW4END1_6", - "CLK_HROW_EE2BEG2_4", - "CLK_HROW_IMUX13_5", - "CLK_HROW_CK_BUFHCLK_L0", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_CK_GCLK_TEST5", - "CLK_HROW_LH2_6", - "CLK_HROW_LOGIC_OUTS_B9_4", - "CLK_HROW_WW4END0_5", - "CLK_HROW_WW4C3_4", - "CLK_HROW_IMUX30_3", - "CLK_HROW_IMUX40_0", - "CLK_HROW_IMUX31_4", - "CLK_HROW_EL1BEG2_6", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN8", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE2BEG2_7", - "CLK_HROW_IMUX9_1", - "CLK_HROW_WW4B1_5", - "CLK_HROW_IMUX13_3", - "CLK_HROW_LOGIC_OUTS_B0_2", - "CLK_HROW_LH3_6", - "CLK_HROW_WW2END2_5", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_IMUX18_6", - "CLK_HROW_WL1END0_7", - "CLK_HROW_SW4A0_6", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_FAN7_3", - "CLK_HROW_IMUX31_7", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN0", - "CLK_HROW_WW4B0_0", - "CLK_HROW_BLOCK_OUTS_B1_6", - "CLK_HROW_IMUX29_3", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NE2A0_1", - "CLK_HROW_BUFHCE_CE_R10", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_FAN3_6", - "CLK_HROW_EE2A3_3", - "CLK_HROW_SW4END2_3", - "CLK_HROW_LH1_1", - "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "CLK_HROW_MONITOR_P_6", - "CLK_HROW_WL1END3_1", - "CLK_HROW_LH4_6", - "CLK_HROW_WW4C1_0", - "CLK_HROW_IMUX24_1", - "CLK_HROW_CK_MUX_OUT_R4", - "CLK_HROW_CK_GCLK_IN_TEST22", - "CLK_HROW_BYP6_7", - "CLK_HROW_EE4A1_0", - "CLK_HROW_CK_GCLK_OUT_TEST13", - "CLK_HROW_R_CK_GCLK12", - "CLK_HROW_NE4C2_7", - "CLK_HROW_IMUX31_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN29", - "CLK_HROW_CK_GCLK_OUT_TEST11", - "CLK_HROW_LOGIC_OUTS_B0_3", - "CLK_HROW_WW4END0_4", - "CLK_HROW_IMUX25_0", - "CLK_HROW_NE2A2_4", - "CLK_HROW_BUFHCE_CE_L8", - "CLK_HROW_EE4C1_4", - "CLK_HROW_WW2A3_3", - "CLK_HROW_LOGIC_OUTS_B9_2", - "CLK_HROW_CLK0_7", - "CLK_HROW_NW4A2_5", - "CLK_HROW_CK_GCLK_TEST_IN27", - "CLK_HROW_CK_GCLK_OUT_TEST28", - "CLK_HROW_IMUX0_1", - "CLK_HROW_IMUX27_6", - "CLK_HROW_CK_GCLK_OUT_TEST7", - "CLK_HROW_NE4BEG3_6", - "CLK_HROW_IMUX15_5", - "CLK_HROW_LOGIC_OUTS_B19_7", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_NW2A2_6", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_SW4A0_0", - "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "CLK_HROW_LH9_1", - "CLK_HROW_FAN0_6", - "CLK_HROW_IMUX22_0", - "CLK_HROW_LH1_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "CLK_HROW_IMUX23_3", - "CLK_HROW_LOGIC_OUTS_B5_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_WW4B2_0", - "CLK_HROW_IMUX35_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WW4B3_7", - "CLK_HROW_NE2A0_4", - "CLK_HROW_SW4A2_6", - "CLK_HROW_SW2A0_7", - "CLK_HROW_EE4A3_7", - "CLK_HROW_IMUX21_6", - "CLK_HROW_IMUX45_2", - "CLK_HROW_EL1BEG1_7", - "CLK_HROW_IMUX41_0", - "CLK_HROW_EE4C3_4", - "CLK_HROW_SW2A3_3", - "CLK_HROW_CK_GCLK_TEST_IN22", - "CLK_HROW_LH9_4", - "CLK_HROW_LOGIC_OUTS_B7_3", - "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "CLK_HROW_IMUX10_5", - "CLK_HROW_ER1BEG3_6", - "CLK_HROW_SW2A1_7", - "CLK_HROW_BYP3_5", - "CLK_HROW_IMUX20_7", - "CLK_HROW_FAN0_2", - "CLK_HROW_EE2A3_4", - "CLK_HROW_IMUX17_7", - "CLK_HROW_FAN0_7", - "CLK_HROW_NE4C0_3", - "CLK_HROW_CLK0_2", - "CLK_HROW_ER1BEG3_7", - "CLK_HROW_IMUX44_3", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_IMUX12_6", - "CLK_HROW_EE4C0_6", - "CLK_HROW_CK_GCLK_TEST27", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WR1END2_6", - "CLK_HROW_LOGIC_OUTS_B15_4", - "CLK_HROW_LH7_4", - "CLK_HROW_LOGIC_OUTS_B22_0", - "CLK_HROW_R_CK_GCLK21", - "CLK_HROW_CK_GCLK_TEST31", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_LH9_7", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_IMUX16_4", - "CLK_HROW_ER1BEG3_5", - "CLK_HROW_SW4END1_4", - "CLK_HROW_IMUX21_0", - "CLK_HROW_LOGIC_OUTS_B3_4", - "CLK_HROW_EE4A1_1", - "CLK_HROW_IMUX11_2", - "CLK_HROW_CK_GCLK_TEST_IN21", - "CLK_HROW_CE_INT_TOP7", - "CLK_HROW_IMUX39_6", - "CLK_HROW_LH1_4", - "CLK_HROW_SW4A3_3", - "CLK_HROW_IMUX36_3", - "CLK_HROW_WW4A3_6", - "CLK_HROW_EE4BEG0_7", - "CLK_HROW_LH3_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_LH6_5", - "CLK_HROW_EL1BEG1_5", - "CLK_HROW_EE2BEG3_6", - "CLK_HROW_LH5_3", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN28", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WW4C0_6", - "CLK_HROW_CK_GCLK_IN_TEST13", - "CLK_HROW_FAN3_7", - "CLK_HROW_IMUX8_7", - "CLK_HROW_MONITOR_N_5", - "CLK_HROW_SW4A1_3", - "CLK_HROW_LH5_7", - "CLK_HROW_LOGIC_OUTS_B0_7", - "CLK_HROW_CK_MUX_OUT_L4", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN17", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_CE_INT_BOT4", - "CLK_HROW_CK_IN_L9", - "CLK_HROW_WW4C1_2", - "CLK_HROW_BYP5_4", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_SW2A3_6", - "CLK_HROW_LOGIC_OUTS_B6_4", - "CLK_HROW_EE2A1_6", - "CLK_HROW_IMUX28_0", - "CLK_HROW_EE4A1_2", - "CLK_HROW_WW2END3_4", - "CLK_HROW_IMUX37_5", - "CLK_HROW_CK_IN_R_IN_TEST", - "CLK_HROW_LOGIC_OUTS_B17_5", - "CLK_HROW_NE2A2_7", - "CLK_HROW_LOGIC_OUTS_B19_3", - "CLK_HROW_WW2A2_2", - "CLK_HROW_FAN1_6", - "CLK_HROW_REFCK_WESTCLK1", - "CLK_HROW_SE4BEG3_5", - "CLK_HROW_WW4B0_6", - "CLK_HROW_BYP5_7", - "CLK_HROW_CK_HCLK_OUT_L8", - "CLK_HROW_EL1BEG3_4", - "CLK_HROW_LH8_0", - "CLK_HROW_CLK1_4", - "CLK_HROW_FAN2_7", - "CLK_HROW_LH12_3", - "CLK_HROW_EE4A3_6", - "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "CLK_HROW_EE4A3_0", - "CLK_HROW_NE2A3_4", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_LOGIC_OUTS_B13_0", - "CLK_HROW_CK_IN_R2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_WW4END0_2", - "CLK_HROW_NE2A1_5", - "CLK_HROW_CK_GCLK_TEST2", - "CLK_HROW_WW2END2_6", - "CLK_HROW_LH8_4", - "CLK_HROW_SE4C2_7", - "CLK_HROW_CK_IN_R_TEST_OUT", - "CLK_HROW_CK_GCLK_TEST_OUT30", - "CLK_HROW_LOGIC_OUTS_B23_4", - "CLK_HROW_FAN6_0", - "CLK_HROW_LOGIC_OUTS_B22_2", - "CLK_HROW_WW4END0_1", - "CLK_HROW_CK_GCLK_TEST24", - "CLK_HROW_CK_BUFRCLK_R3", - "CLK_HROW_SW4END3_1", - "CLK_HROW_WW2END3_0", - "CLK_HROW_EE2BEG0_4", - "CLK_HROW_IMUX25_5", - "CLK_HROW_NE4C3_1", - "CLK_HROW_IMUX4_7", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN18", - "CLK_HROW_EE2A2_5", - "CLK_HROW_NW4END1_0", - "CLK_HROW_CE_INT_TOP4", - "CLK_HROW_CK_GCLK_TEST_OUT16", - "CLK_HROW_IMUX47_4", - "CLK_HROW_CK_GCLK_IN_TEST28", - "CLK_HROW_CK_IN_L_IN_TEST", - "CLK_HROW_LOGIC_OUTS_B22_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_EE4BEG2_6", - "CLK_HROW_BUFHCE_CE_R8", - "CLK_HROW_SW4END2_7", - "CLK_HROW_IMUX3_2", - "CLK_HROW_NW2A2_4", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_WW4A3_1", - "CLK_HROW_CK_HCLK_OUT_R0", - "CLK_HROW_IMUX5_1", - "CLK_HROW_WL1END1_6", - "CLK_HROW_BYP5_2", - "CLK_HROW_CK_GCLK_TEST_IN17", - "CLK_HROW_EE2BEG0_7", - "CLK_HROW_CK_GCLK_TEST_OUT12", - "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "CLK_HROW_CE_INT_BOT10", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_FAN2_3", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_BYP5_6", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_LOGIC_OUTS_B10_7", - "CLK_HROW_NE4C1_1", - "CLK_HROW_CK_GCLK_IN_TEST30", - "CLK_HROW_FAN2_2", - "CLK_HROW_CK_GCLK_OUT_TEST14", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_LH10_7", - "CLK_HROW_SW2A0_2", - "CLK_HROW_EE2BEG3_4", - "CLK_HROW_IMUX44_7", - "CLK_HROW_LH7_1", - "CLK_HROW_SE4BEG3_6", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EE4A0_5", - "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "CLK_HROW_WW4END1_0", - "CLK_HROW_R_CK_GCLK6", - "CLK_HROW_SE4BEG0_4", - "CLK_HROW_IMUX27_5", - "CLK_HROW_LOGIC_OUTS_B16_1", - "CLK_HROW_SW4END3_3", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_BYP1_3", - "CLK_HROW_LOGIC_OUTS_B19_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_CK_BUFHCLK_L3", - "CLK_HROW_NE2A0_0", - "CLK_HROW_CK_BUFHCLK_L11", - "CLK_HROW_NE2A1_1", - "CLK_HROW_BUFHCE_CE_L5", - "CLK_HROW_LOGIC_OUTS_B12_6", - "CLK_HROW_CK_GCLK_OUT_TEST9", - "CLK_HROW_NW2A2_3", - "CLK_HROW_WW4END2_5", - "CLK_HROW_SW4A3_1", - "CLK_HROW_IMUX39_3", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_WW2A3_1", - "CLK_HROW_IMUX3_6", - "CLK_HROW_R_CK_GCLK13", - "CLK_HROW_LOGIC_OUTS_B14_5", - "CLK_HROW_WR1END0_3", - "CLK_HROW_NW2A2_7", - "CLK_HROW_WW2END1_5", - "CLK_HROW_LOGIC_OUTS_B0_4", - "CLK_HROW_SW2A2_5", - "CLK_HROW_LH5_4", - "CLK_HROW_IMUX34_3", - "CLK_HROW_CK_BUFHCLK_R3", - "CLK_HROW_CK_IN_L5", - "CLK_HROW_CK_GCLK_OUT_TEST26", - "CLK_HROW_LOGIC_OUTS_B14_6", - "CLK_HROW_IMUX12_3", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_LOGIC_OUTS_B2_1", - "CLK_HROW_SW2A1_0", - "CLK_HROW_CK_IN_R12", - "CLK_HROW_CK_GCLK_TEST8", - "CLK_HROW_SW4END3_7", - "CLK_HROW_NW4A1_5", - "CLK_HROW_LOGIC_OUTS_B11_7", - "CLK_HROW_BYP2_3", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_SE4C3_7", - "CLK_HROW_CK_GCLK_TEST_IN9", - "CLK_HROW_BYP2_6", - "CLK_HROW_LH7_7", - "CLK_HROW_WW2A0_4", - "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "CLK_HROW_SW4END3_6", - "CLK_HROW_LOGIC_OUTS_B3_3", - "CLK_HROW_CK_GCLK_TEST_IN31", - "CLK_HROW_LOGIC_OUTS_B20_6", - "CLK_HROW_WW2A2_7", - "CLK_HROW_WW4END2_1", - "CLK_HROW_FAN2_1", - "CLK_HROW_IMUX30_6", - "CLK_HROW_BYP4_4", - "CLK_HROW_CK_HCLK_OUT_R2", - "CLK_HROW_IMUX34_5", - "CLK_HROW_EE4A2_2", - "CLK_HROW_WR1END0_2", - "CLK_HROW_EE4C0_7", - "CLK_HROW_IMUX5_5", - "CLK_HROW_IMUX6_3", - "CLK_HROW_SW2A0_1", - "CLK_HROW_LOGIC_OUTS_B16_0", - "CLK_HROW_FAN4_5", - "CLK_HROW_EE2A0_7", - "CLK_HROW_CK_IN_R11", - "CLK_HROW_NW4A2_6", - "CLK_HROW_CE_INT_BOT3", - "CLK_HROW_IMUX5_2", - "CLK_HROW_NW2A3_4", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_REFCK_WESTCLK0", - "CLK_HROW_NE4C0_7", - "CLK_HROW_LH12_7", - "CLK_HROW_IMUX4_4", - "CLK_HROW_IMUX20_6", - "CLK_HROW_CK_GCLK_OUT_TEST2", - "CLK_HROW_IMUX3_4", - "CLK_HROW_LOGIC_OUTS_B15_3", - "CLK_HROW_CK_BUFHCLK_L9", - "CLK_HROW_NE4C2_6", - "CLK_HROW_LH11_3", - "CLK_HROW_ER1BEG1_5", - "CLK_HROW_IMUX26_5", - "CLK_HROW_MONITOR_P_5", - "CLK_HROW_SE2A3_4", - "CLK_HROW_NW4A2_4", - "CLK_HROW_EE4A0_7", - "CLK_HROW_LOGIC_OUTS_B11_1", - "CLK_HROW_CK_IN_R_TEST_IN", - "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "CLK_HROW_BYP0_7", - "CLK_HROW_CTRL1_7", - "CLK_HROW_WW4C0_2", - "CLK_HROW_LH9_0", - "CLK_HROW_IMUX0_6", - "CLK_HROW_IMUX18_4", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN5", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN9", - "CLK_HROW_WW4C0_0", - "CLK_HROW_CK_IN_L7", - "CLK_HROW_IMUX0_3", - "CLK_HROW_CK_GCLK_OUT_TEST24", - "CLK_HROW_SW2A2_1", - "CLK_HROW_CK_IN_R10", - "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "CLK_HROW_WW4A1_0", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_CK_GCLK_TEST_OUT2", - "CLK_HROW_BYP4_5", - "CLK_HROW_CK_GCLK_OUT_TEST1", - "CLK_HROW_EE4C0_3", - "CLK_HROW_WW4END3_0", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_IMUX20_1", - "CLK_HROW_CK_GCLK_TEST_IN25", - "CLK_HROW_EE4C3_3", - "CLK_HROW_NW4A3_2", - "CLK_HROW_IMUX7_4", - "CLK_HROW_EE2BEG2_6", - "CLK_HROW_EE4C0_5", - "CLK_HROW_WW4A0_6", - "CLK_HROW_SW4A3_7", - "CLK_HROW_WW4A1_2", - "CLK_HROW_CLK1_5", - "CLK_HROW_EE4A1_7", - "CLK_HROW_CK_HCLK_OUT_L3", - "CLK_HROW_LOGIC_OUTS_B7_5", - "CLK_HROW_EE2A1_5", - "CLK_HROW_IMUX11_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE4B1_6", - "CLK_HROW_CK_GCLK_TEST_OUT8", - "CLK_HROW_NE2A0_7", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_WR1END0_0", - "CLK_HROW_NW2A0_2", - "CLK_HROW_LOGIC_OUTS_B3_6", - "CLK_HROW_SW4A2_4", - "CLK_HROW_CK_IN_L10", - "CLK_HROW_CK_BUFRCLK_R2", - "CLK_HROW_BLOCK_OUTS_B0_4", - "CLK_HROW_FAN4_3", - "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "CLK_HROW_CK_GCLK_TEST_IN24", - "CLK_HROW_CK_HCLK_OUT_L0", - "CLK_HROW_EL1BEG0_5", - "CLK_HROW_BYP3_2", - "CLK_HROW_WW2A3_4", - "CLK_HROW_EE4B1_0", - "CLK_HROW_NE4C3_3", - "CLK_HROW_IMUX21_5", - "CLK_HROW_IMUX18_7", - "CLK_HROW_CK_GCLK_TEST26", - "CLK_HROW_CK_GCLK_OUT_TEST0", - "CLK_HROW_CK_GCLK_TEST_IN30", - "CLK_HROW_NE2A2_3", - "CLK_HROW_WR1END3_7", - "CLK_HROW_IMUX0_5", - "CLK_HROW_LH7_5", - "CLK_HROW_LH5_5", - "CLK_HROW_CK_GCLK_IN_TEST12", - "CLK_HROW_NW4END3_2", - "CLK_HROW_SW2A1_5", - "CLK_HROW_IMUX44_1", - "CLK_HROW_IMUX32_2", - "CLK_HROW_BYP6_5", - "CLK_HROW_IMUX27_7", - "CLK_HROW_CE_INT_TOP3", - "CLK_HROW_LOGIC_OUTS_B14_1", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_SE2A1_5", - "CLK_HROW_LH8_1", - "CLK_HROW_CK_HCLK_OUT_R6", - "CLK_HROW_NW4END2_3", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_IMUX2_3", - "CLK_HROW_BYP2_1", - "CLK_HROW_IMUX1_5", - "CLK_HROW_IMUX37_2", - "CLK_HROW_CK_MUX_OUT_L5", - "CLK_HROW_WW2A2_1", - "CLK_HROW_CK_GCLK_TEST_IN28", - "CLK_HROW_LOGIC_OUTS_B11_4", - "CLK_HROW_EE4BEG1_6", - "CLK_HROW_R_CK_GCLK1", - "CLK_HROW_IMUX4_5", - "CLK_HROW_NW4A0_6", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_IMUX20_4", - "CLK_HROW_CK_GCLK_TEST23", - "CLK_HROW_CK_GCLK_TEST_OUT21", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_IMUX26_7", - "CLK_HROW_CK_GCLK_IN_TEST7", - "CLK_HROW_IMUX43_2", - "CLK_HROW_FAN1_2", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_LOGIC_OUTS_B17_2", - "CLK_HROW_CTRL0_0", - "CLK_HROW_IMUX45_5", - "CLK_HROW_LH6_6", - "CLK_HROW_CK_GCLK_TEST_IN12", - "CLK_HROW_LOGIC_OUTS_B22_5", - "CLK_HROW_LOGIC_OUTS_B10_0", - "CLK_HROW_WW4END3_5", - "CLK_HROW_ER1BEG0_4", - "CLK_HROW_IMUX12_5", - "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "CLK_HROW_CK_IN_R8", - "CLK_HROW_SE2A3_3", - "CLK_HROW_EE4B1_1", - "CLK_HROW_IMUX45_4", - "CLK_HROW_SW4END1_6", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4A2_7", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_WW4END3_3", - "CLK_HROW_CK_IN_R7", - "CLK_HROW_IMUX33_0", - "CLK_HROW_IMUX14_6", - "CLK_HROW_CK_GCLK_IN_TEST19", - "CLK_HROW_SW4A1_1", - "CLK_HROW_IMUX12_1", - "CLK_HROW_WW4A1_5", - "CLK_HROW_IMUX38_3", - "CLK_HROW_CK_GCLK_OUT_TEST17", - "CLK_HROW_LOGIC_OUTS_B23_2", - "CLK_HROW_IMUX40_3", - "CLK_HROW_CK_GCLK_IN_TEST15", - "CLK_HROW_CK_GCLK_TEST21", - "CLK_HROW_NW4END2_4", - "CLK_HROW_IMUX10_0", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN27", - "CLK_HROW_LOGIC_OUTS_B17_4", - "CLK_HROW_WW4END2_7", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SE2A0_5", - "CLK_HROW_IMUX9_7", - "CLK_HROW_LH2_5", - "CLK_HROW_SW2A1_3", - "CLK_HROW_FAN3_2", - "CLK_HROW_IMUX38_5", - "CLK_HROW_LOGIC_OUTS_B4_0", - "CLK_HROW_EE4BEG0_6", - "CLK_HROW_WW2END1_4", - "CLK_HROW_IMUX23_7", - "CLK_HROW_WW4B2_6", - "CLK_HROW_IMUX40_6", - "CLK_HROW_WL1END0_4", - "CLK_HROW_WW4A3_7", - "CLK_HROW_IMUX34_4", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_SW4END2_5", - "CLK_HROW_WW2A0_2", - "CLK_HROW_CE_INT_TOP0", - "CLK_HROW_EE4B3_5", - "CLK_HROW_FAN7_6", - "CLK_HROW_SW4A2_2", - "CLK_HROW_WW4B2_5", - "CLK_HROW_BLOCK_OUTS_B1_4", - "CLK_HROW_IMUX12_2", - "CLK_HROW_LOGIC_OUTS_B8_0", - "CLK_HROW_IMUX45_0", - "CLK_HROW_SE4C2_4", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN24", - "CLK_HROW_NE2A1_0", - "CLK_HROW_BUFHCE_CE_R3", - "CLK_HROW_IMUX44_2", - "CLK_HROW_CK_GCLK_TEST7", - "CLK_HROW_R_CK_GCLK23", - "CLK_HROW_WW4END2_4", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_LH9_6", - "CLK_HROW_CK_GCLK_TEST_OUT10", - "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "CLK_HROW_CK_GCLK_TEST_IN11", - "CLK_HROW_IMUX38_0", - "CLK_HROW_LH6_2", - "CLK_HROW_IMUX8_4", - "CLK_HROW_IMUX16_5", - "CLK_HROW_LH4_0", - "CLK_HROW_WW4C0_4", - "CLK_HROW_CK_BUFHCLK_L7", - "CLK_HROW_EE4A0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_R_CK_GCLK20", - "CLK_HROW_LOGIC_OUTS_B22_7", - "CLK_HROW_CK_IN_L4", - "CLK_HROW_SW4END3_4", - "CLK_HROW_CK_GCLK_OUT_TEST6", - "CLK_HROW_IMUX42_0", - "CLK_HROW_WR1END0_4", - "CLK_HROW_SE2A1_4", - "CLK_HROW_WW4END2_6", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NW4END2_7", - "CLK_HROW_CK_GCLK_TEST_IN14", - "CLK_HROW_NE4C0_0", - "CLK_HROW_CK_GCLK_TEST29", - "CLK_HROW_IMUX46_6", - "CLK_HROW_LOGIC_OUTS_B18_0", - "CLK_HROW_BYP6_4", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW2A1_2", - "CLK_HROW_SW2A0_5", - "CLK_HROW_WW4B3_5", - "CLK_HROW_LOGIC_OUTS_B2_7", - "CLK_HROW_EE4C1_0", - "CLK_HROW_IMUX33_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_IMUX7_6", - "CLK_HROW_CK_MUX_OUT_L2", - "CLK_HROW_IMUX35_1", - "CLK_HROW_WW4A3_4", - "CLK_HROW_IMUX21_3", - "CLK_HROW_NW4END2_5", - "CLK_HROW_CK_MUX_OUT_R3", - "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "CLK_HROW_EE4A0_6", - "CLK_HROW_CK_GCLK_TEST_IN26", - "CLK_HROW_SE2A3_0", - "CLK_HROW_EE4A2_5", - "CLK_HROW_LOGIC_OUTS_B21_1", - "CLK_HROW_IMUX14_3", - "CLK_HROW_CE_INT_TOP1", - "CLK_HROW_IMUX1_1", - "CLK_HROW_CE_INT_BOT9", - "CLK_HROW_EE4B0_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_NW2A1_6", - "CLK_HROW_EE4C1_6", - "CLK_HROW_CTRL0_5", - "CLK_HROW_EE2A1_4", - "CLK_HROW_WW2A3_2", - "CLK_HROW_EE4BEG1_7", - "CLK_HROW_EE4A0_4", - "CLK_HROW_SE4C3_5", - "CLK_HROW_MONITOR_N_6", - "CLK_HROW_IMUX39_5", - "CLK_HROW_IMUX46_2", - "CLK_HROW_IMUX13_4", - "CLK_HROW_LOGIC_OUTS_B6_2", - "CLK_HROW_WW4A2_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_FAN6_4", - "CLK_HROW_IMUX30_4", - "CLK_HROW_SE4C3_2", - "CLK_HROW_CK_GCLK_OUT_TEST15", - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_CK_HCLK_OUT_R4", - "CLK_HROW_NE4C1_5", - "CLK_HROW_IMUX47_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_WW4A3_2", - "CLK_HROW_CK_MUX_OUT_L11", - "CLK_HROW_LOGIC_OUTS_B19_5", - "CLK_HROW_LOGIC_OUTS_B15_0", - "CLK_HROW_LH11_6", - "CLK_HROW_SE4C0_1", - "CLK_HROW_WW4C0_1", - "CLK_HROW_CLK1_0", - "CLK_HROW_WW2END3_7", - "CLK_HROW_ER1BEG0_6", - "CLK_HROW_CK_GCLK_TEST_OUT24", - "CLK_HROW_NW4END3_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_NW4A1_0", - "CLK_HROW_LOGIC_OUTS_B18_4", - "CLK_HROW_EE4A2_1", - "CLK_HROW_IMUX35_6", - "CLK_HROW_WW4C1_5", - "CLK_HROW_WL1END2_6", - "CLK_HROW_CK_GCLK_TEST15", - "CLK_HROW_LOGIC_OUTS_B5_5", - "CLK_HROW_IMUX15_1", - "CLK_HROW_EE2BEG1_6", - "CLK_HROW_CK_GCLK_OUT_TEST10", - "CLK_HROW_NW4A1_2", - "CLK_HROW_LOGIC_OUTS_B21_5", - "CLK_HROW_LOGIC_OUTS_B10_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN19", - "CLK_HROW_CK_IN_L_TEST_IN", - "CLK_HROW_WW4C2_0", - "CLK_HROW_CK_GCLK_IN_TEST26", - "CLK_HROW_WW2END0_4", - "CLK_HROW_LH7_2", - "CLK_HROW_FAN6_7", - "CLK_HROW_ER1BEG2_4", - "CLK_HROW_NW4A3_7", - "CLK_HROW_CK_IN_L1", - "CLK_HROW_EE4A1_5", - "CLK_HROW_EE4B2_5", - "CLK_HROW_IMUX37_3", - "CLK_HROW_NW2A0_7", - "CLK_HROW_LOGIC_OUTS_B12_7", - "CLK_HROW_CK_GCLK_TEST22", - "CLK_HROW_SW4END2_6", - "CLK_HROW_SW4A2_3", - "CLK_HROW_IMUX23_2", - "CLK_HROW_CK_BUFHCLK_L10", - "CLK_HROW_BYP4_0", - "CLK_HROW_SE2A0_4", - "CLK_HROW_LOGIC_OUTS_B2_3", - "CLK_HROW_WW2A0_1", - "CLK_HROW_EE4B2_4", - "CLK_HROW_IMUX4_3", - "CLK_HROW_CK_GCLK_TEST_OUT27", - "CLK_HROW_IMUX44_4", - "CLK_HROW_EE4BEG0_4", - "CLK_HROW_FAN7_5", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_LOGIC_OUTS_B13_1", - "CLK_HROW_IMUX47_2", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_0", - "CLK_HROW_WW2A1_0", - "CLK_HROW_BUFHCE_CE_L9", - "CLK_HROW_WL1END3_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_CK_GCLK_TEST_OUT23", - "CLK_HROW_IMUX0_4", - "CLK_HROW_NW4A1_4", - "CLK_HROW_SE4BEG1_4", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_WR1END1_4", - "CLK_HROW_SE4C2_6", - "CLK_HROW_LH3_7", - "CLK_HROW_IMUX30_7", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_CK_HCLK_OUT_R9", - "CLK_HROW_WW4END0_6", - "CLK_HROW_WR1END2_7", - "CLK_HROW_FAN6_6", - "CLK_HROW_LOGIC_OUTS_B6_7", - "CLK_HROW_LOGIC_OUTS_B20_2", - "CLK_HROW_WW4C3_0", - "CLK_HROW_NE4BEG1_4", - "CLK_HROW_IMUX20_2", - "CLK_HROW_WL1END2_5", - "CLK_HROW_CTRL1_0", - "CLK_HROW_IMUX41_3", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_NW4END0_7", - "CLK_HROW_NW2A3_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_IMUX1_7", - "CLK_HROW_WR1END1_2", - "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_IMUX4_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_IMUX10_2", - "CLK_HROW_WW2A2_0", - "CLK_HROW_FAN2_6", - "CLK_HROW_CK_GCLK_TEST_OUT15", - "CLK_HROW_IMUX8_3", - "CLK_HROW_IMUX33_4", - "CLK_HROW_NW4END3_7", - "CLK_HROW_CTRL0_2", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE4B0_6", - "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "CLK_HROW_R_CK_GCLK7", - "CLK_HROW_WL1END1_7", - "CLK_HROW_EE2A0_3", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_CE_INT_BOT11", - "CLK_HROW_WW2A2_4", - "CLK_HROW_EE4B0_4", - "CLK_HROW_WW4C0_5", - "CLK_HROW_LOGIC_OUTS_B13_2", - "CLK_HROW_EE2A0_4", - "CLK_HROW_IMUX33_3", - "CLK_HROW_EE2A1_7", - "CLK_HROW_IMUX45_3", - "CLK_HROW_CK_IN_L8", - "CLK_HROW_IMUX5_6", - "CLK_HROW_NW4A3_5", - "CLK_HROW_EE4C1_3", - "CLK_HROW_NE4C2_1", - "CLK_HROW_SW4END0_5", - "CLK_HROW_LOGIC_OUTS_B8_6", - "CLK_HROW_CK_GCLK_TEST_IN16", - "CLK_HROW_R_CK_GCLK11", - "CLK_HROW_BYP0_3", - "CLK_HROW_FAN6_5", - "CLK_HROW_WW4A1_4", - "CLK_HROW_IMUX6_7", - "CLK_HROW_EE2A1_3", - "CLK_HROW_LOGIC_OUTS_B9_1", - "CLK_HROW_CE_INT_BOT8", - "CLK_HROW_IMUX9_4", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_IMUX3_0", - "CLK_HROW_LOGIC_OUTS_B1_4", - "CLK_HROW_IMUX23_1", - "CLK_HROW_BUFHCE_CE_R5", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN21", - "CLK_HROW_IMUX41_5", - "CLK_HROW_EE2A3_0", - "CLK_HROW_IMUX32_1", - "CLK_HROW_CK_GCLK_IN_TEST27", - "CLK_HROW_SE2A2_1", - "CLK_HROW_CK_GCLK_TEST13", - "CLK_HROW_EL1BEG2_7", - "CLK_HROW_EE4C0_4", - "CLK_HROW_EE4A3_5", - "CLK_HROW_LH1_6", - "CLK_HROW_WW4END3_6", - "CLK_HROW_SW2A2_0", - "CLK_HROW_IMUX24_3", - "CLK_HROW_CK_HCLK_OUT_L4", - "CLK_HROW_LOGIC_OUTS_B5_4", - "CLK_HROW_WW2END2_4", - "CLK_HROW_WW2A1_6", - "CLK_HROW_IMUX47_5", - "CLK_HROW_EE4B1_4", - "CLK_HROW_NW4A0_5", - "CLK_HROW_R_CK_GCLK22", - "CLK_HROW_BYP1_2", - "CLK_HROW_BUFHCE_CE_L2", - "CLK_HROW_R_CK_GCLK27", - "CLK_HROW_IMUX24_6", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_IMUX1_0", - "CLK_HROW_R_CK_GCLK16", - "CLK_HROW_LOGIC_OUTS_B0_0", - "CLK_HROW_IMUX17_3", - "CLK_HROW_CK_BUFHCLK_R4", - "CLK_HROW_CK_BUFHCLK_R11", - "CLK_HROW_IMUX43_1", - "CLK_HROW_IMUX12_0", - "CLK_HROW_NW2A3_2", - "CLK_HROW_SW4A3_5", - "CLK_HROW_IMUX33_1", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A3_6", - "CLK_HROW_CK_HCLK_OUT_R3", - "CLK_HROW_CK_GCLK_IN_TEST25", - "CLK_HROW_IMUX16_3", - "CLK_HROW_CK_GCLK_IN_TEST17", - "CLK_HROW_CK_IN_R0", - "CLK_HROW_NW4A3_4", - "CLK_HROW_LH1_7", - "CLK_HROW_IMUX0_2", - "CLK_HROW_WW4A0_1", - "CLK_HROW_IMUX37_6", - "CLK_HROW_WW4A3_5", - "CLK_HROW_CK_GCLK_TEST_OUT26", - "CLK_HROW_FAN5_3", - "CLK_HROW_SW4A2_1", - "CLK_HROW_WW4C2_5", - "CLK_HROW_CK_GCLK_IN_TEST18", - "CLK_HROW_EE4B2_2", - "CLK_HROW_IMUX35_3", - "CLK_HROW_EE4B3_6", - "CLK_HROW_LOGIC_OUTS_B10_6", - "CLK_HROW_R_CK_GCLK26", - "CLK_HROW_IMUX7_0", - "CLK_HROW_R_CK_GCLK10", - "CLK_HROW_CK_MUX_OUT_R10", - "CLK_HROW_LOGIC_OUTS_B11_2", - "CLK_HROW_IMUX36_1", - "CLK_HROW_SE4C0_0", - "CLK_HROW_LOGIC_OUTS_B1_6", - "CLK_HROW_CK_GCLK_TEST3", - "CLK_HROW_WW2END1_0", - "CLK_HROW_LH2_4", - "CLK_HROW_CK_IN_L0", - "CLK_HROW_SE4C2_5", - "CLK_HROW_EE2BEG0_6", - "CLK_HROW_LOGIC_OUTS_B5_3", - "CLK_HROW_WW2END3_5", - "CLK_HROW_BYP3_6", - "CLK_HROW_NE2A0_5", - "CLK_HROW_SE2A0_6", - "CLK_HROW_EE4C3_6", - "CLK_HROW_IMUX43_3", - "CLK_HROW_CK_GCLK_TEST_OUT14", - "CLK_HROW_BLOCK_OUTS_B2_6", - "CLK_HROW_BUFHCE_CE_R4", - "CLK_HROW_WW2A3_6", - "CLK_HROW_IMUX43_5", - "CLK_HROW_IMUX39_7", - "CLK_HROW_NW4END0_3", - "CLK_HROW_SE4C0_2", - "CLK_HROW_LOGIC_OUTS_B11_6", - "CLK_HROW_NW2A2_5", - "CLK_HROW_WW2END0_3", - "CLK_HROW_IMUX26_6", - "CLK_HROW_WR1END2_1", - "CLK_HROW_IMUX19_5", - "CLK_HROW_LOGIC_OUTS_B10_1", - "CLK_HROW_WL1END0_5", - "CLK_HROW_IMUX16_1", - "CLK_HROW_IMUX36_5", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_WW4A0_2", - "CLK_HROW_IMUX28_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_LH10_4", - "CLK_HROW_EE4B0_0", - "CLK_HROW_CK_HCLK_OUT_L10", - "CLK_HROW_LOGIC_OUTS_B5_6", - "CLK_HROW_NE2A3_7", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_WW4END1_4", - "CLK_HROW_IMUX17_5", - "CLK_HROW_LH12_0", - "CLK_HROW_CK_BUFRCLK_L3", - "CLK_HROW_FAN2_4", - "CLK_HROW_CK_BUFHCLK_R7", - "CLK_HROW_NW2A3_5", - "CLK_HROW_WL1END3_0", - "CLK_HROW_IMUX45_6", - "CLK_HROW_WW4A3_3", - "CLK_HROW_CK_MUX_OUT_R9", - "CLK_HROW_LOGIC_OUTS_B8_5", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_WR1END1_5", - "CLK_HROW_BYP7_5", - "CLK_HROW_WR1END2_5", - "CLK_HROW_R_CK_GCLK24", - "CLK_HROW_IMUX8_5", - "CLK_HROW_NW4A2_0", - "CLK_HROW_SW2A1_6", - "CLK_HROW_CK_GCLK_IN_TEST23", - "CLK_HROW_SW4END0_0", - "CLK_HROW_LH2_0", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN23", - "CLK_HROW_CK_IN_L6", - "CLK_HROW_NE4BEG2_6", - "CLK_HROW_CK_HCLK_OUT_R10", - "CLK_HROW_EE2BEG1_5", - "CLK_HROW_NW4A2_7", - "CLK_HROW_IMUX1_2", - "CLK_HROW_IMUX15_6", - "CLK_HROW_SE4C3_1", - "CLK_HROW_CK_HCLK_OUT_R7", - "CLK_HROW_SE4C0_4", - "CLK_HROW_FAN1_0" - ], - "sites": [ - { - "prefix": "BUFHCE", - "y_coord": 0, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L0", - "O": "CLK_HROW_CK_HCLK_OUT_L0", - "CE": "CLK_HROW_BUFHCE_CE_L0" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "BUFHCE", - "y_coord": 1, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L1", - "O": "CLK_HROW_CK_HCLK_OUT_L1", - "CE": "CLK_HROW_BUFHCE_CE_L1" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "BUFHCE", - "y_coord": 2, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L2", - "O": "CLK_HROW_CK_HCLK_OUT_L2", - "CE": "CLK_HROW_BUFHCE_CE_L2" - }, - "x_coord": 0, - "name": "X0Y2" - }, - { - "prefix": "BUFHCE", - "y_coord": 3, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L3", - "O": "CLK_HROW_CK_HCLK_OUT_L3", - "CE": "CLK_HROW_BUFHCE_CE_L3" - }, - "x_coord": 0, - "name": "X0Y3" - }, - { - "prefix": "BUFHCE", - "y_coord": 4, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L4", - "O": "CLK_HROW_CK_HCLK_OUT_L4", - "CE": "CLK_HROW_BUFHCE_CE_L4" - }, - "x_coord": 0, - "name": "X0Y4" - }, - { - "prefix": "BUFHCE", - "y_coord": 5, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L5", - "O": "CLK_HROW_CK_HCLK_OUT_L5", - "CE": "CLK_HROW_BUFHCE_CE_L5" - }, - "x_coord": 0, - "name": "X0Y5" - }, - { - "prefix": "BUFHCE", - "y_coord": 6, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L6", - "O": "CLK_HROW_CK_HCLK_OUT_L6", - "CE": "CLK_HROW_BUFHCE_CE_L6" - }, - "x_coord": 0, - "name": "X0Y6" - }, - { - "prefix": "BUFHCE", - "y_coord": 7, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L7", - "O": "CLK_HROW_CK_HCLK_OUT_L7", - "CE": "CLK_HROW_BUFHCE_CE_L7" - }, - "x_coord": 0, - "name": "X0Y7" - }, - { - "prefix": "BUFHCE", - "y_coord": 8, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L8", - "O": "CLK_HROW_CK_HCLK_OUT_L8", - "CE": "CLK_HROW_BUFHCE_CE_L8" - }, - "x_coord": 0, - "name": "X0Y8" - }, - { - "prefix": "BUFHCE", - "y_coord": 9, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L9", - "O": "CLK_HROW_CK_HCLK_OUT_L9", - "CE": "CLK_HROW_BUFHCE_CE_L9" - }, - "x_coord": 0, - "name": "X0Y9" - }, - { - "prefix": "BUFHCE", - "y_coord": 10, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L10", - "O": "CLK_HROW_CK_HCLK_OUT_L10", - "CE": "CLK_HROW_BUFHCE_CE_L10" - }, - "x_coord": 0, - "name": "X0Y10" - }, - { - "prefix": "BUFHCE", - "y_coord": 11, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L11", - "O": "CLK_HROW_CK_HCLK_OUT_L11", - "CE": "CLK_HROW_BUFHCE_CE_L11" - }, - "x_coord": 0, - "name": "X0Y11" - }, - { - "prefix": "BUFHCE", - "y_coord": 11, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R11", - "O": "CLK_HROW_CK_HCLK_OUT_R11", - "CE": "CLK_HROW_BUFHCE_CE_R11" - }, - "x_coord": 1, - "name": "X1Y11" - }, - { - "prefix": "BUFHCE", - "y_coord": 10, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R10", - "O": "CLK_HROW_CK_HCLK_OUT_R10", - "CE": "CLK_HROW_BUFHCE_CE_R10" - }, - "x_coord": 1, - "name": "X1Y10" - }, - { - "prefix": "BUFHCE", - "y_coord": 9, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R9", - "O": "CLK_HROW_CK_HCLK_OUT_R9", - "CE": "CLK_HROW_BUFHCE_CE_R9" - }, - "x_coord": 1, - "name": "X1Y9" - }, - { - "prefix": "BUFHCE", - "y_coord": 8, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R8", - "O": "CLK_HROW_CK_HCLK_OUT_R8", - "CE": "CLK_HROW_BUFHCE_CE_R8" - }, - "x_coord": 1, - "name": "X1Y8" - }, - { - "prefix": "BUFHCE", - "y_coord": 7, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R7", - "O": "CLK_HROW_CK_HCLK_OUT_R7", - "CE": "CLK_HROW_BUFHCE_CE_R7" - }, - "x_coord": 1, - "name": "X1Y7" - }, - { - "prefix": "BUFHCE", - "y_coord": 6, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R6", - "O": "CLK_HROW_CK_HCLK_OUT_R6", - "CE": "CLK_HROW_BUFHCE_CE_R6" - }, - "x_coord": 1, - "name": "X1Y6" - }, - { - "prefix": "BUFHCE", - "y_coord": 5, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R5", - "O": "CLK_HROW_CK_HCLK_OUT_R5", - "CE": "CLK_HROW_BUFHCE_CE_R5" - }, - "x_coord": 1, - "name": "X1Y5" - }, - { - "prefix": "BUFHCE", - "y_coord": 4, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R4", - "O": "CLK_HROW_CK_HCLK_OUT_R4", - "CE": "CLK_HROW_BUFHCE_CE_R4" - }, - "x_coord": 1, - "name": "X1Y4" - }, - { - "prefix": "BUFHCE", - "y_coord": 3, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R3", - "O": "CLK_HROW_CK_HCLK_OUT_R3", - "CE": "CLK_HROW_BUFHCE_CE_R3" - }, - "x_coord": 1, - "name": "X1Y3" - }, - { - "prefix": "BUFHCE", - "y_coord": 2, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R2", - "O": "CLK_HROW_CK_HCLK_OUT_R2", - "CE": "CLK_HROW_BUFHCE_CE_R2" - }, - "x_coord": 1, - "name": "X1Y2" - }, - { - "prefix": "BUFHCE", - "y_coord": 1, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R1", - "O": "CLK_HROW_CK_HCLK_OUT_R1", - "CE": "CLK_HROW_BUFHCE_CE_R1" - }, - "x_coord": 1, - "name": "X1Y1" - }, - { - "prefix": "BUFHCE", - "y_coord": 0, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R0", - "O": "CLK_HROW_CK_HCLK_OUT_R0", - "CE": "CLK_HROW_BUFHCE_CE_R0" - }, - "x_coord": 1, - "name": "X1Y0" - } - ], "pips": { - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "src_wire": "CLK_HROW_CK_IN_R9", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN22->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN23->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT1", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX1_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN28->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT4", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX4_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP7", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX7_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN27->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT0", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX0_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT6", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX6_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN29->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_INT_1_0", - "is_directional": "1", - "src_wire": "CLK_HROW_CLK0_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN15->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP4", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX4_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L0", "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_INT_1_1", - "is_directional": "1", - "src_wire": "CLK_HROW_CLK1_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP6", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX6_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN20->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP5", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX5_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L_TEST_IN", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R_TEST_IN", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN31->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP0", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX0_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN16->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP9", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX9_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT3", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX3_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN30->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_INT_0_0", - "is_directional": "1", - "src_wire": "CLK_HROW_CLK0_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_INT_0_1", - "is_directional": "1", - "src_wire": "CLK_HROW_CLK1_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT10", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX10_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT5", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX5_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN17->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP1", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX1_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN26->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN25->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN14->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP3", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX3_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT2", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX2_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT11", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX11_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT8", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX8_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN18->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP11", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX11_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN24->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN24", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP10", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX10_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT7", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX7_3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN19->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", + "src_wire": "CLK_HROW_R_CK_GCLK18", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", + "src_wire": "CLK_HROW_R_CK_GCLK10", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "src_wire": "CLK_HROW_CK_INT_1_1", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "src_wire": "CLK_HROW_CK_IN_L3", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L8", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "is_directional": "1", "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "src_wire": "CLK_HROW_CK_IN_R13", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "src_wire": "CLK_HROW_CK_IN_R3", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "is_directional": "1", "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "src_wire": "CLK_HROW_CK_IN_L9", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" }, - "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN21->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN21", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "src_wire": "CLK_HROW_R_CK_GCLK31", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "src_wire": "CLK_HROW_CK_IN_R7", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "src_wire": "CLK_HROW_R_CK_GCLK26", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "src_wire": "CLK_HROW_R_CK_GCLK25", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", + "src_wire": "CLK_HROW_CK_IN_R10", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", + "src_wire": "CLK_HROW_R_CK_GCLK30", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "src_wire": "CLK_HROW_CK_IN_L3", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R5", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R5" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "src_wire": "CLK_HROW_R_CK_GCLK8", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", + "src_wire": "CLK_HROW_R_CK_GCLK6", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP2", + "src_wire": "CLK_HROW_CK_IN_L13", "is_directional": "1", - "src_wire": "CLK_HROW_IMUX2_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", + "src_wire": "CLK_HROW_CK_IN_L9", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "src_wire": "CLK_HROW_R_CK_GCLK27", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", + "src_wire": "CLK_HROW_CK_IN_L6", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP8", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX8_4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { + "CLK_HROW_BOT_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", + "src_wire": "CLK_HROW_IMUX0_3", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT0" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", + "src_wire": "CLK_HROW_CK_IN_R1", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "src_wire": "CLK_HROW_CK_IN_R7", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "src_wire": "CLK_HROW_R_CK_GCLK4", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", + "src_wire": "CLK_HROW_R_CK_GCLK24", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L7", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L7" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27", + "src_wire": "CLK_HROW_CK_IN_R10", "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14", + "src_wire": "CLK_HROW_CK_IN_L6", "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT", + "src_wire": "CLK_HROW_R_CK_GCLK12", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN5", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R1", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R1" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" }, - "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_pseudo": "1" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN23->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX11_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT9", - "is_directional": "1", "src_wire": "CLK_HROW_IMUX9_3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN14->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN27->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN22->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN17->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN18->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN16->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L_TEST_IN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN31->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN20->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN28->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CLK0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_1_0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN15->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN19->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CLK0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_0_0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CLK1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_1_1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN21->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX10_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN24->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN29->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN25->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CLK1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_0_1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", - "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "is_directional": "1", "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN30->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN26->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT1" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R_TEST_IN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_BOT_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP1" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" } }, - "tile_type": "CLK_HROW_BOT_R" + "wires": [ + "CLK_HROW_BOT_R_CK_BUFG_CASCIN2", + "CLK_HROW_IMUX32_2", + "CLK_HROW_BUFHCE_CE_L7", + "CLK_HROW_CK_GCLK_TEST_IN19", + "CLK_HROW_CK_INT_1_0", + "CLK_HROW_SW4END2_4", + "CLK_HROW_BYP4_0", + "CLK_HROW_IMUX8_1", + "CLK_HROW_WW4END1_4", + "CLK_HROW_FAN6_6", + "CLK_HROW_IMUX46_5", + "CLK_HROW_CK_GCLK_TEST_IN7", + "CLK_HROW_IMUX10_7", + "CLK_HROW_IMUX13_6", + "CLK_HROW_EL1BEG0_0", + "CLK_HROW_CK_GCLK_TEST6", + "CLK_HROW_SW2A1_2", + "CLK_HROW_CK_HCLK_OUT_R10", + "CLK_HROW_NW2A3_1", + "CLK_HROW_WW4A1_4", + "CLK_HROW_EE4C2_6", + "CLK_HROW_EE4A0_7", + "CLK_HROW_LOGIC_OUTS_B22_3", + "CLK_HROW_EE2BEG2_3", + "CLK_HROW_LH1_0", + "CLK_HROW_WW4C2_0", + "CLK_HROW_LOGIC_OUTS_B9_3", + "CLK_HROW_WR1END2_6", + "CLK_HROW_BYP7_2", + "CLK_HROW_CLK1_3", + "CLK_HROW_CK_GCLK_TEST_IN0", + "CLK_HROW_CK_GCLK_TEST_IN12", + "CLK_HROW_EE2A3_1", + "CLK_HROW_EE2A2_4", + "CLK_HROW_CE_INT_BOT3", + "CLK_HROW_SW4END3_4", + "CLK_HROW_EE4C0_5", + "CLK_HROW_IMUX43_0", + "CLK_HROW_SE2A0_1", + "CLK_HROW_IMUX24_4", + "CLK_HROW_WW4C2_2", + "CLK_HROW_LOGIC_OUTS_B7_2", + "CLK_HROW_CK_IN_L11", + "CLK_HROW_SE4C0_1", + "CLK_HROW_SW4A1_1", + "CLK_HROW_LH8_4", + "CLK_HROW_IMUX12_0", + "CLK_HROW_SW4A1_7", + "CLK_HROW_LOGIC_OUTS_B17_2", + "CLK_HROW_SE4C3_7", + "CLK_HROW_IMUX33_5", + "CLK_HROW_BYP5_1", + "CLK_HROW_IMUX19_6", + "CLK_HROW_WW4C3_2", + "CLK_HROW_FAN6_5", + "CLK_HROW_NW2A1_7", + "CLK_HROW_IMUX28_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCO23", + "CLK_HROW_BOT_R_CK_BUFG_CASCO29", + "CLK_HROW_IMUX20_3", + "CLK_HROW_IMUX2_7", + "CLK_HROW_CK_HCLK_OUT_L0", + "CLK_HROW_LH5_5", + "CLK_HROW_WR1END3_2", + "CLK_HROW_BYP3_4", + "CLK_HROW_IMUX33_3", + "CLK_HROW_CK_MUX_OUT_L11", + "CLK_HROW_WW2END2_0", + "CLK_HROW_FAN4_6", + "CLK_HROW_R_CK_GCLK15", + "CLK_HROW_SW2A0_5", + "CLK_HROW_CK_GCLK_IN_TEST6", + "CLK_HROW_BYP7_5", + "CLK_HROW_IMUX28_7", + "CLK_HROW_NW4A3_0", + "CLK_HROW_EE2BEG2_6", + "CLK_HROW_CK_GCLK_TEST7", + "CLK_HROW_IMUX37_4", + "CLK_HROW_IMUX45_7", + "CLK_HROW_EE4A0_1", + "CLK_HROW_WW4END3_5", + "CLK_HROW_FAN5_6", + "CLK_HROW_EE2A0_6", + "CLK_HROW_IMUX0_4", + "CLK_HROW_LOGIC_OUTS_B1_4", + "CLK_HROW_CK_BUFRCLK_R0", + "CLK_HROW_IMUX42_2", + "CLK_HROW_WW4END3_0", + "CLK_HROW_EL1BEG1_6", + "CLK_HROW_LOGIC_OUTS_B20_3", + "CLK_HROW_IMUX32_7", + "CLK_HROW_CK_GCLK_TEST_OUT1", + "CLK_HROW_LOGIC_OUTS_B0_6", + "CLK_HROW_CK_GCLK_OUT_TEST28", + "CLK_HROW_CK_GCLK_TEST_OUT0", + "CLK_HROW_ER1BEG0_6", + "CLK_HROW_IMUX11_7", + "CLK_HROW_BYP5_0", + "CLK_HROW_CK_BUFHCLK_L2", + "CLK_HROW_LOGIC_OUTS_B6_6", + "CLK_HROW_CK_GCLK_OUT_TEST29", + "CLK_HROW_FAN7_5", + "CLK_HROW_R_CK_GCLK12", + "CLK_HROW_ER1BEG3_0", + "CLK_HROW_EE4B1_5", + "CLK_HROW_SW2A0_7", + "CLK_HROW_NW4A0_3", + "CLK_HROW_IMUX15_0", + "CLK_HROW_EE2A3_4", + "CLK_HROW_SW2A3_6", + "CLK_HROW_LOGIC_OUTS_B1_6", + "CLK_HROW_LH10_2", + "CLK_HROW_IMUX44_4", + "CLK_HROW_NE4BEG2_5", + "CLK_HROW_EE4A1_7", + "CLK_HROW_IMUX11_1", + "CLK_HROW_IMUX32_4", + "CLK_HROW_LOGIC_OUTS_B10_7", + "CLK_HROW_IMUX5_0", + "CLK_HROW_IMUX38_7", + "CLK_HROW_SE4BEG0_3", + "CLK_HROW_NE4BEG3_6", + "CLK_HROW_IMUX20_6", + "CLK_HROW_IMUX11_2", + "CLK_HROW_IMUX25_0", + "CLK_HROW_LOGIC_OUTS_B23_0", + "CLK_HROW_CK_GCLK_TEST3", + "CLK_HROW_WW4C3_7", + "CLK_HROW_LH6_5", + "CLK_HROW_MONITOR_N_3", + "CLK_HROW_LOGIC_OUTS_B3_4", + "CLK_HROW_CE_INT_BOT10", + "CLK_HROW_SW4END0_5", + "CLK_HROW_EE4C1_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN19", + "CLK_HROW_IMUX32_3", + "CLK_HROW_MONITOR_P_3", + "CLK_HROW_CK_GCLK_IN_TEST30", + "CLK_HROW_LOGIC_OUTS_B13_4", + "CLK_HROW_IMUX31_1", + "CLK_HROW_IMUX5_3", + "CLK_HROW_EL1BEG2_7", + "CLK_HROW_EE4BEG3_2", + "CLK_HROW_LOGIC_OUTS_B8_5", + "CLK_HROW_LOGIC_OUTS_B8_0", + "CLK_HROW_CK_HCLK_OUT_L5", + "CLK_HROW_CK_IN_L3", + "CLK_HROW_NW4END3_2", + "CLK_HROW_EE4BEG3_3", + "CLK_HROW_EE4C3_6", + "CLK_HROW_EL1BEG3_3", + "CLK_HROW_EE4A0_3", + "CLK_HROW_LOGIC_OUTS_B0_4", + "CLK_HROW_CK_IN_L9", + "CLK_HROW_SE4BEG2_7", + "CLK_HROW_FAN0_3", + "CLK_HROW_CK_GCLK_IN_TEST22", + "CLK_HROW_CK_IN_R_OUT_TEST", + "CLK_HROW_BOT_R_CK_BUFG_CASCO1", + "CLK_HROW_BLOCK_OUTS_B2_1", + "CLK_HROW_CK_GCLK_IN_TEST31", + "CLK_HROW_IMUX40_6", + "CLK_HROW_REFCK_EASTCLK0", + "CLK_HROW_IMUX17_2", + "CLK_HROW_IMUX41_4", + "CLK_HROW_CK_MUX_OUT_L10", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN27", + "CLK_HROW_SW4A3_2", + "CLK_HROW_R_CK_GCLK14", + "CLK_HROW_LOGIC_OUTS_B18_0", + "CLK_HROW_LOGIC_OUTS_B11_0", + "CLK_HROW_NE4C3_6", + "CLK_HROW_IMUX3_4", + "CLK_HROW_BYP3_7", + "CLK_HROW_CK_GCLK_IN_TEST21", + "CLK_HROW_SE4BEG2_3", + "CLK_HROW_EE2BEG0_4", + "CLK_HROW_IMUX40_1", + "CLK_HROW_LOGIC_OUTS_B7_1", + "CLK_HROW_LH8_2", + "CLK_HROW_EE2A1_0", + "CLK_HROW_CK_GCLK_IN_TEST13", + "CLK_HROW_LH12_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO15", + "CLK_HROW_NW2A2_1", + "CLK_HROW_CK_GCLK_OUT_TEST24", + "CLK_HROW_NE4C0_3", + "CLK_HROW_BYP7_0", + "CLK_HROW_LOGIC_OUTS_B23_2", + "CLK_HROW_SE2A3_6", + "CLK_HROW_EL1BEG3_2", + "CLK_HROW_LH4_6", + "CLK_HROW_BLOCK_OUTS_B3_5", + "CLK_HROW_SW4END2_2", + "CLK_HROW_WW2A1_7", + "CLK_HROW_CK_MUX_OUT_L9", + "CLK_HROW_BYP2_0", + "CLK_HROW_EE2BEG2_0", + "CLK_HROW_WW2END1_4", + "CLK_HROW_CK_MUX_OUT_L3", + "CLK_HROW_WW4C1_1", + "CLK_HROW_LH3_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN22", + "CLK_HROW_IMUX20_1", + "CLK_HROW_LH1_4", + "CLK_HROW_NE4BEG2_7", + "CLK_HROW_LOGIC_OUTS_B20_5", + "CLK_HROW_SE2A0_5", + "CLK_HROW_FAN1_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCO18", + "CLK_HROW_IMUX43_7", + "CLK_HROW_FAN7_7", + "CLK_HROW_LH10_3", + "CLK_HROW_LOGIC_OUTS_B23_7", + "CLK_HROW_NW4END0_5", + "CLK_HROW_WR1END3_5", + "CLK_HROW_MONITOR_P_5", + "CLK_HROW_BLOCK_OUTS_B2_2", + "CLK_HROW_FAN5_7", + "CLK_HROW_IMUX38_4", + "CLK_HROW_R_CK_GCLK2", + "CLK_HROW_LOGIC_OUTS_B23_6", + "CLK_HROW_IMUX26_5", + "CLK_HROW_CK_GCLK_OUT_TEST3", + "CLK_HROW_EE2BEG0_2", + "CLK_HROW_LH2_2", + "CLK_HROW_SW4A2_5", + "CLK_HROW_IMUX11_5", + "CLK_HROW_EE4BEG0_4", + "CLK_HROW_LOGIC_OUTS_B6_5", + "CLK_HROW_CLK1_6", + "CLK_HROW_BUFHCE_CE_L9", + "CLK_HROW_IMUX29_6", + "CLK_HROW_CK_HCLK_OUT_R8", + "CLK_HROW_NE4C3_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN6", + "CLK_HROW_CK_HCLK_OUT_L9", + "CLK_HROW_CK_GCLK_TEST_OUT28", + "CLK_HROW_SE4BEG1_2", + "CLK_HROW_LOGIC_OUTS_B15_5", + "CLK_HROW_WW4C1_2", + "CLK_HROW_ER1BEG3_3", + "CLK_HROW_NE2A2_1", + "CLK_HROW_WW2A2_5", + "CLK_HROW_EE2BEG3_4", + "CLK_HROW_CK_GCLK_TEST_IN18", + "CLK_HROW_LOGIC_OUTS_B14_0", + "CLK_HROW_NW2A2_4", + "CLK_HROW_NW4A0_5", + "CLK_HROW_BLOCK_OUTS_B3_4", + "CLK_HROW_WW2A3_2", + "CLK_HROW_EE4A3_5", + "CLK_HROW_NE4C1_7", + "CLK_HROW_SE4C0_3", + "CLK_HROW_WW4C1_5", + "CLK_HROW_WW4B1_1", + "CLK_HROW_WR1END1_6", + "CLK_HROW_LOGIC_OUTS_B0_2", + "CLK_HROW_CK_MUX_OUT_L0", + "CLK_HROW_CE_INT_BOT8", + "CLK_HROW_NW4END2_7", + "CLK_HROW_NE4C1_6", + "CLK_HROW_EE4BEG3_4", + "CLK_HROW_IMUX38_5", + "CLK_HROW_NW4A3_1", + "CLK_HROW_LOGIC_OUTS_B9_5", + "CLK_HROW_CK_GCLK_TEST17", + "CLK_HROW_WW2END1_0", + "CLK_HROW_NW4END2_3", + "CLK_HROW_NE2A2_0", + "CLK_HROW_WW2END2_6", + "CLK_HROW_IMUX30_3", + "CLK_HROW_CK_GCLK_OUT_TEST9", + "CLK_HROW_IMUX42_3", + "CLK_HROW_BLOCK_OUTS_B3_0", + "CLK_HROW_WW4B3_7", + "CLK_HROW_SE2A1_2", + "CLK_HROW_CK_GCLK_TEST_IN29", + "CLK_HROW_SW2A1_5", + "CLK_HROW_CK_IN_R3", + "CLK_HROW_CE_INT_TOP7", + "CLK_HROW_CLK0_1", + "CLK_HROW_LH11_6", + "CLK_HROW_SE4BEG0_4", + "CLK_HROW_CK_GCLK_TEST_IN23", + "CLK_HROW_FAN3_4", + "CLK_HROW_IMUX27_2", + "CLK_HROW_NW4A3_4", + "CLK_HROW_SE4BEG3_3", + "CLK_HROW_CK_GCLK_IN_TEST17", + "CLK_HROW_R_CK_GCLK13", + "CLK_HROW_LOGIC_OUTS_B9_2", + "CLK_HROW_SE2A2_6", + "CLK_HROW_EE4BEG1_4", + "CLK_HROW_NW4A0_1", + "CLK_HROW_NE4BEG0_5", + "CLK_HROW_IMUX2_2", + "CLK_HROW_EE4B2_0", + "CLK_HROW_CK_IN_R4", + "CLK_HROW_WW4C0_4", + "CLK_HROW_EE4BEG0_2", + "CLK_HROW_FAN5_1", + "CLK_HROW_FAN2_5", + "CLK_HROW_CE_INT_BOT5", + "CLK_HROW_EE2A0_1", + "CLK_HROW_R_CK_GCLK1", + "CLK_HROW_WW4A1_0", + "CLK_HROW_WW2A2_2", + "CLK_HROW_LH2_0", + "CLK_HROW_LOGIC_OUTS_B19_5", + "CLK_HROW_CK_BUFHCLK_R4", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN30", + "CLK_HROW_EE4C0_4", + "CLK_HROW_CK_GCLK_TEST11", + "CLK_HROW_NW2A2_3", + "CLK_HROW_CTRL0_7", + "CLK_HROW_LOGIC_OUTS_B20_4", + "CLK_HROW_LOGIC_OUTS_B21_1", + "CLK_HROW_IMUX39_5", + "CLK_HROW_IMUX8_0", + "CLK_HROW_BLOCK_OUTS_B0_5", + "CLK_HROW_FAN0_1", + "CLK_HROW_SE4BEG3_7", + "CLK_HROW_IMUX30_1", + "CLK_HROW_LOGIC_OUTS_B16_5", + "CLK_HROW_SE2A1_3", + "CLK_HROW_WW4END0_1", + "CLK_HROW_LH5_2", + "CLK_HROW_WW2END3_3", + "CLK_HROW_WW4B1_5", + "CLK_HROW_IMUX32_1", + "CLK_HROW_CK_IN_L2", + "CLK_HROW_CK_GCLK_IN_TEST10", + "CLK_HROW_LOGIC_OUTS_B4_0", + "CLK_HROW_LOGIC_OUTS_B16_2", + "CLK_HROW_WL1END3_2", + "CLK_HROW_SE4BEG3_1", + "CLK_HROW_WW4C3_5", + "CLK_HROW_CK_GCLK_IN_TEST15", + "CLK_HROW_IMUX25_2", + "CLK_HROW_NW4A1_3", + "CLK_HROW_SE2A0_7", + "CLK_HROW_LH9_6", + "CLK_HROW_LOGIC_OUTS_B1_0", + "CLK_HROW_IMUX36_2", + "CLK_HROW_BYP2_1", + "CLK_HROW_EL1BEG0_7", + "CLK_HROW_IMUX47_1", + "CLK_HROW_BLOCK_OUTS_B1_6", + "CLK_HROW_WL1END2_1", + "CLK_HROW_WW2END2_2", + "CLK_HROW_NE4C2_4", + "CLK_HROW_EE4B2_5", + "CLK_HROW_WR1END1_7", + "CLK_HROW_IMUX33_0", + "CLK_HROW_WL1END3_6", + "CLK_HROW_WW4B1_3", + "CLK_HROW_CK_GCLK_TEST_OUT4", + "CLK_HROW_CK_BUFHCLK_L4", + "CLK_HROW_CK_MUX_OUT_L4", + "CLK_HROW_LOGIC_OUTS_B20_0", + "CLK_HROW_IMUX8_7", + "CLK_HROW_WR1END1_4", + "CLK_HROW_SE2A1_1", + "CLK_HROW_NE4BEG0_4", + "CLK_HROW_WW4C0_3", + "CLK_HROW_EL1BEG0_3", + "CLK_HROW_WW2END1_6", + "CLK_HROW_CK_HCLK_OUT_R9", + "CLK_HROW_EE4A0_4", + "CLK_HROW_LOGIC_OUTS_B16_1", + "CLK_HROW_EE2A3_5", + "CLK_HROW_IMUX12_2", + "CLK_HROW_EE2A3_0", + "CLK_HROW_WW4END1_7", + "CLK_HROW_WW4B2_6", + "CLK_HROW_EE4BEG3_7", + "CLK_HROW_R_CK_GCLK26", + "CLK_HROW_LOGIC_OUTS_B3_3", + "CLK_HROW_IMUX23_7", + "CLK_HROW_CK_GCLK_OUT_TEST5", + "CLK_HROW_SE4C0_4", + "CLK_HROW_SE2A0_6", + "CLK_HROW_EE4A1_5", + "CLK_HROW_CK_GCLK_IN_TEST0", + "CLK_HROW_EE4B3_6", + "CLK_HROW_CK_GCLK_TEST_OUT19", + "CLK_HROW_IMUX3_0", + "CLK_HROW_LH4_2", + "CLK_HROW_IMUX6_2", + "CLK_HROW_IMUX44_2", + "CLK_HROW_WR1END2_3", + "CLK_HROW_CK_MUX_OUT_L7", + "CLK_HROW_WW4B0_0", + "CLK_HROW_CK_GCLK_OUT_TEST13", + "CLK_HROW_LOGIC_OUTS_B9_4", + "CLK_HROW_SW4A1_0", + "CLK_HROW_BYP3_1", + "CLK_HROW_NE2A1_6", + "CLK_HROW_BLOCK_OUTS_B3_2", + "CLK_HROW_EL1BEG2_3", + "CLK_HROW_IMUX5_7", + "CLK_HROW_WL1END0_5", + "CLK_HROW_IMUX6_5", + "CLK_HROW_R_CK_GCLK25", + "CLK_HROW_LH12_4", + "CLK_HROW_LH1_3", + "CLK_HROW_FAN1_3", + "CLK_HROW_CK_BUFRCLK_R1", + "CLK_HROW_WW2END2_1", + "CLK_HROW_CK_HCLK_OUT_L1", + "CLK_HROW_LOGIC_OUTS_B2_6", + "CLK_HROW_IMUX31_3", + "CLK_HROW_IMUX3_5", + "CLK_HROW_CK_IN_L4", + "CLK_HROW_WW4C0_5", + "CLK_HROW_CK_GCLK_OUT_TEST11", + "CLK_HROW_EL1BEG2_5", + "CLK_HROW_EE4BEG3_1", + "CLK_HROW_EE4BEG1_5", + "CLK_HROW_WW2A3_4", + "CLK_HROW_EE2BEG1_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO4", + "CLK_HROW_IMUX17_3", + "CLK_HROW_CK_BUFHCLK_L10", + "CLK_HROW_SE2A3_5", + "CLK_HROW_NE2A1_0", + "CLK_HROW_IMUX13_2", + "CLK_HROW_LOGIC_OUTS_B23_3", + "CLK_HROW_WL1END0_7", + "CLK_HROW_EL1BEG0_5", + "CLK_HROW_BUFHCE_CE_L3", + "CLK_HROW_SW4A1_3", + "CLK_HROW_WW2A0_2", + "CLK_HROW_NW4A2_5", + "CLK_HROW_IMUX8_4", + "CLK_HROW_ER1BEG3_4", + "CLK_HROW_LH6_7", + "CLK_HROW_CK_GCLK_IN_TEST11", + "CLK_HROW_NE4C2_5", + "CLK_HROW_R_CK_GCLK8", + "CLK_HROW_BYP7_1", + "CLK_HROW_IMUX19_2", + "CLK_HROW_EE4C0_3", + "CLK_HROW_IMUX6_0", + "CLK_HROW_CLK0_2", + "CLK_HROW_FAN5_4", + "CLK_HROW_EE4C0_1", + "CLK_HROW_IMUX13_0", + "CLK_HROW_EL1BEG1_4", + "CLK_HROW_CTRL0_6", + "CLK_HROW_FAN7_0", + "CLK_HROW_BLOCK_OUTS_B0_7", + "CLK_HROW_EE4A2_1", + "CLK_HROW_EE4BEG1_1", + "CLK_HROW_SE4C3_1", + "CLK_HROW_EE2A1_3", + "CLK_HROW_CE_INT_TOP9", + "CLK_HROW_WW4END2_2", + "CLK_HROW_CK_IN_R9", + "CLK_HROW_IMUX10_3", + "CLK_HROW_SE4C3_4", + "CLK_HROW_WW2A3_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCO24", + "CLK_HROW_IMUX6_1", + "CLK_HROW_BUFHCE_CE_R5", + "CLK_HROW_IMUX2_4", + "CLK_HROW_LOGIC_OUTS_B17_4", + "CLK_HROW_WL1END2_5", + "CLK_HROW_ER1BEG0_5", + "CLK_HROW_IMUX24_7", + "CLK_HROW_CK_GCLK_TEST18", + "CLK_HROW_CK_IN_R10", + "CLK_HROW_CK_IN_L_TEST_IN", + "CLK_HROW_NE4C1_5", + "CLK_HROW_WW4B3_3", + "CLK_HROW_EE4B2_7", + "CLK_HROW_WR1END0_7", + "CLK_HROW_IMUX1_1", + "CLK_HROW_ER1BEG1_5", + "CLK_HROW_EE2A3_2", + "CLK_HROW_LH1_7", + "CLK_HROW_IMUX45_2", + "CLK_HROW_WW2A3_1", + "CLK_HROW_WW4B3_1", + "CLK_HROW_NW4END3_3", + "CLK_HROW_CK_GCLK_OUT_TEST10", + "CLK_HROW_LOGIC_OUTS_B21_7", + "CLK_HROW_LOGIC_OUTS_B11_6", + "CLK_HROW_WW4A0_2", + "CLK_HROW_EE4C0_7", + "CLK_HROW_IMUX26_2", + "CLK_HROW_NE4C1_3", + "CLK_HROW_EE4B2_3", + "CLK_HROW_FAN3_1", + "CLK_HROW_IMUX4_5", + "CLK_HROW_FAN6_7", + "CLK_HROW_NW4END1_2", + "CLK_HROW_WR1END2_2", + "CLK_HROW_WW2A2_4", + "CLK_HROW_LOGIC_OUTS_B16_6", + "CLK_HROW_EE4C0_0", + "CLK_HROW_SE2A0_0", + "CLK_HROW_NE4C1_0", + "CLK_HROW_BYP5_6", + "CLK_HROW_CK_BUFHCLK_R2", + "CLK_HROW_IMUX1_7", + "CLK_HROW_SW4END3_0", + "CLK_HROW_IMUX18_4", + "CLK_HROW_ER1BEG0_4", + "CLK_HROW_CK_GCLK_IN_TEST28", + "CLK_HROW_IMUX35_1", + "CLK_HROW_NW4END1_6", + "CLK_HROW_IMUX36_7", + "CLK_HROW_IMUX33_4", + "CLK_HROW_CK_GCLK_TEST_IN25", + "CLK_HROW_IMUX1_6", + "CLK_HROW_SW4END0_0", + "CLK_HROW_EE4B2_4", + "CLK_HROW_WR1END1_5", + "CLK_HROW_WL1END2_3", + "CLK_HROW_FAN7_1", + "CLK_HROW_EE4BEG2_6", + "CLK_HROW_IMUX17_1", + "CLK_HROW_CK_GCLK_TEST12", + "CLK_HROW_LOGIC_OUTS_B12_0", + "CLK_HROW_IMUX22_2", + "CLK_HROW_WL1END3_5", + "CLK_HROW_LH6_0", + "CLK_HROW_LH7_0", + "CLK_HROW_LOGIC_OUTS_B14_2", + "CLK_HROW_CK_GCLK_TEST_IN10", + "CLK_HROW_SW2A3_7", + "CLK_HROW_EL1BEG3_5", + "CLK_HROW_SW4A3_6", + "CLK_HROW_CK_GCLK_TEST_OUT13", + "CLK_HROW_WW2A0_6", + "CLK_HROW_IMUX25_3", + "CLK_HROW_CK_GCLK_IN_TEST8", + "CLK_HROW_SW2A2_1", + "CLK_HROW_CK_GCLK_IN_TEST19", + "CLK_HROW_EE2BEG0_0", + "CLK_HROW_IMUX1_0", + "CLK_HROW_CK_GCLK_TEST_IN13", + "CLK_HROW_SE4BEG3_6", + "CLK_HROW_BLOCK_OUTS_B0_1", + "CLK_HROW_EE2BEG1_5", + "CLK_HROW_IMUX46_2", + "CLK_HROW_LOGIC_OUTS_B6_3", + "CLK_HROW_WW2A1_3", + "CLK_HROW_SW4A0_5", + "CLK_HROW_IMUX41_6", + "CLK_HROW_LH11_7", + "CLK_HROW_EE4A1_2", + "CLK_HROW_NE4BEG1_2", + "CLK_HROW_CK_GCLK_TEST_IN31", + "CLK_HROW_NW2A2_0", + "CLK_HROW_LOGIC_OUTS_B7_7", + "CLK_HROW_BYP5_4", + "CLK_HROW_EE4C1_7", + "CLK_HROW_CE_INT_TOP1", + "CLK_HROW_IMUX19_5", + "CLK_HROW_R_CK_GCLK9", + "CLK_HROW_CK_IN_L0", + "CLK_HROW_CK_BUFHCLK_L6", + "CLK_HROW_IMUX47_5", + "CLK_HROW_IMUX41_1", + "CLK_HROW_EE2A3_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN14", + "CLK_HROW_SW4END2_1", + "CLK_HROW_FAN0_7", + "CLK_HROW_NW2A2_6", + "CLK_HROW_CK_IN_L_IN_TEST", + "CLK_HROW_BOT_R_CK_BUFG_CASCO11", + "CLK_HROW_LOGIC_OUTS_B23_1", + "CLK_HROW_CK_GCLK_TEST14", + "CLK_HROW_NE4C0_1", + "CLK_HROW_EE4C3_2", + "CLK_HROW_CK_GCLK_OUT_TEST15", + "CLK_HROW_LOGIC_OUTS_B0_5", + "CLK_HROW_EE2A2_1", + "CLK_HROW_EE2BEG0_6", + "CLK_HROW_EE4BEG1_2", + "CLK_HROW_WW4A0_1", + "CLK_HROW_EE4B0_7", + "CLK_HROW_ER1BEG3_2", + "CLK_HROW_BLOCK_OUTS_B0_4", + "CLK_HROW_IMUX4_1", + "CLK_HROW_LH7_7", + "CLK_HROW_BUFHCE_CE_L0", + "CLK_HROW_CK_HCLK_OUT_R1", + "CLK_HROW_CK_GCLK_TEST_IN22", + "CLK_HROW_LOGIC_OUTS_B19_0", + "CLK_HROW_CK_GCLK_OUT_TEST26", + "CLK_HROW_IMUX22_1", + "CLK_HROW_CK_GCLK_OUT_TEST30", + "CLK_HROW_IMUX26_4", + "CLK_HROW_BUFHCE_CE_R4", + "CLK_HROW_LOGIC_OUTS_B9_1", + "CLK_HROW_EE4BEG3_5", + "CLK_HROW_EE4A1_3", + "CLK_HROW_LOGIC_OUTS_B12_4", + "CLK_HROW_LH11_2", + "CLK_HROW_SE4C1_4", + "CLK_HROW_FAN6_4", + "CLK_HROW_CK_GCLK_TEST4", + "CLK_HROW_BOT_R_CK_BUFG_CASCO26", + "CLK_HROW_IMUX16_5", + "CLK_HROW_EE4B1_4", + "CLK_HROW_LOGIC_OUTS_B9_6", + "CLK_HROW_IMUX2_0", + "CLK_HROW_EE4B0_0", + "CLK_HROW_NE4BEG1_5", + "CLK_HROW_FAN6_0", + "CLK_HROW_SE4C0_6", + "CLK_HROW_EE2BEG0_1", + "CLK_HROW_WW4C0_6", + "CLK_HROW_SW4END3_7", + "CLK_HROW_LH10_1", + "CLK_HROW_BYP0_3", + "CLK_HROW_IMUX12_6", + "CLK_HROW_EE4C1_3", + "CLK_HROW_CTRL1_2", + "CLK_HROW_CK_GCLK_TEST24", + "CLK_HROW_CK_IN_L1", + "CLK_HROW_CK_BUFRCLK_L2", + "CLK_HROW_EE2BEG1_6", + "CLK_HROW_IMUX0_2", + "CLK_HROW_LOGIC_OUTS_B11_5", + "CLK_HROW_CK_MUX_OUT_L8", + "CLK_HROW_CE_INT_BOT11", + "CLK_HROW_IMUX3_1", + "CLK_HROW_LH5_3", + "CLK_HROW_IMUX31_0", + "CLK_HROW_R_CK_GCLK21", + "CLK_HROW_BYP3_6", + "CLK_HROW_SW4END2_5", + "CLK_HROW_SW4END3_1", + "CLK_HROW_CK_IN_L8", + "CLK_HROW_NW4A2_6", + "CLK_HROW_SE4BEG0_5", + "CLK_HROW_LH3_0", + "CLK_HROW_BLOCK_OUTS_B1_2", + "CLK_HROW_CK_GCLK_TEST27", + "CLK_HROW_WW2A1_1", + "CLK_HROW_NW4END2_5", + "CLK_HROW_NW2A0_7", + "CLK_HROW_WR1END3_4", + "CLK_HROW_ER1BEG0_7", + "CLK_HROW_EL1BEG3_4", + "CLK_HROW_NW4END3_1", + "CLK_HROW_LOGIC_OUTS_B10_3", + "CLK_HROW_CK_MUX_OUT_R6", + "CLK_HROW_BUFHCE_CE_R1", + "CLK_HROW_LH9_2", + "CLK_HROW_SW4A3_7", + "CLK_HROW_IMUX27_4", + "CLK_HROW_FAN2_1", + "CLK_HROW_CE_INT_TOP8", + "CLK_HROW_IMUX1_5", + "CLK_HROW_LH10_0", + "CLK_HROW_IMUX14_1", + "CLK_HROW_ER1BEG0_1", + "CLK_HROW_EE4C1_5", + "CLK_HROW_EE2BEG3_0", + "CLK_HROW_IMUX2_1", + "CLK_HROW_CK_IN_R13", + "CLK_HROW_SE4C0_7", + "CLK_HROW_ER1BEG1_1", + "CLK_HROW_BUFHCE_CE_R0", + "CLK_HROW_MONITOR_P_2", + "CLK_HROW_LH8_7", + "CLK_HROW_WW2A2_3", + "CLK_HROW_IMUX36_3", + "CLK_HROW_LOGIC_OUTS_B4_2", + "CLK_HROW_IMUX0_1", + "CLK_HROW_SE4C1_0", + "CLK_HROW_EE4B3_4", + "CLK_HROW_IMUX42_4", + "CLK_HROW_LOGIC_OUTS_B22_1", + "CLK_HROW_IMUX5_1", + "CLK_HROW_CK_GCLK_TEST_IN8", + "CLK_HROW_CE_INT_BOT0", + "CLK_HROW_LH2_5", + "CLK_HROW_BYP6_4", + "CLK_HROW_NW4END0_2", + "CLK_HROW_WW2END0_2", + "CLK_HROW_CE_INT_TOP4", + "CLK_HROW_EE4B3_5", + "CLK_HROW_SE4C3_6", + "CLK_HROW_EE4BEG0_3", + "CLK_HROW_LH1_2", + "CLK_HROW_LOGIC_OUTS_B15_7", + "CLK_HROW_SW4A0_4", + "CLK_HROW_IMUX10_0", + "CLK_HROW_WW4B0_6", + "CLK_HROW_CE_INT_BOT4", + "CLK_HROW_NE2A0_6", + "CLK_HROW_BYP1_3", + "CLK_HROW_CK_HCLK_OUT_R4", + "CLK_HROW_BUFHCE_CE_L8", + "CLK_HROW_BLOCK_OUTS_B1_1", + "CLK_HROW_LOGIC_OUTS_B9_7", + "CLK_HROW_WW4A2_4", + "CLK_HROW_EL1BEG1_7", + "CLK_HROW_EE4C2_3", + "CLK_HROW_FAN3_5", + "CLK_HROW_LH11_5", + "CLK_HROW_IMUX25_1", + "CLK_HROW_BUFHCE_CE_R8", + "CLK_HROW_LOGIC_OUTS_B5_2", + "CLK_HROW_IMUX24_6", + "CLK_HROW_IMUX23_4", + "CLK_HROW_ER1BEG1_2", + "CLK_HROW_WW4END0_0", + "CLK_HROW_LOGIC_OUTS_B20_6", + "CLK_HROW_FAN4_7", + "CLK_HROW_SW4A3_5", + "CLK_HROW_BYP4_3", + "CLK_HROW_EE4A3_6", + "CLK_HROW_EE4A2_5", + "CLK_HROW_WW2END0_1", + "CLK_HROW_CK_GCLK_TEST19", + "CLK_HROW_CK_IN_L10", + "CLK_HROW_BOT_R_CK_BUFG_CASCO0", + "CLK_HROW_LOGIC_OUTS_B11_3", + "CLK_HROW_EE4A1_0", + "CLK_HROW_EE4B1_7", + "CLK_HROW_EE2A3_7", + "CLK_HROW_IMUX18_5", + "CLK_HROW_IMUX37_7", + "CLK_HROW_IMUX1_2", + "CLK_HROW_CK_BUFRCLK_L0", + "CLK_HROW_WW4C3_3", + "CLK_HROW_CK_MUX_OUT_R1", + "CLK_HROW_LOGIC_OUTS_B19_1", + "CLK_HROW_SE4BEG3_0", + "CLK_HROW_SE4C1_7", + "CLK_HROW_CK_GCLK_TEST_IN2", + "CLK_HROW_WW2END3_5", + "CLK_HROW_NE4BEG1_7", + "CLK_HROW_IMUX35_3", + "CLK_HROW_IMUX4_0", + "CLK_HROW_BYP2_6", + "CLK_HROW_REFCK_WESTCLK1", + "CLK_HROW_IMUX22_0", + "CLK_HROW_NW4A2_0", + "CLK_HROW_CK_BUFHCLK_R6", + "CLK_HROW_IMUX29_7", + "CLK_HROW_LH12_0", + "CLK_HROW_EE2BEG3_5", + "CLK_HROW_IMUX15_2", + "CLK_HROW_NW2A1_2", + "CLK_HROW_R_CK_GCLK30", + "CLK_HROW_CK_GCLK_TEST23", + "CLK_HROW_NW4A1_7", + "CLK_HROW_WR1END3_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN4", + "CLK_HROW_NW2A1_6", + "CLK_HROW_EE4A3_1", + "CLK_HROW_BYP4_4", + "CLK_HROW_BYP5_2", + "CLK_HROW_IMUX21_0", + "CLK_HROW_EE2A2_7", + "CLK_HROW_IMUX15_4", + "CLK_HROW_LOGIC_OUTS_B1_7", + "CLK_HROW_WR1END0_3", + "CLK_HROW_IMUX38_0", + "CLK_HROW_WW2END2_5", + "CLK_HROW_LH6_2", + "CLK_HROW_EE4BEG0_5", + "CLK_HROW_CK_GCLK_OUT_TEST6", + "CLK_HROW_LOGIC_OUTS_B17_5", + "CLK_HROW_NW4A1_2", + "CLK_HROW_R_CK_GCLK17", + "CLK_HROW_NE4BEG1_6", + "CLK_HROW_LOGIC_OUTS_B0_0", + "CLK_HROW_SE2A2_3", + "CLK_HROW_WW4END1_6", + "CLK_HROW_IMUX38_2", + "CLK_HROW_LOGIC_OUTS_B16_7", + "CLK_HROW_R_CK_GCLK27", + "CLK_HROW_WW2A3_3", + "CLK_HROW_IMUX18_7", + "CLK_HROW_WW4B2_2", + "CLK_HROW_ER1BEG2_5", + "CLK_HROW_IMUX26_0", + "CLK_HROW_NW4A3_5", + "CLK_HROW_LOGIC_OUTS_B2_5", + "CLK_HROW_LOGIC_OUTS_B3_7", + "CLK_HROW_LH2_4", + "CLK_HROW_CK_GCLK_TEST9", + "CLK_HROW_NW4END0_1", + "CLK_HROW_LH8_1", + "CLK_HROW_LOGIC_OUTS_B0_7", + "CLK_HROW_BYP6_3", + "CLK_HROW_LOGIC_OUTS_B19_3", + "CLK_HROW_CK_INT_0_1", + "CLK_HROW_EE4A2_0", + "CLK_HROW_SE2A1_7", + "CLK_HROW_IMUX28_1", + "CLK_HROW_LOGIC_OUTS_B21_0", + "CLK_HROW_IMUX31_4", + "CLK_HROW_EE4BEG1_6", + "CLK_HROW_MONITOR_P_4", + "CLK_HROW_LOGIC_OUTS_B20_2", + "CLK_HROW_CK_GCLK_IN_TEST4", + "CLK_HROW_SW4END3_5", + "CLK_HROW_LH1_5", + "CLK_HROW_NE4C3_0", + "CLK_HROW_LH6_3", + "CLK_HROW_BYP0_2", + "CLK_HROW_SW2A1_6", + "CLK_HROW_FAN2_4", + "CLK_HROW_EE2A0_0", + "CLK_HROW_SW4END0_7", + "CLK_HROW_CE_INT_TOP6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO13", + "CLK_HROW_LOGIC_OUTS_B2_7", + "CLK_HROW_IMUX28_0", + "CLK_HROW_SE4C1_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO10", + "CLK_HROW_LOGIC_OUTS_B15_2", + "CLK_HROW_IMUX36_6", + "CLK_HROW_IMUX24_0", + "CLK_HROW_WW4B2_3", + "CLK_HROW_FAN6_2", + "CLK_HROW_IMUX26_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN9", + "CLK_HROW_IMUX25_4", + "CLK_HROW_IMUX27_5", + "CLK_HROW_SE2A3_7", + "CLK_HROW_IMUX7_7", + "CLK_HROW_LOGIC_OUTS_B7_6", + "CLK_HROW_NW2A0_5", + "CLK_HROW_NE4BEG0_0", + "CLK_HROW_WR1END0_0", + "CLK_HROW_LOGIC_OUTS_B17_1", + "CLK_HROW_WW2END3_1", + "CLK_HROW_IMUX39_1", + "CLK_HROW_LOGIC_OUTS_B14_6", + "CLK_HROW_WL1END1_3", + "CLK_HROW_EE2A2_0", + "CLK_HROW_SW2A2_5", + "CLK_HROW_IMUX28_4", + "CLK_HROW_CK_GCLK_TEST_IN3", + "CLK_HROW_NW4END3_7", + "CLK_HROW_IMUX9_7", + "CLK_HROW_SE4BEG2_2", + "CLK_HROW_WW2A1_4", + "CLK_HROW_IMUX44_1", + "CLK_HROW_EE4B3_0", + "CLK_HROW_IMUX29_2", + "CLK_HROW_BYP2_4", + "CLK_HROW_BYP1_1", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN1", + "CLK_HROW_SW4END1_1", + "CLK_HROW_SE4BEG1_1", + "CLK_HROW_R_CK_GCLK23", + "CLK_HROW_IMUX0_6", + "CLK_HROW_LOGIC_OUTS_B18_5", + "CLK_HROW_R_CK_GCLK3", + "CLK_HROW_CK_GCLK_TEST_OUT26", + "CLK_HROW_CK_GCLK_TEST25", + "CLK_HROW_WL1END2_6", + "CLK_HROW_FAN1_6", + "CLK_HROW_WL1END0_4", + "CLK_HROW_CK_GCLK_TEST20", + "CLK_HROW_WW4B2_0", + "CLK_HROW_WW4B3_2", + "CLK_HROW_R_CK_GCLK16", + "CLK_HROW_WW4A1_6", + "CLK_HROW_WW2END3_7", + "CLK_HROW_SE4C3_5", + "CLK_HROW_ER1BEG0_3", + "CLK_HROW_CK_HCLK_OUT_R7", + "CLK_HROW_FAN6_1", + "CLK_HROW_LH11_3", + "CLK_HROW_IMUX44_7", + "CLK_HROW_CK_HCLK_OUT_L3", + "CLK_HROW_EE4BEG0_1", + "CLK_HROW_CK_MUX_OUT_R11", + "CLK_HROW_IMUX42_1", + "CLK_HROW_BYP0_6", + "CLK_HROW_NE2A3_5", + "CLK_HROW_SW4END0_6", + "CLK_HROW_EE4C3_3", + "CLK_HROW_BLOCK_OUTS_B0_3", + "CLK_HROW_CK_GCLK_TEST_OUT16", + "CLK_HROW_EE2BEG1_0", + "CLK_HROW_LOGIC_OUTS_B7_5", + "CLK_HROW_LOGIC_OUTS_B10_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN5", + "CLK_HROW_NE4BEG1_3", + "CLK_HROW_WW4C3_1", + "CLK_HROW_SW4A3_0", + "CLK_HROW_NW2A0_0", + "CLK_HROW_WW4A3_6", + "CLK_HROW_NE4BEG0_2", + "CLK_HROW_IMUX4_6", + "CLK_HROW_LOGIC_OUTS_B20_1", + "CLK_HROW_ER1BEG2_4", + "CLK_HROW_EE2A1_2", + "CLK_HROW_R_CK_GCLK10", + "CLK_HROW_IMUX35_0", + "CLK_HROW_LOGIC_OUTS_B18_6", + "CLK_HROW_EL1BEG2_2", + "CLK_HROW_IMUX26_1", + "CLK_HROW_FAN5_5", + "CLK_HROW_CK_GCLK_TEST_IN27", + "CLK_HROW_EE4BEG2_3", + "CLK_HROW_WW2END1_1", + "CLK_HROW_LOGIC_OUTS_B19_6", + "CLK_HROW_EE2A0_5", + "CLK_HROW_SW2A1_3", + "CLK_HROW_NE4BEG1_4", + "CLK_HROW_CK_GCLK_TEST_OUT10", + "CLK_HROW_IMUX13_1", + "CLK_HROW_LOGIC_OUTS_B15_1", + "CLK_HROW_LOGIC_OUTS_B12_2", + "CLK_HROW_LH6_4", + "CLK_HROW_CK_HCLK_OUT_L4", + "CLK_HROW_LOGIC_OUTS_B21_5", + "CLK_HROW_NE2A3_0", + "CLK_HROW_WW4A1_3", + "CLK_HROW_CTRL1_5", + "CLK_HROW_LOGIC_OUTS_B13_6", + "CLK_HROW_IMUX41_7", + "CLK_HROW_SE4C2_3", + "CLK_HROW_IMUX36_4", + "CLK_HROW_WR1END3_1", + "CLK_HROW_WW4C1_3", + "CLK_HROW_CK_GCLK_TEST21", + "CLK_HROW_CK_GCLK_TEST_OUT15", + "CLK_HROW_NW2A1_0", + "CLK_HROW_NE4BEG1_0", + "CLK_HROW_EE4C1_1", + "CLK_HROW_CK_GCLK_IN_TEST9", + "CLK_HROW_IMUX34_0", + "CLK_HROW_CE_INT_BOT9", + "CLK_HROW_LOGIC_OUTS_B12_5", + "CLK_HROW_WL1END0_1", + "CLK_HROW_IMUX37_3", + "CLK_HROW_LOGIC_OUTS_B0_1", + "CLK_HROW_LOGIC_OUTS_B19_4", + "CLK_HROW_SW2A2_7", + "CLK_HROW_LH3_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO7", + "CLK_HROW_WL1END1_4", + "CLK_HROW_WW2A2_7", + "CLK_HROW_CK_BUFHCLK_R0", + "CLK_HROW_WW4A1_7", + "CLK_HROW_WW4END2_6", + "CLK_HROW_CLK1_7", + "CLK_HROW_SW4A0_1", + "CLK_HROW_CK_GCLK_TEST_OUT25", + "CLK_HROW_WW2A1_5", + "CLK_HROW_IMUX27_6", + "CLK_HROW_IMUX40_4", + "CLK_HROW_IMUX14_3", + "CLK_HROW_LH10_6", + "CLK_HROW_EL1BEG1_0", + "CLK_HROW_CK_BUFHCLK_R8", + "CLK_HROW_WW4C0_7", + "CLK_HROW_SE4C0_0", + "CLK_HROW_EE4A3_2", + "CLK_HROW_IMUX42_7", + "CLK_HROW_IMUX5_6", + "CLK_HROW_SW2A3_5", + "CLK_HROW_WR1END0_4", + "CLK_HROW_WW4C2_5", + "CLK_HROW_IMUX16_4", + "CLK_HROW_LOGIC_OUTS_B11_1", + "CLK_HROW_LOGIC_OUTS_B12_7", + "CLK_HROW_ER1BEG0_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN23", + "CLK_HROW_CK_GCLK_TEST_OUT23", + "CLK_HROW_BYP0_1", + "CLK_HROW_IMUX13_7", + "CLK_HROW_NE4BEG2_4", + "CLK_HROW_CE_INT_TOP0", + "CLK_HROW_EE2BEG2_2", + "CLK_HROW_IMUX9_5", + "CLK_HROW_IMUX27_1", + "CLK_HROW_LOGIC_OUTS_B12_6", + "CLK_HROW_WL1END0_2", + "CLK_HROW_IMUX7_3", + "CLK_HROW_SW4END0_3", + "CLK_HROW_LOGIC_OUTS_B15_3", + "CLK_HROW_BLOCK_OUTS_B2_0", + "CLK_HROW_FAN0_2", + "CLK_HROW_SW2A0_2", + "CLK_HROW_WR1END1_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN11", + "CLK_HROW_WW4B0_4", + "CLK_HROW_WW2END0_3", + "CLK_HROW_IMUX11_3", + "CLK_HROW_BYP6_2", + "CLK_HROW_WW4A3_2", + "CLK_HROW_EE4B1_3", + "CLK_HROW_R_CK_GCLK11", + "CLK_HROW_FAN3_0", + "CLK_HROW_SE4C2_7", + "CLK_HROW_LOGIC_OUTS_B6_1", + "CLK_HROW_LH8_0", + "CLK_HROW_WL1END2_4", + "CLK_HROW_IMUX44_0", + "CLK_HROW_EE4B0_5", + "CLK_HROW_CE_INT_BOT2", + "CLK_HROW_CK_IN_R1", + "CLK_HROW_WW2A2_0", + "CLK_HROW_SE4BEG1_5", + "CLK_HROW_WW4A0_4", + "CLK_HROW_NE2A3_6", + "CLK_HROW_SW4A2_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO9", + "CLK_HROW_NE4C3_3", + "CLK_HROW_NW4A0_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN31", + "CLK_HROW_LOGIC_OUTS_B3_2", + "CLK_HROW_ER1BEG1_3", + "CLK_HROW_LOGIC_OUTS_B18_4", + "CLK_HROW_CK_GCLK_IN_TEST29", + "CLK_HROW_LH10_4", + "CLK_HROW_IMUX18_0", + "CLK_HROW_NW4END0_6", + "CLK_HROW_IMUX9_2", + "CLK_HROW_FAN4_5", + "CLK_HROW_IMUX4_2", + "CLK_HROW_MONITOR_N_2", + "CLK_HROW_EE4BEG1_3", + "CLK_HROW_LOGIC_OUTS_B3_6", + "CLK_HROW_LOGIC_OUTS_B21_2", + "CLK_HROW_R_CK_GCLK18", + "CLK_HROW_CK_HCLK_OUT_L8", + "CLK_HROW_EE2BEG3_7", + "CLK_HROW_IMUX23_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN7", + "CLK_HROW_SW4END2_0", + "CLK_HROW_LH4_1", + "CLK_HROW_CK_HCLK_OUT_R3", + "CLK_HROW_CK_MUX_OUT_R0", + "CLK_HROW_IMUX45_4", + "CLK_HROW_IMUX43_2", + "CLK_HROW_LOGIC_OUTS_B12_3", + "CLK_HROW_NW4END1_7", + "CLK_HROW_IMUX11_6", + "CLK_HROW_IMUX35_5", + "CLK_HROW_LH10_5", + "CLK_HROW_ER1BEG3_1", + "CLK_HROW_IMUX47_7", + "CLK_HROW_BUFHCE_CE_L6", + "CLK_HROW_LOGIC_OUTS_B10_6", + "CLK_HROW_NW4END2_0", + "CLK_HROW_SW4A0_2", + "CLK_HROW_NE4BEG2_0", + "CLK_HROW_LOGIC_OUTS_B7_4", + "CLK_HROW_WW4END2_5", + "CLK_HROW_FAN1_7", + "CLK_HROW_IMUX45_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO3", + "CLK_HROW_NE4BEG1_1", + "CLK_HROW_LH9_5", + "CLK_HROW_BUFHCE_CE_R9", + "CLK_HROW_NE4BEG3_2", + "CLK_HROW_EE4B2_6", + "CLK_HROW_WW4END2_3", + "CLK_HROW_CK_MUX_OUT_L5", + "CLK_HROW_IMUX21_5", + "CLK_HROW_LOGIC_OUTS_B10_2", + "CLK_HROW_NW2A3_7", + "CLK_HROW_LOGIC_OUTS_B5_3", + "CLK_HROW_CK_GCLK_TEST_OUT29", + "CLK_HROW_WW4END2_0", + "CLK_HROW_CK_HCLK_OUT_L11", + "CLK_HROW_CK_GCLK_TEST13", + "CLK_HROW_WR1END2_5", + "CLK_HROW_CK_GCLK_TEST_OUT30", + "CLK_HROW_IMUX23_0", + "CLK_HROW_LOGIC_OUTS_B18_2", + "CLK_HROW_CK_BUFHCLK_R10", + "CLK_HROW_WW4A2_2", + "CLK_HROW_CK_IN_L_TEST_OUT", + "CLK_HROW_IMUX8_2", + "CLK_HROW_IMUX2_6", + "CLK_HROW_BYP7_3", + "CLK_HROW_LOGIC_OUTS_B23_4", + "CLK_HROW_IMUX21_6", + "CLK_HROW_CK_GCLK_IN_TEST12", + "CLK_HROW_LH5_7", + "CLK_HROW_SW4END1_2", + "CLK_HROW_IMUX9_4", + "CLK_HROW_CK_IN_L13", + "CLK_HROW_IMUX47_0", + "CLK_HROW_BUFHCE_CE_L10", + "CLK_HROW_WW2END3_2", + "CLK_HROW_NW4END1_5", + "CLK_HROW_BLOCK_OUTS_B1_5", + "CLK_HROW_LOGIC_OUTS_B18_1", + "CLK_HROW_IMUX40_2", + "CLK_HROW_SE4C2_1", + "CLK_HROW_CK_BUFHCLK_R5", + "CLK_HROW_WW4END1_1", + "CLK_HROW_WL1END1_7", + "CLK_HROW_BYP1_0", + "CLK_HROW_FAN2_2", + "CLK_HROW_CK_GCLK_TEST_OUT20", + "CLK_HROW_LOGIC_OUTS_B13_0", + "CLK_HROW_IMUX11_0", + "CLK_HROW_CK_BUFHCLK_L11", + "CLK_HROW_NW2A1_3", + "CLK_HROW_EL1BEG0_6", + "CLK_HROW_WW4C1_0", + "CLK_HROW_SW4A2_1", + "CLK_HROW_WW4B0_2", + "CLK_HROW_BLOCK_OUTS_B3_7", + "CLK_HROW_LOGIC_OUTS_B18_3", + "CLK_HROW_ER1BEG3_5", + "CLK_HROW_BYP2_2", + "CLK_HROW_CK_GCLK_OUT_TEST12", + "CLK_HROW_LOGIC_OUTS_B20_7", + "CLK_HROW_WW4C0_2", + "CLK_HROW_WW2A0_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN21", + "CLK_HROW_BUFHCE_CE_R11", + "CLK_HROW_IMUX44_3", + "CLK_HROW_WW4B2_7", + "CLK_HROW_CK_HCLK_OUT_L6", + "CLK_HROW_CLK0_4", + "CLK_HROW_WW4END0_6", + "CLK_HROW_IMUX14_2", + "CLK_HROW_IMUX5_2", + "CLK_HROW_CLK0_7", + "CLK_HROW_BUFHCE_CE_L1", + "CLK_HROW_WW4END1_5", + "CLK_HROW_LOGIC_OUTS_B12_1", + "CLK_HROW_WR1END2_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCO30", + "CLK_HROW_FAN1_5", + "CLK_HROW_IMUX2_5", + "CLK_HROW_CE_INT_TOP5", + "CLK_HROW_IMUX41_2", + "CLK_HROW_IMUX16_6", + "CLK_HROW_IMUX4_4", + "CLK_HROW_WW2A3_7", + "CLK_HROW_EE2BEG0_7", + "CLK_HROW_WW4B1_7", + "CLK_HROW_WW2A0_7", + "CLK_HROW_FAN2_0", + "CLK_HROW_IMUX7_2", + "CLK_HROW_WL1END0_0", + "CLK_HROW_CK_GCLK_OUT_TEST27", + "CLK_HROW_NE2A3_4", + "CLK_HROW_ER1BEG1_7", + "CLK_HROW_LOGIC_OUTS_B1_3", + "CLK_HROW_EE2BEG1_4", + "CLK_HROW_IMUX29_4", + "CLK_HROW_BYP3_5", + "CLK_HROW_SW2A2_2", + "CLK_HROW_CTRL1_6", + "CLK_HROW_IMUX21_1", + "CLK_HROW_WW4A0_6", + "CLK_HROW_CK_BUFRCLK_R3", + "CLK_HROW_BYP6_0", + "CLK_HROW_EE4A3_0", + "CLK_HROW_LOGIC_OUTS_B5_1", + "CLK_HROW_EE2A1_6", + "CLK_HROW_R_CK_GCLK4", + "CLK_HROW_NW4END0_0", + "CLK_HROW_LOGIC_OUTS_B8_7", + "CLK_HROW_NW4END3_6", + "CLK_HROW_CK_GCLK_TEST_IN28", + "CLK_HROW_LOGIC_OUTS_B5_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN29", + "CLK_HROW_BYP4_6", + "CLK_HROW_SW4A1_6", + "CLK_HROW_LOGIC_OUTS_B9_0", + "CLK_HROW_WW4A2_5", + "CLK_HROW_IMUX39_4", + "CLK_HROW_FAN4_1", + "CLK_HROW_SW4A3_4", + "CLK_HROW_LH7_2", + "CLK_HROW_CK_GCLK_OUT_TEST8", + "CLK_HROW_IMUX21_4", + "CLK_HROW_IMUX40_0", + "CLK_HROW_LOGIC_OUTS_B14_1", + "CLK_HROW_WW4END1_3", + "CLK_HROW_EE4C0_6", + "CLK_HROW_NE4C2_7", + "CLK_HROW_IMUX34_1", + "CLK_HROW_NE4C0_7", + "CLK_HROW_LH3_1", + "CLK_HROW_IMUX24_2", + "CLK_HROW_SE2A1_5", + "CLK_HROW_SW2A1_1", + "CLK_HROW_SW4END3_6", + "CLK_HROW_IMUX3_3", + "CLK_HROW_CTRL1_3", + "CLK_HROW_LOGIC_OUTS_B2_2", + "CLK_HROW_NW4END1_1", + "CLK_HROW_WW4C2_3", + "CLK_HROW_WW2END0_0", + "CLK_HROW_ER1BEG2_1", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN28", + "CLK_HROW_NW4A0_6", + "CLK_HROW_CK_GCLK_TEST_IN11", + "CLK_HROW_LH2_1", + "CLK_HROW_NE4BEG0_6", + "CLK_HROW_IMUX37_0", + "CLK_HROW_LH4_0", + "CLK_HROW_IMUX7_6", + "CLK_HROW_EE4B2_1", + "CLK_HROW_NW2A3_2", + "CLK_HROW_IMUX47_6", + "CLK_HROW_SE2A2_5", + "CLK_HROW_IMUX7_5", + "CLK_HROW_NE4C0_0", + "CLK_HROW_MONITOR_P_6", + "CLK_HROW_CK_GCLK_TEST2", + "CLK_HROW_LH12_5", + "CLK_HROW_LH1_1", + "CLK_HROW_LOGIC_OUTS_B5_5", + "CLK_HROW_IMUX25_7", + "CLK_HROW_IMUX12_5", + "CLK_HROW_MONITOR_P_1", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN16", + "CLK_HROW_WL1END3_3", + "CLK_HROW_IMUX30_6", + "CLK_HROW_WW2END1_5", + "CLK_HROW_LOGIC_OUTS_B22_6", + "CLK_HROW_WR1END3_0", + "CLK_HROW_MONITOR_P_7", + "CLK_HROW_IMUX17_7", + "CLK_HROW_IMUX45_5", + "CLK_HROW_LOGIC_OUTS_B13_2", + "CLK_HROW_IMUX37_5", + "CLK_HROW_CK_INT_1_1", + "CLK_HROW_BLOCK_OUTS_B2_6", + "CLK_HROW_CK_GCLK_TEST_OUT14", + "CLK_HROW_IMUX19_3", + "CLK_HROW_WW4END1_0", + "CLK_HROW_BLOCK_OUTS_B1_0", + "CLK_HROW_SW4A0_7", + "CLK_HROW_LOGIC_OUTS_B5_0", + "CLK_HROW_LH8_5", + "CLK_HROW_CK_HCLK_OUT_R2", + "CLK_HROW_BYP7_6", + "CLK_HROW_LOGIC_OUTS_B14_5", + "CLK_HROW_NE4C1_4", + "CLK_HROW_IMUX21_7", + "CLK_HROW_EE4C3_7", + "CLK_HROW_SW4A2_2", + "CLK_HROW_SE4C2_0", + "CLK_HROW_EE2A0_2", + "CLK_HROW_CK_GCLK_TEST_OUT6", + "CLK_HROW_BLOCK_OUTS_B3_1", + "CLK_HROW_CK_BUFRCLK_R2", + "CLK_HROW_WW4END3_3", + "CLK_HROW_SW2A2_6", + "CLK_HROW_SW4END0_2", + "CLK_HROW_IMUX18_1", + "CLK_HROW_MONITOR_N_5", + "CLK_HROW_WW4A1_1", + "CLK_HROW_LOGIC_OUTS_B15_6", + "CLK_HROW_LOGIC_OUTS_B10_0", + "CLK_HROW_LOGIC_OUTS_B18_7", + "CLK_HROW_IMUX39_7", + "CLK_HROW_IMUX25_5", + "CLK_HROW_EE4B3_3", + "CLK_HROW_CTRL0_3", + "CLK_HROW_IMUX42_6", + "CLK_HROW_CK_GCLK_TEST_OUT31", + "CLK_HROW_BYP1_2", + "CLK_HROW_CK_GCLK_TEST_IN6", + "CLK_HROW_BUFHCE_CE_R2", + "CLK_HROW_NW2A1_1", + "CLK_HROW_IMUX22_7", + "CLK_HROW_IMUX33_7", + "CLK_HROW_CK_GCLK_OUT_TEST1", + "CLK_HROW_SW4END1_6", + "CLK_HROW_BYP4_1", + "CLK_HROW_LOGIC_OUTS_B14_3", + "CLK_HROW_CLK0_3", + "CLK_HROW_CK_BUFHCLK_R9", + "CLK_HROW_CK_IN_R_TEST_OUT", + "CLK_HROW_CK_GCLK_TEST_IN5", + "CLK_HROW_NE4C2_3", + "CLK_HROW_WW4B0_1", + "CLK_HROW_SW2A1_7", + "CLK_HROW_IMUX28_5", + "CLK_HROW_CE_INT_BOT6", + "CLK_HROW_IMUX14_6", + "CLK_HROW_CK_GCLK_TEST_IN17", + "CLK_HROW_SW2A0_6", + "CLK_HROW_SW2A0_4", + "CLK_HROW_CK_MUX_OUT_R8", + "CLK_HROW_IMUX44_5", + "CLK_HROW_LOGIC_OUTS_B5_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO17", + "CLK_HROW_CLK1_2", + "CLK_HROW_CTRL0_4", + "CLK_HROW_WR1END2_0", + "CLK_HROW_LOGIC_OUTS_B3_5", + "CLK_HROW_IMUX23_3", + "CLK_HROW_SW2A0_0", + "CLK_HROW_IMUX37_6", + "CLK_HROW_IMUX18_2", + "CLK_HROW_WW4END3_2", + "CLK_HROW_SE4BEG0_6", + "CLK_HROW_WW4B2_1", + "CLK_HROW_SE4C2_2", + "CLK_HROW_IMUX16_7", + "CLK_HROW_NW4END1_4", + "CLK_HROW_SW4END3_3", + "CLK_HROW_FAN3_7", + "CLK_HROW_CK_GCLK_TEST_IN20", + "CLK_HROW_WW4END0_3", + "CLK_HROW_NE4BEG0_3", + "CLK_HROW_IMUX14_5", + "CLK_HROW_NE4C3_4", + "CLK_HROW_EE2BEG2_4", + "CLK_HROW_WW4A3_0", + "CLK_HROW_BYP6_1", + "CLK_HROW_LH7_5", + "CLK_HROW_CLK1_4", + "CLK_HROW_IMUX34_7", + "CLK_HROW_WW4END2_4", + "CLK_HROW_WR1END3_3", + "CLK_HROW_IMUX13_4", + "CLK_HROW_CK_BUFHCLK_R11", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN26", + "CLK_HROW_IMUX40_7", + "CLK_HROW_FAN0_6", + "CLK_HROW_BYP4_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN18", + "CLK_HROW_EE4BEG1_0", + "CLK_HROW_EE4A1_4", + "CLK_HROW_NE4C3_7", + "CLK_HROW_EE4B0_3", + "CLK_HROW_CTRL1_0", + "CLK_HROW_SE4BEG2_6", + "CLK_HROW_LOGIC_OUTS_B4_7", + "CLK_HROW_CK_GCLK_TEST5", + "CLK_HROW_WL1END2_7", + "CLK_HROW_IMUX40_5", + "CLK_HROW_SE4C3_3", + "CLK_HROW_NW2A2_2", + "CLK_HROW_CK_IN_R5", + "CLK_HROW_WW4C1_6", + "CLK_HROW_EE2A1_7", + "CLK_HROW_FAN4_2", + "CLK_HROW_WL1END1_1", + "CLK_HROW_IMUX44_6", + "CLK_HROW_SE4BEG2_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN25", + "CLK_HROW_NE4BEG3_4", + "CLK_HROW_NE4C2_2", + "CLK_HROW_CK_MUX_OUT_R4", + "CLK_HROW_WW2END0_4", + "CLK_HROW_FAN3_2", + "CLK_HROW_EE4C2_0", + "CLK_HROW_R_CK_GCLK19", + "CLK_HROW_LOGIC_OUTS_B13_1", + "CLK_HROW_WR1END0_5", + "CLK_HROW_CK_GCLK_OUT_TEST4", + "CLK_HROW_NW2A0_1", + "CLK_HROW_WW2END2_4", + "CLK_HROW_IMUX27_7", + "CLK_HROW_NE4BEG3_3", + "CLK_HROW_WW4A3_4", + "CLK_HROW_WL1END2_0", + "CLK_HROW_NW4A1_4", + "CLK_HROW_WW2A2_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO5", + "CLK_HROW_LOGIC_OUTS_B13_5", + "CLK_HROW_WW4B1_0", + "CLK_HROW_EE4A2_2", + "CLK_HROW_IMUX12_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO31", + "CLK_HROW_NW4END3_5", + "CLK_HROW_CK_GCLK_TEST_OUT27", + "CLK_HROW_WL1END1_0", + "CLK_HROW_WW4B3_0", + "CLK_HROW_LH9_1", + "CLK_HROW_IMUX33_6", + "CLK_HROW_NW4END1_3", + "CLK_HROW_EE4C2_4", + "CLK_HROW_BYP0_0", + "CLK_HROW_IMUX26_3", + "CLK_HROW_CK_GCLK_IN_TEST1", + "CLK_HROW_BOT_R_CK_BUFG_CASCO6", + "CLK_HROW_WW4A3_1", + "CLK_HROW_CK_GCLK_TEST_OUT22", + "CLK_HROW_EE4B1_6", + "CLK_HROW_FAN7_3", + "CLK_HROW_NE2A0_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN8", + "CLK_HROW_EL1BEG2_4", + "CLK_HROW_EE4A2_3", + "CLK_HROW_IMUX20_2", + "CLK_HROW_IMUX10_6", + "CLK_HROW_SE2A3_4", + "CLK_HROW_IMUX9_6", + "CLK_HROW_LH5_4", + "CLK_HROW_FAN7_2", + "CLK_HROW_WW4A1_5", + "CLK_HROW_LOGIC_OUTS_B6_7", + "CLK_HROW_EE4A0_6", + "CLK_HROW_EL1BEG0_1", + "CLK_HROW_BLOCK_OUTS_B2_4", + "CLK_HROW_NE2A0_4", + "CLK_HROW_SW2A1_0", + "CLK_HROW_IMUX46_3", + "CLK_HROW_CK_GCLK_TEST16", + "CLK_HROW_NW4A3_6", + "CLK_HROW_LOGIC_OUTS_B8_3", + "CLK_HROW_NW2A0_2", + "CLK_HROW_NE2A3_1", + "CLK_HROW_LOGIC_OUTS_B22_2", + "CLK_HROW_CK_HCLK_OUT_R11", + "CLK_HROW_IMUX43_1", + "CLK_HROW_IMUX46_6", + "CLK_HROW_NW4A1_1", + "CLK_HROW_CK_MUX_OUT_R5", + "CLK_HROW_CK_BUFRCLK_L3", + "CLK_HROW_WW4END2_7", + "CLK_HROW_WW2END1_3", + "CLK_HROW_IMUX20_0", + "CLK_HROW_NE4C2_6", + "CLK_HROW_CK_IN_R_TEST_IN", + "CLK_HROW_IMUX23_1", + "CLK_HROW_LOGIC_OUTS_B17_3", + "CLK_HROW_IMUX9_3", + "CLK_HROW_NE2A2_4", + "CLK_HROW_IMUX10_1", + "CLK_HROW_CK_MUX_OUT_R9", + "CLK_HROW_IMUX14_0", + "CLK_HROW_CTRL0_5", + "CLK_HROW_EL1BEG1_2", + "CLK_HROW_LOGIC_OUTS_B5_4", + "CLK_HROW_SE4C2_6", + "CLK_HROW_EE4B1_2", + "CLK_HROW_BLOCK_OUTS_B0_2", + "CLK_HROW_WW4B2_5", + "CLK_HROW_NE2A0_3", + "CLK_HROW_CLK1_0", + "CLK_HROW_NW2A1_4", + "CLK_HROW_CK_GCLK_TEST_IN15", + "CLK_HROW_ER1BEG1_4", + "CLK_HROW_EL1BEG0_4", + "CLK_HROW_IMUX34_6", + "CLK_HROW_SW2A1_4", + "CLK_HROW_EE4C3_4", + "CLK_HROW_CTRL0_1", + "CLK_HROW_LOGIC_OUTS_B4_4", + "CLK_HROW_BYP0_7", + "CLK_HROW_CK_GCLK_TEST_IN16", + "CLK_HROW_SE4BEG2_4", + "CLK_HROW_LOGIC_OUTS_B19_7", + "CLK_HROW_WL1END3_7", + "CLK_HROW_EE2BEG1_3", + "CLK_HROW_CK_GCLK_TEST_OUT17", + "CLK_HROW_NE4C0_4", + "CLK_HROW_IMUX15_3", + "CLK_HROW_CK_MUX_OUT_R3", + "CLK_HROW_IMUX41_3", + "CLK_HROW_NE2A2_3", + "CLK_HROW_CK_GCLK_TEST_IN26", + "CLK_HROW_EE2BEG2_5", + "CLK_HROW_LOGIC_OUTS_B13_3", + "CLK_HROW_LH4_5", + "CLK_HROW_NW4A0_2", + "CLK_HROW_BYP4_5", + "CLK_HROW_IMUX30_0", + "CLK_HROW_WW4A0_0", + "CLK_HROW_NE4C3_2", + "CLK_HROW_CK_GCLK_TEST_OUT3", + "CLK_HROW_WW4B3_4", + "CLK_HROW_IMUX32_6", + "CLK_HROW_IMUX29_1", + "CLK_HROW_IMUX43_6", + "CLK_HROW_NW4A2_2", + "CLK_HROW_SE2A1_4", + "CLK_HROW_SE4BEG0_1", + "CLK_HROW_CLK0_6", + "CLK_HROW_BUFHCE_CE_L2", + "CLK_HROW_CK_BUFHCLK_R3", + "CLK_HROW_CK_GCLK_IN_TEST20", + "CLK_HROW_IMUX46_4", + "CLK_HROW_NW2A3_4", + "CLK_HROW_NW4A0_4", + "CLK_HROW_WW4A3_7", + "CLK_HROW_LOGIC_OUTS_B6_0", + "CLK_HROW_LOGIC_OUTS_B3_0", + "CLK_HROW_CTRL0_0", + "CLK_HROW_IMUX30_4", + "CLK_HROW_CK_HCLK_OUT_R5", + "CLK_HROW_EL1BEG1_5", + "CLK_HROW_NW4END3_0", + "CLK_HROW_BLOCK_OUTS_B0_0", + "CLK_HROW_WW4END3_7", + "CLK_HROW_CTRL1_7", + "CLK_HROW_NW4A1_6", + "CLK_HROW_SE2A3_1", + "CLK_HROW_LH4_4", + "CLK_HROW_SW2A3_3", + "CLK_HROW_BYP7_7", + "CLK_HROW_CK_GCLK_TEST1", + "CLK_HROW_IMUX43_3", + "CLK_HROW_SE2A3_0", + "CLK_HROW_CK_IN_L6", + "CLK_HROW_WR1END1_3", + "CLK_HROW_LOGIC_OUTS_B16_4", + "CLK_HROW_EE4BEG2_1", + "CLK_HROW_EE2A1_4", + "CLK_HROW_IMUX16_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN3", + "CLK_HROW_CK_HCLK_OUT_L10", + "CLK_HROW_SW2A3_1", + "CLK_HROW_SE2A2_1", + "CLK_HROW_WR1END0_2", + "CLK_HROW_NW2A0_4", + "CLK_HROW_IMUX16_3", + "CLK_HROW_EE4B2_2", + "CLK_HROW_NE2A0_5", + "CLK_HROW_FAN1_4", + "CLK_HROW_WW4END1_2", + "CLK_HROW_IMUX3_2", + "CLK_HROW_CK_GCLK_TEST29", + "CLK_HROW_SW4END1_0", + "CLK_HROW_CK_IN_R0", + "CLK_HROW_CE_INT_BOT7", + "CLK_HROW_IMUX8_3", + "CLK_HROW_CK_GCLK_TEST_OUT9", + "CLK_HROW_IMUX30_5", + "CLK_HROW_SW4A0_3", + "CLK_HROW_WW4C3_6", + "CLK_HROW_LOGIC_OUTS_B22_7", + "CLK_HROW_WW2END0_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO21", + "CLK_HROW_WW4END3_1", + "CLK_HROW_CK_IN_R11", + "CLK_HROW_CK_GCLK_TEST_OUT2", + "CLK_HROW_BUFHCE_CE_R3", + "CLK_HROW_IMUX9_1", + "CLK_HROW_CK_IN_R12", + "CLK_HROW_NW4END0_7", + "CLK_HROW_IMUX39_0", + "CLK_HROW_IMUX17_4", + "CLK_HROW_IMUX22_5", + "CLK_HROW_EE2BEG3_1", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN10", + "CLK_HROW_NW4END1_0", + "CLK_HROW_NW4A2_3", + "CLK_HROW_ER1BEG1_6", + "CLK_HROW_EL1BEG3_6", + "CLK_HROW_NW2A3_6", + "CLK_HROW_IMUX1_3", + "CLK_HROW_IMUX35_4", + "CLK_HROW_SE4C0_5", + "CLK_HROW_LOGIC_OUTS_B21_6", + "CLK_HROW_IMUX35_6", + "CLK_HROW_FAN4_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO28", + "CLK_HROW_CLK1_1", + "CLK_HROW_CK_GCLK_OUT_TEST17", + "CLK_HROW_BUFHCE_CE_R6", + "CLK_HROW_IMUX6_7", + "CLK_HROW_CK_GCLK_TEST_IN30", + "CLK_HROW_CK_GCLK_TEST10", + "CLK_HROW_NW4END3_4", + "CLK_HROW_IMUX16_1", + "CLK_HROW_CK_IN_R6", + "CLK_HROW_EE2BEG1_1", + "CLK_HROW_CK_GCLK_IN_TEST14", + "CLK_HROW_EE4C3_0", + "CLK_HROW_FAN3_6", + "CLK_HROW_WW2A0_4", + "CLK_HROW_CK_MUX_OUT_R10", + "CLK_HROW_CK_GCLK_TEST_OUT8", + "CLK_HROW_EE4A0_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO20", + "CLK_HROW_LOGIC_OUTS_B2_1", + "CLK_HROW_NW4A2_1", + "CLK_HROW_FAN7_6", + "CLK_HROW_WW4END3_4", + "CLK_HROW_LOGIC_OUTS_B8_1", + "CLK_HROW_EE2BEG3_3", + "CLK_HROW_EE4B0_2", + "CLK_HROW_WW4B0_7", + "CLK_HROW_EE4C1_0", + "CLK_HROW_WW2END3_0", + "CLK_HROW_LH1_6", + "CLK_HROW_WR1END2_1", + "CLK_HROW_LOGIC_OUTS_B8_4", + "CLK_HROW_LH8_3", + "CLK_HROW_EE4B3_7", + "CLK_HROW_IMUX35_2", + "CLK_HROW_CK_GCLK_IN_TEST16", + "CLK_HROW_BLOCK_OUTS_B1_7", + "CLK_HROW_CK_IN_L5", + "CLK_HROW_LH12_6", + "CLK_HROW_WW4A0_7", + "CLK_HROW_SE4BEG1_3", + "CLK_HROW_IMUX15_1", + "CLK_HROW_WW2END0_6", + "CLK_HROW_LOGIC_OUTS_B16_0", + "CLK_HROW_EE4C1_4", + "CLK_HROW_IMUX41_5", + "CLK_HROW_WL1END1_6", + "CLK_HROW_EE4BEG0_7", + "CLK_HROW_LOGIC_OUTS_B14_7", + "CLK_HROW_SW4END2_6", + "CLK_HROW_IMUX33_1", + "CLK_HROW_R_CK_GCLK0", + "CLK_HROW_LH12_2", + "CLK_HROW_IMUX6_6", + "CLK_HROW_WW4A2_7", + "CLK_HROW_EE2BEG1_2", + "CLK_HROW_LH8_6", + "CLK_HROW_WW2END2_3", + "CLK_HROW_EE4B1_1", + "CLK_HROW_CK_HCLK_OUT_R0", + "CLK_HROW_NE4BEG2_2", + "CLK_HROW_NE2A2_2", + "CLK_HROW_SE4C1_1", + "CLK_HROW_BLOCK_OUTS_B1_3", + "CLK_HROW_LOGIC_OUTS_B3_1", + "CLK_HROW_BYP0_5", + "CLK_HROW_NE2A3_7", + "CLK_HROW_CK_MUX_OUT_R2", + "CLK_HROW_WW2END3_6", + "CLK_HROW_SE4C1_2", + "CLK_HROW_IMUX28_6", + "CLK_HROW_EE4C3_1", + "CLK_HROW_IMUX12_3", + "CLK_HROW_LOGIC_OUTS_B4_1", + "CLK_HROW_IMUX43_4", + "CLK_HROW_IMUX35_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN12", + "CLK_HROW_WW4B3_6", + "CLK_HROW_EE4A2_6", + "CLK_HROW_IMUX8_6", + "CLK_HROW_IMUX12_4", + "CLK_HROW_CK_GCLK_TEST_IN1", + "CLK_HROW_CE_INT_TOP10", + "CLK_HROW_CK_GCLK_OUT_TEST31", + "CLK_HROW_SE2A0_4", + "CLK_HROW_IMUX27_3", + "CLK_HROW_MONITOR_P_0", + "CLK_HROW_IMUX18_3", + "CLK_HROW_CE_INT_TOP3", + "CLK_HROW_NE2A3_3", + "CLK_HROW_SW2A3_4", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN17", + "CLK_HROW_BUFHCE_CE_R10", + "CLK_HROW_IMUX20_7", + "CLK_HROW_CK_GCLK_OUT_TEST18", + "CLK_HROW_EE4BEG2_4", + "CLK_HROW_CK_GCLK_TEST_IN21", + "CLK_HROW_BLOCK_OUTS_B0_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO14", + "CLK_HROW_NW4A0_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO19", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN20", + "CLK_HROW_LOGIC_OUTS_B8_2", + "CLK_HROW_EE4A3_7", + "CLK_HROW_EE2BEG3_6", + "CLK_HROW_SE4BEG1_7", + "CLK_HROW_IMUX29_3", + "CLK_HROW_SE2A3_3", + "CLK_HROW_IMUX46_7", + "CLK_HROW_IMUX33_2", + "CLK_HROW_NW4A1_0", + "CLK_HROW_ER1BEG1_0", + "CLK_HROW_NW4A1_5", + "CLK_HROW_FAN2_6", + "CLK_HROW_EE2BEG0_5", + "CLK_HROW_LOGIC_OUTS_B17_0", + "CLK_HROW_IMUX10_2", + "CLK_HROW_SE4C2_5", + "CLK_HROW_R_CK_GCLK20", + "CLK_HROW_NE2A1_4", + "CLK_HROW_EE2BEG2_1", + "CLK_HROW_SE4BEG1_0", + "CLK_HROW_NE4BEG2_1", + "CLK_HROW_BYP5_7", + "CLK_HROW_EE4A1_1", + "CLK_HROW_LH7_6", + "CLK_HROW_NW4END0_3", + "CLK_HROW_LOGIC_OUTS_B11_2", + "CLK_HROW_CK_GCLK_TEST_OUT18", + "CLK_HROW_CK_GCLK_IN_TEST2", + "CLK_HROW_CTRL1_1", + "CLK_HROW_CK_GCLK_OUT_TEST20", + "CLK_HROW_SW4A0_6", + "CLK_HROW_IMUX34_2", + "CLK_HROW_SW4A1_2", + "CLK_HROW_FAN7_4", + "CLK_HROW_IMUX23_6", + "CLK_HROW_FAN6_3", + "CLK_HROW_SW2A2_0", + "CLK_HROW_CK_GCLK_IN_TEST18", + "CLK_HROW_LOGIC_OUTS_B17_7", + "CLK_HROW_R_CK_GCLK31", + "CLK_HROW_WW2A3_6", + "CLK_HROW_LOGIC_OUTS_B10_1", + "CLK_HROW_LH12_3", + "CLK_HROW_SW2A2_3", + "CLK_HROW_LOGIC_OUTS_B21_4", + "CLK_HROW_LH4_3", + "CLK_HROW_SE2A0_2", + "CLK_HROW_EE2BEG2_7", + "CLK_HROW_IMUX7_0", + "CLK_HROW_NE2A1_1", + "CLK_HROW_CK_GCLK_TEST26", + "CLK_HROW_IMUX29_5", + "CLK_HROW_IMUX15_6", + "CLK_HROW_FAN0_5", + "CLK_HROW_NE4BEG3_7", + "CLK_HROW_FAN2_7", + "CLK_HROW_IMUX36_1", + "CLK_HROW_EE4A3_3", + "CLK_HROW_NE4C1_1", + "CLK_HROW_IMUX19_4", + "CLK_HROW_EE2A0_7", + "CLK_HROW_LOGIC_OUTS_B23_5", + "CLK_HROW_NW2A3_3", + "CLK_HROW_SE4BEG0_0", + "CLK_HROW_BYP1_5", + "CLK_HROW_BOT_R_CK_BUFG_CASCO27", + "CLK_HROW_WW4END0_5", + "CLK_HROW_CK_GCLK_OUT_TEST0", + "CLK_HROW_WW4A3_5", + "CLK_HROW_SE2A2_0", + "CLK_HROW_LH4_7", + "CLK_HROW_IMUX26_6", + "CLK_HROW_CK_HCLK_OUT_L7", + "CLK_HROW_NE2A0_1", + "CLK_HROW_WW2END0_7", + "CLK_HROW_WR1END1_1", + "CLK_HROW_IMUX22_4", + "CLK_HROW_SW2A3_0", + "CLK_HROW_EE4A0_0", + "CLK_HROW_WR1END0_1", + "CLK_HROW_IMUX38_6", + "CLK_HROW_SW4A2_0", + "CLK_HROW_EE2A0_3", + "CLK_HROW_NW4A3_3", + "CLK_HROW_IMUX34_5", + "CLK_HROW_LH3_4", + "CLK_HROW_ER1BEG3_7", + "CLK_HROW_CTRL1_4", + "CLK_HROW_IMUX5_4", + "CLK_HROW_IMUX45_1", + "CLK_HROW_BYP7_4", + "CLK_HROW_IMUX39_2", + "CLK_HROW_NE2A1_7", + "CLK_HROW_EE4A3_4", + "CLK_HROW_WW2A0_1", + "CLK_HROW_NE2A1_5", + "CLK_HROW_IMUX40_3", + "CLK_HROW_SE4BEG2_5", + "CLK_HROW_NE4BEG0_1", + "CLK_HROW_CK_GCLK_TEST_OUT21", + "CLK_HROW_IMUX37_2", + "CLK_HROW_WL1END3_0", + "CLK_HROW_IMUX8_5", + "CLK_HROW_LH6_1", + "CLK_HROW_IMUX1_4", + "CLK_HROW_EE4B3_2", + "CLK_HROW_BLOCK_OUTS_B3_3", + "CLK_HROW_IMUX27_0", + "CLK_HROW_SW2A0_1", + "CLK_HROW_LOGIC_OUTS_B4_6", + "CLK_HROW_LH3_3", + "CLK_HROW_CK_GCLK_OUT_TEST14", + "CLK_HROW_WW4C3_4", + "CLK_HROW_BUFHCE_CE_L5", + "CLK_HROW_CK_GCLK_IN_TEST7", + "CLK_HROW_EE4C3_5", + "CLK_HROW_NW2A2_7", + "CLK_HROW_EE4BEG2_5", + "CLK_HROW_WW4A1_2", + "CLK_HROW_NE4BEG2_6", + "CLK_HROW_IMUX46_1", + "CLK_HROW_WW4A2_3", + "CLK_HROW_BYP5_3", + "CLK_HROW_LH2_6", + "CLK_HROW_CK_GCLK_TEST_OUT5", + "CLK_HROW_IMUX19_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO2", + "CLK_HROW_WW4END0_2", + "CLK_HROW_CK_GCLK_IN_TEST5", + "CLK_HROW_NW2A3_5", + "CLK_HROW_IMUX36_5", + "CLK_HROW_NW4A2_4", + "CLK_HROW_CK_GCLK_OUT_TEST19", + "CLK_HROW_LH7_1", + "CLK_HROW_WW4B2_4", + "CLK_HROW_EL1BEG2_1", + "CLK_HROW_CK_HCLK_OUT_R6", + "CLK_HROW_CK_MUX_OUT_L6", + "CLK_HROW_MONITOR_N_4", + "CLK_HROW_IMUX3_6", + "CLK_HROW_BYP1_4", + "CLK_HROW_NE4C0_5", + "CLK_HROW_IMUX4_3", + "CLK_HROW_SW4END1_3", + "CLK_HROW_SW4A0_0", + "CLK_HROW_WW4END2_1", + "CLK_HROW_CLK1_5", + "CLK_HROW_SW4END0_4", + "CLK_HROW_WW4B1_6", + "CLK_HROW_BYP3_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN24", + "CLK_HROW_EL1BEG0_2", + "CLK_HROW_LOGIC_OUTS_B15_0", + "CLK_HROW_EE4BEG1_7", + "CLK_HROW_BLOCK_OUTS_B2_7", + "CLK_HROW_NE4BEG2_3", + "CLK_HROW_WW2END3_4", + "CLK_HROW_EE4BEG3_6", + "CLK_HROW_IMUX15_5", + "CLK_HROW_ER1BEG2_2", + "CLK_HROW_FAN4_4", + "CLK_HROW_EL1BEG1_3", + "CLK_HROW_WL1END1_2", + "CLK_HROW_CK_GCLK_TEST_IN24", + "CLK_HROW_BYP2_5", + "CLK_HROW_FAN0_0", + "CLK_HROW_LH6_6", + "CLK_HROW_SW4A3_1", + "CLK_HROW_NE4C2_0", + "CLK_HROW_LOGIC_OUTS_B15_4", + "CLK_HROW_WW2A0_3", + "CLK_HROW_LOGIC_OUTS_B16_3", + "CLK_HROW_R_CK_GCLK29", + "CLK_HROW_LH7_4", + "CLK_HROW_R_CK_GCLK7", + "CLK_HROW_CK_MUX_OUT_L2", + "CLK_HROW_WW2END1_2", + "CLK_HROW_IMUX42_0", + "CLK_HROW_IMUX23_5", + "CLK_HROW_CK_GCLK_TEST28", + "CLK_HROW_LOGIC_OUTS_B2_0", + "CLK_HROW_ER1BEG2_7", + "CLK_HROW_REFCK_EASTCLK1", + "CLK_HROW_WW4C0_1", + "CLK_HROW_LOGIC_OUTS_B0_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO12", + "CLK_HROW_IMUX21_3", + "CLK_HROW_LH5_0", + "CLK_HROW_LH5_6", + "CLK_HROW_SW4A2_6", + "CLK_HROW_NE2A0_7", + "CLK_HROW_BOT_R_CK_BUFG_CASCO8", + "CLK_HROW_IMUX0_3", + "CLK_HROW_IMUX13_5", + "CLK_HROW_LOGIC_OUTS_B17_6", + "CLK_HROW_CK_GCLK_TEST8", + "CLK_HROW_EL1BEG1_1", + "CLK_HROW_EE4C2_1", + "CLK_HROW_SW4END2_3", + "CLK_HROW_IMUX47_3", + "CLK_HROW_CK_GCLK_OUT_TEST22", + "CLK_HROW_BYP3_2", + "CLK_HROW_WW4B1_4", + "CLK_HROW_LH11_0", + "CLK_HROW_CK_BUFHCLK_R7", + "CLK_HROW_NE4C2_1", + "CLK_HROW_SW2A2_4", + "CLK_HROW_WW2END2_7", + "CLK_HROW_LOGIC_OUTS_B22_0", + "CLK_HROW_CK_BUFHCLK_L9", + "CLK_HROW_NW2A0_3", + "CLK_HROW_LH7_3", + "CLK_HROW_IMUX41_0", + "CLK_HROW_CK_IN_R2", + "CLK_HROW_EE4BEG2_2", + "CLK_HROW_IMUX32_5", + "CLK_HROW_CK_HCLK_OUT_L2", + "CLK_HROW_SE4BEG3_2", + "CLK_HROW_ER1BEG2_3", + "CLK_HROW_IMUX20_4", + "CLK_HROW_CE_INT_TOP2", + "CLK_HROW_BYP4_2", + "CLK_HROW_WW4B0_3", + "CLK_HROW_SE4C2_4", + "CLK_HROW_CK_GCLK_TEST_OUT7", + "CLK_HROW_CK_BUFHCLK_L7", + "CLK_HROW_LOGIC_OUTS_B21_3", + "CLK_HROW_WW4END0_4", + "CLK_HROW_SE4C1_6", + "CLK_HROW_IMUX22_3", + "CLK_HROW_FAN2_3", + "CLK_HROW_IMUX31_7", + "CLK_HROW_CLK0_0", + "CLK_HROW_IMUX34_4", + "CLK_HROW_NW2A3_0", + "CLK_HROW_CK_GCLK_TEST_OUT24", + "CLK_HROW_CK_GCLK_OUT_TEST2", + "CLK_HROW_NE2A2_6", + "CLK_HROW_EE4A0_2", + "CLK_HROW_BYP1_7", + "CLK_HROW_NE2A1_2", + "CLK_HROW_EE4C2_7", + "CLK_HROW_CK_GCLK_IN_TEST25", + "CLK_HROW_LOGIC_OUTS_B11_4", + "CLK_HROW_CK_GCLK_TEST_IN4", + "CLK_HROW_IMUX39_6", + "CLK_HROW_R_CK_GCLK24", + "CLK_HROW_WW4C2_1", + "CLK_HROW_BOT_R_CK_BUFG_CASCO22", + "CLK_HROW_CE_INT_TOP11", + "CLK_HROW_SE2A1_6", + "CLK_HROW_IMUX3_7", + "CLK_HROW_IMUX13_3", + "CLK_HROW_CK_GCLK_OUT_TEST25", + "CLK_HROW_IMUX39_3", + "CLK_HROW_NW4END2_4", + "CLK_HROW_LH12_1", + "CLK_HROW_WR1END1_2", + "CLK_HROW_R_CK_GCLK5", + "CLK_HROW_IMUX17_0", + "CLK_HROW_LH5_1", + "CLK_HROW_EL1BEG2_6", + "CLK_HROW_SE4C1_5", + "CLK_HROW_SE4C0_2", + "CLK_HROW_ER1BEG3_6", + "CLK_HROW_WW4C0_0", + "CLK_HROW_WW4A3_3", + "CLK_HROW_IMUX30_7", + "CLK_HROW_LOGIC_OUTS_B7_0", + "CLK_HROW_SW2A0_3", + "CLK_HROW_NE4BEG0_7", + "CLK_HROW_LH9_3", + "CLK_HROW_IMUX31_5", + "CLK_HROW_WW4A2_0", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN0", + "CLK_HROW_WW2A1_2", + "CLK_HROW_EE4B3_1", + "CLK_HROW_EE2A1_5", + "CLK_HROW_NE4C0_2", + "CLK_HROW_SW2A3_2", + "CLK_HROW_EE4B0_6", + "CLK_HROW_BOT_R_CK_BUFG_CASCO25", + "CLK_HROW_MONITOR_N_0", + "CLK_HROW_WL1END3_4", + "CLK_HROW_LOGIC_OUTS_B14_4", + "CLK_HROW_MONITOR_N_1", + "CLK_HROW_SE4BEG3_5", + "CLK_HROW_SE2A2_7", + "CLK_HROW_CE_INT_BOT1", + "CLK_HROW_CK_GCLK_IN_TEST23", + "CLK_HROW_EE4BEG2_7", + "CLK_HROW_IMUX21_2", + "CLK_HROW_CK_INT_0_0", + "CLK_HROW_CK_GCLK_TEST_IN14", + "CLK_HROW_BYP2_3", + "CLK_HROW_IMUX38_1", + "CLK_HROW_IMUX10_4", + "CLK_HROW_WW4B0_5", + "CLK_HROW_NW4END2_6", + "CLK_HROW_EE4C0_2", + "CLK_HROW_IMUX37_1", + "CLK_HROW_LH9_0", + "CLK_HROW_IMUX29_0", + "CLK_HROW_WW2A3_5", + "CLK_HROW_WL1END2_2", + "CLK_HROW_BYP6_6", + "CLK_HROW_CK_IN_L_OUT_TEST", + "CLK_HROW_BUFHCE_CE_L11", + "CLK_HROW_IMUX0_5", + "CLK_HROW_WW2A1_0", + "CLK_HROW_FAN5_2", + "CLK_HROW_CK_IN_L7", + "CLK_HROW_NW2A2_5", + "CLK_HROW_EE2BEG3_2", + "CLK_HROW_IMUX34_3", + "CLK_HROW_CK_GCLK_OUT_TEST16", + "CLK_HROW_NW4A3_2", + "CLK_HROW_WW4A2_1", + "CLK_HROW_WW2A1_6", + "CLK_HROW_EE2A3_6", + "CLK_HROW_IMUX46_0", + "CLK_HROW_LOGIC_OUTS_B22_4", + "CLK_HROW_CK_IN_R8", + "CLK_HROW_SE2A2_2", + "CLK_HROW_LH9_4", + "CLK_HROW_IMUX10_5", + "CLK_HROW_CK_GCLK_TEST30", + "CLK_HROW_SE2A3_2", + "CLK_HROW_CK_GCLK_IN_TEST27", + "CLK_HROW_IMUX12_1", + "CLK_HROW_IMUX7_1", + "CLK_HROW_IMUX20_5", + "CLK_HROW_IMUX24_3", + "CLK_HROW_LH11_1", + "CLK_HROW_WW4C1_7", + "CLK_HROW_IMUX47_2", + "CLK_HROW_CK_GCLK_OUT_TEST21", + "CLK_HROW_CK_GCLK_TEST31", + "CLK_HROW_ER1BEG2_0", + "CLK_HROW_BYP2_7", + "CLK_HROW_IMUX18_6", + "CLK_HROW_WW4C3_0", + "CLK_HROW_CLK0_5", + "CLK_HROW_REFCK_WESTCLK0", + "CLK_HROW_IMUX43_5", + "CLK_HROW_LH2_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCO16", + "CLK_HROW_LOGIC_OUTS_B10_5", + "CLK_HROW_CK_IN_L12", + "CLK_HROW_EE4BEG0_0", + "CLK_HROW_CK_GCLK_TEST_IN9", + "CLK_HROW_CK_GCLK_TEST_OUT12", + "CLK_HROW_EE4A2_4", + "CLK_HROW_EE4C2_5", + "CLK_HROW_CK_MUX_OUT_L1", + "CLK_HROW_WW4A2_6", + "CLK_HROW_SE2A2_4", + "CLK_HROW_NW2A1_5", + "CLK_HROW_R_CK_GCLK28", + "CLK_HROW_CK_GCLK_TEST15", + "CLK_HROW_LH9_7", + "CLK_HROW_IMUX4_7", + "CLK_HROW_CK_IN_R_IN_TEST", + "CLK_HROW_LOGIC_OUTS_B22_5", + "CLK_HROW_IMUX19_0", + "CLK_HROW_CK_GCLK_TEST22", + "CLK_HROW_NE4C1_2", + "CLK_HROW_SE4BEG0_2", + "CLK_HROW_SW4A2_4", + "CLK_HROW_SW4A2_3", + "CLK_HROW_SE2A1_0", + "CLK_HROW_SW4A3_3", + "CLK_HROW_NW4END0_4", + "CLK_HROW_IMUX38_3", + "CLK_HROW_IMUX47_4", + "CLK_HROW_LH2_7", + "CLK_HROW_LOGIC_OUTS_B2_3", + "CLK_HROW_IMUX31_2", + "CLK_HROW_EE4B0_4", + "CLK_HROW_IMUX14_7", + "CLK_HROW_WW2A0_5", + "CLK_HROW_LH3_2", + "CLK_HROW_EL1BEG3_7", + "CLK_HROW_EE2A2_6", + "CLK_HROW_LOGIC_OUTS_B4_3", + "CLK_HROW_EE4A2_7", + "CLK_HROW_WL1END0_3", + "CLK_HROW_BYP1_6", + "CLK_HROW_WW4A0_5", + "CLK_HROW_EE4B0_1", + "CLK_HROW_LOGIC_OUTS_B19_2", + "CLK_HROW_CK_GCLK_OUT_TEST23", + "CLK_HROW_NW4A2_7", + "CLK_HROW_EE2BEG0_3", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN15", + "CLK_HROW_WW4C2_7", + "CLK_HROW_SW4END2_7", + "CLK_HROW_CK_BUFHCLK_R1", + "CLK_HROW_IMUX36_0", + "CLK_HROW_BLOCK_OUTS_B2_3", + "CLK_HROW_EL1BEG3_1", + "CLK_HROW_EE4A1_6", + "CLK_HROW_BUFHCE_CE_L4", + "CLK_HROW_LH3_5", + "CLK_HROW_LOGIC_OUTS_B11_7", + "CLK_HROW_EE4BEG0_6", + "CLK_HROW_SW4A1_4", + "CLK_HROW_CK_GCLK_TEST0", + "CLK_HROW_SW4A1_5", + "CLK_HROW_IMUX28_3", + "CLK_HROW_EE2A0_4", + "CLK_HROW_IMUX6_4", + "CLK_HROW_BYP6_5", + "CLK_HROW_NE4BEG3_1", + "CLK_HROW_NE4C0_6", + "CLK_HROW_EE4C2_2", + "CLK_HROW_BLOCK_OUTS_B1_4", + "CLK_HROW_SW4END1_5", + "CLK_HROW_NE2A2_5", + "CLK_HROW_CK_IN_R7", + "CLK_HROW_IMUX0_7", + "CLK_HROW_WW4A0_3", + "CLK_HROW_IMUX45_0", + "CLK_HROW_IMUX42_5", + "CLK_HROW_CK_BUFHCLK_L1", + "CLK_HROW_WR1END3_6", + "CLK_HROW_SW4END1_7", + "CLK_HROW_MONITOR_N_7", + "CLK_HROW_CK_BUFHCLK_L8", + "CLK_HROW_EL1BEG3_0", + "CLK_HROW_SW4END1_4", + "CLK_HROW_WL1END3_1", + "CLK_HROW_IMUX17_6", + "CLK_HROW_LOGIC_OUTS_B6_2", + "CLK_HROW_SE4C3_0", + "CLK_HROW_CK_GCLK_TEST_OUT11", + "CLK_HROW_IMUX19_1", + "CLK_HROW_NE2A1_3", + "CLK_HROW_SE4C3_2", + "CLK_HROW_SW4END0_1", + "CLK_HROW_BYP0_4", + "CLK_HROW_R_CK_GCLK6", + "CLK_HROW_LOGIC_OUTS_B8_6", + "CLK_HROW_LOGIC_OUTS_B1_2", + "CLK_HROW_NE4BEG3_0", + "CLK_HROW_FAN1_2", + "CLK_HROW_WR1END0_6", + "CLK_HROW_LOGIC_OUTS_B1_1", + "CLK_HROW_WW4B3_5", + "CLK_HROW_IMUX17_5", + "CLK_HROW_CK_GCLK_IN_TEST3", + "CLK_HROW_WW4C2_6", + "CLK_HROW_NE4C3_1", + "CLK_HROW_NE2A3_2", + "CLK_HROW_BOT_R_CK_BUFG_CASCIN13", + "CLK_HROW_BYP3_3", + "CLK_HROW_WW2A2_1", + "CLK_HROW_LOGIC_OUTS_B2_4", + "CLK_HROW_SE4BEG3_4", + "CLK_HROW_FAN5_3", + "CLK_HROW_IMUX15_7", + "CLK_HROW_IMUX31_6", + "CLK_HROW_IMUX30_2", + "CLK_HROW_IMUX24_1", + "CLK_HROW_WW4C2_4", + "CLK_HROW_EE2A2_5", + "CLK_HROW_CK_GCLK_OUT_TEST7", + "CLK_HROW_LH11_4", + "CLK_HROW_EL1BEG2_0", + "CLK_HROW_BUFHCE_CE_R7", + "CLK_HROW_LOGIC_OUTS_B13_7", + "CLK_HROW_BLOCK_OUTS_B2_5", + "CLK_HROW_SE2A0_3", + "CLK_HROW_SE4BEG1_4", + "CLK_HROW_IMUX7_4", + "CLK_HROW_LOGIC_OUTS_B1_5", + "CLK_HROW_FAN0_4", + "CLK_HROW_EE4BEG3_0", + "CLK_HROW_IMUX45_6", + "CLK_HROW_IMUX11_4", + "CLK_HROW_ER1BEG2_6", + "CLK_HROW_WL1END0_6", + "CLK_HROW_WW4END3_6", + "CLK_HROW_WR1END2_7", + "CLK_HROW_CK_BUFRCLK_L1", + "CLK_HROW_IMUX2_3", + "CLK_HROW_BLOCK_OUTS_B3_6", + "CLK_HROW_CK_GCLK_IN_TEST24", + "CLK_HROW_SW4END3_2", + "CLK_HROW_NW4A3_7", + "CLK_HROW_IMUX16_2", + "CLK_HROW_MONITOR_N_6", + "CLK_HROW_SE4BEG0_7", + "CLK_HROW_SE4BEG2_1", + "CLK_HROW_CTRL0_2", + "CLK_HROW_IMUX6_3", + "CLK_HROW_FAN3_3", + "CLK_HROW_FAN1_1", + "CLK_HROW_WL1END1_5", + "CLK_HROW_EE4C1_2", + "CLK_HROW_IMUX32_0", + "CLK_HROW_NE4BEG3_5", + "CLK_HROW_CK_BUFHCLK_L3", + "CLK_HROW_EE2A1_1", + "CLK_HROW_EE2A2_3", + "CLK_HROW_NW4END2_2", + "CLK_HROW_IMUX25_6", + "CLK_HROW_FAN5_0", + "CLK_HROW_BYP5_5", + "CLK_HROW_WW2END1_7", + "CLK_HROW_ER1BEG0_0", + "CLK_HROW_LOGIC_OUTS_B6_4", + "CLK_HROW_EE4B1_0", + "CLK_HROW_NW4END2_1", + "CLK_HROW_CK_GCLK_IN_TEST26", + "CLK_HROW_R_CK_GCLK22", + "CLK_HROW_CK_MUX_OUT_R7", + "CLK_HROW_NW2A0_6", + "CLK_HROW_IMUX24_5", + "CLK_HROW_EE2A2_2", + "CLK_HROW_BYP6_7", + "CLK_HROW_LH10_7", + "CLK_HROW_IMUX9_0", + "CLK_HROW_WW4C1_4", + "CLK_HROW_EE4BEG2_0", + "CLK_HROW_IMUX5_5", + "CLK_HROW_IMUX22_6", + "CLK_HROW_IMUX14_4", + "CLK_HROW_CK_BUFHCLK_L5", + "CLK_HROW_LOGIC_OUTS_B4_5", + "CLK_HROW_FAN4_0", + "CLK_HROW_WW4B1_2", + "CLK_HROW_IMUX0_0", + "CLK_HROW_NE2A0_2", + "CLK_HROW_LOGIC_OUTS_B7_3", + "CLK_HROW_WW4END0_7", + "CLK_HROW_CK_BUFHCLK_L0", + "CLK_HROW_NE2A2_7", + "CLK_HROW_SE4BEG1_6" + ], + "tile_type": "CLK_HROW_BOT_R", + "sites": [ + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L0", + "CE": "CLK_HROW_BUFHCE_CE_L0", + "O": "CLK_HROW_CK_HCLK_OUT_L0" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L1", + "CE": "CLK_HROW_BUFHCE_CE_L1", + "O": "CLK_HROW_CK_HCLK_OUT_L1" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L2", + "CE": "CLK_HROW_BUFHCE_CE_L2", + "O": "CLK_HROW_CK_HCLK_OUT_L2" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y2", + "x_coord": 0, + "y_coord": 2 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L3", + "CE": "CLK_HROW_BUFHCE_CE_L3", + "O": "CLK_HROW_CK_HCLK_OUT_L3" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y3", + "x_coord": 0, + "y_coord": 3 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L4", + "CE": "CLK_HROW_BUFHCE_CE_L4", + "O": "CLK_HROW_CK_HCLK_OUT_L4" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y4", + "x_coord": 0, + "y_coord": 4 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L5", + "CE": "CLK_HROW_BUFHCE_CE_L5", + "O": "CLK_HROW_CK_HCLK_OUT_L5" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y5", + "x_coord": 0, + "y_coord": 5 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L6", + "CE": "CLK_HROW_BUFHCE_CE_L6", + "O": "CLK_HROW_CK_HCLK_OUT_L6" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y6", + "x_coord": 0, + "y_coord": 6 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L7", + "CE": "CLK_HROW_BUFHCE_CE_L7", + "O": "CLK_HROW_CK_HCLK_OUT_L7" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y7", + "x_coord": 0, + "y_coord": 7 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L8", + "CE": "CLK_HROW_BUFHCE_CE_L8", + "O": "CLK_HROW_CK_HCLK_OUT_L8" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y8", + "x_coord": 0, + "y_coord": 8 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L9", + "CE": "CLK_HROW_BUFHCE_CE_L9", + "O": "CLK_HROW_CK_HCLK_OUT_L9" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y9", + "x_coord": 0, + "y_coord": 9 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L10", + "CE": "CLK_HROW_BUFHCE_CE_L10", + "O": "CLK_HROW_CK_HCLK_OUT_L10" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y10", + "x_coord": 0, + "y_coord": 10 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L11", + "CE": "CLK_HROW_BUFHCE_CE_L11", + "O": "CLK_HROW_CK_HCLK_OUT_L11" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y11", + "x_coord": 0, + "y_coord": 11 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R11", + "CE": "CLK_HROW_BUFHCE_CE_R11", + "O": "CLK_HROW_CK_HCLK_OUT_R11" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y11", + "x_coord": 1, + "y_coord": 11 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R10", + "CE": "CLK_HROW_BUFHCE_CE_R10", + "O": "CLK_HROW_CK_HCLK_OUT_R10" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y10", + "x_coord": 1, + "y_coord": 10 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R9", + "CE": "CLK_HROW_BUFHCE_CE_R9", + "O": "CLK_HROW_CK_HCLK_OUT_R9" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y9", + "x_coord": 1, + "y_coord": 9 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R8", + "CE": "CLK_HROW_BUFHCE_CE_R8", + "O": "CLK_HROW_CK_HCLK_OUT_R8" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y8", + "x_coord": 1, + "y_coord": 8 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R7", + "CE": "CLK_HROW_BUFHCE_CE_R7", + "O": "CLK_HROW_CK_HCLK_OUT_R7" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y7", + "x_coord": 1, + "y_coord": 7 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R6", + "CE": "CLK_HROW_BUFHCE_CE_R6", + "O": "CLK_HROW_CK_HCLK_OUT_R6" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y6", + "x_coord": 1, + "y_coord": 6 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R5", + "CE": "CLK_HROW_BUFHCE_CE_R5", + "O": "CLK_HROW_CK_HCLK_OUT_R5" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y5", + "x_coord": 1, + "y_coord": 5 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R4", + "CE": "CLK_HROW_BUFHCE_CE_R4", + "O": "CLK_HROW_CK_HCLK_OUT_R4" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y4", + "x_coord": 1, + "y_coord": 4 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R3", + "CE": "CLK_HROW_BUFHCE_CE_R3", + "O": "CLK_HROW_CK_HCLK_OUT_R3" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y3", + "x_coord": 1, + "y_coord": 3 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R2", + "CE": "CLK_HROW_BUFHCE_CE_R2", + "O": "CLK_HROW_CK_HCLK_OUT_R2" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y2", + "x_coord": 1, + "y_coord": 2 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R1", + "CE": "CLK_HROW_BUFHCE_CE_R1", + "O": "CLK_HROW_CK_HCLK_OUT_R1" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y1", + "x_coord": 1, + "y_coord": 1 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R0", + "CE": "CLK_HROW_BUFHCE_CE_R0", + "O": "CLK_HROW_CK_HCLK_OUT_R0" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y0", + "x_coord": 1, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_HROW_TOP_R.json b/artix7/tile_type_CLK_HROW_TOP_R.json index 60217b2..e15bb66 100644 --- a/artix7/tile_type_CLK_HROW_TOP_R.json +++ b/artix7/tile_type_CLK_HROW_TOP_R.json @@ -1,22381 +1,22381 @@ { - "wires": [ - "CLK_HROW_NW4END0_6", - "CLK_HROW_IMUX37_7", - "CLK_HROW_IMUX14_1", - "CLK_HROW_WR1END3_6", - "CLK_HROW_SW4END0_2", - "CLK_HROW_EE4B1_2", - "CLK_HROW_NW4END3_4", - "CLK_HROW_WW2END2_0", - "CLK_HROW_CK_GCLK_IN_TEST14", - "CLK_HROW_LOGIC_OUTS_B4_1", - "CLK_HROW_MONITOR_P_4", - "CLK_HROW_LOGIC_OUTS_B4_4", - "CLK_HROW_LH10_6", - "CLK_HROW_CK_GCLK_OUT_TEST25", - "CLK_HROW_BYP6_2", - "CLK_HROW_R_CK_GCLK18", - "CLK_HROW_NE2A2_2", - "CLK_HROW_EE2A1_0", - "CLK_HROW_IMUX22_1", - "CLK_HROW_LOGIC_OUTS_B1_7", - "CLK_HROW_IMUX24_7", - "CLK_HROW_NE4BEG2_4", - "CLK_HROW_SW4A3_6", - "CLK_HROW_WW4A2_0", - "CLK_HROW_EE4B3_7", - "CLK_HROW_CK_GCLK_OUT_TEST31", - "CLK_HROW_BUFHCE_CE_L10", - "CLK_HROW_LOGIC_OUTS_B16_6", - "CLK_HROW_CK_BUFHCLK_R10", - "CLK_HROW_NW4A2_1", - "CLK_HROW_BLOCK_OUTS_B3_4", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_WW4END0_0", - "CLK_HROW_IMUX25_4", - "CLK_HROW_IMUX27_3", - "CLK_HROW_LH11_4", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN3", - "CLK_HROW_IMUX14_0", - "CLK_HROW_LOGIC_OUTS_B20_3", - "CLK_HROW_EE2A3_1", - "CLK_HROW_BUFHCE_CE_R0", - "CLK_HROW_SW2A2_7", - "CLK_HROW_LH12_5", - "CLK_HROW_IMUX25_2", - "CLK_HROW_CK_GCLK_TEST_OUT4", - "CLK_HROW_WW4END2_3", - "CLK_HROW_LOGIC_OUTS_B12_3", - "CLK_HROW_BYP7_3", - "CLK_HROW_IMUX13_2", - "CLK_HROW_EE2BEG1_7", - "CLK_HROW_WR1END3_3", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE2A2_3", - "CLK_HROW_SE4C0_5", - "CLK_HROW_IMUX20_3", - "CLK_HROW_CE_INT_BOT6", - "CLK_HROW_IMUX19_4", - "CLK_HROW_ER1BEG0_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN5", - "CLK_HROW_IMUX40_1", - "CLK_HROW_LOGIC_OUTS_B12_5", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_WW4C0_7", - "CLK_HROW_CK_GCLK_IN_TEST11", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_EE2BEG2_5", - "CLK_HROW_CK_IN_R_OUT_TEST", - "CLK_HROW_CLK1_3", - "CLK_HROW_IMUX22_4", - "CLK_HROW_CK_GCLK_TEST_IN29", - "CLK_HROW_IMUX9_0", - "CLK_HROW_WW2A1_3", - "CLK_HROW_IMUX43_6", - "CLK_HROW_BYP3_4", - "CLK_HROW_EE4C1_7", - "CLK_HROW_WL1END0_0", - "CLK_HROW_IMUX38_7", - "CLK_HROW_NW4END1_1", - "CLK_HROW_IMUX19_1", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_WW4B3_1", - "CLK_HROW_CK_BUFHCLK_R6", - "CLK_HROW_EE4BEG3_5", - "CLK_HROW_LOGIC_OUTS_B7_6", - "CLK_HROW_CK_GCLK_OUT_TEST18", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_FAN1_5", - "CLK_HROW_LH11_0", - "CLK_HROW_WL1END0_6", - "CLK_HROW_IMUX8_0", - "CLK_HROW_IMUX15_3", - "CLK_HROW_BUFHCE_CE_R11", - "CLK_HROW_NE4BEG3_5", - "CLK_HROW_CK_BUFHCLK_L6", - "CLK_HROW_LOGIC_OUTS_B11_5", - "CLK_HROW_CK_GCLK_IN_TEST0", - "CLK_HROW_NW4A2_2", - "CLK_HROW_BLOCK_OUTS_B2_4", - "CLK_HROW_BUFHCE_CE_L6", - "CLK_HROW_MONITOR_N_4", - "CLK_HROW_WW4B1_0", - "CLK_HROW_IMUX34_2", - "CLK_HROW_WW4END1_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_IMUX6_5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "CLK_HROW_BUFHCE_CE_L4", - "CLK_HROW_WW4END1_3", - "CLK_HROW_IMUX9_3", - "CLK_HROW_IMUX6_1", - "CLK_HROW_FAN1_1", - "CLK_HROW_BYP5_0", - "CLK_HROW_EE2A3_7", - "CLK_HROW_SE2A3_5", - "CLK_HROW_NW4END0_0", - "CLK_HROW_IMUX44_6", - "CLK_HROW_IMUX41_1", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN22", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN15", - "CLK_HROW_IMUX41_6", - "CLK_HROW_LH1_3", - "CLK_HROW_NE4C0_1", - "CLK_HROW_LH5_1", - "CLK_HROW_CE_INT_TOP5", - "CLK_HROW_SE4BEG2_5", - "CLK_HROW_CK_GCLK_TEST_OUT17", - "CLK_HROW_BUFHCE_CE_L0", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN23", - "CLK_HROW_LOGIC_OUTS_B15_1", - "CLK_HROW_SW2A3_4", - "CLK_HROW_CK_BUFHCLK_L2", - "CLK_HROW_SE2A2_7", - "CLK_HROW_WW2A0_7", - "CLK_HROW_IMUX14_5", - "CLK_HROW_LOGIC_OUTS_B13_4", - "CLK_HROW_SW2A1_4", - "CLK_HROW_IMUX28_6", - "CLK_HROW_LOGIC_OUTS_B12_4", - "CLK_HROW_WW4C2_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_IMUX25_7", - "CLK_HROW_LOGIC_OUTS_B18_6", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW4A1_7", - "CLK_HROW_SW2A0_4", - "CLK_HROW_IMUX26_4", - "CLK_HROW_WW4B1_3", - "CLK_HROW_SE2A0_3", - "CLK_HROW_NW4END3_1", - "CLK_HROW_LH5_0", - "CLK_HROW_FAN5_5", - "CLK_HROW_SE4BEG0_5", - "CLK_HROW_EL1BEG0_6", - "CLK_HROW_CK_GCLK_OUT_TEST20", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_SE4BEG1_6", - "CLK_HROW_IMUX26_1", - "CLK_HROW_IMUX14_2", - "CLK_HROW_SE4BEG2_7", - "CLK_HROW_CK_MUX_OUT_R2", - "CLK_HROW_WW4A1_1", - "CLK_HROW_IMUX2_1", - "CLK_HROW_NE2A0_3", - "CLK_HROW_LOGIC_OUTS_B23_7", - "CLK_HROW_CK_MUX_OUT_L7", - "CLK_HROW_IMUX2_7", - "CLK_HROW_NE4C3_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_IMUX29_7", - "CLK_HROW_WW4B3_6", - "CLK_HROW_CK_HCLK_OUT_L6", - "CLK_HROW_SE4BEG0_7", - "CLK_HROW_LH3_0", - "CLK_HROW_WW4END3_2", - "CLK_HROW_CK_MUX_OUT_L0", - "CLK_HROW_CK_GCLK_OUT_TEST22", - "CLK_HROW_NE4C3_0", - "CLK_HROW_LOGIC_OUTS_B1_1", - "CLK_HROW_CK_GCLK_OUT_TEST4", - "CLK_HROW_BUFHCE_CE_L11", - "CLK_HROW_IMUX11_0", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_LOGIC_OUTS_B8_7", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_IMUX3_3", - "CLK_HROW_NE4C3_5", - "CLK_HROW_EE4BEG2_4", - "CLK_HROW_IMUX5_3", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_NE4BEG1_7", - "CLK_HROW_IMUX8_1", - "CLK_HROW_LOGIC_OUTS_B16_7", - "CLK_HROW_NE2A1_2", - "CLK_HROW_LOGIC_OUTS_B7_2", - "CLK_HROW_CK_GCLK_IN_TEST31", - "CLK_HROW_LOGIC_OUTS_B20_1", - "CLK_HROW_EE4C3_5", - "CLK_HROW_CTRL1_1", - "CLK_HROW_BYP7_4", - "CLK_HROW_CK_GCLK_IN_TEST1", - "CLK_HROW_WW4END3_4", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_NE4C2_3", - "CLK_HROW_FAN5_2", - "CLK_HROW_WW4END1_7", - "CLK_HROW_CK_GCLK_TEST_OUT29", - "CLK_HROW_CE_INT_BOT1", - "CLK_HROW_CK_INT_1_1", - "CLK_HROW_EE2A3_6", - "CLK_HROW_WW4B3_0", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN18", - "CLK_HROW_NE4C0_2", - "CLK_HROW_IMUX18_5", - "CLK_HROW_IMUX44_0", - "CLK_HROW_CK_GCLK_TEST_OUT25", - "CLK_HROW_CK_GCLK_OUT_TEST16", - "CLK_HROW_FAN6_3", - "CLK_HROW_BYP5_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_IMUX36_4", - "CLK_HROW_LOGIC_OUTS_B16_5", - "CLK_HROW_NW4END1_4", - "CLK_HROW_CLK1_1", - "CLK_HROW_EE4BEG3_6", - "CLK_HROW_FAN0_5", - "CLK_HROW_CTRL0_6", - "CLK_HROW_LOGIC_OUTS_B10_3", - "CLK_HROW_EE2BEG1_4", - "CLK_HROW_EE4A0_3", - "CLK_HROW_LOGIC_OUTS_B4_6", - "CLK_HROW_R_CK_GCLK28", - "CLK_HROW_LOGIC_OUTS_B2_4", - "CLK_HROW_LOGIC_OUTS_B10_4", - "CLK_HROW_LOGIC_OUTS_B3_7", - "CLK_HROW_CK_IN_L3", - "CLK_HROW_CK_BUFRCLK_L1", - "CLK_HROW_EE4A2_7", - "CLK_HROW_BYP6_1", - "CLK_HROW_LOGIC_OUTS_B6_5", - "CLK_HROW_FAN3_1", - "CLK_HROW_WW4A2_3", - "CLK_HROW_ER1BEG2_5", - "CLK_HROW_IMUX34_0", - "CLK_HROW_LH2_7", - "CLK_HROW_WW2A1_7", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW4A1_6", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE2A3_5", - "CLK_HROW_LOGIC_OUTS_B3_2", - "CLK_HROW_IMUX40_7", - "CLK_HROW_FAN5_6", - "CLK_HROW_IMUX36_2", - "CLK_HROW_IMUX47_7", - "CLK_HROW_WR1END1_1", - "CLK_HROW_IMUX46_1", - "CLK_HROW_IMUX21_1", - "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "CLK_HROW_LH1_5", - "CLK_HROW_LOGIC_OUTS_B3_5", - "CLK_HROW_FAN4_6", - "CLK_HROW_LH6_3", - "CLK_HROW_WW4A1_3", - "CLK_HROW_IMUX47_1", - "CLK_HROW_IMUX35_0", - "CLK_HROW_SE2A3_7", - "CLK_HROW_IMUX2_4", - "CLK_HROW_IMUX17_1", - "CLK_HROW_CE_INT_BOT5", - "CLK_HROW_WW4B1_4", - "CLK_HROW_LOGIC_OUTS_B21_4", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_IMUX16_6", - "CLK_HROW_IMUX39_1", - "CLK_HROW_LOGIC_OUTS_B23_6", - "CLK_HROW_IMUX18_3", - "CLK_HROW_NW4A1_1", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_LH8_5", - "CLK_HROW_NW4A0_4", - "CLK_HROW_EL1BEG2_4", - "CLK_HROW_EL1BEG2_5", - "CLK_HROW_LOGIC_OUTS_B20_0", - "CLK_HROW_BLOCK_OUTS_B3_7", - "CLK_HROW_CK_GCLK_TEST_IN5", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE4B0_5", - "CLK_HROW_NW2A3_6", - "CLK_HROW_LOGIC_OUTS_B18_7", - "CLK_HROW_WW2A3_7", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN1", - "CLK_HROW_BYP6_6", - "CLK_HROW_EE4C3_1", - "CLK_HROW_CK_BUFRCLK_L2", - "CLK_HROW_NE2A2_0", - "CLK_HROW_CK_HCLK_OUT_R1", - "CLK_HROW_IMUX18_2", - "CLK_HROW_EL1BEG0_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "CLK_HROW_EE4A1_6", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_BYP1_5", - "CLK_HROW_EL1BEG0_4", - "CLK_HROW_BYP1_6", - "CLK_HROW_LOGIC_OUTS_B6_3", - "CLK_HROW_SE2A0_2", - "CLK_HROW_FAN4_7", - "CLK_HROW_IMUX37_1", - "CLK_HROW_LOGIC_OUTS_B9_3", - "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SW4A1_0", - "CLK_HROW_WW4B0_7", - "CLK_HROW_CE_INT_BOT2", - "CLK_HROW_BYP0_4", - "CLK_HROW_CK_GCLK_TEST_OUT28", - "CLK_HROW_FAN5_4", - "CLK_HROW_BUFHCE_CE_R9", - "CLK_HROW_IMUX5_0", - "CLK_HROW_WL1END3_7", - "CLK_HROW_EE4A3_4", - "CLK_HROW_WR1END1_7", - "CLK_HROW_R_CK_GCLK15", - "CLK_HROW_LOGIC_OUTS_B13_5", - "CLK_HROW_LOGIC_OUTS_B1_2", - "CLK_HROW_SW4END0_7", - "CLK_HROW_CTRL0_3", - "CLK_HROW_LH4_5", - "CLK_HROW_WL1END2_1", - "CLK_HROW_EE2A2_7", - "CLK_HROW_EE4B3_4", - "CLK_HROW_NE4BEG0_7", - "CLK_HROW_LOGIC_OUTS_B0_5", - "CLK_HROW_SW4A3_0", - "CLK_HROW_BYP7_2", - "CLK_HROW_CK_GCLK_IN_TEST20", - "CLK_HROW_WW4B2_7", - "CLK_HROW_WW4C1_6", - "CLK_HROW_IMUX42_2", - "CLK_HROW_BYP4_6", - "CLK_HROW_LOGIC_OUTS_B5_1", - "CLK_HROW_LOGIC_OUTS_B8_1", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CK_GCLK_TEST_OUT6", - "CLK_HROW_CK_GCLK_TEST_IN8", - "CLK_HROW_WL1END3_6", - "CLK_HROW_LH4_4", - "CLK_HROW_NW4END3_3", - "CLK_HROW_SW4A1_2", - "CLK_HROW_CK_GCLK_TEST11", - "CLK_HROW_EE4C2_4", - "CLK_HROW_LH1_0", - "CLK_HROW_IMUX37_4", - "CLK_HROW_IMUX43_7", - "CLK_HROW_CK_GCLK_TEST1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_CK_GCLK_IN_TEST2", - "CLK_HROW_SE4C3_4", - "CLK_HROW_R_CK_GCLK19", - "CLK_HROW_CK_GCLK_TEST_IN2", - "CLK_HROW_WW2A3_5", - "CLK_HROW_WR1END0_7", - "CLK_HROW_LH10_3", - "CLK_HROW_IMUX24_5", - "CLK_HROW_CK_GCLK_OUT_TEST30", - "CLK_HROW_CK_GCLK_IN_TEST21", - "CLK_HROW_WW2END0_6", - "CLK_HROW_FAN4_0", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN20", - "CLK_HROW_IMUX40_2", - "CLK_HROW_IMUX28_7", - "CLK_HROW_SE2A2_6", - "CLK_HROW_CK_BUFRCLK_R0", - "CLK_HROW_WW2END3_2", - "CLK_HROW_LH4_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_R_CK_GCLK0", - "CLK_HROW_SW2A0_3", - "CLK_HROW_LH6_0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "CLK_HROW_IMUX31_5", - "CLK_HROW_LOGIC_OUTS_B17_1", - "CLK_HROW_WW4END1_6", - "CLK_HROW_SW2A3_5", - "CLK_HROW_NW2A3_0", - "CLK_HROW_FAN3_0", - "CLK_HROW_WW4C1_3", - "CLK_HROW_NE2A2_1", - "CLK_HROW_CK_GCLK_TEST6", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_WW2END2_7", - "CLK_HROW_NW2A3_3", - "CLK_HROW_IMUX11_6", - "CLK_HROW_WL1END2_4", - "CLK_HROW_IMUX19_7", - "CLK_HROW_IMUX15_7", - "CLK_HROW_WW2A1_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_CLK1_7", - "CLK_HROW_CLK0_4", - "CLK_HROW_IMUX11_3", - "CLK_HROW_LOGIC_OUTS_B13_6", - "CLK_HROW_CK_IN_R6", - "CLK_HROW_SE4BEG0_6", - "CLK_HROW_EE4B0_3", - "CLK_HROW_CK_BUFHCLK_R1", - "CLK_HROW_CLK0_3", - "CLK_HROW_LH3_5", - "CLK_HROW_BUFHCE_CE_L3", - "CLK_HROW_SW2A3_0", - "CLK_HROW_IMUX27_1", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "CLK_HROW_CK_GCLK_OUT_TEST21", - "CLK_HROW_LOGIC_OUTS_B3_0", - "CLK_HROW_CK_MUX_OUT_R1", - "CLK_HROW_LOGIC_OUTS_B3_1", - "CLK_HROW_LH9_5", - "CLK_HROW_SE4BEG3_7", - "CLK_HROW_BYP5_5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "CLK_HROW_IMUX30_1", - "CLK_HROW_EE4C1_1", - "CLK_HROW_CK_BUFHCLK_R9", - "CLK_HROW_BYP3_1", - "CLK_HROW_WW4C3_7", - "CLK_HROW_SE2A3_2", - "CLK_HROW_EE2A2_2", - "CLK_HROW_CK_IN_L2", - "CLK_HROW_LH11_1", - "CLK_HROW_IMUX35_7", - "CLK_HROW_NE4C1_2", - "CLK_HROW_EE4B0_7", - "CLK_HROW_EE4B3_1", - "CLK_HROW_WW2A0_5", - "CLK_HROW_WW4C3_5", - "CLK_HROW_IMUX28_4", - "CLK_HROW_LH10_5", - "CLK_HROW_EE4B2_6", - "CLK_HROW_IMUX12_4", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_LH9_3", - "CLK_HROW_CK_GCLK_TEST_IN15", - "CLK_HROW_IMUX32_7", - "CLK_HROW_IMUX4_1", - "CLK_HROW_WW4C1_4", - "CLK_HROW_IMUX36_0", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_IMUX26_2", - "CLK_HROW_WW4END1_5", - "CLK_HROW_FAN3_5", - "CLK_HROW_CK_INT_0_1", - "CLK_HROW_SW2A0_6", - "CLK_HROW_SW4END3_5", - "CLK_HROW_NE2A0_6", - "CLK_HROW_CK_GCLK_IN_TEST5", - "CLK_HROW_CK_BUFHCLK_L5", - "CLK_HROW_IMUX32_6", - "CLK_HROW_IMUX40_5", - "CLK_HROW_CK_GCLK_IN_TEST10", - "CLK_HROW_EE4B2_7", - "CLK_HROW_SE4C3_6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN24", - "CLK_HROW_LOGIC_OUTS_B4_2", - "CLK_HROW_NW4A3_0", - "CLK_HROW_LOGIC_OUTS_B15_5", - "CLK_HROW_BYP4_1", - "CLK_HROW_NE2A3_1", - "CLK_HROW_R_CK_GCLK14", - "CLK_HROW_IMUX47_6", - "CLK_HROW_LOGIC_OUTS_B12_1", - "CLK_HROW_IMUX19_6", - "CLK_HROW_IMUX33_5", - "CLK_HROW_EE4A1_4", - "CLK_HROW_CK_GCLK_TEST_IN7", - "CLK_HROW_NW4END2_6", - "CLK_HROW_SW4END0_4", - "CLK_HROW_CK_BUFRCLK_L0", - "CLK_HROW_IMUX1_3", - "CLK_HROW_NW2A0_4", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_NE4BEG1_5", - "CLK_HROW_SW4END0_1", - "CLK_HROW_CK_GCLK_OUT_TEST29", - "CLK_HROW_CK_MUX_OUT_L3", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_R_CK_GCLK29", - "CLK_HROW_BYP3_0", - "CLK_HROW_CK_MUX_OUT_L10", - "CLK_HROW_CK_GCLK_TEST_IN3", - "CLK_HROW_BYP0_0", - "CLK_HROW_LH12_1", - "CLK_HROW_BUFHCE_CE_L7", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG0_5", - "CLK_HROW_SE4C1_4", - "CLK_HROW_BLOCK_OUTS_B0_7", - "CLK_HROW_BLOCK_OUTS_B3_5", - "CLK_HROW_SW4A1_5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "CLK_HROW_EE4C1_5", - "CLK_HROW_IMUX13_1", - "CLK_HROW_IMUX38_2", - "CLK_HROW_R_CK_GCLK3", - "CLK_HROW_LH8_7", - "CLK_HROW_NW2A1_5", - "CLK_HROW_CK_GCLK_TEST_OUT19", - "CLK_HROW_IMUX36_6", - "CLK_HROW_LH7_6", - "CLK_HROW_NW2A3_7", - "CLK_HROW_ER1BEG2_6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN30", - "CLK_HROW_NE4BEG3_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "CLK_HROW_WW2END1_6", - "CLK_HROW_IMUX27_4", - "CLK_HROW_SW4END2_2", - "CLK_HROW_NE2A1_4", - "CLK_HROW_LH8_6", - "CLK_HROW_CLK0_5", - "CLK_HROW_BYP2_7", - "CLK_HROW_CK_GCLK_TEST_OUT5", - "CLK_HROW_LH2_1", - "CLK_HROW_SW2A0_0", - "CLK_HROW_IMUX46_3", - "CLK_HROW_IMUX46_0", - "CLK_HROW_IMUX32_0", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_NW2A0_6", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_LH5_6", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_NE4C2_4", - "CLK_HROW_WL1END1_2", - "CLK_HROW_NW2A2_1", - "CLK_HROW_IMUX22_7", - "CLK_HROW_NE4C2_2", - "CLK_HROW_CK_GCLK_TEST_IN20", - "CLK_HROW_WR1END0_6", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_IMUX11_5", - "CLK_HROW_BYP2_4", - "CLK_HROW_IMUX18_0", - "CLK_HROW_LH6_4", - "CLK_HROW_SW4END2_4", - "CLK_HROW_CK_GCLK_TEST_IN18", - "CLK_HROW_IMUX28_1", - "CLK_HROW_CK_GCLK_TEST10", - "CLK_HROW_CK_MUX_OUT_R7", - "CLK_HROW_SW4A0_2", - "CLK_HROW_IMUX24_4", - "CLK_HROW_IMUX23_5", - "CLK_HROW_LOGIC_OUTS_B1_3", - "CLK_HROW_IMUX7_3", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_LOGIC_OUTS_B10_5", - "CLK_HROW_NE2A3_0", - "CLK_HROW_EE4C2_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "CLK_HROW_LOGIC_OUTS_B13_7", - "CLK_HROW_IMUX32_3", - "CLK_HROW_LOGIC_OUTS_B1_5", - "CLK_HROW_WL1END1_4", - "CLK_HROW_CLK0_0", - "CLK_HROW_IMUX4_6", - "CLK_HROW_NE4C1_6", - "CLK_HROW_IMUX31_1", - "CLK_HROW_LOGIC_OUTS_B14_0", - "CLK_HROW_WW4END3_1", - "CLK_HROW_BYP0_1", - "CLK_HROW_IMUX29_5", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A0_0", - "CLK_HROW_CE_INT_TOP10", - "CLK_HROW_IMUX22_2", - "CLK_HROW_BUFHCE_CE_R2", - "CLK_HROW_CK_GCLK_TEST4", - "CLK_HROW_CK_MUX_OUT_L9", - "CLK_HROW_NE2A1_3", - "CLK_HROW_LOGIC_OUTS_B7_4", - "CLK_HROW_IMUX6_2", - "CLK_HROW_WW4A0_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "CLK_HROW_IMUX24_0", - "CLK_HROW_LOGIC_OUTS_B15_6", - "CLK_HROW_IMUX21_4", - "CLK_HROW_BUFHCE_CE_L1", - "CLK_HROW_IMUX17_4", - "CLK_HROW_WW4C3_3", - "CLK_HROW_BLOCK_OUTS_B3_6", - "CLK_HROW_SE4BEG2_4", - "CLK_HROW_IMUX28_3", - "CLK_HROW_CK_MUX_OUT_R8", - "CLK_HROW_NE4C1_7", - "CLK_HROW_IMUX41_4", - "CLK_HROW_EL1BEG3_5", - "CLK_HROW_NE4C1_0", - "CLK_HROW_EL1BEG1_6", - "CLK_HROW_LOGIC_OUTS_B0_1", - "CLK_HROW_WW2A0_0", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_IMUX37_0", - "CLK_HROW_BYP7_0", - "CLK_HROW_SE4BEG3_4", - "CLK_HROW_WW4B0_4", - "CLK_HROW_CE_INT_BOT7", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_IMUX27_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_BLOCK_OUTS_B1_7", - "CLK_HROW_EE2A2_1", - "CLK_HROW_LOGIC_OUTS_B18_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN2", - "CLK_HROW_CK_GCLK_TEST_OUT18", - "CLK_HROW_NW2A1_2", - "CLK_HROW_LOGIC_OUTS_B23_1", - "CLK_HROW_WW2A3_0", - "CLK_HROW_IMUX39_4", - "CLK_HROW_SW4A1_4", - "CLK_HROW_CK_GCLK_TEST17", - "CLK_HROW_NE4C3_4", - "CLK_HROW_IMUX7_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LOGIC_OUTS_B23_3", - "CLK_HROW_CK_HCLK_OUT_L1", - "CLK_HROW_CK_GCLK_TEST_OUT3", - "CLK_HROW_CK_HCLK_OUT_L9", - "CLK_HROW_WW2A0_6", - "CLK_HROW_IMUX14_4", - "CLK_HROW_CK_BUFHCLK_R8", - "CLK_HROW_FAN2_5", - "CLK_HROW_SE2A1_2", - "CLK_HROW_WL1END3_5", - "CLK_HROW_NW4END1_7", - "CLK_HROW_BYP3_7", - "CLK_HROW_LH4_7", - "CLK_HROW_CTRL1_3", - "CLK_HROW_WW4A0_4", - "CLK_HROW_LH5_2", - "CLK_HROW_IMUX10_4", - "CLK_HROW_IMUX3_7", - "CLK_HROW_LOGIC_OUTS_B16_3", - "CLK_HROW_CTRL1_4", - "CLK_HROW_CTRL1_6", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_IMUX17_0", - "CLK_HROW_IMUX9_6", - "CLK_HROW_CK_HCLK_OUT_L11", - "CLK_HROW_WW4A2_4", - "CLK_HROW_IMUX3_1", - "CLK_HROW_EE4A0_0", - "CLK_HROW_IMUX13_0", - "CLK_HROW_LOGIC_OUTS_B18_1", - "CLK_HROW_WW4B0_3", - "CLK_HROW_LOGIC_OUTS_B9_7", - "CLK_HROW_WW2A2_5", - "CLK_HROW_SW4END0_3", - "CLK_HROW_R_CK_GCLK31", - "CLK_HROW_WW2A1_5", - "CLK_HROW_WW2END0_5", - "CLK_HROW_SE2A2_2", - "CLK_HROW_EE4C2_6", - "CLK_HROW_CK_GCLK_TEST14", - "CLK_HROW_CK_GCLK_IN_TEST16", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN7_4", - "CLK_HROW_IMUX40_4", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_IMUX10_6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN9", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_LH8_2", - "CLK_HROW_ER1BEG1_7", - "CLK_HROW_CK_IN_R1", - "CLK_HROW_IMUX31_3", - "CLK_HROW_CK_GCLK_TEST16", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4C0_0", - "CLK_HROW_CK_BUFHCLK_R2", - "CLK_HROW_CK_GCLK_IN_TEST9", - "CLK_HROW_WW2END3_6", - "CLK_HROW_CK_GCLK_TEST_IN6", - "CLK_HROW_IMUX46_4", - "CLK_HROW_CK_MUX_OUT_L8", - "CLK_HROW_WW4B3_2", - "CLK_HROW_FAN0_1", - "CLK_HROW_IMUX25_1", - "CLK_HROW_IMUX42_7", - "CLK_HROW_EE2A2_0", - "CLK_HROW_NE4BEG3_4", - "CLK_HROW_NW2A1_7", - "CLK_HROW_CK_GCLK_OUT_TEST5", - "CLK_HROW_LOGIC_OUTS_B18_5", - "CLK_HROW_WW4B3_4", - "CLK_HROW_LOGIC_OUTS_B20_4", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW4B1_1", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_IMUX15_0", - "CLK_HROW_EE4BEG2_7", - "CLK_HROW_WW4END3_7", - "CLK_HROW_NW4END1_3", - "CLK_HROW_WR1END1_3", - "CLK_HROW_CK_IN_R3", - "CLK_HROW_FAN7_0", - "CLK_HROW_NW4END0_5", - "CLK_HROW_WW4C3_1", - "CLK_HROW_FAN2_0", - "CLK_HROW_EE2BEG3_5", - "CLK_HROW_CE_INT_TOP8", - "CLK_HROW_SE2A0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_CK_GCLK_OUT_TEST3", - "CLK_HROW_R_CK_GCLK9", - "CLK_HROW_NW2A0_1", - "CLK_HROW_WW4A0_7", - "CLK_HROW_CK_GCLK_TEST25", - "CLK_HROW_BYP1_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN7", - "CLK_HROW_SW2A1_1", - "CLK_HROW_CK_GCLK_TEST_IN0", - "CLK_HROW_NW2A2_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_FAN4_4", - "CLK_HROW_SE2A1_3", - "CLK_HROW_BUFHCE_CE_R7", - "CLK_HROW_SW4END2_1", - "CLK_HROW_IMUX24_2", - "CLK_HROW_IMUX44_5", - "CLK_HROW_CK_IN_R5", - "CLK_HROW_LOGIC_OUTS_B9_6", - "CLK_HROW_SE4C2_3", - "CLK_HROW_IMUX35_5", - "CLK_HROW_IMUX42_1", - "CLK_HROW_IMUX18_1", - "CLK_HROW_LOGIC_OUTS_B4_7", - "CLK_HROW_EE4BEG2_5", - "CLK_HROW_WW4C2_1", - "CLK_HROW_SW4END1_7", - "CLK_HROW_FAN0_4", - "CLK_HROW_LOGIC_OUTS_B1_0", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_SW4A0_7", - "CLK_HROW_LOGIC_OUTS_B16_4", - "CLK_HROW_WW4B2_2", - "CLK_HROW_ER1BEG3_4", - "CLK_HROW_EE4A0_2", - "CLK_HROW_NE4C3_7", - "CLK_HROW_LH12_2", - "CLK_HROW_IMUX23_6", - "CLK_HROW_EE4B2_0", - "CLK_HROW_CK_INT_0_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_NE4BEG1_6", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_LH7_3", - "CLK_HROW_CK_IN_L11", - "CLK_HROW_FAN7_7", - "CLK_HROW_EE4BEG3_7", - "CLK_HROW_FAN6_2", - "CLK_HROW_BYP0_5", - "CLK_HROW_WW4C2_7", - "CLK_HROW_LH10_1", - "CLK_HROW_NE4C2_5", - "CLK_HROW_FAN7_1", - "CLK_HROW_BYP6_0", - "CLK_HROW_LOGIC_OUTS_B0_6", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_NE2A3_5", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP0_6", - "CLK_HROW_SW4END1_1", - "CLK_HROW_WL1END3_3", - "CLK_HROW_CK_GCLK_TEST19", - "CLK_HROW_IMUX29_1", - "CLK_HROW_WW2END0_1", - "CLK_HROW_IMUX17_6", - "CLK_HROW_EE4C2_5", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE2BEG0_5", - "CLK_HROW_CK_GCLK_OUT_TEST12", - "CLK_HROW_EE2BEG3_7", - "CLK_HROW_CK_GCLK_TEST_OUT20", - "CLK_HROW_EE2A0_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "CLK_HROW_EE4A2_4", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_IMUX46_7", - "CLK_HROW_IMUX38_1", - "CLK_HROW_CK_IN_R9", - "CLK_HROW_CLK1_6", - "CLK_HROW_CK_IN_L13", - "CLK_HROW_R_CK_GCLK17", - "CLK_HROW_IMUX39_2", - "CLK_HROW_WR1END3_2", - "CLK_HROW_NE4BEG0_6", - "CLK_HROW_CK_GCLK_TEST18", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN13", - "CLK_HROW_WR1END1_6", - "CLK_HROW_SE2A2_3", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_LOGIC_OUTS_B19_4", - "CLK_HROW_LOGIC_OUTS_B6_6", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_IMUX30_2", - "CLK_HROW_SW4END0_6", - "CLK_HROW_FAN5_0", - "CLK_HROW_CE_INT_TOP9", - "CLK_HROW_SW4A1_7", - "CLK_HROW_CK_GCLK_TEST_OUT13", - "CLK_HROW_SE2A2_0", - "CLK_HROW_IMUX12_7", - "CLK_HROW_CK_GCLK_TEST30", - "CLK_HROW_LOGIC_OUTS_B14_7", - "CLK_HROW_EE4BEG1_4", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_SW4A3_2", - "CLK_HROW_IMUX7_5", - "CLK_HROW_CK_MUX_OUT_R0", - "CLK_HROW_IMUX33_6", - "CLK_HROW_WR1END0_5", - "CLK_HROW_NW4A3_1", - "CLK_HROW_SE4C1_1", - "CLK_HROW_EE2A2_6", - "CLK_HROW_IMUX42_4", - "CLK_HROW_IMUX23_4", - "CLK_HROW_NE4C0_6", - "CLK_HROW_LH3_1", - "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "CLK_HROW_NW4A0_3", - "CLK_HROW_LOGIC_OUTS_B2_2", - "CLK_HROW_WW4A0_5", - "CLK_HROW_CK_GCLK_TEST_IN10", - "CLK_HROW_SW4END1_5", - "CLK_HROW_MONITOR_P_7", - "CLK_HROW_IMUX26_0", - "CLK_HROW_WW4C3_6", - "CLK_HROW_IMUX16_0", - "CLK_HROW_IMUX42_6", - "CLK_HROW_IMUX19_3", - "CLK_HROW_LOGIC_OUTS_B19_2", - "CLK_HROW_CTRL1_5", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW2END0_7", - "CLK_HROW_LH7_0", - "CLK_HROW_FAN0_0", - "CLK_HROW_WL1END1_5", - "CLK_HROW_R_CK_GCLK2", - "CLK_HROW_LOGIC_OUTS_B6_0", - "CLK_HROW_EE4B1_5", - "CLK_HROW_LOGIC_OUTS_B12_0", - "CLK_HROW_IMUX2_6", - "CLK_HROW_ER1BEG2_7", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_7", - "CLK_HROW_NW4END0_4", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_SE4C2_0", - "CLK_HROW_NE4BEG2_7", - "CLK_HROW_WW4A0_3", - "CLK_HROW_ER1BEG1_6", - "CLK_HROW_EE4B0_2", - "CLK_HROW_LH6_1", - "CLK_HROW_EL1BEG3_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "CLK_HROW_FAN3_4", - "CLK_HROW_NE4C3_6", - "CLK_HROW_BYP7_1", - "CLK_HROW_CK_MUX_OUT_L1", - "CLK_HROW_EE4BEG3_4", - "CLK_HROW_CK_GCLK_TEST20", - "CLK_HROW_IMUX21_7", - "CLK_HROW_LOGIC_OUTS_B7_1", - "CLK_HROW_LH3_4", - "CLK_HROW_CK_GCLK_TEST_OUT7", - "CLK_HROW_IMUX7_7", - "CLK_HROW_CK_HCLK_OUT_L7", - "CLK_HROW_EE2A0_0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "CLK_HROW_WL1END2_0", - "CLK_HROW_IMUX20_5", - "CLK_HROW_LOGIC_OUTS_B8_3", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_IMUX28_5", - "CLK_HROW_LH12_4", - "CLK_HROW_WR1END3_4", - "CLK_HROW_WW4C1_7", - "CLK_HROW_LOGIC_OUTS_B21_2", - "CLK_HROW_CK_GCLK_TEST_OUT9", - "CLK_HROW_NE4C1_3", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4A3_3", - "CLK_HROW_NE2A1_7", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_SW2A3_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "CLK_HROW_CK_GCLK_TEST_OUT11", - "CLK_HROW_LH2_3", - "CLK_HROW_IMUX5_7", - "CLK_HROW_LH10_0", - "CLK_HROW_IMUX30_5", - "CLK_HROW_LOGIC_OUTS_B18_3", - "CLK_HROW_IMUX32_4", - "CLK_HROW_CK_MUX_OUT_R5", - "CLK_HROW_SW2A1_2", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_NW4END2_0", - "CLK_HROW_WW2A1_4", - "CLK_HROW_IMUX45_1", - "CLK_HROW_CK_HCLK_OUT_R5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN14", - "CLK_HROW_EE4C0_1", - "CLK_HROW_WR1END2_4", - "CLK_HROW_WR1END0_1", - "CLK_HROW_SE2A2_4", - "CLK_HROW_SE4C1_7", - "CLK_HROW_NW4END1_2", - "CLK_HROW_LOGIC_OUTS_B11_0", - "CLK_HROW_R_CK_GCLK25", - "CLK_HROW_SW2A2_2", - "CLK_HROW_WW2END0_0", - "CLK_HROW_SE4C0_7", - "CLK_HROW_LOGIC_OUTS_B2_0", - "CLK_HROW_IMUX26_3", - "CLK_HROW_BUFHCE_CE_R1", - "CLK_HROW_NE4C1_4", - "CLK_HROW_LOGIC_OUTS_B23_0", - "CLK_HROW_NE2A2_5", - "CLK_HROW_IMUX35_4", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW2END1_7", - "CLK_HROW_LH3_3", - "CLK_HROW_CTRL1_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_LOGIC_OUTS_B19_0", - "CLK_HROW_NE2A2_6", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_CK_GCLK_TEST9", - "CLK_HROW_NE2A3_2", - "CLK_HROW_WW4B0_2", - "CLK_HROW_IMUX8_2", - "CLK_HROW_LH11_2", - "CLK_HROW_NE4BEG2_5", - "CLK_HROW_NW4END3_5", - "CLK_HROW_BLOCK_OUTS_B1_5", - "CLK_HROW_LOGIC_OUTS_B21_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_SE4C3_0", - "CLK_HROW_IMUX21_2", - "CLK_HROW_SE4C1_5", - "CLK_HROW_CK_GCLK_IN_TEST29", - "CLK_HROW_EE2A0_5", - "CLK_HROW_LOGIC_OUTS_B21_3", - "CLK_HROW_REFCK_EASTCLK1", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN31", - "CLK_HROW_IMUX6_4", - "CLK_HROW_CK_GCLK_TEST_IN1", - "CLK_HROW_NE2A3_6", - "CLK_HROW_NW4A0_0", - "CLK_HROW_CE_INT_TOP2", - "CLK_HROW_IMUX29_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_IMUX11_7", - "CLK_HROW_IMUX22_6", - "CLK_HROW_SE4C0_6", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_IMUX38_6", - "CLK_HROW_SE2A1_6", - "CLK_HROW_REFCK_EASTCLK0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "CLK_HROW_CK_MUX_OUT_L6", - "CLK_HROW_WW4C0_3", - "CLK_HROW_IMUX8_6", - "CLK_HROW_IMUX34_1", - "CLK_HROW_WR1END3_5", - "CLK_HROW_LOGIC_OUTS_B9_5", - "CLK_HROW_CK_GCLK_TEST12", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_1", - "CLK_HROW_MONITOR_N_7", - "CLK_HROW_SW2A3_1", - "CLK_HROW_IMUX9_2", - "CLK_HROW_LH8_3", - "CLK_HROW_CK_GCLK_IN_TEST3", - "CLK_HROW_BYP3_3", - "CLK_HROW_LH9_2", - "CLK_HROW_EE2A1_2", - "CLK_HROW_CK_GCLK_IN_TEST24", - "CLK_HROW_BYP4_7", - "CLK_HROW_LH2_2", - "CLK_HROW_IMUX2_2", - "CLK_HROW_SW4END1_2", - "CLK_HROW_NW2A1_4", - "CLK_HROW_IMUX2_5", - "CLK_HROW_IMUX10_1", - "CLK_HROW_EE4B2_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_FAN5_7", - "CLK_HROW_IMUX38_4", - "CLK_HROW_LOGIC_OUTS_B16_2", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WW4B1_6", - "CLK_HROW_BLOCK_OUTS_B0_5", - "CLK_HROW_EE4A2_0", - "CLK_HROW_IMUX16_7", - "CLK_HROW_WW4B1_7", - "CLK_HROW_WL1END2_7", - "CLK_HROW_EE4BEG1_5", - "CLK_HROW_SW4A0_5", - "CLK_HROW_EE4C2_7", - "CLK_HROW_IMUX39_0", - "CLK_HROW_CLK0_6", - "CLK_HROW_CK_GCLK_TEST0", - "CLK_HROW_CK_HCLK_OUT_L2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN25", - "CLK_HROW_LH10_2", - "CLK_HROW_CK_BUFRCLK_R1", - "CLK_HROW_WW4A3_0", - "CLK_HROW_CE_INT_TOP11", - "CLK_HROW_IMUX22_3", - "CLK_HROW_CK_IN_L12", - "CLK_HROW_WW4B0_5", - "CLK_HROW_CK_GCLK_TEST_OUT22", - "CLK_HROW_CK_BUFHCLK_L4", - "CLK_HROW_IMUX10_3", - "CLK_HROW_WW4A1_7", - "CLK_HROW_CK_HCLK_OUT_L5", - "CLK_HROW_IMUX1_4", - "CLK_HROW_LH11_7", - "CLK_HROW_LOGIC_OUTS_B22_4", - "CLK_HROW_CTRL0_7", - "CLK_HROW_EE4C3_2", - "CLK_HROW_CE_INT_TOP6", - "CLK_HROW_CK_MUX_OUT_R11", - "CLK_HROW_NE4BEG0_4", - "CLK_HROW_SW2A2_4", - "CLK_HROW_IMUX6_0", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_BLOCK_OUTS_B2_7", - "CLK_HROW_BLOCK_OUTS_B0_6", - "CLK_HROW_IMUX23_0", - "CLK_HROW_BYP7_7", - "CLK_HROW_CK_GCLK_IN_TEST8", - "CLK_HROW_IMUX25_3", - "CLK_HROW_SE4C1_6", - "CLK_HROW_LOGIC_OUTS_B6_1", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN6", - "CLK_HROW_CK_GCLK_OUT_TEST19", - "CLK_HROW_IMUX25_6", - "CLK_HROW_IMUX5_4", - "CLK_HROW_EE2A2_4", - "CLK_HROW_IMUX13_6", - "CLK_HROW_R_CK_GCLK30", - "CLK_HROW_CK_IN_L_OUT_TEST", - "CLK_HROW_SE4C1_3", - "CLK_HROW_LOGIC_OUTS_B4_3", - "CLK_HROW_R_CK_GCLK4", - "CLK_HROW_ER1BEG1_4", - "CLK_HROW_SE2A3_1", - "CLK_HROW_IMUX15_2", - "CLK_HROW_IMUX31_6", - "CLK_HROW_IMUX4_2", - "CLK_HROW_IMUX30_0", - "CLK_HROW_LOGIC_OUTS_B21_7", - "CLK_HROW_LOGIC_OUTS_B12_2", - "CLK_HROW_LOGIC_OUTS_B11_3", - "CLK_HROW_IMUX14_7", - "CLK_HROW_NW4A3_3", - "CLK_HROW_LOGIC_OUTS_B14_3", - "CLK_HROW_SE2A1_0", - "CLK_HROW_EE4C2_0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "CLK_HROW_IMUX45_7", - "CLK_HROW_WL1END1_0", - "CLK_HROW_IMUX19_2", - "CLK_HROW_CK_GCLK_TEST_IN13", - "CLK_HROW_WW4C2_6", - "CLK_HROW_CK_BUFHCLK_R5", - "CLK_HROW_CK_GCLK_TEST_OUT1", - "CLK_HROW_NW2A1_0", - "CLK_HROW_IMUX29_2", - "CLK_HROW_CK_GCLK_TEST_OUT0", - "CLK_HROW_IMUX11_4", - "CLK_HROW_NW4END2_1", - "CLK_HROW_CK_BUFHCLK_R0", - "CLK_HROW_LOGIC_OUTS_B22_6", - "CLK_HROW_SE2A0_7", - "CLK_HROW_SE4BEG1_5", - "CLK_HROW_IMUX13_7", - "CLK_HROW_LOGIC_OUTS_B17_3", - "CLK_HROW_CK_BUFHCLK_L8", - "CLK_HROW_EE2A3_2", - "CLK_HROW_CK_BUFHCLK_L1", - "CLK_HROW_IMUX1_6", - "CLK_HROW_LOGIC_OUTS_B22_3", - "CLK_HROW_LOGIC_OUTS_B5_2", - "CLK_HROW_CK_GCLK_TEST_OUT31", - "CLK_HROW_CK_IN_R13", - "CLK_HROW_CE_INT_BOT0", - "CLK_HROW_EE4B3_0", - "CLK_HROW_LOGIC_OUTS_B5_7", - "CLK_HROW_NW4A1_6", - "CLK_HROW_SE2A2_5", - "CLK_HROW_SW4END1_0", - "CLK_HROW_LOGIC_OUTS_B20_5", - "CLK_HROW_SE2A1_7", - "CLK_HROW_NW4END2_2", - "CLK_HROW_IMUX3_5", - "CLK_HROW_CK_GCLK_TEST_IN19", - "CLK_HROW_WW4C3_2", - "CLK_HROW_IMUX34_7", - "CLK_HROW_IMUX31_0", - "CLK_HROW_IMUX36_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN12", - "CLK_HROW_IMUX42_5", - "CLK_HROW_LOGIC_OUTS_B8_2", - "CLK_HROW_IMUX34_6", - "CLK_HROW_IMUX47_3", - "CLK_HROW_IMUX41_7", - "CLK_HROW_LOGIC_OUTS_B21_6", - "CLK_HROW_LOGIC_OUTS_B14_4", - "CLK_HROW_LOGIC_OUTS_B17_0", - "CLK_HROW_CK_GCLK_OUT_TEST23", - "CLK_HROW_SE2A3_6", - "CLK_HROW_LOGIC_OUTS_B14_2", - "CLK_HROW_IMUX43_0", - "CLK_HROW_BYP2_5", - "CLK_HROW_WL1END2_2", - "CLK_HROW_IMUX29_4", - "CLK_HROW_EE2A0_6", - "CLK_HROW_CK_GCLK_TEST_IN23", - "CLK_HROW_IMUX29_6", - "CLK_HROW_CK_GCLK_TEST_IN4", - "CLK_HROW_IMUX2_0", - "CLK_HROW_LOGIC_OUTS_B7_7", - "CLK_HROW_NE2A1_6", - "CLK_HROW_LH6_7", - "CLK_HROW_WW4END0_3", - "CLK_HROW_IMUX22_5", - "CLK_HROW_IMUX9_5", - "CLK_HROW_IMUX32_5", - "CLK_HROW_NE4C2_0", - "CLK_HROW_CK_HCLK_OUT_R8", - "CLK_HROW_EE4BEG0_5", - "CLK_HROW_SW4A2_5", - "CLK_HROW_EE4C3_7", - "CLK_HROW_BYP7_6", - "CLK_HROW_EE4B1_7", - "CLK_HROW_WW4C2_4", - "CLK_HROW_WW4END0_7", - "CLK_HROW_CK_GCLK_IN_TEST6", - "CLK_HROW_LOGIC_OUTS_B20_7", - "CLK_HROW_CK_GCLK_OUT_TEST8", - "CLK_HROW_FAN1_7", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_CK_GCLK_TEST28", - "CLK_HROW_NW4END1_5", - "CLK_HROW_IMUX19_0", - "CLK_HROW_CK_GCLK_OUT_TEST27", - "CLK_HROW_WL1END0_2", - "CLK_HROW_EL1BEG3_6", - "CLK_HROW_IMUX6_6", - "CLK_HROW_IMUX43_4", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_IMUX27_0", - "CLK_HROW_LOGIC_OUTS_B2_5", - "CLK_HROW_LOGIC_OUTS_B13_3", - "CLK_HROW_WW2END1_3", - "CLK_HROW_LOGIC_OUTS_B4_5", - "CLK_HROW_LOGIC_OUTS_B8_4", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4A2_6", - "CLK_HROW_IMUX7_1", - "CLK_HROW_IMUX42_3", - "CLK_HROW_LOGIC_OUTS_B2_6", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WR1END2_0", - "CLK_HROW_IMUX16_2", - "CLK_HROW_BYP1_1", - "CLK_HROW_LOGIC_OUTS_B9_0", - "CLK_HROW_IMUX10_7", - "CLK_HROW_R_CK_GCLK5", - "CLK_HROW_WW4C2_3", - "CLK_HROW_IMUX17_2", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_WL1END3_4", - "CLK_HROW_LOGIC_OUTS_B23_5", - "CLK_HROW_WW2END1_2", - "CLK_HROW_SE4C2_1", - "CLK_HROW_WL1END0_1", - "CLK_HROW_IMUX0_7", - "CLK_HROW_IMUX33_7", - "CLK_HROW_IMUX20_0", - "CLK_HROW_SW4END2_0", - "CLK_HROW_EE4A2_6", - "CLK_HROW_CK_MUX_OUT_R6", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_IMUX15_4", - "CLK_HROW_LOGIC_OUTS_B17_6", - "CLK_HROW_WW4B3_3", - "CLK_HROW_LOGIC_OUTS_B15_2", - "CLK_HROW_LH4_1", - "CLK_HROW_CK_GCLK_IN_TEST4", - "CLK_HROW_SW4A1_6", - "CLK_HROW_WW2A2_6", - "CLK_HROW_SE4BEG2_6", - "CLK_HROW_WW4A2_5", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN1_4", - "CLK_HROW_LH12_6", - "CLK_HROW_CK_IN_R4", - "CLK_HROW_NE4C0_5", - "CLK_HROW_IMUX41_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "CLK_HROW_NW2A0_5", - "CLK_HROW_IMUX46_5", - "CLK_HROW_SW4A3_4", - "CLK_HROW_SW4END3_0", - "CLK_HROW_CTRL0_4", - "CLK_HROW_LOGIC_OUTS_B15_7", - "CLK_HROW_NW4A1_3", - "CLK_HROW_LH11_5", - "CLK_HROW_CK_HCLK_OUT_R11", - "CLK_HROW_IMUX0_0", - "CLK_HROW_LOGIC_OUTS_B7_0", - "CLK_HROW_LOGIC_OUTS_B17_7", - "CLK_HROW_R_CK_GCLK8", - "CLK_HROW_NW4END3_6", - "CLK_HROW_SE4BEG1_7", - "CLK_HROW_SW2A2_6", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_EL1BEG1_4", - "CLK_HROW_NW4A0_7", - "CLK_HROW_LOGIC_OUTS_B19_6", - "CLK_HROW_FAN5_1", - "CLK_HROW_ER1BEG0_5", - "CLK_HROW_SW4A0_4", - "CLK_HROW_CK_IN_L_TEST_OUT", - "CLK_HROW_SW4END1_3", - "CLK_HROW_CK_INT_1_0", - "CLK_HROW_BLOCK_OUTS_B2_5", - "CLK_HROW_NE4C0_4", - "CLK_HROW_WW4B2_4", - "CLK_HROW_EE4A1_3", - "CLK_HROW_FAN6_1", - "CLK_HROW_EE4C3_0", - "CLK_HROW_BYP1_0", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_BYP1_4", - "CLK_HROW_BUFHCE_CE_R6", - "CLK_HROW_EE4A3_1", - "CLK_HROW_NW4END1_6", - "CLK_HROW_EE2BEG2_4", - "CLK_HROW_IMUX13_5", - "CLK_HROW_CK_BUFHCLK_L0", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_CK_GCLK_TEST5", - "CLK_HROW_LH2_6", - "CLK_HROW_LOGIC_OUTS_B9_4", - "CLK_HROW_WW4END0_5", - "CLK_HROW_WW4C3_4", - "CLK_HROW_IMUX30_3", - "CLK_HROW_IMUX40_0", - "CLK_HROW_IMUX31_4", - "CLK_HROW_EL1BEG2_6", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE2BEG2_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "CLK_HROW_IMUX9_1", - "CLK_HROW_WW4B1_5", - "CLK_HROW_IMUX13_3", - "CLK_HROW_LOGIC_OUTS_B0_2", - "CLK_HROW_LH3_6", - "CLK_HROW_WW2END2_5", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_IMUX18_6", - "CLK_HROW_WL1END0_7", - "CLK_HROW_SW4A0_6", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_FAN7_3", - "CLK_HROW_IMUX31_7", - "CLK_HROW_WW4B0_0", - "CLK_HROW_BLOCK_OUTS_B1_6", - "CLK_HROW_IMUX29_3", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NE2A0_1", - "CLK_HROW_BUFHCE_CE_R10", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_FAN3_6", - "CLK_HROW_EE2A3_3", - "CLK_HROW_SW4END2_3", - "CLK_HROW_LH1_1", - "CLK_HROW_MONITOR_P_6", - "CLK_HROW_WL1END3_1", - "CLK_HROW_LH4_6", - "CLK_HROW_WW4C1_0", - "CLK_HROW_IMUX24_1", - "CLK_HROW_CK_MUX_OUT_R4", - "CLK_HROW_CK_GCLK_IN_TEST22", - "CLK_HROW_BYP6_7", - "CLK_HROW_EE4A1_0", - "CLK_HROW_CK_GCLK_OUT_TEST13", - "CLK_HROW_R_CK_GCLK12", - "CLK_HROW_NE4C2_7", - "CLK_HROW_IMUX31_2", - "CLK_HROW_CK_GCLK_OUT_TEST11", - "CLK_HROW_LOGIC_OUTS_B0_3", - "CLK_HROW_WW4END0_4", - "CLK_HROW_IMUX25_0", - "CLK_HROW_NE2A2_4", - "CLK_HROW_BUFHCE_CE_L8", - "CLK_HROW_EE4C1_4", - "CLK_HROW_WW2A3_3", - "CLK_HROW_LOGIC_OUTS_B9_2", - "CLK_HROW_CLK0_7", - "CLK_HROW_NW4A2_5", - "CLK_HROW_CK_GCLK_TEST_IN27", - "CLK_HROW_CK_GCLK_OUT_TEST28", - "CLK_HROW_IMUX0_1", - "CLK_HROW_IMUX27_6", - "CLK_HROW_CK_GCLK_OUT_TEST7", - "CLK_HROW_NE4BEG3_6", - "CLK_HROW_IMUX15_5", - "CLK_HROW_LOGIC_OUTS_B19_7", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_NW2A2_6", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_SW4A0_0", - "CLK_HROW_LH9_1", - "CLK_HROW_FAN0_6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN8", - "CLK_HROW_IMUX22_0", - "CLK_HROW_LH1_2", - "CLK_HROW_IMUX23_3", - "CLK_HROW_LOGIC_OUTS_B5_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_WW4B2_0", - "CLK_HROW_IMUX35_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WW4B3_7", - "CLK_HROW_NE2A0_4", - "CLK_HROW_SW4A2_6", - "CLK_HROW_SW2A0_7", - "CLK_HROW_EE4A3_7", - "CLK_HROW_IMUX21_6", - "CLK_HROW_IMUX45_2", - "CLK_HROW_EL1BEG1_7", - "CLK_HROW_IMUX41_0", - "CLK_HROW_EE4C3_4", - "CLK_HROW_CK_GCLK_TEST_IN22", - "CLK_HROW_SW2A3_3", - "CLK_HROW_LH9_4", - "CLK_HROW_LOGIC_OUTS_B7_3", - "CLK_HROW_IMUX10_5", - "CLK_HROW_ER1BEG3_6", - "CLK_HROW_SW2A1_7", - "CLK_HROW_BYP3_5", - "CLK_HROW_IMUX20_7", - "CLK_HROW_FAN0_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN0", - "CLK_HROW_EE2A3_4", - "CLK_HROW_IMUX17_7", - "CLK_HROW_FAN0_7", - "CLK_HROW_NE4C0_3", - "CLK_HROW_CLK0_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN4", - "CLK_HROW_ER1BEG3_7", - "CLK_HROW_IMUX44_3", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_IMUX12_6", - "CLK_HROW_EE4C0_6", - "CLK_HROW_CK_GCLK_TEST27", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WR1END2_6", - "CLK_HROW_LOGIC_OUTS_B15_4", - "CLK_HROW_LH7_4", - "CLK_HROW_LOGIC_OUTS_B22_0", - "CLK_HROW_R_CK_GCLK21", - "CLK_HROW_CK_GCLK_TEST31", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_LH9_7", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_IMUX16_4", - "CLK_HROW_ER1BEG3_5", - "CLK_HROW_SW4END1_4", - "CLK_HROW_IMUX21_0", - "CLK_HROW_LOGIC_OUTS_B3_4", - "CLK_HROW_IMUX11_2", - "CLK_HROW_EE4A1_1", - "CLK_HROW_CK_GCLK_TEST_IN21", - "CLK_HROW_CE_INT_TOP7", - "CLK_HROW_IMUX39_6", - "CLK_HROW_LH1_4", - "CLK_HROW_SW4A3_3", - "CLK_HROW_IMUX36_3", - "CLK_HROW_WW4A3_6", - "CLK_HROW_EE4BEG0_7", - "CLK_HROW_LH3_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_LH6_5", - "CLK_HROW_EL1BEG1_5", - "CLK_HROW_EE2BEG3_6", - "CLK_HROW_LH5_3", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WW4C0_6", - "CLK_HROW_CK_GCLK_IN_TEST13", - "CLK_HROW_FAN3_7", - "CLK_HROW_IMUX8_7", - "CLK_HROW_MONITOR_N_5", - "CLK_HROW_SW4A1_3", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN16", - "CLK_HROW_LH5_7", - "CLK_HROW_LOGIC_OUTS_B0_7", - "CLK_HROW_CK_MUX_OUT_L4", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_CE_INT_BOT4", - "CLK_HROW_CK_IN_L9", - "CLK_HROW_WW4C1_2", - "CLK_HROW_BYP5_4", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_SW2A3_6", - "CLK_HROW_LOGIC_OUTS_B6_4", - "CLK_HROW_EE2A1_6", - "CLK_HROW_IMUX28_0", - "CLK_HROW_EE4A1_2", - "CLK_HROW_WW2END3_4", - "CLK_HROW_IMUX37_5", - "CLK_HROW_CK_IN_R_IN_TEST", - "CLK_HROW_LOGIC_OUTS_B17_5", - "CLK_HROW_NE2A2_7", - "CLK_HROW_LOGIC_OUTS_B19_3", - "CLK_HROW_WW2A2_2", - "CLK_HROW_FAN1_6", - "CLK_HROW_REFCK_WESTCLK1", - "CLK_HROW_SE4BEG3_5", - "CLK_HROW_WW4B0_6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN10", - "CLK_HROW_BYP5_7", - "CLK_HROW_CK_HCLK_OUT_L8", - "CLK_HROW_EL1BEG3_4", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN11", - "CLK_HROW_LH8_0", - "CLK_HROW_CLK1_4", - "CLK_HROW_FAN2_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "CLK_HROW_LH12_3", - "CLK_HROW_EE4A3_6", - "CLK_HROW_EE4A3_0", - "CLK_HROW_NE2A3_4", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_LOGIC_OUTS_B13_0", - "CLK_HROW_CK_IN_R2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_WW4END0_2", - "CLK_HROW_NE2A1_5", - "CLK_HROW_CK_GCLK_TEST2", - "CLK_HROW_WW2END2_6", - "CLK_HROW_LH8_4", - "CLK_HROW_SE4C2_7", - "CLK_HROW_CK_IN_R_TEST_OUT", - "CLK_HROW_CK_GCLK_TEST_OUT30", - "CLK_HROW_LOGIC_OUTS_B23_4", - "CLK_HROW_FAN6_0", - "CLK_HROW_SW4END3_1", - "CLK_HROW_LOGIC_OUTS_B22_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "CLK_HROW_CK_GCLK_TEST24", - "CLK_HROW_CK_BUFRCLK_R3", - "CLK_HROW_WW2END3_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_EE2BEG0_4", - "CLK_HROW_IMUX25_5", - "CLK_HROW_NE4C3_1", - "CLK_HROW_IMUX4_7", - "CLK_HROW_EE2A2_5", - "CLK_HROW_NW4END1_0", - "CLK_HROW_CE_INT_TOP4", - "CLK_HROW_CK_GCLK_TEST_OUT16", - "CLK_HROW_IMUX47_4", - "CLK_HROW_CK_GCLK_IN_TEST28", - "CLK_HROW_CK_IN_L_IN_TEST", - "CLK_HROW_LOGIC_OUTS_B22_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_EE4BEG2_6", - "CLK_HROW_BUFHCE_CE_R8", - "CLK_HROW_SW4END2_7", - "CLK_HROW_IMUX3_2", - "CLK_HROW_NW2A2_4", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_WW4A3_1", - "CLK_HROW_CK_HCLK_OUT_R0", - "CLK_HROW_IMUX5_1", - "CLK_HROW_WL1END1_6", - "CLK_HROW_BYP5_2", - "CLK_HROW_CK_GCLK_TEST_IN17", - "CLK_HROW_EE2BEG0_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN19", - "CLK_HROW_CK_GCLK_TEST_OUT12", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_CE_INT_BOT10", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_FAN2_3", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_BYP5_6", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_LOGIC_OUTS_B10_7", - "CLK_HROW_NE4C1_1", - "CLK_HROW_CK_GCLK_IN_TEST30", - "CLK_HROW_FAN2_2", - "CLK_HROW_CK_GCLK_OUT_TEST14", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_LH10_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "CLK_HROW_SW2A0_2", - "CLK_HROW_EE2BEG3_4", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN17", - "CLK_HROW_IMUX44_7", - "CLK_HROW_LH7_1", - "CLK_HROW_SE4BEG3_6", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EE4A0_5", - "CLK_HROW_WW4END1_0", - "CLK_HROW_R_CK_GCLK6", - "CLK_HROW_SE4BEG0_4", - "CLK_HROW_IMUX27_5", - "CLK_HROW_LOGIC_OUTS_B16_1", - "CLK_HROW_SW4END3_3", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_BYP1_3", - "CLK_HROW_LOGIC_OUTS_B19_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_CK_BUFHCLK_L3", - "CLK_HROW_NE2A0_0", - "CLK_HROW_CK_BUFHCLK_L11", - "CLK_HROW_NE2A1_1", - "CLK_HROW_BUFHCE_CE_L5", - "CLK_HROW_LOGIC_OUTS_B12_6", - "CLK_HROW_CK_GCLK_OUT_TEST9", - "CLK_HROW_NW2A2_3", - "CLK_HROW_WW4END2_5", - "CLK_HROW_SW4A3_1", - "CLK_HROW_IMUX39_3", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_WW2A3_1", - "CLK_HROW_IMUX3_6", - "CLK_HROW_R_CK_GCLK13", - "CLK_HROW_LOGIC_OUTS_B14_5", - "CLK_HROW_WR1END0_3", - "CLK_HROW_NW2A2_7", - "CLK_HROW_WW2END1_5", - "CLK_HROW_SW2A2_5", - "CLK_HROW_LOGIC_OUTS_B0_4", - "CLK_HROW_LH5_4", - "CLK_HROW_IMUX34_3", - "CLK_HROW_CK_BUFHCLK_R3", - "CLK_HROW_CK_IN_L5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "CLK_HROW_CK_GCLK_OUT_TEST26", - "CLK_HROW_LOGIC_OUTS_B14_6", - "CLK_HROW_IMUX12_3", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_LOGIC_OUTS_B2_1", - "CLK_HROW_SW2A1_0", - "CLK_HROW_CK_IN_R12", - "CLK_HROW_CK_GCLK_TEST8", - "CLK_HROW_SW4END3_7", - "CLK_HROW_NW4A1_5", - "CLK_HROW_LOGIC_OUTS_B11_7", - "CLK_HROW_BYP2_3", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_SE4C3_7", - "CLK_HROW_CK_GCLK_TEST_IN9", - "CLK_HROW_BYP2_6", - "CLK_HROW_LH7_7", - "CLK_HROW_WW2A0_4", - "CLK_HROW_SW4END3_6", - "CLK_HROW_LOGIC_OUTS_B3_3", - "CLK_HROW_CK_GCLK_TEST_IN31", - "CLK_HROW_LOGIC_OUTS_B20_6", - "CLK_HROW_WW2A2_7", - "CLK_HROW_WW4END2_1", - "CLK_HROW_FAN2_1", - "CLK_HROW_IMUX30_6", - "CLK_HROW_BYP4_4", - "CLK_HROW_CK_HCLK_OUT_R2", - "CLK_HROW_IMUX34_5", - "CLK_HROW_EE4A2_2", - "CLK_HROW_WR1END0_2", - "CLK_HROW_EE4C0_7", - "CLK_HROW_IMUX5_5", - "CLK_HROW_IMUX6_3", - "CLK_HROW_SW2A0_1", - "CLK_HROW_LOGIC_OUTS_B16_0", - "CLK_HROW_FAN4_5", - "CLK_HROW_EE2A0_7", - "CLK_HROW_CK_IN_R11", - "CLK_HROW_NW4A2_6", - "CLK_HROW_CE_INT_BOT3", - "CLK_HROW_IMUX5_2", - "CLK_HROW_NW2A3_4", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_REFCK_WESTCLK0", - "CLK_HROW_NE4C0_7", - "CLK_HROW_LH12_7", - "CLK_HROW_IMUX4_4", - "CLK_HROW_IMUX20_6", - "CLK_HROW_CK_GCLK_OUT_TEST2", - "CLK_HROW_IMUX3_4", - "CLK_HROW_LOGIC_OUTS_B15_3", - "CLK_HROW_CK_BUFHCLK_L9", - "CLK_HROW_NE4C2_6", - "CLK_HROW_LH11_3", - "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "CLK_HROW_ER1BEG1_5", - "CLK_HROW_IMUX26_5", - "CLK_HROW_MONITOR_P_5", - "CLK_HROW_SE2A3_4", - "CLK_HROW_NW4A2_4", - "CLK_HROW_EE4A0_7", - "CLK_HROW_LOGIC_OUTS_B11_1", - "CLK_HROW_CK_IN_R_TEST_IN", - "CLK_HROW_BYP0_7", - "CLK_HROW_CTRL1_7", - "CLK_HROW_WW4C0_2", - "CLK_HROW_LH9_0", - "CLK_HROW_IMUX0_6", - "CLK_HROW_IMUX18_4", - "CLK_HROW_WW4C0_0", - "CLK_HROW_CK_IN_L7", - "CLK_HROW_IMUX0_3", - "CLK_HROW_CK_GCLK_OUT_TEST24", - "CLK_HROW_SW2A2_1", - "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "CLK_HROW_CK_IN_R10", - "CLK_HROW_WW4A1_0", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_CK_GCLK_TEST_OUT2", - "CLK_HROW_BYP4_5", - "CLK_HROW_CK_GCLK_OUT_TEST1", - "CLK_HROW_EE4C0_3", - "CLK_HROW_WW4END3_0", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_IMUX20_1", - "CLK_HROW_CK_GCLK_TEST_IN25", - "CLK_HROW_EE4C3_3", - "CLK_HROW_NW4A3_2", - "CLK_HROW_IMUX7_4", - "CLK_HROW_EE2BEG2_6", - "CLK_HROW_EE4C0_5", - "CLK_HROW_WW4A0_6", - "CLK_HROW_SW4A3_7", - "CLK_HROW_WW4A1_2", - "CLK_HROW_CLK1_5", - "CLK_HROW_EE4A1_7", - "CLK_HROW_CK_HCLK_OUT_L3", - "CLK_HROW_LOGIC_OUTS_B7_5", - "CLK_HROW_EE2A1_5", - "CLK_HROW_IMUX11_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE4B1_6", - "CLK_HROW_CK_GCLK_TEST_OUT8", - "CLK_HROW_NE2A0_7", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_WR1END0_0", - "CLK_HROW_NW2A0_2", - "CLK_HROW_LOGIC_OUTS_B3_6", - "CLK_HROW_SW4A2_4", - "CLK_HROW_CK_IN_L10", - "CLK_HROW_CK_BUFRCLK_R2", - "CLK_HROW_BLOCK_OUTS_B0_4", - "CLK_HROW_FAN4_3", - "CLK_HROW_CK_GCLK_TEST_IN24", - "CLK_HROW_CK_HCLK_OUT_L0", - "CLK_HROW_EL1BEG0_5", - "CLK_HROW_BYP3_2", - "CLK_HROW_WW2A3_4", - "CLK_HROW_EE4B1_0", - "CLK_HROW_NE4C3_3", - "CLK_HROW_IMUX21_5", - "CLK_HROW_IMUX18_7", - "CLK_HROW_CK_GCLK_TEST26", - "CLK_HROW_CK_GCLK_OUT_TEST0", - "CLK_HROW_CK_GCLK_TEST_IN30", - "CLK_HROW_NE2A2_3", - "CLK_HROW_WR1END3_7", - "CLK_HROW_IMUX0_5", - "CLK_HROW_LH7_5", - "CLK_HROW_LH5_5", - "CLK_HROW_CK_GCLK_IN_TEST12", - "CLK_HROW_NW4END3_2", - "CLK_HROW_SW2A1_5", - "CLK_HROW_IMUX44_1", - "CLK_HROW_IMUX32_2", - "CLK_HROW_BYP6_5", - "CLK_HROW_IMUX27_7", - "CLK_HROW_CE_INT_TOP3", - "CLK_HROW_LOGIC_OUTS_B14_1", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_SE2A1_5", - "CLK_HROW_LH8_1", - "CLK_HROW_CK_HCLK_OUT_R6", - "CLK_HROW_NW4END2_3", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_IMUX2_3", - "CLK_HROW_BYP2_1", - "CLK_HROW_IMUX1_5", - "CLK_HROW_IMUX37_2", - "CLK_HROW_CK_MUX_OUT_L5", - "CLK_HROW_WW2A2_1", - "CLK_HROW_CK_GCLK_TEST_IN28", - "CLK_HROW_LOGIC_OUTS_B11_4", - "CLK_HROW_EE4BEG1_6", - "CLK_HROW_R_CK_GCLK1", - "CLK_HROW_IMUX4_5", - "CLK_HROW_NW4A0_6", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_IMUX20_4", - "CLK_HROW_CK_GCLK_TEST23", - "CLK_HROW_CK_GCLK_TEST_OUT21", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_IMUX26_7", - "CLK_HROW_CK_GCLK_IN_TEST7", - "CLK_HROW_IMUX43_2", - "CLK_HROW_FAN1_2", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_LOGIC_OUTS_B17_2", - "CLK_HROW_CTRL0_0", - "CLK_HROW_IMUX45_5", - "CLK_HROW_LH6_6", - "CLK_HROW_CK_GCLK_TEST_IN12", - "CLK_HROW_LOGIC_OUTS_B22_5", - "CLK_HROW_LOGIC_OUTS_B10_0", - "CLK_HROW_WW4END3_5", - "CLK_HROW_ER1BEG0_4", - "CLK_HROW_IMUX12_5", - "CLK_HROW_CK_IN_R8", - "CLK_HROW_SE2A3_3", - "CLK_HROW_EE4B1_1", - "CLK_HROW_IMUX45_4", - "CLK_HROW_SW4END1_6", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4A2_7", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_WW4END3_3", - "CLK_HROW_CK_IN_R7", - "CLK_HROW_IMUX33_0", - "CLK_HROW_IMUX14_6", - "CLK_HROW_CK_GCLK_IN_TEST19", - "CLK_HROW_SW4A1_1", - "CLK_HROW_IMUX12_1", - "CLK_HROW_WW4A1_5", - "CLK_HROW_IMUX38_3", - "CLK_HROW_CK_GCLK_OUT_TEST17", - "CLK_HROW_LOGIC_OUTS_B23_2", - "CLK_HROW_IMUX40_3", - "CLK_HROW_CK_GCLK_IN_TEST15", - "CLK_HROW_CK_GCLK_TEST21", - "CLK_HROW_NW4END2_4", - "CLK_HROW_IMUX10_0", - "CLK_HROW_LOGIC_OUTS_B17_4", - "CLK_HROW_WW4END2_7", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SE2A0_5", - "CLK_HROW_IMUX9_7", - "CLK_HROW_LH2_5", - "CLK_HROW_SW2A1_3", - "CLK_HROW_FAN3_2", - "CLK_HROW_IMUX38_5", - "CLK_HROW_LOGIC_OUTS_B4_0", - "CLK_HROW_EE4BEG0_6", - "CLK_HROW_WW2END1_4", - "CLK_HROW_IMUX23_7", - "CLK_HROW_WW4B2_6", - "CLK_HROW_IMUX40_6", - "CLK_HROW_WL1END0_4", - "CLK_HROW_WW4A3_7", - "CLK_HROW_IMUX34_4", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_SW4END2_5", - "CLK_HROW_WW2A0_2", - "CLK_HROW_CE_INT_TOP0", - "CLK_HROW_EE4B3_5", - "CLK_HROW_FAN7_6", - "CLK_HROW_SW4A2_2", - "CLK_HROW_WW4B2_5", - "CLK_HROW_BLOCK_OUTS_B1_4", - "CLK_HROW_IMUX12_2", - "CLK_HROW_LOGIC_OUTS_B8_0", - "CLK_HROW_IMUX45_0", - "CLK_HROW_SE4C2_4", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN26", - "CLK_HROW_NE2A1_0", - "CLK_HROW_BUFHCE_CE_R3", - "CLK_HROW_IMUX44_2", - "CLK_HROW_CK_GCLK_TEST7", - "CLK_HROW_R_CK_GCLK23", - "CLK_HROW_WW4END2_4", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_LH9_6", - "CLK_HROW_CK_GCLK_TEST_OUT10", - "CLK_HROW_CK_GCLK_TEST_IN11", - "CLK_HROW_IMUX38_0", - "CLK_HROW_LH6_2", - "CLK_HROW_IMUX8_4", - "CLK_HROW_IMUX16_5", - "CLK_HROW_LH4_0", - "CLK_HROW_WW4C0_4", - "CLK_HROW_CK_BUFHCLK_L7", - "CLK_HROW_EE4A0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_R_CK_GCLK20", - "CLK_HROW_LOGIC_OUTS_B22_7", - "CLK_HROW_CK_IN_L4", - "CLK_HROW_SW4END3_4", - "CLK_HROW_CK_GCLK_OUT_TEST6", - "CLK_HROW_IMUX42_0", - "CLK_HROW_WR1END0_4", - "CLK_HROW_SE2A1_4", - "CLK_HROW_WW4END2_6", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NW4END2_7", - "CLK_HROW_CK_GCLK_TEST_IN14", - "CLK_HROW_NE4C0_0", - "CLK_HROW_CK_GCLK_TEST29", - "CLK_HROW_IMUX46_6", - "CLK_HROW_LOGIC_OUTS_B18_0", - "CLK_HROW_BYP6_4", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW2A1_2", - "CLK_HROW_SW2A0_5", - "CLK_HROW_WW4B3_5", - "CLK_HROW_LOGIC_OUTS_B2_7", - "CLK_HROW_EE4C1_0", - "CLK_HROW_IMUX33_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_IMUX7_6", - "CLK_HROW_CK_MUX_OUT_L2", - "CLK_HROW_IMUX35_1", - "CLK_HROW_WW4A3_4", - "CLK_HROW_IMUX21_3", - "CLK_HROW_NW4END2_5", - "CLK_HROW_CK_MUX_OUT_R3", - "CLK_HROW_EE4A0_6", - "CLK_HROW_CK_GCLK_TEST_IN26", - "CLK_HROW_SE2A3_0", - "CLK_HROW_EE4A2_5", - "CLK_HROW_LOGIC_OUTS_B21_1", - "CLK_HROW_IMUX14_3", - "CLK_HROW_CE_INT_TOP1", - "CLK_HROW_IMUX1_1", - "CLK_HROW_CE_INT_BOT9", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN28", - "CLK_HROW_EE4B0_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_NW2A1_6", - "CLK_HROW_EE4C1_6", - "CLK_HROW_CTRL0_5", - "CLK_HROW_EE2A1_4", - "CLK_HROW_WW2A3_2", - "CLK_HROW_EE4BEG1_7", - "CLK_HROW_EE4A0_4", - "CLK_HROW_SE4C3_5", - "CLK_HROW_MONITOR_N_6", - "CLK_HROW_IMUX39_5", - "CLK_HROW_IMUX46_2", - "CLK_HROW_IMUX13_4", - "CLK_HROW_LOGIC_OUTS_B6_2", - "CLK_HROW_WW4A2_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_FAN6_4", - "CLK_HROW_IMUX30_4", - "CLK_HROW_SE4C3_2", - "CLK_HROW_CK_GCLK_OUT_TEST15", - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_CK_HCLK_OUT_R4", - "CLK_HROW_NE4C1_5", - "CLK_HROW_IMUX47_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_WW4A3_2", - "CLK_HROW_CK_MUX_OUT_L11", - "CLK_HROW_LOGIC_OUTS_B19_5", - "CLK_HROW_LOGIC_OUTS_B15_0", - "CLK_HROW_LH11_6", - "CLK_HROW_SE4C0_1", - "CLK_HROW_WW4C0_1", - "CLK_HROW_CLK1_0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "CLK_HROW_WW2END3_7", - "CLK_HROW_ER1BEG0_6", - "CLK_HROW_CK_GCLK_TEST_OUT24", - "CLK_HROW_NW4END3_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_NW4A1_0", - "CLK_HROW_LOGIC_OUTS_B18_4", - "CLK_HROW_EE4A2_1", - "CLK_HROW_IMUX35_6", - "CLK_HROW_WW4C1_5", - "CLK_HROW_WL1END2_6", - "CLK_HROW_CK_GCLK_TEST15", - "CLK_HROW_LOGIC_OUTS_B5_5", - "CLK_HROW_IMUX15_1", - "CLK_HROW_EE2BEG1_6", - "CLK_HROW_CK_GCLK_OUT_TEST10", - "CLK_HROW_NW4A1_2", - "CLK_HROW_LOGIC_OUTS_B21_5", - "CLK_HROW_LOGIC_OUTS_B10_2", - "CLK_HROW_CK_IN_L_TEST_IN", - "CLK_HROW_WW4C2_0", - "CLK_HROW_CK_GCLK_IN_TEST26", - "CLK_HROW_WW2END0_4", - "CLK_HROW_LH7_2", - "CLK_HROW_FAN6_7", - "CLK_HROW_ER1BEG2_4", - "CLK_HROW_NW4A3_7", - "CLK_HROW_CK_IN_L1", - "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "CLK_HROW_EE4A1_5", - "CLK_HROW_EE4B2_5", - "CLK_HROW_IMUX37_3", - "CLK_HROW_NW2A0_7", - "CLK_HROW_LOGIC_OUTS_B12_7", - "CLK_HROW_CK_GCLK_TEST22", - "CLK_HROW_SW4END2_6", - "CLK_HROW_SW4A2_3", - "CLK_HROW_IMUX23_2", - "CLK_HROW_CK_BUFHCLK_L10", - "CLK_HROW_BYP4_0", - "CLK_HROW_SE2A0_4", - "CLK_HROW_WW2A0_1", - "CLK_HROW_EE4B2_4", - "CLK_HROW_LOGIC_OUTS_B2_3", - "CLK_HROW_IMUX4_3", - "CLK_HROW_CK_GCLK_TEST_OUT27", - "CLK_HROW_IMUX44_4", - "CLK_HROW_EE4BEG0_4", - "CLK_HROW_FAN7_5", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_LOGIC_OUTS_B13_1", - "CLK_HROW_IMUX47_2", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_0", - "CLK_HROW_WW2A1_0", - "CLK_HROW_BUFHCE_CE_L9", - "CLK_HROW_WL1END3_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_CK_GCLK_TEST_OUT23", - "CLK_HROW_IMUX0_4", - "CLK_HROW_NW4A1_4", - "CLK_HROW_SE4BEG1_4", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_WR1END1_4", - "CLK_HROW_SE4C2_6", - "CLK_HROW_LH3_7", - "CLK_HROW_IMUX30_7", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_CK_HCLK_OUT_R9", - "CLK_HROW_WW4END0_6", - "CLK_HROW_WR1END2_7", - "CLK_HROW_FAN6_6", - "CLK_HROW_LOGIC_OUTS_B6_7", - "CLK_HROW_LOGIC_OUTS_B20_2", - "CLK_HROW_WW4C3_0", - "CLK_HROW_NE4BEG1_4", - "CLK_HROW_IMUX20_2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN27", - "CLK_HROW_WL1END2_5", - "CLK_HROW_CTRL1_0", - "CLK_HROW_IMUX41_3", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_NW4END0_7", - "CLK_HROW_NW2A3_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_IMUX1_7", - "CLK_HROW_WR1END1_2", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_IMUX4_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_IMUX10_2", - "CLK_HROW_WW2A2_0", - "CLK_HROW_FAN2_6", - "CLK_HROW_CK_GCLK_TEST_OUT15", - "CLK_HROW_IMUX8_3", - "CLK_HROW_IMUX33_4", - "CLK_HROW_NW4END3_7", - "CLK_HROW_CTRL0_2", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE4B0_6", - "CLK_HROW_R_CK_GCLK7", - "CLK_HROW_WL1END1_7", - "CLK_HROW_EE2A0_3", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_CE_INT_BOT11", - "CLK_HROW_WW2A2_4", - "CLK_HROW_EE4B0_4", - "CLK_HROW_WW4C0_5", - "CLK_HROW_LOGIC_OUTS_B13_2", - "CLK_HROW_EE2A0_4", - "CLK_HROW_IMUX33_3", - "CLK_HROW_EE2A1_7", - "CLK_HROW_IMUX45_3", - "CLK_HROW_CK_IN_L8", - "CLK_HROW_IMUX5_6", - "CLK_HROW_NW4A3_5", - "CLK_HROW_EE4C1_3", - "CLK_HROW_SW4END0_5", - "CLK_HROW_NE4C2_1", - "CLK_HROW_LOGIC_OUTS_B8_6", - "CLK_HROW_CK_GCLK_TEST_IN16", - "CLK_HROW_R_CK_GCLK11", - "CLK_HROW_BYP0_3", - "CLK_HROW_FAN6_5", - "CLK_HROW_WW4A1_4", - "CLK_HROW_IMUX6_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "CLK_HROW_EE2A1_3", - "CLK_HROW_LOGIC_OUTS_B9_1", - "CLK_HROW_CE_INT_BOT8", - "CLK_HROW_IMUX9_4", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_IMUX3_0", - "CLK_HROW_LOGIC_OUTS_B1_4", - "CLK_HROW_IMUX23_1", - "CLK_HROW_BUFHCE_CE_R5", - "CLK_HROW_IMUX41_5", - "CLK_HROW_EE2A3_0", - "CLK_HROW_IMUX32_1", - "CLK_HROW_CK_GCLK_IN_TEST27", - "CLK_HROW_SE2A2_1", - "CLK_HROW_CK_GCLK_TEST13", - "CLK_HROW_EL1BEG2_7", - "CLK_HROW_EE4C0_4", - "CLK_HROW_EE4A3_5", - "CLK_HROW_LH1_6", - "CLK_HROW_WW4END3_6", - "CLK_HROW_SW2A2_0", - "CLK_HROW_IMUX24_3", - "CLK_HROW_CK_HCLK_OUT_L4", - "CLK_HROW_LOGIC_OUTS_B5_4", - "CLK_HROW_WW2END2_4", - "CLK_HROW_WW2A1_6", - "CLK_HROW_IMUX47_5", - "CLK_HROW_EE4B1_4", - "CLK_HROW_NW4A0_5", - "CLK_HROW_R_CK_GCLK22", - "CLK_HROW_BYP1_2", - "CLK_HROW_BUFHCE_CE_L2", - "CLK_HROW_R_CK_GCLK27", - "CLK_HROW_IMUX24_6", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_IMUX1_0", - "CLK_HROW_R_CK_GCLK16", - "CLK_HROW_LOGIC_OUTS_B0_0", - "CLK_HROW_IMUX17_3", - "CLK_HROW_CK_BUFHCLK_R4", - "CLK_HROW_CK_BUFHCLK_R11", - "CLK_HROW_IMUX12_0", - "CLK_HROW_IMUX43_1", - "CLK_HROW_NW2A3_2", - "CLK_HROW_SW4A3_5", - "CLK_HROW_IMUX33_1", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A3_6", - "CLK_HROW_CK_HCLK_OUT_R3", - "CLK_HROW_CK_GCLK_IN_TEST25", - "CLK_HROW_IMUX16_3", - "CLK_HROW_CK_GCLK_IN_TEST17", - "CLK_HROW_CK_IN_R0", - "CLK_HROW_NW4A3_4", - "CLK_HROW_LH1_7", - "CLK_HROW_IMUX0_2", - "CLK_HROW_WW4A0_1", - "CLK_HROW_IMUX37_6", - "CLK_HROW_WW4A3_5", - "CLK_HROW_CK_GCLK_TEST_OUT26", - "CLK_HROW_FAN5_3", - "CLK_HROW_SW4A2_1", - "CLK_HROW_WW4C2_5", - "CLK_HROW_CK_GCLK_IN_TEST18", - "CLK_HROW_EE4B2_2", - "CLK_HROW_IMUX35_3", - "CLK_HROW_EE4B3_6", - "CLK_HROW_LOGIC_OUTS_B10_6", - "CLK_HROW_R_CK_GCLK26", - "CLK_HROW_IMUX7_0", - "CLK_HROW_R_CK_GCLK10", - "CLK_HROW_CK_MUX_OUT_R10", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN29", - "CLK_HROW_LOGIC_OUTS_B11_2", - "CLK_HROW_IMUX36_1", - "CLK_HROW_SE4C0_0", - "CLK_HROW_LOGIC_OUTS_B1_6", - "CLK_HROW_CK_GCLK_TEST3", - "CLK_HROW_WW2END1_0", - "CLK_HROW_LH2_4", - "CLK_HROW_CK_IN_L0", - "CLK_HROW_SE4C2_5", - "CLK_HROW_EE2BEG0_6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN21", - "CLK_HROW_LOGIC_OUTS_B5_3", - "CLK_HROW_WW2END3_5", - "CLK_HROW_BYP3_6", - "CLK_HROW_NE2A0_5", - "CLK_HROW_SE2A0_6", - "CLK_HROW_EE4C3_6", - "CLK_HROW_IMUX43_3", - "CLK_HROW_CK_GCLK_TEST_OUT14", - "CLK_HROW_BLOCK_OUTS_B2_6", - "CLK_HROW_BUFHCE_CE_R4", - "CLK_HROW_WW2A3_6", - "CLK_HROW_IMUX43_5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "CLK_HROW_NW4END0_3", - "CLK_HROW_IMUX39_7", - "CLK_HROW_SE4C0_2", - "CLK_HROW_LOGIC_OUTS_B11_6", - "CLK_HROW_NW2A2_5", - "CLK_HROW_WW2END0_3", - "CLK_HROW_IMUX26_6", - "CLK_HROW_WR1END2_1", - "CLK_HROW_IMUX19_5", - "CLK_HROW_WL1END0_5", - "CLK_HROW_LOGIC_OUTS_B10_1", - "CLK_HROW_IMUX16_1", - "CLK_HROW_IMUX36_5", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_WW4A0_2", - "CLK_HROW_IMUX28_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_LH10_4", - "CLK_HROW_EE4B0_0", - "CLK_HROW_CK_HCLK_OUT_L10", - "CLK_HROW_LOGIC_OUTS_B5_6", - "CLK_HROW_NE2A3_7", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_WW4END1_4", - "CLK_HROW_IMUX17_5", - "CLK_HROW_LH12_0", - "CLK_HROW_CK_BUFRCLK_L3", - "CLK_HROW_FAN2_4", - "CLK_HROW_CK_BUFHCLK_R7", - "CLK_HROW_NW2A3_5", - "CLK_HROW_WL1END3_0", - "CLK_HROW_IMUX45_6", - "CLK_HROW_WW4A3_3", - "CLK_HROW_CK_MUX_OUT_R9", - "CLK_HROW_LOGIC_OUTS_B8_5", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_WR1END1_5", - "CLK_HROW_BYP7_5", - "CLK_HROW_WR1END2_5", - "CLK_HROW_R_CK_GCLK24", - "CLK_HROW_IMUX8_5", - "CLK_HROW_NW4A2_0", - "CLK_HROW_SW2A1_6", - "CLK_HROW_CK_GCLK_IN_TEST23", - "CLK_HROW_SW4END0_0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "CLK_HROW_LH2_0", - "CLK_HROW_CK_IN_L6", - "CLK_HROW_NE4BEG2_6", - "CLK_HROW_CK_HCLK_OUT_R10", - "CLK_HROW_EE2BEG1_5", - "CLK_HROW_NW4A2_7", - "CLK_HROW_IMUX1_2", - "CLK_HROW_IMUX15_6", - "CLK_HROW_SE4C3_1", - "CLK_HROW_CK_HCLK_OUT_R7", - "CLK_HROW_SE4C0_4", - "CLK_HROW_FAN1_0" - ], - "sites": [ - { - "prefix": "BUFHCE", - "y_coord": 0, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L0", - "O": "CLK_HROW_CK_HCLK_OUT_L0", - "CE": "CLK_HROW_BUFHCE_CE_L0" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "BUFHCE", - "y_coord": 1, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L1", - "O": "CLK_HROW_CK_HCLK_OUT_L1", - "CE": "CLK_HROW_BUFHCE_CE_L1" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "BUFHCE", - "y_coord": 2, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L2", - "O": "CLK_HROW_CK_HCLK_OUT_L2", - "CE": "CLK_HROW_BUFHCE_CE_L2" - }, - "x_coord": 0, - "name": "X0Y2" - }, - { - "prefix": "BUFHCE", - "y_coord": 3, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L3", - "O": "CLK_HROW_CK_HCLK_OUT_L3", - "CE": "CLK_HROW_BUFHCE_CE_L3" - }, - "x_coord": 0, - "name": "X0Y3" - }, - { - "prefix": "BUFHCE", - "y_coord": 4, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L4", - "O": "CLK_HROW_CK_HCLK_OUT_L4", - "CE": "CLK_HROW_BUFHCE_CE_L4" - }, - "x_coord": 0, - "name": "X0Y4" - }, - { - "prefix": "BUFHCE", - "y_coord": 5, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L5", - "O": "CLK_HROW_CK_HCLK_OUT_L5", - "CE": "CLK_HROW_BUFHCE_CE_L5" - }, - "x_coord": 0, - "name": "X0Y5" - }, - { - "prefix": "BUFHCE", - "y_coord": 6, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L6", - "O": "CLK_HROW_CK_HCLK_OUT_L6", - "CE": "CLK_HROW_BUFHCE_CE_L6" - }, - "x_coord": 0, - "name": "X0Y6" - }, - { - "prefix": "BUFHCE", - "y_coord": 7, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L7", - "O": "CLK_HROW_CK_HCLK_OUT_L7", - "CE": "CLK_HROW_BUFHCE_CE_L7" - }, - "x_coord": 0, - "name": "X0Y7" - }, - { - "prefix": "BUFHCE", - "y_coord": 8, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L8", - "O": "CLK_HROW_CK_HCLK_OUT_L8", - "CE": "CLK_HROW_BUFHCE_CE_L8" - }, - "x_coord": 0, - "name": "X0Y8" - }, - { - "prefix": "BUFHCE", - "y_coord": 9, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L9", - "O": "CLK_HROW_CK_HCLK_OUT_L9", - "CE": "CLK_HROW_BUFHCE_CE_L9" - }, - "x_coord": 0, - "name": "X0Y9" - }, - { - "prefix": "BUFHCE", - "y_coord": 10, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L10", - "O": "CLK_HROW_CK_HCLK_OUT_L10", - "CE": "CLK_HROW_BUFHCE_CE_L10" - }, - "x_coord": 0, - "name": "X0Y10" - }, - { - "prefix": "BUFHCE", - "y_coord": 11, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_L11", - "O": "CLK_HROW_CK_HCLK_OUT_L11", - "CE": "CLK_HROW_BUFHCE_CE_L11" - }, - "x_coord": 0, - "name": "X0Y11" - }, - { - "prefix": "BUFHCE", - "y_coord": 11, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R11", - "O": "CLK_HROW_CK_HCLK_OUT_R11", - "CE": "CLK_HROW_BUFHCE_CE_R11" - }, - "x_coord": 1, - "name": "X1Y11" - }, - { - "prefix": "BUFHCE", - "y_coord": 10, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R10", - "O": "CLK_HROW_CK_HCLK_OUT_R10", - "CE": "CLK_HROW_BUFHCE_CE_R10" - }, - "x_coord": 1, - "name": "X1Y10" - }, - { - "prefix": "BUFHCE", - "y_coord": 9, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R9", - "O": "CLK_HROW_CK_HCLK_OUT_R9", - "CE": "CLK_HROW_BUFHCE_CE_R9" - }, - "x_coord": 1, - "name": "X1Y9" - }, - { - "prefix": "BUFHCE", - "y_coord": 8, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R8", - "O": "CLK_HROW_CK_HCLK_OUT_R8", - "CE": "CLK_HROW_BUFHCE_CE_R8" - }, - "x_coord": 1, - "name": "X1Y8" - }, - { - "prefix": "BUFHCE", - "y_coord": 7, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R7", - "O": "CLK_HROW_CK_HCLK_OUT_R7", - "CE": "CLK_HROW_BUFHCE_CE_R7" - }, - "x_coord": 1, - "name": "X1Y7" - }, - { - "prefix": "BUFHCE", - "y_coord": 6, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R6", - "O": "CLK_HROW_CK_HCLK_OUT_R6", - "CE": "CLK_HROW_BUFHCE_CE_R6" - }, - "x_coord": 1, - "name": "X1Y6" - }, - { - "prefix": "BUFHCE", - "y_coord": 5, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R5", - "O": "CLK_HROW_CK_HCLK_OUT_R5", - "CE": "CLK_HROW_BUFHCE_CE_R5" - }, - "x_coord": 1, - "name": "X1Y5" - }, - { - "prefix": "BUFHCE", - "y_coord": 4, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R4", - "O": "CLK_HROW_CK_HCLK_OUT_R4", - "CE": "CLK_HROW_BUFHCE_CE_R4" - }, - "x_coord": 1, - "name": "X1Y4" - }, - { - "prefix": "BUFHCE", - "y_coord": 3, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R3", - "O": "CLK_HROW_CK_HCLK_OUT_R3", - "CE": "CLK_HROW_BUFHCE_CE_R3" - }, - "x_coord": 1, - "name": "X1Y3" - }, - { - "prefix": "BUFHCE", - "y_coord": 2, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R2", - "O": "CLK_HROW_CK_HCLK_OUT_R2", - "CE": "CLK_HROW_BUFHCE_CE_R2" - }, - "x_coord": 1, - "name": "X1Y2" - }, - { - "prefix": "BUFHCE", - "y_coord": 1, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R1", - "O": "CLK_HROW_CK_HCLK_OUT_R1", - "CE": "CLK_HROW_BUFHCE_CE_R1" - }, - "x_coord": 1, - "name": "X1Y1" - }, - { - "prefix": "BUFHCE", - "y_coord": 0, - "type": "BUFHCE", - "site_pins": { - "I": "CLK_HROW_CK_MUX_OUT_R0", - "O": "CLK_HROW_CK_HCLK_OUT_R0", - "CE": "CLK_HROW_BUFHCE_CE_R0" - }, - "x_coord": 1, - "name": "X1Y0" - } - ], "pips": { - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT5", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX5_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP5", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX5_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0", - "is_pseudo": "0" - }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP9", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX9_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT2", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX2_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP4", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX4_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_INT_1_0", - "is_directional": "1", - "src_wire": "CLK_HROW_CLK0_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN28->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN17->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT10", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX10_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP11", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX11_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R_TEST_IN", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP1", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX1_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN14->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN24->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN30->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT9", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX9_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP10", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX10_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT4", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX4_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN15->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_INT_0_1", - "is_directional": "1", - "src_wire": "CLK_HROW_CLK1_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP8", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX8_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L_TEST_IN", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT1", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX1_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN18->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP7", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX7_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN26->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT0", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX0_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT8", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX8_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_INT_0_0", - "is_directional": "1", - "src_wire": "CLK_HROW_CLK0_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP6", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX6_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP0", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX0_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "src_wire": "CLK_HROW_CK_IN_L4", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT11", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX11_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_INT_1_1", - "is_directional": "1", - "src_wire": "CLK_HROW_CLK1_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP2", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX2_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT7", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX7_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN31->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN27->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_TOP3", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX3_4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN25->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN16->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT3", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX3_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_0_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN23->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN29->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK17", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9", "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN20->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_BOT4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN19->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN19", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CE_INT_BOT6", - "is_directional": "1", - "src_wire": "CLK_HROW_IMUX6_3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK20", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "src_wire": "CLK_HROW_CK_IN_R1", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "src_wire": "CLK_HROW_CK_IN_L8", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "src_wire": "CLK_HROW_CK_IN_L3", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK30", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L8", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", "src_wire": "CLK_HROW_CK_INT_0_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_pseudo": "1" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK29", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK28", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_INT_1_1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN22->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN22", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK15", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_BUFHCE_CE_L8", - "is_directional": "1", - "src_wire": "CLK_HROW_CE_INT_TOP2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK18", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK16", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK31", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK23", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R5", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_BUFHCLK_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_HCLK_OUT_R4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R0", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK24", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN21->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN21", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", - "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK13", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L7", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R10", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "src_wire": "CLK_HROW_CK_IN_R13", "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", + "src_wire": "CLK_HROW_R_CK_GCLK3", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", + "src_wire": "CLK_HROW_CK_IN_R4", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", "src_wire": "CLK_HROW_CK_IN_L1", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", + "src_wire": "CLK_HROW_CK_IN_R6", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_L3", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L4", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { - "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_BUFRCLK_R2", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", - "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_L8", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20", "is_directional": "1", - "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", + "src_wire": "CLK_HROW_R_CK_GCLK10", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_L12", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "src_wire": "CLK_HROW_R_CK_GCLK26", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" - }, - "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { - "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", - "src_wire": "CLK_HROW_R_CK_GCLK19", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "src_wire": "CLK_HROW_CK_IN_L11", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", - "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "src_wire": "CLK_HROW_CK_IN_L5", "is_directional": "1", - "src_wire": "CLK_HROW_CK_IN_R11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" }, - "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", + "src_wire": "CLK_HROW_CK_IN_L10", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L2", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", "src_wire": "CLK_HROW_CK_IN_L0", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R_TEST_IN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN27->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R5", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN22->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN15->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", - "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", - "is_directional": "1", "src_wire": "CLK_HROW_CK_IN_R9", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN18->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R3", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R8", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L11", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN28->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN14->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN31->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN20->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX11_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R4", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L6", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CLK0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_0_0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R6", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R2", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L5", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN19->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CLK0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_1_0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L10", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L7", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L_TEST_IN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX10_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN21->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN16->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN29->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN30->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CLK1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_1_1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R11", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L3", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R7", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN24->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN25->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L9", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R9", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN23->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX9_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_R10", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_TOP9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN26->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L4", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_BOT11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN17->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { + "can_invert": "0", + "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_MUX_OUT_L8", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15" + }, + "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CE_INT_BOT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_BUFHCE_CE_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_INT_1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_HCLK_OUT_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_BUFHCLK_R7" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22" + }, + "CLK_HROW_TOP_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { + "can_invert": "0", + "src_wire": "CLK_HROW_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CE_INT_TOP8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_BUFRCLK_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "CLK_HROW_TOP_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { + "can_invert": "0", + "src_wire": "CLK_HROW_CLK1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_INT_0_1" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { + "can_invert": "0", + "src_wire": "CLK_HROW_R_CK_GCLK16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { + "can_invert": "0", + "src_wire": "CLK_HROW_CK_IN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_HROW_CK_MUX_OUT_L11" } }, - "tile_type": "CLK_HROW_TOP_R" + "wires": [ + "CLK_HROW_IMUX32_2", + "CLK_HROW_CK_GCLK_TEST_IN19", + "CLK_HROW_BUFHCE_CE_L7", + "CLK_HROW_CK_INT_1_0", + "CLK_HROW_SW4END2_4", + "CLK_HROW_BYP4_0", + "CLK_HROW_IMUX8_1", + "CLK_HROW_WW4END1_4", + "CLK_HROW_FAN6_6", + "CLK_HROW_IMUX46_5", + "CLK_HROW_TOP_R_CK_BUFG_CASCO4", + "CLK_HROW_CK_GCLK_TEST_IN7", + "CLK_HROW_IMUX10_7", + "CLK_HROW_IMUX13_6", + "CLK_HROW_EL1BEG0_0", + "CLK_HROW_CK_GCLK_TEST6", + "CLK_HROW_SW2A1_2", + "CLK_HROW_CK_HCLK_OUT_R10", + "CLK_HROW_NW2A3_1", + "CLK_HROW_WW4A1_4", + "CLK_HROW_EE4C2_6", + "CLK_HROW_EE4A0_7", + "CLK_HROW_LOGIC_OUTS_B22_3", + "CLK_HROW_EE2BEG2_3", + "CLK_HROW_LH1_0", + "CLK_HROW_WW4C2_0", + "CLK_HROW_LOGIC_OUTS_B9_3", + "CLK_HROW_WR1END2_6", + "CLK_HROW_BYP7_2", + "CLK_HROW_CLK1_3", + "CLK_HROW_CK_GCLK_TEST_IN0", + "CLK_HROW_CK_GCLK_TEST_IN12", + "CLK_HROW_EE2A3_1", + "CLK_HROW_EE2A2_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCO23", + "CLK_HROW_CE_INT_BOT3", + "CLK_HROW_SW4END3_4", + "CLK_HROW_EE4C0_5", + "CLK_HROW_IMUX43_0", + "CLK_HROW_SE2A0_1", + "CLK_HROW_IMUX24_4", + "CLK_HROW_WW4C2_2", + "CLK_HROW_LOGIC_OUTS_B7_2", + "CLK_HROW_CK_IN_L11", + "CLK_HROW_SE4C0_1", + "CLK_HROW_SW4A1_1", + "CLK_HROW_IMUX12_0", + "CLK_HROW_LH8_4", + "CLK_HROW_SW4A1_7", + "CLK_HROW_LOGIC_OUTS_B17_2", + "CLK_HROW_SE4C3_7", + "CLK_HROW_IMUX33_5", + "CLK_HROW_BYP5_1", + "CLK_HROW_IMUX19_6", + "CLK_HROW_WW4C3_2", + "CLK_HROW_FAN6_5", + "CLK_HROW_NW2A1_7", + "CLK_HROW_IMUX28_2", + "CLK_HROW_IMUX20_3", + "CLK_HROW_IMUX2_7", + "CLK_HROW_CK_HCLK_OUT_L0", + "CLK_HROW_LH5_5", + "CLK_HROW_WR1END3_2", + "CLK_HROW_BYP3_4", + "CLK_HROW_IMUX33_3", + "CLK_HROW_CK_MUX_OUT_L11", + "CLK_HROW_WW2END2_0", + "CLK_HROW_FAN4_6", + "CLK_HROW_R_CK_GCLK15", + "CLK_HROW_SW2A0_5", + "CLK_HROW_CK_GCLK_IN_TEST6", + "CLK_HROW_BYP7_5", + "CLK_HROW_IMUX28_7", + "CLK_HROW_NW4A3_0", + "CLK_HROW_EE2BEG2_6", + "CLK_HROW_CK_GCLK_TEST7", + "CLK_HROW_IMUX37_4", + "CLK_HROW_IMUX45_7", + "CLK_HROW_EE4A0_1", + "CLK_HROW_WW4END3_5", + "CLK_HROW_FAN5_6", + "CLK_HROW_EE2A0_6", + "CLK_HROW_IMUX0_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN28", + "CLK_HROW_LOGIC_OUTS_B1_4", + "CLK_HROW_CK_BUFRCLK_R0", + "CLK_HROW_IMUX42_2", + "CLK_HROW_WW4END3_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN19", + "CLK_HROW_TOP_R_CK_BUFG_CASCO5", + "CLK_HROW_EL1BEG1_6", + "CLK_HROW_LOGIC_OUTS_B20_3", + "CLK_HROW_IMUX32_7", + "CLK_HROW_CK_GCLK_TEST_OUT1", + "CLK_HROW_LOGIC_OUTS_B0_6", + "CLK_HROW_CK_GCLK_OUT_TEST28", + "CLK_HROW_CK_GCLK_TEST_OUT0", + "CLK_HROW_ER1BEG0_6", + "CLK_HROW_IMUX11_7", + "CLK_HROW_BYP5_0", + "CLK_HROW_CK_BUFHCLK_L2", + "CLK_HROW_LOGIC_OUTS_B6_6", + "CLK_HROW_CK_GCLK_OUT_TEST29", + "CLK_HROW_FAN7_5", + "CLK_HROW_R_CK_GCLK12", + "CLK_HROW_ER1BEG3_0", + "CLK_HROW_EE4B1_5", + "CLK_HROW_SW2A0_7", + "CLK_HROW_NW4A0_3", + "CLK_HROW_IMUX15_0", + "CLK_HROW_EE2A3_4", + "CLK_HROW_SW2A3_6", + "CLK_HROW_LOGIC_OUTS_B1_6", + "CLK_HROW_LH10_2", + "CLK_HROW_IMUX44_4", + "CLK_HROW_NE4BEG2_5", + "CLK_HROW_IMUX11_1", + "CLK_HROW_EE4A1_7", + "CLK_HROW_IMUX32_4", + "CLK_HROW_LOGIC_OUTS_B10_7", + "CLK_HROW_IMUX5_0", + "CLK_HROW_IMUX38_7", + "CLK_HROW_SE4BEG0_3", + "CLK_HROW_NE4BEG3_6", + "CLK_HROW_IMUX11_2", + "CLK_HROW_IMUX20_6", + "CLK_HROW_IMUX25_0", + "CLK_HROW_LOGIC_OUTS_B23_0", + "CLK_HROW_CK_GCLK_TEST3", + "CLK_HROW_WW4C3_7", + "CLK_HROW_LH6_5", + "CLK_HROW_LOGIC_OUTS_B3_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCO30", + "CLK_HROW_MONITOR_N_3", + "CLK_HROW_CE_INT_BOT10", + "CLK_HROW_SW4END0_5", + "CLK_HROW_EE4C1_6", + "CLK_HROW_IMUX32_3", + "CLK_HROW_MONITOR_P_3", + "CLK_HROW_CK_GCLK_IN_TEST30", + "CLK_HROW_LOGIC_OUTS_B13_4", + "CLK_HROW_IMUX31_1", + "CLK_HROW_IMUX5_3", + "CLK_HROW_EL1BEG2_7", + "CLK_HROW_EE4BEG3_2", + "CLK_HROW_LOGIC_OUTS_B8_5", + "CLK_HROW_LOGIC_OUTS_B8_0", + "CLK_HROW_CK_HCLK_OUT_L5", + "CLK_HROW_CK_IN_L3", + "CLK_HROW_NW4END3_2", + "CLK_HROW_EE4BEG3_3", + "CLK_HROW_EE4C3_6", + "CLK_HROW_EL1BEG3_3", + "CLK_HROW_EE4A0_3", + "CLK_HROW_LOGIC_OUTS_B0_4", + "CLK_HROW_CK_IN_L9", + "CLK_HROW_SE4BEG2_7", + "CLK_HROW_FAN0_3", + "CLK_HROW_CK_GCLK_IN_TEST22", + "CLK_HROW_CK_IN_R_OUT_TEST", + "CLK_HROW_BLOCK_OUTS_B2_1", + "CLK_HROW_CK_GCLK_IN_TEST31", + "CLK_HROW_IMUX40_6", + "CLK_HROW_REFCK_EASTCLK0", + "CLK_HROW_IMUX17_2", + "CLK_HROW_IMUX41_4", + "CLK_HROW_CK_MUX_OUT_L10", + "CLK_HROW_SW4A3_2", + "CLK_HROW_R_CK_GCLK14", + "CLK_HROW_LOGIC_OUTS_B18_0", + "CLK_HROW_LOGIC_OUTS_B11_0", + "CLK_HROW_NE4C3_6", + "CLK_HROW_IMUX3_4", + "CLK_HROW_BYP3_7", + "CLK_HROW_CK_GCLK_IN_TEST21", + "CLK_HROW_SE4BEG2_3", + "CLK_HROW_EE2BEG0_4", + "CLK_HROW_IMUX40_1", + "CLK_HROW_LOGIC_OUTS_B7_1", + "CLK_HROW_LH8_2", + "CLK_HROW_EE2A1_0", + "CLK_HROW_CK_GCLK_IN_TEST13", + "CLK_HROW_LH12_7", + "CLK_HROW_NW2A2_1", + "CLK_HROW_CK_GCLK_OUT_TEST24", + "CLK_HROW_NE4C0_3", + "CLK_HROW_BYP7_0", + "CLK_HROW_LOGIC_OUTS_B23_2", + "CLK_HROW_SE2A3_6", + "CLK_HROW_EL1BEG3_2", + "CLK_HROW_LH4_6", + "CLK_HROW_BLOCK_OUTS_B3_5", + "CLK_HROW_SW4END2_2", + "CLK_HROW_WW2A1_7", + "CLK_HROW_CK_MUX_OUT_L9", + "CLK_HROW_BYP2_0", + "CLK_HROW_EE2BEG2_0", + "CLK_HROW_WW2END1_4", + "CLK_HROW_CK_MUX_OUT_L3", + "CLK_HROW_WW4C1_1", + "CLK_HROW_LH3_7", + "CLK_HROW_IMUX20_1", + "CLK_HROW_LH1_4", + "CLK_HROW_NE4BEG2_7", + "CLK_HROW_LOGIC_OUTS_B20_5", + "CLK_HROW_SE2A0_5", + "CLK_HROW_FAN1_0", + "CLK_HROW_IMUX43_7", + "CLK_HROW_FAN7_7", + "CLK_HROW_LH10_3", + "CLK_HROW_LOGIC_OUTS_B23_7", + "CLK_HROW_NW4END0_5", + "CLK_HROW_WR1END3_5", + "CLK_HROW_MONITOR_P_5", + "CLK_HROW_BLOCK_OUTS_B2_2", + "CLK_HROW_FAN5_7", + "CLK_HROW_IMUX38_4", + "CLK_HROW_R_CK_GCLK2", + "CLK_HROW_LOGIC_OUTS_B23_6", + "CLK_HROW_IMUX26_5", + "CLK_HROW_CK_GCLK_OUT_TEST3", + "CLK_HROW_EE2BEG0_2", + "CLK_HROW_LH2_2", + "CLK_HROW_SW4A2_5", + "CLK_HROW_IMUX11_5", + "CLK_HROW_EE4BEG0_4", + "CLK_HROW_LOGIC_OUTS_B6_5", + "CLK_HROW_CLK1_6", + "CLK_HROW_BUFHCE_CE_L9", + "CLK_HROW_IMUX29_6", + "CLK_HROW_CK_HCLK_OUT_R8", + "CLK_HROW_NE4C3_5", + "CLK_HROW_CK_HCLK_OUT_L9", + "CLK_HROW_CK_GCLK_TEST_OUT28", + "CLK_HROW_SE4BEG1_2", + "CLK_HROW_LOGIC_OUTS_B15_5", + "CLK_HROW_WW4C1_2", + "CLK_HROW_ER1BEG3_3", + "CLK_HROW_NE2A2_1", + "CLK_HROW_WW2A2_5", + "CLK_HROW_EE2BEG3_4", + "CLK_HROW_CK_GCLK_TEST_IN18", + "CLK_HROW_LOGIC_OUTS_B14_0", + "CLK_HROW_NW2A2_4", + "CLK_HROW_NW4A0_5", + "CLK_HROW_BLOCK_OUTS_B3_4", + "CLK_HROW_WW2A3_2", + "CLK_HROW_EE4A3_5", + "CLK_HROW_NE4C1_7", + "CLK_HROW_SE4C0_3", + "CLK_HROW_WW4C1_5", + "CLK_HROW_WW4B1_1", + "CLK_HROW_WR1END1_6", + "CLK_HROW_LOGIC_OUTS_B0_2", + "CLK_HROW_CK_MUX_OUT_L0", + "CLK_HROW_CE_INT_BOT8", + "CLK_HROW_NW4END2_7", + "CLK_HROW_NE4C1_6", + "CLK_HROW_EE4BEG3_4", + "CLK_HROW_IMUX38_5", + "CLK_HROW_NW4A3_1", + "CLK_HROW_LOGIC_OUTS_B9_5", + "CLK_HROW_CK_GCLK_TEST17", + "CLK_HROW_WW2END1_0", + "CLK_HROW_NW4END2_3", + "CLK_HROW_NE2A2_0", + "CLK_HROW_WW2END2_6", + "CLK_HROW_IMUX30_3", + "CLK_HROW_CK_GCLK_OUT_TEST9", + "CLK_HROW_TOP_R_CK_BUFG_CASCO17", + "CLK_HROW_IMUX42_3", + "CLK_HROW_BLOCK_OUTS_B3_0", + "CLK_HROW_WW4B3_7", + "CLK_HROW_SE2A1_2", + "CLK_HROW_CK_GCLK_TEST_IN29", + "CLK_HROW_SW2A1_5", + "CLK_HROW_CK_IN_R3", + "CLK_HROW_CE_INT_TOP7", + "CLK_HROW_CLK0_1", + "CLK_HROW_LH11_6", + "CLK_HROW_SE4BEG0_4", + "CLK_HROW_CK_GCLK_TEST_IN23", + "CLK_HROW_FAN3_4", + "CLK_HROW_IMUX27_2", + "CLK_HROW_NW4A3_4", + "CLK_HROW_SE4BEG3_3", + "CLK_HROW_CK_GCLK_IN_TEST17", + "CLK_HROW_R_CK_GCLK13", + "CLK_HROW_LOGIC_OUTS_B9_2", + "CLK_HROW_SE2A2_6", + "CLK_HROW_EE4BEG1_4", + "CLK_HROW_NW4A0_1", + "CLK_HROW_NE4BEG0_5", + "CLK_HROW_IMUX2_2", + "CLK_HROW_EE4B2_0", + "CLK_HROW_CK_IN_R4", + "CLK_HROW_WW4C0_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCO0", + "CLK_HROW_EE4BEG0_2", + "CLK_HROW_FAN5_1", + "CLK_HROW_FAN2_5", + "CLK_HROW_CE_INT_BOT5", + "CLK_HROW_EE2A0_1", + "CLK_HROW_R_CK_GCLK1", + "CLK_HROW_WW4A1_0", + "CLK_HROW_WW2A2_2", + "CLK_HROW_LH2_0", + "CLK_HROW_LOGIC_OUTS_B19_5", + "CLK_HROW_CK_BUFHCLK_R4", + "CLK_HROW_EE4C0_4", + "CLK_HROW_CK_GCLK_TEST11", + "CLK_HROW_NW2A2_3", + "CLK_HROW_CTRL0_7", + "CLK_HROW_LOGIC_OUTS_B20_4", + "CLK_HROW_LOGIC_OUTS_B21_1", + "CLK_HROW_IMUX39_5", + "CLK_HROW_IMUX8_0", + "CLK_HROW_BLOCK_OUTS_B0_5", + "CLK_HROW_FAN0_1", + "CLK_HROW_SE4BEG3_7", + "CLK_HROW_IMUX30_1", + "CLK_HROW_LOGIC_OUTS_B16_5", + "CLK_HROW_SE2A1_3", + "CLK_HROW_WW4END0_1", + "CLK_HROW_LH5_2", + "CLK_HROW_WW2END3_3", + "CLK_HROW_WW4B1_5", + "CLK_HROW_IMUX32_1", + "CLK_HROW_CK_IN_L2", + "CLK_HROW_CK_GCLK_IN_TEST10", + "CLK_HROW_LOGIC_OUTS_B4_0", + "CLK_HROW_LOGIC_OUTS_B16_2", + "CLK_HROW_WL1END3_2", + "CLK_HROW_SE4BEG3_1", + "CLK_HROW_WW4C3_5", + "CLK_HROW_CK_GCLK_IN_TEST15", + "CLK_HROW_IMUX25_2", + "CLK_HROW_NW4A1_3", + "CLK_HROW_SE2A0_7", + "CLK_HROW_LH9_6", + "CLK_HROW_LOGIC_OUTS_B1_0", + "CLK_HROW_IMUX36_2", + "CLK_HROW_BYP2_1", + "CLK_HROW_EL1BEG0_7", + "CLK_HROW_IMUX47_1", + "CLK_HROW_BLOCK_OUTS_B1_6", + "CLK_HROW_WL1END2_1", + "CLK_HROW_WW2END2_2", + "CLK_HROW_NE4C2_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN0", + "CLK_HROW_WR1END1_7", + "CLK_HROW_EE4B2_5", + "CLK_HROW_IMUX33_0", + "CLK_HROW_WL1END3_6", + "CLK_HROW_WW4B1_3", + "CLK_HROW_CK_GCLK_TEST_OUT4", + "CLK_HROW_CK_BUFHCLK_L4", + "CLK_HROW_CK_MUX_OUT_L4", + "CLK_HROW_LOGIC_OUTS_B20_0", + "CLK_HROW_IMUX8_7", + "CLK_HROW_WR1END1_4", + "CLK_HROW_SE2A1_1", + "CLK_HROW_NE4BEG0_4", + "CLK_HROW_WW4C0_3", + "CLK_HROW_EL1BEG0_3", + "CLK_HROW_WW2END1_6", + "CLK_HROW_CK_HCLK_OUT_R9", + "CLK_HROW_EE4A0_4", + "CLK_HROW_LOGIC_OUTS_B16_1", + "CLK_HROW_EE2A3_5", + "CLK_HROW_IMUX12_2", + "CLK_HROW_EE2A3_0", + "CLK_HROW_WW4END1_7", + "CLK_HROW_WW4B2_6", + "CLK_HROW_EE4BEG3_7", + "CLK_HROW_R_CK_GCLK26", + "CLK_HROW_LOGIC_OUTS_B3_3", + "CLK_HROW_IMUX23_7", + "CLK_HROW_CK_GCLK_OUT_TEST5", + "CLK_HROW_SE4C0_4", + "CLK_HROW_SE2A0_6", + "CLK_HROW_EE4A1_5", + "CLK_HROW_CK_GCLK_IN_TEST0", + "CLK_HROW_EE4B3_6", + "CLK_HROW_CK_GCLK_TEST_OUT19", + "CLK_HROW_IMUX6_2", + "CLK_HROW_IMUX3_0", + "CLK_HROW_LH4_2", + "CLK_HROW_IMUX44_2", + "CLK_HROW_WR1END2_3", + "CLK_HROW_CK_MUX_OUT_L7", + "CLK_HROW_WW4B0_0", + "CLK_HROW_CK_GCLK_OUT_TEST13", + "CLK_HROW_LOGIC_OUTS_B9_4", + "CLK_HROW_SW4A1_0", + "CLK_HROW_BLOCK_OUTS_B3_2", + "CLK_HROW_NE2A1_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCO31", + "CLK_HROW_BYP3_1", + "CLK_HROW_EL1BEG2_3", + "CLK_HROW_IMUX5_7", + "CLK_HROW_WL1END0_5", + "CLK_HROW_IMUX6_5", + "CLK_HROW_R_CK_GCLK25", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN25", + "CLK_HROW_LH1_3", + "CLK_HROW_LH12_4", + "CLK_HROW_FAN1_3", + "CLK_HROW_CK_BUFRCLK_R1", + "CLK_HROW_WW2END2_1", + "CLK_HROW_CK_HCLK_OUT_L1", + "CLK_HROW_LOGIC_OUTS_B2_6", + "CLK_HROW_IMUX31_3", + "CLK_HROW_IMUX3_5", + "CLK_HROW_CK_IN_L4", + "CLK_HROW_WW4C0_5", + "CLK_HROW_CK_GCLK_OUT_TEST11", + "CLK_HROW_EL1BEG2_5", + "CLK_HROW_EE4BEG3_1", + "CLK_HROW_EE4BEG1_5", + "CLK_HROW_WW2A3_4", + "CLK_HROW_EE2BEG1_7", + "CLK_HROW_IMUX17_3", + "CLK_HROW_CK_BUFHCLK_L10", + "CLK_HROW_SE2A3_5", + "CLK_HROW_NE2A1_0", + "CLK_HROW_IMUX13_2", + "CLK_HROW_LOGIC_OUTS_B23_3", + "CLK_HROW_EL1BEG0_5", + "CLK_HROW_WL1END0_7", + "CLK_HROW_BUFHCE_CE_L3", + "CLK_HROW_SW4A1_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCO24", + "CLK_HROW_WW2A0_2", + "CLK_HROW_NW4A2_5", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN31", + "CLK_HROW_IMUX8_4", + "CLK_HROW_ER1BEG3_4", + "CLK_HROW_LH6_7", + "CLK_HROW_CK_GCLK_IN_TEST11", + "CLK_HROW_NE4C2_5", + "CLK_HROW_R_CK_GCLK8", + "CLK_HROW_BYP7_1", + "CLK_HROW_IMUX19_2", + "CLK_HROW_EE4C0_3", + "CLK_HROW_IMUX6_0", + "CLK_HROW_CLK0_2", + "CLK_HROW_FAN5_4", + "CLK_HROW_EE4C0_1", + "CLK_HROW_IMUX13_0", + "CLK_HROW_EL1BEG1_4", + "CLK_HROW_CTRL0_6", + "CLK_HROW_FAN7_0", + "CLK_HROW_BLOCK_OUTS_B0_7", + "CLK_HROW_EE4A2_1", + "CLK_HROW_EE4BEG1_1", + "CLK_HROW_SE4C3_1", + "CLK_HROW_EE2A1_3", + "CLK_HROW_CE_INT_TOP9", + "CLK_HROW_WW4END2_2", + "CLK_HROW_CK_IN_R9", + "CLK_HROW_IMUX10_3", + "CLK_HROW_SE4C3_4", + "CLK_HROW_WW2A3_0", + "CLK_HROW_IMUX6_1", + "CLK_HROW_BUFHCE_CE_R5", + "CLK_HROW_IMUX2_4", + "CLK_HROW_LOGIC_OUTS_B17_4", + "CLK_HROW_WL1END2_5", + "CLK_HROW_ER1BEG0_5", + "CLK_HROW_IMUX24_7", + "CLK_HROW_CK_GCLK_TEST18", + "CLK_HROW_CK_IN_R10", + "CLK_HROW_CK_IN_L_TEST_IN", + "CLK_HROW_EE4B2_7", + "CLK_HROW_NE4C1_5", + "CLK_HROW_WW4B3_3", + "CLK_HROW_WR1END0_7", + "CLK_HROW_IMUX1_1", + "CLK_HROW_ER1BEG1_5", + "CLK_HROW_EE2A3_2", + "CLK_HROW_LH1_7", + "CLK_HROW_IMUX45_2", + "CLK_HROW_WW2A3_1", + "CLK_HROW_WW4B3_1", + "CLK_HROW_NW4END3_3", + "CLK_HROW_CK_GCLK_OUT_TEST10", + "CLK_HROW_LOGIC_OUTS_B21_7", + "CLK_HROW_LOGIC_OUTS_B11_6", + "CLK_HROW_WW4A0_2", + "CLK_HROW_EE4C0_7", + "CLK_HROW_IMUX26_2", + "CLK_HROW_NE4C1_3", + "CLK_HROW_EE4B2_3", + "CLK_HROW_FAN3_1", + "CLK_HROW_IMUX4_5", + "CLK_HROW_FAN6_7", + "CLK_HROW_NW4END1_2", + "CLK_HROW_WR1END2_2", + "CLK_HROW_WW2A2_4", + "CLK_HROW_LOGIC_OUTS_B16_6", + "CLK_HROW_EE4C0_0", + "CLK_HROW_SE2A0_0", + "CLK_HROW_NE4C1_0", + "CLK_HROW_BYP5_6", + "CLK_HROW_CK_BUFHCLK_R2", + "CLK_HROW_IMUX1_7", + "CLK_HROW_SW4END3_0", + "CLK_HROW_IMUX18_4", + "CLK_HROW_ER1BEG0_4", + "CLK_HROW_CK_GCLK_IN_TEST28", + "CLK_HROW_IMUX35_1", + "CLK_HROW_NW4END1_6", + "CLK_HROW_IMUX33_4", + "CLK_HROW_IMUX36_7", + "CLK_HROW_CK_GCLK_TEST_IN25", + "CLK_HROW_IMUX1_6", + "CLK_HROW_SW4END0_0", + "CLK_HROW_EE4B2_4", + "CLK_HROW_WR1END1_5", + "CLK_HROW_WL1END2_3", + "CLK_HROW_FAN7_1", + "CLK_HROW_EE4BEG2_6", + "CLK_HROW_IMUX17_1", + "CLK_HROW_CK_GCLK_TEST12", + "CLK_HROW_LOGIC_OUTS_B12_0", + "CLK_HROW_IMUX22_2", + "CLK_HROW_WL1END3_5", + "CLK_HROW_LH6_0", + "CLK_HROW_LH7_0", + "CLK_HROW_LOGIC_OUTS_B14_2", + "CLK_HROW_CK_GCLK_TEST_IN10", + "CLK_HROW_SW2A3_7", + "CLK_HROW_EL1BEG3_5", + "CLK_HROW_SW4A3_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN5", + "CLK_HROW_CK_GCLK_TEST_OUT13", + "CLK_HROW_WW2A0_6", + "CLK_HROW_IMUX25_3", + "CLK_HROW_CK_GCLK_IN_TEST8", + "CLK_HROW_SW2A2_1", + "CLK_HROW_CK_GCLK_IN_TEST19", + "CLK_HROW_EE2BEG0_0", + "CLK_HROW_IMUX1_0", + "CLK_HROW_CK_GCLK_TEST_IN13", + "CLK_HROW_SE4BEG3_6", + "CLK_HROW_BLOCK_OUTS_B0_1", + "CLK_HROW_EE2BEG1_5", + "CLK_HROW_IMUX46_2", + "CLK_HROW_LOGIC_OUTS_B6_3", + "CLK_HROW_WW2A1_3", + "CLK_HROW_SW4A0_5", + "CLK_HROW_IMUX41_6", + "CLK_HROW_LH11_7", + "CLK_HROW_EE4A1_2", + "CLK_HROW_NE4BEG1_2", + "CLK_HROW_CK_GCLK_TEST_IN31", + "CLK_HROW_NW2A2_0", + "CLK_HROW_LOGIC_OUTS_B7_7", + "CLK_HROW_BYP5_4", + "CLK_HROW_EE4C1_7", + "CLK_HROW_CE_INT_TOP1", + "CLK_HROW_IMUX19_5", + "CLK_HROW_R_CK_GCLK9", + "CLK_HROW_CK_IN_L0", + "CLK_HROW_CK_BUFHCLK_L6", + "CLK_HROW_IMUX47_5", + "CLK_HROW_IMUX41_1", + "CLK_HROW_EE2A3_3", + "CLK_HROW_SW4END2_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN21", + "CLK_HROW_NW2A2_6", + "CLK_HROW_FAN0_7", + "CLK_HROW_CK_IN_L_IN_TEST", + "CLK_HROW_LOGIC_OUTS_B23_1", + "CLK_HROW_CK_GCLK_TEST14", + "CLK_HROW_NE4C0_1", + "CLK_HROW_EE4C3_2", + "CLK_HROW_CK_GCLK_OUT_TEST15", + "CLK_HROW_LOGIC_OUTS_B0_5", + "CLK_HROW_EE2A2_1", + "CLK_HROW_EE2BEG0_6", + "CLK_HROW_EE4BEG1_2", + "CLK_HROW_WW4A0_1", + "CLK_HROW_ER1BEG3_2", + "CLK_HROW_BLOCK_OUTS_B0_4", + "CLK_HROW_EE4B0_7", + "CLK_HROW_IMUX4_1", + "CLK_HROW_LH7_7", + "CLK_HROW_BUFHCE_CE_L0", + "CLK_HROW_CK_HCLK_OUT_R1", + "CLK_HROW_CK_GCLK_TEST_IN22", + "CLK_HROW_LOGIC_OUTS_B19_0", + "CLK_HROW_CK_GCLK_OUT_TEST26", + "CLK_HROW_IMUX22_1", + "CLK_HROW_CK_GCLK_OUT_TEST30", + "CLK_HROW_IMUX26_4", + "CLK_HROW_BUFHCE_CE_R4", + "CLK_HROW_LOGIC_OUTS_B9_1", + "CLK_HROW_EE4BEG3_5", + "CLK_HROW_EE4A1_3", + "CLK_HROW_LOGIC_OUTS_B12_4", + "CLK_HROW_LH11_2", + "CLK_HROW_SE4C1_4", + "CLK_HROW_FAN6_4", + "CLK_HROW_CK_GCLK_TEST4", + "CLK_HROW_IMUX16_5", + "CLK_HROW_EE4B1_4", + "CLK_HROW_LOGIC_OUTS_B9_6", + "CLK_HROW_IMUX2_0", + "CLK_HROW_EE4B0_0", + "CLK_HROW_NE4BEG1_5", + "CLK_HROW_FAN6_0", + "CLK_HROW_SE4C0_6", + "CLK_HROW_EE2BEG0_1", + "CLK_HROW_WW4C0_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN4", + "CLK_HROW_SW4END3_7", + "CLK_HROW_LH10_1", + "CLK_HROW_BYP0_3", + "CLK_HROW_IMUX12_6", + "CLK_HROW_EE4C1_3", + "CLK_HROW_CTRL1_2", + "CLK_HROW_CK_GCLK_TEST24", + "CLK_HROW_CK_IN_L1", + "CLK_HROW_CK_BUFRCLK_L2", + "CLK_HROW_EE2BEG1_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCO12", + "CLK_HROW_IMUX0_2", + "CLK_HROW_LOGIC_OUTS_B11_5", + "CLK_HROW_CK_MUX_OUT_L8", + "CLK_HROW_CE_INT_BOT11", + "CLK_HROW_IMUX3_1", + "CLK_HROW_LH5_3", + "CLK_HROW_IMUX31_0", + "CLK_HROW_R_CK_GCLK21", + "CLK_HROW_BYP3_6", + "CLK_HROW_SW4END2_5", + "CLK_HROW_SW4END3_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCO28", + "CLK_HROW_CK_IN_L8", + "CLK_HROW_NW4A2_6", + "CLK_HROW_SE4BEG0_5", + "CLK_HROW_LH3_0", + "CLK_HROW_BLOCK_OUTS_B1_2", + "CLK_HROW_CK_GCLK_TEST27", + "CLK_HROW_WW2A1_1", + "CLK_HROW_NW4END2_5", + "CLK_HROW_NW2A0_7", + "CLK_HROW_WR1END3_4", + "CLK_HROW_ER1BEG0_7", + "CLK_HROW_EL1BEG3_4", + "CLK_HROW_NW4END3_1", + "CLK_HROW_LOGIC_OUTS_B10_3", + "CLK_HROW_CK_MUX_OUT_R6", + "CLK_HROW_BUFHCE_CE_R1", + "CLK_HROW_LH9_2", + "CLK_HROW_SW4A3_7", + "CLK_HROW_IMUX27_4", + "CLK_HROW_FAN2_1", + "CLK_HROW_CE_INT_TOP8", + "CLK_HROW_IMUX1_5", + "CLK_HROW_LH10_0", + "CLK_HROW_IMUX14_1", + "CLK_HROW_ER1BEG0_1", + "CLK_HROW_EE4C1_5", + "CLK_HROW_EE2BEG3_0", + "CLK_HROW_IMUX2_1", + "CLK_HROW_CK_IN_R13", + "CLK_HROW_SE4C0_7", + "CLK_HROW_ER1BEG1_1", + "CLK_HROW_BUFHCE_CE_R0", + "CLK_HROW_MONITOR_P_2", + "CLK_HROW_LH8_7", + "CLK_HROW_WW2A2_3", + "CLK_HROW_IMUX36_3", + "CLK_HROW_LOGIC_OUTS_B4_2", + "CLK_HROW_IMUX0_1", + "CLK_HROW_SE4C1_0", + "CLK_HROW_EE4B3_4", + "CLK_HROW_IMUX42_4", + "CLK_HROW_LOGIC_OUTS_B22_1", + "CLK_HROW_IMUX5_1", + "CLK_HROW_CK_GCLK_TEST_IN8", + "CLK_HROW_CE_INT_BOT0", + "CLK_HROW_LH2_5", + "CLK_HROW_BYP6_4", + "CLK_HROW_NW4END0_2", + "CLK_HROW_WW2END0_2", + "CLK_HROW_CE_INT_TOP4", + "CLK_HROW_EE4B3_5", + "CLK_HROW_SE4C3_6", + "CLK_HROW_EE4BEG0_3", + "CLK_HROW_LH1_2", + "CLK_HROW_LOGIC_OUTS_B15_7", + "CLK_HROW_SW4A0_4", + "CLK_HROW_IMUX10_0", + "CLK_HROW_WW4B0_6", + "CLK_HROW_CE_INT_BOT4", + "CLK_HROW_NE2A0_6", + "CLK_HROW_BYP1_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCO15", + "CLK_HROW_CK_HCLK_OUT_R4", + "CLK_HROW_BUFHCE_CE_L8", + "CLK_HROW_BLOCK_OUTS_B1_1", + "CLK_HROW_LOGIC_OUTS_B9_7", + "CLK_HROW_WW4A2_4", + "CLK_HROW_EL1BEG1_7", + "CLK_HROW_EE4C2_3", + "CLK_HROW_FAN3_5", + "CLK_HROW_LH11_5", + "CLK_HROW_IMUX25_1", + "CLK_HROW_BUFHCE_CE_R8", + "CLK_HROW_LOGIC_OUTS_B5_2", + "CLK_HROW_IMUX24_6", + "CLK_HROW_IMUX23_4", + "CLK_HROW_ER1BEG1_2", + "CLK_HROW_WW4END0_0", + "CLK_HROW_LOGIC_OUTS_B20_6", + "CLK_HROW_FAN4_7", + "CLK_HROW_SW4A3_5", + "CLK_HROW_BYP4_3", + "CLK_HROW_EE4A3_6", + "CLK_HROW_EE4A2_5", + "CLK_HROW_WW2END0_1", + "CLK_HROW_CK_GCLK_TEST19", + "CLK_HROW_CK_IN_L10", + "CLK_HROW_LOGIC_OUTS_B11_3", + "CLK_HROW_EE4A1_0", + "CLK_HROW_EE4B1_7", + "CLK_HROW_EE2A3_7", + "CLK_HROW_IMUX18_5", + "CLK_HROW_IMUX1_2", + "CLK_HROW_IMUX37_7", + "CLK_HROW_CK_BUFRCLK_L0", + "CLK_HROW_WW4C3_3", + "CLK_HROW_CK_MUX_OUT_R1", + "CLK_HROW_LOGIC_OUTS_B19_1", + "CLK_HROW_SE4BEG3_0", + "CLK_HROW_SE4C1_7", + "CLK_HROW_CK_GCLK_TEST_IN2", + "CLK_HROW_WW2END3_5", + "CLK_HROW_NE4BEG1_7", + "CLK_HROW_IMUX35_3", + "CLK_HROW_IMUX4_0", + "CLK_HROW_BYP2_6", + "CLK_HROW_REFCK_WESTCLK1", + "CLK_HROW_IMUX22_0", + "CLK_HROW_NW4A2_0", + "CLK_HROW_CK_BUFHCLK_R6", + "CLK_HROW_IMUX29_7", + "CLK_HROW_LH12_0", + "CLK_HROW_EE2BEG3_5", + "CLK_HROW_IMUX15_2", + "CLK_HROW_NW2A1_2", + "CLK_HROW_R_CK_GCLK30", + "CLK_HROW_CK_GCLK_TEST23", + "CLK_HROW_NW4A1_7", + "CLK_HROW_WR1END3_7", + "CLK_HROW_NW2A1_6", + "CLK_HROW_EE4A3_1", + "CLK_HROW_BYP4_4", + "CLK_HROW_BYP5_2", + "CLK_HROW_IMUX21_0", + "CLK_HROW_EE2A2_7", + "CLK_HROW_IMUX15_4", + "CLK_HROW_LOGIC_OUTS_B1_7", + "CLK_HROW_WR1END0_3", + "CLK_HROW_IMUX38_0", + "CLK_HROW_WW2END2_5", + "CLK_HROW_LH6_2", + "CLK_HROW_EE4BEG0_5", + "CLK_HROW_CK_GCLK_OUT_TEST6", + "CLK_HROW_LOGIC_OUTS_B17_5", + "CLK_HROW_NW4A1_2", + "CLK_HROW_R_CK_GCLK17", + "CLK_HROW_NE4BEG1_6", + "CLK_HROW_LOGIC_OUTS_B0_0", + "CLK_HROW_SE2A2_3", + "CLK_HROW_WW4END1_6", + "CLK_HROW_IMUX38_2", + "CLK_HROW_LOGIC_OUTS_B16_7", + "CLK_HROW_R_CK_GCLK27", + "CLK_HROW_WW2A3_3", + "CLK_HROW_IMUX18_7", + "CLK_HROW_WW4B2_2", + "CLK_HROW_ER1BEG2_5", + "CLK_HROW_IMUX26_0", + "CLK_HROW_NW4A3_5", + "CLK_HROW_LOGIC_OUTS_B2_5", + "CLK_HROW_LOGIC_OUTS_B3_7", + "CLK_HROW_LH2_4", + "CLK_HROW_CK_GCLK_TEST9", + "CLK_HROW_NW4END0_1", + "CLK_HROW_LH8_1", + "CLK_HROW_BYP6_3", + "CLK_HROW_LOGIC_OUTS_B0_7", + "CLK_HROW_LOGIC_OUTS_B19_3", + "CLK_HROW_CK_INT_0_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCO1", + "CLK_HROW_EE4A2_0", + "CLK_HROW_SE2A1_7", + "CLK_HROW_IMUX28_1", + "CLK_HROW_LOGIC_OUTS_B21_0", + "CLK_HROW_IMUX31_4", + "CLK_HROW_EE4BEG1_6", + "CLK_HROW_MONITOR_P_4", + "CLK_HROW_LOGIC_OUTS_B20_2", + "CLK_HROW_CK_GCLK_IN_TEST4", + "CLK_HROW_SW4END3_5", + "CLK_HROW_LH1_5", + "CLK_HROW_NE4C3_0", + "CLK_HROW_LH6_3", + "CLK_HROW_BYP0_2", + "CLK_HROW_SW2A1_6", + "CLK_HROW_FAN2_4", + "CLK_HROW_EE2A0_0", + "CLK_HROW_SW4END0_7", + "CLK_HROW_CE_INT_TOP6", + "CLK_HROW_LOGIC_OUTS_B2_7", + "CLK_HROW_IMUX28_0", + "CLK_HROW_SE4C1_3", + "CLK_HROW_IMUX26_7", + "CLK_HROW_LOGIC_OUTS_B15_2", + "CLK_HROW_IMUX24_0", + "CLK_HROW_IMUX36_6", + "CLK_HROW_WW4B2_3", + "CLK_HROW_FAN6_2", + "CLK_HROW_IMUX25_4", + "CLK_HROW_IMUX27_5", + "CLK_HROW_SE2A3_7", + "CLK_HROW_IMUX7_7", + "CLK_HROW_LOGIC_OUTS_B7_6", + "CLK_HROW_NW2A0_5", + "CLK_HROW_NE4BEG0_0", + "CLK_HROW_WR1END0_0", + "CLK_HROW_LOGIC_OUTS_B17_1", + "CLK_HROW_WW2END3_1", + "CLK_HROW_IMUX39_1", + "CLK_HROW_LOGIC_OUTS_B14_6", + "CLK_HROW_WL1END1_3", + "CLK_HROW_EE2A2_0", + "CLK_HROW_SW2A2_5", + "CLK_HROW_IMUX28_4", + "CLK_HROW_CK_GCLK_TEST_IN3", + "CLK_HROW_NW4END3_7", + "CLK_HROW_IMUX9_7", + "CLK_HROW_SE4BEG2_2", + "CLK_HROW_WW2A1_4", + "CLK_HROW_IMUX44_1", + "CLK_HROW_EE4B3_0", + "CLK_HROW_IMUX29_2", + "CLK_HROW_BYP2_4", + "CLK_HROW_BYP1_1", + "CLK_HROW_SW4END1_1", + "CLK_HROW_SE4BEG1_1", + "CLK_HROW_R_CK_GCLK23", + "CLK_HROW_IMUX0_6", + "CLK_HROW_LOGIC_OUTS_B18_5", + "CLK_HROW_R_CK_GCLK3", + "CLK_HROW_CK_GCLK_TEST_OUT26", + "CLK_HROW_CK_GCLK_TEST25", + "CLK_HROW_WL1END2_6", + "CLK_HROW_FAN1_6", + "CLK_HROW_WL1END0_4", + "CLK_HROW_CK_GCLK_TEST20", + "CLK_HROW_WW4B2_0", + "CLK_HROW_WW4B3_2", + "CLK_HROW_R_CK_GCLK16", + "CLK_HROW_WW4A1_6", + "CLK_HROW_WW2END3_7", + "CLK_HROW_SE4C3_5", + "CLK_HROW_ER1BEG0_3", + "CLK_HROW_CK_HCLK_OUT_R7", + "CLK_HROW_FAN6_1", + "CLK_HROW_LH11_3", + "CLK_HROW_IMUX44_7", + "CLK_HROW_CK_HCLK_OUT_L3", + "CLK_HROW_EE4BEG0_1", + "CLK_HROW_CK_MUX_OUT_R11", + "CLK_HROW_IMUX42_1", + "CLK_HROW_BYP0_6", + "CLK_HROW_NE2A3_5", + "CLK_HROW_SW4END0_6", + "CLK_HROW_EE4C3_3", + "CLK_HROW_BLOCK_OUTS_B0_3", + "CLK_HROW_CK_GCLK_TEST_OUT16", + "CLK_HROW_EE2BEG1_0", + "CLK_HROW_LOGIC_OUTS_B7_5", + "CLK_HROW_LOGIC_OUTS_B10_4", + "CLK_HROW_NE4BEG1_3", + "CLK_HROW_WW4C3_1", + "CLK_HROW_SW4A3_0", + "CLK_HROW_NW2A0_0", + "CLK_HROW_WW4A3_6", + "CLK_HROW_NE4BEG0_2", + "CLK_HROW_IMUX4_6", + "CLK_HROW_LOGIC_OUTS_B20_1", + "CLK_HROW_ER1BEG2_4", + "CLK_HROW_EE2A1_2", + "CLK_HROW_R_CK_GCLK10", + "CLK_HROW_IMUX35_0", + "CLK_HROW_LOGIC_OUTS_B18_6", + "CLK_HROW_EL1BEG2_2", + "CLK_HROW_IMUX26_1", + "CLK_HROW_FAN5_5", + "CLK_HROW_CK_GCLK_TEST_IN27", + "CLK_HROW_EE4BEG2_3", + "CLK_HROW_WW2END1_1", + "CLK_HROW_LOGIC_OUTS_B19_6", + "CLK_HROW_EE2A0_5", + "CLK_HROW_SW2A1_3", + "CLK_HROW_NE4BEG1_4", + "CLK_HROW_CK_GCLK_TEST_OUT10", + "CLK_HROW_IMUX13_1", + "CLK_HROW_LOGIC_OUTS_B15_1", + "CLK_HROW_LOGIC_OUTS_B12_2", + "CLK_HROW_LH6_4", + "CLK_HROW_CK_HCLK_OUT_L4", + "CLK_HROW_LOGIC_OUTS_B21_5", + "CLK_HROW_NE2A3_0", + "CLK_HROW_WW4A1_3", + "CLK_HROW_CTRL1_5", + "CLK_HROW_LOGIC_OUTS_B13_6", + "CLK_HROW_IMUX41_7", + "CLK_HROW_SE4C2_3", + "CLK_HROW_IMUX36_4", + "CLK_HROW_WR1END3_1", + "CLK_HROW_WW4C1_3", + "CLK_HROW_CK_GCLK_TEST21", + "CLK_HROW_CK_GCLK_TEST_OUT15", + "CLK_HROW_NW2A1_0", + "CLK_HROW_NE4BEG1_0", + "CLK_HROW_EE4C1_1", + "CLK_HROW_CK_GCLK_IN_TEST9", + "CLK_HROW_IMUX34_0", + "CLK_HROW_CE_INT_BOT9", + "CLK_HROW_LOGIC_OUTS_B12_5", + "CLK_HROW_WL1END0_1", + "CLK_HROW_IMUX37_3", + "CLK_HROW_LOGIC_OUTS_B0_1", + "CLK_HROW_LOGIC_OUTS_B19_4", + "CLK_HROW_SW2A2_7", + "CLK_HROW_LH3_6", + "CLK_HROW_WL1END1_4", + "CLK_HROW_WW2A2_7", + "CLK_HROW_CK_BUFHCLK_R0", + "CLK_HROW_WW4A1_7", + "CLK_HROW_WW4END2_6", + "CLK_HROW_CLK1_7", + "CLK_HROW_SW4A0_1", + "CLK_HROW_CK_GCLK_TEST_OUT25", + "CLK_HROW_WW2A1_5", + "CLK_HROW_IMUX27_6", + "CLK_HROW_IMUX40_4", + "CLK_HROW_IMUX14_3", + "CLK_HROW_LH10_6", + "CLK_HROW_EL1BEG1_0", + "CLK_HROW_CK_BUFHCLK_R8", + "CLK_HROW_WW4C0_7", + "CLK_HROW_SE4C0_0", + "CLK_HROW_EE4A3_2", + "CLK_HROW_IMUX42_7", + "CLK_HROW_IMUX5_6", + "CLK_HROW_SW2A3_5", + "CLK_HROW_WR1END0_4", + "CLK_HROW_WW4C2_5", + "CLK_HROW_IMUX16_4", + "CLK_HROW_LOGIC_OUTS_B12_7", + "CLK_HROW_ER1BEG0_2", + "CLK_HROW_LOGIC_OUTS_B11_1", + "CLK_HROW_CK_GCLK_TEST_OUT23", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN13", + "CLK_HROW_BYP0_1", + "CLK_HROW_IMUX13_7", + "CLK_HROW_NE4BEG2_4", + "CLK_HROW_CE_INT_TOP0", + "CLK_HROW_EE2BEG2_2", + "CLK_HROW_IMUX9_5", + "CLK_HROW_IMUX27_1", + "CLK_HROW_LOGIC_OUTS_B12_6", + "CLK_HROW_WL1END0_2", + "CLK_HROW_IMUX7_3", + "CLK_HROW_SW4END0_3", + "CLK_HROW_LOGIC_OUTS_B15_3", + "CLK_HROW_BLOCK_OUTS_B2_0", + "CLK_HROW_FAN0_2", + "CLK_HROW_SW2A0_2", + "CLK_HROW_WR1END1_0", + "CLK_HROW_WW4B0_4", + "CLK_HROW_WW2END0_3", + "CLK_HROW_IMUX11_3", + "CLK_HROW_BYP6_2", + "CLK_HROW_WW4A3_2", + "CLK_HROW_EE4B1_3", + "CLK_HROW_R_CK_GCLK11", + "CLK_HROW_FAN3_0", + "CLK_HROW_SE4C2_7", + "CLK_HROW_LOGIC_OUTS_B6_1", + "CLK_HROW_LH8_0", + "CLK_HROW_WL1END2_4", + "CLK_HROW_IMUX44_0", + "CLK_HROW_EE4B0_5", + "CLK_HROW_CE_INT_BOT2", + "CLK_HROW_CK_IN_R1", + "CLK_HROW_WW2A2_0", + "CLK_HROW_SE4BEG1_5", + "CLK_HROW_WW4A0_4", + "CLK_HROW_NE2A3_6", + "CLK_HROW_SW4A2_7", + "CLK_HROW_NE4C3_3", + "CLK_HROW_NW4A0_0", + "CLK_HROW_LOGIC_OUTS_B3_2", + "CLK_HROW_ER1BEG1_3", + "CLK_HROW_LOGIC_OUTS_B18_4", + "CLK_HROW_CK_GCLK_IN_TEST29", + "CLK_HROW_LH10_4", + "CLK_HROW_IMUX18_0", + "CLK_HROW_NW4END0_6", + "CLK_HROW_IMUX9_2", + "CLK_HROW_FAN4_5", + "CLK_HROW_IMUX4_2", + "CLK_HROW_MONITOR_N_2", + "CLK_HROW_EE4BEG1_3", + "CLK_HROW_LOGIC_OUTS_B3_6", + "CLK_HROW_LOGIC_OUTS_B21_2", + "CLK_HROW_R_CK_GCLK18", + "CLK_HROW_CK_HCLK_OUT_L8", + "CLK_HROW_EE2BEG3_7", + "CLK_HROW_IMUX23_2", + "CLK_HROW_SW4END2_0", + "CLK_HROW_LH4_1", + "CLK_HROW_CK_HCLK_OUT_R3", + "CLK_HROW_CK_MUX_OUT_R0", + "CLK_HROW_IMUX45_4", + "CLK_HROW_IMUX43_2", + "CLK_HROW_LOGIC_OUTS_B12_3", + "CLK_HROW_NW4END1_7", + "CLK_HROW_IMUX11_6", + "CLK_HROW_IMUX35_5", + "CLK_HROW_LH10_5", + "CLK_HROW_ER1BEG3_1", + "CLK_HROW_IMUX47_7", + "CLK_HROW_BUFHCE_CE_L6", + "CLK_HROW_LOGIC_OUTS_B10_6", + "CLK_HROW_NW4END2_0", + "CLK_HROW_SW4A0_2", + "CLK_HROW_NE4BEG2_0", + "CLK_HROW_LOGIC_OUTS_B7_4", + "CLK_HROW_WW4END2_5", + "CLK_HROW_FAN1_7", + "CLK_HROW_IMUX45_3", + "CLK_HROW_NE4BEG1_1", + "CLK_HROW_LH9_5", + "CLK_HROW_BUFHCE_CE_R9", + "CLK_HROW_NE4BEG3_2", + "CLK_HROW_EE4B2_6", + "CLK_HROW_WW4END2_3", + "CLK_HROW_CK_MUX_OUT_L5", + "CLK_HROW_IMUX21_5", + "CLK_HROW_LOGIC_OUTS_B5_3", + "CLK_HROW_NW2A3_7", + "CLK_HROW_LOGIC_OUTS_B10_2", + "CLK_HROW_CK_GCLK_TEST_OUT29", + "CLK_HROW_WW4END2_0", + "CLK_HROW_CK_HCLK_OUT_L11", + "CLK_HROW_CK_GCLK_TEST13", + "CLK_HROW_WR1END2_5", + "CLK_HROW_CK_GCLK_TEST_OUT30", + "CLK_HROW_IMUX23_0", + "CLK_HROW_LOGIC_OUTS_B18_2", + "CLK_HROW_CK_BUFHCLK_R10", + "CLK_HROW_WW4A2_2", + "CLK_HROW_CK_IN_L_TEST_OUT", + "CLK_HROW_IMUX8_2", + "CLK_HROW_IMUX2_6", + "CLK_HROW_BYP7_3", + "CLK_HROW_LOGIC_OUTS_B23_4", + "CLK_HROW_IMUX21_6", + "CLK_HROW_CK_GCLK_IN_TEST12", + "CLK_HROW_LH5_7", + "CLK_HROW_SW4END1_2", + "CLK_HROW_IMUX9_4", + "CLK_HROW_CK_IN_L13", + "CLK_HROW_IMUX47_0", + "CLK_HROW_BUFHCE_CE_L10", + "CLK_HROW_WW2END3_2", + "CLK_HROW_NW4END1_5", + "CLK_HROW_BLOCK_OUTS_B1_5", + "CLK_HROW_LOGIC_OUTS_B18_1", + "CLK_HROW_IMUX40_2", + "CLK_HROW_SE4C2_1", + "CLK_HROW_CK_BUFHCLK_R5", + "CLK_HROW_WW4END1_1", + "CLK_HROW_WL1END1_7", + "CLK_HROW_BYP1_0", + "CLK_HROW_FAN2_2", + "CLK_HROW_CK_GCLK_TEST_OUT20", + "CLK_HROW_LOGIC_OUTS_B13_0", + "CLK_HROW_IMUX11_0", + "CLK_HROW_CK_BUFHCLK_L11", + "CLK_HROW_NW2A1_3", + "CLK_HROW_EL1BEG0_6", + "CLK_HROW_WW4C1_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCO26", + "CLK_HROW_SW4A2_1", + "CLK_HROW_WW4B0_2", + "CLK_HROW_BLOCK_OUTS_B3_7", + "CLK_HROW_LOGIC_OUTS_B18_3", + "CLK_HROW_ER1BEG3_5", + "CLK_HROW_BYP2_2", + "CLK_HROW_CK_GCLK_OUT_TEST12", + "CLK_HROW_LOGIC_OUTS_B20_7", + "CLK_HROW_WW4C0_2", + "CLK_HROW_WW2A0_0", + "CLK_HROW_BUFHCE_CE_R11", + "CLK_HROW_IMUX44_3", + "CLK_HROW_WW4B2_7", + "CLK_HROW_CK_HCLK_OUT_L6", + "CLK_HROW_CLK0_4", + "CLK_HROW_WW4END0_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN30", + "CLK_HROW_IMUX14_2", + "CLK_HROW_IMUX5_2", + "CLK_HROW_CLK0_7", + "CLK_HROW_BUFHCE_CE_L1", + "CLK_HROW_WW4END1_5", + "CLK_HROW_LOGIC_OUTS_B12_1", + "CLK_HROW_WR1END2_4", + "CLK_HROW_FAN1_5", + "CLK_HROW_IMUX2_5", + "CLK_HROW_CE_INT_TOP5", + "CLK_HROW_IMUX41_2", + "CLK_HROW_IMUX16_6", + "CLK_HROW_IMUX4_4", + "CLK_HROW_WW2A3_7", + "CLK_HROW_EE2BEG0_7", + "CLK_HROW_WW4B1_7", + "CLK_HROW_WW2A0_7", + "CLK_HROW_FAN2_0", + "CLK_HROW_IMUX7_2", + "CLK_HROW_WL1END0_0", + "CLK_HROW_CK_GCLK_OUT_TEST27", + "CLK_HROW_NE2A3_4", + "CLK_HROW_ER1BEG1_7", + "CLK_HROW_LOGIC_OUTS_B1_3", + "CLK_HROW_EE2BEG1_4", + "CLK_HROW_IMUX29_4", + "CLK_HROW_BYP3_5", + "CLK_HROW_SW2A2_2", + "CLK_HROW_CTRL1_6", + "CLK_HROW_IMUX21_1", + "CLK_HROW_WW4A0_6", + "CLK_HROW_CK_BUFRCLK_R3", + "CLK_HROW_BYP6_0", + "CLK_HROW_EE4A3_0", + "CLK_HROW_LOGIC_OUTS_B5_1", + "CLK_HROW_EE2A1_6", + "CLK_HROW_R_CK_GCLK4", + "CLK_HROW_NW4END0_0", + "CLK_HROW_LOGIC_OUTS_B8_7", + "CLK_HROW_NW4END3_6", + "CLK_HROW_CK_GCLK_TEST_IN28", + "CLK_HROW_LOGIC_OUTS_B5_6", + "CLK_HROW_BYP4_6", + "CLK_HROW_SW4A1_6", + "CLK_HROW_LOGIC_OUTS_B9_0", + "CLK_HROW_WW4A2_5", + "CLK_HROW_TOP_R_CK_BUFG_CASCO9", + "CLK_HROW_IMUX39_4", + "CLK_HROW_FAN4_1", + "CLK_HROW_SW4A3_4", + "CLK_HROW_LH7_2", + "CLK_HROW_CK_GCLK_OUT_TEST8", + "CLK_HROW_IMUX21_4", + "CLK_HROW_IMUX40_0", + "CLK_HROW_LOGIC_OUTS_B14_1", + "CLK_HROW_WW4END1_3", + "CLK_HROW_EE4C0_6", + "CLK_HROW_NE4C2_7", + "CLK_HROW_IMUX34_1", + "CLK_HROW_NE4C0_7", + "CLK_HROW_LH3_1", + "CLK_HROW_IMUX24_2", + "CLK_HROW_SE2A1_5", + "CLK_HROW_SW2A1_1", + "CLK_HROW_SW4END3_6", + "CLK_HROW_IMUX3_3", + "CLK_HROW_CTRL1_3", + "CLK_HROW_LOGIC_OUTS_B2_2", + "CLK_HROW_NW4END1_1", + "CLK_HROW_WW4C2_3", + "CLK_HROW_WW2END0_0", + "CLK_HROW_ER1BEG2_1", + "CLK_HROW_NW4A0_6", + "CLK_HROW_CK_GCLK_TEST_IN11", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN15", + "CLK_HROW_LH2_1", + "CLK_HROW_NE4BEG0_6", + "CLK_HROW_IMUX7_6", + "CLK_HROW_LH4_0", + "CLK_HROW_IMUX37_0", + "CLK_HROW_EE4B2_1", + "CLK_HROW_NW2A3_2", + "CLK_HROW_IMUX47_6", + "CLK_HROW_SE2A2_5", + "CLK_HROW_IMUX7_5", + "CLK_HROW_NE4C0_0", + "CLK_HROW_MONITOR_P_6", + "CLK_HROW_CK_GCLK_TEST2", + "CLK_HROW_LH12_5", + "CLK_HROW_LH1_1", + "CLK_HROW_LOGIC_OUTS_B5_5", + "CLK_HROW_IMUX25_7", + "CLK_HROW_IMUX12_5", + "CLK_HROW_MONITOR_P_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN24", + "CLK_HROW_WL1END3_3", + "CLK_HROW_IMUX30_6", + "CLK_HROW_WW2END1_5", + "CLK_HROW_LOGIC_OUTS_B22_6", + "CLK_HROW_WR1END3_0", + "CLK_HROW_MONITOR_P_7", + "CLK_HROW_IMUX17_7", + "CLK_HROW_IMUX45_5", + "CLK_HROW_LOGIC_OUTS_B13_2", + "CLK_HROW_IMUX37_5", + "CLK_HROW_CK_INT_1_1", + "CLK_HROW_BLOCK_OUTS_B2_6", + "CLK_HROW_CK_GCLK_TEST_OUT14", + "CLK_HROW_IMUX19_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN3", + "CLK_HROW_WW4END1_0", + "CLK_HROW_BLOCK_OUTS_B1_0", + "CLK_HROW_SW4A0_7", + "CLK_HROW_LOGIC_OUTS_B5_0", + "CLK_HROW_LH8_5", + "CLK_HROW_CK_HCLK_OUT_R2", + "CLK_HROW_BYP7_6", + "CLK_HROW_LOGIC_OUTS_B14_5", + "CLK_HROW_NE4C1_4", + "CLK_HROW_IMUX21_7", + "CLK_HROW_EE4C3_7", + "CLK_HROW_SW4A2_2", + "CLK_HROW_SE4C2_0", + "CLK_HROW_EE2A0_2", + "CLK_HROW_CK_GCLK_TEST_OUT6", + "CLK_HROW_BLOCK_OUTS_B3_1", + "CLK_HROW_CK_BUFRCLK_R2", + "CLK_HROW_WW4END3_3", + "CLK_HROW_SW2A2_6", + "CLK_HROW_SW4END0_2", + "CLK_HROW_IMUX18_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN22", + "CLK_HROW_MONITOR_N_5", + "CLK_HROW_WW4A1_1", + "CLK_HROW_LOGIC_OUTS_B15_6", + "CLK_HROW_LOGIC_OUTS_B10_0", + "CLK_HROW_LOGIC_OUTS_B18_7", + "CLK_HROW_IMUX39_7", + "CLK_HROW_IMUX25_5", + "CLK_HROW_EE4B3_3", + "CLK_HROW_CTRL0_3", + "CLK_HROW_IMUX42_6", + "CLK_HROW_CK_GCLK_TEST_OUT31", + "CLK_HROW_BYP1_2", + "CLK_HROW_CK_GCLK_TEST_IN6", + "CLK_HROW_BUFHCE_CE_R2", + "CLK_HROW_NW2A1_1", + "CLK_HROW_IMUX22_7", + "CLK_HROW_IMUX33_7", + "CLK_HROW_CK_GCLK_OUT_TEST1", + "CLK_HROW_SW4END1_6", + "CLK_HROW_BYP4_1", + "CLK_HROW_LOGIC_OUTS_B14_3", + "CLK_HROW_CLK0_3", + "CLK_HROW_CK_BUFHCLK_R9", + "CLK_HROW_CK_IN_R_TEST_OUT", + "CLK_HROW_CK_GCLK_TEST_IN5", + "CLK_HROW_NE4C2_3", + "CLK_HROW_WW4B0_1", + "CLK_HROW_SW2A1_7", + "CLK_HROW_IMUX28_5", + "CLK_HROW_CE_INT_BOT6", + "CLK_HROW_IMUX14_6", + "CLK_HROW_CK_GCLK_TEST_IN17", + "CLK_HROW_SW2A0_6", + "CLK_HROW_SW2A0_4", + "CLK_HROW_CK_MUX_OUT_R8", + "CLK_HROW_IMUX44_5", + "CLK_HROW_LOGIC_OUTS_B5_7", + "CLK_HROW_CLK1_2", + "CLK_HROW_CTRL0_4", + "CLK_HROW_WR1END2_0", + "CLK_HROW_LOGIC_OUTS_B3_5", + "CLK_HROW_IMUX23_3", + "CLK_HROW_SW2A0_0", + "CLK_HROW_IMUX18_2", + "CLK_HROW_IMUX37_6", + "CLK_HROW_WW4END3_2", + "CLK_HROW_SE4BEG0_6", + "CLK_HROW_WW4B2_1", + "CLK_HROW_SE4C2_2", + "CLK_HROW_IMUX16_7", + "CLK_HROW_NW4END1_4", + "CLK_HROW_SW4END3_3", + "CLK_HROW_FAN3_7", + "CLK_HROW_CK_GCLK_TEST_IN20", + "CLK_HROW_WW4END0_3", + "CLK_HROW_NE4BEG0_3", + "CLK_HROW_IMUX14_5", + "CLK_HROW_NE4C3_4", + "CLK_HROW_EE2BEG2_4", + "CLK_HROW_WW4A3_0", + "CLK_HROW_BYP6_1", + "CLK_HROW_LH7_5", + "CLK_HROW_CLK1_4", + "CLK_HROW_IMUX34_7", + "CLK_HROW_WW4END2_4", + "CLK_HROW_WR1END3_3", + "CLK_HROW_IMUX13_4", + "CLK_HROW_CK_BUFHCLK_R11", + "CLK_HROW_IMUX40_7", + "CLK_HROW_FAN0_6", + "CLK_HROW_BYP4_7", + "CLK_HROW_EE4BEG1_0", + "CLK_HROW_EE4A1_4", + "CLK_HROW_NE4C3_7", + "CLK_HROW_EE4B0_3", + "CLK_HROW_CTRL1_0", + "CLK_HROW_SE4BEG2_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCO18", + "CLK_HROW_LOGIC_OUTS_B4_7", + "CLK_HROW_CK_GCLK_TEST5", + "CLK_HROW_WL1END2_7", + "CLK_HROW_IMUX40_5", + "CLK_HROW_SE4C3_3", + "CLK_HROW_NW2A2_2", + "CLK_HROW_CK_IN_R5", + "CLK_HROW_WW4C1_6", + "CLK_HROW_EE2A1_7", + "CLK_HROW_FAN4_2", + "CLK_HROW_WL1END1_1", + "CLK_HROW_IMUX44_6", + "CLK_HROW_SE4BEG2_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN8", + "CLK_HROW_NE4BEG3_4", + "CLK_HROW_NE4C2_2", + "CLK_HROW_CK_MUX_OUT_R4", + "CLK_HROW_WW2END0_4", + "CLK_HROW_FAN3_2", + "CLK_HROW_EE4C2_0", + "CLK_HROW_R_CK_GCLK19", + "CLK_HROW_LOGIC_OUTS_B13_1", + "CLK_HROW_WR1END0_5", + "CLK_HROW_CK_GCLK_OUT_TEST4", + "CLK_HROW_NW2A0_1", + "CLK_HROW_WW2END2_4", + "CLK_HROW_IMUX27_7", + "CLK_HROW_NE4BEG3_3", + "CLK_HROW_WW4A3_4", + "CLK_HROW_WL1END2_0", + "CLK_HROW_NW4A1_4", + "CLK_HROW_WW2A2_6", + "CLK_HROW_LOGIC_OUTS_B13_5", + "CLK_HROW_WW4B1_0", + "CLK_HROW_EE4A2_2", + "CLK_HROW_IMUX12_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN12", + "CLK_HROW_CK_GCLK_TEST_OUT27", + "CLK_HROW_NW4END3_5", + "CLK_HROW_WL1END1_0", + "CLK_HROW_WW4B3_0", + "CLK_HROW_LH9_1", + "CLK_HROW_IMUX33_6", + "CLK_HROW_NW4END1_3", + "CLK_HROW_EE4C2_4", + "CLK_HROW_BYP0_0", + "CLK_HROW_IMUX26_3", + "CLK_HROW_CK_GCLK_IN_TEST1", + "CLK_HROW_WW4A3_1", + "CLK_HROW_CK_GCLK_TEST_OUT22", + "CLK_HROW_EE4B1_6", + "CLK_HROW_FAN7_3", + "CLK_HROW_NE2A0_0", + "CLK_HROW_IMUX20_2", + "CLK_HROW_EL1BEG2_4", + "CLK_HROW_IMUX10_6", + "CLK_HROW_EE4A2_3", + "CLK_HROW_SE2A3_4", + "CLK_HROW_IMUX9_6", + "CLK_HROW_LH5_4", + "CLK_HROW_FAN7_2", + "CLK_HROW_WW4A1_5", + "CLK_HROW_LOGIC_OUTS_B6_7", + "CLK_HROW_EE4A0_6", + "CLK_HROW_EL1BEG0_1", + "CLK_HROW_BLOCK_OUTS_B2_4", + "CLK_HROW_NE2A0_4", + "CLK_HROW_SW2A1_0", + "CLK_HROW_IMUX46_3", + "CLK_HROW_CK_GCLK_TEST16", + "CLK_HROW_NW4A3_6", + "CLK_HROW_LOGIC_OUTS_B8_3", + "CLK_HROW_NW2A0_2", + "CLK_HROW_NE2A3_1", + "CLK_HROW_LOGIC_OUTS_B22_2", + "CLK_HROW_CK_HCLK_OUT_R11", + "CLK_HROW_IMUX46_6", + "CLK_HROW_IMUX43_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN17", + "CLK_HROW_NW4A1_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCO29", + "CLK_HROW_CK_MUX_OUT_R5", + "CLK_HROW_CK_BUFRCLK_L3", + "CLK_HROW_WW4END2_7", + "CLK_HROW_WW2END1_3", + "CLK_HROW_IMUX20_0", + "CLK_HROW_NE4C2_6", + "CLK_HROW_CK_IN_R_TEST_IN", + "CLK_HROW_IMUX23_1", + "CLK_HROW_LOGIC_OUTS_B17_3", + "CLK_HROW_IMUX9_3", + "CLK_HROW_NE2A2_4", + "CLK_HROW_IMUX10_1", + "CLK_HROW_CK_MUX_OUT_R9", + "CLK_HROW_IMUX14_0", + "CLK_HROW_CTRL0_5", + "CLK_HROW_EL1BEG1_2", + "CLK_HROW_LOGIC_OUTS_B5_4", + "CLK_HROW_SE4C2_6", + "CLK_HROW_EE4B1_2", + "CLK_HROW_BLOCK_OUTS_B0_2", + "CLK_HROW_WW4B2_5", + "CLK_HROW_TOP_R_CK_BUFG_CASCO16", + "CLK_HROW_NE2A0_3", + "CLK_HROW_CLK1_0", + "CLK_HROW_NW2A1_4", + "CLK_HROW_CK_GCLK_TEST_IN15", + "CLK_HROW_ER1BEG1_4", + "CLK_HROW_EL1BEG0_4", + "CLK_HROW_IMUX34_6", + "CLK_HROW_SW2A1_4", + "CLK_HROW_EE4C3_4", + "CLK_HROW_CTRL0_1", + "CLK_HROW_LOGIC_OUTS_B4_4", + "CLK_HROW_BYP0_7", + "CLK_HROW_CK_GCLK_TEST_IN16", + "CLK_HROW_SE4BEG2_4", + "CLK_HROW_LOGIC_OUTS_B19_7", + "CLK_HROW_WL1END3_7", + "CLK_HROW_EE2BEG1_3", + "CLK_HROW_CK_GCLK_TEST_OUT17", + "CLK_HROW_NE4C0_4", + "CLK_HROW_IMUX15_3", + "CLK_HROW_CK_MUX_OUT_R3", + "CLK_HROW_IMUX41_3", + "CLK_HROW_NE2A2_3", + "CLK_HROW_CK_GCLK_TEST_IN26", + "CLK_HROW_EE2BEG2_5", + "CLK_HROW_LOGIC_OUTS_B13_3", + "CLK_HROW_LH4_5", + "CLK_HROW_NW4A0_2", + "CLK_HROW_BYP4_5", + "CLK_HROW_IMUX30_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCO22", + "CLK_HROW_WW4A0_0", + "CLK_HROW_NE4C3_2", + "CLK_HROW_CK_GCLK_TEST_OUT3", + "CLK_HROW_WW4B3_4", + "CLK_HROW_IMUX32_6", + "CLK_HROW_IMUX29_1", + "CLK_HROW_IMUX43_6", + "CLK_HROW_NW4A2_2", + "CLK_HROW_SE2A1_4", + "CLK_HROW_SE4BEG0_1", + "CLK_HROW_CLK0_6", + "CLK_HROW_BUFHCE_CE_L2", + "CLK_HROW_CK_BUFHCLK_R3", + "CLK_HROW_CK_GCLK_IN_TEST20", + "CLK_HROW_IMUX46_4", + "CLK_HROW_NW2A3_4", + "CLK_HROW_NW4A0_4", + "CLK_HROW_WW4A3_7", + "CLK_HROW_LOGIC_OUTS_B6_0", + "CLK_HROW_LOGIC_OUTS_B3_0", + "CLK_HROW_CTRL0_0", + "CLK_HROW_IMUX30_4", + "CLK_HROW_CK_HCLK_OUT_R5", + "CLK_HROW_EL1BEG1_5", + "CLK_HROW_NW4END3_0", + "CLK_HROW_BLOCK_OUTS_B0_0", + "CLK_HROW_WW4END3_7", + "CLK_HROW_CTRL1_7", + "CLK_HROW_NW4A1_6", + "CLK_HROW_SE2A3_1", + "CLK_HROW_LH4_4", + "CLK_HROW_SW2A3_3", + "CLK_HROW_BYP7_7", + "CLK_HROW_CK_GCLK_TEST1", + "CLK_HROW_IMUX43_3", + "CLK_HROW_SE2A3_0", + "CLK_HROW_CK_IN_L6", + "CLK_HROW_WR1END1_3", + "CLK_HROW_LOGIC_OUTS_B16_4", + "CLK_HROW_EE4BEG2_1", + "CLK_HROW_EE2A1_4", + "CLK_HROW_IMUX16_0", + "CLK_HROW_CK_HCLK_OUT_L10", + "CLK_HROW_SW2A3_1", + "CLK_HROW_SE2A2_1", + "CLK_HROW_WR1END0_2", + "CLK_HROW_NW2A0_4", + "CLK_HROW_IMUX16_3", + "CLK_HROW_EE4B2_2", + "CLK_HROW_NE2A0_5", + "CLK_HROW_FAN1_4", + "CLK_HROW_WW4END1_2", + "CLK_HROW_IMUX3_2", + "CLK_HROW_CK_GCLK_TEST29", + "CLK_HROW_SW4END1_0", + "CLK_HROW_CK_IN_R0", + "CLK_HROW_CE_INT_BOT7", + "CLK_HROW_IMUX8_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCO3", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN7", + "CLK_HROW_CK_GCLK_TEST_OUT9", + "CLK_HROW_IMUX30_5", + "CLK_HROW_SW4A0_3", + "CLK_HROW_WW4C3_6", + "CLK_HROW_LOGIC_OUTS_B22_7", + "CLK_HROW_WW2END0_5", + "CLK_HROW_WW4END3_1", + "CLK_HROW_CK_IN_R11", + "CLK_HROW_CK_GCLK_TEST_OUT2", + "CLK_HROW_BUFHCE_CE_R3", + "CLK_HROW_IMUX9_1", + "CLK_HROW_CK_IN_R12", + "CLK_HROW_NW4END0_7", + "CLK_HROW_IMUX17_4", + "CLK_HROW_IMUX22_5", + "CLK_HROW_IMUX39_0", + "CLK_HROW_EE2BEG3_1", + "CLK_HROW_NW4END1_0", + "CLK_HROW_NW4A2_3", + "CLK_HROW_ER1BEG1_6", + "CLK_HROW_EL1BEG3_6", + "CLK_HROW_NW2A3_6", + "CLK_HROW_IMUX1_3", + "CLK_HROW_IMUX35_4", + "CLK_HROW_SE4C0_5", + "CLK_HROW_LOGIC_OUTS_B21_6", + "CLK_HROW_IMUX35_6", + "CLK_HROW_FAN4_3", + "CLK_HROW_CLK1_1", + "CLK_HROW_CK_GCLK_OUT_TEST17", + "CLK_HROW_BUFHCE_CE_R6", + "CLK_HROW_IMUX6_7", + "CLK_HROW_CK_GCLK_TEST_IN30", + "CLK_HROW_CK_GCLK_TEST10", + "CLK_HROW_NW4END3_4", + "CLK_HROW_IMUX16_1", + "CLK_HROW_CK_IN_R6", + "CLK_HROW_EE2BEG1_1", + "CLK_HROW_CK_GCLK_IN_TEST14", + "CLK_HROW_EE4C3_0", + "CLK_HROW_FAN3_6", + "CLK_HROW_WW2A0_4", + "CLK_HROW_CK_MUX_OUT_R10", + "CLK_HROW_CK_GCLK_TEST_OUT8", + "CLK_HROW_EE4A0_5", + "CLK_HROW_LOGIC_OUTS_B2_1", + "CLK_HROW_NW4A2_1", + "CLK_HROW_FAN7_6", + "CLK_HROW_WW4END3_4", + "CLK_HROW_LOGIC_OUTS_B8_1", + "CLK_HROW_EE2BEG3_3", + "CLK_HROW_EE4B0_2", + "CLK_HROW_WW4B0_7", + "CLK_HROW_EE4C1_0", + "CLK_HROW_WW2END3_0", + "CLK_HROW_LH1_6", + "CLK_HROW_WR1END2_1", + "CLK_HROW_LOGIC_OUTS_B8_4", + "CLK_HROW_LH8_3", + "CLK_HROW_EE4B3_7", + "CLK_HROW_IMUX35_2", + "CLK_HROW_CK_GCLK_IN_TEST16", + "CLK_HROW_BLOCK_OUTS_B1_7", + "CLK_HROW_CK_IN_L5", + "CLK_HROW_LH12_6", + "CLK_HROW_WW4A0_7", + "CLK_HROW_SE4BEG1_3", + "CLK_HROW_IMUX15_1", + "CLK_HROW_WW2END0_6", + "CLK_HROW_LOGIC_OUTS_B16_0", + "CLK_HROW_EE4C1_4", + "CLK_HROW_IMUX41_5", + "CLK_HROW_WL1END1_6", + "CLK_HROW_EE4BEG0_7", + "CLK_HROW_LOGIC_OUTS_B14_7", + "CLK_HROW_SW4END2_6", + "CLK_HROW_IMUX33_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCO20", + "CLK_HROW_R_CK_GCLK0", + "CLK_HROW_LH12_2", + "CLK_HROW_IMUX6_6", + "CLK_HROW_WW4A2_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO27", + "CLK_HROW_EE2BEG1_2", + "CLK_HROW_LH8_6", + "CLK_HROW_WW2END2_3", + "CLK_HROW_EE4B1_1", + "CLK_HROW_CK_HCLK_OUT_R0", + "CLK_HROW_NE4BEG2_2", + "CLK_HROW_NE2A2_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCO25", + "CLK_HROW_SE4C1_1", + "CLK_HROW_BLOCK_OUTS_B1_3", + "CLK_HROW_LOGIC_OUTS_B3_1", + "CLK_HROW_BYP0_5", + "CLK_HROW_NE2A3_7", + "CLK_HROW_CK_MUX_OUT_R2", + "CLK_HROW_WW2END3_6", + "CLK_HROW_SE4C1_2", + "CLK_HROW_IMUX28_6", + "CLK_HROW_EE4C3_1", + "CLK_HROW_IMUX12_3", + "CLK_HROW_LOGIC_OUTS_B4_1", + "CLK_HROW_IMUX43_4", + "CLK_HROW_IMUX35_7", + "CLK_HROW_WW4B3_6", + "CLK_HROW_EE4A2_6", + "CLK_HROW_IMUX8_6", + "CLK_HROW_IMUX12_4", + "CLK_HROW_CK_GCLK_TEST_IN1", + "CLK_HROW_CE_INT_TOP10", + "CLK_HROW_CK_GCLK_OUT_TEST31", + "CLK_HROW_SE2A0_4", + "CLK_HROW_IMUX27_3", + "CLK_HROW_MONITOR_P_0", + "CLK_HROW_IMUX18_3", + "CLK_HROW_CE_INT_TOP3", + "CLK_HROW_NE2A3_3", + "CLK_HROW_SW2A3_4", + "CLK_HROW_BUFHCE_CE_R10", + "CLK_HROW_IMUX20_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN10", + "CLK_HROW_CK_GCLK_OUT_TEST18", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN14", + "CLK_HROW_EE4BEG2_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN16", + "CLK_HROW_CK_GCLK_TEST_IN21", + "CLK_HROW_BLOCK_OUTS_B0_6", + "CLK_HROW_NW4A0_7", + "CLK_HROW_LOGIC_OUTS_B8_2", + "CLK_HROW_EE4A3_7", + "CLK_HROW_EE2BEG3_6", + "CLK_HROW_SE4BEG1_7", + "CLK_HROW_IMUX29_3", + "CLK_HROW_SE2A3_3", + "CLK_HROW_IMUX46_7", + "CLK_HROW_IMUX33_2", + "CLK_HROW_NW4A1_0", + "CLK_HROW_ER1BEG1_0", + "CLK_HROW_NW4A1_5", + "CLK_HROW_FAN2_6", + "CLK_HROW_EE2BEG0_5", + "CLK_HROW_LOGIC_OUTS_B17_0", + "CLK_HROW_IMUX10_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN23", + "CLK_HROW_SE4C2_5", + "CLK_HROW_R_CK_GCLK20", + "CLK_HROW_NE2A1_4", + "CLK_HROW_EE2BEG2_1", + "CLK_HROW_SE4BEG1_0", + "CLK_HROW_NE4BEG2_1", + "CLK_HROW_BYP5_7", + "CLK_HROW_EE4A1_1", + "CLK_HROW_LH7_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN9", + "CLK_HROW_NW4END0_3", + "CLK_HROW_LOGIC_OUTS_B11_2", + "CLK_HROW_CK_GCLK_TEST_OUT18", + "CLK_HROW_CK_GCLK_IN_TEST2", + "CLK_HROW_CTRL1_1", + "CLK_HROW_CK_GCLK_OUT_TEST20", + "CLK_HROW_SW4A0_6", + "CLK_HROW_IMUX34_2", + "CLK_HROW_SW4A1_2", + "CLK_HROW_FAN7_4", + "CLK_HROW_IMUX23_6", + "CLK_HROW_FAN6_3", + "CLK_HROW_SW2A2_0", + "CLK_HROW_CK_GCLK_IN_TEST18", + "CLK_HROW_LOGIC_OUTS_B17_7", + "CLK_HROW_R_CK_GCLK31", + "CLK_HROW_WW2A3_6", + "CLK_HROW_LOGIC_OUTS_B10_1", + "CLK_HROW_LH12_3", + "CLK_HROW_SW2A2_3", + "CLK_HROW_LOGIC_OUTS_B21_4", + "CLK_HROW_LH4_3", + "CLK_HROW_SE2A0_2", + "CLK_HROW_EE2BEG2_7", + "CLK_HROW_IMUX7_0", + "CLK_HROW_NE2A1_1", + "CLK_HROW_CK_GCLK_TEST26", + "CLK_HROW_IMUX29_5", + "CLK_HROW_IMUX15_6", + "CLK_HROW_FAN0_5", + "CLK_HROW_NE4BEG3_7", + "CLK_HROW_FAN2_7", + "CLK_HROW_IMUX36_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN20", + "CLK_HROW_EE4A3_3", + "CLK_HROW_NE4C1_1", + "CLK_HROW_IMUX19_4", + "CLK_HROW_EE2A0_7", + "CLK_HROW_LOGIC_OUTS_B23_5", + "CLK_HROW_NW2A3_3", + "CLK_HROW_SE4BEG0_0", + "CLK_HROW_BYP1_5", + "CLK_HROW_WW4END0_5", + "CLK_HROW_CK_GCLK_OUT_TEST0", + "CLK_HROW_WW4A3_5", + "CLK_HROW_SE2A2_0", + "CLK_HROW_LH4_7", + "CLK_HROW_IMUX26_6", + "CLK_HROW_CK_HCLK_OUT_L7", + "CLK_HROW_NE2A0_1", + "CLK_HROW_WW2END0_7", + "CLK_HROW_WR1END1_1", + "CLK_HROW_IMUX22_4", + "CLK_HROW_SW2A3_0", + "CLK_HROW_EE4A0_0", + "CLK_HROW_WR1END0_1", + "CLK_HROW_IMUX38_6", + "CLK_HROW_SW4A2_0", + "CLK_HROW_EE2A0_3", + "CLK_HROW_NW4A3_3", + "CLK_HROW_IMUX34_5", + "CLK_HROW_LH3_4", + "CLK_HROW_ER1BEG3_7", + "CLK_HROW_CTRL1_4", + "CLK_HROW_IMUX5_4", + "CLK_HROW_IMUX45_1", + "CLK_HROW_BYP7_4", + "CLK_HROW_IMUX39_2", + "CLK_HROW_NE2A1_7", + "CLK_HROW_EE4A3_4", + "CLK_HROW_WW2A0_1", + "CLK_HROW_NE2A1_5", + "CLK_HROW_IMUX40_3", + "CLK_HROW_SE4BEG2_5", + "CLK_HROW_NE4BEG0_1", + "CLK_HROW_CK_GCLK_TEST_OUT21", + "CLK_HROW_IMUX37_2", + "CLK_HROW_WL1END3_0", + "CLK_HROW_IMUX8_5", + "CLK_HROW_LH6_1", + "CLK_HROW_IMUX1_4", + "CLK_HROW_EE4B3_2", + "CLK_HROW_BLOCK_OUTS_B3_3", + "CLK_HROW_IMUX27_0", + "CLK_HROW_SW2A0_1", + "CLK_HROW_LOGIC_OUTS_B4_6", + "CLK_HROW_LH3_3", + "CLK_HROW_CK_GCLK_OUT_TEST14", + "CLK_HROW_WW4C3_4", + "CLK_HROW_BUFHCE_CE_L5", + "CLK_HROW_CK_GCLK_IN_TEST7", + "CLK_HROW_EE4C3_5", + "CLK_HROW_NW2A2_7", + "CLK_HROW_EE4BEG2_5", + "CLK_HROW_WW4A1_2", + "CLK_HROW_NE4BEG2_6", + "CLK_HROW_IMUX46_1", + "CLK_HROW_WW4A2_3", + "CLK_HROW_BYP5_3", + "CLK_HROW_LH2_6", + "CLK_HROW_CK_GCLK_TEST_OUT5", + "CLK_HROW_IMUX19_7", + "CLK_HROW_WW4END0_2", + "CLK_HROW_CK_GCLK_IN_TEST5", + "CLK_HROW_NW2A3_5", + "CLK_HROW_IMUX36_5", + "CLK_HROW_NW4A2_4", + "CLK_HROW_CK_GCLK_OUT_TEST19", + "CLK_HROW_LH7_1", + "CLK_HROW_WW4B2_4", + "CLK_HROW_EL1BEG2_1", + "CLK_HROW_CK_HCLK_OUT_R6", + "CLK_HROW_CK_MUX_OUT_L6", + "CLK_HROW_MONITOR_N_4", + "CLK_HROW_IMUX3_6", + "CLK_HROW_BYP1_4", + "CLK_HROW_NE4C0_5", + "CLK_HROW_IMUX4_3", + "CLK_HROW_SW4END1_3", + "CLK_HROW_SW4A0_0", + "CLK_HROW_WW4END2_1", + "CLK_HROW_CLK1_5", + "CLK_HROW_SW4END0_4", + "CLK_HROW_WW4B1_6", + "CLK_HROW_BYP3_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCO6", + "CLK_HROW_EL1BEG0_2", + "CLK_HROW_LOGIC_OUTS_B15_0", + "CLK_HROW_EE4BEG1_7", + "CLK_HROW_BLOCK_OUTS_B2_7", + "CLK_HROW_NE4BEG2_3", + "CLK_HROW_WW2END3_4", + "CLK_HROW_EE4BEG3_6", + "CLK_HROW_IMUX15_5", + "CLK_HROW_ER1BEG2_2", + "CLK_HROW_FAN4_4", + "CLK_HROW_EL1BEG1_3", + "CLK_HROW_WL1END1_2", + "CLK_HROW_CK_GCLK_TEST_IN24", + "CLK_HROW_BYP2_5", + "CLK_HROW_FAN0_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN27", + "CLK_HROW_SW4A3_1", + "CLK_HROW_LH6_6", + "CLK_HROW_NE4C2_0", + "CLK_HROW_LOGIC_OUTS_B15_4", + "CLK_HROW_WW2A0_3", + "CLK_HROW_LOGIC_OUTS_B16_3", + "CLK_HROW_R_CK_GCLK29", + "CLK_HROW_LH7_4", + "CLK_HROW_R_CK_GCLK7", + "CLK_HROW_CK_MUX_OUT_L2", + "CLK_HROW_WW2END1_2", + "CLK_HROW_IMUX42_0", + "CLK_HROW_IMUX23_5", + "CLK_HROW_CK_GCLK_TEST28", + "CLK_HROW_LOGIC_OUTS_B2_0", + "CLK_HROW_ER1BEG2_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO2", + "CLK_HROW_REFCK_EASTCLK1", + "CLK_HROW_WW4C0_1", + "CLK_HROW_TOP_R_CK_BUFG_CASCO13", + "CLK_HROW_LOGIC_OUTS_B0_3", + "CLK_HROW_IMUX21_3", + "CLK_HROW_LH5_0", + "CLK_HROW_LH5_6", + "CLK_HROW_SW4A2_6", + "CLK_HROW_NE2A0_7", + "CLK_HROW_IMUX0_3", + "CLK_HROW_IMUX13_5", + "CLK_HROW_LOGIC_OUTS_B17_6", + "CLK_HROW_CK_GCLK_TEST8", + "CLK_HROW_EL1BEG1_1", + "CLK_HROW_EE4C2_1", + "CLK_HROW_SW4END2_3", + "CLK_HROW_IMUX47_3", + "CLK_HROW_CK_GCLK_OUT_TEST22", + "CLK_HROW_BYP3_2", + "CLK_HROW_WW4B1_4", + "CLK_HROW_LH11_0", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN1", + "CLK_HROW_CK_BUFHCLK_R7", + "CLK_HROW_NE4C2_1", + "CLK_HROW_SW2A2_4", + "CLK_HROW_WW2END2_7", + "CLK_HROW_LOGIC_OUTS_B22_0", + "CLK_HROW_CK_BUFHCLK_L9", + "CLK_HROW_NW2A0_3", + "CLK_HROW_LH7_3", + "CLK_HROW_IMUX41_0", + "CLK_HROW_CK_IN_R2", + "CLK_HROW_EE4BEG2_2", + "CLK_HROW_IMUX32_5", + "CLK_HROW_CK_HCLK_OUT_L2", + "CLK_HROW_TOP_R_CK_BUFG_CASCO8", + "CLK_HROW_SE4BEG3_2", + "CLK_HROW_ER1BEG2_3", + "CLK_HROW_IMUX20_4", + "CLK_HROW_CE_INT_TOP2", + "CLK_HROW_BYP4_2", + "CLK_HROW_WW4B0_3", + "CLK_HROW_SE4C2_4", + "CLK_HROW_CK_GCLK_TEST_OUT7", + "CLK_HROW_CK_BUFHCLK_L7", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN11", + "CLK_HROW_LOGIC_OUTS_B21_3", + "CLK_HROW_WW4END0_4", + "CLK_HROW_SE4C1_6", + "CLK_HROW_IMUX22_3", + "CLK_HROW_FAN2_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCO21", + "CLK_HROW_IMUX31_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO11", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN29", + "CLK_HROW_CLK0_0", + "CLK_HROW_IMUX34_4", + "CLK_HROW_NW2A3_0", + "CLK_HROW_CK_GCLK_TEST_OUT24", + "CLK_HROW_CK_GCLK_OUT_TEST2", + "CLK_HROW_NE2A2_6", + "CLK_HROW_EE4A0_2", + "CLK_HROW_BYP1_7", + "CLK_HROW_NE2A1_2", + "CLK_HROW_EE4C2_7", + "CLK_HROW_CK_GCLK_IN_TEST25", + "CLK_HROW_TOP_R_CK_BUFG_CASCO7", + "CLK_HROW_LOGIC_OUTS_B11_4", + "CLK_HROW_CK_GCLK_TEST_IN4", + "CLK_HROW_WW4C2_1", + "CLK_HROW_R_CK_GCLK24", + "CLK_HROW_IMUX39_6", + "CLK_HROW_CE_INT_TOP11", + "CLK_HROW_SE2A1_6", + "CLK_HROW_IMUX3_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCO10", + "CLK_HROW_IMUX13_3", + "CLK_HROW_CK_GCLK_OUT_TEST25", + "CLK_HROW_LH12_1", + "CLK_HROW_NW4END2_4", + "CLK_HROW_IMUX39_3", + "CLK_HROW_WR1END1_2", + "CLK_HROW_R_CK_GCLK5", + "CLK_HROW_IMUX17_0", + "CLK_HROW_LH5_1", + "CLK_HROW_EL1BEG2_6", + "CLK_HROW_SE4C1_5", + "CLK_HROW_SE4C0_2", + "CLK_HROW_ER1BEG3_6", + "CLK_HROW_WW4C0_0", + "CLK_HROW_WW4A3_3", + "CLK_HROW_IMUX30_7", + "CLK_HROW_LOGIC_OUTS_B7_0", + "CLK_HROW_SW2A0_3", + "CLK_HROW_NE4BEG0_7", + "CLK_HROW_LH9_3", + "CLK_HROW_IMUX31_5", + "CLK_HROW_WW4A2_0", + "CLK_HROW_WW2A1_2", + "CLK_HROW_EE2A1_5", + "CLK_HROW_EE4B3_1", + "CLK_HROW_NE4C0_2", + "CLK_HROW_SW2A3_2", + "CLK_HROW_EE4B0_6", + "CLK_HROW_MONITOR_N_0", + "CLK_HROW_WL1END3_4", + "CLK_HROW_LOGIC_OUTS_B14_4", + "CLK_HROW_SE4BEG3_5", + "CLK_HROW_MONITOR_N_1", + "CLK_HROW_SE2A2_7", + "CLK_HROW_CE_INT_BOT1", + "CLK_HROW_CK_GCLK_IN_TEST23", + "CLK_HROW_EE4BEG2_7", + "CLK_HROW_IMUX21_2", + "CLK_HROW_CK_INT_0_0", + "CLK_HROW_CK_GCLK_TEST_IN14", + "CLK_HROW_BYP2_3", + "CLK_HROW_IMUX38_1", + "CLK_HROW_IMUX10_4", + "CLK_HROW_WW4B0_5", + "CLK_HROW_NW4END2_6", + "CLK_HROW_EE4C0_2", + "CLK_HROW_IMUX37_1", + "CLK_HROW_LH9_0", + "CLK_HROW_IMUX29_0", + "CLK_HROW_WW2A3_5", + "CLK_HROW_WL1END2_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCO19", + "CLK_HROW_BYP6_6", + "CLK_HROW_CK_IN_L_OUT_TEST", + "CLK_HROW_BUFHCE_CE_L11", + "CLK_HROW_IMUX0_5", + "CLK_HROW_WW2A1_0", + "CLK_HROW_FAN5_2", + "CLK_HROW_CK_IN_L7", + "CLK_HROW_NW2A2_5", + "CLK_HROW_EE2BEG3_2", + "CLK_HROW_IMUX34_3", + "CLK_HROW_CK_GCLK_OUT_TEST16", + "CLK_HROW_NW4A3_2", + "CLK_HROW_WW4A2_1", + "CLK_HROW_WW2A1_6", + "CLK_HROW_EE2A3_6", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN26", + "CLK_HROW_IMUX46_0", + "CLK_HROW_LOGIC_OUTS_B22_4", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN6", + "CLK_HROW_CK_IN_R8", + "CLK_HROW_SE2A2_2", + "CLK_HROW_LH9_4", + "CLK_HROW_IMUX10_5", + "CLK_HROW_CK_GCLK_TEST30", + "CLK_HROW_SE2A3_2", + "CLK_HROW_CK_GCLK_IN_TEST27", + "CLK_HROW_IMUX12_1", + "CLK_HROW_IMUX7_1", + "CLK_HROW_IMUX20_5", + "CLK_HROW_IMUX24_3", + "CLK_HROW_LH11_1", + "CLK_HROW_WW4C1_7", + "CLK_HROW_IMUX47_2", + "CLK_HROW_CK_GCLK_OUT_TEST21", + "CLK_HROW_CK_GCLK_TEST31", + "CLK_HROW_ER1BEG2_0", + "CLK_HROW_BYP2_7", + "CLK_HROW_IMUX18_6", + "CLK_HROW_WW4C3_0", + "CLK_HROW_CLK0_5", + "CLK_HROW_REFCK_WESTCLK0", + "CLK_HROW_IMUX43_5", + "CLK_HROW_LH2_3", + "CLK_HROW_EE4BEG0_0", + "CLK_HROW_LOGIC_OUTS_B10_5", + "CLK_HROW_CK_IN_L12", + "CLK_HROW_CK_GCLK_TEST_IN9", + "CLK_HROW_CK_GCLK_TEST_OUT12", + "CLK_HROW_EE4A2_4", + "CLK_HROW_EE4C2_5", + "CLK_HROW_CK_MUX_OUT_L1", + "CLK_HROW_WW4A2_6", + "CLK_HROW_SE2A2_4", + "CLK_HROW_NW2A1_5", + "CLK_HROW_R_CK_GCLK28", + "CLK_HROW_CK_GCLK_TEST15", + "CLK_HROW_LH9_7", + "CLK_HROW_IMUX4_7", + "CLK_HROW_CK_IN_R_IN_TEST", + "CLK_HROW_LOGIC_OUTS_B22_5", + "CLK_HROW_IMUX19_0", + "CLK_HROW_CK_GCLK_TEST22", + "CLK_HROW_NE4C1_2", + "CLK_HROW_SE4BEG0_2", + "CLK_HROW_SW4A2_4", + "CLK_HROW_SW4A2_3", + "CLK_HROW_SE2A1_0", + "CLK_HROW_SW4A3_3", + "CLK_HROW_NW4END0_4", + "CLK_HROW_IMUX38_3", + "CLK_HROW_IMUX47_4", + "CLK_HROW_LH2_7", + "CLK_HROW_LOGIC_OUTS_B2_3", + "CLK_HROW_IMUX31_2", + "CLK_HROW_EE4B0_4", + "CLK_HROW_IMUX14_7", + "CLK_HROW_WW2A0_5", + "CLK_HROW_LH3_2", + "CLK_HROW_EL1BEG3_7", + "CLK_HROW_EE2A2_6", + "CLK_HROW_LOGIC_OUTS_B4_3", + "CLK_HROW_EE4A2_7", + "CLK_HROW_WL1END0_3", + "CLK_HROW_BYP1_6", + "CLK_HROW_WW4A0_5", + "CLK_HROW_EE4B0_1", + "CLK_HROW_LOGIC_OUTS_B19_2", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN18", + "CLK_HROW_CK_GCLK_OUT_TEST23", + "CLK_HROW_NW4A2_7", + "CLK_HROW_EE2BEG0_3", + "CLK_HROW_SW4END2_7", + "CLK_HROW_WW4C2_7", + "CLK_HROW_CK_BUFHCLK_R1", + "CLK_HROW_IMUX36_0", + "CLK_HROW_BLOCK_OUTS_B2_3", + "CLK_HROW_EL1BEG3_1", + "CLK_HROW_EE4A1_6", + "CLK_HROW_BUFHCE_CE_L4", + "CLK_HROW_LH3_5", + "CLK_HROW_LOGIC_OUTS_B11_7", + "CLK_HROW_EE4BEG0_6", + "CLK_HROW_SW4A1_4", + "CLK_HROW_CK_GCLK_TEST0", + "CLK_HROW_SW4A1_5", + "CLK_HROW_IMUX28_3", + "CLK_HROW_TOP_R_CK_BUFG_CASCO14", + "CLK_HROW_EE2A0_4", + "CLK_HROW_IMUX6_4", + "CLK_HROW_BYP6_5", + "CLK_HROW_NE4BEG3_1", + "CLK_HROW_NE4C0_6", + "CLK_HROW_EE4C2_2", + "CLK_HROW_BLOCK_OUTS_B1_4", + "CLK_HROW_SW4END1_5", + "CLK_HROW_NE2A2_5", + "CLK_HROW_CK_IN_R7", + "CLK_HROW_IMUX0_7", + "CLK_HROW_WW4A0_3", + "CLK_HROW_IMUX45_0", + "CLK_HROW_IMUX42_5", + "CLK_HROW_CK_BUFHCLK_L1", + "CLK_HROW_WR1END3_6", + "CLK_HROW_SW4END1_7", + "CLK_HROW_MONITOR_N_7", + "CLK_HROW_CK_BUFHCLK_L8", + "CLK_HROW_EL1BEG3_0", + "CLK_HROW_SW4END1_4", + "CLK_HROW_WL1END3_1", + "CLK_HROW_IMUX17_6", + "CLK_HROW_LOGIC_OUTS_B6_2", + "CLK_HROW_SE4C3_0", + "CLK_HROW_CK_GCLK_TEST_OUT11", + "CLK_HROW_IMUX19_1", + "CLK_HROW_NE2A1_3", + "CLK_HROW_SE4C3_2", + "CLK_HROW_SW4END0_1", + "CLK_HROW_BYP0_4", + "CLK_HROW_R_CK_GCLK6", + "CLK_HROW_LOGIC_OUTS_B8_6", + "CLK_HROW_LOGIC_OUTS_B1_2", + "CLK_HROW_NE4BEG3_0", + "CLK_HROW_FAN1_2", + "CLK_HROW_WR1END0_6", + "CLK_HROW_LOGIC_OUTS_B1_1", + "CLK_HROW_WW4B3_5", + "CLK_HROW_IMUX17_5", + "CLK_HROW_CK_GCLK_IN_TEST3", + "CLK_HROW_WW4C2_6", + "CLK_HROW_NE4C3_1", + "CLK_HROW_NE2A3_2", + "CLK_HROW_BYP3_3", + "CLK_HROW_WW2A2_1", + "CLK_HROW_LOGIC_OUTS_B2_4", + "CLK_HROW_SE4BEG3_4", + "CLK_HROW_FAN5_3", + "CLK_HROW_IMUX15_7", + "CLK_HROW_IMUX31_6", + "CLK_HROW_IMUX30_2", + "CLK_HROW_IMUX24_1", + "CLK_HROW_WW4C2_4", + "CLK_HROW_EE2A2_5", + "CLK_HROW_CK_GCLK_OUT_TEST7", + "CLK_HROW_LH11_4", + "CLK_HROW_EL1BEG2_0", + "CLK_HROW_BUFHCE_CE_R7", + "CLK_HROW_LOGIC_OUTS_B13_7", + "CLK_HROW_BLOCK_OUTS_B2_5", + "CLK_HROW_SE2A0_3", + "CLK_HROW_SE4BEG1_4", + "CLK_HROW_IMUX7_4", + "CLK_HROW_LOGIC_OUTS_B1_5", + "CLK_HROW_FAN0_4", + "CLK_HROW_EE4BEG3_0", + "CLK_HROW_IMUX45_6", + "CLK_HROW_IMUX11_4", + "CLK_HROW_ER1BEG2_6", + "CLK_HROW_WL1END0_6", + "CLK_HROW_WW4END3_6", + "CLK_HROW_WR1END2_7", + "CLK_HROW_CK_BUFRCLK_L1", + "CLK_HROW_IMUX2_3", + "CLK_HROW_BLOCK_OUTS_B3_6", + "CLK_HROW_CK_GCLK_IN_TEST24", + "CLK_HROW_SW4END3_2", + "CLK_HROW_NW4A3_7", + "CLK_HROW_IMUX16_2", + "CLK_HROW_MONITOR_N_6", + "CLK_HROW_SE4BEG0_7", + "CLK_HROW_SE4BEG2_1", + "CLK_HROW_CTRL0_2", + "CLK_HROW_IMUX6_3", + "CLK_HROW_FAN3_3", + "CLK_HROW_FAN1_1", + "CLK_HROW_WL1END1_5", + "CLK_HROW_EE4C1_2", + "CLK_HROW_IMUX32_0", + "CLK_HROW_NE4BEG3_5", + "CLK_HROW_CK_BUFHCLK_L3", + "CLK_HROW_EE2A1_1", + "CLK_HROW_EE2A2_3", + "CLK_HROW_NW4END2_2", + "CLK_HROW_IMUX25_6", + "CLK_HROW_FAN5_0", + "CLK_HROW_BYP5_5", + "CLK_HROW_WW2END1_7", + "CLK_HROW_ER1BEG0_0", + "CLK_HROW_LOGIC_OUTS_B6_4", + "CLK_HROW_EE4B1_0", + "CLK_HROW_NW4END2_1", + "CLK_HROW_CK_GCLK_IN_TEST26", + "CLK_HROW_R_CK_GCLK22", + "CLK_HROW_CK_MUX_OUT_R7", + "CLK_HROW_NW2A0_6", + "CLK_HROW_IMUX24_5", + "CLK_HROW_EE2A2_2", + "CLK_HROW_BYP6_7", + "CLK_HROW_TOP_R_CK_BUFG_CASCIN2", + "CLK_HROW_LH10_7", + "CLK_HROW_IMUX9_0", + "CLK_HROW_WW4C1_4", + "CLK_HROW_EE4BEG2_0", + "CLK_HROW_IMUX5_5", + "CLK_HROW_IMUX22_6", + "CLK_HROW_IMUX14_4", + "CLK_HROW_CK_BUFHCLK_L5", + "CLK_HROW_LOGIC_OUTS_B4_5", + "CLK_HROW_FAN4_0", + "CLK_HROW_WW4B1_2", + "CLK_HROW_IMUX0_0", + "CLK_HROW_NE2A0_2", + "CLK_HROW_LOGIC_OUTS_B7_3", + "CLK_HROW_WW4END0_7", + "CLK_HROW_CK_BUFHCLK_L0", + "CLK_HROW_NE2A2_7", + "CLK_HROW_SE4BEG1_6" + ], + "tile_type": "CLK_HROW_TOP_R", + "sites": [ + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L0", + "CE": "CLK_HROW_BUFHCE_CE_L0", + "O": "CLK_HROW_CK_HCLK_OUT_L0" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L1", + "CE": "CLK_HROW_BUFHCE_CE_L1", + "O": "CLK_HROW_CK_HCLK_OUT_L1" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L2", + "CE": "CLK_HROW_BUFHCE_CE_L2", + "O": "CLK_HROW_CK_HCLK_OUT_L2" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y2", + "x_coord": 0, + "y_coord": 2 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L3", + "CE": "CLK_HROW_BUFHCE_CE_L3", + "O": "CLK_HROW_CK_HCLK_OUT_L3" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y3", + "x_coord": 0, + "y_coord": 3 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L4", + "CE": "CLK_HROW_BUFHCE_CE_L4", + "O": "CLK_HROW_CK_HCLK_OUT_L4" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y4", + "x_coord": 0, + "y_coord": 4 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L5", + "CE": "CLK_HROW_BUFHCE_CE_L5", + "O": "CLK_HROW_CK_HCLK_OUT_L5" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y5", + "x_coord": 0, + "y_coord": 5 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L6", + "CE": "CLK_HROW_BUFHCE_CE_L6", + "O": "CLK_HROW_CK_HCLK_OUT_L6" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y6", + "x_coord": 0, + "y_coord": 6 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L7", + "CE": "CLK_HROW_BUFHCE_CE_L7", + "O": "CLK_HROW_CK_HCLK_OUT_L7" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y7", + "x_coord": 0, + "y_coord": 7 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L8", + "CE": "CLK_HROW_BUFHCE_CE_L8", + "O": "CLK_HROW_CK_HCLK_OUT_L8" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y8", + "x_coord": 0, + "y_coord": 8 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L9", + "CE": "CLK_HROW_BUFHCE_CE_L9", + "O": "CLK_HROW_CK_HCLK_OUT_L9" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y9", + "x_coord": 0, + "y_coord": 9 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L10", + "CE": "CLK_HROW_BUFHCE_CE_L10", + "O": "CLK_HROW_CK_HCLK_OUT_L10" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y10", + "x_coord": 0, + "y_coord": 10 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_L11", + "CE": "CLK_HROW_BUFHCE_CE_L11", + "O": "CLK_HROW_CK_HCLK_OUT_L11" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X0Y11", + "x_coord": 0, + "y_coord": 11 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R11", + "CE": "CLK_HROW_BUFHCE_CE_R11", + "O": "CLK_HROW_CK_HCLK_OUT_R11" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y11", + "x_coord": 1, + "y_coord": 11 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R10", + "CE": "CLK_HROW_BUFHCE_CE_R10", + "O": "CLK_HROW_CK_HCLK_OUT_R10" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y10", + "x_coord": 1, + "y_coord": 10 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R9", + "CE": "CLK_HROW_BUFHCE_CE_R9", + "O": "CLK_HROW_CK_HCLK_OUT_R9" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y9", + "x_coord": 1, + "y_coord": 9 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R8", + "CE": "CLK_HROW_BUFHCE_CE_R8", + "O": "CLK_HROW_CK_HCLK_OUT_R8" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y8", + "x_coord": 1, + "y_coord": 8 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R7", + "CE": "CLK_HROW_BUFHCE_CE_R7", + "O": "CLK_HROW_CK_HCLK_OUT_R7" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y7", + "x_coord": 1, + "y_coord": 7 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R6", + "CE": "CLK_HROW_BUFHCE_CE_R6", + "O": "CLK_HROW_CK_HCLK_OUT_R6" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y6", + "x_coord": 1, + "y_coord": 6 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R5", + "CE": "CLK_HROW_BUFHCE_CE_R5", + "O": "CLK_HROW_CK_HCLK_OUT_R5" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y5", + "x_coord": 1, + "y_coord": 5 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R4", + "CE": "CLK_HROW_BUFHCE_CE_R4", + "O": "CLK_HROW_CK_HCLK_OUT_R4" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y4", + "x_coord": 1, + "y_coord": 4 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R3", + "CE": "CLK_HROW_BUFHCE_CE_R3", + "O": "CLK_HROW_CK_HCLK_OUT_R3" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y3", + "x_coord": 1, + "y_coord": 3 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R2", + "CE": "CLK_HROW_BUFHCE_CE_R2", + "O": "CLK_HROW_CK_HCLK_OUT_R2" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y2", + "x_coord": 1, + "y_coord": 2 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R1", + "CE": "CLK_HROW_BUFHCE_CE_R1", + "O": "CLK_HROW_CK_HCLK_OUT_R1" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y1", + "x_coord": 1, + "y_coord": 1 + }, + { + "site_pins": { + "I": "CLK_HROW_CK_MUX_OUT_R0", + "CE": "CLK_HROW_BUFHCE_CE_R0", + "O": "CLK_HROW_CK_HCLK_OUT_R0" + }, + "type": "BUFHCE", + "prefix": "BUFHCE", + "name": "X1Y0", + "x_coord": 1, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_MTBF2.json b/artix7/tile_type_CLK_MTBF2.json index 7b7db96..b2a0101 100644 --- a/artix7/tile_type_CLK_MTBF2.json +++ b/artix7/tile_type_CLK_MTBF2.json @@ -1,365 +1,365 @@ { - "wires": [ - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_WR1END0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_BYP2_0", - "CLK_MTBF2_Q3B", - "CLK_FEED_R_CK_GCLK12", - "CLK_PMV_BYP6_0", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_GCLK12", - "CLK_MTBF2_Q4B", - "CLK_PMV_BYP5_0", - "CLK_FEED_R_CK_GCLK15", - "CLK_PMV_IMUX27_0", - "CLK_FEED_EE4BEG0", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2END3", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_EE4A2", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_NW4A0", - "CLK_FEED_WW4C1", - "CLK_FEED_LH6", - "CLK_MTBF2_RESET", - "CLK_FEED_EL1BEG0", - "CLK_FEED_WW4B1", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_WR1END1", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_EL1BEG1", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_EE4A1", - "CLK_FEED_WW4END1", - "CLK_PMV_IMUX41_0", - "CLK_FEED_R_CK_GCLK23", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_FEED_R_CK_GCLK28", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_IMUX7_0", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX46_0", - "CLK_FEED_EL1BEG2", - "CLK_MTBF2_Q1B", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK4", - "CLK_PMV_FAN5_0", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX17_0", - "CLK_FEED_WW4A1", - "CLK_FEED_CK_GCLK0", - "CLK_PMV_IMUX35_0", - "CLK_FEED_EE2A0", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_LH8", - "CLK_FEED_SW4A0", - "CLK_FEED_NE4C3", - "CLK_FEED_SE2A1", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_NE4BEG0", - "CLK_FEED_SE4C0", - "CLK_FEED_EE2A2", - "CLK_PMV_IMUX43_0", - "CLK_FEED_NE4BEG3", - "CLK_FEED_WW4END2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_PMV_CLK1_0", - "CLK_FEED_CK_GCLK8", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_MTBF2_CLK", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_PMV_IMUX34_0", - "CLK_FEED_NE4BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_WR1END3", - "CLK_PMV_FAN6_0", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_SW2A2", - "CLK_FEED_LH9", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_R_CK_GCLK20", - "CLK_PMV_IMUX40_0", - "CLK_FEED_WW4A2", - "CLK_PMV_IMUX24_0", - "CLK_FEED_R_CK_GCLK5", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX5_0", - "CLK_FEED_SE2A0", - "CLK_FEED_NW4END2", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_PMV_CLK0_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_FEED_WW2A0", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_LH3", - "CLK_FEED_MONITOR_N", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_NW4END0", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_EE4B0", - "CLK_FEED_LH11", - "CLK_PMV_FAN4_0", - "CLK_FEED_NW2A0", - "CLK_FEED_SW4A2", - "CLK_MTBF2_DIN", - "CLK_FEED_NW4A2", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_WW4END0", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_WW2END2", - "CLK_FEED_EE2A1", - "CLK_FEED_NE2A0", - "CLK_MTBF2_Q0B", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_EE4A3", - "CLK_FEED_LH12", - "CLK_MTBF2_EN", - "CLK_FEED_EE2BEG3", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_SE4BEG2", - "CLK_FEED_LH7", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_NW4END3", - "CLK_PMV_FAN0_0", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_PMV_IMUX15_0", - "CLK_MTBF2_Q5B", - "CLK_FEED_EE4C0", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX47_0", - "CLK_FEED_R_CK_GCLK2", - "CLK_PMV_BYP0_0", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_EE2BEG2", - "CLK_PMV_IMUX29_0", - "CLK_FEED_EE4BEG1", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX1_0", - "CLK_FEED_LH2", - "CLK_PMV_FAN3_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_FAN2_0", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_WW4A0", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_MTBF2_Q6B", - "CLK_PMV_IMUX39_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_SW4END1", - "CLK_FEED_WW2A3", - "CLK_FEED_SE2A2", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_SE4C1", - "CLK_FEED_SW2A0", - "CLK_FEED_EE2A3", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_WW4END3", - "CLK_FEED_CK_GCLK5", - "CLK_PMV_IMUX38_0", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_PMV_IMUX22_0", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_SW4END0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_FAN7_0", - "CLK_FEED_EE4C2", - "CLK_FEED_LH10", - "CLK_PMV_IMUX28_0", - "CLK_FEED_NE4C1", - "CLK_FEED_ER1BEG0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_CTRL0_0", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_SE4BEG1", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_LH1", - "CLK_FEED_WL1END0", - "CLK_FEED_SW4A3", - "CLK_MTBF2_Q7B", - "CLK_PMV_IMUX6_0", - "CLK_FEED_CK_GCLK13", - "CLK_PMV_IMUX33_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_FEED_CK_GCLK11", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_FEED_LH4", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_NE4C0", - "CLK_FEED_NE2A2", - "CLK_PMV_IMUX9_0", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_NE4BEG1", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_PMV_BYP3_0", - "CLK_FEED_CK_GCLK30", - "CLK_PMV_IMUX31_0", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4C3", - "CLK_FEED_EE4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_ER1BEG2", - "CLK_FEED_WL1END3", - "CLK_FEED_SE2A3", - "CLK_PMV_FAN1_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_EE4BEG2", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_PMV_IMUX8_0", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_WW4B2", - "CLK_PMV_IMUX26_0", - "CLK_FEED_SE4C2", - "CLK_FEED_CK_GCLK10", - "CLK_PMV_BYP4_0", - "CLK_FEED_R_CK_GCLK30", - "CLK_PMV_BYP1_0", - "CLK_PMV_IMUX20_0", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_SE4C3", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_FEED_NW2A1", - "CLK_PMV_IMUX21_0", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_EE4BEG3", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_NW2A2", - "CLK_PMV_IMUX12_0", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_CK_GCLK14", - "CLK_PMV_IMUX36_0", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_PMV_IMUX30_0", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_SW2A1", - "CLK_PMV_IMUX4_0", - "CLK_FEED_EE2BEG0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A3", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_LH5", - "CLK_FEED_EE4C3", - "CLK_FEED_WR1END2", - "CLK_PMV_BYP7_0", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_CK_GCLK22", - "CLK_PMV_LOGIC_OUTS9_0", - "CLK_FEED_SW4A1", - "CLK_FEED_NE4C2", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_PMV_IMUX18_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_WL1END2", - "CLK_MTBF2_Q2B", - "CLK_FEED_CK_GCLK2", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX2_0", - "CLK_FEED_WW4C0", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX37_0", - "CLK_FEED_SW2A3", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_GCLK10", - "CLK_PMV_IMUX25_0", - "CLK_FEED_WW4A3", - "CLK_FEED_WW2END1", - "CLK_PMV_IMUX23_0", - "CLK_FEED_CK_GCLK20", - "CLK_PMV_IMUX32_0", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_NW2A3", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_WW2A1", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_WW4B3", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4END1", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_EE4B1", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_NE2A1", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_EE4A0", - "CLK_FEED_WL1END1", - "CLK_FEED_EE2BEG1", - "CLK_FEED_WW2END0", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_SE4BEG0" - ], - "sites": [], "pips": {}, - "tile_type": "CLK_MTBF2" + "wires": [ + "CLK_FEED_CK_GCLK13", + "CLK_FEED_CK_BUFG_CASC3", + "CLK_FEED_WW4B2", + "CLK_FEED_EE4B2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_WW2A0", + "CLK_PMV_BYP3_0", + "CLK_FEED_EE4A2", + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_PMV_FAN5_0", + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_PMV_FAN1_0", + "CLK_FEED_EE4BEG1", + "CLK_FEED_CK_GCLK29", + "CLK_PMV_IMUX46_0", + "CLK_FEED_WW4C0", + "CLK_FEED_EE4BEG2", + "CLK_PMV_BYP0_0", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_FEED_CK_GCLK19", + "CLK_FEED_CK_BUFG_CASC22", + "CLK_PMV_IMUX44_0", + "CLK_FEED_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_PMV_IMUX36_0", + "CLK_FEED_SW4END1", + "CLK_PMV_BYP5_0", + "CLK_PMV_IMUX2_0", + "CLK_FEED_LH12", + "CLK_PMV_IMUX5_0", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_FEED_WW4END3", + "CLK_FEED_SE4C1", + "CLK_FEED_CK_GCLK9", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_PMV_IMUX25_0", + "CLK_FEED_EE4C3", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_WW2END0", + "CLK_FEED_CK_GCLK2", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_CK_GCLK15", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_PMV_CTRL0_0", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_PMV_FAN0_0", + "CLK_PMV_IMUX43_0", + "CLK_FEED_NE4BEG0", + "CLK_FEED_SE4BEG3", + "CLK_FEED_WW4A2", + "CLK_FEED_SE4BEG1", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_WW2A2", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_PMV_IMUX17_0", + "CLK_MTBF2_EN", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_EE4BEG0", + "CLK_PMV_IMUX13_0", + "CLK_FEED_CK_GCLK11", + "CLK_PMV_IMUX20_0", + "CLK_FEED_CK_GCLK27", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_LH10", + "CLK_MTBF2_Q6B", + "CLK_PMV_IMUX22_0", + "CLK_FEED_SE4C0", + "CLK_FEED_LH3", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_IMUX7_0", + "CLK_PMV_IMUX31_0", + "CLK_FEED_WW2A3", + "CLK_FEED_NW4A1", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_PMV_IMUX28_0", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_LH5", + "CLK_FEED_NW4A2", + "CLK_PMV_BYP1_0", + "CLK_FEED_WW4END1", + "CLK_FEED_EE2BEG2", + "CLK_FEED_WL1END0", + "CLK_FEED_NE4BEG3", + "CLK_PMV_IMUX42_0", + "CLK_PMV_FAN3_0", + "CLK_FEED_WL1END1", + "CLK_FEED_SW2A1", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_FEED_EE2BEG0", + "CLK_FEED_CK_GCLK7", + "CLK_PMV_IMUX40_0", + "CLK_FEED_CK_GCLK22", + "CLK_FEED_EE4A1", + "CLK_FEED_EE4BEG3", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_CK_BUFG_CASC8", + "CLK_FEED_EE2BEG1", + "CLK_FEED_SW4END0", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_SE4BEG2", + "CLK_FEED_NE2A3", + "CLK_MTBF2_Q5B", + "CLK_FEED_LH8", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_PMV_IMUX29_0", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK25", + "CLK_MTBF2_Q0B", + "CLK_FEED_WW4END2", + "CLK_FEED_SW4A3", + "CLK_PMV_IMUX26_0", + "CLK_FEED_LH11", + "CLK_PMV_IMUX0_0", + "CLK_PMV_IMUX11_0", + "CLK_FEED_EE4C1", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_IMUX15_0", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_NE4C0", + "CLK_FEED_CK_GCLK24", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_SE4C2", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_ER1BEG1", + "CLK_PMV_IMUX41_0", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_MONITOR_P", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_PMV_IMUX45_0", + "CLK_PMV_IMUX8_0", + "CLK_FEED_WW4C3", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_WW2END2", + "CLK_FEED_SE2A1", + "CLK_FEED_WW4A3", + "CLK_FEED_CK_GCLK8", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_EL1BEG1", + "CLK_PMV_IMUX34_0", + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_EE2BEG3", + "CLK_FEED_LH7", + "CLK_FEED_SW4A0", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_PMV_FAN7_0", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_FEED_LH9", + "CLK_MTBF2_Q4B", + "CLK_FEED_SW4A2", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK28", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_MONITOR_N", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_FEED_EE4B3", + "CLK_PMV_IMUX24_0", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_PMV_IMUX1_0", + "CLK_FEED_NE2A1", + "CLK_FEED_CK_GCLK25", + "CLK_PMV_FAN2_0", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_SW4END2", + "CLK_PMV_CLK1_0", + "CLK_PMV_BYP4_0", + "CLK_PMV_IMUX32_0", + "CLK_PMV_IMUX9_0", + "CLK_FEED_EE2A1", + "CLK_FEED_SE2A3", + "CLK_FEED_SW2A0", + "CLK_FEED_NE2A2", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_FEED_WW4C2", + "CLK_MTBF2_RESET", + "CLK_FEED_NE4BEG1", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_NW2A1", + "CLK_FEED_EE4B0", + "CLK_FEED_NE4C2", + "CLK_PMV_IMUX10_0", + "CLK_FEED_R_CK_GCLK15", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_FEED_WW4B0", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_PMV_BYP2_0", + "CLK_MTBF2_Q1B", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_FEED_WW2END1", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_PMV_FAN6_0", + "CLK_PMV_IMUX37_0", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_WR1END0", + "CLK_FEED_EE4A3", + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_NW2A2", + "CLK_PMV_IMUX4_0", + "CLK_FEED_LH4", + "CLK_FEED_EE2A0", + "CLK_PMV_IMUX35_0", + "CLK_PMV_IMUX16_0", + "CLK_FEED_ER1BEG2", + "CLK_FEED_ER1BEG3", + "CLK_FEED_WW4A0", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_WR1END3", + "CLK_FEED_LH1", + "CLK_FEED_EE2A3", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2END3", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_SE4C3", + "CLK_MTBF2_CLK", + "CLK_PMV_IMUX23_0", + "CLK_PMV_IMUX38_0", + "CLK_PMV_IMUX12_0", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_NW4END2", + "CLK_FEED_EE4C0", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_WL1END3", + "CLK_FEED_NW2A0", + "CLK_FEED_ER1BEG0", + "CLK_FEED_NW4A0", + "CLK_FEED_WW4A1", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_FEED_LH2", + "CLK_FEED_SW2A2", + "CLK_MTBF2_Q3B", + "CLK_PMV_BYP6_0", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_PMV_IMUX3_0", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_CK_GCLK18", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_LH6", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_GCLK2", + "CLK_PMV_IMUX21_0", + "CLK_FEED_NW4END3", + "CLK_FEED_NE4C1", + "CLK_MTBF2_DIN", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WW2A1", + "CLK_FEED_R_CK_GCLK16", + "CLK_PMV_IMUX33_0", + "CLK_PMV_IMUX18_0", + "CLK_FEED_SE4BEG0", + "CLK_FEED_WL1END2", + "CLK_FEED_NW4END1", + "CLK_FEED_NW4END0", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_FEED_SE2A0", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_WR1END2", + "CLK_FEED_SW4END3", + "CLK_FEED_WW4END0", + "CLK_PMV_CTRL1_0", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_FEED_EE4B1", + "CLK_FEED_SW4A1", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_NE4C3", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_CK_GCLK23", + "CLK_PMV_IMUX19_0", + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_EE2A2", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_FEED_CK_BUFG_CASC16", + "CLK_FEED_NE2A0", + "CLK_MTBF2_Q2B", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_PMV_IMUX39_0", + "CLK_PMV_IMUX6_0", + "CLK_FEED_SE2A2", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_SW2A3", + "CLK_FEED_EE4A0", + "CLK_FEED_CK_GCLK30", + "CLK_PMV_CLK0_0", + "CLK_FEED_EL1BEG3", + "CLK_FEED_WW4C1", + "CLK_PMV_FAN4_0", + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_FEED_EL1BEG0", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_FEED_R_CK_GCLK31", + "CLK_MTBF2_Q7B", + "CLK_PMV_IMUX30_0", + "CLK_PMV_IMUX27_0", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_EE4C2", + "CLK_PMV_IMUX47_0", + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_PMV_IMUX14_0", + "CLK_FEED_WW4B3", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_PMV_BYP7_0", + "CLK_FEED_EL1BEG2", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_WW4B1" + ], + "tile_type": "CLK_MTBF2", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_PMV.json b/artix7/tile_type_CLK_PMV.json index 631db18..e29ee19 100644 --- a/artix7/tile_type_CLK_PMV.json +++ b/artix7/tile_type_CLK_PMV.json @@ -1,1671 +1,1671 @@ { + "pips": {}, "wires": [ - "CLK_PMV_IMUX20_6", - "CLK_PMV_LH2_4", - "CLK_PMV_FAN0_4", - "CLK_PMV_EE4C1_5", - "CLK_PMV_SW2A3_5", - "CLK_PMV_EE4C2_0", - "CLK_PMV_NE2A3_5", - "CLK_PMV_WW4A2_0", - "CLK_PMV_NW4END0_3", - "CLK_PMV_EE4B2_3", - "CLK_PMV_CK_GCLK20", - "CLK_PMV_LH3_1", - "CLK_PMV_IMUX26_3", - "CLK_PMV_R_CK_BUFG_CASC16", - "CLK_PMV_NW4END0_5", - "CLK_PMV_EE2BEG1_1", - "CLK_PMV_BYP0_3", - "CLK_PMV_SW4A2_0", - "CLK_PMV_BYP1_2", - "CLK_PMV_WW4END2_6", - "CLK_PMV_FAN3_5", - "CLK_PMV_EE4BEG1_6", - "CLK_PMV_IMUX8_6", - "CLK_PMV_IMUX41_6", - "CLK_PMV_FAN7_1", - "CLK_PMV_WW4C2_0", - "CLK_PMV_EE4B2_5", - "CLK_PMV_EE4A1_0", - "CLK_PMV_IMUX10_4", - "CLK_PMV_WW4END3_1", - "CLK_PMV_NE4C1_6", - "CLK_PMV_LOGIC_OUTS11_1", - "CLK_PMV_ER1BEG2_0", - "CLK_PMV_FAN6_5", - "CLK_PMV_CK_BUFG_CASC26", - "CLK_PMV_LH9_6", - "CLK_PMV_IMUX45_3", - "CLK_PMV_NW4END2_3", - "CLK_PMV_IMUX23_4", - "CLK_PMV_NE4C0_6", - "CLK_PMV_R_CK_GCLK3", - "CLK_PMV_WW4C1_3", - "CLK_PMV_ER1BEG0_3", - "CLK_PMV_CK_BUFG_CASC27", - "CLK_PMV_EN", - "CLK_PMV_NE2A1_2", - "CLK_PMV_CLK0_3", - "CLK_PMV_FAN1_6", - "CLK_PMV_FAN1_1", - "CLK_PMV_CK_BUFG_CASC24", - "CLK_PMV_IMUX7_4", - "CLK_PMV_IMUX11_1", - "CLK_PMV_FAN0_6", - "CLK_PMV_WR1END3_5", - "CLK_PMV_IMUX1_6", - "CLK_PMV_SE4BEG1_1", - "CLK_PMV_WW2A2_5", - "CLK_PMV_FAN5_2", - "CLK_PMV_FAN3_1", - "CLK_PMV_MONITOR_P_1", - "CLK_PMV_WW4C0_0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_SW4A3_1", - "CLK_PMV_WL1END1_6", - "CLK_PMV_NE4C2_4", - "CLK_PMV_IMUX24_3", - "CLK_PMV_CK_BUFG_CASC31", - "CLK_PMV_BYP4_6", - "CLK_PMV_SW4END1_1", - "CLK_PMV_IMUX33_3", - "CLK_PMV_LH9_0", - "CLK_PMV_WW2A1_0", - "CLK_PMV_IMUX14_0", - "CLK_PMV_SE4C0_5", - "CLK_PMV_IMUX2_6", - "CLK_PMV_EE4BEG3_6", - "CLK_PMV_LOGIC_OUTS9_2", - "CLK_PMV_NW4END0_0", - "CLK_PMV_NE4BEG1_6", - "CLK_PMV_IMUX45_5", - "CLK_PMV_IMUX10_5", - "CLK_PMV_NE4BEG2_1", - "CLK_PMV_LH11_4", - "CLK_PMV_CK_BUFG_CASC18", - "CLK_PMV_SE4C2_0", - "CLK_PMV_ER1BEG3_1", - "CLK_PMV_BYP6_4", - "CLK_PMV_SE4BEG2_1", - "CLK_PMV_IMUX35_6", - "CLK_PMV_CK_BUFG_CASC20", - "CLK_PMV_SE4C1_2", - "CLK_PMV_WW4B0_1", - "CLK_PMV_NW2A2_6", - "CLK_PMV_WW4B1_3", - "CLK_PMV_MONITOR_N_3", - "CLK_PMV_BYP0_2", - "CLK_PMV_CK_GCLK16", - "CLK_PMV_NE4BEG0_3", - "CLK_PMV_WW2END3_6", - "CLK_PMV_LOGIC_OUTS15_5", - "CLK_PMV_WW4C1_6", - "CLK_PMV_NE4BEG3_3", - "CLK_PMV_WL1END1_0", - "CLK_PMV_IMUX46_3", - "CLK_PMV_WL1END2_1", - "CLK_PMV_FAN6_0", - "CLK_PMV_BYP1_4", - "CLK_PMV_EE2BEG0_0", - "CLK_PMV_SE2A0_4", - "CLK_PMV_IMUX28_1", - "CLK_PMV_LH2_6", - "CLK_PMV_IMUX11_5", - "CLK_PMV_NW2A2_1", - "CLK_PMV_LOGIC_OUTS8_5", - "CLK_PMV_IMUX38_4", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX0_6", - "CLK_PMV_LOGIC_OUTS7_6", - "CLK_PMV_LOGIC_OUTS13_4", - "CLK_PMV_NE2A2_5", - "CLK_PMV_NW2A1_0", - "CLK_PMV_WW4A2_3", - "CLK_PMV_WW4C2_4", - "CLK_PMV_CK_BUFG_CASC15", - "CLK_PMV_IMUX43_6", - "CLK_PMV_NE4BEG0_1", - "CLK_PMV_NE4BEG3_0", - "CLK_PMV_WW4A0_5", - "CLK_PMV_LOGIC_OUTS16_4", - "CLK_PMV_SW2A2_3", - "CLK_PMV_FAN6_2", - "CLK_PMV_LH12_1", - "CLK_PMV_IMUX13_5", - "CLK_PMV_WW4A3_4", - "CLK_PMV_EE4A1_4", - "CLK_PMV_IMUX12_2", - "CLK_PMV_EE2BEG2_3", - "CLK_PMV_IMUX38_2", - "CLK_PMV_NW4END0_6", - "CLK_PMV_NE4C1_1", - "CLK_PMV_IMUX17_1", - "CLK_PMV_NE2A1_6", - "CLK_PMV_IMUX41_2", - "CLK_PMV_LOGIC_OUTS20_1", - "CLK_PMV_NE4C0_5", - "CLK_PMV_CK_BUFG_CASC10", - "CLK_PMV_EE4A1_2", - "CLK_PMV_EL1BEG2_0", - "CLK_PMV_MONITOR_P_2", - "CLK_PMV_EE2BEG1_3", - "CLK_PMV_WW4C0_5", - "CLK_PMV_WL1END3_4", - "CLK_PMV_CLK0_4", - "CLK_PMV_EE4B2_2", - "CLK_PMV_BYP0_5", - "CLK_PMV_LOGIC_OUTS23_2", - "CLK_PMV_LOGIC_OUTS13_6", - "CLK_PMV_IMUX1_1", - "CLK_PMV_FAN1_3", - "CLK_PMV_IMUX47_3", - "CLK_PMV_EL1BEG0_3", - "CLK_PMV_ER1BEG3_2", - "CLK_PMV_WW4B2_6", - "CLK_PMV_IMUX32_6", - "CLK_PMV_IMUX32_2", - "CLK_PMV_BYP1_5", - "CLK_PMV_WW2A0_6", - "CLK_PMV_NE4C0_0", - "CLK_PMV_CK_GCLK24", - "CLK_PMV_O", - "CLK_PMV_BYP0_0", - "CLK_PMV_NW4A0_0", - "CLK_PMV_IMUX24_5", - "CLK_PMV_LH1_4", - "CLK_PMV_EE2BEG3_5", - "CLK_PMV_R_CK_BUFG_CASC11", - "CLK_PMV_NW2A3_0", - "CLK_PMV_NE2A3_3", - "CLK_PMV_IMUX15_4", - "CLK_PMV_LOGIC_OUTS0_5", - "CLK_PMV_IMUX34_1", - "CLK_PMV_ER1BEG0_1", - "CLK_PMV_LOGIC_OUTS5_3", - "CLK_PMV_EE4C1_0", - "CLK_PMV_IMUX19_3", - "CLK_PMV_R_CK_BUFG_CASC27", - "CLK_PMV_WR1END0_1", - "CLK_PMV_CK_GCLK28", - "CLK_PMV_NW4END3_2", - "CLK_PMV_SW4A3_0", - "CLK_PMV_CK_GCLK23", - "CLK_PMV_EE2BEG2_2", - "CLK_PMV_R_CK_GCLK21", - "CLK_PMV_NE4C2_1", - "CLK_PMV_IMUX38_6", - "CLK_PMV_IMUX27_5", - "CLK_PMV_EL1BEG1_6", - "CLK_PMV_EE2BEG0_1", - "CLK_PMV_EE2BEG3_3", - "CLK_PMV_ER1BEG1_5", - "CLK_PMV_IMUX10_1", - "CLK_PMV_IMUX37_4", - "CLK_PMV_NW2A0_2", - "CLK_PMV_SE2A1_2", - "CLK_PMV_NE2A3_2", - "CLK_PMV_NW4A2_0", - "CLK_PMV_WW4B0_0", - "CLK_PMV_LOGIC_OUTS17_6", - "CLK_PMV_EE4A0_1", - "CLK_PMV_CK_GCLK7", - "CLK_PMV_R_CK_GCLK14", - "CLK_PMV_IMUX24_4", - "CLK_PMV_WW4END1_6", - "CLK_PMV_LOGIC_OUTS1_2", - "CLK_PMV_NW2A2_3", - "CLK_PMV_NE4BEG1_4", - "CLK_PMV_R_CK_BUFG_CASC25", - "CLK_PMV_EL1BEG1_5", - "CLK_PMV_NW4A3_0", - "CLK_PMV_IMUX46_5", - "CLK_PMV_MONITOR_N_2", - "CLK_PMV_LOGIC_OUTS18_3", - "CLK_PMV_IMUX40_2", - "CLK_PMV_BYP5_4", - "CLK_PMV_LOGIC_OUTS21_6", - "CLK_PMV_SE4C2_5", - "CLK_PMV_NE4BEG1_0", - "CLK_PMV_WL1END3_2", - "CLK_PMV_FAN2_4", - "CLK_PMV_LOGIC_OUTS15_1", - "CLK_PMV_WW4C3_6", - "CLK_PMV_NW4END0_2", - "CLK_PMV_LOGIC_OUTS1_6", - "CLK_PMV_WL1END0_0", - "CLK_PMV_IMUX14_2", - "CLK_PMV_SE4C0_4", - "CLK_PMV_LH6_3", - "CLK_PMV_IMUX22_1", - "CLK_PMV_R_CK_GCLK26", - "CLK_PMV_FAN6_6", - "CLK_PMV_IMUX37_3", - "CLK_PMV_WW2A2_0", - "CLK_PMV_LH8_2", - "CLK_PMV_EL1BEG1_3", - "CLK_PMV_WW4C3_0", - "CLK_PMV_SW2A2_2", - "CLK_PMV_ER1BEG1_3", - "CLK_PMV_NE2A3_1", - "CLK_PMV_R_CK_BUFG_CASC19", - "CLK_PMV_R_CK_GCLK22", - "CLK_PMV_WW4B1_0", - "CLK_PMV_NW4A0_3", - "CLK_PMV_CK_BUFG_CASC19", - "CLK_PMV_LH4_6", - "CLK_PMV_WL1END3_3", - "CLK_PMV_LOGIC_OUTS17_1", - "CLK_PMV_IMUX32_3", - "CLK_PMV_R_CK_GCLK4", - "CLK_PMV_EE4B0_2", - "CLK_PMV_LOGIC_OUTS2_5", - "CLK_PMV_ODIV2", - "CLK_PMV_ODIV4", - "CLK_PMV_SW4END0_3", - "CLK_PMV_NE2A2_3", - "CLK_PMV_NW4END3_6", - "CLK_PMV_EE4BEG2_2", - "CLK_PMV_WR1END2_3", - "CLK_PMV_SW2A2_4", - "CLK_PMV_IMUX6_2", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LH5_6", - "CLK_PMV_SW4A1_5", - "CLK_PMV_EE2BEG2_6", - "CLK_PMV_WW4END0_6", - "CLK_PMV_IMUX35_2", - "CLK_PMV_NE4C3_1", - "CLK_PMV_WW2A0_1", - "CLK_PMV_NW4A3_3", - "CLK_PMV_IMUX39_2", - "CLK_PMV_WW2A3_6", - "CLK_PMV_NE4BEG1_2", - "CLK_PMV_LOGIC_OUTS6_6", - "CLK_PMV_FAN2_1", - "CLK_PMV_WW2A0_3", - "CLK_PMV_IMUX27_1", - "CLK_PMV_FAN1_0", - "CLK_PMV_EE4A1_6", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LH5_3", - "CLK_PMV_WL1END2_0", - "CLK_PMV_WR1END1_1", - "CLK_PMV_IMUX4_1", - "CLK_PMV_WW2A0_0", - "CLK_PMV_FAN6_1", - "CLK_PMV_IMUX14_4", - "CLK_PMV_EE4BEG0_2", - "CLK_PMV_IMUX26_0", - "CLK_PMV_CTRL0_1", - "CLK_PMV_SW2A0_5", - "CLK_PMV_WW4B1_1", - "CLK_PMV_IMUX45_4", - "CLK_PMV_EE2A2_0", - "CLK_PMV_SW4END0_6", - "CLK_PMV_A0", - "CLK_PMV_IMUX42_4", - "CLK_PMV_NE2A0_0", - "CLK_PMV_IMUX6_6", - "CLK_PMV_IMUX9_5", - "CLK_PMV_IMUX43_4", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_NW4A0_5", - "CLK_PMV_CK_BUFG_CASC17", - "CLK_PMV_IMUX43_2", - "CLK_PMV_EL1BEG2_6", - "CLK_PMV_NE2A0_1", - "CLK_PMV_MONITOR_P_4", - "CLK_PMV_LOGIC_OUTS10_6", - "CLK_PMV_WW2END0_4", - "CLK_PMV_LH3_2", - "CLK_PMV_LOGIC_OUTS16_5", - "CLK_PMV_LOGIC_OUTS20_6", - "CLK_PMV_ER1BEG1_6", - "CLK_PMV_LH6_5", - "CLK_PMV_IMUX1_5", - "CLK_PMV_WL1END1_4", - "CLK_PMV_IMUX13_2", - "CLK_PMV_R_CK_BUFG_CASC4", - "CLK_PMV_SE2A0_6", - "CLK_PMV_CK_GCLK5", - "CLK_PMV_EE4BEG1_2", - "CLK_PMV_LH1_0", - "CLK_PMV_IMUX36_1", - "CLK_PMV_EE2A3_5", - "CLK_PMV_LOGIC_OUTS5_5", - "CLK_PMV_WL1END0_3", - "CLK_PMV_SW4A2_1", - "CLK_PMV_LOGIC_OUTS15_3", - "CLK_PMV_WW2END0_6", - "CLK_PMV_IMUX35_5", - "CLK_PMV_EE4BEG0_3", - "CLK_PMV_IMUX42_2", - "CLK_PMV_IMUX13_6", - "CLK_PMV_NW4END2_0", - "CLK_PMV_IMUX2_5", - "CLK_PMV_R_CK_BUFG_CASC9", - "CLK_PMV_IMUX30_6", - "CLK_PMV_EE2A3_0", - "CLK_PMV_LOGIC_OUTS9_0", - "CLK_PMV_EE2A3_4", - "CLK_PMV_WW2END2_2", - "CLK_PMV_LOGIC_OUTS19_4", - "CLK_PMV_IMUX39_3", - "CLK_PMV_SE2A1_1", - "CLK_PMV_EL1BEG1_0", - "CLK_PMV_LOGIC_OUTS12_6", - "CLK_PMV_WL1END0_2", - "CLK_PMV_WW2END3_1", - "CLK_PMV_ER1BEG0_5", - "CLK_PMV_SE4BEG3_6", - "CLK_PMV_WW4C2_6", - "CLK_PMV_ER1BEG2_2", - "CLK_PMV_EE4C2_1", - "CLK_PMV_WW4B3_6", - "CLK_PMV_IMUX37_0", - "CLK_PMV_EE4B0_3", - "CLK_PMV_LOGIC_OUTS11_2", - "CLK_PMV_FAN7_3", - "CLK_PMV_LOGIC_OUTS22_2", - "CLK_PMV_LH3_5", - "CLK_PMV_IMUX31_5", - "CLK_PMV_CK_GCLK3", - "CLK_PMV_NE2A0_4", - "CLK_PMV_R_CK_GCLK17", - "CLK_PMV_WL1END2_6", - "CLK_PMV_CK_GCLK19", - "CLK_PMV_WW2END0_5", - "CLK_PMV_SE4BEG1_4", - "CLK_PMV_NW2A0_5", - "CLK_PMV_WW4B1_4", - "CLK_PMV_EE4C2_6", - "CLK_PMV_SW4END0_5", - "CLK_PMV_LH6_4", - "CLK_PMV_SW2A3_4", - "CLK_PMV_SE2A1_0", - "CLK_PMV_EE4B3_2", - "CLK_PMV_R_CK_GCLK12", - "CLK_PMV_FAN3_6", - "CLK_PMV_R_CK_GCLK29", - "CLK_PMV_IMUX39_5", - "CLK_PMV_NE4BEG3_5", - "CLK_PMV_SE2A0_5", - "CLK_PMV_CK_BUFG_CASC4", - "CLK_PMV_IMUX28_5", - "CLK_PMV_CK_BUFG_CASC7", - "CLK_PMV_IMUX29_2", - "CLK_PMV_IMUX8_5", - "CLK_PMV_NW4END1_0", - "CLK_PMV_LOGIC_OUTS4_1", - "CLK_PMV_ER1BEG0_0", - "CLK_PMV_FAN5_4", - "CLK_PMV_IMUX11_6", - "CLK_PMV_EE2BEG3_2", - "CLK_PMV_WR1END3_1", - "CLK_PMV_EE4B0_6", - "CLK_PMV_NE2A1_1", - "CLK_PMV_FAN5_6", - "CLK_PMV_EE2BEG0_6", - "CLK_PMV_ER1BEG2_4", - "CLK_PMV_BYP2_3", - "CLK_PMV_CK_GCLK6", - "CLK_PMV_WW2A3_0", - "CLK_PMV_LOGIC_OUTS15_6", - "CLK_PMV_EL1BEG3_2", - "CLK_PMV_CK_BUFG_CASC0", - "CLK_PMV_WW4B3_2", - "CLK_PMV_LH10_0", - "CLK_PMV_IMUX9_2", - "CLK_PMV_IMUX37_5", - "CLK_PMV_WW2END2_4", - "CLK_PMV_LOGIC_OUTS13_3", - "CLK_PMV_LOGIC_OUTS2_1", - "CLK_PMV_BYP7_5", - "CLK_PMV_EL1BEG2_4", - "CLK_PMV_LOGIC_OUTS23_3", - "CLK_PMV_IMUX17_5", - "CLK_PMV_LH4_1", - "CLK_PMV_WW4A3_5", - "CLK_PMV_LOGIC_OUTS15_4", - "CLK_PMV_SW4END1_6", - "CLK_PMV_R_CK_GCLK31", - "CLK_PMV_SW4A0_4", - "CLK_PMV_BYP5_1", - "CLK_PMV_IMUX7_3", - "CLK_PMV_SW2A2_0", - "CLK_PMV_SW4END3_2", - "CLK_PMV_NW4A2_1", - "CLK_PMV_WW4B2_2", - "CLK_PMV_NW4A3_4", - "CLK_PMV_SW2A0_3", - "CLK_PMV_SE4BEG2_6", - "CLK_PMV_NE4BEG3_2", - "CLK_PMV_EE4B1_3", - "CLK_PMV_WW4END3_0", - "CLK_PMV_FAN3_2", - "CLK_PMV_SW4END2_6", - "CLK_PMV_CK_GCLK4", - "CLK_PMV_IMUX9_1", - "CLK_PMV_CTRL0_5", - "CLK_PMV_SE2A0_3", - "CLK_PMV_NE2A0_2", - "CLK_PMV_NE4C3_5", - "CLK_PMV_WW2END1_5", - "CLK_PMV_BYP3_1", - "CLK_PMV_LOGIC_OUTS9_6", - "CLK_PMV_LOGIC_OUTS8_4", - "CLK_PMV_WW4A2_4", - "CLK_PMV_EE2A1_5", - "CLK_PMV_LH11_2", - "CLK_PMV_IMUX5_1", - "CLK_PMV_SW4END2_4", - "CLK_PMV_SE4C1_3", - "CLK_PMV_IMUX17_0", - "CLK_PMV_SW4A3_5", - "CLK_PMV_EE2A1_4", - "CLK_PMV_NW2A0_4", - "CLK_PMV_IMUX19_2", - "CLK_PMV_WW4A1_5", - "CLK_PMV_BYP5_6", - "CLK_PMV_WW4B2_3", - "CLK_PMV_LH2_5", - "CLK_PMV_IMUX7_6", - "CLK_PMV_EE4B1_6", - "CLK_PMV_SE4C1_1", - "CLK_PMV_WW4END0_5", - "CLK_PMV_WW2A2_2", - "CLK_PMV_WR1END2_0", - "CLK_PMV_EE4BEG1_4", - "CLK_PMV_EE4BEG3_0", - "CLK_PMV_SE2A2_5", - "CLK_PMV_R_CK_GCLK6", - "CLK_PMV_ER1BEG3_5", - "CLK_PMV_CK_GCLK17", - "CLK_PMV_IMUX34_4", - "CLK_PMV_LH7_3", - "CLK_PMV_EE2BEG0_4", - "CLK_PMV_NE4C1_3", - "CLK_PMV_NE4C3_0", - "CLK_PMV_IMUX38_3", - "CLK_PMV_WL1END1_5", - "CLK_PMV_NE2A3_4", - "CLK_PMV_LOGIC_OUTS9_5", - "CLK_PMV_SE4BEG2_0", - "CLK_PMV_SW4END1_2", - "CLK_PMV_IMUX36_2", - "CLK_PMV_IMUX33_5", - "CLK_PMV_IMUX21_3", - "CLK_PMV_EE4BEG3_1", - "CLK_PMV_IMUX31_4", - "CLK_PMV_IMUX8_3", - "CLK_PMV_EE2BEG2_1", - "CLK_PMV_IMUX44_5", - "CLK_PMV_SE4C2_4", - "CLK_PMV_IMUX45_6", - "CLK_PMV_IMUX6_3", - "CLK_PMV_WW4A0_2", - "CLK_PMV_SE2A2_3", - "CLK_PMV_NW4END3_3", - "CLK_PMV_IMUX10_3", - "CLK_PMV_NW2A1_4", - "CLK_PMV_LOGIC_OUTS17_5", - "CLK_PMV_FAN4_1", - "CLK_PMV_SW2A1_0", - "CLK_PMV_LOGIC_OUTS22_1", - "CLK_PMV_CK_BUFG_CASC2", - "CLK_PMV_A4", - "CLK_PMV_NW4A0_4", - "CLK_PMV_WW4C2_3", - "CLK_PMV_WR1END1_4", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_CK_BUFG_CASC11", - "CLK_PMV_FAN2_5", - "CLK_PMV_SW4A1_4", - "CLK_PMV_NW4END2_2", - "CLK_PMV_WW2END1_4", - "CLK_PMV_R_CK_GCLK30", - "CLK_PMV_R_CK_BUFG_CASC1", - "CLK_PMV_SW4A2_4", - "CLK_PMV_WR1END3_6", - "CLK_PMV_IMUX17_4", - "CLK_PMV_CK_GCLK12", - "CLK_PMV_BYP6_2", - "CLK_PMV_SW4A0_2", - "CLK_PMV_BYP2_1", - "CLK_PMV_SE4C3_6", - "CLK_PMV_LOGIC_OUTS6_1", - "CLK_PMV_NW4A1_1", - "CLK_PMV_SW4A1_2", - "CLK_PMV_EE2BEG1_2", - "CLK_PMV_EE4C3_1", - "CLK_PMV_EE2A3_6", - "CLK_PMV_EE4B3_4", - "CLK_PMV_NE2A1_3", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_SW2A1_5", - "CLK_PMV_EL1BEG0_6", - "CLK_PMV_CLK1_2", - "CLK_PMV_LOGIC_OUTS18_5", - "CLK_PMV_IMUX4_5", - "CLK_PMV_FAN0_0", - "CLK_PMV_NE2A2_6", - "CLK_PMV_LOGIC_OUTS5_1", - "CLK_PMV_LOGIC_OUTS21_2", - "CLK_PMV_NW4END1_1", - "CLK_PMV_R_CK_GCLK16", - "CLK_PMV_IMUX44_3", - "CLK_PMV_LOGIC_OUTS8_2", - "CLK_PMV_CK_BUFG_CASC16", - "CLK_PMV_BYP6_1", - "CLK_PMV_SW4END3_6", - "CLK_PMV_SE4BEG1_6", - "CLK_PMV_EE2BEG1_6", - "CLK_PMV_IMUX28_4", - "CLK_PMV_IMUX43_3", - "CLK_PMV_SE4C0_6", - "CLK_PMV_NE2A0_3", - "CLK_PMV_MONITOR_N_0", - "CLK_PMV_IMUX25_6", - "CLK_PMV_LOGIC_OUTS23_4", - "CLK_PMV_EE2BEG3_6", - "CLK_PMV_SW2A0_1", - "CLK_PMV_WW4B0_2", - "CLK_PMV_CLK0_6", - "CLK_PMV_EL1BEG0_5", - "CLK_PMV_R_CK_BUFG_CASC20", - "CLK_PMV_NE2A2_4", - "CLK_PMV_CK_GCLK29", - "CLK_PMV_EE4B3_0", - "CLK_PMV_LOGIC_OUTS8_6", - "CLK_PMV_NW4A1_3", - "CLK_PMV_EL1BEG0_0", - "CLK_PMV_WW4B2_5", - "CLK_PMV_LOGIC_OUTS12_1", - "CLK_PMV_EE4C1_2", - "CLK_PMV_BYP3_5", - "CLK_PMV_IMUX36_4", - "CLK_PMV_BYP4_5", - "CLK_PMV_WW2END2_1", - "CLK_PMV_LOGIC_OUTS6_3", - "CLK_PMV_IMUX16_6", - "CLK_PMV_SW2A2_1", - "CLK_PMV_IMUX28_2", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_IMUX25_5", - "CLK_PMV_NW4A2_5", - "CLK_PMV_FAN2_0", - "CLK_PMV_BYP6_6", - "CLK_PMV_SE2A1_3", - "CLK_PMV_WW4A1_0", - "CLK_PMV_R_CK_GCLK7", - "CLK_PMV_LOGIC_OUTS18_4", - "CLK_PMV_IMUX39_0", - "CLK_PMV_EE4BEG2_3", - "CLK_PMV_NW4END3_0", - "CLK_PMV_EE4A0_2", - "CLK_PMV_LH12_6", - "CLK_PMV_WW4A0_0", - "CLK_PMV_SW2A0_4", - "CLK_PMV_IMUX25_4", - "CLK_PMV_EE4A1_1", - "CLK_PMV_CK_GCLK22", - "CLK_PMV_EE2A0_6", - "CLK_PMV_SW4A2_5", - "CLK_PMV_IMUX40_6", - "CLK_PMV_SW4END2_5", - "CLK_PMV_IMUX11_2", - "CLK_PMV_WW2A3_5", - "CLK_PMV_SE4C1_4", - "CLK_PMV_WW2END3_5", - "CLK_PMV_EE4A3_6", - "CLK_PMV_IMUX15_3", - "CLK_PMV_IMUX5_4", - "CLK_PMV_LOGIC_OUTS14_2", - "CLK_PMV_IMUX2_1", - "CLK_PMV_IMUX3_3", - "CLK_PMV_IMUX22_0", - "CLK_PMV_NW4END3_5", - "CLK_PMV_FAN3_3", - "CLK_PMV_EE4BEG3_4", - "CLK_PMV_WW2END3_0", - "CLK_PMV_CK_GCLK9", - "CLK_PMV_BYP5_2", - "CLK_PMV_LOGIC_OUTS2_4", - "CLK_PMV_IMUX18_3", - "CLK_PMV_IMUX28_0", - "CLK_PMV_EE4BEG2_4", - "CLK_PMV_CTRL1_0", - "CLK_PMV_LOGIC_OUTS7_5", - "CLK_PMV_NW4END3_1", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CK_GCLK15", - "CLK_PMV_EE4A2_5", - "CLK_PMV_SE2A3_2", - "CLK_PMV_IMUX41_1", - "CLK_PMV_NE4BEG0_5", - "CLK_PMV_LOGIC_OUTS21_5", - "CLK_PMV_WW2A3_2", - "CLK_PMV_IMUX9_3", - "CLK_PMV_SE4BEG3_1", - "CLK_PMV_WR1END0_3", - "CLK_PMV_IMUX17_2", - "CLK_PMV_FAN7_2", - "CLK_PMV_IMUX16_4", - "CLK_PMV_IMUX24_1", - "CLK_PMV_WW4C3_1", - "CLK_PMV_BYP3_3", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX33_0", - "CLK_PMV_WR1END0_5", - "CLK_PMV_WW4B3_4", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS5_4", - "CLK_PMV_LH6_6", - "CLK_PMV_WW4C2_5", - "CLK_PMV_LOGIC_OUTS7_1", - "CLK_PMV_NE4C2_0", - "CLK_PMV_IMUX15_5", - "CLK_PMV_CK_BUFG_CASC5", - "CLK_PMV_EE2A0_1", - "CLK_PMV_WW4B3_0", - "CLK_PMV_IMUX9_0", - "CLK_PMV_BYP3_0", - "CLK_PMV_IMUX45_1", - "CLK_PMV_SW4A3_3", - "CLK_PMV_LOGIC_OUTS3_4", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX26_5", - "CLK_PMV_EE2BEG1_5", - "CLK_PMV_IMUX40_4", - "CLK_PMV_LOGIC_OUTS0_1", - "CLK_PMV_WW4C1_4", - "CLK_PMV_ER1BEG3_4", - "CLK_PMV_EE4BEG2_1", - "CLK_PMV_CK_GCLK10", - "CLK_PMV_EE4C2_4", - "CLK_PMV_LOGIC_OUTS22_6", - "CLK_PMV_LOGIC_OUTS10_4", - "CLK_PMV_BYP3_2", - "CLK_PMV_EE2A0_3", - "CLK_PMV_EE2A0_2", - "CLK_PMV_WW4END2_2", - "CLK_PMV_IMUX34_5", - "CLK_PMV_NW2A3_3", - "CLK_PMV_NW4A2_3", - "CLK_PMV_IMUX22_3", - "CLK_PMV_WR1END3_2", - "CLK_PMV_WW2A1_1", - "CLK_PMV_BYP1_0", - "CLK_PMV_SE2A3_6", - "CLK_PMV_IMUX20_0", - "CLK_PMV_BYP7_3", - "CLK_PMV_MONITOR_P_3", - "CLK_PMV_IMUX43_5", - "CLK_PMV_NW4A1_5", - "CLK_PMV_LOGIC_OUTS10_2", - "CLK_PMV_SW2A1_3", - "CLK_PMV_EE4A2_2", - "CLK_PMV_NW2A2_2", - "CLK_PMV_WW4END1_2", - "CLK_PMV_EE2BEG3_1", - "CLK_PMV_SW2A2_5", - "CLK_PMV_SE2A2_6", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_EE4C0_4", - "CLK_PMV_NW2A3_1", - "CLK_PMV_SW4END3_3", - "CLK_PMV_CTRL1_1", - "CLK_PMV_IMUX21_0", - "CLK_PMV_CK_BUFG_CASC29", - "CLK_PMV_LH7_6", - "CLK_PMV_LOGIC_OUTS17_4", - "CLK_PMV_EL1BEG3_5", - "CLK_PMV_LH7_5", - "CLK_PMV_IMUX15_1", - "CLK_PMV_WL1END2_2", - "CLK_PMV_EE4BEG0_5", - "CLK_PMV_WW4C0_1", - "CLK_PMV_NE4BEG0_2", - "CLK_PMV_IMUX3_2", - "CLK_PMV_CTRL1_2", - "CLK_PMV_IMUX24_2", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS14_6", - "CLK_PMV_SW2A1_1", - "CLK_PMV_WW4B2_0", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_IMUX1_4", - "CLK_PMV_R_CK_BUFG_CASC22", - "CLK_PMV_WW4END3_4", - "CLK_PMV_SW4A0_5", - "CLK_PMV_LOGIC_OUTS19_3", - "CLK_PMV_WL1END2_5", - "CLK_PMV_EE4C1_3", - "CLK_PMV_EE2A0_4", - "CLK_PMV_LOGIC_OUTS2_6", - "CLK_PMV_WW2END1_6", - "CLK_PMV_LOGIC_OUTS19_5", - "CLK_PMV_WW4END3_3", - "CLK_PMV_NW4END0_1", - "CLK_PMV_CK_GCLK31", - "CLK_PMV_WW2END2_0", - "CLK_PMV_SW4END1_0", - "CLK_PMV_WW2END1_1", - "CLK_PMV_SW4END3_0", - "CLK_PMV_NE2A2_1", - "CLK_PMV_IMUX3_1", - "CLK_PMV_R_CK_GCLK0", - "CLK_PMV_WW4A3_2", - "CLK_PMV_IMUX44_6", - "CLK_PMV_SW2A3_3", - "CLK_PMV_LOGIC_OUTS9_4", - "CLK_PMV_LOGIC_OUTS21_1", - "CLK_PMV_SW2A1_2", - "CLK_PMV_SW4A0_0", - "CLK_PMV_EE2A2_4", - "CLK_PMV_SE4BEG1_3", - "CLK_PMV_FAN1_5", - "CLK_PMV_SW2A2_6", - "CLK_PMV_IMUX25_1", - "CLK_PMV_IMUX14_5", - "CLK_PMV_NW2A2_0", - "CLK_PMV_IMUX2_0", - "CLK_PMV_FAN0_1", - "CLK_PMV_SE4C2_2", - "CLK_PMV_R_CK_GCLK2", - "CLK_PMV_SE2A0_2", - "CLK_PMV_IMUX9_6", - "CLK_PMV_EL1BEG2_2", - "CLK_PMV_EE2A2_6", - "CLK_PMV_WR1END1_0", - "CLK_PMV_SE2A0_0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_NE4C1_0", - "CLK_PMV_NW4END2_4", - "CLK_PMV_EE2A2_1", - "CLK_PMV_IMUX23_2", - "CLK_PMV_IMUX11_3", - "CLK_PMV_NW4A3_2", - "CLK_PMV_ER1BEG0_4", - "CLK_PMV_LOGIC_OUTS11_3", - "CLK_PMV_IMUX10_6", - "CLK_PMV_LH8_3", - "CLK_PMV_IMUX23_0", - "CLK_PMV_NW2A0_1", - "CLK_PMV_MONITOR_N_5", - "CLK_PMV_LOGIC_OUTS20_3", - "CLK_PMV_LOGIC_OUTS14_3", - "CLK_PMV_IMUX20_1", - "CLK_PMV_FAN4_6", - "CLK_PMV_NE4BEG0_4", - "CLK_PMV_FAN0_2", - "CLK_PMV_R_CK_GCLK25", - "CLK_PMV_LOGIC_OUTS20_4", - "CLK_PMV_EE4B1_0", - "CLK_PMV_WW4A1_3", - "CLK_PMV_EE4C1_6", - "CLK_PMV_NW4A2_2", - "CLK_PMV_LOGIC_OUTS5_2", - "CLK_PMV_EL1BEG1_1", - "CLK_PMV_LOGIC_OUTS7_4", - "CLK_PMV_EL1BEG1_4", - "CLK_PMV_NE4C2_6", - "CLK_PMV_SE4BEG2_3", - "CLK_PMV_LH5_1", - "CLK_PMV_LH4_3", - "CLK_PMV_EE4A3_0", - "CLK_PMV_NE4C0_1", - "CLK_PMV_LOGIC_OUTS3_1", - "CLK_PMV_SE4C0_1", - "CLK_PMV_EE2A1_3", - "CLK_PMV_SE4BEG0_3", - "CLK_PMV_WW4A1_1", - "CLK_PMV_LOGIC_OUTS1_3", - "CLK_PMV_ER1BEG2_1", - "CLK_PMV_EE4A0_5", - "CLK_PMV_LOGIC_OUTS11_6", - "CLK_PMV_LOGIC_OUTS1_5", - "CLK_PMV_IMUX29_3", - "CLK_PMV_WW4A0_1", - "CLK_PMV_BYP7_1", - "CLK_PMV_WW4END2_1", - "CLK_PMV_SE4C2_3", - "CLK_PMV_BYP2_6", - "CLK_PMV_LH10_6", - "CLK_PMV_IMUX9_4", - "CLK_PMV_WW4A1_2", - "CLK_PMV_CLK1_4", - "CLK_PMV_IMUX6_1", - "CLK_PMV_NW4A0_6", - "CLK_PMV_CK_GCLK2", - "CLK_PMV_IMUX3_4", - "CLK_PMV_IMUX7_1", - "CLK_PMV_IMUX39_6", - "CLK_PMV_LOGIC_OUTS13_5", - "CLK_PMV_WR1END2_6", - "CLK_PMV_IMUX35_4", - "CLK_PMV_BYP2_0", "CLK_PMV_SW4END0_0", - "CLK_PMV_CLK1_3", - "CLK_PMV_WW4C3_2", + "CLK_PMV_LOGIC_OUTS19_6", + "CLK_PMV_NW2A0_5", "CLK_PMV_IMUX42_6", - "CLK_PMV_LH1_2", - "CLK_PMV_LH11_3", - "CLK_PMV_EE4C1_1", - "CLK_PMV_FAN5_3", - "CLK_PMV_IMUX3_6", - "CLK_PMV_SW2A0_2", - "CLK_PMV_WW4END0_1", - "CLK_PMV_BYP5_0", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX27_6", - "CLK_PMV_WW4C1_2", - "CLK_PMV_LOGIC_OUTS12_3", - "CLK_PMV_EE2A1_2", - "CLK_PMV_NW4END0_4", - "CLK_PMV_SW4A0_1", - "CLK_PMV_WL1END0_5", - "CLK_PMV_IMUX30_1", - "CLK_PMV_CTRL1_3", - "CLK_PMV_SE2A3_5", - "CLK_PMV_EE4BEG2_0", - "CLK_PMV_EE2A3_2", - "CLK_PMV_LH4_2", - "CLK_PMV_LOGIC_OUTS12_2", - "CLK_PMV_CK_BUFG_CASC8", - "CLK_PMV_NW4END2_5", - "CLK_PMV_IMUX7_2", - "CLK_PMV_IMUX41_0", - "CLK_PMV_WW4END2_4", - "CLK_PMV_WW2END2_5", - "CLK_PMV_IMUX46_2", - "CLK_PMV_NE4BEG0_0", - "CLK_PMV_LOGIC_OUTS8_3", - "CLK_PMV_R_CK_GCLK9", - "CLK_PMV_FAN2_6", - "CLK_PMV_EE4C3_5", - "CLK_PMV_R_CK_BUFG_CASC21", - "CLK_PMV_EE4B1_2", - "CLK_PMV_CK_BUFG_CASC28", - "CLK_PMV_LOGIC_OUTS14_1", - "CLK_PMV_IMUX1_3", - "CLK_PMV_WW2A0_2", - "CLK_PMV_IMUX37_2", - "CLK_PMV_NE2A0_6", - "CLK_PMV_SW4A0_6", - "CLK_PMV_LOGIC_OUTS17_2", - "CLK_PMV_EL1BEG0_1", - "CLK_PMV_EE2BEG0_5", - "CLK_PMV_LH5_5", - "CLK_PMV_NW4A3_5", - "CLK_PMV_SW4END2_1", - "CLK_PMV_FAN5_0", - "CLK_PMV_IMUX36_6", - "CLK_PMV_IMUX17_6", - "CLK_PMV_BYP2_5", - "CLK_PMV_WW4B1_6", - "CLK_PMV_WW4B3_1", - "CLK_PMV_LH4_0", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX22_4", - "CLK_PMV_WW4A2_2", - "CLK_PMV_LOGIC_OUTS3_6", - "CLK_PMV_WL1END3_1", - "CLK_PMV_EL1BEG3_3", - "CLK_PMV_EE2BEG0_2", - "CLK_PMV_WR1END0_2", - "CLK_PMV_WL1END3_6", - "CLK_PMV_LH9_5", - "CLK_PMV_EE4A2_3", - "CLK_PMV_EE4B1_1", - "CLK_PMV_A5", - "CLK_PMV_IMUX35_3", - "CLK_PMV_R_CK_BUFG_CASC24", - "CLK_PMV_LH6_1", - "CLK_PMV_IMUX43_0", - "CLK_PMV_SE4BEG1_0", - "CLK_PMV_IMUX5_6", - "CLK_PMV_LOGIC_OUTS10_1", - "CLK_PMV_NE4BEG2_2", - "CLK_PMV_LOGIC_OUTS4_3", - "CLK_PMV_FAN6_3", - "CLK_PMV_ER1BEG1_0", - "CLK_PMV_NE4C0_3", - "CLK_PMV_CLK1_0", - "CLK_PMV_SE2A0_1", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_WR1END0_6", - "CLK_PMV_WR1END2_1", - "CLK_PMV_NW4END3_4", - "CLK_PMV_NW2A2_5", - "CLK_PMV_LH8_6", - "CLK_PMV_SE4BEG1_2", - "CLK_PMV_NW4A2_4", - "CLK_PMV_NE2A1_0", - "CLK_PMV_BYP0_6", - "CLK_PMV_CTRL0_2", - "CLK_PMV_EE4C2_5", - "CLK_PMV_EE2A3_3", - "CLK_PMV_IMUX18_2", - "CLK_PMV_EE4B0_1", - "CLK_PMV_IMUX22_5", - "CLK_PMV_IMUX12_6", - "CLK_PMV_SW4END3_1", - "CLK_PMV_FAN5_5", - "CLK_PMV_WR1END2_2", - "CLK_PMV_WW2END3_2", - "CLK_PMV_R_CK_BUFG_CASC18", - "CLK_PMV_SE4C3_4", - "CLK_PMV_SW4END2_0", - "CLK_PMV_BYP7_6", - "CLK_PMV_CK_GCLK26", - "CLK_PMV_CTRL1_5", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX46_6", - "CLK_PMV_WL1END2_3", - "CLK_PMV_SW4A1_6", - "CLK_PMV_IMUX37_6", - "CLK_PMV_IMUX18_1", - "CLK_PMV_R_CK_BUFG_CASC6", - "CLK_PMV_LOGIC_OUTS11_5", - "CLK_PMV_LH4_5", - "CLK_PMV_ER1BEG0_2", - "CLK_PMV_NW2A0_0", - "CLK_PMV_WW4B0_5", - "CLK_PMV_R_CK_GCLK15", - "CLK_PMV_NW4END2_6", - "CLK_PMV_EE4A3_2", - "CLK_PMV_IMUX30_3", - "CLK_PMV_IMUX5_2", + "CLK_PMV_SE4C2_1", + "CLK_PMV_IMUX41_6", + "CLK_PMV_SW2A2_6", + "CLK_PMV_FAN1_2", + "CLK_PMV_IMUX13_2", + "CLK_PMV_IMUX34_4", "CLK_PMV_IMUX27_3", - "CLK_PMV_FAN4_0", - "CLK_PMV_SE4BEG2_2", - "CLK_PMV_LOGIC_OUTS9_3", - "CLK_PMV_EE4B2_1", - "CLK_PMV_ER1BEG2_3", - "CLK_PMV_WW4END0_2", - "CLK_PMV_LH6_2", - "CLK_PMV_WW4A0_4", - "CLK_PMV_CTRL0_6", - "CLK_PMV_EE4B2_0", - "CLK_PMV_SW2A3_6", - "CLK_PMV_LOGIC_OUTS19_1", - "CLK_PMV_WW2END1_0", - "CLK_PMV_WW4END1_5", - "CLK_PMV_IMUX10_2", - "CLK_PMV_WW4C1_5", - "CLK_PMV_IMUX14_3", - "CLK_PMV_BYP4_2", - "CLK_PMV_SE4BEG0_0", - "CLK_PMV_BYP0_1", - "CLK_PMV_IMUX12_5", - "CLK_PMV_MONITOR_N_4", - "CLK_PMV_LOGIC_OUTS4_6", - "CLK_PMV_IMUX23_1", - "CLK_PMV_EE4C2_3", - "CLK_PMV_EE4A0_6", - "CLK_PMV_IMUX44_1", - "CLK_PMV_R_CK_BUFG_CASC29", - "CLK_PMV_SE4C3_2", - "CLK_PMV_CTRL0_4", - "CLK_PMV_IMUX4_4", - "CLK_PMV_EE4B2_4", - "CLK_PMV_BYP7_2", - "CLK_PMV_EE2BEG2_5", - "CLK_PMV_LOGIC_OUTS20_2", - "CLK_PMV_IMUX38_1", - "CLK_PMV_SW4A3_6", - "CLK_PMV_IMUX2_4", - "CLK_PMV_WW4C3_3", - "CLK_PMV_ER1BEG3_3", - "CLK_PMV_IMUX34_3", - "CLK_PMV_WW2END0_1", - "CLK_PMV_EE4BEG1_3", - "CLK_PMV_IMUX34_2", - "CLK_PMV_R_CK_BUFG_CASC13", - "CLK_PMV_NW4A1_0", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX27_4", - "CLK_PMV_LOGIC_OUTS5_6", - "CLK_PMV_WW2A3_4", - "CLK_PMV_WW2END1_3", - "CLK_PMV_NE4BEG2_4", - "CLK_PMV_IMUX16_2", - "CLK_PMV_WW2END3_4", - "CLK_PMV_WR1END3_4", - "CLK_PMV_LH12_3", - "CLK_PMV_IMUX11_4", - "CLK_PMV_NW2A1_2", - "CLK_PMV_IMUX4_3", - "CLK_PMV_SW4A1_3", - "CLK_PMV_EE4C0_6", - "CLK_PMV_IMUX0_1", - "CLK_PMV_LOGIC_OUTS21_3", - "CLK_PMV_NE4BEG3_6", - "CLK_PMV_R_CK_BUFG_CASC14", - "CLK_PMV_SE4BEG0_5", - "CLK_PMV_EE4C0_5", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_EL1BEG2_3", - "CLK_PMV_IMUX21_1", - "CLK_PMV_BYP4_3", - "CLK_PMV_NW2A2_4", - "CLK_PMV_IMUX30_5", - "CLK_PMV_NE4BEG2_3", - "CLK_PMV_LH2_2", - "CLK_PMV_LH8_1", - "CLK_PMV_IMUX35_1", - "CLK_PMV_IMUX0_5", - "CLK_PMV_SW4END0_1", - "CLK_PMV_IMUX45_2", - "CLK_PMV_LH11_6", - "CLK_PMV_EE4B0_0", - "CLK_PMV_SW4A3_2", - "CLK_PMV_FAN7_6", - "CLK_PMV_IMUX41_4", - "CLK_PMV_LOGIC_OUTS22_3", - "CLK_PMV_IMUX25_3", - "CLK_PMV_SW4END1_3", - "CLK_PMV_SE4C3_1", - "CLK_PMV_EE4A2_1", - "CLK_PMV_CK_GCLK8", - "CLK_PMV_WL1END0_4", - "CLK_PMV_LOGIC_OUTS13_1", - "CLK_PMV_EE4BEG0_4", - "CLK_PMV_SE4C0_2", - "CLK_PMV_IMUX44_2", - "CLK_PMV_EE2A0_0", - "CLK_PMV_BYP2_4", - "CLK_PMV_IMUX21_4", - "CLK_PMV_R_CK_BUFG_CASC23", - "CLK_PMV_R_CK_BUFG_CASC3", - "CLK_PMV_EE2A2_5", - "CLK_PMV_NE2A0_5", - "CLK_PMV_LH2_0", - "CLK_PMV_IMUX7_5", + "CLK_PMV_IMUX33_2", + "CLK_PMV_WW4A3_2", + "CLK_PMV_FAN2_6", + "CLK_PMV_WW4B0_6", "CLK_PMV_NW4A1_4", - "CLK_PMV_WW4END3_6", - "CLK_PMV_LH10_4", - "CLK_PMV_IMUX41_3", - "CLK_PMV_IMUX33_6", - "CLK_PMV_EE2BEG0_3", - "CLK_PMV_EE4BEG3_3", - "CLK_PMV_SE2A1_6", - "CLK_PMV_IMUX22_6", - "CLK_PMV_NW4A0_1", - "CLK_PMV_CLK0_1", - "CLK_PMV_FAN5_1", - "CLK_PMV_SW4A1_0", - "CLK_PMV_NW2A1_1", - "CLK_PMV_SW2A0_0", - "CLK_PMV_ER1BEG0_6", - "CLK_PMV_IMUX13_3", - "CLK_PMV_WW2A2_3", - "CLK_PMV_IMUX20_5", - "CLK_PMV_LH9_2", - "CLK_PMV_NW4A0_2", - "CLK_PMV_BYP3_4", - "CLK_PMV_NW2A3_2", - "CLK_PMV_ER1BEG3_0", - "CLK_PMV_IMUX31_1", - "CLK_PMV_WW4B3_3", - "CLK_PMV_EL1BEG3_1", - "CLK_PMV_NE4C3_2", - "CLK_PMV_IMUX40_3", - "CLK_PMV_LH7_4", - "CLK_PMV_IMUX32_5", - "CLK_PMV_BYP4_4", - "CLK_PMV_LH7_1", - "CLK_PMV_CK_BUFG_CASC21", - "CLK_PMV_R_CK_BUFG_CASC31", - "CLK_PMV_IMUX29_4", - "CLK_PMV_CK_BUFG_CASC25", - "CLK_PMV_LH8_0", - "CLK_PMV_WR1END1_5", - "CLK_PMV_WL1END0_1", - "CLK_PMV_BYP4_1", - "CLK_PMV_IMUX32_4", - "CLK_PMV_EL1BEG3_4", - "CLK_PMV_IMUX19_1", - "CLK_PMV_BYP4_0", - "CLK_PMV_LOGIC_OUTS12_4", - "CLK_PMV_EE4B1_5", - "CLK_PMV_IMUX6_4", - "CLK_PMV_IMUX26_2", - "CLK_PMV_SE2A2_2", - "CLK_PMV_SE4C1_6", - "CLK_PMV_NW4END1_2", - "CLK_PMV_LOGIC_OUTS4_2", - "CLK_PMV_LOGIC_OUTS23_1", - "CLK_PMV_LH1_6", - "CLK_PMV_LH3_4", - "CLK_PMV_IMUX33_1", - "CLK_PMV_IMUX26_1", - "CLK_PMV_R_CK_BUFG_CASC28", - "CLK_PMV_SE4BEG0_1", - "CLK_PMV_LOGIC_OUTS1_1", - "CLK_PMV_CK_BUFG_CASC22", - "CLK_PMV_R_CK_BUFG_CASC0", - "CLK_PMV_WW4C2_1", - "CLK_PMV_SE2A1_4", - "CLK_PMV_EE2BEG1_4", - "CLK_PMV_MONITOR_N_6", - "CLK_PMV_IMUX21_5", - "CLK_PMV_NW4A3_6", - "CLK_PMV_LOGIC_OUTS14_4", - "CLK_PMV_IMUX12_0", - "CLK_PMV_CK_GCLK21", - "CLK_PMV_IMUX20_2", + "CLK_PMV_MONITOR_N_2", + "CLK_PMV_IMUX3_1", + "CLK_PMV_BYP6_6", + "CLK_PMV_LOGIC_OUTS9_1", + "CLK_PMV_WW2END1_3", + "CLK_PMV_IMUX46_1", + "CLK_PMV_IMUX12_5", + "CLK_PMV_NE4BEG1_0", "CLK_PMV_IMUX36_0", + "CLK_PMV_EE4A3_5", + "CLK_PMV_LOGIC_OUTS16_6", + "CLK_PMV_WW2END1_0", + "CLK_PMV_SW4A2_5", "CLK_PMV_LOGIC_OUTS3_5", - "CLK_PMV_IMUX30_0", - "CLK_PMV_LOGIC_OUTS22_5", - "CLK_PMV_WW4C3_5", - "CLK_PMV_NW2A1_5", - "CLK_PMV_IMUX4_0", - "CLK_PMV_LH9_1", - "CLK_PMV_LH11_1", - "CLK_PMV_NE4BEG2_5", - "CLK_PMV_SE4BEG0_2", - "CLK_PMV_IMUX15_6", - "CLK_PMV_SE4C0_0", - "CLK_PMV_IMUX28_3", - "CLK_PMV_R_CK_GCLK10", - "CLK_PMV_A2", - "CLK_PMV_WW4C1_1", - "CLK_PMV_WW2A1_6", - "CLK_PMV_MONITOR_P_6", - "CLK_PMV_EL1BEG0_2", - "CLK_PMV_CK_BUFG_CASC30", - "CLK_PMV_NE4C2_2", - "CLK_PMV_WL1END3_0", - "CLK_PMV_IMUX5_5", - "CLK_PMV_IMUX29_1", - "CLK_PMV_LOGIC_OUTS2_3", - "CLK_PMV_NW4END1_5", - "CLK_PMV_LOGIC_OUTS7_2", - "CLK_PMV_A1", - "CLK_PMV_WW2END3_3", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LH1_5", - "CLK_PMV_SE4BEG1_5", - "CLK_PMV_EE4BEG0_0", - "CLK_PMV_SE4BEG3_4", - "CLK_PMV_EE4BEG2_5", - "CLK_PMV_WW4END2_3", - "CLK_PMV_LOGIC_OUTS1_4", - "CLK_PMV_IMUX36_3", - "CLK_PMV_ER1BEG2_6", - "CLK_PMV_IMUX6_5", - "CLK_PMV_SW4A2_6", - "CLK_PMV_R_CK_BUFG_CASC2", - "CLK_PMV_WW4END1_0", - "CLK_PMV_WW4END1_1", - "CLK_PMV_CK_GCLK27", - "CLK_PMV_IMUX25_0", - "CLK_PMV_WW4END1_3", - "CLK_PMV_WL1END3_5", - "CLK_PMV_NE2A3_6", - "CLK_PMV_FAN2_2", - "CLK_PMV_LOGIC_OUTS11_4", - "CLK_PMV_LH5_4", - "CLK_PMV_NE4C1_4", - "CLK_PMV_LOGIC_OUTS18_1", - "CLK_PMV_EE4BEG0_6", - "CLK_PMV_WW4END0_4", - "CLK_PMV_EE4C0_1", - "CLK_PMV_IMUX47_1", - "CLK_PMV_IMUX15_2", + "CLK_PMV_EE4C1_5", + "CLK_PMV_WW2END2_3", + "CLK_PMV_LH4_6", + "CLK_PMV_EE4B1_0", + "CLK_PMV_WR1END1_0", + "CLK_PMV_WW4C0_5", + "CLK_PMV_WR1END2_5", "CLK_PMV_LH1_1", - "CLK_PMV_SE2A3_0", - "CLK_PMV_LOGIC_OUTS0_2", - "CLK_PMV_SW4END3_5", - "CLK_PMV_EE2A0_5", - "CLK_PMV_ER1BEG3_6", - "CLK_PMV_CK_BUFG_CASC13", - "CLK_PMV_BYP1_3", - "CLK_PMV_SW4END1_5", - "CLK_PMV_IMUX8_4", - "CLK_PMV_IMUX19_5", - "CLK_PMV_R_CK_GCLK28", - "CLK_PMV_IMUX8_2", + "CLK_PMV_NE2A3_2", + "CLK_PMV_CK_BUFG_CASC17", + "CLK_PMV_CK_BUFG_CASC0", + "CLK_PMV_EL1BEG0_0", + "CLK_PMV_MONITOR_P_3", + "CLK_PMV_EE2BEG0_6", + "CLK_PMV_LH12_2", + "CLK_PMV_SE2A1_3", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_PMV_IMUX19_2", + "CLK_PMV_LOGIC_OUTS0_1", + "CLK_PMV_IMUX36_4", + "CLK_PMV_BYP0_5", + "CLK_PMV_SE4C0_6", + "CLK_PMV_WW2END0_2", + "CLK_PMV_ER1BEG0_4", + "CLK_PMV_SW4END3_1", + "CLK_PMV_LH7_5", + "CLK_PMV_LOGIC_OUTS18_3", + "CLK_PMV_EE2BEG1_2", + "CLK_PMV_IMUX16_1", + "CLK_PMV_IMUX10_6", + "CLK_PMV_MONITOR_P_4", + "CLK_PMV_LH7_1", + "CLK_PMV_EE4C3_2", + "CLK_PMV_NE2A1_0", + "CLK_PMV_R_CK_BUFG_CASC19", + "CLK_PMV_IMUX35_3", + "CLK_PMV_LOGIC_OUTS2_4", + "CLK_PMV_IMUX23_5", + "CLK_PMV_NE2A2_3", + "CLK_PMV_NW4END0_1", + "CLK_PMV_WR1END0_1", + "CLK_PMV_SW2A1_4", + "CLK_PMV_NW4END3_4", + "CLK_PMV_EE4B2_5", + "CLK_PMV_SE4BEG3_1", + "CLK_PMV_WW2END2_4", + "CLK_PMV_R_CK_BUFG_CASC10", + "CLK_PMV_NE2A0_3", + "CLK_PMV_CK_GCLK31", "CLK_PMV_R_CK_GCLK1", - "CLK_PMV_IMUX38_5", - "CLK_PMV_NE4BEG0_6", - "CLK_PMV_LOGIC_OUTS16_3", - "CLK_PMV_NE4C1_2", - "CLK_PMV_SW4END3_4", - "CLK_PMV_NE2A3_0", - "CLK_PMV_WW4C0_4", - "CLK_PMV_EE2A3_1", - "CLK_PMV_IMUX44_0", - "CLK_PMV_WW4END3_5", + "CLK_PMV_R_CK_GCLK14", + "CLK_PMV_IMUX20_1", + "CLK_PMV_EE4BEG0_1", + "CLK_PMV_WL1END1_0", + "CLK_PMV_CK_GCLK5", + "CLK_PMV_IMUX31_0", + "CLK_PMV_NW4A0_1", + "CLK_PMV_IMUX27_2", + "CLK_PMV_LOGIC_OUTS21_3", + "CLK_PMV_NW4A1_2", + "CLK_PMV_R_CK_BUFG_CASC15", + "CLK_PMV_LH10_0", + "CLK_PMV_WW4B1_6", + "CLK_PMV_NW2A1_5", + "CLK_PMV_WR1END2_2", + "CLK_PMV_LOGIC_OUTS11_5", "CLK_PMV_IMUX18_4", - "CLK_PMV_NE4BEG2_0", - "CLK_PMV_BYP6_0", + "CLK_PMV_BYP2_6", + "CLK_PMV_WW4END0_3", + "CLK_PMV_IMUX4_2", + "CLK_PMV_IMUX1_6", + "CLK_PMV_WW4C1_2", + "CLK_PMV_CK_BUFG_CASC26", + "CLK_PMV_SW2A0_3", + "CLK_PMV_EE4A1_4", + "CLK_PMV_BYP4_6", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_PMV_LOGIC_OUTS19_5", + "CLK_PMV_LOGIC_OUTS9_2", + "CLK_PMV_WW2A2_5", + "CLK_PMV_IMUX6_6", + "CLK_PMV_LOGIC_OUTS11_1", + "CLK_PMV_EE4A2_6", + "CLK_PMV_IMUX6_3", + "CLK_PMV_R_CK_GCLK3", + "CLK_PMV_WW2A3_5", + "CLK_PMV_IMUX34_6", + "CLK_PMV_BYP0_6", + "CLK_PMV_IMUX0_5", + "CLK_PMV_NE4C3_0", + "CLK_PMV_FAN7_2", "CLK_PMV_LH8_4", - "CLK_PMV_CLK1_1", - "CLK_PMV_IMUX41_5", - "CLK_PMV_IMUX8_1", - "CLK_PMV_WW4END0_0", + "CLK_PMV_IMUX12_1", + "CLK_PMV_IMUX40_5", + "CLK_PMV_IMUX17_2", + "CLK_PMV_MONITOR_P_0", + "CLK_PMV_SW4END0_5", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_PMV_IMUX29_0", + "CLK_PMV_WR1END1_4", + "CLK_PMV_R_CK_GCLK22", + "CLK_PMV_IMUX46_3", + "CLK_PMV_EE2A2_3", + "CLK_PMV_LOGIC_OUTS1_5", + "CLK_PMV_NW4END2_1", + "CLK_PMV_SW4A2_2", + "CLK_PMV_NW4A1_6", + "CLK_PMV_NE4BEG2_5", + "CLK_PMV_LH2_0", + "CLK_PMV_LOGIC_OUTS18_2", + "CLK_PMV_WW4A2_0", + "CLK_PMV_FAN2_2", + "CLK_PMV_NW2A1_6", + "CLK_PMV_LOGIC_OUTS17_6", + "CLK_PMV_ER1BEG3_3", + "CLK_PMV_WW2A0_0", + "CLK_PMV_IMUX8_3", + "CLK_PMV_R_CK_GCLK5", + "CLK_PMV_NW4END2_0", + "CLK_PMV_LOGIC_OUTS13_5", + "CLK_PMV_SW4A2_3", + "CLK_PMV_ODIV2", + "CLK_PMV_CK_GCLK29", + "CLK_PMV_SW4END3_4", + "CLK_PMV_EE2A0_0", + "CLK_PMV_NW4END1_0", + "CLK_PMV_WW4A1_2", + "CLK_PMV_LH1_3", + "CLK_PMV_NE2A2_1", + "CLK_PMV_LOGIC_OUTS14_2", + "CLK_PMV_IMUX45_3", + "CLK_PMV_IMUX33_5", + "CLK_PMV_WW2A0_3", + "CLK_PMV_IMUX22_5", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_PMV_LH3_2", + "CLK_PMV_IMUX25_5", + "CLK_PMV_WW2END2_0", + "CLK_PMV_LOGIC_OUTS6_6", + "CLK_PMV_WL1END3_6", + "CLK_PMV_EE4B2_4", + "CLK_PMV_EE2A3_3", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_PMV_FAN5_6", + "CLK_PMV_IMUX43_5", + "CLK_PMV_SW4A3_0", + "CLK_PMV_WW4B0_2", + "CLK_PMV_SW2A3_2", + "CLK_PMV_IMUX28_3", + "CLK_PMV_NW4A3_3", + "CLK_PMV_IMUX24_6", + "CLK_PMV_WW2END0_1", + "CLK_PMV_LOGIC_OUTS18_4", + "CLK_PMV_LOGIC_OUTS21_6", + "CLK_PMV_WW2END3_4", + "CLK_PMV_LOGIC_OUTS14_3", + "CLK_PMV_ER1BEG0_1", + "CLK_PMV_LOGIC_OUTS5_6", + "CLK_PMV_LOGIC_OUTS5_2", + "CLK_PMV_EE4A3_1", + "CLK_PMV_WW4C0_2", + "CLK_PMV_EL1BEG2_1", + "CLK_PMV_SW2A3_4", + "CLK_PMV_IMUX18_5", + "CLK_PMV_NE2A0_4", + "CLK_PMV_NE2A3_3", + "CLK_PMV_NW4A1_3", + "CLK_PMV_IMUX43_3", "CLK_PMV_CK_BUFG_CASC1", - "CLK_PMV_WR1END0_4", - "CLK_PMV_CK_GCLK30", + "CLK_PMV_IMUX7_4", + "CLK_PMV_SE4C0_4", + "CLK_PMV_WW4A3_1", "CLK_PMV_R_CK_GCLK27", + "CLK_PMV_WW2A1_1", + "CLK_PMV_IMUX33_3", + "CLK_PMV_BYP1_6", + "CLK_PMV_NE4C2_1", + "CLK_PMV_SW4END3_0", + "CLK_PMV_NE4C3_5", + "CLK_PMV_SE2A3_6", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_PMV_EE4B3_4", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_PMV_SE2A0_1", + "CLK_PMV_R_CK_GCLK23", + "CLK_PMV_FAN0_6", + "CLK_PMV_IMUX0_2", + "CLK_PMV_IMUX46_2", + "CLK_PMV_SE2A2_3", + "CLK_PMV_IMUX9_0", + "CLK_PMV_CTRL0_5", + "CLK_PMV_R_CK_BUFG_CASC24", + "CLK_PMV_SW4END1_5", + "CLK_PMV_WW2END1_4", + "CLK_PMV_NW4A0_6", + "CLK_PMV_LOGIC_OUTS3_2", + "CLK_PMV_WW4C3_2", + "CLK_PMV_LOGIC_OUTS13_1", + "CLK_PMV_SW2A2_1", + "CLK_PMV_EE4BEG3_2", + "CLK_PMV_EE2BEG1_1", + "CLK_PMV_NE4C0_1", + "CLK_PMV_WW2END3_2", + "CLK_PMV_LH11_2", + "CLK_PMV_IMUX39_5", + "CLK_PMV_EE4B0_0", + "CLK_PMV_CTRL1_6", + "CLK_PMV_WW4B2_3", + "CLK_PMV_LOGIC_OUTS4_2", + "CLK_PMV_IMUX27_1", + "CLK_PMV_NE4C2_3", + "CLK_PMV_IMUX10_0", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_PMV_NE4C1_5", + "CLK_PMV_IMUX33_4", + "CLK_PMV_LOGIC_OUTS20_5", + "CLK_PMV_EE4C1_1", + "CLK_PMV_EE4A3_6", + "CLK_PMV_IMUX29_2", + "CLK_PMV_SE4C1_1", + "CLK_PMV_IMUX10_4", + "CLK_PMV_R_CK_BUFG_CASC27", + "CLK_PMV_CK_GCLK26", + "CLK_PMV_R_CK_BUFG_CASC20", + "CLK_PMV_IMUX32_2", + "CLK_PMV_EE4BEG0_0", + "CLK_PMV_SE2A3_4", + "CLK_PMV_FAN6_0", + "CLK_PMV_WW2A2_2", + "CLK_PMV_LOGIC_OUTS19_4", + "CLK_PMV_WR1END1_3", + "CLK_PMV_LOGIC_OUTS8_4", + "CLK_PMV_LH4_5", + "CLK_PMV_LOGIC_OUTS22_5", + "CLK_PMV_LH10_2", + "CLK_PMV_SE2A3_1", + "CLK_PMV_WR1END2_6", + "CLK_PMV_NE2A1_2", + "CLK_PMV_IMUX35_0", + "CLK_PMV_LOGIC_OUTS15_1", + "CLK_PMV_FAN0_2", + "CLK_PMV_IMUX16_0", + "CLK_PMV_CLK1_3", + "CLK_PMV_IMUX45_2", + "CLK_PMV_FAN3_6", + "CLK_PMV_LOGIC_OUTS23_3", + "CLK_PMV_IMUX31_5", + "CLK_PMV_WL1END2_3", + "CLK_PMV_IMUX44_1", + "CLK_PMV_EE4B2_3", + "CLK_PMV_R_CK_BUFG_CASC3", + "CLK_PMV_LOGIC_OUTS14_6", + "CLK_PMV_CLK1_1", + "CLK_PMV_IMUX37_4", + "CLK_PMV_EE4A0_6", + "CLK_PMV_IMUX36_6", + "CLK_PMV_EE4B1_4", + "CLK_PMV_SE4C3_6", + "CLK_PMV_NW4A2_2", + "CLK_PMV_EE2BEG3_5", + "CLK_PMV_LOGIC_OUTS3_6", + "CLK_PMV_WW2A3_4", + "CLK_PMV_WW2A2_4", + "CLK_PMV_SE2A0_0", + "CLK_PMV_EE4BEG3_6", + "CLK_PMV_NE4C1_0", + "CLK_PMV_IMUX28_6", + "CLK_PMV_WW4END1_3", + "CLK_PMV_WW2END2_6", + "CLK_PMV_FAN1_4", + "CLK_PMV_LOGIC_OUTS6_3", + "CLK_PMV_ER1BEG1_0", + "CLK_PMV_WL1END1_1", + "CLK_PMV_WW2A2_0", + "CLK_PMV_LOGIC_OUTS4_1", + "CLK_PMV_LH5_3", + "CLK_PMV_IMUX35_4", + "CLK_PMV_WR1END0_5", + "CLK_PMV_IMUX21_3", + "CLK_PMV_IMUX40_4", + "CLK_PMV_CK_BUFG_CASC6", + "CLK_PMV_LH6_5", + "CLK_PMV_EE2BEG3_6", + "CLK_PMV_EE4BEG1_6", + "CLK_PMV_WW4B3_6", + "CLK_PMV_IMUX46_5", + "CLK_PMV_CK_GCLK20", + "CLK_PMV_NE4C3_3", + "CLK_PMV_EE4C1_0", + "CLK_PMV_LH3_0", + "CLK_PMV_WL1END2_2", + "CLK_PMV_WL1END0_0", + "CLK_PMV_EE4BEG2_0", + "CLK_PMV_EE2BEG1_4", + "CLK_PMV_LH7_6", + "CLK_PMV_LH3_5", + "CLK_PMV_BYP6_3", + "CLK_PMV_ER1BEG0_3", + "CLK_PMV_R_CK_GCLK13", + "CLK_PMV_IMUX35_5", + "CLK_PMV_IMUX7_6", + "CLK_PMV_EE4C3_5", + "CLK_PMV_LH6_6", + "CLK_PMV_ER1BEG3_5", + "CLK_PMV_LOGIC_OUTS1_4", + "CLK_PMV_SE4BEG2_6", + "CLK_PMV_SW4A1_2", + "CLK_PMV_IMUX18_0", + "CLK_PMV_NW4END3_1", + "CLK_PMV_NE4BEG3_0", + "CLK_PMV_NE4C3_2", + "CLK_PMV_NW4A3_2", + "CLK_PMV_CK_GCLK16", + "CLK_PMV_EE2A0_3", + "CLK_PMV_WW4END2_5", + "CLK_PMV_LOGIC_OUTS12_3", + "CLK_PMV_ER1BEG3_1", + "CLK_PMV_NW2A3_6", + "CLK_PMV_R_CK_BUFG_CASC14", + "CLK_PMV_IMUX2_1", + "CLK_PMV_LH5_1", + "CLK_PMV_LOGIC_OUTS2_3", + "CLK_PMV_WW4END2_1", + "CLK_PMV_IMUX1_3", + "CLK_PMV_EE4BEG0_2", + "CLK_PMV_LOGIC_OUTS19_2", + "CLK_PMV_IMUX6_4", + "CLK_PMV_IMUX15_4", + "CLK_PMV_CK_BUFG_CASC22", + "CLK_PMV_BYP2_3", + "CLK_PMV_SE2A2_6", + "CLK_PMV_WW4C0_0", + "CLK_PMV_WW4B1_4", + "CLK_PMV_SE2A1_4", + "CLK_PMV_WW4B2_1", + "CLK_PMV_EE4B3_2", + "CLK_PMV_IMUX31_6", + "CLK_PMV_WW2A0_5", + "CLK_PMV_NE4C2_4", + "CLK_PMV_IMUX20_3", + "CLK_PMV_IMUX20_5", + "CLK_PMV_EE4A1_2", + "CLK_PMV_CK_BUFG_CASC21", + "CLK_PMV_IMUX34_5", + "CLK_PMV_WW2END1_6", + "CLK_PMV_SE4BEG0_0", + "CLK_PMV_CK_GCLK3", + "CLK_PMV_WW2A1_2", + "CLK_PMV_LH6_1", + "CLK_PMV_IMUX32_4", + "CLK_PMV_NW4END3_5", + "CLK_PMV_CLK0_0", + "CLK_PMV_LOGIC_OUTS21_5", + "CLK_PMV_IMUX39_6", + "CLK_PMV_IMUX22_6", + "CLK_PMV_WW4A1_1", + "CLK_PMV_IMUX26_2", + "CLK_PMV_BYP7_4", + "CLK_PMV_WL1END3_0", + "CLK_PMV_NW4A2_6", + "CLK_PMV_BYP5_2", + "CLK_PMV_LOGIC_OUTS20_2", + "CLK_PMV_EE4BEG0_6", + "CLK_PMV_LOGIC_OUTS5_1", + "CLK_PMV_WW4B0_1", + "CLK_PMV_LOGIC_OUTS5_5", + "CLK_PMV_IMUX47_6", + "CLK_PMV_LOGIC_OUTS15_6", + "CLK_PMV_IMUX6_1", + "CLK_PMV_EE4A2_4", + "CLK_PMV_NE4BEG0_0", + "CLK_PMV_EE4A1_1", + "CLK_PMV_IMUX47_4", + "CLK_PMV_EE4BEG2_6", + "CLK_PMV_IMUX39_3", + "CLK_PMV_LOGIC_OUTS9_6", + "CLK_PMV_ER1BEG2_5", + "CLK_PMV_IMUX43_6", + "CLK_PMV_EL1BEG0_1", + "CLK_PMV_IMUX14_5", + "CLK_PMV_LH11_6", + "CLK_PMV_CK_GCLK7", + "CLK_PMV_WL1END0_3", + "CLK_PMV_SW4A0_5", + "CLK_PMV_FAN1_1", + "CLK_PMV_NW4END0_2", + "CLK_PMV_R_CK_BUFG_CASC4", + "CLK_PMV_LOGIC_OUTS4_3", + "CLK_PMV_SW4A0_4", + "CLK_PMV_CK_BUFG_CASC10", + "CLK_PMV_BYP3_0", + "CLK_PMV_NW2A1_0", + "CLK_PMV_R_CK_BUFG_CASC1", + "CLK_PMV_IMUX36_5", + "CLK_PMV_IMUX37_2", + "CLK_PMV_NW4END1_6", + "CLK_PMV_LOGIC_OUTS20_3", + "CLK_PMV_CK_GCLK27", + "CLK_PMV_WW4C3_3", + "CLK_PMV_EE2BEG0_5", + "CLK_PMV_IMUX46_0", + "CLK_PMV_LOGIC_OUTS16_1", + "CLK_PMV_NE4BEG2_6", + "CLK_PMV_LH12_0", + "CLK_PMV_EE4B0_5", + "CLK_PMV_BYP0_0", + "CLK_PMV_SE2A0_3", + "CLK_PMV_IMUX37_5", + "CLK_PMV_NE4C0_6", + "CLK_PMV_IMUX30_5", + "CLK_PMV_EE4BEG0_5", + "CLK_PMV_IMUX21_6", + "CLK_PMV_EE4BEG0_3", + "CLK_PMV_EL1BEG1_5", + "CLK_PMV_LOGIC_OUTS1_1", + "CLK_PMV_SE4BEG1_2", + "CLK_PMV_BYP3_2", + "CLK_PMV_IMUX0_3", + "CLK_PMV_LOGIC_OUTS11_4", + "CLK_PMV_IMUX5_0", + "CLK_PMV_EE2A1_0", + "CLK_PMV_LOGIC_OUTS12_1", + "CLK_PMV_LH8_2", + "CLK_PMV_SW4A1_4", + "CLK_PMV_SW2A2_0", + "CLK_PMV_ER1BEG2_1", + "CLK_PMV_IMUX25_0", + "CLK_PMV_LOGIC_OUTS18_6", + "CLK_PMV_LOGIC_OUTS2_1", + "CLK_PMV_WW4C2_4", + "CLK_PMV_IMUX7_5", + "CLK_PMV_LOGIC_OUTS18_5", + "CLK_PMV_LOGIC_OUTS15_2", + "CLK_PMV_WW2A1_3", + "CLK_PMV_WL1END2_4", + "CLK_PMV_IMUX5_4", + "CLK_PMV_CTRL0_0", + "CLK_PMV_BYP1_5", + "CLK_PMV_IMUX40_2", + "CLK_PMV_WL1END2_1", + "CLK_PMV_CTRL0_2", + "CLK_PMV_WW2A0_1", + "CLK_PMV_FAN5_4", + "CLK_PMV_CTRL0_3", + "CLK_PMV_EE4B3_0", + "CLK_PMV_NE4C1_2", + "CLK_PMV_ER1BEG1_2", + "CLK_PMV_EE4C0_2", + "CLK_PMV_WL1END0_2", + "CLK_PMV_LH6_4", + "CLK_PMV_LOGIC_OUTS5_4", + "CLK_PMV_R_CK_BUFG_CASC2", + "CLK_PMV_EE4B0_2", + "CLK_PMV_WR1END3_5", + "CLK_PMV_A2", + "CLK_PMV_EE2A2_2", + "CLK_PMV_WL1END3_1", + "CLK_PMV_LOGIC_OUTS0_6", + "CLK_PMV_LOGIC_OUTS7_2", + "CLK_PMV_LOGIC_OUTS4_4", + "CLK_PMV_SE2A1_2", + "CLK_PMV_IMUX22_0", + "CLK_PMV_LH11_0", + "CLK_PMV_SE4C0_5", + "CLK_PMV_LOGIC_OUTS20_1", + "CLK_PMV_EE2BEG1_0", + "CLK_PMV_SE4BEG3_0", + "CLK_PMV_BYP3_5", + "CLK_PMV_R_CK_BUFG_CASC29", + "CLK_PMV_NW4A3_0", + "CLK_PMV_WW4B0_0", + "CLK_PMV_BYP3_1", + "CLK_PMV_CK_BUFG_CASC7", + "CLK_PMV_IMUX7_0", + "CLK_PMV_R_CK_GCLK17", + "CLK_PMV_EL1BEG3_1", + "CLK_PMV_IMUX19_6", + "CLK_PMV_EL1BEG3_0", + "CLK_PMV_R_CK_BUFG_CASC31", + "CLK_PMV_LOGIC_OUTS21_2", + "CLK_PMV_SE2A2_1", + "CLK_PMV_LH10_1", + "CLK_PMV_SE4BEG0_6", + "CLK_PMV_IMUX11_3", + "CLK_PMV_WW4A2_1", + "CLK_PMV_EE4BEG0_4", + "CLK_PMV_IMUX37_1", + "CLK_PMV_IMUX38_1", + "CLK_PMV_BYP1_0", + "CLK_PMV_LH3_1", + "CLK_PMV_NE2A0_6", + "CLK_PMV_FAN6_1", + "CLK_PMV_FAN5_5", + "CLK_PMV_EE4A2_3", + "CLK_PMV_CK_BUFG_CASC18", + "CLK_PMV_IMUX42_0", + "CLK_PMV_EE2A0_2", + "CLK_PMV_SW4END0_3", + "CLK_PMV_NE2A1_5", + "CLK_PMV_WL1END2_5", + "CLK_PMV_LOGIC_OUTS23_2", + "CLK_PMV_SW2A2_3", + "CLK_PMV_IMUX6_2", + "CLK_PMV_SW4END3_6", + "CLK_PMV_IMUX19_1", + "CLK_PMV_WW4END2_6", + "CLK_PMV_NE4BEG1_6", + "CLK_PMV_IMUX10_1", + "CLK_PMV_IMUX24_3", + "CLK_PMV_SW4A0_2", + "CLK_PMV_IMUX7_2", + "CLK_PMV_IMUX21_5", + "CLK_PMV_WW2A2_3", + "CLK_PMV_NW2A3_4", + "CLK_PMV_NW2A2_3", + "CLK_PMV_BYP2_1", + "CLK_PMV_IMUX16_3", + "CLK_PMV_NW4END2_5", + "CLK_PMV_LH9_2", + "CLK_PMV_R_CK_GCLK25", + "CLK_PMV_R_CK_GCLK28", + "CLK_PMV_LOGIC_OUTS22_1", + "CLK_PMV_WW4B0_4", + "CLK_PMV_R_CK_GCLK19", + "CLK_PMV_LH8_5", + "CLK_PMV_EE4A3_2", + "CLK_PMV_CK_BUFG_CASC27", + "CLK_PMV_CK_BUFG_CASC5", + "CLK_PMV_BYP0_3", + "CLK_PMV_IMUX9_5", + "CLK_PMV_CTRL1_2", + "CLK_PMV_IMUX0_0", + "CLK_PMV_IMUX11_0", + "CLK_PMV_IMUX13_6", + "CLK_PMV_LH5_2", + "CLK_PMV_NE2A2_5", + "CLK_PMV_EE2A2_6", + "CLK_PMV_SE2A2_5", + "CLK_PMV_R_CK_BUFG_CASC23", + "CLK_PMV_MONITOR_N_0", + "CLK_PMV_LH11_5", + "CLK_PMV_SE4BEG3_3", + "CLK_PMV_R_CK_GCLK6", + "CLK_PMV_FAN7_4", + "CLK_PMV_IMUX41_3", + "CLK_PMV_IMUX12_2", + "CLK_PMV_R_CK_BUFG_CASC16", + "CLK_PMV_NE4C2_0", + "CLK_PMV_EE2BEG3_2", + "CLK_PMV_BYP7_2", + "CLK_PMV_WR1END0_2", + "CLK_PMV_IMUX42_1", + "CLK_PMV_LH6_3", + "CLK_PMV_SW4A3_3", + "CLK_PMV_CK_GCLK1", + "CLK_PMV_ER1BEG1_3", + "CLK_PMV_BYP5_6", + "CLK_PMV_WW2END1_5", + "CLK_PMV_NW4A2_5", + "CLK_PMV_MONITOR_P_5", + "CLK_PMV_R_CK_BUFG_CASC17", + "CLK_PMV_IMUX47_3", + "CLK_PMV_NE4BEG0_6", + "CLK_PMV_SE4BEG0_4", + "CLK_PMV_NE4BEG1_3", + "CLK_PMV_NW4END2_4", + "CLK_PMV_IMUX28_5", + "CLK_PMV_CLK1_4", + "CLK_PMV_NE2A1_4", + "CLK_PMV_FAN4_4", + "CLK_PMV_WR1END2_3", + "CLK_PMV_EL1BEG1_2", + "CLK_PMV_SW4END2_6", + "CLK_PMV_SE4C3_3", + "CLK_PMV_FAN0_4", + "CLK_PMV_EE4A1_3", + "CLK_PMV_IMUX4_5", + "CLK_PMV_EL1BEG3_3", + "CLK_PMV_SE4BEG0_5", + "CLK_PMV_IMUX1_2", + "CLK_PMV_EE4C2_5", + "CLK_PMV_FAN1_5", + "CLK_PMV_FAN7_0", + "CLK_PMV_CTRL1_1", + "CLK_PMV_IMUX43_2", + "CLK_PMV_LOGIC_OUTS0_2", + "CLK_PMV_BYP5_4", + "CLK_PMV_IMUX3_3", + "CLK_PMV_LOGIC_OUTS12_2", + "CLK_PMV_R_CK_GCLK2", + "CLK_PMV_IMUX13_5", + "CLK_PMV_MONITOR_N_4", + "CLK_PMV_NE4BEG0_2", + "CLK_PMV_WW4END3_2", + "CLK_PMV_IMUX3_5", + "CLK_PMV_IMUX24_0", + "CLK_PMV_LH4_0", + "CLK_PMV_NW2A2_5", + "CLK_PMV_NW4A2_3", + "CLK_PMV_IMUX36_2", + "CLK_PMV_CLK1_0", + "CLK_PMV_IMUX32_0", + "CLK_PMV_WR1END0_0", + "CLK_PMV_WW4A2_3", + "CLK_PMV_IMUX45_4", + "CLK_PMV_CK_BUFG_CASC29", + "CLK_PMV_IMUX2_5", + "CLK_PMV_WW4END3_1", + "CLK_PMV_EE2A3_1", + "CLK_PMV_WW2A3_2", + "CLK_PMV_WW4END0_6", + "CLK_PMV_LOGIC_OUTS3_4", + "CLK_PMV_NE4C1_1", + "CLK_PMV_EE4B3_6", + "CLK_PMV_NE4C3_1", + "CLK_PMV_WW4C1_3", + "CLK_PMV_SW2A3_5", + "CLK_PMV_NW2A2_6", + "CLK_PMV_LH3_3", + "CLK_PMV_SE4BEG3_6", + "CLK_PMV_BYP2_0", + "CLK_PMV_SW2A1_0", + "CLK_PMV_WW4C3_4", + "CLK_PMV_LOGIC_OUTS16_5", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_PMV_IMUX14_6", + "CLK_PMV_EE4C2_1", + "CLK_PMV_WW4B1_3", + "CLK_PMV_LH5_4", + "CLK_PMV_IMUX11_5", + "CLK_PMV_IMUX44_4", + "CLK_PMV_EE4C0_1", + "CLK_PMV_ER1BEG1_5", + "CLK_PMV_WW4END2_3", + "CLK_PMV_EE2A1_1", + "CLK_PMV_CK_GCLK24", + "CLK_PMV_IMUX17_4", + "CLK_PMV_SW4A1_3", + "CLK_PMV_WL1END1_2", + "CLK_PMV_R_CK_BUFG_CASC0", + "CLK_PMV_SE4C1_2", + "CLK_PMV_LH9_4", + "CLK_PMV_EE4B3_1", + "CLK_PMV_WR1END3_4", + "CLK_PMV_CK_GCLK15", + "CLK_PMV_WR1END0_3", + "CLK_PMV_NW4END2_2", + "CLK_PMV_NW4END1_1", + "CLK_PMV_EE2BEG0_0", + "CLK_PMV_WW4A2_5", + "CLK_PMV_SW4END2_4", + "CLK_PMV_ER1BEG2_3", + "CLK_PMV_LOGIC_OUTS23_1", + "CLK_PMV_WW4C1_4", + "CLK_PMV_SE4C2_5", + "CLK_PMV_NE2A2_0", + "CLK_PMV_IMUX20_2", + "CLK_PMV_EL1BEG1_3", + "CLK_PMV_IMUX40_6", + "CLK_PMV_EE2A3_0", + "CLK_PMV_ER1BEG1_6", + "CLK_PMV_IMUX23_0", + "CLK_PMV_CLK0_4", + "CLK_PMV_IMUX5_6", + "CLK_PMV_SW4A1_0", + "CLK_PMV_FAN4_3", + "CLK_PMV_NW4A3_5", + "CLK_PMV_WR1END2_1", + "CLK_PMV_IMUX5_2", + "CLK_PMV_IMUX22_2", + "CLK_PMV_IMUX12_0", + "CLK_PMV_IMUX2_2", + "CLK_PMV_IMUX38_5", + "CLK_PMV_EN", + "CLK_PMV_IMUX19_3", + "CLK_PMV_EE4BEG2_2", + "CLK_PMV_SW4END0_2", + "CLK_PMV_EE2BEG3_1", + "CLK_PMV_FAN3_5", + "CLK_PMV_NW2A1_3", + "CLK_PMV_IMUX27_4", + "CLK_PMV_WL1END0_4", + "CLK_PMV_CK_GCLK30", + "CLK_PMV_NW4A3_6", + "CLK_PMV_LH8_1", + "CLK_PMV_LH2_4", + "CLK_PMV_IMUX3_0", + "CLK_PMV_FAN5_1", + "CLK_PMV_NE4C3_6", + "CLK_PMV_NE2A3_0", + "CLK_PMV_NW2A0_4", + "CLK_PMV_IMUX21_0", + "CLK_PMV_SW4END1_3", + "CLK_PMV_BYP4_4", + "CLK_PMV_NW4A2_0", + "CLK_PMV_WW4A3_6", + "CLK_PMV_NW4A0_5", + "CLK_PMV_SW4END2_3", + "CLK_PMV_BYP7_1", + "CLK_PMV_WW2END0_3", + "CLK_PMV_WL1END3_5", + "CLK_PMV_IMUX33_0", + "CLK_PMV_NW4END3_3", + "CLK_PMV_WW2A3_1", + "CLK_PMV_EE4A3_3", + "CLK_PMV_CK_GCLK28", + "CLK_PMV_IMUX41_1", + "CLK_PMV_IMUX44_3", + "CLK_PMV_LH7_0", + "CLK_PMV_NW2A3_2", + "CLK_PMV_ER1BEG0_6", + "CLK_PMV_BYP0_1", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_PMV_LOGIC_OUTS19_3", + "CLK_PMV_R_CK_GCLK15", + "CLK_PMV_IMUX42_5", + "CLK_PMV_WW4B2_4", + "CLK_PMV_EL1BEG3_2", + "CLK_PMV_EL1BEG1_0", + "CLK_PMV_CTRL1_0", + "CLK_PMV_LH7_2", + "CLK_PMV_LOGIC_OUTS10_1", + "CLK_PMV_SE4BEG1_3", + "CLK_PMV_WW4A0_6", + "CLK_PMV_R_CK_GCLK10", + "CLK_PMV_WW4A0_1", + "CLK_PMV_R_CK_BUFG_CASC5", + "CLK_PMV_LOGIC_OUTS6_4", + "CLK_PMV_SW2A1_1", + "CLK_PMV_LOGIC_OUTS11_3", + "CLK_PMV_R_CK_BUFG_CASC9", + "CLK_PMV_EE2BEG1_3", + "CLK_PMV_EE4C2_2", + "CLK_PMV_LOGIC_OUTS7_5", + "CLK_PMV_IMUX10_5", + "CLK_PMV_WR1END2_4", + "CLK_PMV_WW2A1_0", + "CLK_PMV_WW4END0_1", + "CLK_PMV_SE4C0_1", + "CLK_PMV_LOGIC_OUTS8_3", + "CLK_PMV_ER1BEG3_2", + "CLK_PMV_SW4END2_0", + "CLK_PMV_EE4A2_2", + "CLK_PMV_MONITOR_N_6", + "CLK_PMV_LH1_0", + "CLK_PMV_SE4C1_4", + "CLK_PMV_WW4END3_6", + "CLK_PMV_FAN6_3", + "CLK_PMV_EL1BEG0_6", + "CLK_PMV_LH1_2", + "CLK_PMV_IMUX39_0", + "CLK_PMV_IMUX2_6", + "CLK_PMV_WW4END1_6", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_PMV_IMUX23_2", + "CLK_PMV_R_CK_GCLK4", + "CLK_PMV_BYP3_3", + "CLK_PMV_WR1END1_2", + "CLK_PMV_CK_BUFG_CASC16", + "CLK_PMV_NE4C1_3", + "CLK_PMV_WR1END1_1", + "CLK_PMV_WW4C1_0", + "CLK_PMV_R_CK_BUFG_CASC18", + "CLK_PMV_SW4A1_6", + "CLK_PMV_LOGIC_OUTS23_5", + "CLK_PMV_IMUX45_1", + "CLK_PMV_IMUX18_2", + "CLK_PMV_WW4C2_0", + "CLK_PMV_SE2A0_5", + "CLK_PMV_LH9_0", + "CLK_PMV_IMUX15_2", + "CLK_PMV_WW2A0_4", + "CLK_PMV_IMUX35_2", + "CLK_PMV_EE4B2_1", + "CLK_PMV_ER1BEG2_6", + "CLK_PMV_SW2A3_3", + "CLK_PMV_NW2A2_0", + "CLK_PMV_IMUX27_5", + "CLK_PMV_WL1END0_6", + "CLK_PMV_IMUX7_3", + "CLK_PMV_SW4A2_4", + "CLK_PMV_WW2A1_4", + "CLK_PMV_LH8_6", + "CLK_PMV_EE4C0_4", + "CLK_PMV_SE2A3_0", + "CLK_PMV_WR1END0_6", + "CLK_PMV_FAN5_0", + "CLK_PMV_IMUX30_2", + "CLK_PMV_WR1END2_0", + "CLK_PMV_IMUX38_2", + "CLK_PMV_WW2A1_6", + "CLK_PMV_A3", + "CLK_PMV_NE4C3_4", + "CLK_PMV_ER1BEG3_0", + "CLK_PMV_ER1BEG1_1", + "CLK_PMV_FAN5_2", + "CLK_PMV_LH1_4", + "CLK_PMV_LH4_1", + "CLK_PMV_IMUX19_5", + "CLK_PMV_EE4BEG3_3", + "CLK_PMV_SE2A2_4", + "CLK_PMV_WW4C0_3", + "CLK_PMV_NE4C2_6", + "CLK_PMV_SW4END0_6", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_PMV_A0", + "CLK_PMV_ER1BEG2_2", + "CLK_PMV_IMUX44_0", + "CLK_PMV_WR1END1_5", + "CLK_PMV_BYP5_0", + "CLK_PMV_EE4C0_6", + "CLK_PMV_LH5_5", + "CLK_PMV_NW2A0_3", + "CLK_PMV_NE4BEG0_1", + "CLK_PMV_WW4A1_6", + "CLK_PMV_IMUX23_1", + "CLK_PMV_SW4END3_3", + "CLK_PMV_IMUX13_4", + "CLK_PMV_WW4B1_1", + "CLK_PMV_LOGIC_OUTS13_4", + "CLK_PMV_LOGIC_OUTS3_1", + "CLK_PMV_LH12_4", + "CLK_PMV_WW4B3_0", + "CLK_PMV_SW4A0_3", + "CLK_PMV_IMUX5_1", + "CLK_PMV_SW2A0_2", + "CLK_PMV_WW2A2_1", + "CLK_PMV_IMUX31_1", + "CLK_PMV_WW4END3_0", + "CLK_PMV_IMUX18_6", + "CLK_PMV_NE2A2_4", + "CLK_PMV_SE4BEG1_5", + "CLK_PMV_EE2BEG1_5", + "CLK_PMV_R_CK_GCLK20", + "CLK_PMV_WW4A2_2", + "CLK_PMV_BYP1_3", + "CLK_PMV_NE2A3_6", + "CLK_PMV_IMUX38_4", + "CLK_PMV_SW4END1_4", + "CLK_PMV_EE2A1_4", + "CLK_PMV_WR1END3_3", + "CLK_PMV_LH2_3", + "CLK_PMV_SW4END3_5", + "CLK_PMV_LH11_1", + "CLK_PMV_BYP3_4", + "CLK_PMV_FAN0_0", + "CLK_PMV_NE4C0_5", + "CLK_PMV_IMUX32_1", + "CLK_PMV_A4", + "CLK_PMV_CLK0_1", + "CLK_PMV_WL1END2_0", + "CLK_PMV_IMUX6_5", + "CLK_PMV_EE4BEG1_0", + "CLK_PMV_IMUX45_6", + "CLK_PMV_CLK0_5", + "CLK_PMV_EE4A3_0", + "CLK_PMV_LOGIC_OUTS21_4", + "CLK_PMV_CK_GCLK25", + "CLK_PMV_SE4C3_5", + "CLK_PMV_IMUX13_0", + "CLK_PMV_IMUX29_6", + "CLK_PMV_IMUX20_0", + "CLK_PMV_IMUX22_4", + "CLK_PMV_NW4END0_0", + "CLK_PMV_BYP4_2", + "CLK_PMV_WW4C3_5", + "CLK_PMV_NE4BEG2_4", + "CLK_PMV_CK_BUFG_CASC9", + "CLK_PMV_NE2A3_5", + "CLK_PMV_WR1END0_4", + "CLK_PMV_BYP7_5", + "CLK_PMV_SE2A0_6", + "CLK_PMV_LOGIC_OUTS4_6", + "CLK_PMV_EL1BEG0_4", + "CLK_PMV_EL1BEG2_0", + "CLK_PMV_IMUX17_3", + "CLK_PMV_IMUX9_2", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_BYP4_3", + "CLK_PMV_NE2A3_4", + "CLK_PMV_SW2A0_5", + "CLK_PMV_IMUX28_0", + "CLK_PMV_EL1BEG2_5", + "CLK_PMV_WW4END3_5", + "CLK_PMV_CK_GCLK2", + "CLK_PMV_NE4BEG2_3", + "CLK_PMV_CK_BUFG_CASC15", + "CLK_PMV_R_CK_GCLK9", + "CLK_PMV_CK_GCLK18", + "CLK_PMV_IMUX1_4", + "CLK_PMV_IMUX34_2", + "CLK_PMV_LOGIC_OUTS7_3", + "CLK_PMV_R_CK_GCLK11", + "CLK_PMV_FAN1_6", + "CLK_PMV_IMUX9_1", + "CLK_PMV_LOGIC_OUTS22_3", + "CLK_PMV_NE2A3_1", + "CLK_PMV_EE4B0_3", + "CLK_PMV_CK_BUFG_CASC13", + "CLK_PMV_BYP4_1", + "CLK_PMV_FAN6_5", + "CLK_PMV_SW2A0_0", + "CLK_PMV_LOGIC_OUTS8_5", + "CLK_PMV_EE4B2_0", + "CLK_PMV_SW4A1_1", + "CLK_PMV_FAN3_0", + "CLK_PMV_WW2A0_2", + "CLK_PMV_EE4BEG1_4", + "CLK_PMV_LOGIC_OUTS5_3", + "CLK_PMV_WW4B3_2", + "CLK_PMV_EL1BEG0_3", + "CLK_PMV_SE4BEG0_1", + "CLK_PMV_CK_BUFG_CASC20", + "CLK_PMV_EE4C1_2", + "CLK_PMV_EE2BEG2_4", + "CLK_PMV_WW4C2_2", + "CLK_PMV_WL1END2_6", + "CLK_PMV_LH8_3", + "CLK_PMV_EE4C3_1", + "CLK_PMV_SE4C1_6", + "CLK_PMV_EE2A0_6", + "CLK_PMV_CK_GCLK10", + "CLK_PMV_NE4BEG0_3", + "CLK_PMV_SE4BEG0_2", + "CLK_PMV_SW4A0_6", + "CLK_PMV_IMUX38_6", + "CLK_PMV_SW4END2_2", + "CLK_PMV_FAN5_3", + "CLK_PMV_IMUX20_6", + "CLK_PMV_EE4A0_3", + "CLK_PMV_LOGIC_OUTS6_1", + "CLK_PMV_EE2A1_2", + "CLK_PMV_EE4BEG2_5", + "CLK_PMV_EE2BEG2_0", + "CLK_PMV_WW4END0_2", + "CLK_PMV_WL1END1_5", + "CLK_PMV_NW2A0_0", + "CLK_PMV_LOGIC_OUTS17_4", + "CLK_PMV_WW4C2_3", + "CLK_PMV_IMUX14_3", + "CLK_PMV_SE4BEG3_4", + "CLK_PMV_WW4END2_0", + "CLK_PMV_WL1END3_3", + "CLK_PMV_CLK1_6", + "CLK_PMV_SW2A2_2", + "CLK_PMV_LOGIC_OUTS14_1", + "CLK_PMV_SE4C2_0", + "CLK_PMV_SE2A0_2", + "CLK_PMV_EE2A1_5", + "CLK_PMV_IMUX21_4", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_IMUX15_0", + "CLK_PMV_FAN7_5", + "CLK_PMV_WW4END1_2", + "CLK_PMV_SW4A3_2", + "CLK_PMV_SE4BEG1_1", + "CLK_PMV_LH11_3", + "CLK_PMV_IMUX14_4", + "CLK_PMV_IMUX30_6", + "CLK_PMV_A1", + "CLK_PMV_LOGIC_OUTS0_3", + "CLK_PMV_NE4BEG3_1", + "CLK_PMV_WW4C0_6", + "CLK_PMV_LH12_6", + "CLK_PMV_SE4C3_0", + "CLK_PMV_EL1BEG1_6", + "CLK_PMV_WW4B2_6", + "CLK_PMV_R_CK_GCLK30", + "CLK_PMV_NE4BEG1_5", + "CLK_PMV_CTRL0_6", + "CLK_PMV_SW2A0_1", + "CLK_PMV_IMUX45_0", + "CLK_PMV_IMUX8_0", + "CLK_PMV_IMUX25_4", + "CLK_PMV_LH6_0", + "CLK_PMV_SW2A1_2", + "CLK_PMV_WW4B3_5", + "CLK_PMV_CTRL0_4", + "CLK_PMV_LOGIC_OUTS17_3", + "CLK_PMV_LH1_5", + "CLK_PMV_SW2A1_3", + "CLK_PMV_R_CK_BUFG_CASC21", + "CLK_PMV_EE4C2_0", + "CLK_PMV_EE2A2_4", + "CLK_PMV_EE4A0_0", + "CLK_PMV_EE4A2_0", + "CLK_PMV_IMUX34_0", + "CLK_PMV_LOGIC_OUTS16_4", + "CLK_PMV_NW4END2_3", + "CLK_PMV_WW2END0_5", + "CLK_PMV_WW4B3_3", + "CLK_PMV_IMUX29_1", + "CLK_PMV_WW4C0_1", + "CLK_PMV_IMUX41_4", + "CLK_PMV_R_CK_BUFG_CASC11", + "CLK_PMV_IMUX22_1", + "CLK_PMV_CK_GCLK9", + "CLK_PMV_SE4C2_4", + "CLK_PMV_FAN4_1", + "CLK_PMV_LOGIC_OUTS1_2", + "CLK_PMV_EL1BEG2_3", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_PMV_SW4END0_4", + "CLK_PMV_ER1BEG3_4", + "CLK_PMV_WW2A0_6", + "CLK_PMV_EE4A0_5", + "CLK_PMV_BYP7_6", + "CLK_PMV_IMUX16_6", + "CLK_PMV_SW2A2_5", + "CLK_PMV_WW4A1_4", + "CLK_PMV_IMUX39_1", + "CLK_PMV_EE2BEG2_3", + "CLK_PMV_WW4B1_5", + "CLK_PMV_IMUX47_5", + "CLK_PMV_LOGIC_OUTS10_6", + "CLK_PMV_WW4B0_5", + "CLK_PMV_WW4END2_2", + "CLK_PMV_SW4A1_5", + "CLK_PMV_IMUX1_0", + "CLK_PMV_FAN3_3", + "CLK_PMV_R_CK_BUFG_CASC28", + "CLK_PMV_FAN2_0", + "CLK_PMV_IMUX11_1", + "CLK_PMV_LOGIC_OUTS2_5", + "CLK_PMV_IMUX3_4", + "CLK_PMV_BYP6_2", + "CLK_PMV_WW2END2_5", + "CLK_PMV_CK_BUFG_CASC2", + "CLK_PMV_WW2END0_6", + "CLK_PMV_IMUX25_1", + "CLK_PMV_NW4A3_4", + "CLK_PMV_IMUX37_3", + "CLK_PMV_WW2A3_3", + "CLK_PMV_EL1BEG2_4", + "CLK_PMV_SE2A3_3", + "CLK_PMV_LH10_4", + "CLK_PMV_WW4B2_2", + "CLK_PMV_IMUX3_2", + "CLK_PMV_NW2A2_2", + "CLK_PMV_EE4C2_3", + "CLK_PMV_LOGIC_OUTS12_6", + "CLK_PMV_WL1END0_5", + "CLK_PMV_LH5_6", + "CLK_PMV_IMUX21_2", + "CLK_PMV_IMUX25_6", + "CLK_PMV_SE4BEG2_3", + "CLK_PMV_EE4BEG1_1", + "CLK_PMV_WL1END1_6", + "CLK_PMV_SE2A2_0", + "CLK_PMV_LH2_2", + "CLK_PMV_NW2A3_0", + "CLK_PMV_IMUX1_1", + "CLK_PMV_WW4C1_6", + "CLK_PMV_IMUX37_6", + "CLK_PMV_CK_GCLK0", + "CLK_PMV_IMUX16_5", + "CLK_PMV_LH7_4", + "CLK_PMV_CK_BUFG_CASC14", + "CLK_PMV_EE2BEG2_5", + "CLK_PMV_EE2BEG0_3", + "CLK_PMV_LOGIC_OUTS10_2", + "CLK_PMV_LH10_6", + "CLK_PMV_IMUX21_1", + "CLK_PMV_WR1END3_6", + "CLK_PMV_CLK0_6", + "CLK_PMV_CK_BUFG_CASC8", + "CLK_PMV_IMUX37_0", + "CLK_PMV_NW4END1_5", + "CLK_PMV_IMUX8_6", + "CLK_PMV_EE2BEG2_2", + "CLK_PMV_NW4A3_1", + "CLK_PMV_WW4A1_5", + "CLK_PMV_LOGIC_OUTS9_5", + "CLK_PMV_IMUX4_0", + "CLK_PMV_IMUX18_1", + "CLK_PMV_IMUX24_1", + "CLK_PMV_NW4A1_0", + "CLK_PMV_CK_BUFG_CASC4", + "CLK_PMV_LOGIC_OUTS22_2", + "CLK_PMV_LOGIC_OUTS12_4", + "CLK_PMV_IMUX2_3", + "CLK_PMV_WW4B1_0", + "CLK_PMV_NE4BEG3_4", + "CLK_PMV_IMUX13_3", + "CLK_PMV_NE4BEG2_1", + "CLK_PMV_EE4BEG2_3", + "CLK_PMV_NE4BEG1_1", + "CLK_PMV_FAN2_5", + "CLK_PMV_BYP1_2", + "CLK_PMV_EE4A2_5", + "CLK_PMV_NW4A2_4", + "CLK_PMV_LOGIC_OUTS21_1", + "CLK_PMV_IMUX41_2", + "CLK_PMV_EE4B3_3", + "CLK_PMV_EE2A0_5", + "CLK_PMV_O", + "CLK_PMV_LOGIC_OUTS17_2", + "CLK_PMV_SE4BEG2_2", + "CLK_PMV_IMUX23_4", + "CLK_PMV_EE2BEG2_6", + "CLK_PMV_CK_GCLK8", + "CLK_PMV_IMUX34_1", + "CLK_PMV_FAN3_2", + "CLK_PMV_IMUX36_1", + "CLK_PMV_SW2A2_4", + "CLK_PMV_IMUX42_4", + "CLK_PMV_WW4C2_5", + "CLK_PMV_IMUX9_3", + "CLK_PMV_EE4C2_6", + "CLK_PMV_EE4C1_4", + "CLK_PMV_LH8_0", + "CLK_PMV_MONITOR_P_6", + "CLK_PMV_IMUX2_4", + "CLK_PMV_FAN7_6", + "CLK_PMV_EE2BEG3_3", + "CLK_PMV_SE4C3_2", + "CLK_PMV_CK_BUFG_CASC31", + "CLK_PMV_IMUX9_4", + "CLK_PMV_IMUX24_2", + "CLK_PMV_EL1BEG1_4", + "CLK_PMV_NE2A2_6", + "CLK_PMV_BYP6_0", + "CLK_PMV_LH12_1", + "CLK_PMV_IMUX0_1", + "CLK_PMV_EE2A3_6", + "CLK_PMV_EE4A0_4", + "CLK_PMV_LOGIC_OUTS7_1", + "CLK_PMV_SW4END1_1", + "CLK_PMV_WW2A1_5", + "CLK_PMV_ER1BEG0_0", + "CLK_PMV_SW4A2_6", + "CLK_PMV_NW4END2_6", + "CLK_PMV_IMUX14_2", + "CLK_PMV_NE2A0_0", + "CLK_PMV_ER1BEG1_4", + "CLK_PMV_EL1BEG0_2", + "CLK_PMV_WW4END0_5", + "CLK_PMV_SW2A3_1", + "CLK_PMV_R_CK_GCLK16", + "CLK_PMV_IMUX5_5", + "CLK_PMV_FAN3_1", + "CLK_PMV_WW4B2_0", + "CLK_PMV_IMUX17_5", + "CLK_PMV_EE2A3_2", + "CLK_PMV_NE4C0_3", + "CLK_PMV_IMUX40_3", + "CLK_PMV_IMUX11_6", + "CLK_PMV_LH12_3", + "CLK_PMV_WW4B1_2", + "CLK_PMV_LOGIC_OUTS9_3", + "CLK_PMV_EE4BEG3_0", + "CLK_PMV_BYP0_2", + "CLK_PMV_WW4END1_5", + "CLK_PMV_WL1END1_3", + "CLK_PMV_NE4C0_0", + "CLK_PMV_LH9_3", + "CLK_PMV_NW2A3_3", + "CLK_PMV_LH10_3", + "CLK_PMV_LH6_2", + "CLK_PMV_R_CK_GCLK29", + "CLK_PMV_LOGIC_OUTS19_1", + "CLK_PMV_WW4END0_4", + "CLK_PMV_IMUX13_1", + "CLK_PMV_IMUX39_2", + "CLK_PMV_WW4A3_4", + "CLK_PMV_NW4END0_4", + "CLK_PMV_NW2A1_1", + "CLK_PMV_EE4BEG3_5", + "CLK_PMV_IMUX32_6", + "CLK_PMV_BYP2_4", + "CLK_PMV_NW4END1_3", + "CLK_PMV_IMUX19_0", + "CLK_PMV_R_CK_GCLK26", + "CLK_PMV_NE2A1_3", + "CLK_PMV_WW4END2_4", + "CLK_PMV_LOGIC_OUTS7_4", + "CLK_PMV_LOGIC_OUTS13_6", + "CLK_PMV_R_CK_BUFG_CASC13", + "CLK_PMV_FAN1_3", + "CLK_PMV_SW4END2_5", + "CLK_PMV_BYP3_6", + "CLK_PMV_LOGIC_OUTS10_4", + "CLK_PMV_R_CK_BUFG_CASC30", + "CLK_PMV_R_CK_GCLK12", + "CLK_PMV_IMUX41_5", + "CLK_PMV_SE4BEG2_0", + "CLK_PMV_SE4BEG1_6", + "CLK_PMV_IMUX28_1", + "CLK_PMV_WW4C3_6", + "CLK_PMV_WW4A0_5", + "CLK_PMV_NW2A2_1", + "CLK_PMV_EE4B2_6", + "CLK_PMV_IMUX15_3", + "CLK_PMV_NW2A2_4", + "CLK_PMV_IMUX30_0", + "CLK_PMV_IMUX27_0", + "CLK_PMV_NE4BEG1_4", + "CLK_PMV_IMUX15_1", + "CLK_PMV_SE2A1_1", + "CLK_PMV_NW4END1_2", + "CLK_PMV_IMUX14_0", + "CLK_PMV_SE4C3_1", + "CLK_PMV_WW4A3_5", + "CLK_PMV_EE4A1_0", + "CLK_PMV_ER1BEG2_0", + "CLK_PMV_WL1END0_1", + "CLK_PMV_LH5_0", + "CLK_PMV_IMUX27_6", + "CLK_PMV_WW4A0_2", + "CLK_PMV_SE4C0_3", + "CLK_PMV_LOGIC_OUTS22_6", + "CLK_PMV_EE2BEG3_0", + "CLK_PMV_LOGIC_OUTS23_6", + "CLK_PMV_WW4A0_4", + "CLK_PMV_WW2END3_3", + "CLK_PMV_CK_BUFG_CASC12", + "CLK_PMV_WW2END0_4", + "CLK_PMV_ER1BEG0_5", + "CLK_PMV_LOGIC_OUTS17_1", + "CLK_PMV_LOGIC_OUTS6_2", + "CLK_PMV_FAN0_3", + "CLK_PMV_IMUX8_2", + "CLK_PMV_LH7_3", + "CLK_PMV_LOGIC_OUTS8_2", + "CLK_PMV_FAN0_1", + "CLK_PMV_IMUX22_3", + "CLK_PMV_IMUX11_4", + "CLK_PMV_NW4A1_5", + "CLK_PMV_IMUX29_5", + "CLK_PMV_EE4A2_1", + "CLK_PMV_EE2BEG0_1", + "CLK_PMV_SE4BEG2_5", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_PMV_FAN1_0", + "CLK_PMV_IMUX3_6", + "CLK_PMV_CK_GCLK6", + "CLK_PMV_WW4A2_6", + "CLK_PMV_LH1_6", + "CLK_PMV_IMUX9_6", + "CLK_PMV_NW2A0_1", + "CLK_PMV_LH2_5", + "CLK_PMV_R_CK_GCLK8", + "CLK_PMV_EE2A2_0", + "CLK_PMV_IMUX20_4", + "CLK_PMV_WW4A3_0", + "CLK_PMV_IMUX2_0", + "CLK_PMV_IMUX26_4", + "CLK_PMV_WR1END1_6", + "CLK_PMV_MONITOR_P_2", + "CLK_PMV_EL1BEG3_4", + "CLK_PMV_EE4BEG1_3", + "CLK_PMV_IMUX33_1", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_PMV_NW2A1_2", + "CLK_PMV_SW2A0_6", + "CLK_PMV_FAN4_2", + "CLK_PMV_EE2A0_4", + "CLK_PMV_CLK1_2", + "CLK_PMV_EE4A3_4", + "CLK_PMV_FAN2_3", + "CLK_PMV_R_CK_BUFG_CASC6", + "CLK_PMV_NE2A0_5", + "CLK_PMV_IMUX46_6", + "CLK_PMV_CK_GCLK14", + "CLK_PMV_WW4A3_3", + "CLK_PMV_EE4A0_1", + "CLK_PMV_NW4A0_4", + "CLK_PMV_BYP6_5", + "CLK_PMV_IMUX0_6", + "CLK_PMV_R_CK_GCLK21", + "CLK_PMV_IMUX19_4", + "CLK_PMV_BYP4_5", + "CLK_PMV_IMUX43_0", + "CLK_PMV_SE2A3_5", + "CLK_PMV_SE2A0_4", + "CLK_PMV_LOGIC_OUTS9_4", + "CLK_PMV_EL1BEG2_2", + "CLK_PMV_LOGIC_OUTS20_6", + "CLK_PMV_IMUX1_5", + "CLK_PMV_SW2A3_0", + "CLK_PMV_IMUX8_1", + "CLK_PMV_WW4C3_0", + "CLK_PMV_IMUX17_0", + "CLK_PMV_LOGIC_OUTS14_4", + "CLK_PMV_LOGIC_OUTS6_5", + "CLK_PMV_EE2A0_1", + "CLK_PMV_WW4A0_0", + "CLK_PMV_EE2A2_5", + "CLK_PMV_BYP7_3", + "CLK_PMV_NW4END0_3", + "CLK_PMV_CK_BUFG_CASC25", + "CLK_PMV_CK_GCLK23", + "CLK_PMV_IMUX28_4", + "CLK_PMV_NE2A1_1", + "CLK_PMV_WW2A2_6", + "CLK_PMV_WR1END3_1", + "CLK_PMV_EE4C1_6", + "CLK_PMV_LOGIC_OUTS20_4", + "CLK_PMV_EE4A0_2", + "CLK_PMV_SE2A1_6", + "CLK_PMV_CK_BUFG_CASC24", + "CLK_PMV_SE4BEG3_2", + "CLK_PMV_WW2END0_0", + "CLK_PMV_SE4C1_0", + "CLK_PMV_SE4BEG1_4", + "CLK_PMV_IMUX40_1", + "CLK_PMV_NE4C0_4", + "CLK_PMV_SW4END2_1", + "CLK_PMV_MONITOR_P_1", + "CLK_PMV_EE4C3_0", + "CLK_PMV_IMUX25_2", + "CLK_PMV_LOGIC_OUTS14_5", + "CLK_PMV_LH9_1", + "CLK_PMV_EE4B2_2", + "CLK_PMV_IMUX29_3", + "CLK_PMV_IMUX35_6", + "CLK_PMV_FAN4_5", + "CLK_PMV_WR1END3_0", + "CLK_PMV_SW4A0_1", + "CLK_PMV_EE4C3_6", + "CLK_PMV_EE4B0_1", + "CLK_PMV_FAN6_6", + "CLK_PMV_LOGIC_OUTS2_6", + "CLK_PMV_NW2A1_4", + "CLK_PMV_NW4A0_0", + "CLK_PMV_WW4END3_3", + "CLK_PMV_SE4C2_3", + "CLK_PMV_SE4C2_6", + "CLK_PMV_R_CK_GCLK18", + "CLK_PMV_LOGIC_OUTS7_6", + "CLK_PMV_LH9_5", + "CLK_PMV_EE4BEG1_5", + "CLK_PMV_NW4END3_6", + "CLK_PMV_WW2END3_1", + "CLK_PMV_WW4END1_0", + "CLK_PMV_EE4B1_1", + "CLK_PMV_EL1BEG3_6", + "CLK_PMV_FAN4_6", + "CLK_PMV_SW2A1_5", + "CLK_PMV_IMUX40_0", + "CLK_PMV_CK_GCLK4", + "CLK_PMV_NW4A0_2", + "CLK_PMV_IMUX30_4", + "CLK_PMV_IMUX44_6", + "CLK_PMV_WW4B2_5", + "CLK_PMV_SE4C0_0", + "CLK_PMV_EE2A1_6", + "CLK_PMV_LH10_5", + "CLK_PMV_EL1BEG0_5", + "CLK_PMV_EE4C3_4", + "CLK_PMV_FAN2_1", + "CLK_PMV_SW2A3_6", + "CLK_PMV_SE4C1_3", + "CLK_PMV_LH2_6", + "CLK_PMV_ER1BEG2_4", + "CLK_PMV_R_CK_BUFG_CASC7", + "CLK_PMV_IMUX32_3", + "CLK_PMV_CLK1_5", + "CLK_PMV_WW2END3_6", + "CLK_PMV_EE4BEG2_4", + "CLK_PMV_EL1BEG2_6", + "CLK_PMV_LH12_5", + "CLK_PMV_IMUX4_4", + "CLK_PMV_IMUX4_6", + "CLK_PMV_NE2A1_6", + "CLK_PMV_IMUX26_0", + "CLK_PMV_NW4END1_4", + "CLK_PMV_NW2A3_1", + "CLK_PMV_EE4C0_0", + "CLK_PMV_NW4END0_6", + "CLK_PMV_MONITOR_N_5", + "CLK_PMV_BYP5_1", + "CLK_PMV_SE4BEG2_1", + "CLK_PMV_WW4END0_0", + "CLK_PMV_CK_BUFG_CASC11", + "CLK_PMV_EE2A3_5", + "CLK_PMV_LOGIC_OUTS8_1", + "CLK_PMV_WW2END2_2", + "CLK_PMV_CK_GCLK19", + "CLK_PMV_LH3_4", + "CLK_PMV_LOGIC_OUTS8_6", + "CLK_PMV_SE2A3_2", + "CLK_PMV_CK_BUFG_CASC3", + "CLK_PMV_CK_GCLK22", + "CLK_PMV_IMUX17_1", + "CLK_PMV_IMUX26_5", + "CLK_PMV_IMUX26_1", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_PMV_SW4A2_0", + "CLK_PMV_EE2A1_3", + "CLK_PMV_IMUX41_0", + "CLK_PMV_IMUX23_6", + "CLK_PMV_LOGIC_OUTS1_3", + "CLK_PMV_IMUX31_2", + "CLK_PMV_R_CK_GCLK24", + "CLK_PMV_LOGIC_OUTS0_4", + "CLK_PMV_LOGIC_OUTS4_5", + "CLK_PMV_LOGIC_OUTS22_4", + "CLK_PMV_EE4BEG2_1", + "CLK_PMV_EE2BEG0_2", + "CLK_PMV_NW4END0_5", + "CLK_PMV_CK_BUFG_CASC30", + "CLK_PMV_NW2A3_5", + "CLK_PMV_R_CK_GCLK0", + "CLK_PMV_WL1END1_4", + "CLK_PMV_WW2A3_0", + "CLK_PMV_SE4BEG3_5", + "CLK_PMV_NE4C2_2", + "CLK_PMV_NE2A0_2", + "CLK_PMV_IMUX4_3", + "CLK_PMV_IMUX23_3", + "CLK_PMV_BYP2_2", + "CLK_PMV_IMUX46_4", + "CLK_PMV_NW4A0_3", + "CLK_PMV_LOGIC_OUTS2_2", + "CLK_PMV_WW4END1_1", + "CLK_PMV_EE2BEG3_4", + "CLK_PMV_LH4_3", + "CLK_PMV_WW4A1_0", + "CLK_PMV_EE4C2_4", + "CLK_PMV_SE4BEG2_4", + "CLK_PMV_IMUX26_6", + "CLK_PMV_SW4A0_0", + "CLK_PMV_IMUX47_1", + "CLK_PMV_EE2A2_1", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_PMV_IMUX25_3", + "CLK_PMV_WW2END3_5", + "CLK_PMV_IMUX35_1", + "CLK_PMV_NE4BEG2_0", + "CLK_PMV_SE2A1_5", + "CLK_PMV_IMUX16_2", + "CLK_PMV_FAN6_4", + "CLK_PMV_R_CK_BUFG_CASC22", + "CLK_PMV_IMUX16_4", + "CLK_PMV_FAN3_4", + "CLK_PMV_ER1BEG0_2", + "CLK_PMV_IMUX14_1", + "CLK_PMV_WW4B0_3", + "CLK_PMV_CTRL1_4", + "CLK_PMV_CLK0_3", + "CLK_PMV_LOGIC_OUTS10_5", + "CLK_PMV_EL1BEG1_1", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_PMV_EE4C0_5", + "CLK_PMV_SW4A3_6", + "CLK_PMV_LH2_1", + "CLK_PMV_R_CK_BUFG_CASC26", + "CLK_PMV_EL1BEG3_5", "CLK_PMV_LOGIC_OUTS10_3", "CLK_PMV_MONITOR_N_1", - "CLK_PMV_CK_BUFG_CASC3", - "CLK_PMV_WR1END2_4", - "CLK_PMV_CK_BUFG_CASC12", - "CLK_PMV_WW2A1_3", - "CLK_PMV_SW4END2_3", - "CLK_PMV_IMUX18_6", - "CLK_PMV_IMUX47_6", - "CLK_PMV_EE2A2_3", - "CLK_PMV_LH2_3", - "CLK_PMV_CLK1_6", - "CLK_PMV_LOGIC_OUTS10_5", - "CLK_PMV_R_CK_BUFG_CASC15", - "CLK_PMV_WW2A2_1", - "CLK_PMV_SE4BEG0_4", - "CLK_PMV_LOGIC_OUTS21_4", - "CLK_PMV_WL1END1_1", - "CLK_PMV_R_CK_BUFG_CASC5", - "CLK_PMV_IMUX29_5", - "CLK_PMV_EE4B3_5", - "CLK_PMV_FAN1_2", - "CLK_PMV_NW4A2_6", - "CLK_PMV_EE2BEG2_0", - "CLK_PMV_CK_GCLK11", - "CLK_PMV_IMUX16_5", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_BYP5_5", - "CLK_PMV_BYP2_2", - "CLK_PMV_IMUX30_2", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_IMUX7_0", - "CLK_PMV_R_CK_BUFG_CASC7", - "CLK_PMV_NE4C3_4", - "CLK_PMV_IMUX19_6", - "CLK_PMV_LH10_2", - "CLK_PMV_NW2A0_6", - "CLK_PMV_ER1BEG1_4", - "CLK_PMV_IMUX46_0", - "CLK_PMV_NW4A1_6", - "CLK_PMV_LOGIC_OUTS15_2", - "CLK_PMV_SE4BEG0_6", - "CLK_PMV_WW2END0_0", - "CLK_PMV_LOGIC_OUTS8_1", - "CLK_PMV_CLK0_2", - "CLK_PMV_IMUX31_2", - "CLK_PMV_NW2A3_4", - "CLK_PMV_EL1BEG2_5", - "CLK_PMV_LH3_3", - "CLK_PMV_IMUX34_6", - "CLK_PMV_LOGIC_OUTS17_3", - "CLK_PMV_NE4C1_5", - "CLK_PMV_IMUX23_3", - "CLK_PMV_R_CK_BUFG_CASC10", - "CLK_PMV_EE4BEG3_5", - "CLK_PMV_EE4A3_5", - "CLK_PMV_WR1END1_3", - "CLK_PMV_IMUX4_6", - "CLK_PMV_LH12_5", - "CLK_PMV_WW4C3_4", - "CLK_PMV_EE4A3_1", - "CLK_PMV_IMUX23_6", - "CLK_PMV_FAN7_4", - "CLK_PMV_R_CK_GCLK23", - "CLK_PMV_EE4C0_3", - "CLK_PMV_IMUX12_3", - "CLK_PMV_SW4A2_3", - "CLK_PMV_EL1BEG2_1", - "CLK_PMV_SW2A1_4", - "CLK_PMV_SE4C3_3", - "CLK_PMV_FAN0_3", - "CLK_PMV_NE2A2_0", - "CLK_PMV_IMUX42_3", - "CLK_PMV_IMUX34_0", - "CLK_PMV_SW4A1_1", - "CLK_PMV_LOGIC_OUTS7_3", - "CLK_PMV_IMUX18_5", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_WW2A3_3", - "CLK_PMV_SW2A3_1", - "CLK_PMV_R_CK_BUFG_CASC17", - "CLK_PMV_LH6_0", - "CLK_PMV_LOGIC_OUTS3_3", - "CLK_PMV_WW4END0_3", - "CLK_PMV_SE4C3_0", - "CLK_PMV_CK_BUFG_CASC23", - "CLK_PMV_IMUX1_2", - "CLK_PMV_IMUX40_0", - "CLK_PMV_LOGIC_OUTS19_6", - "CLK_PMV_NW4END1_6", - "CLK_PMV_FAN6_4", - "CLK_PMV_EE4B0_5", - "CLK_PMV_EE2BEG2_4", - "CLK_PMV_WW2END2_6", - "CLK_PMV_SW4A0_3", - "CLK_PMV_LH8_5", - "CLK_PMV_WW4A3_0", - "CLK_PMV_R_CK_BUFG_CASC26", - "CLK_PMV_EE4A0_3", - "CLK_PMV_IMUX2_3", - "CLK_PMV_IMUX47_4", - "CLK_PMV_WW4B1_2", - "CLK_PMV_WW4A2_1", - "CLK_PMV_IMUX5_3", - "CLK_PMV_CLK0_0", - "CLK_PMV_IMUX29_6", - "CLK_PMV_LH5_0", - "CLK_PMV_LOGIC_OUTS18_2", - "CLK_PMV_IMUX40_1", - "CLK_PMV_EE4B3_3", - "CLK_PMV_BYP6_5", - "CLK_PMV_WW2END0_2", - "CLK_PMV_WW4B0_4", - "CLK_PMV_LH9_4", - "CLK_PMV_NE4BEG1_3", - "CLK_PMV_BYP7_4", - "CLK_PMV_WL1END2_4", - "CLK_PMV_IMUX16_1", - "CLK_PMV_EL1BEG3_6", - "CLK_PMV_WW4A1_6", - "CLK_PMV_IMUX42_1", - "CLK_PMV_NE4C0_2", - "CLK_PMV_FAN1_4", - "CLK_PMV_CK_GCLK0", - "CLK_PMV_NE2A2_2", - "CLK_PMV_IMUX21_6", - "CLK_PMV_SE2A3_4", - "CLK_PMV_SE4C1_5", - "CLK_PMV_IMUX46_1", - "CLK_PMV_EE4A0_0", - "CLK_PMV_LOGIC_OUTS3_2", - "CLK_PMV_NW2A0_3", - "CLK_PMV_IMUX36_5", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_SW2A1_6", - "CLK_PMV_IMUX19_4", - "CLK_PMV_IMUX0_2", - "CLK_PMV_WW2A1_5", - "CLK_PMV_LOGIC_OUTS4_5", - "CLK_PMV_EE4A2_4", - "CLK_PMV_WW4B2_1", - "CLK_PMV_EE4C3_2", - "CLK_PMV_EE4A2_6", - "CLK_PMV_IMUX39_1", - "CLK_PMV_CTRL1_6", - "CLK_PMV_EE2A1_6", - "CLK_PMV_EE2A1_0", - "CLK_PMV_WL1END1_2", - "CLK_PMV_LOGIC_OUTS23_5", - "CLK_PMV_MONITOR_P_0", - "CLK_PMV_IMUX15_0", - "CLK_PMV_NE4C0_4", - "CLK_PMV_WL1END1_3", - "CLK_PMV_EE4A3_4", - "CLK_PMV_IMUX20_4", - "CLK_PMV_CK_GCLK18", - "CLK_PMV_IMUX17_3", - "CLK_PMV_EE2A2_2", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX13_4", - "CLK_PMV_R_CK_BUFG_CASC8", - "CLK_PMV_BYP3_6", - "CLK_PMV_EE4C1_4", - "CLK_PMV_WW2A0_5", - "CLK_PMV_IMUX2_2", - "CLK_PMV_R_CK_GCLK8", - "CLK_PMV_EE4BEG1_0", - "CLK_PMV_SE4C0_3", - "CLK_PMV_SE2A2_0", - "CLK_PMV_SE4C2_6", - "CLK_PMV_R_CK_GCLK19", - "CLK_PMV_EE4B3_6", - "CLK_PMV_FAN2_3", - "CLK_PMV_NW4END1_3", - "CLK_PMV_LH7_2", - "CLK_PMV_IMUX10_0", - "CLK_PMV_NW4A3_1", - "CLK_PMV_R_CK_BUFG_CASC30", - "CLK_PMV_FAN3_0", - "CLK_PMV_WW4C0_2", - "CLK_PMV_WW4END2_5", - "CLK_PMV_SE4BEG2_4", - "CLK_PMV_LOGIC_OUTS0_3", - "CLK_PMV_FAN4_2", - "CLK_PMV_IMUX14_6", - "CLK_PMV_R_CK_GCLK11", - "CLK_PMV_R_CK_GCLK13", - "CLK_PMV_ER1BEG2_5", - "CLK_PMV_IMUX13_1", - "CLK_PMV_SE2A2_4", - "CLK_PMV_EE4C0_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_EE4C3_6", - "CLK_PMV_EE4BEG3_2", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_EE4BEG1_1", - "CLK_PMV_WW4A0_6", - "CLK_PMV_EE2A1_1", - "CLK_PMV_EL1BEG1_2", - "CLK_PMV_CLK1_5", - "CLK_PMV_IMUX4_2", - "CLK_PMV_IMUX38_0", - "CLK_PMV_NW2A1_6", - "CLK_PMV_NW4END2_1", - "CLK_PMV_EE2BEG1_0", - "CLK_PMV_LOGIC_OUTS22_4", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_IMUX26_6", - "CLK_PMV_IMUX0_0", - "CLK_PMV_FAN7_0", - "CLK_PMV_FAN3_4", - "CLK_PMV_WW4END3_2", - "CLK_PMV_CK_GCLK13", - "CLK_PMV_IMUX27_2", - "CLK_PMV_WR1END3_3", - "CLK_PMV_IMUX16_0", - "CLK_PMV_NE4C2_5", - "CLK_PMV_IMUX33_2", - "CLK_PMV_EE2BEG3_0", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_IMUX16_3", - "CLK_PMV_BYP1_1", - "CLK_PMV_WR1END3_0", - "CLK_PMV_WW4B2_4", - "CLK_PMV_LOGIC_OUTS9_1", - "CLK_PMV_LOGIC_OUTS16_1", - "CLK_PMV_IMUX25_2", - "CLK_PMV_IMUX14_1", - "CLK_PMV_EE4B2_6", - "CLK_PMV_BYP1_6", - "CLK_PMV_IMUX47_5", - "CLK_PMV_CK_BUFG_CASC9", - "CLK_PMV_NW2A1_3", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_SE4BEG3_2", - "CLK_PMV_CK_GCLK14", - "CLK_PMV_LOGIC_OUTS0_6", - "CLK_PMV_LOGIC_OUTS2_2", - "CLK_PMV_CLK0_5", - "CLK_PMV_WW4A3_1", - "CLK_PMV_LH10_1", - "CLK_PMV_LOGIC_OUTS13_2", - "CLK_PMV_SE2A3_1", - "CLK_PMV_EE4BEG1_5", - "CLK_PMV_IMUX32_1", - "CLK_PMV_NE4BEG3_1", - "CLK_PMV_ER1BEG1_2", - "CLK_PMV_LH3_0", - "CLK_PMV_WW2A1_2", - "CLK_PMV_IMUX22_2", - "CLK_PMV_LH4_4", - "CLK_PMV_WW2END0_3", - "CLK_PMV_LH7_0", - "CLK_PMV_EE4A3_3", - "CLK_PMV_LOGIC_OUTS16_6", - "CLK_PMV_LOGIC_OUTS20_5", - "CLK_PMV_WW4C0_6", - "CLK_PMV_NW2A3_5", - "CLK_PMV_WR1END1_2", - "CLK_PMV_EE4A1_3", - "CLK_PMV_IMUX0_3", - "CLK_PMV_IMUX12_1", - "CLK_PMV_IMUX8_0", - "CLK_PMV_WW4END2_0", - "CLK_PMV_ER1BEG1_1", - "CLK_PMV_EE4B3_1", - "CLK_PMV_WW4A2_6", - "CLK_PMV_LH11_0", - "CLK_PMV_WW4B0_6", - "CLK_PMV_SW4END1_4", - "CLK_PMV_WW2END2_3", - "CLK_PMV_NE4BEG3_4", - "CLK_PMV_NE2A1_5", - "CLK_PMV_NE4BEG1_1", - "CLK_PMV_WW2A1_4", - "CLK_PMV_SE4BEG2_5", - "CLK_PMV_WW4A3_3", - "CLK_PMV_LH12_4", - "CLK_PMV_IMUX47_2", - "CLK_PMV_IMUX42_5", - "CLK_PMV_WW4A3_6", - "CLK_PMV_LH10_3", - "CLK_PMV_CK_GCLK25", - "CLK_PMV_IMUX43_1", - "CLK_PMV_LOGIC_OUTS19_2", - "CLK_PMV_WW4C2_2", - "CLK_PMV_EE4A0_4", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_NE4BEG1_5", - "CLK_PMV_IMUX37_1", - "CLK_PMV_R_CK_GCLK20", - "CLK_PMV_R_CK_GCLK18", - "CLK_PMV_LOGIC_OUTS6_5", - "CLK_PMV_IMUX0_4", - "CLK_PMV_LH2_1", - "CLK_PMV_LH12_0", - "CLK_PMV_EE4A2_0", - "CLK_PMV_IMUX31_6", - "CLK_PMV_NW4END1_4", - "CLK_PMV_EE4B0_4", - "CLK_PMV_FAN4_3", - "CLK_PMV_IMUX24_6", - "CLK_PMV_SE4BEG3_5", - "CLK_PMV_WR1END2_5", - "CLK_PMV_SW4A3_4", - "CLK_PMV_WW4B0_3", - "CLK_PMV_SW4END0_4", - "CLK_PMV_MONITOR_P_5", - "CLK_PMV_LOGIC_OUTS0_4", - "CLK_PMV_LH11_5", - "CLK_PMV_BYP0_4", - "CLK_PMV_LH1_3", - "CLK_PMV_LH9_3", - "CLK_PMV_FAN0_5", - "CLK_PMV_EE4A1_5", - "CLK_PMV_SE4C3_5", - "CLK_PMV_CK_GCLK1", - "CLK_PMV_SE4C1_0", - "CLK_PMV_LH12_2", - "CLK_PMV_IMUX31_3", - "CLK_PMV_R_CK_BUFG_CASC12", - "CLK_PMV_WW2A3_1", - "CLK_PMV_BYP7_0", - "CLK_PMV_EL1BEG3_0", - "CLK_PMV_SW2A0_6", - "CLK_PMV_WW2A0_4", - "CLK_PMV_CTRL0_3", - "CLK_PMV_WW2END1_2", - "CLK_PMV_EE4C3_0", - "CLK_PMV_IMUX39_4", - "CLK_PMV_WW4A2_5", - "CLK_PMV_FAN4_5", - "CLK_PMV_LOGIC_OUTS6_2", - "CLK_PMV_WW4B1_5", - "CLK_PMV_WW2A2_6", - "CLK_PMV_WW4C1_0", - "CLK_PMV_LOGIC_OUTS16_2", - "CLK_PMV_LOGIC_OUTS6_4", - "CLK_PMV_WW4C0_3", - "CLK_PMV_EE4C3_4", - "CLK_PMV_IMUX44_4", - "CLK_PMV_BYP6_3", - "CLK_PMV_IMUX18_0", - "CLK_PMV_SW4A2_2", - "CLK_PMV_IMUX3_5", - "CLK_PMV_LH10_5", - "CLK_PMV_SE4C2_1", - "CLK_PMV_NE4BEG2_6", - "CLK_PMV_IMUX12_4", - "CLK_PMV_IMUX11_0", - "CLK_PMV_NE4C3_6", - "CLK_PMV_LOGIC_OUTS18_6", - "CLK_PMV_LOGIC_OUTS4_4", - "CLK_PMV_WW4B3_5", - "CLK_PMV_IMUX30_4", - "CLK_PMV_EE4BEG2_6", - "CLK_PMV_IMUX20_3", - "CLK_PMV_SW4END2_2", - "CLK_PMV_SE4BEG3_3", - "CLK_PMV_EL1BEG0_4", - "CLK_PMV_EE4BEG0_1", - "CLK_PMV_IMUX33_4", - "CLK_PMV_IMUX23_5", - "CLK_PMV_BYP5_3", - "CLK_PMV_SW2A3_2", - "CLK_PMV_EE2BEG3_4", - "CLK_PMV_A3", - "CLK_PMV_SE2A3_3", - "CLK_PMV_LOGIC_OUTS14_5", - "CLK_PMV_IMUX32_0", - "CLK_PMV_SE2A1_5", - "CLK_PMV_SE4BEG3_0", - "CLK_PMV_IMUX28_6", - "CLK_PMV_WR1END0_0", - "CLK_PMV_LOGIC_OUTS23_6", - "CLK_PMV_LH5_2", - "CLK_PMV_WL1END0_6", - "CLK_PMV_R_CK_GCLK24", - "CLK_PMV_FAN4_4", - "CLK_PMV_CTRL1_4", - "CLK_PMV_NE4C3_3", - "CLK_PMV_SE2A2_1", - "CLK_PMV_WW4END1_4", - "CLK_PMV_NW2A3_6", - "CLK_PMV_LOGIC_OUTS12_5", - "CLK_PMV_EE4C2_2", - "CLK_PMV_WW4A0_3", - "CLK_PMV_IMUX40_5", - "CLK_PMV_NE2A1_4", - "CLK_PMV_EE4C0_2", - "CLK_PMV_WR1END1_6", - "CLK_PMV_SW4END0_2", - "CLK_PMV_IMUX21_2", - "CLK_PMV_FAN7_5", - "CLK_PMV_WW2A2_4", - "CLK_PMV_SW2A3_0", - "CLK_PMV_LH3_6", + "CLK_PMV_LOGIC_OUTS15_4", + "CLK_PMV_BYP4_0", + "CLK_PMV_SE4BEG0_3", + "CLK_PMV_IMUX10_2", + "CLK_PMV_LOGIC_OUTS13_3", + "CLK_PMV_WW4C2_1", + "CLK_PMV_EE2BEG2_1", "CLK_PMV_EE4C3_3", - "CLK_PMV_CK_BUFG_CASC14", - "CLK_PMV_WW4A1_4", - "CLK_PMV_EE4B1_4", - "CLK_PMV_IMUX46_4", - "CLK_PMV_NW4A1_2", - "CLK_PMV_NE4C2_3", - "CLK_PMV_R_CK_GCLK5", - "CLK_PMV_IMUX26_4", - "CLK_PMV_CK_BUFG_CASC6" + "CLK_PMV_EE4C0_3", + "CLK_PMV_LOGIC_OUTS17_5", + "CLK_PMV_LH4_2", + "CLK_PMV_IMUX15_6", + "CLK_PMV_NE4C0_2", + "CLK_PMV_CK_GCLK21", + "CLK_PMV_LH3_6", + "CLK_PMV_CK_BUFG_CASC19", + "CLK_PMV_EE2BEG0_4", + "CLK_PMV_CLK0_2", + "CLK_PMV_FAN7_3", + "CLK_PMV_SE4C2_2", + "CLK_PMV_R_CK_BUFG_CASC12", + "CLK_PMV_BYP1_4", + "CLK_PMV_BYP5_3", + "CLK_PMV_SE4C1_5", + "CLK_PMV_R_CK_BUFG_CASC25", + "CLK_PMV_NE2A0_1", + "CLK_PMV_SW4A2_1", + "CLK_PMV_SE4C0_2", + "CLK_PMV_IMUX34_3", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_PMV_EE4B1_5", + "CLK_PMV_EE4BEG3_4", + "CLK_PMV_IMUX29_4", + "CLK_PMV_IMUX18_3", + "CLK_PMV_FAN7_1", + "CLK_PMV_WW4C2_6", + "CLK_PMV_LH4_4", + "CLK_PMV_BYP5_5", + "CLK_PMV_R_CK_GCLK7", + "CLK_PMV_SE2A2_2", + "CLK_PMV_SW4END0_1", + "CLK_PMV_SE4C3_4", + "CLK_PMV_NW4END3_2", + "CLK_PMV_IMUX42_2", + "CLK_PMV_FAN6_2", + "CLK_PMV_LOGIC_OUTS0_5", + "CLK_PMV_LOGIC_OUTS11_6", + "CLK_PMV_CK_BUFG_CASC23", + "CLK_PMV_R_CK_GCLK31", + "CLK_PMV_NW2A0_2", + "CLK_PMV_EE4A1_5", + "CLK_PMV_NE4C1_6", + "CLK_PMV_SW2A0_4", + "CLK_PMV_EE4B3_5", + "CLK_PMV_SE4BEG1_0", + "CLK_PMV_CTRL1_5", + "CLK_PMV_CK_GCLK11", + "CLK_PMV_CK_GCLK12", + "CLK_PMV_IMUX31_3", + "CLK_PMV_WL1END3_2", + "CLK_PMV_WW4C1_1", + "CLK_PMV_BYP0_4", + "CLK_PMV_FAN0_5", + "CLK_PMV_IMUX38_0", + "CLK_PMV_IMUX4_1", + "CLK_PMV_LOGIC_OUTS3_3", + "CLK_PMV_NE2A2_2", + "CLK_PMV_WW2END1_2", + "CLK_PMV_IMUX44_2", + "CLK_PMV_IMUX30_3", + "CLK_PMV_A5", + "CLK_PMV_BYP2_5", + "CLK_PMV_IMUX44_5", + "CLK_PMV_LOGIC_OUTS16_3", + "CLK_PMV_LOGIC_OUTS12_5", + "CLK_PMV_LOGIC_OUTS1_6", + "CLK_PMV_SW4END1_0", + "CLK_PMV_CK_BUFG_CASC28", + "CLK_PMV_WW4C3_1", + "CLK_PMV_NE4BEG3_6", + "CLK_PMV_IMUX26_3", + "CLK_PMV_WW4END1_4", + "CLK_PMV_IMUX43_4", + "CLK_PMV_NE4BEG1_2", + "CLK_PMV_IMUX12_6", + "CLK_PMV_IMUX38_3", + "CLK_PMV_EE2A3_4", + "CLK_PMV_EE4B1_2", + "CLK_PMV_IMUX45_5", + "CLK_PMV_NW4A2_1", + "CLK_PMV_NE4BEG3_2", + "CLK_PMV_WW2A3_6", + "CLK_PMV_WR1END3_2", + "CLK_PMV_WW4C1_5", + "CLK_PMV_NW4A1_1", + "CLK_PMV_SW4END1_6", + "CLK_PMV_SW2A1_6", + "CLK_PMV_EE4A1_6", + "CLK_PMV_NE4BEG0_4", + "CLK_PMV_WW2END3_0", + "CLK_PMV_MONITOR_N_3", + "CLK_PMV_WW4A2_4", + "CLK_PMV_WW4END3_4", + "CLK_PMV_LH11_4", + "CLK_PMV_NE4BEG0_5", + "CLK_PMV_NE4BEG2_2", + "CLK_PMV_IMUX15_5", + "CLK_PMV_IMUX39_4", + "CLK_PMV_IMUX24_4", + "CLK_PMV_EE4C1_3", + "CLK_PMV_CTRL0_1", + "CLK_PMV_IMUX5_3", + "CLK_PMV_ODIV4", + "CLK_PMV_IMUX12_3", + "CLK_PMV_IMUX31_4", + "CLK_PMV_ER1BEG3_6", + "CLK_PMV_BYP6_4", + "CLK_PMV_SE2A1_0", + "CLK_PMV_IMUX7_1", + "CLK_PMV_IMUX12_4", + "CLK_PMV_IMUX28_2", + "CLK_PMV_SW4A3_5", + "CLK_PMV_FAN2_4", + "CLK_PMV_SW4END1_2", + "CLK_PMV_EE2BEG1_6", + "CLK_PMV_IMUX30_1", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_PMV_IMUX8_4", + "CLK_PMV_IMUX32_5", + "CLK_PMV_WW4C0_4", + "CLK_PMV_LOGIC_OUTS15_5", + "CLK_PMV_WW4B3_4", + "CLK_PMV_CK_GCLK17", + "CLK_PMV_WW4B3_1", + "CLK_PMV_SW4A3_1", + "CLK_PMV_IMUX47_2", + "CLK_PMV_SW4END3_2", + "CLK_PMV_CK_GCLK13", + "CLK_PMV_EE4B0_6", + "CLK_PMV_BYP1_1", + "CLK_PMV_LOGIC_OUTS11_2", + "CLK_PMV_EE4B0_4", + "CLK_PMV_EE4BEG3_1", + "CLK_PMV_EE4B1_6", + "CLK_PMV_LOGIC_OUTS16_2", + "CLK_PMV_IMUX0_4", + "CLK_PMV_LH9_6", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_PMV_LOGIC_OUTS13_2", + "CLK_PMV_IMUX6_0", + "CLK_PMV_IMUX10_3", + "CLK_PMV_NE4C2_5", + "CLK_PMV_NW4END3_0", + "CLK_PMV_FAN4_0", + "CLK_PMV_IMUX24_5", + "CLK_PMV_IMUX11_2", + "CLK_PMV_IMUX17_6", + "CLK_PMV_NE4BEG3_5", + "CLK_PMV_NE4BEG3_3", + "CLK_PMV_SW4A3_4", + "CLK_PMV_CTRL1_3", + "CLK_PMV_NW2A0_6", + "CLK_PMV_EE4BEG1_2", + "CLK_PMV_BYP6_1", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_PMV_IMUX42_3", + "CLK_PMV_IMUX47_0", + "CLK_PMV_IMUX33_6", + "CLK_PMV_WW4A0_3", + "CLK_PMV_IMUX36_3", + "CLK_PMV_WW2END1_1", + "CLK_PMV_WW2END2_1", + "CLK_PMV_WW4A1_3", + "CLK_PMV_BYP7_0", + "CLK_PMV_R_CK_BUFG_CASC8", + "CLK_PMV_LOGIC_OUTS15_3", + "CLK_PMV_LOGIC_OUTS23_4", + "CLK_PMV_NE4C1_4", + "CLK_PMV_WL1END3_4", + "CLK_PMV_IMUX43_1", + "CLK_PMV_EE4B1_3", + "CLK_PMV_LOGIC_OUTS18_1", + "CLK_PMV_IMUX8_5" ], - "sites": [], - "pips": {}, - "tile_type": "CLK_PMV" + "tile_type": "CLK_PMV", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_PMV2.json b/artix7/tile_type_CLK_PMV2.json index 4078315..eb2c686 100644 --- a/artix7/tile_type_CLK_PMV2.json +++ b/artix7/tile_type_CLK_PMV2.json @@ -1,377 +1,377 @@ { + "pips": {}, "wires": [ - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_WR1END0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_BYP2_0", - "CLK_FEED_R_CK_GCLK12", - "CLK_PMV_BYP6_0", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_GCLK12", - "CLK_PMV2_ODIV4", - "CLK_PMV_BYP5_0", - "CLK_FEED_R_CK_GCLK15", - "CLK_PMV_IMUX27_0", - "CLK_FEED_EE4BEG0", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2END3", - "CLK_FEED_R_CK_GCLK17", - "CLK_PMV2_O", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_EE4A2", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_NW4A0", - "CLK_FEED_WW4C1", - "CLK_FEED_LH6", - "CLK_FEED_EL1BEG0", - "CLK_FEED_WW4B1", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_WR1END1", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_EL1BEG1", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_EE4A1", - "CLK_FEED_WW4END1", - "CLK_PMV_IMUX41_0", - "CLK_FEED_R_CK_GCLK23", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_FEED_R_CK_GCLK28", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_IMUX7_0", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX46_0", - "CLK_FEED_EL1BEG2", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK4", - "CLK_PMV_FAN5_0", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX17_0", - "CLK_FEED_WW4A1", - "CLK_PMV2_A2", - "CLK_PMV_IMUX35_0", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_EE2A0", - "CLK_PMV2_A0", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_LH8", - "CLK_FEED_SW4A0", - "CLK_FEED_NE4C3", - "CLK_FEED_SE2A1", - "CLK_FEED_R_CK_GCLK27", - "CLK_PMV2_A1", - "CLK_FEED_NE4BEG0", - "CLK_FEED_SE4C0", - "CLK_FEED_EE2A2", - "CLK_PMV_IMUX43_0", - "CLK_FEED_NE4BEG3", - "CLK_FEED_WW4END2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_PMV_CLK1_0", - "CLK_FEED_CK_GCLK8", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_PMV_IMUX34_0", - "CLK_FEED_NE4BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_WR1END3", - "CLK_PMV_FAN6_0", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_SW2A2", - "CLK_FEED_LH9", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK15", - "CLK_PMV2_EN", - "CLK_FEED_R_CK_GCLK20", - "CLK_PMV_IMUX40_0", - "CLK_FEED_WW4A2", - "CLK_PMV_IMUX24_0", - "CLK_FEED_R_CK_GCLK5", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX5_0", - "CLK_FEED_SE2A0", - "CLK_FEED_NW4END2", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_PMV_CLK0_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_FEED_WW2A0", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_LH3", - "CLK_FEED_MONITOR_N", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_NW4END0", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_EE4B0", - "CLK_FEED_LH11", - "CLK_PMV_FAN4_0", - "CLK_FEED_NW2A0", - "CLK_FEED_SW4A2", - "CLK_FEED_NW4A2", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_WW4END0", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_WW2END2", - "CLK_FEED_EE2A1", - "CLK_FEED_NE2A0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_EE4A3", - "CLK_FEED_LH12", - "CLK_FEED_EE2BEG3", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_SE4BEG2", - "CLK_FEED_LH7", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_NW4END3", - "CLK_PMV_FAN0_0", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_PMV_IMUX15_0", - "CLK_FEED_EE4C0", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX47_0", - "CLK_FEED_R_CK_GCLK2", - "CLK_PMV_BYP0_0", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_EE2BEG2", - "CLK_PMV_IMUX29_0", - "CLK_FEED_EE4BEG1", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX1_0", - "CLK_FEED_LH2", - "CLK_PMV_FAN3_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_FAN2_0", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_WW4A0", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_PMV_IMUX39_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_SW4END1", - "CLK_FEED_WW2A3", - "CLK_FEED_SE2A2", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_SE4C1", - "CLK_FEED_SW2A0", - "CLK_FEED_EE2A3", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_WW4END3", - "CLK_FEED_CK_GCLK5", - "CLK_PMV_IMUX38_0", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_PMV_IMUX22_0", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_SW4END0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_FAN7_0", - "CLK_FEED_EE4C2", - "CLK_FEED_LH10", - "CLK_PMV_IMUX28_0", - "CLK_FEED_NE4C1", - "CLK_FEED_ER1BEG0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_CTRL0_0", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_SE4BEG1", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_LH1", - "CLK_FEED_WL1END0", - "CLK_FEED_SW4A3", - "CLK_PMV_IMUX6_0", "CLK_FEED_CK_GCLK13", - "CLK_PMV_IMUX33_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_FEED_CK_GCLK11", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_FEED_LH4", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_NE4C0", - "CLK_FEED_NE2A2", - "CLK_PMV_IMUX9_0", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_NE4BEG1", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_PMV_BYP3_0", - "CLK_FEED_CK_GCLK30", - "CLK_PMV_IMUX31_0", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4C3", - "CLK_FEED_EE4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_ER1BEG2", - "CLK_FEED_WL1END3", - "CLK_FEED_SE2A3", - "CLK_PMV_FAN1_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_EE4BEG2", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_PMV_IMUX8_0", - "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_CK_BUFG_CASC3", "CLK_FEED_WW4B2", - "CLK_PMV_IMUX26_0", - "CLK_FEED_SE4C2", - "CLK_FEED_CK_GCLK10", - "CLK_PMV_BYP4_0", - "CLK_FEED_R_CK_GCLK30", - "CLK_PMV_BYP1_0", - "CLK_PMV_IMUX20_0", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_SE4C3", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_FEED_NW2A1", - "CLK_PMV_IMUX21_0", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_EE4BEG3", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_NW2A2", - "CLK_PMV_IMUX12_0", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_CK_GCLK14", - "CLK_PMV_IMUX36_0", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_PMV_IMUX30_0", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_SW2A1", - "CLK_PMV_IMUX4_0", - "CLK_FEED_EE2BEG0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A3", - "CLK_FEED_R_CK_GCLK26", - "CLK_PMV_LOGIC_OUTS6_0", + "CLK_FEED_EE4B2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_WW2A0", + "CLK_PMV_BYP3_0", + "CLK_FEED_EE4A2", "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_LH5", - "CLK_FEED_EE4C3", - "CLK_FEED_WR1END2", - "CLK_PMV_BYP7_0", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_CK_GCLK22", - "CLK_PMV_LOGIC_OUTS9_0", - "CLK_FEED_SW4A1", - "CLK_FEED_NE4C2", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_PMV_IMUX18_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_WL1END2", - "CLK_FEED_CK_GCLK2", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX2_0", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_WW4C0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX37_0", - "CLK_FEED_SW2A3", + "CLK_PMV_FAN5_0", + "CLK_FEED_R_CK_GCLK4", "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_GCLK10", - "CLK_PMV_IMUX25_0", - "CLK_FEED_WW4A3", - "CLK_FEED_WW2END1", - "CLK_PMV_IMUX23_0", - "CLK_FEED_CK_GCLK20", - "CLK_PMV_IMUX32_0", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_NW2A3", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_WW2A1", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_WW4B3", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4END1", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_EE4B1", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_NE2A1", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_PMV_FAN1_0", + "CLK_FEED_EE4BEG1", + "CLK_FEED_CK_GCLK29", + "CLK_PMV_IMUX46_0", + "CLK_FEED_WW4C0", + "CLK_FEED_EE4BEG2", + "CLK_PMV_BYP0_0", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_FEED_CK_GCLK19", + "CLK_FEED_CK_BUFG_CASC22", + "CLK_PMV_IMUX44_0", "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_EE4A0", - "CLK_FEED_WL1END1", - "CLK_FEED_EE2BEG1", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_PMV_IMUX36_0", + "CLK_FEED_SW4END1", + "CLK_PMV_BYP5_0", + "CLK_PMV_IMUX2_0", + "CLK_FEED_LH12", + "CLK_PMV_IMUX5_0", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_FEED_WW4END3", + "CLK_FEED_SE4C1", + "CLK_FEED_CK_GCLK9", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_PMV_IMUX25_0", + "CLK_FEED_EE4C3", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_GCLK14", "CLK_FEED_WW2END0", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_CK_GCLK2", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_CK_GCLK15", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_PMV_CTRL0_0", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_PMV_FAN0_0", + "CLK_PMV_IMUX43_0", + "CLK_FEED_NE4BEG0", + "CLK_FEED_SE4BEG3", + "CLK_FEED_WW4A2", + "CLK_FEED_SE4BEG1", + "CLK_PMV2_A1", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_WW2A2", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_PMV_IMUX17_0", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_EE4BEG0", + "CLK_PMV_IMUX13_0", + "CLK_FEED_CK_GCLK11", + "CLK_PMV_IMUX20_0", + "CLK_FEED_CK_GCLK27", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_LH10", + "CLK_PMV_IMUX22_0", + "CLK_FEED_SE4C0", + "CLK_PMV2_A0", + "CLK_FEED_LH3", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_IMUX7_0", + "CLK_PMV_IMUX31_0", + "CLK_FEED_WW2A3", + "CLK_FEED_NW4A1", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_PMV_IMUX28_0", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_LH5", + "CLK_FEED_NW4A2", + "CLK_PMV_BYP1_0", + "CLK_FEED_WW4END1", + "CLK_FEED_EE2BEG2", + "CLK_FEED_WL1END0", + "CLK_FEED_NE4BEG3", + "CLK_PMV_IMUX42_0", + "CLK_PMV_FAN3_0", + "CLK_FEED_WL1END1", + "CLK_FEED_SW2A1", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_FEED_EE2BEG0", + "CLK_FEED_CK_GCLK7", + "CLK_PMV_IMUX40_0", + "CLK_FEED_CK_GCLK22", + "CLK_FEED_EE4A1", + "CLK_FEED_EE4BEG3", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_CK_BUFG_CASC8", + "CLK_FEED_EE2BEG1", + "CLK_FEED_SW4END0", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_SE4BEG2", + "CLK_FEED_NE2A3", + "CLK_FEED_LH8", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_PMV_IMUX29_0", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_WW4END2", + "CLK_FEED_SW4A3", + "CLK_PMV_IMUX26_0", + "CLK_FEED_LH11", + "CLK_PMV_IMUX0_0", + "CLK_PMV_IMUX11_0", + "CLK_FEED_EE4C1", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_IMUX15_0", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_NE4C0", + "CLK_FEED_CK_GCLK24", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_SE4C2", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_ER1BEG1", + "CLK_PMV_IMUX41_0", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_MONITOR_P", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_PMV_IMUX45_0", + "CLK_PMV_IMUX8_0", + "CLK_FEED_WW4C3", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_WW2END2", + "CLK_FEED_SE2A1", + "CLK_FEED_WW4A3", + "CLK_FEED_CK_GCLK8", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_EL1BEG1", + "CLK_PMV_IMUX34_0", + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_EE2BEG3", + "CLK_FEED_LH7", + "CLK_FEED_SW4A0", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_PMV_FAN7_0", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_FEED_LH9", + "CLK_FEED_SW4A2", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK28", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_MONITOR_N", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_FEED_EE4B3", + "CLK_PMV_IMUX24_0", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_PMV_IMUX1_0", + "CLK_FEED_NE2A1", + "CLK_FEED_CK_GCLK25", + "CLK_PMV_FAN2_0", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_SW4END2", + "CLK_PMV_BYP4_0", + "CLK_PMV_CLK1_0", + "CLK_PMV_IMUX32_0", + "CLK_PMV_IMUX9_0", + "CLK_FEED_EE2A1", + "CLK_FEED_SE2A3", + "CLK_FEED_SW2A0", + "CLK_FEED_NE2A2", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_FEED_WW4C2", + "CLK_FEED_NE4BEG1", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_NW2A1", + "CLK_FEED_EE4B0", + "CLK_FEED_NE4C2", + "CLK_PMV_IMUX10_0", + "CLK_FEED_R_CK_GCLK15", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_FEED_WW4B0", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_PMV_BYP2_0", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_FEED_WW2END1", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_PMV_FAN6_0", + "CLK_PMV_IMUX37_0", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_WR1END0", + "CLK_FEED_EE4A3", + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_NW2A2", + "CLK_PMV_IMUX4_0", + "CLK_FEED_LH4", + "CLK_FEED_EE2A0", + "CLK_PMV_IMUX35_0", + "CLK_PMV_IMUX16_0", + "CLK_FEED_ER1BEG2", "CLK_PMV2_ODIV2", - "CLK_FEED_SE4BEG0" + "CLK_FEED_ER1BEG3", + "CLK_FEED_WW4A0", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_WR1END3", + "CLK_PMV2_A2", + "CLK_FEED_LH1", + "CLK_FEED_EE2A3", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2END3", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_SE4C3", + "CLK_PMV_IMUX23_0", + "CLK_PMV_IMUX38_0", + "CLK_PMV_IMUX12_0", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_NW4END2", + "CLK_FEED_EE4C0", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_WL1END3", + "CLK_FEED_NW2A0", + "CLK_FEED_ER1BEG0", + "CLK_FEED_NW4A0", + "CLK_FEED_WW4A1", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_FEED_LH2", + "CLK_FEED_SW2A2", + "CLK_PMV_BYP6_0", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_PMV_IMUX3_0", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_CK_GCLK18", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_LH6", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_GCLK2", + "CLK_PMV_IMUX21_0", + "CLK_FEED_NW4END3", + "CLK_FEED_NE4C1", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WW2A1", + "CLK_FEED_R_CK_GCLK16", + "CLK_PMV_IMUX33_0", + "CLK_PMV_IMUX18_0", + "CLK_FEED_SE4BEG0", + "CLK_FEED_WL1END2", + "CLK_FEED_NW4END1", + "CLK_FEED_NW4END0", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_FEED_SE2A0", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_WR1END2", + "CLK_FEED_SW4END3", + "CLK_FEED_WW4END0", + "CLK_PMV_CTRL1_0", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_FEED_EE4B1", + "CLK_FEED_SW4A1", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_NE4C3", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_CK_GCLK23", + "CLK_PMV_IMUX19_0", + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_EE2A2", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_FEED_CK_BUFG_CASC16", + "CLK_FEED_NE2A0", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_PMV_IMUX6_0", + "CLK_PMV_IMUX39_0", + "CLK_FEED_SE2A2", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_SW2A3", + "CLK_FEED_EE4A0", + "CLK_FEED_CK_GCLK30", + "CLK_PMV_CLK0_0", + "CLK_FEED_EL1BEG3", + "CLK_FEED_WW4C1", + "CLK_PMV_FAN4_0", + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_FEED_EL1BEG0", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_FEED_R_CK_GCLK31", + "CLK_PMV_IMUX47_0", + "CLK_PMV_IMUX30_0", + "CLK_PMV_IMUX27_0", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_EE4C2", + "CLK_PMV2_ODIV4", + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_PMV_IMUX14_0", + "CLK_FEED_WW4B3", + "CLK_PMV2_O", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_PMV_BYP7_0", + "CLK_FEED_EL1BEG2", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_PMV2_EN", + "CLK_FEED_WW4B1" ], + "tile_type": "CLK_PMV2", "sites": [ { - "prefix": "PMV", - "y_coord": 0, - "type": "PMV2", "site_pins": { - "ODIV2": "CLK_PMV2_ODIV2", - "O": "CLK_PMV2_O", - "A0": "CLK_PMV2_A0", + "ODIV4": "CLK_PMV2_ODIV4", "A2": "CLK_PMV2_A2", - "EN": "CLK_PMV2_EN", "A1": "CLK_PMV2_A1", - "ODIV4": "CLK_PMV2_ODIV4" + "EN": "CLK_PMV2_EN", + "ODIV2": "CLK_PMV2_ODIV2", + "A0": "CLK_PMV2_A0", + "O": "CLK_PMV2_O" }, + "type": "PMV2", + "prefix": "PMV", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 } - ], - "pips": {}, - "tile_type": "CLK_PMV2" + ] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_PMV2_SVT.json b/artix7/tile_type_CLK_PMV2_SVT.json index b9745c3..24c95ca 100644 --- a/artix7/tile_type_CLK_PMV2_SVT.json +++ b/artix7/tile_type_CLK_PMV2_SVT.json @@ -1,360 +1,360 @@ { - "wires": [ - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_WR1END0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_BYP2_0", - "CLK_FEED_R_CK_GCLK12", - "CLK_PMV_BYP6_0", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_GCLK12", - "CLK_PMV2_ODIV4", - "CLK_PMV_BYP5_0", - "CLK_FEED_R_CK_GCLK15", - "CLK_PMV_IMUX27_0", - "CLK_FEED_EE4BEG0", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2END3", - "CLK_FEED_R_CK_GCLK17", - "CLK_PMV2_O", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_EE4A2", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_NW4A0", - "CLK_FEED_WW4C1", - "CLK_FEED_LH6", - "CLK_FEED_EL1BEG0", - "CLK_FEED_WW4B1", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_WR1END1", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_EL1BEG1", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_EE4A1", - "CLK_FEED_WW4END1", - "CLK_PMV_IMUX41_0", - "CLK_FEED_R_CK_GCLK23", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_FEED_R_CK_GCLK28", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_IMUX7_0", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX46_0", - "CLK_FEED_EL1BEG2", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK4", - "CLK_PMV_FAN5_0", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX17_0", - "CLK_FEED_WW4A1", - "CLK_PMV2_A2", - "CLK_PMV_IMUX35_0", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_EE2A0", - "CLK_PMV2_A0", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_LH8", - "CLK_FEED_SW4A0", - "CLK_FEED_NE4C3", - "CLK_FEED_SE2A1", - "CLK_FEED_R_CK_GCLK27", - "CLK_PMV2_A1", - "CLK_FEED_NE4BEG0", - "CLK_FEED_SE4C0", - "CLK_FEED_EE2A2", - "CLK_PMV_IMUX43_0", - "CLK_FEED_NE4BEG3", - "CLK_FEED_WW4END2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_PMV_CLK1_0", - "CLK_FEED_CK_GCLK8", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_PMV_IMUX34_0", - "CLK_FEED_NE4BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_WR1END3", - "CLK_PMV_FAN6_0", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_SW2A2", - "CLK_FEED_LH9", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK15", - "CLK_PMV2_EN", - "CLK_FEED_R_CK_GCLK20", - "CLK_PMV_IMUX40_0", - "CLK_FEED_WW4A2", - "CLK_PMV_IMUX24_0", - "CLK_FEED_R_CK_GCLK5", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX5_0", - "CLK_FEED_SE2A0", - "CLK_FEED_NW4END2", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_PMV_CLK0_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_FEED_WW2A0", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_LH3", - "CLK_FEED_MONITOR_N", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_NW4END0", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_EE4B0", - "CLK_FEED_LH11", - "CLK_PMV_FAN4_0", - "CLK_FEED_NW2A0", - "CLK_FEED_SW4A2", - "CLK_FEED_NW4A2", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_WW4END0", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_WW2END2", - "CLK_FEED_EE2A1", - "CLK_FEED_NE2A0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_EE4A3", - "CLK_FEED_LH12", - "CLK_FEED_EE2BEG3", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_SE4BEG2", - "CLK_FEED_LH7", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_NW4END3", - "CLK_PMV_FAN0_0", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_PMV_IMUX15_0", - "CLK_FEED_EE4C0", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX47_0", - "CLK_FEED_R_CK_GCLK2", - "CLK_PMV_BYP0_0", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_EE2BEG2", - "CLK_PMV_IMUX29_0", - "CLK_FEED_EE4BEG1", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX1_0", - "CLK_FEED_LH2", - "CLK_PMV_FAN3_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_FAN2_0", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_WW4A0", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_PMV_IMUX39_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_SW4END1", - "CLK_FEED_WW2A3", - "CLK_FEED_SE2A2", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_SE4C1", - "CLK_FEED_SW2A0", - "CLK_FEED_EE2A3", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_WW4END3", - "CLK_FEED_CK_GCLK5", - "CLK_PMV_IMUX38_0", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_PMV_IMUX22_0", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_SW4END0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_FAN7_0", - "CLK_FEED_EE4C2", - "CLK_FEED_LH10", - "CLK_PMV_IMUX28_0", - "CLK_FEED_NE4C1", - "CLK_FEED_ER1BEG0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_CTRL0_0", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_SE4BEG1", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_LH1", - "CLK_FEED_WL1END0", - "CLK_FEED_SW4A3", - "CLK_PMV_IMUX6_0", - "CLK_FEED_CK_GCLK13", - "CLK_PMV_IMUX33_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_FEED_CK_GCLK11", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_FEED_LH4", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_NE4C0", - "CLK_FEED_NE2A2", - "CLK_PMV_IMUX9_0", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_NE4BEG1", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_PMV_BYP3_0", - "CLK_FEED_CK_GCLK30", - "CLK_PMV_IMUX31_0", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4C3", - "CLK_FEED_EE4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_ER1BEG2", - "CLK_FEED_WL1END3", - "CLK_FEED_SE2A3", - "CLK_PMV_FAN1_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_EE4BEG2", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_PMV_IMUX8_0", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_WW4B2", - "CLK_PMV_IMUX26_0", - "CLK_FEED_SE4C2", - "CLK_FEED_CK_GCLK10", - "CLK_PMV_BYP4_0", - "CLK_FEED_R_CK_GCLK30", - "CLK_PMV_BYP1_0", - "CLK_PMV_IMUX20_0", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_SE4C3", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_FEED_NW2A1", - "CLK_PMV_IMUX21_0", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_EE4BEG3", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_NW2A2", - "CLK_PMV_IMUX12_0", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_CK_GCLK14", - "CLK_PMV_IMUX36_0", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_PMV_IMUX30_0", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_SW2A1", - "CLK_PMV_IMUX4_0", - "CLK_FEED_EE2BEG0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A3", - "CLK_FEED_R_CK_GCLK26", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_LH5", - "CLK_FEED_EE4C3", - "CLK_FEED_WR1END2", - "CLK_PMV_BYP7_0", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_CK_GCLK22", - "CLK_PMV_LOGIC_OUTS9_0", - "CLK_FEED_SW4A1", - "CLK_FEED_NE4C2", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_PMV_IMUX18_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_WL1END2", - "CLK_FEED_CK_GCLK2", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX2_0", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_WW4C0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX37_0", - "CLK_FEED_SW2A3", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_GCLK10", - "CLK_PMV_IMUX25_0", - "CLK_FEED_WW4A3", - "CLK_FEED_WW2END1", - "CLK_PMV_IMUX23_0", - "CLK_FEED_CK_GCLK20", - "CLK_PMV_IMUX32_0", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_NW2A3", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_WW2A1", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_WW4B3", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4END1", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_EE4B1", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_NE2A1", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_EE4A0", - "CLK_FEED_WL1END1", - "CLK_FEED_EE2BEG1", - "CLK_FEED_WW2END0", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_PMV2_ODIV2", - "CLK_FEED_SE4BEG0" - ], - "sites": [], "pips": {}, - "tile_type": "CLK_PMV2_SVT" + "wires": [ + "CLK_FEED_CK_GCLK13", + "CLK_FEED_CK_BUFG_CASC3", + "CLK_FEED_WW4B2", + "CLK_FEED_EE4B2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_WW2A0", + "CLK_PMV_BYP3_0", + "CLK_FEED_EE4A2", + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_PMV_FAN5_0", + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_PMV_FAN1_0", + "CLK_FEED_EE4BEG1", + "CLK_FEED_CK_GCLK29", + "CLK_PMV_IMUX46_0", + "CLK_FEED_WW4C0", + "CLK_FEED_EE4BEG2", + "CLK_PMV_BYP0_0", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_FEED_CK_GCLK19", + "CLK_FEED_CK_BUFG_CASC22", + "CLK_PMV_IMUX44_0", + "CLK_FEED_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_PMV_IMUX36_0", + "CLK_FEED_SW4END1", + "CLK_PMV_BYP5_0", + "CLK_PMV_IMUX2_0", + "CLK_FEED_LH12", + "CLK_PMV_IMUX5_0", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_FEED_WW4END3", + "CLK_FEED_SE4C1", + "CLK_FEED_CK_GCLK9", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_PMV_IMUX25_0", + "CLK_FEED_EE4C3", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_WW2END0", + "CLK_FEED_CK_GCLK2", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_CK_GCLK15", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_PMV_CTRL0_0", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_PMV_FAN0_0", + "CLK_PMV_IMUX43_0", + "CLK_FEED_NE4BEG0", + "CLK_FEED_SE4BEG3", + "CLK_FEED_WW4A2", + "CLK_FEED_SE4BEG1", + "CLK_PMV2_A1", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_WW2A2", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_PMV_IMUX17_0", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_EE4BEG0", + "CLK_PMV_IMUX13_0", + "CLK_FEED_CK_GCLK11", + "CLK_PMV_IMUX20_0", + "CLK_FEED_CK_GCLK27", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_LH10", + "CLK_PMV_IMUX22_0", + "CLK_FEED_SE4C0", + "CLK_PMV2_A0", + "CLK_FEED_LH3", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_IMUX7_0", + "CLK_PMV_IMUX31_0", + "CLK_FEED_WW2A3", + "CLK_FEED_NW4A1", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_PMV_IMUX28_0", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_LH5", + "CLK_FEED_NW4A2", + "CLK_PMV_BYP1_0", + "CLK_FEED_WW4END1", + "CLK_FEED_EE2BEG2", + "CLK_FEED_WL1END0", + "CLK_FEED_NE4BEG3", + "CLK_PMV_IMUX42_0", + "CLK_PMV_FAN3_0", + "CLK_FEED_WL1END1", + "CLK_FEED_SW2A1", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_FEED_EE2BEG0", + "CLK_FEED_CK_GCLK7", + "CLK_PMV_IMUX40_0", + "CLK_FEED_CK_GCLK22", + "CLK_FEED_EE4A1", + "CLK_FEED_EE4BEG3", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_CK_BUFG_CASC8", + "CLK_FEED_EE2BEG1", + "CLK_FEED_SW4END0", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_SE4BEG2", + "CLK_FEED_NE2A3", + "CLK_FEED_LH8", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_PMV_IMUX29_0", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_WW4END2", + "CLK_FEED_SW4A3", + "CLK_PMV_IMUX26_0", + "CLK_FEED_LH11", + "CLK_PMV_IMUX0_0", + "CLK_PMV_IMUX11_0", + "CLK_FEED_EE4C1", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_IMUX15_0", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_NE4C0", + "CLK_FEED_CK_GCLK24", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_SE4C2", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_ER1BEG1", + "CLK_PMV_IMUX41_0", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_MONITOR_P", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_PMV_IMUX45_0", + "CLK_PMV_IMUX8_0", + "CLK_FEED_WW4C3", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_WW2END2", + "CLK_FEED_SE2A1", + "CLK_FEED_WW4A3", + "CLK_FEED_CK_GCLK8", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_EL1BEG1", + "CLK_PMV_IMUX34_0", + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_EE2BEG3", + "CLK_FEED_LH7", + "CLK_FEED_SW4A0", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_PMV_FAN7_0", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_FEED_LH9", + "CLK_FEED_SW4A2", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK28", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_MONITOR_N", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_FEED_EE4B3", + "CLK_PMV_IMUX24_0", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_PMV_IMUX1_0", + "CLK_FEED_NE2A1", + "CLK_FEED_CK_GCLK25", + "CLK_PMV_FAN2_0", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_SW4END2", + "CLK_PMV_BYP4_0", + "CLK_PMV_CLK1_0", + "CLK_PMV_IMUX32_0", + "CLK_PMV_IMUX9_0", + "CLK_FEED_EE2A1", + "CLK_FEED_SE2A3", + "CLK_FEED_SW2A0", + "CLK_FEED_NE2A2", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_FEED_WW4C2", + "CLK_FEED_NE4BEG1", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_NW2A1", + "CLK_FEED_EE4B0", + "CLK_FEED_NE4C2", + "CLK_PMV_IMUX10_0", + "CLK_FEED_R_CK_GCLK15", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_FEED_WW4B0", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_PMV_BYP2_0", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_FEED_WW2END1", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_PMV_FAN6_0", + "CLK_PMV_IMUX37_0", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_WR1END0", + "CLK_FEED_EE4A3", + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_NW2A2", + "CLK_PMV_IMUX4_0", + "CLK_FEED_LH4", + "CLK_FEED_EE2A0", + "CLK_PMV_IMUX35_0", + "CLK_PMV_IMUX16_0", + "CLK_FEED_ER1BEG2", + "CLK_PMV2_ODIV2", + "CLK_FEED_ER1BEG3", + "CLK_FEED_WW4A0", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_WR1END3", + "CLK_PMV2_A2", + "CLK_FEED_LH1", + "CLK_FEED_EE2A3", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2END3", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_SE4C3", + "CLK_PMV_IMUX23_0", + "CLK_PMV_IMUX38_0", + "CLK_PMV_IMUX12_0", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_NW4END2", + "CLK_FEED_EE4C0", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_WL1END3", + "CLK_FEED_NW2A0", + "CLK_FEED_ER1BEG0", + "CLK_FEED_NW4A0", + "CLK_FEED_WW4A1", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_FEED_LH2", + "CLK_FEED_SW2A2", + "CLK_PMV_BYP6_0", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_PMV_IMUX3_0", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_CK_GCLK18", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_LH6", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_GCLK2", + "CLK_PMV_IMUX21_0", + "CLK_FEED_NW4END3", + "CLK_FEED_NE4C1", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WW2A1", + "CLK_FEED_R_CK_GCLK16", + "CLK_PMV_IMUX33_0", + "CLK_PMV_IMUX18_0", + "CLK_FEED_SE4BEG0", + "CLK_FEED_WL1END2", + "CLK_FEED_NW4END1", + "CLK_FEED_NW4END0", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_FEED_SE2A0", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_WR1END2", + "CLK_FEED_SW4END3", + "CLK_FEED_WW4END0", + "CLK_PMV_CTRL1_0", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_FEED_EE4B1", + "CLK_FEED_SW4A1", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_NE4C3", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_CK_GCLK23", + "CLK_PMV_IMUX19_0", + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_EE2A2", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_FEED_CK_BUFG_CASC16", + "CLK_FEED_NE2A0", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_PMV_IMUX6_0", + "CLK_PMV_IMUX39_0", + "CLK_FEED_SE2A2", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_SW2A3", + "CLK_FEED_EE4A0", + "CLK_FEED_CK_GCLK30", + "CLK_PMV_CLK0_0", + "CLK_FEED_EL1BEG3", + "CLK_FEED_WW4C1", + "CLK_PMV_FAN4_0", + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_FEED_EL1BEG0", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_FEED_R_CK_GCLK31", + "CLK_PMV_IMUX47_0", + "CLK_PMV_IMUX30_0", + "CLK_PMV_IMUX27_0", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_EE4C2", + "CLK_PMV2_ODIV4", + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_PMV_IMUX14_0", + "CLK_FEED_WW4B3", + "CLK_PMV2_O", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_PMV_BYP7_0", + "CLK_FEED_EL1BEG2", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_PMV2_EN", + "CLK_FEED_WW4B1" + ], + "tile_type": "CLK_PMV2_SVT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_PMVIOB.json b/artix7/tile_type_CLK_PMVIOB.json index b4e7a5d..9dff3bd 100644 --- a/artix7/tile_type_CLK_PMVIOB.json +++ b/artix7/tile_type_CLK_PMVIOB.json @@ -1,359 +1,359 @@ { - "wires": [ - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_WR1END0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_BYP2_0", - "CLK_FEED_R_CK_GCLK12", - "CLK_PMV_BYP6_0", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_GCLK12", - "CLK_PMV_BYP5_0", - "CLK_FEED_R_CK_GCLK15", - "CLK_PMV_IMUX27_0", - "CLK_FEED_EE4BEG0", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2END3", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_EE4A2", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_NW4A0", - "CLK_FEED_WW4C1", - "CLK_FEED_LH6", - "CLK_FEED_EL1BEG0", - "CLK_FEED_WW4B1", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_WR1END1", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_EL1BEG1", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_EE4A1", - "CLK_FEED_WW4END1", - "CLK_PMV_IMUX41_0", - "CLK_FEED_R_CK_GCLK23", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_FEED_R_CK_GCLK28", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_IMUX7_0", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX46_0", - "CLK_FEED_EL1BEG2", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK4", - "CLK_PMV_FAN5_0", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX17_0", - "CLK_FEED_WW4A1", - "CLK_FEED_CK_GCLK0", - "CLK_PMV_IMUX35_0", - "CLK_FEED_EE2A0", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_LH8", - "CLK_FEED_SW4A0", - "CLK_FEED_NE4C3", - "CLK_FEED_SE2A1", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_NE4BEG0", - "CLK_FEED_SE4C0", - "CLK_FEED_EE2A2", - "CLK_PMV_IMUX43_0", - "CLK_FEED_NE4BEG3", - "CLK_FEED_WW4END2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_PMV_CLK1_0", - "CLK_FEED_CK_GCLK8", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_PMVIOB_O", - "CLK_PMV_IMUX34_0", - "CLK_FEED_EL1BEG3", - "CLK_FEED_NE4BEG2", - "CLK_PMV_FAN6_0", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_WR1END3", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_SW2A2", - "CLK_FEED_LH9", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_R_CK_GCLK20", - "CLK_PMV_IMUX40_0", - "CLK_FEED_WW4A2", - "CLK_PMV_IMUX24_0", - "CLK_FEED_R_CK_GCLK5", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX5_0", - "CLK_FEED_SE2A0", - "CLK_FEED_NW4END2", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_PMV_CLK0_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_FEED_WW2A0", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_LH3", - "CLK_FEED_MONITOR_N", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_NW4END0", - "CLK_PMVIOB_ODIV2", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_EE4B0", - "CLK_FEED_LH11", - "CLK_PMV_FAN4_0", - "CLK_FEED_NW2A0", - "CLK_FEED_SW4A2", - "CLK_FEED_NW4A2", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_WW4END0", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_WW2END2", - "CLK_FEED_EE2A1", - "CLK_FEED_NE2A0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_EE4A3", - "CLK_FEED_LH12", - "CLK_FEED_EE2BEG3", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_SE4BEG2", - "CLK_FEED_LH7", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_NW4END3", - "CLK_PMV_FAN0_0", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_PMV_IMUX15_0", - "CLK_FEED_EE4C0", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX47_0", - "CLK_FEED_R_CK_GCLK2", - "CLK_PMV_BYP0_0", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_EE2BEG2", - "CLK_PMVIOB_ODIV4", - "CLK_PMV_IMUX29_0", - "CLK_FEED_EE4BEG1", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX1_0", - "CLK_FEED_LH2", - "CLK_PMV_FAN3_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_FAN2_0", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_WW4A0", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_PMV_IMUX39_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_SW4END1", - "CLK_FEED_WW2A3", - "CLK_FEED_SE2A2", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_SE4C1", - "CLK_FEED_SW2A0", - "CLK_FEED_EE2A3", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_WW4END3", - "CLK_FEED_CK_GCLK5", - "CLK_PMV_IMUX38_0", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_PMV_IMUX22_0", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_SW4END0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_FAN7_0", - "CLK_FEED_EE4C2", - "CLK_FEED_LH10", - "CLK_PMV_IMUX28_0", - "CLK_FEED_NE4C1", - "CLK_FEED_ER1BEG0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_CTRL0_0", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_SE4BEG1", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_LH1", - "CLK_FEED_WL1END0", - "CLK_FEED_SW4A3", - "CLK_PMV_IMUX6_0", - "CLK_FEED_CK_GCLK13", - "CLK_PMV_IMUX33_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_FEED_CK_GCLK11", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_FEED_LH4", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_NE4C0", - "CLK_FEED_NE2A2", - "CLK_PMV_IMUX9_0", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_NE4BEG1", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_PMV_BYP3_0", - "CLK_FEED_CK_GCLK30", - "CLK_PMV_IMUX31_0", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4C3", - "CLK_FEED_EE4C1", - "CLK_PMVIOB_A0", - "CLK_FEED_WW4C2", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_ER1BEG2", - "CLK_FEED_WL1END3", - "CLK_FEED_SE2A3", - "CLK_PMV_FAN1_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_EE4BEG2", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_PMV_IMUX8_0", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_WW4B2", - "CLK_PMV_IMUX26_0", - "CLK_FEED_SE4C2", - "CLK_FEED_CK_GCLK10", - "CLK_PMV_BYP4_0", - "CLK_FEED_R_CK_GCLK30", - "CLK_PMV_BYP1_0", - "CLK_PMV_IMUX20_0", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_SE4C3", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_FEED_CK_GCLK19", - "CLK_PMVIOB_A1", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_FEED_NW2A1", - "CLK_PMV_IMUX21_0", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_EE4BEG3", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_NW2A2", - "CLK_PMV_IMUX12_0", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_PMVIOB_EN", - "CLK_FEED_CK_GCLK14", - "CLK_PMV_IMUX36_0", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_PMV_IMUX30_0", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_SW2A1", - "CLK_PMV_IMUX4_0", - "CLK_FEED_EE2BEG0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A3", - "CLK_FEED_R_CK_GCLK26", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_LH5", - "CLK_FEED_EE4C3", - "CLK_FEED_WR1END2", - "CLK_PMV_BYP7_0", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_CK_GCLK22", - "CLK_PMV_LOGIC_OUTS9_0", - "CLK_FEED_SW4A1", - "CLK_FEED_NE4C2", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_PMV_IMUX18_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_WL1END2", - "CLK_FEED_CK_GCLK2", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX2_0", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_WW4C0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX37_0", - "CLK_FEED_SW2A3", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_GCLK10", - "CLK_PMV_IMUX25_0", - "CLK_FEED_WW4A3", - "CLK_FEED_WW2END1", - "CLK_PMV_IMUX23_0", - "CLK_FEED_CK_GCLK20", - "CLK_PMV_IMUX32_0", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_NW2A3", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_WW2A1", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_WW4B3", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4END1", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_EE4B1", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_NE2A1", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_EE4A0", - "CLK_FEED_WL1END1", - "CLK_FEED_EE2BEG1", - "CLK_FEED_WW2END0", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_SE4BEG0" - ], - "sites": [], "pips": {}, - "tile_type": "CLK_PMVIOB" + "wires": [ + "CLK_FEED_CK_GCLK13", + "CLK_FEED_CK_BUFG_CASC3", + "CLK_FEED_WW4B2", + "CLK_FEED_EE4B2", + "CLK_FEED_CK_GCLK26", + "CLK_FEED_WW2A0", + "CLK_PMV_BYP3_0", + "CLK_FEED_EE4A2", + "CLK_FEED_R_CK_BUFG_CASC25", + "CLK_PMV_FAN5_0", + "CLK_FEED_R_CK_GCLK4", + "CLK_FEED_R_CK_BUFG_CASC4", + "CLK_PMV_LOGIC_OUTS18_0", + "CLK_PMV_FAN1_0", + "CLK_FEED_EE4BEG1", + "CLK_FEED_CK_GCLK29", + "CLK_PMV_IMUX46_0", + "CLK_PMVIOB_EN", + "CLK_FEED_WW4C0", + "CLK_FEED_EE4BEG2", + "CLK_PMV_BYP0_0", + "CLK_PMV_LOGIC_OUTS8_0", + "CLK_FEED_CK_GCLK19", + "CLK_FEED_CK_BUFG_CASC22", + "CLK_PMV_IMUX44_0", + "CLK_FEED_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC29", + "CLK_PMV_IMUX36_0", + "CLK_FEED_SW4END1", + "CLK_PMV_BYP5_0", + "CLK_PMV_IMUX2_0", + "CLK_FEED_LH12", + "CLK_PMV_IMUX5_0", + "CLK_FEED_CK_BUFG_CASC13", + "CLK_FEED_CK_BUFG_CASC7", + "CLK_FEED_WW4END3", + "CLK_FEED_SE4C1", + "CLK_FEED_CK_GCLK9", + "CLK_PMV_LOGIC_OUTS17_0", + "CLK_PMV_IMUX25_0", + "CLK_FEED_EE4C3", + "CLK_FEED_R_CK_BUFG_CASC22", + "CLK_FEED_WW2END0", + "CLK_FEED_CK_GCLK2", + "CLK_FEED_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_GCLK11", + "CLK_FEED_CK_GCLK15", + "CLK_PMV_LOGIC_OUTS5_0", + "CLK_PMV_CTRL0_0", + "CLK_FEED_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC16", + "CLK_PMV_FAN0_0", + "CLK_PMV_IMUX43_0", + "CLK_FEED_NE4BEG0", + "CLK_FEED_SE4BEG3", + "CLK_FEED_WW4A2", + "CLK_FEED_SE4BEG1", + "CLK_FEED_CK_GCLK0", + "CLK_FEED_WW2A2", + "CLK_FEED_R_CK_GCLK13", + "CLK_FEED_R_CK_BUFG_CASC24", + "CLK_PMV_IMUX17_0", + "CLK_FEED_R_CK_BUFG_CASC13", + "CLK_FEED_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC11", + "CLK_FEED_EE4BEG0", + "CLK_PMV_IMUX13_0", + "CLK_FEED_CK_GCLK11", + "CLK_PMV_IMUX20_0", + "CLK_FEED_CK_GCLK27", + "CLK_FEED_CK_BUFG_CASC2", + "CLK_FEED_CK_GCLK3", + "CLK_FEED_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK0", + "CLK_FEED_LH10", + "CLK_PMV_IMUX22_0", + "CLK_FEED_SE4C0", + "CLK_FEED_LH3", + "CLK_PMV_LOGIC_OUTS10_0", + "CLK_PMV_IMUX7_0", + "CLK_PMV_IMUX31_0", + "CLK_FEED_WW2A3", + "CLK_FEED_NW4A1", + "CLK_FEED_R_CK_BUFG_CASC14", + "CLK_PMV_IMUX28_0", + "CLK_FEED_R_CK_BUFG_CASC30", + "CLK_FEED_LH5", + "CLK_FEED_NW4A2", + "CLK_PMV_BYP1_0", + "CLK_PMVIOB_O", + "CLK_FEED_WW4END1", + "CLK_FEED_EE2BEG2", + "CLK_FEED_WL1END0", + "CLK_FEED_NE4BEG3", + "CLK_PMV_IMUX42_0", + "CLK_PMVIOB_A1", + "CLK_PMV_FAN3_0", + "CLK_FEED_WL1END1", + "CLK_FEED_SW2A1", + "CLK_PMV_LOGIC_OUTS6_0", + "CLK_FEED_EE2BEG0", + "CLK_FEED_CK_GCLK7", + "CLK_PMV_IMUX40_0", + "CLK_FEED_CK_GCLK22", + "CLK_FEED_EE4A1", + "CLK_FEED_EE4BEG3", + "CLK_FEED_R_CK_BUFG_CASC20", + "CLK_FEED_CK_BUFG_CASC8", + "CLK_FEED_EE2BEG1", + "CLK_FEED_SW4END0", + "CLK_FEED_CK_BUFG_CASC12", + "CLK_FEED_SE4BEG2", + "CLK_FEED_NE2A3", + "CLK_FEED_LH8", + "CLK_FEED_R_CK_BUFG_CASC0", + "CLK_PMV_LOGIC_OUTS13_0", + "CLK_PMV_IMUX29_0", + "CLK_FEED_WR1END1", + "CLK_FEED_NE4BEG2", + "CLK_FEED_R_CK_GCLK25", + "CLK_FEED_WW4END2", + "CLK_FEED_SW4A3", + "CLK_PMV_IMUX26_0", + "CLK_FEED_LH11", + "CLK_PMV_IMUX0_0", + "CLK_PMV_IMUX11_0", + "CLK_FEED_EE4C1", + "CLK_PMV_LOGIC_OUTS16_0", + "CLK_PMV_IMUX15_0", + "CLK_FEED_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK27", + "CLK_FEED_NE4C0", + "CLK_FEED_CK_GCLK24", + "CLK_FEED_CK_GCLK14", + "CLK_FEED_R_CK_BUFG_CASC9", + "CLK_FEED_SE4C2", + "CLK_PMV_LOGIC_OUTS4_0", + "CLK_FEED_R_CK_BUFG_CASC1", + "CLK_FEED_ER1BEG1", + "CLK_PMV_IMUX41_0", + "CLK_FEED_R_CK_GCLK6", + "CLK_FEED_MONITOR_P", + "CLK_FEED_CK_GCLK1", + "CLK_FEED_R_CK_BUFG_CASC18", + "CLK_PMV_IMUX45_0", + "CLK_PMV_IMUX8_0", + "CLK_FEED_WW4C3", + "CLK_PMV_LOGIC_OUTS12_0", + "CLK_FEED_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK24", + "CLK_FEED_WW2END2", + "CLK_FEED_SE2A1", + "CLK_FEED_WW4A3", + "CLK_FEED_CK_GCLK8", + "CLK_FEED_CK_GCLK20", + "CLK_FEED_CK_BUFG_CASC10", + "CLK_PMV_LOGIC_OUTS23_0", + "CLK_FEED_CK_BUFG_CASC0", + "CLK_FEED_EL1BEG1", + "CLK_PMV_IMUX34_0", + "CLK_FEED_R_CK_GCLK12", + "CLK_FEED_CK_GCLK6", + "CLK_FEED_R_CK_GCLK8", + "CLK_FEED_R_CK_BUFG_CASC27", + "CLK_FEED_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC26", + "CLK_FEED_EE2BEG3", + "CLK_FEED_LH7", + "CLK_PMV_LOGIC_OUTS1_0", + "CLK_FEED_SW4A0", + "CLK_FEED_CK_BUFG_CASC9", + "CLK_PMV_FAN7_0", + "CLK_PMV_LOGIC_OUTS20_0", + "CLK_FEED_LH9", + "CLK_FEED_SW4A2", + "CLK_FEED_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK28", + "CLK_PMV_LOGIC_OUTS14_0", + "CLK_FEED_R_CK_BUFG_CASC28", + "CLK_FEED_CK_GCLK21", + "CLK_FEED_MONITOR_N", + "CLK_PMV_LOGIC_OUTS3_0", + "CLK_FEED_EE4B3", + "CLK_PMV_IMUX24_0", + "CLK_PMV_IMUX1_0", + "CLK_PMV_LOGIC_OUTS15_0", + "CLK_FEED_NE2A1", + "CLK_FEED_CK_GCLK25", + "CLK_PMV_FAN2_0", + "CLK_FEED_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC7", + "CLK_FEED_SW4END2", + "CLK_PMV_BYP4_0", + "CLK_PMV_CLK1_0", + "CLK_PMV_IMUX32_0", + "CLK_PMV_IMUX9_0", + "CLK_FEED_EE2A1", + "CLK_FEED_SE2A3", + "CLK_FEED_SW2A0", + "CLK_FEED_NE2A2", + "CLK_FEED_R_CK_GCLK17", + "CLK_FEED_CK_BUFG_CASC20", + "CLK_FEED_WW4C2", + "CLK_FEED_NE4BEG1", + "CLK_FEED_CK_GCLK12", + "CLK_FEED_R_CK_GCLK23", + "CLK_FEED_NW2A1", + "CLK_FEED_EE4B0", + "CLK_FEED_NE4C2", + "CLK_PMV_IMUX10_0", + "CLK_FEED_R_CK_GCLK15", + "CLK_FEED_WW4B0", + "CLK_PMV_LOGIC_OUTS9_0", + "CLK_FEED_CK_BUFG_CASC19", + "CLK_PMV_BYP2_0", + "CLK_FEED_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_GCLK20", + "CLK_PMV_LOGIC_OUTS2_0", + "CLK_FEED_WW2END1", + "CLK_FEED_R_CK_BUFG_CASC3", + "CLK_PMV_LOGIC_OUTS7_0", + "CLK_FEED_CK_BUFG_CASC25", + "CLK_PMV_FAN6_0", + "CLK_PMV_IMUX37_0", + "CLK_FEED_NW2A3", + "CLK_FEED_R_CK_GCLK1", + "CLK_FEED_WR1END0", + "CLK_FEED_EE4A3", + "CLK_FEED_R_CK_GCLK10", + "CLK_FEED_R_CK_BUFG_CASC17", + "CLK_FEED_NW2A2", + "CLK_PMV_IMUX4_0", + "CLK_FEED_LH4", + "CLK_FEED_EE2A0", + "CLK_PMV_IMUX35_0", + "CLK_PMV_IMUX16_0", + "CLK_FEED_ER1BEG2", + "CLK_FEED_ER1BEG3", + "CLK_FEED_WW4A0", + "CLK_FEED_CK_BUFG_CASC18", + "CLK_FEED_WR1END3", + "CLK_PMVIOB_ODIV4", + "CLK_FEED_LH1", + "CLK_FEED_EE2A3", + "CLK_FEED_NW4A3", + "CLK_FEED_WW2END3", + "CLK_FEED_CK_BUFG_CASC27", + "CLK_FEED_SE4C3", + "CLK_PMV_IMUX23_0", + "CLK_PMV_IMUX38_0", + "CLK_PMV_IMUX12_0", + "CLK_FEED_CK_BUFG_CASC1", + "CLK_FEED_NW4END2", + "CLK_FEED_EE4C0", + "CLK_FEED_CK_GCLK10", + "CLK_FEED_R_CK_GCLK30", + "CLK_FEED_WL1END3", + "CLK_FEED_NW2A0", + "CLK_FEED_ER1BEG0", + "CLK_FEED_NW4A0", + "CLK_FEED_WW4A1", + "CLK_FEED_R_CK_BUFG_CASC23", + "CLK_FEED_CK_BUFG_CASC15", + "CLK_FEED_LH2", + "CLK_FEED_SW2A2", + "CLK_PMV_BYP6_0", + "CLK_FEED_R_CK_BUFG_CASC2", + "CLK_PMV_IMUX3_0", + "CLK_FEED_CK_GCLK31", + "CLK_FEED_CK_GCLK18", + "CLK_PMVIOB_ODIV2", + "CLK_FEED_R_CK_GCLK3", + "CLK_FEED_LH6", + "CLK_FEED_CK_GCLK4", + "CLK_FEED_R_CK_GCLK2", + "CLK_PMV_IMUX21_0", + "CLK_FEED_NW4END3", + "CLK_FEED_NE4C1", + "CLK_FEED_CK_BUFG_CASC31", + "CLK_FEED_R_CK_GCLK7", + "CLK_FEED_WW2A1", + "CLK_FEED_R_CK_GCLK16", + "CLK_PMV_IMUX33_0", + "CLK_PMV_IMUX18_0", + "CLK_FEED_SE4BEG0", + "CLK_FEED_WL1END2", + "CLK_FEED_NW4END1", + "CLK_FEED_NW4END0", + "CLK_PMV_LOGIC_OUTS11_0", + "CLK_FEED_SE2A0", + "CLK_FEED_CK_GCLK5", + "CLK_FEED_CK_BUFG_CASC4", + "CLK_FEED_WR1END2", + "CLK_FEED_SW4END3", + "CLK_FEED_WW4END0", + "CLK_PMV_CTRL1_0", + "CLK_PMV_LOGIC_OUTS21_0", + "CLK_FEED_EE4B1", + "CLK_FEED_SW4A1", + "CLK_FEED_CK_GCLK28", + "CLK_FEED_NE4C3", + "CLK_FEED_CK_BUFG_CASC17", + "CLK_FEED_CK_GCLK23", + "CLK_PMV_IMUX19_0", + "CLK_FEED_R_CK_GCLK18", + "CLK_FEED_EE2A2", + "CLK_FEED_R_CK_GCLK19", + "CLK_FEED_CK_BUFG_CASC6", + "CLK_FEED_CK_BUFG_CASC16", + "CLK_FEED_NE2A0", + "CLK_PMV_LOGIC_OUTS0_0", + "CLK_FEED_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC8", + "CLK_PMV_IMUX6_0", + "CLK_PMV_IMUX39_0", + "CLK_FEED_SE2A2", + "CLK_FEED_R_CK_GCLK22", + "CLK_FEED_SW2A3", + "CLK_FEED_EE4A0", + "CLK_FEED_CK_GCLK30", + "CLK_PMV_CLK0_0", + "CLK_FEED_EL1BEG3", + "CLK_FEED_WW4C1", + "CLK_PMV_FAN4_0", + "CLK_FEED_R_CK_GCLK26", + "CLK_PMV_LOGIC_OUTS22_0", + "CLK_FEED_CK_BUFG_CASC28", + "CLK_FEED_EL1BEG0", + "CLK_PMV_IMUX47_0", + "CLK_FEED_R_CK_GCLK31", + "CLK_PMV_LOGIC_OUTS19_0", + "CLK_PMV_IMUX30_0", + "CLK_PMV_IMUX27_0", + "CLK_FEED_CK_BUFG_CASC24", + "CLK_FEED_EE4C2", + "CLK_FEED_R_CK_GCLK9", + "CLK_FEED_R_CK_BUFG_CASC12", + "CLK_PMV_IMUX14_0", + "CLK_FEED_WW4B3", + "CLK_FEED_CK_BUFG_CASC30", + "CLK_FEED_CK_BUFG_CASC14", + "CLK_PMV_BYP7_0", + "CLK_FEED_EL1BEG2", + "CLK_PMVIOB_A0", + "CLK_FEED_CK_BUFG_CASC29", + "CLK_FEED_CK_GCLK16", + "CLK_FEED_R_CK_GCLK14", + "CLK_FEED_WW4B1" + ], + "tile_type": "CLK_PMVIOB", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CLK_TERM.json b/artix7/tile_type_CLK_TERM.json index 8075954..93fee4c 100644 --- a/artix7/tile_type_CLK_TERM.json +++ b/artix7/tile_type_CLK_TERM.json @@ -1,71 +1,71 @@ { - "wires": [ - "CLK_TERM_R_GCLK24", - "CLK_TERM_GCLK1", - "CLK_TERM_GCLK15", - "CLK_TERM_R_GCLK18", - "CLK_TERM_GCLK24", - "CLK_TERM_GCLK20", - "CLK_TERM_GCLK6", - "CLK_TERM_GCLK2", - "CLK_TERM_GCLK18", - "CLK_TERM_R_GCLK7", - "CLK_TERM_R_GCLK29", - "CLK_TERM_GCLK31", - "CLK_TERM_R_GCLK10", - "CLK_TERM_R_GCLK9", - "CLK_TERM_R_GCLK13", - "CLK_TERM_R_GCLK19", - "CLK_TERM_GCLK8", - "CLK_TERM_GCLK0", - "CLK_TERM_GCLK27", - "CLK_TERM_GCLK29", - "CLK_TERM_R_GCLK17", - "CLK_TERM_GCLK9", - "CLK_TERM_R_GCLK22", - "CLK_TERM_R_GCLK30", - "CLK_TERM_GCLK3", - "CLK_TERM_R_GCLK1", - "CLK_TERM_R_GCLK15", - "CLK_TERM_R_GCLK25", - "CLK_TERM_GCLK26", - "CLK_TERM_GCLK23", - "CLK_TERM_GCLK12", - "CLK_TERM_R_GCLK5", - "CLK_TERM_GCLK17", - "CLK_TERM_R_GCLK23", - "CLK_TERM_GCLK30", - "CLK_TERM_GCLK25", - "CLK_TERM_R_GCLK2", - "CLK_TERM_GCLK4", - "CLK_TERM_R_GCLK28", - "CLK_TERM_R_GCLK6", - "CLK_TERM_R_GCLK11", - "CLK_TERM_GCLK7", - "CLK_TERM_R_GCLK0", - "CLK_TERM_R_GCLK12", - "CLK_TERM_GCLK5", - "CLK_TERM_GCLK22", - "CLK_TERM_GCLK16", - "CLK_TERM_GCLK13", - "CLK_TERM_R_GCLK20", - "CLK_TERM_R_GCLK8", - "CLK_TERM_R_GCLK14", - "CLK_TERM_R_GCLK26", - "CLK_TERM_GCLK11", - "CLK_TERM_GCLK10", - "CLK_TERM_GCLK19", - "CLK_TERM_R_GCLK16", - "CLK_TERM_R_GCLK31", - "CLK_TERM_GCLK14", - "CLK_TERM_R_GCLK27", - "CLK_TERM_R_GCLK4", - "CLK_TERM_GCLK28", - "CLK_TERM_GCLK21", - "CLK_TERM_R_GCLK21", - "CLK_TERM_R_GCLK3" - ], - "sites": [], "pips": {}, - "tile_type": "CLK_TERM" + "wires": [ + "CLK_TERM_R_GCLK17", + "CLK_TERM_R_GCLK20", + "CLK_TERM_R_GCLK21", + "CLK_TERM_R_GCLK16", + "CLK_TERM_R_GCLK12", + "CLK_TERM_R_GCLK5", + "CLK_TERM_R_GCLK26", + "CLK_TERM_R_GCLK4", + "CLK_TERM_R_GCLK8", + "CLK_TERM_R_GCLK10", + "CLK_TERM_GCLK26", + "CLK_TERM_GCLK30", + "CLK_TERM_R_GCLK19", + "CLK_TERM_R_GCLK25", + "CLK_TERM_R_GCLK1", + "CLK_TERM_R_GCLK3", + "CLK_TERM_GCLK13", + "CLK_TERM_GCLK3", + "CLK_TERM_GCLK23", + "CLK_TERM_GCLK14", + "CLK_TERM_GCLK18", + "CLK_TERM_GCLK22", + "CLK_TERM_GCLK8", + "CLK_TERM_GCLK15", + "CLK_TERM_GCLK31", + "CLK_TERM_GCLK0", + "CLK_TERM_R_GCLK28", + "CLK_TERM_R_GCLK11", + "CLK_TERM_R_GCLK13", + "CLK_TERM_R_GCLK14", + "CLK_TERM_GCLK21", + "CLK_TERM_R_GCLK29", + "CLK_TERM_R_GCLK7", + "CLK_TERM_GCLK27", + "CLK_TERM_GCLK4", + "CLK_TERM_GCLK7", + "CLK_TERM_GCLK6", + "CLK_TERM_GCLK5", + "CLK_TERM_R_GCLK15", + "CLK_TERM_R_GCLK22", + "CLK_TERM_GCLK29", + "CLK_TERM_R_GCLK18", + "CLK_TERM_GCLK12", + "CLK_TERM_GCLK9", + "CLK_TERM_GCLK20", + "CLK_TERM_GCLK19", + "CLK_TERM_GCLK2", + "CLK_TERM_GCLK24", + "CLK_TERM_R_GCLK6", + "CLK_TERM_R_GCLK31", + "CLK_TERM_GCLK16", + "CLK_TERM_R_GCLK0", + "CLK_TERM_GCLK1", + "CLK_TERM_GCLK25", + "CLK_TERM_R_GCLK23", + "CLK_TERM_R_GCLK24", + "CLK_TERM_R_GCLK27", + "CLK_TERM_R_GCLK30", + "CLK_TERM_R_GCLK9", + "CLK_TERM_GCLK11", + "CLK_TERM_R_GCLK2", + "CLK_TERM_GCLK17", + "CLK_TERM_GCLK10", + "CLK_TERM_GCLK28" + ], + "tile_type": "CLK_TERM", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_FIFO_L.json b/artix7/tile_type_CMT_FIFO_L.json index 1ea3c85..48d0045 100644 --- a/artix7/tile_type_CMT_FIFO_L.json +++ b/artix7/tile_type_CMT_FIFO_L.json @@ -1,5261 +1,5261 @@ { - "wires": [ - "CMT_FIFO_WW2A1_11", - "CMT_FIFO_MONITOR_N_9", - "CMT_FIFO_L_CTRL0_5", - "CMT_FIFO_EE4B1_2", - "CMT_FIFO_L_IMUX38_7", - "CMT_FIFO_EE2A0_10", - "CMT_FIFO_L_IMUX17_5", - "CMT_FIFO_NW2A3_0", - "CMT_FIFO_WW4B0_5", - "CMT_FIFO_SW4A3_4", - "CMT_OUT_FIFO_Q22", - "CMT_FIFO_WR1END1_9", - "CMT_FIFO_WR1END1_0", - "CMT_FIFO_L_IMUX47_10", - "CMT_FIFO_L_IMUX40_9", - "CMT_FIFO_WR1END2_4", - "CMT_FIFO_NE2A0_10", - "CMT_OUT_FIFO_D51", - "CMT_FIFO_SW4END1_11", - "CMT_FIFO_L_IMUX11_0", - "CMT_FIFO_EE4B1_11", - "CMT_FIFO_L_IMUX25_0", - "CMT_FIFO_WW4END3_6", - "CMT_OUT_FIFO_TESTWRITEDISB", - "CMT_FIFO_L_LOGIC_OUTS18_5", - "CMT_FIFO_EE2BEG2_11", - "CMT_FIFO_SE2A3_0", - "CMT_FIFO_LH7_3", - "CMT_FIFO_WW4C2_0", - "CMT_FIFO_NE4C3_5", - "CMT_FIFO_SW2A2_8", - "CMT_FIFO_L_BYP1_3", - "CMT_FIFO_L_IMUX13_2", - "CMT_FIFO_L_CLK0_1", - "CMT_FIFO_LH7_8", - "CMT_FIFO_WW2END2_1", - "CMT_FIFO_L_IMUX0_4", - "CMT_FIFO_EE2BEG0_3", - "CMT_FIFO_EE4BEG2_7", - "CMT_FIFO_NW4A0_11", - "CMT_FIFO_SE4C0_1", - "CMT_FIFO_EE4BEG0_10", - "CMT_FIFO_EE4A2_2", - "CMT_FIFO_WW4C2_11", - "CMT_FIFO_L_IMUX4_7", - "CMT_FIFO_NW4END0_7", - "CMT_FIFO_L_LOGIC_OUTS18_0", - "CMT_FIFO_NW4END0_8", - "CMT_FIFO_L_IMUX22_5", - "CMT_OUT_FIFO_D63", - "CMT_FIFO_L_IMUX30_2", - "CMT_FIFO_EE4B0_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_9", - "CMT_FIFO_L_IMUX14_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", - "CMT_FIFO_LH3_8", - "CMT_FIFO_SW4END2_6", - "CMT_FIFO_L_LOGIC_OUTS22_7", - "CMT_FIFO_L_LOGIC_OUTS16_2", - "CMT_FIFO_EE4C0_9", - "CMT_FIFO_L_IMUX39_5", - "CMT_FIFO_L_LOGIC_OUTS14_3", - "CMT_FIFO_L_IMUX2_7", - "CMT_FIFO_L_CLK1_3", - "CMT_IN_FIFO_Q61", - "CMT_FIFO_L_LOGIC_OUTS19_2", - "CMT_FIFO_L_BYP6_5", - "CMT_FIFO_L_IMUX37_0", - "CMT_FIFO_EE2BEG2_3", - "CMT_FIFO_L_FAN0_10", - "CMT_FIFO_L_IMUX38_2", - "CMT_OUT_FIFO_D03", - "CMT_FIFO_L_IMUX37_11", - "CMT_FIFO_L_LOGIC_OUTS3_5", - "CMT_FIFO_EE4B1_9", - "CMT_FIFO_EE4C0_5", - "CMT_FIFO_WW4B2_0", - "CMT_FIFO_L_IMUX21_1", - "CMT_FIFO_SE2A3_6", - "CMT_FIFO_NW4END3_1", - "CMT_FIFO_LH7_2", - "CMT_FIFO_NE4BEG3_2", - "CMT_FIFO_L_IMUX34_4", - "CMT_FIFO_L_IMUX10_1", - "CMT_FIFO_L_LOGIC_OUTS12_7", - "CMT_FIFO_L_IMUX40_7", - "CMT_FIFO_EE2BEG2_4", - "CMT_FIFO_EE4B1_6", - "CMT_FIFO_L_LOGIC_OUTS11_5", - "CMT_OUT_FIFO_Q71", - "CMT_FIFO_NW2A2_3", - "CMT_FIFO_L_IMUX2_3", - "CMT_FIFO_NE4C2_5", - "CMT_FIFO_L_IMUX47_7", - "CMT_FIFO_EE4BEG0_4", - "CMT_FIFO_SE2A1_2", - "CMT_FIFO_L_BYP0_8", - "CMT_FIFO_EE2A0_8", - "CMT_FIFO_NE4C0_3", - "CMT_FIFO_NW4END2_0", - "CMT_FIFO_LH10_2", - "CMT_FIFO_EE4BEG3_4", - "CMT_FIFO_EE4A0_10", - "CMT_OUT_FIFO_SCANIN0", - "CMT_FIFO_NE4C2_2", - "CMT_FIFO_L_CLK0_6", - "CMT_FIFO_WW2END0_5", - "CMT_FIFO_L_IMUX18_3", - "CMT_FIFO_L_FAN7_7", - "CMT_FIFO_L_LOGIC_OUTS16_0", - "CMT_FIFO_EL1BEG3_10", - "CMT_IN_FIFO_Q66", - "CMT_FIFO_L_IMUX42_1", - "CMT_FIFO_WL1END3_2", - "CMT_FIFO_SW4A2_10", - "CMT_FIFO_EE2BEG2_2", - "CMT_OUT_FIFO_D65", - "CMT_FIFO_L_IMUX22_7", - "CMT_FIFO_ER1BEG1_2", - "CMT_FIFO_EE4C3_6", - "CMT_FIFO_LH1_7", - "CMT_FIFO_L_IMUX3_4", - "CMT_FIFO_L_LOGIC_OUTS13_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_5", - "CMT_FIFO_WR1END1_8", - "CMT_FIFO_ER1BEG1_0", - "CMT_FIFO_L_IMUX41_1", - "CMT_FIFO_EE2A0_7", - "CMT_FIFO_SE4C0_0", - "CMT_FIFO_L_IMUX21_4", - "CMT_FIFO_L_BYP4_2", - "CMT_FIFO_LH11_10", - "CMT_FIFO_WR1END0_3", - "CMT_FIFO_L_IMUX12_2", - "CMT_FIFO_LH12_4", - "CMT_FIFO_WR1END1_10", - "CMT_FIFO_SE4C1_2", - "CMT_FIFO_EE4B2_0", - "CMT_FIFO_NE2A2_5", - "CMT_FIFO_WW4A0_2", - "CMT_FIFO_L_IMUX14_3", - "CMT_FIFO_NE4C2_10", - "CMT_FIFO_L_LOGIC_OUTS18_11", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", - "CMT_FIFO_SW4A1_5", - "CMT_OUT_FIFO_Q72", - "CMT_FIFO_WL1END1_8", - "CMT_FIFO_LH2_0", - "CMT_FIFO_L_IMUX46_5", - "CMT_FIFO_SE4C2_4", - "CMT_FIFO_L_IMUX12_5", - "CMT_FIFO_L_BYP6_6", - "CMT_FIFO_L_IMUX19_9", - "CMT_FIFO_WR1END3_3", - "CMT_IN_FIFO_D12", - "CMT_FIFO_EE4BEG3_10", - "CMT_FIFO_SE2A0_9", - "CMT_FIFO_SE4C1_6", - "CMT_FIFO_EE4BEG2_4", - "CMT_OUT_FIFO_ALMOSTEMPTY", - "CMT_FIFO_WW4C1_2", - "CMT_FIFO_WW4C1_8", - "CMT_FIFO_WL1END0_2", - "CMT_FIFO_EE4B3_4", - "CMT_FIFO_L_LOGIC_OUTS5_2", - "CMT_IN_FIFO_Q41", - "CMT_FIFO_SW4A2_4", - "CMT_IN_FIFO_Q53", - "CMT_FIFO_EE4C0_11", - "CMT_OUT_FIFO_Q51", - "CMT_FIFO_L_BYP6_11", - "CMT_FIFO_WW4A1_9", - "CMT_FIFO_WW4END1_8", - "CMT_FIFO_SE2A0_7", - "CMT_FIFO_L_LOGIC_OUTS2_7", - "CMT_FIFO_L_CLK0_11", - "CMT_FIFO_NW4END2_6", - "CMT_FIFO_SW2A0_7", - "CMT_FIFO_L_LOGIC_OUTS23_2", - "CMT_FIFO_L_LOGIC_OUTS23_11", - "CMT_FIFO_L_LOGIC_OUTS23_10", - "CMT_FIFO_LH12_8", - "CMT_OUT_FIFO_RDCLK", - "CMT_FIFO_EL1BEG2_3", - "CMT_FIFO_SE2A2_8", - "CMT_FIFO_L_FAN5_8", - "CMT_FIFO_WW4A2_8", - "CMT_FIFO_L_IMUX38_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", - "CMT_FIFO_L_IMUX29_11", - "CMT_FIFO_SW2A2_9", - "CMT_FIFO_NE4C3_6", - "CMT_FIFO_EE4BEG0_0", - "CMT_FIFO_L_IMUX42_3", - "CMT_FIFO_SW4A1_11", - "CMT_FIFO_NW2A0_3", - "CMT_FIFO_LH11_7", - "CMT_FIFO_NW4A2_6", - "CMT_FIFO_WW2END2_11", - "CMT_FIFO_L_IMUX44_3", - "CMT_FIFO_LH9_11", - "CMT_FIFO_WW2END3_2", - "CMT_OUT_FIFO_Q82", - "CMT_FIFO_LH10_8", - "CMT_FIFO_L_FAN4_7", - "CMT_FIFO_L_BYP2_9", - "CMT_FIFO_L_LOGIC_OUTS17_0", - "CMT_FIFO_LH4_0", - "CMT_FIFO_MONITOR_P_1", - "CMT_FIFO_SE4C2_8", - "CMT_FIFO_L_IMUX42_9", - "CMT_FIFO_SE4C0_4", - "CMT_FIFO_MONITOR_N_8", - "CMT_FIFO_WW4C0_4", - "CMT_FIFO_NW2A2_7", - "CMT_OUT_FIFO_D87", - "CMT_FIFO_NW2A0_5", - "CMT_FIFO_SW2A2_7", - "CMT_FIFO_EE4C3_9", - "CMT_FIFO_LH9_6", - "CMT_FIFO_L_LOGIC_OUTS21_1", - "CMT_FIFO_EE4C3_4", - "CMT_FIFO_SE4C0_7", - "CMT_FIFO_NW4A0_8", - "CMT_FIFO_L_CTRL1_3", - "CMT_FIFO_L_IMUX20_7", - "CMT_FIFO_L_LOGIC_OUTS19_8", - "CMT_FIFO_WR1END2_10", - "CMT_FIFO_NE2A0_8", - "CMT_FIFO_LH5_7", - "CMT_FIFO_L_FAN0_2", - "CMT_OUT_FIFO_D15", - "FIFO_DQS_IOTOPHASER_1", - "CMT_FIFO_EE4C1_3", - "CMT_FIFO_EE2BEG3_7", - "CMT_FIFO_SE2A0_11", - "CMT_FIFO_WW4END3_11", - "CMT_FIFO_SE4C3_0", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", - "CMT_IN_FIFO_Q90", - "CMT_FIFO_SE4BEG2_6", - "CMT_OUT_FIFO_D21", - "CMT_IN_FIFO_Q42", - "CMT_FIFO_L_IMUX25_5", - "CMT_FIFO_L_IMUX23_8", - "CMT_FIFO_L_IMUX5_9", - "CMT_FIFO_L_LOGIC_OUTS11_0", - "CMT_FIFO_SE4C1_10", - "CMT_FIFO_WW4END2_11", - "CMT_FIFO_L_LOGIC_OUTS7_0", - "CMT_FIFO_L_IMUX30_4", - "CMT_FIFO_EE4A3_3", - "CMT_FIFO_WW4A1_2", - "CMT_FIFO_WL1END3_6", - "CMT_FIFO_L_IMUX47_3", - "CMT_FIFO_EE4C1_9", - "CMT_FIFO_L_FAN6_5", - "CMT_FIFO_SE2A3_2", - "CMT_FIFO_L_BYP2_0", - "CMT_FIFO_L_BYP1_5", - "CMT_FIFO_LH7_10", - "CMT_FIFO_NE2A1_1", - "CMT_FIFO_WW2A0_2", - "CMT_FIFO_L_LOGIC_OUTS19_0", - "CMT_FIFO_NE2A1_3", - "CMT_FIFO_WW4END2_4", - "CMT_FIFO_WW4B3_1", - "CMT_FIFO_WW4END2_3", - "CMT_FIFO_WW4B2_7", - "CMT_FIFO_LH12_6", - "CMT_FIFO_EE4A1_3", - "CMT_FIFO_SW4END0_10", - "CMT_FIFO_SW2A0_10", - "CMT_FIFO_L_LOGIC_OUTS1_10", - "CMT_FIFO_L_CLK1_1", - "CMT_FIFO_L_FAN4_1", - "CMT_FIFO_L_FAN5_9", - "CMT_FIFO_EE4A0_4", - "CMT_FIFO_NE4C1_1", - "CMT_IN_FIFO_D03", - "CMT_FIFO_NE2A1_10", - "CMT_FIFO_L_LOGIC_OUTS1_5", - "CMT_FIFO_SE4BEG2_9", - "CMT_FIFO_EE4BEG2_2", - "CMT_IN_FIFO_Q80", - "CMT_FIFO_EL1BEG3_1", - "CMT_FIFO_NE4C3_4", - "CMT_FIFO_L_LOGIC_OUTS6_6", - "CMT_FIFO_NE4BEG2_7", - "CMT_FIFO_L_IMUX15_1", - "CMT_FIFO_WW2A1_10", - "CMT_FIFO_L_LOGIC_OUTS3_6", - "CMT_FIFO_SW2A2_2", - "CMT_FIFO_LH8_11", - "CMT_FIFO_L_BYP3_4", - "CMT_FIFO_WW2END1_10", - "CMT_FIFO_MONITOR_N_0", - "CMT_FIFO_L_IMUX41_3", - "CMT_OUT_FIFO_D70", - "CMT_FIFO_EE4A2_3", - "CMT_FIFO_WW2END2_10", - "CMT_IN_FIFO_Q15", - "CMT_FIFO_EE4A0_8", - "CMT_FIFO_WW4END1_3", - "CMT_FIFO_EE2BEG2_7", - "CMT_FIFO_L_BYP2_8", - "CMT_FIFO_L_IMUX12_11", - "CMT_FIFO_L_LOGIC_OUTS3_0", - "CMT_FIFO_L_LOGIC_OUTS18_2", - "CMT_FIFO_WW4END1_2", - "CMT_FIFO_L_BYP0_0", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", - "CMT_FIFO_L_IMUX23_6", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", - "CMT_FIFO_WW2A3_1", - "CMT_FIFO_L_IMUX14_4", - "CMT_FIFO_SW2A1_8", - "CMT_IN_FIFO_Q45", - "CMT_FIFO_SW2A0_11", - "CMT_FIFO_NW2A2_4", - "CMT_FIFO_NE4C2_8", - "CMT_FIFO_WW4B2_6", - "CMT_FIFO_EE2A1_7", - "CMT_FIFO_EE4BEG0_8", - "CMT_FIFO_L_IMUX19_2", - "CMT_FIFO_LH7_11", - "CMT_FIFO_L_LOGIC_OUTS9_7", - "CMT_FIFO_WW4C3_11", - "CMT_FIFO_LH7_1", - "CMT_FIFO_WW4B0_8", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", - "CMT_FIFO_L_IMUX21_3", - "CMT_FIFO_WW4A3_9", - "CMT_FIFO_L_IMUX11_8", - "FIFO_DQS_IOTOPHASER_2", - "CMT_FIFO_EE2A0_1", - "CMT_FIFO_WW4B2_1", - "CMT_FIFO_EE4B0_5", - "CMT_FIFO_ER1BEG3_8", - "CMT_FIFO_L_IMUX13_1", - "CMT_FIFO_WL1END2_6", - "CMT_FIFO_LH3_0", - "CMT_OUT_FIFO_D05", - "CMT_FIFO_L_LOGIC_OUTS6_7", - "CMT_FIFO_L_LOGIC_OUTS13_10", - "CMT_FIFO_WW2END0_6", - "CMT_FIFO_L_IMUX1_0", - "CMT_FIFO_SE2A2_3", - "CMT_IN_FIFO_Q62", - "CMT_FIFO_ER1BEG3_6", - "CMT_FIFO_L_IMUX28_10", - "CMT_FIFO_NW4A3_0", - "CMT_FIFO_L_LOGIC_OUTS18_3", - "CMT_FIFO_LH8_4", - "CMT_FIFO_WW4A3_6", - "CMT_FIFO_L_IMUX1_4", - "CMT_FIFO_L_IMUX19_10", - "CMT_FIFO_L_IMUX5_10", - "CMT_FIFO_L_FAN0_1", - "CMT_FIFO_NE2A2_8", - "CMT_FIFO_L_CTRL0_10", - "CMT_FIFO_L_LOGIC_OUTS9_9", - "CMT_OUT_FIFO_D01", - "CMT_FIFO_L_CTRL1_2", - "CMT_FIFO_NE2A3_0", - "CMT_FIFO_NE2A3_9", - "CMT_FIFO_L_IMUX11_1", - "CMT_FIFO_L_IMUX10_2", - "CMT_FIFO_L_LOGIC_OUTS13_1", - "CMT_FIFO_LH2_6", - "CMT_IN_FIFO_D02", - "CMT_FIFO_EE2BEG2_5", - "CMT_FIFO_EL1BEG0_4", - "CMT_FIFO_SE4BEG2_0", - "CMT_FIFO_WW2END1_9", - "CMT_FIFO_L_LOGIC_OUTS11_7", - "CMT_FIFO_WW2A3_11", - "CMT_FIFO_L_BYP3_11", - "CMT_FIFO_WW2END1_6", - "CMT_FIFO_WW2A1_3", - "CMT_FIFO_L_IMUX17_2", - "CMT_OUT_FIFO_SCANOUT1", - "CMT_FIFO_L_IMUX26_6", - "CMT_FIFO_WW2A3_0", - "CMT_OUT_FIFO_D84", - "CMT_FIFO_L_LOGIC_OUTS2_11", - "CMT_FIFO_L_IMUX7_8", - "CMT_FIFO_L_LOGIC_OUTS4_8", - "CMT_FIFO_L_BYP4_3", - "CMT_FIFO_L_IMUX29_3", - "CMT_FIFO_EE2A2_6", - "CMT_FIFO_SW4END2_7", - "CMT_FIFO_L_CLK0_9", - "CMT_OUT_FIFO_RESET", - "CMT_FIFO_WW4C3_10", - "CMT_FIFO_NW2A1_11", - "CMT_FIFO_PHASER_TO_IO_ICLK_7", - "CMT_FIFO_L_FAN1_6", - "CMT_FIFO_L_IMUX35_2", - "CMT_FIFO_L_IMUX25_2", - "CMT_FIFO_WR1END3_6", - "CMT_FIFO_NW4END2_11", - "CMT_FIFO_NE2A1_2", - "CMT_OUT_FIFO_D83", - "CMT_FIFO_L_LOGIC_OUTS7_6", - "CMT_FIFO_L_CTRL1_7", - "CMT_IN_FIFO_TESTWRITEDISB", - "CMT_FIFO_SE4BEG2_10", - "CMT_FIFO_WW2END1_0", - "CMT_FIFO_LH8_8", - "CMT_FIFO_L_IMUX35_9", - "CMT_FIFO_NW4END0_4", - "CMT_OUT_FIFO_Q00", - "CMT_FIFO_L_IMUX25_10", - "CMT_FIFO_SE4BEG1_9", - "CMT_FIFO_LH9_7", - "CMT_FIFO_WW4A2_9", - "CMT_FIFO_WW4END3_8", - "CMT_FIFO_WW4C3_7", - "CMT_OUT_FIFO_Q64", - "CMT_FIFO_L_IMUX22_11", - "CMT_FIFO_SE4BEG3_1", - "CMT_FIFO_WL1END1_1", - "CMT_FIFO_EL1BEG3_7", - "CMT_FIFO_EE2BEG2_8", - "CMT_OUT_FIFO_D47", - "CMT_FIFO_SE4BEG2_2", - "CMT_FIFO_EE2A0_3", - "CMT_FIFO_L_IMUX26_1", - "CMT_FIFO_L_LOGIC_OUTS7_2", - "CMT_FIFO_L_BYP4_11", - "CMT_FIFO_WW2END1_7", - "CMT_FIFO_L_IMUX3_3", - "CMT_FIFO_SW4A3_2", - "CMT_FIFO_SW4END0_3", - "CMT_FIFO_L_LOGIC_OUTS5_4", - "CMT_FIFO_L_IMUX40_8", - "CMT_FIFO_L_LOGIC_OUTS2_0", - "CMT_FIFO_NE4BEG3_11", - "CMT_FIFO_L_IMUX9_3", - "CMT_FIFO_NE4BEG0_0", - "CMT_FIFO_EE4A1_0", - "CMT_IN_FIFO_Q04", - "CMT_FIFO_WW4A3_10", - "CMT_IN_FIFO_Q17", - "CMT_FIFO_L_LOGIC_OUTS4_2", - "CMT_FIFO_SE2A1_7", - "CMT_FIFO_WW2END0_2", - "CMT_OUT_FIFO_D23", - "CMT_FIFO_L_FAN2_2", - "CMT_FIFO_EE2A2_9", - "CMT_FIFO_L_IMUX9_2", - "CMT_FIFO_WR1END2_3", - "CMT_FIFO_WW4B3_11", - "CMT_FIFO_L_IMUX2_11", - "CMT_IN_FIFO_Q52", - "CMT_FIFO_SE4BEG1_10", - "CMT_FIFO_EL1BEG1_5", - "CMT_FIFO_L_LOGIC_OUTS9_0", - "CMT_FIFO_WR1END2_11", - "CMT_OUT_FIFO_D33", - "CMT_OUT_FIFO_D07", - "CMT_FIFO_SW2A1_9", - "CMT_FIFO_WW4END1_1", - "CMT_FIFO_WW4A1_3", - "CMT_FIFO_EE4C0_1", - "CMT_FIFO_EE4B0_10", - "CMT_OUT_FIFO_Q70", - "CMT_FIFO_L_FAN2_9", - "CMT_FIFO_WW4C1_1", - "CMT_FIFO_L_IMUX17_11", - "CMT_FIFO_L_IMUX25_9", - "CMT_FIFO_SW4END0_9", - "CMT_FIFO_L_CTRL0_9", - "CMT_FIFO_EL1BEG1_2", - "CMT_OUT_FIFO_Q33", - "CMT_FIFO_L_IMUX3_9", - "CMT_FIFO_L_LOGIC_OUTS12_6", - "CMT_FIFO_L_LOGIC_OUTS0_4", - "CMT_FIFO_NE4C1_3", - "CMT_OUT_FIFO_SCANOUT2", - "CMT_FIFO_SE2A2_4", - "CMT_FIFO_L_LOGIC_OUTS13_11", - "CMT_FIFO_WW4END1_4", - "CMT_FIFO_SE2A2_7", - "CMT_IN_FIFO_Q82", - "CMT_FIFO_L_IMUX23_2", - "CMT_FIFO_EE4C1_10", - "CMT_IN_FIFO_D73", - "CMT_FIFO_L_LOGIC_OUTS9_2", - "CMT_IN_FIFO_Q81", - "CMT_FIFO_LH2_1", - "CMT_FIFO_L_IMUX1_6", - "CMT_FIFO_SE2A2_1", - "CMT_FIFO_NE4BEG2_1", - "CMT_FIFO_WR1END0_0", - "CMT_FIFO_L_IMUX18_11", - "CMT_FIFO_EE4B3_7", - "CMT_FIFO_WW2END1_11", - "CMT_FIFO_NW4A3_1", - "CMT_FIFO_L_IMUX0_5", - "CMT_FIFO_NE4BEG3_8", - "CMT_FIFO_L_BYP5_11", - "CMT_FIFO_EE2A1_10", - "CMT_FIFO_NW2A0_2", - "CMT_FIFO_NE4BEG0_1", - "CMT_FIFO_L_IMUX37_3", - "CMT_IN_FIFO_Q54", - "CMT_FIFO_LH12_10", - "CMT_FIFO_NE4BEG2_9", - "CMT_FIFO_L_IMUX36_5", - "CMT_FIFO_EE2A1_8", - "CMT_FIFO_L_LOGIC_OUTS0_1", - "CMT_FIFO_L_IMUX7_0", - "CMT_FIFO_ER1BEG2_0", - "CMT_FIFO_SW4END3_11", - "CMT_FIFO_EE4B3_2", - "CMT_FIFO_L_LOGIC_OUTS12_0", - "CMT_OUT_FIFO_Q43", - "CMT_FIFO_SE2A3_5", - "CMT_OUT_FIFO_Q31", - "CMT_FIFO_NE2A0_2", - "CMT_FIFO_WW4B1_8", - "CMT_FIFO_WR1END0_4", - "CMT_FIFO_ER1BEG1_11", - "CMT_FIFO_L_FAN7_8", - "CMT_FIFO_NW4A2_2", - "CMT_OUT_FIFO_Q67", - "CMT_FIFO_SE4BEG0_7", - "CMT_FIFO_L_BYP0_3", - "CMT_FIFO_EE4C1_11", - "CMT_OUT_FIFO_Q42", - "CMT_FIFO_L_BYP5_8", - "CMT_FIFO_WL1END0_6", - "CMT_FIFO_EE4A1_2", - "CMT_FIFO_L_IMUX36_11", - "CMT_FIFO_LH2_9", - "CMT_FIFO_EE4B2_8", - "CMT_FIFO_NW4A0_5", - "CMT_FIFO_L_LOGIC_OUTS16_11", - "CMT_FIFO_EE4BEG1_11", - "CMT_FIFO_L_LOGIC_OUTS17_6", - "CMT_FIFO_ER1BEG3_10", - "CMT_FIFO_L_LOGIC_OUTS15_7", - "CMT_OUT_FIFO_D30", - "CMT_FIFO_SW4END1_3", - "CMT_FIFO_EE4BEG1_7", - "CMT_OUT_FIFO_D90", - "CMT_FIFO_L_IMUX30_1", - "CMT_FIFO_EE2A1_0", - "CMT_FIFO_ER1BEG2_10", - "CMT_FIFO_WW2END1_2", - "CMT_FIFO_L_LOGIC_OUTS14_8", - "CMT_FIFO_L_IMUX47_0", - "CMT_FIFO_L_BYP6_10", - "CMT_FIFO_EE4B1_0", - "CMT_FIFO_L_LOGIC_OUTS17_5", - "CMT_FIFO_EE2A2_11", - "CMT_FIFO_NE4BEG1_7", - "CMT_OUT_FIFO_Q02", - "CMT_FIFO_WW2END2_2", - "CMT_IN_FIFO_Q87", - "CMT_FIFO_WW4A2_10", - "CMT_FIFO_LH4_6", - "CMT_OUT_FIFO_D36", - "CMT_FIFO_WW4END0_1", - "CMT_FIFO_WL1END1_5", - "CMT_FIFO_SE4C2_10", - "CMT_FIFO_SW2A1_11", - "CMT_FIFO_L_FAN3_10", - "CMT_FIFO_SW4A2_7", - "CMT_FIFO_L_IMUX1_5", - "CMT_IN_FIFO_Q06", - "CMT_FIFO_WW4A3_3", - "CMT_FIFO_L_IMUX30_7", - "CMT_IN_FIFO_Q21", - "CMT_FIFO_WW4C0_10", - "CMT_FIFO_L_PHASER_RDENABLE", - "FIFO_DQS_IOTOPHASER_11", - "CMT_FIFO_EE4A2_10", - "CMT_FIFO_NW2A2_1", - "CMT_FIFO_EE2BEG1_0", - "CMT_FIFO_SW4A1_0", - "CMT_OUT_FIFO_D74", - "CMT_FIFO_L_BYP4_4", - "CMT_FIFO_L_FAN2_1", - "CMT_FIFO_L_IMUX41_8", - "CMT_FIFO_EE4B3_1", - "CMT_FIFO_L_LOGIC_OUTS12_3", - "CMT_FIFO_L_FAN5_11", - "CMT_IN_FIFO_Q67", - "CMT_FIFO_EL1BEG1_0", - "CMT_FIFO_NW4END3_5", - "CMT_FIFO_LH11_2", - "CMT_FIFO_SE4C2_3", - "CMT_FIFO_LH3_9", - "CMT_FIFO_LH6_2", - "CMT_FIFO_EL1BEG3_6", - "CMT_FIFO_SW4END1_5", - "CMT_FIFO_L_LOGIC_OUTS20_0", - "CMT_OUT_FIFO_D41", - "CMT_FIFO_WW2A3_6", - "CMT_FIFO_L_IMUX7_11", - "CMT_FIFO_EE4C1_8", - "CMT_FIFO_L_LOGIC_OUTS1_6", - "CMT_FIFO_L_LOGIC_OUTS15_5", - "CMT_FIFO_LH6_7", - "CMT_FIFO_L_IMUX28_3", - "CMT_FIFO_L_IMUX33_1", - "CMT_FIFO_WL1END3_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_3", - "CMT_FIFO_NE4C0_11", - "CMT_FIFO_SE4C0_6", - "CMT_FIFO_MONITOR_P_7", - "CMT_FIFO_ER1BEG3_2", - "CMT_FIFO_SE2A0_4", - "CMT_FIFO_L_IMUX3_11", - "CMT_FIFO_L_LOGIC_OUTS6_2", - "CMT_FIFO_SW2A2_11", - "CMT_FIFO_WW4END0_2", - "CMT_FIFO_ER1BEG2_6", - "CMT_FIFO_SW4END3_1", - "CMT_FIFO_L_LOGIC_OUTS12_1", - "CMT_FIFO_NW2A3_9", - "CMT_FIFO_L_IMUX24_0", - "CMT_IN_FIFO_D13", - "CMT_FIFO_L_IMUX34_3", - "CMT_FIFO_WR1END0_6", - "CMT_FIFO_L_LOGIC_OUTS14_4", - "CMT_FIFO_NW2A2_2", - "CMT_FIFO_EL1BEG0_1", - "CMT_FIFO_L_IMUX6_5", - "CMT_FIFO_ER1BEG0_7", - "CMT_FIFO_EE4C0_0", - "CMT_FIFO_L_IMUX32_2", - "CMT_FIFO_EE4C0_6", - "CMT_FIFO_L_BYP5_5", - "CMT_FIFO_EE4BEG2_5", - "CMT_FIFO_L_CTRL0_11", - "CMT_FIFO_NE4BEG1_9", - "CMT_FIFO_L_IMUX27_2", - "CMT_FIFO_LH11_11", - "CMT_FIFO_L_FAN2_3", - "CMT_FIFO_NW4A3_9", - "CMT_FIFO_LH4_5", - "CMT_IN_FIFO_Q10", - "CMT_IN_FIFO_D50", - "CMT_FIFO_L_LOGIC_OUTS23_3", - "CMT_FIFO_L_IMUX34_9", - "CMT_IN_FIFO_SCANOUT2", - "CMT_FIFO_WW4B0_3", - "CMT_FIFO_L_LOGIC_OUTS9_5", - "CMT_IN_FIFO_Q64", - "CMT_FIFO_NE2A3_5", - "CMT_FIFO_WW4END2_2", - "CMT_FIFO_PHASER_TO_IO_ICLK_4", - "CMT_FIFO_SW4A3_1", - "CMT_FIFO_NE4C2_1", - "CMT_FIFO_EE4BEG3_6", - "CMT_FIFO_L_IMUX8_4", - "CMT_FIFO_L_IMUX1_2", - "CMT_FIFO_L_IMUX26_0", - "CMT_FIFO_PHASER_TO_IO_ICLK_9", - "CMT_FIFO_ER1BEG1_5", - "CMT_FIFO_L_IMUX32_3", - "CMT_FIFO_SW4A2_8", - "CMT_FIFO_LH2_11", - "CMT_FIFO_L_LOGIC_OUTS0_9", - "CMT_FIFO_L_LOGIC_OUTS14_5", - "CMT_IN_FIFO_ALMOSTEMPTY", - "CMT_FIFO_EE4B3_3", - "CMT_FIFO_SW4END0_1", - "CMT_FIFO_LH6_9", - "CMT_FIFO_L_LOGIC_OUTS7_11", - "CMT_IN_FIFO_Q07", - "CMT_FIFO_NW2A1_2", - "CMT_FIFO_L_IMUX1_10", - "CMT_OUT_FIFO_Q23", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", - "CMT_FIFO_L_FAN6_10", - "CMT_FIFO_LH1_4", - "CMT_FIFO_L_IMUX21_0", - "CMT_FIFO_L_IMUX30_3", - "CMT_FIFO_L_LOGIC_OUTS20_4", - "CMT_FIFO_L_LOGIC_OUTS2_1", - "CMT_FIFO_NW4A1_7", - "CMT_OUT_FIFO_D82", - "CMT_FIFO_L_LOGIC_OUTS4_10", - "CMT_FIFO_WW4C3_3", - "CMT_FIFO_L_IMUX46_3", - "CMT_FIFO_L_LOGIC_OUTS9_1", - "CMT_FIFO_L_IMUX17_8", - "CMT_FIFO_SE4BEG2_8", - "CMT_FIFO_L_IMUX43_1", - "CMT_FIFO_L_FAN2_8", - "CMT_FIFO_WL1END1_9", - "CMT_FIFO_EE2BEG1_11", - "CMT_FIFO_NW4A0_3", - "CMT_FIFO_L_IMUX36_7", - "CMT_FIFO_ER1BEG2_3", - "CMT_FIFO_NE4C3_10", - "CMT_FIFO_L_LOGIC_OUTS23_7", - "CMT_FIFO_SW4END1_4", - "CMT_FIFO_EE2A2_10", - "CMT_FIFO_EL1BEG3_9", - "CMT_FIFO_SE4BEG1_11", - "CMT_FIFO_EE4B3_8", - "CMT_FIFO_L_LOGIC_OUTS22_2", - "CMT_FIFO_L_IMUX5_0", - "CMT_FIFO_WW2A1_9", - "CMT_FIFO_EE2A0_4", - "CMT_FIFO_SW2A3_7", - "CMT_FIFO_EE2BEG3_11", - "CMT_FIFO_L_LOGIC_OUTS20_1", - "CMT_FIFO_LH1_1", - "CMT_FIFO_L_IMUX5_7", - "CMT_FIFO_L_FAN4_2", - "CMT_FIFO_L_BYP3_7", - "CMT_FIFO_SE4BEG0_4", - "CMT_FIFO_EE2BEG3_8", - "CMT_FIFO_L_IMUX33_8", - "CMT_FIFO_L_FAN4_0", - "CMT_FIFO_L_IMUX22_4", - "CMT_FIFO_L_IMUX2_10", - "CMT_IN_FIFO_Q00", - "CMT_FIFO_EL1BEG0_10", - "CMT_FIFO_L_LOGIC_OUTS1_3", - "CMT_FIFO_L_IMUX7_4", - "CMT_FIFO_L_LOGIC_OUTS2_5", - "CMT_FIFO_ER1BEG1_8", - "CMT_FIFO_L_CTRL1_6", - "CMT_FIFO_L_CLK0_7", - "CMT_FIFO_SE4C2_9", - "CMT_FIFO_EE4BEG1_4", - "CMT_FIFO_NW4END3_3", - "CMT_FIFO_MONITOR_P_2", - "CMT_FIFO_SW4END2_10", - "CMT_FIFO_L_FAN1_8", - "CMT_FIFO_SW2A1_3", - "CMT_IN_FIFO_Q30", - "CMT_FIFO_L_CTRL1_5", - "CMT_FIFO_EE4C0_3", - "CMT_IN_FIFO_Q36", - "CMT_FIFO_NW4END1_6", - "CMT_FIFO_SW4END3_9", - "CMT_FIFO_SW4END1_7", - "CMT_FIFO_L_BYP0_1", - "CMT_FIFO_L_LOGIC_OUTS18_8", - "CMT_FIFO_LH9_0", - "CMT_FIFO_NE2A2_9", - "CMT_FIFO_SW4A2_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", - "CMT_FIFO_L_IMUX31_9", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", - "CMT_FIFO_WW4END3_0", - "CMT_FIFO_NE2A1_6", - "CMT_FIFO_L_IMUX3_10", - "CMT_FIFO_L_IMUX32_6", - "CMT_FIFO_L_BYP4_10", - "CMT_OUT_FIFO_SCANIN1", - "CMT_OUT_FIFO_Q81", - "CMT_FIFO_L_IMUX43_0", - "CMT_FIFO_NE2A1_5", - "CMT_FIFO_L_LOGIC_OUTS5_9", - "CMT_FIFO_NE2A1_9", - "CMT_FIFO_WW4C2_1", - "CMT_FIFO_SW4END1_9", - "CMT_FIFO_L_IMUX19_3", - "CMT_FIFO_EE4C1_1", - "CMT_FIFO_L_IMUX4_0", - "CMT_FIFO_L_IMUX37_6", - "CMT_FIFO_LH2_7", - "CMT_FIFO_L_IMUX11_5", - "CMT_FIFO_L_LOGIC_OUTS22_11", - "CMT_FIFO_NE2A2_1", - "CMT_FIFO_ER1BEG3_7", - "CMT_FIFO_EE4C3_1", - "CMT_FIFO_SW4END0_7", - "CMT_FIFO_NE2A0_4", - "CMT_OUT_FIFO_D56", - "CMT_FIFO_EE4C3_7", - "CMT_FIFO_WL1END3_7", - "CMT_FIFO_NE4C3_2", - "CMT_FIFO_L_IMUX32_5", - "CMT_FIFO_L_IMUX0_8", - "CMT_FIFO_EE4A2_1", - "CMT_FIFO_L_IMUX45_9", - "CMT_FIFO_WW4C2_2", - "CMT_FIFO_WL1END0_3", - "CMT_FIFO_SW4A1_8", - "CMT_FIFO_L_IMUX23_11", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", - "CMT_FIFO_SW2A1_10", - "CMT_FIFO_SE4C1_9", - "CMT_FIFO_SE4C2_1", - "CMT_FIFO_WR1END3_10", - "CMT_FIFO_SW4A0_6", - "CMT_IN_FIFO_TESTREADDISB", - "CMT_FIFO_L_IMUX22_2", - "CMT_FIFO_L_FAN2_4", - "CMT_FIFO_NE4BEG1_11", - "CMT_FIFO_ER1BEG0_1", - "CMT_FIFO_EE4BEG3_3", - "CMT_FIFO_L_IMUX37_5", - "CMT_OUT_FIFO_D06", - "CMT_FIFO_NW4END1_8", - "CMT_FIFO_WR1END1_2", - "CMT_FIFO_L_BYP0_11", - "CMT_FIFO_NW4END1_5", - "CMT_FIFO_WW2END2_7", - "CMT_FIFO_L_IMUX9_11", - "FIFO_DQS_IOTOPHASER_44", - "CMT_FIFO_WW4B1_0", - "CMT_FIFO_L_IMUX39_4", - "CMT_FIFO_L_LOGIC_OUTS15_6", - "CMT_FIFO_L_LOGIC_OUTS9_11", - "CMT_FIFO_ER1BEG1_1", - "CMT_FIFO_NW4END0_1", - "CMT_FIFO_EE4A1_9", - "CMT_FIFO_L_IMUX43_10", - "CMT_FIFO_L_IMUX7_6", - "CMT_FIFO_L_IMUX11_9", - "CMT_IN_FIFO_SCANIN1", - "CMT_FIFO_L_LOGIC_OUTS14_10", - "CMT_FIFO_L_IMUX39_9", - "CMT_FIFO_WW4C3_8", - "CMT_FIFO_SW4A1_10", - "CMT_FIFO_L_CLK0_3", - "CMT_FIFO_L_PHASER_RDCLK", - "CMT_FIFO_L_IMUX24_3", - "CMT_FIFO_L_FAN2_7", - "CMT_IN_FIFO_Q63", - "CMT_FIFO_L_IMUX23_7", - "CMT_OUT_FIFO_D43", - "CMT_FIFO_L_BYP6_0", - "CMT_FIFO_EE2A1_5", - "CMT_FIFO_WW2END2_8", - "CMT_FIFO_L_IMUX2_9", - "CMT_FIFO_EE2A3_2", - "CMT_FIFO_LH5_0", - "CMT_FIFO_L_LOGIC_OUTS5_7", - "CMT_OUT_FIFO_D86", - "CMT_FIFO_L_IMUX20_3", - "CMT_FIFO_L_IMUX29_6", - "CMT_OUT_FIFO_D53", - "CMT_FIFO_L_FAN6_2", - "CMT_FIFO_WW4C2_9", - "CMT_FIFO_WR1END1_5", - "CMT_FIFO_L_IMUX17_3", - "CMT_FIFO_L_BYP3_5", - "CMT_FIFO_L_LOGIC_OUTS0_3", - "CMT_IN_FIFO_D22", - "CMT_FIFO_WW4END2_6", - "CMT_FIFO_L_IMUX10_11", - "CMT_FIFO_EE4C2_3", - "CMT_FIFO_L_IMUX16_1", - "CMT_FIFO_L_IMUX42_11", - "CMT_OUT_FIFO_D55", - "CMT_FIFO_WW2END3_0", - "CMT_FIFO_MONITOR_N_1", - "CMT_FIFO_L_IMUX9_8", - "CMT_FIFO_NE4BEG1_1", - "CMT_FIFO_WW2END2_4", - "CMT_FIFO_SW4A0_4", - "CMT_FIFO_EE4C2_2", - "CMT_FIFO_NE4C1_6", - "CMT_FIFO_MONITOR_P_9", - "CMT_FIFO_L_IMUX34_5", - "CMT_FIFO_WW4A0_5", - "CMT_FIFO_L_CTRL1_8", - "CMT_FIFO_NW4A1_6", - "CMT_FIFO_L_IMUX15_4", - "CMT_FIFO_NE2A0_11", - "CMT_FIFO_NW4END0_10", - "CMT_FIFO_SE4C3_2", - "CMT_FIFO_L_LOGIC_OUTS1_11", - "CMT_FIFO_EE2A0_5", - "CMT_FIFO_L_IMUX24_8", - "CMT_FIFO_LH4_10", - "CMT_FIFO_L_IMUX16_8", - "CMT_FIFO_L_IMUX10_4", - "CMT_OUT_FIFO_D40", - "CMT_FIFO_WW4C1_10", - "CMT_FIFO_L_IMUX40_4", - "CMT_FIFO_EL1BEG3_11", - "CMT_FIFO_L_LOGIC_OUTS8_8", - "CMT_FIFO_L_LOGIC_OUTS18_6", - "CMT_FIFO_NW2A1_4", - "CMT_FIFO_EE4C0_8", - "CMT_FIFO_L_BYP0_6", - "CMT_FIFO_L_IMUX17_9", - "CMT_IN_FIFO_D00", - "CMT_FIFO_EL1BEG2_11", - "CMT_FIFO_NW2A3_6", - "CMT_FIFO_L_BYP5_7", - "CMT_FIFO_L_IMUX3_1", - "CMT_FIFO_L_IMUX22_9", - "CMT_FIFO_L_LOGIC_OUTS3_9", - "CMT_FIFO_L_LOGIC_OUTS18_9", - "CMT_FIFO_NW4END2_5", - "CMT_FIFO_LH8_1", - "CMT_IN_FIFO_Q25", - "CMT_FIFO_L_BYP3_8", - "CMT_FIFO_L_LOGIC_OUTS3_2", - "CMT_FIFO_EL1BEG2_7", - "CMT_FIFO_L_LOGIC_OUTS8_0", - "CMT_FIFO_L_IMUX0_11", - "CMT_IN_FIFO_Q96", - "CMT_FIFO_NW4END2_7", - "CMT_FIFO_L_LOGIC_OUTS6_3", - "CMT_OUT_FIFO_D25", - "CMT_FIFO_SE4C1_11", - "CMT_FIFO_LH10_11", - "CMT_FIFO_L_LOGIC_OUTS3_11", - "CMT_FIFO_EL1BEG0_3", - "CMT_FIFO_L_FAN6_6", - "CMT_FIFO_L_LOGIC_OUTS5_3", - "CMT_FIFO_LH5_9", - "CMT_OUT_FIFO_D45", - "CMT_IN_FIFO_Q12", - "CMT_FIFO_WW2END2_0", - "CMT_FIFO_L_LOGIC_OUTS11_3", - "CMT_FIFO_L_IMUX38_11", - "CMT_FIFO_SW4END2_2", - "CMT_FIFO_WW2END3_6", - "CMT_FIFO_ER1BEG2_4", - "CMT_FIFO_NW4END3_10", - "CMT_FIFO_L_IMUX32_7", - "CMT_FIFO_EE4B2_10", - "CMT_FIFO_NE4BEG2_3", - "CMT_FIFO_L_LOGIC_OUTS10_5", - "CMT_FIFO_L_IMUX8_7", - "CMT_FIFO_L_IMUX11_7", - "CMT_FIFO_L_IMUX14_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_0", - "CMT_FIFO_SE2A1_4", - "CMT_FIFO_NE4BEG1_2", - "CMT_IN_FIFO_D80", - "CMT_FIFO_NW4END2_3", - "CMT_FIFO_L_CLK0_0", - "CMT_IN_FIFO_D43", - "CMT_FIFO_WW4C1_3", - "CMT_FIFO_WW4A1_10", - "CMT_FIFO_LH12_9", - "CMT_OUT_FIFO_Q54", - "CMT_FIFO_LH6_11", - "CMT_FIFO_WW2END0_4", - "CMT_FIFO_WW2END2_3", - "CMT_FIFO_L_BYP7_10", - "CMT_FIFO_L_CLK1_10", - "CMT_FIFO_L_BYP1_8", - "CMT_FIFO_L_IMUX30_10", - "CMT_FIFO_ER1BEG0_11", - "CMT_FIFO_NW4END1_1", - "CMT_FIFO_L_LOGIC_OUTS10_11", - "CMT_OUT_FIFO_D16", - "CMT_FIFO_WL1END2_0", - "CMT_FIFO_EL1BEG1_7", - "CMT_FIFO_L_LOGIC_OUTS8_5", - "CMT_FIFO_NE2A2_3", - "CMT_OUT_FIFO_Q55", - "CMT_OUT_FIFO_D20", - "CMT_FIFO_SE2A0_5", - "CMT_FIFO_LH12_1", - "CMT_FIFO_L_LOGIC_OUTS11_2", - "CMT_FIFO_WW2END3_11", - "CMT_FIFO_SE2A1_0", - "CMT_OUT_FIFO_Q03", - "CMT_FIFO_SW4END1_0", - "CMT_FIFO_L_FAN0_9", - "CMT_FIFO_L_LOGIC_OUTS8_7", - "CMT_FIFO_L_FAN5_10", - "CMT_IN_FIFO_D11", - "CMT_FIFO_EE4A1_4", - "CMT_FIFO_EE2BEG2_6", - "CMT_FIFO_NW2A2_10", - "CMT_FIFO_EE4A2_11", - "CMT_FIFO_L_IMUX8_0", - "CMT_FIFO_NE4BEG3_5", - "CMT_FIFO_SE4C0_10", - "CMT_FIFO_WW4A3_0", - "CMT_FIFO_NW4END2_9", - "CMT_FIFO_L_LOGIC_OUTS13_8", - "CMT_FIFO_WW2A3_10", - "CMT_IN_FIFO_D52", - "CMT_FIFO_WR1END2_9", - "CMT_FIFO_L_IMUX13_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", - "CMT_FIFO_L_IMUX30_9", - "CMT_FIFO_L_IMUX21_6", - "CMT_FIFO_L_IMUX44_11", - "CMT_FIFO_EE4C2_5", - "CMT_FIFO_NE2A2_10", - "CMT_FIFO_L_FAN5_6", - "CMT_FIFO_L_LOGIC_OUTS2_10", - "CMT_IN_FIFO_Q13", - "CMT_FIFO_L_IMUX13_0", - "CMT_FIFO_EE2A3_1", - "CMT_FIFO_SE4BEG1_2", - "CMT_FIFO_LH9_8", - "CMT_FIFO_NE4C3_3", - "CMT_FIFO_L_LOGIC_OUTS8_2", - "CMT_OUT_FIFO_D76", - "CMT_FIFO_WW4B2_5", - "CMT_FIFO_L_FAN7_10", - "CMT_FIFO_L_LOGIC_OUTS21_8", - "CMT_FIFO_LH2_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", - "CMT_FIFO_WW4A2_3", - "CMT_IN_FIFO_Q93", - "CMT_FIFO_SE4C3_4", - "CMT_FIFO_L_IMUX32_1", - "CMT_FIFO_L_LOGIC_OUTS10_1", - "CMT_FIFO_L_LOGIC_OUTS10_3", - "CMT_FIFO_EE4C3_11", - "CMT_FIFO_L_IMUX15_3", - "CMT_FIFO_L_IMUX43_9", - "CMT_FIFO_SE2A0_2", - "CMT_FIFO_NE4BEG0_8", - "CMT_FIFO_L_LOGIC_OUTS11_1", - "CMT_FIFO_WW2A2_6", - "CMT_FIFO_L_IMUX33_11", - "CMT_FIFO_L_IMUX32_11", - "CMT_OUT_FIFO_D67", - "CMT_FIFO_L_IMUX20_11", - "CMT_FIFO_L_BYP5_4", - "CMT_FIFO_L_IMUX44_6", - "CMT_FIFO_L_IMUX42_10", - "CMT_FIFO_LH3_1", - "CMT_FIFO_EL1BEG1_8", - "CMT_OUT_FIFO_D34", - "CMT_FIFO_L_IMUX18_6", - "CMT_FIFO_L_IMUX47_9", - "CMT_FIFO_SE2A1_1", - "CMT_FIFO_WW4END2_8", - "CMT_FIFO_L_IMUX11_2", - "CMT_FIFO_MONITOR_N_3", - "CMT_FIFO_L_IMUX41_10", - "CMT_FIFO_NW4END3_8", - "CMT_FIFO_SE4C0_2", - "CMT_FIFO_L_IMUX42_8", - "CMT_FIFO_L_IMUX4_5", - "CMT_FIFO_L_FAN1_1", - "CMT_FIFO_WW4C1_7", - "CMT_IN_FIFO_Q60", - "CMT_FIFO_L_BYP1_10", - "CMT_FIFO_EE4A2_8", - "CMT_FIFO_EE4BEG2_8", - "CMT_IN_FIFO_D42", - "CMT_OUT_FIFO_Q10", - "CMT_FIFO_NE2A2_7", - "CMT_FIFO_L_IMUX45_6", - "CMT_IN_FIFO_D61", - "CMT_FIFO_L_FAN6_1", - "CMT_FIFO_L_IMUX20_4", - "CMT_FIFO_EE4C2_0", - "CMT_FIFO_EL1BEG2_4", - "CMT_IN_FIFO_SCANOUT1", - "CMT_FIFO_NW4A2_5", - "CMT_FIFO_ER1BEG0_4", - "CMT_FIFO_NW4A0_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", - "CMT_FIFO_EE2BEG1_4", - "CMT_FIFO_L_CLK1_0", - "CMT_FIFO_EE4B3_5", - "CMT_FIFO_EE4A3_4", - "CMT_FIFO_L_IMUX47_5", - "CMT_FIFO_L_IMUX32_8", - "CMT_FIFO_NW2A1_6", - "CMT_FIFO_NW4A2_10", - "CMT_FIFO_L_IMUX42_6", - "CMT_FIFO_L_IMUX8_6", - "CMT_FIFO_L_IMUX14_11", - "CMT_FIFO_L_LOGIC_OUTS3_10", - "CMT_FIFO_L_IMUX16_5", - "CMT_IN_FIFO_Q26", - "CMT_FIFO_L_IMUX10_0", - "CMT_FIFO_EE2A2_7", - "CMT_FIFO_WW2A3_9", - "CMT_FIFO_L_LOGIC_OUTS23_1", - "CMT_FIFO_ER1BEG2_11", - "CMT_FIFO_SW2A0_3", - "CMT_FIFO_EE2BEG1_3", - "CMT_FIFO_L_LOGIC_OUTS9_6", - "CMT_FIFO_LH3_3", - "CMT_FIFO_NE4BEG2_4", - "CMT_FIFO_LH8_7", - "CMT_FIFO_LH5_5", - "CMT_FIFO_L_LOGIC_OUTS20_7", - "CMT_FIFO_SE2A3_10", - "CMT_FIFO_L_LOGIC_OUTS16_8", - "CMT_FIFO_L_IMUX9_6", - "CMT_FIFO_NE4C1_2", - "CMT_FIFO_WW4A1_8", - "CMT_IN_FIFO_D71", - "CMT_FIFO_L_IMUX0_10", - "CMT_FIFO_L_IMUX36_0", - "CMT_FIFO_L_BYP0_5", - "CMT_FIFO_MONITOR_P_0", - "CMT_FIFO_EE2BEG0_9", - "CMT_FIFO_SE4C1_5", - "CMT_FIFO_SE4C1_0", - "CMT_FIFO_L_FAN3_11", - "CMT_FIFO_WW4END2_1", - "CMT_FIFO_SE4BEG0_9", - "CMT_FIFO_MONITOR_P_4", - "CMT_FIFO_L_LOGIC_OUTS21_11", - "CMT_FIFO_WL1END0_4", - "CMT_FIFO_LH8_10", - "CMT_FIFO_EE2BEG3_9", - "CMT_FIFO_L_BYP7_6", - "CMT_FIFO_WW4A1_7", - "CMT_FIFO_WR1END2_7", - "CMT_FIFO_L_LOGIC_OUTS19_7", - "CMT_FIFO_NW2A1_10", - "CMT_FIFO_L_BYP3_10", - "CMT_FIFO_L_IMUX44_10", - "CMT_FIFO_L_BYP0_4", - "CMT_FIFO_L_BYP4_9", - "CMT_FIFO_WW4C0_0", - "CMT_FIFO_L_IMUX29_4", - "CMT_FIFO_WW2A2_5", - "CMT_FIFO_L_LOGIC_OUTS10_2", - "CMT_FIFO_SW2A3_3", - "CMT_FIFO_EE4BEG2_9", - "CMT_FIFO_L_IMUX25_4", - "CMT_FIFO_SE4BEG1_6", - "CMT_FIFO_ER1BEG3_1", - "CMT_FIFO_WW4END2_9", - "CMT_FIFO_L_IMUX38_10", - "CMT_FIFO_EE4C0_4", - "CMT_FIFO_L_IMUX27_3", - "CMT_FIFO_WW4END3_10", - "CMT_FIFO_L_IMUX13_8", - "CMT_FIFO_L_IMUX28_0", - "CMT_FIFO_WL1END2_2", - "CMT_FIFO_EE4C3_5", - "CMT_FIFO_ER1BEG0_6", - "CMT_OUT_FIFO_Q80", - "CMT_FIFO_SW4A1_4", - "CMT_IN_FIFO_D56", - "CMT_FIFO_L_IMUX0_9", - "CMT_FIFO_L_IMUX6_3", - "CMT_IN_FIFO_D01", - "CMT_FIFO_NE2A0_3", - "CMT_FIFO_L_IMUX35_0", - "CMT_FIFO_L_IMUX23_5", - "CMT_FIFO_NW2A2_9", - "CMT_FIFO_L_IMUX35_11", - "CMT_FIFO_MONITOR_N_6", - "CMT_FIFO_WW4END1_11", - "CMT_FIFO_SW2A0_6", - "CMT_FIFO_SW2A3_11", - "CMT_FIFO_L_FAN4_3", - "CMT_FIFO_WW4B0_6", - "CMT_FIFO_EE2BEG1_6", - "CMT_FIFO_NE4C0_8", - "CMT_FIFO_L_IMUX12_7", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", - "CMT_FIFO_SW4A0_11", - "CMT_FIFO_L_IMUX10_6", - "CMT_FIFO_WR1END1_11", - "CMT_OUT_FIFO_D11", - "CMT_FIFO_L_PHASER_WRCLK", - "CMT_FIFO_WW2A0_4", - "CMT_FIFO_SE4C0_11", - "CMT_FIFO_L_BYP2_3", - "CMT_FIFO_L_FAN5_3", - "CMT_FIFO_WW2A0_6", - "CMT_FIFO_EE4A3_8", - "CMT_FIFO_L_FAN5_4", - "CMT_FIFO_L_IMUX25_8", - "CMT_FIFO_L_LOGIC_OUTS20_11", - "CMT_FIFO_L_LOGIC_OUTS5_6", - "CMT_FIFO_L_IMUX6_7", - "CMT_FIFO_EE4B1_5", - "CMT_FIFO_WL1END1_0", - "CMT_FIFO_L_BYP1_4", - "CMT_FIFO_L_IMUX9_1", - "CMT_FIFO_L_IMUX24_10", - "CMT_FIFO_WL1END1_6", - "CMT_FIFO_EE2BEG3_2", - "CMT_FIFO_MONITOR_P_6", - "CMT_FIFO_LH3_11", - "CMT_FIFO_L_FAN6_0", - "CMT_FIFO_EE2A3_9", - "CMT_FIFO_LH9_10", - "CMT_OUT_FIFO_Q63", - "CMT_FIFO_L_LOGIC_OUTS15_11", - "CMT_FIFO_EE2BEG3_6", - "CMT_FIFO_LH8_0", - "CMT_OUT_FIFO_Q61", - "CMT_FIFO_WW4B3_8", - "CMT_FIFO_WL1END2_4", - "CMT_FIFO_L_FAN7_1", - "CMT_FIFO_L_BYP6_7", - "CMT_FIFO_L_LOGIC_OUTS3_8", - "CMT_FIFO_L_IMUX13_5", - "CMT_FIFO_WW4END3_7", - "CMT_FIFO_L_LOGIC_OUTS16_3", - "CMT_IN_FIFO_Q33", - "CMT_FIFO_NW2A1_8", - "CMT_FIFO_SE4C3_10", - "CMT_FIFO_NE4C1_0", - "CMT_FIFO_LH12_7", - "CMT_FIFO_L_IMUX42_2", - "CMT_FIFO_NE2A3_11", - "CMT_FIFO_L_IMUX39_2", - "CMT_FIFO_SW4END2_9", - "CMT_FIFO_WL1END2_11", - "CMT_FIFO_EE4B2_7", - "CMT_FIFO_L_LOGIC_OUTS17_3", - "CMT_FIFO_L_FAN1_0", - "CMT_FIFO_NE2A3_6", - "CMT_FIFO_L_IMUX46_2", - "CMT_FIFO_L_LOGIC_OUTS1_1", - "CMT_FIFO_SW2A0_1", - "CMT_FIFO_L_CLK1_2", - "CMT_FIFO_EE4A3_0", - "CMT_FIFO_L_IMUX38_8", - "CMT_OUT_FIFO_Q12", - "CMT_FIFO_L_IMUX32_9", - "CMT_FIFO_L_LOGIC_OUTS11_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", - "CMT_FIFO_WW4END1_9", - "CMT_FIFO_LH12_5", - "CMT_IN_FIFO_Q76", - "CMT_FIFO_L_BYP6_1", - "CMT_FIFO_EE4A0_5", - "CMT_FIFO_WW4B3_3", - "CMT_OUT_FIFO_Q57", - "CMT_FIFO_L_LOGIC_OUTS15_10", - "CMT_FIFO_L_IMUX31_5", - "CMT_FIFO_L_IMUX46_6", - "CMT_FIFO_L_IMUX22_3", - "CMT_FIFO_EE4C0_10", - "CMT_FIFO_L_LOGIC_OUTS12_2", - "CMT_FIFO_WL1END2_5", - "CMT_IN_FIFO_Q94", - "CMT_FIFO_EE2A3_4", - "CMT_OUT_FIFO_D91", - "CMT_FIFO_L_IMUX43_2", - "CMT_FIFO_NE4BEG1_4", - "CMT_IN_FIFO_D40", - "CMT_FIFO_WW4A3_8", - "CMT_FIFO_SW4A1_2", - "CMT_FIFO_LH9_4", - "CMT_FIFO_NE4BEG1_5", - "CMT_FIFO_L_IMUX18_2", - "CMT_FIFO_WR1END2_6", - "FIFO_DQS_IOTOPHASER_66", - "CMT_FIFO_L_LOGIC_OUTS17_7", - "CMT_FIFO_NE2A3_7", - "CMT_FIFO_L_LOGIC_OUTS15_3", - "CMT_FIFO_NW4A1_11", - "CMT_FIFO_SW2A0_9", - "CMT_FIFO_NW4END2_10", - "CMT_OUT_FIFO_Q91", - "CMT_FIFO_L_LOGIC_OUTS21_0", - "CMT_FIFO_L_IMUX46_7", - "CMT_FIFO_WW4B2_11", - "CMT_FIFO_WW2END3_4", - "CMT_FIFO_WW4END1_6", - "CMT_FIFO_WW2A0_8", - "CMT_FIFO_L_LOGIC_OUTS10_4", - "CMT_FIFO_LH8_2", - "CMT_FIFO_L_IMUX4_8", - "CMT_FIFO_SW4A2_5", - "CMT_FIFO_EE2A3_8", - "CMT_FIFO_L_IMUX9_10", - "CMT_FIFO_EE4C2_7", - "CMT_FIFO_L_IMUX2_0", - "CMT_FIFO_WW4A2_7", - "CMT_FIFO_L_BYP2_1", - "CMT_FIFO_EE4BEG3_0", - "CMT_FIFO_L_IMUX7_9", - "CMT_FIFO_L_LOGIC_OUTS22_3", - "CMT_FIFO_L_IMUX15_11", - "CMT_FIFO_L_LOGIC_OUTS2_8", - "CMT_FIFO_ER1BEG1_7", - "CMT_FIFO_L_IMUX32_4", - "CMT_FIFO_L_LOGIC_OUTS18_4", - "CMT_IN_FIFO_Q73", - "CMT_FIFO_SE4BEG2_5", - "CMT_FIFO_L_IMUX47_1", - "CMT_FIFO_NE4BEG1_3", - "CMT_FIFO_L_IMUX29_10", - "CMT_FIFO_L_IMUX23_4", - "CMT_FIFO_NW2A3_4", - "CMT_FIFO_L_LOGIC_OUTS7_5", - "CMT_FIFO_NW4A3_11", - "CMT_FIFO_ER1BEG0_5", - "CMT_FIFO_L_IMUX38_0", - "CMT_FIFO_SW4A3_5", - "CMT_IN_FIFO_Q22", - "CMT_FIFO_L_IMUX33_3", - "CMT_FIFO_L_FAN6_3", - "CMT_FIFO_EE4A2_0", - "CMT_FIFO_EE2BEG0_10", - "CMT_FIFO_NW4A3_7", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", - "CMT_FIFO_EE4C3_10", - "CMT_FIFO_EE2A2_3", - "CMT_FIFO_SW2A2_0", - "CMT_FIFO_NW2A1_9", - "CMT_FIFO_L_IMUX17_0", - "CMT_FIFO_L_IMUX13_11", - "CMT_FIFO_WW4B0_7", - "CMT_FIFO_NW4END3_4", - "CMT_FIFO_EE4BEG1_0", - "CMT_FIFO_NW2A2_5", - "CMT_FIFO_L_FAN7_2", - "CMT_FIFO_L_FAN7_0", - "CMT_FIFO_NW4A1_2", - "CMT_FIFO_ER1BEG0_2", - "CMT_OUT_FIFO_D52", - "CMT_FIFO_SW4END2_11", - "CMT_FIFO_EE2A1_1", - "CMT_FIFO_L_IMUX46_4", - "CMT_FIFO_EE4BEG3_1", - "CMT_FIFO_NE2A3_8", - "CMT_FIFO_WW4B1_11", - "CMT_FIFO_WW4B2_10", - "CMT_FIFO_EE2A2_5", - "CMT_FIFO_NW4A1_1", - "CMT_FIFO_L_IMUX46_9", - "CMT_FIFO_L_IMUX12_8", - "CMT_FIFO_SW2A3_2", - "CMT_FIFO_L_CLK0_2", - "CMT_FIFO_WL1END2_8", - "CMT_FIFO_L_LOGIC_OUTS8_10", - "CMT_FIFO_L_IMUX40_11", - "CMT_FIFO_ER1BEG3_0", - "CMT_FIFO_L_BYP5_9", - "CMT_FIFO_L_BYP4_5", - "CMT_FIFO_L_IMUX33_2", - "CMT_FIFO_NW4END1_2", - "CMT_FIFO_NW2A2_6", - "CMT_FIFO_NW4A3_4", - "CMT_FIFO_EE4C2_11", - "CMT_FIFO_WL1END0_10", - "CMT_FIFO_L_FAN1_10", - "CMT_FIFO_L_IMUX5_1", - "CMT_FIFO_WW4END3_4", - "CMT_FIFO_LH4_9", - "CMT_FIFO_EE4C3_3", - "CMT_FIFO_SW2A1_6", - "CMT_FIFO_L_IMUX7_5", - "CMT_FIFO_L_BYP6_9", - "CMT_FIFO_L_IMUX24_1", - "CMT_FIFO_EE2BEG2_10", - "CMT_FIFO_L_LOGIC_OUTS17_4", - "CMT_FIFO_NW4END0_2", - "CMT_FIFO_L_LOGIC_OUTS21_7", - "CMT_FIFO_LH10_10", - "CMT_FIFO_L_LOGIC_OUTS19_5", - "CMT_FIFO_L_BYP3_1", - "CMT_FIFO_EE4A3_7", - "CMT_FIFO_L_IMUX30_8", - "CMT_FIFO_L_IMUX19_1", - "CMT_FIFO_L_LOGIC_OUTS1_0", - "CMT_FIFO_L_IMUX0_0", - "CMT_FIFO_WW4B0_11", - "CMT_FIFO_L_CTRL1_1", - "CMT_FIFO_EL1BEG2_10", - "CMT_IN_FIFO_Q32", - "CMT_FIFO_L_LOGIC_OUTS11_11", - "CMT_IN_FIFO_Q92", - "CMT_FIFO_SE4C0_8", - "CMT_FIFO_L_LOGIC_OUTS7_3", - "CMT_FIFO_NE2A0_9", - "CMT_IN_FIFO_Q56", - "CMT_FIFO_NW4A1_10", - "CMT_FIFO_SW4A0_10", - "CMT_FIFO_WR1END1_6", - "CMT_FIFO_L_IMUX39_1", - "CMT_FIFO_SE2A1_11", - "CMT_IN_FIFO_Q43", - "CMT_FIFO_L_IMUX45_4", - "CMT_FIFO_WW4B3_5", - "CMT_FIFO_SW4END3_5", - "CMT_FIFO_L_LOGIC_OUTS21_9", - "CMT_FIFO_L_LOGIC_OUTS4_1", - "CMT_FIFO_L_IMUX26_7", - "CMT_FIFO_L_IMUX36_9", - "CMT_FIFO_SE4C2_0", - "CMT_FIFO_WW4C3_4", - "CMT_FIFO_LH1_8", - "CMT_FIFO_L_IMUX25_11", - "CMT_FIFO_WR1END3_1", - "CMT_FIFO_L_IMUX12_3", - "CMT_FIFO_WL1END1_4", - "CMT_FIFO_EE4A1_7", - "CMT_FIFO_L_IMUX9_4", - "CMT_FIFO_EE2A2_8", - "CMT_FIFO_L_FAN2_6", - "CMT_FIFO_ER1BEG1_10", - "CMT_FIFO_L_IMUX22_8", - "CMT_FIFO_EE2A0_9", - "CMT_FIFO_L_LOGIC_OUTS16_10", - "CMT_FIFO_EE4BEG1_2", - "CMT_FIFO_EL1BEG2_0", - "CMT_FIFO_SE4BEG3_7", - "CMT_FIFO_L_IMUX3_8", - "CMT_FIFO_L_IMUX30_11", - "CMT_FIFO_WW2A3_2", - "CMT_FIFO_WW4A1_4", - "CMT_FIFO_L_IMUX12_6", - "CMT_FIFO_WW4C2_7", - "CMT_FIFO_WW4C0_1", - "CMT_FIFO_EL1BEG1_3", - "CMT_FIFO_WW4B2_3", - "CMT_FIFO_WW4C3_6", - "CMT_FIFO_SE4BEG2_3", - "CMT_FIFO_SW4A2_3", - "CMT_FIFO_SW4A1_9", - "CMT_FIFO_MONITOR_P_5", - "CMT_FIFO_EE4B2_4", - "CMT_FIFO_L_FAN5_5", - "CMT_FIFO_SW4END1_2", - "CMT_FIFO_L_IMUX43_8", - "CMT_FIFO_NW4A0_1", - "CMT_FIFO_L_IMUX27_8", - "CMT_FIFO_SW4A3_8", - "CMT_FIFO_WW4B0_4", - "CMT_FIFO_MONITOR_N_10", - "CMT_FIFO_L_IMUX20_2", - "CMT_FIFO_NE4C2_0", - "CMT_FIFO_L_IMUX20_10", - "CMT_FIFO_MONITOR_N_11", - "CMT_FIFO_EE4A0_0", - "CMT_FIFO_SW4A2_9", - "CMT_FIFO_EE4A0_1", - "CMT_FIFO_WW4END0_3", - "CMT_FIFO_L_IMUX36_6", - "CMT_FIFO_L_LOGIC_OUTS7_7", - "CMT_FIFO_SW4A0_7", - "CMT_FIFO_L_LOGIC_OUTS7_4", - "CMT_FIFO_WW4C0_3", - "CMT_FIFO_L_LOGIC_OUTS19_10", - "CMT_FIFO_L_IMUX43_4", - "CMT_FIFO_EE4A1_1", - "CMT_FIFO_L_IMUX28_6", - "CMT_FIFO_L_IMUX40_2", - "CMT_FIFO_L_IMUX28_2", - "CMT_FIFO_WW4A3_7", - "CMT_FIFO_WW4END3_1", - "CMT_FIFO_ER1BEG0_0", - "CMT_FIFO_L_IMUX15_0", - "CMT_FIFO_L_CTRL1_4", - "CMT_FIFO_LH4_8", - "CMT_OUT_FIFO_D44", - "CMT_FIFO_EE4BEG1_8", - "CMT_FIFO_WL1END0_5", - "CMT_FIFO_L_IMUX47_4", - "CMT_FIFO_L_IMUX4_1", - "CMT_FIFO_NE4C0_6", - "CMT_FIFO_EE2BEG1_1", - "CMT_FIFO_NW4A2_0", - "CMT_FIFO_L_IMUX29_5", - "CMT_FIFO_EE4A3_6", - "CMT_FIFO_L_BYP0_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_10", - "CMT_IN_FIFO_D64", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", - "CMT_FIFO_EE2BEG1_2", - "CMT_FIFO_EE4B0_4", - "CMT_FIFO_L_IMUX45_1", - "CMT_FIFO_L_LOGIC_OUTS7_10", - "CMT_FIFO_NW4A0_6", - "CMT_FIFO_WR1END0_11", - "CMT_FIFO_SE2A1_10", - "CMT_FIFO_L_BYP7_9", - "CMT_OUT_FIFO_SCANIN2", - "CMT_FIFO_NE4BEG1_6", - "CMT_FIFO_EE2BEG3_5", - "CMT_FIFO_SE2A1_3", - "CMT_FIFO_L_IMUX15_5", - "CMT_FIFO_NE2A1_7", - "CMT_FIFO_PHASER_TO_IO_ICLK_5", - "CMT_FIFO_L_IMUX16_9", - "CMT_FIFO_L_IMUX36_3", - "CMT_FIFO_WW2END0_11", - "CMT_IN_FIFO_D90", - "CMT_FIFO_L_IMUX5_5", - "CMT_FIFO_L_BYP4_8", - "CMT_FIFO_L_IMUX31_10", - "CMT_IN_FIFO_D51", - "CMT_FIFO_EE4C1_0", - "CMT_FIFO_EE4C2_9", - "CMT_FIFO_L_IMUX15_6", - "CMT_FIFO_L_IMUX28_11", - "CMT_FIFO_SW2A1_5", - "CMT_FIFO_SW4A3_9", - "CMT_FIFO_L_LOGIC_OUTS3_7", - "CMT_FIFO_L_IMUX6_10", - "CMT_FIFO_L_IMUX32_10", - "CMT_OUT_FIFO_Q66", - "CMT_FIFO_WW4END2_0", - "CMT_FIFO_L_LOGIC_OUTS4_3", - "CMT_FIFO_L_IMUX11_10", - "CMT_FIFO_LH5_6", - "CMT_FIFO_SW4A1_1", - "CMT_FIFO_L_BYP7_1", - "CMT_OUT_FIFO_D17", - "CMT_FIFO_EE2BEG3_3", - "CMT_FIFO_EL1BEG0_6", - "CMT_FIFO_NE4C0_1", - "CMT_FIFO_LH12_2", - "CMT_IN_FIFO_Q84", - "CMT_OUT_FIFO_D04", - "CMT_IN_FIFO_D83", - "CMT_FIFO_L_IMUX22_0", - "CMT_FIFO_L_IMUX3_6", - "CMT_FIFO_L_BYP1_2", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_6", - "CMT_FIFO_NE2A3_3", - "CMT_FIFO_L_IMUX3_7", - "CMT_FIFO_L_IMUX16_10", - "CMT_OUT_FIFO_D13", - "CMT_FIFO_NE4C1_5", - "CMT_FIFO_L_BYP3_3", - "CMT_FIFO_NE4BEG0_5", - "CMT_FIFO_L_LOGIC_OUTS12_4", - "CMT_FIFO_L_IMUX23_0", - "CMT_IN_FIFO_SCANOUT0", - "CMT_FIFO_SE4C3_8", - "CMT_FIFO_SW4A0_8", - "CMT_FIFO_L_LOGIC_OUTS14_9", - "CMT_FIFO_L_LOGIC_OUTS16_9", - "CMT_IN_FIFO_Q95", - "CMT_FIFO_L_LOGIC_OUTS21_6", - "CMT_FIFO_WR1END2_1", - "CMT_FIFO_L_LOGIC_OUTS20_5", - "CMT_FIFO_L_LOGIC_OUTS0_10", - "CMT_FIFO_EE2A3_7", - "CMT_FIFO_NE4C0_2", - "CMT_OUT_FIFO_ALMOSTFULL", - "CMT_FIFO_EE4A2_5", - "CMT_FIFO_WR1END3_0", - "CMT_FIFO_L_LOGIC_OUTS15_8", - "CMT_FIFO_EE4BEG1_9", - "CMT_FIFO_NW4A0_9", - "CMT_FIFO_L_IMUX39_11", - "CMT_FIFO_SE4C1_7", - "CMT_FIFO_EE2A3_11", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", - "CMT_FIFO_EE2A1_3", - "CMT_FIFO_WW2END3_8", - "CMT_FIFO_WW4B1_7", - "CMT_FIFO_L_LOGIC_OUTS1_9", - "CMT_FIFO_L_IMUX19_8", - "CMT_FIFO_L_LOGIC_OUTS4_0", - "CMT_FIFO_EL1BEG1_10", - "CMT_FIFO_NE4C2_7", - "CMT_FIFO_WW2A3_4", - "CMT_FIFO_L_IMUX16_0", - "CMT_FIFO_NW4END2_8", - "CMT_FIFO_L_IMUX20_0", - "CMT_IN_FIFO_SCANIN3", - "CMT_FIFO_WW4C2_8", - "CMT_OUT_FIFO_Q92", - "CMT_FIFO_SE4BEG3_10", - "CMT_FIFO_LH6_4", - "CMT_FIFO_MONITOR_N_5", - "CMT_FIFO_L_IMUX21_11", - "CMT_FIFO_EE4BEG2_10", - "CMT_FIFO_L_IMUX33_7", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", - "CMT_FIFO_WW4B3_10", - "CMT_FIFO_L_LOGIC_OUTS1_2", - "CMT_FIFO_WW4B0_1", - "CMT_OUT_FIFO_Q83", - "CMT_FIFO_L_CLK0_10", - "CMT_OUT_FIFO_Q65", - "CMT_FIFO_L_IMUX45_3", - "CMT_FIFO_WW2END2_6", - "CMT_FIFO_L_IMUX39_8", - "CMT_FIFO_NE4BEG3_0", - "CMT_OUT_FIFO_D26", - "CMT_FIFO_WW4A2_0", - "CMT_FIFO_ER1BEG2_2", - "CMT_FIFO_L_IMUX13_3", - "CMT_FIFO_WL1END0_8", - "CMT_FIFO_L_IMUX47_11", - "CMT_OUT_FIFO_D75", - "CMT_FIFO_L_BYP1_7", - "CMT_FIFO_L_FAN2_5", - "CMT_FIFO_NW4A2_11", - "CMT_IN_FIFO_D41", - "CMT_FIFO_EE2BEG0_1", - "CMT_FIFO_ER1BEG0_3", - "CMT_FIFO_EE4A1_5", - "CMT_OUT_FIFO_D96", - "CMT_FIFO_EE2BEG3_0", - "CMT_FIFO_L_FAN1_3", - "CMT_FIFO_WW4B1_3", - "CMT_OUT_FIFO_D97", - "CMT_FIFO_ER1BEG2_5", - "CMT_FIFO_L_LOGIC_OUTS13_6", - "CMT_FIFO_SW4A3_3", - "CMT_FIFO_EE2A1_4", - "CMT_FIFO_WW2A3_8", - "CMT_FIFO_EE4BEG3_11", - "CMT_FIFO_NW4END2_2", - "CMT_FIFO_EL1BEG0_5", - "CMT_FIFO_SE2A0_8", - "CMT_FIFO_EL1BEG2_1", - "CMT_FIFO_L_LOGIC_OUTS23_8", - "CMT_FIFO_WL1END2_1", - "CMT_FIFO_WW4A1_0", - "CMT_FIFO_L_LOGIC_OUTS10_10", - "CMT_FIFO_WW4C3_5", - "CMT_FIFO_SW2A0_4", - "CMT_FIFO_NE2A3_10", - "CMT_FIFO_NW4A3_3", - "CMT_IN_FIFO_Q23", - "CMT_FIFO_L_FAN5_1", - "CMT_FIFO_L_IMUX1_8", - "CMT_FIFO_L_IMUX5_3", - "CMT_FIFO_L_LOGIC_OUTS8_1", - "CMT_FIFO_NW4END3_6", - "CMT_FIFO_L_IMUX23_1", - "CMT_FIFO_LH1_11", - "CMT_FIFO_L_IMUX9_5", - "CMT_FIFO_NE4C3_0", - "CMT_FIFO_WW4B0_2", - "CMT_FIFO_EL1BEG3_2", - "CMT_FIFO_L_IMUX44_4", - "CMT_IN_FIFO_Q65", - "CMT_FIFO_SE2A0_6", - "CMT_FIFO_NW4END1_7", - "CMT_IN_FIFO_D60", - "CMT_OUT_FIFO_Q50", - "CMT_FIFO_L_IMUX24_11", - "CMT_FIFO_L_IMUX9_0", - "CMT_FIFO_SE4BEG2_7", - "CMT_FIFO_L_LOGIC_OUTS16_6", - "CMT_OUT_FIFO_D85", - "CMT_FIFO_L_IMUX33_10", - "CMT_FIFO_L_IMUX14_1", - "CMT_FIFO_L_LOGIC_OUTS5_1", - "CMT_FIFO_L_FAN7_6", - "CMT_FIFO_WW4C1_11", - "CMT_FIFO_L_IMUX29_0", - "CMT_FIFO_L_LOGIC_OUTS14_6", - "CMT_FIFO_NE4BEG2_8", - "CMT_FIFO_SW4A3_11", - "CMT_FIFO_L_IMUX4_9", - "CMT_FIFO_L_IMUX6_6", - "CMT_OUT_FIFO_Q40", - "CMT_FIFO_SW4END3_7", - "CMT_FIFO_LH6_3", - "CMT_FIFO_WL1END2_10", - "CMT_FIFO_WR1END3_8", - "CMT_IN_FIFO_Q14", - "CMT_FIFO_L_IMUX26_2", - "CMT_FIFO_WW2A2_0", - "CMT_FIFO_L_LOGIC_OUTS2_6", - "CMT_FIFO_L_IMUX4_10", - "CMT_FIFO_NE4C0_5", - "CMT_FIFO_LH6_5", - "CMT_FIFO_LH4_2", - "CMT_FIFO_EE4C1_7", - "CMT_FIFO_L_LOGIC_OUTS0_7", - "CMT_IN_FIFO_D23", - "CMT_FIFO_WW4C3_9", - "CMT_FIFO_SE2A2_6", - "CMT_IN_FIFO_Q37", - "CMT_OUT_FIFO_Q21", - "CMT_FIFO_LH2_5", - "CMT_IN_FIFO_Q70", - "CMT_FIFO_WW2A0_3", - "CMT_FIFO_L_LOGIC_OUTS14_7", - "CMT_FIFO_EE4BEG2_3", - "CMT_FIFO_NE4C1_7", - "CMT_FIFO_WW2A1_0", - "CMT_FIFO_L_IMUX11_6", - "CMT_FIFO_SE4BEG0_5", - "CMT_FIFO_MONITOR_N_4", - "CMT_FIFO_NW2A1_3", - "CMT_FIFO_EE4BEG2_0", - "CMT_FIFO_LH10_9", - "CMT_FIFO_L_IMUX16_2", - "CMT_FIFO_WW2A2_1", - "CMT_FIFO_LH4_1", - "CMT_FIFO_L_IMUX17_1", - "CMT_FIFO_L_IMUX45_8", - "CMT_FIFO_L_LOGIC_OUTS4_5", - "CMT_FIFO_EL1BEG2_6", - "CMT_FIFO_WW4B2_4", - "CMT_FIFO_EE2BEG1_5", - "CMT_FIFO_L_IMUX1_3", - "CMT_FIFO_SW4END0_8", - "CMT_FIFO_SW2A3_8", - "CMT_FIFO_L_FAN3_2", - "CMT_FIFO_WR1END1_3", - "CMT_FIFO_WL1END2_3", - "CMT_FIFO_WW2A0_10", - "CMT_FIFO_SE2A3_7", - "CMT_FIFO_L_IMUX45_10", - "CMT_FIFO_NE4BEG3_7", - "CMT_FIFO_NW2A0_8", - "CMT_FIFO_WR1END1_4", - "CMT_FIFO_SE2A1_8", - "CMT_FIFO_WW2END0_10", - "CMT_FIFO_EE2A0_0", - "CMT_FIFO_SW4END3_4", - "CMT_FIFO_NW4A2_9", - "CMT_FIFO_L_BYP7_11", - "CMT_FIFO_WW2END1_5", - "CMT_FIFO_SE4BEG1_7", - "CMT_FIFO_EE4BEG0_11", - "CMT_FIFO_WW4A0_6", - "CMT_FIFO_WR1END3_7", - "CMT_IN_FIFO_D91", - "CMT_FIFO_L_IMUX39_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", - "CMT_FIFO_L_IMUX46_11", - "CMT_FIFO_L_LOGIC_OUTS8_4", - "CMT_FIFO_LH3_2", - "CMT_FIFO_PHASER_TO_IO_ICLK_3", - "CMT_FIFO_EE4C1_5", - "CMT_FIFO_L_IMUX24_4", - "CMT_FIFO_L_IMUX45_11", - "CMT_FIFO_SW4END3_6", - "CMT_FIFO_EE4BEG0_9", - "CMT_FIFO_LH11_6", - "CMT_FIFO_L_IMUX28_5", - "CMT_FIFO_L_IMUX18_8", - "CMT_FIFO_L_LOGIC_OUTS9_3", - "CMT_FIFO_WW4B0_9", - "CMT_FIFO_LH2_8", - "CMT_FIFO_WW4A2_2", - "CMT_FIFO_NW2A0_1", - "CMT_IN_FIFO_Q31", - "CMT_FIFO_WW4B3_4", - "CMT_FIFO_L_IMUX6_2", - "CMT_FIFO_L_IMUX20_5", - "CMT_FIFO_L_IMUX29_9", - "CMT_FIFO_L_IMUX29_2", - "CMT_FIFO_SE4BEG1_3", - "CMT_FIFO_L_LOGIC_OUTS20_10", - "CMT_FIFO_L_LOGIC_OUTS15_9", - "CMT_FIFO_EE4A2_7", - "CMT_FIFO_L_IMUX37_9", - "CMT_FIFO_L_IMUX13_10", - "CMT_FIFO_EE2A1_9", - "CMT_FIFO_L_IMUX20_6", - "CMT_FIFO_EE4B3_10", - "CMT_FIFO_WW4B3_0", - "CMT_FIFO_ER1BEG0_9", - "CMT_FIFO_EL1BEG3_3", - "CMT_FIFO_LH8_5", - "CMT_OUT_FIFO_D57", - "CMT_FIFO_WW2A2_10", - "CMT_IN_FIFO_D81", - "CMT_FIFO_L_LOGIC_OUTS1_4", - "CMT_FIFO_WW4B1_6", - "CMT_IN_FIFO_D31", - "CMT_FIFO_EE4B3_0", - "CMT_FIFO_SE4BEG0_8", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", - "CMT_FIFO_L_FAN3_5", - "CMT_FIFO_L_LOGIC_OUTS5_5", - "CMT_FIFO_WW4B3_9", - "CMT_FIFO_WW2END0_9", - "CMT_FIFO_L_BYP3_6", - "CMT_FIFO_EE4B3_9", - "CMT_FIFO_NE2A2_2", - "CMT_FIFO_EE4BEG2_11", - "CMT_FIFO_L_IMUX7_3", - "CMT_FIFO_L_IMUX1_11", - "CMT_FIFO_EE4C1_6", - "CMT_FIFO_L_IMUX14_10", - "CMT_FIFO_SW4END1_1", - "CMT_FIFO_LH12_0", - "CMT_FIFO_NW2A0_11", - "CMT_FIFO_WW2A2_8", - "CMT_FIFO_L_LOGIC_OUTS4_9", - "CMT_FIFO_L_IMUX18_1", - "CMT_FIFO_L_LOGIC_OUTS0_2", - "CMT_FIFO_WR1END0_9", - "CMT_FIFO_L_IMUX45_2", - "CMT_IN_FIFO_D55", - "CMT_FIFO_L_IMUX37_4", - "CMT_FIFO_L_IMUX33_4", - "CMT_FIFO_WW4A2_1", - "CMT_FIFO_L_IMUX4_11", - "CMT_FIFO_L_IMUX3_5", - "CMT_FIFO_PHASER_TO_IO_ICLK_6", - "CMT_FIFO_L_LOGIC_OUTS13_7", - "CMT_IN_FIFO_D92", - "CMT_FIFO_SE4BEG1_5", - "CMT_FIFO_LH7_5", - "CMT_FIFO_LH1_6", - "CMT_FIFO_L_FAN5_7", - "CMT_FIFO_L_IMUX21_10", - "CMT_FIFO_SE4C3_9", - "CMT_FIFO_L_LOGIC_OUTS11_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_4", - "CMT_FIFO_SE4C1_1", - "CMT_FIFO_EE4BEG1_1", - "CMT_FIFO_L_IMUX3_0", - "CMT_FIFO_NE2A0_0", - "CMT_IN_FIFO_D33", - "CMT_FIFO_WW2A2_4", - "CMT_FIFO_L_BYP6_4", - "CMT_FIFO_L_BYP3_9", - "CMT_FIFO_L_LOGIC_OUTS6_8", - "CMT_FIFO_WW4A0_8", - "CMT_FIFO_WW4B2_9", - "CMT_FIFO_EE2A3_3", - "CMT_FIFO_EE2BEG0_5", - "CMT_FIFO_WW4C0_11", - "CMT_FIFO_SW4A3_10", - "CMT_FIFO_EE4BEG1_3", - "CMT_FIFO_SW4END3_2", - "CMT_FIFO_NW4A1_8", - "CMT_FIFO_SW2A3_4", - "CMT_FIFO_WW4C1_6", - "CMT_FIFO_L_IMUX28_7", - "CMT_FIFO_L_BYP4_0", - "CMT_FIFO_L_IMUX33_0", - "CMT_IN_FIFO_D30", - "CMT_FIFO_L_LOGIC_OUTS22_5", - "CMT_FIFO_EL1BEG3_0", - "CMT_FIFO_LH10_3", - "CMT_FIFO_L_IMUX8_8", - "CMT_FIFO_L_FAN3_8", - "CMT_FIFO_EE2A2_0", - "CMT_FIFO_EE2BEG1_9", - "CMT_FIFO_WR1END3_11", - "CMT_OUT_FIFO_EMPTY", - "CMT_IN_FIFO_Q47", - "CMT_FIFO_L_IMUX29_7", - "CMT_FIFO_WR1END2_0", - "CMT_FIFO_WW2A1_5", - "CMT_FIFO_L_LOGIC_OUTS19_3", - "CMT_FIFO_EE4B3_6", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", - "CMT_FIFO_L_IMUX38_6", - "CMT_FIFO_PHASER_TO_IO_ICLK_10", - "CMT_FIFO_LH1_10", - "CMT_FIFO_L_LOGIC_OUTS20_2", - "CMT_FIFO_SE4BEG2_11", - "CMT_IN_FIFO_Q91", - "CMT_OUT_FIFO_D81", - "CMT_FIFO_L_IMUX0_1", - "CMT_FIFO_SE4C2_11", - "CMT_FIFO_NE4BEG3_6", - "CMT_FIFO_L_LOGIC_OUTS22_1", - "CMT_FIFO_L_LOGIC_OUTS22_4", - "CMT_FIFO_L_IMUX41_7", - "CMT_FIFO_EE2BEG3_1", - "CMT_FIFO_L_IMUX47_8", - "CMT_FIFO_WL1END3_0", - "CMT_FIFO_MONITOR_P_11", - "CMT_IN_FIFO_D10", - "CMT_OUT_FIFO_D27", - "CMT_FIFO_NW2A1_5", - "CMT_FIFO_L_IMUX5_4", - "CMT_FIFO_SW2A0_5", - "CMT_FIFO_SE4BEG0_10", - "CMT_FIFO_L_IMUX43_7", - "CMT_FIFO_EE2A1_2", - "CMT_FIFO_L_IMUX0_7", - "CMT_IN_FIFO_Q50", - "CMT_FIFO_LH1_9", - "CMT_FIFO_L_FAN0_7", - "CMT_FIFO_SW4A0_0", - "CMT_FIFO_EE4B2_11", - "CMT_FIFO_L_BYP2_4", - "CMT_FIFO_L_CTRL0_8", - "CMT_FIFO_WW2END2_9", - "CMT_IN_FIFO_D93", - "CMT_FIFO_L_CTRL1_10", - "CMT_FIFO_WW4END0_8", - "CMT_FIFO_SE2A1_5", - "CMT_FIFO_NW4END0_5", - "CMT_FIFO_NE2A3_4", - "CMT_FIFO_L_IMUX31_1", - "CMT_FIFO_WR1END1_1", - "CMT_FIFO_WW4B1_9", - "CMT_FIFO_LH6_10", - "CMT_FIFO_EE4B0_8", - "CMT_FIFO_L_IMUX28_1", - "CMT_FIFO_L_BYP2_10", - "CMT_FIFO_L_IMUX18_0", - "CMT_OUT_FIFO_Q30", - "CMT_FIFO_L_LOGIC_OUTS6_0", - "CMT_FIFO_L_IMUX41_5", - "CMT_FIFO_L_IMUX27_0", - "CMT_FIFO_L_IMUX14_2", - "CMT_FIFO_EL1BEG0_9", - "CMT_FIFO_L_FAN5_0", - "CMT_FIFO_L_BYP0_2", - "CMT_FIFO_L_FAN3_0", - "CMT_FIFO_EL1BEG2_2", - "CMT_FIFO_SW4END0_0", - "CMT_FIFO_L_IMUX33_5", - "CMT_FIFO_L_LOGIC_OUTS6_9", - "CMT_FIFO_NE4C3_11", - "CMT_FIFO_LH4_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", - "CMT_FIFO_SE2A1_6", - "CMT_FIFO_SE4C3_1", - "CMT_FIFO_WW2A1_8", - "CMT_FIFO_WW2A0_9", - "CMT_FIFO_L_IMUX4_4", - "CMT_FIFO_L_CTRL0_2", - "CMT_FIFO_WW4B3_2", - "CMT_FIFO_EE4BEG3_2", - "CMT_FIFO_WW4END1_10", - "CMT_FIFO_SE4BEG3_11", - "CMT_FIFO_NW4A3_6", - "CMT_FIFO_L_IMUX8_10", - "CMT_FIFO_WL1END3_9", - "CMT_FIFO_L_IMUX19_5", - "CMT_FIFO_L_FAN1_9", - "CMT_FIFO_EL1BEG1_4", - "CMT_FIFO_L_IMUX21_7", - "CMT_FIFO_LH11_5", - "CMT_FIFO_WW4C2_5", - "CMT_FIFO_L_IMUX17_10", - "CMT_FIFO_L_LOGIC_OUTS21_3", - "CMT_FIFO_L_IMUX1_9", - "CMT_FIFO_EE4A0_2", - "CMT_FIFO_EE2A1_11", - "CMT_IN_FIFO_D62", - "CMT_FIFO_L_IMUX27_10", - "CMT_FIFO_L_IMUX9_7", - "CMT_FIFO_L_IMUX19_6", - "CMT_FIFO_L_CTRL0_7", - "CMT_FIFO_L_LOGIC_OUTS15_1", - "CMT_FIFO_EE4A2_4", - "FIFO_DQS_IOTOPHASER_4", - "CMT_FIFO_SW4END2_1", - "CMT_FIFO_L_LOGIC_OUTS11_6", - "CMT_IN_FIFO_Q86", - "CMT_FIFO_MONITOR_P_10", - "CMT_OUT_FIFO_Q73", - "CMT_FIFO_L_LOGIC_OUTS23_4", - "CMT_OUT_FIFO_D61", - "CMT_FIFO_L_LOGIC_OUTS13_4", - "CMT_FIFO_L_LOGIC_OUTS13_5", - "CMT_OUT_FIFO_D14", - "CMT_FIFO_MONITOR_P_8", - "CMT_FIFO_NW2A3_10", - "CMT_FIFO_WW2END0_1", - "CMT_FIFO_L_IMUX24_9", - "CMT_FIFO_L_IMUX27_9", - "CMT_FIFO_L_IMUX35_3", - "CMT_FIFO_SW4A3_6", - "CMT_FIFO_SE2A0_0", - "CMT_FIFO_L_BYP5_10", - "CMT_IN_FIFO_D21", - "CMT_FIFO_L_IMUX41_9", - "CMT_FIFO_LH3_5", - "CMT_FIFO_L_IMUX2_2", - "CMT_FIFO_L_IMUX7_10", - "CMT_FIFO_SW4A0_3", - "CMT_FIFO_EE4BEG2_6", - "CMT_FIFO_L_CLK1_9", - "CMT_FIFO_L_LOGIC_OUTS4_6", - "CMT_FIFO_L_LOGIC_OUTS0_5", - "CMT_FIFO_L_IMUX26_5", - "CMT_FIFO_NW2A3_1", - "CMT_FIFO_L_LOGIC_OUTS23_5", - "CMT_FIFO_L_LOGIC_OUTS13_2", - "CMT_FIFO_SE4BEG2_1", - "CMT_FIFO_L_IMUX26_8", - "CMT_FIFO_L_IMUX6_4", - "CMT_FIFO_WL1END2_9", - "CMT_FIFO_NE4C2_11", - "CMT_FIFO_WW4END2_10", - "CMT_FIFO_SW2A2_5", - "CMT_FIFO_EL1BEG3_8", - "CMT_FIFO_L_LOGIC_OUTS8_6", - "CMT_IN_FIFO_SCANOUT3", - "CMT_FIFO_WW4END3_9", - "CMT_OUT_FIFO_D71", - "CMT_FIFO_NE4BEG2_11", - "CMT_FIFO_L_IMUX23_9", - "CMT_FIFO_L_IMUX46_0", - "CMT_FIFO_LH7_6", - "CMT_FIFO_L_IMUX16_11", - "CMT_FIFO_WW4END2_5", - "CMT_FIFO_SW2A3_1", - "CMT_FIFO_EE4B1_10", - "CMT_FIFO_L_FAN4_9", - "CMT_FIFO_NE4C2_9", - "CMT_FIFO_NW4A3_8", - "CMT_FIFO_WW2END1_3", - "CMT_IN_FIFO_Q74", - "CMT_FIFO_EE2A0_2", - "CMT_FIFO_L_LOGIC_OUTS22_8", - "CMT_FIFO_L_FAN1_2", - "CMT_FIFO_EL1BEG0_11", - "CMT_FIFO_L_IMUX14_0", - "CMT_FIFO_LH1_3", - "CMT_FIFO_L_BYP7_4", - "CMT_FIFO_SW2A2_6", - "CMT_FIFO_SE2A0_1", - "CMT_FIFO_WW4B3_7", - "CMT_FIFO_L_LOGIC_OUTS2_9", - "CMT_FIFO_LH11_0", - "CMT_FIFO_SW2A3_0", - "CMT_FIFO_LH5_8", - "CMT_FIFO_L_LOGIC_OUTS3_3", - "CMT_FIFO_PHASER_TO_IO_ICLK_1", - "CMT_FIFO_L_LOGIC_OUTS19_4", - "CMT_FIFO_L_LOGIC_OUTS17_9", - "CMT_IN_FIFO_FULL", - "CMT_FIFO_SW4A0_1", - "CMT_FIFO_L_LOGIC_OUTS16_7", - "CMT_FIFO_L_LOGIC_OUTS19_11", - "CMT_FIFO_L_CLK1_8", - "CMT_FIFO_EE2A3_6", - "CMT_FIFO_L_FAN3_4", - "CMT_FIFO_WW4C0_7", - "CMT_FIFO_L_LOGIC_OUTS20_3", - "CMT_FIFO_WW2END3_10", - "CMT_FIFO_L_IMUX2_5", - "CMT_FIFO_ER1BEG3_5", - "CMT_FIFO_L_IMUX30_5", - "CMT_FIFO_L_IMUX16_4", - "CMT_FIFO_WW4END3_5", - "CMT_FIFO_WW4A0_4", - "CMT_FIFO_L_LOGIC_OUTS21_10", - "CMT_FIFO_LH12_3", - "CMT_FIFO_SW4END1_8", - "CMT_FIFO_NW4END1_0", - "CMT_FIFO_SW4A1_3", - "CMT_FIFO_L_FAN1_11", - "CMT_OUT_FIFO_D60", - "CMT_FIFO_EE4B2_9", - "CMT_FIFO_WW4C3_0", - "CMT_FIFO_NW4A1_9", - "CMT_FIFO_L_CLK0_5", - "CMT_FIFO_L_IMUX11_11", - "CMT_FIFO_WL1END0_7", - "CMT_FIFO_L_IMUX26_11", - "CMT_FIFO_SE4BEG1_1", - "CMT_FIFO_NE4C3_7", - "CMT_OUT_FIFO_D73", - "CMT_FIFO_L_BYP0_7", - "CMT_FIFO_WR1END2_5", - "CMT_FIFO_WW4A1_11", - "CMT_FIFO_SE4BEG3_8", - "CMT_FIFO_NW4A0_0", - "CMT_FIFO_WW2A1_1", - "CMT_FIFO_WR1END0_2", - "CMT_FIFO_LH10_0", - "CMT_IN_FIFO_Q83", - "CMT_FIFO_L_FAN7_3", - "CMT_IN_FIFO_Q85", - "CMT_OUT_FIFO_Q62", - "CMT_FIFO_L_IMUX45_5", - "CMT_FIFO_WW4C3_1", - "CMT_FIFO_LH1_5", - "CMT_FIFO_L_LOGIC_OUTS10_9", - "CMT_FIFO_WW2A2_9", - "CMT_FIFO_LH11_3", - "CMT_FIFO_SW4A0_2", - "CMT_FIFO_EE2A2_2", - "CMT_OUT_FIFO_TESTREADDISB", - "CMT_FIFO_SW2A3_9", - "CMT_FIFO_L_LOGIC_OUTS17_1", - "CMT_FIFO_WL1END0_9", - "CMT_FIFO_L_LOGIC_OUTS20_9", - "CMT_FIFO_EE4B0_0", - "CMT_FIFO_LH3_6", - "CMT_FIFO_EE2BEG1_10", - "CMT_FIFO_EE4B0_6", - "CMT_OUT_FIFO_WRCLK", - "CMT_FIFO_WW4END1_5", - "CMT_FIFO_L_FAN3_3", - "CMT_FIFO_L_CLK1_4", - "CMT_FIFO_NW4END3_9", - "CMT_FIFO_NE4C3_1", - "CMT_FIFO_L_FAN6_8", - "CMT_IN_FIFO_D72", - "CMT_FIFO_L_IMUX28_4", - "CMT_FIFO_L_IMUX30_6", - "CMT_IN_FIFO_Q03", - "CMT_FIFO_SE4BEG3_4", - "CMT_FIFO_EE4C2_8", - "CMT_FIFO_L_IMUX44_8", - "CMT_OUT_FIFO_FULL", - "CMT_FIFO_WL1END1_2", - "CMT_FIFO_LH9_1", - "CMT_FIFO_SW4END3_3", - "CMT_FIFO_WW4C0_5", - "CMT_FIFO_SE4BEG3_3", - "CMT_OUT_FIFO_Q93", - "CMT_FIFO_WW2A1_6", - "CMT_FIFO_WW2END0_8", - "CMT_FIFO_EE2BEG3_10", - "CMT_FIFO_LH5_3", - "CMT_FIFO_L_IMUX37_1", - "CMT_FIFO_L_BYP7_3", - "CMT_FIFO_L_IMUX3_2", - "CMT_FIFO_L_LOGIC_OUTS14_0", - "CMT_FIFO_WW4A0_9", - "CMT_FIFO_WL1END3_3", - "CMT_FIFO_SW4A0_9", - "CMT_FIFO_SE4C3_3", - "CMT_OUT_FIFO_WREN", - "CMT_FIFO_ER1BEG1_9", - "CMT_FIFO_L_LOGIC_OUTS17_2", - "CMT_IN_FIFO_Q16", - "CMT_FIFO_PHASER_TO_IO_ICLK_2", - "CMT_FIFO_SE4C1_3", - "CMT_FIFO_NW4END1_9", - "CMT_FIFO_EE4BEG3_5", - "CMT_FIFO_NE4BEG0_10", - "CMT_IN_FIFO_Q34", - "CMT_FIFO_L_LOGIC_OUTS6_4", - "CMT_FIFO_WW4END0_0", - "CMT_FIFO_SE2A1_9", - "CMT_FIFO_L_LOGIC_OUTS6_11", - "CMT_FIFO_L_IMUX39_6", - "CMT_FIFO_L_IMUX8_3", - "CMT_FIFO_NE2A3_1", - "CMT_FIFO_SE4C3_7", - "CMT_FIFO_L_IMUX38_9", - "CMT_FIFO_L_LOGIC_OUTS7_8", - "CMT_FIFO_L_IMUX15_9", - "CMT_FIFO_L_IMUX42_5", - "CMT_FIFO_EE4A3_9", - "CMT_FIFO_WW4C0_9", - "CMT_FIFO_NW4END0_0", - "CMT_FIFO_L_BYP7_2", - "CMT_FIFO_L_IMUX38_3", - "CMT_FIFO_L_BYP5_1", - "CMT_FIFO_L_LOGIC_OUTS2_2", - "CMT_FIFO_WW4C2_3", - "CMT_FIFO_NW2A2_11", - "CMT_FIFO_L_FAN1_5", - "CMT_FIFO_L_FAN2_11", - "CMT_FIFO_EE2BEG0_0", - "CMT_FIFO_WW2A3_5", - "CMT_FIFO_WL1END3_11", - "CMT_FIFO_L_IMUX10_3", - "CMT_FIFO_L_BYP2_2", - "CMT_FIFO_L_IMUX18_5", - "CMT_FIFO_L_IMUX41_11", - "CMT_FIFO_WR1END1_7", - "CMT_FIFO_NE4C2_4", - "CMT_FIFO_L_BYP5_0", - "CMT_FIFO_L_LOGIC_OUTS8_9", - "CMT_FIFO_L_IMUX20_1", - "CMT_FIFO_L_IMUX24_7", - "CMT_FIFO_L_IMUX10_7", - "CMT_FIFO_L_LOGIC_OUTS17_10", - "CMT_FIFO_WW4C3_2", - "CMT_FIFO_NE4BEG0_7", - "CMT_FIFO_L_BYP7_5", - "CMT_FIFO_SE2A2_11", - "CMT_FIFO_EL1BEG3_5", - "CMT_FIFO_L_IMUX32_0", - "CMT_FIFO_L_BYP4_1", - "CMT_FIFO_SW2A1_7", - "CMT_FIFO_NE2A3_2", - "CMT_FIFO_L_LOGIC_OUTS6_10", - "CMT_FIFO_WW2A3_3", - "CMT_FIFO_SW4A2_2", - "CMT_FIFO_L_IMUX40_0", - "CMT_FIFO_WL1END1_10", - "CMT_FIFO_L_LOGIC_OUTS4_7", - "CMT_FIFO_L_IMUX19_0", - "CMT_FIFO_ER1BEG2_7", - "CMT_FIFO_PHASER_TO_IO_ICLK_11", - "CMT_FIFO_L_FAN0_8", - "CMT_FIFO_EE4B0_3", - "CMT_FIFO_L_IMUX11_4", - "CMT_FIFO_L_IMUX35_8", - "CMT_FIFO_L_LOGIC_OUTS12_5", - "CMT_FIFO_L_IMUX40_5", - "CMT_FIFO_EE2A1_6", - "CMT_FIFO_L_CTRL0_4", - "CMT_FIFO_L_LOGIC_OUTS21_4", - "CMT_FIFO_L_CLK1_11", - "CMT_FIFO_NE4BEG1_0", - "CMT_FIFO_SW4A0_5", - "CMT_IN_FIFO_Q40", - "CMT_FIFO_EE4B2_6", - "CMT_FIFO_L_LOGIC_OUTS8_3", - "CMT_FIFO_L_FAN3_1", - "CMT_FIFO_L_IMUX8_1", - "CMT_OUT_FIFO_Q32", - "CMT_FIFO_L_LOGIC_OUTS21_2", - "CMT_FIFO_SE2A2_2", - "CMT_FIFO_NE4BEG3_4", - "CMT_FIFO_L_LOGIC_OUTS5_11", - "CMT_FIFO_WW4END0_7", - "CMT_FIFO_L_BYP5_6", - "CMT_IN_FIFO_Q71", - "CMT_FIFO_LH8_3", - "CMT_FIFO_L_LOGIC_OUTS20_8", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", - "CMT_FIFO_L_LOGIC_OUTS19_1", - "CMT_FIFO_WW4B1_1", - "CMT_FIFO_NW2A3_2", - "CMT_FIFO_LH2_2", - "CMT_FIFO_SW4A1_7", - "CMT_FIFO_L_IMUX42_0", - "CMT_FIFO_L_IMUX37_8", - "CMT_FIFO_L_IMUX40_1", - "CMT_FIFO_NW4A2_1", - "CMT_FIFO_EE2A2_1", - "CMT_IN_FIFO_Q72", - "CMT_FIFO_WW4C1_5", - "CMT_FIFO_L_IMUX4_3", - "CMT_FIFO_L_IMUX46_10", - "CMT_FIFO_MONITOR_P_3", - "CMT_IN_FIFO_D82", - "CMT_FIFO_SW2A2_4", - "CMT_FIFO_WW4C1_0", - "CMT_FIFO_EE4B0_1", - "CMT_FIFO_EE4B1_4", - "CMT_FIFO_L_IMUX34_0", - "CMT_FIFO_L_IMUX14_7", - "CMT_FIFO_L_IMUX0_2", - "CMT_FIFO_NE4BEG2_10", - "CMT_FIFO_WW4A3_1", - "CMT_FIFO_L_IMUX43_11", - "CMT_FIFO_ER1BEG3_11", - "CMT_FIFO_L_LOGIC_OUTS22_9", - "CMT_FIFO_L_IMUX33_6", - "CMT_IN_FIFO_Q24", - "CMT_FIFO_EE2BEG2_1", - "CMT_FIFO_SE4BEG3_9", - "CMT_FIFO_L_LOGIC_OUTS2_4", - "CMT_FIFO_NW2A0_4", - "CMT_FIFO_EE2BEG0_6", - "CMT_FIFO_L_IMUX29_1", - "CMT_FIFO_L_IMUX31_2", - "CMT_FIFO_NE4BEG0_2", - "CMT_FIFO_NW4A2_4", - "CMT_FIFO_L_LOGIC_OUTS19_9", - "CMT_FIFO_NE4C1_8", - "CMT_IN_FIFO_D70", - "CMT_FIFO_L_LOGIC_OUTS1_8", - "CMT_FIFO_L_LOGIC_OUTS8_11", - "CMT_FIFO_NW2A3_11", - "CMT_FIFO_L_BYP1_9", - "CMT_FIFO_SE2A2_10", - "CMT_FIFO_L_LOGIC_OUTS23_9", - "CMT_FIFO_WW2END2_5", - "CMT_FIFO_L_FAN0_3", - "CMT_FIFO_L_IMUX8_9", - "CMT_OUT_FIFO_Q60", - "CMT_IN_FIFO_Q02", - "CMT_IN_FIFO_Q55", - "CMT_FIFO_EE4BEG3_7", - "CMT_FIFO_SW2A2_10", - "CMT_FIFO_LH10_6", - "CMT_IN_FIFO_Q27", - "CMT_FIFO_WW2END0_7", - "CMT_FIFO_L_IMUX5_6", - "CMT_FIFO_ER1BEG2_9", - "CMT_FIFO_L_IMUX27_11", - "CMT_FIFO_NE2A0_1", - "CMT_FIFO_SW4END2_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_11", - "CMT_FIFO_NW4END1_11", - "CMT_FIFO_SE4C0_3", - "CMT_FIFO_L_FAN3_9", - "CMT_FIFO_L_IMUX12_10", - "CMT_FIFO_L_BYP2_6", - "CMT_FIFO_L_IMUX41_6", - "CMT_FIFO_EE4B1_8", - "CMT_FIFO_WW4C0_2", - "CMT_FIFO_L_IMUX9_9", - "CMT_FIFO_L_FAN6_7", - "CMT_OUT_FIFO_D32", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", - "CMT_FIFO_WL1END1_11", - "CMT_FIFO_WW4END3_3", - "CMT_FIFO_EE4C3_8", - "CMT_FIFO_WW4END0_4", - "CMT_FIFO_L_IMUX34_2", - "CMT_FIFO_EE2BEG1_7", - "CMT_FIFO_L_IMUX22_6", - "CMT_FIFO_NW4A1_4", - "CMT_FIFO_L_LOGIC_OUTS12_8", - "CMT_FIFO_WW2A3_7", - "CMT_FIFO_L_IMUX25_3", - "CMT_FIFO_L_LOGIC_OUTS18_10", - "CMT_FIFO_NE4BEG1_8", - "CMT_FIFO_L_IMUX22_10", - "CMT_FIFO_NE4BEG0_9", - "CMT_FIFO_L_FAN4_8", - "CMT_FIFO_EE4C3_2", - "CMT_FIFO_EE4A3_11", - "CMT_FIFO_LH8_6", - "CMT_FIFO_L_BYP5_2", - "CMT_OUT_FIFO_D72", - "CMT_FIFO_L_IMUX47_6", - "CMT_FIFO_L_IMUX17_6", - "CMT_IN_FIFO_Q77", - "CMT_FIFO_NE4C3_8", - "CMT_FIFO_L_IMUX44_9", - "CMT_FIFO_SE4C3_11", - "CMT_FIFO_WW4A0_7", - "CMT_FIFO_NW4END1_4", - "CMT_FIFO_NE2A2_11", - "CMT_FIFO_L_IMUX34_1", - "CMT_FIFO_NW4A0_7", - "CMT_FIFO_LH7_7", - "CMT_FIFO_L_IMUX34_6", - "CMT_FIFO_NW2A2_0", - "CMT_FIFO_L_IMUX31_8", - "CMT_FIFO_NE2A1_11", - "CMT_FIFO_WW2END3_5", - "CMT_FIFO_L_IMUX8_5", - "CMT_FIFO_SE4C3_6", - "CMT_IN_FIFO_SCANENB", - "CMT_FIFO_NE2A0_7", - "CMT_FIFO_WW4B3_6", - "CMT_FIFO_L_LOGIC_OUTS6_5", - "CMT_OUT_FIFO_D94", - "CMT_FIFO_WW4A2_5", - "CMT_FIFO_NE2A1_4", - "CMT_FIFO_SE4C0_5", - "CMT_FIFO_WW4B0_0", - "CMT_FIFO_EE4B1_1", - "CMT_FIFO_SE4C2_2", - "CMT_FIFO_NE4BEG2_2", - "CMT_FIFO_EE4BEG0_7", - "CMT_FIFO_L_CTRL0_6", - "CMT_FIFO_L_LOGIC_OUTS4_11", - "CMT_FIFO_L_FAN1_7", - "CMT_OUT_FIFO_Q11", - "CMT_FIFO_SW2A0_0", - "CMT_FIFO_NE4C3_9", - "FIFO_DQS_IOTOPHASER_6", - "CMT_FIFO_WW4B1_2", - "CMT_FIFO_EE2BEG0_4", - "CMT_FIFO_L_IMUX38_5", - "CMT_FIFO_SW2A3_5", - "CMT_FIFO_ER1BEG3_4", - "CMT_FIFO_WW4C2_4", - "CMT_FIFO_NE4C0_0", - "CMT_FIFO_L_FAN0_11", - "CMT_FIFO_L_IMUX36_1", - "CMT_OUT_FIFO_D22", - "CMT_OUT_FIFO_SCANOUT3", - "CMT_FIFO_LH4_11", - "CMT_FIFO_L_IMUX42_7", - "CMT_IN_FIFO_WRCLK", - "CMT_FIFO_L_IMUX0_6", - "CMT_FIFO_L_FAN4_10", - "CMT_FIFO_L_IMUX31_4", - "CMT_FIFO_L_IMUX45_7", - "CMT_FIFO_EE4A3_2", - "CMT_FIFO_L_FAN7_4", - "FIFO_DQS_IOTOPHASER_5", - "CMT_FIFO_WW4A3_5", - "CMT_FIFO_WW2A0_7", - "CMT_FIFO_L_LOGIC_OUTS13_3", - "CMT_FIFO_L_IMUX28_9", - "CMT_OUT_FIFO_Q56", - "CMT_FIFO_L_IMUX10_5", - "CMT_OUT_FIFO_D62", - "CMT_FIFO_L_IMUX10_10", - "CMT_FIFO_SW4A1_6", - "CMT_OUT_FIFO_D80", - "CMT_FIFO_SW2A0_2", - "FIFO_DQS_IOTOPHASER_55", - "CMT_FIFO_WW4A1_1", - "CMT_OUT_FIFO_Q53", - "CMT_FIFO_L_LOGIC_OUTS0_6", - "CMT_FIFO_NE4C0_9", - "CMT_FIFO_L_LOGIC_OUTS5_8", - "CMT_FIFO_L_IMUX24_5", - "CMT_FIFO_L_IMUX20_9", - "CMT_FIFO_EL1BEG1_11", - "CMT_FIFO_WW2A2_2", - "CMT_FIFO_L_IMUX35_5", - "CMT_FIFO_LH11_1", - "CMT_FIFO_L_LOGIC_OUTS0_8", - "CMT_OUT_FIFO_Q13", - "CMT_FIFO_L_LOGIC_OUTS23_0", - "CMT_FIFO_NE4C1_11", - "CMT_FIFO_EE2BEG0_7", - "CMT_FIFO_SW2A3_10", - "CMT_FIFO_L_LOGIC_OUTS16_1", - "CMT_FIFO_SW2A1_1", - "CMT_FIFO_L_IMUX44_5", - "CMT_FIFO_LH10_7", - "CMT_FIFO_L_IMUX44_0", - "CMT_FIFO_WW4A0_3", - "CMT_FIFO_NW4END0_11", - "CMT_FIFO_L_CLK1_7", - "CMT_FIFO_EE4BEG0_3", - "CMT_FIFO_NW4END2_1", - "CMT_FIFO_L_FAN7_5", - "CMT_FIFO_L_IMUX36_4", - "CMT_FIFO_SE2A0_10", - "CMT_FIFO_EE4C0_7", - "CMT_FIFO_L_IMUX24_6", - "CMT_FIFO_L_IMUX8_2", - "CMT_FIFO_L_LOGIC_OUTS2_3", - "CMT_FIFO_L_IMUX6_9", - "CMT_FIFO_WR1END0_5", - "CMT_FIFO_WW2A0_11", - "CMT_IN_FIFO_Q97", - "CMT_FIFO_EE4A0_7", - "CMT_FIFO_LH9_9", - "CMT_FIFO_EL1BEG0_7", - "CMT_FIFO_WW2END3_1", - "CMT_FIFO_EE2BEG0_11", - "CMT_FIFO_L_LOGIC_OUTS15_2", - "CMT_FIFO_L_LOGIC_OUTS22_0", - "CMT_FIFO_L_IMUX23_10", - "CMT_FIFO_L_FAN4_5", - "CMT_FIFO_L_IMUX19_7", - "CMT_FIFO_NW4END0_9", - "CMT_FIFO_L_IMUX34_8", - "CMT_FIFO_EE4C0_2", - "CMT_FIFO_SW4END0_11", - "CMT_FIFO_SE2A3_4", - "CMT_FIFO_L_CTRL1_9", - "CMT_FIFO_NW4END3_2", - "CMT_FIFO_L_IMUX37_7", - "CMT_FIFO_L_IMUX39_7", - "CMT_FIFO_LH10_5", - "CMT_IN_FIFO_D63", - "CMT_FIFO_L_IMUX2_4", - "CMT_FIFO_L_IMUX20_8", - "CMT_FIFO_L_LOGIC_OUTS17_8", - "CMT_IN_FIFO_TESTMODEB", - "CMT_FIFO_L_FAN2_10", - "CMT_FIFO_L_IMUX21_8", - "CMT_OUT_FIFO_D24", - "CMT_FIFO_L_BYP5_3", - "CMT_FIFO_L_LOGIC_OUTS21_5", - "CMT_FIFO_L_CLK1_5", - "CMT_FIFO_WW2END1_8", - "CMT_FIFO_EE2A3_10", - "CMT_FIFO_L_IMUX31_3", - "CMT_FIFO_EE2BEG2_0", - "CMT_FIFO_L_IMUX4_2", - "CMT_FIFO_NW4A1_0", - "CMT_FIFO_L_BYP6_2", - "CMT_IN_FIFO_D53", - "CMT_FIFO_L_FAN1_4", - "CMT_FIFO_NE4BEG1_10", - "CMT_OUT_FIFO_D92", - "CMT_OUT_FIFO_D54", - "CMT_FIFO_L_BYP4_7", - "CMT_FIFO_L_LOGIC_OUTS3_4", - "CMT_FIFO_SW4A2_6", - "CMT_OUT_FIFO_Q20", - "CMT_FIFO_SE2A2_9", - "CMT_FIFO_L_IMUX41_4", - "CMT_FIFO_L_IMUX12_1", - "CMT_FIFO_L_IMUX41_0", - "CMT_FIFO_L_LOGIC_OUTS9_8", - "CMT_FIFO_L_LOGIC_OUTS11_8", - "CMT_FIFO_L_IMUX44_2", - "CMT_FIFO_L_CTRL1_0", - "CMT_IN_FIFO_Q20", - "CMT_FIFO_WW4C0_8", - "CMT_FIFO_EL1BEG3_4", - "CMT_FIFO_EE4B0_2", - "CMT_FIFO_WW2A0_1", - "CMT_FIFO_ER1BEG1_6", - "CMT_FIFO_EE4B0_11", - "CMT_FIFO_WW4B1_5", - "CMT_FIFO_PHASER_TO_IO_ICLK_0", - "CMT_FIFO_WW4END0_6", - "CMT_FIFO_WW4END0_10", - "CMT_FIFO_LH7_0", - "CMT_FIFO_L_IMUX35_4", - "CMT_FIFO_WW4B0_10", - "CMT_FIFO_SE4C1_8", - "CMT_FIFO_NE4C0_4", - "CMT_FIFO_L_IMUX1_7", - "CMT_FIFO_L_IMUX41_2", - "CMT_FIFO_L_FAN3_6", - "CMT_FIFO_L_LOGIC_OUTS19_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_8", - "CMT_FIFO_L_IMUX43_5", - "CMT_FIFO_L_IMUX7_2", - "CMT_FIFO_WW2A1_4", - "CMT_FIFO_SE2A3_3", - "CMT_FIFO_SW4END1_6", - "CMT_FIFO_WR1END3_4", - "CMT_FIFO_WW2END0_3", - "CMT_FIFO_SE4BEG1_4", - "CMT_FIFO_L_LOGIC_OUTS6_1", - "CMT_FIFO_NE4BEG3_10", - "CMT_FIFO_L_LOGIC_OUTS10_8", - "CMT_FIFO_NE4C1_4", - "CMT_FIFO_WW2A0_0", - "CMT_FIFO_EE2A3_0", - "CMT_FIFO_SE2A3_1", - "CMT_FIFO_L_IMUX4_6", - "CMT_FIFO_EE4A1_10", - "CMT_FIFO_L_IMUX46_8", - "CMT_FIFO_L_FAN2_0", - "CMT_FIFO_ER1BEG0_8", - "CMT_OUT_FIFO_D31", - "CMT_FIFO_ER1BEG2_1", - "CMT_FIFO_EE4C2_1", - "CMT_FIFO_NE4BEG0_11", - "CMT_FIFO_WR1END0_10", - "CMT_FIFO_LH4_3", - "CMT_FIFO_L_IMUX39_10", - "CMT_FIFO_SW2A2_1", - "CMT_FIFO_EE4C2_6", - "CMT_FIFO_SE4C3_5", - "CMT_FIFO_LH6_1", - "CMT_OUT_FIFO_D10", - "CMT_FIFO_L_IMUX31_0", - "CMT_FIFO_LH6_0", - "CMT_OUT_FIFO_D93", - "CMT_IN_FIFO_D65", - "CMT_FIFO_L_LOGIC_OUTS5_10", - "CMT_FIFO_EE4A0_9", - "CMT_FIFO_L_IMUX18_9", - "CMT_IN_FIFO_Q01", - "CMT_FIFO_LH8_9", - "CMT_FIFO_L_LOGIC_OUTS18_1", - "CMT_FIFO_L_IMUX15_2", - "CMT_FIFO_NW4A1_3", - "CMT_OUT_FIFO_SCANIN3", - "CMT_FIFO_SE4BEG3_5", - "CMT_FIFO_LH5_10", - "CMT_FIFO_L_IMUX12_9", - "CMT_FIFO_SW4END0_5", - "CMT_OUT_FIFO_D00", - "CMT_FIFO_L_BYP2_5", - "CMT_OUT_FIFO_RDEN", - "CMT_FIFO_L_IMUX34_7", - "CMT_FIFO_SW2A2_3", - "CMT_FIFO_L_LOGIC_OUTS14_1", - "CMT_FIFO_L_IMUX45_0", - "CMT_FIFO_L_IMUX5_8", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_1", - "CMT_FIFO_NW2A3_7", - "CMT_FIFO_L_IMUX42_4", - "CMT_FIFO_EE4BEG1_6", - "CMT_FIFO_WW4END3_2", - "CMT_FIFO_LH6_8", - "CMT_FIFO_L_LOGIC_OUTS12_9", - "CMT_FIFO_EE4B1_7", - "CMT_FIFO_L_LOGIC_OUTS0_0", - "CMT_IN_FIFO_WREN", - "CMT_FIFO_L_IMUX25_7", - "CMT_FIFO_WW2END3_7", - "CMT_FIFO_SE4C2_6", - "CMT_FIFO_SW4END3_8", - "CMT_FIFO_L_IMUX23_3", - "CMT_OUT_FIFO_D64", - "CMT_IN_FIFO_Q44", - "CMT_FIFO_L_IMUX16_3", - "CMT_FIFO_WL1END2_7", - "CMT_FIFO_LH7_4", - "CMT_FIFO_L_IMUX28_8", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", - "CMT_OUT_FIFO_D12", - "CMT_FIFO_SE4BEG1_0", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", - "CMT_FIFO_NW2A1_7", - "CMT_FIFO_L_IMUX19_4", - "CMT_IN_FIFO_D54", - "CMT_FIFO_L_IMUX15_7", - "CMT_FIFO_L_IMUX10_8", - "CMT_FIFO_WW2A2_3", - "CMT_FIFO_L_PHASER_WRENABLE", - "CMT_FIFO_SW4A3_7", - "CMT_FIFO_L_IMUX31_6", - "CMT_FIFO_L_IMUX37_2", - "CMT_FIFO_NW2A2_8", - "CMT_FIFO_NW2A3_3", - "CMT_FIFO_EE4A0_3", - "CMT_FIFO_LH3_4", - "CMT_FIFO_SW2A1_2", - "CMT_FIFO_L_IMUX1_1", - "CMT_IN_FIFO_RDEN", - "CMT_FIFO_L_BYP7_7", - "CMT_FIFO_LH11_8", - "CMT_FIFO_L_IMUX21_5", - "CMT_IN_FIFO_Q35", - "CMT_FIFO_L_IMUX24_2", - "CMT_FIFO_NW4A2_8", - "CMT_FIFO_L_IMUX26_3", - "CMT_FIFO_WW2END3_3", - "CMT_FIFO_ER1BEG1_3", - "CMT_FIFO_L_CTRL0_3", - "CMT_FIFO_SE2A0_3", - "CMT_OUT_FIFO_D77", - "CMT_FIFO_WW2A1_2", - "CMT_FIFO_L_IMUX27_7", - "CMT_FIFO_MONITOR_N_7", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", - "CMT_FIFO_LH11_9", - "CMT_OUT_FIFO_D66", - "CMT_FIFO_NW4END1_10", - "CMT_FIFO_WW4A0_10", - "CMT_FIFO_EE4A3_1", - "CMT_FIFO_L_IMUX38_1", - "CMT_FIFO_EE2BEG3_4", - "CMT_FIFO_L_IMUX7_7", - "CMT_FIFO_L_BYP6_8", - "CMT_FIFO_L_IMUX10_9", - "CMT_FIFO_L_BYP7_0", - "CMT_FIFO_L_LOGIC_OUTS22_10", - "CMT_FIFO_L_IMUX6_8", - "CMT_FIFO_L_IMUX6_11", - "CMT_FIFO_SE4BEG1_8", - "CMT_FIFO_L_IMUX7_1", - "CMT_FIFO_WW2END0_0", - "CMT_IN_FIFO_SCANIN2", - "CMT_FIFO_WW4END1_7", - "CMT_FIFO_L_FAN4_11", - "CMT_FIFO_L_IMUX36_8", - "CMT_FIFO_LH5_11", - "CMT_FIFO_MONITOR_N_2", - "CMT_FIFO_WR1END3_2", - "CMT_FIFO_WW4END0_9", - "CMT_FIFO_SE4BEG3_6", - "CMT_FIFO_L_IMUX27_6", - "CMT_FIFO_LH9_3", - "CMT_FIFO_LH10_4", - "CMT_OUT_FIFO_Q41", - "CMT_FIFO_WW2END3_9", - "CMT_FIFO_L_IMUX27_4", - "CMT_OUT_FIFO_Q01", - "CMT_FIFO_L_LOGIC_OUTS5_0", - "CMT_FIFO_L_LOGIC_OUTS12_10", - "CMT_FIFO_EE4C2_10", - "CMT_FIFO_SW4END0_4", - "CMT_IN_FIFO_Q05", - "CMT_FIFO_WR1END2_2", - "CMT_FIFO_L_IMUX40_10", - "CMT_FIFO_EE4B2_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", - "CMT_OUT_FIFO_SCANOUT0", - "CMT_FIFO_EE4A2_9", - "CMT_FIFO_EE4BEG0_2", - "CMT_FIFO_L_BYP1_6", - "CMT_FIFO_EE4A2_6", - "CMT_FIFO_L_IMUX40_3", - "CMT_FIFO_L_IMUX31_11", - "CMT_FIFO_L_BYP2_7", - "CMT_FIFO_SW2A1_4", - "CMT_FIFO_L_LOGIC_OUTS0_11", - "CMT_FIFO_NE4C2_6", - "CMT_FIFO_LH4_7", - "CMT_FIFO_L_IMUX5_2", - "CMT_FIFO_L_IMUX5_11", - "CMT_FIFO_NW4END3_7", - "CMT_FIFO_ER1BEG1_4", - "CMT_FIFO_EE4C3_0", - "CMT_FIFO_WW2A2_11", - "CMT_FIFO_NE2A2_0", - "CMT_FIFO_NW4A3_2", - "CMT_FIFO_L_IMUX26_10", - "CMT_FIFO_LH5_2", - "CMT_FIFO_SE4BEG0_11", - "CMT_FIFO_SE4BEG0_6", - "CMT_FIFO_L_LOGIC_OUTS15_0", - "CMT_FIFO_L_IMUX40_6", - "CMT_IN_FIFO_Q75", - "CMT_FIFO_EE4B0_7", - "CMT_FIFO_EE4BEG1_10", - "CMT_FIFO_NE4BEG2_6", - "CMT_FIFO_WW4A1_6", - "CMT_FIFO_L_LOGIC_OUTS3_1", - "FIFO_DQS_IOTOPHASER_33", - "CMT_FIFO_L_IMUX39_3", - "CMT_FIFO_LH1_0", - "CMT_FIFO_EE4BEG3_9", - "CMT_FIFO_NW4END3_11", - "CMT_FIFO_WW2END1_4", - "CMT_FIFO_L_CLK1_6", - "CMT_FIFO_L_IMUX21_2", - "CMT_FIFO_SE4C2_7", - "CMT_FIFO_L_FAN7_9", - "CMT_FIFO_WW4B1_10", - "CMT_FIFO_EE2A2_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_2", - "CMT_FIFO_SW4A2_1", - "CMT_FIFO_SE4BEG0_0", - "CMT_FIFO_SW4END2_5", - "CMT_FIFO_NW2A1_0", - "CMT_FIFO_NE4BEG2_0", - "CMT_FIFO_EE4BEG2_1", - "CMT_FIFO_WW2A1_7", - "CMT_FIFO_L_FAN0_6", - "CMT_FIFO_L_IMUX43_3", - "CMT_FIFO_L_IMUX14_8", - "CMT_FIFO_EE4A1_6", - "CMT_FIFO_EE2BEG0_8", - "CMT_FIFO_NE4BEG3_1", - "CMT_FIFO_WW4A1_5", - "CMT_FIFO_EE4C1_2", - "CMT_FIFO_L_IMUX17_7", - "CMT_FIFO_NE4C0_10", - "CMT_FIFO_SE4BEG0_2", - "CMT_FIFO_NE2A1_8", - "CMT_FIFO_WW4B2_2", - "CMT_FIFO_NW2A0_6", - "CMT_FIFO_NW4A3_10", - "CMT_FIFO_NE2A0_5", - "CMT_FIFO_NW4A3_5", - "CMT_FIFO_NW2A1_1", - "CMT_FIFO_EE4BEG0_5", - "CMT_FIFO_EE2A0_11", - "CMT_FIFO_WW4A0_11", - "CMT_FIFO_L_IMUX35_7", - "CMT_IN_FIFO_D32", - "CMT_IN_FIFO_D66", - "CMT_FIFO_NW4END0_3", - "CMT_FIFO_L_BYP1_11", - "CMT_FIFO_L_LOGIC_OUTS1_7", - "CMT_FIFO_LH11_4", - "CMT_FIFO_L_LOGIC_OUTS23_6", - "CMT_FIFO_SE2A2_5", - "CMT_IN_FIFO_D67", - "CMT_FIFO_SW4END0_6", - "CMT_FIFO_WL1END3_8", - "CMT_FIFO_LH5_1", - "CMT_FIFO_SE2A3_11", - "CMT_FIFO_L_FAN6_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", - "CMT_FIFO_NW4END0_6", - "CMT_FIFO_EE4A3_5", - "CMT_FIFO_WL1END3_10", - "CMT_OUT_FIFO_D46", - "CMT_FIFO_WR1END2_8", - "CMT_FIFO_L_FAN6_9", - "CMT_FIFO_L_FAN4_4", - "CMT_FIFO_L_LOGIC_OUTS18_7", - "CMT_FIFO_L_BYP4_6", - "CMT_FIFO_L_LOGIC_OUTS7_9", - "CMT_FIFO_L_BYP1_0", - "FIFO_DQS_IOTOPHASER_3", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", - "CMT_FIFO_ER1BEG0_10", - "CMT_FIFO_EE4B2_2", - "CMT_FIFO_NW4A0_10", - "CMT_FIFO_EE4BEG3_8", - "CMT_IN_FIFO_RDCLK", - "CMT_FIFO_L_IMUX13_6", - "CMT_FIFO_NE4BEG3_3", - "CMT_FIFO_L_IMUX35_1", - "CMT_FIFO_L_LOGIC_OUTS10_7", - "CMT_IN_FIFO_Q51", - "CMT_FIFO_L_IMUX18_7", - "CMT_FIFO_L_FAN5_2", - "CMT_FIFO_WW4A3_11", - "CMT_FIFO_L_FAN7_11", - "CMT_FIFO_NE4C1_9", - "CMT_OUT_FIFO_D35", - "CMT_FIFO_EL1BEG2_9", - "CMT_FIFO_L_FAN0_4", - "CMT_FIFO_SE2A3_9", - "CMT_FIFO_WW4C0_6", - "CMT_FIFO_L_IMUX26_4", - "CMT_IN_FIFO_RESET", - "CMT_FIFO_L_LOGIC_OUTS7_1", - "CMT_FIFO_L_IMUX36_2", - "CMT_FIFO_SW4END2_4", - "CMT_FIFO_SW4A2_0", - "CMT_OUT_FIFO_TESTMODEB", - "CMT_FIFO_L_LOGIC_OUTS4_4", - "CMT_FIFO_NE2A1_0", - "CMT_FIFO_NW4END1_3", - "CMT_FIFO_L_LOGIC_OUTS9_10", - "CMT_FIFO_NE4C2_3", - "CMT_FIFO_SE4BEG3_2", - "CMT_FIFO_NW2A0_7", - "CMT_FIFO_WL1END0_0", - "CMT_FIFO_SW4END0_2", - "CMT_FIFO_SE4C1_4", - "CMT_FIFO_EE2A0_6", - "CMT_FIFO_WL1END3_1", - "CMT_FIFO_EE4BEG1_5", - "CMT_FIFO_LH9_5", - "CMT_FIFO_EE4B2_3", - "CMT_FIFO_NE2A2_6", - "CMT_FIFO_L_BYP3_2", - "CMT_FIFO_WW4A2_6", - "CMT_FIFO_EE2BEG0_2", - "CMT_FIFO_L_LOGIC_OUTS16_4", - "CMT_FIFO_EE4A0_11", - "CMT_FIFO_L_IMUX44_7", - "CMT_FIFO_L_BYP2_11", - "CMT_FIFO_L_IMUX18_10", - "CMT_FIFO_NW4END2_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", - "CMT_FIFO_NE4BEG0_4", - "CMT_FIFO_L_FAN0_5", - "CMT_FIFO_EE4B1_3", - "CMT_FIFO_WW4B1_4", - "CMT_FIFO_SW2A0_8", - "CMT_FIFO_LH12_11", - "CMT_FIFO_L_IMUX2_8", - "CMT_FIFO_NE4BEG3_9", - "CMT_FIFO_L_IMUX16_6", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", - "CMT_OUT_FIFO_SCANENB", - "CMT_FIFO_WW4C1_9", - "CMT_FIFO_L_BYP6_3", - "CMT_FIFO_SW4END1_10", - "CMT_FIFO_L_IMUX14_9", - "CMT_OUT_FIFO_D50", - "CMT_FIFO_L_IMUX17_4", - "CMT_FIFO_L_LOGIC_OUTS10_0", - "CMT_FIFO_WW4A0_1", - "CMT_FIFO_SE4BEG0_1", - "CMT_FIFO_L_BYP7_8", - "CMT_FIFO_NW4A2_7", - "CMT_FIFO_LH9_2", - "CMT_FIFO_EE4C2_4", - "CMT_FIFO_EL1BEG1_1", - "CMT_FIFO_L_IMUX34_10", - "CMT_FIFO_PHASER_TO_IO_ICLK_8", - "CMT_FIFO_EL1BEG1_6", - "CMT_FIFO_WW2A0_5", - "CMT_FIFO_WW4END0_11", - "CMT_FIFO_L_IMUX16_7", - "CMT_FIFO_L_IMUX15_10", - "CMT_FIFO_WW4A0_0", - "CMT_FIFO_LH10_1", - "CMT_FIFO_L_IMUX21_9", - "CMT_FIFO_L_IMUX22_1", - "CMT_FIFO_L_IMUX12_4", - "CMT_FIFO_WW4A2_11", - "CMT_FIFO_NW4A2_3", - "CMT_FIFO_EE2A3_5", - "CMT_FIFO_L_IMUX2_6", - "CMT_FIFO_ER1BEG2_8", - "CMT_FIFO_EE2BEG2_9", - "CMT_FIFO_L_IMUX47_2", - "CMT_FIFO_L_IMUX43_6", - "CMT_FIFO_L_LOGIC_OUTS15_4", - "CMT_FIFO_LH3_7", - "CMT_FIFO_L_LOGIC_OUTS14_11", - "CMT_FIFO_L_IMUX15_8", - "CMT_FIFO_EE4BEG0_6", - "CMT_FIFO_L_IMUX46_1", - "CMT_FIFO_L_IMUX37_10", - "CMT_OUT_FIFO_Q90", - "CMT_OUT_FIFO_Q52", - "CMT_FIFO_WR1END3_9", - "CMT_FIFO_SW4END2_3", - "CMT_FIFO_L_IMUX19_11", - "CMT_FIFO_WW4B2_8", - "CMT_FIFO_L_IMUX6_0", - "CMT_FIFO_L_FAN3_7", - "CMT_FIFO_L_IMUX31_7", - "CMT_FIFO_NW2A0_9", - "CMT_FIFO_L_CTRL0_1", - "CMT_FIFO_L_LOGIC_OUTS9_4", - "CMT_FIFO_L_LOGIC_OUTS12_11", - "CMT_FIFO_L_IMUX29_8", - "CMT_FIFO_SW4END3_0", - "CMT_FIFO_L_IMUX34_11", - "CMT_FIFO_L_BYP1_1", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", - "CMT_FIFO_EE4C1_4", - "CMT_IN_FIFO_Q11", - "CMT_FIFO_WR1END0_7", - "CMT_FIFO_L_LOGIC_OUTS17_11", - "CMT_FIFO_SW4A3_0", - "CMT_FIFO_NW4END3_0", - "CMT_FIFO_L_IMUX35_10", - "CMT_FIFO_L_IMUX36_10", - "CMT_FIFO_LH5_4", - "CMT_FIFO_ER1BEG3_3", - "CMT_FIFO_L_BYP3_0", - "CMT_FIFO_SW4END2_8", - "CMT_FIFO_WW2END1_1", - "CMT_FIFO_L_IMUX35_6", - "CMT_FIFO_NE2A2_4", - "CMT_FIFO_L_LOGIC_OUTS14_2", - "CMT_FIFO_NE4BEG0_6", - "CMT_FIFO_L_FAN4_6", - "CMT_FIFO_EL1BEG0_0", - "CMT_IN_FIFO_D20", - "CMT_FIFO_WW4A2_4", - "CMT_FIFO_NW2A0_10", - "CMT_FIFO_L_FAN0_0", - "CMT_FIFO_EE4B2_1", - "CMT_FIFO_WW4A3_4", - "CMT_FIFO_WR1END3_5", - "CMT_FIFO_SE4BEG2_4", - "CMT_FIFO_LH7_9", - "CMT_IN_FIFO_D57", - "CMT_FIFO_L_CLK0_4", - "CMT_FIFO_L_CTRL0_0", - "CMT_OUT_FIFO_D95", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", - "CMT_FIFO_L_IMUX25_6", - "CMT_FIFO_EE4BEG0_1", - "CMT_FIFO_EL1BEG2_5", - "CMT_FIFO_SW2A3_6", - "CMT_FIFO_L_IMUX30_0", - "CMT_OUT_FIFO_D37", - "CMT_FIFO_WR1END0_1", - "CMT_FIFO_L_IMUX2_1", - "CMT_IN_FIFO_Q57", - "CMT_FIFO_WW4C1_4", - "CMT_FIFO_LH1_2", - "CMT_FIFO_L_IMUX12_0", - "CMT_FIFO_NW2A3_5", - "CMT_FIFO_SE4BEG0_3", - "CMT_FIFO_WW4A3_2", - "CMT_FIFO_LH6_6", - "CMT_IN_FIFO_SCANIN0", - "CMT_FIFO_L_CLK0_8", - "CMT_FIFO_EL1BEG1_9", - "CMT_FIFO_EE4A1_11", - "CMT_FIFO_WL1END3_4", - "CMT_FIFO_SW4END3_10", - "CMT_FIFO_EL1BEG0_8", - "CMT_FIFO_L_IMUX26_9", - "CMT_FIFO_WW2A2_7", - "CMT_FIFO_WW4END1_0", - "CMT_FIFO_L_IMUX18_4", - "CMT_FIFO_L_IMUX13_9", - "CMT_FIFO_NW2A0_0", - "CMT_FIFO_L_IMUX27_5", - "CMT_FIFO_SE2A2_0", - "CMT_FIFO_L_IMUX33_9", - "CMT_FIFO_EE4B3_11", - "CMT_FIFO_ER1BEG3_9", - "CMT_FIFO_NW4A1_5", - "CMT_OUT_FIFO_D02", - "CMT_FIFO_L_LOGIC_OUTS20_6", - "CMT_FIFO_L_FAN6_4", - "CMT_FIFO_NW2A3_8", - "CMT_FIFO_WL1END0_1", - "CMT_FIFO_WL1END1_7", - "CMT_FIFO_L_LOGIC_OUTS22_6", - "CMT_FIFO_NE2A0_6", - "CMT_FIFO_L_IMUX44_1", - "CMT_FIFO_LH2_10", - "CMT_FIFO_EE4A0_6", - "CMT_FIFO_L_LOGIC_OUTS10_6", - "CMT_FIFO_SE2A3_8", - "CMT_FIFO_NE4C1_10", - "CMT_FIFO_WR1END0_8", - "CMT_FIFO_L_IMUX27_1", - "CMT_FIFO_L_LOGIC_OUTS11_10", - "CMT_FIFO_LH3_10", - "CMT_FIFO_NE4C0_7", - "CMT_FIFO_EE2BEG1_8", - "CMT_FIFO_WW4END2_7", - "CMT_FIFO_L_IMUX0_3", - "CMT_IN_FIFO_EMPTY", - "CMT_IN_FIFO_ALMOSTFULL", - "CMT_OUT_FIFO_D42", - "CMT_FIFO_WW4END0_5", - "CMT_FIFO_EE4A1_8", - "CMT_FIFO_EL1BEG0_2", - "CMT_FIFO_L_BYP0_10", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", - "CMT_FIFO_EE4A3_10", - "CMT_FIFO_L_IMUX13_7", - "CMT_FIFO_L_IMUX6_1", - "CMT_FIFO_SE4C0_9", - "CMT_FIFO_SE4C2_5", - "CMT_FIFO_WW4C2_10", - "CMT_FIFO_L_IMUX25_1", - "CMT_FIFO_NW4A0_2", - "CMT_FIFO_L_IMUX8_11", - "CMT_FIFO_L_LOGIC_OUTS13_9", - "CMT_FIFO_SE4BEG3_0", - "CMT_FIFO_NE4BEG2_5", - "CMT_FIFO_L_LOGIC_OUTS16_5", - "FIFO_DQS_IOTOPHASER_22", - "CMT_FIFO_WL1END0_11", - "CMT_FIFO_NE4BEG0_3", - "CMT_FIFO_WW4C2_6", - "CMT_FIFO_WL1END1_3", - "CMT_FIFO_EL1BEG2_8", - "CMT_FIFO_L_IMUX11_3", - "CMT_FIFO_LH2_3", - "CMT_IN_FIFO_Q46", - "CMT_FIFO_L_CTRL1_11", - "CMT_FIFO_SW2A1_0" - ], - "sites": [ - { - "prefix": "OUT_FIFO", - "y_coord": 0, - "type": "OUT_FIFO", - "site_pins": { - "D92": "CMT_OUT_FIFO_D92", - "Q53": "CMT_OUT_FIFO_Q53", - "D12": "CMT_OUT_FIFO_D12", - "RDCLK": "CMT_OUT_FIFO_RDCLK", - "D82": "CMT_OUT_FIFO_D82", - "D30": "CMT_OUT_FIFO_D30", - "Q01": "CMT_OUT_FIFO_Q01", - "Q57": "CMT_OUT_FIFO_Q57", - "D14": "CMT_OUT_FIFO_D14", - "Q11": "CMT_OUT_FIFO_Q11", - "D05": "CMT_OUT_FIFO_D05", - "Q40": "CMT_OUT_FIFO_Q40", - "D21": "CMT_OUT_FIFO_D21", - "TESTWRITEDISB": "CMT_OUT_FIFO_TESTWRITEDISB", - "D35": "CMT_OUT_FIFO_D35", - "D62": "CMT_OUT_FIFO_D62", - "Q82": "CMT_OUT_FIFO_Q82", - "D26": "CMT_OUT_FIFO_D26", - "Q43": "CMT_OUT_FIFO_Q43", - "Q90": "CMT_OUT_FIFO_Q90", - "D71": "CMT_OUT_FIFO_D71", - "Q00": "CMT_OUT_FIFO_Q00", - "D41": "CMT_OUT_FIFO_D41", - "D80": "CMT_OUT_FIFO_D80", - "SCANIN2": "CMT_OUT_FIFO_SCANIN2", - "D51": "CMT_OUT_FIFO_D51", - "D93": "CMT_OUT_FIFO_D93", - "D47": "CMT_OUT_FIFO_D47", - "D07": "CMT_OUT_FIFO_D07", - "Q93": "CMT_OUT_FIFO_Q93", - "Q51": "CMT_OUT_FIFO_Q51", - "Q91": "CMT_OUT_FIFO_Q91", - "D45": "CMT_OUT_FIFO_D45", - "Q42": "CMT_OUT_FIFO_Q42", - "Q80": "CMT_OUT_FIFO_Q80", - "D44": "CMT_OUT_FIFO_D44", - "D42": "CMT_OUT_FIFO_D42", - "Q10": "CMT_OUT_FIFO_Q10", - "SCANIN1": "CMT_OUT_FIFO_SCANIN1", - "Q52": "CMT_OUT_FIFO_Q52", - "D94": "CMT_OUT_FIFO_D94", - "D83": "CMT_OUT_FIFO_D83", - "Q66": "CMT_OUT_FIFO_Q66", - "ALMOSTEMPTY": "CMT_OUT_FIFO_ALMOSTEMPTY", - "Q23": "CMT_OUT_FIFO_Q23", - "Q73": "CMT_OUT_FIFO_Q73", - "D22": "CMT_OUT_FIFO_D22", - "D76": "CMT_OUT_FIFO_D76", - "D86": "CMT_OUT_FIFO_D86", - "D36": "CMT_OUT_FIFO_D36", - "Q54": "CMT_OUT_FIFO_Q54", - "Q83": "CMT_OUT_FIFO_Q83", - "D87": "CMT_OUT_FIFO_D87", - "Q56": "CMT_OUT_FIFO_Q56", - "D64": "CMT_OUT_FIFO_D64", - "D13": "CMT_OUT_FIFO_D13", - "D81": "CMT_OUT_FIFO_D81", - "D33": "CMT_OUT_FIFO_D33", - "D65": "CMT_OUT_FIFO_D65", - "D96": "CMT_OUT_FIFO_D96", - "Q12": "CMT_OUT_FIFO_Q12", - "Q62": "CMT_OUT_FIFO_Q62", - "D91": "CMT_OUT_FIFO_D91", - "TESTREADDISB": "CMT_OUT_FIFO_TESTREADDISB", - "D24": "CMT_OUT_FIFO_D24", - "D46": "CMT_OUT_FIFO_D46", - "D57": "CMT_OUT_FIFO_D57", - "D52": "CMT_OUT_FIFO_D52", - "D97": "CMT_OUT_FIFO_D97", - "Q30": "CMT_OUT_FIFO_Q30", - "Q63": "CMT_OUT_FIFO_Q63", - "D25": "CMT_OUT_FIFO_D25", - "D01": "CMT_OUT_FIFO_D01", - "Q02": "CMT_OUT_FIFO_Q02", - "Q71": "CMT_OUT_FIFO_Q71", - "TESTMODEB": "CMT_OUT_FIFO_TESTMODEB", - "RESET": "CMT_OUT_FIFO_RESET", - "D00": "CMT_OUT_FIFO_D00", - "D60": "CMT_OUT_FIFO_D60", - "D32": "CMT_OUT_FIFO_D32", - "D04": "CMT_OUT_FIFO_D04", - "D16": "CMT_OUT_FIFO_D16", - "D02": "CMT_OUT_FIFO_D02", - "RDEN": "CMT_OUT_FIFO_RDEN", - "D77": "CMT_OUT_FIFO_D77", - "SCANOUT0": "CMT_OUT_FIFO_SCANOUT0", - "D54": "CMT_OUT_FIFO_D54", - "D17": "CMT_OUT_FIFO_D17", - "FULL": "CMT_OUT_FIFO_FULL", - "D90": "CMT_OUT_FIFO_D90", - "Q65": "CMT_OUT_FIFO_Q65", - "ALMOSTFULL": "CMT_OUT_FIFO_ALMOSTFULL", - "Q61": "CMT_OUT_FIFO_Q61", - "D73": "CMT_OUT_FIFO_D73", - "SCANOUT3": "CMT_OUT_FIFO_SCANOUT3", - "SCANENB": "CMT_OUT_FIFO_SCANENB", - "D37": "CMT_OUT_FIFO_D37", - "D70": "CMT_OUT_FIFO_D70", - "Q32": "CMT_OUT_FIFO_Q32", - "D53": "CMT_OUT_FIFO_D53", - "WREN": "CMT_OUT_FIFO_WREN", - "Q20": "CMT_OUT_FIFO_Q20", - "D67": "CMT_OUT_FIFO_D67", - "D56": "CMT_OUT_FIFO_D56", - "SCANIN0": "CMT_OUT_FIFO_SCANIN0", - "D03": "CMT_OUT_FIFO_D03", - "D74": "CMT_OUT_FIFO_D74", - "D06": "CMT_OUT_FIFO_D06", - "D11": "CMT_OUT_FIFO_D11", - "WRCLK": "CMT_OUT_FIFO_WRCLK", - "D66": "CMT_OUT_FIFO_D66", - "D63": "CMT_OUT_FIFO_D63", - "Q55": "CMT_OUT_FIFO_Q55", - "D10": "CMT_OUT_FIFO_D10", - "D85": "CMT_OUT_FIFO_D85", - "D40": "CMT_OUT_FIFO_D40", - "EMPTY": "CMT_OUT_FIFO_EMPTY", - "Q22": "CMT_OUT_FIFO_Q22", - "Q92": "CMT_OUT_FIFO_Q92", - "D15": "CMT_OUT_FIFO_D15", - "D95": "CMT_OUT_FIFO_D95", - "SCANOUT1": "CMT_OUT_FIFO_SCANOUT1", - "D34": "CMT_OUT_FIFO_D34", - "D31": "CMT_OUT_FIFO_D31", - "SCANIN3": "CMT_OUT_FIFO_SCANIN3", - "Q64": "CMT_OUT_FIFO_Q64", - "D50": "CMT_OUT_FIFO_D50", - "D61": "CMT_OUT_FIFO_D61", - "D27": "CMT_OUT_FIFO_D27", - "Q50": "CMT_OUT_FIFO_Q50", - "Q31": "CMT_OUT_FIFO_Q31", - "D72": "CMT_OUT_FIFO_D72", - "D20": "CMT_OUT_FIFO_D20", - "Q03": "CMT_OUT_FIFO_Q03", - "D43": "CMT_OUT_FIFO_D43", - "D55": "CMT_OUT_FIFO_D55", - "Q70": "CMT_OUT_FIFO_Q70", - "D75": "CMT_OUT_FIFO_D75", - "Q67": "CMT_OUT_FIFO_Q67", - "Q13": "CMT_OUT_FIFO_Q13", - "Q81": "CMT_OUT_FIFO_Q81", - "Q60": "CMT_OUT_FIFO_Q60", - "D84": "CMT_OUT_FIFO_D84", - "Q41": "CMT_OUT_FIFO_Q41", - "SCANOUT2": "CMT_OUT_FIFO_SCANOUT2", - "Q33": "CMT_OUT_FIFO_Q33", - "D23": "CMT_OUT_FIFO_D23", - "Q72": "CMT_OUT_FIFO_Q72", - "Q21": "CMT_OUT_FIFO_Q21" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IN_FIFO", - "y_coord": 0, - "type": "IN_FIFO", - "site_pins": { - "D92": "CMT_IN_FIFO_D92", - "Q53": "CMT_IN_FIFO_Q53", - "D12": "CMT_IN_FIFO_D12", - "SCANIN1": "CMT_IN_FIFO_SCANIN1", - "D82": "CMT_IN_FIFO_D82", - "D30": "CMT_IN_FIFO_D30", - "Q01": "CMT_IN_FIFO_Q01", - "Q07": "CMT_IN_FIFO_Q07", - "Q37": "CMT_IN_FIFO_Q37", - "Q57": "CMT_IN_FIFO_Q57", - "Q75": "CMT_IN_FIFO_Q75", - "Q40": "CMT_IN_FIFO_Q40", - "D21": "CMT_IN_FIFO_D21", - "TESTWRITEDISB": "CMT_IN_FIFO_TESTWRITEDISB", - "D66": "CMT_IN_FIFO_D66", - "D62": "CMT_IN_FIFO_D62", - "Q82": "CMT_IN_FIFO_Q82", - "D50": "CMT_IN_FIFO_D50", - "D91": "CMT_IN_FIFO_D91", - "Q90": "CMT_IN_FIFO_Q90", - "D71": "CMT_IN_FIFO_D71", - "Q00": "CMT_IN_FIFO_Q00", - "D41": "CMT_IN_FIFO_D41", - "D80": "CMT_IN_FIFO_D80", - "SCANIN2": "CMT_IN_FIFO_SCANIN2", - "D51": "CMT_IN_FIFO_D51", - "Q24": "CMT_IN_FIFO_Q24", - "D93": "CMT_IN_FIFO_D93", - "Q93": "CMT_IN_FIFO_Q93", - "D13": "CMT_IN_FIFO_D13", - "Q91": "CMT_IN_FIFO_Q91", - "Q42": "CMT_IN_FIFO_Q42", - "Q36": "CMT_IN_FIFO_Q36", - "Q80": "CMT_IN_FIFO_Q80", - "D42": "CMT_IN_FIFO_D42", - "Q10": "CMT_IN_FIFO_Q10", - "RDCLK": "CMT_IN_FIFO_RDCLK", - "Q52": "CMT_IN_FIFO_Q52", - "Q86": "CMT_IN_FIFO_Q86", - "Q84": "CMT_IN_FIFO_Q84", - "D70": "CMT_IN_FIFO_D70", - "D83": "CMT_IN_FIFO_D83", - "Q74": "CMT_IN_FIFO_Q74", - "Q15": "CMT_IN_FIFO_Q15", - "Q26": "CMT_IN_FIFO_Q26", - "Q23": "CMT_IN_FIFO_Q23", - "Q73": "CMT_IN_FIFO_Q73", - "D22": "CMT_IN_FIFO_D22", - "Q04": "CMT_IN_FIFO_Q04", - "Q54": "CMT_IN_FIFO_Q54", - "Q83": "CMT_IN_FIFO_Q83", - "Q20": "CMT_IN_FIFO_Q20", - "Q56": "CMT_IN_FIFO_Q56", - "D64": "CMT_IN_FIFO_D64", - "Q51": "CMT_IN_FIFO_Q51", - "Q87": "CMT_IN_FIFO_Q87", - "D81": "CMT_IN_FIFO_D81", - "D33": "CMT_IN_FIFO_D33", - "D65": "CMT_IN_FIFO_D65", - "Q94": "CMT_IN_FIFO_Q94", - "Q06": "CMT_IN_FIFO_Q06", - "Q12": "CMT_IN_FIFO_Q12", - "Q62": "CMT_IN_FIFO_Q62", - "TESTREADDISB": "CMT_IN_FIFO_TESTREADDISB", - "Q17": "CMT_IN_FIFO_Q17", - "D57": "CMT_IN_FIFO_D57", - "D52": "CMT_IN_FIFO_D52", - "Q46": "CMT_IN_FIFO_Q46", - "Q30": "CMT_IN_FIFO_Q30", - "Q25": "CMT_IN_FIFO_Q25", - "Q63": "CMT_IN_FIFO_Q63", - "D01": "CMT_IN_FIFO_D01", - "Q02": "CMT_IN_FIFO_Q02", - "Q71": "CMT_IN_FIFO_Q71", - "TESTMODEB": "CMT_IN_FIFO_TESTMODEB", - "RESET": "CMT_IN_FIFO_RESET", - "D00": "CMT_IN_FIFO_D00", - "Q27": "CMT_IN_FIFO_Q27", - "Q16": "CMT_IN_FIFO_Q16", - "D60": "CMT_IN_FIFO_D60", - "D32": "CMT_IN_FIFO_D32", - "Q14": "CMT_IN_FIFO_Q14", - "D02": "CMT_IN_FIFO_D02", - "RDEN": "CMT_IN_FIFO_RDEN", - "SCANOUT0": "CMT_IN_FIFO_SCANOUT0", - "D54": "CMT_IN_FIFO_D54", - "FULL": "CMT_IN_FIFO_FULL", - "D90": "CMT_IN_FIFO_D90", - "Q76": "CMT_IN_FIFO_Q76", - "Q65": "CMT_IN_FIFO_Q65", - "Q47": "CMT_IN_FIFO_Q47", - "ALMOSTFULL": "CMT_IN_FIFO_ALMOSTFULL", - "Q61": "CMT_IN_FIFO_Q61", - "D73": "CMT_IN_FIFO_D73", - "SCANOUT3": "CMT_IN_FIFO_SCANOUT3", - "SCANENB": "CMT_IN_FIFO_SCANENB", - "Q32": "CMT_IN_FIFO_Q32", - "D53": "CMT_IN_FIFO_D53", - "WREN": "CMT_IN_FIFO_WREN", - "Q11": "CMT_IN_FIFO_Q11", - "D67": "CMT_IN_FIFO_D67", - "D56": "CMT_IN_FIFO_D56", - "SCANIN0": "CMT_IN_FIFO_SCANIN0", - "D03": "CMT_IN_FIFO_D03", - "Q66": "CMT_IN_FIFO_Q66", - "D11": "CMT_IN_FIFO_D11", - "Q77": "CMT_IN_FIFO_Q77", - "WRCLK": "CMT_IN_FIFO_WRCLK", - "D63": "CMT_IN_FIFO_D63", - "Q55": "CMT_IN_FIFO_Q55", - "D10": "CMT_IN_FIFO_D10", - "Q45": "CMT_IN_FIFO_Q45", - "Q96": "CMT_IN_FIFO_Q96", - "D40": "CMT_IN_FIFO_D40", - "EMPTY": "CMT_IN_FIFO_EMPTY", - "Q22": "CMT_IN_FIFO_Q22", - "Q92": "CMT_IN_FIFO_Q92", - "Q95": "CMT_IN_FIFO_Q95", - "ALMOSTEMPTY": "CMT_IN_FIFO_ALMOSTEMPTY", - "Q33": "CMT_IN_FIFO_Q33", - "SCANOUT1": "CMT_IN_FIFO_SCANOUT1", - "D31": "CMT_IN_FIFO_D31", - "SCANIN3": "CMT_IN_FIFO_SCANIN3", - "Q35": "CMT_IN_FIFO_Q35", - "Q43": "CMT_IN_FIFO_Q43", - "D61": "CMT_IN_FIFO_D61", - "Q85": "CMT_IN_FIFO_Q85", - "Q50": "CMT_IN_FIFO_Q50", - "Q31": "CMT_IN_FIFO_Q31", - "D72": "CMT_IN_FIFO_D72", - "Q34": "CMT_IN_FIFO_Q34", - "D20": "CMT_IN_FIFO_D20", - "Q03": "CMT_IN_FIFO_Q03", - "D43": "CMT_IN_FIFO_D43", - "D55": "CMT_IN_FIFO_D55", - "Q70": "CMT_IN_FIFO_Q70", - "Q67": "CMT_IN_FIFO_Q67", - "Q13": "CMT_IN_FIFO_Q13", - "Q81": "CMT_IN_FIFO_Q81", - "Q64": "CMT_IN_FIFO_Q64", - "Q60": "CMT_IN_FIFO_Q60", - "Q97": "CMT_IN_FIFO_Q97", - "Q41": "CMT_IN_FIFO_Q41", - "SCANOUT2": "CMT_IN_FIFO_SCANOUT2", - "Q05": "CMT_IN_FIFO_Q05", - "D23": "CMT_IN_FIFO_D23", - "Q72": "CMT_IN_FIFO_Q72", - "Q21": "CMT_IN_FIFO_Q21", - "Q44": "CMT_IN_FIFO_Q44" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D61", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_8", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D23", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D75", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q83", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q74", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D56", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_6", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D30", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D52", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_5", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D86", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D77", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D32", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D55", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_6", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q02", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q70", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D13", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RDEN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_PHASER_RDENABLE", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q24", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D44", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q20", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D43", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D42", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D62", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_8", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D73", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D21", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS22_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q40", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q97", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q31", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D83", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q91", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q30", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q71", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q30", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q23", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D52", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_5", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_WRCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_CLK0_6", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q93", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D76", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS11_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_5", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q52", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q32", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_1->CMT_OUT_FIFO_D14": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D14", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D91", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D90", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D97", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q41", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RESET", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_6", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q47", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q31", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D05", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D82", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D63", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_8", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D00", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q35", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D12", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_RDCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_CLK1_7", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q15", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q03", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q42", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D90", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D65", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_7", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS22_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_9", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q70", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D23", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS20_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q73", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q55", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D92", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D82", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D03", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_ALMOSTFULL", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q60", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q92", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D43", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D13", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q45", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q90", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q84", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS22_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q80", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q16", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q12", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D85", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D80", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q72", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q22", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D72", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q22", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D35", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D00", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D64", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_8", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D53", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_5", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q33", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D80", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_WRCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_PHASER_WRCLK", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D92", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q80", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D20", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D60", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_8", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q73", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q46", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q23", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q00", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D24", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D62", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_8", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D33", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D87", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q01", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS11_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_10", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q82", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS22_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_11", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q90", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RDCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_PHASER_RDCLK", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q42", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q41", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D02", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D66", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_7", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D22", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D51", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_5", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D12", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q96", - "is_pseudo": "0" - }, "CMT_FIFO_L.CMT_OUT_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS22_6": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_6", - "is_directional": "1", "src_wire": "CMT_OUT_FIFO_Q54", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_9->CMT_OUT_FIFO_D71": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D71", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q26", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS19_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_8", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q61", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q21", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q05", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D34", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q86", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q36", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q76", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q02", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RDCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_CLK0_7", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_RDEN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_7", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D74", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS22_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_5", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q50", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D20", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D57", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_6", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D64", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_7", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS11_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_8", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q62", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D55", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_5", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q91", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D81", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q00", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D61", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_8", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q04", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q53", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q95", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q03", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D50", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_5", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_WRCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_CLK1_6", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D84", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_5->CMT_OUT_FIFO_D56": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D56", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_5", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D11", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q81", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q44", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D04", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D42", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q21", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS20_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_5", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q53", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_WREN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_PHASER_WRENABLE", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q65", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q17", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D54", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_6", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D31", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D11", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D54", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_5", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q61", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D16", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D33", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D41", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS19_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_7", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q65", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q66", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS22_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_8", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q60", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D01", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D26", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q57", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_FULL", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_ALMOSTFULL", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D70", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q33", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS22_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_7", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q64", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D47", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D51", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_3->CMT_IN_FIFO_D32": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D32", - "is_directional": "1", "src_wire": "CMT_FIFO_L_IMUX36_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D67", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_8", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D45", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q01", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q52", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q06", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D27", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q64", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D83", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D07", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q20", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D53", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_5", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS20_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q57", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q43", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D30", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D41", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q85", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q54", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q40", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D06", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_1->CMT_IN_FIFO_D10": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D10", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q56", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS11_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_9", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q72", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS11_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q56", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS20_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_7", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q67", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D70", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RDEN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_7", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D60", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_8", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS19_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_9", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q71", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q51", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q94", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_4", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q43", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS19_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_5", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q51", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q87", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D03", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q67", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D72", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_WREN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_6", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D22", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q77", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q10", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D67", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D32" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_11->CMT_IN_FIFO_D93": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D93", - "is_directional": "1", "src_wire": "CMT_FIFO_L_IMUX42_11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D65", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D93" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_9->CMT_OUT_FIFO_D71": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D40", + "src_wire": "CMT_FIFO_L_IMUX21_9", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D71" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { + "CMT_FIFO_L.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D36", + "src_wire": "CMT_OUT_FIFO_Q10", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q34", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D01", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_0", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q50", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q63", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D15", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_RESET", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_7", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D37", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q93", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_WREN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_6", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D31", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_3", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q25", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q13", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D21", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_2", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q32", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS20_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_8", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q63", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q27", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D96", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_EMPTY", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q13", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q14", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D93", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_11", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q62", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS19_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q55", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS20_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_10", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q83", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS11_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_7", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q66", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_EMPTY", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D17", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_1", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D95", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_9->CMT_OUT_FIFO_D73": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D73", - "is_directional": "1", "src_wire": "CMT_FIFO_L_IMUX38_9", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D57", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D73" }, - "CMT_FIFO_L.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0", + "src_wire": "CMT_FIFO_L_IMUX26_3", "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q07", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D30" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D50", + "src_wire": "CMT_FIFO_L_IMUX38_2", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D23" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D25", + "src_wire": "CMT_FIFO_L_IMUX28_9", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D70" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { + "CMT_FIFO_L.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D81", + "src_wire": "CMT_OUT_FIFO_Q20", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2" }, - "CMT_FIFO_L.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { + "CMT_FIFO_L.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3", + "src_wire": "CMT_IN_FIFO_Q86", "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q37", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { + "CMT_FIFO_L.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D91", + "src_wire": "CMT_OUT_FIFO_Q11", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { + "CMT_FIFO_L.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D66", + "src_wire": "CMT_IN_FIFO_Q43", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D71", + "src_wire": "CMT_FIFO_L_IMUX26_9", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D70" }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { + "CMT_FIFO_L.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11", + "src_wire": "CMT_IN_FIFO_Q31", "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q92", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { + "CMT_FIFO_L.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D94", + "src_wire": "CMT_IN_FIFO_Q54", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5" }, - "CMT_FIFO_L.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { + "CMT_FIFO_L.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10", + "src_wire": "CMT_IN_FIFO_Q93", "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q81", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D40", + "src_wire": "CMT_FIFO_L_IMUX26_7", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D64" }, - "CMT_FIFO_L.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { + "CMT_FIFO_L.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6", + "src_wire": "CMT_IN_FIFO_Q03", "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_FULL", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D10", + "src_wire": "CMT_FIFO_L_IMUX6_9", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D77" }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D46", + "src_wire": "CMT_FIFO_L_IMUX40_0", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_4", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q12", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D63", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D01" }, "CMT_FIFO_L.CMT_IN_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS5_10": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10", - "is_directional": "1", "src_wire": "CMT_IN_FIFO_Q82", - "is_pseudo": "0" - }, - "CMT_FIFO_L.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9", "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q75", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D56" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D57" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q52", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5" + }, + "CMT_FIFO_L.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_EMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D31" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D60" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D16" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D80" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D80" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS19_5": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_5" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D33" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D11" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS19_7": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q65", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_7" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D42" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D50" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D05" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D02" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q92", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q03", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q02", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS19_8": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_8" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D00" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D86" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D27" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS19_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_6" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q07", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q97", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11" + }, + "CMT_FIFO_L.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_CLK1_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WRCLK" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D83" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS22_7": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q64", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_7" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D21" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS11_9": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q72", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_9" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D90" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D82" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q05", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D17" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D22" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS22_4": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D76" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D74" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D81" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D22" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D91" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D34" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D92" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D51" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_0->CMT_IN_FIFO_D02": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D02", - "is_directional": "1", "src_wire": "CMT_FIFO_L_IMUX36_0", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D02" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q81", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS20_5": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_5" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q65", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q81", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D51" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D83" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D36" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D66" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D41" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D52" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS11_8": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_8" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDEN" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS22_11": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_11" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D13" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q02", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D03" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D85" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D53" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D41" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D93" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D12" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D31" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D75" + }, + "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_PHASER_RDENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDEN" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D55" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D64" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D67" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D61" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q91", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11" + }, + "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D40" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS22_9": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q70", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_9" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D72" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D67" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_5->CMT_OUT_FIFO_D56": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D56" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WREN" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D57" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D54" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5" + }, + "CMT_FIFO_L.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_CLK0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_WRCLK" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D13" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D32" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q93", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS11_7": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q66", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_7" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D45" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D72" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D73" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D30" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D42" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D23" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D33" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q95", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D46" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q76", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_1->CMT_OUT_FIFO_D14": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D14" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D71" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D96" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D43" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D03" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D50" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q00", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0" + }, + "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_PHASER_RDCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDCLK" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q75", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D95" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D54" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D66" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4" + }, + "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_PHASER_WRENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WREN" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D55" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D26" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D24" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D00" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D84" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RESET" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D91" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS22_8": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_8" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D12" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D63" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS22_5": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_5" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q84", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q70", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q74", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D65" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS22_10": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q80", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D11" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q92", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11" + }, + "CMT_FIFO_L.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_CLK1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RDCLK" + }, + "CMT_FIFO_L.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_FULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D62" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D37" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q00", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D06" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q83", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q91", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D10" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_EMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS11_5": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q52", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_5" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D60" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D20" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D07" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS19_9": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q71", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_9" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q71", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D65" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS20_9": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q73", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9" + }, + "CMT_FIFO_L.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_CLK0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDCLK" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q72", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q67", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q80", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS20_8": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_8" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q04", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0" + }, + "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_PHASER_WRCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WRCLK" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D52" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D61" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D04" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_4" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q73", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q85", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q94", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11" + }, + "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_ALMOSTFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_1->CMT_IN_FIFO_D10": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D10" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D92" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D44" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D20" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q01", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D35" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D53" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D63" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D47" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D01" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D82" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D62" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D97" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS20_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_6" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS20_7": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q67", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_7" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q96", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D94" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_WREN" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS20_10": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q83", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_10" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q64", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_ALMOSTFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D15" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D43" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q01", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q06", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q87", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D90" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS11_10": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q82", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_10" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS11_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_6" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D40" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D81" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D21" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D87" + }, + "CMT_FIFO_L.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_FULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q77", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D25" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RESET" + }, + "CMT_FIFO_L.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RDEN" + }, + "CMT_FIFO_L.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q66", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8" } }, - "tile_type": "CMT_FIFO_L" + "wires": [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_FIFO_NW4A0_2", + "CMT_FIFO_EE4C1_4", + "CMT_FIFO_ER1BEG0_5", + "CMT_FIFO_SE2A3_0", + "CMT_FIFO_L_LOGIC_OUTS16_11", + "CMT_FIFO_L_BYP3_9", + "CMT_FIFO_L_IMUX15_5", + "CMT_FIFO_WW4A1_1", + "CMT_FIFO_L_IMUX12_9", + "CMT_FIFO_L_FAN1_6", + "CMT_FIFO_EE4A2_3", + "CMT_FIFO_SW4END1_1", + "CMT_FIFO_L_IMUX22_3", + "CMT_FIFO_SW2A2_6", + "CMT_FIFO_WL1END0_11", + "CMT_FIFO_L_IMUX40_5", + "CMT_FIFO_EE4B0_4", + "CMT_FIFO_L_IMUX44_5", + "CMT_FIFO_NE4BEG1_5", + "CMT_OUT_FIFO_Q21", + "CMT_FIFO_EE4A3_8", + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_FIFO_NW4END3_1", + "CMT_FIFO_L_IMUX34_1", + "CMT_FIFO_WR1END0_10", + "CMT_FIFO_SW4A3_4", + "CMT_FIFO_WR1END0_9", + "CMT_FIFO_NW4END2_8", + "CMT_OUT_FIFO_D74", + "CMT_FIFO_NW2A3_6", + "CMT_FIFO_NE2A1_4", + "CMT_FIFO_SW4END1_7", + "CMT_FIFO_NW2A1_7", + "CMT_FIFO_NE2A0_11", + "CMT_FIFO_WW2A1_2", + "CMT_FIFO_SE4BEG2_3", + "CMT_FIFO_EE4C3_11", + "CMT_FIFO_L_IMUX17_6", + "CMT_FIFO_WW4B2_11", + "CMT_FIFO_LH7_8", + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_FIFO_NW4A3_9", + "CMT_FIFO_L_IMUX43_10", + "CMT_FIFO_NE4BEG2_4", + "CMT_FIFO_ER1BEG3_1", + "CMT_FIFO_NE4BEG3_2", + "CMT_FIFO_EE4B2_4", + "CMT_FIFO_WW4B2_3", + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_FIFO_NE2A3_4", + "CMT_FIFO_SE4BEG3_8", + "CMT_FIFO_NW4A0_3", + "CMT_FIFO_NW4A2_10", + "CMT_FIFO_WR1END1_6", + "CMT_FIFO_NE2A2_4", + "CMT_FIFO_SE4BEG2_1", + "CMT_FIFO_SE2A1_11", + "CMT_IN_FIFO_Q31", + "CMT_FIFO_NW4A1_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_FIFO_L_IMUX13_4", + "CMT_FIFO_L_CTRL0_5", + "CMT_FIFO_L_LOGIC_OUTS14_8", + "CMT_FIFO_LH9_6", + "CMT_FIFO_NW4A0_9", + "CMT_FIFO_L_IMUX21_2", + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_FIFO_LH1_4", + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_FIFO_EE2A3_7", + "CMT_FIFO_SW2A3_2", + "CMT_FIFO_L_IMUX26_10", + "CMT_FIFO_L_BYP2_4", + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_FIFO_NW2A0_3", + "CMT_FIFO_L_IMUX28_3", + "CMT_FIFO_SE4C0_3", + "CMT_FIFO_NW4A0_11", + "CMT_FIFO_LH11_5", + "CMT_FIFO_LH10_9", + "CMT_OUT_FIFO_D12", + "CMT_FIFO_WW4B0_4", + "CMT_FIFO_L_FAN4_4", + "CMT_FIFO_SW2A2_10", + "CMT_FIFO_WW4C0_11", + "CMT_FIFO_NE4C2_10", + "CMT_FIFO_WW2END1_4", + "CMT_FIFO_EL1BEG3_7", + "CMT_FIFO_L_IMUX29_10", + "CMT_IN_FIFO_D80", + "CMT_FIFO_L_FAN6_8", + "CMT_FIFO_WW4B2_8", + "CMT_FIFO_WW4B0_11", + "CMT_FIFO_L_IMUX24_11", + "CMT_FIFO_LH10_6", + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_FIFO_WW2END0_6", + "CMT_OUT_FIFO_D55", + "CMT_FIFO_WW2END1_5", + "CMT_FIFO_L_FAN7_9", + "CMT_FIFO_L_CLK1_8", + "CMT_FIFO_EE4C0_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_1", + "CMT_FIFO_NE2A3_10", + "CMT_FIFO_SW4END0_4", + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_OUT_FIFO_D62", + "CMT_FIFO_SE4C0_1", + "CMT_IN_FIFO_TESTWRITEDISB", + "CMT_FIFO_EE4A3_7", + "CMT_IN_FIFO_Q03", + "CMT_OUT_FIFO_Q61", + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_FIFO_SW4A2_0", + "CMT_FIFO_L_BYP1_8", + "CMT_FIFO_L_IMUX45_11", + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_FIFO_NE2A0_5", + "CMT_FIFO_LH12_7", + "CMT_FIFO_WW4C1_6", + "CMT_FIFO_WR1END3_7", + "CMT_FIFO_ER1BEG1_7", + "CMT_FIFO_SW4END2_4", + "CMT_FIFO_L_IMUX46_1", + "CMT_FIFO_L_BYP7_0", + "CMT_FIFO_L_IMUX27_5", + "CMT_FIFO_EE4B1_5", + "CMT_FIFO_L_BYP4_6", + "CMT_FIFO_L_BYP5_8", + "CMT_FIFO_WW4END0_7", + "CMT_FIFO_EE4BEG3_7", + "CMT_FIFO_NE2A2_6", + "CMT_FIFO_EE4B3_1", + "CMT_FIFO_LH4_0", + "CMT_FIFO_L_IMUX45_0", + "CMT_FIFO_NE4C2_7", + "CMT_FIFO_WW4B0_7", + "CMT_FIFO_SE4C0_11", + "CMT_FIFO_L_IMUX28_0", + "CMT_FIFO_WW4B3_9", + "CMT_FIFO_LH8_6", + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_FIFO_L_IMUX32_0", + "CMT_FIFO_MONITOR_N_1", + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_FIFO_SE2A3_7", + "CMT_FIFO_NE4BEG2_9", + "CMT_FIFO_SW4END1_4", + "CMT_FIFO_L_FAN3_9", + "CMT_FIFO_EE4BEG3_6", + "CMT_FIFO_EE2A2_11", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_4", + "CMT_FIFO_SW2A1_8", + "CMT_FIFO_L_IMUX25_2", + "CMT_FIFO_L_IMUX27_10", + "CMT_FIFO_EE4BEG0_10", + "CMT_FIFO_EE4BEG2_5", + "CMT_FIFO_SE4C1_9", + "CMT_FIFO_L_IMUX21_3", + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_FIFO_L_IMUX20_0", + "CMT_FIFO_EL1BEG2_2", + "CMT_FIFO_WW4B1_7", + "CMT_FIFO_WL1END1_8", + "CMT_FIFO_SW4A2_6", + "CMT_FIFO_LH7_10", + "CMT_FIFO_WR1END0_7", + "CMT_FIFO_L_FAN0_7", + "CMT_IN_FIFO_Q74", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_6", + "CMT_FIFO_L_FAN6_7", + "CMT_FIFO_NW4END2_9", + "CMT_IN_FIFO_Q30", + "CMT_FIFO_L_FAN6_10", + "CMT_FIFO_LH3_6", + "CMT_FIFO_L_FAN0_3", + "CMT_FIFO_L_IMUX39_11", + "CMT_FIFO_L_IMUX44_11", + "CMT_FIFO_WW2END1_1", + "CMT_FIFO_EL1BEG2_10", + "CMT_FIFO_L_BYP2_2", + "CMT_OUT_FIFO_RDCLK", + "CMT_FIFO_L_CLK0_9", + "CMT_FIFO_LH4_1", + "CMT_FIFO_WL1END2_11", + "CMT_FIFO_SE4BEG1_10", + "CMT_FIFO_NE2A3_1", + "CMT_FIFO_L_IMUX15_1", + "FIFO_DQS_IOTOPHASER_4", + "CMT_FIFO_L_LOGIC_OUTS3_1", + "CMT_FIFO_SW4END3_6", + "CMT_FIFO_NW4END2_4", + "CMT_FIFO_SE4BEG1_6", + "CMT_FIFO_EE4A0_11", + "CMT_FIFO_L_IMUX40_6", + "CMT_FIFO_WW2A3_6", + "CMT_OUT_FIFO_D57", + "CMT_FIFO_WW4B0_2", + "CMT_FIFO_EE2A0_7", + "CMT_FIFO_L_IMUX29_7", + "CMT_FIFO_SE4C1_5", + "CMT_FIFO_NE4BEG2_0", + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_IN_FIFO_WRCLK", + "CMT_FIFO_SE4C0_2", + "CMT_IN_FIFO_D71", + "CMT_FIFO_L_IMUX2_9", + "CMT_OUT_FIFO_Q70", + "CMT_FIFO_EE4BEG2_7", + "CMT_FIFO_L_BYP1_9", + "CMT_IN_FIFO_Q62", + "CMT_FIFO_L_IMUX25_3", + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_FIFO_EL1BEG0_8", + "CMT_FIFO_EE2BEG0_0", + "CMT_FIFO_WW2END0_11", + "CMT_FIFO_WW4END0_5", + "CMT_FIFO_WW4END1_7", + "CMT_FIFO_L_IMUX19_1", + "CMT_FIFO_WR1END3_4", + "CMT_FIFO_SE2A3_6", + "CMT_FIFO_EE4C3_7", + "CMT_FIFO_L_CLK1_10", + "CMT_FIFO_L_IMUX13_10", + "CMT_FIFO_EE4C0_10", + "CMT_FIFO_L_IMUX47_8", + "CMT_FIFO_NE4BEG1_10", + "CMT_FIFO_SE4BEG3_7", + "CMT_FIFO_L_IMUX26_5", + "CMT_IN_FIFO_D02", + "CMT_FIFO_L_IMUX7_9", + "CMT_FIFO_ER1BEG2_5", + "CMT_FIFO_NW2A3_2", + "CMT_FIFO_WW4END1_2", + "CMT_FIFO_EE4C3_10", + "CMT_FIFO_L_IMUX19_0", + "CMT_FIFO_EE4A2_0", + "CMT_FIFO_LH12_8", + "CMT_FIFO_L_FAN3_7", + "CMT_FIFO_WW2END1_8", + "CMT_FIFO_L_IMUX29_9", + "CMT_FIFO_EE4C0_7", + "CMT_OUT_FIFO_D22", + "CMT_FIFO_SE2A0_7", + "CMT_FIFO_L_BYP3_4", + "CMT_FIFO_LH6_9", + "CMT_FIFO_L_BYP3_0", + "CMT_IN_FIFO_Q91", + "CMT_FIFO_L_IMUX15_7", + "CMT_FIFO_ER1BEG3_11", + "CMT_FIFO_NW4A2_2", + "CMT_FIFO_L_IMUX38_8", + "CMT_FIFO_EE4A0_7", + "CMT_FIFO_LH2_11", + "CMT_FIFO_LH10_8", + "CMT_FIFO_L_IMUX30_3", + "CMT_OUT_FIFO_Q40", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_FIFO_EE4B1_0", + "CMT_FIFO_SE4C1_4", + "CMT_FIFO_L_IMUX44_7", + "CMT_FIFO_NW4END1_6", + "CMT_FIFO_WW4END1_3", + "CMT_FIFO_NE2A0_4", + "CMT_FIFO_NW4A0_5", + "CMT_FIFO_SE4BEG1_5", + "CMT_FIFO_L_IMUX28_11", + "CMT_FIFO_L_IMUX32_6", + "CMT_FIFO_SE4C3_0", + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_FIFO_L_IMUX8_9", + "CMT_FIFO_L_BYP6_11", + "CMT_FIFO_L_IMUX1_10", + "CMT_FIFO_WW4END1_5", + "CMT_FIFO_WL1END3_4", + "CMT_FIFO_L_IMUX47_1", + "CMT_FIFO_L_LOGIC_OUTS21_10", + "CMT_FIFO_L_IMUX11_7", + "CMT_IN_FIFO_Q24", + "CMT_FIFO_WW4A1_7", + "CMT_FIFO_EE4C2_9", + "CMT_FIFO_SE4C1_3", + "CMT_FIFO_WW4END0_1", + "CMT_FIFO_EE4C3_0", + "CMT_FIFO_WW4B3_8", + "CMT_FIFO_L_IMUX2_7", + "CMT_FIFO_EE2BEG3_5", + "CMT_FIFO_NW4A1_1", + "CMT_FIFO_WW4END3_6", + "CMT_FIFO_L_IMUX18_8", + "CMT_FIFO_NW2A3_1", + "CMT_OUT_FIFO_D25", + "CMT_FIFO_L_IMUX21_4", + "CMT_FIFO_MONITOR_N_3", + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_FIFO_EE4C1_8", + "CMT_FIFO_L_IMUX9_7", + "CMT_FIFO_WW4B3_7", + "CMT_FIFO_L_IMUX30_2", + "CMT_FIFO_NE4C2_2", + "CMT_FIFO_EL1BEG0_3", + "CMT_FIFO_WW2END1_9", + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_FIFO_EE4A2_1", + "CMT_FIFO_L_IMUX15_4", + "CMT_FIFO_WW4END2_6", + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_FIFO_L_IMUX14_6", + "CMT_FIFO_L_IMUX45_6", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_FIFO_LH6_8", + "CMT_FIFO_LH4_9", + "CMT_FIFO_L_IMUX15_10", + "CMT_FIFO_SE4BEG3_2", + "CMT_FIFO_L_IMUX18_10", + "CMT_FIFO_NW4END0_8", + "CMT_FIFO_L_FAN7_2", + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_IN_FIFO_Q71", + "CMT_OUT_FIFO_RESET", + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_FIFO_ER1BEG2_6", + "CMT_FIFO_WW2A2_4", + "CMT_FIFO_NW4END1_5", + "CMT_FIFO_L_IMUX12_1", + "CMT_FIFO_SE4BEG2_2", + "CMT_IN_FIFO_Q04", + "CMT_FIFO_LH3_5", + "CMT_IN_FIFO_D21", + "CMT_FIFO_ER1BEG0_2", + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_FIFO_L_IMUX7_2", + "CMT_FIFO_L_IMUX18_1", + "CMT_FIFO_L_LOGIC_OUTS16_3", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_FIFO_SW2A0_11", + "CMT_FIFO_SE4BEG0_4", + "CMT_FIFO_SW4A1_3", + "CMT_FIFO_ER1BEG3_10", + "CMT_FIFO_L_IMUX8_3", + "CMT_FIFO_L_IMUX30_10", + "CMT_FIFO_SW2A3_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_2", + "CMT_OUT_FIFO_D80", + "CMT_FIFO_LH11_6", + "CMT_FIFO_SE4BEG0_2", + "CMT_FIFO_WW4A1_6", + "CMT_FIFO_SW4A1_0", + "CMT_FIFO_L_IMUX36_9", + "CMT_FIFO_L_IMUX42_11", + "CMT_FIFO_EE4BEG1_4", + "CMT_FIFO_L_IMUX31_9", + "CMT_FIFO_L_IMUX12_2", + "CMT_FIFO_MONITOR_P_7", + "CMT_FIFO_EE4B2_3", + "CMT_FIFO_WR1END1_7", + "CMT_FIFO_LH7_2", + "CMT_FIFO_L_IMUX19_8", + "CMT_FIFO_L_IMUX17_3", + "CMT_IN_FIFO_D55", + "CMT_OUT_FIFO_D04", + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_FIFO_SE2A2_11", + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_FIFO_L_IMUX9_0", + "CMT_FIFO_L_LOGIC_OUTS16_5", + "CMT_FIFO_NW4END1_3", + "CMT_FIFO_NW2A0_10", + "CMT_OUT_FIFO_D46", + "CMT_FIFO_NE4BEG2_11", + "CMT_FIFO_SE4C3_11", + "CMT_FIFO_L_LOGIC_OUTS16_9", + "CMT_OUT_FIFO_D96", + "CMT_FIFO_ER1BEG3_8", + "CMT_FIFO_SW4END0_9", + "CMT_FIFO_L_BYP5_5", + "CMT_FIFO_WW2END2_2", + "CMT_FIFO_EE2A1_2", + "CMT_OUT_FIFO_Q62", + "CMT_FIFO_EE2A0_4", + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_FIFO_NW4END0_5", + "CMT_FIFO_L_IMUX30_0", + "CMT_FIFO_L_IMUX19_9", + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_FIFO_WW2A1_5", + "CMT_FIFO_WW4B2_0", + "CMT_FIFO_L_IMUX41_5", + "CMT_FIFO_NE2A1_9", + "CMT_FIFO_L_BYP1_7", + "CMT_FIFO_EE4A3_2", + "CMT_FIFO_SW4END2_9", + "CMT_FIFO_L_LOGIC_OUTS14_3", + "CMT_FIFO_L_LOGIC_OUTS7_10", + "CMT_FIFO_WW2A3_7", + "CMT_FIFO_NW4END2_5", + "CMT_FIFO_L_IMUX21_8", + "CMT_FIFO_L_LOGIC_OUTS23_10", + "CMT_FIFO_WW4END0_6", + "CMT_FIFO_EL1BEG1_7", + "CMT_FIFO_L_FAN7_6", + "CMT_FIFO_L_CTRL1_7", + "CMT_FIFO_L_CTRL0_7", + "CMT_FIFO_SE4C1_6", + "CMT_FIFO_L_LOGIC_OUTS15_11", + "CMT_FIFO_LH10_5", + "CMT_FIFO_L_FAN0_0", + "CMT_FIFO_WL1END0_9", + "CMT_FIFO_EE2A3_10", + "CMT_FIFO_L_IMUX38_11", + "CMT_FIFO_LH9_9", + "CMT_FIFO_LH11_7", + "CMT_FIFO_EL1BEG0_1", + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_FIFO_WW4END3_1", + "CMT_OUT_FIFO_SCANENB", + "CMT_FIFO_SW4END1_9", + "CMT_FIFO_SE2A0_10", + "CMT_FIFO_LH4_5", + "CMT_FIFO_EE2A2_10", + "CMT_FIFO_L_IMUX41_2", + "CMT_OUT_FIFO_SCANIN0", + "CMT_FIFO_WL1END3_9", + "CMT_FIFO_L_IMUX46_9", + "CMT_FIFO_L_FAN2_8", + "CMT_FIFO_WW4B0_0", + "CMT_FIFO_L_FAN4_2", + "CMT_FIFO_NW4END2_3", + "CMT_FIFO_EE4C3_8", + "CMT_FIFO_L_FAN2_9", + "CMT_FIFO_LH7_1", + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_FIFO_L_IMUX35_4", + "CMT_FIFO_EE2BEG0_4", + "CMT_FIFO_NW2A1_6", + "CMT_FIFO_SW4A2_8", + "CMT_FIFO_WW4C3_3", + "CMT_FIFO_L_IMUX16_7", + "CMT_FIFO_LH12_6", + "CMT_FIFO_EE2BEG0_7", + "CMT_FIFO_NE4C2_0", + "CMT_FIFO_LH4_2", + "CMT_FIFO_WW4C0_1", + "CMT_FIFO_EE2A2_7", + "CMT_FIFO_L_IMUX9_2", + "CMT_FIFO_NW4A2_11", + "CMT_FIFO_EE4C1_10", + "CMT_FIFO_EE4BEG3_11", + "CMT_FIFO_NE4BEG3_8", + "CMT_FIFO_L_FAN1_5", + "CMT_FIFO_NE4BEG3_9", + "CMT_FIFO_L_IMUX25_8", + "CMT_FIFO_L_IMUX23_11", + "CMT_FIFO_WW4C1_1", + "CMT_FIFO_L_BYP0_5", + "CMT_FIFO_NW4A2_1", + "CMT_FIFO_L_IMUX10_2", + "CMT_IN_FIFO_D03", + "CMT_FIFO_WL1END0_2", + "CMT_FIFO_NW4END3_2", + "CMT_FIFO_NE2A1_10", + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_FIFO_WW4END3_2", + "CMT_FIFO_EE4C3_2", + "CMT_FIFO_SE4C3_3", + "CMT_FIFO_L_CTRL0_10", + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_OUT_FIFO_Q01", + "CMT_FIFO_LH11_3", + "CMT_FIFO_L_IMUX29_2", + "CMT_FIFO_L_IMUX23_6", + "CMT_FIFO_EE4A1_6", + "CMT_OUT_FIFO_Q22", + "CMT_FIFO_WW2A3_11", + "CMT_FIFO_L_IMUX47_10", + "CMT_FIFO_WR1END3_6", + "CMT_OUT_FIFO_D07", + "CMT_FIFO_SW4A2_11", + "CMT_FIFO_SE4BEG2_0", + "CMT_FIFO_L_IMUX6_3", + "CMT_FIFO_NE4C2_11", + "CMT_OUT_FIFO_Q72", + "CMT_OUT_FIFO_Q56", + "CMT_FIFO_WW2A0_1", + "CMT_FIFO_WW4END2_8", + "CMT_FIFO_L_IMUX45_7", + "CMT_FIFO_EE2A3_6", + "CMT_OUT_FIFO_RDEN", + "CMT_IN_FIFO_Q06", + "CMT_FIFO_L_IMUX33_2", + "CMT_FIFO_NW4A3_7", + "CMT_FIFO_SW4A2_1", + "CMT_FIFO_SW4END3_1", + "CMT_FIFO_WR1END0_1", + "CMT_FIFO_L_IMUX6_10", + "CMT_FIFO_L_BYP5_4", + "CMT_FIFO_LH8_10", + "CMT_FIFO_WR1END1_4", + "CMT_FIFO_EL1BEG3_10", + "CMT_FIFO_L_IMUX36_8", + "CMT_FIFO_WW2A1_0", + "CMT_FIFO_WW4A1_3", + "CMT_FIFO_EE4BEG3_8", + "CMT_FIFO_MONITOR_N_6", + "CMT_FIFO_L_IMUX28_8", + "CMT_FIFO_SE4C1_1", + "CMT_FIFO_LH1_9", + "CMT_FIFO_WW4B3_0", + "CMT_FIFO_SE4C2_0", + "CMT_FIFO_NW2A3_3", + "CMT_FIFO_LH1_11", + "CMT_FIFO_L_IMUX40_0", + "CMT_FIFO_L_IMUX24_8", + "CMT_FIFO_ER1BEG0_3", + "CMT_OUT_FIFO_Q33", + "CMT_FIFO_L_BYP7_7", + "CMT_FIFO_WW4A3_9", + "CMT_FIFO_ER1BEG0_7", + "CMT_FIFO_L_LOGIC_OUTS7_1", + "CMT_FIFO_SE4BEG1_0", + "CMT_FIFO_L_IMUX9_11", + "CMT_FIFO_L_IMUX12_7", + "CMT_FIFO_L_LOGIC_OUTS7_0", + "CMT_FIFO_NE4BEG2_5", + "CMT_FIFO_SE4C2_6", + "CMT_FIFO_L_IMUX33_10", + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_FIFO_L_FAN4_5", + "CMT_FIFO_NW4END0_6", + "CMT_OUT_FIFO_D66", + "CMT_FIFO_WW4B1_1", + "CMT_FIFO_NE2A1_8", + "CMT_FIFO_WW4B1_11", + "CMT_OUT_FIFO_D60", + "CMT_FIFO_L_IMUX39_6", + "CMT_FIFO_MONITOR_P_1", + "CMT_FIFO_SE2A0_9", + "CMT_FIFO_L_IMUX21_5", + "CMT_FIFO_LH5_0", + "CMT_FIFO_LH11_8", + "CMT_FIFO_L_IMUX1_6", + "CMT_FIFO_SW4A0_10", + "CMT_FIFO_WW2END0_7", + "CMT_FIFO_L_IMUX33_5", + "CMT_FIFO_WW2A3_5", + "CMT_FIFO_LH5_2", + "CMT_FIFO_SE2A3_4", + "CMT_FIFO_EL1BEG2_3", + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_FIFO_NW2A2_6", + "CMT_FIFO_L_FAN2_3", + "CMT_FIFO_L_BYP5_2", + "CMT_FIFO_SW2A0_0", + "CMT_FIFO_L_LOGIC_OUTS14_5", + "CMT_FIFO_NE2A1_5", + "CMT_FIFO_SW2A3_10", + "CMT_FIFO_SW2A1_0", + "CMT_FIFO_L_CLK1_6", + "CMT_FIFO_SW4END1_11", + "CMT_OUT_FIFO_D71", + "CMT_FIFO_SE4BEG2_9", + "CMT_FIFO_L_LOGIC_OUTS3_11", + "CMT_FIFO_WW2A2_10", + "CMT_FIFO_WW2A1_3", + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_IN_FIFO_Q01", + "CMT_FIFO_NE2A3_5", + "CMT_FIFO_LH8_8", + "CMT_FIFO_WW4B1_5", + "CMT_FIFO_LH8_7", + "CMT_FIFO_L_CLK1_1", + "CMT_FIFO_NW4A3_5", + "CMT_FIFO_L_CTRL0_1", + "CMT_FIFO_EE4A0_5", + "CMT_FIFO_SW4A2_2", + "CMT_FIFO_EE4A3_1", + "CMT_FIFO_L_CTRL0_3", + "CMT_FIFO_L_IMUX36_10", + "CMT_FIFO_WW2END1_3", + "CMT_FIFO_EL1BEG0_10", + "CMT_FIFO_NW4A2_7", + "CMT_FIFO_L_BYP1_4", + "CMT_FIFO_EE4A0_0", + "CMT_FIFO_EE2BEG2_7", + "CMT_FIFO_L_IMUX6_4", + "CMT_FIFO_L_FAN6_2", + "CMT_FIFO_L_IMUX17_11", + "CMT_FIFO_NE4BEG3_11", + "CMT_FIFO_L_FAN7_0", + "CMT_FIFO_L_IMUX17_7", + "CMT_IN_FIFO_D33", + "CMT_FIFO_L_IMUX16_3", + "CMT_FIFO_L_LOGIC_OUTS14_4", + "CMT_FIFO_L_IMUX42_8", + "CMT_FIFO_L_FAN2_7", + "CMT_FIFO_NW4END3_0", + "CMT_FIFO_L_IMUX20_1", + "CMT_FIFO_WW4B1_4", + "CMT_FIFO_L_IMUX10_11", + "CMT_FIFO_L_IMUX37_4", + "CMT_FIFO_L_IMUX25_11", + "CMT_FIFO_LH10_11", + "CMT_OUT_FIFO_D32", + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_FIFO_EE4BEG3_9", + "CMT_FIFO_L_IMUX34_4", + "CMT_FIFO_EE4BEG2_1", + "CMT_FIFO_EE4B3_7", + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_FIFO_NE4BEG1_6", + "CMT_FIFO_L_IMUX33_4", + "CMT_FIFO_LH8_2", + "CMT_FIFO_L_IMUX1_1", + "CMT_FIFO_LH8_5", + "CMT_FIFO_SW2A0_7", + "CMT_FIFO_WL1END3_3", + "CMT_FIFO_L_FAN2_10", + "CMT_FIFO_L_LOGIC_OUTS6_8", + "CMT_FIFO_NE4BEG1_8", + "CMT_FIFO_L_BYP3_8", + "CMT_FIFO_L_IMUX27_7", + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_FIFO_SE4C3_8", + "CMT_FIFO_NW4END1_4", + "CMT_FIFO_L_IMUX43_9", + "CMT_FIFO_SW2A0_8", + "CMT_FIFO_NE4BEG1_2", + "CMT_FIFO_WL1END1_6", + "CMT_FIFO_WL1END3_0", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_10", + "CMT_FIFO_NW2A1_0", + "CMT_FIFO_WW2A0_0", + "CMT_FIFO_WW4END3_5", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_FIFO_SW2A3_0", + "CMT_FIFO_SE2A0_6", + "CMT_FIFO_LH10_0", + "CMT_FIFO_EE2BEG3_8", + "CMT_FIFO_L_IMUX32_7", + "CMT_IN_FIFO_Q83", + "CMT_FIFO_WW4END0_10", + "CMT_FIFO_L_IMUX34_7", + "CMT_FIFO_L_IMUX20_4", + "CMT_FIFO_WW2A3_4", + "CMT_FIFO_L_IMUX8_6", + "CMT_FIFO_EL1BEG2_8", + "CMT_FIFO_EE4B1_11", + "CMT_FIFO_L_IMUX5_7", + "CMT_FIFO_EL1BEG2_4", + "CMT_FIFO_NW4END3_9", + "CMT_FIFO_L_IMUX4_5", + "CMT_IN_FIFO_Q53", + "CMT_FIFO_L_IMUX3_3", + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_FIFO_LH7_11", + "CMT_FIFO_WW4B3_5", + "CMT_FIFO_WL1END3_6", + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_FIFO_L_IMUX38_9", + "CMT_FIFO_WR1END1_10", + "CMT_FIFO_L_IMUX0_6", + "CMT_FIFO_WW2A0_3", + "CMT_FIFO_EE4A2_9", + "CMT_FIFO_SE4BEG1_4", + "CMT_FIFO_EE4BEG2_4", + "CMT_IN_FIFO_D81", + "CMT_OUT_FIFO_D56", + "CMT_FIFO_L_IMUX24_2", + "CMT_FIFO_WW2END1_0", + "CMT_FIFO_NE4C3_8", + "CMT_FIFO_EE2A2_1", + "CMT_FIFO_SW2A3_3", + "CMT_FIFO_WR1END1_5", + "CMT_OUT_FIFO_Q71", + "CMT_FIFO_ER1BEG2_10", + "CMT_FIFO_SW4A2_7", + "CMT_FIFO_NE4C1_5", + "CMT_FIFO_EE4C2_2", + "CMT_FIFO_L_IMUX18_11", + "CMT_FIFO_L_IMUX2_10", + "CMT_FIFO_WW4END3_11", + "CMT_FIFO_L_IMUX12_11", + "CMT_FIFO_NW2A0_2", + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_FIFO_NW4END1_2", + "CMT_FIFO_WR1END2_5", + "CMT_FIFO_NW4A1_9", + "CMT_FIFO_L_IMUX32_10", + "CMT_FIFO_L_IMUX11_9", + "CMT_FIFO_EE2BEG3_2", + "CMT_FIFO_NW2A0_8", + "CMT_FIFO_L_IMUX43_6", + "CMT_FIFO_EE4C2_11", + "CMT_FIFO_WR1END2_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_FIFO_LH12_2", + "CMT_FIFO_WR1END3_5", + "CMT_IN_FIFO_SCANOUT1", + "CMT_FIFO_WW2A2_11", + "CMT_FIFO_NE4C0_4", + "CMT_FIFO_L_IMUX33_8", + "CMT_FIFO_NW4END0_10", + "CMT_FIFO_SE4C2_11", + "CMT_FIFO_EL1BEG3_3", + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_FIFO_WW2A0_5", + "CMT_OUT_FIFO_D13", + "CMT_FIFO_L_IMUX41_9", + "CMT_FIFO_NE2A1_3", + "CMT_FIFO_L_BYP6_6", + "CMT_FIFO_L_IMUX40_2", + "CMT_FIFO_L_IMUX10_0", + "CMT_FIFO_L_CLK1_2", + "CMT_IN_FIFO_D92", + "CMT_FIFO_L_IMUX3_9", + "CMT_FIFO_L_IMUX20_6", + "CMT_FIFO_WW4C0_6", + "CMT_FIFO_SW2A1_3", + "CMT_FIFO_L_FAN3_10", + "CMT_FIFO_L_LOGIC_OUTS3_10", + "CMT_FIFO_SW4END0_1", + "CMT_IN_FIFO_EMPTY", + "CMT_FIFO_SW2A3_6", + "CMT_IN_FIFO_D41", + "CMT_FIFO_WW4END2_1", + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_FIFO_EL1BEG2_1", + "CMT_FIFO_L_IMUX11_6", + "CMT_FIFO_L_IMUX47_3", + "CMT_FIFO_L_IMUX23_5", + "CMT_FIFO_LH11_11", + "CMT_FIFO_L_LOGIC_OUTS3_8", + "CMT_FIFO_L_BYP3_6", + "FIFO_DQS_IOTOPHASER_55", + "CMT_OUT_FIFO_D21", + "CMT_IN_FIFO_FULL", + "CMT_FIFO_NW2A2_3", + "CMT_FIFO_L_IMUX32_1", + "CMT_FIFO_SE2A3_2", + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_FIFO_L_IMUX43_8", + "CMT_FIFO_WW2END3_9", + "CMT_IN_FIFO_D30", + "CMT_FIFO_NE4BEG0_6", + "CMT_FIFO_EE4BEG0_0", + "CMT_FIFO_NE4BEG2_6", + "CMT_FIFO_NW4A2_6", + "CMT_FIFO_LH6_6", + "CMT_FIFO_NE4C1_8", + "CMT_FIFO_WW4A1_11", + "CMT_FIFO_SE4C3_7", + "CMT_FIFO_SE4C3_9", + "CMT_FIFO_L_LOGIC_OUTS14_11", + "CMT_FIFO_L_IMUX9_8", + "CMT_FIFO_L_IMUX38_1", + "CMT_FIFO_L_LOGIC_OUTS3_4", + "CMT_IN_FIFO_Q20", + "CMT_FIFO_L_CTRL0_2", + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_OUT_FIFO_SCANOUT3", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_FIFO_EL1BEG0_9", + "CMT_IN_FIFO_Q23", + "CMT_FIFO_LH6_1", + "CMT_OUT_FIFO_D47", + "CMT_FIFO_WL1END0_1", + "CMT_FIFO_L_IMUX4_10", + "CMT_FIFO_L_IMUX5_8", + "CMT_FIFO_L_BYP6_7", + "CMT_OUT_FIFO_D85", + "CMT_FIFO_ER1BEG1_1", + "CMT_FIFO_LH4_6", + "CMT_FIFO_WW2END2_9", + "CMT_FIFO_EE4B2_9", + "CMT_FIFO_EE2BEG1_0", + "CMT_FIFO_WW4B1_9", + "CMT_FIFO_WW2A1_7", + "CMT_FIFO_MONITOR_N_9", + "CMT_FIFO_NW4END2_10", + "CMT_FIFO_NW4END2_7", + "CMT_FIFO_SE2A1_4", + "CMT_FIFO_L_IMUX39_7", + "CMT_FIFO_L_BYP5_6", + "CMT_FIFO_L_BYP4_8", + "CMT_FIFO_LH2_4", + "CMT_FIFO_LH5_9", + "CMT_FIFO_NW4A2_3", + "CMT_FIFO_WW2END3_8", + "CMT_FIFO_WW4C0_3", + "CMT_FIFO_WR1END3_10", + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_FIFO_NE4C2_1", + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_FIFO_L_IMUX19_10", + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_FIFO_WW4A1_4", + "CMT_FIFO_NW4A3_6", + "CMT_FIFO_L_FAN5_11", + "CMT_FIFO_L_IMUX33_11", + "CMT_FIFO_L_LOGIC_OUTS3_2", + "CMT_FIFO_NE2A3_6", + "CMT_OUT_FIFO_Q13", + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_FIFO_SW2A2_11", + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_FIFO_L_IMUX46_7", + "CMT_FIFO_L_BYP0_9", + "CMT_FIFO_SW2A0_1", + "CMT_FIFO_WW4A1_5", + "CMT_FIFO_WL1END3_10", + "CMT_FIFO_EE4B0_9", + "CMT_FIFO_L_IMUX1_8", + "CMT_FIFO_L_IMUX21_1", + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_FIFO_SW4END3_3", + "CMT_FIFO_SE4C2_3", + "CMT_OUT_FIFO_D64", + "CMT_OUT_FIFO_D40", + "CMT_FIFO_WW4A2_3", + "CMT_FIFO_WW4A3_7", + "CMT_FIFO_WR1END3_8", + "CMT_FIFO_WL1END2_9", + "CMT_FIFO_LH2_0", + "CMT_FIFO_L_IMUX25_5", + "CMT_FIFO_L_FAN4_10", + "CMT_FIFO_EE4B0_8", + "CMT_FIFO_EE4C2_8", + "CMT_OUT_FIFO_SCANOUT1", + "CMT_FIFO_L_IMUX45_1", + "CMT_FIFO_NW4A0_6", + "CMT_FIFO_LH7_7", + "CMT_FIFO_L_IMUX8_7", + "CMT_FIFO_EL1BEG1_5", + "CMT_FIFO_L_IMUX20_3", + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_OUT_FIFO_Q67", + "CMT_FIFO_NE4C3_3", + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_FIFO_L_IMUX11_0", + "CMT_FIFO_L_IMUX30_11", + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_FIFO_L_BYP3_1", + "CMT_FIFO_L_IMUX8_0", + "CMT_FIFO_L_FAN5_3", + "CMT_FIFO_L_IMUX42_6", + "CMT_FIFO_L_IMUX35_3", + "CMT_FIFO_L_CTRL1_9", + "CMT_FIFO_SE2A2_6", + "CMT_FIFO_SE4C2_9", + "CMT_FIFO_L_IMUX7_4", + "CMT_FIFO_L_IMUX21_0", + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_FIFO_EE4A2_6", + "CMT_FIFO_WW4B3_1", + "CMT_FIFO_ER1BEG1_11", + "CMT_FIFO_ER1BEG0_9", + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_FIFO_WW4A0_0", + "CMT_FIFO_L_IMUX33_9", + "CMT_FIFO_L_IMUX10_9", + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_FIFO_EE2A2_6", + "CMT_FIFO_EL1BEG2_7", + "CMT_OUT_FIFO_D84", + "CMT_FIFO_L_IMUX37_11", + "CMT_FIFO_SE2A0_5", + "CMT_FIFO_WW4END2_11", + "CMT_FIFO_NW2A2_11", + "CMT_OUT_FIFO_SCANIN3", + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_IN_FIFO_Q16", + "CMT_IN_FIFO_Q45", + "CMT_FIFO_L_IMUX25_0", + "CMT_FIFO_LH9_5", + "CMT_FIFO_SE2A2_3", + "CMT_OUT_FIFO_D31", + "CMT_FIFO_EE4C1_1", + "CMT_IN_FIFO_Q26", + "CMT_FIFO_NE4C0_7", + "CMT_FIFO_LH7_5", + "CMT_FIFO_WW4C1_0", + "CMT_FIFO_L_IMUX36_4", + "CMT_FIFO_NE4BEG3_3", + "CMT_FIFO_EE4BEG2_10", + "CMT_IN_FIFO_Q44", + "CMT_OUT_FIFO_D05", + "CMT_FIFO_LH8_11", + "CMT_FIFO_EE2A0_1", + "CMT_FIFO_LH6_2", + "CMT_FIFO_WW2END3_10", + "CMT_FIFO_EE2BEG1_4", + "CMT_FIFO_NE2A2_2", + "CMT_OUT_FIFO_D73", + "CMT_FIFO_SE2A1_6", + "CMT_FIFO_L_FAN1_1", + "CMT_FIFO_NW2A3_10", + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_FIFO_L_IMUX45_3", + "CMT_OUT_FIFO_Q93", + "CMT_FIFO_L_FAN4_0", + "CMT_FIFO_L_IMUX5_1", + "CMT_FIFO_L_CTRL0_8", + "CMT_FIFO_SE4C3_10", + "CMT_FIFO_NW2A0_0", + "CMT_FIFO_L_LOGIC_OUTS3_5", + "CMT_FIFO_WW2END2_7", + "CMT_FIFO_SW4A3_11", + "CMT_FIFO_WW4C1_8", + "CMT_FIFO_EL1BEG2_6", + "CMT_FIFO_L_IMUX3_10", + "CMT_FIFO_LH10_10", + "CMT_FIFO_WW4END1_0", + "CMT_FIFO_EE4BEG0_1", + "CMT_FIFO_L_FAN7_4", + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_OUT_FIFO_D81", + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_FIFO_L_IMUX12_8", + "CMT_FIFO_WW2END3_4", + "CMT_FIFO_L_FAN0_1", + "CMT_FIFO_SE2A3_9", + "CMT_FIFO_SE2A3_1", + "CMT_FIFO_L_CLK1_0", + "CMT_FIFO_WW2A3_2", + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_FIFO_WW4END3_4", + "CMT_FIFO_WW4C2_2", + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_FIFO_SE2A0_8", + "CMT_FIFO_L_IMUX37_6", + "CMT_FIFO_SE4C1_0", + "CMT_FIFO_L_FAN7_8", + "CMT_FIFO_L_IMUX32_8", + "CMT_FIFO_L_IMUX25_7", + "CMT_FIFO_EE4A0_3", + "CMT_FIFO_NE4C1_4", + "CMT_FIFO_L_BYP0_11", + "CMT_FIFO_EE2BEG2_0", + "CMT_FIFO_SW2A0_3", + "FIFO_DQS_IOTOPHASER_66", + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_FIFO_SE2A1_9", + "CMT_FIFO_NW4END0_7", + "CMT_FIFO_WW4A3_4", + "CMT_FIFO_L_FAN3_6", + "CMT_FIFO_L_IMUX11_5", + "CMT_FIFO_SW4END3_7", + "CMT_FIFO_L_IMUX14_11", + "CMT_FIFO_WW4C2_5", + "CMT_FIFO_SE4C2_10", + "CMT_FIFO_L_IMUX28_5", + "CMT_FIFO_WR1END0_0", + "CMT_FIFO_EE4B3_6", + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_FIFO_EE2A2_9", + "CMT_FIFO_WR1END1_1", + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_FIFO_SE4BEG3_6", + "CMT_FIFO_LH11_4", + "CMT_FIFO_EE4A1_7", + "CMT_FIFO_LH9_0", + "CMT_OUT_FIFO_D97", + "CMT_FIFO_SW4A3_1", + "CMT_IN_FIFO_SCANOUT0", + "CMT_FIFO_L_FAN5_4", + "CMT_FIFO_SW4A1_5", + "CMT_FIFO_L_FAN1_11", + "CMT_FIFO_EE4A1_11", + "CMT_IN_FIFO_Q93", + "CMT_FIFO_L_IMUX0_0", + "CMT_FIFO_L_IMUX19_4", + "CMT_FIFO_SE4C0_9", + "CMT_OUT_FIFO_Q31", + "CMT_FIFO_L_IMUX41_8", + "CMT_FIFO_L_IMUX15_2", + "CMT_FIFO_NE4BEG0_2", + "CMT_FIFO_L_IMUX41_10", + "CMT_FIFO_EE2A3_3", + "CMT_FIFO_SW4END2_1", + "CMT_FIFO_NE4C3_4", + "CMT_FIFO_SW2A0_2", + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_FIFO_SW2A3_11", + "CMT_FIFO_L_IMUX36_0", + "CMT_FIFO_L_LOGIC_OUTS10_10", + "CMT_FIFO_WL1END3_5", + "CMT_FIFO_L_LOGIC_OUTS6_1", + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_FIFO_SE4C2_5", + "CMT_OUT_FIFO_WRCLK", + "CMT_FIFO_L_FAN1_2", + "CMT_FIFO_SW2A2_4", + "CMT_FIFO_EE4B0_1", + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_FIFO_SE4C3_4", + "CMT_FIFO_L_IMUX1_0", + "CMT_FIFO_NW4END0_0", + "CMT_FIFO_SW4A0_7", + "CMT_FIFO_NW4END2_6", + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_IN_FIFO_Q92", + "CMT_FIFO_L_LOGIC_OUTS15_0", + "CMT_FIFO_EE2BEG2_2", + "CMT_FIFO_L_IMUX17_2", + "CMT_FIFO_EE4BEG0_3", + "CMT_FIFO_EE2A0_10", + "CMT_FIFO_L_LOGIC_OUTS10_1", + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_FIFO_WW4B3_4", + "CMT_FIFO_L_IMUX13_1", + "CMT_OUT_FIFO_Q23", + "CMT_FIFO_L_IMUX39_9", + "CMT_FIFO_EE2BEG3_0", + "CMT_FIFO_L_IMUX31_8", + "CMT_FIFO_L_IMUX35_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_FIFO_L_IMUX0_8", + "CMT_FIFO_WL1END2_5", + "CMT_FIFO_NW4END1_1", + "CMT_FIFO_NE4C2_8", + "CMT_FIFO_NE4C3_1", + "CMT_FIFO_LH3_7", + "CMT_FIFO_NE4BEG0_5", + "FIFO_DQS_IOTOPHASER_2", + "CMT_IN_FIFO_D22", + "CMT_FIFO_L_FAN5_1", + "CMT_FIFO_EE2BEG0_1", + "CMT_FIFO_MONITOR_P_6", + "CMT_FIFO_WW4A2_5", + "CMT_FIFO_ER1BEG1_3", + "CMT_FIFO_SW2A2_1", + "CMT_FIFO_L_IMUX14_0", + "CMT_FIFO_L_IMUX12_4", + "CMT_FIFO_WW4A0_8", + "CMT_FIFO_L_IMUX9_4", + "CMT_IN_FIFO_ALMOSTFULL", + "CMT_FIFO_L_IMUX14_1", + "CMT_FIFO_SW4END3_10", + "CMT_FIFO_SW4END2_0", + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_FIFO_L_IMUX47_7", + "CMT_FIFO_L_IMUX47_0", + "CMT_FIFO_L_IMUX13_3", + "FIFO_DQS_IOTOPHASER_33", + "CMT_FIFO_L_IMUX21_6", + "CMT_FIFO_L_IMUX24_1", + "CMT_FIFO_L_IMUX10_8", + "CMT_FIFO_ER1BEG1_6", + "CMT_FIFO_LH4_4", + "CMT_FIFO_EE4A0_10", + "CMT_FIFO_SE4BEG2_5", + "CMT_FIFO_L_LOGIC_OUTS17_1", + "CMT_FIFO_L_IMUX1_11", + "CMT_FIFO_L_FAN3_1", + "CMT_OUT_FIFO_D77", + "CMT_FIFO_SW4A3_6", + "CMT_FIFO_L_IMUX25_9", + "CMT_FIFO_L_CLK1_5", + "CMT_FIFO_LH4_3", + "CMT_FIFO_WL1END0_4", + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_FIFO_WW2A3_3", + "CMT_FIFO_L_IMUX6_8", + "CMT_FIFO_WW2END2_10", + "CMT_FIFO_LH7_0", + "CMT_FIFO_L_FAN2_2", + "CMT_FIFO_EE2BEG1_3", + "CMT_IN_FIFO_D20", + "CMT_FIFO_WW4B0_1", + "CMT_FIFO_L_IMUX34_6", + "CMT_FIFO_L_LOGIC_OUTS23_11", + "CMT_FIFO_EE4B0_5", + "CMT_FIFO_NW4A1_11", + "CMT_FIFO_L_LOGIC_OUTS2_1", + "CMT_FIFO_L_IMUX10_4", + "CMT_FIFO_EE4C3_6", + "CMT_FIFO_L_IMUX44_0", + "CMT_FIFO_L_IMUX12_0", + "CMT_IN_FIFO_D42", + "CMT_FIFO_WW4C1_11", + "CMT_FIFO_WW4END0_4", + "CMT_OUT_FIFO_D50", + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_FIFO_SW4A1_7", + "CMT_FIFO_WW4A2_0", + "CMT_FIFO_MONITOR_P_8", + "CMT_FIFO_L_IMUX39_8", + "CMT_FIFO_NW4A1_7", + "CMT_FIFO_L_BYP6_5", + "CMT_FIFO_NE4C3_6", + "CMT_FIFO_LH5_6", + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_IN_FIFO_Q12", + "CMT_FIFO_SW2A3_8", + "CMT_FIFO_EE4BEG3_5", + "CMT_FIFO_L_IMUX22_4", + "CMT_FIFO_L_FAN2_4", + "CMT_FIFO_NE4C1_3", + "CMT_FIFO_L_IMUX45_10", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_FIFO_WW2A3_10", + "CMT_FIFO_NE2A0_10", + "CMT_FIFO_WW2END3_2", + "CMT_FIFO_L_IMUX0_3", + "CMT_IN_FIFO_Q22", + "CMT_FIFO_L_IMUX38_7", + "CMT_FIFO_WW4C1_9", + "CMT_FIFO_EE2BEG2_9", + "CMT_FIFO_EE4BEG0_6", + "CMT_FIFO_LH10_4", + "CMT_FIFO_ER1BEG3_2", + "CMT_FIFO_NE4C0_3", + "CMT_FIFO_L_IMUX12_5", + "CMT_FIFO_EE4C1_0", + "CMT_FIFO_SE4BEG2_10", + "CMT_FIFO_L_IMUX4_1", + "CMT_FIFO_WW2A2_9", + "CMT_FIFO_L_BYP6_8", + "CMT_FIFO_L_FAN1_10", + "CMT_FIFO_SW4END0_0", + "CMT_FIFO_EE2A0_11", + "CMT_FIFO_L_IMUX45_8", + "CMT_FIFO_L_IMUX19_7", + "CMT_FIFO_L_FAN2_0", + "CMT_FIFO_WW4B1_6", + "CMT_FIFO_L_IMUX25_6", + "CMT_FIFO_WL1END3_7", + "CMT_FIFO_L_IMUX41_11", + "CMT_FIFO_WW4END2_5", + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_FIFO_EE2A2_4", + "CMT_FIFO_NW4A2_4", + "CMT_FIFO_L_LOGIC_OUTS10_0", + "CMT_FIFO_L_IMUX42_2", + "CMT_FIFO_EE4B2_10", + "CMT_FIFO_L_IMUX44_1", + "CMT_FIFO_WL1END3_2", + "CMT_FIFO_ER1BEG1_5", + "FIFO_DQS_IOTOPHASER_3", + "CMT_FIFO_L_FAN0_11", + "CMT_FIFO_EE2BEG0_6", + "CMT_OUT_FIFO_Q57", + "CMT_FIFO_WW4B0_5", + "CMT_FIFO_NE4BEG2_2", + "CMT_FIFO_L_IMUX38_4", + "FIFO_DQS_IOTOPHASER_5", + "CMT_FIFO_NW2A0_5", + "CMT_FIFO_NE4BEG0_10", + "CMT_FIFO_WR1END0_5", + "CMT_FIFO_EE2A0_9", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_FIFO_EE4B0_2", + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_FIFO_WW4A1_9", + "CMT_FIFO_L_IMUX27_11", + "CMT_FIFO_L_LOGIC_OUTS18_1", + "CMT_FIFO_L_FAN3_4", + "CMT_IN_FIFO_D65", + "CMT_FIFO_L_IMUX3_6", + "CMT_FIFO_SE2A0_2", + "CMT_FIFO_WW4B1_2", + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_FIFO_L_IMUX24_9", + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_FIFO_WW4C0_10", + "CMT_FIFO_L_IMUX40_7", + "CMT_FIFO_NE4C2_4", + "CMT_FIFO_EE4BEG2_0", + "CMT_OUT_FIFO_Q92", + "CMT_FIFO_L_IMUX39_0", + "CMT_FIFO_SE4C0_8", + "CMT_FIFO_L_IMUX37_10", + "CMT_OUT_FIFO_D00", + "CMT_OUT_FIFO_Q80", + "CMT_IN_FIFO_D64", + "CMT_FIFO_NW4A1_6", + "CMT_FIFO_EE4B1_4", + "CMT_FIFO_L_IMUX35_6", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_FIFO_SW4END2_11", + "CMT_FIFO_EE2A3_9", + "CMT_FIFO_L_IMUX46_10", + "CMT_IN_FIFO_Q73", + "CMT_OUT_FIFO_WREN", + "CMT_FIFO_L_IMUX4_3", + "CMT_FIFO_L_IMUX22_6", + "CMT_IN_FIFO_D83", + "CMT_FIFO_L_BYP0_6", + "CMT_FIFO_SW4A3_9", + "CMT_FIFO_NE4C0_2", + "CMT_FIFO_L_IMUX9_9", + "CMT_FIFO_L_IMUX36_2", + "CMT_FIFO_L_IMUX35_11", + "CMT_FIFO_EL1BEG1_11", + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_IN_FIFO_Q41", + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_OUT_FIFO_D15", + "CMT_IN_FIFO_D13", + "CMT_FIFO_MONITOR_P_5", + "CMT_FIFO_L_IMUX34_10", + "CMT_FIFO_L_IMUX12_6", + "CMT_FIFO_SE4BEG0_10", + "FIFO_DQS_IOTOPHASER_11", + "CMT_IN_FIFO_Q95", + "CMT_FIFO_SW4END3_9", + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_IN_FIFO_Q52", + "CMT_FIFO_WW2END0_5", + "CMT_FIFO_ER1BEG3_7", + "CMT_FIFO_WW4C2_4", + "CMT_FIFO_WW4C2_0", + "CMT_FIFO_SE4C2_4", + "CMT_FIFO_L_IMUX15_11", + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_FIFO_L_IMUX29_8", + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_FIFO_EE4A1_2", + "CMT_FIFO_WW4C3_7", + "CMT_FIFO_L_IMUX31_10", + "CMT_FIFO_L_BYP5_7", + "CMT_IN_FIFO_Q82", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_FIFO_WW4A2_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_FIFO_SE4BEG2_4", + "CMT_FIFO_NW4A3_4", + "CMT_FIFO_EE4C2_5", + "CMT_IN_FIFO_D60", + "CMT_FIFO_L_CTRL1_4", + "CMT_FIFO_NE2A3_9", + "CMT_FIFO_L_IMUX3_7", + "CMT_FIFO_SW4A0_4", + "CMT_OUT_FIFO_D30", + "CMT_FIFO_L_LOGIC_OUTS6_2", + "CMT_FIFO_L_IMUX45_2", + "CMT_IN_FIFO_Q13", + "CMT_FIFO_SW2A1_5", + "CMT_FIFO_EE4BEG0_11", + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_FIFO_LH4_8", + "CMT_FIFO_NE2A1_7", + "CMT_FIFO_SW2A2_8", + "CMT_FIFO_SW4A2_3", + "CMT_FIFO_L_IMUX14_2", + "CMT_FIFO_EE4B3_9", + "CMT_FIFO_L_IMUX44_9", + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_IN_FIFO_Q17", + "CMT_FIFO_EE4BEG1_7", + "CMT_FIFO_L_IMUX2_2", + "CMT_FIFO_EE4BEG3_2", + "CMT_FIFO_L_IMUX14_9", + "CMT_FIFO_EE4BEG1_3", + "CMT_FIFO_L_FAN6_11", + "CMT_FIFO_EE4C0_9", + "CMT_FIFO_LH6_11", + "CMT_FIFO_L_LOGIC_OUTS14_2", + "CMT_FIFO_SW2A2_0", + "CMT_FIFO_LH5_3", + "CMT_FIFO_SW4A0_2", + "CMT_FIFO_SE4C0_0", + "CMT_FIFO_WL1END2_10", + "CMT_FIFO_WW4B1_8", + "CMT_FIFO_SE4BEG0_7", + "CMT_FIFO_L_CTRL0_6", + "CMT_FIFO_LH4_10", + "CMT_FIFO_L_IMUX4_4", + "CMT_FIFO_WW2END0_2", + "CMT_FIFO_NW2A1_10", + "CMT_FIFO_WW4C2_7", + "CMT_FIFO_L_LOGIC_OUTS17_11", + "CMT_OUT_FIFO_D43", + "CMT_FIFO_L_IMUX2_4", + "CMT_FIFO_L_IMUX41_3", + "CMT_FIFO_SE2A1_2", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_FIFO_L_IMUX24_5", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_IN_FIFO_SCANIN3", + "CMT_FIFO_NW2A1_1", + "CMT_FIFO_LH9_7", + "CMT_FIFO_L_IMUX18_7", + "CMT_FIFO_L_IMUX44_8", + "CMT_OUT_FIFO_TESTMODEB", + "CMT_FIFO_NW4A0_7", + "CMT_FIFO_NE4BEG1_9", + "CMT_FIFO_L_CLK0_0", + "CMT_FIFO_EE2A0_8", + "CMT_OUT_FIFO_SCANIN1", + "CMT_FIFO_EE4B3_11", + "CMT_FIFO_WR1END2_9", + "CMT_FIFO_L_IMUX8_11", + "CMT_FIFO_L_IMUX3_4", + "CMT_FIFO_L_IMUX34_0", + "CMT_FIFO_EE4A0_4", + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_FIFO_WW4A0_4", + "CMT_IN_FIFO_Q27", + "CMT_FIFO_LH3_8", + "CMT_FIFO_WR1END3_11", + "CMT_FIFO_EE2BEG1_2", + "CMT_FIFO_EE4C1_6", + "CMT_FIFO_EE4BEG2_11", + "CMT_FIFO_EL1BEG2_11", + "CMT_FIFO_L_IMUX39_10", + "CMT_FIFO_EL1BEG3_2", + "CMT_FIFO_L_IMUX1_3", + "CMT_FIFO_WW4A3_6", + "CMT_FIFO_WW4END0_8", + "CMT_FIFO_NE4C1_11", + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_IN_FIFO_Q32", + "CMT_FIFO_WW2A2_6", + "CMT_FIFO_NE4C3_7", + "CMT_FIFO_EE4B2_1", + "CMT_FIFO_L_FAN5_2", + "CMT_FIFO_EE2BEG1_9", + "CMT_OUT_FIFO_D52", + "CMT_FIFO_WR1END0_2", + "CMT_FIFO_WW4C3_5", + "CMT_FIFO_WL1END2_4", + "CMT_FIFO_EE4B2_7", + "CMT_FIFO_LH11_2", + "CMT_IN_FIFO_D32", + "CMT_FIFO_SE4BEG3_10", + "CMT_FIFO_SE4BEG3_3", + "CMT_FIFO_SW2A1_6", + "CMT_OUT_FIFO_Q83", + "CMT_OUT_FIFO_D45", + "CMT_FIFO_L_IMUX45_4", + "CMT_FIFO_WW4A1_2", + "CMT_FIFO_EE2BEG0_9", + "CMT_FIFO_WR1END3_9", + "CMT_FIFO_L_BYP3_10", + "CMT_FIFO_WL1END1_0", + "CMT_FIFO_L_BYP7_10", + "CMT_FIFO_WR1END1_2", + "CMT_FIFO_EE4C3_1", + "CMT_FIFO_WW2END3_0", + "CMT_OUT_FIFO_Q91", + "CMT_FIFO_WL1END2_1", + "CMT_FIFO_EE2BEG3_1", + "CMT_FIFO_EE4A1_1", + "CMT_FIFO_EE4A1_9", + "CMT_FIFO_EE2BEG3_4", + "CMT_FIFO_SE4BEG0_11", + "CMT_FIFO_WL1END0_7", + "CMT_FIFO_SW2A3_5", + "CMT_FIFO_SE2A2_2", + "CMT_FIFO_NE2A2_9", + "CMT_FIFO_WW4C1_4", + "CMT_FIFO_EE4B3_0", + "CMT_FIFO_EE4B3_10", + "CMT_FIFO_L_IMUX24_4", + "CMT_OUT_FIFO_Q90", + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_FIFO_SW4END3_4", + "CMT_FIFO_EE4C0_2", + "CMT_FIFO_EL1BEG3_0", + "CMT_IN_FIFO_Q76", + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_FIFO_SE4BEG0_0", + "CMT_FIFO_EL1BEG1_2", + "CMT_FIFO_L_IMUX2_5", + "CMT_FIFO_NW2A0_4", + "CMT_FIFO_L_LOGIC_OUTS18_0", + "CMT_FIFO_LH5_8", + "CMT_OUT_FIFO_D41", + "CMT_FIFO_NE2A3_7", + "CMT_FIFO_L_FAN1_9", + "CMT_FIFO_WW4A0_6", + "CMT_FIFO_L_IMUX16_0", + "CMT_FIFO_WW4A0_7", + "CMT_FIFO_WW4C3_11", + "CMT_FIFO_EE2A0_6", + "CMT_FIFO_SW4END1_0", + "CMT_IN_FIFO_Q11", + "CMT_FIFO_MONITOR_P_11", + "CMT_FIFO_SE4BEG3_5", + "CMT_FIFO_NW4END0_9", + "CMT_FIFO_SE4BEG1_3", + "CMT_FIFO_SE4BEG0_3", + "CMT_FIFO_L_BYP2_7", + "CMT_FIFO_WW4C0_9", + "CMT_FIFO_WW4END3_7", + "CMT_FIFO_L_IMUX36_11", + "CMT_FIFO_WL1END2_2", + "CMT_OUT_FIFO_D23", + "CMT_FIFO_L_IMUX33_6", + "CMT_FIFO_WW4A2_8", + "CMT_FIFO_WL1END0_6", + "CMT_FIFO_L_FAN1_8", + "CMT_FIFO_L_FAN6_0", + "CMT_FIFO_L_IMUX29_1", + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_IN_FIFO_Q37", + "CMT_FIFO_NE4BEG1_1", + "CMT_FIFO_LH2_9", + "CMT_FIFO_WW2END0_10", + "CMT_FIFO_EE2A2_0", + "CMT_FIFO_LH6_4", + "CMT_FIFO_EE4A1_8", + "CMT_FIFO_EE4B1_9", + "CMT_FIFO_NE2A0_6", + "CMT_FIFO_SE2A0_1", + "CMT_FIFO_LH11_10", + "CMT_FIFO_SW4A3_0", + "CMT_FIFO_L_IMUX2_0", + "CMT_FIFO_NE4C2_6", + "CMT_FIFO_EE4A2_7", + "CMT_FIFO_L_IMUX6_2", + "CMT_OUT_FIFO_D01", + "CMT_FIFO_EE4BEG1_0", + "CMT_FIFO_LH3_0", + "CMT_FIFO_L_CTRL0_0", + "CMT_FIFO_WW4C2_8", + "CMT_FIFO_ER1BEG3_4", + "CMT_FIFO_WW2END0_0", + "CMT_FIFO_L_IMUX37_9", + "CMT_FIFO_L_IMUX43_0", + "CMT_FIFO_EE2A1_1", + "CMT_FIFO_EL1BEG3_6", + "CMT_FIFO_L_IMUX20_5", + "CMT_FIFO_NW4A0_10", + "CMT_FIFO_L_BYP7_1", + "CMT_FIFO_NE2A2_7", + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_FIFO_L_IMUX0_7", + "CMT_FIFO_NE2A1_1", + "CMT_FIFO_L_IMUX6_6", + "CMT_FIFO_SE4BEG3_9", + "CMT_FIFO_L_IMUX13_9", + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_FIFO_NW4A2_8", + "CMT_FIFO_WR1END1_9", + "CMT_FIFO_L_IMUX47_2", + "CMT_FIFO_NW2A0_7", + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_FIFO_L_IMUX29_11", + "CMT_FIFO_L_IMUX14_4", + "CMT_FIFO_NW4A3_3", + "CMT_FIFO_WW2A3_8", + "CMT_FIFO_SW4END2_8", + "CMT_FIFO_EE2A3_11", + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_FIFO_EE2BEG1_1", + "CMT_FIFO_L_IMUX38_10", + "CMT_FIFO_WW4END0_11", + "CMT_FIFO_SE4BEG2_8", + "CMT_FIFO_L_BYP6_1", + "CMT_IN_FIFO_D23", + "CMT_FIFO_SE4C1_7", + "CMT_FIFO_LH8_4", + "CMT_FIFO_SE2A1_8", + "CMT_FIFO_LH6_10", + "CMT_FIFO_EE2A3_4", + "CMT_FIFO_WL1END0_8", + "CMT_FIFO_L_IMUX23_10", + "CMT_FIFO_L_FAN0_5", + "CMT_FIFO_L_IMUX0_4", + "CMT_FIFO_EE4BEG2_8", + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_FIFO_EE2BEG2_4", + "CMT_FIFO_LH9_4", + "CMT_FIFO_EE4BEG2_3", + "CMT_FIFO_L_IMUX15_3", + "CMT_FIFO_NW4A2_0", + "CMT_FIFO_L_IMUX46_3", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_FIFO_L_BYP1_6", + "CMT_FIFO_SW4END1_6", + "CMT_FIFO_L_IMUX42_4", + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_FIFO_EE4C2_10", + "CMT_FIFO_NE4BEG3_0", + "CMT_FIFO_NW4END1_0", + "CMT_FIFO_LH12_5", + "CMT_FIFO_L_LOGIC_OUTS14_0", + "CMT_FIFO_L_IMUX4_11", + "CMT_FIFO_L_IMUX6_5", + "CMT_OUT_FIFO_D26", + "CMT_FIFO_LH3_1", + "CMT_FIFO_EE4A3_0", + "CMT_FIFO_EE4B1_2", + "CMT_FIFO_WW2END2_4", + "CMT_IN_FIFO_Q84", + "CMT_FIFO_WW4END2_4", + "CMT_FIFO_EL1BEG0_11", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_8", + "CMT_OUT_FIFO_D03", + "CMT_FIFO_L_IMUX16_9", + "CMT_FIFO_NE4BEG3_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_FIFO_WW4C1_10", + "CMT_FIFO_L_LOGIC_OUTS4_6", + "CMT_FIFO_SW2A1_1", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_FIFO_L_FAN3_11", + "CMT_FIFO_L_LOGIC_OUTS18_10", + "CMT_FIFO_NE4C1_2", + "CMT_FIFO_SW4A1_8", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_11", + "CMT_FIFO_SE2A1_10", + "CMT_FIFO_WW2A0_7", + "CMT_FIFO_WL1END2_7", + "CMT_FIFO_NW4END3_3", + "CMT_FIFO_EE4C2_3", + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_FIFO_LH2_7", + "CMT_IN_FIFO_Q07", + "CMT_FIFO_WW2A2_8", + "CMT_FIFO_L_BYP4_3", + "CMT_FIFO_L_BYP2_11", + "CMT_FIFO_L_CTRL1_6", + "CMT_IN_FIFO_Q75", + "CMT_OUT_FIFO_Q82", + "CMT_FIFO_NE4BEG3_10", + "CMT_FIFO_NE2A0_2", + "CMT_FIFO_EE2BEG1_8", + "CMT_FIFO_ER1BEG1_8", + "CMT_FIFO_NW2A0_1", + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_FIFO_EE4C0_11", + "CMT_FIFO_SE4C0_7", + "CMT_FIFO_L_IMUX16_2", + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_FIFO_EE4BEG0_8", + "CMT_FIFO_SW4END0_2", + "CMT_FIFO_L_BYP7_5", + "CMT_FIFO_WW4END0_9", + "CMT_FIFO_EE4C2_1", + "CMT_FIFO_SW4A0_5", + "CMT_FIFO_L_FAN5_10", + "CMT_OUT_FIFO_Q73", + "CMT_FIFO_EE2A0_3", + "CMT_FIFO_EE2A2_8", + "CMT_FIFO_L_IMUX18_3", + "CMT_FIFO_MONITOR_P_9", + "FIFO_DQS_IOTOPHASER_22", + "CMT_IN_FIFO_Q65", + "CMT_FIFO_L_LOGIC_OUTS14_1", + "CMT_FIFO_L_IMUX7_8", + "CMT_FIFO_LH8_1", + "CMT_IN_FIFO_D40", + "CMT_FIFO_WW2A1_11", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "FIFO_DQS_IOTOPHASER_6", + "CMT_FIFO_L_BYP2_1", + "CMT_FIFO_SW4A1_9", + "CMT_IN_FIFO_Q96", + "CMT_FIFO_L_IMUX28_7", + "CMT_FIFO_L_IMUX38_5", + "CMT_FIFO_WW2A3_0", + "CMT_FIFO_L_BYP0_2", + "CMT_FIFO_L_BYP7_4", + "CMT_FIFO_L_BYP4_5", + "CMT_FIFO_LH1_1", + "CMT_FIFO_L_CLK0_8", + "CMT_OUT_FIFO_Q02", + "CMT_FIFO_EL1BEG0_5", + "CMT_FIFO_NW4END1_9", + "CMT_FIFO_L_IMUX37_0", + "CMT_FIFO_WW4END2_10", + "CMT_FIFO_WR1END2_11", + "CMT_IN_FIFO_SCANIN0", + "CMT_OUT_FIFO_SCANOUT0", + "CMT_FIFO_L_FAN5_8", + "CMT_FIFO_WW4END2_9", + "CMT_FIFO_L_CTRL0_9", + "CMT_FIFO_L_IMUX26_4", + "CMT_FIFO_NE2A2_3", + "CMT_FIFO_L_IMUX44_6", + "CMT_FIFO_L_IMUX19_2", + "CMT_FIFO_NW2A2_8", + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_FIFO_WW4END0_0", + "CMT_FIFO_L_IMUX8_4", + "CMT_FIFO_L_IMUX23_0", + "CMT_FIFO_NW2A0_11", + "CMT_FIFO_WW4A0_9", + "CMT_FIFO_L_BYP6_10", + "CMT_IN_FIFO_Q55", + "CMT_FIFO_L_IMUX9_6", + "CMT_FIFO_L_IMUX26_3", + "CMT_FIFO_EE4A1_10", + "CMT_FIFO_L_LOGIC_OUTS10_11", + "CMT_FIFO_WW4B2_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_FIFO_LH10_2", + "CMT_FIFO_EL1BEG3_1", + "CMT_IN_FIFO_D82", + "CMT_FIFO_SE4C1_8", + "CMT_FIFO_WW4B3_11", + "CMT_FIFO_WW4C2_6", + "CMT_FIFO_WW4END1_10", + "CMT_FIFO_NW4END3_4", + "CMT_FIFO_L_IMUX23_3", + "CMT_OUT_FIFO_D93", + "CMT_FIFO_L_IMUX23_8", + "CMT_FIFO_WW4END3_8", + "CMT_FIFO_SW4END0_11", + "CMT_FIFO_L_IMUX5_3", + "CMT_FIFO_L_LOGIC_OUTS23_1", + "CMT_FIFO_L_LOGIC_OUTS6_3", + "CMT_FIFO_WW2A1_9", + "CMT_FIFO_SE2A0_4", + "CMT_FIFO_LH9_2", + "CMT_FIFO_EE2A0_0", + "CMT_FIFO_L_BYP6_2", + "CMT_FIFO_SE4BEG0_6", + "CMT_OUT_FIFO_D54", + "CMT_FIFO_LH12_3", + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_FIFO_EE4B2_5", + "CMT_FIFO_EE4A2_4", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_FIFO_L_CLK1_11", + "CMT_FIFO_NE4C3_0", + "CMT_FIFO_EE4A2_2", + "CMT_FIFO_L_IMUX5_11", + "CMT_OUT_FIFO_EMPTY", + "CMT_FIFO_SW4A0_11", + "CMT_FIFO_WW2END3_1", + "CMT_IN_FIFO_Q63", + "CMT_FIFO_L_IMUX10_6", + "CMT_IN_FIFO_Q40", + "CMT_FIFO_L_FAN6_9", + "CMT_FIFO_L_FAN0_8", + "CMT_FIFO_L_IMUX47_4", + "CMT_FIFO_L_FAN2_5", + "CMT_FIFO_NE4BEG1_0", + "CMT_FIFO_L_IMUX40_11", + "CMT_FIFO_NW2A2_7", + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_FIFO_EE4B1_7", + "CMT_FIFO_EE4A3_6", + "CMT_FIFO_L_BYP0_4", + "CMT_FIFO_WW4END3_0", + "CMT_FIFO_WW4C2_1", + "CMT_FIFO_EE2A2_5", + "CMT_FIFO_WW2A0_2", + "CMT_FIFO_ER1BEG0_10", + "CMT_FIFO_L_IMUX3_8", + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_FIFO_EE2BEG0_11", + "CMT_FIFO_L_BYP7_11", + "CMT_FIFO_WW4B2_6", + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_FIFO_L_IMUX14_8", + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_FIFO_LH1_10", + "CMT_OUT_FIFO_Q11", + "CMT_IN_FIFO_D11", + "CMT_FIFO_SE4C3_5", + "CMT_FIFO_EE4C3_9", + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_FIFO_WW4END2_0", + "CMT_FIFO_EE4C3_4", + "CMT_FIFO_LH5_4", + "CMT_IN_FIFO_TESTREADDISB", + "CMT_FIFO_LH5_7", + "CMT_FIFO_WW4C3_4", + "CMT_FIFO_EE4C2_7", + "CMT_FIFO_NE4C1_10", + "CMT_FIFO_EL1BEG2_0", + "CMT_FIFO_NE4BEG1_7", + "CMT_FIFO_EE4C0_3", + "CMT_FIFO_L_CLK0_11", + "CMT_FIFO_ER1BEG1_0", + "CMT_FIFO_WW2END2_6", + "CMT_FIFO_SW2A0_5", + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_FIFO_EE4BEG1_8", + "CMT_FIFO_EE4B0_7", + "CMT_FIFO_SW4A1_10", + "CMT_FIFO_NE2A2_5", + "CMT_FIFO_NW4A3_0", + "CMT_FIFO_L_IMUX42_9", + "CMT_IN_FIFO_RDEN", + "CMT_FIFO_WW4A3_8", + "CMT_FIFO_NE2A2_8", + "CMT_FIFO_LH7_4", + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_FIFO_L_IMUX27_4", + "CMT_FIFO_L_IMUX16_8", + "CMT_FIFO_L_IMUX46_5", + "CMT_FIFO_SE4C2_2", + "CMT_FIFO_SW4A2_10", + "CMT_FIFO_WW4A2_1", + "CMT_FIFO_L_IMUX7_0", + "CMT_FIFO_L_IMUX33_1", + "CMT_FIFO_L_BYP3_11", + "CMT_IN_FIFO_Q81", + "CMT_FIFO_L_BYP6_4", + "CMT_FIFO_L_LOGIC_OUTS6_10", + "CMT_FIFO_WW4A1_10", + "CMT_FIFO_L_BYP7_2", + "CMT_FIFO_NW4A1_8", + "CMT_FIFO_SE2A0_0", + "CMT_OUT_FIFO_D63", + "CMT_FIFO_SW4END1_5", + "CMT_FIFO_EE2BEG3_9", + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_FIFO_WW2A1_4", + "CMT_FIFO_SW4END1_10", + "CMT_FIFO_MONITOR_N_0", + "CMT_FIFO_NW4END0_1", + "CMT_FIFO_L_IMUX19_11", + "CMT_FIFO_LH3_2", + "CMT_FIFO_WR1END0_8", + "CMT_FIFO_L_IMUX0_1", + "CMT_IN_FIFO_Q67", + "CMT_FIFO_WW2A2_5", + "CMT_IN_FIFO_D01", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_3", + "CMT_FIFO_WW4B2_5", + "CMT_FIFO_EE4BEG2_9", + "CMT_FIFO_SE4C2_7", + "CMT_FIFO_L_IMUX32_3", + "CMT_FIFO_L_FAN2_11", + "CMT_FIFO_L_IMUX14_10", + "CMT_OUT_FIFO_D67", + "CMT_OUT_FIFO_D82", + "CMT_FIFO_EE2BEG1_7", + "CMT_FIFO_L_LOGIC_OUTS2_10", + "CMT_FIFO_L_IMUX11_8", + "CMT_FIFO_L_BYP3_7", + "CMT_FIFO_L_BYP6_3", + "CMT_FIFO_EE4C1_2", + "CMT_FIFO_EE4BEG0_9", + "CMT_FIFO_WW4C1_5", + "CMT_FIFO_MONITOR_P_0", + "CMT_FIFO_EE2BEG0_3", + "CMT_FIFO_L_BYP1_2", + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_FIFO_L_BYP4_9", + "CMT_FIFO_WW4B1_0", + "CMT_FIFO_NW2A1_11", + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_FIFO_LH2_6", + "CMT_FIFO_L_IMUX24_0", + "CMT_FIFO_SE4BEG3_1", + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_FIFO_L_LOGIC_OUTS16_1", + "CMT_FIFO_L_IMUX24_3", + "CMT_FIFO_L_FAN1_4", + "CMT_FIFO_L_IMUX21_11", + "CMT_FIFO_NW2A2_5", + "CMT_FIFO_LH1_0", + "CMT_FIFO_WW4C0_4", + "CMT_FIFO_EL1BEG1_3", + "CMT_OUT_FIFO_ALMOSTFULL", + "CMT_FIFO_EL1BEG1_8", + "CMT_IN_FIFO_Q56", + "CMT_FIFO_L_FAN4_11", + "CMT_FIFO_L_IMUX13_7", + "CMT_FIFO_LH2_5", + "CMT_FIFO_WL1END2_3", + "CMT_FIFO_NE4C3_5", + "CMT_FIFO_EE4B1_1", + "CMT_FIFO_L_IMUX24_6", + "CMT_FIFO_L_IMUX47_6", + "CMT_FIFO_WW4END1_1", + "CMT_FIFO_WL1END2_0", + "CMT_FIFO_L_IMUX28_1", + "CMT_FIFO_NE2A3_0", + "CMT_FIFO_EE4BEG0_2", + "CMT_FIFO_EE2BEG2_11", + "CMT_IN_FIFO_D53", + "CMT_FIFO_WR1END2_8", + "CMT_FIFO_L_IMUX39_3", + "CMT_FIFO_L_BYP0_7", + "CMT_FIFO_L_CLK0_6", + "CMT_FIFO_SW2A2_2", + "CMT_FIFO_SW4END2_5", + "CMT_FIFO_SE4C3_6", + "CMT_FIFO_L_IMUX16_10", + "CMT_FIFO_L_IMUX40_4", + "CMT_FIFO_EE2A1_8", + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_FIFO_ER1BEG3_0", + "CMT_FIFO_EE4B2_0", + "CMT_FIFO_L_BYP1_10", + "CMT_FIFO_WW4B0_6", + "CMT_FIFO_WW4END2_3", + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_IN_FIFO_Q46", + "CMT_FIFO_L_IMUX8_1", + "CMT_FIFO_L_BYP1_5", + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_OUT_FIFO_D33", + "CMT_IN_FIFO_D31", + "CMT_FIFO_L_IMUX13_6", + "CMT_FIFO_LH6_0", + "CMT_FIFO_L_IMUX42_1", + "CMT_FIFO_SE2A1_5", + "CMT_FIFO_L_IMUX17_10", + "CMT_IN_FIFO_D43", + "CMT_FIFO_NW4END1_10", + "CMT_FIFO_L_IMUX21_7", + "CMT_FIFO_NW4A0_1", + "CMT_FIFO_MONITOR_N_11", + "CMT_FIFO_L_IMUX4_2", + "CMT_IN_FIFO_Q54", + "CMT_OUT_FIFO_D17", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_FIFO_NE4C1_0", + "CMT_FIFO_LH6_5", + "CMT_FIFO_WW2END2_3", + "CMT_FIFO_WW2END0_1", + "CMT_FIFO_L_IMUX34_11", + "CMT_FIFO_L_BYP3_3", + "CMT_FIFO_WW4B1_3", + "CMT_FIFO_SW4A1_2", + "CMT_FIFO_L_FAN7_10", + "CMT_FIFO_WL1END1_11", + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_FIFO_LH10_3", + "CMT_FIFO_EL1BEG0_2", + "CMT_FIFO_EE4BEG3_1", + "CMT_FIFO_EE2BEG3_7", + "CMT_FIFO_L_IMUX11_10", + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_FIFO_L_IMUX47_9", + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_FIFO_WW4B2_4", + "CMT_FIFO_L_LOGIC_OUTS21_0", + "CMT_FIFO_NE2A3_3", + "CMT_FIFO_WR1END2_6", + "CMT_FIFO_L_FAN5_6", + "CMT_FIFO_L_IMUX0_5", + "CMT_FIFO_L_IMUX27_2", + "CMT_FIFO_WW2END1_11", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_FIFO_L_IMUX3_11", + "CMT_FIFO_MONITOR_N_7", + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_FIFO_L_IMUX22_1", + "CMT_IN_FIFO_Q33", + "CMT_FIFO_WW4C2_11", + "CMT_FIFO_WW4B0_9", + "CMT_FIFO_LH3_10", + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_FIFO_L_IMUX42_7", + "CMT_FIFO_ER1BEG0_0", + "CMT_FIFO_EE2A1_11", + "CMT_FIFO_SW4END3_11", + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_FIFO_L_BYP0_10", + "CMT_FIFO_L_IMUX17_8", + "CMT_FIFO_NW4A1_10", + "CMT_FIFO_NE4BEG2_7", + "CMT_FIFO_L_IMUX22_9", + "CMT_OUT_FIFO_Q12", + "FIFO_DQS_IOTOPHASER_44", + "CMT_FIFO_SW4A3_5", + "CMT_FIFO_L_IMUX37_3", + "CMT_FIFO_L_IMUX37_5", + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_FIFO_L_IMUX47_11", + "CMT_FIFO_WR1END2_10", + "CMT_FIFO_WL1END0_5", + "CMT_FIFO_WL1END0_3", + "CMT_FIFO_EE4C1_7", + "CMT_FIFO_L_IMUX34_9", + "CMT_FIFO_ER1BEG2_1", + "CMT_FIFO_SE4BEG1_7", + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_FIFO_EE2BEG2_1", + "CMT_FIFO_SW2A3_7", + "CMT_FIFO_NW4A3_1", + "CMT_FIFO_NW2A2_2", + "CMT_OUT_FIFO_Q43", + "CMT_FIFO_SE2A2_0", + "CMT_FIFO_WW4END3_9", + "CMT_FIFO_L_IMUX2_3", + "CMT_OUT_FIFO_Q51", + "CMT_FIFO_L_BYP3_2", + "CMT_FIFO_NE2A3_2", + "CMT_FIFO_WW4B3_2", + "CMT_FIFO_L_IMUX25_1", + "CMT_IN_FIFO_D10", + "CMT_FIFO_NE2A0_0", + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_OUT_FIFO_TESTREADDISB", + "CMT_FIFO_WL1END1_7", + "CMT_FIFO_SW2A2_3", + "CMT_FIFO_SW2A0_10", + "CMT_FIFO_SE4BEG2_6", + "CMT_FIFO_NE4C0_1", + "CMT_FIFO_EE2A1_5", + "CMT_FIFO_WR1END1_0", + "CMT_FIFO_L_BYP0_8", + "CMT_FIFO_EE4B0_0", + "CMT_FIFO_NE4C2_9", + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_FIFO_EE4A1_3", + "CMT_FIFO_L_BYP4_4", + "CMT_FIFO_L_FAN4_7", + "CMT_FIFO_LH9_3", + "CMT_FIFO_SE4BEG0_8", + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_IN_FIFO_Q64", + "CMT_FIFO_EE4C1_11", + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_FIFO_SW4END2_7", + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_FIFO_WL1END0_0", + "CMT_FIFO_EL1BEG3_9", + "CMT_FIFO_LH10_1", + "CMT_FIFO_WW4A3_10", + "CMT_FIFO_SW2A1_4", + "CMT_FIFO_L_FAN5_7", + "CMT_FIFO_L_IMUX42_0", + "CMT_FIFO_L_IMUX43_11", + "CMT_FIFO_WW2END0_3", + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_FIFO_EE4BEG1_2", + "CMT_FIFO_L_IMUX42_5", + "CMT_FIFO_L_IMUX17_5", + "CMT_FIFO_SW4A3_7", + "CMT_FIFO_EE2A1_3", + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_FIFO_L_IMUX26_8", + "CMT_FIFO_SE4BEG1_8", + "CMT_FIFO_L_IMUX14_7", + "CMT_FIFO_L_IMUX39_2", + "CMT_FIFO_SW4END0_10", + "CMT_IN_FIFO_SCANIN2", + "CMT_FIFO_L_IMUX36_5", + "CMT_FIFO_NE2A1_6", + "CMT_FIFO_L_CLK0_3", + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_FIFO_L_IMUX12_3", + "CMT_FIFO_EE4B1_10", + "CMT_FIFO_NW2A0_6", + "CMT_FIFO_LH7_9", + "CMT_FIFO_NW4END2_0", + "CMT_FIFO_NW4END1_8", + "CMT_FIFO_SW4END3_2", + "CMT_IN_FIFO_SCANENB", + "CMT_FIFO_L_IMUX43_7", + "CMT_FIFO_WW2A0_8", + "CMT_OUT_FIFO_Q42", + "CMT_FIFO_L_IMUX3_5", + "CMT_FIFO_SW2A3_9", + "CMT_FIFO_EE4A1_4", + "CMT_FIFO_SE4BEG2_11", + "CMT_FIFO_L_IMUX46_11", + "CMT_FIFO_EE2BEG3_10", + "CMT_FIFO_ER1BEG0_4", + "CMT_FIFO_L_BYP1_1", + "CMT_FIFO_L_IMUX5_5", + "CMT_FIFO_MONITOR_N_8", + "CMT_FIFO_L_BYP2_5", + "CMT_FIFO_SW4A3_2", + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_FIFO_L_IMUX0_11", + "CMT_FIFO_EL1BEG3_5", + "CMT_FIFO_L_IMUX6_7", + "CMT_OUT_FIFO_ALMOSTEMPTY", + "CMT_FIFO_NW4A0_4", + "CMT_FIFO_EE4BEG1_6", + "CMT_FIFO_EE2BEG2_6", + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_FIFO_MONITOR_N_4", + "CMT_FIFO_L_FAN0_10", + "CMT_FIFO_WW4A2_11", + "CMT_FIFO_SE4BEG1_2", + "CMT_FIFO_SW4A2_9", + "CMT_IN_FIFO_SCANIN1", + "CMT_FIFO_LH12_4", + "CMT_IN_FIFO_Q35", + "CMT_FIFO_L_IMUX5_6", + "CMT_FIFO_L_IMUX18_2", + "CMT_IN_FIFO_RDCLK", + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_FIFO_SW4A2_4", + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_FIFO_SE4C0_6", + "CMT_OUT_FIFO_D14", + "CMT_FIFO_SW4END1_3", + "CMT_FIFO_WL1END1_4", + "CMT_FIFO_EE4B3_3", + "CMT_FIFO_WW2END1_10", + "CMT_FIFO_NW4A1_0", + "CMT_FIFO_SE2A1_1", + "CMT_FIFO_L_FAN7_5", + "CMT_FIFO_EL1BEG0_6", + "CMT_FIFO_L_IMUX14_3", + "CMT_FIFO_LH1_6", + "CMT_FIFO_NE4BEG1_3", + "CMT_FIFO_L_IMUX16_4", + "CMT_FIFO_NE4C1_6", + "CMT_IN_FIFO_Q97", + "CMT_FIFO_SW4END0_3", + "CMT_FIFO_WL1END3_11", + "CMT_FIFO_L_BYP7_9", + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_FIFO_WW4A3_2", + "CMT_FIFO_L_FAN0_4", + "CMT_FIFO_MONITOR_P_3", + "CMT_FIFO_WW2END1_2", + "CMT_FIFO_SE2A3_5", + "CMT_FIFO_EE4B3_8", + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_FIFO_L_IMUX1_9", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_FIFO_WW2END0_4", + "CMT_FIFO_L_FAN4_8", + "CMT_FIFO_NW4END0_11", + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_FIFO_LH11_0", + "CMT_FIFO_L_IMUX27_1", + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_FIFO_SW4END3_5", + "CMT_FIFO_SW4A0_6", + "CMT_OUT_FIFO_D37", + "CMT_OUT_FIFO_Q50", + "CMT_FIFO_NW4END3_6", + "CMT_FIFO_NE4C0_5", + "CMT_FIFO_EE4BEG1_11", + "CMT_IN_FIFO_D67", + "CMT_FIFO_NW2A3_7", + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_FIFO_NE4BEG2_3", + "CMT_FIFO_L_IMUX29_5", + "CMT_FIFO_WL1END3_8", + "CMT_FIFO_L_IMUX20_9", + "CMT_IN_FIFO_D72", + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_FIFO_L_LOGIC_OUTS3_0", + "CMT_FIFO_L_IMUX26_9", + "CMT_FIFO_NE4C1_1", + "CMT_FIFO_WW4B3_6", + "CMT_FIFO_EE2BEG1_11", + "CMT_FIFO_NE4C3_11", + "CMT_FIFO_LH5_1", + "CMT_FIFO_L_FAN0_9", + "CMT_FIFO_SE2A2_8", + "CMT_FIFO_EE4BEG1_1", + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_FIFO_LH9_8", + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_FIFO_L_IMUX39_1", + "CMT_FIFO_L_IMUX3_0", + "CMT_FIFO_NW4END3_7", + "CMT_FIFO_EE4C1_9", + "CMT_FIFO_EL1BEG2_5", + "CMT_OUT_FIFO_FULL", + "CMT_FIFO_WW4END0_2", + "CMT_FIFO_NW2A1_5", + "CMT_FIFO_L_IMUX5_2", + "CMT_FIFO_NW4END2_1", + "CMT_FIFO_EL1BEG1_1", + "CMT_FIFO_EE2A3_2", + "CMT_FIFO_EE4B3_5", + "CMT_FIFO_L_IMUX7_6", + "CMT_FIFO_L_IMUX45_5", + "CMT_IN_FIFO_D61", + "CMT_FIFO_ER1BEG0_6", + "CMT_FIFO_ER1BEG3_5", + "CMT_FIFO_EE4A0_9", + "CMT_FIFO_NE4BEG0_1", + "CMT_FIFO_WW2A1_8", + "CMT_FIFO_EL1BEG0_4", + "CMT_FIFO_L_BYP1_11", + "CMT_FIFO_EE4A3_9", + "CMT_FIFO_EE2BEG2_10", + "CMT_OUT_FIFO_D76", + "CMT_FIFO_L_IMUX4_9", + "CMT_FIFO_L_FAN7_11", + "CMT_FIFO_L_IMUX18_5", + "CMT_FIFO_L_CTRL0_11", + "CMT_FIFO_EE4B2_8", + "CMT_FIFO_L_FAN4_9", + "CMT_FIFO_SE4BEG2_7", + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_FIFO_EE4BEG3_4", + "CMT_FIFO_NW4A3_8", + "CMT_FIFO_SW4A3_8", + "CMT_FIFO_L_FAN7_3", + "CMT_FIFO_SW4END0_5", + "CMT_FIFO_SE2A2_4", + "CMT_FIFO_LH9_11", + "CMT_FIFO_L_CTRL1_2", + "CMT_FIFO_L_IMUX23_9", + "CMT_FIFO_WW4A0_3", + "CMT_FIFO_L_LOGIC_OUTS3_3", + "CMT_FIFO_ER1BEG3_6", + "CMT_FIFO_L_IMUX27_0", + "CMT_FIFO_L_IMUX31_11", + "CMT_FIFO_NW2A2_4", + "CMT_FIFO_NW2A3_9", + "CMT_FIFO_L_IMUX43_3", + "CMT_FIFO_L_IMUX4_8", + "CMT_FIFO_LH4_11", + "CMT_FIFO_L_IMUX42_3", + "CMT_FIFO_NW4A0_0", + "CMT_FIFO_L_IMUX31_3", + "CMT_FIFO_L_CLK0_2", + "CMT_FIFO_ER1BEG2_4", + "CMT_FIFO_L_IMUX0_9", + "CMT_FIFO_WW2END2_0", + "CMT_FIFO_SE4BEG0_9", + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_FIFO_SW2A1_10", + "CMT_FIFO_L_IMUX16_5", + "CMT_FIFO_SE2A3_3", + "CMT_FIFO_WW2END2_5", + "CMT_FIFO_NW4A1_5", + "CMT_FIFO_SE4BEG3_4", + "CMT_FIFO_L_LOGIC_OUTS17_0", + "CMT_IN_FIFO_Q77", + "CMT_FIFO_NE4C0_8", + "CMT_FIFO_L_FAN5_0", + "CMT_FIFO_L_CLK0_1", + "CMT_FIFO_SE2A0_3", + "CMT_FIFO_L_IMUX43_1", + "CMT_OUT_FIFO_D86", + "CMT_FIFO_EE2A1_9", + "CMT_FIFO_L_IMUX15_9", + "CMT_OUT_FIFO_D02", + "CMT_OUT_FIFO_D65", + "CMT_FIFO_EE4A1_5", + "CMT_FIFO_L_BYP0_3", + "CMT_FIFO_LH8_9", + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_OUT_FIFO_Q63", + "CMT_FIFO_SE4BEG0_5", + "CMT_FIFO_LH2_2", + "CMT_FIFO_L_IMUX40_9", + "CMT_IN_FIFO_Q43", + "CMT_OUT_FIFO_D53", + "CMT_FIFO_L_BYP4_1", + "CMT_FIFO_NW2A3_5", + "CMT_FIFO_L_IMUX40_3", + "CMT_FIFO_SE4C2_1", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_FIFO_WW4C2_9", + "CMT_FIFO_NE4C2_5", + "CMT_FIFO_L_IMUX20_8", + "CMT_FIFO_EE2A1_6", + "CMT_IN_FIFO_Q14", + "CMT_FIFO_L_IMUX8_2", + "CMT_FIFO_L_IMUX21_9", + "CMT_FIFO_WR1END1_3", + "CMT_FIFO_LH9_1", + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_IN_FIFO_Q34", + "CMT_FIFO_L_LOGIC_OUTS21_11", + "CMT_FIFO_NE4C3_2", + "CMT_FIFO_WW4B3_3", + "CMT_FIFO_L_IMUX42_10", + "CMT_FIFO_L_FAN6_6", + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_FIFO_NE4C0_10", + "CMT_FIFO_L_BYP3_5", + "CMT_OUT_FIFO_D34", + "CMT_FIFO_L_IMUX22_5", + "CMT_FIFO_SE2A2_7", + "CMT_FIFO_L_IMUX8_5", + "CMT_FIFO_L_BYP5_0", + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_FIFO_L_IMUX47_5", + "CMT_FIFO_MONITOR_N_5", + "CMT_FIFO_L_FAN5_5", + "CMT_FIFO_L_IMUX17_4", + "CMT_FIFO_L_LOGIC_OUTS6_11", + "CMT_FIFO_EL1BEG2_9", + "CMT_FIFO_L_IMUX7_11", + "CMT_FIFO_EE2A3_1", + "CMT_FIFO_EL1BEG1_10", + "CMT_FIFO_EE2BEG0_8", + "CMT_FIFO_L_FAN6_5", + "CMT_FIFO_L_IMUX27_8", + "CMT_FIFO_NE2A3_8", + "CMT_FIFO_L_IMUX31_6", + "CMT_OUT_FIFO_D36", + "CMT_FIFO_WW4A0_5", + "CMT_FIFO_L_IMUX27_3", + "CMT_FIFO_EE4BEG2_6", + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_FIFO_L_IMUX37_1", + "CMT_FIFO_L_IMUX2_6", + "CMT_OUT_FIFO_Q03", + "CMT_FIFO_WL1END1_10", + "CMT_IN_FIFO_D00", + "CMT_FIFO_LH4_7", + "CMT_FIFO_ER1BEG0_8", + "CMT_FIFO_L_IMUX11_4", + "CMT_FIFO_LH2_1", + "CMT_FIFO_WW2A0_10", + "CMT_FIFO_WW4C1_2", + "CMT_FIFO_L_LOGIC_OUTS6_5", + "CMT_FIFO_WL1END3_1", + "CMT_FIFO_WW4A0_2", + "CMT_OUT_FIFO_D44", + "CMT_IN_FIFO_Q61", + "CMT_FIFO_NW4END2_11", + "CMT_FIFO_NW2A3_4", + "CMT_FIFO_L_IMUX35_1", + "CMT_FIFO_NE4C0_6", + "CMT_FIFO_ER1BEG2_3", + "CMT_FIFO_L_IMUX7_10", + "CMT_FIFO_SW4END1_8", + "CMT_FIFO_L_IMUX29_0", + "CMT_FIFO_ER1BEG2_0", + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_FIFO_WW4C0_0", + "CMT_FIFO_L_FAN3_3", + "CMT_FIFO_ER1BEG1_10", + "CMT_FIFO_WW4A0_11", + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_FIFO_LH1_7", + "CMT_FIFO_WW4C3_8", + "CMT_FIFO_EL1BEG3_4", + "CMT_IN_FIFO_Q66", + "CMT_FIFO_EE4BEG3_3", + "CMT_FIFO_L_IMUX28_9", + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_FIFO_L_IMUX25_4", + "CMT_FIFO_SE4BEG1_1", + "CMT_FIFO_EE2BEG2_5", + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_FIFO_L_IMUX2_11", + "CMT_FIFO_L_IMUX5_10", + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_FIFO_L_BYP7_6", + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_FIFO_WW2A3_9", + "CMT_FIFO_WW4B2_1", + "CMT_FIFO_L_CLK0_10", + "CMT_FIFO_L_IMUX22_8", + "CMT_FIFO_WW4A2_9", + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_FIFO_WW4C2_3", + "CMT_FIFO_L_BYP5_11", + "CMT_OUT_FIFO_Q00", + "CMT_OUT_FIFO_Q30", + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_FIFO_L_IMUX43_2", + "CMT_FIFO_EE4BEG2_2", + "CMT_FIFO_L_BYP2_3", + "CMT_FIFO_WW2A2_2", + "CMT_FIFO_WR1END2_1", + "CMT_FIFO_NW4END3_5", + "CMT_FIFO_L_LOGIC_OUTS14_10", + "CMT_FIFO_L_CTRL1_5", + "CMT_IN_FIFO_D50", + "CMT_FIFO_NW2A2_9", + "CMT_FIFO_L_IMUX37_2", + "CMT_FIFO_L_IMUX41_4", + "CMT_FIFO_NE4C0_9", + "CMT_IN_FIFO_Q94", + "CMT_FIFO_L_IMUX7_1", + "CMT_FIFO_EE4C0_6", + "CMT_FIFO_NE4BEG3_7", + "CMT_FIFO_L_IMUX44_2", + "CMT_OUT_FIFO_D11", + "CMT_FIFO_NE4BEG1_11", + "CMT_FIFO_SW2A2_9", + "CMT_FIFO_EE4C0_0", + "CMT_FIFO_EE2BEG1_6", + "CMT_FIFO_L_IMUX6_9", + "CMT_FIFO_EE4BEG0_7", + "CMT_FIFO_WW4A2_4", + "CMT_FIFO_NE2A0_3", + "CMT_FIFO_L_FAN5_9", + "CMT_FIFO_L_IMUX29_6", + "CMT_FIFO_L_IMUX5_9", + "CMT_FIFO_SE4C3_2", + "CMT_FIFO_SW2A0_4", + "CMT_FIFO_L_IMUX30_1", + "CMT_FIFO_L_LOGIC_OUTS16_0", + "CMT_FIFO_ER1BEG3_3", + "CMT_FIFO_EE4BEG0_4", + "CMT_FIFO_NW2A3_0", + "CMT_FIFO_WW4B2_9", + "CMT_FIFO_L_FAN2_1", + "CMT_FIFO_LH1_8", + "CMT_OUT_FIFO_SCANIN2", + "CMT_FIFO_EE2A1_10", + "CMT_FIFO_EE4C3_5", + "CMT_FIFO_SW4END0_6", + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_IN_FIFO_D12", + "CMT_FIFO_WW2A3_1", + "CMT_FIFO_WW4A3_11", + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_FIFO_SW4END0_7", + "CMT_FIFO_L_IMUX1_7", + "CMT_FIFO_L_IMUX30_7", + "CMT_FIFO_NE2A1_0", + "CMT_FIFO_L_BYP5_1", + "CMT_FIFO_EE2A3_0", + "CMT_IN_FIFO_D57", + "CMT_FIFO_EE2BEG2_3", + "CMT_FIFO_NE2A2_11", + "CMT_FIFO_NE4BEG1_4", + "CMT_FIFO_NE4BEG0_0", + "CMT_FIFO_WW2A1_6", + "CMT_FIFO_SW4A0_0", + "CMT_FIFO_WW2A1_1", + "CMT_FIFO_LH3_3", + "CMT_FIFO_L_IMUX34_8", + "CMT_FIFO_L_IMUX41_6", + "CMT_FIFO_L_BYP5_3", + "CMT_FIFO_L_IMUX9_1", + "CMT_FIFO_NE2A0_1", + "CMT_FIFO_LH1_5", + "CMT_FIFO_L_IMUX33_7", + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_FIFO_WW2A0_11", + "CMT_FIFO_SE2A3_10", + "CMT_FIFO_L_BYP5_10", + "CMT_FIFO_L_IMUX38_2", + "CMT_FIFO_NE4BEG0_7", + "CMT_FIFO_L_LOGIC_OUTS15_10", + "CMT_FIFO_WW4B2_2", + "CMT_FIFO_L_CLK1_7", + "CMT_FIFO_L_CLK1_4", + "CMT_FIFO_WW4C0_5", + "CMT_FIFO_WW4END3_3", + "CMT_FIFO_WW4B0_3", + "CMT_OUT_FIFO_D06", + "CMT_FIFO_L_IMUX46_8", + "CMT_IN_FIFO_TESTMODEB", + "CMT_FIFO_WL1END1_5", + "CMT_FIFO_L_CTRL1_8", + "CMT_FIFO_EE2BEG0_2", + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_FIFO_ER1BEG2_2", + "CMT_FIFO_WW2A0_4", + "CMT_FIFO_L_CLK0_7", + "CMT_FIFO_L_IMUX24_10", + "CMT_FIFO_L_IMUX35_8", + "CMT_FIFO_LH9_10", + "CMT_FIFO_L_IMUX31_7", + "CMT_FIFO_EL1BEG1_9", + "CMT_IN_FIFO_Q05", + "CMT_FIFO_WW4END2_2", + "CMT_FIFO_L_FAN6_3", + "CMT_FIFO_NE4C3_9", + "CMT_FIFO_NW2A3_8", + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_FIFO_L_IMUX4_0", + "CMT_FIFO_L_IMUX35_0", + "CMT_FIFO_WW4A3_3", + "CMT_FIFO_WW2A2_3", + "CMT_FIFO_L_LOGIC_OUTS16_2", + "CMT_FIFO_EE2A1_0", + "CMT_FIFO_L_IMUX3_2", + "CMT_FIFO_L_BYP7_3", + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_FIFO_L_IMUX22_11", + "CMT_FIFO_NW2A1_9", + "CMT_IN_FIFO_D91", + "CMT_FIFO_WW2A2_0", + "CMT_FIFO_L_BYP2_0", + "CMT_FIFO_LH12_1", + "CMT_FIFO_WW2END0_8", + "CMT_FIFO_L_LOGIC_OUTS14_9", + "CMT_FIFO_NW4A3_2", + "CMT_FIFO_WW2END2_11", + "CMT_FIFO_WW4C0_7", + "CMT_FIFO_EE4B2_2", + "CMT_FIFO_SW2A1_7", + "CMT_FIFO_SW2A1_2", + "CMT_FIFO_L_FAN3_8", + "CMT_FIFO_NW4END0_4", + "CMT_FIFO_L_IMUX19_3", + "CMT_FIFO_MONITOR_P_10", + "CMT_FIFO_L_LOGIC_OUTS2_0", + "CMT_IN_FIFO_D56", + "CMT_FIFO_EE4C0_1", + "CMT_FIFO_WW4A3_5", + "CMT_FIFO_LH12_9", + "CMT_IN_FIFO_Q72", + "CMT_FIFO_MONITOR_P_2", + "CMT_FIFO_SE2A1_7", + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_FIFO_SW4END3_8", + "CMT_FIFO_SW4A1_6", + "CMT_FIFO_SE2A2_1", + "CMT_FIFO_L_IMUX20_2", + "CMT_FIFO_LH7_6", + "CMT_OUT_FIFO_D16", + "CMT_FIFO_WL1END1_3", + "CMT_FIFO_EE4A3_5", + "CMT_FIFO_EE2BEG3_3", + "CMT_FIFO_LH5_11", + "CMT_FIFO_WW4A0_10", + "CMT_FIFO_ER1BEG1_4", + "CMT_FIFO_EE4A0_6", + "CMT_FIFO_WW2END3_5", + "CMT_FIFO_L_FAN0_6", + "CMT_FIFO_EE4BEG3_0", + "CMT_FIFO_WR1END3_0", + "CMT_FIFO_EE2BEG0_5", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_FIFO_SE4BEG0_1", + "CMT_FIFO_WW4C3_10", + "CMT_FIFO_EE2BEG3_6", + "CMT_FIFO_L_IMUX27_9", + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_OUT_FIFO_Q64", + "CMT_FIFO_LH12_11", + "CMT_FIFO_SE2A2_5", + "CMT_FIFO_L_IMUX19_5", + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_FIFO_L_IMUX39_4", + "CMT_FIFO_SW4END2_3", + "CMT_FIFO_NW4END1_11", + "CMT_FIFO_L_IMUX1_4", + "CMT_FIFO_WR1END2_0", + "CMT_FIFO_WW4C3_2", + "CMT_FIFO_EE4C2_4", + "CMT_FIFO_NW2A2_1", + "CMT_FIFO_L_IMUX15_0", + "CMT_FIFO_SW4A0_3", + "CMT_FIFO_SE4C3_1", + "CMT_FIFO_NE4BEG0_3", + "CMT_OUT_FIFO_D90", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_FIFO_L_IMUX23_4", + "CMT_FIFO_L_FAN3_0", + "CMT_FIFO_SE4BEG3_11", + "CMT_FIFO_L_IMUX15_8", + "CMT_FIFO_ER1BEG2_9", + "CMT_FIFO_L_IMUX34_2", + "CMT_OUT_FIFO_D94", + "CMT_FIFO_L_IMUX20_10", + "CMT_FIFO_L_IMUX30_4", + "CMT_FIFO_L_IMUX30_9", + "CMT_FIFO_L_IMUX38_6", + "CMT_FIFO_NW2A1_3", + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_FIFO_EE4A3_11", + "CMT_OUT_FIFO_D95", + "CMT_FIFO_L_IMUX10_5", + "CMT_FIFO_EE4A2_10", + "CMT_OUT_FIFO_TESTWRITEDISB", + "CMT_FIFO_EL1BEG3_11", + "CMT_FIFO_EE4C0_5", + "CMT_OUT_FIFO_Q65", + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_IN_FIFO_D90", + "CMT_IN_FIFO_Q60", + "CMT_FIFO_ER1BEG1_9", + "CMT_FIFO_L_FAN1_0", + "CMT_FIFO_L_IMUX27_6", + "CMT_FIFO_L_IMUX34_3", + "CMT_FIFO_NE4C0_11", + "CMT_FIFO_L_CTRL1_3", + "CMT_OUT_FIFO_D92", + "CMT_FIFO_L_IMUX9_3", + "CMT_FIFO_SW4A1_4", + "CMT_FIFO_EE4C2_0", + "CMT_FIFO_EE4B1_8", + "CMT_FIFO_EE2A1_7", + "CMT_FIFO_NW4A2_5", + "CMT_FIFO_WW4A3_1", + "CMT_FIFO_WW2A2_7", + "CMT_FIFO_WR1END0_6", + "CMT_IN_FIFO_D93", + "CMT_OUT_FIFO_Q10", + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_FIFO_L_BYP7_8", + "CMT_FIFO_L_IMUX11_11", + "CMT_FIFO_L_IMUX13_0", + "CMT_FIFO_L_BYP1_3", + "CMT_FIFO_WW2END3_11", + "CMT_FIFO_EL1BEG1_0", + "CMT_FIFO_L_BYP2_6", + "CMT_FIFO_L_IMUX2_8", + "CMT_FIFO_NW4A3_10", + "CMT_FIFO_L_IMUX32_11", + "CMT_FIFO_WR1END3_1", + "CMT_FIFO_WW4C3_1", + "CMT_FIFO_L_IMUX17_0", + "CMT_FIFO_L_CLK1_9", + "CMT_FIFO_NE2A3_11", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_FIFO_NW4END0_2", + "CMT_FIFO_L_IMUX24_7", + "CMT_FIFO_WR1END3_2", + "CMT_FIFO_L_LOGIC_OUTS3_9", + "CMT_FIFO_SE4C0_4", + "CMT_FIFO_SW4END0_8", + "CMT_FIFO_L_IMUX10_3", + "CMT_FIFO_NE4BEG3_6", + "CMT_FIFO_NE2A2_10", + "CMT_IN_FIFO_Q70", + "CMT_FIFO_LH7_3", + "CMT_FIFO_L_BYP6_9", + "CMT_FIFO_L_IMUX45_9", + "CMT_FIFO_L_IMUX36_1", + "CMT_FIFO_NW2A0_9", + "CMT_FIFO_SW2A0_9", + "CMT_FIFO_WW2END3_7", + "CMT_FIFO_NE4C0_0", + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_IN_FIFO_Q36", + "CMT_FIFO_EE4B3_2", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_FIFO_NW2A3_11", + "CMT_FIFO_NE2A0_7", + "CMT_FIFO_L_IMUX46_0", + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_FIFO_L_FAN3_5", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_FIFO_L_LOGIC_OUTS6_0", + "CMT_FIFO_ER1BEG3_9", + "CMT_FIFO_SE2A1_0", + "CMT_FIFO_L_IMUX29_3", + "CMT_FIFO_L_IMUX35_5", + "CMT_FIFO_L_IMUX23_7", + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_FIFO_EE4C2_6", + "CMT_FIFO_EE2A0_5", + "CMT_FIFO_SE4BEG1_11", + "CMT_FIFO_L_LOGIC_OUTS0_6", + "CMT_FIFO_L_IMUX0_2", + "CMT_FIFO_L_IMUX33_3", + "CMT_FIFO_L_IMUX35_10", + "CMT_FIFO_NE2A1_11", + "CMT_FIFO_WL1END1_9", + "CMT_FIFO_WW2END1_6", + "CMT_FIFO_NW4END2_2", + "CMT_FIFO_ER1BEG1_2", + "CMT_FIFO_L_IMUX38_0", + "CMT_FIFO_WW4END1_4", + "CMT_FIFO_L_IMUX44_10", + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_FIFO_L_IMUX41_7", + "CMT_FIFO_WR1END0_3", + "CMT_FIFO_SW4A3_3", + "CMT_FIFO_L_IMUX33_0", + "CMT_FIFO_WW4B0_8", + "CMT_FIFO_L_IMUX28_4", + "CMT_FIFO_L_CTRL1_11", + "CMT_FIFO_L_IMUX46_2", + "CMT_FIFO_EE4C1_5", + "CMT_FIFO_L_IMUX14_5", + "CMT_FIFO_L_BYP4_11", + "CMT_FIFO_NE4BEG0_4", + "CMT_OUT_FIFO_D51", + "CMT_FIFO_L_BYP4_7", + "CMT_FIFO_L_IMUX13_2", + "CMT_IN_FIFO_Q02", + "CMT_FIFO_LH10_7", + "CMT_FIFO_L_IMUX32_9", + "CMT_OUT_FIFO_Q52", + "CMT_FIFO_L_LOGIC_OUTS6_9", + "CMT_FIFO_EE4B0_10", + "CMT_FIFO_L_IMUX15_6", + "CMT_FIFO_L_IMUX17_1", + "CMT_FIFO_NE2A2_1", + "CMT_FIFO_WL1END1_2", + "CMT_FIFO_WR1END0_4", + "CMT_FIFO_WL1END2_8", + "CMT_IN_FIFO_Q57", + "CMT_OUT_FIFO_Q32", + "CMT_FIFO_L_IMUX36_7", + "CMT_FIFO_NW4END3_10", + "CMT_FIFO_SE4BEG3_0", + "CMT_FIFO_SW4END2_10", + "CMT_FIFO_L_IMUX2_1", + "CMT_FIFO_L_IMUX4_7", + "CMT_FIFO_EE2A0_2", + "CMT_FIFO_L_IMUX36_3", + "CMT_FIFO_L_IMUX20_11", + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_FIFO_EE4B0_11", + "CMT_FIFO_NW4END0_3", + "CMT_OUT_FIFO_D91", + "CMT_FIFO_L_IMUX40_1", + "CMT_FIFO_WW4C3_6", + "CMT_FIFO_L_IMUX17_9", + "CMT_FIFO_L_IMUX28_10", + "CMT_FIFO_NW4A2_9", + "CMT_FIFO_NW2A1_2", + "CMT_FIFO_L_IMUX13_5", + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_OUT_FIFO_SCANOUT2", + "CMT_IN_FIFO_RESET", + "CMT_FIFO_EE4BEG3_10", + "CMT_FIFO_L_LOGIC_OUTS15_1", + "CMT_FIFO_L_IMUX37_7", + "CMT_FIFO_LH8_0", + "CMT_FIFO_NE4BEG2_10", + "CMT_FIFO_L_LOGIC_OUTS17_10", + "CMT_FIFO_SE2A3_8", + "CMT_FIFO_WW2END0_9", + "CMT_FIFO_LH5_5", + "CMT_FIFO_L_BYP2_8", + "CMT_FIFO_L_IMUX35_9", + "CMT_FIFO_L_BYP0_0", + "CMT_FIFO_WW2END2_1", + "CMT_FIFO_EE4B0_6", + "CMT_FIFO_MONITOR_P_4", + "CMT_FIFO_EE2A3_8", + "CMT_FIFO_L_FAN1_3", + "CMT_OUT_FIFO_Q41", + "CMT_FIFO_WL1END0_10", + "CMT_FIFO_L_IMUX31_5", + "CMT_FIFO_L_IMUX40_8", + "CMT_FIFO_L_IMUX30_5", + "CMT_FIFO_L_IMUX41_0", + "CMT_IN_FIFO_D51", + "CMT_FIFO_WR1END3_3", + "CMT_FIFO_L_CTRL1_10", + "CMT_FIFO_EE4B2_6", + "CMT_FIFO_SE2A2_9", + "CMT_FIFO_L_LOGIC_OUTS2_11", + "CMT_FIFO_L_FAN2_6", + "CMT_FIFO_L_IMUX26_7", + "CMT_FIFO_L_BYP4_0", + "CMT_FIFO_L_IMUX8_8", + "CMT_IN_FIFO_D54", + "CMT_FIFO_WW4C3_0", + "CMT_FIFO_WW4END0_3", + "CMT_FIFO_L_IMUX11_2", + "CMT_FIFO_EE4A1_0", + "CMT_FIFO_NE4C3_10", + "CMT_FIFO_WW2END3_6", + "CMT_IN_FIFO_Q15", + "CMT_FIFO_WW2END2_8", + "CMT_FIFO_L_IMUX18_6", + "CMT_FIFO_L_FAN0_2", + "CMT_FIFO_LH2_3", + "CMT_FIFO_WW4A1_8", + "CMT_FIFO_LH3_9", + "CMT_FIFO_WW4END1_9", + "CMT_FIFO_SE4C1_2", + "CMT_FIFO_EE4BEG1_10", + "CMT_FIFO_L_IMUX1_5", + "CMT_FIFO_L_CLK0_5", + "CMT_FIFO_WR1END1_8", + "CMT_FIFO_ER1BEG2_8", + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_FIFO_L_BYP4_10", + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_OUT_FIFO_Q60", + "CMT_FIFO_EE4A3_4", + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_FIFO_WR1END2_3", + "CMT_FIFO_WW4C1_7", + "CMT_FIFO_SW4A0_9", + "CMT_FIFO_LH8_3", + "CMT_FIFO_L_IMUX41_1", + "CMT_IN_FIFO_Q86", + "CMT_FIFO_SW2A0_6", + "CMT_FIFO_L_IMUX32_5", + "CMT_FIFO_L_LOGIC_OUTS23_0", + "CMT_IN_FIFO_Q51", + "CMT_IN_FIFO_Q85", + "CMT_FIFO_L_FAN1_7", + "CMT_FIFO_WW2A0_9", + "CMT_FIFO_LH5_10", + "CMT_OUT_FIFO_Q81", + "CMT_FIFO_EL1BEG0_7", + "CMT_FIFO_L_IMUX7_7", + "CMT_FIFO_WW4B2_10", + "CMT_FIFO_MONITOR_N_2", + "CMT_FIFO_EE4A2_5", + "CMT_IN_FIFO_D52", + "CMT_FIFO_WW4A2_7", + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_OUT_FIFO_D72", + "CMT_FIFO_WW2END3_3", + "CMT_FIFO_SW2A2_5", + "CMT_FIFO_L_BYP1_0", + "CMT_FIFO_WW4A0_1", + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_FIFO_NW2A1_8", + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_FIFO_SE2A0_11", + "CMT_FIFO_L_IMUX30_6", + "CMT_FIFO_L_IMUX1_2", + "CMT_OUT_FIFO_Q20", + "CMT_FIFO_L_IMUX34_5", + "CMT_FIFO_L_IMUX19_6", + "CMT_FIFO_L_IMUX23_1", + "CMT_FIFO_L_IMUX23_2", + "CMT_FIFO_SW4A3_10", + "CMT_FIFO_NE4BEG2_1", + "CMT_FIFO_L_IMUX4_6", + "CMT_FIFO_L_IMUX43_4", + "CMT_FIFO_EE2A2_3", + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_FIFO_L_IMUX0_10", + "CMT_FIFO_LH2_8", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_FIFO_EL1BEG1_4", + "CMT_FIFO_L_IMUX12_10", + "CMT_FIFO_EE2A2_2", + "CMT_FIFO_LH11_9", + "CMT_IN_FIFO_SCANOUT2", + "CMT_FIFO_L_IMUX7_5", + "CMT_FIFO_L_IMUX26_2", + "CMT_FIFO_EE2A3_5", + "CMT_FIFO_L_LOGIC_OUTS18_11", + "CMT_FIFO_L_IMUX40_10", + "CMT_FIFO_NW2A2_10", + "CMT_OUT_FIFO_D27", + "CMT_FIFO_ER1BEG2_11", + "CMT_FIFO_L_FAN3_2", + "CMT_FIFO_LH3_11", + "FIFO_DQS_IOTOPHASER_1", + "CMT_FIFO_L_IMUX35_7", + "CMT_OUT_FIFO_Q54", + "CMT_FIFO_WW2END1_7", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_FIFO_WW4C0_2", + "CMT_FIFO_NE4C2_3", + "CMT_FIFO_SW4END2_6", + "CMT_FIFO_L_CTRL1_0", + "CMT_FIFO_L_BYP2_9", + "CMT_FIFO_NW2A2_0", + "CMT_FIFO_L_FAN4_1", + "CMT_FIFO_L_IMUX22_0", + "CMT_FIFO_L_IMUX5_0", + "CMT_IN_FIFO_Q47", + "CMT_FIFO_WR1END0_11", + "CMT_FIFO_L_LOGIC_OUTS16_10", + "CMT_IN_FIFO_WREN", + "CMT_FIFO_ER1BEG2_7", + "CMT_IN_FIFO_Q10", + "CMT_IN_FIFO_Q00", + "CMT_FIFO_WL1END2_6", + "CMT_FIFO_WW4C0_8", + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_FIFO_SE4C0_5", + "CMT_FIFO_L_IMUX22_10", + "CMT_OUT_FIFO_D10", + "CMT_FIFO_EE2A1_4", + "CMT_FIFO_EE2BEG1_10", + "CMT_FIFO_NE4BEG0_9", + "CMT_FIFO_SW4END2_2", + "CMT_FIFO_EE4B1_3", + "CMT_FIFO_L_IMUX31_1", + "CMT_FIFO_WW4END1_6", + "CMT_FIFO_L_FAN4_3", + "CMT_FIFO_L_IMUX16_6", + "CMT_FIFO_SW4END1_2", + "CMT_IN_FIFO_D62", + "CMT_FIFO_SW4END3_0", + "CMT_FIFO_L_IMUX3_1", + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_FIFO_L_IMUX26_1", + "CMT_FIFO_NE4BEG0_11", + "CMT_FIFO_L_FAN7_7", + "CMT_FIFO_MONITOR_N_10", + "CMT_FIFO_LH6_7", + "CMT_FIFO_WW2A2_1", + "CMT_FIFO_NW4A1_3", + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_FIFO_L_BYP4_2", + "CMT_FIFO_EE4A3_10", + "CMT_FIFO_LH12_10", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_IN_FIFO_Q21", + "CMT_FIFO_EE4A2_11", + "CMT_FIFO_NE4BEG2_8", + "CMT_FIFO_NE4BEG0_8", + "CMT_FIFO_EE4BEG1_9", + "CMT_FIFO_L_LOGIC_OUTS7_11", + "CMT_FIFO_L_IMUX44_4", + "CMT_FIFO_L_IMUX28_2", + "CMT_FIFO_L_IMUX29_4", + "CMT_FIFO_EE4A0_1", + "CMT_FIFO_L_CLK1_3", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_5", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_0", + "CMT_FIFO_WW4B0_10", + "CMT_FIFO_L_IMUX9_10", + "CMT_FIFO_EE2BEG3_11", + "CMT_FIFO_SW2A1_11", + "CMT_FIFO_L_IMUX28_6", + "CMT_IN_FIFO_Q25", + "CMT_IN_FIFO_SCANOUT3", + "CMT_FIFO_EE4BEG1_5", + "CMT_FIFO_L_BYP6_0", + "CMT_FIFO_L_IMUX10_1", + "CMT_OUT_FIFO_Q53", + "CMT_FIFO_EE4A2_8", + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_FIFO_WW4A1_0", + "CMT_IN_FIFO_Q90", + "CMT_FIFO_L_IMUX26_11", + "CMT_FIFO_SE2A1_3", + "CMT_FIFO_SE2A3_11", + "CMT_FIFO_WW2A1_10", + "CMT_FIFO_L_LOGIC_OUTS21_1", + "CMT_FIFO_NW4END1_7", + "CMT_FIFO_L_IMUX10_7", + "CMT_FIFO_L_IMUX6_1", + "CMT_FIFO_EE4C3_3", + "CMT_FIFO_SE4BEG1_9", + "CMT_FIFO_L_IMUX22_7", + "CMT_FIFO_L_IMUX26_6", + "CMT_FIFO_WL1END1_1", + "CMT_FIFO_WW4A3_0", + "CMT_FIFO_L_IMUX10_10", + "CMT_FIFO_WW4END1_8", + "CMT_FIFO_EE4BEG0_5", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_9", + "CMT_FIFO_WW4END3_10", + "CMT_FIFO_WW4C3_9", + "CMT_FIFO_L_IMUX6_0", + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_FIFO_EL1BEG1_6", + "CMT_FIFO_L_IMUX13_11", + "CMT_OUT_FIFO_D24", + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_FIFO_L_IMUX8_10", + "CMT_FIFO_L_IMUX31_4", + "CMT_FIFO_L_IMUX46_6", + "CMT_FIFO_EE2BEG2_8", + "CMT_FIFO_SW2A3_1", + "CMT_FIFO_LH6_3", + "CMT_FIFO_SW2A2_7", + "CMT_FIFO_L_IMUX5_4", + "CMT_IN_FIFO_D70", + "CMT_FIFO_L_IMUX46_4", + "CMT_FIFO_L_CTRL0_4", + "CMT_FIFO_LH3_4", + "CMT_FIFO_L_IMUX6_11", + "CMT_OUT_FIFO_D75", + "CMT_FIFO_NE2A2_0", + "CMT_FIFO_ER1BEG0_1", + "CMT_OUT_FIFO_D20", + "CMT_FIFO_WW4C2_10", + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_IN_FIFO_Q87", + "CMT_FIFO_L_IMUX30_8", + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_FIFO_L_IMUX22_2", + "CMT_FIFO_L_IMUX31_0", + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_FIFO_L_IMUX11_1", + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_OUT_FIFO_Q55", + "CMT_FIFO_SE4C1_10", + "CMT_FIFO_WW4END1_11", + "CMT_FIFO_SW2A1_9", + "CMT_FIFO_WW4A2_10", + "CMT_FIFO_EE2BEG1_5", + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_FIFO_L_IMUX18_0", + "CMT_FIFO_SW4A0_1", + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_FIFO_L_IMUX18_9", + "CMT_FIFO_NW4A3_11", + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_FIFO_L_IMUX26_0", + "CMT_FIFO_WW4END2_7", + "CMT_FIFO_LH1_3", + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_FIFO_EE4B3_4", + "CMT_FIFO_L_FAN6_4", + "CMT_FIFO_L_BYP2_10", + "CMT_FIFO_L_BYP0_1", + "CMT_OUT_FIFO_D35", + "CMT_OUT_FIFO_Q66", + "CMT_FIFO_WW4C1_3", + "CMT_FIFO_NW4END3_8", + "CMT_FIFO_L_IMUX32_2", + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_FIFO_L_IMUX16_11", + "CMT_FIFO_ER1BEG0_11", + "CMT_FIFO_L_IMUX31_2", + "CMT_FIFO_L_IMUX16_1", + "CMT_FIFO_WW4B1_10", + "CMT_FIFO_L_CLK0_4", + "CMT_FIFO_EE4A0_8", + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_FIFO_EE4C1_3", + "CMT_FIFO_L_FAN6_1", + "CMT_FIFO_EL1BEG0_0", + "CMT_FIFO_WW4A2_6", + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_FIFO_L_IMUX44_3", + "CMT_IN_FIFO_D63", + "CMT_FIFO_LH1_2", + "CMT_FIFO_EE4A0_2", + "CMT_FIFO_L_IMUX21_10", + "CMT_FIFO_WR1END2_7", + "CMT_FIFO_L_IMUX38_3", + "CMT_OUT_FIFO_D83", + "CMT_FIFO_L_IMUX13_8", + "CMT_FIFO_EE4A3_3", + "CMT_FIFO_WW4B3_10", + "CMT_FIFO_EE4B2_11", + "CMT_FIFO_NE4C1_7", + "CMT_IN_FIFO_Q42", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_FIFO_L_IMUX9_5", + "CMT_IN_FIFO_ALMOSTEMPTY", + "CMT_FIFO_L_IMUX18_4", + "CMT_FIFO_SE4C0_10", + "CMT_FIFO_NE2A0_8", + "CMT_FIFO_SE2A2_10", + "CMT_FIFO_SW4A1_1", + "CMT_FIFO_L_FAN4_6", + "CMT_FIFO_L_LOGIC_OUTS6_4", + "CMT_FIFO_EE4C0_8", + "CMT_FIFO_EE4B0_3", + "CMT_FIFO_L_IMUX20_7", + "CMT_FIFO_NE2A1_2", + "CMT_FIFO_SW4A0_8", + "CMT_IN_FIFO_D73", + "CMT_FIFO_WW2A0_6", + "CMT_IN_FIFO_Q80", + "CMT_FIFO_LH2_10", + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_FIFO_L_IMUX43_5", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_FIFO_LH12_0", + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_FIFO_SW4A2_5", + "CMT_FIFO_WR1END2_2", + "CMT_FIFO_SE4C1_11", + "CMT_FIFO_L_IMUX25_10", + "CMT_FIFO_L_IMUX11_3", + "CMT_OUT_FIFO_D42", + "CMT_FIFO_NW4A0_8", + "CMT_FIFO_L_FAN7_1", + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_FIFO_EE2BEG0_10", + "CMT_FIFO_EE4B1_6", + "CMT_FIFO_NW2A1_4", + "CMT_FIFO_EL1BEG3_8", + "CMT_FIFO_SW4A1_11", + "CMT_FIFO_SE4C2_8", + "CMT_IN_FIFO_D66", + "CMT_FIFO_NE4C1_9", + "CMT_FIFO_NW4A1_2", + "CMT_FIFO_L_LOGIC_OUTS16_4", + "CMT_FIFO_L_IMUX7_3", + "CMT_OUT_FIFO_D61", + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_FIFO_L_BYP5_9", + "CMT_FIFO_NE2A0_9", + "CMT_IN_FIFO_Q50", + "CMT_FIFO_LH11_1", + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_OUT_FIFO_D70", + "CMT_FIFO_WR1END1_11", + "CMT_FIFO_NW4END3_11", + "CMT_FIFO_L_IMUX37_8", + "CMT_FIFO_L_CTRL1_1", + "CMT_FIFO_NE4BEG3_1", + "CMT_FIFO_L_IMUX32_4", + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_FIFO_L_IMUX39_5", + "CMT_FIFO_NE4BEG3_5", + "CMT_FIFO_L_IMUX36_6", + "CMT_OUT_FIFO_D87" + ], + "tile_type": "CMT_FIFO_L", + "sites": [ + { + "site_pins": { + "D85": "CMT_OUT_FIFO_D85", + "RESET": "CMT_OUT_FIFO_RESET", + "D52": "CMT_OUT_FIFO_D52", + "Q21": "CMT_OUT_FIFO_Q21", + "D07": "CMT_OUT_FIFO_D07", + "D24": "CMT_OUT_FIFO_D24", + "D97": "CMT_OUT_FIFO_D97", + "D47": "CMT_OUT_FIFO_D47", + "D76": "CMT_OUT_FIFO_D76", + "D94": "CMT_OUT_FIFO_D94", + "EMPTY": "CMT_OUT_FIFO_EMPTY", + "D75": "CMT_OUT_FIFO_D75", + "D66": "CMT_OUT_FIFO_D66", + "SCANIN2": "CMT_OUT_FIFO_SCANIN2", + "D30": "CMT_OUT_FIFO_D30", + "D35": "CMT_OUT_FIFO_D35", + "D53": "CMT_OUT_FIFO_D53", + "SCANOUT2": "CMT_OUT_FIFO_SCANOUT2", + "D54": "CMT_OUT_FIFO_D54", + "Q50": "CMT_OUT_FIFO_Q50", + "D42": "CMT_OUT_FIFO_D42", + "Q54": "CMT_OUT_FIFO_Q54", + "Q81": "CMT_OUT_FIFO_Q81", + "Q40": "CMT_OUT_FIFO_Q40", + "Q72": "CMT_OUT_FIFO_Q72", + "D82": "CMT_OUT_FIFO_D82", + "D43": "CMT_OUT_FIFO_D43", + "Q66": "CMT_OUT_FIFO_Q66", + "Q22": "CMT_OUT_FIFO_Q22", + "Q91": "CMT_OUT_FIFO_Q91", + "Q56": "CMT_OUT_FIFO_Q56", + "D13": "CMT_OUT_FIFO_D13", + "D45": "CMT_OUT_FIFO_D45", + "D51": "CMT_OUT_FIFO_D51", + "Q90": "CMT_OUT_FIFO_Q90", + "D01": "CMT_OUT_FIFO_D01", + "D41": "CMT_OUT_FIFO_D41", + "FULL": "CMT_OUT_FIFO_FULL", + "D32": "CMT_OUT_FIFO_D32", + "D46": "CMT_OUT_FIFO_D46", + "D71": "CMT_OUT_FIFO_D71", + "D34": "CMT_OUT_FIFO_D34", + "SCANIN0": "CMT_OUT_FIFO_SCANIN0", + "D65": "CMT_OUT_FIFO_D65", + "D96": "CMT_OUT_FIFO_D96", + "WREN": "CMT_OUT_FIFO_WREN", + "Q60": "CMT_OUT_FIFO_Q60", + "Q03": "CMT_OUT_FIFO_Q03", + "D37": "CMT_OUT_FIFO_D37", + "Q61": "CMT_OUT_FIFO_Q61", + "Q41": "CMT_OUT_FIFO_Q41", + "Q20": "CMT_OUT_FIFO_Q20", + "Q30": "CMT_OUT_FIFO_Q30", + "D61": "CMT_OUT_FIFO_D61", + "Q12": "CMT_OUT_FIFO_Q12", + "D44": "CMT_OUT_FIFO_D44", + "Q00": "CMT_OUT_FIFO_Q00", + "D63": "CMT_OUT_FIFO_D63", + "Q92": "CMT_OUT_FIFO_Q92", + "D20": "CMT_OUT_FIFO_D20", + "SCANOUT3": "CMT_OUT_FIFO_SCANOUT3", + "D93": "CMT_OUT_FIFO_D93", + "D31": "CMT_OUT_FIFO_D31", + "D06": "CMT_OUT_FIFO_D06", + "TESTWRITEDISB": "CMT_OUT_FIFO_TESTWRITEDISB", + "D95": "CMT_OUT_FIFO_D95", + "D84": "CMT_OUT_FIFO_D84", + "Q82": "CMT_OUT_FIFO_Q82", + "Q67": "CMT_OUT_FIFO_Q67", + "Q93": "CMT_OUT_FIFO_Q93", + "D73": "CMT_OUT_FIFO_D73", + "D10": "CMT_OUT_FIFO_D10", + "D72": "CMT_OUT_FIFO_D72", + "D62": "CMT_OUT_FIFO_D62", + "D81": "CMT_OUT_FIFO_D81", + "Q51": "CMT_OUT_FIFO_Q51", + "D12": "CMT_OUT_FIFO_D12", + "RDCLK": "CMT_OUT_FIFO_RDCLK", + "D05": "CMT_OUT_FIFO_D05", + "WRCLK": "CMT_OUT_FIFO_WRCLK", + "D87": "CMT_OUT_FIFO_D87", + "D16": "CMT_OUT_FIFO_D16", + "D21": "CMT_OUT_FIFO_D21", + "D23": "CMT_OUT_FIFO_D23", + "Q02": "CMT_OUT_FIFO_Q02", + "D83": "CMT_OUT_FIFO_D83", + "Q80": "CMT_OUT_FIFO_Q80", + "D00": "CMT_OUT_FIFO_D00", + "Q57": "CMT_OUT_FIFO_Q57", + "D40": "CMT_OUT_FIFO_D40", + "SCANIN3": "CMT_OUT_FIFO_SCANIN3", + "D91": "CMT_OUT_FIFO_D91", + "D74": "CMT_OUT_FIFO_D74", + "SCANOUT1": "CMT_OUT_FIFO_SCANOUT1", + "Q52": "CMT_OUT_FIFO_Q52", + "Q70": "CMT_OUT_FIFO_Q70", + "D70": "CMT_OUT_FIFO_D70", + "Q63": "CMT_OUT_FIFO_Q63", + "D57": "CMT_OUT_FIFO_D57", + "ALMOSTFULL": "CMT_OUT_FIFO_ALMOSTFULL", + "D22": "CMT_OUT_FIFO_D22", + "D25": "CMT_OUT_FIFO_D25", + "Q11": "CMT_OUT_FIFO_Q11", + "D36": "CMT_OUT_FIFO_D36", + "ALMOSTEMPTY": "CMT_OUT_FIFO_ALMOSTEMPTY", + "RDEN": "CMT_OUT_FIFO_RDEN", + "SCANENB": "CMT_OUT_FIFO_SCANENB", + "Q31": "CMT_OUT_FIFO_Q31", + "Q62": "CMT_OUT_FIFO_Q62", + "D11": "CMT_OUT_FIFO_D11", + "Q23": "CMT_OUT_FIFO_Q23", + "Q13": "CMT_OUT_FIFO_Q13", + "D14": "CMT_OUT_FIFO_D14", + "D56": "CMT_OUT_FIFO_D56", + "D92": "CMT_OUT_FIFO_D92", + "D17": "CMT_OUT_FIFO_D17", + "TESTMODEB": "CMT_OUT_FIFO_TESTMODEB", + "Q73": "CMT_OUT_FIFO_Q73", + "Q33": "CMT_OUT_FIFO_Q33", + "Q10": "CMT_OUT_FIFO_Q10", + "D50": "CMT_OUT_FIFO_D50", + "D90": "CMT_OUT_FIFO_D90", + "Q71": "CMT_OUT_FIFO_Q71", + "Q64": "CMT_OUT_FIFO_Q64", + "D03": "CMT_OUT_FIFO_D03", + "SCANIN1": "CMT_OUT_FIFO_SCANIN1", + "Q53": "CMT_OUT_FIFO_Q53", + "D02": "CMT_OUT_FIFO_D02", + "D27": "CMT_OUT_FIFO_D27", + "Q65": "CMT_OUT_FIFO_Q65", + "D15": "CMT_OUT_FIFO_D15", + "D55": "CMT_OUT_FIFO_D55", + "D33": "CMT_OUT_FIFO_D33", + "D26": "CMT_OUT_FIFO_D26", + "Q42": "CMT_OUT_FIFO_Q42", + "Q32": "CMT_OUT_FIFO_Q32", + "SCANOUT0": "CMT_OUT_FIFO_SCANOUT0", + "D04": "CMT_OUT_FIFO_D04", + "D67": "CMT_OUT_FIFO_D67", + "Q43": "CMT_OUT_FIFO_Q43", + "Q01": "CMT_OUT_FIFO_Q01", + "Q55": "CMT_OUT_FIFO_Q55", + "D77": "CMT_OUT_FIFO_D77", + "D64": "CMT_OUT_FIFO_D64", + "TESTREADDISB": "CMT_OUT_FIFO_TESTREADDISB", + "D60": "CMT_OUT_FIFO_D60", + "D80": "CMT_OUT_FIFO_D80", + "Q83": "CMT_OUT_FIFO_Q83", + "D86": "CMT_OUT_FIFO_D86" + }, + "type": "OUT_FIFO", + "prefix": "OUT_FIFO", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "Q74": "CMT_IN_FIFO_Q74", + "RESET": "CMT_IN_FIFO_RESET", + "D52": "CMT_IN_FIFO_D52", + "Q21": "CMT_IN_FIFO_Q21", + "Q36": "CMT_IN_FIFO_Q36", + "Q16": "CMT_IN_FIFO_Q16", + "Q34": "CMT_IN_FIFO_Q34", + "Q67": "CMT_IN_FIFO_Q67", + "EMPTY": "CMT_IN_FIFO_EMPTY", + "D66": "CMT_IN_FIFO_D66", + "SCANIN2": "CMT_IN_FIFO_SCANIN2", + "Q04": "CMT_IN_FIFO_Q04", + "D53": "CMT_IN_FIFO_D53", + "SCANOUT2": "CMT_IN_FIFO_SCANOUT2", + "Q43": "CMT_IN_FIFO_Q43", + "Q50": "CMT_IN_FIFO_Q50", + "D42": "CMT_IN_FIFO_D42", + "Q01": "CMT_IN_FIFO_Q01", + "Q54": "CMT_IN_FIFO_Q54", + "Q81": "CMT_IN_FIFO_Q81", + "Q40": "CMT_IN_FIFO_Q40", + "Q72": "CMT_IN_FIFO_Q72", + "D82": "CMT_IN_FIFO_D82", + "Q06": "CMT_IN_FIFO_Q06", + "Q66": "CMT_IN_FIFO_Q66", + "Q22": "CMT_IN_FIFO_Q22", + "Q91": "CMT_IN_FIFO_Q91", + "Q56": "CMT_IN_FIFO_Q56", + "D13": "CMT_IN_FIFO_D13", + "Q93": "CMT_IN_FIFO_Q93", + "D51": "CMT_IN_FIFO_D51", + "Q90": "CMT_IN_FIFO_Q90", + "D01": "CMT_IN_FIFO_D01", + "D41": "CMT_IN_FIFO_D41", + "FULL": "CMT_IN_FIFO_FULL", + "D32": "CMT_IN_FIFO_D32", + "Q37": "CMT_IN_FIFO_Q37", + "Q75": "CMT_IN_FIFO_Q75", + "Q76": "CMT_IN_FIFO_Q76", + "D71": "CMT_IN_FIFO_D71", + "Q85": "CMT_IN_FIFO_Q85", + "D73": "CMT_IN_FIFO_D73", + "D65": "CMT_IN_FIFO_D65", + "WREN": "CMT_IN_FIFO_WREN", + "Q60": "CMT_IN_FIFO_Q60", + "Q03": "CMT_IN_FIFO_Q03", + "Q77": "CMT_IN_FIFO_Q77", + "Q61": "CMT_IN_FIFO_Q61", + "Q41": "CMT_IN_FIFO_Q41", + "Q20": "CMT_IN_FIFO_Q20", + "Q17": "CMT_IN_FIFO_Q17", + "D61": "CMT_IN_FIFO_D61", + "Q12": "CMT_IN_FIFO_Q12", + "D54": "CMT_IN_FIFO_D54", + "Q00": "CMT_IN_FIFO_Q00", + "D63": "CMT_IN_FIFO_D63", + "Q44": "CMT_IN_FIFO_Q44", + "Q92": "CMT_IN_FIFO_Q92", + "D20": "CMT_IN_FIFO_D20", + "Q86": "CMT_IN_FIFO_Q86", + "SCANOUT3": "CMT_IN_FIFO_SCANOUT3", + "D93": "CMT_IN_FIFO_D93", + "D31": "CMT_IN_FIFO_D31", + "Q87": "CMT_IN_FIFO_Q87", + "D67": "CMT_IN_FIFO_D67", + "Q82": "CMT_IN_FIFO_Q82", + "D50": "CMT_IN_FIFO_D50", + "Q14": "CMT_IN_FIFO_Q14", + "D10": "CMT_IN_FIFO_D10", + "D72": "CMT_IN_FIFO_D72", + "D62": "CMT_IN_FIFO_D62", + "D81": "CMT_IN_FIFO_D81", + "Q51": "CMT_IN_FIFO_Q51", + "D12": "CMT_IN_FIFO_D12", + "RDCLK": "CMT_IN_FIFO_RDCLK", + "Q94": "CMT_IN_FIFO_Q94", + "Q30": "CMT_IN_FIFO_Q30", + "WRCLK": "CMT_IN_FIFO_WRCLK", + "D21": "CMT_IN_FIFO_D21", + "D23": "CMT_IN_FIFO_D23", + "Q02": "CMT_IN_FIFO_Q02", + "D83": "CMT_IN_FIFO_D83", + "Q80": "CMT_IN_FIFO_Q80", + "Q46": "CMT_IN_FIFO_Q46", + "D00": "CMT_IN_FIFO_D00", + "Q24": "CMT_IN_FIFO_Q24", + "Q57": "CMT_IN_FIFO_Q57", + "D40": "CMT_IN_FIFO_D40", + "SCANIN3": "CMT_IN_FIFO_SCANIN3", + "D91": "CMT_IN_FIFO_D91", + "D30": "CMT_IN_FIFO_D30", + "Q52": "CMT_IN_FIFO_Q52", + "Q26": "CMT_IN_FIFO_Q26", + "Q70": "CMT_IN_FIFO_Q70", + "D70": "CMT_IN_FIFO_D70", + "TESTWRITEDISB": "CMT_IN_FIFO_TESTWRITEDISB", + "Q63": "CMT_IN_FIFO_Q63", + "D57": "CMT_IN_FIFO_D57", + "ALMOSTFULL": "CMT_IN_FIFO_ALMOSTFULL", + "D22": "CMT_IN_FIFO_D22", + "Q47": "CMT_IN_FIFO_Q47", + "Q07": "CMT_IN_FIFO_Q07", + "Q11": "CMT_IN_FIFO_Q11", + "ALMOSTEMPTY": "CMT_IN_FIFO_ALMOSTEMPTY", + "RDEN": "CMT_IN_FIFO_RDEN", + "SCANENB": "CMT_IN_FIFO_SCANENB", + "Q31": "CMT_IN_FIFO_Q31", + "Q62": "CMT_IN_FIFO_Q62", + "Q15": "CMT_IN_FIFO_Q15", + "D11": "CMT_IN_FIFO_D11", + "Q23": "CMT_IN_FIFO_Q23", + "Q13": "CMT_IN_FIFO_Q13", + "Q25": "CMT_IN_FIFO_Q25", + "Q33": "CMT_IN_FIFO_Q33", + "D56": "CMT_IN_FIFO_D56", + "D92": "CMT_IN_FIFO_D92", + "TESTMODEB": "CMT_IN_FIFO_TESTMODEB", + "Q73": "CMT_IN_FIFO_Q73", + "Q45": "CMT_IN_FIFO_Q45", + "Q10": "CMT_IN_FIFO_Q10", + "D02": "CMT_IN_FIFO_D02", + "Q71": "CMT_IN_FIFO_Q71", + "Q64": "CMT_IN_FIFO_Q64", + "D03": "CMT_IN_FIFO_D03", + "SCANIN1": "CMT_IN_FIFO_SCANIN1", + "Q27": "CMT_IN_FIFO_Q27", + "Q53": "CMT_IN_FIFO_Q53", + "Q35": "CMT_IN_FIFO_Q35", + "D90": "CMT_IN_FIFO_D90", + "Q97": "CMT_IN_FIFO_Q97", + "Q65": "CMT_IN_FIFO_Q65", + "D55": "CMT_IN_FIFO_D55", + "D33": "CMT_IN_FIFO_D33", + "Q95": "CMT_IN_FIFO_Q95", + "Q42": "CMT_IN_FIFO_Q42", + "Q32": "CMT_IN_FIFO_Q32", + "SCANOUT0": "CMT_IN_FIFO_SCANOUT0", + "Q05": "CMT_IN_FIFO_Q05", + "SCANOUT1": "CMT_IN_FIFO_SCANOUT1", + "D43": "CMT_IN_FIFO_D43", + "Q55": "CMT_IN_FIFO_Q55", + "D64": "CMT_IN_FIFO_D64", + "TESTREADDISB": "CMT_IN_FIFO_TESTREADDISB", + "D60": "CMT_IN_FIFO_D60", + "D80": "CMT_IN_FIFO_D80", + "Q96": "CMT_IN_FIFO_Q96", + "SCANIN0": "CMT_IN_FIFO_SCANIN0", + "Q84": "CMT_IN_FIFO_Q84", + "Q83": "CMT_IN_FIFO_Q83" + }, + "type": "IN_FIFO", + "prefix": "IN_FIFO", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_FIFO_R.json b/artix7/tile_type_CMT_FIFO_R.json index 45ff596..855e547 100644 --- a/artix7/tile_type_CMT_FIFO_R.json +++ b/artix7/tile_type_CMT_FIFO_R.json @@ -1,5261 +1,5261 @@ { - "wires": [ - "CMT_FIFO_WW2A1_11", - "CMT_FIFO_MONITOR_N_9", - "CMT_FIFO_L_CTRL0_5", - "CMT_FIFO_EE4B1_2", - "CMT_FIFO_L_IMUX38_7", - "CMT_FIFO_EE2A0_10", - "CMT_FIFO_L_IMUX17_5", - "CMT_FIFO_NW2A3_0", - "CMT_FIFO_WW4B0_5", - "CMT_FIFO_SW4A3_4", - "CMT_OUT_FIFO_Q22", - "CMT_FIFO_WR1END1_9", - "CMT_FIFO_WR1END1_0", - "CMT_FIFO_L_IMUX47_10", - "CMT_FIFO_L_IMUX40_9", - "CMT_FIFO_WR1END2_4", - "CMT_FIFO_NE2A0_10", - "CMT_OUT_FIFO_D51", - "CMT_FIFO_SW4END1_11", - "CMT_FIFO_L_IMUX11_0", - "CMT_FIFO_EE4B1_11", - "CMT_FIFO_L_IMUX25_0", - "CMT_FIFO_WW4END3_6", - "CMT_OUT_FIFO_TESTWRITEDISB", - "CMT_FIFO_L_LOGIC_OUTS18_5", - "CMT_FIFO_EE2BEG2_11", - "CMT_FIFO_SE2A3_0", - "CMT_FIFO_LH7_3", - "CMT_FIFO_WW4C2_0", - "CMT_FIFO_NE4C3_5", - "CMT_FIFO_SW2A2_8", - "CMT_FIFO_L_BYP1_3", - "CMT_FIFO_L_IMUX13_2", - "CMT_FIFO_L_CLK0_1", - "CMT_FIFO_LH7_8", - "CMT_FIFO_WW2END2_1", - "CMT_FIFO_L_IMUX0_4", - "CMT_FIFO_EE2BEG0_3", - "CMT_FIFO_EE4BEG2_7", - "CMT_FIFO_NW4A0_11", - "CMT_FIFO_SE4C0_1", - "CMT_FIFO_EE4BEG0_10", - "CMT_FIFO_EE4A2_2", - "CMT_FIFO_WW4C2_11", - "CMT_FIFO_L_IMUX4_7", - "CMT_FIFO_NW4END0_7", - "CMT_FIFO_L_LOGIC_OUTS18_0", - "CMT_FIFO_NW4END0_8", - "CMT_FIFO_L_IMUX22_5", - "CMT_OUT_FIFO_D63", - "CMT_FIFO_L_IMUX30_2", - "CMT_FIFO_EE4B0_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_9", - "CMT_FIFO_L_IMUX14_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", - "CMT_FIFO_LH3_8", - "CMT_FIFO_SW4END2_6", - "CMT_FIFO_L_LOGIC_OUTS22_7", - "CMT_FIFO_L_LOGIC_OUTS16_2", - "CMT_FIFO_EE4C0_9", - "CMT_FIFO_L_IMUX39_5", - "CMT_FIFO_L_LOGIC_OUTS14_3", - "CMT_FIFO_L_IMUX2_7", - "CMT_FIFO_L_CLK1_3", - "CMT_IN_FIFO_Q61", - "CMT_FIFO_L_LOGIC_OUTS19_2", - "CMT_FIFO_L_BYP6_5", - "CMT_FIFO_L_IMUX37_0", - "CMT_FIFO_EE2BEG2_3", - "CMT_FIFO_L_FAN0_10", - "CMT_FIFO_L_IMUX38_2", - "CMT_OUT_FIFO_D03", - "CMT_FIFO_L_IMUX37_11", - "CMT_FIFO_L_LOGIC_OUTS3_5", - "CMT_FIFO_EE4B1_9", - "CMT_FIFO_EE4C0_5", - "CMT_FIFO_WW4B2_0", - "CMT_FIFO_L_IMUX21_1", - "CMT_FIFO_SE2A3_6", - "CMT_FIFO_NW4END3_1", - "CMT_FIFO_LH7_2", - "CMT_FIFO_NE4BEG3_2", - "CMT_FIFO_L_IMUX34_4", - "CMT_FIFO_L_IMUX10_1", - "CMT_FIFO_L_LOGIC_OUTS12_7", - "CMT_FIFO_L_IMUX40_7", - "CMT_FIFO_EE2BEG2_4", - "CMT_FIFO_EE4B1_6", - "CMT_FIFO_L_LOGIC_OUTS11_5", - "CMT_OUT_FIFO_Q71", - "CMT_FIFO_NW2A2_3", - "CMT_FIFO_L_IMUX2_3", - "CMT_FIFO_NE4C2_5", - "CMT_FIFO_L_IMUX47_7", - "CMT_FIFO_EE4BEG0_4", - "CMT_FIFO_SE2A1_2", - "CMT_FIFO_L_BYP0_8", - "CMT_FIFO_EE2A0_8", - "CMT_FIFO_NE4C0_3", - "CMT_FIFO_NW4END2_0", - "CMT_FIFO_LH10_2", - "CMT_FIFO_EE4BEG3_4", - "CMT_FIFO_EE4A0_10", - "CMT_OUT_FIFO_SCANIN0", - "CMT_FIFO_NE4C2_2", - "CMT_FIFO_L_CLK0_6", - "CMT_FIFO_WW2END0_5", - "CMT_FIFO_L_IMUX18_3", - "CMT_FIFO_L_FAN7_7", - "CMT_FIFO_L_LOGIC_OUTS16_0", - "CMT_FIFO_EL1BEG3_10", - "CMT_IN_FIFO_Q66", - "CMT_FIFO_L_IMUX42_1", - "CMT_FIFO_WL1END3_2", - "CMT_FIFO_SW4A2_10", - "CMT_FIFO_EE2BEG2_2", - "CMT_OUT_FIFO_D65", - "CMT_FIFO_L_IMUX22_7", - "CMT_FIFO_ER1BEG1_2", - "CMT_FIFO_EE4C3_6", - "CMT_FIFO_LH1_7", - "CMT_FIFO_L_IMUX3_4", - "CMT_FIFO_L_LOGIC_OUTS13_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_5", - "CMT_FIFO_WR1END1_8", - "CMT_FIFO_ER1BEG1_0", - "CMT_FIFO_L_IMUX41_1", - "CMT_FIFO_EE2A0_7", - "CMT_FIFO_SE4C0_0", - "CMT_FIFO_L_IMUX21_4", - "CMT_FIFO_L_BYP4_2", - "CMT_FIFO_LH11_10", - "CMT_FIFO_WR1END0_3", - "CMT_FIFO_L_IMUX12_2", - "CMT_FIFO_LH12_4", - "CMT_FIFO_WR1END1_10", - "CMT_FIFO_SE4C1_2", - "CMT_FIFO_EE4B2_0", - "CMT_FIFO_NE2A2_5", - "CMT_FIFO_WW4A0_2", - "CMT_FIFO_L_IMUX14_3", - "CMT_FIFO_NE4C2_10", - "CMT_FIFO_L_LOGIC_OUTS18_11", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", - "CMT_FIFO_SW4A1_5", - "CMT_OUT_FIFO_Q72", - "CMT_FIFO_WL1END1_8", - "CMT_FIFO_LH2_0", - "CMT_FIFO_L_IMUX46_5", - "CMT_FIFO_SE4C2_4", - "CMT_FIFO_L_IMUX12_5", - "CMT_FIFO_L_BYP6_6", - "CMT_FIFO_L_IMUX19_9", - "CMT_FIFO_WR1END3_3", - "CMT_IN_FIFO_D12", - "CMT_FIFO_EE4BEG3_10", - "CMT_FIFO_SE2A0_9", - "CMT_FIFO_SE4C1_6", - "CMT_FIFO_EE4BEG2_4", - "CMT_OUT_FIFO_ALMOSTEMPTY", - "CMT_FIFO_WW4C1_2", - "CMT_FIFO_WW4C1_8", - "CMT_FIFO_WL1END0_2", - "CMT_FIFO_EE4B3_4", - "CMT_FIFO_L_LOGIC_OUTS5_2", - "CMT_IN_FIFO_Q41", - "CMT_FIFO_SW4A2_4", - "CMT_IN_FIFO_Q53", - "CMT_FIFO_EE4C0_11", - "CMT_OUT_FIFO_Q51", - "CMT_FIFO_L_BYP6_11", - "CMT_FIFO_WW4A1_9", - "CMT_FIFO_WW4END1_8", - "CMT_FIFO_SE2A0_7", - "CMT_FIFO_L_LOGIC_OUTS2_7", - "CMT_FIFO_L_CLK0_11", - "CMT_FIFO_NW4END2_6", - "CMT_FIFO_SW2A0_7", - "CMT_FIFO_L_LOGIC_OUTS23_2", - "CMT_FIFO_L_LOGIC_OUTS23_11", - "CMT_FIFO_L_LOGIC_OUTS23_10", - "CMT_FIFO_LH12_8", - "CMT_OUT_FIFO_RDCLK", - "CMT_FIFO_EL1BEG2_3", - "CMT_FIFO_SE2A2_8", - "CMT_FIFO_L_FAN5_8", - "CMT_FIFO_WW4A2_8", - "CMT_FIFO_L_IMUX38_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", - "CMT_FIFO_L_IMUX29_11", - "CMT_FIFO_SW2A2_9", - "CMT_FIFO_NE4C3_6", - "CMT_FIFO_EE4BEG0_0", - "CMT_FIFO_L_IMUX42_3", - "CMT_FIFO_SW4A1_11", - "CMT_FIFO_NW2A0_3", - "CMT_FIFO_LH11_7", - "CMT_FIFO_NW4A2_6", - "CMT_FIFO_WW2END2_11", - "CMT_FIFO_L_IMUX44_3", - "CMT_FIFO_LH9_11", - "CMT_FIFO_WW2END3_2", - "CMT_OUT_FIFO_Q82", - "CMT_FIFO_LH10_8", - "CMT_FIFO_L_FAN4_7", - "CMT_FIFO_L_BYP2_9", - "CMT_FIFO_L_LOGIC_OUTS17_0", - "CMT_FIFO_LH4_0", - "CMT_FIFO_MONITOR_P_1", - "CMT_FIFO_SE4C2_8", - "CMT_FIFO_L_IMUX42_9", - "CMT_FIFO_SE4C0_4", - "CMT_FIFO_MONITOR_N_8", - "CMT_FIFO_WW4C0_4", - "CMT_FIFO_NW2A2_7", - "CMT_OUT_FIFO_D87", - "CMT_FIFO_NW2A0_5", - "CMT_FIFO_SW2A2_7", - "CMT_FIFO_EE4C3_9", - "CMT_FIFO_LH9_6", - "CMT_FIFO_L_LOGIC_OUTS21_1", - "CMT_FIFO_EE4C3_4", - "CMT_FIFO_SE4C0_7", - "CMT_FIFO_NW4A0_8", - "CMT_FIFO_L_CTRL1_3", - "CMT_FIFO_L_IMUX20_7", - "CMT_FIFO_L_LOGIC_OUTS19_8", - "CMT_FIFO_WR1END2_10", - "CMT_FIFO_NE2A0_8", - "CMT_FIFO_LH5_7", - "CMT_FIFO_L_FAN0_2", - "CMT_OUT_FIFO_D15", - "FIFO_DQS_IOTOPHASER_1", - "CMT_FIFO_EE4C1_3", - "CMT_FIFO_EE2BEG3_7", - "CMT_FIFO_SE2A0_11", - "CMT_FIFO_WW4END3_11", - "CMT_FIFO_SE4C3_0", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", - "CMT_IN_FIFO_Q90", - "CMT_FIFO_SE4BEG2_6", - "CMT_OUT_FIFO_D21", - "CMT_IN_FIFO_Q42", - "CMT_FIFO_L_IMUX25_5", - "CMT_FIFO_L_IMUX23_8", - "CMT_FIFO_L_IMUX5_9", - "CMT_FIFO_L_LOGIC_OUTS11_0", - "CMT_FIFO_SE4C1_10", - "CMT_FIFO_WW4END2_11", - "CMT_FIFO_L_LOGIC_OUTS7_0", - "CMT_FIFO_L_IMUX30_4", - "CMT_FIFO_EE4A3_3", - "CMT_FIFO_WW4A1_2", - "CMT_FIFO_WL1END3_6", - "CMT_FIFO_L_IMUX47_3", - "CMT_FIFO_EE4C1_9", - "CMT_FIFO_L_FAN6_5", - "CMT_FIFO_SE2A3_2", - "CMT_FIFO_L_BYP2_0", - "CMT_FIFO_L_BYP1_5", - "CMT_FIFO_LH7_10", - "CMT_FIFO_NE2A1_1", - "CMT_FIFO_WW2A0_2", - "CMT_FIFO_L_LOGIC_OUTS19_0", - "CMT_FIFO_NE2A1_3", - "CMT_FIFO_WW4END2_4", - "CMT_FIFO_WW4B3_1", - "CMT_FIFO_WW4END2_3", - "CMT_FIFO_WW4B2_7", - "CMT_FIFO_LH12_6", - "CMT_FIFO_EE4A1_3", - "CMT_FIFO_SW4END0_10", - "CMT_FIFO_SW2A0_10", - "CMT_FIFO_L_LOGIC_OUTS1_10", - "CMT_FIFO_L_CLK1_1", - "CMT_FIFO_L_FAN4_1", - "CMT_FIFO_L_FAN5_9", - "CMT_FIFO_EE4A0_4", - "CMT_FIFO_NE4C1_1", - "CMT_IN_FIFO_D03", - "CMT_FIFO_NE2A1_10", - "CMT_FIFO_L_LOGIC_OUTS1_5", - "CMT_FIFO_SE4BEG2_9", - "CMT_FIFO_EE4BEG2_2", - "CMT_IN_FIFO_Q80", - "CMT_FIFO_EL1BEG3_1", - "CMT_FIFO_NE4C3_4", - "CMT_FIFO_L_LOGIC_OUTS6_6", - "CMT_FIFO_NE4BEG2_7", - "CMT_FIFO_L_IMUX15_1", - "CMT_FIFO_WW2A1_10", - "CMT_FIFO_L_LOGIC_OUTS3_6", - "CMT_FIFO_SW2A2_2", - "CMT_FIFO_LH8_11", - "CMT_FIFO_L_BYP3_4", - "CMT_FIFO_WW2END1_10", - "CMT_FIFO_MONITOR_N_0", - "CMT_FIFO_L_IMUX41_3", - "CMT_OUT_FIFO_D70", - "CMT_FIFO_EE4A2_3", - "CMT_FIFO_WW2END2_10", - "CMT_IN_FIFO_Q15", - "CMT_FIFO_EE4A0_8", - "CMT_FIFO_WW4END1_3", - "CMT_FIFO_EE2BEG2_7", - "CMT_FIFO_L_BYP2_8", - "CMT_FIFO_L_IMUX12_11", - "CMT_FIFO_L_LOGIC_OUTS3_0", - "CMT_FIFO_L_LOGIC_OUTS18_2", - "CMT_FIFO_WW4END1_2", - "CMT_FIFO_L_BYP0_0", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", - "CMT_FIFO_L_IMUX23_6", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", - "CMT_FIFO_WW2A3_1", - "CMT_FIFO_L_IMUX14_4", - "CMT_FIFO_SW2A1_8", - "CMT_IN_FIFO_Q45", - "CMT_FIFO_SW2A0_11", - "CMT_FIFO_NW2A2_4", - "CMT_FIFO_NE4C2_8", - "CMT_FIFO_WW4B2_6", - "CMT_FIFO_EE2A1_7", - "CMT_FIFO_EE4BEG0_8", - "CMT_FIFO_L_IMUX19_2", - "CMT_FIFO_LH7_11", - "CMT_FIFO_L_LOGIC_OUTS9_7", - "CMT_FIFO_WW4C3_11", - "CMT_FIFO_LH7_1", - "CMT_FIFO_WW4B0_8", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", - "CMT_FIFO_L_IMUX21_3", - "CMT_FIFO_WW4A3_9", - "CMT_FIFO_L_IMUX11_8", - "FIFO_DQS_IOTOPHASER_2", - "CMT_FIFO_EE2A0_1", - "CMT_FIFO_WW4B2_1", - "CMT_FIFO_EE4B0_5", - "CMT_FIFO_ER1BEG3_8", - "CMT_FIFO_L_IMUX13_1", - "CMT_FIFO_WL1END2_6", - "CMT_FIFO_LH3_0", - "CMT_OUT_FIFO_D05", - "CMT_FIFO_L_LOGIC_OUTS6_7", - "CMT_FIFO_L_LOGIC_OUTS13_10", - "CMT_FIFO_WW2END0_6", - "CMT_FIFO_L_IMUX1_0", - "CMT_FIFO_SE2A2_3", - "CMT_IN_FIFO_Q62", - "CMT_FIFO_ER1BEG3_6", - "CMT_FIFO_L_IMUX28_10", - "CMT_FIFO_NW4A3_0", - "CMT_FIFO_L_LOGIC_OUTS18_3", - "CMT_FIFO_LH8_4", - "CMT_FIFO_WW4A3_6", - "CMT_FIFO_L_IMUX1_4", - "CMT_FIFO_L_IMUX19_10", - "CMT_FIFO_L_IMUX5_10", - "CMT_FIFO_L_FAN0_1", - "CMT_FIFO_NE2A2_8", - "CMT_FIFO_L_CTRL0_10", - "CMT_FIFO_L_LOGIC_OUTS9_9", - "CMT_OUT_FIFO_D01", - "CMT_FIFO_L_CTRL1_2", - "CMT_FIFO_NE2A3_0", - "CMT_FIFO_NE2A3_9", - "CMT_FIFO_L_IMUX11_1", - "CMT_FIFO_L_IMUX10_2", - "CMT_FIFO_L_LOGIC_OUTS13_1", - "CMT_FIFO_LH2_6", - "CMT_IN_FIFO_D02", - "CMT_FIFO_EE2BEG2_5", - "CMT_FIFO_EL1BEG0_4", - "CMT_FIFO_SE4BEG2_0", - "CMT_FIFO_WW2END1_9", - "CMT_FIFO_L_LOGIC_OUTS11_7", - "CMT_FIFO_WW2A3_11", - "CMT_FIFO_L_BYP3_11", - "CMT_FIFO_WW2END1_6", - "CMT_FIFO_WW2A1_3", - "CMT_FIFO_L_IMUX17_2", - "CMT_OUT_FIFO_SCANOUT1", - "CMT_FIFO_L_IMUX26_6", - "CMT_FIFO_WW2A3_0", - "CMT_OUT_FIFO_D84", - "CMT_FIFO_L_LOGIC_OUTS2_11", - "CMT_FIFO_L_IMUX7_8", - "CMT_FIFO_L_LOGIC_OUTS4_8", - "CMT_FIFO_L_BYP4_3", - "CMT_FIFO_L_IMUX29_3", - "CMT_FIFO_EE2A2_6", - "CMT_FIFO_SW4END2_7", - "CMT_FIFO_L_CLK0_9", - "CMT_OUT_FIFO_RESET", - "CMT_FIFO_WW4C3_10", - "CMT_FIFO_NW2A1_11", - "CMT_FIFO_PHASER_TO_IO_ICLK_7", - "CMT_FIFO_L_FAN1_6", - "CMT_FIFO_L_IMUX35_2", - "CMT_FIFO_L_IMUX25_2", - "CMT_FIFO_WR1END3_6", - "CMT_FIFO_NW4END2_11", - "CMT_FIFO_NE2A1_2", - "CMT_OUT_FIFO_D83", - "CMT_FIFO_L_LOGIC_OUTS7_6", - "CMT_FIFO_L_CTRL1_7", - "CMT_IN_FIFO_TESTWRITEDISB", - "CMT_FIFO_SE4BEG2_10", - "CMT_FIFO_WW2END1_0", - "CMT_FIFO_LH8_8", - "CMT_FIFO_L_IMUX35_9", - "CMT_FIFO_NW4END0_4", - "CMT_OUT_FIFO_Q00", - "CMT_FIFO_L_IMUX25_10", - "CMT_FIFO_SE4BEG1_9", - "CMT_FIFO_LH9_7", - "CMT_FIFO_WW4A2_9", - "CMT_FIFO_WW4END3_8", - "CMT_FIFO_WW4C3_7", - "CMT_OUT_FIFO_Q64", - "CMT_FIFO_L_IMUX22_11", - "CMT_FIFO_SE4BEG3_1", - "CMT_FIFO_WL1END1_1", - "CMT_FIFO_EL1BEG3_7", - "CMT_FIFO_EE2BEG2_8", - "CMT_OUT_FIFO_D47", - "CMT_FIFO_SE4BEG2_2", - "CMT_FIFO_EE2A0_3", - "CMT_FIFO_L_IMUX26_1", - "CMT_FIFO_L_LOGIC_OUTS7_2", - "CMT_FIFO_L_BYP4_11", - "CMT_FIFO_WW2END1_7", - "CMT_FIFO_L_IMUX3_3", - "CMT_FIFO_SW4A3_2", - "CMT_FIFO_SW4END0_3", - "CMT_FIFO_L_LOGIC_OUTS5_4", - "CMT_FIFO_L_IMUX40_8", - "CMT_FIFO_L_LOGIC_OUTS2_0", - "CMT_FIFO_NE4BEG3_11", - "CMT_FIFO_L_IMUX9_3", - "CMT_FIFO_NE4BEG0_0", - "CMT_FIFO_EE4A1_0", - "CMT_IN_FIFO_Q04", - "CMT_FIFO_WW4A3_10", - "CMT_IN_FIFO_Q17", - "CMT_FIFO_L_LOGIC_OUTS4_2", - "CMT_FIFO_SE2A1_7", - "CMT_FIFO_WW2END0_2", - "CMT_OUT_FIFO_D23", - "CMT_FIFO_L_FAN2_2", - "CMT_FIFO_EE2A2_9", - "CMT_FIFO_L_IMUX9_2", - "CMT_FIFO_WR1END2_3", - "CMT_FIFO_WW4B3_11", - "CMT_FIFO_L_IMUX2_11", - "CMT_IN_FIFO_Q52", - "CMT_FIFO_SE4BEG1_10", - "CMT_FIFO_EL1BEG1_5", - "CMT_FIFO_L_LOGIC_OUTS9_0", - "CMT_FIFO_WR1END2_11", - "CMT_OUT_FIFO_D33", - "CMT_OUT_FIFO_D07", - "CMT_FIFO_SW2A1_9", - "CMT_FIFO_WW4END1_1", - "CMT_FIFO_WW4A1_3", - "CMT_FIFO_EE4C0_1", - "CMT_FIFO_EE4B0_10", - "CMT_OUT_FIFO_Q70", - "CMT_FIFO_L_FAN2_9", - "CMT_FIFO_WW4C1_1", - "CMT_FIFO_L_IMUX17_11", - "CMT_FIFO_L_IMUX25_9", - "CMT_FIFO_SW4END0_9", - "CMT_FIFO_L_CTRL0_9", - "CMT_FIFO_EL1BEG1_2", - "CMT_OUT_FIFO_Q33", - "CMT_FIFO_L_IMUX3_9", - "CMT_FIFO_L_LOGIC_OUTS12_6", - "CMT_FIFO_L_LOGIC_OUTS0_4", - "CMT_FIFO_NE4C1_3", - "CMT_OUT_FIFO_SCANOUT2", - "CMT_FIFO_SE2A2_4", - "CMT_FIFO_L_LOGIC_OUTS13_11", - "CMT_FIFO_WW4END1_4", - "CMT_FIFO_SE2A2_7", - "CMT_IN_FIFO_Q82", - "CMT_FIFO_L_IMUX23_2", - "CMT_FIFO_EE4C1_10", - "CMT_IN_FIFO_D73", - "CMT_FIFO_L_LOGIC_OUTS9_2", - "CMT_IN_FIFO_Q81", - "CMT_FIFO_LH2_1", - "CMT_FIFO_L_IMUX1_6", - "CMT_FIFO_SE2A2_1", - "CMT_FIFO_NE4BEG2_1", - "CMT_FIFO_WR1END0_0", - "CMT_FIFO_L_IMUX18_11", - "CMT_FIFO_EE4B3_7", - "CMT_FIFO_WW2END1_11", - "CMT_FIFO_NW4A3_1", - "CMT_FIFO_L_IMUX0_5", - "CMT_FIFO_NE4BEG3_8", - "CMT_FIFO_L_BYP5_11", - "CMT_FIFO_EE2A1_10", - "CMT_FIFO_NW2A0_2", - "CMT_FIFO_NE4BEG0_1", - "CMT_FIFO_L_IMUX37_3", - "CMT_IN_FIFO_Q54", - "CMT_FIFO_LH12_10", - "CMT_FIFO_NE4BEG2_9", - "CMT_FIFO_L_IMUX36_5", - "CMT_FIFO_EE2A1_8", - "CMT_FIFO_L_LOGIC_OUTS0_1", - "CMT_FIFO_L_IMUX7_0", - "CMT_FIFO_ER1BEG2_0", - "CMT_FIFO_SW4END3_11", - "CMT_FIFO_EE4B3_2", - "CMT_FIFO_L_LOGIC_OUTS12_0", - "CMT_OUT_FIFO_Q43", - "CMT_FIFO_SE2A3_5", - "CMT_OUT_FIFO_Q31", - "CMT_FIFO_NE2A0_2", - "CMT_FIFO_WW4B1_8", - "CMT_FIFO_WR1END0_4", - "CMT_FIFO_ER1BEG1_11", - "CMT_FIFO_L_FAN7_8", - "CMT_FIFO_NW4A2_2", - "CMT_OUT_FIFO_Q67", - "CMT_FIFO_SE4BEG0_7", - "CMT_FIFO_L_BYP0_3", - "CMT_FIFO_EE4C1_11", - "CMT_OUT_FIFO_Q42", - "CMT_FIFO_L_BYP5_8", - "CMT_FIFO_WL1END0_6", - "CMT_FIFO_EE4A1_2", - "CMT_FIFO_L_IMUX36_11", - "CMT_FIFO_LH2_9", - "CMT_FIFO_EE4B2_8", - "CMT_FIFO_NW4A0_5", - "CMT_FIFO_L_LOGIC_OUTS16_11", - "CMT_FIFO_EE4BEG1_11", - "CMT_FIFO_L_LOGIC_OUTS17_6", - "CMT_FIFO_ER1BEG3_10", - "CMT_FIFO_L_LOGIC_OUTS15_7", - "CMT_OUT_FIFO_D30", - "CMT_FIFO_SW4END1_3", - "CMT_FIFO_EE4BEG1_7", - "CMT_OUT_FIFO_D90", - "CMT_FIFO_L_IMUX30_1", - "CMT_FIFO_EE2A1_0", - "CMT_FIFO_ER1BEG2_10", - "CMT_FIFO_WW2END1_2", - "CMT_FIFO_L_LOGIC_OUTS14_8", - "CMT_FIFO_L_IMUX47_0", - "CMT_FIFO_L_BYP6_10", - "CMT_FIFO_EE4B1_0", - "CMT_FIFO_L_LOGIC_OUTS17_5", - "CMT_FIFO_EE2A2_11", - "CMT_FIFO_NE4BEG1_7", - "CMT_OUT_FIFO_Q02", - "CMT_FIFO_WW2END2_2", - "CMT_IN_FIFO_Q87", - "CMT_FIFO_WW4A2_10", - "CMT_FIFO_LH4_6", - "CMT_OUT_FIFO_D36", - "CMT_FIFO_WW4END0_1", - "CMT_FIFO_WL1END1_5", - "CMT_FIFO_SE4C2_10", - "CMT_FIFO_SW2A1_11", - "CMT_FIFO_L_FAN3_10", - "CMT_FIFO_SW4A2_7", - "CMT_FIFO_L_IMUX1_5", - "CMT_IN_FIFO_Q06", - "CMT_FIFO_WW4A3_3", - "CMT_FIFO_L_IMUX30_7", - "CMT_IN_FIFO_Q21", - "CMT_FIFO_WW4C0_10", - "CMT_FIFO_L_PHASER_RDENABLE", - "FIFO_DQS_IOTOPHASER_11", - "CMT_FIFO_EE4A2_10", - "CMT_FIFO_NW2A2_1", - "CMT_FIFO_EE2BEG1_0", - "CMT_FIFO_SW4A1_0", - "CMT_OUT_FIFO_D74", - "CMT_FIFO_L_BYP4_4", - "CMT_FIFO_L_FAN2_1", - "CMT_FIFO_L_IMUX41_8", - "CMT_FIFO_EE4B3_1", - "CMT_FIFO_L_LOGIC_OUTS12_3", - "CMT_FIFO_L_FAN5_11", - "CMT_IN_FIFO_Q67", - "CMT_FIFO_EL1BEG1_0", - "CMT_FIFO_NW4END3_5", - "CMT_FIFO_LH11_2", - "CMT_FIFO_SE4C2_3", - "CMT_FIFO_LH3_9", - "CMT_FIFO_LH6_2", - "CMT_FIFO_EL1BEG3_6", - "CMT_FIFO_SW4END1_5", - "CMT_FIFO_L_LOGIC_OUTS20_0", - "CMT_OUT_FIFO_D41", - "CMT_FIFO_WW2A3_6", - "CMT_FIFO_L_IMUX7_11", - "CMT_FIFO_EE4C1_8", - "CMT_FIFO_L_LOGIC_OUTS1_6", - "CMT_FIFO_L_LOGIC_OUTS15_5", - "CMT_FIFO_LH6_7", - "CMT_FIFO_L_IMUX28_3", - "CMT_FIFO_L_IMUX33_1", - "CMT_FIFO_WL1END3_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_3", - "CMT_FIFO_NE4C0_11", - "CMT_FIFO_SE4C0_6", - "CMT_FIFO_MONITOR_P_7", - "CMT_FIFO_ER1BEG3_2", - "CMT_FIFO_SE2A0_4", - "CMT_FIFO_L_IMUX3_11", - "CMT_FIFO_L_LOGIC_OUTS6_2", - "CMT_FIFO_SW2A2_11", - "CMT_FIFO_WW4END0_2", - "CMT_FIFO_ER1BEG2_6", - "CMT_FIFO_SW4END3_1", - "CMT_FIFO_L_LOGIC_OUTS12_1", - "CMT_FIFO_NW2A3_9", - "CMT_FIFO_L_IMUX24_0", - "CMT_IN_FIFO_D13", - "CMT_FIFO_L_IMUX34_3", - "CMT_FIFO_WR1END0_6", - "CMT_FIFO_L_LOGIC_OUTS14_4", - "CMT_FIFO_NW2A2_2", - "CMT_FIFO_EL1BEG0_1", - "CMT_FIFO_L_IMUX6_5", - "CMT_FIFO_ER1BEG0_7", - "CMT_FIFO_EE4C0_0", - "CMT_FIFO_L_IMUX32_2", - "CMT_FIFO_EE4C0_6", - "CMT_FIFO_L_BYP5_5", - "CMT_FIFO_EE4BEG2_5", - "CMT_FIFO_L_CTRL0_11", - "CMT_FIFO_NE4BEG1_9", - "CMT_FIFO_L_IMUX27_2", - "CMT_FIFO_LH11_11", - "CMT_FIFO_L_FAN2_3", - "CMT_FIFO_NW4A3_9", - "CMT_FIFO_LH4_5", - "CMT_IN_FIFO_Q10", - "CMT_IN_FIFO_D50", - "CMT_FIFO_L_LOGIC_OUTS23_3", - "CMT_FIFO_L_IMUX34_9", - "CMT_IN_FIFO_SCANOUT2", - "CMT_FIFO_WW4B0_3", - "CMT_FIFO_L_LOGIC_OUTS9_5", - "CMT_IN_FIFO_Q64", - "CMT_FIFO_NE2A3_5", - "CMT_FIFO_WW4END2_2", - "CMT_FIFO_PHASER_TO_IO_ICLK_4", - "CMT_FIFO_SW4A3_1", - "CMT_FIFO_NE4C2_1", - "CMT_FIFO_EE4BEG3_6", - "CMT_FIFO_L_IMUX8_4", - "CMT_FIFO_L_IMUX1_2", - "CMT_FIFO_L_IMUX26_0", - "CMT_FIFO_PHASER_TO_IO_ICLK_9", - "CMT_FIFO_ER1BEG1_5", - "CMT_FIFO_L_IMUX32_3", - "CMT_FIFO_SW4A2_8", - "CMT_FIFO_LH2_11", - "CMT_FIFO_L_LOGIC_OUTS0_9", - "CMT_FIFO_L_LOGIC_OUTS14_5", - "CMT_IN_FIFO_ALMOSTEMPTY", - "CMT_FIFO_EE4B3_3", - "CMT_FIFO_SW4END0_1", - "CMT_FIFO_LH6_9", - "CMT_FIFO_L_LOGIC_OUTS7_11", - "CMT_IN_FIFO_Q07", - "CMT_FIFO_NW2A1_2", - "CMT_FIFO_L_IMUX1_10", - "CMT_OUT_FIFO_Q23", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", - "CMT_FIFO_L_FAN6_10", - "CMT_FIFO_LH1_4", - "CMT_FIFO_L_IMUX21_0", - "CMT_FIFO_L_IMUX30_3", - "CMT_FIFO_L_LOGIC_OUTS20_4", - "CMT_FIFO_L_LOGIC_OUTS2_1", - "CMT_FIFO_NW4A1_7", - "CMT_OUT_FIFO_D82", - "CMT_FIFO_L_LOGIC_OUTS4_10", - "CMT_FIFO_WW4C3_3", - "CMT_FIFO_L_IMUX46_3", - "CMT_FIFO_L_LOGIC_OUTS9_1", - "CMT_FIFO_L_IMUX17_8", - "CMT_FIFO_SE4BEG2_8", - "CMT_FIFO_L_IMUX43_1", - "CMT_FIFO_L_FAN2_8", - "CMT_FIFO_WL1END1_9", - "CMT_FIFO_EE2BEG1_11", - "CMT_FIFO_NW4A0_3", - "CMT_FIFO_L_IMUX36_7", - "CMT_FIFO_ER1BEG2_3", - "CMT_FIFO_NE4C3_10", - "CMT_FIFO_L_LOGIC_OUTS23_7", - "CMT_FIFO_SW4END1_4", - "CMT_FIFO_EE2A2_10", - "CMT_FIFO_EL1BEG3_9", - "CMT_FIFO_SE4BEG1_11", - "CMT_FIFO_EE4B3_8", - "CMT_FIFO_L_LOGIC_OUTS22_2", - "CMT_FIFO_L_IMUX5_0", - "CMT_FIFO_WW2A1_9", - "CMT_FIFO_EE2A0_4", - "CMT_FIFO_SW2A3_7", - "CMT_FIFO_EE2BEG3_11", - "CMT_FIFO_L_LOGIC_OUTS20_1", - "CMT_FIFO_LH1_1", - "CMT_FIFO_L_IMUX5_7", - "CMT_FIFO_L_FAN4_2", - "CMT_FIFO_L_BYP3_7", - "CMT_FIFO_SE4BEG0_4", - "CMT_FIFO_EE2BEG3_8", - "CMT_FIFO_L_IMUX33_8", - "CMT_FIFO_L_FAN4_0", - "CMT_FIFO_L_IMUX22_4", - "CMT_FIFO_L_IMUX2_10", - "CMT_IN_FIFO_Q00", - "CMT_FIFO_EL1BEG0_10", - "CMT_FIFO_L_LOGIC_OUTS1_3", - "CMT_FIFO_L_IMUX7_4", - "CMT_FIFO_L_LOGIC_OUTS2_5", - "CMT_FIFO_ER1BEG1_8", - "CMT_FIFO_L_CTRL1_6", - "CMT_FIFO_L_CLK0_7", - "CMT_FIFO_SE4C2_9", - "CMT_FIFO_EE4BEG1_4", - "CMT_FIFO_NW4END3_3", - "CMT_FIFO_MONITOR_P_2", - "CMT_FIFO_SW4END2_10", - "CMT_FIFO_L_FAN1_8", - "CMT_FIFO_SW2A1_3", - "CMT_IN_FIFO_Q30", - "CMT_FIFO_L_CTRL1_5", - "CMT_FIFO_EE4C0_3", - "CMT_IN_FIFO_Q36", - "CMT_FIFO_NW4END1_6", - "CMT_FIFO_SW4END3_9", - "CMT_FIFO_SW4END1_7", - "CMT_FIFO_L_BYP0_1", - "CMT_FIFO_L_LOGIC_OUTS18_8", - "CMT_FIFO_LH9_0", - "CMT_FIFO_NE2A2_9", - "CMT_FIFO_SW4A2_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", - "CMT_FIFO_L_IMUX31_9", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", - "CMT_FIFO_WW4END3_0", - "CMT_FIFO_NE2A1_6", - "CMT_FIFO_L_IMUX3_10", - "CMT_FIFO_L_IMUX32_6", - "CMT_FIFO_L_BYP4_10", - "CMT_OUT_FIFO_SCANIN1", - "CMT_OUT_FIFO_Q81", - "CMT_FIFO_L_IMUX43_0", - "CMT_FIFO_NE2A1_5", - "CMT_FIFO_L_LOGIC_OUTS5_9", - "CMT_FIFO_NE2A1_9", - "CMT_FIFO_WW4C2_1", - "CMT_FIFO_SW4END1_9", - "CMT_FIFO_L_IMUX19_3", - "CMT_FIFO_EE4C1_1", - "CMT_FIFO_L_IMUX4_0", - "CMT_FIFO_L_IMUX37_6", - "CMT_FIFO_LH2_7", - "CMT_FIFO_L_IMUX11_5", - "CMT_FIFO_L_LOGIC_OUTS22_11", - "CMT_FIFO_NE2A2_1", - "CMT_FIFO_ER1BEG3_7", - "CMT_FIFO_EE4C3_1", - "CMT_FIFO_SW4END0_7", - "CMT_FIFO_NE2A0_4", - "CMT_OUT_FIFO_D56", - "CMT_FIFO_EE4C3_7", - "CMT_FIFO_WL1END3_7", - "CMT_FIFO_NE4C3_2", - "CMT_FIFO_L_IMUX32_5", - "CMT_FIFO_L_IMUX0_8", - "CMT_FIFO_EE4A2_1", - "CMT_FIFO_L_IMUX45_9", - "CMT_FIFO_WW4C2_2", - "CMT_FIFO_WL1END0_3", - "CMT_FIFO_SW4A1_8", - "CMT_FIFO_L_IMUX23_11", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", - "CMT_FIFO_SW2A1_10", - "CMT_FIFO_SE4C1_9", - "CMT_FIFO_SE4C2_1", - "CMT_FIFO_WR1END3_10", - "CMT_FIFO_SW4A0_6", - "CMT_IN_FIFO_TESTREADDISB", - "CMT_FIFO_L_IMUX22_2", - "CMT_FIFO_L_FAN2_4", - "CMT_FIFO_NE4BEG1_11", - "CMT_FIFO_ER1BEG0_1", - "CMT_FIFO_EE4BEG3_3", - "CMT_FIFO_L_IMUX37_5", - "CMT_OUT_FIFO_D06", - "CMT_FIFO_NW4END1_8", - "CMT_FIFO_WR1END1_2", - "CMT_FIFO_L_BYP0_11", - "CMT_FIFO_NW4END1_5", - "CMT_FIFO_WW2END2_7", - "CMT_FIFO_L_IMUX9_11", - "FIFO_DQS_IOTOPHASER_44", - "CMT_FIFO_WW4B1_0", - "CMT_FIFO_L_IMUX39_4", - "CMT_FIFO_L_LOGIC_OUTS15_6", - "CMT_FIFO_L_LOGIC_OUTS9_11", - "CMT_FIFO_ER1BEG1_1", - "CMT_FIFO_NW4END0_1", - "CMT_FIFO_EE4A1_9", - "CMT_FIFO_L_IMUX43_10", - "CMT_FIFO_L_IMUX7_6", - "CMT_FIFO_L_IMUX11_9", - "CMT_IN_FIFO_SCANIN1", - "CMT_FIFO_L_LOGIC_OUTS14_10", - "CMT_FIFO_L_IMUX39_9", - "CMT_FIFO_WW4C3_8", - "CMT_FIFO_SW4A1_10", - "CMT_FIFO_L_CLK0_3", - "CMT_FIFO_L_PHASER_RDCLK", - "CMT_FIFO_L_IMUX24_3", - "CMT_FIFO_L_FAN2_7", - "CMT_IN_FIFO_Q63", - "CMT_FIFO_L_IMUX23_7", - "CMT_OUT_FIFO_D43", - "CMT_FIFO_L_BYP6_0", - "CMT_FIFO_EE2A1_5", - "CMT_FIFO_WW2END2_8", - "CMT_FIFO_L_IMUX2_9", - "CMT_FIFO_EE2A3_2", - "CMT_FIFO_LH5_0", - "CMT_FIFO_L_LOGIC_OUTS5_7", - "CMT_OUT_FIFO_D86", - "CMT_FIFO_L_IMUX20_3", - "CMT_FIFO_L_IMUX29_6", - "CMT_OUT_FIFO_D53", - "CMT_FIFO_L_FAN6_2", - "CMT_FIFO_WW4C2_9", - "CMT_FIFO_WR1END1_5", - "CMT_FIFO_L_IMUX17_3", - "CMT_FIFO_L_BYP3_5", - "CMT_FIFO_L_LOGIC_OUTS0_3", - "CMT_IN_FIFO_D22", - "CMT_FIFO_WW4END2_6", - "CMT_FIFO_L_IMUX10_11", - "CMT_FIFO_EE4C2_3", - "CMT_FIFO_L_IMUX16_1", - "CMT_FIFO_L_IMUX42_11", - "CMT_OUT_FIFO_D55", - "CMT_FIFO_WW2END3_0", - "CMT_FIFO_MONITOR_N_1", - "CMT_FIFO_L_IMUX9_8", - "CMT_FIFO_NE4BEG1_1", - "CMT_FIFO_WW2END2_4", - "CMT_FIFO_SW4A0_4", - "CMT_FIFO_EE4C2_2", - "CMT_FIFO_NE4C1_6", - "CMT_FIFO_MONITOR_P_9", - "CMT_FIFO_L_IMUX34_5", - "CMT_FIFO_WW4A0_5", - "CMT_FIFO_L_CTRL1_8", - "CMT_FIFO_NW4A1_6", - "CMT_FIFO_L_IMUX15_4", - "CMT_FIFO_NE2A0_11", - "CMT_FIFO_NW4END0_10", - "CMT_FIFO_SE4C3_2", - "CMT_FIFO_L_LOGIC_OUTS1_11", - "CMT_FIFO_EE2A0_5", - "CMT_FIFO_L_IMUX24_8", - "CMT_FIFO_LH4_10", - "CMT_FIFO_L_IMUX16_8", - "CMT_FIFO_L_IMUX10_4", - "CMT_OUT_FIFO_D40", - "CMT_FIFO_WW4C1_10", - "CMT_FIFO_L_IMUX40_4", - "CMT_FIFO_EL1BEG3_11", - "CMT_FIFO_L_LOGIC_OUTS8_8", - "CMT_FIFO_L_LOGIC_OUTS18_6", - "CMT_FIFO_NW2A1_4", - "CMT_FIFO_EE4C0_8", - "CMT_FIFO_L_BYP0_6", - "CMT_FIFO_L_IMUX17_9", - "CMT_IN_FIFO_D00", - "CMT_FIFO_EL1BEG2_11", - "CMT_FIFO_NW2A3_6", - "CMT_FIFO_L_BYP5_7", - "CMT_FIFO_L_IMUX3_1", - "CMT_FIFO_L_IMUX22_9", - "CMT_FIFO_L_LOGIC_OUTS3_9", - "CMT_FIFO_L_LOGIC_OUTS18_9", - "CMT_FIFO_NW4END2_5", - "CMT_FIFO_LH8_1", - "CMT_IN_FIFO_Q25", - "CMT_FIFO_L_BYP3_8", - "CMT_FIFO_L_LOGIC_OUTS3_2", - "CMT_FIFO_EL1BEG2_7", - "CMT_FIFO_L_LOGIC_OUTS8_0", - "CMT_FIFO_L_IMUX0_11", - "CMT_IN_FIFO_Q96", - "CMT_FIFO_NW4END2_7", - "CMT_FIFO_L_LOGIC_OUTS6_3", - "CMT_OUT_FIFO_D25", - "CMT_FIFO_SE4C1_11", - "CMT_FIFO_LH10_11", - "CMT_FIFO_L_LOGIC_OUTS3_11", - "CMT_FIFO_EL1BEG0_3", - "CMT_FIFO_L_FAN6_6", - "CMT_FIFO_L_LOGIC_OUTS5_3", - "CMT_FIFO_LH5_9", - "CMT_OUT_FIFO_D45", - "CMT_IN_FIFO_Q12", - "CMT_FIFO_WW2END2_0", - "CMT_FIFO_L_LOGIC_OUTS11_3", - "CMT_FIFO_L_IMUX38_11", - "CMT_FIFO_SW4END2_2", - "CMT_FIFO_WW2END3_6", - "CMT_FIFO_ER1BEG2_4", - "CMT_FIFO_NW4END3_10", - "CMT_FIFO_L_IMUX32_7", - "CMT_FIFO_EE4B2_10", - "CMT_FIFO_NE4BEG2_3", - "CMT_FIFO_L_LOGIC_OUTS10_5", - "CMT_FIFO_L_IMUX8_7", - "CMT_FIFO_L_IMUX11_7", - "CMT_FIFO_L_IMUX14_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_0", - "CMT_FIFO_SE2A1_4", - "CMT_FIFO_NE4BEG1_2", - "CMT_IN_FIFO_D80", - "CMT_FIFO_NW4END2_3", - "CMT_FIFO_L_CLK0_0", - "CMT_IN_FIFO_D43", - "CMT_FIFO_WW4C1_3", - "CMT_FIFO_WW4A1_10", - "CMT_FIFO_LH12_9", - "CMT_OUT_FIFO_Q54", - "CMT_FIFO_LH6_11", - "CMT_FIFO_WW2END0_4", - "CMT_FIFO_WW2END2_3", - "CMT_FIFO_L_BYP7_10", - "CMT_FIFO_L_CLK1_10", - "CMT_FIFO_L_BYP1_8", - "CMT_FIFO_L_IMUX30_10", - "CMT_FIFO_ER1BEG0_11", - "CMT_FIFO_NW4END1_1", - "CMT_FIFO_L_LOGIC_OUTS10_11", - "CMT_OUT_FIFO_D16", - "CMT_FIFO_WL1END2_0", - "CMT_FIFO_EL1BEG1_7", - "CMT_FIFO_L_LOGIC_OUTS8_5", - "CMT_FIFO_NE2A2_3", - "CMT_OUT_FIFO_Q55", - "CMT_OUT_FIFO_D20", - "CMT_FIFO_SE2A0_5", - "CMT_FIFO_LH12_1", - "CMT_FIFO_L_LOGIC_OUTS11_2", - "CMT_FIFO_WW2END3_11", - "CMT_FIFO_SE2A1_0", - "CMT_OUT_FIFO_Q03", - "CMT_FIFO_SW4END1_0", - "CMT_FIFO_L_FAN0_9", - "CMT_FIFO_L_LOGIC_OUTS8_7", - "CMT_FIFO_L_FAN5_10", - "CMT_IN_FIFO_D11", - "CMT_FIFO_EE4A1_4", - "CMT_FIFO_EE2BEG2_6", - "CMT_FIFO_NW2A2_10", - "CMT_FIFO_EE4A2_11", - "CMT_FIFO_L_IMUX8_0", - "CMT_FIFO_NE4BEG3_5", - "CMT_FIFO_SE4C0_10", - "CMT_FIFO_WW4A3_0", - "CMT_FIFO_NW4END2_9", - "CMT_FIFO_L_LOGIC_OUTS13_8", - "CMT_FIFO_WW2A3_10", - "CMT_IN_FIFO_D52", - "CMT_FIFO_WR1END2_9", - "CMT_FIFO_L_IMUX13_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", - "CMT_FIFO_L_IMUX30_9", - "CMT_FIFO_L_IMUX21_6", - "CMT_FIFO_L_IMUX44_11", - "CMT_FIFO_EE4C2_5", - "CMT_FIFO_NE2A2_10", - "CMT_FIFO_L_FAN5_6", - "CMT_FIFO_L_LOGIC_OUTS2_10", - "CMT_IN_FIFO_Q13", - "CMT_FIFO_L_IMUX13_0", - "CMT_FIFO_EE2A3_1", - "CMT_FIFO_SE4BEG1_2", - "CMT_FIFO_LH9_8", - "CMT_FIFO_NE4C3_3", - "CMT_FIFO_L_LOGIC_OUTS8_2", - "CMT_OUT_FIFO_D76", - "CMT_FIFO_WW4B2_5", - "CMT_FIFO_L_FAN7_10", - "CMT_FIFO_L_LOGIC_OUTS21_8", - "CMT_FIFO_LH2_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", - "CMT_FIFO_WW4A2_3", - "CMT_IN_FIFO_Q93", - "CMT_FIFO_SE4C3_4", - "CMT_FIFO_L_IMUX32_1", - "CMT_FIFO_L_LOGIC_OUTS10_1", - "CMT_FIFO_L_LOGIC_OUTS10_3", - "CMT_FIFO_EE4C3_11", - "CMT_FIFO_L_IMUX15_3", - "CMT_FIFO_L_IMUX43_9", - "CMT_FIFO_SE2A0_2", - "CMT_FIFO_NE4BEG0_8", - "CMT_FIFO_L_LOGIC_OUTS11_1", - "CMT_FIFO_WW2A2_6", - "CMT_FIFO_L_IMUX33_11", - "CMT_FIFO_L_IMUX32_11", - "CMT_OUT_FIFO_D67", - "CMT_FIFO_L_IMUX20_11", - "CMT_FIFO_L_BYP5_4", - "CMT_FIFO_L_IMUX44_6", - "CMT_FIFO_L_IMUX42_10", - "CMT_FIFO_LH3_1", - "CMT_FIFO_EL1BEG1_8", - "CMT_OUT_FIFO_D34", - "CMT_FIFO_L_IMUX18_6", - "CMT_FIFO_L_IMUX47_9", - "CMT_FIFO_SE2A1_1", - "CMT_FIFO_WW4END2_8", - "CMT_FIFO_L_IMUX11_2", - "CMT_FIFO_MONITOR_N_3", - "CMT_FIFO_L_IMUX41_10", - "CMT_FIFO_NW4END3_8", - "CMT_FIFO_SE4C0_2", - "CMT_FIFO_L_IMUX42_8", - "CMT_FIFO_L_IMUX4_5", - "CMT_FIFO_L_FAN1_1", - "CMT_FIFO_WW4C1_7", - "CMT_IN_FIFO_Q60", - "CMT_FIFO_L_BYP1_10", - "CMT_FIFO_EE4A2_8", - "CMT_FIFO_EE4BEG2_8", - "CMT_IN_FIFO_D42", - "CMT_OUT_FIFO_Q10", - "CMT_FIFO_NE2A2_7", - "CMT_FIFO_L_IMUX45_6", - "CMT_IN_FIFO_D61", - "CMT_FIFO_L_FAN6_1", - "CMT_FIFO_L_IMUX20_4", - "CMT_FIFO_EE4C2_0", - "CMT_FIFO_EL1BEG2_4", - "CMT_IN_FIFO_SCANOUT1", - "CMT_FIFO_NW4A2_5", - "CMT_FIFO_ER1BEG0_4", - "CMT_FIFO_NW4A0_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", - "CMT_FIFO_EE2BEG1_4", - "CMT_FIFO_L_CLK1_0", - "CMT_FIFO_EE4B3_5", - "CMT_FIFO_EE4A3_4", - "CMT_FIFO_L_IMUX47_5", - "CMT_FIFO_L_IMUX32_8", - "CMT_FIFO_NW2A1_6", - "CMT_FIFO_NW4A2_10", - "CMT_FIFO_L_IMUX42_6", - "CMT_FIFO_L_IMUX8_6", - "CMT_FIFO_L_IMUX14_11", - "CMT_FIFO_L_LOGIC_OUTS3_10", - "CMT_FIFO_L_IMUX16_5", - "CMT_IN_FIFO_Q26", - "CMT_FIFO_L_IMUX10_0", - "CMT_FIFO_EE2A2_7", - "CMT_FIFO_WW2A3_9", - "CMT_FIFO_L_LOGIC_OUTS23_1", - "CMT_FIFO_ER1BEG2_11", - "CMT_FIFO_SW2A0_3", - "CMT_FIFO_EE2BEG1_3", - "CMT_FIFO_L_LOGIC_OUTS9_6", - "CMT_FIFO_LH3_3", - "CMT_FIFO_NE4BEG2_4", - "CMT_FIFO_LH8_7", - "CMT_FIFO_LH5_5", - "CMT_FIFO_L_LOGIC_OUTS20_7", - "CMT_FIFO_SE2A3_10", - "CMT_FIFO_L_LOGIC_OUTS16_8", - "CMT_FIFO_L_IMUX9_6", - "CMT_FIFO_NE4C1_2", - "CMT_FIFO_WW4A1_8", - "CMT_IN_FIFO_D71", - "CMT_FIFO_L_IMUX0_10", - "CMT_FIFO_L_IMUX36_0", - "CMT_FIFO_L_BYP0_5", - "CMT_FIFO_MONITOR_P_0", - "CMT_FIFO_EE2BEG0_9", - "CMT_FIFO_SE4C1_5", - "CMT_FIFO_SE4C1_0", - "CMT_FIFO_L_FAN3_11", - "CMT_FIFO_WW4END2_1", - "CMT_FIFO_SE4BEG0_9", - "CMT_FIFO_MONITOR_P_4", - "CMT_FIFO_L_LOGIC_OUTS21_11", - "CMT_FIFO_WL1END0_4", - "CMT_FIFO_LH8_10", - "CMT_FIFO_EE2BEG3_9", - "CMT_FIFO_L_BYP7_6", - "CMT_FIFO_WW4A1_7", - "CMT_FIFO_WR1END2_7", - "CMT_FIFO_L_LOGIC_OUTS19_7", - "CMT_FIFO_NW2A1_10", - "CMT_FIFO_L_BYP3_10", - "CMT_FIFO_L_IMUX44_10", - "CMT_FIFO_L_BYP0_4", - "CMT_FIFO_L_BYP4_9", - "CMT_FIFO_WW4C0_0", - "CMT_FIFO_L_IMUX29_4", - "CMT_FIFO_WW2A2_5", - "CMT_FIFO_L_LOGIC_OUTS10_2", - "CMT_FIFO_SW2A3_3", - "CMT_FIFO_EE4BEG2_9", - "CMT_FIFO_L_IMUX25_4", - "CMT_FIFO_SE4BEG1_6", - "CMT_FIFO_ER1BEG3_1", - "CMT_FIFO_WW4END2_9", - "CMT_FIFO_L_IMUX38_10", - "CMT_FIFO_EE4C0_4", - "CMT_FIFO_L_IMUX27_3", - "CMT_FIFO_WW4END3_10", - "CMT_FIFO_L_IMUX13_8", - "CMT_FIFO_L_IMUX28_0", - "CMT_FIFO_WL1END2_2", - "CMT_FIFO_EE4C3_5", - "CMT_FIFO_ER1BEG0_6", - "CMT_OUT_FIFO_Q80", - "CMT_FIFO_SW4A1_4", - "CMT_IN_FIFO_D56", - "CMT_FIFO_L_IMUX0_9", - "CMT_FIFO_L_IMUX6_3", - "CMT_IN_FIFO_D01", - "CMT_FIFO_NE2A0_3", - "CMT_FIFO_L_IMUX35_0", - "CMT_FIFO_L_IMUX23_5", - "CMT_FIFO_NW2A2_9", - "CMT_FIFO_L_IMUX35_11", - "CMT_FIFO_MONITOR_N_6", - "CMT_FIFO_WW4END1_11", - "CMT_FIFO_SW2A0_6", - "CMT_FIFO_SW2A3_11", - "CMT_FIFO_L_FAN4_3", - "CMT_FIFO_WW4B0_6", - "CMT_FIFO_EE2BEG1_6", - "CMT_FIFO_NE4C0_8", - "CMT_FIFO_L_IMUX12_7", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", - "CMT_FIFO_SW4A0_11", - "CMT_FIFO_L_IMUX10_6", - "CMT_FIFO_WR1END1_11", - "CMT_OUT_FIFO_D11", - "CMT_FIFO_L_PHASER_WRCLK", - "CMT_FIFO_WW2A0_4", - "CMT_FIFO_SE4C0_11", - "CMT_FIFO_L_BYP2_3", - "CMT_FIFO_L_FAN5_3", - "CMT_FIFO_WW2A0_6", - "CMT_FIFO_EE4A3_8", - "CMT_FIFO_L_FAN5_4", - "CMT_FIFO_L_IMUX25_8", - "CMT_FIFO_L_LOGIC_OUTS20_11", - "CMT_FIFO_L_LOGIC_OUTS5_6", - "CMT_FIFO_L_IMUX6_7", - "CMT_FIFO_EE4B1_5", - "CMT_FIFO_WL1END1_0", - "CMT_FIFO_L_BYP1_4", - "CMT_FIFO_L_IMUX9_1", - "CMT_FIFO_L_IMUX24_10", - "CMT_FIFO_WL1END1_6", - "CMT_FIFO_EE2BEG3_2", - "CMT_FIFO_MONITOR_P_6", - "CMT_FIFO_LH3_11", - "CMT_FIFO_L_FAN6_0", - "CMT_FIFO_EE2A3_9", - "CMT_FIFO_LH9_10", - "CMT_OUT_FIFO_Q63", - "CMT_FIFO_L_LOGIC_OUTS15_11", - "CMT_FIFO_EE2BEG3_6", - "CMT_FIFO_LH8_0", - "CMT_OUT_FIFO_Q61", - "CMT_FIFO_WW4B3_8", - "CMT_FIFO_WL1END2_4", - "CMT_FIFO_L_FAN7_1", - "CMT_FIFO_L_BYP6_7", - "CMT_FIFO_L_LOGIC_OUTS3_8", - "CMT_FIFO_L_IMUX13_5", - "CMT_FIFO_WW4END3_7", - "CMT_FIFO_L_LOGIC_OUTS16_3", - "CMT_IN_FIFO_Q33", - "CMT_FIFO_NW2A1_8", - "CMT_FIFO_SE4C3_10", - "CMT_FIFO_NE4C1_0", - "CMT_FIFO_LH12_7", - "CMT_FIFO_L_IMUX42_2", - "CMT_FIFO_NE2A3_11", - "CMT_FIFO_L_IMUX39_2", - "CMT_FIFO_SW4END2_9", - "CMT_FIFO_WL1END2_11", - "CMT_FIFO_EE4B2_7", - "CMT_FIFO_L_LOGIC_OUTS17_3", - "CMT_FIFO_L_FAN1_0", - "CMT_FIFO_NE2A3_6", - "CMT_FIFO_L_IMUX46_2", - "CMT_FIFO_L_LOGIC_OUTS1_1", - "CMT_FIFO_SW2A0_1", - "CMT_FIFO_L_CLK1_2", - "CMT_FIFO_EE4A3_0", - "CMT_FIFO_L_IMUX38_8", - "CMT_OUT_FIFO_Q12", - "CMT_FIFO_L_IMUX32_9", - "CMT_FIFO_L_LOGIC_OUTS11_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", - "CMT_FIFO_WW4END1_9", - "CMT_FIFO_LH12_5", - "CMT_IN_FIFO_Q76", - "CMT_FIFO_L_BYP6_1", - "CMT_FIFO_EE4A0_5", - "CMT_FIFO_WW4B3_3", - "CMT_OUT_FIFO_Q57", - "CMT_FIFO_L_LOGIC_OUTS15_10", - "CMT_FIFO_L_IMUX31_5", - "CMT_FIFO_L_IMUX46_6", - "CMT_FIFO_L_IMUX22_3", - "CMT_FIFO_EE4C0_10", - "CMT_FIFO_L_LOGIC_OUTS12_2", - "CMT_FIFO_WL1END2_5", - "CMT_IN_FIFO_Q94", - "CMT_FIFO_EE2A3_4", - "CMT_OUT_FIFO_D91", - "CMT_FIFO_L_IMUX43_2", - "CMT_FIFO_NE4BEG1_4", - "CMT_IN_FIFO_D40", - "CMT_FIFO_WW4A3_8", - "CMT_FIFO_SW4A1_2", - "CMT_FIFO_LH9_4", - "CMT_FIFO_NE4BEG1_5", - "CMT_FIFO_L_IMUX18_2", - "CMT_FIFO_WR1END2_6", - "FIFO_DQS_IOTOPHASER_66", - "CMT_FIFO_L_LOGIC_OUTS17_7", - "CMT_FIFO_NE2A3_7", - "CMT_FIFO_L_LOGIC_OUTS15_3", - "CMT_FIFO_NW4A1_11", - "CMT_FIFO_SW2A0_9", - "CMT_FIFO_NW4END2_10", - "CMT_OUT_FIFO_Q91", - "CMT_FIFO_L_LOGIC_OUTS21_0", - "CMT_FIFO_L_IMUX46_7", - "CMT_FIFO_WW4B2_11", - "CMT_FIFO_WW2END3_4", - "CMT_FIFO_WW4END1_6", - "CMT_FIFO_WW2A0_8", - "CMT_FIFO_L_LOGIC_OUTS10_4", - "CMT_FIFO_LH8_2", - "CMT_FIFO_L_IMUX4_8", - "CMT_FIFO_SW4A2_5", - "CMT_FIFO_EE2A3_8", - "CMT_FIFO_L_IMUX9_10", - "CMT_FIFO_EE4C2_7", - "CMT_FIFO_L_IMUX2_0", - "CMT_FIFO_WW4A2_7", - "CMT_FIFO_L_BYP2_1", - "CMT_FIFO_EE4BEG3_0", - "CMT_FIFO_L_IMUX7_9", - "CMT_FIFO_L_LOGIC_OUTS22_3", - "CMT_FIFO_L_IMUX15_11", - "CMT_FIFO_L_LOGIC_OUTS2_8", - "CMT_FIFO_ER1BEG1_7", - "CMT_FIFO_L_IMUX32_4", - "CMT_FIFO_L_LOGIC_OUTS18_4", - "CMT_IN_FIFO_Q73", - "CMT_FIFO_SE4BEG2_5", - "CMT_FIFO_L_IMUX47_1", - "CMT_FIFO_NE4BEG1_3", - "CMT_FIFO_L_IMUX29_10", - "CMT_FIFO_L_IMUX23_4", - "CMT_FIFO_NW2A3_4", - "CMT_FIFO_L_LOGIC_OUTS7_5", - "CMT_FIFO_NW4A3_11", - "CMT_FIFO_ER1BEG0_5", - "CMT_FIFO_L_IMUX38_0", - "CMT_FIFO_SW4A3_5", - "CMT_IN_FIFO_Q22", - "CMT_FIFO_L_IMUX33_3", - "CMT_FIFO_L_FAN6_3", - "CMT_FIFO_EE4A2_0", - "CMT_FIFO_EE2BEG0_10", - "CMT_FIFO_NW4A3_7", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", - "CMT_FIFO_EE4C3_10", - "CMT_FIFO_EE2A2_3", - "CMT_FIFO_SW2A2_0", - "CMT_FIFO_NW2A1_9", - "CMT_FIFO_L_IMUX17_0", - "CMT_FIFO_L_IMUX13_11", - "CMT_FIFO_WW4B0_7", - "CMT_FIFO_NW4END3_4", - "CMT_FIFO_EE4BEG1_0", - "CMT_FIFO_NW2A2_5", - "CMT_FIFO_L_FAN7_2", - "CMT_FIFO_L_FAN7_0", - "CMT_FIFO_NW4A1_2", - "CMT_FIFO_ER1BEG0_2", - "CMT_OUT_FIFO_D52", - "CMT_FIFO_SW4END2_11", - "CMT_FIFO_EE2A1_1", - "CMT_FIFO_L_IMUX46_4", - "CMT_FIFO_EE4BEG3_1", - "CMT_FIFO_NE2A3_8", - "CMT_FIFO_WW4B1_11", - "CMT_FIFO_WW4B2_10", - "CMT_FIFO_EE2A2_5", - "CMT_FIFO_NW4A1_1", - "CMT_FIFO_L_IMUX46_9", - "CMT_FIFO_L_IMUX12_8", - "CMT_FIFO_SW2A3_2", - "CMT_FIFO_L_CLK0_2", - "CMT_FIFO_WL1END2_8", - "CMT_FIFO_L_LOGIC_OUTS8_10", - "CMT_FIFO_L_IMUX40_11", - "CMT_FIFO_ER1BEG3_0", - "CMT_FIFO_L_BYP5_9", - "CMT_FIFO_L_BYP4_5", - "CMT_FIFO_L_IMUX33_2", - "CMT_FIFO_NW4END1_2", - "CMT_FIFO_NW2A2_6", - "CMT_FIFO_NW4A3_4", - "CMT_FIFO_EE4C2_11", - "CMT_FIFO_WL1END0_10", - "CMT_FIFO_L_FAN1_10", - "CMT_FIFO_L_IMUX5_1", - "CMT_FIFO_WW4END3_4", - "CMT_FIFO_LH4_9", - "CMT_FIFO_EE4C3_3", - "CMT_FIFO_SW2A1_6", - "CMT_FIFO_L_IMUX7_5", - "CMT_FIFO_L_BYP6_9", - "CMT_FIFO_L_IMUX24_1", - "CMT_FIFO_EE2BEG2_10", - "CMT_FIFO_L_LOGIC_OUTS17_4", - "CMT_FIFO_NW4END0_2", - "CMT_FIFO_L_LOGIC_OUTS21_7", - "CMT_FIFO_LH10_10", - "CMT_FIFO_L_LOGIC_OUTS19_5", - "CMT_FIFO_L_BYP3_1", - "CMT_FIFO_EE4A3_7", - "CMT_FIFO_L_IMUX30_8", - "CMT_FIFO_L_IMUX19_1", - "CMT_FIFO_L_LOGIC_OUTS1_0", - "CMT_FIFO_L_IMUX0_0", - "CMT_FIFO_WW4B0_11", - "CMT_FIFO_L_CTRL1_1", - "CMT_FIFO_EL1BEG2_10", - "CMT_IN_FIFO_Q32", - "CMT_FIFO_L_LOGIC_OUTS11_11", - "CMT_IN_FIFO_Q92", - "CMT_FIFO_SE4C0_8", - "CMT_FIFO_L_LOGIC_OUTS7_3", - "CMT_FIFO_NE2A0_9", - "CMT_IN_FIFO_Q56", - "CMT_FIFO_NW4A1_10", - "CMT_FIFO_SW4A0_10", - "CMT_FIFO_WR1END1_6", - "CMT_FIFO_L_IMUX39_1", - "CMT_FIFO_SE2A1_11", - "CMT_IN_FIFO_Q43", - "CMT_FIFO_L_IMUX45_4", - "CMT_FIFO_WW4B3_5", - "CMT_FIFO_SW4END3_5", - "CMT_FIFO_L_LOGIC_OUTS21_9", - "CMT_FIFO_L_LOGIC_OUTS4_1", - "CMT_FIFO_L_IMUX26_7", - "CMT_FIFO_L_IMUX36_9", - "CMT_FIFO_SE4C2_0", - "CMT_FIFO_WW4C3_4", - "CMT_FIFO_LH1_8", - "CMT_FIFO_L_IMUX25_11", - "CMT_FIFO_WR1END3_1", - "CMT_FIFO_L_IMUX12_3", - "CMT_FIFO_WL1END1_4", - "CMT_FIFO_EE4A1_7", - "CMT_FIFO_L_IMUX9_4", - "CMT_FIFO_EE2A2_8", - "CMT_FIFO_L_FAN2_6", - "CMT_FIFO_ER1BEG1_10", - "CMT_FIFO_L_IMUX22_8", - "CMT_FIFO_EE2A0_9", - "CMT_FIFO_L_LOGIC_OUTS16_10", - "CMT_FIFO_EE4BEG1_2", - "CMT_FIFO_EL1BEG2_0", - "CMT_FIFO_SE4BEG3_7", - "CMT_FIFO_L_IMUX3_8", - "CMT_FIFO_L_IMUX30_11", - "CMT_FIFO_WW2A3_2", - "CMT_FIFO_WW4A1_4", - "CMT_FIFO_L_IMUX12_6", - "CMT_FIFO_WW4C2_7", - "CMT_FIFO_WW4C0_1", - "CMT_FIFO_EL1BEG1_3", - "CMT_FIFO_WW4B2_3", - "CMT_FIFO_WW4C3_6", - "CMT_FIFO_SE4BEG2_3", - "CMT_FIFO_SW4A2_3", - "CMT_FIFO_SW4A1_9", - "CMT_FIFO_MONITOR_P_5", - "CMT_FIFO_EE4B2_4", - "CMT_FIFO_L_FAN5_5", - "CMT_FIFO_SW4END1_2", - "CMT_FIFO_L_IMUX43_8", - "CMT_FIFO_NW4A0_1", - "CMT_FIFO_L_IMUX27_8", - "CMT_FIFO_SW4A3_8", - "CMT_FIFO_WW4B0_4", - "CMT_FIFO_MONITOR_N_10", - "CMT_FIFO_L_IMUX20_2", - "CMT_FIFO_NE4C2_0", - "CMT_FIFO_L_IMUX20_10", - "CMT_FIFO_MONITOR_N_11", - "CMT_FIFO_EE4A0_0", - "CMT_FIFO_SW4A2_9", - "CMT_FIFO_EE4A0_1", - "CMT_FIFO_WW4END0_3", - "CMT_FIFO_L_IMUX36_6", - "CMT_FIFO_L_LOGIC_OUTS7_7", - "CMT_FIFO_SW4A0_7", - "CMT_FIFO_L_LOGIC_OUTS7_4", - "CMT_FIFO_WW4C0_3", - "CMT_FIFO_L_LOGIC_OUTS19_10", - "CMT_FIFO_L_IMUX43_4", - "CMT_FIFO_EE4A1_1", - "CMT_FIFO_L_IMUX28_6", - "CMT_FIFO_L_IMUX40_2", - "CMT_FIFO_L_IMUX28_2", - "CMT_FIFO_WW4A3_7", - "CMT_FIFO_WW4END3_1", - "CMT_FIFO_ER1BEG0_0", - "CMT_FIFO_L_IMUX15_0", - "CMT_FIFO_L_CTRL1_4", - "CMT_FIFO_LH4_8", - "CMT_OUT_FIFO_D44", - "CMT_FIFO_EE4BEG1_8", - "CMT_FIFO_WL1END0_5", - "CMT_FIFO_L_IMUX47_4", - "CMT_FIFO_L_IMUX4_1", - "CMT_FIFO_NE4C0_6", - "CMT_FIFO_EE2BEG1_1", - "CMT_FIFO_NW4A2_0", - "CMT_FIFO_L_IMUX29_5", - "CMT_FIFO_EE4A3_6", - "CMT_FIFO_L_BYP0_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_10", - "CMT_IN_FIFO_D64", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", - "CMT_FIFO_EE2BEG1_2", - "CMT_FIFO_EE4B0_4", - "CMT_FIFO_L_IMUX45_1", - "CMT_FIFO_L_LOGIC_OUTS7_10", - "CMT_FIFO_NW4A0_6", - "CMT_FIFO_WR1END0_11", - "CMT_FIFO_SE2A1_10", - "CMT_FIFO_L_BYP7_9", - "CMT_OUT_FIFO_SCANIN2", - "CMT_FIFO_NE4BEG1_6", - "CMT_FIFO_EE2BEG3_5", - "CMT_FIFO_SE2A1_3", - "CMT_FIFO_L_IMUX15_5", - "CMT_FIFO_NE2A1_7", - "CMT_FIFO_PHASER_TO_IO_ICLK_5", - "CMT_FIFO_L_IMUX16_9", - "CMT_FIFO_L_IMUX36_3", - "CMT_FIFO_WW2END0_11", - "CMT_IN_FIFO_D90", - "CMT_FIFO_L_IMUX5_5", - "CMT_FIFO_L_BYP4_8", - "CMT_FIFO_L_IMUX31_10", - "CMT_IN_FIFO_D51", - "CMT_FIFO_EE4C1_0", - "CMT_FIFO_EE4C2_9", - "CMT_FIFO_L_IMUX15_6", - "CMT_FIFO_L_IMUX28_11", - "CMT_FIFO_SW2A1_5", - "CMT_FIFO_SW4A3_9", - "CMT_FIFO_L_LOGIC_OUTS3_7", - "CMT_FIFO_L_IMUX6_10", - "CMT_FIFO_L_IMUX32_10", - "CMT_OUT_FIFO_Q66", - "CMT_FIFO_WW4END2_0", - "CMT_FIFO_L_LOGIC_OUTS4_3", - "CMT_FIFO_L_IMUX11_10", - "CMT_FIFO_LH5_6", - "CMT_FIFO_SW4A1_1", - "CMT_FIFO_L_BYP7_1", - "CMT_OUT_FIFO_D17", - "CMT_FIFO_EE2BEG3_3", - "CMT_FIFO_EL1BEG0_6", - "CMT_FIFO_NE4C0_1", - "CMT_FIFO_LH12_2", - "CMT_IN_FIFO_Q84", - "CMT_OUT_FIFO_D04", - "CMT_IN_FIFO_D83", - "CMT_FIFO_L_IMUX22_0", - "CMT_FIFO_L_IMUX3_6", - "CMT_FIFO_L_BYP1_2", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_6", - "CMT_FIFO_NE2A3_3", - "CMT_FIFO_L_IMUX3_7", - "CMT_FIFO_L_IMUX16_10", - "CMT_OUT_FIFO_D13", - "CMT_FIFO_NE4C1_5", - "CMT_FIFO_L_BYP3_3", - "CMT_FIFO_NE4BEG0_5", - "CMT_FIFO_L_LOGIC_OUTS12_4", - "CMT_FIFO_L_IMUX23_0", - "CMT_IN_FIFO_SCANOUT0", - "CMT_FIFO_SE4C3_8", - "CMT_FIFO_SW4A0_8", - "CMT_FIFO_L_LOGIC_OUTS14_9", - "CMT_FIFO_L_LOGIC_OUTS16_9", - "CMT_IN_FIFO_Q95", - "CMT_FIFO_L_LOGIC_OUTS21_6", - "CMT_FIFO_WR1END2_1", - "CMT_FIFO_L_LOGIC_OUTS20_5", - "CMT_FIFO_L_LOGIC_OUTS0_10", - "CMT_FIFO_EE2A3_7", - "CMT_FIFO_NE4C0_2", - "CMT_OUT_FIFO_ALMOSTFULL", - "CMT_FIFO_EE4A2_5", - "CMT_FIFO_WR1END3_0", - "CMT_FIFO_L_LOGIC_OUTS15_8", - "CMT_FIFO_EE4BEG1_9", - "CMT_FIFO_NW4A0_9", - "CMT_FIFO_L_IMUX39_11", - "CMT_FIFO_SE4C1_7", - "CMT_FIFO_EE2A3_11", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", - "CMT_FIFO_EE2A1_3", - "CMT_FIFO_WW2END3_8", - "CMT_FIFO_WW4B1_7", - "CMT_FIFO_L_LOGIC_OUTS1_9", - "CMT_FIFO_L_IMUX19_8", - "CMT_FIFO_L_LOGIC_OUTS4_0", - "CMT_FIFO_EL1BEG1_10", - "CMT_FIFO_NE4C2_7", - "CMT_FIFO_WW2A3_4", - "CMT_FIFO_L_IMUX16_0", - "CMT_FIFO_NW4END2_8", - "CMT_FIFO_L_IMUX20_0", - "CMT_IN_FIFO_SCANIN3", - "CMT_FIFO_WW4C2_8", - "CMT_OUT_FIFO_Q92", - "CMT_FIFO_SE4BEG3_10", - "CMT_FIFO_LH6_4", - "CMT_FIFO_MONITOR_N_5", - "CMT_FIFO_L_IMUX21_11", - "CMT_FIFO_EE4BEG2_10", - "CMT_FIFO_L_IMUX33_7", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", - "CMT_FIFO_WW4B3_10", - "CMT_FIFO_L_LOGIC_OUTS1_2", - "CMT_FIFO_WW4B0_1", - "CMT_OUT_FIFO_Q83", - "CMT_FIFO_L_CLK0_10", - "CMT_OUT_FIFO_Q65", - "CMT_FIFO_L_IMUX45_3", - "CMT_FIFO_WW2END2_6", - "CMT_FIFO_L_IMUX39_8", - "CMT_FIFO_NE4BEG3_0", - "CMT_OUT_FIFO_D26", - "CMT_FIFO_WW4A2_0", - "CMT_FIFO_ER1BEG2_2", - "CMT_FIFO_L_IMUX13_3", - "CMT_FIFO_WL1END0_8", - "CMT_FIFO_L_IMUX47_11", - "CMT_OUT_FIFO_D75", - "CMT_FIFO_L_BYP1_7", - "CMT_FIFO_L_FAN2_5", - "CMT_FIFO_NW4A2_11", - "CMT_IN_FIFO_D41", - "CMT_FIFO_EE2BEG0_1", - "CMT_FIFO_ER1BEG0_3", - "CMT_FIFO_EE4A1_5", - "CMT_OUT_FIFO_D96", - "CMT_FIFO_EE2BEG3_0", - "CMT_FIFO_L_FAN1_3", - "CMT_FIFO_WW4B1_3", - "CMT_OUT_FIFO_D97", - "CMT_FIFO_ER1BEG2_5", - "CMT_FIFO_L_LOGIC_OUTS13_6", - "CMT_FIFO_SW4A3_3", - "CMT_FIFO_EE2A1_4", - "CMT_FIFO_WW2A3_8", - "CMT_FIFO_EE4BEG3_11", - "CMT_FIFO_NW4END2_2", - "CMT_FIFO_EL1BEG0_5", - "CMT_FIFO_SE2A0_8", - "CMT_FIFO_EL1BEG2_1", - "CMT_FIFO_L_LOGIC_OUTS23_8", - "CMT_FIFO_WL1END2_1", - "CMT_FIFO_WW4A1_0", - "CMT_FIFO_L_LOGIC_OUTS10_10", - "CMT_FIFO_WW4C3_5", - "CMT_FIFO_SW2A0_4", - "CMT_FIFO_NE2A3_10", - "CMT_FIFO_NW4A3_3", - "CMT_IN_FIFO_Q23", - "CMT_FIFO_L_FAN5_1", - "CMT_FIFO_L_IMUX1_8", - "CMT_FIFO_L_IMUX5_3", - "CMT_FIFO_L_LOGIC_OUTS8_1", - "CMT_FIFO_NW4END3_6", - "CMT_FIFO_L_IMUX23_1", - "CMT_FIFO_LH1_11", - "CMT_FIFO_L_IMUX9_5", - "CMT_FIFO_NE4C3_0", - "CMT_FIFO_WW4B0_2", - "CMT_FIFO_EL1BEG3_2", - "CMT_FIFO_L_IMUX44_4", - "CMT_IN_FIFO_Q65", - "CMT_FIFO_SE2A0_6", - "CMT_FIFO_NW4END1_7", - "CMT_IN_FIFO_D60", - "CMT_OUT_FIFO_Q50", - "CMT_FIFO_L_IMUX24_11", - "CMT_FIFO_L_IMUX9_0", - "CMT_FIFO_SE4BEG2_7", - "CMT_FIFO_L_LOGIC_OUTS16_6", - "CMT_OUT_FIFO_D85", - "CMT_FIFO_L_IMUX33_10", - "CMT_FIFO_L_IMUX14_1", - "CMT_FIFO_L_LOGIC_OUTS5_1", - "CMT_FIFO_L_FAN7_6", - "CMT_FIFO_WW4C1_11", - "CMT_FIFO_L_IMUX29_0", - "CMT_FIFO_L_LOGIC_OUTS14_6", - "CMT_FIFO_NE4BEG2_8", - "CMT_FIFO_SW4A3_11", - "CMT_FIFO_L_IMUX4_9", - "CMT_FIFO_L_IMUX6_6", - "CMT_OUT_FIFO_Q40", - "CMT_FIFO_SW4END3_7", - "CMT_FIFO_LH6_3", - "CMT_FIFO_WL1END2_10", - "CMT_FIFO_WR1END3_8", - "CMT_IN_FIFO_Q14", - "CMT_FIFO_L_IMUX26_2", - "CMT_FIFO_WW2A2_0", - "CMT_FIFO_L_LOGIC_OUTS2_6", - "CMT_FIFO_L_IMUX4_10", - "CMT_FIFO_NE4C0_5", - "CMT_FIFO_LH6_5", - "CMT_FIFO_LH4_2", - "CMT_FIFO_EE4C1_7", - "CMT_FIFO_L_LOGIC_OUTS0_7", - "CMT_IN_FIFO_D23", - "CMT_FIFO_WW4C3_9", - "CMT_FIFO_SE2A2_6", - "CMT_IN_FIFO_Q37", - "CMT_OUT_FIFO_Q21", - "CMT_FIFO_LH2_5", - "CMT_IN_FIFO_Q70", - "CMT_FIFO_WW2A0_3", - "CMT_FIFO_L_LOGIC_OUTS14_7", - "CMT_FIFO_EE4BEG2_3", - "CMT_FIFO_NE4C1_7", - "CMT_FIFO_WW2A1_0", - "CMT_FIFO_L_IMUX11_6", - "CMT_FIFO_SE4BEG0_5", - "CMT_FIFO_MONITOR_N_4", - "CMT_FIFO_NW2A1_3", - "CMT_FIFO_EE4BEG2_0", - "CMT_FIFO_LH10_9", - "CMT_FIFO_L_IMUX16_2", - "CMT_FIFO_WW2A2_1", - "CMT_FIFO_LH4_1", - "CMT_FIFO_L_IMUX17_1", - "CMT_FIFO_L_IMUX45_8", - "CMT_FIFO_L_LOGIC_OUTS4_5", - "CMT_FIFO_EL1BEG2_6", - "CMT_FIFO_WW4B2_4", - "CMT_FIFO_EE2BEG1_5", - "CMT_FIFO_L_IMUX1_3", - "CMT_FIFO_SW4END0_8", - "CMT_FIFO_SW2A3_8", - "CMT_FIFO_L_FAN3_2", - "CMT_FIFO_WR1END1_3", - "CMT_FIFO_WL1END2_3", - "CMT_FIFO_WW2A0_10", - "CMT_FIFO_SE2A3_7", - "CMT_FIFO_L_IMUX45_10", - "CMT_FIFO_NE4BEG3_7", - "CMT_FIFO_NW2A0_8", - "CMT_FIFO_WR1END1_4", - "CMT_FIFO_SE2A1_8", - "CMT_FIFO_WW2END0_10", - "CMT_FIFO_EE2A0_0", - "CMT_FIFO_SW4END3_4", - "CMT_FIFO_NW4A2_9", - "CMT_FIFO_L_BYP7_11", - "CMT_FIFO_WW2END1_5", - "CMT_FIFO_SE4BEG1_7", - "CMT_FIFO_EE4BEG0_11", - "CMT_FIFO_WW4A0_6", - "CMT_FIFO_WR1END3_7", - "CMT_IN_FIFO_D91", - "CMT_FIFO_L_IMUX39_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", - "CMT_FIFO_L_IMUX46_11", - "CMT_FIFO_L_LOGIC_OUTS8_4", - "CMT_FIFO_LH3_2", - "CMT_FIFO_PHASER_TO_IO_ICLK_3", - "CMT_FIFO_EE4C1_5", - "CMT_FIFO_L_IMUX24_4", - "CMT_FIFO_L_IMUX45_11", - "CMT_FIFO_SW4END3_6", - "CMT_FIFO_EE4BEG0_9", - "CMT_FIFO_LH11_6", - "CMT_FIFO_L_IMUX28_5", - "CMT_FIFO_L_IMUX18_8", - "CMT_FIFO_L_LOGIC_OUTS9_3", - "CMT_FIFO_WW4B0_9", - "CMT_FIFO_LH2_8", - "CMT_FIFO_WW4A2_2", - "CMT_FIFO_NW2A0_1", - "CMT_IN_FIFO_Q31", - "CMT_FIFO_WW4B3_4", - "CMT_FIFO_L_IMUX6_2", - "CMT_FIFO_L_IMUX20_5", - "CMT_FIFO_L_IMUX29_9", - "CMT_FIFO_L_IMUX29_2", - "CMT_FIFO_SE4BEG1_3", - "CMT_FIFO_L_LOGIC_OUTS20_10", - "CMT_FIFO_L_LOGIC_OUTS15_9", - "CMT_FIFO_EE4A2_7", - "CMT_FIFO_L_IMUX37_9", - "CMT_FIFO_L_IMUX13_10", - "CMT_FIFO_EE2A1_9", - "CMT_FIFO_L_IMUX20_6", - "CMT_FIFO_EE4B3_10", - "CMT_FIFO_WW4B3_0", - "CMT_FIFO_ER1BEG0_9", - "CMT_FIFO_EL1BEG3_3", - "CMT_FIFO_LH8_5", - "CMT_OUT_FIFO_D57", - "CMT_FIFO_WW2A2_10", - "CMT_IN_FIFO_D81", - "CMT_FIFO_L_LOGIC_OUTS1_4", - "CMT_FIFO_WW4B1_6", - "CMT_IN_FIFO_D31", - "CMT_FIFO_EE4B3_0", - "CMT_FIFO_SE4BEG0_8", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", - "CMT_FIFO_L_FAN3_5", - "CMT_FIFO_L_LOGIC_OUTS5_5", - "CMT_FIFO_WW4B3_9", - "CMT_FIFO_WW2END0_9", - "CMT_FIFO_L_BYP3_6", - "CMT_FIFO_EE4B3_9", - "CMT_FIFO_NE2A2_2", - "CMT_FIFO_EE4BEG2_11", - "CMT_FIFO_L_IMUX7_3", - "CMT_FIFO_L_IMUX1_11", - "CMT_FIFO_EE4C1_6", - "CMT_FIFO_L_IMUX14_10", - "CMT_FIFO_SW4END1_1", - "CMT_FIFO_LH12_0", - "CMT_FIFO_NW2A0_11", - "CMT_FIFO_WW2A2_8", - "CMT_FIFO_L_LOGIC_OUTS4_9", - "CMT_FIFO_L_IMUX18_1", - "CMT_FIFO_L_LOGIC_OUTS0_2", - "CMT_FIFO_WR1END0_9", - "CMT_FIFO_L_IMUX45_2", - "CMT_IN_FIFO_D55", - "CMT_FIFO_L_IMUX37_4", - "CMT_FIFO_L_IMUX33_4", - "CMT_FIFO_WW4A2_1", - "CMT_FIFO_L_IMUX4_11", - "CMT_FIFO_L_IMUX3_5", - "CMT_FIFO_PHASER_TO_IO_ICLK_6", - "CMT_FIFO_L_LOGIC_OUTS13_7", - "CMT_IN_FIFO_D92", - "CMT_FIFO_SE4BEG1_5", - "CMT_FIFO_LH7_5", - "CMT_FIFO_LH1_6", - "CMT_FIFO_L_FAN5_7", - "CMT_FIFO_L_IMUX21_10", - "CMT_FIFO_SE4C3_9", - "CMT_FIFO_L_LOGIC_OUTS11_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_4", - "CMT_FIFO_SE4C1_1", - "CMT_FIFO_EE4BEG1_1", - "CMT_FIFO_L_IMUX3_0", - "CMT_FIFO_NE2A0_0", - "CMT_IN_FIFO_D33", - "CMT_FIFO_WW2A2_4", - "CMT_FIFO_L_BYP6_4", - "CMT_FIFO_L_BYP3_9", - "CMT_FIFO_L_LOGIC_OUTS6_8", - "CMT_FIFO_WW4A0_8", - "CMT_FIFO_WW4B2_9", - "CMT_FIFO_EE2A3_3", - "CMT_FIFO_EE2BEG0_5", - "CMT_FIFO_WW4C0_11", - "CMT_FIFO_SW4A3_10", - "CMT_FIFO_EE4BEG1_3", - "CMT_FIFO_SW4END3_2", - "CMT_FIFO_NW4A1_8", - "CMT_FIFO_SW2A3_4", - "CMT_FIFO_WW4C1_6", - "CMT_FIFO_L_IMUX28_7", - "CMT_FIFO_L_BYP4_0", - "CMT_FIFO_L_IMUX33_0", - "CMT_IN_FIFO_D30", - "CMT_FIFO_L_LOGIC_OUTS22_5", - "CMT_FIFO_EL1BEG3_0", - "CMT_FIFO_LH10_3", - "CMT_FIFO_L_IMUX8_8", - "CMT_FIFO_L_FAN3_8", - "CMT_FIFO_EE2A2_0", - "CMT_FIFO_EE2BEG1_9", - "CMT_FIFO_WR1END3_11", - "CMT_OUT_FIFO_EMPTY", - "CMT_IN_FIFO_Q47", - "CMT_FIFO_L_IMUX29_7", - "CMT_FIFO_WR1END2_0", - "CMT_FIFO_WW2A1_5", - "CMT_FIFO_L_LOGIC_OUTS19_3", - "CMT_FIFO_EE4B3_6", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", - "CMT_FIFO_L_IMUX38_6", - "CMT_FIFO_PHASER_TO_IO_ICLK_10", - "CMT_FIFO_LH1_10", - "CMT_FIFO_L_LOGIC_OUTS20_2", - "CMT_FIFO_SE4BEG2_11", - "CMT_IN_FIFO_Q91", - "CMT_OUT_FIFO_D81", - "CMT_FIFO_L_IMUX0_1", - "CMT_FIFO_SE4C2_11", - "CMT_FIFO_NE4BEG3_6", - "CMT_FIFO_L_LOGIC_OUTS22_1", - "CMT_FIFO_L_LOGIC_OUTS22_4", - "CMT_FIFO_L_IMUX41_7", - "CMT_FIFO_EE2BEG3_1", - "CMT_FIFO_L_IMUX47_8", - "CMT_FIFO_WL1END3_0", - "CMT_FIFO_MONITOR_P_11", - "CMT_IN_FIFO_D10", - "CMT_OUT_FIFO_D27", - "CMT_FIFO_NW2A1_5", - "CMT_FIFO_L_IMUX5_4", - "CMT_FIFO_SW2A0_5", - "CMT_FIFO_SE4BEG0_10", - "CMT_FIFO_L_IMUX43_7", - "CMT_FIFO_EE2A1_2", - "CMT_FIFO_L_IMUX0_7", - "CMT_IN_FIFO_Q50", - "CMT_FIFO_LH1_9", - "CMT_FIFO_L_FAN0_7", - "CMT_FIFO_SW4A0_0", - "CMT_FIFO_EE4B2_11", - "CMT_FIFO_L_BYP2_4", - "CMT_FIFO_L_CTRL0_8", - "CMT_FIFO_WW2END2_9", - "CMT_IN_FIFO_D93", - "CMT_FIFO_L_CTRL1_10", - "CMT_FIFO_WW4END0_8", - "CMT_FIFO_SE2A1_5", - "CMT_FIFO_NW4END0_5", - "CMT_FIFO_NE2A3_4", - "CMT_FIFO_L_IMUX31_1", - "CMT_FIFO_WR1END1_1", - "CMT_FIFO_WW4B1_9", - "CMT_FIFO_LH6_10", - "CMT_FIFO_EE4B0_8", - "CMT_FIFO_L_IMUX28_1", - "CMT_FIFO_L_BYP2_10", - "CMT_FIFO_L_IMUX18_0", - "CMT_OUT_FIFO_Q30", - "CMT_FIFO_L_LOGIC_OUTS6_0", - "CMT_FIFO_L_IMUX41_5", - "CMT_FIFO_L_IMUX27_0", - "CMT_FIFO_L_IMUX14_2", - "CMT_FIFO_EL1BEG0_9", - "CMT_FIFO_L_FAN5_0", - "CMT_FIFO_L_BYP0_2", - "CMT_FIFO_L_FAN3_0", - "CMT_FIFO_EL1BEG2_2", - "CMT_FIFO_SW4END0_0", - "CMT_FIFO_L_IMUX33_5", - "CMT_FIFO_L_LOGIC_OUTS6_9", - "CMT_FIFO_NE4C3_11", - "CMT_FIFO_LH4_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", - "CMT_FIFO_SE2A1_6", - "CMT_FIFO_SE4C3_1", - "CMT_FIFO_WW2A1_8", - "CMT_FIFO_WW2A0_9", - "CMT_FIFO_L_IMUX4_4", - "CMT_FIFO_L_CTRL0_2", - "CMT_FIFO_WW4B3_2", - "CMT_FIFO_EE4BEG3_2", - "CMT_FIFO_WW4END1_10", - "CMT_FIFO_SE4BEG3_11", - "CMT_FIFO_NW4A3_6", - "CMT_FIFO_L_IMUX8_10", - "CMT_FIFO_WL1END3_9", - "CMT_FIFO_L_IMUX19_5", - "CMT_FIFO_L_FAN1_9", - "CMT_FIFO_EL1BEG1_4", - "CMT_FIFO_L_IMUX21_7", - "CMT_FIFO_LH11_5", - "CMT_FIFO_WW4C2_5", - "CMT_FIFO_L_IMUX17_10", - "CMT_FIFO_L_LOGIC_OUTS21_3", - "CMT_FIFO_L_IMUX1_9", - "CMT_FIFO_EE4A0_2", - "CMT_FIFO_EE2A1_11", - "CMT_IN_FIFO_D62", - "CMT_FIFO_L_IMUX27_10", - "CMT_FIFO_L_IMUX9_7", - "CMT_FIFO_L_IMUX19_6", - "CMT_FIFO_L_CTRL0_7", - "CMT_FIFO_L_LOGIC_OUTS15_1", - "CMT_FIFO_EE4A2_4", - "FIFO_DQS_IOTOPHASER_4", - "CMT_FIFO_SW4END2_1", - "CMT_FIFO_L_LOGIC_OUTS11_6", - "CMT_IN_FIFO_Q86", - "CMT_FIFO_MONITOR_P_10", - "CMT_OUT_FIFO_Q73", - "CMT_FIFO_L_LOGIC_OUTS23_4", - "CMT_OUT_FIFO_D61", - "CMT_FIFO_L_LOGIC_OUTS13_4", - "CMT_FIFO_L_LOGIC_OUTS13_5", - "CMT_OUT_FIFO_D14", - "CMT_FIFO_MONITOR_P_8", - "CMT_FIFO_NW2A3_10", - "CMT_FIFO_WW2END0_1", - "CMT_FIFO_L_IMUX24_9", - "CMT_FIFO_L_IMUX27_9", - "CMT_FIFO_L_IMUX35_3", - "CMT_FIFO_SW4A3_6", - "CMT_FIFO_SE2A0_0", - "CMT_FIFO_L_BYP5_10", - "CMT_IN_FIFO_D21", - "CMT_FIFO_L_IMUX41_9", - "CMT_FIFO_LH3_5", - "CMT_FIFO_L_IMUX2_2", - "CMT_FIFO_L_IMUX7_10", - "CMT_FIFO_SW4A0_3", - "CMT_FIFO_EE4BEG2_6", - "CMT_FIFO_L_CLK1_9", - "CMT_FIFO_L_LOGIC_OUTS4_6", - "CMT_FIFO_L_LOGIC_OUTS0_5", - "CMT_FIFO_L_IMUX26_5", - "CMT_FIFO_NW2A3_1", - "CMT_FIFO_L_LOGIC_OUTS23_5", - "CMT_FIFO_L_LOGIC_OUTS13_2", - "CMT_FIFO_SE4BEG2_1", - "CMT_FIFO_L_IMUX26_8", - "CMT_FIFO_L_IMUX6_4", - "CMT_FIFO_WL1END2_9", - "CMT_FIFO_NE4C2_11", - "CMT_FIFO_WW4END2_10", - "CMT_FIFO_SW2A2_5", - "CMT_FIFO_EL1BEG3_8", - "CMT_FIFO_L_LOGIC_OUTS8_6", - "CMT_IN_FIFO_SCANOUT3", - "CMT_FIFO_WW4END3_9", - "CMT_OUT_FIFO_D71", - "CMT_FIFO_NE4BEG2_11", - "CMT_FIFO_L_IMUX23_9", - "CMT_FIFO_L_IMUX46_0", - "CMT_FIFO_LH7_6", - "CMT_FIFO_L_IMUX16_11", - "CMT_FIFO_WW4END2_5", - "CMT_FIFO_SW2A3_1", - "CMT_FIFO_EE4B1_10", - "CMT_FIFO_L_FAN4_9", - "CMT_FIFO_NE4C2_9", - "CMT_FIFO_NW4A3_8", - "CMT_FIFO_WW2END1_3", - "CMT_IN_FIFO_Q74", - "CMT_FIFO_EE2A0_2", - "CMT_FIFO_L_LOGIC_OUTS22_8", - "CMT_FIFO_L_FAN1_2", - "CMT_FIFO_EL1BEG0_11", - "CMT_FIFO_L_IMUX14_0", - "CMT_FIFO_LH1_3", - "CMT_FIFO_L_BYP7_4", - "CMT_FIFO_SW2A2_6", - "CMT_FIFO_SE2A0_1", - "CMT_FIFO_WW4B3_7", - "CMT_FIFO_L_LOGIC_OUTS2_9", - "CMT_FIFO_LH11_0", - "CMT_FIFO_SW2A3_0", - "CMT_FIFO_LH5_8", - "CMT_FIFO_L_LOGIC_OUTS3_3", - "CMT_FIFO_PHASER_TO_IO_ICLK_1", - "CMT_FIFO_L_LOGIC_OUTS19_4", - "CMT_FIFO_L_LOGIC_OUTS17_9", - "CMT_IN_FIFO_FULL", - "CMT_FIFO_SW4A0_1", - "CMT_FIFO_L_LOGIC_OUTS16_7", - "CMT_FIFO_L_LOGIC_OUTS19_11", - "CMT_FIFO_L_CLK1_8", - "CMT_FIFO_EE2A3_6", - "CMT_FIFO_L_FAN3_4", - "CMT_FIFO_WW4C0_7", - "CMT_FIFO_L_LOGIC_OUTS20_3", - "CMT_FIFO_WW2END3_10", - "CMT_FIFO_L_IMUX2_5", - "CMT_FIFO_ER1BEG3_5", - "CMT_FIFO_L_IMUX30_5", - "CMT_FIFO_L_IMUX16_4", - "CMT_FIFO_WW4END3_5", - "CMT_FIFO_WW4A0_4", - "CMT_FIFO_L_LOGIC_OUTS21_10", - "CMT_FIFO_LH12_3", - "CMT_FIFO_SW4END1_8", - "CMT_FIFO_NW4END1_0", - "CMT_FIFO_SW4A1_3", - "CMT_FIFO_L_FAN1_11", - "CMT_OUT_FIFO_D60", - "CMT_FIFO_EE4B2_9", - "CMT_FIFO_WW4C3_0", - "CMT_FIFO_NW4A1_9", - "CMT_FIFO_L_CLK0_5", - "CMT_FIFO_L_IMUX11_11", - "CMT_FIFO_WL1END0_7", - "CMT_FIFO_L_IMUX26_11", - "CMT_FIFO_SE4BEG1_1", - "CMT_FIFO_NE4C3_7", - "CMT_OUT_FIFO_D73", - "CMT_FIFO_L_BYP0_7", - "CMT_FIFO_WR1END2_5", - "CMT_FIFO_WW4A1_11", - "CMT_FIFO_SE4BEG3_8", - "CMT_FIFO_NW4A0_0", - "CMT_FIFO_WW2A1_1", - "CMT_FIFO_WR1END0_2", - "CMT_FIFO_LH10_0", - "CMT_IN_FIFO_Q83", - "CMT_FIFO_L_FAN7_3", - "CMT_IN_FIFO_Q85", - "CMT_OUT_FIFO_Q62", - "CMT_FIFO_L_IMUX45_5", - "CMT_FIFO_WW4C3_1", - "CMT_FIFO_LH1_5", - "CMT_FIFO_L_LOGIC_OUTS10_9", - "CMT_FIFO_WW2A2_9", - "CMT_FIFO_LH11_3", - "CMT_FIFO_SW4A0_2", - "CMT_FIFO_EE2A2_2", - "CMT_OUT_FIFO_TESTREADDISB", - "CMT_FIFO_SW2A3_9", - "CMT_FIFO_L_LOGIC_OUTS17_1", - "CMT_FIFO_WL1END0_9", - "CMT_FIFO_L_LOGIC_OUTS20_9", - "CMT_FIFO_EE4B0_0", - "CMT_FIFO_LH3_6", - "CMT_FIFO_EE2BEG1_10", - "CMT_FIFO_EE4B0_6", - "CMT_OUT_FIFO_WRCLK", - "CMT_FIFO_WW4END1_5", - "CMT_FIFO_L_FAN3_3", - "CMT_FIFO_L_CLK1_4", - "CMT_FIFO_NW4END3_9", - "CMT_FIFO_NE4C3_1", - "CMT_FIFO_L_FAN6_8", - "CMT_IN_FIFO_D72", - "CMT_FIFO_L_IMUX28_4", - "CMT_FIFO_L_IMUX30_6", - "CMT_IN_FIFO_Q03", - "CMT_FIFO_SE4BEG3_4", - "CMT_FIFO_EE4C2_8", - "CMT_FIFO_L_IMUX44_8", - "CMT_OUT_FIFO_FULL", - "CMT_FIFO_WL1END1_2", - "CMT_FIFO_LH9_1", - "CMT_FIFO_SW4END3_3", - "CMT_FIFO_WW4C0_5", - "CMT_FIFO_SE4BEG3_3", - "CMT_OUT_FIFO_Q93", - "CMT_FIFO_WW2A1_6", - "CMT_FIFO_WW2END0_8", - "CMT_FIFO_EE2BEG3_10", - "CMT_FIFO_LH5_3", - "CMT_FIFO_L_IMUX37_1", - "CMT_FIFO_L_BYP7_3", - "CMT_FIFO_L_IMUX3_2", - "CMT_FIFO_L_LOGIC_OUTS14_0", - "CMT_FIFO_WW4A0_9", - "CMT_FIFO_WL1END3_3", - "CMT_FIFO_SW4A0_9", - "CMT_FIFO_SE4C3_3", - "CMT_OUT_FIFO_WREN", - "CMT_FIFO_ER1BEG1_9", - "CMT_FIFO_L_LOGIC_OUTS17_2", - "CMT_IN_FIFO_Q16", - "CMT_FIFO_PHASER_TO_IO_ICLK_2", - "CMT_FIFO_SE4C1_3", - "CMT_FIFO_NW4END1_9", - "CMT_FIFO_EE4BEG3_5", - "CMT_FIFO_NE4BEG0_10", - "CMT_IN_FIFO_Q34", - "CMT_FIFO_L_LOGIC_OUTS6_4", - "CMT_FIFO_WW4END0_0", - "CMT_FIFO_SE2A1_9", - "CMT_FIFO_L_LOGIC_OUTS6_11", - "CMT_FIFO_L_IMUX39_6", - "CMT_FIFO_L_IMUX8_3", - "CMT_FIFO_NE2A3_1", - "CMT_FIFO_SE4C3_7", - "CMT_FIFO_L_IMUX38_9", - "CMT_FIFO_L_LOGIC_OUTS7_8", - "CMT_FIFO_L_IMUX15_9", - "CMT_FIFO_L_IMUX42_5", - "CMT_FIFO_EE4A3_9", - "CMT_FIFO_WW4C0_9", - "CMT_FIFO_NW4END0_0", - "CMT_FIFO_L_BYP7_2", - "CMT_FIFO_L_IMUX38_3", - "CMT_FIFO_L_BYP5_1", - "CMT_FIFO_L_LOGIC_OUTS2_2", - "CMT_FIFO_WW4C2_3", - "CMT_FIFO_NW2A2_11", - "CMT_FIFO_L_FAN1_5", - "CMT_FIFO_L_FAN2_11", - "CMT_FIFO_EE2BEG0_0", - "CMT_FIFO_WW2A3_5", - "CMT_FIFO_WL1END3_11", - "CMT_FIFO_L_IMUX10_3", - "CMT_FIFO_L_BYP2_2", - "CMT_FIFO_L_IMUX18_5", - "CMT_FIFO_L_IMUX41_11", - "CMT_FIFO_WR1END1_7", - "CMT_FIFO_NE4C2_4", - "CMT_FIFO_L_BYP5_0", - "CMT_FIFO_L_LOGIC_OUTS8_9", - "CMT_FIFO_L_IMUX20_1", - "CMT_FIFO_L_IMUX24_7", - "CMT_FIFO_L_IMUX10_7", - "CMT_FIFO_L_LOGIC_OUTS17_10", - "CMT_FIFO_WW4C3_2", - "CMT_FIFO_NE4BEG0_7", - "CMT_FIFO_L_BYP7_5", - "CMT_FIFO_SE2A2_11", - "CMT_FIFO_EL1BEG3_5", - "CMT_FIFO_L_IMUX32_0", - "CMT_FIFO_L_BYP4_1", - "CMT_FIFO_SW2A1_7", - "CMT_FIFO_NE2A3_2", - "CMT_FIFO_L_LOGIC_OUTS6_10", - "CMT_FIFO_WW2A3_3", - "CMT_FIFO_SW4A2_2", - "CMT_FIFO_L_IMUX40_0", - "CMT_FIFO_WL1END1_10", - "CMT_FIFO_L_LOGIC_OUTS4_7", - "CMT_FIFO_L_IMUX19_0", - "CMT_FIFO_ER1BEG2_7", - "CMT_FIFO_PHASER_TO_IO_ICLK_11", - "CMT_FIFO_L_FAN0_8", - "CMT_FIFO_EE4B0_3", - "CMT_FIFO_L_IMUX11_4", - "CMT_FIFO_L_IMUX35_8", - "CMT_FIFO_L_LOGIC_OUTS12_5", - "CMT_FIFO_L_IMUX40_5", - "CMT_FIFO_EE2A1_6", - "CMT_FIFO_L_CTRL0_4", - "CMT_FIFO_L_LOGIC_OUTS21_4", - "CMT_FIFO_L_CLK1_11", - "CMT_FIFO_NE4BEG1_0", - "CMT_FIFO_SW4A0_5", - "CMT_IN_FIFO_Q40", - "CMT_FIFO_EE4B2_6", - "CMT_FIFO_L_LOGIC_OUTS8_3", - "CMT_FIFO_L_FAN3_1", - "CMT_FIFO_L_IMUX8_1", - "CMT_OUT_FIFO_Q32", - "CMT_FIFO_L_LOGIC_OUTS21_2", - "CMT_FIFO_SE2A2_2", - "CMT_FIFO_NE4BEG3_4", - "CMT_FIFO_L_LOGIC_OUTS5_11", - "CMT_FIFO_WW4END0_7", - "CMT_FIFO_L_BYP5_6", - "CMT_IN_FIFO_Q71", - "CMT_FIFO_LH8_3", - "CMT_FIFO_L_LOGIC_OUTS20_8", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", - "CMT_FIFO_L_LOGIC_OUTS19_1", - "CMT_FIFO_WW4B1_1", - "CMT_FIFO_NW2A3_2", - "CMT_FIFO_LH2_2", - "CMT_FIFO_SW4A1_7", - "CMT_FIFO_L_IMUX42_0", - "CMT_FIFO_L_IMUX37_8", - "CMT_FIFO_L_IMUX40_1", - "CMT_FIFO_NW4A2_1", - "CMT_FIFO_EE2A2_1", - "CMT_IN_FIFO_Q72", - "CMT_FIFO_WW4C1_5", - "CMT_FIFO_L_IMUX4_3", - "CMT_FIFO_L_IMUX46_10", - "CMT_FIFO_MONITOR_P_3", - "CMT_IN_FIFO_D82", - "CMT_FIFO_SW2A2_4", - "CMT_FIFO_WW4C1_0", - "CMT_FIFO_EE4B0_1", - "CMT_FIFO_EE4B1_4", - "CMT_FIFO_L_IMUX34_0", - "CMT_FIFO_L_IMUX14_7", - "CMT_FIFO_L_IMUX0_2", - "CMT_FIFO_NE4BEG2_10", - "CMT_FIFO_WW4A3_1", - "CMT_FIFO_L_IMUX43_11", - "CMT_FIFO_ER1BEG3_11", - "CMT_FIFO_L_LOGIC_OUTS22_9", - "CMT_FIFO_L_IMUX33_6", - "CMT_IN_FIFO_Q24", - "CMT_FIFO_EE2BEG2_1", - "CMT_FIFO_SE4BEG3_9", - "CMT_FIFO_L_LOGIC_OUTS2_4", - "CMT_FIFO_NW2A0_4", - "CMT_FIFO_EE2BEG0_6", - "CMT_FIFO_L_IMUX29_1", - "CMT_FIFO_L_IMUX31_2", - "CMT_FIFO_NE4BEG0_2", - "CMT_FIFO_NW4A2_4", - "CMT_FIFO_L_LOGIC_OUTS19_9", - "CMT_FIFO_NE4C1_8", - "CMT_IN_FIFO_D70", - "CMT_FIFO_L_LOGIC_OUTS1_8", - "CMT_FIFO_L_LOGIC_OUTS8_11", - "CMT_FIFO_NW2A3_11", - "CMT_FIFO_L_BYP1_9", - "CMT_FIFO_SE2A2_10", - "CMT_FIFO_L_LOGIC_OUTS23_9", - "CMT_FIFO_WW2END2_5", - "CMT_FIFO_L_FAN0_3", - "CMT_FIFO_L_IMUX8_9", - "CMT_OUT_FIFO_Q60", - "CMT_IN_FIFO_Q02", - "CMT_IN_FIFO_Q55", - "CMT_FIFO_EE4BEG3_7", - "CMT_FIFO_SW2A2_10", - "CMT_FIFO_LH10_6", - "CMT_IN_FIFO_Q27", - "CMT_FIFO_WW2END0_7", - "CMT_FIFO_L_IMUX5_6", - "CMT_FIFO_ER1BEG2_9", - "CMT_FIFO_L_IMUX27_11", - "CMT_FIFO_NE2A0_1", - "CMT_FIFO_SW4END2_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_11", - "CMT_FIFO_NW4END1_11", - "CMT_FIFO_SE4C0_3", - "CMT_FIFO_L_FAN3_9", - "CMT_FIFO_L_IMUX12_10", - "CMT_FIFO_L_BYP2_6", - "CMT_FIFO_L_IMUX41_6", - "CMT_FIFO_EE4B1_8", - "CMT_FIFO_WW4C0_2", - "CMT_FIFO_L_IMUX9_9", - "CMT_FIFO_L_FAN6_7", - "CMT_OUT_FIFO_D32", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", - "CMT_FIFO_WL1END1_11", - "CMT_FIFO_WW4END3_3", - "CMT_FIFO_EE4C3_8", - "CMT_FIFO_WW4END0_4", - "CMT_FIFO_L_IMUX34_2", - "CMT_FIFO_EE2BEG1_7", - "CMT_FIFO_L_IMUX22_6", - "CMT_FIFO_NW4A1_4", - "CMT_FIFO_L_LOGIC_OUTS12_8", - "CMT_FIFO_WW2A3_7", - "CMT_FIFO_L_IMUX25_3", - "CMT_FIFO_L_LOGIC_OUTS18_10", - "CMT_FIFO_NE4BEG1_8", - "CMT_FIFO_L_IMUX22_10", - "CMT_FIFO_NE4BEG0_9", - "CMT_FIFO_L_FAN4_8", - "CMT_FIFO_EE4C3_2", - "CMT_FIFO_EE4A3_11", - "CMT_FIFO_LH8_6", - "CMT_FIFO_L_BYP5_2", - "CMT_OUT_FIFO_D72", - "CMT_FIFO_L_IMUX47_6", - "CMT_FIFO_L_IMUX17_6", - "CMT_IN_FIFO_Q77", - "CMT_FIFO_NE4C3_8", - "CMT_FIFO_L_IMUX44_9", - "CMT_FIFO_SE4C3_11", - "CMT_FIFO_WW4A0_7", - "CMT_FIFO_NW4END1_4", - "CMT_FIFO_NE2A2_11", - "CMT_FIFO_L_IMUX34_1", - "CMT_FIFO_NW4A0_7", - "CMT_FIFO_LH7_7", - "CMT_FIFO_L_IMUX34_6", - "CMT_FIFO_NW2A2_0", - "CMT_FIFO_L_IMUX31_8", - "CMT_FIFO_NE2A1_11", - "CMT_FIFO_WW2END3_5", - "CMT_FIFO_L_IMUX8_5", - "CMT_FIFO_SE4C3_6", - "CMT_IN_FIFO_SCANENB", - "CMT_FIFO_NE2A0_7", - "CMT_FIFO_WW4B3_6", - "CMT_FIFO_L_LOGIC_OUTS6_5", - "CMT_OUT_FIFO_D94", - "CMT_FIFO_WW4A2_5", - "CMT_FIFO_NE2A1_4", - "CMT_FIFO_SE4C0_5", - "CMT_FIFO_WW4B0_0", - "CMT_FIFO_EE4B1_1", - "CMT_FIFO_SE4C2_2", - "CMT_FIFO_NE4BEG2_2", - "CMT_FIFO_EE4BEG0_7", - "CMT_FIFO_L_CTRL0_6", - "CMT_FIFO_L_LOGIC_OUTS4_11", - "CMT_FIFO_L_FAN1_7", - "CMT_OUT_FIFO_Q11", - "CMT_FIFO_SW2A0_0", - "CMT_FIFO_NE4C3_9", - "FIFO_DQS_IOTOPHASER_6", - "CMT_FIFO_WW4B1_2", - "CMT_FIFO_EE2BEG0_4", - "CMT_FIFO_L_IMUX38_5", - "CMT_FIFO_SW2A3_5", - "CMT_FIFO_ER1BEG3_4", - "CMT_FIFO_WW4C2_4", - "CMT_FIFO_NE4C0_0", - "CMT_FIFO_L_FAN0_11", - "CMT_FIFO_L_IMUX36_1", - "CMT_OUT_FIFO_D22", - "CMT_OUT_FIFO_SCANOUT3", - "CMT_FIFO_LH4_11", - "CMT_FIFO_L_IMUX42_7", - "CMT_IN_FIFO_WRCLK", - "CMT_FIFO_L_IMUX0_6", - "CMT_FIFO_L_FAN4_10", - "CMT_FIFO_L_IMUX31_4", - "CMT_FIFO_L_IMUX45_7", - "CMT_FIFO_EE4A3_2", - "CMT_FIFO_L_FAN7_4", - "FIFO_DQS_IOTOPHASER_5", - "CMT_FIFO_WW4A3_5", - "CMT_FIFO_WW2A0_7", - "CMT_FIFO_L_LOGIC_OUTS13_3", - "CMT_FIFO_L_IMUX28_9", - "CMT_OUT_FIFO_Q56", - "CMT_FIFO_L_IMUX10_5", - "CMT_OUT_FIFO_D62", - "CMT_FIFO_L_IMUX10_10", - "CMT_FIFO_SW4A1_6", - "CMT_OUT_FIFO_D80", - "CMT_FIFO_SW2A0_2", - "FIFO_DQS_IOTOPHASER_55", - "CMT_FIFO_WW4A1_1", - "CMT_OUT_FIFO_Q53", - "CMT_FIFO_L_LOGIC_OUTS0_6", - "CMT_FIFO_NE4C0_9", - "CMT_FIFO_L_LOGIC_OUTS5_8", - "CMT_FIFO_L_IMUX24_5", - "CMT_FIFO_L_IMUX20_9", - "CMT_FIFO_EL1BEG1_11", - "CMT_FIFO_WW2A2_2", - "CMT_FIFO_L_IMUX35_5", - "CMT_FIFO_LH11_1", - "CMT_FIFO_L_LOGIC_OUTS0_8", - "CMT_OUT_FIFO_Q13", - "CMT_FIFO_L_LOGIC_OUTS23_0", - "CMT_FIFO_NE4C1_11", - "CMT_FIFO_EE2BEG0_7", - "CMT_FIFO_SW2A3_10", - "CMT_FIFO_L_LOGIC_OUTS16_1", - "CMT_FIFO_SW2A1_1", - "CMT_FIFO_L_IMUX44_5", - "CMT_FIFO_LH10_7", - "CMT_FIFO_L_IMUX44_0", - "CMT_FIFO_WW4A0_3", - "CMT_FIFO_NW4END0_11", - "CMT_FIFO_L_CLK1_7", - "CMT_FIFO_EE4BEG0_3", - "CMT_FIFO_NW4END2_1", - "CMT_FIFO_L_FAN7_5", - "CMT_FIFO_L_IMUX36_4", - "CMT_FIFO_SE2A0_10", - "CMT_FIFO_EE4C0_7", - "CMT_FIFO_L_IMUX24_6", - "CMT_FIFO_L_IMUX8_2", - "CMT_FIFO_L_LOGIC_OUTS2_3", - "CMT_FIFO_L_IMUX6_9", - "CMT_FIFO_WR1END0_5", - "CMT_FIFO_WW2A0_11", - "CMT_IN_FIFO_Q97", - "CMT_FIFO_EE4A0_7", - "CMT_FIFO_LH9_9", - "CMT_FIFO_EL1BEG0_7", - "CMT_FIFO_WW2END3_1", - "CMT_FIFO_EE2BEG0_11", - "CMT_FIFO_L_LOGIC_OUTS15_2", - "CMT_FIFO_L_LOGIC_OUTS22_0", - "CMT_FIFO_L_IMUX23_10", - "CMT_FIFO_L_FAN4_5", - "CMT_FIFO_L_IMUX19_7", - "CMT_FIFO_NW4END0_9", - "CMT_FIFO_L_IMUX34_8", - "CMT_FIFO_EE4C0_2", - "CMT_FIFO_SW4END0_11", - "CMT_FIFO_SE2A3_4", - "CMT_FIFO_L_CTRL1_9", - "CMT_FIFO_NW4END3_2", - "CMT_FIFO_L_IMUX37_7", - "CMT_FIFO_L_IMUX39_7", - "CMT_FIFO_LH10_5", - "CMT_IN_FIFO_D63", - "CMT_FIFO_L_IMUX2_4", - "CMT_FIFO_L_IMUX20_8", - "CMT_FIFO_L_LOGIC_OUTS17_8", - "CMT_IN_FIFO_TESTMODEB", - "CMT_FIFO_L_FAN2_10", - "CMT_FIFO_L_IMUX21_8", - "CMT_OUT_FIFO_D24", - "CMT_FIFO_L_BYP5_3", - "CMT_FIFO_L_LOGIC_OUTS21_5", - "CMT_FIFO_L_CLK1_5", - "CMT_FIFO_WW2END1_8", - "CMT_FIFO_EE2A3_10", - "CMT_FIFO_L_IMUX31_3", - "CMT_FIFO_EE2BEG2_0", - "CMT_FIFO_L_IMUX4_2", - "CMT_FIFO_NW4A1_0", - "CMT_FIFO_L_BYP6_2", - "CMT_IN_FIFO_D53", - "CMT_FIFO_L_FAN1_4", - "CMT_FIFO_NE4BEG1_10", - "CMT_OUT_FIFO_D92", - "CMT_OUT_FIFO_D54", - "CMT_FIFO_L_BYP4_7", - "CMT_FIFO_L_LOGIC_OUTS3_4", - "CMT_FIFO_SW4A2_6", - "CMT_OUT_FIFO_Q20", - "CMT_FIFO_SE2A2_9", - "CMT_FIFO_L_IMUX41_4", - "CMT_FIFO_L_IMUX12_1", - "CMT_FIFO_L_IMUX41_0", - "CMT_FIFO_L_LOGIC_OUTS9_8", - "CMT_FIFO_L_LOGIC_OUTS11_8", - "CMT_FIFO_L_IMUX44_2", - "CMT_FIFO_L_CTRL1_0", - "CMT_IN_FIFO_Q20", - "CMT_FIFO_WW4C0_8", - "CMT_FIFO_EL1BEG3_4", - "CMT_FIFO_EE4B0_2", - "CMT_FIFO_WW2A0_1", - "CMT_FIFO_ER1BEG1_6", - "CMT_FIFO_EE4B0_11", - "CMT_FIFO_WW4B1_5", - "CMT_FIFO_PHASER_TO_IO_ICLK_0", - "CMT_FIFO_WW4END0_6", - "CMT_FIFO_WW4END0_10", - "CMT_FIFO_LH7_0", - "CMT_FIFO_L_IMUX35_4", - "CMT_FIFO_WW4B0_10", - "CMT_FIFO_SE4C1_8", - "CMT_FIFO_NE4C0_4", - "CMT_FIFO_L_IMUX1_7", - "CMT_FIFO_L_IMUX41_2", - "CMT_FIFO_L_FAN3_6", - "CMT_FIFO_L_LOGIC_OUTS19_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_8", - "CMT_FIFO_L_IMUX43_5", - "CMT_FIFO_L_IMUX7_2", - "CMT_FIFO_WW2A1_4", - "CMT_FIFO_SE2A3_3", - "CMT_FIFO_SW4END1_6", - "CMT_FIFO_WR1END3_4", - "CMT_FIFO_WW2END0_3", - "CMT_FIFO_SE4BEG1_4", - "CMT_FIFO_L_LOGIC_OUTS6_1", - "CMT_FIFO_NE4BEG3_10", - "CMT_FIFO_L_LOGIC_OUTS10_8", - "CMT_FIFO_NE4C1_4", - "CMT_FIFO_WW2A0_0", - "CMT_FIFO_EE2A3_0", - "CMT_FIFO_SE2A3_1", - "CMT_FIFO_L_IMUX4_6", - "CMT_FIFO_EE4A1_10", - "CMT_FIFO_L_IMUX46_8", - "CMT_FIFO_L_FAN2_0", - "CMT_FIFO_ER1BEG0_8", - "CMT_OUT_FIFO_D31", - "CMT_FIFO_ER1BEG2_1", - "CMT_FIFO_EE4C2_1", - "CMT_FIFO_NE4BEG0_11", - "CMT_FIFO_WR1END0_10", - "CMT_FIFO_LH4_3", - "CMT_FIFO_L_IMUX39_10", - "CMT_FIFO_SW2A2_1", - "CMT_FIFO_EE4C2_6", - "CMT_FIFO_SE4C3_5", - "CMT_FIFO_LH6_1", - "CMT_OUT_FIFO_D10", - "CMT_FIFO_L_IMUX31_0", - "CMT_FIFO_LH6_0", - "CMT_OUT_FIFO_D93", - "CMT_IN_FIFO_D65", - "CMT_FIFO_L_LOGIC_OUTS5_10", - "CMT_FIFO_EE4A0_9", - "CMT_FIFO_L_IMUX18_9", - "CMT_IN_FIFO_Q01", - "CMT_FIFO_LH8_9", - "CMT_FIFO_L_LOGIC_OUTS18_1", - "CMT_FIFO_L_IMUX15_2", - "CMT_FIFO_NW4A1_3", - "CMT_OUT_FIFO_SCANIN3", - "CMT_FIFO_SE4BEG3_5", - "CMT_FIFO_LH5_10", - "CMT_FIFO_L_IMUX12_9", - "CMT_FIFO_SW4END0_5", - "CMT_OUT_FIFO_D00", - "CMT_FIFO_L_BYP2_5", - "CMT_OUT_FIFO_RDEN", - "CMT_FIFO_L_IMUX34_7", - "CMT_FIFO_SW2A2_3", - "CMT_FIFO_L_LOGIC_OUTS14_1", - "CMT_FIFO_L_IMUX45_0", - "CMT_FIFO_L_IMUX5_8", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_1", - "CMT_FIFO_NW2A3_7", - "CMT_FIFO_L_IMUX42_4", - "CMT_FIFO_EE4BEG1_6", - "CMT_FIFO_WW4END3_2", - "CMT_FIFO_LH6_8", - "CMT_FIFO_L_LOGIC_OUTS12_9", - "CMT_FIFO_EE4B1_7", - "CMT_FIFO_L_LOGIC_OUTS0_0", - "CMT_IN_FIFO_WREN", - "CMT_FIFO_L_IMUX25_7", - "CMT_FIFO_WW2END3_7", - "CMT_FIFO_SE4C2_6", - "CMT_FIFO_SW4END3_8", - "CMT_FIFO_L_IMUX23_3", - "CMT_OUT_FIFO_D64", - "CMT_IN_FIFO_Q44", - "CMT_FIFO_L_IMUX16_3", - "CMT_FIFO_WL1END2_7", - "CMT_FIFO_LH7_4", - "CMT_FIFO_L_IMUX28_8", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", - "CMT_OUT_FIFO_D12", - "CMT_FIFO_SE4BEG1_0", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", - "CMT_FIFO_NW2A1_7", - "CMT_FIFO_L_IMUX19_4", - "CMT_IN_FIFO_D54", - "CMT_FIFO_L_IMUX15_7", - "CMT_FIFO_L_IMUX10_8", - "CMT_FIFO_WW2A2_3", - "CMT_FIFO_L_PHASER_WRENABLE", - "CMT_FIFO_SW4A3_7", - "CMT_FIFO_L_IMUX31_6", - "CMT_FIFO_L_IMUX37_2", - "CMT_FIFO_NW2A2_8", - "CMT_FIFO_NW2A3_3", - "CMT_FIFO_EE4A0_3", - "CMT_FIFO_LH3_4", - "CMT_FIFO_SW2A1_2", - "CMT_FIFO_L_IMUX1_1", - "CMT_IN_FIFO_RDEN", - "CMT_FIFO_L_BYP7_7", - "CMT_FIFO_LH11_8", - "CMT_FIFO_L_IMUX21_5", - "CMT_IN_FIFO_Q35", - "CMT_FIFO_L_IMUX24_2", - "CMT_FIFO_NW4A2_8", - "CMT_FIFO_L_IMUX26_3", - "CMT_FIFO_WW2END3_3", - "CMT_FIFO_ER1BEG1_3", - "CMT_FIFO_L_CTRL0_3", - "CMT_FIFO_SE2A0_3", - "CMT_OUT_FIFO_D77", - "CMT_FIFO_WW2A1_2", - "CMT_FIFO_L_IMUX27_7", - "CMT_FIFO_MONITOR_N_7", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", - "CMT_FIFO_LH11_9", - "CMT_OUT_FIFO_D66", - "CMT_FIFO_NW4END1_10", - "CMT_FIFO_WW4A0_10", - "CMT_FIFO_EE4A3_1", - "CMT_FIFO_L_IMUX38_1", - "CMT_FIFO_EE2BEG3_4", - "CMT_FIFO_L_IMUX7_7", - "CMT_FIFO_L_BYP6_8", - "CMT_FIFO_L_IMUX10_9", - "CMT_FIFO_L_BYP7_0", - "CMT_FIFO_L_LOGIC_OUTS22_10", - "CMT_FIFO_L_IMUX6_8", - "CMT_FIFO_L_IMUX6_11", - "CMT_FIFO_SE4BEG1_8", - "CMT_FIFO_L_IMUX7_1", - "CMT_FIFO_WW2END0_0", - "CMT_IN_FIFO_SCANIN2", - "CMT_FIFO_WW4END1_7", - "CMT_FIFO_L_FAN4_11", - "CMT_FIFO_L_IMUX36_8", - "CMT_FIFO_LH5_11", - "CMT_FIFO_MONITOR_N_2", - "CMT_FIFO_WR1END3_2", - "CMT_FIFO_WW4END0_9", - "CMT_FIFO_SE4BEG3_6", - "CMT_FIFO_L_IMUX27_6", - "CMT_FIFO_LH9_3", - "CMT_FIFO_LH10_4", - "CMT_OUT_FIFO_Q41", - "CMT_FIFO_WW2END3_9", - "CMT_FIFO_L_IMUX27_4", - "CMT_OUT_FIFO_Q01", - "CMT_FIFO_L_LOGIC_OUTS5_0", - "CMT_FIFO_L_LOGIC_OUTS12_10", - "CMT_FIFO_EE4C2_10", - "CMT_FIFO_SW4END0_4", - "CMT_IN_FIFO_Q05", - "CMT_FIFO_WR1END2_2", - "CMT_FIFO_L_IMUX40_10", - "CMT_FIFO_EE4B2_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", - "CMT_OUT_FIFO_SCANOUT0", - "CMT_FIFO_EE4A2_9", - "CMT_FIFO_EE4BEG0_2", - "CMT_FIFO_L_BYP1_6", - "CMT_FIFO_EE4A2_6", - "CMT_FIFO_L_IMUX40_3", - "CMT_FIFO_L_IMUX31_11", - "CMT_FIFO_L_BYP2_7", - "CMT_FIFO_SW2A1_4", - "CMT_FIFO_L_LOGIC_OUTS0_11", - "CMT_FIFO_NE4C2_6", - "CMT_FIFO_LH4_7", - "CMT_FIFO_L_IMUX5_2", - "CMT_FIFO_L_IMUX5_11", - "CMT_FIFO_NW4END3_7", - "CMT_FIFO_ER1BEG1_4", - "CMT_FIFO_EE4C3_0", - "CMT_FIFO_WW2A2_11", - "CMT_FIFO_NE2A2_0", - "CMT_FIFO_NW4A3_2", - "CMT_FIFO_L_IMUX26_10", - "CMT_FIFO_LH5_2", - "CMT_FIFO_SE4BEG0_11", - "CMT_FIFO_SE4BEG0_6", - "CMT_FIFO_L_LOGIC_OUTS15_0", - "CMT_FIFO_L_IMUX40_6", - "CMT_IN_FIFO_Q75", - "CMT_FIFO_EE4B0_7", - "CMT_FIFO_EE4BEG1_10", - "CMT_FIFO_NE4BEG2_6", - "CMT_FIFO_WW4A1_6", - "CMT_FIFO_L_LOGIC_OUTS3_1", - "FIFO_DQS_IOTOPHASER_33", - "CMT_FIFO_L_IMUX39_3", - "CMT_FIFO_LH1_0", - "CMT_FIFO_EE4BEG3_9", - "CMT_FIFO_NW4END3_11", - "CMT_FIFO_WW2END1_4", - "CMT_FIFO_L_CLK1_6", - "CMT_FIFO_L_IMUX21_2", - "CMT_FIFO_SE4C2_7", - "CMT_FIFO_L_FAN7_9", - "CMT_FIFO_WW4B1_10", - "CMT_FIFO_EE2A2_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_2", - "CMT_FIFO_SW4A2_1", - "CMT_FIFO_SE4BEG0_0", - "CMT_FIFO_SW4END2_5", - "CMT_FIFO_NW2A1_0", - "CMT_FIFO_NE4BEG2_0", - "CMT_FIFO_EE4BEG2_1", - "CMT_FIFO_WW2A1_7", - "CMT_FIFO_L_FAN0_6", - "CMT_FIFO_L_IMUX43_3", - "CMT_FIFO_L_IMUX14_8", - "CMT_FIFO_EE4A1_6", - "CMT_FIFO_EE2BEG0_8", - "CMT_FIFO_NE4BEG3_1", - "CMT_FIFO_WW4A1_5", - "CMT_FIFO_EE4C1_2", - "CMT_FIFO_L_IMUX17_7", - "CMT_FIFO_NE4C0_10", - "CMT_FIFO_SE4BEG0_2", - "CMT_FIFO_NE2A1_8", - "CMT_FIFO_WW4B2_2", - "CMT_FIFO_NW2A0_6", - "CMT_FIFO_NW4A3_10", - "CMT_FIFO_NE2A0_5", - "CMT_FIFO_NW4A3_5", - "CMT_FIFO_NW2A1_1", - "CMT_FIFO_EE4BEG0_5", - "CMT_FIFO_EE2A0_11", - "CMT_FIFO_WW4A0_11", - "CMT_FIFO_L_IMUX35_7", - "CMT_IN_FIFO_D32", - "CMT_IN_FIFO_D66", - "CMT_FIFO_NW4END0_3", - "CMT_FIFO_L_BYP1_11", - "CMT_FIFO_L_LOGIC_OUTS1_7", - "CMT_FIFO_LH11_4", - "CMT_FIFO_L_LOGIC_OUTS23_6", - "CMT_FIFO_SE2A2_5", - "CMT_IN_FIFO_D67", - "CMT_FIFO_SW4END0_6", - "CMT_FIFO_WL1END3_8", - "CMT_FIFO_LH5_1", - "CMT_FIFO_SE2A3_11", - "CMT_FIFO_L_FAN6_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", - "CMT_FIFO_NW4END0_6", - "CMT_FIFO_EE4A3_5", - "CMT_FIFO_WL1END3_10", - "CMT_OUT_FIFO_D46", - "CMT_FIFO_WR1END2_8", - "CMT_FIFO_L_FAN6_9", - "CMT_FIFO_L_FAN4_4", - "CMT_FIFO_L_LOGIC_OUTS18_7", - "CMT_FIFO_L_BYP4_6", - "CMT_FIFO_L_LOGIC_OUTS7_9", - "CMT_FIFO_L_BYP1_0", - "FIFO_DQS_IOTOPHASER_3", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", - "CMT_FIFO_ER1BEG0_10", - "CMT_FIFO_EE4B2_2", - "CMT_FIFO_NW4A0_10", - "CMT_FIFO_EE4BEG3_8", - "CMT_IN_FIFO_RDCLK", - "CMT_FIFO_L_IMUX13_6", - "CMT_FIFO_NE4BEG3_3", - "CMT_FIFO_L_IMUX35_1", - "CMT_FIFO_L_LOGIC_OUTS10_7", - "CMT_IN_FIFO_Q51", - "CMT_FIFO_L_IMUX18_7", - "CMT_FIFO_L_FAN5_2", - "CMT_FIFO_WW4A3_11", - "CMT_FIFO_L_FAN7_11", - "CMT_FIFO_NE4C1_9", - "CMT_OUT_FIFO_D35", - "CMT_FIFO_EL1BEG2_9", - "CMT_FIFO_L_FAN0_4", - "CMT_FIFO_SE2A3_9", - "CMT_FIFO_WW4C0_6", - "CMT_FIFO_L_IMUX26_4", - "CMT_IN_FIFO_RESET", - "CMT_FIFO_L_LOGIC_OUTS7_1", - "CMT_FIFO_L_IMUX36_2", - "CMT_FIFO_SW4END2_4", - "CMT_FIFO_SW4A2_0", - "CMT_OUT_FIFO_TESTMODEB", - "CMT_FIFO_L_LOGIC_OUTS4_4", - "CMT_FIFO_NE2A1_0", - "CMT_FIFO_NW4END1_3", - "CMT_FIFO_L_LOGIC_OUTS9_10", - "CMT_FIFO_NE4C2_3", - "CMT_FIFO_SE4BEG3_2", - "CMT_FIFO_NW2A0_7", - "CMT_FIFO_WL1END0_0", - "CMT_FIFO_SW4END0_2", - "CMT_FIFO_SE4C1_4", - "CMT_FIFO_EE2A0_6", - "CMT_FIFO_WL1END3_1", - "CMT_FIFO_EE4BEG1_5", - "CMT_FIFO_LH9_5", - "CMT_FIFO_EE4B2_3", - "CMT_FIFO_NE2A2_6", - "CMT_FIFO_L_BYP3_2", - "CMT_FIFO_WW4A2_6", - "CMT_FIFO_EE2BEG0_2", - "CMT_FIFO_L_LOGIC_OUTS16_4", - "CMT_FIFO_EE4A0_11", - "CMT_FIFO_L_IMUX44_7", - "CMT_FIFO_L_BYP2_11", - "CMT_FIFO_L_IMUX18_10", - "CMT_FIFO_NW4END2_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", - "CMT_FIFO_NE4BEG0_4", - "CMT_FIFO_L_FAN0_5", - "CMT_FIFO_EE4B1_3", - "CMT_FIFO_WW4B1_4", - "CMT_FIFO_SW2A0_8", - "CMT_FIFO_LH12_11", - "CMT_FIFO_L_IMUX2_8", - "CMT_FIFO_NE4BEG3_9", - "CMT_FIFO_L_IMUX16_6", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", - "CMT_OUT_FIFO_SCANENB", - "CMT_FIFO_WW4C1_9", - "CMT_FIFO_L_BYP6_3", - "CMT_FIFO_SW4END1_10", - "CMT_FIFO_L_IMUX14_9", - "CMT_OUT_FIFO_D50", - "CMT_FIFO_L_IMUX17_4", - "CMT_FIFO_L_LOGIC_OUTS10_0", - "CMT_FIFO_WW4A0_1", - "CMT_FIFO_SE4BEG0_1", - "CMT_FIFO_L_BYP7_8", - "CMT_FIFO_NW4A2_7", - "CMT_FIFO_LH9_2", - "CMT_FIFO_EE4C2_4", - "CMT_FIFO_EL1BEG1_1", - "CMT_FIFO_L_IMUX34_10", - "CMT_FIFO_PHASER_TO_IO_ICLK_8", - "CMT_FIFO_EL1BEG1_6", - "CMT_FIFO_WW2A0_5", - "CMT_FIFO_WW4END0_11", - "CMT_FIFO_L_IMUX16_7", - "CMT_FIFO_L_IMUX15_10", - "CMT_FIFO_WW4A0_0", - "CMT_FIFO_LH10_1", - "CMT_FIFO_L_IMUX21_9", - "CMT_FIFO_L_IMUX22_1", - "CMT_FIFO_L_IMUX12_4", - "CMT_FIFO_WW4A2_11", - "CMT_FIFO_NW4A2_3", - "CMT_FIFO_EE2A3_5", - "CMT_FIFO_L_IMUX2_6", - "CMT_FIFO_ER1BEG2_8", - "CMT_FIFO_EE2BEG2_9", - "CMT_FIFO_L_IMUX47_2", - "CMT_FIFO_L_IMUX43_6", - "CMT_FIFO_L_LOGIC_OUTS15_4", - "CMT_FIFO_LH3_7", - "CMT_FIFO_L_LOGIC_OUTS14_11", - "CMT_FIFO_L_IMUX15_8", - "CMT_FIFO_EE4BEG0_6", - "CMT_FIFO_L_IMUX46_1", - "CMT_FIFO_L_IMUX37_10", - "CMT_OUT_FIFO_Q90", - "CMT_OUT_FIFO_Q52", - "CMT_FIFO_WR1END3_9", - "CMT_FIFO_SW4END2_3", - "CMT_FIFO_L_IMUX19_11", - "CMT_FIFO_WW4B2_8", - "CMT_FIFO_L_IMUX6_0", - "CMT_FIFO_L_FAN3_7", - "CMT_FIFO_L_IMUX31_7", - "CMT_FIFO_NW2A0_9", - "CMT_FIFO_L_CTRL0_1", - "CMT_FIFO_L_LOGIC_OUTS9_4", - "CMT_FIFO_L_LOGIC_OUTS12_11", - "CMT_FIFO_L_IMUX29_8", - "CMT_FIFO_SW4END3_0", - "CMT_FIFO_L_IMUX34_11", - "CMT_FIFO_L_BYP1_1", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", - "CMT_FIFO_EE4C1_4", - "CMT_IN_FIFO_Q11", - "CMT_FIFO_WR1END0_7", - "CMT_FIFO_L_LOGIC_OUTS17_11", - "CMT_FIFO_SW4A3_0", - "CMT_FIFO_NW4END3_0", - "CMT_FIFO_L_IMUX35_10", - "CMT_FIFO_L_IMUX36_10", - "CMT_FIFO_LH5_4", - "CMT_FIFO_ER1BEG3_3", - "CMT_FIFO_L_BYP3_0", - "CMT_FIFO_SW4END2_8", - "CMT_FIFO_WW2END1_1", - "CMT_FIFO_L_IMUX35_6", - "CMT_FIFO_NE2A2_4", - "CMT_FIFO_L_LOGIC_OUTS14_2", - "CMT_FIFO_NE4BEG0_6", - "CMT_FIFO_L_FAN4_6", - "CMT_FIFO_EL1BEG0_0", - "CMT_IN_FIFO_D20", - "CMT_FIFO_WW4A2_4", - "CMT_FIFO_NW2A0_10", - "CMT_FIFO_L_FAN0_0", - "CMT_FIFO_EE4B2_1", - "CMT_FIFO_WW4A3_4", - "CMT_FIFO_WR1END3_5", - "CMT_FIFO_SE4BEG2_4", - "CMT_FIFO_LH7_9", - "CMT_IN_FIFO_D57", - "CMT_FIFO_L_CLK0_4", - "CMT_FIFO_L_CTRL0_0", - "CMT_OUT_FIFO_D95", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", - "CMT_FIFO_L_IMUX25_6", - "CMT_FIFO_EE4BEG0_1", - "CMT_FIFO_EL1BEG2_5", - "CMT_FIFO_SW2A3_6", - "CMT_FIFO_L_IMUX30_0", - "CMT_OUT_FIFO_D37", - "CMT_FIFO_WR1END0_1", - "CMT_FIFO_L_IMUX2_1", - "CMT_IN_FIFO_Q57", - "CMT_FIFO_WW4C1_4", - "CMT_FIFO_LH1_2", - "CMT_FIFO_L_IMUX12_0", - "CMT_FIFO_NW2A3_5", - "CMT_FIFO_SE4BEG0_3", - "CMT_FIFO_WW4A3_2", - "CMT_FIFO_LH6_6", - "CMT_IN_FIFO_SCANIN0", - "CMT_FIFO_L_CLK0_8", - "CMT_FIFO_EL1BEG1_9", - "CMT_FIFO_EE4A1_11", - "CMT_FIFO_WL1END3_4", - "CMT_FIFO_SW4END3_10", - "CMT_FIFO_EL1BEG0_8", - "CMT_FIFO_L_IMUX26_9", - "CMT_FIFO_WW2A2_7", - "CMT_FIFO_WW4END1_0", - "CMT_FIFO_L_IMUX18_4", - "CMT_FIFO_L_IMUX13_9", - "CMT_FIFO_NW2A0_0", - "CMT_FIFO_L_IMUX27_5", - "CMT_FIFO_SE2A2_0", - "CMT_FIFO_L_IMUX33_9", - "CMT_FIFO_EE4B3_11", - "CMT_FIFO_ER1BEG3_9", - "CMT_FIFO_NW4A1_5", - "CMT_OUT_FIFO_D02", - "CMT_FIFO_L_LOGIC_OUTS20_6", - "CMT_FIFO_L_FAN6_4", - "CMT_FIFO_NW2A3_8", - "CMT_FIFO_WL1END0_1", - "CMT_FIFO_WL1END1_7", - "CMT_FIFO_L_LOGIC_OUTS22_6", - "CMT_FIFO_NE2A0_6", - "CMT_FIFO_L_IMUX44_1", - "CMT_FIFO_LH2_10", - "CMT_FIFO_EE4A0_6", - "CMT_FIFO_L_LOGIC_OUTS10_6", - "CMT_FIFO_SE2A3_8", - "CMT_FIFO_NE4C1_10", - "CMT_FIFO_WR1END0_8", - "CMT_FIFO_L_IMUX27_1", - "CMT_FIFO_L_LOGIC_OUTS11_10", - "CMT_FIFO_LH3_10", - "CMT_FIFO_NE4C0_7", - "CMT_FIFO_EE2BEG1_8", - "CMT_FIFO_WW4END2_7", - "CMT_FIFO_L_IMUX0_3", - "CMT_IN_FIFO_EMPTY", - "CMT_IN_FIFO_ALMOSTFULL", - "CMT_OUT_FIFO_D42", - "CMT_FIFO_WW4END0_5", - "CMT_FIFO_EE4A1_8", - "CMT_FIFO_EL1BEG0_2", - "CMT_FIFO_L_BYP0_10", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", - "CMT_FIFO_EE4A3_10", - "CMT_FIFO_L_IMUX13_7", - "CMT_FIFO_L_IMUX6_1", - "CMT_FIFO_SE4C0_9", - "CMT_FIFO_SE4C2_5", - "CMT_FIFO_WW4C2_10", - "CMT_FIFO_L_IMUX25_1", - "CMT_FIFO_NW4A0_2", - "CMT_FIFO_L_IMUX8_11", - "CMT_FIFO_L_LOGIC_OUTS13_9", - "CMT_FIFO_SE4BEG3_0", - "CMT_FIFO_NE4BEG2_5", - "CMT_FIFO_L_LOGIC_OUTS16_5", - "FIFO_DQS_IOTOPHASER_22", - "CMT_FIFO_WL1END0_11", - "CMT_FIFO_NE4BEG0_3", - "CMT_FIFO_WW4C2_6", - "CMT_FIFO_WL1END1_3", - "CMT_FIFO_EL1BEG2_8", - "CMT_FIFO_L_IMUX11_3", - "CMT_FIFO_LH2_3", - "CMT_IN_FIFO_Q46", - "CMT_FIFO_L_CTRL1_11", - "CMT_FIFO_SW2A1_0" - ], - "sites": [ - { - "prefix": "OUT_FIFO", - "y_coord": 0, - "type": "OUT_FIFO", - "site_pins": { - "D92": "CMT_OUT_FIFO_D92", - "Q53": "CMT_OUT_FIFO_Q53", - "D12": "CMT_OUT_FIFO_D12", - "RDCLK": "CMT_OUT_FIFO_RDCLK", - "D82": "CMT_OUT_FIFO_D82", - "D30": "CMT_OUT_FIFO_D30", - "Q01": "CMT_OUT_FIFO_Q01", - "Q57": "CMT_OUT_FIFO_Q57", - "D14": "CMT_OUT_FIFO_D14", - "Q11": "CMT_OUT_FIFO_Q11", - "D05": "CMT_OUT_FIFO_D05", - "Q40": "CMT_OUT_FIFO_Q40", - "D21": "CMT_OUT_FIFO_D21", - "TESTWRITEDISB": "CMT_OUT_FIFO_TESTWRITEDISB", - "D35": "CMT_OUT_FIFO_D35", - "D62": "CMT_OUT_FIFO_D62", - "Q82": "CMT_OUT_FIFO_Q82", - "D26": "CMT_OUT_FIFO_D26", - "Q43": "CMT_OUT_FIFO_Q43", - "Q90": "CMT_OUT_FIFO_Q90", - "D71": "CMT_OUT_FIFO_D71", - "Q00": "CMT_OUT_FIFO_Q00", - "D41": "CMT_OUT_FIFO_D41", - "D80": "CMT_OUT_FIFO_D80", - "SCANIN2": "CMT_OUT_FIFO_SCANIN2", - "D51": "CMT_OUT_FIFO_D51", - "D93": "CMT_OUT_FIFO_D93", - "D47": "CMT_OUT_FIFO_D47", - "D07": "CMT_OUT_FIFO_D07", - "Q93": "CMT_OUT_FIFO_Q93", - "Q51": "CMT_OUT_FIFO_Q51", - "Q91": "CMT_OUT_FIFO_Q91", - "D45": "CMT_OUT_FIFO_D45", - "Q42": "CMT_OUT_FIFO_Q42", - "Q80": "CMT_OUT_FIFO_Q80", - "D44": "CMT_OUT_FIFO_D44", - "D42": "CMT_OUT_FIFO_D42", - "Q10": "CMT_OUT_FIFO_Q10", - "SCANIN1": "CMT_OUT_FIFO_SCANIN1", - "Q52": "CMT_OUT_FIFO_Q52", - "D94": "CMT_OUT_FIFO_D94", - "D83": "CMT_OUT_FIFO_D83", - "Q66": "CMT_OUT_FIFO_Q66", - "ALMOSTEMPTY": "CMT_OUT_FIFO_ALMOSTEMPTY", - "Q23": "CMT_OUT_FIFO_Q23", - "Q73": "CMT_OUT_FIFO_Q73", - "D22": "CMT_OUT_FIFO_D22", - "D76": "CMT_OUT_FIFO_D76", - "D86": "CMT_OUT_FIFO_D86", - "D36": "CMT_OUT_FIFO_D36", - "Q54": "CMT_OUT_FIFO_Q54", - "Q83": "CMT_OUT_FIFO_Q83", - "D87": "CMT_OUT_FIFO_D87", - "Q56": "CMT_OUT_FIFO_Q56", - "D64": "CMT_OUT_FIFO_D64", - "D13": "CMT_OUT_FIFO_D13", - "D81": "CMT_OUT_FIFO_D81", - "D33": "CMT_OUT_FIFO_D33", - "D65": "CMT_OUT_FIFO_D65", - "D96": "CMT_OUT_FIFO_D96", - "Q12": "CMT_OUT_FIFO_Q12", - "Q62": "CMT_OUT_FIFO_Q62", - "D91": "CMT_OUT_FIFO_D91", - "TESTREADDISB": "CMT_OUT_FIFO_TESTREADDISB", - "D24": "CMT_OUT_FIFO_D24", - "D46": "CMT_OUT_FIFO_D46", - "D57": "CMT_OUT_FIFO_D57", - "D52": "CMT_OUT_FIFO_D52", - "D97": "CMT_OUT_FIFO_D97", - "Q30": "CMT_OUT_FIFO_Q30", - "Q63": "CMT_OUT_FIFO_Q63", - "D25": "CMT_OUT_FIFO_D25", - "D01": "CMT_OUT_FIFO_D01", - "Q02": "CMT_OUT_FIFO_Q02", - "Q71": "CMT_OUT_FIFO_Q71", - "TESTMODEB": "CMT_OUT_FIFO_TESTMODEB", - "RESET": "CMT_OUT_FIFO_RESET", - "D00": "CMT_OUT_FIFO_D00", - "D60": "CMT_OUT_FIFO_D60", - "D32": "CMT_OUT_FIFO_D32", - "D04": "CMT_OUT_FIFO_D04", - "D16": "CMT_OUT_FIFO_D16", - "D02": "CMT_OUT_FIFO_D02", - "RDEN": "CMT_OUT_FIFO_RDEN", - "D77": "CMT_OUT_FIFO_D77", - "SCANOUT0": "CMT_OUT_FIFO_SCANOUT0", - "D54": "CMT_OUT_FIFO_D54", - "D17": "CMT_OUT_FIFO_D17", - "FULL": "CMT_OUT_FIFO_FULL", - "D90": "CMT_OUT_FIFO_D90", - "Q65": "CMT_OUT_FIFO_Q65", - "ALMOSTFULL": "CMT_OUT_FIFO_ALMOSTFULL", - "Q61": "CMT_OUT_FIFO_Q61", - "D73": "CMT_OUT_FIFO_D73", - "SCANOUT3": "CMT_OUT_FIFO_SCANOUT3", - "SCANENB": "CMT_OUT_FIFO_SCANENB", - "D37": "CMT_OUT_FIFO_D37", - "D70": "CMT_OUT_FIFO_D70", - "Q32": "CMT_OUT_FIFO_Q32", - "D53": "CMT_OUT_FIFO_D53", - "WREN": "CMT_OUT_FIFO_WREN", - "Q20": "CMT_OUT_FIFO_Q20", - "D67": "CMT_OUT_FIFO_D67", - "D56": "CMT_OUT_FIFO_D56", - "SCANIN0": "CMT_OUT_FIFO_SCANIN0", - "D03": "CMT_OUT_FIFO_D03", - "D74": "CMT_OUT_FIFO_D74", - "D06": "CMT_OUT_FIFO_D06", - "D11": "CMT_OUT_FIFO_D11", - "WRCLK": "CMT_OUT_FIFO_WRCLK", - "D66": "CMT_OUT_FIFO_D66", - "D63": "CMT_OUT_FIFO_D63", - "Q55": "CMT_OUT_FIFO_Q55", - "D10": "CMT_OUT_FIFO_D10", - "D85": "CMT_OUT_FIFO_D85", - "D40": "CMT_OUT_FIFO_D40", - "EMPTY": "CMT_OUT_FIFO_EMPTY", - "Q22": "CMT_OUT_FIFO_Q22", - "Q92": "CMT_OUT_FIFO_Q92", - "D15": "CMT_OUT_FIFO_D15", - "D95": "CMT_OUT_FIFO_D95", - "SCANOUT1": "CMT_OUT_FIFO_SCANOUT1", - "D34": "CMT_OUT_FIFO_D34", - "D31": "CMT_OUT_FIFO_D31", - "SCANIN3": "CMT_OUT_FIFO_SCANIN3", - "Q64": "CMT_OUT_FIFO_Q64", - "D50": "CMT_OUT_FIFO_D50", - "D61": "CMT_OUT_FIFO_D61", - "D27": "CMT_OUT_FIFO_D27", - "Q50": "CMT_OUT_FIFO_Q50", - "Q31": "CMT_OUT_FIFO_Q31", - "D72": "CMT_OUT_FIFO_D72", - "D20": "CMT_OUT_FIFO_D20", - "Q03": "CMT_OUT_FIFO_Q03", - "D43": "CMT_OUT_FIFO_D43", - "D55": "CMT_OUT_FIFO_D55", - "Q70": "CMT_OUT_FIFO_Q70", - "D75": "CMT_OUT_FIFO_D75", - "Q67": "CMT_OUT_FIFO_Q67", - "Q13": "CMT_OUT_FIFO_Q13", - "Q81": "CMT_OUT_FIFO_Q81", - "Q60": "CMT_OUT_FIFO_Q60", - "D84": "CMT_OUT_FIFO_D84", - "Q41": "CMT_OUT_FIFO_Q41", - "SCANOUT2": "CMT_OUT_FIFO_SCANOUT2", - "Q33": "CMT_OUT_FIFO_Q33", - "D23": "CMT_OUT_FIFO_D23", - "Q72": "CMT_OUT_FIFO_Q72", - "Q21": "CMT_OUT_FIFO_Q21" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IN_FIFO", - "y_coord": 0, - "type": "IN_FIFO", - "site_pins": { - "D92": "CMT_IN_FIFO_D92", - "Q53": "CMT_IN_FIFO_Q53", - "D12": "CMT_IN_FIFO_D12", - "SCANIN1": "CMT_IN_FIFO_SCANIN1", - "D82": "CMT_IN_FIFO_D82", - "D30": "CMT_IN_FIFO_D30", - "Q01": "CMT_IN_FIFO_Q01", - "Q07": "CMT_IN_FIFO_Q07", - "Q37": "CMT_IN_FIFO_Q37", - "Q57": "CMT_IN_FIFO_Q57", - "Q75": "CMT_IN_FIFO_Q75", - "Q40": "CMT_IN_FIFO_Q40", - "D21": "CMT_IN_FIFO_D21", - "TESTWRITEDISB": "CMT_IN_FIFO_TESTWRITEDISB", - "D66": "CMT_IN_FIFO_D66", - "D62": "CMT_IN_FIFO_D62", - "Q82": "CMT_IN_FIFO_Q82", - "D50": "CMT_IN_FIFO_D50", - "D91": "CMT_IN_FIFO_D91", - "Q90": "CMT_IN_FIFO_Q90", - "D71": "CMT_IN_FIFO_D71", - "Q00": "CMT_IN_FIFO_Q00", - "D41": "CMT_IN_FIFO_D41", - "D80": "CMT_IN_FIFO_D80", - "SCANIN2": "CMT_IN_FIFO_SCANIN2", - "D51": "CMT_IN_FIFO_D51", - "Q24": "CMT_IN_FIFO_Q24", - "D93": "CMT_IN_FIFO_D93", - "Q93": "CMT_IN_FIFO_Q93", - "D13": "CMT_IN_FIFO_D13", - "Q91": "CMT_IN_FIFO_Q91", - "Q42": "CMT_IN_FIFO_Q42", - "Q36": "CMT_IN_FIFO_Q36", - "Q80": "CMT_IN_FIFO_Q80", - "D42": "CMT_IN_FIFO_D42", - "Q10": "CMT_IN_FIFO_Q10", - "RDCLK": "CMT_IN_FIFO_RDCLK", - "Q52": "CMT_IN_FIFO_Q52", - "Q86": "CMT_IN_FIFO_Q86", - "Q84": "CMT_IN_FIFO_Q84", - "D70": "CMT_IN_FIFO_D70", - "D83": "CMT_IN_FIFO_D83", - "Q74": "CMT_IN_FIFO_Q74", - "Q15": "CMT_IN_FIFO_Q15", - "Q26": "CMT_IN_FIFO_Q26", - "Q23": "CMT_IN_FIFO_Q23", - "Q73": "CMT_IN_FIFO_Q73", - "D22": "CMT_IN_FIFO_D22", - "Q04": "CMT_IN_FIFO_Q04", - "Q54": "CMT_IN_FIFO_Q54", - "Q83": "CMT_IN_FIFO_Q83", - "Q20": "CMT_IN_FIFO_Q20", - "Q56": "CMT_IN_FIFO_Q56", - "D64": "CMT_IN_FIFO_D64", - "Q51": "CMT_IN_FIFO_Q51", - "Q87": "CMT_IN_FIFO_Q87", - "D81": "CMT_IN_FIFO_D81", - "D33": "CMT_IN_FIFO_D33", - "D65": "CMT_IN_FIFO_D65", - "Q94": "CMT_IN_FIFO_Q94", - "Q06": "CMT_IN_FIFO_Q06", - "Q12": "CMT_IN_FIFO_Q12", - "Q62": "CMT_IN_FIFO_Q62", - "TESTREADDISB": "CMT_IN_FIFO_TESTREADDISB", - "Q17": "CMT_IN_FIFO_Q17", - "D57": "CMT_IN_FIFO_D57", - "D52": "CMT_IN_FIFO_D52", - "Q46": "CMT_IN_FIFO_Q46", - "Q30": "CMT_IN_FIFO_Q30", - "Q25": "CMT_IN_FIFO_Q25", - "Q63": "CMT_IN_FIFO_Q63", - "D01": "CMT_IN_FIFO_D01", - "Q02": "CMT_IN_FIFO_Q02", - "Q71": "CMT_IN_FIFO_Q71", - "TESTMODEB": "CMT_IN_FIFO_TESTMODEB", - "RESET": "CMT_IN_FIFO_RESET", - "D00": "CMT_IN_FIFO_D00", - "Q27": "CMT_IN_FIFO_Q27", - "Q16": "CMT_IN_FIFO_Q16", - "D60": "CMT_IN_FIFO_D60", - "D32": "CMT_IN_FIFO_D32", - "Q14": "CMT_IN_FIFO_Q14", - "D02": "CMT_IN_FIFO_D02", - "RDEN": "CMT_IN_FIFO_RDEN", - "SCANOUT0": "CMT_IN_FIFO_SCANOUT0", - "D54": "CMT_IN_FIFO_D54", - "FULL": "CMT_IN_FIFO_FULL", - "D90": "CMT_IN_FIFO_D90", - "Q76": "CMT_IN_FIFO_Q76", - "Q65": "CMT_IN_FIFO_Q65", - "Q47": "CMT_IN_FIFO_Q47", - "ALMOSTFULL": "CMT_IN_FIFO_ALMOSTFULL", - "Q61": "CMT_IN_FIFO_Q61", - "D73": "CMT_IN_FIFO_D73", - "SCANOUT3": "CMT_IN_FIFO_SCANOUT3", - "SCANENB": "CMT_IN_FIFO_SCANENB", - "Q32": "CMT_IN_FIFO_Q32", - "D53": "CMT_IN_FIFO_D53", - "WREN": "CMT_IN_FIFO_WREN", - "Q11": "CMT_IN_FIFO_Q11", - "D67": "CMT_IN_FIFO_D67", - "D56": "CMT_IN_FIFO_D56", - "SCANIN0": "CMT_IN_FIFO_SCANIN0", - "D03": "CMT_IN_FIFO_D03", - "Q66": "CMT_IN_FIFO_Q66", - "D11": "CMT_IN_FIFO_D11", - "Q77": "CMT_IN_FIFO_Q77", - "WRCLK": "CMT_IN_FIFO_WRCLK", - "D63": "CMT_IN_FIFO_D63", - "Q55": "CMT_IN_FIFO_Q55", - "D10": "CMT_IN_FIFO_D10", - "Q45": "CMT_IN_FIFO_Q45", - "Q96": "CMT_IN_FIFO_Q96", - "D40": "CMT_IN_FIFO_D40", - "EMPTY": "CMT_IN_FIFO_EMPTY", - "Q22": "CMT_IN_FIFO_Q22", - "Q92": "CMT_IN_FIFO_Q92", - "Q95": "CMT_IN_FIFO_Q95", - "ALMOSTEMPTY": "CMT_IN_FIFO_ALMOSTEMPTY", - "Q33": "CMT_IN_FIFO_Q33", - "SCANOUT1": "CMT_IN_FIFO_SCANOUT1", - "D31": "CMT_IN_FIFO_D31", - "SCANIN3": "CMT_IN_FIFO_SCANIN3", - "Q35": "CMT_IN_FIFO_Q35", - "Q43": "CMT_IN_FIFO_Q43", - "D61": "CMT_IN_FIFO_D61", - "Q85": "CMT_IN_FIFO_Q85", - "Q50": "CMT_IN_FIFO_Q50", - "Q31": "CMT_IN_FIFO_Q31", - "D72": "CMT_IN_FIFO_D72", - "Q34": "CMT_IN_FIFO_Q34", - "D20": "CMT_IN_FIFO_D20", - "Q03": "CMT_IN_FIFO_Q03", - "D43": "CMT_IN_FIFO_D43", - "D55": "CMT_IN_FIFO_D55", - "Q70": "CMT_IN_FIFO_Q70", - "Q67": "CMT_IN_FIFO_Q67", - "Q13": "CMT_IN_FIFO_Q13", - "Q81": "CMT_IN_FIFO_Q81", - "Q64": "CMT_IN_FIFO_Q64", - "Q60": "CMT_IN_FIFO_Q60", - "Q97": "CMT_IN_FIFO_Q97", - "Q41": "CMT_IN_FIFO_Q41", - "SCANOUT2": "CMT_IN_FIFO_SCANOUT2", - "Q05": "CMT_IN_FIFO_Q05", - "D23": "CMT_IN_FIFO_D23", - "Q72": "CMT_IN_FIFO_Q72", - "Q21": "CMT_IN_FIFO_Q21", - "Q44": "CMT_IN_FIFO_Q44" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "CMT_FIFO_R.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { + "CMT_FIFO_R.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3", + "src_wire": "CMT_OUT_FIFO_Q00", "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q37", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q40", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q93", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D86", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q26", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q30", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D53", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D41", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D04", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D21", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q33", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS11_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_10", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q82", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q85", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D24", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q74", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q93", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D22", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q42", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D55", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_6", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D52", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RESET", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_6", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D64", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_8", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D82", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q71", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q32", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q54", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q41", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q92", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q03", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D90", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q76", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_0->CMT_IN_FIFO_D02": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D02", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q95", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D42", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q12", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_11->CMT_IN_FIFO_D93": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D93", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D61", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_8", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D73", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D16", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D70", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_WRCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_PHASER_WRCLK", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q43", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS19_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_9", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q71", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q35", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D74", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_4", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q43", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q57", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D35", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D71", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q36", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q16", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q12", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_RDEN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_7", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D22", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q21", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q24", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D94", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D56", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_6", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D50", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D33", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q66", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q81", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_FULL", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q73", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_WREN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_6", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q34", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q50", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q31", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D97", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q44", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q00", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D55", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D67", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_7", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q27", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS19_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_5", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q51", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q45", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D53", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q86", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D31", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D92", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D72", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D77", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D05", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS19_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q55", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q04", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q23", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_WREN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_PHASER_WRENABLE", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D20", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D02", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D10", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D32", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q77", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D83", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_WRCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_CLK0_6", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D17", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D80", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D40", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D26", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q81", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D12", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q30", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q32", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS11_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_5", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q52", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS11_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_9", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q72", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D30", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_WRCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_CLK1_6", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q70", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q22", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q21", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS20_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q73", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D11", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D21", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D70", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q46", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D61", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_8", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D03", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q20", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D52", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q63", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q94", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D30", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_RDCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_CLK1_7", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q42", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D13", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D00", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RDEN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_7", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS20_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q57", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D87", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q02", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q41", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q55", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q07", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q01", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D42", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D25", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D36", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS22_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_7", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q64", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_EMPTY", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS20_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_5", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q53", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q75", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q13", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D60", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_8", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q92", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q67", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_FULL", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS11_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_8", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q62", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q53", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q52", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS20_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_8", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q63", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D03", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_WREN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_6", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D93", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q84", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS22_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_11", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q90", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q64", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D92", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D47", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS20_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_7", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q67", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q56", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q62", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D46", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q23", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D00", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS20_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_10", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q83", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D54", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_6", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D01", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D90", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D80", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_3->CMT_IN_FIFO_D32": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D32", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q33", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS19_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_8", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q61", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS22_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_5", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q50", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D34", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D63", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_8", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D51", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D06", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_0", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D85", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D81", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D43", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D43", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_5->CMT_OUT_FIFO_D56": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D56", - "is_directional": "1", "src_wire": "CMT_FIFO_L_IMUX7_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_RESET", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D56" }, - "CMT_FIFO_R.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { + "CMT_FIFO_R.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11", + "src_wire": "CMT_IN_FIFO_Q73", "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q91", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { + "CMT_FIFO_R.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D76", + "src_wire": "CMT_IN_FIFO_Q95", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q00", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RDCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_PHASER_RDCLK", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q05", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D82", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D11", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS22_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_9", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q70", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D41", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q25", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q22", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS22_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_8", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q60", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_ALMOSTFULL", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q14", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q61", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D20", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D45", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D67", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_8", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D44", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q20", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q72", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS11_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_7", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q66", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D65", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_7", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q47", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D27", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D75", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS11_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q56", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q65", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS19_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_7", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q65", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_ALMOSTFULL", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D62", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_8", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D72", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RDEN", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_PHASER_RDENABLE", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_RDCLK", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_CLK0_7", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q06", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D13", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q01", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q17", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q87", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D95", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_1->CMT_IN_FIFO_D10": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D10", - "is_directional": "1", "src_wire": "CMT_FIFO_L_IMUX26_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0", "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q03", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D10" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D64", + "src_wire": "CMT_FIFO_L_IMUX36_2", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D22" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { + "CMT_FIFO_R.CMT_OUT_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS11_5": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D01", + "src_wire": "CMT_OUT_FIFO_Q52", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_5" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { + "CMT_FIFO_R.CMT_OUT_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS22_11": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D65", + "src_wire": "CMT_OUT_FIFO_Q90", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_11" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { + "CMT_FIFO_R.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D57", + "src_wire": "CMT_IN_FIFO_Q66", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { + "CMT_FIFO_R.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D23", + "src_wire": "CMT_OUT_FIFO_Q32", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { + "CMT_FIFO_R.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D60", + "src_wire": "CMT_OUT_FIFO_Q30", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX28_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { + "CMT_FIFO_R.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D81", + "src_wire": "CMT_IN_FIFO_Q04", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q31", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D96", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q91", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D84", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q83", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D57", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D62", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX39_8", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_EMPTY", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D37", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q60", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS5_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q82", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q15", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q02", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D31", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_3", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D91", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX40_11", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D40", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_4", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D23", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_2", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D54", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX12_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q80", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q90", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS22_10": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10", - "is_directional": "1", "src_wire": "CMT_OUT_FIFO_Q80", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D33", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D91", + "src_wire": "CMT_FIFO_L_IMUX7_0", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D06" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { + "CMT_FIFO_R.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D63", + "src_wire": "CMT_IN_FIFO_Q01", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0" }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D12", + "src_wire": "CMT_FIFO_L_IMUX7_6", "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D83", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX42_10", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D66", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX36_7", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX38_9->CMT_OUT_FIFO_D73": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D73", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX38_9", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D15", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX5_1", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_OUT_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS22_6": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_6", - "is_directional": "1", - "src_wire": "CMT_OUT_FIFO_Q54", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { - "can_invert": "0", - "dst_wire": "CMT_IN_FIFO_D50", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX26_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D66", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX7_8", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q96", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q51", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D51", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX21_5", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { - "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11", - "is_directional": "1", - "src_wire": "CMT_IN_FIFO_Q97", - "is_pseudo": "0" - }, - "CMT_FIFO_R.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { - "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D07", - "is_directional": "1", - "src_wire": "CMT_FIFO_L_IMUX6_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WREN" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_9->CMT_OUT_FIFO_D71": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D71", - "is_directional": "1", "src_wire": "CMT_FIFO_L_IMUX21_9", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D71" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D30" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D62" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D41" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_3->CMT_IN_FIFO_D32": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D32" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS20_10": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q83", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_10" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D46" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D13" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q74", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D15" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D55" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_ALMOSTFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RESET" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D97" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D70" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D25" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D45" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS19_7": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q65", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_7" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D73" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS22_4": { "can_invert": "0", - "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4", - "is_directional": "1", "src_wire": "CMT_OUT_FIFO_Q40", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_WREN" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D80" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D00" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D22" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q65", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D02" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS20_7": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q67", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_7" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q87", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D16" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D31" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D80" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q91", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_EMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D40" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS19_8": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_8" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_FULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D11" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q70", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D90" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS20_9": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q73", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D76" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q67", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D81" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D62" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D43" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D27" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q83", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q84", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D03" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D96" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D10" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D20" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D32" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D01" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D23" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D03" + }, + "CMT_FIFO_R.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_EMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D67" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q71", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D85" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D21" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D44" + }, + "CMT_FIFO_R.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D71" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D61" + }, + "CMT_FIFO_R.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_PHASER_RDENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDEN" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q92", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D63" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D56" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D64" + }, + "CMT_FIFO_R.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_CLK1_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WRCLK" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS5_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q82", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D20" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D33" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D83" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D57" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_9->CMT_OUT_FIFO_D73": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D73" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D52" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q97", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS19_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_6" + }, + "CMT_FIFO_R.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_CLK0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDCLK" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D00" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D82" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D30" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D37" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D51" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D66" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D01" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS22_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q54", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_6" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS20_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_6" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS20_8": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_8" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D12" + }, + "CMT_FIFO_R.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_CLK0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_WRCLK" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D05" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D53" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q77", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D50" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D23" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D75" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D42" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D92" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D33" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D74" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D87" + }, + "CMT_FIFO_R.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_PHASER_RDCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDCLK" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS11_7": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q66", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_7" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D24" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q81", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS22_7": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q64", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_7" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D43" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q52", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D11" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D66" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D21" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D60" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q06", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q02", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RDEN" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q05", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D26" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_11->CMT_IN_FIFO_D93": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D93" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q91", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D12" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D34" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS22_9": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q70", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_9" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D36" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q03", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D82" + }, + "CMT_FIFO_R.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_PHASER_WRCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WRCLK" + }, + "CMT_FIFO_R.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_PHASER_WRENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_WREN" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q85", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D42" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS11_9": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q72", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_1->CMT_OUT_FIFO_D14": { "can_invert": "0", - "dst_wire": "CMT_OUT_FIFO_D14", - "is_directional": "1", "src_wire": "CMT_FIFO_L_IMUX12_1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D14" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D93" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q94", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D72" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX38_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D53" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q81", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D81" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D72" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX39_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D92" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D55" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS11_6": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_6" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D50" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D54" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D65" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q86", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D95" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS19_9": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q71", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_9" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D04" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D31" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q96", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q72", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D91" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D35" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_0->CMT_IN_FIFO_D02": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D02" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D13" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D47" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q01", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS20_5": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_5" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q93", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D41" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D65" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D64" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D63" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q00", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX7_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D86" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D61" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS19_5": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_5" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q02", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D54" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q80", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D94" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX36_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D52" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D83" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX42_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D67" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_4" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D40" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS22_8": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_8" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D90" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX40_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D51" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q03", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q07", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q75", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9" + }, + "CMT_FIFO_R.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_CLK1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RDCLK" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q64", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS22_5": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_5" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX5_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_RESET" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q54", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q92", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D77" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX12_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D84" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX28_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D60" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D07" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4" + }, + "CMT_FIFO_R.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_ALMOSTFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7" + }, + "CMT_FIFO_R.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_FULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D17" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D57" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS11_8": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_8" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX21_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_D91" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX6_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_OUT_FIFO_RDEN" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q76", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9" + }, + "CMT_FIFO_R.CMT_OUT_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS11_10": { + "can_invert": "0", + "src_wire": "CMT_OUT_FIFO_Q82", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_10" + }, + "CMT_FIFO_R.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { + "can_invert": "0", + "src_wire": "CMT_FIFO_L_IMUX26_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_IN_FIFO_D70" + }, + "CMT_FIFO_R.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { + "can_invert": "0", + "src_wire": "CMT_IN_FIFO_Q93", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11" } }, - "tile_type": "CMT_FIFO_R" + "wires": [ + "CMT_FIFO_L_LOGIC_OUTS22_9", + "CMT_FIFO_NW4A0_2", + "CMT_FIFO_EE4C1_4", + "CMT_FIFO_ER1BEG0_5", + "CMT_FIFO_SE2A3_0", + "CMT_FIFO_L_LOGIC_OUTS16_11", + "CMT_FIFO_L_BYP3_9", + "CMT_FIFO_L_IMUX15_5", + "CMT_FIFO_WW4A1_1", + "CMT_FIFO_L_IMUX12_9", + "CMT_FIFO_L_FAN1_6", + "CMT_FIFO_EE4A2_3", + "CMT_FIFO_SW4END1_1", + "CMT_FIFO_L_IMUX22_3", + "CMT_FIFO_SW2A2_6", + "CMT_FIFO_WL1END0_11", + "CMT_FIFO_L_IMUX40_5", + "CMT_FIFO_EE4B0_4", + "CMT_FIFO_L_IMUX44_5", + "CMT_FIFO_NE4BEG1_5", + "CMT_OUT_FIFO_Q21", + "CMT_FIFO_EE4A3_8", + "CMT_FIFO_L_LOGIC_OUTS7_2", + "CMT_FIFO_NW4END3_1", + "CMT_FIFO_L_IMUX34_1", + "CMT_FIFO_WR1END0_10", + "CMT_FIFO_SW4A3_4", + "CMT_FIFO_WR1END0_9", + "CMT_FIFO_NW4END2_8", + "CMT_OUT_FIFO_D74", + "CMT_FIFO_NW2A3_6", + "CMT_FIFO_NE2A1_4", + "CMT_FIFO_SW4END1_7", + "CMT_FIFO_NW2A1_7", + "CMT_FIFO_NE2A0_11", + "CMT_FIFO_WW2A1_2", + "CMT_FIFO_SE4BEG2_3", + "CMT_FIFO_EE4C3_11", + "CMT_FIFO_L_IMUX17_6", + "CMT_FIFO_WW4B2_11", + "CMT_FIFO_LH7_8", + "CMT_FIFO_L_LOGIC_OUTS12_10", + "CMT_FIFO_NW4A3_9", + "CMT_FIFO_L_IMUX43_10", + "CMT_FIFO_NE4BEG2_4", + "CMT_FIFO_ER1BEG3_1", + "CMT_FIFO_NE4BEG3_2", + "CMT_FIFO_EE4B2_4", + "CMT_FIFO_WW4B2_3", + "CMT_FIFO_PHASER_TO_IO_ICLK_5", + "CMT_FIFO_NE2A3_4", + "CMT_FIFO_SE4BEG3_8", + "CMT_FIFO_NW4A0_3", + "CMT_FIFO_NW4A2_10", + "CMT_FIFO_WR1END1_6", + "CMT_FIFO_NE2A2_4", + "CMT_FIFO_SE4BEG2_1", + "CMT_FIFO_SE2A1_11", + "CMT_IN_FIFO_Q31", + "CMT_FIFO_NW4A1_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", + "CMT_FIFO_L_IMUX13_4", + "CMT_FIFO_L_CTRL0_5", + "CMT_FIFO_L_LOGIC_OUTS14_8", + "CMT_FIFO_LH9_6", + "CMT_FIFO_NW4A0_9", + "CMT_FIFO_L_IMUX21_2", + "CMT_FIFO_L_LOGIC_OUTS10_7", + "CMT_FIFO_LH1_4", + "CMT_FIFO_L_LOGIC_OUTS5_4", + "CMT_FIFO_EE2A3_7", + "CMT_FIFO_SW2A3_2", + "CMT_FIFO_L_IMUX26_10", + "CMT_FIFO_L_BYP2_4", + "CMT_FIFO_L_LOGIC_OUTS12_7", + "CMT_FIFO_PHASER_TO_IO_ICLK_8", + "CMT_FIFO_NW2A0_3", + "CMT_FIFO_L_IMUX28_3", + "CMT_FIFO_SE4C0_3", + "CMT_FIFO_NW4A0_11", + "CMT_FIFO_LH11_5", + "CMT_FIFO_LH10_9", + "CMT_OUT_FIFO_D12", + "CMT_FIFO_WW4B0_4", + "CMT_FIFO_L_FAN4_4", + "CMT_FIFO_SW2A2_10", + "CMT_FIFO_WW4C0_11", + "CMT_FIFO_NE4C2_10", + "CMT_FIFO_WW2END1_4", + "CMT_FIFO_EL1BEG3_7", + "CMT_FIFO_L_IMUX29_10", + "CMT_IN_FIFO_D80", + "CMT_FIFO_L_FAN6_8", + "CMT_FIFO_WW4B2_8", + "CMT_FIFO_WW4B0_11", + "CMT_FIFO_L_IMUX24_11", + "CMT_FIFO_LH10_6", + "CMT_FIFO_L_LOGIC_OUTS1_8", + "CMT_FIFO_WW2END0_6", + "CMT_OUT_FIFO_D55", + "CMT_FIFO_WW2END1_5", + "CMT_FIFO_L_FAN7_9", + "CMT_FIFO_L_CLK1_8", + "CMT_FIFO_EE4C0_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_1", + "CMT_FIFO_NE2A3_10", + "CMT_FIFO_SW4END0_4", + "CMT_FIFO_L_LOGIC_OUTS14_6", + "CMT_OUT_FIFO_D62", + "CMT_FIFO_SE4C0_1", + "CMT_IN_FIFO_TESTWRITEDISB", + "CMT_FIFO_EE4A3_7", + "CMT_IN_FIFO_Q03", + "CMT_OUT_FIFO_Q61", + "CMT_FIFO_L_LOGIC_OUTS1_3", + "CMT_FIFO_SW4A2_0", + "CMT_FIFO_L_BYP1_8", + "CMT_FIFO_L_IMUX45_11", + "CMT_FIFO_L_LOGIC_OUTS17_6", + "CMT_FIFO_NE2A0_5", + "CMT_FIFO_LH12_7", + "CMT_FIFO_WW4C1_6", + "CMT_FIFO_WR1END3_7", + "CMT_FIFO_ER1BEG1_7", + "CMT_FIFO_SW4END2_4", + "CMT_FIFO_L_IMUX46_1", + "CMT_FIFO_L_BYP7_0", + "CMT_FIFO_L_IMUX27_5", + "CMT_FIFO_EE4B1_5", + "CMT_FIFO_L_BYP4_6", + "CMT_FIFO_L_BYP5_8", + "CMT_FIFO_WW4END0_7", + "CMT_FIFO_EE4BEG3_7", + "CMT_FIFO_NE2A2_6", + "CMT_FIFO_EE4B3_1", + "CMT_FIFO_LH4_0", + "CMT_FIFO_L_IMUX45_0", + "CMT_FIFO_NE4C2_7", + "CMT_FIFO_WW4B0_7", + "CMT_FIFO_SE4C0_11", + "CMT_FIFO_L_IMUX28_0", + "CMT_FIFO_WW4B3_9", + "CMT_FIFO_LH8_6", + "CMT_FIFO_L_LOGIC_OUTS23_4", + "CMT_FIFO_L_LOGIC_OUTS19_10", + "CMT_FIFO_L_IMUX32_0", + "CMT_FIFO_MONITOR_N_1", + "CMT_FIFO_L_LOGIC_OUTS12_3", + "CMT_FIFO_SE2A3_7", + "CMT_FIFO_NE4BEG2_9", + "CMT_FIFO_SW4END1_4", + "CMT_FIFO_L_FAN3_9", + "CMT_FIFO_EE4BEG3_6", + "CMT_FIFO_EE2A2_11", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_4", + "CMT_FIFO_SW2A1_8", + "CMT_FIFO_L_IMUX25_2", + "CMT_FIFO_L_IMUX27_10", + "CMT_FIFO_EE4BEG0_10", + "CMT_FIFO_EE4BEG2_5", + "CMT_FIFO_SE4C1_9", + "CMT_FIFO_L_IMUX21_3", + "CMT_FIFO_L_LOGIC_OUTS17_3", + "CMT_FIFO_L_LOGIC_OUTS17_2", + "CMT_FIFO_L_IMUX20_0", + "CMT_FIFO_EL1BEG2_2", + "CMT_FIFO_WW4B1_7", + "CMT_FIFO_WL1END1_8", + "CMT_FIFO_SW4A2_6", + "CMT_FIFO_LH7_10", + "CMT_FIFO_WR1END0_7", + "CMT_FIFO_L_FAN0_7", + "CMT_IN_FIFO_Q74", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_6", + "CMT_FIFO_L_FAN6_7", + "CMT_FIFO_NW4END2_9", + "CMT_IN_FIFO_Q30", + "CMT_FIFO_L_FAN6_10", + "CMT_FIFO_LH3_6", + "CMT_FIFO_L_FAN0_3", + "CMT_FIFO_L_IMUX39_11", + "CMT_FIFO_L_IMUX44_11", + "CMT_FIFO_WW2END1_1", + "CMT_FIFO_EL1BEG2_10", + "CMT_FIFO_L_BYP2_2", + "CMT_OUT_FIFO_RDCLK", + "CMT_FIFO_L_CLK0_9", + "CMT_FIFO_LH4_1", + "CMT_FIFO_WL1END2_11", + "CMT_FIFO_SE4BEG1_10", + "CMT_FIFO_NE2A3_1", + "CMT_FIFO_L_IMUX15_1", + "FIFO_DQS_IOTOPHASER_4", + "CMT_FIFO_L_LOGIC_OUTS3_1", + "CMT_FIFO_SW4END3_6", + "CMT_FIFO_NW4END2_4", + "CMT_FIFO_SE4BEG1_6", + "CMT_FIFO_EE4A0_11", + "CMT_FIFO_L_IMUX40_6", + "CMT_FIFO_WW2A3_6", + "CMT_OUT_FIFO_D57", + "CMT_FIFO_WW4B0_2", + "CMT_FIFO_EE2A0_7", + "CMT_FIFO_L_IMUX29_7", + "CMT_FIFO_SE4C1_5", + "CMT_FIFO_NE4BEG2_0", + "CMT_FIFO_L_LOGIC_OUTS4_2", + "CMT_IN_FIFO_WRCLK", + "CMT_FIFO_SE4C0_2", + "CMT_IN_FIFO_D71", + "CMT_FIFO_L_IMUX2_9", + "CMT_OUT_FIFO_Q70", + "CMT_FIFO_EE4BEG2_7", + "CMT_FIFO_L_BYP1_9", + "CMT_IN_FIFO_Q62", + "CMT_FIFO_L_IMUX25_3", + "CMT_FIFO_L_LOGIC_OUTS0_11", + "CMT_FIFO_EL1BEG0_8", + "CMT_FIFO_EE2BEG0_0", + "CMT_FIFO_WW2END0_11", + "CMT_FIFO_WW4END0_5", + "CMT_FIFO_WW4END1_7", + "CMT_FIFO_L_IMUX19_1", + "CMT_FIFO_WR1END3_4", + "CMT_FIFO_SE2A3_6", + "CMT_FIFO_EE4C3_7", + "CMT_FIFO_L_CLK1_10", + "CMT_FIFO_L_IMUX13_10", + "CMT_FIFO_EE4C0_10", + "CMT_FIFO_L_IMUX47_8", + "CMT_FIFO_NE4BEG1_10", + "CMT_FIFO_SE4BEG3_7", + "CMT_FIFO_L_IMUX26_5", + "CMT_IN_FIFO_D02", + "CMT_FIFO_L_IMUX7_9", + "CMT_FIFO_ER1BEG2_5", + "CMT_FIFO_NW2A3_2", + "CMT_FIFO_WW4END1_2", + "CMT_FIFO_EE4C3_10", + "CMT_FIFO_L_IMUX19_0", + "CMT_FIFO_EE4A2_0", + "CMT_FIFO_LH12_8", + "CMT_FIFO_L_FAN3_7", + "CMT_FIFO_WW2END1_8", + "CMT_FIFO_L_IMUX29_9", + "CMT_FIFO_EE4C0_7", + "CMT_OUT_FIFO_D22", + "CMT_FIFO_SE2A0_7", + "CMT_FIFO_L_BYP3_4", + "CMT_FIFO_LH6_9", + "CMT_FIFO_L_BYP3_0", + "CMT_IN_FIFO_Q91", + "CMT_FIFO_L_IMUX15_7", + "CMT_FIFO_ER1BEG3_11", + "CMT_FIFO_NW4A2_2", + "CMT_FIFO_L_IMUX38_8", + "CMT_FIFO_EE4A0_7", + "CMT_FIFO_LH2_11", + "CMT_FIFO_LH10_8", + "CMT_FIFO_L_IMUX30_3", + "CMT_OUT_FIFO_Q40", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", + "CMT_FIFO_EE4B1_0", + "CMT_FIFO_SE4C1_4", + "CMT_FIFO_L_IMUX44_7", + "CMT_FIFO_NW4END1_6", + "CMT_FIFO_WW4END1_3", + "CMT_FIFO_NE2A0_4", + "CMT_FIFO_NW4A0_5", + "CMT_FIFO_SE4BEG1_5", + "CMT_FIFO_L_IMUX28_11", + "CMT_FIFO_L_IMUX32_6", + "CMT_FIFO_SE4C3_0", + "CMT_FIFO_L_LOGIC_OUTS9_1", + "CMT_FIFO_L_IMUX8_9", + "CMT_FIFO_L_BYP6_11", + "CMT_FIFO_L_IMUX1_10", + "CMT_FIFO_WW4END1_5", + "CMT_FIFO_WL1END3_4", + "CMT_FIFO_L_IMUX47_1", + "CMT_FIFO_L_LOGIC_OUTS21_10", + "CMT_FIFO_L_IMUX11_7", + "CMT_IN_FIFO_Q24", + "CMT_FIFO_WW4A1_7", + "CMT_FIFO_EE4C2_9", + "CMT_FIFO_SE4C1_3", + "CMT_FIFO_WW4END0_1", + "CMT_FIFO_EE4C3_0", + "CMT_FIFO_WW4B3_8", + "CMT_FIFO_L_IMUX2_7", + "CMT_FIFO_EE2BEG3_5", + "CMT_FIFO_NW4A1_1", + "CMT_FIFO_WW4END3_6", + "CMT_FIFO_L_IMUX18_8", + "CMT_FIFO_NW2A3_1", + "CMT_OUT_FIFO_D25", + "CMT_FIFO_L_IMUX21_4", + "CMT_FIFO_MONITOR_N_3", + "CMT_FIFO_L_LOGIC_OUTS16_7", + "CMT_FIFO_EE4C1_8", + "CMT_FIFO_L_IMUX9_7", + "CMT_FIFO_WW4B3_7", + "CMT_FIFO_L_IMUX30_2", + "CMT_FIFO_NE4C2_2", + "CMT_FIFO_EL1BEG0_3", + "CMT_FIFO_WW2END1_9", + "CMT_FIFO_L_LOGIC_OUTS20_9", + "CMT_FIFO_EE4A2_1", + "CMT_FIFO_L_IMUX15_4", + "CMT_FIFO_WW4END2_6", + "CMT_FIFO_L_LOGIC_OUTS9_8", + "CMT_FIFO_L_IMUX14_6", + "CMT_FIFO_L_IMUX45_6", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", + "CMT_FIFO_LH6_8", + "CMT_FIFO_LH4_9", + "CMT_FIFO_L_IMUX15_10", + "CMT_FIFO_SE4BEG3_2", + "CMT_FIFO_L_IMUX18_10", + "CMT_FIFO_NW4END0_8", + "CMT_FIFO_L_FAN7_2", + "CMT_FIFO_L_LOGIC_OUTS2_5", + "CMT_IN_FIFO_Q71", + "CMT_OUT_FIFO_RESET", + "CMT_FIFO_L_LOGIC_OUTS22_0", + "CMT_FIFO_ER1BEG2_6", + "CMT_FIFO_WW2A2_4", + "CMT_FIFO_NW4END1_5", + "CMT_FIFO_L_IMUX12_1", + "CMT_FIFO_SE4BEG2_2", + "CMT_IN_FIFO_Q04", + "CMT_FIFO_LH3_5", + "CMT_IN_FIFO_D21", + "CMT_FIFO_ER1BEG0_2", + "CMT_FIFO_L_LOGIC_OUTS0_9", + "CMT_FIFO_L_IMUX7_2", + "CMT_FIFO_L_IMUX18_1", + "CMT_FIFO_L_LOGIC_OUTS16_3", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", + "CMT_FIFO_SW2A0_11", + "CMT_FIFO_SE4BEG0_4", + "CMT_FIFO_SW4A1_3", + "CMT_FIFO_ER1BEG3_10", + "CMT_FIFO_L_IMUX8_3", + "CMT_FIFO_L_IMUX30_10", + "CMT_FIFO_SW2A3_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_2", + "CMT_OUT_FIFO_D80", + "CMT_FIFO_LH11_6", + "CMT_FIFO_SE4BEG0_2", + "CMT_FIFO_WW4A1_6", + "CMT_FIFO_SW4A1_0", + "CMT_FIFO_L_IMUX36_9", + "CMT_FIFO_L_IMUX42_11", + "CMT_FIFO_EE4BEG1_4", + "CMT_FIFO_L_IMUX31_9", + "CMT_FIFO_L_IMUX12_2", + "CMT_FIFO_MONITOR_P_7", + "CMT_FIFO_EE4B2_3", + "CMT_FIFO_WR1END1_7", + "CMT_FIFO_LH7_2", + "CMT_FIFO_L_IMUX19_8", + "CMT_FIFO_L_IMUX17_3", + "CMT_IN_FIFO_D55", + "CMT_OUT_FIFO_D04", + "CMT_FIFO_L_LOGIC_OUTS16_8", + "CMT_FIFO_SE2A2_11", + "CMT_FIFO_L_LOGIC_OUTS17_7", + "CMT_FIFO_L_IMUX9_0", + "CMT_FIFO_L_LOGIC_OUTS16_5", + "CMT_FIFO_NW4END1_3", + "CMT_FIFO_NW2A0_10", + "CMT_OUT_FIFO_D46", + "CMT_FIFO_NE4BEG2_11", + "CMT_FIFO_SE4C3_11", + "CMT_FIFO_L_LOGIC_OUTS16_9", + "CMT_OUT_FIFO_D96", + "CMT_FIFO_ER1BEG3_8", + "CMT_FIFO_SW4END0_9", + "CMT_FIFO_L_BYP5_5", + "CMT_FIFO_WW2END2_2", + "CMT_FIFO_EE2A1_2", + "CMT_OUT_FIFO_Q62", + "CMT_FIFO_EE2A0_4", + "CMT_FIFO_L_LOGIC_OUTS19_6", + "CMT_FIFO_L_LOGIC_OUTS13_8", + "CMT_FIFO_NW4END0_5", + "CMT_FIFO_L_IMUX30_0", + "CMT_FIFO_L_IMUX19_9", + "CMT_FIFO_L_LOGIC_OUTS17_9", + "CMT_FIFO_WW2A1_5", + "CMT_FIFO_WW4B2_0", + "CMT_FIFO_L_IMUX41_5", + "CMT_FIFO_NE2A1_9", + "CMT_FIFO_L_BYP1_7", + "CMT_FIFO_EE4A3_2", + "CMT_FIFO_SW4END2_9", + "CMT_FIFO_L_LOGIC_OUTS14_3", + "CMT_FIFO_L_LOGIC_OUTS7_10", + "CMT_FIFO_WW2A3_7", + "CMT_FIFO_NW4END2_5", + "CMT_FIFO_L_IMUX21_8", + "CMT_FIFO_L_LOGIC_OUTS23_10", + "CMT_FIFO_WW4END0_6", + "CMT_FIFO_EL1BEG1_7", + "CMT_FIFO_L_FAN7_6", + "CMT_FIFO_L_CTRL1_7", + "CMT_FIFO_L_CTRL0_7", + "CMT_FIFO_SE4C1_6", + "CMT_FIFO_L_LOGIC_OUTS15_11", + "CMT_FIFO_LH10_5", + "CMT_FIFO_L_FAN0_0", + "CMT_FIFO_WL1END0_9", + "CMT_FIFO_EE2A3_10", + "CMT_FIFO_L_IMUX38_11", + "CMT_FIFO_LH9_9", + "CMT_FIFO_LH11_7", + "CMT_FIFO_EL1BEG0_1", + "CMT_FIFO_L_PHASER_RDCLK", + "CMT_FIFO_WW4END3_1", + "CMT_OUT_FIFO_SCANENB", + "CMT_FIFO_SW4END1_9", + "CMT_FIFO_SE2A0_10", + "CMT_FIFO_LH4_5", + "CMT_FIFO_EE2A2_10", + "CMT_FIFO_L_IMUX41_2", + "CMT_OUT_FIFO_SCANIN0", + "CMT_FIFO_WL1END3_9", + "CMT_FIFO_L_IMUX46_9", + "CMT_FIFO_L_FAN2_8", + "CMT_FIFO_WW4B0_0", + "CMT_FIFO_L_FAN4_2", + "CMT_FIFO_NW4END2_3", + "CMT_FIFO_EE4C3_8", + "CMT_FIFO_L_FAN2_9", + "CMT_FIFO_LH7_1", + "CMT_FIFO_L_LOGIC_OUTS0_3", + "CMT_FIFO_L_IMUX35_4", + "CMT_FIFO_EE2BEG0_4", + "CMT_FIFO_NW2A1_6", + "CMT_FIFO_SW4A2_8", + "CMT_FIFO_WW4C3_3", + "CMT_FIFO_L_IMUX16_7", + "CMT_FIFO_LH12_6", + "CMT_FIFO_EE2BEG0_7", + "CMT_FIFO_NE4C2_0", + "CMT_FIFO_LH4_2", + "CMT_FIFO_WW4C0_1", + "CMT_FIFO_EE2A2_7", + "CMT_FIFO_L_IMUX9_2", + "CMT_FIFO_NW4A2_11", + "CMT_FIFO_EE4C1_10", + "CMT_FIFO_EE4BEG3_11", + "CMT_FIFO_NE4BEG3_8", + "CMT_FIFO_L_FAN1_5", + "CMT_FIFO_NE4BEG3_9", + "CMT_FIFO_L_IMUX25_8", + "CMT_FIFO_L_IMUX23_11", + "CMT_FIFO_WW4C1_1", + "CMT_FIFO_L_BYP0_5", + "CMT_FIFO_NW4A2_1", + "CMT_FIFO_L_IMUX10_2", + "CMT_IN_FIFO_D03", + "CMT_FIFO_WL1END0_2", + "CMT_FIFO_NW4END3_2", + "CMT_FIFO_NE2A1_10", + "CMT_FIFO_PHASER_TO_IO_ICLK_9", + "CMT_FIFO_WW4END3_2", + "CMT_FIFO_EE4C3_2", + "CMT_FIFO_SE4C3_3", + "CMT_FIFO_L_CTRL0_10", + "CMT_FIFO_PHASER_TO_IO_ICLK_4", + "CMT_OUT_FIFO_Q01", + "CMT_FIFO_LH11_3", + "CMT_FIFO_L_IMUX29_2", + "CMT_FIFO_L_IMUX23_6", + "CMT_FIFO_EE4A1_6", + "CMT_OUT_FIFO_Q22", + "CMT_FIFO_WW2A3_11", + "CMT_FIFO_L_IMUX47_10", + "CMT_FIFO_WR1END3_6", + "CMT_OUT_FIFO_D07", + "CMT_FIFO_SW4A2_11", + "CMT_FIFO_SE4BEG2_0", + "CMT_FIFO_L_IMUX6_3", + "CMT_FIFO_NE4C2_11", + "CMT_OUT_FIFO_Q72", + "CMT_OUT_FIFO_Q56", + "CMT_FIFO_WW2A0_1", + "CMT_FIFO_WW4END2_8", + "CMT_FIFO_L_IMUX45_7", + "CMT_FIFO_EE2A3_6", + "CMT_OUT_FIFO_RDEN", + "CMT_IN_FIFO_Q06", + "CMT_FIFO_L_IMUX33_2", + "CMT_FIFO_NW4A3_7", + "CMT_FIFO_SW4A2_1", + "CMT_FIFO_SW4END3_1", + "CMT_FIFO_WR1END0_1", + "CMT_FIFO_L_IMUX6_10", + "CMT_FIFO_L_BYP5_4", + "CMT_FIFO_LH8_10", + "CMT_FIFO_WR1END1_4", + "CMT_FIFO_EL1BEG3_10", + "CMT_FIFO_L_IMUX36_8", + "CMT_FIFO_WW2A1_0", + "CMT_FIFO_WW4A1_3", + "CMT_FIFO_EE4BEG3_8", + "CMT_FIFO_MONITOR_N_6", + "CMT_FIFO_L_IMUX28_8", + "CMT_FIFO_SE4C1_1", + "CMT_FIFO_LH1_9", + "CMT_FIFO_WW4B3_0", + "CMT_FIFO_SE4C2_0", + "CMT_FIFO_NW2A3_3", + "CMT_FIFO_LH1_11", + "CMT_FIFO_L_IMUX40_0", + "CMT_FIFO_L_IMUX24_8", + "CMT_FIFO_ER1BEG0_3", + "CMT_OUT_FIFO_Q33", + "CMT_FIFO_L_BYP7_7", + "CMT_FIFO_WW4A3_9", + "CMT_FIFO_ER1BEG0_7", + "CMT_FIFO_L_LOGIC_OUTS7_1", + "CMT_FIFO_SE4BEG1_0", + "CMT_FIFO_L_IMUX9_11", + "CMT_FIFO_L_IMUX12_7", + "CMT_FIFO_L_LOGIC_OUTS7_0", + "CMT_FIFO_NE4BEG2_5", + "CMT_FIFO_SE4C2_6", + "CMT_FIFO_L_IMUX33_10", + "CMT_FIFO_L_LOGIC_OUTS12_11", + "CMT_FIFO_L_FAN4_5", + "CMT_FIFO_NW4END0_6", + "CMT_OUT_FIFO_D66", + "CMT_FIFO_WW4B1_1", + "CMT_FIFO_NE2A1_8", + "CMT_FIFO_WW4B1_11", + "CMT_OUT_FIFO_D60", + "CMT_FIFO_L_IMUX39_6", + "CMT_FIFO_MONITOR_P_1", + "CMT_FIFO_SE2A0_9", + "CMT_FIFO_L_IMUX21_5", + "CMT_FIFO_LH5_0", + "CMT_FIFO_LH11_8", + "CMT_FIFO_L_IMUX1_6", + "CMT_FIFO_SW4A0_10", + "CMT_FIFO_WW2END0_7", + "CMT_FIFO_L_IMUX33_5", + "CMT_FIFO_WW2A3_5", + "CMT_FIFO_LH5_2", + "CMT_FIFO_SE2A3_4", + "CMT_FIFO_EL1BEG2_3", + "CMT_FIFO_L_LOGIC_OUTS4_11", + "CMT_FIFO_NW2A2_6", + "CMT_FIFO_L_FAN2_3", + "CMT_FIFO_L_BYP5_2", + "CMT_FIFO_SW2A0_0", + "CMT_FIFO_L_LOGIC_OUTS14_5", + "CMT_FIFO_NE2A1_5", + "CMT_FIFO_SW2A3_10", + "CMT_FIFO_SW2A1_0", + "CMT_FIFO_L_CLK1_6", + "CMT_FIFO_SW4END1_11", + "CMT_OUT_FIFO_D71", + "CMT_FIFO_SE4BEG2_9", + "CMT_FIFO_L_LOGIC_OUTS3_11", + "CMT_FIFO_WW2A2_10", + "CMT_FIFO_WW2A1_3", + "CMT_FIFO_L_LOGIC_OUTS23_7", + "CMT_IN_FIFO_Q01", + "CMT_FIFO_NE2A3_5", + "CMT_FIFO_LH8_8", + "CMT_FIFO_WW4B1_5", + "CMT_FIFO_LH8_7", + "CMT_FIFO_L_CLK1_1", + "CMT_FIFO_NW4A3_5", + "CMT_FIFO_L_CTRL0_1", + "CMT_FIFO_EE4A0_5", + "CMT_FIFO_SW4A2_2", + "CMT_FIFO_EE4A3_1", + "CMT_FIFO_L_CTRL0_3", + "CMT_FIFO_L_IMUX36_10", + "CMT_FIFO_WW2END1_3", + "CMT_FIFO_EL1BEG0_10", + "CMT_FIFO_NW4A2_7", + "CMT_FIFO_L_BYP1_4", + "CMT_FIFO_EE4A0_0", + "CMT_FIFO_EE2BEG2_7", + "CMT_FIFO_L_IMUX6_4", + "CMT_FIFO_L_FAN6_2", + "CMT_FIFO_L_IMUX17_11", + "CMT_FIFO_NE4BEG3_11", + "CMT_FIFO_L_FAN7_0", + "CMT_FIFO_L_IMUX17_7", + "CMT_IN_FIFO_D33", + "CMT_FIFO_L_IMUX16_3", + "CMT_FIFO_L_LOGIC_OUTS14_4", + "CMT_FIFO_L_IMUX42_8", + "CMT_FIFO_L_FAN2_7", + "CMT_FIFO_NW4END3_0", + "CMT_FIFO_L_IMUX20_1", + "CMT_FIFO_WW4B1_4", + "CMT_FIFO_L_IMUX10_11", + "CMT_FIFO_L_IMUX37_4", + "CMT_FIFO_L_IMUX25_11", + "CMT_FIFO_LH10_11", + "CMT_OUT_FIFO_D32", + "CMT_FIFO_L_LOGIC_OUTS19_2", + "CMT_FIFO_EE4BEG3_9", + "CMT_FIFO_L_IMUX34_4", + "CMT_FIFO_EE4BEG2_1", + "CMT_FIFO_EE4B3_7", + "CMT_FIFO_L_LOGIC_OUTS9_11", + "CMT_FIFO_NE4BEG1_6", + "CMT_FIFO_L_IMUX33_4", + "CMT_FIFO_LH8_2", + "CMT_FIFO_L_IMUX1_1", + "CMT_FIFO_LH8_5", + "CMT_FIFO_SW2A0_7", + "CMT_FIFO_WL1END3_3", + "CMT_FIFO_L_FAN2_10", + "CMT_FIFO_L_LOGIC_OUTS6_8", + "CMT_FIFO_NE4BEG1_8", + "CMT_FIFO_L_BYP3_8", + "CMT_FIFO_L_IMUX27_7", + "CMT_FIFO_PHASER_TO_IO_ICLK_10", + "CMT_FIFO_SE4C3_8", + "CMT_FIFO_NW4END1_4", + "CMT_FIFO_L_IMUX43_9", + "CMT_FIFO_SW2A0_8", + "CMT_FIFO_NE4BEG1_2", + "CMT_FIFO_WL1END1_6", + "CMT_FIFO_WL1END3_0", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_10", + "CMT_FIFO_NW2A1_0", + "CMT_FIFO_WW2A0_0", + "CMT_FIFO_WW4END3_5", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", + "CMT_FIFO_SW2A3_0", + "CMT_FIFO_SE2A0_6", + "CMT_FIFO_LH10_0", + "CMT_FIFO_EE2BEG3_8", + "CMT_FIFO_L_IMUX32_7", + "CMT_IN_FIFO_Q83", + "CMT_FIFO_WW4END0_10", + "CMT_FIFO_L_IMUX34_7", + "CMT_FIFO_L_IMUX20_4", + "CMT_FIFO_WW2A3_4", + "CMT_FIFO_L_IMUX8_6", + "CMT_FIFO_EL1BEG2_8", + "CMT_FIFO_EE4B1_11", + "CMT_FIFO_L_IMUX5_7", + "CMT_FIFO_EL1BEG2_4", + "CMT_FIFO_NW4END3_9", + "CMT_FIFO_L_IMUX4_5", + "CMT_IN_FIFO_Q53", + "CMT_FIFO_L_IMUX3_3", + "CMT_FIFO_L_LOGIC_OUTS7_9", + "CMT_FIFO_LH7_11", + "CMT_FIFO_WW4B3_5", + "CMT_FIFO_WL1END3_6", + "CMT_FIFO_L_LOGIC_OUTS0_1", + "CMT_FIFO_L_IMUX38_9", + "CMT_FIFO_WR1END1_10", + "CMT_FIFO_L_IMUX0_6", + "CMT_FIFO_WW2A0_3", + "CMT_FIFO_EE4A2_9", + "CMT_FIFO_SE4BEG1_4", + "CMT_FIFO_EE4BEG2_4", + "CMT_IN_FIFO_D81", + "CMT_OUT_FIFO_D56", + "CMT_FIFO_L_IMUX24_2", + "CMT_FIFO_WW2END1_0", + "CMT_FIFO_NE4C3_8", + "CMT_FIFO_EE2A2_1", + "CMT_FIFO_SW2A3_3", + "CMT_FIFO_WR1END1_5", + "CMT_OUT_FIFO_Q71", + "CMT_FIFO_ER1BEG2_10", + "CMT_FIFO_SW4A2_7", + "CMT_FIFO_NE4C1_5", + "CMT_FIFO_EE4C2_2", + "CMT_FIFO_L_IMUX18_11", + "CMT_FIFO_L_IMUX2_10", + "CMT_FIFO_WW4END3_11", + "CMT_FIFO_L_IMUX12_11", + "CMT_FIFO_NW2A0_2", + "CMT_FIFO_L_LOGIC_OUTS0_0", + "CMT_FIFO_NW4END1_2", + "CMT_FIFO_WR1END2_5", + "CMT_FIFO_NW4A1_9", + "CMT_FIFO_L_IMUX32_10", + "CMT_FIFO_L_IMUX11_9", + "CMT_FIFO_EE2BEG3_2", + "CMT_FIFO_NW2A0_8", + "CMT_FIFO_L_IMUX43_6", + "CMT_FIFO_EE4C2_11", + "CMT_FIFO_WR1END2_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", + "CMT_FIFO_LH12_2", + "CMT_FIFO_WR1END3_5", + "CMT_IN_FIFO_SCANOUT1", + "CMT_FIFO_WW2A2_11", + "CMT_FIFO_NE4C0_4", + "CMT_FIFO_L_IMUX33_8", + "CMT_FIFO_NW4END0_10", + "CMT_FIFO_SE4C2_11", + "CMT_FIFO_EL1BEG3_3", + "CMT_FIFO_L_LOGIC_OUTS22_7", + "CMT_FIFO_WW2A0_5", + "CMT_OUT_FIFO_D13", + "CMT_FIFO_L_IMUX41_9", + "CMT_FIFO_NE2A1_3", + "CMT_FIFO_L_BYP6_6", + "CMT_FIFO_L_IMUX40_2", + "CMT_FIFO_L_IMUX10_0", + "CMT_FIFO_L_CLK1_2", + "CMT_IN_FIFO_D92", + "CMT_FIFO_L_IMUX3_9", + "CMT_FIFO_L_IMUX20_6", + "CMT_FIFO_WW4C0_6", + "CMT_FIFO_SW2A1_3", + "CMT_FIFO_L_FAN3_10", + "CMT_FIFO_L_LOGIC_OUTS3_10", + "CMT_FIFO_SW4END0_1", + "CMT_IN_FIFO_EMPTY", + "CMT_FIFO_SW2A3_6", + "CMT_IN_FIFO_D41", + "CMT_FIFO_WW4END2_1", + "CMT_FIFO_PHASER_TO_IO_ICLK_6", + "CMT_FIFO_EL1BEG2_1", + "CMT_FIFO_L_IMUX11_6", + "CMT_FIFO_L_IMUX47_3", + "CMT_FIFO_L_IMUX23_5", + "CMT_FIFO_LH11_11", + "CMT_FIFO_L_LOGIC_OUTS3_8", + "CMT_FIFO_L_BYP3_6", + "FIFO_DQS_IOTOPHASER_55", + "CMT_OUT_FIFO_D21", + "CMT_IN_FIFO_FULL", + "CMT_FIFO_NW2A2_3", + "CMT_FIFO_L_IMUX32_1", + "CMT_FIFO_SE2A3_2", + "CMT_FIFO_L_LOGIC_OUTS15_9", + "CMT_FIFO_L_IMUX43_8", + "CMT_FIFO_WW2END3_9", + "CMT_IN_FIFO_D30", + "CMT_FIFO_NE4BEG0_6", + "CMT_FIFO_EE4BEG0_0", + "CMT_FIFO_NE4BEG2_6", + "CMT_FIFO_NW4A2_6", + "CMT_FIFO_LH6_6", + "CMT_FIFO_NE4C1_8", + "CMT_FIFO_WW4A1_11", + "CMT_FIFO_SE4C3_7", + "CMT_FIFO_SE4C3_9", + "CMT_FIFO_L_LOGIC_OUTS14_11", + "CMT_FIFO_L_IMUX9_8", + "CMT_FIFO_L_IMUX38_1", + "CMT_FIFO_L_LOGIC_OUTS3_4", + "CMT_IN_FIFO_Q20", + "CMT_FIFO_L_CTRL0_2", + "CMT_FIFO_L_LOGIC_OUTS19_0", + "CMT_OUT_FIFO_SCANOUT3", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", + "CMT_FIFO_EL1BEG0_9", + "CMT_IN_FIFO_Q23", + "CMT_FIFO_LH6_1", + "CMT_OUT_FIFO_D47", + "CMT_FIFO_WL1END0_1", + "CMT_FIFO_L_IMUX4_10", + "CMT_FIFO_L_IMUX5_8", + "CMT_FIFO_L_BYP6_7", + "CMT_OUT_FIFO_D85", + "CMT_FIFO_ER1BEG1_1", + "CMT_FIFO_LH4_6", + "CMT_FIFO_WW2END2_9", + "CMT_FIFO_EE4B2_9", + "CMT_FIFO_EE2BEG1_0", + "CMT_FIFO_WW4B1_9", + "CMT_FIFO_WW2A1_7", + "CMT_FIFO_MONITOR_N_9", + "CMT_FIFO_NW4END2_10", + "CMT_FIFO_NW4END2_7", + "CMT_FIFO_SE2A1_4", + "CMT_FIFO_L_IMUX39_7", + "CMT_FIFO_L_BYP5_6", + "CMT_FIFO_L_BYP4_8", + "CMT_FIFO_LH2_4", + "CMT_FIFO_LH5_9", + "CMT_FIFO_NW4A2_3", + "CMT_FIFO_WW2END3_8", + "CMT_FIFO_WW4C0_3", + "CMT_FIFO_WR1END3_10", + "CMT_FIFO_L_LOGIC_OUTS22_8", + "CMT_FIFO_NE4C2_1", + "CMT_FIFO_L_LOGIC_OUTS4_4", + "CMT_FIFO_L_IMUX19_10", + "CMT_FIFO_L_LOGIC_OUTS9_5", + "CMT_FIFO_WW4A1_4", + "CMT_FIFO_NW4A3_6", + "CMT_FIFO_L_FAN5_11", + "CMT_FIFO_L_IMUX33_11", + "CMT_FIFO_L_LOGIC_OUTS3_2", + "CMT_FIFO_NE2A3_6", + "CMT_OUT_FIFO_Q13", + "CMT_FIFO_L_LOGIC_OUTS4_1", + "CMT_FIFO_SW2A2_11", + "CMT_FIFO_PHASER_TO_IO_ICLK_1", + "CMT_FIFO_L_IMUX46_7", + "CMT_FIFO_L_BYP0_9", + "CMT_FIFO_SW2A0_1", + "CMT_FIFO_WW4A1_5", + "CMT_FIFO_WL1END3_10", + "CMT_FIFO_EE4B0_9", + "CMT_FIFO_L_IMUX1_8", + "CMT_FIFO_L_IMUX21_1", + "CMT_FIFO_L_LOGIC_OUTS13_10", + "CMT_FIFO_SW4END3_3", + "CMT_FIFO_SE4C2_3", + "CMT_OUT_FIFO_D64", + "CMT_OUT_FIFO_D40", + "CMT_FIFO_WW4A2_3", + "CMT_FIFO_WW4A3_7", + "CMT_FIFO_WR1END3_8", + "CMT_FIFO_WL1END2_9", + "CMT_FIFO_LH2_0", + "CMT_FIFO_L_IMUX25_5", + "CMT_FIFO_L_FAN4_10", + "CMT_FIFO_EE4B0_8", + "CMT_FIFO_EE4C2_8", + "CMT_OUT_FIFO_SCANOUT1", + "CMT_FIFO_L_IMUX45_1", + "CMT_FIFO_NW4A0_6", + "CMT_FIFO_LH7_7", + "CMT_FIFO_L_IMUX8_7", + "CMT_FIFO_EL1BEG1_5", + "CMT_FIFO_L_IMUX20_3", + "CMT_FIFO_L_LOGIC_OUTS22_6", + "CMT_OUT_FIFO_Q67", + "CMT_FIFO_NE4C3_3", + "CMT_FIFO_L_LOGIC_OUTS5_7", + "CMT_FIFO_L_IMUX11_0", + "CMT_FIFO_L_IMUX30_11", + "CMT_FIFO_L_LOGIC_OUTS10_6", + "CMT_FIFO_L_BYP3_1", + "CMT_FIFO_L_IMUX8_0", + "CMT_FIFO_L_FAN5_3", + "CMT_FIFO_L_IMUX42_6", + "CMT_FIFO_L_IMUX35_3", + "CMT_FIFO_L_CTRL1_9", + "CMT_FIFO_SE2A2_6", + "CMT_FIFO_SE4C2_9", + "CMT_FIFO_L_IMUX7_4", + "CMT_FIFO_L_IMUX21_0", + "CMT_FIFO_L_LOGIC_OUTS13_1", + "CMT_FIFO_EE4A2_6", + "CMT_FIFO_WW4B3_1", + "CMT_FIFO_ER1BEG1_11", + "CMT_FIFO_ER1BEG0_9", + "CMT_FIFO_L_LOGIC_OUTS13_2", + "CMT_FIFO_WW4A0_0", + "CMT_FIFO_L_IMUX33_9", + "CMT_FIFO_L_IMUX10_9", + "CMT_FIFO_L_LOGIC_OUTS3_7", + "CMT_FIFO_EE2A2_6", + "CMT_FIFO_EL1BEG2_7", + "CMT_OUT_FIFO_D84", + "CMT_FIFO_L_IMUX37_11", + "CMT_FIFO_SE2A0_5", + "CMT_FIFO_WW4END2_11", + "CMT_FIFO_NW2A2_11", + "CMT_OUT_FIFO_SCANIN3", + "CMT_FIFO_L_LOGIC_OUTS7_3", + "CMT_IN_FIFO_Q16", + "CMT_IN_FIFO_Q45", + "CMT_FIFO_L_IMUX25_0", + "CMT_FIFO_LH9_5", + "CMT_FIFO_SE2A2_3", + "CMT_OUT_FIFO_D31", + "CMT_FIFO_EE4C1_1", + "CMT_IN_FIFO_Q26", + "CMT_FIFO_NE4C0_7", + "CMT_FIFO_LH7_5", + "CMT_FIFO_WW4C1_0", + "CMT_FIFO_L_IMUX36_4", + "CMT_FIFO_NE4BEG3_3", + "CMT_FIFO_EE4BEG2_10", + "CMT_IN_FIFO_Q44", + "CMT_OUT_FIFO_D05", + "CMT_FIFO_LH8_11", + "CMT_FIFO_EE2A0_1", + "CMT_FIFO_LH6_2", + "CMT_FIFO_WW2END3_10", + "CMT_FIFO_EE2BEG1_4", + "CMT_FIFO_NE2A2_2", + "CMT_OUT_FIFO_D73", + "CMT_FIFO_SE2A1_6", + "CMT_FIFO_L_FAN1_1", + "CMT_FIFO_NW2A3_10", + "CMT_FIFO_L_LOGIC_OUTS5_11", + "CMT_FIFO_L_IMUX45_3", + "CMT_OUT_FIFO_Q93", + "CMT_FIFO_L_FAN4_0", + "CMT_FIFO_L_IMUX5_1", + "CMT_FIFO_L_CTRL0_8", + "CMT_FIFO_SE4C3_10", + "CMT_FIFO_NW2A0_0", + "CMT_FIFO_L_LOGIC_OUTS3_5", + "CMT_FIFO_WW2END2_7", + "CMT_FIFO_SW4A3_11", + "CMT_FIFO_WW4C1_8", + "CMT_FIFO_EL1BEG2_6", + "CMT_FIFO_L_IMUX3_10", + "CMT_FIFO_LH10_10", + "CMT_FIFO_WW4END1_0", + "CMT_FIFO_EE4BEG0_1", + "CMT_FIFO_L_FAN7_4", + "CMT_FIFO_L_LOGIC_OUTS8_10", + "CMT_OUT_FIFO_D81", + "CMT_FIFO_L_LOGIC_OUTS0_4", + "CMT_FIFO_L_IMUX12_8", + "CMT_FIFO_WW2END3_4", + "CMT_FIFO_L_FAN0_1", + "CMT_FIFO_SE2A3_9", + "CMT_FIFO_SE2A3_1", + "CMT_FIFO_L_CLK1_0", + "CMT_FIFO_WW2A3_2", + "CMT_FIFO_L_LOGIC_OUTS21_9", + "CMT_FIFO_WW4END3_4", + "CMT_FIFO_WW4C2_2", + "CMT_FIFO_L_LOGIC_OUTS4_0", + "CMT_FIFO_SE2A0_8", + "CMT_FIFO_L_IMUX37_6", + "CMT_FIFO_SE4C1_0", + "CMT_FIFO_L_FAN7_8", + "CMT_FIFO_L_IMUX32_8", + "CMT_FIFO_L_IMUX25_7", + "CMT_FIFO_EE4A0_3", + "CMT_FIFO_NE4C1_4", + "CMT_FIFO_L_BYP0_11", + "CMT_FIFO_EE2BEG2_0", + "CMT_FIFO_SW2A0_3", + "FIFO_DQS_IOTOPHASER_66", + "CMT_FIFO_L_LOGIC_OUTS11_7", + "CMT_FIFO_SE2A1_9", + "CMT_FIFO_NW4END0_7", + "CMT_FIFO_WW4A3_4", + "CMT_FIFO_L_FAN3_6", + "CMT_FIFO_L_IMUX11_5", + "CMT_FIFO_SW4END3_7", + "CMT_FIFO_L_IMUX14_11", + "CMT_FIFO_WW4C2_5", + "CMT_FIFO_SE4C2_10", + "CMT_FIFO_L_IMUX28_5", + "CMT_FIFO_WR1END0_0", + "CMT_FIFO_EE4B3_6", + "CMT_FIFO_L_LOGIC_OUTS19_1", + "CMT_FIFO_EE2A2_9", + "CMT_FIFO_WR1END1_1", + "CMT_FIFO_L_LOGIC_OUTS12_6", + "CMT_FIFO_SE4BEG3_6", + "CMT_FIFO_LH11_4", + "CMT_FIFO_EE4A1_7", + "CMT_FIFO_LH9_0", + "CMT_OUT_FIFO_D97", + "CMT_FIFO_SW4A3_1", + "CMT_IN_FIFO_SCANOUT0", + "CMT_FIFO_L_FAN5_4", + "CMT_FIFO_SW4A1_5", + "CMT_FIFO_L_FAN1_11", + "CMT_FIFO_EE4A1_11", + "CMT_IN_FIFO_Q93", + "CMT_FIFO_L_IMUX0_0", + "CMT_FIFO_L_IMUX19_4", + "CMT_FIFO_SE4C0_9", + "CMT_OUT_FIFO_Q31", + "CMT_FIFO_L_IMUX41_8", + "CMT_FIFO_L_IMUX15_2", + "CMT_FIFO_NE4BEG0_2", + "CMT_FIFO_L_IMUX41_10", + "CMT_FIFO_EE2A3_3", + "CMT_FIFO_SW4END2_1", + "CMT_FIFO_NE4C3_4", + "CMT_FIFO_SW2A0_2", + "CMT_FIFO_L_LOGIC_OUTS12_0", + "CMT_FIFO_SW2A3_11", + "CMT_FIFO_L_IMUX36_0", + "CMT_FIFO_L_LOGIC_OUTS10_10", + "CMT_FIFO_WL1END3_5", + "CMT_FIFO_L_LOGIC_OUTS6_1", + "CMT_FIFO_L_LOGIC_OUTS0_8", + "CMT_FIFO_SE4C2_5", + "CMT_OUT_FIFO_WRCLK", + "CMT_FIFO_L_FAN1_2", + "CMT_FIFO_SW2A2_4", + "CMT_FIFO_EE4B0_1", + "CMT_FIFO_L_LOGIC_OUTS4_8", + "CMT_FIFO_SE4C3_4", + "CMT_FIFO_L_IMUX1_0", + "CMT_FIFO_NW4END0_0", + "CMT_FIFO_SW4A0_7", + "CMT_FIFO_NW4END2_6", + "CMT_FIFO_L_LOGIC_OUTS6_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", + "CMT_IN_FIFO_Q92", + "CMT_FIFO_L_LOGIC_OUTS15_0", + "CMT_FIFO_EE2BEG2_2", + "CMT_FIFO_L_IMUX17_2", + "CMT_FIFO_EE4BEG0_3", + "CMT_FIFO_EE2A0_10", + "CMT_FIFO_L_LOGIC_OUTS10_1", + "CMT_FIFO_L_LOGIC_OUTS20_7", + "CMT_FIFO_WW4B3_4", + "CMT_FIFO_L_IMUX13_1", + "CMT_OUT_FIFO_Q23", + "CMT_FIFO_L_IMUX39_9", + "CMT_FIFO_EE2BEG3_0", + "CMT_FIFO_L_IMUX31_8", + "CMT_FIFO_L_IMUX35_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_3", + "CMT_FIFO_L_IMUX0_8", + "CMT_FIFO_WL1END2_5", + "CMT_FIFO_NW4END1_1", + "CMT_FIFO_NE4C2_8", + "CMT_FIFO_NE4C3_1", + "CMT_FIFO_LH3_7", + "CMT_FIFO_NE4BEG0_5", + "FIFO_DQS_IOTOPHASER_2", + "CMT_IN_FIFO_D22", + "CMT_FIFO_L_FAN5_1", + "CMT_FIFO_EE2BEG0_1", + "CMT_FIFO_MONITOR_P_6", + "CMT_FIFO_WW4A2_5", + "CMT_FIFO_ER1BEG1_3", + "CMT_FIFO_SW2A2_1", + "CMT_FIFO_L_IMUX14_0", + "CMT_FIFO_L_IMUX12_4", + "CMT_FIFO_WW4A0_8", + "CMT_FIFO_L_IMUX9_4", + "CMT_IN_FIFO_ALMOSTFULL", + "CMT_FIFO_L_IMUX14_1", + "CMT_FIFO_SW4END3_10", + "CMT_FIFO_SW4END2_0", + "CMT_FIFO_L_LOGIC_OUTS23_9", + "CMT_FIFO_L_IMUX47_7", + "CMT_FIFO_L_IMUX47_0", + "CMT_FIFO_L_IMUX13_3", + "FIFO_DQS_IOTOPHASER_33", + "CMT_FIFO_L_IMUX21_6", + "CMT_FIFO_L_IMUX24_1", + "CMT_FIFO_L_IMUX10_8", + "CMT_FIFO_ER1BEG1_6", + "CMT_FIFO_LH4_4", + "CMT_FIFO_EE4A0_10", + "CMT_FIFO_SE4BEG2_5", + "CMT_FIFO_L_LOGIC_OUTS17_1", + "CMT_FIFO_L_IMUX1_11", + "CMT_FIFO_L_FAN3_1", + "CMT_OUT_FIFO_D77", + "CMT_FIFO_SW4A3_6", + "CMT_FIFO_L_IMUX25_9", + "CMT_FIFO_L_CLK1_5", + "CMT_FIFO_LH4_3", + "CMT_FIFO_WL1END0_4", + "CMT_FIFO_L_LOGIC_OUTS20_0", + "CMT_FIFO_WW2A3_3", + "CMT_FIFO_L_IMUX6_8", + "CMT_FIFO_WW2END2_10", + "CMT_FIFO_LH7_0", + "CMT_FIFO_L_FAN2_2", + "CMT_FIFO_EE2BEG1_3", + "CMT_IN_FIFO_D20", + "CMT_FIFO_WW4B0_1", + "CMT_FIFO_L_IMUX34_6", + "CMT_FIFO_L_LOGIC_OUTS23_11", + "CMT_FIFO_EE4B0_5", + "CMT_FIFO_NW4A1_11", + "CMT_FIFO_L_LOGIC_OUTS2_1", + "CMT_FIFO_L_IMUX10_4", + "CMT_FIFO_EE4C3_6", + "CMT_FIFO_L_IMUX44_0", + "CMT_FIFO_L_IMUX12_0", + "CMT_IN_FIFO_D42", + "CMT_FIFO_WW4C1_11", + "CMT_FIFO_WW4END0_4", + "CMT_OUT_FIFO_D50", + "CMT_FIFO_L_LOGIC_OUTS15_2", + "CMT_FIFO_SW4A1_7", + "CMT_FIFO_WW4A2_0", + "CMT_FIFO_MONITOR_P_8", + "CMT_FIFO_L_IMUX39_8", + "CMT_FIFO_NW4A1_7", + "CMT_FIFO_L_BYP6_5", + "CMT_FIFO_NE4C3_6", + "CMT_FIFO_LH5_6", + "CMT_FIFO_L_LOGIC_OUTS9_10", + "CMT_IN_FIFO_Q12", + "CMT_FIFO_SW2A3_8", + "CMT_FIFO_EE4BEG3_5", + "CMT_FIFO_L_IMUX22_4", + "CMT_FIFO_L_FAN2_4", + "CMT_FIFO_NE4C1_3", + "CMT_FIFO_L_IMUX45_10", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", + "CMT_FIFO_L_LOGIC_OUTS17_8", + "CMT_FIFO_WW2A3_10", + "CMT_FIFO_NE2A0_10", + "CMT_FIFO_WW2END3_2", + "CMT_FIFO_L_IMUX0_3", + "CMT_IN_FIFO_Q22", + "CMT_FIFO_L_IMUX38_7", + "CMT_FIFO_WW4C1_9", + "CMT_FIFO_EE2BEG2_9", + "CMT_FIFO_EE4BEG0_6", + "CMT_FIFO_LH10_4", + "CMT_FIFO_ER1BEG3_2", + "CMT_FIFO_NE4C0_3", + "CMT_FIFO_L_IMUX12_5", + "CMT_FIFO_EE4C1_0", + "CMT_FIFO_SE4BEG2_10", + "CMT_FIFO_L_IMUX4_1", + "CMT_FIFO_WW2A2_9", + "CMT_FIFO_L_BYP6_8", + "CMT_FIFO_L_FAN1_10", + "CMT_FIFO_SW4END0_0", + "CMT_FIFO_EE2A0_11", + "CMT_FIFO_L_IMUX45_8", + "CMT_FIFO_L_IMUX19_7", + "CMT_FIFO_L_FAN2_0", + "CMT_FIFO_WW4B1_6", + "CMT_FIFO_L_IMUX25_6", + "CMT_FIFO_WL1END3_7", + "CMT_FIFO_L_IMUX41_11", + "CMT_FIFO_WW4END2_5", + "CMT_FIFO_L_LOGIC_OUTS19_3", + "CMT_FIFO_EE2A2_4", + "CMT_FIFO_NW4A2_4", + "CMT_FIFO_L_LOGIC_OUTS10_0", + "CMT_FIFO_L_IMUX42_2", + "CMT_FIFO_EE4B2_10", + "CMT_FIFO_L_IMUX44_1", + "CMT_FIFO_WL1END3_2", + "CMT_FIFO_ER1BEG1_5", + "FIFO_DQS_IOTOPHASER_3", + "CMT_FIFO_L_FAN0_11", + "CMT_FIFO_EE2BEG0_6", + "CMT_OUT_FIFO_Q57", + "CMT_FIFO_WW4B0_5", + "CMT_FIFO_NE4BEG2_2", + "CMT_FIFO_L_IMUX38_4", + "FIFO_DQS_IOTOPHASER_5", + "CMT_FIFO_NW2A0_5", + "CMT_FIFO_NE4BEG0_10", + "CMT_FIFO_WR1END0_5", + "CMT_FIFO_EE2A0_9", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", + "CMT_FIFO_L_LOGIC_OUTS2_7", + "CMT_FIFO_EE4B0_2", + "CMT_FIFO_L_PHASER_WRCLK", + "CMT_FIFO_WW4A1_9", + "CMT_FIFO_L_IMUX27_11", + "CMT_FIFO_L_LOGIC_OUTS18_1", + "CMT_FIFO_L_FAN3_4", + "CMT_IN_FIFO_D65", + "CMT_FIFO_L_IMUX3_6", + "CMT_FIFO_SE2A0_2", + "CMT_FIFO_WW4B1_2", + "CMT_FIFO_L_LOGIC_OUTS20_6", + "CMT_FIFO_L_IMUX24_9", + "CMT_FIFO_L_LOGIC_OUTS11_10", + "CMT_FIFO_WW4C0_10", + "CMT_FIFO_L_IMUX40_7", + "CMT_FIFO_NE4C2_4", + "CMT_FIFO_EE4BEG2_0", + "CMT_OUT_FIFO_Q92", + "CMT_FIFO_L_IMUX39_0", + "CMT_FIFO_SE4C0_8", + "CMT_FIFO_L_IMUX37_10", + "CMT_OUT_FIFO_D00", + "CMT_OUT_FIFO_Q80", + "CMT_IN_FIFO_D64", + "CMT_FIFO_NW4A1_6", + "CMT_FIFO_EE4B1_4", + "CMT_FIFO_L_IMUX35_6", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", + "CMT_FIFO_SW4END2_11", + "CMT_FIFO_EE2A3_9", + "CMT_FIFO_L_IMUX46_10", + "CMT_IN_FIFO_Q73", + "CMT_OUT_FIFO_WREN", + "CMT_FIFO_L_IMUX4_3", + "CMT_FIFO_L_IMUX22_6", + "CMT_IN_FIFO_D83", + "CMT_FIFO_L_BYP0_6", + "CMT_FIFO_SW4A3_9", + "CMT_FIFO_NE4C0_2", + "CMT_FIFO_L_IMUX9_9", + "CMT_FIFO_L_IMUX36_2", + "CMT_FIFO_L_IMUX35_11", + "CMT_FIFO_EL1BEG1_11", + "CMT_FIFO_L_LOGIC_OUTS5_2", + "CMT_IN_FIFO_Q41", + "CMT_FIFO_L_LOGIC_OUTS11_2", + "CMT_OUT_FIFO_D15", + "CMT_IN_FIFO_D13", + "CMT_FIFO_MONITOR_P_5", + "CMT_FIFO_L_IMUX34_10", + "CMT_FIFO_L_IMUX12_6", + "CMT_FIFO_SE4BEG0_10", + "FIFO_DQS_IOTOPHASER_11", + "CMT_IN_FIFO_Q95", + "CMT_FIFO_SW4END3_9", + "CMT_FIFO_L_LOGIC_OUTS20_3", + "CMT_IN_FIFO_Q52", + "CMT_FIFO_WW2END0_5", + "CMT_FIFO_ER1BEG3_7", + "CMT_FIFO_WW4C2_4", + "CMT_FIFO_WW4C2_0", + "CMT_FIFO_SE4C2_4", + "CMT_FIFO_L_IMUX15_11", + "CMT_FIFO_L_LOGIC_OUTS10_5", + "CMT_FIFO_L_IMUX29_8", + "CMT_FIFO_L_LOGIC_OUTS13_7", + "CMT_FIFO_EE4A1_2", + "CMT_FIFO_WW4C3_7", + "CMT_FIFO_L_IMUX31_10", + "CMT_FIFO_L_BYP5_7", + "CMT_IN_FIFO_Q82", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", + "CMT_FIFO_WW4A2_2", + "CMT_FIFO_PHASER_TO_IO_ICLK_11", + "CMT_FIFO_SE4BEG2_4", + "CMT_FIFO_NW4A3_4", + "CMT_FIFO_EE4C2_5", + "CMT_IN_FIFO_D60", + "CMT_FIFO_L_CTRL1_4", + "CMT_FIFO_NE2A3_9", + "CMT_FIFO_L_IMUX3_7", + "CMT_FIFO_SW4A0_4", + "CMT_OUT_FIFO_D30", + "CMT_FIFO_L_LOGIC_OUTS6_2", + "CMT_FIFO_L_IMUX45_2", + "CMT_IN_FIFO_Q13", + "CMT_FIFO_SW2A1_5", + "CMT_FIFO_EE4BEG0_11", + "CMT_FIFO_PHASER_TO_IO_ICLK_2", + "CMT_FIFO_LH4_8", + "CMT_FIFO_NE2A1_7", + "CMT_FIFO_SW2A2_8", + "CMT_FIFO_SW4A2_3", + "CMT_FIFO_L_IMUX14_2", + "CMT_FIFO_EE4B3_9", + "CMT_FIFO_L_IMUX44_9", + "CMT_FIFO_L_LOGIC_OUTS2_2", + "CMT_IN_FIFO_Q17", + "CMT_FIFO_EE4BEG1_7", + "CMT_FIFO_L_IMUX2_2", + "CMT_FIFO_EE4BEG3_2", + "CMT_FIFO_L_IMUX14_9", + "CMT_FIFO_EE4BEG1_3", + "CMT_FIFO_L_FAN6_11", + "CMT_FIFO_EE4C0_9", + "CMT_FIFO_LH6_11", + "CMT_FIFO_L_LOGIC_OUTS14_2", + "CMT_FIFO_SW2A2_0", + "CMT_FIFO_LH5_3", + "CMT_FIFO_SW4A0_2", + "CMT_FIFO_SE4C0_0", + "CMT_FIFO_WL1END2_10", + "CMT_FIFO_WW4B1_8", + "CMT_FIFO_SE4BEG0_7", + "CMT_FIFO_L_CTRL0_6", + "CMT_FIFO_LH4_10", + "CMT_FIFO_L_IMUX4_4", + "CMT_FIFO_WW2END0_2", + "CMT_FIFO_NW2A1_10", + "CMT_FIFO_WW4C2_7", + "CMT_FIFO_L_LOGIC_OUTS17_11", + "CMT_OUT_FIFO_D43", + "CMT_FIFO_L_IMUX2_4", + "CMT_FIFO_L_IMUX41_3", + "CMT_FIFO_SE2A1_2", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", + "CMT_FIFO_L_IMUX24_5", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", + "CMT_IN_FIFO_SCANIN3", + "CMT_FIFO_NW2A1_1", + "CMT_FIFO_LH9_7", + "CMT_FIFO_L_IMUX18_7", + "CMT_FIFO_L_IMUX44_8", + "CMT_OUT_FIFO_TESTMODEB", + "CMT_FIFO_NW4A0_7", + "CMT_FIFO_NE4BEG1_9", + "CMT_FIFO_L_CLK0_0", + "CMT_FIFO_EE2A0_8", + "CMT_OUT_FIFO_SCANIN1", + "CMT_FIFO_EE4B3_11", + "CMT_FIFO_WR1END2_9", + "CMT_FIFO_L_IMUX8_11", + "CMT_FIFO_L_IMUX3_4", + "CMT_FIFO_L_IMUX34_0", + "CMT_FIFO_EE4A0_4", + "CMT_FIFO_L_LOGIC_OUTS9_9", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", + "CMT_FIFO_L_LOGIC_OUTS19_7", + "CMT_FIFO_WW4A0_4", + "CMT_IN_FIFO_Q27", + "CMT_FIFO_LH3_8", + "CMT_FIFO_WR1END3_11", + "CMT_FIFO_EE2BEG1_2", + "CMT_FIFO_EE4C1_6", + "CMT_FIFO_EE4BEG2_11", + "CMT_FIFO_EL1BEG2_11", + "CMT_FIFO_L_IMUX39_10", + "CMT_FIFO_EL1BEG3_2", + "CMT_FIFO_L_IMUX1_3", + "CMT_FIFO_WW4A3_6", + "CMT_FIFO_WW4END0_8", + "CMT_FIFO_NE4C1_11", + "CMT_FIFO_L_LOGIC_OUTS6_6", + "CMT_IN_FIFO_Q32", + "CMT_FIFO_WW2A2_6", + "CMT_FIFO_NE4C3_7", + "CMT_FIFO_EE4B2_1", + "CMT_FIFO_L_FAN5_2", + "CMT_FIFO_EE2BEG1_9", + "CMT_OUT_FIFO_D52", + "CMT_FIFO_WR1END0_2", + "CMT_FIFO_WW4C3_5", + "CMT_FIFO_WL1END2_4", + "CMT_FIFO_EE4B2_7", + "CMT_FIFO_LH11_2", + "CMT_IN_FIFO_D32", + "CMT_FIFO_SE4BEG3_10", + "CMT_FIFO_SE4BEG3_3", + "CMT_FIFO_SW2A1_6", + "CMT_OUT_FIFO_Q83", + "CMT_OUT_FIFO_D45", + "CMT_FIFO_L_IMUX45_4", + "CMT_FIFO_WW4A1_2", + "CMT_FIFO_EE2BEG0_9", + "CMT_FIFO_WR1END3_9", + "CMT_FIFO_L_BYP3_10", + "CMT_FIFO_WL1END1_0", + "CMT_FIFO_L_BYP7_10", + "CMT_FIFO_WR1END1_2", + "CMT_FIFO_EE4C3_1", + "CMT_FIFO_WW2END3_0", + "CMT_OUT_FIFO_Q91", + "CMT_FIFO_WL1END2_1", + "CMT_FIFO_EE2BEG3_1", + "CMT_FIFO_EE4A1_1", + "CMT_FIFO_EE4A1_9", + "CMT_FIFO_EE2BEG3_4", + "CMT_FIFO_SE4BEG0_11", + "CMT_FIFO_WL1END0_7", + "CMT_FIFO_SW2A3_5", + "CMT_FIFO_SE2A2_2", + "CMT_FIFO_NE2A2_9", + "CMT_FIFO_WW4C1_4", + "CMT_FIFO_EE4B3_0", + "CMT_FIFO_EE4B3_10", + "CMT_FIFO_L_IMUX24_4", + "CMT_OUT_FIFO_Q90", + "CMT_FIFO_L_LOGIC_OUTS8_7", + "CMT_FIFO_SW4END3_4", + "CMT_FIFO_EE4C0_2", + "CMT_FIFO_EL1BEG3_0", + "CMT_IN_FIFO_Q76", + "CMT_FIFO_L_LOGIC_OUTS5_10", + "CMT_FIFO_SE4BEG0_0", + "CMT_FIFO_EL1BEG1_2", + "CMT_FIFO_L_IMUX2_5", + "CMT_FIFO_NW2A0_4", + "CMT_FIFO_L_LOGIC_OUTS18_0", + "CMT_FIFO_LH5_8", + "CMT_OUT_FIFO_D41", + "CMT_FIFO_NE2A3_7", + "CMT_FIFO_L_FAN1_9", + "CMT_FIFO_WW4A0_6", + "CMT_FIFO_L_IMUX16_0", + "CMT_FIFO_WW4A0_7", + "CMT_FIFO_WW4C3_11", + "CMT_FIFO_EE2A0_6", + "CMT_FIFO_SW4END1_0", + "CMT_IN_FIFO_Q11", + "CMT_FIFO_MONITOR_P_11", + "CMT_FIFO_SE4BEG3_5", + "CMT_FIFO_NW4END0_9", + "CMT_FIFO_SE4BEG1_3", + "CMT_FIFO_SE4BEG0_3", + "CMT_FIFO_L_BYP2_7", + "CMT_FIFO_WW4C0_9", + "CMT_FIFO_WW4END3_7", + "CMT_FIFO_L_IMUX36_11", + "CMT_FIFO_WL1END2_2", + "CMT_OUT_FIFO_D23", + "CMT_FIFO_L_IMUX33_6", + "CMT_FIFO_WW4A2_8", + "CMT_FIFO_WL1END0_6", + "CMT_FIFO_L_FAN1_8", + "CMT_FIFO_L_FAN6_0", + "CMT_FIFO_L_IMUX29_1", + "CMT_FIFO_L_LOGIC_OUTS20_4", + "CMT_IN_FIFO_Q37", + "CMT_FIFO_NE4BEG1_1", + "CMT_FIFO_LH2_9", + "CMT_FIFO_WW2END0_10", + "CMT_FIFO_EE2A2_0", + "CMT_FIFO_LH6_4", + "CMT_FIFO_EE4A1_8", + "CMT_FIFO_EE4B1_9", + "CMT_FIFO_NE2A0_6", + "CMT_FIFO_SE2A0_1", + "CMT_FIFO_LH11_10", + "CMT_FIFO_SW4A3_0", + "CMT_FIFO_L_IMUX2_0", + "CMT_FIFO_NE4C2_6", + "CMT_FIFO_EE4A2_7", + "CMT_FIFO_L_IMUX6_2", + "CMT_OUT_FIFO_D01", + "CMT_FIFO_EE4BEG1_0", + "CMT_FIFO_LH3_0", + "CMT_FIFO_L_CTRL0_0", + "CMT_FIFO_WW4C2_8", + "CMT_FIFO_ER1BEG3_4", + "CMT_FIFO_WW2END0_0", + "CMT_FIFO_L_IMUX37_9", + "CMT_FIFO_L_IMUX43_0", + "CMT_FIFO_EE2A1_1", + "CMT_FIFO_EL1BEG3_6", + "CMT_FIFO_L_IMUX20_5", + "CMT_FIFO_NW4A0_10", + "CMT_FIFO_L_BYP7_1", + "CMT_FIFO_NE2A2_7", + "CMT_FIFO_L_LOGIC_OUTS22_2", + "CMT_FIFO_L_IMUX0_7", + "CMT_FIFO_NE2A1_1", + "CMT_FIFO_L_IMUX6_6", + "CMT_FIFO_SE4BEG3_9", + "CMT_FIFO_L_IMUX13_9", + "CMT_FIFO_L_LOGIC_OUTS11_1", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", + "CMT_FIFO_NW4A2_8", + "CMT_FIFO_WR1END1_9", + "CMT_FIFO_L_IMUX47_2", + "CMT_FIFO_NW2A0_7", + "CMT_FIFO_L_LOGIC_OUTS2_8", + "CMT_FIFO_L_IMUX29_11", + "CMT_FIFO_L_IMUX14_4", + "CMT_FIFO_NW4A3_3", + "CMT_FIFO_WW2A3_8", + "CMT_FIFO_SW4END2_8", + "CMT_FIFO_EE2A3_11", + "CMT_FIFO_L_LOGIC_OUTS11_11", + "CMT_FIFO_EE2BEG1_1", + "CMT_FIFO_L_IMUX38_10", + "CMT_FIFO_WW4END0_11", + "CMT_FIFO_SE4BEG2_8", + "CMT_FIFO_L_BYP6_1", + "CMT_IN_FIFO_D23", + "CMT_FIFO_SE4C1_7", + "CMT_FIFO_LH8_4", + "CMT_FIFO_SE2A1_8", + "CMT_FIFO_LH6_10", + "CMT_FIFO_EE2A3_4", + "CMT_FIFO_WL1END0_8", + "CMT_FIFO_L_IMUX23_10", + "CMT_FIFO_L_FAN0_5", + "CMT_FIFO_L_IMUX0_4", + "CMT_FIFO_EE4BEG2_8", + "CMT_FIFO_L_LOGIC_OUTS9_6", + "CMT_FIFO_EE2BEG2_4", + "CMT_FIFO_LH9_4", + "CMT_FIFO_EE4BEG2_3", + "CMT_FIFO_L_IMUX15_3", + "CMT_FIFO_NW4A2_0", + "CMT_FIFO_L_IMUX46_3", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", + "CMT_FIFO_L_BYP1_6", + "CMT_FIFO_SW4END1_6", + "CMT_FIFO_L_IMUX42_4", + "CMT_FIFO_L_LOGIC_OUTS13_5", + "CMT_FIFO_EE4C2_10", + "CMT_FIFO_NE4BEG3_0", + "CMT_FIFO_NW4END1_0", + "CMT_FIFO_LH12_5", + "CMT_FIFO_L_LOGIC_OUTS14_0", + "CMT_FIFO_L_IMUX4_11", + "CMT_FIFO_L_IMUX6_5", + "CMT_OUT_FIFO_D26", + "CMT_FIFO_LH3_1", + "CMT_FIFO_EE4A3_0", + "CMT_FIFO_EE4B1_2", + "CMT_FIFO_WW2END2_4", + "CMT_IN_FIFO_Q84", + "CMT_FIFO_WW4END2_4", + "CMT_FIFO_EL1BEG0_11", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_8", + "CMT_OUT_FIFO_D03", + "CMT_FIFO_L_IMUX16_9", + "CMT_FIFO_NE4BEG3_4", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", + "CMT_FIFO_WW4C1_10", + "CMT_FIFO_L_LOGIC_OUTS4_6", + "CMT_FIFO_SW2A1_1", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", + "CMT_FIFO_L_FAN3_11", + "CMT_FIFO_L_LOGIC_OUTS18_10", + "CMT_FIFO_NE4C1_2", + "CMT_FIFO_SW4A1_8", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_11", + "CMT_FIFO_SE2A1_10", + "CMT_FIFO_WW2A0_7", + "CMT_FIFO_WL1END2_7", + "CMT_FIFO_NW4END3_3", + "CMT_FIFO_EE4C2_3", + "CMT_FIFO_L_PHASER_RDENABLE", + "CMT_FIFO_LH2_7", + "CMT_IN_FIFO_Q07", + "CMT_FIFO_WW2A2_8", + "CMT_FIFO_L_BYP4_3", + "CMT_FIFO_L_BYP2_11", + "CMT_FIFO_L_CTRL1_6", + "CMT_IN_FIFO_Q75", + "CMT_OUT_FIFO_Q82", + "CMT_FIFO_NE4BEG3_10", + "CMT_FIFO_NE2A0_2", + "CMT_FIFO_EE2BEG1_8", + "CMT_FIFO_ER1BEG1_8", + "CMT_FIFO_NW2A0_1", + "CMT_FIFO_L_LOGIC_OUTS13_0", + "CMT_FIFO_EE4C0_11", + "CMT_FIFO_SE4C0_7", + "CMT_FIFO_L_IMUX16_2", + "CMT_FIFO_L_LOGIC_OUTS1_7", + "CMT_FIFO_EE4BEG0_8", + "CMT_FIFO_SW4END0_2", + "CMT_FIFO_L_BYP7_5", + "CMT_FIFO_WW4END0_9", + "CMT_FIFO_EE4C2_1", + "CMT_FIFO_SW4A0_5", + "CMT_FIFO_L_FAN5_10", + "CMT_OUT_FIFO_Q73", + "CMT_FIFO_EE2A0_3", + "CMT_FIFO_EE2A2_8", + "CMT_FIFO_L_IMUX18_3", + "CMT_FIFO_MONITOR_P_9", + "FIFO_DQS_IOTOPHASER_22", + "CMT_IN_FIFO_Q65", + "CMT_FIFO_L_LOGIC_OUTS14_1", + "CMT_FIFO_L_IMUX7_8", + "CMT_FIFO_LH8_1", + "CMT_IN_FIFO_D40", + "CMT_FIFO_WW2A1_11", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", + "FIFO_DQS_IOTOPHASER_6", + "CMT_FIFO_L_BYP2_1", + "CMT_FIFO_SW4A1_9", + "CMT_IN_FIFO_Q96", + "CMT_FIFO_L_IMUX28_7", + "CMT_FIFO_L_IMUX38_5", + "CMT_FIFO_WW2A3_0", + "CMT_FIFO_L_BYP0_2", + "CMT_FIFO_L_BYP7_4", + "CMT_FIFO_L_BYP4_5", + "CMT_FIFO_LH1_1", + "CMT_FIFO_L_CLK0_8", + "CMT_OUT_FIFO_Q02", + "CMT_FIFO_EL1BEG0_5", + "CMT_FIFO_NW4END1_9", + "CMT_FIFO_L_IMUX37_0", + "CMT_FIFO_WW4END2_10", + "CMT_FIFO_WR1END2_11", + "CMT_IN_FIFO_SCANIN0", + "CMT_OUT_FIFO_SCANOUT0", + "CMT_FIFO_L_FAN5_8", + "CMT_FIFO_WW4END2_9", + "CMT_FIFO_L_CTRL0_9", + "CMT_FIFO_L_IMUX26_4", + "CMT_FIFO_NE2A2_3", + "CMT_FIFO_L_IMUX44_6", + "CMT_FIFO_L_IMUX19_2", + "CMT_FIFO_NW2A2_8", + "CMT_FIFO_L_LOGIC_OUTS11_3", + "CMT_FIFO_WW4END0_0", + "CMT_FIFO_L_IMUX8_4", + "CMT_FIFO_L_IMUX23_0", + "CMT_FIFO_NW2A0_11", + "CMT_FIFO_WW4A0_9", + "CMT_FIFO_L_BYP6_10", + "CMT_IN_FIFO_Q55", + "CMT_FIFO_L_IMUX9_6", + "CMT_FIFO_L_IMUX26_3", + "CMT_FIFO_EE4A1_10", + "CMT_FIFO_L_LOGIC_OUTS10_11", + "CMT_FIFO_WW4B2_7", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", + "CMT_FIFO_LH10_2", + "CMT_FIFO_EL1BEG3_1", + "CMT_IN_FIFO_D82", + "CMT_FIFO_SE4C1_8", + "CMT_FIFO_WW4B3_11", + "CMT_FIFO_WW4C2_6", + "CMT_FIFO_WW4END1_10", + "CMT_FIFO_NW4END3_4", + "CMT_FIFO_L_IMUX23_3", + "CMT_OUT_FIFO_D93", + "CMT_FIFO_L_IMUX23_8", + "CMT_FIFO_WW4END3_8", + "CMT_FIFO_SW4END0_11", + "CMT_FIFO_L_IMUX5_3", + "CMT_FIFO_L_LOGIC_OUTS23_1", + "CMT_FIFO_L_LOGIC_OUTS6_3", + "CMT_FIFO_WW2A1_9", + "CMT_FIFO_SE2A0_4", + "CMT_FIFO_LH9_2", + "CMT_FIFO_EE2A0_0", + "CMT_FIFO_L_BYP6_2", + "CMT_FIFO_SE4BEG0_6", + "CMT_OUT_FIFO_D54", + "CMT_FIFO_LH12_3", + "CMT_FIFO_L_LOGIC_OUTS3_6", + "CMT_FIFO_EE4B2_5", + "CMT_FIFO_EE4A2_4", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", + "CMT_FIFO_L_CLK1_11", + "CMT_FIFO_NE4C3_0", + "CMT_FIFO_EE4A2_2", + "CMT_FIFO_L_IMUX5_11", + "CMT_OUT_FIFO_EMPTY", + "CMT_FIFO_SW4A0_11", + "CMT_FIFO_WW2END3_1", + "CMT_IN_FIFO_Q63", + "CMT_FIFO_L_IMUX10_6", + "CMT_IN_FIFO_Q40", + "CMT_FIFO_L_FAN6_9", + "CMT_FIFO_L_FAN0_8", + "CMT_FIFO_L_IMUX47_4", + "CMT_FIFO_L_FAN2_5", + "CMT_FIFO_NE4BEG1_0", + "CMT_FIFO_L_IMUX40_11", + "CMT_FIFO_NW2A2_7", + "CMT_FIFO_L_LOGIC_OUTS12_1", + "CMT_FIFO_EE4B1_7", + "CMT_FIFO_EE4A3_6", + "CMT_FIFO_L_BYP0_4", + "CMT_FIFO_WW4END3_0", + "CMT_FIFO_WW4C2_1", + "CMT_FIFO_EE2A2_5", + "CMT_FIFO_WW2A0_2", + "CMT_FIFO_ER1BEG0_10", + "CMT_FIFO_L_IMUX3_8", + "CMT_FIFO_L_LOGIC_OUTS8_11", + "CMT_FIFO_EE2BEG0_11", + "CMT_FIFO_L_BYP7_11", + "CMT_FIFO_WW4B2_6", + "CMT_FIFO_L_LOGIC_OUTS0_5", + "CMT_FIFO_L_LOGIC_OUTS23_5", + "CMT_FIFO_L_IMUX14_8", + "CMT_FIFO_L_LOGIC_OUTS18_7", + "CMT_FIFO_LH1_10", + "CMT_OUT_FIFO_Q11", + "CMT_IN_FIFO_D11", + "CMT_FIFO_SE4C3_5", + "CMT_FIFO_EE4C3_9", + "CMT_FIFO_L_LOGIC_OUTS22_10", + "CMT_FIFO_WW4END2_0", + "CMT_FIFO_EE4C3_4", + "CMT_FIFO_LH5_4", + "CMT_IN_FIFO_TESTREADDISB", + "CMT_FIFO_LH5_7", + "CMT_FIFO_WW4C3_4", + "CMT_FIFO_EE4C2_7", + "CMT_FIFO_NE4C1_10", + "CMT_FIFO_EL1BEG2_0", + "CMT_FIFO_NE4BEG1_7", + "CMT_FIFO_EE4C0_3", + "CMT_FIFO_L_CLK0_11", + "CMT_FIFO_ER1BEG1_0", + "CMT_FIFO_WW2END2_6", + "CMT_FIFO_SW2A0_5", + "CMT_FIFO_L_LOGIC_OUTS9_3", + "CMT_FIFO_EE4BEG1_8", + "CMT_FIFO_EE4B0_7", + "CMT_FIFO_SW4A1_10", + "CMT_FIFO_NE2A2_5", + "CMT_FIFO_NW4A3_0", + "CMT_FIFO_L_IMUX42_9", + "CMT_IN_FIFO_RDEN", + "CMT_FIFO_WW4A3_8", + "CMT_FIFO_NE2A2_8", + "CMT_FIFO_LH7_4", + "CMT_FIFO_L_LOGIC_OUTS17_4", + "CMT_FIFO_L_IMUX27_4", + "CMT_FIFO_L_IMUX16_8", + "CMT_FIFO_L_IMUX46_5", + "CMT_FIFO_SE4C2_2", + "CMT_FIFO_SW4A2_10", + "CMT_FIFO_WW4A2_1", + "CMT_FIFO_L_IMUX7_0", + "CMT_FIFO_L_IMUX33_1", + "CMT_FIFO_L_BYP3_11", + "CMT_IN_FIFO_Q81", + "CMT_FIFO_L_BYP6_4", + "CMT_FIFO_L_LOGIC_OUTS6_10", + "CMT_FIFO_WW4A1_10", + "CMT_FIFO_L_BYP7_2", + "CMT_FIFO_NW4A1_8", + "CMT_FIFO_SE2A0_0", + "CMT_OUT_FIFO_D63", + "CMT_FIFO_SW4END1_5", + "CMT_FIFO_EE2BEG3_9", + "CMT_FIFO_L_LOGIC_OUTS7_4", + "CMT_FIFO_WW2A1_4", + "CMT_FIFO_SW4END1_10", + "CMT_FIFO_MONITOR_N_0", + "CMT_FIFO_NW4END0_1", + "CMT_FIFO_L_IMUX19_11", + "CMT_FIFO_LH3_2", + "CMT_FIFO_WR1END0_8", + "CMT_FIFO_L_IMUX0_1", + "CMT_IN_FIFO_Q67", + "CMT_FIFO_WW2A2_5", + "CMT_IN_FIFO_D01", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_3", + "CMT_FIFO_WW4B2_5", + "CMT_FIFO_EE4BEG2_9", + "CMT_FIFO_SE4C2_7", + "CMT_FIFO_L_IMUX32_3", + "CMT_FIFO_L_FAN2_11", + "CMT_FIFO_L_IMUX14_10", + "CMT_OUT_FIFO_D67", + "CMT_OUT_FIFO_D82", + "CMT_FIFO_EE2BEG1_7", + "CMT_FIFO_L_LOGIC_OUTS2_10", + "CMT_FIFO_L_IMUX11_8", + "CMT_FIFO_L_BYP3_7", + "CMT_FIFO_L_BYP6_3", + "CMT_FIFO_EE4C1_2", + "CMT_FIFO_EE4BEG0_9", + "CMT_FIFO_WW4C1_5", + "CMT_FIFO_MONITOR_P_0", + "CMT_FIFO_EE2BEG0_3", + "CMT_FIFO_L_BYP1_2", + "CMT_FIFO_L_LOGIC_OUTS12_9", + "CMT_FIFO_L_BYP4_9", + "CMT_FIFO_WW4B1_0", + "CMT_FIFO_NW2A1_11", + "CMT_FIFO_L_LOGIC_OUTS2_9", + "CMT_FIFO_LH2_6", + "CMT_FIFO_L_IMUX24_0", + "CMT_FIFO_SE4BEG3_1", + "CMT_FIFO_L_LOGIC_OUTS8_6", + "CMT_FIFO_L_LOGIC_OUTS16_1", + "CMT_FIFO_L_IMUX24_3", + "CMT_FIFO_L_FAN1_4", + "CMT_FIFO_L_IMUX21_11", + "CMT_FIFO_NW2A2_5", + "CMT_FIFO_LH1_0", + "CMT_FIFO_WW4C0_4", + "CMT_FIFO_EL1BEG1_3", + "CMT_OUT_FIFO_ALMOSTFULL", + "CMT_FIFO_EL1BEG1_8", + "CMT_IN_FIFO_Q56", + "CMT_FIFO_L_FAN4_11", + "CMT_FIFO_L_IMUX13_7", + "CMT_FIFO_LH2_5", + "CMT_FIFO_WL1END2_3", + "CMT_FIFO_NE4C3_5", + "CMT_FIFO_EE4B1_1", + "CMT_FIFO_L_IMUX24_6", + "CMT_FIFO_L_IMUX47_6", + "CMT_FIFO_WW4END1_1", + "CMT_FIFO_WL1END2_0", + "CMT_FIFO_L_IMUX28_1", + "CMT_FIFO_NE2A3_0", + "CMT_FIFO_EE4BEG0_2", + "CMT_FIFO_EE2BEG2_11", + "CMT_IN_FIFO_D53", + "CMT_FIFO_WR1END2_8", + "CMT_FIFO_L_IMUX39_3", + "CMT_FIFO_L_BYP0_7", + "CMT_FIFO_L_CLK0_6", + "CMT_FIFO_SW2A2_2", + "CMT_FIFO_SW4END2_5", + "CMT_FIFO_SE4C3_6", + "CMT_FIFO_L_IMUX16_10", + "CMT_FIFO_L_IMUX40_4", + "CMT_FIFO_EE2A1_8", + "CMT_FIFO_L_LOGIC_OUTS21_3", + "CMT_FIFO_ER1BEG3_0", + "CMT_FIFO_EE4B2_0", + "CMT_FIFO_L_BYP1_10", + "CMT_FIFO_WW4B0_6", + "CMT_FIFO_WW4END2_3", + "CMT_FIFO_L_LOGIC_OUTS18_4", + "CMT_IN_FIFO_Q46", + "CMT_FIFO_L_IMUX8_1", + "CMT_FIFO_L_BYP1_5", + "CMT_FIFO_L_LOGIC_OUTS20_5", + "CMT_OUT_FIFO_D33", + "CMT_IN_FIFO_D31", + "CMT_FIFO_L_IMUX13_6", + "CMT_FIFO_LH6_0", + "CMT_FIFO_L_IMUX42_1", + "CMT_FIFO_SE2A1_5", + "CMT_FIFO_L_IMUX17_10", + "CMT_IN_FIFO_D43", + "CMT_FIFO_NW4END1_10", + "CMT_FIFO_L_IMUX21_7", + "CMT_FIFO_NW4A0_1", + "CMT_FIFO_MONITOR_N_11", + "CMT_FIFO_L_IMUX4_2", + "CMT_IN_FIFO_Q54", + "CMT_OUT_FIFO_D17", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", + "CMT_FIFO_NE4C1_0", + "CMT_FIFO_LH6_5", + "CMT_FIFO_WW2END2_3", + "CMT_FIFO_WW2END0_1", + "CMT_FIFO_L_IMUX34_11", + "CMT_FIFO_L_BYP3_3", + "CMT_FIFO_WW4B1_3", + "CMT_FIFO_SW4A1_2", + "CMT_FIFO_L_FAN7_10", + "CMT_FIFO_WL1END1_11", + "CMT_FIFO_L_LOGIC_OUTS8_1", + "CMT_FIFO_LH10_3", + "CMT_FIFO_EL1BEG0_2", + "CMT_FIFO_EE4BEG3_1", + "CMT_FIFO_EE2BEG3_7", + "CMT_FIFO_L_IMUX11_10", + "CMT_FIFO_L_LOGIC_OUTS4_5", + "CMT_FIFO_L_LOGIC_OUTS15_6", + "CMT_FIFO_L_IMUX47_9", + "CMT_FIFO_L_LOGIC_OUTS23_3", + "CMT_FIFO_WW4B2_4", + "CMT_FIFO_L_LOGIC_OUTS21_0", + "CMT_FIFO_NE2A3_3", + "CMT_FIFO_WR1END2_6", + "CMT_FIFO_L_FAN5_6", + "CMT_FIFO_L_IMUX0_5", + "CMT_FIFO_L_IMUX27_2", + "CMT_FIFO_WW2END1_11", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", + "CMT_FIFO_L_IMUX3_11", + "CMT_FIFO_MONITOR_N_7", + "CMT_FIFO_L_LOGIC_OUTS8_0", + "CMT_FIFO_L_LOGIC_OUTS1_2", + "CMT_FIFO_L_IMUX22_1", + "CMT_IN_FIFO_Q33", + "CMT_FIFO_WW4C2_11", + "CMT_FIFO_WW4B0_9", + "CMT_FIFO_LH3_10", + "CMT_FIFO_L_LOGIC_OUTS10_8", + "CMT_FIFO_L_IMUX42_7", + "CMT_FIFO_ER1BEG0_0", + "CMT_FIFO_EE2A1_11", + "CMT_FIFO_SW4END3_11", + "CMT_FIFO_L_LOGIC_OUTS11_4", + "CMT_FIFO_L_BYP0_10", + "CMT_FIFO_L_IMUX17_8", + "CMT_FIFO_NW4A1_10", + "CMT_FIFO_NE4BEG2_7", + "CMT_FIFO_L_IMUX22_9", + "CMT_OUT_FIFO_Q12", + "FIFO_DQS_IOTOPHASER_44", + "CMT_FIFO_SW4A3_5", + "CMT_FIFO_L_IMUX37_3", + "CMT_FIFO_L_IMUX37_5", + "CMT_FIFO_L_LOGIC_OUTS8_8", + "CMT_FIFO_L_IMUX47_11", + "CMT_FIFO_WR1END2_10", + "CMT_FIFO_WL1END0_5", + "CMT_FIFO_WL1END0_3", + "CMT_FIFO_EE4C1_7", + "CMT_FIFO_L_IMUX34_9", + "CMT_FIFO_ER1BEG2_1", + "CMT_FIFO_SE4BEG1_7", + "CMT_FIFO_L_LOGIC_OUTS21_5", + "CMT_FIFO_EE2BEG2_1", + "CMT_FIFO_SW2A3_7", + "CMT_FIFO_NW4A3_1", + "CMT_FIFO_NW2A2_2", + "CMT_OUT_FIFO_Q43", + "CMT_FIFO_SE2A2_0", + "CMT_FIFO_WW4END3_9", + "CMT_FIFO_L_IMUX2_3", + "CMT_OUT_FIFO_Q51", + "CMT_FIFO_L_BYP3_2", + "CMT_FIFO_NE2A3_2", + "CMT_FIFO_WW4B3_2", + "CMT_FIFO_L_IMUX25_1", + "CMT_IN_FIFO_D10", + "CMT_FIFO_NE2A0_0", + "CMT_FIFO_L_LOGIC_OUTS1_0", + "CMT_OUT_FIFO_TESTREADDISB", + "CMT_FIFO_WL1END1_7", + "CMT_FIFO_SW2A2_3", + "CMT_FIFO_SW2A0_10", + "CMT_FIFO_SE4BEG2_6", + "CMT_FIFO_NE4C0_1", + "CMT_FIFO_EE2A1_5", + "CMT_FIFO_WR1END1_0", + "CMT_FIFO_L_BYP0_8", + "CMT_FIFO_EE4B0_0", + "CMT_FIFO_NE4C2_9", + "CMT_FIFO_L_LOGIC_OUTS13_9", + "CMT_FIFO_EE4A1_3", + "CMT_FIFO_L_BYP4_4", + "CMT_FIFO_L_FAN4_7", + "CMT_FIFO_LH9_3", + "CMT_FIFO_SE4BEG0_8", + "CMT_FIFO_L_LOGIC_OUTS1_1", + "CMT_IN_FIFO_Q64", + "CMT_FIFO_EE4C1_11", + "CMT_FIFO_L_LOGIC_OUTS0_7", + "CMT_FIFO_SW4END2_7", + "CMT_FIFO_L_LOGIC_OUTS15_8", + "CMT_FIFO_WL1END0_0", + "CMT_FIFO_EL1BEG3_9", + "CMT_FIFO_LH10_1", + "CMT_FIFO_WW4A3_10", + "CMT_FIFO_SW2A1_4", + "CMT_FIFO_L_FAN5_7", + "CMT_FIFO_L_IMUX42_0", + "CMT_FIFO_L_IMUX43_11", + "CMT_FIFO_WW2END0_3", + "CMT_FIFO_L_LOGIC_OUTS0_10", + "CMT_FIFO_EE4BEG1_2", + "CMT_FIFO_L_IMUX42_5", + "CMT_FIFO_L_IMUX17_5", + "CMT_FIFO_SW4A3_7", + "CMT_FIFO_EE2A1_3", + "CMT_FIFO_L_LOGIC_OUTS5_9", + "CMT_FIFO_L_IMUX26_8", + "CMT_FIFO_SE4BEG1_8", + "CMT_FIFO_L_IMUX14_7", + "CMT_FIFO_L_IMUX39_2", + "CMT_FIFO_SW4END0_10", + "CMT_IN_FIFO_SCANIN2", + "CMT_FIFO_L_IMUX36_5", + "CMT_FIFO_NE2A1_6", + "CMT_FIFO_L_CLK0_3", + "CMT_FIFO_L_LOGIC_OUTS8_4", + "CMT_FIFO_L_IMUX12_3", + "CMT_FIFO_EE4B1_10", + "CMT_FIFO_NW2A0_6", + "CMT_FIFO_LH7_9", + "CMT_FIFO_NW4END2_0", + "CMT_FIFO_NW4END1_8", + "CMT_FIFO_SW4END3_2", + "CMT_IN_FIFO_SCANENB", + "CMT_FIFO_L_IMUX43_7", + "CMT_FIFO_WW2A0_8", + "CMT_OUT_FIFO_Q42", + "CMT_FIFO_L_IMUX3_5", + "CMT_FIFO_SW2A3_9", + "CMT_FIFO_EE4A1_4", + "CMT_FIFO_SE4BEG2_11", + "CMT_FIFO_L_IMUX46_11", + "CMT_FIFO_EE2BEG3_10", + "CMT_FIFO_ER1BEG0_4", + "CMT_FIFO_L_BYP1_1", + "CMT_FIFO_L_IMUX5_5", + "CMT_FIFO_MONITOR_N_8", + "CMT_FIFO_L_BYP2_5", + "CMT_FIFO_SW4A3_2", + "CMT_FIFO_L_LOGIC_OUTS18_5", + "CMT_FIFO_L_IMUX0_11", + "CMT_FIFO_EL1BEG3_5", + "CMT_FIFO_L_IMUX6_7", + "CMT_OUT_FIFO_ALMOSTEMPTY", + "CMT_FIFO_NW4A0_4", + "CMT_FIFO_EE4BEG1_6", + "CMT_FIFO_EE2BEG2_6", + "CMT_FIFO_L_LOGIC_OUTS10_4", + "CMT_FIFO_L_LOGIC_OUTS20_11", + "CMT_FIFO_MONITOR_N_4", + "CMT_FIFO_L_FAN0_10", + "CMT_FIFO_WW4A2_11", + "CMT_FIFO_SE4BEG1_2", + "CMT_FIFO_SW4A2_9", + "CMT_IN_FIFO_SCANIN1", + "CMT_FIFO_LH12_4", + "CMT_IN_FIFO_Q35", + "CMT_FIFO_L_IMUX5_6", + "CMT_FIFO_L_IMUX18_2", + "CMT_IN_FIFO_RDCLK", + "CMT_FIFO_L_LOGIC_OUTS13_4", + "CMT_FIFO_SW4A2_4", + "CMT_FIFO_L_LOGIC_OUTS1_6", + "CMT_FIFO_SE4C0_6", + "CMT_OUT_FIFO_D14", + "CMT_FIFO_SW4END1_3", + "CMT_FIFO_WL1END1_4", + "CMT_FIFO_EE4B3_3", + "CMT_FIFO_WW2END1_10", + "CMT_FIFO_NW4A1_0", + "CMT_FIFO_SE2A1_1", + "CMT_FIFO_L_FAN7_5", + "CMT_FIFO_EL1BEG0_6", + "CMT_FIFO_L_IMUX14_3", + "CMT_FIFO_LH1_6", + "CMT_FIFO_NE4BEG1_3", + "CMT_FIFO_L_IMUX16_4", + "CMT_FIFO_NE4C1_6", + "CMT_IN_FIFO_Q97", + "CMT_FIFO_SW4END0_3", + "CMT_FIFO_WL1END3_11", + "CMT_FIFO_L_BYP7_9", + "CMT_FIFO_PHASER_TO_IO_ICLK_0", + "CMT_FIFO_WW4A3_2", + "CMT_FIFO_L_FAN0_4", + "CMT_FIFO_MONITOR_P_3", + "CMT_FIFO_WW2END1_2", + "CMT_FIFO_SE2A3_5", + "CMT_FIFO_EE4B3_8", + "CMT_FIFO_L_LOGIC_OUTS18_8", + "CMT_FIFO_L_IMUX1_9", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", + "CMT_FIFO_WW2END0_4", + "CMT_FIFO_L_FAN4_8", + "CMT_FIFO_NW4END0_11", + "CMT_FIFO_L_LOGIC_OUTS14_7", + "CMT_FIFO_LH11_0", + "CMT_FIFO_L_IMUX27_1", + "CMT_FIFO_L_LOGIC_OUTS1_11", + "CMT_FIFO_SW4END3_5", + "CMT_FIFO_SW4A0_6", + "CMT_OUT_FIFO_D37", + "CMT_OUT_FIFO_Q50", + "CMT_FIFO_NW4END3_6", + "CMT_FIFO_NE4C0_5", + "CMT_FIFO_EE4BEG1_11", + "CMT_IN_FIFO_D67", + "CMT_FIFO_NW2A3_7", + "CMT_FIFO_L_LOGIC_OUTS10_9", + "CMT_FIFO_NE4BEG2_3", + "CMT_FIFO_L_IMUX29_5", + "CMT_FIFO_WL1END3_8", + "CMT_FIFO_L_IMUX20_9", + "CMT_IN_FIFO_D72", + "CMT_FIFO_L_LOGIC_OUTS9_4", + "CMT_FIFO_L_LOGIC_OUTS3_0", + "CMT_FIFO_L_IMUX26_9", + "CMT_FIFO_NE4C1_1", + "CMT_FIFO_WW4B3_6", + "CMT_FIFO_EE2BEG1_11", + "CMT_FIFO_NE4C3_11", + "CMT_FIFO_LH5_1", + "CMT_FIFO_L_FAN0_9", + "CMT_FIFO_SE2A2_8", + "CMT_FIFO_EE4BEG1_1", + "CMT_FIFO_L_LOGIC_OUTS11_9", + "CMT_FIFO_LH9_8", + "CMT_FIFO_L_LOGIC_OUTS12_4", + "CMT_FIFO_L_IMUX39_1", + "CMT_FIFO_L_IMUX3_0", + "CMT_FIFO_NW4END3_7", + "CMT_FIFO_EE4C1_9", + "CMT_FIFO_EL1BEG2_5", + "CMT_OUT_FIFO_FULL", + "CMT_FIFO_WW4END0_2", + "CMT_FIFO_NW2A1_5", + "CMT_FIFO_L_IMUX5_2", + "CMT_FIFO_NW4END2_1", + "CMT_FIFO_EL1BEG1_1", + "CMT_FIFO_EE2A3_2", + "CMT_FIFO_EE4B3_5", + "CMT_FIFO_L_IMUX7_6", + "CMT_FIFO_L_IMUX45_5", + "CMT_IN_FIFO_D61", + "CMT_FIFO_ER1BEG0_6", + "CMT_FIFO_ER1BEG3_5", + "CMT_FIFO_EE4A0_9", + "CMT_FIFO_NE4BEG0_1", + "CMT_FIFO_WW2A1_8", + "CMT_FIFO_EL1BEG0_4", + "CMT_FIFO_L_BYP1_11", + "CMT_FIFO_EE4A3_9", + "CMT_FIFO_EE2BEG2_10", + "CMT_OUT_FIFO_D76", + "CMT_FIFO_L_IMUX4_9", + "CMT_FIFO_L_FAN7_11", + "CMT_FIFO_L_IMUX18_5", + "CMT_FIFO_L_CTRL0_11", + "CMT_FIFO_EE4B2_8", + "CMT_FIFO_L_FAN4_9", + "CMT_FIFO_SE4BEG2_7", + "CMT_FIFO_L_LOGIC_OUTS11_8", + "CMT_FIFO_EE4BEG3_4", + "CMT_FIFO_NW4A3_8", + "CMT_FIFO_SW4A3_8", + "CMT_FIFO_L_FAN7_3", + "CMT_FIFO_SW4END0_5", + "CMT_FIFO_SE2A2_4", + "CMT_FIFO_LH9_11", + "CMT_FIFO_L_CTRL1_2", + "CMT_FIFO_L_IMUX23_9", + "CMT_FIFO_WW4A0_3", + "CMT_FIFO_L_LOGIC_OUTS3_3", + "CMT_FIFO_ER1BEG3_6", + "CMT_FIFO_L_IMUX27_0", + "CMT_FIFO_L_IMUX31_11", + "CMT_FIFO_NW2A2_4", + "CMT_FIFO_NW2A3_9", + "CMT_FIFO_L_IMUX43_3", + "CMT_FIFO_L_IMUX4_8", + "CMT_FIFO_LH4_11", + "CMT_FIFO_L_IMUX42_3", + "CMT_FIFO_NW4A0_0", + "CMT_FIFO_L_IMUX31_3", + "CMT_FIFO_L_CLK0_2", + "CMT_FIFO_ER1BEG2_4", + "CMT_FIFO_L_IMUX0_9", + "CMT_FIFO_WW2END2_0", + "CMT_FIFO_SE4BEG0_9", + "CMT_FIFO_L_LOGIC_OUTS19_9", + "CMT_FIFO_SW2A1_10", + "CMT_FIFO_L_IMUX16_5", + "CMT_FIFO_SE2A3_3", + "CMT_FIFO_WW2END2_5", + "CMT_FIFO_NW4A1_5", + "CMT_FIFO_SE4BEG3_4", + "CMT_FIFO_L_LOGIC_OUTS17_0", + "CMT_IN_FIFO_Q77", + "CMT_FIFO_NE4C0_8", + "CMT_FIFO_L_FAN5_0", + "CMT_FIFO_L_CLK0_1", + "CMT_FIFO_SE2A0_3", + "CMT_FIFO_L_IMUX43_1", + "CMT_OUT_FIFO_D86", + "CMT_FIFO_EE2A1_9", + "CMT_FIFO_L_IMUX15_9", + "CMT_OUT_FIFO_D02", + "CMT_OUT_FIFO_D65", + "CMT_FIFO_EE4A1_5", + "CMT_FIFO_L_BYP0_3", + "CMT_FIFO_LH8_9", + "CMT_FIFO_L_LOGIC_OUTS15_4", + "CMT_OUT_FIFO_Q63", + "CMT_FIFO_SE4BEG0_5", + "CMT_FIFO_LH2_2", + "CMT_FIFO_L_IMUX40_9", + "CMT_IN_FIFO_Q43", + "CMT_OUT_FIFO_D53", + "CMT_FIFO_L_BYP4_1", + "CMT_FIFO_NW2A3_5", + "CMT_FIFO_L_IMUX40_3", + "CMT_FIFO_SE4C2_1", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", + "CMT_FIFO_WW4C2_9", + "CMT_FIFO_NE4C2_5", + "CMT_FIFO_L_IMUX20_8", + "CMT_FIFO_EE2A1_6", + "CMT_IN_FIFO_Q14", + "CMT_FIFO_L_IMUX8_2", + "CMT_FIFO_L_IMUX21_9", + "CMT_FIFO_WR1END1_3", + "CMT_FIFO_LH9_1", + "CMT_FIFO_L_LOGIC_OUTS8_9", + "CMT_IN_FIFO_Q34", + "CMT_FIFO_L_LOGIC_OUTS21_11", + "CMT_FIFO_NE4C3_2", + "CMT_FIFO_WW4B3_3", + "CMT_FIFO_L_IMUX42_10", + "CMT_FIFO_L_FAN6_6", + "CMT_FIFO_L_LOGIC_OUTS4_10", + "CMT_FIFO_L_LOGIC_OUTS4_9", + "CMT_FIFO_NE4C0_10", + "CMT_FIFO_L_BYP3_5", + "CMT_OUT_FIFO_D34", + "CMT_FIFO_L_IMUX22_5", + "CMT_FIFO_SE2A2_7", + "CMT_FIFO_L_IMUX8_5", + "CMT_FIFO_L_BYP5_0", + "CMT_FIFO_L_LOGIC_OUTS9_0", + "CMT_FIFO_L_IMUX47_5", + "CMT_FIFO_MONITOR_N_5", + "CMT_FIFO_L_FAN5_5", + "CMT_FIFO_L_IMUX17_4", + "CMT_FIFO_L_LOGIC_OUTS6_11", + "CMT_FIFO_EL1BEG2_9", + "CMT_FIFO_L_IMUX7_11", + "CMT_FIFO_EE2A3_1", + "CMT_FIFO_EL1BEG1_10", + "CMT_FIFO_EE2BEG0_8", + "CMT_FIFO_L_FAN6_5", + "CMT_FIFO_L_IMUX27_8", + "CMT_FIFO_NE2A3_8", + "CMT_FIFO_L_IMUX31_6", + "CMT_OUT_FIFO_D36", + "CMT_FIFO_WW4A0_5", + "CMT_FIFO_L_IMUX27_3", + "CMT_FIFO_EE4BEG2_6", + "CMT_FIFO_L_LOGIC_OUTS17_5", + "CMT_FIFO_L_IMUX37_1", + "CMT_FIFO_L_IMUX2_6", + "CMT_OUT_FIFO_Q03", + "CMT_FIFO_WL1END1_10", + "CMT_IN_FIFO_D00", + "CMT_FIFO_LH4_7", + "CMT_FIFO_ER1BEG0_8", + "CMT_FIFO_L_IMUX11_4", + "CMT_FIFO_LH2_1", + "CMT_FIFO_WW2A0_10", + "CMT_FIFO_WW4C1_2", + "CMT_FIFO_L_LOGIC_OUTS6_5", + "CMT_FIFO_WL1END3_1", + "CMT_FIFO_WW4A0_2", + "CMT_OUT_FIFO_D44", + "CMT_IN_FIFO_Q61", + "CMT_FIFO_NW4END2_11", + "CMT_FIFO_NW2A3_4", + "CMT_FIFO_L_IMUX35_1", + "CMT_FIFO_NE4C0_6", + "CMT_FIFO_ER1BEG2_3", + "CMT_FIFO_L_IMUX7_10", + "CMT_FIFO_SW4END1_8", + "CMT_FIFO_L_IMUX29_0", + "CMT_FIFO_ER1BEG2_0", + "CMT_FIFO_L_LOGIC_OUTS4_7", + "CMT_FIFO_WW4C0_0", + "CMT_FIFO_L_FAN3_3", + "CMT_FIFO_ER1BEG1_10", + "CMT_FIFO_WW4A0_11", + "CMT_FIFO_L_LOGIC_OUTS18_9", + "CMT_FIFO_LH1_7", + "CMT_FIFO_WW4C3_8", + "CMT_FIFO_EL1BEG3_4", + "CMT_IN_FIFO_Q66", + "CMT_FIFO_EE4BEG3_3", + "CMT_FIFO_L_IMUX28_9", + "CMT_FIFO_L_LOGIC_OUTS21_2", + "CMT_FIFO_L_IMUX25_4", + "CMT_FIFO_SE4BEG1_1", + "CMT_FIFO_EE2BEG2_5", + "CMT_FIFO_L_LOGIC_OUTS13_6", + "CMT_FIFO_L_IMUX2_11", + "CMT_FIFO_L_IMUX5_10", + "CMT_FIFO_L_LOGIC_OUTS18_3", + "CMT_FIFO_L_BYP7_6", + "CMT_FIFO_L_LOGIC_OUTS2_6", + "CMT_FIFO_WW2A3_9", + "CMT_FIFO_WW4B2_1", + "CMT_FIFO_L_CLK0_10", + "CMT_FIFO_L_IMUX22_8", + "CMT_FIFO_WW4A2_9", + "CMT_FIFO_L_LOGIC_OUTS5_6", + "CMT_FIFO_WW4C2_3", + "CMT_FIFO_L_BYP5_11", + "CMT_OUT_FIFO_Q00", + "CMT_OUT_FIFO_Q30", + "CMT_FIFO_L_LOGIC_OUTS20_10", + "CMT_FIFO_L_IMUX43_2", + "CMT_FIFO_EE4BEG2_2", + "CMT_FIFO_L_BYP2_3", + "CMT_FIFO_WW2A2_2", + "CMT_FIFO_WR1END2_1", + "CMT_FIFO_NW4END3_5", + "CMT_FIFO_L_LOGIC_OUTS14_10", + "CMT_FIFO_L_CTRL1_5", + "CMT_IN_FIFO_D50", + "CMT_FIFO_NW2A2_9", + "CMT_FIFO_L_IMUX37_2", + "CMT_FIFO_L_IMUX41_4", + "CMT_FIFO_NE4C0_9", + "CMT_IN_FIFO_Q94", + "CMT_FIFO_L_IMUX7_1", + "CMT_FIFO_EE4C0_6", + "CMT_FIFO_NE4BEG3_7", + "CMT_FIFO_L_IMUX44_2", + "CMT_OUT_FIFO_D11", + "CMT_FIFO_NE4BEG1_11", + "CMT_FIFO_SW2A2_9", + "CMT_FIFO_EE4C0_0", + "CMT_FIFO_EE2BEG1_6", + "CMT_FIFO_L_IMUX6_9", + "CMT_FIFO_EE4BEG0_7", + "CMT_FIFO_WW4A2_4", + "CMT_FIFO_NE2A0_3", + "CMT_FIFO_L_FAN5_9", + "CMT_FIFO_L_IMUX29_6", + "CMT_FIFO_L_IMUX5_9", + "CMT_FIFO_SE4C3_2", + "CMT_FIFO_SW2A0_4", + "CMT_FIFO_L_IMUX30_1", + "CMT_FIFO_L_LOGIC_OUTS16_0", + "CMT_FIFO_ER1BEG3_3", + "CMT_FIFO_EE4BEG0_4", + "CMT_FIFO_NW2A3_0", + "CMT_FIFO_WW4B2_9", + "CMT_FIFO_L_FAN2_1", + "CMT_FIFO_LH1_8", + "CMT_OUT_FIFO_SCANIN2", + "CMT_FIFO_EE2A1_10", + "CMT_FIFO_EE4C3_5", + "CMT_FIFO_SW4END0_6", + "CMT_FIFO_L_LOGIC_OUTS12_8", + "CMT_FIFO_L_LOGIC_OUTS15_5", + "CMT_FIFO_L_LOGIC_OUTS13_3", + "CMT_IN_FIFO_D12", + "CMT_FIFO_WW2A3_1", + "CMT_FIFO_WW4A3_11", + "CMT_FIFO_L_LOGIC_OUTS8_2", + "CMT_FIFO_SW4END0_7", + "CMT_FIFO_L_IMUX1_7", + "CMT_FIFO_L_IMUX30_7", + "CMT_FIFO_NE2A1_0", + "CMT_FIFO_L_BYP5_1", + "CMT_FIFO_EE2A3_0", + "CMT_IN_FIFO_D57", + "CMT_FIFO_EE2BEG2_3", + "CMT_FIFO_NE2A2_11", + "CMT_FIFO_NE4BEG1_4", + "CMT_FIFO_NE4BEG0_0", + "CMT_FIFO_WW2A1_6", + "CMT_FIFO_SW4A0_0", + "CMT_FIFO_WW2A1_1", + "CMT_FIFO_LH3_3", + "CMT_FIFO_L_IMUX34_8", + "CMT_FIFO_L_IMUX41_6", + "CMT_FIFO_L_BYP5_3", + "CMT_FIFO_L_IMUX9_1", + "CMT_FIFO_NE2A0_1", + "CMT_FIFO_LH1_5", + "CMT_FIFO_L_IMUX33_7", + "CMT_FIFO_L_LOGIC_OUTS7_6", + "CMT_FIFO_WW2A0_11", + "CMT_FIFO_SE2A3_10", + "CMT_FIFO_L_BYP5_10", + "CMT_FIFO_L_IMUX38_2", + "CMT_FIFO_NE4BEG0_7", + "CMT_FIFO_L_LOGIC_OUTS15_10", + "CMT_FIFO_WW4B2_2", + "CMT_FIFO_L_CLK1_7", + "CMT_FIFO_L_CLK1_4", + "CMT_FIFO_WW4C0_5", + "CMT_FIFO_WW4END3_3", + "CMT_FIFO_WW4B0_3", + "CMT_OUT_FIFO_D06", + "CMT_FIFO_L_IMUX46_8", + "CMT_IN_FIFO_TESTMODEB", + "CMT_FIFO_WL1END1_5", + "CMT_FIFO_L_CTRL1_8", + "CMT_FIFO_EE2BEG0_2", + "CMT_FIFO_L_LOGIC_OUTS19_8", + "CMT_FIFO_ER1BEG2_2", + "CMT_FIFO_WW2A0_4", + "CMT_FIFO_L_CLK0_7", + "CMT_FIFO_L_IMUX24_10", + "CMT_FIFO_L_IMUX35_8", + "CMT_FIFO_LH9_10", + "CMT_FIFO_L_IMUX31_7", + "CMT_FIFO_EL1BEG1_9", + "CMT_IN_FIFO_Q05", + "CMT_FIFO_WW4END2_2", + "CMT_FIFO_L_FAN6_3", + "CMT_FIFO_NE4C3_9", + "CMT_FIFO_NW2A3_8", + "CMT_FIFO_L_LOGIC_OUTS8_3", + "CMT_FIFO_L_IMUX4_0", + "CMT_FIFO_L_IMUX35_0", + "CMT_FIFO_WW4A3_3", + "CMT_FIFO_WW2A2_3", + "CMT_FIFO_L_LOGIC_OUTS16_2", + "CMT_FIFO_EE2A1_0", + "CMT_FIFO_L_IMUX3_2", + "CMT_FIFO_L_BYP7_3", + "CMT_FIFO_L_LOGIC_OUTS11_6", + "CMT_FIFO_L_IMUX22_11", + "CMT_FIFO_NW2A1_9", + "CMT_IN_FIFO_D91", + "CMT_FIFO_WW2A2_0", + "CMT_FIFO_L_BYP2_0", + "CMT_FIFO_LH12_1", + "CMT_FIFO_WW2END0_8", + "CMT_FIFO_L_LOGIC_OUTS14_9", + "CMT_FIFO_NW4A3_2", + "CMT_FIFO_WW2END2_11", + "CMT_FIFO_WW4C0_7", + "CMT_FIFO_EE4B2_2", + "CMT_FIFO_SW2A1_7", + "CMT_FIFO_SW2A1_2", + "CMT_FIFO_L_FAN3_8", + "CMT_FIFO_NW4END0_4", + "CMT_FIFO_L_IMUX19_3", + "CMT_FIFO_MONITOR_P_10", + "CMT_FIFO_L_LOGIC_OUTS2_0", + "CMT_IN_FIFO_D56", + "CMT_FIFO_EE4C0_1", + "CMT_FIFO_WW4A3_5", + "CMT_FIFO_LH12_9", + "CMT_IN_FIFO_Q72", + "CMT_FIFO_MONITOR_P_2", + "CMT_FIFO_SE2A1_7", + "CMT_FIFO_L_LOGIC_OUTS5_1", + "CMT_FIFO_SW4END3_8", + "CMT_FIFO_SW4A1_6", + "CMT_FIFO_SE2A2_1", + "CMT_FIFO_L_IMUX20_2", + "CMT_FIFO_LH7_6", + "CMT_OUT_FIFO_D16", + "CMT_FIFO_WL1END1_3", + "CMT_FIFO_EE4A3_5", + "CMT_FIFO_EE2BEG3_3", + "CMT_FIFO_LH5_11", + "CMT_FIFO_WW4A0_10", + "CMT_FIFO_ER1BEG1_4", + "CMT_FIFO_EE4A0_6", + "CMT_FIFO_WW2END3_5", + "CMT_FIFO_L_FAN0_6", + "CMT_FIFO_EE4BEG3_0", + "CMT_FIFO_WR1END3_0", + "CMT_FIFO_EE2BEG0_5", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", + "CMT_FIFO_L_LOGIC_OUTS22_1", + "CMT_FIFO_SE4BEG0_1", + "CMT_FIFO_WW4C3_10", + "CMT_FIFO_EE2BEG3_6", + "CMT_FIFO_L_IMUX27_9", + "CMT_FIFO_L_LOGIC_OUTS1_4", + "CMT_OUT_FIFO_Q64", + "CMT_FIFO_LH12_11", + "CMT_FIFO_SE2A2_5", + "CMT_FIFO_L_IMUX19_5", + "CMT_FIFO_L_LOGIC_OUTS5_0", + "CMT_FIFO_L_IMUX39_4", + "CMT_FIFO_SW4END2_3", + "CMT_FIFO_NW4END1_11", + "CMT_FIFO_L_IMUX1_4", + "CMT_FIFO_WR1END2_0", + "CMT_FIFO_WW4C3_2", + "CMT_FIFO_EE4C2_4", + "CMT_FIFO_NW2A2_1", + "CMT_FIFO_L_IMUX15_0", + "CMT_FIFO_SW4A0_3", + "CMT_FIFO_SE4C3_1", + "CMT_FIFO_NE4BEG0_3", + "CMT_OUT_FIFO_D90", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", + "CMT_FIFO_L_IMUX23_4", + "CMT_FIFO_L_FAN3_0", + "CMT_FIFO_SE4BEG3_11", + "CMT_FIFO_L_IMUX15_8", + "CMT_FIFO_ER1BEG2_9", + "CMT_FIFO_L_IMUX34_2", + "CMT_OUT_FIFO_D94", + "CMT_FIFO_L_IMUX20_10", + "CMT_FIFO_L_IMUX30_4", + "CMT_FIFO_L_IMUX30_9", + "CMT_FIFO_L_IMUX38_6", + "CMT_FIFO_NW2A1_3", + "CMT_FIFO_L_LOGIC_OUTS2_4", + "CMT_FIFO_EE4A3_11", + "CMT_OUT_FIFO_D95", + "CMT_FIFO_L_IMUX10_5", + "CMT_FIFO_EE4A2_10", + "CMT_OUT_FIFO_TESTWRITEDISB", + "CMT_FIFO_EL1BEG3_11", + "CMT_FIFO_EE4C0_5", + "CMT_OUT_FIFO_Q65", + "CMT_FIFO_L_LOGIC_OUTS7_7", + "CMT_IN_FIFO_D90", + "CMT_IN_FIFO_Q60", + "CMT_FIFO_ER1BEG1_9", + "CMT_FIFO_L_FAN1_0", + "CMT_FIFO_L_IMUX27_6", + "CMT_FIFO_L_IMUX34_3", + "CMT_FIFO_NE4C0_11", + "CMT_FIFO_L_CTRL1_3", + "CMT_OUT_FIFO_D92", + "CMT_FIFO_L_IMUX9_3", + "CMT_FIFO_SW4A1_4", + "CMT_FIFO_EE4C2_0", + "CMT_FIFO_EE4B1_8", + "CMT_FIFO_EE2A1_7", + "CMT_FIFO_NW4A2_5", + "CMT_FIFO_WW4A3_1", + "CMT_FIFO_WW2A2_7", + "CMT_FIFO_WR1END0_6", + "CMT_IN_FIFO_D93", + "CMT_OUT_FIFO_Q10", + "CMT_FIFO_L_LOGIC_OUTS1_5", + "CMT_FIFO_L_BYP7_8", + "CMT_FIFO_L_IMUX11_11", + "CMT_FIFO_L_IMUX13_0", + "CMT_FIFO_L_BYP1_3", + "CMT_FIFO_WW2END3_11", + "CMT_FIFO_EL1BEG1_0", + "CMT_FIFO_L_BYP2_6", + "CMT_FIFO_L_IMUX2_8", + "CMT_FIFO_NW4A3_10", + "CMT_FIFO_L_IMUX32_11", + "CMT_FIFO_WR1END3_1", + "CMT_FIFO_WW4C3_1", + "CMT_FIFO_L_IMUX17_0", + "CMT_FIFO_L_CLK1_9", + "CMT_FIFO_NE2A3_11", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", + "CMT_FIFO_NW4END0_2", + "CMT_FIFO_L_IMUX24_7", + "CMT_FIFO_WR1END3_2", + "CMT_FIFO_L_LOGIC_OUTS3_9", + "CMT_FIFO_SE4C0_4", + "CMT_FIFO_SW4END0_8", + "CMT_FIFO_L_IMUX10_3", + "CMT_FIFO_NE4BEG3_6", + "CMT_FIFO_NE2A2_10", + "CMT_IN_FIFO_Q70", + "CMT_FIFO_LH7_3", + "CMT_FIFO_L_BYP6_9", + "CMT_FIFO_L_IMUX45_9", + "CMT_FIFO_L_IMUX36_1", + "CMT_FIFO_NW2A0_9", + "CMT_FIFO_SW2A0_9", + "CMT_FIFO_WW2END3_7", + "CMT_FIFO_NE4C0_0", + "CMT_FIFO_L_LOGIC_OUTS13_11", + "CMT_IN_FIFO_Q36", + "CMT_FIFO_EE4B3_2", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", + "CMT_FIFO_NW2A3_11", + "CMT_FIFO_NE2A0_7", + "CMT_FIFO_L_IMUX46_0", + "CMT_FIFO_L_LOGIC_OUTS10_3", + "CMT_FIFO_L_FAN3_5", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", + "CMT_FIFO_L_LOGIC_OUTS6_0", + "CMT_FIFO_ER1BEG3_9", + "CMT_FIFO_SE2A1_0", + "CMT_FIFO_L_IMUX29_3", + "CMT_FIFO_L_IMUX35_5", + "CMT_FIFO_L_IMUX23_7", + "CMT_FIFO_L_LOGIC_OUTS23_2", + "CMT_FIFO_EE4C2_6", + "CMT_FIFO_EE2A0_5", + "CMT_FIFO_SE4BEG1_11", + "CMT_FIFO_L_LOGIC_OUTS0_6", + "CMT_FIFO_L_IMUX0_2", + "CMT_FIFO_L_IMUX33_3", + "CMT_FIFO_L_IMUX35_10", + "CMT_FIFO_NE2A1_11", + "CMT_FIFO_WL1END1_9", + "CMT_FIFO_WW2END1_6", + "CMT_FIFO_NW4END2_2", + "CMT_FIFO_ER1BEG1_2", + "CMT_FIFO_L_IMUX38_0", + "CMT_FIFO_WW4END1_4", + "CMT_FIFO_L_IMUX44_10", + "CMT_FIFO_L_LOGIC_OUTS22_11", + "CMT_FIFO_L_IMUX41_7", + "CMT_FIFO_WR1END0_3", + "CMT_FIFO_SW4A3_3", + "CMT_FIFO_L_IMUX33_0", + "CMT_FIFO_WW4B0_8", + "CMT_FIFO_L_IMUX28_4", + "CMT_FIFO_L_CTRL1_11", + "CMT_FIFO_L_IMUX46_2", + "CMT_FIFO_EE4C1_5", + "CMT_FIFO_L_IMUX14_5", + "CMT_FIFO_L_BYP4_11", + "CMT_FIFO_NE4BEG0_4", + "CMT_OUT_FIFO_D51", + "CMT_FIFO_L_BYP4_7", + "CMT_FIFO_L_IMUX13_2", + "CMT_IN_FIFO_Q02", + "CMT_FIFO_LH10_7", + "CMT_FIFO_L_IMUX32_9", + "CMT_OUT_FIFO_Q52", + "CMT_FIFO_L_LOGIC_OUTS6_9", + "CMT_FIFO_EE4B0_10", + "CMT_FIFO_L_IMUX15_6", + "CMT_FIFO_L_IMUX17_1", + "CMT_FIFO_NE2A2_1", + "CMT_FIFO_WL1END1_2", + "CMT_FIFO_WR1END0_4", + "CMT_FIFO_WL1END2_8", + "CMT_IN_FIFO_Q57", + "CMT_OUT_FIFO_Q32", + "CMT_FIFO_L_IMUX36_7", + "CMT_FIFO_NW4END3_10", + "CMT_FIFO_SE4BEG3_0", + "CMT_FIFO_SW4END2_10", + "CMT_FIFO_L_IMUX2_1", + "CMT_FIFO_L_IMUX4_7", + "CMT_FIFO_EE2A0_2", + "CMT_FIFO_L_IMUX36_3", + "CMT_FIFO_L_IMUX20_11", + "CMT_FIFO_L_LOGIC_OUTS0_2", + "CMT_FIFO_EE4B0_11", + "CMT_FIFO_NW4END0_3", + "CMT_OUT_FIFO_D91", + "CMT_FIFO_L_IMUX40_1", + "CMT_FIFO_WW4C3_6", + "CMT_FIFO_L_IMUX17_9", + "CMT_FIFO_L_IMUX28_10", + "CMT_FIFO_NW4A2_9", + "CMT_FIFO_NW2A1_2", + "CMT_FIFO_L_IMUX13_5", + "CMT_FIFO_L_LOGIC_OUTS20_1", + "CMT_OUT_FIFO_SCANOUT2", + "CMT_IN_FIFO_RESET", + "CMT_FIFO_EE4BEG3_10", + "CMT_FIFO_L_LOGIC_OUTS15_1", + "CMT_FIFO_L_IMUX37_7", + "CMT_FIFO_LH8_0", + "CMT_FIFO_NE4BEG2_10", + "CMT_FIFO_L_LOGIC_OUTS17_10", + "CMT_FIFO_SE2A3_8", + "CMT_FIFO_WW2END0_9", + "CMT_FIFO_LH5_5", + "CMT_FIFO_L_BYP2_8", + "CMT_FIFO_L_IMUX35_9", + "CMT_FIFO_L_BYP0_0", + "CMT_FIFO_WW2END2_1", + "CMT_FIFO_EE4B0_6", + "CMT_FIFO_MONITOR_P_4", + "CMT_FIFO_EE2A3_8", + "CMT_FIFO_L_FAN1_3", + "CMT_OUT_FIFO_Q41", + "CMT_FIFO_WL1END0_10", + "CMT_FIFO_L_IMUX31_5", + "CMT_FIFO_L_IMUX40_8", + "CMT_FIFO_L_IMUX30_5", + "CMT_FIFO_L_IMUX41_0", + "CMT_IN_FIFO_D51", + "CMT_FIFO_WR1END3_3", + "CMT_FIFO_L_CTRL1_10", + "CMT_FIFO_EE4B2_6", + "CMT_FIFO_SE2A2_9", + "CMT_FIFO_L_LOGIC_OUTS2_11", + "CMT_FIFO_L_FAN2_6", + "CMT_FIFO_L_IMUX26_7", + "CMT_FIFO_L_BYP4_0", + "CMT_FIFO_L_IMUX8_8", + "CMT_IN_FIFO_D54", + "CMT_FIFO_WW4C3_0", + "CMT_FIFO_WW4END0_3", + "CMT_FIFO_L_IMUX11_2", + "CMT_FIFO_EE4A1_0", + "CMT_FIFO_NE4C3_10", + "CMT_FIFO_WW2END3_6", + "CMT_IN_FIFO_Q15", + "CMT_FIFO_WW2END2_8", + "CMT_FIFO_L_IMUX18_6", + "CMT_FIFO_L_FAN0_2", + "CMT_FIFO_LH2_3", + "CMT_FIFO_WW4A1_8", + "CMT_FIFO_LH3_9", + "CMT_FIFO_WW4END1_9", + "CMT_FIFO_SE4C1_2", + "CMT_FIFO_EE4BEG1_10", + "CMT_FIFO_L_IMUX1_5", + "CMT_FIFO_L_CLK0_5", + "CMT_FIFO_WR1END1_8", + "CMT_FIFO_ER1BEG2_8", + "CMT_FIFO_L_LOGIC_OUTS1_9", + "CMT_FIFO_L_BYP4_10", + "CMT_FIFO_L_LOGIC_OUTS22_5", + "CMT_FIFO_L_LOGIC_OUTS2_3", + "CMT_OUT_FIFO_Q60", + "CMT_FIFO_EE4A3_4", + "CMT_FIFO_L_LOGIC_OUTS19_4", + "CMT_FIFO_WR1END2_3", + "CMT_FIFO_WW4C1_7", + "CMT_FIFO_SW4A0_9", + "CMT_FIFO_LH8_3", + "CMT_FIFO_L_IMUX41_1", + "CMT_IN_FIFO_Q86", + "CMT_FIFO_SW2A0_6", + "CMT_FIFO_L_IMUX32_5", + "CMT_FIFO_L_LOGIC_OUTS23_0", + "CMT_IN_FIFO_Q51", + "CMT_IN_FIFO_Q85", + "CMT_FIFO_L_FAN1_7", + "CMT_FIFO_WW2A0_9", + "CMT_FIFO_LH5_10", + "CMT_OUT_FIFO_Q81", + "CMT_FIFO_EL1BEG0_7", + "CMT_FIFO_L_IMUX7_7", + "CMT_FIFO_WW4B2_10", + "CMT_FIFO_MONITOR_N_2", + "CMT_FIFO_EE4A2_5", + "CMT_IN_FIFO_D52", + "CMT_FIFO_WW4A2_7", + "CMT_FIFO_L_LOGIC_OUTS18_2", + "CMT_OUT_FIFO_D72", + "CMT_FIFO_WW2END3_3", + "CMT_FIFO_SW2A2_5", + "CMT_FIFO_L_BYP1_0", + "CMT_FIFO_WW4A0_1", + "CMT_FIFO_L_LOGIC_OUTS21_4", + "CMT_FIFO_NW2A1_8", + "CMT_FIFO_L_LOGIC_OUTS21_7", + "CMT_FIFO_SE2A0_11", + "CMT_FIFO_L_IMUX30_6", + "CMT_FIFO_L_IMUX1_2", + "CMT_OUT_FIFO_Q20", + "CMT_FIFO_L_IMUX34_5", + "CMT_FIFO_L_IMUX19_6", + "CMT_FIFO_L_IMUX23_1", + "CMT_FIFO_L_IMUX23_2", + "CMT_FIFO_SW4A3_10", + "CMT_FIFO_NE4BEG2_1", + "CMT_FIFO_L_IMUX4_6", + "CMT_FIFO_L_IMUX43_4", + "CMT_FIFO_EE2A2_3", + "CMT_FIFO_L_PHASER_WRENABLE", + "CMT_FIFO_L_IMUX0_10", + "CMT_FIFO_LH2_8", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", + "CMT_FIFO_EL1BEG1_4", + "CMT_FIFO_L_IMUX12_10", + "CMT_FIFO_EE2A2_2", + "CMT_FIFO_LH11_9", + "CMT_IN_FIFO_SCANOUT2", + "CMT_FIFO_L_IMUX7_5", + "CMT_FIFO_L_IMUX26_2", + "CMT_FIFO_EE2A3_5", + "CMT_FIFO_L_LOGIC_OUTS18_11", + "CMT_FIFO_L_IMUX40_10", + "CMT_FIFO_NW2A2_10", + "CMT_OUT_FIFO_D27", + "CMT_FIFO_ER1BEG2_11", + "CMT_FIFO_L_FAN3_2", + "CMT_FIFO_LH3_11", + "FIFO_DQS_IOTOPHASER_1", + "CMT_FIFO_L_IMUX35_7", + "CMT_OUT_FIFO_Q54", + "CMT_FIFO_WW2END1_7", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", + "CMT_FIFO_WW4C0_2", + "CMT_FIFO_NE4C2_3", + "CMT_FIFO_SW4END2_6", + "CMT_FIFO_L_CTRL1_0", + "CMT_FIFO_L_BYP2_9", + "CMT_FIFO_NW2A2_0", + "CMT_FIFO_L_FAN4_1", + "CMT_FIFO_L_IMUX22_0", + "CMT_FIFO_L_IMUX5_0", + "CMT_IN_FIFO_Q47", + "CMT_FIFO_WR1END0_11", + "CMT_FIFO_L_LOGIC_OUTS16_10", + "CMT_IN_FIFO_WREN", + "CMT_FIFO_ER1BEG2_7", + "CMT_IN_FIFO_Q10", + "CMT_IN_FIFO_Q00", + "CMT_FIFO_WL1END2_6", + "CMT_FIFO_WW4C0_8", + "CMT_FIFO_L_LOGIC_OUTS20_2", + "CMT_FIFO_SE4C0_5", + "CMT_FIFO_L_IMUX22_10", + "CMT_OUT_FIFO_D10", + "CMT_FIFO_EE2A1_4", + "CMT_FIFO_EE2BEG1_10", + "CMT_FIFO_NE4BEG0_9", + "CMT_FIFO_SW4END2_2", + "CMT_FIFO_EE4B1_3", + "CMT_FIFO_L_IMUX31_1", + "CMT_FIFO_WW4END1_6", + "CMT_FIFO_L_FAN4_3", + "CMT_FIFO_L_IMUX16_6", + "CMT_FIFO_SW4END1_2", + "CMT_IN_FIFO_D62", + "CMT_FIFO_SW4END3_0", + "CMT_FIFO_L_IMUX3_1", + "CMT_FIFO_L_LOGIC_OUTS5_8", + "CMT_FIFO_L_IMUX26_1", + "CMT_FIFO_NE4BEG0_11", + "CMT_FIFO_L_FAN7_7", + "CMT_FIFO_MONITOR_N_10", + "CMT_FIFO_LH6_7", + "CMT_FIFO_WW2A2_1", + "CMT_FIFO_NW4A1_3", + "CMT_FIFO_L_LOGIC_OUTS21_8", + "CMT_FIFO_L_LOGIC_OUTS19_11", + "CMT_FIFO_L_BYP4_2", + "CMT_FIFO_EE4A3_10", + "CMT_FIFO_LH12_10", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", + "CMT_IN_FIFO_Q21", + "CMT_FIFO_EE4A2_11", + "CMT_FIFO_NE4BEG2_8", + "CMT_FIFO_NE4BEG0_8", + "CMT_FIFO_EE4BEG1_9", + "CMT_FIFO_L_LOGIC_OUTS7_11", + "CMT_FIFO_L_IMUX44_4", + "CMT_FIFO_L_IMUX28_2", + "CMT_FIFO_L_IMUX29_4", + "CMT_FIFO_EE4A0_1", + "CMT_FIFO_L_CLK1_3", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_5", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_0", + "CMT_FIFO_WW4B0_10", + "CMT_FIFO_L_IMUX9_10", + "CMT_FIFO_EE2BEG3_11", + "CMT_FIFO_SW2A1_11", + "CMT_FIFO_L_IMUX28_6", + "CMT_IN_FIFO_Q25", + "CMT_IN_FIFO_SCANOUT3", + "CMT_FIFO_EE4BEG1_5", + "CMT_FIFO_L_BYP6_0", + "CMT_FIFO_L_IMUX10_1", + "CMT_OUT_FIFO_Q53", + "CMT_FIFO_EE4A2_8", + "CMT_FIFO_L_LOGIC_OUTS9_7", + "CMT_FIFO_WW4A1_0", + "CMT_IN_FIFO_Q90", + "CMT_FIFO_L_IMUX26_11", + "CMT_FIFO_SE2A1_3", + "CMT_FIFO_SE2A3_11", + "CMT_FIFO_WW2A1_10", + "CMT_FIFO_L_LOGIC_OUTS21_1", + "CMT_FIFO_NW4END1_7", + "CMT_FIFO_L_IMUX10_7", + "CMT_FIFO_L_IMUX6_1", + "CMT_FIFO_EE4C3_3", + "CMT_FIFO_SE4BEG1_9", + "CMT_FIFO_L_IMUX22_7", + "CMT_FIFO_L_IMUX26_6", + "CMT_FIFO_WL1END1_1", + "CMT_FIFO_WW4A3_0", + "CMT_FIFO_L_IMUX10_10", + "CMT_FIFO_WW4END1_8", + "CMT_FIFO_EE4BEG0_5", + "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_9", + "CMT_FIFO_WW4END3_10", + "CMT_FIFO_WW4C3_9", + "CMT_FIFO_L_IMUX6_0", + "CMT_FIFO_L_LOGIC_OUTS8_5", + "CMT_FIFO_EL1BEG1_6", + "CMT_FIFO_L_IMUX13_11", + "CMT_OUT_FIFO_D24", + "CMT_FIFO_L_LOGIC_OUTS5_3", + "CMT_FIFO_L_IMUX8_10", + "CMT_FIFO_L_IMUX31_4", + "CMT_FIFO_L_IMUX46_6", + "CMT_FIFO_EE2BEG2_8", + "CMT_FIFO_SW2A3_1", + "CMT_FIFO_LH6_3", + "CMT_FIFO_SW2A2_7", + "CMT_FIFO_L_IMUX5_4", + "CMT_IN_FIFO_D70", + "CMT_FIFO_L_IMUX46_4", + "CMT_FIFO_L_CTRL0_4", + "CMT_FIFO_LH3_4", + "CMT_FIFO_L_IMUX6_11", + "CMT_OUT_FIFO_D75", + "CMT_FIFO_NE2A2_0", + "CMT_FIFO_ER1BEG0_1", + "CMT_OUT_FIFO_D20", + "CMT_FIFO_WW4C2_10", + "CMT_FIFO_L_LOGIC_OUTS11_0", + "CMT_IN_FIFO_Q87", + "CMT_FIFO_L_IMUX30_8", + "CMT_FIFO_L_LOGIC_OUTS22_4", + "CMT_FIFO_L_IMUX22_2", + "CMT_FIFO_L_IMUX31_0", + "CMT_FIFO_L_LOGIC_OUTS20_8", + "CMT_FIFO_L_IMUX11_1", + "CMT_FIFO_L_LOGIC_OUTS15_3", + "CMT_OUT_FIFO_Q55", + "CMT_FIFO_SE4C1_10", + "CMT_FIFO_WW4END1_11", + "CMT_FIFO_SW2A1_9", + "CMT_FIFO_WW4A2_10", + "CMT_FIFO_EE2BEG1_5", + "CMT_FIFO_L_LOGIC_OUTS7_8", + "CMT_FIFO_L_IMUX18_0", + "CMT_FIFO_SW4A0_1", + "CMT_FIFO_L_LOGIC_OUTS12_2", + "CMT_FIFO_L_IMUX18_9", + "CMT_FIFO_NW4A3_11", + "CMT_FIFO_L_LOGIC_OUTS9_2", + "CMT_FIFO_L_IMUX26_0", + "CMT_FIFO_WW4END2_7", + "CMT_FIFO_LH1_3", + "CMT_FIFO_L_LOGIC_OUTS16_6", + "CMT_FIFO_EE4B3_4", + "CMT_FIFO_L_FAN6_4", + "CMT_FIFO_L_BYP2_10", + "CMT_FIFO_L_BYP0_1", + "CMT_OUT_FIFO_D35", + "CMT_OUT_FIFO_Q66", + "CMT_FIFO_WW4C1_3", + "CMT_FIFO_NW4END3_8", + "CMT_FIFO_L_IMUX32_2", + "CMT_FIFO_L_LOGIC_OUTS23_6", + "CMT_FIFO_L_LOGIC_OUTS21_6", + "CMT_FIFO_L_IMUX16_11", + "CMT_FIFO_ER1BEG0_11", + "CMT_FIFO_L_IMUX31_2", + "CMT_FIFO_L_IMUX16_1", + "CMT_FIFO_WW4B1_10", + "CMT_FIFO_L_CLK0_4", + "CMT_FIFO_EE4A0_8", + "CMT_FIFO_L_LOGIC_OUTS10_2", + "CMT_FIFO_EE4C1_3", + "CMT_FIFO_L_FAN6_1", + "CMT_FIFO_EL1BEG0_0", + "CMT_FIFO_WW4A2_6", + "CMT_FIFO_L_LOGIC_OUTS11_5", + "CMT_FIFO_L_LOGIC_OUTS19_5", + "CMT_FIFO_L_IMUX44_3", + "CMT_IN_FIFO_D63", + "CMT_FIFO_LH1_2", + "CMT_FIFO_EE4A0_2", + "CMT_FIFO_L_IMUX21_10", + "CMT_FIFO_WR1END2_7", + "CMT_FIFO_L_IMUX38_3", + "CMT_OUT_FIFO_D83", + "CMT_FIFO_L_IMUX13_8", + "CMT_FIFO_EE4A3_3", + "CMT_FIFO_WW4B3_10", + "CMT_FIFO_EE4B2_11", + "CMT_FIFO_NE4C1_7", + "CMT_IN_FIFO_Q42", + "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", + "CMT_FIFO_L_LOGIC_OUTS18_6", + "CMT_FIFO_L_IMUX9_5", + "CMT_IN_FIFO_ALMOSTEMPTY", + "CMT_FIFO_L_IMUX18_4", + "CMT_FIFO_SE4C0_10", + "CMT_FIFO_NE2A0_8", + "CMT_FIFO_SE2A2_10", + "CMT_FIFO_SW4A1_1", + "CMT_FIFO_L_FAN4_6", + "CMT_FIFO_L_LOGIC_OUTS6_4", + "CMT_FIFO_EE4C0_8", + "CMT_FIFO_EE4B0_3", + "CMT_FIFO_L_IMUX20_7", + "CMT_FIFO_NE2A1_2", + "CMT_FIFO_SW4A0_8", + "CMT_IN_FIFO_D73", + "CMT_FIFO_WW2A0_6", + "CMT_IN_FIFO_Q80", + "CMT_FIFO_LH2_10", + "CMT_FIFO_PHASER_TO_IO_ICLK_7", + "CMT_FIFO_L_LOGIC_OUTS5_5", + "CMT_FIFO_L_IMUX43_5", + "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", + "CMT_FIFO_LH12_0", + "CMT_FIFO_L_LOGIC_OUTS7_5", + "CMT_FIFO_L_LOGIC_OUTS1_10", + "CMT_FIFO_SW4A2_5", + "CMT_FIFO_WR1END2_2", + "CMT_FIFO_SE4C1_11", + "CMT_FIFO_L_IMUX25_10", + "CMT_FIFO_L_IMUX11_3", + "CMT_OUT_FIFO_D42", + "CMT_FIFO_NW4A0_8", + "CMT_FIFO_L_FAN7_1", + "CMT_FIFO_L_LOGIC_OUTS22_3", + "CMT_FIFO_EE2BEG0_10", + "CMT_FIFO_EE4B1_6", + "CMT_FIFO_NW2A1_4", + "CMT_FIFO_EL1BEG3_8", + "CMT_FIFO_SW4A1_11", + "CMT_FIFO_SE4C2_8", + "CMT_IN_FIFO_D66", + "CMT_FIFO_NE4C1_9", + "CMT_FIFO_NW4A1_2", + "CMT_FIFO_L_LOGIC_OUTS16_4", + "CMT_FIFO_L_IMUX7_3", + "CMT_OUT_FIFO_D61", + "CMT_FIFO_L_LOGIC_OUTS4_3", + "CMT_FIFO_L_LOGIC_OUTS15_7", + "CMT_FIFO_L_BYP5_9", + "CMT_FIFO_NE2A0_9", + "CMT_IN_FIFO_Q50", + "CMT_FIFO_LH11_1", + "CMT_FIFO_L_LOGIC_OUTS23_8", + "CMT_OUT_FIFO_D70", + "CMT_FIFO_WR1END1_11", + "CMT_FIFO_NW4END3_11", + "CMT_FIFO_L_IMUX37_8", + "CMT_FIFO_L_CTRL1_1", + "CMT_FIFO_NE4BEG3_1", + "CMT_FIFO_L_IMUX32_4", + "CMT_FIFO_L_LOGIC_OUTS12_5", + "CMT_FIFO_L_IMUX39_5", + "CMT_FIFO_NE4BEG3_5", + "CMT_FIFO_L_IMUX36_6", + "CMT_OUT_FIFO_D87" + ], + "tile_type": "CMT_FIFO_R", + "sites": [ + { + "site_pins": { + "D85": "CMT_OUT_FIFO_D85", + "RESET": "CMT_OUT_FIFO_RESET", + "D52": "CMT_OUT_FIFO_D52", + "Q21": "CMT_OUT_FIFO_Q21", + "D07": "CMT_OUT_FIFO_D07", + "D24": "CMT_OUT_FIFO_D24", + "D97": "CMT_OUT_FIFO_D97", + "D47": "CMT_OUT_FIFO_D47", + "D76": "CMT_OUT_FIFO_D76", + "D94": "CMT_OUT_FIFO_D94", + "EMPTY": "CMT_OUT_FIFO_EMPTY", + "D75": "CMT_OUT_FIFO_D75", + "D66": "CMT_OUT_FIFO_D66", + "SCANIN2": "CMT_OUT_FIFO_SCANIN2", + "D30": "CMT_OUT_FIFO_D30", + "D35": "CMT_OUT_FIFO_D35", + "D53": "CMT_OUT_FIFO_D53", + "SCANOUT2": "CMT_OUT_FIFO_SCANOUT2", + "D54": "CMT_OUT_FIFO_D54", + "Q50": "CMT_OUT_FIFO_Q50", + "D42": "CMT_OUT_FIFO_D42", + "Q54": "CMT_OUT_FIFO_Q54", + "Q81": "CMT_OUT_FIFO_Q81", + "Q40": "CMT_OUT_FIFO_Q40", + "Q72": "CMT_OUT_FIFO_Q72", + "D82": "CMT_OUT_FIFO_D82", + "D43": "CMT_OUT_FIFO_D43", + "Q66": "CMT_OUT_FIFO_Q66", + "Q22": "CMT_OUT_FIFO_Q22", + "Q91": "CMT_OUT_FIFO_Q91", + "Q56": "CMT_OUT_FIFO_Q56", + "D13": "CMT_OUT_FIFO_D13", + "D45": "CMT_OUT_FIFO_D45", + "D51": "CMT_OUT_FIFO_D51", + "Q90": "CMT_OUT_FIFO_Q90", + "D01": "CMT_OUT_FIFO_D01", + "D41": "CMT_OUT_FIFO_D41", + "FULL": "CMT_OUT_FIFO_FULL", + "D32": "CMT_OUT_FIFO_D32", + "D46": "CMT_OUT_FIFO_D46", + "D71": "CMT_OUT_FIFO_D71", + "D34": "CMT_OUT_FIFO_D34", + "SCANIN0": "CMT_OUT_FIFO_SCANIN0", + "D65": "CMT_OUT_FIFO_D65", + "D96": "CMT_OUT_FIFO_D96", + "WREN": "CMT_OUT_FIFO_WREN", + "Q60": "CMT_OUT_FIFO_Q60", + "Q03": "CMT_OUT_FIFO_Q03", + "D37": "CMT_OUT_FIFO_D37", + "Q61": "CMT_OUT_FIFO_Q61", + "Q41": "CMT_OUT_FIFO_Q41", + "Q20": "CMT_OUT_FIFO_Q20", + "Q30": "CMT_OUT_FIFO_Q30", + "D61": "CMT_OUT_FIFO_D61", + "Q12": "CMT_OUT_FIFO_Q12", + "D44": "CMT_OUT_FIFO_D44", + "Q00": "CMT_OUT_FIFO_Q00", + "D63": "CMT_OUT_FIFO_D63", + "Q92": "CMT_OUT_FIFO_Q92", + "D20": "CMT_OUT_FIFO_D20", + "SCANOUT3": "CMT_OUT_FIFO_SCANOUT3", + "D93": "CMT_OUT_FIFO_D93", + "D31": "CMT_OUT_FIFO_D31", + "D06": "CMT_OUT_FIFO_D06", + "TESTWRITEDISB": "CMT_OUT_FIFO_TESTWRITEDISB", + "D95": "CMT_OUT_FIFO_D95", + "D84": "CMT_OUT_FIFO_D84", + "Q82": "CMT_OUT_FIFO_Q82", + "Q67": "CMT_OUT_FIFO_Q67", + "Q93": "CMT_OUT_FIFO_Q93", + "D73": "CMT_OUT_FIFO_D73", + "D10": "CMT_OUT_FIFO_D10", + "D72": "CMT_OUT_FIFO_D72", + "D62": "CMT_OUT_FIFO_D62", + "D81": "CMT_OUT_FIFO_D81", + "Q51": "CMT_OUT_FIFO_Q51", + "D12": "CMT_OUT_FIFO_D12", + "RDCLK": "CMT_OUT_FIFO_RDCLK", + "D05": "CMT_OUT_FIFO_D05", + "WRCLK": "CMT_OUT_FIFO_WRCLK", + "D87": "CMT_OUT_FIFO_D87", + "D16": "CMT_OUT_FIFO_D16", + "D21": "CMT_OUT_FIFO_D21", + "D23": "CMT_OUT_FIFO_D23", + "Q02": "CMT_OUT_FIFO_Q02", + "D83": "CMT_OUT_FIFO_D83", + "Q80": "CMT_OUT_FIFO_Q80", + "D00": "CMT_OUT_FIFO_D00", + "Q57": "CMT_OUT_FIFO_Q57", + "D40": "CMT_OUT_FIFO_D40", + "SCANIN3": "CMT_OUT_FIFO_SCANIN3", + "D91": "CMT_OUT_FIFO_D91", + "D74": "CMT_OUT_FIFO_D74", + "SCANOUT1": "CMT_OUT_FIFO_SCANOUT1", + "Q52": "CMT_OUT_FIFO_Q52", + "Q70": "CMT_OUT_FIFO_Q70", + "D70": "CMT_OUT_FIFO_D70", + "Q63": "CMT_OUT_FIFO_Q63", + "D57": "CMT_OUT_FIFO_D57", + "ALMOSTFULL": "CMT_OUT_FIFO_ALMOSTFULL", + "D22": "CMT_OUT_FIFO_D22", + "D25": "CMT_OUT_FIFO_D25", + "Q11": "CMT_OUT_FIFO_Q11", + "D36": "CMT_OUT_FIFO_D36", + "ALMOSTEMPTY": "CMT_OUT_FIFO_ALMOSTEMPTY", + "RDEN": "CMT_OUT_FIFO_RDEN", + "SCANENB": "CMT_OUT_FIFO_SCANENB", + "Q31": "CMT_OUT_FIFO_Q31", + "Q62": "CMT_OUT_FIFO_Q62", + "D11": "CMT_OUT_FIFO_D11", + "Q23": "CMT_OUT_FIFO_Q23", + "Q13": "CMT_OUT_FIFO_Q13", + "D14": "CMT_OUT_FIFO_D14", + "D56": "CMT_OUT_FIFO_D56", + "D92": "CMT_OUT_FIFO_D92", + "D17": "CMT_OUT_FIFO_D17", + "TESTMODEB": "CMT_OUT_FIFO_TESTMODEB", + "Q73": "CMT_OUT_FIFO_Q73", + "Q33": "CMT_OUT_FIFO_Q33", + "Q10": "CMT_OUT_FIFO_Q10", + "D50": "CMT_OUT_FIFO_D50", + "D90": "CMT_OUT_FIFO_D90", + "Q71": "CMT_OUT_FIFO_Q71", + "Q64": "CMT_OUT_FIFO_Q64", + "D03": "CMT_OUT_FIFO_D03", + "SCANIN1": "CMT_OUT_FIFO_SCANIN1", + "Q53": "CMT_OUT_FIFO_Q53", + "D02": "CMT_OUT_FIFO_D02", + "D27": "CMT_OUT_FIFO_D27", + "Q65": "CMT_OUT_FIFO_Q65", + "D15": "CMT_OUT_FIFO_D15", + "D55": "CMT_OUT_FIFO_D55", + "D33": "CMT_OUT_FIFO_D33", + "D26": "CMT_OUT_FIFO_D26", + "Q42": "CMT_OUT_FIFO_Q42", + "Q32": "CMT_OUT_FIFO_Q32", + "SCANOUT0": "CMT_OUT_FIFO_SCANOUT0", + "D04": "CMT_OUT_FIFO_D04", + "D67": "CMT_OUT_FIFO_D67", + "Q43": "CMT_OUT_FIFO_Q43", + "Q01": "CMT_OUT_FIFO_Q01", + "Q55": "CMT_OUT_FIFO_Q55", + "D77": "CMT_OUT_FIFO_D77", + "D64": "CMT_OUT_FIFO_D64", + "TESTREADDISB": "CMT_OUT_FIFO_TESTREADDISB", + "D60": "CMT_OUT_FIFO_D60", + "D80": "CMT_OUT_FIFO_D80", + "Q83": "CMT_OUT_FIFO_Q83", + "D86": "CMT_OUT_FIFO_D86" + }, + "type": "OUT_FIFO", + "prefix": "OUT_FIFO", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "Q74": "CMT_IN_FIFO_Q74", + "RESET": "CMT_IN_FIFO_RESET", + "D52": "CMT_IN_FIFO_D52", + "Q21": "CMT_IN_FIFO_Q21", + "Q36": "CMT_IN_FIFO_Q36", + "Q16": "CMT_IN_FIFO_Q16", + "Q34": "CMT_IN_FIFO_Q34", + "Q67": "CMT_IN_FIFO_Q67", + "EMPTY": "CMT_IN_FIFO_EMPTY", + "D66": "CMT_IN_FIFO_D66", + "SCANIN2": "CMT_IN_FIFO_SCANIN2", + "Q04": "CMT_IN_FIFO_Q04", + "D53": "CMT_IN_FIFO_D53", + "SCANOUT2": "CMT_IN_FIFO_SCANOUT2", + "Q43": "CMT_IN_FIFO_Q43", + "Q50": "CMT_IN_FIFO_Q50", + "D42": "CMT_IN_FIFO_D42", + "Q01": "CMT_IN_FIFO_Q01", + "Q54": "CMT_IN_FIFO_Q54", + "Q81": "CMT_IN_FIFO_Q81", + "Q40": "CMT_IN_FIFO_Q40", + "Q72": "CMT_IN_FIFO_Q72", + "D82": "CMT_IN_FIFO_D82", + "Q06": "CMT_IN_FIFO_Q06", + "Q66": "CMT_IN_FIFO_Q66", + "Q22": "CMT_IN_FIFO_Q22", + "Q91": "CMT_IN_FIFO_Q91", + "Q56": "CMT_IN_FIFO_Q56", + "D13": "CMT_IN_FIFO_D13", + "Q93": "CMT_IN_FIFO_Q93", + "D51": "CMT_IN_FIFO_D51", + "Q90": "CMT_IN_FIFO_Q90", + "D01": "CMT_IN_FIFO_D01", + "D41": "CMT_IN_FIFO_D41", + "FULL": "CMT_IN_FIFO_FULL", + "D32": "CMT_IN_FIFO_D32", + "Q37": "CMT_IN_FIFO_Q37", + "Q75": "CMT_IN_FIFO_Q75", + "Q76": "CMT_IN_FIFO_Q76", + "D71": "CMT_IN_FIFO_D71", + "Q85": "CMT_IN_FIFO_Q85", + "D73": "CMT_IN_FIFO_D73", + "D65": "CMT_IN_FIFO_D65", + "WREN": "CMT_IN_FIFO_WREN", + "Q60": "CMT_IN_FIFO_Q60", + "Q03": "CMT_IN_FIFO_Q03", + "Q77": "CMT_IN_FIFO_Q77", + "Q61": "CMT_IN_FIFO_Q61", + "Q41": "CMT_IN_FIFO_Q41", + "Q20": "CMT_IN_FIFO_Q20", + "Q17": "CMT_IN_FIFO_Q17", + "D61": "CMT_IN_FIFO_D61", + "Q12": "CMT_IN_FIFO_Q12", + "D54": "CMT_IN_FIFO_D54", + "Q00": "CMT_IN_FIFO_Q00", + "D63": "CMT_IN_FIFO_D63", + "Q44": "CMT_IN_FIFO_Q44", + "Q92": "CMT_IN_FIFO_Q92", + "D20": "CMT_IN_FIFO_D20", + "Q86": "CMT_IN_FIFO_Q86", + "SCANOUT3": "CMT_IN_FIFO_SCANOUT3", + "D93": "CMT_IN_FIFO_D93", + "D31": "CMT_IN_FIFO_D31", + "Q87": "CMT_IN_FIFO_Q87", + "D67": "CMT_IN_FIFO_D67", + "Q82": "CMT_IN_FIFO_Q82", + "D50": "CMT_IN_FIFO_D50", + "Q14": "CMT_IN_FIFO_Q14", + "D10": "CMT_IN_FIFO_D10", + "D72": "CMT_IN_FIFO_D72", + "D62": "CMT_IN_FIFO_D62", + "D81": "CMT_IN_FIFO_D81", + "Q51": "CMT_IN_FIFO_Q51", + "D12": "CMT_IN_FIFO_D12", + "RDCLK": "CMT_IN_FIFO_RDCLK", + "Q94": "CMT_IN_FIFO_Q94", + "Q30": "CMT_IN_FIFO_Q30", + "WRCLK": "CMT_IN_FIFO_WRCLK", + "D21": "CMT_IN_FIFO_D21", + "D23": "CMT_IN_FIFO_D23", + "Q02": "CMT_IN_FIFO_Q02", + "D83": "CMT_IN_FIFO_D83", + "Q80": "CMT_IN_FIFO_Q80", + "Q46": "CMT_IN_FIFO_Q46", + "D00": "CMT_IN_FIFO_D00", + "Q24": "CMT_IN_FIFO_Q24", + "Q57": "CMT_IN_FIFO_Q57", + "D40": "CMT_IN_FIFO_D40", + "SCANIN3": "CMT_IN_FIFO_SCANIN3", + "D91": "CMT_IN_FIFO_D91", + "D30": "CMT_IN_FIFO_D30", + "Q52": "CMT_IN_FIFO_Q52", + "Q26": "CMT_IN_FIFO_Q26", + "Q70": "CMT_IN_FIFO_Q70", + "D70": "CMT_IN_FIFO_D70", + "TESTWRITEDISB": "CMT_IN_FIFO_TESTWRITEDISB", + "Q63": "CMT_IN_FIFO_Q63", + "D57": "CMT_IN_FIFO_D57", + "ALMOSTFULL": "CMT_IN_FIFO_ALMOSTFULL", + "D22": "CMT_IN_FIFO_D22", + "Q47": "CMT_IN_FIFO_Q47", + "Q07": "CMT_IN_FIFO_Q07", + "Q11": "CMT_IN_FIFO_Q11", + "ALMOSTEMPTY": "CMT_IN_FIFO_ALMOSTEMPTY", + "RDEN": "CMT_IN_FIFO_RDEN", + "SCANENB": "CMT_IN_FIFO_SCANENB", + "Q31": "CMT_IN_FIFO_Q31", + "Q62": "CMT_IN_FIFO_Q62", + "Q15": "CMT_IN_FIFO_Q15", + "D11": "CMT_IN_FIFO_D11", + "Q23": "CMT_IN_FIFO_Q23", + "Q13": "CMT_IN_FIFO_Q13", + "Q25": "CMT_IN_FIFO_Q25", + "Q33": "CMT_IN_FIFO_Q33", + "D56": "CMT_IN_FIFO_D56", + "D92": "CMT_IN_FIFO_D92", + "TESTMODEB": "CMT_IN_FIFO_TESTMODEB", + "Q73": "CMT_IN_FIFO_Q73", + "Q45": "CMT_IN_FIFO_Q45", + "Q10": "CMT_IN_FIFO_Q10", + "D02": "CMT_IN_FIFO_D02", + "Q71": "CMT_IN_FIFO_Q71", + "Q64": "CMT_IN_FIFO_Q64", + "D03": "CMT_IN_FIFO_D03", + "SCANIN1": "CMT_IN_FIFO_SCANIN1", + "Q27": "CMT_IN_FIFO_Q27", + "Q53": "CMT_IN_FIFO_Q53", + "Q35": "CMT_IN_FIFO_Q35", + "D90": "CMT_IN_FIFO_D90", + "Q97": "CMT_IN_FIFO_Q97", + "Q65": "CMT_IN_FIFO_Q65", + "D55": "CMT_IN_FIFO_D55", + "D33": "CMT_IN_FIFO_D33", + "Q95": "CMT_IN_FIFO_Q95", + "Q42": "CMT_IN_FIFO_Q42", + "Q32": "CMT_IN_FIFO_Q32", + "SCANOUT0": "CMT_IN_FIFO_SCANOUT0", + "Q05": "CMT_IN_FIFO_Q05", + "SCANOUT1": "CMT_IN_FIFO_SCANOUT1", + "D43": "CMT_IN_FIFO_D43", + "Q55": "CMT_IN_FIFO_Q55", + "D64": "CMT_IN_FIFO_D64", + "TESTREADDISB": "CMT_IN_FIFO_TESTREADDISB", + "D60": "CMT_IN_FIFO_D60", + "D80": "CMT_IN_FIFO_D80", + "Q96": "CMT_IN_FIFO_Q96", + "SCANIN0": "CMT_IN_FIFO_SCANIN0", + "Q84": "CMT_IN_FIFO_Q84", + "Q83": "CMT_IN_FIFO_Q83" + }, + "type": "IN_FIFO", + "prefix": "IN_FIFO", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_PMV.json b/artix7/tile_type_CMT_PMV.json index b799816..da57b25 100644 --- a/artix7/tile_type_CMT_PMV.json +++ b/artix7/tile_type_CMT_PMV.json @@ -1,230 +1,230 @@ { - "wires": [ - "CMT_PMV_NW2A3", - "CMT_PMV_LOGIC_OUTS23", - "CMT_PMV_SW4END3", - "CMT_PMV_ER1BEG2", - "CMT_PMV_FAN4", - "CMT_PMV_LH6", - "CMT_PMV_IMUX17", - "CMT_PMV_NW4A1", - "CMT_PMV_WW4C3", - "CMT_PMV_NE2A3", - "CMT_PMV_WW2A3", - "CMT_PMV_EE2A2", - "CMT_PMV_IMUX32", - "CMT_PMV_IMUX46", - "CMT_PMV_SE4C0", - "CMT_PMV_IMUX38", - "CMT_PMV_WR1END1", - "CMT_PMV_SW4A3", - "CMT_PMV_SW2A0", - "CMT_PMV_SW4A2", - "CMT_PMV_BYP7", - "CMT_PMV_BYP6", - "CMT_PMV_IMUX22", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV", - "CMT_PMV_IMUX0", - "CMT_PMV_WW4END0", - "CMT_PMV_IMUX4", - "CMT_PMV_LOGIC_OUTS13", - "CMT_PMV_IMUX30", - "CMT_PMV_IMUX10", - "CMT_PMV_IMUX45", - "CMT_PMV_WR1END3", - "CMT_PMV_EE4B0", - "CMT_PMV_LOGIC_OUTS22", - "CMT_PMV_LOGIC_OUTS14", - "CMT_PMV_IMUX3", - "CMT_PMV_IMUX26", - "CMT_PMV_LH3", - "CMT_PMV_IMUX23", - "CMT_PMV_EL1BEG0", - "CMT_PMV_LOGIC_OUTS21", - "CMT_PMV_FAN2", - "CMT_PMV_IMUX28", - "CMT_PMV_WW2A0", - "CMT_PMV_NW4A0", - "CMT_PMV_WW4END1", - "CMT_PMV_BYP3", - "CMT_PMV_IMUX29", - "CMT_PMV_WL1END1", - "CMT_PMV_SW4END1", - "CMT_PMV_LOGIC_OUTS16", - "CMT_PMV_IMUX35", - "CMT_PMV_LOGIC_OUTS15", - "CMT_PMV_EE2A0", - "CMT_PMV_EE4A3", - "CMT_PMV_NW2A2", - "CMT_PMV_IMUX24", - "CMT_PMV_IMUX44", - "CMT_PMV_LOGIC_OUTS5", - "CMT_PMV_BYP5", - "CMT_PMV_LOGIC_OUTS3", - "CMT_PMV_WW4END2", - "CMT_PMV_WL1END3", - "CMT_PMV_EE2BEG3", - "CMT_PMV_IMUX7", - "CMT_PMV_WW2A2", - "CMT_PMV_IMUX9", - "CMT_PMV_SE4BEG0", - "CMT_PMV_EE4BEG1", - "CMT_PMV_IMUX27", - "CMT_PMV_EE4C3", - "CMT_PMV_IMUX36", - "CMT_PMV_IMUX21", - "CMT_PMV_WL1END2", - "CMT_PMV_LOGIC_OUTS18", - "CMT_PMV_WW4A0", - "CMT_PMV_FAN7", - "CMT_PMV_WW4C2", - "CMT_PMV_LH5", - "CMT_PMV_SW4END0", - "CMT_PMV_EE2BEG0", - "CMT_PMV_LOGIC_OUTS2", - "CMT_PMV_IMUX37", - "CMT_PMV_EE2BEG2", - "CMT_PMV_NW4END1", - "CMT_PMV_EE4BEG3", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", - "CMT_PMV_BYP4", - "CMT_PMV_BYP2", - "CMT_PMV_MONITOR_N", - "CMT_PMV_NE4C2", - "CMT_PMV_LOGIC_OUTS12", - "CMT_PMV_WW4A3", - "CMT_PMV_IMUX15", - "CMT_PMV_SE4C1", - "CMT_PMV_EL1BEG2", - "CMT_PMV_IMUX33", - "CMT_PMV_LOGIC_OUTS0", - "CMT_PMV_FAN1", - "CMT_PMV_NE4C0", - "CMT_PMV_IMUX14", - "CMT_PMV_IMUX20", - "CMT_PMV_NW4END2", - "CMT_PMV_SW4A1", - "CMT_PMV_IMUX8", - "CMT_PMV_LH2", - "CMT_PMV_IMUX6", - "CMT_PMV_IMUX2", - "CMT_PMV_LOGIC_OUTS1", - "CMT_PMV_ER1BEG0", - "CMT_PMV_SE2A3", - "CMT_PMV_LH7", - "CMT_PMV_LH10", - "CMT_PMV_LOGIC_OUTS20", - "CMT_PMV_EE4B3", - "CMT_PMV_EL1BEG3", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "CMT_PMV_EE4C1", - "CMT_PMV_WR1END2", - "CMT_PMV_IMUX16", - "CMT_PMV_WW4A1", - "CMT_PMV_WW4END3", - "CMT_PMV_ER1BEG3", - "CMT_PMV_SE4BEG2", - "CMT_PMV_CLK0", - "CMT_PMV_NE4BEG0", - "CMT_PMV_LOGIC_OUTS7", - "CMT_PMV_EE4C0", - "CMT_PMV_FAN0", - "CMT_PMV_NE2A1", - "CMT_PMV_WR1END0", - "CMT_PMV_NW2A1", - "CMT_PMV_IMUX34", - "CMT_PMV_CTRL1", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "CMT_PMV_SW4A0", - "CMT_PMV_EE4BEG0", - "CMT_PMV_LH9", - "CMT_PMV_IMUX1", - "CMT_PMV_IMUX40", - "CMT_PMV_WW4C0", - "CMT_PMV_SE4C3", - "CMT_PMV_NE2A2", - "CMT_PMV_EE4A2", - "CMT_PMV_NE4BEG3", - "CMT_PMV_WW2END0", - "CMT_PMV_CTRL0", - "CMT_PMV_LH11", - "CMT_PMV_LH8", - "CMT_PMV_WW4B1", - "CMT_PMV_IMUX31", - "CMT_PMV_WW2END1", - "CMT_PMV_IMUX5", - "CMT_PMV_SW2A3", - "CMT_PMV_IMUX13", - "CMT_PMV_NW4A2", - "CMT_PMV_NW4END0", - "CMT_PMV_IMUX11", - "CMT_PMV_CLK1", - "CMT_PMV_MONITOR_P", - "CMT_PMV_LOGIC_OUTS9", - "CMT_PMV_IMUX19", - "CMT_PMV_EE4BEG2", - "CMT_PMV_LOGIC_OUTS10", - "CMT_PMV_SE2A1", - "CMT_PMV_FAN6", - "CMT_PMV_FAN5", - "CMT_PMV_EE4B2", - "CMT_PMV_EE2A1", - "CMT_PMV_LH12", - "CMT_PMV_IMUX18", - "CMT_PMV_LH4", - "CMT_PMV_NW4END3", - "CMT_PMV_EE2BEG1", - "CMT_PMV_WW2END3", - "CMT_PMV_WW4A2", - "CMT_PMV_BYP1", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "CMT_PMV_EE4C2", - "CMT_PMV_NE4C3", - "CMT_PMV_NW2A0", - "CMT_PMV_NE4BEG1", - "CMT_PMV_SW4END2", - "CMT_PMV_NE4C1", - "CMT_PMV_LH1", - "CMT_PMV_EE4A0", - "CMT_PMV_WL1END0", - "CMT_PMV_ER1BEG1", - "CMT_PMV_WW2A1", - "CMT_PMV_IMUX42", - "CMT_PMV_EL1BEG1", - "CMT_PMV_NE4BEG2", - "CMT_PMV_EE4A1", - "CMT_PMV_SE2A2", - "CMT_PMV_SE4BEG3", - "CMT_PMV_WW4C1", - "CMT_PMV_IMUX43", - "CMT_PMV_LOGIC_OUTS6", - "CMT_PMV_BYP0", - "CMT_PMV_IMUX41", - "CMT_PMV_EE4B1", - "CMT_PMV_WW4B0", - "CMT_PMV_SE2A0", - "CMT_PMV_IMUX39", - "CMT_PMV_LOGIC_OUTS4", - "CMT_PMV_LOGIC_OUTS19", - "CMT_PMV_IMUX25", - "CMT_PMV_NW4A3", - "CMT_PMV_WW2END2", - "CMT_PMV_NE2A0", - "CMT_PMV_SW2A2", - "CMT_PMV_WW4B3", - "CMT_PMV_IMUX12", - "CMT_PMV_LOGIC_OUTS8", - "CMT_PMV_LOGIC_OUTS11", - "CMT_PMV_WW4B2", - "CMT_PMV_EE2A3", - "CMT_PMV_SW2A1", - "CMT_PMV_FAN3", - "CMT_PMV_SE4C2", - "CMT_PMV_IMUX47", - "CMT_PMV_SE4BEG1", - "CMT_PMV_LOGIC_OUTS17" - ], - "sites": [], "pips": {}, - "tile_type": "CMT_PMV" + "wires": [ + "CMT_PMV_IMUX16", + "CMT_PMV_LOGIC_OUTS17", + "CMT_PMV_LOGIC_OUTS10", + "CMT_PMV_IMUX29", + "CMT_PMV_BYP1", + "CMT_PMV_BYP0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "CMT_PMV_LOGIC_OUTS7", + "CMT_PMV_IMUX45", + "CMT_PMV_LOGIC_OUTS13", + "CMT_PMV_SW2A0", + "CMT_PMV_LOGIC_OUTS11", + "CMT_PMV_WW4C3", + "CMT_PMV_NW2A3", + "CMT_PMV_NE4BEG2", + "CMT_PMV_SW4A3", + "CMT_PMV_EE4C1", + "CMT_PMV_EE4B2", + "CMT_PMV_IMUX39", + "CMT_PMV_SW2A1", + "CMT_PMV_LOGIC_OUTS21", + "CMT_PMV_WW2END3", + "CMT_PMV_IMUX22", + "CMT_PMV_LH5", + "CMT_PMV_IMUX40", + "CMT_PMV_SW4A2", + "CMT_PMV_WW4A3", + "CMT_PMV_NW2A0", + "CMT_PMV_SE4C2", + "CMT_PMV_NW4END0", + "CMT_PMV_LH9", + "CMT_PMV_LOGIC_OUTS1", + "CMT_PMV_EE4A2", + "CMT_PMV_SE2A2", + "CMT_PMV_ER1BEG1", + "CMT_PMV_NW4A2", + "CMT_PMV_SE4C0", + "CMT_PMV_ER1BEG2", + "CMT_PMV_NW4A3", + "CMT_PMV_NW4END3", + "CMT_PMV_WW4B1", + "CMT_PMV_EE2BEG1", + "CMT_PMV_EE4BEG1", + "CMT_PMV_WL1END0", + "CMT_PMV_SE4BEG0", + "CMT_PMV_SW4A1", + "CMT_PMV_IMUX7", + "CMT_PMV_SW4END0", + "CMT_PMV_EE4C3", + "CMT_PMV_IMUX43", + "CMT_PMV_NW2A1", + "CMT_PMV_IMUX8", + "CMT_PMV_IMUX19", + "CMT_PMV_LH1", + "CMT_PMV_IMUX1", + "CMT_PMV_WR1END3", + "CMT_PMV_IMUX12", + "CMT_PMV_SE4BEG2", + "CMT_PMV_LH12", + "CMT_PMV_IMUX10", + "CMT_PMV_LOGIC_OUTS12", + "CMT_PMV_WW4B0", + "CMT_PMV_SE2A1", + "CMT_PMV_IMUX21", + "CMT_PMV_IMUX25", + "CMT_PMV_EE4BEG2", + "CMT_PMV_LOGIC_OUTS16", + "CMT_PMV_LOGIC_OUTS19", + "CMT_PMV_FAN4", + "CMT_PMV_SW2A3", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", + "CMT_PMV_LH10", + "CMT_PMV_CTRL0", + "CMT_PMV_IMUX20", + "CMT_PMV_WW4B3", + "CMT_PMV_IMUX4", + "CMT_PMV_NE2A2", + "CMT_PMV_LOGIC_OUTS5", + "CMT_PMV_MONITOR_P", + "CMT_PMV_CLK0", + "CMT_PMV_LOGIC_OUTS14", + "CMT_PMV_EE4B0", + "CMT_PMV_WW4A2", + "CMT_PMV_WW4END3", + "CMT_PMV_LOGIC_OUTS23", + "CMT_PMV_IMUX32", + "CMT_PMV_IMUX42", + "CMT_PMV_LH4", + "CMT_PMV_LOGIC_OUTS2", + "CMT_PMV_LH8", + "CMT_PMV_SE4BEG1", + "CMT_PMV_IMUX27", + "CMT_PMV_LH2", + "CMT_PMV_BYP3", + "CMT_PMV_WW4B2", + "CMT_PMV_FAN3", + "CMT_PMV_FAN6", + "CMT_PMV_EE4B3", + "CMT_PMV_WW4C2", + "CMT_PMV_ER1BEG0", + "CMT_PMV_SE4C1", + "CMT_PMV_FAN7", + "CMT_PMV_MONITOR_N", + "CMT_PMV_WW2A0", + "CMT_PMV_EE4A1", + "CMT_PMV_BYP5", + "CMT_PMV_IMUX28", + "CMT_PMV_IMUX15", + "CMT_PMV_WW2A1", + "CMT_PMV_WW4A0", + "CMT_PMV_CTRL1", + "CMT_PMV_IMUX3", + "CMT_PMV_CLK1", + "CMT_PMV_EE2A2", + "CMT_PMV_WW2END2", + "CMT_PMV_NE4C1", + "CMT_PMV_NE2A3", + "CMT_PMV_NE2A1", + "CMT_PMV_IMUX37", + "CMT_PMV_EE2BEG3", + "CMT_PMV_LOGIC_OUTS6", + "CMT_PMV_LOGIC_OUTS9", + "CMT_PMV_LOGIC_OUTS4", + "CMT_PMV_NE4BEG3", + "CMT_PMV_WR1END0", + "CMT_PMV_BYP6", + "CMT_PMV_FAN0", + "CMT_PMV_IMUX6", + "CMT_PMV_WW4C1", + "CMT_PMV_NW2A2", + "CMT_PMV_SW2A2", + "CMT_PMV_IMUX36", + "CMT_PMV_SW4A0", + "CMT_PMV_IMUX35", + "CMT_PMV_FAN1", + "CMT_PMV_IMUX11", + "CMT_PMV_EE4BEG0", + "CMT_PMV_EE2A3", + "CMT_PMV_WW4C0", + "CMT_PMV_NE4BEG1", + "CMT_PMV_NW4END1", + "CMT_PMV_IMUX38", + "CMT_PMV_EE4A0", + "CMT_PMV_NW4A0", + "CMT_PMV_BYP4", + "CMT_PMV_NW4END2", + "CMT_PMV_EE2A1", + "CMT_PMV_WW4END0", + "CMT_PMV_WW4END2", + "CMT_PMV_WL1END2", + "CMT_PMV_SE4C3", + "CMT_PMV_IMUX13", + "CMT_PMV_WW2A2", + "CMT_PMV_LOGIC_OUTS8", + "CMT_PMV_EE4C2", + "CMT_PMV_EL1BEG1", + "CMT_PMV_LOGIC_OUTS0", + "CMT_PMV_SW4END3", + "CMT_PMV_IMUX2", + "CMT_PMV_IMUX14", + "CMT_PMV_EL1BEG0", + "CMT_PMV_IMUX0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "CMT_PMV_EE2BEG2", + "CMT_PMV_IMUX47", + "CMT_PMV_EE4BEG3", + "CMT_PMV_IMUX34", + "CMT_PMV_IMUX46", + "CMT_PMV_WW4A1", + "CMT_PMV_LOGIC_OUTS18", + "CMT_PMV_WW2END1", + "CMT_PMV_SE2A0", + "CMT_PMV_WW4END1", + "CMT_PMV_IMUX26", + "CMT_PMV_NE4C3", + "CMT_PMV_IMUX33", + "CMT_PMV_EE4A3", + "L_TERM_INT_PHASER_TO_IO_OCLK", + "CMT_PMV_LH3", + "CMT_PMV_WR1END2", + "CMT_PMV_EE2BEG0", + "CMT_PMV_BYP2", + "CMT_PMV_NE4C0", + "CMT_PMV_BYP7", + "CMT_PMV_EE2A0", + "CMT_PMV_WW2END0", + "CMT_PMV_SW4END1", + "CMT_PMV_NW4A1", + "CMT_PMV_EE4B1", + "CMT_PMV_ER1BEG3", + "CMT_PMV_LH7", + "CMT_PMV_NE4C2", + "CMT_PMV_SW4END2", + "CMT_PMV_IMUX31", + "CMT_PMV_IMUX24", + "CMT_PMV_FAN5", + "CMT_PMV_LOGIC_OUTS22", + "CMT_PMV_IMUX23", + "CMT_PMV_FAN2", + "CMT_PMV_LOGIC_OUTS3", + "CMT_PMV_LOGIC_OUTS15", + "CMT_PMV_EL1BEG2", + "CMT_PMV_LOGIC_OUTS20", + "CMT_PMV_WW2A3", + "CMT_PMV_WL1END1", + "CMT_PMV_EL1BEG3", + "CMT_PMV_IMUX5", + "CMT_PMV_IMUX9", + "CMT_PMV_LH6", + "CMT_PMV_WL1END3", + "CMT_PMV_LH11", + "CMT_PMV_NE2A0", + "CMT_PMV_IMUX18", + "CMT_PMV_IMUX17", + "CMT_PMV_WR1END1", + "CMT_PMV_NE4BEG0", + "CMT_PMV_IMUX30", + "CMT_PMV_IMUX44", + "CMT_PMV_IMUX41", + "L_TERM_INT_PHASER_TO_IO_ICLK", + "CMT_PMV_EE4C0", + "CMT_PMV_SE2A3", + "CMT_PMV_SE4BEG3" + ], + "tile_type": "CMT_PMV", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_PMV_L.json b/artix7/tile_type_CMT_PMV_L.json index 00d8cc2..8c10e6d 100644 --- a/artix7/tile_type_CMT_PMV_L.json +++ b/artix7/tile_type_CMT_PMV_L.json @@ -1,230 +1,230 @@ { - "wires": [ - "CMT_PMV_NW2A3", - "CMT_PMV_LOGIC_OUTS23", - "CMT_PMV_SW4END3", - "CMT_PMV_ER1BEG2", - "CMT_PMV_FAN4", - "CMT_PMV_LH6", - "CMT_PMV_IMUX17", - "CMT_PMV_NW4A1", - "CMT_PMV_WW4C3", - "CMT_PMV_NE2A3", - "CMT_PMV_WW2A3", - "CMT_PMV_EE2A2", - "CMT_PMV_IMUX32", - "CMT_PMV_IMUX46", - "CMT_PMV_SE4C0", - "CMT_PMV_IMUX38", - "CMT_PMV_WR1END1", - "CMT_PMV_SW4A3", - "CMT_PMV_SW2A0", - "CMT_PMV_SW4A2", - "CMT_PMV_BYP7", - "CMT_PMV_BYP6", - "CMT_PMV_IMUX22", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV", - "CMT_PMV_IMUX0", - "CMT_PMV_WW4END0", - "CMT_PMV_IMUX4", - "CMT_PMV_LOGIC_OUTS13", - "CMT_PMV_IMUX30", - "CMT_PMV_IMUX10", - "CMT_PMV_IMUX45", - "CMT_PMV_WR1END3", - "CMT_PMV_EE4B0", - "CMT_PMV_LOGIC_OUTS22", - "CMT_PMV_LOGIC_OUTS14", - "CMT_PMV_IMUX3", - "CMT_PMV_IMUX26", - "CMT_PMV_LH3", - "CMT_PMV_IMUX23", - "CMT_PMV_EL1BEG0", - "CMT_PMV_LOGIC_OUTS21", - "CMT_PMV_FAN2", - "CMT_PMV_IMUX28", - "CMT_PMV_WW2A0", - "CMT_PMV_NW4A0", - "CMT_PMV_WW4END1", - "CMT_PMV_BYP3", - "CMT_PMV_IMUX29", - "CMT_PMV_WL1END1", - "CMT_PMV_SW4END1", - "CMT_PMV_LOGIC_OUTS16", - "CMT_PMV_IMUX35", - "CMT_PMV_LOGIC_OUTS15", - "CMT_PMV_EE2A0", - "CMT_PMV_EE4A3", - "CMT_PMV_NW2A2", - "CMT_PMV_IMUX24", - "CMT_PMV_IMUX44", - "CMT_PMV_LOGIC_OUTS5", - "CMT_PMV_BYP5", - "CMT_PMV_LOGIC_OUTS3", - "CMT_PMV_WW4END2", - "CMT_PMV_WL1END3", - "CMT_PMV_EE2BEG3", - "CMT_PMV_IMUX7", - "CMT_PMV_WW2A2", - "CMT_PMV_IMUX9", - "CMT_PMV_SE4BEG0", - "CMT_PMV_EE4BEG1", - "CMT_PMV_IMUX27", - "CMT_PMV_EE4C3", - "CMT_PMV_IMUX36", - "CMT_PMV_IMUX21", - "CMT_PMV_WL1END2", - "CMT_PMV_LOGIC_OUTS18", - "CMT_PMV_WW4A0", - "CMT_PMV_FAN7", - "CMT_PMV_WW4C2", - "CMT_PMV_LH5", - "CMT_PMV_SW4END0", - "CMT_PMV_EE2BEG0", - "CMT_PMV_LOGIC_OUTS2", - "CMT_PMV_IMUX37", - "CMT_PMV_EE2BEG2", - "CMT_PMV_NW4END1", - "CMT_PMV_EE4BEG3", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", - "CMT_PMV_BYP4", - "CMT_PMV_BYP2", - "CMT_PMV_MONITOR_N", - "CMT_PMV_NE4C2", - "CMT_PMV_LOGIC_OUTS12", - "CMT_PMV_WW4A3", - "CMT_PMV_IMUX15", - "CMT_PMV_SE4C1", - "CMT_PMV_EL1BEG2", - "CMT_PMV_IMUX33", - "CMT_PMV_LOGIC_OUTS0", - "CMT_PMV_FAN1", - "CMT_PMV_NE4C0", - "CMT_PMV_IMUX14", - "CMT_PMV_IMUX20", - "CMT_PMV_NW4END2", - "CMT_PMV_SW4A1", - "CMT_PMV_IMUX8", - "CMT_PMV_LH2", - "CMT_PMV_IMUX6", - "CMT_PMV_IMUX2", - "CMT_PMV_LOGIC_OUTS1", - "CMT_PMV_ER1BEG0", - "CMT_PMV_SE2A3", - "CMT_PMV_LH7", - "CMT_PMV_LH10", - "CMT_PMV_LOGIC_OUTS20", - "CMT_PMV_EE4B3", - "CMT_PMV_EL1BEG3", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "CMT_PMV_EE4C1", - "CMT_PMV_WR1END2", - "CMT_PMV_IMUX16", - "CMT_PMV_WW4A1", - "CMT_PMV_WW4END3", - "CMT_PMV_ER1BEG3", - "CMT_PMV_SE4BEG2", - "CMT_PMV_CLK0", - "CMT_PMV_NE4BEG0", - "CMT_PMV_LOGIC_OUTS7", - "CMT_PMV_EE4C0", - "CMT_PMV_FAN0", - "CMT_PMV_NE2A1", - "CMT_PMV_WR1END0", - "CMT_PMV_NW2A1", - "CMT_PMV_IMUX34", - "CMT_PMV_CTRL1", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "CMT_PMV_SW4A0", - "CMT_PMV_EE4BEG0", - "CMT_PMV_LH9", - "CMT_PMV_IMUX1", - "CMT_PMV_IMUX40", - "CMT_PMV_WW4C0", - "CMT_PMV_SE4C3", - "CMT_PMV_NE2A2", - "CMT_PMV_EE4A2", - "CMT_PMV_NE4BEG3", - "CMT_PMV_WW2END0", - "CMT_PMV_CTRL0", - "CMT_PMV_LH11", - "CMT_PMV_LH8", - "CMT_PMV_WW4B1", - "CMT_PMV_IMUX31", - "CMT_PMV_WW2END1", - "CMT_PMV_IMUX5", - "CMT_PMV_SW2A3", - "CMT_PMV_IMUX13", - "CMT_PMV_NW4A2", - "CMT_PMV_NW4END0", - "CMT_PMV_IMUX11", - "CMT_PMV_CLK1", - "CMT_PMV_MONITOR_P", - "CMT_PMV_LOGIC_OUTS9", - "CMT_PMV_IMUX19", - "CMT_PMV_EE4BEG2", - "CMT_PMV_LOGIC_OUTS10", - "CMT_PMV_SE2A1", - "CMT_PMV_FAN6", - "CMT_PMV_FAN5", - "CMT_PMV_EE4B2", - "CMT_PMV_EE2A1", - "CMT_PMV_LH12", - "CMT_PMV_IMUX18", - "CMT_PMV_LH4", - "CMT_PMV_NW4END3", - "CMT_PMV_EE2BEG1", - "CMT_PMV_WW2END3", - "CMT_PMV_WW4A2", - "CMT_PMV_BYP1", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "CMT_PMV_EE4C2", - "CMT_PMV_NE4C3", - "CMT_PMV_NW2A0", - "CMT_PMV_NE4BEG1", - "CMT_PMV_SW4END2", - "CMT_PMV_NE4C1", - "CMT_PMV_LH1", - "CMT_PMV_EE4A0", - "CMT_PMV_WL1END0", - "CMT_PMV_ER1BEG1", - "CMT_PMV_WW2A1", - "CMT_PMV_IMUX42", - "CMT_PMV_EL1BEG1", - "CMT_PMV_NE4BEG2", - "CMT_PMV_EE4A1", - "CMT_PMV_SE2A2", - "CMT_PMV_SE4BEG3", - "CMT_PMV_WW4C1", - "CMT_PMV_IMUX43", - "CMT_PMV_LOGIC_OUTS6", - "CMT_PMV_BYP0", - "CMT_PMV_IMUX41", - "CMT_PMV_EE4B1", - "CMT_PMV_WW4B0", - "CMT_PMV_SE2A0", - "CMT_PMV_IMUX39", - "CMT_PMV_LOGIC_OUTS4", - "CMT_PMV_LOGIC_OUTS19", - "CMT_PMV_IMUX25", - "CMT_PMV_NW4A3", - "CMT_PMV_WW2END2", - "CMT_PMV_NE2A0", - "CMT_PMV_SW2A2", - "CMT_PMV_WW4B3", - "CMT_PMV_IMUX12", - "CMT_PMV_LOGIC_OUTS8", - "CMT_PMV_LOGIC_OUTS11", - "CMT_PMV_WW4B2", - "CMT_PMV_EE2A3", - "CMT_PMV_SW2A1", - "CMT_PMV_FAN3", - "CMT_PMV_SE4C2", - "CMT_PMV_IMUX47", - "CMT_PMV_SE4BEG1", - "CMT_PMV_LOGIC_OUTS17" - ], - "sites": [], "pips": {}, - "tile_type": "CMT_PMV_L" + "wires": [ + "CMT_PMV_IMUX16", + "CMT_PMV_LOGIC_OUTS17", + "CMT_PMV_LOGIC_OUTS10", + "CMT_PMV_IMUX29", + "CMT_PMV_BYP1", + "CMT_PMV_BYP0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "CMT_PMV_LOGIC_OUTS7", + "CMT_PMV_IMUX45", + "CMT_PMV_LOGIC_OUTS13", + "CMT_PMV_SW2A0", + "CMT_PMV_LOGIC_OUTS11", + "CMT_PMV_WW4C3", + "CMT_PMV_NW2A3", + "CMT_PMV_NE4BEG2", + "CMT_PMV_SW4A3", + "CMT_PMV_EE4C1", + "CMT_PMV_EE4B2", + "CMT_PMV_IMUX39", + "CMT_PMV_SW2A1", + "CMT_PMV_LOGIC_OUTS21", + "CMT_PMV_WW2END3", + "CMT_PMV_IMUX22", + "CMT_PMV_LH5", + "CMT_PMV_IMUX40", + "CMT_PMV_SW4A2", + "CMT_PMV_WW4A3", + "CMT_PMV_NW2A0", + "CMT_PMV_SE4C2", + "CMT_PMV_NW4END0", + "CMT_PMV_LH9", + "CMT_PMV_LOGIC_OUTS1", + "CMT_PMV_EE4A2", + "CMT_PMV_SE2A2", + "CMT_PMV_ER1BEG1", + "CMT_PMV_NW4A2", + "CMT_PMV_SE4C0", + "CMT_PMV_ER1BEG2", + "CMT_PMV_NW4A3", + "CMT_PMV_NW4END3", + "CMT_PMV_WW4B1", + "CMT_PMV_EE2BEG1", + "CMT_PMV_EE4BEG1", + "CMT_PMV_WL1END0", + "CMT_PMV_SE4BEG0", + "CMT_PMV_SW4A1", + "CMT_PMV_IMUX7", + "CMT_PMV_SW4END0", + "CMT_PMV_EE4C3", + "CMT_PMV_IMUX43", + "CMT_PMV_NW2A1", + "CMT_PMV_IMUX8", + "CMT_PMV_IMUX19", + "CMT_PMV_LH1", + "CMT_PMV_IMUX1", + "CMT_PMV_WR1END3", + "CMT_PMV_IMUX12", + "CMT_PMV_SE4BEG2", + "CMT_PMV_LH12", + "CMT_PMV_IMUX10", + "CMT_PMV_LOGIC_OUTS12", + "CMT_PMV_WW4B0", + "CMT_PMV_SE2A1", + "CMT_PMV_IMUX21", + "CMT_PMV_IMUX25", + "CMT_PMV_EE4BEG2", + "CMT_PMV_LOGIC_OUTS16", + "CMT_PMV_LOGIC_OUTS19", + "CMT_PMV_FAN4", + "CMT_PMV_SW2A3", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", + "CMT_PMV_LH10", + "CMT_PMV_CTRL0", + "CMT_PMV_IMUX20", + "CMT_PMV_WW4B3", + "CMT_PMV_IMUX4", + "CMT_PMV_NE2A2", + "CMT_PMV_LOGIC_OUTS5", + "CMT_PMV_MONITOR_P", + "CMT_PMV_CLK0", + "CMT_PMV_LOGIC_OUTS14", + "CMT_PMV_EE4B0", + "CMT_PMV_WW4A2", + "CMT_PMV_WW4END3", + "CMT_PMV_LOGIC_OUTS23", + "CMT_PMV_IMUX32", + "CMT_PMV_IMUX42", + "CMT_PMV_LH4", + "CMT_PMV_LOGIC_OUTS2", + "CMT_PMV_LH8", + "CMT_PMV_SE4BEG1", + "CMT_PMV_IMUX27", + "CMT_PMV_LH2", + "CMT_PMV_BYP3", + "CMT_PMV_WW4B2", + "CMT_PMV_FAN3", + "CMT_PMV_FAN6", + "CMT_PMV_EE4B3", + "CMT_PMV_WW4C2", + "CMT_PMV_ER1BEG0", + "CMT_PMV_SE4C1", + "CMT_PMV_FAN7", + "CMT_PMV_MONITOR_N", + "CMT_PMV_WW2A0", + "CMT_PMV_EE4A1", + "CMT_PMV_BYP5", + "CMT_PMV_IMUX28", + "CMT_PMV_IMUX15", + "CMT_PMV_WW2A1", + "CMT_PMV_WW4A0", + "CMT_PMV_CTRL1", + "CMT_PMV_IMUX3", + "CMT_PMV_CLK1", + "CMT_PMV_EE2A2", + "CMT_PMV_WW2END2", + "CMT_PMV_NE4C1", + "CMT_PMV_NE2A3", + "CMT_PMV_NE2A1", + "CMT_PMV_IMUX37", + "CMT_PMV_EE2BEG3", + "CMT_PMV_LOGIC_OUTS6", + "CMT_PMV_LOGIC_OUTS9", + "CMT_PMV_LOGIC_OUTS4", + "CMT_PMV_NE4BEG3", + "CMT_PMV_WR1END0", + "CMT_PMV_BYP6", + "CMT_PMV_FAN0", + "CMT_PMV_IMUX6", + "CMT_PMV_WW4C1", + "CMT_PMV_NW2A2", + "CMT_PMV_SW2A2", + "CMT_PMV_IMUX36", + "CMT_PMV_SW4A0", + "CMT_PMV_IMUX35", + "CMT_PMV_FAN1", + "CMT_PMV_IMUX11", + "CMT_PMV_EE4BEG0", + "CMT_PMV_EE2A3", + "CMT_PMV_WW4C0", + "CMT_PMV_NE4BEG1", + "CMT_PMV_NW4END1", + "CMT_PMV_IMUX38", + "CMT_PMV_EE4A0", + "CMT_PMV_NW4A0", + "CMT_PMV_BYP4", + "CMT_PMV_NW4END2", + "CMT_PMV_EE2A1", + "CMT_PMV_WW4END0", + "CMT_PMV_WW4END2", + "CMT_PMV_WL1END2", + "CMT_PMV_SE4C3", + "CMT_PMV_IMUX13", + "CMT_PMV_WW2A2", + "CMT_PMV_LOGIC_OUTS8", + "CMT_PMV_EE4C2", + "CMT_PMV_EL1BEG1", + "CMT_PMV_LOGIC_OUTS0", + "CMT_PMV_SW4END3", + "CMT_PMV_IMUX2", + "CMT_PMV_IMUX14", + "CMT_PMV_EL1BEG0", + "CMT_PMV_IMUX0", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "CMT_PMV_EE2BEG2", + "CMT_PMV_IMUX47", + "CMT_PMV_EE4BEG3", + "CMT_PMV_IMUX34", + "CMT_PMV_IMUX46", + "CMT_PMV_WW4A1", + "CMT_PMV_LOGIC_OUTS18", + "CMT_PMV_WW2END1", + "CMT_PMV_SE2A0", + "CMT_PMV_WW4END1", + "CMT_PMV_IMUX26", + "CMT_PMV_NE4C3", + "CMT_PMV_IMUX33", + "CMT_PMV_EE4A3", + "L_TERM_INT_PHASER_TO_IO_OCLK", + "CMT_PMV_LH3", + "CMT_PMV_WR1END2", + "CMT_PMV_EE2BEG0", + "CMT_PMV_BYP2", + "CMT_PMV_NE4C0", + "CMT_PMV_BYP7", + "CMT_PMV_EE2A0", + "CMT_PMV_WW2END0", + "CMT_PMV_SW4END1", + "CMT_PMV_NW4A1", + "CMT_PMV_EE4B1", + "CMT_PMV_ER1BEG3", + "CMT_PMV_LH7", + "CMT_PMV_NE4C2", + "CMT_PMV_SW4END2", + "CMT_PMV_IMUX31", + "CMT_PMV_IMUX24", + "CMT_PMV_FAN5", + "CMT_PMV_LOGIC_OUTS22", + "CMT_PMV_IMUX23", + "CMT_PMV_FAN2", + "CMT_PMV_LOGIC_OUTS3", + "CMT_PMV_LOGIC_OUTS15", + "CMT_PMV_EL1BEG2", + "CMT_PMV_LOGIC_OUTS20", + "CMT_PMV_WW2A3", + "CMT_PMV_WL1END1", + "CMT_PMV_EL1BEG3", + "CMT_PMV_IMUX5", + "CMT_PMV_IMUX9", + "CMT_PMV_LH6", + "CMT_PMV_WL1END3", + "CMT_PMV_LH11", + "CMT_PMV_NE2A0", + "CMT_PMV_IMUX18", + "CMT_PMV_IMUX17", + "CMT_PMV_WR1END1", + "CMT_PMV_NE4BEG0", + "CMT_PMV_IMUX30", + "CMT_PMV_IMUX44", + "CMT_PMV_IMUX41", + "L_TERM_INT_PHASER_TO_IO_ICLK", + "CMT_PMV_EE4C0", + "CMT_PMV_SE2A3", + "CMT_PMV_SE4BEG3" + ], + "tile_type": "CMT_PMV_L", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_TOP_L_LOWER_B.json b/artix7/tile_type_CMT_TOP_L_LOWER_B.json index 0a1a3d7..72adfdd 100644 --- a/artix7/tile_type_CMT_TOP_L_LOWER_B.json +++ b/artix7/tile_type_CMT_TOP_L_LOWER_B.json @@ -1,5450 +1,5450 @@ { - "wires": [ - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_EE2A0_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG1_13", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_NE2A1_7", - "CMT_TOP_WW4A2_13", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_IMUX44_11", - "CMT_TOP_BYP5_2", - "CMT_TOP_EE2A3_5", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX19_0", - "CMT_TOP_LH11_4", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2END3_7", - "CMT_TOP_BYP6_0", - "CMT_TOP_CTRL1_12", - "CMT_TOP_NW2A2_9", - "CMT_TOP_IMUX44_1", - "CMT_TOP_NE2A1_8", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_IMUX39_5", - "CMT_MMCM_PHASERA_CTSBUS1", - "CMT_TOP_WW2A2_6", - "CMT_TOP_ICLKDIV_13", - "CMT_TOP_CLK1_14", - "CMT_TOP_IMUX44_10", - "CMT_TOP_NW2A0_1", - "CMT_TOP_EE2BEG2_13", - "CMT_TOP_EE4A1_10", - "CMT_TOP_NW4A0_2", - "CMT_TOP_WW2END0_8", - "CMT_TOP_SW4A0_1", - "CMT_TOP_WR1END3_14", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_WW4A2_2", - "CMT_TOP_IMUX23_0", - "CMT_TOP_NE4C3_15", - "CMT_TOP_ER1BEG3_14", - "CMT_TOP_WW4C0_8", - "CMT_TOP_BYP6_1", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_IMUX15_1", - "CMT_TOP_SE2A0_0", - "CMT_TOP_EE4BEG0_11", - "CMT_LR_LOWER_B_MMCM_DO10", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_SW2A2_1", - "CMT_TOP_FAN0_1", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_WW4END0_6", - "CMT_TOP_SW2A1_4", - "CMT_TOP_WW4A1_12", - "CMT_TOP_EE4B1_14", - "CMT_TOP_EE2A2_10", - "CMT_TOP_NW4END2_7", - "CMT_TOP_LH12_15", - "CMT_TOP_LH6_12", - "CMT_TOP_SE2A0_12", - "CMT_TOP_LOGIC_OUTS_L_B11_14", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_EE4B1_10", - "CMT_TOP_BYP5_3", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_WW4B0_10", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_WW4C2_3", - "CMT_TOP_IMUX21_13", - "CMT_TOP_BYP6_4", - "CMT_TOP_SW4A2_12", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX14_3", - "CMT_TOP_BYP7_6", - "CMT_LR_LOWER_B_MMCM_TESTOUT49", - "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "CMT_TOP_NW2A2_8", - "CMT_TOP_EL1BEG2_15", - "CMT_TOP_IMUX46_14", - "CMT_TOP_SE2A1_0", - "CMT_TOP_LOGIC_OUTS_L_B14_13", - "CMT_TOP_CTRL1_4", - "CMT_TOP_ICLK_11", - "CMT_TOP_IMUX25_14", - "CMT_TOP_IMUX0_0", - "CMT_TOP_FAN7_11", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_IMUX15_11", - "CMT_TOP_MONITOR_P_14", - "CMT_TOP_NW4END1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_EE4C0_1", - "CMT_TOP_IMUX40_13", - "CMT_TOP_WR1END0_13", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_LH1_13", - "CMT_TOP_LH8_15", - "CMT_TOP_IMUX10_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_LH6_13", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_EE4B3_15", - "CMT_TOP_IMUX29_14", - "CMT_TOP_NE4C0_0", - "CMT_TOP_EE2A1_11", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_LH1_15", - "CMT_TOP_LH11_12", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_SW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B13_15", - "CMT_TOP_WW4END0_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "CMT_TOP_IMUX28_9", - "CMT_TOP_NE4C3_6", - "CMT_TOP_LH9_1", - "CMT_TOP_EE4A3_1", - "CMT_TOP_WW2A0_6", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B17_14", - "CMT_TOP_LOGIC_OUTS_L_B0_15", - "CMT_TOP_LOGIC_OUTS_L_B12_15", - "CMT_TOP_IMUX10_4", - "CMT_TOP_BYP0_1", - "CMT_TOP_NE2A0_4", - "CMT_TOP_IMUX31_4", - "CMT_L_LOWER_B_CLK_MMCM13", - "CMT_TOP_IMUX19_10", - "CMT_TOP_IMUX45_6", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_LH10_7", - "CMT_TOP_NW2A0_15", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_BYP2_15", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_WW4B3_11", - "CMT_TOP_NW4A3_1", - "CMT_TOP_EE4A2_6", - "CMT_TOP_FAN3_13", - "CMT_TOP_WL1END0_10", - "CMT_TOP_SW2A3_4", - "CMT_TOP_IMUX41_11", - "CMT_TOP_EE4A0_14", - "CMT_TOP_OCLK_2", - "CMT_TOP_SE4C3_11", - "CMT_TOP_EE4B2_3", - "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", - "CMT_TOP_BYP1_14", - "CMT_TOP_SE2A0_2", - "CMT_TOP_IMUX14_12", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LH11_7", - "CMT_TOP_IMUX31_1", - "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX12_6", - "CMT_TOP_SW4END3_6", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_L_LOWER_B_CLK_IN3_HCLK", - "CMT_TOP_WW2END1_1", - "CMT_TOP_LOGIC_OUTS_L_B10_14", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_IMUX29_11", - "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "CMT_TOP_WL1END2_5", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_WR1END1_8", - "CMT_TOP_IMUX12_5", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_SE4BEG2_15", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_IMUX42_5", - "CMT_TOP_EE4C1_13", - "CMT_TOP_IMUX39_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_IMUX24_7", - "CMT_LR_LOWER_B_MMCM_PSDONE", - "CMT_MMCM_A_RDCLK_TOFIFO", - "CMT_TOP_IMUX10_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_IMUX5_8", - "CMT_TOP_EE4B3_8", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2END1_14", - "CMT_TOP_WW2END2_13", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX2_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_SW2A2_11", - "CMT_TOP_IMUX47_5", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_WW4B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_EL1BEG1_15", - "CMT_TOP_WR1END2_11", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX6_6", - "CMT_TOP_SW4END1_0", - "CMT_MMCM_PHASER_OUT_A_OCLKDIV", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX30_10", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_MONITOR_N_13", - "CMT_TOP_WL1END3_6", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_SE2A2_0", - "CMT_TOP_IMUX27_0", - "CMT_TOP_SE2A2_8", - "CMT_TOP_IMUX26_10", - "CMT_TOP_WW2END2_7", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_WR1END3_7", - "CMT_MMCM_A_WREN_TOFIFO", - "CMT_TOP_EE2A0_14", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_IMUX39_9", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_EE4C3_13", - "CMT_TOP_EE4B3_12", - "CMT_TOP_LH11_8", - "CMT_TOP_WW4END2_4", - "CMT_TOP_EE2A1_15", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_WW4END3_15", - "CMT_TOP_EE2A3_12", - "CMT_TOP_WW4A0_8", - "CMT_TOP_LH1_6", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX34_2", - "CMT_TOP_SE4C1_13", - "CMT_TOP_EE2A0_10", - "CMT_TOP_IMUX17_6", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "CMT_TOP_IMUX37_11", - "CMT_TOP_EE4B2_9", - "CMT_TOP_SE4C1_10", - "CMT_TOP_LH5_5", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_EE2A2_5", - "CMT_MMCM_PHASER_OUT_A_OCLK", - "CMT_TOP_LH4_8", - "CMT_TOP_IMUX17_15", - "CMT_TOP_IMUX45_1", - "CMT_TOP_SW4A0_4", - "CMT_TOP_FAN2_4", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX19_5", - "CMT_TOP_EE4B1_0", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4A1_13", - "CMT_TOP_BYP7_7", - "CMT_TOP_IMUX7_12", - "MMCM_CLK_FREQ_BB_NS0", - "CMT_TOP_BYP3_9", - "CMT_TOP_EE4B0_9", - "CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "CMT_TOP_WR1END1_12", - "CMT_MMCM_PHASERREF_ABOVE0", - "CMT_TOP_IMUX25_10", - "CMT_TOP_WR1END0_3", - "CMT_TOP_SW4A2_8", - "CMT_TOP_BYP4_15", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_SW4A0_3", - "CMT_TOP_CLK0_6", - "CMT_TOP_IMUX3_12", - "CMT_TOP_SE2A3_4", - "CMT_TOP_FAN7_9", - "CMT_TOP_IMUX39_10", - "CMT_TOP_LH7_6", - "CMT_TOP_EE4B2_15", - "CMT_TOP_EE2A2_11", - "CMT_TOP_BYP7_13", - "CMT_TOP_IMUX41_1", - "CMT_TOP_NE4C2_7", - "CMT_TOP_SW4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LH7_8", - "CMT_TOP_WR1END2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_12", - "CMT_TOP_FAN6_3", - "CMT_TOP_WW2A0_7", - "CMT_TOP_BYP4_2", - "CMT_TOP_IMUX33_11", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_EE4B3_1", - "CMT_LR_LOWER_B_MMCM_DI6", - "CMT_TOP_WW4END0_2", - "CMT_TOP_SW2A0_15", - "CMT_LR_LOWER_B_MMCM_TESTIN28", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_WW4A0_7", - "CMT_TOP_LH9_3", - "CMT_TOP_NE2A0_5", - "CMT_TOP_EE4C3_2", - "CMT_TOP_BYP1_15", - "CMT_TOP_NE4BEG0_15", - "CMT_TOP_LH5_10", - "CMT_LR_LOWER_B_MMCM_DI2", - "CMT_TOP_IMUX1_14", - "CMT_TOP_NE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_EE4C1_3", - "CMT_TOP_SW4A1_8", - "CMT_TOP_CTRL0_8", - "CMT_TOP_IMUX40_14", - "CMT_TOP_NW2A0_4", - "CMT_TOP_IMUX9_11", - "CMT_TOP_LOGIC_OUTS_L_B23_13", - "CMT_TOP_IMUX1_12", - "CMT_TOP_IMUX33_3", - "CMT_TOP_CTRL1_14", - "CMT_TOP_IMUX13_6", - "CMT_TOP_LH12_14", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX21_9", - "CMT_TOP_WL1END1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LH4_3", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_LR_LOWER_B_MMCM_TESTIN22", - "CMT_TOP_CTRL1_0", - "CMT_TOP_LH11_10", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_SE2A3_11", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_BYP3_13", - "CMT_TOP_SW2A3_0", - "CMT_TOP_BYP7_5", - "CMT_TOP_ICLK_7", - "CMT_L_LOWER_B_CLK_MMCM0", - "CMT_TOP_WW4C3_7", - "CMT_TOP_IMUX8_14", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_FAN1_0", - "CMT_TOP_SW4END1_4", - "CMT_TOP_EE4C3_3", - "CMT_LR_LOWER_B_MMCM_TMUXOUT", - "CMT_TOP_BYP0_12", - "CMT_TOP_WW4B1_12", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX9_5", - "CMT_TOP_WW4B1_11", - "CMT_LR_LOWER_B_MMCM_TESTOUT53", - "CMT_TOP_IMUX13_9", - "CMT_TOP_LOGIC_OUTS_L_B20_14", - "CMT_TOP_FAN6_8", - "CMT_TOP_SE2A2_10", - "CMT_TOP_EE4A0_15", - "CMT_TOP_WW4A0_0", - "CMT_TOP_BLOCK_OUTS_L_B1_14", - "CMT_TOP_CTRL0_5", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_WW2A1_11", - "CMT_TOP_IMUX14_10", - "CMT_TOP_IMUX14_2", - "CMT_TOP_EE4B0_8", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX22_14", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_IMUX7_4", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_IMUX38_12", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_WW2A0_12", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_BYP7_2", - "CMT_TOP_WW4B3_14", - "CMT_TOP_IMUX27_14", - "CMT_TOP_IMUX4_14", - "CMT_TOP_SE4C1_0", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX15_4", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_IMUX23_3", - "CMT_TOP_WW2A2_3", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_EE4A1_7", - "CMT_TOP_IMUX31_3", - "CMT_TOP_EE4B3_11", - "CMT_TOP_IMUX25_8", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_EE2A3_11", - "CMT_TOP_SE2A0_15", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_IMUX35_2", - "CMT_LR_LOWER_B_MMCM_DO2", - "CMT_LR_LOWER_B_MMCM_DRDY", - "CMT_TOP_IMUX12_9", - "CMT_TOP_EE2A1_10", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NW2A3_0", - "CMT_TOP_SW4A3_10", - "CMT_TOP_WL1END0_3", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_WW2A3_5", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_WW2END1_3", - "CMT_TOP_SW2A2_5", - "CMT_TOP_ER1BEG3_1", - "CMT_MMCM_A_RDEN_TOFIFO", - "CMT_TOP_CTRL0_10", - "CMT_TOP_IMUX28_11", - "CMT_TOP_IMUX42_11", - "CMT_TOP_WW2END2_10", - "CMT_TOP_EE4B3_6", - "CMT_TOP_IMUX37_7", - "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "CMT_LR_LOWER_B_MMCM_DI15", - "CMT_TOP_WW4A3_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "CMT_TOP_LOGIC_OUTS_L_B9_15", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_1", - "CMT_TOP_IMUX47_9", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_IMUX17_1", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "CMT_TOP_BYP4_0", - "CMT_TOP_FAN2_9", - "CMT_TOP_SE4C3_8", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW2A3_15", - "CMT_TOP_NE2A2_1", - "CMT_TOP_IMUX37_5", - "CMT_TOP_EE2BEG0_13", - "CMT_TOP_IMUX7_7", - "CMT_TOP_LH8_12", - "CMT_TOP_IMUX20_6", - "CMT_TOP_WW4C1_9", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_SE4C3_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT56", - "CMT_TOP_NE4C3_11", - "CMT_TOP_IMUX33_5", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_EE4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BYP5_4", - "CMT_TOP_NW4END1_15", - "CMT_TOP_IMUX17_13", - "CMT_TOP_LH10_9", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_IMUX26_15", - "CMT_TOP_WW4C3_15", - "CMT_TOP_NW4A1_10", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_IMUX25_9", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EE4B0_10", - "CMT_TOP_WW4END3_2", - "CMT_TOP_IMUX30_8", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_IMUX47_0", - "CMT_TOP_BLOCK_OUTS_L_B3_13", - "CMT_LR_LOWER_B_MMCM_TESTIN23", - "CMT_TOP_IMUX16_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END1_6", - "CMT_TOP_IMUX11_11", - "CMT_TOP_WW2A0_11", - "CMT_TOP_SW4END2_7", - "CMT_TOP_IMUX34_4", - "CMT_TOP_LH12_0", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_SW4A3_11", - "CMT_TOP_NW4END2_8", - "CMT_TOP_IMUX44_13", - "CMT_TOP_IMUX36_0", - "CMT_TOP_FAN7_8", - "CMT_TOP_LH3_3", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_SE4C0_10", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX10_5", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_OCLK_15", - "CMT_TOP_NW4END2_12", - "CMT_TOP_LH7_14", - "CMT_TOP_WW2A3_0", - "CMT_TOP_LH3_4", - "CMT_TOP_IMUX45_15", - "CMT_TOP_IMUX16_6", - "CMT_TOP_FAN2_11", - "CMT_TOP_IMUX3_14", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX47_14", - "CMT_TOP_IMUX40_4", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_IMUX38_0", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_IMUX25_13", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_WW4A1_10", - "CMT_TOP_NW4A3_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_SE4BEG2_3", - "CMT_L_LOWER_B_CLK_FREQ_BB1", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_9", - "CMT_TOP_LH8_5", - "CMT_TOP_EE4B2_10", - "CMT_TOP_WW2A2_5", - "CMT_TOP_NW2A1_15", - "CMT_LR_LOWER_B_MMCM_DI9", - "CMT_TOP_IMUX29_0", - "CMT_TOP_EE4A0_8", - "CMT_TOP_WW2END3_15", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_NW4END0_2", - "CMT_TOP_IMUX16_7", - "CMT_TOP_FAN1_1", - "CMT_TOP_LH1_4", - "CMT_TOP_NW4A2_13", - "CMT_TOP_WW4C0_14", - "CMT_TOP_SW2A2_9", - "CMT_TOP_FAN2_12", - "CMT_MMCM_PHASERREF1", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_IMUX45_9", - "CMT_TOP_IMUX2_13", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_ER1BEG0_13", - "CMT_TOP_SE4C0_7", - "CMT_TOP_WR1END0_12", - "CMT_TOP_IMUX46_3", - "CMT_TOP_SW4END2_2", - "CMT_TOP_WW4B3_5", - "CMT_TOP_IMUX6_7", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_NW4A0_7", - "CMT_TOP_EE4A1_6", - "CMT_TOP_FAN2_0", - "CMT_TOP_WW4A0_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX37_2", - "CMT_TOP_IMUX28_14", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_WW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_IMUX45_8", - "CMT_TOP_FAN0_4", - "CMT_TOP_NW4END0_14", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SE4C0_3", - "CMT_TOP_IMUX22_12", - "CMT_TOP_IMUX29_6", - "CMT_MMCM_PHASERREF_BELOW1", - "CMT_TOP_EE2BEG2_6", - "CMT_L_LOWER_B_CLK_IN2_INT", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_WL1END1_6", - "CMT_TOP_CTRL1_15", - "CMT_TOP_WW2END1_2", - "CMT_TOP_SE4BEG3_12", - "CMT_LR_LOWER_B_MMCM_RST", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_EE2BEG3_15", - "CMT_TOP_SW4A1_6", - "CMT_TOP_FAN5_12", - "CMT_TOP_IMUX36_12", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_EL1BEG0_14", - "CMT_TOP_FAN3_9", - "CMT_TOP_EE4A1_3", - "CMT_TOP_OCLK_11", - "CMT_L_LOWER_B_CLK_MMCM2", - "CMT_TOP_WW2END2_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_SE4BEG0_12", - "MMCM_CLK_FREQ_BB_NS1", - "CMT_TOP_CLK1_15", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_WW4END3_9", - "CMT_LR_LOWER_B_MMCM_TESTIN8", - "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "CMT_TOP_IMUX26_1", - "CMT_TOP_CLK1_2", - "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_ER1BEG2_13", - "CMT_LR_LOWER_B_MMCM_DO15", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_IMUX31_10", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_IMUX23_12", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_WL1END0_8", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_IMUX29_7", - "CMT_TOP_IMUX31_15", - "CMT_TOP_NE2A3_6", - "CMT_TOP_WW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_SE4C1_15", - "CMT_TOP_NW4END1_14", - "CMT_TOP_NE2A1_6", - "CMT_TOP_IMUX27_2", - "CMT_TOP_SW4A3_1", - "CMT_TOP_NW2A3_8", - "CMT_TOP_LH7_1", - "CMT_TOP_WW4END1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_IMUX19_15", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_IMUX6_13", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_IMUX13_2", - "CMT_TOP_WW4END2_7", - "CMT_TOP_NW4END1_0", - "CMT_TOP_EE4C0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_NE4C2_9", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_IMUX29_5", - "CMT_TOP_WW2END0_0", - "CMT_TOP_IMUX20_1", - "CMT_LR_LOWER_B_MMCM_TESTIN31", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX40_7", - "CMT_TOP_FAN7_10", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_BYP6_2", - "CMT_TOP_WW4END3_13", - "CMT_TOP_IMUX42_7", - "CMT_TOP_BYP5_5", - "CMT_TOP_WW2A3_10", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX2_1", - "CMT_TOP_FAN5_7", - "CMT_TOP_SE2A2_6", - "CMT_TOP_IMUX12_11", - "CMT_TOP_EE4B1_8", - "CMT_TOP_NE2A3_4", - "CMT_TOP_SW4A3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_15", - "CMT_TOP_IMUX15_12", - "CMT_TOP_WL1END2_11", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_IMUX24_9", - "CMT_TOP_LH1_10", - "CMT_TOP_IMUX23_14", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW2A3_1", - "CMT_TOP_EE2A1_0", - "CMT_TOP_WW4C3_5", - "CMT_TOP_IMUX14_11", - "CMT_TOP_BYP1_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_7", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_NE2A1_2", - "CMT_TOP_BYP6_11", - "CMT_TOP_IMUX7_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_CLK0_12", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_LOGIC_OUTS_L_B4_14", - "CMT_TOP_IMUX30_4", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_EE4C2_13", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_WW2END3_1", - "CMT_TOP_IMUX22_0", - "CMT_TOP_WW2A3_6", - "CMT_TOP_EE4A0_6", - "CMT_TOP_SE4C2_9", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_EE4A0_9", - "CMT_TOP_FAN6_7", - "CMT_TOP_WW4A0_10", - "CMT_TOP_LH5_9", - "CMT_TOP_IMUX11_13", - "CMT_TOP_ICLK_2", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_NW4END3_0", - "CMT_TOP_SW2A1_2", - "CMT_TOP_FAN1_5", - "CMT_TOP_NW2A3_14", - "CMT_TOP_CTRL0_7", - "CMT_TOP_NW4END3_7", - "CMT_TOP_WW2A0_9", - "CMT_TOP_SE4C1_9", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_IMUX44_2", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW2END0_3", - "CMT_TOP_EE4A0_12", - "CMT_TOP_LH10_2", - "CMT_TOP_WW4C1_14", - "CMT_TOP_LH10_14", - "CMT_TOP_NE4C2_2", - "CMT_TOP_IMUX9_6", - "CMT_TOP_NW4END3_3", - "CMT_TOP_SW4A2_14", - "CMT_TOP_IMUX45_2", - "CMT_TOP_SW4A2_11", - "CMT_TOP_FAN6_1", - "CMT_TOP_IMUX22_9", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_EE2A0_13", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX17_12", - "CMT_TOP_SW4A3_8", - "CMT_TOP_LH12_8", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_FAN1_14", - "CMT_LR_LOWER_B_CLKFBOUT2IN", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_NW2A0_12", - "CMT_TOP_IMUX31_11", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_WW4END0_1", - "CMT_TOP_EE4B0_6", - "CMT_MMCM_PHASERREF_ABOVE1", - "CMT_TOP_ER1BEG1_15", - "CMT_TOP_BYP3_0", - "CMT_TOP_EE4B0_7", - "CMT_TOP_LH9_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_ER1BEG1_14", - "CMT_TOP_ER1BEG2_15", - "CMT_TOP_SW4END2_0", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_EE2A1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX35_1", - "CMT_TOP_WW2END1_8", - "CMT_TOP_EE4BEG3_14", - "CMT_TOP_IMUX19_9", - "CMT_TOP_EE4A1_15", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_LR_LOWER_B_MMCM_PSCLK", - "CMT_TOP_WW4A2_9", - "CMT_TOP_EE4B2_2", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_WW4C3_4", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_NW2A3_13", - "CMT_TOP_NE2A0_6", - "CMT_TOP_BYP1_5", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_IMUX11_10", - "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "CMT_TOP_FAN1_3", - "CMT_TOP_SE2A3_7", - "CMT_TOP_LH2_6", - "CMT_TOP_SW2A0_4", - "CMT_TOP_IMUX2_14", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_IMUX25_2", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_WR1END3_4", - "CMT_TOP_CTRL1_11", - "CMT_TOP_IMUX26_9", - "CMT_TOP_IMUX34_14", - "CMT_TOP_IMUX35_10", - "CMT_TOP_FAN0_3", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_IMUX18_12", - "CMT_TOP_EE4BEG1_13", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_WW4B1_14", - "CMT_TOP_WW4B3_10", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE4BEG3_14", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN6_15", - "CMT_TOP_IMUX32_3", - "CMT_TOP_LH7_9", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_CLK0_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WW4B1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG0_13", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_BYP6_5", - "CMT_TOP_LH6_14", - "CMT_TOP_WW2A0_10", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_IMUX39_2", - "CMT_LR_LOWER_B_MMCM_TESTOUT58", - "CMT_TOP_IMUX32_14", - "CMT_TOP_SW4A1_11", - "CMT_TOP_WR1END3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_CTRL0_4", - "CMT_TOP_LH4_5", - "CMT_LR_LOWER_B_MMCM_DI13", - "CMT_TOP_SW4END1_7", - "CMT_TOP_NW4END3_4", - "CMT_TOP_WW4B2_14", - "CMT_TOP_EE4C3_4", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_IMUX46_10", - "CMT_TOP_NW4A0_5", - "CMT_TOP_SW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_IMUX2_11", - "CMT_TOP_WW2A3_13", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_LH11_14", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_IMUX0_3", - "CMT_TOP_OCLK_5", - "CMT_TOP_FAN5_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_EE2A1_12", - "CMT_TOP_IMUX13_14", - "CMT_TOP_WL1END0_2", - "CMT_LR_LOWER_B_MMCM_TESTIN19", - "CMT_TOP_NW2A0_14", - "CMT_TOP_BYP0_5", - "CMT_TOP_NW2A0_10", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_NE4BEG2_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_EE2A2_7", - "CMT_TOP_SE2A2_2", - "CMT_TOP_CTRL1_13", - "CMT_TOP_BYP2_13", - "CMT_TOP_IMUX9_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SE2A3_15", - "CMT_TOP_NE4C1_15", - "CMT_TOP_WW4A3_11", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SW4END0_3", - "CMT_TOP_IMUX46_0", - "CMT_TOP_WW2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LH7_0", - "CMT_TOP_SE2A0_13", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_WW2A2_0", - "CMT_TOP_IMUX34_11", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_CTRL0_2", - "CMT_TOP_IMUX23_9", - "CMT_TOP_WL1END1_3", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_WW4A2_10", - "CMT_TOP_SW4END1_15", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_NE2A1_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT63", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_LOGIC_OUTS_L_B2_13", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_OCLK1X_90_13", - "CMT_TOP_IMUX16_1", - "CMT_TOP_EE2BEG2_15", - "CMT_TOP_IMUX29_12", - "CMT_TOP_WW2A0_15", - "CMT_TOP_IMUX35_11", - "CMT_TOP_NE2A3_5", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_NW2A1_1", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP5_7", - "CMT_TOP_IMUX6_1", - "CMT_TOP_LH4_10", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SW2A3_7", - "CMT_TOP_WW4C3_10", - "CMT_TOP_LH3_12", - "CMT_TOP_WW4END1_10", - "CMT_TOP_IMUX44_0", - "CMT_TOP_BYP7_11", - "CMT_TOP_LOGIC_OUTS_L_B6_14", - "CMT_TOP_WL1END1_15", - "CMT_MMCM_PHASER_OUT_B_OCLK1X_90", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX28_1", - "CMT_TOP_SE4C3_14", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LH8_1", - "CMT_TOP_WW4A0_3", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_CLK1_0", - "CMT_TOP_IMUX2_10", - "CMT_TOP_SW4A0_9", - "CMT_TOP_IMUX27_4", - "CMT_TOP_SW4A1_7", - "CMT_TOP_IMUX40_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EE4C3_12", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_IMUX15_14", - "CMT_TOP_NW2A0_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_NW4A1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_WW2A1_9", - "CMT_TOP_BYP1_11", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SW4A1_15", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_LOGIC_OUTS_L_B15_15", - "CMT_TOP_NE4C2_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "CMT_LR_LOWER_B_MMCM_TESTIN6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_NE4C1_7", - "CMT_TOP_WW4B2_1", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_NE4C0_11", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_SE2A3_2", - "CMT_TOP_LH8_3", - "CMT_TOP_IMUX13_8", - "CMT_TOP_FAN4_13", - "CMT_TOP_EE2A3_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_BLOCK_OUTS_L_B0_12", - "CMT_LR_LOWER_B_MMCM_TESTIN0", - "CMT_LR_LOWER_B_MMCM_DEN", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_WW4C3_2", - "CMT_TOP_IMUX30_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_EE4B0_2", - "CMT_TOP_BYP6_10", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_LH5_1", - "CMT_TOP_EE4B2_11", - "CMT_TOP_BYP4_9", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_SE2A1_10", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_WR1END3_2", - "CMT_TOP_EE4B2_14", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LH8_10", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_WW4END2_15", - "CMT_TOP_IMUX13_12", - "CMT_TOP_LOGIC_OUTS_L_B18_14", - "CMT_TOP_LOGIC_OUTS_L_B21_15", - "CMT_TOP_IMUX34_7", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_NW4A2_7", - "CMT_TOP_LH9_11", - "CMT_LR_LOWER_B_MMCM_TESTIN2", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EE2A2_1", - "CMT_TOP_FAN4_6", - "CMT_TOP_EE4B3_9", - "CMT_TOP_BYP3_11", - "CMT_TOP_WW4END1_1", - "CMT_TOP_SW4END0_14", - "CMT_TOP_FAN0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_NE4C0_5", - "CMT_TOP_BYP0_11", - "CMT_TOP_SW2A0_8", - "CMT_TOP_NW2A2_2", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX0_10", - "CMT_LR_LOWER_B_MMCM_DO8", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_IMUX37_12", - "CMT_TOP_WR1END1_11", - "CMT_TOP_IMUX44_14", - "CMT_TOP_IMUX36_15", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_BYP4_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_LR_LOWER_B_MMCM_DADDR6", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_EE2A1_6", - "CMT_TOP_NE2A1_5", - "CMT_TOP_WR1END3_15", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_IMUX21_12", - "CMT_TOP_FAN3_4", - "CMT_TOP_LH7_5", - "CMT_TOP_IMUX0_15", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX17_11", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "CMT_TOP_BYP0_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "CMT_TOP_LOGIC_OUTS_L_B19_13", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_PHASER_A_OCLKDIV_TOIOI", - "CMT_TOP_IMUX43_8", - "CMT_TOP_SE2A3_5", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4C1_6", - "CMT_TOP_WW4C0_2", - "CMT_TOP_LH12_7", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_EE2A1_9", - "CMT_TOP_WW2END2_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_NE2A0_13", - "CMT_MMCM_PHASER_IN_A_ICLKDIV", - "CMT_TOP_BYP4_5", - "CMT_TOP_IMUX22_3", - "CMT_TOP_NE2A2_6", - "CMT_TOP_FAN5_10", - "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "CMT_TOP_SW4A3_13", - "CMT_TOP_EE4A0_7", - "CMT_TOP_WW2END1_10", - "CMT_TOP_IMUX19_12", - "CMT_TOP_LOGIC_OUTS_L_B23_14", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_IMUX38_11", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WW4B2_5", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_NE2A2_9", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_FAN1_13", - "CMT_TOP_FAN0_12", - "CMT_TOP_IMUX2_8", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END1_13", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WW2A2_10", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_IMUX28_2", - "CMT_TOP_SE4C0_13", - "CMT_TOP_WW4C1_4", - "CMT_TOP_EE4C2_7", - "CMT_TOP_LH12_1", - "CMT_TOP_NE2A0_3", - "CMT_TOP_SE2A3_13", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE4C0_4", - "CMT_TOP_IMUX46_13", - "CMT_TOP_LH11_0", - "CMT_TOP_WW2A1_2", - "CMT_TOP_FAN6_2", - "CMT_TOP_IMUX22_7", - "CMT_TOP_WW2END3_4", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SE2A2_4", - "CMT_TOP_NW4END0_12", - "CMT_TOP_SW4A1_0", - "CMT_MMCM_PHYCTRL_SYNC_BB_UP", - "CMT_TOP_IMUX1_8", - "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "CMT_TOP_WW4C2_4", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_2", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_IMUX39_15", - "CMT_TOP_IMUX20_11", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4END3_10", - "CMT_TOP_IMUX21_15", - "CMT_TOP_CLK0_2", - "CMT_L_LOWER_B_CLK_MMCM10", - "CMT_TOP_IMUX11_2", - "CMT_TOP_WW2END0_5", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_WW4B1_1", - "CMT_TOP_LH6_7", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE4B2_8", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_WW4A3_6", - "CMT_TOP_SW2A0_14", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B10_15", - "CMT_TOP_BYP5_11", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_EE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_EE2BEG3_14", - "CMT_TOP_CTRL1_3", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_CLK1_3", - "CMT_TOP_IMUX34_0", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_IMUX30_11", - "CMT_TOP_NE4BEG0_14", - "CMT_TOP_SE2A3_8", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX30_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_FAN7_3", - "CMT_TOP_EE4C1_15", - "CMT_TOP_IMUX33_6", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_IMUX4_13", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_NW4END1_9", - "CMT_LR_LOWER_B_MMCM_TESTOUT55", - "CMT_TOP_WW4END2_10", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_SW4END0_10", - "CMT_TOP_EE4BEG0_15", - "CMT_TOP_EE4C2_11", - "CMT_TOP_WW4END1_6", - "CMT_TOP_IMUX16_10", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_WR1END3_1", - "CMT_TOP_NE2A2_15", - "CMT_TOP_IMUX26_11", - "CMT_TOP_NE2A0_0", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX28_6", - "CMT_TOP_SE4C2_11", - "CMT_TOP_IMUX31_14", - "CMT_TOP_FAN2_14", - "CMT_TOP_EE4A2_2", - "CMT_TOP_IMUX13_1", - "CMT_TOP_WW4END0_14", - "CMT_TOP_IMUX24_0", - "CMT_TOP_NW4END2_4", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW4C3_3", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_EE4C3_5", - "CMT_TOP_SE2A0_8", - "CMT_TOP_IMUX0_2", - "CMT_TOP_EE4C0_5", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SW4END2_12", - "CMT_TOP_EE4BEG3_13", - "CMT_TOP_NW4END0_13", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX36_4", - "CMT_TOP_WW4C1_13", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_WR1END1_4", - "CMT_TOP_SW4END0_11", - "CMT_TOP_LH5_8", - "CMT_TOP_LH8_9", - "CMT_TOP_IMUX21_0", - "CMT_TOP_WL1END0_7", - "CMT_TOP_SW2A0_6", - "CMT_TOP_WL1END3_14", - "CMT_TOP_WW4END3_6", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_IMUX7_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_EE2A1_5", - "CMT_TOP_NW2A0_8", - "CMT_TOP_WL1END0_12", - "CMT_TOP_IMUX21_10", - "CMT_TOP_SW2A2_6", - "CMT_TOP_IMUX26_0", - "CMT_TOP_NW4A3_15", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_IMUX30_14", - "CMT_TOP_IMUX23_1", - "CMT_TOP_EL1BEG1_5", - "CMT_LR_LOWER_B_MMCM_TESTIN30", - "CMT_TOP_WW4C1_12", - "CMT_TOP_IMUX3_6", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_BYP0_0", - "CMT_TOP_SW4END0_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_ICLK_12", - "CMT_TOP_IMUX40_12", - "CMT_TOP_SW4A3_14", - "CMT_TOP_BYP3_4", - "CMT_TOP_WW4C2_1", - "CMT_TOP_BYP1_3", - "CMT_LR_LOWER_B_MMCM_TESTIN26", - "CMT_TOP_IMUX8_0", - "CMT_TOP_EE2A2_13", - "CMT_TOP_IMUX24_12", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_IMUX43_3", - "CMT_TOP_WW4END1_15", - "CMT_TOP_NW4A2_8", - "CMT_TOP_WR1END3_6", - "CMT_TOP_SE4BEG2_14", - "CMT_TOP_IMUX10_13", - "CMT_TOP_LH4_14", - "CMT_TOP_WW4C3_12", - "CMT_TOP_ICLK_5", - "CMT_TOP_WW2END0_15", - "CMT_TOP_IMUX0_12", - "CMT_TOP_IMUX39_13", - "CMT_TOP_WW2END2_4", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_IMUX18_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_IMUX9_15", - "CMT_TOP_NW4A2_9", - "CMT_MMCM_PHASER_OUT_B_OCLK", - "CMT_TOP_EE4A3_15", - "CMT_TOP_WW4END0_0", - "CMT_TOP_NW4END0_11", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_WW4C2_11", - "CMT_TOP_IMUX18_5", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SW2A1_1", - "CMT_TOP_EE4C0_12", - "CMT_TOP_BYP3_10", - "CMT_TOP_IMUX16_12", - "CMT_TOP_EE4A3_4", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX20_5", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_14", - "CMT_TOP_WW4B0_13", - "CMT_LR_LOWER_B_MMCM_TESTOUT6", - "CMT_TOP_WL1END2_15", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_IMUX24_8", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LH3_5", - "CMT_TOP_IMUX26_2", - "CMT_TOP_LOGIC_OUTS_L_B11_15", - "CMT_TOP_WW4A0_11", - "CMT_TOP_IMUX19_8", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_SE2A1_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "CMT_TOP_WL1END1_12", - "CMT_TOP_BYP4_11", - "CMT_TOP_NW4A3_10", - "CMT_TOP_SE4BEG2_13", - "CMT_TOP_FAN1_7", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_WW4A2_0", - "CMT_TOP_IMUX28_10", - "CMT_TOP_NW4A2_12", - "CMT_LR_LOWER_B_MMCM_DI0", - "MMCMOUT_CLK_FREQ_BB_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_WW2A3_9", - "CMT_TOP_NE4C2_14", - "CMT_TOP_EE4A1_4", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX33_12", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_IMUX46_5", - "CMT_TOP_NE2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B17_13", - "CMT_TOP_EE4A1_13", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LH10_12", - "MMCM_CLK_FREQ_BB_REBUF2_NS", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_WR1END2_8", - "CMT_TOP_IMUX10_12", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE4A1_14", - "CMT_LR_LOWER_B_MMCM_DO13", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX26_7", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_FAN3_14", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_NW4END2_10", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2BEG0_14", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_FAN3_8", - "CMT_TOP_EE4BEG3_2", - "CMT_LR_LOWER_B_MMCM_CLKIN2", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_SE2A2_13", - "CMT_TOP_NW4END0_1", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_FAN3_6", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_SW4END1_14", - "CMT_TOP_EE2A3_10", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_SW4END3_1", - "CMT_TOP_LOGIC_OUTS_L_B1_15", - "CMT_LR_LOWER_B_MMCM_DADDR4", - "CMT_TOP_IMUX22_11", - "CMT_TOP_WW4A2_7", - "CMT_TOP_NW4A2_1", - "CMT_TOP_IMUX22_15", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW4C3_8", - "CMT_TOP_NE2A0_8", - "CMT_LR_LOWER_B_MMCM_DI4", - "CMT_TOP_IMUX12_10", - "CMT_TOP_WW4C3_9", - "CMT_TOP_NE2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_FAN5_9", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_IMUX4_15", - "CMT_TOP_FAN3_0", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_3", - "CMT_TOP_SW2A0_7", - "CMT_LR_LOWER_B_MMCM_DI10", - "CMT_TOP_LH3_13", - "CMT_TOP_IMUX3_1", - "CMT_TOP_NE4C0_1", - "CMT_TOP_WL1END3_4", - "CMT_TOP_IMUX37_9", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_NW4END3_5", - "CMT_TOP_LH12_13", - "CMT_TOP_IMUX24_14", - "CMT_TOP_WW2A2_7", - "CMT_TOP_FAN2_5", - "CMT_TOP_IMUX18_14", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WL1END3_0", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_IMUX36_1", - "CMT_TOP_SW2A1_9", - "CMT_TOP_EE4A3_2", - "CMT_TOP_BYP3_14", - "CMT_TOP_IMUX15_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LH3_6", - "CMT_TOP_IMUX27_6", - "CMT_TOP_WW2END2_0", - "CMT_TOP_NW4END1_13", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX43_2", - "CMT_TOP_EE4B2_13", - "CMT_TOP_WW4A1_15", - "CMT_TOP_NE4C3_9", - "CMT_TOP_WW2END2_9", - "CMT_TOP_IMUX29_13", - "CMT_TOP_LH9_15", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW2A1_13", - "CMT_TOP_IMUX4_5", - "CMT_PHASER_A_OCLK_TOIOI", - "CMT_TOP_EE4C0_9", - "CMT_TOP_BYP7_12", - "CMT_LR_LOWER_B_MMCM_DO1", - "CMT_TOP_ER1BEG3_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_WR1END2_10", - "CMT_TOP_NW4A0_14", - "CMT_TOP_NE4C1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_SW2A3_12", - "CMT_TOP_WW2A0_8", - "CMT_TOP_SE4C2_8", - "CMT_TOP_IMUX26_12", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_IMUX38_8", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_LH1_3", - "CMT_TOP_BYP1_2", - "CMT_TOP_LOGIC_OUTS_L_B4_15", - "CMT_TOP_IMUX26_5", - "CMT_TOP_SE4C3_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_NE4C0_10", - "CMT_TOP_WW4C0_12", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_LOGIC_OUTS_L_B3_14", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX38_15", - "CMT_TOP_WW4C0_1", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_IMUX38_6", - "CMT_TOP_LH6_10", - "CMT_TOP_FAN3_12", - "CMT_TOP_LH10_15", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_NW2A2_13", - "CMT_TOP_WW4B3_4", - "CMT_TOP_IMUX16_15", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_SW4A1_13", - "CMT_TOP_IMUX1_10", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WL1END2_13", - "CMT_TOP_SE2A0_9", - "CMT_TOP_WW4B0_12", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX36_7", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_IMUX39_8", - "CMT_TOP_SE2A0_14", - "CMT_TOP_WW4B0_5", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_BYP4_7", - "CMT_TOP_IMUX43_9", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_NE4BEG3_2", - "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "CMT_TOP_WW2END3_10", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_LR_LOWER_B_MMCM_TESTIN14", - "CMT_TOP_IMUX12_12", - "CMT_TOP_SW2A0_5", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_LH4_12", - "CMT_TOP_SW4END1_9", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_ER1BEG3_15", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_FAN0_2", - "CMT_TOP_BYP7_15", - "CMT_TOP_IMUX19_1", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_NW2A3_11", - "CMT_TOP_IMUX41_0", - "CMT_TOP_FAN3_2", - "CMT_TOP_WW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_SW2A3_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SE2A1_11", - "CMT_TOP_WW4A0_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_EE4B0_0", - "CMT_TOP_NW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_NE2A3_14", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_NW2A3_3", - "CMT_TOP_SE4C0_8", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4END2_3", - "CMT_TOP_NE2A3_10", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_L_LOWER_B_CLK_IN1_HCLK", - "CMT_TOP_NW4END3_15", - "CMT_TOP_LH1_5", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_WW4B2_10", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END3_14", - "CMT_TOP_SW4END1_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_IMUX25_6", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LH9_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX47_4", - "CMT_TOP_FAN0_14", - "CMT_TOP_IMUX37_3", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_LH1_9", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_ICLK_13", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_MMCM_PHASERREF_BELOW0", - "CMT_TOP_EE2BEG1_14", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_SW4A3_12", - "CMT_TOP_EE4C2_6", - "CMT_TOP_IMUX36_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_WW4A2_14", - "CMT_TOP_WW4A3_3", - "CMT_TOP_LH2_8", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX39_12", - "CMT_LR_LOWER_B_MMCM_TESTOUT7", - "CMT_TOP_IMUX29_8", - "CMT_TOP_FAN7_12", - "CMT_TOP_WW2A2_15", - "CMT_TOP_IMUX34_10", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_WW4A3_2", - "CMT_LR_LOWER_B_MMCM_PWRDWN", - "CMT_TOP_EE4B1_12", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_EE4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_LH12_12", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_WR1END2_14", - "CMT_TOP_NE2A2_11", - "CMT_TOP_LH3_1", - "CMT_TOP_SW4A3_5", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_WW4END1_5", - "MMCM_CLK_FREQ_BB_NS3", - "CMT_TOP_EE2BEG3_13", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX0_14", - "CMT_TOP_IMUX11_8", - "CMT_TOP_NW4END2_11", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX8_2", - "CMT_TOP_EL1BEG1_12", - "CMT_L_LOWER_B_CLK_MMCM11", - "CMT_TOP_OCLK1X_90_6", - "CMT_LR_LOWER_B_MMCM_DI1", - "CMT_TOP_IMUX17_14", - "CMT_TOP_WW2A3_3", - "CMT_TOP_EE4A2_3", - "CMT_TOP_SW4A1_1", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_8", - "CMT_TOP_WW4A1_6", - "CMT_TOP_IMUX41_2", - "CMT_TOP_LH8_6", - "CMT_TOP_SE4C1_8", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WW4A2_6", - "CMT_TOP_BYP0_6", - "CMT_TOP_IMUX43_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX42_12", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WL1END1_13", - "CMT_TOP_NE4C1_14", - "CMT_TOP_NW4END3_11", - "CMT_TOP_WR1END3_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_ER1BEG0_15", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_EE2A2_15", - "CMT_LR_LOWER_B_MMCM_DI5", - "CMT_TOP_NW4A0_4", - "CMT_TOP_IMUX24_4", - "CMT_TOP_EE4C1_10", - "CMT_TOP_CLK0_11", - "CMT_LR_LOWER_B_MMCM_TESTIN18", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WW4C1_8", - "CMT_TOP_IMUX22_1", - "CMT_TOP_NW2A0_7", - "CMT_TOP_LH1_11", - "CMT_L_LOWER_B_CLK_FREQ_BB2", - "CMT_TOP_IMUX17_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_IMUX19_11", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX4_1", - "CMT_TOP_OCLKDIV_13", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX10_9", - "CMT_TOP_EE2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_FAN3_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT5", - "CMT_TOP_IMUX11_12", - "CMT_TOP_CLK1_4", - "CMT_TOP_LH5_14", - "CMT_TOP_LH2_2", - "CMT_TOP_WW2END0_14", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_IMUX44_15", - "CMT_TOP_LOGIC_OUTS_L_B20_13", - "CMT_TOP_NE4C2_3", - "CMT_TOP_EE4A2_7", - "CMT_TOP_LOGIC_OUTS_L_B16_14", - "CMT_TOP_IMUX11_0", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_SW2A2_13", - "CMT_TOP_IMUX38_3", - "CMT_TOP_SW4A0_13", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_10", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_10", - "CMT_TOP_LH3_9", - "CMT_TOP_NW4END2_2", - "CMT_TOP_WW4A1_14", - "CMT_TOP_WW2A2_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_LH4_9", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4B0_6", - "CMT_TOP_BYP1_9", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_NW4A1_5", - "CMT_TOP_WW2END3_13", - "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "CMT_TOP_SE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_EL1BEG3_15", - "CMT_TOP_SE4BEG2_12", - "CMT_L_LOWER_B_CLK_MMCM3", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_SW4END3_10", - "CMT_TOP_IMUX9_1", - "CMT_TOP_NW4A1_9", - "CMT_TOP_WW4C2_14", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_BYP7_8", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX46_7", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_IMUX30_1", - "CMT_TOP_WW4C0_5", - "CMT_TOP_NW4A1_2", - "CMT_TOP_WW4C3_14", - "CMT_TOP_LH4_13", - "CMT_TOP_WW2END0_2", - "CMT_TOP_NW4A1_15", - "CMT_TOP_FAN0_0", - "CMT_TOP_IMUX32_13", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX28_13", - "CMT_TOP_IMUX18_8", - "CMT_TOP_CLK0_14", - "CMT_TOP_NW4A1_12", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4C0_13", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX20_4", - "CMT_TOP_ER1BEG2_14", - "CMT_TOP_EE4C3_6", - "CMT_TOP_FAN6_12", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_IMUX39_11", - "CMT_TOP_NE4C0_2", - "CMT_TOP_EE4B1_2", - "CMT_LR_LOWER_B_MMCM_TESTOUT59", - "CMT_TOP_IMUX4_9", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SE4C1_1", - "CMT_TOP_EE4A1_9", - "CMT_TOP_IMUX21_14", - "CMT_TOP_IMUX30_2", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_EE2A2_2", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4A2_8", - "CMT_TOP_IMUX30_15", - "CMT_MMCM_PHASER_IN_A_ICLK", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_IMUX23_8", - "CMT_TOP_SW4END0_6", - "CMT_TOP_IMUX12_2", - "CMT_TOP_NW2A2_7", - "CMT_TOP_LOGIC_OUTS_L_B18_15", - "CMT_TOP_WL1END2_7", - "CMT_TOP_BYP5_1", - "CMT_TOP_EE4B1_9", - "CMT_TOP_SE4C0_15", - "CMT_TOP_IMUX43_15", - "CMT_TOP_IMUX2_12", - "CMT_TOP_NE2A3_15", - "CMT_TOP_IMUX33_0", - "CMT_TOP_WW2A2_9", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_IMUX18_15", - "CMT_TOP_IMUX27_15", - "CMT_TOP_OCLK_7", - "CMT_TOP_FAN1_10", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_SW2A1_10", - "CMT_TOP_IMUX19_7", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_IMUX16_14", - "CMT_TOP_SE4C0_6", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_IMUX3_0", - "CMT_TOP_WL1END1_8", - "CMT_TOP_NW4END1_5", - "CMT_LR_LOWER_B_MMCM_DO5", - "CMT_LR_LOWER_B_MMCM_TESTIN24", - "CMT_TOP_BYP5_6", - "CMT_TOP_LH6_2", - "CMT_TOP_IMUX39_6", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_IMUX36_2", - "CMT_TOP_WW2A0_5", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_BYP5_14", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_BYP2_0", - "CMT_TOP_IMUX8_3", - "CMT_TOP_ICLK_6", - "CMT_TOP_WW2END2_14", - "CMT_TOP_LH2_0", - "CMT_TOP_EE2A3_15", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX40_2", - "CMT_TOP_BYP5_15", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "CMT_TOP_WW4END3_1", - "CMT_TOP_SW4A2_4", - "CMT_TOP_LH11_11", - "CMT_TOP_WW4C0_15", - "CMT_TOP_IMUX46_2", - "CMT_TOP_LOGIC_OUTS_L_B12_14", - "CMT_TOP_NE2A3_1", - "CMT_TOP_WW4B3_13", - "CMT_TOP_IMUX16_13", - "CMT_TOP_NW4A3_2", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_IMUX17_10", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX30_12", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW4END1_3", - "CMT_TOP_SE4BEG1_15", - "CMT_TOP_NW2A3_7", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_NW4A3_8", - "CMT_TOP_LOGIC_OUTS_L_B6_13", - "CMT_TOP_SW4END2_8", - "CMT_TOP_WL1END3_12", - "CMT_TOP_IMUX43_13", - "CMT_TOP_SE2A0_11", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_SW2A1_15", - "CMT_TOP_SW4A1_14", - "CMT_TOP_IMUX24_13", - "CMT_TOP_EE4A1_12", - "CMT_TOP_WW2END0_7", - "CMT_TOP_SW4A2_13", - "CMT_TOP_WW4A2_15", - "CMT_TOP_EE4C0_6", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_EE4C0_7", - "CMT_TOP_WL1END0_0", - "CMT_TOP_EE4C3_15", - "CMT_TOP_FAN7_2", - "CMT_TOP_WL1END3_1", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_LH3_15", - "CMT_TOP_LH8_4", - "CMT_TOP_LH5_6", - "CMT_TOP_BYP2_11", - "CMT_TOP_SW4A0_6", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_WR1END2_12", - "CMT_TOP_IMUX7_14", - "CMT_TOP_BYP7_4", - "CMT_TOP_EE4C2_12", - "CMT_TOP_LH10_6", - "CMT_TOP_WW4END1_14", - "CMT_TOP_SE4C2_4", - "CMT_TOP_FAN1_12", - "CMT_TOP_IMUX35_9", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_EE2BEG0_15", - "CMT_TOP_IMUX46_4", - "CMT_TOP_LH4_2", - "CMT_TOP_IMUX6_12", - "CMT_TOP_IMUX44_3", - "CMT_TOP_EE4A3_8", - "CMT_TOP_IMUX24_2", - "CMT_TOP_EE4A3_11", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX34_5", - "CMT_TOP_LH4_15", - "CMT_TOP_NW4END2_9", - "CMT_TOP_IMUX20_9", - "CMT_TOP_WW4B1_13", - "CMT_TOP_IMUX29_1", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_IMUX13_13", - "CMT_TOP_EL1BEG3_14", - "CMT_TOP_SW4A2_3", - "CMT_TOP_FAN1_9", - "CMT_TOP_BYP7_1", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WL1END3_8", - "CMT_L_LOWER_B_CLK_IN3_INT", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX35_0", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_IMUX19_6", - "CMT_L_LOWER_B_CLK_MMCM8", - "CMT_TOP_WW2A3_8", - "CMT_TOP_OCLK_0", - "CMT_TOP_SE4C2_13", - "CMT_TOP_IMUX13_11", - "CMT_TOP_IMUX17_7", - "CMT_TOP_IMUX31_7", - "CMT_TOP_WR1END0_14", - "CMT_LR_LOWER_B_MMCM_DADDR5", - "CMT_TOP_WL1END1_11", - "CMT_TOP_EE2BEG1_15", - "CMT_TOP_IMUX2_2", - "CMT_TOP_WW4END3_5", - "CMT_TOP_LH1_1", - "CMT_TOP_FAN5_8", - "CMT_TOP_SW4A0_15", - "CMT_TOP_NW4END3_8", - "CMT_TOP_WW4B2_15", - "CMT_TOP_WW4A1_1", - "CMT_LR_LOWER_B_MMCM_DO7", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_IMUX22_13", - "CMT_TOP_EE2A3_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT61", - "CMT_TOP_WW2END2_3", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_WW2END2_6", - "CMT_TOP_IMUX41_10", - "CMT_LR_LOWER_B_MMCM_DO9", - "CMT_TOP_SW4A0_14", - "CMT_TOP_EE4B2_1", - "CMT_TOP_NW4END3_1", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_12", - "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "CMT_TOP_EE4B1_13", - "CMT_TOP_IMUX13_15", - "CMT_TOP_IMUX33_13", - "CMT_TOP_LH3_0", - "CMT_TOP_LH2_5", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_IMUX19_14", - "CMT_TOP_EE4A3_3", - "CMT_TOP_NW4A2_3", - "CMT_L_LOWER_B_CLK_MMCM5", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_WW4END2_14", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SE4C0_12", - "CMT_TOP_IMUX34_8", - "CMT_TOP_EE4A3_14", - "CMT_TOP_SW4A2_10", - "CMT_TOP_NW2A3_1", - "CMT_TOP_IMUX31_6", - "CMT_TOP_WW4B3_15", - "CMT_TOP_IMUX32_11", - "CMT_TOP_WW4B3_7", - "CMT_TOP_LH11_9", - "CMT_TOP_NE2A2_2", - "CMT_TOP_FAN7_14", - "CMT_TOP_FAN5_3", - "CMT_TOP_NW4A2_0", - "CMT_TOP_IMUX12_15", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_WW4C2_10", - "CMT_TOP_BYP7_0", - "CMT_TOP_LH6_0", - "CMT_TOP_NE4C1_4", - "CMT_TOP_IMUX16_9", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_EE4A0_10", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B7_15", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX31_13", - "CMT_TOP_WW4C0_10", - "CMT_TOP_IMUX45_14", - "CMT_TOP_FAN1_2", - "CMT_TOP_MONITOR_P_15", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_FAN1_15", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_WW4B2_6", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_IMUX29_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LH3_11", - "CMT_TOP_IMUX32_7", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_WR1END0_15", - "CMT_TOP_BYP2_3", - "CMT_TOP_IMUX1_6", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX20_3", - "CMT_TOP_LH7_3", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX28_8", - "CMT_TOP_NW4END2_5", - "CMT_TOP_WW2A0_3", - "CMT_TOP_SE2A2_14", - "CMT_TOP_IMUX33_9", - "CMT_TOP_WR1END1_9", - "CMT_TOP_IMUX18_4", - "CMT_LR_LOWER_B_MMCM_DADDR2", - "CMT_TOP_WW4END1_13", - "CMT_TOP_BYP1_13", - "CMT_TOP_IMUX23_11", - "CMT_TOP_SW4END2_4", - "CMT_TOP_FAN6_0", - "CMT_TOP_LH6_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_IMUX4_3", - "CMT_TOP_EE4B3_14", - "CMT_TOP_WL1END2_12", - "CMT_TOP_SW4END3_3", - "CMT_TOP_NE4C3_14", - "CMT_TOP_WW4B0_3", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP3_2", - "CMT_TOP_CTRL0_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_SW4END0_13", - "CMT_TOP_CLK1_8", - "CMT_TOP_SE2A1_14", - "CMT_TOP_FAN3_3", - "CMT_TOP_EE4A3_6", - "CMT_TOP_OCLK_13", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_LR_LOWER_B_MMCM_TESTOUT62", - "CMT_TOP_IMUX41_14", - "CMT_TOP_IMUX42_0", - "CMT_TOP_LH12_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT60", - "CMT_TOP_IMUX20_13", - "CMT_TOP_SW2A0_9", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_FAN0_6", - "CMT_MMCM_DQS_TO_PHASERA", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_NE2A2_13", - "CMT_TOP_EE4A2_13", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "CMT_TOP_WW4A0_13", - "CMT_TOP_SW4END0_1", - "CMT_TOP_FAN5_11", - "CMT_TOP_IMUX1_0", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_NW2A3_4", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_NE4C0_15", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_WW4END1_9", - "CMT_TOP_EE2A2_4", - "CMT_TOP_ER1BEG1_13", - "CMT_TOP_WL1END0_4", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_IMUX4_10", - "CMT_TOP_WL1END0_14", - "CMT_TOP_WL1END1_14", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_IMUX45_13", - "CMT_TOP_IMUX34_12", - "CMT_TOP_SW4END3_4", - "CMT_TOP_WW4C3_1", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_EE4BEG3_8", - "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "CMT_TOP_WL1END0_6", - "CMT_TOP_IMUX41_13", - "CMT_TOP_EE4A0_3", - "CMT_TOP_NW4A3_6", - "CMT_TOP_LH7_12", - "CMT_TOP_BYP2_5", - "CMT_TOP_ICLK_0", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LH6_9", - "CMT_TOP_CTRL1_9", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_IMUX33_4", - "CMT_TOP_NW2A1_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_LOGIC_OUTS_L_B19_14", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_EE4B0_4", - "CMT_TOP_NE2A1_0", - "CMT_TOP_IMUX1_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_WR1END0_6", - "CMT_TOP_LH12_2", - "CMT_TOP_FAN5_5", - "CMT_TOP_IMUX4_8", - "CMT_TOP_SW2A2_7", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX5_15", - "CMT_TOP_LOGIC_OUTS_L_B22_15", - "CMT_TOP_WW4A3_7", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_WL1END1_10", - "CMT_TOP_BYP6_3", - "CMT_TOP_FAN2_6", - "CMT_TOP_WR1END1_1", - "CMT_TOP_OCLK_3", - "CMT_TOP_EE4C2_8", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_IMUX31_9", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX35_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "CMT_TOP_OCLK_8", - "CMT_TOP_FAN4_3", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_IMUX8_15", - "CMT_TOP_IMUX9_14", - "CMT_TOP_NE4BEG0_5", - "CMT_LR_LOWER_B_MMCM_DADDR1", - "CMT_TOP_LH4_4", - "CMT_TOP_EE4B3_0", - "CMT_TOP_NE4C0_12", - "CMT_TOP_NE4C2_13", - "CMT_TOP_EE4C3_11", - "CMT_TOP_LOGIC_OUTS_L_B7_14", - "CMT_TOP_FAN4_8", - "CMT_TOP_SW2A3_13", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_LOGIC_OUTS_L_B23_15", - "CMT_LR_LOWER_B_MMCM_DO12", - "CMT_TOP_EE2A3_7", - "CMT_TOP_WR1END1_15", - "CMT_TOP_EE4B1_5", - "CMT_TOP_OCLKDIV_15", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_LH8_13", - "CMT_TOP_IMUX42_14", - "CMT_TOP_IMUX33_1", - "CMT_TOP_EE4C1_5", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4B3_0", - "CMT_TOP_LOGIC_OUTS_L_B14_15", - "CMT_TOP_LH2_1", - "CMT_TOP_LH6_8", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_WL1END0_1", - "CMT_TOP_NE2A3_3", - "CMT_TOP_IMUX12_8", - "CMT_TOP_EE4A1_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_EE4BEG1_15", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_WW4A1_11", - "CMT_TOP_IMUX46_9", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE4C2_6", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX18_1", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_NW4END1_10", - "CMT_TOP_IMUX20_8", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NE2A3_2", - "CMT_TOP_SE2A0_6", - "CMT_TOP_IMUX30_3", - "CMT_TOP_LH7_10", - "CMT_TOP_OCLK_6", - "CMT_TOP_WW4END0_12", - "CMT_TOP_SW4END0_9", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX37_6", - "CMT_TOP_EE4BEG0_13", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_LOGIC_OUTS_L_B19_15", - "CMT_TOP_WW4END3_14", - "CMT_TOP_BLOCK_OUTS_L_B3_14", - "CMT_TOP_WW4B2_3", - "CMT_TOP_BYP4_14", - "CMT_TOP_WW4C2_5", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_EE4B2_5", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WW4A1_5", - "CMT_TOP_BYP3_7", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_FAN2_1", - "CMT_TOP_IMUX36_11", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_IMUX44_6", - "CMT_TOP_OCLK_1", - "CMT_TOP_NE4BEG2_13", - "CMT_TOP_NW2A0_9", - "CMT_TOP_WW4C2_12", - "CMT_TOP_IMUX43_12", - "CMT_TOP_IMUX36_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_CLK0_15", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_IMUX6_15", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_WW4END2_2", - "CMT_TOP_LH12_9", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_NE2A2_10", - "CMT_TOP_SW4END2_9", - "CMT_TOP_EE2A2_3", - "CMT_TOP_LH4_7", - "CMT_TOP_ER1BEG1_2", - "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_L_LOWER_B_CLK_MMCM7", - "CMT_TOP_IMUX6_0", - "CMT_LR_LOWER_B_MMCM_TESTOUT50", - "CMT_LR_LOWER_B_MMCM_TESTOUT9", - "CMT_TOP_NE2A0_9", - "CMT_TOP_WW4B3_3", - "CMT_TOP_BYP4_6", - "CMT_TOP_FAN3_10", - "CMT_TOP_BYP6_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_NE2A1_1", - "CMT_TOP_WW4END1_8", - "CMT_TOP_SW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_CTRL0_3", - "CMT_TOP_WW4B3_1", - "CMT_TOP_NW4A2_4", - "CMT_TOP_OCLK1X_90_15", - "CMT_TOP_LH4_11", - "CMT_TOP_SW4END1_13", - "CMT_TOP_IMUX6_14", - "CMT_LR_LOWER_B_MMCM_DO3", - "CMT_TOP_LOGIC_OUTS_L_B3_13", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_SE4C3_3", - "CMT_TOP_WW2END1_9", - "CMT_TOP_LOGIC_OUTS_L_B11_13", - "CMT_TOP_EE4BEG0_14", - "CMT_LR_LOWER_B_MMCM_DI12", - "CMT_TOP_NE4C3_1", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WL1END3_9", - "CMT_TOP_IMUX23_15", - "CMT_TOP_SE4C0_4", - "CMT_TOP_IMUX47_15", - "CMT_TOP_EE4C3_0", - "CMT_TOP_IMUX9_10", - "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", - "CMT_TOP_LOGIC_OUTS_L_B5_14", - "CMT_TOP_WW4C1_3", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_EE4A1_11", - "CMT_TOP_NW2A2_10", - "CMT_TOP_CTRL1_8", - "CMT_TOP_WL1END1_1", - "CMT_TOP_OCLKDIV_5", - "CMT_LR_LOWER_B_MMCM_TESTIN20", - "CMT_TOP_NW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_NW2A1_11", - "CMT_TOP_EE4B2_0", - "CMT_TOP_LH5_7", - "CMT_LR_LOWER_B_MMCM_TESTIN27", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX2_5", - "CMT_TOP_LH11_15", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_CLK0_1", - "CMT_TOP_IMUX6_4", - "CMT_TOP_NW4A2_11", - "CMT_TOP_EE2A2_8", - "CMT_TOP_LH1_14", - "CMT_TOP_SE4C3_7", - "CMT_TOP_WW4C0_7", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_SW2A1_12", - "CMT_TOP_NW4A1_14", - "CMT_TOP_SE4C2_5", - "CMT_TOP_IMUX32_0", - "CMT_TOP_SW2A3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_NE4BEG0_10", - "CMT_MMCM_PHASERREF0", - "CMT_TOP_WW2END3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_SW2A3_14", - "CMT_TOP_EE4B1_4", - "CMT_TOP_IMUX29_15", - "CMT_TOP_IMUX43_7", - "CMT_TOP_NW4END3_13", - "CMT_TOP_OCLK_14", - "CMT_TOP_IMUX27_5", - "CMT_TOP_IMUX20_14", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_EE4C0_0", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_LOGIC_OUTS_L_B5_15", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_WW4B0_9", - "CMT_TOP_OCLK1X_90_10", - "CMT_MMCM_PHASERA_DTSBUS0", - "CMT_TOP_NW4END2_0", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_WW4END3_11", - "MMCM_CLK_FREQ_BB_REBUF3_NS", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_EE4B1_3", - "CMT_TOP_LOGIC_OUTS_L_B2_14", - "CMT_TOP_NW4END3_2", - "CMT_TOP_IMUX21_1", - "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "CMT_TOP_IMUX31_12", - "MMCM_CLK_FREQ_BB_NS2", - "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "CMT_TOP_SW4END0_0", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW2END1_7", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_IMUX32_12", - "CMT_TOP_WW4C0_3", - "CMT_TOP_BYP7_10", - "CMT_TOP_IMUX6_9", - "CMT_TOP_WW4A0_1", - "CMT_TOP_EE4B1_11", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_FAN5_13", - "CMT_TOP_IMUX38_13", - "CMT_TOP_WW4C2_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_NW4A0_10", - "CMT_TOP_EE4B2_12", - "CMT_TOP_WW4END0_11", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NE4C3_4", - "CMT_TOP_WW2A1_14", - "CMT_TOP_BYP6_9", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_IMUX44_9", - "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "CMT_TOP_IMUX29_10", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW2A0_2", - "CMT_TOP_BYP2_8", - "CMT_TOP_WW2END2_2", - "CMT_L_LOWER_B_CLK_PERF3", - "CMT_TOP_WW4C0_0", - "CMT_TOP_BYP6_8", - "CMT_LR_LOWER_B_MMCM_DI11", - "CMT_TOP_IMUX28_0", - "CMT_TOP_SE4BEG3_15", - "CMT_TOP_NW2A1_14", - "CMT_TOP_LOGIC_OUTS_L_B21_14", - "CMT_TOP_EE4A2_0", - "CMT_TOP_NE4BEG1_13", - "CMT_TOP_BYP2_12", - "CMT_TOP_SW2A2_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_LH5_13", - "CMT_TOP_LH12_10", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_LOGIC_OUTS_L_B13_13", - "CMT_TOP_SW2A3_5", - "CMT_TOP_IMUX39_14", - "CMT_TOP_SW4END1_10", - "CMT_TOP_NW4END0_5", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_IMUX3_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_IMUX2_15", - "CMT_TOP_SW4END3_8", - "CMT_TOP_NW4END0_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT8", - "CMT_TOP_NW4END3_6", - "CMT_TOP_IMUX14_4", - "CMT_TOP_LH6_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SE2A2_9", - "CMT_TOP_FAN6_14", - "CMT_TOP_SW4A2_0", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_NW4A2_15", - "CMT_TOP_WL1END3_2", - "CMT_PHASER_A_OCLK90_TOIOI", - "CMT_TOP_WW2A1_10", - "CMT_TOP_SW4A2_7", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_WW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_FAN4_0", - "CMT_TOP_IMUX0_11", - "CMT_TOP_SE2A1_13", - "CMT_TOP_IMUX41_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_WW4C2_13", - "CMT_TOP_WW4A3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_LH6_1", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WL1END2_9", - "CMT_TOP_BYP4_10", - "CMT_TOP_IMUX11_4", - "CMT_TOP_WL1END3_10", - "CMT_TOP_IMUX47_12", - "CMT_TOP_NE4C3_0", - "CMT_TOP_WW4END1_0", - "CMT_TOP_FAN7_5", - "CMT_TOP_OCLK_12", - "CMT_TOP_SE4C0_9", - "CMT_TOP_BYP0_8", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_IMUX22_2", - "CMT_TOP_FAN4_5", - "CMT_TOP_NE4C1_13", - "CMT_LR_LOWER_B_MMCM_DWE", - "CMT_TOP_NE2A1_12", - "CMT_TOP_EE4B2_6", - "CMT_TOP_SW4A1_3", - "CMT_TOP_WW4END2_0", - "CMT_TOP_FAN5_15", - "CMT_TOP_WW2A2_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_IMUX19_3", - "CMT_TOP_SW4END1_12", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_WW4A3_13", - "CMT_TOP_SE4C1_12", - "CMT_TOP_IMUX0_13", - "CMT_TOP_EE4A1_8", - "CMT_TOP_WW4B1_2", - "CMT_LR_LOWER_B_MMCM_DO4", - "CMT_TOP_IMUX9_9", - "CMT_TOP_IMUX1_13", - "CMT_TOP_NW4END3_14", - "CMT_TOP_IMUX42_15", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_SW2A0_12", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LH9_9", - "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_SE4BEG3_13", - "CMT_TOP_NE4C1_12", - "CMT_TOP_WW2A2_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_WW4B3_9", - "CMT_TOP_NE4C3_10", - "CMT_TOP_WW2A0_14", - "CMT_TOP_FAN5_6", - "CMT_LR_LOWER_B_MMCM_DADDR3", - "CMT_TOP_IMUX30_6", - "CMT_TOP_BYP3_12", - "CMT_TOP_IMUX23_5", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_IMUX1_15", - "CMT_TOP_FAN0_10", - "CMT_TOP_IMUX40_10", - "CMT_TOP_IMUX38_14", - "CMT_TOP_LH2_3", - "CMT_TOP_IMUX5_14", - "CMT_TOP_MONITOR_N_14", - "CMT_TOP_EE4A0_13", - "CMT_TOP_EE4C3_8", - "CMT_MMCM_PHASERA_DQSBUS1", - "CMT_TOP_SW4END2_3", - "CMT_TOP_WW4B2_12", - "CMT_TOP_NE4C0_13", - "CMT_TOP_IMUX46_12", - "CMT_LR_LOWER_B_MMCM_DI3", - "CMT_TOP_EE2A0_9", - "CMT_TOP_WW4A1_3", - "CMT_TOP_BYP5_10", - "CMT_TOP_SW2A0_13", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4B0_13", - "CMT_TOP_WR1END0_4", - "CMT_TOP_IMUX42_13", - "CMT_TOP_NW2A0_2", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_SE4C3_0", - "CMT_TOP_LH5_15", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_BLOCK_OUTS_L_B0_15", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_SE2A1_5", - "CMT_TOP_FAN0_11", - "CMT_TOP_LH11_13", - "CMT_TOP_WL1END3_11", - "CMT_TOP_FAN6_5", - "CMT_TOP_EE4A2_4", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_WR1END0_7", - "CMT_TOP_EE4A3_7", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A3_9", - "CMT_TOP_ICLK_14", - "CMT_TOP_NE2A1_4", - "CMT_TOP_WR1END1_0", - "CMT_TOP_LOGIC_OUTS_L_B22_13", - "CMT_TOP_EE4BEG2_12", - "CMT_LR_LOWER_B_MMCM_CLKIN1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_EE4A2_15", - "CMT_TOP_IMUX32_15", - "CMT_TOP_LOGIC_OUTS_L_B21_13", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_EL1BEG1_14", - "CMT_TOP_IMUX32_1", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4BEG1_14", - "CMT_TOP_BYP6_13", - "CMT_TOP_EE4C1_1", - "CMT_TOP_FAN5_14", - "CMT_TOP_WW2END3_12", - "CMT_TOP_IMUX20_2", - "CMT_TOP_LH8_14", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_NW4END1_11", - "CMT_TOP_FAN0_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_WW2END1_11", - "CMT_TOP_FAN0_9", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NW4A0_0", - "CMT_TOP_SW4A3_15", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_EE4C1_12", - "CMT_TOP_BYP1_8", - "CMT_TOP_IMUX28_15", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EE4B2_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_EE4B3_2", - "CMT_TOP_SE4C1_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_IMUX25_12", - "CMT_TOP_IMUX36_3", - "CMT_TOP_SE4C2_3", - "CMT_TOP_NW4END0_3", - "CMT_TOP_FAN4_9", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX27_8", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_WL1END3_13", - "CMT_TOP_ICLKDIV_15", - "CMT_TOP_WW4B1_4", - "CMT_MMCM_PHASERA_CTSBUS0", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_EE4A3_0", - "CMT_L_LOWER_B_CLK_PERF2", - "CMT_TOP_IMUX38_1", - "CMT_TOP_BYP3_6", - "CMT_MMCM_PHASERA_DTSBUS1", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A2_12", - "CMT_TOP_EE2A3_14", - "CMT_TOP_WW4B1_3", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_BYP2_10", - "CMT_TOP_IMUX27_11", - "CMT_TOP_IMUX33_15", - "CMT_TOP_SE2A2_3", - "CMT_TOP_NE2A1_15", - "CMT_TOP_FAN7_4", - "CMT_TOP_SE4C3_6", - "CMT_TOP_NE4C3_3", - "CMT_TOP_WR1END2_9", - "CMT_TOP_CTRL0_6", - "CMT_TOP_FAN2_2", - "CMT_TOP_NW4END1_2", - "CMT_TOP_IMUX18_7", - "CMT_TOP_WL1END2_14", - "CMT_TOP_OCLK_10", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LH2_11", - "CMT_TOP_IMUX40_15", - "CMT_TOP_BLOCK_OUTS_L_B1_13", - "CMT_TOP_NW4A1_0", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_NW4END2_15", - "CMT_TOP_FAN6_13", - "CMT_TOP_IMUX35_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4END3_3", - "CMT_TOP_BYP7_9", - "CMT_TOP_SW4END1_6", - "CMT_LR_LOWER_B_MMCM_DI8", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_IMUX7_15", - "CMT_TOP_EE2A0_15", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4C0_8", - "CMT_TOP_SE4C0_1", - "CMT_TOP_EE2A0_1", - "CMT_TOP_NW2A1_8", - "CMT_TOP_BLOCK_OUTS_L_B2_15", - "CMT_TOP_SW4END0_15", - "CMT_TOP_LH9_4", - "CMT_TOP_SW4END1_1", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_IMUX37_15", - "CMT_LR_LOWER_B_MMCM_DO6", - "CMT_TOP_LH10_8", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WW2END3_3", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_FAN1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_SE4C1_2", - "CMT_TOP_NW2A2_6", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX46_8", - "CMT_TOP_EE4B1_7", - "CMT_LR_LOWER_B_MMCM_TESTIN17", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_EE4B0_5", - "CMT_TOP_MONITOR_N_15", - "CMT_TOP_NE4C0_14", - "CMT_TOP_NW2A0_3", - "CMT_TOP_WW2A3_15", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_SE4BEG0_14", - "CMT_TOP_WW4B2_7", - "CMT_TOP_LH10_11", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_IMUX6_2", - "CMT_TOP_NE4C2_6", - "CMT_TOP_WW4END2_9", - "CMT_TOP_IMUX13_10", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_LR_LOWER_B_MMCM_TESTOUT1", - "CMT_TOP_WW2END3_11", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_LH9_13", - "CMT_TOP_LH8_8", - "CMT_TOP_LOGIC_OUTS_L_B20_15", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW4A2_2", - "MMCM_CLK_FREQ_BB_REBUF0_NS", - "CMT_TOP_WW2A1_6", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_IMUX36_14", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_ICLK_15", - "CMT_TOP_SW2A0_11", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_IMUX3_8", - "CMT_TOP_BYP3_15", - "CMT_TOP_NW4END2_13", - "CMT_TOP_FAN6_9", - "CMT_TOP_SE4C1_3", - "CMT_TOP_WL1END2_6", - "CMT_TOP_LH11_2", - "CMT_TOP_WW4C0_9", - "CMT_TOP_LH3_14", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_IMUX3_13", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_IMUX12_1", - "CMT_TOP_SE2A0_1", - "CMT_TOP_IMUX46_11", - "CMT_TOP_WW4A1_13", - "CMT_TOP_IMUX37_4", - "CMT_TOP_EE4C3_10", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B9_13", - "CMT_TOP_LOGIC_OUTS_L_B4_13", - "CMT_TOP_EL1BEG0_13", - "CMT_TOP_NE2A0_14", - "CMT_TOP_NE4C1_3", - "CMT_TOP_IMUX11_15", - "CMT_TOP_FAN5_4", - "CMT_TOP_SE4BEG0_13", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_NW4END3_12", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX0_4", - "CMT_TOP_NW4A3_12", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_LH1_12", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_IMUX27_13", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_IMUX40_9", - "CMT_TOP_NW4A3_13", - "CMT_TOP_SW2A1_7", - "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "CMT_TOP_WL1END1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_WL1END1_9", - "CMT_TOP_WW4B1_15", - "CMT_TOP_WW4C1_15", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_SE2A2_5", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_SW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LH2_4", - "CMT_TOP_WW4A0_14", - "CMT_TOP_WW2END3_14", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_WW4END0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_ER1BEG3_13", - "CMT_TOP_SE2A3_9", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX7_10", - "CMT_TOP_WW4A1_8", - "CMT_TOP_ICLKDIV_14", - "CMT_TOP_WW4END3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_15", - "CMT_TOP_SE2A3_10", - "CMT_TOP_WW2A3_7", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_WW4B0_1", - "CMT_TOP_IMUX15_13", - "CMT_TOP_WW4END2_6", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_NE2A1_11", - "CMT_TOP_LOGIC_OUTS_L_B7_13", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_SE4BEG3_5", - "CMT_L_LOWER_B_CLK_MMCM6", - "CMT_TOP_NW2A0_11", - "CMT_TOP_IMUX42_2", - "CMT_TOP_LH8_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_EE4A0_5", - "CMT_TOP_WW4A3_14", - "CMT_TOP_WL1END2_3", - "CMT_TOP_SE2A1_8", - "CMT_TOP_FAN4_14", - "CMT_TOP_NE4C1_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_NW2A0_6", - "CMT_TOP_WW4A3_8", - "CMT_TOP_SW2A1_3", - "CMT_TOP_IMUX40_5", - "CMT_TOP_SE2A1_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_CTRL1_5", - "CMT_TOP_SE4C3_1", - "CMT_TOP_IMUX13_4", - "CMT_TOP_EE2A1_1", - "CMT_TOP_IMUX18_3", - "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", - "CMT_TOP_EL1BEG2_14", - "CMT_LR_LOWER_B_MMCM_TESTIN1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_IMUX16_5", - "CMT_TOP_LH9_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_LOGIC_OUTS_L_B3_15", - "CMT_TOP_EE2A1_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_WL1END3_7", - "CMT_MMCM_PHASERA_DQSBUS0", - "CMT_TOP_EE4A3_12", - "CMT_TOP_BYP5_8", - "CMT_TOP_IMUX47_3", - "CMT_TOP_NE2A2_7", - "CMT_TOP_WW4B1_5", - "CMT_TOP_SE4C3_9", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END3_12", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_EE2A2_0", - "CMT_TOP_IMUX4_12", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_LH9_7", - "CMT_TOP_NE2A0_15", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW2END3_5", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CLK1_9", - "CMT_TOP_EE4A2_14", - "CMT_TOP_WW2A0_13", - "CMT_TOP_IMUX5_11", - "CMT_TOP_WR1END2_6", - "CMT_TOP_CTRL1_2", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_NW2A1_12", - "CMT_TOP_IMUX10_11", - "CMT_TOP_LH6_6", - "CMT_TOP_WW4C0_13", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_SE2A3_12", - "CMT_TOP_EE2A3_1", - "CMT_TOP_IMUX2_0", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_IMUX28_12", - "CMT_TOP_EE4B3_5", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX38_2", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_NE2A0_12", - "CMT_TOP_FAN4_10", - "CMT_TOP_CLK0_5", - "CMT_TOP_SW4A3_0", - "CMT_TOP_IMUX18_13", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_OCLK_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "CMT_TOP_LH12_6", - "CMT_TOP_IMUX4_6", - "CMT_LR_LOWER_B_MMCM_TESTIN21", - "CMT_TOP_WR1END2_3", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_WR1END1_14", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX4_11", - "CMT_TOP_NW2A2_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_SE4C1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_14", - "CMT_TOP_WW4C0_4", - "CMT_TOP_IMUX6_8", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_WW4A2_4", - "CMT_TOP_IMUX7_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_SE4C2_15", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SW4A3_9", - "CMT_TOP_IMUX20_7", - "CMT_TOP_FAN0_13", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_IMUX35_7", - "CMT_TOP_EE4A3_5", - "CMT_TOP_LH6_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_NE4BEG3_15", - "CMT_TOP_ICLK_8", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_IMUX44_12", - "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "CMT_TOP_NW2A3_9", - "CMT_TOP_LOGIC_OUTS_L_B8_15", - "CMT_TOP_CLK0_8", - "CMT_TOP_IMUX7_2", - "CMT_TOP_SE2A2_11", - "CMT_TOP_FAN4_2", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BYP5_13", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_LH12_3", - "CMT_TOP_WW2A1_8", - "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "CMT_TOP_NE4C2_12", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LH9_14", - "CMT_TOP_NE4BEG1_14", - "CMT_TOP_LH8_2", - "CMT_MMCM_PHYCTRL_SYNC_BB_DN", - "CMT_TOP_EE2BEG3_7", - "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_IMUX23_7", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_SE4C0_14", - "CMT_TOP_IMUX39_0", - "CMT_TOP_NE2A2_14", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX33_8", - "CMT_TOP_SW2A2_2", - "CMT_TOP_LH10_0", - "CMT_TOP_IMUX46_15", - "CMT_TOP_LH6_3", - "CMT_TOP_EE2A0_0", - "CMT_TOP_IMUX12_0", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_NW4A1_1", - "CMT_TOP_SE4BEG3_14", - "CMT_TOP_IMUX21_8", - "CMT_TOP_LH2_14", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX10_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE2A2_14", - "CMT_TOP_FAN2_10", - "CMT_TOP_NE4BEG2_15", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_LH9_12", - "CMT_TOP_IMUX5_12", - "CMT_TOP_LH12_11", - "CMT_TOP_IMUX36_10", - "CMT_TOP_LH4_1", - "CMT_TOP_SE4C3_12", - "CMT_TOP_NE4C2_11", - "CMT_TOP_IMUX3_3", - "CMT_TOP_CTRL0_15", - "CMT_TOP_BYP1_1", - "CMT_TOP_LOGIC_OUTS_L_B0_13", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_SW4END1_5", - "CMT_TOP_FAN7_0", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW4END2_14", - "CMT_TOP_LH1_7", - "CMT_TOP_IMUX35_12", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_WW4A0_4", - "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "CMT_TOP_NW4A2_14", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW2A1_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_FAN0_15", - "CMT_TOP_WW4C2_0", - "CMT_TOP_SE2A3_3", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_WL1END2_4", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_IMUX9_0", - "CMT_TOP_NW4A0_12", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LH5_0", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_WW2END0_13", - "CMT_TOP_IMUX9_13", - "CMT_TOP_IMUX22_5", - "CMT_TOP_FAN2_15", - "CMT_TOP_WW4END0_15", - "CMT_TOP_NE2A3_12", - "CMT_TOP_SW4END3_13", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE2A2_12", - "CMT_TOP_EL1BEG2_13", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_IMUX11_1", - "CMT_TOP_EE4B0_15", - "CMT_TOP_NE2A3_8", - "CMT_TOP_BLOCK_OUTS_L_B1_15", - "CMT_TOP_EE2A3_0", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_BLOCK_OUTS_L_B0_14", - "CMT_TOP_WL1END0_15", - "CMT_TOP_LH4_6", - "CMT_TOP_WW4A3_9", - "CMT_TOP_FAN7_7", - "CMT_TOP_SE2A1_4", - "CMT_TOP_CTRL0_13", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "MMCMOUT_CLK_FREQ_BB_3", - "CMT_TOP_SE4C0_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_LH5_3", - "CMT_TOP_BYP0_13", - "CMT_TOP_SW2A3_10", - "CMT_TOP_OCLK1X_90_14", - "CMT_TOP_WW4END2_11", - "CMT_TOP_IMUX26_14", - "CMT_TOP_NE4BEG1_15", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_IMUX25_1", - "CMT_TOP_ICLK_9", - "CMT_LR_LOWER_B_MMCM_LOCKED", - "CMT_TOP_IMUX14_13", - "CMT_TOP_IMUX31_8", - "CMT_TOP_WL1END0_13", - "CMT_TOP_LH3_2", - "CMT_TOP_IMUX25_15", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_L_LOWER_B_CLK_FREQ_BB3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4END2_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_CLK1_13", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_BYP4_13", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_BYP1_7", - "CMT_TOP_LH3_10", - "CMT_TOP_WL1END2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_WL1END3_5", - "CMT_TOP_ICLK_3", - "CMT_TOP_IMUX0_5", - "CMT_TOP_SW4A0_8", - "CMT_TOP_FAN7_6", - "CMT_TOP_IMUX4_0", - "CMT_TOP_BYP1_10", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX20_12", - "CMT_TOP_SW4A2_15", - "CMT_LR_LOWER_B_MMCM_DI14", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_IMUX19_4", - "CMT_TOP_WW4B1_8", - "CMT_TOP_LH4_0", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_EE4A2_10", - "CMT_LR_LOWER_B_MMCM_DADDR0", - "CMT_TOP_IMUX44_7", - "CMT_TOP_EE4B2_4", - "CMT_TOP_BYP7_14", - "CMT_L_LOWER_B_CLK_MMCM4", - "CMT_TOP_LH10_13", - "CMT_L_LOWER_B_CLK_MMCM9", - "CMT_TOP_NW2A2_15", - "CMT_TOP_EE4C3_7", - "CMT_TOP_WL1END1_5", - "CMT_TOP_IMUX42_9", - "CMT_TOP_CTRL0_12", - "CMT_TOP_IMUX3_2", - "CMT_TOP_SE4C0_2", - "CMT_TOP_EE4A3_13", - "CMT_TOP_WW2A1_12", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4C3_13", - "CMT_TOP_SW4END0_12", - "CMT_TOP_NE4C3_13", - "CMT_TOP_LH7_2", - "CMT_TOP_WW4A1_4", - "CMT_TOP_IMUX11_14", - "CMT_TOP_WW4END0_13", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_CLK0_3", - "CMT_TOP_IMUX44_8", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_WW2A3_12", - "CMT_TOP_SE4C2_0", - "CMT_TOP_EE2A2_12", - "CMT_TOP_IMUX23_2", - "CMT_TOP_WW4END3_7", - "CMT_TOP_IMUX14_15", - "CMT_TOP_IMUX34_15", - "CMT_TOP_SW2A2_8", - "CMT_TOP_NW4A0_8", - "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", - "CMT_PHASER_A_ICLK_TOIOI", - "CMT_TOP_WW4END3_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX21_2", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_FAN6_10", - "CMT_TOP_LH11_6", - "CMT_TOP_LOGIC_OUTS_L_B22_14", - "CMT_TOP_CLK1_10", - "CMT_TOP_SE2A3_14", - "CMT_TOP_IMUX45_12", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_SW2A3_2", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX24_15", - "CMT_TOP_WW2A0_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_FAN7_15", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_IMUX33_10", - "CMT_TOP_IMUX37_14", - "CMT_TOP_EE4B3_10", - "CMT_TOP_WW4C1_7", - "CMT_TOP_IMUX24_5", - "CMT_TOP_WW4C2_8", - "CMT_TOP_EE2A3_8", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_L_LOWER_B_CLK_PERF1", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "CMT_TOP_NW4END0_6", - "CMT_TOP_SE2A3_0", - "CMT_TOP_EE4C0_10", - "CMT_TOP_IMUX43_10", - "CMT_TOP_NW2A3_6", - "CMT_TOP_IMUX33_14", - "CMT_TOP_NE2A3_0", - "CMT_TOP_LH12_5", - "CMT_TOP_WW2END1_12", - "CMT_TOP_IMUX35_6", - "CMT_TOP_EE4C2_3", - "CMT_TOP_WW2END0_10", - "CMT_TOP_FAN2_7", - "CMT_TOP_WW4A3_0", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_IMUX31_2", - "CMT_TOP_FAN3_7", - "CMT_TOP_IMUX3_4", - "CMT_TOP_SW4END2_15", - "CMT_TOP_LOGIC_OUTS_L_B5_13", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX12_14", - "CMT_TOP_EE4A1_1", - "CMT_TOP_LOGIC_OUTS_L_B14_14", - "CMT_TOP_SW4A0_5", - "CMT_TOP_EE2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_EE4B1_6", - "CMT_LR_LOWER_B_MMCM_TESTIN7", - "CMT_TOP_NE2A1_13", - "CMT_TOP_WR1END1_10", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2A0_6", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX47_6", - "CMT_TOP_SW4A2_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_CTRL1_6", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_13", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_OCLKDIV_14", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NW4END1_1", - "CMT_TOP_CLK1_5", - "CMT_TOP_WW4C1_0", - "CMT_TOP_EE4B3_3", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_WW4B2_2", - "CMT_TOP_NW4END1_7", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX10_10", - "CMT_TOP_SE4BEG1_14", - "CMT_TOP_WW4B3_6", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_WW2A2_13", - "CMT_LR_LOWER_B_MMCM_DI7", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_WW4A3_5", - "CMT_TOP_LH1_0", - "CMT_TOP_WW4B1_10", - "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_OCLK1X_90_7", - "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LH10_5", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_IMUX15_0", - "CMT_TOP_EE4A1_5", - "CMT_TOP_IMUX41_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "CMT_TOP_NW2A3_12", - "CMT_TOP_EE4C2_9", - "CMT_TOP_SE2A3_1", - "CMT_TOP_BYP0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_IMUX19_13", - "CMT_TOP_LH2_13", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_WR1END0_11", - "CMT_TOP_BLOCK_OUTS_L_B0_13", - "CMT_TOP_IMUX36_13", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX8_5", - "CMT_TOP_WW4C2_9", - "CMT_TOP_CLK1_6", - "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "CMT_TOP_FAN6_11", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX27_12", - "CMT_TOP_NW4END3_9", - "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "CMT_TOP_WR1END3_13", - "CMT_TOP_LOGIC_OUTS_L_B6_15", - "CMT_TOP_WW4A2_3", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX17_3", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B0_14", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LH1_8", - "CMT_TOP_LH11_1", - "CMT_TOP_IMUX3_5", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_EE4BEG3_15", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_FAN4_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_SE4C1_6", - "CMT_TOP_WR1END3_10", - "CMT_LR_LOWER_B_MMCM_CLKOUT0B", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_IMUX15_9", - "CMT_TOP_BYP0_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_LH2_10", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_SE4C1_11", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_IMUX12_13", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SW4A3_2", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_LH8_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_LH5_11", - "CMT_TOP_FAN4_4", - "CMT_TOP_WW4C3_0", - "CMT_TOP_SE4C3_15", - "CMT_TOP_EE4C2_10", - "CMT_TOP_CTRL0_14", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_CLK0_13", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_SW2A1_11", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX35_3", - "CMT_TOP_NE4C2_4", - "CMT_L_LOWER_B_CLK_MMCM12", - "CMT_TOP_NW2A0_13", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_IMUX38_9", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_SE4C2_1", - "CMT_TOP_CTRL0_1", - "CMT_TOP_IMUX2_4", - "CMT_TOP_EE2A0_12", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX16_2", - "CMT_TOP_SW4A1_4", - "CMT_TOP_WW2A3_14", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_NE4C1_11", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_SW2A1_13", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_FAN7_13", - "CMT_TOP_NE2A1_10", - "CMT_TOP_SW4END2_14", - "CMT_TOP_FAN3_11", - "CMT_TOP_EE4C0_14", - "CMT_TOP_IMUX17_5", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_CLK1_12", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_WW4A0_15", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_SW4END1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BYP1_4", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_EE2BEG1_13", - "CMT_TOP_IMUX32_4", - "CMT_TOP_IMUX7_0", - "CMT_TOP_NW4END0_9", - "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX26_4", - "CMT_TOP_SE4C2_14", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_BYP4_3", - "CMT_TOP_WL1END2_10", - "CMT_TOP_FAN5_2", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4C0_9", - "CMT_TOP_IMUX29_3", - "CMT_TOP_EE4C1_7", - "CMT_LR_LOWER_B_MMCM_TESTIN13", - "CMT_TOP_WL1END3_15", - "CMT_TOP_IMUX29_2", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4A2_1", - "CMT_TOP_EE4BEG2_14", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SW4END3_12", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_NW2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_EE4B0_3", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_SW4END2_11", - "CMT_TOP_WW4B2_8", - "CMT_TOP_IMUX47_13", - "CMT_TOP_SW4A2_9", - "CMT_TOP_NW4A2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4END0_9", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_NE2A3_7", - "CMT_TOP_FAN5_1", - "CMT_TOP_LOGIC_OUTS_L_B8_14", - "CMT_TOP_IMUX21_11", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_FAN1_11", - "CMT_TOP_IMUX32_6", - "CMT_TOP_SW4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_IMUX8_10", - "CMT_LR_LOWER_B_MMCM_TESTOUT51", - "CMT_TOP_WW4A2_12", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX24_10", - "CMT_TOP_LH3_7", - "CMT_TOP_WR1END1_7", - "CMT_TOP_NW2A0_5", - "CMT_TOP_EE4B0_11", - "CMT_TOP_BYP3_1", - "CMT_TOP_EL1BEG3_13", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_EE4B1_15", - "CMT_TOP_LH9_2", - "CMT_TOP_WW2A2_4", - "CMT_TOP_SW2A1_14", - "CMT_TOP_BYP5_9", - "CMT_TOP_IMUX41_9", - "CMT_TOP_IMUX40_6", - "CMT_TOP_WL1END3_3", - "CMT_TOP_NW4A3_0", - "CMT_TOP_LH9_8", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX15_15", - "MMCMOUT_CLK_FREQ_BB_2", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_WW4A0_5", - "CMT_TOP_SW2A2_15", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_IMUX12_7", - "CMT_TOP_SW4A0_7", - "CMT_TOP_NW4A0_15", - "CMT_TOP_EE4A0_4", - "CMT_TOP_IMUX7_11", - "CMT_TOP_EE4B3_7", - "CMT_TOP_IMUX4_7", - "CMT_TOP_LOGIC_OUTS_L_B10_13", - "CMT_LR_LOWER_B_MMCM_TESTIN11", - "CMT_TOP_EE4C2_0", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4END1_12", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_SE4C0_0", - "CMT_TOP_WW4A1_0", - "CMT_TOP_LH1_2", - "CMT_TOP_SW4END0_8", - "CMT_TOP_FAN3_5", - "CMT_TOP_MONITOR_P_13", - "CMT_LR_LOWER_B_MMCM_TESTOUT52", - "CMT_TOP_SE2A1_6", - "CMT_TOP_IMUX20_15", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE2A1_14", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_EE4BEG0_8", - "CMT_LR_LOWER_B_MMCM_DO14", - "CMT_TOP_LH11_5", - "CMT_LR_LOWER_B_MMCM_TESTIN15", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_WR1END0_2", - "CMT_TOP_IMUX30_5", - "CMT_TOP_LOGIC_OUTS_L_B16_15", - "CMT_TOP_WW2END1_15", - "CMT_TOP_NW4A3_3", - "CMT_TOP_FAN4_15", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_WW4B3_8", - "CMT_LR_LOWER_B_MMCM_CLKINSEL", - "CMT_TOP_WW2END2_8", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX38_7", - "CMT_TOP_NW2A1_3", - "CMT_L_LOWER_B_CLK_IN1_INT", - "CMT_TOP_EE4A2_5", - "CMT_TOP_NE2A2_0", - "CMT_TOP_WW4C1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_WW4B2_11", - "CMT_TOP_LOGIC_OUTS_L_B13_14", - "CMT_TOP_CLK0_7", - "CMT_TOP_EE2A1_3", - "CMT_TOP_SW4END1_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_FAN7_1", - "CMT_L_LOWER_B_CLK_FREQ_BB0", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LH11_3", - "CMT_TOP_IMUX13_3", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_LH10_10", - "CMT_TOP_SW4A1_10", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NE4C0_6", - "CMT_TOP_BYP0_3", - "CMT_TOP_SE4C2_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_IMUX5_7", - "CMT_TOP_LH10_4", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX8_4", - "CMT_L_LOWER_B_CLK_PERF0", - "CMT_TOP_WL1END0_9", - "CMT_TOP_EE4C0_15", - "CMT_TOP_SW2A1_6", - "CMT_TOP_IMUX26_3", - "CMT_TOP_NW2A2_0", - "CMT_TOP_WW4END0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_SW4A0_12", - "CMT_TOP_EE4C1_14", - "CMT_TOP_IMUX14_14", - "CMT_TOP_SE4C1_14", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WR1END2_2", - "CMT_TOP_SE4C2_12", - "CMT_TOP_IMUX37_13", - "CMT_TOP_LH7_13", - "CMT_TOP_WW4C1_1", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_WW2A1_5", - "CMT_TOP_CTRL1_1", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_LR_LOWER_B_MMCM_TESTIN3", - "CMT_TOP_BYP7_3", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END2_13", - "CMT_TOP_IMUX45_0", - "CMT_TOP_WL1END1_7", - "CMT_TOP_LH2_7", - "CMT_TOP_WW4B0_15", - "CMT_TOP_WW4END1_2", - "CMT_TOP_LH7_7", - "CMT_TOP_IMUX26_8", - "CMT_LR_LOWER_B_MMCM_TESTIN9", - "CMT_TOP_BYP4_12", - "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "MMCMOUT_CLK_FREQ_BB_0", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_SE4C2_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_EE4A2_11", - "CMT_TOP_NW4END1_4", - "CMT_TOP_IMUX25_11", - "CMT_TOP_SW2A3_15", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_IMUX35_13", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_NW2A1_6", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_BYP2_4", - "CMT_TOP_NW4END2_3", - "CMT_TOP_WL1END0_11", - "CMT_TOP_EE4C2_15", - "CMT_TOP_IMUX18_10", - "CMT_LR_LOWER_B_MMCM_DO0", - "CMT_TOP_EE4C1_8", - "CMT_TOP_BYP2_14", - "CMT_TOP_WW2END1_4", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_SE2A2_15", - "CMT_TOP_WW2END3_9", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_NW4A0_13", - "CMT_TOP_EE4C2_4", - "CMT_LR_LOWER_B_MMCM_TESTIN25", - "CMT_TOP_WR1END2_15", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_IMUX1_9", - "CMT_LR_LOWER_B_MMCM_TESTIN29", - "CMT_TOP_NW4A1_4", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_SW2A0_3", - "CMT_TOP_IMUX22_6", - "CMT_TOP_EE4C2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_14", - "CMT_TOP_IMUX5_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_EE4C3_1", - "CMT_TOP_NE2A2_4", - "CMT_TOP_LH9_6", - "CMT_TOP_IMUX28_5", - "CMT_TOP_EE2A2_9", - "CMT_TOP_LH6_15", - "CMT_TOP_IMUX3_15", - "CMT_TOP_LOGIC_OUTS_L_B12_13", - "CMT_TOP_NW4A3_4", - "CMT_TOP_SW2A2_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LH2_9", - "CMT_TOP_WW2A2_2", - "CMT_TOP_IMUX3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_LR_LOWER_B_MMCM_PSEN", - "CMT_TOP_NW4A3_14", - "CMT_TOP_EE2A1_13", - "CMT_TOP_ER1BEG0_14", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_NW4END0_15", - "CMT_TOP_IMUX10_14", - "CMT_TOP_IMUX45_11", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX45_5", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_NW4END1_12", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_WW4C3_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX24_6", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_IMUX35_5", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_EE2A0_7", - "CMT_TOP_WW4B2_4", - "CMT_TOP_FAN2_8", - "CMT_TOP_EE4BEG2_15", - "CMT_TOP_EE4B0_14", - "CMT_TOP_SW2A1_0", - "CMT_TOP_WW2END2_15", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_IMUX30_13", - "CMT_TOP_WL1END0_5", - "CMT_LR_LOWER_B_MMCM_TESTIN4", - "CMT_TOP_CLK0_9", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX29_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT57", - "CMT_TOP_NE2A0_11", - "CMT_TOP_FAN2_3", - "CMT_TOP_NE4C2_1", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_IMUX31_5", - "CMT_TOP_WR1END1_5", - "CMT_TOP_CTRL1_7", - "CMT_TOP_IMUX8_7", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_IMUX27_9", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4C3_8", - "CMT_TOP_BYP6_6", - "CMT_TOP_IMUX34_13", - "CMT_TOP_SW2A2_14", - "CMT_TOP_EE4C1_4", - "CMT_TOP_IMUX46_6", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4END0_7", - "CMT_TOP_SW4A1_12", - "CMT_TOP_CLK1_11", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_BYP3_8", - "CMT_TOP_WW4END2_12", - "CMT_TOP_IMUX16_8", - "CMT_TOP_SW4END3_7", - "CMT_TOP_WW2A1_4", - "CMT_TOP_EE4B3_13", - "CMT_TOP_SW4END3_15", - "CMT_TOP_LH2_12", - "CMT_TOP_WW2END3_0", - "CMT_TOP_SE2A0_5", - "CMT_TOP_WW2A1_0", - "CMT_TOP_NW4A2_5", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_LH7_15", - "CMT_TOP_WW4END2_1", - "CMT_TOP_NW2A2_5", - "CMT_TOP_IMUX43_14", - "CMT_TOP_WW4B2_13", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_IMUX18_9", - "CMT_TOP_SE2A0_4", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_IMUX6_5", - "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_EE4A2_8", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX5_13", - "CMT_TOP_CTRL0_9", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_WR1END1_13", - "CMT_TOP_IMUX6_11", - "CMT_TOP_LH5_12", - "CMT_TOP_BYP6_15", - "CMT_TOP_WW4B3_2", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_EE4C0_4", - "CMT_TOP_BYP2_1", - "CMT_TOP_IMUX36_8", - "CMT_TOP_EL1BEG3_0", - "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "CMT_TOP_NW2A3_5", - "CMT_TOP_IMUX7_13", - "CMT_TOP_IMUX8_13", - "CMT_TOP_IMUX27_3", - "CMT_TOP_BYP0_15", - "CMT_TOP_LH7_11", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_WW4C2_2", - "CMT_LR_LOWER_B_MMCM_DO11", - "CMT_TOP_BYP1_6", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_EE4C2_14", - "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "CMT_TOP_WW2A1_15", - "CMT_TOP_SE2A0_10", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_NW4END0_10", - "CMT_TOP_EE2A3_13", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_IMUX8_8", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX2_9", - "CMT_TOP_SE2A2_1", - "CMT_TOP_EE4BEG2_6", - "CMT_LR_LOWER_B_MMCM_TESTIN12", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_NE4C2_10", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_IMUX13_0", - "CMT_TOP_EE4A2_9", - "CMT_TOP_IMUX3_9", - "CMT_TOP_WW2A3_2", - "CMT_TOP_EL1BEG0_15", - "CMT_TOP_BYP5_0", - "CMT_TOP_NE4C2_8", - "CMT_TOP_BLOCK_OUTS_L_B1_12", - "CMT_TOP_IMUX40_3", - "CMT_LR_LOWER_B_MMCM_TESTIN5", - "CMT_TOP_IMUX17_9", - "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "CMT_L_LOWER_B_CLK_MMCM1", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_IMUX0_8", - "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "CMT_TOP_LOGIC_OUTS_L_B16_13", - "CMT_TOP_NE4C3_5", - "CMT_TOP_WR1END3_9", - "CMT_TOP_EE4C3_9", - "CMT_TOP_IMUX35_8", - "CMT_TOP_EE4BEG2_13", - "CMT_TOP_BYP3_5", - "CMT_TOP_IMUX32_8", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_IMUX10_15", - "CMT_TOP_EE2BEG2_14", - "CMT_LR_LOWER_B_MMCM_TESTIN16", - "CMT_TOP_WW2END0_12", - "CMT_TOP_NE4BEG3_13", - "CMT_TOP_NW4A0_11", - "CMT_TOP_IMUX34_9", - "CMT_TOP_SE4C3_5", - "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "CMT_TOP_IMUX25_4", - "CMT_TOP_WW4B0_14", - "CMT_TOP_IMUX47_11", - "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_NE4BEG2_11", - "MMCM_CLK_FREQ_BB_REBUF1_NS", - "CMT_TOP_FAN6_4", - "CMT_TOP_IMUX21_7", - "CMT_TOP_WW2END0_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_EL1BEG1_13", - "CMT_TOP_LH5_2", - "CMT_TOP_IMUX17_4", - "CMT_TOP_SW2A1_8", - "CMT_TOP_LOGIC_OUTS_L_B9_14", - "CMT_TOP_LOGIC_OUTS_L_B2_15", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_NE4C1_9", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_LH3_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_WW2END0_4", - "CMT_TOP_EE2A1_7", - "CMT_TOP_NW2A2_11", - "CMT_TOP_WW2END3_6", - "CMT_MMCM_A_WRCLK_TOFIFO", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_SE4C3_13", - "CMT_TOP_NE2A3_13", - "CMT_TOP_LOGIC_OUTS_L_B15_13", - "CMT_TOP_WW4B0_11", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_WW2END2_12", - "CMT_TOP_LOGIC_OUTS_L_B18_13", - "CMT_MMCM_PHASER_IN_B_ICLK", - "CMT_TOP_IMUX8_12", - "CMT_TOP_SW2A3_9", - "CMT_TOP_LOGIC_OUTS_L_B15_14", - "CMT_TOP_FAN2_13", - "CMT_TOP_IMUX26_13", - "CMT_TOP_BYP6_14", - "CMT_TOP_EE4C3_14", - "CMT_TOP_IMUX32_9", - "CMT_TOP_LOGIC_OUTS_L_B8_13", - "CMT_TOP_EE2A0_2", - "CMT_TOP_SW4END2_6", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_IMUX47_1", - "CMT_TOP_WW4END2_13", - "CMT_TOP_WW2A2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_13", - "CMT_TOP_NW2A1_7", - "CMT_TOP_IMUX14_0", - "CMT_TOP_LH7_4", - "CMT_TOP_EE4C0_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX45_3", - "CMT_TOP_SW4END3_11", - "CMT_TOP_WW4C1_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_IMUX42_8", - "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX33_7", - "CMT_TOP_SE2A1_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT54", - "CMT_L_LOWER_B_CLK_IN2_HCLK", - "CMT_TOP_NW2A1_13", - "CMT_PHASER_A_ICLKDIV_TOIOI", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "CMT_TOP_SE4BEG0_15", - "CMT_TOP_FAN4_11", - "CMT_TOP_LH5_4", - "CMT_TOP_CLK0_4", - "CMT_TOP_OCLK_9", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX23_13", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_WW4A3_4", - "CMT_TOP_LH2_15", - "CMT_TOP_NW4A1_6", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SW4END2_13", - "CMT_TOP_IMUX41_12", - "CMT_TOP_SW4A3_4", - "CMT_TOP_NE2A0_10", - "CMT_LR_LOWER_B_MMCM_DCLK", - "CMT_TOP_OCLK1X_90_4", - "CMT_LR_LOWER_B_MMCM_TESTIN10", - "CMT_TOP_LH8_7", - "CMT_TOP_IMUX32_5", - "CMT_TOP_SW2A1_5", - "CMT_TOP_WR1END0_1", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_LOGIC_OUTS_L_B13_10" - ], - "sites": [ - { - "prefix": "MMCME2_ADV", - "y_coord": 0, - "type": "MMCME2_ADV", - "site_pins": { - "TESTOUT33": "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "TESTOUT45": "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "TESTOUT41": "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "TESTOUT48": "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "DI10": "CMT_LR_LOWER_B_MMCM_DI10", - "TESTOUT8": "CMT_LR_LOWER_B_MMCM_TESTOUT8", - "DO8": "CMT_LR_LOWER_B_MMCM_DO8", - "TESTOUT10": "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "DADDR0": "CMT_LR_LOWER_B_MMCM_DADDR0", - "TESTIN16": "CMT_LR_LOWER_B_MMCM_TESTIN16", - "TESTIN14": "CMT_LR_LOWER_B_MMCM_TESTIN14", - "TESTOUT29": "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "TESTIN7": "CMT_LR_LOWER_B_MMCM_TESTIN7", - "TESTOUT14": "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "TESTIN23": "CMT_LR_LOWER_B_MMCM_TESTIN23", - "TESTOUT3": "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "DADDR5": "CMT_LR_LOWER_B_MMCM_DADDR5", - "TESTIN28": "CMT_LR_LOWER_B_MMCM_TESTIN28", - "TESTOUT24": "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "CLKOUT1B": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "DO15": "CMT_LR_LOWER_B_MMCM_DO15", - "TESTOUT62": "CMT_LR_LOWER_B_MMCM_TESTOUT62", - "TESTIN1": "CMT_LR_LOWER_B_MMCM_TESTIN1", - "DI8": "CMT_LR_LOWER_B_MMCM_DI8", - "DI13": "CMT_LR_LOWER_B_MMCM_DI13", - "CLKINSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", - "TESTIN15": "CMT_LR_LOWER_B_MMCM_TESTIN15", - "TESTOUT7": "CMT_LR_LOWER_B_MMCM_TESTOUT7", - "DI1": "CMT_LR_LOWER_B_MMCM_DI1", - "PSEN": "CMT_LR_LOWER_B_MMCM_PSEN", - "TESTIN12": "CMT_LR_LOWER_B_MMCM_TESTIN12", - "TESTOUT25": "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "DI3": "CMT_LR_LOWER_B_MMCM_DI3", - "TESTOUT31": "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "DI9": "CMT_LR_LOWER_B_MMCM_DI9", - "TESTOUT44": "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "TESTOUT63": "CMT_LR_LOWER_B_MMCM_TESTOUT63", - "DO4": "CMT_LR_LOWER_B_MMCM_DO4", - "TESTOUT21": "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "DO10": "CMT_LR_LOWER_B_MMCM_DO10", - "TESTOUT57": "CMT_LR_LOWER_B_MMCM_TESTOUT57", - "CLKFBSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", - "TESTIN10": "CMT_LR_LOWER_B_MMCM_TESTIN10", - "DO11": "CMT_LR_LOWER_B_MMCM_DO11", - "DI11": "CMT_LR_LOWER_B_MMCM_DI11", - "TESTOUT15": "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "TESTOUT40": "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "CLKOUT1": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "TESTIN8": "CMT_LR_LOWER_B_MMCM_TESTIN8", - "DO6": "CMT_LR_LOWER_B_MMCM_DO6", - "TESTOUT60": "CMT_LR_LOWER_B_MMCM_TESTOUT60", - "TESTOUT20": "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "DI14": "CMT_LR_LOWER_B_MMCM_DI14", - "TESTOUT27": "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "DEN": "CMT_LR_LOWER_B_MMCM_DEN", - "DADDR6": "CMT_LR_LOWER_B_MMCM_DADDR6", - "DADDR4": "CMT_LR_LOWER_B_MMCM_DADDR4", - "DADDR1": "CMT_LR_LOWER_B_MMCM_DADDR1", - "TESTIN20": "CMT_LR_LOWER_B_MMCM_TESTIN20", - "DO7": "CMT_LR_LOWER_B_MMCM_DO7", - "TESTIN9": "CMT_LR_LOWER_B_MMCM_TESTIN9", - "PSDONE": "CMT_LR_LOWER_B_MMCM_PSDONE", - "TESTIN19": "CMT_LR_LOWER_B_MMCM_TESTIN19", - "TESTIN27": "CMT_LR_LOWER_B_MMCM_TESTIN27", - "DI0": "CMT_LR_LOWER_B_MMCM_DI0", - "CLKOUT6": "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "TESTOUT28": "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "TESTIN30": "CMT_LR_LOWER_B_MMCM_TESTIN30", - "TESTOUT6": "CMT_LR_LOWER_B_MMCM_TESTOUT6", - "TMUXOUT": "CMT_LR_LOWER_B_MMCM_TMUXOUT", - "TESTOUT42": "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "TESTIN17": "CMT_LR_LOWER_B_MMCM_TESTIN17", - "DO3": "CMT_LR_LOWER_B_MMCM_DO3", - "CLKOUT2": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "CLKOUT0": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "TESTOUT52": "CMT_LR_LOWER_B_MMCM_TESTOUT52", - "DI2": "CMT_LR_LOWER_B_MMCM_DI2", - "TESTOUT9": "CMT_LR_LOWER_B_MMCM_TESTOUT9", - "DRDY": "CMT_LR_LOWER_B_MMCM_DRDY", - "TESTOUT51": "CMT_LR_LOWER_B_MMCM_TESTOUT51", - "DCLK": "CMT_LR_LOWER_B_MMCM_DCLK", - "RST": "CMT_LR_LOWER_B_MMCM_RST", - "DI7": "CMT_LR_LOWER_B_MMCM_DI7", - "DO0": "CMT_LR_LOWER_B_MMCM_DO0", - "PWRDWN": "CMT_LR_LOWER_B_MMCM_PWRDWN", - "TESTOUT61": "CMT_LR_LOWER_B_MMCM_TESTOUT61", - "CLKINSEL": "CMT_LR_LOWER_B_MMCM_CLKINSEL", - "TESTOUT19": "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "TESTOUT23": "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "CLKIN1": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "TESTOUT30": "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "TESTOUT18": "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "DI15": "CMT_LR_LOWER_B_MMCM_DI15", - "TESTIN6": "CMT_LR_LOWER_B_MMCM_TESTIN6", - "TESTIN11": "CMT_LR_LOWER_B_MMCM_TESTIN11", - "TESTIN4": "CMT_LR_LOWER_B_MMCM_TESTIN4", - "PSCLK": "CMT_LR_LOWER_B_MMCM_PSCLK", - "TESTOUT50": "CMT_LR_LOWER_B_MMCM_TESTOUT50", - "DI12": "CMT_LR_LOWER_B_MMCM_DI12", - "DO1": "CMT_LR_LOWER_B_MMCM_DO1", - "DO5": "CMT_LR_LOWER_B_MMCM_DO5", - "CLKOUT3B": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "TESTOUT16": "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "TESTOUT22": "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "TESTIN31": "CMT_LR_LOWER_B_MMCM_TESTIN31", - "CLKOUT4": "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "DO2": "CMT_LR_LOWER_B_MMCM_DO2", - "TESTOUT59": "CMT_LR_LOWER_B_MMCM_TESTOUT59", - "TESTIN5": "CMT_LR_LOWER_B_MMCM_TESTIN5", - "TESTOUT11": "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "TESTOUT58": "CMT_LR_LOWER_B_MMCM_TESTOUT58", - "DWE": "CMT_LR_LOWER_B_MMCM_DWE", - "TESTOUT37": "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "DI5": "CMT_LR_LOWER_B_MMCM_DI5", - "TESTIN18": "CMT_LR_LOWER_B_MMCM_TESTIN18", - "CLKFBIN": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "CLKFBOUT": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "DI6": "CMT_LR_LOWER_B_MMCM_DI6", - "TESTOUT26": "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "TESTOUT35": "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "TESTOUT32": "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "TESTOUT0": "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "TESTIN25": "CMT_LR_LOWER_B_MMCM_TESTIN25", - "DO12": "CMT_LR_LOWER_B_MMCM_DO12", - "TESTOUT53": "CMT_LR_LOWER_B_MMCM_TESTOUT53", - "TESTIN21": "CMT_LR_LOWER_B_MMCM_TESTIN21", - "CLKOUT0B": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", - "TESTOUT39": "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "DO14": "CMT_LR_LOWER_B_MMCM_DO14", - "TESTOUT46": "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "CLKIN2": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "CLKOUT2B": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "TESTOUT4": "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "TESTOUT55": "CMT_LR_LOWER_B_MMCM_TESTOUT55", - "TESTOUT47": "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "TESTOUT43": "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "TESTOUT36": "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "TESTIN2": "CMT_LR_LOWER_B_MMCM_TESTIN2", - "DADDR2": "CMT_LR_LOWER_B_MMCM_DADDR2", - "TESTOUT54": "CMT_LR_LOWER_B_MMCM_TESTOUT54", - "CLKOUT5": "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "TESTIN24": "CMT_LR_LOWER_B_MMCM_TESTIN24", - "TESTIN29": "CMT_LR_LOWER_B_MMCM_TESTIN29", - "TESTOUT38": "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "LOCKED": "CMT_LR_LOWER_B_MMCM_LOCKED", - "TESTOUT56": "CMT_LR_LOWER_B_MMCM_TESTOUT56", - "PSINCDEC": "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "CLKOUT3": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "TESTIN0": "CMT_LR_LOWER_B_MMCM_TESTIN0", - "TESTIN13": "CMT_LR_LOWER_B_MMCM_TESTIN13", - "TESTIN26": "CMT_LR_LOWER_B_MMCM_TESTIN26", - "TESTOUT2": "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "DO9": "CMT_LR_LOWER_B_MMCM_DO9", - "TESTOUT34": "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "DI4": "CMT_LR_LOWER_B_MMCM_DI4", - "TESTOUT49": "CMT_LR_LOWER_B_MMCM_TESTOUT49", - "TESTIN3": "CMT_LR_LOWER_B_MMCM_TESTIN3", - "TESTIN22": "CMT_LR_LOWER_B_MMCM_TESTIN22", - "TESTOUT17": "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "TESTOUT5": "CMT_LR_LOWER_B_MMCM_TESTOUT5", - "TESTOUT13": "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "DO13": "CMT_LR_LOWER_B_MMCM_DO13", - "TESTOUT12": "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "CLKFBOUTB": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", - "DADDR3": "CMT_LR_LOWER_B_MMCM_DADDR3", - "TESTOUT1": "CMT_LR_LOWER_B_MMCM_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_15": { + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF1": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_15", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_INT->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_IN1_INT", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_8", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX6_0->>CMT_LR_LOWER_B_MMCM_DI12": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI12", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX6_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_TMUXOUT->>CMT_L_LOWER_B_CLK_MMCM13": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM13", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_TMUXOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", - "is_directional": "1", "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3->>CMT_L_LOWER_B_CLK_FREQ_BB0": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", "is_directional": "1", - "src_wire": "MMCM_CLK_FREQ_BB_NS3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSDONE->>CMT_TOP_LOGIC_OUTS_L_B21_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_PSDONE", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1->>CMT_L_LOWER_B_CLK_FREQ_BB2": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", - "is_directional": "1", - "src_wire": "MMCM_CLK_FREQ_BB_NS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX47_1->>CMT_LR_LOWER_B_MMCM_PWRDWN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_PWRDWN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX22_1->>CMT_LR_LOWER_B_MMCM_DWE": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DWE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX22_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUTB->>CMT_L_LOWER_B_CLK_MMCM12": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM12", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO14->>CMT_TOP_LOGIC_OUTS_L_B7_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO14", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX5_0->>CMT_LR_LOWER_B_MMCM_DI10": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI10", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX5_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX32_0->>CMT_LR_LOWER_B_MMCM_DI1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_INT->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_IN3_INT", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX4_0->>CMT_LR_LOWER_B_MMCM_DI8": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX4_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_14": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_14", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_13": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_13", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2->>CMT_L_LOWER_B_CLK_FREQ_BB1": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", - "is_directional": "1", - "src_wire": "MMCM_CLK_FREQ_BB_NS2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX34_0->>CMT_LR_LOWER_B_MMCM_DI5": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO8->>CMT_TOP_LOGIC_OUTS_L_B10_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO8", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>MMCMOUT_CLK_FREQ_BB_0": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_15": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_15", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX0_0->>CMT_LR_LOWER_B_MMCM_DI0": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO2->>CMT_TOP_LOGIC_OUTS_L_B0_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX7_0->>CMT_LR_LOWER_B_MMCM_DI14": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI14", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX7_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO7->>CMT_TOP_LOGIC_OUTS_L_B19_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO3->>CMT_TOP_LOGIC_OUTS_L_B22_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_MMCM0": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_MMCM2": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_MMCM4": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM4", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_IN2_HCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX2_0->>CMT_LR_LOWER_B_MMCM_DI4": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_IN1_HCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK->>CMT_PHASER_A_OCLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT5->>CMT_L_LOWER_B_CLK_MMCM9": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM9", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX38_0->>CMT_LR_LOWER_B_MMCM_DI13": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI13", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX38_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO9->>CMT_TOP_LOGIC_OUTS_L_B16_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO9", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX33_0->>CMT_LR_LOWER_B_MMCM_DI3": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX33_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_MMCM6": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM6", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_LR_LOWER_B_CLKFBOUT2IN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_14": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_14", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_8", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX35_0->>CMT_LR_LOWER_B_MMCM_DI7": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX35_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX15_1->>CMT_LR_LOWER_B_MMCM_DEN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX2_2->>CMT_LR_LOWER_B_MMCM_PSINCDEC": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_CLK1_15->>CMT_L_LOWER_B_CLK_IN2_INT": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_IN2_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK1_15", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO10->>CMT_TOP_LOGIC_OUTS_L_B2_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO10", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX1_0->>CMT_LR_LOWER_B_MMCM_DI2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX1_2->>CMT_LR_LOWER_B_MMCM_PSEN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_PSEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_8", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX34_1->>CMT_LR_LOWER_B_MMCM_DADDR3": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLK->>CMT_PHASER_A_ICLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_A_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO15->>CMT_TOP_LOGIC_OUTS_L_B17_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO15", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO12->>CMT_TOP_LOGIC_OUTS_L_B15_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO12", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DRDY", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_15->>CMT_L_LOWER_B_CLK_IN1_INT": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_IN1_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_15", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1" }, "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_4", - "is_directional": "1", "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_INT->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_IN2_INT", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4" }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLKDIV->>CMT_PHASER_A_ICLKDIV_TOIOI": { + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX7_0->>CMT_LR_LOWER_B_MMCM_DI14": { "can_invert": "0", - "dst_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "src_wire": "CMT_TOP_IMUX7_0", "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_A_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX2_1->>CMT_LR_LOWER_B_MMCM_DADDR2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO4->>CMT_TOP_LOGIC_OUTS_L_B13_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0->>CMT_L_LOWER_B_CLK_FREQ_BB3": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", - "is_directional": "1", - "src_wire": "MMCM_CLK_FREQ_BB_NS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF2": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_14": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_14", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2B->>CMT_L_LOWER_B_CLK_MMCM5": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM5", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_MMCM11": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM11", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>MMCMOUT_CLK_FREQ_BB_3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX0_2->>CMT_LR_LOWER_B_MMCM_CLKINSEL": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKINSEL", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1B->>CMT_L_LOWER_B_CLK_MMCM3": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK1X_90_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK90_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX35_1->>CMT_LR_LOWER_B_MMCM_DADDR5": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX35_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX0_1->>CMT_LR_LOWER_B_MMCM_DADDR0": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_1->>CMT_LR_LOWER_B_MMCM_PSCLK": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_PSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF1_NS<<->>MMCM_CLK_FREQ_BB_NS1": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQ_BB_NS1", - "is_directional": "0", - "src_wire": "MMCM_CLK_FREQ_BB_REBUF1_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI14" }, "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK1X_90->>CMT_PHASER_A_OCLK90_TOIOI": { "can_invert": "0", - "dst_wire": "CMT_PHASER_A_OCLK90_TOIOI", - "is_directional": "1", "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQ_BB_NS0", - "is_directional": "0", - "src_wire": "MMCM_CLK_FREQ_BB_REBUF0_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX36_0->>CMT_LR_LOWER_B_MMCM_DI9": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI9", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX36_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX3_1->>CMT_LR_LOWER_B_MMCM_DADDR4": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B18_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_15": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_15", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX34_2->>CMT_LR_LOWER_B_MMCM_RST": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>MMCMOUT_CLK_FREQ_BB_2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX37_0->>CMT_LR_LOWER_B_MMCM_DI11": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI11", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX37_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF2": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO5->>CMT_TOP_LOGIC_OUTS_L_B23_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_0->>CMT_LR_LOWER_B_MMCM_DCLK": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_14->>CMT_L_LOWER_B_CLK_IN3_INT": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_IN3_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_14", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO11->>CMT_TOP_LOGIC_OUTS_L_B20_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO11", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_13": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_13", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_HCLK->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_IN3_HCLK", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLK90_TOIOI" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO13->>CMT_TOP_LOGIC_OUTS_L_B21_0": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", - "is_directional": "1", "src_wire": "CMT_LR_LOWER_B_MMCM_DO13", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF2": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0" }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLKDIV->>CMT_PHASER_A_OCLKDIV_TOIOI": { + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { "can_invert": "0", - "dst_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>MMCMOUT_CLK_FREQ_BB_1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_15": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_15", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF2": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_13": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_13", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3B->>CMT_L_LOWER_B_CLK_MMCM7": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM7", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF2_NS<<->>MMCM_CLK_FREQ_BB_NS2": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQ_BB_NS2", - "is_directional": "0", - "src_wire": "MMCM_CLK_FREQ_BB_REBUF2_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT6->>CMT_L_LOWER_B_CLK_MMCM10": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM10", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX39_0->>CMT_LR_LOWER_B_MMCM_DI15": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI15", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX39_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHYCTRL_SYNC_BB_DN<<->>CMT_MMCM_PHYCTRL_SYNC_BB_UP": { - "can_invert": "0", - "dst_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_UP", - "is_directional": "0", - "src_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_DN", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX3_0->>CMT_LR_LOWER_B_MMCM_DI6": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B18_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_LOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_12" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX1_1->>CMT_LR_LOWER_B_MMCM_DADDR1": { "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR1", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX1_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_7", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR1" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "can_invert": "0", "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO6->>CMT_TOP_LOGIC_OUTS_L_B5_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_0", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5" }, - "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX44_1->>CMT_LR_LOWER_B_MMCM_DADDR6": { + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT6->>CMT_L_LOWER_B_CLK_MMCM10": { "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR6", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT6", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM10" }, - "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_3": { "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", "is_directional": "1", - "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO0->>CMT_TOP_LOGIC_OUTS_L_B8_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3" }, "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_12", - "is_directional": "1", "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_11", "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_12" }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_0->>CMT_LR_LOWER_B_MMCM_DCLK": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_1", + "src_wire": "CMT_TOP_CLK0_0", "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DCLK" }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT4->>CMT_L_LOWER_B_CLK_MMCM8": { + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_8": { "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM8", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8" }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_8": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_4", - "is_directional": "1", "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0B->>CMT_L_LOWER_B_CLK_MMCM1": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_MMCM1", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_15": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_15" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX36_0->>CMT_LR_LOWER_B_MMCM_DI9": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI9" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO3->>CMT_TOP_LOGIC_OUTS_L_B22_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>MMCMOUT_CLK_FREQ_BB_3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_3" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" }, "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_11": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_11", - "is_directional": "1", "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF2": { - "can_invert": "0", - "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11" }, - "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX37_0->>CMT_LR_LOWER_B_MMCM_DI11": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_5", + "src_wire": "CMT_TOP_IMUX37_0", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI11" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK1_15->>CMT_L_LOWER_B_CLK_IN2_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK1_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_IN2_INT" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_INT->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_IN1_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1->>CMT_L_LOWER_B_CLK_FREQ_BB2": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_NS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_15": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_15" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "can_invert": "0", "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS<<->>MMCM_CLK_FREQ_BB_NS3": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQ_BB_NS3", - "is_directional": "0", - "src_wire": "MMCM_CLK_FREQ_BB_REBUF3_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_13": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_13", "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10" }, - "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_14": { + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_14", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0" }, - "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO1->>CMT_TOP_LOGIC_OUTS_L_B18_0": { + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF0": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>MMCMOUT_CLK_FREQ_BB_2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_2" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX35_1->>CMT_LR_LOWER_B_MMCM_DADDR5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR5" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_MMCM4": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM4" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2B->>CMT_L_LOWER_B_CLK_MMCM5": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM5" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B16_2": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_2", - "is_directional": "1", "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_2" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO7->>CMT_TOP_LOGIC_OUTS_L_B19_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_INT->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_IN2_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_REBUF0_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_14->>CMT_L_LOWER_B_CLK_IN3_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_IN3_INT" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLKDIV->>CMT_PHASER_A_ICLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_ICLKDIV_TOIOI" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK->>CMT_PHASER_A_OCLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLK_TOIOI" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_8": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_8" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX0_0->>CMT_LR_LOWER_B_MMCM_DI0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLKDIV->>CMT_PHASER_A_OCLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLKDIV_TOIOI" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX34_2->>CMT_LR_LOWER_B_MMCM_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_RST" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX47_1->>CMT_LR_LOWER_B_MMCM_PWRDWN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PWRDWN" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_1->>CMT_LR_LOWER_B_MMCM_PSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSCLK" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO12->>CMT_TOP_LOGIC_OUTS_L_B15_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO14->>CMT_TOP_LOGIC_OUTS_L_B7_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUTB->>CMT_L_LOWER_B_CLK_MMCM12": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM12" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_13": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_13" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX4_0->>CMT_LR_LOWER_B_MMCM_DI8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI8" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS<<->>MMCM_CLK_FREQ_BB_NS3": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_REBUF3_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS3" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3->>CMT_L_LOWER_B_CLK_FREQ_BB0": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_NS3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_13": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_13" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF2_NS<<->>MMCM_CLK_FREQ_BB_NS2": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_REBUF2_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS2" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3B->>CMT_L_LOWER_B_CLK_MMCM7": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM7" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO6->>CMT_TOP_LOGIC_OUTS_L_B5_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_14": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_14" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLK->>CMT_PHASER_A_ICLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_A_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_ICLK_TOIOI" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX2_0->>CMT_LR_LOWER_B_MMCM_DI4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI4" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_CLK0_15->>CMT_L_LOWER_B_CLK_IN1_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_IN1_INT" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX1_2->>CMT_LR_LOWER_B_MMCM_PSEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSEN" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX34_1->>CMT_LR_LOWER_B_MMCM_DADDR3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR3" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX3_1->>CMT_LR_LOWER_B_MMCM_DADDR4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR4" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_14": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_14" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_MMCM11": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM11" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX22_1->>CMT_LR_LOWER_B_MMCM_DWE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DWE" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK90_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_8" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_INT->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_IN3_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX0_1->>CMT_LR_LOWER_B_MMCM_DADDR0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_8": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_8" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_14": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_14" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1B->>CMT_L_LOWER_B_CLK_MMCM3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM3" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_13": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_13" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO8->>CMT_TOP_LOGIC_OUTS_L_B10_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX5_0->>CMT_LR_LOWER_B_MMCM_DI10": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI10" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN2_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_IN2_HCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT5->>CMT_L_LOWER_B_CLK_MMCM9": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM9" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>MMCMOUT_CLK_FREQ_BB_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX2_2->>CMT_LR_LOWER_B_MMCM_PSINCDEC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSINCDEC" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_L_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_12" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT4->>CMT_L_LOWER_B_CLK_MMCM8": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM8" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX15_1->>CMT_LR_LOWER_B_MMCM_DEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DEN" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO15->>CMT_TOP_LOGIC_OUTS_L_B17_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO4->>CMT_TOP_LOGIC_OUTS_L_B13_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2->>CMT_L_LOWER_B_CLK_FREQ_BB1": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_NS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX38_0->>CMT_LR_LOWER_B_MMCM_DI13": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI13" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_LR_LOWER_B_CLKFBOUT2IN": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_15": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_15" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX2_1->>CMT_LR_LOWER_B_MMCM_DADDR2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR2" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_13": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_13" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0B->>CMT_L_LOWER_B_CLK_MMCM1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM1" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO11->>CMT_TOP_LOGIC_OUTS_L_B20_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_0" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0->>CMT_L_LOWER_B_CLK_FREQ_BB3": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_NS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO1->>CMT_TOP_LOGIC_OUTS_L_B18_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_0" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHYCTRL_SYNC_BB_DN<<->>CMT_MMCM_PHYCTRL_SYNC_BB_UP": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_DN", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_UP" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_PSDONE->>CMT_TOP_LOGIC_OUTS_L_B21_1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_PSDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX32_0->>CMT_LR_LOWER_B_MMCM_DI1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI1" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_14": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_14" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_8": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_8" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B18_1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_LOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_1" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASERA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_TMUXOUT->>CMT_L_LOWER_B_CLK_MMCM13": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM13" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B18_2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX35_0->>CMT_LR_LOWER_B_MMCM_DI7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI7" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX0_2->>CMT_LR_LOWER_B_MMCM_CLKINSEL": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKINSEL" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX39_0->>CMT_LR_LOWER_B_MMCM_DI15": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI15" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX44_1->>CMT_LR_LOWER_B_MMCM_DADDR6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR6" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO2->>CMT_TOP_LOGIC_OUTS_L_B0_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_MMCM2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM2" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_12" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO0->>CMT_TOP_LOGIC_OUTS_L_B8_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX6_0->>CMT_LR_LOWER_B_MMCM_DI12": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI12" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX33_0->>CMT_LR_LOWER_B_MMCM_DI3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI3" + }, + "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF1_NS<<->>MMCM_CLK_FREQ_BB_NS1": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_REBUF1_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS1" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1" + }, + "CMT_TOP_L_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_15": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_15" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO5->>CMT_TOP_LOGIC_OUTS_L_B23_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_MMCM0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM0" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX3_0->>CMT_LR_LOWER_B_MMCM_DI6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI6" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_MMCM6": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_MMCM6" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF1" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_L_LOWER_B_CLK_PERF0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0" + }, + "CMT_TOP_L_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO10->>CMT_TOP_LOGIC_OUTS_L_B2_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN3_HCLK->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_IN3_HCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_DO9->>CMT_TOP_LOGIC_OUTS_L_B16_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>MMCMOUT_CLK_FREQ_BB_1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_1" + }, + "CMT_TOP_L_LOWER_B.CMT_L_LOWER_B_CLK_IN1_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_L_LOWER_B_CLK_IN1_HCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX1_0->>CMT_LR_LOWER_B_MMCM_DI2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI2" + }, + "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX34_0->>CMT_LR_LOWER_B_MMCM_DI5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI5" } }, - "tile_type": "CMT_TOP_L_LOWER_B" + "wires": [ + "CMT_TOP_LOGIC_OUTS_L_B8_14", + "CMT_TOP_IMUX18_15", + "CMT_TOP_NW4A2_6", + "CMT_TOP_WW2END3_2", + "CMT_TOP_BYP1_3", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_LR_LOWER_B_MMCM_TESTIN25", + "CMT_TOP_SE4C2_14", + "CMT_TOP_EE4B1_15", + "CMT_TOP_WW4A3_11", + "CMT_TOP_WW4END1_15", + "CMT_TOP_SW4END1_14", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_WW2A1_12", + "CMT_TOP_LH7_10", + "CMT_TOP_EE4C3_15", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_NW4A1_2", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_ER1BEG2_13", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_WW2A1_6", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_WW4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4END1_8", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WW4END2_8", + "CMT_MMCM_DQS_TO_PHASERA", + "CMT_TOP_IMUX7_3", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NE4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_BYP6_2", + "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "CMT_TOP_LH3_8", + "CMT_TOP_WW4B0_5", + "CMT_TOP_LH12_10", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX41_8", + "CMT_TOP_IMUX36_7", + "CMT_TOP_NE4C0_9", + "CMT_TOP_IMUX32_8", + "CMT_TOP_IMUX17_10", + "CMT_TOP_IMUX7_9", + "CMT_TOP_SW4END0_1", + "CMT_TOP_WW2END3_5", + "CMT_TOP_FAN5_13", + "CMT_TOP_IMUX12_8", + "CMT_TOP_NW4END3_1", + "CMT_TOP_EE4A2_14", + "CMT_TOP_IMUX38_14", + "CMT_TOP_LOGIC_OUTS_L_B6_14", + "CMT_TOP_NE2A3_0", + "CMT_TOP_CLK1_3", + "CMT_TOP_EL1BEG1_14", + "CMT_TOP_WR1END0_8", + "CMT_TOP_FAN2_8", + "CMT_TOP_IMUX29_10", + "CMT_TOP_LH12_14", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_SW2A1_15", + "CMT_TOP_WW2END0_15", + "CMT_TOP_WW4B3_13", + "CMT_TOP_EE4B3_0", + "CMT_TOP_BYP4_1", + "CMT_TOP_NE2A3_12", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_OCLK_7", + "CMT_TOP_WW4C0_11", + "CMT_TOP_WW4C0_3", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_NE4C2_13", + "CMT_TOP_EE4C2_1", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_IMUX1_1", + "CMT_TOP_EE2A0_9", + "CMT_TOP_LH2_9", + "CMT_TOP_NE2A0_14", + "CMT_TOP_SE4C1_10", + "CMT_TOP_NW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_NE4BEG2_13", + "CMT_TOP_SE4C2_9", + "CMT_TOP_IMUX35_6", + "CMT_TOP_WW2A3_12", + "CMT_TOP_EE4A0_6", + "CMT_TOP_SE4C0_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_WL1END1_9", + "CMT_TOP_BYP5_12", + "CMT_TOP_EE4C0_9", + "CMT_TOP_WW2END1_3", + "CMT_TOP_IMUX3_4", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_NE2A1_0", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_IMUX39_7", + "CMT_TOP_IMUX14_2", + "CMT_MMCM_PHYCTRL_SYNC_BB_DN", + "CMT_TOP_WW4C3_2", + "CMT_TOP_EE4B3_8", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW4END1_5", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_IMUX11_14", + "CMT_TOP_EE4A2_7", + "CMT_TOP_EE2A0_1", + "CMT_TOP_LOGIC_OUTS_L_B10_12", + "CMT_TOP_IMUX4_14", + "CMT_TOP_WW4B0_6", + "CMT_TOP_IMUX12_9", + "CMT_TOP_WW4A0_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_NE4BEG2_12", + "CMT_TOP_WW2A1_11", + "CMT_TOP_IMUX36_15", + "CMT_TOP_IMUX23_6", + "CMT_TOP_IMUX26_12", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B13_12", + "CMT_TOP_NE4BEG2_15", + "CMT_TOP_IMUX1_3", + "CMT_TOP_SE4C1_9", + "CMT_TOP_EE4C2_13", + "CMT_TOP_WW4END0_14", + "CMT_TOP_WW2A0_9", + "CMT_TOP_WW4C1_11", + "CMT_TOP_ER1BEG1_14", + "CMT_TOP_BYP7_3", + "CMT_TOP_EE4A0_9", + "CMT_TOP_IMUX6_11", + "CMT_TOP_OCLKDIV_14", + "CMT_TOP_IMUX30_7", + "CMT_TOP_ICLK_4", + "CMT_TOP_BYP5_9", + "CMT_TOP_EE2A0_13", + "CMT_TOP_LOGIC_OUTS_L_B21_15", + "CMT_TOP_OCLKDIV_8", + "CMT_L_LOWER_B_CLK_MMCM13", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_WW4B0_14", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN1_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT12", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX30_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_LOGIC_OUTS_L_B11_13", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_WW2A0_5", + "CMT_TOP_LOGIC_OUTS_L_B18_15", + "CMT_TOP_WW4C1_0", + "CMT_TOP_WL1END2_11", + "CMT_TOP_IMUX14_3", + "CMT_TOP_EE4B1_9", + "CMT_LR_LOWER_B_MMCM_DADDR2", + "CMT_TOP_SW4END1_5", + "CMT_TOP_WL1END3_14", + "CMT_TOP_NE2A0_2", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_WW4C2_11", + "CMT_TOP_NW2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_NE4BEG0_15", + "CMT_TOP_FAN3_8", + "CMT_LR_LOWER_B_MMCM_DO10", + "CMT_TOP_EL1BEG0_14", + "CMT_TOP_IMUX27_7", + "CMT_TOP_WW4END1_1", + "CMT_TOP_CLK1_15", + "CMT_TOP_FAN4_11", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LH8_6", + "CMT_TOP_SW4A3_15", + "CMT_TOP_FAN0_12", + "CMT_TOP_EE4A0_1", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_WL1END0_14", + "CMT_TOP_WL1END2_3", + "CMT_TOP_SW4END1_9", + "CMT_TOP_NW4A1_14", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4END1_6", + "CMT_TOP_WL1END2_4", + "CMT_TOP_FAN5_15", + "CMT_TOP_WR1END0_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT9", + "CMT_TOP_LH5_9", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX3_3", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_WW4B0_12", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_EE4A0_15", + "CMT_TOP_SW4A2_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT63", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_SE4BEG1_12", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_IMUX27_13", + "CMT_TOP_IMUX46_15", + "CMT_TOP_LOGIC_OUTS_L_B17_12", + "CMT_TOP_LH10_14", + "CMT_TOP_WW4B2_13", + "CMT_TOP_IMUX44_14", + "CMT_TOP_WW4A1_9", + "CMT_TOP_EE4A3_13", + "CMT_TOP_EE2A0_5", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH4_7", + "CMT_TOP_IMUX8_11", + "CMT_TOP_LH2_15", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B23_12", + "CMT_TOP_LH4_11", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_WR1END3_14", + "CMT_TOP_EE4A1_2", + "CMT_TOP_EE4C0_14", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_IMUX14_4", + "CMT_TOP_EE4C0_13", + "CMT_TOP_EE4A3_14", + "CMT_TOP_EE4B2_13", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_IMUX14_12", + "CMT_TOP_CTRL0_5", + "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "CMT_TOP_WW4C0_13", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_EE4A0_3", + "CMT_TOP_IMUX11_12", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX43_3", + "CMT_TOP_WW4A3_15", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LH11_11", + "CMT_TOP_FAN1_5", + "CMT_TOP_NW2A0_7", + "CMT_TOP_MONITOR_P_14", + "CMT_TOP_EE4B2_1", + "CMT_TOP_IMUX31_7", + "CMT_TOP_BYP2_12", + "CMT_TOP_WW4B2_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX6_10", + "CMT_L_LOWER_B_CLK_MMCM7", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_IMUX47_0", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_IMUX21_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_FAN4_9", + "CMT_TOP_WW4A2_14", + "CMT_TOP_ER1BEG0_13", + "CMT_TOP_SW4A0_8", + "CMT_LR_LOWER_B_MMCM_DRDY", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_IMUX22_15", + "CMT_TOP_CLK0_0", + "CMT_TOP_LH9_7", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END3_7", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_IMUX5_11", + "CMT_TOP_EL1BEG3_13", + "CMT_TOP_EE4B2_9", + "CMT_TOP_IMUX33_12", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_NW2A1_2", + "CMT_TOP_WL1END0_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT14", + "CMT_TOP_SW4END1_1", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_TOP_NW4A1_1", + "CMT_LR_LOWER_B_MMCM_DWE", + "CMT_TOP_NW2A0_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT59", + "CMT_TOP_BYP3_9", + "CMT_TOP_WW2A2_4", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_SW4A0_9", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_NE2A0_11", + "CMT_TOP_EE4A2_11", + "CMT_TOP_SE4C2_5", + "CMT_TOP_WW4END2_7", + "CMT_TOP_EE4A3_4", + "CMT_TOP_LH9_5", + "CMT_TOP_BYP5_15", + "CMT_TOP_NE2A0_3", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_IMUX46_9", + "CMT_TOP_WR1END2_14", + "CMT_TOP_EE2A2_0", + "CMT_TOP_IMUX1_14", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_WW4END2_14", + "CMT_TOP_WW2A3_15", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_IMUX33_11", + "CMT_L_LOWER_B_CLK_PERF2", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_IMUX26_4", + "CMT_TOP_WW4END1_14", + "CMT_TOP_IMUX38_1", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WR1END0_11", + "CMT_TOP_FAN4_10", + "CMT_TOP_FAN2_11", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_EE4B1_13", + "CMT_TOP_BYP1_8", + "CMT_TOP_IMUX31_1", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_SW4A2_14", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EE4C3_9", + "CMT_TOP_IMUX36_8", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SW4A1_0", + "CMT_TOP_SE2A1_10", + "CMT_TOP_EE4C0_5", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_LH7_0", + "CMT_TOP_IMUX33_7", + "CMT_TOP_SE4C1_2", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_13", + "CMT_TOP_FAN7_10", + "CMT_TOP_LH2_7", + "CMT_TOP_NE4C2_1", + "CMT_TOP_SW4A2_7", + "CMT_TOP_IMUX23_11", + "CMT_TOP_WR1END1_5", + "CMT_TOP_WW4A1_13", + "CMT_TOP_LOGIC_OUTS_L_B17_15", + "CMT_TOP_NE2A0_10", + "CMT_TOP_SW4END2_0", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_13", + "CMT_TOP_IMUX17_13", + "CMT_TOP_EE4C0_3", + "CMT_TOP_NW4A2_14", + "CMT_TOP_WL1END0_13", + "CMT_TOP_NW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_IMUX8_6", + "CMT_TOP_LH6_12", + "CMT_TOP_BYP0_7", + "CMT_TOP_LH5_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT7", + "CMT_TOP_IMUX5_2", + "CMT_TOP_BYP1_9", + "CMT_TOP_WL1END2_6", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX47_1", + "CMT_TOP_WW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_EE2A1_9", + "CMT_TOP_ER1BEG1_12", + "CMT_TOP_NE4C3_4", + "CMT_TOP_EE4B2_7", + "CMT_TOP_OCLK_5", + "CMT_TOP_NE2A1_6", + "CMT_TOP_IMUX45_4", + "CMT_TOP_IMUX8_2", + "CMT_TOP_IMUX1_2", + "CMT_TOP_IMUX46_0", + "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "CMT_TOP_EE4C1_9", + "MMCM_CLK_FREQ_BB_REBUF2_NS", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_SW4A0_15", + "CMT_TOP_LH1_7", + "CMT_TOP_BYP5_3", + "CMT_TOP_EE4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_12", + "CMT_TOP_IMUX40_4", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_BYP7_0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_LOGIC_OUTS_L_B23_14", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SW4A3_12", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4A3_6", + "CMT_TOP_LOGIC_OUTS_L_B12_13", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_EE4BEG0_12", + "CMT_TOP_FAN7_15", + "CMT_TOP_IMUX17_11", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_WR1END2_5", + "CMT_TOP_EE4A0_4", + "CMT_TOP_SE2A1_12", + "CMT_TOP_LOGIC_OUTS_L_B4_14", + "CMT_TOP_SW4A0_3", + "CMT_TOP_IMUX6_12", + "CMT_TOP_FAN3_15", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX11_6", + "CMT_TOP_IMUX25_7", + "CMT_TOP_IMUX4_8", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_WW4END3_12", + "CMT_TOP_WR1END3_12", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_WW2END0_13", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_IMUX16_8", + "CMT_TOP_MONITOR_P_15", + "CMT_TOP_NW4END0_5", + "CMT_TOP_NE4C3_10", + "CMT_TOP_WW4END1_12", + "CMT_TOP_SE2A3_6", + "CMT_TOP_IMUX3_9", + "CMT_TOP_IMUX7_4", + "CMT_TOP_LOGIC_OUTS_L_B14_15", + "CMT_TOP_EE4A0_13", + "CMT_TOP_LH3_11", + "CMT_TOP_EE2A3_14", + "CMT_TOP_BYP5_6", + "CMT_TOP_WW4C2_5", + "CMT_TOP_LH7_6", + "CMT_TOP_LOGIC_OUTS_L_B12_12", + "CMT_TOP_SE2A1_5", + "CMT_TOP_FAN4_7", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH9_2", + "CMT_TOP_LH2_12", + "CMT_TOP_BYP0_1", + "CMT_TOP_LH11_0", + "CMT_TOP_SE4BEG2_13", + "CMT_TOP_LH11_15", + "CMT_TOP_IMUX14_0", + "CMT_TOP_IMUX27_9", + "CMT_TOP_NW2A1_5", + "CMT_LR_LOWER_B_MMCM_TESTIN11", + "CMT_TOP_IMUX21_7", + "CMT_TOP_WW4A0_2", + "CMT_TOP_NE2A1_11", + "CMT_TOP_IMUX9_15", + "CMT_TOP_SW4END0_14", + "CMT_TOP_IMUX7_6", + "CMT_TOP_EE4B0_14", + "CMT_TOP_SW2A2_15", + "CMT_TOP_WL1END0_10", + "CMT_TOP_SW4END3_8", + "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "CMT_TOP_NW2A1_15", + "CMT_TOP_NW4A1_12", + "CMT_TOP_IMUX23_7", + "CMT_TOP_IMUX10_10", + "CMT_TOP_IMUX40_15", + "CMT_TOP_NW4END1_13", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4C1_2", + "CMT_TOP_LH4_3", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH5_6", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW4C1_4", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_FAN4_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_IMUX9_9", + "CMT_PHASER_A_OCLK_TOIOI", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NW4A3_5", + "CMT_TOP_BYP0_11", + "CMT_TOP_EE2BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B21_13", + "CMT_TOP_ICLK_13", + "CMT_TOP_IMUX25_15", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_IMUX33_2", + "CMT_TOP_BYP2_1", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_LOGIC_OUTS_L_B13_15", + "CMT_L_LOWER_B_CLK_IN3_HCLK", + "CMT_TOP_SE2A3_8", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_IMUX25_9", + "CMT_TOP_WW2END1_2", + "CMT_TOP_CLK0_14", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_LH8_12", + "CMT_TOP_EE4B2_2", + "CMT_LR_LOWER_B_MMCM_TESTIN26", + "CMT_TOP_WW4C3_14", + "CMT_LR_LOWER_B_MMCM_TESTIN29", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_IMUX13_9", + "CMT_TOP_NE4BEG0_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT51", + "CMT_TOP_ICLKDIV_12", + "CMT_TOP_NW2A2_7", + "CMT_TOP_OCLKDIV_11", + "CMT_LR_LOWER_B_MMCM_DI4", + "CMT_TOP_IMUX5_8", + "CMT_TOP_ICLKDIV_15", + "CMT_TOP_EL1BEG3_15", + "CMT_LR_LOWER_B_MMCM_TESTIN5", + "CMT_TOP_WW4C0_14", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_IMUX33_5", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WW4END2_11", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE4BEG0_15", + "CMT_TOP_EE2A0_7", + "CMT_TOP_WR1END1_10", + "CMT_TOP_FAN0_9", + "CMT_TOP_FAN4_15", + "CMT_TOP_EE4C2_10", + "CMT_TOP_SW4END3_0", + "CMT_TOP_WR1END1_2", + "CMT_TOP_NW4A1_5", + "CMT_TOP_EE4B3_12", + "CMT_TOP_IMUX4_9", + "CMT_TOP_IMUX47_8", + "CMT_LR_LOWER_B_MMCM_DO2", + "CMT_TOP_WW4C1_3", + "CMT_TOP_IMUX26_9", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_IMUX41_2", + "CMT_TOP_SE4C1_5", + "CMT_TOP_WL1END2_7", + "CMT_TOP_WW4A0_1", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_LH3_13", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_CTRL0_4", + "CMT_TOP_NW4END2_3", + "CMT_TOP_SE2A2_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT53", + "CMT_TOP_LOGIC_OUTS_L_B22_14", + "CMT_TOP_WW4C2_3", + "CMT_TOP_IMUX0_15", + "CMT_TOP_WW2A3_3", + "CMT_TOP_WL1END3_4", + "CMT_TOP_SE2A3_14", + "CMT_TOP_NE2A2_8", + "CMT_TOP_SW2A0_9", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_SW2A0_8", + "CMT_TOP_WW4B3_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_SW4A3_9", + "CMT_TOP_SE4C0_7", + "CMT_TOP_IMUX1_10", + "CMT_TOP_IMUX4_0", + "CMT_TOP_IMUX40_2", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_IMUX6_15", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX1_6", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_IMUX14_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_IMUX7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WW4A2_4", + "CMT_TOP_WW4B1_7", + "CMT_TOP_SE4BEG1_13", + "CMT_TOP_EE2A1_6", + "CMT_TOP_IMUX19_2", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_WW4C2_13", + "CMT_TOP_IMUX25_12", + "CMT_TOP_MONITOR_N_6", + "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_FAN3_4", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP7_9", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX24_10", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_SW4END1_13", + "CMT_TOP_IMUX19_12", + "CMT_TOP_SW2A0_2", + "CMT_TOP_BYP7_8", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX47_7", + "CMT_TOP_BYP0_4", + "CMT_TOP_IMUX21_6", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_EE4A3_11", + "CMT_TOP_FAN4_13", + "CMT_TOP_IMUX5_4", + "CMT_TOP_SE2A3_10", + "CMT_TOP_SW4END2_10", + "CMT_TOP_NW2A0_5", + "CMT_TOP_SE2A0_14", + "CMT_TOP_NE4C1_2", + "CMT_TOP_WW4C0_9", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_WW2END0_1", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_EE2BEG1_15", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_LR_LOWER_B_MMCM_DI8", + "CMT_LR_LOWER_B_MMCM_DI1", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX33_13", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX0_0", + "CMT_MMCM_A_RDCLK_TOFIFO", + "CMT_TOP_IMUX15_9", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SW2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B19_15", + "CMT_TOP_WW4C2_0", + "CMT_TOP_ICLK_8", + "CMT_TOP_FAN4_14", + "CMT_TOP_EE4C1_15", + "CMT_TOP_NW2A1_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT50", + "CMT_TOP_CTRL0_6", + "CMT_LR_LOWER_B_MMCM_DI9", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_NE4BEG1_9", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_WW4A0_6", + "CMT_TOP_IMUX6_8", + "CMT_TOP_WW4C0_15", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WR1END0_1", + "CMT_TOP_CLK0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_IMUX41_13", + "CMT_L_LOWER_B_CLK_MMCM3", + "CMT_TOP_EE4B3_15", + "CMT_LR_LOWER_B_MMCM_TESTIN30", + "CMT_TOP_FAN6_15", + "CMT_TOP_LH10_12", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_SW2A1_4", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_IMUX27_1", + "CMT_TOP_IMUX31_15", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_LOGIC_OUTS_L_B19_13", + "CMT_TOP_BYP3_14", + "CMT_TOP_IMUX23_9", + "CMT_TOP_IMUX4_13", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_IMUX30_6", + "CMT_TOP_NW4END1_9", + "CMT_TOP_EE2BEG0_15", + "CMT_TOP_IMUX39_2", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX10_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_WW4END3_0", + "MMCMOUT_CLK_FREQ_BB_2", + "CMT_TOP_LH9_15", + "CMT_TOP_NW4END1_11", + "CMT_TOP_LOGIC_OUTS_L_B15_12", + "CMT_TOP_EE4C2_8", + "CMT_TOP_IMUX16_3", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_SW4A3_11", + "CMT_TOP_IMUX43_11", + "CMT_TOP_OCLK_8", + "CMT_TOP_NE2A0_6", + "CMT_TOP_WW2A3_2", + "CMT_LR_LOWER_B_MMCM_TESTIN22", + "CMT_TOP_CTRL1_6", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_WW4B2_14", + "CMT_LR_LOWER_B_MMCM_DO0", + "CMT_TOP_WW4A1_14", + "CMT_TOP_EE4A0_8", + "CMT_TOP_SE4C1_3", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_IMUX8_5", + "CMT_TOP_IMUX9_1", + "CMT_TOP_IMUX20_14", + "CMT_TOP_EE4BEG2_13", + "CMT_TOP_WW4A0_9", + "CMT_TOP_IMUX30_13", + "CMT_TOP_WR1END1_15", + "CMT_LR_LOWER_B_MMCM_DO8", + "CMT_TOP_EE4A3_8", + "CMT_TOP_IMUX37_5", + "CMT_LR_LOWER_B_MMCM_DO3", + "CMT_TOP_SW4A1_12", + "CMT_TOP_IMUX11_10", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX44_2", + "CMT_TOP_IMUX28_6", + "CMT_TOP_NW4A0_7", + "CMT_TOP_IMUX32_14", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_IMUX40_10", + "CMT_TOP_EE2A2_12", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_IMUX32_13", + "CMT_TOP_IMUX23_14", + "CMT_TOP_WW2END2_14", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_CLK0_1", + "CMT_TOP_SW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX23_1", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_LH3_14", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_WW2END1_6", + "CMT_TOP_SW2A0_1", + "CMT_TOP_CTRL1_3", + "CMT_TOP_IMUX10_7", + "CMT_TOP_LOGIC_OUTS_L_B20_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT1", + "CMT_TOP_NE4C2_8", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_WW2A0_13", + "CMT_TOP_BYP3_15", + "CMT_TOP_IMUX6_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_LOGIC_OUTS_L_B15_15", + "CMT_TOP_NW2A3_4", + "CMT_TOP_WR1END2_9", + "CMT_TOP_IMUX27_8", + "CMT_TOP_LH6_3", + "CMT_TOP_NE2A1_1", + "CMT_TOP_CLK0_9", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_BYP0_9", + "CMT_TOP_EE2A2_9", + "CMT_TOP_IMUX39_14", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_SW2A2_12", + "CMT_TOP_IMUX38_13", + "CMT_TOP_WW2END1_1", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_EE2A0_4", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B21_14", + "CMT_TOP_FAN1_7", + "CMT_TOP_LH12_15", + "CMT_TOP_WW4A3_3", + "CMT_TOP_IMUX19_15", + "CMT_TOP_NW4END3_2", + "CMT_TOP_SW4END2_1", + "CMT_TOP_EE4A3_3", + "CMT_TOP_EE4A1_0", + "CMT_TOP_SW4A2_9", + "CMT_TOP_IMUX33_15", + "CMT_TOP_LH3_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_IMUX41_0", + "CMT_TOP_IMUX32_6", + "CMT_TOP_WR1END3_4", + "CMT_TOP_BYP7_12", + "CMT_TOP_SW2A1_11", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_LOGIC_OUTS_L_B20_14", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX11_7", + "CMT_TOP_SW2A2_5", + "CMT_TOP_FAN5_0", + "CMT_TOP_WW2END2_7", + "CMT_TOP_NW4A2_10", + "CMT_TOP_SW4END1_8", + "CMT_TOP_EL1BEG2_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT34", + "CMT_TOP_BYP1_4", + "CMT_TOP_IMUX17_4", + "CMT_TOP_WR1END0_12", + "CMT_TOP_WW2A1_8", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_IMUX4_10", + "CMT_TOP_FAN6_9", + "CMT_TOP_NW2A3_15", + "CMT_TOP_BYP1_14", + "CMT_TOP_NW2A2_0", + "CMT_TOP_IMUX11_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_IMUX21_12", + "CMT_TOP_EL1BEG0_15", + "CMT_TOP_WW2A3_9", + "CMT_TOP_WW4B3_11", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_LOGIC_OUTS_L_B5_15", + "CMT_TOP_SE2A1_14", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_WL1END1_13", + "CMT_TOP_LOGIC_OUTS_L_B18_12", + "CMT_TOP_WW4END2_3", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_WW4END0_7", + "CMT_TOP_IMUX7_15", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_BYP7_15", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_LH6_10", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4END1_12", + "CMT_TOP_IMUX41_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_NE2A2_6", + "CMT_TOP_IMUX37_2", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WR1END1_7", + "CMT_TOP_IMUX14_9", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_IMUX7_2", + "CMT_TOP_FAN2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_L_LOWER_B_CLK_MMCM8", + "CMT_TOP_WW4A0_7", + "CMT_TOP_EE4C0_8", + "CMT_TOP_EE4BEG3_15", + "CMT_TOP_WR1END0_14", + "CMT_TOP_SE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_CTRL0_13", + "CMT_TOP_WR1END3_8", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_IMUX37_1", + "CMT_TOP_NW2A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_12", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_WW4A3_13", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX7_12", + "CMT_TOP_NW2A2_3", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A2_6", + "CMT_TOP_EE4C0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_FAN3_11", + "CMT_TOP_SW4END0_0", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_NE4C3_11", + "CMT_TOP_IMUX37_6", + "CMT_TOP_BYP5_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_LH8_4", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SE4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_IMUX46_5", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_LH8_8", + "CMT_TOP_NE4C3_9", + "CMT_TOP_WW4B1_1", + "CMT_TOP_BLOCK_OUTS_L_B2_12", + "CMT_LR_LOWER_B_MMCM_DADDR5", + "CMT_TOP_OCLK1X_90_14", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX26_10", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_IMUX2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_IMUX36_4", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SW2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B13_13", + "CMT_TOP_EE4A1_10", + "CMT_TOP_SW2A3_8", + "CMT_TOP_WW2A2_5", + "CMT_TOP_IMUX24_11", + "CMT_TOP_SW2A2_9", + "CMT_TOP_FAN5_12", + "CMT_TOP_SW4A0_6", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW4A0_14", + "CMT_TOP_WR1END0_5", + "CMT_TOP_IMUX4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_CTRL0_11", + "CMT_TOP_IMUX19_8", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_IMUX36_5", + "CMT_TOP_WW2A0_3", + "CMT_TOP_BYP6_14", + "CMT_TOP_LH10_5", + "CMT_TOP_BYP6_15", + "CMT_TOP_NE4C3_3", + "CMT_TOP_FAN7_2", + "CMT_TOP_IMUX7_10", + "CMT_L_LOWER_B_CLK_IN1_INT", + "CMT_TOP_SE4BEG2_14", + "CMT_TOP_WW4B1_11", + "CMT_TOP_BYP6_1", + "CMT_TOP_WL1END2_1", + "CMT_TOP_SW4A0_2", + "CMT_TOP_IMUX10_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_LH12_13", + "CMT_TOP_OCLK_10", + "CMT_TOP_LH5_2", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_SW2A2_6", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_NW4END3_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT49", + "CMT_TOP_NW4END3_8", + "CMT_TOP_WL1END3_13", + "CMT_TOP_WL1END0_7", + "CMT_TOP_IMUX35_15", + "CMT_TOP_IMUX10_11", + "CMT_TOP_SE4C1_15", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX9_7", + "CMT_TOP_BYP5_7", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_NW4END3_13", + "CMT_TOP_EE2A3_13", + "CMT_TOP_SW2A1_6", + "CMT_TOP_IMUX13_13", + "CMT_TOP_IMUX12_14", + "CMT_TOP_IMUX18_11", + "CMT_TOP_IMUX37_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_LOGIC_OUTS_L_B18_13", + "CMT_TOP_EE4B2_8", + "CMT_TOP_WW2A1_10", + "CMT_TOP_LH11_13", + "CMT_TOP_IMUX42_5", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_IMUX22_12", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LH8_10", + "CMT_TOP_MONITOR_N_15", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_LR_LOWER_B_MMCM_TESTIN24", + "CMT_TOP_IMUX24_5", + "CMT_TOP_NW2A2_10", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_SW2A2_8", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN1_12", + "CMT_TOP_FAN5_6", + "CMT_TOP_LOGIC_OUTS_L_B20_15", + "CMT_TOP_FAN3_3", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_EE2A1_3", + "CMT_TOP_IMUX24_9", + "CMT_TOP_SE2A2_2", + "CMT_TOP_IMUX25_10", + "CMT_LR_LOWER_B_MMCM_DO7", + "CMT_TOP_SE4C3_0", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_EE2A1_7", + "CMT_TOP_BYP7_13", + "CMT_TOP_WL1END2_13", + "CMT_TOP_IMUX45_6", + "CMT_TOP_SW4END0_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX3_8", + "CMT_TOP_WW2END2_12", + "CMT_TOP_WR1END2_12", + "CMT_TOP_WW2END1_9", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_LH6_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT11", + "CMT_TOP_OCLK_11", + "CMT_TOP_BYP1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_SW4A1_4", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_IMUX40_9", + "CMT_TOP_IMUX25_11", + "CMT_TOP_LH10_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_SE4C2_12", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_WW4END3_3", + "CMT_TOP_WW4B3_2", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_FAN3_0", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_WW4B3_12", + "CMT_TOP_IMUX32_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_EE4A0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4END0_12", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_FAN0_11", + "CMT_TOP_SE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_IMUX44_4", + "CMT_TOP_SW4A2_11", + "CMT_TOP_SW4END0_9", + "CMT_TOP_EE4C1_5", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_IMUX29_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT13", + "CMT_LR_LOWER_B_MMCM_DO4", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX32_0", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_LOGIC_OUTS_L_B3_14", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_SW4END2_3", + "CMT_TOP_BYP4_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_FAN5_4", + "CMT_TOP_EE2A2_2", + "CMT_TOP_EE4A2_1", + "CMT_TOP_EE2A2_11", + "CMT_TOP_NW4A2_11", + "CMT_TOP_IMUX43_15", + "CMT_TOP_ICLKDIV_13", + "CMT_TOP_NW4END3_10", + "CMT_TOP_OCLK1X_90_12", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4END1_15", + "CMT_TOP_LH11_8", + "CMT_TOP_IMUX45_5", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WR1END0_6", + "CMT_TOP_IMUX20_15", + "CMT_TOP_SW4A3_13", + "CMT_TOP_IMUX3_1", + "CMT_TOP_IMUX10_12", + "CMT_TOP_WW4END3_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_IMUX16_2", + "CMT_TOP_IMUX34_10", + "CMT_TOP_FAN4_4", + "CMT_TOP_FAN7_3", + "CMT_LR_LOWER_B_MMCM_DADDR1", + "CMT_TOP_IMUX15_14", + "CMT_TOP_NW4END2_13", + "CMT_TOP_LH4_0", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_NE2A3_13", + "CMT_TOP_FAN3_9", + "CMT_TOP_FAN0_15", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_IMUX22_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_WL1END1_14", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_EE4C3_6", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_L_LOWER_B_CLK_IN3_INT", + "CMT_TOP_BYP1_10", + "CMT_TOP_FAN7_0", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_FAN2_9", + "CMT_TOP_WW2A0_11", + "CMT_TOP_SW4A1_2", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_IMUX4_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_IMUX26_2", + "CMT_TOP_WW2END0_14", + "CMT_TOP_BYP5_11", + "CMT_TOP_IMUX33_14", + "CMT_TOP_BYP2_10", + "CMT_TOP_FAN1_8", + "CMT_L_LOWER_B_CLK_FREQ_BB2", + "CMT_TOP_LH8_11", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_IMUX11_8", + "CMT_TOP_SE4C2_10", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX5_6", + "CMT_TOP_IMUX38_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT6", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_SE4BEG1_14", + "CMT_TOP_LH2_10", + "CMT_TOP_CLK1_7", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4B3_1", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_IMUX16_5", + "CMT_TOP_CLK1_4", + "CMT_TOP_LH8_3", + "CMT_TOP_LH7_13", + "CMT_TOP_IMUX22_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_NE4BEG0_13", + "CMT_TOP_IMUX45_2", + "CMT_TOP_LH4_12", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_NE4C0_11", + "CMT_TOP_EE4B1_2", + "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "CMT_TOP_IMUX15_10", + "CMT_TOP_NE2A3_14", + "CMT_TOP_WW4C0_0", + "CMT_TOP_SW2A1_7", + "CMT_TOP_EE4C3_13", + "CMT_TOP_BYP2_4", + "CMT_L_LOWER_B_CLK_MMCM11", + "CMT_TOP_EE4B3_1", + "CMT_TOP_SE4C3_3", + "CMT_TOP_WW4END1_9", + "CMT_TOP_IMUX47_13", + "CMT_TOP_EE4B1_12", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_SW4END1_4", + "CMT_TOP_IMUX31_14", + "CMT_TOP_IMUX12_12", + "CMT_TOP_NE4BEG2_3", + "CMT_LR_LOWER_B_MMCM_DO15", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_WW2A0_7", + "CMT_TOP_IMUX34_7", + "CMT_TOP_EE4A0_14", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_WW2A2_12", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX27_4", + "CMT_TOP_OCLK_1", + "CMT_TOP_NW4END0_2", + "CMT_TOP_EE2A1_5", + "CMT_TOP_FAN4_2", + "CMT_TOP_CTRL1_11", + "CMT_LR_LOWER_B_MMCM_DADDR0", + "CMT_TOP_WW4C3_8", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_1", + "CMT_TOP_IMUX45_9", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_IMUX37_14", + "CMT_TOP_SW4END2_11", + "CMT_LR_LOWER_B_MMCM_TESTIN4", + "CMT_TOP_SE2A2_5", + "CMT_TOP_WR1END2_6", + "CMT_TOP_IMUX15_13", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_IMUX45_13", + "CMT_TOP_IMUX24_14", + "CMT_TOP_NW2A0_15", + "CMT_TOP_FAN2_7", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW2END2_11", + "CMT_TOP_OCLK_15", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_SW4A3_1", + "CMT_TOP_NE2A2_12", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX42_6", + "CMT_TOP_SW4END3_13", + "CMT_TOP_EE4B1_1", + "CMT_TOP_BYP0_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_NW4END0_13", + "CMT_TOP_IMUX44_15", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_IMUX10_13", + "CMT_TOP_CLK1_11", + "CMT_LR_LOWER_B_MMCM_DI2", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_EE4C3_11", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_IMUX32_10", + "CMT_TOP_IMUX25_13", + "CMT_TOP_IMUX2_14", + "CMT_TOP_NW4A0_4", + "CMT_TOP_IMUX23_15", + "CMT_TOP_EL1BEG2_12", + "CMT_TOP_SW4A3_10", + "CMT_TOP_OCLKDIV_15", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_NW4END2_8", + "CMT_TOP_SE2A3_12", + "CMT_LR_LOWER_B_MMCM_TESTIN23", + "CMT_TOP_EE2A0_10", + "CMT_TOP_EE2A3_9", + "CMT_TOP_SW2A2_14", + "CMT_TOP_LOGIC_OUTS_L_B0_13", + "CMT_TOP_SW2A1_1", + "CMT_TOP_EE4B2_4", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_WW2A3_14", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX18_0", + "CMT_TOP_LOGIC_OUTS_L_B3_15", + "CMT_TOP_EE4C3_14", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_BYP6_4", + "CMT_TOP_NW4END1_6", + "CMT_TOP_NW4A3_13", + "CMT_TOP_IMUX7_14", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_LH7_4", + "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "CMT_TOP_IMUX42_14", + "CMT_TOP_IMUX23_0", + "CMT_TOP_NW4END3_15", + "CMT_TOP_IMUX43_8", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX21_4", + "CMT_TOP_IMUX21_2", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_EE4A2_9", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE4B0_5", + "CMT_TOP_IMUX47_10", + "CMT_L_LOWER_B_CLK_MMCM12", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_6", + "CMT_TOP_EE2BEG0_14", + "CMT_TOP_WW4C0_1", + "CMT_TOP_WW2A3_0", + "CMT_TOP_FAN7_1", + "CMT_TOP_MONITOR_P_12", + "CMT_TOP_IMUX46_13", + "CMT_TOP_WL1END1_15", + "CMT_TOP_NW2A1_3", + "CMT_LR_LOWER_B_MMCM_TESTOUT45", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_IMUX18_14", + "CMT_TOP_IMUX4_3", + "CMT_L_LOWER_B_CLK_IN2_HCLK", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_EE4A2_13", + "CMT_TOP_WW2END3_13", + "CMT_TOP_LH1_10", + "CMT_TOP_EE4BEG2_12", + "CMT_TOP_BYP1_15", + "CMT_TOP_NW4END3_14", + "CMT_TOP_EE4B0_10", + "CMT_TOP_SE2A3_2", + "CMT_TOP_IMUX16_6", + "CMT_TOP_IMUX11_13", + "CMT_TOP_IMUX1_5", + "CMT_LR_LOWER_B_MMCM_DI0", + "CMT_LR_LOWER_B_MMCM_TESTIN28", + "CMT_TOP_IMUX5_15", + "CMT_TOP_SE4C1_4", + "CMT_MMCM_PHASERA_DQSBUS1", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_LH1_14", + "CMT_TOP_NW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_EE4B3_5", + "CMT_TOP_IMUX26_7", + "CMT_TOP_NE4C1_0", + "CMT_TOP_EE2A3_8", + "CMT_TOP_IMUX45_11", + "CMT_TOP_FAN4_12", + "CMT_TOP_ER1BEG2_12", + "CMT_TOP_WW4B2_4", + "CMT_TOP_BYP2_14", + "CMT_TOP_IMUX40_0", + "CMT_TOP_IMUX14_6", + "CMT_TOP_NW2A3_0", + "CMT_MMCM_PHASERA_CTSBUS0", + "CMT_TOP_EE4A0_2", + "CMT_TOP_BYP2_15", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_EE4B0_15", + "CMT_TOP_EE2A1_15", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_NW4END3_11", + "CMT_TOP_IMUX8_7", + "CMT_TOP_WW2END0_4", + "CMT_TOP_SW4A1_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_LH10_7", + "CMT_TOP_EE4C2_3", + "CMT_TOP_SE2A3_9", + "CMT_TOP_IMUX1_12", + "CMT_TOP_EL1BEG3_3", + "CMT_LR_LOWER_B_MMCM_DI6", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_11", + "CMT_TOP_IMUX20_13", + "CMT_TOP_EE2A1_11", + "CMT_LR_LOWER_B_MMCM_TESTIN20", + "CMT_TOP_WW4C1_12", + "CMT_TOP_SE2A1_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_SE2A0_13", + "CMT_TOP_WR1END0_0", + "CMT_TOP_WW2A1_9", + "CMT_MMCM_PHASERREF_BELOW0", + "CMT_TOP_FAN1_11", + "CMT_TOP_IMUX18_4", + "CMT_L_LOWER_B_CLK_MMCM6", + "CMT_TOP_WL1END1_5", + "CMT_TOP_SW4A1_13", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_IMUX39_13", + "CMT_TOP_NE2A2_3", + "CMT_TOP_NE4BEG1_13", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_WW4END1_3", + "CMT_TOP_IMUX24_1", + "CMT_TOP_WW2END2_6", + "CMT_TOP_SE2A2_13", + "CMT_TOP_WW2A2_11", + "CMT_TOP_SW2A0_10", + "CMT_TOP_EE2A3_0", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_WW2A3_7", + "CMT_TOP_WL1END2_0", + "CMT_TOP_IMUX9_14", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_EE4B3_14", + "CMT_TOP_SW2A0_6", + "CMT_TOP_LOGIC_OUTS_L_B5_12", + "CMT_TOP_NW4A3_9", + "CMT_TOP_IMUX13_11", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_IMUX6_0", + "CMT_TOP_NW2A0_1", + "CMT_TOP_LH1_11", + "CMT_TOP_NW2A2_6", + "CMT_TOP_CTRL0_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT39", + "CMT_TOP_WR1END1_3", + "CMT_TOP_WW4A2_13", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX43_0", + "CMT_TOP_SE2A1_11", + "CMT_TOP_LH9_13", + "CMT_TOP_LOGIC_OUTS_L_B2_14", + "CMT_TOP_ER1BEG1_15", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4C3_0", + "CMT_TOP_LH11_1", + "CMT_TOP_SW2A1_8", + "CMT_TOP_EE4C3_4", + "CMT_TOP_NW4A3_11", + "CMT_TOP_ER1BEG3_8", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN7_4", + "CMT_TOP_NW4END0_4", + "CMT_TOP_FAN1_6", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_IMUX22_10", + "CMT_TOP_WW4B2_5", + "CMT_TOP_OCLK_14", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C1_4", + "CMT_TOP_IMUX20_4", + "CMT_TOP_WW2A2_1", + "CMT_TOP_WR1END1_11", + "CMT_TOP_IMUX18_12", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_12", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_L_LOWER_B_CLK_PERF0", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WR1END3_10", + "CMT_TOP_WW4A1_6", + "CMT_TOP_BYP7_11", + "CMT_TOP_WL1END2_15", + "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_NW2A1_12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_WW4B0_9", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX41_12", + "CMT_TOP_IMUX1_15", + "CMT_TOP_IMUX0_4", + "CMT_TOP_SE2A3_11", + "CMT_TOP_WW2A2_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT57", + "CMT_TOP_WR1END0_7", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_IMUX20_3", + "CMT_TOP_CTRL1_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EE4A2_5", + "CMT_TOP_SE4C1_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_IMUX27_12", + "CMT_TOP_NW4END0_0", + "CMT_TOP_NW4A3_10", + "CMT_LR_LOWER_B_MMCM_TESTIN31", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX12_2", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_LOGIC_OUTS_L_B0_14", + "CMT_TOP_NW4A3_8", + "CMT_TOP_WW4B0_2", + "CMT_TOP_NE2A0_7", + "CMT_TOP_IMUX34_5", + "CMT_TOP_EE4C2_12", + "CMT_TOP_SE4C3_13", + "CMT_TOP_EE4C2_5", + "CMT_TOP_WL1END2_2", + "CMT_TOP_IMUX6_3", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_IMUX12_13", + "CMT_TOP_ER1BEG3_15", + "CMT_TOP_IMUX35_7", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_IMUX28_10", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_IMUX2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_CTRL0_10", + "CMT_TOP_IMUX46_12", + "CMT_TOP_WW4END2_2", + "CMT_TOP_WL1END0_8", + "CMT_TOP_IMUX39_15", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_IMUX47_6", + "CMT_TOP_BYP1_12", + "CMT_TOP_IMUX23_2", + "CMT_TOP_LOGIC_OUTS_L_B15_13", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_WL1END0_9", + "CMT_TOP_IMUX39_6", + "CMT_TOP_EE4A3_12", + "CMT_TOP_IMUX2_12", + "CMT_TOP_EE4C0_10", + "CMT_TOP_IMUX6_4", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_IMUX12_3", + "CMT_TOP_LH8_2", + "CMT_TOP_EE2A3_15", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4A2_12", + "CMT_TOP_BYP2_5", + "CMT_TOP_NW2A0_10", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX38_8", + "CMT_TOP_IMUX0_6", + "CMT_TOP_NE4BEG3_11", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SE2A0_8", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NE2A0_1", + "CMT_LR_LOWER_B_MMCM_DADDR6", + "CMT_TOP_IMUX31_4", + "CMT_LR_LOWER_B_MMCM_DO14", + "CMT_LR_LOWER_B_MMCM_TESTOUT37", + "CMT_TOP_IMUX0_14", + "CMT_MMCM_PHASERA_CTSBUS1", + "CMT_TOP_NE2A3_9", + "CMT_TOP_WW4B3_9", + "CMT_L_LOWER_B_CLK_PERF1", + "CMT_TOP_IMUX5_1", + "CMT_TOP_IMUX47_2", + "CMT_TOP_LH12_1", + "CMT_TOP_SW2A3_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_SE4BEG0_14", + "CMT_TOP_WW2END3_6", + "CMT_TOP_NW2A0_8", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_IMUX44_3", + "CMT_TOP_LH3_4", + "CMT_TOP_EE2A2_1", + "CMT_TOP_WW4A2_3", + "CMT_TOP_IMUX27_15", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EL1BEG1_12", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX39_8", + "CMT_TOP_SW4END2_7", + "CMT_TOP_FAN2_4", + "CMT_TOP_EE4A1_6", + "CMT_TOP_EE4B1_3", + "CMT_TOP_WW2A2_9", + "CMT_TOP_IMUX42_10", + "CMT_TOP_IMUX22_14", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_NE4BEG1_15", + "CMT_TOP_WW4END0_1", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE4B1_0", + "CMT_TOP_IMUX34_11", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_SW4END3_15", + "CMT_TOP_IMUX10_3", + "CMT_TOP_IMUX47_15", + "CMT_TOP_WL1END3_2", + "CMT_LR_LOWER_B_MMCM_TESTIN14", + "CMT_TOP_NW4A2_8", + "CMT_TOP_LOGIC_OUTS_L_B19_14", + "CMT_TOP_IMUX35_5", + "CMT_TOP_WW4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_NE4C3_2", + "CMT_TOP_NE2A3_8", + "CMT_TOP_WW4END3_4", + "CMT_TOP_LH1_1", + "CMT_TOP_CTRL1_5", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_LH7_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_CLK0_8", + "CMT_TOP_NE2A0_5", + "CMT_TOP_SW4END2_6", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_EE4C3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_13", + "CMT_TOP_IMUX8_8", + "CMT_TOP_NE4C2_14", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_WR1END0_13", + "CMT_TOP_WW2A1_14", + "CMT_TOP_EE2A2_4", + "CMT_TOP_NE2A3_5", + "CMT_TOP_IMUX13_1", + "CMT_TOP_WW2END1_15", + "CMT_TOP_IMUX8_14", + "CMT_TOP_WW2END0_3", + "CMT_TOP_EE4C1_13", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_EE4A2_0", + "CMT_TOP_EE4C1_3", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_ER1BEG3_12", + "CMT_TOP_NE4C2_9", + "CMT_LR_LOWER_B_MMCM_DO5", + "CMT_TOP_EE2BEG3_12", + "CMT_TOP_NW2A2_4", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX37_3", + "CMT_TOP_IMUX37_8", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_IMUX2_13", + "CMT_TOP_LOGIC_OUTS_L_B9_12", + "CMT_TOP_NW4END2_14", + "CMT_TOP_CTRL1_2", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B4_15", + "CMT_TOP_BYP1_13", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_NE4BEG1_12", + "CMT_TOP_EE4B0_0", + "CMT_TOP_SE2A0_0", + "CMT_TOP_IMUX18_9", + "CMT_TOP_WW2END3_15", + "CMT_TOP_ICLKDIV_14", + "CMT_TOP_LH7_14", + "CMT_TOP_WW4B1_15", + "CMT_TOP_WW2END3_12", + "CMT_TOP_WW2END1_13", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4A3_9", + "CMT_TOP_IMUX3_2", + "CMT_TOP_SE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B0_13", + "CMT_TOP_WW4END1_0", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_IMUX8_13", + "CMT_TOP_WW2END3_14", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_WW4A1_15", + "CMT_LR_LOWER_B_MMCM_RST", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_NW4END2_6", + "CMT_TOP_IMUX34_1", + "CMT_TOP_LH6_9", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW4A2_1", + "CMT_TOP_SW4A2_4", + "CMT_TOP_LOGIC_OUTS_L_B23_15", + "CMT_TOP_IMUX21_15", + "CMT_TOP_NE4C2_11", + "MMCM_CLK_FREQ_BB_NS2", + "CMT_TOP_WW4END1_10", + "CMT_TOP_LH9_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_NE4C3_6", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WW2END3_1", + "CMT_TOP_BYP4_3", + "CMT_TOP_IMUX3_15", + "CMT_TOP_WW2END2_10", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_SE2A0_7", + "CMT_TOP_IMUX35_11", + "CMT_TOP_WW2END2_2", + "CMT_TOP_BYP7_5", + "CMT_TOP_SW4END0_11", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX45_12", + "CMT_TOP_SW2A1_2", + "CMT_TOP_EE4B1_6", + "CMT_TOP_WW2END0_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_EE4BEG1_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT15", + "CMT_TOP_NE4C1_14", + "CMT_TOP_EE2A2_14", + "CMT_MMCM_PHASERREF1", + "CMT_TOP_BYP5_0", + "CMT_TOP_IMUX32_9", + "CMT_TOP_EE2A0_12", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX38_10", + "CMT_TOP_LH1_4", + "CMT_TOP_IMUX13_15", + "CMT_TOP_NW4A0_6", + "CMT_TOP_LOGIC_OUTS_L_B10_15", + "CMT_TOP_WW4END3_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT31", + "CMT_TOP_EE4C2_2", + "CMT_TOP_CLK1_10", + "CMT_TOP_WW2A3_13", + "CMT_TOP_WL1END3_11", + "CMT_TOP_IMUX30_14", + "CMT_TOP_IMUX29_15", + "CMT_TOP_SE4C0_13", + "CMT_TOP_NW4A0_12", + "CMT_TOP_WW2END3_4", + "CMT_TOP_WW4C1_8", + "CMT_TOP_IMUX39_10", + "CMT_TOP_WR1END1_8", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_WW4END3_10", + "CMT_TOP_SE2A2_14", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4C3_10", + "CMT_TOP_EE4B3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_EE4B3_7", + "CMT_TOP_NW4END0_7", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SW4A1_10", + "CMT_TOP_LH4_6", + "CMT_TOP_NW4END1_14", + "CMT_TOP_WW4C2_14", + "CMT_TOP_IMUX22_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT44", + "CMT_TOP_NW2A2_5", + "CMT_TOP_LH7_3", + "CMT_TOP_IMUX20_1", + "CMT_TOP_WW4B1_3", + "CMT_TOP_FAN5_8", + "CMT_TOP_LOGIC_OUTS_L_B7_14", + "CMT_TOP_SE2A1_9", + "CMT_TOP_OCLK_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT10", + "CMT_TOP_SE4C2_0", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_FAN2_15", + "CMT_TOP_WW2A0_2", + "CMT_TOP_IMUX11_5", + "CMT_TOP_SW4END3_14", + "CMT_TOP_IMUX44_11", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_WW4A1_5", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX43_2", + "CMT_TOP_LH12_5", + "CMT_TOP_LOGIC_OUTS_L_B3_12", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_OCLK1X_90_13", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_IMUX46_1", + "CMT_TOP_EE4C2_6", + "CMT_TOP_WW4C3_1", + "CMT_TOP_WW2A1_13", + "CMT_TOP_ICLK_1", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B5_14", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_IMUX42_1", + "CMT_TOP_BYP7_6", + "CMT_TOP_NW4END1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_LH4_13", + "CMT_TOP_NE4C1_15", + "CMT_TOP_NW4A3_2", + "CMT_TOP_SW4A0_5", + "CMT_TOP_IMUX4_6", + "CMT_TOP_CLK0_12", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_NE4BEG3_13", + "CMT_TOP_WW4END0_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_IMUX3_6", + "CMT_TOP_SE4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_WW2A3_1", + "CMT_TOP_WW4C3_15", + "CMT_TOP_IMUX35_3", + "CMT_L_LOWER_B_CLK_FREQ_BB3", + "CMT_TOP_SW4END0_10", + "CMT_TOP_LH2_13", + "CMT_TOP_LH12_2", + "CMT_TOP_IMUX0_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WW4END2_6", + "CMT_TOP_NW4END1_15", + "CMT_TOP_LH11_7", + "CMT_TOP_SW4END3_3", + "CMT_TOP_SW2A3_13", + "CMT_TOP_IMUX46_14", + "CMT_TOP_IMUX28_12", + "CMT_TOP_WW4B1_12", + "CMT_TOP_NW4A1_7", + "CMT_TOP_BYP4_14", + "CMT_TOP_WW2A3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_NE2A1_13", + "CMT_TOP_IMUX47_14", + "CMT_TOP_IMUX19_6", + "CMT_TOP_ER1BEG0_15", + "CMT_TOP_FAN4_8", + "CMT_TOP_EE2A2_3", + "CMT_TOP_IMUX34_3", + "CMT_TOP_WW4END1_11", + "CMT_TOP_NW2A2_15", + "CMT_TOP_CLK0_7", + "CMT_TOP_FAN7_14", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4C3_14", + "CMT_TOP_SE4C3_7", + "CMT_TOP_WW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_IMUX35_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_MONITOR_P_13", + "CMT_TOP_IMUX10_0", + "CMT_TOP_LH11_3", + "CMT_TOP_SE2A0_9", + "CMT_TOP_SW4A2_15", + "CMT_TOP_WL1END3_7", + "CMT_TOP_IMUX34_8", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WR1END3_3", + "CMT_TOP_IMUX46_4", + "CMT_TOP_SE2A2_10", + "CMT_TOP_WW4C2_4", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_IMUX22_0", + "CMT_TOP_IMUX9_11", + "CMT_TOP_WW4A2_9", + "CMT_TOP_SE4C1_0", + "CMT_TOP_IMUX14_5", + "CMT_TOP_WL1END2_9", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_EE4C1_1", + "CMT_TOP_NW4A0_11", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX13_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_SE4C2_3", + "CMT_TOP_BYP3_13", + "CMT_TOP_WW4END0_12", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_EE4BEG2_15", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX27_5", + "CMT_TOP_OCLK_0", + "CMT_TOP_LH7_8", + "CMT_TOP_IMUX7_8", + "CMT_TOP_ICLK_0", + "CMT_TOP_NE4C0_13", + "CMT_LR_LOWER_B_MMCM_DO1", + "CMT_TOP_WW2END2_3", + "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "CMT_TOP_WR1END0_10", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END1_5", + "CMT_TOP_IMUX44_6", + "CMT_TOP_EE4B1_14", + "CMT_TOP_IMUX22_3", + "CMT_TOP_NE4C2_4", + "CMT_TOP_IMUX8_12", + "CMT_TOP_WL1END1_2", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_CTRL1_13", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX30_12", + "CMT_TOP_SE4C3_6", + "CMT_TOP_LH9_10", + "CMT_TOP_SE4C1_14", + "CMT_TOP_EE4C0_12", + "CMT_TOP_EE4C0_15", + "CMT_TOP_NW2A1_10", + "CMT_TOP_SW4A3_8", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW2A2_0", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX13_3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX28_4", + "CMT_TOP_WW4END0_15", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH1_8", + "CMT_TOP_LH10_10", + "CMT_TOP_IMUX42_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_BYP0_13", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_IMUX3_12", + "CMT_TOP_WL1END1_1", + "CMT_TOP_IMUX40_14", + "CMT_TOP_SE4BEG1_15", + "CMT_TOP_LH2_14", + "CMT_TOP_IMUX10_15", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_EE2A1_12", + "CMT_TOP_IMUX3_10", + "CMT_TOP_NE4BEG0_14", + "CMT_TOP_OCLK_12", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_WW2END2_8", + "CMT_TOP_EE2A0_15", + "CMT_TOP_EE2A0_8", + "CMT_TOP_LH7_1", + "CMT_TOP_SW2A3_5", + "CMT_TOP_IMUX31_11", + "CMT_TOP_IMUX5_14", + "CMT_TOP_IMUX32_12", + "CMT_LR_LOWER_B_MMCM_DI10", + "CMT_TOP_IMUX19_3", + "CMT_TOP_NW4END2_12", + "CMT_TOP_FAN0_7", + "CMT_TOP_WW2END1_4", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_NW4END3_7", + "CMT_TOP_NE4C3_14", + "CMT_TOP_EE2A3_12", + "CMT_TOP_CLK1_2", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_IMUX13_14", + "CMT_TOP_IMUX34_9", + "CMT_TOP_ICLK_14", + "CMT_TOP_EE4B0_6", + "CMT_TOP_EE4B2_5", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW4C2_9", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_WW2A2_2", + "CMT_TOP_SW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_12", + "CMT_TOP_NE2A3_2", + "CMT_TOP_IMUX43_1", + "CMT_TOP_WW4END2_10", + "CMT_TOP_EE4C1_4", + "CMT_TOP_IMUX44_9", + "CMT_TOP_WW4B1_6", + "CMT_TOP_NW4A1_11", + "CMT_TOP_IMUX42_0", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_IMUX18_13", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_IMUX24_7", + "CMT_TOP_EE4B0_12", + "CMT_LR_LOWER_B_MMCM_DI12", + "CMT_TOP_IMUX47_4", + "CMT_TOP_WW4END2_15", + "CMT_TOP_WL1END1_12", + "CMT_TOP_NE2A1_2", + "CMT_MMCM_PHASERREF0", + "CMT_TOP_IMUX39_4", + "CMT_TOP_BYP5_2", + "CMT_TOP_EL1BEG2_14", + "CMT_TOP_FAN7_8", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EL1BEG1_13", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_SW2A1_10", + "CMT_TOP_BYP4_15", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_LH7_15", + "CMT_TOP_IMUX33_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT52", + "CMT_TOP_NE4C1_1", + "CMT_TOP_NE4C3_8", + "CMT_TOP_EE4A3_10", + "CMT_TOP_IMUX28_3", + "CMT_TOP_BYP7_14", + "CMT_TOP_IMUX1_4", + "CMT_TOP_IMUX13_4", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_EE4B2_12", + "CMT_TOP_SW4END0_13", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_SW4END0_12", + "CMT_TOP_EE4B1_8", + "CMT_TOP_NE4BEG0_12", + "CMT_TOP_SW4A1_9", + "CMT_TOP_SE4C2_8", + "CMT_TOP_LH1_5", + "CMT_TOP_IMUX10_14", + "CMT_TOP_WW4END3_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_WW2END3_3", + "CMT_TOP_EE4BEG3_13", + "CMT_TOP_NE2A2_14", + "CMT_TOP_WL1END3_12", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_NE4C0_2", + "CMT_TOP_IMUX44_12", + "CMT_TOP_FAN6_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_IMUX19_10", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_LH7_5", + "CMT_TOP_WW4A2_15", + "CMT_TOP_LOGIC_OUTS_L_B1_12", + "CMT_TOP_IMUX19_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_FAN0_2", + "CMT_TOP_FAN6_0", + "CMT_TOP_IMUX47_5", + "CMT_TOP_IMUX27_3", + "CMT_TOP_IMUX24_0", + "CMT_TOP_IMUX26_0", + "CMT_TOP_EL1BEG0_13", + "CMT_TOP_WR1END2_3", + "CMT_TOP_EE4A0_12", + "CMT_TOP_WR1END1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_NE4C0_6", + "CMT_TOP_EE4C0_0", + "CMT_TOP_LOGIC_OUTS_L_B7_13", + "CMT_TOP_IMUX21_14", + "CMT_TOP_LOGIC_OUTS_L_B16_13", + "CMT_TOP_EE2A3_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT62", + "CMT_TOP_SE4C1_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT17", + "CMT_TOP_EE2A0_2", + "CMT_LR_LOWER_B_MMCM_DO11", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_EE2A1_14", + "CMT_TOP_IMUX47_9", + "CMT_TOP_SE4C1_7", + "CMT_TOP_FAN0_10", + "CMT_TOP_EE2A3_4", + "CMT_TOP_IMUX45_7", + "CMT_TOP_ER1BEG2_10", + "CMT_TOP_IMUX13_0", + "CMT_TOP_WW2END1_10", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_IMUX29_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_IMUX33_9", + "CMT_TOP_SW4END3_1", + "CMT_TOP_IMUX26_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT33", + "CMT_TOP_IMUX5_5", + "CMT_TOP_NE4BEG3_12", + "CMT_TOP_SW4END2_13", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_NW4A1_9", + "CMT_TOP_WW2END0_11", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4C0_8", + "CMT_TOP_IMUX16_10", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_IMUX15_4", + "CMT_TOP_LH10_11", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_NW2A2_9", + "CMT_TOP_EE4B3_11", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_WW4A1_1", + "CMT_TOP_EE2A1_0", + "CMT_TOP_LH9_9", + "CMT_TOP_IMUX25_14", + "CMT_TOP_EE4B0_1", + "CMT_TOP_WL1END2_12", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_WW2END0_12", + "CMT_TOP_EE4B3_13", + "CMT_TOP_SE2A0_10", + "CMT_LR_LOWER_B_MMCM_DI7", + "CMT_TOP_BLOCK_OUTS_L_B1_15", + "CMT_TOP_BLOCK_OUTS_L_B3_12", + "CMT_TOP_NE4C2_3", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE2BEG0_12", + "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "CMT_TOP_CLK0_3", + "CMT_TOP_IMUX14_1", + "CMT_TOP_LH8_9", + "CMT_TOP_WW2A3_11", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_SE4C1_12", + "CMT_TOP_IMUX2_7", + "CMT_TOP_CLK1_6", + "CMT_TOP_LOGIC_OUTS_L_B8_15", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW4C3_6", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_EE4C0_4", + "CMT_TOP_IMUX28_8", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LH2_6", + "CMT_TOP_IMUX11_9", + "CMT_TOP_WW4A1_11", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "CMT_TOP_BYP4_8", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_MMCM_PHASER_IN_A_ICLK", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2BEG2_15", + "CMT_TOP_NW4END3_9", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LH12_7", + "CMT_TOP_WW2END1_7", + "CMT_TOP_FAN0_13", + "CMT_TOP_LH6_2", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX45_8", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_EE2A0_3", + "CMT_TOP_BLOCK_OUTS_L_B1_13", + "CMT_TOP_WW4B0_10", + "CMT_TOP_WW4END3_14", + "CMT_TOP_WW2END1_14", + "CMT_TOP_SW4A0_13", + "CMT_TOP_IMUX33_4", + "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "CMT_TOP_BYP1_11", + "CMT_TOP_IMUX41_15", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_WL1END0_11", + "CMT_TOP_SW2A0_5", + "CMT_TOP_EE4C3_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT22", + "CMT_TOP_CLK1_13", + "CMT_TOP_IMUX35_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_WW2A3_10", + "CMT_TOP_LOGIC_OUTS_L_B2_13", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_EE4B0_13", + "CMT_TOP_NW4END1_7", + "CMT_MMCM_PHASERA_DQSBUS0", + "CMT_TOP_IMUX36_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_SW4END3_2", + "CMT_TOP_WL1END0_5", + "CMT_TOP_ER1BEG2_14", + "CMT_TOP_WW2A0_15", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_IMUX35_13", + "CMT_TOP_WW4END0_13", + "CMT_TOP_SW2A1_5", + "CMT_TOP_IMUX33_6", + "CMT_TOP_EE4C2_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT35", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_EE4B3_3", + "CMT_TOP_IMUX35_14", + "CMT_TOP_WW4A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_LH5_12", + "CMT_TOP_IMUX3_13", + "CMT_TOP_WW2END2_1", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_WW4END0_11", + "CMT_TOP_WR1END1_13", + "CMT_TOP_IMUX25_4", + "CMT_TOP_IMUX2_9", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_SW4END1_0", + "CMT_TOP_EE2A1_1", + "CMT_TOP_SE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_NE2A1_14", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_LOGIC_OUTS_L_B14_13", + "CMT_LR_LOWER_B_MMCM_PSEN", + "CMT_TOP_EE4A3_6", + "CMT_TOP_NE2A2_7", + "CMT_L_LOWER_B_CLK_IN1_HCLK", + "CMT_LR_LOWER_B_MMCM_TESTOUT54", + "CMT_TOP_SE4C2_11", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_BYP2_11", + "CMT_TOP_WW4C3_13", + "CMT_TOP_BYP1_1", + "CMT_TOP_LH11_6", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_NW2A0_11", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WR1END0_3", + "CMT_MMCM_PHASER_OUT_B_OCLK1X_90", + "CMT_TOP_LOGIC_OUTS_L_B1_14", + "CMT_TOP_EE4A1_13", + "CMT_TOP_WW4B3_5", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_IMUX31_9", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_LR_LOWER_B_MMCM_DI5", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_BYP6_0", + "CMT_TOP_SW4END2_12", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_IMUX36_6", + "CMT_TOP_EE2A2_13", + "CMT_TOP_WR1END1_6", + "CMT_TOP_LOGIC_OUTS_L_B17_13", + "CMT_TOP_SE4C0_2", + "CMT_TOP_LH11_10", + "CMT_TOP_EE4A2_8", + "CMT_TOP_SE2A1_1", + "CMT_TOP_NW4END1_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_IMUX31_3", + "CMT_TOP_EE4C1_8", + "CMT_TOP_IMUX20_11", + "CMT_TOP_EE2BEG2_14", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_WW4END1_4", + "CMT_TOP_FAN6_14", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX36_13", + "CMT_TOP_NW2A2_12", + "CMT_TOP_IMUX9_10", + "CMT_TOP_SW4A1_5", + "CMT_TOP_SE4C0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_LR_LOWER_B_MMCM_TESTIN1", + "MMCM_CLK_FREQ_BB_REBUF1_NS", + "CMT_TOP_ER1BEG3_14", + "CMT_TOP_SW2A1_0", + "CMT_TOP_SE4BEG1_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT47", + "CMT_TOP_EE2A0_0", + "CMT_TOP_CTRL1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_NE4C3_15", + "CMT_TOP_WW4A1_2", + "CMT_TOP_WW4C3_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_LH5_15", + "CMT_TOP_IMUX5_9", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_IMUX38_2", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_IMUX1_11", + "CMT_TOP_IMUX22_13", + "CMT_TOP_IMUX35_10", + "CMT_TOP_EE4A3_0", + "CMT_TOP_WW2A3_6", + "CMT_TOP_NW2A3_1", + "CMT_TOP_BYP3_5", + "CMT_TOP_BYP6_11", + "CMT_TOP_SW2A3_4", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX42_8", + "CMT_TOP_SE4C1_13", + "CMT_TOP_IMUX30_2", + "CMT_TOP_IMUX45_1", + "CMT_TOP_WW4B3_0", + "CMT_LR_LOWER_B_MMCM_PSCLK", + "CMT_MMCM_PHASER_OUT_A_OCLK", + "CMT_TOP_LOGIC_OUTS_L_B2_12", + "CMT_TOP_LH3_6", + "CMT_TOP_LH12_12", + "CMT_TOP_IMUX12_0", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_ER1BEG3_13", + "CMT_TOP_IMUX11_0", + "CMT_TOP_NW4A2_15", + "CMT_TOP_IMUX24_3", + "CMT_TOP_EE2BEG2_12", + "CMT_TOP_EE4B2_10", + "CMT_LR_LOWER_B_MMCM_TESTIN9", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX24_2", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_SE4BEG2_12", + "CMT_TOP_LH3_0", + "CMT_TOP_LOGIC_OUTS_L_B22_13", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_WW2A1_1", + "CMT_TOP_LH2_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT58", + "CMT_TOP_IMUX22_2", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX2_8", + "CMT_TOP_LH3_15", + "CMT_TOP_IMUX22_9", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_OCLKDIV_12", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_NW2A2_13", + "CMT_TOP_ICLK_10", + "CMT_TOP_LOGIC_OUTS_L_B18_14", + "CMT_TOP_SE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_LH2_11", + "CMT_TOP_SW4END1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_TOP_NE4C2_15", + "CMT_TOP_WL1END1_4", + "CMT_LR_LOWER_B_MMCM_PSDONE", + "CMT_TOP_IMUX37_9", + "CMT_TOP_FAN0_14", + "CMT_TOP_EE2A2_10", + "CMT_TOP_WW4C3_9", + "CMT_TOP_SE2A0_15", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP6_12", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH7_11", + "CMT_LR_LOWER_B_MMCM_TESTIN12", + "CMT_TOP_IMUX42_12", + "MMCM_CLK_FREQ_BB_REBUF3_NS", + "CMT_LR_LOWER_B_MMCM_DCLK", + "CMT_TOP_EE4A0_7", + "CMT_TOP_EE2BEG0_13", + "CMT_TOP_EE4A0_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_EE4B1_5", + "CMT_TOP_CLK1_12", + "CMT_TOP_NE2A0_15", + "CMT_TOP_WW2A2_13", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_IMUX19_1", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_NE4BEG3_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT20", + "CMT_TOP_WW4B2_10", + "CMT_TOP_IMUX17_3", + "CMT_TOP_NW4A0_1", + "CMT_TOP_EE4A1_12", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX36_0", + "CMT_TOP_WW4A1_12", + "CMT_TOP_WW2A2_7", + "CMT_TOP_IMUX33_8", + "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "CMT_TOP_SW4END2_8", + "CMT_TOP_NE4C3_7", + "CMT_TOP_CLK1_9", + "CMT_TOP_WW4C2_7", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LH6_13", + "CMT_TOP_NW2A2_2", + "CMT_LR_LOWER_B_MMCM_TESTOUT0", + "CMT_TOP_EE2BEG3_14", + "CMT_TOP_LH11_12", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW4END0_5", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_BYP3_2", + "CMT_TOP_NW4END2_1", + "CMT_TOP_IMUX15_0", + "CMT_TOP_IMUX45_3", + "CMT_TOP_NW4A1_10", + "CMT_TOP_IMUX33_10", + "CMT_TOP_SE4C0_6", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_LH1_9", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH10_4", + "CMT_TOP_NE2A0_13", + "CMT_TOP_SE4C2_7", + "CMT_TOP_WW4A0_12", + "CMT_TOP_IMUX32_3", + "CMT_TOP_EE4A1_15", + "CMT_TOP_IMUX16_9", + "CMT_TOP_EE4BEG0_14", + "CMT_TOP_IMUX3_11", + "CMT_TOP_BYP5_1", + "CMT_TOP_IMUX12_15", + "CMT_TOP_CTRL1_14", + "CMT_TOP_IMUX23_13", + "CMT_TOP_NE4C2_12", + "CMT_TOP_WW2A1_7", + "CMT_TOP_IMUX9_12", + "CMT_TOP_IMUX17_5", + "CMT_TOP_BYP2_2", + "CMT_TOP_LH1_6", + "CMT_TOP_SW4A1_11", + "CMT_LR_LOWER_B_MMCM_TESTIN6", + "CMT_TOP_IMUX40_12", + "CMT_TOP_IMUX12_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_WR1END3_15", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX13_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_NW2A1_9", + "CMT_MMCM_PHASER_OUT_B_OCLK", + "CMT_TOP_IMUX36_14", + "CMT_TOP_SE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B6_15", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_14", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_EE4C0_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_NE4C2_0", + "CMT_TOP_IMUX1_7", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX21_5", + "CMT_TOP_ER1BEG0_12", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH12_3", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_EE4C2_15", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_13", + "CMT_TOP_LH5_14", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LH12_8", + "CMT_TOP_LOGIC_OUTS_L_B1_13", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_NW4END1_12", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_CTRL0_8", + "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "CMT_TOP_NW4A3_7", + "CMT_LR_LOWER_B_MMCM_TESTIN16", + "CMT_TOP_NW4END3_0", + "CMT_TOP_NE2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_WW4A2_12", + "CMT_TOP_IMUX20_8", + "CMT_TOP_WW2END0_8", + "CMT_TOP_LH9_3", + "CMT_TOP_SW4END0_15", + "CMT_TOP_IMUX29_9", + "CMT_TOP_LH6_4", + "CMT_TOP_ICLK_15", + "CMT_TOP_EE4C1_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT32", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_WW2A2_10", + "CMT_TOP_FAN2_12", + "CMT_TOP_BLOCK_OUTS_L_B2_13", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_SE4C2_15", + "CMT_TOP_NE4C3_0", + "CMT_TOP_SW2A0_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT18", + "CMT_TOP_BYP6_5", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_WL1END0_6", + "CMT_TOP_LOGIC_OUTS_L_B12_14", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_IMUX29_14", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_IMUX15_6", + "CMT_TOP_WR1END3_13", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_MONITOR_N_14", + "CMT_TOP_IMUX36_2", + "CMT_TOP_FAN1_3", + "CMT_TOP_LH9_0", + "CMT_TOP_WL1END0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_WR1END3_6", + "CMT_TOP_LOGIC_OUTS_L_B2_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT29", + "CMT_TOP_NE2A3_3", + "CMT_TOP_SW4A2_10", + "CMT_TOP_WR1END2_10", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX26_6", + "CMT_TOP_FAN3_13", + "CMT_TOP_SE4C0_12", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_WW4B3_14", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_NW4A1_13", + "CMT_TOP_IMUX29_0", + "CMT_TOP_WR1END2_0", + "CMT_TOP_SW2A3_6", + "CMT_MMCM_A_WRCLK_TOFIFO", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX43_9", + "CMT_TOP_IMUX8_10", + "CMT_TOP_NW4A2_13", + "CMT_TOP_BYP3_3", + "CMT_MMCM_PHASERREF_ABOVE1", + "CMT_TOP_WW2A2_3", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX44_0", + "CMT_TOP_WW4C1_1", + "CMT_TOP_IMUX15_12", + "CMT_TOP_EE4A1_7", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW2A1_3", + "CMT_TOP_IMUX4_15", + "CMT_TOP_IMUX39_5", + "CMT_TOP_LH1_0", + "CMT_TOP_EE4BEG2_14", + "CMT_TOP_IMUX28_5", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_NE2A1_7", + "CMT_TOP_IMUX41_10", + "CMT_TOP_WR1END3_5", + "CMT_TOP_IMUX37_10", + "CMT_TOP_IMUX23_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX15_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT28", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_SW4A0_7", + "CMT_TOP_NW4A0_15", + "CMT_TOP_WW4A3_14", + "CMT_TOP_LH12_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT55", + "CMT_TOP_WW4A2_11", + "CMT_TOP_FAN2_14", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_WW4END1_13", + "CMT_TOP_WW4A1_7", + "CMT_TOP_LH4_14", + "CMT_TOP_IMUX45_14", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_BYP0_12", + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX5_3", + "CMT_TOP_IMUX24_15", + "CMT_TOP_WW4A3_2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_LH7_7", + "CMT_TOP_WW4C0_7", + "CMT_TOP_EE2BEG1_14", + "CMT_TOP_BYP4_13", + "CMT_L_LOWER_B_CLK_MMCM10", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_IMUX39_11", + "CMT_TOP_BYP5_4", + "CMT_TOP_FAN4_3", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_FAN6_2", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH4_5", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SW2A0_12", + "CMT_TOP_WR1END2_4", + "CMT_TOP_LH9_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_CTRL0_15", + "CMT_TOP_SE4BEG0_3", + "CMT_LR_LOWER_B_MMCM_TESTIN15", + "CMT_TOP_EE4C3_0", + "CMT_TOP_BYP4_9", + "CMT_TOP_NE4C1_6", + "CMT_TOP_NW4END2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_14", + "CMT_TOP_BYP2_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT61", + "CMT_TOP_WW2A0_10", + "CMT_TOP_IMUX7_11", + "CMT_TOP_WW4END0_0", + "CMT_TOP_BYP5_13", + "CMT_TOP_NE4C0_12", + "CMT_TOP_BLOCK_OUTS_L_B0_14", + "CMT_TOP_EE2A2_7", + "CMT_TOP_LH2_1", + "CMT_TOP_MONITOR_N_12", + "CMT_TOP_NW4END3_12", + "CMT_TOP_WW4END3_7", + "CMT_TOP_WW2END2_13", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_WW4B2_12", + "CMT_TOP_EE2BEG0_9", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX4_12", + "CMT_TOP_LH11_5", + "CMT_TOP_WW4C2_15", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_WW4C1_5", + "CMT_TOP_BYP5_8", + "CMT_TOP_LOGIC_OUTS_L_B14_14", + "CMT_TOP_WR1END2_11", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_8", + "CMT_TOP_LH6_14", + "CMT_TOP_LOGIC_OUTS_L_B9_15", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_WL1END1_7", + "CMT_TOP_WL1END1_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_NW4A1_15", + "CMT_TOP_FAN6_13", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_IMUX14_13", + "CMT_TOP_NW4A3_6", + "CMT_TOP_LH6_7", + "CMT_TOP_WW4B1_8", + "CMT_L_LOWER_B_CLK_MMCM0", + "CMT_TOP_EE4BEG1_15", + "CMT_TOP_WW4A3_0", + "CMT_TOP_FAN3_7", + "CMT_TOP_IMUX14_14", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_SW2A2_10", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT38", + "CMT_TOP_IMUX25_5", + "CMT_TOP_CLK0_4", + "CMT_TOP_EE2A0_14", + "CMT_TOP_NW2A0_9", + "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "CMT_TOP_CLK0_13", + "CMT_TOP_FAN5_3", + "CMT_TOP_EE4A1_4", + "CMT_TOP_IMUX31_6", + "CMT_TOP_NE2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_IMUX38_7", + "CMT_LR_LOWER_B_MMCM_DO12", + "CMT_TOP_LH4_15", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_LH5_13", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_NE2A1_12", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_LR_LOWER_B_CLKFBOUT2IN", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_ICLK_7", + "CMT_TOP_LOGIC_OUTS_L_B5_13", + "CMT_TOP_IMUX15_3", + "CMT_TOP_FAN1_9", + "CMT_TOP_FAN2_3", + "CMT_PHASER_A_ICLKDIV_TOIOI", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_SW4A0_4", + "CMT_TOP_NW2A0_14", + "CMT_TOP_LH11_9", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_IMUX8_3", + "CMT_LR_LOWER_B_MMCM_DEN", + "CMT_TOP_NW4END2_15", + "CMT_TOP_WW4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_EE4C2_11", + "CMT_TOP_NE4C3_1", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CTRL0_3", + "CMT_TOP_FAN0_8", + "CMT_TOP_EE4C2_7", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_SW4A1_1", + "CMT_TOP_NW2A1_13", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_NW4END2_10", + "CMT_TOP_IMUX16_12", + "CMT_TOP_IMUX35_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT27", + "CMT_TOP_IMUX9_6", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX31_8", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX28_7", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LH8_15", + "CMT_TOP_LOGIC_OUTS_L_B16_14", + "CMT_TOP_IMUX2_15", + "CMT_TOP_BYP2_13", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_SW4END2_15", + "CMT_TOP_IMUX41_1", + "CMT_TOP_SW2A3_7", + "CMT_TOP_LH4_9", + "CMT_TOP_SE4BEG2_15", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_SE2A3_13", + "CMT_TOP_NW2A3_9", + "CMT_TOP_SE2A1_15", + "CMT_TOP_EE4B3_4", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_IMUX24_4", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_FAN6_6", + "CMT_TOP_IMUX25_2", + "CMT_TOP_SW4A2_13", + "CMT_TOP_BYP2_3", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_FAN4_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_SW4A3_14", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_NW4A1_3", + "CMT_TOP_IMUX35_4", + "CMT_TOP_WW2END3_10", + "CMT_TOP_IMUX41_5", + "CMT_TOP_NW4A1_8", + "CMT_TOP_IMUX10_6", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_LH12_6", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_BYP6_10", + "CMT_LR_LOWER_B_MMCM_TESTIN7", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_IMUX12_7", + "CMT_TOP_OCLKDIV_13", + "CMT_TOP_FAN1_14", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_15", + "CMT_TOP_BYP7_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_IMUX5_12", + "CMT_TOP_SW4A2_1", + "CMT_TOP_LH1_3", + "CMT_TOP_FAN0_5", + "CMT_TOP_EE2A1_8", + "CMT_TOP_WW4C3_7", + "CMT_TOP_WW4A0_13", + "CMT_TOP_LH2_3", + "CMT_TOP_IMUX27_14", + "CMT_TOP_FAN7_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_NE2A0_12", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT16", + "CMT_TOP_NW4A3_0", + "CMT_TOP_EE4B1_10", + "CMT_TOP_LH9_12", + "CMT_TOP_WW4END2_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX38_4", + "CMT_TOP_WW4C1_15", + "CMT_TOP_NE2A1_4", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_IMUX27_2", + "CMT_TOP_WW4C0_6", + "CMT_LR_LOWER_B_MMCM_DI3", + "CMT_TOP_IMUX1_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_NE2A2_5", + "CMT_TOP_NW4A0_3", + "CMT_TOP_LOGIC_OUTS_L_B4_12", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_IMUX44_13", + "CMT_TOP_EE4BEG3_12", + "CMT_TOP_NW2A3_6", + "CMT_TOP_WW4END3_5", + "CMT_TOP_IMUX34_12", + "CMT_TOP_WW4B1_5", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX23_10", + "CMT_TOP_CTRL1_15", + "CMT_TOP_IMUX17_0", + "CMT_TOP_CLK0_2", + "CMT_TOP_EE4B3_2", + "CMT_TOP_IMUX31_5", + "CMT_TOP_FAN0_0", + "CMT_TOP_EE4C3_2", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX46_3", + "CMT_TOP_IMUX43_7", + "CMT_TOP_IMUX40_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_EE4A3_9", + "CMT_TOP_WW4END3_6", + "CMT_TOP_FAN2_5", + "CMT_TOP_CLK0_6", + "CMT_LR_LOWER_B_MMCM_TESTIN27", + "CMT_TOP_IMUX10_5", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_WW2A3_8", + "CMT_TOP_NE4C1_8", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX5_13", + "CMT_TOP_WW4A3_12", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4C0_4", + "CMT_TOP_BYP0_6", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX12_4", + "CMT_TOP_LH10_3", + "CMT_TOP_LH3_2", + "CMT_TOP_IMUX11_15", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LOGIC_OUTS_L_B9_14", + "MMCMOUT_CLK_FREQ_BB_3", + "CMT_LR_LOWER_B_MMCM_DO13", + "CMT_TOP_IMUX43_4", + "CMT_TOP_LH10_6", + "CMT_TOP_SE4C0_15", + "CMT_TOP_NE4C1_10", + "CMT_TOP_IMUX15_11", + "CMT_TOP_NE4C1_9", + "CMT_TOP_WW4B0_3", + "CMT_TOP_NE2A1_15", + "CMT_TOP_WW4C3_10", + "CMT_TOP_SE2A2_6", + "CMT_TOP_NW2A3_5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_EE4BEG0_13", + "CMT_LR_LOWER_B_MMCM_DADDR3", + "CMT_TOP_LH9_14", + "CMT_TOP_LH1_15", + "CMT_TOP_WW4A2_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_LH10_15", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_SW2A1_12", + "CMT_TOP_IMUX38_11", + "CMT_TOP_SE4C2_13", + "CMT_TOP_SW4END2_9", + "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_CTRL0_14", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_LH3_1", + "CMT_TOP_LOGIC_OUTS_L_B3_13", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END2_5", + "CMT_TOP_FAN0_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_EE2BEG3_15", + "CMT_TOP_IMUX42_11", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX4_5", + "CMT_TOP_LOGIC_OUTS_L_B13_14", + "CMT_TOP_BYP4_0", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LH4_4", + "CMT_TOP_LH3_9", + "CMT_TOP_SE4BEG3_15", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_EL1BEG2_9", + "MMCM_CLK_FREQ_BB_NS3", + "CMT_TOP_WW4C1_2", + "CMT_TOP_IMUX37_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT40", + "CMT_TOP_IMUX17_14", + "CMT_TOP_WR1END1_0", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_IMUX22_5", + "CMT_MMCM_PHASER_IN_B_ICLK", + "CMT_LR_LOWER_B_MMCM_TESTOUT42", + "CMT_TOP_OCLK_3", + "CMT_TOP_IMUX23_5", + "CMT_TOP_SW4END2_4", + "CMT_TOP_IMUX37_12", + "CMT_TOP_EE4A1_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT26", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW2END0_2", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_WW4A0_15", + "CMT_TOP_SE2A1_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT48", + "CMT_TOP_NE4BEG1_14", + "CMT_TOP_NW2A3_13", + "CMT_TOP_BLOCK_OUTS_L_B2_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT30", + "CMT_TOP_CTRL0_1", + "CMT_LR_LOWER_B_MMCM_DO9", + "CMT_LR_LOWER_B_MMCM_TESTOUT41", + "CMT_TOP_NE2A1_10", + "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "CMT_TOP_WW2END0_9", + "CMT_L_LOWER_B_CLK_MMCM2", + "CMT_LR_LOWER_B_MMCM_TESTOUT23", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_WW4B0_0", + "CMT_TOP_LH7_12", + "CMT_TOP_EL1BEG1_15", + "CMT_TOP_IMUX6_5", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_WW4B0_4", + "CMT_TOP_IMUX10_9", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_IMUX26_13", + "CMT_TOP_IMUX45_0", + "CMT_TOP_WW4END2_13", + "CMT_TOP_IMUX45_10", + "CMT_TOP_IMUX39_1", + "CMT_TOP_WW4B3_15", + "CMT_TOP_WL1END1_8", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WW2END3_8", + "CMT_TOP_IMUX9_5", + "CMT_TOP_BYP4_10", + "CMT_TOP_WW4C2_12", + "CMT_TOP_IMUX17_9", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_IMUX23_4", + "CMT_TOP_IMUX32_15", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_FAN3_10", + "CMT_TOP_EE4B0_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_SW2A3_15", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX42_9", + "CMT_TOP_IMUX38_12", + "CMT_TOP_EE2A2_6", + "CMT_TOP_IMUX25_3", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_EL1BEG2_13", + "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "CMT_TOP_LOGIC_OUTS_L_B11_15", + "CMT_TOP_NE4BEG2_14", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WR1END1_12", + "CMT_TOP_CLK0_15", + "CMT_TOP_IMUX28_15", + "CMT_TOP_IMUX34_4", + "CMT_TOP_LH7_2", + "CMT_TOP_LH6_1", + "CMT_TOP_NW4END2_2", + "CMT_TOP_IMUX37_13", + "CMT_TOP_LH1_2", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_NE2A2_13", + "CMT_TOP_NW2A2_14", + "CMT_TOP_IMUX13_2", + "CMT_TOP_WW4A0_8", + "CMT_TOP_FAN6_8", + "CMT_TOP_IMUX17_7", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_NW4A0_2", + "CMT_TOP_BYP6_6", + "CMT_TOP_SE4C0_14", + "CMT_TOP_WW4C1_13", + "CMT_TOP_WW4B2_15", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_LR_LOWER_B_MMCM_DI15", + "CMT_TOP_SW4END1_7", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NW4END0_6", + "CMT_TOP_WR1END3_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_IMUX6_14", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_ER1BEG0_14", + "CMT_TOP_NE2A3_7", + "CMT_TOP_EE4A1_14", + "CMT_TOP_IMUX3_7", + "CMT_TOP_WW4B1_13", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_TOP_BYP2_6", + "CMT_TOP_IMUX14_8", + "CMT_TOP_WW4C1_14", + "CMT_TOP_NE4C0_0", + "CMT_TOP_BYP0_3", + "CMT_TOP_NE4C2_10", + "CMT_TOP_SE2A2_12", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH6_11", + "CMT_TOP_FAN5_10", + "CMT_TOP_WL1END2_14", + "CMT_TOP_EE2A2_15", + "CMT_TOP_WW4END2_4", + "CMT_LR_LOWER_B_MMCM_TESTIN21", + "CMT_TOP_EE4C3_12", + "CMT_TOP_NW2A3_11", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT2", + "CMT_TOP_IMUX41_14", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE4A2_15", + "CMT_TOP_NW2A2_8", + "MMCM_CLK_FREQ_BB_NS0", + "CMT_TOP_WR1END1_14", + "CMT_TOP_IMUX19_4", + "CMT_L_LOWER_B_CLK_MMCM5", + "CMT_TOP_WW2END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_SW2A3_14", + "CMT_TOP_FAN2_13", + "CMT_TOP_IMUX30_4", + "CMT_TOP_SW2A0_14", + "CMT_TOP_SE4BEG0_13", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX28_1", + "CMT_TOP_NW4A0_0", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_LH3_7", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX16_4", + "CMT_LR_LOWER_B_MMCM_TESTIN2", + "CMT_TOP_EE2A3_7", + "CMT_TOP_SE4C3_11", + "CMT_TOP_ICLK_9", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_WW4A1_10", + "CMT_TOP_WW2END0_0", + "CMT_TOP_NW4A2_12", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_WW4C3_11", + "CMT_TOP_BYP3_6", + "CMT_TOP_NE4BEG2_10", + "CMT_MMCM_A_WREN_TOFIFO", + "CMT_TOP_WW2A2_8", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_WW4B3_7", + "CMT_PHASER_A_OCLKDIV_TOIOI", + "CMT_TOP_SW4END3_4", + "CMT_TOP_EE2BEG3_13", + "CMT_TOP_EE4C1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_IMUX20_12", + "CMT_TOP_BYP0_8", + "CMT_TOP_WW4A0_14", + "CMT_TOP_FAN3_14", + "CMT_TOP_IMUX1_13", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_L_LOWER_B_CLK_PERF3", + "CMT_TOP_WW4END1_7", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WW4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_SE4BEG0_12", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX5_0", + "CMT_TOP_WW4B3_10", + "CMT_TOP_IMUX9_13", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_WW2END3_9", + "CMT_TOP_SW4END1_10", + "CMT_TOP_WW4B0_7", + "CMT_TOP_BYP3_7", + "CMT_TOP_EE2A3_11", + "CMT_TOP_IMUX43_13", + "CMT_TOP_LH6_5", + "CMT_TOP_IMUX28_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_WW4A3_5", + "CMT_TOP_EL1BEG0_12", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_BLOCK_OUTS_L_B3_14", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_NW2A1_14", + "CMT_MMCM_A_RDEN_TOFIFO", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_WL1END0_3", + "CMT_TOP_WW4C0_2", + "CMT_TOP_IMUX0_7", + "CMT_TOP_WW4B1_0", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_EE4C2_14", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SW4END0_8", + "CMT_TOP_EE4BEG3_14", + "CMT_TOP_WW4C2_10", + "CMT_TOP_IMUX8_1", + "CMT_TOP_EE4BEG3_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT24", + "CMT_TOP_IMUX38_15", + "CMT_TOP_IMUX34_6", + "CMT_TOP_IMUX32_11", + "CMT_TOP_NE2A3_1", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_EE4C1_12", + "CMT_MMCM_PHASERREF_ABOVE0", + "CMT_TOP_EE4B0_3", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A3_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_IMUX46_10", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_SW4A0_14", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C0_5", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_BYP4_4", + "CMT_TOP_NW4A2_9", + "CMT_TOP_WR1END2_1", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_IMUX15_15", + "CMT_TOP_IMUX16_1", + "CMT_TOP_NW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_L_LOWER_B_CLK_MMCM4", + "CMT_TOP_FAN2_6", + "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "CMT_TOP_WR1END3_7", + "CMT_TOP_IMUX23_12", + "CMT_TOP_IMUX38_9", + "CMT_TOP_IMUX36_12", + "CMT_TOP_IMUX28_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_FAN5_7", + "CMT_TOP_BYP7_10", + "CMT_TOP_IMUX15_7", + "CMT_TOP_BLOCK_OUTS_L_B3_13", + "CMT_TOP_IMUX13_12", + "CMT_TOP_LH8_5", + "CMT_TOP_IMUX30_9", + "CMT_TOP_EE4A3_5", + "CMT_PHASER_A_ICLK_TOIOI", + "CMT_TOP_WR1END2_15", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_NE4C0_5", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_IMUX25_0", + "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "CMT_TOP_IMUX31_13", + "CMT_TOP_IMUX31_10", + "CMT_TOP_BLOCK_OUTS_L_B0_15", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_SW4A0_12", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_NE4C1_13", + "CMT_TOP_IMUX34_2", + "CMT_TOP_EE4B2_14", + "CMT_TOP_LH10_2", + "CMT_TOP_SW4A2_12", + "CMT_TOP_SW4A1_15", + "CMT_LR_LOWER_B_MMCM_DI14", + "CMT_TOP_LH12_0", + "CMT_TOP_FAN4_0", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_NW4A0_8", + "CMT_TOP_WW4A2_10", + "CMT_TOP_BYP3_0", + "CMT_TOP_IMUX2_1", + "CMT_TOP_WW4END3_15", + "CMT_TOP_IMUX22_1", + "CMT_TOP_NW4END0_14", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_BLOCK_OUTS_L_B1_12", + "CMT_TOP_EE2A3_5", + "CMT_LR_LOWER_B_MMCM_TESTIN19", + "CMT_LR_LOWER_B_MMCM_TESTOUT5", + "CMT_TOP_OCLK1X_90_15", + "CMT_TOP_IMUX4_7", + "CMT_TOP_SE2A2_0", + "CMT_TOP_LH2_4", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SW4A3_6", + "CMT_TOP_NW4END1_5", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WR1END3_1", + "CMT_TOP_BYP1_0", + "CMT_TOP_EE2BEG1_12", + "CMT_TOP_WW2A0_6", + "CMT_TOP_SE2A3_0", + "CMT_LR_LOWER_B_MMCM_DADDR4", + "CMT_TOP_IMUX35_9", + "CMT_TOP_SW4END2_5", + "CMT_TOP_SE4C3_5", + "CMT_TOP_LH4_1", + "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "CMT_TOP_SW2A1_14", + "CMT_TOP_NW4A0_9", + "CMT_TOP_SW4A1_6", + "CMT_TOP_WL1END3_15", + "CMT_TOP_LH1_13", + "CMT_TOP_SW2A2_0", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE4C3_10", + "CMT_TOP_LOGIC_OUTS_L_B11_12", + "CMT_TOP_LOGIC_OUTS_L_B7_15", + "CMT_L_LOWER_B_CLK_MMCM9", + "CMT_TOP_SW4END0_7", + "CMT_TOP_EE4BEG1_12", + "CMT_LR_LOWER_B_MMCM_TESTIN18", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT8", + "CMT_TOP_IMUX13_5", + "CMT_TOP_SE2A1_13", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EE4A2_4", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_LH2_8", + "CMT_TOP_SE2A3_1", + "CMT_TOP_IMUX2_6", + "CMT_LR_LOWER_B_MMCM_TESTIN10", + "CMT_TOP_IMUX3_0", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_NE4C0_15", + "CMT_TOP_EE4C2_4", + "CMT_TOP_BYP6_13", + "CMT_TOP_NE4BEG1_5", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_EE2A3_2", + "CMT_TOP_IMUX14_10", + "CMT_TOP_IMUX23_8", + "CMT_TOP_WW4A3_8", + "CMT_TOP_IMUX40_6", + "CMT_TOP_IMUX24_12", + "CMT_LR_LOWER_B_MMCM_DI11", + "CMT_TOP_LH10_9", + "CMT_TOP_BYP3_12", + "CMT_TOP_NW2A3_14", + "CMT_TOP_WW2A1_15", + "CMT_TOP_FAN1_0", + "CMT_TOP_LH4_10", + "CMT_TOP_IMUX0_2", + "CMT_TOP_EL1BEG3_12", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_LH1_12", + "CMT_LR_LOWER_B_MMCM_DO6", + "CMT_TOP_LH5_3", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_NW2A0_3", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT36", + "CMT_TOP_IMUX18_1", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_IMUX42_13", + "CMT_TOP_NW4A3_14", + "CMT_TOP_SW4END3_10", + "CMT_TOP_FAN2_10", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_LOGIC_OUTS_L_B0_15", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_WR1END1_1", + "CMT_TOP_SW2A2_7", + "CMT_PHASER_A_OCLK90_TOIOI", + "CMT_TOP_ICLK_5", + "CMT_TOP_BYP0_14", + "CMT_TOP_SW2A0_7", + "CMT_TOP_FAN7_13", + "CMT_TOP_LH6_15", + "CMT_TOP_FAN6_5", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WW2A1_2", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_FAN4_1", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_IMUX19_13", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_ER1BEG1_13", + "CMT_TOP_SE4C0_11", + "CMT_TOP_BYP5_14", + "MMCM_CLK_FREQ_BB_NS1", + "CMT_TOP_WW2END0_6", + "CMT_TOP_CTRL1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_LR_LOWER_B_MMCM_TESTOUT46", + "CMT_TOP_BLOCK_OUTS_L_B1_14", + "CMT_TOP_WW4B1_14", + "CMT_TOP_WW4B1_2", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_NE4BEG3_15", + "CMT_TOP_FAN6_3", + "CMT_TOP_WL1END1_11", + "CMT_TOP_SW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_LOGIC_OUTS_L_B20_13", + "CMT_TOP_NW2A3_10", + "CMT_TOP_LH11_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_IMUX28_13", + "CMT_TOP_WW2END2_15", + "CMT_TOP_SE4C2_6", + "CMT_TOP_FAN5_11", + "CMT_TOP_IMUX39_12", + "CMT_TOP_SW4END1_6", + "CMT_TOP_IMUX2_2", + "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH6_0", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX29_3", + "MMCMOUT_CLK_FREQ_BB_0", + "CMT_TOP_WL1END1_6", + "CMT_TOP_IMUX0_13", + "CMT_TOP_NW4A2_5", + "CMT_TOP_IMUX6_9", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX9_2", + "CMT_TOP_IMUX19_5", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_SE4BEG3_13", + "CMT_TOP_EE4A1_9", + "CMT_TOP_EE4B3_9", + "CMT_TOP_IMUX3_14", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_NE2A3_4", + "CMT_TOP_EE2A0_11", + "CMT_TOP_IMUX40_3", + "CMT_TOP_SW2A3_12", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_EL1BEG2_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT60", + "CMT_TOP_ICLK_3", + "CMT_TOP_SW4END0_6", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_IMUX41_6", + "CMT_TOP_EE2BEG2_13", + "CMT_TOP_EE4A0_11", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_IMUX46_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_EE4C0_2", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX11_3", + "CMT_TOP_IMUX17_12", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_LH5_8", + "CMT_TOP_WW4A2_8", + "CMT_TOP_WW4A3_4", + "CMT_LR_LOWER_B_MMCM_CLKIN2", + "CMT_TOP_LH11_4", + "CMT_TOP_IMUX34_0", + "CMT_TOP_EE2A1_13", + "CMT_TOP_BYP1_6", + "CMT_TOP_WW4B0_1", + "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "CMT_TOP_NW4END0_15", + "CMT_TOP_WL1END0_12", + "CMT_TOP_IMUX2_4", + "CMT_TOP_SW4A1_8", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_SE4C3_15", + "CMT_TOP_WL1END3_10", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX29_7", + "CMT_TOP_IMUX33_3", + "CMT_TOP_SW4END3_12", + "CMT_TOP_SW2A2_3", + "CMT_TOP_FAN6_12", + "CMT_TOP_IMUX44_8", + "CMT_TOP_SW4A1_14", + "CMT_L_LOWER_B_CLK_MMCM1", + "CMT_TOP_IMUX32_7", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SW2A3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_OCLK_13", + "CMT_TOP_BLOCK_OUTS_L_B3_15", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX32_1", + "MMCMOUT_CLK_FREQ_BB_1", + "CMT_TOP_LH8_1", + "CMT_TOP_SE2A2_1", + "CMT_TOP_WW4B0_13", + "CMT_TOP_NW2A3_12", + "CMT_TOP_IMUX31_12", + "CMT_TOP_WW4C3_3", + "CMT_TOP_SE4C3_1", + "CMT_TOP_CTRL0_7", + "CMT_TOP_NW2A0_13", + "CMT_TOP_IMUX26_3", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_IMUX24_6", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_NE2A2_10", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_LR_LOWER_B_MMCM_TESTIN3", + "CMT_TOP_LOGIC_OUTS_L_B7_12", + "CMT_TOP_IMUX17_1", + "CMT_TOP_EE4C3_7", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NE2A2_15", + "CMT_TOP_CLK1_14", + "CMT_TOP_ICLK_6", + "CMT_LR_LOWER_B_MMCM_TESTIN17", + "CMT_TOP_SE2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_SE2A3_7", + "CMT_TOP_BYP6_9", + "CMT_TOP_EE4B2_3", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_WW2A0_8", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX30_10", + "CMT_TOP_SE2A2_15", + "CMT_TOP_WW4END0_9", + "CMT_TOP_SW4END0_5", + "CMT_TOP_IMUX0_3", + "CMT_TOP_IMUX27_10", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_SW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_IMUX40_13", + "CMT_TOP_CTRL1_1", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_IMUX29_12", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_IMUX12_11", + "CMT_TOP_WW4A3_10", + "CMT_TOP_FAN3_6", + "CMT_TOP_LH5_4", + "CMT_TOP_LOGIC_OUTS_L_B21_12", + "CMT_TOP_NE4C1_12", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_WW2END1_12", + "CMT_TOP_IMUX47_3", + "CMT_TOP_SW4A3_5", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_EE2A1_4", + "CMT_TOP_NW4END1_4", + "CMT_TOP_IMUX25_1", + "CMT_TOP_LH5_11", + "CMT_MMCM_PHASERA_DTSBUS0", + "CMT_TOP_FAN1_10", + "CMT_TOP_LH3_12", + "CMT_TOP_NW4END0_11", + "CMT_TOP_IMUX34_14", + "CMT_TOP_EE4C0_11", + "CMT_TOP_BLOCK_OUTS_L_B0_12", + "CMT_TOP_IMUX25_8", + "CMT_TOP_EE4A1_3", + "CMT_TOP_IMUX14_15", + "CMT_TOP_NW2A3_7", + "CMT_TOP_IMUX30_11", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_EE2A1_2", + "CMT_TOP_LOGIC_OUTS_L_B16_15", + "CMT_TOP_IMUX34_15", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WW4C0_12", + "CMT_TOP_WW4C2_8", + "CMT_TOP_EL1BEG3_14", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_LOGIC_OUTS_L_B15_14", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX26_11", + "CMT_LR_LOWER_B_MMCM_TESTIN13", + "CMT_TOP_NE2A2_1", + "CMT_TOP_CTRL1_8", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NW4END3_3", + "CMT_TOP_WW4B2_2", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX16_11", + "CMT_TOP_WW4A0_3", + "CMT_TOP_LH5_1", + "CMT_TOP_WL1END0_4", + "CMT_TOP_NW4A3_12", + "CMT_TOP_IMUX45_15", + "CMT_TOP_IMUX44_7", + "CMT_TOP_SW2A3_3", + "CMT_TOP_IMUX42_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT4", + "CMT_TOP_SE2A2_3", + "CMT_TOP_FAN6_10", + "CMT_TOP_SE4C2_4", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX19_14", + "CMT_TOP_NE4C1_3", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX18_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT19", + "CMT_TOP_BYP3_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_CLK1_5", + "CMT_TOP_SW2A0_4", + "CMT_TOP_IMUX0_10", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_LR_LOWER_B_MMCM_TESTIN8", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_WW2A0_14", + "CMT_TOP_IMUX13_7", + "CMT_TOP_IMUX26_14", + "CMT_TOP_NE4C2_2", + "CMT_TOP_IMUX10_4", + "CMT_TOP_EE4A1_11", + "CMT_TOP_EE2A0_6", + "CMT_TOP_NW4END1_0", + "CMT_TOP_LH5_10", + "CMT_TOP_IMUX46_7", + "CMT_TOP_LOGIC_OUTS_L_B10_13", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_WW4C2_2", + "CMT_TOP_IMUX17_15", + "CMT_TOP_LOGIC_OUTS_L_B4_13", + "CMT_TOP_EE2A2_8", + "CMT_TOP_OCLK_9", + "CMT_TOP_NW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_WW4END3_9", + "CMT_TOP_EE4C3_1", + "CMT_TOP_IMUX14_11", + "CMT_TOP_WW4C1_9", + "CMT_TOP_IMUX0_9", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_WL1END3_9", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_EE4A3_15", + "CMT_TOP_IMUX13_6", + "CMT_TOP_EE4A2_6", + "CMT_TOP_IMUX20_0", + "CMT_TOP_IMUX16_13", + "CMT_TOP_WW4B2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_WW2A0_1", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_FAN7_9", + "CMT_LR_LOWER_B_MMCM_LOCKED", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_FAN7_12", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LH5_7", + "CMT_TOP_IMUX21_9", + "CMT_TOP_IMUX35_1", + "CMT_TOP_IMUX47_12", + "CMT_LR_LOWER_B_MMCM_TESTIN0", + "CMT_TOP_LH11_14", + "CMT_TOP_EL1BEG2_15", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_NW2A3_8", + "CMT_TOP_SE2A3_4", + "CMT_TOP_SW4END3_9", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NE4C0_10", + "CMT_TOP_IMUX26_5", + "CMT_TOP_BYP4_11", + "CMT_MMCM_PHASERA_DTSBUS1", + "CMT_TOP_IMUX25_6", + "CMT_TOP_BYP0_2", + "CMT_TOP_BYP6_7", + "CMT_TOP_EE4BEG1_13", + "CMT_TOP_IMUX37_15", + "CMT_TOP_ICLK_12", + "CMT_L_LOWER_B_CLK_FREQ_BB0", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_IMUX30_15", + "CMT_TOP_NE2A1_8", + "CMT_TOP_WW4A0_10", + "CMT_TOP_SW2A0_13", + "CMT_TOP_BYP4_12", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_5", + "CMT_TOP_IMUX8_15", + "CMT_TOP_WW4B2_0", + "CMT_TOP_SE4BEG3_12", + "CMT_TOP_NE4C3_13", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_SW2A1_13", + "CMT_TOP_WW2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_SW2A2_13", + "CMT_TOP_WW4B0_15", + "CMT_TOP_WL1END3_0", + "CMT_L_LOWER_B_CLK_IN2_INT", + "CMT_TOP_WW4END0_3", + "CMT_TOP_MONITOR_N_13", + "CMT_TOP_NW4END0_1", + "CMT_TOP_IMUX12_10", + "CMT_TOP_LH6_6", + "CMT_TOP_NE4C3_5", + "CMT_TOP_FAN3_12", + "CMT_TOP_NW4END0_8", + "CMT_TOP_IMUX39_0", + "CMT_TOP_WW4END2_0", + "CMT_TOP_IMUX34_13", + "CMT_TOP_WW4B3_4", + "CMT_TOP_SE4BEG0_15", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_IMUX9_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT3", + "CMT_TOP_LH10_13", + "CMT_TOP_FAN2_0", + "CMT_TOP_SE2A3_15", + "CMT_TOP_IMUX29_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT43", + "CMT_LR_LOWER_B_MMCM_TESTOUT25", + "CMT_TOP_IMUX30_5", + "CMT_TOP_IMUX8_9", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_NW4END2_5", + "CMT_TOP_NE4C0_7", + "CMT_TOP_ER1BEG2_15", + "CMT_TOP_WW2END2_4", + "CMT_TOP_IMUX21_13", + "CMT_L_LOWER_B_CLK_FREQ_BB1", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_WL1END3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_FAN5_14", + "CMT_TOP_SW4A3_4", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NW2A0_2", + "CMT_TOP_IMUX17_6", + "CMT_TOP_IMUX7_0", + "CMT_TOP_SE2A1_2", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_IMUX20_2", + "CMT_TOP_LH8_7", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_WW4A2_5", + "CMT_TOP_NE4C1_11", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_OCLK_6", + "CMT_TOP_CTRL1_12", + "CMT_TOP_IMUX18_10", + "CMT_TOP_BYP4_7", + "CMT_TOP_LH2_2", + "CMT_TOP_BYP0_5", + "CMT_TOP_SE2A2_4", + "CMT_TOP_SE4C2_1", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B0_12", + "CMT_TOP_LH8_14", + "CMT_TOP_IMUX16_15", + "CMT_TOP_IMUX43_14", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_NW4END3_4", + "CMT_TOP_IMUX40_11", + "CMT_MMCM_PHASERREF_BELOW1", + "CMT_TOP_LH9_8", + "CMT_TOP_LOGIC_OUTS_L_B16_12", + "CMT_TOP_LH9_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT56", + "CMT_TOP_NE2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_LR_LOWER_B_MMCM_PWRDWN", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX28_11", + "CMT_TOP_LOGIC_OUTS_L_B6_12", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_LH3_10", + "CMT_MMCM_PHYCTRL_SYNC_BB_UP", + "CMT_TOP_IMUX42_7", + "CMT_TOP_IMUX5_10", + "CMT_TOP_WL1END3_8", + "CMT_TOP_IMUX29_13", + "CMT_TOP_IMUX17_2", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SE4BEG3_14", + "CMT_LR_LOWER_B_MMCM_DI13", + "CMT_TOP_IMUX2_10", + "CMT_TOP_EE4B2_15", + "CMT_TOP_SE2A0_6", + "CMT_TOP_EE2BEG1_13", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_SE4C1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_MONITOR_P_2", + "CMT_TOP_IMUX41_4", + "CMT_TOP_WL1END0_1", + "CMT_TOP_IMUX0_12", + "CMT_TOP_NW4END2_4", + "CMT_TOP_IMUX7_13", + "CMT_TOP_FAN5_1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_NW4A3_15", + "CMT_TOP_IMUX20_10", + "CMT_TOP_WR1END0_15", + "CMT_TOP_NE2A2_11", + "CMT_TOP_EE4BEG1_14", + "CMT_TOP_WW2A2_15", + "CMT_TOP_FAN5_2", + "CMT_TOP_SW2A3_9", + "CMT_TOP_NW2A1_1", + "CMT_TOP_FAN1_1", + "CMT_TOP_IMUX5_7", + "CMT_TOP_NE2A3_15", + "CMT_TOP_IMUX11_11", + "CMT_TOP_NE2A1_5", + "CMT_TOP_CLK1_0", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_SW4END1_11", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_LOGIC_OUTS_L_B10_14", + "CMT_TOP_IMUX28_9", + "CMT_TOP_NW4A1_4", + "CMT_TOP_NE4C2_5", + "CMT_TOP_NE4C0_14", + "CMT_TOP_FAN1_15", + "CMT_TOP_WW4B2_8", + "CMT_TOP_LOGIC_OUTS_L_B8_13", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_WW4END3_13", + "CMT_TOP_WR1END2_13", + "MMCM_CLK_FREQ_BB_REBUF0_NS", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_IMUX6_13", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_WW4B2_6", + "CMT_TOP_LOGIC_OUTS_L_B23_13", + "CMT_TOP_WW2END1_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT21", + "CMT_TOP_IMUX19_0", + "CMT_TOP_BLOCK_OUTS_L_B2_15", + "CMT_TOP_SW4END2_14", + "CMT_TOP_IMUX28_14", + "CMT_TOP_LH3_3", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX31_2", + "CMT_TOP_LOGIC_OUTS_L_B22_15", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_LH4_2", + "CMT_TOP_SE2A0_11", + "CMT_TOP_LH8_13", + "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LOGIC_OUTS_L_B12_15", + "CMT_TOP_LH12_9", + "CMT_TOP_SW2A0_0", + "CMT_TOP_SW2A0_11", + "CMT_TOP_IMUX16_14", + "CMT_TOP_WW4A3_7", + "CMT_TOP_WW4END2_12", + "CMT_TOP_BYP5_10", + "CMT_TOP_LH12_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW2A0_4", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_IMUX30_1", + "CMT_TOP_IMUX0_1", + "CMT_TOP_IMUX39_3", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_FAN6_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_IMUX43_12", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_10", + "CMT_TOP_NE2A2_9", + "CMT_TOP_EE4B1_11", + "CMT_TOP_BYP0_15", + "CMT_TOP_IMUX37_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_NW4END0_10", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_NE4BEG3_14", + "CMT_TOP_IMUX44_1", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX37_7", + "CMT_TOP_CTRL0_12", + "CMT_TOP_IMUX29_1", + "CMT_TOP_FAN6_11", + "CMT_LR_LOWER_B_MMCM_CLKIN1" + ], + "tile_type": "CMT_TOP_L_LOWER_B", + "sites": [ + { + "site_pins": { + "CLKOUT2": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "TESTOUT25": "CMT_LR_LOWER_B_MMCM_TESTOUT25", + "PSDONE": "CMT_LR_LOWER_B_MMCM_PSDONE", + "DADDR5": "CMT_LR_LOWER_B_MMCM_DADDR5", + "TESTOUT32": "CMT_LR_LOWER_B_MMCM_TESTOUT32", + "TESTOUT29": "CMT_LR_LOWER_B_MMCM_TESTOUT29", + "TESTOUT43": "CMT_LR_LOWER_B_MMCM_TESTOUT43", + "TESTIN29": "CMT_LR_LOWER_B_MMCM_TESTIN29", + "DADDR2": "CMT_LR_LOWER_B_MMCM_DADDR2", + "TESTOUT18": "CMT_LR_LOWER_B_MMCM_TESTOUT18", + "DI10": "CMT_LR_LOWER_B_MMCM_DI10", + "TESTIN14": "CMT_LR_LOWER_B_MMCM_TESTIN14", + "TESTIN21": "CMT_LR_LOWER_B_MMCM_TESTIN21", + "CLKOUT0B": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "TESTIN18": "CMT_LR_LOWER_B_MMCM_TESTIN18", + "TESTOUT61": "CMT_LR_LOWER_B_MMCM_TESTOUT61", + "DO12": "CMT_LR_LOWER_B_MMCM_DO12", + "DO10": "CMT_LR_LOWER_B_MMCM_DO10", + "TESTOUT40": "CMT_LR_LOWER_B_MMCM_TESTOUT40", + "TESTOUT23": "CMT_LR_LOWER_B_MMCM_TESTOUT23", + "TESTOUT59": "CMT_LR_LOWER_B_MMCM_TESTOUT59", + "TESTOUT50": "CMT_LR_LOWER_B_MMCM_TESTOUT50", + "TESTOUT49": "CMT_LR_LOWER_B_MMCM_TESTOUT49", + "DI3": "CMT_LR_LOWER_B_MMCM_DI3", + "TESTOUT46": "CMT_LR_LOWER_B_MMCM_TESTOUT46", + "CLKIN1": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "TESTOUT6": "CMT_LR_LOWER_B_MMCM_TESTOUT6", + "TESTOUT12": "CMT_LR_LOWER_B_MMCM_TESTOUT12", + "TESTIN22": "CMT_LR_LOWER_B_MMCM_TESTIN22", + "DI15": "CMT_LR_LOWER_B_MMCM_DI15", + "DCLK": "CMT_LR_LOWER_B_MMCM_DCLK", + "CLKFBIN": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "DI9": "CMT_LR_LOWER_B_MMCM_DI9", + "CLKINSEL": "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "TESTIN30": "CMT_LR_LOWER_B_MMCM_TESTIN30", + "TESTOUT0": "CMT_LR_LOWER_B_MMCM_TESTOUT0", + "TESTOUT60": "CMT_LR_LOWER_B_MMCM_TESTOUT60", + "TESTOUT9": "CMT_LR_LOWER_B_MMCM_TESTOUT9", + "DO0": "CMT_LR_LOWER_B_MMCM_DO0", + "TESTOUT35": "CMT_LR_LOWER_B_MMCM_TESTOUT35", + "TESTOUT47": "CMT_LR_LOWER_B_MMCM_TESTOUT47", + "DO3": "CMT_LR_LOWER_B_MMCM_DO3", + "DI4": "CMT_LR_LOWER_B_MMCM_DI4", + "DI0": "CMT_LR_LOWER_B_MMCM_DI0", + "DI7": "CMT_LR_LOWER_B_MMCM_DI7", + "TESTOUT57": "CMT_LR_LOWER_B_MMCM_TESTOUT57", + "TESTIN4": "CMT_LR_LOWER_B_MMCM_TESTIN4", + "TESTOUT24": "CMT_LR_LOWER_B_MMCM_TESTOUT24", + "DADDR3": "CMT_LR_LOWER_B_MMCM_DADDR3", + "TESTOUT63": "CMT_LR_LOWER_B_MMCM_TESTOUT63", + "TESTOUT48": "CMT_LR_LOWER_B_MMCM_TESTOUT48", + "CLKOUT3B": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "TESTIN1": "CMT_LR_LOWER_B_MMCM_TESTIN1", + "TESTOUT27": "CMT_LR_LOWER_B_MMCM_TESTOUT27", + "TESTOUT13": "CMT_LR_LOWER_B_MMCM_TESTOUT13", + "TESTOUT7": "CMT_LR_LOWER_B_MMCM_TESTOUT7", + "CLKOUT4": "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "TESTOUT3": "CMT_LR_LOWER_B_MMCM_TESTOUT3", + "TESTIN28": "CMT_LR_LOWER_B_MMCM_TESTIN28", + "TESTOUT54": "CMT_LR_LOWER_B_MMCM_TESTOUT54", + "RST": "CMT_LR_LOWER_B_MMCM_RST", + "TESTOUT8": "CMT_LR_LOWER_B_MMCM_TESTOUT8", + "CLKOUT5": "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "DO13": "CMT_LR_LOWER_B_MMCM_DO13", + "PSEN": "CMT_LR_LOWER_B_MMCM_PSEN", + "TESTOUT39": "CMT_LR_LOWER_B_MMCM_TESTOUT39", + "TESTOUT51": "CMT_LR_LOWER_B_MMCM_TESTOUT51", + "TESTOUT20": "CMT_LR_LOWER_B_MMCM_TESTOUT20", + "PWRDWN": "CMT_LR_LOWER_B_MMCM_PWRDWN", + "TESTIN27": "CMT_LR_LOWER_B_MMCM_TESTIN27", + "TESTOUT52": "CMT_LR_LOWER_B_MMCM_TESTOUT52", + "DI13": "CMT_LR_LOWER_B_MMCM_DI13", + "TESTIN24": "CMT_LR_LOWER_B_MMCM_TESTIN24", + "TESTIN10": "CMT_LR_LOWER_B_MMCM_TESTIN10", + "DO1": "CMT_LR_LOWER_B_MMCM_DO1", + "PSINCDEC": "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "DADDR4": "CMT_LR_LOWER_B_MMCM_DADDR4", + "TESTIN11": "CMT_LR_LOWER_B_MMCM_TESTIN11", + "TESTIN6": "CMT_LR_LOWER_B_MMCM_TESTIN6", + "DI2": "CMT_LR_LOWER_B_MMCM_DI2", + "DADDR0": "CMT_LR_LOWER_B_MMCM_DADDR0", + "DO8": "CMT_LR_LOWER_B_MMCM_DO8", + "DI12": "CMT_LR_LOWER_B_MMCM_DI12", + "DO14": "CMT_LR_LOWER_B_MMCM_DO14", + "TESTOUT34": "CMT_LR_LOWER_B_MMCM_TESTOUT34", + "DI6": "CMT_LR_LOWER_B_MMCM_DI6", + "TESTOUT15": "CMT_LR_LOWER_B_MMCM_TESTOUT15", + "TESTOUT14": "CMT_LR_LOWER_B_MMCM_TESTOUT14", + "DI5": "CMT_LR_LOWER_B_MMCM_DI5", + "TESTIN25": "CMT_LR_LOWER_B_MMCM_TESTIN25", + "DI11": "CMT_LR_LOWER_B_MMCM_DI11", + "CLKOUT3": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "TESTIN23": "CMT_LR_LOWER_B_MMCM_TESTIN23", + "TESTOUT2": "CMT_LR_LOWER_B_MMCM_TESTOUT2", + "DADDR1": "CMT_LR_LOWER_B_MMCM_DADDR1", + "TESTOUT30": "CMT_LR_LOWER_B_MMCM_TESTOUT30", + "TESTIN12": "CMT_LR_LOWER_B_MMCM_TESTIN12", + "DWE": "CMT_LR_LOWER_B_MMCM_DWE", + "TMUXOUT": "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "TESTOUT11": "CMT_LR_LOWER_B_MMCM_TESTOUT11", + "TESTIN31": "CMT_LR_LOWER_B_MMCM_TESTIN31", + "DO9": "CMT_LR_LOWER_B_MMCM_DO9", + "DI14": "CMT_LR_LOWER_B_MMCM_DI14", + "TESTOUT4": "CMT_LR_LOWER_B_MMCM_TESTOUT4", + "TESTOUT58": "CMT_LR_LOWER_B_MMCM_TESTOUT58", + "TESTOUT36": "CMT_LR_LOWER_B_MMCM_TESTOUT36", + "TESTOUT56": "CMT_LR_LOWER_B_MMCM_TESTOUT56", + "PSCLK": "CMT_LR_LOWER_B_MMCM_PSCLK", + "TESTOUT44": "CMT_LR_LOWER_B_MMCM_TESTOUT44", + "CLKFBOUTB": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "TESTIN26": "CMT_LR_LOWER_B_MMCM_TESTIN26", + "TESTOUT22": "CMT_LR_LOWER_B_MMCM_TESTOUT22", + "TESTIN5": "CMT_LR_LOWER_B_MMCM_TESTIN5", + "TESTIN7": "CMT_LR_LOWER_B_MMCM_TESTIN7", + "TESTOUT42": "CMT_LR_LOWER_B_MMCM_TESTOUT42", + "TESTOUT17": "CMT_LR_LOWER_B_MMCM_TESTOUT17", + "TESTIN8": "CMT_LR_LOWER_B_MMCM_TESTIN8", + "CLKFBOUT": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "TESTIN9": "CMT_LR_LOWER_B_MMCM_TESTIN9", + "TESTOUT33": "CMT_LR_LOWER_B_MMCM_TESTOUT33", + "DADDR6": "CMT_LR_LOWER_B_MMCM_DADDR6", + "CLKINSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "TESTIN20": "CMT_LR_LOWER_B_MMCM_TESTIN20", + "DRDY": "CMT_LR_LOWER_B_MMCM_DRDY", + "TESTIN0": "CMT_LR_LOWER_B_MMCM_TESTIN0", + "DI1": "CMT_LR_LOWER_B_MMCM_DI1", + "DO15": "CMT_LR_LOWER_B_MMCM_DO15", + "CLKIN2": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "DO5": "CMT_LR_LOWER_B_MMCM_DO5", + "DO7": "CMT_LR_LOWER_B_MMCM_DO7", + "TESTOUT31": "CMT_LR_LOWER_B_MMCM_TESTOUT31", + "LOCKED": "CMT_LR_LOWER_B_MMCM_LOCKED", + "DO2": "CMT_LR_LOWER_B_MMCM_DO2", + "TESTIN13": "CMT_LR_LOWER_B_MMCM_TESTIN13", + "TESTIN16": "CMT_LR_LOWER_B_MMCM_TESTIN16", + "TESTIN2": "CMT_LR_LOWER_B_MMCM_TESTIN2", + "DI8": "CMT_LR_LOWER_B_MMCM_DI8", + "CLKFBSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "TESTOUT5": "CMT_LR_LOWER_B_MMCM_TESTOUT5", + "DO11": "CMT_LR_LOWER_B_MMCM_DO11", + "TESTOUT53": "CMT_LR_LOWER_B_MMCM_TESTOUT53", + "CLKOUT2B": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "TESTOUT38": "CMT_LR_LOWER_B_MMCM_TESTOUT38", + "DEN": "CMT_LR_LOWER_B_MMCM_DEN", + "TESTOUT10": "CMT_LR_LOWER_B_MMCM_TESTOUT10", + "TESTOUT62": "CMT_LR_LOWER_B_MMCM_TESTOUT62", + "TESTIN3": "CMT_LR_LOWER_B_MMCM_TESTIN3", + "TESTOUT1": "CMT_LR_LOWER_B_MMCM_TESTOUT1", + "TESTOUT21": "CMT_LR_LOWER_B_MMCM_TESTOUT21", + "TESTIN15": "CMT_LR_LOWER_B_MMCM_TESTIN15", + "TESTOUT16": "CMT_LR_LOWER_B_MMCM_TESTOUT16", + "TESTOUT19": "CMT_LR_LOWER_B_MMCM_TESTOUT19", + "TESTOUT45": "CMT_LR_LOWER_B_MMCM_TESTOUT45", + "TESTOUT26": "CMT_LR_LOWER_B_MMCM_TESTOUT26", + "CLKOUT1": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "TESTOUT28": "CMT_LR_LOWER_B_MMCM_TESTOUT28", + "TESTOUT55": "CMT_LR_LOWER_B_MMCM_TESTOUT55", + "TESTIN17": "CMT_LR_LOWER_B_MMCM_TESTIN17", + "TESTOUT41": "CMT_LR_LOWER_B_MMCM_TESTOUT41", + "CLKOUT1B": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "DO4": "CMT_LR_LOWER_B_MMCM_DO4", + "CLKOUT6": "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "TESTIN19": "CMT_LR_LOWER_B_MMCM_TESTIN19", + "CLKOUT0": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "DO6": "CMT_LR_LOWER_B_MMCM_DO6", + "TESTOUT37": "CMT_LR_LOWER_B_MMCM_TESTOUT37" + }, + "type": "MMCME2_ADV", + "prefix": "MMCME2_ADV", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_TOP_L_LOWER_T.json b/artix7/tile_type_CMT_TOP_L_LOWER_T.json index 2a2c071..e75f2c2 100644 --- a/artix7/tile_type_CMT_TOP_L_LOWER_T.json +++ b/artix7/tile_type_CMT_TOP_L_LOWER_T.json @@ -1,4823 +1,4823 @@ { - "wires": [ - "CMT_TOP_IMUX1_6", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_TOP_WR1END2_4", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX20_3", - "CMT_TOP_EE2A0_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_LH7_3", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX28_8", - "CMT_TOP_EE4B1_1", - "CMT_TOP_NW4END2_5", - "CMT_TOP_WW2A0_3", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_NE2A1_7", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_TOP_IMUX18_4", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_BYP5_2", - "CMT_TOP_EE2A3_5", - "CMT_TOP_IMUX42_4", - "CMT_PHASER_BOT_REFMUX_0", - "CMT_TOP_IMUX19_0", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_TOP_LH11_4", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_TOP_SW4END2_4", - "CMT_TOP_WW2A0_4", - "CMT_TOP_FAN6_0", - "CMT_TOP_WW2END3_7", - "CMT_TOP_BYP6_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_NE2A1_8", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX39_5", - "CMT_TOP_WW2A2_6", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_TOP_SW4END3_3", - "CMT_TOP_WW4B0_3", - "CMT_TOP_BYP3_2", - "CMT_TOP_CTRL0_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_TOP_CLK1_8", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_TOP_NW2A0_1", - "CMT_TOP_FAN3_3", - "CMT_TOP_EE4A3_6", - "CMT_TOP_NW4A0_2", - "CMT_TOP_WW2END0_8", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SE4BEG1_8", - "CMT_LR_LOWER_T_CLK_MMCM10", - "CMT_TOP_WW4A2_2", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX23_0", - "CMT_TOP_LH12_4", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_TOP_WW4C0_8", - "CMT_TOP_BYP6_1", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_IMUX15_1", - "CMT_TOP_SE2A0_0", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_FAN0_6", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_SW2A2_1", - "CMT_TOP_FAN0_1", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_PHASER_IN_B_RCLK1", - "CMT_TOP_SW4END0_1", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_TOP_WW4END0_6", - "CMT_TOP_IMUX1_0", - "CMT_TOP_SW2A1_4", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW4END2_7", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_NE4BEG2_5", - "CMT_PHASER_OUT_B_RDEN_TOFIFO", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE2A2_4", - "CMT_TOP_WL1END0_4", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_IMUX26_6", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_IMUX14_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_BYP7_6", - "CMT_TOP_NW2A2_8", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_SE2A1_0", - "CMT_TOP_CTRL1_4", - "CMT_TOP_IMUX0_0", - "CMT_TOP_SW4END3_4", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_WW4C3_1", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_LR_LOWER_T_CLK_MMCM13", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_NW4END1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_WL1END0_6", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4A0_3", - "CMT_TOP_NW4A3_6", - "CMT_TOP_BYP2_5", - "CMT_TOP_IMUX10_0", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_TOP_NW2A2_1", - "CMT_TOP_ICLK_0", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_IMUX33_4", - "CMT_TOP_NW2A1_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_NE4C0_0", - "CMT_TOP_EE4B0_4", - "CMT_TOP_NE2A1_0", - "CMT_TOP_WR1END0_6", - "CMT_TOP_LH12_2", - "CMT_TOP_FAN5_5", - "CMT_TOP_SW4END0_2", - "CMT_TOP_IMUX4_8", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SE4BEG3_1", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_TOP_IMUX43_6", - "CMT_PHASER_IN_DB_TESTIN7", - "CMT_PHASER_IN_B_ICLK", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4A3_7", - "CMT_TOP_NE4C3_6", - "CMT_TOP_LH9_1", - "CMT_TOP_EE4A3_1", - "CMT_TOP_WW2A0_6", - "CMT_TOP_BYP6_3", - "CMT_TOP_FAN2_6", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_OCLK_3", - "CMT_TOP_WR1END1_1", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_EE4C2_8", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX10_4", - "CMT_TOP_OCLK_8", - "CMT_TOP_FAN4_3", - "CMT_TOP_BYP0_1", - "CMT_TOP_NE2A0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_TOP_IMUX31_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_ICLKDIV_3", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_LH4_4", - "CMT_TOP_EE4B3_0", - "CMT_TOP_LH10_7", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_FAN4_8", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NW4A3_1", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_SW2A3_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_OCLK_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_IMUX33_1", - "CMT_TOP_EE4C1_5", - "CMT_TOP_WW4B3_0", - "CMT_TOP_SE2A0_2", - "CMT_TOP_LH11_7", - "CMT_TOP_IMUX31_1", - "CMT_TOP_LH2_1", - "CMT_TOP_IMUX12_6", - "CMT_TOP_SW4END3_6", - "CMT_TOP_LH6_8", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WW2END1_1", - "CMT_TOP_NE2A3_3", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_TOP_IMUX12_8", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_EE4A1_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_WL1END2_5", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX18_1", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_IMUX42_5", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_LR_LOWER_T_CLK_IN3_HCLK", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_IMUX20_8", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_IMUX39_1", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_NE2A3_2", - "CMT_TOP_IMUX24_7", - "CMT_TOP_NW2A3_2", - "CMT_TOP_SE2A0_6", - "CMT_TOP_IMUX30_3", - "CMT_TOP_OCLK_6", - "CMT_TOP_IMUX10_6", - "CMT_TOP_SE2A2_7", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_IMUX4_2", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_EE4B3_8", - "CMT_TOP_IMUX5_8", - "CMT_TOP_WW2A1_1", - "CMT_PHASER_OUT_A_RDEN_TOFIFO", - "CMT_TOP_IMUX37_6", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX28_4", - "CMT_TOP_NE4BEG1_6", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_TOP_IMUX2_7", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_TOP_BYP4_8", - "CMT_TOP_WW4B2_3", - "CMT_TOP_IMUX47_5", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_TOP_WW4B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_WW4C2_5", - "CMT_TOP_IMUX38_5", - "CMT_TOP_EE4B2_5", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_TOP_IMUX44_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_SW4END1_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_SE4C1_7", - "CMT_TOP_IMUX18_6", - "CMT_TOP_SE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_IMUX44_6", - "CMT_TOP_OCLK_1", - "CMT_TOP_WL1END3_6", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_SE2A2_0", - "CMT_TOP_IMUX27_0", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_SE2A2_8", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW4END2_2", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_TOP_WR1END3_7", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_PHASERA_DTSBUS1", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_LH11_8", - "CMT_TOP_WW4END2_4", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_EE2A2_3", - "CMT_TOP_LH4_7", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_WW4A0_8", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_TOP_LH1_6", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX17_6", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_IMUX6_0", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_BYP4_6", - "CMT_LR_LOWER_T_CLK_MMCM0", - "CMT_TOP_BYP6_7", - "CMT_TOP_LH5_5", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_EE2A2_5", - "CMT_TOP_NE2A1_1", - "CMT_TOP_WW4END1_8", - "CMT_TOP_SW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LH4_8", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_IMUX45_1", - "CMT_TOP_CTRL0_3", - "CMT_TOP_WW4B3_1", - "CMT_TOP_NW4A2_4", - "CMT_TOP_SW4A0_4", - "CMT_TOP_FAN2_4", - "CMT_TOP_IMUX43_1", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_TOP_IMUX19_5", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_TOP_EE4B1_0", - "CMT_TOP_BYP7_7", - "CMT_TOP_SE4C3_3", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_TOP_WR1END0_3", - "CMT_TOP_SW4A2_8", - "CMT_TOP_NE4C3_1", - "CMT_TOP_WW2A1_3", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SW4A0_3", - "CMT_TOP_EE4C3_0", - "CMT_TOP_CLK0_6", - "CMT_TOP_WW4C1_3", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_TOP_SE2A3_4", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_TOP_CTRL1_8", - "CMT_TOP_LH7_6", - "CMT_TOP_WL1END1_1", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_IMUX41_1", - "CMT_TOP_NE4C2_7", - "CMT_TOP_EE4B2_0", - "CMT_TOP_LH5_7", - "CMT_TOP_SW4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_IMUX41_4", - "CMT_TOP_LH7_8", - "CMT_TOP_IMUX2_5", - "CMT_TOP_WR1END2_7", - "CMT_TOP_FAN6_3", - "CMT_TOP_WW2A0_7", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_LR_LOWER_T_CLK_PERF2", - "CMT_TOP_BYP4_2", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_TOP_CLK0_1", - "CMT_TOP_IMUX6_4", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE2A2_8", - "CMT_TOP_WW4END0_2", - "CMT_TOP_SE4C3_7", - "CMT_PHASER_IN_B_ICLKDIV", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4A0_7", - "CMT_TOP_LH9_3", - "CMT_TOP_EL1BEG2_0", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_TOP_NE2A0_5", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_TOP_EE4C3_2", - "CMT_R_TOP_LOWER_B_CLKINT_0", - "CMT_PHASER_DOWN_DQS_TO_PHASER_A", - "CMT_TOP_SE4C2_5", - "CMT_TOP_IMUX32_0", - "CMT_TOP_SW2A3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_TOP_WW2END3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_NE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4C1_3", - "CMT_TOP_IMUX43_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_IMUX27_5", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_CTRL0_8", - "CMT_TOP_EE4C0_0", - "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "CMT_TOP_NW2A0_4", - "CMT_TOP_SE4BEG3_6", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_TOP_IMUX33_3", - "CMT_TOP_NW4END2_0", - "CMT_TOP_IMUX13_6", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_IMUX1_2", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_EE4B1_3", - "CMT_TOP_WL1END1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_TOP_LH4_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_NW4END3_2", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_IMUX21_1", - "CMT_TOP_CTRL1_0", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_SW2A3_0", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_TOP_SW4END0_0", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_TOP_WW4A1_2", - "CMT_TOP_BYP7_5", - "CMT_TOP_ICLK_7", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW2END1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_PHASER_DOWN_DQS_TO_PHASER_B", - "CMT_TOP_WW4C0_3", - "CMT_PHASER_IN_CA_RCLK", - "CMT_TOP_FAN1_0", - "CMT_TOP_SW4END1_4", - "CMT_TOP_EE4C3_3", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX9_5", - "CMT_TOP_WW4A0_1", - "CMT_TOP_FAN6_8", - "CMT_TOP_WW4A0_0", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_TOP_CTRL0_5", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_TOP_EE4B0_8", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX40_1", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_IMUX7_4", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4C3_4", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_SE4BEG3_4", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_TOP_BYP7_2", - "CMT_TOP_SE4C1_0", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_TOP_IMUX15_4", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW4A1_2", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_TOP_BYP2_8", - "CMT_TOP_WW2END2_2", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_IMUX23_3", - "CMT_TOP_WW4C0_0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_TOP_BYP6_8", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_TOP_WW2A2_3", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_IMUX28_0", - "CMT_TOP_EE4A1_7", - "CMT_TOP_IMUX31_3", - "CMT_TOP_EE4A2_0", - "CMT_TOP_IMUX25_8", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_PHASER_B_ICLK_TOIOI", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_TOP_IMUX35_2", - "CMT_TOP_NE4BEG2_6", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NW2A3_0", - "CMT_TOP_WL1END0_3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_PHASER_BOT_IRANKA0", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2END1_3", - "CMT_TOP_SW2A2_5", - "CMT_TOP_ER1BEG3_1", - "CMT_PHASERREF_DOWN_PHASEROUT_B", - "CMT_TOP_SW2A3_5", - "CMT_TOP_NW4END0_5", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_IMUX37_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END3_6", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_IMUX14_4", - "CMT_TOP_LH10_3", - "CMT_TOP_LH6_5", - "CMT_TOP_LH10_1", - "CMT_TOP_IMUX17_1", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_TOP_BYP4_0", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_IMUX37_5", - "CMT_TOP_EE2BEG2_2", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_TOP_WL1END3_2", - "CMT_TOP_IMUX7_7", - "CMT_TOP_SW4A2_7", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX20_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_SE4C3_4", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_PHASER_BOT_IRANKB1", - "CMT_TOP_FAN4_0", - "CMT_TOP_IMUX41_7", - "CMT_PHASER_B_OCLK90_TOIOI", - "CMT_TOP_IMUX33_5", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_LH6_1", - "CMT_LR_LOWER_T_CLK_MMCM4", - "CMT_TOP_WW4C2_7", - "CMT_TOP_BYP5_4", - "CMT_PHASER_BOT_IBURSTPENDING1", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_IMUX11_4", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_NE4C3_0", - "CMT_TOP_WW4END1_0", - "CMT_TOP_FAN7_5", - "CMT_TOP_BYP0_8", - "CMT_TOP_IMUX22_2", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_WW4END3_2", - "CMT_TOP_FAN4_5", - "CMT_TOP_IMUX30_8", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_IMUX47_0", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_TOP_EE4B2_6", - "CMT_PHASER_OUT_B_OCLK1X_90", - "CMT_TOP_IMUX16_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_SW4A1_3", - "CMT_TOP_NW4END1_6", - "CMT_TOP_WW4END2_0", - "CMT_TOP_IMUX34_4", - "CMT_TOP_SW4END2_7", - "CMT_TOP_IMUX19_3", - "CMT_TOP_LH12_0", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_NW4END2_8", - "CMT_TOP_EE4A1_8", - "CMT_TOP_WW4B1_2", - "CMT_TOP_IMUX36_0", - "CMT_TOP_FAN7_8", - "CMT_TOP_LH3_3", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX10_5", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_WW2A3_0", - "CMT_LR_LOWER_T_CLK_IN1_HCLK", - "CMT_TOP_LH3_4", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX40_4", - "CMT_TOP_FAN5_6", - "CMT_TOP_IMUX38_0", - "CMT_TOP_IMUX30_6", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_IMUX23_5", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_LH2_3", - "CMT_TOP_EE4C3_8", - "CMT_TOP_NW4A3_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SW4END2_3", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_TOP_SW4END3_2", - "CMT_TOP_LH8_5", - "CMT_TOP_WW2A2_5", - "CMT_PHASER_OUT_B_OCLK", - "CMT_TOP_WW4A1_3", - "CMT_TOP_IMUX29_0", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_WR1END0_4", - "CMT_TOP_NW2A0_2", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_NW4END0_2", - "CMT_TOP_FAN1_1", - "CMT_TOP_LH1_4", - "CMT_TOP_SE4C3_0", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_TOP_IMUX16_7", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_TOP_SE2A1_5", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_SE4C0_7", - "CMT_TOP_FAN6_5", - "CMT_TOP_EE4A2_4", - "CMT_TOP_WR1END0_7", - "CMT_TOP_EE4A3_7", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_WR1END1_0", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_TOP_IMUX46_3", - "CMT_TOP_SW4END2_2", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_PHASERA_DTSBUS0", - "CMT_TOP_WW4B3_5", - "CMT_TOP_IMUX6_7", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_TOP_NW4A0_7", - "CMT_TOP_IMUX32_1", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4C1_6", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_TOP_FAN2_0", - "CMT_TOP_WW4A0_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX37_2", - "CMT_TOP_EE4C1_1", - "CMT_TOP_MONITOR_P_7", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_TOP_WW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_IMUX45_8", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_TOP_FAN0_4", - "CMT_TOP_IMUX20_2", - "CMT_TOP_SW4A2_6", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_FAN0_8", - "CMT_TOP_SE4C0_3", - "CMT_TOP_IMUX29_6", - "CMT_TOP_EE2BEG2_6", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_WL1END1_6", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_WW2END1_2", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NW4A0_0", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_SW4A1_6", - "CMT_TOP_EE4A1_3", - "CMT_TOP_BYP1_8", - "CMT_PHASER_BOT_IRANKA1", - "CMT_TOP_WW2END2_1", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EE4B2_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_EE4B3_2", - "CMT_TOP_SE4C1_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_IMUX36_3", - "CMT_TOP_SE4C2_3", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_TOP_IMUX26_1", - "CMT_TOP_CLK1_2", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_TOP_NW4END0_3", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX27_8", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_6", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_TOP_IMUX38_1", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_WL1END0_8", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_IMUX29_7", - "CMT_TOP_SE2A1_2", - "CMT_TOP_NE2A3_6", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4B1_3", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_IMUX27_2", - "CMT_TOP_NE2A1_6", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_NW2A3_8", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_TOP_LH7_1", - "CMT_TOP_WW4END1_7", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_TOP_SE2A2_3", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_FAN7_4", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_SE4C3_6", - "CMT_TOP_NE4C3_3", - "CMT_TOP_CTRL0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_FAN2_2", - "CMT_TOP_NW4END1_2", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX18_7", - "CMT_TOP_WW4END2_7", - "CMT_TOP_NW4END1_0", - "CMT_TOP_EE4C0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_SE4BEG1_4", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_TOP_IMUX29_5", - "CMT_TOP_NW2A1_5", - "CMT_TOP_WW2END0_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_NW4A1_0", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX40_7", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_TOP_BYP6_2", - "CMT_TOP_IMUX42_7", - "CMT_TOP_BYP5_5", - "CMT_TOP_WR1END0_8", - "CMT_PHASER_OUT_A_OCLK1X_90", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX2_1", - "CMT_TOP_FAN5_7", - "CMT_TOP_SE2A2_6", - "CMT_TOP_EE4B1_8", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4END3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4END1_6", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_EE4C0_8", - "CMT_TOP_SE4C0_1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_TOP_EE2A0_1", - "CMT_TOP_NW2A1_8", - "CMT_TOP_SW2A3_1", - "CMT_TOP_EE2A1_0", - "CMT_TOP_WW4C3_5", - "CMT_TOP_IMUX24_1", - "CMT_TOP_BYP1_0", - "CMT_TOP_LH9_4", - "CMT_TOP_WW4B0_8", - "CMT_TOP_SW4END1_1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_TOP_WW4B0_7", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_NE2A1_2", - "CMT_PHASER_B_TOMMCM_OCLK1X_90", - "CMT_TOP_WW4B2_0", - "CMT_TOP_LH10_8", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_IMUX30_4", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WW2END3_3", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_FAN1_6", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_WW2END3_1", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_TOP_SE4C1_2", - "CMT_TOP_NW2A2_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_EE4A0_0", - "CMT_TOP_IMUX22_0", - "CMT_TOP_EE4A2_1", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_IMUX46_8", - "CMT_TOP_WW2A3_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4A0_6", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_EE4B0_5", - "CMT_TOP_NW2A0_3", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_TOP_ICLK_2", - "CMT_TOP_WW4B2_7", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_IMUX6_2", - "CMT_TOP_NE4C2_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_NW4END3_0", - "CMT_TOP_SW2A1_2", - "CMT_LR_LOWER_T_CLK_MMCM11", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_TOP_FAN1_5", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_IMUX10_8", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_TOP_CTRL0_7", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_TOP_NW4END3_7", - "CMT_TOP_LH8_8", - "CMT_TOP_IMUX44_2", - "CMT_TOP_SW2A2_0", - "CMT_TOP_WW4A2_5", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_TOP_SW4A2_2", - "CMT_PHASERA_CTSBUS1", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2A1_6", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_LH10_2", - "CMT_TOP_IMUX38_4", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE2A2_5", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_TOP_IMUX9_6", - "CMT_TOP_NW4END3_3", - "CMT_TOP_IMUX45_2", - "CMT_TOP_FAN6_1", - "CMT_TOP_IMUX3_8", - "CMT_PHASER_IN_CA_ICLK", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_TOP_IMUX13_5", - "CMT_TOP_SE4C1_3", - "CMT_TOP_WL1END2_6", - "CMT_TOP_LH11_2", - "CMT_TOP_SW4A3_8", - "CMT_PHASER_IN_DB_RST", - "CMT_TOP_LH12_8", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_SE2A0_1", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_TOP_IMUX37_4", - "CMT_TOP_WW4END0_1", - "CMT_TOP_EE4B0_6", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_BYP3_0", - "CMT_TOP_EE4B0_7", - "CMT_TOP_NE4C1_3", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_TOP_SW4END2_0", - "CMT_TOP_NW2A1_0", - "CMT_TOP_FAN5_4", - "CMT_TOP_NE4C1_1", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EE2A1_4", - "CMT_TOP_IMUX1_5", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_SE4BEG0_1", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX35_1", - "CMT_TOP_WW2END1_8", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_IMUX39_4", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_ER1BEG2_6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_TOP_EE4B2_2", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW4A1_5", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WW4C3_4", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_SE2A2_5", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_NE2A0_6", - "CMT_TOP_BYP1_5", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_FAN1_3", - "CMT_TOP_SE2A3_7", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_6", - "CMT_TOP_SW2A0_4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_TOP_SW4END3_5", - "CMT_TOP_EL1BEG3_5", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_TOP_WW4END0_7", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_IMUX25_2", - "CMT_TOP_WR1END3_4", - "CMT_TOP_FAN0_3", - "CMT_TOP_IMUX42_6", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_WW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_NE2A2_8", - "CMT_TOP_WW4END3_4", - "CMT_TOP_FAN0_7", - "CMT_TOP_IMUX32_3", - "CMT_TOP_WW2A3_7", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_WW4B0_1", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_EL1BEG1_0", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_TOP_WL1END2_2", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_WW4B1_0", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_IMUX42_2", - "CMT_TOP_LH8_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_EE4A0_5", - "CMT_TOP_BYP6_5", - "CMT_TOP_WL1END2_3", - "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "CMT_TOP_IMUX39_2", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_SE2A1_8", - "CMT_R_TOP_LOWER_B_CLKINT_1", - "CMT_TOP_NE4C1_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_NW2A0_6", - "CMT_TOP_WR1END3_0", - "CMT_TOP_FAN3_1", - "CMT_PHASERREF_DOWN_PHASERIN_A", - "CMT_TOP_WW4A3_8", - "CMT_TOP_SW2A1_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_LH4_5", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_TOP_IMUX40_5", - "CMT_TOP_SW4END1_7", - "CMT_TOP_NW4END3_4", - "CMT_TOP_EE4C3_4", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_WR1END0_0", - "CMT_TOP_NW4A0_5", - "CMT_BOT_HCLKMUX_CLKINT_1", - "CMT_TOP_CTRL1_5", - "CMT_TOP_SE4C3_1", - "CMT_LR_LOWER_T_CLK_MMCM5", - "CMT_TOP_IMUX18_3", - "CMT_TOP_EE2A1_1", - "CMT_TOP_IMUX13_4", - "CMT_TOP_SW2A0_1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_IMUX16_5", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_TOP_LH9_5", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_TOP_WW2END0_6", - "CMT_TOP_IMUX0_3", - "CMT_TOP_EE2A1_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_OCLK_5", - "CMT_TOP_EE4B0_1", - "CMT_TOP_WL1END3_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_IMUX47_3", - "CMT_TOP_FAN5_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_NE2A2_7", - "CMT_TOP_WW4B1_5", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WR1END1_6", - "CMT_TOP_BYP0_5", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_PHASER_OUT_B_RDCLK_TOFIFO", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_7", - "CMT_PHASER_IN_A_ICLKDIV", - "CMT_TOP_SE2A2_2", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_WR1END3_8", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_TOP_LH9_7", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_IMUX9_4", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW2END3_5", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SW4END0_3", - "CMT_TOP_WR1END2_6", - "CMT_TOP_IMUX46_0", - "CMT_TOP_WW2A3_4", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_CTRL1_2", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LH7_0", - "CMT_TOP_LH6_6", - "CMT_LR_LOWER_T_CLK_MMCM6", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_WW2A2_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_IMUX2_0", - "CMT_TOP_CTRL0_2", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_TOP_WL1END1_3", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_EE4B3_5", - "CMT_TOP_IMUX5_3", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_IMUX38_2", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_SW4END0_5", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NW2A1_1", - "CMT_TOP_BYP4_1", - "CMT_TOP_CLK0_5", - "CMT_TOP_BYP5_7", - "CMT_TOP_IMUX6_1", - "CMT_TOP_SW4A3_0", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_OCLK_4", - "CMT_TOP_SW2A3_7", - "CMT_TOP_LH12_6", - "CMT_TOP_IMUX4_6", - "CMT_TOP_WR1END2_3", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX22_4", - "CMT_TOP_NW2A2_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_SE4C1_4", - "CMT_TOP_WW4C0_4", - "CMT_TOP_IMUX6_8", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_WW4A2_4", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX32_2", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_TOP_IMUX28_1", - "CMT_TOP_SE2A3_6", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LH8_1", - "CMT_TOP_WW4A0_3", - "CMT_TOP_IMUX20_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_IMUX35_7", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EE4A3_5", - "CMT_TOP_LH6_4", - "CMT_TOP_CLK1_0", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_IMUX27_4", - "CMT_TOP_ICLK_8", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_SW4A1_7", - "CMT_TOP_IMUX40_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_CLK0_8", - "CMT_TOP_IMUX7_2", - "MMCM_CLK_FREQBB_REBUFOUT0", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_TOP_FAN4_2", - "CMT_TOP_CLK1_1", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW4A1_7", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_LH12_3", - "CMT_TOP_WW2A1_8", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_NE4C1_7", - "CMT_TOP_WW4B2_1", - "CMT_PHASER_BOT_ENCALIB1", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE4BEG1_4", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG3_7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_TOP_WL1END2_8", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_TOP_LH8_2", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_SE2A3_2", - "CMT_TOP_LH8_3", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_TOP_IMUX13_8", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_IMUX23_7", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_WW2END1_0", - "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "CMT_TOP_IMUX39_0", - "CMT_TOP_WW4C3_2", - "CMT_TOP_IMUX30_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_EE4B0_2", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_TOP_IMUX12_4", - "CMT_PHASER_BOT_OBURSTPENDING0", - "CMT_TOP_IMUX33_8", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_SW2A2_2", - "CMT_TOP_LH5_1", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "CMT_TOP_LH10_0", - "CMT_PHASER_BOT_IBURSTPENDING0", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_LH6_3", - "CMT_TOP_EE2A0_0", - "CMT_TOP_WR1END3_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_IMUX12_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_IMUX21_8", - "CMT_PHASERA_DQSBUS0", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_LR_LOWER_T_CLK_MMCM2", - "CMT_TOP_IMUX5_1", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_IMUX10_2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_TOP_IMUX34_7", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_NW4A2_7", - "CMT_TOP_EE4BEG0_7", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EE2A2_1", - "CMT_TOP_LH4_1", - "CMT_TOP_FAN4_6", - "CMT_PHASERREF_DOWN_PHASERIN_B", - "CMT_TOP_WW4END1_1", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_FAN0_5", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_TOP_NE4C0_5", - "CMT_TOP_IMUX3_3", - "CMT_TOP_SW2A0_8", - "CMT_TOP_NW2A2_2", - "CMT_TOP_BYP1_1", - "CMT_TOP_IMUX37_1", - "CMT_TOP_NE4BEG3_5", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_SW4END1_5", - "CMT_TOP_FAN7_0", - "CMT_TOP_LH1_7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_BYP4_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_EE2A1_6", - "CMT_TOP_NE2A1_5", - "CMT_TOP_EE2A3_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_FAN3_4", - "CMT_TOP_NW4END2_6", - "CMT_TOP_LH7_5", - "CMT_TOP_IMUX18_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_WW4C2_0", - "CMT_TOP_SE2A3_3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_TOP_WL1END2_4", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_IMUX9_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_IMUX43_8", - "CMT_TOP_SE2A3_5", - "CMT_TOP_LH5_0", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4C1_6", - "CMT_TOP_WW4C0_2", - "CMT_TOP_LH12_7", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_WW2END2_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_BYP4_5", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_3", - "CMT_TOP_NE2A2_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_NE4C1_0", - "CMT_PHASER_OUT_CA_RST", - "CMT_TOP_IMUX11_1", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_EE2A3_0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_TOP_WR1END1_2", - "CMT_TOP_LH4_6", - "CMT_TOP_WW4B2_5", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_TOP_FAN7_7", - "CMT_TOP_SE2A1_4", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_LR_LOWER_T_CLK_PERF3", - "CMT_TOP_SE4C0_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_IMUX2_8", - "CMT_TOP_LH5_3", - "CMT_TOP_WW2END3_2", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_TOP_WR1END2_0", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_TOP_ER1BEG0_4", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_IMUX28_2", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_IMUX25_1", - "CMT_TOP_WW4C1_4", - "CMT_TOP_EE4C2_7", - "CMT_TOP_IMUX31_8", - "CMT_TOP_LH12_1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_TOP_NE2A0_3", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_TOP_LH3_2", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4END2_8", - "CMT_TOP_NE4C0_4", - "CMT_TOP_LH11_0", - "CMT_TOP_WW2A1_2", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_FAN6_2", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_BYP1_7", - "CMT_TOP_IMUX22_7", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WL1END2_0", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SW4A1_0", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_WL1END3_5", - "CMT_TOP_ICLK_3", - "CMT_TOP_IMUX0_5", - "CMT_TOP_SW4A0_8", - "CMT_TOP_IMUX1_8", - "CMT_TOP_FAN7_6", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX14_6", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_TOP_IMUX19_4", - "CMT_TOP_WW4C2_4", - "CMT_PHASER_B_TOMMCM_OCLKDIV", - "CMT_TOP_WW4B1_8", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LH4_0", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_BYP2_7", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_TOP_IMUX44_7", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_TOP_BYP2_2", - "CMT_TOP_EE4B2_4", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_TOP_WW4B0_2", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_TOP_CLK0_2", - "CMT_TOP_IMUX3_2", - "CMT_LR_LOWER_T_CLK_MMCM7", - "CMT_TOP_WL1END1_5", - "CMT_TOP_EE4C3_7", - "CMT_TOP_IMUX11_2", - "CMT_TOP_WW2END0_5", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4BEG1_0", - "CMT_PHASERA_DQSBUS1", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_WW4B1_1", - "CMT_TOP_LH7_2", - "CMT_TOP_WW4A1_4", - "CMT_TOP_CLK0_3", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LH6_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_EE4B2_8", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_TOP_WW4A3_6", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_SE4C2_0", - "CMT_TOP_IMUX23_2", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_OUT_DB_DIVIDERST", - "CMT_TOP_WW4END3_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_NW4A0_8", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_EE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_TOP_WW4END3_0", - "CMT_TOP_IMUX27_1", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_TOP_CTRL1_3", - "CMT_TOP_IMUX21_2", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_CLK1_3", - "CMT_TOP_IMUX34_0", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE2A3_8", - "CMT_TOP_LH11_6", - "CMT_TOP_SW2A0_0", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_FAN7_3", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_TOP_IMUX33_6", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_SW2A3_2", - "CMT_TOP_IMUX44_5", - "CMT_TOP_WW2A0_2", - "CMT_TOP_IMUX11_3", - "CMT_LR_LOWER_T_CLK_IN2_HCLK", - "CMT_TOP_WW4END1_6", - "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_WR1END3_1", - "CMT_TOP_IMUX24_5", - "CMT_TOP_WW4C1_7", - "CMT_TOP_NE2A0_0", - "CMT_TOP_WW4C2_8", - "CMT_TOP_EE2A3_8", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX28_6", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_EE4A2_2", - "CMT_TOP_IMUX13_1", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_TOP_IMUX24_0", - "CMT_TOP_NW4END2_4", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW4C3_3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE2BEG0_5", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_TOP_EE4C3_5", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_IMUX0_2", - "CMT_TOP_NW4END0_6", - "CMT_TOP_EE4C0_5", - "CMT_TOP_SE4BEG1_2", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_TOP_SE2A3_0", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX36_4", - "CMT_TOP_NW2A3_6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_TOP_NE2A3_0", - "CMT_TOP_LH12_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_EE4C2_3", - "CMT_TOP_FAN2_7", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WR1END1_4", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_TOP_IMUX31_2", - "CMT_TOP_LH5_8", - "CMT_TOP_FAN3_7", - "CMT_TOP_IMUX21_0", - "CMT_TOP_IMUX3_4", - "CMT_TOP_WL1END0_7", - "CMT_TOP_SW2A0_6", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_WW4END3_6", - "CMT_TOP_IMUX7_8", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_IMUX8_6", - "CMT_TOP_EE2A1_5", - "CMT_TOP_NW2A0_8", - "CMT_TOP_EE4A1_1", - "CMT_LR_LOWER_T_CLK_PERF1", - "CMT_TOP_SW2A2_6", - "CMT_TOP_IMUX26_0", - "CMT_TOP_SW4A0_5", - "CMT_TOP_EE2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EL1BEG2_5", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_TOP_EE2A0_6", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX23_1", - "CMT_PHASER_BOT_REFMUX_2", - "CMT_TOP_IMUX15_2", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX3_6", - "CMT_TOP_BYP0_0", - "CMT_TOP_SW4END0_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX47_6", - "CMT_TOP_SW4A2_5", - "CMT_TOP_EE2BEG1_6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_BYP3_4", - "CMT_TOP_CTRL1_6", - "CMT_BOT_HCLKMUX_CLKINT_0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_WW4C2_1", - "CMT_TOP_BYP1_3", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX43_3", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_TOP_NW4A2_8", - "CMT_PHASER_IN_A_RCLK0", - "CMT_TOP_NE2A1_3", - "CMT_TOP_WR1END3_6", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NW4END1_1", - "CMT_TOP_CLK1_5", - "CMT_TOP_WW4C1_0", - "CMT_TOP_EE4B3_3", - "CMT_TOP_ICLK_5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_PHASERA_CTSBUS0", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW2END2_4", - "CMT_TOP_NW4END1_7", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_IMUX9_2", - "CMT_TOP_NW4A0_1", - "CMT_TOP_WW4END0_0", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_WW4B3_6", - "CMT_PHASER_IN_B_WREN_TOFIFO", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_LH1_0", - "CMT_TOP_IMUX18_5", - "CMT_TOP_SE2A1_7", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_TOP_SW2A1_1", - "CMT_TOP_OCLK1X_90_7", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_TOP_LH10_5", - "CMT_TOP_EE4A3_4", - "CMT_TOP_IMUX20_5", - "CMT_TOP_NW2A2_3", - "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "CMT_TOP_IMUX15_0", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_TOP_EE4A1_5", - "CMT_TOP_SE2A3_1", - "CMT_TOP_BYP0_4", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_TOP_IMUX24_8", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LH3_5", - "CMT_PHASER_B_OCLKDIV_TOIOI", - "CMT_TOP_IMUX26_2", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_TOP_IMUX19_8", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_IMUX42_1", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_SE2A1_3", - "CMT_TOP_IMUX8_5", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_TOP_CLK1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_WW4A2_0", - "CMT_TOP_IMUX23_4", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_TOP_WW4A2_3", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX17_3", - "MMCM_CLK_FREQBB_REBUFOUT1", - "CMT_PHASER_B_TOMMCM_ICLKDIV", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_EE4A1_4", - "CMT_TOP_IMUX16_4", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_LH1_8", - "CMT_TOP_IMUX46_5", - "CMT_TOP_NE2A0_1", - "CMT_TOP_LH11_1", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_WR1END2_8", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_IMUX3_5", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_EE2BEG1_0", - "CMT_PHASER_IN_DB_RCLK", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX26_7", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_FAN4_1", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_SE4C1_6", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2A3_6", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_IMUX24_3", - "CMT_TOP_BYP0_2", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_NW4END0_1", - "CMT_LR_LOWER_T_CLK_MMCM3", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_FAN3_6", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SE4BEG3_0", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_TOP_WW4A2_7", - "CMT_TOP_NW4A2_1", - "CMT_TOP_SW4A3_2", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW4C3_8", - "CMT_TOP_NE2A0_8", - "CMT_TOP_FAN4_4", - "CMT_TOP_WW4C3_0", - "CMT_TOP_NE2A2_3", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_SW2A2_4", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_PHASER_OUT_A_OCLKDIV", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_TOP_NE4C0_8", - "CMT_TOP_FAN3_0", - "CMT_TOP_IMUX6_3", - "CMT_TOP_NE4C0_3", - "CMT_TOP_IMUX35_3", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_TOP_NE4C2_4", - "CMT_TOP_SW2A0_7", - "CMT_PHASER_BOT_ENCALIB0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_NE4C0_1", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_WL1END3_4", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_TOP_SE4C2_1", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_CTRL0_1", - "CMT_TOP_NW4END3_5", - "CMT_TOP_IMUX2_4", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_WW2A2_7", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_FAN2_5", - "CMT_TOP_WR1END0_5", - "CMT_TOP_IMUX17_2", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_TOP_WL1END3_0", - "CMT_PHASER_IN_DB_ICLK", - "CMT_TOP_SW4A1_4", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX36_1", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE4A3_2", - "CMT_TOP_IMUX27_6", - "CMT_TOP_LH3_6", - "CMT_TOP_WW2END2_0", - "CMT_TOP_IMUX11_7", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_TOP_IMUX43_2", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_TOP_IMUX17_5", - "CMT_TOP_ER1BEG0_3", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C1_6", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_TOP_BYP1_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_NE4BEG1_0", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_CA_TESTIN4", - "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_IMUX7_0", - "CMT_TOP_NE4C1_8", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_WW2A0_8", - "CMT_TOP_SE4C2_8", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_IMUX26_4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_TOP_IMUX38_8", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_LH1_3", - "CMT_TOP_BYP1_2", - "CMT_TOP_IMUX26_5", - "CMT_TOP_BYP4_3", - "CMT_TOP_FAN5_2", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_IMUX29_3", - "CMT_PHASER_IN_A_WRCLK_TOFIFO", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_TOP_EE4C1_7", - "CMT_LR_LOWER_T_CLK_MMCM9", - "CMT_TOP_IMUX29_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4C0_1", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_IMUX38_6", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_TOP_WW4B3_4", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_TOP_NW2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_EE4B0_3", - "MMCM_CLK_FREQBB_REBUFOUT3", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_TOP_WW4B2_8", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_TOP_NW4A2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_TOP_WW4C2_6", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_IMUX36_7", - "CMT_TOP_NE2A3_7", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_NW4END0_8", - "CMT_TOP_FAN5_1", - "CMT_TOP_IMUX39_8", - "CMT_TOP_WW4B0_5", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_IMUX32_6", - "CMT_TOP_NE4BEG1_5", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_BYP4_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_LH3_7", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_NE4BEG3_2", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_TOP_WR1END1_7", - "CMT_TOP_NW2A0_5", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_TOP_BYP3_1", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_MONITOR_N_0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_TOP_SW2A0_5", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_LH9_2", - "CMT_TOP_WW2A2_4", - "CMT_TOP_IMUX40_6", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_WL1END3_3", - "CMT_TOP_NW4A3_0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_TOP_LH9_8", - "CMT_TOP_FAN0_2", - "CMT_TOP_IMUX7_5", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_TOP_IMUX19_1", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_IMUX41_0", - "CMT_TOP_WW4A0_5", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_FAN3_2", - "CMT_TOP_IMUX12_7", - "CMT_TOP_WW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW2A3_6", - "CMT_PHASERREF_DOWN_PHASEROUT_A", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_TOP_WW2A1_7", - "CMT_TOP_EE4B3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_IMUX4_7", - "CMT_TOP_EE4A0_4", - "CMT_TOP_IMUX1_7", - "CMT_TOP_WW4A0_6", - "CMT_TOP_EE4B0_0", - "CMT_TOP_NW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_EE4C2_0", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_SE4C0_0", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_TOP_NW2A3_3", - "CMT_TOP_SE4C0_8", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4END2_3", - "CMT_TOP_LH1_2", - "CMT_TOP_SW4END0_8", - "CMT_TOP_FAN3_5", - "CMT_TOP_LH1_5", - "CMT_PHASER_BOT_SYNC_BB", - "CMT_TOP_SE2A1_6", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_LR_LOWER_T_CLK_MMCM1", - "CMT_TOP_SW4END2_1", - "CMT_TOP_EE4B3_4", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_TOP_SW4END1_3", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_IMUX25_6", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_LH9_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_LH11_5", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_WR1END0_2", - "CMT_TOP_IMUX30_5", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX37_3", - "CMT_TOP_MONITOR_P_5", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW2END2_8", - "CMT_TOP_EE4C2_6", - "CMT_TOP_IMUX38_7", - "CMT_TOP_NW2A1_3", - "CMT_TOP_IMUX36_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_EE4A2_5", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_TOP_WW4A3_3", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_TOP_LH2_8", - "CMT_TOP_IMUX17_8", - "CMT_TOP_NE2A2_0", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_TOP_WW4C1_2", - "CMT_TOP_IMUX29_8", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_ER1BEG3_6", - "CMT_PHASER_BOT_REFMUX_1", - "CMT_TOP_CLK0_7", - "CMT_TOP_EE2A1_3", - "CMT_TOP_SW4END1_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_FAN7_1", - "CMT_TOP_LH11_3", - "CMT_TOP_IMUX13_3", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_WW4A3_2", - "CMT_TOP_NE4C0_6", - "CMT_TOP_BYP0_3", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_TOP_EE4A0_2", - "CMT_TOP_SE4C2_2", - "CMT_TOP_NW4A1_3", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX3_7", - "CMT_TOP_LH10_4", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_IMUX8_4", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_TOP_LH3_1", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW2A1_6", - "CMT_PHASER_OUT_A_OCLK", - "CMT_TOP_IMUX26_3", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_NW2A2_0", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "MMCM_CLK_FREQBB_REBUFOUT2", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_IMUX25_3", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_TOP_IMUX11_8", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_EE2BEG1_5", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_TOP_IMUX8_2", - "CMT_PHASER_DOWN_PHASERREF1", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_WW2END1_6", - "CMT_PHASER_OUT_B_OCLKDIV", - "CMT_TOP_WW2A3_3", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_TOP_EE4A2_3", - "CMT_TOP_WR1END2_2", - "CMT_TOP_SW4A1_1", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_8", - "CMT_TOP_WW4A1_6", - "CMT_TOP_IMUX41_2", - "CMT_TOP_LH8_6", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW2A1_5", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_CTRL1_1", - "CMT_TOP_SE4C1_8", - "CMT_TOP_WR1END1_3", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_WW4A2_6", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP0_6", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_IMUX43_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX31_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WL1END1_7", - "CMT_TOP_LH2_7", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_TOP_WW4END1_2", - "CMT_TOP_LH7_7", - "CMT_TOP_WR1END3_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_IMUX26_8", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_NW4A0_4", - "CMT_TOP_IMUX24_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_WR1END2_5", - "CMT_TOP_NW4END1_4", - "CMT_TOP_WW4C1_8", - "CMT_TOP_NW2A0_7", - "CMT_TOP_IMUX22_1", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_TOP_IMUX17_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_NW2A1_6", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX4_1", - "CMT_TOP_BYP2_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_NW4END2_3", - "CMT_TOP_EE2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_TOP_EE4C1_8", - "CMT_TOP_CLK1_4", - "CMT_TOP_LH2_2", - "CMT_TOP_NE4BEG2_7", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_TOP_NE4C2_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_EE4A2_7", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE4C2_4", - "CMT_PHASER_IN_CA_RST", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_IMUX11_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_NW4A1_4", - "CMT_PHASER_B_OCLK_TOIOI", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_SW2A0_3", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX38_3", - "CMT_TOP_EE4C2_2", - "CMT_TOP_WW4END0_4", - "CMT_TOP_IMUX5_6", - "CMT_TOP_NW4END2_2", - "CMT_TOP_BYP0_7", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_NE2A2_4", - "CMT_TOP_LH9_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4B0_6", - "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_NW4A1_5", - "CMT_TOP_IMUX28_5", - "CMT_TOP_SE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_SW2A2_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_IMUX9_7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_PHASER_OUT_A_RDCLK_TOFIFO", - "CMT_TOP_IMUX9_1", - "CMT_TOP_WW2A2_2", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_TOP_BYP7_8", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX4_4", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_IMUX30_1", - "CMT_TOP_WW4C0_5", - "CMT_TOP_NW4A1_2", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_WW2END0_2", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX45_5", - "CMT_TOP_FAN0_0", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_IMUX25_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX18_8", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_IMUX35_5", - "CMT_TOP_EE2A0_7", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_TOP_WW4B2_4", - "CMT_TOP_IMUX20_4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_TOP_EE4C3_6", - "CMT_TOP_FAN2_8", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_TOP_SE4BEG0_8", - "CMT_PHASER_B_TOMMCM_OCLK", - "CMT_TOP_SW2A1_0", - "CMT_TOP_WL1END0_5", - "CMT_LR_LOWER_T_CLK_PERF0", - "CMT_TOP_NE4C0_2", - "CMT_TOP_EE4B1_2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_TOP_IMUX10_3", - "CMT_TOP_SE4C1_1", - "CMT_TOP_IMUX29_4", - "CMT_TOP_FAN2_3", - "CMT_TOP_NE4C2_1", - "CMT_TOP_IMUX30_2", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2A2_2", - "CMT_TOP_IMUX31_5", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WW4A2_8", - "CMT_TOP_IMUX8_7", - "CMT_TOP_CTRL1_7", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_IMUX23_8", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_TOP_SW4END0_6", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_IMUX12_2", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_BYP6_6", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_TOP_WL1END2_7", - "CMT_TOP_EE4C1_4", - "CMT_TOP_BYP5_1", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_TOP_IMUX46_6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_TOP_NW4END0_7", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_BYP3_8", - "CMT_TOP_IMUX33_0", - "CMT_TOP_IMUX16_8", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_SW4END3_7", - "CMT_TOP_WW2A1_4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_TOP_OCLK_7", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_IMUX19_7", - "CMT_TOP_WW2END3_0", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_SE2A0_5", - "CMT_TOP_WW2A1_0", - "CMT_TOP_NW4A2_5", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_SE4C0_6", - "CMT_TOP_NE4BEG1_3", - "CMT_LR_LOWER_T_CLK_MMCM8", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_TOP_IMUX3_0", - "CMT_TOP_WL1END1_8", - "CMT_TOP_NW4END1_5", - "CMT_TOP_WW4END2_1", - "CMT_TOP_NW2A2_5", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_TOP_BYP5_6", - "CMT_TOP_LH6_2", - "CMT_TOP_IMUX39_6", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_PHASER_OUT_DB_RST", - "CMT_TOP_SE2A0_4", - "CMT_TOP_IMUX36_2", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_IMUX6_5", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_WW2A0_5", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_EE4A2_8", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX7_6", - "CMT_TOP_BYP2_0", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_TOP_IMUX8_3", - "CMT_TOP_ICLK_6", - "CMT_TOP_LH2_0", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_TOP_IMUX16_3", - "CMT_TOP_WW4B3_2", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_IMUX40_2", - "CMT_TOP_EE4C0_4", - "CMT_TOP_BYP2_1", - "CMT_TOP_IMUX36_8", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_NW2A3_5", - "CMT_TOP_IMUX27_3", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_TOP_WW4END3_1", - "CMT_TOP_SW4A2_4", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_WW4C2_2", - "CMT_TOP_IMUX46_2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_TOP_BYP1_6", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NW4A3_2", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_EE4A1_0", - "CMT_PHASER_BOT_OBURSTPENDING1", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX19_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_IMUX8_8", - "CMT_TOP_NW2A3_7", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_NW4A3_8", - "CMT_TOP_SW4END2_8", - "CMT_TOP_EL1BEG0_6", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_TOP_IMUX37_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_SE2A2_1", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_TOP_WW2END0_7", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_EE4C0_7", - "CMT_TOP_WL1END0_0", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_FAN7_2", - "CMT_TOP_WL1END3_1", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_WR1END3_5", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_TOP_LH8_4", - "CMT_TOP_LH5_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_IMUX13_0", - "CMT_TOP_SW4A0_6", - "CMT_TOP_WW2A3_2", - "CMT_TOP_BYP5_0", - "CMT_TOP_NE4C2_8", - "CMT_TOP_IMUX40_3", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_BYP7_4", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_TOP_LH10_6", - "CMT_TOP_SE4C2_4", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_PHASER_DOWN_PHASERREF0", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX46_4", - "CMT_TOP_LH4_2", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_TESTOUT1", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "CMT_TOP_EE4A3_8", - "CMT_TOP_IMUX44_3", - "CMT_TOP_NE4C3_5", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX14_5", - "CMT_TOP_BYP3_5", - "CMT_TOP_IMUX32_8", - "CMT_PHASER_IN_DB_STG1REGR1", - "CMT_TOP_IMUX34_5", - "CMT_TOP_EE4C1_0", - "CMT_PHASER_IN_B_WRCLK_TOFIFO", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_IMUX29_1", - "CMT_PHASER_BOT_IRANKB0", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SE4C3_5", - "CMT_TOP_BYP7_1", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_TOP_WL1END3_8", - "CMT_TOP_IMUX45_7", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX17_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_OCLK_0", - "CMT_PHASER_IN_A_ICLK", - "CMT_TOP_IMUX31_7", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_TOP_FAN6_4", - "CMT_PHASER_IN_A_WREN_TOFIFO", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_TOP_IMUX2_2", - "CMT_TOP_WW4END3_5", - "CMT_TOP_IMUX21_7", - "CMT_TOP_LH1_1", - "CMT_TOP_FAN5_8", - "CMT_TOP_NW4END3_8", - "CMT_TOP_WW2END0_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LH5_2", - "CMT_TOP_WW4A1_1", - "CMT_TOP_IMUX17_4", - "CMT_TOP_SW2A1_8", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_TOP_NE4BEG3_1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_TOP_EE2A3_2", - "CMT_TOP_LH3_8", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_TOP_WW2END0_4", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_EE2A1_7", - "CMT_TOP_WW2END2_3", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END2_6", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_PHASER_B_TOMMCM_ICLK", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE4B2_1", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_TOP_NW4END3_1", - "CMT_TOP_MONITOR_N_4", - "CMT_LR_LOWER_T_CLK_MMCM12", - "CMT_TOP_LH3_0", - "CMT_TOP_LH2_5", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_NW4A2_3", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2A0_2", - "CMT_TOP_IMUX5_4", - "CMT_TOP_SW4END2_6", - "CMT_TOP_IMUX47_1", - "CMT_TOP_WW2A2_1", - "CMT_TOP_NW2A1_7", - "CMT_TOP_SW4END3_0", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX34_8", - "CMT_TOP_LH7_4", - "CMT_TOP_EE4C0_2", - "CMT_TOP_IMUX39_3", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_TOP_IMUX45_3", - "CMT_TOP_NW2A3_1", - "CMT_TOP_IMUX31_6", - "CMT_TOP_WW4C1_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_WW4B3_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_NE2A2_2", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX33_7", - "CMT_TOP_FAN5_3", - "CMT_TOP_NW4A2_0", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_BYP7_0", - "CMT_TOP_LH6_0", - "CMT_TOP_NE4C1_4", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_TOP_LH5_4", - "CMT_TOP_CLK0_4", - "CMT_TOP_IMUX22_8", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_WW4A3_4", - "CMT_TOP_IMUX5_2", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "CMT_TOP_NW4A1_6", - "CMT_TOP_FAN1_2", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_SW4A3_4", - "CMT_TOP_WW4B2_6", - "CMT_TOP_CLK0_0", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_LH8_7", - "CMT_TOP_IMUX32_5", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_SW2A1_5", - "CMT_TOP_IMUX32_7", - "CMT_PHASER_B_ICLKDIV_TOIOI", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_WR1END0_1", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_BYP2_3" - ], - "sites": [ - { - "prefix": "PHASER_OUT_PHY", - "y_coord": 0, - "type": "PHASER_OUT_PHY", - "site_pins": { - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "RST": "CMT_PHASER_OUT_CA_RST", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "PHASER_IN_PHY", - "y_coord": 0, - "type": "PHASER_IN_PHY", - "site_pins": { - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", - "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", - "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", - "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", - "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", - "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", - "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", - "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "ICLK": "CMT_PHASER_IN_CA_ICLK", - "RCLK": "CMT_PHASER_IN_CA_RCLK", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", - "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", - "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", - "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", - "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", - "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", - "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", - "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", - "SCANIN": "CMT_PHASER_IN_CA_SCANIN", - "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", - "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", - "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", - "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", - "STG1READ": "CMT_PHASER_IN_CA_STG1READ", - "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", - "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", - "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", - "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", - "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", - "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", - "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", - "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", - "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", - "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", - "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", - "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", - "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", - "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", - "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", - "SCANENB": "CMT_PHASER_IN_CA_SCANENB", - "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", - "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", - "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", - "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", - "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", - "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", - "RST": "CMT_PHASER_IN_CA_RST", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", - "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", - "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", - "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", - "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", - "FINEINC": "CMT_PHASER_IN_CA_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", - "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", - "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", - "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", - "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", - "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", - "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", - "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", - "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", - "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", - "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "PHASER_OUT_PHY", - "y_coord": 1, - "type": "PHASER_OUT_PHY", - "site_pins": { - "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", - "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", - "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", - "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", - "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", - "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", - "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", - "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", - "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", - "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", - "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", - "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", - "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", - "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", - "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", - "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", - "OCLK": "CMT_PHASER_OUT_DB_OCLK", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", - "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", - "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", - "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", - "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", - "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", - "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", - "RST": "CMT_PHASER_OUT_DB_RST", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", - "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", - "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", - "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", - "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", - "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", - "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", - "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", - "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", - "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", - "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", - "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", - "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", - "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "PHASER_IN_PHY", - "y_coord": 1, - "type": "PHASER_IN_PHY", - "site_pins": { - "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", - "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", - "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", - "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", - "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", - "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", - "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", - "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", - "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "ICLK": "CMT_PHASER_IN_DB_ICLK", - "RCLK": "CMT_PHASER_IN_DB_RCLK", - "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", - "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", - "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", - "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", - "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", - "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", - "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", - "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", - "SCANIN": "CMT_PHASER_IN_DB_SCANIN", - "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", - "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", - "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", - "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", - "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", - "STG1READ": "CMT_PHASER_IN_DB_STG1READ", - "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", - "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", - "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", - "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", - "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", - "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", - "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", - "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", - "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", - "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", - "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", - "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", - "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", - "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", - "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", - "SCANENB": "CMT_PHASER_IN_DB_SCANENB", - "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", - "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", - "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", - "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", - "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", - "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", - "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", - "RST": "CMT_PHASER_IN_DB_RST", - "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", - "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", - "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", - "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", - "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", - "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", - "FINEINC": "CMT_PHASER_IN_DB_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", - "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", - "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", - "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", - "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", - "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", - "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", - "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", - "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", - "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", - "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", - "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_A_ICLK": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_ICLK", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { - "can_invert": "0", - "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK1_8", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_6->CMT_PHASER_IN_DB_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX29_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLKDIV->>CMT_PHASER_B_ICLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_B_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX12_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK->>CMT_PHASER_B_OCLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_B_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_5->CMT_PHASER_OUT_DB_COARSEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKA1->CMT_PHASER_IN_CA_RANKSELPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IRANKA1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_WRENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_OCLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_TOMMCM_OCLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_A_RCLK0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_RCLK0", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_RCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B18_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_B->CMT_PHASER_IN_DB_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_A->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_A", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING1->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_OBURSTPENDING1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", - "is_pseudo": "1" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_6->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_CTSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX28_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_A_WREN_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_WREN_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_WRENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT3->>MMCM_CLK_FREQBB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT3", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX41_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX9_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT0->>MMCM_CLK_FREQBB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT0", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKB1->CMT_PHASER_IN_DB_RANKSELPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IRANKB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX11_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_DQSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING0->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_OBURSTPENDING0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->CMT_PHASER_B_TOMMCM_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_TOMMCM_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_7->CMT_PHASER_IN_DB_RANKSEL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B16_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_DTSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT1->>MMCM_CLK_FREQBB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT1", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX12_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { - "can_invert": "0", - "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_8", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO->CMT_PHASER_IN_B_ICLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_ICLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX39_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_ICLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_A->CMT_PHASER_OUT_CA_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX8_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_5->CMT_PHASER_OUT_DB_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_A->CMT_PHASER_IN_CA_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_CTSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_DTSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO->CMT_PHASER_IN_A_ICLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_ICLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_A_WRCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_7->CMT_PHASER_IN_DB_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKB0->CMT_PHASER_IN_DB_RANKSELPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IRANKB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B6_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B1_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING0->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IBURSTPENDING0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_ICLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_TOMMCM_ICLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX25_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING1->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IBURSTPENDING1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_B_OCLK1X_90": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90", - "is_directional": "1", "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90" }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING1->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_2", + "src_wire": "CMT_PHASER_BOT_IBURSTPENDING1", "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY" }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK1X_90_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK90_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT2->>MMCM_CLK_FREQBB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT2", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", - "is_pseudo": "1" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX32_2->CMT_PHASER_OUT_CA_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX25_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->CMT_PHASER_B_TOMMCM_ICLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_TOMMCM_ICLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV->>CMT_PHASER_B_OCLKDIV_TOIOI": { "can_invert": "0", - "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_directional": "1", "src_wire": "CMT_PHASER_OUT_B_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI" }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "src_wire": "CMT_PHASER_BOT_REFMUX_0", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX21_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK" }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO", + "src_wire": "CMT_TOP_IMUX41_2", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE" }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2" }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", + "src_wire": "CMT_TOP_IMUX14_4", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK90_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLK->>CMT_PHASER_B_ICLK_TOIOI": { "can_invert": "0", - "dst_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_directional": "1", "src_wire": "CMT_PHASER_IN_B_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_B->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_B", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_ICLK_TOIOI" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_0": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_0", - "is_directional": "1", "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_3", "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0" }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_5", + "src_wire": "CMT_TOP_IMUX45_4", "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_DQSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKA0->CMT_PHASER_IN_CA_RANKSELPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IRANKA0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX44_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0" }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_6", + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B18_4": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_4" }, - "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_B->CMT_PHASER_OUT_DB_PHASEREFCLK": { + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "src_wire": "CMT_TOP_IMUX0_5", "is_directional": "1", - "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST" }, - "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_RCLK1", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_RCLK", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1" }, - "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_ICLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT0->>MMCM_CLK_FREQBB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_6": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_6", - "is_directional": "1", "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_RCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_RCLK1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_A->CMT_PHASER_OUT_CA_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT2->>MMCM_CLK_FREQBB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKB0->CMT_PHASER_IN_DB_RANKSELPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IRANKB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_7->CMT_PHASER_IN_DB_RANKSEL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_ICLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_ICLKDIV" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYSCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKB1->CMT_PHASER_IN_DB_RANKSELPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IRANKB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_DB_RCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT3->>MMCM_CLK_FREQBB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_OCLKDIV" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING0->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IBURSTPENDING0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_5->CMT_PHASER_OUT_DB_COARSEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B16_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_3" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX12_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RST" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYNCIN" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX9_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_A_WREN_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_WRENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_WREN_TOFIFO" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_CA_RCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_CTSBUS1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_7->CMT_PHASER_IN_DB_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RST" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DTSBUS0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_EDGEADV" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_WRENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT1->>MMCM_CLK_FREQBB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->CMT_PHASER_B_TOMMCM_ICLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_ICLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_ICLKDIV->>CMT_PHASER_B_ICLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_B_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_ICLKDIV_TOIOI" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_EDGEADV" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_A_ICLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_ICLK" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEINC" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKA1->CMT_PHASER_IN_CA_RANKSELPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IRANKA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_A_RCLK0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_RCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_RCLK0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_A->CMT_PHASER_IN_CA_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX23_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYSCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKA0->CMT_PHASER_IN_CA_RANKSELPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IRANKA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_RST" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_B->CMT_PHASER_OUT_DB_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING0->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_OBURSTPENDING0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B6_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DQSBUS1" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX23_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_B->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_6->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING1->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_OBURSTPENDING1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO->CMT_PHASER_IN_B_ICLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_ICLKDIV" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX32_2->CMT_PHASER_OUT_CA_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEINC" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK->>CMT_PHASER_B_OCLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_B_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLK_TOIOI" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_CTSBUS0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX25_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DTSBUS1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_A->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_A", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEINC" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B1_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_5->CMT_PHASER_OUT_DB_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_RST" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->CMT_PHASER_B_TOMMCM_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_OCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX23_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_B->CMT_PHASER_IN_DB_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DQSBUS0" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_6->CMT_PHASER_IN_DB_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEINC" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_A_WRCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYNCIN" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1" + }, + "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO->CMT_PHASER_IN_A_ICLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_ICLKDIV" } }, - "tile_type": "CMT_TOP_L_LOWER_T" + "wires": [ + "CMT_PHASER_IN_B_WREN_TOFIFO", + "CMT_PHASER_IN_DB_TESTIN3", + "CMT_LR_LOWER_T_CLK_IN1_HCLK", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_NW4A2_6", + "CMT_TOP_WW2END3_2", + "CMT_TOP_WW2END3_3", + "CMT_TOP_BYP1_3", + "CMT_PHASER_OUT_CA_DIVIDERST", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_PHASER_IN_CA_STG1REGL7", + "CMT_PHASER_OUT_DB_TESTIN14", + "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_NE4C0_2", + "CMT_TOP_FAN6_7", + "CMT_PHASER_IN_DB_STG1REGR4", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_LH7_5", + "CMT_TOP_IMUX19_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_FAN0_2", + "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "CMT_TOP_IMUX47_5", + "CMT_TOP_IMUX27_3", + "CMT_TOP_NW4A1_2", + "CMT_TOP_FAN6_0", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_IMUX24_0", + "CMT_TOP_IMUX26_0", + "CMT_PHASER_OUT_DB_PHASEREFCLK", + "CMT_TOP_WW2A1_6", + "CMT_TOP_WR1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_WW4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_PHASER_IN_CA_TESTIN3", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_PHASER_OUT_DB_TESTIN4", + "CMT_TOP_WW4END1_8", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_NE4C0_6", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WW4END2_8", + "CMT_TOP_EE4C0_0", + "CMT_PHASER_IN_B_ICLKDIV", + "CMT_TOP_IMUX7_3", + "CMT_TOP_WW4B3_6", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_BYP6_2", + "CMT_PHASER_IN_A_WREN_TOFIFO", + "CMT_TOP_SE4C1_8", + "CMT_PHASER_IN_DB_STG1REGR1", + "CMT_TOP_EE2A0_2", + "CMT_TOP_LH3_8", + "CMT_TOP_WW4B0_5", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_IMUX41_8", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WL1END3_5", + "CMT_PHASER_IN_DB_TESTOUT3", + "CMT_TOP_IMUX36_7", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_IMUX32_8", + "CMT_TOP_SE4C1_7", + "CMT_PHASER_IN_CA_TESTOUT2", + "CMT_TOP_IMUX45_7", + "CMT_TOP_WW2END3_5", + "CMT_TOP_SW4END0_1", + "CMT_TOP_EE2A3_4", + "CMT_TOP_IMUX12_8", + "CMT_TOP_NW4END3_1", + "CMT_TOP_IMUX13_0", + "CMT_PHASER_OUT_CA_FREQREFCLK", + "CMT_TOP_EE2BEG1_3", + "CMT_PHASER_OUT_CA_TESTIN3", + "CMT_TOP_IMUX29_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_NE2A3_0", + "CMT_PHASER_OUT_DB_ENCALIB0", + "CMT_TOP_SW4END3_1", + "CMT_TOP_CLK1_3", + "CMT_TOP_IMUX5_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "CMT_TOP_WR1END0_8", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_FAN2_8", + "CMT_PHASER_IN_CA_PHASEREFCLK", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4C0_8", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "CMT_PHASER_B_TOMMCM_ICLK", + "CMT_PHASER_IN_CA_TESTIN5", + "CMT_PHASER_IN_DB_PHASEREFCLK", + "CMT_TOP_IMUX15_4", + "CMT_TOP_EE4BEG0_0", + "CMT_PHASER_IN_DB_SCANIN", + "CMT_PHASER_IN_CA_STG1REGR4", + "CMT_PHASER_OUT_CA_DQSBUS0", + "CMT_TOP_SE4BEG3_5", + "CMT_PHASER_OUT_DB_MEMREFCLK", + "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "CMT_TOP_EE2A1_0", + "CMT_TOP_WW4A1_1", + "CMT_TOP_EE4B3_0", + "CMT_PHASER_IN_DB_TESTIN12", + "CMT_TOP_BYP4_1", + "CMT_TOP_EE4B0_1", + "CMT_TOP_SE4BEG3_4", + "CMT_PHASER_IN_DB_SCANENB", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_OCLK_7", + "CMT_TOP_WW4C0_3", + "CMT_TOP_SE4BEG2_5", + "CMT_PHASER_IN_CA_TESTIN2", + "CMT_TOP_EE4C2_1", + "CMT_PHASER_OUT_DB_SYNCIN", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_IMUX1_1", + "CMT_TOP_NW4A2_2", + "CMT_TOP_NE4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_CLK0_3", + "CMT_TOP_IMUX14_1", + "CMT_TOP_IMUX35_6", + "CMT_TOP_EE4A0_6", + "CMT_TOP_FAN5_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_NE4BEG2_5", + "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "CMT_TOP_NE2A1_0", + "CMT_TOP_IMUX3_4", + "CMT_TOP_SE4BEG1_6", + "CMT_PHASER_DOWN_DQS_TO_PHASER_B", + "CMT_TOP_IMUX2_7", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX39_7", + "CMT_TOP_IMUX14_2", + "CMT_PHASER_IN_DB_TESTIN10", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW4C3_6", + "CMT_TOP_WW4C3_2", + "CMT_TOP_EE4C0_4", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX28_8", + "CMT_TOP_NW4END0_3", + "CMT_TOP_EE4B3_8", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW4END1_5", + "CMT_TOP_LH2_6", + "CMT_PHASER_B_OCLK90_TOIOI", + "CMT_PHASER_BOT_IRANKA0", + "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "CMT_PHASER_OUT_CA_BURSTPENDING", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_BYP4_8", + "CMT_TOP_EE4C1_6", + "CMT_PHASER_OUT_DB_FINEINC", + "CMT_TOP_EE2A0_1", + "CMT_TOP_EE4A2_7", + "CMT_TOP_NW2A0_4", + "CMT_TOP_WW4B0_6", + "CMT_TOP_WW4A0_4", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_LH12_7", + "CMT_TOP_WW2END1_7", + "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "CMT_TOP_LH6_2", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX1_3", + "CMT_TOP_IMUX45_8", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_EE2A0_3", + "CMT_LR_LOWER_T_CLK_MMCM1", + "CMT_TOP_IMUX33_4", + "CMT_TOP_BYP7_3", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "CMT_LR_LOWER_T_CLK_MMCM12", + "CMT_TOP_IMUX30_7", + "CMT_TOP_ICLK_4", + "CMT_PHASER_IN_CA_STG1REGR1", + "CMT_TOP_SW2A0_5", + "CMT_TOP_EE4C3_8", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_IMUX35_2", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_PHASER_OUT_DB_CTSBUS1", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN7_7", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_WW2END1_0", + "CMT_TOP_NW4END1_7", + "CMT_TOP_IMUX30_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_WW2A0_5", + "CMT_TOP_WW4C1_0", + "CMT_TOP_CLK1_8", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_IMUX14_3", + "CMT_TOP_SW4END3_2", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "CMT_TOP_WL1END0_5", + "CMT_TOP_SW4END1_5", + "CMT_TOP_NE2A0_2", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_PHASER_OUT_DB_BURSTPENDING", + "CMT_TOP_FAN3_8", + "CMT_TOP_IMUX27_7", + "CMT_TOP_NE4C0_1", + "CMT_TOP_WW4END1_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LH8_6", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "CMT_TOP_SW2A1_5", + "CMT_TOP_EE4A0_1", + "CMT_TOP_IMUX33_6", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_WL1END2_3", + "CMT_TOP_EE4B3_3", + "CMT_TOP_WW4A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_WW2END2_1", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4END1_6", + "CMT_TOP_IMUX25_4", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_SW4END1_0", + "CMT_PHASER_OUT_CA_CTSBUS0", + "CMT_TOP_EE2A1_1", + "CMT_TOP_WL1END2_4", + "CMT_TOP_SE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_IMUX11_4", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_IMUX3_3", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WR1END0_2", + "CMT_TOP_BYP7_4", + "CMT_R_TOP_LOWER_B_CLKINT_1", + "CMT_TOP_EE4A3_6", + "CMT_TOP_NE2A2_7", + "CMT_PHASER_IN_DB_RSTDQSFIND", + "CMT_TOP_WR1END0_4", + "CMT_PHASER_IN_CA_TESTIN6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_SW4A2_0", + "CMT_PHASER_OUT_DB_TESTOUT0", + "CMT_PHASER_OUT_CA_FINEINC", + "CMT_TOP_BYP1_1", + "CMT_TOP_LH11_6", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WR1END0_3", + "CMT_PHASER_IN_DB_TESTOUT0", + "CMT_TOP_WW4B3_5", + "CMT_TOP_EL1BEG1_6", + "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "CMT_PHASER_OUT_CA_ENCALIB0", + "CMT_TOP_EE2A0_5", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH4_7", + "CMT_TOP_BYP6_0", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WR1END1_6", + "CMT_TOP_ER1BEG1_2", + "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "CMT_TOP_SE4C0_2", + "CMT_TOP_EE4A1_2", + "CMT_PHASER_OUT_B_OCLKDIV", + "CMT_PHASER_OUT_CA_TESTOUT3", + "CMT_TOP_EE4A2_8", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_SE2A1_1", + "CMT_TOP_IMUX14_4", + "CMT_TOP_NW4END1_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_IMUX31_3", + "CMT_TOP_EE4C1_8", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_WW4END1_4", + "CMT_TOP_CTRL0_5", + "CMT_PHASER_IN_DB_STG1REGL3", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_EE4A0_3", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_SW4A1_5", + "CMT_TOP_SE4C0_0", + "CMT_TOP_IMUX43_3", + "CMT_TOP_FAN1_5", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_NW2A0_7", + "CMT_TOP_EE4B2_1", + "CMT_TOP_IMUX31_7", + "CMT_TOP_SW2A1_0", + "CMT_TOP_WW4B2_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_SE4BEG1_7", + "CMT_PHASER_IN_CA_ISERDESRST", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_IMUX47_0", + "CMT_TOP_EE2A0_0", + "CMT_PHASER_IN_DB_DIVIDERST", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "CMT_TOP_CTRL1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX21_0", + "CMT_TOP_IMUX10_2", + "CMT_TOP_WW4A1_2", + "CMT_TOP_SW4A0_8", + "CMT_TOP_WW4C3_4", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_CLK0_0", + "CMT_TOP_LH9_7", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END3_7", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_IMUX38_2", + "CMT_TOP_EE4A3_0", + "CMT_TOP_WW2A3_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "CMT_TOP_NW2A3_1", + "CMT_TOP_BYP3_5", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_NW2A1_2", + "CMT_TOP_SW2A3_4", + "CMT_TOP_SW4END1_1", + "CMT_TOP_ER1BEG1_6", + "CMT_PHASER_OUT_CA_FINEENABLE", + "CMT_TOP_NW4A1_1", + "CMT_TOP_IMUX42_8", + "CMT_TOP_WW2A2_4", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "CMT_TOP_IMUX30_2", + "CMT_TOP_IMUX45_1", + "CMT_TOP_WW4B3_0", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_EE4A3_4", + "CMT_TOP_SE4C2_5", + "CMT_TOP_WW4END2_7", + "CMT_TOP_LH9_5", + "CMT_TOP_LH3_6", + "CMT_TOP_NE2A0_3", + "CMT_TOP_IMUX12_0", + "CMT_TOP_EE2A2_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_IMUX11_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "CMT_TOP_IMUX24_3", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_IMUX9_8", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "CMT_TOP_IMUX24_2", + "CMT_TOP_IMUX26_4", + "CMT_LR_LOWER_T_CLK_MMCM7", + "CMT_TOP_LH3_0", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_WW2A1_1", + "CMT_PHASER_IN_DB_STG1REGR6", + "CMT_TOP_IMUX38_1", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_LH2_0", + "CMT_TOP_NW4A1_0", + "CMT_PHASER_IN_CA_STG1REGL8", + "CMT_TOP_IMUX22_2", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX2_8", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_BYP1_8", + "CMT_TOP_IMUX31_1", + "CMT_PHASER_OUT_DB_SCANIN", + "CMT_PHASER_IN_CA_TESTIN7", + "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "CMT_TOP_SW4A3_2", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_IMUX36_8", + "CMT_TOP_SW4END1_2", + "CMT_PHASER_IN_DB_SELCALORSTG1", + "CMT_TOP_SW4A1_0", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "CMT_PHASERA_DQSBUS0", + "CMT_TOP_EE4C0_5", + "CMT_TOP_WL1END1_4", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_LH7_0", + "CMT_TOP_IMUX33_7", + "CMT_TOP_WW2A1_4", + "CMT_TOP_SE4C1_2", + "CMT_TOP_ER1BEG1_0", + "CMT_LR_LOWER_T_CLK_PERF0", + "CMT_TOP_LH2_7", + "CMT_TOP_NE4C2_1", + "CMT_TOP_SW4A2_7", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_WR1END1_5", + "CMT_TOP_IMUX36_1", + "CMT_TOP_SW4END2_0", + "CMT_TOP_LH8_0", + "CMT_TOP_EE4A0_7", + "CMT_TOP_EE4C0_3", + "CMT_TOP_EE4A0_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_EE4B1_5", + "CMT_PHASER_IN_DB_STG1REGL6", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_IMUX8_6", + "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "CMT_TOP_BYP0_7", + "CMT_TOP_LH5_0", + "CMT_TOP_IMUX5_2", + "CMT_TOP_WL1END2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_IMUX19_1", + "CMT_TOP_IMUX9_3", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_BYP1_7", + "CMT_PHASER_OUT_CA_TESTIN7", + "CMT_PHASER_BOT_REFMUX_1", + "CMT_TOP_IMUX47_1", + "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "CMT_TOP_IMUX17_3", + "CMT_PHASER_BOT_ENCALIB1", + "CMT_PHASER_BOT_IRANKB0", + "CMT_TOP_WW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2BEG3_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CMT_PHASER_IN_DB_BURSTPENDING", + "CMT_TOP_NE4C3_4", + "CMT_TOP_EE4B2_7", + "CMT_TOP_OCLK_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_NE2A1_6", + "CMT_TOP_IMUX36_0", + "CMT_TOP_WW2A2_7", + "CMT_TOP_IMUX33_8", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "CMT_TOP_IMUX45_4", + "CMT_TOP_IMUX8_2", + "CMT_TOP_IMUX1_2", + "CMT_TOP_SW4END2_8", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX46_0", + "CMT_TOP_WW4C2_7", + "CMT_PHASER_IN_DB_SCANOUT", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_LH1_7", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_BYP5_3", + "CMT_PHASER_IN_CA_TESTIN13", + "CMT_TOP_NW2A2_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX40_4", + "CMT_LR_LOWER_T_CLK_MMCM13", + "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_WW4END0_5", + "CMT_TOP_BYP7_0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_BYP3_2", + "CMT_PHASER_IN_CA_FINEOVERFLOW", + "CMT_TOP_NW4END2_1", + "CMT_PHASER_IN_CA_STG1REGR0", + "CMT_TOP_WW4C1_7", + "CMT_TOP_IMUX45_3", + "CMT_TOP_IMUX15_0", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4A3_6", + "CMT_TOP_NE4BEG3_8", + "CMT_PHASER_OUT_CA_TESTIN10", + "CMT_TOP_SE4C0_6", + "CMT_TOP_MONITOR_P_1", + "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH10_4", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_IMUX32_3", + "CMT_PHASER_OUT_A_OCLKDIV", + "CMT_TOP_WR1END2_5", + "CMT_TOP_SE4C2_7", + "CMT_TOP_EE4A0_4", + "CMT_TOP_SW4A0_3", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX11_6", + "CMT_TOP_IMUX25_7", + "CMT_PHASERA_DTSBUS0", + "CMT_TOP_IMUX4_8", + "CMT_TOP_BYP5_1", + "CMT_PHASER_OUT_B_RDEN_TOFIFO", + "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "CMT_TOP_WW2A1_7", + "CMT_PHASER_IN_DB_COUNTERLOADEN", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_IMUX17_5", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_BYP2_2", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_IMUX16_8", + "CMT_TOP_LH1_6", + "CMT_TOP_NW4END0_5", + "CMT_TOP_SE2A3_6", + "CMT_TOP_IMUX7_4", + "MMCM_CLK_FREQBB_REBUFOUT3", + "CMT_TOP_IMUX12_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX30_3", + "CMT_TOP_BYP5_6", + "CMT_TOP_WW4C2_5", + "CMT_TOP_LH7_6", + "CMT_TOP_SE2A1_5", + "CMT_TOP_FAN4_7", + "CMT_TOP_SE2A3_3", + "CMT_PHASER_BOT_IBURSTPENDING1", + "CMT_TOP_EE4A2_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_LR_LOWER_T_CLK_MMCM6", + "CMT_TOP_LH9_2", + "CMT_TOP_EE4C0_1", + "CMT_TOP_BYP0_1", + "CMT_TOP_NE4C2_0", + "CMT_TOP_LH11_0", + "CMT_PHASER_OUT_DB_TESTIN7", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX14_0", + "CMT_TOP_NW2A1_5", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX21_5", + "CMT_TOP_IMUX21_7", + "CMT_TOP_WW4A0_2", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH12_3", + "CMT_TOP_IMUX7_6", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX23_7", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4C1_2", + "CMT_TOP_LH4_3", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH5_6", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW4C1_4", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LH12_8", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_FAN4_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NW4A3_5", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_CTRL0_8", + "CMT_PHASER_OUT_CA_TESTIN4", + "CMT_TOP_NW4A3_7", + "CMT_PHASER_OUT_CA_SYSCLK", + "CMT_TOP_NW4END3_0", + "CMT_TOP_IMUX33_2", + "CMT_TOP_BYP2_1", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_NE2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_SE2A3_8", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_IMUX20_8", + "CMT_TOP_WW2END0_8", + "CMT_TOP_WW2END1_2", + "CMT_TOP_LH9_3", + "CMT_PHASER_OUT_CA_TESTIN12", + "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "CMT_TOP_ER1BEG3_3", + "CMT_PHASER_OUT_DB_COARSEINC", + "CMT_TOP_LH6_4", + "CMT_TOP_EE4B2_2", + "CMT_PHASER_OUT_DB_TESTIN0", + "CMT_TOP_SE4BEG0_2", + "CMT_PHASER_OUT_CA_OSERDESRST", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_NW2A2_7", + "CMT_TOP_IMUX5_8", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_PHASER_IN_CA_STG1REGR3", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_IMUX33_5", + "CMT_PHASER_OUT_CA_COARSEINC", + "CMT_PHASER_IN_CA_ENCALIB1", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE2A0_7", + "CMT_TOP_NE4C3_0", + "CMT_PHASER_IN_CA_COUNTERLOADEN", + "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "CMT_TOP_BYP6_5", + "CMT_TOP_SW4END3_0", + "CMT_TOP_WL1END0_6", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_WR1END1_2", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_NW4A1_5", + "CMT_PHASER_OUT_DB_RDENABLE", + "CMT_PHASER_IN_CA_SYSCLK", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_PHASER_OUT_DB_COUNTERREADEN", + "CMT_TOP_IMUX47_8", + "CMT_TOP_IMUX15_6", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_IMUX41_2", + "CMT_TOP_SE4C1_5", + "CMT_TOP_ICLK_2", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_WL1END2_7", + "CMT_TOP_IMUX36_2", + "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "CMT_TOP_FAN1_3", + "CMT_TOP_WW4A0_1", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_LH9_0", + "CMT_TOP_CTRL0_4", + "CMT_TOP_NW4END2_3", + "CMT_TOP_SE2A2_8", + "CMT_TOP_WL1END0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_WR1END3_6", + "CMT_PHASER_IN_CA_STG1LOAD", + "CMT_PHASER_OUT_DB_SCANOUT", + "CMT_TOP_WW4C2_3", + "CMT_TOP_WW2A3_3", + "CMT_TOP_WL1END3_4", + "CMT_TOP_NE2A2_8", + "CMT_TOP_NE2A3_3", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_SW2A0_8", + "CMT_TOP_WW4B3_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_IMUX29_8", + "CMT_PHASER_IN_CA_TESTIN10", + "CMT_PHASER_IN_DB_STG1REGR8", + "CMT_TOP_IMUX26_6", + "CMT_TOP_SE4C0_7", + "CMT_PHASER_OUT_DB_TESTIN2", + "CMT_TOP_IMUX4_0", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_NE4BEG0_7", + "CMT_PHASER_OUT_DB_OCLKDIV", + "CMT_TOP_IMUX40_2", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_EE2BEG3_8", + "CMT_PHASERA_DTSBUS1", + "CMT_PHASER_OUT_DB_DQSBUS0", + "CMT_TOP_IMUX29_0", + "CMT_TOP_WR1END2_0", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX1_6", + "CMT_PHASER_OUT_CA_RDENABLE", + "CMT_PHASER_IN_DB_ICLK", + "CMT_TOP_SW2A3_6", + "CMT_TOP_IMUX14_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_IMUX7_7", + "CMT_TOP_BYP3_3", + "CMT_TOP_IMUX29_5", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX44_0", + "CMT_TOP_WW4A2_4", + "CMT_TOP_WW4C1_1", + "CMT_TOP_WW4B1_7", + "CMT_TOP_EE2A1_6", + "CMT_PHASER_IN_DB_MEMREFCLK", + "CMT_TOP_EE4A1_7", + "CMT_TOP_IMUX19_2", + "CMT_PHASER_OUT_DB_EDGEADV", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW2A1_3", + "CMT_PHASER_OUT_DB_TESTOUT3", + "CMT_TOP_IMUX39_5", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_FAN3_4", + "CMT_TOP_FAN3_2", + "CMT_TOP_LH1_0", + "CMT_TOP_IMUX28_5", + "CMT_TOP_IMUX6_7", + "CMT_TOP_NE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SW2A0_2", + "CMT_TOP_BYP7_8", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX47_7", + "CMT_TOP_WW4A1_8", + "CMT_TOP_BYP0_4", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_IMUX21_6", + "CMT_TOP_IMUX5_4", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX15_5", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_NW2A0_5", + "CMT_TOP_SW4A0_7", + "CMT_PHASER_IN_CA_STG1REGL2", + "CMT_TOP_NE4C1_2", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "CMT_TOP_LH12_4", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_WW2END0_1", + "CMT_TOP_WW4A1_7", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX5_3", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_PHASER_IN_DB_TESTIN13", + "CMT_PHASER_OUT_DB_CTSBUS0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_LH7_7", + "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_WW4C0_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "CMT_PHASER_IN_DB_WRENABLE", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX0_0", + "CMT_TOP_BYP5_4", + "CMT_TOP_FAN4_3", + "CMT_PHASER_OUT_CA_TESTIN15", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SW2A2_4", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_FAN6_2", + "CMT_TOP_WW4C2_0", + "CMT_TOP_IMUX20_6", + "CMT_TOP_ICLK_8", + "CMT_PHASER_OUT_A_OCLK1X_90", + "CMT_TOP_LH4_5", + "CMT_TOP_IMUX22_4", + "CMT_PHASER_B_OCLK_TOIOI", + "CMT_TOP_WR1END2_4", + "CMT_TOP_NW2A1_7", + "CMT_TOP_LH9_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_EE4C3_0", + "CMT_TOP_NE4C1_6", + "CMT_TOP_CTRL0_6", + "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "CMT_TOP_BYP2_0", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_WW4A0_6", + "CMT_TOP_IMUX6_8", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WW4END0_0", + "CMT_TOP_WR1END0_1", + "CMT_TOP_EE2A2_7", + "CMT_TOP_LH2_1", + "CMT_TOP_CLK0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_WW4END3_7", + "CMT_PHASER_OUT_CA_COARSEENABLE", + "CMT_PHASER_IN_CA_STG1REGR6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_SE4BEG0_1", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CMT_TOP_LH11_5", + "CMT_TOP_SW2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_WW4C1_5", + "CMT_TOP_BYP5_8", + "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "CMT_TOP_IMUX27_1", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_8", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_IMUX30_6", + "CMT_TOP_WL1END1_7", + "CMT_TOP_IMUX39_2", + "CMT_TOP_EE4C0_6", + "CMT_PHASER_OUT_DB_DTSBUS0", + "CMT_PHASER_IN_CA_COUNTERREADEN", + "CMT_TOP_IMUX10_8", + "CMT_PHASER_B_OCLKDIV_TOIOI", + "CMT_TOP_WW4C2_1", + "CMT_TOP_WW4END3_0", + "CMT_TOP_NW4A3_6", + "CMT_TOP_EE4C2_8", + "CMT_TOP_LH6_7", + "CMT_TOP_IMUX16_3", + "CMT_PHASER_IN_DB_TESTIN4", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_LH2_2", + "CMT_TOP_OCLK_8", + "CMT_TOP_NE2A0_6", + "CMT_TOP_WW2A3_2", + "CMT_TOP_WW4B1_8", + "CMT_TOP_CTRL1_6", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_WW4A3_0", + "CMT_TOP_FAN3_7", + "CMT_TOP_ER1BEG1_1", + "CMT_PHASER_IN_B_ICLK", + "CMT_TOP_EE4A0_8", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_IMUX25_5", + "CMT_TOP_IMUX8_5", + "CMT_TOP_IMUX9_1", + "CMT_TOP_CLK0_4", + "CMT_TOP_EE4A3_8", + "CMT_TOP_IMUX37_5", + "CMT_TOP_FAN5_3", + "CMT_TOP_EE4A1_4", + "CMT_TOP_IMUX31_6", + "CMT_TOP_IMUX38_7", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX28_6", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_CLK0_1", + "CMT_TOP_ICLK_7", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX15_3", + "CMT_TOP_IMUX23_1", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_WW2END1_6", + "CMT_PHASER_OUT_DB_TESTIN10", + "CMT_TOP_SW2A0_1", + "CMT_TOP_CTRL1_3", + "CMT_TOP_FAN2_3", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX10_7", + "CMT_TOP_NE4C2_8", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_NW2A1_6", + "CMT_TOP_SW4A0_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_IMUX8_3", + "CMT_PHASERA_CTSBUS0", + "CMT_TOP_NW2A3_4", + "CMT_TOP_IMUX27_8", + "CMT_PHASER_IN_CA_STG1REGR7", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_LH6_3", + "CMT_TOP_NE4C3_1", + "CMT_TOP_CTRL0_3", + "CMT_TOP_EE4C2_7", + "CMT_PHASER_IN_DB_ENSTG1", + "CMT_TOP_NE2A1_1", + "CMT_TOP_FAN0_8", + "CMT_PHASER_OUT_DB_TESTIN15", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_EE4BEG1_4", + "CMT_PHASER_IN_DB_TESTIN9", + "CMT_TOP_SW4A1_1", + "CMT_TOP_EL1BEG1_4", + "CMT_PHASER_IN_CA_SCANCLK", + "CMT_TOP_WW2END1_1", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_IMUX9_6", + "CMT_TOP_EE2A0_4", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX31_8", + "CMT_TOP_FAN1_7", + "CMT_TOP_WW4A3_3", + "CMT_TOP_ER1BEG0_4", + "CMT_PHASER_IN_CA_ENCALIBPHY0", + "CMT_TOP_IMUX28_7", + "CMT_TOP_NW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_SW4END2_1", + "CMT_TOP_EE4A3_3", + "CMT_PHASER_IN_DB_STG1REGL4", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A1_0", + "CMT_TOP_SW2A3_7", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_LH3_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_IMUX32_6", + "CMT_TOP_IMUX41_0", + "MMCM_CLK_FREQBB_REBUFOUT0", + "CMT_TOP_WR1END3_4", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_EE4B3_4", + "CMT_TOP_SE4BEG1_1", + "CMT_PHASER_OUT_CA_OCLKDELAYED", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX24_4", + "CMT_TOP_IMUX11_7", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_FAN6_6", + "CMT_TOP_SW2A2_5", + "CMT_TOP_FAN5_0", + "CMT_TOP_IMUX25_2", + "CMT_TOP_BYP2_3", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_FAN4_5", + "CMT_PHASER_IN_DB_TESTOUT2", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_WW2END2_7", + "CMT_TOP_NW4A1_3", + "CMT_TOP_SW4END1_8", + "CMT_TOP_IMUX35_4", + "CMT_TOP_IMUX41_5", + "CMT_TOP_IMUX17_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_NW4A1_8", + "CMT_TOP_IMUX10_6", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_LH12_6", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4A0_0", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_WW2A1_8", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NW2A2_0", + "CMT_TOP_NE4BEG1_6", + "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "CMT_PHASER_IN_DB_STG1REGL5", + "CMT_TOP_BYP7_1", + "CMT_TOP_IMUX11_2", + "CMT_TOP_WW2A0_0", + "CMT_TOP_SW4A2_1", + "CMT_TOP_LH1_3", + "CMT_PHASER_IN_A_RCLK0", + "CMT_TOP_FAN0_5", + "CMT_TOP_BYP2_7", + "CMT_TOP_EE2A1_8", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_LH2_3", + "CMT_TOP_FAN7_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_WW4END2_3", + "CMT_TOP_NE4C1_7", + "CMT_TOP_BYP0_0", + "CMT_PHASER_IN_CA_STG1REGL4", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_WW4END0_7", + "CMT_PHASER_IN_CA_TESTIN4", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_PHASER_OUT_CA_PHASEREFCLK", + "CMT_TOP_NW4A3_0", + "CMT_TOP_NE2A2_6", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "CMT_TOP_IMUX37_2", + "CMT_TOP_WR1END1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CMT_PHASER_IN_CA_ENCALIB0", + "CMT_TOP_WW4END2_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX7_2", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN2_1", + "CMT_TOP_NE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_IMUX27_2", + "CMT_TOP_WW4A0_7", + "CMT_TOP_WW4C0_6", + "CMT_PHASER_OUT_DB_TESTOUT1", + "CMT_TOP_EE4C0_8", + "CMT_PHASER_OUT_B_OCLK1X_90", + "CMT_PHASER_OUT_CA_DQSBUS1", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX1_8", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_BYP6_3", + "CMT_TOP_NE2A2_5", + "CMT_TOP_NW4A0_3", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_WR1END3_8", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_IMUX37_1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "CMT_TOP_NW2A1_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_NW2A3_6", + "CMT_TOP_WW4END3_5", + "CMT_TOP_WW4B1_5", + "CMT_TOP_WW4A1_4", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_NW2A2_3", + "CMT_TOP_WW2A2_6", + "CMT_TOP_EE4C0_7", + "CMT_TOP_IMUX17_0", + "CMT_TOP_CLK0_2", + "CMT_TOP_EE4B3_2", + "CMT_PHASER_OUT_CA_COUNTERREADEN", + "CMT_TOP_SW4END0_0", + "CMT_TOP_IMUX31_5", + "CMT_TOP_FAN0_0", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_IMUX37_6", + "CMT_TOP_EE4C3_2", + "CMT_TOP_BYP5_5", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SE4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_IMUX46_5", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_IMUX43_7", + "CMT_TOP_IMUX46_3", + "CMT_TOP_IMUX40_1", + "CMT_TOP_EL1BEG0_1", + "CMT_PHASER_IN_CA_FREQREFCLK", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_NE4BEG0_2", + "CMT_PHASER_OUT_CA_TESTIN8", + "CMT_TOP_WW4END3_6", + "CMT_TOP_LH8_8", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "CMT_TOP_FAN2_5", + "CMT_TOP_CLK0_6", + "CMT_TOP_WW4B1_1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "CMT_TOP_IMUX10_5", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_PHASER_OUT_DB_COARSEENABLE", + "CMT_PHASER_DOWN_PHASERREF0", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_IMUX2_3", + "CMT_TOP_WW2A3_8", + "CMT_TOP_NE4C1_8", + "CMT_TOP_EE2A3_3", + "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "CMT_TOP_IMUX36_4", + "CMT_TOP_EE4A1_1", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_IMUX43_5", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4C0_4", + "CMT_TOP_SW2A0_3", + "CMT_PHASER_OUT_CA_TESTIN6", + "CMT_TOP_IMUX12_4", + "CMT_TOP_BYP0_6", + "CMT_TOP_LH10_3", + "CMT_TOP_SW2A3_8", + "CMT_TOP_LH3_2", + "CMT_TOP_WW2A2_5", + "CMT_TOP_EL1BEG3_7", + "CMT_PHASER_IN_CA_STG1INCDEC", + "CMT_TOP_SW4A0_6", + "CMT_TOP_IMUX38_6", + "CMT_TOP_WR1END0_5", + "CMT_PHASER_OUT_CA_TESTOUT2", + "CMT_TOP_IMUX4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_IMUX43_4", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_IMUX19_8", + "CMT_TOP_LH10_6", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_PHASER_BOT_IRANKB1", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_IMUX36_5", + "CMT_PHASER_IN_DB_RANKSEL0", + "CMT_TOP_WW2A0_3", + "CMT_TOP_LH10_5", + "CMT_PHASER_IN_DB_STG1INCDEC", + "CMT_TOP_WW4B0_3", + "CMT_TOP_NE4C3_3", + "CMT_TOP_FAN7_2", + "CMT_PHASER_IN_CA_STG1REGL6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_BYP6_1", + "CMT_TOP_WL1END2_1", + "CMT_TOP_SW4A0_2", + "CMT_TOP_IMUX10_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_NW2A3_5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_LH5_2", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_SW2A2_6", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_WW4A2_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_PHASER_BOT_ENCALIB0", + "CMT_TOP_NW4END3_6", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_NW4END3_8", + "CMT_TOP_WL1END0_7", + "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "CMT_PHASER_OUT_DB_FINEENABLE", + "CMT_PHASER_IN_CA_STG1REGR2", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX9_7", + "CMT_TOP_BYP5_7", + "CMT_TOP_LH3_1", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END2_5", + "CMT_TOP_FAN0_6", + "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "CMT_TOP_SW2A1_6", + "CMT_TOP_EE2BEG2_8", + "CMT_PHASER_IN_CA_STG1READ", + "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX37_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_IMUX4_5", + "CMT_TOP_EE4B2_8", + "CMT_TOP_IMUX42_5", + "CMT_TOP_BYP4_0", + "CMT_PHASER_IN_DB_FREQREFCLK", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4C1_5", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LH4_4", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_PHASER_IN_DB_TESTOUT1", + "CMT_TOP_IMUX24_5", + "CMT_PHASER_OUT_DB_SCANCLK", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_EL1BEG1_1", + "CMT_PHASER_OUT_CA_TESTOUT0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_6", + "CMT_TOP_WW4C1_2", + "CMT_TOP_FAN3_3", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_WR1END1_0", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_IMUX22_5", + "CMT_TOP_EE2A1_3", + "CMT_PHASER_OUT_DB_TESTIN1", + "CMT_TOP_SE2A2_2", + "CMT_TOP_OCLK_3", + "CMT_TOP_IMUX23_5", + "CMT_PHASER_OUT_CA_TESTIN11", + "CMT_PHASER_OUT_DB_TESTIN9", + "CMT_TOP_SW4END2_4", + "CMT_TOP_EE4A1_8", + "CMT_PHASER_OUT_CA_DTSBUS0", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW2END0_2", + "CMT_TOP_SE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_EE2A1_7", + "CMT_TOP_SE2A1_6", + "CMT_TOP_IMUX45_6", + "CMT_TOP_SW4END0_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX3_8", + "CMT_PHASER_OUT_DB_ENCALIB1", + "CMT_TOP_CTRL0_1", + "MMCM_CLK_FREQBB_REBUFOUT2", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_LH6_8", + "CMT_TOP_WW4B0_0", + "CMT_TOP_BYP1_5", + "CMT_BOT_HCLKMUX_CLKINT_0", + "CMT_TOP_SW4A1_4", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX6_5", + "CMT_TOP_IMUX46_6", + "CMT_PHASER_IN_DB_TESTIN2", + "CMT_TOP_WW4B0_4", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "CMT_TOP_LH10_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_IMUX45_0", + "CMT_TOP_WW4END3_3", + "CMT_TOP_WW4B3_2", + "CMT_PHASER_OUT_DB_DTSBUS1", + "CMT_PHASER_IN_CA_RCLK", + "CMT_TOP_IMUX39_1", + "CMT_TOP_FAN3_0", + "CMT_TOP_WL1END1_8", + "CMT_TOP_EE2A3_6", + "CMT_TOP_IMUX9_5", + "CMT_TOP_WW2END3_8", + "CMT_TOP_IMUX32_4", + "CMT_PHASERREF_DOWN_PHASEROUT_B", + "CMT_TOP_IMUX26_8", + "CMT_TOP_IMUX23_4", + "CMT_TOP_EE4A0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_EE4B0_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_WL1END0_2", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_SE2A0_2", + "CMT_TOP_EE2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_IMUX44_4", + "CMT_TOP_IMUX25_3", + "CMT_TOP_EE4C1_5", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_IMUX29_4", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_PHASER_IN_CA_ICLKDIV", + "CMT_PHASER_IN_CA_RANKSELPHY1", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX32_0", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW4END2_3", + "CMT_TOP_BYP4_2", + "CMT_PHASER_IN_DB_RANKSELPHY0", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WL1END3_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_FAN5_4", + "CMT_TOP_EE2A2_2", + "CMT_TOP_EE4A2_1", + "CMT_TOP_IMUX34_4", + "CMT_TOP_LH7_2", + "CMT_TOP_LH6_1", + "CMT_TOP_NW4END2_2", + "CMT_TOP_WW4END0_8", + "CMT_TOP_LH11_8", + "CMT_TOP_IMUX45_5", + "CMT_TOP_IMUX18_2", + "CMT_PHASER_IN_DB_STG1REGL2", + "CMT_TOP_LH1_2", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_WR1END0_6", + "CMT_TOP_IMUX3_1", + "CMT_PHASER_IN_A_WRCLK_TOFIFO", + "CMT_PHASER_IN_CA_TESTIN1", + "CMT_TOP_WW4END3_1", + "CMT_TOP_IMUX13_2", + "CMT_TOP_WW4A0_8", + "CMT_TOP_FAN6_8", + "CMT_PHASER_OUT_A_RDEN_TOFIFO", + "CMT_TOP_IMUX17_7", + "CMT_TOP_IMUX16_2", + "CMT_TOP_FAN4_4", + "CMT_PHASERA_DQSBUS1", + "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "CMT_TOP_FAN7_3", + "CMT_TOP_NW4A0_2", + "CMT_TOP_BYP6_6", + "CMT_PHASER_IN_CA_WRENABLE", + "CMT_TOP_LH4_0", + "CMT_PHASER_IN_CA_ICLK", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_IMUX22_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_SW4END1_7", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NW4END0_6", + "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "CMT_TOP_WR1END3_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_EE4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_PHASER_OUT_B_OCLK", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "CMT_TOP_NE2A3_7", + "CMT_TOP_FAN7_0", + "CMT_TOP_IMUX3_7", + "CMT_TOP_EE2BEG2_6", + "CMT_PHASER_OUT_DB_TESTIN5", + "CMT_TOP_SW4A1_2", + "CMT_TOP_BYP2_6", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_IMUX4_1", + "CMT_TOP_IMUX14_8", + "CMT_PHASER_IN_CA_RST", + "CMT_PHASER_IN_DB_TESTIN5", + "CMT_TOP_IMUX26_2", + "CMT_TOP_NE4C0_0", + "CMT_TOP_BYP0_3", + "CMT_PHASER_B_ICLKDIV_TOIOI", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_FAN1_8", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_IMUX11_8", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX5_6", + "CMT_TOP_IMUX38_0", + "CMT_PHASER_IN_DB_ENCALIB0", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_WW4END2_4", + "CMT_TOP_CLK1_7", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_PHASER_OUT_CA_TESTIN0", + "CMT_TOP_WW4B3_1", + "CMT_PHASER_BOT_OBURSTPENDING0", + "CMT_PHASER_OUT_DB_DQSBUS1", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NW2A2_8", + "CMT_TOP_IMUX16_5", + "CMT_TOP_IMUX19_4", + "CMT_TOP_CLK1_4", + "CMT_TOP_LH8_3", + "CMT_TOP_SW2A1_3", + "CMT_PHASER_OUT_DB_TESTIN3", + "CMT_TOP_IMUX30_4", + "CMT_TOP_WW2END2_0", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_PHASER_IN_DB_DQSFOUND", + "CMT_TOP_IMUX45_2", + "CMT_PHASER_IN_DB_FINEOVERFLOW", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX28_1", + "CMT_TOP_NW4A0_0", + "CMT_TOP_EE4BEG3_4", + "CMT_PHASER_BOT_IRANKA1", + "CMT_TOP_EE4B1_2", + "CMT_TOP_LH3_7", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_WW4C0_0", + "CMT_TOP_SW2A1_7", + "CMT_TOP_BYP2_4", + "CMT_TOP_IMUX16_4", + "CMT_PHASER_IN_DB_TESTIN11", + "CMT_TOP_EE2A3_7", + "CMT_PHASER_IN_CA_FINEINC", + "CMT_TOP_EE4B3_1", + "CMT_TOP_SE4C3_3", + "CMT_TOP_WW2END0_0", + "CMT_TOP_BYP3_6", + "CMT_TOP_SW4END1_4", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_IMUX34_7", + "CMT_TOP_WW2A0_7", + "CMT_TOP_WW2A2_8", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_IMUX27_4", + "CMT_TOP_WW4B3_7", + "CMT_TOP_WL1END2_5", + "CMT_TOP_OCLK_1", + "CMT_TOP_NW4END0_2", + "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_4", + "CMT_PHASER_OUT_DB_TESTOUT2", + "CMT_TOP_FAN4_2", + "CMT_TOP_EE4C1_7", + "CMT_TOP_WW4C3_8", + "CMT_TOP_EE4B0_7", + "CMT_TOP_NW4END1_1", + "CMT_TOP_BYP0_8", + "CMT_LR_LOWER_T_CLK_PERF2", + "CMT_PHASER_IN_DB_FINEENABLE", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_WW4END1_7", + "CMT_TOP_FAN3_1", + "CMT_TOP_WW4C2_6", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_LR_LOWER_T_CLK_MMCM4", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX5_0", + "CMT_PHASER_OUT_DB_SYSCLK", + "CMT_PHASER_IN_CA_STG1REGL5", + "CMT_TOP_WR1END2_6", + "CMT_TOP_SE2A2_5", + "CMT_PHASER_OUT_CA_TESTIN5", + "CMT_TOP_SE4BEG1_4", + "CMT_PHASER_IN_DB_ENCALIB1", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_FAN2_7", + "CMT_TOP_WW4B0_7", + "CMT_TOP_BYP3_7", + "CMT_TOP_EE2BEG1_5", + "CMT_LR_LOWER_T_CLK_MMCM11", + "CMT_TOP_SW4A3_1", + "CMT_TOP_LH10_8", + "CMT_TOP_LH6_5", + "CMT_TOP_IMUX42_6", + "CMT_PHASER_IN_CA_SYNCIN", + "CMT_TOP_EE4B1_1", + "CMT_TOP_IMUX28_2", + "CMT_TOP_SE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_WW4A3_5", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "CMT_TOP_NW4A0_4", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WL1END0_3", + "CMT_PHASER_BOT_SYNC_BB", + "CMT_TOP_WW4C0_2", + "CMT_TOP_IMUX0_7", + "CMT_PHASER_OUT_DB_SCANENB", + "CMT_TOP_WW4B1_0", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SW4END0_8", + "CMT_TOP_NW4END2_8", + "CMT_TOP_IMUX8_1", + "CMT_TOP_EE4BEG3_6", + "CMT_PHASER_IN_CA_TESTIN8", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW2A1_1", + "CMT_PHASER_IN_DB_COUNTERREADEN", + "CMT_TOP_EE4B2_4", + "CMT_TOP_NE2A3_1", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX18_0", + "CMT_TOP_EE4B0_3", + "CMT_TOP_SE2A2_7", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_BYP6_4", + "CMT_TOP_NW4END1_6", + "CMT_PHASER_OUT_DB_TESTIN13", + "CMT_TOP_BYP2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_LH7_4", + "CMT_TOP_IMUX23_0", + "CMT_TOP_IMUX4_4", + "CMT_TOP_ER1BEG2_5", + "CMT_PHASER_IN_DB_RCLK", + "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "CMT_TOP_IMUX43_8", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX21_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX21_2", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C0_5", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_BYP4_4", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WR1END2_1", + "CMT_PHASER_IN_CA_PHASELOCKED", + "CMT_TOP_EE2BEG0_7", + "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "CMT_PHASER_IN_DB_STG1READ", + "CMT_TOP_IMUX16_1", + "CMT_TOP_NW4A2_3", + "CMT_TOP_FAN2_6", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_6", + "CMT_PHASER_IN_DB_EDGEADV", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WW4C0_1", + "CMT_TOP_WW2A3_0", + "CMT_TOP_FAN7_1", + "CMT_TOP_IMUX28_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_NW2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_PHASER_IN_CA_EDGEADV", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_FAN5_7", + "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "CMT_PHASER_OUT_CA_SCANCLK", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CMT_TOP_IMUX15_7", + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "CMT_TOP_IMUX4_3", + "CMT_TOP_LH8_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "CMT_TOP_EE4BEG3_3", + "CMT_PHASER_IN_CA_STG1REGR5", + "CMT_PHASER_OUT_A_OCLK", + "CMT_PHASER_IN_DB_STG1OVERFLOW", + "CMT_TOP_EE4A3_5", + "CMT_PHASER_B_ICLK_TOIOI", + "CMT_PHASERREF_DOWN_PHASEROUT_A", + "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_NE4C0_5", + "CMT_TOP_SE2A3_2", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_IMUX25_0", + "CMT_TOP_IMUX16_6", + "CMT_TOP_IMUX1_5", + "CMT_PHASER_IN_DB_RST", + "CMT_PHASER_IN_DB_STG1REGL0", + "CMT_TOP_SE4C1_4", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_IMUX34_2", + "CMT_TOP_LH10_2", + "CMT_PHASER_OUT_DB_OCLK", + "CMT_TOP_LH12_0", + "CMT_TOP_FAN4_0", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_NW4A3_1", + "CMT_TOP_NW4A0_8", + "CMT_TOP_EE4B3_5", + "CMT_TOP_BYP3_0", + "CMT_TOP_IMUX26_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_NE4C1_0", + "CMT_TOP_EE2A3_8", + "CMT_PHASER_IN_DB_STG1REGR5", + "CMT_PHASER_IN_CA_SELCALORSTG1", + "CMT_TOP_IMUX22_1", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_PHASER_IN_DB_ENCALIBPHY0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_EE2A3_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_IMUX14_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_IMUX4_7", + "CMT_TOP_SE2A2_0", + "CMT_TOP_EE4A0_2", + "CMT_TOP_LH2_4", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SW4A3_6", + "CMT_TOP_NW4END1_5", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WR1END3_1", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_BYP1_0", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_NE4BEG1_4", + "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "CMT_TOP_WW2A0_6", + "CMT_TOP_IMUX8_7", + "CMT_TOP_WW2END0_4", + "CMT_TOP_SE2A3_0", + "CMT_PHASER_IN_DB_STG1REGL7", + "CMT_TOP_SW4A1_7", + "CMT_TOP_LH10_7", + "CMT_TOP_EE4C2_3", + "CMT_TOP_SW4END2_5", + "CMT_TOP_SE4C3_5", + "CMT_PHASER_IN_CA_TESTIN9", + "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "CMT_TOP_LH4_1", + "CMT_TOP_SW4A1_6", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_SW2A2_0", + "CMT_TOP_BYP6_8", + "CMT_PHASER_DOWN_DQS_TO_PHASER_A", + "CMT_TOP_SW4END0_7", + "CMT_TOP_IMUX13_5", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SE2A1_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EE4A2_4", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_LH2_8", + "CMT_TOP_WR1END0_0", + "CMT_TOP_SE2A3_1", + "CMT_TOP_IMUX2_6", + "CMT_TOP_IMUX3_0", + "CMT_TOP_IMUX18_4", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4C2_4", + "CMT_TOP_WL1END1_5", + "CMT_TOP_NE4BEG1_5", + "CMT_PHASER_IN_CA_DQSFOUND", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_PHASER_IN_CA_STG1OVERFLOW", + "CMT_TOP_NE2A2_3", + "CMT_TOP_EE2BEG3_4", + "CMT_PHASER_IN_CA_FINEENABLE", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_WW4END1_3", + "CMT_PHASER_B_TOMMCM_OCLK", + "CMT_TOP_IMUX24_1", + "CMT_TOP_ER1BEG0_6", + "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "CMT_TOP_WW2END2_6", + "CMT_TOP_EE2A3_2", + "CMT_TOP_EE2A3_0", + "CMT_PHASER_OUT_DB_RST", + "CMT_TOP_IMUX23_8", + "CMT_TOP_WW4A3_8", + "CMT_TOP_IMUX40_6", + "CMT_TOP_WW2A3_7", + "CMT_TOP_WL1END2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_PHASER_OUT_CA_SCANIN", + "CMT_TOP_SW2A0_6", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_NW2A0_1", + "CMT_TOP_FAN1_0", + "CMT_TOP_IMUX6_0", + "CMT_PHASER_IN_CA_TESTOUT1", + "CMT_TOP_IMUX0_2", + "CMT_TOP_NW2A2_6", + "CMT_TOP_CTRL0_0", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_WR1END1_3", + "CMT_TOP_IMUX31_0", + "CMT_TOP_LH5_3", + "CMT_TOP_IMUX43_0", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_NW2A0_3", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4C3_0", + "CMT_TOP_IMUX18_1", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_LH11_1", + "CMT_TOP_SW2A1_8", + "CMT_TOP_EE4C3_4", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN7_4", + "CMT_TOP_NW4END0_4", + "CMT_TOP_ER1BEG3_8", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX15_8", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_WW4B2_5", + "CMT_PHASER_OUT_DB_SCANMODEB", + "CMT_TOP_WR1END1_1", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C1_4", + "CMT_TOP_SW2A2_7", + "CMT_TOP_IMUX20_4", + "CMT_LR_LOWER_T_CLK_MMCM2", + "CMT_TOP_WW2A2_1", + "CMT_PHASER_OUT_CA_SCANOUT", + "CMT_R_TOP_LOWER_B_CLKINT_0", + "CMT_TOP_ICLK_5", + "CMT_PHASER_OUT_DB_DIVIDERST", + "CMT_TOP_SW2A0_7", + "CMT_PHASER_OUT_DB_OSERDESRST", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_FAN6_5", + "CMT_TOP_ER1BEG0_7", + "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "CMT_TOP_NW4A2_0", + "CMT_TOP_WW2A1_2", + "CMT_TOP_FAN4_1", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_WW4A1_6", + "CMT_PHASER_DOWN_PHASERREF1", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_PHASER_OUT_DB_TESTIN12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX0_4", + "CMT_TOP_WW2END0_6", + "CMT_TOP_CTRL1_0", + "CMT_TOP_WR1END0_7", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_IMUX20_3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EE4A2_5", + "CMT_TOP_FAN3_5", + "CMT_PHASER_OUT_CA_DTSBUS1", + "CMT_TOP_WW4B1_2", + "CMT_TOP_NW4END0_0", + "CMT_TOP_FAN6_3", + "CMT_TOP_FAN1_4", + "CMT_TOP_SW4A2_3", + "CMT_TOP_IMUX12_2", + "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_LH11_2", + "CMT_TOP_NW4A3_8", + "CMT_TOP_WW4B0_2", + "CMT_TOP_NE2A0_7", + "CMT_TOP_IMUX34_5", + "CMT_TOP_SE4C2_6", + "CMT_PHASER_IN_DB_TESTIN1", + "CMT_PHASER_IN_CA_TESTIN11", + "CMT_PHASER_OUT_CA_SCANMODEB", + "CMT_TOP_SW4END1_6", + "CMT_TOP_IMUX2_2", + "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "CMT_TOP_EE4C2_5", + "CMT_TOP_WL1END2_2", + "CMT_TOP_IMUX6_3", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW2END0_5", + "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "CMT_TOP_SE4C3_8", + "CMT_TOP_LH6_0", + "CMT_TOP_IMUX20_7", + "CMT_PHASER_IN_CA_RANKSEL0", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX29_3", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_IMUX35_7", + "CMT_PHASER_IN_A_ICLK", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_WL1END1_6", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_NW4A2_5", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX9_2", + "CMT_TOP_IMUX19_5", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_WW4END2_2", + "CMT_TOP_WL1END0_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_IMUX47_6", + "CMT_TOP_NE2A3_4", + "CMT_TOP_IMUX40_3", + "CMT_TOP_IMUX23_2", + "CMT_PHASER_BOT_IBURSTPENDING0", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_IMUX39_6", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_PHASER_IN_A_ICLKDIV", + "CMT_TOP_EL1BEG2_1", + "CMT_BOT_HCLKMUX_CLKINT_1", + "CMT_TOP_IMUX6_4", + "CMT_TOP_ICLK_3", + "CMT_TOP_IMUX12_3", + "CMT_TOP_SW4END0_6", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_LH8_2", + "CMT_TOP_IMUX41_6", + "CMT_PHASER_OUT_CA_OCLKDIV", + "CMT_TOP_BYP2_5", + "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_IMUX38_8", + "CMT_TOP_IMUX0_6", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SW4A2_6", + "CMT_TOP_EE4C0_2", + "CMT_TOP_SE2A0_8", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NE2A0_1", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_IMUX31_4", + "CMT_TOP_IMUX11_3", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_IMUX47_2", + "CMT_TOP_IMUX5_1", + "CMT_TOP_LH12_1", + "CMT_TOP_IMUX26_1", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_LH5_8", + "CMT_TOP_WW2END3_6", + "CMT_TOP_NW2A0_8", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_WW4A2_8", + "CMT_TOP_IMUX44_3", + "CMT_TOP_WW4A3_4", + "CMT_TOP_LH3_4", + "CMT_TOP_EE2A2_1", + "CMT_TOP_WW4A2_3", + "CMT_TOP_LH11_4", + "CMT_TOP_NW2A3_2", + "CMT_TOP_IMUX34_0", + "CMT_TOP_BYP1_6", + "CMT_TOP_WW4B0_1", + "CMT_LR_LOWER_T_CLK_IN2_HCLK", + "CMT_TOP_IMUX2_4", + "CMT_TOP_SW4A1_8", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX39_8", + "CMT_TOP_IMUX29_7", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX33_3", + "CMT_TOP_SW4END2_7", + "CMT_TOP_SW2A2_3", + "CMT_TOP_FAN2_4", + "CMT_TOP_EE4A1_6", + "CMT_TOP_EE4B1_3", + "CMT_TOP_IMUX44_8", + "CMT_PHASER_IN_CA_STG1REGL1", + "CMT_TOP_WW4END0_1", + "CMT_TOP_IMUX9_4", + "CMT_TOP_IMUX32_7", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SE2A0_5", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EE4B1_0", + "CMT_TOP_WW4A2_2", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_IMUX32_1", + "CMT_TOP_LH8_1", + "CMT_TOP_SE2A2_1", + "CMT_PHASER_IN_CA_SCANENB", + "CMT_TOP_IMUX10_3", + "CMT_TOP_WL1END3_2", + "CMT_LR_LOWER_T_CLK_MMCM9", + "CMT_PHASER_IN_CA_ENCALIBPHY1", + "CMT_TOP_WW4C3_3", + "CMT_TOP_SE4C3_1", + "CMT_TOP_NW4A2_8", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX26_3", + "CMT_TOP_IMUX24_6", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_IMUX35_5", + "CMT_TOP_WW4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_NE4C3_2", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "CMT_TOP_NE2A3_8", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_WW4END3_4", + "CMT_TOP_LH1_1", + "CMT_TOP_IMUX17_1", + "CMT_TOP_CTRL1_5", + "CMT_TOP_EE4C3_7", + "CMT_TOP_IMUX15_1", + "CMT_LR_LOWER_T_CLK_PERF1", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_IMUX32_2", + "CMT_PHASER_IN_DB_TESTIN8", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_CLK0_8", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NE2A0_5", + "CMT_TOP_SW4END2_6", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_ICLK_6", + "CMT_PHASER_IN_CA_RSTDQSFIND", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_EE4C3_5", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_SE2A3_7", + "CMT_PHASERREF_DOWN_PHASERIN_A", + "CMT_PHASER_IN_CA_TESTOUT0", + "CMT_TOP_IMUX8_8", + "CMT_LR_LOWER_T_CLK_MMCM0", + "CMT_TOP_EE4B2_3", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_EE2A2_4", + "CMT_TOP_IMUX0_3", + "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "CMT_TOP_IMUX13_1", + "CMT_TOP_NE2A3_5", + "CMT_TOP_SW4END0_5", + "CMT_TOP_SW4A2_2", + "CMT_PHASER_OUT_CA_ENCALIB1", + "CMT_TOP_WW2END0_3", + "CMT_PHASER_IN_DB_RANKSEL1", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_PHASER_IN_DB_TESTIN7", + "CMT_TOP_EE4C1_3", + "CMT_TOP_EE4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_CTRL1_1", + "CMT_TOP_SE4BEG0_8", + "CMT_PHASER_IN_DB_STG1REGL8", + "CMT_PHASER_OUT_CA_OCLK", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_NW2A2_4", + "CMT_PHASERREF_DOWN_PHASERIN_B", + "CMT_TOP_FAN3_6", + "CMT_TOP_FAN2_2", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX37_3", + "CMT_TOP_IMUX37_8", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_IMUX47_3", + "CMT_LR_LOWER_T_CLK_IN3_HCLK", + "CMT_TOP_SW4A3_5", + "CMT_TOP_CTRL1_2", + "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_EE2A1_4", + "CMT_TOP_NW4END1_4", + "CMT_TOP_IMUX25_1", + "CMT_TOP_EE4B0_0", + "CMT_TOP_SE2A0_0", + "CMT_PHASER_OUT_DB_TESTIN11", + "CMT_TOP_IMUX25_8", + "CMT_TOP_EE4A1_3", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_NW4A2_4", + "CMT_TOP_NW2A3_7", + "CMT_TOP_IMUX3_2", + "CMT_LR_LOWER_T_CLK_MMCM8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_SE2A1_7", + "CMT_TOP_EE4BEG3_0", + "CMT_PHASER_OUT_DB_TESTIN8", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_EE2A1_2", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_NW4END2_6", + "CMT_PHASER_IN_CA_SCANMODEB", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WW4C2_8", + "CMT_TOP_IMUX34_1", + "CMT_TOP_IMUX32_5", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_NW4A2_1", + "CMT_TOP_SW4A2_4", + "CMT_PHASER_OUT_CA_MEMREFCLK", + "CMT_TOP_NE2A2_1", + "CMT_TOP_CTRL1_8", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NW4END3_3", + "CMT_TOP_WW4B2_2", + "CMT_TOP_IMUX18_3", + "CMT_PHASER_IN_CA_STG1REGL3", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_LH9_4", + "CMT_TOP_NE4C3_6", + "CMT_TOP_WW4A0_3", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WW2END3_1", + "CMT_TOP_LH5_1", + "CMT_TOP_WL1END0_4", + "CMT_TOP_BYP4_3", + "CMT_TOP_IMUX44_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "CMT_TOP_SW2A3_3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "CMT_TOP_SE2A2_3", + "CMT_PHASER_OUT_CA_TESTIN9", + "CMT_TOP_SE2A0_7", + "CMT_TOP_WW2END2_2", + "CMT_PHASER_IN_DB_STG1REGR2", + "CMT_TOP_SE4C2_4", + "CMT_TOP_BYP7_5", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX0_8", + "CMT_TOP_SW2A1_2", + "CMT_TOP_NE4C1_3", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX18_8", + "CMT_TOP_EE4B1_6", + "CMT_TOP_IMUX20_5", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_BYP3_4", + "CMT_PHASER_B_TOMMCM_ICLKDIV", + "CMT_TOP_SW4A3_7", + "CMT_TOP_CLK1_5", + "CMT_TOP_SW2A0_4", + "CMT_TOP_BYP5_0", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_SW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_IMUX13_7", + "CMT_PHASER_IN_DB_STG1LOAD", + "CMT_TOP_NE4C2_2", + "CMT_TOP_IMUX10_4", + "CMT_TOP_LH1_4", + "CMT_PHASER_OUT_DB_TESTIN6", + "CMT_TOP_NW4A0_6", + "CMT_PHASER_IN_DB_ISERDESRST", + "CMT_TOP_EE2A0_6", + "CMT_TOP_WW4END3_8", + "CMT_TOP_NW4END1_0", + "CMT_TOP_IMUX46_7", + "CMT_PHASER_IN_DB_SYSCLK", + "CMT_TOP_EE4C2_2", + "CMT_PHASER_IN_DB_STG1REGR7", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_WW2END3_4", + "CMT_PHASER_IN_DB_FINEINC", + "CMT_TOP_WW4C1_8", + "CMT_PHASER_IN_DB_SYNCIN", + "CMT_TOP_WR1END1_8", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE2A2_8", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4B3_6", + "CMT_TOP_EE4C3_1", + "CMT_PHASER_IN_DB_SCANCLK", + "CMT_TOP_EE4B3_7", + "CMT_TOP_NW4END0_7", + "CMT_PHASER_IN_CA_SCANOUT", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX22_7", + "CMT_TOP_IMUX13_6", + "CMT_TOP_NW2A2_5", + "CMT_TOP_EE4A2_6", + "CMT_TOP_LH7_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_IMUX20_1", + "CMT_TOP_WW4B1_3", + "CMT_TOP_FAN5_8", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_OCLK_4", + "CMT_PHASER_IN_DB_STG1REGL1", + "CMT_TOP_SE4C2_0", + "CMT_TOP_WR1END2_2", + "CMT_TOP_WW2A0_1", + "CMT_TOP_NE2A0_8", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_IMUX11_5", + "CMT_TOP_WW2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_WW4B0_8", + "CMT_PHASER_IN_DB_PHASELOCKED", + "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_WW4A1_5", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LH5_7", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX35_1", + "CMT_PHASER_IN_DB_STG1REGR0", + "CMT_TOP_IMUX43_2", + "CMT_TOP_LH12_5", + "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "CMT_PHASER_OUT_CA_SYNCIN", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_IMUX46_1", + "CMT_TOP_EE4C2_6", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_WL1END1_3", + "CMT_TOP_WW4C3_1", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_NW2A3_8", + "CMT_TOP_ICLK_1", + "CMT_TOP_SE2A3_4", + "CMT_TOP_NE4C2_6", + "CMT_TOP_IMUX26_5", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_IMUX25_6", + "CMT_TOP_BYP0_2", + "CMT_TOP_BYP6_7", + "CMT_TOP_IMUX42_1", + "CMT_PHASER_IN_CA_TESTIN12", + "CMT_TOP_BYP7_6", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_NE2A1_8", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_NW4A3_2", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_5", + "CMT_TOP_IMUX4_6", + "CMT_TOP_WW4B2_0", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_WW4END0_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX3_6", + "CMT_TOP_WW2A3_1", + "CMT_PHASER_IN_CA_BURSTPENDING", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_PHASER_IN_DB_SCANMODEB", + "CMT_TOP_WL1END3_0", + "CMT_TOP_WW4END0_3", + "CMT_TOP_IMUX35_3", + "CMT_TOP_NW4END0_1", + "CMT_LR_LOWER_T_CLK_MMCM3", + "CMT_TOP_LH6_6", + "CMT_TOP_LH12_2", + "CMT_TOP_NE4C3_5", + "CMT_TOP_NW4END0_8", + "CMT_PHASER_BOT_REFMUX_2", + "CMT_TOP_IMUX39_0", + "CMT_TOP_WW4END2_0", + "MMCM_CLK_FREQBB_REBUFOUT1", + "CMT_PHASER_IN_CA_STG1REGL0", + "CMT_TOP_WW4END2_6", + "CMT_TOP_WW4B3_4", + "CMT_TOP_LH11_7", + "CMT_PHASER_B_TOMMCM_OCLK1X_90", + "CMT_TOP_SW4END3_3", + "CMT_PHASER_OUT_CA_TESTIN14", + "CMT_TOP_IMUX9_0", + "CMT_TOP_NW4A1_7", + "CMT_TOP_WW2A3_5", + "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "CMT_TOP_FAN2_0", + "CMT_TOP_IMUX19_6", + "CMT_TOP_IMUX30_5", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_FAN4_8", + "CMT_PHASER_IN_B_RCLK1", + "CMT_TOP_NW4END2_5", + "CMT_TOP_IMUX34_3", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WW2END2_4", + "CMT_PHASER_IN_DB_TESTIN6", + "CMT_PHASER_IN_DB_STG1REGR3", + "CMT_TOP_CLK0_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4C3_7", + "CMT_TOP_WW4A3_1", + "CMT_TOP_WL1END3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_IMUX35_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_SW4A3_4", + "CMT_TOP_IMUX10_0", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NW2A0_2", + "CMT_TOP_LH11_3", + "CMT_TOP_IMUX17_6", + "CMT_TOP_WL1END3_7", + "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_SE2A1_2", + "CMT_TOP_IMUX7_0", + "CMT_TOP_IMUX34_8", + "CMT_TOP_IMUX20_2", + "CMT_TOP_LH8_7", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WW4A2_5", + "CMT_TOP_WR1END3_3", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_OCLK_6", + "CMT_TOP_IMUX46_4", + "CMT_TOP_WW4C2_4", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_IMUX22_0", + "CMT_TOP_SE4C1_0", + "CMT_TOP_IMUX14_5", + "CMT_TOP_BYP4_7", + "CMT_PHASER_IN_CA_STG1REGR8", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_EE4C1_1", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX13_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_BYP0_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_NW2A1_8", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX7_5", + "CMT_TOP_SE4C2_1", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_WW2A1_5", + "CMT_TOP_SE4C2_3", + "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "CMT_TOP_NE4C0_3", + "CMT_LR_LOWER_T_CLK_MMCM5", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_NW4END3_4", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX27_5", + "CMT_TOP_OCLK_0", + "CMT_TOP_LH7_8", + "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "CMT_TOP_LH9_8", + "CMT_PHASER_IN_CA_DIVIDERST", + "CMT_TOP_IMUX7_8", + "CMT_TOP_ICLK_0", + "CMT_TOP_WW2END2_3", + "CMT_TOP_NE2A2_0", + "CMT_PHASER_OUT_CA_CTSBUS1", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END1_5", + "CMT_TOP_IMUX44_6", + "CMT_PHASER_IN_CA_MEMREFCLK", + "CMT_TOP_WW4C1_6", + "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "CMT_TOP_IMUX22_3", + "CMT_TOP_NE4C2_4", + "CMT_PHASER_IN_CA_ENSTG1", + "CMT_PHASER_IN_CA_TESTIN0", + "CMT_TOP_WL1END1_2", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_IMUX42_7", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_WL1END3_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_EE2A3_1", + "CMT_PHASER_IN_DB_ENCALIBPHY1", + "CMT_TOP_SE4C3_6", + "CMT_TOP_SE2A0_6", + "CMT_TOP_NE2A2_4", + "CMT_PHASER_OUT_CA_TESTIN2", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_SW4A3_8", + "CMT_TOP_EE4B1_7", + "CMT_TOP_SE4C1_6", + "CMT_TOP_WW2A2_0", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX13_3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_PHASER_OUT_CA_RST", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_MONITOR_P_2", + "CMT_PHASER_IN_DB_TESTIN0", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX41_4", + "CMT_TOP_WL1END0_1", + "CMT_TOP_NW4END2_4", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX28_4", + "CMT_PHASER_IN_CA_RANKSEL1", + "CMT_TOP_FAN5_1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH1_8", + "CMT_PHASER_IN_CA_TESTOUT3", + "CMT_TOP_IMUX42_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_WL1END1_1", + "CMT_PHASER_OUT_CA_TESTIN1", + "CMT_TOP_FAN5_2", + "CMT_TOP_NW2A1_1", + "CMT_TOP_FAN1_1", + "CMT_PHASER_BOT_REFMUX_0", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_IMUX5_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "CMT_TOP_SE4BEG3_1", + "CMT_LR_LOWER_T_CLK_PERF3", + "CMT_TOP_WW2END2_8", + "CMT_TOP_EE2A0_8", + "CMT_TOP_LH7_1", + "CMT_TOP_NE2A1_5", + "CMT_TOP_SW2A3_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "CMT_PHASER_OUT_CA_TESTIN13", + "CMT_TOP_CLK1_0", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "CMT_TOP_NW4A1_4", + "CMT_TOP_IMUX19_3", + "CMT_TOP_NE4C2_5", + "CMT_TOP_WW4B2_8", + "CMT_LR_LOWER_T_CLK_MMCM10", + "CMT_TOP_SE4BEG1_3", + "CMT_PHASER_IN_CA_RANKSELPHY0", + "CMT_TOP_FAN0_7", + "CMT_TOP_WW2END1_4", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_NW4END3_7", + "CMT_TOP_CLK1_2", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_EE4B0_6", + "CMT_PHASER_OUT_DB_OCLKDELAYED", + "CMT_TOP_EE4B2_5", + "CMT_TOP_IMUX42_2", + "CMT_PHASER_OUT_DB_FREQREFCLK", + "CMT_TOP_WW4B2_6", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WW2A2_2", + "CMT_TOP_SW4A2_5", + "CMT_TOP_NE2A3_2", + "CMT_PHASER_OUT_CA_SCANENB", + "CMT_TOP_IMUX43_1", + "CMT_TOP_LH3_3", + "CMT_TOP_IMUX31_2", + "CMT_PHASER_IN_CA_SCANIN", + "CMT_TOP_IMUX38_5", + "CMT_TOP_EE4C1_4", + "CMT_TOP_LH4_2", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_WW4B1_6", + "CMT_TOP_IMUX42_0", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_SW2A0_0", + "CMT_TOP_WW4A3_7", + "CMT_TOP_IMUX24_7", + "CMT_PHASERA_CTSBUS1", + "CMT_TOP_IMUX47_4", + "CMT_TOP_SW4A1_3", + "CMT_TOP_NE2A1_2", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_IMUX39_4", + "CMT_PHASER_BOT_OBURSTPENDING1", + "CMT_TOP_BYP5_2", + "CMT_PHASER_OUT_CA_EDGEADV", + "CMT_TOP_WW2A0_4", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_FAN7_8", + "CMT_PHASER_IN_DB_RANKSELPHY1", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_IMUX30_1", + "CMT_PHASER_OUT_CA_TESTOUT1", + "CMT_TOP_IMUX0_1", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_IMUX33_0", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_NE4C1_1", + "CMT_TOP_FAN6_1", + "CMT_TOP_IMUX27_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "CMT_PHASER_B_TOMMCM_OCLKDIV", + "CMT_TOP_NE4C3_8", + "CMT_TOP_IMUX28_3", + "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "CMT_TOP_IMUX1_4", + "CMT_TOP_IMUX13_4", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_IMUX37_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "CMT_TOP_EE4B1_8", + "CMT_TOP_OCLKDIV_2", + "CMT_PHASER_IN_DB_ICLKDIV", + "CMT_TOP_IMUX44_1", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX29_1", + "CMT_TOP_SE4C2_8", + "CMT_TOP_LH1_5", + "CMT_TOP_NW4A0_1", + "CMT_TOP_NE2A0_4" + ], + "tile_type": "CMT_TOP_L_LOWER_T", + "sites": [ + { + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", + "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", + "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", + "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", + "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", + "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", + "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", + "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", + "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", + "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", + "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", + "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", + "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", + "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", + "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", + "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", + "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", + "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", + "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", + "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", + "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", + "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", + "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", + "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", + "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", + "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "OCLK": "CMT_PHASER_OUT_CA_OCLK", + "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", + "RST": "CMT_PHASER_OUT_CA_RST", + "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", + "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", + "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", + "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", + "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", + "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", + "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", + "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", + "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", + "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", + "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE" + }, + "type": "PHASER_OUT_PHY", + "prefix": "PHASER_OUT_PHY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", + "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", + "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", + "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", + "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", + "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", + "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", + "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", + "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", + "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", + "RCLK": "CMT_PHASER_IN_CA_RCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", + "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", + "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", + "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", + "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", + "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", + "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", + "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", + "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "STG1READ": "CMT_PHASER_IN_CA_STG1READ", + "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", + "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", + "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", + "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", + "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", + "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", + "SCANENB": "CMT_PHASER_IN_CA_SCANENB", + "FINEINC": "CMT_PHASER_IN_CA_FINEINC", + "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", + "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", + "ICLK": "CMT_PHASER_IN_CA_ICLK", + "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", + "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", + "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", + "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", + "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", + "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", + "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", + "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", + "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", + "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", + "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", + "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", + "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", + "RST": "CMT_PHASER_IN_CA_RST", + "SCANIN": "CMT_PHASER_IN_CA_SCANIN", + "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", + "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", + "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", + "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", + "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", + "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", + "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", + "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", + "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", + "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", + "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", + "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", + "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", + "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", + "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", + "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", + "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", + "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", + "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", + "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST" + }, + "type": "PHASER_IN_PHY", + "prefix": "PHASER_IN_PHY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", + "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", + "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", + "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", + "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", + "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", + "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", + "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", + "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", + "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", + "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", + "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", + "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", + "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", + "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", + "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", + "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", + "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", + "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", + "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", + "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", + "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", + "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", + "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", + "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", + "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "OCLK": "CMT_PHASER_OUT_DB_OCLK", + "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", + "RST": "CMT_PHASER_OUT_DB_RST", + "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", + "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", + "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", + "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", + "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", + "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", + "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", + "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", + "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", + "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", + "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE" + }, + "type": "PHASER_OUT_PHY", + "prefix": "PHASER_OUT_PHY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", + "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", + "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", + "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", + "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", + "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", + "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", + "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", + "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", + "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", + "RCLK": "CMT_PHASER_IN_DB_RCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", + "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", + "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", + "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", + "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", + "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", + "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", + "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", + "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "STG1READ": "CMT_PHASER_IN_DB_STG1READ", + "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", + "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", + "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", + "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", + "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", + "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", + "SCANENB": "CMT_PHASER_IN_DB_SCANENB", + "FINEINC": "CMT_PHASER_IN_DB_FINEINC", + "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", + "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", + "ICLK": "CMT_PHASER_IN_DB_ICLK", + "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", + "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", + "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", + "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", + "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", + "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", + "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", + "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", + "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", + "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", + "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", + "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", + "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", + "RST": "CMT_PHASER_IN_DB_RST", + "SCANIN": "CMT_PHASER_IN_DB_SCANIN", + "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", + "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", + "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", + "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", + "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", + "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", + "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", + "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", + "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", + "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", + "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", + "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", + "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", + "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", + "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", + "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", + "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", + "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", + "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", + "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST" + }, + "type": "PHASER_IN_PHY", + "prefix": "PHASER_IN_PHY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_TOP_L_UPPER_B.json b/artix7/tile_type_CMT_TOP_L_UPPER_B.json index 861f78c..9c6fd1c 100644 --- a/artix7/tile_type_CMT_TOP_L_UPPER_B.json +++ b/artix7/tile_type_CMT_TOP_L_UPPER_B.json @@ -1,6524 +1,6524 @@ { - "wires": [ - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_EE2A0_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_IMUX44_11", - "CMT_TOP_BYP5_2", - "CMT_PHY_CONTROL_IBURSTPENDING3", - "CMT_TOP_EE2A3_5", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX19_0", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_TOP_LH11_4", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2END3_7", - "CMT_TOP_BYP6_0", - "CMT_TOP_NW2A2_9", - "CMT_TOP_IMUX44_1", - "CMT_TOP_NE2A1_8", - "CMT_TOP_EE4C1_11", - "CMT_TOP_IMUX39_5", - "CMT_TOP_WW2A2_6", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_TOP_IMUX44_10", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_TOP_NW2A0_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_NW4A0_2", - "CMT_TOP_WW2END0_8", - "CMT_TOP_SW4A0_1", - "CMT_FREQ_BB_PREF_IN2", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_WW4A2_2", - "CMT_TOP_IMUX23_0", - "CMT_R_TOP_UPPER_B_CLKFBIN", - "CMT_TOP_WW4C0_8", - "CMT_TOP_BYP6_1", - "CMT_TOP_SE2A0_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_SW2A2_1", - "CMT_TOP_FAN0_1", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_TOP_WW4END0_6", - "CMT_TOP_SW2A1_4", - "CMT_R_TOP_UPPER_B_CLKPLL2", - "CMT_TOP_EE2A2_10", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_EE4B1_10", - "CMT_TOP_BYP5_3", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_WW4B0_10", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_WW4C2_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX14_3", - "CMT_TOP_BYP7_6", - "CMT_PHASERD_DTSBUS1", - "CMT_TOP_NW2A2_8", - "CMT_TOP_SE2A1_0", - "CMT_TOP_CTRL1_4", - "CMT_TOP_ICLK_11", - "CMT_PHASER_REF_TESTOUT7", - "CMT_TOP_IMUX0_0", - "CMT_TOP_FAN7_11", - "CMT_TOP_IMUX15_11", - "CMT_TOP_EL1BEG0_0", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_PHY_CONTROL_IRANKD1", - "CMT_TOP_NW4END1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_EE4C0_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_IMUX10_0", - "CMT_PHASER_OUT_D_OCLKDIV", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_TOP_NW2A2_1", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_NE4C0_0", - "CMT_TOP_EE2A1_11", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_WW4END0_3", - "CMT_TOP_IMUX28_9", - "CMT_PHASER_REF_PWRDWN", - "CMT_TOP_NE4C3_6", - "CMT_TOP_LH9_1", - "CMT_TOP_EE4A3_1", - "CMT_TOP_WW2A0_6", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_IMUX10_4", - "CMT_TOP_BYP0_1", - "CMT_TOP_NE2A0_4", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX19_10", - "CMT_PHASER_REF_TESTOUT5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_EE2BEG3_6", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_FREQ_PHASER_REFMUX_1", - "CMT_TOP_LH10_7", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_WW4B3_11", - "CMT_TOP_NW4A3_1", - "CMT_TOP_EE4A2_6", - "CMT_TOP_WL1END0_10", - "CMT_TOP_SW2A3_4", - "CMT_TOP_IMUX41_11", - "CMT_TOP_OCLK_2", - "CMT_TOP_SE4C3_11", - "CMT_TOP_EE4B2_3", - "CMT_PHY_CONTROL_INRANKB1", - "CMT_PHY_CONTROL_IBURSTPENDING0", - "CMT_TOP_SE2A0_2", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LH11_7", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX12_6", - "CMT_TOP_SW4END3_6", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_WW2END1_1", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_IMUX29_11", - "PLL_CLK_FREQBB_REBUFOUT0", - "CMT_TOP_WL1END2_5", - "CMT_PHASER_UP_PHASERREF1", - "CMT_TOP_WR1END1_8", - "CMT_TOP_IMUX12_5", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX39_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX10_6", - "CMT_TOP_SE2A2_7", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_EE4B3_8", - "CMT_TOP_IMUX5_8", - "CMT_TOP_WW2A1_1", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX28_4", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_TOP_IMUX2_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_SW2A2_11", - "CMT_TOP_IMUX47_5", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_WW4B1_7", - "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_WR1END2_11", - "CMT_TOP_IMUX38_5", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX6_6", - "CMT_TOP_SW4END1_0", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX30_10", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_WL1END3_6", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_SE2A2_0", - "CMT_PHY_CONTROL_TESTINPUT14", - "CMT_TOP_IMUX27_0", - "CMT_PHY_CONTROL_PHYCLK", - "CMT_TOP_SE2A2_8", - "CMT_TOP_IMUX26_10", - "CMT_TOP_WW2END2_7", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_WR1END3_7", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_IMUX39_9", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_TOP_LH11_8", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4A0_8", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_TOP_LH1_6", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX17_6", - "CMT_TOP_EE2A0_10", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_IMUX37_11", - "CMT_TOP_EE4B2_9", - "CMT_TOP_SE4C1_10", - "CMT_TOP_LH5_5", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_R_TOP_UPPER_B_CLKPLL3", - "CMT_TOP_EE2A2_5", - "CMT_TOP_LH4_8", - "CMT_TOP_IMUX45_1", - "CMT_TOP_SW4A0_4", - "CMT_TOP_FAN2_4", - "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX19_5", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_TOP_EE4B1_0", - "CMT_TOP_NW4END3_10", - "CMT_TOP_BYP7_7", - "CMT_PHASER_UP_PHASERREF_BELOW1", - "CMT_PHASER_IN_C_WRENABLE_FIFO", - "CMT_TOP_BYP3_9", - "CMT_TOP_EE4B0_9", - "CMT_TOP_IMUX25_10", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_TOP_WR1END0_3", - "CMT_TOP_SW4A2_8", - "CMT_PHY_CONTROL_TESTOUTPUT11", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_SW4A0_3", - "CMT_TOP_CLK0_6", - "CMT_TOP_SE2A3_4", - "CMT_TOP_FAN7_9", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_TOP_IMUX39_10", - "CMT_TOP_LH7_6", - "CMT_TOP_EE2A2_11", - "CMT_TOP_IMUX41_1", - "CMT_TOP_NE4C2_7", - "CMT_TOP_SW4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LH7_8", - "CMT_TOP_WR1END2_7", - "CMT_TOP_FAN6_3", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_TOP_WW2A0_7", - "CMT_TOP_BYP4_2", - "CMT_TOP_IMUX33_11", - "CMT_PHY_CONTROL_INRANKB0", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_WW4END0_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_WW4A0_7", - "CMT_TOP_LH9_3", - "CMT_TOP_NE2A0_5", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_TOP_EE4C3_2", - "CMT_PHASER_TOP_SYNC_BB", - "CMT_TOP_LH5_10", - "CMT_TOP_NE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_EE4C1_3", - "CMT_TOP_SW4A1_8", - "CMT_TOP_CTRL0_8", - "CMT_TOP_NW2A0_4", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX21_9", - "CMT_TOP_WL1END1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_TOP_LH4_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_CTRL1_0", - "CMT_TOP_LH11_10", - "CMT_R_PHASER_OUT_C_RDCLK_FIFO", - "CMT_TOP_SE2A3_11", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_SW2A3_0", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_TOP_BYP7_5", - "CMT_TOP_ICLK_7", - "CMT_TOP_WW4C3_7", - "CMT_TOP_EE4BEG1_8", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_TOP_FAN1_0", - "CMT_TOP_SW4END1_4", - "CMT_TOP_EE4C3_3", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX9_5", - "CMT_TOP_WW4B1_11", - "CMT_PHY_CONTROL_PHYCTLWD3", - "CMT_TOP_IMUX13_9", - "CMT_TOP_FAN6_8", - "CMT_TOP_SE2A2_10", - "CMT_TOP_WW4A0_0", - "CMT_TOP_CTRL0_5", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_WW2A1_11", - "CMT_TOP_IMUX14_10", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX13_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_IMUX40_1", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_IMUX7_4", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_BYP7_2", - "CMT_PHASER_IN_D_ICLKDIV", - "CMT_TOP_SE4C1_0", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_TOP_IMUX15_4", - "CMT_PHY_CONTROL_PHYCTLREADY", - "CMT_TOP_IMUX0_9", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_IMUX23_3", - "CMT_TOP_WW2A2_3", - "CMT_TOP_SE4BEG1_1", - "CMT_PHY_CONTROL_IRANKA1", - "CMT_PHY_CONTROL_WRITECALIBENABLE", - "CMT_TOP_IMUX31_3", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4B3_11", - "CMT_TOP_IMUX25_8", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_TOP_EE2A3_11", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX12_9", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_TOP_EE2A1_10", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NW2A3_0", - "CMT_TOP_SW4A3_10", - "CMT_TOP_WL1END0_3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_WW2A3_5", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_WW2END1_3", - "CMT_TOP_SW2A2_5", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_IMUX28_11", - "CMT_TOP_IMUX42_11", - "CMT_TOP_WW2END2_10", - "CMT_TOP_EE4B3_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_LH10_3", - "CMT_TOP_IMUX47_9", - "CMT_TOP_LH10_1", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_IMUX17_1", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_BYP4_0", - "CMT_TOP_FAN2_9", - "CMT_TOP_SE4C3_8", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NE2A2_1", - "CMT_TOP_IMUX37_5", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX20_6", - "CMT_TOP_WW4C1_9", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_SE4C3_4", - "CMT_TOP_NE4C3_11", - "CMT_TOP_IMUX33_5", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_EE4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BYP5_4", - "CMT_PHY_CONTROL_PHYCTLWD11", - "CMT_TOP_LH10_9", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_NW4A1_10", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_IMUX25_9", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EE4B0_10", - "CMT_TOP_WW4END3_2", - "CMT_TOP_IMUX30_8", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX16_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_IMUX11_11", - "CMT_TOP_NW4END1_6", - "CMT_TOP_WW2A0_11", - "CMT_TOP_IMUX34_4", - "CMT_TOP_SW4END2_7", - "CMT_PHASER_REF_TESTIN3", - "CMT_TOP_LH12_0", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_SW4A3_11", - "CMT_TOP_NW4END2_8", - "CMT_TOP_IMUX36_0", - "CMT_TOP_FAN7_8", - "CMT_TOP_LH3_3", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_SE4C0_10", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX10_5", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_WW2A3_0", - "CMT_TOP_LH3_4", - "CMT_TOP_IMUX16_6", - "CMT_TOP_FAN2_11", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX40_4", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_IMUX38_0", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_WW4A1_10", - "CMT_PHY_CONTROL_PHYCTLWD12", - "CMT_TOP_NW4A3_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SW4END3_9", - "CMT_TOP_SW4END3_2", - "CMT_TOP_LH8_5", - "CMT_TOP_EE4B2_10", - "CMT_TOP_WW2A2_5", - "CMT_TOP_IMUX29_0", - "CMT_TOP_EE4A0_8", - "CMT_TOP_OCLKDIV_4", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_TOP_IMUX16_7", - "CMT_TOP_NW4END0_2", - "CMT_TOP_FAN1_1", - "CMT_TOP_LH1_4", - "CMT_PHY_CONTROL_TESTOUTPUT3", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_TOP_SW2A2_9", - "CMT_TOP_IMUX45_9", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_SE4C0_7", - "CMT_PHY_CONTROL_PHYCTLWD23", - "CMT_PHY_CONTROL_TESTINPUT9", - "CMT_TOP_IMUX46_3", - "CMT_TOP_SW4END2_2", - "CMT_TOP_WW4B3_5", - "CMT_TOP_IMUX6_7", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_NW4A0_7", - "CMT_TOP_EE4A1_6", - "CMT_TOP_FAN2_0", - "CMT_PHY_CONTROL_TESTOUTPUT5", - "CMT_TOP_WW4A0_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX37_2", - "CMT_TOP_MONITOR_P_7", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_TOP_WW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_IMUX45_8", - "CMT_PHY_CONTROL_TESTINPUT7", - "CMT_TOP_FAN0_4", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SE4C0_3", - "CMT_TOP_IMUX29_6", - "CMT_TOP_EE2BEG2_6", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WW2END1_2", - "CMT_PHY_CONTROL_TESTOUTPUT7", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_TOP_SW4A1_6", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_FAN3_9", - "CMT_TOP_EE4A1_3", - "CMT_TOP_OCLK_11", - "CMT_TOP_WW2END2_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_WW4END3_9", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_TOP_IMUX26_1", - "CMT_TOP_CLK1_2", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_IMUX31_10", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_WL1END0_8", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_IMUX29_7", - "CMT_TOP_NE2A3_6", - "CMT_TOP_WW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_IMUX27_2", - "CMT_TOP_NE2A1_6", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_NW2A3_8", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_TOP_LH7_1", - "CMT_TOP_WW4END1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_IMUX13_2", - "CMT_TOP_WW4END2_7", - "CMT_TOP_NW4END1_0", - "CMT_TOP_EE4C0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_NE4C2_9", - "CMT_TOP_SE4BEG1_4", - "CMT_PHASERD_CTSBUS0", - "CMT_TOP_IMUX29_5", - "CMT_TOP_NW2A1_5", - "CMT_TOP_WW2END0_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX40_7", - "CMT_TOP_FAN7_10", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_BYP6_2", - "CMT_TOP_IMUX42_7", - "CMT_TOP_BYP5_5", - "CMT_TOP_WW2A3_10", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX2_1", - "CMT_TOP_FAN5_7", - "CMT_PHASER_REF_TESTIN7", - "CMT_TOP_SE2A2_6", - "CMT_TOP_IMUX12_11", - "CMT_TOP_EE4B1_8", - "CMT_TOP_NE2A3_4", - "CMT_TOP_SW4A3_7", - "CMT_TOP_WL1END2_11", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_IMUX24_9", - "CMT_TOP_LH1_10", - "CMT_TOP_SW4A1_9", - "CMT_PHY_CONTROL_TESTSELECT2", - "CMT_TOP_SW2A3_1", - "CMT_TOP_EE2A1_0", - "CMT_TOP_WW4C3_5", - "CMT_TOP_IMUX14_11", - "CMT_TOP_IMUX24_1", - "CMT_TOP_BYP1_0", - "CMT_TOP_WW4B0_8", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_TOP_WW4B0_7", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_NE2A1_2", - "CMT_TOP_BYP6_11", - "CMT_TOP_IMUX7_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_IMUX30_4", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_WW2END3_1", - "CMT_TOP_IMUX22_0", - "CMT_TOP_WW2A3_6", - "CMT_TOP_EE4A0_6", - "CMT_TOP_SE4C2_9", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_EE4A0_9", - "CMT_TOP_FAN6_7", - "CMT_TOP_WW4A0_10", - "CMT_TOP_LH5_9", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_TOP_ICLK_2", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_NW4END3_0", - "CMT_TOP_SW2A1_2", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_TOP_FAN1_5", - "CMT_TOP_CTRL0_7", - "CMT_TOP_NW4END3_7", - "CMT_TOP_WW2A0_9", - "CMT_TOP_SE4C1_9", - "CMT_TOP_IMUX44_2", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW2END0_3", - "CMT_TOP_LH10_2", - "CMT_TOP_NE4C2_2", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_TOP_IMUX9_6", - "CMT_TOP_NW4END3_3", - "CMT_TOP_IMUX45_2", - "CMT_TOP_SW4A2_11", - "CMT_TOP_FAN6_1", - "CMT_TOP_IMUX22_9", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "CMT_TOP_IMUX13_5", - "CMT_TOP_SW4A3_8", - "CMT_PHASER_IN_DB_RST", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_LH12_8", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_IMUX31_11", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_WW4END0_1", - "CMT_TOP_EE4B0_6", - "CMT_TOP_BYP3_0", - "CMT_TOP_EE4B0_7", - "CMT_TOP_LH9_10", - "CMT_PHASER_REF_TESTOUT6", - "CMT_TOP_EE2A0_11", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_TOP_SW4END2_0", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_EE2A1_4", - "CMT_TOP_IMUX1_5", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX5_5", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_TOP_IMUX35_1", - "CMT_TOP_WW2END1_8", - "CMT_TOP_IMUX19_9", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_WW4A2_9", - "CMT_PHY_CONTROL_PHYCTLWD25", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_TOP_EE4B2_2", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_WW4C3_4", - "CMT_TOP_EE4BEG2_10", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_TOP_NE2A0_6", - "CMT_TOP_BYP1_5", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_IMUX11_10", - "CMT_TOP_FAN1_3", - "CMT_TOP_SE2A3_7", - "CMT_TOP_LH2_6", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_IMUX25_2", - "CMT_TOP_WR1END3_4", - "CMT_TOP_CTRL1_11", - "CMT_TOP_IMUX26_9", - "CMT_TOP_IMUX35_10", - "CMT_TOP_FAN0_3", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_WW4B3_10", - "CMT_TOP_NE2A2_8", - "CMT_TOP_FAN0_7", - "CMT_TOP_IMUX32_3", - "CMT_TOP_LH7_9", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_PHY_CONTROL_TESTINPUT13", - "CMT_TOP_CLK0_10", - "CMT_TOP_IMUX40_11", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WW4B1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_BYP6_5", - "CMT_TOP_WW2A0_10", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_IMUX39_2", - "CMT_TOP_SW4A1_11", - "CMT_TOP_WR1END3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_CTRL0_4", - "CMT_TOP_LH4_5", - "CMT_TOP_SW4END1_7", - "CMT_TOP_NW4END3_4", - "CMT_TOP_EE4C3_4", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_IMUX46_10", - "CMT_TOP_NW4A0_5", - "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "CMT_PHY_CONTROL_TESTOUTPUT12", - "CMT_TOP_SW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_TOP_IMUX2_11", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_PHY_CONTROL_TESTINPUT8", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_TOP_IMUX0_3", - "CMT_PHASER_IN_D_ICLK", - "CMT_TOP_OCLK_5", - "CMT_TOP_FAN5_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_WL1END0_2", - "CMT_TOP_BYP0_5", - "CMT_TOP_NW2A0_10", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_EE2BEG2_1", - "CMT_PHASER_C_OCLKDIV_TOIOI", - "CMT_TOP_IMUX35_4", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_EE2A2_7", - "CMT_TOP_SE2A2_2", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_IMUX9_4", - "CMT_TOP_SW4A2_1", - "CMT_TOP_WW4A3_11", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SW4END0_3", - "CMT_TOP_IMUX46_0", - "CMT_TOP_WW2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LH7_0", - "CMT_PHASER_REF_TESTOUT1", - "CMT_TOP_WW2A2_0", - "CMT_TOP_IMUX34_11", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_CTRL0_2", - "CMT_TOP_IMUX23_9", - "CMT_TOP_WL1END1_3", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_WW4A2_10", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_ER1BEG1_0", - "CMT_PHY_CONTROL_PHYCTLWD29", - "CMT_TOP_SW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_IMUX16_1", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_TOP_IMUX35_11", - "CMT_TOP_NE2A3_5", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_NW2A1_1", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP5_7", - "CMT_TOP_IMUX6_1", - "CMT_PHASER_REF_TESTOUT0", - "CMT_TOP_LH4_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SW2A3_7", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4END1_10", - "CMT_TOP_IMUX44_0", - "CMT_TOP_BYP7_11", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX28_1", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LH8_1", - "CMT_TOP_WW4A0_3", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_IMUX2_10", - "CMT_TOP_CLK1_0", - "CMT_TOP_IMUX27_4", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_7", - "CMT_TOP_IMUX40_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_NW2A0_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_NW4A1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_WW2A1_9", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_TOP_BYP1_11", - "CMT_TOP_SE4C2_7", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_NE4C1_7", - "CMT_TOP_WW4B2_1", - "CMT_TOP_EE2BEG3_4", - "CMT_PHASERD_DQSBUS1", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_NE4C0_11", - "CMT_TOP_EE4BEG3_7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_TOP_WL1END2_8", - "CMT_TOP_SE2A3_2", - "CMT_TOP_LH8_3", - "CMT_TOP_IMUX13_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_IMUX30_7", - "CMT_TOP_WW4C3_2", - "CMT_PHY_CONTROL_MEMREFCLK", - "CMT_TOP_SW4END1_8", - "CMT_TOP_EE4B0_2", - "CMT_TOP_BYP6_10", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_LH5_1", - "CMT_TOP_EE4B2_11", - "CMT_TOP_BYP4_9", - "CMT_TOP_SE2A1_10", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_WR1END3_2", - "CMT_TOP_LH8_10", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_MONITOR_N_2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_TOP_IMUX34_7", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_PHASERREF_PHASEROUT_D", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_NW4A2_7", - "CMT_TOP_LH9_11", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EE2A2_1", - "CMT_TOP_FAN4_6", - "CMT_TOP_EE4B3_9", - "CMT_TOP_BYP3_11", - "CMT_TOP_WW4END1_1", - "CMT_TOP_FAN0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_BYP0_11", - "CMT_TOP_NE4C0_5", - "CMT_TOP_SW2A0_8", - "CMT_TOP_NW2A2_2", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX0_10", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_WR1END1_11", - "CMT_PHASERTOP_PHYCTLEMPTY", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_BYP4_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_EE2A1_6", - "CMT_TOP_NE2A1_5", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2A3_3", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_FAN3_4", - "CMT_TOP_LH7_5", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX17_11", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_L_TOP_UPPER_B_CLKINT_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_IMUX43_8", - "CMT_TOP_SE2A3_5", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4C1_6", - "CMT_TOP_WW4C0_2", - "CMT_TOP_LH12_7", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_EE2A1_9", - "CMT_TOP_WW2END2_5", - "CMT_TOP_IMUX0_6", - "CMT_PHY_CONTROL_AUXOUTPUT2", - "CMT_TOP_BYP4_5", - "CMT_TOP_IMUX22_3", - "CMT_TOP_NE2A2_6", - "CMT_PHY_CONTROL_TESTOUTPUT14", - "CMT_TOP_FAN5_10", - "CMT_TOP_EE4A0_7", - "CMT_TOP_WW2END1_10", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_IMUX38_11", - "CMT_TOP_WW2END2_11", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WW4B2_5", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_NE2A2_9", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_IMUX2_8", - "CMT_TOP_WW2END3_2", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WW2A2_10", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_IMUX28_2", - "CMT_PHY_CONTROL_TESTOUTPUT4", - "CMT_TOP_WW4C1_4", - "CMT_TOP_EE4C2_7", - "CMT_TOP_LH12_1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_TOP_NE2A0_3", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE4C0_4", - "CMT_PHY_CONTROL_TESTSELECT1", - "CMT_TOP_LH11_0", - "CMT_TOP_WW2A1_2", - "CMT_TOP_FAN6_2", - "CMT_TOP_IMUX22_7", - "CMT_TOP_WW2END3_4", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SW4A1_0", - "CMT_TOP_IMUX1_8", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_TOP_WW4C2_4", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_2", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_IMUX20_11", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4END3_10", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_TOP_CLK0_2", - "CMT_TOP_IMUX11_2", - "CMT_TOP_WW2END0_5", - "CMT_TOP_SE4BEG1_0", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_WW4B1_1", - "CMT_TOP_LH6_7", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE4B2_8", - "CMT_TOP_WW4A3_6", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_OUT_DB_DIVIDERST", - "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "CMT_TOP_BYP5_11", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_EE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_CLK1_3", - "CMT_TOP_IMUX34_0", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_IMUX30_11", - "CMT_TOP_SE2A3_8", - "CMT_PHASER_C_OCLK90_TOIOI", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX30_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_FAN7_3", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_TOP_IMUX33_6", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_NW4END1_9", - "CMT_TOP_WW4END2_10", - "CMT_TOP_SW4END0_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_WW4END1_6", - "CMT_TOP_IMUX16_10", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_WR1END3_1", - "CMT_TOP_IMUX26_11", - "CMT_TOP_NE2A0_0", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX28_6", - "CMT_TOP_SE4C2_11", - "CMT_TOP_EE4A2_2", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX24_0", - "CMT_TOP_NW4END2_4", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW4C3_3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_TOP_SE4BEG3_3", - "CMT_PHASER_OUT_C_OCLKDIV", - "CMT_TOP_EE4C3_5", - "CMT_TOP_SE2A0_8", - "CMT_TOP_IMUX0_2", - "CMT_TOP_EE4C0_5", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX36_4", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_WR1END1_4", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_TOP_SW4END0_11", - "CMT_TOP_LH5_8", - "CMT_TOP_LH8_9", - "CMT_TOP_IMUX21_0", - "CMT_TOP_WL1END0_7", - "CMT_TOP_SW2A0_6", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_WW4END3_6", - "CMT_TOP_IMUX7_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_EE2A1_5", - "CMT_TOP_NW2A0_8", - "CMT_TOP_IMUX21_10", - "CMT_TOP_SW2A2_6", - "CMT_TOP_IMUX26_0", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_IMUX23_1", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_BYP0_0", - "CMT_TOP_SW4END0_7", - "CMT_TOP_IMUX41_8", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_TOP_BYP3_4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_TOP_WW4C2_1", - "CMT_TOP_BYP1_3", - "CMT_TOP_IMUX8_0", - "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_IMUX43_3", - "CMT_TOP_NW4A2_8", - "CMT_PHY_CONTROL_PHYCTLWD2", - "CMT_TOP_WR1END3_6", - "CMT_TOP_ICLK_5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_TOP_WW2END2_4", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_IMUX18_11", - "CMT_TOP_NW4A2_9", - "CMT_TOP_WW4END0_0", - "CMT_R_TOP_UPPER_B_CLKPLL7", - "CMT_TOP_NW4END0_11", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_WW4C2_11", - "CMT_TOP_IMUX18_5", - "CMT_TOP_SE2A1_7", - "CMT_PHASER_REF_TESTIN0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_TOP_SW2A1_1", - "CMT_TOP_BYP3_10", - "CMT_PHASER_UP_DQS_TO_PHASER_D", - "CMT_PHY_CONTROL_AUXOUTPUT3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX20_5", - "CMT_TOP_NW2A2_3", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_TOP_IMUX24_8", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LH3_5", - "CMT_TOP_IMUX26_2", - "CMT_TOP_WW4A0_11", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_PHY_CONTROL_PHYCTLWD17", - "CMT_TOP_IMUX19_8", - "CMT_PHY_CONTROL_PHYCTLWD6", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_SE2A1_3", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_TOP_BYP4_11", - "CMT_TOP_NW4A3_10", - "CMT_TOP_FAN1_7", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_WW4A2_0", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_TOP_IMUX28_10", - "CMT_TOP_NE4C1_10", - "CMT_TOP_WW2A3_9", - "CMT_PHY_CONTROL_INRANKD1", - "CMT_TOP_EE4A1_4", - "CMT_TOP_IMUX16_4", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_IMUX46_5", - "CMT_TOP_NE2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_WR1END2_8", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX26_7", - "CMT_PHASER_REF_TESTIN2", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_NW4END2_10", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2A3_6", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_FAN3_8", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_NW4END0_1", - "CMT_TOP_OCLK1X_90_9", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_FAN3_6", - "CMT_TOP_EE2A3_10", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_SW4END3_1", - "CMT_TOP_IMUX22_11", - "CMT_TOP_WW4A2_7", - "CMT_TOP_NW4A2_1", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW4C3_8", - "CMT_TOP_NE2A0_8", - "CMT_TOP_IMUX12_10", - "CMT_TOP_WW4C3_9", - "CMT_TOP_NE2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_FAN5_9", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_FAN3_0", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_3", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_TOP_SW2A0_7", - "CMT_TOP_IMUX3_1", - "CMT_TOP_NE4C0_1", - "CMT_TOP_WL1END3_4", - "CMT_TOP_IMUX37_9", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_NW4END3_5", - "CMT_TOP_WW2A2_7", - "CMT_TOP_FAN2_5", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WL1END3_0", - "CMT_PHASER_IN_DB_ICLK", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_IMUX36_1", - "CMT_TOP_SW2A1_9", - "CMT_TOP_EE4A3_2", - "CMT_TOP_IMUX15_10", - "CMT_TOP_IMUX27_6", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LH3_6", - "CMT_TOP_WW2END2_0", - "CMT_TOP_IMUX11_7", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_TOP_IMUX43_2", - "CMT_TOP_NE4C3_9", - "CMT_TOP_WW2END2_9", - "CMT_PHASER_REF_TESTIN6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_TOP_WW4C1_6", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4B2_9", - "CMT_TOP_IMUX4_5", - "CMT_TOP_EE4C0_9", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_CA_TESTIN4", - "CMT_TOP_ER1BEG3_3", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_WR1END2_10", - "CMT_TOP_NE4C1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_WW2A0_8", - "CMT_TOP_SE4C2_8", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_TOP_IMUX38_8", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_LH1_3", - "CMT_TOP_BYP1_2", - "CMT_TOP_IMUX26_5", - "CMT_TOP_SE4C3_10", - "CMT_TOP_EE2BEG0_11", - "CMT_PHY_CONTROL_TESTOUTPUT6", - "CMT_TOP_NE4C0_10", - "CMT_TOP_ICLKDIV_6", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_PHY_CONTROL_OBURSTPENDING1", - "CMT_TOP_IMUX12_3", - "CMT_PHY_CONTROL_INRANKA0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_IMUX38_6", - "CMT_TOP_LH6_10", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_WW4B3_4", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_IMUX1_10", - "CMT_TOP_WW2END0_9", - "CMT_PHY_CONTROL_PHYCTLFULL", - "CMT_TOP_SE2A0_9", - "CMT_TOP_IMUX8_9", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_TOP_IMUX36_7", - "CMT_PHY_CONTROL_OBURSTPENDING3", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_IMUX39_8", - "CMT_TOP_WW4B0_5", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_BYP4_7", - "CMT_TOP_IMUX43_9", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_NE4BEG3_2", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_TOP_WW2END3_10", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_SW2A0_5", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_SW4END1_9", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_PHASER_UP_PHASERREF_ABOVE0", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_TOP_FAN0_2", - "CMT_TOP_IMUX19_1", - "CMT_TOP_NW2A3_11", - "CMT_TOP_IMUX41_0", - "CMT_TOP_FAN3_2", - "PLL_CLK_FREQBB_REBUFOUT3", - "CMT_TOP_WW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_SW2A3_6", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_TOP_WW2A1_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SE2A1_11", - "CMT_TOP_WW4A0_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_EE4B0_0", - "CMT_TOP_NW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_NW2A3_3", - "CMT_TOP_SE4C0_8", - "CMT_PHY_CONTROL_PHYCTLWD13", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4END2_3", - "CMT_TOP_NE2A3_10", - "CMT_TOP_LH1_5", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_WW4B2_10", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_TOP_SW4END2_1", - "CMT_TOP_EE4B3_4", - "CMT_TOP_SW4END1_3", - "CMT_TOP_IMUX25_6", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LH9_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX37_3", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_LH1_9", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EL1BEG1_10", - "CMT_PHY_CONTROL_PHYCTLWD21", - "CMT_TOP_IMUX36_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_WW4A3_3", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_TOP_LH2_8", - "CMT_TOP_IMUX17_8", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_TOP_IMUX29_8", - "CMT_PHY_CONTROL_TESTOUTPUT1", - "CMT_TOP_IMUX34_10", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_WW4A3_2", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_TOP_EE4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_NE2A2_11", - "CMT_TOP_LH3_1", - "CMT_TOP_SW4A3_5", - "CMT_PHY_CONTROL_IBURSTPENDING1", - "CMT_TOP_EL1BEG3_7", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_TOP_WW4END1_5", - "CMT_TOP_IMUX45_10", - "CMT_PHY_CONTROL_PHYCTLWD8", - "CMT_PHY_CONTROL_REFDLLLOCK", - "CMT_TOP_IMUX25_3", - "CMT_PHY_CONTROL_PHYCTLWD7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_NW4END2_11", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_EE2BEG1_5", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX5_10", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_WW2A3_3", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_TOP_EE4A2_3", - "CMT_TOP_SW4A1_1", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_8", - "CMT_TOP_WW4A1_6", - "CMT_PHY_CONTROL_OBURSTPENDING0", - "CMT_TOP_IMUX41_2", - "CMT_TOP_LH8_6", - "CMT_TOP_SE4C1_8", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WW4A2_6", - "CMT_TOP_BYP0_6", - "CMT_TOP_IMUX43_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_IMUX31_0", - "CMT_TOP_WR1END2_1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_TOP_NW4END3_11", - "CMT_TOP_WR1END3_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_PHASER_OUT_D_OCLK", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_NW4A0_4", - "CMT_TOP_IMUX24_4", - "CMT_TOP_EE4C1_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WW4C1_8", - "CMT_TOP_NW2A0_7", - "CMT_TOP_LH1_11", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_TOP_IMUX22_1", - "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "CMT_TOP_IMUX17_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_IMUX19_11", - "CMT_PHY_CONTROL_PHYCTLWD26", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX10_9", - "CMT_TOP_EE2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_TOP_CLK1_4", - "CMT_TOP_LH2_2", - "CMT_TOP_NE4BEG2_7", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_TOP_NE4C2_3", - "CMT_TOP_EE4A2_7", - "CMT_TOP_IMUX11_0", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_ER1BEG1_1", - "CMT_PHASER_IN_C_RCLK2", - "CMT_TOP_IMUX38_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_10", - "CMT_TOP_LH3_9", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_10", - "CMT_TOP_NW4END2_2", - "CMT_TOP_WW2A2_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_LH4_9", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4B0_6", - "CMT_TOP_BYP1_9", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_NW4A1_5", - "CMT_TOP_SE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_SW4END3_10", - "CMT_TOP_IMUX9_1", - "CMT_TOP_NW4A1_9", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_BYP7_8", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX4_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_IMUX30_1", - "CMT_TOP_WW4C0_5", - "CMT_TOP_NW4A1_2", - "CMT_R_TOP_UPPER_B_CLKPLL6", - "CMT_TOP_WW2END0_2", - "CMT_TOP_FAN0_0", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX18_8", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX20_4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_TOP_EE4C3_6", - "CMT_PHY_CONTROL_PHYCTLWD31", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_IMUX39_11", - "CMT_PHASER_OUT_D_OCLK1X_90", - "CMT_PHY_CONTROL_TESTINPUT0", - "CMT_PHASER_REF_LOCKED", - "CMT_TOP_NE4C0_2", - "CMT_TOP_EE4B1_2", - "CMT_TOP_IMUX4_9", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SE4C1_1", - "CMT_TOP_EE4A1_9", - "CMT_TOP_IMUX30_2", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_EE2A2_2", - "CMT_TOP_WW4A2_8", - "CMT_TOP_MONITOR_P_2", - "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "CMT_TOP_IMUX23_8", - "CMT_TOP_SW4END0_6", - "CMT_TOP_IMUX12_2", - "CMT_TOP_NW2A2_7", - "CMT_TOP_WL1END2_7", - "CMT_TOP_BYP5_1", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_TOP_EE4B1_9", - "CMT_TOP_IMUX33_0", - "CMT_TOP_WW2A2_9", - "CMT_TOP_EL1BEG2_4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_UP_BUFMRCE_CE1", - "CMT_TOP_OCLK_7", - "CMT_TOP_FAN1_10", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_SW2A1_10", - "CMT_TOP_IMUX19_7", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_SE4C0_6", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_IMUX3_0", - "CMT_TOP_WL1END1_8", - "CMT_TOP_NW4END1_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_LH6_2", - "CMT_TOP_IMUX39_6", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_IMUX36_2", - "CMT_PHY_CONTROL_RESET", - "CMT_TOP_WW2A0_5", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_BYP2_0", - "CMT_TOP_IMUX8_3", - "CMT_TOP_ICLK_6", - "CMT_TOP_LH2_0", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHY_CONTROL_INRANKD0", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_TOP_IMUX16_3", - "CMT_PHY_CONTROL_TESTINPUT10", - "CMT_TOP_IMUX40_2", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_WW4END3_1", - "CMT_TOP_SW4A2_4", - "CMT_TOP_LH11_11", - "CMT_TOP_IMUX46_2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NW4A3_2", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_IMUX17_10", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX19_2", - "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW4END1_3", - "CMT_TOP_NW2A3_7", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_NW4A3_8", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SE2A0_11", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_WW2END0_7", - "CMT_TOP_EE4C0_6", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_EE4C0_7", - "CMT_TOP_WL1END0_0", - "CMT_TOP_FAN7_2", - "CMT_TOP_WL1END3_1", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_LH8_4", - "CMT_TOP_LH5_6", - "CMT_TOP_BYP2_11", - "CMT_TOP_SW4A0_6", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_BYP7_4", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_TOP_LH10_6", - "CMT_TOP_SE4C2_4", - "CMT_TOP_IMUX35_9", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_IMUX46_4", - "CMT_TOP_LH4_2", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_TESTOUT1", - "CMT_TOP_IMUX44_3", - "CMT_TOP_EE4A3_8", - "CMT_TOP_IMUX24_2", - "CMT_TOP_EE4A3_11", - "CMT_TOP_IMUX14_5", - "CMT_PHASER_IN_DB_STG1REGR1", - "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "CMT_TOP_IMUX34_5", - "CMT_TOP_NW4END2_9", - "CMT_TOP_IMUX20_9", - "CMT_TOP_IMUX29_1", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_SW4A2_3", - "CMT_TOP_FAN1_9", - "CMT_TOP_BYP7_1", - "CMT_TOP_WW2A3_11", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_TOP_WL1END3_8", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX19_6", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX17_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_OCLK_0", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX13_11", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_TOP_WL1END1_11", - "CMT_TOP_IMUX2_2", - "CMT_TOP_WW4END3_5", - "CMT_TOP_LH1_1", - "CMT_TOP_FAN5_8", - "CMT_TOP_NW4END3_8", - "CMT_TOP_WW4A1_1", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_TOP_NE4BEG3_1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_TOP_EE2A3_2", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_WW2END2_3", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_WW2END2_6", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_TOP_IMUX41_10", - "CMT_TOP_EE4B2_1", - "CMT_TOP_NW4END3_1", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_LH3_0", - "CMT_TOP_LH2_5", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_EE4A3_3", - "CMT_TOP_NW4A2_3", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_SW4END3_0", - "CMT_TOP_IMUX34_8", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_TOP_SW4A2_10", - "CMT_TOP_NW2A3_1", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX32_11", - "CMT_TOP_WW4B3_7", - "CMT_TOP_LH11_9", - "CMT_TOP_NE2A2_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_NW4A2_0", - "CMT_TOP_WW4C2_10", - "CMT_TOP_BYP7_0", - "CMT_TOP_LH6_0", - "CMT_TOP_NE4C1_4", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_TOP_IMUX16_9", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_PHASER_REF_TESTOUT4", - "CMT_TOP_EE4A0_10", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_IMUX5_2", - "CMT_TOP_WW4C0_10", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "CMT_TOP_FAN1_2", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_NE4BEG2_2", - "CMT_PHY_CONTROL_TESTINPUT4", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_WW4B2_6", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_IMUX29_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LH3_11", - "CMT_TOP_IMUX32_7", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_BYP2_3", - "CMT_TOP_IMUX1_6", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_TOP_WR1END2_4", - "CMT_PHY_CONTROL_TESTOUTPUT2", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX20_3", - "CMT_TOP_LH7_3", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX28_8", - "CMT_TOP_NW4END2_5", - "CMT_TOP_WW2A0_3", - "CMT_PHASERD_DQSBUS0", - "CMT_TOP_IMUX33_9", - "CMT_TOP_WR1END1_9", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX23_11", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_TOP_SW4END2_4", - "CMT_TOP_FAN6_0", - "CMT_TOP_LH6_11", - "CMT_PHY_CONTROL_TESTOUTPUT13", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_IMUX4_3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_TOP_SW4END3_3", - "CMT_TOP_WW4B0_3", - "CMT_TOP_BYP3_2", - "CMT_TOP_CTRL0_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_CLK1_8", - "CMT_TOP_FAN3_3", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_IMUX42_0", - "CMT_TOP_LH12_4", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_TOP_SW2A0_9", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_TOP_FAN0_6", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_R_TOP_UPPER_B_CLKIN2", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_R_TOP_UPPER_B_CLKPLL5", - "CMT_TOP_SW4END0_1", - "CMT_TOP_FAN5_11", - "CMT_TOP_IMUX1_0", - "CMT_TOP_NW2A3_4", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_WW4END1_9", - "CMT_TOP_EE2A2_4", - "CMT_TOP_WL1END0_4", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_IMUX4_10", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_OCLK1X_90_0", - "CMT_PHASER_REF_TESTIN4", - "CMT_TOP_SW4END3_4", - "CMT_TOP_WW4C3_1", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_WL1END0_6", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_TOP_EE4A0_3", - "CMT_TOP_NW4A3_6", - "CMT_TOP_BYP2_5", - "CMT_TOP_ICLK_0", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_PHY_CONTROL_TESTINPUT6", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_CTRL1_9", - "CMT_TOP_LH6_9", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_IMUX33_4", - "CMT_TOP_NW2A1_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_EE4B0_4", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_IMUX1_11", - "CMT_TOP_WR1END0_6", - "CMT_TOP_LH12_2", - "CMT_TOP_FAN5_5", - "CMT_TOP_IMUX4_8", - "CMT_TOP_SW2A2_7", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_TOP_IMUX43_6", - "CMT_PHASER_IN_DB_TESTIN7", - "PLL_CLK_FREQBB_REBUFOUT1", - "CMT_TOP_WW4A3_7", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_WL1END1_10", - "CMT_TOP_BYP6_3", - "CMT_TOP_FAN2_6", - "CMT_TOP_IMUX31_9", - "CMT_TOP_OCLK_3", - "CMT_TOP_WR1END1_1", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_EE4C2_8", - "CMT_TOP_IMUX30_0", - "CMT_TOP_OCLK_8", - "CMT_PHASER_REF_TESTIN1", - "CMT_TOP_FAN4_3", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_LH4_4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4C3_11", - "CMT_TOP_FAN4_8", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_TOP_NE4C2_0", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_IMUX33_1", - "CMT_TOP_EE4C1_5", - "CMT_TOP_WW4B3_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH6_8", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_TOP_NW4A1_11", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_WL1END0_1", - "CMT_TOP_NE2A3_3", - "CMT_TOP_IMUX12_8", - "CMT_TOP_EE4A1_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_WW4A1_11", - "CMT_TOP_IMUX46_9", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE4C2_6", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX18_1", - "CMT_TOP_EL1BEG3_3", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_NW4END1_10", - "CMT_TOP_IMUX20_8", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NE2A3_2", - "CMT_TOP_SE2A0_6", - "CMT_TOP_IMUX30_3", - "CMT_TOP_LH7_10", - "CMT_TOP_OCLK_6", - "CMT_PHY_CONTROL_PHYCTLWD9", - "CMT_TOP_SW4END0_9", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_IMUX4_2", - "CMT_PHY_CONTROL_PHYCTLWD1", - "CMT_TOP_IMUX37_6", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_PHASER_IN_D_WRENABLE_FIFO", - "CMT_TOP_NE4BEG1_6", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_TOP_WW4B2_3", - "CMT_PHY_CONTROL_PHYCTLWD20", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_TOP_WW4C2_5", - "CMT_TOP_EE4B2_5", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WW4A1_5", - "CMT_TOP_BYP3_7", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_FAN2_1", - "CMT_TOP_IMUX36_11", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_IMUX44_6", - "CMT_TOP_OCLK_1", - "CMT_TOP_NW2A0_9", - "CMT_TOP_IMUX36_9", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_WW4END2_2", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_TOP_LH12_9", - "CMT_PHASERD_CTSBUS1", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_NE2A2_10", - "CMT_TOP_SW4END2_9", - "CMT_TOP_EE2A2_3", - "CMT_TOP_LH4_7", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_IMUX6_0", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_PHY_CONTROL_PHYCTLWD27", - "CMT_TOP_NE2A0_9", - "CMT_TOP_WW4B3_3", - "CMT_TOP_BYP4_6", - "CMT_TOP_FAN3_10", - "CMT_TOP_BYP6_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_NE2A1_1", - "CMT_TOP_WW4END1_8", - "CMT_TOP_SW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_CTRL0_3", - "CMT_TOP_WW4B3_1", - "CMT_TOP_NW4A2_4", - "CMT_TOP_LH4_11", - "CMT_PHY_CONTROL_PLLLOCK", - "CMT_R_TOP_UPPER_B_CLKIN1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_SE4C3_3", - "CMT_TOP_WW2END1_9", - "CMT_PHASER_OUT_C_OCLK", - "CMT_TOP_NE4C3_1", - "CMT_TOP_WW2A1_3", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_TOP_WL1END3_9", - "CMT_TOP_SE4C0_4", - "CMT_TOP_IMUX9_10", - "CMT_TOP_EE4C3_0", - "CMT_TOP_WW4C1_3", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_EE4A1_11", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_TOP_NW2A2_10", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_TOP_CTRL1_8", - "CMT_TOP_WL1END1_1", - "CMT_TOP_OCLKDIV_5", - "CMT_PHY_CONTROL_INBURSTPENDING2", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_PHY_CONTROL_TESTINPUT15", - "CMT_TOP_NW2A1_11", - "CMT_TOP_EE4B2_0", - "CMT_TOP_LH5_7", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX2_5", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_CLK0_1", - "CMT_PHY_CONTROL_TESTINPUT2", - "CMT_TOP_IMUX6_4", - "CMT_TOP_NW4A2_11", - "CMT_TOP_EE2A2_8", - "CMT_TOP_SE4C3_7", - "CMT_TOP_WW4C0_7", - "CMT_TOP_EL1BEG2_0", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_TOP_SE4C2_5", - "CMT_TOP_IMUX32_0", - "CMT_TOP_SW2A3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_NE4BEG0_10", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_TOP_WW2END3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_EE4B1_4", - "CMT_PHASER_REF_CLKOUT", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX27_5", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_EE4C0_0", - "CMT_TOP_SE4BEG3_6", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_WW4B0_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_WW4END3_11", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_EE4B1_3", - "CMT_TOP_NW4END3_2", - "CMT_TOP_IMUX21_1", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_TOP_SW4END0_0", - "CMT_TOP_WW4A1_2", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW4C0_3", - "CMT_PHASER_IN_CA_RCLK", - "CMT_TOP_BYP7_10", - "CMT_TOP_IMUX6_9", - "CMT_TOP_WW4A0_1", - "CMT_TOP_EE4B1_11", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_SE4BEG2_10", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_TOP_NW4A0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NE4C3_4", - "CMT_TOP_BYP6_9", - "CMT_PHY_CONTROL_SCANENABLEN", - "CMT_PHASER_REF_TESTOUT2", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX21_4", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX29_10", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW2A0_2", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_TOP_BYP2_8", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW4C0_0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_TOP_BYP6_8", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_TOP_IMUX28_0", - "CMT_TOP_EE4A2_0", - "CMT_TOP_SW2A2_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_NE4BEG2_6", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_TOP_LH12_10", - "CMT_R_TOP_UPPER_B_CLKPLL4", - "CMT_PHASER_REF_TESTOUT3", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW4END1_10", - "CMT_TOP_NW4END0_5", - "CMT_TOP_IMUX3_10", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_WW4C1_11", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_SW4END3_8", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END3_6", - "CMT_PHASER_C_ICLKDIV_TOIOI", - "CMT_PHASER_OUT_C_OCLK1X_90", - "CMT_TOP_IMUX14_4", - "CMT_TOP_LH6_5", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_FREQ_BB_PREF_IN0", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WW2A1_10", - "CMT_TOP_SW4A2_7", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX39_7", - "CMT_PHY_CONTROL_PHYCTLEMPTY", - "CMT_PHY_CONTROL_IRANKB0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_IMUX0_11", - "CMT_TOP_FAN4_0", - "CMT_TOP_IMUX41_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_WW4A3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_LH6_1", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WL1END2_9", - "CMT_TOP_BYP4_10", - "CMT_TOP_IMUX11_4", - "CMT_TOP_WL1END3_10", - "CMT_TOP_NE4C3_0", - "CMT_TOP_WW4END1_0", - "CMT_TOP_FAN7_5", - "CMT_TOP_SE4C0_9", - "CMT_TOP_BYP0_8", - "CMT_PHASER_C_OCLK_TOIOI", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_IMUX22_2", - "CMT_TOP_FAN4_5", - "CMT_PHASER_REF_RST", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_TOP_EE4B2_6", - "CMT_TOP_SW4A1_3", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW2A2_11", - "CMT_TOP_IMUX19_3", - "CMT_TOP_EE4A1_8", - "CMT_TOP_WW4B1_2", - "CMT_TOP_IMUX9_9", - "CMT_TOP_ER1BEG3_7", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LH9_9", - "CMT_TOP_ICLKDIV_11", - "CMT_PHY_CONTROL_INBURSTPENDING0", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_WW4B3_9", - "CMT_FREQ_BB_PREF_IN3", - "CMT_TOP_NE4C3_10", - "CMT_TOP_FAN5_6", - "CMT_TOP_IMUX30_6", - "CMT_TOP_IMUX23_5", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_FAN0_10", - "CMT_TOP_IMUX40_10", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_TOP_LH2_3", - "CMT_TOP_EE4C3_8", - "CMT_TOP_SW4END2_3", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_TOP_EE2A0_9", - "CMT_TOP_WW4A1_3", - "CMT_TOP_BYP5_10", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_WR1END0_4", - "CMT_TOP_NW2A0_2", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_SE4C3_0", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_SE2A1_5", - "CMT_TOP_FAN0_11", - "CMT_TOP_WL1END3_11", - "CMT_TOP_FAN6_5", - "CMT_TOP_EE4A3_7", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_WR1END0_7", - "CMT_TOP_EE4A2_4", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_WR1END1_0", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_IMUX32_1", - "CMT_TOP_EE4C1_6", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_TOP_EE4C1_1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_TOP_IMUX20_2", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_NW4END1_11", - "CMT_TOP_FAN0_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_WW2END1_11", - "CMT_TOP_FAN0_9", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NW4A0_0", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_PHASER_UP_PHASERREF0", - "CMT_PHY_CONTROL_TESTSELECT0", - "CMT_TOP_BYP1_8", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EE4B2_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_EE4B3_2", - "CMT_TOP_SE4C1_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_IMUX36_3", - "CMT_TOP_SE4C2_3", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_TOP_NW4END0_3", - "CMT_TOP_IMUX10_1", - "CMT_TOP_FAN4_9", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX27_8", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_6", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WW4A2_11", - "CMT_TOP_EE4A3_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_BYP3_6", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE2A1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_BYP2_10", - "CMT_TOP_IMUX27_11", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_TOP_SE2A2_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_SE4C3_6", - "CMT_TOP_NE4C3_3", - "CMT_TOP_WR1END2_9", - "CMT_TOP_CTRL0_6", - "CMT_TOP_FAN2_2", - "CMT_TOP_NW4END1_2", - "CMT_TOP_IMUX18_7", - "CMT_TOP_OCLK_10", - "CMT_PHY_CONTROL_INRANKA1", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LH2_11", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_PHY_CONTROL_PCENABLECALIB0", - "CMT_TOP_NW4A1_0", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_FREQ_PHASER_REFMUX_2", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_TOP_WR1END0_8", - "CMT_PHY_CONTROL_PHYCTLWD24", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4END3_3", - "CMT_TOP_BYP7_9", - "CMT_TOP_SW4END1_6", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_EE4C0_8", - "CMT_TOP_SE4C0_1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_TOP_EE2A0_1", - "CMT_TOP_NW2A1_8", - "CMT_TOP_LH9_4", - "CMT_TOP_SW4END1_1", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LH10_8", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WW2END3_3", - "CMT_TOP_FAN1_6", - "CMT_TOP_CLK1_7", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_TOP_SE4C1_2", - "CMT_TOP_NW2A2_6", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A2_1", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX46_8", - "CMT_TOP_EE4B1_7", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_L_TOP_UPPER_B_CLKINT_2", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_EE4B0_5", - "CMT_TOP_NW2A0_3", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_PHASERTOP_PHYCTLMSTREMPTY", - "CMT_TOP_WW4B2_7", - "CMT_PHY_CONTROL_SYNCIN", - "CMT_TOP_LH10_11", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_IMUX6_2", - "CMT_TOP_NE4C2_6", - "CMT_TOP_WW4END2_9", - "CMT_TOP_IMUX13_10", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_WW2END3_11", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_EE2BEG0_8", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_TOP_LH8_8", - "CMT_TOP_SW2A2_0", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_TOP_SW4A2_2", - "CMT_PHY_CONTROL_READCALIBENABLE", - "CMT_TOP_WW2A1_6", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_PHY_CONTROL_INBURSTPENDING3", - "CMT_TOP_IMUX3_8", - "CMT_PHASER_IN_CA_ICLK", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_SW2A0_11", - "CMT_PHY_CONTROL_OBURSTPENDING2", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_TOP_FAN6_9", - "CMT_TOP_SE4C1_3", - "CMT_TOP_WL1END2_6", - "CMT_TOP_LH11_2", - "CMT_TOP_WW4C0_9", - "CMT_TOP_ICLKDIV_10", - "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX37_4", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_TOP_IMUX46_11", - "CMT_TOP_SE2A0_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_NE4C1_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_EL1BEG1_4", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX0_4", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_IMUX15_3", - "CMT_PHY_CONTROL_PHYCTLWD30", - "CMT_TOP_IMUX39_4", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_ER1BEG2_6", - "CMT_PHASER_IN_D_RCLK3", - "CMT_TOP_IMUX40_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW4A1_5", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_9", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_SE2A2_5", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_SW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LH2_4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_TOP_EL1BEG3_5", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_TOP_WW4END0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_SE2A3_9", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX7_10", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4END3_4", - "CMT_TOP_SE2A3_10", - "CMT_TOP_WW2A3_7", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4END2_6", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_NE2A1_11", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHY_CONTROL_IRANKC0", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_NW2A0_11", - "CMT_TOP_IMUX42_2", - "CMT_TOP_LH8_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_EE4A0_5", - "CMT_TOP_WL1END2_3", - "CMT_TOP_SE2A1_8", - "CMT_PHY_CONTROL_TESTOUTPUT9", - "CMT_TOP_NE4C1_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_NW2A0_6", - "CMT_TOP_WW4A3_8", - "CMT_TOP_SW2A1_3", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_TOP_IMUX40_5", - "CMT_TOP_SE2A1_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_CTRL1_5", - "CMT_TOP_SE4C3_1", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX18_3", - "CMT_TOP_EE2A1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_IMUX16_5", - "CMT_TOP_LH9_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_EE2A1_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_WL1END3_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_IMUX47_3", - "CMT_TOP_NE2A2_7", - "CMT_TOP_WW4B1_5", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_TOP_SE4C3_9", - "CMT_TOP_WR1END1_6", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_EE2A2_0", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_LH9_7", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW2END3_5", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CLK1_9", - "CMT_TOP_IMUX5_11", - "CMT_TOP_WR1END2_6", - "CMT_TOP_CTRL1_2", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_IMUX10_11", - "CMT_TOP_LH6_6", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_EE2A3_1", - "CMT_TOP_IMUX2_0", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE4B3_5", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX38_2", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_FAN4_10", - "CMT_TOP_CLK0_5", - "CMT_TOP_SW4A3_0", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_OCLK_4", - "CMT_TOP_LH12_6", - "CMT_TOP_IMUX4_6", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_WR1END2_3", - "CMT_PHASER_REF_CLKIN", - "CMT_PHASER_REF_CLKOUT_TOHCLK", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX4_11", - "CMT_TOP_NW2A2_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_SE4C1_4", - "CMT_TOP_WW4C0_4", - "CMT_TOP_IMUX6_8", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_WW4A2_4", - "CMT_TOP_IMUX7_1", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SW4A3_9", - "CMT_TOP_IMUX20_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_IMUX35_7", - "CMT_TOP_EE4A3_5", - "CMT_TOP_LH6_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_ICLK_8", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_NW2A3_9", - "CMT_TOP_CLK0_8", - "CMT_TOP_IMUX7_2", - "CMT_TOP_SE2A2_11", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_TOP_FAN4_2", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_R_PHASER_IN_C_WRCLK_FIFO", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_LH12_3", - "CMT_TOP_WW2A1_8", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_TOP_LH8_2", - "CMT_TOP_EE2BEG3_7", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_IMUX23_7", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_IMUX39_0", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX33_8", - "CMT_TOP_SW2A2_2", - "CMT_TOP_LH10_0", - "CMT_R_TOP_UPPER_B_CLKPLL0", - "CMT_TOP_LH6_3", - "CMT_TOP_EE2A0_0", - "CMT_TOP_IMUX12_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_IMUX21_8", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX10_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_FAN2_10", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_LH12_11", - "CMT_PHY_CONTROL_PCENABLECALIB1", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_TOP_IMUX36_10", - "CMT_PHY_CONTROL_IRANKB1", - "CMT_TOP_LH4_1", - "CMT_TOP_NE4C2_11", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_TOP_IMUX3_3", - "CMT_TOP_BYP1_1", - "CMT_TOP_NE4BEG3_5", - "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_SW4END1_5", - "CMT_TOP_FAN7_0", - "CMT_TOP_NW2A3_10", - "CMT_TOP_LH1_7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_WW4A0_4", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW2A1_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_WW4C2_0", - "CMT_TOP_SE2A3_3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_TOP_WL1END2_4", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_IMUX9_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LH5_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_IMUX22_5", - "CMT_TOP_NE4C1_0", - "CMT_TOP_ER1BEG1_10", - "CMT_PHASER_OUT_CA_RST", - "CMT_TOP_IMUX11_1", - "CMT_TOP_NE2A3_8", - "CMT_TOP_EE2A3_0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LH4_6", - "CMT_TOP_WW4A3_9", - "CMT_TOP_FAN7_7", - "CMT_TOP_SE2A1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_PHY_CONTROL_TESTOUTPUT15", - "CMT_TOP_SE4C0_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_LH5_3", - "CMT_PHY_CONTROL_TESTINPUT1", - "CMT_TOP_SW2A3_10", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_TOP_WW4END2_11", - "CMT_TOP_ER1BEG0_4", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_TOP_IMUX25_1", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX31_8", - "CMT_TOP_LH3_2", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4END2_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_BYP1_7", - "CMT_TOP_LH3_10", - "CMT_PHASER_UP_DQS_TO_PHASER_C", - "CMT_TOP_WL1END2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_WL1END3_5", - "CMT_TOP_ICLK_3", - "CMT_TOP_IMUX0_5", - "CMT_TOP_SW4A0_8", - "CMT_TOP_FAN7_6", - "CMT_TOP_IMUX4_0", - "CMT_TOP_BYP1_10", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX19_4", - "CMT_TOP_WW4B1_8", - "CMT_TOP_LH4_0", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_EE4A2_10", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_TOP_IMUX44_7", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_TOP_EE4B2_4", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_PHY_CONTROL_ECALIB0", - "CMT_TOP_EE4C3_7", - "CMT_TOP_IMUX3_2", - "CMT_TOP_WL1END1_5", - "CMT_TOP_IMUX42_9", - "CMT_TOP_SE4C0_2", - "CMT_TOP_WW4A1_9", - "CMT_TOP_LH7_2", - "CMT_TOP_WW4A1_4", - "CMT_TOP_CLK0_3", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_IMUX44_8", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_TOP_SE4C2_0", - "CMT_TOP_IMUX23_2", - "CMT_TOP_WW4END3_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_NW4A0_8", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_TOP_WW4END3_0", - "CMT_TOP_IMUX27_1", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_TOP_IMUX21_2", - "CMT_TOP_SE4BEG0_2", - "CMT_PHY_CONTROL_IRANKC1", - "CMT_TOP_FAN6_10", - "CMT_TOP_LH11_6", - "CMT_TOP_CLK1_10", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_PHASER_C_ICLK_TOIOI", - "CMT_TOP_SW2A3_2", - "CMT_TOP_IMUX44_5", - "CMT_TOP_WW2A0_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX33_10", - "CMT_TOP_EE4B3_10", - "CMT_TOP_IMUX24_5", - "CMT_TOP_WW4C1_7", - "CMT_PHY_CONTROL_INBURSTPENDING1", - "CMT_TOP_WW4C2_8", - "CMT_TOP_EE2A3_8", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE2BEG0_5", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_NW4END0_6", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_TOP_SE2A3_0", - "CMT_TOP_EE4C0_10", - "CMT_TOP_IMUX43_10", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NE2A3_0", - "CMT_TOP_LH12_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_EE4C2_3", - "CMT_TOP_WW2END0_10", - "CMT_TOP_FAN2_7", - "CMT_TOP_WW4A3_0", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_IMUX31_2", - "CMT_TOP_FAN3_7", - "CMT_TOP_IMUX3_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_IMUX8_6", - "CMT_TOP_EE4A1_1", - "CMT_TOP_SW4A0_5", - "CMT_TOP_EE2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_WR1END1_10", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_TOP_EE2A0_6", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX47_6", - "CMT_TOP_SW4A2_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_CTRL1_6", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_EL1BEG1_11", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_TOP_NE2A1_3", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NW4END1_1", - "CMT_TOP_CLK1_5", - "CMT_TOP_WW4C1_0", - "CMT_TOP_EE4B3_3", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_WW4B2_2", - "CMT_TOP_NW4END1_7", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_IMUX9_2", - "CMT_TOP_NW4A0_1", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX10_10", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_WW4B3_6", - "CMT_PHY_CONTROL_TESTINPUT3", - "CMT_TOP_EE2BEG0_9", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_LH1_0", - "CMT_TOP_WW4B1_10", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_OCLK1X_90_7", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_TOP_LH10_5", - "CMT_TOP_IMUX15_0", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4C2_9", - "CMT_TOP_SE2A3_1", - "CMT_TOP_BYP0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_WR1END0_11", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX8_5", - "CMT_TOP_WW4C2_9", - "CMT_TOP_CLK1_6", - "CMT_TOP_FAN6_11", - "CMT_TOP_IMUX23_4", - "CMT_TOP_NW4END3_9", - "CMT_PHY_CONTROL_TESTOUTPUT8", - "CMT_TOP_WW4A2_3", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX17_3", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LH1_8", - "CMT_TOP_LH11_1", - "CMT_TOP_IMUX3_5", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_ER1BEG2_10", - "CMT_PHASER_IN_DB_RCLK", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_PHY_CONTROL_IRANKD0", - "CMT_TOP_SW4A0_10", - "CMT_TOP_FAN4_1", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_SE4C1_6", - "CMT_PHY_CONTROL_TESTINPUT12", - "CMT_TOP_WR1END3_10", - "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", - "CMT_TOP_IMUX15_9", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_IMUX24_3", - "CMT_TOP_BYP0_2", - "CMT_TOP_LH2_10", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_SE4C1_11", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_SE4BEG3_0", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_PHY_CONTROL_AUXOUTPUT1", - "CMT_TOP_SW4A3_2", - "CMT_TOP_EL1BEG1_9", - "CMT_PHY_CONTROL_PHYCTLWD15", - "CMT_TOP_LH8_11", - "CMT_TOP_LH5_11", - "CMT_TOP_FAN4_4", - "CMT_PHY_CONTROL_PHYCTLWD22", - "CMT_TOP_WW4C3_0", - "CMT_TOP_EE4C2_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_SW2A1_11", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX35_3", - "CMT_TOP_NE4C2_4", - "CMT_PHY_CONTROL_PHYCTLWD10", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_IMUX38_9", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_SE4C2_1", - "CMT_TOP_CTRL0_1", - "CMT_TOP_IMUX2_4", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_IMUX17_2", - "CMT_PHASER_IN_C_ICLK", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_TOP_IMUX16_2", - "CMT_TOP_SW4A1_4", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_NE4C1_11", - "CMT_TOP_EE2BEG3_1", - "CMT_PHASERD_DTSBUS0", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_NE2A1_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_IMUX17_5", - "CMT_TOP_ER1BEG0_3", - "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_SW4END1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_TOP_BYP1_4", - "CMT_PHY_CONTROL_PHYCTLWD14", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_NW4END0_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX26_4", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_BYP4_3", - "CMT_TOP_WL1END2_10", - "CMT_TOP_FAN5_2", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4C0_9", - "CMT_TOP_IMUX29_3", - "CMT_TOP_EE4C1_7", - "CMT_TOP_IMUX29_2", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4A2_1", - "CMT_TOP_SE4BEG1_10", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_NW2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_EE4B0_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_SW4END2_11", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_TOP_WW4B2_8", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_TOP_SW4A2_9", - "CMT_TOP_NW4A2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4END0_9", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_NE2A3_7", - "CMT_TOP_FAN5_1", - "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "CMT_TOP_IMUX21_11", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_FAN1_11", - "CMT_TOP_IMUX32_6", - "CMT_TOP_SW4A0_11", - "CMT_TOP_IMUX8_10", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX24_10", - "CMT_TOP_LH3_7", - "CMT_TOP_WR1END1_7", - "CMT_TOP_NW2A0_5", - "CMT_TOP_EE4B0_11", - "CMT_TOP_BYP3_1", - "CMT_TOP_MONITOR_N_0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_TOP_LH9_2", - "CMT_TOP_WW2A2_4", - "CMT_TOP_IMUX41_9", - "CMT_TOP_BYP5_9", - "CMT_TOP_IMUX40_6", - "CMT_PHASERREF_PHASEROUT_C", - "CMT_TOP_WL1END3_3", - "CMT_TOP_NW4A3_0", - "CMT_TOP_LH9_8", - "CMT_TOP_IMUX7_5", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_EE4BEG1_2", - "CMT_PHY_CONTROL_IBURSTPENDING2", - "CMT_TOP_WW4A0_5", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_IMUX12_7", - "CMT_TOP_SW4A0_7", - "CMT_TOP_EE4A0_4", - "CMT_TOP_IMUX7_11", - "CMT_TOP_EE4B3_7", - "CMT_TOP_IMUX4_7", - "CMT_TOP_EE4C2_0", - "CMT_TOP_WW4B1_9", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_SE4C0_0", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_TOP_WW4A1_0", - "CMT_TOP_LH1_2", - "CMT_TOP_SW4END0_8", - "CMT_TOP_FAN3_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_EE4BEG1_9", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_LH11_5", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_WR1END0_2", - "CMT_TOP_IMUX30_5", - "CMT_R_PHASER_OUT_C_RDENABLE_FIFO", - "CMT_TOP_NW4A3_3", - "CMT_TOP_WW4B3_8", - "CMT_TOP_IMUX0_1", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_WW2END2_8", - "CMT_TOP_IMUX38_7", - "CMT_TOP_NW2A1_3", - "CMT_TOP_EE4A2_5", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_TOP_NE2A2_0", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_TOP_WW4C1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_WW4B2_11", - "CMT_TOP_CLK0_7", - "CMT_TOP_EE2A1_3", - "CMT_TOP_SW4END1_2", - "CMT_PHASER_REF_TESTIN5", - "CMT_TOP_IMUX9_3", - "CMT_TOP_FAN7_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LH11_3", - "CMT_TOP_IMUX13_3", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_LH10_10", - "CMT_TOP_SW4A1_10", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NE4C0_6", - "CMT_TOP_BYP0_3", - "CMT_TOP_SE4C2_2", - "CMT_TOP_NW4A1_3", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_TOP_IMUX5_7", - "CMT_TOP_LH10_4", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX8_4", - "CMT_TOP_WL1END0_9", - "CMT_PHASER_UP_PHASERREF_ABOVE1", - "CMT_TOP_SW2A1_6", - "CMT_TOP_IMUX26_3", - "CMT_TOP_NW2A2_0", - "CMT_TOP_WW4END0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_OCLKDIV_8", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_PHY_CONTROL_PHYCTLWD28", - "CMT_TOP_WW2END1_6", - "CMT_PHY_CONTROL_TESTOUTPUT10", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WW4C1_1", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_WW2A1_5", - "CMT_TOP_CTRL1_1", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_BYP7_3", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_PHASER_IN_C_ICLKDIV", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_WR1END0_10", - "CMT_TOP_IMUX45_0", - "CMT_TOP_WL1END1_7", - "CMT_PHASER_REF_TMUXOUT", - "CMT_TOP_LH2_7", - "CMT_TOP_WW4END1_2", - "CMT_TOP_LH7_7", - "CMT_TOP_IMUX26_8", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_SE4C2_10", - "CMT_FREQ_BB_PREF_IN1", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_EE4A2_11", - "CMT_TOP_NW4END1_4", - "CMT_PHASER_UP_PHASERREF_BELOW0", - "CMT_TOP_IMUX25_11", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_NW2A1_6", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_PHY_CONTROL_ECALIB1", - "CMT_TOP_BYP2_4", - "CMT_TOP_NW4END2_3", - "CMT_TOP_WL1END0_11", - "CMT_TOP_IMUX18_10", - "CMT_TOP_EE4C1_8", - "CMT_PHY_CONTROL_PHYCTLWD19", - "CMT_TOP_WW2END1_4", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_WW2END3_9", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE4C2_4", - "CMT_PHASER_IN_CA_RST", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_IMUX1_9", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_NW4A1_4", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_SW2A0_3", - "CMT_TOP_IMUX22_6", - "CMT_TOP_EE4C2_2", - "CMT_TOP_IMUX5_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_EE4C3_1", - "CMT_TOP_NE2A2_4", - "CMT_TOP_LH9_6", - "CMT_TOP_IMUX28_5", - "CMT_TOP_EE2A2_9", - "CMT_TOP_NW4A3_4", - "CMT_TOP_SW2A2_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX11_9", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LH2_9", - "CMT_TOP_WW2A2_2", - "CMT_TOP_IMUX3_11", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_IMUX45_11", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX45_5", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_WW4C3_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX24_6", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_IMUX35_5", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_EE2A0_7", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_TOP_WW4B2_4", - "CMT_TOP_FAN2_8", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_TOP_SW2A1_0", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_WL1END0_5", - "CMT_TOP_CLK0_9", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX29_4", - "CMT_TOP_NE2A0_11", - "CMT_TOP_FAN2_3", - "CMT_TOP_NE4C2_1", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_IMUX31_5", - "CMT_TOP_WR1END1_5", - "CMT_TOP_IMUX8_7", - "CMT_TOP_CTRL1_7", - "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", - "CMT_TOP_IMUX27_9", - "CMT_TOP_EL1BEG1_3", - "CMT_PHY_CONTROL_IRANKA0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4C3_8", - "CMT_TOP_BYP6_6", - "CMT_PHY_CONTROL_TESTINPUT5", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_TOP_EE4C1_4", - "CMT_TOP_IMUX46_6", - "CMT_TOP_NW4A3_11", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_PHASER_UP_BUFMRCE_CE0", - "CMT_TOP_NW4END0_7", - "CMT_TOP_CLK1_11", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_BYP3_8", - "CMT_TOP_IMUX16_8", - "CMT_TOP_SW4END3_7", - "CMT_TOP_WW2A1_4", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_TOP_WW2END3_0", - "CMT_TOP_SE2A0_5", - "CMT_TOP_WW2A1_0", - "CMT_TOP_NW4A2_5", - "CMT_TOP_EE2BEG1_8", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_PHY_CONTROL_TESTOUTPUT0", - "CMT_PHY_CONTROL_PHYCTLWD16", - "CMT_TOP_WW4END2_1", - "CMT_TOP_NW2A2_5", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_TOP_MONITOR_N_9", - "CMT_PHASER_OUT_DB_RST", - "CMT_TOP_IMUX18_9", - "CMT_TOP_SE2A0_4", - "CMT_PHY_CONTROL_PHYCTLWD18", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_IMUX6_5", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_EE4A2_8", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX7_6", - "CMT_TOP_CTRL0_9", - "CMT_TOP_EE2BEG3_9", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_PHY_CONTROL_PHYCTLWD4", - "CMT_TOP_IMUX6_11", - "CMT_TOP_WW4B3_2", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_EE4C0_4", - "CMT_TOP_BYP2_1", - "CMT_TOP_IMUX36_8", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_NW2A3_5", - "CMT_TOP_IMUX27_3", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_TOP_LH7_11", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_WW4C2_2", - "CMT_TOP_BYP1_6", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_SE2A0_10", - "CMT_TOP_IMUX1_3", - "CMT_PHY_CONTROL_TESTINPUT11", - "CMT_PHY_CONTROL_PHYCTLWD5", - "CMT_TOP_IMUX1_4", - "CMT_TOP_NW4END0_10", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_IMUX8_8", - "CMT_TOP_EL1BEG0_6", - "CMT_PHASERREF_PHASERIN_C", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX2_9", - "CMT_TOP_SE2A2_1", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG1_0", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_NE4C2_10", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX3_9", - "CMT_TOP_EE4A2_9", - "CMT_TOP_WW2A3_2", - "CMT_TOP_BYP5_0", - "CMT_TOP_NE4C2_8", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX17_9", - "PLL_CLK_FREQBB_REBUFOUT2", - "CMT_PHY_CONTROL_AUXOUTPUT0", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_IMUX0_8", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_FREQ_PHASER_REFMUX_0", - "CMT_TOP_NE4C3_5", - "CMT_TOP_WR1END3_9", - "CMT_TOP_EE4C3_9", - "CMT_TOP_IMUX35_8", - "CMT_TOP_BYP3_5", - "CMT_TOP_IMUX32_8", - "CMT_PHY_CONTROL_INRANKC1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_NW4A0_11", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_TOP_IMUX34_9", - "CMT_R_TOP_UPPER_B_CLKPLL1", - "CMT_TOP_SE4C3_5", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX47_11", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_FAN6_4", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_TOP_IMUX21_7", - "CMT_TOP_WW2END0_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LH5_2", - "CMT_TOP_IMUX17_4", - "CMT_TOP_SW2A1_8", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_NE4C1_9", - "CMT_TOP_LH3_8", - "CMT_TOP_BYP0_9", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_TOP_WW2END0_4", - "CMT_TOP_EE2A1_7", - "CMT_TOP_NW2A2_11", - "CMT_TOP_WW2END3_6", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_WW4B0_11", - "CMT_TOP_EE2BEG1_2", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_TOP_SW2A3_9", - "CMT_PHY_CONTROL_PHYCTLWD0", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_TOP_IMUX32_9", - "CMT_TOP_EE2A0_2", - "CMT_TOP_SW4END2_6", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_IMUX47_1", - "CMT_TOP_WW2A2_1", - "CMT_TOP_NW2A1_7", - "CMT_TOP_IMUX14_0", - "CMT_TOP_LH7_4", - "CMT_TOP_EE4C0_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX45_3", - "CMT_TOP_SW4END3_11", - "CMT_TOP_WW4C1_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX33_7", - "CMT_PHY_CONTROL_INRANKC0", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_FAN4_11", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_TOP_LH5_4", - "CMT_TOP_CLK0_4", - "CMT_TOP_OCLK_9", - "CMT_TOP_IMUX22_8", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_PHASERREF_PHASERIN_D", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_WW4A3_4", - "CMT_TOP_NW4A1_6", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SW4A3_4", - "CMT_TOP_NE2A0_10", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_LH8_7", - "CMT_TOP_IMUX32_5", - "CMT_TOP_SW2A1_5", - "CMT_TOP_WR1END0_1", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_LOGIC_OUTS_L_B13_10" - ], - "sites": [ - { - "prefix": "PHASER_REF", - "y_coord": 0, - "type": "PHASER_REF", - "site_pins": { - "TESTIN1": "CMT_PHASER_REF_TESTIN1", - "LOCKED": "CMT_PHASER_REF_LOCKED", - "CLKOUT": "CMT_PHASER_REF_CLKOUT", - "TESTIN5": "CMT_PHASER_REF_TESTIN5", - "TESTIN0": "CMT_PHASER_REF_TESTIN0", - "TESTOUT7": "CMT_PHASER_REF_TESTOUT7", - "TESTOUT6": "CMT_PHASER_REF_TESTOUT6", - "TMUXOUT": "CMT_PHASER_REF_TMUXOUT", - "TESTOUT2": "CMT_PHASER_REF_TESTOUT2", - "TESTOUT3": "CMT_PHASER_REF_TESTOUT3", - "TESTOUT4": "CMT_PHASER_REF_TESTOUT4", - "TESTIN3": "CMT_PHASER_REF_TESTIN3", - "TESTOUT1": "CMT_PHASER_REF_TESTOUT1", - "TESTIN6": "CMT_PHASER_REF_TESTIN6", - "TESTOUT0": "CMT_PHASER_REF_TESTOUT0", - "PWRDWN": "CMT_PHASER_REF_PWRDWN", - "TESTIN4": "CMT_PHASER_REF_TESTIN4", - "TESTOUT5": "CMT_PHASER_REF_TESTOUT5", - "CLKIN": "CMT_PHASER_REF_CLKIN", - "TESTIN2": "CMT_PHASER_REF_TESTIN2", - "RST": "CMT_PHASER_REF_RST", - "TESTIN7": "CMT_PHASER_REF_TESTIN7" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "PHY_CONTROL", - "y_coord": 0, - "type": "PHY_CONTROL", - "site_pins": { - "OUTBURSTPENDING3": "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "PHYCTLWD27": "CMT_PHY_CONTROL_PHYCTLWD27", - "INRANKD0": "CMT_PHY_CONTROL_INRANKD0", - "PHYCTLWD8": "CMT_PHY_CONTROL_PHYCTLWD8", - "PHYCTLWD19": "CMT_PHY_CONTROL_PHYCTLWD19", - "TESTINPUT2": "CMT_PHY_CONTROL_TESTINPUT2", - "PHYCTLWD13": "CMT_PHY_CONTROL_PHYCTLWD13", - "PHYCTLWD0": "CMT_PHY_CONTROL_PHYCTLWD0", - "PHYCTLWD1": "CMT_PHY_CONTROL_PHYCTLWD1", - "TESTSELECT0": "CMT_PHY_CONTROL_TESTSELECT0", - "PLLLOCK": "CMT_PHY_CONTROL_PLLLOCK", - "TESTOUTPUT7": "CMT_PHY_CONTROL_TESTOUTPUT7", - "PHYCTLWD11": "CMT_PHY_CONTROL_PHYCTLWD11", - "TESTINPUT3": "CMT_PHY_CONTROL_TESTINPUT3", - "PHYCTLWD2": "CMT_PHY_CONTROL_PHYCTLWD2", - "INRANKB1": "CMT_PHY_CONTROL_INRANKB1", - "PHYCTLREADY": "CMT_PHY_CONTROL_PHYCTLREADY", - "PHYCTLWD22": "CMT_PHY_CONTROL_PHYCTLWD22", - "AUXOUTPUT1": "CMT_PHY_CONTROL_AUXOUTPUT1", - "PCENABLECALIB0": "CMT_PHY_CONTROL_PCENABLECALIB0", - "TESTOUTPUT11": "CMT_PHY_CONTROL_TESTOUTPUT11", - "PHYCTLWD6": "CMT_PHY_CONTROL_PHYCTLWD6", - "OUTBURSTPENDING0": "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "REFDLLLOCK": "CMT_PHY_CONTROL_REFDLLLOCK", - "OUTBURSTPENDING1": "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "PHYCLK": "CMT_PHY_CONTROL_PHYCLK", - "TESTINPUT8": "CMT_PHY_CONTROL_TESTINPUT8", - "TESTOUTPUT5": "CMT_PHY_CONTROL_TESTOUTPUT5", - "TESTINPUT13": "CMT_PHY_CONTROL_TESTINPUT13", - "PHYCTLWD25": "CMT_PHY_CONTROL_PHYCTLWD25", - "INRANKD1": "CMT_PHY_CONTROL_INRANKD1", - "PHYCTLWD28": "CMT_PHY_CONTROL_PHYCTLWD28", - "PHYCTLWD23": "CMT_PHY_CONTROL_PHYCTLWD23", - "PHYCTLWD31": "CMT_PHY_CONTROL_PHYCTLWD31", - "INRANKC0": "CMT_PHY_CONTROL_INRANKC0", - "AUXOUTPUT3": "CMT_PHY_CONTROL_AUXOUTPUT3", - "PHYCTLWD17": "CMT_PHY_CONTROL_PHYCTLWD17", - "PHYCTLMSTREMPTY": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "TESTINPUT6": "CMT_PHY_CONTROL_TESTINPUT6", - "AUXOUTPUT2": "CMT_PHY_CONTROL_AUXOUTPUT2", - "TESTINPUT5": "CMT_PHY_CONTROL_TESTINPUT5", - "INBURSTPENDING0": "CMT_PHY_CONTROL_INBURSTPENDING0", - "TESTINPUT10": "CMT_PHY_CONTROL_TESTINPUT10", - "INRANKA1": "CMT_PHY_CONTROL_INRANKA1", - "PHYCTLWD15": "CMT_PHY_CONTROL_PHYCTLWD15", - "TESTINPUT1": "CMT_PHY_CONTROL_TESTINPUT1", - "TESTOUTPUT8": "CMT_PHY_CONTROL_TESTOUTPUT8", - "INRANKC1": "CMT_PHY_CONTROL_INRANKC1", - "WRITECALIBENABLE": "CMT_PHY_CONTROL_WRITECALIBENABLE", - "INBURSTPENDING3": "CMT_PHY_CONTROL_INBURSTPENDING3", - "TESTOUTPUT1": "CMT_PHY_CONTROL_TESTOUTPUT1", - "PHYCTLWD16": "CMT_PHY_CONTROL_PHYCTLWD16", - "PHYCTLWD5": "CMT_PHY_CONTROL_PHYCTLWD5", - "PHYCTLWD3": "CMT_PHY_CONTROL_PHYCTLWD3", - "PHYCTLWD7": "CMT_PHY_CONTROL_PHYCTLWD7", - "TESTINPUT4": "CMT_PHY_CONTROL_TESTINPUT4", - "PCENABLECALIB1": "CMT_PHY_CONTROL_PCENABLECALIB1", - "PHYCTLWD18": "CMT_PHY_CONTROL_PHYCTLWD18", - "PHYCTLFULL": "CMT_PHY_CONTROL_PHYCTLFULL", - "PHYCTLWD12": "CMT_PHY_CONTROL_PHYCTLWD12", - "MEMREFCLK": "CMT_PHY_CONTROL_MEMREFCLK", - "TESTOUTPUT0": "CMT_PHY_CONTROL_TESTOUTPUT0", - "TESTOUTPUT3": "CMT_PHY_CONTROL_TESTOUTPUT3", - "PHYCTLWD26": "CMT_PHY_CONTROL_PHYCTLWD26", - "PHYCTLEMPTY": "CMT_PHY_CONTROL_PHYCTLEMPTY", - "SYNCIN": "CMT_PHY_CONTROL_SYNCIN", - "TESTSELECT2": "CMT_PHY_CONTROL_TESTSELECT2", - "TESTINPUT11": "CMT_PHY_CONTROL_TESTINPUT11", - "AUXOUTPUT0": "CMT_PHY_CONTROL_AUXOUTPUT0", - "TESTOUTPUT4": "CMT_PHY_CONTROL_TESTOUTPUT4", - "PHYCTLWD29": "CMT_PHY_CONTROL_PHYCTLWD29", - "TESTOUTPUT10": "CMT_PHY_CONTROL_TESTOUTPUT10", - "INRANKB0": "CMT_PHY_CONTROL_INRANKB0", - "TESTINPUT14": "CMT_PHY_CONTROL_TESTINPUT14", - "PHYCTLALMOSTFULL": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "TESTINPUT7": "CMT_PHY_CONTROL_TESTINPUT7", - "OUTBURSTPENDING2": "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "PHYCTLWD4": "CMT_PHY_CONTROL_PHYCTLWD4", - "PHYCTLWD9": "CMT_PHY_CONTROL_PHYCTLWD9", - "TESTINPUT12": "CMT_PHY_CONTROL_TESTINPUT12", - "TESTOUTPUT9": "CMT_PHY_CONTROL_TESTOUTPUT9", - "INRANKA0": "CMT_PHY_CONTROL_INRANKA0", - "TESTINPUT9": "CMT_PHY_CONTROL_TESTINPUT9", - "TESTINPUT0": "CMT_PHY_CONTROL_TESTINPUT0", - "TESTOUTPUT15": "CMT_PHY_CONTROL_TESTOUTPUT15", - "SCANENABLEN": "CMT_PHY_CONTROL_SCANENABLEN", - "PHYCTLWD20": "CMT_PHY_CONTROL_PHYCTLWD20", - "PHYCTLWD21": "CMT_PHY_CONTROL_PHYCTLWD21", - "TESTINPUT15": "CMT_PHY_CONTROL_TESTINPUT15", - "TESTOUTPUT12": "CMT_PHY_CONTROL_TESTOUTPUT12", - "PHYCTLWD30": "CMT_PHY_CONTROL_PHYCTLWD30", - "INBURSTPENDING2": "CMT_PHY_CONTROL_INBURSTPENDING2", - "PHYCTLWD10": "CMT_PHY_CONTROL_PHYCTLWD10", - "READCALIBENABLE": "CMT_PHY_CONTROL_READCALIBENABLE", - "PHYCTLWRENABLE": "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "TESTOUTPUT14": "CMT_PHY_CONTROL_TESTOUTPUT14", - "PHYCTLWD24": "CMT_PHY_CONTROL_PHYCTLWD24", - "TESTOUTPUT2": "CMT_PHY_CONTROL_TESTOUTPUT2", - "TESTOUTPUT13": "CMT_PHY_CONTROL_TESTOUTPUT13", - "TESTOUTPUT6": "CMT_PHY_CONTROL_TESTOUTPUT6", - "TESTSELECT1": "CMT_PHY_CONTROL_TESTSELECT1", - "PHYCTLWD14": "CMT_PHY_CONTROL_PHYCTLWD14", - "INBURSTPENDING1": "CMT_PHY_CONTROL_INBURSTPENDING1", - "RESET": "CMT_PHY_CONTROL_RESET" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "PHASER_OUT_PHY", - "y_coord": 5, - "type": "PHASER_OUT_PHY", - "site_pins": { - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "RST": "CMT_PHASER_OUT_CA_RST", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y5" - }, - { - "prefix": "PHASER_IN_PHY", - "y_coord": 5, - "type": "PHASER_IN_PHY", - "site_pins": { - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", - "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", - "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", - "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", - "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", - "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", - "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", - "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "ICLK": "CMT_PHASER_IN_CA_ICLK", - "RCLK": "CMT_PHASER_IN_CA_RCLK", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", - "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", - "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", - "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", - "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", - "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", - "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", - "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", - "SCANIN": "CMT_PHASER_IN_CA_SCANIN", - "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", - "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", - "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", - "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", - "STG1READ": "CMT_PHASER_IN_CA_STG1READ", - "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", - "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", - "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", - "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", - "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", - "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", - "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", - "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", - "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", - "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", - "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", - "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", - "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", - "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", - "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", - "SCANENB": "CMT_PHASER_IN_CA_SCANENB", - "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", - "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", - "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", - "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", - "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", - "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", - "RST": "CMT_PHASER_IN_CA_RST", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", - "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", - "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", - "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", - "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", - "FINEINC": "CMT_PHASER_IN_CA_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", - "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", - "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", - "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", - "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", - "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", - "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", - "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", - "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", - "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", - "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y5" - }, - { - "prefix": "PHASER_OUT_PHY", - "y_coord": 6, - "type": "PHASER_OUT_PHY", - "site_pins": { - "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", - "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", - "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", - "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", - "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", - "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", - "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", - "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", - "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", - "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", - "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", - "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", - "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", - "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", - "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", - "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", - "OCLK": "CMT_PHASER_OUT_DB_OCLK", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", - "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", - "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", - "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", - "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", - "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", - "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", - "RST": "CMT_PHASER_OUT_DB_RST", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", - "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", - "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", - "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", - "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", - "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", - "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", - "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", - "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", - "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", - "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", - "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", - "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", - "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y6" - }, - { - "prefix": "PHASER_IN_PHY", - "y_coord": 6, - "type": "PHASER_IN_PHY", - "site_pins": { - "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", - "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", - "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", - "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", - "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", - "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", - "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", - "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", - "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "ICLK": "CMT_PHASER_IN_DB_ICLK", - "RCLK": "CMT_PHASER_IN_DB_RCLK", - "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", - "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", - "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", - "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", - "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", - "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", - "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", - "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", - "SCANIN": "CMT_PHASER_IN_DB_SCANIN", - "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", - "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", - "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", - "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", - "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", - "STG1READ": "CMT_PHASER_IN_DB_STG1READ", - "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", - "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", - "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", - "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", - "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", - "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", - "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", - "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", - "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", - "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", - "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", - "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", - "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", - "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", - "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", - "SCANENB": "CMT_PHASER_IN_DB_SCANENB", - "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", - "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", - "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", - "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", - "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", - "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", - "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", - "RST": "CMT_PHASER_IN_DB_RST", - "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", - "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", - "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", - "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", - "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", - "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", - "FINEINC": "CMT_PHASER_IN_DB_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", - "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", - "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", - "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", - "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", - "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", - "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", - "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", - "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", - "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", - "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", - "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y6" - } - ], "pips": { - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT1->CMT_TOP_LOGIC_OUTS_L_B21_9": { + "CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY->>CMT_PHASER_TOP_SYNC_BB": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_9", + "src_wire": "CMT_PHASERTOP_PHYCTLEMPTY", "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_BB_PREF_IN1", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQBB_REBUFOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX17_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B6_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_D_OCLK1X_90": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_D_OCLK1X_90", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX28_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX39_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_C_ICLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_C_ICLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHY_CONTROL_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_LOCKED->CMT_TOP_LOGIC_OUTS_L_B14_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_REF_LOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B21_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX37_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IRANKD1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKC0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKC0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RDENABLE->CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING0->CMT_PHY_CONTROL_IBURSTPENDING0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B3_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX9_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASEROUT_D->CMT_PHASER_OUT_DB_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKA1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKA1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA0->CMT_PHY_CONTROL_IRANKA0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKA0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKA0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING1->CMT_PHY_CONTROL_IBURSTPENDING1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX4_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASERIN_C->CMT_PHASER_IN_CA_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_PHASERIN_C", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX8_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B15_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX18_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_R_PHASER_IN_D_WRCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX16_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_R_PHASER_OUT_C_RDCLK_FIFO": { - "can_invert": "0", - "dst_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_WRENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERD_CTSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX12_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING3->CMT_PHY_CONTROL_IBURSTPENDING3": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO->CMT_PHASER_OUT_D_OCLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_D_OCLKDIV", - "is_directional": "1", - "src_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_D->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_D", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_C_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX17_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_C_RCLK2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_C_RCLK2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_RCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHY_CONTROL_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASERIN_D->CMT_PHASER_IN_DB_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_PHASERIN_D", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS0->CMT_PHASERD_DTSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERD_DTSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IRANKD0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_C_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_C_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX41_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX11_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_TOP_SYNC_BB->>CMT_PHASERTOP_PHYCTLMSTREMPTY": { - "can_invert": "0", - "dst_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", - "is_directional": "1", - "src_wire": "CMT_PHASER_TOP_SYNC_BB", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS0->CMT_PHASERD_CTSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERD_CTSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_C_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_BB_PREF_IN0", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQBB_REBUFOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX8_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASEROUT_C->CMT_PHASER_OUT_CA_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B16_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_CLK1_0->>CMT_L_TOP_UPPER_B_CLKINT_3": { - "can_invert": "0", - "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_3", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK1_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX41_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDIV->CMT_R_PHASER_OUT_D_RDCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX4_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT->CMT_PHASER_REF_TMUXOUT_TOHCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_REF_TMUXOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IRANKC1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_D_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_D_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKB1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_0->>CMT_L_TOP_UPPER_B_CLKINT_2": { - "can_invert": "0", - "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_2", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS0->CMT_PHASERD_DQSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERD_DQSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", - "is_pseudo": "1" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": { - "can_invert": "0", - "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX4_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX9_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", - "is_pseudo": "1" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT2->CMT_TOP_LOGIC_OUTS_L_B17_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_10", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_C_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_D_ICLKDIV", - "is_directional": "1", - "src_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_RESET", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX11_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY->CMT_PHY_CONTROL_PHYCTLMSTREMPTY": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "is_directional": "1", - "src_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_BB_PREF_IN2", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQBB_REBUFOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_D_ICLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX11_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_REF_CLKIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_CLKIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_R_PHASER_OUT_C_RDENABLE_FIFO": { - "can_invert": "0", - "dst_wire": "CMT_R_PHASER_OUT_C_RDENABLE_FIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>CMT_FREQ_PHASER_REFMUX_0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX41_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PLLLOCK", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_TOP_SYNC_BB" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", - "is_directional": "1", "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_4", "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6" }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": { + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_D_RCLK3", + "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_RCLK", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY" }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": { + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2", + "src_wire": "CMT_TOP_IMUX0_3", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND" }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", + "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY" }, - "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO->CMT_PHASER_OUT_C_OCLKDIV": { + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHY_CONTROL_MEMREFCLK": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", "is_directional": "1", - "src_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_MEMREFCLK" }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_R_PHASER_IN_C_WRCLK_FIFO": { + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": { "can_invert": "0", - "dst_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO", + "src_wire": "CMT_TOP_IMUX14_11", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKD0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKD0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX22_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERD_DQSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_BB_PREF_IN3", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQBB_REBUFOUT3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_10->CMT_PHY_CONTROL_PHYCTLWD18": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX15_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT0->CMT_TOP_LOGIC_OUTS_L_B3_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_9", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_C->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_C", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKD1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKD1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK1X_90_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK90_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX18_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY->>CMT_PHASER_TOP_SYNC_BB": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_TOP_SYNC_BB", - "is_directional": "1", - "src_wire": "CMT_PHASERTOP_PHYCTLEMPTY", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>CMT_FREQ_PHASER_REFMUX_1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKB0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18" }, "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_1": { "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_directional": "1", "src_wire": "CMT_FREQ_BB_PREF_IN3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_ECALIB0", "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": { + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_2": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2" }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", + "src_wire": "CMT_TOP_IMUX14_1", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX9_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS1->CMT_PHASERD_DTSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERD_DTSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_8", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_0->CMT_PHASER_REF_PWRDWN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_PWRDWN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO->CMT_PHASER_IN_C_ICLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_C_ICLKDIV", - "is_directional": "1", - "src_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX16_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX17_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT->CMT_PHASER_REF_CLKOUT_TOHCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_CLKOUT_TOHCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_REF_CLKOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IRANKC0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "is_directional": "1", "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT3->CMT_TOP_LOGIC_OUTS_L_B17_11": { + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_11", + "src_wire": "CMT_TOP_IMUX30_3", "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5" }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": { + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7" }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": { + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK1_0->>CMT_L_TOP_UPPER_B_CLKINT_3": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12", + "src_wire": "CMT_TOP_CLK1_0", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_3" }, - "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": { + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKC1", + "src_wire": "CMT_TOP_IMUX23_3", "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKC1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN" }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": { + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3" }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": { + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO", + "src_wire": "CMT_TOP_IMUX23_7", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_WRENABLE", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1" }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "src_wire": "CMT_TOP_IMUX0_0", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0" }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7" }, - "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": { + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", - "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": { + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_D": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FINEINC", + "src_wire": "CMT_PHASER_UP_PHASERREF0", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYNCIN" + }, + "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQBB_REBUFOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_1": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING3->CMT_PHY_CONTROL_IBURSTPENDING3": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING3" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX8_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING2->CMT_PHY_CONTROL_IBURSTPENDING2": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", - "is_directional": "1", "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING2" }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": { + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_1": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1" }, - "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": { + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_8": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_2", - "is_directional": "1", "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX18_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASERIN_C->CMT_PHASER_IN_CA_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING0->CMT_PHY_CONTROL_IBURSTPENDING0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_C_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLK_TOIOI" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX17_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT1->CMT_TOP_LOGIC_OUTS_L_B21_9": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_9" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_C_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_C_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_ICLK_TOIOI" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_EDGEADV" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", - "is_directional": "1", "src_wire": "CMT_TOP_CLK0_5", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_LOCKED->CMT_TOP_LOGIC_OUTS_L_B14_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_REF_LOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX37_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B21_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_3" + }, + "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO->CMT_PHASER_OUT_D_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLKDIV" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX20_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B16_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_1": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY->CMT_PHY_CONTROL_PHYCTLMSTREMPTY": { + "can_invert": "0", + "src_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_R_PHASER_IN_C_WRCLK_FIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEINC" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDIV->CMT_R_PHASER_OUT_D_RDCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX4_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_WRENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS0->CMT_PHASERD_DQSBUS0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DQSBUS0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_ECALIB0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKC0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKC0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IRANKD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RDENABLE->CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKB0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>CMT_FREQ_PHASER_REFMUX_1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B3_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX28_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX12_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT->CMT_PHASER_REF_TMUXOUT_TOHCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_REF_TMUXOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_TMUXOUT_TOHCLK" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B6_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PLLLOCK" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_0": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKB1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6" + }, + "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": { + "can_invert": "0", + "src_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_ICLKDIV" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEINC" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQBB_REBUFOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX39_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RST" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX11_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_RESET" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK90_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_7" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASERIN_D->CMT_PHASER_IN_DB_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT3->CMT_TOP_LOGIC_OUTS_L_B17_11": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_11" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS1->CMT_PHASERD_DTSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DTSBUS1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO->CMT_PHASER_OUT_C_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_REF_CLKIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_CLKIN" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_RST" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_ECALIB1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT2->CMT_TOP_LOGIC_OUTS_L_B17_10": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_10" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEINC" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKD0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX16_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B15_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_3" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX8_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_RCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_RCLK3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_0->CMT_PHASER_REF_PWRDWN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_PWRDWN" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYSCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX22_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_DB_RCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKA1" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_0": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_ICLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_R_PHASER_IN_D_WRCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DQSBUS1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IRANKC1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX20_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_RST" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_R_PHASER_OUT_C_RDENABLE_FIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_OUT_C_RDENABLE_FIFO" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX41_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX4_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1" + }, + "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQBB_REBUFOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_TOP_SYNC_BB->>CMT_PHASERTOP_PHYCTLMSTREMPTY": { + "can_invert": "0", + "src_wire": "CMT_PHASER_TOP_SYNC_BB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYSCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT->CMT_PHASER_REF_CLKOUT_TOHCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_REF_CLKOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_CLKOUT_TOHCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_R_PHASER_OUT_C_RDCLK_FIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IRANKC0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_1": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKC1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKC1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT0->CMT_TOP_LOGIC_OUTS_L_B3_9": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_9" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_C_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IRANKD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0" + }, + "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO->CMT_PHASER_IN_C_ICLKDIV": { + "can_invert": "0", + "src_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_ICLKDIV" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_D_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASEROUT_C->CMT_PHASER_OUT_CA_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX41_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_EDGEADV" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS0->CMT_PHASERD_DTSBUS0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DTSBUS0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_CA_RCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX4_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_D->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_D", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA0->CMT_PHY_CONTROL_IRANKA0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKA0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS0->CMT_PHASERD_CTSBUS0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_CTSBUS0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_0": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_0->>CMT_L_TOP_UPPER_B_CLKINT_2": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_C->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_C", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX18_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX9_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_CTSBUS1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX11_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX17_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0" + }, + "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQBB_REBUFOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>CMT_FREQ_PHASER_REFMUX_0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_C_ICLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_ICLK" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING1->CMT_PHY_CONTROL_IBURSTPENDING1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_WRENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_0": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKD1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX9_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYNCIN" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX9_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_D_OCLK1X_90": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLK1X_90" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_C_RCLK2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_RCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_RCLK2" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1" + }, + "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASEROUT_D->CMT_PHASER_OUT_DB_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_RST" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX20_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEINC" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0" + }, + "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHY_CONTROL_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_SYNCIN" + }, + "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX41_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3" + }, + "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX11_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RST" + }, + "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7" } }, - "tile_type": "CMT_TOP_L_UPPER_B" + "wires": [ + "CMT_PHASER_IN_DB_TESTIN3", + "CMT_TOP_NW4A2_6", + "CMT_TOP_WW2END3_2", + "CMT_TOP_BYP1_3", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_WW4A3_11", + "CMT_PHASER_IN_DB_STG1REGR4", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_LH7_10", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_NW4A1_2", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_EL1BEG0_11", + "CMT_PHASER_OUT_DB_PHASEREFCLK", + "CMT_TOP_WW2A1_6", + "CMT_TOP_WW4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_PHASER_IN_CA_TESTIN3", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_PHASER_OUT_DB_TESTIN4", + "CMT_TOP_WW4END1_8", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WW4END2_8", + "CMT_TOP_IMUX7_3", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_WW4B3_6", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_PHY_CONTROL_PHYCTLWD21", + "CMT_TOP_BYP6_2", + "CMT_TOP_LH3_8", + "CMT_TOP_WW4B0_5", + "CMT_TOP_LH12_10", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX41_8", + "CMT_PHASER_IN_DB_TESTOUT3", + "CMT_TOP_IMUX36_7", + "CMT_TOP_NE4C0_9", + "CMT_TOP_IMUX32_8", + "CMT_TOP_IMUX17_10", + "CMT_TOP_IMUX7_9", + "CMT_PHASER_IN_CA_TESTOUT2", + "CMT_TOP_WW2END3_5", + "CMT_TOP_SW4END0_1", + "CMT_TOP_IMUX12_8", + "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "CMT_TOP_NW4END3_1", + "CMT_PHY_CONTROL_PHYCTLWD23", + "CMT_PHASER_OUT_CA_TESTIN3", + "CMT_TOP_NE2A3_0", + "CMT_TOP_CLK1_3", + "CMT_TOP_WR1END0_8", + "CMT_TOP_FAN2_8", + "CMT_TOP_IMUX29_10", + "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_PHASER_IN_CA_STG1REGR4", + "CMT_PHASER_OUT_CA_DQSBUS0", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_EE4B3_0", + "CMT_PHASER_IN_DB_TESTIN12", + "CMT_TOP_BYP4_1", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_OCLK_7", + "CMT_R_PHASER_OUT_C_RDENABLE_FIFO", + "CMT_TOP_WW4C0_11", + "CMT_TOP_WW4C0_3", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_IMUX1_1", + "CMT_TOP_EE2A0_9", + "CMT_TOP_LH2_9", + "CMT_TOP_SE4C1_10", + "CMT_TOP_NW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_SE4C2_9", + "CMT_TOP_IMUX35_6", + "CMT_TOP_EE4A0_6", + "CMT_TOP_SE4C0_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_WL1END1_9", + "CMT_TOP_EE4C0_9", + "CMT_TOP_WW2END1_3", + "CMT_TOP_IMUX3_4", + "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "CMT_TOP_NE2A1_0", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_IMUX39_7", + "CMT_TOP_IMUX14_2", + "CMT_PHASER_IN_DB_TESTIN10", + "CMT_TOP_WW4C3_2", + "CMT_TOP_EE4B3_8", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW4END1_5", + "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "CMT_R_TOP_UPPER_B_CLKPLL7", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_EE4A2_7", + "CMT_TOP_EE2A0_1", + "CMT_TOP_WW4B0_6", + "CMT_TOP_IMUX12_9", + "CMT_TOP_WW4A0_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_WW2A1_11", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_PHASER_UP_PHASERREF0", + "CMT_TOP_IMUX1_3", + "CMT_TOP_SE4C1_9", + "CMT_TOP_WW2A0_9", + "CMT_TOP_WW4C1_11", + "CMT_TOP_BYP7_3", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "CMT_TOP_EE4A0_9", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX30_7", + "CMT_TOP_ICLK_4", + "CMT_TOP_BYP5_9", + "CMT_PHY_CONTROL_TESTOUTPUT14", + "CMT_TOP_OCLKDIV_8", + "CMT_PHASER_REF_TESTOUT5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_PHASER_OUT_DB_CTSBUS1", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX30_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_WW2A0_5", + "CMT_TOP_WW4C1_0", + "CMT_TOP_WL1END2_11", + "CMT_TOP_IMUX14_3", + "CMT_TOP_EE4B1_9", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "CMT_TOP_SW4END1_5", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_NE2A0_2", + "CMT_PHASER_OUT_DB_BURSTPENDING", + "CMT_TOP_WW4C2_11", + "CMT_TOP_NW2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_FAN3_8", + "CMT_TOP_IMUX27_7", + "CMT_TOP_WW4END1_1", + "CMT_TOP_FAN4_11", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LH8_6", + "CMT_TOP_EE4A0_1", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_SW4END1_9", + "CMT_TOP_WL1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_MONITOR_N_8", + "CMT_PHASER_UP_PHASERREF1", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4END1_6", + "CMT_PHASER_OUT_CA_CTSBUS0", + "CMT_TOP_WL1END2_4", + "CMT_TOP_WR1END0_9", + "CMT_TOP_LH5_9", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX3_3", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_WR1END0_4", + "CMT_PHASER_IN_DB_RSTDQSFIND", + "CMT_PHASER_IN_CA_TESTIN6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_SW4A2_0", + "CMT_PHY_CONTROL_PHYCTLWD31", + "CMT_PHASER_OUT_DB_TESTOUT0", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_PHASER_IN_DB_TESTOUT0", + "CMT_TOP_WW4A1_9", + "CMT_TOP_EE2A0_5", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH4_7", + "CMT_PHASERD_DQSBUS0", + "CMT_TOP_IMUX8_11", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LH4_11", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_EE4A1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_IMUX14_4", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_CTRL0_5", + "CMT_PHASER_IN_DB_STG1REGL3", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_EE4A0_3", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX43_3", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LH11_11", + "CMT_TOP_FAN1_5", + "CMT_TOP_NW2A0_7", + "CMT_TOP_EE4B2_1", + "CMT_TOP_IMUX31_7", + "CMT_TOP_WW4B2_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX6_10", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_IMUX47_0", + "CMT_PHASER_IN_DB_DIVIDERST", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "CMT_TOP_IMUX21_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_FAN4_9", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_CLK0_0", + "CMT_TOP_LH9_7", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END3_7", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_IMUX5_11", + "CMT_TOP_EE4B2_9", + "CMT_PHY_CONTROL_TESTOUTPUT7", + "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_NW2A1_2", + "CMT_TOP_SW4END1_1", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_PHASER_OUT_CA_FINEENABLE", + "CMT_TOP_NW4A1_1", + "CMT_TOP_BYP3_9", + "CMT_TOP_WW2A2_4", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "CMT_TOP_SW4A0_9", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_NE2A0_11", + "CMT_TOP_EE4A2_11", + "CMT_TOP_SE4C2_5", + "CMT_TOP_WW4END2_7", + "CMT_TOP_EE4A3_4", + "CMT_TOP_LH9_5", + "CMT_TOP_NE2A0_3", + "CMT_TOP_IMUX46_9", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_EE2A2_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_IMUX33_11", + "CMT_TOP_IMUX9_8", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_IMUX26_4", + "CMT_PHASER_IN_DB_STG1REGR6", + "CMT_TOP_IMUX38_1", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WR1END0_11", + "CMT_TOP_FAN4_10", + "CMT_TOP_FAN2_11", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_BYP1_8", + "CMT_TOP_IMUX31_1", + "CMT_PHASER_OUT_DB_SCANIN", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EE4C3_9", + "CMT_TOP_IMUX36_8", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_PHASER_IN_DB_SELCALORSTG1", + "CMT_TOP_SW4A1_0", + "CMT_TOP_SE2A1_10", + "CMT_TOP_EE4C0_5", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_LH7_0", + "CMT_PHY_CONTROL_PHYCTLWD9", + "CMT_TOP_IMUX33_7", + "CMT_TOP_SE4C1_2", + "CMT_TOP_ER1BEG1_0", + "CMT_PHY_CONTROL_IBURSTPENDING2", + "CMT_TOP_FAN7_10", + "CMT_TOP_LH2_7", + "CMT_TOP_NE4C2_1", + "CMT_TOP_SW4A2_7", + "CMT_TOP_IMUX23_11", + "CMT_PHY_CONTROL_PHYCTLWD11", + "CMT_TOP_WR1END1_5", + "CMT_TOP_NE2A0_10", + "CMT_TOP_SW4END2_0", + "CMT_TOP_LH8_0", + "CMT_TOP_EE4C0_3", + "CMT_TOP_NW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_IMUX8_6", + "CMT_TOP_BYP0_7", + "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "CMT_PHASER_REF_LOCKED", + "CMT_TOP_LH5_0", + "CMT_TOP_IMUX5_2", + "CMT_TOP_WL1END2_6", + "CMT_TOP_BYP1_9", + "CMT_TOP_IMUX9_3", + "CMT_TOP_BYP1_7", + "CMT_PHASER_OUT_CA_TESTIN7", + "CMT_TOP_IMUX47_1", + "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "CMT_TOP_WW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_EE2A1_9", + "CMT_PHASER_IN_DB_BURSTPENDING", + "CMT_TOP_NE4C3_4", + "CMT_TOP_EE4B2_7", + "CMT_TOP_OCLK_5", + "CMT_TOP_NE2A1_6", + "CMT_PHY_CONTROL_TESTINPUT3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_IMUX8_2", + "CMT_TOP_IMUX1_2", + "CMT_TOP_IMUX46_0", + "CMT_TOP_EE4C1_9", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_LH1_7", + "CMT_TOP_BYP5_3", + "CMT_PHASER_IN_CA_TESTIN13", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX40_4", + "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_BYP7_0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_WW4C1_7", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4A3_6", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_IMUX17_11", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_WR1END2_5", + "CMT_TOP_EE4A0_4", + "CMT_PHASER_OUT_D_OCLK1X_90", + "CMT_TOP_SW4A0_3", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX11_6", + "CMT_TOP_IMUX25_7", + "CMT_TOP_IMUX4_8", + "CMT_PHASER_REF_CLKIN", + "CMT_TOP_SE4BEG2_11", + "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "CMT_PHY_CONTROL_PCENABLECALIB0", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX3_9", + "CMT_TOP_NW4END0_5", + "CMT_TOP_NE4C3_10", + "CMT_TOP_SE2A3_6", + "CMT_TOP_IMUX7_4", + "CMT_TOP_LH3_11", + "CMT_TOP_BYP5_6", + "CMT_TOP_WW4C2_5", + "CMT_TOP_LH7_6", + "CMT_TOP_SE2A1_5", + "CMT_TOP_FAN4_7", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH9_2", + "CMT_TOP_BYP0_1", + "CMT_TOP_LH11_0", + "CMT_PHASER_OUT_DB_TESTIN7", + "CMT_TOP_IMUX27_9", + "CMT_TOP_IMUX14_0", + "CMT_TOP_NW2A1_5", + "CMT_TOP_IMUX21_7", + "CMT_TOP_WW4A0_2", + "CMT_TOP_NE2A1_11", + "CMT_TOP_IMUX7_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX23_7", + "CMT_TOP_IMUX10_10", + "CMT_PHY_CONTROL_INBURSTPENDING1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4C1_2", + "CMT_TOP_LH4_3", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH5_6", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW4C1_4", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_FAN4_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_IMUX9_9", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NW4A3_5", + "CMT_TOP_BYP0_11", + "CMT_TOP_EE2BEG1_10", + "PLL_CLK_FREQBB_REBUFOUT2", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_IMUX33_2", + "CMT_TOP_BYP2_1", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_SE2A3_8", + "CMT_TOP_EE4BEG0_2", + "CMT_PHASER_REF_TESTOUT2", + "CMT_TOP_IMUX25_9", + "CMT_TOP_WW2END1_2", + "CMT_PHASER_OUT_CA_TESTIN12", + "CMT_TOP_ER1BEG3_3", + "CMT_PHY_CONTROL_INRANKC0", + "CMT_PHASER_OUT_DB_COARSEINC", + "CMT_TOP_EE4B2_2", + "CMT_PHASER_OUT_DB_TESTIN0", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_IMUX13_9", + "CMT_PHASER_OUT_CA_OSERDESRST", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_NW2A2_7", + "CMT_TOP_OCLKDIV_11", + "CMT_PHASER_IN_C_RCLK2", + "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "CMT_TOP_IMUX5_8", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_IMUX33_5", + "CMT_PHASER_IN_CA_ENCALIB1", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WW4END2_11", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE2A0_7", + "CMT_TOP_WR1END1_10", + "CMT_PHASER_IN_CA_COUNTERLOADEN", + "CMT_TOP_FAN0_9", + "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "CMT_TOP_EE4C2_10", + "CMT_TOP_SW4END3_0", + "CMT_TOP_WR1END1_2", + "CMT_TOP_NW4A1_5", + "CMT_TOP_IMUX4_9", + "CMT_PHASER_OUT_DB_RDENABLE", + "CMT_PHASER_IN_CA_SYSCLK", + "CMT_TOP_IMUX47_8", + "CMT_PHASER_OUT_DB_COUNTERREADEN", + "CMT_TOP_WW4C1_3", + "CMT_TOP_IMUX26_9", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_IMUX41_2", + "CMT_TOP_SE4C1_5", + "CMT_TOP_WL1END2_7", + "CMT_TOP_WW4A0_1", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_R_TOP_UPPER_B_CLKPLL1", + "CMT_FREQ_BB_PREF_IN3", + "CMT_TOP_CTRL0_4", + "CMT_TOP_NW4END2_3", + "CMT_TOP_SE2A2_8", + "CMT_PHASER_IN_CA_STG1LOAD", + "CMT_PHASER_OUT_DB_SCANOUT", + "CMT_TOP_WW4C2_3", + "CMT_TOP_WW2A3_3", + "CMT_TOP_WL1END3_4", + "CMT_TOP_NE2A2_8", + "CMT_TOP_SW2A0_9", + "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_SW2A0_8", + "CMT_TOP_WW4B3_3", + "CMT_TOP_WW2END0_7", + "CMT_PHASER_IN_CA_TESTIN10", + "CMT_TOP_SW4A3_9", + "CMT_PHY_CONTROL_TESTOUTPUT4", + "CMT_TOP_SE4C0_7", + "CMT_TOP_IMUX1_10", + "CMT_TOP_IMUX4_0", + "CMT_PHY_CONTROL_TESTINPUT0", + "CMT_PHASER_OUT_DB_OCLKDIV", + "CMT_TOP_IMUX40_2", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_EE2BEG3_8", + "CMT_PHASER_OUT_DB_DQSBUS0", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX1_6", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_IMUX14_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_IMUX7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WW4A2_4", + "CMT_TOP_WW4B1_7", + "CMT_TOP_EE2A1_6", + "CMT_TOP_IMUX19_2", + "CMT_PHASER_OUT_DB_EDGEADV", + "CMT_TOP_EE2BEG0_11", + "CMT_PHASER_OUT_DB_TESTOUT3", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_FAN3_4", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP7_9", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX24_10", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_SW2A0_2", + "CMT_TOP_BYP7_8", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX47_7", + "CMT_TOP_BYP0_4", + "CMT_TOP_IMUX21_6", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_EE4A3_11", + "CMT_TOP_IMUX5_4", + "CMT_TOP_SE2A3_10", + "CMT_TOP_SW4END2_10", + "CMT_TOP_NW2A0_5", + "CMT_TOP_NE4C1_2", + "CMT_TOP_WW4C0_9", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_WW2END0_1", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_TOP_ER1BEG2_4", + "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", + "CMT_TOP_IMUX2_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX0_0", + "CMT_PHASER_OUT_CA_TESTIN15", + "CMT_TOP_IMUX15_9", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SW2A2_4", + "CMT_TOP_WW4C2_0", + "CMT_TOP_ICLK_8", + "CMT_TOP_NW2A1_7", + "CMT_TOP_CTRL0_6", + "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "CMT_PHASER_REF_RST", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_NE4BEG1_9", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_WW4A0_6", + "CMT_TOP_IMUX6_8", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WR1END0_1", + "CMT_TOP_CLK0_5", + "CMT_TOP_IMUX41_3", + "CMT_PHY_CONTROL_PLLLOCK", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_SW2A1_4", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_IMUX27_1", + "CMT_PHASER_OUT_C_OCLK", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_IMUX23_9", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_IMUX30_6", + "CMT_TOP_NW4END1_9", + "CMT_TOP_IMUX39_2", + "CMT_TOP_EE4C0_6", + "CMT_PHASER_OUT_DB_DTSBUS0", + "CMT_TOP_IMUX10_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_WW4END3_0", + "CMT_PHY_CONTROL_OBURSTPENDING2", + "CMT_TOP_NW4END1_11", + "CMT_TOP_EE4C2_8", + "CMT_TOP_IMUX43_11", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_SW4A3_11", + "CMT_TOP_IMUX16_3", + "CMT_TOP_OCLK_8", + "CMT_TOP_NE2A0_6", + "CMT_TOP_WW2A3_2", + "CMT_TOP_LH2_2", + "CMT_TOP_CTRL1_6", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_EE4A0_8", + "CMT_TOP_SE4C1_3", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_IMUX8_5", + "CMT_TOP_IMUX9_1", + "CMT_TOP_WW4A0_9", + "CMT_TOP_EE4A3_8", + "CMT_TOP_IMUX37_5", + "CMT_TOP_IMUX11_10", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX28_6", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_IMUX40_10", + "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_MONITOR_N_4", + "CMT_PHY_CONTROL_TESTOUTPUT0", + "CMT_TOP_CLK0_1", + "CMT_TOP_SW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX23_1", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_OCLKDIV_6", + "CMT_PHASER_UP_PHASERREF_ABOVE1", + "CMT_TOP_WW2END1_6", + "CMT_TOP_SW2A0_1", + "CMT_TOP_CTRL1_3", + "CMT_TOP_IMUX10_7", + "CMT_TOP_NE4C2_8", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_IMUX6_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_NW2A3_4", + "CMT_TOP_WR1END2_9", + "CMT_TOP_IMUX27_8", + "CMT_PHASER_IN_CA_STG1REGR7", + "CMT_TOP_LH6_3", + "CMT_TOP_NE2A1_1", + "CMT_TOP_CLK0_9", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_BYP0_9", + "CMT_TOP_EE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_EE4BEG1_4", + "CMT_PHY_CONTROL_TESTSELECT1", + "CMT_TOP_WW2END1_1", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_ER1BEG0_3", + "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "CMT_TOP_WW4END0_2", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_EE2A0_4", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_FAN1_7", + "CMT_PHASER_REF_TESTIN2", + "CMT_TOP_WW4A3_3", + "CMT_PHASER_IN_CA_ENCALIBPHY0", + "CMT_TOP_NW4END3_2", + "CMT_TOP_SW4END2_1", + "CMT_TOP_EE4A3_3", + "CMT_TOP_EE4A1_0", + "CMT_TOP_SW4A2_9", + "CMT_TOP_LH3_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_IMUX41_0", + "CMT_TOP_IMUX32_6", + "CMT_TOP_WR1END3_4", + "CMT_TOP_SW2A1_11", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX11_7", + "CMT_PHASER_C_OCLK_TOIOI", + "CMT_TOP_SW2A2_5", + "CMT_TOP_FAN5_0", + "CMT_PHASER_IN_DB_TESTOUT2", + "CMT_TOP_WW2END2_7", + "CMT_TOP_NW4A2_10", + "CMT_TOP_SW4END1_8", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_IMUX17_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_WW2A1_8", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_IMUX4_10", + "CMT_TOP_FAN6_9", + "CMT_PHY_CONTROL_PHYCTLWD29", + "CMT_TOP_NW2A2_0", + "CMT_PHASER_IN_DB_STG1REGL5", + "CMT_TOP_IMUX11_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_WW2A3_9", + "CMT_TOP_WW4B3_11", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_WW4END2_3", + "CMT_TOP_BYP0_0", + "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "CMT_PHASER_REF_CLKOUT", + "CMT_PHASER_IN_CA_STG1REGL4", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_WW4END0_7", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_PHASER_IN_CA_TESTIN4", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_LH6_10", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_PHASER_OUT_CA_PHASEREFCLK", + "CMT_TOP_NE2A2_6", + "CMT_TOP_IMUX37_2", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WR1END1_7", + "CMT_TOP_IMUX14_9", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_IMUX7_2", + "CMT_TOP_FAN2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_PHY_CONTROL_PHYCTLWD0", + "CMT_TOP_WW4A0_7", + "CMT_TOP_EE4C0_8", + "CMT_PHASER_OUT_CA_DQSBUS1", + "CMT_PHY_CONTROL_PHYCTLWD17", + "CMT_TOP_SE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_WR1END3_8", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_IMUX37_1", + "CMT_TOP_NW2A1_0", + "CMT_TOP_EL1BEG0_4", + "CMT_PHASER_UP_DQS_TO_PHASER_D", + "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_NW2A2_3", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A2_6", + "CMT_TOP_EE4C0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_FAN3_11", + "CMT_TOP_SW4END0_0", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_NE4C3_11", + "CMT_TOP_IMUX37_6", + "CMT_TOP_BYP5_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_LH8_4", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SE4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_IMUX46_5", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_EL1BEG0_1", + "CMT_PHASER_IN_CA_FREQREFCLK", + "CMT_TOP_LH8_8", + "CMT_TOP_NE4C3_9", + "CMT_TOP_WW4B1_1", + "CMT_TOP_BYP2_9", + "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "CMT_TOP_IMUX26_10", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_SE4BEG3_2", + "CMT_PHY_CONTROL_TESTINPUT10", + "CMT_PHASER_OUT_DB_COARSEENABLE", + "CMT_TOP_IMUX2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_IMUX36_4", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SW2A0_3", + "CMT_PHASER_OUT_CA_TESTIN6", + "CMT_TOP_EE4A1_10", + "CMT_TOP_SW2A3_8", + "CMT_TOP_WW2A2_5", + "CMT_TOP_IMUX24_11", + "CMT_TOP_SW2A2_9", + "CMT_TOP_SW4A0_6", + "CMT_TOP_IMUX38_6", + "CMT_TOP_WR1END0_5", + "CMT_TOP_IMUX4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_CTRL0_11", + "CMT_TOP_IMUX19_8", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_IMUX36_5", + "CMT_PHASER_IN_DB_RANKSEL0", + "CMT_TOP_WW2A0_3", + "CMT_TOP_LH10_5", + "CMT_TOP_NE4C3_3", + "CMT_TOP_FAN7_2", + "CMT_TOP_IMUX7_10", + "CMT_PHASER_IN_CA_STG1REGL6", + "CMT_TOP_WW4B1_11", + "CMT_TOP_BYP6_1", + "CMT_TOP_WL1END2_1", + "CMT_TOP_SW4A0_2", + "CMT_TOP_IMUX10_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_OCLK_10", + "CMT_TOP_LH5_2", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_PHASERREF_PHASERIN_D", + "CMT_TOP_SW2A2_6", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_NW4END3_6", + "CMT_TOP_NW4END3_8", + "CMT_TOP_WL1END0_7", + "CMT_TOP_IMUX10_11", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX9_7", + "CMT_TOP_BYP5_7", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "CMT_TOP_SW2A1_6", + "CMT_TOP_IMUX18_11", + "CMT_PHASER_IN_CA_STG1READ", + "CMT_TOP_IMUX37_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_EE4B2_8", + "CMT_TOP_WW2A1_10", + "CMT_TOP_IMUX42_5", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_PHASER_IN_DB_FREQREFCLK", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LH8_10", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_IMUX24_5", + "CMT_PHASER_OUT_DB_SCANCLK", + "CMT_TOP_NW2A2_10", + "CMT_TOP_ER1BEG2_8", + "CMT_PHASER_OUT_CA_TESTOUT0", + "CMT_PHASER_REF_TMUXOUT_TOHCLK", + "CMT_TOP_SW2A2_8", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_6", + "CMT_PHASER_REF_TESTOUT3", + "CMT_TOP_FAN3_3", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_EE2A1_3", + "CMT_PHASER_OUT_DB_TESTIN1", + "CMT_PHY_CONTROL_PHYCTLWD1", + "CMT_TOP_IMUX24_9", + "CMT_TOP_SE2A2_2", + "CMT_PHASER_OUT_CA_TESTIN11", + "CMT_TOP_IMUX25_10", + "CMT_PHASER_OUT_CA_DTSBUS0", + "CMT_TOP_SE4C3_0", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_EE2A1_7", + "CMT_TOP_IMUX45_6", + "CMT_TOP_SW4END0_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX3_8", + "CMT_PHASER_OUT_DB_ENCALIB1", + "CMT_TOP_WW2END1_9", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_LH6_8", + "CMT_TOP_OCLK_11", + "CMT_TOP_BYP1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_SW4A1_4", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX46_6", + "CMT_PHASER_IN_DB_TESTIN2", + "CMT_PHY_CONTROL_INBURSTPENDING0", + "CMT_TOP_IMUX40_9", + "CMT_TOP_IMUX25_11", + "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "CMT_TOP_LH10_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_WW4END3_3", + "CMT_TOP_WW4B3_2", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_FAN3_0", + "CMT_PHY_CONTROL_TESTINPUT5", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_IMUX32_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_EE4A0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_PHY_CONTROL_REFDLLLOCK", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_FAN0_11", + "CMT_TOP_SE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_IMUX44_4", + "CMT_TOP_SW4A2_11", + "CMT_PHASER_REF_TMUXOUT", + "CMT_TOP_SW4END0_9", + "CMT_TOP_EE4C1_5", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_IMUX29_4", + "CMT_PHASER_IN_CA_ICLKDIV", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX32_0", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_SW4END2_3", + "CMT_TOP_BYP4_2", + "CMT_PHASER_IN_DB_RANKSELPHY0", + "CMT_TOP_WL1END3_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_FAN5_4", + "CMT_TOP_EE2A2_2", + "CMT_TOP_EE4A2_1", + "CMT_TOP_EE2A2_11", + "CMT_TOP_NW4A2_11", + "CMT_TOP_NW4END3_10", + "CMT_TOP_WW4END0_8", + "CMT_TOP_LH11_8", + "CMT_TOP_IMUX45_5", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WR1END0_6", + "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", + "CMT_TOP_IMUX3_1", + "CMT_TOP_WW4END3_1", + "CMT_PHY_CONTROL_INRANKA1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_IMUX16_2", + "CMT_TOP_IMUX34_10", + "CMT_TOP_FAN4_4", + "CMT_TOP_FAN7_3", + "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "CMT_TOP_LH4_0", + "CMT_TOP_NE4BEG2_0", + "CMT_PHASER_UP_DQS_TO_PHASER_C", + "CMT_TOP_FAN3_9", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_IMUX22_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_EE4C3_6", + "CMT_PHY_CONTROL_TESTINPUT12", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_BYP1_10", + "CMT_TOP_FAN7_0", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_FAN2_9", + "CMT_PHASER_OUT_DB_TESTIN5", + "CMT_TOP_WW2A0_11", + "CMT_TOP_SW4A1_2", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_IMUX4_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_IMUX26_2", + "CMT_PHY_CONTROL_PHYCTLWD2", + "CMT_TOP_BYP5_11", + "CMT_TOP_BYP2_10", + "CMT_TOP_FAN1_8", + "CMT_TOP_LH8_11", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_IMUX11_8", + "CMT_TOP_SE4C2_10", + "CMT_TOP_ER1BEG3_4", + "CMT_PHY_CONTROL_PHYCTLWD28", + "CMT_TOP_IMUX5_6", + "CMT_TOP_IMUX38_0", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_LH2_10", + "CMT_TOP_CLK1_7", + "CMT_PHASER_OUT_CA_TESTIN0", + "CMT_TOP_WW4B3_1", + "CMT_TOP_EE4A0_10", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_IMUX16_5", + "CMT_TOP_CLK1_4", + "CMT_TOP_LH8_3", + "CMT_TOP_IMUX22_11", + "CMT_PHASER_OUT_DB_TESTIN3", + "CMT_TOP_WW2END2_0", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_PHASER_IN_DB_DQSFOUND", + "CMT_TOP_IMUX45_2", + "CMT_PHASER_IN_DB_FINEOVERFLOW", + "CMT_PHY_CONTROL_TESTOUTPUT15", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_NE4C0_11", + "CMT_TOP_EE4B1_2", + "CMT_TOP_IMUX15_10", + "CMT_TOP_WW4C0_0", + "CMT_TOP_SW2A1_7", + "CMT_TOP_BYP2_4", + "CMT_PHASER_IN_DB_TESTIN11", + "CMT_PHY_CONTROL_TESTINPUT7", + "CMT_TOP_EE4B3_1", + "CMT_TOP_SE4C3_3", + "CMT_TOP_WW4END1_9", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_SW4END1_4", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_IMUX34_7", + "CMT_TOP_WW2A0_7", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_IMUX27_4", + "CMT_TOP_WL1END2_5", + "CMT_TOP_OCLK_1", + "CMT_TOP_NW4END0_2", + "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "CMT_TOP_EE2A1_5", + "CMT_PHASER_OUT_DB_TESTOUT2", + "CMT_TOP_FAN4_2", + "CMT_TOP_CTRL1_11", + "CMT_TOP_WW4C3_8", + "CMT_TOP_NW4END1_1", + "CMT_PHASER_IN_DB_FINEENABLE", + "CMT_TOP_FAN3_1", + "CMT_TOP_IMUX45_9", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_SW4END2_11", + "CMT_TOP_WR1END2_6", + "CMT_TOP_SE2A2_5", + "CMT_TOP_SE4BEG1_4", + "CMT_PHY_CONTROL_TESTOUTPUT8", + "CMT_TOP_FAN2_7", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW2END2_11", + "CMT_PHY_CONTROL_PHYCTLWD27", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_SW4A3_1", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX42_6", + "CMT_PHASER_IN_CA_SYNCIN", + "CMT_TOP_EE4B1_1", + "CMT_TOP_BYP0_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_CLK1_11", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_EE4C3_11", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_IMUX32_10", + "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "CMT_TOP_NW4A0_4", + "CMT_PHASER_OUT_D_OCLK", + "CMT_PHY_CONTROL_TESTOUTPUT3", + "CMT_TOP_SW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_NW4END2_8", + "CMT_TOP_EE2A0_10", + "CMT_TOP_EE2A3_9", + "CMT_PHASER_IN_CA_TESTIN8", + "CMT_TOP_SW2A1_1", + "CMT_TOP_EE4B2_4", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX18_0", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_BYP6_4", + "CMT_TOP_NW4END1_6", + "CMT_PHASER_OUT_DB_TESTIN13", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_LH7_4", + "CMT_TOP_IMUX23_0", + "CMT_PHASER_IN_DB_RCLK", + "CMT_TOP_IMUX43_8", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX21_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX21_2", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_EE4A2_9", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE4B0_5", + "CMT_TOP_IMUX47_10", + "CMT_PHY_CONTROL_PHYCTLWD26", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_6", + "CMT_PHASER_IN_DB_EDGEADV", + "CMT_TOP_WW4C0_1", + "CMT_TOP_WW2A3_0", + "CMT_TOP_FAN7_1", + "CMT_TOP_NW2A1_3", + "CMT_PHASER_IN_CA_EDGEADV", + "CMT_TOP_NE4BEG0_9", + "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "CMT_TOP_EE2BEG2_10", + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE4BEG3_3", + "CMT_PHASER_IN_CA_STG1REGR5", + "CMT_PHY_CONTROL_PHYCTLWD22", + "CMT_TOP_LH1_10", + "CMT_PHASER_IN_DB_STG1OVERFLOW", + "CMT_TOP_EE4B0_10", + "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "CMT_TOP_SE2A3_2", + "CMT_TOP_IMUX16_6", + "CMT_TOP_IMUX1_5", + "CMT_PHASER_IN_DB_RST", + "CMT_PHASER_IN_DB_STG1REGL0", + "CMT_TOP_SE4C1_4", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_NW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_EE4B3_5", + "CMT_TOP_IMUX26_7", + "CMT_TOP_NE4C1_0", + "CMT_TOP_EE2A3_8", + "CMT_TOP_IMUX45_11", + "CMT_PHASER_IN_DB_ENCALIBPHY0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_IMUX40_0", + "CMT_TOP_IMUX14_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_EE4A0_2", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE2BEG1_6", + "CMT_R_TOP_UPPER_B_CLKPLL4", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_NW4END3_11", + "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_IMUX8_7", + "CMT_TOP_WW2END0_4", + "CMT_TOP_SW4A1_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_LH10_7", + "CMT_TOP_EE4C2_3", + "CMT_R_TOP_UPPER_B_CLKPLL5", + "CMT_PHASER_IN_CA_TESTIN9", + "CMT_TOP_SE2A3_9", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_11", + "CMT_PHY_CONTROL_PHYCTLWD10", + "CMT_TOP_EE2A1_11", + "CMT_TOP_SE2A1_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_WW2A1_9", + "CMT_TOP_FAN1_11", + "CMT_TOP_IMUX18_4", + "CMT_TOP_WL1END1_5", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_NE2A2_3", + "CMT_PHASER_IN_CA_FINEENABLE", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_IMUX24_1", + "CMT_TOP_WW4END1_3", + "CMT_TOP_WW2END2_6", + "CMT_TOP_WW2A2_11", + "CMT_TOP_SW2A0_10", + "CMT_PHASER_OUT_DB_RST", + "CMT_TOP_EE2A3_0", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_WW2A3_7", + "CMT_TOP_WL1END2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_SW2A0_6", + "CMT_TOP_IMUX13_11", + "CMT_TOP_NW4A3_9", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_NW2A0_1", + "CMT_TOP_IMUX6_0", + "CMT_TOP_LH1_11", + "CMT_TOP_NW2A2_6", + "CMT_TOP_CTRL0_0", + "CMT_TOP_WR1END1_3", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX43_0", + "CMT_TOP_SE2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4C3_0", + "CMT_TOP_LH11_1", + "CMT_TOP_SW2A1_8", + "CMT_TOP_EE4C3_4", + "CMT_TOP_NW4A3_11", + "CMT_TOP_ER1BEG3_8", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN7_4", + "CMT_TOP_NW4END0_4", + "CMT_TOP_FAN1_6", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_IMUX22_10", + "CMT_TOP_WW4B2_5", + "CMT_PHASER_OUT_DB_SCANMODEB", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C1_4", + "CMT_TOP_IMUX20_4", + "CMT_TOP_WW2A2_1", + "CMT_PHASER_OUT_CA_SCANOUT", + "CMT_TOP_WR1END1_11", + "CMT_PHASER_OUT_DB_DIVIDERST", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WR1END3_10", + "CMT_TOP_WW4A1_6", + "CMT_TOP_BYP7_11", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_PHY_CONTROL_IBURSTPENDING3", + "CMT_TOP_SE2A1_3", + "CMT_TOP_WW4B0_9", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX0_4", + "CMT_TOP_SE2A3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_R_PHASER_IN_C_WRCLK_FIFO", + "CMT_TOP_IMUX20_3", + "CMT_TOP_CTRL1_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EE4A2_5", + "CMT_TOP_SE4C1_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_NW4END0_0", + "CMT_TOP_NW4A3_10", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX12_2", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_NW4A3_8", + "CMT_TOP_WW4B0_2", + "CMT_TOP_NE2A0_7", + "CMT_TOP_IMUX34_5", + "CMT_PHASER_IN_CA_TESTIN11", + "CMT_PHASER_IN_DB_TESTIN1", + "CMT_PHASER_OUT_CA_SCANMODEB", + "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "CMT_TOP_EE4C2_5", + "CMT_TOP_WL1END2_2", + "CMT_TOP_IMUX6_3", + "CMT_PHASER_OUT_C_OCLKDIV", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_IMUX35_7", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_IMUX28_10", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_IMUX2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_CTRL0_10", + "CMT_TOP_WW4END2_2", + "CMT_TOP_WL1END0_8", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_IMUX47_6", + "CMT_TOP_IMUX23_2", + "CMT_TOP_WL1END0_9", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_IMUX39_6", + "CMT_TOP_EE4C0_10", + "CMT_TOP_IMUX6_4", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_IMUX12_3", + "CMT_TOP_LH8_2", + "CMT_TOP_IMUX36_9", + "CMT_TOP_BYP2_5", + "CMT_TOP_NW2A0_10", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX38_8", + "CMT_TOP_IMUX0_6", + "CMT_TOP_NE4BEG3_11", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SE2A0_8", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NE2A0_1", + "CMT_TOP_IMUX31_4", + "CMT_TOP_NE2A3_9", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX5_1", + "CMT_TOP_IMUX47_2", + "CMT_TOP_LH12_1", + "CMT_TOP_SW2A3_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_WW2END3_6", + "CMT_TOP_NW2A0_8", + "CMT_PHASER_UP_PHASERREF_BELOW0", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_IMUX44_3", + "CMT_TOP_LH3_4", + "CMT_TOP_EE2A2_1", + "CMT_TOP_WW4A2_3", + "CMT_TOP_NW2A3_2", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX39_8", + "CMT_TOP_SW4END2_7", + "CMT_TOP_FAN2_4", + "CMT_TOP_EE4A1_6", + "CMT_TOP_EE4B1_3", + "CMT_TOP_WW2A2_9", + "CMT_TOP_IMUX42_10", + "CMT_PHASER_IN_CA_STG1REGL1", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_WW4END0_1", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE4B1_0", + "CMT_TOP_IMUX34_11", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_ICLKDIV_0", + "CMT_PHASER_IN_CA_SCANENB", + "CMT_TOP_IMUX10_3", + "CMT_TOP_WL1END3_2", + "CMT_PHASER_IN_CA_ENCALIBPHY1", + "CMT_TOP_NW4A2_8", + "CMT_TOP_IMUX35_5", + "CMT_TOP_WW4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_NE4C3_2", + "CMT_PHY_CONTROL_INRANKD0", + "CMT_TOP_NE2A3_8", + "CMT_TOP_WW4END3_4", + "CMT_TOP_LH1_1", + "CMT_PHASERD_DQSBUS1", + "CMT_TOP_CTRL1_5", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_EE2BEG3_10", + "CMT_PHY_CONTROL_TESTINPUT4", + "CMT_TOP_LH7_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_CLK0_8", + "CMT_TOP_NE2A0_5", + "CMT_TOP_SW4END2_6", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_EE4C3_5", + "CMT_R_PHASER_OUT_C_RDCLK_FIFO", + "CMT_TOP_IMUX8_8", + "CMT_TOP_EE2BEG3_1", + "CMT_PHASERTOP_PHYCTLEMPTY", + "CMT_TOP_EE2A2_4", + "CMT_TOP_NE2A3_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "CMT_TOP_IMUX13_1", + "CMT_PHASER_OUT_CA_ENCALIB1", + "CMT_TOP_WW2END0_3", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_PHASER_IN_DB_RANKSEL1", + "CMT_TOP_EE4C1_3", + "CMT_TOP_EE4A2_0", + "CMT_PHY_CONTROL_OBURSTPENDING1", + "CMT_PHASER_OUT_CA_OCLK", + "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_EE4B2_11", + "CMT_TOP_NE4C2_9", + "CMT_TOP_NW2A2_4", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX37_3", + "CMT_TOP_IMUX37_8", + "CMT_TOP_ICLKDIV_4", + "CMT_PHASERREF_PHASEROUT_D", + "CMT_TOP_CTRL1_2", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_EE4B0_0", + "CMT_TOP_IMUX18_9", + "CMT_TOP_SE2A0_0", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_EE2A1_10", + "CMT_PHY_CONTROL_IRANKD1", + "CMT_PHASER_C_ICLK_TOIOI", + "CMT_TOP_NW4A2_4", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_IMUX3_2", + "CMT_TOP_WW4A3_9", + "CMT_TOP_SE2A1_7", + "CMT_TOP_WW4END1_0", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_NW4END2_6", + "CMT_PHASER_IN_CA_SCANMODEB", + "CMT_TOP_IMUX34_1", + "CMT_TOP_LH6_9", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW4A2_1", + "CMT_TOP_SW4A2_4", + "CMT_PHASER_OUT_CA_MEMREFCLK", + "CMT_TOP_NE4C2_11", + "CMT_TOP_WW4END1_10", + "CMT_TOP_LH9_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_NE4C3_6", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WW2END3_1", + "CMT_TOP_BYP4_3", + "CMT_PHY_CONTROL_IRANKD0", + "CMT_TOP_WW2END2_10", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "CMT_PHASER_OUT_CA_TESTIN9", + "CMT_TOP_SE2A0_7", + "CMT_TOP_IMUX35_11", + "CMT_TOP_WW2END2_2", + "CMT_TOP_BYP7_5", + "CMT_TOP_SW4END0_11", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX0_8", + "CMT_TOP_SW2A1_2", + "CMT_TOP_EE4B1_6", + "CMT_TOP_IMUX20_5", + "CMT_TOP_WW2END0_10", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_BYP5_0", + "CMT_TOP_IMUX32_9", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX38_10", + "CMT_PHASER_IN_DB_STG1LOAD", + "CMT_TOP_LH1_4", + "CMT_PHASER_OUT_DB_TESTIN6", + "CMT_TOP_NW4A0_6", + "CMT_TOP_WW4END3_8", + "CMT_FREQ_PHASER_REFMUX_1", + "CMT_TOP_EE4C2_2", + "CMT_PHASER_IN_DB_STG1REGR7", + "CMT_TOP_CLK1_10", + "CMT_TOP_WL1END3_11", + "CMT_TOP_WW2END3_4", + "CMT_PHASER_IN_DB_FINEINC", + "CMT_TOP_WW4C1_8", + "CMT_TOP_IMUX39_10", + "CMT_PHASER_IN_DB_SYNCIN", + "CMT_TOP_WR1END1_8", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_WW4END3_10", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4C3_10", + "CMT_TOP_EE4B3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_PHASER_IN_DB_SCANCLK", + "CMT_TOP_EE4B3_7", + "CMT_R_TOP_UPPER_B_CLKPLL2", + "CMT_TOP_NW4END0_7", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SW4A1_10", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX22_7", + "CMT_TOP_NW2A2_5", + "CMT_TOP_LH7_3", + "CMT_TOP_IMUX20_1", + "CMT_TOP_WW4B1_3", + "CMT_TOP_FAN5_8", + "CMT_TOP_SE2A1_9", + "CMT_TOP_OCLK_4", + "CMT_TOP_SE4C2_0", + "CMT_PHASER_UP_PHASERREF_ABOVE0", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_WW2A0_2", + "CMT_PHY_CONTROL_IRANKC1", + "CMT_PHASER_IN_DB_PHASELOCKED", + "CMT_TOP_IMUX44_11", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_WW4A1_5", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX43_2", + "CMT_TOP_LH12_5", + "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "CMT_PHASER_C_OCLK90_TOIOI", + "CMT_TOP_IMUX41_11", + "CMT_PHASER_OUT_CA_SYNCIN", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_IMUX46_1", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_EE4C2_6", + "CMT_TOP_WW4C3_1", + "CMT_TOP_ICLK_1", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_IMUX42_1", + "CMT_TOP_BYP7_6", + "CMT_TOP_NW4END1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_NW4A3_2", + "CMT_TOP_SW4A0_5", + "CMT_TOP_IMUX4_6", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_WW4END0_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_IMUX3_6", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_WW2A3_1", + "CMT_PHY_CONTROL_TESTOUTPUT1", + "CMT_TOP_IMUX35_3", + "CMT_TOP_SW4END0_10", + "CMT_TOP_LH12_2", + "CMT_TOP_IMUX0_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_EE2BEG3_11", + "CMT_PHASER_IN_CA_STG1REGL0", + "CMT_TOP_WW4END2_6", + "CMT_PHASER_IN_D_ICLK", + "CMT_TOP_LH11_7", + "CMT_TOP_SW4END3_3", + "CMT_PHASER_OUT_CA_TESTIN14", + "CMT_PHASERD_DTSBUS0", + "CMT_TOP_NW4A1_7", + "CMT_TOP_WW2A3_5", + "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_IMUX19_6", + "CMT_TOP_FAN4_8", + "CMT_TOP_IMUX34_3", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WW4END1_11", + "CMT_PHASER_IN_DB_STG1REGR3", + "CMT_TOP_CLK0_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4C3_7", + "CMT_TOP_WW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_FREQ_BB_PREF_IN1", + "CMT_TOP_IMUX35_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_IMUX10_0", + "CMT_TOP_LH11_3", + "CMT_TOP_SE2A0_9", + "CMT_TOP_WL1END3_7", + "CMT_TOP_IMUX34_8", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WR1END3_3", + "CMT_TOP_IMUX46_4", + "CMT_TOP_SE2A2_10", + "CMT_TOP_WW4C2_4", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_IMUX22_0", + "CMT_TOP_IMUX9_11", + "CMT_TOP_WW4A2_9", + "CMT_TOP_SE4C1_0", + "CMT_TOP_IMUX14_5", + "CMT_TOP_WL1END2_9", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_EE4C1_1", + "CMT_TOP_NW4A0_11", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX13_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_SE4C2_3", + "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX27_5", + "CMT_TOP_OCLK_0", + "CMT_TOP_LH7_8", + "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "CMT_TOP_IMUX7_8", + "CMT_TOP_ICLK_0", + "CMT_TOP_WW2END2_3", + "CMT_TOP_WR1END0_10", + "CMT_PHASER_OUT_CA_CTSBUS1", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END1_5", + "CMT_TOP_IMUX44_6", + "CMT_PHASER_IN_CA_MEMREFCLK", + "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "CMT_TOP_IMUX22_3", + "CMT_TOP_NE4C2_4", + "CMT_PHASER_IN_CA_ENSTG1", + "CMT_TOP_WL1END1_2", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_PHASER_IN_DB_ENCALIBPHY1", + "CMT_TOP_SE4C3_6", + "CMT_PHY_CONTROL_INBURSTPENDING3", + "CMT_TOP_LH9_10", + "CMT_TOP_NW2A1_10", + "CMT_TOP_SW4A3_8", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW2A2_0", + "CMT_TOP_IMUX13_3", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX18_7", + "CMT_PHASER_OUT_CA_RST", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX28_4", + "CMT_PHASER_IN_CA_RANKSEL1", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH1_8", + "CMT_TOP_LH10_10", + "CMT_TOP_IMUX42_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_WL1END1_1", + "CMT_FREQ_PHASER_REFMUX_0", + "CMT_PHY_CONTROL_RESET", + "CMT_TOP_IMUX3_10", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_WW2END2_8", + "CMT_TOP_EE2A0_8", + "CMT_TOP_LH7_1", + "CMT_TOP_SW2A3_5", + "CMT_TOP_IMUX31_11", + "CMT_PHASER_OUT_CA_TESTIN13", + "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "CMT_PHASERD_CTSBUS0", + "CMT_PHY_CONTROL_TESTSELECT2", + "CMT_TOP_IMUX19_3", + "CMT_TOP_FAN0_7", + "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "CMT_TOP_WW2END1_4", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_NW4END3_7", + "CMT_PHASER_REF_TESTIN7", + "CMT_TOP_CLK1_2", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_IMUX34_9", + "CMT_TOP_EE4B0_6", + "CMT_PHASER_OUT_DB_OCLKDELAYED", + "CMT_TOP_EE4B2_5", + "CMT_TOP_IMUX42_2", + "CMT_PHASER_OUT_DB_FREQREFCLK", + "CMT_TOP_WW4C2_9", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_WW2A2_2", + "CMT_TOP_SW4A2_5", + "CMT_TOP_NE2A3_2", + "CMT_PHASER_OUT_CA_SCANENB", + "CMT_TOP_IMUX43_1", + "CMT_PHASER_IN_CA_SCANIN", + "CMT_TOP_WW4END2_10", + "CMT_TOP_EE4C1_4", + "CMT_TOP_IMUX44_9", + "CMT_PHASER_IN_C_ICLK", + "CMT_TOP_WW4B1_6", + "CMT_TOP_NW4A1_11", + "CMT_TOP_IMUX42_0", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_IMUX24_7", + "CMT_PHY_CONTROL_INBURSTPENDING2", + "CMT_TOP_IMUX47_4", + "CMT_TOP_NE2A1_2", + "CMT_TOP_BYP5_2", + "CMT_TOP_IMUX39_4", + "CMT_TOP_FAN7_8", + "CMT_TOP_IMUX40_8", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_SW2A1_10", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_IMUX33_0", + "CMT_TOP_NE4C1_1", + "CMT_TOP_NE4C3_8", + "CMT_TOP_EE4A3_10", + "CMT_TOP_IMUX28_3", + "CMT_TOP_IMUX1_4", + "CMT_TOP_IMUX13_4", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_EE4B1_8", + "CMT_TOP_SW4A1_9", + "CMT_TOP_SE4C2_8", + "CMT_TOP_LH1_5", + "CMT_TOP_WW4END3_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_WW2END3_3", + "CMT_PHASER_OUT_CA_DIVIDERST", + "CMT_PHASER_IN_CA_STG1REGL7", + "CMT_PHASER_OUT_DB_TESTIN14", + "CMT_TOP_EL1BEG2_5", + "CMT_L_TOP_UPPER_B_CLKINT_3", + "CMT_TOP_NE4C0_2", + "CMT_TOP_FAN6_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_IMUX19_10", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_LH7_5", + "CMT_TOP_IMUX19_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_FAN0_2", + "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "CMT_TOP_IMUX47_5", + "CMT_TOP_IMUX27_3", + "CMT_TOP_FAN6_0", + "CMT_TOP_IMUX24_0", + "CMT_TOP_IMUX26_0", + "CMT_TOP_WR1END2_3", + "CMT_PHY_CONTROL_PHYCTLWD6", + "CMT_TOP_WR1END1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_PHY_CONTROL_ECALIB0", + "CMT_TOP_NE4C0_6", + "CMT_TOP_EE4C0_0", + "CMT_TOP_EE2A3_10", + "CMT_PHY_CONTROL_PHYCTLWD7", + "CMT_TOP_SE4C1_8", + "CMT_PHASER_IN_DB_STG1REGR1", + "CMT_TOP_EE2A0_2", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_IMUX47_9", + "CMT_TOP_SE4C1_7", + "CMT_TOP_FAN0_10", + "CMT_TOP_IMUX45_7", + "CMT_TOP_EE2A3_4", + "CMT_TOP_IMUX13_0", + "CMT_TOP_ER1BEG2_10", + "CMT_PHASER_OUT_CA_FREQREFCLK", + "CMT_TOP_WW2END1_10", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_IMUX29_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_IMUX33_9", + "CMT_PHASER_OUT_DB_ENCALIB0", + "CMT_TOP_SW4END3_1", + "CMT_TOP_IMUX5_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_NW4A1_9", + "CMT_PHASER_IN_CA_PHASEREFCLK", + "CMT_TOP_WW2END0_11", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4C0_8", + "CMT_TOP_IMUX16_10", + "CMT_PHASER_OUT_D_OCLKDIV", + "CMT_PHASER_IN_DB_PHASEREFCLK", + "CMT_PHASER_IN_CA_TESTIN5", + "CMT_TOP_IMUX15_4", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_LH10_11", + "CMT_PHY_CONTROL_IBURSTPENDING0", + "CMT_PHASER_IN_DB_SCANIN", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_NW2A2_9", + "CMT_PHASER_OUT_DB_MEMREFCLK", + "CMT_TOP_EE4B3_11", + "CMT_TOP_EE2A1_0", + "CMT_TOP_WW4A1_1", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_LH9_9", + "CMT_TOP_EE4B0_1", + "CMT_TOP_SE4BEG3_4", + "CMT_PHASER_IN_DB_SCANENB", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_PHASER_IN_CA_TESTIN2", + "CMT_TOP_SE2A0_10", + "CMT_PHASER_OUT_DB_SYNCIN", + "CMT_TOP_NE4C2_3", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_CLK0_3", + "CMT_TOP_IMUX14_1", + "CMT_PHASERD_CTSBUS1", + "CMT_PHY_CONTROL_TESTSELECT0", + "CMT_TOP_LH8_9", + "CMT_TOP_WW2A3_11", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_IMUX2_7", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW4C3_6", + "CMT_TOP_EE4C0_4", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX28_8", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LH2_6", + "CMT_PHY_CONTROL_TESTOUTPUT13", + "CMT_TOP_IMUX11_9", + "CMT_TOP_WW4A1_11", + "CMT_PHASER_REF_TESTOUT1", + "CMT_PHASER_OUT_CA_BURSTPENDING", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_BYP4_8", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_EE4C1_6", + "CMT_PHASER_OUT_DB_FINEINC", + "CMT_PHY_CONTROL_TESTINPUT6", + "CMT_TOP_NW2A0_4", + "CMT_TOP_NW4END3_9", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LH12_7", + "CMT_TOP_WW2END1_7", + "CMT_PHY_CONTROL_PHYCTLWD24", + "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "CMT_TOP_LH6_2", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX45_8", + "CMT_PHASER_REF_CLKOUT_TOHCLK", + "CMT_FREQ_BB_PREF_IN0", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_EE2A0_3", + "CMT_TOP_WW4B0_10", + "CMT_TOP_IMUX33_4", + "CMT_TOP_BYP1_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_WL1END0_11", + "CMT_PHASER_IN_CA_STG1REGR1", + "CMT_TOP_SW2A0_5", + "CMT_TOP_EE4C3_8", + "CMT_PHASER_REF_TESTIN1", + "CMT_TOP_IMUX35_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_WW2A3_10", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_NW4END1_7", + "CMT_TOP_IMUX36_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_EE4BEG1_3", + "CMT_PHY_CONTROL_PHYCTLWD4", + "CMT_TOP_SW4END3_2", + "CMT_TOP_WL1END0_5", + "PLL_CLK_FREQBB_REBUFOUT0", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_NE4C0_1", + "CMT_PHY_CONTROL_IRANKA0", + "CMT_TOP_IMUX11_1", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "CMT_TOP_SW2A1_5", + "CMT_TOP_IMUX33_6", + "CMT_PHY_CONTROL_PHYCTLWD15", + "CMT_TOP_EE4C2_9", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_EE4B3_3", + "CMT_TOP_WW4A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_WW2END2_1", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_WW4END0_11", + "CMT_PHY_CONTROL_PHYCTLFULL", + "CMT_TOP_IMUX25_4", + "CMT_TOP_IMUX2_9", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_SW4END1_0", + "CMT_TOP_EE2A1_1", + "CMT_TOP_SE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_EE4A3_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_SE4C2_11", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_PHASER_OUT_CA_FINEINC", + "CMT_TOP_BYP2_11", + "CMT_TOP_BYP1_1", + "CMT_TOP_LH11_6", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_NW2A0_11", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WR1END0_3", + "CMT_TOP_WW4B3_5", + "CMT_TOP_EL1BEG1_6", + "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "CMT_TOP_IMUX31_9", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_PHASER_OUT_CA_ENCALIB0", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_BYP6_0", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WR1END1_6", + "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "CMT_TOP_SE4C0_2", + "CMT_TOP_LH11_10", + "CMT_PHASER_OUT_CA_TESTOUT3", + "CMT_TOP_EE4A2_8", + "CMT_TOP_SE2A1_1", + "CMT_TOP_NW4END1_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_IMUX31_3", + "CMT_TOP_EE4C1_8", + "CMT_TOP_IMUX20_11", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_WW4END1_4", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX9_10", + "CMT_TOP_SW4A1_5", + "CMT_TOP_SE4C0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_SW2A1_0", + "CMT_TOP_SE4BEG1_7", + "CMT_PHASER_IN_CA_ISERDESRST", + "CMT_TOP_EE2A0_0", + "CMT_TOP_CTRL1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_WW4A1_2", + "CMT_TOP_WW4C3_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_IMUX5_9", + "CMT_PHY_CONTROL_TESTOUTPUT12", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_IMUX38_2", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_IMUX1_11", + "CMT_TOP_IMUX35_10", + "CMT_TOP_EE4A3_0", + "CMT_TOP_WW2A3_6", + "CMT_TOP_NW2A3_1", + "CMT_TOP_BYP3_5", + "CMT_TOP_BYP6_11", + "CMT_TOP_SW2A3_4", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX42_8", + "CMT_PHY_CONTROL_TESTINPUT14", + "CMT_TOP_IMUX30_2", + "CMT_TOP_IMUX45_1", + "CMT_TOP_WW4B3_0", + "CMT_TOP_LH3_6", + "CMT_TOP_IMUX12_0", + "CMT_TOP_EE2BEG2_9", + "CMT_PHY_CONTROL_PHYCTLWD20", + "CMT_TOP_IMUX11_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "CMT_TOP_IMUX24_3", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX19_9", + "CMT_PHASER_REF_TESTIN0", + "CMT_TOP_IMUX24_2", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_LH3_0", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_WW2A1_1", + "CMT_TOP_LH2_0", + "CMT_PHASER_IN_CA_STG1REGL8", + "CMT_TOP_IMUX22_2", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX2_8", + "CMT_TOP_IMUX22_9", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_PHASER_IN_CA_TESTIN7", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_ICLK_10", + "CMT_TOP_SE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_LH2_11", + "CMT_TOP_SW4END1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_TOP_WL1END1_4", + "CMT_TOP_IMUX37_9", + "CMT_TOP_EE2A2_10", + "CMT_TOP_WW4C3_9", + "CMT_PHASER_REF_TESTOUT7", + "CMT_PHY_CONTROL_TESTOUTPUT10", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE4B0_11", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH7_11", + "CMT_TOP_EE4A0_7", + "CMT_TOP_EE4A0_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_EE4B1_5", + "CMT_PHASER_IN_DB_STG1REGL6", + "CMT_PHY_CONTROL_TESTOUTPUT11", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_IMUX19_1", + "CMT_TOP_ER1BEG3_6", + "CMT_PHASER_REF_TESTIN6", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_WW4B2_10", + "CMT_TOP_IMUX17_3", + "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CMT_PHY_CONTROL_INRANKD1", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX36_0", + "CMT_TOP_WW2A2_7", + "CMT_TOP_IMUX33_8", + "CMT_TOP_SW4END2_8", + "CMT_TOP_NE4C3_7", + "CMT_TOP_CLK1_9", + "CMT_TOP_WW4C2_7", + "CMT_PHASER_IN_DB_SCANOUT", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_NW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW4END0_5", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_BYP3_2", + "CMT_PHASER_IN_CA_FINEOVERFLOW", + "CMT_TOP_NW4END2_1", + "CMT_PHASER_IN_CA_STG1REGR0", + "CMT_TOP_IMUX15_0", + "CMT_TOP_IMUX45_3", + "CMT_TOP_NW4A1_10", + "CMT_TOP_IMUX33_10", + "CMT_PHASER_OUT_CA_TESTIN10", + "CMT_TOP_SE4C0_6", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_LH1_9", + "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH10_4", + "CMT_TOP_IMUX32_3", + "CMT_TOP_SE4C2_7", + "CMT_PHASER_TOP_SYNC_BB", + "CMT_TOP_IMUX16_9", + "CMT_TOP_BYP5_1", + "CMT_TOP_IMUX3_11", + "CMT_TOP_WW2A1_7", + "CMT_PHASER_IN_DB_COUNTERLOADEN", + "CMT_TOP_IMUX17_5", + "CMT_TOP_BYP2_2", + "CMT_TOP_LH1_6", + "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "CMT_PHY_CONTROL_OBURSTPENDING0", + "CMT_TOP_SW4A1_11", + "CMT_TOP_IMUX12_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX13_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_NW2A1_9", + "CMT_TOP_SE2A3_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_EE4C0_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_NE4C2_0", + "CMT_TOP_IMUX1_7", + "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX21_5", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH12_3", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LH12_8", + "CMT_FREQ_BB_PREF_IN2", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_PHY_CONTROL_TESTINPUT13", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_CTRL0_8", + "CMT_PHASER_OUT_CA_TESTIN4", + "CMT_TOP_NW4A3_7", + "CMT_PHASER_OUT_CA_SYSCLK", + "CMT_TOP_NW4END3_0", + "CMT_TOP_NE2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_IMUX20_8", + "CMT_TOP_WW2END0_8", + "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "CMT_TOP_LH9_3", + "CMT_TOP_IMUX29_9", + "CMT_TOP_LH6_4", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_WW2A2_10", + "CMT_PHASER_IN_CA_STG1REGR3", + "CMT_TOP_MONITOR_P_3", + "CMT_PHASER_OUT_CA_COARSEINC", + "CMT_TOP_NE4C3_0", + "CMT_TOP_BYP6_5", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_WL1END0_6", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_IMUX15_6", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_IMUX36_2", + "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "CMT_TOP_FAN1_3", + "CMT_TOP_LH9_0", + "CMT_TOP_WL1END0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_PHASERD_DTSBUS1", + "CMT_TOP_WR1END3_6", + "CMT_PHY_CONTROL_IRANKC0", + "CMT_TOP_NE2A3_3", + "CMT_TOP_SW4A2_10", + "CMT_TOP_WR1END2_10", + "CMT_TOP_IMUX29_8", + "CMT_PHASER_IN_DB_STG1REGR8", + "CMT_TOP_IMUX26_6", + "CMT_TOP_FAN7_11", + "CMT_PHASER_UP_BUFMRCE_CE1", + "CMT_PHASER_OUT_DB_TESTIN2", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_IMUX29_0", + "CMT_TOP_WR1END2_0", + "CMT_PHASER_OUT_CA_RDENABLE", + "CMT_PHASER_IN_DB_ICLK", + "CMT_TOP_SW2A3_6", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX43_9", + "CMT_TOP_IMUX8_10", + "CMT_TOP_BYP3_3", + "CMT_TOP_WW2A2_3", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX44_0", + "CMT_TOP_WW4C1_1", + "CMT_PHASER_IN_DB_MEMREFCLK", + "CMT_TOP_EE4A1_7", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW2A1_3", + "CMT_TOP_IMUX39_5", + "CMT_TOP_LH1_0", + "CMT_TOP_IMUX28_5", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_NE2A1_7", + "CMT_TOP_IMUX41_10", + "CMT_TOP_WR1END3_5", + "CMT_TOP_IMUX37_10", + "CMT_TOP_IMUX23_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX15_5", + "CMT_PHASER_C_ICLKDIV_TOIOI", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_SW4A0_7", + "CMT_PHASER_IN_CA_STG1REGL2", + "CMT_TOP_LH12_4", + "CMT_TOP_WW4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_WW4A1_7", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX5_3", + "CMT_PHASER_IN_DB_TESTIN13", + "CMT_PHASER_OUT_DB_CTSBUS0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_LH7_7", + "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "CMT_TOP_WW4C0_7", + "CMT_PHASER_IN_DB_WRENABLE", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_IMUX39_11", + "CMT_TOP_BYP5_4", + "CMT_TOP_FAN4_3", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_FAN6_2", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH4_5", + "CMT_TOP_IMUX22_4", + "CMT_TOP_WR1END2_4", + "CMT_TOP_LH9_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_EE4C3_0", + "CMT_TOP_BYP4_9", + "CMT_TOP_NW4END2_11", + "CMT_TOP_NE4C1_6", + "CMT_TOP_BYP2_0", + "CMT_TOP_WW2A0_10", + "CMT_TOP_IMUX7_11", + "CMT_TOP_WW4END0_0", + "CMT_TOP_EE2A2_7", + "CMT_TOP_LH2_1", + "CMT_TOP_WW4END3_7", + "CMT_PHASER_OUT_CA_COARSEENABLE", + "CMT_PHY_CONTROL_PHYCTLWD5", + "CMT_PHASER_IN_CA_STG1REGR6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_EE2BEG0_9", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CMT_TOP_LH11_5", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_WW4C1_5", + "CMT_TOP_BYP5_8", + "CMT_TOP_WR1END2_11", + "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "CMT_PHY_CONTROL_MEMREFCLK", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_8", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_WL1END1_7", + "CMT_TOP_WL1END1_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_PHASER_IN_CA_COUNTERREADEN", + "CMT_TOP_NW4A3_6", + "CMT_TOP_LH6_7", + "CMT_PHASER_IN_DB_TESTIN4", + "CMT_TOP_WW4B1_8", + "CMT_TOP_WW4A3_0", + "CMT_TOP_FAN3_7", + "CMT_TOP_ER1BEG1_1", + "CMT_PHASER_IN_C_WRENABLE_FIFO", + "CMT_TOP_SW2A2_10", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_IMUX25_5", + "CMT_TOP_CLK0_4", + "CMT_PHY_CONTROL_TESTINPUT8", + "CMT_TOP_NW2A0_9", + "CMT_TOP_FAN5_3", + "CMT_TOP_EE4A1_4", + "CMT_TOP_IMUX31_6", + "CMT_TOP_NE2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_PHASER_REF_PWRDWN", + "CMT_TOP_IMUX38_7", + "CMT_PHASER_REF_TESTIN3", + "CMT_PHY_CONTROL_PCENABLECALIB1", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_PHASER_UP_BUFMRCE_CE0", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_ICLK_7", + "CMT_TOP_IMUX15_3", + "CMT_PHASER_REF_TESTIN4", + "CMT_PHASER_OUT_DB_TESTIN10", + "CMT_TOP_FAN1_9", + "CMT_TOP_FAN2_3", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_SW4A0_4", + "CMT_TOP_LH11_9", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_IMUX8_3", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_EE4C2_11", + "CMT_TOP_NE4C3_1", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CTRL0_3", + "CMT_TOP_FAN0_8", + "CMT_PHASER_IN_DB_ENSTG1", + "CMT_TOP_EE4C2_7", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_PHASER_OUT_DB_TESTIN15", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "PLL_CLK_FREQBB_REBUFOUT1", + "CMT_PHASER_IN_DB_TESTIN9", + "CMT_TOP_SW4A1_1", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_NW4END2_10", + "CMT_PHASER_IN_CA_SCANCLK", + "CMT_TOP_IMUX9_6", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX31_8", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX28_7", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_PHASER_IN_DB_STG1REGL4", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_SW2A3_7", + "CMT_TOP_LH4_9", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_NW2A3_9", + "CMT_TOP_EE4B3_4", + "CMT_TOP_SE4BEG1_1", + "CMT_PHASER_OUT_CA_OCLKDELAYED", + "CMT_PHY_CONTROL_TESTOUTPUT6", + "CMT_TOP_IMUX24_4", + "CMT_TOP_FAN6_6", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_IMUX25_2", + "CMT_TOP_BYP2_3", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_FAN4_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_NW4A1_3", + "CMT_TOP_IMUX35_4", + "CMT_TOP_WW2END3_10", + "CMT_TOP_IMUX41_5", + "CMT_TOP_NW4A1_8", + "CMT_TOP_IMUX10_6", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_LH12_6", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_BYP6_10", + "CMT_PHASERREF_PHASEROUT_C", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_BYP7_1", + "CMT_PHY_CONTROL_PHYCTLWD18", + "CMT_TOP_WW2A0_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_SW4A2_1", + "CMT_TOP_LH1_3", + "CMT_TOP_FAN0_5", + "CMT_TOP_EE2A1_8", + "CMT_TOP_WW4C3_7", + "CMT_TOP_LH2_3", + "CMT_TOP_FAN7_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_NW4A3_0", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "CMT_TOP_EE4B1_10", + "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CMT_PHASER_IN_CA_ENCALIB0", + "CMT_TOP_WW4END2_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX38_4", + "CMT_TOP_NE2A1_4", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_IMUX27_2", + "CMT_TOP_WW4C0_6", + "CMT_PHASER_OUT_DB_TESTOUT1", + "CMT_TOP_IMUX1_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_NE2A2_5", + "CMT_TOP_NW4A0_3", + "CMT_TOP_ICLKDIV_8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "CMT_PHY_CONTROL_AUXOUTPUT0", + "CMT_TOP_NW2A3_6", + "CMT_TOP_WW4END3_5", + "CMT_TOP_WW4B1_5", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX23_10", + "CMT_TOP_IMUX17_0", + "CMT_TOP_CLK0_2", + "CMT_TOP_EE4B3_2", + "CMT_PHASER_OUT_CA_COUNTERREADEN", + "CMT_TOP_IMUX31_5", + "CMT_TOP_FAN0_0", + "CMT_PHY_CONTROL_PHYCTLWD30", + "CMT_TOP_EE4C3_2", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX46_3", + "CMT_TOP_IMUX43_7", + "CMT_TOP_IMUX40_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_EE4A3_9", + "CMT_PHASER_OUT_CA_TESTIN8", + "CMT_TOP_WW4END3_6", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "CMT_TOP_FAN2_5", + "CMT_TOP_CLK0_6", + "CMT_TOP_IMUX10_5", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_PHASER_IN_C_ICLKDIV", + "CMT_TOP_WW2A3_8", + "CMT_TOP_NE4C1_8", + "CMT_TOP_EE4A1_1", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4C0_4", + "CMT_TOP_BYP0_6", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX12_4", + "CMT_TOP_LH10_3", + "CMT_TOP_LH3_2", + "CMT_TOP_EL1BEG3_7", + "CMT_PHASER_IN_CA_STG1INCDEC", + "CMT_PHY_CONTROL_TESTINPUT2", + "CMT_PHASER_OUT_CA_TESTOUT2", + "CMT_TOP_IMUX43_4", + "CMT_TOP_LH10_6", + "CMT_TOP_NE4C1_10", + "CMT_TOP_IMUX15_11", + "CMT_PHASER_IN_DB_STG1INCDEC", + "CMT_TOP_NE4C1_9", + "CMT_TOP_WW4B0_3", + "CMT_PHASERREF_PHASERIN_C", + "CMT_PHASER_OUT_C_OCLK1X_90", + "CMT_TOP_WW4C3_10", + "CMT_TOP_SE2A2_6", + "CMT_TOP_NW2A3_5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_WW4A2_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_IMUX38_11", + "CMT_TOP_SW4END2_9", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_PHASER_OUT_DB_FINEENABLE", + "CMT_PHASER_IN_CA_STG1REGR2", + "CMT_TOP_LH3_1", + "CMT_PHY_CONTROL_PHYCTLREADY", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END2_5", + "CMT_TOP_FAN0_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_IMUX42_11", + "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX4_5", + "CMT_TOP_BYP4_0", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LH4_4", + "CMT_TOP_LH3_9", + "CMT_PHASER_IN_DB_TESTOUT1", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_EL1BEG2_9", + "CMT_TOP_WW4C1_2", + "CMT_TOP_IMUX37_11", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_WR1END1_0", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_IMUX22_5", + "CMT_TOP_OCLK_3", + "CMT_TOP_IMUX23_5", + "CMT_PHASER_OUT_DB_TESTIN9", + "CMT_TOP_SW4END2_4", + "CMT_TOP_EE4A1_8", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW2END0_2", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_SE2A1_6", + "CMT_TOP_CTRL0_1", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END0_9", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_WW4B0_0", + "CMT_TOP_IMUX6_5", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_WW4B0_4", + "CMT_TOP_IMUX10_9", + "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_FREQ_PHASER_REFMUX_2", + "CMT_TOP_IMUX45_0", + "CMT_PHASER_OUT_DB_DTSBUS1", + "CMT_R_TOP_UPPER_B_CLKPLL0", + "CMT_TOP_IMUX45_10", + "CMT_PHASER_IN_CA_RCLK", + "CMT_TOP_IMUX39_1", + "CMT_TOP_WL1END1_8", + "CMT_PHY_CONTROL_OBURSTPENDING3", + "CMT_TOP_EE2A3_6", + "CMT_TOP_IMUX9_5", + "CMT_TOP_WW2END3_8", + "CMT_TOP_BYP4_10", + "CMT_TOP_IMUX17_9", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_IMUX23_4", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_FAN3_10", + "CMT_TOP_EE4B0_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_PHY_CONTROL_AUXOUTPUT1", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX42_9", + "CMT_TOP_EE2A2_6", + "CMT_TOP_IMUX25_3", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_PHASER_IN_CA_RANKSELPHY1", + "CMT_TOP_NW4A3_4", + "CMT_TOP_IMUX34_4", + "CMT_TOP_LH7_2", + "CMT_TOP_LH6_1", + "CMT_TOP_NW4END2_2", + "CMT_PHASER_IN_DB_STG1REGL2", + "CMT_TOP_LH1_2", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_PHASER_IN_CA_TESTIN1", + "CMT_TOP_IMUX13_2", + "CMT_TOP_WW4A0_8", + "CMT_TOP_FAN6_8", + "CMT_TOP_IMUX17_7", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_NW4A0_2", + "CMT_TOP_BYP6_6", + "CMT_PHASER_IN_CA_WRENABLE", + "CMT_PHASER_IN_CA_ICLK", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_PHY_CONTROL_INRANKB0", + "CMT_PHY_CONTROL_IRANKA1", + "CMT_TOP_SW4END1_7", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NW4END0_6", + "CMT_TOP_WR1END3_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_R_TOP_UPPER_B_CLKPLL6", + "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "CMT_TOP_NE2A3_7", + "CMT_TOP_IMUX3_7", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_TOP_BYP2_6", + "CMT_TOP_IMUX14_8", + "CMT_PHASER_IN_CA_RST", + "CMT_PHASER_IN_DB_TESTIN5", + "CMT_TOP_BYP0_3", + "CMT_PHASER_IN_D_WRENABLE_FIFO", + "CMT_TOP_NE4C0_0", + "CMT_TOP_NE4C2_10", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH6_11", + "CMT_TOP_FAN5_10", + "CMT_PHY_CONTROL_PHYCLK", + "CMT_PHASER_IN_DB_ENCALIB0", + "CMT_TOP_WW4END2_4", + "CMT_TOP_NW2A3_11", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_PHASER_OUT_DB_DQSBUS1", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_NW2A2_8", + "CMT_TOP_IMUX19_4", + "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "CMT_TOP_WW2END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_IMUX30_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX28_1", + "CMT_TOP_NW4A0_0", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_LH3_7", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX16_4", + "CMT_TOP_EE2A3_7", + "CMT_TOP_SE4C3_11", + "CMT_TOP_ICLK_9", + "CMT_PHASER_IN_CA_FINEINC", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_WW4A1_10", + "CMT_PHASER_UP_PHASERREF_BELOW1", + "CMT_TOP_WW2END0_0", + "CMT_PHY_CONTROL_PHYCTLWD16", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_WW4C3_11", + "CMT_TOP_BYP3_6", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_WW2A2_8", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_WW4B3_7", + "CMT_TOP_SW4END3_4", + "CMT_TOP_EE4C1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_BYP0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_WW4END1_7", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WW4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX5_0", + "CMT_PHASER_OUT_DB_SYSCLK", + "CMT_PHASER_IN_CA_STG1REGL5", + "CMT_TOP_WW4B3_10", + "CMT_PHASER_OUT_CA_TESTIN5", + "CMT_PHASER_IN_DB_ENCALIB1", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_WW2END3_9", + "CMT_PHY_CONTROL_TESTOUTPUT9", + "CMT_TOP_SW4END1_10", + "CMT_TOP_WW4B0_7", + "CMT_TOP_BYP3_7", + "CMT_TOP_EE2A3_11", + "CMT_TOP_LH6_5", + "CMT_TOP_IMUX28_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_WW4A3_5", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_EE2BEG2_0", + "CMT_PHASER_IN_D_RCLK3", + "CMT_TOP_WW4A0_11", + "CMT_TOP_WL1END0_3", + "CMT_TOP_WW4C0_2", + "CMT_TOP_IMUX0_7", + "CMT_PHASER_OUT_DB_SCANENB", + "CMT_TOP_WW4B1_0", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SW4END0_8", + "CMT_L_TOP_UPPER_B_CLKINT_2", + "CMT_TOP_IMUX8_1", + "CMT_TOP_WW4C2_10", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_IMUX34_6", + "CMT_PHASER_IN_DB_COUNTERREADEN", + "CMT_TOP_IMUX32_11", + "CMT_TOP_NE2A3_1", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_EE4B0_3", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A3_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_IMUX46_10", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ER1BEG2_5", + "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C0_5", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_BYP4_4", + "CMT_TOP_NW4A2_9", + "CMT_TOP_WR1END2_1", + "CMT_PHASER_IN_CA_PHASELOCKED", + "CMT_TOP_EE2BEG0_7", + "CMT_PHASER_IN_DB_STG1READ", + "CMT_TOP_IMUX16_1", + "CMT_TOP_NW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_FAN2_6", + "CMT_TOP_WR1END3_7", + "CMT_TOP_IMUX38_9", + "CMT_TOP_IMUX28_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_FAN5_7", + "CMT_PHASER_OUT_CA_SCANCLK", + "CMT_TOP_BYP7_10", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CMT_TOP_IMUX15_7", + "CMT_R_TOP_UPPER_B_CLKPLL3", + "CMT_TOP_IMUX30_9", + "CMT_TOP_LH8_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "CMT_TOP_EE4A3_5", + "CMT_PHASER_REF_TESTOUT0", + "CMT_PHASER_REF_TESTIN5", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_NE4C0_5", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_IMUX25_0", + "CMT_TOP_IMUX31_10", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_IMUX34_2", + "CMT_TOP_LH10_2", + "CMT_PHASER_OUT_DB_OCLK", + "CMT_TOP_LH12_0", + "CMT_TOP_FAN4_0", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_NW4A0_8", + "CMT_TOP_WW4A2_10", + "CMT_TOP_BYP3_0", + "CMT_TOP_IMUX2_1", + "CMT_PHY_CONTROL_INRANKC1", + "CMT_PHASER_IN_DB_STG1REGR5", + "CMT_PHASER_IN_CA_SELCALORSTG1", + "CMT_TOP_IMUX22_1", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_EE2A3_5", + "CMT_TOP_IMUX4_7", + "CMT_TOP_SE2A2_0", + "CMT_TOP_LH2_4", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SW4A3_6", + "CMT_TOP_NW4END1_5", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WR1END3_1", + "CMT_TOP_BYP1_0", + "CMT_PHY_CONTROL_TESTINPUT9", + "CMT_TOP_WW2A0_6", + "CMT_TOP_SE2A3_0", + "CMT_PHASER_IN_DB_STG1REGL7", + "CMT_TOP_IMUX35_9", + "CMT_TOP_SW4END2_5", + "CMT_TOP_SE4C3_5", + "CMT_TOP_LH4_1", + "CMT_TOP_NW4A0_9", + "CMT_TOP_SW4A1_6", + "CMT_TOP_SW2A2_0", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE4C3_10", + "PLL_CLK_FREQBB_REBUFOUT3", + "CMT_TOP_SW4END0_7", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_IMUX13_5", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EE4A2_4", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_EL1BEG2_6", + "CMT_R_TOP_UPPER_B_CLKIN2", + "CMT_TOP_LH2_8", + "CMT_TOP_SE2A3_1", + "CMT_TOP_IMUX2_6", + "CMT_PHY_CONTROL_ECALIB1", + "CMT_TOP_IMUX3_0", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4C2_4", + "CMT_TOP_NE4BEG1_5", + "CMT_PHASER_IN_CA_DQSFOUND", + "CMT_PHASER_IN_CA_STG1OVERFLOW", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_ER1BEG0_6", + "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "CMT_TOP_EE2A3_2", + "CMT_TOP_IMUX14_10", + "CMT_TOP_IMUX23_8", + "CMT_TOP_WW4A3_8", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LH10_9", + "CMT_PHASER_OUT_CA_SCANIN", + "CMT_TOP_FAN1_0", + "CMT_TOP_LH4_10", + "CMT_PHASER_IN_CA_TESTOUT1", + "CMT_TOP_IMUX0_2", + "CMT_R_TOP_UPPER_B_CLKFBIN", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_LH5_3", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_NW2A0_3", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX18_1", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_SW4END3_10", + "CMT_TOP_FAN2_10", + "CMT_PHASER_REF_TESTOUT6", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_WR1END1_1", + "CMT_TOP_SW2A2_7", + "CMT_TOP_ICLK_5", + "CMT_TOP_SW2A0_7", + "CMT_PHASER_OUT_DB_OSERDESRST", + "CMT_TOP_FAN6_5", + "CMT_TOP_ER1BEG0_7", + "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "CMT_TOP_NW4A2_0", + "CMT_TOP_WW2A1_2", + "CMT_TOP_FAN4_1", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_SE4C0_11", + "CMT_PHASER_OUT_DB_TESTIN12", + "CMT_TOP_WW2END0_6", + "CMT_TOP_CTRL1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "CMT_PHASER_OUT_CA_DTSBUS1", + "CMT_TOP_WW4B1_2", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_FAN6_3", + "CMT_TOP_WL1END1_11", + "CMT_TOP_SW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_LH11_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_SE4C2_6", + "CMT_TOP_FAN5_11", + "CMT_TOP_SW4END1_6", + "CMT_PHY_CONTROL_AUXOUTPUT2", + "CMT_TOP_IMUX2_2", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW2END0_5", + "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "CMT_TOP_LH6_0", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_PHASER_IN_CA_RANKSEL0", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX29_3", + "CMT_PHY_CONTROL_IBURSTPENDING1", + "CMT_PHY_CONTROL_TESTINPUT1", + "CMT_TOP_WL1END1_6", + "CMT_TOP_NW4A2_5", + "CMT_TOP_IMUX6_9", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX9_2", + "CMT_TOP_IMUX19_5", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_EE4B3_9", + "CMT_TOP_EE4A1_9", + "CMT_PHY_CONTROL_WRITECALIBENABLE", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_NE2A3_4", + "CMT_TOP_EE2A0_11", + "CMT_TOP_IMUX40_3", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_ICLK_3", + "CMT_TOP_SW4END0_6", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_IMUX41_6", + "CMT_PHASER_OUT_CA_OCLKDIV", + "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "CMT_TOP_EE4A0_11", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_IMUX46_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_EE4C0_2", + "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX11_3", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_LH5_8", + "CMT_TOP_WW4A2_8", + "CMT_TOP_WW4A3_4", + "CMT_TOP_LH11_4", + "CMT_TOP_IMUX34_0", + "CMT_TOP_BYP1_6", + "CMT_TOP_WW4B0_1", + "CMT_PHY_CONTROL_TESTINPUT15", + "CMT_TOP_IMUX2_4", + "CMT_TOP_SW4A1_8", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_PHASER_IN_D_ICLKDIV", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_WL1END3_10", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX29_7", + "CMT_TOP_IMUX33_3", + "CMT_TOP_SW2A2_3", + "CMT_TOP_IMUX44_8", + "CMT_TOP_IMUX32_7", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SW2A3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX32_1", + "CMT_TOP_LH8_1", + "CMT_TOP_SE2A2_1", + "CMT_TOP_WW4C3_3", + "CMT_TOP_SE4C3_1", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX26_3", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_IMUX24_6", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_EE4BEG2_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "CMT_TOP_SE4BEG0_11", + "CMT_PHY_CONTROL_PHYCTLWD14", + "CMT_TOP_NE2A2_10", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_IMUX17_1", + "CMT_TOP_EE4C3_7", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX32_2", + "CMT_PHASER_IN_DB_TESTIN8", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_ICLK_6", + "CMT_PHASER_IN_CA_RSTDQSFIND", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_SE2A3_7", + "CMT_PHASER_IN_CA_TESTOUT0", + "CMT_TOP_BYP6_9", + "CMT_TOP_EE4B2_3", + "CMT_TOP_SE4BEG0_6", + "CMT_PHY_CONTROL_SYNCIN", + "CMT_TOP_WW2A0_8", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX0_3", + "CMT_TOP_IMUX30_10", + "CMT_TOP_IMUX27_10", + "CMT_TOP_WW4END0_9", + "CMT_TOP_SW4END0_5", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_SW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_PHASER_IN_DB_TESTIN7", + "CMT_TOP_CTRL1_1", + "CMT_TOP_SE4BEG0_8", + "CMT_PHASER_IN_DB_STG1REGL8", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_IMUX12_11", + "CMT_PHY_CONTROL_IRANKB0", + "CMT_TOP_WW4A3_10", + "CMT_TOP_FAN3_6", + "CMT_TOP_LH5_4", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_IMUX47_3", + "CMT_TOP_SW4A3_5", + "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_EE2A1_4", + "CMT_TOP_NW4END1_4", + "CMT_TOP_IMUX25_1", + "CMT_TOP_LH5_11", + "CMT_TOP_FAN1_10", + "CMT_TOP_NW4END0_11", + "CMT_TOP_EE4C0_11", + "CMT_PHASER_OUT_DB_TESTIN11", + "CMT_TOP_IMUX25_8", + "CMT_TOP_EE4A1_3", + "CMT_TOP_NW2A3_7", + "CMT_TOP_IMUX30_11", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_EE4BEG3_0", + "CMT_PHASER_OUT_DB_TESTIN8", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_EE2A1_2", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WW4C2_8", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX26_11", + "CMT_TOP_NE2A2_1", + "CMT_TOP_CTRL1_8", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NW4END3_3", + "CMT_TOP_WW4B2_2", + "CMT_TOP_IMUX18_3", + "CMT_PHASER_IN_CA_STG1REGL3", + "CMT_TOP_IMUX16_11", + "CMT_TOP_WW4A0_3", + "CMT_TOP_LH5_1", + "CMT_TOP_WL1END0_4", + "CMT_TOP_IMUX44_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SE2A2_3", + "CMT_PHASER_IN_DB_STG1REGR2", + "CMT_TOP_SE4C2_4", + "CMT_TOP_FAN6_10", + "CMT_TOP_EE4C2_0", + "CMT_PHY_CONTROL_IRANKB1", + "CMT_TOP_NE4C1_3", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX18_8", + "CMT_TOP_BYP3_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_CLK1_5", + "CMT_TOP_SW2A0_4", + "CMT_TOP_IMUX0_10", + "CMT_PHY_CONTROL_INRANKA0", + "CMT_PHY_CONTROL_TESTOUTPUT5", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_IMUX13_7", + "CMT_TOP_NE4C2_2", + "CMT_TOP_IMUX10_4", + "CMT_TOP_EE4A1_11", + "CMT_PHASER_IN_DB_ISERDESRST", + "CMT_TOP_EE2A0_6", + "CMT_TOP_NW4END1_0", + "CMT_TOP_LH5_10", + "CMT_TOP_IMUX46_7", + "CMT_PHASER_IN_DB_SYSCLK", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE2A2_8", + "CMT_TOP_OCLK_9", + "CMT_TOP_NW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_WW4END3_9", + "CMT_TOP_EE4C3_1", + "CMT_TOP_IMUX14_11", + "CMT_PHASER_IN_CA_SCANOUT", + "CMT_TOP_WW4C1_9", + "CMT_TOP_IMUX0_9", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_WL1END3_9", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_IMUX13_6", + "CMT_TOP_EE4A2_6", + "CMT_TOP_IMUX20_0", + "CMT_PHY_CONTROL_INRANKB1", + "CMT_TOP_WW4B2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_PHASER_IN_DB_STG1REGL1", + "CMT_TOP_WR1END2_2", + "CMT_TOP_WW2A0_1", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_EE2BEG0_5", + "CMT_PHY_CONTROL_PHYCTLEMPTY", + "CMT_TOP_WW4B0_8", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LH5_7", + "CMT_TOP_IMUX21_9", + "CMT_PHY_CONTROL_PHYCTLWD12", + "CMT_TOP_IMUX35_1", + "CMT_PHASER_IN_DB_STG1REGR0", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_PHY_CONTROL_PHYCTLWD25", + "CMT_TOP_NW2A3_8", + "CMT_TOP_SE2A3_4", + "CMT_TOP_SW4END3_9", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NE4C0_10", + "CMT_TOP_IMUX26_5", + "CMT_TOP_BYP4_11", + "CMT_TOP_IMUX25_6", + "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "CMT_TOP_BYP0_2", + "CMT_TOP_BYP6_7", + "CMT_PHASER_IN_CA_TESTIN12", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_NE2A1_8", + "CMT_TOP_WW4A0_10", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_5", + "CMT_TOP_WW4B2_0", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_PHASER_IN_CA_BURSTPENDING", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_PHASER_IN_DB_SCANMODEB", + "CMT_TOP_WL1END3_0", + "CMT_TOP_WW4END0_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_NW4END0_1", + "CMT_TOP_LH6_6", + "CMT_TOP_NE4C3_5", + "CMT_PHY_CONTROL_TESTINPUT11", + "CMT_PHY_CONTROL_PHYCTLWD19", + "CMT_TOP_NW4END0_8", + "CMT_TOP_IMUX39_0", + "CMT_TOP_WW4END2_0", + "CMT_TOP_WW4B3_4", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_PHY_CONTROL_AUXOUTPUT3", + "CMT_TOP_IMUX9_0", + "CMT_PHY_CONTROL_PHYCTLWD13", + "CMT_PHASER_REF_TESTOUT4", + "CMT_TOP_FAN2_0", + "CMT_PHY_CONTROL_TESTOUTPUT2", + "CMT_TOP_IMUX29_11", + "CMT_TOP_IMUX30_5", + "CMT_TOP_IMUX8_9", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_NW4END2_5", + "CMT_TOP_NE4C0_7", + "CMT_TOP_WW2END2_4", + "CMT_PHASER_IN_DB_TESTIN6", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_WL1END3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NW2A0_2", + "CMT_TOP_IMUX17_6", + "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "CMT_TOP_SE2A1_2", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_IMUX7_0", + "CMT_TOP_IMUX20_2", + "CMT_TOP_LH8_7", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_WW4A2_5", + "CMT_TOP_NE4C1_11", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_OCLK_6", + "CMT_TOP_IMUX18_10", + "CMT_PHY_CONTROL_READCALIBENABLE", + "CMT_TOP_BYP4_7", + "CMT_PHASER_IN_CA_STG1REGR8", + "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "CMT_TOP_BYP0_5", + "CMT_TOP_SE2A2_4", + "CMT_TOP_SE4C2_1", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_NW4END3_4", + "CMT_TOP_IMUX40_11", + "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "CMT_TOP_LH9_8", + "CMT_PHASER_IN_CA_DIVIDERST", + "CMT_TOP_LH9_11", + "CMT_TOP_NE2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX28_11", + "CMT_PHASER_IN_CA_TESTIN0", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_LH3_10", + "CMT_TOP_IMUX42_7", + "CMT_TOP_IMUX5_10", + "CMT_TOP_WL1END3_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_EE2A3_1", + "CMT_TOP_IMUX2_10", + "CMT_TOP_SE2A0_6", + "CMT_TOP_NE2A2_4", + "CMT_PHASER_OUT_CA_TESTIN2", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_SE4C1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "CMT_TOP_MONITOR_P_2", + "CMT_PHASER_IN_DB_TESTIN0", + "CMT_TOP_IMUX41_4", + "CMT_TOP_WL1END0_1", + "CMT_PHASER_C_OCLKDIV_TOIOI", + "CMT_TOP_NW4END2_4", + "CMT_TOP_FAN5_1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_IMUX20_10", + "CMT_PHASER_IN_CA_TESTOUT3", + "CMT_TOP_NE2A2_11", + "CMT_PHASER_OUT_CA_TESTIN1", + "CMT_TOP_FAN5_2", + "CMT_TOP_SW2A3_9", + "CMT_TOP_NW2A1_1", + "CMT_TOP_FAN1_1", + "CMT_TOP_IMUX5_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "CMT_TOP_IMUX11_11", + "CMT_TOP_NE2A1_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "CMT_TOP_CLK1_0", + "CMT_TOP_SW4END1_11", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_R_TOP_UPPER_B_CLKIN1", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_IMUX28_9", + "CMT_TOP_NW4A1_4", + "CMT_TOP_NE4C2_5", + "CMT_TOP_WW4B2_8", + "CMT_TOP_SE4BEG1_3", + "CMT_PHASER_IN_CA_RANKSELPHY0", + "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_WW4B2_6", + "CMT_TOP_WW2END1_11", + "CMT_TOP_IMUX19_0", + "CMT_TOP_LH3_3", + "CMT_TOP_IMUX38_5", + "CMT_PHY_CONTROL_SCANENABLEN", + "CMT_TOP_IMUX31_2", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_LH4_2", + "CMT_TOP_SE2A0_11", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH12_9", + "CMT_TOP_SW2A0_0", + "CMT_PHY_CONTROL_PHYCTLWD8", + "CMT_TOP_SW2A0_11", + "CMT_TOP_WW4A3_7", + "CMT_PHY_CONTROL_PHYCTLWD3", + "CMT_TOP_BYP5_10", + "CMT_TOP_LH12_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_PHASER_OUT_CA_EDGEADV", + "CMT_TOP_WW2A0_4", + "CMT_TOP_SE4BEG2_2", + "CMT_PHASER_IN_DB_RANKSELPHY1", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_IMUX30_1", + "CMT_PHASER_OUT_CA_TESTOUT1", + "CMT_TOP_IMUX0_1", + "CMT_TOP_IMUX39_3", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_FAN6_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_10", + "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "CMT_TOP_NE2A2_9", + "CMT_TOP_EE4B1_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_NW4END0_10", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "CMT_TOP_OCLKDIV_2", + "CMT_PHASER_IN_DB_ICLKDIV", + "CMT_TOP_IMUX44_1", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX29_1", + "CMT_TOP_FAN6_11", + "CMT_TOP_NW4A0_1" + ], + "tile_type": "CMT_TOP_L_UPPER_B", + "sites": [ + { + "site_pins": { + "TESTOUT3": "CMT_PHASER_REF_TESTOUT3", + "TESTIN3": "CMT_PHASER_REF_TESTIN3", + "TESTOUT1": "CMT_PHASER_REF_TESTOUT1", + "TESTOUT5": "CMT_PHASER_REF_TESTOUT5", + "TESTOUT6": "CMT_PHASER_REF_TESTOUT6", + "TESTIN7": "CMT_PHASER_REF_TESTIN7", + "TESTIN5": "CMT_PHASER_REF_TESTIN5", + "TESTIN4": "CMT_PHASER_REF_TESTIN4", + "TESTIN0": "CMT_PHASER_REF_TESTIN0", + "TESTOUT2": "CMT_PHASER_REF_TESTOUT2", + "TESTIN1": "CMT_PHASER_REF_TESTIN1", + "LOCKED": "CMT_PHASER_REF_LOCKED", + "TESTOUT0": "CMT_PHASER_REF_TESTOUT0", + "TMUXOUT": "CMT_PHASER_REF_TMUXOUT", + "TESTIN2": "CMT_PHASER_REF_TESTIN2", + "TESTOUT7": "CMT_PHASER_REF_TESTOUT7", + "TESTOUT4": "CMT_PHASER_REF_TESTOUT4", + "PWRDWN": "CMT_PHASER_REF_PWRDWN", + "CLKIN": "CMT_PHASER_REF_CLKIN", + "TESTIN6": "CMT_PHASER_REF_TESTIN6", + "CLKOUT": "CMT_PHASER_REF_CLKOUT", + "RST": "CMT_PHASER_REF_RST" + }, + "type": "PHASER_REF", + "prefix": "PHASER_REF", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "PHYCTLWD4": "CMT_PHY_CONTROL_PHYCTLWD4", + "MEMREFCLK": "CMT_PHY_CONTROL_MEMREFCLK", + "TESTSELECT2": "CMT_PHY_CONTROL_TESTSELECT2", + "PHYCTLWD13": "CMT_PHY_CONTROL_PHYCTLWD13", + "RESET": "CMT_PHY_CONTROL_RESET", + "TESTINPUT3": "CMT_PHY_CONTROL_TESTINPUT3", + "PHYCTLWRENABLE": "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "PHYCTLWD24": "CMT_PHY_CONTROL_PHYCTLWD24", + "PHYCTLWD16": "CMT_PHY_CONTROL_PHYCTLWD16", + "INRANKC0": "CMT_PHY_CONTROL_INRANKC0", + "TESTINPUT8": "CMT_PHY_CONTROL_TESTINPUT8", + "PHYCTLWD21": "CMT_PHY_CONTROL_PHYCTLWD21", + "PHYCTLWD28": "CMT_PHY_CONTROL_PHYCTLWD28", + "TESTOUTPUT9": "CMT_PHY_CONTROL_TESTOUTPUT9", + "INBURSTPENDING3": "CMT_PHY_CONTROL_INBURSTPENDING3", + "PHYCTLALMOSTFULL": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "PHYCTLWD2": "CMT_PHY_CONTROL_PHYCTLWD2", + "TESTINPUT4": "CMT_PHY_CONTROL_TESTINPUT4", + "TESTOUTPUT13": "CMT_PHY_CONTROL_TESTOUTPUT13", + "PHYCTLWD8": "CMT_PHY_CONTROL_PHYCTLWD8", + "TESTOUTPUT7": "CMT_PHY_CONTROL_TESTOUTPUT7", + "TESTINPUT12": "CMT_PHY_CONTROL_TESTINPUT12", + "INRANKA1": "CMT_PHY_CONTROL_INRANKA1", + "SYNCIN": "CMT_PHY_CONTROL_SYNCIN", + "READCALIBENABLE": "CMT_PHY_CONTROL_READCALIBENABLE", + "PHYCTLWD22": "CMT_PHY_CONTROL_PHYCTLWD22", + "INBURSTPENDING2": "CMT_PHY_CONTROL_INBURSTPENDING2", + "PHYCTLMSTREMPTY": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "PHYCTLWD3": "CMT_PHY_CONTROL_PHYCTLWD3", + "PHYCTLWD1": "CMT_PHY_CONTROL_PHYCTLWD1", + "TESTINPUT0": "CMT_PHY_CONTROL_TESTINPUT0", + "TESTOUTPUT12": "CMT_PHY_CONTROL_TESTOUTPUT12", + "PLLLOCK": "CMT_PHY_CONTROL_PLLLOCK", + "TESTOUTPUT10": "CMT_PHY_CONTROL_TESTOUTPUT10", + "TESTOUTPUT5": "CMT_PHY_CONTROL_TESTOUTPUT5", + "PHYCTLWD19": "CMT_PHY_CONTROL_PHYCTLWD19", + "TESTINPUT14": "CMT_PHY_CONTROL_TESTINPUT14", + "PHYCTLWD31": "CMT_PHY_CONTROL_PHYCTLWD31", + "AUXOUTPUT3": "CMT_PHY_CONTROL_AUXOUTPUT3", + "TESTOUTPUT0": "CMT_PHY_CONTROL_TESTOUTPUT0", + "REFDLLLOCK": "CMT_PHY_CONTROL_REFDLLLOCK", + "WRITECALIBENABLE": "CMT_PHY_CONTROL_WRITECALIBENABLE", + "PHYCTLEMPTY": "CMT_PHY_CONTROL_PHYCTLEMPTY", + "TESTINPUT15": "CMT_PHY_CONTROL_TESTINPUT15", + "INRANKD0": "CMT_PHY_CONTROL_INRANKD0", + "PHYCTLWD11": "CMT_PHY_CONTROL_PHYCTLWD11", + "OUTBURSTPENDING2": "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "PHYCTLWD29": "CMT_PHY_CONTROL_PHYCTLWD29", + "SCANENABLEN": "CMT_PHY_CONTROL_SCANENABLEN", + "TESTINPUT9": "CMT_PHY_CONTROL_TESTINPUT9", + "INRANKA0": "CMT_PHY_CONTROL_INRANKA0", + "PHYCTLWD25": "CMT_PHY_CONTROL_PHYCTLWD25", + "TESTINPUT11": "CMT_PHY_CONTROL_TESTINPUT11", + "TESTOUTPUT8": "CMT_PHY_CONTROL_TESTOUTPUT8", + "AUXOUTPUT0": "CMT_PHY_CONTROL_AUXOUTPUT0", + "TESTINPUT1": "CMT_PHY_CONTROL_TESTINPUT1", + "PHYCTLWD9": "CMT_PHY_CONTROL_PHYCTLWD9", + "PHYCTLWD17": "CMT_PHY_CONTROL_PHYCTLWD17", + "OUTBURSTPENDING0": "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "TESTSELECT1": "CMT_PHY_CONTROL_TESTSELECT1", + "INBURSTPENDING1": "CMT_PHY_CONTROL_INBURSTPENDING1", + "PHYCTLWD20": "CMT_PHY_CONTROL_PHYCTLWD20", + "PCENABLECALIB0": "CMT_PHY_CONTROL_PCENABLECALIB0", + "PHYCTLWD6": "CMT_PHY_CONTROL_PHYCTLWD6", + "PHYCTLWD15": "CMT_PHY_CONTROL_PHYCTLWD15", + "TESTINPUT13": "CMT_PHY_CONTROL_TESTINPUT13", + "TESTOUTPUT11": "CMT_PHY_CONTROL_TESTOUTPUT11", + "TESTOUTPUT6": "CMT_PHY_CONTROL_TESTOUTPUT6", + "PHYCTLWD14": "CMT_PHY_CONTROL_PHYCTLWD14", + "PHYCTLWD12": "CMT_PHY_CONTROL_PHYCTLWD12", + "TESTOUTPUT3": "CMT_PHY_CONTROL_TESTOUTPUT3", + "TESTOUTPUT2": "CMT_PHY_CONTROL_TESTOUTPUT2", + "TESTINPUT2": "CMT_PHY_CONTROL_TESTINPUT2", + "TESTOUTPUT1": "CMT_PHY_CONTROL_TESTOUTPUT1", + "PHYCLK": "CMT_PHY_CONTROL_PHYCLK", + "TESTINPUT10": "CMT_PHY_CONTROL_TESTINPUT10", + "TESTOUTPUT14": "CMT_PHY_CONTROL_TESTOUTPUT14", + "INRANKD1": "CMT_PHY_CONTROL_INRANKD1", + "PHYCTLWD10": "CMT_PHY_CONTROL_PHYCTLWD10", + "TESTOUTPUT15": "CMT_PHY_CONTROL_TESTOUTPUT15", + "PHYCTLREADY": "CMT_PHY_CONTROL_PHYCTLREADY", + "PHYCTLWD23": "CMT_PHY_CONTROL_PHYCTLWD23", + "PHYCTLWD27": "CMT_PHY_CONTROL_PHYCTLWD27", + "PHYCTLWD30": "CMT_PHY_CONTROL_PHYCTLWD30", + "TESTSELECT0": "CMT_PHY_CONTROL_TESTSELECT0", + "PHYCTLFULL": "CMT_PHY_CONTROL_PHYCTLFULL", + "TESTINPUT6": "CMT_PHY_CONTROL_TESTINPUT6", + "TESTOUTPUT4": "CMT_PHY_CONTROL_TESTOUTPUT4", + "INRANKB1": "CMT_PHY_CONTROL_INRANKB1", + "INBURSTPENDING0": "CMT_PHY_CONTROL_INBURSTPENDING0", + "AUXOUTPUT2": "CMT_PHY_CONTROL_AUXOUTPUT2", + "PHYCTLWD5": "CMT_PHY_CONTROL_PHYCTLWD5", + "INRANKC1": "CMT_PHY_CONTROL_INRANKC1", + "AUXOUTPUT1": "CMT_PHY_CONTROL_AUXOUTPUT1", + "PCENABLECALIB1": "CMT_PHY_CONTROL_PCENABLECALIB1", + "OUTBURSTPENDING1": "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "PHYCTLWD7": "CMT_PHY_CONTROL_PHYCTLWD7", + "INRANKB0": "CMT_PHY_CONTROL_INRANKB0", + "PHYCTLWD0": "CMT_PHY_CONTROL_PHYCTLWD0", + "PHYCTLWD18": "CMT_PHY_CONTROL_PHYCTLWD18", + "OUTBURSTPENDING3": "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "TESTINPUT5": "CMT_PHY_CONTROL_TESTINPUT5", + "TESTINPUT7": "CMT_PHY_CONTROL_TESTINPUT7", + "PHYCTLWD26": "CMT_PHY_CONTROL_PHYCTLWD26" + }, + "type": "PHY_CONTROL", + "prefix": "PHY_CONTROL", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", + "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", + "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", + "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", + "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", + "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", + "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", + "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", + "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", + "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", + "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", + "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", + "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", + "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", + "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", + "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", + "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", + "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", + "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", + "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", + "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", + "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", + "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", + "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", + "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", + "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "OCLK": "CMT_PHASER_OUT_CA_OCLK", + "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", + "RST": "CMT_PHASER_OUT_CA_RST", + "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", + "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", + "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", + "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", + "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", + "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", + "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", + "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", + "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", + "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", + "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE" + }, + "type": "PHASER_OUT_PHY", + "prefix": "PHASER_OUT_PHY", + "name": "X0Y5", + "x_coord": 0, + "y_coord": 5 + }, + { + "site_pins": { + "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", + "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", + "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", + "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", + "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", + "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", + "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", + "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", + "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", + "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", + "RCLK": "CMT_PHASER_IN_CA_RCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", + "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", + "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", + "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", + "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", + "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", + "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", + "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", + "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "STG1READ": "CMT_PHASER_IN_CA_STG1READ", + "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", + "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", + "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", + "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", + "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", + "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", + "SCANENB": "CMT_PHASER_IN_CA_SCANENB", + "FINEINC": "CMT_PHASER_IN_CA_FINEINC", + "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", + "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", + "ICLK": "CMT_PHASER_IN_CA_ICLK", + "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", + "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", + "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", + "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", + "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", + "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", + "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", + "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", + "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", + "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", + "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", + "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", + "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", + "RST": "CMT_PHASER_IN_CA_RST", + "SCANIN": "CMT_PHASER_IN_CA_SCANIN", + "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", + "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", + "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", + "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", + "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", + "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", + "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", + "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", + "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", + "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", + "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", + "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", + "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", + "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", + "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", + "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", + "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", + "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", + "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", + "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST" + }, + "type": "PHASER_IN_PHY", + "prefix": "PHASER_IN_PHY", + "name": "X0Y5", + "x_coord": 0, + "y_coord": 5 + }, + { + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", + "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", + "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", + "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", + "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", + "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", + "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", + "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", + "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", + "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", + "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", + "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", + "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", + "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", + "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", + "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", + "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", + "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", + "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", + "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", + "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", + "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", + "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", + "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", + "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", + "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "OCLK": "CMT_PHASER_OUT_DB_OCLK", + "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", + "RST": "CMT_PHASER_OUT_DB_RST", + "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", + "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", + "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", + "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", + "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", + "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", + "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", + "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", + "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", + "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", + "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE" + }, + "type": "PHASER_OUT_PHY", + "prefix": "PHASER_OUT_PHY", + "name": "X0Y6", + "x_coord": 0, + "y_coord": 6 + }, + { + "site_pins": { + "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", + "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", + "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", + "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", + "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", + "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", + "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", + "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", + "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", + "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", + "RCLK": "CMT_PHASER_IN_DB_RCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", + "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", + "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", + "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", + "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", + "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", + "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", + "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", + "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "STG1READ": "CMT_PHASER_IN_DB_STG1READ", + "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", + "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", + "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", + "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", + "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", + "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", + "SCANENB": "CMT_PHASER_IN_DB_SCANENB", + "FINEINC": "CMT_PHASER_IN_DB_FINEINC", + "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", + "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", + "ICLK": "CMT_PHASER_IN_DB_ICLK", + "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", + "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", + "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", + "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", + "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", + "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", + "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", + "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", + "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", + "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", + "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", + "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", + "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", + "RST": "CMT_PHASER_IN_DB_RST", + "SCANIN": "CMT_PHASER_IN_DB_SCANIN", + "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", + "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", + "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", + "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", + "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", + "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", + "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", + "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", + "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", + "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", + "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", + "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", + "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", + "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", + "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", + "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", + "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", + "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", + "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", + "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST" + }, + "type": "PHASER_IN_PHY", + "prefix": "PHASER_IN_PHY", + "name": "X0Y6", + "x_coord": 0, + "y_coord": 6 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_TOP_L_UPPER_T.json b/artix7/tile_type_CMT_TOP_L_UPPER_T.json index 6d92adc..1206109 100644 --- a/artix7/tile_type_CMT_TOP_L_UPPER_T.json +++ b/artix7/tile_type_CMT_TOP_L_UPPER_T.json @@ -1,4422 +1,4422 @@ { - "wires": [ - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_EE2A0_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_IMUX44_11", - "CMT_TOP_BYP5_2", - "CMT_TOP_EE2A3_5", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX19_0", - "CMT_TOP_LH11_4", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2END3_7", - "CMT_TOP_BYP6_0", - "CMT_TOP_CTRL1_12", - "CMT_TOP_NW2A2_9", - "CMT_TOP_EE4C1_11", - "CMT_TOP_NE2A1_8", - "CMT_TOP_IMUX44_1", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_IMUX39_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_IMUX44_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", - "CMT_TOP_NW2A0_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_NW4A0_2", - "CMT_TOP_WW2END0_8", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SE4BEG1_8", - "CMT_PLL_PHASERD_CTSBUS1", - "CMT_TOP_WW4A2_2", - "CMT_TOP_IMUX23_0", - "CMT_TOP_WW4C0_8", - "CMT_TOP_BYP6_1", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_SE2A0_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_SW2A2_1", - "CMT_TOP_FAN0_1", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_WW4END0_6", - "CMT_TOP_SW2A1_4", - "CMT_TOP_WW4A1_12", - "CMT_TOP_EE2A2_10", - "CMT_TOP_NW4END2_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", - "CMT_TOP_LH6_12", - "CMT_TOP_SE2A0_12", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_EE4B1_10", - "CMT_TOP_BYP5_3", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_WW4B0_10", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_WW4C2_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_SW4A2_12", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX14_3", - "CMT_TOP_BYP7_6", - "CMT_TOP_NW2A2_8", - "CMT_TOP_SE2A1_0", - "CMT_TOP_CTRL1_4", - "CMT_TOP_ICLK_11", - "CMT_TOP_IMUX0_0", - "CMT_TOP_FAN7_11", - "CMT_TOP_IMUX15_11", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_NW4END1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_EE4C0_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_IMUX10_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_NE4C0_0", - "CMT_TOP_EE2A1_11", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_LH11_12", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_SW2A2_12", - "CMT_TOP_WW4END0_3", - "CMT_TOP_IMUX28_9", - "CMT_TOP_NE4C3_6", - "CMT_TOP_LH9_1", - "CMT_TOP_EE4A3_1", - "CMT_TOP_WW2A0_6", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", - "CMT_TOP_IMUX10_4", - "CMT_TOP_BYP0_1", - "CMT_TOP_NE2A0_4", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX19_10", - "CMT_TOP_IMUX45_6", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_LH10_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_R_UPPER_T_PLLE2_RST", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_WW4B3_11", - "CMT_TOP_NW4A3_1", - "CMT_TOP_EE4A2_6", - "CMT_TOP_WL1END0_10", - "CMT_TOP_SW2A3_4", - "CMT_TOP_IMUX41_11", - "CMT_TOP_OCLK_2", - "CMT_TOP_SE4C3_11", - "CMT_TOP_EE4B2_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "CMT_TOP_SE2A0_2", - "CMT_TOP_IMUX14_12", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LH11_7", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX12_6", - "CMT_TOP_SW4END3_6", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_WW2END1_1", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_IMUX29_11", - "CMT_TOP_WL1END2_5", - "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_WR1END1_8", - "CMT_TOP_IMUX12_5", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX39_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX10_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_IMUX5_8", - "CMT_TOP_EE4B3_8", - "CMT_TOP_WW2A1_1", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX2_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_SW2A2_11", - "CMT_TOP_IMUX47_5", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_WW4B1_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_WR1END2_11", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX6_6", - "CMT_TOP_SW4END1_0", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX30_10", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_L_UPPER_T_CLKPLL7", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_WL1END3_6", - "CMT_TOP_SE2A2_0", - "CMT_TOP_IMUX27_0", - "CMT_TOP_SE2A2_8", - "CMT_TOP_L_UPPER_T_CLKPLL4", - "CMT_TOP_IMUX26_10", - "CMT_TOP_WW2END2_7", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_WR1END3_7", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_IMUX39_9", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_EE4B3_12", - "CMT_TOP_LH11_8", - "CMT_TOP_WW4END2_4", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "CMT_TOP_EE2A3_12", - "CMT_TOP_WW4A0_8", - "CMT_TOP_LH1_6", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX17_6", - "CMT_TOP_EE2A0_10", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_IMUX37_11", - "CMT_TOP_EE4B2_9", - "CMT_TOP_SE4C1_10", - "CMT_TOP_LH5_5", - "CMT_TOP_L_UPPER_T_CLKPLL1", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_EE2A2_5", - "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "CMT_TOP_LH4_8", - "CMT_TOP_IMUX45_1", - "CMT_TOP_SW4A0_4", - "CMT_TOP_FAN2_4", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX19_5", - "CMT_TOP_EE4B1_0", - "CMT_TOP_NW4END3_10", - "CMT_TOP_BYP7_7", - "CMT_TOP_IMUX7_12", - "CMT_TOP_BYP3_9", - "CMT_TOP_EE4B0_9", - "CMT_TOP_WR1END1_12", - "CMT_TOP_IMUX25_10", - "CMT_TOP_WR1END0_3", - "CMT_TOP_SW4A2_8", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_SW4A0_3", - "CMT_TOP_CLK0_6", - "CMT_TOP_IMUX3_12", - "CMT_TOP_SE2A3_4", - "CMT_TOP_FAN7_9", - "CMT_PLL_PHASERREF1", - "CMT_TOP_IMUX39_10", - "CMT_TOP_LH7_6", - "CMT_TOP_EE2A2_11", - "CMT_TOP_IMUX41_1", - "CMT_TOP_NE4C2_7", - "CMT_TOP_SW4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LH7_8", - "CMT_TOP_WR1END2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_12", - "CMT_TOP_FAN6_3", - "CMT_TOP_WW2A0_7", - "CMT_TOP_BYP4_2", - "CMT_TOP_IMUX33_11", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_WW4END0_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_WW4A0_7", - "CMT_TOP_LH9_3", - "CMT_TOP_NE2A0_5", - "CMT_TOP_EE4C3_2", - "CMT_TOP_LH5_10", - "CMT_TOP_NE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_EE4C1_3", - "CMT_TOP_SW4A1_8", - "CMT_TOP_CTRL0_8", - "CMT_TOP_NW2A0_4", - "CMT_TOP_IMUX1_12", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX21_9", - "CMT_TOP_WL1END1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LH4_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_CTRL1_0", - "CMT_TOP_LH11_10", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_SE2A3_11", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_SW2A3_0", - "CMT_TOP_BYP7_5", - "CMT_TOP_ICLK_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", - "CMT_TOP_WW4C3_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_FAN1_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", - "CMT_TOP_SW4END1_4", - "CMT_TOP_EE4C3_3", - "CMT_TOP_BYP0_12", - "CMT_TOP_WW4B1_12", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX9_5", - "CMT_TOP_WW4B1_11", - "CMT_TOP_IMUX13_9", - "CMT_TOP_FAN6_8", - "CMT_TOP_SE2A2_10", - "CMT_TOP_WW4A0_0", - "CMT_TOP_CTRL0_5", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_WW2A1_11", - "CMT_TOP_IMUX14_10", - "CMT_TOP_IMUX14_2", - "CMT_TOP_EE4B0_8", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX40_1", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX38_12", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_WW2A0_12", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_BYP7_2", - "CMT_TOP_SE4C1_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX15_4", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_IMUX23_3", - "CMT_TOP_WW2A2_3", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_EE4A1_7", - "CMT_TOP_IMUX31_3", - "CMT_TOP_EE4B3_11", - "CMT_TOP_IMUX25_8", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_EE2A3_11", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX12_9", - "CMT_TOP_EE2A1_10", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NW2A3_0", - "CMT_TOP_SW4A3_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", - "CMT_TOP_WL1END0_3", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_WW2A3_5", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_WW2END1_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", - "CMT_TOP_SW2A2_5", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", - "CMT_TOP_IMUX28_11", - "CMT_TOP_IMUX42_11", - "CMT_TOP_WW2END2_10", - "CMT_TOP_EE4B3_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_LH10_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", - "CMT_TOP_IMUX47_9", - "CMT_TOP_LH10_1", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_IMUX17_1", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_BYP4_0", - "CMT_TOP_FAN2_9", - "CMT_TOP_SE4C3_8", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NE2A2_1", - "CMT_TOP_IMUX37_5", - "CMT_TOP_IMUX7_7", - "CMT_TOP_LH8_12", - "CMT_TOP_IMUX20_6", - "CMT_TOP_WW4C1_9", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_SE4C3_4", - "CMT_TOP_NE4C3_11", - "CMT_TOP_IMUX33_5", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_EE4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BYP5_4", - "CMT_TOP_LH10_9", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_NW4A1_10", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_IMUX25_9", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EE4B0_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", - "CMT_TOP_WW4END3_2", - "CMT_TOP_IMUX30_8", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_IMUX47_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", - "CMT_TOP_IMUX16_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END1_6", - "CMT_TOP_IMUX11_11", - "CMT_TOP_WW2A0_11", - "CMT_TOP_SW4END2_7", - "CMT_TOP_IMUX34_4", - "CMT_TOP_LH12_0", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_SW4A3_11", - "CMT_TOP_NW4END2_8", - "CMT_TOP_IMUX36_0", - "CMT_TOP_FAN7_8", - "CMT_TOP_LH3_3", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_SE4C0_10", - "CMT_TOP_IMUX28_7", - "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "CMT_TOP_IMUX10_5", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_NW4END2_12", - "CMT_TOP_WW2A3_0", - "CMT_TOP_LH3_4", - "CMT_TOP_IMUX16_6", - "CMT_TOP_FAN2_11", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX40_4", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_IMUX38_0", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_PLL_PHASER_OUT_D_OCLK", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_WW4A1_10", - "CMT_TOP_NW4A3_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_9", - "CMT_TOP_LH8_5", - "CMT_TOP_EE4B2_10", - "CMT_TOP_WW2A2_5", - "CMT_TOP_IMUX29_0", - "CMT_TOP_EE4A0_8", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_IMUX16_7", - "CMT_TOP_NW4END0_2", - "CMT_TOP_FAN1_1", - "CMT_TOP_LH1_4", - "CMT_TOP_SW2A2_9", - "CMT_TOP_FAN2_12", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_IMUX45_9", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_SE4C0_7", - "CMT_TOP_WR1END0_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", - "CMT_TOP_IMUX46_3", - "CMT_TOP_SW4END2_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", - "CMT_TOP_WW4B3_5", - "CMT_TOP_IMUX6_7", - "PLL_CLK_FREQ_BB_BUFOUT_NS2", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_NW4A0_7", - "CMT_TOP_EE4A1_6", - "CMT_TOP_FAN2_0", - "CMT_TOP_WW4A0_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX37_2", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_WW2A0_1", - "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_IMUX45_8", - "CMT_TOP_FAN0_4", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SE4C0_3", - "CMT_TOP_IMUX22_12", - "CMT_TOP_IMUX29_6", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WW2END1_2", - "CMT_TOP_SE4BEG3_12", - "CMT_TOP_L_UPPER_T_CLKPLL2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_SW4A1_6", - "CMT_TOP_IMUX36_12", - "CMT_TOP_FAN5_12", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_FAN3_9", - "CMT_TOP_EE4A1_3", - "CMT_TOP_OCLK_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", - "CMT_TOP_WW2END2_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_SE4BEG0_12", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "CMT_TOP_WW4END3_9", - "CMT_TOP_IMUX26_1", - "CMT_TOP_CLK1_2", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_IMUX31_10", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_IMUX23_12", - "CMT_PLL_PHASER_OUT_D_OCLK1X_90", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_WL1END0_8", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_IMUX29_7", - "CMT_TOP_NE2A3_6", - "CMT_TOP_WW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "PLL_CLK_FREQ_BB1_NS", - "CMT_TOP_NE2A1_6", - "CMT_TOP_IMUX27_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", - "CMT_TOP_SW4A3_1", - "CMT_TOP_NW2A3_8", - "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "CMT_TOP_LH7_1", - "CMT_TOP_WW4END1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_PLL_PHASER_OUT_D_OCLKDIV", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_IMUX13_2", - "CMT_TOP_WW4END2_7", - "CMT_TOP_NW4END1_0", - "CMT_TOP_EE4C0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_NE4C2_9", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_IMUX29_5", - "CMT_TOP_WW2END0_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX34_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_BYP6_2", - "CMT_TOP_IMUX42_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", - "CMT_TOP_BYP5_5", - "CMT_TOP_WW2A3_10", - "CMT_TOP_IMUX15_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_IMUX2_1", - "CMT_TOP_SE2A2_6", - "CMT_TOP_IMUX12_11", - "CMT_TOP_EE4B1_8", - "CMT_TOP_NE2A3_4", - "CMT_TOP_SW4A3_7", - "CMT_PLL_PHASER_RDENABLE_TOFIFO", - "CMT_TOP_IMUX15_12", - "CMT_TOP_WL1END2_11", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_IMUX24_9", - "CMT_TOP_LH1_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW2A3_1", - "CMT_TOP_EE2A1_0", - "CMT_TOP_WW4C3_5", - "CMT_TOP_IMUX14_11", - "CMT_TOP_BYP1_0", - "CMT_TOP_IMUX24_1", - "PLL_CLK_FREQ_BB0_NS", - "CMT_TOP_WW4B0_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "CMT_TOP_WW4B0_7", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_NE2A1_2", - "CMT_TOP_BYP6_11", - "CMT_TOP_IMUX7_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_CLK0_12", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_IMUX30_4", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_WW2END3_1", - "CMT_TOP_IMUX22_0", - "CMT_TOP_WW2A3_6", - "CMT_TOP_EE4A0_6", - "CMT_TOP_SE4C2_9", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_EE4A0_9", - "CMT_TOP_FAN6_7", - "CMT_TOP_WW4A0_10", - "CMT_TOP_LH5_9", - "CMT_TOP_ICLK_2", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_NW4END3_0", - "CMT_TOP_SW2A1_2", - "CMT_TOP_FAN1_5", - "CMT_TOP_CTRL0_7", - "CMT_TOP_NW4END3_7", - "CMT_TOP_WW2A0_9", - "CMT_TOP_SE4C1_9", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_IMUX44_2", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW2END0_3", - "CMT_TOP_EE4A0_12", - "CMT_TOP_LH10_2", - "CMT_TOP_NE4C2_2", - "CMT_TOP_IMUX9_6", - "CMT_TOP_NW4END3_3", - "CMT_TOP_IMUX45_2", - "CMT_TOP_SW4A2_11", - "CMT_TOP_FAN6_1", - "CMT_TOP_IMUX22_9", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX17_12", - "CMT_TOP_SW4A3_8", - "CMT_TOP_LH12_8", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_NW2A0_12", - "CMT_TOP_IMUX31_11", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_WW4END0_1", - "CMT_TOP_EE4B0_6", - "CMT_TOP_BYP3_0", - "CMT_TOP_EE4B0_7", - "CMT_TOP_LH9_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_SW4END2_0", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NE4C1_1", - "CMT_PLL_DQS_TO_PHASER_D", - "CMT_TOP_EE2A1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX35_1", - "CMT_TOP_WW2END1_8", - "CMT_TOP_IMUX19_9", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_WW4A2_9", - "CMT_TOP_EE4B2_2", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_WW4C3_4", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_NE2A0_6", - "CMT_TOP_BYP1_5", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_IMUX11_10", - "CMT_TOP_FAN1_3", - "CMT_TOP_SE2A3_7", - "CMT_TOP_LH2_6", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_IMUX25_2", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_WR1END3_4", - "CMT_TOP_CTRL1_11", - "CMT_TOP_IMUX26_9", - "CMT_TOP_IMUX35_10", - "CMT_TOP_FAN0_3", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_IMUX18_12", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_WW4B3_10", - "CMT_TOP_NE2A2_8", - "CMT_TOP_FAN0_7", - "CMT_TOP_IMUX32_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "CMT_TOP_LH7_9", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_CLK0_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WW4B1_0", - "CMT_TOP_NE4BEG1_1", - "PLL_CLK_FREQ_BB2_NS", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_BYP6_5", - "CMT_TOP_WW2A0_10", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_IMUX39_2", - "CMT_TOP_SW4A1_11", - "CMT_TOP_WR1END3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_CTRL0_4", - "CMT_TOP_LH4_5", - "CMT_TOP_SW4END1_7", - "CMT_TOP_NW4END3_4", - "CMT_TOP_EE4C3_4", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_IMUX46_10", - "CMT_TOP_NW4A0_5", - "CMT_TOP_SW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_IMUX2_11", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_IMUX0_3", - "CMT_PLL_PHASERD_DQSBUS1", - "CMT_TOP_OCLK_5", - "CMT_TOP_FAN5_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_EE2A1_12", - "CMT_TOP_WL1END0_2", - "CMT_TOP_BYP0_5", - "CMT_TOP_NW2A0_10", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_EE2A2_7", - "CMT_TOP_SE2A2_2", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_SW4A2_1", - "CMT_TOP_IMUX9_4", - "CMT_TOP_WW4A3_11", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SW4END0_3", - "CMT_TOP_IMUX46_0", - "CMT_TOP_WW2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LH7_0", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_WW2A2_0", - "CMT_TOP_IMUX34_11", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_CTRL0_2", - "CMT_TOP_IMUX23_9", - "CMT_TOP_WL1END1_3", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_WW4A2_10", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_L_UPPER_T_CLKPLL3", - "CMT_TOP_SW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX29_12", - "CMT_TOP_IMUX35_11", - "CMT_TOP_NE2A3_5", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_NW2A1_1", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP5_7", - "CMT_TOP_IMUX6_1", - "CMT_TOP_LH4_10", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SW2A3_7", - "CMT_TOP_WW4C3_10", - "CMT_TOP_LH3_12", - "CMT_TOP_WW4END1_10", - "CMT_TOP_IMUX44_0", - "CMT_TOP_BYP7_11", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX28_1", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LH8_1", - "CMT_TOP_WW4A0_3", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_CLK1_0", - "CMT_TOP_IMUX2_10", - "CMT_TOP_SW4A0_9", - "CMT_TOP_IMUX27_4", - "CMT_TOP_SW4A1_7", - "CMT_TOP_IMUX40_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EE4C3_12", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_NW2A0_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_NW4A1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_WW2A1_9", - "CMT_TOP_BYP1_11", - "CMT_TOP_SE4C2_7", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_NE4C1_7", - "CMT_TOP_WW4B2_1", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_NE4C0_11", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_SE2A3_2", - "CMT_TOP_LH8_3", - "CMT_TOP_IMUX13_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_BLOCK_OUTS_L_B0_12", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_IMUX30_7", - "CMT_TOP_WW4C3_2", - "CMT_TOP_SW4END1_8", - "CMT_TOP_EE4B0_2", - "CMT_TOP_BYP6_10", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "CMT_TOP_LH5_1", - "CMT_TOP_EE4B2_11", - "CMT_TOP_BYP4_9", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_SE2A1_10", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_WR1END3_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LH8_10", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_IMUX13_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", - "CMT_TOP_IMUX34_7", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_NW4A2_7", - "CMT_TOP_LH9_11", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EE2A2_1", - "CMT_TOP_FAN4_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", - "CMT_TOP_EE4B3_9", - "CMT_TOP_BYP3_11", - "CMT_TOP_WW4END1_1", - "CMT_TOP_FAN0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_BYP0_11", - "CMT_TOP_NE4C0_5", - "CMT_TOP_SW2A0_8", - "CMT_TOP_NW2A2_2", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX0_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_IMUX37_12", - "CMT_TOP_BYP4_4", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_EE2A1_6", - "CMT_TOP_NE2A1_5", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_IMUX21_12", - "CMT_TOP_FAN3_4", - "CMT_TOP_LH7_5", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX17_11", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_IMUX43_8", - "CMT_TOP_SE2A3_5", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4C1_6", - "CMT_TOP_WW4C0_2", - "CMT_TOP_LH12_7", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_EE2A1_9", - "CMT_TOP_WW2END2_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_BYP4_5", - "CMT_TOP_IMUX22_3", - "CMT_TOP_NE2A2_6", - "CMT_TOP_FAN5_10", - "CMT_TOP_EE4A0_7", - "CMT_TOP_WW2END1_10", - "CMT_TOP_IMUX19_12", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_IMUX38_11", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WW4B2_5", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_NE2A2_9", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", - "CMT_TOP_FAN0_12", - "CMT_TOP_IMUX2_8", - "CMT_TOP_WW2END3_2", - "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WW2A2_10", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_IMUX28_2", - "CMT_TOP_WW4C1_4", - "CMT_TOP_EE4C2_7", - "CMT_TOP_LH12_1", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE4C0_4", - "CMT_TOP_LH11_0", - "CMT_TOP_WW2A1_2", - "CMT_TOP_FAN6_2", - "CMT_TOP_IMUX22_7", - "CMT_TOP_WW2END3_4", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SE2A2_4", - "CMT_TOP_NW4END0_12", - "CMT_TOP_SW4A1_0", - "CMT_TOP_IMUX1_8", - "CMT_TOP_WW4C2_4", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_2", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_IMUX20_11", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4END3_10", - "CMT_TOP_CLK0_2", - "CMT_TOP_IMUX11_2", - "CMT_TOP_WW2END0_5", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_WW4B1_1", - "CMT_TOP_LH6_7", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE4B2_8", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_WW4A3_6", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_BYP5_11", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_EE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_CLK1_3", - "CMT_TOP_IMUX34_0", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_IMUX30_11", - "CMT_TOP_SE2A3_8", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX30_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_FAN7_3", - "CMT_TOP_IMUX33_6", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_NW4END1_9", - "CMT_TOP_WW4END2_10", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", - "CMT_TOP_L_UPPER_T_FREQ_BB0", - "CMT_TOP_SW4END0_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_WW4END1_6", - "CMT_TOP_IMUX16_10", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", - "CMT_TOP_WR1END3_1", - "CMT_TOP_IMUX26_11", - "CMT_TOP_NE2A0_0", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX28_6", - "CMT_TOP_SE4C2_11", - "CMT_TOP_EE4A2_2", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX24_0", - "CMT_TOP_NW4END2_4", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW4C3_3", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", - "CMT_TOP_EE4C3_5", - "CMT_TOP_SE2A0_8", - "CMT_TOP_IMUX0_2", - "CMT_TOP_EE4C0_5", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SW4END2_12", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX36_4", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_WR1END1_4", - "CMT_TOP_SW4END0_11", - "CMT_TOP_LH5_8", - "CMT_TOP_LH8_9", - "CMT_TOP_IMUX21_0", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "CMT_TOP_WL1END0_7", - "CMT_TOP_SW2A0_6", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_WW4END3_6", - "CMT_TOP_IMUX7_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_EE2A1_5", - "CMT_TOP_NW2A0_8", - "CMT_TOP_WL1END0_12", - "CMT_TOP_IMUX21_10", - "CMT_TOP_SW2A2_6", - "CMT_TOP_IMUX26_0", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_IMUX23_1", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_WW4C1_12", - "CMT_TOP_IMUX3_6", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_BYP0_0", - "CMT_TOP_SW4END0_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_ICLK_12", - "CMT_TOP_IMUX40_12", - "CMT_TOP_BYP3_4", - "CMT_TOP_WW4C2_1", - "CMT_TOP_BYP1_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX24_12", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_IMUX43_3", - "CMT_TOP_NW4A2_8", - "CMT_TOP_WR1END3_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", - "CMT_TOP_WW4C3_12", - "CMT_TOP_ICLK_5", - "CMT_TOP_IMUX0_12", - "CMT_TOP_WW2END2_4", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_IMUX18_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_NW4A2_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_NW4END0_11", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", - "CMT_TOP_WW4C2_11", - "CMT_TOP_IMUX18_5", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SW2A1_1", - "CMT_TOP_EE4C0_12", - "CMT_TOP_BYP3_10", - "CMT_TOP_IMUX16_12", - "CMT_TOP_EE4A3_4", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX20_5", - "CMT_TOP_NW2A2_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_IMUX24_8", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LH3_5", - "CMT_TOP_IMUX26_2", - "CMT_TOP_WW4A0_11", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "CMT_TOP_IMUX19_8", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_SE2A1_3", - "CMT_TOP_WL1END1_12", - "CMT_TOP_BYP4_11", - "CMT_TOP_NW4A3_10", - "CMT_TOP_FAN1_7", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_WW4A2_0", - "CMT_TOP_IMUX28_10", - "CMT_TOP_NW4A2_12", - "CMT_TOP_NE4C1_10", - "CMT_TOP_WW2A3_9", - "CMT_TOP_EE4A1_4", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX33_12", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_IMUX46_5", - "CMT_TOP_NE2A0_1", - "CMT_TOP_LH10_12", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_WR1END2_8", - "CMT_TOP_IMUX10_12", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX26_7", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_NW4END2_10", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2A3_6", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_FAN3_8", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_NW4END0_1", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_FAN3_6", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_EE2A3_10", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_SW4END3_1", - "CMT_TOP_IMUX22_11", - "CMT_TOP_WW4A2_7", - "CMT_TOP_NW4A2_1", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW4C3_8", - "CMT_TOP_NE2A0_8", - "CMT_TOP_IMUX12_10", - "CMT_TOP_WW4C3_9", - "CMT_TOP_NE2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_FAN5_9", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_FAN3_0", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_3", - "CMT_TOP_SW2A0_7", - "CMT_TOP_NE4C0_1", - "CMT_TOP_IMUX3_1", - "CMT_TOP_WL1END3_4", - "CMT_TOP_IMUX37_9", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_NW4END3_5", - "CMT_TOP_WW2A2_7", - "CMT_TOP_FAN2_5", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WL1END3_0", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_IMUX36_1", - "CMT_TOP_SW2A1_9", - "CMT_TOP_EE4A3_2", - "CMT_TOP_IMUX15_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LH3_6", - "CMT_TOP_IMUX27_6", - "CMT_TOP_WW2END2_0", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX43_2", - "CMT_TOP_NE4C3_9", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C1_6", - "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "CMT_TOP_WW4B2_9", - "CMT_TOP_IMUX4_5", - "CMT_TOP_EE4C0_9", - "CMT_TOP_BYP7_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_WR1END2_10", - "CMT_TOP_NE4C1_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_SW2A3_12", - "CMT_TOP_WW2A0_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", - "CMT_TOP_SE4C2_8", - "CMT_TOP_IMUX26_12", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "CMT_TOP_IMUX38_8", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_LH1_3", - "CMT_TOP_BYP1_2", - "CMT_TOP_IMUX26_5", - "CMT_TOP_SE4C3_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_NE4C0_10", - "CMT_TOP_WW4C0_12", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", - "CMT_TOP_IMUX12_3", - "CMT_TOP_WW4C0_1", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_IMUX38_6", - "CMT_TOP_LH6_10", - "CMT_TOP_FAN3_12", - "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_WW4B3_4", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_IMUX1_10", - "CMT_TOP_WW2END0_9", - "CMT_TOP_SE2A0_9", - "CMT_TOP_WW4B0_12", - "CMT_PHASER_D_OCLK_TOIOI", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX36_7", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_IMUX39_8", - "CMT_TOP_WW4B0_5", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_BYP4_7", - "CMT_TOP_IMUX43_9", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_WW2END3_10", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_IMUX12_12", - "CMT_TOP_SW2A0_5", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_LH4_12", - "CMT_TOP_SW4END1_9", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_FAN0_2", - "CMT_TOP_IMUX19_1", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_NW2A3_11", - "CMT_TOP_IMUX41_0", - "CMT_TOP_FAN3_2", - "CMT_TOP_WW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_SW2A3_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SE2A1_11", - "CMT_TOP_WW4A0_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_EE4B0_0", - "CMT_TOP_NW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CMT_TOP_NW2A3_3", - "CMT_TOP_SE4C0_8", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4END2_3", - "CMT_TOP_NE2A3_10", - "CMT_TOP_LH1_5", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_WW4B2_10", - "CMT_TOP_SW4END2_1", - "CMT_TOP_EE4B3_4", - "CMT_TOP_SW4END1_3", - "CMT_TOP_IMUX25_6", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LH9_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX37_3", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_LH1_9", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_SW4A3_12", - "CMT_TOP_EE4C2_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", - "CMT_TOP_IMUX36_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_WW4A3_3", - "CMT_TOP_LH2_8", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX39_12", - "CMT_TOP_IMUX29_8", - "CMT_TOP_FAN7_12", - "CMT_TOP_IMUX34_10", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_WW4A3_2", - "CMT_TOP_EE4B1_12", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_EE4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_LH12_12", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_NE2A2_11", - "CMT_TOP_LH3_1", - "CMT_TOP_SW4A3_5", - "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_WW4END1_5", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX11_8", - "CMT_TOP_NW4END2_11", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX8_2", - "CMT_TOP_EL1BEG1_12", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_WW2A3_3", - "CMT_TOP_EE4A2_3", - "CMT_TOP_SW4A1_1", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_8", - "CMT_TOP_WW4A1_6", - "CMT_TOP_IMUX41_2", - "CMT_TOP_LH8_6", - "CMT_TOP_SE4C1_8", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WW4A2_6", - "CMT_TOP_BYP0_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", - "CMT_TOP_IMUX43_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX42_12", - "CMT_TOP_WR1END2_1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", - "CMT_TOP_NW4END3_11", - "CMT_TOP_WR1END3_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", - "CMT_TOP_NW4A0_4", - "CMT_TOP_IMUX24_4", - "CMT_TOP_EE4C1_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WW4C1_8", - "CMT_TOP_NW2A0_7", - "CMT_TOP_LH1_11", - "CMT_TOP_IMUX22_1", - "CMT_TOP_IMUX17_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_IMUX19_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX10_9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", - "CMT_TOP_EE2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_IMUX11_12", - "CMT_TOP_CLK1_4", - "CMT_TOP_LH2_2", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4C2_3", - "CMT_TOP_EE4A2_7", - "CMT_TOP_IMUX11_0", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_IMUX38_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_10", - "CMT_TOP_LH3_9", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_10", - "CMT_TOP_NW4END2_2", - "CMT_TOP_WW2A2_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_LH4_9", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4B0_6", - "CMT_TOP_BYP1_9", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_NW4A1_5", - "CMT_TOP_SE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_SE4BEG2_12", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_SW4END3_10", - "CMT_TOP_IMUX9_1", - "CMT_TOP_NW4A1_9", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_BYP7_8", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX46_7", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_IMUX30_1", - "CMT_TOP_WW4C0_5", - "CMT_TOP_NW4A1_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", - "CMT_TOP_WW2END0_2", - "CMT_TOP_FAN0_0", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX18_8", - "CMT_TOP_NW4A1_12", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX20_4", - "CMT_TOP_EE4C3_6", - "CMT_TOP_FAN6_12", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_IMUX39_11", - "CMT_TOP_NE4C0_2", - "CMT_TOP_EE4B1_2", - "CMT_TOP_IMUX4_9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SE4C1_1", - "CMT_TOP_EE4A1_9", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "CMT_TOP_IMUX30_2", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_EE2A2_2", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4A2_8", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_IMUX23_8", - "CMT_TOP_SW4END0_6", - "CMT_TOP_IMUX12_2", - "CMT_TOP_NW2A2_7", - "CMT_TOP_WL1END2_7", - "CMT_TOP_BYP5_1", - "CMT_TOP_EE4B1_9", - "CMT_TOP_IMUX2_12", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "CMT_TOP_IMUX33_0", - "CMT_TOP_WW2A2_9", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_OCLK_7", - "CMT_TOP_FAN1_10", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_SW2A1_10", - "CMT_TOP_IMUX19_7", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_L_UPPER_T_CLKFBIN", - "CMT_TOP_SE4C0_6", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_IMUX3_0", - "CMT_TOP_WL1END1_8", - "CMT_TOP_NW4END1_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_LH6_2", - "CMT_TOP_IMUX39_6", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_IMUX36_2", - "CMT_TOP_WW2A0_5", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_BYP2_0", - "CMT_TOP_IMUX8_3", - "CMT_TOP_ICLK_6", - "CMT_TOP_LH2_0", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX40_2", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_WW4END3_1", - "CMT_TOP_SW4A2_4", - "CMT_TOP_LH11_11", - "CMT_TOP_IMUX46_2", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NW4A3_2", - "CMT_TOP_IMUX17_10", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX30_12", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW4END1_3", - "CMT_PLL_PHASER_WRCLK_TOFIFO", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_NW2A3_7", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_NW4A3_8", - "CMT_TOP_SW4END2_8", - "CMT_TOP_WL1END3_12", - "CMT_TOP_SE2A0_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_EE4A1_12", - "CMT_TOP_WW2END0_7", - "CMT_TOP_L_UPPER_T_CLKIN2", - "CMT_TOP_EE4C0_6", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_EE4C0_7", - "CMT_TOP_WL1END0_0", - "CMT_PHASER_D_ICLK_TOIOI", - "CMT_TOP_FAN7_2", - "CMT_TOP_WL1END3_1", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_LH8_4", - "CMT_TOP_LH5_6", - "CMT_TOP_BYP2_11", - "CMT_TOP_SW4A0_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", - "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_WR1END2_12", - "CMT_TOP_BYP7_4", - "CMT_TOP_EE4C2_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", - "CMT_TOP_LH10_6", - "CMT_TOP_SE4C2_4", - "CMT_TOP_FAN1_12", - "CMT_TOP_IMUX35_9", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LH4_2", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX6_12", - "CMT_TOP_EE4A3_8", - "CMT_TOP_IMUX44_3", - "CMT_PLL_PHASERREF0", - "CMT_TOP_IMUX24_2", - "CMT_TOP_EE4A3_11", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX34_5", - "CMT_TOP_NW4END2_9", - "CMT_TOP_IMUX20_9", - "CMT_TOP_IMUX29_1", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_SW4A2_3", - "CMT_TOP_FAN1_9", - "CMT_TOP_BYP7_1", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WL1END3_8", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX19_6", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX17_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_OCLK_0", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX13_11", - "CMT_TOP_WL1END1_11", - "CMT_TOP_IMUX2_2", - "CMT_TOP_WW4END3_5", - "CMT_TOP_LH1_1", - "CMT_TOP_FAN5_8", - "CMT_TOP_NW4END3_8", - "CMT_TOP_WW4A1_1", - "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_EE2A3_2", - "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_WW2END2_3", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_WW2END2_6", - "CMT_TOP_IMUX41_10", - "CMT_TOP_EE4B2_1", - "CMT_TOP_NW4END3_1", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_12", - "CMT_TOP_LH3_0", - "PLL_CLK_FREQ_BB3_NS", - "CMT_TOP_LH2_5", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_EE4A3_3", - "CMT_TOP_NW4A2_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SE4C0_12", - "CMT_TOP_IMUX34_8", - "CMT_TOP_SW4A2_10", - "CMT_TOP_NW2A3_1", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX32_11", - "CMT_TOP_WW4B3_7", - "CMT_TOP_LH11_9", - "CMT_TOP_NE2A2_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_NW4A2_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_WW4C2_10", - "CMT_TOP_BYP7_0", - "CMT_TOP_LH6_0", - "CMT_TOP_NE4C1_4", - "CMT_TOP_IMUX16_9", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_EE4A0_10", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_IMUX5_2", - "CMT_TOP_WW4C0_10", - "CMT_PLL_PHYCTRL_SYNC_BB_UP", - "CMT_TOP_FAN1_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_WW4B2_6", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_IMUX29_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LH3_11", - "CMT_TOP_IMUX32_7", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_BYP2_3", - "CMT_TOP_IMUX1_6", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_L_UPPER_T_CLKPLL6", - "CMT_TOP_WR1END2_4", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX20_3", - "CMT_TOP_LH7_3", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX28_8", - "CMT_TOP_NW4END2_5", - "CMT_TOP_WW2A0_3", - "CMT_TOP_IMUX33_9", - "CMT_TOP_WR1END1_9", - "PLL_CLK_FREQ_BB_BUFOUT_NS1", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX23_11", - "CMT_TOP_SW4END2_4", - "CMT_TOP_FAN6_0", - "CMT_TOP_LH6_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_IMUX4_3", - "CMT_TOP_WL1END2_12", - "CMT_TOP_SW4END3_3", - "CMT_TOP_WW4B0_3", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP3_2", - "CMT_TOP_CTRL0_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_CLK1_8", - "CMT_TOP_FAN3_3", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_IMUX42_0", - "CMT_TOP_LH12_4", - "CMT_TOP_SW2A0_9", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_FAN0_6", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_SW4END0_1", - "CMT_TOP_FAN5_11", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_IMUX1_0", - "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", - "CMT_TOP_NW2A3_4", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_WW4END1_9", - "CMT_TOP_EE2A2_4", - "CMT_TOP_L_UPPER_T_CLKIN1", - "CMT_TOP_WL1END0_4", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_IMUX4_10", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_IMUX34_12", - "CMT_TOP_SW4END3_4", - "CMT_TOP_WW4C3_1", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_WL1END0_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "CMT_TOP_EE4A0_3", - "CMT_TOP_NW4A3_6", - "CMT_TOP_LH7_12", - "CMT_TOP_BYP2_5", - "CMT_TOP_ICLK_0", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LH6_9", - "CMT_TOP_CTRL1_9", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "CMT_TOP_IMUX33_4", - "CMT_TOP_NW2A1_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_EE4B0_4", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_IMUX1_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_WR1END0_6", - "CMT_TOP_LH12_2", - "CMT_TOP_FAN5_5", - "CMT_TOP_IMUX4_8", - "CMT_TOP_SW2A2_7", - "CMT_TOP_IMUX43_6", - "CMT_PLL_PHASER_RDCLK_TOFIFO", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WL1END1_10", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", - "CMT_TOP_BYP6_3", - "CMT_TOP_FAN2_6", - "CMT_TOP_WR1END1_1", - "CMT_TOP_OCLK_3", - "CMT_TOP_EE4C2_8", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_IMUX31_9", - "CMT_TOP_IMUX30_0", - "CMT_TOP_OCLK_8", - "CMT_TOP_FAN4_3", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_LH4_4", - "CMT_TOP_EE4B3_0", - "CMT_TOP_NE4C0_12", - "CMT_TOP_EE4C3_11", - "CMT_TOP_FAN4_8", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_IMUX33_1", - "CMT_TOP_EE4C1_5", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4B3_0", - "CMT_TOP_LH2_1", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "CMT_TOP_LH6_8", - "CMT_TOP_NW4A1_11", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_WL1END0_1", - "CMT_TOP_NE2A3_3", - "CMT_TOP_IMUX12_8", - "CMT_TOP_EE4A1_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", - "CMT_TOP_BYP3_3", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_WW4A1_11", - "CMT_TOP_IMUX46_9", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE4C2_6", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX18_1", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_NW4END1_10", - "CMT_TOP_IMUX20_8", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NE2A3_2", - "CMT_TOP_SE2A0_6", - "CMT_TOP_IMUX30_3", - "CMT_TOP_LH7_10", - "CMT_TOP_L_CLKFBOUT2IN", - "CMT_TOP_OCLK_6", - "CMT_TOP_WW4END0_12", - "CMT_TOP_SW4END0_9", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX37_6", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4C2_5", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_EE4B2_5", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WW4A1_5", - "CMT_TOP_BYP3_7", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_FAN2_1", - "CMT_TOP_IMUX36_11", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", - "CMT_TOP_IMUX44_6", - "CMT_TOP_OCLK_1", - "CMT_TOP_NW2A0_9", - "CMT_TOP_WW4C2_12", - "CMT_TOP_IMUX43_12", - "CMT_TOP_L_UPPER_T_FREQ_BB2", - "CMT_TOP_IMUX36_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_WW4END2_2", - "CMT_TOP_LH12_9", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_NE2A2_10", - "CMT_TOP_SW4END2_9", - "CMT_TOP_EE2A2_3", - "CMT_TOP_LH4_7", - "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_L_UPPER_T_CLKPLL5", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_IMUX6_0", - "CMT_TOP_NE2A0_9", - "CMT_TOP_WW4B3_3", - "CMT_TOP_BYP4_6", - "CMT_TOP_FAN3_10", - "CMT_TOP_BYP6_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_NE2A1_1", - "CMT_TOP_WW4END1_8", - "CMT_TOP_SW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_CTRL0_3", - "CMT_TOP_WW4B3_1", - "CMT_TOP_NW4A2_4", - "CMT_TOP_LH4_11", - "PLLOUT_CLK_FREQ_BB_3", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_SE4C3_3", - "CMT_TOP_WW2END1_9", - "CMT_TOP_NE4C3_1", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WL1END3_9", - "CMT_TOP_SE4C0_4", - "CMT_TOP_EE4C3_0", - "CMT_TOP_IMUX9_10", - "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", - "CMT_TOP_WW4C1_3", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_EE4A1_11", - "CMT_TOP_NW2A2_10", - "CMT_TOP_CTRL1_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "CMT_TOP_WL1END1_1", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_NW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_NW2A1_11", - "CMT_TOP_EE4B2_0", - "CMT_TOP_LH5_7", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX2_5", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_CLK0_1", - "CMT_TOP_IMUX6_4", - "CMT_TOP_NW4A2_11", - "CMT_TOP_EE2A2_8", - "CMT_TOP_SE4C3_7", - "CMT_TOP_WW4C0_7", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_SW2A1_12", - "CMT_TOP_SE4C2_5", - "CMT_TOP_IMUX32_0", - "CMT_TOP_SW2A3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_WW2END3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_EE4B1_4", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX27_5", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_EE4C0_0", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_WW4B0_9", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_NW4END2_0", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_WW4END3_11", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_EE4B1_3", - "CMT_TOP_NW4END3_2", - "CMT_TOP_IMUX21_1", - "CMT_TOP_IMUX31_12", - "CMT_TOP_SW4END0_0", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW2END1_7", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_IMUX32_12", - "CMT_TOP_WW4C0_3", - "CMT_TOP_BYP7_10", - "CMT_TOP_IMUX6_9", - "CMT_TOP_WW4A0_1", - "CMT_TOP_EE4B1_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_NW4A0_10", - "CMT_TOP_EE4B2_12", - "CMT_TOP_WW4END0_11", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NE4C3_4", - "CMT_TOP_BYP6_9", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX29_10", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW2A0_2", - "CMT_TOP_BYP2_8", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW4C0_0", - "CMT_TOP_BYP6_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "CMT_TOP_IMUX28_0", - "CMT_TOP_EE4A2_0", - "CMT_TOP_BYP2_12", - "CMT_TOP_SW2A2_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "CMT_TOP_LH12_10", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW4END1_10", - "CMT_TOP_NW4END0_5", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_IMUX3_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "CMT_TOP_SW4END3_8", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END3_6", - "CMT_TOP_IMUX14_4", - "CMT_TOP_LH6_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WW2A1_10", - "CMT_TOP_SW4A2_7", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_WW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_IMUX0_11", - "CMT_TOP_FAN4_0", - "CMT_PLL_PHASERREF_BELOW0", - "CMT_TOP_IMUX41_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_WW4A3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_LH6_1", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WL1END2_9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", - "CMT_TOP_BYP4_10", - "CMT_TOP_IMUX11_4", - "CMT_TOP_WL1END3_10", - "CMT_TOP_IMUX47_12", - "CMT_TOP_NE4C3_0", - "CMT_TOP_WW4END1_0", - "CMT_TOP_FAN7_5", - "CMT_TOP_OCLK_12", - "CMT_TOP_SE4C0_9", - "CMT_TOP_BYP0_8", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_IMUX22_2", - "CMT_TOP_FAN4_5", - "CMT_TOP_NE2A1_12", - "CMT_TOP_EE4B2_6", - "CMT_TOP_SW4A1_3", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW2A2_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_IMUX19_3", - "CMT_TOP_SW4END1_12", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_SE4C1_12", - "CMT_TOP_EE4A1_8", - "CMT_TOP_WW4B1_2", - "CMT_TOP_IMUX9_9", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_SW2A0_12", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LH9_9", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_NE4C1_12", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_WW4B3_9", - "CMT_TOP_NE4C3_10", - "CMT_TOP_FAN5_6", - "CMT_TOP_IMUX30_6", - "CMT_TOP_BYP3_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_FAN0_10", - "CMT_TOP_IMUX40_10", - "CMT_TOP_LH2_3", - "CMT_TOP_EE4C3_8", - "CMT_TOP_SW4END2_3", - "CMT_TOP_WW4B2_12", - "CMT_TOP_IMUX46_12", - "CMT_TOP_EE2A0_9", - "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "CMT_TOP_WW4A1_3", - "CMT_TOP_BYP5_10", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_WR1END0_4", - "CMT_TOP_NW2A0_2", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_SE4C3_0", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_SE2A1_5", - "CMT_TOP_FAN0_11", - "CMT_TOP_WL1END3_11", - "CMT_TOP_FAN6_5", - "CMT_TOP_EE4A3_7", - "CMT_TOP_WR1END0_7", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_EE4A2_4", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A3_9", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "CMT_TOP_NE2A1_4", - "CMT_TOP_WR1END1_0", - "CMT_TOP_EE4BEG2_12", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_IMUX32_1", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_1", - "CMT_TOP_WW2END3_12", - "CMT_TOP_IMUX20_2", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_NW4END1_11", - "CMT_TOP_FAN0_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_WW2END1_11", - "CMT_TOP_FAN0_9", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_NE4C3_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", - "CMT_TOP_NW4A0_0", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_EE4C1_12", - "CMT_TOP_BYP1_8", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EE4B2_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_EE4B3_2", - "CMT_TOP_SE4C1_5", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CMT_TOP_FAN6_6", - "CMT_TOP_IMUX25_12", - "CMT_TOP_IMUX36_3", - "CMT_TOP_SE4C2_3", - "CMT_TOP_NW4END0_3", - "CMT_TOP_FAN4_9", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX25_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", - "CMT_TOP_IMUX27_8", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_EE4A3_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_BYP3_6", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A2_12", - "CMT_TOP_WW4B1_3", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_BYP2_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "CMT_TOP_IMUX27_11", - "CMT_TOP_SE2A2_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_SE4C3_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", - "CMT_TOP_NE4C3_3", - "CMT_TOP_WR1END2_9", - "CMT_TOP_CTRL0_6", - "CMT_TOP_FAN2_2", - "CMT_TOP_NW4END1_2", - "CMT_TOP_IMUX18_7", - "CMT_TOP_OCLK_10", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LH2_11", - "CMT_TOP_NW4A1_0", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4END3_3", - "CMT_TOP_BYP7_9", - "CMT_TOP_SW4END1_6", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4C0_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "CMT_TOP_SE4C0_1", - "CMT_TOP_EE2A0_1", - "CMT_TOP_NW2A1_8", - "CMT_TOP_LH9_4", - "CMT_TOP_SW4END1_1", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LH10_8", - "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WW2END3_3", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_FAN1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_SE4C1_2", - "CMT_TOP_NW2A2_6", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX46_8", - "CMT_TOP_EE4B1_7", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_EE4B0_5", - "CMT_TOP_NW2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_LH10_11", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_IMUX6_2", - "CMT_TOP_NE4C2_6", - "CMT_TOP_WW4END2_9", - "CMT_TOP_IMUX13_10", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_WW2END3_11", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_LH8_8", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW4A2_2", - "CMT_TOP_WW2A1_6", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_IMUX3_8", - "CMT_TOP_SW2A0_11", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_FAN6_9", - "CMT_TOP_SE4C1_3", - "CMT_TOP_WL1END2_6", - "CMT_TOP_LH11_2", - "CMT_TOP_WW4C0_9", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "PLL_CLK_FREQ_BB_BUFOUT_NS3", - "CMT_TOP_IMUX12_1", - "CMT_TOP_SE2A0_1", - "CMT_TOP_IMUX46_11", - "CMT_TOP_IMUX37_4", - "CMT_TOP_EE4C3_10", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_NE4C1_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_NW4END3_12", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX0_4", - "CMT_TOP_NW4A3_12", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_LH1_12", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_IMUX40_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW4A1_5", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_9", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_SE2A2_5", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_SW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LH2_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_WW4END0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_SE2A3_9", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX7_10", - "CMT_TOP_WW4A1_8", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "CMT_TOP_WW4END3_4", - "CMT_TOP_SE2A3_10", - "CMT_TOP_WW2A3_7", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4END2_6", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_NE2A1_11", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_NW2A0_11", - "CMT_TOP_IMUX42_2", - "CMT_TOP_LH8_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_EE4A0_5", - "CMT_TOP_WL1END2_3", - "CMT_TOP_SE2A1_8", - "CMT_TOP_NE4C1_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_NW2A0_6", - "CMT_TOP_WW4A3_8", - "CMT_TOP_SW2A1_3", - "CMT_TOP_IMUX40_5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", - "CMT_TOP_SE2A1_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", - "CMT_TOP_CTRL1_5", - "CMT_TOP_SE4C3_1", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX18_3", - "CMT_TOP_EE2A1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_IMUX16_5", - "CMT_TOP_LH9_5", - "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "CMT_TOP_WW2END0_6", - "CMT_TOP_EE2A1_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_WL1END3_7", - "CMT_TOP_EE4A3_12", - "CMT_TOP_BYP5_8", - "CMT_TOP_IMUX47_3", - "CMT_TOP_NE2A2_7", - "CMT_TOP_WW4B1_5", - "CMT_TOP_SE4C3_9", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END3_12", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_EE2A2_0", - "CMT_TOP_IMUX4_12", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_LH9_7", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW2END3_5", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CLK1_9", - "CMT_TOP_IMUX5_11", - "CMT_TOP_WR1END2_6", - "CMT_TOP_CTRL1_2", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_NW2A1_12", - "CMT_TOP_IMUX10_11", - "CMT_TOP_LH6_6", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_SE2A3_12", - "CMT_TOP_EE2A3_1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", - "CMT_TOP_IMUX2_0", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_IMUX28_12", - "CMT_TOP_EE4B3_5", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX38_2", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_NE2A0_12", - "CMT_TOP_FAN4_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", - "CMT_TOP_CLK0_5", - "CMT_TOP_SW4A3_0", - "CMT_PLL_PHASERD_DTSBUS1", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_ICLK_4", - "CMT_PLL_PHASERREF_ABOVE0", - "CMT_TOP_OCLK_4", - "CMT_TOP_LH12_6", - "CMT_TOP_IMUX4_6", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_WR1END2_3", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX4_11", - "CMT_TOP_NW2A2_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_SE4C1_4", - "CMT_TOP_WW4C0_4", - "CMT_TOP_IMUX6_8", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_WW4A2_4", - "CMT_TOP_IMUX7_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SW4A3_9", - "CMT_TOP_IMUX20_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_IMUX35_7", - "CMT_TOP_EE4A3_5", - "CMT_TOP_LH6_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_ICLK_8", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_IMUX44_12", - "CMT_TOP_NW2A3_9", - "CMT_TOP_CLK0_8", - "CMT_TOP_IMUX7_2", - "CMT_TOP_SE2A2_11", - "CMT_TOP_FAN4_2", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_LH12_3", - "CMT_TOP_WW2A1_8", - "CMT_TOP_NE4C2_12", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LH8_2", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_IMUX23_7", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_IMUX39_0", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX33_8", - "CMT_TOP_SW2A2_2", - "CMT_TOP_LH10_0", - "CMT_TOP_LH6_3", - "CMT_TOP_EE2A0_0", - "CMT_TOP_IMUX12_0", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_NW4A1_1", - "CMT_TOP_IMUX21_8", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX10_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_FAN2_10", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_LH9_12", - "CMT_TOP_IMUX5_12", - "CMT_TOP_LH12_11", - "CMT_TOP_IMUX36_10", - "CMT_TOP_LH4_1", - "CMT_TOP_SE4C3_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", - "CMT_TOP_NE4C2_11", - "CMT_TOP_IMUX3_3", - "CMT_TOP_L_UPPER_T_FREQ_BB1", - "CMT_TOP_BYP1_1", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_SW4END1_5", - "CMT_TOP_FAN7_0", - "CMT_TOP_IMUX35_12", - "CMT_TOP_NW2A3_10", - "CMT_TOP_LH1_7", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_WW4A0_4", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW2A1_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", - "CMT_TOP_WW4C2_0", - "CMT_TOP_SE2A3_3", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_WL1END2_4", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_IMUX9_0", - "CMT_TOP_NW4A0_12", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LH5_0", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_PLL_PHASERREF_ABOVE1", - "CMT_TOP_IMUX22_5", - "CMT_TOP_NE2A3_12", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE2A2_12", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_IMUX11_1", - "CMT_TOP_NE2A3_8", - "CMT_TOP_EE2A3_0", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LH4_6", - "CMT_TOP_WW4A3_9", - "CMT_TOP_FAN7_7", - "CMT_TOP_SE2A1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_SE4C0_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_LH5_3", - "CMT_TOP_SW2A3_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_IMUX25_1", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX31_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "CMT_TOP_LH3_2", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4END2_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_BYP1_7", - "CMT_TOP_LH3_10", - "CMT_TOP_WL1END2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_WL1END3_5", - "CMT_TOP_ICLK_3", - "CMT_TOP_IMUX0_5", - "CMT_TOP_SW4A0_8", - "CMT_TOP_FAN7_6", - "CMT_TOP_IMUX4_0", - "CMT_TOP_BYP1_10", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX20_12", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_IMUX19_4", - "CMT_TOP_WW4B1_8", - "CMT_TOP_LH4_0", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_EE4A2_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", - "CMT_TOP_IMUX44_7", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4C3_7", - "CMT_TOP_WL1END1_5", - "CMT_TOP_IMUX42_9", - "CMT_TOP_CTRL0_12", - "CMT_TOP_IMUX3_2", - "CMT_TOP_SE4C0_2", - "CMT_TOP_L_UPPER_T_CLKPLL0", - "CMT_TOP_WW2A1_12", - "CMT_TOP_WW4A1_9", - "CMT_TOP_SW4END0_12", - "CMT_TOP_LH7_2", - "CMT_TOP_WW4A1_4", - "CMT_TOP_CLK0_3", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_IMUX44_8", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_WW2A3_12", - "CMT_TOP_SE4C2_0", - "CMT_TOP_EE2A2_12", - "CMT_TOP_IMUX23_2", - "CMT_TOP_WW4END3_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_NW4A0_8", - "CMT_TOP_WW4END3_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX21_2", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_FAN6_10", - "CMT_TOP_LH11_6", - "CMT_TOP_CLK1_10", - "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "CMT_TOP_IMUX45_12", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_SW2A3_2", - "CMT_TOP_IMUX44_5", - "CMT_TOP_WW2A0_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_IMUX33_10", - "CMT_TOP_EE4B3_10", - "CMT_TOP_WW4C1_7", - "CMT_TOP_IMUX24_5", - "CMT_TOP_WW4C2_8", - "CMT_TOP_EE2A3_8", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_NW4END0_6", - "CMT_PHASER_D_OCLK90_TOIOI", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "CMT_TOP_SE2A3_0", - "CMT_TOP_EE4C0_10", - "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "CMT_TOP_IMUX43_10", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NE2A3_0", - "CMT_TOP_LH12_5", - "CMT_TOP_WW2END1_12", - "CMT_TOP_IMUX35_6", - "CMT_TOP_EE4C2_3", - "CMT_TOP_WW2END0_10", - "CMT_TOP_FAN2_7", - "CMT_TOP_WW4A3_0", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_IMUX31_2", - "CMT_TOP_FAN3_7", - "CMT_TOP_IMUX3_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_IMUX8_6", - "CMT_TOP_EE4A1_1", - "CMT_TOP_SW4A0_5", - "CMT_TOP_EE2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_WR1END1_10", - "CMT_TOP_EE2A0_6", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX47_6", - "CMT_TOP_SW4A2_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_CTRL1_6", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_NE2A1_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NW4END1_1", - "CMT_TOP_CLK1_5", - "CMT_TOP_WW4C1_0", - "CMT_TOP_EE4B3_3", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_WW4B2_2", - "CMT_TOP_NW4END1_7", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX10_10", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_WW4B3_6", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_WW4A3_5", - "CMT_TOP_LH1_0", - "CMT_TOP_WW4B1_10", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LH10_5", - "CMT_PLL_PHYCTRL_SYNC_BB_DN", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_IMUX15_0", - "CMT_TOP_EE4A1_5", - "CMT_TOP_NW2A3_12", - "CMT_TOP_EE4C2_9", - "CMT_TOP_SE2A3_1", - "CMT_TOP_BYP0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_WR1END0_11", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX8_5", - "CMT_TOP_WW4C2_9", - "CMT_TOP_CLK1_6", - "CMT_TOP_FAN6_11", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX27_12", - "CMT_TOP_NW4END3_9", - "CMT_TOP_WW4A2_3", - "CMT_TOP_IMUX25_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "CMT_TOP_IMUX17_3", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_PLL_PHASER_IN_D_ICLKDIV", - "CMT_TOP_LH1_8", - "CMT_TOP_LH11_1", - "CMT_TOP_IMUX3_5", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_FAN4_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_SE4C1_6", - "CMT_TOP_WR1END3_10", - "CMT_TOP_IMUX15_9", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_BYP0_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_LH2_10", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_SE4C1_11", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_PLL_PHASERD_CTSBUS0", - "CMT_PHASER_D_ICLKDIV_TOIOI", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", - "CMT_TOP_SW4A3_2", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_LH8_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_LH5_11", - "CMT_TOP_FAN4_4", - "CMT_TOP_WW4C3_0", - "CMT_TOP_EE4C2_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_SW2A1_11", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX35_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_IMUX38_9", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_SE4C2_1", - "CMT_TOP_CTRL0_1", - "CMT_TOP_IMUX2_4", - "CMT_TOP_EE2A0_12", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX16_2", - "CMT_TOP_SW4A1_4", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_NE4C1_11", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_NE2A1_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_IMUX17_5", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_CLK1_12", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_SW4END1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BYP1_4", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_NW4END0_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX26_4", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_BYP4_3", - "CMT_TOP_WL1END2_10", - "CMT_TOP_FAN5_2", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4C0_9", - "CMT_TOP_IMUX29_3", - "CMT_TOP_EE4C1_7", - "CMT_TOP_IMUX29_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4A2_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SW4END3_12", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_NW2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_EE4B0_3", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_SW4END2_11", - "CMT_TOP_WW4B2_8", - "CMT_TOP_SW4A2_9", - "CMT_TOP_NW4A2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4END0_9", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_NE2A3_7", - "CMT_TOP_FAN5_1", - "CMT_TOP_IMUX21_11", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_FAN1_11", - "CMT_TOP_IMUX32_6", - "CMT_TOP_SW4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_IMUX8_10", - "CMT_TOP_WW4A2_12", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX24_10", - "CMT_TOP_LH3_7", - "CMT_TOP_WR1END1_7", - "CMT_TOP_NW2A0_5", - "CMT_TOP_EE4B0_11", - "CMT_TOP_BYP3_1", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_LH9_2", - "CMT_TOP_WW2A2_4", - "CMT_TOP_IMUX41_9", - "CMT_TOP_BYP5_9", - "CMT_TOP_IMUX40_6", - "CMT_TOP_WL1END3_3", - "CMT_TOP_NW4A3_0", - "CMT_TOP_LH9_8", - "CMT_TOP_IMUX7_5", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_WW4A0_5", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_IMUX12_7", - "CMT_TOP_SW4A0_7", - "CMT_TOP_EE4A0_4", - "CMT_TOP_IMUX7_11", - "CMT_TOP_EE4B3_7", - "CMT_TOP_IMUX4_7", - "CMT_TOP_EE4C2_0", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4END1_12", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_SE4C0_0", - "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "CMT_TOP_WW4A1_0", - "CMT_TOP_LH1_2", - "CMT_TOP_SW4END0_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", - "CMT_TOP_FAN3_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_LH11_5", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_WR1END0_2", - "CMT_TOP_IMUX30_5", - "PLLOUT_CLK_FREQ_BB_1", - "CMT_TOP_NW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_WW4B3_8", - "CMT_TOP_IMUX0_1", - "CMT_TOP_WW2END2_8", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX38_7", - "CMT_TOP_NW2A1_3", - "CMT_TOP_EE4A2_5", - "CMT_TOP_NE2A2_0", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "CMT_PHASER_D_OCLKDIV_TOIOI", - "CMT_TOP_WW4C1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_WW4B2_11", - "CMT_TOP_CLK0_7", - "CMT_TOP_EE2A1_3", - "CMT_TOP_SW4END1_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_FAN7_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LH11_3", - "CMT_TOP_IMUX13_3", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_LH10_10", - "CMT_TOP_SW4A1_10", - "CMT_TOP_NW2A1_9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", - "CMT_TOP_NE4C0_6", - "CMT_TOP_BYP0_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", - "CMT_TOP_SE4C2_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_IMUX5_7", - "CMT_TOP_LH10_4", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX8_4", - "CMT_TOP_WL1END0_9", - "CMT_TOP_SW2A1_6", - "CMT_TOP_IMUX26_3", - "CMT_TOP_NW2A2_0", - "CMT_TOP_WW4END0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_SW4A0_12", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WR1END2_2", - "CMT_TOP_SE4C2_12", - "CMT_TOP_WW4C1_1", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_WW2A1_5", - "CMT_TOP_CTRL1_1", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_BYP7_3", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_WR1END0_10", - "CMT_TOP_IMUX45_0", - "CMT_TOP_WL1END1_7", - "CMT_TOP_LH2_7", - "CMT_TOP_WW4END1_2", - "CMT_TOP_LH7_7", - "CMT_TOP_IMUX26_8", - "CMT_TOP_BYP4_12", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_SE4C2_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_EE4A2_11", - "CMT_TOP_NW4END1_4", - "CMT_TOP_IMUX25_11", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_NW2A1_6", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_BYP2_4", - "CMT_TOP_NW4END2_3", - "CMT_TOP_WL1END0_11", - "CMT_TOP_IMUX18_10", - "CMT_TOP_EE4C1_8", - "CMT_TOP_WW2END1_4", - "CMT_PLL_PHASER_WRENABLE_TOFIFO", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_WW2END3_9", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE4C2_4", - "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_IMUX1_9", - "CMT_TOP_NW4A1_4", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_SW2A0_3", - "CMT_TOP_IMUX22_6", - "CMT_TOP_EE4C2_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", - "CMT_TOP_IMUX5_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_EE4C3_1", - "CMT_TOP_NE2A2_4", - "CMT_TOP_LH9_6", - "CMT_TOP_IMUX28_5", - "CMT_TOP_EE2A2_9", - "CMT_TOP_NW4A3_4", - "CMT_TOP_SW2A2_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LH2_9", - "CMT_TOP_WW2A2_2", - "CMT_TOP_IMUX3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_IMUX45_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_IMUX27_7", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_IMUX45_5", - "CMT_TOP_NW4END1_12", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_WW4C3_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", - "CMT_TOP_IMUX24_6", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_IMUX35_5", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_EE2A0_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "CMT_TOP_WW4B2_4", - "CMT_TOP_FAN2_8", - "CMT_TOP_SW2A1_0", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_WL1END0_5", - "CMT_TOP_CLK0_9", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX29_4", - "CMT_TOP_NE2A0_11", - "CMT_TOP_FAN2_3", - "CMT_TOP_NE4C2_1", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_IMUX31_5", - "CMT_TOP_WR1END1_5", - "PLL_CLK_FREQ_BB_BUFOUT_NS0", - "CMT_TOP_CTRL1_7", - "CMT_TOP_IMUX8_7", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_IMUX27_9", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4C3_8", - "CMT_TOP_BYP6_6", - "CMT_TOP_EE4C1_4", - "CMT_TOP_IMUX46_6", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4END0_7", - "CMT_TOP_SW4A1_12", - "CMT_TOP_CLK1_11", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_BYP3_8", - "CMT_TOP_WW4END2_12", - "CMT_TOP_IMUX16_8", - "CMT_TOP_SW4END3_7", - "CMT_TOP_WW2A1_4", - "CMT_TOP_LH2_12", - "CMT_TOP_WW2END3_0", - "CMT_TOP_SE2A0_5", - "CMT_TOP_WW2A1_0", - "CMT_TOP_NW4A2_5", - "CMT_TOP_EE2BEG1_8", - "PLLOUT_CLK_FREQ_BB_2", - "CMT_TOP_WW4END2_1", - "CMT_TOP_NW2A2_5", - "CMT_TOP_MONITOR_N_9", - "CMT_PLL_PHASERD_DQSBUS0", - "CMT_TOP_IMUX18_9", - "CMT_TOP_SE2A0_4", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_IMUX6_5", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_EE4A2_8", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX7_6", - "CMT_TOP_CTRL0_9", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_IMUX6_11", - "CMT_TOP_LH5_12", - "CMT_TOP_WW4B3_2", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_EE4C0_4", - "CMT_TOP_BYP2_1", - "CMT_TOP_IMUX36_8", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_NW2A3_5", - "CMT_TOP_IMUX27_3", - "CMT_TOP_LH7_11", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_WW4C2_2", - "CMT_TOP_BYP1_6", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_L_UPPER_T_FREQ_BB3", - "CMT_TOP_SE2A0_10", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_NW4END0_10", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_IMUX8_8", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX2_9", - "CMT_TOP_SE2A2_1", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_NE4C2_10", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX3_9", - "CMT_TOP_EE4A2_9", - "CMT_TOP_WW2A3_2", - "CMT_TOP_BYP5_0", - "CMT_TOP_NE4C2_8", - "CMT_TOP_BLOCK_OUTS_L_B1_12", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX17_9", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_IMUX0_8", - "CMT_TOP_NE4C3_5", - "CMT_TOP_WR1END3_9", - "CMT_TOP_EE4C3_9", - "CMT_TOP_IMUX35_8", - "CMT_TOP_BYP3_5", - "CMT_TOP_IMUX32_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_EE4C1_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_WW2END0_12", - "CMT_TOP_NW4A0_11", - "CMT_TOP_IMUX34_9", - "CMT_TOP_SE4C3_5", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX47_11", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_FAN6_4", - "CMT_TOP_IMUX21_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "CMT_TOP_WW2END0_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LH5_2", - "CMT_PLL_PHASER_IN_D_ICLK", - "CMT_TOP_IMUX17_4", - "CMT_TOP_SW2A1_8", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_PLL_PHASERD_DTSBUS0", - "CMT_TOP_NE4C1_9", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_LH3_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_WW2END0_4", - "CMT_TOP_EE2A1_7", - "CMT_TOP_NW2A2_11", - "CMT_TOP_WW2END3_6", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_WW4B0_11", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_WW2END2_12", - "CMT_PLL_PHASERREF_BELOW1", - "CMT_TOP_IMUX8_12", - "CMT_TOP_SW2A3_9", - "CMT_TOP_IMUX32_9", - "CMT_TOP_EE2A0_2", - "CMT_TOP_SW4END2_6", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_IMUX47_1", - "CMT_TOP_WW2A2_1", - "CMT_TOP_NW2A1_7", - "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "CMT_TOP_IMUX14_0", - "CMT_TOP_LH7_4", - "CMT_TOP_EE4C0_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX45_3", - "CMT_TOP_SW4END3_11", - "CMT_TOP_WW4C1_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX33_7", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_FAN4_11", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "CMT_TOP_LH5_4", - "CMT_TOP_CLK0_4", - "CMT_TOP_OCLK_9", - "CMT_TOP_IMUX22_8", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_WW4A3_4", - "CMT_TOP_NW4A1_6", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_IMUX41_12", - "CMT_TOP_SW4A3_4", - "CMT_TOP_NE2A0_10", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_LH8_7", - "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "CMT_TOP_IMUX32_5", - "CMT_TOP_SW2A1_5", - "PLLOUT_CLK_FREQ_BB_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_LOGIC_OUTS_L_B13_10" - ], - "sites": [ - { - "prefix": "PLLE2_ADV", - "y_coord": 0, - "type": "PLLE2_ADV", - "site_pins": { - "TESTOUT33": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", - "TESTOUT45": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", - "TESTOUT41": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", - "TESTOUT48": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", - "DI10": "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "TESTOUT8": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", - "DO8": "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "TESTOUT10": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", - "DADDR0": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "TESTIN16": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "TESTIN14": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "TESTOUT29": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", - "TESTIN7": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", - "TESTOUT14": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", - "TESTIN23": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "DADDR5": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "TESTIN28": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", - "TESTOUT24": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", - "DO15": "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "TESTOUT62": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", - "TESTIN1": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "DI8": "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "DI13": "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "TESTOUT51": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", - "TESTIN15": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "TESTOUT7": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", - "DI1": "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "TESTIN12": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "TESTOUT3": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", - "DI3": "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "TESTOUT31": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", - "DI9": "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "TESTOUT44": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", - "TESTOUT63": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", - "DO4": "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "TESTOUT21": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", - "DO10": "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "TESTOUT57": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", - "TESTOUT50": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", - "TESTIN10": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "DO11": "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "DI11": "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "TESTOUT15": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", - "TESTOUT40": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", - "CLKOUT1": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "TESTIN8": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", - "DO6": "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "TESTOUT60": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", - "TESTOUT20": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", - "DI14": "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "TESTOUT27": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", - "DO9": "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "DADDR6": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "DADDR4": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "DADDR1": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "TESTIN20": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "DO7": "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "TESTIN9": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", - "TESTIN19": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "TESTIN27": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", - "DI0": "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "TESTOUT28": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", - "TESTIN30": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", - "TESTOUT6": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", - "TMUXOUT": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", - "DEN": "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "TESTOUT42": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", - "TESTIN17": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "DO3": "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "CLKOUT2": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CLKOUT0": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "TESTOUT52": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", - "DI2": "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "TESTOUT9": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", - "DRDY": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "DCLK": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "RST": "CMT_TOP_R_UPPER_T_PLLE2_RST", - "DI7": "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "DO0": "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "PWRDWN": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "TESTOUT61": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", - "CLKINSEL": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "TESTOUT19": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", - "TESTOUT23": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", - "CLKIN1": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "TESTOUT30": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", - "TESTOUT18": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", - "DI15": "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "TESTIN6": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", - "TESTIN11": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "TESTIN4": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", - "DI12": "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "DO1": "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "DO5": "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "TESTOUT16": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", - "TESTOUT22": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", - "TESTIN31": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", - "CLKOUT4": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "DO2": "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "TESTOUT59": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", - "TESTIN5": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", - "TESTOUT11": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", - "TESTOUT58": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", - "DWE": "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "TESTOUT25": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", - "TESTOUT37": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", - "DI5": "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "TESTIN18": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "CLKFBIN": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CLKFBOUT": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "DI6": "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "TESTOUT26": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", - "TESTOUT35": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", - "TESTOUT32": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", - "TESTOUT0": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", - "TESTIN25": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "DO12": "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "TESTOUT53": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", - "TESTIN21": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "TESTOUT39": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", - "DO14": "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "TESTOUT46": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", - "CLKIN2": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "TESTOUT4": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", - "TESTOUT55": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", - "TESTOUT47": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", - "TESTOUT43": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", - "TESTOUT36": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", - "TESTIN2": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "DADDR2": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "TESTOUT54": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", - "CLKOUT5": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "TESTIN24": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "TESTIN29": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", - "TESTOUT38": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", - "LOCKED": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "TESTOUT56": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", - "CLKOUT3": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "TESTIN0": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "TESTIN13": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "TESTIN26": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", - "TESTOUT2": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", - "TESTOUT34": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", - "DI4": "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "TESTOUT49": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", - "TESTIN3": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", - "TESTIN22": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "TESTOUT17": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", - "TESTOUT5": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", - "TESTOUT13": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", - "DO13": "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "TESTOUT12": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", - "DADDR3": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "TESTOUT1": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX38_12->>CMT_TOP_R_UPPER_T_PLLE2_DI2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX38_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX35_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX35_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>CMT_TOP_L_UPPER_T_CLKPLL0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL0", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO0->>CMT_TOP_LOGIC_OUTS_L_B17_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX1_12->>CMT_TOP_R_UPPER_T_PLLE2_DI13": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX33_12->>CMT_TOP_R_UPPER_T_PLLE2_DI12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX33_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX39_12->>CMT_TOP_R_UPPER_T_PLLE2_DI0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX39_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX44_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO9->>CMT_TOP_LOGIC_OUTS_L_B5_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX13_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO6->>CMT_TOP_LOGIC_OUTS_L_B16_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO10->>CMT_TOP_LOGIC_OUTS_L_B23_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX2_11->>CMT_TOP_R_UPPER_T_PLLE2_DWE": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO2->>CMT_TOP_LOGIC_OUTS_L_B21_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS0": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS0", - "is_directional": "0", - "src_wire": "PLL_CLK_FREQ_BB0_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5->>CMT_TOP_L_UPPER_T_CLKPLL5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL5", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX47_10->>CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX2_12->>CMT_TOP_R_UPPER_T_PLLE2_DI11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX6_12->>CMT_TOP_R_UPPER_T_PLLE2_DI3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX6_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>PLLOUT_CLK_FREQ_BB_0": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_0", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_CLK1_0->>CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK1_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX3_12->>CMT_TOP_R_UPPER_T_PLLE2_DI9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->>CMT_TOP_L_UPPER_T_CLKPLL6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL6", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX34_12->>CMT_TOP_R_UPPER_T_PLLE2_DI10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_IN_D_ICLK->>CMT_PHASER_D_ICLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_IN_D_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKIN2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_CLKIN2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX1_11->>CMT_TOP_R_UPPER_T_PLLE2_DEN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO3->>CMT_TOP_LOGIC_OUTS_L_B15_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX5_12->>CMT_TOP_R_UPPER_T_PLLE2_DI5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX5_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS->>CMT_TOP_L_UPPER_T_FREQ_BB0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQ_BB0_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX0_12->>CMT_TOP_R_UPPER_T_PLLE2_DI15": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN->CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_L_CLKFBOUT2IN", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO15->>CMT_TOP_LOGIC_OUTS_L_B8_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->CMT_TOP_L_CLKFBOUT2IN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_CLKFBOUT2IN", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO8->>CMT_TOP_LOGIC_OUTS_L_B19_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX7_12->>CMT_TOP_R_UPPER_T_PLLE2_DI1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX7_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKIN1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_CLKIN1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX15_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR1": { "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX15_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS->>CMT_TOP_L_UPPER_T_FREQ_BB2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", "is_directional": "1", - "src_wire": "PLL_CLK_FREQ_BB2_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK1X_90->>CMT_PHASER_D_OCLK90_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_OCLK90_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK1X_90", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX47_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_11", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX32_12->>CMT_TOP_R_UPPER_T_PLLE2_DI14": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX0_11->>CMT_TOP_R_UPPER_T_PLLE2_PWRDWN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO13->>CMT_TOP_LOGIC_OUTS_L_B0_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS->>CMT_TOP_L_UPPER_T_FREQ_BB3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQ_BB3_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX22_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX22_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO1->>CMT_TOP_LOGIC_OUTS_L_B7_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_IN_D_ICLKDIV->>CMT_PHASER_D_ICLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_IN_D_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4->>CMT_TOP_L_UPPER_T_CLKPLL4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL4", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>PLLOUT_CLK_FREQ_BB_3": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_3", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS2": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS2", - "is_directional": "0", - "src_wire": "PLL_CLK_FREQ_BB2_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>CMT_TOP_L_UPPER_T_CLKPLL2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL2", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO4->>CMT_TOP_LOGIC_OUTS_L_B20_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS->>CMT_TOP_L_UPPER_T_FREQ_BB1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQ_BB1_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX13_10->>CMT_TOP_R_UPPER_T_PLLE2_RST": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_10", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_DN<<->>CMT_PLL_PHYCTRL_SYNC_BB_UP": { - "can_invert": "0", - "dst_wire": "CMT_PLL_PHYCTRL_SYNC_BB_UP", - "is_directional": "0", - "src_wire": "CMT_PLL_PHYCTRL_SYNC_BB_DN", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS3": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS3", - "is_directional": "0", - "src_wire": "PLL_CLK_FREQ_BB3_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX37_12->>CMT_TOP_R_UPPER_T_PLLE2_DI4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX37_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX3_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_CLK0_12->>CMT_TOP_R_UPPER_T_PLLE2_DCLK": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>PLLOUT_CLK_FREQ_BB_1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO7->>CMT_TOP_LOGIC_OUTS_L_B10_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO12->>CMT_TOP_LOGIC_OUTS_L_B22_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B21_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_11", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS1": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS1", - "is_directional": "0", - "src_wire": "PLL_CLK_FREQ_BB1_NS", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>PLLOUT_CLK_FREQ_BB_2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_2", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKFBIN->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_CLKFBIN", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO14->>CMT_TOP_LOGIC_OUTS_L_B18_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO5->>CMT_TOP_LOGIC_OUTS_L_B2_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX36_12->>CMT_TOP_R_UPPER_T_PLLE2_DI6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX36_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>CMT_TOP_L_UPPER_T_CLKPLL1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO11->>CMT_TOP_LOGIC_OUTS_L_B13_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK->>CMT_PHASER_D_OCLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX35_12->>CMT_TOP_R_UPPER_T_PLLE2_DI8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX35_12", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_CLK0_0->>CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1" }, "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLKDIV->>CMT_PHASER_D_OCLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_OUT_D_OCLKDIV", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>PLLOUT_CLK_FREQ_BB_0": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_DQSBUS0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_0" }, - "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "src_wire": "CMT_PLL_PHASERD_DQSBUS1", "is_directional": "1", - "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7" }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>PLLOUT_CLK_FREQ_BB_3": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_7", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_3" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO9->>CMT_TOP_LOGIC_OUTS_L_B5_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX2_12->>CMT_TOP_R_UPPER_T_PLLE2_DI11": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI11" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX47_10->>CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS1": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB1_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS1" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "can_invert": "0", "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_DN<<->>CMT_PLL_PHYCTRL_SYNC_BB_UP": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHYCTRL_SYNC_BB_DN", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CMT_PLL_PHYCTRL_SYNC_BB_UP" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX7_12->>CMT_TOP_R_UPPER_T_PLLE2_DI1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX7_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI1" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_IN_D_ICLK->>CMT_PHASER_D_ICLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_IN_D_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_ICLK_TOIOI" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX36_12->>CMT_TOP_R_UPPER_T_PLLE2_DI6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX36_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI6" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS->>CMT_TOP_L_UPPER_T_FREQ_BB2": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB2_NS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO14->>CMT_TOP_LOGIC_OUTS_L_B18_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX47_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX3_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX0_11->>CMT_TOP_R_UPPER_T_PLLE2_PWRDWN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO3->>CMT_TOP_LOGIC_OUTS_L_B15_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO0->>CMT_TOP_LOGIC_OUTS_L_B17_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX37_12->>CMT_TOP_R_UPPER_T_PLLE2_DI4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX37_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI4" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKIN1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_CLKIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX1_11->>CMT_TOP_R_UPPER_T_PLLE2_DEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DEN" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKIN2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_CLKIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" }, "CMT_TOP_L_UPPER_T.CMT_TOP_CLK0_1->>CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT": { "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", - "is_directional": "1", "src_wire": "CMT_TOP_CLK0_1", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK1X_90_7", "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK90_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT->>CMT_TOP_L_UPPER_T_CLKPLL7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL7", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>CMT_TOP_L_UPPER_T_CLKPLL3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL3", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_DTSBUS1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT" }, "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX4_12->>CMT_TOP_R_UPPER_T_PLLE2_DI7": { "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX4_12", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI7" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_CLK0_0->>CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX0_12->>CMT_TOP_R_UPPER_T_PLLE2_DI15": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI15" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK90_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_7" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO8->>CMT_TOP_LOGIC_OUTS_L_B19_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX3_12->>CMT_TOP_R_UPPER_T_PLLE2_DI9": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI9" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO4->>CMT_TOP_LOGIC_OUTS_L_B20_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX13_10->>CMT_TOP_R_UPPER_T_PLLE2_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_RST" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK->>CMT_PHASER_D_OCLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLK_TOIOI" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>CMT_TOP_L_UPPER_T_CLKPLL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL2" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->CMT_TOP_L_CLKFBOUT2IN": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_CLKFBOUT2IN" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS3": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB3_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS3" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX44_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX35_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX35_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_CLK0_12->>CMT_TOP_R_UPPER_T_PLLE2_DCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DCLK" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->>CMT_TOP_L_UPPER_T_CLKPLL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL6" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX33_12->>CMT_TOP_R_UPPER_T_PLLE2_DI12": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX33_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI12" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO2->>CMT_TOP_LOGIC_OUTS_L_B21_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO12->>CMT_TOP_LOGIC_OUTS_L_B22_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>CMT_TOP_L_UPPER_T_CLKPLL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL3" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX34_12->>CMT_TOP_R_UPPER_T_PLLE2_DI10": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI10" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX1_12->>CMT_TOP_R_UPPER_T_PLLE2_DI13": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI13" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX39_12->>CMT_TOP_R_UPPER_T_PLLE2_DI0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX39_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLKDIV->>CMT_PHASER_D_OCLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLKDIV_TOIOI" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO13->>CMT_TOP_LOGIC_OUTS_L_B0_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT->>CMT_TOP_L_UPPER_T_CLKPLL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL7" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>CMT_TOP_L_UPPER_T_CLKPLL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL1" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX2_11->>CMT_TOP_R_UPPER_T_PLLE2_DWE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DWE" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS0": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB0_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS0" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO1->>CMT_TOP_LOGIC_OUTS_L_B7_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO7->>CMT_TOP_LOGIC_OUTS_L_B10_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO11->>CMT_TOP_LOGIC_OUTS_L_B13_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS->>CMT_TOP_L_UPPER_T_FREQ_BB3": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB3_NS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>CMT_TOP_L_UPPER_T_CLKPLL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL0" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK1X_90->>CMT_PHASER_D_OCLK90_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLK90_TOIOI" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_CLK1_0->>CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO15->>CMT_TOP_LOGIC_OUTS_L_B8_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5->>CMT_TOP_L_UPPER_T_CLKPLL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL5" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO5->>CMT_TOP_LOGIC_OUTS_L_B2_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO6->>CMT_TOP_LOGIC_OUTS_L_B16_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX5_12->>CMT_TOP_R_UPPER_T_PLLE2_DI5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX5_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI5" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX22_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX22_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B21_11": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_11" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS2": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB2_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS2" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX35_12->>CMT_TOP_R_UPPER_T_PLLE2_DI8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX35_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI8" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX38_12->>CMT_TOP_R_UPPER_T_PLLE2_DI2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX38_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI2" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS->>CMT_TOP_L_UPPER_T_FREQ_BB0": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB0_NS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX13_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO10->>CMT_TOP_LOGIC_OUTS_L_B23_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_12" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX32_12->>CMT_TOP_R_UPPER_T_PLLE2_DI14": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI14" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_IMUX6_12->>CMT_TOP_R_UPPER_T_PLLE2_DI3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX6_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI3" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASER_IN_D_ICLKDIV->>CMT_PHASER_D_ICLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_IN_D_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_ICLKDIV_TOIOI" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_11": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_11" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4->>CMT_TOP_L_UPPER_T_CLKPLL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL4" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN->CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_CLKFBOUT2IN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKFBIN->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_CLKFBIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>PLLOUT_CLK_FREQ_BB_2": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_2" + }, + "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS->>CMT_TOP_L_UPPER_T_FREQ_BB1": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB1_NS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_L_UPPER_T.CMT_PLL_PHASERD_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7" + }, + "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>PLLOUT_CLK_FREQ_BB_1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_1" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_12" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5" + }, + "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6" } }, - "tile_type": "CMT_TOP_L_UPPER_T" + "wires": [ + "CMT_TOP_NW4A2_6", + "CMT_TOP_WW2END3_2", + "CMT_TOP_BYP1_3", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_WW4A3_11", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_WW2A1_12", + "CMT_TOP_LH7_10", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_NW4A1_2", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_WW2A1_6", + "CMT_TOP_WW4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4END1_8", + "CMT_PHASER_D_OCLK_TOIOI", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WW4END2_8", + "CMT_TOP_IMUX7_3", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NE4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_LH3_8", + "CMT_TOP_WW4B0_5", + "CMT_TOP_LH12_10", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX36_7", + "CMT_TOP_NE4C0_9", + "CMT_TOP_IMUX32_8", + "CMT_TOP_IMUX17_10", + "CMT_TOP_IMUX7_9", + "CMT_TOP_SW4END0_1", + "CMT_TOP_WW2END3_5", + "CMT_TOP_IMUX12_8", + "CMT_TOP_NW4END3_1", + "CMT_PLL_PHASER_OUT_D_OCLK1X_90", + "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "CMT_TOP_NE2A3_0", + "CMT_TOP_CLK1_3", + "CMT_TOP_WR1END0_8", + "CMT_TOP_FAN2_8", + "CMT_TOP_IMUX29_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_PLL_PHASERREF0", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_EE4B3_0", + "CMT_TOP_BYP4_1", + "CMT_TOP_NE2A3_12", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_OCLK_7", + "CMT_TOP_WW4C0_11", + "CMT_TOP_WW4C0_3", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_EE2A0_9", + "CMT_TOP_LH2_9", + "CMT_TOP_IMUX1_1", + "CMT_TOP_SE4C1_10", + "CMT_TOP_NW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_SE4C2_9", + "CMT_TOP_IMUX35_6", + "CMT_TOP_WW2A3_12", + "CMT_TOP_EE4A0_6", + "CMT_TOP_SE4C0_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_WL1END1_9", + "CMT_TOP_BYP5_12", + "CMT_TOP_EE4C0_9", + "CMT_TOP_WW2END1_3", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_IMUX3_4", + "CMT_TOP_NE2A1_0", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_IMUX39_7", + "CMT_PLL_PHASERD_DTSBUS1", + "CMT_TOP_IMUX14_2", + "CMT_TOP_WW4C3_2", + "CMT_TOP_EE4B3_8", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW4END1_5", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_EE4A2_7", + "CMT_TOP_EE2A0_1", + "CMT_TOP_LOGIC_OUTS_L_B10_12", + "CMT_TOP_WW4B0_6", + "CMT_TOP_IMUX12_9", + "CMT_TOP_WW4A0_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_NE4BEG2_12", + "CMT_TOP_WW2A1_11", + "CMT_TOP_IMUX23_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", + "CMT_TOP_IMUX26_12", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B13_12", + "CMT_TOP_IMUX1_3", + "CMT_TOP_SE4C1_9", + "CMT_TOP_WW2A0_9", + "CMT_TOP_WW4C1_11", + "CMT_TOP_BYP7_3", + "CMT_TOP_EE4A0_9", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX30_7", + "CMT_TOP_ICLK_4", + "CMT_TOP_BYP5_9", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX30_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_WW2A0_5", + "CMT_TOP_WW4C1_0", + "CMT_TOP_WL1END2_11", + "CMT_TOP_IMUX14_3", + "CMT_TOP_EE4B1_9", + "CMT_TOP_SW4END1_5", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_NE2A0_2", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "CMT_TOP_WW4C2_11", + "CMT_TOP_NW2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_FAN3_8", + "CMT_TOP_IMUX27_7", + "CMT_TOP_WW4END1_1", + "CMT_TOP_FAN4_11", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LH8_6", + "CMT_TOP_FAN0_12", + "CMT_TOP_EE4A0_1", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_SW4END1_9", + "CMT_TOP_WL1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4END1_6", + "CMT_TOP_WL1END2_4", + "CMT_TOP_WR1END0_9", + "CMT_TOP_LH5_9", + "CMT_TOP_IMUX11_4", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_IMUX3_3", + "CMT_TOP_BYP7_4", + "CMT_TOP_WW4B0_12", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_SW4A2_0", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_SE4BEG1_12", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_LOGIC_OUTS_L_B17_12", + "CMT_PLL_PHASERREF_ABOVE0", + "CMT_TOP_WW4A1_9", + "CMT_TOP_EE2A0_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH4_7", + "CMT_TOP_IMUX8_11", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B23_12", + "CMT_TOP_LH4_11", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "CMT_TOP_EE4A1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_IMUX14_4", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_IMUX14_12", + "CMT_TOP_CTRL0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_EE4A0_3", + "CMT_TOP_IMUX11_12", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX43_3", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LH11_11", + "CMT_TOP_FAN1_5", + "CMT_TOP_NW2A0_7", + "CMT_TOP_EE4B2_1", + "CMT_TOP_BYP2_12", + "CMT_TOP_IMUX31_7", + "CMT_TOP_WW4B2_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX6_10", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_IMUX47_0", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_IMUX21_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_FAN4_9", + "PLL_CLK_FREQ_BB_BUFOUT_NS1", + "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_CLK0_0", + "CMT_TOP_LH9_7", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END3_7", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_IMUX5_11", + "CMT_TOP_EE4B2_9", + "CMT_TOP_IMUX33_12", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_NW2A1_2", + "CMT_TOP_SW4END1_1", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_PLL_PHASERD_CTSBUS0", + "CMT_TOP_NW4A1_1", + "CMT_TOP_NW2A0_12", + "CMT_TOP_BYP3_9", + "CMT_TOP_WW2A2_4", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_SW4A0_9", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_NE2A0_11", + "CMT_TOP_EE4A3_4", + "CMT_TOP_SE4C2_5", + "CMT_TOP_WW4END2_7", + "CMT_TOP_EE4A2_11", + "CMT_TOP_LH9_5", + "CMT_TOP_NE2A0_3", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_IMUX46_9", + "CMT_TOP_EE2A2_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_IMUX33_11", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_IMUX26_4", + "CMT_TOP_IMUX38_1", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WR1END0_11", + "CMT_TOP_FAN4_10", + "CMT_TOP_FAN2_11", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_BYP1_8", + "CMT_TOP_IMUX31_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EE4C3_9", + "CMT_TOP_IMUX36_8", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SW4A1_0", + "CMT_TOP_SE2A1_10", + "CMT_TOP_EE4C0_5", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_LH7_0", + "CMT_TOP_IMUX33_7", + "CMT_TOP_SE4C1_2", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_FAN7_10", + "CMT_TOP_LH2_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", + "CMT_TOP_NE4C2_1", + "CMT_TOP_SW4A2_7", + "CMT_TOP_IMUX23_11", + "CMT_TOP_WR1END1_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", + "CMT_TOP_NE2A0_10", + "CMT_TOP_SW4END2_0", + "CMT_TOP_LH8_0", + "CMT_TOP_EE4C0_3", + "CMT_TOP_NW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_IMUX8_6", + "CMT_TOP_LH6_12", + "CMT_TOP_BYP0_7", + "CMT_TOP_LH5_0", + "CMT_TOP_IMUX5_2", + "CMT_TOP_WL1END2_6", + "CMT_TOP_BYP1_9", + "CMT_TOP_IMUX9_3", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX47_1", + "CMT_TOP_WW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_EE2A1_9", + "CMT_TOP_ER1BEG1_12", + "CMT_TOP_NE4C3_4", + "CMT_TOP_EE4B2_7", + "CMT_TOP_OCLK_5", + "CMT_TOP_NE2A1_6", + "CMT_TOP_IMUX45_4", + "CMT_TOP_IMUX8_2", + "CMT_TOP_IMUX1_2", + "CMT_TOP_IMUX46_0", + "CMT_TOP_EE4C1_9", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_LH1_7", + "CMT_TOP_BYP5_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", + "CMT_TOP_EE4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_12", + "CMT_TOP_IMUX40_4", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", + "CMT_TOP_BYP7_0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SW4A3_12", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4A3_6", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_EE4BEG0_12", + "CMT_TOP_IMUX17_11", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_WR1END2_5", + "CMT_TOP_EE4A0_4", + "CMT_TOP_SE2A1_12", + "CMT_TOP_SW4A0_3", + "CMT_TOP_IMUX6_12", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX11_6", + "CMT_TOP_IMUX25_7", + "CMT_TOP_IMUX4_8", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_WW4END3_12", + "CMT_TOP_WR1END3_12", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX3_9", + "CMT_TOP_NW4END0_5", + "CMT_TOP_NE4C3_10", + "CMT_TOP_WW4END1_12", + "CMT_TOP_SE2A3_6", + "CMT_TOP_IMUX7_4", + "CMT_TOP_LH3_11", + "CMT_TOP_BYP5_6", + "CMT_TOP_WW4C2_5", + "CMT_TOP_LH7_6", + "CMT_TOP_LOGIC_OUTS_L_B12_12", + "CMT_TOP_SE2A1_5", + "CMT_TOP_FAN4_7", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH9_2", + "CMT_TOP_LH2_12", + "CMT_TOP_BYP0_1", + "CMT_TOP_LH11_0", + "CMT_TOP_IMUX14_0", + "CMT_TOP_IMUX27_9", + "CMT_TOP_NW2A1_5", + "CMT_TOP_IMUX21_7", + "CMT_TOP_WW4A0_2", + "CMT_TOP_NE2A1_11", + "CMT_TOP_IMUX7_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX23_7", + "CMT_TOP_NW4A1_12", + "CMT_TOP_IMUX10_10", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4C1_2", + "CMT_TOP_LH4_3", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH5_6", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW4C1_4", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_FAN4_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_IMUX9_9", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NW4A3_5", + "CMT_TOP_BYP0_11", + "CMT_TOP_EE2BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_IMUX33_2", + "CMT_TOP_BYP2_1", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_SE2A3_8", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_IMUX25_9", + "CMT_TOP_WW2END1_2", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_LH8_12", + "CMT_TOP_EE4B2_2", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_IMUX13_9", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_ICLKDIV_12", + "CMT_TOP_NW2A2_7", + "CMT_TOP_OCLKDIV_11", + "CMT_TOP_IMUX5_8", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_IMUX33_5", + "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WW4END2_11", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE2A0_7", + "CMT_TOP_WR1END1_10", + "CMT_TOP_FAN0_9", + "CMT_TOP_EE4C2_10", + "CMT_TOP_SW4END3_0", + "CMT_TOP_L_UPPER_T_CLKIN2", + "CMT_TOP_WR1END1_2", + "CMT_TOP_NW4A1_5", + "CMT_TOP_EE4B3_12", + "CMT_TOP_IMUX4_9", + "CMT_TOP_IMUX47_8", + "CMT_TOP_WW4C1_3", + "CMT_TOP_IMUX26_9", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_IMUX41_2", + "CMT_TOP_SE4C1_5", + "CMT_TOP_WL1END2_7", + "CMT_TOP_WW4A0_1", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_CTRL0_4", + "CMT_TOP_NW4END2_3", + "CMT_TOP_SE2A2_8", + "CMT_TOP_WW4C2_3", + "CMT_TOP_WW2A3_3", + "CMT_TOP_WL1END3_4", + "CMT_TOP_NE2A2_8", + "CMT_TOP_SW2A0_9", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_SW2A0_8", + "CMT_TOP_WW4B3_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_SW4A3_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "CMT_TOP_SE4C0_7", + "CMT_TOP_IMUX1_10", + "CMT_TOP_IMUX4_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", + "CMT_TOP_IMUX40_2", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX1_6", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_IMUX14_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_IMUX7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WW4A2_4", + "CMT_TOP_WW4B1_7", + "CMT_TOP_EE2A1_6", + "CMT_TOP_IMUX19_2", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_IMUX25_12", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_FAN3_4", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP7_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX24_10", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_IMUX19_12", + "CMT_TOP_SW2A0_2", + "CMT_TOP_BYP7_8", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX47_7", + "CMT_TOP_BYP0_4", + "CMT_TOP_IMUX21_6", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_EE4A3_11", + "CMT_TOP_IMUX5_4", + "CMT_TOP_SE2A3_10", + "CMT_TOP_SW4END2_10", + "CMT_TOP_NW2A0_5", + "CMT_TOP_NE4C1_2", + "CMT_TOP_WW4C0_9", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_WW2END0_1", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX0_0", + "CMT_TOP_IMUX15_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SW2A2_4", + "CMT_TOP_WW4C2_0", + "CMT_TOP_ICLK_8", + "CMT_TOP_NW2A1_7", + "CMT_TOP_CTRL0_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_NE4BEG1_9", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_WW4A0_6", + "CMT_TOP_IMUX6_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WR1END0_1", + "CMT_TOP_CLK0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_LH10_12", + "CMT_TOP_SE4BEG0_1", + "CMT_PLL_PHASER_RDCLK_TOFIFO", + "CMT_TOP_SW2A1_4", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_IMUX27_1", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_IMUX23_9", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_IMUX30_6", + "CMT_TOP_NW4END1_9", + "CMT_TOP_IMUX39_2", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX10_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_WW4END3_0", + "CMT_TOP_NW4END1_11", + "CMT_TOP_LOGIC_OUTS_L_B15_12", + "CMT_TOP_EE4C2_8", + "CMT_TOP_SW4A3_11", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_IMUX16_3", + "CMT_TOP_LH2_2", + "CMT_TOP_OCLK_8", + "CMT_TOP_NE2A0_6", + "CMT_TOP_WW2A3_2", + "CMT_TOP_IMUX43_11", + "CMT_TOP_CTRL1_6", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_EE4A0_8", + "CMT_TOP_SE4C1_3", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_IMUX8_5", + "CMT_TOP_IMUX9_1", + "CMT_TOP_WW4A0_9", + "CMT_TOP_EE4A3_8", + "PLLOUT_CLK_FREQ_BB_3", + "CMT_TOP_IMUX37_5", + "CMT_TOP_SW4A1_12", + "CMT_TOP_IMUX11_10", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX44_2", + "CMT_TOP_IMUX28_6", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_IMUX40_10", + "CMT_TOP_EE2A2_12", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_CLK0_1", + "CMT_TOP_SW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX23_1", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_WW2END1_6", + "CMT_TOP_SW2A0_1", + "CMT_TOP_CTRL1_3", + "CMT_TOP_IMUX10_7", + "CMT_TOP_LOGIC_OUTS_L_B20_12", + "CMT_TOP_NE4C2_8", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_IMUX6_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", + "CMT_TOP_NW2A3_4", + "CMT_TOP_WR1END2_9", + "CMT_TOP_IMUX27_8", + "CMT_TOP_LH6_3", + "CMT_TOP_NE2A1_1", + "CMT_TOP_CLK0_9", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_BYP0_9", + "CMT_TOP_EE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_SW2A2_12", + "CMT_TOP_WW2END1_1", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_EE2A0_4", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_FAN1_7", + "CMT_TOP_WW4A3_3", + "CMT_TOP_NW4END3_2", + "CMT_TOP_SW4END2_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", + "CMT_TOP_EE4A3_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", + "CMT_TOP_EE4A1_0", + "CMT_TOP_SW4A2_9", + "CMT_TOP_LH3_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_IMUX41_0", + "CMT_TOP_IMUX32_6", + "CMT_TOP_WR1END3_4", + "CMT_TOP_BYP7_12", + "CMT_TOP_SW2A1_11", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX11_7", + "CMT_TOP_SW2A2_5", + "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "CMT_TOP_FAN5_0", + "CMT_TOP_WW2END2_7", + "CMT_TOP_NW4A2_10", + "CMT_TOP_SW4END1_8", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_IMUX17_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_WR1END0_12", + "CMT_TOP_WW2A1_8", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_IMUX4_10", + "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "CMT_TOP_FAN6_9", + "CMT_TOP_NW2A2_0", + "CMT_TOP_IMUX11_2", + "CMT_TOP_IMUX21_12", + "CMT_TOP_IMUX1_9", + "CMT_TOP_WW2A3_9", + "CMT_TOP_WW4B3_11", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_LOGIC_OUTS_L_B18_12", + "CMT_TOP_WW4END2_3", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_WW4END0_7", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_LH6_10", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4END1_12", + "CMT_TOP_IMUX41_7", + "CMT_PLL_PHASER_IN_D_ICLKDIV", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_NE2A2_6", + "CMT_TOP_IMUX37_2", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WR1END1_7", + "CMT_TOP_IMUX14_9", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_IMUX7_2", + "CMT_TOP_FAN2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_TOP_WW4A0_7", + "CMT_TOP_EE4C0_8", + "CMT_TOP_SE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", + "CMT_TOP_WR1END3_8", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_IMUX37_1", + "CMT_TOP_LOGIC_OUTS_L_B19_12", + "CMT_TOP_NW2A1_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX7_12", + "CMT_TOP_NW2A2_3", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A2_6", + "CMT_TOP_EE4C0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_FAN3_11", + "CMT_TOP_SW4END0_0", + "CMT_PLL_PHASER_OUT_D_OCLKDIV", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", + "CMT_TOP_NE4C3_11", + "CMT_TOP_IMUX37_6", + "CMT_TOP_BYP5_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_LH8_4", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SE4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_IMUX46_5", + "PLLOUT_CLK_FREQ_BB_0", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_LH8_8", + "CMT_TOP_NE4C3_9", + "CMT_TOP_WW4B1_1", + "CMT_TOP_BLOCK_OUTS_L_B2_12", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX26_10", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_L_UPPER_T_FREQ_BB2", + "CMT_TOP_IMUX2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_IMUX36_4", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SW2A0_3", + "CMT_TOP_EE4A1_10", + "CMT_TOP_SW2A3_8", + "CMT_TOP_WW2A2_5", + "CMT_TOP_IMUX24_11", + "CMT_TOP_SW2A2_9", + "CMT_TOP_FAN5_12", + "CMT_TOP_SW4A0_6", + "CMT_TOP_IMUX38_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", + "CMT_TOP_WR1END0_5", + "CMT_TOP_IMUX4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_CTRL0_11", + "CMT_TOP_IMUX19_8", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_IMUX36_5", + "CMT_TOP_WW2A0_3", + "CMT_TOP_LH10_5", + "CMT_TOP_NE4C3_3", + "CMT_TOP_FAN7_2", + "CMT_TOP_IMUX7_10", + "CMT_TOP_WW4B1_11", + "CMT_TOP_BYP6_1", + "CMT_TOP_WL1END2_1", + "CMT_TOP_SW4A0_2", + "CMT_TOP_IMUX10_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_OCLK_10", + "CMT_TOP_LH5_2", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_SW2A2_6", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_L_UPPER_T_CLKPLL6", + "CMT_TOP_NW4END3_6", + "CMT_TOP_L_UPPER_T_FREQ_BB0", + "CMT_TOP_NW4END3_8", + "CMT_TOP_WL1END0_7", + "CMT_TOP_IMUX10_11", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX9_7", + "CMT_TOP_BYP5_7", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_SW2A1_6", + "CMT_TOP_IMUX18_11", + "CMT_TOP_IMUX37_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_EE4B2_8", + "CMT_TOP_WW2A1_10", + "CMT_TOP_IMUX22_12", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_IMUX42_5", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LH8_10", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_IMUX24_5", + "CMT_TOP_NW2A2_10", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_SW2A2_8", + "CMT_TOP_EE4B2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", + "CMT_TOP_FAN1_12", + "CMT_TOP_FAN5_6", + "CMT_TOP_FAN3_3", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_EE2A1_3", + "CMT_TOP_IMUX24_9", + "CMT_TOP_SE2A2_2", + "CMT_TOP_IMUX25_10", + "CMT_TOP_SE4C3_0", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_EE2A1_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", + "CMT_TOP_IMUX45_6", + "CMT_TOP_SW4END0_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX3_8", + "CMT_TOP_WW2END2_12", + "CMT_TOP_WR1END2_12", + "CMT_TOP_WW2END1_9", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_LH6_8", + "CMT_TOP_OCLK_11", + "CMT_TOP_BYP1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_SW4A1_4", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_IMUX40_9", + "CMT_TOP_IMUX25_11", + "CMT_TOP_LH10_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_SE4C2_12", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_WW4END3_3", + "CMT_TOP_WW4B3_2", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_FAN3_0", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_WW4B3_12", + "CMT_TOP_IMUX32_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_EE4A0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4END0_12", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_FAN0_11", + "CMT_TOP_SE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_IMUX44_4", + "CMT_TOP_SW4A2_11", + "CMT_TOP_SW4END0_9", + "CMT_TOP_EE4C1_5", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_IMUX29_4", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX32_0", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_SW4END2_3", + "CMT_TOP_BYP4_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_FAN5_4", + "CMT_TOP_EE2A2_2", + "CMT_TOP_EE4A2_1", + "CMT_TOP_EE2A2_11", + "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "CMT_TOP_NW4A2_11", + "CMT_TOP_NW4END3_10", + "CMT_TOP_OCLK1X_90_12", + "CMT_TOP_WW4END0_8", + "CMT_TOP_LH11_8", + "CMT_TOP_IMUX45_5", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WR1END0_6", + "CMT_TOP_IMUX3_1", + "CMT_TOP_IMUX10_12", + "CMT_TOP_WW4END3_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_IMUX16_2", + "CMT_TOP_IMUX34_10", + "CMT_TOP_FAN4_4", + "CMT_TOP_FAN7_3", + "CMT_TOP_LH4_0", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "CMT_TOP_FAN3_9", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_IMUX22_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_EE4C3_6", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_BYP1_10", + "CMT_TOP_FAN7_0", + "CMT_PLL_PHASER_WRCLK_TOFIFO", + "CMT_TOP_FAN2_9", + "CMT_TOP_WW2A0_11", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_SW4A1_2", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_IMUX4_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_SE4BEG1_11", + "PLL_CLK_FREQ_BB_BUFOUT_NS3", + "CMT_TOP_IMUX26_2", + "CMT_TOP_BYP5_11", + "CMT_TOP_BYP2_10", + "CMT_TOP_FAN1_8", + "CMT_TOP_LH8_11", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_IMUX11_8", + "CMT_TOP_SE4C2_10", + "CMT_PLL_PHASER_WRENABLE_TOFIFO", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX5_6", + "CMT_TOP_IMUX38_0", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "CMT_TOP_LH2_10", + "CMT_TOP_CLK1_7", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4B3_1", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_IMUX16_5", + "CMT_TOP_CLK1_4", + "CMT_TOP_LH8_3", + "CMT_TOP_IMUX22_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_LH4_12", + "CMT_TOP_IMUX45_2", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_NE4C0_11", + "CMT_TOP_EE4B1_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", + "CMT_TOP_IMUX15_10", + "CMT_TOP_BYP2_4", + "CMT_TOP_WW4C0_0", + "CMT_TOP_SW2A1_7", + "CMT_TOP_EE4B3_1", + "CMT_TOP_SE4C3_3", + "CMT_TOP_WW4END1_9", + "CMT_TOP_EE4B1_12", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_SW4END1_4", + "CMT_TOP_IMUX12_12", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_WW2A0_7", + "CMT_TOP_IMUX34_7", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_WW2A2_12", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX27_4", + "CMT_TOP_OCLK_1", + "CMT_TOP_NW4END0_2", + "CMT_TOP_EE2A1_5", + "CMT_TOP_FAN4_2", + "CMT_TOP_CTRL1_11", + "CMT_TOP_WW4C3_8", + "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "CMT_TOP_NW4END1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", + "CMT_TOP_FAN3_1", + "CMT_TOP_IMUX45_9", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", + "CMT_TOP_WR1END3_9", + "CMT_TOP_SW4END2_11", + "CMT_TOP_WR1END2_6", + "CMT_TOP_SE2A2_5", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_FAN2_7", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW2END2_11", + "CMT_TOP_L_UPPER_T_FREQ_BB3", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_SW4A3_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", + "CMT_TOP_NE2A2_12", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX42_6", + "CMT_TOP_EE4B1_1", + "CMT_TOP_BYP0_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_CLK1_11", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_EE4C3_11", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_IMUX32_10", + "CMT_TOP_NW4A0_4", + "CMT_TOP_EL1BEG2_12", + "CMT_TOP_SW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_NW4END2_8", + "CMT_TOP_SE2A3_12", + "CMT_TOP_EE2A0_10", + "CMT_TOP_EE2A3_9", + "CMT_TOP_SW2A1_1", + "CMT_TOP_EE4B2_4", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX18_0", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_BYP6_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", + "CMT_TOP_NW4END1_6", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_LH7_4", + "CMT_TOP_IMUX23_0", + "CMT_TOP_IMUX43_8", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX21_4", + "CMT_TOP_L_UPPER_T_CLKPLL2", + "CMT_TOP_IMUX21_2", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_EE4A2_9", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE4B0_5", + "CMT_TOP_IMUX47_10", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_6", + "CMT_TOP_WW4C0_1", + "CMT_TOP_WW2A3_0", + "CMT_TOP_FAN7_1", + "CMT_TOP_MONITOR_P_12", + "CMT_TOP_NW2A1_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_LH1_10", + "CMT_TOP_EE4BEG2_12", + "CMT_TOP_EE4B0_10", + "CMT_TOP_SE2A3_2", + "CMT_TOP_IMUX16_6", + "CMT_TOP_IMUX1_5", + "CMT_TOP_SE4C1_4", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "CMT_TOP_NW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_EE4B3_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", + "CMT_TOP_IMUX26_7", + "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "CMT_TOP_NE4C1_0", + "CMT_TOP_EE2A3_8", + "CMT_TOP_IMUX45_11", + "CMT_TOP_FAN4_12", + "CMT_TOP_ER1BEG2_12", + "CMT_TOP_WW4B2_4", + "CMT_TOP_IMUX40_0", + "CMT_TOP_IMUX14_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_EE4A0_2", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", + "CMT_TOP_NW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_IMUX8_7", + "CMT_TOP_WW2END0_4", + "CMT_TOP_SW4A1_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_LH10_7", + "CMT_TOP_EE4C2_3", + "CMT_TOP_SE2A3_9", + "CMT_TOP_IMUX1_12", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "PLLOUT_CLK_FREQ_BB_1", + "CMT_TOP_ICLK_11", + "CMT_TOP_EE2A1_11", + "CMT_TOP_WW4C1_12", + "CMT_TOP_SE2A1_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "CMT_TOP_WR1END0_0", + "CMT_TOP_WW2A1_9", + "CMT_TOP_FAN1_11", + "CMT_TOP_IMUX18_4", + "CMT_TOP_WL1END1_5", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_NE2A2_3", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_WW4END1_3", + "CMT_TOP_IMUX24_1", + "CMT_TOP_WW2END2_6", + "CMT_TOP_WW2A2_11", + "CMT_TOP_SW2A0_10", + "CMT_TOP_EE2A3_0", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_WW2A3_7", + "CMT_TOP_WL1END2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_SW2A0_6", + "CMT_TOP_LOGIC_OUTS_L_B5_12", + "CMT_TOP_IMUX13_11", + "CMT_TOP_NW4A3_9", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_NW2A0_1", + "CMT_TOP_IMUX6_0", + "CMT_TOP_LH1_11", + "CMT_TOP_NW2A2_6", + "CMT_TOP_CTRL0_0", + "CMT_TOP_WR1END1_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX43_0", + "CMT_TOP_SE2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4C3_0", + "CMT_TOP_LH11_1", + "CMT_TOP_SW2A1_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", + "CMT_TOP_NW4A3_11", + "CMT_TOP_EE4C3_4", + "CMT_TOP_ER1BEG3_8", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN7_4", + "CMT_TOP_NW4END0_4", + "CMT_TOP_FAN1_6", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_IMUX22_10", + "CMT_TOP_WW4B2_5", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C1_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", + "CMT_TOP_IMUX20_4", + "CMT_TOP_WW2A2_1", + "CMT_TOP_WR1END1_11", + "CMT_TOP_IMUX18_12", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_12", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WR1END3_10", + "CMT_TOP_WW4A1_6", + "CMT_TOP_BYP7_11", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_NW2A1_12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "CMT_TOP_WW4B0_9", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX41_12", + "CMT_TOP_IMUX0_4", + "CMT_TOP_SE2A3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_IMUX20_3", + "CMT_TOP_CTRL1_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EE4A2_5", + "CMT_TOP_SE4C1_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_IMUX27_12", + "CMT_TOP_NW4END0_0", + "CMT_TOP_NW4A3_10", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX12_2", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", + "CMT_TOP_IMUX43_10", + "CMT_TOP_NW4A3_8", + "CMT_TOP_WW4B0_2", + "CMT_TOP_NE2A0_7", + "CMT_TOP_IMUX34_5", + "CMT_TOP_EE4C2_12", + "CMT_TOP_EE4C2_5", + "CMT_TOP_WL1END2_2", + "CMT_TOP_IMUX6_3", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_IMUX35_7", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_IMUX28_10", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_IMUX2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_CTRL0_10", + "CMT_TOP_IMUX46_12", + "CMT_TOP_WW4END2_2", + "CMT_TOP_WL1END0_8", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_IMUX47_6", + "CMT_TOP_BYP1_12", + "CMT_TOP_IMUX23_2", + "CMT_TOP_WL1END0_9", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_IMUX39_6", + "CMT_TOP_EE4A3_12", + "CMT_TOP_IMUX2_12", + "CMT_TOP_EE4C0_10", + "CMT_TOP_IMUX6_4", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_IMUX12_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", + "CMT_TOP_LH8_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4A2_12", + "CMT_TOP_BYP2_5", + "CMT_TOP_NW2A0_10", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX38_8", + "CMT_TOP_IMUX0_6", + "CMT_TOP_NE4BEG3_11", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SE2A0_8", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NE2A0_1", + "CMT_TOP_IMUX31_4", + "CMT_TOP_R_UPPER_T_PLLE2_RST", + "CMT_TOP_NE2A3_9", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX5_1", + "CMT_TOP_IMUX47_2", + "CMT_TOP_LH12_1", + "CMT_TOP_SW2A3_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "CMT_TOP_WW2END3_6", + "CMT_TOP_NW2A0_8", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_IMUX44_3", + "CMT_TOP_LH3_4", + "CMT_TOP_EE2A2_1", + "CMT_TOP_WW4A2_3", + "CMT_TOP_NW2A3_2", + "CMT_TOP_L_UPPER_T_CLKPLL7", + "CMT_TOP_EL1BEG1_12", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX39_8", + "CMT_TOP_SW4END2_7", + "CMT_TOP_FAN2_4", + "CMT_TOP_EE4A1_6", + "CMT_TOP_EE4B1_3", + "CMT_TOP_WW2A2_9", + "CMT_TOP_IMUX42_10", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_WW4END0_1", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE4B1_0", + "CMT_TOP_IMUX34_11", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX10_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", + "CMT_TOP_WL1END3_2", + "CMT_TOP_NW4A2_8", + "CMT_TOP_IMUX35_5", + "CMT_TOP_WW4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_NE4C3_2", + "CMT_TOP_NE2A3_8", + "CMT_TOP_WW4END3_4", + "CMT_TOP_LH1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", + "CMT_TOP_CTRL1_5", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "CMT_TOP_LH7_9", + "CMT_TOP_CLK0_8", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_NE2A0_5", + "CMT_TOP_SW4END2_6", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_EE4C3_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_EE2A2_4", + "CMT_TOP_NE2A3_5", + "CMT_TOP_IMUX13_1", + "CMT_TOP_WW2END0_3", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_EE4C1_3", + "CMT_TOP_EE4A2_0", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_ER1BEG3_12", + "CMT_TOP_NE4C2_9", + "CMT_TOP_EE2BEG3_12", + "CMT_TOP_NW2A2_4", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX37_3", + "CMT_TOP_IMUX37_8", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_LOGIC_OUTS_L_B9_12", + "CMT_TOP_CTRL1_2", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_NE4BEG1_12", + "CMT_TOP_EE4B0_0", + "CMT_TOP_SE2A0_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", + "CMT_TOP_IMUX18_9", + "CMT_TOP_WW2END3_12", + "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4A3_9", + "CMT_TOP_IMUX3_2", + "CMT_TOP_SE2A1_7", + "CMT_TOP_WW4END1_0", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_NW4END2_6", + "CMT_TOP_IMUX34_1", + "CMT_TOP_LH6_9", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW4A2_1", + "CMT_TOP_SW4A2_4", + "CMT_TOP_NE4C2_11", + "CMT_TOP_WW4END1_10", + "CMT_TOP_LH9_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_NE4C3_6", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WW2END3_1", + "CMT_TOP_BYP4_3", + "CMT_TOP_WW2END2_10", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_SE2A0_7", + "CMT_TOP_IMUX35_11", + "CMT_TOP_WW2END2_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "CMT_TOP_BYP7_5", + "CMT_TOP_SW4END0_11", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX45_12", + "CMT_TOP_SW2A1_2", + "CMT_TOP_EE4B1_6", + "CMT_TOP_WW2END0_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_BYP5_0", + "CMT_TOP_IMUX32_9", + "CMT_TOP_EE2A0_12", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX38_10", + "CMT_TOP_LH1_4", + "CMT_TOP_NW4A0_6", + "CMT_TOP_WW4END3_8", + "CMT_TOP_EE4C2_2", + "CMT_TOP_CLK1_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", + "CMT_TOP_WL1END3_11", + "CMT_TOP_NW4A0_12", + "CMT_TOP_WW2END3_4", + "CMT_TOP_WW4C1_8", + "CMT_TOP_IMUX39_10", + "CMT_TOP_WR1END1_8", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_WW4END3_10", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4C3_10", + "CMT_TOP_EE4B3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_EE4B3_7", + "CMT_TOP_NW4END0_7", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SW4A1_10", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX22_7", + "CMT_TOP_NW2A2_5", + "CMT_TOP_LH7_3", + "CMT_TOP_IMUX20_1", + "CMT_TOP_WW4B1_3", + "CMT_TOP_FAN5_8", + "CMT_TOP_SE2A1_9", + "CMT_TOP_OCLK_4", + "CMT_TOP_SE4C2_0", + "CMT_TOP_NE2A0_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_WW2A0_2", + "CMT_TOP_IMUX44_11", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_WW4A1_5", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX17_8", + "CMT_TOP_LH12_5", + "CMT_TOP_IMUX43_2", + "CMT_TOP_LOGIC_OUTS_L_B3_12", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_IMUX46_1", + "CMT_TOP_EE4C2_6", + "CMT_TOP_WW4C3_1", + "CMT_TOP_ICLK_1", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", + "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "CMT_TOP_IMUX42_1", + "CMT_TOP_BYP7_6", + "CMT_TOP_NW4END1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_NW4A3_2", + "CMT_TOP_SW4A0_5", + "CMT_TOP_IMUX4_6", + "CMT_TOP_CLK0_12", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_WW4END0_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_SE4C3_12", + "CMT_TOP_IMUX3_6", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_WW2A3_1", + "CMT_TOP_IMUX35_3", + "CMT_TOP_SW4END0_10", + "CMT_TOP_LH12_2", + "CMT_TOP_IMUX0_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WW4END2_6", + "CMT_TOP_LH11_7", + "CMT_TOP_SW4END3_3", + "CMT_TOP_IMUX28_12", + "CMT_TOP_WW4B1_12", + "CMT_TOP_NW4A1_7", + "CMT_TOP_WW2A3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_IMUX19_6", + "CMT_TOP_FAN4_8", + "CMT_TOP_EE2A2_3", + "CMT_TOP_IMUX34_3", + "CMT_TOP_WW4END1_11", + "CMT_TOP_CLK0_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4C3_7", + "CMT_TOP_WW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_IMUX35_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "CMT_TOP_IMUX10_0", + "CMT_TOP_LH11_3", + "CMT_TOP_SE2A0_9", + "CMT_TOP_WL1END3_7", + "CMT_TOP_IMUX34_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WR1END3_3", + "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", + "CMT_TOP_IMUX46_4", + "CMT_TOP_SE2A2_10", + "CMT_TOP_WW4C2_4", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_IMUX22_0", + "CMT_TOP_IMUX9_11", + "CMT_TOP_WW4A2_9", + "CMT_TOP_SE4C1_0", + "CMT_PHASER_D_OCLK90_TOIOI", + "CMT_TOP_IMUX14_5", + "CMT_TOP_WL1END2_9", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_EE4C1_1", + "CMT_TOP_NW4A0_11", + "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX13_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_SE4C2_3", + "CMT_TOP_WW4END0_12", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX27_5", + "CMT_TOP_OCLK_0", + "CMT_TOP_LH7_8", + "CMT_TOP_IMUX7_8", + "CMT_TOP_ICLK_0", + "CMT_TOP_WW2END2_3", + "CMT_TOP_WR1END0_10", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END1_5", + "CMT_TOP_IMUX44_6", + "CMT_TOP_IMUX22_3", + "CMT_TOP_NE4C2_4", + "CMT_TOP_IMUX8_12", + "CMT_TOP_WL1END1_2", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX30_12", + "CMT_TOP_SE4C3_6", + "CMT_TOP_LH9_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", + "CMT_TOP_EE4C0_12", + "CMT_TOP_NW2A1_10", + "CMT_TOP_SW4A3_8", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW2A2_0", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX13_3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX28_4", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH1_8", + "CMT_TOP_LH10_10", + "CMT_TOP_IMUX42_3", + "CMT_TOP_IMUX3_12", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "CMT_TOP_WL1END1_1", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_EE2A1_12", + "CMT_TOP_IMUX3_10", + "CMT_TOP_OCLK_12", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_WW2END2_8", + "CMT_TOP_EE2A0_8", + "CMT_TOP_LH7_1", + "CMT_TOP_SW2A3_5", + "CMT_TOP_IMUX31_11", + "CMT_PLL_PHYCTRL_SYNC_BB_UP", + "CMT_TOP_IMUX32_12", + "CMT_TOP_IMUX19_3", + "CMT_TOP_NW4END2_12", + "CMT_TOP_FAN0_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", + "CMT_TOP_WW2END1_4", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_NW4END3_7", + "CMT_TOP_EE2A3_12", + "CMT_TOP_CLK1_2", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_IMUX34_9", + "CMT_TOP_EE4B0_6", + "CMT_TOP_EE4B2_5", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW4C2_9", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_WW2A2_2", + "CMT_TOP_SW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_12", + "CMT_TOP_NE2A3_2", + "CMT_TOP_IMUX43_1", + "CMT_TOP_WW4END2_10", + "CMT_TOP_EE4C1_4", + "CMT_TOP_IMUX44_9", + "CMT_TOP_WW4B1_6", + "CMT_TOP_NW4A1_11", + "CMT_TOP_IMUX42_0", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_IMUX24_7", + "CMT_TOP_EE4B0_12", + "CMT_TOP_IMUX47_4", + "CMT_TOP_WL1END1_12", + "CMT_TOP_NE2A1_2", + "CMT_TOP_BYP5_2", + "CMT_TOP_IMUX39_4", + "CMT_TOP_FAN7_8", + "CMT_PHASER_D_OCLKDIV_TOIOI", + "CMT_TOP_IMUX40_8", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_SW2A1_10", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_IMUX33_0", + "CMT_TOP_NE4C1_1", + "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "CMT_TOP_NE4C3_8", + "CMT_TOP_EE4A3_10", + "CMT_TOP_IMUX28_3", + "CMT_TOP_IMUX1_4", + "CMT_TOP_IMUX13_4", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_EE4B2_12", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_SW4END0_12", + "CMT_TOP_EE4B1_8", + "PLLOUT_CLK_FREQ_BB_2", + "CMT_TOP_NE4BEG0_12", + "CMT_TOP_SW4A1_9", + "CMT_TOP_SE4C2_8", + "CMT_TOP_LH1_5", + "CMT_TOP_WW4END3_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_WW2END3_3", + "CMT_TOP_WL1END3_12", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_NE4C0_2", + "CMT_TOP_IMUX44_12", + "CMT_TOP_FAN6_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_IMUX19_10", + "CMT_TOP_ER1BEG0_5", + "CMT_PLL_PHASERREF_ABOVE1", + "CMT_TOP_LH7_5", + "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "CMT_TOP_LOGIC_OUTS_L_B1_12", + "CMT_TOP_IMUX19_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_FAN0_2", + "CMT_TOP_FAN6_0", + "CMT_TOP_IMUX27_3", + "CMT_TOP_IMUX47_5", + "CMT_TOP_IMUX24_0", + "CMT_TOP_IMUX26_0", + "CMT_TOP_WR1END2_3", + "CMT_TOP_EE4A0_12", + "CMT_TOP_WR1END1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_NE4C0_6", + "CMT_TOP_EE4C0_0", + "CMT_TOP_EE2A3_10", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE2A0_2", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_IMUX47_9", + "CMT_TOP_SE4C1_7", + "CMT_TOP_FAN0_10", + "CMT_TOP_IMUX45_7", + "CMT_TOP_EE2A3_4", + "PLL_CLK_FREQ_BB0_NS", + "CMT_TOP_ER1BEG2_10", + "CMT_TOP_IMUX13_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", + "CMT_TOP_WW2END1_10", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_IMUX29_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_IMUX33_9", + "CMT_TOP_SW4END3_1", + "CMT_TOP_IMUX5_5", + "CMT_TOP_NE4BEG3_12", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_NW4A1_9", + "CMT_TOP_WW2END0_11", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4C0_8", + "CMT_TOP_IMUX16_10", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_IMUX15_4", + "CMT_TOP_LH10_11", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_NW2A2_9", + "CMT_TOP_EE4B3_11", + "CMT_TOP_EE2A1_0", + "CMT_TOP_WW4A1_1", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_LH9_9", + "CMT_TOP_EE4B0_1", + "CMT_TOP_WL1END2_12", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_WW2END0_12", + "CMT_TOP_SE2A0_10", + "CMT_TOP_BLOCK_OUTS_L_B3_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", + "CMT_TOP_NE4C2_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE2BEG0_12", + "CMT_TOP_CLK0_3", + "CMT_TOP_IMUX14_1", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "CMT_TOP_LH8_9", + "CMT_TOP_WW2A3_11", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_SE4C1_12", + "CMT_TOP_IMUX2_7", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW4C3_6", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_EE4C0_4", + "CMT_TOP_IMUX28_8", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LH2_6", + "CMT_TOP_IMUX11_9", + "CMT_TOP_WW4A1_11", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_BYP4_8", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW2A0_4", + "CMT_TOP_NW4END3_9", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LH12_7", + "CMT_TOP_WW2END1_7", + "CMT_TOP_LH6_2", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX45_8", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_EE2A0_3", + "CMT_TOP_WW4B0_10", + "CMT_TOP_IMUX33_4", + "CMT_TOP_BYP1_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_WL1END0_11", + "CMT_TOP_SW2A0_5", + "CMT_TOP_EE4C3_8", + "CMT_TOP_IMUX35_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_WW2A3_10", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_NW4END1_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "CMT_TOP_IMUX36_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_SW4END3_2", + "CMT_TOP_WL1END0_5", + "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_SW2A1_5", + "CMT_TOP_IMUX33_6", + "CMT_TOP_EE4C2_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", + "CMT_TOP_EE4B3_3", + "CMT_TOP_WW4A1_0", + "CMT_TOP_LH5_12", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_WW2END2_1", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_WW4END0_11", + "CMT_TOP_IMUX25_4", + "CMT_TOP_IMUX2_9", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_SW4END1_0", + "CMT_TOP_EE2A1_1", + "CMT_TOP_SE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_EE4A3_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_SE4C2_11", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_BYP2_11", + "CMT_TOP_LH11_6", + "CMT_TOP_BYP1_1", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_NW2A0_11", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WR1END0_3", + "CMT_TOP_WW4B3_5", + "CMT_TOP_L_CLKFBOUT2IN", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_IMUX31_9", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_BYP6_0", + "CMT_TOP_SW4END2_12", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WR1END1_6", + "CMT_TOP_SE4C0_2", + "CMT_TOP_LH11_10", + "CMT_TOP_EE4A2_8", + "CMT_TOP_SE2A1_1", + "CMT_TOP_NW4END1_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_IMUX31_3", + "CMT_TOP_EE4C1_8", + "CMT_TOP_IMUX20_11", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_WW4END1_4", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_NW2A2_12", + "CMT_TOP_IMUX9_10", + "CMT_TOP_SW4A1_5", + "CMT_TOP_SE4C0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_SW2A1_0", + "CMT_TOP_SE4BEG1_7", + "CMT_TOP_EE2A0_0", + "CMT_TOP_CTRL1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_WW4A1_2", + "CMT_TOP_WW4C3_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_IMUX5_9", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_IMUX38_2", + "CMT_TOP_IMUX1_11", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_IMUX35_10", + "CMT_TOP_EE4A3_0", + "CMT_TOP_WW2A3_6", + "CMT_TOP_NW2A3_1", + "CMT_TOP_BYP3_5", + "CMT_TOP_BYP6_11", + "CMT_TOP_SW2A3_4", + "CMT_TOP_L_UPPER_T_CLKPLL0", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "CMT_TOP_IMUX42_8", + "CMT_TOP_IMUX30_2", + "CMT_TOP_IMUX45_1", + "CMT_TOP_WW4B3_0", + "CMT_TOP_LOGIC_OUTS_L_B2_12", + "CMT_TOP_LH3_6", + "CMT_TOP_LH12_12", + "CMT_TOP_IMUX12_0", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", + "CMT_TOP_IMUX11_0", + "CMT_TOP_IMUX24_3", + "CMT_TOP_EE2BEG2_12", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX24_2", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_SE4BEG2_12", + "CMT_TOP_LH3_0", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_WW2A1_1", + "CMT_TOP_LH2_0", + "CMT_TOP_IMUX22_2", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX2_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", + "CMT_TOP_IMUX22_9", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_OCLKDIV_12", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_ICLK_10", + "CMT_TOP_SE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_LH2_11", + "CMT_TOP_SW4END1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", + "CMT_TOP_WL1END1_4", + "CMT_TOP_IMUX37_9", + "CMT_TOP_EE2A2_10", + "CMT_TOP_WW4C3_9", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP6_12", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH7_11", + "CMT_TOP_IMUX42_12", + "CMT_TOP_EE4A0_7", + "CMT_TOP_EE4A0_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_EE4B1_5", + "CMT_TOP_CLK1_12", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_IMUX19_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_WW4B2_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", + "CMT_TOP_IMUX17_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", + "CMT_TOP_EE4A1_12", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_WW4A1_12", + "CMT_TOP_IMUX36_0", + "CMT_TOP_WW2A2_7", + "CMT_TOP_IMUX33_8", + "CMT_TOP_SW4END2_8", + "CMT_TOP_NE4C3_7", + "CMT_TOP_CLK1_9", + "CMT_TOP_WW4C2_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", + "CMT_PLL_PHASERREF_BELOW0", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_NW2A2_2", + "CMT_TOP_LH11_12", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW4END0_5", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_BYP3_2", + "CMT_TOP_NW4END2_1", + "CMT_TOP_IMUX15_0", + "CMT_TOP_IMUX45_3", + "CMT_TOP_NW4A1_10", + "CMT_TOP_IMUX33_10", + "CMT_TOP_SE4C0_6", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_LH1_9", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH10_4", + "CMT_TOP_SE4C2_7", + "CMT_TOP_WW4A0_12", + "CMT_TOP_IMUX32_3", + "CMT_TOP_IMUX16_9", + "CMT_TOP_IMUX3_11", + "CMT_TOP_BYP5_1", + "CMT_TOP_NE4C2_12", + "CMT_TOP_WW2A1_7", + "CMT_TOP_IMUX9_12", + "CMT_TOP_IMUX17_5", + "CMT_TOP_BYP2_2", + "CMT_PLL_PHASER_OUT_D_OCLK", + "CMT_TOP_L_UPPER_T_CLKPLL4", + "CMT_TOP_LH1_6", + "CMT_TOP_SW4A1_11", + "CMT_TOP_IMUX40_12", + "CMT_TOP_IMUX12_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX13_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_NW2A1_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "CMT_TOP_SE2A3_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_EE4C0_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_NE4C2_0", + "CMT_TOP_IMUX1_7", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX21_5", + "CMT_TOP_ER1BEG0_12", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH12_3", + "PLL_CLK_FREQ_BB3_NS", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LH12_8", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_NW4END1_12", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_CTRL0_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", + "CMT_TOP_NW4A3_7", + "CMT_TOP_NW4END3_0", + "CMT_TOP_NE2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_WW4A2_12", + "CMT_TOP_IMUX20_8", + "CMT_TOP_WW2END0_8", + "CMT_TOP_LH9_3", + "CMT_TOP_IMUX29_9", + "CMT_TOP_LH6_4", + "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_WW2A2_10", + "CMT_TOP_FAN2_12", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "CMT_TOP_NE4C3_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", + "CMT_TOP_BYP6_5", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_WL1END0_6", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_IMUX15_6", + "PLL_CLK_FREQ_BB_BUFOUT_NS2", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "CMT_TOP_ICLK_2", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_IMUX36_2", + "CMT_TOP_FAN1_3", + "CMT_TOP_LH9_0", + "CMT_TOP_WL1END0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_WR1END3_6", + "CMT_PHASER_D_ICLK_TOIOI", + "CMT_TOP_NE2A3_3", + "CMT_TOP_SW4A2_10", + "CMT_TOP_WR1END2_10", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX26_6", + "CMT_TOP_SE4C0_12", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_IMUX29_0", + "CMT_TOP_WR1END2_0", + "CMT_TOP_SW2A3_6", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX43_9", + "CMT_TOP_IMUX8_10", + "CMT_TOP_BYP3_3", + "CMT_TOP_WW2A2_3", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX44_0", + "CMT_TOP_WW4C1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", + "CMT_TOP_IMUX15_12", + "CMT_TOP_EE4A1_7", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW2A1_3", + "CMT_TOP_IMUX39_5", + "CMT_TOP_LH1_0", + "CMT_TOP_IMUX28_5", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", + "CMT_TOP_NE2A1_7", + "CMT_TOP_IMUX41_10", + "CMT_TOP_WR1END3_5", + "CMT_TOP_IMUX37_10", + "CMT_TOP_IMUX23_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX15_5", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_SW4A0_7", + "CMT_TOP_LH12_4", + "CMT_TOP_WW4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_PLL_PHASERREF_BELOW1", + "CMT_TOP_WW4A1_7", + "CMT_TOP_BYP0_12", + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_LH7_7", + "CMT_TOP_WW4C0_7", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_IMUX39_11", + "CMT_TOP_BYP5_4", + "CMT_TOP_FAN4_3", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_FAN6_2", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH4_5", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SW2A0_12", + "CMT_TOP_WR1END2_4", + "CMT_TOP_LH9_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_EE4C3_0", + "CMT_TOP_BYP4_9", + "CMT_TOP_NW4END2_11", + "CMT_TOP_NE4C1_6", + "CMT_TOP_BYP2_0", + "CMT_TOP_WW2A0_10", + "CMT_TOP_IMUX7_11", + "CMT_TOP_WW4END0_0", + "CMT_TOP_NE4C0_12", + "CMT_TOP_EE2A2_7", + "CMT_TOP_LH2_1", + "CMT_TOP_MONITOR_N_12", + "CMT_TOP_NW4END3_12", + "CMT_TOP_WW4END3_7", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_WW4B2_12", + "CMT_TOP_EE2BEG0_9", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX4_12", + "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "CMT_TOP_LH11_5", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_WW4C1_5", + "CMT_TOP_BYP5_8", + "CMT_TOP_WR1END2_11", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_8", + "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_WL1END1_7", + "CMT_TOP_WL1END1_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "CMT_TOP_NW4A3_6", + "CMT_TOP_LH6_7", + "CMT_TOP_WW4B1_8", + "CMT_TOP_WW4A3_0", + "CMT_TOP_FAN3_7", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", + "CMT_TOP_SW2A2_10", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_L_UPPER_T_CLKPLL3", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_IMUX25_5", + "CMT_TOP_CLK0_4", + "CMT_TOP_NW2A0_9", + "CMT_TOP_FAN5_3", + "CMT_TOP_EE4A1_4", + "CMT_TOP_IMUX31_6", + "CMT_TOP_NE2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_IMUX38_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_NE2A1_12", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_ICLK_7", + "CMT_TOP_IMUX15_3", + "CMT_TOP_FAN1_9", + "CMT_TOP_FAN2_3", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_SW4A0_4", + "CMT_TOP_LH11_9", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_IMUX8_3", + "CMT_TOP_WW4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_EE4C2_11", + "CMT_TOP_NE4C3_1", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CTRL0_3", + "CMT_TOP_FAN0_8", + "CMT_TOP_L_UPPER_T_CLKPLL5", + "CMT_TOP_EE4C2_7", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_SW4A1_1", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_NW4END2_10", + "CMT_TOP_IMUX16_12", + "CMT_TOP_IMUX35_12", + "CMT_TOP_IMUX9_6", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX31_8", + "CMT_PHASER_D_ICLKDIV_TOIOI", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX28_7", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_SW2A3_7", + "CMT_TOP_LH4_9", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_NW2A3_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "CMT_TOP_EE4B3_4", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", + "CMT_TOP_IMUX24_4", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_FAN6_6", + "CMT_TOP_IMUX25_2", + "CMT_TOP_BYP2_3", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_FAN4_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_NW4A1_3", + "CMT_TOP_IMUX35_4", + "CMT_TOP_WW2END3_10", + "CMT_TOP_IMUX41_5", + "CMT_TOP_NW4A1_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", + "CMT_TOP_IMUX10_6", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_LH12_6", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_BYP6_10", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_BYP7_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_IMUX5_12", + "CMT_TOP_SW4A2_1", + "CMT_TOP_LH1_3", + "CMT_TOP_FAN0_5", + "CMT_TOP_EE2A1_8", + "CMT_TOP_WW4C3_7", + "CMT_TOP_LH2_3", + "CMT_TOP_FAN7_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_NE2A0_12", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_NW4A3_0", + "CMT_TOP_EE4B1_10", + "CMT_TOP_LH9_12", + "CMT_TOP_WW4END2_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX38_4", + "CMT_TOP_NE2A1_4", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_IMUX27_2", + "CMT_TOP_WW4C0_6", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "CMT_TOP_IMUX1_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_NE2A2_5", + "CMT_TOP_NW4A0_3", + "CMT_TOP_LOGIC_OUTS_L_B4_12", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_EE4BEG3_12", + "CMT_TOP_NW2A3_6", + "CMT_TOP_WW4END3_5", + "CMT_TOP_IMUX34_12", + "CMT_TOP_WW4B1_5", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX23_10", + "CMT_TOP_IMUX17_0", + "CMT_TOP_CLK0_2", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "CMT_TOP_EE4B3_2", + "CMT_TOP_IMUX31_5", + "CMT_TOP_FAN0_0", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "CMT_TOP_EE4C3_2", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX46_3", + "CMT_TOP_IMUX43_7", + "CMT_TOP_IMUX40_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_EE4A3_9", + "CMT_TOP_WW4END3_6", + "CMT_TOP_FAN2_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", + "CMT_TOP_CLK0_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", + "CMT_TOP_IMUX10_5", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_WW2A3_8", + "CMT_TOP_NE4C1_8", + "CMT_TOP_EE4A1_1", + "CMT_TOP_WW4A3_12", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4C0_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", + "CMT_TOP_BYP0_6", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX12_4", + "CMT_TOP_LH10_3", + "CMT_TOP_LH3_2", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_IMUX43_4", + "CMT_TOP_LH10_6", + "CMT_TOP_NE4C1_10", + "CMT_TOP_IMUX15_11", + "CMT_TOP_NE4C1_9", + "CMT_TOP_WW4B0_3", + "CMT_TOP_WW4C3_10", + "CMT_TOP_SE2A2_6", + "CMT_TOP_NW2A3_5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_WW4A2_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_SW2A1_12", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_IMUX38_11", + "CMT_TOP_SW4END2_9", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_LH3_1", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END2_5", + "CMT_TOP_FAN0_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_IMUX42_11", + "CMT_TOP_SE2A0_3", + "CMT_PLL_PHASER_RDENABLE_TOFIFO", + "CMT_TOP_IMUX4_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", + "CMT_TOP_BYP4_0", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LH4_4", + "CMT_TOP_LH3_9", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_EL1BEG2_9", + "CMT_TOP_WW4C1_2", + "CMT_TOP_IMUX37_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_WR1END1_0", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_IMUX22_5", + "PLL_CLK_FREQ_BB1_NS", + "CMT_TOP_OCLK_3", + "CMT_TOP_IMUX23_5", + "CMT_TOP_SW4END2_4", + "CMT_TOP_IMUX37_12", + "CMT_TOP_EE4A1_8", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW2END0_2", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_SE2A1_6", + "CMT_TOP_CTRL0_1", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END0_9", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_WW4B0_0", + "CMT_TOP_LH7_12", + "CMT_TOP_IMUX6_5", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_WW4B0_4", + "CMT_TOP_IMUX10_9", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_IMUX45_0", + "CMT_TOP_IMUX45_10", + "CMT_TOP_IMUX39_1", + "CMT_TOP_WL1END1_8", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WW2END3_8", + "CMT_TOP_IMUX9_5", + "CMT_TOP_BYP4_10", + "CMT_TOP_WW4C2_12", + "CMT_TOP_IMUX17_9", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_IMUX23_4", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_FAN3_10", + "CMT_TOP_EE4B0_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX42_9", + "CMT_TOP_IMUX38_12", + "CMT_TOP_EE2A2_6", + "CMT_TOP_IMUX25_3", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_PLL_DQS_TO_PHASER_D", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WR1END1_12", + "CMT_TOP_IMUX34_4", + "CMT_TOP_LH7_2", + "CMT_TOP_LH6_1", + "CMT_TOP_NW4END2_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", + "CMT_TOP_LH1_2", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_IMUX13_2", + "CMT_TOP_WW4A0_8", + "CMT_TOP_FAN6_8", + "CMT_TOP_IMUX17_7", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_NW4A0_2", + "CMT_TOP_BYP6_6", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NW4END0_6", + "CMT_TOP_WR1END3_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_NE2A3_7", + "CMT_TOP_IMUX3_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_TOP_BYP2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", + "CMT_TOP_IMUX14_8", + "CMT_TOP_BYP0_3", + "CMT_TOP_NE4C0_0", + "CMT_TOP_NE4C2_10", + "CMT_TOP_SE2A2_12", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH6_11", + "CMT_TOP_FAN5_10", + "CMT_TOP_WW4END2_4", + "CMT_TOP_EE4C3_12", + "CMT_TOP_NW2A3_11", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_NW2A2_8", + "CMT_TOP_IMUX19_4", + "CMT_TOP_WW2END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_IMUX30_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX28_1", + "CMT_TOP_NW4A0_0", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_LH3_7", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX16_4", + "CMT_TOP_EE2A3_7", + "CMT_TOP_SE4C3_11", + "CMT_TOP_ICLK_9", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_WW4A1_10", + "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "CMT_TOP_WW2END0_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", + "CMT_TOP_NW4A2_12", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_WW4C3_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", + "CMT_TOP_BYP3_6", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_WW2A2_8", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_WW4B3_7", + "PLL_CLK_FREQ_BB_BUFOUT_NS0", + "CMT_TOP_SW4END3_4", + "CMT_TOP_EE4C1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_IMUX20_12", + "CMT_TOP_BYP0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_WW4END1_7", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WW4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_SE4BEG0_12", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX5_0", + "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "CMT_TOP_WW4B3_10", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_WW2END3_9", + "CMT_TOP_SW4END1_10", + "CMT_TOP_WW4B0_7", + "CMT_TOP_BYP3_7", + "CMT_TOP_EE2A3_11", + "CMT_TOP_LH6_5", + "CMT_TOP_IMUX28_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", + "CMT_TOP_WW4A3_5", + "CMT_TOP_EL1BEG0_12", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_WL1END0_3", + "CMT_TOP_WW4C0_2", + "CMT_TOP_IMUX0_7", + "CMT_TOP_WW4B1_0", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SW4END0_8", + "CMT_TOP_WW4C2_10", + "CMT_TOP_IMUX8_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", + "CMT_TOP_IMUX34_6", + "CMT_TOP_IMUX32_11", + "CMT_TOP_NE2A3_1", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_EE4C1_12", + "CMT_TOP_EE4B0_3", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A3_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_PLL_PHASERD_CTSBUS1", + "CMT_TOP_IMUX46_10", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_SW2A3_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", + "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "CMT_TOP_WW4C0_5", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_BYP4_4", + "CMT_TOP_NW4A2_9", + "CMT_TOP_WR1END2_1", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_IMUX16_1", + "CMT_TOP_NW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_FAN2_6", + "CMT_TOP_WR1END3_7", + "CMT_TOP_IMUX23_12", + "CMT_TOP_IMUX38_9", + "CMT_TOP_IMUX36_12", + "CMT_TOP_IMUX28_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_FAN5_7", + "CMT_TOP_BYP7_10", + "CMT_TOP_IMUX15_7", + "CMT_TOP_IMUX13_12", + "CMT_TOP_IMUX30_9", + "CMT_TOP_LH8_5", + "CMT_TOP_EE4A3_5", + "CMT_TOP_L_UPPER_T_CLKFBIN", + "CMT_TOP_NE4C0_5", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_IMUX25_0", + "CMT_TOP_IMUX31_10", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_SW4A0_12", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_IMUX34_2", + "CMT_TOP_LH10_2", + "CMT_TOP_SW4A2_12", + "CMT_TOP_LH12_0", + "CMT_TOP_FAN4_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_NW4A0_8", + "CMT_TOP_WW4A2_10", + "CMT_TOP_BYP3_0", + "CMT_TOP_IMUX2_1", + "CMT_TOP_IMUX22_1", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_BLOCK_OUTS_L_B1_12", + "CMT_TOP_EE2A3_5", + "CMT_TOP_IMUX4_7", + "CMT_TOP_SE2A2_0", + "CMT_TOP_LH2_4", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SW4A3_6", + "CMT_TOP_NW4END1_5", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WR1END3_1", + "CMT_TOP_BYP1_0", + "CMT_TOP_EE2BEG1_12", + "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "CMT_TOP_WW2A0_6", + "CMT_TOP_SE2A3_0", + "CMT_TOP_IMUX35_9", + "CMT_TOP_SW4END2_5", + "CMT_TOP_SE4C3_5", + "CMT_TOP_LH4_1", + "CMT_TOP_NW4A0_9", + "CMT_TOP_SW4A1_6", + "CMT_TOP_SW2A2_0", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE4C3_10", + "CMT_TOP_LOGIC_OUTS_L_B11_12", + "CMT_TOP_SW4END0_7", + "CMT_TOP_EE4BEG1_12", + "CMT_TOP_IMUX13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_NE4C0_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EE4A2_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_LH2_8", + "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", + "CMT_TOP_SE2A3_1", + "CMT_TOP_IMUX2_6", + "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "CMT_TOP_IMUX3_0", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4C2_4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "CMT_TOP_NE4BEG1_5", + "CMT_PLL_PHASERD_DQSBUS0", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_EE2A3_2", + "CMT_TOP_IMUX14_10", + "CMT_TOP_IMUX23_8", + "CMT_TOP_WW4A3_8", + "CMT_TOP_IMUX40_6", + "CMT_TOP_IMUX24_12", + "CMT_TOP_LH10_9", + "CMT_TOP_BYP3_12", + "CMT_TOP_FAN1_0", + "CMT_TOP_LH4_10", + "CMT_TOP_IMUX0_2", + "CMT_TOP_EL1BEG3_12", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_LH1_12", + "CMT_TOP_LH5_3", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "CMT_TOP_NW2A3_3", + "CMT_TOP_NW2A0_3", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX18_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", + "CMT_PLL_PHASERREF1", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_SW4END3_10", + "CMT_TOP_FAN2_10", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_WR1END1_1", + "CMT_TOP_SW2A2_7", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "CMT_TOP_ICLK_5", + "CMT_TOP_SW2A0_7", + "CMT_TOP_FAN6_5", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WW2A1_2", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_FAN4_1", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_SE4C0_11", + "CMT_TOP_WW2END0_6", + "CMT_TOP_CTRL1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_WW4B1_2", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_FAN6_3", + "CMT_TOP_WL1END1_11", + "CMT_TOP_SW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_LH11_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_SE4C2_6", + "CMT_TOP_IMUX39_12", + "CMT_TOP_FAN5_11", + "CMT_TOP_SW4END1_6", + "CMT_TOP_IMUX2_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH6_0", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX29_3", + "CMT_TOP_WL1END1_6", + "CMT_TOP_NW4A2_5", + "CMT_TOP_IMUX6_9", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX9_2", + "CMT_TOP_IMUX19_5", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_EE4A1_9", + "CMT_TOP_EE4B3_9", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_NE2A3_4", + "CMT_TOP_EE2A0_11", + "CMT_TOP_IMUX40_3", + "CMT_TOP_SW2A3_12", + "CMT_TOP_L_UPPER_T_FREQ_BB1", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_ICLK_3", + "CMT_TOP_SW4END0_6", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_IMUX41_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", + "CMT_TOP_EE4A0_11", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_IMUX46_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_EE4C0_2", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX11_3", + "CMT_TOP_IMUX17_12", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_LH5_8", + "CMT_PLL_PHYCTRL_SYNC_BB_DN", + "CMT_TOP_WW4A2_8", + "CMT_TOP_WW4A3_4", + "CMT_TOP_LH11_4", + "CMT_TOP_IMUX34_0", + "CMT_TOP_BYP1_6", + "CMT_TOP_WW4B0_1", + "CMT_TOP_WL1END0_12", + "CMT_TOP_IMUX2_4", + "CMT_TOP_SW4A1_8", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_WL1END3_10", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX29_7", + "CMT_TOP_IMUX33_3", + "CMT_TOP_SW4END3_12", + "CMT_TOP_SW2A2_3", + "CMT_TOP_FAN6_12", + "CMT_TOP_IMUX44_8", + "CMT_TOP_IMUX32_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SW2A3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX32_1", + "CMT_TOP_LH8_1", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW2A3_12", + "CMT_TOP_IMUX31_12", + "CMT_TOP_WW4C3_3", + "CMT_TOP_SE4C3_1", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX26_3", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_IMUX24_6", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_NE2A2_10", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_LOGIC_OUTS_L_B7_12", + "CMT_TOP_IMUX17_1", + "CMT_TOP_EE4C3_7", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_ICLK_6", + "CMT_TOP_SE2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_SE2A3_7", + "CMT_TOP_BYP6_9", + "CMT_TOP_EE4B2_3", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "CMT_TOP_WW2A0_8", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX0_3", + "CMT_TOP_IMUX30_10", + "CMT_TOP_WW4END0_9", + "CMT_TOP_SW4END0_5", + "CMT_TOP_IMUX27_10", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_SW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_PLL_PHASER_IN_D_ICLK", + "CMT_TOP_CTRL1_1", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_IMUX29_12", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_IMUX12_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", + "CMT_TOP_WW4A3_10", + "CMT_TOP_FAN3_6", + "CMT_TOP_LH5_4", + "CMT_TOP_LOGIC_OUTS_L_B21_12", + "CMT_TOP_NE4C1_12", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_WW2END1_12", + "CMT_TOP_IMUX47_3", + "CMT_TOP_SW4A3_5", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_EE2A1_4", + "CMT_TOP_NW4END1_4", + "CMT_TOP_IMUX25_1", + "CMT_TOP_LH5_11", + "CMT_TOP_FAN1_10", + "CMT_TOP_LH3_12", + "CMT_TOP_NW4END0_11", + "CMT_TOP_EE4C0_11", + "CMT_TOP_BLOCK_OUTS_L_B0_12", + "CMT_TOP_IMUX25_8", + "CMT_TOP_EE4A1_3", + "CMT_TOP_NW2A3_7", + "CMT_TOP_IMUX30_11", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_EE2A1_2", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WW4C0_12", + "CMT_TOP_WW4C2_8", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX26_11", + "CMT_TOP_NE2A2_1", + "CMT_TOP_CTRL1_8", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NW4END3_3", + "CMT_TOP_WW4B2_2", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX16_11", + "CMT_TOP_WW4A0_3", + "CMT_TOP_LH5_1", + "CMT_TOP_WL1END0_4", + "CMT_TOP_NW4A3_12", + "CMT_TOP_IMUX44_7", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SE2A2_3", + "CMT_TOP_FAN6_10", + "CMT_TOP_SE4C2_4", + "CMT_TOP_EE4C2_0", + "CMT_TOP_NE4C1_3", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX18_8", + "CMT_TOP_BYP3_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_CLK1_5", + "CMT_TOP_SW2A0_4", + "CMT_TOP_IMUX0_10", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_IMUX13_7", + "CMT_TOP_NE4C2_2", + "PLL_CLK_FREQ_BB2_NS", + "CMT_TOP_IMUX10_4", + "CMT_TOP_EE4A1_11", + "CMT_TOP_EE2A0_6", + "CMT_TOP_NW4END1_0", + "CMT_TOP_LH5_10", + "CMT_TOP_IMUX46_7", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE2A2_8", + "CMT_TOP_OCLK_9", + "CMT_TOP_NW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_WW4END3_9", + "CMT_TOP_EE4C3_1", + "CMT_TOP_IMUX14_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", + "CMT_TOP_WW4C1_9", + "CMT_TOP_IMUX0_9", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_WL1END3_9", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_IMUX13_6", + "CMT_TOP_EE4A2_6", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WW4B2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_WW2A0_1", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_FAN7_12", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LH5_7", + "CMT_TOP_IMUX21_9", + "CMT_TOP_IMUX35_1", + "CMT_TOP_IMUX47_12", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_NW2A3_8", + "CMT_TOP_SE2A3_4", + "CMT_TOP_SW4END3_9", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NE4C0_10", + "CMT_TOP_IMUX26_5", + "CMT_TOP_BYP4_11", + "CMT_TOP_IMUX25_6", + "CMT_TOP_BYP0_2", + "CMT_TOP_BYP6_7", + "CMT_TOP_ICLK_12", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_NE2A1_8", + "CMT_TOP_WW4A0_10", + "CMT_TOP_BYP4_12", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_5", + "CMT_TOP_WW4B2_0", + "CMT_TOP_SE4BEG3_12", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_WW2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_WL1END3_0", + "CMT_TOP_WW4END0_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_NW4END0_1", + "CMT_TOP_LH6_6", + "CMT_TOP_NE4C3_5", + "CMT_TOP_FAN3_12", + "CMT_TOP_NW4END0_8", + "CMT_TOP_IMUX39_0", + "CMT_TOP_WW4END2_0", + "CMT_TOP_WW4B3_4", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_IMUX9_0", + "CMT_TOP_FAN2_0", + "CMT_TOP_IMUX29_11", + "CMT_TOP_IMUX30_5", + "CMT_TOP_IMUX8_9", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_NW4END2_5", + "CMT_TOP_NE4C0_7", + "CMT_TOP_L_UPPER_T_CLKIN1", + "CMT_TOP_WW2END2_4", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_WL1END3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NW2A0_2", + "CMT_TOP_IMUX17_6", + "CMT_TOP_IMUX7_0", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_SE2A1_2", + "CMT_TOP_IMUX20_2", + "CMT_TOP_LH8_7", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_WW4A2_5", + "CMT_TOP_NE4C1_11", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_OCLK_6", + "CMT_TOP_CTRL1_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", + "CMT_TOP_IMUX18_10", + "CMT_TOP_BYP4_7", + "CMT_TOP_BYP0_5", + "CMT_TOP_SE2A2_4", + "CMT_TOP_SE4C2_1", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B0_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_NW4END3_4", + "CMT_TOP_IMUX40_11", + "CMT_TOP_LH9_8", + "CMT_TOP_LOGIC_OUTS_L_B16_12", + "CMT_TOP_LH9_11", + "CMT_TOP_NE2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX28_11", + "CMT_TOP_LOGIC_OUTS_L_B6_12", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_LH3_10", + "CMT_TOP_IMUX42_7", + "CMT_TOP_IMUX5_10", + "CMT_TOP_WL1END3_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_EE2A3_1", + "CMT_TOP_IMUX2_10", + "CMT_TOP_SE2A0_6", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_SE4C1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_MONITOR_P_2", + "CMT_TOP_IMUX41_4", + "CMT_TOP_WL1END0_1", + "CMT_TOP_IMUX0_12", + "CMT_TOP_NW4END2_4", + "CMT_TOP_FAN5_1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_IMUX20_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", + "CMT_TOP_NE2A2_11", + "CMT_TOP_FAN5_2", + "CMT_TOP_SW2A3_9", + "CMT_TOP_NW2A1_1", + "CMT_TOP_FAN1_1", + "CMT_TOP_IMUX5_7", + "CMT_PLL_PHASERD_DQSBUS1", + "CMT_TOP_IMUX11_11", + "CMT_TOP_NE2A1_5", + "CMT_TOP_CLK1_0", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_SW4END1_11", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_IMUX28_9", + "CMT_TOP_NW4A1_4", + "CMT_TOP_NE4C2_5", + "CMT_TOP_WW4B2_8", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_L_UPPER_T_CLKPLL1", + "CMT_PLL_PHASERD_DTSBUS0", + "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_WW4B2_6", + "CMT_TOP_WW2END1_11", + "CMT_TOP_IMUX19_0", + "CMT_TOP_LH3_3", + "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "CMT_TOP_IMUX31_2", + "CMT_TOP_IMUX38_5", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_LH4_2", + "CMT_TOP_SE2A0_11", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH12_9", + "CMT_TOP_SW2A0_0", + "CMT_TOP_SW2A0_11", + "CMT_TOP_WW4A3_7", + "CMT_TOP_WW4END2_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", + "CMT_TOP_BYP5_10", + "CMT_TOP_LH12_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW2A0_4", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_IMUX30_1", + "CMT_TOP_IMUX0_1", + "CMT_TOP_IMUX39_3", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_FAN6_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_IMUX43_12", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_10", + "CMT_TOP_NE2A2_9", + "CMT_TOP_EE4B1_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_NW4END0_10", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX44_1", + "CMT_TOP_IMUX37_7", + "CMT_TOP_CTRL0_12", + "CMT_TOP_IMUX29_1", + "CMT_TOP_FAN6_11", + "CMT_TOP_NW4A0_1" + ], + "tile_type": "CMT_TOP_L_UPPER_T", + "sites": [ + { + "site_pins": { + "CLKOUT2": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "TESTOUT25": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", + "DADDR5": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "TESTOUT32": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", + "TESTOUT29": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", + "TESTOUT43": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", + "TESTIN29": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", + "TESTOUT18": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", + "DI10": "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "TESTIN14": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", + "TESTIN21": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", + "TESTOUT15": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", + "TESTIN18": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", + "TESTOUT61": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", + "DO12": "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "DO10": "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "TESTOUT40": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", + "TESTOUT23": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", + "TESTOUT59": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", + "TESTOUT50": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", + "TESTOUT49": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", + "DI3": "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "TESTOUT46": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", + "CLKIN1": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "TESTOUT6": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", + "TESTOUT12": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", + "TESTIN22": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", + "DI15": "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "DCLK": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "CLKFBIN": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "DI9": "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "CLKINSEL": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "TESTIN30": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", + "TESTOUT0": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", + "TESTOUT60": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", + "TESTOUT9": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", + "DO0": "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "TESTOUT35": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", + "TESTOUT47": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", + "DO3": "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "DI4": "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "DI0": "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "DI7": "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "TESTOUT57": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", + "TESTIN4": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", + "TESTOUT24": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", + "DADDR3": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "DO4": "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "TESTOUT48": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", + "TESTIN1": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", + "TESTOUT27": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", + "TESTOUT13": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", + "TESTOUT7": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", + "CLKOUT4": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "TESTOUT3": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", + "TESTIN28": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", + "TESTOUT54": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", + "RST": "CMT_TOP_R_UPPER_T_PLLE2_RST", + "TESTOUT8": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", + "CLKOUT5": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "TESTIN20": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", + "TESTIN9": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", + "TESTOUT39": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", + "TESTOUT51": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", + "TESTOUT20": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", + "PWRDWN": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "TESTIN27": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", + "TESTOUT52": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", + "DI13": "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "TESTIN24": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", + "TESTOUT11": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", + "DO1": "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "DADDR4": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "DI14": "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "TESTIN6": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", + "DI2": "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "DADDR0": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "DO8": "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "DI12": "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "DO14": "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "TESTOUT34": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", + "DI6": "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "TESTOUT14": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", + "DI5": "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "TESTIN25": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", + "DO9": "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "DI11": "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "CLKOUT3": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "TESTIN23": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", + "TESTOUT2": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", + "DADDR1": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "TESTOUT30": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", + "TESTIN12": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", + "DWE": "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "TMUXOUT": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "TESTIN10": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", + "TESTIN31": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", + "TESTIN11": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", + "TESTOUT4": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", + "TESTOUT58": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", + "TESTOUT36": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", + "TESTOUT56": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", + "TESTOUT44": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", + "TESTOUT63": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", + "TESTIN26": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", + "TESTOUT22": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", + "TESTIN5": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", + "TESTIN7": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", + "DO5": "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "TESTOUT17": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", + "TESTIN8": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", + "CLKFBOUT": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "TESTOUT33": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", + "DADDR6": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "DO13": "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "DRDY": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "DO7": "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "DI1": "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "DO15": "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "CLKIN2": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "TESTOUT42": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", + "TESTIN0": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", + "TESTOUT31": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", + "LOCKED": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "DO2": "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "TESTIN13": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", + "TESTIN16": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", + "TESTIN2": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", + "DI8": "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "DADDR2": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "TESTOUT5": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", + "DO11": "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "TESTOUT53": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", + "TESTOUT38": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", + "DEN": "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "TESTOUT10": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", + "TESTOUT62": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", + "TESTIN3": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", + "TESTOUT1": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", + "TESTOUT21": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", + "TESTIN15": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", + "TESTOUT16": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", + "TESTOUT45": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", + "TESTOUT26": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", + "CLKOUT1": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "TESTOUT28": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", + "TESTOUT55": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", + "TESTIN17": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", + "TESTOUT41": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", + "TESTOUT19": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", + "TESTIN19": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", + "CLKOUT0": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "DO6": "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "TESTOUT37": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37" + }, + "type": "PLLE2_ADV", + "prefix": "PLLE2_ADV", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_TOP_R_LOWER_B.json b/artix7/tile_type_CMT_TOP_R_LOWER_B.json index de5a611..dd892b4 100644 --- a/artix7/tile_type_CMT_TOP_R_LOWER_B.json +++ b/artix7/tile_type_CMT_TOP_R_LOWER_B.json @@ -1,5450 +1,5450 @@ { - "wires": [ - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_EE2A0_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG1_13", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_NE2A1_7", - "CMT_TOP_WW4A2_13", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_IMUX44_11", - "CMT_TOP_BYP5_2", - "CMT_TOP_EE2A3_5", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX19_0", - "CMT_TOP_LH11_4", - "CMT_TOP_WW2A0_4", - "CMT_R_LOWER_B_CLK_MMCM5", - "CMT_TOP_WW2END3_7", - "CMT_TOP_BYP6_0", - "CMT_TOP_CTRL1_12", - "CMT_TOP_NW2A2_9", - "CMT_TOP_IMUX44_1", - "CMT_TOP_NE2A1_8", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_IMUX39_5", - "CMT_MMCM_PHASERA_CTSBUS1", - "CMT_TOP_WW2A2_6", - "CMT_TOP_ICLKDIV_13", - "CMT_TOP_CLK1_14", - "CMT_TOP_IMUX44_10", - "CMT_TOP_NW2A0_1", - "CMT_TOP_EE2BEG2_13", - "CMT_TOP_EE4A1_10", - "CMT_TOP_NW4A0_2", - "CMT_TOP_WW2END0_8", - "CMT_TOP_SW4A0_1", - "CMT_TOP_WR1END3_14", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_WW4A2_2", - "CMT_TOP_IMUX23_0", - "CMT_TOP_NE4C3_15", - "CMT_TOP_ER1BEG3_14", - "CMT_TOP_WW4C0_8", - "CMT_TOP_BYP6_1", - "CMT_TOP_SE2A0_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_EE4BEG0_11", - "CMT_LR_LOWER_B_MMCM_DO10", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_SW2A2_1", - "CMT_TOP_FAN0_1", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_R_LOWER_B_CLK_IN1_HCLK", - "CMT_TOP_WW4END0_6", - "CMT_TOP_SW2A1_4", - "CMT_TOP_WW4A1_12", - "CMT_TOP_EE4B1_14", - "CMT_TOP_EE2A2_10", - "CMT_TOP_NW4END2_7", - "CMT_TOP_LH12_15", - "CMT_TOP_LH6_12", - "CMT_TOP_SE2A0_12", - "CMT_TOP_LOGIC_OUTS_L_B11_14", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_EE4B1_10", - "CMT_TOP_BYP5_3", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_WW4B0_10", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_WW4C2_3", - "CMT_TOP_IMUX21_13", - "CMT_TOP_BYP6_4", - "CMT_TOP_SW4A2_12", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX14_3", - "CMT_TOP_BYP7_6", - "CMT_LR_LOWER_B_MMCM_TESTOUT49", - "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "CMT_TOP_NW2A2_8", - "CMT_TOP_EL1BEG2_15", - "CMT_TOP_IMUX46_14", - "CMT_TOP_SE2A1_0", - "CMT_TOP_LOGIC_OUTS_L_B14_13", - "CMT_TOP_CTRL1_4", - "CMT_TOP_ICLK_11", - "CMT_TOP_IMUX25_14", - "CMT_TOP_IMUX0_0", - "CMT_TOP_FAN7_11", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_IMUX15_11", - "CMT_TOP_MONITOR_P_14", - "CMT_TOP_NW4END1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_EE4C0_1", - "CMT_TOP_IMUX40_13", - "CMT_TOP_WR1END0_13", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_LH1_13", - "CMT_TOP_LH8_15", - "CMT_TOP_IMUX10_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_LH6_13", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_EE4B3_15", - "CMT_TOP_IMUX29_14", - "CMT_TOP_NE4C0_0", - "CMT_TOP_EE2A1_11", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_LH1_15", - "CMT_TOP_LH11_12", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_SW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B13_15", - "CMT_TOP_WW4END0_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "CMT_TOP_IMUX28_9", - "CMT_TOP_NE4C3_6", - "CMT_TOP_LH9_1", - "CMT_TOP_EE4A3_1", - "CMT_TOP_WW2A0_6", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B17_14", - "CMT_TOP_LOGIC_OUTS_L_B0_15", - "CMT_TOP_LOGIC_OUTS_L_B12_15", - "CMT_TOP_IMUX10_4", - "CMT_TOP_BYP0_1", - "CMT_TOP_NE2A0_4", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX19_10", - "CMT_TOP_IMUX45_6", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_LH10_7", - "CMT_TOP_NW2A0_15", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_BYP2_15", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_WW4B3_11", - "CMT_TOP_NW4A3_1", - "CMT_TOP_EE4A2_6", - "CMT_TOP_FAN3_13", - "CMT_TOP_WL1END0_10", - "CMT_TOP_SW2A3_4", - "CMT_TOP_IMUX41_11", - "CMT_TOP_EE4A0_14", - "CMT_TOP_OCLK_2", - "CMT_TOP_SE4C3_11", - "CMT_TOP_EE4B2_3", - "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", - "CMT_TOP_BYP1_14", - "CMT_TOP_SE2A0_2", - "CMT_TOP_IMUX14_12", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LH11_7", - "CMT_TOP_IMUX31_1", - "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX12_6", - "CMT_TOP_SW4END3_6", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_WW2END1_1", - "CMT_TOP_LOGIC_OUTS_L_B10_14", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_IMUX29_11", - "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "CMT_TOP_WL1END2_5", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_WR1END1_8", - "CMT_TOP_IMUX12_5", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_SE4BEG2_15", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_IMUX42_5", - "CMT_TOP_EE4C1_13", - "CMT_TOP_IMUX39_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_IMUX24_7", - "CMT_LR_LOWER_B_MMCM_PSDONE", - "CMT_MMCM_A_RDCLK_TOFIFO", - "CMT_TOP_IMUX10_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_IMUX5_8", - "CMT_TOP_EE4B3_8", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2END1_14", - "CMT_TOP_WW2END2_13", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX2_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_SW2A2_11", - "CMT_TOP_IMUX47_5", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_WW4B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_EL1BEG1_15", - "CMT_TOP_WR1END2_11", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX6_6", - "CMT_TOP_SW4END1_0", - "CMT_MMCM_PHASER_OUT_A_OCLKDIV", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX30_10", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_MONITOR_N_13", - "CMT_TOP_WL1END3_6", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_SE2A2_0", - "CMT_TOP_IMUX27_0", - "CMT_TOP_SE2A2_8", - "CMT_TOP_IMUX26_10", - "CMT_TOP_WW2END2_7", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_WR1END3_7", - "CMT_MMCM_A_WREN_TOFIFO", - "CMT_TOP_EE2A0_14", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_IMUX39_9", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_EE4C3_13", - "CMT_TOP_EE4B3_12", - "CMT_TOP_LH11_8", - "CMT_TOP_WW4END2_4", - "CMT_R_LOWER_B_CLK_MMCM2", - "CMT_TOP_EE2A1_15", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_WW4END3_15", - "CMT_TOP_EE2A3_12", - "CMT_TOP_WW4A0_8", - "CMT_TOP_LH1_6", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX34_2", - "CMT_TOP_SE4C1_13", - "CMT_TOP_IMUX17_6", - "CMT_TOP_EE2A0_10", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "CMT_TOP_IMUX37_11", - "CMT_TOP_EE4B2_9", - "CMT_TOP_SE4C1_10", - "CMT_TOP_LH5_5", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_EE2A2_5", - "CMT_MMCM_PHASER_OUT_A_OCLK", - "CMT_TOP_LH4_8", - "CMT_TOP_IMUX17_15", - "CMT_TOP_IMUX45_1", - "CMT_TOP_SW4A0_4", - "CMT_TOP_FAN2_4", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX19_5", - "CMT_TOP_EE4B1_0", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4A1_13", - "CMT_TOP_BYP7_7", - "CMT_TOP_IMUX7_12", - "MMCM_CLK_FREQ_BB_NS0", - "CMT_TOP_BYP3_9", - "CMT_TOP_EE4B0_9", - "CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "CMT_TOP_WR1END1_12", - "CMT_MMCM_PHASERREF_ABOVE0", - "CMT_TOP_IMUX25_10", - "CMT_TOP_WR1END0_3", - "CMT_TOP_SW4A2_8", - "CMT_TOP_BYP4_15", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_SW4A0_3", - "CMT_TOP_CLK0_6", - "CMT_TOP_IMUX3_12", - "CMT_TOP_SE2A3_4", - "CMT_TOP_FAN7_9", - "CMT_TOP_IMUX39_10", - "CMT_TOP_LH7_6", - "CMT_TOP_EE4B2_15", - "CMT_TOP_EE2A2_11", - "CMT_TOP_BYP7_13", - "CMT_TOP_IMUX41_1", - "CMT_TOP_NE4C2_7", - "CMT_TOP_SW4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LH7_8", - "CMT_TOP_WR1END2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_12", - "CMT_TOP_FAN6_3", - "CMT_TOP_WW2A0_7", - "CMT_TOP_BYP4_2", - "CMT_TOP_IMUX33_11", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_EE4B3_1", - "CMT_LR_LOWER_B_MMCM_DI6", - "CMT_TOP_WW4END0_2", - "CMT_TOP_SW2A0_15", - "CMT_LR_LOWER_B_MMCM_TESTIN28", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_WW4A0_7", - "CMT_TOP_LH9_3", - "CMT_TOP_NE2A0_5", - "CMT_TOP_EE4C3_2", - "CMT_TOP_BYP1_15", - "CMT_TOP_NE4BEG0_15", - "CMT_TOP_LH5_10", - "CMT_LR_LOWER_B_MMCM_DI2", - "CMT_TOP_IMUX1_14", - "CMT_TOP_NE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_EE4C1_3", - "CMT_TOP_SW4A1_8", - "CMT_TOP_CTRL0_8", - "CMT_TOP_IMUX40_14", - "CMT_TOP_NW2A0_4", - "CMT_TOP_IMUX9_11", - "CMT_TOP_LOGIC_OUTS_L_B23_13", - "CMT_TOP_IMUX1_12", - "CMT_TOP_IMUX33_3", - "CMT_TOP_CTRL1_14", - "CMT_TOP_IMUX13_6", - "CMT_TOP_LH12_14", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX21_9", - "CMT_TOP_WL1END1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LH4_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_LR_LOWER_B_MMCM_TESTIN22", - "CMT_TOP_CTRL1_0", - "CMT_TOP_LH11_10", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_SE2A3_11", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_BYP3_13", - "CMT_TOP_SW2A3_0", - "CMT_TOP_BYP7_5", - "CMT_TOP_ICLK_7", - "CMT_TOP_WW4C3_7", - "CMT_TOP_IMUX8_14", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_FAN1_0", - "CMT_TOP_SW4END1_4", - "CMT_TOP_EE4C3_3", - "CMT_LR_LOWER_B_MMCM_TMUXOUT", - "CMT_TOP_BYP0_12", - "CMT_TOP_WW4B1_12", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX9_5", - "CMT_TOP_WW4B1_11", - "CMT_LR_LOWER_B_MMCM_TESTOUT53", - "CMT_TOP_IMUX13_9", - "CMT_TOP_LOGIC_OUTS_L_B20_14", - "CMT_TOP_FAN6_8", - "CMT_TOP_SE2A2_10", - "CMT_TOP_EE4A0_15", - "CMT_TOP_WW4A0_0", - "CMT_TOP_BLOCK_OUTS_L_B1_14", - "CMT_TOP_CTRL0_5", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_WW2A1_11", - "CMT_TOP_IMUX14_10", - "CMT_TOP_IMUX14_2", - "CMT_TOP_EE4B0_8", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX22_14", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_IMUX7_4", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_IMUX38_12", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_WW2A0_12", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_BYP7_2", - "CMT_TOP_WW4B3_14", - "CMT_TOP_IMUX27_14", - "CMT_TOP_IMUX4_14", - "CMT_TOP_SE4C1_0", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX15_4", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_IMUX23_3", - "CMT_TOP_WW2A2_3", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_EE4A1_7", - "CMT_TOP_IMUX31_3", - "CMT_TOP_EE4B3_11", - "CMT_TOP_IMUX25_8", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_EE2A3_11", - "CMT_TOP_SE2A0_15", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_IMUX35_2", - "CMT_LR_LOWER_B_MMCM_DO2", - "CMT_LR_LOWER_B_MMCM_DRDY", - "CMT_TOP_IMUX12_9", - "CMT_TOP_EE2A1_10", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NW2A3_0", - "CMT_TOP_SW4A3_10", - "CMT_TOP_WL1END0_3", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_WW2A3_5", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_WW2END1_3", - "CMT_TOP_SW2A2_5", - "CMT_TOP_ER1BEG3_1", - "CMT_MMCM_A_RDEN_TOFIFO", - "CMT_TOP_CTRL0_10", - "CMT_TOP_IMUX28_11", - "CMT_TOP_IMUX42_11", - "CMT_TOP_WW2END2_10", - "CMT_TOP_EE4B3_6", - "CMT_TOP_IMUX37_7", - "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "CMT_LR_LOWER_B_MMCM_DI15", - "CMT_TOP_WW4A3_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "CMT_TOP_LOGIC_OUTS_L_B9_15", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_1", - "CMT_TOP_IMUX47_9", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_IMUX17_1", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "CMT_TOP_BYP4_0", - "CMT_TOP_FAN2_9", - "CMT_TOP_SE4C3_8", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW2A3_15", - "CMT_TOP_NE2A2_1", - "CMT_TOP_IMUX37_5", - "CMT_R_LOWER_B_CLK_IN3_HCLK", - "CMT_TOP_EE2BEG0_13", - "CMT_TOP_IMUX7_7", - "CMT_TOP_LH8_12", - "CMT_TOP_IMUX20_6", - "CMT_TOP_WW4C1_9", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_SE4C3_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT56", - "CMT_TOP_NE4C3_11", - "CMT_TOP_IMUX33_5", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_EE4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BYP5_4", - "CMT_TOP_NW4END1_15", - "CMT_TOP_IMUX17_13", - "CMT_TOP_LH10_9", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_IMUX26_15", - "CMT_TOP_WW4C3_15", - "CMT_TOP_NW4A1_10", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_IMUX25_9", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EE4B0_10", - "CMT_TOP_WW4END3_2", - "CMT_TOP_IMUX30_8", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_IMUX47_0", - "CMT_TOP_BLOCK_OUTS_L_B3_13", - "CMT_LR_LOWER_B_MMCM_TESTIN23", - "CMT_TOP_IMUX16_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END1_6", - "CMT_TOP_IMUX11_11", - "CMT_TOP_WW2A0_11", - "CMT_TOP_SW4END2_7", - "CMT_TOP_IMUX34_4", - "CMT_TOP_LH12_0", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_SW4A3_11", - "CMT_TOP_NW4END2_8", - "CMT_TOP_IMUX44_13", - "CMT_TOP_IMUX36_0", - "CMT_TOP_FAN7_8", - "CMT_TOP_LH3_3", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_SE4C0_10", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX10_5", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_OCLK_15", - "CMT_TOP_NW4END2_12", - "CMT_TOP_LH7_14", - "CMT_TOP_WW2A3_0", - "CMT_TOP_LH3_4", - "CMT_TOP_IMUX45_15", - "CMT_TOP_IMUX16_6", - "CMT_TOP_FAN2_11", - "CMT_TOP_IMUX3_14", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX47_14", - "CMT_TOP_IMUX40_4", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_IMUX38_0", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_IMUX25_13", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_WW4A1_10", - "CMT_TOP_NW4A3_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_9", - "CMT_TOP_LH8_5", - "CMT_TOP_EE4B2_10", - "CMT_TOP_WW2A2_5", - "CMT_TOP_NW2A1_15", - "CMT_LR_LOWER_B_MMCM_DI9", - "CMT_TOP_IMUX29_0", - "CMT_TOP_EE4A0_8", - "CMT_TOP_WW2END3_15", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_NW4END0_2", - "CMT_TOP_IMUX16_7", - "CMT_TOP_FAN1_1", - "CMT_TOP_LH1_4", - "CMT_TOP_NW4A2_13", - "CMT_TOP_WW4C0_14", - "CMT_TOP_SW2A2_9", - "CMT_TOP_FAN2_12", - "CMT_MMCM_PHASERREF1", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_IMUX45_9", - "CMT_TOP_IMUX2_13", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_ER1BEG0_13", - "CMT_TOP_SE4C0_7", - "CMT_TOP_WR1END0_12", - "CMT_TOP_IMUX46_3", - "CMT_TOP_SW4END2_2", - "CMT_TOP_WW4B3_5", - "CMT_TOP_IMUX6_7", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_NW4A0_7", - "CMT_TOP_EE4A1_6", - "CMT_TOP_FAN2_0", - "CMT_TOP_WW4A0_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX37_2", - "CMT_TOP_IMUX28_14", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_WW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_IMUX45_8", - "CMT_TOP_FAN0_4", - "CMT_TOP_NW4END0_14", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SE4C0_3", - "CMT_TOP_IMUX22_12", - "CMT_TOP_IMUX29_6", - "CMT_MMCM_PHASERREF_BELOW1", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_WL1END1_6", - "CMT_TOP_CTRL1_15", - "CMT_TOP_WW2END1_2", - "CMT_TOP_SE4BEG3_12", - "CMT_LR_LOWER_B_MMCM_RST", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_EE2BEG3_15", - "CMT_TOP_SW4A1_6", - "CMT_TOP_FAN5_12", - "CMT_TOP_IMUX36_12", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_EL1BEG0_14", - "CMT_TOP_FAN3_9", - "CMT_TOP_EE4A1_3", - "CMT_TOP_OCLK_11", - "CMT_TOP_WW2END2_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_SE4BEG0_12", - "MMCM_CLK_FREQ_BB_NS1", - "CMT_TOP_CLK1_15", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_WW4END3_9", - "CMT_LR_LOWER_B_MMCM_TESTIN8", - "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "CMT_TOP_IMUX26_1", - "CMT_TOP_CLK1_2", - "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "CMT_TOP_ER1BEG2_13", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_LR_LOWER_B_MMCM_DO15", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_IMUX31_10", - "CMT_TOP_EE4BEG2_5", - "CMT_R_LOWER_B_CLK_MMCM13", - "CMT_TOP_IMUX23_12", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_WL1END0_8", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_IMUX29_7", - "CMT_TOP_IMUX31_15", - "CMT_TOP_NE2A3_6", - "CMT_TOP_WW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_SE4C1_15", - "CMT_TOP_NW4END1_14", - "CMT_TOP_NE2A1_6", - "CMT_TOP_IMUX27_2", - "CMT_TOP_SW4A3_1", - "CMT_TOP_NW2A3_8", - "CMT_TOP_LH7_1", - "CMT_TOP_WW4END1_7", - "CMT_R_LOWER_B_CLK_MMCM4", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_IMUX19_15", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_IMUX6_13", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_IMUX13_2", - "CMT_TOP_WW4END2_7", - "CMT_TOP_NW4END1_0", - "CMT_TOP_EE4C0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_NE4C2_9", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_IMUX29_5", - "CMT_TOP_WW2END0_0", - "CMT_TOP_IMUX20_1", - "CMT_LR_LOWER_B_MMCM_TESTIN31", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX40_7", - "CMT_TOP_FAN7_10", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_BYP6_2", - "CMT_TOP_WW4END3_13", - "CMT_TOP_IMUX42_7", - "CMT_TOP_BYP5_5", - "CMT_TOP_WW2A3_10", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX2_1", - "CMT_TOP_FAN5_7", - "CMT_TOP_SE2A2_6", - "CMT_TOP_IMUX12_11", - "CMT_TOP_EE4B1_8", - "CMT_TOP_NE2A3_4", - "CMT_TOP_SW4A3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_15", - "CMT_TOP_IMUX15_12", - "CMT_TOP_WL1END2_11", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_IMUX24_9", - "CMT_TOP_LH1_10", - "CMT_TOP_IMUX23_14", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW2A3_1", - "CMT_TOP_EE2A1_0", - "CMT_TOP_WW4C3_5", - "CMT_TOP_IMUX14_11", - "CMT_TOP_BYP1_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_7", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_NE2A1_2", - "CMT_TOP_BYP6_11", - "CMT_TOP_IMUX7_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_CLK0_12", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_LOGIC_OUTS_L_B4_14", - "CMT_TOP_IMUX30_4", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_EE4C2_13", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_WW2END3_1", - "CMT_TOP_IMUX22_0", - "CMT_TOP_WW2A3_6", - "CMT_TOP_EE4A0_6", - "CMT_TOP_SE4C2_9", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_EE4A0_9", - "CMT_TOP_FAN6_7", - "CMT_TOP_WW4A0_10", - "CMT_TOP_LH5_9", - "CMT_TOP_IMUX11_13", - "CMT_TOP_ICLK_2", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_NW4END3_0", - "CMT_TOP_SW2A1_2", - "CMT_TOP_FAN1_5", - "CMT_TOP_NW2A3_14", - "CMT_TOP_CTRL0_7", - "CMT_TOP_NW4END3_7", - "CMT_TOP_WW2A0_9", - "CMT_TOP_SE4C1_9", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_IMUX44_2", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW2END0_3", - "CMT_TOP_EE4A0_12", - "CMT_TOP_LH10_2", - "CMT_TOP_WW4C1_14", - "CMT_TOP_LH10_14", - "CMT_TOP_NE4C2_2", - "CMT_TOP_IMUX9_6", - "CMT_TOP_NW4END3_3", - "CMT_TOP_SW4A2_14", - "CMT_TOP_IMUX45_2", - "CMT_TOP_SW4A2_11", - "CMT_TOP_FAN6_1", - "CMT_TOP_IMUX22_9", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_EE2A0_13", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX17_12", - "CMT_TOP_SW4A3_8", - "CMT_TOP_LH12_8", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_FAN1_14", - "CMT_LR_LOWER_B_CLKFBOUT2IN", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_NW2A0_12", - "CMT_TOP_IMUX31_11", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_WW4END0_1", - "CMT_TOP_EE4B0_6", - "CMT_MMCM_PHASERREF_ABOVE1", - "CMT_TOP_ER1BEG1_15", - "CMT_TOP_BYP3_0", - "CMT_TOP_EE4B0_7", - "CMT_TOP_LH9_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_ER1BEG1_14", - "CMT_TOP_ER1BEG2_15", - "CMT_TOP_SW4END2_0", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_EE2A1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX35_1", - "CMT_TOP_WW2END1_8", - "CMT_TOP_EE4BEG3_14", - "CMT_TOP_IMUX19_9", - "CMT_TOP_EE4A1_15", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_LR_LOWER_B_MMCM_PSCLK", - "CMT_TOP_WW4A2_9", - "CMT_TOP_EE4B2_2", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_WW4C3_4", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_NW2A3_13", - "CMT_TOP_NE2A0_6", - "CMT_TOP_BYP1_5", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_IMUX11_10", - "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "CMT_TOP_FAN1_3", - "CMT_TOP_SE2A3_7", - "CMT_TOP_LH2_6", - "CMT_TOP_SW2A0_4", - "CMT_TOP_IMUX2_14", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_IMUX25_2", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_WR1END3_4", - "CMT_TOP_CTRL1_11", - "CMT_TOP_IMUX26_9", - "CMT_TOP_IMUX34_14", - "CMT_TOP_IMUX35_10", - "CMT_TOP_FAN0_3", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_IMUX18_12", - "CMT_TOP_EE4BEG1_13", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_WW4B1_14", - "CMT_TOP_WW4B3_10", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE4BEG3_14", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN6_15", - "CMT_TOP_IMUX32_3", - "CMT_TOP_LH7_9", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_CLK0_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WW4B1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG0_13", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_BYP6_5", - "CMT_TOP_LH6_14", - "CMT_TOP_WW2A0_10", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_IMUX39_2", - "CMT_LR_LOWER_B_MMCM_TESTOUT58", - "CMT_TOP_IMUX32_14", - "CMT_TOP_SW4A1_11", - "CMT_TOP_WR1END3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_CTRL0_4", - "CMT_TOP_LH4_5", - "CMT_LR_LOWER_B_MMCM_DI13", - "CMT_TOP_SW4END1_7", - "CMT_TOP_NW4END3_4", - "CMT_TOP_WW4B2_14", - "CMT_TOP_EE4C3_4", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_IMUX46_10", - "CMT_TOP_NW4A0_5", - "CMT_TOP_SW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_IMUX2_11", - "CMT_TOP_WW2A3_13", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_LH11_14", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_IMUX0_3", - "CMT_TOP_OCLK_5", - "CMT_TOP_FAN5_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_EE2A1_12", - "CMT_TOP_IMUX13_14", - "CMT_TOP_WL1END0_2", - "CMT_LR_LOWER_B_MMCM_TESTIN19", - "CMT_TOP_NW2A0_14", - "CMT_TOP_BYP0_5", - "CMT_TOP_NW2A0_10", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_NE4BEG2_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_EE2A2_7", - "CMT_TOP_SE2A2_2", - "CMT_TOP_CTRL1_13", - "CMT_TOP_BYP2_13", - "CMT_TOP_IMUX9_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SE2A3_15", - "CMT_TOP_NE4C1_15", - "CMT_TOP_WW4A3_11", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SW4END0_3", - "CMT_TOP_IMUX46_0", - "CMT_TOP_WW2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LH7_0", - "CMT_TOP_SE2A0_13", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_WW2A2_0", - "CMT_TOP_IMUX34_11", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_CTRL0_2", - "CMT_TOP_IMUX23_9", - "CMT_TOP_WL1END1_3", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_WW4A2_10", - "CMT_TOP_SW4END1_15", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_NE2A1_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT63", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_LOGIC_OUTS_L_B2_13", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_OCLK1X_90_13", - "CMT_TOP_IMUX16_1", - "CMT_TOP_EE2BEG2_15", - "CMT_TOP_IMUX29_12", - "CMT_TOP_WW2A0_15", - "CMT_TOP_IMUX35_11", - "CMT_TOP_NE2A3_5", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_NW2A1_1", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP5_7", - "CMT_TOP_IMUX6_1", - "CMT_TOP_LH4_10", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SW2A3_7", - "CMT_TOP_WW4C3_10", - "CMT_TOP_LH3_12", - "CMT_TOP_WW4END1_10", - "CMT_TOP_IMUX44_0", - "CMT_TOP_BYP7_11", - "CMT_TOP_LOGIC_OUTS_L_B6_14", - "CMT_TOP_WL1END1_15", - "CMT_MMCM_PHASER_OUT_B_OCLK1X_90", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX28_1", - "CMT_TOP_SE4C3_14", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LH8_1", - "CMT_TOP_WW4A0_3", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_CLK1_0", - "CMT_TOP_IMUX2_10", - "CMT_TOP_SW4A0_9", - "CMT_TOP_IMUX27_4", - "CMT_TOP_SW4A1_7", - "CMT_TOP_IMUX40_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EE4C3_12", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_IMUX15_14", - "CMT_TOP_NW2A0_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_NW4A1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_WW2A1_9", - "CMT_TOP_BYP1_11", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SW4A1_15", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_LOGIC_OUTS_L_B15_15", - "CMT_TOP_NE4C2_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "CMT_LR_LOWER_B_MMCM_TESTIN6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_NE4C1_7", - "CMT_TOP_WW4B2_1", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_NE4C0_11", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_SE2A3_2", - "CMT_TOP_LH8_3", - "CMT_TOP_IMUX13_8", - "CMT_TOP_FAN4_13", - "CMT_TOP_EE2A3_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_BLOCK_OUTS_L_B0_12", - "CMT_LR_LOWER_B_MMCM_TESTIN0", - "CMT_LR_LOWER_B_MMCM_DEN", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_WW4C3_2", - "CMT_TOP_IMUX30_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_EE4B0_2", - "CMT_TOP_BYP6_10", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX40_8", - "CMT_R_LOWER_B_CLK_IN1_INT", - "CMT_TOP_LH5_1", - "CMT_TOP_EE4B2_11", - "CMT_TOP_BYP4_9", - "CMT_R_LOWER_B_CLK_MMCM10", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_SE2A1_10", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_WR1END3_2", - "CMT_TOP_EE4B2_14", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LH8_10", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_WW4END2_15", - "CMT_TOP_IMUX13_12", - "CMT_TOP_LOGIC_OUTS_L_B18_14", - "CMT_TOP_LOGIC_OUTS_L_B21_15", - "CMT_TOP_IMUX34_7", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_NW4A2_7", - "CMT_TOP_LH9_11", - "CMT_LR_LOWER_B_MMCM_TESTIN2", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EE2A2_1", - "CMT_TOP_FAN4_6", - "CMT_TOP_EE4B3_9", - "CMT_TOP_BYP3_11", - "CMT_TOP_WW4END1_1", - "CMT_TOP_SW4END0_14", - "CMT_TOP_FAN0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_NE4C0_5", - "CMT_TOP_BYP0_11", - "CMT_TOP_SW2A0_8", - "CMT_TOP_NW2A2_2", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX0_10", - "CMT_LR_LOWER_B_MMCM_DO8", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_WR1END1_11", - "CMT_TOP_IMUX37_12", - "CMT_TOP_IMUX44_14", - "CMT_TOP_IMUX36_15", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_BYP4_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_LR_LOWER_B_MMCM_DADDR6", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_EE2A1_6", - "CMT_TOP_NE2A1_5", - "CMT_TOP_WR1END3_15", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2A3_3", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_IMUX21_12", - "CMT_TOP_FAN3_4", - "CMT_TOP_LH7_5", - "CMT_TOP_IMUX0_15", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX17_11", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "CMT_TOP_BYP0_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "CMT_TOP_LOGIC_OUTS_L_B19_13", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_PHASER_A_OCLKDIV_TOIOI", - "CMT_TOP_IMUX43_8", - "CMT_TOP_SE2A3_5", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4C1_6", - "CMT_TOP_WW4C0_2", - "CMT_TOP_LH12_7", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_EE2A1_9", - "CMT_TOP_WW2END2_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_NE2A0_13", - "CMT_MMCM_PHASER_IN_A_ICLKDIV", - "CMT_TOP_BYP4_5", - "CMT_TOP_IMUX22_3", - "CMT_TOP_NE2A2_6", - "CMT_TOP_FAN5_10", - "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "CMT_TOP_SW4A3_13", - "CMT_TOP_EE4A0_7", - "CMT_TOP_WW2END1_10", - "CMT_TOP_IMUX19_12", - "CMT_TOP_LOGIC_OUTS_L_B23_14", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_IMUX38_11", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WW4B2_5", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_NE2A2_9", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_FAN1_13", - "CMT_TOP_FAN0_12", - "CMT_TOP_IMUX2_8", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END1_13", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WW2A2_10", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_IMUX28_2", - "CMT_TOP_SE4C0_13", - "CMT_TOP_WW4C1_4", - "CMT_TOP_EE4C2_7", - "CMT_TOP_LH12_1", - "CMT_TOP_NE2A0_3", - "CMT_TOP_SE2A3_13", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE4C0_4", - "CMT_TOP_IMUX46_13", - "CMT_R_LOWER_B_CLK_MMCM3", - "CMT_TOP_LH11_0", - "CMT_TOP_WW2A1_2", - "CMT_TOP_FAN6_2", - "CMT_TOP_IMUX22_7", - "CMT_TOP_WW2END3_4", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SE2A2_4", - "CMT_TOP_NW4END0_12", - "CMT_TOP_SW4A1_0", - "CMT_MMCM_PHYCTRL_SYNC_BB_UP", - "CMT_TOP_IMUX1_8", - "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "CMT_TOP_WW4C2_4", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_2", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_IMUX39_15", - "CMT_TOP_IMUX20_11", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4END3_10", - "CMT_TOP_IMUX21_15", - "CMT_TOP_CLK0_2", - "CMT_TOP_IMUX11_2", - "CMT_TOP_WW2END0_5", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_WW4B1_1", - "CMT_TOP_LH6_7", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE4B2_8", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_WW4A3_6", - "CMT_TOP_SW2A0_14", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B10_15", - "CMT_TOP_BYP5_11", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_EE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_EE2BEG3_14", - "CMT_TOP_CTRL1_3", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_CLK1_3", - "CMT_TOP_IMUX34_0", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_IMUX30_11", - "CMT_TOP_NE4BEG0_14", - "CMT_TOP_SE2A3_8", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX30_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_FAN7_3", - "CMT_TOP_EE4C1_15", - "CMT_TOP_IMUX33_6", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_IMUX4_13", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_NW4END1_9", - "CMT_LR_LOWER_B_MMCM_TESTOUT55", - "CMT_TOP_WW4END2_10", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_SW4END0_10", - "CMT_TOP_EE4BEG0_15", - "CMT_TOP_EE4C2_11", - "CMT_TOP_WW4END1_6", - "CMT_TOP_IMUX16_10", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_WR1END3_1", - "CMT_TOP_NE2A2_15", - "CMT_TOP_IMUX26_11", - "CMT_TOP_NE2A0_0", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX28_6", - "CMT_TOP_SE4C2_11", - "CMT_TOP_IMUX31_14", - "CMT_TOP_FAN2_14", - "CMT_TOP_EE4A2_2", - "CMT_TOP_IMUX13_1", - "CMT_TOP_WW4END0_14", - "CMT_TOP_IMUX24_0", - "CMT_TOP_NW4END2_4", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW4C3_3", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_EE4C3_5", - "CMT_TOP_SE2A0_8", - "CMT_TOP_IMUX0_2", - "CMT_TOP_EE4C0_5", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SW4END2_12", - "CMT_TOP_EE4BEG3_13", - "CMT_TOP_NW4END0_13", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX36_4", - "CMT_TOP_WW4C1_13", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_WR1END1_4", - "CMT_TOP_SW4END0_11", - "CMT_TOP_LH5_8", - "CMT_TOP_LH8_9", - "CMT_TOP_IMUX21_0", - "CMT_TOP_WL1END0_7", - "CMT_TOP_SW2A0_6", - "CMT_TOP_WL1END3_14", - "CMT_TOP_WW4END3_6", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_IMUX7_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_EE2A1_5", - "CMT_TOP_NW2A0_8", - "CMT_TOP_WL1END0_12", - "CMT_TOP_IMUX21_10", - "CMT_TOP_SW2A2_6", - "CMT_TOP_IMUX26_0", - "CMT_TOP_NW4A3_15", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_IMUX30_14", - "CMT_TOP_IMUX23_1", - "CMT_TOP_EL1BEG1_5", - "CMT_LR_LOWER_B_MMCM_TESTIN30", - "CMT_TOP_WW4C1_12", - "CMT_TOP_IMUX3_6", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_BYP0_0", - "CMT_TOP_SW4END0_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_ICLK_12", - "CMT_TOP_IMUX40_12", - "CMT_TOP_SW4A3_14", - "CMT_TOP_BYP3_4", - "CMT_TOP_WW4C2_1", - "CMT_TOP_BYP1_3", - "CMT_LR_LOWER_B_MMCM_TESTIN26", - "CMT_TOP_IMUX8_0", - "CMT_TOP_EE2A2_13", - "CMT_TOP_IMUX24_12", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_IMUX43_3", - "CMT_TOP_WW4END1_15", - "CMT_TOP_NW4A2_8", - "CMT_TOP_WR1END3_6", - "CMT_TOP_SE4BEG2_14", - "CMT_TOP_IMUX10_13", - "CMT_TOP_LH4_14", - "CMT_TOP_WW4C3_12", - "CMT_TOP_ICLK_5", - "CMT_TOP_WW2END0_15", - "CMT_TOP_IMUX0_12", - "CMT_TOP_IMUX39_13", - "CMT_TOP_WW2END2_4", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_IMUX18_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_IMUX9_15", - "CMT_TOP_NW4A2_9", - "CMT_MMCM_PHASER_OUT_B_OCLK", - "CMT_TOP_EE4A3_15", - "CMT_TOP_WW4END0_0", - "CMT_TOP_NW4END0_11", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_WW4C2_11", - "CMT_TOP_IMUX18_5", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SW2A1_1", - "CMT_TOP_EE4C0_12", - "CMT_TOP_BYP3_10", - "CMT_TOP_IMUX16_12", - "CMT_TOP_EE4A3_4", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX20_5", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_14", - "CMT_TOP_WW4B0_13", - "CMT_LR_LOWER_B_MMCM_TESTOUT6", - "CMT_TOP_WL1END2_15", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_IMUX24_8", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LH3_5", - "CMT_TOP_IMUX26_2", - "CMT_TOP_LOGIC_OUTS_L_B11_15", - "CMT_TOP_WW4A0_11", - "CMT_TOP_IMUX19_8", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_SE2A1_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "CMT_TOP_WL1END1_12", - "CMT_TOP_BYP4_11", - "CMT_TOP_NW4A3_10", - "CMT_TOP_SE4BEG2_13", - "CMT_TOP_FAN1_7", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_WW4A2_0", - "CMT_TOP_IMUX28_10", - "CMT_TOP_NW4A2_12", - "CMT_LR_LOWER_B_MMCM_DI0", - "MMCMOUT_CLK_FREQ_BB_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_WW2A3_9", - "CMT_TOP_NE4C2_14", - "CMT_TOP_EE4A1_4", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX33_12", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_IMUX46_5", - "CMT_TOP_NE2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B17_13", - "CMT_TOP_EE4A1_13", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LH10_12", - "MMCM_CLK_FREQ_BB_REBUF2_NS", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_WR1END2_8", - "CMT_TOP_IMUX10_12", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE4A1_14", - "CMT_LR_LOWER_B_MMCM_DO13", - "CMT_TOP_IMUX26_7", - "CMT_TOP_IMUX28_3", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_FAN3_14", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_NW4END2_10", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2BEG0_14", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_FAN3_8", - "CMT_TOP_EE4BEG3_2", - "CMT_LR_LOWER_B_MMCM_CLKIN2", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_SE2A2_13", - "CMT_TOP_NW4END0_1", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_FAN3_6", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_SW4END1_14", - "CMT_TOP_EE2A3_10", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_SW4END3_1", - "CMT_TOP_LOGIC_OUTS_L_B1_15", - "CMT_LR_LOWER_B_MMCM_DADDR4", - "CMT_TOP_IMUX22_11", - "CMT_TOP_WW4A2_7", - "CMT_TOP_NW4A2_1", - "CMT_TOP_IMUX22_15", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW4C3_8", - "CMT_TOP_NE2A0_8", - "CMT_LR_LOWER_B_MMCM_DI4", - "CMT_TOP_IMUX12_10", - "CMT_TOP_WW4C3_9", - "CMT_TOP_NE2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_FAN5_9", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_IMUX4_15", - "CMT_TOP_FAN3_0", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_3", - "CMT_TOP_SW2A0_7", - "CMT_LR_LOWER_B_MMCM_DI10", - "CMT_TOP_LH3_13", - "CMT_TOP_IMUX3_1", - "CMT_TOP_NE4C0_1", - "CMT_TOP_WL1END3_4", - "CMT_TOP_IMUX37_9", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_NW4END3_5", - "CMT_TOP_LH12_13", - "CMT_TOP_IMUX24_14", - "CMT_TOP_WW2A2_7", - "CMT_TOP_FAN2_5", - "CMT_TOP_IMUX18_14", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WL1END3_0", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_IMUX36_1", - "CMT_TOP_SW2A1_9", - "CMT_TOP_EE4A3_2", - "CMT_TOP_BYP3_14", - "CMT_TOP_IMUX15_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LH3_6", - "CMT_TOP_IMUX27_6", - "CMT_TOP_WW2END2_0", - "CMT_TOP_NW4END1_13", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX43_2", - "CMT_TOP_EE4B2_13", - "CMT_TOP_WW4A1_15", - "CMT_TOP_NE4C3_9", - "CMT_TOP_WW2END2_9", - "CMT_TOP_IMUX29_13", - "CMT_TOP_LH9_15", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW2A1_13", - "CMT_TOP_IMUX4_5", - "CMT_PHASER_A_OCLK_TOIOI", - "CMT_TOP_EE4C0_9", - "CMT_TOP_BYP7_12", - "CMT_LR_LOWER_B_MMCM_DO1", - "CMT_TOP_ER1BEG3_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_WR1END2_10", - "CMT_TOP_NW4A0_14", - "CMT_TOP_NE4C1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_SW2A3_12", - "CMT_TOP_WW2A0_8", - "CMT_TOP_SE4C2_8", - "CMT_TOP_IMUX26_12", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_IMUX38_8", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_LH1_3", - "CMT_TOP_BYP1_2", - "CMT_TOP_LOGIC_OUTS_L_B4_15", - "CMT_TOP_IMUX26_5", - "CMT_TOP_SE4C3_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_NE4C0_10", - "CMT_TOP_WW4C0_12", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_LOGIC_OUTS_L_B3_14", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX38_15", - "CMT_TOP_WW4C0_1", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_IMUX38_6", - "CMT_TOP_LH6_10", - "CMT_TOP_FAN3_12", - "CMT_TOP_LH10_15", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_NW2A2_13", - "CMT_TOP_WW4B3_4", - "CMT_TOP_IMUX16_15", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_SW4A1_13", - "CMT_TOP_IMUX1_10", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WL1END2_13", - "CMT_TOP_SE2A0_9", - "CMT_TOP_WW4B0_12", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX36_7", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_IMUX39_8", - "CMT_TOP_SE2A0_14", - "CMT_TOP_WW4B0_5", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_BYP4_7", - "CMT_TOP_IMUX43_9", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_NE4BEG3_2", - "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "CMT_TOP_WW2END3_10", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_LR_LOWER_B_MMCM_TESTIN14", - "CMT_TOP_IMUX12_12", - "CMT_TOP_SW2A0_5", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_LH4_12", - "CMT_TOP_SW4END1_9", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_ER1BEG3_15", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_FAN0_2", - "CMT_TOP_BYP7_15", - "CMT_TOP_IMUX19_1", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_NW2A3_11", - "CMT_TOP_IMUX41_0", - "CMT_TOP_FAN3_2", - "CMT_TOP_WW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_SW2A3_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SE2A1_11", - "CMT_TOP_WW4A0_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_EE4B0_0", - "CMT_TOP_NW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_NE2A3_14", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_NW2A3_3", - "CMT_TOP_SE4C0_8", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4END2_3", - "CMT_TOP_NE2A3_10", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_TOP_NW4END3_15", - "CMT_TOP_LH1_5", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_WW4B2_10", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END3_14", - "CMT_TOP_SW4END1_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_IMUX25_6", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LH9_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX47_4", - "CMT_TOP_FAN0_14", - "CMT_TOP_IMUX37_3", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_LH1_9", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_ICLK_13", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_MMCM_PHASERREF_BELOW0", - "CMT_TOP_EE2BEG1_14", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_SW4A3_12", - "CMT_TOP_EE4C2_6", - "CMT_TOP_IMUX36_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_WW4A2_14", - "CMT_TOP_WW4A3_3", - "CMT_R_LOWER_B_CLK_PERF0", - "CMT_TOP_IMUX17_8", - "CMT_TOP_LH2_8", - "CMT_TOP_IMUX39_12", - "CMT_LR_LOWER_B_MMCM_TESTOUT7", - "CMT_TOP_IMUX29_8", - "CMT_TOP_FAN7_12", - "CMT_TOP_WW2A2_15", - "CMT_TOP_IMUX34_10", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_WW4A3_2", - "CMT_LR_LOWER_B_MMCM_PWRDWN", - "CMT_TOP_EE4B1_12", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_EE4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_LH12_12", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_WR1END2_14", - "CMT_TOP_NE2A2_11", - "CMT_TOP_LH3_1", - "CMT_TOP_SW4A3_5", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_WW4END1_5", - "MMCM_CLK_FREQ_BB_NS3", - "CMT_TOP_EE2BEG3_13", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX0_14", - "CMT_TOP_IMUX11_8", - "CMT_TOP_NW4END2_11", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX8_2", - "CMT_TOP_EL1BEG1_12", - "CMT_TOP_OCLK1X_90_6", - "CMT_LR_LOWER_B_MMCM_DI1", - "CMT_TOP_IMUX17_14", - "CMT_TOP_WW2A3_3", - "CMT_TOP_EE4A2_3", - "CMT_TOP_SW4A1_1", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_8", - "CMT_TOP_WW4A1_6", - "CMT_TOP_IMUX41_2", - "CMT_TOP_LH8_6", - "CMT_TOP_SE4C1_8", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WW4A2_6", - "CMT_TOP_BYP0_6", - "CMT_TOP_IMUX43_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX42_12", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WL1END1_13", - "CMT_TOP_NE4C1_14", - "CMT_TOP_NW4END3_11", - "CMT_TOP_WR1END3_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_ER1BEG0_15", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_EE2A2_15", - "CMT_LR_LOWER_B_MMCM_DI5", - "CMT_TOP_NW4A0_4", - "CMT_TOP_IMUX24_4", - "CMT_TOP_EE4C1_10", - "CMT_TOP_CLK0_11", - "CMT_LR_LOWER_B_MMCM_TESTIN18", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WW4C1_8", - "CMT_TOP_IMUX22_1", - "CMT_TOP_NW2A0_7", - "CMT_TOP_LH1_11", - "CMT_TOP_IMUX17_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_IMUX19_11", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX4_1", - "CMT_TOP_OCLKDIV_13", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX10_9", - "CMT_TOP_EE2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_FAN3_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT5", - "CMT_TOP_IMUX11_12", - "CMT_TOP_CLK1_4", - "CMT_TOP_LH5_14", - "CMT_TOP_LH2_2", - "CMT_TOP_WW2END0_14", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_IMUX44_15", - "CMT_TOP_LOGIC_OUTS_L_B20_13", - "CMT_TOP_NE4C2_3", - "CMT_TOP_EE4A2_7", - "CMT_TOP_LOGIC_OUTS_L_B16_14", - "CMT_TOP_IMUX11_0", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_SW2A2_13", - "CMT_TOP_IMUX38_3", - "CMT_TOP_SW4A0_13", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_10", - "CMT_TOP_IMUX6_10", - "CMT_TOP_IMUX5_9", - "CMT_TOP_LH3_9", - "CMT_TOP_NW4END2_2", - "CMT_TOP_WW4A1_14", - "CMT_TOP_WW2A2_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_LH4_9", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4B0_6", - "CMT_TOP_BYP1_9", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_NW4A1_5", - "CMT_TOP_WW2END3_13", - "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "CMT_TOP_SE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_EL1BEG3_15", - "CMT_TOP_SE4BEG2_12", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_SW4END3_10", - "CMT_TOP_IMUX9_1", - "CMT_TOP_NW4A1_9", - "CMT_TOP_WW4C2_14", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_BYP7_8", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX46_7", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_IMUX30_1", - "CMT_TOP_WW4C0_5", - "CMT_TOP_NW4A1_2", - "CMT_TOP_WW4C3_14", - "CMT_TOP_LH4_13", - "CMT_TOP_WW2END0_2", - "CMT_TOP_NW4A1_15", - "CMT_TOP_FAN0_0", - "CMT_TOP_IMUX32_13", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX28_13", - "CMT_TOP_IMUX18_8", - "CMT_TOP_CLK0_14", - "CMT_TOP_NW4A1_12", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4C0_13", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX20_4", - "CMT_TOP_ER1BEG2_14", - "CMT_TOP_EE4C3_6", - "CMT_TOP_FAN6_12", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_IMUX39_11", - "CMT_TOP_NE4C0_2", - "CMT_TOP_EE4B1_2", - "CMT_LR_LOWER_B_MMCM_TESTOUT59", - "CMT_TOP_IMUX4_9", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SE4C1_1", - "CMT_TOP_EE4A1_9", - "CMT_TOP_IMUX21_14", - "CMT_TOP_IMUX30_2", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_EE2A2_2", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4A2_8", - "CMT_TOP_IMUX30_15", - "CMT_MMCM_PHASER_IN_A_ICLK", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_IMUX23_8", - "CMT_TOP_SW4END0_6", - "CMT_TOP_IMUX12_2", - "CMT_TOP_NW2A2_7", - "CMT_TOP_LOGIC_OUTS_L_B18_15", - "CMT_TOP_WL1END2_7", - "CMT_TOP_BYP5_1", - "CMT_TOP_EE4B1_9", - "CMT_TOP_SE4C0_15", - "CMT_TOP_IMUX43_15", - "CMT_TOP_IMUX2_12", - "CMT_TOP_NE2A3_15", - "CMT_TOP_IMUX33_0", - "CMT_TOP_WW2A2_9", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_IMUX18_15", - "CMT_TOP_IMUX27_15", - "CMT_TOP_OCLK_7", - "CMT_TOP_FAN1_10", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_SW2A1_10", - "CMT_TOP_IMUX19_7", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_IMUX16_14", - "CMT_TOP_SE4C0_6", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_IMUX3_0", - "CMT_TOP_WL1END1_8", - "CMT_TOP_NW4END1_5", - "CMT_LR_LOWER_B_MMCM_DO5", - "CMT_LR_LOWER_B_MMCM_TESTIN24", - "CMT_TOP_BYP5_6", - "CMT_TOP_LH6_2", - "CMT_TOP_IMUX39_6", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_IMUX36_2", - "CMT_TOP_WW2A0_5", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_BYP5_14", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_BYP2_0", - "CMT_TOP_IMUX8_3", - "CMT_TOP_ICLK_6", - "CMT_TOP_WW2END2_14", - "CMT_TOP_LH2_0", - "CMT_TOP_EE2A3_15", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX40_2", - "CMT_TOP_BYP5_15", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "CMT_TOP_WW4END3_1", - "CMT_TOP_SW4A2_4", - "CMT_TOP_LH11_11", - "CMT_TOP_WW4C0_15", - "CMT_TOP_IMUX46_2", - "CMT_TOP_LOGIC_OUTS_L_B12_14", - "CMT_TOP_NE2A3_1", - "CMT_TOP_WW4B3_13", - "CMT_TOP_IMUX16_13", - "CMT_TOP_NW4A3_2", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_IMUX17_10", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX30_12", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW4END1_3", - "CMT_TOP_SE4BEG1_15", - "CMT_TOP_NW2A3_7", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_NW4A3_8", - "CMT_TOP_LOGIC_OUTS_L_B6_13", - "CMT_TOP_SW4END2_8", - "CMT_TOP_WL1END3_12", - "CMT_TOP_IMUX43_13", - "CMT_TOP_SE2A0_11", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_SW2A1_15", - "CMT_TOP_SW4A1_14", - "CMT_TOP_IMUX24_13", - "CMT_TOP_EE4A1_12", - "CMT_TOP_WW2END0_7", - "CMT_TOP_SW4A2_13", - "CMT_TOP_WW4A2_15", - "CMT_TOP_EE4C0_6", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_EE4C0_7", - "CMT_TOP_WL1END0_0", - "CMT_TOP_EE4C3_15", - "CMT_TOP_FAN7_2", - "CMT_TOP_WL1END3_1", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_LH3_15", - "CMT_TOP_LH8_4", - "CMT_TOP_LH5_6", - "CMT_TOP_BYP2_11", - "CMT_TOP_SW4A0_6", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_WR1END2_12", - "CMT_TOP_IMUX7_14", - "CMT_TOP_BYP7_4", - "CMT_TOP_EE4C2_12", - "CMT_TOP_LH10_6", - "CMT_TOP_WW4END1_14", - "CMT_TOP_SE4C2_4", - "CMT_TOP_FAN1_12", - "CMT_TOP_IMUX35_9", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_EE2BEG0_15", - "CMT_TOP_IMUX46_4", - "CMT_TOP_LH4_2", - "CMT_TOP_IMUX6_12", - "CMT_TOP_IMUX44_3", - "CMT_TOP_EE4A3_8", - "CMT_TOP_IMUX24_2", - "CMT_TOP_EE4A3_11", - "CMT_TOP_IMUX14_5", - "CMT_R_LOWER_B_CLK_PERF3", - "CMT_TOP_IMUX34_5", - "CMT_TOP_LH4_15", - "CMT_TOP_NW4END2_9", - "CMT_TOP_IMUX20_9", - "CMT_TOP_WW4B1_13", - "CMT_TOP_IMUX29_1", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_IMUX13_13", - "CMT_TOP_EL1BEG3_14", - "CMT_TOP_SW4A2_3", - "CMT_TOP_FAN1_9", - "CMT_TOP_BYP7_1", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WL1END3_8", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX35_0", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX17_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_OCLK_0", - "CMT_TOP_SE4C2_13", - "CMT_TOP_IMUX13_11", - "CMT_TOP_IMUX31_7", - "CMT_TOP_WR1END0_14", - "CMT_LR_LOWER_B_MMCM_DADDR5", - "CMT_TOP_WL1END1_11", - "CMT_TOP_EE2BEG1_15", - "CMT_TOP_IMUX2_2", - "CMT_TOP_WW4END3_5", - "CMT_TOP_LH1_1", - "CMT_TOP_FAN5_8", - "CMT_TOP_SW4A0_15", - "CMT_TOP_NW4END3_8", - "CMT_TOP_WW4B2_15", - "CMT_TOP_WW4A1_1", - "CMT_LR_LOWER_B_MMCM_DO7", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_IMUX22_13", - "CMT_TOP_EE2A3_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_LR_LOWER_B_MMCM_TESTOUT61", - "CMT_TOP_WW2END2_3", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_WW2END2_6", - "CMT_TOP_IMUX41_10", - "CMT_LR_LOWER_B_MMCM_DO9", - "CMT_TOP_SW4A0_14", - "CMT_TOP_EE4B2_1", - "CMT_TOP_NW4END3_1", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_12", - "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "CMT_TOP_EE4B1_13", - "CMT_TOP_IMUX13_15", - "CMT_TOP_IMUX33_13", - "CMT_TOP_LH3_0", - "CMT_TOP_LH2_5", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_IMUX19_14", - "CMT_TOP_EE4A3_3", - "CMT_TOP_NW4A2_3", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_WW4END2_14", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SE4C0_12", - "CMT_TOP_IMUX34_8", - "CMT_TOP_EE4A3_14", - "CMT_TOP_SW4A2_10", - "CMT_TOP_NW2A3_1", - "CMT_TOP_IMUX31_6", - "CMT_TOP_WW4B3_15", - "CMT_TOP_IMUX32_11", - "CMT_TOP_WW4B3_7", - "CMT_TOP_LH11_9", - "CMT_TOP_NE2A2_2", - "CMT_TOP_FAN7_14", - "CMT_TOP_FAN5_3", - "CMT_TOP_NW4A2_0", - "CMT_TOP_IMUX12_15", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_WW4C2_10", - "CMT_TOP_BYP7_0", - "CMT_TOP_LH6_0", - "CMT_TOP_NE4C1_4", - "CMT_TOP_IMUX16_9", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_EE4A0_10", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B7_15", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX31_13", - "CMT_TOP_WW4C0_10", - "CMT_TOP_IMUX45_14", - "CMT_TOP_FAN1_2", - "CMT_TOP_MONITOR_P_15", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_FAN1_15", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_WW4B2_6", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_IMUX29_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LH3_11", - "CMT_TOP_IMUX32_7", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_WR1END0_15", - "CMT_TOP_BYP2_3", - "CMT_TOP_IMUX1_6", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX20_3", - "CMT_TOP_LH7_3", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX28_8", - "CMT_TOP_NW4END2_5", - "CMT_TOP_WW2A0_3", - "CMT_R_LOWER_B_CLK_MMCM7", - "CMT_TOP_SE2A2_14", - "CMT_TOP_IMUX33_9", - "CMT_TOP_WR1END1_9", - "CMT_TOP_IMUX18_4", - "CMT_LR_LOWER_B_MMCM_DADDR2", - "CMT_TOP_WW4END1_13", - "CMT_TOP_BYP1_13", - "CMT_TOP_IMUX23_11", - "CMT_TOP_SW4END2_4", - "CMT_TOP_FAN6_0", - "CMT_TOP_LH6_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_IMUX4_3", - "CMT_TOP_EE4B3_14", - "CMT_TOP_WL1END2_12", - "CMT_TOP_SW4END3_3", - "CMT_TOP_NE4C3_14", - "CMT_TOP_WW4B0_3", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP3_2", - "CMT_TOP_CTRL0_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_SW4END0_13", - "CMT_TOP_CLK1_8", - "CMT_TOP_SE2A1_14", - "CMT_TOP_FAN3_3", - "CMT_TOP_EE4A3_6", - "CMT_TOP_OCLK_13", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_LR_LOWER_B_MMCM_TESTOUT62", - "CMT_TOP_IMUX41_14", - "CMT_TOP_IMUX42_0", - "CMT_TOP_LH12_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT60", - "CMT_TOP_IMUX20_13", - "CMT_TOP_SW2A0_9", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_FAN0_6", - "CMT_MMCM_DQS_TO_PHASERA", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_NE2A2_13", - "CMT_TOP_EE4A2_13", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "CMT_TOP_WW4A0_13", - "CMT_TOP_SW4END0_1", - "CMT_TOP_FAN5_11", - "CMT_TOP_IMUX1_0", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_NW2A3_4", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_NE4C0_15", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_WW4END1_9", - "CMT_TOP_EE2A2_4", - "CMT_TOP_ER1BEG1_13", - "CMT_TOP_WL1END0_4", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_IMUX4_10", - "CMT_TOP_WL1END0_14", - "CMT_TOP_WL1END1_14", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_IMUX45_13", - "CMT_TOP_IMUX34_12", - "CMT_TOP_SW4END3_4", - "CMT_TOP_WW4C3_1", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_EE4BEG3_8", - "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "CMT_TOP_WL1END0_6", - "CMT_TOP_IMUX41_13", - "CMT_TOP_EE4A0_3", - "CMT_TOP_NW4A3_6", - "CMT_TOP_LH7_12", - "CMT_TOP_BYP2_5", - "CMT_TOP_ICLK_0", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LH6_9", - "CMT_TOP_CTRL1_9", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_IMUX33_4", - "CMT_TOP_NW2A1_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_LOGIC_OUTS_L_B19_14", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_EE4B0_4", - "CMT_TOP_NE2A1_0", - "CMT_TOP_IMUX1_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_WR1END0_6", - "CMT_TOP_LH12_2", - "CMT_TOP_FAN5_5", - "CMT_TOP_IMUX4_8", - "CMT_TOP_SW2A2_7", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX5_15", - "CMT_TOP_LOGIC_OUTS_L_B22_15", - "CMT_TOP_WW4A3_7", - "CMT_R_LOWER_B_CLK_PERF1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_WL1END1_10", - "CMT_TOP_BYP6_3", - "CMT_TOP_FAN2_6", - "CMT_TOP_WR1END1_1", - "CMT_TOP_OCLK_3", - "CMT_TOP_EE4C2_8", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_IMUX31_9", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX35_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "CMT_TOP_OCLK_8", - "CMT_TOP_FAN4_3", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_IMUX8_15", - "CMT_TOP_IMUX9_14", - "CMT_TOP_NE4BEG0_5", - "CMT_LR_LOWER_B_MMCM_DADDR1", - "CMT_TOP_LH4_4", - "CMT_TOP_EE4B3_0", - "CMT_TOP_NE4C0_12", - "CMT_TOP_NE4C2_13", - "CMT_TOP_EE4C3_11", - "CMT_TOP_LOGIC_OUTS_L_B7_14", - "CMT_TOP_FAN4_8", - "CMT_TOP_SW2A3_13", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_LOGIC_OUTS_L_B23_15", - "CMT_LR_LOWER_B_MMCM_DO12", - "CMT_TOP_EE2A3_7", - "CMT_TOP_WR1END1_15", - "CMT_TOP_EE4B1_5", - "CMT_TOP_OCLKDIV_15", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_LH8_13", - "CMT_TOP_IMUX42_14", - "CMT_TOP_IMUX33_1", - "CMT_TOP_EE4C1_5", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4B3_0", - "CMT_TOP_LOGIC_OUTS_L_B14_15", - "CMT_TOP_LH2_1", - "CMT_TOP_LH6_8", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_IMUX14_8", - "CMT_R_LOWER_B_CLK_MMCM12", - "CMT_TOP_WL1END0_1", - "CMT_TOP_NE2A3_3", - "CMT_TOP_IMUX12_8", - "CMT_TOP_EE4A1_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_EE4BEG1_15", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_WW4A1_11", - "CMT_TOP_IMUX46_9", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE4C2_6", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX18_1", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_NW4END1_10", - "CMT_TOP_IMUX20_8", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NE2A3_2", - "CMT_TOP_SE2A0_6", - "CMT_TOP_IMUX30_3", - "CMT_TOP_LH7_10", - "CMT_TOP_OCLK_6", - "CMT_TOP_WW4END0_12", - "CMT_TOP_SW4END0_9", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX37_6", - "CMT_TOP_EE4BEG0_13", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_LOGIC_OUTS_L_B19_15", - "CMT_TOP_WW4END3_14", - "CMT_TOP_BLOCK_OUTS_L_B3_14", - "CMT_TOP_WW4B2_3", - "CMT_TOP_BYP4_14", - "CMT_TOP_WW4C2_5", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_EE4B2_5", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WW4A1_5", - "CMT_TOP_BYP3_7", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_FAN2_1", - "CMT_TOP_IMUX36_11", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_IMUX44_6", - "CMT_TOP_OCLK_1", - "CMT_TOP_NE4BEG2_13", - "CMT_TOP_NW2A0_9", - "CMT_TOP_WW4C2_12", - "CMT_TOP_IMUX43_12", - "CMT_TOP_IMUX36_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_CLK0_15", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_IMUX6_15", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_WW4END2_2", - "CMT_TOP_LH12_9", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_NE2A2_10", - "CMT_TOP_SW4END2_9", - "CMT_TOP_EE2A2_3", - "CMT_TOP_LH4_7", - "CMT_TOP_ER1BEG1_2", - "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_IMUX6_0", - "CMT_LR_LOWER_B_MMCM_TESTOUT9", - "CMT_LR_LOWER_B_MMCM_TESTOUT50", - "CMT_TOP_NE2A0_9", - "CMT_TOP_WW4B3_3", - "CMT_TOP_BYP4_6", - "CMT_TOP_FAN3_10", - "CMT_TOP_BYP6_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_NE2A1_1", - "CMT_TOP_WW4END1_8", - "CMT_TOP_SW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_CTRL0_3", - "CMT_TOP_WW4B3_1", - "CMT_TOP_NW4A2_4", - "CMT_TOP_OCLK1X_90_15", - "CMT_TOP_LH4_11", - "CMT_TOP_SW4END1_13", - "CMT_TOP_IMUX6_14", - "CMT_LR_LOWER_B_MMCM_DO3", - "CMT_TOP_LOGIC_OUTS_L_B3_13", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_SE4C3_3", - "CMT_TOP_WW2END1_9", - "CMT_TOP_LOGIC_OUTS_L_B11_13", - "CMT_R_LOWER_B_CLK_FREQ_BB3", - "CMT_TOP_EE4BEG0_14", - "CMT_LR_LOWER_B_MMCM_DI12", - "CMT_TOP_NE4C3_1", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WL1END3_9", - "CMT_TOP_IMUX23_15", - "CMT_TOP_SE4C0_4", - "CMT_TOP_IMUX47_15", - "CMT_TOP_EE4C3_0", - "CMT_TOP_IMUX9_10", - "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", - "CMT_TOP_LOGIC_OUTS_L_B5_14", - "CMT_TOP_WW4C1_3", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_EE4A1_11", - "CMT_TOP_NW2A2_10", - "CMT_TOP_CTRL1_8", - "CMT_TOP_WL1END1_1", - "CMT_TOP_OCLKDIV_5", - "CMT_LR_LOWER_B_MMCM_TESTIN20", - "CMT_TOP_NW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_NW2A1_11", - "CMT_TOP_EE4B2_0", - "CMT_TOP_LH5_7", - "CMT_LR_LOWER_B_MMCM_TESTIN27", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX2_5", - "CMT_TOP_LH11_15", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_CLK0_1", - "CMT_TOP_IMUX6_4", - "CMT_TOP_NW4A2_11", - "CMT_TOP_EE2A2_8", - "CMT_TOP_LH1_14", - "CMT_TOP_SE4C3_7", - "CMT_TOP_WW4C0_7", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_SW2A1_12", - "CMT_TOP_NW4A1_14", - "CMT_TOP_SE4C2_5", - "CMT_TOP_IMUX32_0", - "CMT_TOP_SW2A3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_NE4BEG0_10", - "CMT_MMCM_PHASERREF0", - "CMT_TOP_WW2END3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_SW2A3_14", - "CMT_TOP_EE4B1_4", - "CMT_TOP_IMUX29_15", - "CMT_TOP_IMUX43_7", - "CMT_TOP_NW4END3_13", - "CMT_TOP_OCLK_14", - "CMT_TOP_IMUX27_5", - "CMT_TOP_IMUX20_14", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_EE4C0_0", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_LOGIC_OUTS_L_B5_15", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_WW4B0_9", - "CMT_TOP_OCLK1X_90_10", - "CMT_MMCM_PHASERA_DTSBUS0", - "CMT_TOP_NW4END2_0", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_WW4END3_11", - "MMCM_CLK_FREQ_BB_REBUF3_NS", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_EE4B1_3", - "CMT_TOP_LOGIC_OUTS_L_B2_14", - "CMT_TOP_NW4END3_2", - "CMT_TOP_IMUX21_1", - "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "CMT_TOP_IMUX31_12", - "MMCM_CLK_FREQ_BB_NS2", - "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "CMT_TOP_SW4END0_0", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW2END1_7", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_IMUX32_12", - "CMT_TOP_WW4C0_3", - "CMT_TOP_BYP7_10", - "CMT_TOP_IMUX6_9", - "CMT_TOP_WW4A0_1", - "CMT_TOP_EE4B1_11", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_FAN5_13", - "CMT_TOP_IMUX38_13", - "CMT_TOP_WW4C2_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_NW4A0_10", - "CMT_TOP_EE4B2_12", - "CMT_TOP_WW4END0_11", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NE4C3_4", - "CMT_TOP_WW2A1_14", - "CMT_TOP_BYP6_9", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_IMUX44_9", - "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "CMT_TOP_IMUX29_10", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW2A0_2", - "CMT_TOP_BYP2_8", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW4C0_0", - "CMT_TOP_BYP6_8", - "CMT_LR_LOWER_B_MMCM_DI11", - "CMT_TOP_IMUX28_0", - "CMT_TOP_SE4BEG3_15", - "CMT_TOP_NW2A1_14", - "CMT_TOP_LOGIC_OUTS_L_B21_14", - "CMT_TOP_EE4A2_0", - "CMT_TOP_NE4BEG1_13", - "CMT_TOP_BYP2_12", - "CMT_TOP_SW2A2_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_LH5_13", - "CMT_TOP_LH12_10", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_LOGIC_OUTS_L_B13_13", - "CMT_TOP_SW2A3_5", - "CMT_TOP_IMUX39_14", - "CMT_TOP_SW4END1_10", - "CMT_TOP_NW4END0_5", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_IMUX3_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_IMUX2_15", - "CMT_TOP_SW4END3_8", - "CMT_TOP_NW4END0_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT8", - "CMT_TOP_NW4END3_6", - "CMT_TOP_IMUX14_4", - "CMT_TOP_LH6_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SE2A2_9", - "CMT_TOP_FAN6_14", - "CMT_TOP_SW4A2_0", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_NW4A2_15", - "CMT_TOP_WL1END3_2", - "CMT_PHASER_A_OCLK90_TOIOI", - "CMT_TOP_WW2A1_10", - "CMT_TOP_SW4A2_7", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_WW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_FAN4_0", - "CMT_TOP_IMUX0_11", - "CMT_TOP_SE2A1_13", - "CMT_TOP_IMUX41_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_WW4C2_13", - "CMT_TOP_WW4A3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_LH6_1", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WL1END2_9", - "CMT_TOP_BYP4_10", - "CMT_TOP_IMUX11_4", - "CMT_TOP_WL1END3_10", - "CMT_TOP_IMUX47_12", - "CMT_TOP_NE4C3_0", - "CMT_TOP_WW4END1_0", - "CMT_TOP_FAN7_5", - "CMT_TOP_OCLK_12", - "CMT_TOP_SE4C0_9", - "CMT_TOP_BYP0_8", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_IMUX22_2", - "CMT_TOP_FAN4_5", - "CMT_TOP_NE4C1_13", - "CMT_LR_LOWER_B_MMCM_DWE", - "CMT_TOP_NE2A1_12", - "CMT_TOP_EE4B2_6", - "CMT_TOP_SW4A1_3", - "CMT_TOP_WW4END2_0", - "CMT_TOP_FAN5_15", - "CMT_TOP_WW2A2_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_IMUX19_3", - "CMT_TOP_SW4END1_12", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_WW4A3_13", - "CMT_TOP_SE4C1_12", - "CMT_TOP_IMUX0_13", - "CMT_TOP_EE4A1_8", - "CMT_TOP_WW4B1_2", - "CMT_LR_LOWER_B_MMCM_DO4", - "CMT_TOP_IMUX9_9", - "CMT_TOP_IMUX1_13", - "CMT_TOP_NW4END3_14", - "CMT_TOP_IMUX42_15", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_SW2A0_12", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LH9_9", - "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_SE4BEG3_13", - "CMT_TOP_NE4C1_12", - "CMT_TOP_WW2A2_14", - "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_WW4B3_9", - "CMT_TOP_NE4C3_10", - "CMT_TOP_WW2A0_14", - "CMT_TOP_FAN5_6", - "CMT_LR_LOWER_B_MMCM_DADDR3", - "CMT_TOP_IMUX30_6", - "CMT_TOP_BYP3_12", - "CMT_TOP_IMUX23_5", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_IMUX1_15", - "CMT_TOP_FAN0_10", - "CMT_TOP_IMUX40_10", - "CMT_TOP_IMUX38_14", - "CMT_TOP_LH2_3", - "CMT_TOP_IMUX5_14", - "CMT_TOP_MONITOR_N_14", - "CMT_TOP_EE4A0_13", - "CMT_TOP_EE4C3_8", - "CMT_MMCM_PHASERA_DQSBUS1", - "CMT_TOP_SW4END2_3", - "CMT_TOP_WW4B2_12", - "CMT_TOP_NE4C0_13", - "CMT_TOP_IMUX46_12", - "CMT_LR_LOWER_B_MMCM_DI3", - "CMT_TOP_EE2A0_9", - "CMT_TOP_WW4A1_3", - "CMT_TOP_BYP5_10", - "CMT_TOP_SW2A0_13", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4B0_13", - "CMT_TOP_WR1END0_4", - "CMT_TOP_IMUX42_13", - "CMT_TOP_NW2A0_2", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_SE4C3_0", - "CMT_TOP_LH5_15", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_BLOCK_OUTS_L_B0_15", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_SE2A1_5", - "CMT_TOP_FAN0_11", - "CMT_TOP_LH11_13", - "CMT_TOP_WL1END3_11", - "CMT_TOP_FAN6_5", - "CMT_TOP_EE4A2_4", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_WR1END0_7", - "CMT_TOP_EE4A3_7", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A3_9", - "CMT_TOP_ICLK_14", - "CMT_TOP_NE2A1_4", - "CMT_TOP_WR1END1_0", - "CMT_TOP_LOGIC_OUTS_L_B22_13", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_LR_LOWER_B_MMCM_CLKIN1", - "CMT_TOP_EE4BEG2_12", - "CMT_TOP_EE4A2_15", - "CMT_TOP_IMUX32_15", - "CMT_TOP_LOGIC_OUTS_L_B21_13", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_EL1BEG1_14", - "CMT_TOP_IMUX32_1", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4BEG1_14", - "CMT_TOP_BYP6_13", - "CMT_TOP_EE4C1_1", - "CMT_TOP_FAN5_14", - "CMT_TOP_WW2END3_12", - "CMT_TOP_IMUX20_2", - "CMT_TOP_LH8_14", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_NW4END1_11", - "CMT_TOP_FAN0_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_WW2END1_11", - "CMT_TOP_FAN0_9", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NW4A0_0", - "CMT_TOP_SW4A3_15", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_EE4C1_12", - "CMT_TOP_BYP1_8", - "CMT_TOP_IMUX28_15", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EE4B2_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_EE4B3_2", - "CMT_TOP_SE4C1_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_IMUX25_12", - "CMT_TOP_IMUX36_3", - "CMT_TOP_SE4C2_3", - "CMT_TOP_NW4END0_3", - "CMT_TOP_FAN4_9", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX27_8", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_WL1END3_13", - "CMT_TOP_ICLKDIV_15", - "CMT_TOP_WW4B1_4", - "CMT_MMCM_PHASERA_CTSBUS0", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_EE4A3_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_BYP3_6", - "CMT_MMCM_PHASERA_DTSBUS1", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A2_12", - "CMT_TOP_EE2A3_14", - "CMT_TOP_WW4B1_3", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_BYP2_10", - "CMT_TOP_IMUX27_11", - "CMT_TOP_IMUX33_15", - "CMT_TOP_SE2A2_3", - "CMT_TOP_NE2A1_15", - "CMT_TOP_FAN7_4", - "CMT_TOP_SE4C3_6", - "CMT_TOP_NE4C3_3", - "CMT_TOP_WR1END2_9", - "CMT_TOP_CTRL0_6", - "CMT_TOP_FAN2_2", - "CMT_TOP_NW4END1_2", - "CMT_TOP_IMUX18_7", - "CMT_TOP_WL1END2_14", - "CMT_TOP_OCLK_10", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LH2_11", - "CMT_TOP_IMUX40_15", - "CMT_TOP_BLOCK_OUTS_L_B1_13", - "CMT_TOP_NW4A1_0", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_NW4END2_15", - "CMT_TOP_FAN6_13", - "CMT_TOP_IMUX35_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4END3_3", - "CMT_TOP_BYP7_9", - "CMT_TOP_SW4END1_6", - "CMT_LR_LOWER_B_MMCM_DI8", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_IMUX7_15", - "CMT_TOP_EE2A0_15", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4C0_8", - "CMT_TOP_SE4C0_1", - "CMT_TOP_EE2A0_1", - "CMT_TOP_NW2A1_8", - "CMT_TOP_BLOCK_OUTS_L_B2_15", - "CMT_TOP_SW4END0_15", - "CMT_TOP_LH9_4", - "CMT_TOP_SW4END1_1", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_IMUX37_15", - "CMT_LR_LOWER_B_MMCM_DO6", - "CMT_TOP_LH10_8", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WW2END3_3", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_FAN1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_SE4C1_2", - "CMT_TOP_NW2A2_6", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX46_8", - "CMT_TOP_EE4B1_7", - "CMT_LR_LOWER_B_MMCM_TESTIN17", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_EE4B0_5", - "CMT_TOP_MONITOR_N_15", - "CMT_TOP_NE4C0_14", - "CMT_TOP_NW2A0_3", - "CMT_TOP_WW2A3_15", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_SE4BEG0_14", - "CMT_TOP_WW4B2_7", - "CMT_TOP_LH10_11", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_IMUX6_2", - "CMT_TOP_NE4C2_6", - "CMT_TOP_WW4END2_9", - "CMT_TOP_IMUX13_10", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_LR_LOWER_B_MMCM_TESTOUT1", - "CMT_TOP_WW2END3_11", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_LH9_13", - "CMT_TOP_LH8_8", - "CMT_TOP_LOGIC_OUTS_L_B20_15", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW4A2_2", - "MMCM_CLK_FREQ_BB_REBUF0_NS", - "CMT_TOP_WW2A1_6", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_IMUX36_14", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_ICLK_15", - "CMT_TOP_SW2A0_11", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_IMUX3_8", - "CMT_TOP_BYP3_15", - "CMT_TOP_NW4END2_13", - "CMT_R_LOWER_B_CLK_MMCM0", - "CMT_TOP_FAN6_9", - "CMT_TOP_SE4C1_3", - "CMT_TOP_WL1END2_6", - "CMT_TOP_LH11_2", - "CMT_TOP_WW4C0_9", - "CMT_TOP_LH3_14", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_IMUX3_13", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_IMUX12_1", - "CMT_TOP_SE2A0_1", - "CMT_TOP_IMUX46_11", - "CMT_TOP_WW4A1_13", - "CMT_TOP_IMUX37_4", - "CMT_TOP_EE4C3_10", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B9_13", - "CMT_TOP_LOGIC_OUTS_L_B4_13", - "CMT_TOP_EL1BEG0_13", - "CMT_TOP_NE2A0_14", - "CMT_TOP_NE4C1_3", - "CMT_TOP_IMUX11_15", - "CMT_TOP_FAN5_4", - "CMT_TOP_SE4BEG0_13", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_NW4END3_12", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX0_4", - "CMT_TOP_NW4A3_12", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_LH1_12", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_IMUX27_13", - "CMT_TOP_ER1BEG2_6", - "CMT_R_LOWER_B_CLK_MMCM8", - "CMT_TOP_IMUX40_9", - "CMT_TOP_NW4A3_13", - "CMT_TOP_SW2A1_7", - "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "CMT_TOP_WL1END1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_WL1END1_9", - "CMT_TOP_WW4B1_15", - "CMT_TOP_WW4C1_15", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_SE2A2_5", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_SW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LH2_4", - "CMT_TOP_WW4A0_14", - "CMT_TOP_WW2END3_14", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_WW4END0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_ER1BEG3_13", - "CMT_TOP_SE2A3_9", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX7_10", - "CMT_TOP_WW4A1_8", - "CMT_TOP_ICLKDIV_14", - "CMT_TOP_WW4END3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_15", - "CMT_TOP_SE2A3_10", - "CMT_TOP_WW2A3_7", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_WW4B0_1", - "CMT_TOP_IMUX15_13", - "CMT_TOP_WW4END2_6", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_NE2A1_11", - "CMT_R_LOWER_B_CLK_MMCM6", - "CMT_TOP_LOGIC_OUTS_L_B7_13", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_NW2A0_11", - "CMT_TOP_IMUX42_2", - "CMT_TOP_LH8_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_EE4A0_5", - "CMT_TOP_WW4A3_14", - "CMT_TOP_WL1END2_3", - "CMT_TOP_SE2A1_8", - "CMT_TOP_FAN4_14", - "CMT_TOP_NE4C1_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_NW2A0_6", - "CMT_TOP_WW4A3_8", - "CMT_TOP_SW2A1_3", - "CMT_TOP_IMUX40_5", - "CMT_TOP_SE2A1_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_CTRL1_5", - "CMT_TOP_SE4C3_1", - "CMT_TOP_IMUX13_4", - "CMT_TOP_EE2A1_1", - "CMT_TOP_IMUX18_3", - "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", - "CMT_TOP_EL1BEG2_14", - "CMT_LR_LOWER_B_MMCM_TESTIN1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_IMUX16_5", - "CMT_TOP_LH9_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_LOGIC_OUTS_L_B3_15", - "CMT_TOP_EE2A1_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_WL1END3_7", - "CMT_MMCM_PHASERA_DQSBUS0", - "CMT_TOP_EE4A3_12", - "CMT_TOP_BYP5_8", - "CMT_TOP_IMUX47_3", - "CMT_TOP_NE2A2_7", - "CMT_TOP_WW4B1_5", - "CMT_TOP_SE4C3_9", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END3_12", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_EE2A2_0", - "CMT_TOP_IMUX4_12", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_LH9_7", - "CMT_TOP_NE2A0_15", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW2END3_5", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CLK1_9", - "CMT_TOP_EE4A2_14", - "CMT_TOP_WW2A0_13", - "CMT_TOP_IMUX5_11", - "CMT_TOP_WR1END2_6", - "CMT_TOP_CTRL1_2", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_NW2A1_12", - "CMT_TOP_IMUX10_11", - "CMT_TOP_LH6_6", - "CMT_TOP_WW4C0_13", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_SE2A3_12", - "CMT_TOP_EE2A3_1", - "CMT_TOP_IMUX2_0", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_IMUX28_12", - "CMT_TOP_EE4B3_5", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX38_2", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_NE2A0_12", - "CMT_TOP_FAN4_10", - "CMT_TOP_CLK0_5", - "CMT_TOP_SW4A3_0", - "CMT_TOP_IMUX18_13", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_OCLK_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "CMT_TOP_LH12_6", - "CMT_TOP_IMUX4_6", - "CMT_LR_LOWER_B_MMCM_TESTIN21", - "CMT_TOP_WR1END2_3", - "CMT_TOP_EE4BEG1_10", - "CMT_R_LOWER_B_CLK_FREQ_BB1", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_WR1END1_14", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX4_11", - "CMT_TOP_NW2A2_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_SE4C1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_14", - "CMT_TOP_WW4C0_4", - "CMT_TOP_IMUX6_8", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_WW4A2_4", - "CMT_TOP_IMUX7_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_SE4C2_15", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SW4A3_9", - "CMT_TOP_IMUX20_7", - "CMT_TOP_FAN0_13", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_IMUX35_7", - "CMT_TOP_EE4A3_5", - "CMT_TOP_LH6_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_NE4BEG3_15", - "CMT_TOP_ICLK_8", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_IMUX44_12", - "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "CMT_TOP_NW2A3_9", - "CMT_TOP_LOGIC_OUTS_L_B8_15", - "CMT_TOP_CLK0_8", - "CMT_TOP_IMUX7_2", - "CMT_TOP_SE2A2_11", - "CMT_TOP_FAN4_2", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BYP5_13", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX2_6", - "CMT_R_LOWER_B_CLK_MMCM9", - "CMT_TOP_LH12_3", - "CMT_TOP_WW2A1_8", - "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "CMT_TOP_NE4C2_12", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LH9_14", - "CMT_TOP_NE4BEG1_14", - "CMT_TOP_LH8_2", - "CMT_MMCM_PHYCTRL_SYNC_BB_DN", - "CMT_TOP_EE2BEG3_7", - "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_IMUX23_7", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_SE4C0_14", - "CMT_TOP_IMUX39_0", - "CMT_TOP_NE2A2_14", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX33_8", - "CMT_TOP_SW2A2_2", - "CMT_TOP_LH10_0", - "CMT_TOP_IMUX46_15", - "CMT_TOP_LH6_3", - "CMT_TOP_EE2A0_0", - "CMT_TOP_IMUX12_0", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_NW4A1_1", - "CMT_TOP_SE4BEG3_14", - "CMT_TOP_IMUX21_8", - "CMT_TOP_LH2_14", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX10_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE2A2_14", - "CMT_TOP_FAN2_10", - "CMT_TOP_NE4BEG2_15", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_LH9_12", - "CMT_TOP_IMUX5_12", - "CMT_TOP_LH12_11", - "CMT_TOP_IMUX36_10", - "CMT_TOP_LH4_1", - "CMT_TOP_SE4C3_12", - "CMT_TOP_NE4C2_11", - "CMT_TOP_IMUX3_3", - "CMT_TOP_CTRL0_15", - "CMT_TOP_BYP1_1", - "CMT_TOP_LOGIC_OUTS_L_B0_13", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_SW4END1_5", - "CMT_TOP_FAN7_0", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW4END2_14", - "CMT_TOP_LH1_7", - "CMT_TOP_IMUX35_12", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_WW4A0_4", - "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "CMT_TOP_NW4A2_14", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW2A1_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_FAN0_15", - "CMT_TOP_WW4C2_0", - "CMT_TOP_SE2A3_3", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_WL1END2_4", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_IMUX9_0", - "CMT_TOP_NW4A0_12", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LH5_0", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_WW2END0_13", - "CMT_TOP_IMUX9_13", - "CMT_TOP_IMUX22_5", - "CMT_TOP_FAN2_15", - "CMT_TOP_WW4END0_15", - "CMT_TOP_NE2A3_12", - "CMT_TOP_SW4END3_13", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE2A2_12", - "CMT_TOP_EL1BEG2_13", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_IMUX11_1", - "CMT_TOP_EE4B0_15", - "CMT_TOP_NE2A3_8", - "CMT_TOP_BLOCK_OUTS_L_B1_15", - "CMT_TOP_EE2A3_0", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_BLOCK_OUTS_L_B0_14", - "CMT_TOP_WL1END0_15", - "CMT_TOP_LH4_6", - "CMT_TOP_WW4A3_9", - "CMT_TOP_FAN7_7", - "CMT_TOP_SE2A1_4", - "CMT_TOP_CTRL0_13", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "MMCMOUT_CLK_FREQ_BB_3", - "CMT_TOP_SE4C0_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_LH5_3", - "CMT_TOP_BYP0_13", - "CMT_TOP_SW2A3_10", - "CMT_TOP_OCLK1X_90_14", - "CMT_TOP_WW4END2_11", - "CMT_TOP_IMUX26_14", - "CMT_TOP_NE4BEG1_15", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_IMUX25_1", - "CMT_R_LOWER_B_CLK_FREQ_BB2", - "CMT_TOP_ICLK_9", - "CMT_LR_LOWER_B_MMCM_LOCKED", - "CMT_TOP_IMUX14_13", - "CMT_TOP_IMUX31_8", - "CMT_TOP_WL1END0_13", - "CMT_TOP_LH3_2", - "CMT_TOP_IMUX25_15", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4END2_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_CLK1_13", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_BYP4_13", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_BYP1_7", - "CMT_TOP_LH3_10", - "CMT_TOP_WL1END2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_WL1END3_5", - "CMT_TOP_ICLK_3", - "CMT_TOP_IMUX0_5", - "CMT_TOP_SW4A0_8", - "CMT_TOP_FAN7_6", - "CMT_TOP_IMUX4_0", - "CMT_TOP_BYP1_10", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX20_12", - "CMT_TOP_SW4A2_15", - "CMT_LR_LOWER_B_MMCM_DI14", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_IMUX19_4", - "CMT_TOP_WW4B1_8", - "CMT_TOP_LH4_0", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_EE4A2_10", - "CMT_LR_LOWER_B_MMCM_DADDR0", - "CMT_TOP_IMUX44_7", - "CMT_TOP_EE4B2_4", - "CMT_TOP_BYP7_14", - "CMT_TOP_LH10_13", - "CMT_TOP_NW2A2_15", - "CMT_TOP_EE4C3_7", - "CMT_TOP_WL1END1_5", - "CMT_TOP_IMUX42_9", - "CMT_TOP_CTRL0_12", - "CMT_TOP_IMUX3_2", - "CMT_TOP_SE4C0_2", - "CMT_TOP_EE4A3_13", - "CMT_R_LOWER_B_CLK_MMCM11", - "CMT_TOP_WW2A1_12", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4C3_13", - "CMT_TOP_SW4END0_12", - "CMT_TOP_NE4C3_13", - "CMT_TOP_LH7_2", - "CMT_TOP_WW4A1_4", - "CMT_TOP_IMUX11_14", - "CMT_TOP_WW4END0_13", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_CLK0_3", - "CMT_TOP_IMUX44_8", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_WW2A3_12", - "CMT_TOP_SE4C2_0", - "CMT_TOP_EE2A2_12", - "CMT_TOP_IMUX23_2", - "CMT_TOP_WW4END3_7", - "CMT_TOP_IMUX14_15", - "CMT_TOP_IMUX34_15", - "CMT_TOP_SW2A2_8", - "CMT_TOP_NW4A0_8", - "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", - "CMT_PHASER_A_ICLK_TOIOI", - "CMT_TOP_WW4END3_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX21_2", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_FAN6_10", - "CMT_TOP_LH11_6", - "CMT_TOP_LOGIC_OUTS_L_B22_14", - "CMT_TOP_CLK1_10", - "CMT_TOP_SE2A3_14", - "CMT_TOP_IMUX45_12", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_SW2A3_2", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX24_15", - "CMT_TOP_WW2A0_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_FAN7_15", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_IMUX33_10", - "CMT_TOP_IMUX37_14", - "CMT_TOP_EE4B3_10", - "CMT_TOP_WW4C1_7", - "CMT_TOP_IMUX24_5", - "CMT_TOP_WW4C2_8", - "CMT_TOP_EE2A3_8", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "CMT_TOP_NW4END0_6", - "CMT_TOP_SE2A3_0", - "CMT_TOP_EE4C0_10", - "CMT_TOP_IMUX43_10", - "CMT_TOP_NW2A3_6", - "CMT_TOP_IMUX33_14", - "CMT_TOP_NE2A3_0", - "CMT_TOP_LH12_5", - "CMT_TOP_WW2END1_12", - "CMT_TOP_IMUX35_6", - "CMT_TOP_EE4C2_3", - "CMT_TOP_WW2END0_10", - "CMT_TOP_FAN2_7", - "CMT_TOP_WW4A3_0", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_IMUX31_2", - "CMT_TOP_FAN3_7", - "CMT_TOP_IMUX3_4", - "CMT_TOP_SW4END2_15", - "CMT_TOP_LOGIC_OUTS_L_B5_13", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX12_14", - "CMT_TOP_EE4A1_1", - "CMT_TOP_LOGIC_OUTS_L_B14_14", - "CMT_TOP_SW4A0_5", - "CMT_TOP_EE2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_EE4B1_6", - "CMT_LR_LOWER_B_MMCM_TESTIN7", - "CMT_TOP_NE2A1_13", - "CMT_TOP_WR1END1_10", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2A0_6", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX47_6", - "CMT_TOP_SW4A2_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_CTRL1_6", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_13", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_OCLKDIV_14", - "CMT_R_LOWER_B_CLK_IN3_INT", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NW4END1_1", - "CMT_TOP_CLK1_5", - "CMT_TOP_WW4C1_0", - "CMT_TOP_EE4B3_3", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_WW4B2_2", - "CMT_TOP_NW4END1_7", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX10_10", - "CMT_TOP_SE4BEG1_14", - "CMT_TOP_WW4B3_6", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_WW2A2_13", - "CMT_LR_LOWER_B_MMCM_DI7", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_WW4A3_5", - "CMT_TOP_LH1_0", - "CMT_TOP_WW4B1_10", - "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_OCLK1X_90_7", - "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LH10_5", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_IMUX15_0", - "CMT_TOP_EE4A1_5", - "CMT_TOP_IMUX41_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "CMT_TOP_NW2A3_12", - "CMT_TOP_EE4C2_9", - "CMT_TOP_SE2A3_1", - "CMT_TOP_BYP0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_IMUX19_13", - "CMT_TOP_LH2_13", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_WR1END0_11", - "CMT_TOP_BLOCK_OUTS_L_B0_13", - "CMT_TOP_IMUX36_13", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX8_5", - "CMT_TOP_WW4C2_9", - "CMT_TOP_CLK1_6", - "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "CMT_TOP_FAN6_11", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX27_12", - "CMT_TOP_NW4END3_9", - "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "CMT_TOP_WR1END3_13", - "CMT_TOP_LOGIC_OUTS_L_B6_15", - "CMT_TOP_WW4A2_3", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX17_3", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B0_14", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LH1_8", - "CMT_TOP_LH11_1", - "CMT_TOP_IMUX3_5", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_EE4BEG3_15", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_FAN4_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_SE4C1_6", - "CMT_TOP_WR1END3_10", - "CMT_LR_LOWER_B_MMCM_CLKOUT0B", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_IMUX15_9", - "CMT_TOP_BYP0_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_LH2_10", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_SE4C1_11", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_IMUX12_13", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SW4A3_2", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_LH8_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_LH5_11", - "CMT_TOP_FAN4_4", - "CMT_TOP_WW4C3_0", - "CMT_TOP_SE4C3_15", - "CMT_TOP_EE4C2_10", - "CMT_TOP_CTRL0_14", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_CLK0_13", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_SW2A1_11", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX35_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NW2A0_13", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_IMUX38_9", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_SE4C2_1", - "CMT_TOP_CTRL0_1", - "CMT_TOP_IMUX2_4", - "CMT_TOP_EE2A0_12", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX16_2", - "CMT_TOP_SW4A1_4", - "CMT_TOP_WW2A3_14", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_NE4C1_11", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_SW2A1_13", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_FAN7_13", - "CMT_TOP_NE2A1_10", - "CMT_TOP_SW4END2_14", - "CMT_TOP_FAN3_11", - "CMT_TOP_EE4C0_14", - "CMT_TOP_IMUX17_5", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_CLK1_12", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_WW4A0_15", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_SW4END1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BYP1_4", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_EE2BEG1_13", - "CMT_TOP_IMUX32_4", - "CMT_TOP_IMUX7_0", - "CMT_TOP_NW4END0_9", - "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX26_4", - "CMT_TOP_SE4C2_14", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_BYP4_3", - "CMT_TOP_WL1END2_10", - "CMT_TOP_FAN5_2", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4C0_9", - "CMT_TOP_IMUX29_3", - "CMT_TOP_EE4C1_7", - "CMT_LR_LOWER_B_MMCM_TESTIN13", - "CMT_TOP_WL1END3_15", - "CMT_TOP_IMUX29_2", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4A2_1", - "CMT_TOP_EE4BEG2_14", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SW4END3_12", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_NW2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_EE4B0_3", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_SW4END2_11", - "CMT_TOP_WW4B2_8", - "CMT_TOP_IMUX47_13", - "CMT_TOP_SW4A2_9", - "CMT_TOP_NW4A2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4END0_9", - "CMT_TOP_ER1BEG2_5", - "CMT_R_LOWER_B_CLK_IN2_INT", - "CMT_TOP_NE2A3_7", - "CMT_TOP_FAN5_1", - "CMT_TOP_LOGIC_OUTS_L_B8_14", - "CMT_TOP_IMUX21_11", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_FAN1_11", - "CMT_TOP_IMUX32_6", - "CMT_TOP_SW4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_IMUX8_10", - "CMT_LR_LOWER_B_MMCM_TESTOUT51", - "CMT_TOP_WW4A2_12", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX24_10", - "CMT_TOP_LH3_7", - "CMT_TOP_WR1END1_7", - "CMT_TOP_NW2A0_5", - "CMT_TOP_EE4B0_11", - "CMT_TOP_BYP3_1", - "CMT_TOP_EL1BEG3_13", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_EE4B1_15", - "CMT_TOP_LH9_2", - "CMT_TOP_WW2A2_4", - "CMT_TOP_SW2A1_14", - "CMT_TOP_IMUX41_9", - "CMT_TOP_BYP5_9", - "CMT_TOP_IMUX40_6", - "CMT_R_LOWER_B_CLK_IN2_HCLK", - "CMT_TOP_WL1END3_3", - "CMT_TOP_NW4A3_0", - "CMT_TOP_LH9_8", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX15_15", - "MMCMOUT_CLK_FREQ_BB_2", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_WW4A0_5", - "CMT_TOP_SW2A2_15", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_IMUX12_7", - "CMT_TOP_SW4A0_7", - "CMT_TOP_NW4A0_15", - "CMT_TOP_EE4A0_4", - "CMT_TOP_IMUX7_11", - "CMT_TOP_EE4B3_7", - "CMT_TOP_IMUX4_7", - "CMT_TOP_LOGIC_OUTS_L_B10_13", - "CMT_LR_LOWER_B_MMCM_TESTIN11", - "CMT_TOP_EE4C2_0", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4END1_12", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_SE4C0_0", - "CMT_TOP_WW4A1_0", - "CMT_TOP_LH1_2", - "CMT_TOP_SW4END0_8", - "CMT_TOP_FAN3_5", - "CMT_TOP_MONITOR_P_13", - "CMT_LR_LOWER_B_MMCM_TESTOUT52", - "CMT_TOP_SE2A1_6", - "CMT_TOP_IMUX20_15", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE2A1_14", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_EE4BEG0_8", - "CMT_LR_LOWER_B_MMCM_DO14", - "CMT_TOP_LH11_5", - "CMT_LR_LOWER_B_MMCM_TESTIN15", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_WR1END0_2", - "CMT_TOP_IMUX30_5", - "CMT_TOP_LOGIC_OUTS_L_B16_15", - "CMT_TOP_WW2END1_15", - "CMT_TOP_NW4A3_3", - "CMT_TOP_FAN4_15", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_WW4B3_8", - "CMT_LR_LOWER_B_MMCM_CLKINSEL", - "CMT_TOP_WW2END2_8", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX38_7", - "CMT_TOP_NW2A1_3", - "CMT_TOP_EE4A2_5", - "CMT_TOP_NE2A2_0", - "CMT_TOP_WW4C1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_WW4B2_11", - "CMT_TOP_LOGIC_OUTS_L_B13_14", - "CMT_TOP_CLK0_7", - "CMT_TOP_EE2A1_3", - "CMT_TOP_SW4END1_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_FAN7_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LH11_3", - "CMT_TOP_IMUX13_3", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_LH10_10", - "CMT_TOP_SW4A1_10", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NE4C0_6", - "CMT_TOP_BYP0_3", - "CMT_TOP_SE4C2_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_IMUX5_7", - "CMT_TOP_LH10_4", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX8_4", - "CMT_TOP_WL1END0_9", - "CMT_TOP_EE4C0_15", - "CMT_TOP_SW2A1_6", - "CMT_TOP_IMUX26_3", - "CMT_TOP_NW2A2_0", - "CMT_TOP_WW4END0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_SW4A0_12", - "CMT_TOP_EE4C1_14", - "CMT_TOP_IMUX14_14", - "CMT_TOP_SE4C1_14", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WR1END2_2", - "CMT_TOP_SE4C2_12", - "CMT_TOP_IMUX37_13", - "CMT_TOP_LH7_13", - "CMT_TOP_WW4C1_1", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_WW2A1_5", - "CMT_TOP_CTRL1_1", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_LR_LOWER_B_MMCM_TESTIN3", - "CMT_TOP_BYP7_3", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END2_13", - "CMT_TOP_IMUX45_0", - "CMT_TOP_WL1END1_7", - "CMT_TOP_LH2_7", - "CMT_TOP_WW4B0_15", - "CMT_TOP_WW4END1_2", - "CMT_TOP_LH7_7", - "CMT_TOP_IMUX26_8", - "CMT_LR_LOWER_B_MMCM_TESTIN9", - "CMT_TOP_BYP4_12", - "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "MMCMOUT_CLK_FREQ_BB_0", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_SE4C2_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_EE4A2_11", - "CMT_TOP_NW4END1_4", - "CMT_TOP_IMUX25_11", - "CMT_TOP_SW2A3_15", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_IMUX35_13", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_NW2A1_6", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_BYP2_4", - "CMT_TOP_NW4END2_3", - "CMT_TOP_WL1END0_11", - "CMT_TOP_EE4C2_15", - "CMT_TOP_IMUX18_10", - "CMT_LR_LOWER_B_MMCM_DO0", - "CMT_TOP_EE4C1_8", - "CMT_TOP_BYP2_14", - "CMT_TOP_WW2END1_4", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_SE2A2_15", - "CMT_TOP_WW2END3_9", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_NW4A0_13", - "CMT_TOP_EE4C2_4", - "CMT_LR_LOWER_B_MMCM_TESTIN25", - "CMT_TOP_WR1END2_15", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_IMUX1_9", - "CMT_LR_LOWER_B_MMCM_TESTIN29", - "CMT_TOP_NW4A1_4", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_SW2A0_3", - "CMT_TOP_IMUX22_6", - "CMT_TOP_EE4C2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_14", - "CMT_TOP_IMUX5_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_EE4C3_1", - "CMT_TOP_NE2A2_4", - "CMT_TOP_LH9_6", - "CMT_TOP_IMUX28_5", - "CMT_TOP_EE2A2_9", - "CMT_TOP_LH6_15", - "CMT_TOP_IMUX3_15", - "CMT_TOP_LOGIC_OUTS_L_B12_13", - "CMT_TOP_NW4A3_4", - "CMT_TOP_SW2A2_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LH2_9", - "CMT_TOP_WW2A2_2", - "CMT_TOP_IMUX3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_LR_LOWER_B_MMCM_PSEN", - "CMT_TOP_NW4A3_14", - "CMT_TOP_EE2A1_13", - "CMT_TOP_ER1BEG0_14", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_NW4END0_15", - "CMT_TOP_IMUX10_14", - "CMT_TOP_IMUX45_11", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX45_5", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_NW4END1_12", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_WW4C3_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX24_6", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_IMUX35_5", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_EE2A0_7", - "CMT_TOP_WW4B2_4", - "CMT_TOP_FAN2_8", - "CMT_R_LOWER_B_CLK_MMCM1", - "CMT_TOP_EE4BEG2_15", - "CMT_TOP_EE4B0_14", - "CMT_TOP_SW2A1_0", - "CMT_TOP_WW2END2_15", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_IMUX30_13", - "CMT_TOP_WL1END0_5", - "CMT_LR_LOWER_B_MMCM_TESTIN4", - "CMT_TOP_CLK0_9", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX29_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT57", - "CMT_TOP_NE2A0_11", - "CMT_TOP_FAN2_3", - "CMT_TOP_NE4C2_1", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_IMUX31_5", - "CMT_TOP_WR1END1_5", - "CMT_TOP_CTRL1_7", - "CMT_TOP_IMUX8_7", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_IMUX27_9", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4C3_8", - "CMT_TOP_BYP6_6", - "CMT_TOP_IMUX34_13", - "CMT_TOP_SW2A2_14", - "CMT_TOP_EE4C1_4", - "CMT_TOP_IMUX46_6", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4END0_7", - "CMT_TOP_SW4A1_12", - "CMT_TOP_CLK1_11", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_BYP3_8", - "CMT_TOP_WW4END2_12", - "CMT_TOP_IMUX16_8", - "CMT_TOP_SW4END3_7", - "CMT_TOP_WW2A1_4", - "CMT_TOP_EE4B3_13", - "CMT_TOP_SW4END3_15", - "CMT_TOP_LH2_12", - "CMT_TOP_WW2END3_0", - "CMT_TOP_SE2A0_5", - "CMT_TOP_WW2A1_0", - "CMT_TOP_NW4A2_5", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_LH7_15", - "CMT_TOP_WW4END2_1", - "CMT_TOP_NW2A2_5", - "CMT_TOP_IMUX43_14", - "CMT_TOP_WW4B2_13", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_IMUX18_9", - "CMT_TOP_SE2A0_4", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_IMUX6_5", - "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_EE4A2_8", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX5_13", - "CMT_TOP_CTRL0_9", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_WR1END1_13", - "CMT_TOP_IMUX6_11", - "CMT_TOP_LH5_12", - "CMT_TOP_BYP6_15", - "CMT_TOP_WW4B3_2", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_EE4C0_4", - "CMT_TOP_BYP2_1", - "CMT_TOP_IMUX36_8", - "CMT_TOP_EL1BEG3_0", - "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "CMT_TOP_NW2A3_5", - "CMT_TOP_IMUX7_13", - "CMT_TOP_IMUX8_13", - "CMT_TOP_IMUX27_3", - "CMT_TOP_BYP0_15", - "CMT_TOP_LH7_11", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_WW4C2_2", - "CMT_LR_LOWER_B_MMCM_DO11", - "CMT_TOP_BYP1_6", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_EE4C2_14", - "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "CMT_TOP_WW2A1_15", - "CMT_TOP_SE2A0_10", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_NW4END0_10", - "CMT_TOP_EE2A3_13", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_IMUX8_8", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX2_9", - "CMT_TOP_SE2A2_1", - "CMT_TOP_EE4BEG2_6", - "CMT_LR_LOWER_B_MMCM_TESTIN12", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_ICLKDIV_7", - "CMT_R_LOWER_B_CLK_FREQ_BB0", - "CMT_R_LOWER_B_CLK_PERF2", - "CMT_TOP_NE4C2_10", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_IMUX13_0", - "CMT_TOP_EE4A2_9", - "CMT_TOP_IMUX3_9", - "CMT_TOP_WW2A3_2", - "CMT_TOP_EL1BEG0_15", - "CMT_TOP_BYP5_0", - "CMT_TOP_NE4C2_8", - "CMT_TOP_BLOCK_OUTS_L_B1_12", - "CMT_TOP_IMUX40_3", - "CMT_LR_LOWER_B_MMCM_TESTIN5", - "CMT_TOP_IMUX17_9", - "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_IMUX0_8", - "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "CMT_TOP_LOGIC_OUTS_L_B16_13", - "CMT_TOP_NE4C3_5", - "CMT_TOP_WR1END3_9", - "CMT_TOP_EE4C3_9", - "CMT_TOP_IMUX35_8", - "CMT_TOP_EE4BEG2_13", - "CMT_TOP_BYP3_5", - "CMT_TOP_IMUX32_8", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_IMUX10_15", - "CMT_TOP_EE2BEG2_14", - "CMT_LR_LOWER_B_MMCM_TESTIN16", - "CMT_TOP_WW2END0_12", - "CMT_TOP_NE4BEG3_13", - "CMT_TOP_NW4A0_11", - "CMT_TOP_IMUX34_9", - "CMT_TOP_SE4C3_5", - "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "CMT_TOP_IMUX25_4", - "CMT_TOP_WW4B0_14", - "CMT_TOP_IMUX47_11", - "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_NE4BEG2_11", - "MMCM_CLK_FREQ_BB_REBUF1_NS", - "CMT_TOP_FAN6_4", - "CMT_TOP_IMUX21_7", - "CMT_TOP_WW2END0_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_EL1BEG1_13", - "CMT_TOP_LH5_2", - "CMT_TOP_IMUX17_4", - "CMT_TOP_SW2A1_8", - "CMT_TOP_LOGIC_OUTS_L_B9_14", - "CMT_TOP_LOGIC_OUTS_L_B2_15", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_NE4C1_9", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_LH3_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_WW2END0_4", - "CMT_TOP_EE2A1_7", - "CMT_TOP_NW2A2_11", - "CMT_TOP_WW2END3_6", - "CMT_MMCM_A_WRCLK_TOFIFO", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_SE4C3_13", - "CMT_TOP_NE2A3_13", - "CMT_TOP_LOGIC_OUTS_L_B15_13", - "CMT_TOP_WW4B0_11", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_WW2END2_12", - "CMT_TOP_LOGIC_OUTS_L_B18_13", - "CMT_MMCM_PHASER_IN_B_ICLK", - "CMT_TOP_IMUX8_12", - "CMT_TOP_SW2A3_9", - "CMT_TOP_LOGIC_OUTS_L_B15_14", - "CMT_TOP_FAN2_13", - "CMT_TOP_IMUX26_13", - "CMT_TOP_BYP6_14", - "CMT_TOP_EE4C3_14", - "CMT_TOP_IMUX32_9", - "CMT_TOP_LOGIC_OUTS_L_B8_13", - "CMT_TOP_EE2A0_2", - "CMT_TOP_SW4END2_6", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_IMUX47_1", - "CMT_TOP_WW4END2_13", - "CMT_TOP_WW2A2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_13", - "CMT_TOP_NW2A1_7", - "CMT_TOP_IMUX14_0", - "CMT_TOP_LH7_4", - "CMT_TOP_EE4C0_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX45_3", - "CMT_TOP_SW4END3_11", - "CMT_TOP_WW4C1_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_IMUX42_8", - "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX33_7", - "CMT_TOP_SE2A1_15", - "CMT_LR_LOWER_B_MMCM_TESTOUT54", - "CMT_TOP_NW2A1_13", - "CMT_PHASER_A_ICLKDIV_TOIOI", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "CMT_TOP_SE4BEG0_15", - "CMT_TOP_FAN4_11", - "CMT_TOP_LH5_4", - "CMT_TOP_CLK0_4", - "CMT_TOP_OCLK_9", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX23_13", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_WW4A3_4", - "CMT_TOP_LH2_15", - "CMT_TOP_NW4A1_6", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SW4END2_13", - "CMT_TOP_IMUX41_12", - "CMT_TOP_SW4A3_4", - "CMT_TOP_NE2A0_10", - "CMT_LR_LOWER_B_MMCM_DCLK", - "CMT_TOP_OCLK1X_90_4", - "CMT_LR_LOWER_B_MMCM_TESTIN10", - "CMT_TOP_LH8_7", - "CMT_TOP_IMUX32_5", - "CMT_TOP_SW2A1_5", - "CMT_TOP_WR1END0_1", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_LOGIC_OUTS_L_B13_10" - ], - "sites": [ - { - "prefix": "MMCME2_ADV", - "y_coord": 0, - "type": "MMCME2_ADV", - "site_pins": { - "TESTOUT33": "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "TESTOUT45": "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "TESTOUT41": "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "TESTOUT48": "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "DI10": "CMT_LR_LOWER_B_MMCM_DI10", - "TESTOUT8": "CMT_LR_LOWER_B_MMCM_TESTOUT8", - "DO8": "CMT_LR_LOWER_B_MMCM_DO8", - "TESTOUT10": "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "DADDR0": "CMT_LR_LOWER_B_MMCM_DADDR0", - "TESTIN16": "CMT_LR_LOWER_B_MMCM_TESTIN16", - "TESTIN14": "CMT_LR_LOWER_B_MMCM_TESTIN14", - "TESTOUT29": "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "TESTIN7": "CMT_LR_LOWER_B_MMCM_TESTIN7", - "TESTOUT14": "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "TESTIN23": "CMT_LR_LOWER_B_MMCM_TESTIN23", - "TESTOUT3": "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "DADDR5": "CMT_LR_LOWER_B_MMCM_DADDR5", - "TESTIN28": "CMT_LR_LOWER_B_MMCM_TESTIN28", - "TESTOUT24": "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "CLKOUT1B": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "DO15": "CMT_LR_LOWER_B_MMCM_DO15", - "TESTOUT62": "CMT_LR_LOWER_B_MMCM_TESTOUT62", - "TESTIN1": "CMT_LR_LOWER_B_MMCM_TESTIN1", - "DI8": "CMT_LR_LOWER_B_MMCM_DI8", - "DI13": "CMT_LR_LOWER_B_MMCM_DI13", - "CLKINSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", - "TESTIN15": "CMT_LR_LOWER_B_MMCM_TESTIN15", - "TESTOUT7": "CMT_LR_LOWER_B_MMCM_TESTOUT7", - "DI1": "CMT_LR_LOWER_B_MMCM_DI1", - "PSEN": "CMT_LR_LOWER_B_MMCM_PSEN", - "TESTIN12": "CMT_LR_LOWER_B_MMCM_TESTIN12", - "TESTOUT25": "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "DI3": "CMT_LR_LOWER_B_MMCM_DI3", - "TESTOUT31": "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "DI9": "CMT_LR_LOWER_B_MMCM_DI9", - "TESTOUT44": "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "TESTOUT63": "CMT_LR_LOWER_B_MMCM_TESTOUT63", - "DO4": "CMT_LR_LOWER_B_MMCM_DO4", - "TESTOUT21": "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "DO10": "CMT_LR_LOWER_B_MMCM_DO10", - "TESTOUT57": "CMT_LR_LOWER_B_MMCM_TESTOUT57", - "CLKFBSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", - "TESTIN10": "CMT_LR_LOWER_B_MMCM_TESTIN10", - "DO11": "CMT_LR_LOWER_B_MMCM_DO11", - "DI11": "CMT_LR_LOWER_B_MMCM_DI11", - "TESTOUT15": "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "TESTOUT40": "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "CLKOUT1": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "TESTIN8": "CMT_LR_LOWER_B_MMCM_TESTIN8", - "DO6": "CMT_LR_LOWER_B_MMCM_DO6", - "TESTOUT60": "CMT_LR_LOWER_B_MMCM_TESTOUT60", - "TESTOUT20": "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "DI14": "CMT_LR_LOWER_B_MMCM_DI14", - "TESTOUT27": "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "DEN": "CMT_LR_LOWER_B_MMCM_DEN", - "DADDR6": "CMT_LR_LOWER_B_MMCM_DADDR6", - "DADDR4": "CMT_LR_LOWER_B_MMCM_DADDR4", - "DADDR1": "CMT_LR_LOWER_B_MMCM_DADDR1", - "TESTIN20": "CMT_LR_LOWER_B_MMCM_TESTIN20", - "DO7": "CMT_LR_LOWER_B_MMCM_DO7", - "TESTIN9": "CMT_LR_LOWER_B_MMCM_TESTIN9", - "PSDONE": "CMT_LR_LOWER_B_MMCM_PSDONE", - "TESTIN19": "CMT_LR_LOWER_B_MMCM_TESTIN19", - "TESTIN27": "CMT_LR_LOWER_B_MMCM_TESTIN27", - "DI0": "CMT_LR_LOWER_B_MMCM_DI0", - "CLKOUT6": "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "TESTOUT28": "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "TESTIN30": "CMT_LR_LOWER_B_MMCM_TESTIN30", - "TESTOUT6": "CMT_LR_LOWER_B_MMCM_TESTOUT6", - "TMUXOUT": "CMT_LR_LOWER_B_MMCM_TMUXOUT", - "TESTOUT42": "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "TESTIN17": "CMT_LR_LOWER_B_MMCM_TESTIN17", - "DO3": "CMT_LR_LOWER_B_MMCM_DO3", - "CLKOUT2": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "CLKOUT0": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "TESTOUT52": "CMT_LR_LOWER_B_MMCM_TESTOUT52", - "DI2": "CMT_LR_LOWER_B_MMCM_DI2", - "TESTOUT9": "CMT_LR_LOWER_B_MMCM_TESTOUT9", - "DRDY": "CMT_LR_LOWER_B_MMCM_DRDY", - "TESTOUT51": "CMT_LR_LOWER_B_MMCM_TESTOUT51", - "DCLK": "CMT_LR_LOWER_B_MMCM_DCLK", - "RST": "CMT_LR_LOWER_B_MMCM_RST", - "DI7": "CMT_LR_LOWER_B_MMCM_DI7", - "DO0": "CMT_LR_LOWER_B_MMCM_DO0", - "PWRDWN": "CMT_LR_LOWER_B_MMCM_PWRDWN", - "TESTOUT61": "CMT_LR_LOWER_B_MMCM_TESTOUT61", - "CLKINSEL": "CMT_LR_LOWER_B_MMCM_CLKINSEL", - "TESTOUT19": "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "TESTOUT23": "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "CLKIN1": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "TESTOUT30": "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "TESTOUT18": "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "DI15": "CMT_LR_LOWER_B_MMCM_DI15", - "TESTIN6": "CMT_LR_LOWER_B_MMCM_TESTIN6", - "TESTIN11": "CMT_LR_LOWER_B_MMCM_TESTIN11", - "TESTIN4": "CMT_LR_LOWER_B_MMCM_TESTIN4", - "PSCLK": "CMT_LR_LOWER_B_MMCM_PSCLK", - "TESTOUT50": "CMT_LR_LOWER_B_MMCM_TESTOUT50", - "DI12": "CMT_LR_LOWER_B_MMCM_DI12", - "DO1": "CMT_LR_LOWER_B_MMCM_DO1", - "DO5": "CMT_LR_LOWER_B_MMCM_DO5", - "CLKOUT3B": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "TESTOUT16": "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "TESTOUT22": "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "TESTIN31": "CMT_LR_LOWER_B_MMCM_TESTIN31", - "CLKOUT4": "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "DO2": "CMT_LR_LOWER_B_MMCM_DO2", - "TESTOUT59": "CMT_LR_LOWER_B_MMCM_TESTOUT59", - "TESTIN5": "CMT_LR_LOWER_B_MMCM_TESTIN5", - "TESTOUT11": "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "TESTOUT58": "CMT_LR_LOWER_B_MMCM_TESTOUT58", - "DWE": "CMT_LR_LOWER_B_MMCM_DWE", - "TESTOUT37": "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "DI5": "CMT_LR_LOWER_B_MMCM_DI5", - "TESTIN18": "CMT_LR_LOWER_B_MMCM_TESTIN18", - "CLKFBIN": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "CLKFBOUT": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "DI6": "CMT_LR_LOWER_B_MMCM_DI6", - "TESTOUT26": "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "TESTOUT35": "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "TESTOUT32": "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "TESTOUT0": "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "TESTIN25": "CMT_LR_LOWER_B_MMCM_TESTIN25", - "DO12": "CMT_LR_LOWER_B_MMCM_DO12", - "TESTOUT53": "CMT_LR_LOWER_B_MMCM_TESTOUT53", - "TESTIN21": "CMT_LR_LOWER_B_MMCM_TESTIN21", - "CLKOUT0B": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", - "TESTOUT39": "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "DO14": "CMT_LR_LOWER_B_MMCM_DO14", - "TESTOUT46": "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "CLKIN2": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "CLKOUT2B": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "TESTOUT4": "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "TESTOUT55": "CMT_LR_LOWER_B_MMCM_TESTOUT55", - "TESTOUT47": "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "TESTOUT43": "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "TESTOUT36": "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "TESTIN2": "CMT_LR_LOWER_B_MMCM_TESTIN2", - "DADDR2": "CMT_LR_LOWER_B_MMCM_DADDR2", - "TESTOUT54": "CMT_LR_LOWER_B_MMCM_TESTOUT54", - "CLKOUT5": "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "TESTIN24": "CMT_LR_LOWER_B_MMCM_TESTIN24", - "TESTIN29": "CMT_LR_LOWER_B_MMCM_TESTIN29", - "TESTOUT38": "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "LOCKED": "CMT_LR_LOWER_B_MMCM_LOCKED", - "TESTOUT56": "CMT_LR_LOWER_B_MMCM_TESTOUT56", - "PSINCDEC": "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "CLKOUT3": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "TESTIN0": "CMT_LR_LOWER_B_MMCM_TESTIN0", - "TESTIN13": "CMT_LR_LOWER_B_MMCM_TESTIN13", - "TESTIN26": "CMT_LR_LOWER_B_MMCM_TESTIN26", - "TESTOUT2": "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "DO9": "CMT_LR_LOWER_B_MMCM_DO9", - "TESTOUT34": "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "DI4": "CMT_LR_LOWER_B_MMCM_DI4", - "TESTOUT49": "CMT_LR_LOWER_B_MMCM_TESTOUT49", - "TESTIN3": "CMT_LR_LOWER_B_MMCM_TESTIN3", - "TESTIN22": "CMT_LR_LOWER_B_MMCM_TESTIN22", - "TESTOUT17": "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "TESTOUT5": "CMT_LR_LOWER_B_MMCM_TESTOUT5", - "TESTOUT13": "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "DO13": "CMT_LR_LOWER_B_MMCM_DO13", - "TESTOUT12": "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "CLKFBOUTB": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", - "DADDR3": "CMT_LR_LOWER_B_MMCM_DADDR3", - "TESTOUT1": "CMT_LR_LOWER_B_MMCM_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_14": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_14", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_14->>CMT_R_LOWER_B_CLK_IN3_INT": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_IN3_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_14", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_CLK1_15->>CMT_R_LOWER_B_CLK_IN2_INT": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_IN2_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK1_15", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX7_0->>CMT_LR_LOWER_B_MMCM_DI14": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI14", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX7_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>MMCMOUT_CLK_FREQ_BB_3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK1X_90->>CMT_PHASER_A_OCLK90_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_A_OCLK90_TOIOI", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX44_1->>CMT_LR_LOWER_B_MMCM_DADDR6": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO1->>CMT_TOP_LOGIC_OUTS_L_B18_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX2_2->>CMT_LR_LOWER_B_MMCM_PSINCDEC": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX6_0->>CMT_LR_LOWER_B_MMCM_DI12": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI12", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX6_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX1_2->>CMT_LR_LOWER_B_MMCM_PSEN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_PSEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_MMCM2": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF2": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_13": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_13", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT4->>CMT_R_LOWER_B_CLK_MMCM8": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM8", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO10->>CMT_TOP_LOGIC_OUTS_L_B2_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO10", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0B->>CMT_R_LOWER_B_CLK_MMCM1": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2B->>CMT_R_LOWER_B_CLK_MMCM5": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM5", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX3_1->>CMT_LR_LOWER_B_MMCM_DADDR4": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT5->>CMT_R_LOWER_B_CLK_MMCM9": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM9", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX22_1->>CMT_LR_LOWER_B_MMCM_DWE": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DWE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX22_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX36_0->>CMT_LR_LOWER_B_MMCM_DI9": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI9", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX36_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_8", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK->>CMT_PHASER_A_OCLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO13->>CMT_TOP_LOGIC_OUTS_L_B21_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO13", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DRDY", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_15": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_15", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_1->>CMT_LR_LOWER_B_MMCM_PSCLK": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_PSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX0_1->>CMT_LR_LOWER_B_MMCM_DADDR0": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS<<->>MMCM_CLK_FREQ_BB_NS3": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQ_BB_NS3", - "is_directional": "0", - "src_wire": "MMCM_CLK_FREQ_BB_REBUF3_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF1_NS<<->>MMCM_CLK_FREQ_BB_NS1": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQ_BB_NS1", - "is_directional": "0", - "src_wire": "MMCM_CLK_FREQ_BB_REBUF1_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT6->>CMT_R_LOWER_B_CLK_MMCM10": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM10", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX15_1->>CMT_LR_LOWER_B_MMCM_DEN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_IN1_HCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSDONE->>CMT_TOP_LOGIC_OUTS_L_B21_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_PSDONE", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLK->>CMT_PHASER_A_ICLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_A_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX33_0->>CMT_LR_LOWER_B_MMCM_DI3": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX33_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX4_0->>CMT_LR_LOWER_B_MMCM_DI8": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX4_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQ_BB_NS0", - "is_directional": "0", - "src_wire": "MMCM_CLK_FREQ_BB_REBUF0_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_13": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_13", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO0->>CMT_TOP_LOGIC_OUTS_L_B8_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO4->>CMT_TOP_LOGIC_OUTS_L_B13_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_INT->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_IN3_INT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_8", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B18_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_LOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO3->>CMT_TOP_LOGIC_OUTS_L_B22_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>MMCMOUT_CLK_FREQ_BB_1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", - "is_pseudo": "0" - }, "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX47_1->>CMT_LR_LOWER_B_MMCM_PWRDWN": { "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_PWRDWN", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX47_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX1_1->>CMT_LR_LOWER_B_MMCM_DADDR1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR1", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO7->>CMT_TOP_LOGIC_OUTS_L_B19_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO7", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_MMCM11": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM11", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_15": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_15", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX37_0->>CMT_LR_LOWER_B_MMCM_DI11": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI11", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX37_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF2": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B16_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PWRDWN" }, "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_12": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_12", - "is_directional": "1", "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX2_0->>CMT_LR_LOWER_B_MMCM_DI4": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI4", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX1_0->>CMT_LR_LOWER_B_MMCM_DI2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>MMCMOUT_CLK_FREQ_BB_2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX5_0->>CMT_LR_LOWER_B_MMCM_DI10": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI10", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX5_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_13": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_13", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX35_0->>CMT_LR_LOWER_B_MMCM_DI7": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX35_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_MMCM6": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM6", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO6->>CMT_TOP_LOGIC_OUTS_L_B5_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO8->>CMT_TOP_LOGIC_OUTS_L_B10_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO8", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1B->>CMT_R_LOWER_B_CLK_MMCM3": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B18_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO9->>CMT_TOP_LOGIC_OUTS_L_B16_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO9", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_14": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_14", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX0_2->>CMT_LR_LOWER_B_MMCM_CLKINSEL": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKINSEL", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_HCLK->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_IN3_HCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLKDIV->>CMT_PHASER_A_ICLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_A_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLKDIV->>CMT_PHASER_A_OCLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO12->>CMT_TOP_LOGIC_OUTS_L_B15_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO12", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_INT->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_IN1_INT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX35_1->>CMT_LR_LOWER_B_MMCM_DADDR5": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX35_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO2->>CMT_TOP_LOGIC_OUTS_L_B0_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHYCTRL_SYNC_BB_DN<<->>CMT_MMCM_PHYCTRL_SYNC_BB_UP": { - "can_invert": "0", - "dst_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_UP", - "is_directional": "0", - "src_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_DN", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO5->>CMT_TOP_LOGIC_OUTS_L_B23_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3->>CMT_R_LOWER_B_CLK_FREQ_BB0": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", - "is_directional": "1", - "src_wire": "MMCM_CLK_FREQ_BB_NS3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_INT->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_IN2_INT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX34_1->>CMT_LR_LOWER_B_MMCM_DADDR3": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_14": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_14", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF2": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO15->>CMT_TOP_LOGIC_OUTS_L_B17_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO15", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_8", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_MMCM4": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM4", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_MMCM0": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_TMUXOUT->>CMT_R_LOWER_B_CLK_MMCM13": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM13", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_TMUXOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_LR_LOWER_B_CLKFBOUT2IN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_12" }, "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "is_directional": "1", "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0->>CMT_R_LOWER_B_CLK_FREQ_BB3": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", "is_directional": "1", - "src_wire": "MMCM_CLK_FREQ_BB_NS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_15": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_15", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX38_0->>CMT_LR_LOWER_B_MMCM_DI13": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI13", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX38_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX32_0->>CMT_LR_LOWER_B_MMCM_DI1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX34_0->>CMT_LR_LOWER_B_MMCM_DI5": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_15->>CMT_R_LOWER_B_CLK_IN1_INT": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_IN1_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_15", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>MMCMOUT_CLK_FREQ_BB_0": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF1": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF1", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" }, "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_2": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_2", - "is_directional": "1", "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO14->>CMT_TOP_LOGIC_OUTS_L_B7_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2" }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_14": { + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>MMCMOUT_CLK_FREQ_BB_3": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_14", - "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF2": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", - "is_directional": "1", "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF0": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF0", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_3" }, - "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1->>CMT_R_LOWER_B_CLK_FREQ_BB2": { + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", - "is_directional": "1", - "src_wire": "MMCM_CLK_FREQ_BB_NS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX34_2->>CMT_LR_LOWER_B_MMCM_RST": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF3": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF3", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO11->>CMT_TOP_LOGIC_OUTS_L_B20_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_0", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_DO11", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX2_1->>CMT_LR_LOWER_B_MMCM_DADDR2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3B->>CMT_R_LOWER_B_CLK_MMCM7": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM7", - "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_6", - "is_directional": "1", "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_15": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_15", "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_12" }, - "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF2": { + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN2": { "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_PERF2", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", "is_directional": "1", - "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2->>CMT_R_LOWER_B_CLK_FREQ_BB1": { - "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", - "is_directional": "1", - "src_wire": "MMCM_CLK_FREQ_BB_NS2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK1X_90_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_OCLK90_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_10", - "is_directional": "1", "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_3", "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF2_NS<<->>MMCM_CLK_FREQ_BB_NS2": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQ_BB_NS2", - "is_directional": "0", - "src_wire": "MMCM_CLK_FREQ_BB_REBUF2_NS", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9" }, "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_0->>CMT_LR_LOWER_B_MMCM_DCLK": { "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DCLK", - "is_directional": "1", "src_wire": "CMT_TOP_CLK0_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX0_0->>CMT_LR_LOWER_B_MMCM_DI0": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI0", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DCLK" }, - "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_14": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_9", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_14" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_MMCM6": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM6" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "can_invert": "0", "src_wire": "CMT_PHASER_A_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10" }, - "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_1": { "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "src_wire": "CMT_LR_LOWER_B_MMCM_DRDY", "is_directional": "1", - "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1" }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX6_0->>CMT_LR_LOWER_B_MMCM_DI12": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", + "src_wire": "CMT_TOP_IMUX6_0", "is_directional": "1", - "src_wire": "CMT_MMCM_PHASERA_CTSBUS1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI12" }, - "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_13": { + "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_14->>CMT_R_LOWER_B_CLK_IN3_INT": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_13", + "src_wire": "CMT_TOP_CLK0_14", "is_directional": "1", - "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_IN3_INT" }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX3_0->>CMT_LR_LOWER_B_MMCM_DI6": { + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2->>CMT_R_LOWER_B_CLK_FREQ_BB1": { "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI6", + "src_wire": "MMCM_CLK_FREQ_BB_NS2", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK90_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_8" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT6->>CMT_R_LOWER_B_CLK_MMCM10": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM10" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_INT->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_IN1_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_MMCM4": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM4" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO9->>CMT_TOP_LOGIC_OUTS_L_B16_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS<<->>MMCM_CLK_FREQ_BB_NS3": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_REBUF3_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS3" }, "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUTB->>CMT_R_LOWER_B_CLK_MMCM12": { "can_invert": "0", - "dst_wire": "CMT_R_LOWER_B_CLK_MMCM12", - "is_directional": "1", "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX39_0->>CMT_LR_LOWER_B_MMCM_DI15": { - "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_DI15", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX39_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM12" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX1_1->>CMT_LR_LOWER_B_MMCM_DADDR1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR1" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_MMCM2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM2" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX36_0->>CMT_LR_LOWER_B_MMCM_DI9": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI9" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_8": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_8" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO2->>CMT_TOP_LOGIC_OUTS_L_B0_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO10->>CMT_TOP_LOGIC_OUTS_L_B2_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX32_0->>CMT_LR_LOWER_B_MMCM_DI1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI1" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0->>CMT_R_LOWER_B_CLK_FREQ_BB3": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_NS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_INT->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_IN2_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_LR_LOWER_B_CLKFBOUT2IN": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO5->>CMT_TOP_LOGIC_OUTS_L_B23_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX0_1->>CMT_LR_LOWER_B_MMCM_DADDR0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX38_0->>CMT_LR_LOWER_B_MMCM_DI13": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI13" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX22_1->>CMT_LR_LOWER_B_MMCM_DWE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DWE" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_HCLK->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_IN3_HCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_MMCM0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLK->>CMT_PHASER_A_ICLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_A_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_ICLK_TOIOI" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN1_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_IN1_HCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3B->>CMT_R_LOWER_B_CLK_MMCM7": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM7" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2B->>CMT_R_LOWER_B_CLK_MMCM5": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM5" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX4_0->>CMT_LR_LOWER_B_MMCM_DI8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI8" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_A_ICLKDIV->>CMT_PHASER_A_ICLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_ICLKDIV_TOIOI" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX3_0->>CMT_LR_LOWER_B_MMCM_DI6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI6" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_REBUF0_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX34_1->>CMT_LR_LOWER_B_MMCM_DADDR3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR3" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN3_INT->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_IN3_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B18_2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX15_1->>CMT_LR_LOWER_B_MMCM_DEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DEN" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO7->>CMT_TOP_LOGIC_OUTS_L_B19_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX0_0->>CMT_LR_LOWER_B_MMCM_DI0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX3_1->>CMT_LR_LOWER_B_MMCM_DADDR4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR4" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO4->>CMT_TOP_LOGIC_OUTS_L_B13_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_1->>CMT_LR_LOWER_B_MMCM_PSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSCLK" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1B->>CMT_R_LOWER_B_CLK_MMCM3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM3" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>MMCMOUT_CLK_FREQ_BB_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_MMCM11": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM11" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF2_NS<<->>MMCM_CLK_FREQ_BB_NS2": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_REBUF2_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS2" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_15": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_15" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO3->>CMT_TOP_LOGIC_OUTS_L_B22_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_0" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3->>CMT_R_LOWER_B_CLK_FREQ_BB0": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_NS3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_15": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_15" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1->>CMT_R_LOWER_B_CLK_FREQ_BB2": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_NS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX1_2->>CMT_LR_LOWER_B_MMCM_PSEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSEN" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB3->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX35_0->>CMT_LR_LOWER_B_MMCM_DI7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI7" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B16_2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_2" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_8": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_8" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX35_1->>CMT_LR_LOWER_B_MMCM_DADDR5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR5" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_14": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_14" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_R_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO12->>CMT_TOP_LOGIC_OUTS_L_B15_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLK->>CMT_TOP_OCLK_13": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_13" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>CMT_R_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO11->>CMT_TOP_LOGIC_OUTS_L_B20_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_CLK0_15->>CMT_R_LOWER_B_CLK_IN1_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_IN1_INT" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_R_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_12" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_15": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_15" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>MMCMOUT_CLK_FREQ_BB_1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_1" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO15->>CMT_TOP_LOGIC_OUTS_L_B17_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX5_0->>CMT_LR_LOWER_B_MMCM_DI10": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI10" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK->>CMT_PHASER_A_OCLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLK_TOIOI" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX34_0->>CMT_LR_LOWER_B_MMCM_DI5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI5" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO13->>CMT_TOP_LOGIC_OUTS_L_B21_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX2_2->>CMT_LR_LOWER_B_MMCM_PSINCDEC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_PSINCDEC" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_CLK1_15->>CMT_R_LOWER_B_CLK_IN2_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK1_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_IN2_INT" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11" + }, + "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF1_NS<<->>MMCM_CLK_FREQ_BB_NS1": { + "can_invert": "0", + "src_wire": "MMCM_CLK_FREQ_BB_REBUF1_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQ_BB_NS1" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_13": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_13" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_14": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_14" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB2->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLKDIV->>CMT_PHASER_A_OCLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLKDIV_TOIOI" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_TMUXOUT->>CMT_R_LOWER_B_CLK_MMCM13": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM13" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX2_0->>CMT_LR_LOWER_B_MMCM_DI4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI4" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B18_1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_LOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_1" }, "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_IN2_HCLK->>CMT_LR_LOWER_B_MMCM_CLKIN2": { "can_invert": "0", - "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "is_directional": "1", "src_wire": "CMT_R_LOWER_B_CLK_IN2_HCLK", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT4->>CMT_R_LOWER_B_CLK_MMCM8": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM8" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX44_1->>CMT_LR_LOWER_B_MMCM_DADDR6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR6" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX7_0->>CMT_LR_LOWER_B_MMCM_DI14": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI14" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0B->>CMT_R_LOWER_B_CLK_MMCM1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM1" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO0->>CMT_TOP_LOGIC_OUTS_L_B8_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT5->>CMT_R_LOWER_B_CLK_MMCM9": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_MMCM9" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO1->>CMT_TOP_LOGIC_OUTS_L_B18_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_15": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_15" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO6->>CMT_TOP_LOGIC_OUTS_L_B5_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_0" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX2_1->>CMT_LR_LOWER_B_MMCM_DADDR2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR2" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHYCTRL_SYNC_BB_DN<<->>CMT_MMCM_PHYCTRL_SYNC_BB_UP": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_DN", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CMT_MMCM_PHYCTRL_SYNC_BB_UP" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLKDIV->>CMT_TOP_ICLKDIV_13": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_13" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX37_0->>CMT_LR_LOWER_B_MMCM_DI11": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI11" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF1" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_B_OCLKDIV->>CMT_TOP_OCLKDIV_14": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_14" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX33_0->>CMT_LR_LOWER_B_MMCM_DI3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI3" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT2->>MMCMOUT_CLK_FREQ_BB_2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_2" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASERA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_8": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASERA_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_8" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF2": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF2" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX0_2->>CMT_LR_LOWER_B_MMCM_CLKINSEL": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKINSEL" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB1->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_OUT_A_OCLK1X_90->>CMT_PHASER_A_OCLK90_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_A_OCLK90_TOIOI" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_12" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX34_2->>CMT_LR_LOWER_B_MMCM_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_RST" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_PSDONE->>CMT_TOP_LOGIC_OUTS_L_B21_1": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_PSDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO14->>CMT_TOP_LOGIC_OUTS_L_B7_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0" + }, + "CMT_TOP_R_LOWER_B.CMT_PHASER_A_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_A_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX1_0->>CMT_LR_LOWER_B_MMCM_DI2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI2" + }, + "CMT_TOP_R_LOWER_B.CMT_TOP_IMUX39_0->>CMT_LR_LOWER_B_MMCM_DI15": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_DI15" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT3->>CMT_R_LOWER_B_CLK_PERF0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF0" + }, + "CMT_TOP_R_LOWER_B.CMT_MMCM_PHASER_IN_B_ICLK->>CMT_TOP_ICLK_13": { + "can_invert": "0", + "src_wire": "CMT_MMCM_PHASER_IN_B_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_13" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_R_LOWER_B_CLK_PERF3": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_LOWER_B_CLK_PERF3" + }, + "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_MMCM_DO8->>CMT_TOP_LOGIC_OUTS_L_B10_0": { + "can_invert": "0", + "src_wire": "CMT_LR_LOWER_B_MMCM_DO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_0" + }, + "CMT_TOP_R_LOWER_B.CMT_R_LOWER_B_CLK_FREQ_BB0->>CMT_LR_LOWER_B_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" } }, - "tile_type": "CMT_TOP_R_LOWER_B" + "wires": [ + "CMT_TOP_LOGIC_OUTS_L_B8_14", + "CMT_TOP_IMUX18_15", + "CMT_TOP_NW4A2_6", + "CMT_TOP_WW2END3_2", + "CMT_TOP_BYP1_3", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_LR_LOWER_B_MMCM_TESTIN25", + "CMT_TOP_SE4C2_14", + "CMT_TOP_EE4B1_15", + "CMT_TOP_WW4A3_11", + "CMT_TOP_WW4END1_15", + "CMT_TOP_SW4END1_14", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_WW2A1_12", + "CMT_TOP_LH7_10", + "CMT_TOP_EE4C3_15", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_NW4A1_2", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_ER1BEG2_13", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_WW2A1_6", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_WW4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4END1_8", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_EE4B0_4", + "CMT_MMCM_DQS_TO_PHASERA", + "CMT_TOP_WW4END2_8", + "CMT_TOP_IMUX7_3", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NE4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_BYP6_2", + "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "CMT_R_LOWER_B_CLK_PERF3", + "CMT_TOP_LH3_8", + "CMT_TOP_WW4B0_5", + "CMT_TOP_LH12_10", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX41_8", + "CMT_TOP_IMUX36_7", + "CMT_TOP_NE4C0_9", + "CMT_TOP_IMUX32_8", + "CMT_TOP_IMUX17_10", + "CMT_TOP_IMUX7_9", + "CMT_TOP_SW4END0_1", + "CMT_TOP_WW2END3_5", + "CMT_TOP_FAN5_13", + "CMT_TOP_IMUX12_8", + "CMT_TOP_NW4END3_1", + "CMT_TOP_EE4A2_14", + "CMT_TOP_IMUX38_14", + "CMT_TOP_LOGIC_OUTS_L_B6_14", + "CMT_TOP_NE2A3_0", + "CMT_TOP_CLK1_3", + "CMT_TOP_EL1BEG1_14", + "CMT_TOP_WR1END0_8", + "CMT_TOP_FAN2_8", + "CMT_TOP_IMUX29_10", + "CMT_TOP_LH12_14", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_SW2A1_15", + "CMT_TOP_WW2END0_15", + "CMT_TOP_WW4B3_13", + "CMT_TOP_EE4B3_0", + "CMT_TOP_BYP4_1", + "CMT_TOP_NE2A3_12", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_OCLK_7", + "CMT_TOP_WW4C0_11", + "CMT_TOP_WW4C0_3", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_NE4C2_13", + "CMT_TOP_EE4C2_1", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_IMUX1_1", + "CMT_TOP_EE2A0_9", + "CMT_TOP_LH2_9", + "CMT_TOP_NE2A0_14", + "CMT_TOP_SE4C1_10", + "CMT_TOP_NW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_NE4BEG2_13", + "CMT_TOP_SE4C2_9", + "CMT_TOP_IMUX35_6", + "CMT_TOP_WW2A3_12", + "CMT_TOP_EE4A0_6", + "CMT_TOP_SE4C0_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_WL1END1_9", + "CMT_TOP_BYP5_12", + "CMT_TOP_EE4C0_9", + "CMT_TOP_WW2END1_3", + "CMT_TOP_IMUX3_4", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_NE2A1_0", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_IMUX39_7", + "CMT_TOP_IMUX14_2", + "CMT_MMCM_PHYCTRL_SYNC_BB_DN", + "CMT_TOP_WW4C3_2", + "CMT_TOP_EE4B3_8", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW4END1_5", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_IMUX11_14", + "CMT_TOP_EE4A2_7", + "CMT_TOP_EE2A0_1", + "CMT_TOP_LOGIC_OUTS_L_B10_12", + "CMT_TOP_IMUX4_14", + "CMT_TOP_WW4B0_6", + "CMT_TOP_IMUX12_9", + "CMT_TOP_WW4A0_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_NE4BEG2_12", + "CMT_TOP_WW2A1_11", + "CMT_TOP_IMUX36_15", + "CMT_TOP_IMUX23_6", + "CMT_TOP_IMUX26_12", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B13_12", + "CMT_TOP_NE4BEG2_15", + "CMT_TOP_IMUX1_3", + "CMT_TOP_SE4C1_9", + "CMT_TOP_EE4C2_13", + "CMT_TOP_WW4END0_14", + "CMT_TOP_WW2A0_9", + "CMT_TOP_WW4C1_11", + "CMT_TOP_ER1BEG1_14", + "CMT_TOP_BYP7_3", + "CMT_TOP_EE4A0_9", + "CMT_TOP_IMUX6_11", + "CMT_TOP_OCLKDIV_14", + "CMT_TOP_IMUX30_7", + "CMT_TOP_ICLK_4", + "CMT_TOP_BYP5_9", + "CMT_TOP_EE2A0_13", + "CMT_TOP_LOGIC_OUTS_L_B21_15", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_WW4B0_14", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN1_13", + "CMT_LR_LOWER_B_MMCM_TESTOUT12", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX30_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_LOGIC_OUTS_L_B11_13", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_WW2A0_5", + "CMT_TOP_LOGIC_OUTS_L_B18_15", + "CMT_TOP_WW4C1_0", + "CMT_TOP_WL1END2_11", + "CMT_TOP_IMUX14_3", + "CMT_TOP_EE4B1_9", + "CMT_LR_LOWER_B_MMCM_DADDR2", + "CMT_TOP_SW4END1_5", + "CMT_TOP_WL1END3_14", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_NE2A0_2", + "CMT_TOP_WW4C2_11", + "CMT_TOP_NW2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_NE4BEG0_15", + "CMT_TOP_FAN3_8", + "CMT_LR_LOWER_B_MMCM_DO10", + "CMT_TOP_EL1BEG0_14", + "CMT_TOP_IMUX27_7", + "CMT_TOP_WW4END1_1", + "CMT_TOP_CLK1_15", + "CMT_TOP_FAN4_11", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LH8_6", + "CMT_TOP_SW4A3_15", + "CMT_TOP_FAN0_12", + "CMT_TOP_EE4A0_1", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_WL1END0_14", + "CMT_TOP_WL1END2_3", + "CMT_TOP_SW4END1_9", + "CMT_TOP_NW4A1_14", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4END1_6", + "CMT_TOP_WL1END2_4", + "CMT_TOP_FAN5_15", + "CMT_TOP_WR1END0_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT9", + "CMT_TOP_LH5_9", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX3_3", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_WW4B0_12", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_EE4A0_15", + "CMT_TOP_SW4A2_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT63", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_SE4BEG1_12", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_IMUX27_13", + "CMT_TOP_IMUX46_15", + "CMT_TOP_LOGIC_OUTS_L_B17_12", + "CMT_TOP_LH10_14", + "CMT_TOP_WW4B2_13", + "CMT_TOP_IMUX44_14", + "CMT_TOP_WW4A1_9", + "CMT_TOP_EE4A3_13", + "CMT_TOP_EE2A0_5", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH4_7", + "CMT_TOP_IMUX8_11", + "CMT_TOP_LH2_15", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B23_12", + "CMT_TOP_LH4_11", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_WR1END3_14", + "CMT_TOP_EE4A1_2", + "CMT_TOP_EE4C0_14", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_IMUX14_4", + "CMT_TOP_EE4C0_13", + "CMT_TOP_EE4A3_14", + "CMT_TOP_EE4B2_13", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_IMUX14_12", + "CMT_TOP_CTRL0_5", + "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "CMT_TOP_WW4C0_13", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_EE4A0_3", + "CMT_TOP_IMUX11_12", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX43_3", + "CMT_TOP_WW4A3_15", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LH11_11", + "CMT_TOP_FAN1_5", + "CMT_TOP_NW2A0_7", + "CMT_TOP_MONITOR_P_14", + "CMT_TOP_EE4B2_1", + "CMT_TOP_BYP2_12", + "CMT_TOP_IMUX31_7", + "CMT_TOP_WW4B2_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX6_10", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_IMUX47_0", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_IMUX21_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_FAN4_9", + "CMT_TOP_WW4A2_14", + "CMT_TOP_ER1BEG0_13", + "CMT_TOP_SW4A0_8", + "CMT_LR_LOWER_B_MMCM_DRDY", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_IMUX22_15", + "CMT_TOP_CLK0_0", + "CMT_TOP_LH9_7", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END3_7", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_IMUX5_11", + "CMT_TOP_EL1BEG3_13", + "CMT_TOP_EE4B2_9", + "CMT_TOP_IMUX33_12", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_NW2A1_2", + "CMT_TOP_WL1END0_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT14", + "CMT_TOP_SW4END1_1", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_TOP_NW4A1_1", + "CMT_LR_LOWER_B_MMCM_DWE", + "CMT_TOP_NW2A0_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT59", + "CMT_TOP_BYP3_9", + "CMT_TOP_WW2A2_4", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_SW4A0_9", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_NE2A0_11", + "CMT_TOP_EE4A2_11", + "CMT_TOP_SE4C2_5", + "CMT_TOP_WW4END2_7", + "CMT_TOP_BYP5_15", + "CMT_TOP_EE4A3_4", + "CMT_TOP_LH9_5", + "CMT_TOP_NE2A0_3", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_IMUX46_9", + "CMT_TOP_WR1END2_14", + "CMT_TOP_EE2A2_0", + "CMT_TOP_IMUX1_14", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_WW4END2_14", + "CMT_R_LOWER_B_CLK_MMCM3", + "CMT_TOP_WW2A3_15", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_IMUX33_11", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_IMUX26_4", + "CMT_TOP_WW4END1_14", + "CMT_TOP_IMUX38_1", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WR1END0_11", + "CMT_TOP_FAN4_10", + "CMT_TOP_FAN2_11", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_EE4B1_13", + "CMT_TOP_BYP1_8", + "CMT_TOP_IMUX31_1", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_SW4A2_14", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EE4C3_9", + "CMT_TOP_IMUX36_8", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SW4A1_0", + "CMT_TOP_SE2A1_10", + "CMT_TOP_EE4C0_5", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_LH7_0", + "CMT_TOP_IMUX33_7", + "CMT_TOP_SE4C1_2", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B6_13", + "CMT_TOP_FAN7_10", + "CMT_TOP_LH2_7", + "CMT_TOP_NE4C2_1", + "CMT_TOP_SW4A2_7", + "CMT_TOP_IMUX23_11", + "CMT_TOP_WR1END1_5", + "CMT_TOP_WW4A1_13", + "CMT_TOP_LOGIC_OUTS_L_B17_15", + "CMT_TOP_NE2A0_10", + "CMT_TOP_SW4END2_0", + "CMT_TOP_LH8_0", + "CMT_TOP_IMUX24_13", + "CMT_TOP_IMUX17_13", + "CMT_TOP_EE4C0_3", + "CMT_TOP_NW4A2_14", + "CMT_TOP_WL1END0_13", + "CMT_TOP_NW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_IMUX8_6", + "CMT_TOP_LH6_12", + "CMT_TOP_BYP0_7", + "CMT_TOP_LH5_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT7", + "CMT_TOP_IMUX5_2", + "CMT_TOP_BYP1_9", + "CMT_TOP_WL1END2_6", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX9_3", + "CMT_TOP_IMUX47_1", + "CMT_TOP_WW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_EE2A1_9", + "CMT_TOP_ER1BEG1_12", + "CMT_TOP_NE4C3_4", + "CMT_TOP_EE4B2_7", + "CMT_TOP_OCLK_5", + "CMT_TOP_NE2A1_6", + "CMT_TOP_IMUX45_4", + "CMT_TOP_IMUX8_2", + "CMT_TOP_IMUX1_2", + "CMT_TOP_IMUX46_0", + "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "CMT_TOP_EE4C1_9", + "MMCM_CLK_FREQ_BB_REBUF2_NS", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_SW4A0_15", + "CMT_TOP_LH1_7", + "CMT_R_LOWER_B_CLK_IN2_HCLK", + "CMT_TOP_BYP5_3", + "CMT_TOP_EE4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_12", + "CMT_TOP_IMUX40_4", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_BYP7_0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_LOGIC_OUTS_L_B23_14", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SW4A3_12", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4A3_6", + "CMT_TOP_LOGIC_OUTS_L_B12_13", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_EE4BEG0_12", + "CMT_TOP_FAN7_15", + "CMT_TOP_IMUX17_11", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_WR1END2_5", + "CMT_TOP_EE4A0_4", + "CMT_TOP_SE2A1_12", + "CMT_TOP_LOGIC_OUTS_L_B4_14", + "CMT_TOP_SW4A0_3", + "CMT_TOP_IMUX6_12", + "CMT_TOP_FAN3_15", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX11_6", + "CMT_TOP_IMUX25_7", + "CMT_TOP_IMUX4_8", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_WW4END3_12", + "CMT_TOP_WR1END3_12", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_WW2END0_13", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_IMUX16_8", + "CMT_TOP_MONITOR_P_15", + "CMT_TOP_NW4END0_5", + "CMT_TOP_NE4C3_10", + "CMT_TOP_WW4END1_12", + "CMT_TOP_SE2A3_6", + "CMT_TOP_IMUX3_9", + "CMT_TOP_IMUX7_4", + "CMT_TOP_LOGIC_OUTS_L_B14_15", + "CMT_TOP_EE4A0_13", + "CMT_TOP_LH3_11", + "CMT_TOP_EE2A3_14", + "CMT_TOP_BYP5_6", + "CMT_TOP_WW4C2_5", + "CMT_TOP_LH7_6", + "CMT_TOP_LOGIC_OUTS_L_B12_12", + "CMT_TOP_SE2A1_5", + "CMT_TOP_FAN4_7", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH9_2", + "CMT_TOP_LH2_12", + "CMT_TOP_BYP0_1", + "CMT_TOP_LH11_0", + "CMT_TOP_SE4BEG2_13", + "CMT_TOP_LH11_15", + "CMT_TOP_IMUX14_0", + "CMT_TOP_IMUX27_9", + "CMT_TOP_NW2A1_5", + "CMT_LR_LOWER_B_MMCM_TESTIN11", + "CMT_TOP_IMUX21_7", + "CMT_TOP_WW4A0_2", + "CMT_TOP_NE2A1_11", + "CMT_TOP_IMUX9_15", + "CMT_TOP_SW4END0_14", + "CMT_TOP_IMUX7_6", + "CMT_R_LOWER_B_CLK_IN2_INT", + "CMT_TOP_EE4B0_14", + "CMT_TOP_SW2A2_15", + "CMT_TOP_WL1END0_10", + "CMT_TOP_SW4END3_8", + "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "CMT_TOP_NW2A1_15", + "CMT_TOP_NW4A1_12", + "CMT_TOP_IMUX23_7", + "CMT_TOP_IMUX10_10", + "CMT_TOP_IMUX40_15", + "CMT_TOP_NW4END1_13", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4C1_2", + "CMT_TOP_LH4_3", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH5_6", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW4C1_4", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_FAN4_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_IMUX9_9", + "CMT_PHASER_A_OCLK_TOIOI", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NW4A3_5", + "CMT_TOP_BYP0_11", + "CMT_TOP_EE2BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B21_13", + "CMT_TOP_ICLK_13", + "CMT_TOP_IMUX25_15", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_IMUX33_2", + "CMT_TOP_BYP2_1", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_LOGIC_OUTS_L_B13_15", + "CMT_TOP_SE2A3_8", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_IMUX25_9", + "CMT_TOP_WW2END1_2", + "CMT_TOP_CLK0_14", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_LH8_12", + "CMT_TOP_EE4B2_2", + "CMT_LR_LOWER_B_MMCM_TESTIN26", + "CMT_TOP_WW4C3_14", + "CMT_LR_LOWER_B_MMCM_TESTIN29", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_IMUX13_9", + "CMT_TOP_NE4BEG0_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT51", + "CMT_TOP_ICLKDIV_12", + "CMT_TOP_NW2A2_7", + "CMT_TOP_OCLKDIV_11", + "CMT_LR_LOWER_B_MMCM_DI4", + "CMT_TOP_IMUX5_8", + "CMT_TOP_ICLKDIV_15", + "CMT_TOP_EL1BEG3_15", + "CMT_LR_LOWER_B_MMCM_TESTIN5", + "CMT_TOP_WW4C0_14", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_IMUX33_5", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WW4END2_11", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE4BEG0_15", + "CMT_TOP_EE2A0_7", + "CMT_TOP_WR1END1_10", + "CMT_TOP_FAN0_9", + "CMT_TOP_FAN4_15", + "CMT_TOP_EE4C2_10", + "CMT_TOP_SW4END3_0", + "CMT_TOP_WR1END1_2", + "CMT_TOP_NW4A1_5", + "CMT_TOP_EE4B3_12", + "CMT_TOP_IMUX4_9", + "CMT_TOP_IMUX47_8", + "CMT_LR_LOWER_B_MMCM_DO2", + "CMT_TOP_WW4C1_3", + "CMT_TOP_IMUX26_9", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_IMUX41_2", + "CMT_TOP_SE4C1_5", + "CMT_TOP_WL1END2_7", + "CMT_TOP_WW4A0_1", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_LH3_13", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_CTRL0_4", + "CMT_TOP_NW4END2_3", + "CMT_TOP_SE2A2_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT53", + "CMT_TOP_LOGIC_OUTS_L_B22_14", + "CMT_TOP_WW4C2_3", + "CMT_TOP_IMUX0_15", + "CMT_TOP_WW2A3_3", + "CMT_TOP_WL1END3_4", + "CMT_TOP_SE2A3_14", + "CMT_TOP_NE2A2_8", + "CMT_TOP_SW2A0_9", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_SW2A0_8", + "CMT_TOP_WW4B3_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_SW4A3_9", + "CMT_TOP_SE4C0_7", + "CMT_TOP_IMUX1_10", + "CMT_TOP_IMUX4_0", + "CMT_TOP_IMUX40_2", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_IMUX6_15", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX1_6", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_IMUX14_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_IMUX7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WW4A2_4", + "CMT_TOP_WW4B1_7", + "CMT_TOP_SE4BEG1_13", + "CMT_TOP_EE2A1_6", + "CMT_TOP_IMUX19_2", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_WW4C2_13", + "CMT_TOP_IMUX25_12", + "CMT_TOP_MONITOR_N_6", + "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_FAN3_4", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP7_9", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX24_10", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_SW4END1_13", + "CMT_TOP_IMUX19_12", + "CMT_TOP_SW2A0_2", + "CMT_TOP_BYP7_8", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX47_7", + "CMT_TOP_BYP0_4", + "CMT_TOP_IMUX21_6", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_EE4A3_11", + "CMT_TOP_FAN4_13", + "CMT_TOP_IMUX5_4", + "CMT_TOP_SE2A3_10", + "CMT_TOP_SW4END2_10", + "CMT_TOP_NW2A0_5", + "CMT_TOP_SE2A0_14", + "CMT_TOP_NE4C1_2", + "CMT_TOP_WW4C0_9", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_WW2END0_1", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_EE2BEG1_15", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_LR_LOWER_B_MMCM_DI1", + "CMT_LR_LOWER_B_MMCM_DI8", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_IMUX33_13", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX0_0", + "CMT_MMCM_A_RDCLK_TOFIFO", + "CMT_TOP_IMUX15_9", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SW2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B19_15", + "CMT_TOP_WW4C2_0", + "CMT_TOP_ICLK_8", + "CMT_TOP_FAN4_14", + "CMT_TOP_EE4C1_15", + "CMT_TOP_NW2A1_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT50", + "CMT_TOP_CTRL0_6", + "CMT_LR_LOWER_B_MMCM_DI9", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_NE4BEG1_9", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_WW4A0_6", + "CMT_TOP_IMUX6_8", + "CMT_TOP_WW4C0_15", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WR1END0_1", + "CMT_TOP_CLK0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_IMUX41_13", + "CMT_TOP_EE4B3_15", + "CMT_LR_LOWER_B_MMCM_TESTIN30", + "CMT_TOP_FAN6_15", + "CMT_TOP_LH10_12", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_SW2A1_4", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_IMUX27_1", + "CMT_TOP_IMUX31_15", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_LOGIC_OUTS_L_B19_13", + "CMT_TOP_BYP3_14", + "CMT_TOP_IMUX23_9", + "CMT_TOP_IMUX4_13", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_IMUX30_6", + "CMT_TOP_NW4END1_9", + "CMT_TOP_EE2BEG0_15", + "CMT_TOP_IMUX39_2", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX10_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_WW4END3_0", + "MMCMOUT_CLK_FREQ_BB_2", + "CMT_TOP_LH9_15", + "CMT_TOP_NW4END1_11", + "CMT_TOP_LOGIC_OUTS_L_B15_12", + "CMT_TOP_EE4C2_8", + "CMT_TOP_IMUX16_3", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_SW4A3_11", + "CMT_TOP_IMUX43_11", + "CMT_TOP_OCLK_8", + "CMT_TOP_NE2A0_6", + "CMT_TOP_WW2A3_2", + "CMT_LR_LOWER_B_MMCM_TESTIN22", + "CMT_TOP_CTRL1_6", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_WW4B2_14", + "CMT_LR_LOWER_B_MMCM_DO0", + "CMT_TOP_WW4A1_14", + "CMT_TOP_EE4A0_8", + "CMT_TOP_SE4C1_3", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_IMUX8_5", + "CMT_TOP_IMUX9_1", + "CMT_TOP_IMUX20_14", + "CMT_TOP_EE4BEG2_13", + "CMT_TOP_WW4A0_9", + "CMT_TOP_IMUX30_13", + "CMT_TOP_WR1END1_15", + "CMT_LR_LOWER_B_MMCM_DO8", + "CMT_TOP_EE4A3_8", + "CMT_TOP_IMUX37_5", + "CMT_LR_LOWER_B_MMCM_DO3", + "CMT_TOP_SW4A1_12", + "CMT_TOP_IMUX11_10", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX44_2", + "CMT_TOP_IMUX28_6", + "CMT_TOP_NW4A0_7", + "CMT_TOP_IMUX32_14", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_IMUX40_10", + "CMT_TOP_EE2A2_12", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_IMUX32_13", + "CMT_TOP_IMUX23_14", + "CMT_TOP_WW2END2_14", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_CLK0_1", + "CMT_TOP_SW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX23_1", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_LH3_14", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_WW2END1_6", + "CMT_TOP_SW2A0_1", + "CMT_TOP_CTRL1_3", + "CMT_TOP_IMUX10_7", + "CMT_TOP_LOGIC_OUTS_L_B20_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT1", + "CMT_TOP_NE4C2_8", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_WW2A0_13", + "CMT_TOP_BYP3_15", + "CMT_TOP_IMUX6_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_LOGIC_OUTS_L_B15_15", + "CMT_TOP_NW2A3_4", + "CMT_TOP_WR1END2_9", + "CMT_TOP_IMUX27_8", + "CMT_TOP_LH6_3", + "CMT_TOP_NE2A1_1", + "CMT_TOP_CLK0_9", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_BYP0_9", + "CMT_TOP_EE2A2_9", + "CMT_TOP_IMUX39_14", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_SW2A2_12", + "CMT_TOP_IMUX38_13", + "CMT_TOP_WW2END1_1", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_EE2A0_4", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_LOGIC_OUTS_L_B21_14", + "CMT_TOP_FAN1_7", + "CMT_TOP_LH12_15", + "CMT_TOP_WW4A3_3", + "CMT_TOP_IMUX19_15", + "CMT_TOP_NW4END3_2", + "CMT_TOP_SW4END2_1", + "CMT_TOP_EE4A3_3", + "CMT_R_LOWER_B_CLK_IN3_INT", + "CMT_TOP_EE4A1_0", + "CMT_TOP_SW4A2_9", + "CMT_TOP_IMUX33_15", + "CMT_TOP_LH3_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_IMUX41_0", + "CMT_TOP_IMUX32_6", + "CMT_TOP_WR1END3_4", + "CMT_TOP_BYP7_12", + "CMT_TOP_SW2A1_11", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_LOGIC_OUTS_L_B20_14", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX11_7", + "CMT_TOP_SW2A2_5", + "CMT_TOP_FAN5_0", + "CMT_TOP_WW2END2_7", + "CMT_TOP_NW4A2_10", + "CMT_TOP_SW4END1_8", + "CMT_TOP_EL1BEG2_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT34", + "CMT_TOP_BYP1_4", + "CMT_TOP_IMUX17_4", + "CMT_TOP_WR1END0_12", + "CMT_TOP_WW2A1_8", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_IMUX4_10", + "CMT_TOP_FAN6_9", + "CMT_TOP_NW2A3_15", + "CMT_TOP_BYP1_14", + "CMT_TOP_NW2A2_0", + "CMT_TOP_IMUX11_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_IMUX21_12", + "CMT_TOP_EL1BEG0_15", + "CMT_TOP_WW2A3_9", + "CMT_TOP_WW4B3_11", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_LOGIC_OUTS_L_B5_15", + "CMT_TOP_SE2A1_14", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_WL1END1_13", + "CMT_TOP_LOGIC_OUTS_L_B18_12", + "CMT_TOP_WW4END2_3", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_WW4END0_7", + "CMT_TOP_IMUX7_15", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_BYP7_15", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_LH6_10", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4END1_12", + "CMT_TOP_IMUX41_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_NE2A2_6", + "CMT_TOP_IMUX37_2", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WR1END1_7", + "CMT_TOP_IMUX14_9", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_IMUX7_2", + "CMT_TOP_FAN2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_TOP_WW4A0_7", + "CMT_TOP_EE4C0_8", + "CMT_TOP_EE4BEG3_15", + "CMT_TOP_WR1END0_14", + "CMT_TOP_SE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_CTRL0_13", + "CMT_TOP_WR1END3_8", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_IMUX37_1", + "CMT_TOP_NW2A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_12", + "CMT_TOP_EL1BEG0_4", + "CMT_R_LOWER_B_CLK_PERF1", + "CMT_TOP_WW4A3_13", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX7_12", + "CMT_TOP_NW2A2_3", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A2_6", + "CMT_TOP_EE4C0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_FAN3_11", + "CMT_TOP_SW4END0_0", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_NE4C3_11", + "CMT_TOP_IMUX37_6", + "CMT_TOP_BYP5_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_LH8_4", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SE4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_IMUX46_5", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_LH8_8", + "CMT_TOP_NE4C3_9", + "CMT_TOP_WW4B1_1", + "CMT_TOP_BLOCK_OUTS_L_B2_12", + "CMT_LR_LOWER_B_MMCM_DADDR5", + "CMT_TOP_OCLK1X_90_14", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX26_10", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_IMUX2_3", + "CMT_R_LOWER_B_CLK_MMCM10", + "CMT_TOP_EE2A3_3", + "CMT_TOP_IMUX36_4", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SW2A0_3", + "CMT_TOP_LOGIC_OUTS_L_B13_13", + "CMT_TOP_EE4A1_10", + "CMT_TOP_SW2A3_8", + "CMT_TOP_WW2A2_5", + "CMT_TOP_IMUX24_11", + "CMT_TOP_SW2A2_9", + "CMT_TOP_FAN5_12", + "CMT_TOP_SW4A0_6", + "CMT_TOP_IMUX38_6", + "CMT_TOP_NW4A0_14", + "CMT_TOP_WR1END0_5", + "CMT_TOP_IMUX4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_CTRL0_11", + "CMT_TOP_IMUX19_8", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_IMUX36_5", + "CMT_TOP_WW2A0_3", + "CMT_TOP_BYP6_14", + "CMT_TOP_LH10_5", + "CMT_TOP_BYP6_15", + "CMT_TOP_NE4C3_3", + "CMT_TOP_FAN7_2", + "CMT_TOP_IMUX7_10", + "CMT_TOP_SE4BEG2_14", + "CMT_TOP_WW4B1_11", + "CMT_TOP_BYP6_1", + "CMT_TOP_WL1END2_1", + "CMT_TOP_SW4A0_2", + "CMT_TOP_IMUX10_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_LH12_13", + "CMT_TOP_OCLK_10", + "CMT_TOP_LH5_2", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_SW2A2_6", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_NW4END3_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT49", + "CMT_TOP_NW4END3_8", + "CMT_TOP_WL1END3_13", + "CMT_TOP_WL1END0_7", + "CMT_TOP_IMUX35_15", + "CMT_TOP_IMUX10_11", + "CMT_TOP_SE4C1_15", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX9_7", + "CMT_TOP_BYP5_7", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_NW4END3_13", + "CMT_TOP_EE2A3_13", + "CMT_TOP_SW2A1_6", + "CMT_TOP_IMUX13_13", + "CMT_TOP_IMUX12_14", + "CMT_TOP_IMUX18_11", + "CMT_TOP_IMUX37_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_LOGIC_OUTS_L_B18_13", + "CMT_TOP_EE4B2_8", + "CMT_TOP_WW2A1_10", + "CMT_TOP_LH11_13", + "CMT_TOP_IMUX42_5", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_IMUX22_12", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LH8_10", + "CMT_TOP_MONITOR_N_15", + "CMT_R_LOWER_B_CLK_FREQ_BB2", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_LR_LOWER_B_MMCM_TESTIN24", + "CMT_TOP_IMUX24_5", + "CMT_TOP_NW2A2_10", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_SW2A2_8", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN1_12", + "CMT_TOP_FAN5_6", + "CMT_TOP_LOGIC_OUTS_L_B20_15", + "CMT_TOP_FAN3_3", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_EE2A1_3", + "CMT_TOP_IMUX24_9", + "CMT_TOP_SE2A2_2", + "CMT_TOP_IMUX25_10", + "CMT_LR_LOWER_B_MMCM_DO7", + "CMT_TOP_SE4C3_0", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_EE2A1_7", + "CMT_TOP_BYP7_13", + "CMT_TOP_WL1END2_13", + "CMT_TOP_IMUX45_6", + "CMT_TOP_SW4END0_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX3_8", + "CMT_TOP_WW2END2_12", + "CMT_TOP_WR1END2_12", + "CMT_TOP_WW2END1_9", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_LH6_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT11", + "CMT_TOP_OCLK_11", + "CMT_TOP_BYP1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_SW4A1_4", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_IMUX40_9", + "CMT_TOP_IMUX25_11", + "CMT_TOP_LH10_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_SE4C2_12", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_WW4END3_3", + "CMT_TOP_WW4B3_2", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_FAN3_0", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_WW4B3_12", + "CMT_TOP_IMUX32_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_EE4A0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4END0_12", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_FAN0_11", + "CMT_TOP_SE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_IMUX44_4", + "CMT_TOP_SW4A2_11", + "CMT_TOP_SW4END0_9", + "CMT_TOP_EE4C1_5", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_IMUX29_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT13", + "CMT_LR_LOWER_B_MMCM_DO4", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX32_0", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_LOGIC_OUTS_L_B3_14", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_SW4END2_3", + "CMT_TOP_BYP4_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_FAN5_4", + "CMT_TOP_EE2A2_2", + "CMT_TOP_EE4A2_1", + "CMT_TOP_EE2A2_11", + "CMT_TOP_NW4A2_11", + "CMT_TOP_IMUX43_15", + "CMT_TOP_ICLKDIV_13", + "CMT_TOP_NW4END3_10", + "CMT_TOP_OCLK1X_90_12", + "CMT_TOP_WW4END0_8", + "CMT_TOP_SW4END1_15", + "CMT_TOP_LH11_8", + "CMT_TOP_IMUX45_5", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WR1END0_6", + "CMT_TOP_IMUX20_15", + "CMT_TOP_SW4A3_13", + "CMT_TOP_IMUX3_1", + "CMT_TOP_IMUX10_12", + "CMT_TOP_WW4END3_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_IMUX16_2", + "CMT_TOP_IMUX34_10", + "CMT_TOP_FAN4_4", + "CMT_TOP_FAN7_3", + "CMT_LR_LOWER_B_MMCM_DADDR1", + "CMT_TOP_IMUX15_14", + "CMT_TOP_NW4END2_13", + "CMT_TOP_LH4_0", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_NE2A3_13", + "CMT_TOP_FAN3_9", + "CMT_TOP_FAN0_15", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_IMUX22_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_WL1END1_14", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_EE4C3_6", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_BYP1_10", + "CMT_TOP_FAN7_0", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_FAN2_9", + "CMT_TOP_WW2A0_11", + "CMT_TOP_SW4A1_2", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_IMUX4_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_IMUX26_2", + "CMT_TOP_WW2END0_14", + "CMT_TOP_BYP5_11", + "CMT_TOP_IMUX33_14", + "CMT_TOP_BYP2_10", + "CMT_TOP_FAN1_8", + "CMT_TOP_LH8_11", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_IMUX11_8", + "CMT_TOP_SE4C2_10", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX5_6", + "CMT_TOP_IMUX38_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT6", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_SE4BEG1_14", + "CMT_TOP_LH2_10", + "CMT_TOP_CLK1_7", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4B3_1", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_IMUX16_5", + "CMT_TOP_CLK1_4", + "CMT_TOP_LH8_3", + "CMT_TOP_LH7_13", + "CMT_TOP_IMUX22_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_NE4BEG0_13", + "CMT_TOP_IMUX45_2", + "CMT_TOP_LH4_12", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_NE4C0_11", + "CMT_TOP_EE4B1_2", + "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "CMT_TOP_IMUX15_10", + "CMT_TOP_NE2A3_14", + "CMT_TOP_WW4C0_0", + "CMT_TOP_SW2A1_7", + "CMT_TOP_EE4C3_13", + "CMT_TOP_BYP2_4", + "CMT_TOP_EE4B3_1", + "CMT_TOP_SE4C3_3", + "CMT_TOP_WW4END1_9", + "CMT_TOP_IMUX47_13", + "CMT_TOP_EE4B1_12", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_SW4END1_4", + "CMT_TOP_IMUX31_14", + "CMT_TOP_IMUX12_12", + "CMT_TOP_NE4BEG2_3", + "CMT_LR_LOWER_B_MMCM_DO15", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_WW2A0_7", + "CMT_TOP_IMUX34_7", + "CMT_TOP_EE4A0_14", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_WW2A2_12", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX27_4", + "CMT_TOP_OCLK_1", + "CMT_TOP_NW4END0_2", + "CMT_TOP_EE2A1_5", + "CMT_TOP_FAN4_2", + "CMT_TOP_CTRL1_11", + "CMT_LR_LOWER_B_MMCM_DADDR0", + "CMT_TOP_WW4C3_8", + "CMT_TOP_NW4END1_1", + "CMT_TOP_FAN3_1", + "CMT_TOP_IMUX45_9", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_IMUX37_14", + "CMT_TOP_SW4END2_11", + "CMT_LR_LOWER_B_MMCM_TESTIN4", + "CMT_TOP_SE2A2_5", + "CMT_TOP_WR1END2_6", + "CMT_TOP_IMUX15_13", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_IMUX45_13", + "CMT_TOP_IMUX24_14", + "CMT_TOP_NW2A0_15", + "CMT_TOP_FAN2_7", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW2END2_11", + "CMT_TOP_OCLK_15", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_SW4A3_1", + "CMT_TOP_NE2A2_12", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX42_6", + "CMT_TOP_SW4END3_13", + "CMT_TOP_EE4B1_1", + "CMT_TOP_BYP0_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_NW4END0_13", + "CMT_TOP_IMUX44_15", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_IMUX10_13", + "CMT_TOP_CLK1_11", + "CMT_LR_LOWER_B_MMCM_DI2", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_EE4C3_11", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_IMUX32_10", + "CMT_TOP_IMUX25_13", + "CMT_TOP_IMUX2_14", + "CMT_TOP_NW4A0_4", + "CMT_TOP_IMUX23_15", + "CMT_TOP_EL1BEG2_12", + "CMT_TOP_SW4A3_10", + "CMT_TOP_OCLKDIV_15", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_NW4END2_8", + "CMT_TOP_SE2A3_12", + "CMT_LR_LOWER_B_MMCM_TESTIN23", + "CMT_TOP_EE2A0_10", + "CMT_TOP_EE2A3_9", + "CMT_TOP_SW2A2_14", + "CMT_TOP_LOGIC_OUTS_L_B0_13", + "CMT_TOP_SW2A1_1", + "CMT_TOP_EE4B2_4", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_WW2A3_14", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX18_0", + "CMT_TOP_LOGIC_OUTS_L_B3_15", + "CMT_TOP_EE4C3_14", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_BYP6_4", + "CMT_TOP_NW4END1_6", + "CMT_TOP_NW4A3_13", + "CMT_TOP_IMUX7_14", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_LH7_4", + "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "CMT_TOP_IMUX42_14", + "CMT_TOP_IMUX23_0", + "CMT_TOP_NW4END3_15", + "CMT_TOP_IMUX43_8", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX21_4", + "CMT_TOP_IMUX21_2", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_EE4A2_9", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE4B0_5", + "CMT_TOP_IMUX47_10", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_6", + "CMT_TOP_EE2BEG0_14", + "CMT_TOP_WW4C0_1", + "CMT_TOP_WW2A3_0", + "CMT_TOP_FAN7_1", + "CMT_TOP_MONITOR_P_12", + "CMT_TOP_IMUX46_13", + "CMT_TOP_WL1END1_15", + "CMT_TOP_NW2A1_3", + "CMT_LR_LOWER_B_MMCM_TESTOUT45", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_IMUX18_14", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_EE4A2_13", + "CMT_TOP_WW2END3_13", + "CMT_TOP_LH1_10", + "CMT_TOP_EE4BEG2_12", + "CMT_TOP_BYP1_15", + "CMT_TOP_NW4END3_14", + "CMT_TOP_EE4B0_10", + "CMT_TOP_SE2A3_2", + "CMT_TOP_IMUX16_6", + "CMT_TOP_IMUX11_13", + "CMT_TOP_IMUX1_5", + "CMT_LR_LOWER_B_MMCM_DI0", + "CMT_LR_LOWER_B_MMCM_TESTIN28", + "CMT_TOP_IMUX5_15", + "CMT_TOP_SE4C1_4", + "CMT_MMCM_PHASERA_DQSBUS1", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_LH1_14", + "CMT_TOP_NW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_EE4B3_5", + "CMT_TOP_IMUX26_7", + "CMT_TOP_NE4C1_0", + "CMT_TOP_EE2A3_8", + "CMT_R_LOWER_B_CLK_MMCM1", + "CMT_TOP_IMUX45_11", + "CMT_TOP_FAN4_12", + "CMT_TOP_ER1BEG2_12", + "CMT_TOP_WW4B2_4", + "CMT_TOP_BYP2_14", + "CMT_TOP_IMUX40_0", + "CMT_TOP_IMUX14_6", + "CMT_TOP_NW2A3_0", + "CMT_MMCM_PHASERA_CTSBUS0", + "CMT_TOP_EE4A0_2", + "CMT_TOP_BYP2_15", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_EE4B0_15", + "CMT_TOP_EE2A1_15", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_NW4END3_11", + "CMT_TOP_IMUX8_7", + "CMT_TOP_WW2END0_4", + "CMT_TOP_SW4A1_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_LH10_7", + "CMT_TOP_EE4C2_3", + "CMT_TOP_SE2A3_9", + "CMT_TOP_IMUX1_12", + "CMT_TOP_EL1BEG3_3", + "CMT_LR_LOWER_B_MMCM_DI6", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_11", + "CMT_TOP_IMUX20_13", + "CMT_TOP_EE2A1_11", + "CMT_LR_LOWER_B_MMCM_TESTIN20", + "CMT_TOP_WW4C1_12", + "CMT_TOP_SE2A1_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_SE2A0_13", + "CMT_TOP_WR1END0_0", + "CMT_TOP_WW2A1_9", + "CMT_MMCM_PHASERREF_BELOW0", + "CMT_TOP_FAN1_11", + "CMT_TOP_IMUX18_4", + "CMT_TOP_WL1END1_5", + "CMT_TOP_SW4A1_13", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_IMUX39_13", + "CMT_TOP_NE2A2_3", + "CMT_TOP_NE4BEG1_13", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_WW4END1_3", + "CMT_TOP_IMUX24_1", + "CMT_TOP_WW2END2_6", + "CMT_TOP_SE2A2_13", + "CMT_TOP_WW2A2_11", + "CMT_TOP_SW2A0_10", + "CMT_TOP_EE2A3_0", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_WW2A3_7", + "CMT_TOP_WL1END2_0", + "CMT_TOP_IMUX9_14", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_EE4B3_14", + "CMT_TOP_SW2A0_6", + "CMT_TOP_LOGIC_OUTS_L_B5_12", + "CMT_TOP_NW4A3_9", + "CMT_TOP_IMUX13_11", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_IMUX6_0", + "CMT_TOP_NW2A0_1", + "CMT_TOP_LH1_11", + "CMT_TOP_NW2A2_6", + "CMT_TOP_CTRL0_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT39", + "CMT_TOP_WR1END1_3", + "CMT_TOP_WW4A2_13", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX43_0", + "CMT_TOP_SE2A1_11", + "CMT_TOP_LH9_13", + "CMT_TOP_LOGIC_OUTS_L_B2_14", + "CMT_TOP_ER1BEG1_15", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4C3_0", + "CMT_TOP_LH11_1", + "CMT_TOP_SW2A1_8", + "CMT_TOP_EE4C3_4", + "CMT_TOP_NW4A3_11", + "CMT_TOP_ER1BEG3_8", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN7_4", + "CMT_TOP_NW4END0_4", + "CMT_TOP_FAN1_6", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_IMUX22_10", + "CMT_TOP_WW4B2_5", + "CMT_TOP_OCLK_14", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C1_4", + "CMT_TOP_IMUX20_4", + "CMT_TOP_WW2A2_1", + "CMT_TOP_WR1END1_11", + "CMT_TOP_IMUX18_12", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_12", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WR1END3_10", + "CMT_TOP_WW4A1_6", + "CMT_TOP_BYP7_11", + "CMT_TOP_WL1END2_15", + "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_NW2A1_12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_WW4B0_9", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX41_12", + "CMT_TOP_IMUX1_15", + "CMT_TOP_IMUX0_4", + "CMT_TOP_SE2A3_11", + "CMT_TOP_WW2A2_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT57", + "CMT_TOP_WR1END0_7", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_IMUX20_3", + "CMT_TOP_CTRL1_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EE4A2_5", + "CMT_TOP_SE4C1_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_IMUX27_12", + "CMT_TOP_NW4END0_0", + "CMT_TOP_NW4A3_10", + "CMT_LR_LOWER_B_MMCM_TESTIN31", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX12_2", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_LOGIC_OUTS_L_B0_14", + "CMT_TOP_NW4A3_8", + "CMT_TOP_WW4B0_2", + "CMT_TOP_NE2A0_7", + "CMT_TOP_IMUX34_5", + "CMT_TOP_EE4C2_12", + "CMT_TOP_SE4C3_13", + "CMT_TOP_EE4C2_5", + "CMT_TOP_WL1END2_2", + "CMT_TOP_IMUX6_3", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_IMUX12_13", + "CMT_TOP_ER1BEG3_15", + "CMT_TOP_IMUX35_7", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_IMUX28_10", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_IMUX2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_CTRL0_10", + "CMT_TOP_IMUX46_12", + "CMT_TOP_WW4END2_2", + "CMT_TOP_WL1END0_8", + "CMT_TOP_IMUX39_15", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_IMUX47_6", + "CMT_TOP_BYP1_12", + "CMT_TOP_IMUX23_2", + "CMT_TOP_LOGIC_OUTS_L_B15_13", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_WL1END0_9", + "CMT_TOP_IMUX39_6", + "CMT_TOP_EE4A3_12", + "CMT_TOP_IMUX2_12", + "CMT_TOP_EE4C0_10", + "CMT_TOP_IMUX6_4", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_IMUX12_3", + "CMT_TOP_LH8_2", + "CMT_TOP_EE2A3_15", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4A2_12", + "CMT_TOP_BYP2_5", + "CMT_TOP_NW2A0_10", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX38_8", + "CMT_TOP_IMUX0_6", + "CMT_TOP_NE4BEG3_11", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SE2A0_8", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NE2A0_1", + "CMT_LR_LOWER_B_MMCM_DADDR6", + "CMT_TOP_IMUX31_4", + "CMT_LR_LOWER_B_MMCM_DO14", + "CMT_LR_LOWER_B_MMCM_TESTOUT37", + "CMT_TOP_IMUX0_14", + "CMT_MMCM_PHASERA_CTSBUS1", + "CMT_TOP_NE2A3_9", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX5_1", + "CMT_TOP_IMUX47_2", + "CMT_TOP_LH12_1", + "CMT_TOP_SW2A3_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_SE4BEG0_14", + "CMT_TOP_WW2END3_6", + "CMT_TOP_NW2A0_8", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_IMUX44_3", + "CMT_TOP_LH3_4", + "CMT_TOP_EE2A2_1", + "CMT_TOP_WW4A2_3", + "CMT_TOP_IMUX27_15", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EL1BEG1_12", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX39_8", + "CMT_TOP_SW4END2_7", + "CMT_TOP_FAN2_4", + "CMT_TOP_EE4A1_6", + "CMT_TOP_EE4B1_3", + "CMT_TOP_WW2A2_9", + "CMT_TOP_IMUX42_10", + "CMT_TOP_IMUX22_14", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_NE4BEG1_15", + "CMT_TOP_WW4END0_1", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE4B1_0", + "CMT_TOP_IMUX34_11", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_SW4END3_15", + "CMT_TOP_IMUX10_3", + "CMT_TOP_IMUX47_15", + "CMT_TOP_WL1END3_2", + "CMT_LR_LOWER_B_MMCM_TESTIN14", + "CMT_TOP_NW4A2_8", + "CMT_TOP_LOGIC_OUTS_L_B19_14", + "CMT_TOP_IMUX35_5", + "CMT_TOP_WW4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_NE4C3_2", + "CMT_TOP_NE2A3_8", + "CMT_TOP_WW4END3_4", + "CMT_TOP_LH1_1", + "CMT_TOP_CTRL1_5", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_LH7_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_CLK0_8", + "CMT_TOP_NE2A0_5", + "CMT_TOP_SW4END2_6", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_EE4C3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_13", + "CMT_TOP_IMUX8_8", + "CMT_TOP_NE4C2_14", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_WR1END0_13", + "CMT_TOP_WW2A1_14", + "CMT_TOP_EE2A2_4", + "CMT_TOP_NE2A3_5", + "CMT_TOP_IMUX13_1", + "CMT_TOP_WW2END1_15", + "CMT_TOP_IMUX8_14", + "CMT_TOP_WW2END0_3", + "CMT_TOP_EE4C1_13", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_EE4A2_0", + "CMT_TOP_EE4C1_3", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_ER1BEG3_12", + "CMT_TOP_NE4C2_9", + "CMT_LR_LOWER_B_MMCM_DO5", + "CMT_TOP_EE2BEG3_12", + "CMT_TOP_NW2A2_4", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX37_3", + "CMT_TOP_IMUX37_8", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_IMUX2_13", + "CMT_TOP_LOGIC_OUTS_L_B9_12", + "CMT_TOP_NW4END2_14", + "CMT_TOP_CTRL1_2", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B4_15", + "CMT_TOP_BYP1_13", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_NE4BEG1_12", + "CMT_TOP_EE4B0_0", + "CMT_TOP_SE2A0_0", + "CMT_TOP_IMUX18_9", + "CMT_TOP_WW2END3_15", + "CMT_TOP_ICLKDIV_14", + "CMT_TOP_LH7_14", + "CMT_TOP_WW4B1_15", + "CMT_TOP_WW2END3_12", + "CMT_TOP_WW2END1_13", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4A3_9", + "CMT_TOP_IMUX3_2", + "CMT_TOP_SE2A1_7", + "CMT_TOP_BLOCK_OUTS_L_B0_13", + "CMT_TOP_WW4END1_0", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_IMUX8_13", + "CMT_TOP_WW2END3_14", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_WW4A1_15", + "CMT_LR_LOWER_B_MMCM_RST", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_NW4END2_6", + "CMT_TOP_IMUX34_1", + "CMT_TOP_LH6_9", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW4A2_1", + "CMT_TOP_SW4A2_4", + "CMT_TOP_LOGIC_OUTS_L_B23_15", + "CMT_TOP_IMUX21_15", + "CMT_TOP_NE4C2_11", + "MMCM_CLK_FREQ_BB_NS2", + "CMT_TOP_WW4END1_10", + "CMT_TOP_LH9_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_NE4C3_6", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WW2END3_1", + "CMT_TOP_BYP4_3", + "CMT_TOP_IMUX3_15", + "CMT_TOP_WW2END2_10", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_SE2A0_7", + "CMT_TOP_IMUX35_11", + "CMT_TOP_WW2END2_2", + "CMT_TOP_BYP7_5", + "CMT_TOP_SW4END0_11", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX45_12", + "CMT_TOP_SW2A1_2", + "CMT_TOP_EE4B1_6", + "CMT_TOP_WW2END0_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_EE4BEG1_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT15", + "CMT_TOP_NE4C1_14", + "CMT_TOP_EE2A2_14", + "CMT_MMCM_PHASERREF1", + "CMT_TOP_BYP5_0", + "CMT_TOP_IMUX32_9", + "CMT_TOP_EE2A0_12", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX38_10", + "CMT_TOP_LH1_4", + "CMT_TOP_IMUX13_15", + "CMT_TOP_NW4A0_6", + "CMT_TOP_LOGIC_OUTS_L_B10_15", + "CMT_TOP_WW4END3_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT31", + "CMT_TOP_EE4C2_2", + "CMT_TOP_CLK1_10", + "CMT_TOP_WW2A3_13", + "CMT_TOP_WL1END3_11", + "CMT_TOP_IMUX30_14", + "CMT_TOP_IMUX29_15", + "CMT_TOP_SE4C0_13", + "CMT_TOP_NW4A0_12", + "CMT_TOP_WW2END3_4", + "CMT_TOP_WW4C1_8", + "CMT_TOP_IMUX39_10", + "CMT_TOP_WR1END1_8", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_WW4END3_10", + "CMT_TOP_SE2A2_14", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4C3_10", + "CMT_TOP_EE4B3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_EE4B3_7", + "CMT_TOP_NW4END0_7", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SW4A1_10", + "CMT_TOP_LH4_6", + "CMT_TOP_NW4END1_14", + "CMT_TOP_WW4C2_14", + "CMT_TOP_IMUX22_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT44", + "CMT_TOP_NW2A2_5", + "CMT_TOP_LH7_3", + "CMT_TOP_IMUX20_1", + "CMT_TOP_WW4B1_3", + "CMT_TOP_FAN5_8", + "CMT_TOP_LOGIC_OUTS_L_B7_14", + "CMT_TOP_SE2A1_9", + "CMT_TOP_OCLK_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT10", + "CMT_TOP_SE4C2_0", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_FAN2_15", + "CMT_TOP_WW2A0_2", + "CMT_TOP_IMUX11_5", + "CMT_TOP_SW4END3_14", + "CMT_TOP_IMUX44_11", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_WW4A1_5", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX43_2", + "CMT_TOP_LH12_5", + "CMT_TOP_LOGIC_OUTS_L_B3_12", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_OCLK1X_90_13", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_IMUX46_1", + "CMT_TOP_EE4C2_6", + "CMT_TOP_WW4C3_1", + "CMT_TOP_WW2A1_13", + "CMT_TOP_ICLK_1", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B5_14", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_IMUX42_1", + "CMT_TOP_BYP7_6", + "CMT_TOP_NW4END1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_LH4_13", + "CMT_TOP_NE4C1_15", + "CMT_TOP_NW4A3_2", + "CMT_TOP_SW4A0_5", + "CMT_TOP_IMUX4_6", + "CMT_TOP_CLK0_12", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_NE4BEG3_13", + "CMT_TOP_WW4END0_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_IMUX3_6", + "CMT_TOP_SE4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_WW2A3_1", + "CMT_TOP_WW4C3_15", + "CMT_TOP_IMUX35_3", + "CMT_TOP_SW4END0_10", + "CMT_TOP_LH12_2", + "CMT_TOP_LH2_13", + "CMT_TOP_IMUX0_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WW4END2_6", + "CMT_TOP_NW4END1_15", + "CMT_TOP_LH11_7", + "CMT_TOP_SW4END3_3", + "CMT_TOP_SW2A3_13", + "CMT_TOP_IMUX46_14", + "CMT_TOP_IMUX28_12", + "CMT_TOP_WW4B1_12", + "CMT_TOP_NW4A1_7", + "CMT_TOP_BYP4_14", + "CMT_R_LOWER_B_CLK_MMCM13", + "CMT_TOP_WW2A3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_NE2A1_13", + "CMT_TOP_IMUX47_14", + "CMT_TOP_IMUX19_6", + "CMT_TOP_ER1BEG0_15", + "CMT_TOP_FAN4_8", + "CMT_TOP_EE2A2_3", + "CMT_TOP_IMUX34_3", + "CMT_TOP_WW4END1_11", + "CMT_TOP_NW2A2_15", + "CMT_TOP_CLK0_7", + "CMT_TOP_FAN7_14", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4C3_14", + "CMT_TOP_SE4C3_7", + "CMT_TOP_WW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_IMUX35_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_MONITOR_P_13", + "CMT_TOP_IMUX10_0", + "CMT_TOP_LH11_3", + "CMT_TOP_SE2A0_9", + "CMT_TOP_SW4A2_15", + "CMT_TOP_WL1END3_7", + "CMT_TOP_IMUX34_8", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WR1END3_3", + "CMT_TOP_IMUX46_4", + "CMT_TOP_SE2A2_10", + "CMT_TOP_WW4C2_4", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_IMUX22_0", + "CMT_TOP_IMUX9_11", + "CMT_TOP_WW4A2_9", + "CMT_TOP_SE4C1_0", + "CMT_R_LOWER_B_CLK_MMCM5", + "CMT_TOP_IMUX14_5", + "CMT_TOP_WL1END2_9", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_EE4C1_1", + "CMT_TOP_NW4A0_11", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX13_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_SE4C2_3", + "CMT_TOP_BYP3_13", + "CMT_TOP_WW4END0_12", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_EE4BEG2_15", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX27_5", + "CMT_TOP_OCLK_0", + "CMT_TOP_LH7_8", + "CMT_TOP_IMUX7_8", + "CMT_TOP_ICLK_0", + "CMT_TOP_NE4C0_13", + "CMT_LR_LOWER_B_MMCM_DO1", + "CMT_TOP_WW2END2_3", + "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "CMT_TOP_WR1END0_10", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END1_5", + "CMT_TOP_IMUX44_6", + "CMT_TOP_EE4B1_14", + "CMT_TOP_IMUX22_3", + "CMT_TOP_NE4C2_4", + "CMT_TOP_IMUX8_12", + "CMT_TOP_WL1END1_2", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_CTRL1_13", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX30_12", + "CMT_TOP_SE4C3_6", + "CMT_TOP_LH9_10", + "CMT_TOP_SE4C1_14", + "CMT_TOP_EE4C0_12", + "CMT_TOP_EE4C0_15", + "CMT_TOP_NW2A1_10", + "CMT_TOP_SW4A3_8", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW2A2_0", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX13_3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX28_4", + "CMT_R_LOWER_B_CLK_IN3_HCLK", + "CMT_TOP_WW4END0_15", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH1_8", + "CMT_TOP_LH10_10", + "CMT_TOP_IMUX42_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_BYP0_13", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_IMUX3_12", + "CMT_TOP_WL1END1_1", + "CMT_TOP_IMUX40_14", + "CMT_TOP_SE4BEG1_15", + "CMT_TOP_LH2_14", + "CMT_TOP_IMUX10_15", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_EE2A1_12", + "CMT_TOP_IMUX3_10", + "CMT_TOP_NE4BEG0_14", + "CMT_TOP_OCLK_12", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_WW2END2_8", + "CMT_TOP_EE2A0_15", + "CMT_TOP_EE2A0_8", + "CMT_TOP_LH7_1", + "CMT_TOP_SW2A3_5", + "CMT_TOP_IMUX31_11", + "CMT_TOP_IMUX5_14", + "CMT_TOP_IMUX32_12", + "CMT_LR_LOWER_B_MMCM_DI10", + "CMT_TOP_IMUX19_3", + "CMT_TOP_NW4END2_12", + "CMT_TOP_FAN0_7", + "CMT_R_LOWER_B_CLK_FREQ_BB3", + "CMT_TOP_WW2END1_4", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_NW4END3_7", + "CMT_TOP_NE4C3_14", + "CMT_TOP_EE2A3_12", + "CMT_TOP_CLK1_2", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_IMUX13_14", + "CMT_TOP_IMUX34_9", + "CMT_TOP_ICLK_14", + "CMT_TOP_EE4B0_6", + "CMT_TOP_EE4B2_5", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW4C2_9", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_WW2A2_2", + "CMT_TOP_SW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_12", + "CMT_TOP_NE2A3_2", + "CMT_TOP_IMUX43_1", + "CMT_TOP_WW4END2_10", + "CMT_TOP_EE4C1_4", + "CMT_R_LOWER_B_CLK_IN1_HCLK", + "CMT_TOP_IMUX44_9", + "CMT_TOP_WW4B1_6", + "CMT_TOP_NW4A1_11", + "CMT_TOP_IMUX42_0", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_IMUX18_13", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_IMUX24_7", + "CMT_TOP_EE4B0_12", + "CMT_LR_LOWER_B_MMCM_DI12", + "CMT_TOP_IMUX47_4", + "CMT_TOP_WW4END2_15", + "CMT_TOP_WL1END1_12", + "CMT_TOP_NE2A1_2", + "CMT_MMCM_PHASERREF0", + "CMT_TOP_IMUX39_4", + "CMT_TOP_BYP5_2", + "CMT_TOP_EL1BEG2_14", + "CMT_TOP_FAN7_8", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EL1BEG1_13", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_SW2A1_10", + "CMT_TOP_BYP4_15", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_LH7_15", + "CMT_TOP_IMUX33_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT52", + "CMT_TOP_NE4C1_1", + "CMT_TOP_NE4C3_8", + "CMT_TOP_EE4A3_10", + "CMT_TOP_IMUX28_3", + "CMT_TOP_BYP7_14", + "CMT_TOP_IMUX1_4", + "CMT_TOP_IMUX13_4", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_EE4B2_12", + "CMT_TOP_SW4END0_13", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_SW4END0_12", + "CMT_TOP_EE4B1_8", + "CMT_TOP_NE4BEG0_12", + "CMT_TOP_SW4A1_9", + "CMT_TOP_SE4C2_8", + "CMT_TOP_LH1_5", + "CMT_TOP_IMUX10_14", + "CMT_TOP_WW4END3_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_WW2END3_3", + "CMT_TOP_EE4BEG3_13", + "CMT_TOP_NE2A2_14", + "CMT_TOP_WL1END3_12", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_NE4C0_2", + "CMT_TOP_IMUX44_12", + "CMT_TOP_FAN6_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_IMUX19_10", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_LH7_5", + "CMT_TOP_WW4A2_15", + "CMT_TOP_LOGIC_OUTS_L_B1_12", + "CMT_TOP_IMUX19_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_FAN0_2", + "CMT_TOP_FAN6_0", + "CMT_TOP_IMUX47_5", + "CMT_TOP_IMUX27_3", + "CMT_TOP_IMUX24_0", + "CMT_TOP_IMUX26_0", + "CMT_TOP_EL1BEG0_13", + "CMT_TOP_WR1END2_3", + "CMT_TOP_EE4A0_12", + "CMT_TOP_WR1END1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_NE4C0_6", + "CMT_TOP_EE4C0_0", + "CMT_TOP_LOGIC_OUTS_L_B7_13", + "CMT_TOP_IMUX21_14", + "CMT_TOP_LOGIC_OUTS_L_B16_13", + "CMT_TOP_EE2A3_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT62", + "CMT_TOP_SE4C1_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT17", + "CMT_TOP_EE2A0_2", + "CMT_LR_LOWER_B_MMCM_DO11", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_EE2A1_14", + "CMT_TOP_IMUX47_9", + "CMT_TOP_SE4C1_7", + "CMT_TOP_FAN0_10", + "CMT_TOP_EE2A3_4", + "CMT_TOP_IMUX45_7", + "CMT_TOP_ER1BEG2_10", + "CMT_TOP_IMUX13_0", + "CMT_TOP_WW2END1_10", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_IMUX29_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_IMUX33_9", + "CMT_TOP_SW4END3_1", + "CMT_TOP_IMUX26_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT33", + "CMT_TOP_IMUX5_5", + "CMT_TOP_NE4BEG3_12", + "CMT_TOP_SW4END2_13", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_NW4A1_9", + "CMT_TOP_WW2END0_11", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4C0_8", + "CMT_TOP_IMUX16_10", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_IMUX15_4", + "CMT_TOP_LH10_11", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_NW2A2_9", + "CMT_TOP_EE4B3_11", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_WW4A1_1", + "CMT_TOP_EE2A1_0", + "CMT_TOP_LH9_9", + "CMT_TOP_IMUX25_14", + "CMT_TOP_EE4B0_1", + "CMT_TOP_WL1END2_12", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_WW2END0_12", + "CMT_TOP_EE4B3_13", + "CMT_TOP_SE2A0_10", + "CMT_LR_LOWER_B_MMCM_DI7", + "CMT_TOP_BLOCK_OUTS_L_B1_15", + "CMT_TOP_BLOCK_OUTS_L_B3_12", + "CMT_TOP_NE4C2_3", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE2BEG0_12", + "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "CMT_TOP_CLK0_3", + "CMT_TOP_IMUX14_1", + "CMT_TOP_LH8_9", + "CMT_TOP_WW2A3_11", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_SE4C1_12", + "CMT_TOP_IMUX2_7", + "CMT_TOP_CLK1_6", + "CMT_TOP_LOGIC_OUTS_L_B8_15", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW4C3_6", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_EE4C0_4", + "CMT_TOP_IMUX28_8", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LH2_6", + "CMT_TOP_IMUX11_9", + "CMT_TOP_WW4A1_11", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "CMT_TOP_BYP4_8", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_MMCM_PHASER_IN_A_ICLK", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW2A0_4", + "CMT_TOP_EE2BEG2_15", + "CMT_TOP_NW4END3_9", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LH12_7", + "CMT_TOP_WW2END1_7", + "CMT_TOP_FAN0_13", + "CMT_TOP_LH6_2", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX45_8", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_EE2A0_3", + "CMT_TOP_BLOCK_OUTS_L_B1_13", + "CMT_TOP_WW4B0_10", + "CMT_TOP_WW4END3_14", + "CMT_TOP_WW2END1_14", + "CMT_TOP_SW4A0_13", + "CMT_TOP_IMUX33_4", + "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "CMT_TOP_BYP1_11", + "CMT_TOP_IMUX41_15", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_WL1END0_11", + "CMT_TOP_SW2A0_5", + "CMT_TOP_EE4C3_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT22", + "CMT_TOP_CLK1_13", + "CMT_TOP_IMUX35_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_WW2A3_10", + "CMT_TOP_LOGIC_OUTS_L_B2_13", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_EE4B0_13", + "CMT_TOP_NW4END1_7", + "CMT_MMCM_PHASERA_DQSBUS0", + "CMT_TOP_IMUX36_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_SW4END3_2", + "CMT_TOP_WL1END0_5", + "CMT_TOP_ER1BEG2_14", + "CMT_TOP_WW2A0_15", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_IMUX35_13", + "CMT_TOP_WW4END0_13", + "CMT_TOP_SW2A1_5", + "CMT_TOP_IMUX33_6", + "CMT_TOP_EE4C2_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT35", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_EE4B3_3", + "CMT_TOP_IMUX35_14", + "CMT_TOP_WW4A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_LH5_12", + "CMT_TOP_IMUX3_13", + "CMT_TOP_WW2END2_1", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_WW4END0_11", + "CMT_TOP_WR1END1_13", + "CMT_TOP_IMUX25_4", + "CMT_TOP_IMUX2_9", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_SW4END1_0", + "CMT_TOP_EE2A1_1", + "CMT_TOP_SE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_NE2A1_14", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_LOGIC_OUTS_L_B14_13", + "CMT_LR_LOWER_B_MMCM_PSEN", + "CMT_TOP_EE4A3_6", + "CMT_TOP_NE2A2_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT54", + "CMT_TOP_SE4C2_11", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_BYP2_11", + "CMT_TOP_WW4C3_13", + "CMT_TOP_BYP1_1", + "CMT_TOP_LH11_6", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_NW2A0_11", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WR1END0_3", + "CMT_MMCM_PHASER_OUT_B_OCLK1X_90", + "CMT_TOP_LOGIC_OUTS_L_B1_14", + "CMT_TOP_EE4A1_13", + "CMT_TOP_WW4B3_5", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_IMUX31_9", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_LR_LOWER_B_MMCM_DI5", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_BYP6_0", + "CMT_TOP_SW4END2_12", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_IMUX36_6", + "CMT_TOP_EE2A2_13", + "CMT_TOP_WR1END1_6", + "CMT_TOP_LOGIC_OUTS_L_B17_13", + "CMT_TOP_SE4C0_2", + "CMT_TOP_LH11_10", + "CMT_TOP_EE4A2_8", + "CMT_TOP_SE2A1_1", + "CMT_TOP_NW4END1_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_IMUX31_3", + "CMT_TOP_EE4C1_8", + "CMT_TOP_IMUX20_11", + "CMT_TOP_EE2BEG2_14", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_WW4END1_4", + "CMT_TOP_FAN6_14", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX36_13", + "CMT_TOP_NW2A2_12", + "CMT_TOP_IMUX9_10", + "CMT_TOP_SW4A1_5", + "CMT_TOP_SE4C0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_R_LOWER_B_CLK_MMCM11", + "CMT_LR_LOWER_B_MMCM_TESTIN1", + "MMCM_CLK_FREQ_BB_REBUF1_NS", + "CMT_TOP_ER1BEG3_14", + "CMT_TOP_SW2A1_0", + "CMT_TOP_SE4BEG1_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT47", + "CMT_TOP_EE2A0_0", + "CMT_TOP_CTRL1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_NE4C3_15", + "CMT_TOP_WW4A1_2", + "CMT_TOP_WW4C3_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_LH5_15", + "CMT_TOP_IMUX5_9", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_IMUX38_2", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_IMUX1_11", + "CMT_TOP_IMUX22_13", + "CMT_TOP_IMUX35_10", + "CMT_TOP_EE4A3_0", + "CMT_TOP_WW2A3_6", + "CMT_TOP_NW2A3_1", + "CMT_TOP_BYP3_5", + "CMT_TOP_BYP6_11", + "CMT_TOP_SW2A3_4", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX42_8", + "CMT_TOP_SE4C1_13", + "CMT_TOP_IMUX30_2", + "CMT_TOP_IMUX45_1", + "CMT_TOP_WW4B3_0", + "CMT_LR_LOWER_B_MMCM_PSCLK", + "CMT_MMCM_PHASER_OUT_A_OCLK", + "CMT_TOP_LOGIC_OUTS_L_B2_12", + "CMT_TOP_LH3_6", + "CMT_TOP_LH12_12", + "CMT_TOP_IMUX12_0", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_ER1BEG3_13", + "CMT_TOP_IMUX11_0", + "CMT_TOP_NW4A2_15", + "CMT_TOP_IMUX24_3", + "CMT_TOP_EE2BEG2_12", + "CMT_TOP_EE4B2_10", + "CMT_LR_LOWER_B_MMCM_TESTIN9", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX24_2", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_SE4BEG2_12", + "CMT_TOP_LH3_0", + "CMT_TOP_LOGIC_OUTS_L_B22_13", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_WW2A1_1", + "CMT_TOP_LH2_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT58", + "CMT_TOP_IMUX22_2", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX2_8", + "CMT_TOP_LH3_15", + "CMT_TOP_IMUX22_9", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_OCLKDIV_12", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_NW2A2_13", + "CMT_TOP_ICLK_10", + "CMT_TOP_LOGIC_OUTS_L_B18_14", + "CMT_TOP_SE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_LH2_11", + "CMT_TOP_SW4END1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_TOP_NE4C2_15", + "CMT_TOP_WL1END1_4", + "CMT_LR_LOWER_B_MMCM_PSDONE", + "CMT_TOP_IMUX37_9", + "CMT_TOP_FAN0_14", + "CMT_TOP_EE2A2_10", + "CMT_TOP_WW4C3_9", + "CMT_TOP_SE2A0_15", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP6_12", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH7_11", + "CMT_LR_LOWER_B_MMCM_TESTIN12", + "CMT_TOP_IMUX42_12", + "MMCM_CLK_FREQ_BB_REBUF3_NS", + "CMT_LR_LOWER_B_MMCM_DCLK", + "CMT_TOP_EE4A0_7", + "CMT_TOP_EE2BEG0_13", + "CMT_TOP_EE4A0_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_EE4B1_5", + "CMT_TOP_CLK1_12", + "CMT_TOP_NE2A0_15", + "CMT_TOP_WW2A2_13", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_IMUX19_1", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_NE4BEG3_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT20", + "CMT_TOP_WW4B2_10", + "CMT_TOP_IMUX17_3", + "CMT_TOP_NW4A0_1", + "CMT_TOP_EE4A1_12", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX36_0", + "CMT_TOP_WW4A1_12", + "CMT_TOP_WW2A2_7", + "CMT_TOP_IMUX33_8", + "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "CMT_TOP_SW4END2_8", + "CMT_TOP_NE4C3_7", + "CMT_TOP_CLK1_9", + "CMT_TOP_WW4C2_7", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_LH6_13", + "CMT_TOP_NW2A2_2", + "CMT_LR_LOWER_B_MMCM_TESTOUT0", + "CMT_TOP_EE2BEG3_14", + "CMT_TOP_LH11_12", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW4END0_5", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_BYP3_2", + "CMT_TOP_NW4END2_1", + "CMT_TOP_IMUX15_0", + "CMT_TOP_IMUX45_3", + "CMT_TOP_NW4A1_10", + "CMT_TOP_IMUX33_10", + "CMT_TOP_SE4C0_6", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_LH1_9", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH10_4", + "CMT_TOP_NE2A0_13", + "CMT_TOP_SE4C2_7", + "CMT_TOP_WW4A0_12", + "CMT_TOP_IMUX32_3", + "CMT_TOP_EE4A1_15", + "CMT_TOP_IMUX16_9", + "CMT_TOP_EE4BEG0_14", + "CMT_TOP_IMUX3_11", + "CMT_TOP_BYP5_1", + "CMT_TOP_IMUX12_15", + "CMT_TOP_CTRL1_14", + "CMT_TOP_IMUX23_13", + "CMT_TOP_NE4C2_12", + "CMT_TOP_WW2A1_7", + "CMT_TOP_IMUX9_12", + "CMT_TOP_IMUX17_5", + "CMT_TOP_BYP2_2", + "CMT_TOP_LH1_6", + "CMT_TOP_SW4A1_11", + "CMT_LR_LOWER_B_MMCM_TESTIN6", + "CMT_TOP_IMUX40_12", + "CMT_TOP_IMUX12_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_WR1END3_15", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX13_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_NW2A1_9", + "CMT_MMCM_PHASER_OUT_B_OCLK", + "CMT_TOP_IMUX36_14", + "CMT_TOP_SE2A3_3", + "CMT_TOP_LOGIC_OUTS_L_B6_15", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_14", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_EE4C0_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_NE4C2_0", + "CMT_TOP_IMUX1_7", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX21_5", + "CMT_TOP_ER1BEG0_12", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH12_3", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_EE4C2_15", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_NW4A0_13", + "CMT_TOP_LH5_14", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LH12_8", + "CMT_TOP_LOGIC_OUTS_L_B1_13", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX40_7", + "CMT_R_LOWER_B_CLK_MMCM2", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_NW4END1_12", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_CTRL0_8", + "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "CMT_TOP_NW4A3_7", + "CMT_LR_LOWER_B_MMCM_TESTIN16", + "CMT_TOP_NW4END3_0", + "CMT_TOP_NE2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_WW4A2_12", + "CMT_TOP_IMUX20_8", + "CMT_TOP_WW2END0_8", + "CMT_TOP_LH9_3", + "CMT_TOP_SW4END0_15", + "CMT_TOP_IMUX29_9", + "CMT_TOP_LH6_4", + "CMT_TOP_ICLK_15", + "CMT_TOP_EE4C1_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT32", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_WW2A2_10", + "CMT_TOP_FAN2_12", + "CMT_TOP_BLOCK_OUTS_L_B2_13", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_SE4C2_15", + "CMT_TOP_NE4C3_0", + "CMT_TOP_SW2A0_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT18", + "CMT_TOP_BYP6_5", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_WL1END0_6", + "CMT_TOP_LOGIC_OUTS_L_B12_14", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_IMUX29_14", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_IMUX15_6", + "CMT_TOP_WR1END3_13", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_MONITOR_N_14", + "CMT_TOP_IMUX36_2", + "CMT_TOP_FAN1_3", + "CMT_TOP_LH9_0", + "CMT_TOP_WL1END0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_WR1END3_6", + "CMT_TOP_LOGIC_OUTS_L_B2_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT29", + "CMT_R_LOWER_B_CLK_MMCM12", + "CMT_TOP_NE2A3_3", + "CMT_TOP_SW4A2_10", + "CMT_TOP_WR1END2_10", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX26_6", + "CMT_TOP_FAN3_13", + "CMT_TOP_SE4C0_12", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_WW4B3_14", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_NW4A1_13", + "CMT_TOP_IMUX29_0", + "CMT_TOP_WR1END2_0", + "CMT_TOP_SW2A3_6", + "CMT_MMCM_A_WRCLK_TOFIFO", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX43_9", + "CMT_TOP_IMUX8_10", + "CMT_TOP_NW4A2_13", + "CMT_TOP_BYP3_3", + "CMT_MMCM_PHASERREF_ABOVE1", + "CMT_TOP_WW2A2_3", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX44_0", + "CMT_TOP_WW4C1_1", + "CMT_TOP_IMUX15_12", + "CMT_TOP_EE4A1_7", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW2A1_3", + "CMT_TOP_IMUX4_15", + "CMT_TOP_IMUX39_5", + "CMT_TOP_LH1_0", + "CMT_TOP_EE4BEG2_14", + "CMT_TOP_IMUX28_5", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_NE2A1_7", + "CMT_TOP_IMUX41_10", + "CMT_TOP_WR1END3_5", + "CMT_TOP_IMUX37_10", + "CMT_TOP_IMUX23_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX15_5", + "CMT_LR_LOWER_B_MMCM_TESTOUT28", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_SW4A0_7", + "CMT_TOP_NW4A0_15", + "CMT_TOP_WW4A3_14", + "CMT_TOP_LH12_4", + "CMT_LR_LOWER_B_MMCM_TESTOUT55", + "CMT_TOP_WW4A2_11", + "CMT_TOP_FAN2_14", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_WW4END1_13", + "CMT_R_LOWER_B_CLK_MMCM9", + "CMT_TOP_WW4A1_7", + "CMT_TOP_LH4_14", + "CMT_TOP_IMUX45_14", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_BYP0_12", + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX5_3", + "CMT_TOP_IMUX24_15", + "CMT_TOP_WW4A3_2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_LH7_7", + "CMT_TOP_WW4C0_7", + "CMT_TOP_EE2BEG1_14", + "CMT_TOP_BYP4_13", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_IMUX39_11", + "CMT_TOP_BYP5_4", + "CMT_TOP_FAN4_3", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_FAN6_2", + "CMT_TOP_IMUX20_6", + "CMT_TOP_LH4_5", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SW2A0_12", + "CMT_TOP_WR1END2_4", + "CMT_TOP_LH9_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_CTRL0_15", + "CMT_TOP_SE4BEG0_3", + "CMT_LR_LOWER_B_MMCM_TESTIN15", + "CMT_TOP_EE4C3_0", + "CMT_TOP_BYP4_9", + "CMT_TOP_NE4C1_6", + "CMT_TOP_NW4END2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_14", + "CMT_TOP_BYP2_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT61", + "CMT_TOP_WW2A0_10", + "CMT_TOP_IMUX7_11", + "CMT_TOP_WW4END0_0", + "CMT_TOP_BYP5_13", + "CMT_TOP_NE4C0_12", + "CMT_TOP_BLOCK_OUTS_L_B0_14", + "CMT_TOP_EE2A2_7", + "CMT_TOP_LH2_1", + "CMT_TOP_MONITOR_N_12", + "CMT_TOP_NW4END3_12", + "CMT_TOP_WW4END3_7", + "CMT_TOP_WW2END2_13", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_WW4B2_12", + "CMT_TOP_EE2BEG0_9", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX4_12", + "CMT_TOP_LH11_5", + "CMT_TOP_WW4C2_15", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_WW4C1_5", + "CMT_TOP_BYP5_8", + "CMT_TOP_LOGIC_OUTS_L_B14_14", + "CMT_TOP_WR1END2_11", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_8", + "CMT_TOP_LH6_14", + "CMT_TOP_LOGIC_OUTS_L_B9_15", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_WL1END1_7", + "CMT_TOP_WL1END1_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_NW4A1_15", + "CMT_TOP_FAN6_13", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_IMUX14_13", + "CMT_TOP_NW4A3_6", + "CMT_TOP_LH6_7", + "CMT_TOP_WW4B1_8", + "CMT_TOP_EE4BEG1_15", + "CMT_TOP_WW4A3_0", + "CMT_TOP_FAN3_7", + "CMT_TOP_IMUX14_14", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_SW2A2_10", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT38", + "CMT_TOP_IMUX25_5", + "CMT_TOP_CLK0_4", + "CMT_TOP_EE2A0_14", + "CMT_TOP_NW2A0_9", + "CMT_MMCM_PHASER_OUT_A_OCLKDIV", + "CMT_TOP_CLK0_13", + "CMT_TOP_FAN5_3", + "CMT_TOP_EE4A1_4", + "CMT_TOP_IMUX31_6", + "CMT_TOP_NE2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_IMUX38_7", + "CMT_LR_LOWER_B_MMCM_DO12", + "CMT_TOP_LH4_15", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_LH5_13", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_NE2A1_12", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_LR_LOWER_B_CLKFBOUT2IN", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_ICLK_7", + "CMT_TOP_LOGIC_OUTS_L_B5_13", + "CMT_TOP_IMUX15_3", + "CMT_TOP_FAN1_9", + "CMT_TOP_FAN2_3", + "CMT_PHASER_A_ICLKDIV_TOIOI", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_SW4A0_4", + "CMT_TOP_NW2A0_14", + "CMT_TOP_LH11_9", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_IMUX8_3", + "CMT_LR_LOWER_B_MMCM_DEN", + "CMT_TOP_NW4END2_15", + "CMT_TOP_WW4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_EE4C2_11", + "CMT_TOP_NE4C3_1", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CTRL0_3", + "CMT_TOP_FAN0_8", + "CMT_TOP_EE4C2_7", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_SW4A1_1", + "CMT_TOP_NW2A1_13", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_NW4END2_10", + "CMT_TOP_IMUX16_12", + "CMT_TOP_IMUX35_12", + "CMT_LR_LOWER_B_MMCM_TESTOUT27", + "CMT_TOP_IMUX9_6", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX31_8", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX28_7", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LH8_15", + "CMT_TOP_LOGIC_OUTS_L_B16_14", + "CMT_TOP_IMUX2_15", + "CMT_TOP_BYP2_13", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_SW4END2_15", + "CMT_TOP_IMUX41_1", + "CMT_TOP_SW2A3_7", + "CMT_TOP_LH4_9", + "CMT_TOP_SE4BEG2_15", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_SE2A3_13", + "CMT_TOP_NW2A3_9", + "CMT_TOP_SE2A1_15", + "CMT_TOP_EE4B3_4", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_IMUX24_4", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_FAN6_6", + "CMT_TOP_IMUX25_2", + "CMT_TOP_SW4A2_13", + "CMT_TOP_BYP2_3", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_FAN4_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_SW4A3_14", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_NW4A1_3", + "CMT_TOP_IMUX35_4", + "CMT_TOP_WW2END3_10", + "CMT_TOP_IMUX41_5", + "CMT_TOP_NW4A1_8", + "CMT_TOP_IMUX10_6", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_LH12_6", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_BYP6_10", + "CMT_LR_LOWER_B_MMCM_TESTIN7", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_IMUX12_7", + "CMT_TOP_OCLKDIV_13", + "CMT_TOP_FAN1_14", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B1_15", + "CMT_TOP_BYP7_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_IMUX5_12", + "CMT_TOP_SW4A2_1", + "CMT_TOP_LH1_3", + "CMT_TOP_FAN0_5", + "CMT_TOP_EE2A1_8", + "CMT_TOP_WW4C3_7", + "CMT_TOP_WW4A0_13", + "CMT_TOP_LH2_3", + "CMT_TOP_IMUX27_14", + "CMT_TOP_FAN7_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_NE2A0_12", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT16", + "CMT_TOP_NW4A3_0", + "CMT_R_LOWER_B_CLK_MMCM8", + "CMT_TOP_EE4B1_10", + "CMT_TOP_LH9_12", + "CMT_TOP_WW4END2_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX38_4", + "CMT_TOP_WW4C1_15", + "CMT_TOP_NE2A1_4", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_IMUX27_2", + "CMT_TOP_WW4C0_6", + "CMT_LR_LOWER_B_MMCM_DI3", + "CMT_TOP_IMUX1_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_NE2A2_5", + "CMT_TOP_NW4A0_3", + "CMT_TOP_LOGIC_OUTS_L_B4_12", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_IMUX44_13", + "CMT_TOP_EE4BEG3_12", + "CMT_TOP_NW2A3_6", + "CMT_TOP_WW4END3_5", + "CMT_TOP_IMUX34_12", + "CMT_TOP_WW4B1_5", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX23_10", + "CMT_TOP_CTRL1_15", + "CMT_TOP_IMUX17_0", + "CMT_TOP_CLK0_2", + "CMT_TOP_EE4B3_2", + "CMT_TOP_IMUX31_5", + "CMT_TOP_FAN0_0", + "CMT_TOP_EE4C3_2", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX46_3", + "CMT_TOP_IMUX43_7", + "CMT_TOP_IMUX40_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_EE4A3_9", + "CMT_TOP_WW4END3_6", + "CMT_TOP_FAN2_5", + "CMT_TOP_CLK0_6", + "CMT_LR_LOWER_B_MMCM_TESTIN27", + "CMT_TOP_IMUX10_5", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_WW2A3_8", + "CMT_TOP_NE4C1_8", + "CMT_TOP_EE4A1_1", + "CMT_TOP_IMUX5_13", + "CMT_TOP_WW4A3_12", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4C0_4", + "CMT_TOP_BYP0_6", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX12_4", + "CMT_TOP_LH10_3", + "CMT_TOP_LH3_2", + "CMT_TOP_IMUX11_15", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_LOGIC_OUTS_L_B9_14", + "MMCMOUT_CLK_FREQ_BB_3", + "CMT_LR_LOWER_B_MMCM_DO13", + "CMT_TOP_IMUX43_4", + "CMT_TOP_LH10_6", + "CMT_TOP_SE4C0_15", + "CMT_TOP_NE4C1_10", + "CMT_TOP_IMUX15_11", + "CMT_TOP_NE4C1_9", + "CMT_TOP_WW4B0_3", + "CMT_TOP_NE2A1_15", + "CMT_TOP_WW4C3_10", + "CMT_TOP_SE2A2_6", + "CMT_TOP_NW2A3_5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_EE4BEG0_13", + "CMT_LR_LOWER_B_MMCM_DADDR3", + "CMT_TOP_LH9_14", + "CMT_TOP_LH1_15", + "CMT_TOP_WW4A2_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_LH10_15", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_SW2A1_12", + "CMT_TOP_IMUX38_11", + "CMT_TOP_SE4C2_13", + "CMT_TOP_SW4END2_9", + "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_R_LOWER_B_CLK_MMCM7", + "CMT_TOP_CTRL0_14", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_LH3_1", + "CMT_TOP_LOGIC_OUTS_L_B3_13", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END2_5", + "CMT_TOP_FAN0_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_EE2BEG3_15", + "CMT_TOP_IMUX42_11", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX4_5", + "CMT_TOP_LOGIC_OUTS_L_B13_14", + "CMT_TOP_BYP4_0", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LH4_4", + "CMT_TOP_LH3_9", + "CMT_TOP_SE4BEG3_15", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_EL1BEG2_9", + "MMCM_CLK_FREQ_BB_NS3", + "CMT_TOP_WW4C1_2", + "CMT_TOP_IMUX37_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT40", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_WR1END1_0", + "CMT_TOP_IMUX17_14", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_IMUX22_5", + "CMT_MMCM_PHASER_IN_B_ICLK", + "CMT_LR_LOWER_B_MMCM_TESTOUT42", + "CMT_TOP_OCLK_3", + "CMT_TOP_IMUX23_5", + "CMT_TOP_SW4END2_4", + "CMT_TOP_IMUX37_12", + "CMT_TOP_EE4A1_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT26", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW2END0_2", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_WW4A0_15", + "CMT_TOP_SE2A1_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT48", + "CMT_TOP_NE4BEG1_14", + "CMT_TOP_NW2A3_13", + "CMT_TOP_BLOCK_OUTS_L_B2_14", + "CMT_LR_LOWER_B_MMCM_TESTOUT30", + "CMT_TOP_CTRL0_1", + "CMT_LR_LOWER_B_MMCM_DO9", + "CMT_LR_LOWER_B_MMCM_TESTOUT41", + "CMT_TOP_NE2A1_10", + "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "CMT_TOP_WW2END0_9", + "CMT_LR_LOWER_B_MMCM_TESTOUT23", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_WW4B0_0", + "CMT_TOP_LH7_12", + "CMT_TOP_EL1BEG1_15", + "CMT_TOP_IMUX6_5", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_WW4B0_4", + "CMT_TOP_IMUX10_9", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_IMUX26_13", + "CMT_TOP_IMUX45_0", + "CMT_TOP_WW4END2_13", + "CMT_TOP_IMUX45_10", + "CMT_TOP_IMUX39_1", + "CMT_TOP_WW4B3_15", + "CMT_TOP_WL1END1_8", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WW2END3_8", + "CMT_TOP_IMUX9_5", + "CMT_TOP_BYP4_10", + "CMT_TOP_WW4C2_12", + "CMT_TOP_IMUX17_9", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_R_LOWER_B_CLK_FREQ_BB1", + "CMT_TOP_IMUX23_4", + "CMT_TOP_IMUX32_15", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_FAN3_10", + "CMT_TOP_EE4B0_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_SW2A3_15", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX42_9", + "CMT_TOP_IMUX38_12", + "CMT_TOP_EE2A2_6", + "CMT_TOP_IMUX25_3", + "CMT_R_LOWER_B_CLK_MMCM6", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_EL1BEG2_13", + "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "CMT_TOP_LOGIC_OUTS_L_B11_15", + "CMT_TOP_NE4BEG2_14", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WR1END1_12", + "CMT_TOP_CLK0_15", + "CMT_TOP_IMUX28_15", + "CMT_TOP_IMUX34_4", + "CMT_TOP_LH7_2", + "CMT_TOP_LH6_1", + "CMT_TOP_NW4END2_2", + "CMT_TOP_IMUX37_13", + "CMT_TOP_LH1_2", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_NE2A2_13", + "CMT_TOP_NW2A2_14", + "CMT_TOP_IMUX13_2", + "CMT_TOP_WW4A0_8", + "CMT_TOP_FAN6_8", + "CMT_TOP_IMUX17_7", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_NW4A0_2", + "CMT_TOP_BYP6_6", + "CMT_TOP_SE4C0_14", + "CMT_TOP_WW4C1_13", + "CMT_TOP_WW4B2_15", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_LR_LOWER_B_MMCM_DI15", + "CMT_TOP_SW4END1_7", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NW4END0_6", + "CMT_TOP_WR1END3_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_IMUX6_14", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_ER1BEG0_14", + "CMT_TOP_NE2A3_7", + "CMT_TOP_EE4A1_14", + "CMT_TOP_IMUX3_7", + "CMT_TOP_WW4B1_13", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_TOP_BYP2_6", + "CMT_TOP_IMUX14_8", + "CMT_TOP_WW4C1_14", + "CMT_TOP_NE4C0_0", + "CMT_TOP_BYP0_3", + "CMT_TOP_NE4C2_10", + "CMT_TOP_SE2A2_12", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH6_11", + "CMT_TOP_FAN5_10", + "CMT_TOP_WL1END2_14", + "CMT_TOP_EE2A2_15", + "CMT_TOP_WW4END2_4", + "CMT_LR_LOWER_B_MMCM_TESTIN21", + "CMT_TOP_EE4C3_12", + "CMT_TOP_NW2A3_11", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_LR_LOWER_B_MMCM_TESTOUT2", + "CMT_TOP_IMUX41_14", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_EE4A2_15", + "CMT_TOP_NW2A2_8", + "MMCM_CLK_FREQ_BB_NS0", + "CMT_TOP_WR1END1_14", + "CMT_TOP_IMUX19_4", + "CMT_TOP_WW2END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_SW2A3_14", + "CMT_TOP_FAN2_13", + "CMT_TOP_IMUX30_4", + "CMT_TOP_SW2A0_14", + "CMT_TOP_SE4BEG0_13", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX28_1", + "CMT_TOP_NW4A0_0", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_LH3_7", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX16_4", + "CMT_LR_LOWER_B_MMCM_TESTIN2", + "CMT_TOP_EE2A3_7", + "CMT_TOP_SE4C3_11", + "CMT_TOP_ICLK_9", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_WW4A1_10", + "CMT_TOP_WW2END0_0", + "CMT_TOP_NW4A2_12", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_WW4C3_11", + "CMT_TOP_BYP3_6", + "CMT_TOP_NE4BEG2_10", + "CMT_MMCM_A_WREN_TOFIFO", + "CMT_TOP_WW2A2_8", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_WW4B3_7", + "CMT_PHASER_A_OCLKDIV_TOIOI", + "CMT_TOP_SW4END3_4", + "CMT_TOP_EE2BEG3_13", + "CMT_TOP_EE4C1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_IMUX20_12", + "CMT_TOP_BYP0_8", + "CMT_TOP_WW4A0_14", + "CMT_TOP_FAN3_14", + "CMT_TOP_IMUX1_13", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_WW4END1_7", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WW4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_SE4BEG0_12", + "CMT_R_LOWER_B_CLK_MMCM4", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX5_0", + "CMT_TOP_WW4B3_10", + "CMT_TOP_IMUX9_13", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_WW2END3_9", + "CMT_TOP_SW4END1_10", + "CMT_TOP_WW4B0_7", + "CMT_TOP_BYP3_7", + "CMT_TOP_EE2A3_11", + "CMT_TOP_IMUX43_13", + "CMT_TOP_LH6_5", + "CMT_TOP_IMUX28_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_WW4A3_5", + "CMT_TOP_EL1BEG0_12", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_BLOCK_OUTS_L_B3_14", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_NW2A1_14", + "CMT_MMCM_A_RDEN_TOFIFO", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_WL1END0_3", + "CMT_TOP_WW4C0_2", + "CMT_TOP_IMUX0_7", + "CMT_TOP_WW4B1_0", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_EE4C2_14", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SW4END0_8", + "CMT_TOP_EE4BEG3_14", + "CMT_TOP_WW4C2_10", + "CMT_TOP_IMUX8_1", + "CMT_TOP_EE4BEG3_6", + "CMT_LR_LOWER_B_MMCM_TESTOUT24", + "CMT_TOP_IMUX38_15", + "CMT_TOP_IMUX34_6", + "CMT_TOP_IMUX32_11", + "CMT_TOP_NE2A3_1", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_R_LOWER_B_CLK_FREQ_BB0", + "CMT_TOP_EE4C1_12", + "CMT_MMCM_PHASERREF_ABOVE0", + "CMT_TOP_EE4B0_3", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A3_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_IMUX46_10", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_SW4A0_14", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C0_5", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_BYP4_4", + "CMT_TOP_NW4A2_9", + "CMT_TOP_WR1END2_1", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_IMUX15_15", + "CMT_TOP_IMUX16_1", + "CMT_TOP_NW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_FAN2_6", + "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "CMT_TOP_WR1END3_7", + "CMT_TOP_IMUX23_12", + "CMT_TOP_IMUX38_9", + "CMT_TOP_IMUX36_12", + "CMT_TOP_IMUX28_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_FAN5_7", + "CMT_TOP_BYP7_10", + "CMT_TOP_IMUX15_7", + "CMT_TOP_BLOCK_OUTS_L_B3_13", + "CMT_R_LOWER_B_CLK_IN1_INT", + "CMT_TOP_IMUX13_12", + "CMT_TOP_LH8_5", + "CMT_TOP_IMUX30_9", + "CMT_TOP_EE4A3_5", + "CMT_PHASER_A_ICLK_TOIOI", + "CMT_TOP_WR1END2_15", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_NE4C0_5", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_IMUX25_0", + "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "CMT_TOP_IMUX31_13", + "CMT_TOP_IMUX31_10", + "CMT_TOP_BLOCK_OUTS_L_B0_15", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_SW4A0_12", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_NE4C1_13", + "CMT_TOP_IMUX34_2", + "CMT_TOP_EE4B2_14", + "CMT_TOP_LH10_2", + "CMT_TOP_SW4A2_12", + "CMT_TOP_SW4A1_15", + "CMT_LR_LOWER_B_MMCM_DI14", + "CMT_TOP_LH12_0", + "CMT_TOP_FAN4_0", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_NW4A0_8", + "CMT_TOP_WW4A2_10", + "CMT_TOP_BYP3_0", + "CMT_TOP_IMUX2_1", + "CMT_TOP_WW4END3_15", + "CMT_TOP_IMUX22_1", + "CMT_TOP_NW4END0_14", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_BLOCK_OUTS_L_B1_12", + "CMT_TOP_EE2A3_5", + "CMT_LR_LOWER_B_MMCM_TESTIN19", + "CMT_LR_LOWER_B_MMCM_TESTOUT5", + "CMT_TOP_OCLK1X_90_15", + "CMT_TOP_IMUX4_7", + "CMT_TOP_SE2A2_0", + "CMT_TOP_LH2_4", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SW4A3_6", + "CMT_TOP_NW4END1_5", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WR1END3_1", + "CMT_TOP_BYP1_0", + "CMT_TOP_EE2BEG1_12", + "CMT_TOP_WW2A0_6", + "CMT_TOP_SE2A3_0", + "CMT_LR_LOWER_B_MMCM_DADDR4", + "CMT_TOP_IMUX35_9", + "CMT_TOP_SW4END2_5", + "CMT_TOP_SE4C3_5", + "CMT_TOP_LH4_1", + "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "CMT_TOP_SW2A1_14", + "CMT_TOP_NW4A0_9", + "CMT_TOP_SW4A1_6", + "CMT_TOP_WL1END3_15", + "CMT_TOP_LH1_13", + "CMT_TOP_SW2A2_0", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE4C3_10", + "CMT_TOP_LOGIC_OUTS_L_B11_12", + "CMT_TOP_LOGIC_OUTS_L_B7_15", + "CMT_TOP_SW4END0_7", + "CMT_TOP_EE4BEG1_12", + "CMT_LR_LOWER_B_MMCM_TESTIN18", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT8", + "CMT_TOP_IMUX13_5", + "CMT_TOP_SE2A1_13", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EE4A2_4", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_LH2_8", + "CMT_TOP_SE2A3_1", + "CMT_TOP_IMUX2_6", + "CMT_LR_LOWER_B_MMCM_TESTIN10", + "CMT_TOP_IMUX3_0", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_NE4C0_15", + "CMT_TOP_EE4C2_4", + "CMT_TOP_BYP6_13", + "CMT_TOP_NE4BEG1_5", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_EE2A3_2", + "CMT_TOP_IMUX14_10", + "CMT_TOP_IMUX23_8", + "CMT_TOP_WW4A3_8", + "CMT_TOP_IMUX40_6", + "CMT_TOP_IMUX24_12", + "CMT_LR_LOWER_B_MMCM_DI11", + "CMT_TOP_LH10_9", + "CMT_TOP_BYP3_12", + "CMT_TOP_NW2A3_14", + "CMT_TOP_WW2A1_15", + "CMT_TOP_FAN1_0", + "CMT_TOP_LH4_10", + "CMT_TOP_IMUX0_2", + "CMT_TOP_EL1BEG3_12", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_LH1_12", + "CMT_LR_LOWER_B_MMCM_DO6", + "CMT_TOP_LH5_3", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_NW2A0_3", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_LR_LOWER_B_MMCM_TESTOUT36", + "CMT_TOP_IMUX18_1", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_IMUX42_13", + "CMT_TOP_NW4A3_14", + "CMT_TOP_SW4END3_10", + "CMT_TOP_FAN2_10", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_LOGIC_OUTS_L_B0_15", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_WR1END1_1", + "CMT_TOP_SW2A2_7", + "CMT_PHASER_A_OCLK90_TOIOI", + "CMT_TOP_ICLK_5", + "CMT_TOP_BYP0_14", + "CMT_TOP_SW2A0_7", + "CMT_TOP_FAN7_13", + "CMT_TOP_LH6_15", + "CMT_TOP_FAN6_5", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WW2A1_2", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_FAN4_1", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_IMUX19_13", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_ER1BEG1_13", + "CMT_TOP_SE4C0_11", + "CMT_TOP_BYP5_14", + "MMCM_CLK_FREQ_BB_NS1", + "CMT_TOP_WW2END0_6", + "CMT_TOP_CTRL1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_LR_LOWER_B_MMCM_TESTOUT46", + "CMT_TOP_BLOCK_OUTS_L_B1_14", + "CMT_TOP_WW4B1_14", + "CMT_TOP_WW4B1_2", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_NE4BEG3_15", + "CMT_TOP_FAN6_3", + "CMT_TOP_WL1END1_11", + "CMT_TOP_SW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_LOGIC_OUTS_L_B20_13", + "CMT_TOP_NW2A3_10", + "CMT_TOP_LH11_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_IMUX28_13", + "CMT_TOP_WW2END2_15", + "CMT_TOP_SE4C2_6", + "CMT_TOP_FAN5_11", + "CMT_TOP_IMUX39_12", + "CMT_TOP_SW4END1_6", + "CMT_TOP_IMUX2_2", + "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH6_0", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX29_3", + "MMCMOUT_CLK_FREQ_BB_0", + "CMT_TOP_WL1END1_6", + "CMT_TOP_IMUX0_13", + "CMT_TOP_NW4A2_5", + "CMT_TOP_IMUX6_9", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX9_2", + "CMT_TOP_IMUX19_5", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_SE4BEG3_13", + "CMT_TOP_EE4A1_9", + "CMT_TOP_EE4B3_9", + "CMT_TOP_IMUX3_14", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_NE2A3_4", + "CMT_TOP_EE2A0_11", + "CMT_TOP_IMUX40_3", + "CMT_TOP_SW2A3_12", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_EL1BEG2_1", + "CMT_LR_LOWER_B_MMCM_TESTOUT60", + "CMT_TOP_ICLK_3", + "CMT_TOP_SW4END0_6", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_IMUX41_6", + "CMT_TOP_EE2BEG2_13", + "CMT_TOP_EE4A0_11", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_IMUX46_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_EE4C0_2", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX11_3", + "CMT_TOP_IMUX17_12", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_LH5_8", + "CMT_TOP_WW4A2_8", + "CMT_TOP_WW4A3_4", + "CMT_R_LOWER_B_CLK_PERF0", + "CMT_LR_LOWER_B_MMCM_CLKIN2", + "CMT_TOP_LH11_4", + "CMT_TOP_IMUX34_0", + "CMT_TOP_EE2A1_13", + "CMT_TOP_BYP1_6", + "CMT_TOP_WW4B0_1", + "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "CMT_TOP_NW4END0_15", + "CMT_TOP_WL1END0_12", + "CMT_R_LOWER_B_CLK_PERF2", + "CMT_TOP_IMUX2_4", + "CMT_TOP_SW4A1_8", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_SE4C3_15", + "CMT_TOP_WL1END3_10", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX29_7", + "CMT_TOP_IMUX33_3", + "CMT_TOP_SW4END3_12", + "CMT_TOP_SW2A2_3", + "CMT_TOP_FAN6_12", + "CMT_TOP_IMUX44_8", + "CMT_TOP_SW4A1_14", + "CMT_TOP_IMUX32_7", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SW2A3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_OCLK_13", + "CMT_TOP_BLOCK_OUTS_L_B3_15", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX32_1", + "MMCMOUT_CLK_FREQ_BB_1", + "CMT_TOP_LH8_1", + "CMT_TOP_SE2A2_1", + "CMT_TOP_WW4B0_13", + "CMT_TOP_NW2A3_12", + "CMT_TOP_IMUX31_12", + "CMT_TOP_WW4C3_3", + "CMT_TOP_SE4C3_1", + "CMT_TOP_CTRL0_7", + "CMT_TOP_NW2A0_13", + "CMT_TOP_IMUX26_3", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_IMUX24_6", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_NE2A2_10", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_LR_LOWER_B_MMCM_TESTIN3", + "CMT_TOP_LOGIC_OUTS_L_B7_12", + "CMT_TOP_IMUX17_1", + "CMT_TOP_EE4C3_7", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NE2A2_15", + "CMT_TOP_CLK1_14", + "CMT_TOP_ICLK_6", + "CMT_LR_LOWER_B_MMCM_TESTIN17", + "CMT_TOP_SE2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_SE2A3_7", + "CMT_TOP_BYP6_9", + "CMT_TOP_EE4B2_3", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_WW2A0_8", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX30_10", + "CMT_TOP_SE2A2_15", + "CMT_TOP_WW4END0_9", + "CMT_TOP_SW4END0_5", + "CMT_TOP_IMUX0_3", + "CMT_TOP_IMUX27_10", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_SW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_IMUX40_13", + "CMT_TOP_CTRL1_1", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_IMUX29_12", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_IMUX12_11", + "CMT_TOP_WW4A3_10", + "CMT_TOP_FAN3_6", + "CMT_TOP_LH5_4", + "CMT_TOP_LOGIC_OUTS_L_B21_12", + "CMT_TOP_NE4C1_12", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_WW2END1_12", + "CMT_TOP_IMUX47_3", + "CMT_TOP_SW4A3_5", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_EE2A1_4", + "CMT_TOP_NW4END1_4", + "CMT_TOP_IMUX25_1", + "CMT_TOP_LH5_11", + "CMT_MMCM_PHASERA_DTSBUS0", + "CMT_TOP_FAN1_10", + "CMT_TOP_LH3_12", + "CMT_TOP_NW4END0_11", + "CMT_TOP_IMUX34_14", + "CMT_TOP_EE4C0_11", + "CMT_TOP_BLOCK_OUTS_L_B0_12", + "CMT_TOP_IMUX25_8", + "CMT_TOP_EE4A1_3", + "CMT_TOP_IMUX14_15", + "CMT_TOP_NW2A3_7", + "CMT_TOP_IMUX30_11", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_EE2A1_2", + "CMT_TOP_LOGIC_OUTS_L_B16_15", + "CMT_TOP_IMUX34_15", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WW4C0_12", + "CMT_TOP_WW4C2_8", + "CMT_TOP_EL1BEG3_14", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_LOGIC_OUTS_L_B15_14", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX26_11", + "CMT_LR_LOWER_B_MMCM_TESTIN13", + "CMT_TOP_NE2A2_1", + "CMT_TOP_CTRL1_8", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NW4END3_3", + "CMT_TOP_WW4B2_2", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX16_11", + "CMT_TOP_WW4A0_3", + "CMT_TOP_LH5_1", + "CMT_TOP_WL1END0_4", + "CMT_TOP_NW4A3_12", + "CMT_TOP_IMUX45_15", + "CMT_TOP_IMUX44_7", + "CMT_TOP_SW2A3_3", + "CMT_TOP_IMUX42_15", + "CMT_LR_LOWER_B_MMCM_TESTOUT4", + "CMT_TOP_SE2A2_3", + "CMT_TOP_FAN6_10", + "CMT_TOP_SE4C2_4", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX19_14", + "CMT_TOP_NE4C1_3", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX18_8", + "CMT_LR_LOWER_B_MMCM_TESTOUT19", + "CMT_TOP_BYP3_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_CLK1_5", + "CMT_TOP_SW2A0_4", + "CMT_TOP_IMUX0_10", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_LR_LOWER_B_MMCM_TESTIN8", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_WW2A0_14", + "CMT_TOP_IMUX13_7", + "CMT_TOP_IMUX26_14", + "CMT_TOP_NE4C2_2", + "CMT_TOP_IMUX10_4", + "CMT_TOP_EE4A1_11", + "CMT_TOP_EE2A0_6", + "CMT_TOP_NW4END1_0", + "CMT_TOP_LH5_10", + "CMT_TOP_IMUX46_7", + "CMT_TOP_LOGIC_OUTS_L_B10_13", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_WW4C2_2", + "CMT_TOP_IMUX17_15", + "CMT_TOP_LOGIC_OUTS_L_B4_13", + "CMT_TOP_EE2A2_8", + "CMT_TOP_OCLK_9", + "CMT_TOP_NW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_WW4END3_9", + "CMT_TOP_EE4C3_1", + "CMT_TOP_IMUX14_11", + "CMT_TOP_WW4C1_9", + "CMT_TOP_IMUX0_9", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_WL1END3_9", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_EE4A3_15", + "CMT_TOP_IMUX13_6", + "CMT_TOP_EE4A2_6", + "CMT_TOP_IMUX20_0", + "CMT_TOP_IMUX16_13", + "CMT_TOP_WW4B2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_WW2A0_1", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_FAN7_9", + "CMT_LR_LOWER_B_MMCM_LOCKED", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_FAN7_12", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LH5_7", + "CMT_TOP_IMUX21_9", + "CMT_TOP_IMUX35_1", + "CMT_TOP_IMUX47_12", + "CMT_LR_LOWER_B_MMCM_TESTIN0", + "CMT_TOP_LH11_14", + "CMT_TOP_EL1BEG2_15", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_NW2A3_8", + "CMT_TOP_SE2A3_4", + "CMT_TOP_SW4END3_9", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NE4C0_10", + "CMT_TOP_IMUX26_5", + "CMT_TOP_BYP4_11", + "CMT_MMCM_PHASERA_DTSBUS1", + "CMT_TOP_IMUX25_6", + "CMT_TOP_BYP0_2", + "CMT_TOP_BYP6_7", + "CMT_TOP_EE4BEG1_13", + "CMT_TOP_IMUX37_15", + "CMT_TOP_ICLK_12", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_IMUX30_15", + "CMT_TOP_NE2A1_8", + "CMT_TOP_WW4A0_10", + "CMT_TOP_SW2A0_13", + "CMT_TOP_BYP4_12", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_5", + "CMT_TOP_IMUX8_15", + "CMT_TOP_WW4B2_0", + "CMT_TOP_SE4BEG3_12", + "CMT_TOP_NE4C3_13", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_SW2A1_13", + "CMT_TOP_WW2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_SW2A2_13", + "CMT_TOP_WW4B0_15", + "CMT_TOP_WL1END3_0", + "CMT_TOP_WW4END0_3", + "CMT_TOP_MONITOR_N_13", + "CMT_TOP_NW4END0_1", + "CMT_TOP_IMUX12_10", + "CMT_TOP_LH6_6", + "CMT_TOP_NE4C3_5", + "CMT_TOP_FAN3_12", + "CMT_TOP_NW4END0_8", + "CMT_TOP_IMUX39_0", + "CMT_TOP_WW4END2_0", + "CMT_TOP_IMUX34_13", + "CMT_TOP_WW4B3_4", + "CMT_TOP_SE4BEG0_15", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_IMUX9_0", + "CMT_LR_LOWER_B_MMCM_TESTOUT3", + "CMT_TOP_LH10_13", + "CMT_TOP_FAN2_0", + "CMT_TOP_SE2A3_15", + "CMT_TOP_IMUX29_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT43", + "CMT_LR_LOWER_B_MMCM_TESTOUT25", + "CMT_TOP_IMUX30_5", + "CMT_TOP_IMUX8_9", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_NW4END2_5", + "CMT_TOP_NE4C0_7", + "CMT_TOP_ER1BEG2_15", + "CMT_TOP_WW2END2_4", + "CMT_TOP_IMUX21_13", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_WL1END3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_FAN5_14", + "CMT_TOP_SW4A3_4", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NW2A0_2", + "CMT_TOP_IMUX17_6", + "CMT_TOP_IMUX7_0", + "CMT_TOP_SE2A1_2", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_IMUX20_2", + "CMT_TOP_LH8_7", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_WW4A2_5", + "CMT_TOP_NE4C1_11", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_OCLK_6", + "CMT_TOP_CTRL1_12", + "CMT_TOP_IMUX18_10", + "CMT_TOP_BYP4_7", + "CMT_TOP_LH2_2", + "CMT_TOP_BYP0_5", + "CMT_TOP_SE2A2_4", + "CMT_TOP_SE4C2_1", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B0_12", + "CMT_R_LOWER_B_CLK_MMCM0", + "CMT_TOP_LH8_14", + "CMT_TOP_IMUX16_15", + "CMT_TOP_IMUX43_14", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_NW4END3_4", + "CMT_TOP_IMUX40_11", + "CMT_MMCM_PHASERREF_BELOW1", + "CMT_TOP_LH9_8", + "CMT_TOP_LOGIC_OUTS_L_B16_12", + "CMT_TOP_LH9_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT56", + "CMT_TOP_NE2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_LR_LOWER_B_MMCM_PWRDWN", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX28_11", + "CMT_TOP_LOGIC_OUTS_L_B6_12", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_LH3_10", + "CMT_MMCM_PHYCTRL_SYNC_BB_UP", + "CMT_TOP_IMUX42_7", + "CMT_TOP_IMUX5_10", + "CMT_TOP_WL1END3_8", + "CMT_TOP_IMUX29_13", + "CMT_TOP_IMUX17_2", + "CMT_TOP_EE2A3_1", + "CMT_TOP_SE4BEG3_14", + "CMT_LR_LOWER_B_MMCM_DI13", + "CMT_TOP_IMUX2_10", + "CMT_TOP_EE4B2_15", + "CMT_TOP_SE2A0_6", + "CMT_TOP_EE2BEG1_13", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_SE4C1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_MONITOR_P_2", + "CMT_TOP_IMUX41_4", + "CMT_TOP_WL1END0_1", + "CMT_TOP_IMUX0_12", + "CMT_TOP_NW4END2_4", + "CMT_TOP_IMUX7_13", + "CMT_TOP_FAN5_1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_NW4A3_15", + "CMT_TOP_IMUX20_10", + "CMT_TOP_WR1END0_15", + "CMT_TOP_NE2A2_11", + "CMT_TOP_EE4BEG1_14", + "CMT_TOP_WW2A2_15", + "CMT_TOP_FAN5_2", + "CMT_TOP_SW2A3_9", + "CMT_TOP_NW2A1_1", + "CMT_TOP_FAN1_1", + "CMT_TOP_IMUX5_7", + "CMT_TOP_NE2A3_15", + "CMT_TOP_IMUX11_11", + "CMT_TOP_NE2A1_5", + "CMT_TOP_CLK1_0", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_SW4END1_11", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_LOGIC_OUTS_L_B10_14", + "CMT_TOP_IMUX28_9", + "CMT_TOP_NW4A1_4", + "CMT_TOP_NE4C2_5", + "CMT_TOP_NE4C0_14", + "CMT_TOP_FAN1_15", + "CMT_TOP_WW4B2_8", + "CMT_TOP_LOGIC_OUTS_L_B8_13", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_WW4END3_13", + "CMT_TOP_WR1END2_13", + "MMCM_CLK_FREQ_BB_REBUF0_NS", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_IMUX6_13", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_WW4B2_6", + "CMT_TOP_LOGIC_OUTS_L_B23_13", + "CMT_TOP_WW2END1_11", + "CMT_LR_LOWER_B_MMCM_TESTOUT21", + "CMT_TOP_IMUX19_0", + "CMT_TOP_BLOCK_OUTS_L_B2_15", + "CMT_TOP_SW4END2_14", + "CMT_TOP_IMUX28_14", + "CMT_TOP_LH3_3", + "CMT_TOP_IMUX38_5", + "CMT_TOP_IMUX31_2", + "CMT_TOP_LOGIC_OUTS_L_B22_15", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_LH4_2", + "CMT_TOP_SE2A0_11", + "CMT_TOP_LH8_13", + "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LOGIC_OUTS_L_B12_15", + "CMT_TOP_LH12_9", + "CMT_TOP_SW2A0_0", + "CMT_TOP_SW2A0_11", + "CMT_TOP_IMUX16_14", + "CMT_TOP_WW4A3_7", + "CMT_TOP_WW4END2_12", + "CMT_TOP_BYP5_10", + "CMT_TOP_LH12_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW2A0_4", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_IMUX30_1", + "CMT_TOP_IMUX0_1", + "CMT_TOP_IMUX39_3", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_FAN6_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_IMUX43_12", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_10", + "CMT_TOP_NE2A2_9", + "CMT_TOP_EE4B1_11", + "CMT_TOP_BYP0_15", + "CMT_TOP_IMUX37_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_NW4END0_10", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_NE4BEG3_14", + "CMT_TOP_IMUX44_1", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX37_7", + "CMT_TOP_CTRL0_12", + "CMT_TOP_IMUX29_1", + "CMT_TOP_FAN6_11", + "CMT_LR_LOWER_B_MMCM_CLKIN1" + ], + "tile_type": "CMT_TOP_R_LOWER_B", + "sites": [ + { + "site_pins": { + "CLKOUT2": "CMT_LR_LOWER_B_MMCM_CLKOUT2", + "TESTOUT25": "CMT_LR_LOWER_B_MMCM_TESTOUT25", + "PSDONE": "CMT_LR_LOWER_B_MMCM_PSDONE", + "DADDR5": "CMT_LR_LOWER_B_MMCM_DADDR5", + "TESTOUT32": "CMT_LR_LOWER_B_MMCM_TESTOUT32", + "TESTOUT29": "CMT_LR_LOWER_B_MMCM_TESTOUT29", + "TESTOUT43": "CMT_LR_LOWER_B_MMCM_TESTOUT43", + "TESTIN29": "CMT_LR_LOWER_B_MMCM_TESTIN29", + "DADDR2": "CMT_LR_LOWER_B_MMCM_DADDR2", + "TESTOUT18": "CMT_LR_LOWER_B_MMCM_TESTOUT18", + "DI10": "CMT_LR_LOWER_B_MMCM_DI10", + "TESTIN14": "CMT_LR_LOWER_B_MMCM_TESTIN14", + "TESTIN21": "CMT_LR_LOWER_B_MMCM_TESTIN21", + "CLKOUT0B": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", + "TESTIN18": "CMT_LR_LOWER_B_MMCM_TESTIN18", + "TESTOUT61": "CMT_LR_LOWER_B_MMCM_TESTOUT61", + "DO12": "CMT_LR_LOWER_B_MMCM_DO12", + "DO10": "CMT_LR_LOWER_B_MMCM_DO10", + "TESTOUT40": "CMT_LR_LOWER_B_MMCM_TESTOUT40", + "TESTOUT23": "CMT_LR_LOWER_B_MMCM_TESTOUT23", + "TESTOUT59": "CMT_LR_LOWER_B_MMCM_TESTOUT59", + "TESTOUT50": "CMT_LR_LOWER_B_MMCM_TESTOUT50", + "TESTOUT49": "CMT_LR_LOWER_B_MMCM_TESTOUT49", + "DI3": "CMT_LR_LOWER_B_MMCM_DI3", + "TESTOUT46": "CMT_LR_LOWER_B_MMCM_TESTOUT46", + "CLKIN1": "CMT_LR_LOWER_B_MMCM_CLKIN1", + "TESTOUT6": "CMT_LR_LOWER_B_MMCM_TESTOUT6", + "TESTOUT12": "CMT_LR_LOWER_B_MMCM_TESTOUT12", + "TESTIN22": "CMT_LR_LOWER_B_MMCM_TESTIN22", + "DI15": "CMT_LR_LOWER_B_MMCM_DI15", + "DCLK": "CMT_LR_LOWER_B_MMCM_DCLK", + "CLKFBIN": "CMT_LR_LOWER_B_MMCM_CLKFBIN", + "DI9": "CMT_LR_LOWER_B_MMCM_DI9", + "CLKINSEL": "CMT_LR_LOWER_B_MMCM_CLKINSEL", + "TESTIN30": "CMT_LR_LOWER_B_MMCM_TESTIN30", + "TESTOUT0": "CMT_LR_LOWER_B_MMCM_TESTOUT0", + "TESTOUT60": "CMT_LR_LOWER_B_MMCM_TESTOUT60", + "TESTOUT9": "CMT_LR_LOWER_B_MMCM_TESTOUT9", + "DO0": "CMT_LR_LOWER_B_MMCM_DO0", + "TESTOUT35": "CMT_LR_LOWER_B_MMCM_TESTOUT35", + "TESTOUT47": "CMT_LR_LOWER_B_MMCM_TESTOUT47", + "DO3": "CMT_LR_LOWER_B_MMCM_DO3", + "DI4": "CMT_LR_LOWER_B_MMCM_DI4", + "DI0": "CMT_LR_LOWER_B_MMCM_DI0", + "DI7": "CMT_LR_LOWER_B_MMCM_DI7", + "TESTOUT57": "CMT_LR_LOWER_B_MMCM_TESTOUT57", + "TESTIN4": "CMT_LR_LOWER_B_MMCM_TESTIN4", + "TESTOUT24": "CMT_LR_LOWER_B_MMCM_TESTOUT24", + "DADDR3": "CMT_LR_LOWER_B_MMCM_DADDR3", + "TESTOUT63": "CMT_LR_LOWER_B_MMCM_TESTOUT63", + "TESTOUT48": "CMT_LR_LOWER_B_MMCM_TESTOUT48", + "CLKOUT3B": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", + "TESTIN1": "CMT_LR_LOWER_B_MMCM_TESTIN1", + "TESTOUT27": "CMT_LR_LOWER_B_MMCM_TESTOUT27", + "TESTOUT13": "CMT_LR_LOWER_B_MMCM_TESTOUT13", + "TESTOUT7": "CMT_LR_LOWER_B_MMCM_TESTOUT7", + "CLKOUT4": "CMT_LR_LOWER_B_MMCM_CLKOUT4", + "TESTOUT3": "CMT_LR_LOWER_B_MMCM_TESTOUT3", + "TESTIN28": "CMT_LR_LOWER_B_MMCM_TESTIN28", + "TESTOUT54": "CMT_LR_LOWER_B_MMCM_TESTOUT54", + "RST": "CMT_LR_LOWER_B_MMCM_RST", + "TESTOUT8": "CMT_LR_LOWER_B_MMCM_TESTOUT8", + "CLKOUT5": "CMT_LR_LOWER_B_MMCM_CLKOUT5", + "DO13": "CMT_LR_LOWER_B_MMCM_DO13", + "PSEN": "CMT_LR_LOWER_B_MMCM_PSEN", + "TESTOUT39": "CMT_LR_LOWER_B_MMCM_TESTOUT39", + "TESTOUT51": "CMT_LR_LOWER_B_MMCM_TESTOUT51", + "TESTOUT20": "CMT_LR_LOWER_B_MMCM_TESTOUT20", + "PWRDWN": "CMT_LR_LOWER_B_MMCM_PWRDWN", + "TESTIN27": "CMT_LR_LOWER_B_MMCM_TESTIN27", + "TESTOUT52": "CMT_LR_LOWER_B_MMCM_TESTOUT52", + "DI13": "CMT_LR_LOWER_B_MMCM_DI13", + "TESTIN24": "CMT_LR_LOWER_B_MMCM_TESTIN24", + "TESTIN10": "CMT_LR_LOWER_B_MMCM_TESTIN10", + "DO1": "CMT_LR_LOWER_B_MMCM_DO1", + "PSINCDEC": "CMT_LR_LOWER_B_MMCM_PSINCDEC", + "DADDR4": "CMT_LR_LOWER_B_MMCM_DADDR4", + "TESTIN11": "CMT_LR_LOWER_B_MMCM_TESTIN11", + "TESTIN6": "CMT_LR_LOWER_B_MMCM_TESTIN6", + "DI2": "CMT_LR_LOWER_B_MMCM_DI2", + "DADDR0": "CMT_LR_LOWER_B_MMCM_DADDR0", + "DO8": "CMT_LR_LOWER_B_MMCM_DO8", + "DI12": "CMT_LR_LOWER_B_MMCM_DI12", + "DO14": "CMT_LR_LOWER_B_MMCM_DO14", + "TESTOUT34": "CMT_LR_LOWER_B_MMCM_TESTOUT34", + "DI6": "CMT_LR_LOWER_B_MMCM_DI6", + "TESTOUT15": "CMT_LR_LOWER_B_MMCM_TESTOUT15", + "TESTOUT14": "CMT_LR_LOWER_B_MMCM_TESTOUT14", + "DI5": "CMT_LR_LOWER_B_MMCM_DI5", + "TESTIN25": "CMT_LR_LOWER_B_MMCM_TESTIN25", + "DI11": "CMT_LR_LOWER_B_MMCM_DI11", + "CLKOUT3": "CMT_LR_LOWER_B_MMCM_CLKOUT3", + "TESTIN23": "CMT_LR_LOWER_B_MMCM_TESTIN23", + "TESTOUT2": "CMT_LR_LOWER_B_MMCM_TESTOUT2", + "DADDR1": "CMT_LR_LOWER_B_MMCM_DADDR1", + "TESTOUT30": "CMT_LR_LOWER_B_MMCM_TESTOUT30", + "TESTIN12": "CMT_LR_LOWER_B_MMCM_TESTIN12", + "DWE": "CMT_LR_LOWER_B_MMCM_DWE", + "TMUXOUT": "CMT_LR_LOWER_B_MMCM_TMUXOUT", + "TESTOUT11": "CMT_LR_LOWER_B_MMCM_TESTOUT11", + "TESTIN31": "CMT_LR_LOWER_B_MMCM_TESTIN31", + "DO9": "CMT_LR_LOWER_B_MMCM_DO9", + "DI14": "CMT_LR_LOWER_B_MMCM_DI14", + "TESTOUT4": "CMT_LR_LOWER_B_MMCM_TESTOUT4", + "TESTOUT58": "CMT_LR_LOWER_B_MMCM_TESTOUT58", + "TESTOUT36": "CMT_LR_LOWER_B_MMCM_TESTOUT36", + "TESTOUT56": "CMT_LR_LOWER_B_MMCM_TESTOUT56", + "PSCLK": "CMT_LR_LOWER_B_MMCM_PSCLK", + "TESTOUT44": "CMT_LR_LOWER_B_MMCM_TESTOUT44", + "CLKFBOUTB": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", + "TESTIN26": "CMT_LR_LOWER_B_MMCM_TESTIN26", + "TESTOUT22": "CMT_LR_LOWER_B_MMCM_TESTOUT22", + "TESTIN5": "CMT_LR_LOWER_B_MMCM_TESTIN5", + "TESTIN7": "CMT_LR_LOWER_B_MMCM_TESTIN7", + "TESTOUT42": "CMT_LR_LOWER_B_MMCM_TESTOUT42", + "TESTOUT17": "CMT_LR_LOWER_B_MMCM_TESTOUT17", + "TESTIN8": "CMT_LR_LOWER_B_MMCM_TESTIN8", + "CLKFBOUT": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", + "TESTIN9": "CMT_LR_LOWER_B_MMCM_TESTIN9", + "TESTOUT33": "CMT_LR_LOWER_B_MMCM_TESTOUT33", + "DADDR6": "CMT_LR_LOWER_B_MMCM_DADDR6", + "CLKINSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", + "TESTIN20": "CMT_LR_LOWER_B_MMCM_TESTIN20", + "DRDY": "CMT_LR_LOWER_B_MMCM_DRDY", + "TESTIN0": "CMT_LR_LOWER_B_MMCM_TESTIN0", + "DI1": "CMT_LR_LOWER_B_MMCM_DI1", + "DO15": "CMT_LR_LOWER_B_MMCM_DO15", + "CLKIN2": "CMT_LR_LOWER_B_MMCM_CLKIN2", + "DO5": "CMT_LR_LOWER_B_MMCM_DO5", + "DO7": "CMT_LR_LOWER_B_MMCM_DO7", + "TESTOUT31": "CMT_LR_LOWER_B_MMCM_TESTOUT31", + "LOCKED": "CMT_LR_LOWER_B_MMCM_LOCKED", + "DO2": "CMT_LR_LOWER_B_MMCM_DO2", + "TESTIN13": "CMT_LR_LOWER_B_MMCM_TESTIN13", + "TESTIN16": "CMT_LR_LOWER_B_MMCM_TESTIN16", + "TESTIN2": "CMT_LR_LOWER_B_MMCM_TESTIN2", + "DI8": "CMT_LR_LOWER_B_MMCM_DI8", + "CLKFBSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", + "TESTOUT5": "CMT_LR_LOWER_B_MMCM_TESTOUT5", + "DO11": "CMT_LR_LOWER_B_MMCM_DO11", + "TESTOUT53": "CMT_LR_LOWER_B_MMCM_TESTOUT53", + "CLKOUT2B": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", + "TESTOUT38": "CMT_LR_LOWER_B_MMCM_TESTOUT38", + "DEN": "CMT_LR_LOWER_B_MMCM_DEN", + "TESTOUT10": "CMT_LR_LOWER_B_MMCM_TESTOUT10", + "TESTOUT62": "CMT_LR_LOWER_B_MMCM_TESTOUT62", + "TESTIN3": "CMT_LR_LOWER_B_MMCM_TESTIN3", + "TESTOUT1": "CMT_LR_LOWER_B_MMCM_TESTOUT1", + "TESTOUT21": "CMT_LR_LOWER_B_MMCM_TESTOUT21", + "TESTIN15": "CMT_LR_LOWER_B_MMCM_TESTIN15", + "TESTOUT16": "CMT_LR_LOWER_B_MMCM_TESTOUT16", + "TESTOUT19": "CMT_LR_LOWER_B_MMCM_TESTOUT19", + "TESTOUT45": "CMT_LR_LOWER_B_MMCM_TESTOUT45", + "TESTOUT26": "CMT_LR_LOWER_B_MMCM_TESTOUT26", + "CLKOUT1": "CMT_LR_LOWER_B_MMCM_CLKOUT1", + "TESTOUT28": "CMT_LR_LOWER_B_MMCM_TESTOUT28", + "TESTOUT55": "CMT_LR_LOWER_B_MMCM_TESTOUT55", + "TESTIN17": "CMT_LR_LOWER_B_MMCM_TESTIN17", + "TESTOUT41": "CMT_LR_LOWER_B_MMCM_TESTOUT41", + "CLKOUT1B": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", + "DO4": "CMT_LR_LOWER_B_MMCM_DO4", + "CLKOUT6": "CMT_LR_LOWER_B_MMCM_CLKOUT6", + "TESTIN19": "CMT_LR_LOWER_B_MMCM_TESTIN19", + "CLKOUT0": "CMT_LR_LOWER_B_MMCM_CLKOUT0", + "DO6": "CMT_LR_LOWER_B_MMCM_DO6", + "TESTOUT37": "CMT_LR_LOWER_B_MMCM_TESTOUT37" + }, + "type": "MMCME2_ADV", + "prefix": "MMCME2_ADV", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_TOP_R_LOWER_T.json b/artix7/tile_type_CMT_TOP_R_LOWER_T.json index 528ee4d..57ac99d 100644 --- a/artix7/tile_type_CMT_TOP_R_LOWER_T.json +++ b/artix7/tile_type_CMT_TOP_R_LOWER_T.json @@ -1,4823 +1,4823 @@ { - "wires": [ - "CMT_TOP_IMUX1_6", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_TOP_WR1END2_4", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX20_3", - "CMT_TOP_EE2A0_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_LH7_3", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX28_8", - "CMT_TOP_EE4B1_1", - "CMT_TOP_NW4END2_5", - "CMT_TOP_WW2A0_3", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_NE2A1_7", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_TOP_IMUX18_4", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_BYP5_2", - "CMT_TOP_EE2A3_5", - "CMT_TOP_IMUX42_4", - "CMT_PHASER_BOT_REFMUX_0", - "CMT_TOP_IMUX19_0", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_TOP_LH11_4", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_TOP_SW4END2_4", - "CMT_TOP_WW2A0_4", - "CMT_TOP_FAN6_0", - "CMT_TOP_WW2END3_7", - "CMT_TOP_BYP6_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_NE2A1_8", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX39_5", - "CMT_TOP_WW2A2_6", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_TOP_SW4END3_3", - "CMT_TOP_WW4B0_3", - "CMT_TOP_BYP3_2", - "CMT_TOP_CTRL0_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_TOP_CLK1_8", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_TOP_NW2A0_1", - "CMT_TOP_FAN3_3", - "CMT_TOP_EE4A3_6", - "CMT_TOP_NW4A0_2", - "CMT_TOP_WW2END0_8", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SE4BEG1_8", - "CMT_LR_LOWER_T_CLK_MMCM10", - "CMT_TOP_WW4A2_2", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX23_0", - "CMT_TOP_LH12_4", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_TOP_WW4C0_8", - "CMT_TOP_BYP6_1", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_IMUX15_1", - "CMT_TOP_SE2A0_0", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_FAN0_6", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_SW2A2_1", - "CMT_TOP_FAN0_1", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_PHASER_IN_B_RCLK1", - "CMT_TOP_SW4END0_1", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_TOP_WW4END0_6", - "CMT_TOP_IMUX1_0", - "CMT_TOP_SW2A1_4", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW4END2_7", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_NE4BEG2_5", - "CMT_PHASER_OUT_B_RDEN_TOFIFO", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE2A2_4", - "CMT_TOP_WL1END0_4", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_IMUX26_6", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_IMUX14_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_BYP7_6", - "CMT_TOP_NW2A2_8", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_SE2A1_0", - "CMT_TOP_CTRL1_4", - "CMT_TOP_IMUX0_0", - "CMT_TOP_SW4END3_4", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_WW4C3_1", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_LR_LOWER_T_CLK_MMCM13", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_NW4END1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_WL1END0_6", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4A0_3", - "CMT_TOP_NW4A3_6", - "CMT_TOP_BYP2_5", - "CMT_TOP_IMUX10_0", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_TOP_NW2A2_1", - "CMT_TOP_ICLK_0", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_IMUX33_4", - "CMT_TOP_NW2A1_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_NE4C0_0", - "CMT_TOP_EE4B0_4", - "CMT_TOP_NE2A1_0", - "CMT_TOP_WR1END0_6", - "CMT_TOP_LH12_2", - "CMT_TOP_FAN5_5", - "CMT_TOP_SW4END0_2", - "CMT_TOP_IMUX4_8", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SE4BEG3_1", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_TOP_IMUX43_6", - "CMT_PHASER_IN_DB_TESTIN7", - "CMT_PHASER_IN_B_ICLK", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4A3_7", - "CMT_TOP_NE4C3_6", - "CMT_TOP_LH9_1", - "CMT_TOP_EE4A3_1", - "CMT_TOP_WW2A0_6", - "CMT_TOP_BYP6_3", - "CMT_TOP_FAN2_6", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_OCLK_3", - "CMT_TOP_WR1END1_1", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_EE4C2_8", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX10_4", - "CMT_TOP_OCLK_8", - "CMT_TOP_FAN4_3", - "CMT_TOP_BYP0_1", - "CMT_TOP_NE2A0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_TOP_IMUX31_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_ICLKDIV_3", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_LH4_4", - "CMT_TOP_EE4B3_0", - "CMT_TOP_LH10_7", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_FAN4_8", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NW4A3_1", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_SW2A3_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_OCLK_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_IMUX33_1", - "CMT_TOP_EE4C1_5", - "CMT_TOP_WW4B3_0", - "CMT_TOP_SE2A0_2", - "CMT_TOP_LH11_7", - "CMT_TOP_IMUX31_1", - "CMT_TOP_LH2_1", - "CMT_TOP_IMUX12_6", - "CMT_TOP_SW4END3_6", - "CMT_TOP_LH6_8", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WW2END1_1", - "CMT_TOP_NE2A3_3", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_TOP_IMUX12_8", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_EE4A1_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_WL1END2_5", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX18_1", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_IMUX42_5", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_LR_LOWER_T_CLK_IN3_HCLK", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_IMUX20_8", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_IMUX39_1", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_NE2A3_2", - "CMT_TOP_IMUX24_7", - "CMT_TOP_NW2A3_2", - "CMT_TOP_SE2A0_6", - "CMT_TOP_IMUX30_3", - "CMT_TOP_OCLK_6", - "CMT_TOP_IMUX10_6", - "CMT_TOP_SE2A2_7", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_IMUX4_2", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_EE4B3_8", - "CMT_TOP_IMUX5_8", - "CMT_TOP_WW2A1_1", - "CMT_PHASER_OUT_A_RDEN_TOFIFO", - "CMT_TOP_IMUX37_6", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX28_4", - "CMT_TOP_NE4BEG1_6", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_TOP_IMUX2_7", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_TOP_BYP4_8", - "CMT_TOP_WW4B2_3", - "CMT_TOP_IMUX47_5", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_TOP_WW4B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_WW4C2_5", - "CMT_TOP_IMUX38_5", - "CMT_TOP_EE4B2_5", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_TOP_IMUX44_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_SW4END1_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_SE4C1_7", - "CMT_TOP_IMUX18_6", - "CMT_TOP_SE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_IMUX44_6", - "CMT_TOP_OCLK_1", - "CMT_TOP_WL1END3_6", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_SE2A2_0", - "CMT_TOP_IMUX27_0", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_SE2A2_8", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW4END2_2", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_TOP_WR1END3_7", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_PHASERA_DTSBUS1", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_LH11_8", - "CMT_TOP_WW4END2_4", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_EE2A2_3", - "CMT_TOP_LH4_7", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_WW4A0_8", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_TOP_LH1_6", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX17_6", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_IMUX6_0", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_BYP4_6", - "CMT_LR_LOWER_T_CLK_MMCM0", - "CMT_TOP_BYP6_7", - "CMT_TOP_LH5_5", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_EE2A2_5", - "CMT_TOP_NE2A1_1", - "CMT_TOP_WW4END1_8", - "CMT_TOP_SW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LH4_8", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_IMUX45_1", - "CMT_TOP_CTRL0_3", - "CMT_TOP_WW4B3_1", - "CMT_TOP_NW4A2_4", - "CMT_TOP_SW4A0_4", - "CMT_TOP_FAN2_4", - "CMT_TOP_IMUX43_1", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_TOP_IMUX19_5", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_TOP_EE4B1_0", - "CMT_TOP_BYP7_7", - "CMT_TOP_SE4C3_3", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_TOP_WR1END0_3", - "CMT_TOP_SW4A2_8", - "CMT_TOP_NE4C3_1", - "CMT_TOP_WW2A1_3", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SW4A0_3", - "CMT_TOP_EE4C3_0", - "CMT_TOP_CLK0_6", - "CMT_TOP_WW4C1_3", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_TOP_SE2A3_4", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_TOP_CTRL1_8", - "CMT_TOP_LH7_6", - "CMT_TOP_WL1END1_1", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_IMUX41_1", - "CMT_TOP_NE4C2_7", - "CMT_TOP_EE4B2_0", - "CMT_TOP_LH5_7", - "CMT_TOP_SW4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_IMUX41_4", - "CMT_TOP_LH7_8", - "CMT_TOP_IMUX2_5", - "CMT_TOP_WR1END2_7", - "CMT_TOP_FAN6_3", - "CMT_TOP_WW2A0_7", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_LR_LOWER_T_CLK_PERF2", - "CMT_TOP_BYP4_2", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_TOP_CLK0_1", - "CMT_TOP_IMUX6_4", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE2A2_8", - "CMT_TOP_WW4END0_2", - "CMT_TOP_SE4C3_7", - "CMT_PHASER_IN_B_ICLKDIV", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4A0_7", - "CMT_TOP_LH9_3", - "CMT_TOP_EL1BEG2_0", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_TOP_NE2A0_5", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_TOP_EE4C3_2", - "CMT_R_TOP_LOWER_B_CLKINT_0", - "CMT_PHASER_DOWN_DQS_TO_PHASER_A", - "CMT_TOP_SE4C2_5", - "CMT_TOP_IMUX32_0", - "CMT_TOP_SW2A3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_TOP_WW2END3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_NE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4C1_3", - "CMT_TOP_IMUX43_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_IMUX27_5", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_CTRL0_8", - "CMT_TOP_EE4C0_0", - "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "CMT_TOP_NW2A0_4", - "CMT_TOP_SE4BEG3_6", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_TOP_IMUX33_3", - "CMT_TOP_NW4END2_0", - "CMT_TOP_IMUX13_6", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_IMUX1_2", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_EE4B1_3", - "CMT_TOP_WL1END1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_TOP_LH4_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_NW4END3_2", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_IMUX21_1", - "CMT_TOP_CTRL1_0", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_SW2A3_0", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_TOP_SW4END0_0", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_TOP_WW4A1_2", - "CMT_TOP_BYP7_5", - "CMT_TOP_ICLK_7", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW2END1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_PHASER_DOWN_DQS_TO_PHASER_B", - "CMT_TOP_WW4C0_3", - "CMT_PHASER_IN_CA_RCLK", - "CMT_TOP_FAN1_0", - "CMT_TOP_SW4END1_4", - "CMT_TOP_EE4C3_3", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX9_5", - "CMT_TOP_WW4A0_1", - "CMT_TOP_FAN6_8", - "CMT_TOP_WW4A0_0", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_TOP_CTRL0_5", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_TOP_EE4B0_8", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX40_1", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_IMUX7_4", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4C3_4", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_SE4BEG3_4", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_TOP_BYP7_2", - "CMT_TOP_SE4C1_0", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_TOP_IMUX15_4", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW4A1_2", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_TOP_BYP2_8", - "CMT_TOP_WW2END2_2", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_IMUX23_3", - "CMT_TOP_WW4C0_0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_TOP_BYP6_8", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_TOP_WW2A2_3", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_IMUX28_0", - "CMT_TOP_EE4A1_7", - "CMT_TOP_IMUX31_3", - "CMT_TOP_EE4A2_0", - "CMT_TOP_IMUX25_8", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_PHASER_B_ICLK_TOIOI", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_TOP_IMUX35_2", - "CMT_TOP_NE4BEG2_6", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NW2A3_0", - "CMT_TOP_WL1END0_3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_PHASER_BOT_IRANKA0", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2END1_3", - "CMT_TOP_SW2A2_5", - "CMT_TOP_ER1BEG3_1", - "CMT_PHASERREF_DOWN_PHASEROUT_B", - "CMT_TOP_SW2A3_5", - "CMT_TOP_NW4END0_5", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_IMUX37_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END3_6", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_IMUX14_4", - "CMT_TOP_LH10_3", - "CMT_TOP_LH6_5", - "CMT_TOP_LH10_1", - "CMT_TOP_IMUX17_1", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_TOP_BYP4_0", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_IMUX37_5", - "CMT_TOP_EE2BEG2_2", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_TOP_WL1END3_2", - "CMT_TOP_IMUX7_7", - "CMT_TOP_SW4A2_7", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX20_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_SE4C3_4", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_PHASER_BOT_IRANKB1", - "CMT_TOP_FAN4_0", - "CMT_TOP_IMUX41_7", - "CMT_PHASER_B_OCLK90_TOIOI", - "CMT_TOP_IMUX33_5", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_LH6_1", - "CMT_LR_LOWER_T_CLK_MMCM4", - "CMT_TOP_WW4C2_7", - "CMT_TOP_BYP5_4", - "CMT_PHASER_BOT_IBURSTPENDING1", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_IMUX11_4", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_NE4C3_0", - "CMT_TOP_WW4END1_0", - "CMT_TOP_FAN7_5", - "CMT_TOP_BYP0_8", - "CMT_TOP_IMUX22_2", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_WW4END3_2", - "CMT_TOP_FAN4_5", - "CMT_TOP_IMUX30_8", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_IMUX47_0", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_TOP_EE4B2_6", - "CMT_PHASER_OUT_B_OCLK1X_90", - "CMT_TOP_IMUX16_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_SW4A1_3", - "CMT_TOP_NW4END1_6", - "CMT_TOP_WW4END2_0", - "CMT_TOP_IMUX34_4", - "CMT_TOP_SW4END2_7", - "CMT_TOP_IMUX19_3", - "CMT_TOP_LH12_0", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_NW4END2_8", - "CMT_TOP_EE4A1_8", - "CMT_TOP_WW4B1_2", - "CMT_TOP_IMUX36_0", - "CMT_TOP_FAN7_8", - "CMT_TOP_LH3_3", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX10_5", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_WW2A3_0", - "CMT_LR_LOWER_T_CLK_IN1_HCLK", - "CMT_TOP_LH3_4", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX40_4", - "CMT_TOP_FAN5_6", - "CMT_TOP_IMUX38_0", - "CMT_TOP_IMUX30_6", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_IMUX23_5", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_LH2_3", - "CMT_TOP_EE4C3_8", - "CMT_TOP_NW4A3_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SW4END2_3", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_TOP_SW4END3_2", - "CMT_TOP_LH8_5", - "CMT_TOP_WW2A2_5", - "CMT_PHASER_OUT_B_OCLK", - "CMT_TOP_WW4A1_3", - "CMT_TOP_IMUX29_0", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_WR1END0_4", - "CMT_TOP_NW2A0_2", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_NW4END0_2", - "CMT_TOP_FAN1_1", - "CMT_TOP_LH1_4", - "CMT_TOP_SE4C3_0", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_TOP_IMUX16_7", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_TOP_SE2A1_5", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_SE4C0_7", - "CMT_TOP_FAN6_5", - "CMT_TOP_EE4A2_4", - "CMT_TOP_WR1END0_7", - "CMT_TOP_EE4A3_7", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_WR1END1_0", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_TOP_IMUX46_3", - "CMT_TOP_SW4END2_2", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_PHASERA_DTSBUS0", - "CMT_TOP_WW4B3_5", - "CMT_TOP_IMUX6_7", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_TOP_NW4A0_7", - "CMT_TOP_IMUX32_1", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4C1_6", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_TOP_FAN2_0", - "CMT_TOP_WW4A0_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX37_2", - "CMT_TOP_EE4C1_1", - "CMT_TOP_MONITOR_P_7", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_TOP_WW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_IMUX45_8", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_TOP_FAN0_4", - "CMT_TOP_IMUX20_2", - "CMT_TOP_SW4A2_6", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_FAN0_8", - "CMT_TOP_SE4C0_3", - "CMT_TOP_IMUX29_6", - "CMT_TOP_EE2BEG2_6", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_WL1END1_6", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_WW2END1_2", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NW4A0_0", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_SW4A1_6", - "CMT_TOP_EE4A1_3", - "CMT_TOP_BYP1_8", - "CMT_PHASER_BOT_IRANKA1", - "CMT_TOP_WW2END2_1", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EE4B2_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_EE4B3_2", - "CMT_TOP_SE4C1_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_IMUX36_3", - "CMT_TOP_SE4C2_3", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_TOP_IMUX26_1", - "CMT_TOP_CLK1_2", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_TOP_NW4END0_3", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX27_8", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_6", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_TOP_IMUX38_1", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_WL1END0_8", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_IMUX29_7", - "CMT_TOP_SE2A1_2", - "CMT_TOP_NE2A3_6", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4B1_3", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_IMUX27_2", - "CMT_TOP_NE2A1_6", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_NW2A3_8", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_TOP_LH7_1", - "CMT_TOP_WW4END1_7", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_TOP_SE2A2_3", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_FAN7_4", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_SE4C3_6", - "CMT_TOP_NE4C3_3", - "CMT_TOP_CTRL0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_FAN2_2", - "CMT_TOP_NW4END1_2", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX18_7", - "CMT_TOP_WW4END2_7", - "CMT_TOP_NW4END1_0", - "CMT_TOP_EE4C0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_SE4BEG1_4", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_TOP_IMUX29_5", - "CMT_TOP_NW2A1_5", - "CMT_TOP_WW2END0_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_NW4A1_0", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX40_7", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_TOP_BYP6_2", - "CMT_TOP_IMUX42_7", - "CMT_TOP_BYP5_5", - "CMT_TOP_WR1END0_8", - "CMT_PHASER_OUT_A_OCLK1X_90", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX2_1", - "CMT_TOP_FAN5_7", - "CMT_TOP_SE2A2_6", - "CMT_TOP_EE4B1_8", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4END3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4END1_6", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_EE4C0_8", - "CMT_TOP_SE4C0_1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_TOP_EE2A0_1", - "CMT_TOP_NW2A1_8", - "CMT_TOP_SW2A3_1", - "CMT_TOP_EE2A1_0", - "CMT_TOP_WW4C3_5", - "CMT_TOP_IMUX24_1", - "CMT_TOP_BYP1_0", - "CMT_TOP_LH9_4", - "CMT_TOP_WW4B0_8", - "CMT_TOP_SW4END1_1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_TOP_WW4B0_7", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_NE2A1_2", - "CMT_PHASER_B_TOMMCM_OCLK1X_90", - "CMT_TOP_WW4B2_0", - "CMT_TOP_LH10_8", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_IMUX30_4", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WW2END3_3", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_FAN1_6", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_WW2END3_1", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_TOP_SE4C1_2", - "CMT_TOP_NW2A2_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_EE4A0_0", - "CMT_TOP_IMUX22_0", - "CMT_TOP_EE4A2_1", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_IMUX46_8", - "CMT_TOP_WW2A3_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4A0_6", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_EE4B0_5", - "CMT_TOP_NW2A0_3", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_TOP_ICLK_2", - "CMT_TOP_WW4B2_7", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_IMUX6_2", - "CMT_TOP_NE4C2_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_NW4END3_0", - "CMT_TOP_SW2A1_2", - "CMT_LR_LOWER_T_CLK_MMCM11", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_TOP_FAN1_5", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_IMUX10_8", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_TOP_CTRL0_7", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_TOP_NW4END3_7", - "CMT_TOP_LH8_8", - "CMT_TOP_IMUX44_2", - "CMT_TOP_SW2A2_0", - "CMT_TOP_WW4A2_5", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_TOP_SW4A2_2", - "CMT_PHASERA_CTSBUS1", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2A1_6", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_LH10_2", - "CMT_TOP_IMUX38_4", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE2A2_5", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_TOP_IMUX9_6", - "CMT_TOP_NW4END3_3", - "CMT_TOP_IMUX45_2", - "CMT_TOP_FAN6_1", - "CMT_TOP_IMUX3_8", - "CMT_PHASER_IN_CA_ICLK", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_TOP_IMUX13_5", - "CMT_TOP_SE4C1_3", - "CMT_TOP_WL1END2_6", - "CMT_TOP_LH11_2", - "CMT_TOP_SW4A3_8", - "CMT_PHASER_IN_DB_RST", - "CMT_TOP_LH12_8", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_SE2A0_1", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_TOP_IMUX37_4", - "CMT_TOP_WW4END0_1", - "CMT_TOP_EE4B0_6", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_BYP3_0", - "CMT_TOP_EE4B0_7", - "CMT_TOP_NE4C1_3", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_TOP_SW4END2_0", - "CMT_TOP_NW2A1_0", - "CMT_TOP_FAN5_4", - "CMT_TOP_NE4C1_1", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EE2A1_4", - "CMT_TOP_IMUX1_5", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_SE4BEG0_1", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX35_1", - "CMT_TOP_WW2END1_8", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_IMUX39_4", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_ER1BEG2_6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_TOP_EE4B2_2", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW4A1_5", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WW4C3_4", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_SE2A2_5", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_NE2A0_6", - "CMT_TOP_BYP1_5", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_FAN1_3", - "CMT_TOP_SE2A3_7", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_6", - "CMT_TOP_SW2A0_4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_TOP_SW4END3_5", - "CMT_TOP_EL1BEG3_5", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_TOP_WW4END0_7", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_IMUX25_2", - "CMT_TOP_WR1END3_4", - "CMT_TOP_FAN0_3", - "CMT_TOP_IMUX42_6", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_WW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_NE2A2_8", - "CMT_TOP_WW4END3_4", - "CMT_TOP_FAN0_7", - "CMT_TOP_IMUX32_3", - "CMT_TOP_WW2A3_7", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_WW4B0_1", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_EL1BEG1_0", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_TOP_WL1END2_2", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_WW4B1_0", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_IMUX42_2", - "CMT_TOP_LH8_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_EE4A0_5", - "CMT_TOP_BYP6_5", - "CMT_TOP_WL1END2_3", - "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "CMT_TOP_IMUX39_2", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_SE2A1_8", - "CMT_R_TOP_LOWER_B_CLKINT_1", - "CMT_TOP_NE4C1_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_NW2A0_6", - "CMT_TOP_WR1END3_0", - "CMT_TOP_FAN3_1", - "CMT_PHASERREF_DOWN_PHASERIN_A", - "CMT_TOP_WW4A3_8", - "CMT_TOP_SW2A1_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_LH4_5", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_TOP_IMUX40_5", - "CMT_TOP_SW4END1_7", - "CMT_TOP_NW4END3_4", - "CMT_TOP_EE4C3_4", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_WR1END0_0", - "CMT_TOP_NW4A0_5", - "CMT_BOT_HCLKMUX_CLKINT_1", - "CMT_TOP_CTRL1_5", - "CMT_TOP_SE4C3_1", - "CMT_LR_LOWER_T_CLK_MMCM5", - "CMT_TOP_IMUX18_3", - "CMT_TOP_EE2A1_1", - "CMT_TOP_IMUX13_4", - "CMT_TOP_SW2A0_1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_IMUX16_5", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_TOP_LH9_5", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_TOP_WW2END0_6", - "CMT_TOP_IMUX0_3", - "CMT_TOP_EE2A1_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_OCLK_5", - "CMT_TOP_EE4B0_1", - "CMT_TOP_WL1END3_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_IMUX47_3", - "CMT_TOP_FAN5_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_NE2A2_7", - "CMT_TOP_WW4B1_5", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WR1END1_6", - "CMT_TOP_BYP0_5", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_PHASER_OUT_B_RDCLK_TOFIFO", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_7", - "CMT_PHASER_IN_A_ICLKDIV", - "CMT_TOP_SE2A2_2", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_WR1END3_8", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_TOP_LH9_7", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_IMUX9_4", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW2END3_5", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SW4END0_3", - "CMT_TOP_WR1END2_6", - "CMT_TOP_IMUX46_0", - "CMT_TOP_WW2A3_4", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_CTRL1_2", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LH7_0", - "CMT_TOP_LH6_6", - "CMT_LR_LOWER_T_CLK_MMCM6", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_WW2A2_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_IMUX2_0", - "CMT_TOP_CTRL0_2", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_TOP_WL1END1_3", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_EE4B3_5", - "CMT_TOP_IMUX5_3", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_IMUX38_2", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_SW4END0_5", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NW2A1_1", - "CMT_TOP_BYP4_1", - "CMT_TOP_CLK0_5", - "CMT_TOP_BYP5_7", - "CMT_TOP_IMUX6_1", - "CMT_TOP_SW4A3_0", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_OCLK_4", - "CMT_TOP_SW2A3_7", - "CMT_TOP_LH12_6", - "CMT_TOP_IMUX4_6", - "CMT_TOP_WR1END2_3", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX22_4", - "CMT_TOP_NW2A2_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_SE4C1_4", - "CMT_TOP_WW4C0_4", - "CMT_TOP_IMUX6_8", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_WW4A2_4", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX32_2", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_TOP_IMUX28_1", - "CMT_TOP_SE2A3_6", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LH8_1", - "CMT_TOP_WW4A0_3", - "CMT_TOP_IMUX20_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_IMUX35_7", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EE4A3_5", - "CMT_TOP_LH6_4", - "CMT_TOP_CLK1_0", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_IMUX27_4", - "CMT_TOP_ICLK_8", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_SW4A1_7", - "CMT_TOP_IMUX40_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_CLK0_8", - "CMT_TOP_IMUX7_2", - "MMCM_CLK_FREQBB_REBUFOUT0", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_TOP_FAN4_2", - "CMT_TOP_CLK1_1", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW4A1_7", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_LH12_3", - "CMT_TOP_WW2A1_8", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_NE4C1_7", - "CMT_TOP_WW4B2_1", - "CMT_PHASER_BOT_ENCALIB1", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE4BEG1_4", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG3_7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_TOP_WL1END2_8", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_TOP_LH8_2", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_SE2A3_2", - "CMT_TOP_LH8_3", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_TOP_IMUX13_8", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_IMUX23_7", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_WW2END1_0", - "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "CMT_TOP_IMUX39_0", - "CMT_TOP_WW4C3_2", - "CMT_TOP_IMUX30_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_EE4B0_2", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_TOP_IMUX12_4", - "CMT_PHASER_BOT_OBURSTPENDING0", - "CMT_TOP_IMUX33_8", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_SW2A2_2", - "CMT_TOP_LH5_1", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "CMT_TOP_LH10_0", - "CMT_PHASER_BOT_IBURSTPENDING0", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_LH6_3", - "CMT_TOP_EE2A0_0", - "CMT_TOP_WR1END3_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_IMUX12_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_IMUX21_8", - "CMT_PHASERA_DQSBUS0", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_LR_LOWER_T_CLK_MMCM2", - "CMT_TOP_IMUX5_1", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_IMUX10_2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_TOP_IMUX34_7", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_NW4A2_7", - "CMT_TOP_EE4BEG0_7", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EE2A2_1", - "CMT_TOP_LH4_1", - "CMT_TOP_FAN4_6", - "CMT_PHASERREF_DOWN_PHASERIN_B", - "CMT_TOP_WW4END1_1", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_FAN0_5", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_TOP_NE4C0_5", - "CMT_TOP_IMUX3_3", - "CMT_TOP_SW2A0_8", - "CMT_TOP_NW2A2_2", - "CMT_TOP_BYP1_1", - "CMT_TOP_IMUX37_1", - "CMT_TOP_NE4BEG3_5", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_SW4END1_5", - "CMT_TOP_FAN7_0", - "CMT_TOP_LH1_7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_BYP4_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_EE2A1_6", - "CMT_TOP_NE2A1_5", - "CMT_TOP_EE2A3_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_FAN3_4", - "CMT_TOP_NW4END2_6", - "CMT_TOP_LH7_5", - "CMT_TOP_IMUX18_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_WW4C2_0", - "CMT_TOP_SE2A3_3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_TOP_WL1END2_4", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_IMUX9_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_IMUX43_8", - "CMT_TOP_SE2A3_5", - "CMT_TOP_LH5_0", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4C1_6", - "CMT_TOP_WW4C0_2", - "CMT_TOP_LH12_7", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_WW2END2_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_BYP4_5", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_3", - "CMT_TOP_NE2A2_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_NE4C1_0", - "CMT_PHASER_OUT_CA_RST", - "CMT_TOP_IMUX11_1", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_EE2A3_0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_TOP_WR1END1_2", - "CMT_TOP_LH4_6", - "CMT_TOP_WW4B2_5", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_TOP_FAN7_7", - "CMT_TOP_SE2A1_4", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_LR_LOWER_T_CLK_PERF3", - "CMT_TOP_SE4C0_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_IMUX2_8", - "CMT_TOP_LH5_3", - "CMT_TOP_WW2END3_2", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_TOP_WR1END2_0", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_TOP_ER1BEG0_4", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_IMUX28_2", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_IMUX25_1", - "CMT_TOP_WW4C1_4", - "CMT_TOP_EE4C2_7", - "CMT_TOP_IMUX31_8", - "CMT_TOP_LH12_1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_TOP_NE2A0_3", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_TOP_LH3_2", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4END2_8", - "CMT_TOP_NE4C0_4", - "CMT_TOP_LH11_0", - "CMT_TOP_WW2A1_2", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_FAN6_2", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_BYP1_7", - "CMT_TOP_IMUX22_7", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WL1END2_0", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SW4A1_0", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_WL1END3_5", - "CMT_TOP_ICLK_3", - "CMT_TOP_IMUX0_5", - "CMT_TOP_SW4A0_8", - "CMT_TOP_IMUX1_8", - "CMT_TOP_FAN7_6", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX14_6", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_TOP_IMUX19_4", - "CMT_TOP_WW4C2_4", - "CMT_PHASER_B_TOMMCM_OCLKDIV", - "CMT_TOP_WW4B1_8", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LH4_0", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_BYP2_7", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_TOP_IMUX44_7", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_TOP_BYP2_2", - "CMT_TOP_EE4B2_4", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_TOP_WW4B0_2", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_TOP_CLK0_2", - "CMT_TOP_IMUX3_2", - "CMT_LR_LOWER_T_CLK_MMCM7", - "CMT_TOP_WL1END1_5", - "CMT_TOP_EE4C3_7", - "CMT_TOP_IMUX11_2", - "CMT_TOP_WW2END0_5", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4BEG1_0", - "CMT_PHASERA_DQSBUS1", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_WW4B1_1", - "CMT_TOP_LH7_2", - "CMT_TOP_WW4A1_4", - "CMT_TOP_CLK0_3", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LH6_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_EE4B2_8", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_TOP_WW4A3_6", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_SE4C2_0", - "CMT_TOP_IMUX23_2", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_OUT_DB_DIVIDERST", - "CMT_TOP_WW4END3_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_NW4A0_8", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_EE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_TOP_WW4END3_0", - "CMT_TOP_IMUX27_1", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_TOP_CTRL1_3", - "CMT_TOP_IMUX21_2", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_CLK1_3", - "CMT_TOP_IMUX34_0", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE2A3_8", - "CMT_TOP_LH11_6", - "CMT_TOP_SW2A0_0", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_FAN7_3", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_TOP_IMUX33_6", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_SW2A3_2", - "CMT_TOP_IMUX44_5", - "CMT_TOP_WW2A0_2", - "CMT_TOP_IMUX11_3", - "CMT_LR_LOWER_T_CLK_IN2_HCLK", - "CMT_TOP_WW4END1_6", - "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_WR1END3_1", - "CMT_TOP_IMUX24_5", - "CMT_TOP_WW4C1_7", - "CMT_TOP_NE2A0_0", - "CMT_TOP_WW4C2_8", - "CMT_TOP_EE2A3_8", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX28_6", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_EE4A2_2", - "CMT_TOP_IMUX13_1", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_TOP_IMUX24_0", - "CMT_TOP_NW4END2_4", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW4C3_3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE2BEG0_5", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_TOP_EE4C3_5", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_IMUX0_2", - "CMT_TOP_NW4END0_6", - "CMT_TOP_EE4C0_5", - "CMT_TOP_SE4BEG1_2", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_TOP_SE2A3_0", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX36_4", - "CMT_TOP_NW2A3_6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_TOP_NE2A3_0", - "CMT_TOP_LH12_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_EE4C2_3", - "CMT_TOP_FAN2_7", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WR1END1_4", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_TOP_IMUX31_2", - "CMT_TOP_LH5_8", - "CMT_TOP_FAN3_7", - "CMT_TOP_IMUX21_0", - "CMT_TOP_IMUX3_4", - "CMT_TOP_WL1END0_7", - "CMT_TOP_SW2A0_6", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_WW4END3_6", - "CMT_TOP_IMUX7_8", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_IMUX8_6", - "CMT_TOP_EE2A1_5", - "CMT_TOP_NW2A0_8", - "CMT_TOP_EE4A1_1", - "CMT_LR_LOWER_T_CLK_PERF1", - "CMT_TOP_SW2A2_6", - "CMT_TOP_IMUX26_0", - "CMT_TOP_SW4A0_5", - "CMT_TOP_EE2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EL1BEG2_5", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_TOP_EE2A0_6", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX23_1", - "CMT_PHASER_BOT_REFMUX_2", - "CMT_TOP_IMUX15_2", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX3_6", - "CMT_TOP_BYP0_0", - "CMT_TOP_SW4END0_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX47_6", - "CMT_TOP_SW4A2_5", - "CMT_TOP_EE2BEG1_6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_BYP3_4", - "CMT_TOP_CTRL1_6", - "CMT_BOT_HCLKMUX_CLKINT_0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_WW4C2_1", - "CMT_TOP_BYP1_3", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX43_3", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_TOP_NW4A2_8", - "CMT_PHASER_IN_A_RCLK0", - "CMT_TOP_NE2A1_3", - "CMT_TOP_WR1END3_6", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NW4END1_1", - "CMT_TOP_CLK1_5", - "CMT_TOP_WW4C1_0", - "CMT_TOP_EE4B3_3", - "CMT_TOP_ICLK_5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_PHASERA_CTSBUS0", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW2END2_4", - "CMT_TOP_NW4END1_7", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_IMUX9_2", - "CMT_TOP_NW4A0_1", - "CMT_TOP_WW4END0_0", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_WW4B3_6", - "CMT_PHASER_IN_B_WREN_TOFIFO", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_LH1_0", - "CMT_TOP_IMUX18_5", - "CMT_TOP_SE2A1_7", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_TOP_SW2A1_1", - "CMT_TOP_OCLK1X_90_7", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_TOP_LH10_5", - "CMT_TOP_EE4A3_4", - "CMT_TOP_IMUX20_5", - "CMT_TOP_NW2A2_3", - "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "CMT_TOP_IMUX15_0", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_TOP_EE4A1_5", - "CMT_TOP_SE2A3_1", - "CMT_TOP_BYP0_4", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_TOP_IMUX24_8", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LH3_5", - "CMT_PHASER_B_OCLKDIV_TOIOI", - "CMT_TOP_IMUX26_2", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_TOP_IMUX19_8", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_IMUX42_1", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_SE2A1_3", - "CMT_TOP_IMUX8_5", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_TOP_CLK1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_WW4A2_0", - "CMT_TOP_IMUX23_4", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_TOP_WW4A2_3", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX17_3", - "MMCM_CLK_FREQBB_REBUFOUT1", - "CMT_PHASER_B_TOMMCM_ICLKDIV", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_EE4A1_4", - "CMT_TOP_IMUX16_4", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_LH1_8", - "CMT_TOP_IMUX46_5", - "CMT_TOP_NE2A0_1", - "CMT_TOP_LH11_1", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_WR1END2_8", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_IMUX3_5", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_EE2BEG1_0", - "CMT_PHASER_IN_DB_RCLK", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX26_7", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_FAN4_1", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_SE4C1_6", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2A3_6", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_IMUX24_3", - "CMT_TOP_BYP0_2", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_NW4END0_1", - "CMT_LR_LOWER_T_CLK_MMCM3", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_FAN3_6", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SE4BEG3_0", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_TOP_WW4A2_7", - "CMT_TOP_NW4A2_1", - "CMT_TOP_SW4A3_2", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW4C3_8", - "CMT_TOP_NE2A0_8", - "CMT_TOP_FAN4_4", - "CMT_TOP_WW4C3_0", - "CMT_TOP_NE2A2_3", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_SW2A2_4", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_PHASER_OUT_A_OCLKDIV", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_TOP_NE4C0_8", - "CMT_TOP_FAN3_0", - "CMT_TOP_IMUX6_3", - "CMT_TOP_NE4C0_3", - "CMT_TOP_IMUX35_3", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_TOP_NE4C2_4", - "CMT_TOP_SW2A0_7", - "CMT_PHASER_BOT_ENCALIB0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_NE4C0_1", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_WL1END3_4", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_TOP_SE4C2_1", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_CTRL0_1", - "CMT_TOP_NW4END3_5", - "CMT_TOP_IMUX2_4", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_WW2A2_7", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_FAN2_5", - "CMT_TOP_WR1END0_5", - "CMT_TOP_IMUX17_2", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_TOP_WL1END3_0", - "CMT_PHASER_IN_DB_ICLK", - "CMT_TOP_SW4A1_4", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX36_1", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE4A3_2", - "CMT_TOP_IMUX27_6", - "CMT_TOP_LH3_6", - "CMT_TOP_WW2END2_0", - "CMT_TOP_IMUX11_7", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_TOP_IMUX43_2", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_TOP_IMUX17_5", - "CMT_TOP_ER1BEG0_3", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C1_6", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_TOP_BYP1_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_NE4BEG1_0", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_CA_TESTIN4", - "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_IMUX7_0", - "CMT_TOP_NE4C1_8", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_WW2A0_8", - "CMT_TOP_SE4C2_8", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_IMUX26_4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_TOP_IMUX38_8", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_LH1_3", - "CMT_TOP_BYP1_2", - "CMT_TOP_IMUX26_5", - "CMT_TOP_BYP4_3", - "CMT_TOP_FAN5_2", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_IMUX29_3", - "CMT_PHASER_IN_A_WRCLK_TOFIFO", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_TOP_EE4C1_7", - "CMT_LR_LOWER_T_CLK_MMCM9", - "CMT_TOP_IMUX29_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4C0_1", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_IMUX38_6", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_TOP_WW4B3_4", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_TOP_NW2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_EE4B0_3", - "MMCM_CLK_FREQBB_REBUFOUT3", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_TOP_WW4B2_8", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_TOP_NW4A2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_TOP_WW4C2_6", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_IMUX36_7", - "CMT_TOP_NE2A3_7", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_NW4END0_8", - "CMT_TOP_FAN5_1", - "CMT_TOP_IMUX39_8", - "CMT_TOP_WW4B0_5", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_IMUX32_6", - "CMT_TOP_NE4BEG1_5", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_BYP4_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_LH3_7", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_NE4BEG3_2", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_TOP_WR1END1_7", - "CMT_TOP_NW2A0_5", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_TOP_BYP3_1", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_MONITOR_N_0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_TOP_SW2A0_5", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_LH9_2", - "CMT_TOP_WW2A2_4", - "CMT_TOP_IMUX40_6", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_WL1END3_3", - "CMT_TOP_NW4A3_0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_TOP_LH9_8", - "CMT_TOP_FAN0_2", - "CMT_TOP_IMUX7_5", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_TOP_IMUX19_1", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_IMUX41_0", - "CMT_TOP_WW4A0_5", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_FAN3_2", - "CMT_TOP_IMUX12_7", - "CMT_TOP_WW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW2A3_6", - "CMT_PHASERREF_DOWN_PHASEROUT_A", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_TOP_WW2A1_7", - "CMT_TOP_EE4B3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_IMUX4_7", - "CMT_TOP_EE4A0_4", - "CMT_TOP_IMUX1_7", - "CMT_TOP_WW4A0_6", - "CMT_TOP_EE4B0_0", - "CMT_TOP_NW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_EE4C2_0", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_SE4C0_0", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_TOP_NW2A3_3", - "CMT_TOP_SE4C0_8", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4END2_3", - "CMT_TOP_LH1_2", - "CMT_TOP_SW4END0_8", - "CMT_TOP_FAN3_5", - "CMT_TOP_LH1_5", - "CMT_PHASER_BOT_SYNC_BB", - "CMT_TOP_SE2A1_6", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_LR_LOWER_T_CLK_MMCM1", - "CMT_TOP_SW4END2_1", - "CMT_TOP_EE4B3_4", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_TOP_SW4END1_3", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_IMUX25_6", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_LH9_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_LH11_5", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_WR1END0_2", - "CMT_TOP_IMUX30_5", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX37_3", - "CMT_TOP_MONITOR_P_5", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW2END2_8", - "CMT_TOP_EE4C2_6", - "CMT_TOP_IMUX38_7", - "CMT_TOP_NW2A1_3", - "CMT_TOP_IMUX36_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_EE4A2_5", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_TOP_WW4A3_3", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_TOP_LH2_8", - "CMT_TOP_IMUX17_8", - "CMT_TOP_NE2A2_0", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_TOP_WW4C1_2", - "CMT_TOP_IMUX29_8", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_ER1BEG3_6", - "CMT_PHASER_BOT_REFMUX_1", - "CMT_TOP_CLK0_7", - "CMT_TOP_EE2A1_3", - "CMT_TOP_SW4END1_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_FAN7_1", - "CMT_TOP_LH11_3", - "CMT_TOP_IMUX13_3", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_WW4A3_2", - "CMT_TOP_NE4C0_6", - "CMT_TOP_BYP0_3", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_TOP_EE4A0_2", - "CMT_TOP_SE4C2_2", - "CMT_TOP_NW4A1_3", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX3_7", - "CMT_TOP_LH10_4", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_IMUX8_4", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_TOP_LH3_1", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW2A1_6", - "CMT_PHASER_OUT_A_OCLK", - "CMT_TOP_IMUX26_3", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_NW2A2_0", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "MMCM_CLK_FREQBB_REBUFOUT2", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_IMUX25_3", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_TOP_IMUX11_8", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_EE2BEG1_5", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_TOP_IMUX8_2", - "CMT_PHASER_DOWN_PHASERREF1", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_WW2END1_6", - "CMT_PHASER_OUT_B_OCLKDIV", - "CMT_TOP_WW2A3_3", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_TOP_EE4A2_3", - "CMT_TOP_WR1END2_2", - "CMT_TOP_SW4A1_1", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_8", - "CMT_TOP_WW4A1_6", - "CMT_TOP_IMUX41_2", - "CMT_TOP_LH8_6", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW2A1_5", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_CTRL1_1", - "CMT_TOP_SE4C1_8", - "CMT_TOP_WR1END1_3", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_WW4A2_6", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP0_6", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_IMUX43_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX31_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WL1END1_7", - "CMT_TOP_LH2_7", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_TOP_WW4END1_2", - "CMT_TOP_LH7_7", - "CMT_TOP_WR1END3_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_IMUX26_8", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_NW4A0_4", - "CMT_TOP_IMUX24_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_WR1END2_5", - "CMT_TOP_NW4END1_4", - "CMT_TOP_WW4C1_8", - "CMT_TOP_NW2A0_7", - "CMT_TOP_IMUX22_1", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_TOP_IMUX17_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_NW2A1_6", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX4_1", - "CMT_TOP_BYP2_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_NW4END2_3", - "CMT_TOP_EE2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_TOP_EE4C1_8", - "CMT_TOP_CLK1_4", - "CMT_TOP_LH2_2", - "CMT_TOP_NE4BEG2_7", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_TOP_NE4C2_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_EE4A2_7", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE4C2_4", - "CMT_PHASER_IN_CA_RST", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_IMUX11_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_NW4A1_4", - "CMT_PHASER_B_OCLK_TOIOI", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_SW2A0_3", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX38_3", - "CMT_TOP_EE4C2_2", - "CMT_TOP_WW4END0_4", - "CMT_TOP_IMUX5_6", - "CMT_TOP_NW4END2_2", - "CMT_TOP_BYP0_7", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_NE2A2_4", - "CMT_TOP_LH9_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4B0_6", - "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_NW4A1_5", - "CMT_TOP_IMUX28_5", - "CMT_TOP_SE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_SW2A2_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_IMUX9_7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_PHASER_OUT_A_RDCLK_TOFIFO", - "CMT_TOP_IMUX9_1", - "CMT_TOP_WW2A2_2", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_TOP_BYP7_8", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX4_4", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_IMUX30_1", - "CMT_TOP_WW4C0_5", - "CMT_TOP_NW4A1_2", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_WW2END0_2", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX45_5", - "CMT_TOP_FAN0_0", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_IMUX25_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX18_8", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_IMUX35_5", - "CMT_TOP_EE2A0_7", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_TOP_WW4B2_4", - "CMT_TOP_IMUX20_4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_TOP_EE4C3_6", - "CMT_TOP_FAN2_8", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_TOP_SE4BEG0_8", - "CMT_PHASER_B_TOMMCM_OCLK", - "CMT_TOP_SW2A1_0", - "CMT_TOP_WL1END0_5", - "CMT_LR_LOWER_T_CLK_PERF0", - "CMT_TOP_NE4C0_2", - "CMT_TOP_EE4B1_2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_TOP_IMUX10_3", - "CMT_TOP_SE4C1_1", - "CMT_TOP_IMUX29_4", - "CMT_TOP_FAN2_3", - "CMT_TOP_NE4C2_1", - "CMT_TOP_IMUX30_2", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2A2_2", - "CMT_TOP_IMUX31_5", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WW4A2_8", - "CMT_TOP_IMUX8_7", - "CMT_TOP_CTRL1_7", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_IMUX23_8", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_TOP_SW4END0_6", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_IMUX12_2", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_BYP6_6", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_TOP_WL1END2_7", - "CMT_TOP_EE4C1_4", - "CMT_TOP_BYP5_1", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_TOP_IMUX46_6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_TOP_NW4END0_7", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_BYP3_8", - "CMT_TOP_IMUX33_0", - "CMT_TOP_IMUX16_8", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_SW4END3_7", - "CMT_TOP_WW2A1_4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_TOP_OCLK_7", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_IMUX19_7", - "CMT_TOP_WW2END3_0", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_SE2A0_5", - "CMT_TOP_WW2A1_0", - "CMT_TOP_NW4A2_5", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_SE4C0_6", - "CMT_TOP_NE4BEG1_3", - "CMT_LR_LOWER_T_CLK_MMCM8", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_TOP_IMUX3_0", - "CMT_TOP_WL1END1_8", - "CMT_TOP_NW4END1_5", - "CMT_TOP_WW4END2_1", - "CMT_TOP_NW2A2_5", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_TOP_BYP5_6", - "CMT_TOP_LH6_2", - "CMT_TOP_IMUX39_6", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_PHASER_OUT_DB_RST", - "CMT_TOP_SE2A0_4", - "CMT_TOP_IMUX36_2", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_IMUX6_5", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_WW2A0_5", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_EE4A2_8", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX7_6", - "CMT_TOP_BYP2_0", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_TOP_IMUX8_3", - "CMT_TOP_ICLK_6", - "CMT_TOP_LH2_0", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_TOP_IMUX16_3", - "CMT_TOP_WW4B3_2", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_IMUX40_2", - "CMT_TOP_EE4C0_4", - "CMT_TOP_BYP2_1", - "CMT_TOP_IMUX36_8", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_NW2A3_5", - "CMT_TOP_IMUX27_3", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_TOP_WW4END3_1", - "CMT_TOP_SW4A2_4", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_WW4C2_2", - "CMT_TOP_IMUX46_2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_TOP_BYP1_6", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NW4A3_2", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_EE4A1_0", - "CMT_PHASER_BOT_OBURSTPENDING1", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX19_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_IMUX8_8", - "CMT_TOP_NW2A3_7", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_NW4A3_8", - "CMT_TOP_SW4END2_8", - "CMT_TOP_EL1BEG0_6", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_TOP_IMUX37_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_SE2A2_1", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_TOP_WW2END0_7", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_EE4C0_7", - "CMT_TOP_WL1END0_0", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_FAN7_2", - "CMT_TOP_WL1END3_1", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_WR1END3_5", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_TOP_LH8_4", - "CMT_TOP_LH5_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_IMUX13_0", - "CMT_TOP_SW4A0_6", - "CMT_TOP_WW2A3_2", - "CMT_TOP_BYP5_0", - "CMT_TOP_NE4C2_8", - "CMT_TOP_IMUX40_3", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_BYP7_4", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_TOP_LH10_6", - "CMT_TOP_SE4C2_4", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_PHASER_DOWN_PHASERREF0", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX46_4", - "CMT_TOP_LH4_2", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_TESTOUT1", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "CMT_TOP_EE4A3_8", - "CMT_TOP_IMUX44_3", - "CMT_TOP_NE4C3_5", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX14_5", - "CMT_TOP_BYP3_5", - "CMT_TOP_IMUX32_8", - "CMT_PHASER_IN_DB_STG1REGR1", - "CMT_TOP_IMUX34_5", - "CMT_TOP_EE4C1_0", - "CMT_PHASER_IN_B_WRCLK_TOFIFO", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_IMUX29_1", - "CMT_PHASER_BOT_IRANKB0", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SE4C3_5", - "CMT_TOP_BYP7_1", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_TOP_WL1END3_8", - "CMT_TOP_IMUX45_7", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX17_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_OCLK_0", - "CMT_PHASER_IN_A_ICLK", - "CMT_TOP_IMUX31_7", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_TOP_FAN6_4", - "CMT_PHASER_IN_A_WREN_TOFIFO", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_TOP_IMUX2_2", - "CMT_TOP_WW4END3_5", - "CMT_TOP_IMUX21_7", - "CMT_TOP_LH1_1", - "CMT_TOP_FAN5_8", - "CMT_TOP_NW4END3_8", - "CMT_TOP_WW2END0_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LH5_2", - "CMT_TOP_WW4A1_1", - "CMT_TOP_IMUX17_4", - "CMT_TOP_SW2A1_8", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_TOP_NE4BEG3_1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_TOP_EE2A3_2", - "CMT_TOP_LH3_8", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_TOP_WW2END0_4", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_EE2A1_7", - "CMT_TOP_WW2END2_3", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END2_6", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_PHASER_B_TOMMCM_ICLK", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE4B2_1", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_TOP_NW4END3_1", - "CMT_TOP_MONITOR_N_4", - "CMT_LR_LOWER_T_CLK_MMCM12", - "CMT_TOP_LH3_0", - "CMT_TOP_LH2_5", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_NW4A2_3", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2A0_2", - "CMT_TOP_IMUX5_4", - "CMT_TOP_SW4END2_6", - "CMT_TOP_IMUX47_1", - "CMT_TOP_WW2A2_1", - "CMT_TOP_NW2A1_7", - "CMT_TOP_SW4END3_0", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX34_8", - "CMT_TOP_LH7_4", - "CMT_TOP_EE4C0_2", - "CMT_TOP_IMUX39_3", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_TOP_IMUX45_3", - "CMT_TOP_NW2A3_1", - "CMT_TOP_IMUX31_6", - "CMT_TOP_WW4C1_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_WW4B3_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_NE2A2_2", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX33_7", - "CMT_TOP_FAN5_3", - "CMT_TOP_NW4A2_0", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_BYP7_0", - "CMT_TOP_LH6_0", - "CMT_TOP_NE4C1_4", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_TOP_LH5_4", - "CMT_TOP_CLK0_4", - "CMT_TOP_IMUX22_8", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_WW4A3_4", - "CMT_TOP_IMUX5_2", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "CMT_TOP_NW4A1_6", - "CMT_TOP_FAN1_2", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_SW4A3_4", - "CMT_TOP_WW4B2_6", - "CMT_TOP_CLK0_0", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_LH8_7", - "CMT_TOP_IMUX32_5", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_SW2A1_5", - "CMT_TOP_IMUX32_7", - "CMT_PHASER_B_ICLKDIV_TOIOI", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_WR1END0_1", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_BYP2_3" - ], - "sites": [ - { - "prefix": "PHASER_OUT_PHY", - "y_coord": 0, - "type": "PHASER_OUT_PHY", - "site_pins": { - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "RST": "CMT_PHASER_OUT_CA_RST", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "PHASER_IN_PHY", - "y_coord": 0, - "type": "PHASER_IN_PHY", - "site_pins": { - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", - "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", - "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", - "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", - "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", - "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", - "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", - "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "ICLK": "CMT_PHASER_IN_CA_ICLK", - "RCLK": "CMT_PHASER_IN_CA_RCLK", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", - "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", - "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", - "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", - "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", - "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", - "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", - "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", - "SCANIN": "CMT_PHASER_IN_CA_SCANIN", - "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", - "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", - "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", - "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", - "STG1READ": "CMT_PHASER_IN_CA_STG1READ", - "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", - "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", - "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", - "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", - "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", - "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", - "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", - "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", - "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", - "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", - "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", - "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", - "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", - "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", - "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", - "SCANENB": "CMT_PHASER_IN_CA_SCANENB", - "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", - "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", - "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", - "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", - "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", - "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", - "RST": "CMT_PHASER_IN_CA_RST", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", - "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", - "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", - "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", - "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", - "FINEINC": "CMT_PHASER_IN_CA_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", - "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", - "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", - "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", - "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", - "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", - "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", - "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", - "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", - "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", - "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "PHASER_OUT_PHY", - "y_coord": 1, - "type": "PHASER_OUT_PHY", - "site_pins": { - "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", - "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", - "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", - "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", - "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", - "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", - "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", - "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", - "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", - "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", - "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", - "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", - "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", - "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", - "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", - "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", - "OCLK": "CMT_PHASER_OUT_DB_OCLK", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", - "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", - "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", - "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", - "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", - "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", - "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", - "RST": "CMT_PHASER_OUT_DB_RST", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", - "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", - "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", - "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", - "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", - "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", - "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", - "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", - "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", - "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", - "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", - "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", - "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", - "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "PHASER_IN_PHY", - "y_coord": 1, - "type": "PHASER_IN_PHY", - "site_pins": { - "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", - "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", - "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", - "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", - "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", - "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", - "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", - "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", - "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "ICLK": "CMT_PHASER_IN_DB_ICLK", - "RCLK": "CMT_PHASER_IN_DB_RCLK", - "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", - "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", - "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", - "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", - "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", - "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", - "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", - "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", - "SCANIN": "CMT_PHASER_IN_DB_SCANIN", - "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", - "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", - "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", - "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", - "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", - "STG1READ": "CMT_PHASER_IN_DB_STG1READ", - "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", - "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", - "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", - "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", - "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", - "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", - "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", - "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", - "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", - "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", - "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", - "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", - "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", - "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", - "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", - "SCANENB": "CMT_PHASER_IN_DB_SCANENB", - "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", - "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", - "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", - "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", - "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", - "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", - "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", - "RST": "CMT_PHASER_IN_DB_RST", - "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", - "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", - "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", - "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", - "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", - "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", - "FINEINC": "CMT_PHASER_IN_DB_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", - "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", - "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", - "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", - "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", - "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", - "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", - "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", - "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", - "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", - "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", - "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_RCLK1", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_RCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING0->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IBURSTPENDING0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B16_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_DTSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX32_2->CMT_PHASER_OUT_CA_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX21_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT3->>MMCM_CLK_FREQBB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT3", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT2->>MMCM_CLK_FREQBB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT2", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { - "can_invert": "0", - "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_8", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_B->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_B", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX9_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX11_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING0->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_OBURSTPENDING0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_5->CMT_PHASER_OUT_DB_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_5->CMT_PHASER_OUT_DB_COARSEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_7->CMT_PHASER_IN_DB_RANKSEL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_DTSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_WRENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", - "is_pseudo": "1" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX12_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX28_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { - "can_invert": "0", - "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK1_8", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_B->CMT_PHASER_OUT_DB_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_CTSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_B_OCLK1X_90": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_6->CMT_PHASER_IN_DB_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_CTSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_A_ICLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_ICLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX25_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", - "is_pseudo": "1" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_A_RCLK0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_RCLK0", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_RCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_DQSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLKDIV->>CMT_PHASER_B_ICLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_B_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX41_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERA_DQSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT0->>MMCM_CLK_FREQBB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT0", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX46_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->CMT_PHASER_B_TOMMCM_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_TOMMCM_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_A->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_A", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO->CMT_PHASER_IN_A_ICLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_ICLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_OCLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_TOMMCM_OCLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK1X_90_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK90_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_2", - "is_pseudo": "0" - }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN", - "is_directional": "1", "src_wire": "CMT_PHASER_BOT_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKA0->CMT_PHASER_IN_CA_RANKSELPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IRANKA0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->CMT_PHASER_B_TOMMCM_ICLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_TOMMCM_ICLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX8_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX39_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX25_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_A->CMT_PHASER_OUT_CA_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_A->CMT_PHASER_IN_CA_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO->CMT_PHASER_IN_B_ICLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_ICLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", "src_wire": "CMT_PHASER_DOWN_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_A_WRCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLK->>CMT_PHASER_B_ICLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_B_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_6->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKB0->CMT_PHASER_IN_DB_RANKSELPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IRANKB0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING1->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_6": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IBURSTPENDING1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKA1->CMT_PHASER_IN_CA_RANKSELPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_IRANKA1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B1_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B18_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_ENCALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_B": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV->>CMT_PHASER_B_OCLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_B_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_B_ICLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_0", - "is_directional": "1", "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_2", "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_B": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_4", + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", "is_directional": "1", - "src_wire": "CMT_PHASER_B_ICLK_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0" }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_A_WREN_TOFIFO": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_A_WREN_TOFIFO", + "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_WRENABLE", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO" }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "src_wire": "CMT_PHASER_BOT_ENCALIB1", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_A_WRCLK_TOFIFO->CMT_PHASER_IN_A_ICLKDIV": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", + "src_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_ICLKDIV" }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { "can_invert": "0", - "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "src_wire": "CMT_PHASER_BOT_ENCALIB0", "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING1->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "src_wire": "CMT_PHASER_IN_DB_ICLK", "is_directional": "1", - "src_wire": "CMT_PHASER_BOT_OBURSTPENDING1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_ICLK" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "src_wire": "CMT_TOP_IMUX45_1", "is_directional": "1", - "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_2": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", + "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6" }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_RST", + "src_wire": "CMT_PHASER_BOT_REFMUX_1", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_1", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", "is_directional": "1", - "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90", + "src_wire": "CMT_TOP_IMUX0_5", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK->>CMT_PHASER_B_OCLK_TOIOI": { "can_invert": "0", - "dst_wire": "CMT_PHASER_B_OCLK_TOIOI", - "is_directional": "1", "src_wire": "CMT_PHASER_OUT_B_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RST", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX12_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLK_TOIOI" }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B6_3": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", + "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO" }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->CMT_PHASER_B_TOMMCM_ICLK": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_ICLK" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1", + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DQSBUS0" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_ICLKDIV": { + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", - "dst_wire": "CMT_PHASER_B_TOMMCM_ICLKDIV", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "can_invert": "0", "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_7->CMT_PHASER_IN_DB_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RST", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3" }, - "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV->>CMT_PHASER_B_OCLKDIV_TOIOI": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "src_wire": "CMT_PHASER_OUT_B_OCLKDIV", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_A_WREN_TOFIFO": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_3", + "src_wire": "CMT_PHASER_IN_CA_WRENABLE", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_WREN_TOFIFO" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX32_2->CMT_PHASER_OUT_CA_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEINC" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "can_invert": "0", "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4" }, - "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_2": { + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", + "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX46_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_A_RCLK0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_RCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_RCLK0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKB1->CMT_PHASER_IN_DB_RANKSELPHY1": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", - "is_directional": "1", "src_wire": "CMT_PHASER_BOT_IRANKB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1" }, - "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT1->>MMCM_CLK_FREQBB_REBUFOUT1": { + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { "can_invert": "0", - "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT1", + "src_wire": "CMT_TOP_IMUX14_6", "is_directional": "1", - "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4" }, - "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_B->CMT_PHASER_IN_DB_PHASEREFCLK": { + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "src_wire": "CMT_TOP_IMUX14_3", "is_directional": "1", - "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEINC" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_WRENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX41_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEINC" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_RST" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKA1->CMT_PHASER_IN_CA_RANKSELPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IRANKA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { "can_invert": "0", - "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", - "is_directional": "1", "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKB0->CMT_PHASER_IN_DB_RANKSELPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IRANKB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING0->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IBURSTPENDING0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLKDIV->>CMT_PHASER_B_ICLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_B_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_ICLKDIV_TOIOI" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_5->CMT_PHASER_OUT_DB_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_RST" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_B->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_5->CMT_PHASER_OUT_DB_COARSEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING0->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_OBURSTPENDING0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_OCLKDIV" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYSCLK" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_CTSBUS1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DQSBUS1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_EDGEADV" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B6_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_DB_RCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B18_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_4" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX25_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT1->>MMCM_CLK_FREQBB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->CMT_PHASER_B_TOMMCM_ICLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_ICLKDIV" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_A->CMT_PHASER_IN_CA_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_A", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_B->CMT_PHASER_OUT_DB_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_B->CMT_PHASER_IN_DB_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_B", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_RCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_RCLK1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_A->CMT_PHASER_OUT_CA_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKA0->CMT_PHASER_IN_CA_RANKSELPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IRANKA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING1->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_OBURSTPENDING1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_7->CMT_PHASER_IN_DB_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RST" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYSCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLK" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT2->>MMCM_CLK_FREQBB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->CMT_PHASER_B_TOMMCM_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_TOMMCM_OCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASEROUT_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYNCIN" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_A_ICLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_ICLK" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_6->CMT_PHASER_IN_DB_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEINC" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B1_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_3" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYNCIN" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX23_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING1->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_IBURSTPENDING1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DTSBUS1" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT3->>MMCM_CLK_FREQBB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX12_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RST" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX23_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_B_OCLK1X_90": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_A_WRCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_EDGEADV" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX23_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_7->CMT_PHASER_IN_DB_RANKSEL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_CTSBUS0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_6->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT0->>MMCM_CLK_FREQBB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT0" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX9_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_ICLK->>CMT_PHASER_B_ICLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_B_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_B_ICLK_TOIOI" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERA_DTSBUS0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_DQS_TO_PHASER_A->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_DQS_TO_PHASER_A", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW1->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_B_WRCLK_TOFIFO->CMT_PHASER_IN_B_ICLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_B_ICLKDIV" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_CA_RCLK" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B16_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_3" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_ABOVE1->>CMT_PHASERREF_DOWN_PHASERIN_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF0->>CMT_PHASERREF_DOWN_PHASERIN_A": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_DOWN_PHASERREF_BELOW0->>CMT_PHASERREF_DOWN_PHASEROUT_B": { + "can_invert": "0", + "src_wire": "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4" + }, + "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_BOT_ENCALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_B_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_B_OCLK90_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_4" + }, + "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2" } }, - "tile_type": "CMT_TOP_R_LOWER_T" + "wires": [ + "CMT_PHASER_IN_B_WREN_TOFIFO", + "CMT_PHASER_IN_DB_TESTIN3", + "CMT_LR_LOWER_T_CLK_IN1_HCLK", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_NW4A2_6", + "CMT_TOP_WW2END3_2", + "CMT_TOP_WW2END3_3", + "CMT_TOP_BYP1_3", + "CMT_PHASER_OUT_CA_DIVIDERST", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_PHASER_IN_CA_STG1REGL7", + "CMT_PHASER_OUT_DB_TESTIN14", + "MMCMOUT_CLK_FREQ_BB_REBUFIN3", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_NE4C0_2", + "CMT_TOP_FAN6_7", + "CMT_PHASER_IN_DB_STG1REGR4", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_LH7_5", + "CMT_TOP_IMUX19_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_FAN0_2", + "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "CMT_TOP_IMUX47_5", + "CMT_TOP_IMUX27_3", + "CMT_TOP_NW4A1_2", + "CMT_TOP_FAN6_0", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_IMUX24_0", + "CMT_TOP_IMUX26_0", + "CMT_PHASER_OUT_DB_PHASEREFCLK", + "CMT_TOP_WW2A1_6", + "CMT_TOP_WR1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_WW4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_PHASER_IN_CA_TESTIN3", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_PHASER_OUT_DB_TESTIN4", + "CMT_TOP_WW4END1_8", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_NE4C0_6", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WW4END2_8", + "CMT_TOP_EE4C0_0", + "CMT_PHASER_IN_B_ICLKDIV", + "CMT_TOP_IMUX7_3", + "CMT_TOP_WW4B3_6", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_BYP6_2", + "CMT_PHASER_IN_A_WREN_TOFIFO", + "CMT_TOP_SE4C1_8", + "CMT_PHASER_IN_DB_STG1REGR1", + "CMT_TOP_EE2A0_2", + "CMT_TOP_LH3_8", + "CMT_TOP_WW4B0_5", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_IMUX41_8", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WL1END3_5", + "CMT_PHASER_IN_DB_TESTOUT3", + "CMT_TOP_IMUX36_7", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_IMUX32_8", + "CMT_TOP_SE4C1_7", + "CMT_PHASER_IN_CA_TESTOUT2", + "CMT_TOP_IMUX45_7", + "CMT_TOP_WW2END3_5", + "CMT_TOP_SW4END0_1", + "CMT_TOP_EE2A3_4", + "CMT_TOP_IMUX12_8", + "CMT_TOP_NW4END3_1", + "CMT_TOP_IMUX13_0", + "CMT_PHASER_OUT_CA_FREQREFCLK", + "CMT_TOP_EE2BEG1_3", + "CMT_PHASER_OUT_CA_TESTIN3", + "CMT_TOP_IMUX29_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_NE2A3_0", + "CMT_PHASER_OUT_DB_ENCALIB0", + "CMT_TOP_SW4END3_1", + "CMT_TOP_CLK1_3", + "CMT_TOP_IMUX5_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "CMT_TOP_WR1END0_8", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_FAN2_8", + "CMT_PHASER_IN_CA_PHASEREFCLK", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4C0_8", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", + "CMT_PHASER_B_TOMMCM_ICLK", + "CMT_PHASER_IN_CA_TESTIN5", + "CMT_PHASER_IN_DB_PHASEREFCLK", + "CMT_TOP_IMUX15_4", + "CMT_TOP_EE4BEG0_0", + "CMT_PHASER_IN_DB_SCANIN", + "CMT_PHASER_IN_CA_STG1REGR4", + "CMT_PHASER_OUT_CA_DQSBUS0", + "CMT_TOP_SE4BEG3_5", + "CMT_PHASER_OUT_DB_MEMREFCLK", + "CMT_PHASER_DOWN_PHASERREF_ABOVE1", + "CMT_TOP_EE2A1_0", + "CMT_TOP_WW4A1_1", + "CMT_TOP_EE4B3_0", + "CMT_PHASER_IN_DB_TESTIN12", + "CMT_TOP_BYP4_1", + "CMT_TOP_EE4B0_1", + "CMT_TOP_SE4BEG3_4", + "CMT_PHASER_IN_DB_SCANENB", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_OCLK_7", + "CMT_TOP_WW4C0_3", + "CMT_TOP_SE4BEG2_5", + "CMT_PHASER_IN_CA_TESTIN2", + "CMT_TOP_EE4C2_1", + "CMT_PHASER_OUT_DB_SYNCIN", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_IMUX1_1", + "CMT_TOP_NW4A2_2", + "CMT_TOP_NE4C2_3", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_CLK0_3", + "CMT_TOP_IMUX14_1", + "CMT_TOP_IMUX35_6", + "CMT_TOP_EE4A0_6", + "CMT_TOP_FAN5_5", + "CMT_TOP_WW2END1_3", + "CMT_TOP_NE4BEG2_5", + "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "CMT_TOP_NE2A1_0", + "CMT_TOP_IMUX3_4", + "CMT_TOP_SE4BEG1_6", + "CMT_PHASER_DOWN_DQS_TO_PHASER_B", + "CMT_TOP_IMUX2_7", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX39_7", + "CMT_TOP_IMUX14_2", + "CMT_PHASER_IN_DB_TESTIN10", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW4C3_6", + "CMT_TOP_WW4C3_2", + "CMT_TOP_EE4C0_4", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_IMUX28_8", + "CMT_TOP_NW4END0_3", + "CMT_TOP_EE4B3_8", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW4END1_5", + "CMT_TOP_LH2_6", + "CMT_PHASER_B_OCLK90_TOIOI", + "CMT_PHASER_BOT_IRANKA0", + "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "CMT_PHASER_OUT_CA_BURSTPENDING", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_BYP4_8", + "CMT_TOP_EE4C1_6", + "CMT_PHASER_OUT_DB_FINEINC", + "CMT_TOP_EE2A0_1", + "CMT_TOP_EE4A2_7", + "CMT_TOP_NW2A0_4", + "CMT_TOP_WW4B0_6", + "CMT_TOP_WW4A0_4", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_LH12_7", + "CMT_TOP_WW2END1_7", + "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "CMT_TOP_LH6_2", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX1_3", + "CMT_TOP_IMUX45_8", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_EE2A0_3", + "CMT_LR_LOWER_T_CLK_MMCM1", + "CMT_TOP_IMUX33_4", + "CMT_TOP_BYP7_3", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "CMT_LR_LOWER_T_CLK_MMCM12", + "CMT_TOP_IMUX30_7", + "CMT_TOP_ICLK_4", + "CMT_PHASER_IN_CA_STG1REGR1", + "CMT_TOP_SW2A0_5", + "CMT_TOP_EE4C3_8", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_IMUX35_2", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_PHASER_OUT_DB_CTSBUS1", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_FAN7_7", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_WW2END1_0", + "CMT_TOP_NW4END1_7", + "CMT_TOP_IMUX30_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_WW2A0_5", + "CMT_TOP_WW4C1_0", + "CMT_TOP_CLK1_8", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_IMUX14_3", + "CMT_TOP_SW4END3_2", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "CMT_TOP_WL1END0_5", + "CMT_TOP_SW4END1_5", + "CMT_TOP_NE2A0_2", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_PHASER_OUT_DB_BURSTPENDING", + "CMT_TOP_FAN3_8", + "CMT_TOP_IMUX27_7", + "CMT_TOP_NE4C0_1", + "CMT_TOP_WW4END1_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LH8_6", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "CMT_TOP_SW2A1_5", + "CMT_TOP_EE4A0_1", + "CMT_TOP_IMUX33_6", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_WL1END2_3", + "CMT_TOP_EE4B3_3", + "CMT_TOP_WW4A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_WW2END2_1", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4END1_6", + "CMT_TOP_IMUX25_4", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_SW4END1_0", + "CMT_PHASER_OUT_CA_CTSBUS0", + "CMT_TOP_EE2A1_1", + "CMT_TOP_WL1END2_4", + "CMT_TOP_SE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_IMUX11_4", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_IMUX3_3", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_WR1END0_2", + "CMT_TOP_BYP7_4", + "CMT_R_TOP_LOWER_B_CLKINT_1", + "CMT_TOP_EE4A3_6", + "CMT_TOP_NE2A2_7", + "CMT_PHASER_IN_DB_RSTDQSFIND", + "CMT_TOP_WR1END0_4", + "CMT_PHASER_IN_CA_TESTIN6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_SW4A2_0", + "CMT_PHASER_OUT_DB_TESTOUT0", + "CMT_PHASER_OUT_CA_FINEINC", + "CMT_TOP_BYP1_1", + "CMT_TOP_LH11_6", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WR1END0_3", + "CMT_PHASER_IN_DB_TESTOUT0", + "CMT_TOP_WW4B3_5", + "CMT_TOP_EL1BEG1_6", + "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "CMT_PHASER_OUT_CA_ENCALIB0", + "CMT_TOP_EE2A0_5", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH4_7", + "CMT_TOP_BYP6_0", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WR1END1_6", + "CMT_TOP_ER1BEG1_2", + "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "CMT_TOP_SE4C0_2", + "CMT_TOP_EE4A1_2", + "CMT_PHASER_OUT_B_OCLKDIV", + "CMT_PHASER_OUT_CA_TESTOUT3", + "CMT_TOP_EE4A2_8", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_SE2A1_1", + "CMT_TOP_IMUX14_4", + "CMT_TOP_NW4END1_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_IMUX31_3", + "CMT_TOP_EE4C1_8", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_WW4END1_4", + "CMT_TOP_CTRL0_5", + "CMT_PHASER_IN_DB_STG1REGL3", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_EE4A0_3", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_SW4A1_5", + "CMT_TOP_SE4C0_0", + "CMT_TOP_IMUX43_3", + "CMT_TOP_FAN1_5", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_NW2A0_7", + "CMT_TOP_EE4B2_1", + "CMT_TOP_IMUX31_7", + "CMT_TOP_SW2A1_0", + "CMT_TOP_WW4B2_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_SE4BEG1_7", + "CMT_PHASER_IN_CA_ISERDESRST", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_IMUX47_0", + "CMT_TOP_EE2A0_0", + "CMT_PHASER_IN_DB_DIVIDERST", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "CMT_TOP_CTRL1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX21_0", + "CMT_TOP_IMUX10_2", + "CMT_TOP_WW4A1_2", + "CMT_TOP_SW4A0_8", + "CMT_TOP_WW4C3_4", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_CLK0_0", + "CMT_TOP_LH9_7", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END3_7", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_IMUX38_2", + "CMT_TOP_EE4A3_0", + "CMT_TOP_WW2A3_6", + "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "CMT_TOP_NW2A3_1", + "CMT_TOP_BYP3_5", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_NW2A1_2", + "CMT_TOP_SW2A3_4", + "CMT_TOP_SW4END1_1", + "CMT_TOP_ER1BEG1_6", + "CMT_PHASER_OUT_CA_FINEENABLE", + "CMT_TOP_NW4A1_1", + "CMT_TOP_IMUX42_8", + "CMT_TOP_WW2A2_4", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "CMT_TOP_IMUX30_2", + "CMT_TOP_IMUX45_1", + "CMT_TOP_WW4B3_0", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_EE4A3_4", + "CMT_TOP_SE4C2_5", + "CMT_TOP_WW4END2_7", + "CMT_TOP_LH9_5", + "CMT_TOP_LH3_6", + "CMT_TOP_NE2A0_3", + "CMT_TOP_IMUX12_0", + "CMT_TOP_EE2A2_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_IMUX11_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "CMT_TOP_IMUX24_3", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_IMUX9_8", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", + "CMT_TOP_IMUX24_2", + "CMT_TOP_IMUX26_4", + "CMT_LR_LOWER_T_CLK_MMCM7", + "CMT_TOP_LH3_0", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_WW2A1_1", + "CMT_PHASER_IN_DB_STG1REGR6", + "CMT_TOP_IMUX38_1", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_LH2_0", + "CMT_TOP_NW4A1_0", + "CMT_PHASER_IN_CA_STG1REGL8", + "CMT_TOP_IMUX22_2", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX2_8", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_BYP1_8", + "CMT_TOP_IMUX31_1", + "CMT_PHASER_OUT_DB_SCANIN", + "CMT_PHASER_IN_CA_TESTIN7", + "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "CMT_TOP_SW4A3_2", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_IMUX36_8", + "CMT_TOP_SW4END1_2", + "CMT_PHASER_IN_DB_SELCALORSTG1", + "CMT_TOP_SW4A1_0", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_PHASER_DOWN_PHASERREF_BELOW0", + "CMT_PHASERA_DQSBUS0", + "CMT_TOP_EE4C0_5", + "CMT_TOP_WL1END1_4", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_LH7_0", + "CMT_TOP_IMUX33_7", + "CMT_TOP_WW2A1_4", + "CMT_TOP_SE4C1_2", + "CMT_TOP_ER1BEG1_0", + "CMT_LR_LOWER_T_CLK_PERF0", + "CMT_TOP_LH2_7", + "CMT_TOP_NE4C2_1", + "CMT_TOP_SW4A2_7", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_WR1END1_5", + "CMT_TOP_IMUX36_1", + "CMT_TOP_SW4END2_0", + "CMT_TOP_LH8_0", + "CMT_TOP_EE4A0_7", + "CMT_TOP_EE4C0_3", + "CMT_TOP_EE4A0_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_EE4B1_5", + "CMT_PHASER_IN_DB_STG1REGL6", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_IMUX8_6", + "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "CMT_TOP_BYP0_7", + "CMT_TOP_LH5_0", + "CMT_TOP_IMUX5_2", + "CMT_TOP_WL1END2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_IMUX19_1", + "CMT_TOP_IMUX9_3", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_BYP1_7", + "CMT_PHASER_OUT_CA_TESTIN7", + "CMT_PHASER_BOT_REFMUX_1", + "CMT_TOP_IMUX47_1", + "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "CMT_TOP_IMUX17_3", + "CMT_PHASER_BOT_ENCALIB1", + "CMT_PHASER_BOT_IRANKB0", + "CMT_TOP_WW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2BEG3_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CMT_PHASER_IN_DB_BURSTPENDING", + "CMT_TOP_NE4C3_4", + "CMT_TOP_EE4B2_7", + "CMT_TOP_OCLK_5", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_NE2A1_6", + "CMT_TOP_IMUX36_0", + "CMT_TOP_WW2A2_7", + "CMT_TOP_IMUX33_8", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", + "CMT_TOP_IMUX45_4", + "CMT_TOP_IMUX8_2", + "CMT_TOP_IMUX1_2", + "CMT_TOP_SW4END2_8", + "CMT_TOP_NE4C3_7", + "CMT_TOP_IMUX46_0", + "CMT_TOP_WW4C2_7", + "CMT_PHASER_IN_DB_SCANOUT", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_LH1_7", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_BYP5_3", + "CMT_PHASER_IN_CA_TESTIN13", + "CMT_TOP_NW2A2_2", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX40_4", + "CMT_LR_LOWER_T_CLK_MMCM13", + "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_WW4END0_5", + "CMT_TOP_BYP7_0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_BYP3_2", + "CMT_PHASER_IN_CA_FINEOVERFLOW", + "CMT_TOP_NW4END2_1", + "CMT_PHASER_IN_CA_STG1REGR0", + "CMT_TOP_WW4C1_7", + "CMT_TOP_IMUX45_3", + "CMT_TOP_IMUX15_0", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4A3_6", + "CMT_TOP_NE4BEG3_8", + "CMT_PHASER_OUT_CA_TESTIN10", + "CMT_TOP_SE4C0_6", + "CMT_TOP_MONITOR_P_1", + "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH10_4", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_IMUX32_3", + "CMT_PHASER_OUT_A_OCLKDIV", + "CMT_TOP_WR1END2_5", + "CMT_TOP_SE4C2_7", + "CMT_TOP_EE4A0_4", + "CMT_TOP_SW4A0_3", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX11_6", + "CMT_TOP_IMUX25_7", + "CMT_PHASERA_DTSBUS0", + "CMT_TOP_IMUX4_8", + "CMT_TOP_BYP5_1", + "CMT_PHASER_OUT_B_RDEN_TOFIFO", + "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "CMT_TOP_WW2A1_7", + "CMT_PHASER_IN_DB_COUNTERLOADEN", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_IMUX17_5", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_BYP2_2", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_IMUX16_8", + "CMT_TOP_LH1_6", + "CMT_TOP_NW4END0_5", + "CMT_TOP_SE2A3_6", + "CMT_TOP_IMUX7_4", + "MMCM_CLK_FREQBB_REBUFOUT3", + "CMT_TOP_IMUX12_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_IMUX30_3", + "CMT_TOP_BYP5_6", + "CMT_TOP_WW4C2_5", + "CMT_TOP_LH7_6", + "CMT_TOP_SE2A1_5", + "CMT_TOP_FAN4_7", + "CMT_TOP_SE2A3_3", + "CMT_PHASER_BOT_IBURSTPENDING1", + "CMT_TOP_EE4A2_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_LR_LOWER_T_CLK_MMCM6", + "CMT_TOP_LH9_2", + "CMT_TOP_EE4C0_1", + "CMT_TOP_BYP0_1", + "CMT_TOP_NE4C2_0", + "CMT_TOP_LH11_0", + "CMT_PHASER_OUT_DB_TESTIN7", + "CMT_TOP_IMUX1_7", + "CMT_TOP_IMUX14_0", + "CMT_TOP_NW2A1_5", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX21_5", + "CMT_TOP_IMUX21_7", + "CMT_TOP_WW4A0_2", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH12_3", + "CMT_TOP_IMUX7_6", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX23_7", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4C1_2", + "CMT_TOP_LH4_3", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH5_6", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW4C1_4", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_SW4END3_7", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LH12_8", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_FAN4_6", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NW4A3_5", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_CTRL0_8", + "CMT_PHASER_OUT_CA_TESTIN4", + "CMT_TOP_NW4A3_7", + "CMT_PHASER_OUT_CA_SYSCLK", + "CMT_TOP_NW4END3_0", + "CMT_TOP_IMUX33_2", + "CMT_TOP_BYP2_1", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_NE2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_SE2A3_8", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_IMUX20_8", + "CMT_TOP_WW2END0_8", + "CMT_TOP_WW2END1_2", + "CMT_TOP_LH9_3", + "CMT_PHASER_OUT_CA_TESTIN12", + "MMCMOUT_CLK_FREQ_BB_REBUFIN2", + "CMT_TOP_ER1BEG3_3", + "CMT_PHASER_OUT_DB_COARSEINC", + "CMT_TOP_LH6_4", + "CMT_TOP_EE4B2_2", + "CMT_PHASER_OUT_DB_TESTIN0", + "CMT_TOP_SE4BEG0_2", + "CMT_PHASER_OUT_CA_OSERDESRST", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_NW2A2_7", + "CMT_TOP_IMUX5_8", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_PHASER_IN_CA_STG1REGR3", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_IMUX33_5", + "CMT_PHASER_OUT_CA_COARSEINC", + "CMT_PHASER_IN_CA_ENCALIB1", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE2A0_7", + "CMT_TOP_NE4C3_0", + "CMT_PHASER_IN_CA_COUNTERLOADEN", + "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "CMT_TOP_BYP6_5", + "CMT_TOP_SW4END3_0", + "CMT_TOP_WL1END0_6", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_WR1END1_2", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_NW4A1_5", + "CMT_PHASER_OUT_DB_RDENABLE", + "CMT_PHASER_IN_CA_SYSCLK", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_PHASER_OUT_DB_COUNTERREADEN", + "CMT_TOP_IMUX47_8", + "CMT_TOP_IMUX15_6", + "CMT_TOP_WW4C1_3", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_IMUX41_2", + "CMT_TOP_SE4C1_5", + "CMT_TOP_ICLK_2", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_WL1END2_7", + "CMT_TOP_IMUX36_2", + "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "CMT_TOP_FAN1_3", + "CMT_TOP_WW4A0_1", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_LH9_0", + "CMT_TOP_CTRL0_4", + "CMT_TOP_NW4END2_3", + "CMT_TOP_SE2A2_8", + "CMT_TOP_WL1END0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_WR1END3_6", + "CMT_PHASER_IN_CA_STG1LOAD", + "CMT_PHASER_OUT_DB_SCANOUT", + "CMT_TOP_WW4C2_3", + "CMT_TOP_WW2A3_3", + "CMT_TOP_WL1END3_4", + "CMT_TOP_NE2A2_8", + "CMT_TOP_NE2A3_3", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_SW2A0_8", + "CMT_TOP_WW4B3_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_IMUX29_8", + "CMT_PHASER_IN_CA_TESTIN10", + "CMT_PHASER_IN_DB_STG1REGR8", + "CMT_TOP_IMUX26_6", + "CMT_TOP_SE4C0_7", + "CMT_PHASER_OUT_DB_TESTIN2", + "CMT_TOP_IMUX4_0", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_NE4BEG0_7", + "CMT_PHASER_OUT_DB_OCLKDIV", + "CMT_TOP_IMUX40_2", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_EE2BEG3_8", + "CMT_PHASERA_DTSBUS1", + "CMT_PHASER_OUT_DB_DQSBUS0", + "CMT_TOP_IMUX29_0", + "CMT_TOP_WR1END2_0", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX1_6", + "CMT_PHASER_OUT_CA_RDENABLE", + "CMT_PHASER_IN_DB_ICLK", + "CMT_TOP_SW2A3_6", + "CMT_TOP_IMUX14_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_IMUX7_7", + "CMT_TOP_BYP3_3", + "CMT_TOP_IMUX29_5", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WW2A2_3", + "CMT_TOP_IMUX44_0", + "CMT_TOP_WW4A2_4", + "CMT_TOP_WW4C1_1", + "CMT_TOP_WW4B1_7", + "CMT_TOP_EE2A1_6", + "CMT_PHASER_IN_DB_MEMREFCLK", + "CMT_TOP_EE4A1_7", + "CMT_TOP_IMUX19_2", + "CMT_PHASER_OUT_DB_EDGEADV", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW2A1_3", + "CMT_PHASER_OUT_DB_TESTOUT3", + "CMT_TOP_IMUX39_5", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_FAN3_4", + "CMT_TOP_FAN3_2", + "CMT_TOP_LH1_0", + "CMT_TOP_IMUX28_5", + "CMT_TOP_IMUX6_7", + "CMT_TOP_NE2A1_7", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_WR1END3_5", + "CMT_TOP_SW2A0_2", + "CMT_TOP_BYP7_8", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX23_3", + "CMT_TOP_IMUX47_7", + "CMT_TOP_WW4A1_8", + "CMT_TOP_BYP0_4", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_IMUX21_6", + "CMT_TOP_IMUX5_4", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX15_5", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_NW2A0_5", + "CMT_TOP_SW4A0_7", + "CMT_PHASER_IN_CA_STG1REGL2", + "CMT_TOP_NE4C1_2", + "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", + "CMT_TOP_LH12_4", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_WW2END0_1", + "CMT_TOP_WW4A1_7", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX5_3", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_PHASER_IN_DB_TESTIN13", + "CMT_PHASER_OUT_DB_CTSBUS0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_LH7_7", + "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_WW4C0_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "CMT_PHASER_IN_DB_WRENABLE", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX0_0", + "CMT_TOP_BYP5_4", + "CMT_TOP_FAN4_3", + "CMT_PHASER_OUT_CA_TESTIN15", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SW2A2_4", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_FAN6_2", + "CMT_TOP_WW4C2_0", + "CMT_TOP_IMUX20_6", + "CMT_TOP_ICLK_8", + "CMT_PHASER_OUT_A_OCLK1X_90", + "CMT_TOP_LH4_5", + "CMT_TOP_IMUX22_4", + "CMT_PHASER_B_OCLK_TOIOI", + "CMT_TOP_WR1END2_4", + "CMT_TOP_NW2A1_7", + "CMT_TOP_LH9_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_EE4C3_0", + "CMT_TOP_NE4C1_6", + "CMT_TOP_CTRL0_6", + "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "CMT_TOP_BYP2_0", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_WW4A0_6", + "CMT_TOP_IMUX6_8", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WW4END0_0", + "CMT_TOP_WR1END0_1", + "CMT_TOP_EE2A2_7", + "CMT_TOP_LH2_1", + "CMT_TOP_CLK0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_WW4END3_7", + "CMT_PHASER_OUT_CA_COARSEENABLE", + "CMT_PHASER_IN_CA_STG1REGR6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_SE4BEG0_1", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CMT_TOP_LH11_5", + "CMT_TOP_SW2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_WW4C1_5", + "CMT_TOP_BYP5_8", + "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "CMT_TOP_IMUX27_1", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_8", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_IMUX30_6", + "CMT_TOP_WL1END1_7", + "CMT_TOP_IMUX39_2", + "CMT_TOP_EE4C0_6", + "CMT_PHASER_OUT_DB_DTSBUS0", + "CMT_PHASER_IN_CA_COUNTERREADEN", + "CMT_TOP_IMUX10_8", + "CMT_PHASER_B_OCLKDIV_TOIOI", + "CMT_TOP_WW4C2_1", + "CMT_TOP_WW4END3_0", + "CMT_TOP_NW4A3_6", + "CMT_TOP_EE4C2_8", + "CMT_TOP_LH6_7", + "CMT_TOP_IMUX16_3", + "CMT_PHASER_IN_DB_TESTIN4", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_LH2_2", + "CMT_TOP_OCLK_8", + "CMT_TOP_NE2A0_6", + "CMT_TOP_WW2A3_2", + "CMT_TOP_WW4B1_8", + "CMT_TOP_CTRL1_6", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_WW4A3_0", + "CMT_TOP_FAN3_7", + "CMT_TOP_ER1BEG1_1", + "CMT_PHASER_IN_B_ICLK", + "CMT_TOP_EE4A0_8", + "CMT_TOP_SE4C1_3", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_IMUX25_5", + "CMT_TOP_IMUX8_5", + "CMT_TOP_IMUX9_1", + "CMT_TOP_CLK0_4", + "CMT_TOP_EE4A3_8", + "CMT_TOP_IMUX37_5", + "CMT_TOP_FAN5_3", + "CMT_TOP_EE4A1_4", + "CMT_TOP_IMUX31_6", + "CMT_TOP_IMUX38_7", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX28_6", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_CLK0_1", + "CMT_TOP_ICLK_7", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX15_3", + "CMT_TOP_IMUX23_1", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_WW2END1_6", + "CMT_PHASER_OUT_DB_TESTIN10", + "CMT_TOP_SW2A0_1", + "CMT_TOP_CTRL1_3", + "CMT_TOP_FAN2_3", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_IMUX10_7", + "CMT_TOP_NE4C2_8", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_NW2A1_6", + "CMT_TOP_SW4A0_4", + "CMT_TOP_IMUX6_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_IMUX8_3", + "CMT_PHASERA_CTSBUS0", + "CMT_TOP_NW2A3_4", + "CMT_TOP_IMUX27_8", + "CMT_PHASER_IN_CA_STG1REGR7", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_LH6_3", + "CMT_TOP_NE4C3_1", + "CMT_TOP_CTRL0_3", + "CMT_TOP_EE4C2_7", + "CMT_PHASER_IN_DB_ENSTG1", + "CMT_TOP_NE2A1_1", + "CMT_TOP_FAN0_8", + "CMT_PHASER_OUT_DB_TESTIN15", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_EE4BEG1_4", + "CMT_PHASER_IN_DB_TESTIN9", + "CMT_TOP_SW4A1_1", + "CMT_TOP_EL1BEG1_4", + "CMT_PHASER_IN_CA_SCANCLK", + "CMT_TOP_WW2END1_1", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_IMUX9_6", + "CMT_TOP_EE2A0_4", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX31_8", + "CMT_TOP_FAN1_7", + "CMT_TOP_WW4A3_3", + "CMT_TOP_ER1BEG0_4", + "CMT_PHASER_IN_CA_ENCALIBPHY0", + "CMT_TOP_IMUX28_7", + "CMT_TOP_NW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_SW4END2_1", + "CMT_TOP_EE4A3_3", + "CMT_PHASER_IN_DB_STG1REGL4", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_EE4A1_0", + "CMT_TOP_SW2A3_7", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_LH3_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_IMUX32_6", + "CMT_TOP_IMUX41_0", + "MMCM_CLK_FREQBB_REBUFOUT0", + "CMT_TOP_WR1END3_4", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_EE4B3_4", + "CMT_TOP_SE4BEG1_1", + "CMT_PHASER_OUT_CA_OCLKDELAYED", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX24_4", + "CMT_TOP_IMUX11_7", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_FAN6_6", + "CMT_TOP_SW2A2_5", + "CMT_TOP_FAN5_0", + "CMT_TOP_IMUX25_2", + "CMT_TOP_BYP2_3", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_FAN4_5", + "CMT_PHASER_IN_DB_TESTOUT2", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_WW2END2_7", + "CMT_TOP_NW4A1_3", + "CMT_TOP_SW4END1_8", + "CMT_TOP_IMUX35_4", + "CMT_TOP_IMUX41_5", + "CMT_TOP_IMUX17_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_NW4A1_8", + "CMT_TOP_IMUX10_6", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_LH12_6", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4A0_0", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_WW2A1_8", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NW2A2_0", + "CMT_TOP_NE4BEG1_6", + "MMCMOUT_CLK_FREQ_BB_REBUFIN0", + "CMT_PHASER_IN_DB_STG1REGL5", + "CMT_TOP_BYP7_1", + "CMT_TOP_IMUX11_2", + "CMT_TOP_WW2A0_0", + "CMT_TOP_SW4A2_1", + "CMT_TOP_LH1_3", + "CMT_PHASER_IN_A_RCLK0", + "CMT_TOP_FAN0_5", + "CMT_TOP_BYP2_7", + "CMT_TOP_EE2A1_8", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_WW4C3_7", + "CMT_TOP_LH2_3", + "CMT_TOP_FAN7_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_WW4END2_3", + "CMT_TOP_NE4C1_7", + "CMT_TOP_BYP0_0", + "CMT_PHASER_IN_CA_STG1REGL4", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_WW4END0_7", + "CMT_PHASER_IN_CA_TESTIN4", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_PHASER_OUT_CA_PHASEREFCLK", + "CMT_TOP_NW4A3_0", + "CMT_TOP_NE2A2_6", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "CMT_TOP_IMUX37_2", + "CMT_TOP_WR1END1_7", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CMT_PHASER_IN_CA_ENCALIB0", + "CMT_TOP_WW4END2_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX7_2", + "CMT_TOP_IMUX38_4", + "CMT_TOP_FAN2_1", + "CMT_TOP_NE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_IMUX27_2", + "CMT_TOP_WW4A0_7", + "CMT_TOP_WW4C0_6", + "CMT_PHASER_OUT_DB_TESTOUT1", + "CMT_TOP_EE4C0_8", + "CMT_PHASER_OUT_B_OCLK1X_90", + "CMT_PHASER_OUT_CA_DQSBUS1", + "CMT_TOP_SE4C0_3", + "CMT_TOP_IMUX1_8", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_BYP6_3", + "CMT_TOP_NE2A2_5", + "CMT_TOP_NW4A0_3", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_WR1END3_8", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_IMUX37_1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "CMT_TOP_NW2A1_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_NW2A3_6", + "CMT_TOP_WW4END3_5", + "CMT_TOP_WW4B1_5", + "CMT_TOP_WW4A1_4", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_NW2A2_3", + "CMT_TOP_WW2A2_6", + "CMT_TOP_EE4C0_7", + "CMT_TOP_IMUX17_0", + "CMT_TOP_CLK0_2", + "CMT_TOP_EE4B3_2", + "CMT_PHASER_OUT_CA_COUNTERREADEN", + "CMT_TOP_SW4END0_0", + "CMT_TOP_IMUX31_5", + "CMT_TOP_FAN0_0", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_IMUX37_6", + "CMT_TOP_EE4C3_2", + "CMT_TOP_BYP5_5", + "CMT_TOP_LH8_4", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_PHASER_IN_B_WRCLK_TOFIFO", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SE4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_IMUX46_5", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_IMUX43_7", + "CMT_TOP_IMUX46_3", + "CMT_TOP_IMUX40_1", + "CMT_TOP_EL1BEG0_1", + "CMT_PHASER_IN_CA_FREQREFCLK", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_NE4BEG0_2", + "CMT_PHASER_OUT_CA_TESTIN8", + "CMT_TOP_WW4END3_6", + "CMT_TOP_LH8_8", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "CMT_TOP_FAN2_5", + "CMT_TOP_CLK0_6", + "CMT_TOP_WW4B1_1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "CMT_TOP_IMUX10_5", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_PHASER_OUT_DB_COARSEENABLE", + "CMT_PHASER_DOWN_PHASERREF0", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_IMUX2_3", + "CMT_TOP_WW2A3_8", + "CMT_TOP_NE4C1_8", + "CMT_TOP_EE2A3_3", + "CMT_PHASER_DOWN_PHASERREF_ABOVE0", + "CMT_TOP_IMUX36_4", + "CMT_TOP_EE4A1_1", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_IMUX43_5", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4C0_4", + "CMT_TOP_SW2A0_3", + "CMT_PHASER_OUT_CA_TESTIN6", + "CMT_TOP_IMUX12_4", + "CMT_TOP_BYP0_6", + "CMT_TOP_LH10_3", + "CMT_TOP_SW2A3_8", + "CMT_TOP_LH3_2", + "CMT_TOP_WW2A2_5", + "CMT_TOP_EL1BEG3_7", + "CMT_PHASER_IN_CA_STG1INCDEC", + "CMT_TOP_SW4A0_6", + "CMT_TOP_IMUX38_6", + "CMT_TOP_WR1END0_5", + "CMT_PHASER_OUT_CA_TESTOUT2", + "CMT_TOP_IMUX4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_IMUX43_4", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_IMUX19_8", + "CMT_TOP_LH10_6", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_PHASER_BOT_IRANKB1", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_IMUX36_5", + "CMT_PHASER_IN_DB_RANKSEL0", + "CMT_TOP_WW2A0_3", + "CMT_TOP_LH10_5", + "CMT_PHASER_IN_DB_STG1INCDEC", + "CMT_TOP_WW4B0_3", + "CMT_TOP_NE4C3_3", + "CMT_TOP_FAN7_2", + "CMT_PHASER_IN_CA_STG1REGL6", + "CMT_TOP_SE2A2_6", + "CMT_TOP_BYP6_1", + "CMT_TOP_WL1END2_1", + "CMT_TOP_SW4A0_2", + "CMT_TOP_IMUX10_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_NW2A3_5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_LH5_2", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_SW2A2_6", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_WW4A2_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_PHASER_BOT_ENCALIB0", + "CMT_TOP_NW4END3_6", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_NW4END3_8", + "CMT_TOP_WL1END0_7", + "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "CMT_PHASER_OUT_DB_FINEENABLE", + "CMT_PHASER_IN_CA_STG1REGR2", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX9_7", + "CMT_TOP_BYP5_7", + "CMT_TOP_LH3_1", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END2_5", + "CMT_TOP_FAN0_6", + "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "CMT_TOP_SW2A1_6", + "CMT_TOP_EE2BEG2_8", + "CMT_PHASER_IN_CA_STG1READ", + "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX37_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_IMUX4_5", + "CMT_TOP_EE4B2_8", + "CMT_TOP_IMUX42_5", + "CMT_TOP_BYP4_0", + "CMT_PHASER_IN_DB_FREQREFCLK", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4C1_5", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LH4_4", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_PHASER_IN_DB_TESTOUT1", + "CMT_TOP_IMUX24_5", + "CMT_PHASER_OUT_DB_SCANCLK", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_EL1BEG1_1", + "CMT_PHASER_OUT_CA_TESTOUT0", + "CMT_TOP_SW2A2_8", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_6", + "CMT_TOP_WW4C1_2", + "CMT_TOP_FAN3_3", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_WR1END1_0", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_IMUX22_5", + "CMT_TOP_EE2A1_3", + "CMT_PHASER_OUT_DB_TESTIN1", + "CMT_TOP_SE2A2_2", + "CMT_TOP_OCLK_3", + "CMT_TOP_IMUX23_5", + "CMT_PHASER_OUT_CA_TESTIN11", + "CMT_PHASER_OUT_DB_TESTIN9", + "CMT_TOP_SW4END2_4", + "CMT_TOP_EE4A1_8", + "CMT_PHASER_OUT_CA_DTSBUS0", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW2END0_2", + "CMT_TOP_SE4C3_0", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_EE2A1_7", + "CMT_TOP_SE2A1_6", + "CMT_TOP_IMUX45_6", + "CMT_TOP_SW4END0_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX3_8", + "CMT_PHASER_OUT_DB_ENCALIB1", + "CMT_TOP_CTRL0_1", + "MMCM_CLK_FREQBB_REBUFOUT2", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_LH6_8", + "CMT_TOP_WW4B0_0", + "CMT_TOP_BYP1_5", + "CMT_BOT_HCLKMUX_CLKINT_0", + "CMT_TOP_SW4A1_4", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX6_5", + "CMT_TOP_IMUX46_6", + "CMT_PHASER_IN_DB_TESTIN2", + "CMT_TOP_WW4B0_4", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "CMT_TOP_LH10_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_IMUX45_0", + "CMT_TOP_WW4END3_3", + "CMT_TOP_WW4B3_2", + "CMT_PHASER_OUT_DB_DTSBUS1", + "CMT_PHASER_IN_CA_RCLK", + "CMT_TOP_IMUX39_1", + "CMT_TOP_FAN3_0", + "CMT_TOP_WL1END1_8", + "CMT_TOP_EE2A3_6", + "CMT_TOP_IMUX9_5", + "CMT_TOP_WW2END3_8", + "CMT_TOP_IMUX32_4", + "CMT_PHASERREF_DOWN_PHASEROUT_B", + "CMT_TOP_IMUX26_8", + "CMT_TOP_IMUX23_4", + "CMT_TOP_EE4A0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_EE4B0_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_WL1END0_2", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_SE2A0_2", + "CMT_TOP_EE2A2_6", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_IMUX44_4", + "CMT_TOP_IMUX25_3", + "CMT_TOP_EE4C1_5", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_IMUX29_4", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_PHASER_IN_CA_ICLKDIV", + "CMT_PHASER_IN_CA_RANKSELPHY1", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX32_0", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_SW4END2_3", + "CMT_TOP_BYP4_2", + "CMT_PHASER_IN_DB_RANKSELPHY0", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WL1END3_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_FAN5_4", + "CMT_TOP_EE2A2_2", + "CMT_TOP_EE4A2_1", + "CMT_TOP_IMUX34_4", + "CMT_TOP_LH7_2", + "CMT_TOP_LH6_1", + "CMT_TOP_NW4END2_2", + "CMT_TOP_WW4END0_8", + "CMT_TOP_LH11_8", + "CMT_TOP_IMUX45_5", + "CMT_TOP_IMUX18_2", + "CMT_PHASER_IN_DB_STG1REGL2", + "CMT_TOP_LH1_2", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_WR1END0_6", + "CMT_TOP_IMUX3_1", + "CMT_PHASER_IN_A_WRCLK_TOFIFO", + "CMT_PHASER_IN_CA_TESTIN1", + "CMT_TOP_WW4END3_1", + "CMT_TOP_IMUX13_2", + "CMT_TOP_WW4A0_8", + "CMT_TOP_FAN6_8", + "CMT_PHASER_OUT_A_RDEN_TOFIFO", + "CMT_TOP_IMUX17_7", + "CMT_TOP_IMUX16_2", + "CMT_TOP_FAN4_4", + "CMT_PHASERA_DQSBUS1", + "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "CMT_TOP_FAN7_3", + "CMT_TOP_NW4A0_2", + "CMT_TOP_BYP6_6", + "CMT_PHASER_IN_CA_WRENABLE", + "CMT_TOP_LH4_0", + "CMT_PHASER_IN_CA_ICLK", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_IMUX22_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_SW4END1_7", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NW4END0_6", + "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "CMT_TOP_WR1END3_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_EE4C3_6", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_PHASER_OUT_B_OCLK", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "CMT_TOP_NE2A3_7", + "CMT_TOP_FAN7_0", + "CMT_TOP_IMUX3_7", + "CMT_TOP_EE2BEG2_6", + "CMT_PHASER_OUT_DB_TESTIN5", + "CMT_TOP_SW4A1_2", + "CMT_TOP_BYP2_6", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_IMUX4_1", + "CMT_TOP_IMUX14_8", + "CMT_PHASER_IN_CA_RST", + "CMT_PHASER_IN_DB_TESTIN5", + "CMT_TOP_IMUX26_2", + "CMT_TOP_NE4C0_0", + "CMT_TOP_BYP0_3", + "CMT_PHASER_B_ICLKDIV_TOIOI", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_FAN1_8", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_IMUX11_8", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX5_6", + "CMT_TOP_IMUX38_0", + "CMT_PHASER_IN_DB_ENCALIB0", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_WW4END2_4", + "CMT_TOP_CLK1_7", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_PHASER_OUT_CA_TESTIN0", + "CMT_TOP_WW4B3_1", + "CMT_PHASER_BOT_OBURSTPENDING0", + "CMT_PHASER_OUT_DB_DQSBUS1", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_NW2A2_8", + "CMT_TOP_IMUX16_5", + "CMT_TOP_IMUX19_4", + "CMT_TOP_CLK1_4", + "CMT_TOP_LH8_3", + "CMT_TOP_SW2A1_3", + "CMT_PHASER_OUT_DB_TESTIN3", + "CMT_TOP_IMUX30_4", + "CMT_TOP_WW2END2_0", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_PHASER_IN_DB_DQSFOUND", + "CMT_TOP_IMUX45_2", + "CMT_PHASER_IN_DB_FINEOVERFLOW", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX28_1", + "CMT_TOP_NW4A0_0", + "CMT_TOP_EE4BEG3_4", + "CMT_PHASER_BOT_IRANKA1", + "CMT_TOP_EE4B1_2", + "CMT_TOP_LH3_7", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_WW4C0_0", + "CMT_TOP_SW2A1_7", + "CMT_TOP_BYP2_4", + "CMT_TOP_IMUX16_4", + "CMT_PHASER_IN_DB_TESTIN11", + "CMT_TOP_EE2A3_7", + "CMT_PHASER_IN_CA_FINEINC", + "CMT_TOP_EE4B3_1", + "CMT_TOP_SE4C3_3", + "CMT_TOP_WW2END0_0", + "CMT_TOP_BYP3_6", + "CMT_TOP_SW4END1_4", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_IMUX34_7", + "CMT_TOP_WW2A0_7", + "CMT_TOP_WW2A2_8", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_IMUX27_4", + "CMT_TOP_WW4B3_7", + "CMT_TOP_WL1END2_5", + "CMT_TOP_OCLK_1", + "CMT_TOP_NW4END0_2", + "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "CMT_TOP_EE2A1_5", + "CMT_TOP_SW4END3_4", + "CMT_PHASER_OUT_DB_TESTOUT2", + "CMT_TOP_FAN4_2", + "CMT_TOP_EE4C1_7", + "CMT_TOP_WW4C3_8", + "CMT_TOP_EE4B0_7", + "CMT_TOP_NW4END1_1", + "CMT_TOP_BYP0_8", + "CMT_LR_LOWER_T_CLK_PERF2", + "CMT_PHASER_IN_DB_FINEENABLE", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_WW4END1_7", + "CMT_TOP_FAN3_1", + "CMT_TOP_WW4C2_6", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_LR_LOWER_T_CLK_MMCM4", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX5_0", + "CMT_PHASER_OUT_DB_SYSCLK", + "CMT_PHASER_IN_CA_STG1REGL5", + "CMT_TOP_WR1END2_6", + "CMT_TOP_SE2A2_5", + "CMT_PHASER_OUT_CA_TESTIN5", + "CMT_TOP_SE4BEG1_4", + "CMT_PHASER_IN_DB_ENCALIB1", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_FAN2_7", + "CMT_TOP_WW4B0_7", + "CMT_TOP_BYP3_7", + "CMT_TOP_EE2BEG1_5", + "CMT_LR_LOWER_T_CLK_MMCM11", + "CMT_TOP_SW4A3_1", + "CMT_TOP_LH10_8", + "CMT_TOP_LH6_5", + "CMT_TOP_IMUX42_6", + "CMT_PHASER_IN_CA_SYNCIN", + "CMT_TOP_EE4B1_1", + "CMT_TOP_IMUX28_2", + "CMT_TOP_SE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_WW4A3_5", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "CMT_TOP_NW4A0_4", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WL1END0_3", + "CMT_PHASER_BOT_SYNC_BB", + "CMT_TOP_WW4C0_2", + "CMT_TOP_IMUX0_7", + "CMT_PHASER_OUT_DB_SCANENB", + "CMT_TOP_WW4B1_0", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SW4END0_8", + "CMT_TOP_NW4END2_8", + "CMT_TOP_IMUX8_1", + "CMT_TOP_EE4BEG3_6", + "CMT_PHASER_IN_CA_TESTIN8", + "CMT_TOP_IMUX34_6", + "CMT_TOP_SW2A1_1", + "CMT_PHASER_IN_DB_COUNTERREADEN", + "CMT_TOP_EE4B2_4", + "CMT_TOP_NE2A3_1", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX18_0", + "CMT_TOP_EE4B0_3", + "CMT_TOP_SE2A2_7", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_BYP6_4", + "CMT_TOP_NW4END1_6", + "CMT_PHASER_OUT_DB_TESTIN13", + "CMT_TOP_BYP2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_LH7_4", + "CMT_TOP_IMUX23_0", + "CMT_TOP_IMUX4_4", + "CMT_TOP_ER1BEG2_5", + "CMT_PHASER_IN_DB_RCLK", + "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "CMT_TOP_IMUX43_8", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX21_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX21_2", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C0_5", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_BYP4_4", + "CMT_TOP_EE4B0_5", + "CMT_TOP_WR1END2_1", + "CMT_PHASER_IN_CA_PHASELOCKED", + "CMT_TOP_EE2BEG0_7", + "MMCMOUT_CLK_FREQ_BB_REBUFIN1", + "CMT_PHASER_IN_DB_STG1READ", + "CMT_TOP_IMUX16_1", + "CMT_TOP_NW4A2_3", + "CMT_TOP_FAN2_6", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_6", + "CMT_PHASER_IN_DB_EDGEADV", + "CMT_TOP_WR1END3_7", + "CMT_TOP_WW4C0_1", + "CMT_TOP_WW2A3_0", + "CMT_TOP_FAN7_1", + "CMT_TOP_IMUX28_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_NW2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_PHASER_IN_CA_EDGEADV", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_FAN5_7", + "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "CMT_PHASER_OUT_CA_SCANCLK", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CMT_TOP_IMUX15_7", + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "CMT_TOP_IMUX4_3", + "CMT_TOP_LH8_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "CMT_TOP_EE4BEG3_3", + "CMT_PHASER_IN_CA_STG1REGR5", + "CMT_PHASER_OUT_A_OCLK", + "CMT_PHASER_IN_DB_STG1OVERFLOW", + "CMT_TOP_EE4A3_5", + "CMT_PHASER_B_ICLK_TOIOI", + "CMT_PHASERREF_DOWN_PHASEROUT_A", + "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_NE4C0_5", + "CMT_TOP_SE2A3_2", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_IMUX25_0", + "CMT_TOP_IMUX16_6", + "CMT_TOP_IMUX1_5", + "CMT_PHASER_IN_DB_RST", + "CMT_PHASER_IN_DB_STG1REGL0", + "CMT_TOP_SE4C1_4", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_IMUX34_2", + "CMT_TOP_LH10_2", + "CMT_PHASER_OUT_DB_OCLK", + "CMT_TOP_LH12_0", + "CMT_TOP_FAN4_0", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_NW4A3_1", + "CMT_TOP_NW4A0_8", + "CMT_TOP_EE4B3_5", + "CMT_TOP_BYP3_0", + "CMT_TOP_IMUX26_7", + "CMT_TOP_IMUX2_1", + "CMT_TOP_NE4C1_0", + "CMT_TOP_EE2A3_8", + "CMT_PHASER_IN_DB_STG1REGR5", + "CMT_PHASER_IN_CA_SELCALORSTG1", + "CMT_TOP_IMUX22_1", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_PHASER_IN_DB_ENCALIBPHY0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_EE2A3_5", + "CMT_TOP_IMUX40_0", + "CMT_TOP_IMUX14_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_IMUX4_7", + "CMT_TOP_SE2A2_0", + "CMT_TOP_EE4A0_2", + "CMT_TOP_LH2_4", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SW4A3_6", + "CMT_TOP_NW4END1_5", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WR1END3_1", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_BYP1_0", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_NE4BEG1_4", + "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "CMT_TOP_WW2A0_6", + "CMT_TOP_IMUX8_7", + "CMT_TOP_WW2END0_4", + "CMT_TOP_SE2A3_0", + "CMT_PHASER_IN_DB_STG1REGL7", + "CMT_TOP_SW4A1_7", + "CMT_TOP_LH10_7", + "CMT_TOP_EE4C2_3", + "CMT_TOP_SW4END2_5", + "CMT_TOP_SE4C3_5", + "CMT_PHASER_IN_CA_TESTIN9", + "CMT_PHASER_OUT_A_RDCLK_TOFIFO", + "CMT_TOP_LH4_1", + "CMT_TOP_SW4A1_6", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_SW2A2_0", + "CMT_TOP_BYP6_8", + "CMT_PHASER_DOWN_DQS_TO_PHASER_A", + "CMT_TOP_SW4END0_7", + "CMT_TOP_IMUX13_5", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SE2A1_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EE4A2_4", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_LH2_8", + "CMT_TOP_WR1END0_0", + "CMT_TOP_SE2A3_1", + "CMT_TOP_IMUX2_6", + "CMT_TOP_IMUX3_0", + "CMT_TOP_IMUX18_4", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4C2_4", + "CMT_TOP_WL1END1_5", + "CMT_TOP_NE4BEG1_5", + "CMT_PHASER_IN_CA_DQSFOUND", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_PHASER_IN_CA_STG1OVERFLOW", + "CMT_TOP_NE2A2_3", + "CMT_TOP_EE2BEG3_4", + "CMT_PHASER_IN_CA_FINEENABLE", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_WW4END1_3", + "CMT_PHASER_B_TOMMCM_OCLK", + "CMT_TOP_IMUX24_1", + "CMT_TOP_ER1BEG0_6", + "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "CMT_TOP_WW2END2_6", + "CMT_TOP_EE2A3_2", + "CMT_TOP_EE2A3_0", + "CMT_PHASER_OUT_DB_RST", + "CMT_TOP_IMUX23_8", + "CMT_TOP_WW4A3_8", + "CMT_TOP_IMUX40_6", + "CMT_TOP_WW2A3_7", + "CMT_TOP_WL1END2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_PHASER_OUT_CA_SCANIN", + "CMT_TOP_SW2A0_6", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_NW2A0_1", + "CMT_TOP_FAN1_0", + "CMT_TOP_IMUX6_0", + "CMT_PHASER_IN_CA_TESTOUT1", + "CMT_TOP_IMUX0_2", + "CMT_TOP_NW2A2_6", + "CMT_TOP_CTRL0_0", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_WR1END1_3", + "CMT_TOP_IMUX31_0", + "CMT_TOP_LH5_3", + "CMT_TOP_IMUX43_0", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_NW2A0_3", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4C3_0", + "CMT_TOP_IMUX18_1", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_LH11_1", + "CMT_TOP_SW2A1_8", + "CMT_TOP_EE4C3_4", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN7_4", + "CMT_TOP_NW4END0_4", + "CMT_TOP_ER1BEG3_8", + "CMT_TOP_FAN1_6", + "CMT_TOP_IMUX15_8", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_WW4B2_5", + "CMT_PHASER_OUT_DB_SCANMODEB", + "CMT_TOP_WR1END1_1", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C1_4", + "CMT_TOP_SW2A2_7", + "CMT_TOP_IMUX20_4", + "CMT_LR_LOWER_T_CLK_MMCM2", + "CMT_TOP_WW2A2_1", + "CMT_PHASER_OUT_CA_SCANOUT", + "CMT_R_TOP_LOWER_B_CLKINT_0", + "CMT_TOP_ICLK_5", + "CMT_PHASER_OUT_DB_DIVIDERST", + "CMT_TOP_SW2A0_7", + "CMT_PHASER_OUT_DB_OSERDESRST", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_FAN6_5", + "CMT_TOP_ER1BEG0_7", + "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "CMT_TOP_NW4A2_0", + "CMT_TOP_WW2A1_2", + "CMT_TOP_FAN4_1", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_WW4A1_6", + "CMT_PHASER_DOWN_PHASERREF1", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_PHASER_OUT_DB_TESTIN12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX0_4", + "CMT_TOP_WW2END0_6", + "CMT_TOP_CTRL1_0", + "CMT_TOP_WR1END0_7", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_IMUX20_3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EE4A2_5", + "CMT_TOP_FAN3_5", + "CMT_PHASER_OUT_CA_DTSBUS1", + "CMT_TOP_WW4B1_2", + "CMT_TOP_NW4END0_0", + "CMT_TOP_FAN6_3", + "CMT_TOP_FAN1_4", + "CMT_TOP_SW4A2_3", + "CMT_TOP_IMUX12_2", + "CMT_PHASER_OUT_B_RDCLK_TOFIFO", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_LH11_2", + "CMT_TOP_NW4A3_8", + "CMT_TOP_WW4B0_2", + "CMT_TOP_NE2A0_7", + "CMT_TOP_IMUX34_5", + "CMT_TOP_SE4C2_6", + "CMT_PHASER_IN_DB_TESTIN1", + "CMT_PHASER_IN_CA_TESTIN11", + "CMT_PHASER_OUT_CA_SCANMODEB", + "CMT_TOP_SW4END1_6", + "CMT_TOP_IMUX2_2", + "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "CMT_TOP_EE4C2_5", + "CMT_TOP_WL1END2_2", + "CMT_TOP_IMUX6_3", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW2END0_5", + "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "CMT_TOP_SE4C3_8", + "CMT_TOP_LH6_0", + "CMT_TOP_IMUX20_7", + "CMT_PHASER_IN_CA_RANKSEL0", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX29_3", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_IMUX35_7", + "CMT_PHASER_IN_A_ICLK", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_WL1END1_6", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_NW4A2_5", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX9_2", + "CMT_TOP_IMUX19_5", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_WW4END2_2", + "CMT_TOP_WL1END0_8", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_IMUX47_6", + "CMT_TOP_NE2A3_4", + "CMT_TOP_IMUX40_3", + "CMT_TOP_IMUX23_2", + "CMT_PHASER_BOT_IBURSTPENDING0", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_IMUX39_6", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_PHASER_IN_A_ICLKDIV", + "CMT_TOP_EL1BEG2_1", + "CMT_BOT_HCLKMUX_CLKINT_1", + "CMT_TOP_IMUX6_4", + "CMT_TOP_ICLK_3", + "CMT_TOP_IMUX12_3", + "CMT_TOP_SW4END0_6", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_LH8_2", + "CMT_TOP_IMUX41_6", + "CMT_PHASER_OUT_CA_OCLKDIV", + "CMT_TOP_BYP2_5", + "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_IMUX38_8", + "CMT_TOP_IMUX0_6", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SW4A2_6", + "CMT_TOP_EE4C0_2", + "CMT_TOP_SE2A0_8", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NE2A0_1", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_IMUX31_4", + "CMT_TOP_IMUX11_3", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_IMUX47_2", + "CMT_TOP_IMUX5_1", + "CMT_TOP_LH12_1", + "CMT_TOP_IMUX26_1", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_LH5_8", + "CMT_TOP_WW2END3_6", + "CMT_TOP_NW2A0_8", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_WW4A2_8", + "CMT_TOP_IMUX44_3", + "CMT_TOP_WW4A3_4", + "CMT_TOP_LH3_4", + "CMT_TOP_EE2A2_1", + "CMT_TOP_WW4A2_3", + "CMT_TOP_LH11_4", + "CMT_TOP_NW2A3_2", + "CMT_TOP_IMUX34_0", + "CMT_TOP_BYP1_6", + "CMT_TOP_WW4B0_1", + "CMT_LR_LOWER_T_CLK_IN2_HCLK", + "CMT_TOP_IMUX2_4", + "CMT_TOP_SW4A1_8", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX39_8", + "CMT_TOP_IMUX29_7", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX33_3", + "CMT_TOP_SW4END2_7", + "CMT_TOP_SW2A2_3", + "CMT_TOP_FAN2_4", + "CMT_TOP_EE4A1_6", + "CMT_TOP_EE4B1_3", + "CMT_TOP_IMUX44_8", + "CMT_PHASER_IN_CA_STG1REGL1", + "CMT_TOP_WW4END0_1", + "CMT_TOP_IMUX9_4", + "CMT_TOP_IMUX32_7", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SE2A0_5", + "CMT_TOP_SW2A3_0", + "CMT_TOP_EE4B1_0", + "CMT_TOP_WW4A2_2", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_IMUX32_1", + "CMT_TOP_LH8_1", + "CMT_TOP_SE2A2_1", + "CMT_PHASER_IN_CA_SCANENB", + "CMT_TOP_IMUX10_3", + "CMT_TOP_WL1END3_2", + "CMT_LR_LOWER_T_CLK_MMCM9", + "CMT_PHASER_IN_CA_ENCALIBPHY1", + "CMT_TOP_WW4C3_3", + "CMT_TOP_SE4C3_1", + "CMT_TOP_NW4A2_8", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX26_3", + "CMT_TOP_IMUX24_6", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_IMUX35_5", + "CMT_TOP_WW4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_NE4C3_2", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "CMT_TOP_NE2A3_8", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_WW4END3_4", + "CMT_TOP_LH1_1", + "CMT_TOP_IMUX17_1", + "CMT_TOP_CTRL1_5", + "CMT_TOP_EE4C3_7", + "CMT_TOP_IMUX15_1", + "CMT_LR_LOWER_T_CLK_PERF1", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_IMUX32_2", + "CMT_PHASER_IN_DB_TESTIN8", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_CLK0_8", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_NE2A0_5", + "CMT_TOP_SW4END2_6", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_ICLK_6", + "CMT_PHASER_IN_CA_RSTDQSFIND", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_EE4C3_5", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_SE2A3_7", + "CMT_PHASERREF_DOWN_PHASERIN_A", + "CMT_PHASER_IN_CA_TESTOUT0", + "CMT_TOP_IMUX8_8", + "CMT_LR_LOWER_T_CLK_MMCM0", + "CMT_TOP_EE4B2_3", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_WW2A0_8", + "CMT_TOP_EE2A2_4", + "CMT_TOP_IMUX0_3", + "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "CMT_TOP_IMUX13_1", + "CMT_TOP_NE2A3_5", + "CMT_TOP_SW4END0_5", + "CMT_TOP_SW4A2_2", + "CMT_PHASER_OUT_CA_ENCALIB1", + "CMT_TOP_WW2END0_3", + "CMT_PHASER_IN_DB_RANKSEL1", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_PHASER_IN_DB_TESTIN7", + "CMT_TOP_EE4C1_3", + "CMT_TOP_EE4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_TOP_CTRL1_1", + "CMT_TOP_SE4BEG0_8", + "CMT_PHASER_IN_DB_STG1REGL8", + "CMT_PHASER_OUT_CA_OCLK", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_NW2A2_4", + "CMT_PHASERREF_DOWN_PHASERIN_B", + "CMT_TOP_FAN3_6", + "CMT_TOP_FAN2_2", + "CMT_TOP_LH5_4", + "CMT_TOP_IMUX37_3", + "CMT_TOP_IMUX37_8", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_IMUX47_3", + "CMT_LR_LOWER_T_CLK_IN3_HCLK", + "CMT_TOP_SW4A3_5", + "CMT_TOP_CTRL1_2", + "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_EE2A1_4", + "CMT_TOP_NW4END1_4", + "CMT_TOP_IMUX25_1", + "CMT_TOP_EE4B0_0", + "CMT_TOP_SE2A0_0", + "CMT_PHASER_OUT_DB_TESTIN11", + "CMT_TOP_IMUX25_8", + "CMT_TOP_EE4A1_3", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_NW4A2_4", + "CMT_TOP_NW2A3_7", + "CMT_TOP_IMUX3_2", + "CMT_LR_LOWER_T_CLK_MMCM8", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_SE2A1_7", + "CMT_TOP_EE4BEG3_0", + "CMT_PHASER_OUT_DB_TESTIN8", + "CMT_TOP_WW4END1_0", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_EE2A1_2", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_NW4END2_6", + "CMT_PHASER_IN_CA_SCANMODEB", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WW4C2_8", + "CMT_TOP_IMUX34_1", + "CMT_TOP_IMUX32_5", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_NW4A2_1", + "CMT_TOP_SW4A2_4", + "CMT_PHASER_OUT_CA_MEMREFCLK", + "CMT_TOP_NE2A2_1", + "CMT_TOP_CTRL1_8", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NW4END3_3", + "CMT_TOP_WW4B2_2", + "CMT_TOP_IMUX18_3", + "CMT_PHASER_IN_CA_STG1REGL3", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_LH9_4", + "CMT_TOP_NE4C3_6", + "CMT_TOP_WW4A0_3", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WW2END3_1", + "CMT_TOP_LH5_1", + "CMT_TOP_WL1END0_4", + "CMT_TOP_BYP4_3", + "CMT_TOP_IMUX44_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "CMT_TOP_SW2A3_3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "CMT_TOP_SE2A2_3", + "CMT_PHASER_OUT_CA_TESTIN9", + "CMT_TOP_SE2A0_7", + "CMT_TOP_WW2END2_2", + "CMT_PHASER_IN_DB_STG1REGR2", + "CMT_TOP_SE4C2_4", + "CMT_TOP_BYP7_5", + "CMT_TOP_EE4C2_0", + "CMT_TOP_IMUX0_8", + "CMT_TOP_SW2A1_2", + "CMT_TOP_NE4C1_3", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX18_8", + "CMT_TOP_EE4B1_6", + "CMT_TOP_IMUX20_5", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_BYP3_4", + "CMT_PHASER_B_TOMMCM_ICLKDIV", + "CMT_TOP_SW4A3_7", + "CMT_TOP_CLK1_5", + "CMT_TOP_SW2A0_4", + "CMT_TOP_BYP5_0", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_SW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_IMUX13_7", + "CMT_PHASER_IN_DB_STG1LOAD", + "CMT_TOP_NE4C2_2", + "CMT_TOP_IMUX10_4", + "CMT_TOP_LH1_4", + "CMT_PHASER_OUT_DB_TESTIN6", + "CMT_TOP_NW4A0_6", + "CMT_PHASER_IN_DB_ISERDESRST", + "CMT_TOP_EE2A0_6", + "CMT_TOP_WW4END3_8", + "CMT_TOP_NW4END1_0", + "CMT_TOP_IMUX46_7", + "CMT_PHASER_IN_DB_SYSCLK", + "CMT_TOP_EE4C2_2", + "CMT_PHASER_IN_DB_STG1REGR7", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_WW2END3_4", + "CMT_PHASER_IN_DB_FINEINC", + "CMT_TOP_WW4C1_8", + "CMT_PHASER_IN_DB_SYNCIN", + "CMT_TOP_WR1END1_8", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE2A2_8", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4B3_6", + "CMT_TOP_EE4C3_1", + "CMT_PHASER_IN_DB_SCANCLK", + "CMT_TOP_EE4B3_7", + "CMT_TOP_NW4END0_7", + "CMT_PHASER_IN_CA_SCANOUT", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX22_7", + "CMT_TOP_IMUX13_6", + "CMT_TOP_NW2A2_5", + "CMT_TOP_EE4A2_6", + "CMT_TOP_LH7_3", + "CMT_TOP_IMUX20_0", + "CMT_TOP_IMUX20_1", + "CMT_TOP_WW4B1_3", + "CMT_TOP_FAN5_8", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_OCLK_4", + "CMT_PHASER_IN_DB_STG1REGL1", + "CMT_TOP_SE4C2_0", + "CMT_TOP_WR1END2_2", + "CMT_TOP_WW2A0_1", + "CMT_TOP_NE2A0_8", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_IMUX11_5", + "CMT_TOP_WW2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_WW4B0_8", + "CMT_PHASER_IN_DB_PHASELOCKED", + "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_WW4A1_5", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LH5_7", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX35_1", + "CMT_PHASER_IN_DB_STG1REGR0", + "CMT_TOP_IMUX43_2", + "CMT_TOP_LH12_5", + "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "CMT_PHASER_OUT_CA_SYNCIN", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_IMUX46_1", + "CMT_TOP_EE4C2_6", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_WL1END1_3", + "CMT_TOP_WW4C3_1", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_NW2A3_8", + "CMT_TOP_ICLK_1", + "CMT_TOP_SE2A3_4", + "CMT_TOP_NE4C2_6", + "CMT_TOP_IMUX26_5", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_IMUX25_6", + "CMT_TOP_BYP0_2", + "CMT_TOP_BYP6_7", + "CMT_TOP_IMUX42_1", + "CMT_PHASER_IN_CA_TESTIN12", + "CMT_TOP_BYP7_6", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_NE2A1_8", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_NW4A3_2", + "CMT_TOP_SW4A0_5", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_5", + "CMT_TOP_IMUX4_6", + "CMT_TOP_WW4B2_0", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_WW4END0_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_IMUX3_6", + "CMT_TOP_WW2A3_1", + "CMT_PHASER_IN_CA_BURSTPENDING", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_PHASER_IN_DB_SCANMODEB", + "CMT_TOP_WL1END3_0", + "CMT_TOP_WW4END0_3", + "CMT_TOP_IMUX35_3", + "CMT_TOP_NW4END0_1", + "CMT_LR_LOWER_T_CLK_MMCM3", + "CMT_TOP_LH6_6", + "CMT_TOP_LH12_2", + "CMT_TOP_NE4C3_5", + "CMT_TOP_NW4END0_8", + "CMT_PHASER_BOT_REFMUX_2", + "CMT_TOP_IMUX39_0", + "CMT_TOP_WW4END2_0", + "MMCM_CLK_FREQBB_REBUFOUT1", + "CMT_PHASER_IN_CA_STG1REGL0", + "CMT_TOP_WW4END2_6", + "CMT_TOP_WW4B3_4", + "CMT_TOP_LH11_7", + "CMT_PHASER_B_TOMMCM_OCLK1X_90", + "CMT_TOP_SW4END3_3", + "CMT_PHASER_OUT_CA_TESTIN14", + "CMT_TOP_IMUX9_0", + "CMT_TOP_NW4A1_7", + "CMT_TOP_WW2A3_5", + "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "CMT_TOP_FAN2_0", + "CMT_TOP_IMUX19_6", + "CMT_TOP_IMUX30_5", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_FAN4_8", + "CMT_PHASER_IN_B_RCLK1", + "CMT_TOP_NW4END2_5", + "CMT_TOP_IMUX34_3", + "CMT_TOP_NE4C0_7", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WW2END2_4", + "CMT_PHASER_IN_DB_TESTIN6", + "CMT_PHASER_IN_DB_STG1REGR3", + "CMT_TOP_CLK0_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4C3_7", + "CMT_TOP_WW4A3_1", + "CMT_TOP_WL1END3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_IMUX35_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_SW4A3_4", + "CMT_TOP_IMUX10_0", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NW2A0_2", + "CMT_TOP_LH11_3", + "CMT_TOP_IMUX17_6", + "CMT_TOP_WL1END3_7", + "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_SE2A1_2", + "CMT_TOP_IMUX7_0", + "CMT_TOP_IMUX34_8", + "CMT_TOP_IMUX20_2", + "CMT_TOP_LH8_7", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WW4A2_5", + "CMT_TOP_WR1END3_3", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_OCLK_6", + "CMT_TOP_IMUX46_4", + "CMT_TOP_WW4C2_4", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_IMUX22_0", + "CMT_TOP_SE4C1_0", + "CMT_TOP_IMUX14_5", + "CMT_TOP_BYP4_7", + "CMT_PHASER_IN_CA_STG1REGR8", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_EE4C1_1", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX13_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_BYP0_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_NW2A1_8", + "CMT_TOP_SE2A2_4", + "CMT_TOP_IMUX7_5", + "CMT_TOP_SE4C2_1", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_WW2A1_5", + "CMT_TOP_SE4C2_3", + "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "CMT_TOP_NE4C0_3", + "CMT_LR_LOWER_T_CLK_MMCM5", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_NW4END3_4", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX27_5", + "CMT_TOP_OCLK_0", + "CMT_TOP_LH7_8", + "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "CMT_TOP_LH9_8", + "CMT_PHASER_IN_CA_DIVIDERST", + "CMT_TOP_IMUX7_8", + "CMT_TOP_ICLK_0", + "CMT_TOP_WW2END2_3", + "CMT_TOP_NE2A2_0", + "CMT_PHASER_OUT_CA_CTSBUS1", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END1_5", + "CMT_TOP_IMUX44_6", + "CMT_PHASER_IN_CA_MEMREFCLK", + "CMT_TOP_WW4C1_6", + "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "CMT_TOP_IMUX22_3", + "CMT_TOP_NE4C2_4", + "CMT_PHASER_IN_CA_ENSTG1", + "CMT_PHASER_IN_CA_TESTIN0", + "CMT_TOP_WL1END1_2", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_IMUX42_7", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_WL1END3_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_EE2A3_1", + "CMT_PHASER_IN_DB_ENCALIBPHY1", + "CMT_TOP_SE4C3_6", + "CMT_TOP_SE2A0_6", + "CMT_TOP_NE2A2_4", + "CMT_PHASER_OUT_CA_TESTIN2", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_SW4A3_8", + "CMT_TOP_EE4B1_7", + "CMT_TOP_SE4C1_6", + "CMT_TOP_WW2A2_0", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX13_3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_PHASER_OUT_CA_RST", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_MONITOR_P_2", + "CMT_PHASER_IN_DB_TESTIN0", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX41_4", + "CMT_TOP_WL1END0_1", + "CMT_TOP_NW4END2_4", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX28_4", + "CMT_PHASER_IN_CA_RANKSEL1", + "CMT_TOP_FAN5_1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH1_8", + "CMT_PHASER_IN_CA_TESTOUT3", + "CMT_TOP_IMUX42_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_WL1END1_1", + "CMT_PHASER_OUT_CA_TESTIN1", + "CMT_TOP_FAN5_2", + "CMT_TOP_NW2A1_1", + "CMT_TOP_FAN1_1", + "CMT_PHASER_BOT_REFMUX_0", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_IMUX5_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "CMT_TOP_SE4BEG3_1", + "CMT_LR_LOWER_T_CLK_PERF3", + "CMT_TOP_WW2END2_8", + "CMT_TOP_EE2A0_8", + "CMT_TOP_LH7_1", + "CMT_TOP_NE2A1_5", + "CMT_TOP_SW2A3_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "CMT_PHASER_OUT_CA_TESTIN13", + "CMT_TOP_CLK1_0", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "CMT_TOP_NW4A1_4", + "CMT_TOP_IMUX19_3", + "CMT_TOP_NE4C2_5", + "CMT_TOP_WW4B2_8", + "CMT_LR_LOWER_T_CLK_MMCM10", + "CMT_TOP_SE4BEG1_3", + "CMT_PHASER_IN_CA_RANKSELPHY0", + "CMT_TOP_FAN0_7", + "CMT_TOP_WW2END1_4", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_NW4END3_7", + "CMT_TOP_CLK1_2", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_SE4BEG3_7", + "CMT_TOP_EE4B0_6", + "CMT_PHASER_OUT_DB_OCLKDELAYED", + "CMT_TOP_EE4B2_5", + "CMT_TOP_IMUX42_2", + "CMT_PHASER_OUT_DB_FREQREFCLK", + "CMT_TOP_WW4B2_6", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_IMUX19_0", + "CMT_TOP_WW2A2_2", + "CMT_TOP_SW4A2_5", + "CMT_TOP_NE2A3_2", + "CMT_PHASER_OUT_CA_SCANENB", + "CMT_TOP_IMUX43_1", + "CMT_TOP_LH3_3", + "CMT_TOP_IMUX31_2", + "CMT_PHASER_IN_CA_SCANIN", + "CMT_TOP_IMUX38_5", + "CMT_TOP_EE4C1_4", + "CMT_TOP_LH4_2", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_WW4B1_6", + "CMT_TOP_IMUX42_0", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_SW2A0_0", + "CMT_TOP_WW4A3_7", + "CMT_TOP_IMUX24_7", + "CMT_PHASERA_CTSBUS1", + "CMT_TOP_IMUX47_4", + "CMT_TOP_SW4A1_3", + "CMT_TOP_NE2A1_2", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_IMUX39_4", + "CMT_PHASER_BOT_OBURSTPENDING1", + "CMT_TOP_BYP5_2", + "CMT_PHASER_OUT_CA_EDGEADV", + "CMT_TOP_WW2A0_4", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_FAN7_8", + "CMT_PHASER_IN_DB_RANKSELPHY1", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_IMUX40_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_IMUX30_1", + "CMT_PHASER_OUT_CA_TESTOUT1", + "CMT_TOP_IMUX0_1", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_IMUX39_3", + "CMT_TOP_IMUX33_0", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_NE4C1_1", + "CMT_TOP_FAN6_1", + "CMT_TOP_IMUX27_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "CMT_PHASER_B_TOMMCM_OCLKDIV", + "CMT_TOP_NE4C3_8", + "CMT_TOP_IMUX28_3", + "CMT_PHASER_DOWN_PHASERREF_BELOW1", + "CMT_TOP_IMUX1_4", + "CMT_TOP_IMUX13_4", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_IMUX37_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "CMT_TOP_EE4B1_8", + "CMT_TOP_OCLKDIV_2", + "CMT_PHASER_IN_DB_ICLKDIV", + "CMT_TOP_IMUX44_1", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX29_1", + "CMT_TOP_SE4C2_8", + "CMT_TOP_LH1_5", + "CMT_TOP_NW4A0_1", + "CMT_TOP_NE2A0_4" + ], + "tile_type": "CMT_TOP_R_LOWER_T", + "sites": [ + { + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", + "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", + "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", + "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", + "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", + "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", + "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", + "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", + "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", + "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", + "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", + "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", + "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", + "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", + "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", + "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", + "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", + "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", + "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", + "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", + "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", + "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", + "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", + "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", + "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", + "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "OCLK": "CMT_PHASER_OUT_CA_OCLK", + "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", + "RST": "CMT_PHASER_OUT_CA_RST", + "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", + "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", + "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", + "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", + "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", + "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", + "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", + "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", + "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", + "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", + "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE" + }, + "type": "PHASER_OUT_PHY", + "prefix": "PHASER_OUT_PHY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", + "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", + "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", + "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", + "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", + "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", + "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", + "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", + "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", + "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", + "RCLK": "CMT_PHASER_IN_CA_RCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", + "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", + "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", + "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", + "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", + "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", + "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", + "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", + "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "STG1READ": "CMT_PHASER_IN_CA_STG1READ", + "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", + "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", + "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", + "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", + "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", + "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", + "SCANENB": "CMT_PHASER_IN_CA_SCANENB", + "FINEINC": "CMT_PHASER_IN_CA_FINEINC", + "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", + "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", + "ICLK": "CMT_PHASER_IN_CA_ICLK", + "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", + "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", + "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", + "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", + "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", + "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", + "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", + "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", + "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", + "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", + "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", + "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", + "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", + "RST": "CMT_PHASER_IN_CA_RST", + "SCANIN": "CMT_PHASER_IN_CA_SCANIN", + "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", + "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", + "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", + "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", + "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", + "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", + "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", + "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", + "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", + "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", + "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", + "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", + "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", + "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", + "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", + "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", + "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", + "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", + "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", + "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST" + }, + "type": "PHASER_IN_PHY", + "prefix": "PHASER_IN_PHY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", + "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", + "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", + "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", + "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", + "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", + "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", + "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", + "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", + "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", + "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", + "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", + "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", + "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", + "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", + "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", + "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", + "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", + "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", + "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", + "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", + "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", + "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", + "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", + "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", + "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "OCLK": "CMT_PHASER_OUT_DB_OCLK", + "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", + "RST": "CMT_PHASER_OUT_DB_RST", + "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", + "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", + "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", + "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", + "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", + "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", + "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", + "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", + "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", + "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", + "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE" + }, + "type": "PHASER_OUT_PHY", + "prefix": "PHASER_OUT_PHY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", + "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", + "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", + "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", + "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", + "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", + "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", + "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", + "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", + "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", + "RCLK": "CMT_PHASER_IN_DB_RCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", + "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", + "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", + "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", + "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", + "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", + "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", + "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", + "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "STG1READ": "CMT_PHASER_IN_DB_STG1READ", + "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", + "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", + "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", + "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", + "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", + "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", + "SCANENB": "CMT_PHASER_IN_DB_SCANENB", + "FINEINC": "CMT_PHASER_IN_DB_FINEINC", + "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", + "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", + "ICLK": "CMT_PHASER_IN_DB_ICLK", + "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", + "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", + "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", + "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", + "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", + "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", + "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", + "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", + "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", + "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", + "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", + "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", + "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", + "RST": "CMT_PHASER_IN_DB_RST", + "SCANIN": "CMT_PHASER_IN_DB_SCANIN", + "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", + "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", + "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", + "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", + "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", + "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", + "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", + "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", + "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", + "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", + "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", + "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", + "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", + "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", + "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", + "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", + "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", + "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", + "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", + "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST" + }, + "type": "PHASER_IN_PHY", + "prefix": "PHASER_IN_PHY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_TOP_R_UPPER_B.json b/artix7/tile_type_CMT_TOP_R_UPPER_B.json index 5e451ad..2d85052 100644 --- a/artix7/tile_type_CMT_TOP_R_UPPER_B.json +++ b/artix7/tile_type_CMT_TOP_R_UPPER_B.json @@ -1,6524 +1,6524 @@ { - "wires": [ - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_EE2A0_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_IMUX44_11", - "CMT_TOP_BYP5_2", - "CMT_PHY_CONTROL_IBURSTPENDING3", - "CMT_TOP_EE2A3_5", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX19_0", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_TOP_LH11_4", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2END3_7", - "CMT_TOP_BYP6_0", - "CMT_TOP_NW2A2_9", - "CMT_TOP_IMUX44_1", - "CMT_TOP_NE2A1_8", - "CMT_TOP_EE4C1_11", - "CMT_TOP_IMUX39_5", - "CMT_TOP_WW2A2_6", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_TOP_IMUX44_10", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_TOP_NW2A0_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_NW4A0_2", - "CMT_TOP_WW2END0_8", - "CMT_TOP_SW4A0_1", - "CMT_FREQ_BB_PREF_IN2", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_WW4A2_2", - "CMT_TOP_IMUX23_0", - "CMT_R_TOP_UPPER_B_CLKFBIN", - "CMT_TOP_WW4C0_8", - "CMT_TOP_BYP6_1", - "CMT_TOP_SE2A0_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_SW2A2_1", - "CMT_TOP_FAN0_1", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_TOP_WW4END0_6", - "CMT_TOP_SW2A1_4", - "CMT_R_TOP_UPPER_B_CLKPLL2", - "CMT_TOP_EE2A2_10", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_EE4B1_10", - "CMT_TOP_BYP5_3", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_WW4B0_10", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_WW4C2_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX14_3", - "CMT_TOP_BYP7_6", - "CMT_PHASERD_DTSBUS1", - "CMT_TOP_NW2A2_8", - "CMT_TOP_SE2A1_0", - "CMT_TOP_CTRL1_4", - "CMT_TOP_ICLK_11", - "CMT_PHASER_REF_TESTOUT7", - "CMT_TOP_IMUX0_0", - "CMT_TOP_FAN7_11", - "CMT_TOP_IMUX15_11", - "CMT_TOP_EL1BEG0_0", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_PHY_CONTROL_IRANKD1", - "CMT_TOP_NW4END1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_EE4C0_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_IMUX10_0", - "CMT_PHASER_OUT_D_OCLKDIV", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_TOP_NW2A2_1", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_NE4C0_0", - "CMT_TOP_EE2A1_11", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_WW4END0_3", - "CMT_TOP_IMUX28_9", - "CMT_PHASER_REF_PWRDWN", - "CMT_TOP_NE4C3_6", - "CMT_TOP_LH9_1", - "CMT_TOP_EE4A3_1", - "CMT_TOP_WW2A0_6", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_IMUX10_4", - "CMT_TOP_BYP0_1", - "CMT_TOP_NE2A0_4", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX19_10", - "CMT_PHASER_REF_TESTOUT5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_EE2BEG3_6", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_FREQ_PHASER_REFMUX_1", - "CMT_TOP_LH10_7", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_WW4B3_11", - "CMT_TOP_NW4A3_1", - "CMT_TOP_EE4A2_6", - "CMT_TOP_WL1END0_10", - "CMT_TOP_SW2A3_4", - "CMT_TOP_IMUX41_11", - "CMT_TOP_OCLK_2", - "CMT_TOP_SE4C3_11", - "CMT_TOP_EE4B2_3", - "CMT_PHY_CONTROL_INRANKB1", - "CMT_PHY_CONTROL_IBURSTPENDING0", - "CMT_TOP_SE2A0_2", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LH11_7", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX12_6", - "CMT_TOP_SW4END3_6", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_WW2END1_1", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_IMUX29_11", - "PLL_CLK_FREQBB_REBUFOUT0", - "CMT_TOP_WL1END2_5", - "CMT_PHASER_UP_PHASERREF1", - "CMT_TOP_WR1END1_8", - "CMT_TOP_IMUX12_5", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX39_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX10_6", - "CMT_TOP_SE2A2_7", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_EE4B3_8", - "CMT_TOP_IMUX5_8", - "CMT_TOP_WW2A1_1", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX28_4", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_TOP_IMUX2_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_SW2A2_11", - "CMT_TOP_IMUX47_5", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_WW4B1_7", - "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_WR1END2_11", - "CMT_TOP_IMUX38_5", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX6_6", - "CMT_TOP_SW4END1_0", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX30_10", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_WL1END3_6", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_SE2A2_0", - "CMT_PHY_CONTROL_TESTINPUT14", - "CMT_TOP_IMUX27_0", - "CMT_PHY_CONTROL_PHYCLK", - "CMT_TOP_SE2A2_8", - "CMT_TOP_IMUX26_10", - "CMT_TOP_WW2END2_7", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_WR1END3_7", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_IMUX39_9", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_TOP_LH11_8", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4A0_8", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_TOP_IMUX21_3", - "CMT_TOP_LH1_6", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX17_6", - "CMT_TOP_EE2A0_10", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_PHASER_OUT_C_RDENABLE_TOFIFO", - "CMT_TOP_IMUX37_11", - "CMT_TOP_EE4B2_9", - "CMT_TOP_SE4C1_10", - "CMT_TOP_LH5_5", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_R_TOP_UPPER_B_CLKPLL3", - "CMT_TOP_EE2A2_5", - "CMT_TOP_LH4_8", - "CMT_TOP_IMUX45_1", - "CMT_TOP_SW4A0_4", - "CMT_TOP_FAN2_4", - "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX19_5", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_TOP_EE4B1_0", - "CMT_TOP_NW4END3_10", - "CMT_TOP_BYP7_7", - "CMT_PHASER_UP_PHASERREF_BELOW1", - "CMT_PHASER_IN_C_WRENABLE_FIFO", - "CMT_TOP_BYP3_9", - "CMT_TOP_EE4B0_9", - "CMT_PHASER_OUT_C_RDCLK_TOFIFO", - "CMT_TOP_IMUX25_10", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_TOP_WR1END0_3", - "CMT_TOP_SW4A2_8", - "CMT_PHY_CONTROL_TESTOUTPUT11", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_SW4A0_3", - "CMT_TOP_CLK0_6", - "CMT_TOP_SE2A3_4", - "CMT_TOP_FAN7_9", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_TOP_IMUX39_10", - "CMT_TOP_LH7_6", - "CMT_TOP_EE2A2_11", - "CMT_TOP_IMUX41_1", - "CMT_TOP_NE4C2_7", - "CMT_PHASER_IN_D_WRCLK_TOFIFO", - "CMT_TOP_SW4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LH7_8", - "CMT_TOP_WR1END2_7", - "CMT_TOP_FAN6_3", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_TOP_WW2A0_7", - "CMT_TOP_BYP4_2", - "CMT_TOP_IMUX33_11", - "CMT_PHY_CONTROL_INRANKB0", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_WW4END0_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_WW4A0_7", - "CMT_TOP_LH9_3", - "CMT_TOP_NE2A0_5", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_TOP_EE4C3_2", - "CMT_PHASER_TOP_SYNC_BB", - "CMT_TOP_LH5_10", - "CMT_TOP_NE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_EE4C1_3", - "CMT_TOP_SW4A1_8", - "CMT_TOP_CTRL0_8", - "CMT_TOP_NW2A0_4", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX21_9", - "CMT_TOP_WL1END1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_TOP_LH4_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_CTRL1_0", - "CMT_TOP_LH11_10", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_SE2A3_11", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_SW2A3_0", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_TOP_BYP7_5", - "CMT_TOP_ICLK_7", - "CMT_TOP_WW4C3_7", - "CMT_TOP_EE4BEG1_8", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_TOP_FAN1_0", - "CMT_TOP_SW4END1_4", - "CMT_TOP_EE4C3_3", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX9_5", - "CMT_PHASER_IN_C_WRCLK_TOFIFO", - "CMT_TOP_WW4B1_11", - "CMT_PHY_CONTROL_PHYCTLWD3", - "CMT_TOP_IMUX13_9", - "CMT_TOP_FAN6_8", - "CMT_TOP_SE2A2_10", - "CMT_TOP_WW4A0_0", - "CMT_TOP_CTRL0_5", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_WW2A1_11", - "CMT_TOP_IMUX14_10", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX13_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_IMUX40_1", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_IMUX7_4", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_BYP7_2", - "CMT_PHASER_IN_D_ICLKDIV", - "CMT_TOP_SE4C1_0", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_TOP_IMUX15_4", - "CMT_PHY_CONTROL_PHYCTLREADY", - "CMT_TOP_IMUX0_9", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_IMUX23_3", - "CMT_TOP_WW2A2_3", - "CMT_TOP_SE4BEG1_1", - "CMT_PHY_CONTROL_IRANKA1", - "CMT_PHY_CONTROL_WRITECALIBENABLE", - "CMT_TOP_IMUX31_3", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4B3_11", - "CMT_TOP_IMUX25_8", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_TOP_EE2A3_11", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX12_9", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_TOP_EE2A1_10", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NW2A3_0", - "CMT_TOP_SW4A3_10", - "CMT_TOP_WL1END0_3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_WW2A3_5", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_WW2END1_3", - "CMT_TOP_SW2A2_5", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_IMUX28_11", - "CMT_TOP_IMUX42_11", - "CMT_TOP_WW2END2_10", - "CMT_TOP_EE4B3_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_LH10_3", - "CMT_TOP_IMUX47_9", - "CMT_TOP_LH10_1", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_IMUX17_1", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_BYP4_0", - "CMT_TOP_FAN2_9", - "CMT_TOP_SE4C3_8", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NE2A2_1", - "CMT_TOP_IMUX37_5", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX20_6", - "CMT_TOP_WW4C1_9", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_SE4C3_4", - "CMT_TOP_NE4C3_11", - "CMT_TOP_IMUX33_5", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_EE4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BYP5_4", - "CMT_PHY_CONTROL_PHYCTLWD11", - "CMT_TOP_LH10_9", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_NW4A1_10", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_IMUX25_9", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EE4B0_10", - "CMT_TOP_WW4END3_2", - "CMT_TOP_IMUX30_8", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX16_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_IMUX11_11", - "CMT_TOP_NW4END1_6", - "CMT_TOP_WW2A0_11", - "CMT_TOP_IMUX34_4", - "CMT_TOP_SW4END2_7", - "CMT_PHASER_REF_TESTIN3", - "CMT_TOP_LH12_0", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_SW4A3_11", - "CMT_TOP_NW4END2_8", - "CMT_TOP_IMUX36_0", - "CMT_TOP_FAN7_8", - "CMT_TOP_LH3_3", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_SE4C0_10", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX10_5", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_WW2A3_0", - "CMT_TOP_LH3_4", - "CMT_TOP_IMUX16_6", - "CMT_TOP_FAN2_11", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX40_4", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_IMUX38_0", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_WW4A1_10", - "CMT_PHY_CONTROL_PHYCTLWD12", - "CMT_TOP_NW4A3_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_9", - "CMT_TOP_LH8_5", - "CMT_TOP_EE4B2_10", - "CMT_TOP_WW2A2_5", - "CMT_TOP_IMUX29_0", - "CMT_TOP_EE4A0_8", - "CMT_TOP_OCLKDIV_4", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_TOP_IMUX16_7", - "CMT_TOP_NW4END0_2", - "CMT_TOP_FAN1_1", - "CMT_TOP_LH1_4", - "CMT_PHY_CONTROL_TESTOUTPUT3", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_TOP_SW2A2_9", - "CMT_TOP_IMUX45_9", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_SE4C0_7", - "CMT_PHY_CONTROL_PHYCTLWD23", - "CMT_PHY_CONTROL_TESTINPUT9", - "CMT_TOP_IMUX46_3", - "CMT_TOP_SW4END2_2", - "CMT_TOP_WW4B3_5", - "CMT_TOP_IMUX6_7", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_NW4A0_7", - "CMT_TOP_EE4A1_6", - "CMT_TOP_FAN2_0", - "CMT_PHY_CONTROL_TESTOUTPUT5", - "CMT_TOP_WW4A0_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX37_2", - "CMT_TOP_MONITOR_P_7", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_TOP_WW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_IMUX45_8", - "CMT_PHY_CONTROL_TESTINPUT7", - "CMT_TOP_FAN0_4", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SE4C0_3", - "CMT_TOP_IMUX29_6", - "CMT_TOP_EE2BEG2_6", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WW2END1_2", - "CMT_PHY_CONTROL_TESTOUTPUT7", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_TOP_SW4A1_6", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_FAN3_9", - "CMT_TOP_EE4A1_3", - "CMT_TOP_OCLK_11", - "CMT_TOP_WW2END2_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_WW4END3_9", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_TOP_IMUX26_1", - "CMT_TOP_CLK1_2", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_IMUX31_10", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_WL1END0_8", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_IMUX29_7", - "CMT_TOP_NE2A3_6", - "CMT_TOP_WW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_IMUX27_2", - "CMT_TOP_NE2A1_6", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_NW2A3_8", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_TOP_LH7_1", - "CMT_TOP_WW4END1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_IMUX13_2", - "CMT_TOP_WW4END2_7", - "CMT_TOP_NW4END1_0", - "CMT_TOP_EE4C0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_NE4C2_9", - "CMT_PHASERD_CTSBUS0", - "CMT_TOP_IMUX29_5", - "CMT_TOP_NW2A1_5", - "CMT_TOP_WW2END0_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX40_7", - "CMT_TOP_FAN7_10", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_BYP6_2", - "CMT_TOP_IMUX42_7", - "CMT_TOP_BYP5_5", - "CMT_TOP_WW2A3_10", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX2_1", - "CMT_TOP_FAN5_7", - "CMT_PHASER_REF_TESTIN7", - "CMT_TOP_SE2A2_6", - "CMT_TOP_EE4B1_8", - "CMT_TOP_IMUX12_11", - "CMT_TOP_NE2A3_4", - "CMT_TOP_SW4A3_7", - "CMT_TOP_WL1END2_11", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_IMUX24_9", - "CMT_TOP_LH1_10", - "CMT_TOP_SW4A1_9", - "CMT_PHY_CONTROL_TESTSELECT2", - "CMT_TOP_SW2A3_1", - "CMT_TOP_EE2A1_0", - "CMT_TOP_WW4C3_5", - "CMT_TOP_IMUX24_1", - "CMT_TOP_IMUX14_11", - "CMT_TOP_BYP1_0", - "CMT_TOP_WW4B0_8", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_TOP_WW4B0_7", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_NE2A1_2", - "CMT_TOP_BYP6_11", - "CMT_TOP_IMUX7_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_IMUX30_4", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_WW2END3_1", - "CMT_TOP_IMUX22_0", - "CMT_TOP_WW2A3_6", - "CMT_TOP_EE4A0_6", - "CMT_TOP_SE4C2_9", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_EE4A0_9", - "CMT_TOP_FAN6_7", - "CMT_TOP_WW4A0_10", - "CMT_TOP_LH5_9", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_TOP_ICLK_2", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_NW4END3_0", - "CMT_TOP_SW2A1_2", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_TOP_FAN1_5", - "CMT_TOP_CTRL0_7", - "CMT_TOP_NW4END3_7", - "CMT_TOP_WW2A0_9", - "CMT_TOP_SE4C1_9", - "CMT_TOP_IMUX44_2", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW2END0_3", - "CMT_TOP_LH10_2", - "CMT_TOP_NE4C2_2", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_TOP_IMUX9_6", - "CMT_TOP_NW4END3_3", - "CMT_TOP_IMUX45_2", - "CMT_TOP_SW4A2_11", - "CMT_TOP_FAN6_1", - "CMT_TOP_IMUX22_9", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "CMT_TOP_IMUX13_5", - "CMT_TOP_SW4A3_8", - "CMT_PHASER_IN_DB_RST", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_LH12_8", - "CMT_R_TOP_UPPER_B_CLKINT_2", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_IMUX31_11", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_WW4END0_1", - "CMT_TOP_EE4B0_6", - "CMT_TOP_BYP3_0", - "CMT_TOP_EE4B0_7", - "CMT_TOP_LH9_10", - "CMT_PHASER_REF_TESTOUT6", - "CMT_TOP_EE2A0_11", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_TOP_SW4END2_0", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_EE2A1_4", - "CMT_TOP_IMUX1_5", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX5_5", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_TOP_IMUX35_1", - "CMT_TOP_WW2END1_8", - "CMT_TOP_IMUX19_9", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_WW4A2_9", - "CMT_PHY_CONTROL_PHYCTLWD25", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_TOP_EE4B2_2", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_WW4C3_4", - "CMT_TOP_EE4BEG2_10", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_TOP_NE2A0_6", - "CMT_TOP_BYP1_5", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_IMUX11_10", - "CMT_TOP_FAN1_3", - "CMT_TOP_SE2A3_7", - "CMT_TOP_LH2_6", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_IMUX25_2", - "CMT_TOP_WR1END3_4", - "CMT_TOP_IMUX35_10", - "CMT_TOP_IMUX26_9", - "CMT_TOP_CTRL1_11", - "CMT_TOP_FAN0_3", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_WW4B3_10", - "CMT_TOP_NE2A2_8", - "CMT_TOP_FAN0_7", - "CMT_TOP_IMUX32_3", - "CMT_TOP_LH7_9", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_PHY_CONTROL_TESTINPUT13", - "CMT_TOP_CLK0_10", - "CMT_TOP_IMUX40_11", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WW4B1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_BYP6_5", - "CMT_TOP_WW2A0_10", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_IMUX39_2", - "CMT_TOP_SW4A1_11", - "CMT_TOP_WR1END3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_CTRL0_4", - "CMT_TOP_LH4_5", - "CMT_TOP_SW4END1_7", - "CMT_TOP_NW4END3_4", - "CMT_TOP_EE4C3_4", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_IMUX46_10", - "CMT_TOP_NW4A0_5", - "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "CMT_PHY_CONTROL_TESTOUTPUT12", - "CMT_TOP_SW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_TOP_IMUX2_11", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_PHY_CONTROL_TESTINPUT8", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_TOP_IMUX0_3", - "CMT_PHASER_IN_D_ICLK", - "CMT_TOP_OCLK_5", - "CMT_TOP_FAN5_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_WL1END0_2", - "CMT_TOP_BYP0_5", - "CMT_TOP_NW2A0_10", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_EE2BEG2_1", - "CMT_PHASER_C_OCLKDIV_TOIOI", - "CMT_TOP_IMUX35_4", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_EE2A2_7", - "CMT_TOP_SE2A2_2", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_IMUX9_4", - "CMT_TOP_SW4A2_1", - "CMT_TOP_WW4A3_11", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SW4END0_3", - "CMT_TOP_IMUX46_0", - "CMT_TOP_WW2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LH7_0", - "CMT_PHASER_REF_TESTOUT1", - "CMT_TOP_WW2A2_0", - "CMT_TOP_IMUX34_11", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_CTRL0_2", - "CMT_TOP_IMUX23_9", - "CMT_TOP_WL1END1_3", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_WW4A2_10", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_ER1BEG1_0", - "CMT_PHY_CONTROL_PHYCTLWD29", - "CMT_TOP_SW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_IMUX16_1", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_TOP_IMUX35_11", - "CMT_TOP_NE2A3_5", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_NW2A1_1", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP5_7", - "CMT_TOP_IMUX6_1", - "CMT_PHASER_REF_TESTOUT0", - "CMT_TOP_LH4_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SW2A3_7", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4END1_10", - "CMT_TOP_IMUX44_0", - "CMT_TOP_BYP7_11", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX28_1", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LH8_1", - "CMT_TOP_WW4A0_3", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_IMUX2_10", - "CMT_TOP_CLK1_0", - "CMT_TOP_IMUX27_4", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_7", - "CMT_TOP_IMUX40_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_NW2A0_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_NW4A1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_WW2A1_9", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_TOP_BYP1_11", - "CMT_TOP_SE4C2_7", - "CMT_TOP_EL1BEG0_4", - "CMT_R_TOP_UPPER_B_CLKINT_3", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_NE4C1_7", - "CMT_TOP_WW4B2_1", - "CMT_TOP_EE2BEG3_4", - "CMT_PHASERD_DQSBUS1", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_NE4C0_11", - "CMT_TOP_EE4BEG3_7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_TOP_WL1END2_8", - "CMT_TOP_SE2A3_2", - "CMT_TOP_LH8_3", - "CMT_TOP_IMUX13_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_IMUX30_7", - "CMT_TOP_WW4C3_2", - "CMT_PHY_CONTROL_MEMREFCLK", - "CMT_TOP_SW4END1_8", - "CMT_TOP_EE4B0_2", - "CMT_TOP_BYP6_10", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_LH5_1", - "CMT_TOP_EE4B2_11", - "CMT_TOP_BYP4_9", - "CMT_TOP_SE2A1_10", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_WR1END3_2", - "CMT_TOP_LH8_10", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_MONITOR_N_2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_TOP_IMUX34_7", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_PHASERREF_PHASEROUT_D", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_NW4A2_7", - "CMT_TOP_LH9_11", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EE2A2_1", - "CMT_TOP_FAN4_6", - "CMT_TOP_EE4B3_9", - "CMT_TOP_BYP3_11", - "CMT_TOP_WW4END1_1", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_FAN0_5", - "CMT_TOP_BYP0_11", - "CMT_TOP_NE4C0_5", - "CMT_TOP_SW2A0_8", - "CMT_TOP_NW2A2_2", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX0_10", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_WR1END1_11", - "CMT_PHASERTOP_PHYCTLEMPTY", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_BYP4_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_EE2A1_6", - "CMT_TOP_NE2A1_5", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2A3_3", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_FAN3_4", - "CMT_TOP_LH7_5", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX17_11", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_IMUX43_8", - "CMT_TOP_SE2A3_5", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4C1_6", - "CMT_TOP_WW4C0_2", - "CMT_TOP_LH12_7", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_EE2A1_9", - "CMT_TOP_WW2END2_5", - "CMT_TOP_IMUX0_6", - "CMT_PHY_CONTROL_AUXOUTPUT2", - "CMT_TOP_BYP4_5", - "CMT_TOP_IMUX22_3", - "CMT_TOP_NE2A2_6", - "CMT_PHY_CONTROL_TESTOUTPUT14", - "CMT_TOP_EE4A0_7", - "CMT_TOP_FAN5_10", - "CMT_TOP_WW2END1_10", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_IMUX38_11", - "CMT_TOP_WW2END2_11", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WW4B2_5", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_NE2A2_9", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_IMUX2_8", - "CMT_TOP_WW2END3_2", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WW2A2_10", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_IMUX28_2", - "CMT_PHY_CONTROL_TESTOUTPUT4", - "CMT_TOP_WW4C1_4", - "CMT_TOP_EE4C2_7", - "CMT_TOP_LH12_1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_TOP_NE2A0_3", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE4C0_4", - "CMT_PHY_CONTROL_TESTSELECT1", - "CMT_TOP_LH11_0", - "CMT_TOP_WW2A1_2", - "CMT_TOP_FAN6_2", - "CMT_TOP_IMUX22_7", - "CMT_TOP_WW2END3_4", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SW4A1_0", - "CMT_TOP_IMUX1_8", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_TOP_WW4C2_4", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_2", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_IMUX20_11", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4END3_10", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_TOP_CLK0_2", - "CMT_TOP_IMUX11_2", - "CMT_TOP_WW2END0_5", - "CMT_TOP_SE4BEG1_0", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_WW4B1_1", - "CMT_TOP_LH6_7", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE4B2_8", - "CMT_TOP_WW4A3_6", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_OUT_DB_DIVIDERST", - "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "CMT_TOP_BYP5_11", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_EE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CLK1_3", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_IMUX34_0", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_IMUX30_11", - "CMT_TOP_SE2A3_8", - "CMT_PHASER_C_OCLK90_TOIOI", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX30_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_FAN7_3", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_TOP_IMUX33_6", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_NW4END1_9", - "CMT_TOP_WW4END2_10", - "CMT_TOP_SW4END0_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_WW4END1_6", - "CMT_TOP_IMUX16_10", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_WR1END3_1", - "CMT_TOP_IMUX26_11", - "CMT_TOP_NE2A0_0", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX28_6", - "CMT_TOP_SE4C2_11", - "CMT_TOP_EE4A2_2", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX24_0", - "CMT_TOP_NW4END2_4", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW4C3_3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_TOP_SE4BEG3_3", - "CMT_PHASER_OUT_C_OCLKDIV", - "CMT_TOP_EE4C3_5", - "CMT_TOP_SE2A0_8", - "CMT_TOP_IMUX0_2", - "CMT_TOP_EE4C0_5", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX36_4", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_WR1END1_4", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_TOP_SW4END0_11", - "CMT_TOP_LH5_8", - "CMT_TOP_IMUX21_0", - "CMT_TOP_LH8_9", - "CMT_TOP_WL1END0_7", - "CMT_TOP_SW2A0_6", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_WW4END3_6", - "CMT_TOP_IMUX7_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_EE2A1_5", - "CMT_TOP_NW2A0_8", - "CMT_TOP_IMUX21_10", - "CMT_TOP_SW2A2_6", - "CMT_TOP_IMUX26_0", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_IMUX23_1", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_BYP0_0", - "CMT_TOP_SW4END0_7", - "CMT_TOP_IMUX41_8", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_TOP_BYP3_4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_TOP_WW4C2_1", - "CMT_TOP_BYP1_3", - "CMT_TOP_IMUX8_0", - "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_IMUX43_3", - "CMT_TOP_NW4A2_8", - "CMT_PHY_CONTROL_PHYCTLWD2", - "CMT_TOP_WR1END3_6", - "CMT_TOP_ICLK_5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_TOP_WW2END2_4", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_IMUX18_11", - "CMT_TOP_NW4A2_9", - "CMT_TOP_WW4END0_0", - "CMT_R_TOP_UPPER_B_CLKPLL7", - "CMT_TOP_NW4END0_11", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_WW4C2_11", - "CMT_TOP_IMUX18_5", - "CMT_TOP_SE2A1_7", - "CMT_PHASER_REF_TESTIN0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_TOP_SW2A1_1", - "CMT_TOP_BYP3_10", - "CMT_PHASER_UP_DQS_TO_PHASER_D", - "CMT_PHY_CONTROL_AUXOUTPUT3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX20_5", - "CMT_TOP_NW2A2_3", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_TOP_IMUX24_8", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LH3_5", - "CMT_TOP_IMUX26_2", - "CMT_TOP_WW4A0_11", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_PHY_CONTROL_PHYCTLWD17", - "CMT_TOP_IMUX19_8", - "CMT_PHY_CONTROL_PHYCTLWD6", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_SE2A1_3", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_TOP_BYP4_11", - "CMT_TOP_NW4A3_10", - "CMT_TOP_FAN1_7", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_WW4A2_0", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_TOP_IMUX28_10", - "CMT_TOP_NE4C1_10", - "CMT_TOP_WW2A3_9", - "CMT_PHY_CONTROL_INRANKD1", - "CMT_TOP_EE4A1_4", - "CMT_TOP_IMUX16_4", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_IMUX46_5", - "CMT_TOP_NE2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_WR1END2_8", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX26_7", - "CMT_PHASER_REF_TESTIN2", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_NW4END2_10", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2A3_6", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_FAN3_8", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_NW4END0_1", - "CMT_TOP_OCLK1X_90_9", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_FAN3_6", - "CMT_TOP_EE2A3_10", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_SW4END3_1", - "CMT_TOP_IMUX22_11", - "CMT_TOP_WW4A2_7", - "CMT_TOP_NW4A2_1", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW4C3_8", - "CMT_TOP_NE2A0_8", - "CMT_TOP_IMUX12_10", - "CMT_TOP_WW4C3_9", - "CMT_TOP_NE2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_FAN5_9", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_FAN3_0", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_3", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_TOP_SW2A0_7", - "CMT_TOP_IMUX3_1", - "CMT_TOP_NE4C0_1", - "CMT_TOP_WL1END3_4", - "CMT_TOP_IMUX37_9", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_NW4END3_5", - "CMT_TOP_WW2A2_7", - "CMT_TOP_FAN2_5", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WL1END3_0", - "CMT_PHASER_IN_DB_ICLK", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_IMUX36_1", - "CMT_TOP_SW2A1_9", - "CMT_TOP_EE4A3_2", - "CMT_TOP_IMUX15_10", - "CMT_TOP_IMUX27_6", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LH3_6", - "CMT_TOP_WW2END2_0", - "CMT_TOP_IMUX11_7", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_TOP_IMUX43_2", - "CMT_TOP_NE4C3_9", - "CMT_TOP_WW2END2_9", - "CMT_PHASER_REF_TESTIN6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_TOP_WW4C1_6", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4B2_9", - "CMT_TOP_IMUX4_5", - "CMT_TOP_EE4C0_9", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_CA_TESTIN4", - "CMT_TOP_ER1BEG3_3", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_WR1END2_10", - "CMT_TOP_NE4C1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_WW2A0_8", - "CMT_TOP_SE4C2_8", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_TOP_IMUX38_8", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_LH1_3", - "CMT_TOP_BYP1_2", - "CMT_TOP_IMUX26_5", - "CMT_TOP_SE4C3_10", - "CMT_TOP_EE2BEG0_11", - "CMT_PHY_CONTROL_TESTOUTPUT6", - "CMT_TOP_NE4C0_10", - "CMT_TOP_ICLKDIV_6", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_PHY_CONTROL_OBURSTPENDING1", - "CMT_TOP_IMUX12_3", - "CMT_PHY_CONTROL_INRANKA0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_IMUX38_6", - "CMT_TOP_LH6_10", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_WW4B3_4", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_IMUX1_10", - "CMT_TOP_WW2END0_9", - "CMT_PHY_CONTROL_PHYCTLFULL", - "CMT_TOP_SE2A0_9", - "CMT_TOP_IMUX8_9", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_TOP_IMUX36_7", - "CMT_PHY_CONTROL_OBURSTPENDING3", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_IMUX39_8", - "CMT_TOP_WW4B0_5", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_BYP4_7", - "CMT_TOP_IMUX43_9", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_NE4BEG3_2", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_TOP_WW2END3_10", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_SW2A0_5", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_SW4END1_9", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_PHASER_UP_PHASERREF_ABOVE0", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_TOP_FAN0_2", - "CMT_TOP_IMUX19_1", - "CMT_TOP_NW2A3_11", - "CMT_TOP_IMUX41_0", - "CMT_TOP_FAN3_2", - "PLL_CLK_FREQBB_REBUFOUT3", - "CMT_TOP_WW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_SW2A3_6", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_TOP_WW2A1_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SE2A1_11", - "CMT_TOP_WW4A0_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_EE4B0_0", - "CMT_TOP_NW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_NW2A3_3", - "CMT_TOP_SE4C0_8", - "CMT_PHY_CONTROL_PHYCTLWD13", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4END2_3", - "CMT_TOP_NE2A3_10", - "CMT_TOP_LH1_5", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_WW4B2_10", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_TOP_SW4END2_1", - "CMT_TOP_EE4B3_4", - "CMT_TOP_SW4END1_3", - "CMT_TOP_IMUX25_6", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LH9_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX37_3", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_LH1_9", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EL1BEG1_10", - "CMT_PHY_CONTROL_PHYCTLWD21", - "CMT_TOP_IMUX36_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_WW4A3_3", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_TOP_LH2_8", - "CMT_TOP_IMUX17_8", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_TOP_IMUX29_8", - "CMT_PHY_CONTROL_TESTOUTPUT1", - "CMT_TOP_IMUX34_10", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_WW4A3_2", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_TOP_EE4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_NE2A2_11", - "CMT_TOP_LH3_1", - "CMT_TOP_SW4A3_5", - "CMT_PHY_CONTROL_IBURSTPENDING1", - "CMT_TOP_EL1BEG3_7", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_TOP_WW4END1_5", - "CMT_TOP_IMUX45_10", - "CMT_PHY_CONTROL_PHYCTLWD8", - "CMT_PHY_CONTROL_REFDLLLOCK", - "CMT_TOP_IMUX25_3", - "CMT_PHY_CONTROL_PHYCTLWD7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_NW4END2_11", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_EE2BEG1_5", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX5_10", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_WW2A3_3", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_TOP_EE4A2_3", - "CMT_TOP_SW4A1_1", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_8", - "CMT_TOP_WW4A1_6", - "CMT_PHY_CONTROL_OBURSTPENDING0", - "CMT_TOP_IMUX41_2", - "CMT_TOP_LH8_6", - "CMT_TOP_SE4C1_8", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WW4A2_6", - "CMT_TOP_BYP0_6", - "CMT_TOP_IMUX43_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_IMUX31_0", - "CMT_TOP_WR1END2_1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_TOP_NW4END3_11", - "CMT_TOP_WR1END3_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_PHASER_OUT_D_OCLK", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_NW4A0_4", - "CMT_TOP_IMUX24_4", - "CMT_TOP_EE4C1_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WW4C1_8", - "CMT_TOP_NW2A0_7", - "CMT_TOP_IMUX22_1", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_TOP_LH1_11", - "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "CMT_TOP_IMUX17_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_IMUX19_11", - "CMT_PHY_CONTROL_PHYCTLWD26", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX10_9", - "CMT_TOP_EE2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_TOP_CLK1_4", - "CMT_TOP_LH2_2", - "CMT_TOP_NE4BEG2_7", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_TOP_NE4C2_3", - "CMT_TOP_EE4A2_7", - "CMT_TOP_IMUX11_0", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_ER1BEG1_1", - "CMT_PHASER_IN_C_RCLK2", - "CMT_TOP_IMUX38_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_10", - "CMT_TOP_LH3_9", - "CMT_TOP_IMUX6_10", - "CMT_TOP_IMUX5_9", - "CMT_TOP_NW4END2_2", - "CMT_TOP_WW2A2_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_LH4_9", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4B0_6", - "CMT_TOP_BYP1_9", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_NW4A1_5", - "CMT_TOP_SE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_SW4END3_10", - "CMT_TOP_IMUX9_1", - "CMT_TOP_NW4A1_9", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_BYP7_8", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX4_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_IMUX30_1", - "CMT_TOP_WW4C0_5", - "CMT_TOP_NW4A1_2", - "CMT_R_TOP_UPPER_B_CLKPLL6", - "CMT_TOP_WW2END0_2", - "CMT_TOP_FAN0_0", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX18_8", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX20_4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_TOP_EE4C3_6", - "CMT_PHY_CONTROL_PHYCTLWD31", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_IMUX39_11", - "CMT_PHASER_OUT_D_OCLK1X_90", - "CMT_PHY_CONTROL_TESTINPUT0", - "CMT_PHASER_REF_LOCKED", - "CMT_TOP_NE4C0_2", - "CMT_TOP_EE4B1_2", - "CMT_TOP_IMUX4_9", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SE4C1_1", - "CMT_TOP_EE4A1_9", - "CMT_TOP_IMUX30_2", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_EE2A2_2", - "CMT_TOP_WW4A2_8", - "CMT_TOP_MONITOR_P_2", - "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "CMT_TOP_IMUX23_8", - "CMT_TOP_SW4END0_6", - "CMT_TOP_IMUX12_2", - "CMT_TOP_NW2A2_7", - "CMT_TOP_WL1END2_7", - "CMT_TOP_BYP5_1", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_TOP_EE4B1_9", - "CMT_TOP_IMUX33_0", - "CMT_TOP_WW2A2_9", - "CMT_TOP_EL1BEG2_4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_UP_BUFMRCE_CE1", - "CMT_TOP_OCLK_7", - "CMT_TOP_FAN1_10", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_SW2A1_10", - "CMT_TOP_IMUX19_7", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_SE4C0_6", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_IMUX3_0", - "CMT_TOP_WL1END1_8", - "CMT_TOP_NW4END1_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_LH6_2", - "CMT_TOP_IMUX39_6", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_IMUX36_2", - "CMT_PHY_CONTROL_RESET", - "CMT_TOP_WW2A0_5", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_BYP2_0", - "CMT_TOP_IMUX8_3", - "CMT_TOP_ICLK_6", - "CMT_TOP_LH2_0", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHY_CONTROL_INRANKD0", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_TOP_IMUX16_3", - "CMT_PHY_CONTROL_TESTINPUT10", - "CMT_TOP_IMUX40_2", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_WW4END3_1", - "CMT_TOP_SW4A2_4", - "CMT_TOP_LH11_11", - "CMT_TOP_IMUX46_2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NW4A3_2", - "CMT_TOP_IMUX17_10", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX19_2", - "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW4END1_3", - "CMT_TOP_NW2A3_7", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_NW4A3_8", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SE2A0_11", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_WW2END0_7", - "CMT_TOP_EE4C0_6", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_EE4C0_7", - "CMT_TOP_WL1END0_0", - "CMT_TOP_FAN7_2", - "CMT_TOP_WL1END3_1", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_LH8_4", - "CMT_TOP_LH5_6", - "CMT_TOP_BYP2_11", - "CMT_TOP_SW4A0_6", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_BYP7_4", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_TOP_LH10_6", - "CMT_TOP_SE4C2_4", - "CMT_TOP_IMUX35_9", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_IMUX46_4", - "CMT_TOP_LH4_2", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_TESTOUT1", - "CMT_TOP_IMUX44_3", - "CMT_TOP_EE4A3_8", - "CMT_TOP_IMUX24_2", - "CMT_TOP_EE4A3_11", - "CMT_TOP_IMUX14_5", - "CMT_PHASER_IN_DB_STG1REGR1", - "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "CMT_TOP_IMUX34_5", - "CMT_TOP_NW4END2_9", - "CMT_TOP_IMUX20_9", - "CMT_TOP_IMUX29_1", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_SW4A2_3", - "CMT_TOP_FAN1_9", - "CMT_TOP_BYP7_1", - "CMT_TOP_WW2A3_11", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_TOP_WL1END3_8", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX19_6", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX17_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_OCLK_0", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX13_11", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_TOP_WL1END1_11", - "CMT_TOP_IMUX2_2", - "CMT_TOP_WW4END3_5", - "CMT_TOP_LH1_1", - "CMT_TOP_FAN5_8", - "CMT_TOP_NW4END3_8", - "CMT_TOP_WW4A1_1", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_TOP_NE4BEG3_1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_TOP_EE2A3_2", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_WW2END2_3", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_WW2END2_6", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_TOP_IMUX41_10", - "CMT_TOP_EE4B2_1", - "CMT_TOP_NW4END3_1", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_LH3_0", - "CMT_TOP_LH2_5", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_EE4A3_3", - "CMT_TOP_NW4A2_3", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_SW4END3_0", - "CMT_TOP_IMUX34_8", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_TOP_SW4A2_10", - "CMT_TOP_NW2A3_1", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX32_11", - "CMT_TOP_WW4B3_7", - "CMT_TOP_LH11_9", - "CMT_TOP_NE2A2_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_NW4A2_0", - "CMT_TOP_WW4C2_10", - "CMT_TOP_BYP7_0", - "CMT_TOP_LH6_0", - "CMT_TOP_NE4C1_4", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_TOP_IMUX16_9", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_PHASER_REF_TESTOUT4", - "CMT_TOP_EE4A0_10", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_IMUX5_2", - "CMT_TOP_WW4C0_10", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "CMT_TOP_FAN1_2", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_NE4BEG2_2", - "CMT_PHY_CONTROL_TESTINPUT4", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_WW4B2_6", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_IMUX29_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LH3_11", - "CMT_TOP_IMUX32_7", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_BYP2_3", - "CMT_TOP_IMUX1_6", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_TOP_WR1END2_4", - "CMT_PHY_CONTROL_TESTOUTPUT2", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX20_3", - "CMT_TOP_LH7_3", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX28_8", - "CMT_TOP_NW4END2_5", - "CMT_TOP_WW2A0_3", - "CMT_PHASERD_DQSBUS0", - "CMT_TOP_IMUX33_9", - "CMT_TOP_WR1END1_9", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX23_11", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_TOP_SW4END2_4", - "CMT_TOP_FAN6_0", - "CMT_TOP_LH6_11", - "CMT_PHY_CONTROL_TESTOUTPUT13", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_IMUX4_3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_TOP_SW4END3_3", - "CMT_TOP_WW4B0_3", - "CMT_TOP_BYP3_2", - "CMT_TOP_CTRL0_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_CLK1_8", - "CMT_TOP_FAN3_3", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_IMUX42_0", - "CMT_TOP_LH12_4", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_TOP_SW2A0_9", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_TOP_FAN0_6", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_R_TOP_UPPER_B_CLKIN2", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_R_TOP_UPPER_B_CLKPLL5", - "CMT_TOP_SW4END0_1", - "CMT_TOP_FAN5_11", - "CMT_TOP_IMUX1_0", - "CMT_TOP_NW2A3_4", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_WW4END1_9", - "CMT_TOP_EE2A2_4", - "CMT_TOP_WL1END0_4", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_IMUX4_10", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_OCLK1X_90_0", - "CMT_PHASER_REF_TESTIN4", - "CMT_TOP_SW4END3_4", - "CMT_TOP_WW4C3_1", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_WL1END0_6", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_TOP_EE4A0_3", - "CMT_TOP_NW4A3_6", - "CMT_TOP_BYP2_5", - "CMT_TOP_ICLK_0", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_PHY_CONTROL_TESTINPUT6", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LH6_9", - "CMT_TOP_CTRL1_9", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_IMUX33_4", - "CMT_TOP_NW2A1_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_EE4B0_4", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_IMUX1_11", - "CMT_TOP_WR1END0_6", - "CMT_TOP_LH12_2", - "CMT_TOP_FAN5_5", - "CMT_TOP_IMUX4_8", - "CMT_TOP_SW2A2_7", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_TOP_IMUX43_6", - "CMT_PHASER_IN_DB_TESTIN7", - "PLL_CLK_FREQBB_REBUFOUT1", - "CMT_TOP_WW4A3_7", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_WL1END1_10", - "CMT_TOP_BYP6_3", - "CMT_TOP_FAN2_6", - "CMT_TOP_IMUX31_9", - "CMT_TOP_OCLK_3", - "CMT_TOP_WR1END1_1", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_IMUX30_0", - "CMT_TOP_EE4C2_8", - "CMT_TOP_OCLK_8", - "CMT_PHASER_REF_TESTIN1", - "CMT_TOP_FAN4_3", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_LH4_4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4C3_11", - "CMT_TOP_FAN4_8", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_TOP_NE4C2_0", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_IMUX33_1", - "CMT_TOP_EE4C1_5", - "CMT_TOP_WW4B3_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH6_8", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_TOP_NW4A1_11", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_WL1END0_1", - "CMT_TOP_NE2A3_3", - "CMT_TOP_IMUX12_8", - "CMT_TOP_EE4A1_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_WW4A1_11", - "CMT_TOP_IMUX46_9", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE4C2_6", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX18_1", - "CMT_TOP_EL1BEG3_3", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_NW4END1_10", - "CMT_TOP_IMUX20_8", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NE2A3_2", - "CMT_TOP_SE2A0_6", - "CMT_TOP_IMUX30_3", - "CMT_TOP_LH7_10", - "CMT_TOP_OCLK_6", - "CMT_PHY_CONTROL_PHYCTLWD9", - "CMT_TOP_SW4END0_9", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_IMUX4_2", - "CMT_PHY_CONTROL_PHYCTLWD1", - "CMT_TOP_IMUX37_6", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_PHASER_IN_D_WRENABLE_FIFO", - "CMT_TOP_NE4BEG1_6", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_TOP_WW4B2_3", - "CMT_PHY_CONTROL_PHYCTLWD20", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_TOP_WW4C2_5", - "CMT_TOP_EE4B2_5", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WW4A1_5", - "CMT_TOP_BYP3_7", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_FAN2_1", - "CMT_TOP_IMUX36_11", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_IMUX44_6", - "CMT_TOP_OCLK_1", - "CMT_TOP_NW2A0_9", - "CMT_TOP_IMUX36_9", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_WW4END2_2", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_TOP_LH12_9", - "CMT_PHASERD_CTSBUS1", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_NE2A2_10", - "CMT_TOP_SW4END2_9", - "CMT_TOP_LH4_7", - "CMT_TOP_EE2A2_3", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_IMUX6_0", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_PHY_CONTROL_PHYCTLWD27", - "CMT_TOP_NE2A0_9", - "CMT_TOP_WW4B3_3", - "CMT_TOP_BYP4_6", - "CMT_TOP_FAN3_10", - "CMT_TOP_BYP6_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_NE2A1_1", - "CMT_TOP_WW4END1_8", - "CMT_TOP_SW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_CTRL0_3", - "CMT_TOP_WW4B3_1", - "CMT_TOP_NW4A2_4", - "CMT_TOP_LH4_11", - "CMT_PHY_CONTROL_PLLLOCK", - "CMT_R_TOP_UPPER_B_CLKIN1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_SE4C3_3", - "CMT_TOP_WW2END1_9", - "CMT_PHASER_OUT_C_OCLK", - "CMT_TOP_NE4C3_1", - "CMT_TOP_WW2A1_3", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_TOP_WL1END3_9", - "CMT_TOP_SE4C0_4", - "CMT_TOP_IMUX9_10", - "CMT_TOP_EE4C3_0", - "CMT_TOP_WW4C1_3", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_EE4A1_11", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_TOP_NW2A2_10", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_TOP_CTRL1_8", - "CMT_TOP_WL1END1_1", - "CMT_TOP_OCLKDIV_5", - "CMT_PHY_CONTROL_INBURSTPENDING2", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_PHY_CONTROL_TESTINPUT15", - "CMT_TOP_NW2A1_11", - "CMT_TOP_EE4B2_0", - "CMT_TOP_LH5_7", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX2_5", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_CLK0_1", - "CMT_PHY_CONTROL_TESTINPUT2", - "CMT_TOP_IMUX6_4", - "CMT_TOP_NW4A2_11", - "CMT_TOP_EE2A2_8", - "CMT_TOP_SE4C3_7", - "CMT_TOP_WW4C0_7", - "CMT_TOP_EL1BEG2_0", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_TOP_SE4C2_5", - "CMT_TOP_IMUX32_0", - "CMT_TOP_SW2A3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_NE4BEG0_10", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_TOP_WW2END3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_EE4B1_4", - "CMT_PHASER_REF_CLKOUT", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX27_5", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_EE4C0_0", - "CMT_TOP_SE4BEG3_6", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_WW4B0_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_WW4END3_11", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_EE4B1_3", - "CMT_TOP_NW4END3_2", - "CMT_TOP_IMUX21_1", - "CMT_PHASER_OUT_D_RDCLK_TOFIFO", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_TOP_SW4END0_0", - "CMT_TOP_WW4A1_2", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW4C0_3", - "CMT_PHASER_IN_CA_RCLK", - "CMT_TOP_BYP7_10", - "CMT_TOP_IMUX6_9", - "CMT_TOP_WW4A0_1", - "CMT_TOP_EE4B1_11", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_SE4BEG2_10", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_TOP_NW4A0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NE4C3_4", - "CMT_TOP_BYP6_9", - "CMT_PHY_CONTROL_SCANENABLEN", - "CMT_PHASER_REF_TESTOUT2", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX21_4", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX29_10", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW2A0_2", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_TOP_BYP2_8", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW4C0_0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_TOP_BYP6_8", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_TOP_IMUX28_0", - "CMT_TOP_EE4A2_0", - "CMT_TOP_SW2A2_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_NE4BEG2_6", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_TOP_LH12_10", - "CMT_R_TOP_UPPER_B_CLKPLL4", - "CMT_PHASER_REF_TESTOUT3", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW4END1_10", - "CMT_TOP_NW4END0_5", - "CMT_TOP_IMUX3_10", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_WW4C1_11", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_SW4END3_8", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END3_6", - "CMT_PHASER_C_ICLKDIV_TOIOI", - "CMT_PHASER_OUT_C_OCLK1X_90", - "CMT_TOP_IMUX14_4", - "CMT_TOP_LH6_5", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_FREQ_BB_PREF_IN0", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WW2A1_10", - "CMT_TOP_SW4A2_7", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX39_7", - "CMT_PHY_CONTROL_PHYCTLEMPTY", - "CMT_PHY_CONTROL_IRANKB0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_IMUX0_11", - "CMT_TOP_FAN4_0", - "CMT_TOP_IMUX41_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_WW4A3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_LH6_1", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WL1END2_9", - "CMT_TOP_BYP4_10", - "CMT_TOP_IMUX11_4", - "CMT_TOP_WL1END3_10", - "CMT_TOP_NE4C3_0", - "CMT_TOP_WW4END1_0", - "CMT_TOP_FAN7_5", - "CMT_TOP_SE4C0_9", - "CMT_TOP_BYP0_8", - "CMT_PHASER_C_OCLK_TOIOI", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_IMUX22_2", - "CMT_TOP_FAN4_5", - "CMT_PHASER_REF_RST", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_TOP_EE4B2_6", - "CMT_TOP_SW4A1_3", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW2A2_11", - "CMT_TOP_IMUX19_3", - "CMT_TOP_EE4A1_8", - "CMT_TOP_WW4B1_2", - "CMT_TOP_IMUX9_9", - "CMT_TOP_ER1BEG3_7", - "CMT_PHASER_OUT_D_RDENABLE_TOFIFO", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LH9_9", - "CMT_TOP_ICLKDIV_11", - "CMT_PHY_CONTROL_INBURSTPENDING0", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_WW4B3_9", - "CMT_FREQ_BB_PREF_IN3", - "CMT_TOP_NE4C3_10", - "CMT_TOP_FAN5_6", - "CMT_TOP_IMUX30_6", - "CMT_TOP_IMUX23_5", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_FAN0_10", - "CMT_TOP_IMUX40_10", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_TOP_LH2_3", - "CMT_TOP_EE4C3_8", - "CMT_TOP_SW4END2_3", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_TOP_EE2A0_9", - "CMT_TOP_WW4A1_3", - "CMT_TOP_BYP5_10", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_WR1END0_4", - "CMT_TOP_NW2A0_2", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_SE4C3_0", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_SE2A1_5", - "CMT_TOP_FAN0_11", - "CMT_TOP_WL1END3_11", - "CMT_TOP_FAN6_5", - "CMT_TOP_EE4A2_4", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_WR1END0_7", - "CMT_TOP_EE4A3_7", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_WR1END1_0", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_IMUX32_1", - "CMT_TOP_EE4C1_6", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_TOP_EE4C1_1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_TOP_IMUX20_2", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_NW4END1_11", - "CMT_TOP_FAN0_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_WW2END1_11", - "CMT_TOP_FAN0_9", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NW4A0_0", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_PHASER_UP_PHASERREF0", - "CMT_PHY_CONTROL_TESTSELECT0", - "CMT_TOP_BYP1_8", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EE4B2_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_EE4B3_2", - "CMT_TOP_SE4C1_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_IMUX36_3", - "CMT_TOP_SE4C2_3", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_TOP_NW4END0_3", - "CMT_TOP_IMUX10_1", - "CMT_TOP_FAN4_9", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX27_8", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_6", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WR1END3_11", - "CMT_TOP_EE4A3_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_BYP3_6", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE2A1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_BYP2_10", - "CMT_TOP_IMUX27_11", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_TOP_SE2A2_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_SE4C3_6", - "CMT_TOP_NE4C3_3", - "CMT_TOP_WR1END2_9", - "CMT_TOP_CTRL0_6", - "CMT_TOP_FAN2_2", - "CMT_TOP_NW4END1_2", - "CMT_TOP_IMUX18_7", - "CMT_TOP_OCLK_10", - "CMT_PHY_CONTROL_INRANKA1", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LH2_11", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_PHY_CONTROL_PCENABLECALIB0", - "CMT_TOP_NW4A1_0", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_FREQ_PHASER_REFMUX_2", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_TOP_WR1END0_8", - "CMT_PHY_CONTROL_PHYCTLWD24", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4END3_3", - "CMT_TOP_BYP7_9", - "CMT_TOP_SW4END1_6", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_EE4C0_8", - "CMT_TOP_SE4C0_1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_TOP_EE2A0_1", - "CMT_TOP_NW2A1_8", - "CMT_TOP_LH9_4", - "CMT_TOP_SW4END1_1", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LH10_8", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WW2END3_3", - "CMT_TOP_CLK1_7", - "CMT_TOP_FAN1_6", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_TOP_SE4C1_2", - "CMT_TOP_NW2A2_6", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A2_1", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX46_8", - "CMT_TOP_EE4B1_7", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_EE4B0_5", - "CMT_TOP_NW2A0_3", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_PHASERTOP_PHYCTLMSTREMPTY", - "CMT_TOP_WW4B2_7", - "CMT_PHY_CONTROL_SYNCIN", - "CMT_TOP_LH10_11", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_IMUX6_2", - "CMT_TOP_NE4C2_6", - "CMT_TOP_WW4END2_9", - "CMT_TOP_IMUX13_10", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_WW2END3_11", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_EE2BEG0_8", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_TOP_LH8_8", - "CMT_TOP_SW2A2_0", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_TOP_SW4A2_2", - "CMT_PHY_CONTROL_READCALIBENABLE", - "CMT_TOP_WW2A1_6", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_PHY_CONTROL_INBURSTPENDING3", - "CMT_TOP_IMUX3_8", - "CMT_PHASER_IN_CA_ICLK", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_SW2A0_11", - "CMT_PHY_CONTROL_OBURSTPENDING2", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_TOP_FAN6_9", - "CMT_TOP_SE4C1_3", - "CMT_TOP_WL1END2_6", - "CMT_TOP_LH11_2", - "CMT_TOP_WW4C0_9", - "CMT_TOP_ICLKDIV_10", - "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX37_4", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_TOP_IMUX46_11", - "CMT_TOP_SE2A0_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_NE4C1_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_EL1BEG1_4", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX0_4", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_IMUX15_3", - "CMT_PHY_CONTROL_PHYCTLWD30", - "CMT_TOP_IMUX39_4", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_ER1BEG2_6", - "CMT_PHASER_IN_D_RCLK3", - "CMT_TOP_IMUX40_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW2A1_7", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_9", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_SE2A2_5", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_SW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LH2_4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_TOP_EL1BEG3_5", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_TOP_WW4END0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_SE2A3_9", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX7_10", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4END3_4", - "CMT_TOP_SE2A3_10", - "CMT_TOP_WW2A3_7", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4END2_6", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_NE2A1_11", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHY_CONTROL_IRANKC0", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_NW2A0_11", - "CMT_TOP_IMUX42_2", - "CMT_TOP_LH8_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_EE4A0_5", - "CMT_TOP_WL1END2_3", - "CMT_TOP_SE2A1_8", - "CMT_PHY_CONTROL_TESTOUTPUT9", - "CMT_TOP_NE4C1_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_NW2A0_6", - "CMT_TOP_WW4A3_8", - "CMT_TOP_SW2A1_3", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_TOP_IMUX40_5", - "CMT_TOP_SE2A1_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_CTRL1_5", - "CMT_TOP_SE4C3_1", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX18_3", - "CMT_TOP_EE2A1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_IMUX16_5", - "CMT_TOP_LH9_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_EE2A1_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_WL1END3_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_IMUX47_3", - "CMT_TOP_NE2A2_7", - "CMT_TOP_WW4B1_5", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_TOP_SE4C3_9", - "CMT_TOP_WR1END1_6", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_EE2A2_0", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_LH9_7", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW2END3_5", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CLK1_9", - "CMT_TOP_IMUX5_11", - "CMT_TOP_WR1END2_6", - "CMT_TOP_CTRL1_2", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_IMUX10_11", - "CMT_TOP_LH6_6", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_EE2A3_1", - "CMT_TOP_IMUX2_0", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE4B3_5", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX38_2", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_FAN4_10", - "CMT_TOP_CLK0_5", - "CMT_TOP_SW4A3_0", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_OCLK_4", - "CMT_TOP_LH12_6", - "CMT_TOP_IMUX4_6", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_WR1END2_3", - "CMT_PHASER_REF_CLKIN", - "CMT_PHASER_REF_CLKOUT_TOHCLK", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX4_11", - "CMT_TOP_NW2A2_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_SE4C1_4", - "CMT_TOP_WW4C0_4", - "CMT_TOP_IMUX6_8", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_WW4A2_4", - "CMT_TOP_IMUX7_1", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SW4A3_9", - "CMT_TOP_IMUX20_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_IMUX35_7", - "CMT_TOP_EE4A3_5", - "CMT_TOP_LH6_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_ICLK_8", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_NW2A3_9", - "CMT_TOP_CLK0_8", - "CMT_TOP_IMUX7_2", - "CMT_TOP_SE2A2_11", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_TOP_FAN4_2", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_LH12_3", - "CMT_TOP_WW2A1_8", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_TOP_LH8_2", - "CMT_TOP_EE2BEG3_7", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_IMUX23_7", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_IMUX39_0", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX33_8", - "CMT_TOP_SW2A2_2", - "CMT_TOP_LH10_0", - "CMT_R_TOP_UPPER_B_CLKPLL0", - "CMT_TOP_LH6_3", - "CMT_TOP_EE2A0_0", - "CMT_TOP_IMUX12_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_IMUX21_8", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_TOP_IMUX5_1", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_IMUX10_2", - "CMT_TOP_FAN2_10", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_LH12_11", - "CMT_PHY_CONTROL_PCENABLECALIB1", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_TOP_IMUX36_10", - "CMT_PHY_CONTROL_IRANKB1", - "CMT_TOP_LH4_1", - "CMT_TOP_NE4C2_11", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_TOP_IMUX3_3", - "CMT_TOP_BYP1_1", - "CMT_TOP_NE4BEG3_5", - "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_SW4END1_5", - "CMT_TOP_FAN7_0", - "CMT_TOP_NW2A3_10", - "CMT_TOP_LH1_7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_WW4A0_4", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW2A1_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_WW4C2_0", - "CMT_TOP_SE2A3_3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_TOP_WL1END2_4", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_IMUX9_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LH5_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_IMUX22_5", - "CMT_TOP_NE4C1_0", - "CMT_TOP_ER1BEG1_10", - "CMT_PHASER_OUT_CA_RST", - "CMT_TOP_IMUX11_1", - "CMT_TOP_NE2A3_8", - "CMT_TOP_EE2A3_0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LH4_6", - "CMT_TOP_WW4A3_9", - "CMT_TOP_FAN7_7", - "CMT_TOP_SE2A1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_PHY_CONTROL_TESTOUTPUT15", - "CMT_TOP_SE4C0_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_LH5_3", - "CMT_PHY_CONTROL_TESTINPUT1", - "CMT_TOP_SW2A3_10", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_TOP_WW4END2_11", - "CMT_TOP_ER1BEG0_4", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_TOP_IMUX25_1", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX31_8", - "CMT_TOP_LH3_2", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4END2_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_BYP1_7", - "CMT_TOP_LH3_10", - "CMT_PHASER_UP_DQS_TO_PHASER_C", - "CMT_TOP_WL1END2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_WL1END3_5", - "CMT_TOP_ICLK_3", - "CMT_TOP_IMUX0_5", - "CMT_TOP_SW4A0_8", - "CMT_TOP_FAN7_6", - "CMT_TOP_IMUX4_0", - "CMT_TOP_BYP1_10", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX19_4", - "CMT_TOP_WW4B1_8", - "CMT_TOP_LH4_0", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_EE4A2_10", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_TOP_IMUX44_7", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_TOP_EE4B2_4", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_PHY_CONTROL_ECALIB0", - "CMT_TOP_EE4C3_7", - "CMT_TOP_IMUX3_2", - "CMT_TOP_WL1END1_5", - "CMT_TOP_IMUX42_9", - "CMT_TOP_SE4C0_2", - "CMT_TOP_WW4A1_9", - "CMT_TOP_LH7_2", - "CMT_TOP_WW4A1_4", - "CMT_TOP_CLK0_3", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_IMUX44_8", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_TOP_SE4C2_0", - "CMT_TOP_IMUX23_2", - "CMT_TOP_WW4END3_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_NW4A0_8", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_TOP_WW4END3_0", - "CMT_TOP_IMUX27_1", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_TOP_IMUX21_2", - "CMT_TOP_SE4BEG0_2", - "CMT_PHY_CONTROL_IRANKC1", - "CMT_TOP_FAN6_10", - "CMT_TOP_LH11_6", - "CMT_TOP_CLK1_10", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_PHASER_C_ICLK_TOIOI", - "CMT_TOP_SW2A3_2", - "CMT_TOP_IMUX44_5", - "CMT_TOP_WW2A0_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX33_10", - "CMT_TOP_EE4B3_10", - "CMT_TOP_IMUX24_5", - "CMT_TOP_WW4C1_7", - "CMT_PHY_CONTROL_INBURSTPENDING1", - "CMT_TOP_WW4C2_8", - "CMT_TOP_EE2A3_8", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE2BEG0_5", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_NW4END0_6", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_TOP_SE2A3_0", - "CMT_TOP_EE4C0_10", - "CMT_TOP_IMUX43_10", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NE2A3_0", - "CMT_TOP_LH12_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_EE4C2_3", - "CMT_TOP_WW2END0_10", - "CMT_TOP_FAN2_7", - "CMT_TOP_WW4A3_0", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_IMUX31_2", - "CMT_TOP_FAN3_7", - "CMT_TOP_IMUX3_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_IMUX8_6", - "CMT_TOP_EE4A1_1", - "CMT_TOP_SW4A0_5", - "CMT_TOP_EE2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_WR1END1_10", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_TOP_EE2A0_6", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX47_6", - "CMT_TOP_SW4A2_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_CTRL1_6", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_EL1BEG1_11", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_TOP_NE2A1_3", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NW4END1_1", - "CMT_TOP_CLK1_5", - "CMT_TOP_WW4C1_0", - "CMT_TOP_EE4B3_3", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_WW4B2_2", - "CMT_TOP_NW4END1_7", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_IMUX9_2", - "CMT_TOP_NW4A0_1", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX10_10", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_WW4B3_6", - "CMT_PHY_CONTROL_TESTINPUT3", - "CMT_TOP_EE2BEG0_9", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_LH1_0", - "CMT_TOP_WW4B1_10", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_OCLK1X_90_7", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_TOP_LH10_5", - "CMT_TOP_IMUX15_0", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4C2_9", - "CMT_TOP_SE2A3_1", - "CMT_TOP_BYP0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_WR1END0_11", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX8_5", - "CMT_TOP_WW4C2_9", - "CMT_TOP_CLK1_6", - "CMT_TOP_FAN6_11", - "CMT_TOP_IMUX23_4", - "CMT_TOP_NW4END3_9", - "CMT_PHY_CONTROL_TESTOUTPUT8", - "CMT_TOP_WW4A2_3", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX17_3", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LH1_8", - "CMT_TOP_LH11_1", - "CMT_TOP_IMUX3_5", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_ER1BEG2_10", - "CMT_PHASER_IN_DB_RCLK", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_PHY_CONTROL_IRANKD0", - "CMT_TOP_SW4A0_10", - "CMT_TOP_FAN4_1", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_SE4C1_6", - "CMT_PHY_CONTROL_TESTINPUT12", - "CMT_TOP_WR1END3_10", - "CMT_TOP_IMUX15_9", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_IMUX24_3", - "CMT_TOP_BYP0_2", - "CMT_TOP_LH2_10", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_SE4C1_11", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_SE4BEG3_0", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_PHY_CONTROL_AUXOUTPUT1", - "CMT_TOP_SW4A3_2", - "CMT_TOP_EL1BEG1_9", - "CMT_PHY_CONTROL_PHYCTLWD15", - "CMT_TOP_LH8_11", - "CMT_TOP_LH5_11", - "CMT_TOP_FAN4_4", - "CMT_PHY_CONTROL_PHYCTLWD22", - "CMT_TOP_WW4C3_0", - "CMT_TOP_EE4C2_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_SW2A1_11", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX35_3", - "CMT_TOP_NE4C2_4", - "CMT_PHY_CONTROL_PHYCTLWD10", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_IMUX38_9", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_SE4C2_1", - "CMT_TOP_CTRL0_1", - "CMT_TOP_IMUX2_4", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_IMUX17_2", - "CMT_PHASER_IN_C_ICLK", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_TOP_IMUX16_2", - "CMT_TOP_SW4A1_4", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_NE4C1_11", - "CMT_TOP_EE2BEG3_1", - "CMT_PHASERD_DTSBUS0", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_NE2A1_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_IMUX17_5", - "CMT_TOP_ER1BEG0_3", - "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_SW4END1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_TOP_BYP1_4", - "CMT_PHY_CONTROL_PHYCTLWD14", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_NW4END0_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX26_4", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_BYP4_3", - "CMT_TOP_WL1END2_10", - "CMT_TOP_FAN5_2", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4C0_9", - "CMT_TOP_IMUX29_3", - "CMT_TOP_EE4C1_7", - "CMT_TOP_IMUX29_2", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4A2_1", - "CMT_TOP_SE4BEG1_10", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_NW2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_EE4B0_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_SW4END2_11", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_TOP_WW4B2_8", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_TOP_SW4A2_9", - "CMT_TOP_NW4A2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4END0_9", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_NE2A3_7", - "CMT_TOP_FAN5_1", - "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "CMT_TOP_IMUX21_11", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_FAN1_11", - "CMT_TOP_IMUX32_6", - "CMT_TOP_SW4A0_11", - "CMT_TOP_IMUX8_10", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX24_10", - "CMT_TOP_LH3_7", - "CMT_TOP_WR1END1_7", - "CMT_TOP_NW2A0_5", - "CMT_TOP_EE4B0_11", - "CMT_TOP_BYP3_1", - "CMT_TOP_MONITOR_N_0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_TOP_LH9_2", - "CMT_TOP_WW2A2_4", - "CMT_TOP_IMUX41_9", - "CMT_TOP_BYP5_9", - "CMT_TOP_IMUX40_6", - "CMT_PHASERREF_PHASEROUT_C", - "CMT_TOP_WL1END3_3", - "CMT_TOP_NW4A3_0", - "CMT_TOP_LH9_8", - "CMT_TOP_IMUX7_5", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_EE4BEG1_2", - "CMT_PHY_CONTROL_IBURSTPENDING2", - "CMT_TOP_WW4A0_5", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_IMUX12_7", - "CMT_TOP_SW4A0_7", - "CMT_TOP_EE4A0_4", - "CMT_TOP_IMUX7_11", - "CMT_TOP_EE4B3_7", - "CMT_TOP_IMUX4_7", - "CMT_TOP_EE4C2_0", - "CMT_TOP_WW4B1_9", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_SE4C0_0", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_TOP_WW4A1_0", - "CMT_TOP_LH1_2", - "CMT_TOP_SW4END0_8", - "CMT_TOP_FAN3_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_EE4BEG1_9", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_LH11_5", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_WR1END0_2", - "CMT_TOP_IMUX30_5", - "CMT_TOP_NW4A3_3", - "CMT_TOP_WW4B3_8", - "CMT_TOP_IMUX0_1", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_WW2END2_8", - "CMT_TOP_IMUX38_7", - "CMT_TOP_NW2A1_3", - "CMT_TOP_EE4A2_5", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_TOP_NE2A2_0", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_TOP_WW4C1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_WW4B2_11", - "CMT_TOP_CLK0_7", - "CMT_TOP_EE2A1_3", - "CMT_TOP_SW4END1_2", - "CMT_PHASER_REF_TESTIN5", - "CMT_TOP_IMUX9_3", - "CMT_TOP_FAN7_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LH11_3", - "CMT_TOP_IMUX13_3", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_LH10_10", - "CMT_TOP_SW4A1_10", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NE4C0_6", - "CMT_TOP_BYP0_3", - "CMT_TOP_SE4C2_2", - "CMT_TOP_NW4A1_3", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_TOP_LH10_4", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX8_4", - "CMT_TOP_WL1END0_9", - "CMT_PHASER_UP_PHASERREF_ABOVE1", - "CMT_TOP_SW2A1_6", - "CMT_TOP_IMUX26_3", - "CMT_TOP_NW2A2_0", - "CMT_TOP_WW4END0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_OCLKDIV_8", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_PHY_CONTROL_PHYCTLWD28", - "CMT_TOP_WW2END1_6", - "CMT_PHY_CONTROL_TESTOUTPUT10", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WW4C1_1", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_WW2A1_5", - "CMT_TOP_CTRL1_1", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_BYP7_3", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_PHASER_IN_C_ICLKDIV", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_WR1END0_10", - "CMT_TOP_IMUX45_0", - "CMT_TOP_WL1END1_7", - "CMT_PHASER_REF_TMUXOUT", - "CMT_TOP_LH2_7", - "CMT_TOP_WW4END1_2", - "CMT_TOP_LH7_7", - "CMT_TOP_IMUX26_8", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_SE4C2_10", - "CMT_FREQ_BB_PREF_IN1", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_EE4A2_11", - "CMT_TOP_NW4END1_4", - "CMT_PHASER_UP_PHASERREF_BELOW0", - "CMT_TOP_IMUX25_11", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_NW2A1_6", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_PHY_CONTROL_ECALIB1", - "CMT_TOP_BYP2_4", - "CMT_TOP_NW4END2_3", - "CMT_TOP_WL1END0_11", - "CMT_TOP_IMUX18_10", - "CMT_TOP_EE4C1_8", - "CMT_PHY_CONTROL_PHYCTLWD19", - "CMT_TOP_WW2END1_4", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_WW2END3_9", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE4C2_4", - "CMT_PHASER_IN_CA_RST", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_IMUX1_9", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_NW4A1_4", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_SW2A0_3", - "CMT_TOP_IMUX22_6", - "CMT_TOP_EE4C2_2", - "CMT_TOP_IMUX5_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_EE4C3_1", - "CMT_TOP_NE2A2_4", - "CMT_TOP_LH9_6", - "CMT_TOP_IMUX28_5", - "CMT_TOP_EE2A2_9", - "CMT_TOP_NW4A3_4", - "CMT_TOP_SW2A2_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX11_9", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LH2_9", - "CMT_TOP_WW2A2_2", - "CMT_TOP_IMUX3_11", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_IMUX45_11", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX45_5", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_WW4C3_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX24_6", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_IMUX35_5", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_EE2A0_7", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_TOP_WW4B2_4", - "CMT_TOP_FAN2_8", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_TOP_SW2A1_0", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_WL1END0_5", - "CMT_TOP_CLK0_9", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX29_4", - "CMT_TOP_NE2A0_11", - "CMT_TOP_FAN2_3", - "CMT_TOP_NE4C2_1", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_IMUX31_5", - "CMT_TOP_WR1END1_5", - "CMT_TOP_IMUX8_7", - "CMT_TOP_CTRL1_7", - "CMT_TOP_IMUX27_9", - "CMT_TOP_EL1BEG1_3", - "CMT_PHY_CONTROL_IRANKA0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4C3_8", - "CMT_TOP_BYP6_6", - "CMT_PHY_CONTROL_TESTINPUT5", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_TOP_EE4C1_4", - "CMT_TOP_IMUX46_6", - "CMT_TOP_NW4A3_11", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_PHASER_UP_BUFMRCE_CE0", - "CMT_TOP_NW4END0_7", - "CMT_TOP_CLK1_11", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_BYP3_8", - "CMT_TOP_IMUX16_8", - "CMT_TOP_SW4END3_7", - "CMT_TOP_WW2A1_4", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_TOP_WW2END3_0", - "CMT_TOP_SE2A0_5", - "CMT_TOP_WW2A1_0", - "CMT_TOP_NW4A2_5", - "CMT_TOP_EE2BEG1_8", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_PHY_CONTROL_TESTOUTPUT0", - "CMT_PHY_CONTROL_PHYCTLWD16", - "CMT_TOP_WW4END2_1", - "CMT_TOP_NW2A2_5", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_TOP_MONITOR_N_9", - "CMT_PHASER_OUT_DB_RST", - "CMT_TOP_IMUX18_9", - "CMT_TOP_SE2A0_4", - "CMT_PHY_CONTROL_PHYCTLWD18", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_IMUX6_5", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_EE4A2_8", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX7_6", - "CMT_TOP_CTRL0_9", - "CMT_TOP_EE2BEG3_9", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_PHY_CONTROL_PHYCTLWD4", - "CMT_TOP_IMUX6_11", - "CMT_TOP_WW4B3_2", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_EE4C0_4", - "CMT_TOP_BYP2_1", - "CMT_TOP_IMUX36_8", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_NW2A3_5", - "CMT_TOP_IMUX27_3", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_TOP_LH7_11", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_WW4C2_2", - "CMT_TOP_BYP1_6", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_SE2A0_10", - "CMT_TOP_IMUX1_3", - "CMT_PHY_CONTROL_TESTINPUT11", - "CMT_PHY_CONTROL_PHYCTLWD5", - "CMT_TOP_IMUX1_4", - "CMT_TOP_NW4END0_10", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_IMUX8_8", - "CMT_TOP_EL1BEG0_6", - "CMT_PHASERREF_PHASERIN_C", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX2_9", - "CMT_TOP_SE2A2_1", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG1_0", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_NE4C2_10", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX3_9", - "CMT_TOP_EE4A2_9", - "CMT_TOP_WW2A3_2", - "CMT_TOP_BYP5_0", - "CMT_TOP_NE4C2_8", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX17_9", - "PLL_CLK_FREQBB_REBUFOUT2", - "CMT_PHY_CONTROL_AUXOUTPUT0", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_IMUX0_8", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_FREQ_PHASER_REFMUX_0", - "CMT_TOP_NE4C3_5", - "CMT_TOP_WR1END3_9", - "CMT_TOP_EE4C3_9", - "CMT_TOP_IMUX35_8", - "CMT_TOP_BYP3_5", - "CMT_TOP_IMUX32_8", - "CMT_PHY_CONTROL_INRANKC1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_NW4A0_11", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_TOP_IMUX34_9", - "CMT_R_TOP_UPPER_B_CLKPLL1", - "CMT_TOP_SE4C3_5", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX47_11", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_FAN6_4", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_TOP_IMUX21_7", - "CMT_TOP_WW2END0_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LH5_2", - "CMT_TOP_IMUX17_4", - "CMT_TOP_SW2A1_8", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_NE4C1_9", - "CMT_TOP_LH3_8", - "CMT_TOP_BYP0_9", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_TOP_WW2END0_4", - "CMT_TOP_EE2A1_7", - "CMT_TOP_NW2A2_11", - "CMT_TOP_WW2END3_6", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_WW4B0_11", - "CMT_TOP_EE2BEG1_2", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_TOP_SW2A3_9", - "CMT_PHY_CONTROL_PHYCTLWD0", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_TOP_IMUX32_9", - "CMT_TOP_EE2A0_2", - "CMT_TOP_SW4END2_6", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_IMUX47_1", - "CMT_TOP_WW2A2_1", - "CMT_TOP_NW2A1_7", - "CMT_TOP_IMUX14_0", - "CMT_TOP_LH7_4", - "CMT_TOP_EE4C0_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX45_3", - "CMT_TOP_SW4END3_11", - "CMT_TOP_WW4C1_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX33_7", - "CMT_PHY_CONTROL_INRANKC0", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_FAN4_11", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_TOP_LH5_4", - "CMT_TOP_CLK0_4", - "CMT_TOP_OCLK_9", - "CMT_TOP_IMUX22_8", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_PHASERREF_PHASERIN_D", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_WW4A3_4", - "CMT_TOP_NW4A1_6", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SW4A3_4", - "CMT_TOP_NE2A0_10", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_LH8_7", - "CMT_TOP_IMUX32_5", - "CMT_TOP_SW2A1_5", - "CMT_TOP_WR1END0_1", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_LOGIC_OUTS_L_B13_10" - ], - "sites": [ - { - "prefix": "PHASER_REF", - "y_coord": 0, - "type": "PHASER_REF", - "site_pins": { - "TESTIN1": "CMT_PHASER_REF_TESTIN1", - "LOCKED": "CMT_PHASER_REF_LOCKED", - "CLKOUT": "CMT_PHASER_REF_CLKOUT", - "TESTIN5": "CMT_PHASER_REF_TESTIN5", - "TESTIN0": "CMT_PHASER_REF_TESTIN0", - "TESTOUT7": "CMT_PHASER_REF_TESTOUT7", - "TESTOUT6": "CMT_PHASER_REF_TESTOUT6", - "TMUXOUT": "CMT_PHASER_REF_TMUXOUT", - "TESTOUT2": "CMT_PHASER_REF_TESTOUT2", - "TESTOUT3": "CMT_PHASER_REF_TESTOUT3", - "TESTOUT4": "CMT_PHASER_REF_TESTOUT4", - "TESTIN3": "CMT_PHASER_REF_TESTIN3", - "TESTOUT1": "CMT_PHASER_REF_TESTOUT1", - "TESTIN6": "CMT_PHASER_REF_TESTIN6", - "TESTOUT0": "CMT_PHASER_REF_TESTOUT0", - "PWRDWN": "CMT_PHASER_REF_PWRDWN", - "TESTIN4": "CMT_PHASER_REF_TESTIN4", - "TESTOUT5": "CMT_PHASER_REF_TESTOUT5", - "CLKIN": "CMT_PHASER_REF_CLKIN", - "TESTIN2": "CMT_PHASER_REF_TESTIN2", - "RST": "CMT_PHASER_REF_RST", - "TESTIN7": "CMT_PHASER_REF_TESTIN7" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "PHY_CONTROL", - "y_coord": 0, - "type": "PHY_CONTROL", - "site_pins": { - "OUTBURSTPENDING3": "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "PHYCTLWD27": "CMT_PHY_CONTROL_PHYCTLWD27", - "INRANKD0": "CMT_PHY_CONTROL_INRANKD0", - "PHYCTLWD8": "CMT_PHY_CONTROL_PHYCTLWD8", - "PHYCTLWD19": "CMT_PHY_CONTROL_PHYCTLWD19", - "TESTINPUT2": "CMT_PHY_CONTROL_TESTINPUT2", - "PHYCTLWD13": "CMT_PHY_CONTROL_PHYCTLWD13", - "PHYCTLWD0": "CMT_PHY_CONTROL_PHYCTLWD0", - "PHYCTLWD1": "CMT_PHY_CONTROL_PHYCTLWD1", - "TESTSELECT0": "CMT_PHY_CONTROL_TESTSELECT0", - "PLLLOCK": "CMT_PHY_CONTROL_PLLLOCK", - "TESTOUTPUT7": "CMT_PHY_CONTROL_TESTOUTPUT7", - "PHYCTLWD11": "CMT_PHY_CONTROL_PHYCTLWD11", - "TESTINPUT3": "CMT_PHY_CONTROL_TESTINPUT3", - "PHYCTLWD2": "CMT_PHY_CONTROL_PHYCTLWD2", - "INRANKB1": "CMT_PHY_CONTROL_INRANKB1", - "PHYCTLREADY": "CMT_PHY_CONTROL_PHYCTLREADY", - "PHYCTLWD22": "CMT_PHY_CONTROL_PHYCTLWD22", - "AUXOUTPUT1": "CMT_PHY_CONTROL_AUXOUTPUT1", - "PCENABLECALIB0": "CMT_PHY_CONTROL_PCENABLECALIB0", - "TESTOUTPUT11": "CMT_PHY_CONTROL_TESTOUTPUT11", - "PHYCTLWD6": "CMT_PHY_CONTROL_PHYCTLWD6", - "OUTBURSTPENDING0": "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "REFDLLLOCK": "CMT_PHY_CONTROL_REFDLLLOCK", - "OUTBURSTPENDING1": "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "PHYCLK": "CMT_PHY_CONTROL_PHYCLK", - "TESTINPUT8": "CMT_PHY_CONTROL_TESTINPUT8", - "TESTOUTPUT5": "CMT_PHY_CONTROL_TESTOUTPUT5", - "TESTINPUT13": "CMT_PHY_CONTROL_TESTINPUT13", - "PHYCTLWD25": "CMT_PHY_CONTROL_PHYCTLWD25", - "INRANKD1": "CMT_PHY_CONTROL_INRANKD1", - "PHYCTLWD28": "CMT_PHY_CONTROL_PHYCTLWD28", - "PHYCTLWD23": "CMT_PHY_CONTROL_PHYCTLWD23", - "PHYCTLWD31": "CMT_PHY_CONTROL_PHYCTLWD31", - "INRANKC0": "CMT_PHY_CONTROL_INRANKC0", - "AUXOUTPUT3": "CMT_PHY_CONTROL_AUXOUTPUT3", - "PHYCTLWD17": "CMT_PHY_CONTROL_PHYCTLWD17", - "PHYCTLMSTREMPTY": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "TESTINPUT6": "CMT_PHY_CONTROL_TESTINPUT6", - "AUXOUTPUT2": "CMT_PHY_CONTROL_AUXOUTPUT2", - "TESTINPUT5": "CMT_PHY_CONTROL_TESTINPUT5", - "INBURSTPENDING0": "CMT_PHY_CONTROL_INBURSTPENDING0", - "TESTINPUT10": "CMT_PHY_CONTROL_TESTINPUT10", - "INRANKA1": "CMT_PHY_CONTROL_INRANKA1", - "PHYCTLWD15": "CMT_PHY_CONTROL_PHYCTLWD15", - "TESTINPUT1": "CMT_PHY_CONTROL_TESTINPUT1", - "TESTOUTPUT8": "CMT_PHY_CONTROL_TESTOUTPUT8", - "INRANKC1": "CMT_PHY_CONTROL_INRANKC1", - "WRITECALIBENABLE": "CMT_PHY_CONTROL_WRITECALIBENABLE", - "INBURSTPENDING3": "CMT_PHY_CONTROL_INBURSTPENDING3", - "TESTOUTPUT1": "CMT_PHY_CONTROL_TESTOUTPUT1", - "PHYCTLWD16": "CMT_PHY_CONTROL_PHYCTLWD16", - "PHYCTLWD5": "CMT_PHY_CONTROL_PHYCTLWD5", - "PHYCTLWD3": "CMT_PHY_CONTROL_PHYCTLWD3", - "PHYCTLWD7": "CMT_PHY_CONTROL_PHYCTLWD7", - "TESTINPUT4": "CMT_PHY_CONTROL_TESTINPUT4", - "PCENABLECALIB1": "CMT_PHY_CONTROL_PCENABLECALIB1", - "PHYCTLWD18": "CMT_PHY_CONTROL_PHYCTLWD18", - "PHYCTLFULL": "CMT_PHY_CONTROL_PHYCTLFULL", - "PHYCTLWD12": "CMT_PHY_CONTROL_PHYCTLWD12", - "MEMREFCLK": "CMT_PHY_CONTROL_MEMREFCLK", - "TESTOUTPUT0": "CMT_PHY_CONTROL_TESTOUTPUT0", - "TESTOUTPUT3": "CMT_PHY_CONTROL_TESTOUTPUT3", - "PHYCTLWD26": "CMT_PHY_CONTROL_PHYCTLWD26", - "PHYCTLEMPTY": "CMT_PHY_CONTROL_PHYCTLEMPTY", - "SYNCIN": "CMT_PHY_CONTROL_SYNCIN", - "TESTSELECT2": "CMT_PHY_CONTROL_TESTSELECT2", - "TESTINPUT11": "CMT_PHY_CONTROL_TESTINPUT11", - "AUXOUTPUT0": "CMT_PHY_CONTROL_AUXOUTPUT0", - "TESTOUTPUT4": "CMT_PHY_CONTROL_TESTOUTPUT4", - "PHYCTLWD29": "CMT_PHY_CONTROL_PHYCTLWD29", - "TESTOUTPUT10": "CMT_PHY_CONTROL_TESTOUTPUT10", - "INRANKB0": "CMT_PHY_CONTROL_INRANKB0", - "TESTINPUT14": "CMT_PHY_CONTROL_TESTINPUT14", - "PHYCTLALMOSTFULL": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "TESTINPUT7": "CMT_PHY_CONTROL_TESTINPUT7", - "OUTBURSTPENDING2": "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "PHYCTLWD4": "CMT_PHY_CONTROL_PHYCTLWD4", - "PHYCTLWD9": "CMT_PHY_CONTROL_PHYCTLWD9", - "TESTINPUT12": "CMT_PHY_CONTROL_TESTINPUT12", - "TESTOUTPUT9": "CMT_PHY_CONTROL_TESTOUTPUT9", - "INRANKA0": "CMT_PHY_CONTROL_INRANKA0", - "TESTINPUT9": "CMT_PHY_CONTROL_TESTINPUT9", - "TESTINPUT0": "CMT_PHY_CONTROL_TESTINPUT0", - "TESTOUTPUT15": "CMT_PHY_CONTROL_TESTOUTPUT15", - "SCANENABLEN": "CMT_PHY_CONTROL_SCANENABLEN", - "PHYCTLWD20": "CMT_PHY_CONTROL_PHYCTLWD20", - "PHYCTLWD21": "CMT_PHY_CONTROL_PHYCTLWD21", - "TESTINPUT15": "CMT_PHY_CONTROL_TESTINPUT15", - "TESTOUTPUT12": "CMT_PHY_CONTROL_TESTOUTPUT12", - "PHYCTLWD30": "CMT_PHY_CONTROL_PHYCTLWD30", - "INBURSTPENDING2": "CMT_PHY_CONTROL_INBURSTPENDING2", - "PHYCTLWD10": "CMT_PHY_CONTROL_PHYCTLWD10", - "READCALIBENABLE": "CMT_PHY_CONTROL_READCALIBENABLE", - "PHYCTLWRENABLE": "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "TESTOUTPUT14": "CMT_PHY_CONTROL_TESTOUTPUT14", - "PHYCTLWD24": "CMT_PHY_CONTROL_PHYCTLWD24", - "TESTOUTPUT2": "CMT_PHY_CONTROL_TESTOUTPUT2", - "TESTOUTPUT13": "CMT_PHY_CONTROL_TESTOUTPUT13", - "TESTOUTPUT6": "CMT_PHY_CONTROL_TESTOUTPUT6", - "TESTSELECT1": "CMT_PHY_CONTROL_TESTSELECT1", - "PHYCTLWD14": "CMT_PHY_CONTROL_PHYCTLWD14", - "INBURSTPENDING1": "CMT_PHY_CONTROL_INBURSTPENDING1", - "RESET": "CMT_PHY_CONTROL_RESET" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "PHASER_OUT_PHY", - "y_coord": 8, - "type": "PHASER_OUT_PHY", - "site_pins": { - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "RST": "CMT_PHASER_OUT_CA_RST", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y8" - }, - { - "prefix": "PHASER_IN_PHY", - "y_coord": 8, - "type": "PHASER_IN_PHY", - "site_pins": { - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", - "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", - "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", - "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", - "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", - "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", - "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", - "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "ICLK": "CMT_PHASER_IN_CA_ICLK", - "RCLK": "CMT_PHASER_IN_CA_RCLK", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", - "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", - "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", - "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", - "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", - "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", - "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", - "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", - "SCANIN": "CMT_PHASER_IN_CA_SCANIN", - "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", - "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", - "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", - "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", - "STG1READ": "CMT_PHASER_IN_CA_STG1READ", - "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", - "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", - "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", - "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", - "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", - "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", - "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", - "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", - "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", - "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", - "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", - "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", - "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", - "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", - "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", - "SCANENB": "CMT_PHASER_IN_CA_SCANENB", - "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", - "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", - "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", - "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", - "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", - "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", - "RST": "CMT_PHASER_IN_CA_RST", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", - "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", - "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", - "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", - "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", - "FINEINC": "CMT_PHASER_IN_CA_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", - "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", - "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", - "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", - "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", - "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", - "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", - "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", - "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", - "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", - "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y8" - }, - { - "prefix": "PHASER_OUT_PHY", - "y_coord": 9, - "type": "PHASER_OUT_PHY", - "site_pins": { - "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", - "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", - "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", - "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", - "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", - "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", - "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", - "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", - "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", - "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", - "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", - "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", - "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", - "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", - "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", - "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", - "OCLK": "CMT_PHASER_OUT_DB_OCLK", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", - "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", - "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", - "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", - "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", - "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", - "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", - "RST": "CMT_PHASER_OUT_DB_RST", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", - "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", - "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", - "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", - "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", - "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", - "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", - "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", - "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", - "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", - "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", - "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", - "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", - "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y9" - }, - { - "prefix": "PHASER_IN_PHY", - "y_coord": 9, - "type": "PHASER_IN_PHY", - "site_pins": { - "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", - "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", - "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", - "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", - "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", - "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", - "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", - "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", - "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "ICLK": "CMT_PHASER_IN_DB_ICLK", - "RCLK": "CMT_PHASER_IN_DB_RCLK", - "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", - "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", - "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", - "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", - "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", - "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", - "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", - "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", - "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", - "SCANIN": "CMT_PHASER_IN_DB_SCANIN", - "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", - "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", - "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", - "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", - "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", - "STG1READ": "CMT_PHASER_IN_DB_STG1READ", - "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", - "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", - "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", - "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", - "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", - "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", - "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", - "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", - "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", - "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", - "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", - "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", - "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", - "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", - "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", - "SCANENB": "CMT_PHASER_IN_DB_SCANENB", - "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", - "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", - "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", - "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", - "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", - "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", - "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", - "RST": "CMT_PHASER_IN_DB_RST", - "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", - "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", - "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", - "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", - "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", - "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", - "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", - "FINEINC": "CMT_PHASER_IN_DB_FINEINC", - "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", - "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", - "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", - "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", - "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", - "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", - "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", - "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", - "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", - "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", - "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", - "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", - "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", - "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y9" - } - ], "pips": { - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_0": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_C_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B16_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKA1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKA1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKD1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKD1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKC1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKC1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_WRENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_REF_LOCKED->CMT_TOP_LOGIC_OUTS_L_B14_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_REF_LOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_directional": "1", "src_wire": "CMT_FREQ_BB_PREF_IN3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_C_ICLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_C_ICLK", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERD_DQSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING3->CMT_PHY_CONTROL_IBURSTPENDING3": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_WRENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_C_RDCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_C_RDCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_D_WRCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_D_WRCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS0->CMT_PHASERD_CTSBUS0": { "can_invert": "0", - "dst_wire": "CMT_PHASERD_CTSBUS0", - "is_directional": "1", "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO->CMT_PHASER_IN_C_ICLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_C_ICLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_C_WRCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX9_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY->CMT_PHY_CONTROL_PHYCTLMSTREMPTY": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "is_directional": "1", - "src_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_D_RDCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_D_RDCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX41_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX28_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX41_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKD0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKD0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASEROUT_D->CMT_PHASER_OUT_DB_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": { - "can_invert": "0", - "dst_wire": "CMT_PHASERD_CTSBUS1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX18_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IRANKC1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING1->CMT_PHY_CONTROL_IBURSTPENDING1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX37_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B15_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>CMT_FREQ_PHASER_REFMUX_1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASERIN_D->CMT_PHASER_IN_DB_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_PHASERIN_D", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_BB_PREF_IN3", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQBB_REBUFOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IRANKD0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX23_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX41_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_D_ICLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_D_WRCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IRANKD1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PLLLOCK", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_D_OCLK1X_90": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_D_OCLK1X_90", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDCLK_TOFIFO->CMT_PHASER_OUT_D_OCLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_D_OCLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_D_RDCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_CLK1_0->>CMT_R_TOP_UPPER_B_CLKINT_3": { - "can_invert": "0", - "dst_wire": "CMT_R_TOP_UPPER_B_CLKINT_3", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK1_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHY_CONTROL_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX4_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS0->CMT_PHASERD_DTSBUS0": { - "can_invert": "0", - "dst_wire": "CMT_PHASERD_DTSBUS0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT0->CMT_TOP_LOGIC_OUTS_L_B3_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_9", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT1->CMT_TOP_LOGIC_OUTS_L_B21_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_9", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": { - "can_invert": "0", - "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING0->CMT_PHY_CONTROL_IBURSTPENDING0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_ECALIB0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT2->CMT_TOP_LOGIC_OUTS_L_B17_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_10", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_D_ICLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_BB_PREF_IN2", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQBB_REBUFOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASEROUT_C->CMT_PHASER_OUT_CA_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_PHASEROUT_C", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_BB_PREF_IN0", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQBB_REBUFOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B21_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_RESET", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX11_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_REF_TMUXOUT->CMT_PHASER_REF_TMUXOUT_TOHCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_REF_TMUXOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_C_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING2->CMT_PHY_CONTROL_IBURSTPENDING2": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX39_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX8_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_REF_CLKIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_CLKIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT3->CMT_TOP_LOGIC_OUTS_L_B17_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_11", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_D_RDENABLE_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_D_RDENABLE_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHY_CONTROL_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO->CMT_PHASER_OUT_C_OCLKDIV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_C_RDCLK_TOFIFO", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY->>CMT_PHASER_TOP_SYNC_BB": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_TOP_SYNC_BB", - "is_directional": "1", - "src_wire": "CMT_PHASERTOP_PHYCTLEMPTY", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX9_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX4_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_BB_PREF_IN1", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQBB_REBUFOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_10->CMT_PHY_CONTROL_PHYCTLWD18": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX11_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKA0->CMT_PHY_CONTROL_IRANKA0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKA0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKA0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX9_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASERIN_C->CMT_PHASER_IN_CA_PHASEREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", - "is_directional": "1", - "src_wire": "CMT_PHASERREF_PHASERIN_C", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_CTSBUS0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS0->CMT_PHASERD_DQSBUS0": { "can_invert": "0", - "dst_wire": "CMT_PHASERD_DQSBUS0", - "is_directional": "1", "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_C_RDENABLE_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_C_RDENABLE_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_C_RCLK2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_C_RCLK2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_RCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", - "is_pseudo": "1" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_0->>CMT_R_TOP_UPPER_B_CLKINT_2": { - "can_invert": "0", - "dst_wire": "CMT_R_TOP_UPPER_B_CLKINT_2", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKB0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX17_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX30_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_D": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_D", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_SYNCIN", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX18_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX27_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_FINEINC", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DQSBUS0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_1", - "is_directional": "1", "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1" }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": { "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "src_wire": "CMT_TOP_IMUX34_4", "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": { + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX12_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX11_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX31_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_TOP_SYNC_BB->>CMT_PHASERTOP_PHYCTLMSTREMPTY": { - "can_invert": "0", - "dst_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", - "is_directional": "1", - "src_wire": "CMT_PHASER_TOP_SYNC_BB", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_1": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_IRANKC0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B3_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK1X_90_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK90_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX45_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_C->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_C", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_RCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", - "is_pseudo": "1" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B6_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX29_3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_D_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_D_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_2": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_0": { - "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_C_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX22_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX17_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_D_RCLK3", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_RCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_C_WRCLK_TOFIFO": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_C_WRCLK_TOFIFO", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX46_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKC0", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKC0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "is_directional": "1", "src_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX4_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1" }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_1": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": { "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", + "src_wire": "CMT_PHASER_IN_CA_ISERDESRST", "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_C", - "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_10", - "is_directional": "1", "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX43_11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5" }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS1->CMT_PHASERD_DTSBUS1": { + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": { "can_invert": "0", - "dst_wire": "CMT_PHASERD_DTSBUS1", + "src_wire": "CMT_TOP_IMUX14_9", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": { + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12", + "src_wire": "CMT_TOP_IMUX4_9", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0" }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": { + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", + "src_wire": "CMT_TOP_IMUX41_4", "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_EDGEADV" }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "src_wire": "CMT_TOP_IMUX20_10", "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_ECALIB1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": { + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_1": { "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30", + "src_wire": "CMT_FREQ_BB_PREF_IN2", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_C": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0" }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_D->>CMT_PHASERREF_PHASERIN_D": { + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": { "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2", "is_directional": "1", - "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_D", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKOUT->CMT_PHASER_REF_CLKOUT_TOHCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_CLKOUT_TOHCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_REF_CLKOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX8_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_C_OCLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_C_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>CMT_FREQ_PHASER_REFMUX_0": { "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_directional": "1", "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0", "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_2": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_8", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX17_5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX20_9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", - "is_directional": "1", - "src_wire": "CMT_FREQ_PHASER_REFMUX_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": { - "can_invert": "0", - "dst_wire": "CMT_PHY_CONTROL_IRANKB1", - "is_directional": "1", - "src_wire": "CMT_PHY_CONTROL_INRANKB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_C_OCLK", - "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_7", - "is_directional": "1", "src_wire": "CMT_PHASER_C_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_C": { - "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASEROUT_C", "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2" }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_D": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { "can_invert": "0", - "dst_wire": "CMT_PHASERREF_PHASERIN_D", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0", "is_directional": "1", - "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": { + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", + "src_wire": "CMT_TOP_IMUX46_10", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX16_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX14_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7" }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": { + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6", + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0" }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": { + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1", + "src_wire": "CMT_TOP_IMUX13_9", "is_directional": "1", - "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { "can_invert": "0", - "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX16_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9" }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5" }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHY_CONTROL_SYNCIN": { "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_SYNCIN" }, - "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_2": { + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { "can_invert": "0", - "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", + "src_wire": "CMT_TOP_IMUX2_5", "is_directional": "1", - "src_wire": "CMT_FREQ_BB_PREF_IN2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4" }, - "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": { + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING1->CMT_PHY_CONTROL_IBURSTPENDING1": { "can_invert": "0", - "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING1", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX19_6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "is_directional": "1", - "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_0->CMT_PHASER_REF_PWRDWN": { "can_invert": "0", - "dst_wire": "CMT_PHASER_REF_PWRDWN", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX45_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_PWRDWN" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_RST" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT1->CMT_TOP_LOGIC_OUTS_L_B21_9": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_9" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_C_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_ICLK_TOIOI" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING0->CMT_PHY_CONTROL_IBURSTPENDING0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_REF_LOCKED->CMT_TOP_LOGIC_OUTS_L_B14_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_REF_LOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IRANKD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B21_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASERIN_D->CMT_PHASER_IN_DB_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_PHASERIN_D", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX23_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKC0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKC0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHY_CONTROL_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_MEMREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_D_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_REF_CLKIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_CLKIN" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_D_RDCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_RDCLK_TOFIFO" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B6_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_DQSFOUND", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8", "is_directional": "1", - "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK1_0->>CMT_R_TOP_UPPER_B_CLKINT_3": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_TOP_UPPER_B_CLKINT_3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_EDGEADV" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX11_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RST" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_C_WRCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_WRCLK_TOFIFO" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_C_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLK_TOIOI" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_DQSFOUND", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B3_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_3" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_1": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_ECALIB1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_CA_RCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKD1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKA0->CMT_PHY_CONTROL_IRANKA0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKA0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_C_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_WRENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_C_ICLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_ICLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5" + }, + "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQBB_REBUFOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY->CMT_PHY_CONTROL_PHYCTLMSTREMPTY": { + "can_invert": "0", + "src_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYSCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_10->CMT_PHY_CONTROL_PHYCTLWD18": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING2->CMT_PHY_CONTROL_IBURSTPENDING2": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING2" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_C_RDCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_RDCLK_TOFIFO" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_C_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX9_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX4_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK" + }, + "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQBB_REBUFOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN3" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_0": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_RST" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT0->CMT_TOP_LOGIC_OUTS_L_B3_9": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_9" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX20_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_C->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_C", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B15_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_D_RDENABLE_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_RDENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_RDENABLE_TOFIFO" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_FINEINC": { "can_invert": "0", - "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX47_1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEINC" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_D_RDCLK_TOFIFO->CMT_PHASER_OUT_D_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_D_RDCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLKDIV" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING3->CMT_PHY_CONTROL_IBURSTPENDING3": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_REF_TMUXOUT->CMT_PHASER_REF_TMUXOUT_TOHCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_REF_TMUXOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_TMUXOUT_TOHCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IRANKC0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX11_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_RESET" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX17_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO->CMT_PHASER_IN_C_ICLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_C_WRCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_ICLKDIV" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT3->CMT_TOP_LOGIC_OUTS_L_B17_11": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_11" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_1": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_C_RCLK2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_RCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_C_RCLK2" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_1": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PLLLOCK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_ECALIB0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX8_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASEROUT_C->CMT_PHASER_OUT_CA_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_PHASEROUT_C", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B16_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_5" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_WRENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX37_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_D->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_D", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_0": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY->>CMT_PHASER_TOP_SYNC_BB": { + "can_invert": "0", + "src_wire": "CMT_PHASERTOP_PHYCTLEMPTY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_TOP_SYNC_BB" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS0->CMT_PHASERD_DTSBUS0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DTSBUS0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX17_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKB0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DQSBUS1" + }, + "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQBB_REBUFOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_REF_CLKOUT->CMT_PHASER_REF_CLKOUT_TOHCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_REF_CLKOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_REF_CLKOUT_TOHCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "CMT_PHASER_IN_DB_RCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX4_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASERIN_C->CMT_PHASER_IN_CA_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_PHASERIN_C", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_D_OCLK1X_90": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_D_OCLK1X_90" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_0": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX11_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQBB_REBUFOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_BB_PREF_IN0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX28_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_D_WRCLK_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_WRCLK_TOFIFO" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK90_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_7" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_SYNCIN" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_RST" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKD0" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYSCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKB1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_TOP_SYNC_BB->>CMT_PHASERTOP_PHYCTLMSTREMPTY": { + "can_invert": "0", + "src_wire": "CMT_PHASER_TOP_SYNC_BB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX20_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_C" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX39_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RST" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_0->>CMT_R_TOP_UPPER_B_CLKINT_2": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_R_TOP_UPPER_B_CLKINT_2" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS1->CMT_PHASERD_DTSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_DTSBUS1" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX46_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERD_CTSBUS1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX14_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEINC" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_C": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_C" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX8_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASERIN_D" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IRANKD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKA1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX16_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX45_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX9_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX18_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_ECALIB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX9_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>CMT_FREQ_PHASER_REFMUX_1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_RCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_RCLK3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX43_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_FINEINC" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ISERDESRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_IRANKC1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX41_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX12_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT2->CMT_TOP_LOGIC_OUTS_L_B17_10": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_10" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_C_RDENABLE_TOFIFO": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_RDENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_RDENABLE_TOFIFO" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX22_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASERREF_PHASEROUT_D->CMT_PHASER_OUT_DB_PHASEREFCLK": { + "can_invert": "0", + "src_wire": "CMT_PHASERREF_PHASEROUT_D", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO->CMT_PHASER_OUT_C_OCLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_C_RDCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX18_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_D_WRCLK_TOFIFO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_ICLKDIV" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_INRANKC1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHY_CONTROL_IRANKC1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": { + "can_invert": "0", + "src_wire": "CMT_PHASER_IN_DB_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_D_ICLK" + }, + "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { + "can_invert": "0", + "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX41_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_D": { + "can_invert": "0", + "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASERREF_PHASEROUT_D" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6" + }, + "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { + "can_invert": "0", + "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX30_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_FINEINC" + }, + "CMT_TOP_R_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3" + }, + "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": { + "can_invert": "0", + "src_wire": "CMT_FREQ_PHASER_REFMUX_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_IN_CA_SYNCIN" + }, + "CMT_TOP_R_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_2": { + "can_invert": "0", + "src_wire": "CMT_FREQ_BB_PREF_IN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_FREQ_PHASER_REFMUX_2" } }, - "tile_type": "CMT_TOP_R_UPPER_B" + "wires": [ + "CMT_PHASER_IN_DB_TESTIN3", + "CMT_TOP_NW4A2_6", + "CMT_TOP_WW2END3_2", + "CMT_TOP_BYP1_3", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_WW4A3_11", + "CMT_PHASER_IN_DB_STG1REGR4", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_LH7_10", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_NW4A1_2", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_EL1BEG0_11", + "CMT_PHASER_OUT_DB_PHASEREFCLK", + "CMT_TOP_WW2A1_6", + "CMT_TOP_WW4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_PHASER_IN_CA_TESTIN3", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_PHASER_OUT_DB_TESTIN4", + "CMT_TOP_WW4END1_8", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WW4END2_8", + "CMT_TOP_IMUX7_3", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_WW4B3_6", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_PHY_CONTROL_PHYCTLWD21", + "CMT_TOP_BYP6_2", + "CMT_TOP_LH3_8", + "CMT_TOP_WW4B0_5", + "CMT_TOP_LH12_10", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX41_8", + "CMT_PHASER_IN_DB_TESTOUT3", + "CMT_TOP_IMUX36_7", + "CMT_TOP_NE4C0_9", + "CMT_TOP_IMUX32_8", + "CMT_TOP_IMUX17_10", + "CMT_TOP_IMUX7_9", + "CMT_PHASER_IN_CA_TESTOUT2", + "CMT_TOP_WW2END3_5", + "CMT_TOP_SW4END0_1", + "CMT_TOP_IMUX12_8", + "PLLOUT_CLK_FREQ_BB_REBUFIN2", + "CMT_TOP_NW4END3_1", + "CMT_PHY_CONTROL_PHYCTLWD23", + "CMT_PHASER_OUT_CA_TESTIN3", + "CMT_TOP_NE2A3_0", + "CMT_TOP_CLK1_3", + "CMT_TOP_WR1END0_8", + "CMT_TOP_FAN2_8", + "CMT_TOP_IMUX29_10", + "PLLOUT_CLK_FREQ_BB_REBUFOUT0", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_PHASER_IN_CA_STG1REGR4", + "CMT_PHASER_OUT_CA_DQSBUS0", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_EE4B3_0", + "CMT_PHASER_IN_DB_TESTIN12", + "CMT_TOP_BYP4_1", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_OCLK_7", + "CMT_TOP_WW4C0_11", + "CMT_TOP_WW4C0_3", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_IMUX1_1", + "CMT_TOP_LH2_9", + "CMT_TOP_EE2A0_9", + "CMT_TOP_SE4C1_10", + "CMT_TOP_NW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_SE4C2_9", + "CMT_TOP_IMUX35_6", + "CMT_TOP_EE4A0_6", + "CMT_TOP_SE4C0_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_WL1END1_9", + "CMT_TOP_EE4C0_9", + "CMT_TOP_WW2END1_3", + "CMT_TOP_IMUX3_4", + "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_NE2A1_0", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_IMUX39_7", + "CMT_TOP_IMUX14_2", + "CMT_PHASER_IN_DB_TESTIN10", + "CMT_TOP_WW4C3_2", + "CMT_TOP_EE4B3_8", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW4END1_5", + "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "CMT_R_TOP_UPPER_B_CLKPLL7", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_EE4A2_7", + "CMT_TOP_EE2A0_1", + "CMT_TOP_WW4B0_6", + "CMT_TOP_IMUX12_9", + "CMT_TOP_WW4A0_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_WW2A1_11", + "CMT_TOP_IMUX23_6", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_PHASER_UP_PHASERREF0", + "CMT_TOP_IMUX1_3", + "CMT_TOP_SE4C1_9", + "CMT_TOP_WW2A0_9", + "CMT_TOP_WW4C1_11", + "CMT_TOP_BYP7_3", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "CMT_TOP_EE4A0_9", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX30_7", + "CMT_TOP_ICLK_4", + "CMT_TOP_BYP5_9", + "CMT_PHY_CONTROL_TESTOUTPUT14", + "CMT_TOP_OCLKDIV_8", + "CMT_PHASER_REF_TESTOUT5", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_PHASER_OUT_DB_CTSBUS1", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX30_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_WW4C1_0", + "CMT_TOP_WL1END2_11", + "CMT_TOP_WW2A0_5", + "CMT_TOP_IMUX14_3", + "CMT_TOP_EE4B1_9", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "CMT_TOP_SW4END1_5", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_NE2A0_2", + "CMT_PHASER_OUT_DB_BURSTPENDING", + "CMT_TOP_WW4C2_11", + "CMT_TOP_NW2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_FAN3_8", + "CMT_TOP_IMUX27_7", + "CMT_TOP_WW4END1_1", + "CMT_TOP_FAN4_11", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LH8_6", + "CMT_TOP_EE4A0_1", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_SW4END1_9", + "CMT_TOP_WL1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_MONITOR_N_8", + "CMT_PHASER_UP_PHASERREF1", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WW4END1_6", + "CMT_PHASER_OUT_CA_CTSBUS0", + "CMT_TOP_WL1END2_4", + "CMT_TOP_WR1END0_9", + "CMT_TOP_LH5_9", + "CMT_TOP_IMUX11_4", + "CMT_TOP_IMUX3_3", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_BYP7_4", + "CMT_TOP_WR1END0_4", + "CMT_PHASER_IN_DB_RSTDQSFIND", + "CMT_PHASER_IN_CA_TESTIN6", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_SW4A2_0", + "CMT_PHY_CONTROL_PHYCTLWD31", + "CMT_PHASER_OUT_DB_TESTOUT0", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_PHASER_IN_DB_TESTOUT0", + "CMT_TOP_WW4A1_9", + "CMT_TOP_EE2A0_5", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH4_7", + "CMT_PHASERD_DQSBUS0", + "CMT_TOP_IMUX8_11", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LH4_11", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_EE4A1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_IMUX14_4", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_CTRL0_5", + "CMT_PHASER_IN_DB_STG1REGL3", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_EE4A0_3", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX43_3", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LH11_11", + "CMT_TOP_FAN1_5", + "CMT_TOP_NW2A0_7", + "CMT_TOP_EE4B2_1", + "CMT_TOP_IMUX31_7", + "CMT_TOP_WW4B2_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX6_10", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_IMUX47_0", + "CMT_PHASER_IN_DB_DIVIDERST", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "CMT_TOP_IMUX21_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_FAN4_9", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_CLK0_0", + "CMT_TOP_LH9_7", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END3_7", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_IMUX5_11", + "CMT_TOP_EE4B2_9", + "CMT_PHY_CONTROL_TESTOUTPUT7", + "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_NW2A1_2", + "CMT_TOP_SW4END1_1", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_PHASER_OUT_CA_FINEENABLE", + "CMT_TOP_NW4A1_1", + "CMT_TOP_BYP3_9", + "CMT_TOP_WW2A2_4", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "CMT_TOP_SW4A0_9", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_NE2A0_11", + "CMT_TOP_EE4A2_11", + "CMT_TOP_SE4C2_5", + "CMT_TOP_WW4END2_7", + "CMT_TOP_EE4A3_4", + "CMT_TOP_LH9_5", + "CMT_TOP_NE2A0_3", + "CMT_TOP_IMUX46_9", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_EE2A2_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_IMUX33_11", + "CMT_TOP_IMUX9_8", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_IMUX26_4", + "CMT_PHASER_IN_DB_STG1REGR6", + "CMT_TOP_IMUX38_1", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WR1END0_11", + "CMT_TOP_FAN4_10", + "CMT_TOP_FAN2_11", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_BYP1_8", + "CMT_TOP_IMUX31_1", + "CMT_PHASER_OUT_DB_SCANIN", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EE4C3_9", + "CMT_TOP_IMUX36_8", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_PHASER_IN_DB_SELCALORSTG1", + "CMT_TOP_SW4A1_0", + "CMT_TOP_SE2A1_10", + "CMT_TOP_EE4C0_5", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_LH7_0", + "CMT_PHY_CONTROL_PHYCTLWD9", + "CMT_TOP_IMUX33_7", + "CMT_TOP_SE4C1_2", + "CMT_TOP_ER1BEG1_0", + "CMT_PHY_CONTROL_IBURSTPENDING2", + "CMT_TOP_FAN7_10", + "CMT_TOP_LH2_7", + "CMT_TOP_NE4C2_1", + "CMT_TOP_SW4A2_7", + "CMT_TOP_IMUX23_11", + "CMT_PHY_CONTROL_PHYCTLWD11", + "CMT_TOP_WR1END1_5", + "CMT_TOP_NE2A0_10", + "CMT_TOP_SW4END2_0", + "CMT_TOP_LH8_0", + "CMT_TOP_EE4C0_3", + "CMT_TOP_NW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_IMUX8_6", + "CMT_TOP_BYP0_7", + "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "CMT_PHASER_REF_LOCKED", + "CMT_TOP_LH5_0", + "CMT_TOP_IMUX5_2", + "CMT_TOP_WL1END2_6", + "CMT_TOP_BYP1_9", + "CMT_TOP_IMUX9_3", + "CMT_TOP_BYP1_7", + "CMT_PHASER_OUT_CA_TESTIN7", + "CMT_TOP_IMUX47_1", + "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "CMT_TOP_WW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_EE2A1_9", + "CMT_PHASER_IN_DB_BURSTPENDING", + "CMT_TOP_NE4C3_4", + "CMT_TOP_EE4B2_7", + "CMT_TOP_OCLK_5", + "CMT_TOP_NE2A1_6", + "CMT_PHY_CONTROL_TESTINPUT3", + "CMT_TOP_IMUX45_4", + "CMT_TOP_IMUX8_2", + "CMT_TOP_IMUX1_2", + "CMT_TOP_IMUX46_0", + "CMT_TOP_EE4C1_9", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_LH1_7", + "CMT_TOP_BYP5_3", + "CMT_PHASER_IN_CA_TESTIN13", + "CMT_TOP_EE4A3_1", + "CMT_TOP_IMUX40_4", + "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_BYP7_0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_WW4C1_7", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4A3_6", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_IMUX17_11", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_WR1END2_5", + "CMT_TOP_EE4A0_4", + "CMT_PHASER_OUT_D_OCLK1X_90", + "CMT_TOP_SW4A0_3", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX11_6", + "CMT_TOP_IMUX25_7", + "CMT_TOP_IMUX4_8", + "CMT_PHASER_REF_CLKIN", + "CMT_TOP_SE4BEG2_11", + "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "CMT_PHY_CONTROL_PCENABLECALIB0", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX3_9", + "CMT_TOP_NW4END0_5", + "CMT_TOP_SE2A3_6", + "CMT_TOP_NE4C3_10", + "CMT_TOP_IMUX7_4", + "CMT_TOP_LH3_11", + "CMT_TOP_BYP5_6", + "CMT_TOP_WW4C2_5", + "CMT_TOP_LH7_6", + "CMT_TOP_SE2A1_5", + "CMT_TOP_FAN4_7", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH9_2", + "CMT_TOP_BYP0_1", + "CMT_TOP_LH11_0", + "CMT_PHASER_OUT_DB_TESTIN7", + "CMT_TOP_IMUX27_9", + "CMT_TOP_IMUX14_0", + "CMT_TOP_NW2A1_5", + "CMT_TOP_IMUX21_7", + "CMT_TOP_WW4A0_2", + "CMT_TOP_NE2A1_11", + "CMT_TOP_IMUX7_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX23_7", + "CMT_TOP_IMUX10_10", + "CMT_PHY_CONTROL_INBURSTPENDING1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4C1_2", + "CMT_TOP_LH4_3", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH5_6", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW4C1_4", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_FAN4_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_IMUX9_9", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NW4A3_5", + "CMT_TOP_BYP0_11", + "CMT_TOP_EE2BEG1_10", + "PLL_CLK_FREQBB_REBUFOUT2", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_IMUX33_2", + "CMT_TOP_BYP2_1", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_SE2A3_8", + "CMT_TOP_EE4BEG0_2", + "CMT_PHASER_REF_TESTOUT2", + "CMT_TOP_IMUX25_9", + "CMT_TOP_WW2END1_2", + "CMT_PHASER_OUT_CA_TESTIN12", + "CMT_TOP_ER1BEG3_3", + "CMT_PHY_CONTROL_INRANKC0", + "CMT_PHASER_OUT_DB_COARSEINC", + "CMT_TOP_EE4B2_2", + "CMT_PHASER_OUT_DB_TESTIN0", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_IMUX13_9", + "CMT_PHASER_OUT_CA_OSERDESRST", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_NW2A2_7", + "CMT_TOP_OCLKDIV_11", + "CMT_PHASER_IN_C_RCLK2", + "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "CMT_TOP_IMUX5_8", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_IMUX33_5", + "CMT_PHASER_IN_CA_ENCALIB1", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WW4END2_11", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE2A0_7", + "CMT_TOP_WR1END1_10", + "CMT_PHASER_IN_CA_COUNTERLOADEN", + "CMT_TOP_FAN0_9", + "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "CMT_TOP_EE4C2_10", + "CMT_TOP_SW4END3_0", + "CMT_TOP_WR1END1_2", + "CMT_TOP_NW4A1_5", + "CMT_TOP_IMUX4_9", + "CMT_PHASER_OUT_DB_RDENABLE", + "CMT_PHASER_IN_CA_SYSCLK", + "CMT_TOP_IMUX47_8", + "CMT_PHASER_OUT_DB_COUNTERREADEN", + "CMT_TOP_WW4C1_3", + "CMT_TOP_IMUX26_9", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_IMUX41_2", + "CMT_TOP_SE4C1_5", + "CMT_TOP_WL1END2_7", + "CMT_TOP_WW4A0_1", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_R_TOP_UPPER_B_CLKPLL1", + "CMT_FREQ_BB_PREF_IN3", + "CMT_TOP_CTRL0_4", + "CMT_TOP_NW4END2_3", + "CMT_TOP_SE2A2_8", + "CMT_PHASER_IN_CA_STG1LOAD", + "CMT_PHASER_OUT_DB_SCANOUT", + "CMT_TOP_WW4C2_3", + "CMT_TOP_WW2A3_3", + "CMT_TOP_WL1END3_4", + "CMT_TOP_NE2A2_8", + "CMT_TOP_SW2A0_9", + "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_SW2A0_8", + "CMT_TOP_WW4B3_3", + "CMT_TOP_WW2END0_7", + "CMT_PHASER_IN_CA_TESTIN10", + "CMT_TOP_SW4A3_9", + "CMT_PHY_CONTROL_TESTOUTPUT4", + "CMT_TOP_SE4C0_7", + "CMT_TOP_IMUX1_10", + "CMT_TOP_IMUX4_0", + "CMT_PHY_CONTROL_TESTINPUT0", + "CMT_PHASER_OUT_DB_OCLKDIV", + "CMT_TOP_IMUX40_2", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_EE2BEG3_8", + "CMT_PHASER_OUT_DB_DQSBUS0", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX1_6", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_IMUX14_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_IMUX7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WW4A2_4", + "CMT_TOP_WW4B1_7", + "CMT_TOP_EE2A1_6", + "CMT_TOP_IMUX19_2", + "CMT_PHASER_OUT_DB_EDGEADV", + "CMT_TOP_EE2BEG0_11", + "CMT_PHASER_OUT_DB_TESTOUT3", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_FAN3_4", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP7_9", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX24_10", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_SW2A0_2", + "CMT_TOP_BYP7_8", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX47_7", + "CMT_TOP_BYP0_4", + "CMT_TOP_IMUX21_6", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_EE4A3_11", + "CMT_TOP_IMUX5_4", + "CMT_TOP_SE2A3_10", + "CMT_TOP_SW4END2_10", + "CMT_TOP_NW2A0_5", + "CMT_TOP_NE4C1_2", + "CMT_TOP_WW4C0_9", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_WW2END0_1", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_IMUX2_5", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX0_0", + "CMT_PHASER_OUT_CA_TESTIN15", + "CMT_TOP_IMUX15_9", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SW2A2_4", + "CMT_TOP_WW4C2_0", + "CMT_TOP_ICLK_8", + "CMT_TOP_NW2A1_7", + "CMT_TOP_CTRL0_6", + "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "CMT_PHASER_REF_RST", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_NE4BEG1_9", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_WW4A0_6", + "CMT_TOP_IMUX6_8", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WR1END0_1", + "CMT_TOP_CLK0_5", + "CMT_TOP_IMUX41_3", + "CMT_PHY_CONTROL_PLLLOCK", + "CMT_TOP_SE4BEG0_1", + "CMT_TOP_SW2A1_4", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_IMUX27_1", + "CMT_PHASER_OUT_C_OCLK", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_IMUX23_9", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_IMUX30_6", + "CMT_TOP_NW4END1_9", + "CMT_TOP_IMUX39_2", + "CMT_TOP_EE4C0_6", + "CMT_PHASER_OUT_DB_DTSBUS0", + "CMT_TOP_IMUX10_8", + "CMT_TOP_WW4END3_0", + "CMT_TOP_WW4C2_1", + "CMT_PHY_CONTROL_OBURSTPENDING2", + "CMT_TOP_NW4END1_11", + "CMT_TOP_EE4C2_8", + "CMT_TOP_IMUX43_11", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_SW4A3_11", + "CMT_TOP_IMUX16_3", + "CMT_TOP_OCLK_8", + "CMT_TOP_NE2A0_6", + "CMT_TOP_WW2A3_2", + "CMT_TOP_LH2_2", + "CMT_TOP_CTRL1_6", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_EE4A0_8", + "CMT_TOP_SE4C1_3", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_IMUX8_5", + "CMT_TOP_IMUX9_1", + "CMT_TOP_WW4A0_9", + "CMT_TOP_EE4A3_8", + "CMT_TOP_IMUX37_5", + "CMT_TOP_IMUX11_10", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_IMUX44_2", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX28_6", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_IMUX40_10", + "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_MONITOR_N_4", + "CMT_PHY_CONTROL_TESTOUTPUT0", + "CMT_TOP_CLK0_1", + "CMT_TOP_SW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX23_1", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_OCLKDIV_6", + "CMT_PHASER_UP_PHASERREF_ABOVE1", + "CMT_TOP_WW2END1_6", + "CMT_TOP_SW2A0_1", + "CMT_TOP_CTRL1_3", + "CMT_TOP_IMUX10_7", + "CMT_TOP_NE4C2_8", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_IMUX6_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_NW2A3_4", + "CMT_TOP_WR1END2_9", + "CMT_TOP_IMUX27_8", + "CMT_PHASER_IN_CA_STG1REGR7", + "CMT_TOP_LH6_3", + "CMT_TOP_NE2A1_1", + "CMT_TOP_CLK0_9", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_BYP0_9", + "CMT_TOP_EE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_EE4BEG1_4", + "CMT_PHY_CONTROL_TESTSELECT1", + "CMT_TOP_WW2END1_1", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_ER1BEG0_3", + "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "CMT_TOP_WW4END0_2", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_EE2A0_4", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_FAN1_7", + "CMT_PHASER_REF_TESTIN2", + "CMT_TOP_WW4A3_3", + "CMT_PHASER_IN_CA_ENCALIBPHY0", + "CMT_TOP_NW4END3_2", + "CMT_TOP_SW4END2_1", + "CMT_TOP_EE4A3_3", + "CMT_TOP_EE4A1_0", + "CMT_TOP_SW4A2_9", + "CMT_TOP_LH3_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_IMUX32_6", + "CMT_TOP_IMUX41_0", + "CMT_TOP_WR1END3_4", + "CMT_TOP_SW2A1_11", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX11_7", + "CMT_PHASER_C_OCLK_TOIOI", + "CMT_TOP_SW2A2_5", + "CMT_TOP_FAN5_0", + "CMT_PHASER_IN_DB_TESTOUT2", + "CMT_TOP_WW2END2_7", + "CMT_TOP_NW4A2_10", + "CMT_TOP_SW4END1_8", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_IMUX17_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_WW2A1_8", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_IMUX4_10", + "CMT_TOP_FAN6_9", + "CMT_PHY_CONTROL_PHYCTLWD29", + "CMT_TOP_NW2A2_0", + "CMT_PHASER_IN_DB_STG1REGL5", + "CMT_TOP_IMUX11_2", + "CMT_TOP_IMUX1_9", + "CMT_TOP_WW2A3_9", + "CMT_TOP_WW4B3_11", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_WW4END2_3", + "CMT_TOP_BYP0_0", + "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "CMT_PHASER_REF_CLKOUT", + "CMT_PHASER_IN_CA_STG1REGL4", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_WW4END0_7", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_PHASER_IN_CA_TESTIN4", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_LH6_10", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_IMUX41_7", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_PHASER_OUT_CA_PHASEREFCLK", + "CMT_TOP_NE2A2_6", + "CMT_TOP_IMUX37_2", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WR1END1_7", + "CMT_TOP_IMUX14_9", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_IMUX7_2", + "CMT_TOP_FAN2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_PHASER_OUT_D_RDENABLE_TOFIFO", + "CMT_PHY_CONTROL_PHYCTLWD0", + "CMT_TOP_WW4A0_7", + "CMT_TOP_EE4C0_8", + "CMT_PHASER_OUT_CA_DQSBUS1", + "CMT_PHY_CONTROL_PHYCTLWD17", + "CMT_TOP_SE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_WR1END3_8", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_IMUX37_1", + "CMT_TOP_NW2A1_0", + "CMT_TOP_EL1BEG0_4", + "CMT_PHASER_UP_DQS_TO_PHASER_D", + "PLLOUT_CLK_FREQ_BB_REBUFIN1", + "CMT_TOP_WW4A1_4", + "CMT_TOP_NW2A2_3", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A2_6", + "CMT_TOP_EE4C0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_FAN3_11", + "CMT_TOP_SW4END0_0", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_NE4C3_11", + "CMT_TOP_IMUX37_6", + "CMT_TOP_BYP5_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_LH8_4", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SE4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_IMUX46_5", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_EL1BEG0_1", + "CMT_PHASER_IN_CA_FREQREFCLK", + "CMT_TOP_LH8_8", + "CMT_TOP_NE4C3_9", + "CMT_TOP_WW4B1_1", + "CMT_TOP_BYP2_9", + "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "CMT_TOP_IMUX26_10", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_SE4BEG3_2", + "CMT_PHY_CONTROL_TESTINPUT10", + "CMT_PHASER_OUT_DB_COARSEENABLE", + "CMT_TOP_IMUX2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_IMUX36_4", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SW2A0_3", + "CMT_PHASER_OUT_CA_TESTIN6", + "CMT_TOP_EE4A1_10", + "CMT_TOP_SW2A3_8", + "CMT_TOP_WW2A2_5", + "CMT_TOP_IMUX24_11", + "CMT_TOP_SW2A2_9", + "CMT_TOP_SW4A0_6", + "CMT_TOP_IMUX38_6", + "CMT_TOP_WR1END0_5", + "CMT_TOP_IMUX4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_IMUX19_8", + "CMT_TOP_CTRL0_11", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_IMUX36_5", + "CMT_PHASER_IN_DB_RANKSEL0", + "CMT_TOP_WW2A0_3", + "CMT_TOP_LH10_5", + "CMT_TOP_NE4C3_3", + "CMT_TOP_FAN7_2", + "CMT_TOP_IMUX7_10", + "CMT_PHASER_IN_CA_STG1REGL6", + "CMT_TOP_WW4B1_11", + "CMT_TOP_BYP6_1", + "CMT_TOP_WL1END2_1", + "CMT_TOP_SW4A0_2", + "CMT_TOP_IMUX10_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_OCLK_10", + "CMT_TOP_LH5_2", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_PHASERREF_PHASERIN_D", + "CMT_TOP_SW2A2_6", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_NW4END3_6", + "CMT_TOP_NW4END3_8", + "CMT_TOP_WL1END0_7", + "CMT_TOP_IMUX10_11", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX9_7", + "CMT_TOP_BYP5_7", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "CMT_TOP_SW2A1_6", + "CMT_TOP_IMUX18_11", + "CMT_PHASER_IN_CA_STG1READ", + "CMT_TOP_IMUX37_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_EE4B2_8", + "CMT_TOP_WW2A1_10", + "CMT_TOP_IMUX42_5", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_PHASER_IN_DB_FREQREFCLK", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LH8_10", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_IMUX24_5", + "CMT_PHASER_OUT_DB_SCANCLK", + "CMT_TOP_NW2A2_10", + "CMT_TOP_ER1BEG2_8", + "CMT_PHASER_OUT_CA_TESTOUT0", + "CMT_PHASER_REF_TMUXOUT_TOHCLK", + "CMT_TOP_SW2A2_8", + "CMT_TOP_EE4B2_6", + "CMT_TOP_FAN5_6", + "CMT_PHASER_REF_TESTOUT3", + "CMT_TOP_FAN3_3", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_EE2A1_3", + "CMT_PHASER_OUT_DB_TESTIN1", + "CMT_PHY_CONTROL_PHYCTLWD1", + "CMT_TOP_IMUX24_9", + "CMT_TOP_SE2A2_2", + "CMT_PHASER_OUT_CA_TESTIN11", + "CMT_TOP_IMUX25_10", + "CMT_PHASER_OUT_CA_DTSBUS0", + "CMT_TOP_SE4C3_0", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_EE2A1_7", + "CMT_TOP_IMUX45_6", + "CMT_TOP_SW4END0_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX3_8", + "CMT_PHASER_OUT_DB_ENCALIB1", + "CMT_TOP_WW2END1_9", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_LH6_8", + "CMT_TOP_OCLK_11", + "CMT_TOP_BYP1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_SW4A1_4", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX46_6", + "CMT_PHASER_IN_DB_TESTIN2", + "CMT_PHY_CONTROL_INBURSTPENDING0", + "CMT_TOP_IMUX40_9", + "CMT_TOP_IMUX25_11", + "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "CMT_TOP_LH10_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_WW4END3_3", + "CMT_TOP_WW4B3_2", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_FAN3_0", + "CMT_PHY_CONTROL_TESTINPUT5", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_IMUX32_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_EE4A0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_PHY_CONTROL_REFDLLLOCK", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_FAN0_11", + "CMT_TOP_SE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_IMUX44_4", + "CMT_TOP_SW4A2_11", + "CMT_PHASER_REF_TMUXOUT", + "CMT_TOP_SW4END0_9", + "CMT_TOP_EE4C1_5", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_IMUX29_4", + "CMT_PHASER_IN_CA_ICLKDIV", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX32_0", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_SW4END2_3", + "CMT_TOP_BYP4_2", + "CMT_PHASER_IN_DB_RANKSELPHY0", + "CMT_TOP_WL1END3_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_FAN5_4", + "CMT_TOP_EE2A2_2", + "CMT_TOP_EE4A2_1", + "CMT_TOP_EE2A2_11", + "CMT_TOP_NW4A2_11", + "CMT_TOP_NW4END3_10", + "CMT_TOP_WW4END0_8", + "CMT_TOP_LH11_8", + "CMT_TOP_IMUX45_5", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WR1END0_6", + "CMT_TOP_IMUX3_1", + "CMT_TOP_WW4END3_1", + "CMT_PHY_CONTROL_INRANKA1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_IMUX16_2", + "CMT_TOP_IMUX34_10", + "CMT_TOP_FAN7_3", + "CMT_TOP_FAN4_4", + "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "CMT_TOP_LH4_0", + "CMT_TOP_NE4BEG2_0", + "CMT_PHASER_UP_DQS_TO_PHASER_C", + "CMT_TOP_FAN3_9", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_IMUX22_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_EE4C3_6", + "CMT_PHY_CONTROL_TESTINPUT12", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_PHASER_IN_C_WRCLK_TOFIFO", + "CMT_TOP_BYP1_10", + "CMT_TOP_FAN7_0", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_FAN2_9", + "CMT_PHASER_OUT_DB_TESTIN5", + "CMT_TOP_WW2A0_11", + "CMT_TOP_SW4A1_2", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_IMUX4_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_SE4BEG1_11", + "CMT_TOP_IMUX26_2", + "CMT_PHY_CONTROL_PHYCTLWD2", + "CMT_TOP_BYP5_11", + "CMT_TOP_BYP2_10", + "CMT_TOP_FAN1_8", + "CMT_TOP_LH8_11", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_IMUX11_8", + "CMT_TOP_SE4C2_10", + "CMT_TOP_ER1BEG3_4", + "CMT_PHY_CONTROL_PHYCTLWD28", + "CMT_TOP_IMUX5_6", + "CMT_TOP_IMUX38_0", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_LH2_10", + "CMT_TOP_CLK1_7", + "CMT_PHASER_OUT_CA_TESTIN0", + "CMT_TOP_WW4B3_1", + "CMT_TOP_EE4A0_10", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_IMUX16_5", + "CMT_TOP_CLK1_4", + "CMT_TOP_LH8_3", + "CMT_TOP_IMUX22_11", + "CMT_PHASER_OUT_DB_TESTIN3", + "CMT_TOP_WW2END2_0", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_PHASER_IN_DB_DQSFOUND", + "CMT_TOP_IMUX45_2", + "CMT_PHASER_IN_DB_FINEOVERFLOW", + "CMT_PHY_CONTROL_TESTOUTPUT15", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_NE4C0_11", + "CMT_TOP_EE4B1_2", + "CMT_TOP_IMUX15_10", + "CMT_TOP_WW4C0_0", + "CMT_TOP_SW2A1_7", + "CMT_TOP_BYP2_4", + "CMT_PHASER_IN_DB_TESTIN11", + "CMT_PHY_CONTROL_TESTINPUT7", + "CMT_TOP_EE4B3_1", + "CMT_TOP_SE4C3_3", + "CMT_TOP_WW4END1_9", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_SW4END1_4", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_IMUX34_7", + "CMT_TOP_WW2A0_7", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_IMUX27_4", + "CMT_TOP_WL1END2_5", + "CMT_TOP_OCLK_1", + "CMT_TOP_NW4END0_2", + "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "CMT_TOP_EE2A1_5", + "CMT_PHASER_OUT_DB_TESTOUT2", + "CMT_TOP_FAN4_2", + "CMT_TOP_CTRL1_11", + "CMT_TOP_WW4C3_8", + "CMT_TOP_NW4END1_1", + "CMT_PHASER_IN_DB_FINEENABLE", + "CMT_TOP_FAN3_1", + "CMT_TOP_IMUX45_9", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_WR1END3_9", + "CMT_TOP_SW4END2_11", + "CMT_TOP_SE2A2_5", + "CMT_TOP_WR1END2_6", + "CMT_TOP_SE4BEG1_4", + "CMT_PHY_CONTROL_TESTOUTPUT8", + "CMT_TOP_FAN2_7", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW2END2_11", + "CMT_PHY_CONTROL_PHYCTLWD27", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_SW4A3_1", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX42_6", + "CMT_PHASER_IN_CA_SYNCIN", + "CMT_TOP_EE4B1_1", + "CMT_TOP_BYP0_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_CLK1_11", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_EE4C3_11", + "CMT_TOP_IMUX32_10", + "CMT_TOP_EE2BEG1_8", + "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "CMT_TOP_NW4A0_4", + "CMT_PHASER_OUT_D_OCLK", + "CMT_PHY_CONTROL_TESTOUTPUT3", + "CMT_TOP_SW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_NW4END2_8", + "CMT_TOP_EE2A0_10", + "CMT_TOP_EE2A3_9", + "CMT_PHASER_IN_CA_TESTIN8", + "CMT_TOP_SW2A1_1", + "CMT_TOP_EE4B2_4", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX18_0", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_BYP6_4", + "CMT_TOP_NW4END1_6", + "CMT_PHASER_OUT_DB_TESTIN13", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_LH7_4", + "CMT_TOP_IMUX23_0", + "CMT_PHASER_IN_DB_RCLK", + "CMT_TOP_IMUX43_8", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX21_4", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "CMT_TOP_IMUX21_2", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_EE4A2_9", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE4B0_5", + "CMT_TOP_IMUX47_10", + "CMT_PHY_CONTROL_PHYCTLWD26", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_6", + "CMT_PHASER_IN_DB_EDGEADV", + "CMT_TOP_WW4C0_1", + "CMT_TOP_WW2A3_0", + "CMT_TOP_FAN7_1", + "CMT_TOP_NW2A1_3", + "CMT_PHASER_IN_CA_EDGEADV", + "CMT_TOP_NE4BEG0_9", + "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "CMT_TOP_EE2BEG2_10", + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE4BEG3_3", + "CMT_PHASER_IN_CA_STG1REGR5", + "CMT_PHY_CONTROL_PHYCTLWD22", + "CMT_TOP_LH1_10", + "CMT_PHASER_IN_DB_STG1OVERFLOW", + "CMT_TOP_EE4B0_10", + "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "CMT_TOP_SE2A3_2", + "CMT_TOP_IMUX16_6", + "CMT_TOP_IMUX1_5", + "CMT_PHASER_IN_DB_RST", + "CMT_PHASER_IN_DB_STG1REGL0", + "CMT_TOP_SE4C1_4", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_NW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_EE4B3_5", + "CMT_TOP_IMUX26_7", + "CMT_TOP_NE4C1_0", + "CMT_TOP_EE2A3_8", + "CMT_TOP_IMUX45_11", + "CMT_PHASER_IN_DB_ENCALIBPHY0", + "CMT_TOP_WW4B2_4", + "CMT_TOP_IMUX40_0", + "CMT_TOP_IMUX14_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_EE4A0_2", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE2BEG1_6", + "CMT_R_TOP_UPPER_B_CLKPLL4", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_NW4END3_11", + "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_IMUX8_7", + "CMT_TOP_WW2END0_4", + "CMT_TOP_SW4A1_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_LH10_7", + "CMT_TOP_EE4C2_3", + "CMT_R_TOP_UPPER_B_CLKPLL5", + "CMT_PHASER_IN_CA_TESTIN9", + "CMT_TOP_SE2A3_9", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "CMT_TOP_ICLK_11", + "CMT_PHY_CONTROL_PHYCTLWD10", + "CMT_TOP_EE2A1_11", + "CMT_TOP_SE2A1_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_WR1END0_0", + "CMT_TOP_WW2A1_9", + "CMT_TOP_FAN1_11", + "CMT_TOP_IMUX18_4", + "CMT_TOP_WL1END1_5", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_NE2A2_3", + "CMT_PHASER_IN_CA_FINEENABLE", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_IMUX24_1", + "CMT_TOP_WW4END1_3", + "CMT_TOP_WW2END2_6", + "CMT_TOP_WW2A2_11", + "CMT_TOP_SW2A0_10", + "CMT_PHASER_OUT_DB_RST", + "CMT_TOP_EE2A3_0", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_WW2A3_7", + "CMT_TOP_WL1END2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_SW2A0_6", + "CMT_TOP_IMUX13_11", + "CMT_TOP_NW4A3_9", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_NW2A0_1", + "CMT_TOP_IMUX6_0", + "CMT_TOP_LH1_11", + "CMT_TOP_NW2A2_6", + "CMT_TOP_CTRL0_0", + "CMT_TOP_WR1END1_3", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX43_0", + "CMT_TOP_SE2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4C3_0", + "CMT_TOP_LH11_1", + "CMT_TOP_SW2A1_8", + "CMT_TOP_EE4C3_4", + "CMT_TOP_NW4A3_11", + "CMT_TOP_ER1BEG3_8", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN7_4", + "CMT_TOP_NW4END0_4", + "CMT_TOP_FAN1_6", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_IMUX22_10", + "CMT_TOP_WW4B2_5", + "CMT_PHASER_OUT_DB_SCANMODEB", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C1_4", + "CMT_TOP_IMUX20_4", + "CMT_TOP_WW2A2_1", + "CMT_PHASER_OUT_CA_SCANOUT", + "CMT_TOP_WR1END1_11", + "CMT_PHASER_OUT_DB_DIVIDERST", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WR1END3_10", + "CMT_TOP_WW4A1_6", + "CMT_TOP_BYP7_11", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_PHY_CONTROL_IBURSTPENDING3", + "CMT_TOP_SE2A1_3", + "CMT_TOP_WW4B0_9", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX0_4", + "CMT_TOP_SE2A3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_IMUX20_3", + "CMT_TOP_CTRL1_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EE4A2_5", + "CMT_TOP_SE4C1_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_NW4END0_0", + "CMT_TOP_NW4A3_10", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX12_2", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_IMUX43_10", + "CMT_TOP_NW4A3_8", + "CMT_TOP_WW4B0_2", + "CMT_TOP_NE2A0_7", + "CMT_TOP_IMUX34_5", + "CMT_PHASER_IN_CA_TESTIN11", + "CMT_PHASER_IN_DB_TESTIN1", + "CMT_PHASER_OUT_CA_SCANMODEB", + "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "CMT_TOP_EE4C2_5", + "CMT_TOP_WL1END2_2", + "CMT_TOP_IMUX6_3", + "CMT_PHASER_OUT_C_OCLKDIV", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_IMUX35_7", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_IMUX28_10", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_IMUX2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_CTRL0_10", + "CMT_TOP_WW4END2_2", + "CMT_TOP_WL1END0_8", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_IMUX47_6", + "CMT_TOP_IMUX23_2", + "CMT_TOP_WL1END0_9", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_IMUX39_6", + "CMT_TOP_EE4C0_10", + "CMT_TOP_IMUX6_4", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_IMUX12_3", + "CMT_TOP_LH8_2", + "CMT_TOP_IMUX36_9", + "CMT_TOP_BYP2_5", + "CMT_TOP_NW2A0_10", + "CMT_PHASER_IN_D_WRCLK_TOFIFO", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX38_8", + "CMT_TOP_IMUX0_6", + "CMT_TOP_NE4BEG3_11", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SE2A0_8", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NE2A0_1", + "CMT_TOP_IMUX31_4", + "CMT_TOP_NE2A3_9", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX5_1", + "CMT_TOP_IMUX47_2", + "CMT_TOP_LH12_1", + "CMT_TOP_SW2A3_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_WW2END3_6", + "CMT_TOP_NW2A0_8", + "CMT_PHASER_UP_PHASERREF_BELOW0", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_IMUX44_3", + "CMT_TOP_LH3_4", + "CMT_TOP_EE2A2_1", + "CMT_TOP_WW4A2_3", + "CMT_TOP_NW2A3_2", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX39_8", + "CMT_TOP_SW4END2_7", + "CMT_TOP_FAN2_4", + "CMT_TOP_EE4A1_6", + "CMT_TOP_EE4B1_3", + "CMT_TOP_WW2A2_9", + "CMT_TOP_IMUX42_10", + "CMT_PHASER_IN_CA_STG1REGL1", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_WW4END0_1", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE4B1_0", + "CMT_TOP_IMUX34_11", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_ICLKDIV_0", + "CMT_PHASER_IN_CA_SCANENB", + "CMT_TOP_IMUX10_3", + "CMT_TOP_WL1END3_2", + "CMT_PHASER_IN_CA_ENCALIBPHY1", + "CMT_TOP_NW4A2_8", + "CMT_TOP_IMUX35_5", + "CMT_TOP_WW4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_NE4C3_2", + "CMT_PHY_CONTROL_INRANKD0", + "CMT_TOP_NE2A3_8", + "CMT_TOP_WW4END3_4", + "CMT_TOP_LH1_1", + "CMT_PHASERD_DQSBUS1", + "CMT_TOP_CTRL1_5", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_EE2BEG3_10", + "CMT_PHY_CONTROL_TESTINPUT4", + "CMT_TOP_LH7_9", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_CLK0_8", + "CMT_TOP_NE2A0_5", + "CMT_TOP_SW4END2_6", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_EE4C3_5", + "CMT_TOP_IMUX8_8", + "CMT_TOP_EE2BEG3_1", + "CMT_PHASERTOP_PHYCTLEMPTY", + "CMT_TOP_EE2A2_4", + "CMT_TOP_NE2A3_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "CMT_TOP_IMUX13_1", + "CMT_PHASER_OUT_CA_ENCALIB1", + "CMT_TOP_WW2END0_3", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_PHASER_IN_DB_RANKSEL1", + "CMT_TOP_EE4A2_0", + "CMT_TOP_EE4C1_3", + "CMT_PHY_CONTROL_OBURSTPENDING1", + "CMT_PHASER_OUT_CA_OCLK", + "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_EE4B2_11", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_NE4C2_9", + "CMT_TOP_NW2A2_4", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX37_3", + "CMT_TOP_IMUX37_8", + "CMT_TOP_ICLKDIV_4", + "CMT_PHASERREF_PHASEROUT_D", + "CMT_TOP_CTRL1_2", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_EE4B0_0", + "CMT_TOP_IMUX18_9", + "CMT_TOP_SE2A0_0", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_EE2A1_10", + "CMT_PHY_CONTROL_IRANKD1", + "CMT_PHASER_C_ICLK_TOIOI", + "CMT_TOP_NW4A2_4", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_IMUX3_2", + "CMT_TOP_WW4A3_9", + "CMT_TOP_SE2A1_7", + "CMT_TOP_WW4END1_0", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_NW4END2_6", + "CMT_PHASER_IN_CA_SCANMODEB", + "CMT_TOP_IMUX34_1", + "CMT_TOP_LH6_9", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW4A2_1", + "CMT_TOP_SW4A2_4", + "CMT_PHASER_OUT_CA_MEMREFCLK", + "CMT_TOP_NE4C2_11", + "CMT_TOP_WW4END1_10", + "CMT_TOP_LH9_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_NE4C3_6", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WW2END3_1", + "CMT_TOP_BYP4_3", + "CMT_PHY_CONTROL_IRANKD0", + "CMT_TOP_WW2END2_10", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "CMT_PHASER_OUT_CA_TESTIN9", + "CMT_TOP_SE2A0_7", + "CMT_TOP_IMUX35_11", + "CMT_TOP_WW2END2_2", + "CMT_TOP_BYP7_5", + "CMT_TOP_SW4END0_11", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX0_8", + "CMT_TOP_SW2A1_2", + "CMT_TOP_EE4B1_6", + "CMT_TOP_IMUX20_5", + "CMT_TOP_WW2END0_10", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_BYP5_0", + "CMT_TOP_IMUX32_9", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX38_10", + "CMT_PHASER_IN_DB_STG1LOAD", + "CMT_TOP_LH1_4", + "CMT_PHASER_OUT_DB_TESTIN6", + "CMT_TOP_NW4A0_6", + "CMT_TOP_WW4END3_8", + "CMT_FREQ_PHASER_REFMUX_1", + "CMT_TOP_EE4C2_2", + "CMT_PHASER_IN_DB_STG1REGR7", + "CMT_TOP_CLK1_10", + "CMT_TOP_WL1END3_11", + "CMT_TOP_WW2END3_4", + "CMT_PHASER_IN_DB_FINEINC", + "CMT_TOP_WW4C1_8", + "CMT_TOP_IMUX39_10", + "CMT_PHASER_IN_DB_SYNCIN", + "CMT_TOP_WR1END1_8", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_WW4END3_10", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4B3_6", + "CMT_TOP_EE4C3_10", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_PHASER_IN_DB_SCANCLK", + "CMT_TOP_EE4B3_7", + "CMT_R_TOP_UPPER_B_CLKPLL2", + "CMT_TOP_NW4END0_7", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SW4A1_10", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX22_7", + "CMT_TOP_NW2A2_5", + "CMT_TOP_LH7_3", + "CMT_TOP_IMUX20_1", + "CMT_TOP_WW4B1_3", + "CMT_TOP_FAN5_8", + "CMT_TOP_SE2A1_9", + "CMT_TOP_OCLK_4", + "CMT_TOP_SE4C2_0", + "CMT_PHASER_UP_PHASERREF_ABOVE0", + "CMT_TOP_NE2A0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_WW2A0_2", + "CMT_PHY_CONTROL_IRANKC1", + "CMT_PHASER_IN_DB_PHASELOCKED", + "CMT_TOP_IMUX44_11", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_WW4A1_5", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX17_8", + "CMT_TOP_IMUX43_2", + "CMT_TOP_LH12_5", + "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "CMT_PHASER_C_OCLK90_TOIOI", + "CMT_TOP_IMUX41_11", + "CMT_PHASER_OUT_CA_SYNCIN", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_IMUX46_1", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_EE4C2_6", + "CMT_TOP_WW4C3_1", + "CMT_TOP_ICLK_1", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_IMUX42_1", + "CMT_TOP_BYP7_6", + "CMT_TOP_NW4END1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_NW4A3_2", + "CMT_TOP_SW4A0_5", + "CMT_TOP_IMUX4_6", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_WW4END0_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_IMUX3_6", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_WW2A3_1", + "CMT_PHY_CONTROL_TESTOUTPUT1", + "CMT_TOP_IMUX35_3", + "CMT_TOP_SW4END0_10", + "CMT_TOP_LH12_2", + "CMT_TOP_IMUX0_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_EE2BEG3_11", + "CMT_PHASER_IN_CA_STG1REGL0", + "CMT_TOP_WW4END2_6", + "CMT_PHASER_IN_D_ICLK", + "CMT_TOP_LH11_7", + "CMT_TOP_SW4END3_3", + "CMT_PHASER_OUT_CA_TESTIN14", + "CMT_PHASERD_DTSBUS0", + "CMT_TOP_NW4A1_7", + "CMT_TOP_WW2A3_5", + "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_IMUX19_6", + "CMT_TOP_FAN4_8", + "CMT_TOP_IMUX34_3", + "CMT_TOP_EE2A2_3", + "CMT_TOP_WW4END1_11", + "CMT_PHASER_IN_DB_STG1REGR3", + "CMT_TOP_CLK0_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4C3_7", + "CMT_TOP_WW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_FREQ_BB_PREF_IN1", + "CMT_TOP_IMUX35_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_IMUX10_0", + "CMT_TOP_LH11_3", + "CMT_TOP_SE2A0_9", + "CMT_TOP_WL1END3_7", + "CMT_TOP_IMUX34_8", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WR1END3_3", + "CMT_TOP_IMUX46_4", + "CMT_TOP_SE2A2_10", + "CMT_TOP_WW4C2_4", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_IMUX22_0", + "CMT_TOP_IMUX9_11", + "CMT_TOP_WW4A2_9", + "CMT_TOP_SE4C1_0", + "CMT_TOP_IMUX14_5", + "CMT_TOP_WL1END2_9", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_EE4C1_1", + "CMT_TOP_NW4A0_11", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX13_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_SE4C2_3", + "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_NE4C0_3", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX27_5", + "CMT_TOP_OCLK_0", + "CMT_TOP_LH7_8", + "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "CMT_TOP_IMUX7_8", + "CMT_TOP_ICLK_0", + "CMT_TOP_WW2END2_3", + "CMT_TOP_WR1END0_10", + "CMT_PHASER_OUT_CA_CTSBUS1", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END1_5", + "CMT_TOP_IMUX44_6", + "CMT_PHASER_IN_CA_MEMREFCLK", + "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "CMT_TOP_IMUX22_3", + "CMT_TOP_NE4C2_4", + "CMT_PHASER_IN_CA_ENSTG1", + "CMT_TOP_WL1END1_2", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_PHASER_IN_DB_ENCALIBPHY1", + "CMT_TOP_SE4C3_6", + "CMT_PHY_CONTROL_INBURSTPENDING3", + "CMT_TOP_LH9_10", + "CMT_TOP_NW2A1_10", + "CMT_TOP_SW4A3_8", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW2A2_0", + "CMT_TOP_IMUX13_3", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX18_7", + "CMT_PHASER_OUT_CA_RST", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX28_4", + "CMT_PHASER_IN_CA_RANKSEL1", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH1_8", + "CMT_TOP_LH10_10", + "CMT_TOP_IMUX42_3", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_WL1END1_1", + "CMT_FREQ_PHASER_REFMUX_0", + "CMT_PHY_CONTROL_RESET", + "CMT_TOP_IMUX3_10", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_WW2END2_8", + "CMT_TOP_LH7_1", + "CMT_TOP_EE2A0_8", + "CMT_TOP_SW2A3_5", + "CMT_TOP_IMUX31_11", + "CMT_PHASER_OUT_CA_TESTIN13", + "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "CMT_PHASERD_CTSBUS0", + "CMT_PHY_CONTROL_TESTSELECT2", + "CMT_TOP_IMUX19_3", + "CMT_TOP_FAN0_7", + "PLLOUT_CLK_FREQ_BB_REBUFOUT3", + "CMT_TOP_WW2END1_4", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_NW4END3_7", + "CMT_PHASER_REF_TESTIN7", + "CMT_TOP_CLK1_2", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_IMUX34_9", + "CMT_TOP_EE4B0_6", + "CMT_PHASER_OUT_DB_OCLKDELAYED", + "CMT_TOP_EE4B2_5", + "CMT_TOP_IMUX42_2", + "CMT_PHASER_OUT_DB_FREQREFCLK", + "CMT_TOP_WW4C2_9", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_WW2A2_2", + "CMT_TOP_SW4A2_5", + "CMT_TOP_NE2A3_2", + "CMT_PHASER_OUT_CA_SCANENB", + "CMT_TOP_IMUX43_1", + "CMT_PHASER_IN_CA_SCANIN", + "CMT_TOP_WW4END2_10", + "CMT_TOP_EE4C1_4", + "CMT_TOP_IMUX44_9", + "CMT_PHASER_IN_C_ICLK", + "CMT_TOP_WW4B1_6", + "CMT_TOP_NW4A1_11", + "CMT_TOP_IMUX42_0", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_IMUX24_7", + "CMT_PHY_CONTROL_INBURSTPENDING2", + "CMT_TOP_IMUX47_4", + "CMT_TOP_NE2A1_2", + "CMT_TOP_BYP5_2", + "CMT_TOP_IMUX39_4", + "CMT_TOP_FAN7_8", + "CMT_TOP_IMUX40_8", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_SW2A1_10", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_IMUX33_0", + "CMT_TOP_NE4C1_1", + "CMT_TOP_NE4C3_8", + "CMT_TOP_EE4A3_10", + "CMT_TOP_IMUX28_3", + "CMT_TOP_IMUX1_4", + "CMT_TOP_IMUX13_4", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_EE4B1_8", + "CMT_TOP_SW4A1_9", + "CMT_TOP_SE4C2_8", + "CMT_TOP_LH1_5", + "CMT_TOP_WW4END3_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_WW2END3_3", + "CMT_PHASER_OUT_CA_DIVIDERST", + "CMT_PHASER_IN_CA_STG1REGL7", + "CMT_PHASER_OUT_DB_TESTIN14", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_NE4C0_2", + "CMT_TOP_FAN6_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_IMUX19_10", + "CMT_TOP_ER1BEG0_5", + "CMT_TOP_LH7_5", + "CMT_TOP_IMUX19_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_FAN0_2", + "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "CMT_TOP_IMUX27_3", + "CMT_TOP_IMUX47_5", + "CMT_TOP_FAN6_0", + "CMT_TOP_IMUX24_0", + "CMT_TOP_IMUX26_0", + "CMT_TOP_WR1END2_3", + "CMT_PHY_CONTROL_PHYCTLWD6", + "CMT_TOP_WR1END1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_PHY_CONTROL_ECALIB0", + "CMT_TOP_NE4C0_6", + "CMT_TOP_EE4C0_0", + "CMT_TOP_EE2A3_10", + "CMT_PHY_CONTROL_PHYCTLWD7", + "CMT_TOP_SE4C1_8", + "CMT_PHASER_IN_DB_STG1REGR1", + "CMT_TOP_EE2A0_2", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_IMUX47_9", + "CMT_TOP_SE4C1_7", + "CMT_TOP_FAN0_10", + "CMT_TOP_IMUX45_7", + "CMT_TOP_EE2A3_4", + "CMT_TOP_IMUX13_0", + "CMT_TOP_ER1BEG2_10", + "CMT_PHASER_OUT_CA_FREQREFCLK", + "CMT_TOP_WW2END1_10", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_IMUX29_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_IMUX33_9", + "CMT_PHASER_OUT_DB_ENCALIB0", + "CMT_TOP_SW4END3_1", + "CMT_TOP_IMUX5_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_NW4A1_9", + "CMT_PHASER_IN_CA_PHASEREFCLK", + "CMT_TOP_WW2END0_11", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4C0_8", + "CMT_TOP_IMUX16_10", + "CMT_PHASER_OUT_D_OCLKDIV", + "CMT_PHASER_IN_DB_PHASEREFCLK", + "CMT_PHASER_IN_CA_TESTIN5", + "CMT_TOP_IMUX15_4", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_LH10_11", + "CMT_PHY_CONTROL_IBURSTPENDING0", + "CMT_PHASER_IN_DB_SCANIN", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_NW2A2_9", + "CMT_PHASER_OUT_DB_MEMREFCLK", + "CMT_TOP_EE4B3_11", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_WW4A1_1", + "CMT_TOP_EE2A1_0", + "CMT_TOP_LH9_9", + "CMT_TOP_EE4B0_1", + "CMT_TOP_SE4BEG3_4", + "CMT_PHASER_IN_DB_SCANENB", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_PHASER_IN_CA_TESTIN2", + "CMT_TOP_SE2A0_10", + "CMT_PHASER_OUT_DB_SYNCIN", + "CMT_TOP_NE4C2_3", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_CLK0_3", + "CMT_TOP_IMUX14_1", + "CMT_PHASERD_CTSBUS1", + "CMT_PHY_CONTROL_TESTSELECT0", + "CMT_PHASER_OUT_D_RDCLK_TOFIFO", + "CMT_TOP_LH8_9", + "CMT_TOP_WW2A3_11", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_IMUX2_7", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW4C3_6", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_EE4C0_4", + "CMT_TOP_IMUX28_8", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LH2_6", + "CMT_PHY_CONTROL_TESTOUTPUT13", + "CMT_TOP_IMUX11_9", + "CMT_TOP_WW4A1_11", + "CMT_PHASER_REF_TESTOUT1", + "CMT_PHASER_OUT_CA_BURSTPENDING", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_BYP4_8", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_EE4C1_6", + "CMT_PHASER_OUT_DB_FINEINC", + "CMT_PHY_CONTROL_TESTINPUT6", + "CMT_TOP_NW2A0_4", + "CMT_TOP_NW4END3_9", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LH12_7", + "CMT_TOP_WW2END1_7", + "CMT_PHY_CONTROL_PHYCTLWD24", + "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "CMT_TOP_LH6_2", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX45_8", + "CMT_PHASER_REF_CLKOUT_TOHCLK", + "CMT_FREQ_BB_PREF_IN0", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_EE2A0_3", + "CMT_TOP_WW4B0_10", + "CMT_TOP_IMUX33_4", + "CMT_TOP_BYP1_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_WL1END0_11", + "CMT_PHASER_IN_CA_STG1REGR1", + "CMT_TOP_SW2A0_5", + "CMT_TOP_EE4C3_8", + "CMT_PHASER_REF_TESTIN1", + "CMT_TOP_IMUX35_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_WW2A3_10", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_NW4END1_7", + "CMT_TOP_IMUX36_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_EE4BEG1_3", + "CMT_PHY_CONTROL_PHYCTLWD4", + "CMT_TOP_SW4END3_2", + "CMT_TOP_WL1END0_5", + "PLL_CLK_FREQBB_REBUFOUT0", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_NE4C0_1", + "CMT_PHY_CONTROL_IRANKA0", + "CMT_TOP_IMUX11_1", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "CMT_TOP_SW2A1_5", + "CMT_TOP_IMUX33_6", + "CMT_PHY_CONTROL_PHYCTLWD15", + "CMT_TOP_EE4C2_9", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_EE4B3_3", + "CMT_TOP_WW4A1_0", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_WW2END2_1", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_WW4END0_11", + "CMT_PHY_CONTROL_PHYCTLFULL", + "CMT_TOP_IMUX25_4", + "CMT_TOP_IMUX2_9", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_SW4END1_0", + "CMT_TOP_EE2A1_1", + "CMT_TOP_SE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_EE4A3_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_SE4C2_11", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_PHASER_OUT_CA_FINEINC", + "CMT_TOP_BYP2_11", + "CMT_TOP_BYP1_1", + "CMT_TOP_LH11_6", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_NW2A0_11", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WR1END0_3", + "CMT_TOP_WW4B3_5", + "CMT_TOP_EL1BEG1_6", + "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "CMT_TOP_IMUX31_9", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_PHASER_OUT_CA_ENCALIB0", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_BYP6_0", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WR1END1_6", + "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "CMT_TOP_SE4C0_2", + "CMT_TOP_LH11_10", + "CMT_PHASER_OUT_CA_TESTOUT3", + "CMT_TOP_EE4A2_8", + "CMT_TOP_SE2A1_1", + "CMT_TOP_NW4END1_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_IMUX31_3", + "CMT_TOP_EE4C1_8", + "CMT_TOP_IMUX20_11", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_WW4END1_4", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_IMUX9_10", + "CMT_TOP_SW4A1_5", + "CMT_TOP_SE4C0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_SW2A1_0", + "CMT_TOP_SE4BEG1_7", + "CMT_PHASER_IN_CA_ISERDESRST", + "CMT_TOP_EE2A0_0", + "CMT_TOP_CTRL1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_WW4A1_2", + "CMT_TOP_WW4C3_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_IMUX5_9", + "CMT_PHY_CONTROL_TESTOUTPUT12", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_IMUX38_2", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_IMUX1_11", + "CMT_TOP_IMUX35_10", + "CMT_TOP_EE4A3_0", + "CMT_TOP_WW2A3_6", + "CMT_TOP_NW2A3_1", + "CMT_TOP_BYP3_5", + "CMT_TOP_BYP6_11", + "CMT_TOP_SW2A3_4", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_IMUX42_8", + "CMT_PHY_CONTROL_TESTINPUT14", + "CMT_TOP_IMUX30_2", + "CMT_TOP_IMUX45_1", + "CMT_TOP_WW4B3_0", + "CMT_TOP_LH3_6", + "CMT_TOP_IMUX12_0", + "CMT_TOP_EE2BEG2_9", + "CMT_PHY_CONTROL_PHYCTLWD20", + "CMT_TOP_IMUX11_0", + "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "CMT_TOP_IMUX24_3", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX19_9", + "CMT_PHASER_REF_TESTIN0", + "CMT_TOP_IMUX24_2", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_LH3_0", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_WW2A1_1", + "CMT_TOP_LH2_0", + "CMT_PHASER_IN_CA_STG1REGL8", + "CMT_TOP_IMUX22_2", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX2_8", + "CMT_TOP_IMUX22_9", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_PHASER_IN_CA_TESTIN7", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_ICLK_10", + "CMT_TOP_SE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_LH2_11", + "CMT_TOP_SW4END1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_TOP_WL1END1_4", + "CMT_TOP_IMUX37_9", + "CMT_TOP_EE2A2_10", + "CMT_TOP_WW4C3_9", + "CMT_PHASER_REF_TESTOUT7", + "CMT_PHY_CONTROL_TESTOUTPUT10", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE4B0_11", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH7_11", + "CMT_TOP_EE4A0_7", + "CMT_TOP_EE4A0_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_EE4B1_5", + "CMT_PHASER_IN_DB_STG1REGL6", + "CMT_PHY_CONTROL_TESTOUTPUT11", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_IMUX19_1", + "CMT_TOP_ER1BEG3_6", + "CMT_PHASER_REF_TESTIN6", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_WW4B2_10", + "CMT_TOP_IMUX17_3", + "CMT_PHASERTOP_PHYCTLMSTREMPTY", + "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "CMT_PHY_CONTROL_INRANKD1", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_IMUX36_0", + "CMT_TOP_WW2A2_7", + "CMT_TOP_IMUX33_8", + "CMT_TOP_SW4END2_8", + "CMT_TOP_NE4C3_7", + "CMT_TOP_CLK1_9", + "CMT_TOP_WW4C2_7", + "CMT_PHASER_IN_DB_SCANOUT", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_NW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW4END0_5", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_BYP3_2", + "CMT_PHASER_IN_CA_FINEOVERFLOW", + "CMT_TOP_NW4END2_1", + "CMT_PHASER_IN_CA_STG1REGR0", + "CMT_TOP_IMUX15_0", + "CMT_TOP_IMUX45_3", + "CMT_TOP_NW4A1_10", + "CMT_TOP_IMUX33_10", + "CMT_PHASER_OUT_CA_TESTIN10", + "CMT_TOP_SE4C0_6", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_LH1_9", + "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH10_4", + "CMT_TOP_IMUX32_3", + "CMT_TOP_SE4C2_7", + "CMT_PHASER_TOP_SYNC_BB", + "CMT_TOP_IMUX16_9", + "CMT_TOP_BYP5_1", + "CMT_TOP_IMUX3_11", + "CMT_TOP_WW2A1_7", + "CMT_PHASER_IN_DB_COUNTERLOADEN", + "CMT_TOP_IMUX17_5", + "CMT_TOP_BYP2_2", + "CMT_TOP_LH1_6", + "PLLOUT_CLK_FREQ_BB_REBUFOUT2", + "CMT_PHY_CONTROL_OBURSTPENDING0", + "CMT_TOP_SW4A1_11", + "CMT_TOP_IMUX12_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX13_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_NW2A1_9", + "CMT_TOP_SE2A3_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_EE4C0_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_NE4C2_0", + "CMT_TOP_IMUX1_7", + "PLLOUT_CLK_FREQ_BB_REBUFOUT1", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX21_5", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH12_3", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LH12_8", + "CMT_FREQ_BB_PREF_IN2", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_PHY_CONTROL_TESTINPUT13", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_CTRL0_8", + "CMT_PHASER_OUT_CA_TESTIN4", + "CMT_TOP_NW4A3_7", + "CMT_PHASER_OUT_CA_SYSCLK", + "CMT_TOP_NW4END3_0", + "CMT_TOP_NE2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_IMUX20_8", + "CMT_TOP_WW2END0_8", + "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "CMT_TOP_LH9_3", + "CMT_TOP_IMUX29_9", + "CMT_TOP_LH6_4", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_WW2A2_10", + "CMT_PHASER_IN_CA_STG1REGR3", + "CMT_TOP_MONITOR_P_3", + "CMT_PHASER_OUT_CA_COARSEINC", + "CMT_TOP_NE4C3_0", + "CMT_TOP_BYP6_5", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_WL1END0_6", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_IMUX15_6", + "CMT_TOP_ICLK_2", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_IMUX36_2", + "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "CMT_TOP_FAN1_3", + "CMT_TOP_LH9_0", + "CMT_TOP_WL1END0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_PHASERD_DTSBUS1", + "CMT_TOP_WR1END3_6", + "CMT_PHY_CONTROL_IRANKC0", + "CMT_TOP_NE2A3_3", + "CMT_TOP_SW4A2_10", + "CMT_TOP_WR1END2_10", + "CMT_TOP_IMUX29_8", + "CMT_PHASER_IN_DB_STG1REGR8", + "CMT_TOP_IMUX26_6", + "CMT_TOP_FAN7_11", + "CMT_PHASER_UP_BUFMRCE_CE1", + "CMT_PHASER_OUT_DB_TESTIN2", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_IMUX29_0", + "CMT_TOP_WR1END2_0", + "CMT_PHASER_OUT_CA_RDENABLE", + "CMT_PHASER_IN_DB_ICLK", + "CMT_TOP_SW2A3_6", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX43_9", + "CMT_TOP_IMUX8_10", + "CMT_TOP_BYP3_3", + "CMT_TOP_WW2A2_3", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX44_0", + "CMT_TOP_WW4C1_1", + "CMT_PHASER_IN_DB_MEMREFCLK", + "CMT_TOP_EE4A1_7", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW2A1_3", + "CMT_TOP_IMUX39_5", + "CMT_TOP_LH1_0", + "CMT_TOP_IMUX28_5", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_NE2A1_7", + "CMT_TOP_IMUX41_10", + "CMT_TOP_WR1END3_5", + "CMT_TOP_IMUX37_10", + "CMT_TOP_IMUX23_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX15_5", + "CMT_PHASER_C_ICLKDIV_TOIOI", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_SW4A0_7", + "CMT_PHASER_IN_CA_STG1REGL2", + "CMT_TOP_LH12_4", + "CMT_TOP_WW4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_TOP_WW4A1_7", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX5_3", + "CMT_PHASER_IN_DB_TESTIN13", + "CMT_PHASER_OUT_DB_CTSBUS0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_LH7_7", + "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "CMT_TOP_WW4C0_7", + "CMT_PHASER_IN_DB_WRENABLE", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_IMUX39_11", + "CMT_TOP_BYP5_4", + "CMT_TOP_FAN4_3", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_FAN6_2", + "CMT_TOP_IMUX20_6", + "CMT_TOP_IMUX22_4", + "CMT_TOP_LH4_5", + "CMT_TOP_WR1END2_4", + "CMT_TOP_LH9_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_EE4C3_0", + "CMT_TOP_BYP4_9", + "CMT_TOP_NW4END2_11", + "CMT_TOP_NE4C1_6", + "CMT_TOP_BYP2_0", + "CMT_TOP_WW2A0_10", + "CMT_TOP_IMUX7_11", + "CMT_TOP_WW4END0_0", + "CMT_TOP_EE2A2_7", + "CMT_TOP_LH2_1", + "CMT_TOP_WW4END3_7", + "CMT_PHASER_OUT_CA_COARSEENABLE", + "CMT_PHY_CONTROL_PHYCTLWD5", + "CMT_PHASER_IN_CA_STG1REGR6", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_EE2BEG0_9", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CMT_TOP_LH11_5", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_WW4C1_5", + "CMT_TOP_BYP5_8", + "CMT_TOP_WR1END2_11", + "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "CMT_PHY_CONTROL_MEMREFCLK", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_8", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_WL1END1_7", + "CMT_TOP_WL1END1_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_PHASER_IN_CA_COUNTERREADEN", + "CMT_TOP_NW4A3_6", + "CMT_TOP_LH6_7", + "CMT_PHASER_IN_DB_TESTIN4", + "CMT_TOP_WW4B1_8", + "CMT_TOP_WW4A3_0", + "CMT_TOP_FAN3_7", + "CMT_TOP_ER1BEG1_1", + "CMT_PHASER_IN_C_WRENABLE_FIFO", + "CMT_TOP_SW2A2_10", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_IMUX25_5", + "CMT_TOP_CLK0_4", + "CMT_PHY_CONTROL_TESTINPUT8", + "CMT_TOP_NW2A0_9", + "CMT_TOP_FAN5_3", + "CMT_TOP_EE4A1_4", + "CMT_TOP_IMUX31_6", + "CMT_TOP_NE2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_PHASER_REF_PWRDWN", + "CMT_TOP_IMUX38_7", + "CMT_PHASER_REF_TESTIN3", + "CMT_PHY_CONTROL_PCENABLECALIB1", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_PHASER_UP_BUFMRCE_CE0", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_ICLK_7", + "CMT_TOP_IMUX15_3", + "CMT_PHASER_REF_TESTIN4", + "CMT_PHASER_OUT_DB_TESTIN10", + "CMT_TOP_FAN1_9", + "CMT_TOP_FAN2_3", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_SW4A0_4", + "CMT_TOP_LH11_9", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_IMUX8_3", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_EE4C2_11", + "CMT_TOP_NE4C3_1", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CTRL0_3", + "CMT_TOP_EE4C2_7", + "CMT_PHASER_IN_DB_ENSTG1", + "CMT_TOP_FAN0_8", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_PHASER_OUT_DB_TESTIN15", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "PLL_CLK_FREQBB_REBUFOUT1", + "CMT_PHASER_IN_DB_TESTIN9", + "CMT_TOP_SW4A1_1", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_NW4END2_10", + "CMT_PHASER_IN_CA_SCANCLK", + "CMT_TOP_IMUX9_6", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX31_8", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX28_7", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_PHASER_IN_DB_STG1REGL4", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_SW2A3_7", + "CMT_TOP_LH4_9", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_NW2A3_9", + "CMT_TOP_EE4B3_4", + "CMT_TOP_SE4BEG1_1", + "CMT_PHASER_OUT_CA_OCLKDELAYED", + "CMT_PHY_CONTROL_TESTOUTPUT6", + "CMT_TOP_IMUX24_4", + "CMT_TOP_FAN6_6", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_IMUX25_2", + "CMT_TOP_BYP2_3", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_FAN4_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_NW4A1_3", + "CMT_TOP_IMUX35_4", + "CMT_TOP_WW2END3_10", + "CMT_TOP_IMUX41_5", + "CMT_TOP_NW4A1_8", + "CMT_TOP_IMUX10_6", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_LH12_6", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_BYP6_10", + "CMT_PHASERREF_PHASEROUT_C", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_BYP7_1", + "CMT_PHY_CONTROL_PHYCTLWD18", + "CMT_TOP_WW2A0_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_SW4A2_1", + "CMT_TOP_LH1_3", + "CMT_TOP_FAN0_5", + "CMT_TOP_EE2A1_8", + "CMT_TOP_WW4C3_7", + "CMT_TOP_LH2_3", + "CMT_TOP_FAN7_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_NW4A3_0", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "CMT_TOP_EE4B1_10", + "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "CMT_PHASER_IN_CA_ENCALIB0", + "CMT_TOP_WW4END2_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX38_4", + "CMT_TOP_NE2A1_4", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_IMUX27_2", + "CMT_TOP_WW4C0_6", + "CMT_PHASER_OUT_DB_TESTOUT1", + "CMT_TOP_IMUX1_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_NE2A2_5", + "CMT_TOP_NW4A0_3", + "CMT_TOP_ICLKDIV_8", + "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "CMT_PHY_CONTROL_AUXOUTPUT0", + "CMT_TOP_NW2A3_6", + "CMT_TOP_WW4END3_5", + "CMT_TOP_WW4B1_5", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX23_10", + "CMT_TOP_IMUX17_0", + "CMT_TOP_CLK0_2", + "CMT_TOP_EE4B3_2", + "CMT_PHASER_OUT_CA_COUNTERREADEN", + "CMT_TOP_IMUX31_5", + "CMT_TOP_FAN0_0", + "CMT_PHY_CONTROL_PHYCTLWD30", + "CMT_TOP_EE4C3_2", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX46_3", + "CMT_TOP_IMUX43_7", + "CMT_TOP_IMUX40_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_EE4A3_9", + "CMT_PHASER_OUT_CA_TESTIN8", + "CMT_TOP_WW4END3_6", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "CMT_TOP_FAN2_5", + "CMT_TOP_CLK0_6", + "CMT_TOP_IMUX10_5", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_PHASER_IN_C_ICLKDIV", + "CMT_TOP_WW2A3_8", + "CMT_TOP_NE4C1_8", + "CMT_TOP_EE4A1_1", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4C0_4", + "CMT_TOP_BYP0_6", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX12_4", + "CMT_TOP_LH10_3", + "CMT_TOP_LH3_2", + "CMT_TOP_EL1BEG3_7", + "CMT_PHASER_IN_CA_STG1INCDEC", + "CMT_PHY_CONTROL_TESTINPUT2", + "CMT_PHASER_OUT_CA_TESTOUT2", + "CMT_TOP_IMUX43_4", + "CMT_TOP_LH10_6", + "CMT_TOP_NE4C1_10", + "CMT_TOP_IMUX15_11", + "CMT_PHASER_IN_DB_STG1INCDEC", + "CMT_TOP_NE4C1_9", + "CMT_TOP_WW4B0_3", + "CMT_PHASERREF_PHASERIN_C", + "CMT_PHASER_OUT_C_OCLK1X_90", + "CMT_TOP_WW4C3_10", + "CMT_TOP_SE2A2_6", + "CMT_TOP_NW2A3_5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_WW4A2_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_IMUX38_11", + "CMT_TOP_SW4END2_9", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_PHASER_OUT_DB_FINEENABLE", + "CMT_PHASER_IN_CA_STG1REGR2", + "CMT_TOP_LH3_1", + "CMT_PHY_CONTROL_PHYCTLREADY", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END2_5", + "CMT_TOP_FAN0_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_IMUX42_11", + "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "CMT_TOP_SE2A0_3", + "CMT_TOP_IMUX4_5", + "CMT_TOP_BYP4_0", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LH4_4", + "CMT_TOP_LH3_9", + "CMT_PHASER_IN_DB_TESTOUT1", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_EL1BEG2_9", + "CMT_TOP_WW4C1_2", + "CMT_TOP_IMUX37_11", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_WR1END1_0", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_IMUX22_5", + "CMT_TOP_OCLK_3", + "CMT_TOP_IMUX23_5", + "CMT_PHASER_OUT_DB_TESTIN9", + "CMT_TOP_SW4END2_4", + "CMT_TOP_EE4A1_8", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW2END0_2", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_SE2A1_6", + "CMT_TOP_CTRL0_1", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END0_9", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_WW4B0_0", + "CMT_TOP_IMUX6_5", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_WW4B0_4", + "CMT_TOP_IMUX10_9", + "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_FREQ_PHASER_REFMUX_2", + "CMT_TOP_IMUX45_0", + "CMT_PHASER_OUT_DB_DTSBUS1", + "CMT_R_TOP_UPPER_B_CLKPLL0", + "CMT_TOP_IMUX45_10", + "CMT_PHASER_IN_CA_RCLK", + "CMT_TOP_IMUX39_1", + "CMT_TOP_WL1END1_8", + "CMT_PHY_CONTROL_OBURSTPENDING3", + "CMT_TOP_EE2A3_6", + "CMT_TOP_IMUX9_5", + "CMT_TOP_WW2END3_8", + "CMT_TOP_BYP4_10", + "CMT_TOP_IMUX17_9", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_IMUX23_4", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_FAN3_10", + "CMT_TOP_EE4B0_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_R_TOP_UPPER_B_CLKINT_2", + "CMT_PHY_CONTROL_AUXOUTPUT1", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX42_9", + "CMT_TOP_EE2A2_6", + "CMT_TOP_IMUX25_3", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_PHASER_IN_CA_RANKSELPHY1", + "CMT_TOP_NW4A3_4", + "CMT_TOP_IMUX34_4", + "CMT_TOP_LH7_2", + "CMT_TOP_LH6_1", + "CMT_TOP_NW4END2_2", + "CMT_PHASER_IN_DB_STG1REGL2", + "CMT_TOP_LH1_2", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_PHASER_IN_CA_TESTIN1", + "CMT_TOP_IMUX13_2", + "CMT_TOP_WW4A0_8", + "CMT_TOP_FAN6_8", + "CMT_TOP_IMUX17_7", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_NW4A0_2", + "CMT_TOP_BYP6_6", + "CMT_PHASER_IN_CA_WRENABLE", + "CMT_PHASER_IN_CA_ICLK", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_PHY_CONTROL_INRANKB0", + "CMT_PHY_CONTROL_IRANKA1", + "CMT_TOP_SW4END1_7", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NW4END0_6", + "CMT_TOP_WR1END3_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_R_TOP_UPPER_B_CLKPLL6", + "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "CMT_TOP_NE2A3_7", + "CMT_TOP_IMUX3_7", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_TOP_BYP2_6", + "CMT_TOP_IMUX14_8", + "CMT_PHASER_IN_CA_RST", + "CMT_PHASER_IN_DB_TESTIN5", + "CMT_TOP_BYP0_3", + "CMT_PHASER_IN_D_WRENABLE_FIFO", + "CMT_TOP_NE4C0_0", + "CMT_TOP_NE4C2_10", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH6_11", + "CMT_TOP_FAN5_10", + "CMT_PHY_CONTROL_PHYCLK", + "CMT_PHASER_IN_DB_ENCALIB0", + "CMT_TOP_WW4END2_4", + "CMT_TOP_NW2A3_11", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_PHASER_OUT_DB_DQSBUS1", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_NW2A2_8", + "CMT_TOP_IMUX19_4", + "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "CMT_TOP_WW2END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_IMUX30_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX28_1", + "CMT_TOP_NW4A0_0", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_LH3_7", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX16_4", + "CMT_TOP_EE2A3_7", + "CMT_TOP_SE4C3_11", + "CMT_TOP_ICLK_9", + "CMT_PHASER_IN_CA_FINEINC", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_WW4A1_10", + "CMT_PHASER_UP_PHASERREF_BELOW1", + "CMT_TOP_WW2END0_0", + "CMT_PHY_CONTROL_PHYCTLWD16", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_WW4C3_11", + "CMT_TOP_BYP3_6", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_WW2A2_8", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_WW4B3_7", + "CMT_TOP_SW4END3_4", + "CMT_TOP_EE4C1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_BYP0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_WW4END1_7", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WW4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX5_0", + "CMT_PHASER_OUT_DB_SYSCLK", + "CMT_PHASER_IN_CA_STG1REGL5", + "CMT_TOP_WW4B3_10", + "CMT_PHASER_OUT_CA_TESTIN5", + "CMT_PHASER_IN_DB_ENCALIB1", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_WW2END3_9", + "CMT_PHY_CONTROL_TESTOUTPUT9", + "CMT_TOP_SW4END1_10", + "CMT_TOP_WW4B0_7", + "CMT_TOP_BYP3_7", + "CMT_TOP_EE2A3_11", + "CMT_TOP_LH6_5", + "CMT_TOP_IMUX28_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_WW4A3_5", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_EE2BEG2_0", + "CMT_PHASER_IN_D_RCLK3", + "CMT_TOP_WW4A0_11", + "CMT_TOP_WL1END0_3", + "CMT_TOP_WW4C0_2", + "CMT_TOP_IMUX0_7", + "CMT_PHASER_OUT_DB_SCANENB", + "CMT_TOP_WW4B1_0", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SW4END0_8", + "CMT_TOP_IMUX8_1", + "CMT_TOP_WW4C2_10", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_IMUX34_6", + "CMT_PHASER_IN_DB_COUNTERREADEN", + "CMT_TOP_IMUX32_11", + "CMT_TOP_NE2A3_1", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_EE4B0_3", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A3_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_TOP_IMUX46_10", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ER1BEG2_5", + "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "CMT_TOP_SW2A3_2", + "CMT_TOP_WW4C0_5", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_BYP4_4", + "CMT_TOP_NW4A2_9", + "CMT_TOP_WR1END2_1", + "CMT_PHASER_IN_CA_PHASELOCKED", + "CMT_TOP_EE2BEG0_7", + "CMT_PHASER_IN_DB_STG1READ", + "CMT_TOP_IMUX16_1", + "CMT_TOP_NW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_FAN2_6", + "CMT_TOP_WR1END3_7", + "CMT_TOP_IMUX38_9", + "CMT_TOP_IMUX28_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_FAN5_7", + "CMT_PHASER_OUT_CA_SCANCLK", + "CMT_TOP_BYP7_10", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CMT_TOP_IMUX15_7", + "CMT_R_TOP_UPPER_B_CLKPLL3", + "CMT_TOP_IMUX30_9", + "CMT_TOP_LH8_5", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "CMT_TOP_EE4A3_5", + "CMT_PHASER_REF_TESTOUT0", + "CMT_PHASER_REF_TESTIN5", + "CMT_TOP_NE4C0_5", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_IMUX25_0", + "CMT_TOP_IMUX31_10", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_IMUX34_2", + "CMT_TOP_LH10_2", + "CMT_PHASER_OUT_DB_OCLK", + "CMT_TOP_LH12_0", + "CMT_TOP_FAN4_0", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_NW4A0_8", + "CMT_TOP_WW4A2_10", + "CMT_TOP_BYP3_0", + "CMT_TOP_IMUX2_1", + "CMT_PHY_CONTROL_INRANKC1", + "CMT_PHASER_IN_DB_STG1REGR5", + "CMT_PHASER_IN_CA_SELCALORSTG1", + "CMT_TOP_IMUX22_1", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_EE2A3_5", + "CMT_TOP_IMUX4_7", + "CMT_TOP_SE2A2_0", + "CMT_TOP_LH2_4", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SW4A3_6", + "CMT_TOP_NW4END1_5", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WR1END3_1", + "CMT_TOP_BYP1_0", + "CMT_PHY_CONTROL_TESTINPUT9", + "CMT_TOP_WW2A0_6", + "CMT_TOP_SE2A3_0", + "CMT_PHASER_IN_DB_STG1REGL7", + "CMT_TOP_IMUX35_9", + "CMT_TOP_SW4END2_5", + "CMT_TOP_SE4C3_5", + "CMT_TOP_LH4_1", + "CMT_TOP_NW4A0_9", + "CMT_TOP_SW4A1_6", + "CMT_TOP_SW2A2_0", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE4C3_10", + "PLL_CLK_FREQBB_REBUFOUT3", + "CMT_TOP_SW4END0_7", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_IMUX13_5", + "CMT_TOP_NE4C0_4", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EE4A2_4", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_EL1BEG2_6", + "CMT_R_TOP_UPPER_B_CLKIN2", + "CMT_TOP_LH2_8", + "CMT_TOP_SE2A3_1", + "CMT_TOP_IMUX2_6", + "CMT_PHY_CONTROL_ECALIB1", + "CMT_TOP_IMUX3_0", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4C2_4", + "CMT_TOP_NE4BEG1_5", + "CMT_PHASER_IN_CA_DQSFOUND", + "CMT_PHASER_IN_CA_STG1OVERFLOW", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_ER1BEG0_6", + "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "CMT_TOP_EE2A3_2", + "CMT_TOP_IMUX14_10", + "CMT_TOP_IMUX23_8", + "CMT_TOP_WW4A3_8", + "CMT_TOP_IMUX40_6", + "CMT_TOP_LH10_9", + "CMT_PHASER_OUT_CA_SCANIN", + "CMT_TOP_FAN1_0", + "CMT_TOP_LH4_10", + "CMT_PHASER_IN_CA_TESTOUT1", + "CMT_TOP_IMUX0_2", + "CMT_R_TOP_UPPER_B_CLKFBIN", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_LH5_3", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_NW2A0_3", + "CMT_TOP_NW2A3_3", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX18_1", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_SW4END3_10", + "CMT_TOP_FAN2_10", + "CMT_PHASER_REF_TESTOUT6", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_WR1END1_1", + "CMT_TOP_SW2A2_7", + "CMT_TOP_ICLK_5", + "CMT_TOP_SW2A0_7", + "CMT_PHASER_OUT_DB_OSERDESRST", + "CMT_TOP_FAN6_5", + "CMT_TOP_ER1BEG0_7", + "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "CMT_TOP_NW4A2_0", + "CMT_TOP_WW2A1_2", + "CMT_TOP_FAN4_1", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_SE4C0_11", + "CMT_PHASER_OUT_DB_TESTIN12", + "CMT_TOP_WW2END0_6", + "CMT_TOP_CTRL1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "CMT_PHASER_OUT_CA_DTSBUS1", + "CMT_TOP_WW4B1_2", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_FAN6_3", + "CMT_TOP_SW4A2_3", + "CMT_TOP_WL1END1_11", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_LH11_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_SE4C2_6", + "CMT_TOP_FAN5_11", + "CMT_TOP_SW4END1_6", + "CMT_PHY_CONTROL_AUXOUTPUT2", + "CMT_TOP_IMUX2_2", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW2END0_5", + "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "CMT_TOP_LH6_0", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_PHASER_IN_CA_RANKSEL0", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX29_3", + "CMT_PHY_CONTROL_IBURSTPENDING1", + "CMT_PHY_CONTROL_TESTINPUT1", + "CMT_TOP_WL1END1_6", + "CMT_TOP_NW4A2_5", + "CMT_TOP_IMUX6_9", + "CMT_TOP_IMUX33_1", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX9_2", + "CMT_TOP_IMUX19_5", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_EE4B3_9", + "CMT_TOP_EE4A1_9", + "CMT_PHY_CONTROL_WRITECALIBENABLE", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_NE2A3_4", + "CMT_TOP_IMUX40_3", + "CMT_TOP_EE2A0_11", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_ICLK_3", + "CMT_TOP_SW4END0_6", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_IMUX41_6", + "CMT_PHASER_OUT_CA_OCLKDIV", + "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "CMT_TOP_EE4A0_11", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_IMUX46_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_EE4C0_2", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX11_3", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_LH5_8", + "CMT_TOP_WW4A2_8", + "CMT_TOP_WW4A3_4", + "CMT_TOP_LH11_4", + "CMT_TOP_IMUX34_0", + "CMT_TOP_BYP1_6", + "CMT_TOP_WW4B0_1", + "CMT_PHY_CONTROL_TESTINPUT15", + "CMT_TOP_IMUX2_4", + "CMT_TOP_SW4A1_8", + "CMT_TOP_MONITOR_P_8", + "CMT_PHASER_IN_D_ICLKDIV", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_WL1END3_10", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX29_7", + "CMT_TOP_IMUX33_3", + "CMT_TOP_SW2A2_3", + "CMT_TOP_IMUX44_8", + "CMT_TOP_IMUX32_7", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SW2A3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX32_1", + "CMT_TOP_LH8_1", + "CMT_TOP_SE2A2_1", + "CMT_TOP_WW4C3_3", + "CMT_TOP_SE4C3_1", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX26_3", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_IMUX24_6", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_EE4BEG2_8", + "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "CMT_TOP_SE4BEG0_11", + "CMT_PHY_CONTROL_PHYCTLWD14", + "CMT_TOP_NE2A2_10", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_IMUX17_1", + "CMT_TOP_EE4C3_7", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX32_2", + "CMT_PHASER_IN_DB_TESTIN8", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_ICLK_6", + "CMT_PHASER_IN_CA_RSTDQSFIND", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_SE2A3_7", + "CMT_PHASER_IN_CA_TESTOUT0", + "CMT_TOP_BYP6_9", + "CMT_TOP_EE4B2_3", + "CMT_TOP_SE4BEG0_6", + "CMT_PHY_CONTROL_SYNCIN", + "CMT_TOP_WW2A0_8", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX0_3", + "CMT_TOP_IMUX30_10", + "CMT_TOP_IMUX27_10", + "CMT_TOP_WW4END0_9", + "CMT_TOP_SW4END0_5", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_SW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_PHASER_IN_DB_TESTIN7", + "CMT_TOP_CTRL1_1", + "CMT_TOP_SE4BEG0_8", + "CMT_PHASER_IN_DB_STG1REGL8", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_IMUX12_11", + "CMT_PHY_CONTROL_IRANKB0", + "CMT_TOP_WW4A3_10", + "CMT_TOP_FAN3_6", + "CMT_TOP_LH5_4", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_IMUX47_3", + "CMT_TOP_SW4A3_5", + "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_EE2A1_4", + "CMT_TOP_NW4END1_4", + "CMT_TOP_IMUX25_1", + "CMT_TOP_LH5_11", + "CMT_TOP_FAN1_10", + "CMT_TOP_NW4END0_11", + "CMT_TOP_EE4C0_11", + "CMT_PHASER_OUT_DB_TESTIN11", + "CMT_TOP_IMUX25_8", + "CMT_TOP_EE4A1_3", + "CMT_TOP_NW2A3_7", + "CMT_TOP_IMUX30_11", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_EE4BEG3_0", + "CMT_PHASER_OUT_DB_TESTIN8", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_EE2A1_2", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WW4C2_8", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX26_11", + "CMT_TOP_NE2A2_1", + "CMT_TOP_CTRL1_8", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NW4END3_3", + "CMT_TOP_WW4B2_2", + "CMT_TOP_IMUX18_3", + "CMT_PHASER_IN_CA_STG1REGL3", + "CMT_TOP_IMUX16_11", + "CMT_TOP_WW4A0_3", + "CMT_TOP_LH5_1", + "CMT_TOP_WL1END0_4", + "CMT_TOP_IMUX44_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SE2A2_3", + "CMT_PHASER_IN_DB_STG1REGR2", + "CMT_TOP_SE4C2_4", + "CMT_TOP_FAN6_10", + "CMT_TOP_EE4C2_0", + "CMT_PHY_CONTROL_IRANKB1", + "CMT_TOP_NE4C1_3", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX18_8", + "CMT_TOP_BYP3_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_CLK1_5", + "CMT_TOP_SW2A0_4", + "CMT_TOP_IMUX0_10", + "CMT_PHY_CONTROL_INRANKA0", + "CMT_PHY_CONTROL_TESTOUTPUT5", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_R_TOP_UPPER_B_CLKINT_3", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_IMUX13_7", + "CMT_TOP_NE4C2_2", + "CMT_TOP_EE4A1_11", + "CMT_TOP_IMUX10_4", + "CMT_PHASER_IN_DB_ISERDESRST", + "CMT_TOP_EE2A0_6", + "CMT_TOP_NW4END1_0", + "CMT_TOP_LH5_10", + "CMT_TOP_IMUX46_7", + "CMT_PHASER_IN_DB_SYSCLK", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE2A2_8", + "CMT_TOP_OCLK_9", + "CMT_TOP_NW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_WW4END3_9", + "CMT_TOP_EE4C3_1", + "CMT_TOP_IMUX14_11", + "CMT_PHASER_IN_CA_SCANOUT", + "CMT_TOP_WW4C1_9", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_WL1END3_9", + "CMT_TOP_IMUX0_9", + "CMT_TOP_IMUX13_6", + "CMT_TOP_EE4A2_6", + "CMT_TOP_IMUX20_0", + "CMT_PHY_CONTROL_INRANKB1", + "CMT_TOP_WW4B2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_PHASER_IN_DB_STG1REGL1", + "CMT_TOP_WR1END2_2", + "CMT_TOP_WW2A0_1", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_EE2BEG0_5", + "CMT_PHY_CONTROL_PHYCTLEMPTY", + "CMT_TOP_WW4B0_8", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LH5_7", + "CMT_TOP_IMUX21_9", + "CMT_PHY_CONTROL_PHYCTLWD12", + "CMT_TOP_IMUX35_1", + "CMT_PHASER_IN_DB_STG1REGR0", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_NW2A3_8", + "CMT_PHY_CONTROL_PHYCTLWD25", + "CMT_TOP_SE2A3_4", + "CMT_TOP_SW4END3_9", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NE4C0_10", + "CMT_TOP_IMUX26_5", + "CMT_TOP_BYP4_11", + "CMT_TOP_IMUX25_6", + "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "CMT_TOP_BYP0_2", + "CMT_TOP_BYP6_7", + "CMT_PHASER_IN_CA_TESTIN12", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_NE2A1_8", + "CMT_TOP_WW4A0_10", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_5", + "CMT_TOP_WW4B2_0", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_PHASER_IN_CA_BURSTPENDING", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_PHASER_IN_DB_SCANMODEB", + "CMT_TOP_WL1END3_0", + "CMT_TOP_WW4END0_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_NW4END0_1", + "CMT_TOP_LH6_6", + "CMT_TOP_NE4C3_5", + "CMT_PHY_CONTROL_TESTINPUT11", + "CMT_PHY_CONTROL_PHYCTLWD19", + "CMT_TOP_NW4END0_8", + "CMT_TOP_IMUX39_0", + "CMT_TOP_WW4END2_0", + "CMT_TOP_WW4B3_4", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_PHY_CONTROL_AUXOUTPUT3", + "CMT_TOP_IMUX9_0", + "CMT_PHY_CONTROL_PHYCTLWD13", + "CMT_PHASER_REF_TESTOUT4", + "CMT_TOP_FAN2_0", + "CMT_PHY_CONTROL_TESTOUTPUT2", + "CMT_TOP_IMUX29_11", + "CMT_TOP_IMUX30_5", + "CMT_TOP_IMUX8_9", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_NW4END2_5", + "CMT_TOP_NE4C0_7", + "CMT_TOP_WW2END2_4", + "CMT_PHASER_IN_DB_TESTIN6", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_WL1END3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NW2A0_2", + "CMT_TOP_IMUX17_6", + "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "CMT_TOP_SE2A1_2", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_IMUX7_0", + "CMT_TOP_IMUX20_2", + "CMT_TOP_LH8_7", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_WW4A2_5", + "CMT_TOP_NE4C1_11", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_OCLK_6", + "CMT_TOP_IMUX18_10", + "CMT_PHY_CONTROL_READCALIBENABLE", + "CMT_TOP_BYP4_7", + "CMT_PHASER_IN_CA_STG1REGR8", + "PLLOUT_CLK_FREQ_BB_REBUFIN3", + "CMT_TOP_BYP0_5", + "CMT_TOP_SE2A2_4", + "CMT_TOP_SE4C2_1", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_NW4END3_4", + "CMT_TOP_IMUX40_11", + "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "CMT_TOP_LH9_8", + "CMT_PHASER_IN_CA_DIVIDERST", + "CMT_TOP_LH9_11", + "CMT_TOP_NE2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX28_11", + "CMT_PHASER_IN_CA_TESTIN0", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_LH3_10", + "CMT_TOP_IMUX42_7", + "CMT_TOP_IMUX5_10", + "CMT_TOP_WL1END3_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_EE2A3_1", + "CMT_TOP_IMUX2_10", + "CMT_TOP_SE2A0_6", + "CMT_TOP_NE2A2_4", + "CMT_PHASER_OUT_CA_TESTIN2", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_SE4C1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "CMT_TOP_MONITOR_P_2", + "CMT_PHASER_IN_DB_TESTIN0", + "CMT_TOP_IMUX41_4", + "CMT_TOP_WL1END0_1", + "CMT_PHASER_C_OCLKDIV_TOIOI", + "CMT_TOP_NW4END2_4", + "CMT_TOP_FAN5_1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_IMUX20_10", + "CMT_PHASER_IN_CA_TESTOUT3", + "CMT_TOP_NE2A2_11", + "CMT_PHASER_OUT_CA_TESTIN1", + "CMT_TOP_FAN5_2", + "CMT_TOP_SW2A3_9", + "CMT_TOP_NW2A1_1", + "CMT_TOP_FAN1_1", + "CMT_TOP_IMUX5_7", + "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "CMT_TOP_IMUX11_11", + "CMT_TOP_NE2A1_5", + "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "CMT_TOP_CLK1_0", + "CMT_TOP_SW4END1_11", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_R_TOP_UPPER_B_CLKIN1", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_IMUX28_9", + "CMT_TOP_NW4A1_4", + "CMT_TOP_NE4C2_5", + "CMT_TOP_WW4B2_8", + "CMT_TOP_SE4BEG1_3", + "CMT_PHASER_IN_CA_RANKSELPHY0", + "PLLOUT_CLK_FREQ_BB_REBUFIN0", + "CMT_TOP_SE4BEG3_7", + "CMT_PHASER_OUT_C_RDCLK_TOFIFO", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_WW4B2_6", + "CMT_TOP_WW2END1_11", + "CMT_TOP_IMUX19_0", + "CMT_TOP_LH3_3", + "CMT_TOP_IMUX38_5", + "CMT_PHY_CONTROL_SCANENABLEN", + "CMT_TOP_IMUX31_2", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_LH4_2", + "CMT_PHASER_OUT_C_RDENABLE_TOFIFO", + "CMT_TOP_SE2A0_11", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH12_9", + "CMT_TOP_SW2A0_0", + "CMT_PHY_CONTROL_PHYCTLWD8", + "CMT_TOP_SW2A0_11", + "CMT_TOP_WW4A3_7", + "CMT_PHY_CONTROL_PHYCTLWD3", + "CMT_TOP_BYP5_10", + "CMT_TOP_LH12_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_PHASER_OUT_CA_EDGEADV", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW2A0_4", + "CMT_PHASER_IN_DB_RANKSELPHY1", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_IMUX30_1", + "CMT_PHASER_OUT_CA_TESTOUT1", + "CMT_TOP_IMUX0_1", + "CMT_TOP_IMUX39_3", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_FAN6_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_10", + "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "CMT_TOP_NE2A2_9", + "CMT_TOP_EE4B1_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_NW4END0_10", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "CMT_TOP_OCLKDIV_2", + "CMT_PHASER_IN_DB_ICLKDIV", + "CMT_TOP_IMUX44_1", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX37_7", + "CMT_TOP_IMUX29_1", + "CMT_TOP_FAN6_11", + "CMT_TOP_NW4A0_1" + ], + "tile_type": "CMT_TOP_R_UPPER_B", + "sites": [ + { + "site_pins": { + "TESTOUT3": "CMT_PHASER_REF_TESTOUT3", + "TESTIN3": "CMT_PHASER_REF_TESTIN3", + "TESTOUT1": "CMT_PHASER_REF_TESTOUT1", + "TESTOUT5": "CMT_PHASER_REF_TESTOUT5", + "TESTOUT6": "CMT_PHASER_REF_TESTOUT6", + "TESTIN7": "CMT_PHASER_REF_TESTIN7", + "TESTIN5": "CMT_PHASER_REF_TESTIN5", + "TESTIN4": "CMT_PHASER_REF_TESTIN4", + "TESTIN0": "CMT_PHASER_REF_TESTIN0", + "TESTOUT2": "CMT_PHASER_REF_TESTOUT2", + "TESTIN1": "CMT_PHASER_REF_TESTIN1", + "LOCKED": "CMT_PHASER_REF_LOCKED", + "TESTOUT0": "CMT_PHASER_REF_TESTOUT0", + "TMUXOUT": "CMT_PHASER_REF_TMUXOUT", + "TESTIN2": "CMT_PHASER_REF_TESTIN2", + "TESTOUT7": "CMT_PHASER_REF_TESTOUT7", + "TESTOUT4": "CMT_PHASER_REF_TESTOUT4", + "PWRDWN": "CMT_PHASER_REF_PWRDWN", + "CLKIN": "CMT_PHASER_REF_CLKIN", + "TESTIN6": "CMT_PHASER_REF_TESTIN6", + "CLKOUT": "CMT_PHASER_REF_CLKOUT", + "RST": "CMT_PHASER_REF_RST" + }, + "type": "PHASER_REF", + "prefix": "PHASER_REF", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "PHYCTLWD4": "CMT_PHY_CONTROL_PHYCTLWD4", + "MEMREFCLK": "CMT_PHY_CONTROL_MEMREFCLK", + "TESTSELECT2": "CMT_PHY_CONTROL_TESTSELECT2", + "PHYCTLWD13": "CMT_PHY_CONTROL_PHYCTLWD13", + "RESET": "CMT_PHY_CONTROL_RESET", + "TESTINPUT3": "CMT_PHY_CONTROL_TESTINPUT3", + "PHYCTLWRENABLE": "CMT_PHY_CONTROL_PHYCTLWRENABLE", + "PHYCTLWD24": "CMT_PHY_CONTROL_PHYCTLWD24", + "PHYCTLWD16": "CMT_PHY_CONTROL_PHYCTLWD16", + "INRANKC0": "CMT_PHY_CONTROL_INRANKC0", + "TESTINPUT8": "CMT_PHY_CONTROL_TESTINPUT8", + "PHYCTLWD21": "CMT_PHY_CONTROL_PHYCTLWD21", + "PHYCTLWD28": "CMT_PHY_CONTROL_PHYCTLWD28", + "TESTOUTPUT9": "CMT_PHY_CONTROL_TESTOUTPUT9", + "INBURSTPENDING3": "CMT_PHY_CONTROL_INBURSTPENDING3", + "PHYCTLALMOSTFULL": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", + "PHYCTLWD2": "CMT_PHY_CONTROL_PHYCTLWD2", + "TESTINPUT4": "CMT_PHY_CONTROL_TESTINPUT4", + "TESTOUTPUT13": "CMT_PHY_CONTROL_TESTOUTPUT13", + "PHYCTLWD8": "CMT_PHY_CONTROL_PHYCTLWD8", + "TESTOUTPUT7": "CMT_PHY_CONTROL_TESTOUTPUT7", + "TESTINPUT12": "CMT_PHY_CONTROL_TESTINPUT12", + "INRANKA1": "CMT_PHY_CONTROL_INRANKA1", + "SYNCIN": "CMT_PHY_CONTROL_SYNCIN", + "READCALIBENABLE": "CMT_PHY_CONTROL_READCALIBENABLE", + "PHYCTLWD22": "CMT_PHY_CONTROL_PHYCTLWD22", + "INBURSTPENDING2": "CMT_PHY_CONTROL_INBURSTPENDING2", + "PHYCTLMSTREMPTY": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", + "PHYCTLWD3": "CMT_PHY_CONTROL_PHYCTLWD3", + "PHYCTLWD1": "CMT_PHY_CONTROL_PHYCTLWD1", + "TESTINPUT0": "CMT_PHY_CONTROL_TESTINPUT0", + "TESTOUTPUT12": "CMT_PHY_CONTROL_TESTOUTPUT12", + "PLLLOCK": "CMT_PHY_CONTROL_PLLLOCK", + "TESTOUTPUT10": "CMT_PHY_CONTROL_TESTOUTPUT10", + "TESTOUTPUT5": "CMT_PHY_CONTROL_TESTOUTPUT5", + "PHYCTLWD19": "CMT_PHY_CONTROL_PHYCTLWD19", + "TESTINPUT14": "CMT_PHY_CONTROL_TESTINPUT14", + "PHYCTLWD31": "CMT_PHY_CONTROL_PHYCTLWD31", + "AUXOUTPUT3": "CMT_PHY_CONTROL_AUXOUTPUT3", + "TESTOUTPUT0": "CMT_PHY_CONTROL_TESTOUTPUT0", + "REFDLLLOCK": "CMT_PHY_CONTROL_REFDLLLOCK", + "WRITECALIBENABLE": "CMT_PHY_CONTROL_WRITECALIBENABLE", + "PHYCTLEMPTY": "CMT_PHY_CONTROL_PHYCTLEMPTY", + "TESTINPUT15": "CMT_PHY_CONTROL_TESTINPUT15", + "INRANKD0": "CMT_PHY_CONTROL_INRANKD0", + "PHYCTLWD11": "CMT_PHY_CONTROL_PHYCTLWD11", + "OUTBURSTPENDING2": "CMT_PHY_CONTROL_OUTBURSTPENDING2", + "PHYCTLWD29": "CMT_PHY_CONTROL_PHYCTLWD29", + "SCANENABLEN": "CMT_PHY_CONTROL_SCANENABLEN", + "TESTINPUT9": "CMT_PHY_CONTROL_TESTINPUT9", + "INRANKA0": "CMT_PHY_CONTROL_INRANKA0", + "PHYCTLWD25": "CMT_PHY_CONTROL_PHYCTLWD25", + "TESTINPUT11": "CMT_PHY_CONTROL_TESTINPUT11", + "TESTOUTPUT8": "CMT_PHY_CONTROL_TESTOUTPUT8", + "AUXOUTPUT0": "CMT_PHY_CONTROL_AUXOUTPUT0", + "TESTINPUT1": "CMT_PHY_CONTROL_TESTINPUT1", + "PHYCTLWD9": "CMT_PHY_CONTROL_PHYCTLWD9", + "PHYCTLWD17": "CMT_PHY_CONTROL_PHYCTLWD17", + "OUTBURSTPENDING0": "CMT_PHY_CONTROL_OUTBURSTPENDING0", + "TESTSELECT1": "CMT_PHY_CONTROL_TESTSELECT1", + "INBURSTPENDING1": "CMT_PHY_CONTROL_INBURSTPENDING1", + "PHYCTLWD20": "CMT_PHY_CONTROL_PHYCTLWD20", + "PCENABLECALIB0": "CMT_PHY_CONTROL_PCENABLECALIB0", + "PHYCTLWD6": "CMT_PHY_CONTROL_PHYCTLWD6", + "PHYCTLWD15": "CMT_PHY_CONTROL_PHYCTLWD15", + "TESTINPUT13": "CMT_PHY_CONTROL_TESTINPUT13", + "TESTOUTPUT11": "CMT_PHY_CONTROL_TESTOUTPUT11", + "TESTOUTPUT6": "CMT_PHY_CONTROL_TESTOUTPUT6", + "PHYCTLWD14": "CMT_PHY_CONTROL_PHYCTLWD14", + "PHYCTLWD12": "CMT_PHY_CONTROL_PHYCTLWD12", + "TESTOUTPUT3": "CMT_PHY_CONTROL_TESTOUTPUT3", + "TESTOUTPUT2": "CMT_PHY_CONTROL_TESTOUTPUT2", + "TESTINPUT2": "CMT_PHY_CONTROL_TESTINPUT2", + "TESTOUTPUT1": "CMT_PHY_CONTROL_TESTOUTPUT1", + "PHYCLK": "CMT_PHY_CONTROL_PHYCLK", + "TESTINPUT10": "CMT_PHY_CONTROL_TESTINPUT10", + "TESTOUTPUT14": "CMT_PHY_CONTROL_TESTOUTPUT14", + "INRANKD1": "CMT_PHY_CONTROL_INRANKD1", + "PHYCTLWD10": "CMT_PHY_CONTROL_PHYCTLWD10", + "TESTOUTPUT15": "CMT_PHY_CONTROL_TESTOUTPUT15", + "PHYCTLREADY": "CMT_PHY_CONTROL_PHYCTLREADY", + "PHYCTLWD23": "CMT_PHY_CONTROL_PHYCTLWD23", + "PHYCTLWD27": "CMT_PHY_CONTROL_PHYCTLWD27", + "PHYCTLWD30": "CMT_PHY_CONTROL_PHYCTLWD30", + "TESTSELECT0": "CMT_PHY_CONTROL_TESTSELECT0", + "PHYCTLFULL": "CMT_PHY_CONTROL_PHYCTLFULL", + "TESTINPUT6": "CMT_PHY_CONTROL_TESTINPUT6", + "TESTOUTPUT4": "CMT_PHY_CONTROL_TESTOUTPUT4", + "INRANKB1": "CMT_PHY_CONTROL_INRANKB1", + "INBURSTPENDING0": "CMT_PHY_CONTROL_INBURSTPENDING0", + "AUXOUTPUT2": "CMT_PHY_CONTROL_AUXOUTPUT2", + "PHYCTLWD5": "CMT_PHY_CONTROL_PHYCTLWD5", + "INRANKC1": "CMT_PHY_CONTROL_INRANKC1", + "AUXOUTPUT1": "CMT_PHY_CONTROL_AUXOUTPUT1", + "PCENABLECALIB1": "CMT_PHY_CONTROL_PCENABLECALIB1", + "OUTBURSTPENDING1": "CMT_PHY_CONTROL_OUTBURSTPENDING1", + "PHYCTLWD7": "CMT_PHY_CONTROL_PHYCTLWD7", + "INRANKB0": "CMT_PHY_CONTROL_INRANKB0", + "PHYCTLWD0": "CMT_PHY_CONTROL_PHYCTLWD0", + "PHYCTLWD18": "CMT_PHY_CONTROL_PHYCTLWD18", + "OUTBURSTPENDING3": "CMT_PHY_CONTROL_OUTBURSTPENDING3", + "TESTINPUT5": "CMT_PHY_CONTROL_TESTINPUT5", + "TESTINPUT7": "CMT_PHY_CONTROL_TESTINPUT7", + "PHYCTLWD26": "CMT_PHY_CONTROL_PHYCTLWD26" + }, + "type": "PHY_CONTROL", + "prefix": "PHY_CONTROL", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", + "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", + "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", + "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", + "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", + "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", + "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", + "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", + "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", + "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", + "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", + "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", + "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", + "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", + "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3", + "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", + "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", + "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", + "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", + "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", + "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", + "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", + "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", + "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", + "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", + "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", + "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", + "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", + "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", + "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", + "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", + "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", + "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", + "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", + "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", + "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", + "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", + "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", + "OCLK": "CMT_PHASER_OUT_CA_OCLK", + "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", + "RST": "CMT_PHASER_OUT_CA_RST", + "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", + "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", + "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", + "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", + "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", + "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", + "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", + "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", + "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", + "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", + "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", + "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", + "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", + "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", + "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", + "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", + "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE" + }, + "type": "PHASER_OUT_PHY", + "prefix": "PHASER_OUT_PHY", + "name": "X0Y8", + "x_coord": 0, + "y_coord": 8 + }, + { + "site_pins": { + "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", + "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", + "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", + "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", + "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", + "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", + "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", + "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", + "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", + "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", + "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", + "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", + "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", + "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", + "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", + "RCLK": "CMT_PHASER_IN_CA_RCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", + "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", + "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", + "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", + "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", + "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", + "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", + "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", + "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", + "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", + "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", + "STG1READ": "CMT_PHASER_IN_CA_STG1READ", + "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", + "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", + "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", + "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", + "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", + "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", + "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", + "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", + "SCANENB": "CMT_PHASER_IN_CA_SCANENB", + "FINEINC": "CMT_PHASER_IN_CA_FINEINC", + "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", + "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", + "ICLK": "CMT_PHASER_IN_CA_ICLK", + "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", + "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", + "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", + "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", + "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", + "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", + "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", + "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", + "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", + "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", + "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", + "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", + "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", + "RST": "CMT_PHASER_IN_CA_RST", + "SCANIN": "CMT_PHASER_IN_CA_SCANIN", + "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", + "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", + "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", + "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", + "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE", + "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", + "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", + "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", + "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", + "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", + "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", + "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", + "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", + "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", + "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", + "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", + "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", + "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", + "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", + "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", + "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", + "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", + "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", + "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", + "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST" + }, + "type": "PHASER_IN_PHY", + "prefix": "PHASER_IN_PHY", + "name": "X0Y8", + "x_coord": 0, + "y_coord": 8 + }, + { + "site_pins": { + "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", + "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", + "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", + "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", + "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", + "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", + "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", + "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", + "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", + "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", + "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", + "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", + "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", + "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", + "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", + "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", + "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", + "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3", + "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", + "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", + "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", + "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", + "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", + "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", + "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", + "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", + "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", + "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", + "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", + "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", + "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", + "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", + "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", + "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", + "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", + "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", + "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", + "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", + "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", + "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", + "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", + "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", + "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", + "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", + "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", + "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", + "OCLK": "CMT_PHASER_OUT_DB_OCLK", + "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", + "RST": "CMT_PHASER_OUT_DB_RST", + "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", + "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", + "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", + "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", + "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", + "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", + "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", + "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", + "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", + "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", + "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", + "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", + "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", + "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", + "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", + "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", + "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", + "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", + "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", + "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE" + }, + "type": "PHASER_OUT_PHY", + "prefix": "PHASER_OUT_PHY", + "name": "X0Y9", + "x_coord": 0, + "y_coord": 9 + }, + { + "site_pins": { + "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", + "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", + "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", + "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", + "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", + "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", + "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", + "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", + "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", + "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", + "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", + "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", + "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", + "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", + "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", + "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", + "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", + "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", + "RCLK": "CMT_PHASER_IN_DB_RCLK", + "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", + "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", + "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", + "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", + "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", + "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", + "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", + "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", + "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", + "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", + "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", + "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", + "STG1READ": "CMT_PHASER_IN_DB_STG1READ", + "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", + "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", + "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", + "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", + "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", + "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", + "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", + "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", + "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", + "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", + "SCANENB": "CMT_PHASER_IN_DB_SCANENB", + "FINEINC": "CMT_PHASER_IN_DB_FINEINC", + "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", + "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", + "ICLK": "CMT_PHASER_IN_DB_ICLK", + "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", + "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", + "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", + "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", + "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", + "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", + "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", + "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", + "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", + "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", + "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", + "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", + "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", + "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", + "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", + "RST": "CMT_PHASER_IN_DB_RST", + "SCANIN": "CMT_PHASER_IN_DB_SCANIN", + "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", + "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", + "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", + "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", + "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE", + "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", + "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", + "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", + "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", + "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", + "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", + "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", + "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", + "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", + "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", + "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", + "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", + "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", + "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", + "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", + "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", + "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", + "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", + "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", + "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", + "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", + "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", + "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST" + }, + "type": "PHASER_IN_PHY", + "prefix": "PHASER_IN_PHY", + "name": "X0Y9", + "x_coord": 0, + "y_coord": 9 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_CMT_TOP_R_UPPER_T.json b/artix7/tile_type_CMT_TOP_R_UPPER_T.json index 147f41e..ef7676c 100644 --- a/artix7/tile_type_CMT_TOP_R_UPPER_T.json +++ b/artix7/tile_type_CMT_TOP_R_UPPER_T.json @@ -1,4422 +1,4422 @@ { - "wires": [ - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_EE2A0_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_IMUX44_11", - "CMT_TOP_BYP5_2", - "CMT_TOP_EE2A3_5", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX19_0", - "CMT_TOP_LH11_4", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2END3_7", - "CMT_TOP_BYP6_0", - "CMT_TOP_CTRL1_12", - "CMT_TOP_NW2A2_9", - "CMT_TOP_EE4C1_11", - "CMT_TOP_NE2A1_8", - "CMT_TOP_IMUX44_1", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_IMUX39_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_IMUX44_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", - "CMT_TOP_NW2A0_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_NW4A0_2", - "CMT_TOP_WW2END0_8", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SE4BEG1_8", - "CMT_PLL_PHASERD_CTSBUS1", - "CMT_TOP_WW4A2_2", - "CMT_TOP_IMUX23_0", - "CMT_TOP_WW4C0_8", - "CMT_TOP_BYP6_1", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_SE2A0_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_SW2A2_1", - "CMT_TOP_FAN0_1", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_WW4END0_6", - "CMT_TOP_SW2A1_4", - "CMT_TOP_WW4A1_12", - "CMT_TOP_EE2A2_10", - "CMT_TOP_NW4END2_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", - "CMT_TOP_LH6_12", - "CMT_TOP_SE2A0_12", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_EE4B1_10", - "CMT_TOP_BYP5_3", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_WW4B0_10", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_WW4C2_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_SW4A2_12", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX14_3", - "CMT_TOP_BYP7_6", - "CMT_TOP_NW2A2_8", - "CMT_TOP_SE2A1_0", - "CMT_TOP_CTRL1_4", - "CMT_TOP_ICLK_11", - "CMT_TOP_IMUX0_0", - "CMT_TOP_FAN7_11", - "CMT_TOP_IMUX15_11", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_NW4END1_8", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_EE4C0_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_IMUX10_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_NE4C0_0", - "CMT_TOP_EE2A1_11", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_LH11_12", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_SW2A2_12", - "CMT_TOP_WW4END0_3", - "CMT_TOP_IMUX28_9", - "CMT_TOP_NE4C3_6", - "CMT_TOP_LH9_1", - "CMT_TOP_EE4A3_1", - "CMT_TOP_WW2A0_6", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", - "CMT_TOP_IMUX10_4", - "CMT_TOP_BYP0_1", - "CMT_TOP_NE2A0_4", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX19_10", - "CMT_TOP_IMUX45_6", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_LH10_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_R_UPPER_T_PLLE2_RST", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_WW4B3_11", - "CMT_TOP_NW4A3_1", - "CMT_TOP_EE4A2_6", - "CMT_TOP_WL1END0_10", - "CMT_TOP_SW2A3_4", - "CMT_TOP_IMUX41_11", - "CMT_TOP_OCLK_2", - "CMT_TOP_SE4C3_11", - "CMT_TOP_EE4B2_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "CMT_TOP_SE2A0_2", - "CMT_TOP_IMUX14_12", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LH11_7", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX12_6", - "CMT_TOP_SW4END3_6", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_WW2END1_1", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_IMUX29_11", - "CMT_TOP_WL1END2_5", - "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_WR1END1_8", - "CMT_TOP_IMUX12_5", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_IMUX42_5", - "CMT_TOP_R_UPPER_T_CLKPLL2", - "CMT_TOP_IMUX39_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX10_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_IMUX5_8", - "CMT_TOP_EE4B3_8", - "CMT_TOP_WW2A1_1", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX2_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_SW2A2_11", - "CMT_TOP_IMUX47_5", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_WW4B1_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_WR1END2_11", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX6_6", - "CMT_TOP_SW4END1_0", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX30_10", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_WL1END3_6", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_SE2A2_0", - "CMT_TOP_IMUX27_0", - "CMT_TOP_SE2A2_8", - "CMT_TOP_IMUX26_10", - "CMT_TOP_WW2END2_7", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_WR1END3_7", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_IMUX39_9", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_EE4B3_12", - "CMT_TOP_LH11_8", - "CMT_TOP_WW4END2_4", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "CMT_TOP_EE2A3_12", - "CMT_TOP_WW4A0_8", - "CMT_TOP_LH1_6", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX17_6", - "CMT_TOP_EE2A0_10", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_R_UPPER_T_CLKPLL7", - "CMT_TOP_IMUX37_11", - "CMT_TOP_EE4B2_9", - "CMT_TOP_SE4C1_10", - "CMT_TOP_LH5_5", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_EE2A2_5", - "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "CMT_TOP_LH4_8", - "CMT_TOP_IMUX45_1", - "CMT_TOP_SW4A0_4", - "CMT_TOP_FAN2_4", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX19_5", - "CMT_TOP_EE4B1_0", - "CMT_TOP_NW4END3_10", - "CMT_TOP_BYP7_7", - "CMT_TOP_IMUX7_12", - "CMT_TOP_BYP3_9", - "CMT_TOP_EE4B0_9", - "CMT_TOP_WR1END1_12", - "CMT_TOP_IMUX25_10", - "CMT_TOP_WR1END0_3", - "CMT_TOP_SW4A2_8", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_SW4A0_3", - "CMT_TOP_CLK0_6", - "CMT_TOP_IMUX3_12", - "CMT_TOP_SE2A3_4", - "CMT_TOP_FAN7_9", - "CMT_PLL_PHASERREF1", - "CMT_TOP_IMUX39_10", - "CMT_TOP_LH7_6", - "CMT_TOP_EE2A2_11", - "CMT_TOP_IMUX41_1", - "CMT_TOP_NE4C2_7", - "CMT_TOP_SW4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LH7_8", - "CMT_TOP_WR1END2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_12", - "CMT_TOP_FAN6_3", - "CMT_TOP_WW2A0_7", - "CMT_TOP_BYP4_2", - "CMT_TOP_IMUX33_11", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_WW4END0_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_WW4A0_7", - "CMT_TOP_LH9_3", - "CMT_TOP_NE2A0_5", - "CMT_TOP_EE4C3_2", - "CMT_TOP_LH5_10", - "CMT_TOP_NE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_EE4C1_3", - "CMT_TOP_SW4A1_8", - "CMT_TOP_CTRL0_8", - "CMT_TOP_NW2A0_4", - "CMT_TOP_IMUX1_12", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX21_9", - "CMT_TOP_WL1END1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LH4_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_CTRL1_0", - "CMT_TOP_LH11_10", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_SE2A3_11", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_SW2A3_0", - "CMT_TOP_BYP7_5", - "CMT_TOP_ICLK_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", - "CMT_TOP_WW4C3_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_FAN1_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", - "CMT_TOP_SW4END1_4", - "CMT_TOP_EE4C3_3", - "CMT_TOP_BYP0_12", - "CMT_TOP_WW4B1_12", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX9_5", - "CMT_TOP_WW4B1_11", - "CMT_TOP_IMUX13_9", - "CMT_TOP_FAN6_8", - "CMT_TOP_SE2A2_10", - "CMT_TOP_WW4A0_0", - "CMT_TOP_CTRL0_5", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_WW2A1_11", - "CMT_TOP_IMUX14_10", - "CMT_TOP_IMUX14_2", - "CMT_TOP_EE4B0_8", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX40_1", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX38_12", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_WW2A0_12", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_BYP7_2", - "CMT_TOP_SE4C1_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX15_4", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_IMUX23_3", - "CMT_TOP_WW2A2_3", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_EE4A1_7", - "CMT_TOP_IMUX31_3", - "CMT_TOP_EE4B3_11", - "CMT_TOP_IMUX25_8", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_EE2A3_11", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX12_9", - "CMT_TOP_EE2A1_10", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NW2A3_0", - "CMT_TOP_SW4A3_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", - "CMT_TOP_WL1END0_3", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_WW2A3_5", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_WW2END1_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", - "CMT_TOP_SW2A2_5", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", - "CMT_TOP_IMUX28_11", - "CMT_TOP_IMUX42_11", - "CMT_TOP_WW2END2_10", - "CMT_TOP_EE4B3_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_LH10_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", - "CMT_TOP_IMUX47_9", - "CMT_TOP_LH10_1", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_IMUX17_1", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_BYP4_0", - "CMT_TOP_FAN2_9", - "CMT_TOP_SE4C3_8", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NE2A2_1", - "CMT_TOP_IMUX37_5", - "CMT_TOP_IMUX7_7", - "CMT_TOP_LH8_12", - "CMT_TOP_IMUX20_6", - "CMT_TOP_WW4C1_9", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_SE4C3_4", - "CMT_TOP_NE4C3_11", - "CMT_TOP_IMUX33_5", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_EE4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BYP5_4", - "CMT_TOP_LH10_9", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_NW4A1_10", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_IMUX25_9", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EE4B0_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", - "CMT_TOP_WW4END3_2", - "CMT_TOP_IMUX30_8", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_IMUX47_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", - "CMT_TOP_IMUX16_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END1_6", - "CMT_TOP_IMUX11_11", - "CMT_TOP_WW2A0_11", - "CMT_TOP_R_UPPER_T_CLKPLL3", - "CMT_TOP_SW4END2_7", - "CMT_TOP_IMUX34_4", - "CMT_TOP_LH12_0", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_SW4A3_11", - "CMT_TOP_NW4END2_8", - "CMT_TOP_IMUX36_0", - "CMT_TOP_FAN7_8", - "CMT_TOP_LH3_3", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_SE4C0_10", - "CMT_TOP_IMUX28_7", - "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "CMT_TOP_IMUX10_5", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_NW4END2_12", - "CMT_TOP_WW2A3_0", - "CMT_TOP_LH3_4", - "CMT_TOP_IMUX16_6", - "CMT_TOP_FAN2_11", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX40_4", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_IMUX38_0", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_PLL_PHASER_OUT_D_OCLK", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_WW4A1_10", - "CMT_TOP_NW4A3_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "CMT_TOP_SW4END3_9", - "CMT_TOP_SW4END3_2", - "CMT_TOP_LH8_5", - "CMT_TOP_EE4B2_10", - "CMT_TOP_WW2A2_5", - "CMT_TOP_IMUX29_0", - "CMT_TOP_EE4A0_8", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_IMUX16_7", - "CMT_TOP_NW4END0_2", - "CMT_TOP_FAN1_1", - "CMT_TOP_LH1_4", - "CMT_TOP_SW2A2_9", - "CMT_TOP_FAN2_12", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_IMUX45_9", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_WR1END0_12", - "CMT_TOP_SE4C0_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", - "CMT_TOP_IMUX46_3", - "CMT_TOP_SW4END2_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", - "CMT_TOP_WW4B3_5", - "CMT_TOP_IMUX6_7", - "PLL_CLK_FREQ_BB_BUFOUT_NS2", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_NW4A0_7", - "CMT_TOP_EE4A1_6", - "CMT_TOP_FAN2_0", - "CMT_TOP_WW4A0_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX37_2", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_WW2A0_1", - "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_IMUX45_8", - "CMT_TOP_FAN0_4", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SE4C0_3", - "CMT_TOP_IMUX22_12", - "CMT_TOP_IMUX29_6", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WW2END1_2", - "CMT_TOP_SE4BEG3_12", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_SW4A1_6", - "CMT_TOP_IMUX36_12", - "CMT_TOP_FAN5_12", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_FAN3_9", - "CMT_TOP_EE4A1_3", - "CMT_TOP_OCLK_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", - "CMT_TOP_WW2END2_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_SE4BEG0_12", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "CMT_TOP_WW4END3_9", - "CMT_TOP_IMUX26_1", - "CMT_TOP_CLK1_2", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_IMUX31_10", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_IMUX23_12", - "CMT_PLL_PHASER_OUT_D_OCLK1X_90", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_WL1END0_8", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_IMUX29_7", - "CMT_TOP_NE2A3_6", - "CMT_TOP_WW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "PLL_CLK_FREQ_BB1_NS", - "CMT_TOP_NE2A1_6", - "CMT_TOP_IMUX27_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", - "CMT_TOP_SW4A3_1", - "CMT_TOP_NW2A3_8", - "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "CMT_TOP_LH7_1", - "CMT_TOP_WW4END1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_PLL_PHASER_OUT_D_OCLKDIV", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_IMUX13_2", - "CMT_TOP_WW4END2_7", - "CMT_TOP_NW4END1_0", - "CMT_TOP_EE4C0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_NE4C2_9", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_IMUX29_5", - "CMT_TOP_WW2END0_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX34_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_BYP6_2", - "CMT_TOP_IMUX42_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", - "CMT_TOP_BYP5_5", - "CMT_TOP_WW2A3_10", - "CMT_TOP_IMUX15_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_IMUX2_1", - "CMT_TOP_SE2A2_6", - "CMT_TOP_IMUX12_11", - "CMT_TOP_EE4B1_8", - "CMT_TOP_NE2A3_4", - "CMT_TOP_SW4A3_7", - "CMT_PLL_PHASER_RDENABLE_TOFIFO", - "CMT_TOP_IMUX15_12", - "CMT_TOP_WL1END2_11", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_IMUX24_9", - "CMT_TOP_LH1_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW2A3_1", - "CMT_TOP_EE2A1_0", - "CMT_TOP_WW4C3_5", - "CMT_TOP_IMUX14_11", - "CMT_TOP_BYP1_0", - "CMT_TOP_IMUX24_1", - "PLL_CLK_FREQ_BB0_NS", - "CMT_TOP_WW4B0_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "CMT_TOP_WW4B0_7", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_NE2A1_2", - "CMT_TOP_BYP6_11", - "CMT_TOP_IMUX7_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_CLK0_12", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_IMUX30_4", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_WW2END3_1", - "CMT_TOP_IMUX22_0", - "CMT_TOP_WW2A3_6", - "CMT_TOP_EE4A0_6", - "CMT_TOP_SE4C2_9", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_EE4A0_9", - "CMT_TOP_FAN6_7", - "CMT_TOP_WW4A0_10", - "CMT_TOP_LH5_9", - "CMT_TOP_ICLK_2", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_NW4END3_0", - "CMT_TOP_SW2A1_2", - "CMT_TOP_FAN1_5", - "CMT_TOP_CTRL0_7", - "CMT_TOP_NW4END3_7", - "CMT_TOP_WW2A0_9", - "CMT_TOP_SE4C1_9", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_IMUX44_2", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW2END0_3", - "CMT_TOP_EE4A0_12", - "CMT_TOP_LH10_2", - "CMT_TOP_NE4C2_2", - "CMT_TOP_IMUX9_6", - "CMT_TOP_NW4END3_3", - "CMT_TOP_IMUX45_2", - "CMT_TOP_SW4A2_11", - "CMT_TOP_FAN6_1", - "CMT_TOP_IMUX22_9", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX17_12", - "CMT_TOP_SW4A3_8", - "CMT_TOP_LH12_8", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_NW2A0_12", - "CMT_TOP_IMUX31_11", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_WW4END0_1", - "CMT_TOP_EE4B0_6", - "CMT_TOP_BYP3_0", - "CMT_TOP_EE4B0_7", - "CMT_TOP_LH9_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_SW4END2_0", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NE4C1_1", - "CMT_PLL_DQS_TO_PHASER_D", - "CMT_TOP_EE2A1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX35_1", - "CMT_TOP_WW2END1_8", - "CMT_TOP_IMUX19_9", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_WW4A2_9", - "CMT_TOP_EE4B2_2", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_WW4C3_4", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_NE2A0_6", - "CMT_TOP_BYP1_5", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_IMUX11_10", - "CMT_TOP_FAN1_3", - "CMT_TOP_SE2A3_7", - "CMT_TOP_LH2_6", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_IMUX25_2", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_WR1END3_4", - "CMT_TOP_CTRL1_11", - "CMT_TOP_IMUX26_9", - "CMT_TOP_IMUX35_10", - "CMT_TOP_FAN0_3", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_IMUX18_12", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_WW4B3_10", - "CMT_TOP_NE2A2_8", - "CMT_TOP_FAN0_7", - "CMT_TOP_IMUX32_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "CMT_TOP_LH7_9", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_CLK0_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WW4B1_0", - "CMT_TOP_NE4BEG1_1", - "PLL_CLK_FREQ_BB2_NS", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_BYP6_5", - "CMT_TOP_WW2A0_10", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_IMUX39_2", - "CMT_TOP_SW4A1_11", - "CMT_TOP_WR1END3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_CTRL0_4", - "CMT_TOP_LH4_5", - "CMT_TOP_SW4END1_7", - "CMT_TOP_NW4END3_4", - "CMT_TOP_EE4C3_4", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_IMUX46_10", - "CMT_TOP_NW4A0_5", - "CMT_TOP_SW2A0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_IMUX2_11", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_IMUX0_3", - "CMT_PLL_PHASERD_DQSBUS1", - "CMT_TOP_OCLK_5", - "CMT_TOP_FAN5_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_EE2A1_12", - "CMT_TOP_WL1END0_2", - "CMT_TOP_BYP0_5", - "CMT_TOP_NW2A0_10", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_EE2A2_7", - "CMT_TOP_SE2A2_2", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_SW4A2_1", - "CMT_TOP_IMUX9_4", - "CMT_TOP_WW4A3_11", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SW4END0_3", - "CMT_TOP_IMUX46_0", - "CMT_TOP_WW2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LH7_0", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_WW2A2_0", - "CMT_TOP_IMUX34_11", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_CTRL0_2", - "CMT_TOP_IMUX23_9", - "CMT_TOP_WL1END1_3", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_WW4A2_10", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_SW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX29_12", - "CMT_TOP_IMUX35_11", - "CMT_TOP_NE2A3_5", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_NW2A1_1", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP5_7", - "CMT_TOP_IMUX6_1", - "CMT_TOP_LH4_10", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SW2A3_7", - "CMT_TOP_WW4C3_10", - "CMT_TOP_LH3_12", - "CMT_TOP_WW4END1_10", - "CMT_TOP_IMUX44_0", - "CMT_TOP_BYP7_11", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX28_1", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LH8_1", - "CMT_TOP_WW4A0_3", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_CLK1_0", - "CMT_TOP_IMUX2_10", - "CMT_TOP_SW4A0_9", - "CMT_TOP_IMUX27_4", - "CMT_TOP_SW4A1_7", - "CMT_TOP_IMUX40_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EE4C3_12", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_NW2A0_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_NW4A1_7", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_WW2A1_9", - "CMT_TOP_BYP1_11", - "CMT_TOP_SE4C2_7", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_NE4C1_7", - "CMT_TOP_WW4B2_1", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_NE4C0_11", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_SE2A3_2", - "CMT_TOP_LH8_3", - "CMT_TOP_IMUX13_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_BLOCK_OUTS_L_B0_12", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_IMUX30_7", - "CMT_TOP_WW4C3_2", - "CMT_TOP_SW4END1_8", - "CMT_TOP_EE4B0_2", - "CMT_TOP_BYP6_10", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "CMT_TOP_LH5_1", - "CMT_TOP_EE4B2_11", - "CMT_TOP_BYP4_9", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_SE2A1_10", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_WR1END3_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LH8_10", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_IMUX13_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", - "CMT_TOP_IMUX34_7", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_NW4A2_7", - "CMT_TOP_LH9_11", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EE2A2_1", - "CMT_TOP_FAN4_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", - "CMT_TOP_EE4B3_9", - "CMT_TOP_BYP3_11", - "CMT_TOP_WW4END1_1", - "CMT_TOP_FAN0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_BYP0_11", - "CMT_TOP_NE4C0_5", - "CMT_TOP_SW2A0_8", - "CMT_TOP_NW2A2_2", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX0_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_IMUX37_12", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_BYP4_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_EE2A1_6", - "CMT_TOP_NE2A1_5", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_IMUX21_12", - "CMT_TOP_FAN3_4", - "CMT_TOP_LH7_5", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX17_11", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_R_UPPER_T_FREQ_BB2", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_IMUX43_8", - "CMT_TOP_SE2A3_5", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4C1_6", - "CMT_TOP_WW4C0_2", - "CMT_TOP_LH12_7", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_EE2A1_9", - "CMT_TOP_WW2END2_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_BYP4_5", - "CMT_TOP_IMUX22_3", - "CMT_TOP_NE2A2_6", - "CMT_TOP_FAN5_10", - "CMT_TOP_EE4A0_7", - "CMT_TOP_WW2END1_10", - "CMT_TOP_IMUX19_12", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_IMUX38_11", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WW4B2_5", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_NE2A2_9", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", - "CMT_TOP_FAN0_12", - "CMT_TOP_IMUX2_8", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WW2A2_10", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_IMUX28_2", - "CMT_TOP_WW4C1_4", - "CMT_TOP_EE4C2_7", - "CMT_TOP_LH12_1", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE4C0_4", - "CMT_TOP_LH11_0", - "CMT_TOP_WW2A1_2", - "CMT_TOP_FAN6_2", - "CMT_TOP_IMUX22_7", - "CMT_TOP_WW2END3_4", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SE2A2_4", - "CMT_TOP_NW4END0_12", - "CMT_TOP_SW4A1_0", - "CMT_TOP_IMUX1_8", - "CMT_TOP_WW4C2_4", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_2", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_IMUX20_11", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4END3_10", - "CMT_TOP_CLK0_2", - "CMT_TOP_IMUX11_2", - "CMT_TOP_WW2END0_5", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_WW4B1_1", - "CMT_TOP_LH6_7", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE4B2_8", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_WW4A3_6", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_BYP5_11", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_EE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_CLK1_3", - "CMT_TOP_IMUX34_0", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_IMUX30_11", - "CMT_TOP_SE2A3_8", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX30_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_FAN7_3", - "CMT_TOP_IMUX33_6", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_NW4END1_9", - "CMT_TOP_WW4END2_10", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", - "CMT_TOP_SW4END0_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_WW4END1_6", - "CMT_TOP_IMUX16_10", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", - "CMT_TOP_WR1END3_1", - "CMT_TOP_IMUX26_11", - "CMT_TOP_NE2A0_0", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX28_6", - "CMT_TOP_SE4C2_11", - "CMT_TOP_EE4A2_2", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX24_0", - "CMT_TOP_NW4END2_4", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW4C3_3", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", - "CMT_TOP_EE4C3_5", - "CMT_TOP_SE2A0_8", - "CMT_TOP_IMUX0_2", - "CMT_TOP_EE4C0_5", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SW4END2_12", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX36_4", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_WR1END1_4", - "CMT_TOP_SW4END0_11", - "CMT_TOP_LH5_8", - "CMT_TOP_LH8_9", - "CMT_TOP_IMUX21_0", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "CMT_TOP_WL1END0_7", - "CMT_TOP_SW2A0_6", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_WW4END3_6", - "CMT_TOP_IMUX7_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_EE2A1_5", - "CMT_TOP_NW2A0_8", - "CMT_TOP_WL1END0_12", - "CMT_TOP_IMUX21_10", - "CMT_TOP_SW2A2_6", - "CMT_TOP_IMUX26_0", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_IMUX23_1", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_WW4C1_12", - "CMT_TOP_IMUX3_6", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_BYP0_0", - "CMT_TOP_SW4END0_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_ICLK_12", - "CMT_TOP_IMUX40_12", - "CMT_TOP_BYP3_4", - "CMT_TOP_WW4C2_1", - "CMT_TOP_BYP1_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX24_12", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_IMUX43_3", - "CMT_TOP_NW4A2_8", - "CMT_TOP_WR1END3_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", - "CMT_TOP_WW4C3_12", - "CMT_TOP_ICLK_5", - "CMT_TOP_IMUX0_12", - "CMT_TOP_WW2END2_4", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_IMUX18_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_NW4A2_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_NW4END0_11", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", - "CMT_TOP_WW4C2_11", - "CMT_TOP_IMUX18_5", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SW2A1_1", - "CMT_TOP_EE4C0_12", - "CMT_TOP_BYP3_10", - "CMT_TOP_IMUX16_12", - "CMT_TOP_EE4A3_4", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX20_5", - "CMT_TOP_NW2A2_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_IMUX24_8", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LH3_5", - "CMT_TOP_IMUX26_2", - "CMT_TOP_WW4A0_11", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "CMT_TOP_IMUX19_8", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_SE2A1_3", - "CMT_TOP_WL1END1_12", - "CMT_TOP_BYP4_11", - "CMT_TOP_NW4A3_10", - "CMT_TOP_FAN1_7", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_WW4A2_0", - "CMT_TOP_IMUX28_10", - "CMT_TOP_NW4A2_12", - "CMT_TOP_NE4C1_10", - "CMT_TOP_WW2A3_9", - "CMT_TOP_EE4A1_4", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX33_12", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_IMUX46_5", - "CMT_TOP_NE2A0_1", - "CMT_TOP_LH10_12", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_WR1END2_8", - "CMT_TOP_IMUX10_12", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX26_7", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_NW4END2_10", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2A3_6", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_FAN3_8", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_NW4END0_1", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_FAN3_6", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_EE2A3_10", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_SW4END3_1", - "CMT_TOP_IMUX22_11", - "CMT_TOP_WW4A2_7", - "CMT_TOP_NW4A2_1", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW4C3_8", - "CMT_TOP_NE2A0_8", - "CMT_TOP_IMUX12_10", - "CMT_TOP_WW4C3_9", - "CMT_TOP_NE2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_FAN5_9", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_FAN3_0", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_3", - "CMT_TOP_SW2A0_7", - "CMT_TOP_NE4C0_1", - "CMT_TOP_IMUX3_1", - "CMT_TOP_WL1END3_4", - "CMT_TOP_IMUX37_9", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_NW4END3_5", - "CMT_TOP_WW2A2_7", - "CMT_TOP_FAN2_5", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WL1END3_0", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_IMUX36_1", - "CMT_TOP_SW2A1_9", - "CMT_TOP_EE4A3_2", - "CMT_TOP_IMUX15_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LH3_6", - "CMT_TOP_IMUX27_6", - "CMT_TOP_WW2END2_0", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX43_2", - "CMT_TOP_NE4C3_9", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C1_6", - "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "CMT_TOP_WW4B2_9", - "CMT_TOP_IMUX4_5", - "CMT_TOP_EE4C0_9", - "CMT_TOP_BYP7_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_WR1END2_10", - "CMT_TOP_NE4C1_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_SW2A3_12", - "CMT_TOP_WW2A0_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", - "CMT_TOP_SE4C2_8", - "CMT_TOP_IMUX26_12", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "CMT_TOP_IMUX38_8", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_LH1_3", - "CMT_TOP_BYP1_2", - "CMT_TOP_IMUX26_5", - "CMT_TOP_SE4C3_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_NE4C0_10", - "CMT_TOP_WW4C0_12", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", - "CMT_TOP_IMUX12_3", - "CMT_TOP_WW4C0_1", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_IMUX38_6", - "CMT_TOP_LH6_10", - "CMT_TOP_FAN3_12", - "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_WW4B3_4", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_IMUX1_10", - "CMT_TOP_WW2END0_9", - "CMT_TOP_SE2A0_9", - "CMT_TOP_WW4B0_12", - "CMT_PHASER_D_OCLK_TOIOI", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX36_7", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_IMUX39_8", - "CMT_TOP_WW4B0_5", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_BYP4_7", - "CMT_TOP_IMUX43_9", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_WW2END3_10", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_IMUX12_12", - "CMT_TOP_SW2A0_5", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_LH4_12", - "CMT_TOP_SW4END1_9", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_FAN0_2", - "CMT_TOP_IMUX19_1", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_NW2A3_11", - "CMT_TOP_IMUX41_0", - "CMT_TOP_FAN3_2", - "CMT_TOP_WW4END0_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_SW2A3_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SE2A1_11", - "CMT_TOP_WW4A0_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_EE4B0_0", - "CMT_TOP_NW4A1_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CMT_TOP_NW2A3_3", - "CMT_TOP_SE4C0_8", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4END2_3", - "CMT_TOP_NE2A3_10", - "CMT_TOP_LH1_5", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_WW4B2_10", - "CMT_TOP_SW4END2_1", - "CMT_TOP_EE4B3_4", - "CMT_TOP_SW4END1_3", - "CMT_TOP_IMUX25_6", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LH9_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX37_3", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_LH1_9", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_SW4A3_12", - "CMT_TOP_EE4C2_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", - "CMT_TOP_IMUX36_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_WW4A3_3", - "CMT_TOP_LH2_8", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX39_12", - "CMT_TOP_IMUX29_8", - "CMT_TOP_FAN7_12", - "CMT_TOP_IMUX34_10", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_WW4A3_2", - "CMT_TOP_EE4B1_12", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_EE4A0_2", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_LH12_12", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_NE2A2_11", - "CMT_TOP_LH3_1", - "CMT_TOP_SW4A3_5", - "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_WW4END1_5", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX11_8", - "CMT_TOP_NW4END2_11", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX8_2", - "CMT_TOP_EL1BEG1_12", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_WW2A3_3", - "CMT_TOP_EE4A2_3", - "CMT_TOP_SW4A1_1", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_8", - "CMT_TOP_WW4A1_6", - "CMT_TOP_IMUX41_2", - "CMT_TOP_LH8_6", - "CMT_TOP_SE4C1_8", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WW4A2_6", - "CMT_TOP_BYP0_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", - "CMT_TOP_IMUX43_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX42_12", - "CMT_TOP_WR1END2_1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", - "CMT_TOP_NW4END3_11", - "CMT_TOP_WR1END3_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", - "CMT_TOP_NW4A0_4", - "CMT_TOP_IMUX24_4", - "CMT_TOP_EE4C1_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WW4C1_8", - "CMT_TOP_NW2A0_7", - "CMT_TOP_LH1_11", - "CMT_TOP_IMUX22_1", - "CMT_TOP_IMUX17_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_IMUX19_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX10_9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", - "CMT_TOP_EE2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_IMUX11_12", - "CMT_TOP_CLK1_4", - "CMT_TOP_LH2_2", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4C2_3", - "CMT_TOP_EE4A2_7", - "CMT_TOP_IMUX11_0", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_IMUX38_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_10", - "CMT_TOP_LH3_9", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_10", - "CMT_TOP_NW4END2_2", - "CMT_TOP_WW2A2_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_LH4_9", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4B0_6", - "CMT_TOP_BYP1_9", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_NW4A1_5", - "CMT_TOP_SE4C3_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_SE4BEG2_12", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_SW4END3_10", - "CMT_TOP_IMUX9_1", - "CMT_TOP_NW4A1_9", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_BYP7_8", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX46_7", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_IMUX30_1", - "CMT_TOP_WW4C0_5", - "CMT_TOP_NW4A1_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", - "CMT_TOP_WW2END0_2", - "CMT_TOP_FAN0_0", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX18_8", - "CMT_TOP_NW4A1_12", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX20_4", - "CMT_TOP_EE4C3_6", - "CMT_TOP_R_UPPER_T_CLKIN2", - "CMT_TOP_FAN6_12", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_IMUX39_11", - "CMT_TOP_NE4C0_2", - "CMT_TOP_EE4B1_2", - "CMT_TOP_IMUX4_9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SE4C1_1", - "CMT_TOP_EE4A1_9", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "CMT_TOP_IMUX30_2", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_EE2A2_2", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4A2_8", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_IMUX23_8", - "CMT_TOP_SW4END0_6", - "CMT_TOP_IMUX12_2", - "CMT_TOP_NW2A2_7", - "CMT_TOP_WL1END2_7", - "CMT_TOP_BYP5_1", - "CMT_TOP_EE4B1_9", - "CMT_TOP_IMUX2_12", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "CMT_TOP_IMUX33_0", - "CMT_TOP_WW2A2_9", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_OCLK_7", - "CMT_TOP_FAN1_10", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_SW2A1_10", - "CMT_TOP_IMUX19_7", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_SE4C0_6", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_IMUX3_0", - "CMT_TOP_WL1END1_8", - "CMT_TOP_NW4END1_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_LH6_2", - "CMT_TOP_IMUX39_6", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_IMUX36_2", - "CMT_TOP_WW2A0_5", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_BYP2_0", - "CMT_TOP_IMUX8_3", - "CMT_TOP_ICLK_6", - "CMT_TOP_LH2_0", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX40_2", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_WW4END3_1", - "CMT_TOP_SW4A2_4", - "CMT_TOP_LH11_11", - "CMT_TOP_IMUX46_2", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NW4A3_2", - "CMT_TOP_IMUX17_10", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX30_12", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW4END1_3", - "CMT_PLL_PHASER_WRCLK_TOFIFO", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_NW2A3_7", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_NW4A3_8", - "CMT_TOP_SW4END2_8", - "CMT_TOP_WL1END3_12", - "CMT_TOP_SE2A0_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_EE4A1_12", - "CMT_TOP_WW2END0_7", - "CMT_TOP_EE4C0_6", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_EE4C0_7", - "CMT_TOP_WL1END0_0", - "CMT_PHASER_D_ICLK_TOIOI", - "CMT_TOP_FAN7_2", - "CMT_TOP_WL1END3_1", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_LH8_4", - "CMT_TOP_LH5_6", - "CMT_TOP_BYP2_11", - "CMT_TOP_SW4A0_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", - "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_WR1END2_12", - "CMT_TOP_BYP7_4", - "CMT_TOP_EE4C2_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", - "CMT_TOP_LH10_6", - "CMT_TOP_SE4C2_4", - "CMT_TOP_FAN1_12", - "CMT_TOP_IMUX35_9", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LH4_2", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX6_12", - "CMT_TOP_EE4A3_8", - "CMT_TOP_IMUX44_3", - "CMT_PLL_PHASERREF0", - "CMT_TOP_IMUX24_2", - "CMT_TOP_EE4A3_11", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX34_5", - "CMT_TOP_NW4END2_9", - "CMT_TOP_IMUX20_9", - "CMT_TOP_IMUX29_1", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_SW4A2_3", - "CMT_TOP_FAN1_9", - "CMT_TOP_BYP7_1", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WL1END3_8", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX19_6", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX17_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_OCLK_0", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX13_11", - "CMT_TOP_WL1END1_11", - "CMT_TOP_IMUX2_2", - "CMT_TOP_WW4END3_5", - "CMT_TOP_LH1_1", - "CMT_TOP_FAN5_8", - "CMT_TOP_NW4END3_8", - "CMT_TOP_WW4A1_1", - "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_EE2A3_2", - "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_WW2END2_3", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_WW2END2_6", - "CMT_TOP_IMUX41_10", - "CMT_TOP_EE4B2_1", - "CMT_TOP_NW4END3_1", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_12", - "CMT_TOP_LH3_0", - "PLL_CLK_FREQ_BB3_NS", - "CMT_TOP_LH2_5", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_EE4A3_3", - "CMT_TOP_NW4A2_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SE4C0_12", - "CMT_TOP_IMUX34_8", - "CMT_TOP_SW4A2_10", - "CMT_TOP_NW2A3_1", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX32_11", - "CMT_TOP_WW4B3_7", - "CMT_TOP_LH11_9", - "CMT_TOP_NE2A2_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_NW4A2_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_WW4C2_10", - "CMT_TOP_BYP7_0", - "CMT_TOP_LH6_0", - "CMT_TOP_NE4C1_4", - "CMT_TOP_IMUX16_9", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_EE4A0_10", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_IMUX5_2", - "CMT_TOP_WW4C0_10", - "CMT_PLL_PHYCTRL_SYNC_BB_UP", - "CMT_TOP_FAN1_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_WW4B2_6", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_IMUX29_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LH3_11", - "CMT_TOP_IMUX32_7", - "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_BYP2_3", - "CMT_TOP_IMUX1_6", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX20_3", - "CMT_TOP_LH7_3", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX28_8", - "CMT_TOP_NW4END2_5", - "CMT_TOP_WW2A0_3", - "CMT_TOP_IMUX33_9", - "CMT_TOP_WR1END1_9", - "PLL_CLK_FREQ_BB_BUFOUT_NS1", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX23_11", - "CMT_TOP_SW4END2_4", - "CMT_TOP_FAN6_0", - "CMT_TOP_LH6_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_IMUX4_3", - "CMT_TOP_WL1END2_12", - "CMT_TOP_SW4END3_3", - "CMT_TOP_WW4B0_3", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP3_2", - "CMT_TOP_CTRL0_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_CLK1_8", - "CMT_TOP_FAN3_3", - "CMT_TOP_EE4A3_6", - "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_IMUX42_0", - "CMT_TOP_LH12_4", - "CMT_TOP_SW2A0_9", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_FAN0_6", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_SW4END0_1", - "CMT_TOP_FAN5_11", - "CMT_TOP_R_UPPER_T_CLKFBIN", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "CMT_TOP_R_UPPER_T_FREQ_BB3", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_IMUX1_0", - "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", - "CMT_TOP_NW2A3_4", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_WW4END1_9", - "CMT_TOP_EE2A2_4", - "CMT_TOP_WL1END0_4", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_IMUX4_10", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_IMUX34_12", - "CMT_TOP_SW4END3_4", - "CMT_TOP_WW4C3_1", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_WL1END0_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "CMT_TOP_EE4A0_3", - "CMT_TOP_NW4A3_6", - "CMT_TOP_LH7_12", - "CMT_TOP_BYP2_5", - "CMT_TOP_ICLK_0", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LH6_9", - "CMT_TOP_CTRL1_9", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "CMT_TOP_IMUX33_4", - "CMT_TOP_NW2A1_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_EE4B0_4", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_IMUX1_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_WR1END0_6", - "CMT_TOP_LH12_2", - "CMT_TOP_FAN5_5", - "CMT_TOP_IMUX4_8", - "CMT_TOP_SW2A2_7", - "CMT_TOP_IMUX43_6", - "CMT_PLL_PHASER_RDCLK_TOFIFO", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WL1END1_10", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", - "CMT_TOP_BYP6_3", - "CMT_TOP_FAN2_6", - "CMT_TOP_WR1END1_1", - "CMT_TOP_OCLK_3", - "CMT_TOP_EE4C2_8", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_IMUX31_9", - "CMT_TOP_IMUX30_0", - "CMT_TOP_OCLK_8", - "CMT_TOP_FAN4_3", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_LH4_4", - "CMT_TOP_EE4B3_0", - "CMT_TOP_NE4C0_12", - "CMT_TOP_EE4C3_11", - "CMT_TOP_FAN4_8", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE4B1_5", - "CMT_TOP_R_UPPER_T_CLKPLL6", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_IMUX33_1", - "CMT_TOP_EE4C1_5", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4B3_0", - "CMT_TOP_LH2_1", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "CMT_TOP_LH6_8", - "CMT_TOP_NW4A1_11", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_WL1END0_1", - "CMT_TOP_NE2A3_3", - "CMT_TOP_IMUX12_8", - "CMT_TOP_EE4A1_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", - "CMT_TOP_BYP3_3", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_WW4A1_11", - "CMT_TOP_IMUX46_9", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE4C2_6", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX18_1", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_NW4END1_10", - "CMT_TOP_IMUX20_8", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_R_UPPER_T_FREQ_BB0", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NE2A3_2", - "CMT_TOP_SE2A0_6", - "CMT_TOP_IMUX30_3", - "CMT_TOP_LH7_10", - "CMT_TOP_OCLK_6", - "CMT_TOP_WW4END0_12", - "CMT_TOP_SW4END0_9", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX37_6", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4C2_5", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_EE4B2_5", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WW4A1_5", - "CMT_TOP_BYP3_7", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_FAN2_1", - "CMT_TOP_IMUX36_11", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", - "CMT_TOP_IMUX44_6", - "CMT_TOP_OCLK_1", - "CMT_TOP_NW2A0_9", - "CMT_TOP_WW4C2_12", - "CMT_TOP_IMUX43_12", - "CMT_TOP_IMUX36_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_WW4END2_2", - "CMT_TOP_LH12_9", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_NE2A2_10", - "CMT_TOP_SW4END2_9", - "CMT_TOP_EE2A2_3", - "CMT_TOP_LH4_7", - "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_IMUX6_0", - "CMT_TOP_NE2A0_9", - "CMT_TOP_WW4B3_3", - "CMT_TOP_BYP4_6", - "CMT_TOP_FAN3_10", - "CMT_TOP_BYP6_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_NE2A1_1", - "CMT_TOP_WW4END1_8", - "CMT_TOP_SW4END2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_CTRL0_3", - "CMT_TOP_WW4B3_1", - "CMT_TOP_NW4A2_4", - "CMT_TOP_LH4_11", - "PLLOUT_CLK_FREQ_BB_3", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_SE4C3_3", - "CMT_TOP_WW2END1_9", - "CMT_TOP_NE4C3_1", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WL1END3_9", - "CMT_TOP_SE4C0_4", - "CMT_TOP_EE4C3_0", - "CMT_TOP_IMUX9_10", - "CMT_TOP_WW4C1_3", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_EE4A1_11", - "CMT_TOP_NW2A2_10", - "CMT_TOP_CTRL1_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "CMT_TOP_WL1END1_1", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_NW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_NW2A1_11", - "CMT_TOP_EE4B2_0", - "CMT_TOP_LH5_7", - "CMT_TOP_IMUX41_4", - "CMT_TOP_R_UPPER_T_FREQ_BB1", - "CMT_TOP_IMUX2_5", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_CLK0_1", - "CMT_TOP_IMUX6_4", - "CMT_TOP_NW4A2_11", - "CMT_TOP_EE2A2_8", - "CMT_TOP_SE4C3_7", - "CMT_TOP_WW4C0_7", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_SW2A1_12", - "CMT_TOP_SE4C2_5", - "CMT_TOP_IMUX32_0", - "CMT_TOP_SW2A3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_WW2END3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_EE4B1_4", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX27_5", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_EE4C0_0", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_WW4B0_9", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_NW4END2_0", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_WW4END3_11", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_EE4B1_3", - "CMT_TOP_NW4END3_2", - "CMT_TOP_IMUX21_1", - "CMT_TOP_IMUX31_12", - "CMT_TOP_SW4END0_0", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW2END1_7", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_IMUX32_12", - "CMT_TOP_WW4C0_3", - "CMT_TOP_BYP7_10", - "CMT_TOP_IMUX6_9", - "CMT_TOP_WW4A0_1", - "CMT_TOP_EE4B1_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_NW4A0_10", - "CMT_TOP_EE4B2_12", - "CMT_TOP_WW4END0_11", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NE4C3_4", - "CMT_TOP_BYP6_9", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX29_10", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW2A0_2", - "CMT_TOP_BYP2_8", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW4C0_0", - "CMT_TOP_BYP6_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "CMT_TOP_IMUX28_0", - "CMT_TOP_EE4A2_0", - "CMT_TOP_BYP2_12", - "CMT_TOP_SW2A2_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "CMT_TOP_LH12_10", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW4END1_10", - "CMT_TOP_NW4END0_5", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_IMUX3_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "CMT_TOP_SW4END3_8", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END3_6", - "CMT_TOP_IMUX14_4", - "CMT_TOP_LH6_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WW2A1_10", - "CMT_TOP_SW4A2_7", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_WW2A2_12", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_IMUX0_11", - "CMT_TOP_FAN4_0", - "CMT_PLL_PHASERREF_BELOW0", - "CMT_TOP_IMUX41_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_WW4A3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_LH6_1", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WL1END2_9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", - "CMT_TOP_BYP4_10", - "CMT_TOP_IMUX11_4", - "CMT_TOP_WL1END3_10", - "CMT_TOP_IMUX47_12", - "CMT_TOP_NE4C3_0", - "CMT_TOP_WW4END1_0", - "CMT_TOP_FAN7_5", - "CMT_TOP_OCLK_12", - "CMT_TOP_SE4C0_9", - "CMT_TOP_BYP0_8", - "CMT_TOP_R_UPPER_T_CLKPLL4", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_IMUX22_2", - "CMT_TOP_FAN4_5", - "CMT_TOP_NE2A1_12", - "CMT_TOP_EE4B2_6", - "CMT_TOP_SW4A1_3", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW2A2_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_IMUX19_3", - "CMT_TOP_SW4END1_12", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_SE4C1_12", - "CMT_TOP_EE4A1_8", - "CMT_TOP_WW4B1_2", - "CMT_TOP_IMUX9_9", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_SW2A0_12", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LH9_9", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_NE4C1_12", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_WW4B3_9", - "CMT_TOP_NE4C3_10", - "CMT_TOP_FAN5_6", - "CMT_TOP_IMUX30_6", - "CMT_TOP_BYP3_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_FAN0_10", - "CMT_TOP_IMUX40_10", - "CMT_TOP_LH2_3", - "CMT_TOP_EE4C3_8", - "CMT_TOP_SW4END2_3", - "CMT_TOP_WW4B2_12", - "CMT_TOP_IMUX46_12", - "CMT_TOP_EE2A0_9", - "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "CMT_TOP_WW4A1_3", - "CMT_TOP_BYP5_10", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_WR1END0_4", - "CMT_TOP_NW2A0_2", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_SE4C3_0", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_SE2A1_5", - "CMT_TOP_FAN0_11", - "CMT_TOP_WL1END3_11", - "CMT_TOP_FAN6_5", - "CMT_TOP_EE4A3_7", - "CMT_TOP_WR1END0_7", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_EE4A2_4", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4A0_3", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "CMT_TOP_NE2A1_4", - "CMT_TOP_WR1END1_0", - "CMT_TOP_EE4BEG2_12", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_IMUX32_1", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_1", - "CMT_TOP_WW2END3_12", - "CMT_TOP_IMUX20_2", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_NW4END1_11", - "CMT_TOP_FAN0_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_WW2END1_11", - "CMT_TOP_FAN0_9", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_NE4C3_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", - "CMT_TOP_NW4A0_0", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_EE4C1_12", - "CMT_TOP_BYP1_8", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EE4B2_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_EE4B3_2", - "CMT_TOP_SE4C1_5", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CMT_TOP_FAN6_6", - "CMT_TOP_IMUX25_12", - "CMT_TOP_IMUX36_3", - "CMT_TOP_SE4C2_3", - "CMT_TOP_NW4END0_3", - "CMT_TOP_FAN4_9", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX25_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", - "CMT_TOP_IMUX27_8", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_EE4A3_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_BYP3_6", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A2_12", - "CMT_TOP_WW4B1_3", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_BYP2_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "CMT_TOP_IMUX27_11", - "CMT_TOP_SE2A2_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_SE4C3_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", - "CMT_TOP_NE4C3_3", - "CMT_TOP_WR1END2_9", - "CMT_TOP_CTRL0_6", - "CMT_TOP_FAN2_2", - "CMT_TOP_NW4END1_2", - "CMT_TOP_IMUX18_7", - "CMT_TOP_OCLK_10", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LH2_11", - "CMT_TOP_NW4A1_0", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4END3_3", - "CMT_TOP_BYP7_9", - "CMT_TOP_SW4END1_6", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4C0_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "CMT_TOP_SE4C0_1", - "CMT_TOP_EE2A0_1", - "CMT_TOP_NW2A1_8", - "CMT_TOP_LH9_4", - "CMT_TOP_SW4END1_1", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LH10_8", - "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WW2END3_3", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_FAN1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_SE4C1_2", - "CMT_TOP_NW2A2_6", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX46_8", - "CMT_TOP_EE4B1_7", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_EE4B0_5", - "CMT_TOP_NW2A0_3", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_LH10_11", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_IMUX6_2", - "CMT_TOP_NE4C2_6", - "CMT_TOP_WW4END2_9", - "CMT_TOP_IMUX13_10", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_WW2END3_11", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_LH8_8", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW4A2_2", - "CMT_TOP_WW2A1_6", - "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_IMUX3_8", - "CMT_TOP_SW2A0_11", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_FAN6_9", - "CMT_TOP_SE4C1_3", - "CMT_TOP_WL1END2_6", - "CMT_TOP_LH11_2", - "CMT_TOP_WW4C0_9", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "PLL_CLK_FREQ_BB_BUFOUT_NS3", - "CMT_TOP_IMUX12_1", - "CMT_TOP_SE2A0_1", - "CMT_TOP_IMUX46_11", - "CMT_TOP_IMUX37_4", - "CMT_TOP_EE4C3_10", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_NE4C1_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_NW4END3_12", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX0_4", - "CMT_TOP_R_UPPER_T_CLKPLL1", - "CMT_TOP_NW4A3_12", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_LH1_12", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_IMUX40_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW4A1_5", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_9", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_SE2A2_5", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_SW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LH2_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_WW4END0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_SE2A3_9", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX7_10", - "CMT_TOP_WW4A1_8", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "CMT_TOP_WW4END3_4", - "CMT_TOP_SE2A3_10", - "CMT_TOP_WW2A3_7", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4END2_6", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_NE2A1_11", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_NW2A0_11", - "CMT_TOP_IMUX42_2", - "CMT_TOP_LH8_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_EE4A0_5", - "CMT_TOP_WL1END2_3", - "CMT_TOP_SE2A1_8", - "CMT_TOP_NE4C1_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_NW2A0_6", - "CMT_TOP_WW4A3_8", - "CMT_TOP_SW2A1_3", - "CMT_TOP_IMUX40_5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", - "CMT_TOP_SE2A1_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", - "CMT_TOP_CTRL1_5", - "CMT_TOP_SE4C3_1", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX18_3", - "CMT_TOP_EE2A1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_IMUX16_5", - "CMT_TOP_LH9_5", - "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "CMT_TOP_WW2END0_6", - "CMT_TOP_EE2A1_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_WL1END3_7", - "CMT_TOP_EE4A3_12", - "CMT_TOP_BYP5_8", - "CMT_TOP_IMUX47_3", - "CMT_TOP_NE2A2_7", - "CMT_TOP_WW4B1_5", - "CMT_TOP_SE4C3_9", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END3_12", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_EE2A2_0", - "CMT_TOP_IMUX4_12", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_LH9_7", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW2END3_5", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CLK1_9", - "CMT_TOP_IMUX5_11", - "CMT_TOP_WR1END2_6", - "CMT_TOP_CTRL1_2", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_NW2A1_12", - "CMT_TOP_IMUX10_11", - "CMT_TOP_LH6_6", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_SE2A3_12", - "CMT_TOP_EE2A3_1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", - "CMT_TOP_IMUX2_0", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_IMUX28_12", - "CMT_TOP_EE4B3_5", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX38_2", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_NE2A0_12", - "CMT_TOP_FAN4_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", - "CMT_TOP_CLK0_5", - "CMT_TOP_SW4A3_0", - "CMT_PLL_PHASERD_DTSBUS1", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_ICLK_4", - "CMT_PLL_PHASERREF_ABOVE0", - "CMT_TOP_OCLK_4", - "CMT_TOP_LH12_6", - "CMT_TOP_IMUX4_6", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_WR1END2_3", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX4_11", - "CMT_TOP_NW2A2_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_SE4C1_4", - "CMT_TOP_WW4C0_4", - "CMT_TOP_IMUX6_8", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_WW4A2_4", - "CMT_TOP_IMUX7_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SW4A3_9", - "CMT_TOP_IMUX20_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_IMUX35_7", - "CMT_TOP_EE4A3_5", - "CMT_TOP_LH6_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_ICLK_8", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_IMUX44_12", - "CMT_TOP_NW2A3_9", - "CMT_TOP_CLK0_8", - "CMT_TOP_IMUX7_2", - "CMT_TOP_SE2A2_11", - "CMT_TOP_FAN4_2", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_LH12_3", - "CMT_TOP_WW2A1_8", - "CMT_TOP_NE4C2_12", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LH8_2", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_IMUX23_7", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_IMUX39_0", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX33_8", - "CMT_TOP_SW2A2_2", - "CMT_TOP_LH10_0", - "CMT_TOP_LH6_3", - "CMT_TOP_EE2A0_0", - "CMT_TOP_IMUX12_0", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_NW4A1_1", - "CMT_TOP_IMUX21_8", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX10_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_FAN2_10", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_LH9_12", - "CMT_TOP_IMUX5_12", - "CMT_TOP_LH12_11", - "CMT_TOP_IMUX36_10", - "CMT_TOP_LH4_1", - "CMT_TOP_SE4C3_12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", - "CMT_TOP_NE4C2_11", - "CMT_TOP_IMUX3_3", - "CMT_TOP_BYP1_1", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_SW4END1_5", - "CMT_TOP_FAN7_0", - "CMT_TOP_IMUX35_12", - "CMT_TOP_NW2A3_10", - "CMT_TOP_LH1_7", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_WW4A0_4", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW2A1_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", - "CMT_TOP_WW4C2_0", - "CMT_TOP_SE2A3_3", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_WL1END2_4", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_IMUX9_0", - "CMT_TOP_NW4A0_12", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LH5_0", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_PLL_PHASERREF_ABOVE1", - "CMT_TOP_IMUX22_5", - "CMT_TOP_NE2A3_12", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE2A2_12", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_IMUX11_1", - "CMT_TOP_NE2A3_8", - "CMT_TOP_EE2A3_0", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LH4_6", - "CMT_TOP_WW4A3_9", - "CMT_TOP_FAN7_7", - "CMT_TOP_SE2A1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_SE4C0_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_LH5_3", - "CMT_TOP_SW2A3_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_IMUX25_1", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX31_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "CMT_TOP_LH3_2", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4END2_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_BYP1_7", - "CMT_TOP_LH3_10", - "CMT_TOP_WL1END2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_WL1END3_5", - "CMT_TOP_ICLK_3", - "CMT_TOP_IMUX0_5", - "CMT_TOP_SW4A0_8", - "CMT_TOP_FAN7_6", - "CMT_TOP_IMUX4_0", - "CMT_TOP_BYP1_10", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX20_12", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_IMUX19_4", - "CMT_TOP_WW4B1_8", - "CMT_TOP_LH4_0", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_EE4A2_10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", - "CMT_TOP_IMUX44_7", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4C3_7", - "CMT_TOP_WL1END1_5", - "CMT_TOP_IMUX42_9", - "CMT_TOP_CTRL0_12", - "CMT_TOP_IMUX3_2", - "CMT_TOP_SE4C0_2", - "CMT_TOP_WW2A1_12", - "CMT_TOP_WW4A1_9", - "CMT_TOP_SW4END0_12", - "CMT_TOP_LH7_2", - "CMT_TOP_WW4A1_4", - "CMT_TOP_CLK0_3", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_IMUX44_8", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_WW2A3_12", - "CMT_TOP_SE4C2_0", - "CMT_TOP_EE2A2_12", - "CMT_TOP_IMUX23_2", - "CMT_TOP_WW4END3_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_NW4A0_8", - "CMT_TOP_WW4END3_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX21_2", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_FAN6_10", - "CMT_TOP_LH11_6", - "CMT_TOP_CLK1_10", - "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "CMT_TOP_IMUX45_12", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_SW2A3_2", - "CMT_TOP_IMUX44_5", - "CMT_TOP_WW2A0_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_IMUX33_10", - "CMT_TOP_EE4B3_10", - "CMT_TOP_WW4C1_7", - "CMT_TOP_IMUX24_5", - "CMT_TOP_WW4C2_8", - "CMT_TOP_EE2A3_8", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_NW4END0_6", - "CMT_PHASER_D_OCLK90_TOIOI", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "CMT_TOP_SE2A3_0", - "CMT_TOP_EE4C0_10", - "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "CMT_TOP_IMUX43_10", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NE2A3_0", - "CMT_TOP_LH12_5", - "CMT_TOP_WW2END1_12", - "CMT_TOP_IMUX35_6", - "CMT_TOP_EE4C2_3", - "CMT_TOP_WW2END0_10", - "CMT_TOP_FAN2_7", - "CMT_TOP_WW4A3_0", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_IMUX31_2", - "CMT_TOP_FAN3_7", - "CMT_TOP_IMUX3_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_IMUX8_6", - "CMT_TOP_EE4A1_1", - "CMT_TOP_SW4A0_5", - "CMT_TOP_EE2A3_4", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_WR1END1_10", - "CMT_TOP_EE2A0_6", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX47_6", - "CMT_TOP_SW4A2_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_CTRL1_6", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_NE2A1_3", - "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NW4END1_1", - "CMT_TOP_CLK1_5", - "CMT_TOP_WW4C1_0", - "CMT_TOP_EE4B3_3", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_WW4B2_2", - "CMT_TOP_NW4END1_7", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX10_10", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_WW4B3_6", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_WW4A3_5", - "CMT_TOP_LH1_0", - "CMT_TOP_WW4B1_10", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LH10_5", - "CMT_PLL_PHYCTRL_SYNC_BB_DN", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_IMUX15_0", - "CMT_TOP_EE4A1_5", - "CMT_TOP_NW2A3_12", - "CMT_TOP_EE4C2_9", - "CMT_TOP_SE2A3_1", - "CMT_TOP_BYP0_4", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_WR1END0_11", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX8_5", - "CMT_TOP_WW4C2_9", - "CMT_TOP_CLK1_6", - "CMT_TOP_FAN6_11", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX27_12", - "CMT_TOP_NW4END3_9", - "CMT_TOP_WW4A2_3", - "CMT_TOP_IMUX25_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "CMT_TOP_IMUX17_3", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_PLL_PHASER_IN_D_ICLKDIV", - "CMT_TOP_LH1_8", - "CMT_TOP_LH11_1", - "CMT_TOP_IMUX3_5", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_FAN4_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_SE4C1_6", - "CMT_TOP_WR1END3_10", - "CMT_TOP_IMUX15_9", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_BYP0_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_LH2_10", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_SE4C1_11", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_PLL_PHASERD_CTSBUS0", - "CMT_PHASER_D_ICLKDIV_TOIOI", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", - "CMT_TOP_SW4A3_2", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_LH8_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_LH5_11", - "CMT_TOP_FAN4_4", - "CMT_TOP_WW4C3_0", - "CMT_TOP_EE4C2_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_SW2A1_11", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX35_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_IMUX38_9", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_SE4C2_1", - "CMT_TOP_CTRL0_1", - "CMT_TOP_IMUX2_4", - "CMT_TOP_EE2A0_12", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX16_2", - "CMT_TOP_SW4A1_4", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_NE4C1_11", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_NE2A1_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_IMUX17_5", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_CLK1_12", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_SW4END1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BYP1_4", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_NW4END0_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX26_4", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_BYP4_3", - "CMT_TOP_WL1END2_10", - "CMT_TOP_FAN5_2", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4C0_9", - "CMT_TOP_IMUX29_3", - "CMT_TOP_EE4C1_7", - "CMT_TOP_IMUX29_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4A2_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SW4END3_12", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_NW2A1_2", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_EE4B0_3", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_SW4END2_11", - "CMT_TOP_WW4B2_8", - "CMT_TOP_SW4A2_9", - "CMT_TOP_NW4A2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4END0_9", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_NE2A3_7", - "CMT_TOP_FAN5_1", - "CMT_TOP_IMUX21_11", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_FAN1_11", - "CMT_TOP_IMUX32_6", - "CMT_TOP_SW4A0_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_IMUX8_10", - "CMT_TOP_WW4A2_12", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX24_10", - "CMT_TOP_LH3_7", - "CMT_TOP_WR1END1_7", - "CMT_TOP_NW2A0_5", - "CMT_TOP_EE4B0_11", - "CMT_TOP_BYP3_1", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_LH9_2", - "CMT_TOP_WW2A2_4", - "CMT_TOP_IMUX41_9", - "CMT_TOP_BYP5_9", - "CMT_TOP_IMUX40_6", - "CMT_TOP_WL1END3_3", - "CMT_TOP_NW4A3_0", - "CMT_TOP_LH9_8", - "CMT_TOP_IMUX7_5", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_WW4A0_5", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_IMUX12_7", - "CMT_TOP_SW4A0_7", - "CMT_TOP_EE4A0_4", - "CMT_TOP_IMUX7_11", - "CMT_TOP_EE4B3_7", - "CMT_TOP_IMUX4_7", - "CMT_TOP_EE4C2_0", - "CMT_TOP_R_CLKFBOUT2IN", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4END1_12", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_SE4C0_0", - "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "CMT_TOP_WW4A1_0", - "CMT_TOP_LH1_2", - "CMT_TOP_SW4END0_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", - "CMT_TOP_FAN3_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_R_UPPER_T_CLKPLL0", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_LH11_5", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_WR1END0_2", - "CMT_TOP_IMUX30_5", - "PLLOUT_CLK_FREQ_BB_1", - "CMT_TOP_NW4A3_3", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_WW4B3_8", - "CMT_TOP_IMUX0_1", - "CMT_TOP_WW2END2_8", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX38_7", - "CMT_TOP_NW2A1_3", - "CMT_TOP_EE4A2_5", - "CMT_TOP_NE2A2_0", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "CMT_PHASER_D_OCLKDIV_TOIOI", - "CMT_TOP_WW4C1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_WW4B2_11", - "CMT_TOP_CLK0_7", - "CMT_TOP_EE2A1_3", - "CMT_TOP_SW4END1_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_FAN7_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LH11_3", - "CMT_TOP_IMUX13_3", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_LH10_10", - "CMT_TOP_SW4A1_10", - "CMT_TOP_NE4C0_6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", - "CMT_TOP_NW2A1_9", - "CMT_TOP_BYP0_3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", - "CMT_TOP_SE4C2_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_IMUX5_7", - "CMT_TOP_LH10_4", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX8_4", - "CMT_TOP_WL1END0_9", - "CMT_TOP_SW2A1_6", - "CMT_TOP_IMUX26_3", - "CMT_TOP_NW2A2_0", - "CMT_TOP_WW4END0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_SW4A0_12", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WR1END2_2", - "CMT_TOP_SE4C2_12", - "CMT_TOP_WW4C1_1", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_WW2A1_5", - "CMT_TOP_CTRL1_1", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_BYP7_3", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_WR1END0_10", - "CMT_TOP_IMUX45_0", - "CMT_TOP_WL1END1_7", - "CMT_TOP_LH2_7", - "CMT_TOP_WW4END1_2", - "CMT_TOP_LH7_7", - "CMT_TOP_IMUX26_8", - "CMT_TOP_BYP4_12", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_SE4C2_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_EE4A2_11", - "CMT_TOP_NW4END1_4", - "CMT_TOP_IMUX25_11", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_NW2A1_6", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_BYP2_4", - "CMT_TOP_NW4END2_3", - "CMT_TOP_WL1END0_11", - "CMT_TOP_IMUX18_10", - "CMT_TOP_EE4C1_8", - "CMT_TOP_WW2END1_4", - "CMT_PLL_PHASER_WRENABLE_TOFIFO", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_WW2END3_9", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE4C2_4", - "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_IMUX1_9", - "CMT_TOP_NW4A1_4", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_SW2A0_3", - "CMT_TOP_IMUX22_6", - "CMT_TOP_EE4C2_2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", - "CMT_TOP_IMUX5_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_EE4C3_1", - "CMT_TOP_NE2A2_4", - "CMT_TOP_LH9_6", - "CMT_TOP_IMUX28_5", - "CMT_TOP_R_UPPER_T_CLKIN1", - "CMT_TOP_EE2A2_9", - "CMT_TOP_NW4A3_4", - "CMT_TOP_SW2A2_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LH2_9", - "CMT_TOP_WW2A2_2", - "CMT_TOP_IMUX3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_IMUX45_11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_IMUX27_7", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_IMUX45_5", - "CMT_TOP_NW4END1_12", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_WW4C3_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", - "CMT_TOP_IMUX24_6", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_IMUX35_5", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_EE2A0_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "CMT_TOP_WW4B2_4", - "CMT_TOP_FAN2_8", - "CMT_TOP_SW2A1_0", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_WL1END0_5", - "CMT_TOP_CLK0_9", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX29_4", - "CMT_TOP_NE2A0_11", - "CMT_TOP_FAN2_3", - "CMT_TOP_NE4C2_1", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_IMUX31_5", - "CMT_TOP_WR1END1_5", - "PLL_CLK_FREQ_BB_BUFOUT_NS0", - "CMT_TOP_CTRL1_7", - "CMT_TOP_IMUX8_7", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_IMUX27_9", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4C3_8", - "CMT_TOP_BYP6_6", - "CMT_TOP_EE4C1_4", - "CMT_TOP_IMUX46_6", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4END0_7", - "CMT_TOP_SW4A1_12", - "CMT_TOP_CLK1_11", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_BYP3_8", - "CMT_TOP_WW4END2_12", - "CMT_TOP_IMUX16_8", - "CMT_TOP_SW4END3_7", - "CMT_TOP_WW2A1_4", - "CMT_TOP_LH2_12", - "CMT_TOP_WW2END3_0", - "CMT_TOP_SE2A0_5", - "CMT_TOP_WW2A1_0", - "CMT_TOP_NW4A2_5", - "CMT_TOP_EE2BEG1_8", - "PLLOUT_CLK_FREQ_BB_2", - "CMT_TOP_WW4END2_1", - "CMT_TOP_NW2A2_5", - "CMT_TOP_MONITOR_N_9", - "CMT_PLL_PHASERD_DQSBUS0", - "CMT_TOP_IMUX18_9", - "CMT_TOP_SE2A0_4", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_IMUX6_5", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_EE4A2_8", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX7_6", - "CMT_TOP_CTRL0_9", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_IMUX6_11", - "CMT_TOP_LH5_12", - "CMT_TOP_WW4B3_2", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_EE4C0_4", - "CMT_TOP_BYP2_1", - "CMT_TOP_IMUX36_8", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_NW2A3_5", - "CMT_TOP_IMUX27_3", - "CMT_TOP_LH7_11", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_WW4C2_2", - "CMT_TOP_BYP1_6", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_SE2A0_10", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_NW4END0_10", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_IMUX8_8", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX2_9", - "CMT_TOP_SE2A2_1", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_NE4C2_10", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX3_9", - "CMT_TOP_EE4A2_9", - "CMT_TOP_WW2A3_2", - "CMT_TOP_BYP5_0", - "CMT_TOP_NE4C2_8", - "CMT_TOP_BLOCK_OUTS_L_B1_12", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX17_9", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_IMUX0_8", - "CMT_TOP_NE4C3_5", - "CMT_TOP_WR1END3_9", - "CMT_TOP_EE4C3_9", - "CMT_TOP_IMUX35_8", - "CMT_TOP_BYP3_5", - "CMT_TOP_IMUX32_8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_EE4C1_0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_WW2END0_12", - "CMT_TOP_NW4A0_11", - "CMT_TOP_IMUX34_9", - "CMT_TOP_SE4C3_5", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX47_11", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_FAN6_4", - "CMT_TOP_IMUX21_7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "CMT_TOP_WW2END0_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LH5_2", - "CMT_PLL_PHASER_IN_D_ICLK", - "CMT_TOP_IMUX17_4", - "CMT_TOP_SW2A1_8", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_PLL_PHASERD_DTSBUS0", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_NE4C1_9", - "CMT_TOP_LH3_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_WW2END0_4", - "CMT_TOP_EE2A1_7", - "CMT_TOP_NW2A2_11", - "CMT_TOP_WW2END3_6", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_WW4B0_11", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_WW2END2_12", - "CMT_PLL_PHASERREF_BELOW1", - "CMT_TOP_IMUX8_12", - "CMT_TOP_SW2A3_9", - "CMT_TOP_IMUX32_9", - "CMT_TOP_EE2A0_2", - "CMT_TOP_SW4END2_6", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_IMUX47_1", - "CMT_TOP_WW2A2_1", - "CMT_TOP_NW2A1_7", - "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "CMT_TOP_IMUX14_0", - "CMT_TOP_LH7_4", - "CMT_TOP_EE4C0_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX45_3", - "CMT_TOP_SW4END3_11", - "CMT_TOP_WW4C1_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX33_7", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_R_UPPER_T_CLKPLL5", - "CMT_TOP_FAN4_11", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "CMT_TOP_LH5_4", - "CMT_TOP_CLK0_4", - "CMT_TOP_OCLK_9", - "CMT_TOP_IMUX22_8", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_WW4A3_4", - "CMT_TOP_NW4A1_6", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_IMUX41_12", - "CMT_TOP_SW4A3_4", - "CMT_TOP_NE2A0_10", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_LH8_7", - "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "CMT_TOP_IMUX32_5", - "CMT_TOP_SW2A1_5", - "PLLOUT_CLK_FREQ_BB_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_LOGIC_OUTS_L_B13_10" - ], - "sites": [ - { - "prefix": "PLLE2_ADV", - "y_coord": 0, - "type": "PLLE2_ADV", - "site_pins": { - "TESTOUT33": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", - "TESTOUT45": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", - "TESTOUT41": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", - "TESTOUT48": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", - "DI10": "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "TESTOUT8": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", - "DO8": "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "TESTOUT10": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", - "DADDR0": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "TESTIN16": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "TESTIN14": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "TESTOUT29": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", - "TESTIN7": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", - "TESTOUT14": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", - "TESTIN23": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "DADDR5": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "TESTIN28": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", - "TESTOUT24": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", - "DO15": "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "TESTOUT62": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", - "TESTIN1": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "DI8": "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "DI13": "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "TESTOUT51": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", - "TESTIN15": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "TESTOUT7": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", - "DI1": "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "TESTIN12": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "TESTOUT3": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", - "DI3": "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "TESTOUT31": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", - "DI9": "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "TESTOUT44": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", - "TESTOUT63": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", - "DO4": "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "TESTOUT21": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", - "DO10": "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "TESTOUT57": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", - "TESTOUT50": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", - "TESTIN10": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "DO11": "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "DI11": "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "TESTOUT15": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", - "TESTOUT40": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", - "CLKOUT1": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "TESTIN8": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", - "DO6": "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "TESTOUT60": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", - "TESTOUT20": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", - "DI14": "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "TESTOUT27": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", - "DO9": "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "DADDR6": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "DADDR4": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "DADDR1": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "TESTIN20": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "DO7": "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "TESTIN9": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", - "TESTIN19": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "TESTIN27": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", - "DI0": "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "TESTOUT28": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", - "TESTIN30": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", - "TESTOUT6": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", - "TMUXOUT": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", - "DEN": "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "TESTOUT42": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", - "TESTIN17": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "DO3": "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "CLKOUT2": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CLKOUT0": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "TESTOUT52": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", - "DI2": "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "TESTOUT9": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", - "DRDY": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "DCLK": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "RST": "CMT_TOP_R_UPPER_T_PLLE2_RST", - "DI7": "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "DO0": "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "PWRDWN": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "TESTOUT61": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", - "CLKINSEL": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "TESTOUT19": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", - "TESTOUT23": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", - "CLKIN1": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "TESTOUT30": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", - "TESTOUT18": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", - "DI15": "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "TESTIN6": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", - "TESTIN11": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "TESTIN4": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", - "DI12": "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "DO1": "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "DO5": "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "TESTOUT16": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", - "TESTOUT22": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", - "TESTIN31": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", - "CLKOUT4": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "DO2": "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "TESTOUT59": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", - "TESTIN5": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", - "TESTOUT11": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", - "TESTOUT58": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", - "DWE": "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "TESTOUT25": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", - "TESTOUT37": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", - "DI5": "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "TESTIN18": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "CLKFBIN": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CLKFBOUT": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "DI6": "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "TESTOUT26": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", - "TESTOUT35": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", - "TESTOUT32": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", - "TESTOUT0": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", - "TESTIN25": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "DO12": "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "TESTOUT53": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", - "TESTIN21": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "TESTOUT39": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", - "DO14": "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "TESTOUT46": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", - "CLKIN2": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "TESTOUT4": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", - "TESTOUT55": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", - "TESTOUT47": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", - "TESTOUT43": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", - "TESTOUT36": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", - "TESTIN2": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "DADDR2": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "TESTOUT54": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", - "CLKOUT5": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "TESTIN24": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "TESTIN29": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", - "TESTOUT38": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", - "LOCKED": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "TESTOUT56": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", - "CLKOUT3": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "TESTIN0": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "TESTIN13": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "TESTIN26": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", - "TESTOUT2": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", - "TESTOUT34": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", - "DI4": "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "TESTOUT49": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", - "TESTIN3": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", - "TESTIN22": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "TESTOUT17": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", - "TESTOUT5": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", - "TESTOUT13": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", - "DO13": "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "TESTOUT12": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", - "DADDR3": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "TESTOUT1": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO0->>CMT_TOP_LOGIC_OUTS_L_B17_12": { + "CMT_TOP_R_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_DN<<->>CMT_PLL_PHYCTRL_SYNC_BB_UP": { "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "is_pseudo": "0" + "src_wire": "CMT_PLL_PHYCTRL_SYNC_BB_DN", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "CMT_PLL_PHYCTRL_SYNC_BB_UP" }, "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>PLLOUT_CLK_FREQ_BB_3": { "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_3", - "is_directional": "1", "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_11", "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_DQSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX44_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX44_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_DTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX47_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO4->>CMT_TOP_LOGIC_OUTS_L_B20_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX38_12->>CMT_TOP_R_UPPER_T_PLLE2_DI2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX38_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO15->>CMT_TOP_LOGIC_OUTS_L_B8_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO11->>CMT_TOP_LOGIC_OUTS_L_B13_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK1X_90->>CMT_PHASER_D_OCLK90_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_OCLK90_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK1X_90", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKIN2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_CLKIN2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5->>CMT_TOP_R_UPPER_T_CLKPLL5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL5", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->>CMT_TOP_R_UPPER_T_CLKPLL6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL6", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS->>CMT_TOP_R_UPPER_T_FREQ_BB0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQ_BB0_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_CLK1_0->>CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK1_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS2": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS2", - "is_directional": "0", - "src_wire": "PLL_CLK_FREQ_BB2_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX32_12->>CMT_TOP_R_UPPER_T_PLLE2_DI14": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX32_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX35_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX35_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKIN1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_CLKIN1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX7_12->>CMT_TOP_R_UPPER_T_PLLE2_DI1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX7_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>PLLOUT_CLK_FREQ_BB_2": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_2", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO13->>CMT_TOP_LOGIC_OUTS_L_B0_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO2->>CMT_TOP_LOGIC_OUTS_L_B21_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_CTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>CMT_TOP_R_UPPER_T_CLKPLL1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS->>CMT_TOP_R_UPPER_T_FREQ_BB2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQ_BB2_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B21_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_11", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS1": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS1", - "is_directional": "0", - "src_wire": "PLL_CLK_FREQ_BB1_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX47_10->>CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX47_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>PLLOUT_CLK_FREQ_BB_1": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX36_12->>CMT_TOP_R_UPPER_T_PLLE2_DI6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX36_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_CTSBUS0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX3_12->>CMT_TOP_R_UPPER_T_PLLE2_DI9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKFBIN->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_CLKFBIN", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO7->>CMT_TOP_LOGIC_OUTS_L_B10_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>CMT_TOP_R_UPPER_T_CLKPLL3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL3", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX2_11->>CMT_TOP_R_UPPER_T_PLLE2_DWE": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX0_12->>CMT_TOP_R_UPPER_T_PLLE2_DI15": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4->>CMT_TOP_R_UPPER_T_CLKPLL4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL4", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_CLKFBOUT2IN->CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_R_CLKFBOUT2IN", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO8->>CMT_TOP_LOGIC_OUTS_L_B19_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX0_11->>CMT_TOP_R_UPPER_T_PLLE2_PWRDWN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX0_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO14->>CMT_TOP_LOGIC_OUTS_L_B18_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>CMT_TOP_R_UPPER_T_CLKPLL0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL0", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_9": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_9", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO3->>CMT_TOP_LOGIC_OUTS_L_B15_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX13_10->>CMT_TOP_R_UPPER_T_PLLE2_RST": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_RST", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX2_12->>CMT_TOP_R_UPPER_T_PLLE2_DI11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX2_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK->>CMT_PHASER_D_OCLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO10->>CMT_TOP_LOGIC_OUTS_L_B23_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_DQSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX39_12->>CMT_TOP_R_UPPER_T_PLLE2_DI0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX39_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>CMT_TOP_R_UPPER_T_CLKPLL2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL2", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO9->>CMT_TOP_LOGIC_OUTS_L_B5_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX4_12->>CMT_TOP_R_UPPER_T_PLLE2_DI7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX4_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_3" }, "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX1_12->>CMT_TOP_R_UPPER_T_PLLE2_DI13": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI13", "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO1->>CMT_TOP_LOGIC_OUTS_L_B7_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>PLLOUT_CLK_FREQ_BB_0": { - "can_invert": "0", - "dst_wire": "PLLOUT_CLK_FREQ_BB_0", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO5->>CMT_TOP_LOGIC_OUTS_L_B2_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_IN_D_ICLK->>CMT_PHASER_D_ICLK_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_IN_D_ICLK", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_IN_D_ICLKDIV->>CMT_PHASER_D_ICLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_IN_D_ICLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_2", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_0": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_0", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX5_12->>CMT_TOP_R_UPPER_T_PLLE2_DI5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX5_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_DN<<->>CMT_PLL_PHYCTRL_SYNC_BB_UP": { - "can_invert": "0", - "dst_wire": "CMT_PLL_PHYCTRL_SYNC_BB_UP", - "is_directional": "0", - "src_wire": "CMT_PLL_PHYCTRL_SYNC_BB_DN", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_5", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK1X_90_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK90_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_10", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_3", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX35_12->>CMT_TOP_R_UPPER_T_PLLE2_DI8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX35_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX3_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX3_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_11", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASERD_DTSBUS1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_CLK0_0->>CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_0", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_CLK0_1->>CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX13_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX13_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO12->>CMT_TOP_LOGIC_OUTS_L_B22_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS->>CMT_TOP_R_UPPER_T_FREQ_BB3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", - "is_directional": "1", - "src_wire": "PLL_CLK_FREQ_BB3_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO6->>CMT_TOP_LOGIC_OUTS_L_B16_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_12", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS3": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS3", - "is_directional": "0", - "src_wire": "PLL_CLK_FREQ_BB3_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_12", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS0": { - "can_invert": "0", - "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS0", - "is_directional": "0", - "src_wire": "PLL_CLK_FREQ_BB0_NS", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_4", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLKDIV->>CMT_PHASER_D_OCLKDIV_TOIOI": { - "can_invert": "0", - "dst_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_directional": "1", - "src_wire": "CMT_PLL_PHASER_OUT_D_OCLKDIV", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_CLK0_12->>CMT_TOP_R_UPPER_T_PLLE2_DCLK": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "is_directional": "1", - "src_wire": "CMT_TOP_CLK0_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX1_11->>CMT_TOP_R_UPPER_T_PLLE2_DEN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX1_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_1", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_11", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_ICLKDIV_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX34_12->>CMT_TOP_R_UPPER_T_PLLE2_DI10": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX34_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX6_12->>CMT_TOP_R_UPPER_T_PLLE2_DI3": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX6_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_6": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLK_6", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLK_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX37_12->>CMT_TOP_R_UPPER_T_PLLE2_DI4": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX37_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX33_12->>CMT_TOP_R_UPPER_T_PLLE2_DI12": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX33_12", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX15_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR1": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "is_directional": "1", - "src_wire": "CMT_TOP_IMUX15_11", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->CMT_TOP_R_CLKFBOUT2IN": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_CLKFBOUT2IN", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT->>CMT_TOP_R_UPPER_T_CLKPLL7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL7", - "is_directional": "1", - "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_8", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" - }, - "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { - "can_invert": "0", - "dst_wire": "CMT_TOP_OCLKDIV_7", - "is_directional": "1", - "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" }, "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX22_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR2": { "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "is_directional": "1", "src_wire": "CMT_TOP_IMUX22_11", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS->>CMT_TOP_R_UPPER_T_FREQ_BB3": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB3_NS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_7" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->CMT_TOP_R_CLKFBOUT2IN": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_CLKFBOUT2IN" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO6->>CMT_TOP_LOGIC_OUTS_L_B16_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO5->>CMT_TOP_LOGIC_OUTS_L_B2_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO7->>CMT_TOP_LOGIC_OUTS_L_B10_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>CMT_TOP_R_UPPER_T_CLKPLL0": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_3" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B21_11": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_11" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS1": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB1_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS1" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_7" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_6" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5->>CMT_TOP_R_UPPER_T_CLKPLL5": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL5" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX47_10->>CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_1" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX0_11->>CMT_TOP_R_UPPER_T_PLLE2_PWRDWN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_2" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK->>CMT_PHASER_D_OCLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLK_TOIOI" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO15->>CMT_TOP_LOGIC_OUTS_L_B8_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3->>CMT_TOP_R_UPPER_T_CLKPLL3": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL3" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_5" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_11" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_6" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO0->>CMT_TOP_LOGIC_OUTS_L_B17_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_12" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_5" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_1" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_3" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO3->>CMT_TOP_LOGIC_OUTS_L_B15_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX39_12->>CMT_TOP_R_UPPER_T_PLLE2_DI0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX39_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO12->>CMT_TOP_LOGIC_OUTS_L_B22_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B22_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX4_12->>CMT_TOP_R_UPPER_T_PLLE2_DI7": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX4_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI7" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_9" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX13_10->>CMT_TOP_R_UPPER_T_PLLE2_RST": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_RST" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLK1X_90->>CMT_PHASER_D_OCLK90_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLK90_TOIOI" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>CMT_TOP_R_UPPER_T_CLKPLL2": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_10" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX6_12->>CMT_TOP_R_UPPER_T_PLLE2_DI3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX6_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI3" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO9->>CMT_TOP_LOGIC_OUTS_L_B5_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_12" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_6" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_4" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_5" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX3_12->>CMT_TOP_R_UPPER_T_PLLE2_DI9": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI9" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_8" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS2": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB2_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS2" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX2_12->>CMT_TOP_R_UPPER_T_PLLE2_DI11": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI11" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKIN2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_CLKIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX1_11->>CMT_TOP_R_UPPER_T_PLLE2_DEN": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DEN" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0->>PLLOUT_CLK_FREQ_BB_0": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX5_12->>CMT_TOP_R_UPPER_T_PLLE2_DI5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX5_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI5" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_IN_D_ICLKDIV->>CMT_PHASER_D_ICLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_IN_D_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_ICLKDIV_TOIOI" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX15_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX15_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_OUT_D_OCLKDIV->>CMT_PHASER_D_OCLKDIV_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_OUT_D_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_OCLKDIV_TOIOI" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_10" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX38_12->>CMT_TOP_R_UPPER_T_PLLE2_DI2": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX38_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_9" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX0_12->>CMT_TOP_R_UPPER_T_PLLE2_DI15": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX0_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI15" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_3" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO2->>CMT_TOP_LOGIC_OUTS_L_B21_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX33_12->>CMT_TOP_R_UPPER_T_PLLE2_DI12": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX33_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI12" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_1" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_8" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2->>PLLOUT_CLK_FREQ_BB_2": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_9" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT->>CMT_TOP_R_UPPER_T_CLKPLL7": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL7" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_CLKFBOUT2IN->CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_CLKFBOUT2IN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_3": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_3" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_4" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>PLLOUT_CLK_FREQ_BB_1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PLLOUT_CLK_FREQ_BB_1" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKFBIN->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_CLKFBIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_10" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX1_12->>CMT_TOP_R_UPPER_T_PLLE2_DI13": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX1_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI13" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_7" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_CLKIN1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_CLKIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_CLK0_0->>CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_CLK1_0->>CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_DQSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_4" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO11->>CMT_TOP_LOGIC_OUTS_L_B13_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B13_12" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK_TOIOI->>CMT_TOP_OCLK_9": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK_9" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX13_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR3": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX13_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO4->>CMT_TOP_LOGIC_OUTS_L_B20_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_12" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS3": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB3_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS3" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_DTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_DTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASER_IN_D_ICLK->>CMT_PHASER_D_ICLK_TOIOI": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASER_IN_D_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_PHASER_D_ICLK_TOIOI" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_CLK0_12->>CMT_TOP_R_UPPER_T_PLLE2_DCLK": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DCLK" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB1->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX34_12->>CMT_TOP_R_UPPER_T_PLLE2_DI10": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX34_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI10" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS->>CMT_TOP_R_UPPER_T_FREQ_BB2": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB2_NS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_6" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_12": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO14->>CMT_TOP_LOGIC_OUTS_L_B18_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX44_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX44_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_11" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLK90_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLK1X_90_7" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS0": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB0_NS", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS0" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_CTSBUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_5" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_CTSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_4": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_4" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1->>CMT_TOP_R_UPPER_T_CLKPLL1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL1" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO13->>CMT_TOP_LOGIC_OUTS_L_B0_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX35_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR5": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX35_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX47_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR0": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX47_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_8" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX35_12->>CMT_TOP_R_UPPER_T_PLLE2_DI8": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX35_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI8" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_11": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_11" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO10->>CMT_TOP_LOGIC_OUTS_L_B23_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_12" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_11" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_1" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4->>CMT_TOP_R_UPPER_T_CLKPLL4": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL4" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX2_11->>CMT_TOP_R_UPPER_T_PLLE2_DWE": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX2_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DWE" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_CLK0_1->>CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT": { + "can_invert": "0", + "src_wire": "CMT_TOP_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB3->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_7": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_7" + }, + "CMT_TOP_R_UPPER_T.CMT_PLL_PHASERD_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { + "can_invert": "0", + "src_wire": "CMT_PLL_PHASERD_DQSBUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7" }, "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS->>CMT_TOP_R_UPPER_T_FREQ_BB1": { "can_invert": "0", - "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", - "is_directional": "1", "src_wire": "PLL_CLK_FREQ_BB1_NS", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_8" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX36_12->>CMT_TOP_R_UPPER_T_PLLE2_DI6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX36_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI6" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX32_12->>CMT_TOP_R_UPPER_T_PLLE2_DI14": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX32_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI14" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO8->>CMT_TOP_LOGIC_OUTS_L_B19_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_12" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLK_TOIOI->>CMT_TOP_ICLK_10": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLK_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLK_10" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO1->>CMT_TOP_LOGIC_OUTS_L_B7_12": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_12" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT->>CMT_TOP_R_UPPER_T_CLKPLL6": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL6" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB0->>CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_ICLKDIV_2" + }, + "CMT_TOP_R_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": { + "can_invert": "0", + "src_wire": "CMT_PHASER_D_OCLKDIV_TOIOI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_OCLKDIV_11" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX37_12->>CMT_TOP_R_UPPER_T_PLLE2_DI4": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX37_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI4" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_FREQ_BB2->>CMT_TOP_R_UPPER_T_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS->>CMT_TOP_R_UPPER_T_FREQ_BB0": { + "can_invert": "0", + "src_wire": "PLL_CLK_FREQ_BB0_NS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX3_11->>CMT_TOP_R_UPPER_T_PLLE2_DADDR6": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX3_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6" + }, + "CMT_TOP_R_UPPER_T.CMT_TOP_IMUX7_12->>CMT_TOP_R_UPPER_T_PLLE2_DI1": { + "can_invert": "0", + "src_wire": "CMT_TOP_IMUX7_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CMT_TOP_R_UPPER_T_PLLE2_DI1" } }, - "tile_type": "CMT_TOP_R_UPPER_T" + "wires": [ + "CMT_TOP_NW4A2_6", + "CMT_TOP_WW2END3_2", + "CMT_TOP_BYP1_3", + "CMT_TOP_LOGIC_OUTS_L_B14_5", + "CMT_TOP_WW4A3_11", + "CMT_TOP_OCLKDIV_1", + "CMT_TOP_WW2A1_12", + "CMT_TOP_LH7_10", + "CMT_TOP_EE4BEG3_5", + "CMT_TOP_NW4A1_2", + "CMT_TOP_OCLK1X_90_1", + "CMT_TOP_EL1BEG0_11", + "CMT_TOP_WW2A1_6", + "CMT_TOP_WW4B2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_6", + "CMT_TOP_LOGIC_OUTS_L_B8_0", + "CMT_TOP_WW4END1_8", + "CMT_PHASER_D_OCLK_TOIOI", + "CMT_TOP_EL1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_2", + "CMT_TOP_EE4B0_4", + "CMT_TOP_WW4END2_8", + "CMT_TOP_IMUX7_3", + "CMT_TOP_LOGIC_OUTS_L_B0_10", + "CMT_TOP_WW4B3_6", + "CMT_TOP_NE4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B11_4", + "CMT_TOP_BYP6_2", + "CMT_TOP_LH3_8", + "CMT_TOP_WW4B0_5", + "CMT_TOP_LH12_10", + "CMT_TOP_LOGIC_OUTS_L_B11_1", + "CMT_TOP_EE4BEG0_4", + "CMT_TOP_IMUX41_8", + "CMT_TOP_SW2A1_9", + "CMT_TOP_IMUX36_7", + "CMT_TOP_NE4C0_9", + "CMT_TOP_IMUX32_8", + "CMT_TOP_IMUX17_10", + "CMT_TOP_IMUX7_9", + "CMT_TOP_SW4END0_1", + "CMT_TOP_WW2END3_5", + "CMT_TOP_IMUX12_8", + "CMT_TOP_NW4END3_1", + "CMT_PLL_PHASER_OUT_D_OCLK1X_90", + "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "CMT_TOP_NE2A3_0", + "CMT_TOP_CLK1_3", + "CMT_TOP_WR1END0_8", + "CMT_TOP_FAN2_8", + "CMT_TOP_IMUX29_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", + "CMT_TOP_BLOCK_OUTS_L_B0_9", + "CMT_PLL_PHASERREF0", + "CMT_TOP_BLOCK_OUTS_L_B3_11", + "CMT_TOP_EE4B3_0", + "CMT_TOP_BYP4_1", + "CMT_TOP_NE2A3_12", + "CMT_TOP_LOGIC_OUTS_L_B23_2", + "CMT_TOP_OCLK_7", + "CMT_TOP_WW4C0_11", + "CMT_TOP_WW4C0_3", + "CMT_TOP_SE4BEG2_5", + "CMT_TOP_EE4C2_1", + "CMT_TOP_LOGIC_OUTS_L_B20_2", + "CMT_TOP_EE2A0_9", + "CMT_TOP_LH2_9", + "CMT_TOP_IMUX1_1", + "CMT_TOP_SE4C1_10", + "CMT_TOP_NW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_8", + "CMT_TOP_EE4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B9_1", + "CMT_TOP_SE4C2_9", + "CMT_TOP_IMUX35_6", + "CMT_TOP_WW2A3_12", + "CMT_TOP_EE4A0_6", + "CMT_TOP_SE4C0_10", + "CMT_TOP_FAN5_5", + "CMT_TOP_WL1END1_9", + "CMT_TOP_BYP5_12", + "CMT_TOP_EE4C0_9", + "CMT_TOP_WW2END1_3", + "CMT_TOP_NE4BEG2_5", + "CMT_TOP_IMUX3_4", + "CMT_TOP_NE2A1_0", + "CMT_TOP_ER1BEG3_11", + "CMT_TOP_IMUX39_7", + "CMT_PLL_PHASERD_DTSBUS1", + "CMT_TOP_IMUX14_2", + "CMT_TOP_WW4C3_2", + "CMT_TOP_EE4B3_8", + "CMT_TOP_BYP4_6", + "CMT_TOP_WW4END1_5", + "CMT_TOP_EL1BEG2_2", + "CMT_TOP_EE4A2_7", + "CMT_TOP_EE2A0_1", + "CMT_TOP_LOGIC_OUTS_L_B10_12", + "CMT_TOP_WW4B0_6", + "CMT_TOP_IMUX12_9", + "CMT_TOP_WW4A0_4", + "CMT_TOP_IMUX39_9", + "CMT_TOP_NE4BEG2_12", + "CMT_TOP_WW2A1_11", + "CMT_TOP_IMUX23_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", + "CMT_TOP_IMUX26_12", + "CMT_TOP_LOGIC_OUTS_L_B3_0", + "CMT_TOP_LOGIC_OUTS_L_B13_12", + "CMT_TOP_IMUX1_3", + "CMT_TOP_SE4C1_9", + "CMT_TOP_WW2A0_9", + "CMT_TOP_WW4C1_11", + "CMT_TOP_BYP7_3", + "CMT_TOP_EE4A0_9", + "CMT_TOP_IMUX6_11", + "CMT_TOP_IMUX30_7", + "CMT_TOP_ICLK_4", + "CMT_TOP_BYP5_9", + "CMT_TOP_OCLKDIV_8", + "CMT_TOP_LOGIC_OUTS_L_B1_5", + "CMT_TOP_R_UPPER_T_FREQ_BB0", + "CMT_TOP_OCLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B8_10", + "CMT_TOP_LOGIC_OUTS_L_B13_2", + "CMT_TOP_ICLKDIV_7", + "CMT_TOP_LOGIC_OUTS_L_B22_4", + "CMT_TOP_WW2END1_0", + "CMT_TOP_IMUX30_8", + "CMT_TOP_IMUX22_8", + "CMT_TOP_EE4BEG1_7", + "CMT_TOP_WW2A0_5", + "CMT_TOP_WW4C1_0", + "CMT_TOP_WL1END2_11", + "CMT_TOP_IMUX14_3", + "CMT_TOP_EE4B1_9", + "CMT_TOP_SW4END1_5", + "CMT_TOP_BLOCK_OUTS_L_B1_2", + "CMT_TOP_NE2A0_2", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "CMT_TOP_WW4C2_11", + "CMT_TOP_NW2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B17_9", + "CMT_TOP_FAN3_8", + "CMT_TOP_IMUX27_7", + "CMT_TOP_WW4END1_1", + "CMT_TOP_FAN4_11", + "CMT_TOP_NW4END2_7", + "CMT_TOP_LH8_6", + "CMT_TOP_FAN0_12", + "CMT_TOP_EE4A0_1", + "CMT_TOP_BLOCK_OUTS_L_B0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_9", + "CMT_TOP_SW4END1_9", + "CMT_TOP_WL1END2_3", + "CMT_TOP_LOGIC_OUTS_L_B10_2", + "CMT_TOP_SE4BEG0_5", + "CMT_TOP_MONITOR_N_8", + "CMT_TOP_WW4END1_6", + "CMT_TOP_WW4END1_2", + "CMT_TOP_WL1END2_4", + "CMT_TOP_WR1END0_9", + "CMT_TOP_LH5_9", + "CMT_TOP_IMUX11_4", + "CMT_TOP_SE4BEG1_5", + "CMT_TOP_IMUX3_3", + "CMT_TOP_BYP7_4", + "CMT_TOP_WW4B0_12", + "CMT_TOP_WR1END0_4", + "CMT_TOP_EE2BEG3_3", + "CMT_TOP_EE4BEG3_10", + "CMT_TOP_SW4A2_0", + "CMT_TOP_SE4BEG2_10", + "CMT_TOP_SE4BEG1_12", + "CMT_TOP_BLOCK_OUTS_L_B3_5", + "CMT_TOP_LOGIC_OUTS_L_B17_12", + "CMT_PLL_PHASERREF_ABOVE0", + "CMT_TOP_WW4A1_9", + "CMT_TOP_EE2A0_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", + "CMT_TOP_SE2A1_8", + "CMT_TOP_LH4_7", + "CMT_TOP_IMUX8_11", + "CMT_TOP_EE4C1_10", + "CMT_TOP_LOGIC_OUTS_L_B23_12", + "CMT_TOP_LH4_11", + "CMT_TOP_ER1BEG1_2", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "CMT_TOP_EE4A1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_3", + "CMT_TOP_IMUX14_4", + "CMT_TOP_MONITOR_N_3", + "CMT_TOP_IMUX14_12", + "CMT_TOP_CTRL0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_2", + "CMT_TOP_EE4A0_3", + "CMT_TOP_IMUX11_12", + "CMT_TOP_LOGIC_OUTS_L_B1_0", + "CMT_TOP_EE4A2_10", + "CMT_TOP_IMUX43_3", + "CMT_TOP_ER1BEG2_9", + "CMT_TOP_LH11_11", + "CMT_TOP_FAN1_5", + "CMT_TOP_NW2A0_7", + "CMT_TOP_EE4B2_1", + "CMT_TOP_BYP2_12", + "CMT_TOP_IMUX31_7", + "CMT_TOP_WW4B2_7", + "CMT_TOP_NW4END2_0", + "CMT_TOP_IMUX6_10", + "CMT_TOP_SE4BEG3_9", + "CMT_TOP_BLOCK_OUTS_L_B0_1", + "CMT_TOP_IMUX47_0", + "CMT_TOP_LOGIC_OUTS_L_B16_4", + "CMT_TOP_IMUX21_0", + "CMT_TOP_EL1BEG3_9", + "CMT_TOP_FAN4_9", + "PLL_CLK_FREQ_BB_BUFOUT_NS1", + "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "CMT_TOP_SW4A0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_4", + "CMT_TOP_NE2A3_6", + "CMT_TOP_CLK0_0", + "CMT_TOP_LH9_7", + "CMT_TOP_EE4BEG3_8", + "CMT_TOP_WW2END3_7", + "CMT_TOP_OCLK1X_90_3", + "CMT_TOP_IMUX5_11", + "CMT_TOP_EE4B2_9", + "CMT_TOP_IMUX33_12", + "CMT_TOP_ER1BEG2_7", + "CMT_TOP_NW2A1_2", + "CMT_TOP_SW4END1_1", + "CMT_TOP_BLOCK_OUTS_L_B3_9", + "CMT_PLL_PHASERD_CTSBUS0", + "CMT_TOP_NW4A1_1", + "CMT_TOP_NW2A0_12", + "CMT_TOP_BYP3_9", + "CMT_TOP_WW2A2_4", + "CMT_TOP_ER1BEG3_2", + "CMT_TOP_LOGIC_OUTS_L_B15_5", + "CMT_TOP_SW4A0_9", + "CMT_TOP_OCLK1X_90_7", + "CMT_TOP_NE2A0_11", + "CMT_TOP_EE4A2_11", + "CMT_TOP_SE4C2_5", + "CMT_TOP_WW4END2_7", + "CMT_TOP_EE4A3_4", + "CMT_TOP_LH9_5", + "CMT_TOP_NE2A0_3", + "CMT_TOP_BLOCK_OUTS_L_B1_9", + "CMT_TOP_IMUX46_9", + "CMT_TOP_EE2A2_0", + "CMT_TOP_MONITOR_P_0", + "CMT_TOP_EE2BEG1_2", + "CMT_TOP_IMUX9_8", + "CMT_TOP_IMUX33_11", + "CMT_TOP_LOGIC_OUTS_L_B15_11", + "CMT_TOP_IMUX26_4", + "CMT_TOP_IMUX38_1", + "CMT_TOP_LOGIC_OUTS_L_B2_7", + "CMT_TOP_NW4A1_0", + "CMT_TOP_WR1END0_11", + "CMT_TOP_FAN4_10", + "CMT_TOP_FAN2_11", + "CMT_TOP_EL1BEG3_6", + "CMT_TOP_BYP1_8", + "CMT_TOP_IMUX31_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", + "CMT_TOP_LOGIC_OUTS_L_B23_9", + "CMT_TOP_SW4A3_2", + "CMT_TOP_EE4C3_9", + "CMT_TOP_IMUX36_8", + "CMT_TOP_BLOCK_OUTS_L_B0_2", + "CMT_TOP_SW4A1_0", + "CMT_TOP_SE2A1_10", + "CMT_TOP_EE4C0_5", + "CMT_TOP_LOGIC_OUTS_L_B12_6", + "CMT_TOP_LH7_0", + "CMT_TOP_IMUX33_7", + "CMT_TOP_SE4C1_2", + "CMT_TOP_ER1BEG1_0", + "CMT_TOP_FAN7_10", + "CMT_TOP_LH2_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", + "CMT_TOP_NE4C2_1", + "CMT_TOP_SW4A2_7", + "CMT_TOP_IMUX23_11", + "CMT_TOP_WR1END1_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", + "CMT_TOP_NE2A0_10", + "CMT_TOP_SW4END2_0", + "CMT_TOP_LH8_0", + "CMT_TOP_EE4C0_3", + "CMT_TOP_NW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B23_6", + "CMT_TOP_IMUX8_6", + "CMT_TOP_LH6_12", + "CMT_TOP_BYP0_7", + "CMT_TOP_LH5_0", + "CMT_TOP_IMUX5_2", + "CMT_TOP_WL1END2_6", + "CMT_TOP_BYP1_9", + "CMT_TOP_IMUX9_3", + "CMT_TOP_BYP1_7", + "CMT_TOP_IMUX47_1", + "CMT_TOP_WW4END3_2", + "CMT_TOP_LOGIC_OUTS_L_B19_7", + "CMT_TOP_IMUX16_0", + "CMT_TOP_EE2BEG3_5", + "CMT_TOP_EE2A1_9", + "CMT_TOP_ER1BEG1_12", + "CMT_TOP_NE4C3_4", + "CMT_TOP_EE4B2_7", + "CMT_TOP_OCLK_5", + "CMT_TOP_NE2A1_6", + "CMT_TOP_IMUX45_4", + "CMT_TOP_IMUX8_2", + "CMT_TOP_IMUX1_2", + "CMT_TOP_IMUX46_0", + "CMT_TOP_EE4C1_9", + "CMT_TOP_LOGIC_OUTS_L_B14_4", + "CMT_TOP_LH1_7", + "CMT_TOP_BYP5_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", + "CMT_TOP_EE4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B14_12", + "CMT_TOP_IMUX40_4", + "CMT_TOP_EE4BEG1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", + "CMT_TOP_BYP7_0", + "CMT_TOP_IMUX21_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", + "CMT_TOP_WW4C1_7", + "CMT_TOP_SW4A3_12", + "CMT_TOP_WW2A3_4", + "CMT_TOP_IMUX21_1", + "CMT_TOP_WW4A3_6", + "CMT_TOP_NE4BEG3_8", + "CMT_TOP_EE4BEG0_12", + "CMT_TOP_IMUX17_11", + "CMT_TOP_EL1BEG2_7", + "CMT_TOP_WR1END2_5", + "CMT_TOP_EE4A0_4", + "CMT_TOP_SE2A1_12", + "CMT_TOP_SW4A0_3", + "CMT_TOP_IMUX6_12", + "CMT_TOP_IMUX6_6", + "CMT_TOP_IMUX11_6", + "CMT_TOP_IMUX25_7", + "CMT_TOP_IMUX4_8", + "CMT_TOP_SE4BEG2_11", + "CMT_TOP_WW4END3_12", + "CMT_TOP_WR1END3_12", + "CMT_TOP_EL1BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B18_4", + "CMT_TOP_EL1BEG2_4", + "CMT_TOP_IMUX16_8", + "CMT_TOP_IMUX3_9", + "CMT_TOP_NW4END0_5", + "CMT_TOP_NE4C3_10", + "CMT_TOP_WW4END1_12", + "CMT_TOP_SE2A3_6", + "CMT_TOP_IMUX7_4", + "CMT_TOP_LH3_11", + "CMT_TOP_BYP5_6", + "CMT_TOP_WW4C2_5", + "CMT_TOP_LH7_6", + "CMT_TOP_LOGIC_OUTS_L_B12_12", + "CMT_TOP_SE2A1_5", + "CMT_TOP_FAN4_7", + "CMT_TOP_EE4A2_3", + "CMT_TOP_LH9_2", + "CMT_TOP_LH2_12", + "CMT_TOP_BYP0_1", + "CMT_TOP_LH11_0", + "CMT_TOP_IMUX14_0", + "CMT_TOP_IMUX27_9", + "CMT_TOP_NW2A1_5", + "CMT_TOP_IMUX21_7", + "CMT_TOP_WW4A0_2", + "CMT_TOP_NE2A1_11", + "CMT_TOP_IMUX7_6", + "CMT_TOP_WL1END0_10", + "CMT_TOP_SW4END3_8", + "CMT_TOP_IMUX23_7", + "CMT_TOP_NW4A1_12", + "CMT_TOP_IMUX10_10", + "CMT_TOP_WW2END2_5", + "CMT_TOP_EE4C1_2", + "CMT_TOP_LH4_3", + "CMT_TOP_SW4END2_2", + "CMT_TOP_LH5_6", + "CMT_TOP_LOGIC_OUTS_L_B15_0", + "CMT_TOP_WW4C1_4", + "CMT_TOP_MONITOR_N_2", + "CMT_TOP_IMUX27_6", + "CMT_TOP_LOGIC_OUTS_L_B0_8", + "CMT_TOP_LOGIC_OUTS_L_B13_3", + "CMT_TOP_NE4BEG2_11", + "CMT_TOP_FAN4_6", + "CMT_TOP_WW4B1_9", + "CMT_TOP_IMUX9_9", + "CMT_TOP_IMUX18_6", + "CMT_TOP_NW4A3_5", + "CMT_TOP_BYP0_11", + "CMT_TOP_EE2BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B23_11", + "CMT_TOP_IMUX33_2", + "CMT_TOP_BYP2_1", + "CMT_TOP_LOGIC_OUTS_L_B1_6", + "CMT_TOP_SE2A3_8", + "CMT_TOP_EE4BEG0_2", + "CMT_TOP_IMUX25_9", + "CMT_TOP_WW2END1_2", + "CMT_TOP_ER1BEG3_3", + "CMT_TOP_LH8_12", + "CMT_TOP_EE4B2_2", + "CMT_TOP_SE4BEG0_2", + "CMT_TOP_IMUX13_9", + "CMT_TOP_NE4BEG0_1", + "CMT_TOP_ICLKDIV_12", + "CMT_TOP_NW2A2_7", + "CMT_TOP_OCLKDIV_11", + "CMT_TOP_IMUX5_8", + "CMT_TOP_LOGIC_OUTS_L_B16_2", + "CMT_TOP_EL1BEG0_5", + "CMT_TOP_IMUX33_5", + "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "CMT_TOP_LOGIC_OUTS_L_B14_0", + "CMT_TOP_WW4END2_11", + "CMT_TOP_WW2END1_8", + "CMT_TOP_EE2A0_7", + "CMT_TOP_WR1END1_10", + "CMT_TOP_FAN0_9", + "CMT_TOP_EE4C2_10", + "CMT_TOP_SW4END3_0", + "CMT_TOP_WR1END1_2", + "CMT_TOP_NW4A1_5", + "CMT_TOP_EE4B3_12", + "CMT_TOP_IMUX4_9", + "CMT_TOP_IMUX47_8", + "CMT_TOP_WW4C1_3", + "CMT_TOP_IMUX26_9", + "CMT_TOP_LOGIC_OUTS_L_B3_1", + "CMT_TOP_IMUX41_2", + "CMT_TOP_SE4C1_5", + "CMT_TOP_WL1END2_7", + "CMT_TOP_WW4A0_1", + "CMT_TOP_EE2BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B3_5", + "CMT_TOP_CTRL0_4", + "CMT_TOP_NW4END2_3", + "CMT_TOP_SE2A2_8", + "CMT_TOP_WW4C2_3", + "CMT_TOP_WW2A3_3", + "CMT_TOP_WL1END3_4", + "CMT_TOP_NE2A2_8", + "CMT_TOP_SW2A0_9", + "CMT_TOP_ICLKDIV_3", + "CMT_TOP_SE4BEG3_8", + "CMT_TOP_SW2A0_8", + "CMT_TOP_WW4B3_3", + "CMT_TOP_WW2END0_7", + "CMT_TOP_SW4A3_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "CMT_TOP_SE4C0_7", + "CMT_TOP_IMUX1_10", + "CMT_TOP_IMUX4_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", + "CMT_TOP_IMUX40_2", + "CMT_TOP_LOGIC_OUTS_L_B6_8", + "CMT_TOP_EE2BEG3_8", + "CMT_TOP_MONITOR_P_11", + "CMT_TOP_IMUX44_5", + "CMT_TOP_IMUX1_6", + "CMT_TOP_ER1BEG3_9", + "CMT_TOP_IMUX14_7", + "CMT_TOP_OCLK_2", + "CMT_TOP_IMUX7_7", + "CMT_TOP_IMUX29_5", + "CMT_TOP_EL1BEG0_2", + "CMT_TOP_WW4A2_4", + "CMT_TOP_WW4B1_7", + "CMT_TOP_EE2A1_6", + "CMT_TOP_IMUX19_2", + "CMT_TOP_EE2BEG0_11", + "CMT_TOP_IMUX25_12", + "CMT_TOP_MONITOR_N_6", + "CMT_TOP_EL1BEG1_8", + "CMT_TOP_FAN3_4", + "CMT_TOP_FAN3_2", + "CMT_TOP_BYP7_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", + "CMT_TOP_IMUX6_7", + "CMT_TOP_IMUX24_10", + "CMT_TOP_NE4BEG2_4", + "CMT_TOP_LOGIC_OUTS_L_B23_10", + "CMT_TOP_IMUX19_12", + "CMT_TOP_SW2A0_2", + "CMT_TOP_BYP7_8", + "CMT_TOP_NE4BEG3_5", + "CMT_TOP_IMUX47_7", + "CMT_TOP_BYP0_4", + "CMT_TOP_IMUX21_6", + "CMT_TOP_LOGIC_OUTS_L_B15_9", + "CMT_TOP_EE4A3_11", + "CMT_TOP_IMUX5_4", + "CMT_TOP_SE2A3_10", + "CMT_TOP_SW4END2_10", + "CMT_TOP_NW2A0_5", + "CMT_TOP_NE4C1_2", + "CMT_TOP_WW4C0_9", + "CMT_TOP_EL1BEG3_8", + "CMT_TOP_WW2END0_1", + "CMT_TOP_NE4BEG3_6", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "CMT_TOP_BLOCK_OUTS_L_B2_9", + "CMT_TOP_BLOCK_OUTS_L_B2_6", + "CMT_TOP_ER1BEG2_4", + "CMT_TOP_IMUX2_5", + "CMT_TOP_EL1BEG1_2", + "CMT_TOP_NE4C2_7", + "CMT_TOP_IMUX0_0", + "CMT_TOP_IMUX15_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", + "CMT_TOP_IMUX16_7", + "CMT_TOP_SW2A2_4", + "CMT_TOP_WW4C2_0", + "CMT_TOP_ICLK_8", + "CMT_TOP_NW2A1_7", + "CMT_TOP_CTRL0_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", + "CMT_TOP_R_UPPER_T_CLKPLL0", + "CMT_TOP_LOGIC_OUTS_L_B17_1", + "CMT_TOP_NE4BEG1_9", + "CMT_TOP_NE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B20_8", + "CMT_TOP_WW4A0_6", + "CMT_TOP_IMUX6_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", + "CMT_TOP_IMUX29_6", + "CMT_TOP_WR1END0_1", + "CMT_TOP_CLK0_5", + "CMT_TOP_IMUX41_3", + "CMT_TOP_LH10_12", + "CMT_TOP_SE4BEG0_1", + "CMT_PLL_PHASER_RDCLK_TOFIFO", + "CMT_TOP_SW2A1_4", + "CMT_TOP_EE2BEG1_9", + "CMT_TOP_IMUX27_1", + "CMT_TOP_LOGIC_OUTS_L_B5_3", + "CMT_TOP_IMUX23_9", + "CMT_TOP_NE4BEG2_1", + "CMT_TOP_IMUX30_6", + "CMT_TOP_NW4END1_9", + "CMT_TOP_IMUX39_2", + "CMT_TOP_EE4C0_6", + "CMT_TOP_IMUX10_8", + "CMT_TOP_WW4C2_1", + "CMT_TOP_WW4END3_0", + "CMT_TOP_NW4END1_11", + "CMT_TOP_LOGIC_OUTS_L_B15_12", + "CMT_TOP_EE4C2_8", + "CMT_TOP_SW4A3_11", + "CMT_TOP_LOGIC_OUTS_L_B22_3", + "CMT_TOP_IMUX16_3", + "CMT_TOP_LH2_2", + "CMT_TOP_OCLK_8", + "CMT_TOP_NE2A0_6", + "CMT_TOP_WW2A3_2", + "CMT_TOP_IMUX43_11", + "CMT_TOP_CTRL1_6", + "CMT_TOP_BLOCK_OUTS_L_B2_1", + "CMT_TOP_EE4A0_8", + "CMT_TOP_SE4C1_3", + "CMT_TOP_MONITOR_N_9", + "CMT_TOP_IMUX8_5", + "CMT_TOP_IMUX9_1", + "CMT_TOP_WW4A0_9", + "CMT_TOP_EE4A3_8", + "PLLOUT_CLK_FREQ_BB_3", + "CMT_TOP_IMUX37_5", + "CMT_TOP_SW4A1_12", + "CMT_TOP_IMUX11_10", + "CMT_TOP_SE4BEG2_1", + "CMT_TOP_EE4A1_5", + "CMT_TOP_IMUX44_2", + "CMT_TOP_IMUX28_6", + "CMT_TOP_NW4A0_7", + "CMT_TOP_LOGIC_OUTS_L_B0_7", + "CMT_TOP_IMUX40_10", + "CMT_TOP_EE2A2_12", + "CMT_TOP_EL1BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B7_7", + "CMT_TOP_MONITOR_N_4", + "CMT_TOP_CLK0_1", + "CMT_TOP_SW4A0_10", + "CMT_TOP_LOGIC_OUTS_L_B21_7", + "CMT_TOP_IMUX23_1", + "CMT_TOP_LOGIC_OUTS_L_B19_9", + "CMT_TOP_BLOCK_OUTS_L_B0_0", + "CMT_TOP_OCLKDIV_6", + "CMT_TOP_WW2END1_6", + "CMT_TOP_SW2A0_1", + "CMT_TOP_CTRL1_3", + "CMT_TOP_IMUX10_7", + "CMT_TOP_LOGIC_OUTS_L_B20_12", + "CMT_TOP_NE4C2_8", + "CMT_TOP_OCLK1X_90_6", + "CMT_TOP_LOGIC_OUTS_L_B15_1", + "CMT_TOP_IMUX6_1", + "CMT_TOP_LOGIC_OUTS_L_B10_1", + "CMT_TOP_EE4BEG0_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", + "CMT_TOP_NW2A3_4", + "CMT_TOP_WR1END2_9", + "CMT_TOP_IMUX27_8", + "CMT_TOP_LH6_3", + "CMT_TOP_NE2A1_1", + "CMT_TOP_CLK0_9", + "CMT_TOP_EE4BEG2_1", + "CMT_TOP_BYP0_9", + "CMT_TOP_EE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B7_8", + "CMT_TOP_LOGIC_OUTS_L_B4_8", + "CMT_TOP_EE4BEG1_4", + "CMT_TOP_SW2A2_12", + "CMT_TOP_WW2END1_1", + "CMT_TOP_LOGIC_OUTS_L_B22_9", + "CMT_TOP_ER1BEG0_3", + "CMT_TOP_WW4END0_2", + "CMT_TOP_MONITOR_P_9", + "CMT_TOP_EE2A0_4", + "CMT_TOP_EL1BEG3_11", + "CMT_TOP_FAN1_7", + "CMT_TOP_WW4A3_3", + "CMT_TOP_NW4END3_2", + "CMT_TOP_SW4END2_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", + "CMT_TOP_EE4A3_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", + "CMT_TOP_EE4A1_0", + "CMT_TOP_SW4A2_9", + "CMT_TOP_LH3_5", + "CMT_TOP_IMUX30_0", + "CMT_TOP_IMUX41_0", + "CMT_TOP_IMUX32_6", + "CMT_TOP_WR1END3_4", + "CMT_TOP_BYP7_12", + "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT", + "CMT_TOP_SW2A1_11", + "CMT_TOP_MONITOR_P_4", + "CMT_TOP_ER1BEG1_3", + "CMT_TOP_IMUX11_7", + "CMT_TOP_SW2A2_5", + "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "CMT_TOP_FAN5_0", + "CMT_TOP_WW2END2_7", + "CMT_TOP_NW4A2_10", + "CMT_TOP_SW4END1_8", + "CMT_TOP_EL1BEG2_10", + "CMT_TOP_IMUX17_4", + "CMT_TOP_BYP1_4", + "CMT_TOP_WR1END0_12", + "CMT_TOP_WW2A1_8", + "CMT_TOP_EE4BEG0_5", + "CMT_TOP_IMUX4_10", + "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "CMT_TOP_FAN6_9", + "CMT_TOP_NW2A2_0", + "CMT_TOP_IMUX11_2", + "CMT_TOP_IMUX21_12", + "CMT_TOP_IMUX1_9", + "CMT_TOP_WW2A3_9", + "CMT_TOP_WW4B3_11", + "CMT_TOP_ER1BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B22_11", + "CMT_TOP_BYP2_7", + "CMT_TOP_LOGIC_OUTS_L_B11_3", + "CMT_TOP_LOGIC_OUTS_L_B18_12", + "CMT_TOP_WW4END2_3", + "CMT_TOP_BYP0_0", + "CMT_TOP_EE2BEG0_2", + "CMT_TOP_WW4END0_7", + "CMT_TOP_LOGIC_OUTS_L_B17_11", + "CMT_TOP_NE4BEG2_8", + "CMT_TOP_LH6_10", + "CMT_TOP_ER1BEG1_4", + "CMT_TOP_SW4END1_12", + "CMT_TOP_IMUX41_7", + "CMT_PLL_PHASER_IN_D_ICLKDIV", + "CMT_TOP_LOGIC_OUTS_L_B14_8", + "CMT_TOP_NE2A2_6", + "CMT_TOP_IMUX37_2", + "CMT_TOP_EE4B3_10", + "CMT_TOP_WR1END1_7", + "CMT_TOP_IMUX14_9", + "CMT_TOP_LOGIC_OUTS_L_B1_7", + "CMT_TOP_LOGIC_OUTS_L_B21_2", + "CMT_TOP_IMUX7_2", + "CMT_TOP_FAN2_1", + "CMT_TOP_LOGIC_OUTS_L_B11_7", + "CMT_TOP_BLOCK_OUTS_L_B3_10", + "CMT_TOP_WW4A0_7", + "CMT_TOP_EE4C0_8", + "CMT_TOP_SE4C0_3", + "CMT_TOP_LOGIC_OUTS_L_B5_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", + "CMT_TOP_WR1END3_8", + "CMT_TOP_BLOCK_OUTS_L_B2_7", + "CMT_TOP_IMUX37_1", + "CMT_TOP_LOGIC_OUTS_L_B19_12", + "CMT_TOP_NW2A1_0", + "CMT_TOP_EL1BEG0_4", + "CMT_TOP_WW4A1_4", + "CMT_TOP_IMUX7_12", + "CMT_TOP_NW2A2_3", + "CMT_TOP_NW4END2_9", + "CMT_TOP_WW2A2_6", + "CMT_TOP_EE4C0_7", + "CMT_TOP_LOGIC_OUTS_L_B3_11", + "CMT_TOP_FAN3_11", + "CMT_TOP_SW4END0_0", + "CMT_PLL_PHASER_OUT_D_OCLKDIV", + "CMT_TOP_NE4BEG2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", + "CMT_TOP_NE4C3_11", + "CMT_TOP_IMUX37_6", + "CMT_TOP_BYP5_5", + "CMT_TOP_LOGIC_OUTS_L_B4_5", + "CMT_TOP_LH8_4", + "CMT_TOP_NW4A0_5", + "CMT_TOP_SE4C0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_2", + "CMT_TOP_SE4BEG1_0", + "CMT_TOP_IMUX46_5", + "PLLOUT_CLK_FREQ_BB_0", + "CMT_TOP_EL1BEG0_1", + "CMT_TOP_LH8_8", + "CMT_TOP_NE4C3_9", + "CMT_TOP_WW4B1_1", + "CMT_TOP_BLOCK_OUTS_L_B2_12", + "CMT_TOP_BYP2_9", + "CMT_TOP_IMUX26_10", + "CMT_TOP_LOGIC_OUTS_L_B21_6", + "CMT_TOP_SE4BEG3_2", + "CMT_TOP_IMUX2_3", + "CMT_TOP_EE2A3_3", + "CMT_TOP_IMUX36_4", + "CMT_TOP_EE4BEG2_0", + "CMT_TOP_IMUX43_5", + "CMT_TOP_SW2A0_3", + "CMT_TOP_EE4A1_10", + "CMT_TOP_SW2A3_8", + "CMT_TOP_WW2A2_5", + "CMT_TOP_IMUX24_11", + "CMT_TOP_SW2A2_9", + "CMT_TOP_FAN5_12", + "CMT_TOP_SW4A0_6", + "CMT_TOP_IMUX38_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", + "CMT_TOP_WR1END0_5", + "CMT_TOP_IMUX4_2", + "CMT_TOP_LOGIC_OUTS_L_B4_7", + "CMT_TOP_LOGIC_OUTS_L_B3_7", + "CMT_TOP_CTRL0_11", + "CMT_TOP_IMUX19_8", + "CMT_TOP_LOGIC_OUTS_L_B17_6", + "CMT_TOP_BLOCK_OUTS_L_B1_7", + "CMT_TOP_IMUX36_5", + "CMT_TOP_WW2A0_3", + "CMT_TOP_LH10_5", + "CMT_TOP_NE4C3_3", + "CMT_TOP_FAN7_2", + "CMT_TOP_IMUX7_10", + "CMT_TOP_WW4B1_11", + "CMT_TOP_BYP6_1", + "CMT_TOP_WL1END2_1", + "CMT_TOP_SW4A0_2", + "CMT_TOP_IMUX10_1", + "CMT_TOP_LOGIC_OUTS_L_B14_6", + "CMT_TOP_OCLK_10", + "CMT_TOP_LH5_2", + "CMT_TOP_LOGIC_OUTS_L_B18_8", + "CMT_TOP_SW2A2_6", + "CMT_TOP_EE2BEG2_1", + "CMT_TOP_NE4BEG1_0", + "CMT_TOP_NW4END3_6", + "CMT_TOP_NW4END3_8", + "CMT_TOP_WL1END0_7", + "CMT_TOP_IMUX10_11", + "CMT_TOP_NW2A1_4", + "CMT_TOP_IMUX9_7", + "CMT_TOP_BYP5_7", + "CMT_TOP_LOGIC_OUTS_L_B23_1", + "CMT_TOP_SW2A1_6", + "CMT_TOP_IMUX18_11", + "CMT_TOP_IMUX37_4", + "CMT_TOP_SW2A2_1", + "CMT_TOP_EE4B2_8", + "CMT_TOP_WW2A1_10", + "CMT_TOP_IMUX22_12", + "CMT_TOP_LOGIC_OUTS_L_B6_9", + "CMT_TOP_IMUX42_5", + "CMT_TOP_LOGIC_OUTS_L_B6_10", + "CMT_TOP_IMUX2_0", + "CMT_TOP_NE4C1_5", + "CMT_TOP_LH8_10", + "CMT_TOP_LOGIC_OUTS_L_B9_4", + "CMT_TOP_IMUX24_5", + "CMT_TOP_NW2A2_10", + "CMT_TOP_ER1BEG2_8", + "CMT_TOP_SW2A2_8", + "CMT_TOP_EE4B2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", + "CMT_TOP_FAN1_12", + "CMT_TOP_FAN5_6", + "CMT_TOP_FAN3_3", + "CMT_TOP_IMUX46_8", + "CMT_TOP_BLOCK_OUTS_L_B3_4", + "CMT_TOP_EE2A1_3", + "CMT_TOP_IMUX24_9", + "CMT_TOP_SE2A2_2", + "CMT_TOP_IMUX25_10", + "CMT_TOP_SE4C3_0", + "CMT_TOP_ER1BEG2_2", + "CMT_TOP_EE2A1_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", + "CMT_TOP_IMUX45_6", + "CMT_TOP_SW4END0_4", + "CMT_TOP_NW4A3_3", + "CMT_TOP_IMUX3_8", + "CMT_TOP_WW2END2_12", + "CMT_TOP_WR1END2_12", + "CMT_TOP_WW2END1_9", + "CMT_TOP_BLOCK_OUTS_L_B0_4", + "CMT_TOP_LH6_8", + "CMT_TOP_OCLK_11", + "CMT_TOP_BYP1_5", + "CMT_TOP_LOGIC_OUTS_L_B8_11", + "CMT_TOP_SW4A1_4", + "CMT_TOP_IMUX12_5", + "CMT_TOP_IMUX46_6", + "CMT_TOP_IMUX40_9", + "CMT_TOP_IMUX25_11", + "CMT_TOP_LH10_0", + "CMT_TOP_IMUX24_8", + "CMT_TOP_SE4C2_12", + "CMT_TOP_EE4BEG2_11", + "CMT_TOP_WW4END3_3", + "CMT_TOP_WW4B3_2", + "CMT_TOP_NE4BEG3_10", + "CMT_TOP_FAN3_0", + "CMT_TOP_OCLK1X_90_10", + "CMT_TOP_WW4B3_12", + "CMT_TOP_IMUX32_4", + "CMT_TOP_IMUX26_8", + "CMT_TOP_EE4A0_0", + "CMT_TOP_BLOCK_OUTS_L_B1_3", + "CMT_TOP_NW4END0_12", + "CMT_TOP_LOGIC_OUTS_L_B5_5", + "CMT_TOP_FAN0_11", + "CMT_TOP_SE2A0_2", + "CMT_TOP_LOGIC_OUTS_L_B2_5", + "CMT_TOP_IMUX44_4", + "CMT_TOP_SW4A2_11", + "CMT_TOP_SW4END0_9", + "CMT_TOP_EE4C1_5", + "CMT_TOP_EL1BEG1_0", + "CMT_TOP_IMUX29_4", + "CMT_TOP_CLK1_1", + "CMT_TOP_IMUX32_0", + "CMT_TOP_LOGIC_OUTS_L_B0_6", + "CMT_TOP_LOGIC_OUTS_L_B11_9", + "CMT_TOP_SW4END2_3", + "CMT_TOP_BYP4_2", + "CMT_TOP_WL1END3_3", + "CMT_TOP_CTRL0_2", + "CMT_TOP_FAN5_4", + "CMT_TOP_EE2A2_2", + "CMT_TOP_EE4A2_1", + "CMT_TOP_EE2A2_11", + "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "CMT_TOP_NW4A2_11", + "CMT_TOP_NW4END3_10", + "CMT_TOP_OCLK1X_90_12", + "CMT_TOP_WW4END0_8", + "CMT_TOP_LH11_8", + "CMT_TOP_IMUX45_5", + "CMT_TOP_IMUX18_2", + "CMT_TOP_WR1END0_6", + "CMT_TOP_IMUX3_1", + "CMT_TOP_IMUX10_12", + "CMT_TOP_WW4END3_1", + "CMT_TOP_WL1END2_10", + "CMT_TOP_IMUX16_2", + "CMT_TOP_IMUX34_10", + "CMT_TOP_FAN4_4", + "CMT_TOP_FAN7_3", + "CMT_TOP_LH4_0", + "CMT_TOP_NE4BEG2_0", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "CMT_TOP_FAN3_9", + "CMT_TOP_LOGIC_OUTS_L_B6_4", + "CMT_TOP_LOGIC_OUTS_L_B15_10", + "CMT_TOP_IMUX22_6", + "CMT_TOP_LOGIC_OUTS_L_B9_6", + "CMT_TOP_EL1BEG2_11", + "CMT_TOP_NE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B1_10", + "CMT_TOP_LOGIC_OUTS_L_B13_5", + "CMT_TOP_EE4C3_6", + "CMT_TOP_BLOCK_OUTS_L_B3_2", + "CMT_TOP_BYP1_10", + "CMT_TOP_FAN7_0", + "CMT_PLL_PHASER_WRCLK_TOFIFO", + "CMT_TOP_FAN2_9", + "CMT_TOP_WW2A0_11", + "CMT_TOP_EE2BEG2_6", + "CMT_TOP_SW4A1_2", + "CMT_TOP_EE4BEG1_10", + "CMT_TOP_LOGIC_OUTS_L_B3_2", + "CMT_TOP_IMUX4_1", + "CMT_TOP_CLK0_10", + "CMT_TOP_SE4BEG1_11", + "PLL_CLK_FREQ_BB_BUFOUT_NS3", + "CMT_TOP_IMUX26_2", + "CMT_TOP_BYP5_11", + "CMT_TOP_BYP2_10", + "CMT_TOP_FAN1_8", + "CMT_TOP_LH8_11", + "CMT_TOP_LOGIC_OUTS_L_B18_0", + "CMT_TOP_LOGIC_OUTS_L_B7_6", + "CMT_TOP_IMUX11_8", + "CMT_TOP_SE4C2_10", + "CMT_PLL_PHASER_WRENABLE_TOFIFO", + "CMT_TOP_ER1BEG3_4", + "CMT_TOP_IMUX5_6", + "CMT_TOP_IMUX38_0", + "CMT_TOP_OCLK1X_90_5", + "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "CMT_TOP_LH2_10", + "CMT_TOP_CLK1_7", + "CMT_TOP_EE4A0_10", + "CMT_TOP_WW4B3_1", + "CMT_TOP_NE4BEG1_1", + "CMT_TOP_IMUX16_5", + "CMT_TOP_CLK1_4", + "CMT_TOP_LH8_3", + "CMT_TOP_IMUX22_11", + "CMT_TOP_WW2END2_0", + "CMT_TOP_LOGIC_OUTS_L_B6_7", + "CMT_TOP_LH4_12", + "CMT_TOP_IMUX45_2", + "CMT_TOP_EE4BEG3_4", + "CMT_TOP_NE4C0_11", + "CMT_TOP_EE4B1_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", + "CMT_TOP_IMUX15_10", + "CMT_TOP_WW4C0_0", + "CMT_TOP_SW2A1_7", + "CMT_TOP_BYP2_4", + "CMT_TOP_EE4B3_1", + "CMT_TOP_SE4C3_3", + "CMT_TOP_WW4END1_9", + "CMT_TOP_EE4B1_12", + "CMT_TOP_LOGIC_OUTS_L_B18_9", + "CMT_TOP_SW4END1_4", + "CMT_TOP_IMUX12_12", + "CMT_TOP_NE4BEG2_3", + "CMT_TOP_OCLKDIV_9", + "CMT_TOP_WW2A0_7", + "CMT_TOP_IMUX34_7", + "CMT_TOP_BLOCK_OUTS_L_B1_5", + "CMT_TOP_WW2A2_12", + "CMT_TOP_WL1END2_5", + "CMT_TOP_IMUX27_4", + "CMT_TOP_OCLK_1", + "CMT_TOP_NW4END0_2", + "CMT_TOP_EE2A1_5", + "CMT_TOP_FAN4_2", + "CMT_TOP_CTRL1_11", + "CMT_TOP_WW4C3_8", + "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "CMT_TOP_NW4END1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", + "CMT_TOP_FAN3_1", + "CMT_TOP_IMUX45_9", + "CMT_TOP_NE4BEG3_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", + "CMT_TOP_WR1END3_9", + "CMT_TOP_SW4END2_11", + "CMT_TOP_WR1END2_6", + "CMT_TOP_SE2A2_5", + "CMT_TOP_SE4BEG1_4", + "CMT_TOP_FAN2_7", + "CMT_TOP_LOGIC_OUTS_L_B13_9", + "CMT_TOP_WW2END2_11", + "CMT_TOP_EE2BEG1_5", + "CMT_TOP_SW4A3_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", + "CMT_TOP_NE2A2_12", + "CMT_TOP_LH10_8", + "CMT_TOP_IMUX42_6", + "CMT_TOP_EE4B1_1", + "CMT_TOP_BYP0_10", + "CMT_TOP_SE2A0_4", + "CMT_TOP_MONITOR_N_5", + "CMT_TOP_CLK1_11", + "CMT_TOP_ER1BEG1_10", + "CMT_TOP_EE4C3_11", + "CMT_TOP_EE2BEG1_8", + "CMT_TOP_IMUX32_10", + "CMT_TOP_NW4A0_4", + "CMT_TOP_EL1BEG2_12", + "CMT_TOP_SW4A3_10", + "CMT_TOP_LOGIC_OUTS_L_B19_5", + "CMT_TOP_NW4END2_8", + "CMT_TOP_SE2A3_12", + "CMT_TOP_EE2A0_10", + "CMT_TOP_EE2A3_9", + "CMT_TOP_SW2A1_1", + "CMT_TOP_EE4B2_4", + "CMT_TOP_BLOCK_OUTS_L_B1_6", + "CMT_TOP_SW4A2_8", + "CMT_TOP_IMUX18_0", + "CMT_TOP_BLOCK_OUTS_L_B1_0", + "CMT_TOP_BYP6_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", + "CMT_TOP_NW4END1_6", + "CMT_TOP_LOGIC_OUTS_L_B2_9", + "CMT_TOP_LH7_4", + "CMT_TOP_IMUX23_0", + "CMT_TOP_IMUX43_8", + "CMT_TOP_EE4B2_0", + "CMT_TOP_IMUX21_4", + "CMT_TOP_IMUX21_2", + "CMT_TOP_EE2BEG1_11", + "CMT_TOP_EE4A2_9", + "CMT_TOP_ER1BEG2_3", + "CMT_TOP_EE4B0_5", + "CMT_TOP_IMUX47_10", + "CMT_TOP_IMUX43_6", + "CMT_TOP_NW4A1_6", + "CMT_TOP_WW4C0_1", + "CMT_TOP_WW2A3_0", + "CMT_TOP_FAN7_1", + "CMT_TOP_MONITOR_P_12", + "CMT_TOP_NW2A1_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", + "CMT_TOP_NE4BEG0_9", + "CMT_TOP_EE2BEG2_10", + "CMT_TOP_IMUX4_3", + "CMT_TOP_EE4BEG3_3", + "CMT_TOP_LH1_10", + "CMT_TOP_EE4BEG2_12", + "CMT_TOP_EE4B0_10", + "CMT_TOP_SE2A3_2", + "CMT_TOP_IMUX16_6", + "CMT_TOP_IMUX1_5", + "CMT_TOP_SE4C1_4", + "CMT_TOP_LOGIC_OUTS_L_B22_5", + "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "CMT_TOP_NW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B1_3", + "CMT_TOP_EE4B3_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", + "CMT_TOP_IMUX26_7", + "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "CMT_TOP_NE4C1_0", + "CMT_TOP_EE2A3_8", + "CMT_TOP_IMUX45_11", + "CMT_TOP_FAN4_12", + "CMT_TOP_ER1BEG2_12", + "CMT_TOP_WW4B2_4", + "CMT_TOP_IMUX40_0", + "CMT_TOP_IMUX14_6", + "CMT_TOP_NW2A3_0", + "CMT_TOP_EE4A0_2", + "CMT_TOP_SE4BEG0_7", + "CMT_TOP_EE2BEG1_6", + "CMT_TOP_LOGIC_OUTS_L_B18_1", + "CMT_TOP_NE4BEG1_4", + "CMT_TOP_OCLK1X_90_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", + "CMT_TOP_NW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B18_10", + "CMT_TOP_IMUX8_7", + "CMT_TOP_WW2END0_4", + "CMT_TOP_SW4A1_7", + "CMT_TOP_CTRL1_9", + "CMT_TOP_LH10_7", + "CMT_TOP_EE4C2_3", + "CMT_TOP_SE2A3_9", + "CMT_TOP_IMUX1_12", + "CMT_TOP_EL1BEG3_3", + "CMT_TOP_BYP6_8", + "CMT_TOP_LOGIC_OUTS_L_B19_10", + "PLLOUT_CLK_FREQ_BB_1", + "CMT_TOP_ICLK_11", + "CMT_TOP_EE2A1_11", + "CMT_TOP_WW4C1_12", + "CMT_TOP_SE2A1_0", + "CMT_TOP_MONITOR_N_0", + "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "CMT_TOP_WR1END0_0", + "CMT_TOP_WW2A1_9", + "CMT_TOP_FAN1_11", + "CMT_TOP_IMUX18_4", + "CMT_TOP_WL1END1_5", + "CMT_TOP_LOGIC_OUTS_L_B12_8", + "CMT_TOP_NE2A2_3", + "CMT_TOP_LOGIC_OUTS_L_B20_7", + "CMT_TOP_WW4END1_3", + "CMT_TOP_IMUX24_1", + "CMT_TOP_WW2END2_6", + "CMT_TOP_WW2A2_11", + "CMT_TOP_SW2A0_10", + "CMT_TOP_EE2A3_0", + "CMT_TOP_ER1BEG0_9", + "CMT_TOP_WW2A3_7", + "CMT_TOP_WL1END2_0", + "CMT_TOP_LOGIC_OUTS_L_B22_1", + "CMT_TOP_SW2A0_6", + "CMT_TOP_LOGIC_OUTS_L_B5_12", + "CMT_TOP_IMUX13_11", + "CMT_TOP_NW4A3_9", + "CMT_TOP_LOGIC_OUTS_L_B10_7", + "CMT_TOP_NW2A0_1", + "CMT_TOP_IMUX6_0", + "CMT_TOP_LH1_11", + "CMT_TOP_NW2A2_6", + "CMT_TOP_CTRL0_0", + "CMT_TOP_WR1END1_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", + "CMT_TOP_IMUX31_0", + "CMT_TOP_IMUX43_0", + "CMT_TOP_SE2A1_11", + "CMT_TOP_LOGIC_OUTS_L_B7_3", + "CMT_TOP_WW4C3_0", + "CMT_TOP_LH11_1", + "CMT_TOP_SW2A1_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", + "CMT_TOP_NW4A3_11", + "CMT_TOP_EE4C3_4", + "CMT_TOP_ER1BEG3_8", + "CMT_TOP_SW4A3_3", + "CMT_TOP_FAN7_4", + "CMT_TOP_NW4END0_4", + "CMT_TOP_FAN1_6", + "CMT_TOP_ER1BEG2_1", + "CMT_TOP_IMUX22_10", + "CMT_TOP_WW4B2_5", + "CMT_TOP_BYP4_5", + "CMT_TOP_NE4C1_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", + "CMT_TOP_IMUX20_4", + "CMT_TOP_WW2A2_1", + "CMT_TOP_WR1END1_11", + "CMT_TOP_IMUX18_12", + "CMT_TOP_SW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B22_12", + "CMT_TOP_LOGIC_OUTS_L_B5_7", + "CMT_TOP_NE4BEG0_11", + "CMT_TOP_WR1END3_10", + "CMT_TOP_WW4A1_6", + "CMT_TOP_BYP7_11", + "CMT_TOP_LH2_5", + "CMT_TOP_LOGIC_OUTS_L_B1_4", + "CMT_TOP_NW2A1_12", + "CMT_TOP_SE2A1_3", + "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "CMT_TOP_WW4B0_9", + "CMT_TOP_ICLKDIV_1", + "CMT_TOP_IMUX41_12", + "CMT_TOP_IMUX0_4", + "CMT_TOP_SE2A3_11", + "CMT_TOP_WR1END0_7", + "CMT_TOP_LOGIC_OUTS_L_B16_9", + "CMT_TOP_IMUX20_3", + "CMT_TOP_CTRL1_10", + "CMT_TOP_LOGIC_OUTS_L_B15_6", + "CMT_TOP_EE4A2_5", + "CMT_TOP_SE4C1_11", + "CMT_TOP_FAN3_5", + "CMT_TOP_IMUX27_12", + "CMT_TOP_NW4END0_0", + "CMT_TOP_NW4A3_10", + "CMT_TOP_FAN1_4", + "CMT_TOP_IMUX12_2", + "CMT_TOP_BLOCK_OUTS_L_B0_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", + "CMT_TOP_IMUX43_10", + "CMT_TOP_NW4A3_8", + "CMT_TOP_WW4B0_2", + "CMT_TOP_NE2A0_7", + "CMT_TOP_IMUX34_5", + "CMT_TOP_EE4C2_12", + "CMT_TOP_EE4C2_5", + "CMT_TOP_WL1END2_2", + "CMT_TOP_IMUX6_3", + "CMT_TOP_NE4BEG0_10", + "CMT_TOP_SE4C3_8", + "CMT_TOP_SW4A0_11", + "CMT_TOP_IMUX35_7", + "CMT_TOP_NE4BEG1_2", + "CMT_TOP_IMUX28_10", + "CMT_TOP_LOGIC_OUTS_L_B13_6", + "CMT_TOP_IMUX2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_5", + "CMT_TOP_NE4BEG3_0", + "CMT_TOP_CTRL0_10", + "CMT_TOP_IMUX46_12", + "CMT_TOP_WW4END2_2", + "CMT_TOP_WL1END0_8", + "CMT_TOP_LOGIC_OUTS_L_B18_2", + "CMT_TOP_IMUX47_6", + "CMT_TOP_BYP1_12", + "CMT_TOP_IMUX23_2", + "CMT_TOP_WL1END0_9", + "CMT_TOP_LOGIC_OUTS_L_B7_5", + "CMT_TOP_IMUX39_6", + "CMT_TOP_EE4A3_12", + "CMT_TOP_IMUX2_12", + "CMT_TOP_EE4C0_10", + "CMT_TOP_IMUX6_4", + "CMT_TOP_LOGIC_OUTS_L_B20_10", + "CMT_TOP_IMUX12_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", + "CMT_TOP_LH8_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", + "CMT_TOP_IMUX36_9", + "CMT_TOP_EE4A2_12", + "CMT_TOP_BYP2_5", + "CMT_TOP_NW2A0_10", + "CMT_TOP_SE4C3_2", + "CMT_TOP_SE4C0_4", + "CMT_TOP_IMUX21_11", + "CMT_TOP_IMUX38_8", + "CMT_TOP_IMUX0_6", + "CMT_TOP_NE4BEG3_11", + "CMT_TOP_ER1BEG1_7", + "CMT_TOP_NE2A3_10", + "CMT_TOP_WW4B1_4", + "CMT_TOP_SE2A0_8", + "CMT_TOP_NE2A2_2", + "CMT_TOP_NE2A0_1", + "CMT_TOP_IMUX31_4", + "CMT_TOP_R_UPPER_T_PLLE2_RST", + "CMT_TOP_NE2A3_9", + "CMT_TOP_WW4B3_9", + "CMT_TOP_IMUX5_1", + "CMT_TOP_IMUX47_2", + "CMT_TOP_LH12_1", + "CMT_TOP_SW2A3_10", + "CMT_TOP_IMUX26_1", + "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "CMT_TOP_WW2END3_6", + "CMT_TOP_NW2A0_8", + "CMT_TOP_EE2BEG3_7", + "CMT_TOP_SE4BEG2_8", + "CMT_TOP_IMUX44_3", + "CMT_TOP_LH3_4", + "CMT_TOP_EE2A2_1", + "CMT_TOP_WW4A2_3", + "CMT_TOP_NW2A3_2", + "CMT_TOP_EL1BEG1_12", + "CMT_TOP_FAN1_2", + "CMT_TOP_IMUX39_8", + "CMT_TOP_SW4END2_7", + "CMT_TOP_FAN2_4", + "CMT_TOP_EE4A1_6", + "CMT_TOP_EE4B1_3", + "CMT_TOP_WW2A2_9", + "CMT_TOP_IMUX42_10", + "CMT_TOP_EE4BEG0_11", + "CMT_TOP_WW4END0_1", + "CMT_TOP_IMUX9_4", + "CMT_TOP_EE2BEG0_0", + "CMT_TOP_SE2A0_5", + "CMT_TOP_EE4B1_0", + "CMT_TOP_IMUX34_11", + "CMT_TOP_ER1BEG1_8", + "CMT_TOP_ICLKDIV_0", + "CMT_TOP_IMUX10_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", + "CMT_TOP_WL1END3_2", + "CMT_TOP_NW4A2_8", + "CMT_TOP_IMUX35_5", + "CMT_TOP_WW4A2_6", + "CMT_TOP_LOGIC_OUTS_L_B22_7", + "CMT_TOP_ICLKDIV_5", + "CMT_TOP_NE4C3_2", + "CMT_TOP_NE2A3_8", + "CMT_TOP_WW4END3_4", + "CMT_TOP_LH1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", + "CMT_TOP_CTRL1_5", + "CMT_TOP_MONITOR_P_7", + "CMT_TOP_EE2BEG3_10", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "CMT_TOP_LH7_9", + "CMT_TOP_CLK0_8", + "CMT_TOP_LOGIC_OUTS_L_B16_3", + "CMT_TOP_NE2A0_5", + "CMT_TOP_SW4END2_6", + "CMT_TOP_EE2BEG2_4", + "CMT_TOP_EE4C3_5", + "CMT_TOP_R_CLKFBOUT2IN", + "CMT_TOP_IMUX8_8", + "CMT_TOP_EE2BEG3_1", + "CMT_TOP_EE2A2_4", + "CMT_TOP_NE2A3_5", + "CMT_TOP_IMUX13_1", + "CMT_TOP_WW2END0_3", + "CMT_TOP_LOGIC_OUTS_L_B2_8", + "CMT_TOP_EE4C1_3", + "CMT_TOP_EE4A2_0", + "CMT_TOP_R_UPPER_T_CLKPLL2", + "CMT_TOP_EE4B2_11", + "CMT_TOP_BLOCK_OUTS_L_B3_8", + "CMT_TOP_ER1BEG0_1", + "CMT_TOP_ER1BEG3_12", + "CMT_TOP_NE4C2_9", + "CMT_TOP_EE2BEG3_12", + "CMT_TOP_NW2A2_4", + "CMT_TOP_FAN2_2", + "CMT_TOP_IMUX37_3", + "CMT_TOP_IMUX37_8", + "CMT_TOP_ICLKDIV_4", + "CMT_TOP_LOGIC_OUTS_L_B9_12", + "CMT_TOP_CTRL1_2", + "CMT_TOP_EL1BEG0_10", + "CMT_TOP_NE4BEG1_11", + "CMT_TOP_NE4BEG1_12", + "CMT_TOP_EE4B0_0", + "CMT_TOP_SE2A0_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", + "CMT_TOP_IMUX18_9", + "CMT_TOP_WW2END3_12", + "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "CMT_TOP_OCLK1X_90_2", + "CMT_TOP_EE2A1_10", + "CMT_TOP_EL1BEG3_10", + "CMT_TOP_NW4A2_4", + "CMT_TOP_WW4A3_9", + "CMT_TOP_IMUX3_2", + "CMT_TOP_SE2A1_7", + "CMT_TOP_WW4END1_0", + "CMT_TOP_ER1BEG1_5", + "CMT_TOP_EE2BEG2_2", + "CMT_TOP_EE2BEG2_5", + "CMT_TOP_NW4END2_6", + "CMT_TOP_IMUX34_1", + "CMT_TOP_LH6_9", + "CMT_TOP_IMUX32_5", + "CMT_TOP_NW4A2_1", + "CMT_TOP_SW4A2_4", + "CMT_TOP_NE4C2_11", + "CMT_TOP_WW4END1_10", + "CMT_TOP_LH9_4", + "CMT_TOP_LOGIC_OUTS_L_B7_4", + "CMT_TOP_NE4C3_6", + "CMT_TOP_WL1END3_6", + "CMT_TOP_WW2END3_1", + "CMT_TOP_BYP4_3", + "CMT_TOP_WW2END2_10", + "CMT_TOP_LOGIC_OUTS_L_B8_9", + "CMT_TOP_SE2A0_7", + "CMT_TOP_IMUX35_11", + "CMT_TOP_WW2END2_2", + "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "CMT_TOP_BYP7_5", + "CMT_TOP_SW4END0_11", + "CMT_TOP_WW4END0_10", + "CMT_TOP_IMUX0_8", + "CMT_TOP_IMUX45_12", + "CMT_TOP_R_UPPER_T_CLKIN1", + "CMT_TOP_SW2A1_2", + "CMT_TOP_EE4B1_6", + "CMT_TOP_WW2END0_10", + "CMT_TOP_IMUX20_5", + "CMT_TOP_EE4BEG1_6", + "CMT_TOP_BYP5_0", + "CMT_TOP_IMUX32_9", + "CMT_TOP_EE2A0_12", + "CMT_TOP_FAN5_9", + "CMT_TOP_IMUX38_10", + "CMT_TOP_LH1_4", + "CMT_TOP_NW4A0_6", + "CMT_TOP_WW4END3_8", + "CMT_TOP_EE4C2_2", + "CMT_TOP_CLK1_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", + "CMT_TOP_WL1END3_11", + "CMT_TOP_NW4A0_12", + "CMT_TOP_WW2END3_4", + "CMT_TOP_WW4C1_8", + "CMT_TOP_IMUX39_10", + "CMT_TOP_WR1END1_8", + "CMT_TOP_EE2BEG2_3", + "CMT_TOP_WW4END3_10", + "CMT_TOP_SE2A3_5", + "CMT_TOP_EE4C3_10", + "CMT_TOP_EE4B3_6", + "CMT_TOP_LOGIC_OUTS_L_B3_10", + "CMT_TOP_EE4B3_7", + "CMT_TOP_NW4END0_7", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "CMT_TOP_SE4C3_4", + "CMT_TOP_SW4A1_10", + "CMT_TOP_LH4_6", + "CMT_TOP_IMUX22_7", + "CMT_TOP_NW2A2_5", + "CMT_TOP_LH7_3", + "CMT_TOP_IMUX20_1", + "CMT_TOP_WW4B1_3", + "CMT_TOP_FAN5_8", + "CMT_TOP_SE2A1_9", + "CMT_TOP_OCLK_4", + "CMT_TOP_SE4C2_0", + "CMT_TOP_NE2A0_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", + "CMT_TOP_LOGIC_OUTS_L_B7_10", + "CMT_TOP_IMUX11_5", + "CMT_TOP_WW2A0_2", + "CMT_TOP_IMUX44_11", + "CMT_TOP_EE2BEG0_8", + "CMT_TOP_WW4A1_5", + "CMT_TOP_IMUX27_11", + "CMT_TOP_IMUX17_8", + "CMT_TOP_LH12_5", + "CMT_TOP_IMUX43_2", + "CMT_TOP_LOGIC_OUTS_L_B3_12", + "CMT_TOP_IMUX41_11", + "CMT_TOP_EE4BEG1_5", + "CMT_TOP_ER1BEG2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_3", + "CMT_TOP_EE4BEG3_11", + "CMT_TOP_IMUX46_1", + "CMT_TOP_EE4C2_6", + "CMT_TOP_WW4C3_1", + "CMT_TOP_ICLK_1", + "CMT_TOP_WL1END1_0", + "CMT_TOP_LOGIC_OUTS_L_B9_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", + "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "CMT_TOP_IMUX42_1", + "CMT_TOP_BYP7_6", + "CMT_TOP_NW4END1_10", + "CMT_TOP_LOGIC_OUTS_L_B20_4", + "CMT_TOP_NE4BEG1_3", + "CMT_TOP_NW4A3_2", + "CMT_TOP_SW4A0_5", + "CMT_TOP_IMUX4_6", + "CMT_TOP_CLK0_12", + "CMT_TOP_ER1BEG3_7", + "CMT_TOP_WW4END0_6", + "CMT_TOP_LOGIC_OUTS_L_B16_6", + "CMT_TOP_SE4C3_12", + "CMT_TOP_IMUX3_6", + "CMT_TOP_LOGIC_OUTS_L_B11_11", + "CMT_TOP_WW2A3_1", + "CMT_TOP_IMUX35_3", + "CMT_TOP_SW4END0_10", + "CMT_TOP_LH12_2", + "CMT_TOP_IMUX0_11", + "CMT_TOP_WW4B2_11", + "CMT_TOP_EE2BEG3_11", + "CMT_TOP_WW4END2_6", + "CMT_TOP_LH11_7", + "CMT_TOP_SW4END3_3", + "CMT_TOP_IMUX28_12", + "CMT_TOP_WW4B1_12", + "CMT_TOP_NW4A1_7", + "CMT_TOP_WW2A3_5", + "CMT_TOP_LOGIC_OUTS_L_B9_11", + "CMT_TOP_IMUX19_6", + "CMT_TOP_FAN4_8", + "CMT_TOP_EE2A2_3", + "CMT_TOP_IMUX34_3", + "CMT_TOP_WW4END1_11", + "CMT_TOP_CLK0_7", + "CMT_TOP_EE4A3_7", + "CMT_TOP_SE4C3_7", + "CMT_TOP_WW4A3_1", + "CMT_TOP_LOGIC_OUTS_L_B10_11", + "CMT_TOP_IMUX35_8", + "CMT_TOP_SE4C1_1", + "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "CMT_TOP_IMUX10_0", + "CMT_TOP_LH11_3", + "CMT_TOP_SE2A0_9", + "CMT_TOP_WL1END3_7", + "CMT_TOP_IMUX34_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", + "CMT_TOP_IMUX8_4", + "CMT_TOP_WR1END3_3", + "CMT_TOP_IMUX46_4", + "CMT_TOP_SE2A2_10", + "CMT_TOP_WW4C2_4", + "CMT_TOP_BLOCK_OUTS_L_B2_0", + "CMT_TOP_IMUX22_0", + "CMT_TOP_IMUX9_11", + "CMT_TOP_WW4A2_9", + "CMT_TOP_SE4C1_0", + "CMT_PHASER_D_OCLK90_TOIOI", + "CMT_TOP_IMUX14_5", + "CMT_TOP_WL1END2_9", + "CMT_TOP_ER1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B2_1", + "CMT_TOP_LH5_5", + "CMT_TOP_EE4C1_1", + "CMT_TOP_NW4A0_11", + "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "CMT_TOP_WW4END0_4", + "CMT_TOP_IMUX13_8", + "CMT_TOP_LOGIC_OUTS_L_B23_5", + "CMT_TOP_LOGIC_OUTS_L_B4_2", + "CMT_TOP_NW2A1_8", + "CMT_TOP_IMUX7_5", + "CMT_TOP_EE2BEG1_1", + "CMT_TOP_SE4C2_3", + "CMT_TOP_WW4END0_12", + "CMT_TOP_NE4C0_3", + "CMT_TOP_SE4BEG0_0", + "CMT_TOP_EE4B0_8", + "CMT_TOP_IMUX27_5", + "CMT_TOP_OCLK_0", + "CMT_TOP_LH7_8", + "CMT_TOP_IMUX7_8", + "CMT_TOP_ICLK_0", + "CMT_TOP_WW2END2_3", + "CMT_TOP_WR1END0_10", + "CMT_TOP_IMUX7_1", + "CMT_TOP_WW2END1_5", + "CMT_TOP_IMUX44_6", + "CMT_TOP_IMUX22_3", + "CMT_TOP_NE4C2_4", + "CMT_TOP_IMUX8_12", + "CMT_TOP_WL1END1_2", + "CMT_TOP_EL1BEG3_5", + "CMT_TOP_WR1END3_11", + "CMT_TOP_EL1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B10_0", + "CMT_TOP_IMUX30_12", + "CMT_TOP_SE4C3_6", + "CMT_TOP_LH9_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", + "CMT_TOP_EE4C0_12", + "CMT_TOP_NW2A1_10", + "CMT_TOP_SW4A3_8", + "CMT_TOP_EE4B1_7", + "CMT_TOP_WW2A2_0", + "CMT_TOP_WW2A1_0", + "CMT_TOP_IMUX13_3", + "CMT_TOP_IMUX18_7", + "CMT_TOP_ER1BEG0_2", + "CMT_TOP_CTRL1_7", + "CMT_TOP_IMUX0_5", + "CMT_TOP_IMUX28_4", + "CMT_TOP_WW4C3_5", + "CMT_TOP_LH1_8", + "CMT_TOP_LH10_10", + "CMT_TOP_IMUX42_3", + "CMT_TOP_IMUX3_12", + "CMT_TOP_LOGIC_OUTS_L_B6_0", + "CMT_TOP_LOGIC_OUTS_L_B18_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "CMT_TOP_WL1END1_1", + "CMT_TOP_LOGIC_OUTS_L_B0_4", + "CMT_TOP_EE2A1_12", + "CMT_TOP_IMUX3_10", + "CMT_TOP_OCLK_12", + "CMT_TOP_SE4BEG3_1", + "CMT_TOP_WW2END2_8", + "CMT_TOP_EE2A0_8", + "CMT_TOP_LH7_1", + "CMT_TOP_SW2A3_5", + "CMT_TOP_IMUX31_11", + "CMT_PLL_PHYCTRL_SYNC_BB_UP", + "CMT_TOP_IMUX32_12", + "CMT_TOP_IMUX19_3", + "CMT_TOP_NW4END2_12", + "CMT_TOP_FAN0_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", + "CMT_TOP_WW2END1_4", + "CMT_TOP_EL1BEG3_1", + "CMT_TOP_NW4END3_7", + "CMT_TOP_EE2A3_12", + "CMT_TOP_CLK1_2", + "CMT_TOP_NE4BEG0_4", + "CMT_TOP_LOGIC_OUTS_L_B23_8", + "CMT_TOP_SW4END0_2", + "CMT_TOP_IMUX34_9", + "CMT_TOP_EE4B0_6", + "CMT_TOP_EE4B2_5", + "CMT_TOP_IMUX42_2", + "CMT_TOP_WW4C2_9", + "CMT_TOP_NE4BEG0_5", + "CMT_TOP_WW2A2_2", + "CMT_TOP_SW4A2_5", + "CMT_TOP_LOGIC_OUTS_L_B8_12", + "CMT_TOP_NE2A3_2", + "CMT_TOP_IMUX43_1", + "CMT_TOP_WW4END2_10", + "CMT_TOP_EE4C1_4", + "CMT_TOP_IMUX44_9", + "CMT_TOP_WW4B1_6", + "CMT_TOP_NW4A1_11", + "CMT_TOP_IMUX42_0", + "CMT_TOP_EE2BEG3_6", + "CMT_TOP_SE4BEG0_10", + "CMT_TOP_IMUX24_7", + "CMT_TOP_EE4B0_12", + "CMT_TOP_IMUX47_4", + "CMT_TOP_WL1END1_12", + "CMT_TOP_NE2A1_2", + "CMT_TOP_BYP5_2", + "CMT_TOP_IMUX39_4", + "CMT_TOP_FAN7_8", + "CMT_PHASER_D_OCLKDIV_TOIOI", + "CMT_TOP_IMUX40_8", + "CMT_TOP_SE4BEG3_10", + "CMT_TOP_SW2A1_10", + "CMT_TOP_ICLKDIV_2", + "CMT_TOP_IMUX33_0", + "CMT_TOP_NE4C1_1", + "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "CMT_TOP_NE4C3_8", + "CMT_TOP_EE4A3_10", + "CMT_TOP_IMUX28_3", + "CMT_TOP_IMUX1_4", + "CMT_TOP_IMUX13_4", + "CMT_TOP_MONITOR_N_1", + "CMT_TOP_EE4B2_12", + "CMT_TOP_LOGIC_OUTS_L_B2_10", + "CMT_TOP_SW4END0_12", + "CMT_TOP_EE4B1_8", + "PLLOUT_CLK_FREQ_BB_2", + "CMT_TOP_NE4BEG0_12", + "CMT_TOP_SW4A1_9", + "CMT_TOP_SE4C2_8", + "CMT_TOP_LH1_5", + "CMT_TOP_WW4END3_11", + "CMT_TOP_NE2A0_4", + "CMT_TOP_LOGIC_OUTS_L_B8_4", + "CMT_TOP_WW2END3_3", + "CMT_TOP_WL1END3_12", + "CMT_TOP_EL1BEG2_5", + "CMT_TOP_NE4C0_2", + "CMT_TOP_IMUX44_12", + "CMT_TOP_FAN6_7", + "CMT_TOP_WW4B1_10", + "CMT_TOP_IMUX19_10", + "CMT_TOP_ER1BEG0_5", + "CMT_PLL_PHASERREF_ABOVE1", + "CMT_TOP_LH7_5", + "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "CMT_TOP_LOGIC_OUTS_L_B1_12", + "CMT_TOP_IMUX19_7", + "CMT_TOP_WL1END2_8", + "CMT_TOP_FAN0_2", + "CMT_TOP_FAN6_0", + "CMT_TOP_IMUX27_3", + "CMT_TOP_IMUX47_5", + "CMT_TOP_IMUX24_0", + "CMT_TOP_IMUX26_0", + "CMT_TOP_WR1END2_3", + "CMT_TOP_EE4A0_12", + "CMT_TOP_WR1END1_9", + "CMT_TOP_LOGIC_OUTS_L_B8_5", + "CMT_TOP_NE4C0_6", + "CMT_TOP_EE4C0_0", + "CMT_TOP_EE2A3_10", + "CMT_TOP_SE4C1_8", + "CMT_TOP_EE2A0_2", + "CMT_TOP_IMUX42_4", + "CMT_TOP_WL1END3_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", + "CMT_TOP_LOGIC_OUTS_L_B12_7", + "CMT_TOP_EE4BEG2_10", + "CMT_TOP_IMUX47_9", + "CMT_TOP_SE4C1_7", + "CMT_TOP_FAN0_10", + "CMT_TOP_IMUX45_7", + "CMT_TOP_EE2A3_4", + "PLL_CLK_FREQ_BB0_NS", + "CMT_TOP_ER1BEG2_10", + "CMT_TOP_IMUX13_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", + "CMT_TOP_WW2END1_10", + "CMT_TOP_EE2BEG1_3", + "CMT_TOP_IMUX29_2", + "CMT_TOP_FAN0_4", + "CMT_TOP_EL1BEG0_3", + "CMT_TOP_IMUX33_9", + "CMT_TOP_SW4END3_1", + "CMT_TOP_IMUX5_5", + "CMT_TOP_NE4BEG3_12", + "CMT_TOP_OCLK1X_90_4", + "CMT_TOP_NW4A1_9", + "CMT_TOP_WW2END0_11", + "CMT_TOP_NW2A0_0", + "CMT_TOP_SE4C0_8", + "CMT_TOP_IMUX16_10", + "CMT_TOP_EE4BEG0_0", + "CMT_TOP_IMUX15_4", + "CMT_TOP_LH10_11", + "CMT_TOP_SE4BEG3_5", + "CMT_TOP_NW2A2_9", + "CMT_TOP_EE4B3_11", + "CMT_TOP_EE2A1_0", + "CMT_TOP_WW4A1_1", + "CMT_TOP_LOGIC_OUTS_L_B14_11", + "CMT_TOP_LH9_9", + "CMT_TOP_EE4B0_1", + "CMT_TOP_WL1END2_12", + "CMT_TOP_SE4BEG3_4", + "CMT_TOP_LOGIC_OUTS_L_B0_9", + "CMT_TOP_WW2END0_12", + "CMT_TOP_SE2A0_10", + "CMT_TOP_BLOCK_OUTS_L_B3_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", + "CMT_TOP_NE4C2_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", + "CMT_TOP_NE4BEG3_4", + "CMT_TOP_EE2BEG0_12", + "CMT_TOP_CLK0_3", + "CMT_TOP_IMUX14_1", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "CMT_TOP_LH8_9", + "CMT_TOP_WW2A3_11", + "CMT_TOP_SE4BEG1_6", + "CMT_TOP_SE4C1_12", + "CMT_TOP_IMUX2_7", + "CMT_TOP_CLK1_6", + "CMT_TOP_IMUX38_3", + "CMT_TOP_WW4C3_6", + "CMT_TOP_EE4BEG3_1", + "CMT_TOP_EE4C0_4", + "CMT_TOP_IMUX28_8", + "CMT_TOP_NW4END0_3", + "CMT_TOP_LH2_6", + "CMT_TOP_IMUX11_9", + "CMT_TOP_WW4A1_11", + "CMT_TOP_LOGIC_OUTS_L_B19_6", + "CMT_TOP_BYP4_8", + "CMT_TOP_LOGIC_OUTS_L_B21_10", + "CMT_TOP_EE4C1_6", + "CMT_TOP_NW2A0_4", + "CMT_TOP_NW4END3_9", + "CMT_TOP_IMUX36_11", + "CMT_TOP_LH12_7", + "CMT_TOP_WW2END1_7", + "CMT_TOP_LH6_2", + "CMT_TOP_EE4A3_2", + "CMT_TOP_IMUX45_8", + "CMT_TOP_EL1BEG1_3", + "CMT_TOP_EE2A0_3", + "CMT_TOP_WW4B0_10", + "CMT_TOP_IMUX33_4", + "CMT_TOP_BYP1_11", + "CMT_TOP_LOGIC_OUTS_L_B2_4", + "CMT_TOP_WL1END0_11", + "CMT_TOP_SW2A0_5", + "CMT_TOP_EE4C3_8", + "CMT_TOP_IMUX35_2", + "CMT_TOP_FAN7_7", + "CMT_TOP_WW2A3_10", + "CMT_TOP_SE4BEG2_6", + "CMT_TOP_NW4END1_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "CMT_TOP_IMUX36_10", + "CMT_TOP_CLK1_8", + "CMT_TOP_EE4BEG1_3", + "CMT_TOP_SW4END3_2", + "CMT_TOP_WL1END0_5", + "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "CMT_TOP_SE4BEG2_9", + "CMT_TOP_NE4C0_1", + "CMT_TOP_IMUX11_1", + "CMT_TOP_SW2A1_5", + "CMT_TOP_IMUX33_6", + "CMT_TOP_EE4C2_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", + "CMT_TOP_BLOCK_OUTS_L_B0_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", + "CMT_TOP_EE4B3_3", + "CMT_TOP_WW4A1_0", + "CMT_TOP_LH5_12", + "CMT_TOP_LOGIC_OUTS_L_B19_0", + "CMT_TOP_WW2END2_1", + "CMT_TOP_NE4BEG0_8", + "CMT_TOP_WW4END0_11", + "CMT_TOP_IMUX25_4", + "CMT_TOP_IMUX2_9", + "CMT_TOP_R_UPPER_T_CLKIN2", + "CMT_TOP_EE4BEG0_1", + "CMT_TOP_SW4END1_0", + "CMT_TOP_EE2A1_1", + "CMT_TOP_SE2A1_4", + "CMT_TOP_LOGIC_OUTS_L_B2_3", + "CMT_TOP_LOGIC_OUTS_L_B3_8", + "CMT_TOP_OCLK1X_90_11", + "CMT_TOP_WR1END0_2", + "CMT_TOP_EE4A3_6", + "CMT_TOP_NE2A2_7", + "CMT_TOP_SE4C2_11", + "CMT_TOP_LOGIC_OUTS_L_B14_1", + "CMT_TOP_BYP2_11", + "CMT_TOP_BYP1_1", + "CMT_TOP_LH11_6", + "CMT_TOP_EL1BEG0_9", + "CMT_TOP_NW2A0_11", + "CMT_TOP_IMUX21_8", + "CMT_TOP_IMUX36_3", + "CMT_TOP_WR1END0_3", + "CMT_TOP_WW4B3_5", + "CMT_TOP_EL1BEG1_6", + "CMT_TOP_IMUX31_9", + "CMT_TOP_LOGIC_OUTS_L_B13_10", + "CMT_TOP_ICLKDIV_10", + "CMT_TOP_BYP6_0", + "CMT_TOP_SW4END2_12", + "CMT_TOP_EE4BEG0_6", + "CMT_TOP_IMUX36_6", + "CMT_TOP_WR1END1_6", + "CMT_TOP_SE4C0_2", + "CMT_TOP_LH11_10", + "CMT_TOP_EE4A2_8", + "CMT_TOP_SE2A1_1", + "CMT_TOP_NW4END1_2", + "CMT_TOP_NW4END1_8", + "CMT_TOP_IMUX31_3", + "CMT_TOP_EE4C1_8", + "CMT_TOP_IMUX20_11", + "CMT_TOP_OCLKDIV_10", + "CMT_TOP_WW4END1_4", + "CMT_TOP_EE2BEG0_6", + "CMT_TOP_NW2A2_12", + "CMT_TOP_IMUX9_10", + "CMT_TOP_SW4A1_5", + "CMT_TOP_SE4C0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_1", + "CMT_TOP_SW2A1_0", + "CMT_TOP_SE4BEG1_7", + "CMT_TOP_EE2A0_0", + "CMT_TOP_CTRL1_4", + "CMT_TOP_MONITOR_N_7", + "CMT_TOP_IMUX10_2", + "CMT_TOP_WW4A1_2", + "CMT_TOP_WW4C3_4", + "CMT_TOP_EL1BEG3_2", + "CMT_TOP_IMUX5_9", + "CMT_TOP_OCLKDIV_0", + "CMT_TOP_IMUX38_2", + "CMT_TOP_IMUX1_11", + "CMT_TOP_LOGIC_OUTS_L_B8_3", + "CMT_TOP_IMUX35_10", + "CMT_TOP_EE4A3_0", + "CMT_TOP_WW2A3_6", + "CMT_TOP_NW2A3_1", + "CMT_TOP_BYP3_5", + "CMT_TOP_BYP6_11", + "CMT_TOP_SW2A3_4", + "CMT_TOP_ER1BEG1_6", + "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "CMT_TOP_IMUX42_8", + "CMT_TOP_IMUX30_2", + "CMT_TOP_IMUX45_1", + "CMT_TOP_WW4B3_0", + "CMT_TOP_LOGIC_OUTS_L_B2_12", + "CMT_TOP_LH3_6", + "CMT_TOP_LH12_12", + "CMT_TOP_IMUX12_0", + "CMT_TOP_EE2BEG2_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", + "CMT_TOP_IMUX11_0", + "CMT_TOP_IMUX24_3", + "CMT_TOP_EE2BEG2_12", + "CMT_TOP_EE4B2_10", + "CMT_TOP_IMUX19_9", + "CMT_TOP_IMUX24_2", + "CMT_TOP_SE4BEG1_10", + "CMT_TOP_SE4BEG2_12", + "CMT_TOP_LH3_0", + "CMT_TOP_SW2A3_1", + "CMT_TOP_SE4BEG1_8", + "CMT_TOP_WW2A1_1", + "CMT_TOP_LH2_0", + "CMT_TOP_IMUX22_2", + "CMT_TOP_WR1END3_0", + "CMT_TOP_LH10_1", + "CMT_TOP_IMUX2_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", + "CMT_TOP_IMUX22_9", + "CMT_TOP_LOGIC_OUTS_L_B9_10", + "CMT_TOP_OCLKDIV_12", + "CMT_TOP_BLOCK_OUTS_L_B2_4", + "CMT_TOP_ICLK_10", + "CMT_TOP_SE2A2_9", + "CMT_TOP_LOGIC_OUTS_L_B3_4", + "CMT_TOP_LH2_11", + "CMT_TOP_SW4END1_2", + "CMT_TOP_LOGIC_OUTS_L_B10_9", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", + "CMT_TOP_WL1END1_4", + "CMT_TOP_IMUX37_9", + "CMT_TOP_EE2A2_10", + "CMT_TOP_WW4C3_9", + "CMT_TOP_WW2A1_4", + "CMT_TOP_EE4B0_11", + "CMT_TOP_BYP6_12", + "CMT_TOP_LOGIC_OUTS_L_B16_5", + "CMT_TOP_LOGIC_OUTS_L_B22_10", + "CMT_TOP_IMUX36_1", + "CMT_TOP_LH7_11", + "CMT_TOP_IMUX42_12", + "CMT_TOP_EE4A0_7", + "CMT_TOP_EE4A0_5", + "CMT_TOP_ER1BEG3_5", + "CMT_TOP_EE4B1_5", + "CMT_TOP_CLK1_12", + "CMT_TOP_LOGIC_OUTS_L_B22_0", + "CMT_TOP_IMUX19_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", + "CMT_TOP_ER1BEG3_6", + "CMT_TOP_NE4BEG3_9", + "CMT_TOP_WW4B2_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", + "CMT_TOP_IMUX17_3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", + "CMT_TOP_EE4A1_12", + "CMT_TOP_SE4BEG3_0", + "CMT_TOP_WW4A1_12", + "CMT_TOP_IMUX36_0", + "CMT_TOP_WW2A2_7", + "CMT_TOP_IMUX33_8", + "CMT_TOP_SW4END2_8", + "CMT_TOP_NE4C3_7", + "CMT_TOP_CLK1_9", + "CMT_TOP_WW4C2_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", + "CMT_PLL_PHASERREF_BELOW0", + "CMT_TOP_R_UPPER_T_FREQ_BB2", + "CMT_TOP_BLOCK_OUTS_L_B3_0", + "CMT_TOP_NW2A2_2", + "CMT_TOP_LH11_12", + "CMT_TOP_LOGIC_OUTS_L_B4_9", + "CMT_TOP_WW4END0_5", + "CMT_TOP_EL1BEG1_10", + "CMT_TOP_BYP3_2", + "CMT_TOP_NW4END2_1", + "CMT_TOP_IMUX15_0", + "CMT_TOP_IMUX45_3", + "CMT_TOP_NW4A1_10", + "CMT_TOP_IMUX33_10", + "CMT_TOP_SE4C0_6", + "CMT_TOP_MONITOR_P_1", + "CMT_TOP_LH1_9", + "CMT_TOP_IMUX15_2", + "CMT_TOP_LH10_4", + "CMT_TOP_SE4C2_7", + "CMT_TOP_WW4A0_12", + "CMT_TOP_IMUX32_3", + "CMT_TOP_IMUX16_9", + "CMT_TOP_IMUX3_11", + "CMT_TOP_BYP5_1", + "CMT_TOP_NE4C2_12", + "CMT_TOP_WW2A1_7", + "CMT_TOP_IMUX9_12", + "CMT_TOP_IMUX17_5", + "CMT_TOP_BYP2_2", + "CMT_PLL_PHASER_OUT_D_OCLK", + "CMT_TOP_LH1_6", + "CMT_TOP_SW4A1_11", + "CMT_TOP_IMUX40_12", + "CMT_TOP_IMUX12_6", + "CMT_TOP_WW4C0_8", + "CMT_TOP_SE4BEG1_2", + "CMT_TOP_NW4END0_9", + "CMT_TOP_IMUX13_10", + "CMT_TOP_IMUX30_3", + "CMT_TOP_NW2A1_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "CMT_TOP_SE2A3_3", + "CMT_TOP_BLOCK_OUTS_L_B2_8", + "CMT_TOP_MONITOR_P_10", + "CMT_TOP_EE4C0_1", + "CMT_TOP_CTRL0_9", + "CMT_TOP_NE4C2_0", + "CMT_TOP_IMUX1_7", + "CMT_TOP_NW4END1_3", + "CMT_TOP_IMUX21_5", + "CMT_TOP_ER1BEG0_12", + "CMT_TOP_ER1BEG3_1", + "CMT_TOP_WW4A2_7", + "CMT_TOP_LH12_3", + "PLL_CLK_FREQ_BB3_NS", + "CMT_TOP_EE2BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B4_3", + "CMT_TOP_SW4END3_7", + "CMT_TOP_LH12_8", + "CMT_TOP_WW4B2_1", + "CMT_TOP_IMUX40_7", + "CMT_TOP_BLOCK_OUTS_L_B3_3", + "CMT_TOP_NW4END1_12", + "CMT_TOP_SE4BEG0_4", + "CMT_TOP_CTRL0_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", + "CMT_TOP_NW4A3_7", + "CMT_TOP_NW4END3_0", + "CMT_TOP_NE2A1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_2", + "CMT_TOP_WW4A2_12", + "CMT_TOP_IMUX20_8", + "CMT_TOP_WW2END0_8", + "CMT_TOP_LH9_3", + "CMT_TOP_IMUX29_9", + "CMT_TOP_LH6_4", + "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "CMT_TOP_LOGIC_OUTS_L_B2_11", + "CMT_TOP_WW2A2_10", + "CMT_TOP_FAN2_12", + "CMT_TOP_MONITOR_P_3", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "CMT_TOP_NE4C3_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", + "CMT_TOP_BYP6_5", + "CMT_TOP_EL1BEG2_0", + "CMT_TOP_WL1END0_6", + "CMT_TOP_EE4BEG1_0", + "CMT_TOP_LOGIC_OUTS_L_B1_8", + "CMT_TOP_IMUX15_6", + "PLL_CLK_FREQ_BB_BUFOUT_NS2", + "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT", + "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "CMT_TOP_ICLK_2", + "CMT_TOP_LOGIC_OUTS_L_B21_4", + "CMT_TOP_ICLKDIV_11", + "CMT_TOP_IMUX36_2", + "CMT_TOP_FAN1_3", + "CMT_TOP_LH9_0", + "CMT_TOP_WL1END0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_5", + "CMT_TOP_WR1END3_6", + "CMT_TOP_R_UPPER_T_FREQ_BB3", + "CMT_PHASER_D_ICLK_TOIOI", + "CMT_TOP_NE2A3_3", + "CMT_TOP_SW4A2_10", + "CMT_TOP_WR1END2_10", + "CMT_TOP_IMUX29_8", + "CMT_TOP_IMUX26_6", + "CMT_TOP_SE4C0_12", + "CMT_TOP_FAN7_11", + "CMT_TOP_LOGIC_OUTS_L_B18_5", + "CMT_TOP_LOGIC_OUTS_L_B10_4", + "CMT_TOP_NE4BEG0_7", + "CMT_TOP_LOGIC_OUTS_L_B9_9", + "CMT_TOP_EE2BEG2_7", + "CMT_TOP_IMUX29_0", + "CMT_TOP_WR1END2_0", + "CMT_TOP_SW2A3_6", + "CMT_TOP_SE2A2_11", + "CMT_TOP_IMUX43_9", + "CMT_TOP_IMUX8_10", + "CMT_TOP_BYP3_3", + "CMT_TOP_WW2A2_3", + "CMT_TOP_BYP3_11", + "CMT_TOP_IMUX44_0", + "CMT_TOP_WW4C1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", + "CMT_TOP_IMUX15_12", + "CMT_TOP_EE4A1_7", + "CMT_TOP_FAN0_1", + "CMT_TOP_WW2A1_3", + "CMT_TOP_IMUX39_5", + "CMT_TOP_LH1_0", + "CMT_TOP_IMUX28_5", + "CMT_TOP_LOGIC_OUTS_L_B21_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", + "CMT_TOP_NE2A1_7", + "CMT_TOP_IMUX41_10", + "CMT_TOP_WR1END3_5", + "CMT_TOP_IMUX37_10", + "CMT_TOP_IMUX23_3", + "CMT_TOP_WW4A1_8", + "CMT_TOP_OCLKDIV_3", + "CMT_TOP_BYP7_7", + "CMT_TOP_IMUX15_5", + "CMT_TOP_LOGIC_OUTS_L_B5_8", + "CMT_TOP_SW4A0_7", + "CMT_TOP_LH12_4", + "CMT_TOP_WW4A2_11", + "CMT_TOP_LOGIC_OUTS_L_B17_7", + "CMT_PLL_PHASERREF_BELOW1", + "CMT_TOP_WW4A1_7", + "CMT_TOP_BYP0_12", + "CMT_TOP_WR1END2_7", + "CMT_TOP_IMUX5_3", + "CMT_TOP_LOGIC_OUTS_L_B13_0", + "CMT_TOP_WW4A3_2", + "CMT_TOP_IMUX18_5", + "CMT_TOP_LH7_7", + "CMT_TOP_WW4C0_7", + "CMT_TOP_LOGIC_OUTS_L_B10_8", + "CMT_TOP_IMUX39_11", + "CMT_TOP_BYP5_4", + "CMT_TOP_FAN4_3", + "CMT_TOP_EE2BEG0_4", + "CMT_TOP_FAN6_2", + "CMT_TOP_IMUX20_6", + "CMT_TOP_R_UPPER_T_CLKPLL1", + "CMT_TOP_LH4_5", + "CMT_TOP_IMUX22_4", + "CMT_TOP_SW2A0_12", + "CMT_TOP_WR1END2_4", + "CMT_TOP_LH9_1", + "CMT_TOP_LOGIC_OUTS_L_B19_2", + "CMT_TOP_SE4BEG0_3", + "CMT_TOP_EE4C3_0", + "CMT_TOP_BYP4_9", + "CMT_TOP_NW4END2_11", + "CMT_TOP_NE4C1_6", + "CMT_TOP_BYP2_0", + "CMT_TOP_WW2A0_10", + "CMT_TOP_IMUX7_11", + "CMT_TOP_WW4END0_0", + "CMT_TOP_NE4C0_12", + "CMT_TOP_EE2A2_7", + "CMT_TOP_LH2_1", + "CMT_TOP_MONITOR_N_12", + "CMT_TOP_NW4END3_12", + "CMT_TOP_WW4END3_7", + "CMT_TOP_EE4BEG2_5", + "CMT_TOP_WW4B2_12", + "CMT_TOP_EE2BEG0_9", + "CMT_TOP_WW4END2_9", + "CMT_TOP_LOGIC_OUTS_L_B5_10", + "CMT_TOP_IMUX4_12", + "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "CMT_TOP_LH11_5", + "CMT_TOP_R_UPPER_T_CLKPLL7", + "CMT_TOP_LOGIC_OUTS_L_B17_3", + "CMT_TOP_WW4C1_5", + "CMT_TOP_BYP5_8", + "CMT_TOP_WR1END2_11", + "CMT_TOP_EE4BEG2_7", + "CMT_TOP_BYP3_8", + "CMT_TOP_BLOCK_OUTS_L_B1_10", + "CMT_TOP_WL1END1_7", + "CMT_TOP_WL1END1_10", + "CMT_TOP_EE2BEG3_9", + "CMT_TOP_EE2BEG0_10", + "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "CMT_TOP_NW4A3_6", + "CMT_TOP_LH6_7", + "CMT_TOP_WW4B1_8", + "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT", + "CMT_TOP_WW4A3_0", + "CMT_TOP_FAN3_7", + "CMT_TOP_ER1BEG1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", + "CMT_TOP_SW2A2_10", + "CMT_TOP_ER1BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B15_8", + "CMT_TOP_IMUX25_5", + "CMT_TOP_CLK0_4", + "CMT_TOP_NW2A0_9", + "CMT_TOP_FAN5_3", + "CMT_TOP_EE4A1_4", + "CMT_TOP_IMUX31_6", + "CMT_TOP_NE2A1_9", + "CMT_TOP_LOGIC_OUTS_L_B5_11", + "CMT_TOP_IMUX38_7", + "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "CMT_TOP_LOGIC_OUTS_L_B13_7", + "CMT_TOP_FAN7_5", + "CMT_TOP_IMUX8_0", + "CMT_TOP_NE2A1_12", + "CMT_TOP_LOGIC_OUTS_L_B8_1", + "CMT_TOP_LOGIC_OUTS_L_B11_8", + "CMT_TOP_LOGIC_OUTS_L_B12_9", + "CMT_TOP_ICLK_7", + "CMT_TOP_IMUX15_3", + "CMT_TOP_FAN1_9", + "CMT_TOP_FAN2_3", + "CMT_TOP_EL1BEG1_5", + "CMT_TOP_NW2A1_6", + "CMT_TOP_SW4A0_4", + "CMT_TOP_LH11_9", + "CMT_TOP_OCLKDIV_5", + "CMT_TOP_IMUX8_3", + "CMT_TOP_WW4C3_12", + "CMT_TOP_LOGIC_OUTS_L_B7_11", + "CMT_TOP_NE4BEG1_7", + "CMT_TOP_EE4C2_11", + "CMT_TOP_NE4C3_1", + "CMT_TOP_WW2END3_11", + "CMT_TOP_CTRL0_3", + "CMT_TOP_FAN0_8", + "CMT_TOP_EE4C2_7", + "CMT_TOP_LOGIC_OUTS_L_B18_11", + "CMT_TOP_LOGIC_OUTS_L_B5_0", + "CMT_TOP_LOGIC_OUTS_L_B20_6", + "CMT_TOP_SW4A1_1", + "CMT_TOP_EL1BEG1_4", + "CMT_TOP_NW4END2_10", + "CMT_TOP_IMUX16_12", + "CMT_TOP_IMUX35_12", + "CMT_TOP_IMUX9_6", + "CMT_TOP_NW4A2_7", + "CMT_TOP_IMUX31_8", + "CMT_PHASER_D_ICLKDIV_TOIOI", + "CMT_TOP_ER1BEG0_4", + "CMT_TOP_IMUX28_7", + "CMT_TOP_LOGIC_OUTS_L_B12_3", + "CMT_TOP_LOGIC_OUTS_L_B18_6", + "CMT_TOP_IMUX41_1", + "CMT_TOP_SW2A3_7", + "CMT_TOP_LH4_9", + "CMT_TOP_EE2BEG0_3", + "CMT_TOP_NW2A3_9", + "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "CMT_TOP_EE4B3_4", + "CMT_TOP_SE4BEG1_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", + "CMT_TOP_IMUX24_4", + "CMT_TOP_LOGIC_OUTS_L_B20_0", + "CMT_TOP_FAN6_6", + "CMT_TOP_IMUX25_2", + "CMT_TOP_BYP2_3", + "CMT_TOP_EE4BEG1_2", + "CMT_TOP_FAN4_5", + "CMT_TOP_LOGIC_OUTS_L_B6_6", + "CMT_TOP_EE2BEG1_4", + "CMT_TOP_NW4A1_3", + "CMT_TOP_IMUX35_4", + "CMT_TOP_WW2END3_10", + "CMT_TOP_IMUX41_5", + "CMT_TOP_NW4A1_8", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", + "CMT_TOP_IMUX10_6", + "CMT_TOP_LOGIC_OUTS_L_B19_8", + "CMT_TOP_LH12_6", + "CMT_TOP_NE2A0_0", + "CMT_TOP_SW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B21_9", + "CMT_TOP_BYP6_10", + "CMT_TOP_SE4BEG3_6", + "CMT_TOP_IMUX12_7", + "CMT_TOP_NE4BEG1_6", + "CMT_TOP_BYP7_1", + "CMT_TOP_WW2A0_0", + "CMT_TOP_EE4BEG3_9", + "CMT_TOP_IMUX5_12", + "CMT_TOP_SW4A2_1", + "CMT_TOP_LH1_3", + "CMT_TOP_FAN0_5", + "CMT_TOP_EE2A1_8", + "CMT_TOP_WW4C3_7", + "CMT_TOP_LH2_3", + "CMT_TOP_FAN7_6", + "CMT_TOP_OCLK1X_90_8", + "CMT_TOP_NE2A0_12", + "CMT_TOP_ER1BEG0_10", + "CMT_TOP_NE4C1_7", + "CMT_TOP_LOGIC_OUTS_L_B13_1", + "CMT_TOP_NW4A3_0", + "CMT_TOP_EE4B1_10", + "CMT_TOP_LH9_12", + "CMT_TOP_WW4END2_1", + "CMT_TOP_BYP7_2", + "CMT_TOP_IMUX38_4", + "CMT_TOP_NE2A1_4", + "CMT_TOP_BLOCK_OUTS_L_B2_2", + "CMT_TOP_IMUX27_2", + "CMT_TOP_WW4C0_6", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "CMT_TOP_IMUX1_8", + "CMT_TOP_BYP6_3", + "CMT_TOP_NE2A2_5", + "CMT_TOP_NW4A0_3", + "CMT_TOP_LOGIC_OUTS_L_B4_12", + "CMT_TOP_ICLKDIV_8", + "CMT_TOP_EE4BEG3_12", + "CMT_TOP_NW2A3_6", + "CMT_TOP_WW4END3_5", + "CMT_TOP_IMUX34_12", + "CMT_TOP_WW4B1_5", + "CMT_TOP_EE4BEG3_7", + "CMT_TOP_IMUX23_10", + "CMT_TOP_IMUX17_0", + "CMT_TOP_CLK0_2", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "CMT_TOP_EE4B3_2", + "CMT_TOP_IMUX31_5", + "CMT_TOP_FAN0_0", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "CMT_TOP_EE4C3_2", + "CMT_TOP_SE4C0_9", + "CMT_TOP_IMUX46_3", + "CMT_TOP_IMUX43_7", + "CMT_TOP_IMUX40_1", + "CMT_TOP_EE2BEG1_7", + "CMT_TOP_NE4BEG0_2", + "CMT_TOP_EE4A3_9", + "CMT_TOP_WW4END3_6", + "CMT_TOP_FAN2_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", + "CMT_TOP_CLK0_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", + "CMT_TOP_R_UPPER_T_CLKPLL3", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", + "CMT_TOP_IMUX10_5", + "CMT_TOP_LOGIC_OUTS_L_B17_0", + "CMT_TOP_LOGIC_OUTS_L_B8_7", + "CMT_TOP_WW2A3_8", + "CMT_TOP_NE4C1_8", + "CMT_TOP_EE4A1_1", + "CMT_TOP_WW4A3_12", + "CMT_TOP_FAN0_3", + "CMT_TOP_WW4C0_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", + "CMT_TOP_BYP0_6", + "CMT_TOP_WW4C1_10", + "CMT_TOP_IMUX12_4", + "CMT_TOP_LH10_3", + "CMT_TOP_LH3_2", + "CMT_TOP_EL1BEG3_7", + "CMT_TOP_IMUX43_4", + "CMT_TOP_LH10_6", + "CMT_TOP_NE4C1_10", + "CMT_TOP_IMUX15_11", + "CMT_TOP_NE4C1_9", + "CMT_TOP_WW4B0_3", + "CMT_TOP_WW4C3_10", + "CMT_TOP_SE2A2_6", + "CMT_TOP_NW2A3_5", + "CMT_TOP_SE4C0_5", + "CMT_TOP_WW4A2_1", + "CMT_TOP_NW4END3_5", + "CMT_TOP_EE2BEG2_11", + "CMT_TOP_SW2A1_12", + "CMT_TOP_LOGIC_OUTS_L_B12_4", + "CMT_TOP_IMUX38_11", + "CMT_TOP_SW4END2_9", + "CMT_TOP_IMUX47_11", + "CMT_TOP_SW4END1_3", + "CMT_TOP_LOGIC_OUTS_L_B5_6", + "CMT_TOP_LOGIC_OUTS_L_B16_11", + "CMT_TOP_LH3_1", + "CMT_TOP_EE4C1_0", + "CMT_TOP_WW4END2_5", + "CMT_TOP_FAN0_6", + "CMT_TOP_EE2BEG2_8", + "CMT_TOP_IMUX42_11", + "CMT_TOP_SE2A0_3", + "CMT_PLL_PHASER_RDENABLE_TOFIFO", + "CMT_TOP_IMUX4_5", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", + "CMT_TOP_BYP4_0", + "CMT_TOP_EE4BEG0_8", + "CMT_TOP_NE4BEG2_2", + "CMT_TOP_IMUX35_0", + "CMT_TOP_LH4_4", + "CMT_TOP_LH3_9", + "CMT_TOP_EL1BEG1_1", + "CMT_TOP_NE2A0_9", + "CMT_TOP_EL1BEG2_9", + "CMT_TOP_WW4C1_2", + "CMT_TOP_IMUX37_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", + "CMT_TOP_EE4BEG2_6", + "CMT_TOP_WR1END1_0", + "CMT_TOP_ER1BEG0_8", + "CMT_TOP_IMUX22_5", + "PLL_CLK_FREQ_BB1_NS", + "CMT_TOP_OCLK_3", + "CMT_TOP_IMUX23_5", + "CMT_TOP_SW4END2_4", + "CMT_TOP_IMUX37_12", + "CMT_TOP_EE4A1_8", + "CMT_TOP_IMUX19_11", + "CMT_TOP_LOGIC_OUTS_L_B21_8", + "CMT_TOP_WW4A0_0", + "CMT_TOP_LOGIC_OUTS_L_B6_1", + "CMT_TOP_WW2END0_2", + "CMT_TOP_LOGIC_OUTS_L_B11_5", + "CMT_TOP_SE2A1_6", + "CMT_TOP_CTRL0_1", + "CMT_TOP_NE2A1_10", + "CMT_TOP_WW2END0_9", + "CMT_TOP_EE4BEG2_9", + "CMT_TOP_WW4B0_0", + "CMT_TOP_LH7_12", + "CMT_TOP_IMUX6_5", + "CMT_TOP_BLOCK_OUTS_L_B1_8", + "CMT_TOP_WW4B0_4", + "CMT_TOP_IMUX10_9", + "CMT_TOP_LOGIC_OUTS_L_B1_9", + "CMT_TOP_IMUX45_0", + "CMT_TOP_IMUX45_10", + "CMT_TOP_IMUX39_1", + "CMT_TOP_WL1END1_8", + "CMT_TOP_EE2A3_6", + "CMT_TOP_WW2END3_8", + "CMT_TOP_R_UPPER_T_FREQ_BB1", + "CMT_TOP_IMUX9_5", + "CMT_TOP_BYP4_10", + "CMT_TOP_WW4C2_12", + "CMT_TOP_IMUX17_9", + "CMT_TOP_BLOCK_OUTS_L_B1_11", + "CMT_TOP_IMUX23_4", + "CMT_TOP_WW4A1_3", + "CMT_TOP_LOGIC_OUTS_L_B8_8", + "CMT_TOP_FAN3_10", + "CMT_TOP_EE4B0_2", + "CMT_TOP_LOGIC_OUTS_L_B23_3", + "CMT_TOP_WL1END0_2", + "CMT_TOP_IMUX42_9", + "CMT_TOP_IMUX38_12", + "CMT_TOP_EE2A2_6", + "CMT_TOP_IMUX25_3", + "CMT_TOP_BLOCK_OUTS_L_B1_1", + "CMT_TOP_BLOCK_OUTS_L_B0_7", + "CMT_PLL_DQS_TO_PHASER_D", + "CMT_TOP_LOGIC_OUTS_L_B3_9", + "CMT_TOP_NW4A3_4", + "CMT_TOP_WR1END1_12", + "CMT_TOP_IMUX34_4", + "CMT_TOP_LH7_2", + "CMT_TOP_LH6_1", + "CMT_TOP_NW4END2_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", + "CMT_TOP_LH1_2", + "CMT_TOP_LOGIC_OUTS_L_B19_4", + "CMT_TOP_IMUX13_2", + "CMT_TOP_WW4A0_8", + "CMT_TOP_FAN6_8", + "CMT_TOP_IMUX17_7", + "CMT_TOP_EL1BEG1_9", + "CMT_TOP_NW4A0_2", + "CMT_TOP_BYP6_6", + "CMT_TOP_LOGIC_OUTS_L_B15_2", + "CMT_TOP_SW4END1_7", + "CMT_TOP_IMUX6_2", + "CMT_TOP_IMUX46_2", + "CMT_TOP_LOGIC_OUTS_L_B23_7", + "CMT_TOP_NW4END0_6", + "CMT_TOP_WR1END3_2", + "CMT_TOP_BYP1_2", + "CMT_TOP_BLOCK_OUTS_L_B1_4", + "CMT_TOP_NE2A3_7", + "CMT_TOP_IMUX3_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", + "CMT_TOP_LOGIC_OUTS_L_B17_10", + "CMT_TOP_BYP2_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", + "CMT_TOP_IMUX14_8", + "CMT_TOP_BYP0_3", + "CMT_TOP_NE4C0_0", + "CMT_TOP_NE4C2_10", + "CMT_TOP_SE2A2_12", + "CMT_TOP_LOGIC_OUTS_L_B4_4", + "CMT_TOP_R_UPPER_T_CLKFBIN", + "CMT_TOP_BLOCK_OUTS_L_B2_5", + "CMT_TOP_LOGIC_OUTS_L_B20_3", + "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "CMT_TOP_EE4B1_4", + "CMT_TOP_LH6_11", + "CMT_TOP_FAN5_10", + "CMT_TOP_WW4END2_4", + "CMT_TOP_EE4C3_12", + "CMT_TOP_NW2A3_11", + "CMT_TOP_BLOCK_OUTS_L_B3_7", + "CMT_TOP_LOGIC_OUTS_L_B14_9", + "CMT_TOP_LOGIC_OUTS_L_B2_6", + "CMT_TOP_NW2A2_8", + "CMT_TOP_IMUX19_4", + "CMT_TOP_WW2END2_9", + "CMT_TOP_SW2A1_3", + "CMT_TOP_IMUX30_4", + "CMT_TOP_SW4END0_3", + "CMT_TOP_IMUX28_1", + "CMT_TOP_NW4A0_0", + "CMT_TOP_EE4BEG1_11", + "CMT_TOP_LOGIC_OUTS_L_B11_2", + "CMT_TOP_LH3_7", + "CMT_TOP_LH4_8", + "CMT_TOP_LOGIC_OUTS_L_B23_4", + "CMT_TOP_IMUX20_9", + "CMT_TOP_SE4C3_9", + "CMT_TOP_IMUX16_4", + "CMT_TOP_EE2A3_7", + "CMT_TOP_SE4C3_11", + "CMT_TOP_ICLK_9", + "CMT_TOP_LOGIC_OUTS_L_B13_11", + "CMT_TOP_LOGIC_OUTS_L_B4_11", + "CMT_TOP_WW4A1_10", + "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "CMT_TOP_WW2END0_0", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", + "CMT_TOP_NW4A2_12", + "CMT_TOP_ER1BEG3_10", + "CMT_TOP_WW4C3_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", + "CMT_TOP_BYP3_6", + "CMT_TOP_NE4BEG2_10", + "CMT_TOP_WW2A2_8", + "CMT_TOP_NE4BEG3_2", + "CMT_TOP_WW4B3_7", + "PLL_CLK_FREQ_BB_BUFOUT_NS0", + "CMT_TOP_SW4END3_4", + "CMT_TOP_EE4C1_7", + "CMT_TOP_EE4B0_7", + "CMT_TOP_IMUX20_12", + "CMT_TOP_BYP0_8", + "CMT_TOP_LOGIC_OUTS_L_B7_1", + "CMT_TOP_WW4END1_7", + "CMT_TOP_WW4C0_10", + "CMT_TOP_WW4C2_6", + "CMT_TOP_LOGIC_OUTS_L_B0_1", + "CMT_TOP_SE4BEG0_12", + "CMT_TOP_EE4BEG1_9", + "CMT_TOP_FAN6_4", + "CMT_TOP_IMUX5_0", + "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "CMT_TOP_WW4B3_10", + "CMT_TOP_SE4BEG2_4", + "CMT_TOP_WW2END3_9", + "CMT_TOP_SW4END1_10", + "CMT_TOP_WW4B0_7", + "CMT_TOP_BYP3_7", + "CMT_TOP_EE2A3_11", + "CMT_TOP_LH6_5", + "CMT_TOP_IMUX28_2", + "CMT_TOP_EE4B0_9", + "CMT_TOP_BLOCK_OUTS_L_B2_11", + "CMT_TOP_LOGIC_OUTS_L_B10_5", + "CMT_TOP_LOGIC_OUTS_L_B2_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", + "CMT_TOP_WW4A3_5", + "CMT_TOP_EL1BEG0_12", + "CMT_TOP_LOGIC_OUTS_L_B21_3", + "CMT_TOP_BLOCK_OUTS_L_B3_1", + "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "CMT_TOP_EE2BEG2_0", + "CMT_TOP_WW4A0_11", + "CMT_TOP_WL1END0_3", + "CMT_TOP_WW4C0_2", + "CMT_TOP_IMUX0_7", + "CMT_TOP_WW4B1_0", + "CMT_TOP_LOGIC_OUTS_L_B12_2", + "CMT_TOP_LOGIC_OUTS_L_B16_1", + "CMT_TOP_NE4BEG3_3", + "CMT_TOP_SW4END0_8", + "CMT_TOP_WW4C2_10", + "CMT_TOP_IMUX8_1", + "CMT_TOP_EE4BEG3_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", + "CMT_TOP_IMUX34_6", + "CMT_TOP_IMUX32_11", + "CMT_TOP_NE2A3_1", + "CMT_TOP_BLOCK_OUTS_L_B0_8", + "CMT_TOP_EE4C1_12", + "CMT_TOP_EE4B0_3", + "CMT_TOP_SE2A2_7", + "CMT_TOP_SW2A3_11", + "CMT_TOP_BYP2_8", + "CMT_TOP_LOGIC_OUTS_L_B11_0", + "CMT_PLL_PHASERD_CTSBUS1", + "CMT_TOP_IMUX46_10", + "CMT_TOP_IMUX4_4", + "CMT_TOP_NE2A3_11", + "CMT_TOP_ER1BEG2_5", + "CMT_TOP_SW2A3_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", + "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "CMT_TOP_WW4C0_5", + "CMT_TOP_NE4BEG2_9", + "CMT_TOP_BYP4_4", + "CMT_TOP_NW4A2_9", + "CMT_TOP_WR1END2_1", + "CMT_TOP_EE2BEG0_7", + "CMT_TOP_IMUX16_1", + "CMT_TOP_NW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B0_11", + "CMT_TOP_FAN2_6", + "CMT_TOP_WR1END3_7", + "CMT_TOP_IMUX23_12", + "CMT_TOP_IMUX38_9", + "CMT_TOP_IMUX36_12", + "CMT_TOP_IMUX28_0", + "CMT_TOP_NE4C0_8", + "CMT_TOP_LOGIC_OUTS_L_B17_8", + "CMT_TOP_LOGIC_OUTS_L_B21_5", + "CMT_TOP_FAN5_7", + "CMT_TOP_BYP7_10", + "CMT_TOP_IMUX15_7", + "CMT_TOP_IMUX13_12", + "CMT_TOP_IMUX30_9", + "CMT_TOP_LH8_5", + "CMT_TOP_EE4A3_5", + "CMT_TOP_NE4C0_5", + "CMT_TOP_NE4BEG0_6", + "CMT_TOP_EE4BEG1_8", + "CMT_TOP_IMUX25_0", + "CMT_TOP_IMUX31_10", + "CMT_TOP_EE4BEG0_10", + "CMT_TOP_SW4A0_12", + "CMT_TOP_LOGIC_OUTS_L_B17_5", + "CMT_TOP_IMUX34_2", + "CMT_TOP_LH10_2", + "CMT_TOP_SW4A2_12", + "CMT_TOP_R_UPPER_T_CLKPLL5", + "CMT_TOP_LH12_0", + "CMT_TOP_FAN4_0", + "CMT_TOP_IMUX41_9", + "CMT_TOP_LOGIC_OUTS_L_B16_0", + "CMT_TOP_NW4A0_8", + "CMT_TOP_WW4A2_10", + "CMT_TOP_BYP3_0", + "CMT_TOP_IMUX2_1", + "CMT_TOP_IMUX22_1", + "CMT_TOP_LOGIC_OUTS_L_B14_7", + "CMT_TOP_BLOCK_OUTS_L_B1_12", + "CMT_TOP_EE2A3_5", + "CMT_TOP_IMUX4_7", + "CMT_TOP_SE2A2_0", + "CMT_TOP_LH2_4", + "CMT_TOP_IMUX1_0", + "CMT_TOP_SW4A3_6", + "CMT_TOP_NW4END1_5", + "CMT_TOP_NW2A2_1", + "CMT_TOP_WR1END3_1", + "CMT_TOP_BYP1_0", + "CMT_TOP_EE2BEG1_12", + "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "CMT_TOP_R_UPPER_T_CLKPLL4", + "CMT_TOP_WW2A0_6", + "CMT_TOP_SE2A3_0", + "CMT_TOP_IMUX35_9", + "CMT_TOP_SW4END2_5", + "CMT_TOP_SE4C3_5", + "CMT_TOP_LH4_1", + "CMT_TOP_NW4A0_9", + "CMT_TOP_SW4A1_6", + "CMT_TOP_SW2A2_0", + "CMT_TOP_WW4B0_11", + "CMT_TOP_SE4C3_10", + "CMT_TOP_LOGIC_OUTS_L_B11_12", + "CMT_TOP_SW4END0_7", + "CMT_TOP_EE4BEG1_12", + "CMT_TOP_IMUX13_5", + "CMT_TOP_LOGIC_OUTS_L_B16_10", + "CMT_TOP_NE4C0_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", + "CMT_TOP_SW4END3_5", + "CMT_TOP_EE4A2_4", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", + "CMT_TOP_LOGIC_OUTS_L_B0_2", + "CMT_TOP_EL1BEG2_6", + "CMT_TOP_LH2_8", + "CMT_TOP_SE2A3_1", + "CMT_TOP_IMUX2_6", + "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "CMT_TOP_IMUX3_0", + "CMT_TOP_EL1BEG2_8", + "CMT_TOP_EE4C2_4", + "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "CMT_TOP_NE4BEG1_5", + "CMT_PLL_PHASERD_DQSBUS0", + "CMT_TOP_EE2BEG3_4", + "CMT_TOP_ER1BEG0_6", + "CMT_TOP_EE2A3_2", + "CMT_TOP_IMUX14_10", + "CMT_TOP_IMUX23_8", + "CMT_TOP_WW4A3_8", + "CMT_TOP_IMUX40_6", + "CMT_TOP_IMUX24_12", + "CMT_TOP_LH10_9", + "CMT_TOP_BYP3_12", + "CMT_TOP_FAN1_0", + "CMT_TOP_LH4_10", + "CMT_TOP_IMUX0_2", + "CMT_TOP_EL1BEG3_12", + "CMT_TOP_EE4BEG0_7", + "CMT_TOP_LH1_12", + "CMT_TOP_LH5_3", + "CMT_TOP_ICLKDIV_6", + "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "CMT_TOP_NW2A3_3", + "CMT_TOP_NW2A0_3", + "CMT_TOP_SW4A0_1", + "CMT_TOP_LOGIC_OUTS_L_B14_10", + "CMT_TOP_IMUX18_1", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", + "CMT_PLL_PHASERREF1", + "CMT_TOP_EL1BEG0_6", + "CMT_TOP_SW4END3_10", + "CMT_TOP_FAN2_10", + "CMT_TOP_LOGIC_OUTS_L_B7_0", + "CMT_TOP_LOGIC_OUTS_L_B3_6", + "CMT_TOP_IMUX15_8", + "CMT_TOP_LOGIC_OUTS_L_B9_5", + "CMT_TOP_NE4BEG2_7", + "CMT_TOP_WR1END1_1", + "CMT_TOP_SW2A2_7", + "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "CMT_TOP_ICLK_5", + "CMT_TOP_SW2A0_7", + "CMT_TOP_FAN6_5", + "CMT_TOP_ER1BEG0_7", + "CMT_TOP_WW2A1_2", + "CMT_TOP_NW4A2_0", + "CMT_TOP_LOGIC_OUTS_L_B12_10", + "CMT_TOP_FAN4_1", + "CMT_TOP_LOGIC_OUTS_L_B2_0", + "CMT_TOP_LH9_6", + "CMT_TOP_SE4BEG2_3", + "CMT_TOP_SE4C0_11", + "CMT_TOP_WW2END0_6", + "CMT_TOP_CTRL1_0", + "CMT_TOP_SE4BEG3_3", + "CMT_TOP_WW4B1_2", + "CMT_TOP_BLOCK_OUTS_L_B2_10", + "CMT_TOP_FAN6_3", + "CMT_TOP_WL1END1_11", + "CMT_TOP_SW4A2_3", + "CMT_TOP_LOGIC_OUTS_L_B9_3", + "CMT_TOP_NW2A3_10", + "CMT_TOP_LH11_2", + "CMT_TOP_LOGIC_OUTS_L_B10_10", + "CMT_TOP_CLK0_11", + "CMT_TOP_SE4C2_6", + "CMT_TOP_IMUX39_12", + "CMT_TOP_FAN5_11", + "CMT_TOP_SW4END1_6", + "CMT_TOP_IMUX2_2", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", + "CMT_TOP_OCLKDIV_4", + "CMT_TOP_WW2END0_5", + "CMT_TOP_LH6_0", + "CMT_TOP_LOGIC_OUTS_L_B15_3", + "CMT_TOP_IMUX20_7", + "CMT_TOP_IMUX29_3", + "CMT_TOP_WL1END1_6", + "CMT_TOP_NW4A2_5", + "CMT_TOP_IMUX6_9", + "CMT_TOP_BYP3_10", + "CMT_TOP_IMUX33_1", + "CMT_TOP_IMUX19_5", + "CMT_TOP_IMUX9_2", + "CMT_TOP_NE4BEG3_7", + "CMT_TOP_NW2A0_6", + "CMT_TOP_EE4A1_9", + "CMT_TOP_EE4B3_9", + "CMT_TOP_EE4BEG0_3", + "CMT_TOP_LOGIC_OUTS_L_B0_5", + "CMT_TOP_NE2A3_4", + "CMT_TOP_EE2A0_11", + "CMT_TOP_IMUX40_3", + "CMT_TOP_SW2A3_12", + "CMT_TOP_LOGIC_OUTS_L_B4_6", + "CMT_TOP_LOGIC_OUTS_L_B6_3", + "CMT_TOP_EL1BEG2_1", + "CMT_TOP_ICLK_3", + "CMT_TOP_SW4END0_6", + "CMT_TOP_EL1BEG1_7", + "CMT_TOP_SW4END3_6", + "CMT_TOP_IMUX41_6", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", + "CMT_TOP_EE4A0_11", + "CMT_TOP_ER1BEG1_9", + "CMT_TOP_WW4A0_5", + "CMT_TOP_MONITOR_P_5", + "CMT_TOP_IMUX46_11", + "CMT_TOP_SW4A2_6", + "CMT_TOP_EE4C0_2", + "CMT_TOP_OCLK1X_90_0", + "CMT_TOP_LOGIC_OUTS_L_B1_11", + "CMT_TOP_IMUX11_3", + "CMT_TOP_IMUX17_12", + "CMT_TOP_LOGIC_OUTS_L_B22_2", + "CMT_TOP_EE2BEG0_1", + "CMT_TOP_LH5_8", + "CMT_PLL_PHYCTRL_SYNC_BB_DN", + "CMT_TOP_WW4A2_8", + "CMT_TOP_WW4A3_4", + "CMT_TOP_LH11_4", + "CMT_TOP_IMUX34_0", + "CMT_TOP_BYP1_6", + "CMT_TOP_WW4B0_1", + "CMT_TOP_WL1END0_12", + "CMT_TOP_IMUX2_4", + "CMT_TOP_SW4A1_8", + "CMT_TOP_LOGIC_OUTS_L_B9_2", + "CMT_TOP_MONITOR_P_8", + "CMT_TOP_WL1END3_10", + "CMT_TOP_WR1END1_4", + "CMT_TOP_IMUX29_7", + "CMT_TOP_IMUX33_3", + "CMT_TOP_SW4END3_12", + "CMT_TOP_SW2A2_3", + "CMT_TOP_FAN6_12", + "CMT_TOP_IMUX44_8", + "CMT_TOP_IMUX32_7", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", + "CMT_TOP_IMUX12_1", + "CMT_TOP_SW2A3_0", + "CMT_TOP_LOGIC_OUTS_L_B7_9", + "CMT_TOP_WW4A2_2", + "CMT_TOP_IMUX32_1", + "CMT_TOP_LH8_1", + "CMT_TOP_SE2A2_1", + "CMT_TOP_NW2A3_12", + "CMT_TOP_IMUX31_12", + "CMT_TOP_WW4C3_3", + "CMT_TOP_SE4C3_1", + "CMT_TOP_CTRL0_7", + "CMT_TOP_IMUX26_3", + "CMT_TOP_BLOCK_OUTS_L_B0_6", + "CMT_TOP_IMUX24_6", + "CMT_TOP_EE4BEG2_3", + "CMT_TOP_EE4BEG2_8", + "CMT_TOP_SE4BEG0_11", + "CMT_TOP_NE2A2_10", + "CMT_TOP_BLOCK_OUTS_L_B0_10", + "CMT_TOP_LOGIC_OUTS_L_B7_12", + "CMT_TOP_IMUX17_1", + "CMT_TOP_EE4C3_7", + "CMT_TOP_IMUX15_1", + "CMT_TOP_IMUX32_2", + "CMT_TOP_LOGIC_OUTS_L_B4_1", + "CMT_TOP_ICLK_6", + "CMT_TOP_SE2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B4_0", + "CMT_TOP_ER1BEG2_0", + "CMT_TOP_SE2A3_7", + "CMT_TOP_BYP6_9", + "CMT_TOP_EE4B2_3", + "CMT_TOP_SE4BEG0_6", + "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "CMT_TOP_WW2A0_8", + "CMT_TOP_EE4C1_11", + "CMT_TOP_IMUX0_3", + "CMT_TOP_IMUX30_10", + "CMT_TOP_WW4END0_9", + "CMT_TOP_SW4END0_5", + "CMT_TOP_IMUX27_10", + "CMT_TOP_SE4BEG1_9", + "CMT_TOP_SW4A2_2", + "CMT_TOP_LOGIC_OUTS_L_B11_6", + "CMT_PLL_PHASER_IN_D_ICLK", + "CMT_TOP_CTRL1_1", + "CMT_TOP_SE4BEG0_8", + "CMT_TOP_IMUX29_12", + "CMT_TOP_WR1END2_8", + "CMT_TOP_LOGIC_OUTS_L_B18_3", + "CMT_TOP_IMUX3_5", + "CMT_TOP_IMUX12_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", + "CMT_TOP_WW4A3_10", + "CMT_TOP_FAN3_6", + "CMT_TOP_LH5_4", + "CMT_TOP_LOGIC_OUTS_L_B21_12", + "CMT_TOP_NE4C1_12", + "CMT_TOP_ICLKDIV_9", + "CMT_TOP_WW2END1_12", + "CMT_TOP_IMUX47_3", + "CMT_TOP_SW4A3_5", + "CMT_TOP_NE4BEG0_0", + "CMT_TOP_EE2A1_4", + "CMT_TOP_NW4END1_4", + "CMT_TOP_IMUX25_1", + "CMT_TOP_LH5_11", + "CMT_TOP_FAN1_10", + "CMT_TOP_LH3_12", + "CMT_TOP_NW4END0_11", + "CMT_TOP_EE4C0_11", + "CMT_TOP_BLOCK_OUTS_L_B0_12", + "CMT_TOP_IMUX25_8", + "CMT_TOP_EE4A1_3", + "CMT_TOP_NW2A3_7", + "CMT_TOP_IMUX30_11", + "CMT_TOP_LOGIC_OUTS_L_B16_8", + "CMT_TOP_EE4BEG3_0", + "CMT_TOP_LOGIC_OUTS_L_B11_10", + "CMT_TOP_LOGIC_OUTS_L_B8_6", + "CMT_TOP_EE2A1_2", + "CMT_TOP_SE4C2_2", + "CMT_TOP_WW4C0_12", + "CMT_TOP_WW4C2_8", + "CMT_TOP_MONITOR_N_10", + "CMT_TOP_LOGIC_OUTS_L_B12_1", + "CMT_TOP_IMUX26_11", + "CMT_TOP_NE2A2_1", + "CMT_TOP_CTRL1_8", + "CMT_TOP_SW4A3_0", + "CMT_TOP_NW4END3_3", + "CMT_TOP_WW4B2_2", + "CMT_TOP_IMUX18_3", + "CMT_TOP_IMUX16_11", + "CMT_TOP_WW4A0_3", + "CMT_TOP_LH5_1", + "CMT_TOP_WL1END0_4", + "CMT_TOP_NW4A3_12", + "CMT_TOP_IMUX44_7", + "CMT_TOP_SW2A3_3", + "CMT_TOP_SE2A2_3", + "CMT_TOP_FAN6_10", + "CMT_TOP_SE4C2_4", + "CMT_TOP_EE4C2_0", + "CMT_TOP_NE4C1_3", + "CMT_TOP_R_UPPER_T_CLKPLL6", + "CMT_TOP_BYP3_1", + "CMT_TOP_IMUX18_8", + "CMT_TOP_BYP3_4", + "CMT_TOP_SW4A3_7", + "CMT_TOP_CLK1_5", + "CMT_TOP_SW2A0_4", + "CMT_TOP_IMUX0_10", + "CMT_TOP_LOGIC_OUTS_L_B14_3", + "CMT_TOP_SE4BEG0_9", + "CMT_TOP_SW2A2_2", + "CMT_TOP_LOGIC_OUTS_L_B19_1", + "CMT_TOP_IMUX13_7", + "CMT_TOP_NE4C2_2", + "PLL_CLK_FREQ_BB2_NS", + "CMT_TOP_IMUX10_4", + "CMT_TOP_EE4A1_11", + "CMT_TOP_EE2A0_6", + "CMT_TOP_NW4END1_0", + "CMT_TOP_LH5_10", + "CMT_TOP_IMUX46_7", + "CMT_TOP_SW4END3_11", + "CMT_TOP_LOGIC_OUTS_L_B15_4", + "CMT_TOP_SE4BEG3_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", + "CMT_TOP_WW4C2_2", + "CMT_TOP_EE2A2_8", + "CMT_TOP_OCLK_9", + "CMT_TOP_NW2A2_11", + "CMT_TOP_LOGIC_OUTS_L_B12_0", + "CMT_TOP_WW4END3_9", + "CMT_TOP_EE4C3_1", + "CMT_TOP_IMUX14_11", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", + "CMT_TOP_WW4C1_9", + "CMT_TOP_IMUX0_9", + "CMT_TOP_SE4BEG2_0", + "CMT_TOP_WL1END3_9", + "CMT_TOP_EE4BEG2_4", + "CMT_TOP_IMUX13_6", + "CMT_TOP_EE4A2_6", + "CMT_TOP_IMUX20_0", + "CMT_TOP_WW4B2_9", + "CMT_TOP_LOGIC_OUTS_L_B13_4", + "CMT_TOP_WR1END2_2", + "CMT_TOP_WW2A0_1", + "CMT_TOP_MONITOR_N_11", + "CMT_TOP_FAN7_9", + "CMT_TOP_EE2BEG0_5", + "CMT_TOP_LOGIC_OUTS_L_B1_1", + "CMT_TOP_WW4B0_8", + "CMT_TOP_FAN7_12", + "CMT_TOP_LOGIC_OUTS_L_B13_8", + "CMT_TOP_LH5_7", + "CMT_TOP_IMUX21_9", + "CMT_TOP_IMUX35_1", + "CMT_TOP_IMUX47_12", + "CMT_TOP_WW2END3_0", + "CMT_TOP_WW4B3_8", + "CMT_TOP_WL1END1_3", + "CMT_TOP_LOGIC_OUTS_L_B23_0", + "CMT_TOP_NW2A3_8", + "CMT_TOP_SE2A3_4", + "CMT_TOP_SW4END3_9", + "CMT_TOP_NE4C2_6", + "CMT_TOP_NE4C0_10", + "CMT_TOP_IMUX26_5", + "CMT_TOP_BYP4_11", + "CMT_TOP_IMUX25_6", + "CMT_TOP_BYP0_2", + "CMT_TOP_BYP6_7", + "CMT_TOP_ICLK_12", + "CMT_TOP_EL1BEG0_0", + "CMT_TOP_LOGIC_OUTS_L_B0_0", + "CMT_TOP_NE2A1_8", + "CMT_TOP_WW4A0_10", + "CMT_TOP_BYP4_12", + "CMT_TOP_EL1BEG0_8", + "CMT_TOP_IMUX40_5", + "CMT_TOP_EE2A2_5", + "CMT_TOP_WW4B2_0", + "CMT_TOP_SE4BEG3_12", + "CMT_TOP_LOGIC_OUTS_L_B8_2", + "CMT_TOP_WW2A0_12", + "CMT_TOP_LOGIC_OUTS_L_B17_2", + "CMT_TOP_WL1END3_0", + "CMT_TOP_WW4END0_3", + "CMT_TOP_IMUX12_10", + "CMT_TOP_NW4END0_1", + "CMT_TOP_LH6_6", + "CMT_TOP_NE4C3_5", + "CMT_TOP_FAN3_12", + "CMT_TOP_NW4END0_8", + "CMT_TOP_IMUX39_0", + "CMT_TOP_WW4END2_0", + "CMT_TOP_WW4B3_4", + "CMT_TOP_LOGIC_OUTS_L_B4_10", + "CMT_TOP_IMUX9_0", + "CMT_TOP_FAN2_0", + "CMT_TOP_IMUX29_11", + "CMT_TOP_IMUX30_5", + "CMT_TOP_IMUX8_9", + "CMT_TOP_EE2BEG3_2", + "CMT_TOP_NW4END2_5", + "CMT_TOP_NE4C0_7", + "CMT_TOP_WW2END2_4", + "CMT_TOP_LOGIC_OUTS_L_B12_11", + "CMT_TOP_WL1END3_1", + "CMT_TOP_BLOCK_OUTS_L_B3_6", + "CMT_TOP_SW4A3_4", + "CMT_TOP_LOGIC_OUTS_L_B19_3", + "CMT_TOP_NW2A0_2", + "CMT_TOP_IMUX17_6", + "CMT_TOP_IMUX7_0", + "CMT_TOP_MONITOR_P_6", + "CMT_TOP_SE2A1_2", + "CMT_TOP_IMUX20_2", + "CMT_TOP_LH8_7", + "CMT_TOP_IMUX4_11", + "CMT_TOP_LOGIC_OUTS_L_B9_7", + "CMT_TOP_WW4A2_5", + "CMT_TOP_NE4C1_11", + "CMT_TOP_LOGIC_OUTS_L_B20_1", + "CMT_TOP_OCLK_6", + "CMT_TOP_CTRL1_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", + "CMT_TOP_IMUX18_10", + "CMT_TOP_BYP4_7", + "CMT_TOP_BYP0_5", + "CMT_TOP_SE2A2_4", + "CMT_TOP_SE4C2_1", + "CMT_TOP_WW2A1_5", + "CMT_TOP_LOGIC_OUTS_L_B0_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", + "CMT_TOP_LOGIC_OUTS_L_B3_3", + "CMT_TOP_SE2A0_1", + "CMT_TOP_NW4END3_4", + "CMT_TOP_IMUX40_11", + "CMT_TOP_LH9_8", + "CMT_TOP_LOGIC_OUTS_L_B16_12", + "CMT_TOP_LH9_11", + "CMT_TOP_NE2A2_0", + "CMT_TOP_LOGIC_OUTS_L_B5_4", + "CMT_TOP_LOGIC_OUTS_L_B6_11", + "CMT_TOP_WW4C1_6", + "CMT_TOP_IMUX28_11", + "CMT_TOP_LOGIC_OUTS_L_B6_12", + "CMT_TOP_EE4BEG3_2", + "CMT_TOP_LH3_10", + "CMT_TOP_IMUX42_7", + "CMT_TOP_IMUX5_10", + "CMT_TOP_WL1END3_8", + "CMT_TOP_IMUX17_2", + "CMT_TOP_EE2A3_1", + "CMT_TOP_IMUX2_10", + "CMT_TOP_SE2A0_6", + "CMT_TOP_NE2A2_4", + "CMT_TOP_LOGIC_OUTS_L_B20_5", + "CMT_TOP_SE4C1_6", + "CMT_TOP_LOGIC_OUTS_L_B22_6", + "CMT_TOP_MONITOR_P_2", + "CMT_TOP_IMUX41_4", + "CMT_TOP_WL1END0_1", + "CMT_TOP_IMUX0_12", + "CMT_TOP_NW4END2_4", + "CMT_TOP_FAN5_1", + "CMT_TOP_WW4A2_0", + "CMT_TOP_IMUX20_10", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", + "CMT_TOP_NE2A2_11", + "CMT_TOP_FAN5_2", + "CMT_TOP_SW2A3_9", + "CMT_TOP_NW2A1_1", + "CMT_TOP_FAN1_1", + "CMT_TOP_IMUX5_7", + "CMT_PLL_PHASERD_DQSBUS1", + "CMT_TOP_IMUX11_11", + "CMT_TOP_NE2A1_5", + "CMT_TOP_CLK1_0", + "CMT_TOP_LOGIC_OUTS_L_B16_7", + "CMT_TOP_SW4END1_11", + "CMT_TOP_EE4BEG2_2", + "CMT_TOP_LOGIC_OUTS_L_B15_7", + "CMT_TOP_IMUX28_9", + "CMT_TOP_NW4A1_4", + "CMT_TOP_NE4C2_5", + "CMT_TOP_WW4B2_8", + "CMT_TOP_SE4BEG1_3", + "CMT_TOP_SE4BEG3_7", + "CMT_PLL_PHASERD_DTSBUS0", + "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "CMT_TOP_LOGIC_OUTS_L_B5_9", + "CMT_TOP_WW4B2_6", + "CMT_TOP_WW2END1_11", + "CMT_TOP_IMUX19_0", + "CMT_TOP_LH3_3", + "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "CMT_TOP_IMUX31_2", + "CMT_TOP_IMUX38_5", + "CMT_TOP_ER1BEG0_11", + "CMT_TOP_LOGIC_OUTS_L_B19_11", + "CMT_TOP_LH4_2", + "CMT_TOP_SE2A0_11", + "CMT_TOP_LOGIC_OUTS_L_B6_2", + "CMT_TOP_LH12_9", + "CMT_TOP_SW2A0_0", + "CMT_TOP_SW2A0_11", + "CMT_TOP_WW4A3_7", + "CMT_TOP_WW4END2_12", + "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", + "CMT_TOP_BYP5_10", + "CMT_TOP_LH12_11", + "CMT_TOP_SW4A1_3", + "CMT_TOP_IMUX44_10", + "CMT_TOP_BLOCK_OUTS_L_B2_3", + "CMT_TOP_SE4BEG2_2", + "CMT_TOP_WW2A0_4", + "CMT_TOP_NE4BEG1_8", + "CMT_TOP_EE4C3_3", + "CMT_TOP_IMUX30_1", + "CMT_TOP_IMUX0_1", + "CMT_TOP_IMUX39_3", + "CMT_TOP_LOGIC_OUTS_L_B21_0", + "CMT_TOP_FAN6_1", + "CMT_TOP_IMUX27_0", + "CMT_TOP_IMUX43_12", + "CMT_TOP_ER1BEG2_11", + "CMT_TOP_IMUX21_10", + "CMT_TOP_NE2A2_9", + "CMT_TOP_EE4B1_11", + "CMT_TOP_IMUX37_0", + "CMT_TOP_EL1BEG2_3", + "CMT_TOP_NW4END0_10", + "CMT_TOP_LOGIC_OUTS_L_B20_11", + "CMT_TOP_LOGIC_OUTS_L_B22_8", + "CMT_TOP_OCLKDIV_2", + "CMT_TOP_SE4BEG2_7", + "CMT_TOP_IMUX44_1", + "CMT_TOP_IMUX37_7", + "CMT_TOP_CTRL0_12", + "CMT_TOP_IMUX29_1", + "CMT_TOP_FAN6_11", + "CMT_TOP_NW4A0_1" + ], + "tile_type": "CMT_TOP_R_UPPER_T", + "sites": [ + { + "site_pins": { + "CLKOUT2": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", + "TESTOUT25": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", + "DADDR5": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", + "TESTOUT32": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", + "TESTOUT29": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", + "TESTOUT43": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", + "TESTIN29": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", + "TESTOUT18": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", + "DI10": "CMT_TOP_R_UPPER_T_PLLE2_DI10", + "TESTIN14": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", + "TESTIN21": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", + "TESTOUT15": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", + "TESTIN18": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", + "TESTOUT61": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", + "DO12": "CMT_TOP_R_UPPER_T_PLLE2_DO12", + "DO10": "CMT_TOP_R_UPPER_T_PLLE2_DO10", + "TESTOUT40": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", + "TESTOUT23": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", + "TESTOUT59": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", + "TESTOUT50": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", + "TESTOUT49": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", + "DI3": "CMT_TOP_R_UPPER_T_PLLE2_DI3", + "TESTOUT46": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", + "CLKIN1": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", + "TESTOUT6": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", + "TESTOUT12": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", + "TESTIN22": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", + "DI15": "CMT_TOP_R_UPPER_T_PLLE2_DI15", + "DCLK": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", + "CLKFBIN": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", + "DI9": "CMT_TOP_R_UPPER_T_PLLE2_DI9", + "CLKINSEL": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", + "TESTIN30": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", + "TESTOUT0": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", + "TESTOUT60": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", + "TESTOUT9": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", + "DO0": "CMT_TOP_R_UPPER_T_PLLE2_DO0", + "TESTOUT35": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", + "TESTOUT47": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", + "DO3": "CMT_TOP_R_UPPER_T_PLLE2_DO3", + "DI4": "CMT_TOP_R_UPPER_T_PLLE2_DI4", + "DI0": "CMT_TOP_R_UPPER_T_PLLE2_DI0", + "DI7": "CMT_TOP_R_UPPER_T_PLLE2_DI7", + "TESTOUT57": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", + "TESTIN4": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", + "TESTOUT24": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", + "DADDR3": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", + "DO4": "CMT_TOP_R_UPPER_T_PLLE2_DO4", + "TESTOUT48": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", + "TESTIN1": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", + "TESTOUT27": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", + "TESTOUT13": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", + "TESTOUT7": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", + "CLKOUT4": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", + "TESTOUT3": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", + "TESTIN28": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", + "TESTOUT54": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", + "RST": "CMT_TOP_R_UPPER_T_PLLE2_RST", + "TESTOUT8": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", + "CLKOUT5": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", + "TESTIN20": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", + "TESTIN9": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", + "TESTOUT39": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", + "TESTOUT51": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", + "TESTOUT20": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", + "PWRDWN": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", + "TESTIN27": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", + "TESTOUT52": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", + "DI13": "CMT_TOP_R_UPPER_T_PLLE2_DI13", + "TESTIN24": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", + "TESTOUT11": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", + "DO1": "CMT_TOP_R_UPPER_T_PLLE2_DO1", + "DADDR4": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", + "DI14": "CMT_TOP_R_UPPER_T_PLLE2_DI14", + "TESTIN6": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", + "DI2": "CMT_TOP_R_UPPER_T_PLLE2_DI2", + "DADDR0": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", + "DO8": "CMT_TOP_R_UPPER_T_PLLE2_DO8", + "DI12": "CMT_TOP_R_UPPER_T_PLLE2_DI12", + "DO14": "CMT_TOP_R_UPPER_T_PLLE2_DO14", + "TESTOUT34": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", + "DI6": "CMT_TOP_R_UPPER_T_PLLE2_DI6", + "TESTOUT14": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", + "DI5": "CMT_TOP_R_UPPER_T_PLLE2_DI5", + "TESTIN25": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", + "DO9": "CMT_TOP_R_UPPER_T_PLLE2_DO9", + "DI11": "CMT_TOP_R_UPPER_T_PLLE2_DI11", + "CLKOUT3": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", + "TESTIN23": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", + "TESTOUT2": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", + "DADDR1": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", + "TESTOUT30": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", + "TESTIN12": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", + "DWE": "CMT_TOP_R_UPPER_T_PLLE2_DWE", + "TMUXOUT": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", + "TESTIN10": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", + "TESTIN31": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", + "TESTIN11": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", + "TESTOUT4": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", + "TESTOUT58": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", + "TESTOUT36": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", + "TESTOUT56": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", + "TESTOUT44": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", + "TESTOUT63": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", + "TESTIN26": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", + "TESTOUT22": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", + "TESTIN5": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", + "TESTIN7": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", + "DO5": "CMT_TOP_R_UPPER_T_PLLE2_DO5", + "TESTOUT17": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", + "TESTIN8": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", + "CLKFBOUT": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", + "TESTOUT33": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", + "DADDR6": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", + "DO13": "CMT_TOP_R_UPPER_T_PLLE2_DO13", + "DRDY": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", + "DO7": "CMT_TOP_R_UPPER_T_PLLE2_DO7", + "DI1": "CMT_TOP_R_UPPER_T_PLLE2_DI1", + "DO15": "CMT_TOP_R_UPPER_T_PLLE2_DO15", + "CLKIN2": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", + "TESTOUT42": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", + "TESTIN0": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", + "TESTOUT31": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", + "LOCKED": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", + "DO2": "CMT_TOP_R_UPPER_T_PLLE2_DO2", + "TESTIN13": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", + "TESTIN16": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", + "TESTIN2": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", + "DI8": "CMT_TOP_R_UPPER_T_PLLE2_DI8", + "DADDR2": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", + "TESTOUT5": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", + "DO11": "CMT_TOP_R_UPPER_T_PLLE2_DO11", + "TESTOUT53": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", + "TESTOUT38": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", + "DEN": "CMT_TOP_R_UPPER_T_PLLE2_DEN", + "TESTOUT10": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", + "TESTOUT62": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", + "TESTIN3": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", + "TESTOUT1": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", + "TESTOUT21": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", + "TESTIN15": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", + "TESTOUT16": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", + "TESTOUT45": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", + "TESTOUT26": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", + "CLKOUT1": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", + "TESTOUT28": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", + "TESTOUT55": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", + "TESTIN17": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", + "TESTOUT41": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", + "TESTOUT19": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", + "TESTIN19": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", + "CLKOUT0": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", + "DO6": "CMT_TOP_R_UPPER_T_PLLE2_DO6", + "TESTOUT37": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37" + }, + "type": "PLLE2_ADV", + "prefix": "PLLE2_ADV", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_DSP_L.json b/artix7/tile_type_DSP_L.json index 4db11fa..c23a5c9 100644 --- a/artix7/tile_type_DSP_L.json +++ b/artix7/tile_type_DSP_L.json @@ -1,8474 +1,8474 @@ { + "pips": { + "DSP_L.DSP_CLK0_1->DSP_0_CLK": { + "can_invert": "0", + "src_wire": "DSP_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CLK" + }, + "DSP_L.DSP_FAN6_4->DSP_1_D17": { + "can_invert": "0", + "src_wire": "DSP_FAN6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17" + }, + "DSP_L.DSP_GND_L->DSP_0_D19": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19" + }, + "DSP_L.DSP_0_PCOUT9->DSP_1_PCIN9": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN9" + }, + "DSP_L.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { + "can_invert": "0", + "src_wire": "DSP_1_P22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D24": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24" + }, + "DSP_L.DSP_GND_L->DSP_0_D10": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10" + }, + "DSP_L.DSP_BYP4_4->DSP_1_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_BYP4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3" + }, + "DSP_L.DSP_1_BCOUT6->DSP_BCOUT6": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT6" + }, + "DSP_L.DSP_IMUX20_3->DSP_0_C34": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C34" + }, + "DSP_L.DSP_0_ACOUT24->DSP_1_ACIN24": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN24" + }, + "DSP_L.DSP_GND_L->DSP_1_D15": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15" + }, + "DSP_L.DSP_VCC_L->DSP_1_D4": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4" + }, + "DSP_L.DSP_GND_L->DSP_0_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2" + }, + "DSP_L.DSP_1_PCOUT29->DSP_PCOUT29": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT29" + }, + "DSP_L.DSP_0_ACOUT19->DSP_1_ACIN19": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN19" + }, + "DSP_L.DSP_IMUX4_3->DSP_1_A15": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A15" + }, + "DSP_L.DSP_IMUX36_3->DSP_1_OPMODE2": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE2" + }, + "DSP_L.DSP_IMUX40_1->DSP_0_CEA1": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEA1" + }, + "DSP_L.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { + "can_invert": "0", + "src_wire": "DSP_0_P10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_2" + }, + "DSP_L.DSP_0_ACOUT1->DSP_1_ACIN1": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN1" + }, + "DSP_L.DSP_VCC_L->DSP_1_D14": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14" + }, + "DSP_L.DSP_IMUX35_1->DSP_0_C5": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C5" + }, + "DSP_L.DSP_BYP4_3->DSP_1_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_BYP4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE" + }, + "DSP_L.DSP_IMUX38_1->DSP_0_B4": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B4" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3" + }, + "DSP_L.DSP_IMUX40_4->DSP_1_ALUMODE1": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE1" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0" + }, + "DSP_L.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL0" + }, + "DSP_L.DSP_1_ACOUT22->DSP_ACOUT22": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT22" + }, + "DSP_L.DSP_IMUX12_0->DSP_1_C22": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C22" + }, + "DSP_L.DSP_IMUX17_1->DSP_0_A7": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A7" + }, + "DSP_L.DSP_IMUX22_0->DSP_0_B0": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B0" + }, + "DSP_L.DSP_VCC_L->DSP_0_CEAD": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD" + }, + "DSP_L.DSP_IMUX47_3->DSP_0_A12": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A12" + }, + "DSP_L.DSP_1_PCOUT14->DSP_PCOUT14": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT14" + }, + "DSP_L.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { + "can_invert": "0", + "src_wire": "DSP_0_P30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_2" + }, + "DSP_L.DSP_IMUX8_3->DSP_1_CEB1": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEB1" + }, + "DSP_L.DSP_GND_L->DSP_1_D22": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22" + }, + "DSP_L.DSP_GND_L->DSP_0_RSTD": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD" + }, + "DSP_L.DSP_0_BCOUT6->DSP_1_BCIN6": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN6" + }, + "DSP_L.DSP_FAN3_3->DSP_1_D12": { + "can_invert": "0", + "src_wire": "DSP_FAN3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12" + }, + "DSP_L.DSP_GND_L->DSP_1_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2" + }, + "DSP_L.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { + "can_invert": "0", + "src_wire": "DSP_0_P44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_4" + }, + "DSP_L.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { + "can_invert": "0", + "src_wire": "DSP_0_P34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_3" + }, + "DSP_L.DSP_0_PCOUT29->DSP_1_PCIN29": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN29" + }, + "DSP_L.DSP_0_ACOUT0->DSP_1_ACIN0": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN0" + }, + "DSP_L.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { + "can_invert": "0", + "src_wire": "DSP_1_P24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_1" + }, + "DSP_L.DSP_IMUX13_4->DSP_1_C18": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C18" + }, + "DSP_L.DSP_0_PCOUT23->DSP_1_PCIN23": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN23" + }, + "DSP_L.DSP_IMUX19_0->DSP_0_A1": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A1" + }, + "DSP_L.DSP_0_PCOUT18->DSP_1_PCIN18": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN18" + }, + "DSP_L.DSP_IMUX20_4->DSP_0_C38": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C38" + }, + "DSP_L.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { + "can_invert": "0", + "src_wire": "DSP_1_P2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D21": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21" + }, + "DSP_L.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { + "can_invert": "0", + "src_wire": "DSP_1_P34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_3" + }, + "DSP_L.DSP_IMUX6_3->DSP_0_A15": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A15" + }, + "DSP_L.DSP_VCC_L->DSP_1_D13": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13" + }, + "DSP_L.DSP_1_PCOUT30->DSP_PCOUT30": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT30" + }, + "DSP_L.DSP_GND_L->DSP_1_D3": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3" + }, + "DSP_L.DSP_GND_L->DSP_1_D14": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14" + }, + "DSP_L.DSP_VCC_L->DSP_0_D20": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20" + }, + "DSP_L.DSP_IMUX11_0->DSP_1_A1": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A1" + }, + "DSP_L.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { + "can_invert": "0", + "src_wire": "DSP_1_P23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_0" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4" + }, + "DSP_L.DSP_FAN1_2->DSP_0_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_FAN1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2" + }, + "DSP_L.DSP_0_PCOUT22->DSP_1_PCIN22": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN22" + }, + "DSP_L.DSP_1_PCOUT24->DSP_PCOUT24": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT24" + }, + "DSP_L.DSP_IMUX11_1->DSP_1_A5": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A5" + }, + "DSP_L.DSP_IMUX11_4->DSP_1_C46": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C46" + }, + "DSP_L.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { + "can_invert": "0", + "src_wire": "DSP_1_P16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_4" + }, + "DSP_L.DSP_IMUX46_4->DSP_0_A18": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A18" + }, + "DSP_L.DSP_GND_L->DSP_0_D23": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23" + }, + "DSP_L.DSP_0_ACOUT22->DSP_1_ACIN22": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN22" + }, + "DSP_L.DSP_1_PCOUT19->DSP_PCOUT19": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT19" + }, + "DSP_L.DSP_GND_L->DSP_1_D1": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1" + }, + "DSP_L.DSP_0_ACOUT3->DSP_1_ACIN3": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN3" + }, + "DSP_L.DSP_VCC_L->DSP_0_D24": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24" + }, + "DSP_L.DSP_VCC_L->DSP_0_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE" + }, + "DSP_L.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { + "can_invert": "0", + "src_wire": "DSP_0_P7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_1" + }, + "DSP_L.DSP_IMUX27_0->DSP_1_C40": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C40" + }, + "DSP_L.DSP_VCC_L->DSP_0_D9": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9" + }, + "DSP_L.DSP_IMUX44_1->DSP_1_A26": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A26" + }, + "DSP_L.DSP_GND_L->DSP_0_D4": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4" + }, + "DSP_L.DSP_0_PCOUT37->DSP_1_PCIN37": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN37" + }, + "DSP_L.DSP_IMUX8_0->DSP_1_C41": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C41" + }, + "DSP_L.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { + "can_invert": "0", + "src_wire": "DSP_1_P18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_4" + }, + "DSP_L.DSP_IMUX37_4->DSP_0_C45": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C45" + }, + "DSP_L.DSP_0_PCOUT38->DSP_1_PCIN38": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN38" + }, + "DSP_L.DSP_0_PCOUT47->DSP_1_PCIN47": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN47" + }, + "DSP_L.DSP_BYP3_0->DSP_0_D2": { + "can_invert": "0", + "src_wire": "DSP_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2" + }, + "DSP_L.DSP_0_PCOUT35->DSP_1_PCIN35": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN35" + }, + "DSP_L.DSP_0_ACOUT12->DSP_1_ACIN12": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN12" + }, + "DSP_L.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { + "can_invert": "0", + "src_wire": "DSP_1_P9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_2" + }, + "DSP_L.DSP_IMUX27_3->DSP_1_C13": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C13" + }, + "DSP_L.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { + "can_invert": "0", + "src_wire": "DSP_1_P0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D21": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21" + }, + "DSP_L.DSP_0_PCOUT13->DSP_1_PCIN13": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN13" + }, + "DSP_L.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { + "can_invert": "0", + "src_wire": "DSP_1_PATTERNDETECT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_2" + }, + "DSP_L.DSP_IMUX41_4->DSP_1_C19": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C19" + }, + "DSP_L.DSP_1_PCOUT26->DSP_PCOUT26": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT26" + }, + "DSP_L.DSP_FAN7_1->DSP_0_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_FAN7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1" + }, + "DSP_L.DSP_IMUX15_1->DSP_1_A4": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A4" + }, + "DSP_L.DSP_VCC_L->DSP_0_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2" + }, + "DSP_L.DSP_IMUX5_2->DSP_1_A29": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A29" + }, + "DSP_L.DSP_0_ACOUT23->DSP_1_ACIN23": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN23" + }, + "DSP_L.DSP_1_BCOUT5->DSP_BCOUT5": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT5" + }, + "DSP_L.DSP_GND_L->DSP_1_RSTD": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD" + }, + "DSP_L.DSP_IMUX0_3->DSP_1_B15": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B15" + }, + "DSP_L.DSP_IMUX26_0->DSP_1_B1": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B1" + }, + "DSP_L.DSP_VCC_L->DSP_0_D5": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5" + }, + "DSP_L.DSP_VCC_L->DSP_0_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3" + }, + "DSP_L.DSP_IMUX29_4->DSP_1_C45": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C45" + }, + "DSP_L.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL1" + }, + "DSP_L.DSP_1_ACOUT11->DSP_ACOUT11": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT11" + }, + "DSP_L.DSP_IMUX6_2->DSP_0_C28": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C28" + }, + "DSP_L.DSP_IMUX34_0->DSP_0_B1": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B1" + }, + "DSP_L.DSP_1_PCOUT6->DSP_PCOUT6": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT6" + }, + "DSP_L.DSP_VCC_L->DSP_1_D10": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10" + }, + "DSP_L.DSP_0_BCOUT14->DSP_1_BCIN14": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN14" + }, + "DSP_L.DSP_GND_L->DSP_0_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3" + }, + "DSP_L.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { + "can_invert": "0", + "src_wire": "DSP_1_P6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_1" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0" + }, + "DSP_L.DSP_0_PCOUT27->DSP_1_PCIN27": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN27" + }, + "DSP_L.DSP_IMUX5_4->DSP_1_A17": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A17" + }, + "DSP_L.DSP_IMUX1_3->DSP_1_B13": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B13" + }, + "DSP_L.DSP_IMUX45_4->DSP_1_A16": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A16" + }, + "DSP_L.DSP_1_ACOUT12->DSP_ACOUT12": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT12" + }, + "DSP_L.DSP_1_ACOUT21->DSP_ACOUT21": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT21" + }, + "DSP_L.DSP_1_BCOUT15->DSP_BCOUT15": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT15" + }, + "DSP_L.DSP_1_ACOUT19->DSP_ACOUT19": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT19" + }, + "DSP_L.DSP_FAN1_0->DSP_1_D20": { + "can_invert": "0", + "src_wire": "DSP_FAN1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20" + }, + "DSP_L.DSP_IMUX41_1->DSP_0_CEB1": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEB1" + }, + "DSP_L.DSP_IMUX13_2->DSP_1_A10": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A10" + }, + "DSP_L.DSP_1_ACOUT7->DSP_ACOUT7": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT7" + }, + "DSP_L.DSP_GND_L->DSP_0_D5": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5" + }, + "DSP_L.DSP_0_BCOUT4->DSP_1_BCIN4": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN4" + }, + "DSP_L.DSP_0_ACOUT21->DSP_1_ACIN21": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN21" + }, + "DSP_L.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { + "can_invert": "0", + "src_wire": "DSP_1_P35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_3" + }, + "DSP_L.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { + "can_invert": "0", + "src_wire": "DSP_0_P8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_2" + }, + "DSP_L.DSP_FAN5_4->DSP_1_D18": { + "can_invert": "0", + "src_wire": "DSP_FAN5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18" + }, + "DSP_L.DSP_IMUX4_0->DSP_1_A23": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A23" + }, + "DSP_L.DSP_IMUX35_0->DSP_0_C40": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C40" + }, + "DSP_L.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { + "can_invert": "0", + "src_wire": "DSP_1_P31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_2" + }, + "DSP_L.DSP_0_PCOUT42->DSP_1_PCIN42": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN42" + }, + "DSP_L.DSP_FAN4_0->DSP_1_D3": { + "can_invert": "0", + "src_wire": "DSP_FAN4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3" + }, + "DSP_L.DSP_IMUX37_1->DSP_0_C6": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C6" + }, + "DSP_L.DSP_FAN3_1->DSP_1_D4": { + "can_invert": "0", + "src_wire": "DSP_FAN3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4" + }, + "DSP_L.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "DSP_0_P38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_4" + }, + "DSP_L.DSP_FAN4_2->DSP_1_D11": { + "can_invert": "0", + "src_wire": "DSP_FAN4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11" + }, + "DSP_L.DSP_IMUX46_1->DSP_0_A26": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A26" + }, + "DSP_L.DSP_IMUX15_3->DSP_1_CARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYIN" + }, + "DSP_L.DSP_IMUX41_3->DSP_1_B12": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B12" + }, + "DSP_L.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "DSP_1_P40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D12": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12" + }, + "DSP_L.DSP_IMUX26_3->DSP_1_CECARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CECARRYIN" + }, + "DSP_L.DSP_GND_L->DSP_0_D8": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8" + }, + "DSP_L.DSP_GND_L->DSP_1_D24": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24" + }, + "DSP_L.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "DSP_0_P6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_1" + }, + "DSP_L.DSP_GND_L->DSP_0_D7": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7" + }, + "DSP_L.DSP_VCC_L->DSP_0_D23": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23" + }, + "DSP_L.DSP_VCC_L->DSP_1_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2" + }, + "DSP_L.DSP_VCC_L->DSP_1_D20": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20" + }, + "DSP_L.DSP_IMUX24_3->DSP_1_C35": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C35" + }, + "DSP_L.DSP_IMUX33_3->DSP_0_C15": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C15" + }, + "DSP_L.DSP_GND_L->DSP_0_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE" + }, + "DSP_L.DSP_IMUX14_0->DSP_1_B0": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B0" + }, + "DSP_L.DSP_BYP6_4->DSP_1_RSTD": { + "can_invert": "0", + "src_wire": "DSP_BYP6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD" + }, + "DSP_L.DSP_VCC_L->DSP_1_D18": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18" + }, + "DSP_L.DSP_1_PCOUT43->DSP_PCOUT43": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT43" + }, + "DSP_L.DSP_VCC_L->DSP_1_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3" + }, + "DSP_L.DSP_VCC_L->DSP_1_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6" + }, + "DSP_L.DSP_IMUX1_0->DSP_0_C3": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C3" + }, + "DSP_L.DSP_0_PCOUT43->DSP_1_PCIN43": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN43" + }, + "DSP_L.DSP_IMUX21_1->DSP_0_A6": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A6" + }, + "DSP_L.DSP_1_ACOUT24->DSP_ACOUT24": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT24" + }, + "DSP_L.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "DSP_1_P46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_4" + }, + "DSP_L.DSP_FAN7_0->DSP_1_D24": { + "can_invert": "0", + "src_wire": "DSP_FAN7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24" + }, + "DSP_L.DSP_IMUX34_2->DSP_0_CEP": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEP" + }, + "DSP_L.DSP_FAN2_3->DSP_1_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_FAN2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE" + }, + "DSP_L.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { + "can_invert": "0", + "src_wire": "DSP_1_P25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_1" + }, + "DSP_L.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTALLCARRYIN" + }, + "DSP_L.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYCASCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_CARRYCASCOUT" + }, + "DSP_L.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTALLCARRYIN" + }, + "DSP_L.DSP_IMUX13_1->DSP_1_A6": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A6" + }, + "DSP_L.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { + "can_invert": "0", + "src_wire": "DSP_1_P20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_0" + }, + "DSP_L.DSP_IMUX31_0->DSP_1_C0": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C0" + }, + "DSP_L.DSP_IMUX42_2->DSP_1_B9": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B9" + }, + "DSP_L.DSP_0_ACOUT9->DSP_1_ACIN9": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN9" + }, + "DSP_L.DSP_GND_L->DSP_0_D22": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22" + }, + "DSP_L.DSP_IMUX16_4->DSP_1_OPMODE3": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE3" + }, + "DSP_L.DSP_1_BCOUT12->DSP_BCOUT12": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT12" + }, + "DSP_L.DSP_GND_L->DSP_1_D6": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6" + }, + "DSP_L.DSP_IMUX17_0->DSP_0_A3": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A3" + }, + "DSP_L.DSP_IMUX46_3->DSP_0_A14": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A14" + }, + "DSP_L.DSP_0_ACOUT4->DSP_1_ACIN4": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN4" + }, + "DSP_L.DSP_1_PCOUT21->DSP_PCOUT21": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT21" + }, + "DSP_L.DSP_IMUX24_0->DSP_1_C23": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C23" + }, + "DSP_L.DSP_VCC_L->DSP_0_D11": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11" + }, + "DSP_L.DSP_1_ACOUT18->DSP_ACOUT18": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT18" + }, + "DSP_L.DSP_CTRL0_0->DSP_0_RSTP": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTP" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2" + }, + "DSP_L.DSP_1_ACOUT16->DSP_ACOUT16": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT16" + }, + "DSP_L.DSP_0_PCOUT11->DSP_1_PCIN11": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN11" + }, + "DSP_L.DSP_IMUX19_2->DSP_0_A9": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A9" + }, + "DSP_L.DSP_IMUX4_2->DSP_0_C30": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C30" + }, + "DSP_L.DSP_IMUX9_0->DSP_1_A3": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A3" + }, + "DSP_L.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { + "can_invert": "0", + "src_wire": "DSP_0_P16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_4" + }, + "DSP_L.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { + "can_invert": "0", + "src_wire": "DSP_0_P33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_3" + }, + "DSP_L.DSP_VCC_L->DSP_0_D16": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16" + }, + "DSP_L.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { + "can_invert": "0", + "src_wire": "DSP_0_P40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_0" + }, + "DSP_L.DSP_VCC_L->DSP_0_D8": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8" + }, + "DSP_L.DSP_1_BCOUT1->DSP_BCOUT1": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT1" + }, + "DSP_L.DSP_IMUX15_0->DSP_1_A0": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A0" + }, + "DSP_L.DSP_IMUX3_4->DSP_0_B17": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B17" + }, + "DSP_L.DSP_1_BCOUT13->DSP_BCOUT13": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT13" + }, + "DSP_L.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { + "can_invert": "0", + "src_wire": "DSP_1_P29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_2" + }, + "DSP_L.DSP_IMUX12_3->DSP_1_C34": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C34" + }, + "DSP_L.DSP_IMUX1_4->DSP_0_C19": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C19" + }, + "DSP_L.DSP_IMUX40_0->DSP_0_B3": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B3" + }, + "DSP_L.DSP_IMUX33_1->DSP_0_C7": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C7" + }, + "DSP_L.DSP_0_ACOUT27->DSP_1_ACIN27": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN27" + }, + "DSP_L.DSP_IMUX28_3->DSP_1_OPMODE0": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE0" + }, + "DSP_L.DSP_BYP5_0->DSP_0_D1": { + "can_invert": "0", + "src_wire": "DSP_BYP5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1" + }, + "DSP_L.DSP_1_BCOUT9->DSP_BCOUT9": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT9" + }, + "DSP_L.DSP_IMUX43_1->DSP_0_RSTCTRL": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTCTRL" + }, + "DSP_L.DSP_IMUX21_4->DSP_0_C18": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C18" + }, + "DSP_L.DSP_1_PCOUT46->DSP_PCOUT46": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT46" + }, + "DSP_L.DSP_BYP0_3->DSP_1_CEAD": { + "can_invert": "0", + "src_wire": "DSP_BYP0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD" + }, + "DSP_L.DSP_IMUX44_2->DSP_1_B10": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B10" + }, + "DSP_L.DSP_1_PCOUT22->DSP_PCOUT22": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT22" + }, + "DSP_L.DSP_IMUX7_1->DSP_0_A25": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A25" + }, + "DSP_L.DSP_IMUX20_0->DSP_0_C22": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C22" + }, + "DSP_L.DSP_0_ACOUT8->DSP_1_ACIN8": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN8" + }, + "DSP_L.DSP_1_PCOUT17->DSP_PCOUT17": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT17" + }, + "DSP_L.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { + "can_invert": "0", + "src_wire": "DSP_0_MULTSIGNOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_MULTSIGNIN" + }, + "DSP_L.DSP_1_ACOUT27->DSP_ACOUT27": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT27" + }, + "DSP_L.DSP_IMUX12_2->DSP_0_OPMODE5": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE5" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2" + }, + "DSP_L.DSP_GND_L->DSP_1_D5": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5" + }, + "DSP_L.DSP_IMUX15_2->DSP_1_A8": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A8" + }, + "DSP_L.DSP_IMUX18_3->DSP_0_C33": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C33" + }, + "DSP_L.DSP_IMUX22_1->DSP_0_C24": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C24" + }, + "DSP_L.DSP_IMUX41_0->DSP_1_C3": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C3" + }, + "DSP_L.DSP_1_PCOUT1->DSP_PCOUT1": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT1" + }, + "DSP_L.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { + "can_invert": "0", + "src_wire": "DSP_0_P29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_2" + }, + "DSP_L.DSP_GND_L->DSP_0_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2" + }, + "DSP_L.DSP_IMUX12_4->DSP_1_C38": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C38" + }, + "DSP_L.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { + "can_invert": "0", + "src_wire": "DSP_1_P45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_4" + }, + "DSP_L.DSP_0_PCOUT1->DSP_1_PCIN1": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN1" + }, + "DSP_L.DSP_VCC_L->DSP_0_D15": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15" + }, + "DSP_L.DSP_0_BCOUT11->DSP_1_BCIN11": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN11" + }, + "DSP_L.DSP_IMUX31_3->DSP_1_C12": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C12" + }, + "DSP_L.DSP_IMUX43_4->DSP_0_B16": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B16" + }, + "DSP_L.DSP_1_ACOUT4->DSP_ACOUT4": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT4" + }, + "DSP_L.DSP_IMUX28_0->DSP_1_B2": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B2" + }, + "DSP_L.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "DSP_0_P42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_0" + }, + "DSP_L.DSP_IMUX42_3->DSP_0_B14": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B14" + }, + "DSP_L.DSP_1_ACOUT10->DSP_ACOUT10": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT10" + }, + "DSP_L.DSP_0_ACOUT16->DSP_1_ACIN16": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN16" + }, + "DSP_L.DSP_BYP4_2->DSP_1_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_BYP4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0" + }, + "DSP_L.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { + "can_invert": "0", + "src_wire": "DSP_1_P38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_4" + }, + "DSP_L.DSP_IMUX30_2->DSP_0_OPMODE1": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE1" + }, + "DSP_L.DSP_BYP2_2->DSP_0_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_BYP2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2" + }, + "DSP_L.DSP_BYP7_1->DSP_0_D4": { + "can_invert": "0", + "src_wire": "DSP_BYP7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4" + }, + "DSP_L.DSP_0_PCOUT20->DSP_1_PCIN20": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN20" + }, + "DSP_L.DSP_IMUX40_3->DSP_1_B14": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B14" + }, + "DSP_L.DSP_0_PCOUT0->DSP_1_PCIN0": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN0" + }, + "DSP_L.DSP_1_PCOUT28->DSP_PCOUT28": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT28" + }, + "DSP_L.DSP_GND_L->DSP_0_D9": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9" + }, + "DSP_L.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { + "can_invert": "0", + "src_wire": "DSP_1_P12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_3" + }, + "DSP_L.DSP_GND_L->DSP_1_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6" + }, + "DSP_L.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "DSP_0_P5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_1" + }, + "DSP_L.DSP_CTRL1_2->DSP_1_RSTA": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTA" + }, + "DSP_L.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { + "can_invert": "0", + "src_wire": "DSP_1_P33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_3" + }, + "DSP_L.DSP_IMUX36_0->DSP_0_B2": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B2" + }, + "DSP_L.DSP_1_PCOUT18->DSP_PCOUT18": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT18" + }, + "DSP_L.DSP_IMUX10_1->DSP_1_B5": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B5" + }, + "DSP_L.DSP_VCC_L->DSP_1_D0": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0" + }, + "DSP_L.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "DSP_0_P43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_0" + }, + "DSP_L.DSP_GND_L->DSP_1_D18": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18" + }, + "DSP_L.DSP_GND_L->DSP_0_D14": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14" + }, + "DSP_L.DSP_GND_L->DSP_1_D10": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10" + }, + "DSP_L.DSP_IMUX25_3->DSP_1_C15": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C15" + }, + "DSP_L.DSP_IMUX9_3->DSP_1_CEA1": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEA1" + }, + "DSP_L.DSP_BYP2_4->DSP_1_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_BYP2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2" + }, + "DSP_L.DSP_1_BCOUT11->DSP_BCOUT11": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT11" + }, + "DSP_L.DSP_IMUX41_2->DSP_0_CECTRL": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CECTRL" + }, + "DSP_L.DSP_IMUX9_4->DSP_1_OPMODE5": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE5" + }, + "DSP_L.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "DSP_0_P32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_3" + }, + "DSP_L.DSP_IMUX32_4->DSP_0_C37": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C37" + }, + "DSP_L.DSP_IMUX18_1->DSP_0_B5": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B5" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1" + }, + "DSP_L.DSP_GND_L->DSP_1_D21": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21" + }, + "DSP_L.DSP_IMUX16_3->DSP_1_CEB2": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEB2" + }, + "DSP_L.DSP_CTRL0_3->DSP_1_RSTC": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTC" + }, + "DSP_L.DSP_IMUX18_2->DSP_0_B9": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B9" + }, + "DSP_L.DSP_IMUX33_4->DSP_0_C47": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C47" + }, + "DSP_L.DSP_1_PCOUT13->DSP_PCOUT13": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT13" + }, + "DSP_L.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "DSP_0_P36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_4" + }, + "DSP_L.DSP_VCC_L->DSP_0_D19": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19" + }, + "DSP_L.DSP_1_PCOUT36->DSP_PCOUT36": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT36" + }, + "DSP_L.DSP_FAN1_1->DSP_1_D21": { + "can_invert": "0", + "src_wire": "DSP_FAN1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21" + }, + "DSP_L.DSP_GND_L->DSP_1_D9": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9" + }, + "DSP_L.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { + "can_invert": "0", + "src_wire": "DSP_1_P27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_1" + }, + "DSP_L.DSP_FAN4_1->DSP_1_D7": { + "can_invert": "0", + "src_wire": "DSP_FAN4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7" + }, + "DSP_L.DSP_IMUX33_0->DSP_0_C43": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C43" + }, + "DSP_L.DSP_1_PCOUT10->DSP_PCOUT10": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT10" + }, + "DSP_L.DSP_GND_L->DSP_1_D13": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13" + }, + "DSP_L.DSP_1_PCOUT20->DSP_PCOUT20": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT20" + }, + "DSP_L.DSP_0_BCOUT13->DSP_1_BCIN13": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN13" + }, + "DSP_L.DSP_FAN5_3->DSP_1_D14": { + "can_invert": "0", + "src_wire": "DSP_FAN5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1" + }, + "DSP_L.DSP_BYP0_4->DSP_1_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_BYP0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3" + }, + "DSP_L.DSP_VCC_L->DSP_1_D15": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15" + }, + "DSP_L.DSP_1_ACOUT1->DSP_ACOUT1": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT1" + }, + "DSP_L.DSP_FAN5_2->DSP_1_D10": { + "can_invert": "0", + "src_wire": "DSP_FAN5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10" + }, + "DSP_L.DSP_VCC_L->DSP_0_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2" + }, + "DSP_L.DSP_0_ACOUT7->DSP_1_ACIN7": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN7" + }, + "DSP_L.DSP_1_BCOUT17->DSP_BCOUT17": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT17" + }, + "DSP_L.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { + "can_invert": "0", + "src_wire": "DSP_1_P47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_4" + }, + "DSP_L.DSP_VCC_L->DSP_0_D7": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1" + }, + "DSP_L.DSP_GND_L->DSP_1_D7": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7" + }, + "DSP_L.DSP_IMUX14_2->DSP_1_B8": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B8" + }, + "DSP_L.DSP_FAN1_3->DSP_0_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_FAN1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4" + }, + "DSP_L.DSP_VCC_L->DSP_0_D6": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6" + }, + "DSP_L.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { + "can_invert": "0", + "src_wire": "DSP_1_P1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_0" + }, + "DSP_L.DSP_IMUX18_4->DSP_0_C39": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C39" + }, + "DSP_L.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { + "can_invert": "0", + "src_wire": "DSP_1_MULTSIGNOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_MULTSIGNOUT" + }, + "DSP_L.DSP_GND_L->DSP_1_CEAD": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD" + }, + "DSP_L.DSP_VCC_L->DSP_0_D1": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1" + }, + "DSP_L.DSP_IMUX19_1->DSP_0_A5": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A5" + }, + "DSP_L.DSP_VCC_L->DSP_0_D18": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18" + }, + "DSP_L.DSP_IMUX30_0->DSP_1_C20": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C20" + }, + "DSP_L.DSP_1_PCOUT15->DSP_PCOUT15": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT15" + }, + "DSP_L.DSP_VCC_L->DSP_1_D23": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23" + }, + "DSP_L.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { + "can_invert": "0", + "src_wire": "DSP_0_P9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_2" + }, + "DSP_L.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "DSP_0_P2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_0" + }, + "DSP_L.DSP_IMUX12_1->DSP_1_C26": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C26" + }, + "DSP_L.DSP_IMUX5_1->DSP_1_A25": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A25" + }, + "DSP_L.DSP_IMUX10_0->DSP_1_C21": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C21" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1" + }, + "DSP_L.DSP_IMUX29_0->DSP_1_C2": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C2" + }, + "DSP_L.DSP_BYP4_1->DSP_0_RSTD": { + "can_invert": "0", + "src_wire": "DSP_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD" + }, + "DSP_L.DSP_FAN6_1->DSP_1_D5": { + "can_invert": "0", + "src_wire": "DSP_FAN6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5" + }, + "DSP_L.DSP_0_BCOUT12->DSP_1_BCIN12": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN12" + }, + "DSP_L.DSP_IMUX35_2->DSP_0_OPMODE0": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE0" + }, + "DSP_L.DSP_0_PCOUT28->DSP_1_PCIN28": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN28" + }, + "DSP_L.DSP_IMUX39_4->DSP_0_C16": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C16" + }, + "DSP_L.DSP_IMUX8_1->DSP_1_B7": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B7" + }, + "DSP_L.DSP_IMUX1_1->DSP_0_CEB2": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEB2" + }, + "DSP_L.DSP_IMUX0_2->DSP_0_CECARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CECARRYIN" + }, + "DSP_L.DSP_IMUX47_2->DSP_0_A28": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A28" + }, + "DSP_L.DSP_IMUX43_3->DSP_0_B12": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B12" + }, + "DSP_L.DSP_0_BCOUT2->DSP_1_BCIN2": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN2" + }, + "DSP_L.DSP_IMUX46_2->DSP_1_C28": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C28" + }, + "DSP_L.DSP_IMUX23_3->DSP_0_CARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYIN" + }, + "DSP_L.DSP_VCC_L->DSP_1_D7": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7" + }, + "DSP_L.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { + "can_invert": "0", + "src_wire": "DSP_0_P0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_0" + }, + "DSP_L.DSP_1_ACOUT5->DSP_ACOUT5": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT5" + }, + "DSP_L.DSP_IMUX33_2->DSP_0_C11": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C11" + }, + "DSP_L.DSP_IMUX29_3->DSP_1_C14": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C14" + }, + "DSP_L.DSP_IMUX35_3->DSP_0_C13": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C13" + }, + "DSP_L.DSP_CTRL0_2->DSP_0_RSTB": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTB" + }, + "DSP_L.DSP_0_PCOUT40->DSP_1_PCIN40": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN40" + }, + "DSP_L.DSP_1_PCOUT33->DSP_PCOUT33": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT33" + }, + "DSP_L.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { + "can_invert": "0", + "src_wire": "DSP_1_P41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_0" + }, + "DSP_L.DSP_0_PCOUT45->DSP_1_PCIN45": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN45" + }, + "DSP_L.DSP_VCC_L->DSP_1_D12": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12" + }, + "DSP_L.DSP_IMUX3_2->DSP_0_C9": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C9" + }, + "DSP_L.DSP_VCC_L->DSP_1_D1": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1" + }, + "DSP_L.DSP_IMUX35_4->DSP_0_C17": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C17" + }, + "DSP_L.DSP_IMUX42_4->DSP_1_B16": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B16" + }, + "DSP_L.DSP_0_PCOUT44->DSP_1_PCIN44": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN44" + }, + "DSP_L.DSP_0_ACOUT25->DSP_1_ACIN25": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN25" + }, + "DSP_L.DSP_GND_L->DSP_0_D3": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3" + }, + "DSP_L.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_3" + }, + "DSP_L.DSP_IMUX27_4->DSP_1_C17": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C17" + }, + "DSP_L.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { + "can_invert": "0", + "src_wire": "DSP_0_P25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_1" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0" + }, + "DSP_L.DSP_VCC_L->DSP_1_RSTD": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD" + }, + "DSP_L.DSP_1_PCOUT5->DSP_PCOUT5": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT5" + }, + "DSP_L.DSP_0_PCOUT15->DSP_1_PCIN15": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN15" + }, + "DSP_L.DSP_VCC_L->DSP_1_D6": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6" + }, + "DSP_L.DSP_FAN6_0->DSP_1_D1": { + "can_invert": "0", + "src_wire": "DSP_FAN6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1" + }, + "DSP_L.DSP_IMUX25_0->DSP_1_C43": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C43" + }, + "DSP_L.DSP_0_BCOUT7->DSP_1_BCIN7": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN7" + }, + "DSP_L.DSP_1_PCOUT42->DSP_PCOUT42": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT42" + }, + "DSP_L.DSP_IMUX26_4->DSP_1_C44": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C44" + }, + "DSP_L.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { + "can_invert": "0", + "src_wire": "DSP_1_P15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_3" + }, + "DSP_L.DSP_IMUX44_0->DSP_1_A22": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A22" + }, + "DSP_L.DSP_FAN5_1->DSP_1_D6": { + "can_invert": "0", + "src_wire": "DSP_FAN5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6" + }, + "DSP_L.DSP_BYP6_2->DSP_0_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_BYP6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3" + }, + "DSP_L.DSP_0_ACOUT14->DSP_1_ACIN14": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN14" + }, + "DSP_L.DSP_GND_L->DSP_0_CED": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED" + }, + "DSP_L.DSP_FAN2_2->DSP_1_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_FAN2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4" + }, + "DSP_L.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { + "can_invert": "0", + "src_wire": "DSP_0_P45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_4" + }, + "DSP_L.DSP_BYP6_3->DSP_0_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_BYP6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0" + }, + "DSP_L.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { + "can_invert": "0", + "src_wire": "DSP_1_P13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_3" + }, + "DSP_L.DSP_IMUX22_4->DSP_1_RSTALUMODE": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTALUMODE" + }, + "DSP_L.DSP_IMUX14_4->DSP_1_RSTCTRL": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTCTRL" + }, + "DSP_L.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "DSP_1_P42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_0" + }, + "DSP_L.DSP_BYP4_0->DSP_0_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE" + }, + "DSP_L.DSP_0_PCOUT4->DSP_1_PCIN4": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN4" + }, + "DSP_L.DSP_FAN4_3->DSP_1_D15": { + "can_invert": "0", + "src_wire": "DSP_FAN4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15" + }, + "DSP_L.DSP_IMUX6_4->DSP_0_A19": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A19" + }, + "DSP_L.DSP_IMUX44_4->DSP_1_A18": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A18" + }, + "DSP_L.DSP_IMUX32_1->DSP_0_C27": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C27" + }, + "DSP_L.DSP_IMUX37_0->DSP_0_C2": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C2" + }, + "DSP_L.DSP_0_BCOUT9->DSP_1_BCIN9": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN9" + }, + "DSP_L.DSP_IMUX47_1->DSP_0_A24": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A24" + }, + "DSP_L.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { + "can_invert": "0", + "src_wire": "DSP_1_P44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_4" + }, + "DSP_L.DSP_IMUX2_3->DSP_0_B15": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B15" + }, + "DSP_L.DSP_1_BCOUT0->DSP_BCOUT0": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT0" + }, + "DSP_L.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "DSP_0_P18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_4" + }, + "DSP_L.DSP_1_PCOUT32->DSP_PCOUT32": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT32" + }, + "DSP_L.DSP_0_ACOUT5->DSP_1_ACIN5": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN5" + }, + "DSP_L.DSP_0_PCOUT16->DSP_1_PCIN16": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN16" + }, + "DSP_L.DSP_IMUX9_2->DSP_1_A11": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A11" + }, + "DSP_L.DSP_0_PCOUT19->DSP_1_PCIN19": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN19" + }, + "DSP_L.DSP_1_BCOUT4->DSP_BCOUT4": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT4" + }, + "DSP_L.DSP_IMUX17_3->DSP_1_CEA2": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEA2" + }, + "DSP_L.DSP_GND_L->DSP_1_D2": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2" + }, + "DSP_L.DSP_IMUX25_4->DSP_1_C47": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C47" + }, + "DSP_L.DSP_1_PCOUT44->DSP_PCOUT44": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT44" + }, + "DSP_L.DSP_0_PCOUT24->DSP_1_PCIN24": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN24" + }, + "DSP_L.DSP_IMUX34_4->DSP_0_C44": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C44" + }, + "DSP_L.DSP_IMUX13_0->DSP_1_A2": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A2" + }, + "DSP_L.DSP_VCC_L->DSP_1_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE" + }, + "DSP_L.DSP_IMUX20_2->DSP_0_OPMODE4": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE4" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4" + }, + "DSP_L.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { + "can_invert": "0", + "src_wire": "DSP_1_P30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_2" + }, + "DSP_L.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { + "can_invert": "0", + "src_wire": "DSP_1_P39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_4" + }, + "DSP_L.DSP_IMUX7_2->DSP_0_A29": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A29" + }, + "DSP_L.DSP_0_PCOUT25->DSP_1_PCIN25": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN25" + }, + "DSP_L.DSP_0_PCOUT10->DSP_1_PCIN10": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN10" + }, + "DSP_L.DSP_FAN6_2->DSP_1_D9": { + "can_invert": "0", + "src_wire": "DSP_FAN6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9" + }, + "DSP_L.DSP_0_BCOUT10->DSP_1_BCIN10": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN10" + }, + "DSP_L.DSP_0_ACOUT17->DSP_1_ACIN17": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN17" + }, + "DSP_L.DSP_IMUX25_2->DSP_1_C11": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C11" + }, + "DSP_L.DSP_0_PCOUT14->DSP_1_PCIN14": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN14" + }, + "DSP_L.DSP_VCC_L->DSP_1_D17": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17" + }, + "DSP_L.DSP_1_ACOUT6->DSP_ACOUT6": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT6" + }, + "DSP_L.DSP_IMUX27_1->DSP_1_C5": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C5" + }, + "DSP_L.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { + "can_invert": "0", + "src_wire": "DSP_0_P12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_3" + }, + "DSP_L.DSP_FAN4_4->DSP_1_D19": { + "can_invert": "0", + "src_wire": "DSP_FAN4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19" + }, + "DSP_L.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "DSP_0_P19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_4" + }, + "DSP_L.DSP_IMUX16_1->DSP_0_B7": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B7" + }, + "DSP_L.DSP_0_PCOUT32->DSP_1_PCIN32": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN32" + }, + "DSP_L.DSP_0_ACOUT13->DSP_1_ACIN13": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN13" + }, + "DSP_L.DSP_1_ACOUT13->DSP_ACOUT13": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT13" + }, + "DSP_L.DSP_BYP7_0->DSP_0_D0": { + "can_invert": "0", + "src_wire": "DSP_BYP7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0" + }, + "DSP_L.DSP_0_PCOUT33->DSP_1_PCIN33": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN33" + }, + "DSP_L.DSP_IMUX3_0->DSP_0_C1": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C1" + }, + "DSP_L.DSP_0_PCOUT31->DSP_1_PCIN31": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN31" + }, + "DSP_L.DSP_0_PCOUT36->DSP_1_PCIN36": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN36" + }, + "DSP_L.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { + "can_invert": "0", + "src_wire": "DSP_0_UNDERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_2" + }, + "DSP_L.DSP_FAN7_3->DSP_1_D23": { + "can_invert": "0", + "src_wire": "DSP_FAN7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23" + }, + "DSP_L.DSP_1_PCOUT31->DSP_PCOUT31": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT31" + }, + "DSP_L.DSP_IMUX3_1->DSP_0_RSTALUMODE": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTALUMODE" + }, + "DSP_L.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { + "can_invert": "0", + "src_wire": "DSP_0_P39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_4" + }, + "DSP_L.DSP_GND_L->DSP_0_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6" + }, + "DSP_L.DSP_IMUX46_0->DSP_0_A22": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A22" + }, + "DSP_L.DSP_0_PCOUT39->DSP_1_PCIN39": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN39" + }, + "DSP_L.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { + "can_invert": "0", + "src_wire": "DSP_0_P26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_1" + }, + "DSP_L.DSP_0_PCOUT6->DSP_1_PCIN6": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN6" + }, + "DSP_L.DSP_IMUX1_2->DSP_0_CEM": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEM" + }, + "DSP_L.DSP_GND_L->DSP_1_D0": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0" + }, + "DSP_L.DSP_VCC_L->DSP_1_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE" + }, + "DSP_L.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { + "can_invert": "0", + "src_wire": "DSP_1_OVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_2" + }, + "DSP_L.DSP_BYP3_4->DSP_0_D18": { + "can_invert": "0", + "src_wire": "DSP_BYP3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18" + }, + "DSP_L.DSP_GND_L->DSP_0_D15": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15" + }, + "DSP_L.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { + "can_invert": "0", + "src_wire": "DSP_0_P17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_4" + }, + "DSP_L.DSP_IMUX17_4->DSP_1_OPMODE4": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE4" + }, + "DSP_L.DSP_GND_L->DSP_0_D12": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12" + }, + "DSP_L.DSP_VCC_L->DSP_1_D2": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2" + }, + "DSP_L.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { + "can_invert": "0", + "src_wire": "DSP_0_P35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_3" + }, + "DSP_L.DSP_1_PCOUT25->DSP_PCOUT25": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT25" + }, + "DSP_L.DSP_GND_L->DSP_1_D23": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23" + }, + "DSP_L.DSP_IMUX8_4->DSP_1_OPMODE1": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE1" + }, + "DSP_L.DSP_IMUX45_2->DSP_1_A28": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A28" + }, + "DSP_L.DSP_0_PCOUT17->DSP_1_PCIN17": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN17" + }, + "DSP_L.DSP_BYP2_1->DSP_1_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_BYP2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1" + }, + "DSP_L.DSP_1_ACOUT9->DSP_ACOUT9": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT9" + }, + "DSP_L.DSP_GND_L->DSP_1_D8": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8" + }, + "DSP_L.DSP_CTRL1_4->DSP_1_RSTB": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTB" + }, + "DSP_L.DSP_0_PCOUT46->DSP_1_PCIN46": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN46" + }, + "DSP_L.DSP_FAN0_1->DSP_0_CED": { + "can_invert": "0", + "src_wire": "DSP_FAN0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED" + }, + "DSP_L.DSP_IMUX37_3->DSP_0_C14": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C14" + }, + "DSP_L.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL1" + }, + "DSP_L.DSP_BYP6_0->DSP_0_D20": { + "can_invert": "0", + "src_wire": "DSP_BYP6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20" + }, + "DSP_L.DSP_1_ACOUT0->DSP_ACOUT0": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT0" + }, + "DSP_L.DSP_IMUX7_3->DSP_0_A13": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A13" + }, + "DSP_L.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { + "can_invert": "0", + "src_wire": "DSP_0_P37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_4" + }, + "DSP_L.DSP_IMUX39_2->DSP_0_C8": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C8" + }, + "DSP_L.DSP_IMUX45_0->DSP_1_A20": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A20" + }, + "DSP_L.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { + "can_invert": "0", + "src_wire": "DSP_0_P4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_1" + }, + "DSP_L.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { + "can_invert": "0", + "src_wire": "DSP_0_P3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_0" + }, + "DSP_L.DSP_BYP3_2->DSP_0_D10": { + "can_invert": "0", + "src_wire": "DSP_BYP3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10" + }, + "DSP_L.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { + "can_invert": "0", + "src_wire": "DSP_0_P13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_3" + }, + "DSP_L.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_3" + }, + "DSP_L.DSP_IMUX43_2->DSP_1_C9": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C9" + }, + "DSP_L.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "DSP_0_P27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_1" + }, + "DSP_L.DSP_GND_L->DSP_0_D13": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13" + }, + "DSP_L.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { + "can_invert": "0", + "src_wire": "DSP_1_P14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_3" + }, + "DSP_L.DSP_IMUX20_1->DSP_0_C26": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C26" + }, + "DSP_L.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "DSP_0_P23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_0" + }, + "DSP_L.DSP_IMUX3_3->DSP_0_B13": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B13" + }, + "DSP_L.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { + "can_invert": "0", + "src_wire": "DSP_0_P15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_3" + }, + "DSP_L.DSP_VCC_L->DSP_1_CED": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED" + }, + "DSP_L.DSP_0_PCOUT2->DSP_1_PCIN2": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN2" + }, + "DSP_L.DSP_FAN2_0->DSP_0_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_FAN2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE" + }, + "DSP_L.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_1" + }, + "DSP_L.DSP_0_ACOUT6->DSP_1_ACIN6": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN6" + }, + "DSP_L.DSP_IMUX16_2->DSP_0_B11": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B11" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3" + }, + "DSP_L.DSP_CLK0_3->DSP_1_CLK": { + "can_invert": "0", + "src_wire": "DSP_CLK0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CLK" + }, + "DSP_L.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYCASCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYCASCIN" + }, + "DSP_L.DSP_1_ACOUT8->DSP_ACOUT8": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT8" + }, + "DSP_L.DSP_1_PCOUT11->DSP_PCOUT11": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT11" + }, + "DSP_L.DSP_VCC_L->DSP_1_D22": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22" + }, + "DSP_L.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_3" + }, + "DSP_L.DSP_CTRL0_4->DSP_1_RSTP": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTP" + }, + "DSP_L.DSP_CTRL1_0->DSP_0_RSTA": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTA" + }, + "DSP_L.DSP_1_PCOUT2->DSP_PCOUT2": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT2" + }, + "DSP_L.DSP_IMUX37_2->DSP_0_C10": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C10" + }, + "DSP_L.DSP_BYP7_4->DSP_0_D16": { + "can_invert": "0", + "src_wire": "DSP_BYP7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16" + }, + "DSP_L.DSP_IMUX0_0->DSP_1_B3": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B3" + }, + "DSP_L.DSP_GND_L->DSP_0_D24": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24" + }, + "DSP_L.DSP_IMUX28_1->DSP_1_B6": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B6" + }, + "DSP_L.DSP_CTRL1_1->DSP_0_RSTM": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTM" + }, + "DSP_L.DSP_1_ACOUT14->DSP_ACOUT14": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT14" + }, + "DSP_L.DSP_0_ACOUT10->DSP_1_ACIN10": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN10" + }, + "DSP_L.DSP_1_PCOUT35->DSP_PCOUT35": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT35" + }, + "DSP_L.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { + "can_invert": "0", + "src_wire": "DSP_0_P47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_4" + }, + "DSP_L.DSP_0_ACOUT15->DSP_1_ACIN15": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN15" + }, + "DSP_L.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { + "can_invert": "0", + "src_wire": "DSP_1_P36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_4" + }, + "DSP_L.DSP_1_PCOUT47->DSP_PCOUT47": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT47" + }, + "DSP_L.DSP_GND_L->DSP_0_D20": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20" + }, + "DSP_L.DSP_FAN0_0->DSP_0_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_FAN0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2" + }, + "DSP_L.DSP_BYP0_2->DSP_0_D22": { + "can_invert": "0", + "src_wire": "DSP_BYP0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22" + }, + "DSP_L.DSP_IMUX34_1->DSP_0_C25": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C25" + }, + "DSP_L.DSP_0_ACOUT18->DSP_1_ACIN18": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN18" + }, + "DSP_L.DSP_VCC_L->DSP_0_D4": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4" + }, + "DSP_L.DSP_GND_L->DSP_0_CEAD": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD" + }, + "DSP_L.DSP_IMUX19_4->DSP_0_C46": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C46" + }, + "DSP_L.DSP_0_ACOUT26->DSP_1_ACIN26": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN26" + }, + "DSP_L.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "DSP_1_UNDERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_3" + }, + "DSP_L.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { + "can_invert": "0", + "src_wire": "DSP_0_P1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_0" + }, + "DSP_L.DSP_GND_L->DSP_0_D1": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1" + }, + "DSP_L.DSP_IMUX27_2->DSP_0_OPMODE2": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE2" + }, + "DSP_L.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_3" + }, + "DSP_L.DSP_GND_L->DSP_1_D17": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17" + }, + "DSP_L.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { + "can_invert": "0", + "src_wire": "DSP_1_P32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_3" + }, + "DSP_L.DSP_BYP7_3->DSP_0_D12": { + "can_invert": "0", + "src_wire": "DSP_BYP7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12" + }, + "DSP_L.DSP_BYP3_3->DSP_0_D14": { + "can_invert": "0", + "src_wire": "DSP_BYP3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14" + }, + "DSP_L.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { + "can_invert": "0", + "src_wire": "DSP_1_P7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_1" + }, + "DSP_L.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL0" + }, + "DSP_L.DSP_BYP1_4->DSP_0_D19": { + "can_invert": "0", + "src_wire": "DSP_BYP1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19" + }, + "DSP_L.DSP_IMUX5_3->DSP_1_A13": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A13" + }, + "DSP_L.DSP_GND_L->DSP_1_D16": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16" + }, + "DSP_L.DSP_BYP2_0->DSP_0_D24": { + "can_invert": "0", + "src_wire": "DSP_BYP2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24" + }, + "DSP_L.DSP_GND_L->DSP_0_D18": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18" + }, + "DSP_L.DSP_IMUX0_1->DSP_0_CEA2": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEA2" + }, + "DSP_L.DSP_0_BCOUT5->DSP_1_BCIN5": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN5" + }, + "DSP_L.DSP_0_ACOUT29->DSP_1_ACIN29": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN29" + }, + "DSP_L.DSP_FAN2_4->DSP_1_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_FAN2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6" + }, + "DSP_L.DSP_BYP1_1->DSP_0_D7": { + "can_invert": "0", + "src_wire": "DSP_BYP1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7" + }, + "DSP_L.DSP_BYP1_3->DSP_0_D15": { + "can_invert": "0", + "src_wire": "DSP_BYP1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15" + }, + "DSP_L.DSP_1_BCOUT16->DSP_BCOUT16": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT16" + }, + "DSP_L.DSP_IMUX29_1->DSP_1_C6": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C6" + }, + "DSP_L.DSP_VCC_L->DSP_0_D3": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3" + }, + "DSP_L.DSP_IMUX10_3->DSP_1_C33": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C33" + }, + "DSP_L.DSP_VCC_L->DSP_1_D3": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3" + }, + "DSP_L.DSP_IMUX18_0->DSP_0_C21": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C21" + }, + "DSP_L.DSP_0_PCOUT34->DSP_1_PCIN34": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN34" + }, + "DSP_L.DSP_GND_L->DSP_0_D11": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11" + }, + "DSP_L.DSP_1_ACOUT3->DSP_ACOUT3": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT3" + }, + "DSP_L.DSP_1_ACOUT25->DSP_ACOUT25": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT25" + }, + "DSP_L.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { + "can_invert": "0", + "src_wire": "DSP_0_OVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_2" + }, + "DSP_L.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { + "can_invert": "0", + "src_wire": "DSP_1_P8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_2" + }, + "DSP_L.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "DSP_0_P24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_1" + }, + "DSP_L.DSP_0_PCOUT12->DSP_1_PCIN12": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN12" + }, + "DSP_L.DSP_IMUX10_2->DSP_1_C29": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C29" + }, + "DSP_L.DSP_FAN3_2->DSP_1_D8": { + "can_invert": "0", + "src_wire": "DSP_FAN3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8" + }, + "DSP_L.DSP_1_PCOUT27->DSP_PCOUT27": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT27" + }, + "DSP_L.DSP_IMUX38_3->DSP_0_C32": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C32" + }, + "DSP_L.DSP_IMUX10_4->DSP_1_C39": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C39" + }, + "DSP_L.DSP_0_PCOUT41->DSP_1_PCIN41": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN41" + }, + "DSP_L.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { + "can_invert": "0", + "src_wire": "DSP_1_P19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_4" + }, + "DSP_L.DSP_IMUX7_4->DSP_0_A17": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A17" + }, + "DSP_L.DSP_IMUX6_1->DSP_0_A27": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A27" + }, + "DSP_L.DSP_IMUX7_0->DSP_0_A21": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A21" + }, + "DSP_L.DSP_BYP3_1->DSP_0_D6": { + "can_invert": "0", + "src_wire": "DSP_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6" + }, + "DSP_L.DSP_IMUX21_2->DSP_0_A10": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A10" + }, + "DSP_L.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { + "can_invert": "0", + "src_wire": "DSP_0_PATTERNDETECT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_2" + }, + "DSP_L.DSP_1_PCOUT41->DSP_PCOUT41": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT41" + }, + "DSP_L.DSP_IMUX31_1->DSP_1_C4": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C4" + }, + "DSP_L.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { + "can_invert": "0", + "src_wire": "DSP_1_P26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_1" + }, + "DSP_L.DSP_1_ACOUT20->DSP_ACOUT20": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT20" + }, + "DSP_L.DSP_VCC_L->DSP_0_CED": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED" + }, + "DSP_L.DSP_VCC_L->DSP_0_RSTD": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD" + }, + "DSP_L.DSP_BYP5_1->DSP_0_D5": { + "can_invert": "0", + "src_wire": "DSP_BYP5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5" + }, + "DSP_L.DSP_FAN5_0->DSP_1_D2": { + "can_invert": "0", + "src_wire": "DSP_FAN5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2" + }, + "DSP_L.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { + "can_invert": "0", + "src_wire": "DSP_1_P37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_4" + }, + "DSP_L.DSP_IMUX47_4->DSP_0_A16": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A16" + }, + "DSP_L.DSP_1_ACOUT23->DSP_ACOUT23": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT23" + }, + "DSP_L.DSP_IMUX9_1->DSP_1_A7": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A7" + }, + "DSP_L.DSP_BYP5_2->DSP_0_D9": { + "can_invert": "0", + "src_wire": "DSP_BYP5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9" + }, + "DSP_L.DSP_1_ACOUT15->DSP_ACOUT15": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT15" + }, + "DSP_L.DSP_IMUX29_2->DSP_1_C10": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C10" + }, + "DSP_L.DSP_VCC_L->DSP_0_D13": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13" + }, + "DSP_L.DSP_IMUX11_2->DSP_1_A9": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A9" + }, + "DSP_L.DSP_VCC_L->DSP_1_D9": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9" + }, + "DSP_L.DSP_FAN3_0->DSP_1_D0": { + "can_invert": "0", + "src_wire": "DSP_FAN3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0" + }, + "DSP_L.DSP_VCC_L->DSP_1_CEAD": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD" + }, + "DSP_L.DSP_1_PCOUT23->DSP_PCOUT23": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT23" + }, + "DSP_L.DSP_0_PCOUT8->DSP_1_PCIN8": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN8" + }, + "DSP_L.DSP_GND_L->DSP_1_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE" + }, + "DSP_L.DSP_1_BCOUT2->DSP_BCOUT2": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT2" + }, + "DSP_L.DSP_1_PCOUT45->DSP_PCOUT45": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT45" + }, + "DSP_L.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_1" + }, + "DSP_L.DSP_FAN6_3->DSP_1_D13": { + "can_invert": "0", + "src_wire": "DSP_FAN6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13" + }, + "DSP_L.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { + "can_invert": "0", + "src_wire": "DSP_1_P17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_4" + }, + "DSP_L.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { + "can_invert": "0", + "src_wire": "DSP_0_P20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_0" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4" + }, + "DSP_L.DSP_IMUX28_2->DSP_1_C30": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C30" + }, + "DSP_L.DSP_1_BCOUT3->DSP_BCOUT3": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT3" + }, + "DSP_L.DSP_IMUX24_4->DSP_1_C37": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C37" + }, + "DSP_L.DSP_0_ACOUT11->DSP_1_ACIN11": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN11" + }, + "DSP_L.DSP_IMUX38_4->DSP_0_C36": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C36" + }, + "DSP_L.DSP_BYP0_0->DSP_0_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_BYP0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3" + }, + "DSP_L.DSP_1_ACOUT2->DSP_ACOUT2": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT2" + }, + "DSP_L.DSP_BYP5_3->DSP_0_D13": { + "can_invert": "0", + "src_wire": "DSP_BYP5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13" + }, + "DSP_L.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { + "can_invert": "0", + "src_wire": "DSP_1_P11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_2" + }, + "DSP_L.DSP_GND_L->DSP_1_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3" + }, + "DSP_L.DSP_1_PCOUT12->DSP_PCOUT12": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT12" + }, + "DSP_L.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "DSP_0_PATTERNBDETECT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_2" + }, + "DSP_L.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { + "can_invert": "0", + "src_wire": "DSP_0_P31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_2" + }, + "DSP_L.DSP_IMUX42_0->DSP_0_C42": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C42" + }, + "DSP_L.DSP_IMUX5_0->DSP_1_A21": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A21" + }, + "DSP_L.DSP_IMUX44_3->DSP_1_A14": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A14" + }, + "DSP_L.DSP_0_BCOUT17->DSP_1_BCIN17": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN17" + }, + "DSP_L.DSP_IMUX39_3->DSP_0_C12": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C12" + }, + "DSP_L.DSP_BYP7_2->DSP_0_D8": { + "can_invert": "0", + "src_wire": "DSP_BYP7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8" + }, + "DSP_L.DSP_GND_L->DSP_1_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE" + }, + "DSP_L.DSP_IMUX36_1->DSP_0_B6": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B6" + }, + "DSP_L.DSP_BYP5_4->DSP_0_D17": { + "can_invert": "0", + "src_wire": "DSP_BYP5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17" + }, + "DSP_L.DSP_1_PCOUT34->DSP_PCOUT34": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT34" + }, + "DSP_L.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { + "can_invert": "0", + "src_wire": "DSP_1_P3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_0" + }, + "DSP_L.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { + "can_invert": "0", + "src_wire": "DSP_1_P10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_2" + }, + "DSP_L.DSP_0_BCOUT16->DSP_1_BCIN16": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN16" + }, + "DSP_L.DSP_IMUX23_2->DSP_0_A8": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A8" + }, + "DSP_L.DSP_GND_L->DSP_1_D12": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12" + }, + "DSP_L.DSP_IMUX43_0->DSP_1_C1": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C1" + }, + "DSP_L.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_1" + }, + "DSP_L.DSP_1_PCOUT16->DSP_PCOUT16": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT16" + }, + "DSP_L.DSP_IMUX0_4->DSP_1_ALUMODE0": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE0" + }, + "DSP_L.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { + "can_invert": "0", + "src_wire": "DSP_1_P5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_1" + }, + "DSP_L.DSP_IMUX32_2->DSP_0_C31": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C31" + }, + "DSP_L.DSP_IMUX45_1->DSP_1_A24": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A24" + }, + "DSP_L.DSP_0_BCOUT15->DSP_1_BCIN15": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN15" + }, + "DSP_L.DSP_IMUX24_2->DSP_1_C31": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C31" + }, + "DSP_L.DSP_GND_L->DSP_1_D11": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11" + }, + "DSP_L.DSP_1_ACOUT29->DSP_ACOUT29": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT29" + }, + "DSP_L.DSP_GND_L->DSP_1_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3" + }, + "DSP_L.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "DSP_0_P28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_2" + }, + "DSP_L.DSP_0_PCOUT7->DSP_1_PCIN7": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN7" + }, + "DSP_L.DSP_IMUX8_2->DSP_1_B11": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B11" + }, + "DSP_L.DSP_IMUX23_1->DSP_0_A4": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A4" + }, + "DSP_L.DSP_1_PCOUT9->DSP_PCOUT9": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT9" + }, + "DSP_L.DSP_GND_L->DSP_0_D2": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2" + }, + "DSP_L.DSP_VCC_L->DSP_0_D0": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0" + }, + "DSP_L.DSP_1_PCOUT7->DSP_PCOUT7": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT7" + }, + "DSP_L.DSP_IMUX16_0->DSP_0_C41": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C41" + }, + "DSP_L.DSP_GND_L->DSP_0_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2" + }, + "DSP_L.DSP_0_PCOUT30->DSP_1_PCIN30": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN30" + }, + "DSP_L.DSP_IMUX25_1->DSP_1_C7": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C7" + }, + "DSP_L.DSP_IMUX21_0->DSP_0_A2": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A2" + }, + "DSP_L.DSP_IMUX22_3->DSP_1_C32": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C32" + }, + "DSP_L.DSP_IMUX21_3->DSP_0_ALUMODE0": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE0" + }, + "DSP_L.DSP_IMUX32_3->DSP_0_C35": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C35" + }, + "DSP_L.DSP_0_PCOUT26->DSP_1_PCIN26": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN26" + }, + "DSP_L.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "DSP_1_P43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_0" + }, + "DSP_L.DSP_0_BCOUT1->DSP_1_BCIN1": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN1" + }, + "DSP_L.DSP_VCC_L->DSP_1_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2" + }, + "DSP_L.DSP_IMUX26_2->DSP_1_CEP": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEP" + }, + "DSP_L.DSP_FAN0_4->DSP_1_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_FAN0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2" + }, + "DSP_L.DSP_VCC_L->DSP_0_D14": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14" + }, + "DSP_L.DSP_IMUX23_4->DSP_1_RSTINMODE": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTINMODE" + }, + "DSP_L.DSP_BYP0_1->DSP_0_CEAD": { + "can_invert": "0", + "src_wire": "DSP_BYP0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD" + }, + "DSP_L.DSP_GND_L->DSP_0_D0": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0" + }, + "DSP_L.DSP_IMUX36_2->DSP_0_B10": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B10" + }, + "DSP_L.DSP_BYP6_1->DSP_0_D21": { + "can_invert": "0", + "src_wire": "DSP_BYP6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21" + }, + "DSP_L.DSP_VCC_L->DSP_1_D19": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19" + }, + "DSP_L.DSP_1_PCOUT8->DSP_PCOUT8": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT8" + }, + "DSP_L.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "DSP_0_P41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_0" + }, + "DSP_L.DSP_BYP1_2->DSP_0_D11": { + "can_invert": "0", + "src_wire": "DSP_BYP1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11" + }, + "DSP_L.DSP_GND_L->DSP_1_D19": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19" + }, + "DSP_L.DSP_IMUX17_2->DSP_0_A11": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A11" + }, + "DSP_L.DSP_0_ACOUT20->DSP_1_ACIN20": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN20" + }, + "DSP_L.DSP_VCC_L->DSP_1_D5": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5" + }, + "DSP_L.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { + "can_invert": "0", + "src_wire": "DSP_1_P4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_1" + }, + "DSP_L.DSP_FAN3_4->DSP_1_D16": { + "can_invert": "0", + "src_wire": "DSP_FAN3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16" + }, + "DSP_L.DSP_VCC_L->DSP_1_D8": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8" + }, + "DSP_L.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { + "can_invert": "0", + "src_wire": "DSP_1_P21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_0" + }, + "DSP_L.DSP_1_BCOUT10->DSP_BCOUT10": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT10" + }, + "DSP_L.DSP_IMUX26_1->DSP_1_C25": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C25" + }, + "DSP_L.DSP_IMUX24_1->DSP_1_C27": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C27" + }, + "DSP_L.DSP_0_BCOUT3->DSP_1_BCIN3": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN3" + }, + "DSP_L.DSP_GND_L->DSP_1_D4": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4" + }, + "DSP_L.DSP_IMUX31_4->DSP_1_C16": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C16" + }, + "DSP_L.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "DSP_0_P22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_0" + }, + "DSP_L.DSP_IMUX31_2->DSP_1_C8": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C8" + }, + "DSP_L.DSP_CTRL1_3->DSP_1_RSTM": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTM" + }, + "DSP_L.DSP_0_ACOUT2->DSP_1_ACIN2": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN2" + }, + "DSP_L.DSP_IMUX47_0->DSP_0_A20": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A20" + }, + "DSP_L.DSP_IMUX2_2->DSP_0_C29": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C29" + }, + "DSP_L.DSP_GND_L->DSP_1_CED": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED" + }, + "DSP_L.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "DSP_0_P46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_4" + }, + "DSP_L.DSP_IMUX32_0->DSP_0_C23": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C23" + }, + "DSP_L.DSP_1_PCOUT0->DSP_PCOUT0": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT0" + }, + "DSP_L.DSP_GND_L->DSP_1_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2" + }, + "DSP_L.DSP_VCC_L->DSP_0_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0" + }, + "DSP_L.DSP_IMUX14_1->DSP_1_C24": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C24" + }, + "DSP_L.DSP_VCC_L->DSP_0_D2": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2" + }, + "DSP_L.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "DSP_0_P14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_3" + }, + "DSP_L.DSP_VCC_L->DSP_1_D16": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16" + }, + "DSP_L.DSP_VCC_L->DSP_0_D10": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10" + }, + "DSP_L.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { + "can_invert": "0", + "src_wire": "DSP_1_P28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_2" + }, + "DSP_L.DSP_IMUX40_2->DSP_0_CEC": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEC" + }, + "DSP_L.DSP_1_PCOUT40->DSP_PCOUT40": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT40" + }, + "DSP_L.DSP_IMUX42_1->DSP_0_RSTINMODE": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTINMODE" + }, + "DSP_L.DSP_BYP1_0->DSP_0_D3": { + "can_invert": "0", + "src_wire": "DSP_BYP1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3" + }, + "DSP_L.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_1" + }, + "DSP_L.DSP_0_ACOUT28->DSP_1_ACIN28": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN28" + }, + "DSP_L.DSP_1_BCOUT7->DSP_BCOUT7": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT7" + }, + "DSP_L.DSP_IMUX4_1->DSP_1_A27": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A27" + }, + "DSP_L.DSP_IMUX2_4->DSP_1_B17": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B17" + }, + "DSP_L.DSP_IMUX19_3->DSP_1_CEM": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEM" + }, + "DSP_L.DSP_1_BCOUT14->DSP_BCOUT14": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT14" + }, + "DSP_L.DSP_IMUX30_4->DSP_1_C36": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C36" + }, + "DSP_L.DSP_CTRL0_1->DSP_0_RSTC": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTC" + }, + "DSP_L.DSP_IMUX30_1->DSP_1_B4": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B4" + }, + "DSP_L.DSP_FAN7_2->DSP_0_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_FAN7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6" + }, + "DSP_L.DSP_0_PCOUT21->DSP_1_PCIN21": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN21" + }, + "DSP_L.DSP_IMUX13_3->DSP_0_ALUMODE1": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE1" + }, + "DSP_L.DSP_VCC_L->DSP_1_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3" + }, + "DSP_L.DSP_GND_L->DSP_0_D16": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16" + }, + "DSP_L.DSP_IMUX39_0->DSP_0_C0": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C0" + }, + "DSP_L.DSP_1_ACOUT28->DSP_ACOUT28": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT28" + }, + "DSP_L.DSP_0_BCOUT8->DSP_1_BCIN8": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN8" + }, + "DSP_L.DSP_0_PCOUT5->DSP_1_PCIN5": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN5" + }, + "DSP_L.DSP_VCC_L->DSP_0_D17": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17" + }, + "DSP_L.DSP_VCC_L->DSP_0_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6" + }, + "DSP_L.DSP_IMUX45_3->DSP_1_A12": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A12" + }, + "DSP_L.DSP_0_PCOUT3->DSP_1_PCIN3": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN3" + }, + "DSP_L.DSP_1_BCOUT8->DSP_BCOUT8": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT8" + }, + "DSP_L.DSP_IMUX4_4->DSP_1_A19": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A19" + }, + "DSP_L.DSP_IMUX11_3->DSP_1_CECTRL": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CECTRL" + }, + "DSP_L.DSP_0_BCOUT0->DSP_1_BCIN0": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN0" + }, + "DSP_L.DSP_IMUX23_0->DSP_0_A0": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A0" + }, + "DSP_L.DSP_VCC_L->DSP_1_D11": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11" + }, + "DSP_L.DSP_GND_L->DSP_0_D17": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17" + }, + "DSP_L.DSP_GND_L->DSP_0_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2" + }, + "DSP_L.DSP_GND_L->DSP_0_D21": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21" + }, + "DSP_L.DSP_GND_L->DSP_0_D6": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6" + }, + "DSP_L.DSP_1_PCOUT4->DSP_PCOUT4": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT4" + }, + "DSP_L.DSP_IMUX34_3->DSP_1_CEC": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEC" + }, + "DSP_L.DSP_BYP2_3->DSP_0_D23": { + "can_invert": "0", + "src_wire": "DSP_BYP2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23" + }, + "DSP_L.DSP_1_PCOUT39->DSP_PCOUT39": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT39" + }, + "DSP_L.DSP_IMUX38_0->DSP_0_C20": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C20" + }, + "DSP_L.DSP_1_ACOUT26->DSP_ACOUT26": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT26" + }, + "DSP_L.DSP_FAN0_2->DSP_1_D22": { + "can_invert": "0", + "src_wire": "DSP_FAN0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22" + }, + "DSP_L.DSP_VCC_L->DSP_0_D22": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22" + }, + "DSP_L.DSP_1_PCOUT37->DSP_PCOUT37": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT37" + }, + "DSP_L.DSP_FAN0_3->DSP_1_CED": { + "can_invert": "0", + "src_wire": "DSP_FAN0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED" + }, + "DSP_L.DSP_IMUX39_1->DSP_0_C4": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C4" + }, + "DSP_L.DSP_VCC_L->DSP_0_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_VCC_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE" + }, + "DSP_L.DSP_IMUX6_0->DSP_0_A23": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A23" + }, + "DSP_L.DSP_FAN7_4->DSP_1_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_FAN7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2" + }, + "DSP_L.DSP_IMUX2_0->DSP_1_C42": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C42" + }, + "DSP_L.DSP_GND_L->DSP_1_D20": { + "can_invert": "0", + "src_wire": "DSP_GND_L", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20" + }, + "DSP_L.DSP_IMUX38_2->DSP_0_OPMODE3": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE3" + }, + "DSP_L.DSP_1_PCOUT38->DSP_PCOUT38": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT38" + }, + "DSP_L.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { + "can_invert": "0", + "src_wire": "DSP_0_P11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_2" + }, + "DSP_L.DSP_IMUX22_2->DSP_0_B8": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B8" + }, + "DSP_L.DSP_1_ACOUT17->DSP_ACOUT17": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT17" + }, + "DSP_L.DSP_1_PCOUT3->DSP_PCOUT3": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT3" + }, + "DSP_L.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "DSP_0_P21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_0" + }, + "DSP_L.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { + "can_invert": "0", + "src_wire": "DSP_1_PATTERNBDETECT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_2" + } + }, "wires": [ - "DSP_1_C34", - "DSP_WW2END2_4", - "DSP_0_BCIN16", - "DSP_EE2A3_2", - "DSP_IMUX44_1", - "DSP_0_INMODE3", - "DSP_NE2A3_0", - "DSP_1_C7", - "DSP_EL1BEG1_1", - "DSP_NW2A3_0", - "DSP_IMUX13_4", - "DSP_LOGIC_OUTS_B10_1", - "DSP_BLOCK_OUTS_B2_1", - "DSP_SW4END0_3", - "DSP_0_PCOUT18", - "DSP_BYP2_4", - "DSP_0_C17", - "DSP_0_PCIN25", - "DSP_0_PCOUT17", - "DSP_0_P2", - "DSP_IMUX47_0", - "DSP_WW4A2_3", - "DSP_IMUX28_1", - "DSP_NW2A2_4", - "DSP_1_P34", - "DSP_1_B8", - "DSP_IMUX19_4", - "DSP_EE2BEG3_1", - "DSP_BCOUT8", - "DSP_IMUX17_1", - "DSP_1_BCIN17", - "DSP_LH3_2", - "DSP_NE4BEG2_3", - "DSP_IMUX15_2", - "DSP_EE2A3_4", - "DSP_NE4BEG3_3", - "DSP_SW4A3_0", - "DSP_0_PCOUT6", - "DSP_1_A15", - "DSP_0_P31", - "DSP_1_ACIN25", - "DSP_1_PCIN6", - "DSP_0_ACIN2", - "DSP_BYP2_3", - "DSP_0_D22", - "DSP_0_ACOUT16", - "DSP_WW4B3_1", - "DSP_IMUX45_4", - "DSP_SW2A3_1", - "DSP_0_PCOUT12", - "DSP_SE2A1_2", - "DSP_1_PCIN28", - "DSP_1_A20", - "DSP_WW4A0_0", - "DSP_SE4BEG1_1", - "DSP_0_C45", - "DSP_ER1BEG2_3", - "DSP_1_P22", - "DSP_0_PATTERNBDETECT", - "DSP_EE2A2_3", - "DSP_IMUX23_0", - "DSP_NE4C0_3", - "DSP_0_ACOUT26", - "DSP_0_ACIN11", - "DSP_1_PATTERNBDETECT", - "DSP_NW4A0_3", - "DSP_EE4BEG1_3", - "DSP_LH3_3", - "DSP_BCOUT15", - "DSP_WW2END1_0", - "DSP_EE2A1_0", - "DSP_1_CARRYINSEL2", - "DSP_0_PCIN18", - "DSP_EE4C1_2", - "DSP_ACOUT4", - "DSP_IMUX34_2", - "DSP_EE2A0_1", - "DSP_1_B1", - "DSP_BLOCK_OUTS_B0_3", - "DSP_1_CEC", - "DSP_IMUX14_2", - "DSP_NE4C3_4", - "DSP_WL1END3_2", - "DSP_1_BCIN3", - "DSP_1_BCOUT11", - "DSP_1_A16", - "DSP_WW4C3_1", - "DSP_0_RSTC", - "DSP_PCOUT11", - "DSP_BLOCK_OUTS_B2_2", - "DSP_1_PCOUT45", - "DSP_WW4B1_1", - "DSP_0_B10", - "DSP_EE4B1_2", - "DSP_1_PCIN2", - "DSP_SW4A1_0", - "DSP_WL1END0_4", - "DSP_PCOUT18", - "DSP_PCOUT25", - "DSP_EE4BEG0_4", - "DSP_VCC_L", - "DSP_IMUX21_1", - "DSP_0_RSTALLCARRYIN", - "DSP_1_B10", - "DSP_SW4END3_3", - "DSP_SE4BEG2_0", - "DSP_SE4C3_3", - "DSP_IMUX12_0", - "DSP_EE2A1_3", - "DSP_1_ACIN6", - "DSP_LH11_2", - "DSP_0_P24", - "DSP_PCOUT43", - "DSP_0_A20", - "DSP_LOGIC_OUTS_B14_1", - "DSP_ER1BEG2_2", - "DSP_IMUX39_1", - "DSP_LOGIC_OUTS_B18_0", - "DSP_IMUX21_3", - "DSP_IMUX10_2", - "DSP_0_ACIN19", - "DSP_LOGIC_OUTS_B8_1", - "DSP_1_D13", - "DSP_0_PCIN3", - "DSP_ER1BEG0_0", - "DSP_IMUX25_0", - "DSP_1_PCIN21", - "DSP_NE2A0_4", - "DSP_1_B0", - "DSP_0_PCOUT28", - "DSP_IMUX10_4", - "DSP_NW4A2_1", - "DSP_1_PCIN44", - "DSP_EE2BEG3_0", - "DSP_1_UNDERFLOW", - "DSP_0_PCOUT35", - "DSP_0_C34", - "DSP_0_BCOUT11", - "DSP_IMUX26_3", - "DSP_EE4A3_3", - "DSP_0_PCIN36", - "DSP_IMUX3_4", - "DSP_WR1END0_1", - "DSP_0_PCIN26", - "DSP_1_A22", - "DSP_0_D8", - "DSP_FAN5_4", - "DSP_1_C18", - "DSP_LOGIC_OUTS_B11_4", - "DSP_1_ACOUT4", - "DSP_1_ACIN5", - "DSP_0_PCOUT45", - "DSP_LH12_1", - "DSP_1_D16", - "DSP_1_PCIN1", - "DSP_PCOUT4", - "DSP_EE2BEG1_0", - "DSP_0_PCIN34", - "DSP_WW4END1_2", - "DSP_1_D20", - "DSP_IMUX29_1", - "DSP_IMUX21_2", - "DSP_WW4A3_1", - "DSP_LOGIC_OUTS_B19_0", - "DSP_EE4B0_0", - "DSP_1_PCIN37", - "DSP_LOGIC_OUTS_B20_4", - "DSP_BCOUT2", - "DSP_1_PCOUT1", - "DSP_FAN7_3", - "DSP_0_C4", - "DSP_1_C45", - "DSP_1_PCOUT29", - "DSP_WL1END1_2", - "DSP_1_C39", - "DSP_LH6_3", - "DSP_LH6_4", - "DSP_1_B2", - "DSP_MONITOR_N_4", - "DSP_NE2A1_0", - "DSP_0_RSTD", - "DSP_LH4_3", - "DSP_EE4C0_0", - "DSP_0_A3", - "DSP_LOGIC_OUTS_B13_1", - "DSP_1_P32", - "DSP_1_OPMODE1", - "DSP_1_CLK", - "DSP_MONITOR_N_3", - "DSP_0_PCOUT46", - "DSP_NW2A3_3", - "DSP_IMUX18_3", - "DSP_1_ACIN1", - "DSP_0_B0", - "DSP_BCOUT11", - "DSP_IMUX28_0", - "DSP_BYP4_3", - "DSP_1_PCOUT17", - "DSP_WW2A0_1", - "DSP_SW4A0_2", - "DSP_1_B12", - "DSP_WW2A3_0", - "DSP_1_C43", - "DSP_NE4C1_3", - "DSP_LOGIC_OUTS_B9_1", - "DSP_FAN0_3", - "DSP_NE4C3_0", - "DSP_SW2A2_1", - "DSP_LOGIC_OUTS_B0_2", - "DSP_IMUX18_2", - "DSP_0_BCOUT0", - "DSP_BCOUT7", - "DSP_ACOUT25", - "DSP_NW4A1_2", - "DSP_1_BCOUT8", - "DSP_IMUX37_1", - "DSP_1_PCIN23", - "DSP_1_CARRYIN", - "DSP_LOGIC_OUTS_B8_0", - "DSP_BYP3_3", - "DSP_SW4A1_4", - "DSP_SE2A0_2", - "DSP_0_P0", - "DSP_WW4C1_2", - "DSP_LOGIC_OUTS_B14_3", - "DSP_1_PCOUT5", - "DSP_BYP7_4", - "DSP_EE4C1_3", - "DSP_0_PCIN31", - "DSP_0_D23", - "DSP_0_A15", - "DSP_WW4END1_1", - "DSP_BCOUT17", - "DSP_LOGIC_OUTS_B22_3", - "DSP_0_B15", - "DSP_1_C4", - "DSP_IMUX43_0", - "DSP_IMUX35_1", - "DSP_CTRL1_0", - "DSP_WL1END1_0", - "DSP_EE2BEG2_3", - "DSP_WW2END0_1", - "DSP_1_D10", - "DSP_IMUX0_2", - "DSP_1_CARRYCASCOUT", - "DSP_WW2A3_4", - "DSP_1_C5", - "DSP_1_P2", - "DSP_NW2A0_3", - "DSP_1_PCOUT20", - "DSP_IMUX38_1", - "DSP_0_PCOUT27", - "DSP_EE2BEG3_3", - "DSP_WW2END1_1", - "DSP_LH1_0", - "DSP_1_RSTP", - "DSP_WW2A2_1", - "DSP_SE4C3_1", - "DSP_EE4A0_3", - "DSP_LOGIC_OUTS_B14_0", - "DSP_0_ACOUT15", - "DSP_0_PCIN17", - "DSP_EL1BEG0_0", - "DSP_0_BCOUT8", - "DSP_0_ACOUT5", - "DSP_0_D0", - "DSP_EE4B0_4", - "DSP_0_BCOUT15", - "DSP_0_C25", - "DSP_IMUX24_3", - "DSP_EE2A0_0", - "DSP_0_C1", - "DSP_WW4C2_1", - "DSP_NW2A1_2", - "DSP_SW4A1_2", - "DSP_IMUX9_1", - "DSP_ER1BEG0_2", - "DSP_0_D6", - "DSP_WL1END0_1", - "DSP_PCOUT14", - "DSP_IMUX13_3", - "DSP_PCOUT23", - "DSP_IMUX7_0", - "DSP_WW4C3_4", - "DSP_IMUX30_4", - "DSP_LOGIC_OUTS_B18_3", - "DSP_0_ACIN8", - "DSP_1_C17", - "DSP_LOGIC_OUTS_B12_4", - "DSP_CTRL1_3", - "DSP_SW4END3_2", - "DSP_LH12_2", - "DSP_BYP3_4", - "DSP_WW4B0_2", - "DSP_1_A11", - "DSP_LOGIC_OUTS_B1_0", - "DSP_IMUX27_3", - "DSP_LH1_3", - "DSP_1_PCOUT2", - "DSP_ACOUT13", - "DSP_NW4A3_2", - "DSP_1_PCIN14", - "DSP_0_D10", - "DSP_1_C3", - "DSP_EE4C0_4", - "DSP_1_D17", - "DSP_1_PCIN26", - "DSP_1_ACOUT20", - "DSP_NE4BEG2_1", - "DSP_0_C23", - "DSP_IMUX3_2", - "DSP_IMUX8_0", - "DSP_WW4END1_0", - "DSP_WW4C0_3", - "DSP_IMUX35_0", - "DSP_0_BCIN17", - "DSP_0_PCOUT34", - "DSP_IMUX35_4", - "DSP_0_B13", - "DSP_SW2A3_3", - "DSP_BLOCK_OUTS_B1_3", - "DSP_LH11_0", - "DSP_WW4END3_1", - "DSP_1_ACOUT27", - "DSP_0_B9", - "DSP_WL1END0_2", - "DSP_PCOUT0", - "DSP_NE2A0_0", - "DSP_0_C9", - "DSP_WW2A3_1", - "DSP_SW2A2_0", - "DSP_0_BCIN1", - "DSP_1_A3", - "DSP_IMUX1_4", - "DSP_SW4A0_1", - "DSP_LH1_4", - "DSP_0_C18", - "DSP_0_A23", - "DSP_1_A2", - "DSP_PCOUT34", - "DSP_MONITOR_P_2", - "DSP_0_BCIN12", - "DSP_WW2END2_0", - "DSP_0_A28", - "DSP_EL1BEG1_3", - "DSP_SW4END3_0", - "DSP_EE4C3_3", - "DSP_LOGIC_OUTS_B4_2", - "DSP_1_P33", - "DSP_NW4A3_1", - "DSP_FAN0_4", - "DSP_EE4BEG2_4", - "DSP_IMUX20_1", - "DSP_1_RSTALUMODE", - "DSP_1_PCIN25", - "DSP_0_D13", - "DSP_1_RSTALLCARRYIN", - "DSP_BYP0_2", - "DSP_ACOUT27", - "DSP_NW4END2_3", - "DSP_0_PCOUT40", - "DSP_FAN6_3", - "DSP_0_PCOUT8", - "DSP_LOGIC_OUTS_B13_0", - "DSP_1_PCIN40", - "DSP_WW4B0_1", - "DSP_EE4BEG3_3", - "DSP_LOGIC_OUTS_B12_1", - "DSP_1_D2", - "DSP_1_P11", - "DSP_1_ACOUT21", - "DSP_PCOUT20", - "DSP_FAN0_2", - "DSP_0_C31", - "DSP_LOGIC_OUTS_B23_3", - "DSP_0_RSTM", - "DSP_WW4B2_1", - "DSP_LOGIC_OUTS_B7_4", - "DSP_1_PCIN41", - "DSP_1_C21", - "DSP_NE2A2_3", - "DSP_IMUX13_0", - "DSP_MONITOR_N_1", - "DSP_WW4A0_4", - "DSP_WW4B3_2", - "DSP_1_P46", - "DSP_NW4END3_3", - "DSP_EE4BEG2_1", - "DSP_WL1END2_3", - "DSP_0_PCIN4", - "DSP_WW4C2_2", - "DSP_1_D23", - "DSP_WW4END1_4", - "DSP_IMUX31_1", - "DSP_BYP6_2", - "DSP_EE4BEG2_3", - "DSP_WW4END2_4", - "DSP_WW2END1_2", - "DSP_1_BCOUT3", - "DSP_0_BCIN0", - "DSP_1_A14", - "DSP_WW4END3_0", - "DSP_ER1BEG2_4", - "DSP_WW4C1_3", - "DSP_1_B14", - "DSP_1_ALUMODE0", - "DSP_0_D7", - "DSP_SE4BEG2_2", - "DSP_EE4A0_0", - "DSP_0_P11", - "DSP_NW4A3_4", - "DSP_SW4A3_1", - "DSP_1_PCOUT46", - "DSP_PCOUT45", - "DSP_0_P45", - "DSP_1_P45", - "DSP_1_C42", - "DSP_1_BCOUT5", - "DSP_IMUX9_2", - "DSP_WW4A3_2", - "DSP_0_ACIN17", - "DSP_0_C0", - "DSP_EE2A0_3", - "DSP_1_P5", - "DSP_NW2A1_1", - "DSP_LH10_4", - "DSP_LOGIC_OUTS_B7_2", - "DSP_PCOUT46", - "DSP_1_PCIN18", - "DSP_0_B4", - "DSP_0_BCOUT6", - "DSP_FAN0_1", - "DSP_NE2A2_2", - "DSP_EL1BEG2_3", - "DSP_EL1BEG1_2", - "DSP_BLOCK_OUTS_B0_2", - "DSP_FAN1_0", - "DSP_0_BCOUT5", - "DSP_1_PCIN5", - "DSP_1_C12", - "DSP_IMUX3_1", - "DSP_SW4END2_3", - "DSP_1_OPMODE6", - "DSP_1_P37", - "DSP_1_B13", - "DSP_0_PCIN19", - "DSP_IMUX44_3", - "DSP_IMUX6_4", - "DSP_LOGIC_OUTS_B3_4", - "DSP_CLK0_3", - "DSP_1_BCIN8", - "DSP_MONITOR_P_1", - "DSP_WW4B2_3", - "DSP_0_A8", - "DSP_1_A23", - "DSP_0_D18", - "DSP_LOGIC_OUTS_B0_4", - "DSP_EE4A2_4", - "DSP_PCOUT38", - "DSP_BYP2_1", - "DSP_1_ACOUT17", - "DSP_EE2A3_1", - "DSP_0_A10", - "DSP_0_CEALUMODE", - "DSP_1_PCOUT38", - "DSP_1_ACOUT2", - "DSP_0_ACIN24", - "DSP_1_A18", - "DSP_1_P42", - "DSP_SW4A2_3", - "DSP_1_D21", - "DSP_0_B16", - "DSP_IMUX40_1", - "DSP_EE4C2_0", - "DSP_NE4C1_1", - "DSP_EE4BEG3_2", - "DSP_1_PCIN29", - "DSP_1_ACIN0", - "DSP_SE2A0_0", - "DSP_1_ACOUT24", - "DSP_EL1BEG0_1", - "DSP_BCOUT16", - "DSP_EE4B3_4", - "DSP_SW2A0_4", - "DSP_1_P14", - "DSP_0_OPMODE5", - "DSP_BLOCK_OUTS_B0_4", - "DSP_1_ACIN14", - "DSP_1_B9", - "DSP_SE4C2_2", - "DSP_IMUX47_2", - "DSP_BYP0_0", - "DSP_LOGIC_OUTS_B17_1", - "DSP_LH4_2", - "DSP_1_PCOUT37", - "DSP_LOGIC_OUTS_B21_2", - "DSP_1_BCIN14", - "DSP_ACOUT0", - "DSP_1_ACOUT18", - "DSP_0_ACOUT24", - "DSP_1_PCIN17", - "DSP_1_A24", - "DSP_1_ACOUT26", - "DSP_WW4C0_2", - "DSP_LOGIC_OUTS_B9_3", - "DSP_BLOCK_OUTS_B1_4", - "DSP_1_ACOUT10", - "DSP_IMUX34_4", - "DSP_ACOUT24", - "DSP_1_ACOUT0", - "DSP_WW2END2_3", - "DSP_IMUX18_4", - "DSP_WR1END1_0", - "DSP_EE4BEG3_0", - "DSP_EE2BEG0_1", - "DSP_WW4C2_0", - "DSP_WW4C3_0", - "DSP_WW2END2_1", - "DSP_1_C8", - "DSP_EE4C2_3", - "DSP_1_P39", - "DSP_BCOUT5", - "DSP_LOGIC_OUTS_B11_3", - "DSP_0_PCOUT30", - "DSP_IMUX4_3", - "DSP_IMUX37_4", - "DSP_0_ACIN28", - "DSP_1_PCIN10", - "DSP_SW2A0_3", - "DSP_EE4A0_4", - "DSP_IMUX6_1", - "DSP_1_CEM", - "DSP_IMUX11_3", - "DSP_IMUX43_4", - "DSP_LOGIC_OUTS_B20_2", - "DSP_0_PCIN44", - "DSP_1_P28", - "DSP_0_PCIN45", - "DSP_1_D7", - "DSP_WW4B1_2", - "DSP_EE4B0_2", - "DSP_IMUX8_1", - "DSP_0_C39", - "DSP_IMUX2_4", - "DSP_WR1END3_0", - "DSP_NW4END3_0", - "DSP_1_C26", - "DSP_BYP6_1", - "DSP_EE4B3_3", - "DSP_NE4BEG0_1", - "DSP_LOGIC_OUTS_B15_3", - "DSP_1_PCIN30", - "DSP_SW4A1_1", - "DSP_1_PCIN43", - "DSP_ER1BEG0_3", - "DSP_0_RSTCTRL", - "DSP_0_P41", - "DSP_1_A17", - "DSP_0_A26", - "DSP_LOGIC_OUTS_B20_1", - "DSP_PCOUT8", - "DSP_1_RSTD", - "DSP_NW2A2_2", - "DSP_IMUX30_1", - "DSP_NW4END0_0", - "DSP_IMUX44_0", - "DSP_1_D12", - "DSP_0_CEM", - "DSP_WW4C1_4", - "DSP_NW4A0_0", - "DSP_NW4END3_4", - "DSP_0_ALUMODE3", - "DSP_FAN5_3", - "DSP_ACOUT6", - "DSP_BYP5_4", - "DSP_LOGIC_OUTS_B2_0", + "DSP_1_PCOUT16", + "DSP_1_BCIN6", + "DSP_1_PCOUT4", + "DSP_FAN2_1", + "DSP_FAN3_3", "DSP_1_PCIN9", - "DSP_0_PCIN29", - "DSP_0_BCIN5", - "DSP_0_PCIN32", - "DSP_PCOUT33", - "DSP_PCOUT47", + "DSP_0_PCIN23", + "DSP_IMUX28_4", + "DSP_1_PCIN25", + "DSP_EE4BEG3_1", + "DSP_LH5_3", + "DSP_IMUX45_0", + "DSP_0_C16", + "DSP_BYP0_2", + "DSP_1_CARRYCASCOUT", + "DSP_BYP5_0", + "DSP_1_RSTM", + "DSP_LH7_1", + "DSP_LOGIC_OUTS_B14_0", + "DSP_0_CARRYCASCIN", + "DSP_LOGIC_OUTS_B18_2", + "DSP_BLOCK_OUTS_B0_4", + "DSP_IMUX11_0", + "DSP_0_PCIN34", + "DSP_0_RSTM", + "DSP_EE4A2_2", + "DSP_IMUX2_3", + "DSP_0_A13", + "DSP_0_ACOUT12", + "DSP_0_PCOUT20", + "DSP_BYP2_1", + "DSP_0_ACIN20", + "DSP_EL1BEG3_2", + "DSP_1_B11", + "DSP_WW4END3_3", + "DSP_NW4END0_0", + "DSP_SE4C1_4", "DSP_0_B5", - "DSP_EE4BEG2_0", - "DSP_WL1END0_0", - "DSP_SE2A0_1", + "DSP_WW4END1_2", + "DSP_ACOUT6", + "DSP_1_PCOUT43", + "DSP_NE4BEG1_2", + "DSP_1_C16", + "DSP_WW4C2_2", + "DSP_IMUX6_0", + "DSP_WW2A3_1", + "DSP_LOGIC_OUTS_B12_0", + "DSP_0_PCOUT8", + "DSP_SE4C3_1", + "DSP_IMUX34_0", + "DSP_1_P9", + "DSP_1_B8", + "DSP_IMUX27_0", + "DSP_WW4C2_3", + "DSP_1_C20", + "DSP_NE2A2_2", + "DSP_LH7_0", + "DSP_0_B16", + "DSP_0_B0", + "DSP_1_PCIN41", + "DSP_0_A27", + "DSP_NE4BEG2_2", + "DSP_WW4B2_4", + "DSP_BCOUT14", + "DSP_LH8_3", + "DSP_EE2BEG2_3", + "DSP_NE4C2_1", + "DSP_LH4_1", + "DSP_SE2A1_3", + "DSP_0_D21", + "DSP_0_PCOUT45", + "DSP_1_ACOUT15", + "DSP_1_INMODE0", + "DSP_PCOUT38", + "DSP_EE4BEG0_4", + "DSP_0_PCIN35", + "DSP_IMUX35_1", + "DSP_0_ACOUT10", + "DSP_0_A22", + "DSP_WW4C3_1", + "DSP_SE4BEG3_3", + "DSP_IMUX23_3", + "DSP_1_A11", + "DSP_NW4A2_4", + "DSP_1_BCIN16", + "DSP_0_ACIN27", + "DSP_0_RSTALLCARRYIN", + "DSP_1_OPMODE1", + "DSP_ACOUT26", + "DSP_LOGIC_OUTS_B8_0", + "DSP_0_RSTB", + "DSP_0_BCIN11", + "DSP_IMUX20_0", + "DSP_WW4END0_3", + "DSP_0_PCIN28", + "DSP_WW4B0_0", + "DSP_EE4A2_3", + "DSP_IMUX17_4", + "DSP_1_ACOUT9", + "DSP_0_PCOUT17", + "DSP_0_C22", + "DSP_WW4B2_1", + "DSP_EE2BEG1_0", + "DSP_1_CEA1", + "DSP_IMUX24_0", + "DSP_LH6_2", + "DSP_0_MULTSIGNOUT", + "DSP_0_A18", + "DSP_IMUX36_4", + "DSP_1_BCIN11", + "DSP_0_C36", + "DSP_PCOUT12", + "DSP_SE4BEG1_3", + "DSP_0_PCOUT35", + "DSP_LOGIC_OUTS_B12_1", + "DSP_LOGIC_OUTS_B17_4", + "DSP_LH11_0", + "DSP_WL1END1_1", + "DSP_0_C25", + "DSP_EE4B0_4", + "DSP_NW2A2_4", + "DSP_0_C44", + "DSP_ACOUT0", + "DSP_BLOCK_OUTS_B1_3", + "DSP_IMUX16_1", + "DSP_BLOCK_OUTS_B3_3", + "DSP_1_PCOUT7", + "DSP_EL1BEG1_3", + "DSP_0_PCOUT22", + "DSP_EE2BEG2_0", + "DSP_SW4END1_3", + "DSP_FAN7_3", + "DSP_0_D23", + "DSP_1_CARRYCASCIN", + "DSP_1_CLK", + "DSP_WW4A2_1", + "DSP_LH12_2", + "DSP_BYP7_4", + "DSP_0_BCIN17", + "DSP_IMUX30_2", + "DSP_BYP0_3", + "DSP_NE2A3_0", + "DSP_0_RSTA", + "DSP_0_PCOUT0", + "DSP_EE2A3_2", + "DSP_IMUX21_4", + "DSP_WL1END0_2", + "DSP_WW2END2_4", + "DSP_1_PCIN17", + "DSP_IMUX25_4", + "DSP_SW2A3_2", + "DSP_SE4C0_0", + "DSP_EE4A0_2", + "DSP_1_P22", + "DSP_IMUX0_0", + "DSP_NW4END1_3", + "DSP_BYP7_0", + "DSP_0_PCOUT16", + "DSP_1_ACIN19", + "DSP_1_BCOUT16", + "DSP_IMUX43_2", + "DSP_1_P36", + "DSP_IMUX39_1", + "DSP_WW4END0_4", + "DSP_IMUX32_4", + "DSP_1_PCIN6", + "DSP_FAN1_2", + "DSP_NW4END1_4", + "DSP_IMUX26_1", + "DSP_EE4A1_0", + "DSP_SE4C0_2", + "DSP_SE4C1_2", + "DSP_EE2A3_0", + "DSP_IMUX3_3", + "DSP_WW4C1_0", + "DSP_SW4A2_0", + "DSP_ER1BEG3_3", + "DSP_SE4C1_0", + "DSP_SW2A1_0", + "DSP_0_P5", + "DSP_0_P27", + "DSP_ACOUT10", + "DSP_WW4C1_2", + "DSP_0_OPMODE3", + "DSP_LOGIC_OUTS_B21_3", + "DSP_0_P7", + "DSP_NW4A2_3", + "DSP_ACOUT23", + "DSP_0_D19", + "DSP_1_C14", + "DSP_WW2END1_1", + "DSP_1_P10", + "DSP_IMUX24_2", + "DSP_SE4C1_3", + "DSP_FAN7_2", + "DSP_0_C11", + "DSP_0_PCOUT15", + "DSP_0_ACOUT4", + "DSP_EE2A2_2", + "DSP_EL1BEG1_0", + "DSP_0_PCIN15", + "DSP_1_ACIN10", + "DSP_WW4C1_3", + "DSP_0_D14", + "DSP_0_ACIN13", + "DSP_0_B15", + "DSP_LH6_3", + "DSP_WW2END2_0", + "DSP_NE2A1_4", + "DSP_WW4C0_3", + "DSP_1_PCOUT33", + "DSP_1_ACOUT3", + "DSP_1_ACOUT21", + "DSP_PCOUT13", + "DSP_0_PCOUT31", + "DSP_1_PCIN10", + "DSP_0_PCOUT10", + "DSP_WR1END3_4", + "DSP_1_C15", + "DSP_1_ACIN3", + "DSP_0_A1", + "DSP_LH1_0", + "DSP_IMUX15_0", + "DSP_NW2A3_1", + "DSP_IMUX44_3", + "DSP_IMUX31_4", + "DSP_ER1BEG0_4", + "DSP_WW2A1_4", + "DSP_0_BCOUT15", + "DSP_EE2A2_3", + "DSP_SW4END2_1", + "DSP_WR1END3_3", + "DSP_1_ALUMODE3", + "DSP_1_ACOUT19", + "DSP_PCOUT42", + "DSP_LOGIC_OUTS_B14_1", + "DSP_LH6_4", + "DSP_SW4A2_2", + "DSP_BYP6_1", + "DSP_1_C39", + "DSP_EE4A1_1", + "DSP_NE4BEG3_1", + "DSP_IMUX13_1", + "DSP_EE4B1_4", + "DSP_NW2A2_2", + "DSP_0_P17", + "DSP_CLK0_2", + "DSP_LOGIC_OUTS_B22_2", + "DSP_1_P44", + "DSP_EE2BEG0_4", + "DSP_NE2A1_1", + "DSP_1_B4", + "DSP_0_A2", + "DSP_1_PCIN24", + "DSP_0_ACIN1", + "DSP_LOGIC_OUTS_B21_2", + "DSP_EE4A2_0", + "DSP_SW2A3_3", + "DSP_PCOUT15", + "DSP_LOGIC_OUTS_B20_1", + "DSP_1_C28", + "DSP_SW2A0_4", + "DSP_0_P8", + "DSP_0_ALUMODE3", + "DSP_IMUX8_3", + "DSP_BYP5_4", + "DSP_0_P9", + "DSP_0_BCIN14", + "DSP_WR1END1_2", + "DSP_1_P45", + "DSP_WW4B2_3", + "DSP_0_D5", + "DSP_WR1END2_3", + "DSP_1_ACOUT29", + "DSP_FAN4_1", + "DSP_1_ACIN14", + "DSP_0_D13", + "DSP_BCOUT8", + "DSP_1_C11", + "DSP_1_PCIN15", + "DSP_0_D24", + "DSP_0_C39", + "DSP_SE4BEG2_4", + "DSP_CLK1_0", + "DSP_WR1END1_0", + "DSP_BYP1_1", + "DSP_0_ACIN8", + "DSP_1_ACOUT2", + "DSP_BCOUT0", + "DSP_NE4C3_0", + "DSP_PCOUT19", + "DSP_FAN3_2", + "DSP_1_PCIN37", + "DSP_WW4END1_4", + "DSP_IMUX13_3", + "DSP_1_BCOUT14", + "DSP_LOGIC_OUTS_B3_0", + "DSP_FAN2_0", + "DSP_IMUX15_2", + "DSP_0_PCIN11", + "DSP_1_A10", + "DSP_BCOUT1", + "DSP_0_PATTERNDETECT", + "DSP_0_PCOUT34", + "DSP_IMUX11_2", + "DSP_0_PCIN12", + "DSP_WW2A1_0", + "DSP_1_OPMODE2", + "DSP_BCOUT12", + "DSP_SW4A0_4", + "DSP_1_RSTC", + "DSP_LOGIC_OUTS_B10_1", + "DSP_1_ACIN22", + "DSP_EE2BEG1_2", + "DSP_0_P6", + "DSP_EE4B1_3", + "DSP_LOGIC_OUTS_B11_1", + "DSP_ER1BEG0_3", + "DSP_IMUX12_1", + "DSP_1_P7", + "DSP_IMUX10_1", + "DSP_IMUX0_1", + "DSP_1_PCOUT8", + "DSP_WW2A2_4", + "DSP_LH3_4", + "DSP_1_CARRYOUT3", + "DSP_NE2A2_4", + "DSP_0_CARRYINSEL0", + "DSP_1_A14", + "DSP_ACOUT2", + "DSP_LOGIC_OUTS_B19_1", + "DSP_BYP6_2", + "DSP_SE2A2_0", + "DSP_NW2A3_0", + "DSP_0_C43", + "DSP_EE4A0_3", + "DSP_1_C35", + "DSP_IMUX5_3", + "DSP_EE4C3_2", + "DSP_IMUX22_4", + "DSP_1_P8", + "DSP_NE4BEG2_4", + "DSP_0_PCIN17", + "DSP_0_D12", + "DSP_WL1END1_4", + "DSP_BYP1_0", + "DSP_EE4C3_0", + "DSP_IMUX20_4", + "DSP_1_P11", + "DSP_0_A0", + "DSP_EE4BEG2_3", + "DSP_1_B12", + "DSP_LOGIC_OUTS_B18_4", + "DSP_NE4C0_4", + "DSP_0_PCOUT33", + "DSP_1_PCIN42", + "DSP_0_PCOUT46", + "DSP_1_PCIN2", + "DSP_1_A8", + "DSP_IMUX22_0", + "DSP_BYP0_1", + "DSP_WW4A0_4", + "DSP_IMUX20_2", + "DSP_0_C32", + "DSP_IMUX1_1", + "DSP_1_CARRYINSEL0", + "DSP_IMUX26_0", + "DSP_0_PCOUT19", + "DSP_0_B7", + "DSP_1_P43", + "DSP_1_D14", + "DSP_1_OPMODE3", + "DSP_EE4A3_1", + "DSP_SE4BEG2_3", + "DSP_SE4BEG1_4", + "DSP_1_A27", + "DSP_IMUX11_1", + "DSP_LOGIC_OUTS_B11_0", + "DSP_1_D9", + "DSP_1_C10", + "DSP_IMUX2_0", + "DSP_SW4END0_2", + "DSP_1_A4", + "DSP_WL1END2_1", + "DSP_0_PCOUT44", + "DSP_0_OPMODE2", + "DSP_EE2A1_1", + "DSP_LH3_1", + "DSP_0_C30", + "DSP_LOGIC_OUTS_B9_3", + "DSP_1_PCOUT1", + "DSP_1_C31", + "DSP_LH5_1", + "DSP_LOGIC_OUTS_B15_4", + "DSP_LH3_2", + "DSP_NW4END2_0", + "DSP_0_BCOUT4", + "DSP_WW4END2_0", + "DSP_BYP4_0", + "DSP_1_CARRYOUT1", + "DSP_LOGIC_OUTS_B11_3", + "DSP_0_PCOUT14", + "DSP_SE4C2_0", + "DSP_0_C35", + "DSP_1_ACIN6", + "DSP_EE2BEG3_0", + "DSP_IMUX31_2", + "DSP_1_ACIN26", + "DSP_0_PCIN25", + "DSP_IMUX15_1", + "DSP_1_ACIN0", + "DSP_IMUX13_4", + "DSP_0_PCIN27", + "DSP_NW4END2_4", + "DSP_0_ACOUT18", + "DSP_0_INMODE1", + "DSP_0_ACIN29", + "DSP_EL1BEG3_1", + "DSP_EE4BEG0_3", + "DSP_NE4C0_0", + "DSP_1_ACIN27", + "DSP_0_CEB1", + "DSP_EL1BEG3_4", + "DSP_IMUX17_3", + "DSP_1_OPMODE6", + "DSP_ER1BEG2_3", + "DSP_BCOUT7", + "DSP_SE2A1_1", + "DSP_0_OPMODE6", + "DSP_EL1BEG2_3", + "DSP_1_ALUMODE1", + "DSP_IMUX38_4", + "DSP_SE4BEG0_3", + "DSP_1_P34", + "DSP_1_P29", + "DSP_IMUX7_0", + "DSP_0_CARRYOUT3", + "DSP_IMUX26_4", + "DSP_LOGIC_OUTS_B16_1", + "DSP_LOGIC_OUTS_B4_2", + "DSP_1_ACOUT12", + "DSP_EL1BEG1_4", + "DSP_WW2END3_0", + "DSP_IMUX38_2", + "DSP_LH9_1", + "DSP_EL1BEG0_3", + "DSP_IMUX44_2", + "DSP_IMUX16_0", + "DSP_NW4END1_2", + "DSP_1_MULTSIGNOUT", + "DSP_ACOUT28", + "DSP_LH11_3", + "DSP_1_PCOUT38", + "DSP_EE4BEG3_0", + "DSP_NE4BEG2_3", + "DSP_1_PCOUT37", + "DSP_ACOUT24", + "DSP_PCOUT29", + "DSP_NW4A2_0", + "DSP_IMUX17_1", + "DSP_0_PCIN1", + "DSP_0_PCOUT24", + "DSP_LH8_0", + "DSP_1_P20", + "DSP_MONITOR_P_2", + "DSP_0_C5", + "DSP_WW2A2_2", + "DSP_WW2END2_2", + "DSP_0_PCOUT25", + "DSP_WR1END0_4", + "DSP_LH3_3", + "DSP_EE4C2_0", + "DSP_EL1BEG3_3", + "DSP_0_PCIN8", + "DSP_SW4A1_3", + "DSP_0_PCOUT29", + "DSP_IMUX29_0", + "DSP_1_C9", + "DSP_0_RSTCTRL", + "DSP_LOGIC_OUTS_B16_4", + "DSP_1_ACIN25", + "DSP_0_P35", + "DSP_1_CARRYOUT0", + "DSP_1_PCIN1", + "DSP_1_ACOUT17", + "DSP_BYP1_2", + "DSP_1_ACOUT28", + "DSP_CLK0_0", + "DSP_LH4_3", + "DSP_LOGIC_OUTS_B17_3", + "DSP_0_C47", + "DSP_0_D2", + "DSP_NE2A0_3", + "DSP_WW2END2_1", + "DSP_1_BCOUT0", + "DSP_LOGIC_OUTS_B5_0", + "DSP_1_A29", + "DSP_0_P15", + "DSP_SE2A2_3", + "DSP_IMUX9_0", + "DSP_0_PCOUT21", + "DSP_LOGIC_OUTS_B11_2", + "DSP_ACOUT11", + "DSP_1_C34", + "DSP_0_D11", + "DSP_0_C20", + "DSP_1_BCIN4", + "DSP_LH12_4", + "DSP_IMUX21_1", + "DSP_EE2BEG0_2", + "DSP_1_PCOUT15", + "DSP_0_PCOUT13", + "DSP_CLK1_4", + "DSP_MONITOR_P_0", + "DSP_PCOUT28", + "DSP_0_PCOUT12", + "DSP_ACOUT18", + "DSP_EE4A0_0", + "DSP_WL1END1_3", + "DSP_ER1BEG3_0", + "DSP_MULTSIGNOUT", + "DSP_1_ACIN23", + "DSP_PCOUT6", + "DSP_IMUX5_2", + "DSP_1_P15", + "DSP_IMUX29_4", + "DSP_1_PCOUT12", + "DSP_1_CARRYIN", + "DSP_NE4C0_3", + "DSP_IMUX40_1", + "DSP_IMUX30_3", + "DSP_1_D13", + "DSP_1_PCOUT10", + "DSP_IMUX2_4", + "DSP_0_ACIN23", + "DSP_BYP2_3", + "DSP_1_C18", + "DSP_0_CARRYINSEL1", + "DSP_LOGIC_OUTS_B21_0", + "DSP_0_BCOUT12", + "DSP_WW4B1_4", + "DSP_0_PCIN41", + "DSP_IMUX3_1", + "DSP_0_PCIN21", + "DSP_LH2_1", + "DSP_1_PCIN38", + "DSP_BLOCK_OUTS_B3_4", + "DSP_LOGIC_OUTS_B22_4", + "DSP_1_PCOUT35", + "DSP_LH1_1", + "DSP_1_INMODE1", + "DSP_NE4C1_1", + "DSP_0_P43", + "DSP_1_PCIN46", + "DSP_WW2END0_2", + "DSP_0_BCOUT9", + "DSP_PCOUT37", + "DSP_IMUX46_4", + "DSP_0_PCIN46", + "DSP_1_PCIN45", "DSP_0_PCOUT38", + "DSP_0_D9", + "DSP_1_B15", + "DSP_EE4B0_0", + "DSP_NW4A1_0", + "DSP_BCOUT15", + "DSP_IMUX41_0", + "DSP_1_PCOUT22", + "DSP_SW4A0_3", + "DSP_SW4END3_1", + "DSP_IMUX0_4", + "DSP_IMUX24_3", + "DSP_0_UNDERFLOW", + "DSP_0_ACOUT24", + "DSP_SE4BEG3_4", + "DSP_NW4A2_1", + "DSP_0_CEA1", + "DSP_LOGIC_OUTS_B6_3", + "DSP_IMUX4_0", + "DSP_SW4A3_3", + "DSP_0_B8", + "DSP_EE2A0_1", + "DSP_IMUX1_0", + "DSP_1_ACOUT6", + "DSP_LOGIC_OUTS_B6_4", + "DSP_CTRL0_0", + "DSP_WW2A3_0", + "DSP_EE4C2_3", + "DSP_1_ACIN18", + "DSP_NW4A0_3", + "DSP_LH7_3", + "DSP_1_BCOUT10", + "DSP_0_ACIN22", + "DSP_WW4B0_3", + "DSP_0_D6", + "DSP_1_CEM", + "DSP_1_A2", + "DSP_1_CEC", + "DSP_NE4C3_2", + "DSP_1_PCOUT5", + "DSP_1_PCIN31", + "DSP_0_D8", + "DSP_EL1BEG0_4", + "DSP_IMUX25_2", + "DSP_1_BCOUT17", + "DSP_0_P4", + "DSP_EL1BEG0_0", + "DSP_0_CEA2", + "DSP_1_PCOUT11", + "DSP_IMUX32_0", + "DSP_1_PCOUT31", + "DSP_1_PCIN35", + "DSP_1_D22", + "DSP_0_C4", + "DSP_CTRL0_2", + "DSP_LH8_1", + "DSP_1_D0", + "DSP_1_ACIN17", + "DSP_0_B1", + "DSP_1_BCIN3", + "DSP_EE4B1_2", + "DSP_WW4C3_3", + "DSP_BYP7_3", + "DSP_0_ACOUT6", + "DSP_SW4END2_2", + "DSP_BYP6_3", + "DSP_BLOCK_OUTS_B1_0", + "DSP_IMUX14_4", + "DSP_NE4C1_2", + "DSP_IMUX18_0", + "DSP_0_A5", + "DSP_0_C0", + "DSP_BYP3_0", + "DSP_PCOUT23", + "DSP_1_BCOUT9", + "DSP_1_RSTP", + "DSP_0_PCIN30", + "DSP_1_C23", + "DSP_PCOUT8", + "DSP_MONITOR_N_0", + "DSP_1_P0", + "DSP_0_P31", + "DSP_SE2A3_0", + "DSP_WR1END0_2", + "DSP_0_C14", + "DSP_0_C27", + "DSP_0_A7", + "DSP_IMUX18_3", + "DSP_ACOUT29", + "DSP_1_A5", + "DSP_1_P3", + "DSP_0_D20", + "DSP_IMUX19_2", + "DSP_SE4BEG1_0", + "DSP_0_A20", + "DSP_NE4C1_4", + "DSP_BYP3_4", + "DSP_1_A25", + "DSP_IMUX28_0", + "DSP_0_CEP", + "DSP_IMUX33_0", + "DSP_LOGIC_OUTS_B19_0", + "DSP_NW4A0_0", + "DSP_WL1END1_0", + "DSP_EE4C0_2", + "DSP_ER1BEG2_1", + "DSP_SE4BEG2_2", + "DSP_IMUX9_4", + "DSP_IMUX4_1", + "DSP_IMUX6_4", + "DSP_WW2A3_2", + "DSP_LOGIC_OUTS_B19_2", + "DSP_EE4BEG3_2", + "DSP_EE4B0_1", + "DSP_EE4C0_0", + "DSP_IMUX8_2", + "DSP_EL1BEG2_0", + "DSP_SE4C2_3", + "DSP_0_ACOUT26", + "DSP_NE4BEG1_0", + "DSP_WL1END3_1", + "DSP_SE2A1_2", + "DSP_1_D21", + "DSP_PCOUT43", + "DSP_LOGIC_OUTS_B13_2", + "DSP_1_P24", + "DSP_1_P41", + "DSP_SE4C2_1", + "DSP_SW4A3_4", + "DSP_SW4END2_3", + "DSP_0_PCIN42", + "DSP_ER1BEG2_2", + "DSP_CTRL0_4", + "DSP_1_PCOUT41", + "DSP_0_ACOUT27", + "DSP_SE4C2_4", + "DSP_FAN1_3", + "DSP_1_CECARRYIN", + "DSP_0_CARRYOUT2", + "DSP_ER1BEG2_4", + "DSP_0_ACIN7", + "DSP_IMUX36_0", + "DSP_IMUX34_3", + "DSP_1_BCOUT1", + "DSP_0_RSTP", + "DSP_IMUX18_1", + "DSP_PCOUT30", + "DSP_LH9_4", + "DSP_1_CEB2", + "DSP_SW2A0_1", + "DSP_0_C24", + "DSP_NE4C2_3", + "DSP_0_INMODE0", + "DSP_PCOUT3", + "DSP_IMUX37_1", + "DSP_IMUX27_2", + "DSP_NW4END3_0", + "DSP_WW4END2_3", + "DSP_BCOUT11", + "DSP_MONITOR_N_3", + "DSP_0_P3", + "DSP_EE2BEG3_4", + "DSP_LOGIC_OUTS_B9_4", + "DSP_1_ACIN4", + "DSP_SW4A3_2", + "DSP_IMUX40_0", + "DSP_1_A16", + "DSP_0_ACOUT22", + "DSP_SW4END3_0", + "DSP_0_PCOUT40", + "DSP_0_D1", + "DSP_IMUX37_4", + "DSP_BCOUT10", + "DSP_0_ACOUT29", + "DSP_1_B2", + "DSP_EE4C3_4", + "DSP_1_BCIN14", + "DSP_SW2A2_2", + "DSP_SW4A2_3", + "DSP_1_BCIN1", + "DSP_0_D16", + "DSP_SW4END3_2", + "DSP_IMUX17_2", + "DSP_FAN1_1", + "DSP_0_P29", + "DSP_0_PCIN4", + "DSP_1_A23", + "DSP_PCOUT21", + "DSP_IMUX47_4", + "DSP_EE4A2_4", + "DSP_1_A3", + "DSP_BYP1_4", + "DSP_NW4A1_2", + "DSP_WW4END0_1", + "DSP_EE2A1_3", + "DSP_BYP4_1", + "DSP_SE2A1_0", + "DSP_1_D1", + "DSP_0_D7", + "DSP_0_PCIN5", + "DSP_1_PCIN0", + "DSP_1_BCOUT15", + "DSP_IMUX43_1", + "DSP_1_OPMODE0", + "DSP_LOGIC_OUTS_B16_2", + "DSP_IMUX33_3", + "DSP_0_B9", + "DSP_IMUX42_0", + "DSP_ER1BEG0_0", + "DSP_0_D4", + "DSP_LH6_0", + "DSP_BLOCK_OUTS_B2_4", + "DSP_EE4A3_2", + "DSP_0_ACIN3", + "DSP_LOGIC_OUTS_B0_0", + "DSP_PCOUT14", + "DSP_PCOUT10", + "DSP_0_PCIN44", + "DSP_SE4BEG2_1", + "DSP_0_PCOUT41", + "DSP_0_PCIN38", + "DSP_1_PCOUT27", + "DSP_BLOCK_OUTS_B2_1", + "DSP_1_PCIN3", + "DSP_FAN6_2", + "DSP_1_ACOUT20", + "DSP_0_P37", + "DSP_IMUX44_0", + "DSP_0_P26", + "DSP_1_C1", + "DSP_0_CECARRYIN", + "DSP_EL1BEG1_2", + "DSP_BCOUT3", + "DSP_IMUX20_1", + "DSP_WW4END2_1", + "DSP_NE2A3_4", + "DSP_MONITOR_N_2", + "DSP_0_ACIN10", + "DSP_FAN6_4", + "DSP_NE4BEG0_4", + "DSP_1_D6", + "DSP_0_PCOUT28", + "DSP_EL1BEG2_2", + "DSP_WW4C1_1", + "DSP_LOGIC_OUTS_B20_0", + "DSP_PCOUT27", + "DSP_1_C19", + "DSP_1_ACOUT25", + "DSP_1_PCOUT3", + "DSP_IMUX3_2", + "DSP_FAN3_4", + "DSP_WW4A1_1", + "DSP_FAN0_4", + "DSP_0_ACIN9", + "DSP_EE4A2_1", + "DSP_1_PCIN20", + "DSP_NE4BEG1_1", + "DSP_LOGIC_OUTS_B20_2", + "DSP_WW2END0_0", + "DSP_0_PCOUT11", + "DSP_IMUX22_3", + "DSP_NE4C3_1", + "DSP_1_A28", + "DSP_WW4C2_0", + "DSP_CTRL1_4", + "DSP_1_PCIN39", + "DSP_FAN7_0", + "DSP_EE4C3_1", + "DSP_1_C40", + "DSP_IMUX4_4", + "DSP_0_C19", + "DSP_IMUX38_0", + "DSP_IMUX12_2", + "DSP_0_C1", + "DSP_LOGIC_OUTS_B23_2", + "DSP_FAN6_0", + "DSP_0_B13", + "DSP_EE4C0_3", + "DSP_0_ACIN16", + "DSP_0_PCIN36", + "DSP_IMUX30_0", + "DSP_SW4A3_1", + "DSP_1_PCIN30", + "DSP_PCOUT24", + "DSP_0_PCIN40", + "DSP_SW4A1_0", + "DSP_0_C12", + "DSP_BYP3_1", + "DSP_IMUX31_3", + "DSP_BLOCK_OUTS_B1_1", + "DSP_EE2BEG1_1", + "DSP_LH3_0", + "DSP_LOGIC_OUTS_B2_4", + "DSP_BCOUT5", + "DSP_1_PCOUT47", + "DSP_0_ACOUT15", + "DSP_1_PCIN23", + "DSP_WW2A0_2", + "DSP_1_ALUMODE2", + "DSP_1_D5", + "DSP_IMUX3_0", + "DSP_LOGIC_OUTS_B11_4", + "DSP_WL1END3_4", + "DSP_1_BCOUT12", + "DSP_IMUX2_1", + "DSP_PCOUT46", + "DSP_0_RSTC", + "DSP_IMUX41_1", + "DSP_LH2_4", + "DSP_WW2END1_0", + "DSP_WW4A3_4", + "DSP_WL1END3_3", + "DSP_IMUX9_1", + "DSP_0_PCOUT37", + "DSP_LOGIC_OUTS_B16_0", + "DSP_1_BCOUT11", + "DSP_NE4C1_3", + "DSP_ACOUT27", + "DSP_1_RSTALUMODE", "DSP_1_OPMODE5", + "DSP_0_BCIN8", + "DSP_0_CEC", + "DSP_0_D18", + "DSP_0_A9", + "DSP_0_BCOUT16", + "DSP_1_INMODE4", + "DSP_LH8_4", + "DSP_0_CED", + "DSP_LOGIC_OUTS_B22_0", + "DSP_1_D4", + "DSP_1_CEAD", + "DSP_BYP1_3", + "DSP_1_BCIN2", + "DSP_0_P38", + "DSP_0_C33", + "DSP_1_ACIN12", + "DSP_1_P28", + "DSP_0_PCIN29", + "DSP_SW2A1_1", + "DSP_1_A9", + "DSP_LOGIC_OUTS_B16_3", + "DSP_1_C2", + "DSP_ACOUT7", + "DSP_WW4C1_4", + "DSP_0_BCOUT7", + "DSP_EE2BEG2_1", + "DSP_SE4BEG2_0", + "DSP_BLOCK_OUTS_B3_0", + "DSP_PCOUT34", + "DSP_EE4B3_0", + "DSP_WW4B3_1", + "DSP_EE4B1_0", + "DSP_EE2BEG1_4", + "DSP_FAN2_3", + "DSP_WW4B3_3", + "DSP_WR1END1_1", + "DSP_LOGIC_OUTS_B5_3", + "DSP_NW4END0_4", + "DSP_0_OPMODE1", + "DSP_LH8_2", + "DSP_LH5_4", + "DSP_0_OPMODE0", + "DSP_LOGIC_OUTS_B0_4", + "DSP_NW4END3_3", + "DSP_1_C36", + "DSP_1_P6", + "DSP_NW4A3_3", + "DSP_1_P2", + "DSP_WL1END3_2", + "DSP_1_ACIN1", + "DSP_0_PCIN33", + "DSP_0_ACIN11", + "DSP_0_P25", + "DSP_0_INMODE2", + "DSP_0_BCIN2", + "DSP_ER1BEG1_4", + "DSP_0_CEINMODE", + "DSP_WL1END2_3", + "DSP_WW2END2_3", + "DSP_SW2A0_2", + "DSP_0_BCIN12", + "DSP_LH10_2", + "DSP_0_ACIN2", + "DSP_1_B9", + "DSP_0_ACOUT5", + "DSP_NW4END2_3", + "DSP_0_PCOUT27", + "DSP_IMUX14_2", + "DSP_WW4A3_0", + "DSP_1_PCOUT13", + "DSP_1_D20", + "DSP_FAN1_4", + "DSP_1_CEALUMODE", + "DSP_BCOUT6", + "DSP_IMUX5_0", + "DSP_1_D7", + "DSP_IMUX29_2", + "DSP_LH9_3", + "DSP_ACOUT17", + "DSP_NE4C2_4", + "DSP_1_P30", + "DSP_1_CEA2", + "DSP_IMUX33_2", + "DSP_1_P38", + "DSP_WL1END2_4", + "DSP_0_C10", + "DSP_0_P13", + "DSP_0_C2", + "DSP_LH10_1", + "DSP_1_C38", + "DSP_0_ALUMODE2", + "DSP_EE2A2_1", + "DSP_SE2A3_4", + "DSP_LOGIC_OUTS_B2_1", + "DSP_1_D19", + "DSP_1_C7", + "DSP_1_P12", + "DSP_0_BCOUT14", + "DSP_IMUX32_1", + "DSP_1_ACOUT5", + "DSP_SW4END3_3", + "DSP_IMUX31_0", + "DSP_1_PCIN22", + "DSP_1_B5", + "DSP_1_P32", + "DSP_BYP5_2", + "DSP_1_C17", + "DSP_0_P16", + "DSP_IMUX19_4", + "DSP_PCOUT39", + "DSP_FAN7_1", + "DSP_LOGIC_OUTS_B13_3", + "DSP_1_RSTD", + "DSP_WW4B3_2", + "DSP_WW4C0_1", + "DSP_0_PCIN13", + "DSP_LOGIC_OUTS_B7_0", + "DSP_IMUX28_2", + "DSP_0_PCOUT43", + "DSP_0_ACOUT8", + "DSP_NW4A0_2", + "DSP_SE2A2_4", + "DSP_1_C33", + "DSP_1_P5", + "DSP_NW4END2_2", + "DSP_LOGIC_OUTS_B3_2", + "DSP_1_ACOUT22", + "DSP_MONITOR_P_4", + "DSP_NE2A2_3", + "DSP_0_P47", + "DSP_IMUX6_3", + "DSP_0_CARRYINSEL2", + "DSP_0_A25", + "DSP_LH9_2", + "DSP_1_PCIN27", + "DSP_IMUX34_4", + "DSP_IMUX10_0", + "DSP_0_PCOUT30", + "DSP_IMUX25_1", + "DSP_0_P18", + "DSP_1_PCIN26", + "DSP_1_A13", + "DSP_1_ACOUT24", + "DSP_1_BCIN7", + "DSP_WW4B3_0", + "DSP_NE2A3_1", + "DSP_WW4C2_4", + "DSP_IMUX47_1", + "DSP_IMUX29_1", + "DSP_0_A6", + "DSP_1_PCIN5", + "DSP_LOGIC_OUTS_B23_4", + "DSP_1_PCOUT26", + "DSP_0_A8", + "DSP_0_B14", + "DSP_0_P2", + "DSP_EE4A3_3", + "DSP_IMUX8_0", + "DSP_0_PCOUT6", + "DSP_LOGIC_OUTS_B4_1", + "DSP_1_C47", + "DSP_ACOUT5", + "DSP_SW4A3_0", + "DSP_NE2A1_3", + "DSP_SW4END0_4", + "DSP_0_PCOUT23", + "DSP_BYP4_2", + "DSP_WL1END1_2", + "DSP_1_RSTB", + "DSP_0_BCIN0", + "DSP_EE4A1_2", + "DSP_1_CEB1", + "DSP_SW4END0_3", + "DSP_1_PCIN28", + "DSP_1_P25", + "DSP_IMUX23_1", + "DSP_1_PCOUT2", + "DSP_0_BCOUT17", + "DSP_WW4B0_2", + "DSP_0_P46", + "DSP_0_A17", + "DSP_ACOUT8", + "DSP_1_P23", + "DSP_0_P40", + "DSP_0_ACOUT17", + "DSP_1_C27", + "DSP_1_C24", + "DSP_NW2A3_3", + "DSP_EE2A2_0", + "DSP_WW4A1_4", + "DSP_1_ACOUT27", + "DSP_LOGIC_OUTS_B3_3", + "DSP_NE2A2_1", + "DSP_SE2A0_0", + "DSP_FAN0_2", + "DSP_PCOUT33", + "DSP_0_PCIN45", + "DSP_0_ACOUT25", + "DSP_BYP2_0", + "DSP_LOGIC_OUTS_B2_2", + "DSP_0_RSTD", + "DSP_0_C17", + "DSP_IMUX28_3", + "DSP_LH4_2", + "DSP_LOGIC_OUTS_B0_1", + "DSP_IMUX1_2", + "DSP_SE4C3_2", + "DSP_1_PCIN34", + "DSP_1_C30", + "DSP_IMUX1_3", + "DSP_1_D16", + "DSP_IMUX4_3", + "DSP_0_ACOUT1", + "DSP_BCOUT16", + "DSP_NW2A1_1", + "DSP_1_D15", + "DSP_EE4B2_0", + "DSP_WW4END3_2", + "DSP_0_ACIN25", + "DSP_1_PCIN33", + "DSP_0_C37", + "DSP_0_BCOUT13", + "DSP_0_INMODE3", + "DSP_WR1END1_3", + "DSP_1_D18", + "DSP_1_RSTA", + "DSP_PCOUT45", + "DSP_IMUX7_4", + "DSP_FAN4_2", + "DSP_EE4A0_4", + "DSP_IMUX5_1", + "DSP_SW2A1_4", + "DSP_WW2END1_2", + "DSP_PCOUT2", + "DSP_1_ACOUT11", + "DSP_LOGIC_OUTS_B14_4", + "DSP_SW4A0_2", + "DSP_1_ACIN20", + "DSP_LOGIC_OUTS_B14_2", + "DSP_WW2A0_1", + "DSP_1_P35", + "DSP_ACOUT20", + "DSP_SE4C3_4", + "DSP_0_P10", + "DSP_EE2A0_3", + "DSP_LH1_4", + "DSP_SW4A0_1", + "DSP_LH1_3", + "DSP_1_BCOUT4", + "DSP_IMUX35_3", + "DSP_NE4BEG1_3", + "DSP_EL1BEG0_1", + "DSP_PCOUT0", + "DSP_LH12_0", + "DSP_LH11_2", + "DSP_LOGIC_OUTS_B13_4", + "DSP_1_PCOUT45", + "DSP_LOGIC_OUTS_B22_3", + "DSP_SE4C3_3", + "DSP_LOGIC_OUTS_B2_0", + "DSP_LOGIC_OUTS_B8_2", + "DSP_0_CARRYOUT0", + "DSP_WR1END3_0", + "DSP_ACOUT25", + "DSP_EE4C2_1", + "DSP_LOGIC_OUTS_B18_1", + "DSP_1_B1", + "DSP_0_PCIN14", + "DSP_IMUX30_1", + "DSP_WR1END0_0", + "DSP_MONITOR_N_4", + "DSP_0_C41", + "DSP_NW4END3_1", + "DSP_WW2A3_3", + "DSP_EE2BEG2_2", + "DSP_PCOUT31", + "DSP_LH10_4", + "DSP_1_ACOUT13", + "DSP_0_PCIN43", + "DSP_FAN7_4", + "DSP_1_D17", + "DSP_CTRL1_0", + "DSP_LOGIC_OUTS_B4_3", + "DSP_WR1END2_2", + "DSP_EE4BEG2_4", + "DSP_CLK0_3", + "DSP_WL1END2_2", + "DSP_WW2END0_3", + "DSP_WW4A2_0", + "DSP_0_A21", + "DSP_LOGIC_OUTS_B10_2", + "DSP_0_D0", + "DSP_ACOUT4", + "DSP_WW4C3_0", + "DSP_NE2A1_0", + "DSP_0_C45", + "DSP_SE4BEG3_1", + "DSP_IMUX36_2", + "DSP_0_PCOUT26", + "DSP_0_D17", + "DSP_1_PCIN13", + "DSP_0_BCIN16", + "DSP_NW4A3_0", + "DSP_0_P0", + "DSP_IMUX32_2", + "DSP_0_ACOUT20", + "DSP_0_INMODE4", + "DSP_0_A23", + "DSP_0_PCOUT18", + "DSP_EE4BEG0_1", + "DSP_SW4A2_1", + "DSP_1_PCIN47", + "DSP_1_ACOUT26", + "DSP_1_MULTSIGNIN", + "DSP_0_A14", + "DSP_BLOCK_OUTS_B1_4", + "DSP_IMUX12_4", + "DSP_BYP5_1", + "DSP_NW2A3_2", + "DSP_1_C5", + "DSP_1_PCOUT40", + "DSP_BYP5_3", + "DSP_1_P33", + "DSP_EE4B3_4", + "DSP_EE2A0_2", + "DSP_0_PCIN7", + "DSP_EE4BEG2_1", + "DSP_NE4BEG1_4", + "DSP_IMUX46_0", + "DSP_IMUX0_2", + "DSP_WL1END0_1", + "DSP_0_P22", + "DSP_NW2A1_0", + "DSP_1_A7", + "DSP_0_PCIN9", + "DSP_NW4END0_1", + "DSP_NW4END1_0", + "DSP_0_C31", + "DSP_WW2A2_1", + "DSP_1_PCOUT46", + "DSP_SW4END0_0", + "DSP_BYP7_1", + "DSP_PCOUT17", + "DSP_ACOUT15", + "DSP_0_C13", + "DSP_IMUX38_1", + "DSP_0_ALUMODE1", + "DSP_IMUX18_4", + "DSP_SE2A0_1", + "DSP_WW4B1_1", + "DSP_NE4BEG3_0", + "DSP_0_ACOUT23", + "DSP_1_ACOUT0", + "DSP_1_B7", + "DSP_1_B14", + "DSP_WW4A1_3", + "DSP_WW2A1_3", + "DSP_BYP4_3", + "DSP_0_P23", + "DSP_1_PCOUT25", + "DSP_WW4A2_4", + "DSP_1_BCOUT7", + "DSP_0_ACIN26", + "DSP_0_ACIN4", + "DSP_0_PCOUT4", + "DSP_1_PCOUT42", + "DSP_BYP4_4", + "DSP_ACOUT9", + "DSP_1_BCOUT6", + "DSP_0_ACIN14", + "DSP_IMUX10_4", + "DSP_IMUX13_2", + "DSP_0_ACIN6", + "DSP_IMUX33_4", + "DSP_NW4A3_4", + "DSP_CTRL0_1", + "DSP_EE4B2_2", + "DSP_NE4BEG0_3", + "DSP_0_PCOUT7", + "DSP_WW2END1_3", + "DSP_NW4A3_1", + "DSP_1_CEP", + "DSP_1_P1", + "DSP_0_P28", + "DSP_SE2A2_2", + "DSP_EE4B0_2", + "DSP_0_P39", + "DSP_LOGIC_OUTS_B15_2", + "DSP_PCOUT40", + "DSP_1_B10", + "DSP_NW2A0_2", + "DSP_0_P1", + "DSP_FAN5_3", + "DSP_EE4C3_3", + "DSP_1_P47", + "DSP_EE4BEG2_2", + "DSP_1_P18", + "DSP_1_ACIN9", + "DSP_1_PCIN14", + "DSP_NW4END2_1", + "DSP_SW2A2_4", + "DSP_LH2_3", + "DSP_0_PCIN20", + "DSP_WW4END1_1", + "DSP_NE2A0_1", + "DSP_GND_L", + "DSP_NW4A0_4", + "DSP_IMUX13_0", + "DSP_WW2A1_1", + "DSP_LOGIC_OUTS_B0_2", + "DSP_1_C32", + "DSP_WW4C0_0", + "DSP_0_A15", + "DSP_PCOUT11", + "DSP_0_ACOUT2", + "DSP_0_A11", + "DSP_IMUX12_3", + "DSP_1_PCOUT32", + "DSP_IMUX23_4", + "DSP_0_CLK", + "DSP_ER1BEG3_4", + "DSP_FAN5_1", + "DSP_1_PCOUT9", + "DSP_NW2A3_4", + "DSP_0_ACOUT28", + "DSP_0_D10", + "DSP_1_PCIN18", + "DSP_EE4BEG0_2", + "DSP_1_PCOUT19", + "DSP_NW4A1_3", + "DSP_1_C8", + "DSP_NE2A3_3", + "DSP_WW4A2_2", + "DSP_CLK1_1", + "DSP_1_A0", + "DSP_IMUX46_1", + "DSP_1_INMODE2", + "DSP_0_BCOUT5", + "DSP_SE4C0_3", + "DSP_1_CEINMODE", + "DSP_CLK1_3", + "DSP_SE2A1_4", + "DSP_1_PCOUT18", + "DSP_PCOUT41", + "DSP_0_BCIN13", + "DSP_IMUX3_4", + "DSP_EE4A1_4", + "DSP_WW4A0_2", + "DSP_ER1BEG1_0", + "DSP_1_PCOUT21", + "DSP_EE2A3_1", + "DSP_0_PCOUT1", + "DSP_WW2END3_4", + "DSP_0_P33", + "DSP_SE4C0_1", + "DSP_IMUX21_3", + "DSP_EE4B3_2", + "DSP_1_ACIN8", + "DSP_LOGIC_OUTS_B15_1", + "DSP_CTRL1_1", + "DSP_EE4C1_0", + "DSP_NE4BEG2_1", + "DSP_0_CEM", + "DSP_1_PCOUT36", + "DSP_1_C3", + "DSP_WW2A2_3", + "DSP_NE4C2_0", + "DSP_0_BCIN6", + "DSP_1_P27", + "DSP_PCOUT26", + "DSP_0_PCIN16", + "DSP_WW4C0_4", + "DSP_NE2A1_2", + "DSP_LH4_4", + "DSP_LOGIC_OUTS_B15_3", + "DSP_IMUX14_1", + "DSP_1_PCOUT30", + "DSP_WW2A2_0", + "DSP_BLOCK_OUTS_B0_0", + "DSP_IMUX37_2", + "DSP_IMUX40_2", + "DSP_SE2A3_3", + "DSP_IMUX17_0", + "DSP_SE2A0_3", + "DSP_WW4B1_2", + "DSP_NW2A0_0", + "DSP_0_PCIN39", + "DSP_EL1BEG3_0", + "DSP_LOGIC_OUTS_B9_2", + "DSP_1_D2", + "DSP_WR1END3_2", + "DSP_WW4END3_1", + "DSP_0_MULTSIGNIN", + "DSP_1_ACOUT7", + "DSP_LH5_2", + "DSP_WW4END1_0", + "DSP_0_ACOUT14", + "DSP_IMUX22_2", + "DSP_WR1END0_3", + "DSP_1_C25", + "DSP_1_ACOUT14", + "DSP_SE2A0_4", + "DSP_IMUX38_3", + "DSP_0_P24", + "DSP_PCOUT9", + "DSP_1_ACIN21", + "DSP_PCOUT22", + "DSP_0_P34", + "DSP_IMUX36_3", + "DSP_EE4C0_1", + "DSP_IMUX42_1", + "DSP_EL1BEG2_1", + "DSP_1_P14", + "DSP_WW4A3_2", + "DSP_IMUX15_4", + "DSP_FAN3_1", + "DSP_LH4_0", + "DSP_1_RSTCTRL", + "DSP_NW4A3_2", + "DSP_BLOCK_OUTS_B2_3", + "DSP_ACOUT3", + "DSP_1_PCIN4", + "DSP_1_ACIN29", + "DSP_NW2A2_0", + "DSP_SW2A1_3", + "DSP_IMUX29_3", + "DSP_SE4C2_2", + "DSP_IMUX2_2", + "DSP_ER1BEG3_2", + "DSP_LH10_3", + "DSP_0_ACOUT9", + "DSP_0_ACIN19", + "DSP_0_D22", + "DSP_LOGIC_OUTS_B17_0", + "DSP_EE4B3_1", + "DSP_IMUX4_2", + "DSP_NW2A0_3", + "DSP_1_P42", + "DSP_WW4END3_0", + "DSP_EE4BEG3_3", + "DSP_IMUX34_1", + "DSP_0_OPMODE4", + "DSP_1_A15", + "DSP_0_C6", + "DSP_SW4A0_0", + "DSP_CTRL1_3", + "DSP_0_C38", + "DSP_WW2END3_3", + "DSP_ER1BEG1_2", + "DSP_WR1END2_1", + "DSP_CARRYCASCOUT", + "DSP_0_ACOUT13", + "DSP_0_PCOUT32", + "DSP_IMUX41_4", + "DSP_1_A17", + "DSP_EE2BEG3_1", + "DSP_BYP2_4", + "DSP_SW2A3_4", + "DSP_IMUX25_0", + "DSP_1_C37", + "DSP_LOGIC_OUTS_B10_4", + "DSP_0_PCIN0", + "DSP_0_CARRYCASCOUT", + "DSP_ER1BEG1_3", + "DSP_LOGIC_OUTS_B5_4", + "DSP_0_BCIN7", + "DSP_1_C46", + "DSP_IMUX43_0", + "DSP_0_CEAD", + "DSP_1_B3", + "DSP_EE4B0_3", + "DSP_0_C40", + "DSP_IMUX45_2", + "DSP_0_BCOUT6", + "DSP_0_B12", + "DSP_PCOUT47", + "DSP_1_PCIN43", + "DSP_0_A16", + "DSP_LOGIC_OUTS_B5_1", + "DSP_FAN1_0", + "DSP_WW4A0_3", + "DSP_0_BCIN5", + "DSP_BYP7_2", + "DSP_EE2A0_0", + "DSP_WW4C3_2", + "DSP_IMUX37_3", + "DSP_0_B17", + "DSP_EE4BEG3_4", + "DSP_WW4B2_2", + "DSP_1_PATTERNBDETECT", + "DSP_1_C44", + "DSP_WW4B0_1", + "DSP_IMUX45_4", + "DSP_LH11_1", + "DSP_0_BCOUT8", + "DSP_EL1BEG0_2", + "DSP_1_BCIN15", + "DSP_0_PCIN10", + "DSP_NW4END0_2", + "DSP_NW4A0_1", + "DSP_0_ACIN12", + "DSP_0_PCIN47", + "DSP_NW2A1_3", + "DSP_LOGIC_OUTS_B5_2", + "DSP_BYP3_2", + "DSP_IMUX32_3", + "DSP_LOGIC_OUTS_B0_3", + "DSP_1_ACOUT8", + "DSP_1_PCOUT28", + "DSP_1_D12", + "DSP_0_P44", + "DSP_WW4END3_4", + "DSP_0_PCIN19", + "DSP_FAN0_3", + "DSP_SW2A3_1", + "DSP_WL1END0_3", + "DSP_0_PCOUT9", + "DSP_SW2A2_1", + "DSP_0_A4", + "DSP_IMUX35_0", + "DSP_IMUX42_4", + "DSP_1_BCOUT5", + "DSP_0_ALUMODE0", + "DSP_BYP0_0", + "DSP_EE4C1_2", + "DSP_1_P16", + "DSP_1_RSTINMODE", + "DSP_1_PCOUT17", + "DSP_0_CECTRL", + "DSP_LOGIC_OUTS_B22_1", + "DSP_LOGIC_OUTS_B4_4", + "DSP_WW4B2_0", + "DSP_IMUX27_4", + "DSP_0_OPMODE5", + "DSP_0_PCIN37", + "DSP_EE2BEG0_3", + "DSP_IMUX26_3", + "DSP_1_ACIN11", + "DSP_WR1END1_4", + "DSP_LOGIC_OUTS_B12_4", + "DSP_0_ACOUT16", + "DSP_0_ACIN17", + "DSP_EE4C0_4", + "DSP_BYP3_3", + "DSP_IMUX0_3", + "DSP_0_BCIN1", + "DSP_0_P14", + "DSP_1_BCIN12", + "DSP_NW2A2_3", + "DSP_WW4C0_2", + "DSP_WL1END3_0", + "DSP_EE2A1_2", + "DSP_IMUX44_4", + "DSP_IMUX10_3", + "DSP_WW4B0_4", + "DSP_1_BCIN10", + "DSP_1_C21", + "DSP_0_CEB2", + "DSP_EE2BEG3_2", + "DSP_LOGIC_OUTS_B9_1", + "DSP_1_BCOUT3", + "DSP_1_ACIN15", + "DSP_1_D23", + "DSP_1_RSTALLCARRYIN", + "DSP_IMUX14_3", + "DSP_0_B10", + "DSP_0_C42", + "DSP_NE4BEG3_2", + "DSP_ER1BEG0_2", + "DSP_1_PCOUT20", + "DSP_LOGIC_OUTS_B7_3", + "DSP_EE2A1_0", + "DSP_EE2BEG0_1", + "DSP_NW4A1_4", + "DSP_0_P11", + "DSP_0_ACIN24", + "DSP_IMUX35_2", + "DSP_IMUX45_3", + "DSP_1_P21", + "DSP_SW4END1_4", + "DSP_LOGIC_OUTS_B6_2", + "DSP_1_PCOUT6", + "DSP_ER1BEG3_1", + "DSP_WW4A1_2", + "DSP_IMUX8_1", + "DSP_SE4BEG1_2", + "DSP_0_C7", + "DSP_1_ACIN7", + "DSP_1_PCIN40", + "DSP_SW4END2_4", + "DSP_MONITOR_N_1", + "DSP_NE4C3_3", + "DSP_1_PCIN44", + "DSP_IMUX8_4", + "DSP_NW2A2_1", + "DSP_1_C12", + "DSP_EE4A0_1", + "DSP_0_A12", + "DSP_0_D15", + "DSP_EE4A3_0", + "DSP_SE4C1_1", + "DSP_WW2A3_4", + "DSP_0_A29", + "DSP_WR1END2_4", + "DSP_NE4BEG0_1", + "DSP_IMUX23_0", + "DSP_1_BCOUT8", + "DSP_IMUX1_4", + "DSP_NE4BEG0_2", + "DSP_1_D11", + "DSP_0_P36", + "DSP_SE4BEG0_4", + "DSP_1_ACOUT16", + "DSP_IMUX22_1", + "DSP_1_BCOUT2", + "DSP_1_ACIN13", + "DSP_0_C3", + "DSP_NE4C0_2", + "DSP_PCOUT7", + "DSP_1_B17", + "DSP_LOGIC_OUTS_B1_4", + "DSP_BLOCK_OUTS_B2_2", + "DSP_FAN4_3", + "DSP_NW4END3_4", + "DSP_IMUX10_2", + "DSP_IMUX7_1", + "DSP_0_C34", + "DSP_1_C42", + "DSP_WW4C2_1", + "DSP_1_BCIN9", + "DSP_0_ACOUT3", + "DSP_0_BCOUT2", + "DSP_SW4A1_4", + "DSP_1_PCIN36", + "DSP_ACOUT22", + "DSP_BCOUT9", + "DSP_1_ACOUT18", + "DSP_LH7_2", + "DSP_1_BCOUT13", + "DSP_0_PATTERNBDETECT", + "DSP_LOGIC_OUTS_B2_3", + "DSP_EE2BEG1_3", + "DSP_IMUX20_3", + "DSP_1_OPMODE4", + "DSP_EE4B2_3", + "DSP_LOGIC_OUTS_B20_4", + "DSP_WR1END2_0", + "DSP_IMUX42_2", + "DSP_PCOUT44", + "DSP_0_ACIN0", + "DSP_IMUX11_3", + "DSP_1_C4", + "DSP_BCOUT4", + "DSP_IMUX14_0", + "DSP_1_P13", + "DSP_SW4A1_2", + "DSP_EE4B3_3", + "DSP_1_B6", + "DSP_NE4BEG3_4", + "DSP_1_P17", + "DSP_PCOUT18", + "DSP_NW2A1_2", + "DSP_IMUX18_2", + "DSP_WW4A0_0", + "DSP_IMUX47_3", + "DSP_1_D10", + "DSP_NE2A3_2", + "DSP_SE4BEG0_0", + "DSP_1_D8", + "DSP_IMUX36_1", + "DSP_IMUX15_3", + "DSP_0_PCIN31", + "DSP_1_BCIN5", + "DSP_LOGIC_OUTS_B7_2", + "DSP_LOGIC_OUTS_B1_3", + "DSP_1_ACOUT10", + "DSP_0_C26", + "DSP_MONITOR_P_3", + "DSP_PCOUT36", + "DSP_NE4BEG0_0", + "DSP_0_ACIN21", + "DSP_WW4END0_0", + "DSP_LH7_4", + "DSP_0_ACIN28", + "DSP_EE4BEG1_4", + "DSP_1_PATTERNDETECT", + "DSP_IMUX6_1", + "DSP_ER1BEG1_1", + "DSP_LH9_0", + "DSP_CTRL1_2", + "DSP_0_C46", + "DSP_SW2A2_0", + "DSP_LOGIC_OUTS_B13_1", + "DSP_IMUX24_4", + "DSP_VCC_L", + "DSP_IMUX41_2", + "DSP_BYP0_4", + "DSP_NW4END1_1", + "DSP_0_BCOUT11", + "DSP_FAN0_0", + "DSP_1_CARRYINSEL2", + "DSP_IMUX39_0", + "DSP_0_PCIN26", + "DSP_1_C0", + "DSP_LOGIC_OUTS_B3_4", + "DSP_LH2_2", + "DSP_ER1BEG2_0", + "DSP_1_PCOUT29", + "DSP_1_ACOUT1", + "DSP_LOGIC_OUTS_B21_1", + "DSP_1_ACIN16", + "DSP_1_C13", + "DSP_1_P40", + "DSP_LOGIC_OUTS_B12_2", + "DSP_SW4END1_0", + "DSP_WW2A1_2", + "DSP_WW2END1_4", + "DSP_EE2BEG2_4", + "DSP_LOGIC_OUTS_B12_3", + "DSP_FAN5_4", + "DSP_EE4BEG0_0", + "DSP_0_PCOUT36", + "DSP_1_PCOUT23", + "DSP_LOGIC_OUTS_B17_1", + "DSP_PCOUT20", + "DSP_1_A22", + "DSP_1_A6", + "DSP_0_A10", + "DSP_1_C43", + "DSP_WW4END2_2", + "DSP_EE4A3_4", + "DSP_0_ACIN5", + "DSP_IMUX9_3", + "DSP_IMUX44_1", + "DSP_WW4END1_3", + "DSP_BLOCK_OUTS_B2_0", + "DSP_1_ACOUT4", + "DSP_IMUX6_2", + "DSP_BLOCK_OUTS_B0_1", + "DSP_0_P21", + "DSP_WW4B1_3", + "DSP_0_PCIN3", + "DSP_NW4A1_1", + "DSP_FAN5_0", + "DSP_1_BCIN13", + "DSP_WW2END3_1", + "DSP_1_P37", + "DSP_0_ACOUT0", + "DSP_FAN6_1", + "DSP_LH10_0", + "DSP_SE4C0_4", + "DSP_IMUX19_0", + "DSP_WW4C3_4", + "DSP_0_BCIN9", + "DSP_0_B11", + "DSP_LOGIC_OUTS_B17_2", + "DSP_IMUX39_4", + "DSP_BLOCK_OUTS_B0_2", + "DSP_EE4B2_1", + "DSP_LOGIC_OUTS_B8_3", + "DSP_IMUX35_4", + "DSP_IMUX25_3", + "DSP_0_C8", + "DSP_WL1END0_0", + "DSP_NE4C1_0", + "DSP_PCOUT5", + "DSP_SW2A2_3", + "DSP_1_CECTRL", + "DSP_LOGIC_OUTS_B23_3", + "DSP_EE2A0_4", + "DSP_0_PCOUT42", + "DSP_1_PCOUT44", + "DSP_NE4C0_1", + "DSP_LH12_3", + "DSP_WW2END0_4", + "DSP_SE2A0_2", + "DSP_FAN6_3", + "DSP_IMUX26_2", + "DSP_NW2A0_4", + "DSP_NE4C3_4", + "DSP_LOGIC_OUTS_B7_4", + "DSP_FAN3_0", + "DSP_1_D24", + "DSP_0_A26", + "DSP_1_PCIN16", + "DSP_1_P4", + "DSP_LOGIC_OUTS_B13_0", + "DSP_IMUX21_2", + "DSP_SW2A0_0", + "DSP_0_P12", + "DSP_SW4END2_0", + "DSP_BYP6_0", + "DSP_IMUX43_3", + "DSP_EE4BEG1_0", + "DSP_1_PCIN12", + "DSP_1_A21", + "DSP_WW4A3_1", + "DSP_PCOUT35", + "DSP_WL1END2_0", + "DSP_WW4B1_0", + "DSP_IMUX42_3", + "DSP_WW4END0_2", + "DSP_1_CARRYOUT2", + "DSP_BLOCK_OUTS_B3_2", + "DSP_LH11_4", + "DSP_LOGIC_OUTS_B9_0", + "DSP_0_B3", + "DSP_BYP6_4", + "DSP_SE4BEG3_0", + "DSP_EE4C1_3", + "DSP_1_P19", + "DSP_EE2A2_4", + "DSP_NW4END3_2", + "DSP_0_P42", + "DSP_EE4C2_4", + "DSP_LOGIC_OUTS_B1_1", + "DSP_0_A28", + "DSP_FAN4_4", + "DSP_WW2A0_0", + "DSP_ACOUT13", + "DSP_WW4A3_3", + "DSP_WW2END3_2", + "DSP_1_C41", + "DSP_IMUX37_0", + "DSP_LOGIC_OUTS_B10_3", + "DSP_0_BCIN4", + "DSP_IMUX9_2", + "DSP_EL1BEG1_1", + "DSP_IMUX7_2", + "DSP_1_BCIN8", + "DSP_LH5_0", + "DSP_FAN0_1", + "DSP_IMUX24_1", + "DSP_PCOUT25", + "DSP_1_CED", + "DSP_LOGIC_OUTS_B19_3", + "DSP_1_ACOUT23", + "DSP_LH2_0", + "DSP_1_PCOUT24", + "DSP_IMUX16_4", + "DSP_SE2A2_1", + "DSP_0_C28", + "DSP_PCOUT16", + "DSP_LOGIC_OUTS_B8_1", + "DSP_NE4C2_2", + "DSP_ACOUT19", + "DSP_1_PCOUT0", + "DSP_1_B13", + "DSP_1_PCOUT39", + "DSP_FAN4_0", + "DSP_0_ACOUT21", + "DSP_LOGIC_OUTS_B15_0", + "DSP_0_CEALUMODE", + "DSP_EE4BEG1_3", + "DSP_SW4END1_2", + "DSP_1_P31", + "DSP_EE4B1_1", + "DSP_IMUX7_3", + "DSP_0_PCOUT5", + "DSP_WL1END0_4", + "DSP_WR1END0_1", + "DSP_LOGIC_OUTS_B23_0", + "DSP_0_BCIN3", + "DSP_0_RSTALUMODE", + "DSP_IMUX40_4", + "DSP_0_P32", + "DSP_0_C18", + "DSP_SW4END0_1", + "DSP_CTRL0_3", + "DSP_1_A12", + "DSP_WW4A2_3", + "DSP_0_P20", + "DSP_IMUX40_3", + "DSP_PCOUT32", + "DSP_NW4END0_3", + "DSP_IMUX11_4", + "DSP_0_ACOUT11", + "DSP_WW2A0_4", + "DSP_0_A19", + "DSP_SW4A2_4", + "DSP_0_P30", + "DSP_EE2BEG0_0", + "DSP_SW2A0_3", + "DSP_ACOUT14", + "DSP_EE2A3_4", + "DSP_0_ACIN18", + "DSP_LOGIC_OUTS_B19_4", + "DSP_0_PCOUT2", + "DSP_0_PCOUT47", + "DSP_IMUX39_3", + "DSP_IMUX5_4", + "DSP_ACOUT21", + "DSP_LOGIC_OUTS_B4_0", + "DSP_IMUX45_1", + "DSP_1_PCIN29", + "DSP_1_PCIN7", + "DSP_EE4C2_2", + "DSP_0_P45", + "DSP_BYP2_2", + "DSP_1_PCIN8", + "DSP_1_C6", + "DSP_1_ACIN2", + "DSP_WW4A1_0", + "DSP_LOGIC_OUTS_B20_3", + "DSP_1_D3", + "DSP_IMUX41_3", + "DSP_SW4END3_4", + "DSP_0_PCOUT3", + "DSP_0_C9", + "DSP_BLOCK_OUTS_B0_3", + "DSP_IMUX28_1", + "DSP_BLOCK_OUTS_B1_2", + "DSP_0_BCOUT10", + "DSP_0_B6", + "DSP_BCOUT17", + "DSP_1_P39", + "DSP_WW4A0_1", + "DSP_0_PCIN22", + "DSP_ACOUT12", + "DSP_0_PCIN32", + "DSP_1_ALUMODE0", + "DSP_0_B2", + "DSP_PCOUT1", + "DSP_0_A3", + "DSP_1_C26", + "DSP_FAN2_4", + "DSP_IMUX19_1", + "DSP_EE4BEG1_1", + "DSP_LH12_1", + "DSP_IMUX34_2", + "DSP_1_P26", + "DSP_0_BCOUT1", + "DSP_EE4C1_4", + "DSP_1_PCIN11", + "DSP_IMUX31_1", + "DSP_SW2A3_0", + "DSP_0_PCIN18", + "DSP_SE4BEG3_2", + "DSP_LOGIC_OUTS_B7_1", + "DSP_IMUX47_2", + "DSP_1_ACIN24", + "DSP_IMUX46_3", + "DSP_1_A24", + "DSP_WW2END0_1", + "DSP_0_A24", + "DSP_0_PCOUT39", + "DSP_WW4B3_4", + "DSP_LOGIC_OUTS_B3_1", + "DSP_1_PCIN21", + "DSP_1_A1", + "DSP_NE2A0_2", + "DSP_IMUX21_0", + "DSP_CLK0_4", + "DSP_IMUX19_3", + "DSP_0_D3", + "DSP_EL1BEG2_4", + "DSP_FAN2_2", + "DSP_IMUX39_2", + "DSP_1_A20", + "DSP_EE4A1_3", + "DSP_LOGIC_OUTS_B23_1", + "DSP_1_PCIN32", + "DSP_IMUX16_2", + "DSP_NE2A2_0", + "DSP_IMUX27_3", + "DSP_IMUX16_3", + "DSP_0_ACOUT19", + "DSP_IMUX27_1", + "DSP_NE4BEG3_3", + "DSP_LH1_2", + "DSP_LOGIC_OUTS_B18_3", + "DSP_WW4END2_4", + "DSP_FAN5_2", + "DSP_EE2A3_3", + "DSP_0_ACOUT7", + "DSP_0_P41", + "DSP_1_A18", + "DSP_1_BCIN17", + "DSP_1_ACIN28", + "DSP_NW4A2_2", + "DSP_1_UNDERFLOW", + "DSP_SE4BEG0_2", + "DSP_LOGIC_OUTS_B21_4", + "DSP_0_C15", + "DSP_SW4END1_1", + "DSP_0_BCIN15", + "DSP_LOGIC_OUTS_B1_0", + "DSP_LOGIC_OUTS_B6_0", + "DSP_LOGIC_OUTS_B14_3", + "DSP_LOGIC_OUTS_B6_1", + "DSP_ACOUT1", + "DSP_0_C23", + "DSP_CLK0_1", + "DSP_CLK1_2", + "DSP_0_RSTINMODE", + "DSP_LOGIC_OUTS_B10_0", + "DSP_ACOUT16", + "DSP_SE4C3_0", + "DSP_1_ACIN5", + "DSP_1_BCIN0", + "DSP_EE2BEG3_3", + "DSP_1_C45", + "DSP_1_A26", + "DSP_0_CARRYOUT1", + "DSP_NE2A0_0", + "DSP_0_B4", + "DSP_LOGIC_OUTS_B8_4", + "DSP_IMUX43_4", + "DSP_0_P19", + "DSP_0_PCIN2", + "DSP_EE2A1_4", + "DSP_EE4B2_4", + "DSP_NW2A0_1", + "DSP_SE2A3_2", + "DSP_IMUX12_0", + "DSP_WR1END3_1", + "DSP_IMUX46_2", + "DSP_NE2A0_4", + "DSP_1_PCIN19", + "DSP_IMUX30_4", + "DSP_0_PCIN24", + "DSP_0_CARRYIN", + "DSP_0_BCOUT0", + "DSP_BLOCK_OUTS_B3_1", + "DSP_LOGIC_OUTS_B1_2", + "DSP_NW2A1_4", + "DSP_LH6_1", + "DSP_WW2A0_3", + "DSP_0_BCOUT3", + "DSP_1_A19", + "DSP_SW4A1_1", + "DSP_1_B0", + "DSP_0_ACIN15", + "DSP_0_C21", + "DSP_0_BCIN10", + "DSP_EE4BEG2_0", + "DSP_LOGIC_OUTS_B18_0", + "DSP_1_PCOUT34", + "DSP_1_C29", + "DSP_0_PCIN6", + "DSP_BCOUT13", + "DSP_SE2A3_1", + "DSP_EE4C1_1", + "DSP_1_P46", + "DSP_MONITOR_P_1", + "DSP_0_C29", + "DSP_1_OVERFLOW", + "DSP_ER1BEG0_1", + "DSP_1_PCOUT14", "DSP_NE4BEG2_0", "DSP_SE4BEG0_1", - "DSP_EE4A1_3", - "DSP_NE4BEG3_4", - "DSP_IMUX5_1", - "DSP_0_PCOUT32", - "DSP_1_A13", - "DSP_1_P8", - "DSP_1_A12", - "DSP_LOGIC_OUTS_B22_0", - "DSP_1_BCOUT9", - "DSP_1_PCOUT4", - "DSP_IMUX28_3", - "DSP_NE4C3_1", - "DSP_0_BCOUT7", - "DSP_1_PCOUT34", - "DSP_EE4C3_2", - "DSP_1_PCOUT7", - "DSP_PCOUT3", - "DSP_LOGIC_OUTS_B10_0", - "DSP_1_P44", - "DSP_SW4A1_3", - "DSP_IMUX25_2", - "DSP_BYP0_1", - "DSP_1_C6", - "DSP_1_PCOUT10", - "DSP_WW4A1_4", - "DSP_0_ACOUT29", - "DSP_IMUX27_2", - "DSP_SW4END3_1", - "DSP_IMUX28_4", - "DSP_IMUX16_4", - "DSP_SW4END2_2", - "DSP_IMUX46_1", - "DSP_FAN1_2", - "DSP_WW4END0_3", - "DSP_0_UNDERFLOW", - "DSP_LOGIC_OUTS_B17_2", - "DSP_0_PCIN20", - "DSP_NE2A3_4", - "DSP_WW4C1_1", - "DSP_0_BCOUT12", - "DSP_SW2A3_0", - "DSP_EE4C0_3", - "DSP_EL1BEG1_4", - "DSP_1_P29", - "DSP_0_P5", - "DSP_LH9_1", - "DSP_1_PCOUT0", - "DSP_WR1END1_1", - "DSP_NE4BEG1_1", - "DSP_0_C16", - "DSP_NE4BEG0_2", - "DSP_LH6_1", - "DSP_NW4A0_2", - "DSP_MONITOR_P_3", - "DSP_0_PATTERNDETECT", - "DSP_LH10_3", - "DSP_1_B6", - "DSP_1_P7", - "DSP_WW4C0_0", - "DSP_SW4A2_2", - "DSP_EL1BEG2_2", - "DSP_SW4A0_4", - "DSP_IMUX40_3", - "DSP_ACOUT12", - "DSP_FAN5_0", - "DSP_NE4BEG1_0", - "DSP_1_P15", - "DSP_0_CEB1", - "DSP_0_PCIN16", - "DSP_1_PCOUT39", - "DSP_0_P20", - "DSP_LOGIC_OUTS_B16_0", - "DSP_0_P42", - "DSP_IMUX21_4", - "DSP_IMUX36_0", - "DSP_IMUX0_1", - "DSP_SE2A0_3", - "DSP_0_PCIN10", - "DSP_0_P17", - "DSP_EE4C3_4", - "DSP_BYP3_2", - "DSP_LH5_3", - "DSP_EE4BEG1_2", - "DSP_0_P47", - "DSP_1_BCOUT2", - "DSP_IMUX24_0", - "DSP_WW4END3_3", - "DSP_1_A29", - "DSP_SW2A2_3", - "DSP_BLOCK_OUTS_B2_4", - "DSP_1_C41", - "DSP_PCOUT5", - "DSP_IMUX31_4", - "DSP_FAN3_1", - "DSP_BYP1_0", - "DSP_0_BCOUT9", - "DSP_1_BCOUT12", - "DSP_0_A11", - "DSP_0_P7", - "DSP_PCOUT31", - "DSP_1_D9", - "DSP_NE4BEG1_4", - "DSP_IMUX38_4", - "DSP_IMUX30_0", - "DSP_WL1END1_4", - "DSP_EE4B1_4", - "DSP_ER1BEG3_0", - "DSP_IMUX14_1", - "DSP_0_ACOUT9", - "DSP_EE4A2_1", - "DSP_1_BCOUT0", - "DSP_EE2BEG2_4", - "DSP_FAN6_1", - "DSP_1_OPMODE0", - "DSP_ER1BEG1_3", - "DSP_LOGIC_OUTS_B10_2", - "DSP_0_C19", - "DSP_SW4END2_1", - "DSP_PCOUT1", - "DSP_LH8_0", - "DSP_LH7_0", - "DSP_SE4BEG3_1", - "DSP_NE2A1_1", - "DSP_IMUX5_2", - "DSP_IMUX41_0", - "DSP_WW4END0_1", - "DSP_IMUX22_3", - "DSP_1_BCIN2", - "DSP_PCOUT40", - "DSP_1_CEP", - "DSP_SE4BEG2_3", - "DSP_0_BCOUT10", - "DSP_0_CARRYCASCOUT", - "DSP_1_B4", - "DSP_SW2A2_4", - "DSP_1_P43", - "DSP_1_P10", - "DSP_0_ACIN6", - "DSP_NE4C3_3", - "DSP_0_C14", - "DSP_LOGIC_OUTS_B13_2", - "DSP_LH9_2", - "DSP_SW2A1_1", - "DSP_WW2END3_3", - "DSP_1_ACOUT5", - "DSP_0_BCOUT1", - "DSP_EE4B2_0", - "DSP_EE4A2_3", - "DSP_WW2A3_3", - "DSP_NW4A1_0", - "DSP_IMUX2_1", - "DSP_0_PCOUT10", - "DSP_LOGIC_OUTS_B11_1", - "DSP_CLK0_0", - "DSP_IMUX32_1", - "DSP_IMUX10_1", - "DSP_0_B12", - "DSP_0_ACOUT4", - "DSP_WW4END2_0", - "DSP_0_P44", - "DSP_NE4C0_2", - "DSP_IMUX12_2", - "DSP_BLOCK_OUTS_B3_4", - "DSP_1_C11", - "DSP_ACOUT11", - "DSP_0_P15", - "DSP_LOGIC_OUTS_B22_2", - "DSP_0_D11", - "DSP_LOGIC_OUTS_B23_1", - "DSP_LOGIC_OUTS_B8_4", - "DSP_SE4C2_0", - "DSP_IMUX19_0", - "DSP_0_PCOUT22", - "DSP_0_A22", - "DSP_1_PCIN13", - "DSP_IMUX44_2", - "DSP_0_P26", - "DSP_EL1BEG2_4", - "DSP_BYP7_1", - "DSP_SW4A2_4", - "DSP_LH1_2", - "DSP_WR1END0_4", - "DSP_1_ACOUT23", - "DSP_1_PCOUT30", - "DSP_NE4C2_4", - "DSP_MONITOR_N_2", - "DSP_1_P40", - "DSP_0_P35", - "DSP_IMUX46_0", - "DSP_LOGIC_OUTS_B17_0", - "DSP_0_ACOUT3", - "DSP_1_ACIN21", - "DSP_1_OPMODE4", - "DSP_1_D14", - "DSP_IMUX7_4", - "DSP_NE2A2_0", - "DSP_WW4B0_3", - "DSP_WW4C1_0", - "DSP_IMUX45_2", - "DSP_BCOUT9", - "DSP_BCOUT4", - "DSP_1_C1", - "DSP_SE4C0_4", - "DSP_WW4C3_2", - "DSP_EE4C3_1", - "DSP_SW2A3_4", - "DSP_1_C20", - "DSP_LOGIC_OUTS_B2_1", - "DSP_1_C38", - "DSP_0_D17", - "DSP_0_P23", - "DSP_1_PCOUT14", - "DSP_IMUX9_4", - "DSP_1_P47", - "DSP_IMUX5_0", - "DSP_SE4C3_2", - "DSP_1_A7", - "DSP_1_RSTB", - "DSP_IMUX22_2", - "DSP_FAN1_3", - "DSP_1_A27", - "DSP_EE2A2_1", - "DSP_IMUX29_0", - "DSP_IMUX37_2", - "DSP_ACOUT20", - "DSP_0_MULTSIGNOUT", - "DSP_NE4BEG2_2", - "DSP_0_INMODE0", - "DSP_0_PCIN23", - "DSP_1_A1", - "DSP_ER1BEG3_2", - "DSP_NW4END3_2", - "DSP_LOGIC_OUTS_B9_2", - "DSP_0_B6", - "DSP_1_PCIN36", - "DSP_EE4A1_0", - "DSP_0_PCOUT13", - "DSP_0_ACIN5", - "DSP_1_BCIN11", - "DSP_BLOCK_OUTS_B0_1", - "DSP_EE4BEG2_2", - "DSP_1_ACIN12", - "DSP_LH7_2", - "DSP_NE2A0_3", - "DSP_0_C15", - "DSP_0_ACIN0", - "DSP_0_ACOUT2", - "DSP_0_A18", - "DSP_0_D5", - "DSP_SW4A3_3", - "DSP_1_D11", - "DSP_ER1BEG2_0", - "DSP_LOGIC_OUTS_B17_4", - "DSP_FAN3_2", - "DSP_EE4B1_1", - "DSP_WW4B0_0", - "DSP_MONITOR_P_4", - "DSP_SE4C0_0", - "DSP_LH2_3", - "DSP_0_D16", - "DSP_WW2A0_2", - "DSP_1_INMODE4", - "DSP_LOGIC_OUTS_B4_0", - "DSP_BYP6_4", - "DSP_0_PCOUT42", - "DSP_LH2_0", - "DSP_0_PCIN11", - "DSP_0_B14", - "DSP_0_ACIN23", - "DSP_0_CEA2", - "DSP_1_C31", - "DSP_NE4C1_0", - "DSP_0_PCIN22", - "DSP_BLOCK_OUTS_B2_3", - "DSP_IMUX34_3", - "DSP_EE4C0_1", - "DSP_IMUX1_3", - "DSP_WW4A1_3", - "DSP_0_P29", - "DSP_0_PCOUT4", - "DSP_WW4B3_4", - "DSP_LOGIC_OUTS_B12_0", - "DSP_0_ALUMODE2", - "DSP_SE4BEG1_0", - "DSP_1_PCOUT15", - "DSP_0_ACOUT13", - "DSP_CTRL1_4", - "DSP_IMUX41_1", - "DSP_EE2BEG0_3", - "DSP_0_PCOUT26", - "DSP_WW2A0_3", - "DSP_0_B8", - "DSP_NW4END2_4", - "DSP_IMUX20_4", - "DSP_IMUX37_3", - "DSP_BYP4_4", - "DSP_IMUX8_3", - "DSP_IMUX16_3", - "DSP_1_PCOUT26", - "DSP_SE4BEG1_2", - "DSP_0_OPMODE6", - "DSP_0_P36", - "DSP_IMUX36_1", - "DSP_1_ACOUT19", - "DSP_0_BCIN15", - "DSP_NE4BEG3_1", - "DSP_EE4A3_2", - "DSP_NW2A1_3", - "DSP_0_ALUMODE0", - "DSP_LH5_0", - "DSP_1_P18", - "DSP_0_C26", - "DSP_CTRL1_1", - "DSP_1_A4", - "DSP_1_ACOUT1", - "DSP_BYP3_1", - "DSP_IMUX7_1", - "DSP_WW4B1_4", - "DSP_0_A2", - "DSP_NW4END1_4", - "DSP_0_ACIN16", - "DSP_BCOUT3", - "DSP_IMUX13_1", - "DSP_1_CEB2", - "DSP_NW2A0_0", - "DSP_IMUX42_2", - "DSP_FAN6_0", - "DSP_0_ACIN14", - "DSP_WW4A2_2", - "DSP_IMUX42_0", - "DSP_0_PCIN43", - "DSP_1_ALUMODE3", - "DSP_EE2BEG0_0", - "DSP_FAN4_3", - "DSP_WW4C2_3", - "DSP_0_CEA1", - "DSP_1_OPMODE2", - "DSP_0_PCIN37", - "DSP_LOGIC_OUTS_B21_0", - "DSP_0_BCOUT2", - "DSP_1_D19", - "DSP_IMUX39_4", - "DSP_0_INMODE2", - "DSP_1_PATTERNDETECT", - "DSP_NW4END0_1", - "DSP_SW2A1_4", - "DSP_0_A27", - "DSP_WR1END3_4", - "DSP_LOGIC_OUTS_B17_3", - "DSP_1_PCIN46", - "DSP_1_RSTC", - "DSP_0_C28", - "DSP_EE2A3_0", - "DSP_0_OPMODE3", - "DSP_1_CARRYCASCIN", - "DSP_BYP6_0", - "DSP_WW4C2_4", - "DSP_1_C36", - "DSP_1_ACIN18", - "DSP_SE4C3_4", - "DSP_0_D21", - "DSP_1_ACIN9", - "DSP_WW4B3_3", - "DSP_NE4BEG0_4", - "DSP_0_INMODE4", - "DSP_NW4A2_2", - "DSP_EE2BEG1_4", - "DSP_1_BCOUT10", - "DSP_1_BCOUT7", - "DSP_LOGIC_OUTS_B19_1", - "DSP_1_ACIN16", - "DSP_0_PCIN35", - "DSP_IMUX9_3", - "DSP_SW4A0_0", - "DSP_WW4A2_0", - "DSP_WW2A1_3", - "DSP_1_D18", - "DSP_LOGIC_OUTS_B5_1", - "DSP_EE4A2_0", - "DSP_1_PCOUT22", - "DSP_IMUX20_2", - "DSP_1_CECTRL", - "DSP_SE4C0_2", - "DSP_1_BCOUT17", - "DSP_0_PCIN7", - "DSP_1_PCIN39", - "DSP_NW4A1_3", - "DSP_1_P24", - "DSP_1_PCIN35", - "DSP_0_PCOUT39", - "DSP_1_ACIN23", - "DSP_0_C2", - "DSP_ACOUT21", - "DSP_FAN5_1", - "DSP_1_ACIN20", - "DSP_1_A19", - "DSP_1_PCOUT28", - "DSP_IMUX17_3", - "DSP_IMUX15_4", - "DSP_PCOUT35", - "DSP_1_P17", - "DSP_1_C9", - "DSP_0_P13", - "DSP_0_PCIN30", - "DSP_BYP5_2", - "DSP_1_ACOUT11", - "DSP_WL1END2_0", - "DSP_1_P13", - "DSP_1_BCOUT16", - "DSP_0_C8", - "DSP_FAN0_0", - "DSP_IMUX26_4", - "DSP_0_PCIN28", - "DSP_WL1END3_4", - "DSP_0_BCIN9", - "DSP_LOGIC_OUTS_B15_2", - "DSP_WW2END0_0", - "DSP_IMUX10_0", - "DSP_NW2A2_1", - "DSP_0_ACOUT0", - "DSP_1_ACOUT12", - "DSP_WW4A3_3", - "DSP_0_A12", - "DSP_1_ACIN17", - "DSP_0_CARRYOUT3", - "DSP_SW4A0_3", - "DSP_LOGIC_OUTS_B4_1", - "DSP_0_B3", - "DSP_LOGIC_OUTS_B9_4", - "DSP_0_PCOUT24", - "DSP_SE4BEG1_3", - "DSP_IMUX42_3", - "DSP_WW2A1_2", - "DSP_IMUX45_3", - "DSP_0_BCOUT14", - "DSP_NW2A3_1", - "DSP_0_A21", - "DSP_0_P4", - "DSP_1_P19", - "DSP_LOGIC_OUTS_B1_1", - "DSP_0_RSTA", - "DSP_BYP1_4", - "DSP_WW4A0_1", - "DSP_ACOUT15", - "DSP_1_ACOUT29", - "DSP_1_B5", - "DSP_LOGIC_OUTS_B16_4", - "DSP_0_PCIN12", - "DSP_EE2A2_0", - "DSP_0_A16", - "DSP_PCOUT22", - "DSP_1_C37", - "DSP_1_P3", - "DSP_NE2A2_4", - "DSP_SW4A3_2", - "DSP_SE2A3_2", - "DSP_GND_L", - "DSP_NW4A2_0", - "DSP_1_PCIN20", - "DSP_0_RSTALUMODE", - "DSP_EE4A3_0", - "DSP_0_ACOUT6", - "DSP_0_C12", - "DSP_0_P1", - "DSP_1_PCOUT11", - "DSP_LH2_2", - "DSP_WW4B1_3", - "DSP_LOGIC_OUTS_B6_4", - "DSP_CTRL0_1", - "DSP_EE4BEG0_0", - "DSP_LOGIC_OUTS_B15_4", - "DSP_IMUX38_3", - "DSP_WW4A1_2", - "DSP_NW4END1_1", - "DSP_0_BCOUT4", - "DSP_0_ACIN7", - "DSP_0_OPMODE4", - "DSP_1_PCOUT44", - "DSP_LOGIC_OUTS_B18_2", - "DSP_BCOUT12", - "DSP_0_PCOUT0", - "DSP_1_OPMODE3", - "DSP_IMUX6_0", - "DSP_SE2A2_1", - "DSP_1_ACOUT22", - "DSP_WW2A2_0", - "DSP_IMUX21_0", - "DSP_MULTSIGNOUT", - "DSP_WW4B0_4", - "DSP_EL1BEG3_2", - "DSP_1_C47", - "DSP_NE4BEG2_4", - "DSP_0_PCIN46", - "DSP_IMUX32_2", - "DSP_WW4A1_1", - "DSP_0_ACOUT10", - "DSP_1_BCIN5", - "DSP_1_BCOUT6", - "DSP_1_CEAD", - "DSP_0_C6", - "DSP_1_PCOUT21", - "DSP_LOGIC_OUTS_B6_1", - "DSP_0_PCIN39", - "DSP_FAN1_1", - "DSP_LOGIC_OUTS_B0_1", - "DSP_IMUX25_4", - "DSP_LOGIC_OUTS_B2_3", - "DSP_IMUX42_1", - "DSP_1_C24", - "DSP_1_BCOUT4", - "DSP_1_BCIN9", - "DSP_NE2A0_2", - "DSP_1_A6", - "DSP_SE4C0_3", - "DSP_EE4A1_4", - "DSP_0_PCIN27", - "DSP_WW2END0_3", - "DSP_0_ACOUT17", - "DSP_NE4C2_1", - "DSP_0_PCIN40", - "DSP_1_BCIN10", - "DSP_WL1END3_3", - "DSP_IMUX9_0", - "DSP_NW4A1_4", - "DSP_BYP2_2", - "DSP_IMUX29_2", - "DSP_0_ACIN20", - "DSP_LOGIC_OUTS_B9_0", - "DSP_1_C46", - "DSP_0_P12", - "DSP_0_P32", - "DSP_ACOUT3", - "DSP_EE4C1_4", - "DSP_WW2A1_4", - "DSP_EE2BEG1_3", - "DSP_LH12_0", - "DSP_0_P46", - "DSP_LOGIC_OUTS_B14_4", - "DSP_EE4C2_2", - "DSP_ACOUT29", - "DSP_NE4BEG3_2", - "DSP_1_ACOUT3", - "DSP_1_C10", - "DSP_NW4END1_0", - "DSP_1_BCOUT14", - "DSP_FAN2_4", - "DSP_SW2A0_2", - "DSP_1_INMODE3", - "DSP_0_ACOUT28", - "DSP_1_BCOUT13", - "DSP_IMUX27_0", - "DSP_MONITOR_N_0", - "DSP_0_OPMODE0", - "DSP_IMUX4_4", - "DSP_IMUX3_0", - "DSP_EE4B2_2", - "DSP_IMUX47_1", - "DSP_IMUX11_4", - "DSP_SE2A3_1", - "DSP_1_P9", - "DSP_SW4END0_2", - "DSP_EL1BEG3_1", - "DSP_0_C27", - "DSP_NE4BEG0_3", - "DSP_EE4C2_4", - "DSP_0_PCIN47", - "DSP_0_P18", - "DSP_WL1END1_1", - "DSP_0_CARRYIN", - "DSP_1_BCIN12", - "DSP_IMUX4_2", - "DSP_NW4A0_4", - "DSP_1_ACIN22", - "DSP_NE2A1_4", - "DSP_IMUX47_4", - "DSP_SE4C1_3", - "DSP_1_D0", - "DSP_WW2A2_2", - "DSP_WR1END0_2", - "DSP_0_D3", - "DSP_SW4END1_0", - "DSP_0_B2", - "DSP_1_INMODE1", - "DSP_NE4C0_0", - "DSP_0_P8", - "DSP_1_P38", - "DSP_SE4BEG3_2", - "DSP_0_PCIN1", - "DSP_SW2A0_0", - "DSP_ER1BEG1_1", - "DSP_EE4BEG1_1", - "DSP_1_C35", - "DSP_1_B16", - "DSP_1_C23", - "DSP_WW4END3_2", - "DSP_EE4B0_3", - "DSP_LOGIC_OUTS_B19_4", - "DSP_0_ACIN1", - "DSP_NE4C0_1", - "DSP_WW2A0_4", - "DSP_ER1BEG2_1", - "DSP_0_BCIN6", - "DSP_EE4B1_3", - "DSP_0_BCOUT3", - "DSP_IMUX24_1", - "DSP_0_P28", - "DSP_IMUX11_2", - "DSP_IMUX1_1", - "DSP_FAN2_0", - "DSP_WR1END2_0", - "DSP_SW2A3_2", - "DSP_CLK1_4", - "DSP_SE4C2_4", - "DSP_1_PCOUT6", - "DSP_SE4C1_1", - "DSP_0_P25", - "DSP_BLOCK_OUTS_B1_0", - "DSP_SE4C1_0", - "DSP_IMUX2_2", - "DSP_0_C41", - "DSP_1_D6", - "DSP_0_P27", - "DSP_1_PCOUT43", - "DSP_EE2BEG0_2", - "DSP_WW2END2_2", - "DSP_LH7_3", - "DSP_0_A25", - "DSP_SE2A3_4", - "DSP_0_C47", - "DSP_0_A0", - "DSP_0_PCIN38", - "DSP_ACOUT28", - "DSP_NE2A2_1", - "DSP_0_B7", - "DSP_IMUX39_3", - "DSP_MONITOR_P_0", - "DSP_IMUX1_2", - "DSP_1_BCOUT1", - "DSP_LOGIC_OUTS_B7_3", - "DSP_PCOUT16", - "DSP_LOGIC_OUTS_B11_0", - "DSP_IMUX33_2", - "DSP_PCOUT42", - "DSP_0_D20", - "DSP_1_C28", - "DSP_SE4BEG0_4", - "DSP_0_ACIN22", - "DSP_1_PCIN3", - "DSP_0_A5", - "DSP_LOGIC_OUTS_B13_4", - "DSP_IMUX17_0", - "DSP_EE4B3_0", - "DSP_1_C40", - "DSP_0_PCOUT37", - "DSP_IMUX5_4", - "DSP_IMUX22_0", - "DSP_0_C20", - "DSP_WW4C3_3", - "DSP_0_A1", - "DSP_1_PCIN24", - "DSP_ACOUT5", - "DSP_1_C13", - "DSP_IMUX11_1", - "DSP_EE4C0_2", - "DSP_EE2BEG3_4", - "DSP_0_OVERFLOW", - "DSP_LH5_1", - "DSP_1_B15", - "DSP_0_D1", - "DSP_NW2A2_0", - "DSP_CLK1_2", - "DSP_IMUX40_0", - "DSP_1_P6", - "DSP_SW4END0_0", - "DSP_IMUX46_3", - "DSP_0_ACIN3", - "DSP_1_ALUMODE2", - "DSP_IMUX41_4", - "DSP_LOGIC_OUTS_B5_4", - "DSP_IMUX11_0", - "DSP_IMUX40_4", - "DSP_FAN4_4", - "DSP_EE2A2_2", - "DSP_0_PCOUT9", - "DSP_SE4BEG0_3", - "DSP_IMUX16_1", - "DSP_0_ACIN18", - "DSP_0_CARRYOUT1", - "DSP_NE4C2_3", - "DSP_IMUX17_2", - "DSP_IMUX27_1", - "DSP_LOGIC_OUTS_B5_2", - "DSP_ACOUT7", - "DSP_0_D15", - "DSP_IMUX23_4", - "DSP_EE4B2_1", - "DSP_1_BCOUT15", - "DSP_LOGIC_OUTS_B1_3", - "DSP_0_ACOUT19", - "DSP_0_B17", - "DSP_SE2A2_3", - "DSP_WW4C0_4", - "DSP_ACOUT9", - "DSP_SW4END1_4", - "DSP_EE4A1_2", - "DSP_EE2A3_3", - "DSP_IMUX6_3", - "DSP_0_C33", - "DSP_LOGIC_OUTS_B21_3", - "DSP_1_PCOUT19", - "DSP_LOGIC_OUTS_B5_0", - "DSP_LH3_0", - "DSP_0_ACOUT23", - "DSP_IMUX36_4", - "DSP_WW2A1_1", - "DSP_NE2A3_1", - "DSP_SE4C1_2", - "DSP_LH2_4", - "DSP_SW2A1_2", - "DSP_LOGIC_OUTS_B16_2", - "DSP_WR1END1_3", - "DSP_SE2A1_3", - "DSP_LOGIC_OUTS_B15_0", - "DSP_IMUX2_0", - "DSP_LOGIC_OUTS_B5_3", - "DSP_WW2END1_4", - "DSP_PCOUT26", - "DSP_FAN2_3", - "DSP_EL1BEG1_0", - "DSP_EE4C2_1", - "DSP_0_P30", - "DSP_NE2A0_1", - "DSP_ACOUT1", - "DSP_1_A9", - "DSP_1_BCIN13", - "DSP_BYP3_0", - "DSP_0_PCOUT21", - "DSP_PCOUT10", - "DSP_1_ACIN4", - "DSP_BCOUT1", - "DSP_LH8_4", - "DSP_WW2END3_1", - "DSP_BLOCK_OUTS_B3_2", - "DSP_WL1END2_4", - "DSP_IMUX1_0", - "DSP_1_ACOUT25", - "DSP_1_PCIN0", - "DSP_0_C38", - "DSP_IMUX31_0", - "DSP_WR1END3_2", - "DSP_NW4A2_4", "DSP_1_CARRYINSEL1", - "DSP_WW4A3_0", - "DSP_BYP6_3", - "DSP_0_P16", - "DSP_0_RSTINMODE", - "DSP_FAN7_4", - "DSP_0_A7", - "DSP_FAN6_4", - "DSP_1_OVERFLOW", - "DSP_LH10_2", - "DSP_IMUX17_4", - "DSP_0_ACOUT27", - "DSP_1_D1", - "DSP_0_P19", - "DSP_0_PCIN41", - "DSP_BYP1_2", - "DSP_1_P23", - "DSP_SW4END1_2", - "DSP_1_P36", - "DSP_0_PCOUT2", - "DSP_0_ACIN9", - "DSP_1_CEINMODE", - "DSP_SE4BEG3_3", - "DSP_0_PCOUT7", - "DSP_WW2A3_2", - "DSP_WR1END2_4", - "DSP_IMUX7_2", - "DSP_0_P21", - "DSP_EE4A0_1", - "DSP_LH3_4", - "DSP_0_OPMODE1", - "DSP_IMUX27_4", - "DSP_LOGIC_OUTS_B23_0", - "DSP_1_D15", - "DSP_IMUX46_2", - "DSP_0_BCIN11", - "DSP_IMUX8_4", - "DSP_NW4END2_0", - "DSP_0_A24", - "DSP_0_P33", - "DSP_1_B17", - "DSP_SW4A2_0", - "DSP_WW4END0_2", - "DSP_IMUX26_2", - "DSP_WW2A1_0", - "DSP_NW2A1_0", - "DSP_1_PCOUT33", - "DSP_WR1END0_3", - "DSP_PCOUT6", - "DSP_WL1END0_3", - "DSP_0_MULTSIGNIN", - "DSP_0_P38", - "DSP_1_PCIN11", - "DSP_1_PCIN47", - "DSP_0_CARRYINSEL1", - "DSP_IMUX20_0", - "DSP_CTRL0_3", - "DSP_LOGIC_OUTS_B21_1", - "DSP_LH11_3", - "DSP_0_A4", - "DSP_1_P16", - "DSP_PCOUT28", - "DSP_0_PCIN24", - "DSP_WW2END3_4", - "DSP_0_C40", - "DSP_1_PCOUT18", - "DSP_1_INMODE2", - "DSP_1_PCOUT13", - "DSP_IMUX30_3", - "DSP_1_PCOUT16", - "DSP_EE4BEG0_2", - "DSP_0_PCOUT47", - "DSP_1_PCIN31", - "DSP_1_CEB1", - "DSP_WW2A0_0", - "DSP_PCOUT41", - "DSP_WW4A0_3", - "DSP_NW4A0_1", - "DSP_LH9_0", - "DSP_IMUX32_3", - "DSP_1_P31", - "DSP_0_PCOUT41", - "DSP_BCOUT0", - "DSP_1_C14", - "DSP_LOGIC_OUTS_B22_4", - "DSP_0_PCIN0", - "DSP_0_ACIN29", - "DSP_IMUX8_2", - "DSP_1_P25", - "DSP_EE4BEG1_4", - "DSP_1_BCIN7", - "DSP_IMUX35_2", - "DSP_ER1BEG1_0", - "DSP_0_P43", - "DSP_NE4C0_4", - "DSP_WW2END0_4", - "DSP_0_P10", - "DSP_0_OPMODE2", - "DSP_0_PCIN8", - "DSP_1_D22", - "DSP_0_BCIN4", - "DSP_0_P34", - "DSP_1_CARRYOUT1", - "DSP_WR1END3_3", + "DSP_SW2A1_2", "DSP_IMUX23_2", - "DSP_0_P39", - "DSP_1_BCIN1", - "DSP_1_PCOUT31", - "DSP_0_ACOUT25", - "DSP_IMUX35_3", - "DSP_FAN6_2", - "DSP_IMUX39_0", - "DSP_1_P21", - "DSP_LOGIC_OUTS_B3_2", - "DSP_EE4BEG3_4", - "DSP_0_D24", - "DSP_1_P1", - "DSP_0_ACOUT14", - "DSP_CTRL0_0", - "DSP_FAN4_1", - "DSP_FAN4_2", - "DSP_SE4C0_1", - "DSP_ACOUT16", - "DSP_1_PCOUT25", - "DSP_1_PCOUT35", - "DSP_IMUX28_2", - "DSP_0_ACOUT8", - "DSP_LH9_4", - "DSP_WW4B2_0", - "DSP_LOGIC_OUTS_B4_4", - "DSP_1_CARRYOUT3", - "DSP_1_C16", - "DSP_IMUX33_3", - "DSP_SE4C2_1", - "DSP_0_B1", - "DSP_1_PCIN22", - "DSP_1_C19", - "DSP_1_A8", - "DSP_IMUX40_2", - "DSP_1_ACOUT14", - "DSP_WW4END0_0", - "DSP_PCOUT17", - "DSP_IMUX16_2", - "DSP_0_PCIN13", - "DSP_BYP0_3", - "DSP_WW4C0_1", - "DSP_WR1END1_2", - "DSP_EE4B3_1", - "DSP_IMUX14_4", - "DSP_IMUX41_2", - "DSP_0_A9", - "DSP_WW2END0_2", - "DSP_NW2A1_4", - "DSP_LH8_3", - "DSP_1_C30", - "DSP_WW4END3_4", - "DSP_0_C21", - "DSP_WR1END2_2", - "DSP_0_PCIN21", - "DSP_IMUX36_3", - "DSP_1_ACIN2", - "DSP_1_PCIN45", - "DSP_PCOUT30", - "DSP_1_CECARRYIN", - "DSP_NW4A1_1", - "DSP_WW4B2_4", - "DSP_ACOUT18", - "DSP_1_ACIN13", - "DSP_WW2A2_3", - "DSP_IMUX29_4", - "DSP_0_PCIN14", - "DSP_LH4_1", - "DSP_0_C10", - "DSP_NE4BEG1_2", - "DSP_LOGIC_OUTS_B8_2", - "DSP_EE4A2_2", - "DSP_SW2A2_2", - "DSP_1_ACIN24", - "DSP_1_ACIN29", - "DSP_0_CARRYINSEL2", - "DSP_0_D2", - "DSP_BYP5_3", - "DSP_LH5_2", - "DSP_PCOUT32", - "DSP_SE4BEG1_4", - "DSP_0_BCIN14", - "DSP_BYP4_2", - "DSP_SE4BEG2_1", - "DSP_1_P4", - "DSP_LOGIC_OUTS_B20_3", - "DSP_WL1END2_2", - "DSP_1_PCIN42", - "DSP_LOGIC_OUTS_B12_3", - "DSP_1_C0", - "DSP_BYP5_1", - "DSP_ER1BEG3_3", - "DSP_SE2A2_0", - "DSP_1_ACOUT6", - "DSP_0_ACOUT20", - "DSP_EE4B3_2", - "DSP_CLK1_0", - "DSP_NE2A1_3", - "DSP_WW4END1_3", - "DSP_LOGIC_OUTS_B16_1", - "DSP_IMUX29_3", - "DSP_0_PCOUT23", - "DSP_0_CEAD", - "DSP_0_ACIN25", - "DSP_1_ACOUT28", - "DSP_WW2END3_2", - "DSP_1_CARRYOUT2", - "DSP_1_PCIN16", - "DSP_IMUX15_0", - "DSP_NE4BEG0_0", - "DSP_WR1END3_1", - "DSP_1_A0", - "DSP_1_PCIN7", - "DSP_EL1BEG0_4", - "DSP_LOGIC_OUTS_B19_2", - "DSP_EE2BEG2_0", - "DSP_IMUX15_1", - "DSP_1_CED", - "DSP_0_PCOUT44", - "DSP_1_BCIN4", - "DSP_NW4END0_2", - "DSP_0_C44", - "DSP_0_CARRYCASCIN", - "DSP_EE2BEG2_1", - "DSP_CARRYCASCOUT", - "DSP_PCOUT27", - "DSP_LOGIC_OUTS_B3_0", - "DSP_CLK1_1", - "DSP_NE2A3_2", - "DSP_1_PCOUT23", - "DSP_LOGIC_OUTS_B11_2", - "DSP_1_MULTSIGNOUT", - "DSP_ER1BEG1_2", - "DSP_LOGIC_OUTS_B1_4", - "DSP_LH10_1", - "DSP_IMUX34_1", - "DSP_0_PCOUT25", - "DSP_1_BCIN6", - "DSP_EE4A0_2", - "DSP_0_C29", - "DSP_IMUX13_2", - "DSP_LH1_1", - "DSP_0_A19", - "DSP_0_PCOUT43", - "DSP_0_RSTB", - "DSP_0_PCOUT15", - "DSP_BCOUT14", - "DSP_IMUX31_2", - "DSP_NE4C1_2", - "DSP_FAN3_0", - "DSP_0_P40", - "DSP_0_ACOUT11", - "DSP_1_C32", - "DSP_1_PCIN34", - "DSP_IMUX14_0", - "DSP_FAN3_3", - "DSP_0_ACIN21", - "DSP_0_PCOUT5", - "DSP_EE2BEG2_2", - "DSP_NE4BEG1_3", - "DSP_ER1BEG3_4", - "DSP_0_ACIN26", - "DSP_1_ACIN15", - "DSP_0_P37", - "DSP_FAN1_4", - "DSP_WW2END3_0", - "DSP_SW4END0_1", - "DSP_IMUX32_4", - "DSP_EE2A0_2", - "DSP_ACOUT2", - "DSP_EE4A3_4", - "DSP_0_ACOUT7", - "DSP_1_PCIN38", - "DSP_0_D12", - "DSP_ACOUT14", - "DSP_LOGIC_OUTS_B6_0", - "DSP_IMUX43_3", - "DSP_EE4A1_1", - "DSP_0_CARRYOUT0", - "DSP_WW4END2_2", - "DSP_1_PCOUT3", - "DSP_0_C24", - "DSP_1_P20", - "DSP_WR1END0_0", - "DSP_BLOCK_OUTS_B3_1", - "DSP_1_ACIN11", - "DSP_1_ALUMODE1", - "DSP_1_RSTA", - "DSP_CLK1_3", - "DSP_PCOUT15", - "DSP_EL1BEG3_4", - "DSP_0_CLK", - "DSP_1_RSTINMODE", - "DSP_LH7_1", - "DSP_1_D3", - "DSP_0_C35", - "DSP_PCOUT44", - "DSP_SE2A0_4", - "DSP_PCOUT7", - "DSP_WL1END1_3", - "DSP_NE2A3_3", - "DSP_NE4C3_2", - "DSP_1_B7", - "DSP_0_PCIN15", - "DSP_IMUX0_0", - "DSP_SE4C2_3", - "DSP_ER1BEG0_4", - "DSP_ACOUT17", - "DSP_FAN7_2", - "DSP_IMUX25_1", - "DSP_IMUX38_0", - "DSP_LOGIC_OUTS_B12_2", - "DSP_SW4A3_4", - "DSP_LOGIC_OUTS_B10_4", - "DSP_1_CEA2", - "DSP_1_P12", - "DSP_0_PCOUT1", - "DSP_LOGIC_OUTS_B6_3", - "DSP_LOGIC_OUTS_B0_3", - "DSP_1_D5", - "DSP_IMUX31_3", - "DSP_WW4A2_1", - "DSP_IMUX4_0", - "DSP_BYP7_3", - "DSP_1_C15", - "DSP_1_A5", - "DSP_IMUX42_4", - "DSP_IMUX16_0", - "DSP_BCOUT10", - "DSP_EE4C1_1", - "DSP_EL1BEG3_0", - "DSP_LH8_1", - "DSP_NW4A2_3", - "DSP_0_ACIN4", - "DSP_LH7_4", - "DSP_IMUX45_1", - "DSP_0_PCOUT36", - "DSP_ER1BEG1_4", - "DSP_ACOUT23", - "DSP_SW4END2_0", - "DSP_1_CARRYINSEL0", - "DSP_CLK0_1", - "DSP_LOGIC_OUTS_B3_3", - "DSP_WW4END0_4", - "DSP_1_PCIN32", - "DSP_1_ACIN28", - "DSP_1_P41", - "DSP_FAN7_1", - "DSP_1_MULTSIGNIN", - "DSP_0_CEC", - "DSP_EE4C1_0", - "DSP_EL1BEG0_3", - "DSP_1_C27", - "DSP_0_PCIN5", - "DSP_BYP1_1", - "DSP_1_PCOUT47", - "DSP_SE4C1_4", - "DSP_NW2A0_4", - "DSP_IMUX23_3", - "DSP_1_RSTCTRL", - "DSP_1_A28", - "DSP_WL1END2_1", - "DSP_EE4BEG0_3", - "DSP_IMUX39_2", - "DSP_0_C43", - "DSP_IMUX38_2", - "DSP_WR1END2_3", - "DSP_FAN7_0", - "DSP_NE4C2_0", - "DSP_0_CEP", - "DSP_SE4C3_0", - "DSP_0_C36", - "DSP_0_ALUMODE1", - "DSP_0_BCIN8", - "DSP_EE2BEG3_2", - "DSP_0_C22", - "DSP_EE2A1_4", - "DSP_LOGIC_OUTS_B0_0", - "DSP_0_PCOUT31", - "DSP_IMUX22_1", - "DSP_IMUX19_3", - "DSP_IMUX18_1", - "DSP_0_ACIN27", - "DSP_LOGIC_OUTS_B23_2", - "DSP_PCOUT12", - "DSP_LOGIC_OUTS_B7_1", - "DSP_1_ACOUT7", - "DSP_0_C37", - "DSP_LOGIC_OUTS_B1_2", - "DSP_1_D8", - "DSP_1_C2", - "DSP_IMUX2_3", - "DSP_CLK0_4", - "DSP_0_PCIN33", - "DSP_IMUX24_2", - "DSP_SE2A3_3", - "DSP_IMUX43_1", - "DSP_IMUX12_3", - "DSP_BLOCK_OUTS_B3_0", - "DSP_WW4B1_0", - "DSP_0_PCOUT19", - "DSP_LH12_3", - "DSP_FAN2_2", - "DSP_EE4BEG0_1", - "DSP_1_CEA1", - "DSP_0_PCOUT14", - "DSP_BLOCK_OUTS_B1_1", - "DSP_1_ACIN8", - "DSP_0_A6", - "DSP_0_PCOUT11", - "DSP_0_ACIN10", - "DSP_0_CARRYOUT2", - "DSP_0_BCOUT17", - "DSP_0_ACIN15", - "DSP_SE4BEG0_2", - "DSP_ACOUT10", - "DSP_0_CECTRL", - "DSP_1_INMODE0", - "DSP_SW4END1_3", - "DSP_LOGIC_OUTS_B23_4", - "DSP_0_CARRYINSEL0", - "DSP_NW4END1_3", - "DSP_IMUX22_4", - "DSP_NW4END0_3", - "DSP_EE4BEG1_0", - "DSP_IMUX19_2", - "DSP_LOGIC_OUTS_B21_4", - "DSP_LOGIC_OUTS_B18_4", - "DSP_0_INMODE1", - "DSP_1_ACOUT15", - "DSP_IMUX19_1", - "DSP_LOGIC_OUTS_B4_3", - "DSP_0_PCOUT29", - "DSP_LH8_2", - "DSP_1_PCOUT42", - "DSP_NE4C2_2", - "DSP_IMUX26_0", - "DSP_LH9_3", - "DSP_0_C5", - "DSP_0_ACOUT1", - "DSP_EL1BEG0_2", - "DSP_IMUX34_0", - "DSP_0_C46", - "DSP_IMUX4_1", - "DSP_WW4B3_0", - "DSP_NW4A3_3", - "DSP_EE4B2_4", - "DSP_NW4A3_0", - "DSP_NW4END2_2", - "DSP_LOGIC_OUTS_B13_3", - "DSP_1_PCOUT8", - "DSP_BYP1_3", - "DSP_LH12_4", - "DSP_LOGIC_OUTS_B8_3", - "DSP_1_P0", - "DSP_IMUX41_3", "DSP_IMUX33_1", - "DSP_IMUX45_0", - "DSP_IMUX12_4", - "DSP_0_BCIN13", - "DSP_SE2A3_0", - "DSP_1_PCOUT36", - "DSP_SE4BEG3_0", - "DSP_BLOCK_OUTS_B2_0", - "DSP_0_CEINMODE", - "DSP_EE2A0_4", - "DSP_1_ACIN27", - "DSP_1_P30", - "DSP_LH6_0", - "DSP_EE2BEG1_2", - "DSP_SW4END1_1", - "DSP_1_A26", - "DSP_BYP0_4", - "DSP_0_ACOUT21", - "DSP_BLOCK_OUTS_B0_0", - "DSP_LH10_0", - "DSP_0_PCOUT16", - "DSP_LOGIC_OUTS_B20_0", - "DSP_0_C42", - "DSP_IMUX0_4", - "DSP_BCOUT13", - "DSP_PCOUT9", - "DSP_1_PCIN8", - "DSP_1_PCOUT24", - "DSP_LOGIC_OUTS_B22_1", - "DSP_0_BCOUT13", - "DSP_0_A17", - "DSP_FAN2_1", - "DSP_IMUX33_0", - "DSP_IMUX37_0", - "DSP_1_B11", - "DSP_EL1BEG3_3", - "DSP_1_PCOUT9", - "DSP_LH3_1", - "DSP_1_A10", - "DSP_IMUX24_4", - "DSP_SE2A1_0", - "DSP_CLK0_2", - "DSP_SE2A2_4", - "DSP_ACOUT19", - "DSP_EE4BEG3_1", - "DSP_0_ACOUT12", - "DSP_0_P9", - "DSP_NW4END3_1", - "DSP_0_BCOUT16", - "DSP_IMUX33_4", - "DSP_SW4END2_4", - "DSP_SE4BEG0_0", - "DSP_1_RSTM", - "DSP_1_ACIN10", - "DSP_IMUX18_0", - "DSP_NW4END0_4", - "DSP_NW2A3_4", - "DSP_LH4_0", - "DSP_CTRL0_2", - "DSP_1_P27", - "DSP_LOGIC_OUTS_B14_2", - "DSP_IMUX32_0", - "DSP_0_BCIN10", - "DSP_WR1END2_1", - "DSP_SW2A1_3", - "DSP_WW4A2_4", - "DSP_1_A25", - "DSP_1_ACOUT9", - "DSP_1_ACIN26", - "DSP_IMUX15_3", - "DSP_IMUX12_1", - "DSP_FAN3_4", - "DSP_LOGIC_OUTS_B7_0", - "DSP_PCOUT37", - "DSP_1_ACIN3", - "DSP_ER1BEG3_1", - "DSP_LH11_1", - "DSP_NW2A2_3", - "DSP_PCOUT39", - "DSP_EE4B1_0", - "DSP_1_C29", - "DSP_IMUX43_2", - "DSP_0_P6", - "DSP_1_BCIN16", - "DSP_SW4END0_4", - "DSP_WW2END1_3", - "DSP_PCOUT19", - "DSP_NW4END2_1", - "DSP_PCOUT13", - "DSP_LOGIC_OUTS_B16_3", - "DSP_0_P3", - "DSP_IMUX47_3", - "DSP_0_D19", - "DSP_PCOUT24", - "DSP_IMUX14_3", - "DSP_1_P26", - "DSP_0_CED", - "DSP_EL1BEG2_0", - "DSP_0_P22", - "DSP_0_BCIN2", - "DSP_0_C7", - "DSP_SW4A2_1", - "DSP_1_PCOUT32", - "DSP_1_ACOUT13", - "DSP_BLOCK_OUTS_B3_3", - "DSP_IMUX44_4", - "DSP_BYP4_1", - "DSP_EE4A3_1", - "DSP_0_C32", - "DSP_1_C44", - "DSP_0_RSTP", - "DSP_1_PCIN19", - "DSP_LOGIC_OUTS_B18_1", - "DSP_ACOUT8", - "DSP_WW4A0_2", - "DSP_EE2A1_2", - "DSP_BYP2_0", - "DSP_IMUX23_1", - "DSP_1_ACIN7", - "DSP_IMUX30_2", - "DSP_NW2A0_2", - "DSP_0_BCIN7", - "DSP_LOGIC_OUTS_B10_3", - "DSP_IMUX20_3", - "DSP_IMUX25_3", - "DSP_0_ACIN12", - "DSP_LH11_4", - "DSP_1_BCIN0", - "DSP_0_P14", - "DSP_LH2_1", - "DSP_WW4END2_1", - "DSP_1_ACIN19", - "DSP_0_A13", - "DSP_IMUX46_4", - "DSP_FAN5_2", - "DSP_IMUX5_3", - "DSP_WW4B2_2", - "DSP_1_PCOUT27", - "DSP_1_PCOUT40", - "DSP_EE2BEG1_1", - "DSP_0_A29", - "DSP_ACOUT22", - "DSP_ACOUT26", - "DSP_1_C25", - "DSP_IMUX3_3", - "DSP_1_PCOUT12", - "DSP_WW2A2_4", - "DSP_0_C3", - "DSP_1_CEALUMODE", - "DSP_LH5_4", - "DSP_0_C13", - "DSP_0_B11", - "DSP_WL1END3_0", - "DSP_EL1BEG2_1", - "DSP_EE2A2_4", - "DSP_0_PCOUT33", - "DSP_1_PCIN4", - "DSP_NW2A3_2", - "DSP_1_P35", - "DSP_1_C33", - "DSP_0_A14", - "DSP_0_ACOUT22", - "DSP_BYP7_0", - "DSP_LOGIC_OUTS_B2_4", - "DSP_1_B3", - "DSP_WW4A3_4", - "DSP_SW2A1_0", - "DSP_PCOUT29", - "DSP_IMUX36_2", - "DSP_0_CECARRYIN", - "DSP_FAN4_0", - "DSP_0_D9", - "DSP_0_CEB2", - "DSP_IMUX10_3", - "DSP_PCOUT2", - "DSP_SE2A1_1", - "DSP_1_BCIN15", - "DSP_0_PCIN42", - "DSP_LOGIC_OUTS_B19_3", - "DSP_BYP5_0", - "DSP_1_PCIN27", - "DSP_0_C11", - "DSP_SE4BEG2_4", - "DSP_SW2A0_1", - "DSP_BCOUT6", - "DSP_SE2A1_4", - "DSP_NW4END1_2", - "DSP_0_PCIN6", - "DSP_1_PCIN15", + "DSP_IMUX47_0", + "DSP_1_INMODE3", + "DSP_0_OVERFLOW", + "DSP_BCOUT2", + "DSP_EE4BEG1_2", + "DSP_PCOUT4", + "DSP_1_B16", "DSP_1_C22", - "DSP_0_C30", - "DSP_WL1END3_1", - "DSP_1_PCIN33", - "DSP_LH6_2", - "DSP_NW2A0_1", - "DSP_LOGIC_OUTS_B6_2", - "DSP_1_ACOUT16", - "DSP_1_PCOUT41", - "DSP_IMUX7_3", - "DSP_EE4B2_3", - "DSP_0_D4", - "DSP_SE2A2_2", - "DSP_EE2A1_1", - "DSP_0_PCIN9", - "DSP_IMUX0_3", - "DSP_ER1BEG0_1", - "DSP_EE4C3_0", - "DSP_LOGIC_OUTS_B15_1", - "DSP_BYP4_0", - "DSP_NE4C1_4", - "DSP_0_ACIN13", - "DSP_IMUX26_1", - "DSP_PCOUT21", - "DSP_0_BCIN3", - "DSP_LOGIC_OUTS_B3_1", - "DSP_PCOUT36", - "DSP_1_A21", - "DSP_BYP7_2", - "DSP_WR1END1_4", - "DSP_NE4BEG3_0", - "DSP_1_PCIN12", - "DSP_IMUX6_2", - "DSP_0_PCOUT3", - "DSP_CTRL0_4", - "DSP_0_PCOUT20", - "DSP_WW4A1_0", - "DSP_1_CARRYOUT0", - "DSP_NE2A1_2", - "DSP_EE4B0_1", - "DSP_1_D24", - "DSP_LH4_4", - "DSP_SE4BEG3_4", - "DSP_1_ACOUT8", - "DSP_EE2BEG0_4", - "DSP_0_D14", - "DSP_SW4END3_4", - "DSP_WW4END2_3", - "DSP_1_D4", - "DSP_0_PCIN2", - "DSP_LOGIC_OUTS_B2_2", - "DSP_CTRL1_2", - "DSP_BLOCK_OUTS_B1_2", - "DSP_0_ACOUT18" + "DSP_SE4BEG1_1" ], + "tile_type": "DSP_L", "sites": [ { - "prefix": "DSP48", - "y_coord": 0, - "type": "DSP48E1", "site_pins": { - "BCOUT1": "DSP_0_BCOUT1", - "D0": "DSP_0_D0", - "B9": "DSP_0_B9", - "C5": "DSP_0_C5", - "B12": "DSP_0_B12", - "ACOUT12": "DSP_0_ACOUT12", - "C2": "DSP_0_C2", - "BCIN17": "DSP_0_BCIN17", - "CEINMODE": "DSP_0_CEINMODE", - "PCIN10": "DSP_0_PCIN10", - "D12": "DSP_0_D12", - "BCIN3": "DSP_0_BCIN3", - "BCIN5": "DSP_0_BCIN5", - "A9": "DSP_0_A9", - "CARRYCASCIN": "DSP_0_CARRYCASCIN", - "RSTCTRL": "DSP_0_RSTCTRL", - "PCIN41": "DSP_0_PCIN41", - "PCIN16": "DSP_0_PCIN16", - "ACOUT10": "DSP_0_ACOUT10", - "ACOUT0": "DSP_0_ACOUT0", - "ACIN10": "DSP_0_ACIN10", - "C25": "DSP_0_C25", - "PCOUT9": "DSP_0_PCOUT9", - "A10": "DSP_0_A10", - "PCIN3": "DSP_0_PCIN3", - "PCOUT14": "DSP_0_PCOUT14", - "BCIN16": "DSP_0_BCIN16", - "P44": "DSP_0_P44", - "P17": "DSP_0_P17", - "D5": "DSP_0_D5", - "A16": "DSP_0_A16", - "C4": "DSP_0_C4", - "D21": "DSP_0_D21", - "PCOUT43": "DSP_0_PCOUT43", - "ACOUT18": "DSP_0_ACOUT18", - "PCIN37": "DSP_0_PCIN37", - "ACIN0": "DSP_0_ACIN0", - "ACOUT23": "DSP_0_ACOUT23", - "A23": "DSP_0_A23", - "ACOUT28": "DSP_0_ACOUT28", - "RSTD": "DSP_0_RSTD", - "PCOUT36": "DSP_0_PCOUT36", - "CEA1": "DSP_0_CEA1", - "CEP": "DSP_0_CEP", - "C40": "DSP_0_C40", - "ACIN2": "DSP_0_ACIN2", - "BCIN1": "DSP_0_BCIN1", - "PCOUT17": "DSP_0_PCOUT17", - "C20": "DSP_0_C20", "P45": "DSP_0_P45", - "B4": "DSP_0_B4", - "PCIN1": "DSP_0_PCIN1", - "A20": "DSP_0_A20", - "B14": "DSP_0_B14", - "A25": "DSP_0_A25", - "BCOUT13": "DSP_0_BCOUT13", - "ACOUT27": "DSP_0_ACOUT27", - "CARRYOUT0": "DSP_0_CARRYOUT0", - "CARRYOUT2": "DSP_0_CARRYOUT2", - "PCIN0": "DSP_0_PCIN0", - "ACIN11": "DSP_0_ACIN11", - "A14": "DSP_0_A14", - "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", - "ACOUT26": "DSP_0_ACOUT26", - "PCOUT32": "DSP_0_PCOUT32", - "PCOUT40": "DSP_0_PCOUT40", - "ACIN7": "DSP_0_ACIN7", - "CEALUMODE": "DSP_0_CEALUMODE", - "C0": "DSP_0_C0", - "A7": "DSP_0_A7", - "ALUMODE1": "DSP_0_ALUMODE1", - "C8": "DSP_0_C8", - "OPMODE0": "DSP_0_OPMODE0", - "D22": "DSP_0_D22", - "A5": "DSP_0_A5", - "PCIN25": "DSP_0_PCIN25", - "CED": "DSP_0_CED", - "BCIN10": "DSP_0_BCIN10", - "P16": "DSP_0_P16", - "ACIN25": "DSP_0_ACIN25", - "ACOUT25": "DSP_0_ACOUT25", - "PCIN20": "DSP_0_PCIN20", - "CEB2": "DSP_0_CEB2", - "PCIN18": "DSP_0_PCIN18", - "PCIN17": "DSP_0_PCIN17", - "D13": "DSP_0_D13", - "PCOUT19": "DSP_0_PCOUT19", - "OPMODE6": "DSP_0_OPMODE6", - "ACOUT1": "DSP_0_ACOUT1", - "PCOUT7": "DSP_0_PCOUT7", - "P2": "DSP_0_P2", - "OPMODE3": "DSP_0_OPMODE3", - "D2": "DSP_0_D2", - "D24": "DSP_0_D24", - "C3": "DSP_0_C3", - "C32": "DSP_0_C32", - "BCOUT4": "DSP_0_BCOUT4", - "C12": "DSP_0_C12", - "BCOUT0": "DSP_0_BCOUT0", - "ACIN29": "DSP_0_ACIN29", - "A21": "DSP_0_A21", - "C28": "DSP_0_C28", - "PCIN7": "DSP_0_PCIN7", - "PCIN42": "DSP_0_PCIN42", - "BCIN9": "DSP_0_BCIN9", - "PCOUT23": "DSP_0_PCOUT23", - "PCIN36": "DSP_0_PCIN36", - "OPMODE2": "DSP_0_OPMODE2", - "D1": "DSP_0_D1", - "RSTALUMODE": "DSP_0_RSTALUMODE", - "C10": "DSP_0_C10", - "PCOUT4": "DSP_0_PCOUT4", - "C17": "DSP_0_C17", - "D18": "DSP_0_D18", - "C9": "DSP_0_C9", - "PCIN22": "DSP_0_PCIN22", - "PCOUT44": "DSP_0_PCOUT44", - "BCOUT5": "DSP_0_BCOUT5", - "B8": "DSP_0_B8", - "A15": "DSP_0_A15", - "C11": "DSP_0_C11", - "ACIN19": "DSP_0_ACIN19", - "ACOUT22": "DSP_0_ACOUT22", - "P37": "DSP_0_P37", - "D8": "DSP_0_D8", - "D17": "DSP_0_D17", - "PCOUT12": "DSP_0_PCOUT12", - "ACIN21": "DSP_0_ACIN21", - "ACIN26": "DSP_0_ACIN26", - "PCIN4": "DSP_0_PCIN4", - "B1": "DSP_0_B1", - "PCOUT46": "DSP_0_PCOUT46", - "PCIN13": "DSP_0_PCIN13", - "C21": "DSP_0_C21", - "ACIN12": "DSP_0_ACIN12", - "ACIN3": "DSP_0_ACIN3", - "A28": "DSP_0_A28", - "P13": "DSP_0_P13", - "C7": "DSP_0_C7", - "ACOUT2": "DSP_0_ACOUT2", - "PCIN27": "DSP_0_PCIN27", - "B2": "DSP_0_B2", - "PCIN11": "DSP_0_PCIN11", - "CARRYIN": "DSP_0_CARRYIN", - "P25": "DSP_0_P25", - "ACIN16": "DSP_0_ACIN16", - "PCIN14": "DSP_0_PCIN14", - "PCOUT31": "DSP_0_PCOUT31", - "PCIN6": "DSP_0_PCIN6", - "B5": "DSP_0_B5", - "PCIN28": "DSP_0_PCIN28", - "PCIN12": "DSP_0_PCIN12", - "RSTA": "DSP_0_RSTA", - "PCIN40": "DSP_0_PCIN40", - "PCOUT21": "DSP_0_PCOUT21", - "D11": "DSP_0_D11", - "B0": "DSP_0_B0", - "BCOUT3": "DSP_0_BCOUT3", - "BCIN12": "DSP_0_BCIN12", - "CEC": "DSP_0_CEC", - "PCIN45": "DSP_0_PCIN45", - "A8": "DSP_0_A8", - "C33": "DSP_0_C33", "BCIN8": "DSP_0_BCIN8", - "BCOUT11": "DSP_0_BCOUT11", - "OPMODE5": "DSP_0_OPMODE5", - "D9": "DSP_0_D9", - "P33": "DSP_0_P33", - "PCOUT0": "DSP_0_PCOUT0", - "BCIN7": "DSP_0_BCIN7", - "P7": "DSP_0_P7", - "P43": "DSP_0_P43", - "ACIN4": "DSP_0_ACIN4", - "BCOUT2": "DSP_0_BCOUT2", - "C16": "DSP_0_C16", - "PCOUT11": "DSP_0_PCOUT11", - "P4": "DSP_0_P4", - "INMODE1": "DSP_0_INMODE1", - "PCIN21": "DSP_0_PCIN21", - "C38": "DSP_0_C38", - "PCOUT27": "DSP_0_PCOUT27", - "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", - "PCOUT26": "DSP_0_PCOUT26", - "P40": "DSP_0_P40", - "BCOUT14": "DSP_0_BCOUT14", - "BCIN6": "DSP_0_BCIN6", - "D20": "DSP_0_D20", - "P31": "DSP_0_P31", - "D7": "DSP_0_D7", - "ALUMODE3": "DSP_0_ALUMODE3", - "P28": "DSP_0_P28", - "BCIN0": "DSP_0_BCIN0", - "INMODE2": "DSP_0_INMODE2", - "BCOUT17": "DSP_0_BCOUT17", - "ACIN23": "DSP_0_ACIN23", - "C23": "DSP_0_C23", - "ACOUT5": "DSP_0_ACOUT5", - "PCOUT20": "DSP_0_PCOUT20", - "ACIN6": "DSP_0_ACIN6", - "P32": "DSP_0_P32", - "PCOUT8": "DSP_0_PCOUT8", + "CECTRL": "DSP_0_CECTRL", + "PCIN6": "DSP_0_PCIN6", + "PCOUT46": "DSP_0_PCOUT46", + "ACIN22": "DSP_0_ACIN22", + "PCIN14": "DSP_0_PCIN14", + "OVERFLOW": "DSP_0_OVERFLOW", + "ACIN29": "DSP_0_ACIN29", + "A22": "DSP_0_A22", + "ACOUT24": "DSP_0_ACOUT24", "PCIN43": "DSP_0_PCIN43", - "P27": "DSP_0_P27", - "ACIN5": "DSP_0_ACIN5", - "BCOUT6": "DSP_0_BCOUT6", - "C41": "DSP_0_C41", - "D23": "DSP_0_D23", - "ACOUT14": "DSP_0_ACOUT14", - "PCIN47": "DSP_0_PCIN47", - "ACIN17": "DSP_0_ACIN17", - "CARRYOUT3": "DSP_0_CARRYOUT3", - "PCOUT41": "DSP_0_PCOUT41", - "BCOUT12": "DSP_0_BCOUT12", - "B11": "DSP_0_B11", - "PCIN33": "DSP_0_PCIN33", - "PCIN9": "DSP_0_PCIN9", - "PCIN31": "DSP_0_PCIN31", - "C42": "DSP_0_C42", - "ACIN8": "DSP_0_ACIN8", - "A19": "DSP_0_A19", - "PCOUT30": "DSP_0_PCOUT30", + "BCOUT0": "DSP_0_BCOUT0", + "A7": "DSP_0_A7", + "PCIN30": "DSP_0_PCIN30", + "A1": "DSP_0_A1", + "P9": "DSP_0_P9", + "P12": "DSP_0_P12", + "P7": "DSP_0_P7", + "BCIN15": "DSP_0_BCIN15", "PCOUT24": "DSP_0_PCOUT24", - "P41": "DSP_0_P41", - "CARRYINSEL2": "DSP_0_CARRYINSEL2", - "CARRYOUT1": "DSP_0_CARRYOUT1", - "D3": "DSP_0_D3", - "A2": "DSP_0_A2", - "ALUMODE2": "DSP_0_ALUMODE2", - "C6": "DSP_0_C6", - "P46": "DSP_0_P46", - "D14": "DSP_0_D14", - "P29": "DSP_0_P29", - "PCOUT3": "DSP_0_PCOUT3", - "A24": "DSP_0_A24", + "PCIN46": "DSP_0_PCIN46", + "P0": "DSP_0_P0", + "P18": "DSP_0_P18", + "P15": "DSP_0_P15", + "BCIN1": "DSP_0_BCIN1", + "B6": "DSP_0_B6", + "PCIN7": "DSP_0_PCIN7", + "ACIN17": "DSP_0_ACIN17", + "C18": "DSP_0_C18", + "P30": "DSP_0_P30", "C46": "DSP_0_C46", - "B10": "DSP_0_B10", - "BCIN14": "DSP_0_BCIN14", + "P36": "DSP_0_P36", + "C12": "DSP_0_C12", + "PCOUT11": "DSP_0_PCOUT11", + "C32": "DSP_0_C32", + "BCIN12": "DSP_0_BCIN12", + "B11": "DSP_0_B11", + "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", + "PCIN41": "DSP_0_PCIN41", + "P43": "DSP_0_P43", + "A27": "DSP_0_A27", + "C45": "DSP_0_C45", + "B12": "DSP_0_B12", + "ACIN3": "DSP_0_ACIN3", + "P44": "DSP_0_P44", + "PCOUT0": "DSP_0_PCOUT0", + "ACOUT9": "DSP_0_ACOUT9", + "C28": "DSP_0_C28", "ACOUT11": "DSP_0_ACOUT11", "C13": "DSP_0_C13", - "PCOUT16": "DSP_0_PCOUT16", - "BCOUT10": "DSP_0_BCOUT10", - "A22": "DSP_0_A22", - "PCOUT28": "DSP_0_PCOUT28", - "ACOUT6": "DSP_0_ACOUT6", - "BCOUT7": "DSP_0_BCOUT7", - "ACIN27": "DSP_0_ACIN27", - "ACOUT4": "DSP_0_ACOUT4", - "PCOUT39": "DSP_0_PCOUT39", - "P9": "DSP_0_P9", - "C14": "DSP_0_C14", - "PCOUT22": "DSP_0_PCOUT22", - "B13": "DSP_0_B13", - "P19": "DSP_0_P19", - "PCIN15": "DSP_0_PCIN15", - "ACOUT17": "DSP_0_ACOUT17", - "A1": "DSP_0_A1", - "B3": "DSP_0_B3", - "C24": "DSP_0_C24", - "P35": "DSP_0_P35", - "P38": "DSP_0_P38", - "INMODE0": "DSP_0_INMODE0", - "PCIN26": "DSP_0_PCIN26", - "BCOUT9": "DSP_0_BCOUT9", - "P3": "DSP_0_P3", - "ALUMODE0": "DSP_0_ALUMODE0", - "A6": "DSP_0_A6", - "A18": "DSP_0_A18", - "P34": "DSP_0_P34", - "RSTINMODE": "DSP_0_RSTINMODE", - "A0": "DSP_0_A0", - "ACIN22": "DSP_0_ACIN22", - "ACOUT13": "DSP_0_ACOUT13", - "A17": "DSP_0_A17", - "C34": "DSP_0_C34", - "P10": "DSP_0_P10", - "BCIN15": "DSP_0_BCIN15", - "PATTERNDETECT": "DSP_0_PATTERNDETECT", - "C45": "DSP_0_C45", - "PCIN19": "DSP_0_PCIN19", + "C7": "DSP_0_C7", + "BCOUT3": "DSP_0_BCOUT3", + "C40": "DSP_0_C40", + "PCIN24": "DSP_0_PCIN24", + "BCIN16": "DSP_0_BCIN16", + "B5": "DSP_0_B5", + "C15": "DSP_0_C15", + "PCIN23": "DSP_0_PCIN23", + "ACOUT18": "DSP_0_ACOUT18", "BCIN2": "DSP_0_BCIN2", - "CEAD": "DSP_0_CEAD", - "PCIN46": "DSP_0_PCIN46", - "INMODE3": "DSP_0_INMODE3", - "P24": "DSP_0_P24", - "PCIN32": "DSP_0_PCIN32", - "A12": "DSP_0_A12", - "PCOUT35": "DSP_0_PCOUT35", - "C37": "DSP_0_C37", - "P42": "DSP_0_P42", - "PCIN30": "DSP_0_PCIN30", - "P26": "DSP_0_P26", - "ACOUT3": "DSP_0_ACOUT3", - "B6": "DSP_0_B6", - "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", - "ACIN20": "DSP_0_ACIN20", + "C14": "DSP_0_C14", + "C9": "DSP_0_C9", + "D0": "DSP_0_D0", + "A4": "DSP_0_A4", + "ACOUT23": "DSP_0_ACOUT23", + "PCIN33": "DSP_0_PCIN33", + "ACOUT16": "DSP_0_ACOUT16", + "PCIN25": "DSP_0_PCIN25", + "B0": "DSP_0_B0", "CEB1": "DSP_0_CEB1", - "P0": "DSP_0_P0", + "RSTB": "DSP_0_RSTB", + "P16": "DSP_0_P16", + "PCIN18": "DSP_0_PCIN18", + "RSTM": "DSP_0_RSTM", + "PCOUT3": "DSP_0_PCOUT3", + "PCIN40": "DSP_0_PCIN40", + "CARRYOUT2": "DSP_0_CARRYOUT2", + "ALUMODE3": "DSP_0_ALUMODE3", + "C5": "DSP_0_C5", + "BCIN9": "DSP_0_BCIN9", + "D20": "DSP_0_D20", + "BCIN17": "DSP_0_BCIN17", + "C38": "DSP_0_C38", + "A6": "DSP_0_A6", + "A13": "DSP_0_A13", + "CARRYOUT1": "DSP_0_CARRYOUT1", + "P32": "DSP_0_P32", + "C19": "DSP_0_C19", + "C11": "DSP_0_C11", "PCOUT5": "DSP_0_PCOUT5", "PCOUT25": "DSP_0_PCOUT25", - "PCIN23": "DSP_0_PCIN23", - "A3": "DSP_0_A3", - "PCOUT18": "DSP_0_PCOUT18", - "BCOUT8": "DSP_0_BCOUT8", - "P11": "DSP_0_P11", - "ACIN18": "DSP_0_ACIN18", - "B16": "DSP_0_B16", - "MULTSIGNIN": "DSP_0_MULTSIGNIN", - "ACOUT21": "DSP_0_ACOUT21", - "PCIN38": "DSP_0_PCIN38", - "C30": "DSP_0_C30", - "CARRYINSEL0": "DSP_0_CARRYINSEL0", - "C29": "DSP_0_C29", - "C19": "DSP_0_C19", - "ACOUT8": "DSP_0_ACOUT8", - "ACIN13": "DSP_0_ACIN13", - "PCOUT38": "DSP_0_PCOUT38", - "OPMODE1": "DSP_0_OPMODE1", - "PCOUT45": "DSP_0_PCOUT45", - "ACIN24": "DSP_0_ACIN24", - "OPMODE4": "DSP_0_OPMODE4", - "PCIN5": "DSP_0_PCIN5", - "PCOUT6": "DSP_0_PCOUT6", - "D16": "DSP_0_D16", - "ACOUT15": "DSP_0_ACOUT15", - "P12": "DSP_0_P12", - "ACOUT29": "DSP_0_ACOUT29", - "INMODE4": "DSP_0_INMODE4", - "C15": "DSP_0_C15", - "PCIN44": "DSP_0_PCIN44", - "P36": "DSP_0_P36", - "PCOUT2": "DSP_0_PCOUT2", - "C27": "DSP_0_C27", - "P1": "DSP_0_P1", - "CARRYINSEL1": "DSP_0_CARRYINSEL1", - "P8": "DSP_0_P8", - "PCOUT47": "DSP_0_PCOUT47", - "RSTALLCARRYIN": "DSP_0_RSTALLCARRYIN", - "P18": "DSP_0_P18", - "PCOUT10": "DSP_0_PCOUT10", - "ACIN1": "DSP_0_ACIN1", - "C1": "DSP_0_C1", - "PCIN24": "DSP_0_PCIN24", - "RSTB": "DSP_0_RSTB", - "PCIN29": "DSP_0_PCIN29", - "P30": "DSP_0_P30", - "BCOUT15": "DSP_0_BCOUT15", - "P22": "DSP_0_P22", "BCIN13": "DSP_0_BCIN13", - "PCOUT34": "DSP_0_PCOUT34", - "BCIN11": "DSP_0_BCIN11", - "C18": "DSP_0_C18", - "A11": "DSP_0_A11", - "C43": "DSP_0_C43", - "C35": "DSP_0_C35", - "C47": "DSP_0_C47", - "PCIN34": "DSP_0_PCIN34", + "P38": "DSP_0_P38", + "ACOUT10": "DSP_0_ACOUT10", + "PCIN38": "DSP_0_PCIN38", + "C2": "DSP_0_C2", + "CEB2": "DSP_0_CEB2", "ACIN14": "DSP_0_ACIN14", - "PCIN8": "DSP_0_PCIN8", - "CEA2": "DSP_0_CEA2", - "A4": "DSP_0_A4", - "ACIN28": "DSP_0_ACIN28", - "A13": "DSP_0_A13", - "PCOUT42": "DSP_0_PCOUT42", - "PCOUT15": "DSP_0_PCOUT15", - "D10": "DSP_0_D10", - "CECTRL": "DSP_0_CECTRL", - "P6": "DSP_0_P6", - "ACOUT16": "DSP_0_ACOUT16", - "CEM": "DSP_0_CEM", - "A27": "DSP_0_A27", - "ACIN15": "DSP_0_ACIN15", - "D15": "DSP_0_D15", - "P23": "DSP_0_P23", - "UNDERFLOW": "DSP_0_UNDERFLOW", - "OVERFLOW": "DSP_0_OVERFLOW", - "RSTP": "DSP_0_RSTP", - "P39": "DSP_0_P39", - "CLK": "DSP_0_CLK", - "A29": "DSP_0_A29", - "P15": "DSP_0_P15", - "ACOUT24": "DSP_0_ACOUT24", - "ACOUT9": "DSP_0_ACOUT9", - "CECARRYIN": "DSP_0_CECARRYIN", + "ALUMODE1": "DSP_0_ALUMODE1", "P47": "DSP_0_P47", - "B7": "DSP_0_B7", - "BCOUT16": "DSP_0_BCOUT16", - "PCOUT13": "DSP_0_PCOUT13", - "ACIN9": "DSP_0_ACIN9", - "P14": "DSP_0_P14", - "ACOUT7": "DSP_0_ACOUT7", - "D4": "DSP_0_D4", - "C22": "DSP_0_C22", - "A26": "DSP_0_A26", - "P21": "DSP_0_P21", - "D6": "DSP_0_D6", - "D19": "DSP_0_D19", - "B17": "DSP_0_B17", - "P20": "DSP_0_P20", - "PCIN35": "DSP_0_PCIN35", - "PCIN39": "DSP_0_PCIN39", - "RSTC": "DSP_0_RSTC", - "B15": "DSP_0_B15", - "ACOUT19": "DSP_0_ACOUT19", - "PCOUT37": "DSP_0_PCOUT37", - "ACOUT20": "DSP_0_ACOUT20", + "PCOUT10": "DSP_0_PCOUT10", + "PCIN19": "DSP_0_PCIN19", + "P27": "DSP_0_P27", + "PCOUT39": "DSP_0_PCOUT39", + "P19": "DSP_0_P19", + "D12": "DSP_0_D12", + "ACOUT25": "DSP_0_ACOUT25", + "CEM": "DSP_0_CEM", + "P6": "DSP_0_P6", + "A25": "DSP_0_A25", + "BCIN6": "DSP_0_BCIN6", + "C47": "DSP_0_C47", + "PCIN2": "DSP_0_PCIN2", + "BCIN14": "DSP_0_BCIN14", + "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", + "D16": "DSP_0_D16", + "P2": "DSP_0_P2", + "ACOUT3": "DSP_0_ACOUT3", + "A11": "DSP_0_A11", + "PCIN8": "DSP_0_PCIN8", + "PCIN13": "DSP_0_PCIN13", + "P40": "DSP_0_P40", + "OPMODE3": "DSP_0_OPMODE3", + "BCOUT11": "DSP_0_BCOUT11", + "C4": "DSP_0_C4", + "PCIN4": "DSP_0_PCIN4", + "PCIN28": "DSP_0_PCIN28", + "ACOUT4": "DSP_0_ACOUT4", + "PCOUT2": "DSP_0_PCOUT2", + "BCIN0": "DSP_0_BCIN0", + "ACOUT26": "DSP_0_ACOUT26", + "ACOUT13": "DSP_0_ACOUT13", + "PCIN10": "DSP_0_PCIN10", + "PCOUT6": "DSP_0_PCOUT6", + "C43": "DSP_0_C43", + "A2": "DSP_0_A2", + "ACIN26": "DSP_0_ACIN26", + "CECARRYIN": "DSP_0_CECARRYIN", + "ACOUT15": "DSP_0_ACOUT15", + "PCOUT28": "DSP_0_PCOUT28", + "B2": "DSP_0_B2", + "ACIN1": "DSP_0_ACIN1", + "P23": "DSP_0_P23", + "PCIN0": "DSP_0_PCIN0", + "PCIN47": "DSP_0_PCIN47", + "BCOUT17": "DSP_0_BCOUT17", + "PCOUT42": "DSP_0_PCOUT42", + "D22": "DSP_0_D22", + "CED": "DSP_0_CED", + "ACIN23": "DSP_0_ACIN23", + "ACIN2": "DSP_0_ACIN2", + "A17": "DSP_0_A17", + "PCOUT20": "DSP_0_PCOUT20", + "BCIN7": "DSP_0_BCIN7", + "D14": "DSP_0_D14", + "P8": "DSP_0_P8", + "ALUMODE2": "DSP_0_ALUMODE2", + "D17": "DSP_0_D17", + "ACIN10": "DSP_0_ACIN10", + "OPMODE4": "DSP_0_OPMODE4", "C26": "DSP_0_C26", - "RSTM": "DSP_0_RSTM", - "PCOUT1": "DSP_0_PCOUT1", + "ACIN16": "DSP_0_ACIN16", + "PCIN5": "DSP_0_PCIN5", "C44": "DSP_0_C44", + "ACIN5": "DSP_0_ACIN5", + "PCIN37": "DSP_0_PCIN37", + "PCIN15": "DSP_0_PCIN15", + "PCOUT44": "DSP_0_PCOUT44", + "C22": "DSP_0_C22", + "A0": "DSP_0_A0", + "INMODE4": "DSP_0_INMODE4", + "B3": "DSP_0_B3", + "C0": "DSP_0_C0", + "P29": "DSP_0_P29", + "ACOUT21": "DSP_0_ACOUT21", + "PCIN1": "DSP_0_PCIN1", + "B15": "DSP_0_B15", + "PCIN39": "DSP_0_PCIN39", + "OPMODE1": "DSP_0_OPMODE1", + "ACIN12": "DSP_0_ACIN12", + "ACIN27": "DSP_0_ACIN27", + "PCOUT41": "DSP_0_PCOUT41", + "ACOUT2": "DSP_0_ACOUT2", + "ACIN8": "DSP_0_ACIN8", + "B13": "DSP_0_B13", + "A28": "DSP_0_A28", + "PCOUT8": "DSP_0_PCOUT8", + "P11": "DSP_0_P11", "P5": "DSP_0_P5", - "PCOUT33": "DSP_0_PCOUT33", + "CARRYOUT0": "DSP_0_CARRYOUT0", + "D7": "DSP_0_D7", + "CEC": "DSP_0_CEC", + "ACOUT12": "DSP_0_ACOUT12", + "A29": "DSP_0_A29", + "B1": "DSP_0_B1", + "C17": "DSP_0_C17", + "B4": "DSP_0_B4", + "C27": "DSP_0_C27", + "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", + "P28": "DSP_0_P28", + "A24": "DSP_0_A24", + "RSTINMODE": "DSP_0_RSTINMODE", + "P20": "DSP_0_P20", + "CEALUMODE": "DSP_0_CEALUMODE", + "ACOUT20": "DSP_0_ACOUT20", + "P14": "DSP_0_P14", + "C33": "DSP_0_C33", + "P34": "DSP_0_P34", + "C1": "DSP_0_C1", + "BCOUT13": "DSP_0_BCOUT13", + "PCIN42": "DSP_0_PCIN42", + "P39": "DSP_0_P39", + "B7": "DSP_0_B7", + "B10": "DSP_0_B10", + "PCIN16": "DSP_0_PCIN16", + "CARRYINSEL0": "DSP_0_CARRYINSEL0", + "PCOUT26": "DSP_0_PCOUT26", + "C6": "DSP_0_C6", + "CEA2": "DSP_0_CEA2", + "ACOUT5": "DSP_0_ACOUT5", + "PCOUT18": "DSP_0_PCOUT18", + "BCIN10": "DSP_0_BCIN10", + "PCOUT32": "DSP_0_PCOUT32", + "PCIN20": "DSP_0_PCIN20", + "OPMODE5": "DSP_0_OPMODE5", + "A26": "DSP_0_A26", + "PCOUT14": "DSP_0_PCOUT14", + "P13": "DSP_0_P13", + "BCOUT5": "DSP_0_BCOUT5", + "CEAD": "DSP_0_CEAD", + "MULTSIGNIN": "DSP_0_MULTSIGNIN", + "ACOUT14": "DSP_0_ACOUT14", + "D1": "DSP_0_D1", + "OPMODE2": "DSP_0_OPMODE2", + "A12": "DSP_0_A12", + "C41": "DSP_0_C41", + "C10": "DSP_0_C10", + "PCOUT9": "DSP_0_PCOUT9", + "D24": "DSP_0_D24", + "PCIN27": "DSP_0_PCIN27", + "ACOUT1": "DSP_0_ACOUT1", + "ACOUT29": "DSP_0_ACOUT29", + "ACIN25": "DSP_0_ACIN25", + "A3": "DSP_0_A3", + "B9": "DSP_0_B9", + "A21": "DSP_0_A21", + "PCOUT17": "DSP_0_PCOUT17", + "PCOUT34": "DSP_0_PCOUT34", + "PCOUT35": "DSP_0_PCOUT35", + "ACOUT27": "DSP_0_ACOUT27", + "D13": "DSP_0_D13", + "A15": "DSP_0_A15", + "P24": "DSP_0_P24", + "D5": "DSP_0_D5", + "BCOUT2": "DSP_0_BCOUT2", + "CARRYIN": "DSP_0_CARRYIN", + "C37": "DSP_0_C37", + "ACOUT22": "DSP_0_ACOUT22", "C36": "DSP_0_C36", + "ACOUT17": "DSP_0_ACOUT17", + "P1": "DSP_0_P1", + "PCOUT45": "DSP_0_PCOUT45", + "PCIN45": "DSP_0_PCIN45", + "P10": "DSP_0_P10", + "P33": "DSP_0_P33", + "B17": "DSP_0_B17", + "C16": "DSP_0_C16", + "A23": "DSP_0_A23", + "PCIN32": "DSP_0_PCIN32", + "PCOUT40": "DSP_0_PCOUT40", + "A5": "DSP_0_A5", + "INMODE2": "DSP_0_INMODE2", + "RSTA": "DSP_0_RSTA", + "A14": "DSP_0_A14", + "BCOUT7": "DSP_0_BCOUT7", + "ACIN0": "DSP_0_ACIN0", + "PCIN31": "DSP_0_PCIN31", + "PCIN22": "DSP_0_PCIN22", + "PCOUT13": "DSP_0_PCOUT13", + "PCOUT15": "DSP_0_PCOUT15", + "P17": "DSP_0_P17", + "ACIN4": "DSP_0_ACIN4", + "PCIN11": "DSP_0_PCIN11", + "A20": "DSP_0_A20", + "ACIN11": "DSP_0_ACIN11", + "BCOUT9": "DSP_0_BCOUT9", + "OPMODE0": "DSP_0_OPMODE0", + "PCIN12": "DSP_0_PCIN12", + "RSTD": "DSP_0_RSTD", + "A10": "DSP_0_A10", + "ACOUT19": "DSP_0_ACOUT19", + "C25": "DSP_0_C25", + "ACIN28": "DSP_0_ACIN28", + "D6": "DSP_0_D6", + "ACOUT0": "DSP_0_ACOUT0", + "BCOUT1": "DSP_0_BCOUT1", + "P46": "DSP_0_P46", + "P4": "DSP_0_P4", + "C35": "DSP_0_C35", + "D10": "DSP_0_D10", + "C42": "DSP_0_C42", + "P42": "DSP_0_P42", + "PCIN44": "DSP_0_PCIN44", + "PCOUT43": "DSP_0_PCOUT43", + "CEP": "DSP_0_CEP", + "C23": "DSP_0_C23", + "A8": "DSP_0_A8", + "A18": "DSP_0_A18", + "CARRYINSEL2": "DSP_0_CARRYINSEL2", + "ACOUT28": "DSP_0_ACOUT28", + "C29": "DSP_0_C29", + "BCOUT12": "DSP_0_BCOUT12", + "P35": "DSP_0_P35", + "ACOUT8": "DSP_0_ACOUT8", + "RSTP": "DSP_0_RSTP", + "ACIN24": "DSP_0_ACIN24", + "PCIN9": "DSP_0_PCIN9", + "ACIN6": "DSP_0_ACIN6", + "BCOUT14": "DSP_0_BCOUT14", + "P41": "DSP_0_P41", + "BCOUT16": "DSP_0_BCOUT16", + "RSTALUMODE": "DSP_0_RSTALUMODE", + "C8": "DSP_0_C8", + "PCOUT23": "DSP_0_PCOUT23", + "BCOUT8": "DSP_0_BCOUT8", + "C24": "DSP_0_C24", + "C30": "DSP_0_C30", + "ACIN21": "DSP_0_ACIN21", + "ACIN13": "DSP_0_ACIN13", + "PCOUT33": "DSP_0_PCOUT33", + "ACIN19": "DSP_0_ACIN19", + "D21": "DSP_0_D21", + "ACIN20": "DSP_0_ACIN20", + "D23": "DSP_0_D23", + "A19": "DSP_0_A19", + "B16": "DSP_0_B16", + "PCOUT4": "DSP_0_PCOUT4", + "PCOUT27": "DSP_0_PCOUT27", + "PCIN29": "DSP_0_PCIN29", + "CLK": "DSP_0_CLK", + "PCOUT19": "DSP_0_PCOUT19", + "PCOUT47": "DSP_0_PCOUT47", + "PCIN34": "DSP_0_PCIN34", + "D2": "DSP_0_D2", + "P25": "DSP_0_P25", + "ACIN9": "DSP_0_ACIN9", + "BCOUT6": "DSP_0_BCOUT6", + "PCIN21": "DSP_0_PCIN21", + "C3": "DSP_0_C3", + "PCOUT7": "DSP_0_PCOUT7", + "PCOUT31": "DSP_0_PCOUT31", + "PCOUT12": "DSP_0_PCOUT12", + "BCOUT4": "DSP_0_BCOUT4", + "B8": "DSP_0_B8", + "C34": "DSP_0_C34", + "BCIN3": "DSP_0_BCIN3", + "INMODE1": "DSP_0_INMODE1", + "PCIN26": "DSP_0_PCIN26", + "CARRYOUT3": "DSP_0_CARRYOUT3", + "D11": "DSP_0_D11", + "INMODE3": "DSP_0_INMODE3", + "BCOUT15": "DSP_0_BCOUT15", + "D3": "DSP_0_D3", + "P37": "DSP_0_P37", + "PCOUT16": "DSP_0_PCOUT16", + "D8": "DSP_0_D8", + "ACIN18": "DSP_0_ACIN18", + "C21": "DSP_0_C21", + "PCOUT36": "DSP_0_PCOUT36", + "BCIN11": "DSP_0_BCIN11", + "CARRYINSEL1": "DSP_0_CARRYINSEL1", + "D9": "DSP_0_D9", + "C20": "DSP_0_C20", + "ACOUT7": "DSP_0_ACOUT7", + "P26": "DSP_0_P26", + "RSTCTRL": "DSP_0_RSTCTRL", + "RSTC": "DSP_0_RSTC", + "D19": "DSP_0_D19", + "D18": "DSP_0_D18", + "ACIN7": "DSP_0_ACIN7", + "PCIN17": "DSP_0_PCIN17", + "D15": "DSP_0_D15", + "PCOUT1": "DSP_0_PCOUT1", + "RSTALLCARRYIN": "DSP_0_RSTALLCARRYIN", + "PCOUT21": "DSP_0_PCOUT21", + "A9": "DSP_0_A9", + "ALUMODE0": "DSP_0_ALUMODE0", + "BCOUT10": "DSP_0_BCOUT10", + "UNDERFLOW": "DSP_0_UNDERFLOW", + "PCIN35": "DSP_0_PCIN35", + "ACOUT6": "DSP_0_ACOUT6", "C31": "DSP_0_C31", "PCOUT29": "DSP_0_PCOUT29", - "C39": "DSP_0_C39", + "P31": "DSP_0_P31", + "INMODE0": "DSP_0_INMODE0", + "PCOUT22": "DSP_0_PCOUT22", + "PCOUT30": "DSP_0_PCOUT30", "BCIN4": "DSP_0_BCIN4", - "PCIN2": "DSP_0_PCIN2" + "D4": "DSP_0_D4", + "ACIN15": "DSP_0_ACIN15", + "PCIN36": "DSP_0_PCIN36", + "P3": "DSP_0_P3", + "PCIN3": "DSP_0_PCIN3", + "PCOUT37": "DSP_0_PCOUT37", + "OPMODE6": "DSP_0_OPMODE6", + "B14": "DSP_0_B14", + "C39": "DSP_0_C39", + "P22": "DSP_0_P22", + "CEA1": "DSP_0_CEA1", + "PATTERNDETECT": "DSP_0_PATTERNDETECT", + "A16": "DSP_0_A16", + "CARRYCASCIN": "DSP_0_CARRYCASCIN", + "CEINMODE": "DSP_0_CEINMODE", + "P21": "DSP_0_P21", + "BCIN5": "DSP_0_BCIN5", + "PCOUT38": "DSP_0_PCOUT38" }, + "type": "DSP48E1", + "prefix": "DSP48", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 }, { - "prefix": "DSP48", - "y_coord": 1, - "type": "DSP48E1", "site_pins": { - "BCOUT1": "DSP_1_BCOUT1", - "D0": "DSP_1_D0", - "B9": "DSP_1_B9", - "C5": "DSP_1_C5", - "B12": "DSP_1_B12", - "ACOUT12": "DSP_1_ACOUT12", - "C2": "DSP_1_C2", - "BCIN17": "DSP_1_BCIN17", - "CEINMODE": "DSP_1_CEINMODE", - "PCIN10": "DSP_1_PCIN10", - "D12": "DSP_1_D12", - "BCIN3": "DSP_1_BCIN3", - "BCIN5": "DSP_1_BCIN5", - "A9": "DSP_1_A9", - "CARRYCASCIN": "DSP_1_CARRYCASCIN", - "RSTCTRL": "DSP_1_RSTCTRL", - "PCIN41": "DSP_1_PCIN41", - "PCIN16": "DSP_1_PCIN16", - "ACOUT10": "DSP_1_ACOUT10", - "ACOUT0": "DSP_1_ACOUT0", - "ACIN10": "DSP_1_ACIN10", - "C25": "DSP_1_C25", - "PCOUT9": "DSP_1_PCOUT9", - "A10": "DSP_1_A10", - "PCIN3": "DSP_1_PCIN3", - "PCOUT14": "DSP_1_PCOUT14", - "BCIN16": "DSP_1_BCIN16", - "P44": "DSP_1_P44", - "P17": "DSP_1_P17", - "D5": "DSP_1_D5", - "A16": "DSP_1_A16", - "C4": "DSP_1_C4", - "D21": "DSP_1_D21", - "PCOUT43": "DSP_1_PCOUT43", - "ACOUT18": "DSP_1_ACOUT18", - "PCIN37": "DSP_1_PCIN37", - "ACIN0": "DSP_1_ACIN0", - "ACOUT23": "DSP_1_ACOUT23", - "A23": "DSP_1_A23", - "ACOUT28": "DSP_1_ACOUT28", - "RSTD": "DSP_1_RSTD", - "PCOUT36": "DSP_1_PCOUT36", - "CEA1": "DSP_1_CEA1", - "CEP": "DSP_1_CEP", - "C40": "DSP_1_C40", - "ACIN2": "DSP_1_ACIN2", - "BCIN1": "DSP_1_BCIN1", - "PCOUT17": "DSP_1_PCOUT17", - "C20": "DSP_1_C20", "P45": "DSP_1_P45", - "B4": "DSP_1_B4", - "PCIN1": "DSP_1_PCIN1", - "A20": "DSP_1_A20", - "B14": "DSP_1_B14", - "A25": "DSP_1_A25", - "BCOUT13": "DSP_1_BCOUT13", - "ACOUT27": "DSP_1_ACOUT27", - "CARRYOUT0": "DSP_1_CARRYOUT0", - "CARRYOUT2": "DSP_1_CARRYOUT2", - "PCIN0": "DSP_1_PCIN0", - "ACIN11": "DSP_1_ACIN11", - "A14": "DSP_1_A14", - "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", - "ACOUT26": "DSP_1_ACOUT26", - "PCOUT32": "DSP_1_PCOUT32", - "PCOUT40": "DSP_1_PCOUT40", - "ACIN7": "DSP_1_ACIN7", - "CEALUMODE": "DSP_1_CEALUMODE", - "C0": "DSP_1_C0", - "A7": "DSP_1_A7", - "ALUMODE1": "DSP_1_ALUMODE1", - "C8": "DSP_1_C8", - "OPMODE0": "DSP_1_OPMODE0", - "D22": "DSP_1_D22", - "A5": "DSP_1_A5", - "PCIN25": "DSP_1_PCIN25", - "CED": "DSP_1_CED", - "BCIN10": "DSP_1_BCIN10", - "P16": "DSP_1_P16", - "ACIN25": "DSP_1_ACIN25", - "ACOUT25": "DSP_1_ACOUT25", - "PCIN20": "DSP_1_PCIN20", - "CEB2": "DSP_1_CEB2", - "PCIN18": "DSP_1_PCIN18", - "PCIN17": "DSP_1_PCIN17", - "D13": "DSP_1_D13", - "PCOUT19": "DSP_1_PCOUT19", - "OPMODE6": "DSP_1_OPMODE6", - "ACOUT1": "DSP_1_ACOUT1", - "PCOUT7": "DSP_1_PCOUT7", - "P2": "DSP_1_P2", - "OPMODE3": "DSP_1_OPMODE3", - "D2": "DSP_1_D2", - "D24": "DSP_1_D24", - "C3": "DSP_1_C3", - "C32": "DSP_1_C32", - "BCOUT4": "DSP_1_BCOUT4", - "C12": "DSP_1_C12", - "BCOUT0": "DSP_1_BCOUT0", - "ACIN29": "DSP_1_ACIN29", - "A21": "DSP_1_A21", - "C28": "DSP_1_C28", - "PCIN7": "DSP_1_PCIN7", - "PCIN42": "DSP_1_PCIN42", - "BCIN9": "DSP_1_BCIN9", - "PCOUT23": "DSP_1_PCOUT23", - "PCIN36": "DSP_1_PCIN36", - "OPMODE2": "DSP_1_OPMODE2", - "D1": "DSP_1_D1", - "RSTALUMODE": "DSP_1_RSTALUMODE", - "C10": "DSP_1_C10", - "PCOUT4": "DSP_1_PCOUT4", - "C17": "DSP_1_C17", - "D18": "DSP_1_D18", - "C9": "DSP_1_C9", - "PCIN22": "DSP_1_PCIN22", - "PCOUT44": "DSP_1_PCOUT44", - "BCOUT5": "DSP_1_BCOUT5", - "B8": "DSP_1_B8", - "A15": "DSP_1_A15", - "C11": "DSP_1_C11", - "ACIN19": "DSP_1_ACIN19", - "ACOUT22": "DSP_1_ACOUT22", - "P37": "DSP_1_P37", - "D8": "DSP_1_D8", - "D17": "DSP_1_D17", - "PCOUT12": "DSP_1_PCOUT12", - "ACIN21": "DSP_1_ACIN21", - "ACIN26": "DSP_1_ACIN26", - "PCIN4": "DSP_1_PCIN4", - "B1": "DSP_1_B1", - "PCOUT46": "DSP_1_PCOUT46", - "PCIN13": "DSP_1_PCIN13", - "C21": "DSP_1_C21", - "ACIN12": "DSP_1_ACIN12", - "ACIN3": "DSP_1_ACIN3", - "A28": "DSP_1_A28", - "P13": "DSP_1_P13", - "C7": "DSP_1_C7", - "ACOUT2": "DSP_1_ACOUT2", - "PCIN27": "DSP_1_PCIN27", - "B2": "DSP_1_B2", - "PCIN11": "DSP_1_PCIN11", - "CARRYIN": "DSP_1_CARRYIN", - "P25": "DSP_1_P25", - "ACIN16": "DSP_1_ACIN16", - "PCIN14": "DSP_1_PCIN14", - "PCOUT31": "DSP_1_PCOUT31", - "PCIN6": "DSP_1_PCIN6", - "B5": "DSP_1_B5", - "PCIN28": "DSP_1_PCIN28", - "PCIN12": "DSP_1_PCIN12", - "RSTA": "DSP_1_RSTA", - "PCIN40": "DSP_1_PCIN40", - "PCOUT21": "DSP_1_PCOUT21", - "D11": "DSP_1_D11", - "B0": "DSP_1_B0", - "BCOUT3": "DSP_1_BCOUT3", - "BCIN12": "DSP_1_BCIN12", - "CEC": "DSP_1_CEC", - "PCIN45": "DSP_1_PCIN45", - "A8": "DSP_1_A8", - "C33": "DSP_1_C33", "BCIN8": "DSP_1_BCIN8", - "BCOUT11": "DSP_1_BCOUT11", - "OPMODE5": "DSP_1_OPMODE5", - "D9": "DSP_1_D9", - "P33": "DSP_1_P33", - "PCOUT0": "DSP_1_PCOUT0", - "BCIN7": "DSP_1_BCIN7", - "P7": "DSP_1_P7", - "P43": "DSP_1_P43", - "ACIN4": "DSP_1_ACIN4", - "BCOUT2": "DSP_1_BCOUT2", - "C16": "DSP_1_C16", - "PCOUT11": "DSP_1_PCOUT11", - "P4": "DSP_1_P4", - "INMODE1": "DSP_1_INMODE1", - "PCIN21": "DSP_1_PCIN21", - "C38": "DSP_1_C38", - "PCOUT27": "DSP_1_PCOUT27", - "CARRYCASCOUT": "DSP_1_CARRYCASCOUT", - "PCOUT26": "DSP_1_PCOUT26", - "P40": "DSP_1_P40", - "BCOUT14": "DSP_1_BCOUT14", - "BCIN6": "DSP_1_BCIN6", - "D20": "DSP_1_D20", - "P31": "DSP_1_P31", - "D7": "DSP_1_D7", - "ALUMODE3": "DSP_1_ALUMODE3", - "P28": "DSP_1_P28", - "BCIN0": "DSP_1_BCIN0", - "INMODE2": "DSP_1_INMODE2", - "BCOUT17": "DSP_1_BCOUT17", - "ACIN23": "DSP_1_ACIN23", - "C23": "DSP_1_C23", - "ACOUT5": "DSP_1_ACOUT5", - "PCOUT20": "DSP_1_PCOUT20", - "ACIN6": "DSP_1_ACIN6", - "P32": "DSP_1_P32", - "PCOUT8": "DSP_1_PCOUT8", + "CECTRL": "DSP_1_CECTRL", + "PCIN6": "DSP_1_PCIN6", + "PCOUT46": "DSP_1_PCOUT46", + "ACIN22": "DSP_1_ACIN22", + "PCIN14": "DSP_1_PCIN14", + "OVERFLOW": "DSP_1_OVERFLOW", + "ACIN29": "DSP_1_ACIN29", + "A22": "DSP_1_A22", + "ACOUT24": "DSP_1_ACOUT24", "PCIN43": "DSP_1_PCIN43", - "P27": "DSP_1_P27", - "ACIN5": "DSP_1_ACIN5", - "BCOUT6": "DSP_1_BCOUT6", - "C41": "DSP_1_C41", - "D23": "DSP_1_D23", - "ACOUT14": "DSP_1_ACOUT14", - "PCIN47": "DSP_1_PCIN47", - "ACIN17": "DSP_1_ACIN17", - "CARRYOUT3": "DSP_1_CARRYOUT3", - "PCOUT41": "DSP_1_PCOUT41", - "BCOUT12": "DSP_1_BCOUT12", - "B11": "DSP_1_B11", - "PCIN33": "DSP_1_PCIN33", - "PCIN9": "DSP_1_PCIN9", - "PCIN31": "DSP_1_PCIN31", - "C42": "DSP_1_C42", - "ACIN8": "DSP_1_ACIN8", - "A19": "DSP_1_A19", - "PCOUT30": "DSP_1_PCOUT30", + "BCOUT0": "DSP_1_BCOUT0", + "A7": "DSP_1_A7", + "PCIN30": "DSP_1_PCIN30", + "A1": "DSP_1_A1", + "P9": "DSP_1_P9", + "P12": "DSP_1_P12", + "P7": "DSP_1_P7", + "BCIN15": "DSP_1_BCIN15", "PCOUT24": "DSP_1_PCOUT24", - "P41": "DSP_1_P41", - "CARRYINSEL2": "DSP_1_CARRYINSEL2", - "CARRYOUT1": "DSP_1_CARRYOUT1", - "D3": "DSP_1_D3", - "A2": "DSP_1_A2", - "ALUMODE2": "DSP_1_ALUMODE2", - "C6": "DSP_1_C6", - "P46": "DSP_1_P46", - "D14": "DSP_1_D14", - "P29": "DSP_1_P29", - "PCOUT3": "DSP_1_PCOUT3", - "A24": "DSP_1_A24", + "PCIN46": "DSP_1_PCIN46", + "P0": "DSP_1_P0", + "P18": "DSP_1_P18", + "P15": "DSP_1_P15", + "BCIN1": "DSP_1_BCIN1", + "B6": "DSP_1_B6", + "PCIN7": "DSP_1_PCIN7", + "ACIN17": "DSP_1_ACIN17", + "C18": "DSP_1_C18", + "P30": "DSP_1_P30", "C46": "DSP_1_C46", - "B10": "DSP_1_B10", - "BCIN14": "DSP_1_BCIN14", + "P36": "DSP_1_P36", + "C12": "DSP_1_C12", + "PCOUT11": "DSP_1_PCOUT11", + "C32": "DSP_1_C32", + "BCIN12": "DSP_1_BCIN12", + "B11": "DSP_1_B11", + "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", + "PCIN41": "DSP_1_PCIN41", + "P43": "DSP_1_P43", + "A27": "DSP_1_A27", + "C45": "DSP_1_C45", + "B12": "DSP_1_B12", + "ACIN3": "DSP_1_ACIN3", + "P44": "DSP_1_P44", + "PCOUT0": "DSP_1_PCOUT0", + "ACOUT9": "DSP_1_ACOUT9", + "C28": "DSP_1_C28", "ACOUT11": "DSP_1_ACOUT11", "C13": "DSP_1_C13", - "PCOUT16": "DSP_1_PCOUT16", - "BCOUT10": "DSP_1_BCOUT10", - "A22": "DSP_1_A22", - "PCOUT28": "DSP_1_PCOUT28", - "ACOUT6": "DSP_1_ACOUT6", - "BCOUT7": "DSP_1_BCOUT7", - "ACIN27": "DSP_1_ACIN27", - "ACOUT4": "DSP_1_ACOUT4", - "PCOUT39": "DSP_1_PCOUT39", - "P9": "DSP_1_P9", - "C14": "DSP_1_C14", - "PCOUT22": "DSP_1_PCOUT22", - "B13": "DSP_1_B13", - "P19": "DSP_1_P19", - "PCIN15": "DSP_1_PCIN15", - "ACOUT17": "DSP_1_ACOUT17", - "A1": "DSP_1_A1", - "B3": "DSP_1_B3", - "C24": "DSP_1_C24", - "P35": "DSP_1_P35", - "P38": "DSP_1_P38", - "INMODE0": "DSP_1_INMODE0", - "PCIN26": "DSP_1_PCIN26", - "BCOUT9": "DSP_1_BCOUT9", - "P3": "DSP_1_P3", - "ALUMODE0": "DSP_1_ALUMODE0", - "A6": "DSP_1_A6", - "A18": "DSP_1_A18", - "P34": "DSP_1_P34", - "RSTINMODE": "DSP_1_RSTINMODE", - "A0": "DSP_1_A0", - "ACIN22": "DSP_1_ACIN22", - "ACOUT13": "DSP_1_ACOUT13", - "A17": "DSP_1_A17", - "C34": "DSP_1_C34", - "P10": "DSP_1_P10", - "BCIN15": "DSP_1_BCIN15", - "PATTERNDETECT": "DSP_1_PATTERNDETECT", - "C45": "DSP_1_C45", - "PCIN19": "DSP_1_PCIN19", + "C7": "DSP_1_C7", + "BCOUT3": "DSP_1_BCOUT3", + "C40": "DSP_1_C40", + "PCIN24": "DSP_1_PCIN24", + "BCIN16": "DSP_1_BCIN16", + "B5": "DSP_1_B5", + "C15": "DSP_1_C15", + "PCIN23": "DSP_1_PCIN23", + "ACOUT18": "DSP_1_ACOUT18", "BCIN2": "DSP_1_BCIN2", - "CEAD": "DSP_1_CEAD", - "PCIN46": "DSP_1_PCIN46", - "INMODE3": "DSP_1_INMODE3", - "P24": "DSP_1_P24", - "PCIN32": "DSP_1_PCIN32", - "A12": "DSP_1_A12", - "PCOUT35": "DSP_1_PCOUT35", - "C37": "DSP_1_C37", - "P42": "DSP_1_P42", - "PCIN30": "DSP_1_PCIN30", - "P26": "DSP_1_P26", - "ACOUT3": "DSP_1_ACOUT3", - "B6": "DSP_1_B6", - "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", - "ACIN20": "DSP_1_ACIN20", + "C14": "DSP_1_C14", + "C9": "DSP_1_C9", + "D0": "DSP_1_D0", + "A4": "DSP_1_A4", + "ACOUT23": "DSP_1_ACOUT23", + "PCIN33": "DSP_1_PCIN33", + "ACOUT16": "DSP_1_ACOUT16", + "PCIN25": "DSP_1_PCIN25", + "B0": "DSP_1_B0", "CEB1": "DSP_1_CEB1", - "P0": "DSP_1_P0", + "RSTB": "DSP_1_RSTB", + "P16": "DSP_1_P16", + "PCIN18": "DSP_1_PCIN18", + "RSTM": "DSP_1_RSTM", + "PCOUT3": "DSP_1_PCOUT3", + "PCIN40": "DSP_1_PCIN40", + "CARRYOUT2": "DSP_1_CARRYOUT2", + "ALUMODE3": "DSP_1_ALUMODE3", + "C5": "DSP_1_C5", + "BCIN9": "DSP_1_BCIN9", + "D20": "DSP_1_D20", + "BCIN17": "DSP_1_BCIN17", + "C38": "DSP_1_C38", + "A6": "DSP_1_A6", + "A13": "DSP_1_A13", + "CARRYOUT1": "DSP_1_CARRYOUT1", + "P32": "DSP_1_P32", + "C19": "DSP_1_C19", + "C11": "DSP_1_C11", "PCOUT5": "DSP_1_PCOUT5", "PCOUT25": "DSP_1_PCOUT25", - "PCIN23": "DSP_1_PCIN23", - "A3": "DSP_1_A3", - "PCOUT18": "DSP_1_PCOUT18", - "BCOUT8": "DSP_1_BCOUT8", - "P11": "DSP_1_P11", - "ACIN18": "DSP_1_ACIN18", - "B16": "DSP_1_B16", - "MULTSIGNIN": "DSP_1_MULTSIGNIN", - "ACOUT21": "DSP_1_ACOUT21", - "PCIN38": "DSP_1_PCIN38", - "C30": "DSP_1_C30", - "CARRYINSEL0": "DSP_1_CARRYINSEL0", - "C29": "DSP_1_C29", - "C19": "DSP_1_C19", - "ACOUT8": "DSP_1_ACOUT8", - "ACIN13": "DSP_1_ACIN13", - "PCOUT38": "DSP_1_PCOUT38", - "OPMODE1": "DSP_1_OPMODE1", - "PCOUT45": "DSP_1_PCOUT45", - "ACIN24": "DSP_1_ACIN24", - "OPMODE4": "DSP_1_OPMODE4", - "PCIN5": "DSP_1_PCIN5", - "PCOUT6": "DSP_1_PCOUT6", - "D16": "DSP_1_D16", - "ACOUT15": "DSP_1_ACOUT15", - "P12": "DSP_1_P12", - "ACOUT29": "DSP_1_ACOUT29", - "INMODE4": "DSP_1_INMODE4", - "C15": "DSP_1_C15", - "PCIN44": "DSP_1_PCIN44", - "P36": "DSP_1_P36", - "PCOUT2": "DSP_1_PCOUT2", - "C27": "DSP_1_C27", - "P1": "DSP_1_P1", - "CARRYINSEL1": "DSP_1_CARRYINSEL1", - "P8": "DSP_1_P8", - "PCOUT47": "DSP_1_PCOUT47", - "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", - "P18": "DSP_1_P18", - "PCOUT10": "DSP_1_PCOUT10", - "ACIN1": "DSP_1_ACIN1", - "C1": "DSP_1_C1", - "PCIN24": "DSP_1_PCIN24", - "RSTB": "DSP_1_RSTB", - "PCIN29": "DSP_1_PCIN29", - "P30": "DSP_1_P30", - "BCOUT15": "DSP_1_BCOUT15", - "P22": "DSP_1_P22", "BCIN13": "DSP_1_BCIN13", - "PCOUT34": "DSP_1_PCOUT34", - "BCIN11": "DSP_1_BCIN11", - "C18": "DSP_1_C18", - "A11": "DSP_1_A11", - "C43": "DSP_1_C43", - "C35": "DSP_1_C35", - "C47": "DSP_1_C47", - "PCIN34": "DSP_1_PCIN34", + "P38": "DSP_1_P38", + "ACOUT10": "DSP_1_ACOUT10", + "PCIN38": "DSP_1_PCIN38", + "C2": "DSP_1_C2", + "CEB2": "DSP_1_CEB2", "ACIN14": "DSP_1_ACIN14", - "PCIN8": "DSP_1_PCIN8", - "CEA2": "DSP_1_CEA2", - "A4": "DSP_1_A4", - "ACIN28": "DSP_1_ACIN28", - "A13": "DSP_1_A13", - "PCOUT42": "DSP_1_PCOUT42", - "PCOUT15": "DSP_1_PCOUT15", - "D10": "DSP_1_D10", - "CECTRL": "DSP_1_CECTRL", - "P6": "DSP_1_P6", - "ACOUT16": "DSP_1_ACOUT16", - "CEM": "DSP_1_CEM", - "A27": "DSP_1_A27", - "ACIN15": "DSP_1_ACIN15", - "D15": "DSP_1_D15", - "P23": "DSP_1_P23", - "UNDERFLOW": "DSP_1_UNDERFLOW", - "OVERFLOW": "DSP_1_OVERFLOW", - "RSTP": "DSP_1_RSTP", - "P39": "DSP_1_P39", - "CLK": "DSP_1_CLK", - "A29": "DSP_1_A29", - "P15": "DSP_1_P15", - "ACOUT24": "DSP_1_ACOUT24", - "ACOUT9": "DSP_1_ACOUT9", - "CECARRYIN": "DSP_1_CECARRYIN", + "ALUMODE1": "DSP_1_ALUMODE1", "P47": "DSP_1_P47", - "B7": "DSP_1_B7", - "BCOUT16": "DSP_1_BCOUT16", - "PCOUT13": "DSP_1_PCOUT13", - "ACIN9": "DSP_1_ACIN9", - "P14": "DSP_1_P14", - "ACOUT7": "DSP_1_ACOUT7", - "D4": "DSP_1_D4", - "C22": "DSP_1_C22", - "A26": "DSP_1_A26", - "P21": "DSP_1_P21", - "D6": "DSP_1_D6", - "D19": "DSP_1_D19", - "B17": "DSP_1_B17", - "P20": "DSP_1_P20", - "PCIN35": "DSP_1_PCIN35", - "PCIN39": "DSP_1_PCIN39", - "RSTC": "DSP_1_RSTC", - "B15": "DSP_1_B15", - "ACOUT19": "DSP_1_ACOUT19", - "PCOUT37": "DSP_1_PCOUT37", - "ACOUT20": "DSP_1_ACOUT20", + "PCOUT10": "DSP_1_PCOUT10", + "PCIN19": "DSP_1_PCIN19", + "P27": "DSP_1_P27", + "PCOUT39": "DSP_1_PCOUT39", + "P19": "DSP_1_P19", + "D12": "DSP_1_D12", + "ACOUT25": "DSP_1_ACOUT25", + "CEM": "DSP_1_CEM", + "P6": "DSP_1_P6", + "A25": "DSP_1_A25", + "BCIN6": "DSP_1_BCIN6", + "C47": "DSP_1_C47", + "PCIN2": "DSP_1_PCIN2", + "BCIN14": "DSP_1_BCIN14", + "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", + "D16": "DSP_1_D16", + "P2": "DSP_1_P2", + "ACOUT3": "DSP_1_ACOUT3", + "A11": "DSP_1_A11", + "PCIN8": "DSP_1_PCIN8", + "PCIN13": "DSP_1_PCIN13", + "P40": "DSP_1_P40", + "OPMODE3": "DSP_1_OPMODE3", + "BCOUT11": "DSP_1_BCOUT11", + "C4": "DSP_1_C4", + "PCIN4": "DSP_1_PCIN4", + "PCIN28": "DSP_1_PCIN28", + "ACOUT4": "DSP_1_ACOUT4", + "PCOUT2": "DSP_1_PCOUT2", + "BCIN0": "DSP_1_BCIN0", + "ACOUT26": "DSP_1_ACOUT26", + "ACOUT13": "DSP_1_ACOUT13", + "PCIN10": "DSP_1_PCIN10", + "PCOUT6": "DSP_1_PCOUT6", + "C43": "DSP_1_C43", + "A2": "DSP_1_A2", + "ACIN26": "DSP_1_ACIN26", + "CECARRYIN": "DSP_1_CECARRYIN", + "ACOUT15": "DSP_1_ACOUT15", + "PCOUT28": "DSP_1_PCOUT28", + "B2": "DSP_1_B2", + "ACIN1": "DSP_1_ACIN1", + "P23": "DSP_1_P23", + "PCIN0": "DSP_1_PCIN0", + "PCIN47": "DSP_1_PCIN47", + "BCOUT17": "DSP_1_BCOUT17", + "PCOUT42": "DSP_1_PCOUT42", + "D22": "DSP_1_D22", + "CED": "DSP_1_CED", + "ACIN23": "DSP_1_ACIN23", + "ACIN2": "DSP_1_ACIN2", + "A17": "DSP_1_A17", + "PCOUT20": "DSP_1_PCOUT20", + "BCIN7": "DSP_1_BCIN7", + "D14": "DSP_1_D14", + "P8": "DSP_1_P8", + "ALUMODE2": "DSP_1_ALUMODE2", + "D17": "DSP_1_D17", + "ACIN10": "DSP_1_ACIN10", + "OPMODE4": "DSP_1_OPMODE4", "C26": "DSP_1_C26", - "RSTM": "DSP_1_RSTM", - "PCOUT1": "DSP_1_PCOUT1", + "ACIN16": "DSP_1_ACIN16", + "PCIN5": "DSP_1_PCIN5", "C44": "DSP_1_C44", + "ACIN5": "DSP_1_ACIN5", + "PCIN37": "DSP_1_PCIN37", + "PCIN15": "DSP_1_PCIN15", + "PCOUT44": "DSP_1_PCOUT44", + "C22": "DSP_1_C22", + "A0": "DSP_1_A0", + "INMODE4": "DSP_1_INMODE4", + "B3": "DSP_1_B3", + "C0": "DSP_1_C0", + "P29": "DSP_1_P29", + "ACOUT21": "DSP_1_ACOUT21", + "PCIN1": "DSP_1_PCIN1", + "B15": "DSP_1_B15", + "PCIN39": "DSP_1_PCIN39", + "OPMODE1": "DSP_1_OPMODE1", + "ACIN12": "DSP_1_ACIN12", + "ACIN27": "DSP_1_ACIN27", + "PCOUT41": "DSP_1_PCOUT41", + "ACOUT2": "DSP_1_ACOUT2", + "ACIN8": "DSP_1_ACIN8", + "B13": "DSP_1_B13", + "A28": "DSP_1_A28", + "PCOUT8": "DSP_1_PCOUT8", + "P11": "DSP_1_P11", "P5": "DSP_1_P5", - "PCOUT33": "DSP_1_PCOUT33", + "CARRYOUT0": "DSP_1_CARRYOUT0", + "D7": "DSP_1_D7", + "CEC": "DSP_1_CEC", + "ACOUT12": "DSP_1_ACOUT12", + "A29": "DSP_1_A29", + "B1": "DSP_1_B1", + "C17": "DSP_1_C17", + "B4": "DSP_1_B4", + "C27": "DSP_1_C27", + "CARRYCASCOUT": "DSP_1_CARRYCASCOUT", + "P28": "DSP_1_P28", + "A24": "DSP_1_A24", + "RSTINMODE": "DSP_1_RSTINMODE", + "P20": "DSP_1_P20", + "CEALUMODE": "DSP_1_CEALUMODE", + "ACOUT20": "DSP_1_ACOUT20", + "P14": "DSP_1_P14", + "C33": "DSP_1_C33", + "P34": "DSP_1_P34", + "C1": "DSP_1_C1", + "BCOUT13": "DSP_1_BCOUT13", + "PCIN42": "DSP_1_PCIN42", + "P39": "DSP_1_P39", + "B7": "DSP_1_B7", + "B10": "DSP_1_B10", + "PCIN16": "DSP_1_PCIN16", + "CARRYINSEL0": "DSP_1_CARRYINSEL0", + "PCOUT26": "DSP_1_PCOUT26", + "C6": "DSP_1_C6", + "CEA2": "DSP_1_CEA2", + "ACOUT5": "DSP_1_ACOUT5", + "PCOUT18": "DSP_1_PCOUT18", + "BCIN10": "DSP_1_BCIN10", + "PCOUT32": "DSP_1_PCOUT32", + "PCIN20": "DSP_1_PCIN20", + "OPMODE5": "DSP_1_OPMODE5", + "A26": "DSP_1_A26", + "PCOUT14": "DSP_1_PCOUT14", + "P13": "DSP_1_P13", + "BCOUT5": "DSP_1_BCOUT5", + "CEAD": "DSP_1_CEAD", + "MULTSIGNIN": "DSP_1_MULTSIGNIN", + "ACOUT14": "DSP_1_ACOUT14", + "D1": "DSP_1_D1", + "OPMODE2": "DSP_1_OPMODE2", + "A12": "DSP_1_A12", + "C41": "DSP_1_C41", + "C10": "DSP_1_C10", + "PCOUT9": "DSP_1_PCOUT9", + "D24": "DSP_1_D24", + "PCIN27": "DSP_1_PCIN27", + "ACOUT1": "DSP_1_ACOUT1", + "ACOUT29": "DSP_1_ACOUT29", + "ACIN25": "DSP_1_ACIN25", + "A3": "DSP_1_A3", + "B9": "DSP_1_B9", + "A21": "DSP_1_A21", + "PCOUT17": "DSP_1_PCOUT17", + "PCOUT34": "DSP_1_PCOUT34", + "PCOUT35": "DSP_1_PCOUT35", + "ACOUT27": "DSP_1_ACOUT27", + "D13": "DSP_1_D13", + "A15": "DSP_1_A15", + "P24": "DSP_1_P24", + "D5": "DSP_1_D5", + "BCOUT2": "DSP_1_BCOUT2", + "CARRYIN": "DSP_1_CARRYIN", + "C37": "DSP_1_C37", + "ACOUT22": "DSP_1_ACOUT22", "C36": "DSP_1_C36", + "ACOUT17": "DSP_1_ACOUT17", + "P1": "DSP_1_P1", + "PCOUT45": "DSP_1_PCOUT45", + "PCIN45": "DSP_1_PCIN45", + "P10": "DSP_1_P10", + "P33": "DSP_1_P33", + "B17": "DSP_1_B17", + "C16": "DSP_1_C16", + "A23": "DSP_1_A23", + "PCIN32": "DSP_1_PCIN32", + "PCOUT40": "DSP_1_PCOUT40", + "A5": "DSP_1_A5", + "INMODE2": "DSP_1_INMODE2", + "RSTA": "DSP_1_RSTA", + "A14": "DSP_1_A14", + "BCOUT7": "DSP_1_BCOUT7", + "ACIN0": "DSP_1_ACIN0", + "PCIN31": "DSP_1_PCIN31", + "PCIN22": "DSP_1_PCIN22", + "PCOUT13": "DSP_1_PCOUT13", + "PCOUT15": "DSP_1_PCOUT15", + "P17": "DSP_1_P17", + "ACIN4": "DSP_1_ACIN4", + "PCIN11": "DSP_1_PCIN11", + "A20": "DSP_1_A20", + "ACIN11": "DSP_1_ACIN11", + "BCOUT9": "DSP_1_BCOUT9", + "OPMODE0": "DSP_1_OPMODE0", + "PCIN12": "DSP_1_PCIN12", + "RSTD": "DSP_1_RSTD", + "A10": "DSP_1_A10", + "ACOUT19": "DSP_1_ACOUT19", + "C25": "DSP_1_C25", + "ACIN28": "DSP_1_ACIN28", + "D6": "DSP_1_D6", + "ACOUT0": "DSP_1_ACOUT0", + "BCOUT1": "DSP_1_BCOUT1", + "P46": "DSP_1_P46", + "P4": "DSP_1_P4", + "C35": "DSP_1_C35", + "D10": "DSP_1_D10", + "C42": "DSP_1_C42", + "P42": "DSP_1_P42", + "PCIN44": "DSP_1_PCIN44", + "PCOUT43": "DSP_1_PCOUT43", + "CEP": "DSP_1_CEP", + "C23": "DSP_1_C23", + "A8": "DSP_1_A8", + "A18": "DSP_1_A18", + "CARRYINSEL2": "DSP_1_CARRYINSEL2", + "ACOUT28": "DSP_1_ACOUT28", + "C29": "DSP_1_C29", + "BCOUT12": "DSP_1_BCOUT12", + "P35": "DSP_1_P35", + "ACOUT8": "DSP_1_ACOUT8", + "RSTP": "DSP_1_RSTP", + "ACIN24": "DSP_1_ACIN24", + "PCIN9": "DSP_1_PCIN9", + "ACIN6": "DSP_1_ACIN6", + "BCOUT14": "DSP_1_BCOUT14", + "P41": "DSP_1_P41", + "BCOUT16": "DSP_1_BCOUT16", + "RSTALUMODE": "DSP_1_RSTALUMODE", + "C8": "DSP_1_C8", + "PCOUT23": "DSP_1_PCOUT23", + "BCOUT8": "DSP_1_BCOUT8", + "C24": "DSP_1_C24", + "C30": "DSP_1_C30", + "ACIN21": "DSP_1_ACIN21", + "ACIN13": "DSP_1_ACIN13", + "PCOUT33": "DSP_1_PCOUT33", + "ACIN19": "DSP_1_ACIN19", + "D21": "DSP_1_D21", + "ACIN20": "DSP_1_ACIN20", + "D23": "DSP_1_D23", + "A19": "DSP_1_A19", + "B16": "DSP_1_B16", + "PCOUT4": "DSP_1_PCOUT4", + "PCOUT27": "DSP_1_PCOUT27", + "PCIN29": "DSP_1_PCIN29", + "CLK": "DSP_1_CLK", + "PCOUT19": "DSP_1_PCOUT19", + "PCOUT47": "DSP_1_PCOUT47", + "PCIN34": "DSP_1_PCIN34", + "D2": "DSP_1_D2", + "P25": "DSP_1_P25", + "ACIN9": "DSP_1_ACIN9", + "BCOUT6": "DSP_1_BCOUT6", + "PCIN21": "DSP_1_PCIN21", + "C3": "DSP_1_C3", + "PCOUT7": "DSP_1_PCOUT7", + "PCOUT31": "DSP_1_PCOUT31", + "PCOUT12": "DSP_1_PCOUT12", + "BCOUT4": "DSP_1_BCOUT4", + "B8": "DSP_1_B8", + "C34": "DSP_1_C34", + "BCIN3": "DSP_1_BCIN3", + "INMODE1": "DSP_1_INMODE1", + "PCIN26": "DSP_1_PCIN26", + "CARRYOUT3": "DSP_1_CARRYOUT3", + "D11": "DSP_1_D11", + "INMODE3": "DSP_1_INMODE3", + "BCOUT15": "DSP_1_BCOUT15", + "D3": "DSP_1_D3", + "P37": "DSP_1_P37", + "PCOUT16": "DSP_1_PCOUT16", + "D8": "DSP_1_D8", + "ACIN18": "DSP_1_ACIN18", + "C21": "DSP_1_C21", + "PCOUT36": "DSP_1_PCOUT36", + "BCIN11": "DSP_1_BCIN11", + "CARRYINSEL1": "DSP_1_CARRYINSEL1", + "D9": "DSP_1_D9", + "C20": "DSP_1_C20", + "ACOUT7": "DSP_1_ACOUT7", + "P26": "DSP_1_P26", + "RSTCTRL": "DSP_1_RSTCTRL", + "RSTC": "DSP_1_RSTC", + "D19": "DSP_1_D19", + "D18": "DSP_1_D18", + "ACIN7": "DSP_1_ACIN7", + "PCIN17": "DSP_1_PCIN17", + "D15": "DSP_1_D15", + "PCOUT1": "DSP_1_PCOUT1", + "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", + "PCOUT21": "DSP_1_PCOUT21", + "A9": "DSP_1_A9", + "ALUMODE0": "DSP_1_ALUMODE0", + "BCOUT10": "DSP_1_BCOUT10", + "UNDERFLOW": "DSP_1_UNDERFLOW", + "PCIN35": "DSP_1_PCIN35", + "ACOUT6": "DSP_1_ACOUT6", "C31": "DSP_1_C31", "PCOUT29": "DSP_1_PCOUT29", - "C39": "DSP_1_C39", + "P31": "DSP_1_P31", + "INMODE0": "DSP_1_INMODE0", + "PCOUT22": "DSP_1_PCOUT22", + "PCOUT30": "DSP_1_PCOUT30", "BCIN4": "DSP_1_BCIN4", - "PCIN2": "DSP_1_PCIN2" + "D4": "DSP_1_D4", + "ACIN15": "DSP_1_ACIN15", + "PCIN36": "DSP_1_PCIN36", + "P3": "DSP_1_P3", + "PCIN3": "DSP_1_PCIN3", + "PCOUT37": "DSP_1_PCOUT37", + "OPMODE6": "DSP_1_OPMODE6", + "B14": "DSP_1_B14", + "C39": "DSP_1_C39", + "P22": "DSP_1_P22", + "CEA1": "DSP_1_CEA1", + "PATTERNDETECT": "DSP_1_PATTERNDETECT", + "A16": "DSP_1_A16", + "CARRYCASCIN": "DSP_1_CARRYCASCIN", + "CEINMODE": "DSP_1_CEINMODE", + "P21": "DSP_1_P21", + "BCIN5": "DSP_1_BCIN5", + "PCOUT38": "DSP_1_PCOUT38" }, + "type": "DSP48E1", + "prefix": "DSP48", + "name": "X0Y1", "x_coord": 0, - "name": "X0Y1" + "y_coord": 1 }, { - "prefix": "TIEOFF", - "y_coord": 87, - "type": "TIEOFF", "site_pins": { "HARD0": "DSP_GND_L", "HARD1": "DSP_VCC_L" }, + "type": "TIEOFF", + "prefix": "TIEOFF", + "name": "X34Y87", "x_coord": 34, - "name": "X34Y87" + "y_coord": 87 } - ], - "pips": { - "DSP_L.DSP_1_ACOUT14->DSP_ACOUT14": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT14", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT14", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_0", - "is_directional": "1", - "src_wire": "DSP_1_P20", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT41->DSP_1_PCIN41": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN41", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT41", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX17_2->DSP_0_A11": { - "can_invert": "0", - "dst_wire": "DSP_0_A11", - "is_directional": "1", - "src_wire": "DSP_IMUX17_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D23": { - "can_invert": "0", - "dst_wire": "DSP_0_D23", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D12": { - "can_invert": "0", - "dst_wire": "DSP_0_D12", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN0_2->DSP_1_D22": { - "can_invert": "0", - "dst_wire": "DSP_1_D22", - "is_directional": "1", - "src_wire": "DSP_FAN0_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE4", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_CLK0_3->DSP_1_CLK": { - "can_invert": "0", - "dst_wire": "DSP_1_CLK", - "is_directional": "1", - "src_wire": "DSP_CLK0_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D23": { - "can_invert": "0", - "dst_wire": "DSP_1_D23", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP4_2->DSP_1_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE0", - "is_directional": "1", - "src_wire": "DSP_BYP4_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX12_3->DSP_1_C34": { - "can_invert": "0", - "dst_wire": "DSP_1_C34", - "is_directional": "1", - "src_wire": "DSP_IMUX12_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX19_3->DSP_1_CEM": { - "can_invert": "0", - "dst_wire": "DSP_1_CEM", - "is_directional": "1", - "src_wire": "DSP_IMUX19_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT20->DSP_1_PCIN20": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN20", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT20", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT10->DSP_BCOUT10": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT10", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT10", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX41_3->DSP_1_B12": { - "can_invert": "0", - "dst_wire": "DSP_1_B12", - "is_directional": "1", - "src_wire": "DSP_IMUX41_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT6->DSP_1_ACIN6": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN6", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT6", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX39_0->DSP_0_C0": { - "can_invert": "0", - "dst_wire": "DSP_0_C0", - "is_directional": "1", - "src_wire": "DSP_IMUX39_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D18": { - "can_invert": "0", - "dst_wire": "DSP_0_D18", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX43_0->DSP_1_C1": { - "can_invert": "0", - "dst_wire": "DSP_1_C1", - "is_directional": "1", - "src_wire": "DSP_IMUX43_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN7_3->DSP_1_D23": { - "can_invert": "0", - "dst_wire": "DSP_1_D23", - "is_directional": "1", - "src_wire": "DSP_FAN7_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTALLCARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX2_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B8_3", - "is_directional": "1", - "src_wire": "DSP_1_CARRYOUT0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX27_1->DSP_1_C5": { - "can_invert": "0", - "dst_wire": "DSP_1_C5", - "is_directional": "1", - "src_wire": "DSP_IMUX27_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT3->DSP_1_ACIN3": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN3", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT15->DSP_BCOUT15": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT15", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT15", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT3->DSP_1_PCIN3": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN3", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT3", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP4_1->DSP_0_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTD", - "is_directional": "1", - "src_wire": "DSP_BYP4_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D10": { - "can_invert": "0", - "dst_wire": "DSP_0_D10", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP3_0->DSP_0_D2": { - "can_invert": "0", - "dst_wire": "DSP_0_D2", - "is_directional": "1", - "src_wire": "DSP_BYP3_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_3", - "is_directional": "1", - "src_wire": "DSP_0_P34", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN1_0->DSP_1_D20": { - "can_invert": "0", - "dst_wire": "DSP_1_D20", - "is_directional": "1", - "src_wire": "DSP_FAN1_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX4_4->DSP_1_A19": { - "can_invert": "0", - "dst_wire": "DSP_1_A19", - "is_directional": "1", - "src_wire": "DSP_IMUX4_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B9_2", - "is_directional": "1", - "src_wire": "DSP_0_UNDERFLOW", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX33_0->DSP_0_C43": { - "can_invert": "0", - "dst_wire": "DSP_0_C43", - "is_directional": "1", - "src_wire": "DSP_IMUX33_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT23->DSP_1_ACIN23": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN23", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT23", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX27_3->DSP_1_C13": { - "can_invert": "0", - "dst_wire": "DSP_1_C13", - "is_directional": "1", - "src_wire": "DSP_IMUX27_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX17_0->DSP_0_A3": { - "can_invert": "0", - "dst_wire": "DSP_0_A3", - "is_directional": "1", - "src_wire": "DSP_IMUX17_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX40_0->DSP_0_B3": { - "can_invert": "0", - "dst_wire": "DSP_0_B3", - "is_directional": "1", - "src_wire": "DSP_IMUX40_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX44_2->DSP_1_B10": { - "can_invert": "0", - "dst_wire": "DSP_1_B10", - "is_directional": "1", - "src_wire": "DSP_IMUX44_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT13->DSP_PCOUT13": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT13", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT13", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_1_CEAD", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX18_3->DSP_0_C33": { - "can_invert": "0", - "dst_wire": "DSP_0_C33", - "is_directional": "1", - "src_wire": "DSP_IMUX18_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D3": { - "can_invert": "0", - "dst_wire": "DSP_0_D3", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP2_0->DSP_0_D24": { - "can_invert": "0", - "dst_wire": "DSP_0_D24", - "is_directional": "1", - "src_wire": "DSP_BYP2_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX38_4->DSP_0_C36": { - "can_invert": "0", - "dst_wire": "DSP_0_C36", - "is_directional": "1", - "src_wire": "DSP_IMUX38_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT13->DSP_BCOUT13": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT13", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT13", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP0_0->DSP_0_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_BYP0_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D10": { - "can_invert": "0", - "dst_wire": "DSP_0_D10", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX0_4->DSP_1_ALUMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE0", - "is_directional": "1", - "src_wire": "DSP_IMUX0_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_2", - "is_directional": "1", - "src_wire": "DSP_0_OVERFLOW", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_3", - "is_directional": "1", - "src_wire": "DSP_1_P35", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT17->DSP_BCOUT17": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT17", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT17", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D23": { - "can_invert": "0", - "dst_wire": "DSP_1_D23", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX21_4->DSP_0_C18": { - "can_invert": "0", - "dst_wire": "DSP_0_C18", - "is_directional": "1", - "src_wire": "DSP_IMUX21_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_1", - "is_directional": "1", - "src_wire": "DSP_1_P4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT12->DSP_BCOUT12": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT12", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT12", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX9_1->DSP_1_A7": { - "can_invert": "0", - "dst_wire": "DSP_1_A7", - "is_directional": "1", - "src_wire": "DSP_IMUX9_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX12_0->DSP_1_C22": { - "can_invert": "0", - "dst_wire": "DSP_1_C22", - "is_directional": "1", - "src_wire": "DSP_IMUX12_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX19_0->DSP_0_A1": { - "can_invert": "0", - "dst_wire": "DSP_0_A1", - "is_directional": "1", - "src_wire": "DSP_IMUX19_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT29->DSP_ACOUT29": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT29", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT29", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_3", - "is_directional": "1", - "src_wire": "DSP_1_P14", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE2", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX9_2->DSP_1_A11": { - "can_invert": "0", - "dst_wire": "DSP_1_A11", - "is_directional": "1", - "src_wire": "DSP_IMUX9_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT14->DSP_BCOUT14": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT14", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT14", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D18": { - "can_invert": "0", - "dst_wire": "DSP_1_D18", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX10_1->DSP_1_B5": { - "can_invert": "0", - "dst_wire": "DSP_1_B5", - "is_directional": "1", - "src_wire": "DSP_IMUX10_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_CED": { - "can_invert": "0", - "dst_wire": "DSP_1_CED", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP6_2->DSP_0_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE3", - "is_directional": "1", - "src_wire": "DSP_BYP6_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX42_1->DSP_0_RSTINMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTINMODE", - "is_directional": "1", - "src_wire": "DSP_IMUX42_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX43_2->DSP_1_C9": { - "can_invert": "0", - "dst_wire": "DSP_1_C9", - "is_directional": "1", - "src_wire": "DSP_IMUX43_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX37_3->DSP_0_C14": { - "can_invert": "0", - "dst_wire": "DSP_0_C14", - "is_directional": "1", - "src_wire": "DSP_IMUX37_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT43->DSP_PCOUT43": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT43", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT43", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "DSP_0_P26", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "DSP_0_P2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX22_0->DSP_0_B0": { - "can_invert": "0", - "dst_wire": "DSP_0_B0", - "is_directional": "1", - "src_wire": "DSP_IMUX22_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX8_1->DSP_1_B7": { - "can_invert": "0", - "dst_wire": "DSP_1_B7", - "is_directional": "1", - "src_wire": "DSP_IMUX8_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL1_2->DSP_1_RSTA": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTA", - "is_directional": "1", - "src_wire": "DSP_CTRL1_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN4_3->DSP_1_D15": { - "can_invert": "0", - "dst_wire": "DSP_1_D15", - "is_directional": "1", - "src_wire": "DSP_FAN4_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT27->DSP_ACOUT27": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT27", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT27", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX27_4->DSP_1_C17": { - "can_invert": "0", - "dst_wire": "DSP_1_C17", - "is_directional": "1", - "src_wire": "DSP_IMUX27_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX18_1->DSP_0_B5": { - "can_invert": "0", - "dst_wire": "DSP_0_B5", - "is_directional": "1", - "src_wire": "DSP_IMUX18_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "DSP_0_P46", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D1": { - "can_invert": "0", - "dst_wire": "DSP_1_D1", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT42->DSP_1_PCIN42": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN42", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT42", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT10->DSP_PCOUT10": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT10", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT10", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL1_3->DSP_1_RSTM": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTM", - "is_directional": "1", - "src_wire": "DSP_CTRL1_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D6": { - "can_invert": "0", - "dst_wire": "DSP_1_D6", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D1": { - "can_invert": "0", - "dst_wire": "DSP_0_D1", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT21->DSP_PCOUT21": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT21", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT21", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL1_0->DSP_0_RSTA": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTA", - "is_directional": "1", - "src_wire": "DSP_CTRL1_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP3_3->DSP_0_D14": { - "can_invert": "0", - "dst_wire": "DSP_0_D14", - "is_directional": "1", - "src_wire": "DSP_BYP3_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_4", - "is_directional": "1", - "src_wire": "DSP_0_P17", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "DSP_0_P15", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT47->DSP_PCOUT47": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT47", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT47", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "DSP_1_P43", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX14_4->DSP_1_RSTCTRL": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTCTRL", - "is_directional": "1", - "src_wire": "DSP_IMUX14_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT17->DSP_PCOUT17": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT17", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT17", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_2", - "is_directional": "1", - "src_wire": "DSP_0_PATTERNDETECT", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT15->DSP_ACOUT15": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT15", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT15", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX21_0->DSP_0_A2": { - "can_invert": "0", - "dst_wire": "DSP_0_A2", - "is_directional": "1", - "src_wire": "DSP_IMUX21_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP1_3->DSP_0_D15": { - "can_invert": "0", - "dst_wire": "DSP_0_D15", - "is_directional": "1", - "src_wire": "DSP_BYP1_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT37->DSP_PCOUT37": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT37", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT37", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D13": { - "can_invert": "0", - "dst_wire": "DSP_1_D13", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D12": { - "can_invert": "0", - "dst_wire": "DSP_1_D12", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX20_1->DSP_0_C26": { - "can_invert": "0", - "dst_wire": "DSP_0_C26", - "is_directional": "1", - "src_wire": "DSP_IMUX20_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D8": { - "can_invert": "0", - "dst_wire": "DSP_1_D8", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX42_2->DSP_1_B9": { - "can_invert": "0", - "dst_wire": "DSP_1_B9", - "is_directional": "1", - "src_wire": "DSP_IMUX42_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT23->DSP_PCOUT23": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT23", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT23", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN3_1->DSP_1_D4": { - "can_invert": "0", - "dst_wire": "DSP_1_D4", - "is_directional": "1", - "src_wire": "DSP_FAN3_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT4->DSP_1_BCIN4": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN4", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "DSP_0_P42", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_0", - "is_directional": "1", - "src_wire": "DSP_1_P21", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX38_0->DSP_0_C20": { - "can_invert": "0", - "dst_wire": "DSP_0_C20", - "is_directional": "1", - "src_wire": "DSP_IMUX38_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX45_1->DSP_1_A24": { - "can_invert": "0", - "dst_wire": "DSP_1_A24", - "is_directional": "1", - "src_wire": "DSP_IMUX45_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT7->DSP_ACOUT7": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT7", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT7", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX6_1->DSP_0_A27": { - "can_invert": "0", - "dst_wire": "DSP_0_A27", - "is_directional": "1", - "src_wire": "DSP_IMUX6_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX7_1->DSP_0_A25": { - "can_invert": "0", - "dst_wire": "DSP_0_A25", - "is_directional": "1", - "src_wire": "DSP_IMUX7_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN3_4->DSP_1_D16": { - "can_invert": "0", - "dst_wire": "DSP_1_D16", - "is_directional": "1", - "src_wire": "DSP_FAN3_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN6_4->DSP_1_D17": { - "can_invert": "0", - "dst_wire": "DSP_1_D17", - "is_directional": "1", - "src_wire": "DSP_FAN6_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D9": { - "can_invert": "0", - "dst_wire": "DSP_1_D9", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT36->DSP_PCOUT36": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT36", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT36", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN2_0->DSP_0_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_FAN2_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_4", - "is_directional": "1", - "src_wire": "DSP_1_P19", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL0", - "is_directional": "1", - "src_wire": "DSP_IMUX30_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP1_4->DSP_0_D19": { - "can_invert": "0", - "dst_wire": "DSP_0_D19", - "is_directional": "1", - "src_wire": "DSP_BYP1_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP2_3->DSP_0_D23": { - "can_invert": "0", - "dst_wire": "DSP_0_D23", - "is_directional": "1", - "src_wire": "DSP_BYP2_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT19->DSP_PCOUT19": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT19", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT19", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D4": { - "can_invert": "0", - "dst_wire": "DSP_0_D4", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX13_3->DSP_0_ALUMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE1", - "is_directional": "1", - "src_wire": "DSP_IMUX13_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT9->DSP_1_ACIN9": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN9", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT9", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN7_1->DSP_0_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE1", - "is_directional": "1", - "src_wire": "DSP_FAN7_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "DSP_1_P8", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "DSP_0_P22", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX35_2->DSP_0_OPMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE0", - "is_directional": "1", - "src_wire": "DSP_IMUX35_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE0", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT20->DSP_1_ACIN20": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN20", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT20", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "DSP_0_P28", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D4": { - "can_invert": "0", - "dst_wire": "DSP_1_D4", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX45_2->DSP_1_A28": { - "can_invert": "0", - "dst_wire": "DSP_1_A28", - "is_directional": "1", - "src_wire": "DSP_IMUX45_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D8": { - "can_invert": "0", - "dst_wire": "DSP_0_D8", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D6": { - "can_invert": "0", - "dst_wire": "DSP_1_D6", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "DSP_0_P18", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE3", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL1", - "is_directional": "1", - "src_wire": "DSP_IMUX28_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN5_0->DSP_1_D2": { - "can_invert": "0", - "dst_wire": "DSP_1_D2", - "is_directional": "1", - "src_wire": "DSP_FAN5_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT5->DSP_1_ACIN5": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN5", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT5", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D0": { - "can_invert": "0", - "dst_wire": "DSP_0_D0", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX39_1->DSP_0_C4": { - "can_invert": "0", - "dst_wire": "DSP_0_C4", - "is_directional": "1", - "src_wire": "DSP_IMUX39_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX33_2->DSP_0_C11": { - "can_invert": "0", - "dst_wire": "DSP_0_C11", - "is_directional": "1", - "src_wire": "DSP_IMUX33_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT21->DSP_1_PCIN21": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN21", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT21", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_3", - "is_directional": "1", - "src_wire": "DSP_1_P13", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_2", - "is_directional": "1", - "src_wire": "DSP_0_P11", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT14->DSP_1_ACIN14": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN14", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT14", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT34->DSP_PCOUT34": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT34", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT34", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D7": { - "can_invert": "0", - "dst_wire": "DSP_1_D7", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT16->DSP_1_BCIN16": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN16", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT16", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { - "can_invert": "0", - "dst_wire": "DSP_1_MULTSIGNIN", - "is_directional": "1", - "src_wire": "DSP_0_MULTSIGNOUT", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT14->DSP_1_PCIN14": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN14", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT14", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT16->DSP_1_ACIN16": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN16", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT16", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT6->DSP_BCOUT6": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT6", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT6", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT9->DSP_PCOUT9": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT9", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT9", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP6_1->DSP_0_D21": { - "can_invert": "0", - "dst_wire": "DSP_0_D21", - "is_directional": "1", - "src_wire": "DSP_BYP6_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D19": { - "can_invert": "0", - "dst_wire": "DSP_0_D19", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT2->DSP_ACOUT2": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT2", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX35_3->DSP_0_C13": { - "can_invert": "0", - "dst_wire": "DSP_0_C13", - "is_directional": "1", - "src_wire": "DSP_IMUX35_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B9_4", - "is_directional": "1", - "src_wire": "DSP_0_P44", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX23_3->DSP_0_CARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX23_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D20": { - "can_invert": "0", - "dst_wire": "DSP_1_D20", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT24->DSP_ACOUT24": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT24", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT24", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX24_3->DSP_1_C35": { - "can_invert": "0", - "dst_wire": "DSP_1_C35", - "is_directional": "1", - "src_wire": "DSP_IMUX24_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX26_4->DSP_1_C44": { - "can_invert": "0", - "dst_wire": "DSP_1_C44", - "is_directional": "1", - "src_wire": "DSP_IMUX26_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX9_4->DSP_1_OPMODE5": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE5", - "is_directional": "1", - "src_wire": "DSP_IMUX9_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN0_4->DSP_1_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_FAN0_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT12->DSP_PCOUT12": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT12", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT12", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D16": { - "can_invert": "0", - "dst_wire": "DSP_0_D16", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN1_3->DSP_0_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE4", - "is_directional": "1", - "src_wire": "DSP_FAN1_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "DSP_0_P27", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX37_0->DSP_0_C2": { - "can_invert": "0", - "dst_wire": "DSP_0_C2", - "is_directional": "1", - "src_wire": "DSP_IMUX37_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX23_4->DSP_1_RSTINMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTINMODE", - "is_directional": "1", - "src_wire": "DSP_IMUX23_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT25->DSP_PCOUT25": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT25", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT25", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX20_0->DSP_0_C22": { - "can_invert": "0", - "dst_wire": "DSP_0_C22", - "is_directional": "1", - "src_wire": "DSP_IMUX20_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP2_4->DSP_1_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_BYP2_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D20": { - "can_invert": "0", - "dst_wire": "DSP_0_D20", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT14->DSP_1_BCIN14": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN14", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT14", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX40_1->DSP_0_CEA1": { - "can_invert": "0", - "dst_wire": "DSP_0_CEA1", - "is_directional": "1", - "src_wire": "DSP_IMUX40_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT0->DSP_1_ACIN0": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN0", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "DSP_0_P3", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL1_4->DSP_1_RSTB": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTB", - "is_directional": "1", - "src_wire": "DSP_CTRL1_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX33_1->DSP_0_C7": { - "can_invert": "0", - "dst_wire": "DSP_0_C7", - "is_directional": "1", - "src_wire": "DSP_IMUX33_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN2_4->DSP_1_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_FAN2_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D10": { - "can_invert": "0", - "dst_wire": "DSP_1_D10", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX47_4->DSP_0_A16": { - "can_invert": "0", - "dst_wire": "DSP_0_A16", - "is_directional": "1", - "src_wire": "DSP_IMUX47_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX10_3->DSP_1_C33": { - "can_invert": "0", - "dst_wire": "DSP_1_C33", - "is_directional": "1", - "src_wire": "DSP_IMUX10_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX16_2->DSP_0_B11": { - "can_invert": "0", - "dst_wire": "DSP_0_B11", - "is_directional": "1", - "src_wire": "DSP_IMUX16_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX0_2->DSP_0_CECARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_0_CECARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX0_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX25_0->DSP_1_C43": { - "can_invert": "0", - "dst_wire": "DSP_1_C43", - "is_directional": "1", - "src_wire": "DSP_IMUX25_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT6->DSP_ACOUT6": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT6", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT6", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D17": { - "can_invert": "0", - "dst_wire": "DSP_0_D17", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT31->DSP_1_PCIN31": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN31", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT31", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT13->DSP_1_BCIN13": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN13", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT13", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP0_4->DSP_1_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_BYP0_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT3->DSP_BCOUT3": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT3", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT22->DSP_ACOUT22": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT22", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT22", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT45->DSP_1_PCIN45": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN45", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT45", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT6->DSP_1_PCIN6": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN6", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT6", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT45->DSP_PCOUT45": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT45", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT45", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX31_3->DSP_1_C12": { - "can_invert": "0", - "dst_wire": "DSP_1_C12", - "is_directional": "1", - "src_wire": "DSP_IMUX31_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX27_2->DSP_0_OPMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE2", - "is_directional": "1", - "src_wire": "DSP_IMUX27_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN5_3->DSP_1_D14": { - "can_invert": "0", - "dst_wire": "DSP_1_D14", - "is_directional": "1", - "src_wire": "DSP_FAN5_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D21": { - "can_invert": "0", - "dst_wire": "DSP_1_D21", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT0->DSP_1_BCIN0": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN0", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "DSP_1_P18", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_3", - "is_directional": "1", - "src_wire": "DSP_1_P32", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT18->DSP_1_PCIN18": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN18", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT18", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN0_3->DSP_1_CED": { - "can_invert": "0", - "dst_wire": "DSP_1_CED", - "is_directional": "1", - "src_wire": "DSP_FAN0_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX1_1->DSP_0_CEB2": { - "can_invert": "0", - "dst_wire": "DSP_0_CEB2", - "is_directional": "1", - "src_wire": "DSP_IMUX1_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "DSP_1_P47", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT11->DSP_PCOUT11": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT11", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT11", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX20_3->DSP_0_C34": { - "can_invert": "0", - "dst_wire": "DSP_0_C34", - "is_directional": "1", - "src_wire": "DSP_IMUX20_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP3_4->DSP_0_D18": { - "can_invert": "0", - "dst_wire": "DSP_0_D18", - "is_directional": "1", - "src_wire": "DSP_BYP3_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX29_0->DSP_1_C2": { - "can_invert": "0", - "dst_wire": "DSP_1_C2", - "is_directional": "1", - "src_wire": "DSP_IMUX29_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D11": { - "can_invert": "0", - "dst_wire": "DSP_0_D11", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX31_1->DSP_1_C4": { - "can_invert": "0", - "dst_wire": "DSP_1_C4", - "is_directional": "1", - "src_wire": "DSP_IMUX31_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT33->DSP_PCOUT33": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT33", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT33", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX9_0->DSP_1_A3": { - "can_invert": "0", - "dst_wire": "DSP_1_A3", - "is_directional": "1", - "src_wire": "DSP_IMUX9_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_1", - "is_directional": "1", - "src_wire": "DSP_1_P6", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT36->DSP_1_PCIN36": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN36", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT36", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT13->DSP_ACOUT13": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT13", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT13", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX27_0->DSP_1_C40": { - "can_invert": "0", - "dst_wire": "DSP_1_C40", - "is_directional": "1", - "src_wire": "DSP_IMUX27_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE3", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D0": { - "can_invert": "0", - "dst_wire": "DSP_1_D0", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL1_1->DSP_0_RSTM": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTM", - "is_directional": "1", - "src_wire": "DSP_CTRL1_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX28_0->DSP_1_B2": { - "can_invert": "0", - "dst_wire": "DSP_1_B2", - "is_directional": "1", - "src_wire": "DSP_IMUX28_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX36_3->DSP_1_OPMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE2", - "is_directional": "1", - "src_wire": "DSP_IMUX36_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D24": { - "can_invert": "0", - "dst_wire": "DSP_0_D24", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_0", - "is_directional": "1", - "src_wire": "DSP_1_P2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX2_3->DSP_0_B15": { - "can_invert": "0", - "dst_wire": "DSP_0_B15", - "is_directional": "1", - "src_wire": "DSP_IMUX2_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D4": { - "can_invert": "0", - "dst_wire": "DSP_1_D4", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_0", - "is_directional": "1", - "src_wire": "DSP_0_P0", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE1", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT26->DSP_1_PCIN26": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN26", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT26", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT30->DSP_PCOUT30": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT30", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT30", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT37->DSP_1_PCIN37": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN37", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT37", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX11_0->DSP_1_A1": { - "can_invert": "0", - "dst_wire": "DSP_1_A1", - "is_directional": "1", - "src_wire": "DSP_IMUX11_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT9->DSP_1_BCIN9": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN9", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT9", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX13_1->DSP_1_A6": { - "can_invert": "0", - "dst_wire": "DSP_1_A6", - "is_directional": "1", - "src_wire": "DSP_IMUX13_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT10->DSP_1_BCIN10": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN10", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT10", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN7_2->DSP_0_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_FAN7_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP7_2->DSP_0_D8": { - "can_invert": "0", - "dst_wire": "DSP_0_D8", - "is_directional": "1", - "src_wire": "DSP_BYP7_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN6_1->DSP_1_D5": { - "can_invert": "0", - "dst_wire": "DSP_1_D5", - "is_directional": "1", - "src_wire": "DSP_FAN6_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT35->DSP_PCOUT35": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT35", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT35", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP5_2->DSP_0_D9": { - "can_invert": "0", - "dst_wire": "DSP_0_D9", - "is_directional": "1", - "src_wire": "DSP_BYP5_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX33_3->DSP_0_C15": { - "can_invert": "0", - "dst_wire": "DSP_0_C15", - "is_directional": "1", - "src_wire": "DSP_IMUX33_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D6": { - "can_invert": "0", - "dst_wire": "DSP_0_D6", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_1", - "is_directional": "1", - "src_wire": "DSP_1_P27", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_2", - "is_directional": "1", - "src_wire": "DSP_0_P30", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT3->DSP_ACOUT3": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT3", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX39_3->DSP_0_C12": { - "can_invert": "0", - "dst_wire": "DSP_0_C12", - "is_directional": "1", - "src_wire": "DSP_IMUX39_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT0->DSP_ACOUT0": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT0", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_1", - "is_directional": "1", - "src_wire": "DSP_1_P5", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX10_2->DSP_1_C29": { - "can_invert": "0", - "dst_wire": "DSP_1_C29", - "is_directional": "1", - "src_wire": "DSP_IMUX10_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT46->DSP_PCOUT46": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT46", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT46", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX30_2->DSP_0_OPMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE1", - "is_directional": "1", - "src_wire": "DSP_IMUX30_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX8_0->DSP_1_C41": { - "can_invert": "0", - "dst_wire": "DSP_1_C41", - "is_directional": "1", - "src_wire": "DSP_IMUX8_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B8_4", - "is_directional": "1", - "src_wire": "DSP_0_P47", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D0": { - "can_invert": "0", - "dst_wire": "DSP_1_D0", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "DSP_0_P37", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_4", - "is_directional": "1", - "src_wire": "DSP_0_P45", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_4", - "is_directional": "1", - "src_wire": "DSP_1_P45", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX4_0->DSP_1_A23": { - "can_invert": "0", - "dst_wire": "DSP_1_A23", - "is_directional": "1", - "src_wire": "DSP_IMUX4_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX12_2->DSP_0_OPMODE5": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE5", - "is_directional": "1", - "src_wire": "DSP_IMUX12_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT6->DSP_PCOUT6": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT6", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT6", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX34_0->DSP_0_B1": { - "can_invert": "0", - "dst_wire": "DSP_0_B1", - "is_directional": "1", - "src_wire": "DSP_IMUX34_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX44_4->DSP_1_A18": { - "can_invert": "0", - "dst_wire": "DSP_1_A18", - "is_directional": "1", - "src_wire": "DSP_IMUX44_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_4", - "is_directional": "1", - "src_wire": "DSP_1_P17", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX38_2->DSP_0_OPMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE3", - "is_directional": "1", - "src_wire": "DSP_IMUX38_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_1", - "is_directional": "1", - "src_wire": "DSP_1_P7", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP7_1->DSP_0_D4": { - "can_invert": "0", - "dst_wire": "DSP_0_D4", - "is_directional": "1", - "src_wire": "DSP_BYP7_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D24": { - "can_invert": "0", - "dst_wire": "DSP_0_D24", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX31_0->DSP_1_C0": { - "can_invert": "0", - "dst_wire": "DSP_1_C0", - "is_directional": "1", - "src_wire": "DSP_IMUX31_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP3_1->DSP_0_D6": { - "can_invert": "0", - "dst_wire": "DSP_0_D6", - "is_directional": "1", - "src_wire": "DSP_BYP3_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP1_1->DSP_0_D7": { - "can_invert": "0", - "dst_wire": "DSP_0_D7", - "is_directional": "1", - "src_wire": "DSP_BYP1_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT3->DSP_PCOUT3": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT3", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX45_0->DSP_1_A20": { - "can_invert": "0", - "dst_wire": "DSP_1_A20", - "is_directional": "1", - "src_wire": "DSP_IMUX45_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_2", - "is_directional": "1", - "src_wire": "DSP_1_P29", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_CED": { - "can_invert": "0", - "dst_wire": "DSP_1_CED", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX0_3->DSP_1_B15": { - "can_invert": "0", - "dst_wire": "DSP_1_B15", - "is_directional": "1", - "src_wire": "DSP_IMUX0_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "DSP_1_CARRYOUT3", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN6_3->DSP_1_D13": { - "can_invert": "0", - "dst_wire": "DSP_1_D13", - "is_directional": "1", - "src_wire": "DSP_FAN6_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D4": { - "can_invert": "0", - "dst_wire": "DSP_0_D4", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX34_1->DSP_0_C25": { - "can_invert": "0", - "dst_wire": "DSP_0_C25", - "is_directional": "1", - "src_wire": "DSP_IMUX34_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT0->DSP_1_PCIN0": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN0", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL1", - "is_directional": "1", - "src_wire": "DSP_IMUX14_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX6_2->DSP_0_C28": { - "can_invert": "0", - "dst_wire": "DSP_0_C28", - "is_directional": "1", - "src_wire": "DSP_IMUX6_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP5_4->DSP_0_D17": { - "can_invert": "0", - "dst_wire": "DSP_0_D17", - "is_directional": "1", - "src_wire": "DSP_BYP5_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT16->DSP_ACOUT16": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT16", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT16", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D5": { - "can_invert": "0", - "dst_wire": "DSP_0_D5", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_1_CEAD", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE4", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX28_2->DSP_1_C30": { - "can_invert": "0", - "dst_wire": "DSP_1_C30", - "is_directional": "1", - "src_wire": "DSP_IMUX28_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX3_0->DSP_0_C1": { - "can_invert": "0", - "dst_wire": "DSP_0_C1", - "is_directional": "1", - "src_wire": "DSP_IMUX3_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL0", - "is_directional": "1", - "src_wire": "DSP_IMUX36_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX15_1->DSP_1_A4": { - "can_invert": "0", - "dst_wire": "DSP_1_A4", - "is_directional": "1", - "src_wire": "DSP_IMUX15_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT27->DSP_PCOUT27": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT27", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT27", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D19": { - "can_invert": "0", - "dst_wire": "DSP_1_D19", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX7_2->DSP_0_A29": { - "can_invert": "0", - "dst_wire": "DSP_0_A29", - "is_directional": "1", - "src_wire": "DSP_IMUX7_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D5": { - "can_invert": "0", - "dst_wire": "DSP_1_D5", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_3", - "is_directional": "1", - "src_wire": "DSP_0_P33", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX32_0->DSP_0_C23": { - "can_invert": "0", - "dst_wire": "DSP_0_C23", - "is_directional": "1", - "src_wire": "DSP_IMUX32_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT8->DSP_ACOUT8": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT8", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT8", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX29_1->DSP_1_C6": { - "can_invert": "0", - "dst_wire": "DSP_1_C6", - "is_directional": "1", - "src_wire": "DSP_IMUX29_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D17": { - "can_invert": "0", - "dst_wire": "DSP_1_D17", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT12->DSP_1_PCIN12": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN12", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT12", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX6_0->DSP_0_A23": { - "can_invert": "0", - "dst_wire": "DSP_0_A23", - "is_directional": "1", - "src_wire": "DSP_IMUX6_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D12": { - "can_invert": "0", - "dst_wire": "DSP_0_D12", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX46_1->DSP_0_A26": { - "can_invert": "0", - "dst_wire": "DSP_0_A26", - "is_directional": "1", - "src_wire": "DSP_IMUX46_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE4", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX22_4->DSP_1_RSTALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTALUMODE", - "is_directional": "1", - "src_wire": "DSP_IMUX22_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT11->DSP_BCOUT11": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT11", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT11", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT1->DSP_1_PCIN1": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN1", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT20->DSP_ACOUT20": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT20", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT20", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT10->DSP_ACOUT10": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT10", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT10", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT12->DSP_1_ACIN12": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN12", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT12", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX18_0->DSP_0_C21": { - "can_invert": "0", - "dst_wire": "DSP_0_C21", - "is_directional": "1", - "src_wire": "DSP_IMUX18_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT42->DSP_PCOUT42": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT42", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT42", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN3_2->DSP_1_D8": { - "can_invert": "0", - "dst_wire": "DSP_1_D8", - "is_directional": "1", - "src_wire": "DSP_FAN3_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT23->DSP_1_PCIN23": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN23", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT23", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX8_2->DSP_1_B11": { - "can_invert": "0", - "dst_wire": "DSP_1_B11", - "is_directional": "1", - "src_wire": "DSP_IMUX8_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT17->DSP_1_ACIN17": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN17", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT17", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT1->DSP_1_ACIN1": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN1", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX7_0->DSP_0_A21": { - "can_invert": "0", - "dst_wire": "DSP_0_A21", - "is_directional": "1", - "src_wire": "DSP_IMUX7_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX46_2->DSP_1_C28": { - "can_invert": "0", - "dst_wire": "DSP_1_C28", - "is_directional": "1", - "src_wire": "DSP_IMUX46_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTD", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D13": { - "can_invert": "0", - "dst_wire": "DSP_1_D13", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_1", - "is_directional": "1", - "src_wire": "DSP_1_P25", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT12->DSP_1_BCIN12": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN12", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT12", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX37_2->DSP_0_C10": { - "can_invert": "0", - "dst_wire": "DSP_0_C10", - "is_directional": "1", - "src_wire": "DSP_IMUX37_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX41_0->DSP_1_C3": { - "can_invert": "0", - "dst_wire": "DSP_1_C3", - "is_directional": "1", - "src_wire": "DSP_IMUX41_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_3", - "is_directional": "1", - "src_wire": "DSP_0_P12", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX41_2->DSP_0_CECTRL": { - "can_invert": "0", - "dst_wire": "DSP_0_CECTRL", - "is_directional": "1", - "src_wire": "DSP_IMUX41_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP6_0->DSP_0_D20": { - "can_invert": "0", - "dst_wire": "DSP_0_D20", - "is_directional": "1", - "src_wire": "DSP_BYP6_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D2": { - "can_invert": "0", - "dst_wire": "DSP_1_D2", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT19->DSP_1_PCIN19": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN19", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT19", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX46_0->DSP_0_A22": { - "can_invert": "0", - "dst_wire": "DSP_0_A22", - "is_directional": "1", - "src_wire": "DSP_IMUX46_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D24": { - "can_invert": "0", - "dst_wire": "DSP_1_D24", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX19_1->DSP_0_A5": { - "can_invert": "0", - "dst_wire": "DSP_0_A5", - "is_directional": "1", - "src_wire": "DSP_IMUX19_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL0_3->DSP_1_RSTC": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTC", - "is_directional": "1", - "src_wire": "DSP_CTRL0_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN7_4->DSP_1_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE2", - "is_directional": "1", - "src_wire": "DSP_FAN7_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D9": { - "can_invert": "0", - "dst_wire": "DSP_1_D9", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_4", - "is_directional": "1", - "src_wire": "DSP_0_P16", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT13->DSP_1_PCIN13": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN13", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT13", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX9_3->DSP_1_CEA1": { - "can_invert": "0", - "dst_wire": "DSP_1_CEA1", - "is_directional": "1", - "src_wire": "DSP_IMUX9_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D22": { - "can_invert": "0", - "dst_wire": "DSP_0_D22", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "DSP_0_P14", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "DSP_1_PATTERNDETECT", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT5->DSP_1_PCIN5": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN5", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT5", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT44->DSP_PCOUT44": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT44", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT44", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT8->DSP_1_BCIN8": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN8", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT8", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D23": { - "can_invert": "0", - "dst_wire": "DSP_0_D23", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX41_1->DSP_0_CEB1": { - "can_invert": "0", - "dst_wire": "DSP_0_CEB1", - "is_directional": "1", - "src_wire": "DSP_IMUX41_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT8->DSP_PCOUT8": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT8", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT8", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT15->DSP_1_PCIN15": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN15", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT15", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_4", - "is_directional": "1", - "src_wire": "DSP_1_P39", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX37_1->DSP_0_C6": { - "can_invert": "0", - "dst_wire": "DSP_0_C6", - "is_directional": "1", - "src_wire": "DSP_IMUX37_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D7": { - "can_invert": "0", - "dst_wire": "DSP_0_D7", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D5": { - "can_invert": "0", - "dst_wire": "DSP_1_D5", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX0_0->DSP_1_B3": { - "can_invert": "0", - "dst_wire": "DSP_1_B3", - "is_directional": "1", - "src_wire": "DSP_IMUX0_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN4_2->DSP_1_D11": { - "can_invert": "0", - "dst_wire": "DSP_1_D11", - "is_directional": "1", - "src_wire": "DSP_FAN4_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT35->DSP_1_PCIN35": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN35", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT35", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D14": { - "can_invert": "0", - "dst_wire": "DSP_1_D14", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT7->DSP_1_BCIN7": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN7", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT7", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D10": { - "can_invert": "0", - "dst_wire": "DSP_1_D10", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX15_3->DSP_1_CARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX15_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX1_3->DSP_1_B13": { - "can_invert": "0", - "dst_wire": "DSP_1_B13", - "is_directional": "1", - "src_wire": "DSP_IMUX1_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_2", - "is_directional": "1", - "src_wire": "DSP_0_P10", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "DSP_0_P43", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTD", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT41->DSP_PCOUT41": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT41", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT41", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_4", - "is_directional": "1", - "src_wire": "DSP_0_P39", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX44_0->DSP_1_A22": { - "can_invert": "0", - "dst_wire": "DSP_1_A22", - "is_directional": "1", - "src_wire": "DSP_IMUX44_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT46->DSP_1_PCIN46": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN46", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT46", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT16->DSP_BCOUT16": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT16", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT16", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX45_4->DSP_1_A16": { - "can_invert": "0", - "dst_wire": "DSP_1_A16", - "is_directional": "1", - "src_wire": "DSP_IMUX45_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D6": { - "can_invert": "0", - "dst_wire": "DSP_0_D6", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE2", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX43_4->DSP_0_B16": { - "can_invert": "0", - "dst_wire": "DSP_0_B16", - "is_directional": "1", - "src_wire": "DSP_IMUX43_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX46_4->DSP_0_A18": { - "can_invert": "0", - "dst_wire": "DSP_0_A18", - "is_directional": "1", - "src_wire": "DSP_IMUX46_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX11_3->DSP_1_CECTRL": { - "can_invert": "0", - "dst_wire": "DSP_1_CECTRL", - "is_directional": "1", - "src_wire": "DSP_IMUX11_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_3", - "is_directional": "1", - "src_wire": "DSP_1_CARRYOUT1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX12_1->DSP_1_C26": { - "can_invert": "0", - "dst_wire": "DSP_1_C26", - "is_directional": "1", - "src_wire": "DSP_IMUX12_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "DSP_0_P21", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX36_0->DSP_0_B2": { - "can_invert": "0", - "dst_wire": "DSP_0_B2", - "is_directional": "1", - "src_wire": "DSP_IMUX36_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP4_4->DSP_1_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE3", - "is_directional": "1", - "src_wire": "DSP_BYP4_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D7": { - "can_invert": "0", - "dst_wire": "DSP_0_D7", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX4_3->DSP_1_A15": { - "can_invert": "0", - "dst_wire": "DSP_1_A15", - "is_directional": "1", - "src_wire": "DSP_IMUX4_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL0_1->DSP_0_RSTC": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTC", - "is_directional": "1", - "src_wire": "DSP_CTRL0_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN6_2->DSP_1_D9": { - "can_invert": "0", - "dst_wire": "DSP_1_D9", - "is_directional": "1", - "src_wire": "DSP_FAN6_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX21_3->DSP_0_ALUMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE0", - "is_directional": "1", - "src_wire": "DSP_IMUX21_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE3", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP7_3->DSP_0_D12": { - "can_invert": "0", - "dst_wire": "DSP_0_D12", - "is_directional": "1", - "src_wire": "DSP_BYP7_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_0_CEAD", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX47_0->DSP_0_A20": { - "can_invert": "0", - "dst_wire": "DSP_0_A20", - "is_directional": "1", - "src_wire": "DSP_IMUX47_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX16_1->DSP_0_B7": { - "can_invert": "0", - "dst_wire": "DSP_0_B7", - "is_directional": "1", - "src_wire": "DSP_IMUX16_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D17": { - "can_invert": "0", - "dst_wire": "DSP_1_D17", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX32_4->DSP_0_C37": { - "can_invert": "0", - "dst_wire": "DSP_0_C37", - "is_directional": "1", - "src_wire": "DSP_IMUX32_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX32_3->DSP_0_C35": { - "can_invert": "0", - "dst_wire": "DSP_0_C35", - "is_directional": "1", - "src_wire": "DSP_IMUX32_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT9->DSP_ACOUT9": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT9", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT9", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT28->DSP_1_ACIN28": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN28", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT28", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX6_4->DSP_0_A19": { - "can_invert": "0", - "dst_wire": "DSP_0_A19", - "is_directional": "1", - "src_wire": "DSP_IMUX6_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP5_0->DSP_0_D1": { - "can_invert": "0", - "dst_wire": "DSP_0_D1", - "is_directional": "1", - "src_wire": "DSP_BYP5_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "DSP_0_P35", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D9": { - "can_invert": "0", - "dst_wire": "DSP_0_D9", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT28->DSP_1_PCIN28": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN28", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT28", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT3->DSP_1_BCIN3": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN3", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT15->DSP_PCOUT15": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT15", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT15", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN5_1->DSP_1_D6": { - "can_invert": "0", - "dst_wire": "DSP_1_D6", - "is_directional": "1", - "src_wire": "DSP_FAN5_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX35_1->DSP_0_C5": { - "can_invert": "0", - "dst_wire": "DSP_0_C5", - "is_directional": "1", - "src_wire": "DSP_IMUX35_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D7": { - "can_invert": "0", - "dst_wire": "DSP_1_D7", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D21": { - "can_invert": "0", - "dst_wire": "DSP_1_D21", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT23->DSP_ACOUT23": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT23", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT23", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX29_4->DSP_1_C45": { - "can_invert": "0", - "dst_wire": "DSP_1_C45", - "is_directional": "1", - "src_wire": "DSP_IMUX29_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "DSP_1_P37", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_4", - "is_directional": "1", - "src_wire": "DSP_1_P16", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX26_2->DSP_1_CEP": { - "can_invert": "0", - "dst_wire": "DSP_1_CEP", - "is_directional": "1", - "src_wire": "DSP_IMUX26_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D2": { - "can_invert": "0", - "dst_wire": "DSP_1_D2", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT18->DSP_PCOUT18": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT18", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT18", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX29_2->DSP_1_C10": { - "can_invert": "0", - "dst_wire": "DSP_1_C10", - "is_directional": "1", - "src_wire": "DSP_IMUX29_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTD", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP3_2->DSP_0_D10": { - "can_invert": "0", - "dst_wire": "DSP_0_D10", - "is_directional": "1", - "src_wire": "DSP_BYP3_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX19_4->DSP_0_C46": { - "can_invert": "0", - "dst_wire": "DSP_0_C46", - "is_directional": "1", - "src_wire": "DSP_IMUX19_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN7_0->DSP_1_D24": { - "can_invert": "0", - "dst_wire": "DSP_1_D24", - "is_directional": "1", - "src_wire": "DSP_FAN7_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP5_1->DSP_0_D5": { - "can_invert": "0", - "dst_wire": "DSP_0_D5", - "is_directional": "1", - "src_wire": "DSP_BYP5_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_1", - "is_directional": "1", - "src_wire": "DSP_0_P25", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D1": { - "can_invert": "0", - "dst_wire": "DSP_1_D1", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "DSP_0_P36", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D9": { - "can_invert": "0", - "dst_wire": "DSP_0_D9", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT31->DSP_PCOUT31": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT31", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT31", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN2_3->DSP_1_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_FAN2_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT10->DSP_1_PCIN10": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN10", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT10", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "DSP_0_P32", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX5_2->DSP_1_A29": { - "can_invert": "0", - "dst_wire": "DSP_1_A29", - "is_directional": "1", - "src_wire": "DSP_IMUX5_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "DSP_1_CARRYOUT2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT17->DSP_ACOUT17": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT17", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT17", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_2", - "is_directional": "1", - "src_wire": "DSP_0_P9", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX12_4->DSP_1_C38": { - "can_invert": "0", - "dst_wire": "DSP_1_C38", - "is_directional": "1", - "src_wire": "DSP_IMUX12_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX40_4->DSP_1_ALUMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE1", - "is_directional": "1", - "src_wire": "DSP_IMUX40_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D22": { - "can_invert": "0", - "dst_wire": "DSP_0_D22", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT26->DSP_1_ACIN26": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN26", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT26", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX40_3->DSP_1_B14": { - "can_invert": "0", - "dst_wire": "DSP_1_B14", - "is_directional": "1", - "src_wire": "DSP_IMUX40_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "DSP_0_CARRYOUT2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT11->DSP_1_ACIN11": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN11", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT11", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX42_0->DSP_0_C42": { - "can_invert": "0", - "dst_wire": "DSP_0_C42", - "is_directional": "1", - "src_wire": "DSP_IMUX42_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT11->DSP_1_BCIN11": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN11", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT11", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX25_1->DSP_1_C7": { - "can_invert": "0", - "dst_wire": "DSP_1_C7", - "is_directional": "1", - "src_wire": "DSP_IMUX25_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT8->DSP_1_ACIN8": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN8", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT8", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_2", - "is_directional": "1", - "src_wire": "DSP_1_P31", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT8->DSP_1_PCIN8": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN8", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT8", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX39_4->DSP_0_C16": { - "can_invert": "0", - "dst_wire": "DSP_0_C16", - "is_directional": "1", - "src_wire": "DSP_IMUX39_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN4_0->DSP_1_D3": { - "can_invert": "0", - "dst_wire": "DSP_1_D3", - "is_directional": "1", - "src_wire": "DSP_FAN4_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN2_2->DSP_1_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE4", - "is_directional": "1", - "src_wire": "DSP_FAN2_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT24->DSP_1_ACIN24": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN24", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT24", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX26_1->DSP_1_C25": { - "can_invert": "0", - "dst_wire": "DSP_1_C25", - "is_directional": "1", - "src_wire": "DSP_IMUX26_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX24_4->DSP_1_C37": { - "can_invert": "0", - "dst_wire": "DSP_1_C37", - "is_directional": "1", - "src_wire": "DSP_IMUX24_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX23_1->DSP_0_A4": { - "can_invert": "0", - "dst_wire": "DSP_0_A4", - "is_directional": "1", - "src_wire": "DSP_IMUX23_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_0", - "is_directional": "1", - "src_wire": "DSP_0_P1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX31_2->DSP_1_C8": { - "can_invert": "0", - "dst_wire": "DSP_1_C8", - "is_directional": "1", - "src_wire": "DSP_IMUX31_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT40->DSP_PCOUT40": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT40", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT40", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX5_1->DSP_1_A25": { - "can_invert": "0", - "dst_wire": "DSP_1_A25", - "is_directional": "1", - "src_wire": "DSP_IMUX5_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D18": { - "can_invert": "0", - "dst_wire": "DSP_0_D18", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT29->DSP_PCOUT29": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT29", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT29", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_1", - "is_directional": "1", - "src_wire": "DSP_1_P26", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX18_2->DSP_0_B9": { - "can_invert": "0", - "dst_wire": "DSP_0_B9", - "is_directional": "1", - "src_wire": "DSP_IMUX18_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX31_4->DSP_1_C16": { - "can_invert": "0", - "dst_wire": "DSP_1_C16", - "is_directional": "1", - "src_wire": "DSP_IMUX31_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX3_1->DSP_0_RSTALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTALUMODE", - "is_directional": "1", - "src_wire": "DSP_IMUX3_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_2", - "is_directional": "1", - "src_wire": "DSP_1_P9", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX8_3->DSP_1_CEB1": { - "can_invert": "0", - "dst_wire": "DSP_1_CEB1", - "is_directional": "1", - "src_wire": "DSP_IMUX8_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX16_3->DSP_1_CEB2": { - "can_invert": "0", - "dst_wire": "DSP_1_CEB2", - "is_directional": "1", - "src_wire": "DSP_IMUX16_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT18->DSP_ACOUT18": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT18", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT18", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT21->DSP_1_ACIN21": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN21", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT21", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX14_0->DSP_1_B0": { - "can_invert": "0", - "dst_wire": "DSP_1_B0", - "is_directional": "1", - "src_wire": "DSP_IMUX14_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT11->DSP_1_PCIN11": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN11", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT11", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D18": { - "can_invert": "0", - "dst_wire": "DSP_1_D18", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX0_1->DSP_0_CEA2": { - "can_invert": "0", - "dst_wire": "DSP_0_CEA2", - "is_directional": "1", - "src_wire": "DSP_IMUX0_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D22": { - "can_invert": "0", - "dst_wire": "DSP_1_D22", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "DSP_1_P36", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT22->DSP_PCOUT22": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT22", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT22", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT6->DSP_1_BCIN6": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN6", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT6", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX26_3->DSP_1_CECARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_1_CECARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX26_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT4->DSP_1_ACIN4": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN4", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT4", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX10_4->DSP_1_C39": { - "can_invert": "0", - "dst_wire": "DSP_1_C39", - "is_directional": "1", - "src_wire": "DSP_IMUX10_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT4->DSP_PCOUT4": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT4", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT38->DSP_PCOUT38": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT38", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT38", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT29->DSP_1_ACIN29": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN29", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT29", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT12->DSP_ACOUT12": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT12", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT12", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX24_0->DSP_1_C23": { - "can_invert": "0", - "dst_wire": "DSP_1_C23", - "is_directional": "1", - "src_wire": "DSP_IMUX24_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX26_0->DSP_1_B1": { - "can_invert": "0", - "dst_wire": "DSP_1_B1", - "is_directional": "1", - "src_wire": "DSP_IMUX26_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "DSP_1_P42", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX20_4->DSP_0_C38": { - "can_invert": "0", - "dst_wire": "DSP_0_C38", - "is_directional": "1", - "src_wire": "DSP_IMUX20_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D11": { - "can_invert": "0", - "dst_wire": "DSP_1_D11", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D14": { - "can_invert": "0", - "dst_wire": "DSP_0_D14", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT17->DSP_1_PCIN17": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN17", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT17", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_0", - "is_directional": "1", - "src_wire": "DSP_1_P1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE0", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT32->DSP_PCOUT32": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT32", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT32", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX13_0->DSP_1_A2": { - "can_invert": "0", - "dst_wire": "DSP_1_A2", - "is_directional": "1", - "src_wire": "DSP_IMUX13_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP4_0->DSP_0_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_BYP4_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_CLK0_1->DSP_0_CLK": { - "can_invert": "0", - "dst_wire": "DSP_0_CLK", - "is_directional": "1", - "src_wire": "DSP_CLK0_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT10->DSP_1_ACIN10": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN10", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT10", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE2", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT4->DSP_ACOUT4": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT4", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT4", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE4", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX1_0->DSP_0_C3": { - "can_invert": "0", - "dst_wire": "DSP_0_C3", - "is_directional": "1", - "src_wire": "DSP_IMUX1_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_2", - "is_directional": "1", - "src_wire": "DSP_1_P30", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT18->DSP_1_ACIN18": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN18", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT18", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTD", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D17": { - "can_invert": "0", - "dst_wire": "DSP_0_D17", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT7->DSP_PCOUT7": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT7", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT7", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX30_1->DSP_1_B4": { - "can_invert": "0", - "dst_wire": "DSP_1_B4", - "is_directional": "1", - "src_wire": "DSP_IMUX30_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "DSP_0_P41", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX25_3->DSP_1_C15": { - "can_invert": "0", - "dst_wire": "DSP_1_C15", - "is_directional": "1", - "src_wire": "DSP_IMUX25_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT39->DSP_1_PCIN39": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN39", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT39", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX37_4->DSP_0_C45": { - "can_invert": "0", - "dst_wire": "DSP_0_C45", - "is_directional": "1", - "src_wire": "DSP_IMUX37_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX22_1->DSP_0_C24": { - "can_invert": "0", - "dst_wire": "DSP_0_C24", - "is_directional": "1", - "src_wire": "DSP_IMUX22_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_3", - "is_directional": "1", - "src_wire": "DSP_1_P34", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX39_2->DSP_0_C8": { - "can_invert": "0", - "dst_wire": "DSP_0_C8", - "is_directional": "1", - "src_wire": "DSP_IMUX39_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX47_2->DSP_0_A28": { - "can_invert": "0", - "dst_wire": "DSP_0_A28", - "is_directional": "1", - "src_wire": "DSP_IMUX47_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX47_1->DSP_0_A24": { - "can_invert": "0", - "dst_wire": "DSP_0_A24", - "is_directional": "1", - "src_wire": "DSP_IMUX47_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX25_4->DSP_1_C47": { - "can_invert": "0", - "dst_wire": "DSP_1_C47", - "is_directional": "1", - "src_wire": "DSP_IMUX25_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX2_2->DSP_0_C29": { - "can_invert": "0", - "dst_wire": "DSP_0_C29", - "is_directional": "1", - "src_wire": "DSP_IMUX2_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX2_0->DSP_1_C42": { - "can_invert": "0", - "dst_wire": "DSP_1_C42", - "is_directional": "1", - "src_wire": "DSP_IMUX2_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX34_4->DSP_0_C44": { - "can_invert": "0", - "dst_wire": "DSP_0_C44", - "is_directional": "1", - "src_wire": "DSP_IMUX34_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX11_4->DSP_1_C46": { - "can_invert": "0", - "dst_wire": "DSP_1_C46", - "is_directional": "1", - "src_wire": "DSP_IMUX11_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT4->DSP_1_PCIN4": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN4", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_2", - "is_directional": "1", - "src_wire": "DSP_1_P11", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT27->DSP_1_ACIN27": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN27", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT27", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D3": { - "can_invert": "0", - "dst_wire": "DSP_1_D3", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE0", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX22_2->DSP_0_B8": { - "can_invert": "0", - "dst_wire": "DSP_0_B8", - "is_directional": "1", - "src_wire": "DSP_IMUX22_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT2->DSP_1_BCIN2": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN2", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_1", - "is_directional": "1", - "src_wire": "DSP_0_CARRYOUT1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT40->DSP_1_PCIN40": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN40", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT40", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX44_3->DSP_1_A14": { - "can_invert": "0", - "dst_wire": "DSP_1_A14", - "is_directional": "1", - "src_wire": "DSP_IMUX44_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT25->DSP_1_PCIN25": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN25", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT25", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D24": { - "can_invert": "0", - "dst_wire": "DSP_1_D24", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP2_2->DSP_0_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_BYP2_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN1_2->DSP_0_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE2", - "is_directional": "1", - "src_wire": "DSP_FAN1_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX17_4->DSP_1_OPMODE4": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE4", - "is_directional": "1", - "src_wire": "DSP_IMUX17_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_1", - "is_directional": "1", - "src_wire": "DSP_0_P4", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D20": { - "can_invert": "0", - "dst_wire": "DSP_1_D20", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX24_2->DSP_1_C31": { - "can_invert": "0", - "dst_wire": "DSP_1_C31", - "is_directional": "1", - "src_wire": "DSP_IMUX24_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { - "can_invert": "0", - "dst_wire": "DSP_CARRYCASCOUT", - "is_directional": "1", - "src_wire": "DSP_1_CARRYCASCOUT", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "DSP_1_P15", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX16_0->DSP_0_C41": { - "can_invert": "0", - "dst_wire": "DSP_0_C41", - "is_directional": "1", - "src_wire": "DSP_IMUX16_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX17_3->DSP_1_CEA2": { - "can_invert": "0", - "dst_wire": "DSP_1_CEA2", - "is_directional": "1", - "src_wire": "DSP_IMUX17_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT5->DSP_1_BCIN5": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN5", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT5", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT11->DSP_ACOUT11": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT11", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT11", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX5_3->DSP_1_A13": { - "can_invert": "0", - "dst_wire": "DSP_1_A13", - "is_directional": "1", - "src_wire": "DSP_IMUX5_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX42_3->DSP_0_B14": { - "can_invert": "0", - "dst_wire": "DSP_0_B14", - "is_directional": "1", - "src_wire": "DSP_IMUX42_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX35_4->DSP_0_C17": { - "can_invert": "0", - "dst_wire": "DSP_0_C17", - "is_directional": "1", - "src_wire": "DSP_IMUX35_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_3", - "is_directional": "1", - "src_wire": "DSP_0_P13", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT16->DSP_PCOUT16": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT16", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT16", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D14": { - "can_invert": "0", - "dst_wire": "DSP_0_D14", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "DSP_1_P44", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP0_3->DSP_1_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_1_CEAD", - "is_directional": "1", - "src_wire": "DSP_BYP0_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN4_4->DSP_1_D19": { - "can_invert": "0", - "dst_wire": "DSP_1_D19", - "is_directional": "1", - "src_wire": "DSP_FAN4_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP6_4->DSP_1_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTD", - "is_directional": "1", - "src_wire": "DSP_BYP6_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT26->DSP_ACOUT26": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT26", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT26", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "DSP_1_UNDERFLOW", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX23_0->DSP_0_A0": { - "can_invert": "0", - "dst_wire": "DSP_0_A0", - "is_directional": "1", - "src_wire": "DSP_IMUX23_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX13_4->DSP_1_C18": { - "can_invert": "0", - "dst_wire": "DSP_1_C18", - "is_directional": "1", - "src_wire": "DSP_IMUX13_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP6_3->DSP_0_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE0", - "is_directional": "1", - "src_wire": "DSP_BYP6_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D16": { - "can_invert": "0", - "dst_wire": "DSP_1_D16", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX32_1->DSP_0_C27": { - "can_invert": "0", - "dst_wire": "DSP_0_C27", - "is_directional": "1", - "src_wire": "DSP_IMUX32_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL0_2->DSP_0_RSTB": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTB", - "is_directional": "1", - "src_wire": "DSP_CTRL0_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT5->DSP_PCOUT5": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT5", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT5", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT2->DSP_1_PCIN2": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN2", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT2", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D3": { - "can_invert": "0", - "dst_wire": "DSP_1_D3", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_0", - "is_directional": "1", - "src_wire": "DSP_0_P20", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D5": { - "can_invert": "0", - "dst_wire": "DSP_0_D5", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX43_3->DSP_0_B12": { - "can_invert": "0", - "dst_wire": "DSP_0_B12", - "is_directional": "1", - "src_wire": "DSP_IMUX43_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT19->DSP_ACOUT19": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT19", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT19", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP2_1->DSP_1_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE1", - "is_directional": "1", - "src_wire": "DSP_BYP2_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN3_0->DSP_1_D0": { - "can_invert": "0", - "dst_wire": "DSP_1_D0", - "is_directional": "1", - "src_wire": "DSP_FAN3_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "DSP_0_CARRYOUT3", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D2": { - "can_invert": "0", - "dst_wire": "DSP_0_D2", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT14->DSP_PCOUT14": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT14", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT14", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN0_1->DSP_0_CED": { - "can_invert": "0", - "dst_wire": "DSP_0_CED", - "is_directional": "1", - "src_wire": "DSP_FAN0_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP7_4->DSP_0_D16": { - "can_invert": "0", - "dst_wire": "DSP_0_D16", - "is_directional": "1", - "src_wire": "DSP_BYP7_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX3_2->DSP_0_C9": { - "can_invert": "0", - "dst_wire": "DSP_0_C9", - "is_directional": "1", - "src_wire": "DSP_IMUX3_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT19->DSP_1_ACIN19": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN19", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT19", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX42_4->DSP_1_B16": { - "can_invert": "0", - "dst_wire": "DSP_1_B16", - "is_directional": "1", - "src_wire": "DSP_IMUX42_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "DSP_0_P40", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT28->DSP_ACOUT28": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT28", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT28", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "DSP_1_P33", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D19": { - "can_invert": "0", - "dst_wire": "DSP_0_D19", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D8": { - "can_invert": "0", - "dst_wire": "DSP_0_D8", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT1->DSP_ACOUT1": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT1", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT1", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP0_2->DSP_0_D22": { - "can_invert": "0", - "dst_wire": "DSP_0_D22", - "is_directional": "1", - "src_wire": "DSP_BYP0_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT44->DSP_1_PCIN44": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN44", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT44", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D16": { - "can_invert": "0", - "dst_wire": "DSP_0_D16", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX29_3->DSP_1_C14": { - "can_invert": "0", - "dst_wire": "DSP_1_C14", - "is_directional": "1", - "src_wire": "DSP_IMUX29_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "DSP_0_P23", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX38_3->DSP_0_C32": { - "can_invert": "0", - "dst_wire": "DSP_0_C32", - "is_directional": "1", - "src_wire": "DSP_IMUX38_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT4->DSP_BCOUT4": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT4", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT33->DSP_1_PCIN33": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN33", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT33", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "DSP_0_P6", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX6_3->DSP_0_A15": { - "can_invert": "0", - "dst_wire": "DSP_0_A15", - "is_directional": "1", - "src_wire": "DSP_IMUX6_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE3", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN6_0->DSP_1_D1": { - "can_invert": "0", - "dst_wire": "DSP_1_D1", - "is_directional": "1", - "src_wire": "DSP_FAN6_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX34_3->DSP_1_CEC": { - "can_invert": "0", - "dst_wire": "DSP_1_CEC", - "is_directional": "1", - "src_wire": "DSP_IMUX34_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "DSP_0_P5", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX1_4->DSP_0_C19": { - "can_invert": "0", - "dst_wire": "DSP_0_C19", - "is_directional": "1", - "src_wire": "DSP_IMUX1_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP1_0->DSP_0_D3": { - "can_invert": "0", - "dst_wire": "DSP_0_D3", - "is_directional": "1", - "src_wire": "DSP_BYP1_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX18_4->DSP_0_C39": { - "can_invert": "0", - "dst_wire": "DSP_0_C39", - "is_directional": "1", - "src_wire": "DSP_IMUX18_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_CED": { - "can_invert": "0", - "dst_wire": "DSP_0_CED", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D12": { - "can_invert": "0", - "dst_wire": "DSP_1_D12", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP5_3->DSP_0_D13": { - "can_invert": "0", - "dst_wire": "DSP_0_D13", - "is_directional": "1", - "src_wire": "DSP_BYP5_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT5->DSP_BCOUT5": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT5", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT5", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D13": { - "can_invert": "0", - "dst_wire": "DSP_0_D13", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE2", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT22->DSP_1_PCIN22": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN22", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT22", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX3_4->DSP_0_B17": { - "can_invert": "0", - "dst_wire": "DSP_0_B17", - "is_directional": "1", - "src_wire": "DSP_IMUX3_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "DSP_0_P7", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D15": { - "can_invert": "0", - "dst_wire": "DSP_0_D15", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_0", - "is_directional": "1", - "src_wire": "DSP_1_P3", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D19": { - "can_invert": "0", - "dst_wire": "DSP_1_D19", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D1": { - "can_invert": "0", - "dst_wire": "DSP_0_D1", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "DSP_0_PATTERNBDETECT", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP1_2->DSP_0_D11": { - "can_invert": "0", - "dst_wire": "DSP_0_D11", - "is_directional": "1", - "src_wire": "DSP_BYP1_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_0_CEAD", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_2", - "is_directional": "1", - "src_wire": "DSP_0_P31", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT25->DSP_1_ACIN25": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN25", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT25", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT1->DSP_PCOUT1": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT1", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX7_4->DSP_0_A17": { - "can_invert": "0", - "dst_wire": "DSP_0_A17", - "is_directional": "1", - "src_wire": "DSP_IMUX7_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B8_2", - "is_directional": "1", - "src_wire": "DSP_1_OVERFLOW", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT24->DSP_PCOUT24": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT24", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT24", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL0_4->DSP_1_RSTP": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTP", - "is_directional": "1", - "src_wire": "DSP_CTRL0_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX24_1->DSP_1_C27": { - "can_invert": "0", - "dst_wire": "DSP_1_C27", - "is_directional": "1", - "src_wire": "DSP_IMUX24_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D20": { - "can_invert": "0", - "dst_wire": "DSP_0_D20", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D15": { - "can_invert": "0", - "dst_wire": "DSP_0_D15", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT15->DSP_1_BCIN15": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN15", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT15", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT1->DSP_BCOUT1": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT1", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT1", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN5_2->DSP_1_D10": { - "can_invert": "0", - "dst_wire": "DSP_1_D10", - "is_directional": "1", - "src_wire": "DSP_FAN5_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT32->DSP_1_PCIN32": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN32", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT32", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX33_4->DSP_0_C47": { - "can_invert": "0", - "dst_wire": "DSP_0_C47", - "is_directional": "1", - "src_wire": "DSP_IMUX33_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX28_3->DSP_1_OPMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE0", - "is_directional": "1", - "src_wire": "DSP_IMUX28_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT34->DSP_1_PCIN34": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN34", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT34", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D11": { - "can_invert": "0", - "dst_wire": "DSP_0_D11", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D13": { - "can_invert": "0", - "dst_wire": "DSP_0_D13", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT2->DSP_1_ACIN2": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN2", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT2", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D14": { - "can_invert": "0", - "dst_wire": "DSP_1_D14", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP4_3->DSP_1_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_BYP4_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYCASCIN", - "is_directional": "1", - "src_wire": "DSP_0_CARRYCASCOUT", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX19_2->DSP_0_A9": { - "can_invert": "0", - "dst_wire": "DSP_0_A9", - "is_directional": "1", - "src_wire": "DSP_IMUX19_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT38->DSP_1_PCIN38": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN38", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT38", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT30->DSP_1_PCIN30": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN30", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT30", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "DSP_1_P12", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX30_4->DSP_1_C36": { - "can_invert": "0", - "dst_wire": "DSP_1_C36", - "is_directional": "1", - "src_wire": "DSP_IMUX30_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT26->DSP_PCOUT26": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT26", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT26", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX14_2->DSP_1_B8": { - "can_invert": "0", - "dst_wire": "DSP_1_B8", - "is_directional": "1", - "src_wire": "DSP_IMUX14_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX20_2->DSP_0_OPMODE4": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE4", - "is_directional": "1", - "src_wire": "DSP_IMUX20_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX11_2->DSP_1_A9": { - "can_invert": "0", - "dst_wire": "DSP_1_A9", - "is_directional": "1", - "src_wire": "DSP_IMUX11_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX7_3->DSP_0_A13": { - "can_invert": "0", - "dst_wire": "DSP_0_A13", - "is_directional": "1", - "src_wire": "DSP_IMUX7_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX34_2->DSP_0_CEP": { - "can_invert": "0", - "dst_wire": "DSP_0_CEP", - "is_directional": "1", - "src_wire": "DSP_IMUX34_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX38_1->DSP_0_B4": { - "can_invert": "0", - "dst_wire": "DSP_0_B4", - "is_directional": "1", - "src_wire": "DSP_IMUX38_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT28->DSP_PCOUT28": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT28", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT28", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT39->DSP_PCOUT39": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT39", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT39", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX1_2->DSP_0_CEM": { - "can_invert": "0", - "dst_wire": "DSP_0_CEM", - "is_directional": "1", - "src_wire": "DSP_IMUX1_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX32_2->DSP_0_C31": { - "can_invert": "0", - "dst_wire": "DSP_0_C31", - "is_directional": "1", - "src_wire": "DSP_IMUX32_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX4_1->DSP_1_A27": { - "can_invert": "0", - "dst_wire": "DSP_1_A27", - "is_directional": "1", - "src_wire": "DSP_IMUX4_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT47->DSP_1_PCIN47": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN47", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT47", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT8->DSP_BCOUT8": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT8", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT8", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX15_0->DSP_1_A0": { - "can_invert": "0", - "dst_wire": "DSP_1_A0", - "is_directional": "1", - "src_wire": "DSP_IMUX15_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D0": { - "can_invert": "0", - "dst_wire": "DSP_0_D0", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D21": { - "can_invert": "0", - "dst_wire": "DSP_0_D21", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "DSP_0_P19", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE0", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT13->DSP_1_ACIN13": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN13", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT13", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX21_2->DSP_0_A10": { - "can_invert": "0", - "dst_wire": "DSP_0_A10", - "is_directional": "1", - "src_wire": "DSP_IMUX21_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D15": { - "can_invert": "0", - "dst_wire": "DSP_1_D15", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT43->DSP_1_PCIN43": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN43", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT43", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT0->DSP_PCOUT0": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT0", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT29->DSP_1_PCIN29": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN29", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT29", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX30_0->DSP_1_C20": { - "can_invert": "0", - "dst_wire": "DSP_1_C20", - "is_directional": "1", - "src_wire": "DSP_IMUX30_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "DSP_0_P38", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT7->DSP_BCOUT7": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT7", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT7", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT9->DSP_BCOUT9": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT9", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT9", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "DSP_1_P40", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "DSP_1_P46", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX3_3->DSP_0_B13": { - "can_invert": "0", - "dst_wire": "DSP_0_B13", - "is_directional": "1", - "src_wire": "DSP_IMUX3_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP7_0->DSP_0_D0": { - "can_invert": "0", - "dst_wire": "DSP_0_D0", - "is_directional": "1", - "src_wire": "DSP_BYP7_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D21": { - "can_invert": "0", - "dst_wire": "DSP_0_D21", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT27->DSP_1_PCIN27": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN27", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT27", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT7->DSP_1_PCIN7": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN7", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT7", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX44_1->DSP_1_A26": { - "can_invert": "0", - "dst_wire": "DSP_1_A26", - "is_directional": "1", - "src_wire": "DSP_IMUX44_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_0", - "is_directional": "1", - "src_wire": "DSP_1_P0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX11_1->DSP_1_A5": { - "can_invert": "0", - "dst_wire": "DSP_1_A5", - "is_directional": "1", - "src_wire": "DSP_IMUX11_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_1", - "is_directional": "1", - "src_wire": "DSP_1_P24", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX13_2->DSP_1_A10": { - "can_invert": "0", - "dst_wire": "DSP_1_A10", - "is_directional": "1", - "src_wire": "DSP_IMUX13_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_2", - "is_directional": "1", - "src_wire": "DSP_0_P8", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX28_1->DSP_1_B6": { - "can_invert": "0", - "dst_wire": "DSP_1_B6", - "is_directional": "1", - "src_wire": "DSP_IMUX28_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT20->DSP_PCOUT20": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT20", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT20", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT0->DSP_BCOUT0": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT0", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX36_2->DSP_0_B10": { - "can_invert": "0", - "dst_wire": "DSP_0_B10", - "is_directional": "1", - "src_wire": "DSP_IMUX36_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_0", - "is_directional": "1", - "src_wire": "DSP_1_P22", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX2_4->DSP_1_B17": { - "can_invert": "0", - "dst_wire": "DSP_1_B17", - "is_directional": "1", - "src_wire": "DSP_IMUX2_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT25->DSP_ACOUT25": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT25", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT25", - "is_pseudo": "0" - }, - "DSP_L.DSP_CTRL0_0->DSP_0_RSTP": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTP", - "is_directional": "1", - "src_wire": "DSP_CTRL0_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT15->DSP_1_ACIN15": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN15", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT15", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D8": { - "can_invert": "0", - "dst_wire": "DSP_1_D8", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE1", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_2", - "is_directional": "1", - "src_wire": "DSP_0_P29", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX25_2->DSP_1_C11": { - "can_invert": "0", - "dst_wire": "DSP_1_C11", - "is_directional": "1", - "src_wire": "DSP_IMUX25_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX14_1->DSP_1_C24": { - "can_invert": "0", - "dst_wire": "DSP_1_C24", - "is_directional": "1", - "src_wire": "DSP_IMUX14_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT9->DSP_1_PCIN9": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN9", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT9", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PCOUT2->DSP_PCOUT2": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT2", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX47_3->DSP_0_A12": { - "can_invert": "0", - "dst_wire": "DSP_0_A12", - "is_directional": "1", - "src_wire": "DSP_IMUX47_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D15": { - "can_invert": "0", - "dst_wire": "DSP_1_D15", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "DSP_1_P38", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D16": { - "can_invert": "0", - "dst_wire": "DSP_1_D16", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX23_2->DSP_0_A8": { - "can_invert": "0", - "dst_wire": "DSP_0_A8", - "is_directional": "1", - "src_wire": "DSP_IMUX23_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN3_3->DSP_1_D12": { - "can_invert": "0", - "dst_wire": "DSP_1_D12", - "is_directional": "1", - "src_wire": "DSP_FAN3_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX15_2->DSP_1_A8": { - "can_invert": "0", - "dst_wire": "DSP_1_A8", - "is_directional": "1", - "src_wire": "DSP_IMUX15_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "DSP_1_PATTERNBDETECT", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX22_3->DSP_1_C32": { - "can_invert": "0", - "dst_wire": "DSP_1_C32", - "is_directional": "1", - "src_wire": "DSP_IMUX22_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX45_3->DSP_1_A12": { - "can_invert": "0", - "dst_wire": "DSP_1_A12", - "is_directional": "1", - "src_wire": "DSP_IMUX45_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN1_1->DSP_1_D21": { - "can_invert": "0", - "dst_wire": "DSP_1_D21", - "is_directional": "1", - "src_wire": "DSP_FAN1_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX46_3->DSP_0_A14": { - "can_invert": "0", - "dst_wire": "DSP_0_A14", - "is_directional": "1", - "src_wire": "DSP_IMUX46_3", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "DSP_1_P10", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX10_0->DSP_1_C21": { - "can_invert": "0", - "dst_wire": "DSP_1_C21", - "is_directional": "1", - "src_wire": "DSP_IMUX10_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "DSP_0_CARRYOUT0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX41_4->DSP_1_C19": { - "can_invert": "0", - "dst_wire": "DSP_1_C19", - "is_directional": "1", - "src_wire": "DSP_IMUX41_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT21->DSP_ACOUT21": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT21", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT21", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX40_2->DSP_0_CEC": { - "can_invert": "0", - "dst_wire": "DSP_0_CEC", - "is_directional": "1", - "src_wire": "DSP_IMUX40_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTALLCARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX15_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT7->DSP_1_ACIN7": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN7", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT7", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT24->DSP_1_PCIN24": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN24", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT24", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN0_0->DSP_0_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_FAN0_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT1->DSP_1_BCIN1": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN1", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_BCOUT2->DSP_BCOUT2": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT2", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_PCOUT16->DSP_1_PCIN16": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN16", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT16", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX8_4->DSP_1_OPMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE1", - "is_directional": "1", - "src_wire": "DSP_IMUX8_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_ACOUT5->DSP_ACOUT5": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT5", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT5", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX4_2->DSP_0_C30": { - "can_invert": "0", - "dst_wire": "DSP_0_C30", - "is_directional": "1", - "src_wire": "DSP_IMUX4_2", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "DSP_0_P24", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX35_0->DSP_0_C40": { - "can_invert": "0", - "dst_wire": "DSP_0_C40", - "is_directional": "1", - "src_wire": "DSP_IMUX35_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX43_1->DSP_0_RSTCTRL": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTCTRL", - "is_directional": "1", - "src_wire": "DSP_IMUX43_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_D2": { - "can_invert": "0", - "dst_wire": "DSP_0_D2", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE1", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX36_1->DSP_0_B6": { - "can_invert": "0", - "dst_wire": "DSP_0_B6", - "is_directional": "1", - "src_wire": "DSP_IMUX36_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX21_1->DSP_0_A6": { - "can_invert": "0", - "dst_wire": "DSP_0_A6", - "is_directional": "1", - "src_wire": "DSP_IMUX21_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_BYP0_1->DSP_0_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_0_CEAD", - "is_directional": "1", - "src_wire": "DSP_BYP0_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_2", - "is_directional": "1", - "src_wire": "DSP_1_P28", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX5_0->DSP_1_A21": { - "can_invert": "0", - "dst_wire": "DSP_1_A21", - "is_directional": "1", - "src_wire": "DSP_IMUX5_0", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX17_1->DSP_0_A7": { - "can_invert": "0", - "dst_wire": "DSP_0_A7", - "is_directional": "1", - "src_wire": "DSP_IMUX17_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_0_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE1", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX5_4->DSP_1_A17": { - "can_invert": "0", - "dst_wire": "DSP_1_A17", - "is_directional": "1", - "src_wire": "DSP_IMUX5_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_D3": { - "can_invert": "0", - "dst_wire": "DSP_0_D3", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_ACOUT22->DSP_1_ACIN22": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN22", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT22", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "DSP_1_P41", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_0", - "is_directional": "1", - "src_wire": "DSP_1_P23", - "is_pseudo": "0" - }, - "DSP_L.DSP_GND_L->DSP_1_D22": { - "can_invert": "0", - "dst_wire": "DSP_1_D22", - "is_directional": "1", - "src_wire": "DSP_GND_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN4_1->DSP_1_D7": { - "can_invert": "0", - "dst_wire": "DSP_1_D7", - "is_directional": "1", - "src_wire": "DSP_FAN4_1", - "is_pseudo": "0" - }, - "DSP_L.DSP_IMUX16_4->DSP_1_OPMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE3", - "is_directional": "1", - "src_wire": "DSP_IMUX16_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { - "can_invert": "0", - "dst_wire": "DSP_MULTSIGNOUT", - "is_directional": "1", - "src_wire": "DSP_1_MULTSIGNOUT", - "is_pseudo": "0" - }, - "DSP_L.DSP_0_BCOUT17->DSP_1_BCIN17": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN17", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT17", - "is_pseudo": "0" - }, - "DSP_L.DSP_FAN5_4->DSP_1_D18": { - "can_invert": "0", - "dst_wire": "DSP_1_D18", - "is_directional": "1", - "src_wire": "DSP_FAN5_4", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_1_D11": { - "can_invert": "0", - "dst_wire": "DSP_1_D11", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - }, - "DSP_L.DSP_VCC_L->DSP_0_CED": { - "can_invert": "0", - "dst_wire": "DSP_0_CED", - "is_directional": "1", - "src_wire": "DSP_VCC_L", - "is_pseudo": "0" - } - }, - "tile_type": "DSP_L" + ] } \ No newline at end of file diff --git a/artix7/tile_type_DSP_R.json b/artix7/tile_type_DSP_R.json index 226f042..a5c69d4 100644 --- a/artix7/tile_type_DSP_R.json +++ b/artix7/tile_type_DSP_R.json @@ -1,8474 +1,8474 @@ { + "pips": { + "DSP_R.DSP_IMUX25_1->DSP_1_C7": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C7" + }, + "DSP_R.DSP_GND_R->DSP_0_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE" + }, + "DSP_R.DSP_1_BCOUT15->DSP_BCOUT15": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT15" + }, + "DSP_R.DSP_1_PCOUT3->DSP_PCOUT3": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT3" + }, + "DSP_R.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { + "can_invert": "0", + "src_wire": "DSP_1_P37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_4" + }, + "DSP_R.DSP_BYP3_2->DSP_0_D10": { + "can_invert": "0", + "src_wire": "DSP_BYP3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10" + }, + "DSP_R.DSP_1_PCOUT2->DSP_PCOUT2": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT2" + }, + "DSP_R.DSP_1_PCOUT19->DSP_PCOUT19": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT19" + }, + "DSP_R.DSP_FAN1_0->DSP_1_D20": { + "can_invert": "0", + "src_wire": "DSP_FAN1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20" + }, + "DSP_R.DSP_0_ACOUT29->DSP_1_ACIN29": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN29" + }, + "DSP_R.DSP_IMUX43_3->DSP_0_B12": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B12" + }, + "DSP_R.DSP_IMUX45_1->DSP_1_A24": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A24" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4" + }, + "DSP_R.DSP_0_ACOUT0->DSP_1_ACIN0": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN0" + }, + "DSP_R.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "DSP_0_P19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_4" + }, + "DSP_R.DSP_0_ACOUT19->DSP_1_ACIN19": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN19" + }, + "DSP_R.DSP_IMUX27_3->DSP_1_C13": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C13" + }, + "DSP_R.DSP_IMUX23_2->DSP_0_A8": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A8" + }, + "DSP_R.DSP_1_PCOUT34->DSP_PCOUT34": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT34" + }, + "DSP_R.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_1" + }, + "DSP_R.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { + "can_invert": "0", + "src_wire": "DSP_1_P19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_4" + }, + "DSP_R.DSP_VCC_R->DSP_1_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2" + }, + "DSP_R.DSP_IMUX1_3->DSP_1_B13": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B13" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3" + }, + "DSP_R.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { + "can_invert": "0", + "src_wire": "DSP_1_P23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_0" + }, + "DSP_R.DSP_IMUX17_0->DSP_0_A3": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A3" + }, + "DSP_R.DSP_FAN0_0->DSP_0_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_FAN0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2" + }, + "DSP_R.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "DSP_0_P38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_4" + }, + "DSP_R.DSP_0_PCOUT26->DSP_1_PCIN26": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN26" + }, + "DSP_R.DSP_IMUX4_2->DSP_0_C30": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C30" + }, + "DSP_R.DSP_0_BCOUT4->DSP_1_BCIN4": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN4" + }, + "DSP_R.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { + "can_invert": "0", + "src_wire": "DSP_0_P11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_2" + }, + "DSP_R.DSP_IMUX43_1->DSP_0_RSTCTRL": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTCTRL" + }, + "DSP_R.DSP_IMUX18_4->DSP_0_C39": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C39" + }, + "DSP_R.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { + "can_invert": "0", + "src_wire": "DSP_0_P20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_0" + }, + "DSP_R.DSP_IMUX11_3->DSP_1_CECTRL": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CECTRL" + }, + "DSP_R.DSP_VCC_R->DSP_0_D4": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4" + }, + "DSP_R.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { + "can_invert": "0", + "src_wire": "DSP_0_OVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_2" + }, + "DSP_R.DSP_GND_R->DSP_0_D24": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1" + }, + "DSP_R.DSP_VCC_R->DSP_0_D9": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0" + }, + "DSP_R.DSP_FAN3_2->DSP_1_D8": { + "can_invert": "0", + "src_wire": "DSP_FAN3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8" + }, + "DSP_R.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { + "can_invert": "0", + "src_wire": "DSP_1_P44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_4" + }, + "DSP_R.DSP_0_PCOUT28->DSP_1_PCIN28": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN28" + }, + "DSP_R.DSP_IMUX34_0->DSP_0_B1": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B1" + }, + "DSP_R.DSP_IMUX29_3->DSP_1_C14": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C14" + }, + "DSP_R.DSP_1_ACOUT9->DSP_ACOUT9": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT9" + }, + "DSP_R.DSP_1_PCOUT39->DSP_PCOUT39": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT39" + }, + "DSP_R.DSP_FAN1_3->DSP_0_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_FAN1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4" + }, + "DSP_R.DSP_GND_R->DSP_1_D20": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20" + }, + "DSP_R.DSP_VCC_R->DSP_0_RSTD": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD" + }, + "DSP_R.DSP_GND_R->DSP_0_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2" + }, + "DSP_R.DSP_IMUX39_2->DSP_0_C8": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C8" + }, + "DSP_R.DSP_FAN4_3->DSP_1_D15": { + "can_invert": "0", + "src_wire": "DSP_FAN4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15" + }, + "DSP_R.DSP_1_ACOUT26->DSP_ACOUT26": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT26" + }, + "DSP_R.DSP_0_PCOUT36->DSP_1_PCIN36": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN36" + }, + "DSP_R.DSP_IMUX14_1->DSP_1_C24": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C24" + }, + "DSP_R.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "DSP_0_P43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_0" + }, + "DSP_R.DSP_IMUX14_0->DSP_1_B0": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B0" + }, + "DSP_R.DSP_IMUX38_1->DSP_0_B4": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B4" + }, + "DSP_R.DSP_1_ACOUT23->DSP_ACOUT23": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT23" + }, + "DSP_R.DSP_IMUX17_2->DSP_0_A11": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A11" + }, + "DSP_R.DSP_BYP1_2->DSP_0_D11": { + "can_invert": "0", + "src_wire": "DSP_BYP1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11" + }, + "DSP_R.DSP_VCC_R->DSP_0_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6" + }, + "DSP_R.DSP_0_ACOUT24->DSP_1_ACIN24": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN24" + }, + "DSP_R.DSP_IMUX19_2->DSP_0_A9": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A9" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2" + }, + "DSP_R.DSP_GND_R->DSP_0_CED": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED" + }, + "DSP_R.DSP_GND_R->DSP_1_D7": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7" + }, + "DSP_R.DSP_BYP2_4->DSP_1_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_BYP2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2" + }, + "DSP_R.DSP_IMUX10_3->DSP_1_C33": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C33" + }, + "DSP_R.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "DSP_0_P22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_0" + }, + "DSP_R.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { + "can_invert": "0", + "src_wire": "DSP_0_P3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_0" + }, + "DSP_R.DSP_IMUX10_0->DSP_1_C21": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C21" + }, + "DSP_R.DSP_IMUX32_0->DSP_0_C23": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C23" + }, + "DSP_R.DSP_GND_R->DSP_1_D1": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1" + }, + "DSP_R.DSP_GND_R->DSP_0_RSTD": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD" + }, + "DSP_R.DSP_IMUX37_2->DSP_0_C10": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C10" + }, + "DSP_R.DSP_IMUX40_4->DSP_1_ALUMODE1": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE1" + }, + "DSP_R.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_3" + }, + "DSP_R.DSP_VCC_R->DSP_1_D0": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0" + }, + "DSP_R.DSP_IMUX21_1->DSP_0_A6": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A6" + }, + "DSP_R.DSP_VCC_R->DSP_1_RSTD": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD" + }, + "DSP_R.DSP_FAN3_0->DSP_1_D0": { + "can_invert": "0", + "src_wire": "DSP_FAN3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0" + }, + "DSP_R.DSP_GND_R->DSP_0_D21": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21" + }, + "DSP_R.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { + "can_invert": "0", + "src_wire": "DSP_0_MULTSIGNOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_MULTSIGNIN" + }, + "DSP_R.DSP_BYP4_0->DSP_0_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE" + }, + "DSP_R.DSP_IMUX23_0->DSP_0_A0": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A0" + }, + "DSP_R.DSP_1_PCOUT14->DSP_PCOUT14": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT14" + }, + "DSP_R.DSP_GND_R->DSP_1_CEAD": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD" + }, + "DSP_R.DSP_1_ACOUT27->DSP_ACOUT27": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT27" + }, + "DSP_R.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { + "can_invert": "0", + "src_wire": "DSP_1_P27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_1" + }, + "DSP_R.DSP_1_PCOUT45->DSP_PCOUT45": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT45" + }, + "DSP_R.DSP_IMUX44_3->DSP_1_A14": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A14" + }, + "DSP_R.DSP_CTRL0_3->DSP_1_RSTC": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTC" + }, + "DSP_R.DSP_BYP7_1->DSP_0_D4": { + "can_invert": "0", + "src_wire": "DSP_BYP7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4" + }, + "DSP_R.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL0" + }, + "DSP_R.DSP_BYP4_1->DSP_0_RSTD": { + "can_invert": "0", + "src_wire": "DSP_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTD" + }, + "DSP_R.DSP_1_BCOUT10->DSP_BCOUT10": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT10" + }, + "DSP_R.DSP_1_BCOUT3->DSP_BCOUT3": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT3" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2" + }, + "DSP_R.DSP_IMUX9_1->DSP_1_A7": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A7" + }, + "DSP_R.DSP_IMUX11_0->DSP_1_A1": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A1" + }, + "DSP_R.DSP_IMUX9_2->DSP_1_A11": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A11" + }, + "DSP_R.DSP_IMUX26_4->DSP_1_C44": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C44" + }, + "DSP_R.DSP_IMUX39_1->DSP_0_C4": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C4" + }, + "DSP_R.DSP_IMUX47_3->DSP_0_A12": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A12" + }, + "DSP_R.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { + "can_invert": "0", + "src_wire": "DSP_0_P7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_1" + }, + "DSP_R.DSP_CTRL1_4->DSP_1_RSTB": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTB" + }, + "DSP_R.DSP_BYP0_1->DSP_0_CEAD": { + "can_invert": "0", + "src_wire": "DSP_BYP0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3" + }, + "DSP_R.DSP_1_PCOUT16->DSP_PCOUT16": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT16" + }, + "DSP_R.DSP_1_PCOUT6->DSP_PCOUT6": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT6" + }, + "DSP_R.DSP_BYP1_0->DSP_0_D3": { + "can_invert": "0", + "src_wire": "DSP_BYP1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3" + }, + "DSP_R.DSP_0_PCOUT47->DSP_1_PCIN47": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN47" + }, + "DSP_R.DSP_IMUX33_3->DSP_0_C15": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C15" + }, + "DSP_R.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { + "can_invert": "0", + "src_wire": "DSP_1_P7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_1" + }, + "DSP_R.DSP_IMUX7_3->DSP_0_A13": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A13" + }, + "DSP_R.DSP_GND_R->DSP_1_D9": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9" + }, + "DSP_R.DSP_IMUX15_2->DSP_1_A8": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A8" + }, + "DSP_R.DSP_IMUX6_2->DSP_0_C28": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C28" + }, + "DSP_R.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { + "can_invert": "0", + "src_wire": "DSP_1_P3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_0" + }, + "DSP_R.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { + "can_invert": "0", + "src_wire": "DSP_0_P8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_2" + }, + "DSP_R.DSP_VCC_R->DSP_1_D23": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23" + }, + "DSP_R.DSP_GND_R->DSP_1_CED": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED" + }, + "DSP_R.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { + "can_invert": "0", + "src_wire": "DSP_1_P21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_0" + }, + "DSP_R.DSP_IMUX31_1->DSP_1_C4": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C4" + }, + "DSP_R.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { + "can_invert": "0", + "src_wire": "DSP_1_P4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_1" + }, + "DSP_R.DSP_VCC_R->DSP_0_D5": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5" + }, + "DSP_R.DSP_0_PCOUT11->DSP_1_PCIN11": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN11" + }, + "DSP_R.DSP_GND_R->DSP_0_D13": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13" + }, + "DSP_R.DSP_IMUX22_1->DSP_0_C24": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C24" + }, + "DSP_R.DSP_BYP2_1->DSP_1_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_BYP2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1" + }, + "DSP_R.DSP_IMUX27_4->DSP_1_C17": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C17" + }, + "DSP_R.DSP_GND_R->DSP_0_D5": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5" + }, + "DSP_R.DSP_VCC_R->DSP_1_D24": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24" + }, + "DSP_R.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "DSP_0_P2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_0" + }, + "DSP_R.DSP_IMUX39_0->DSP_0_C0": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C0" + }, + "DSP_R.DSP_IMUX21_3->DSP_0_ALUMODE0": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE0" + }, + "DSP_R.DSP_0_PCOUT43->DSP_1_PCIN43": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN43" + }, + "DSP_R.DSP_1_ACOUT8->DSP_ACOUT8": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT8" + }, + "DSP_R.DSP_GND_R->DSP_0_D16": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16" + }, + "DSP_R.DSP_1_ACOUT22->DSP_ACOUT22": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT22" + }, + "DSP_R.DSP_IMUX37_0->DSP_0_C2": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C2" + }, + "DSP_R.DSP_VCC_R->DSP_1_D21": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21" + }, + "DSP_R.DSP_BYP7_0->DSP_0_D0": { + "can_invert": "0", + "src_wire": "DSP_BYP7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0" + }, + "DSP_R.DSP_1_ACOUT14->DSP_ACOUT14": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT14" + }, + "DSP_R.DSP_GND_R->DSP_1_D14": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14" + }, + "DSP_R.DSP_IMUX40_2->DSP_0_CEC": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEC" + }, + "DSP_R.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL0" + }, + "DSP_R.DSP_0_ACOUT8->DSP_1_ACIN8": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN8" + }, + "DSP_R.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { + "can_invert": "0", + "src_wire": "DSP_1_P28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_2" + }, + "DSP_R.DSP_IMUX8_2->DSP_1_B11": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B11" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4" + }, + "DSP_R.DSP_GND_R->DSP_0_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE" + }, + "DSP_R.DSP_IMUX44_4->DSP_1_A18": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A18" + }, + "DSP_R.DSP_1_ACOUT3->DSP_ACOUT3": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT3" + }, + "DSP_R.DSP_FAN0_1->DSP_0_CED": { + "can_invert": "0", + "src_wire": "DSP_FAN0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED" + }, + "DSP_R.DSP_IMUX37_1->DSP_0_C6": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C6" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE4" + }, + "DSP_R.DSP_VCC_R->DSP_0_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE" + }, + "DSP_R.DSP_IMUX43_2->DSP_1_C9": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C9" + }, + "DSP_R.DSP_VCC_R->DSP_1_D22": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22" + }, + "DSP_R.DSP_GND_R->DSP_1_D3": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3" + }, + "DSP_R.DSP_IMUX24_4->DSP_1_C37": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C37" + }, + "DSP_R.DSP_0_BCOUT2->DSP_1_BCIN2": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN2" + }, + "DSP_R.DSP_IMUX22_2->DSP_0_B8": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B8" + }, + "DSP_R.DSP_0_PCOUT30->DSP_1_PCIN30": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN30" + }, + "DSP_R.DSP_GND_R->DSP_0_D9": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9" + }, + "DSP_R.DSP_BYP0_2->DSP_0_D22": { + "can_invert": "0", + "src_wire": "DSP_BYP0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22" + }, + "DSP_R.DSP_0_ACOUT17->DSP_1_ACIN17": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN17" + }, + "DSP_R.DSP_1_PCOUT22->DSP_PCOUT22": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT22" + }, + "DSP_R.DSP_VCC_R->DSP_0_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2" + }, + "DSP_R.DSP_1_PCOUT4->DSP_PCOUT4": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT4" + }, + "DSP_R.DSP_IMUX31_0->DSP_1_C0": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C0" + }, + "DSP_R.DSP_0_PCOUT5->DSP_1_PCIN5": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN5" + }, + "DSP_R.DSP_1_PCOUT41->DSP_PCOUT41": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT41" + }, + "DSP_R.DSP_IMUX38_2->DSP_0_OPMODE3": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE3" + }, + "DSP_R.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { + "can_invert": "0", + "src_wire": "DSP_1_P14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_3" + }, + "DSP_R.DSP_IMUX19_0->DSP_0_A1": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A1" + }, + "DSP_R.DSP_VCC_R->DSP_1_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE" + }, + "DSP_R.DSP_IMUX3_2->DSP_0_C9": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C9" + }, + "DSP_R.DSP_FAN3_1->DSP_1_D4": { + "can_invert": "0", + "src_wire": "DSP_FAN3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4" + }, + "DSP_R.DSP_GND_R->DSP_1_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE" + }, + "DSP_R.DSP_1_PCOUT33->DSP_PCOUT33": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT33" + }, + "DSP_R.DSP_IMUX15_1->DSP_1_A4": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A4" + }, + "DSP_R.DSP_VCC_R->DSP_0_D11": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11" + }, + "DSP_R.DSP_GND_R->DSP_0_D11": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D11" + }, + "DSP_R.DSP_CLK0_3->DSP_1_CLK": { + "can_invert": "0", + "src_wire": "DSP_CLK0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CLK" + }, + "DSP_R.DSP_1_ACOUT5->DSP_ACOUT5": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT5" + }, + "DSP_R.DSP_0_ACOUT9->DSP_1_ACIN9": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN9" + }, + "DSP_R.DSP_1_PCOUT44->DSP_PCOUT44": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT44" + }, + "DSP_R.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { + "can_invert": "0", + "src_wire": "DSP_0_P30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_2" + }, + "DSP_R.DSP_IMUX22_3->DSP_1_C32": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C32" + }, + "DSP_R.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_3" + }, + "DSP_R.DSP_IMUX3_4->DSP_0_B17": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B17" + }, + "DSP_R.DSP_VCC_R->DSP_0_D0": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0" + }, + "DSP_R.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { + "can_invert": "0", + "src_wire": "DSP_1_P5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_1" + }, + "DSP_R.DSP_IMUX43_4->DSP_0_B16": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B16" + }, + "DSP_R.DSP_1_BCOUT8->DSP_BCOUT8": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT8" + }, + "DSP_R.DSP_0_BCOUT9->DSP_1_BCIN9": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN9" + }, + "DSP_R.DSP_1_ACOUT6->DSP_ACOUT6": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT6" + }, + "DSP_R.DSP_1_BCOUT1->DSP_BCOUT1": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT1" + }, + "DSP_R.DSP_IMUX14_2->DSP_1_B8": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B8" + }, + "DSP_R.DSP_BYP6_0->DSP_0_D20": { + "can_invert": "0", + "src_wire": "DSP_BYP6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20" + }, + "DSP_R.DSP_IMUX9_3->DSP_1_CEA1": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEA1" + }, + "DSP_R.DSP_1_ACOUT12->DSP_ACOUT12": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT12" + }, + "DSP_R.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { + "can_invert": "0", + "src_wire": "DSP_0_P45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_4" + }, + "DSP_R.DSP_VCC_R->DSP_1_D18": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18" + }, + "DSP_R.DSP_IMUX41_2->DSP_0_CECTRL": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CECTRL" + }, + "DSP_R.DSP_IMUX35_0->DSP_0_C40": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C40" + }, + "DSP_R.DSP_0_BCOUT15->DSP_1_BCIN15": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN15" + }, + "DSP_R.DSP_IMUX7_2->DSP_0_A29": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A29" + }, + "DSP_R.DSP_1_ACOUT10->DSP_ACOUT10": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT10" + }, + "DSP_R.DSP_IMUX5_1->DSP_1_A25": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A25" + }, + "DSP_R.DSP_0_ACOUT15->DSP_1_ACIN15": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN15" + }, + "DSP_R.DSP_IMUX36_1->DSP_0_B6": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B6" + }, + "DSP_R.DSP_VCC_R->DSP_1_D9": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9" + }, + "DSP_R.DSP_0_PCOUT23->DSP_1_PCIN23": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN23" + }, + "DSP_R.DSP_VCC_R->DSP_0_D10": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10" + }, + "DSP_R.DSP_1_PCOUT23->DSP_PCOUT23": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT23" + }, + "DSP_R.DSP_IMUX35_1->DSP_0_C5": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C5" + }, + "DSP_R.DSP_IMUX27_1->DSP_1_C5": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C5" + }, + "DSP_R.DSP_0_PCOUT12->DSP_1_PCIN12": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN12" + }, + "DSP_R.DSP_1_PCOUT32->DSP_PCOUT32": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT32" + }, + "DSP_R.DSP_0_PCOUT27->DSP_1_PCIN27": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN27" + }, + "DSP_R.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { + "can_invert": "0", + "src_wire": "DSP_0_P47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_4" + }, + "DSP_R.DSP_BYP3_4->DSP_0_D18": { + "can_invert": "0", + "src_wire": "DSP_BYP3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18" + }, + "DSP_R.DSP_0_ACOUT2->DSP_1_ACIN2": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN2" + }, + "DSP_R.DSP_1_PCOUT20->DSP_PCOUT20": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT20" + }, + "DSP_R.DSP_IMUX21_0->DSP_0_A2": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A2" + }, + "DSP_R.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "DSP_0_P24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_1" + }, + "DSP_R.DSP_IMUX20_1->DSP_0_C26": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C26" + }, + "DSP_R.DSP_FAN6_0->DSP_1_D1": { + "can_invert": "0", + "src_wire": "DSP_FAN6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1" + }, + "DSP_R.DSP_1_PCOUT11->DSP_PCOUT11": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT11" + }, + "DSP_R.DSP_FAN7_0->DSP_1_D24": { + "can_invert": "0", + "src_wire": "DSP_FAN7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24" + }, + "DSP_R.DSP_IMUX45_4->DSP_1_A16": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A16" + }, + "DSP_R.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { + "can_invert": "0", + "src_wire": "DSP_0_P31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_2" + }, + "DSP_R.DSP_IMUX30_0->DSP_1_C20": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C20" + }, + "DSP_R.DSP_FAN3_3->DSP_1_D12": { + "can_invert": "0", + "src_wire": "DSP_FAN3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12" + }, + "DSP_R.DSP_FAN5_0->DSP_1_D2": { + "can_invert": "0", + "src_wire": "DSP_FAN5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2" + }, + "DSP_R.DSP_VCC_R->DSP_0_D19": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19" + }, + "DSP_R.DSP_BYP6_1->DSP_0_D21": { + "can_invert": "0", + "src_wire": "DSP_BYP6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21" + }, + "DSP_R.DSP_IMUX32_2->DSP_0_C31": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C31" + }, + "DSP_R.DSP_1_PCOUT40->DSP_PCOUT40": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT40" + }, + "DSP_R.DSP_IMUX16_2->DSP_0_B11": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B11" + }, + "DSP_R.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { + "can_invert": "0", + "src_wire": "DSP_1_P39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_4" + }, + "DSP_R.DSP_1_PCOUT29->DSP_PCOUT29": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT29" + }, + "DSP_R.DSP_VCC_R->DSP_0_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE2" + }, + "DSP_R.DSP_0_PCOUT21->DSP_1_PCIN21": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN21" + }, + "DSP_R.DSP_VCC_R->DSP_0_D3": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3" + }, + "DSP_R.DSP_1_ACOUT4->DSP_ACOUT4": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT4" + }, + "DSP_R.DSP_GND_R->DSP_0_D2": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2" + }, + "DSP_R.DSP_IMUX28_0->DSP_1_B2": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B2" + }, + "DSP_R.DSP_IMUX33_2->DSP_0_C11": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C11" + }, + "DSP_R.DSP_1_BCOUT7->DSP_BCOUT7": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT7" + }, + "DSP_R.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { + "can_invert": "0", + "src_wire": "DSP_1_MULTSIGNOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_MULTSIGNOUT" + }, + "DSP_R.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { + "can_invert": "0", + "src_wire": "DSP_1_P45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_4" + }, + "DSP_R.DSP_IMUX33_4->DSP_0_C47": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C47" + }, + "DSP_R.DSP_IMUX4_4->DSP_1_A19": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A19" + }, + "DSP_R.DSP_0_PCOUT2->DSP_1_PCIN2": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN2" + }, + "DSP_R.DSP_IMUX2_4->DSP_1_B17": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B17" + }, + "DSP_R.DSP_BYP0_3->DSP_1_CEAD": { + "can_invert": "0", + "src_wire": "DSP_BYP0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD" + }, + "DSP_R.DSP_FAN1_2->DSP_0_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_FAN1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2" + }, + "DSP_R.DSP_IMUX40_3->DSP_1_B14": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B14" + }, + "DSP_R.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { + "can_invert": "0", + "src_wire": "DSP_1_P15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_3" + }, + "DSP_R.DSP_BYP1_3->DSP_0_D15": { + "can_invert": "0", + "src_wire": "DSP_BYP1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15" + }, + "DSP_R.DSP_IMUX39_3->DSP_0_C12": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C12" + }, + "DSP_R.DSP_IMUX10_4->DSP_1_C39": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C39" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0" + }, + "DSP_R.DSP_IMUX19_3->DSP_1_CEM": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEM" + }, + "DSP_R.DSP_1_ACOUT11->DSP_ACOUT11": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT11" + }, + "DSP_R.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { + "can_invert": "0", + "src_wire": "DSP_0_P9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_2" + }, + "DSP_R.DSP_0_PCOUT25->DSP_1_PCIN25": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN25" + }, + "DSP_R.DSP_FAN2_3->DSP_1_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_FAN2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE" + }, + "DSP_R.DSP_VCC_R->DSP_1_D14": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14" + }, + "DSP_R.DSP_IMUX37_3->DSP_0_C14": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C14" + }, + "DSP_R.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { + "can_invert": "0", + "src_wire": "DSP_0_P39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_4" + }, + "DSP_R.DSP_IMUX8_4->DSP_1_OPMODE1": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE1" + }, + "DSP_R.DSP_0_ACOUT28->DSP_1_ACIN28": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN28" + }, + "DSP_R.DSP_FAN7_4->DSP_1_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_FAN7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2" + }, + "DSP_R.DSP_0_ACOUT25->DSP_1_ACIN25": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN25" + }, + "DSP_R.DSP_0_PCOUT6->DSP_1_PCIN6": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN6" + }, + "DSP_R.DSP_IMUX16_1->DSP_0_B7": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B7" + }, + "DSP_R.DSP_1_PCOUT12->DSP_PCOUT12": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT12" + }, + "DSP_R.DSP_GND_R->DSP_1_D0": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D0" + }, + "DSP_R.DSP_1_BCOUT5->DSP_BCOUT5": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT5" + }, + "DSP_R.DSP_CTRL0_2->DSP_0_RSTB": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTB" + }, + "DSP_R.DSP_VCC_R->DSP_1_D2": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2" + }, + "DSP_R.DSP_GND_R->DSP_0_D8": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8" + }, + "DSP_R.DSP_IMUX31_3->DSP_1_C12": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C12" + }, + "DSP_R.DSP_FAN6_2->DSP_1_D9": { + "can_invert": "0", + "src_wire": "DSP_FAN6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D9" + }, + "DSP_R.DSP_IMUX31_2->DSP_1_C8": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C8" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4" + }, + "DSP_R.DSP_0_PCOUT0->DSP_1_PCIN0": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN0" + }, + "DSP_R.DSP_0_PCOUT15->DSP_1_PCIN15": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN15" + }, + "DSP_R.DSP_0_ACOUT14->DSP_1_ACIN14": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN14" + }, + "DSP_R.DSP_0_BCOUT6->DSP_1_BCIN6": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN6" + }, + "DSP_R.DSP_IMUX5_4->DSP_1_A17": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A17" + }, + "DSP_R.DSP_CTRL1_3->DSP_1_RSTM": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTM" + }, + "DSP_R.DSP_IMUX46_1->DSP_0_A26": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A26" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1" + }, + "DSP_R.DSP_1_PCOUT24->DSP_PCOUT24": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT24" + }, + "DSP_R.DSP_0_PCOUT3->DSP_1_PCIN3": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN3" + }, + "DSP_R.DSP_IMUX7_1->DSP_0_A25": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A25" + }, + "DSP_R.DSP_0_PCOUT7->DSP_1_PCIN7": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN7" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3" + }, + "DSP_R.DSP_0_PCOUT24->DSP_1_PCIN24": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN24" + }, + "DSP_R.DSP_GND_R->DSP_0_D4": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D4" + }, + "DSP_R.DSP_IMUX38_4->DSP_0_C36": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C36" + }, + "DSP_R.DSP_IMUX23_1->DSP_0_A4": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A4" + }, + "DSP_R.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { + "can_invert": "0", + "src_wire": "DSP_0_P44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_4" + }, + "DSP_R.DSP_GND_R->DSP_1_D2": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D2" + }, + "DSP_R.DSP_0_ACOUT1->DSP_1_ACIN1": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN1" + }, + "DSP_R.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "DSP_0_P6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_1" + }, + "DSP_R.DSP_VCC_R->DSP_0_D22": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22" + }, + "DSP_R.DSP_IMUX35_2->DSP_0_OPMODE0": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE0" + }, + "DSP_R.DSP_0_BCOUT14->DSP_1_BCIN14": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN14" + }, + "DSP_R.DSP_GND_R->DSP_1_D22": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22" + }, + "DSP_R.DSP_0_BCOUT8->DSP_1_BCIN8": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN8" + }, + "DSP_R.DSP_1_BCOUT6->DSP_BCOUT6": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT6" + }, + "DSP_R.DSP_0_BCOUT11->DSP_1_BCIN11": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN11" + }, + "DSP_R.DSP_GND_R->DSP_1_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2" + }, + "DSP_R.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { + "can_invert": "0", + "src_wire": "DSP_0_P25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_1" + }, + "DSP_R.DSP_VCC_R->DSP_0_D7": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7" + }, + "DSP_R.DSP_IMUX45_0->DSP_1_A20": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A20" + }, + "DSP_R.DSP_VCC_R->DSP_1_CED": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED" + }, + "DSP_R.DSP_VCC_R->DSP_1_CEAD": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEAD" + }, + "DSP_R.DSP_1_ACOUT0->DSP_ACOUT0": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT0" + }, + "DSP_R.DSP_IMUX26_0->DSP_1_B1": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B1" + }, + "DSP_R.DSP_VCC_R->DSP_1_D20": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D20" + }, + "DSP_R.DSP_IMUX1_0->DSP_0_C3": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C3" + }, + "DSP_R.DSP_GND_R->DSP_0_D14": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14" + }, + "DSP_R.DSP_0_PCOUT34->DSP_1_PCIN34": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN34" + }, + "DSP_R.DSP_IMUX38_3->DSP_0_C32": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C32" + }, + "DSP_R.DSP_IMUX13_0->DSP_1_A2": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A2" + }, + "DSP_R.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_1" + }, + "DSP_R.DSP_1_PCOUT7->DSP_PCOUT7": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT7" + }, + "DSP_R.DSP_FAN2_0->DSP_0_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_FAN2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEINMODE" + }, + "DSP_R.DSP_IMUX46_2->DSP_1_C28": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C28" + }, + "DSP_R.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { + "can_invert": "0", + "src_wire": "DSP_1_P26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_1" + }, + "DSP_R.DSP_1_PCOUT0->DSP_PCOUT0": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT0" + }, + "DSP_R.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { + "can_invert": "0", + "src_wire": "DSP_1_P47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_4" + }, + "DSP_R.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "DSP_0_P21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_0" + }, + "DSP_R.DSP_IMUX34_3->DSP_1_CEC": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEC" + }, + "DSP_R.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { + "can_invert": "0", + "src_wire": "DSP_0_P26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_1" + }, + "DSP_R.DSP_IMUX45_3->DSP_1_A12": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A12" + }, + "DSP_R.DSP_1_PCOUT36->DSP_PCOUT36": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT36" + }, + "DSP_R.DSP_0_ACOUT10->DSP_1_ACIN10": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN10" + }, + "DSP_R.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "DSP_0_P36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_4" + }, + "DSP_R.DSP_IMUX36_3->DSP_1_OPMODE2": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE2" + }, + "DSP_R.DSP_VCC_R->DSP_1_D8": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8" + }, + "DSP_R.DSP_IMUX12_3->DSP_1_C34": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C34" + }, + "DSP_R.DSP_IMUX26_3->DSP_1_CECARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CECARRYIN" + }, + "DSP_R.DSP_1_BCOUT14->DSP_BCOUT14": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT14" + }, + "DSP_R.DSP_IMUX29_2->DSP_1_C10": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C10" + }, + "DSP_R.DSP_IMUX42_0->DSP_0_C42": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C42" + }, + "DSP_R.DSP_IMUX13_2->DSP_1_A10": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A10" + }, + "DSP_R.DSP_IMUX12_4->DSP_1_C38": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C38" + }, + "DSP_R.DSP_FAN0_4->DSP_1_ALUMODE2": { + "can_invert": "0", + "src_wire": "DSP_FAN0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE2" + }, + "DSP_R.DSP_1_ACOUT2->DSP_ACOUT2": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT2" + }, + "DSP_R.DSP_VCC_R->DSP_0_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3" + }, + "DSP_R.DSP_GND_R->DSP_0_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6" + }, + "DSP_R.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "DSP_1_UNDERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_3" + }, + "DSP_R.DSP_GND_R->DSP_1_D17": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17" + }, + "DSP_R.DSP_1_PCOUT35->DSP_PCOUT35": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT35" + }, + "DSP_R.DSP_0_PCOUT1->DSP_1_PCIN1": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN1" + }, + "DSP_R.DSP_IMUX26_2->DSP_1_CEP": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEP" + }, + "DSP_R.DSP_IMUX38_0->DSP_0_C20": { + "can_invert": "0", + "src_wire": "DSP_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C20" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3" + }, + "DSP_R.DSP_FAN2_2->DSP_1_INMODE4": { + "can_invert": "0", + "src_wire": "DSP_FAN2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE4" + }, + "DSP_R.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { + "can_invert": "0", + "src_wire": "DSP_0_P40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_0" + }, + "DSP_R.DSP_0_PCOUT46->DSP_1_PCIN46": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN46" + }, + "DSP_R.DSP_IMUX42_2->DSP_1_B9": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B9" + }, + "DSP_R.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { + "can_invert": "0", + "src_wire": "DSP_0_P17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_4" + }, + "DSP_R.DSP_GND_R->DSP_1_D15": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15" + }, + "DSP_R.DSP_1_ACOUT29->DSP_ACOUT29": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT29" + }, + "DSP_R.DSP_BYP4_4->DSP_1_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_BYP4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE3" + }, + "DSP_R.DSP_IMUX2_3->DSP_0_B15": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B15" + }, + "DSP_R.DSP_1_ACOUT16->DSP_ACOUT16": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT16" + }, + "DSP_R.DSP_GND_R->DSP_1_D16": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16" + }, + "DSP_R.DSP_CTRL0_0->DSP_0_RSTP": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTP" + }, + "DSP_R.DSP_GND_R->DSP_0_CEAD": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD" + }, + "DSP_R.DSP_0_ACOUT13->DSP_1_ACIN13": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN13" + }, + "DSP_R.DSP_IMUX14_4->DSP_1_RSTCTRL": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTCTRL" + }, + "DSP_R.DSP_GND_R->DSP_1_D11": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11" + }, + "DSP_R.DSP_IMUX28_2->DSP_1_C30": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C30" + }, + "DSP_R.DSP_FAN4_1->DSP_1_D7": { + "can_invert": "0", + "src_wire": "DSP_FAN4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7" + }, + "DSP_R.DSP_IMUX13_1->DSP_1_A6": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A6" + }, + "DSP_R.DSP_VCC_R->DSP_1_D1": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D1" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0" + }, + "DSP_R.DSP_GND_R->DSP_1_D19": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19" + }, + "DSP_R.DSP_IMUX0_2->DSP_0_CECARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CECARRYIN" + }, + "DSP_R.DSP_0_BCOUT7->DSP_1_BCIN7": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN7" + }, + "DSP_R.DSP_IMUX20_2->DSP_0_OPMODE4": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE4" + }, + "DSP_R.DSP_0_PCOUT29->DSP_1_PCIN29": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN29" + }, + "DSP_R.DSP_IMUX18_1->DSP_0_B5": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B5" + }, + "DSP_R.DSP_0_PCOUT37->DSP_1_PCIN37": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN37" + }, + "DSP_R.DSP_VCC_R->DSP_0_CED": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CED" + }, + "DSP_R.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { + "can_invert": "0", + "src_wire": "DSP_1_P13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_3" + }, + "DSP_R.DSP_IMUX34_4->DSP_0_C44": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C44" + }, + "DSP_R.DSP_IMUX17_1->DSP_0_A7": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A7" + }, + "DSP_R.DSP_0_BCOUT12->DSP_1_BCIN12": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN12" + }, + "DSP_R.DSP_1_BCOUT13->DSP_BCOUT13": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT13" + }, + "DSP_R.DSP_VCC_R->DSP_0_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE2" + }, + "DSP_R.DSP_VCC_R->DSP_1_D16": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16" + }, + "DSP_R.DSP_IMUX0_1->DSP_0_CEA2": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEA2" + }, + "DSP_R.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { + "can_invert": "0", + "src_wire": "DSP_0_P4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_1" + }, + "DSP_R.DSP_0_PCOUT41->DSP_1_PCIN41": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN41" + }, + "DSP_R.DSP_FAN6_1->DSP_1_D5": { + "can_invert": "0", + "src_wire": "DSP_FAN6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5" + }, + "DSP_R.DSP_IMUX1_2->DSP_0_CEM": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEM" + }, + "DSP_R.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { + "can_invert": "0", + "src_wire": "DSP_0_P29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_2" + }, + "DSP_R.DSP_1_ACOUT18->DSP_ACOUT18": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT18" + }, + "DSP_R.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { + "can_invert": "0", + "src_wire": "DSP_1_P2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_0" + }, + "DSP_R.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYCASCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_CARRYCASCOUT" + }, + "DSP_R.DSP_FAN7_1->DSP_0_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_FAN7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1" + }, + "DSP_R.DSP_0_BCOUT10->DSP_1_BCIN10": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN10" + }, + "DSP_R.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_1" + }, + "DSP_R.DSP_1_PCOUT21->DSP_PCOUT21": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT21" + }, + "DSP_R.DSP_IMUX43_0->DSP_1_C1": { + "can_invert": "0", + "src_wire": "DSP_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C1" + }, + "DSP_R.DSP_1_ACOUT20->DSP_ACOUT20": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT20" + }, + "DSP_R.DSP_VCC_R->DSP_0_D23": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23" + }, + "DSP_R.DSP_0_PCOUT13->DSP_1_PCIN13": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN13" + }, + "DSP_R.DSP_BYP1_4->DSP_0_D19": { + "can_invert": "0", + "src_wire": "DSP_BYP1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19" + }, + "DSP_R.DSP_IMUX32_1->DSP_0_C27": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C27" + }, + "DSP_R.DSP_GND_R->DSP_0_D3": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D3" + }, + "DSP_R.DSP_BYP5_1->DSP_0_D5": { + "can_invert": "0", + "src_wire": "DSP_BYP5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D5" + }, + "DSP_R.DSP_0_ACOUT26->DSP_1_ACIN26": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN26" + }, + "DSP_R.DSP_0_ACOUT23->DSP_1_ACIN23": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN23" + }, + "DSP_R.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL1" + }, + "DSP_R.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "DSP_0_P42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_0" + }, + "DSP_R.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { + "can_invert": "0", + "src_wire": "DSP_0_P33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B19_3" + }, + "DSP_R.DSP_GND_R->DSP_0_D15": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15" + }, + "DSP_R.DSP_IMUX31_4->DSP_1_C16": { + "can_invert": "0", + "src_wire": "DSP_IMUX31_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C16" + }, + "DSP_R.DSP_VCC_R->DSP_0_D13": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13" + }, + "DSP_R.DSP_GND_R->DSP_0_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2" + }, + "DSP_R.DSP_IMUX12_0->DSP_1_C22": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C22" + }, + "DSP_R.DSP_0_PCOUT39->DSP_1_PCIN39": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN39" + }, + "DSP_R.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "DSP_0_P41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_0" + }, + "DSP_R.DSP_IMUX29_4->DSP_1_C45": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C45" + }, + "DSP_R.DSP_IMUX1_1->DSP_0_CEB2": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEB2" + }, + "DSP_R.DSP_0_ACOUT20->DSP_1_ACIN20": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN20" + }, + "DSP_R.DSP_IMUX30_1->DSP_1_B4": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B4" + }, + "DSP_R.DSP_VCC_R->DSP_0_D18": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18" + }, + "DSP_R.DSP_0_BCOUT16->DSP_1_BCIN16": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN16" + }, + "DSP_R.DSP_BYP4_3->DSP_1_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_BYP4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE" + }, + "DSP_R.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { + "can_invert": "0", + "src_wire": "DSP_1_P35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_3" + }, + "DSP_R.DSP_0_ACOUT11->DSP_1_ACIN11": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN11" + }, + "DSP_R.DSP_IMUX36_0->DSP_0_B2": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B2" + }, + "DSP_R.DSP_0_PCOUT14->DSP_1_PCIN14": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN14" + }, + "DSP_R.DSP_VCC_R->DSP_1_CEINMODE": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEINMODE" + }, + "DSP_R.DSP_GND_R->DSP_0_D1": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1" + }, + "DSP_R.DSP_BYP4_2->DSP_1_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_BYP4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0" + }, + "DSP_R.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B12_1" + }, + "DSP_R.DSP_IMUX13_4->DSP_1_C18": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C18" + }, + "DSP_R.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { + "can_invert": "0", + "src_wire": "DSP_1_P32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_3" + }, + "DSP_R.DSP_0_PCOUT18->DSP_1_PCIN18": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN18" + }, + "DSP_R.DSP_BYP0_4->DSP_1_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_BYP0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3" + }, + "DSP_R.DSP_0_PCOUT38->DSP_1_PCIN38": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN38" + }, + "DSP_R.DSP_IMUX25_3->DSP_1_C15": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C15" + }, + "DSP_R.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { + "can_invert": "0", + "src_wire": "DSP_1_P24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_1" + }, + "DSP_R.DSP_IMUX46_3->DSP_0_A14": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A14" + }, + "DSP_R.DSP_IMUX24_2->DSP_1_C31": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C31" + }, + "DSP_R.DSP_GND_R->DSP_0_D20": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20" + }, + "DSP_R.DSP_IMUX2_2->DSP_0_C29": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C29" + }, + "DSP_R.DSP_BYP6_2->DSP_0_INMODE3": { + "can_invert": "0", + "src_wire": "DSP_BYP6_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE3" + }, + "DSP_R.DSP_IMUX8_1->DSP_1_B7": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B7" + }, + "DSP_R.DSP_BYP5_3->DSP_0_D13": { + "can_invert": "0", + "src_wire": "DSP_BYP5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D13" + }, + "DSP_R.DSP_IMUX25_2->DSP_1_C11": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C11" + }, + "DSP_R.DSP_BYP6_4->DSP_1_RSTD": { + "can_invert": "0", + "src_wire": "DSP_BYP6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD" + }, + "DSP_R.DSP_IMUX23_4->DSP_1_RSTINMODE": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTINMODE" + }, + "DSP_R.DSP_IMUX3_1->DSP_0_RSTALUMODE": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTALUMODE" + }, + "DSP_R.DSP_0_PCOUT22->DSP_1_PCIN22": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN22" + }, + "DSP_R.DSP_IMUX18_0->DSP_0_C21": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C21" + }, + "DSP_R.DSP_GND_R->DSP_1_D6": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6" + }, + "DSP_R.DSP_0_PCOUT44->DSP_1_PCIN44": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN44" + }, + "DSP_R.DSP_1_PCOUT1->DSP_PCOUT1": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT1" + }, + "DSP_R.DSP_VCC_R->DSP_0_D20": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D20" + }, + "DSP_R.DSP_1_PCOUT30->DSP_PCOUT30": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT30" + }, + "DSP_R.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { + "can_invert": "0", + "src_wire": "DSP_0_PATTERNDETECT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_2" + }, + "DSP_R.DSP_0_PCOUT33->DSP_1_PCIN33": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN33" + }, + "DSP_R.DSP_IMUX24_3->DSP_1_C35": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C35" + }, + "DSP_R.DSP_BYP2_2->DSP_0_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_BYP2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL2" + }, + "DSP_R.DSP_IMUX4_3->DSP_1_A15": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A15" + }, + "DSP_R.DSP_GND_R->DSP_1_D24": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D24" + }, + "DSP_R.DSP_1_PCOUT13->DSP_PCOUT13": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT13" + }, + "DSP_R.DSP_IMUX6_3->DSP_0_A15": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A15" + }, + "DSP_R.DSP_BYP3_0->DSP_0_D2": { + "can_invert": "0", + "src_wire": "DSP_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2" + }, + "DSP_R.DSP_BYP3_1->DSP_0_D6": { + "can_invert": "0", + "src_wire": "DSP_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6" + }, + "DSP_R.DSP_IMUX22_0->DSP_0_B0": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B0" + }, + "DSP_R.DSP_GND_R->DSP_1_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3" + }, + "DSP_R.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { + "can_invert": "0", + "src_wire": "DSP_0_P12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_3" + }, + "DSP_R.DSP_IMUX3_0->DSP_0_C1": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C1" + }, + "DSP_R.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { + "can_invert": "0", + "src_wire": "DSP_1_OVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B8_2" + }, + "DSP_R.DSP_0_ACOUT12->DSP_1_ACIN12": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN12" + }, + "DSP_R.DSP_GND_R->DSP_0_D22": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D22" + }, + "DSP_R.DSP_0_BCOUT5->DSP_1_BCIN5": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN5" + }, + "DSP_R.DSP_FAN5_1->DSP_1_D6": { + "can_invert": "0", + "src_wire": "DSP_FAN5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6" + }, + "DSP_R.DSP_IMUX10_2->DSP_1_C29": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C29" + }, + "DSP_R.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { + "can_invert": "0", + "src_wire": "DSP_1_P25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_1" + }, + "DSP_R.DSP_CLK0_1->DSP_0_CLK": { + "can_invert": "0", + "src_wire": "DSP_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CLK" + }, + "DSP_R.DSP_VCC_R->DSP_1_D5": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5" + }, + "DSP_R.DSP_IMUX15_3->DSP_1_CARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYIN" + }, + "DSP_R.DSP_IMUX40_1->DSP_0_CEA1": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEA1" + }, + "DSP_R.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "DSP_0_PATTERNBDETECT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_2" + }, + "DSP_R.DSP_1_PCOUT46->DSP_PCOUT46": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT46" + }, + "DSP_R.DSP_IMUX42_4->DSP_1_B16": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B16" + }, + "DSP_R.DSP_IMUX11_2->DSP_1_A9": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A9" + }, + "DSP_R.DSP_IMUX8_3->DSP_1_CEB1": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEB1" + }, + "DSP_R.DSP_FAN0_2->DSP_1_D22": { + "can_invert": "0", + "src_wire": "DSP_FAN0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D22" + }, + "DSP_R.DSP_1_PCOUT43->DSP_PCOUT43": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT43" + }, + "DSP_R.DSP_IMUX5_0->DSP_1_A21": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A21" + }, + "DSP_R.DSP_IMUX32_3->DSP_0_C35": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C35" + }, + "DSP_R.DSP_IMUX33_1->DSP_0_C7": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C7" + }, + "DSP_R.DSP_1_ACOUT21->DSP_ACOUT21": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT21" + }, + "DSP_R.DSP_1_PCOUT8->DSP_PCOUT8": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT8" + }, + "DSP_R.DSP_IMUX0_4->DSP_1_ALUMODE0": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE0" + }, + "DSP_R.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { + "can_invert": "0", + "src_wire": "DSP_0_CARRYCASCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYCASCIN" + }, + "DSP_R.DSP_IMUX34_1->DSP_0_C25": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C25" + }, + "DSP_R.DSP_1_PCOUT42->DSP_PCOUT42": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT42" + }, + "DSP_R.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { + "can_invert": "0", + "src_wire": "DSP_0_UNDERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B9_2" + }, + "DSP_R.DSP_0_BCOUT13->DSP_1_BCIN13": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN13" + }, + "DSP_R.DSP_VCC_R->DSP_1_D19": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19" + }, + "DSP_R.DSP_IMUX8_0->DSP_1_C41": { + "can_invert": "0", + "src_wire": "DSP_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C41" + }, + "DSP_R.DSP_1_BCOUT16->DSP_BCOUT16": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT16" + }, + "DSP_R.DSP_0_ACOUT4->DSP_1_ACIN4": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN4" + }, + "DSP_R.DSP_1_PCOUT15->DSP_PCOUT15": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT15" + }, + "DSP_R.DSP_IMUX33_0->DSP_0_C43": { + "can_invert": "0", + "src_wire": "DSP_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C43" + }, + "DSP_R.DSP_IMUX1_4->DSP_0_C19": { + "can_invert": "0", + "src_wire": "DSP_IMUX1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C19" + }, + "DSP_R.DSP_VCC_R->DSP_1_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6" + }, + "DSP_R.DSP_0_PCOUT8->DSP_1_PCIN8": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN8" + }, + "DSP_R.DSP_GND_R->DSP_1_D10": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10" + }, + "DSP_R.DSP_VCC_R->DSP_1_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2" + }, + "DSP_R.DSP_VCC_R->DSP_0_D8": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8" + }, + "DSP_R.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { + "can_invert": "0", + "src_wire": "DSP_1_P6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_1" + }, + "DSP_R.DSP_VCC_R->DSP_0_D15": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D15" + }, + "DSP_R.DSP_FAN0_3->DSP_1_CED": { + "can_invert": "0", + "src_wire": "DSP_FAN0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CED" + }, + "DSP_R.DSP_FAN5_2->DSP_1_D10": { + "can_invert": "0", + "src_wire": "DSP_FAN5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10" + }, + "DSP_R.DSP_GND_R->DSP_0_D12": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12" + }, + "DSP_R.DSP_0_ACOUT27->DSP_1_ACIN27": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN27" + }, + "DSP_R.DSP_FAN5_4->DSP_1_D18": { + "can_invert": "0", + "src_wire": "DSP_FAN5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18" + }, + "DSP_R.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_3" + }, + "DSP_R.DSP_IMUX9_0->DSP_1_A3": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A3" + }, + "DSP_R.DSP_IMUX22_4->DSP_1_RSTALUMODE": { + "can_invert": "0", + "src_wire": "DSP_IMUX22_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTALUMODE" + }, + "DSP_R.DSP_IMUX21_2->DSP_0_A10": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A10" + }, + "DSP_R.DSP_VCC_R->DSP_0_D24": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24" + }, + "DSP_R.DSP_IMUX37_4->DSP_0_C45": { + "can_invert": "0", + "src_wire": "DSP_IMUX37_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C45" + }, + "DSP_R.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { + "can_invert": "0", + "src_wire": "DSP_1_P29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_2" + }, + "DSP_R.DSP_IMUX44_1->DSP_1_A26": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A26" + }, + "DSP_R.DSP_IMUX41_0->DSP_1_C3": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C3" + }, + "DSP_R.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { + "can_invert": "0", + "src_wire": "DSP_0_P1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_0" + }, + "DSP_R.DSP_0_PCOUT42->DSP_1_PCIN42": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN42" + }, + "DSP_R.DSP_BYP5_4->DSP_0_D17": { + "can_invert": "0", + "src_wire": "DSP_BYP5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17" + }, + "DSP_R.DSP_0_ACOUT21->DSP_1_ACIN21": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN21" + }, + "DSP_R.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { + "can_invert": "0", + "src_wire": "DSP_1_P30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_2" + }, + "DSP_R.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { + "can_invert": "0", + "src_wire": "DSP_1_P1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_0" + }, + "DSP_R.DSP_VCC_R->DSP_1_D4": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4" + }, + "DSP_R.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { + "can_invert": "0", + "src_wire": "DSP_1_P18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_4" + }, + "DSP_R.DSP_1_BCOUT2->DSP_BCOUT2": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT2" + }, + "DSP_R.DSP_FAN5_3->DSP_1_D14": { + "can_invert": "0", + "src_wire": "DSP_FAN5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D14" + }, + "DSP_R.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { + "can_invert": "0", + "src_wire": "DSP_1_P9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_2" + }, + "DSP_R.DSP_1_PCOUT47->DSP_PCOUT47": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT47" + }, + "DSP_R.DSP_0_PCOUT35->DSP_1_PCIN35": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN35" + }, + "DSP_R.DSP_1_ACOUT28->DSP_ACOUT28": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT28" + }, + "DSP_R.DSP_IMUX0_0->DSP_1_B3": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B3" + }, + "DSP_R.DSP_VCC_R->DSP_1_D13": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13" + }, + "DSP_R.DSP_GND_R->DSP_1_D23": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23" + }, + "DSP_R.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { + "can_invert": "0", + "src_wire": "DSP_1_P31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B0_2" + }, + "DSP_R.DSP_0_PCOUT20->DSP_1_PCIN20": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN20" + }, + "DSP_R.DSP_IMUX40_0->DSP_0_B3": { + "can_invert": "0", + "src_wire": "DSP_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B3" + }, + "DSP_R.DSP_IMUX19_4->DSP_0_C46": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C46" + }, + "DSP_R.DSP_0_BCOUT0->DSP_1_BCIN0": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN0" + }, + "DSP_R.DSP_IMUX16_3->DSP_1_CEB2": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEB2" + }, + "DSP_R.DSP_BYP1_1->DSP_0_D7": { + "can_invert": "0", + "src_wire": "DSP_BYP1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7" + }, + "DSP_R.DSP_FAN6_3->DSP_1_D13": { + "can_invert": "0", + "src_wire": "DSP_FAN6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13" + }, + "DSP_R.DSP_0_BCOUT1->DSP_1_BCIN1": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN1" + }, + "DSP_R.DSP_IMUX34_2->DSP_0_CEP": { + "can_invert": "0", + "src_wire": "DSP_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEP" + }, + "DSP_R.DSP_BYP5_0->DSP_0_D1": { + "can_invert": "0", + "src_wire": "DSP_BYP5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1" + }, + "DSP_R.DSP_1_PCOUT25->DSP_PCOUT25": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT25" + }, + "DSP_R.DSP_BYP2_3->DSP_0_D23": { + "can_invert": "0", + "src_wire": "DSP_BYP2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23" + }, + "DSP_R.DSP_VCC_R->DSP_0_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEALUMODE" + }, + "DSP_R.DSP_0_ACOUT18->DSP_1_ACIN18": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN18" + }, + "DSP_R.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { + "can_invert": "0", + "src_wire": "DSP_1_P0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_0" + }, + "DSP_R.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "DSP_0_P14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_3" + }, + "DSP_R.DSP_GND_R->DSP_0_D10": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D10" + }, + "DSP_R.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "DSP_0_P32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_3" + }, + "DSP_R.DSP_FAN3_4->DSP_1_D16": { + "can_invert": "0", + "src_wire": "DSP_FAN3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D16" + }, + "DSP_R.DSP_GND_R->DSP_0_D7": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D7" + }, + "DSP_R.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "DSP_0_P28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B17_2" + }, + "DSP_R.DSP_GND_R->DSP_1_CEALUMODE": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEALUMODE" + }, + "DSP_R.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { + "can_invert": "0", + "src_wire": "DSP_1_P10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B6_2" + }, + "DSP_R.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { + "can_invert": "0", + "src_wire": "DSP_1_CARRYOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_3" + }, + "DSP_R.DSP_1_ACOUT17->DSP_ACOUT17": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT17" + }, + "DSP_R.DSP_0_PCOUT16->DSP_1_PCIN16": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN16" + }, + "DSP_R.DSP_IMUX27_2->DSP_0_OPMODE2": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE2" + }, + "DSP_R.DSP_IMUX12_1->DSP_1_C26": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C26" + }, + "DSP_R.DSP_VCC_R->DSP_1_D7": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D7" + }, + "DSP_R.DSP_GND_R->DSP_1_D21": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21" + }, + "DSP_R.DSP_VCC_R->DSP_0_D16": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16" + }, + "DSP_R.DSP_VCC_R->DSP_1_D15": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D15" + }, + "DSP_R.DSP_IMUX5_2->DSP_1_A29": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A29" + }, + "DSP_R.DSP_1_ACOUT24->DSP_ACOUT24": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT24" + }, + "DSP_R.DSP_CTRL0_4->DSP_1_RSTP": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTP" + }, + "DSP_R.DSP_CTRL1_2->DSP_1_RSTA": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTA" + }, + "DSP_R.DSP_IMUX30_4->DSP_1_C36": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C36" + }, + "DSP_R.DSP_1_ACOUT1->DSP_ACOUT1": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT1" + }, + "DSP_R.DSP_IMUX29_0->DSP_1_C2": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C2" + }, + "DSP_R.DSP_IMUX6_1->DSP_0_A27": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A27" + }, + "DSP_R.DSP_VCC_R->DSP_0_D1": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D1" + }, + "DSP_R.DSP_IMUX17_3->DSP_1_CEA2": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CEA2" + }, + "DSP_R.DSP_GND_R->DSP_1_RSTD": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTD" + }, + "DSP_R.DSP_FAN1_1->DSP_1_D21": { + "can_invert": "0", + "src_wire": "DSP_FAN1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D21" + }, + "DSP_R.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { + "can_invert": "0", + "src_wire": "DSP_1_P34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_3" + }, + "DSP_R.DSP_0_ACOUT16->DSP_1_ACIN16": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN16" + }, + "DSP_R.DSP_BYP7_2->DSP_0_D8": { + "can_invert": "0", + "src_wire": "DSP_BYP7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D8" + }, + "DSP_R.DSP_VCC_R->DSP_1_D17": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17" + }, + "DSP_R.DSP_1_ACOUT25->DSP_ACOUT25": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT25" + }, + "DSP_R.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "DSP_0_P5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_1" + }, + "DSP_R.DSP_0_PCOUT19->DSP_1_PCIN19": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN19" + }, + "DSP_R.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { + "can_invert": "0", + "src_wire": "DSP_1_P36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_4" + }, + "DSP_R.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { + "can_invert": "0", + "src_wire": "DSP_0_P37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_4" + }, + "DSP_R.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { + "can_invert": "0", + "src_wire": "DSP_1_P20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B7_0" + }, + "DSP_R.DSP_1_ACOUT15->DSP_ACOUT15": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT15" + }, + "DSP_R.DSP_1_ACOUT13->DSP_ACOUT13": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT13" + }, + "DSP_R.DSP_IMUX18_2->DSP_0_B9": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B9" + }, + "DSP_R.DSP_1_BCOUT4->DSP_BCOUT4": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT4" + }, + "DSP_R.DSP_CTRL1_1->DSP_0_RSTM": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTM" + }, + "DSP_R.DSP_BYP6_3->DSP_0_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_BYP6_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D14": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14" + }, + "DSP_R.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { + "can_invert": "0", + "src_wire": "DSP_IMUX14_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYINSEL1" + }, + "DSP_R.DSP_IMUX24_1->DSP_1_C27": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C27" + }, + "DSP_R.DSP_1_BCOUT12->DSP_BCOUT12": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT12" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE0": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE0" + }, + "DSP_R.DSP_FAN6_4->DSP_1_D17": { + "can_invert": "0", + "src_wire": "DSP_FAN6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D17" + }, + "DSP_R.DSP_BYP5_2->DSP_0_D9": { + "can_invert": "0", + "src_wire": "DSP_BYP5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D9" + }, + "DSP_R.DSP_IMUX15_0->DSP_1_A0": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A0" + }, + "DSP_R.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { + "can_invert": "0", + "src_wire": "DSP_0_P35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_3" + }, + "DSP_R.DSP_IMUX5_3->DSP_1_A13": { + "can_invert": "0", + "src_wire": "DSP_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A13" + }, + "DSP_R.DSP_IMUX0_3->DSP_1_B15": { + "can_invert": "0", + "src_wire": "DSP_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B15" + }, + "DSP_R.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { + "can_invert": "0", + "src_wire": "DSP_1_P8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_2" + }, + "DSP_R.DSP_FAN7_2->DSP_0_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_FAN7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE6" + }, + "DSP_R.DSP_GND_R->DSP_1_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6" + }, + "DSP_R.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { + "can_invert": "0", + "src_wire": "DSP_1_P41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B11_0" + }, + "DSP_R.DSP_IMUX44_0->DSP_1_A22": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A22" + }, + "DSP_R.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { + "can_invert": "0", + "src_wire": "DSP_0_P13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B23_3" + }, + "DSP_R.DSP_0_PCOUT4->DSP_1_PCIN4": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN4" + }, + "DSP_R.DSP_GND_R->DSP_0_D17": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17" + }, + "DSP_R.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "DSP_0_P23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_0" + }, + "DSP_R.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "DSP_1_P40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_0" + }, + "DSP_R.DSP_IMUX44_2->DSP_1_B10": { + "can_invert": "0", + "src_wire": "DSP_IMUX44_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B10" + }, + "DSP_R.DSP_VCC_R->DSP_1_D10": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D10" + }, + "DSP_R.DSP_0_PCOUT17->DSP_1_PCIN17": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN17" + }, + "DSP_R.DSP_0_BCOUT3->DSP_1_BCIN3": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN3" + }, + "DSP_R.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { + "can_invert": "0", + "src_wire": "DSP_0_P10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_2" + }, + "DSP_R.DSP_IMUX25_0->DSP_1_C43": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C43" + }, + "DSP_R.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { + "can_invert": "0", + "src_wire": "DSP_0_P15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B18_3" + }, + "DSP_R.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { + "can_invert": "0", + "src_wire": "DSP_1_PATTERNBDETECT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B15_2" + }, + "DSP_R.DSP_IMUX41_4->DSP_1_C19": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C19" + }, + "DSP_R.DSP_IMUX26_1->DSP_1_C25": { + "can_invert": "0", + "src_wire": "DSP_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C25" + }, + "DSP_R.DSP_0_PCOUT45->DSP_1_PCIN45": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN45" + }, + "DSP_R.DSP_GND_R->DSP_1_D4": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D4" + }, + "DSP_R.DSP_BYP7_4->DSP_0_D16": { + "can_invert": "0", + "src_wire": "DSP_BYP7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D16" + }, + "DSP_R.DSP_BYP7_3->DSP_0_D12": { + "can_invert": "0", + "src_wire": "DSP_BYP7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12" + }, + "DSP_R.DSP_IMUX18_3->DSP_0_C33": { + "can_invert": "0", + "src_wire": "DSP_IMUX18_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C33" + }, + "DSP_R.DSP_VCC_R->DSP_1_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ALUMODE3" + }, + "DSP_R.DSP_GND_R->DSP_1_D18": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D18" + }, + "DSP_R.DSP_1_BCOUT0->DSP_BCOUT0": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT0" + }, + "DSP_R.DSP_IMUX30_2->DSP_0_OPMODE1": { + "can_invert": "0", + "src_wire": "DSP_IMUX30_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE1" + }, + "DSP_R.DSP_GND_R->DSP_0_D23": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D23" + }, + "DSP_R.DSP_0_ACOUT5->DSP_1_ACIN5": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN5" + }, + "DSP_R.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { + "can_invert": "0", + "src_wire": "DSP_1_P33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B5_3" + }, + "DSP_R.DSP_IMUX11_1->DSP_1_A5": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A5" + }, + "DSP_R.DSP_0_PCOUT40->DSP_1_PCIN40": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN40" + }, + "DSP_R.DSP_IMUX29_1->DSP_1_C6": { + "can_invert": "0", + "src_wire": "DSP_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C6" + }, + "DSP_R.DSP_VCC_R->DSP_1_D6": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D6" + }, + "DSP_R.DSP_GND_R->DSP_1_CARRYINSEL2": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_CARRYINSEL2" + }, + "DSP_R.DSP_GND_R->DSP_0_D6": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6" + }, + "DSP_R.DSP_IMUX4_0->DSP_1_A23": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A23" + }, + "DSP_R.DSP_IMUX47_2->DSP_0_A28": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A28" + }, + "DSP_R.DSP_IMUX6_4->DSP_0_A19": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A19" + }, + "DSP_R.DSP_0_PCOUT31->DSP_1_PCIN31": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN31" + }, + "DSP_R.DSP_0_BCOUT17->DSP_1_BCIN17": { + "can_invert": "0", + "src_wire": "DSP_0_BCOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_BCIN17" + }, + "DSP_R.DSP_IMUX28_3->DSP_1_OPMODE0": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE0" + }, + "DSP_R.DSP_VCC_R->DSP_0_D2": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D2" + }, + "DSP_R.DSP_VCC_R->DSP_0_D12": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D12" + }, + "DSP_R.DSP_0_ACOUT22->DSP_1_ACIN22": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN22" + }, + "DSP_R.DSP_1_PCOUT31->DSP_PCOUT31": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT31" + }, + "DSP_R.DSP_FAN2_4->DSP_1_OPMODE6": { + "can_invert": "0", + "src_wire": "DSP_FAN2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE6" + }, + "DSP_R.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { + "can_invert": "0", + "src_wire": "DSP_1_P22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_0" + }, + "DSP_R.DSP_GND_R->DSP_0_D0": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D0" + }, + "DSP_R.DSP_GND_R->DSP_0_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3" + }, + "DSP_R.DSP_VCC_R->DSP_1_D11": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11" + }, + "DSP_R.DSP_GND_R->DSP_1_INMODE2": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE2" + }, + "DSP_R.DSP_BYP2_0->DSP_0_D24": { + "can_invert": "0", + "src_wire": "DSP_BYP2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D24" + }, + "DSP_R.DSP_IMUX19_1->DSP_0_A5": { + "can_invert": "0", + "src_wire": "DSP_IMUX19_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A5" + }, + "DSP_R.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "DSP_1_P42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B10_0" + }, + "DSP_R.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { + "can_invert": "0", + "src_wire": "DSP_1_PATTERNDETECT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_2" + }, + "DSP_R.DSP_IMUX28_1->DSP_1_B6": { + "can_invert": "0", + "src_wire": "DSP_IMUX28_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B6" + }, + "DSP_R.DSP_IMUX47_4->DSP_0_A16": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A16" + }, + "DSP_R.DSP_1_BCOUT11->DSP_BCOUT11": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT11" + }, + "DSP_R.DSP_1_PCOUT10->DSP_PCOUT10": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT10" + }, + "DSP_R.DSP_FAN4_4->DSP_1_D19": { + "can_invert": "0", + "src_wire": "DSP_FAN4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D19" + }, + "DSP_R.DSP_BYP3_3->DSP_0_D14": { + "can_invert": "0", + "src_wire": "DSP_BYP3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D14" + }, + "DSP_R.DSP_0_ACOUT7->DSP_1_ACIN7": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN7" + }, + "DSP_R.DSP_IMUX16_0->DSP_0_C41": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C41" + }, + "DSP_R.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "DSP_1_P46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_4" + }, + "DSP_R.DSP_GND_R->DSP_1_D13": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D13" + }, + "DSP_R.DSP_GND_R->DSP_0_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_INMODE1" + }, + "DSP_R.DSP_1_PCOUT18->DSP_PCOUT18": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT18" + }, + "DSP_R.DSP_IMUX35_3->DSP_0_C13": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C13" + }, + "DSP_R.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { + "can_invert": "0", + "src_wire": "DSP_1_P12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_3" + }, + "DSP_R.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "DSP_0_P46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B13_4" + }, + "DSP_R.DSP_1_PCOUT38->DSP_PCOUT38": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT38" + }, + "DSP_R.DSP_1_PCOUT9->DSP_PCOUT9": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT9" + }, + "DSP_R.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "DSP_0_P18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B16_4" + }, + "DSP_R.DSP_GND_R->DSP_0_D18": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D18" + }, + "DSP_R.DSP_IMUX6_0->DSP_0_A23": { + "can_invert": "0", + "src_wire": "DSP_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A23" + }, + "DSP_R.DSP_0_ACOUT3->DSP_1_ACIN3": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN3" + }, + "DSP_R.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { + "can_invert": "0", + "src_wire": "DSP_1_P38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B2_4" + }, + "DSP_R.DSP_1_PCOUT27->DSP_PCOUT27": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT27" + }, + "DSP_R.DSP_1_PCOUT26->DSP_PCOUT26": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT26" + }, + "DSP_R.DSP_IMUX46_0->DSP_0_A22": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A22" + }, + "DSP_R.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { + "can_invert": "0", + "src_wire": "DSP_0_P16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_4" + }, + "DSP_R.DSP_GND_R->DSP_1_D8": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D8" + }, + "DSP_R.DSP_IMUX41_3->DSP_1_B12": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B12" + }, + "DSP_R.DSP_1_ACOUT19->DSP_ACOUT19": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT19" + }, + "DSP_R.DSP_CTRL1_0->DSP_0_RSTA": { + "can_invert": "0", + "src_wire": "DSP_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTA" + }, + "DSP_R.DSP_FAN4_0->DSP_1_D3": { + "can_invert": "0", + "src_wire": "DSP_FAN4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3" + }, + "DSP_R.DSP_IMUX17_4->DSP_1_OPMODE4": { + "can_invert": "0", + "src_wire": "DSP_IMUX17_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE4" + }, + "DSP_R.DSP_FAN7_3->DSP_1_D23": { + "can_invert": "0", + "src_wire": "DSP_FAN7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D23" + }, + "DSP_R.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { + "can_invert": "0", + "src_wire": "DSP_0_P34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B20_3" + }, + "DSP_R.DSP_FAN4_2->DSP_1_D11": { + "can_invert": "0", + "src_wire": "DSP_FAN4_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D11" + }, + "DSP_R.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { + "can_invert": "0", + "src_wire": "DSP_1_P11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B4_2" + }, + "DSP_R.DSP_IMUX13_3->DSP_0_ALUMODE1": { + "can_invert": "0", + "src_wire": "DSP_IMUX13_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE1" + }, + "DSP_R.DSP_1_BCOUT17->DSP_BCOUT17": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT17" + }, + "DSP_R.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTALLCARRYIN" + }, + "DSP_R.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "DSP_0_P27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B22_1" + }, + "DSP_R.DSP_IMUX45_2->DSP_1_A28": { + "can_invert": "0", + "src_wire": "DSP_IMUX45_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A28" + }, + "DSP_R.DSP_IMUX12_2->DSP_0_OPMODE5": { + "can_invert": "0", + "src_wire": "DSP_IMUX12_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_OPMODE5" + }, + "DSP_R.DSP_IMUX47_1->DSP_0_A24": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A24" + }, + "DSP_R.DSP_VCC_R->DSP_1_D12": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12" + }, + "DSP_R.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "DSP_1_P43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B14_0" + }, + "DSP_R.DSP_IMUX42_1->DSP_0_RSTINMODE": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTINMODE" + }, + "DSP_R.DSP_BYP0_0->DSP_0_ALUMODE3": { + "can_invert": "0", + "src_wire": "DSP_BYP0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_ALUMODE3" + }, + "DSP_R.DSP_IMUX16_4->DSP_1_OPMODE3": { + "can_invert": "0", + "src_wire": "DSP_IMUX16_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE3" + }, + "DSP_R.DSP_IMUX23_3->DSP_0_CARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CARRYIN" + }, + "DSP_R.DSP_IMUX39_4->DSP_0_C16": { + "can_invert": "0", + "src_wire": "DSP_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C16" + }, + "DSP_R.DSP_IMUX47_0->DSP_0_A20": { + "can_invert": "0", + "src_wire": "DSP_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A20" + }, + "DSP_R.DSP_GND_R->DSP_1_D12": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D12" + }, + "DSP_R.DSP_IMUX27_0->DSP_1_C40": { + "can_invert": "0", + "src_wire": "DSP_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C40" + }, + "DSP_R.DSP_IMUX9_4->DSP_1_OPMODE5": { + "can_invert": "0", + "src_wire": "DSP_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_OPMODE5" + }, + "DSP_R.DSP_IMUX20_0->DSP_0_C22": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C22" + }, + "DSP_R.DSP_IMUX11_4->DSP_1_C46": { + "can_invert": "0", + "src_wire": "DSP_IMUX11_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C46" + }, + "DSP_R.DSP_IMUX7_0->DSP_0_A21": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A21" + }, + "DSP_R.DSP_CTRL0_1->DSP_0_RSTC": { + "can_invert": "0", + "src_wire": "DSP_CTRL0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_RSTC" + }, + "DSP_R.DSP_VCC_R->DSP_1_D3": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D3" + }, + "DSP_R.DSP_1_PCOUT37->DSP_PCOUT37": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT37" + }, + "DSP_R.DSP_IMUX21_4->DSP_0_C18": { + "can_invert": "0", + "src_wire": "DSP_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C18" + }, + "DSP_R.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { + "can_invert": "0", + "src_wire": "DSP_1_P17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B1_4" + }, + "DSP_R.DSP_IMUX24_0->DSP_1_C23": { + "can_invert": "0", + "src_wire": "DSP_IMUX24_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C23" + }, + "DSP_R.DSP_IMUX10_1->DSP_1_B5": { + "can_invert": "0", + "src_wire": "DSP_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_B5" + }, + "DSP_R.DSP_0_PCOUT9->DSP_1_PCIN9": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN9" + }, + "DSP_R.DSP_IMUX20_4->DSP_0_C38": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C38" + }, + "DSP_R.DSP_VCC_R->DSP_0_D21": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D21" + }, + "DSP_R.DSP_IMUX41_1->DSP_0_CEB1": { + "can_invert": "0", + "src_wire": "DSP_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEB1" + }, + "DSP_R.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { + "can_invert": "0", + "src_wire": "DSP_IMUX15_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_RSTALLCARRYIN" + }, + "DSP_R.DSP_IMUX2_0->DSP_1_C42": { + "can_invert": "0", + "src_wire": "DSP_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C42" + }, + "DSP_R.DSP_1_BCOUT9->DSP_BCOUT9": { + "can_invert": "0", + "src_wire": "DSP_1_BCOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_BCOUT9" + }, + "DSP_R.DSP_IMUX35_4->DSP_0_C17": { + "can_invert": "0", + "src_wire": "DSP_IMUX35_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C17" + }, + "DSP_R.DSP_VCC_R->DSP_0_D17": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D17" + }, + "DSP_R.DSP_GND_R->DSP_0_D19": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D19" + }, + "DSP_R.DSP_1_PCOUT17->DSP_PCOUT17": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT17" + }, + "DSP_R.DSP_IMUX7_4->DSP_0_A17": { + "can_invert": "0", + "src_wire": "DSP_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A17" + }, + "DSP_R.DSP_IMUX4_1->DSP_1_A27": { + "can_invert": "0", + "src_wire": "DSP_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_A27" + }, + "DSP_R.DSP_1_PCOUT28->DSP_PCOUT28": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT28" + }, + "DSP_R.DSP_1_ACOUT7->DSP_ACOUT7": { + "can_invert": "0", + "src_wire": "DSP_1_ACOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_ACOUT7" + }, + "DSP_R.DSP_IMUX20_3->DSP_0_C34": { + "can_invert": "0", + "src_wire": "DSP_IMUX20_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C34" + }, + "DSP_R.DSP_VCC_R->DSP_0_D6": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_D6" + }, + "DSP_R.DSP_IMUX42_3->DSP_0_B14": { + "can_invert": "0", + "src_wire": "DSP_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B14" + }, + "DSP_R.DSP_IMUX46_4->DSP_0_A18": { + "can_invert": "0", + "src_wire": "DSP_IMUX46_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_A18" + }, + "DSP_R.DSP_0_PCOUT32->DSP_1_PCIN32": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN32" + }, + "DSP_R.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { + "can_invert": "0", + "src_wire": "DSP_0_P0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B21_0" + }, + "DSP_R.DSP_VCC_R->DSP_1_INMODE1": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_INMODE1" + }, + "DSP_R.DSP_1_PCOUT5->DSP_PCOUT5": { + "can_invert": "0", + "src_wire": "DSP_1_PCOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_PCOUT5" + }, + "DSP_R.DSP_IMUX3_3->DSP_0_B13": { + "can_invert": "0", + "src_wire": "DSP_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B13" + }, + "DSP_R.DSP_IMUX25_4->DSP_1_C47": { + "can_invert": "0", + "src_wire": "DSP_IMUX25_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_C47" + }, + "DSP_R.DSP_0_PCOUT10->DSP_1_PCIN10": { + "can_invert": "0", + "src_wire": "DSP_0_PCOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_PCIN10" + }, + "DSP_R.DSP_GND_R->DSP_1_D5": { + "can_invert": "0", + "src_wire": "DSP_GND_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_D5" + }, + "DSP_R.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { + "can_invert": "0", + "src_wire": "DSP_1_P16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_LOGIC_OUTS_B3_4" + }, + "DSP_R.DSP_0_ACOUT6->DSP_1_ACIN6": { + "can_invert": "0", + "src_wire": "DSP_0_ACOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_1_ACIN6" + }, + "DSP_R.DSP_IMUX32_4->DSP_0_C37": { + "can_invert": "0", + "src_wire": "DSP_IMUX32_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_C37" + }, + "DSP_R.DSP_IMUX36_2->DSP_0_B10": { + "can_invert": "0", + "src_wire": "DSP_IMUX36_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_B10" + }, + "DSP_R.DSP_VCC_R->DSP_0_CEAD": { + "can_invert": "0", + "src_wire": "DSP_VCC_R", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "DSP_0_CEAD" + } + }, "wires": [ - "DSP_1_C34", - "DSP_WW2END2_4", - "DSP_0_BCIN16", - "DSP_EE2A3_2", - "DSP_IMUX44_1", - "DSP_0_INMODE3", - "DSP_NE2A3_0", - "DSP_1_C7", - "DSP_EL1BEG1_1", - "DSP_NW2A3_0", - "DSP_IMUX13_4", - "DSP_LOGIC_OUTS_B10_1", - "DSP_BLOCK_OUTS_B2_1", - "DSP_SW4END0_3", - "DSP_0_PCOUT18", - "DSP_BYP2_4", - "DSP_0_C17", - "DSP_0_PCIN25", - "DSP_0_PCOUT17", - "DSP_0_P2", - "DSP_IMUX47_0", - "DSP_WW4A2_3", - "DSP_IMUX28_1", - "DSP_NW2A2_4", - "DSP_1_P34", - "DSP_1_B8", - "DSP_IMUX19_4", - "DSP_EE2BEG3_1", - "DSP_BCOUT8", - "DSP_IMUX17_1", - "DSP_1_BCIN17", - "DSP_LH3_2", - "DSP_NE4BEG2_3", - "DSP_IMUX15_2", - "DSP_EE2A3_4", - "DSP_NE4BEG3_3", - "DSP_SW4A3_0", - "DSP_0_PCOUT6", - "DSP_1_A15", - "DSP_0_P31", - "DSP_1_ACIN25", - "DSP_1_PCIN6", - "DSP_0_ACIN2", - "DSP_BYP2_3", - "DSP_0_D22", - "DSP_0_ACOUT16", - "DSP_VCC_R", - "DSP_WW4B3_1", - "DSP_IMUX45_4", - "DSP_SW2A3_1", - "DSP_0_PCOUT12", - "DSP_SE2A1_2", - "DSP_1_PCIN28", - "DSP_1_A20", - "DSP_WW4A0_0", - "DSP_SE4BEG1_1", - "DSP_0_C45", - "DSP_ER1BEG2_3", - "DSP_1_P22", - "DSP_0_PATTERNBDETECT", - "DSP_EE2A2_3", - "DSP_IMUX23_0", - "DSP_NE4C0_3", - "DSP_0_ACOUT26", - "DSP_0_ACIN11", - "DSP_1_PATTERNBDETECT", - "DSP_NW4A0_3", - "DSP_EE4BEG1_3", - "DSP_LH3_3", - "DSP_BCOUT15", - "DSP_WW2END1_0", - "DSP_EE2A1_0", - "DSP_1_CARRYINSEL2", - "DSP_0_PCIN18", - "DSP_EE4C1_2", - "DSP_ACOUT4", - "DSP_IMUX34_2", - "DSP_EE2A0_1", - "DSP_1_B1", - "DSP_BLOCK_OUTS_B0_3", - "DSP_1_CEC", - "DSP_IMUX14_2", - "DSP_NE4C3_4", - "DSP_WL1END3_2", - "DSP_1_BCIN3", - "DSP_1_BCOUT11", - "DSP_1_A16", - "DSP_WW4C3_1", - "DSP_0_RSTC", - "DSP_PCOUT11", - "DSP_BLOCK_OUTS_B2_2", - "DSP_1_PCOUT45", - "DSP_WW4B1_1", - "DSP_0_B10", - "DSP_EE4B1_2", - "DSP_1_PCIN2", - "DSP_SW4A1_0", - "DSP_WL1END0_4", - "DSP_PCOUT18", - "DSP_PCOUT25", - "DSP_EE4BEG0_4", - "DSP_IMUX21_1", - "DSP_0_RSTALLCARRYIN", - "DSP_1_B10", - "DSP_SW4END3_3", - "DSP_SE4BEG2_0", - "DSP_SE4C3_3", - "DSP_IMUX12_0", - "DSP_EE2A1_3", - "DSP_1_ACIN6", - "DSP_LH11_2", - "DSP_0_P24", - "DSP_PCOUT43", - "DSP_0_A20", - "DSP_LOGIC_OUTS_B14_1", - "DSP_ER1BEG2_2", - "DSP_IMUX39_1", - "DSP_LOGIC_OUTS_B18_0", - "DSP_IMUX21_3", - "DSP_IMUX10_2", - "DSP_0_ACIN19", - "DSP_LOGIC_OUTS_B8_1", - "DSP_1_D13", - "DSP_0_PCIN3", - "DSP_ER1BEG0_0", - "DSP_IMUX25_0", - "DSP_1_PCIN21", - "DSP_NE2A0_4", - "DSP_1_B0", - "DSP_0_PCOUT28", - "DSP_IMUX10_4", - "DSP_NW4A2_1", - "DSP_1_PCIN44", - "DSP_EE2BEG3_0", - "DSP_1_UNDERFLOW", - "DSP_0_PCOUT35", - "DSP_0_C34", - "DSP_0_BCOUT11", - "DSP_IMUX26_3", - "DSP_EE4A3_3", - "DSP_0_PCIN36", - "DSP_IMUX3_4", - "DSP_WR1END0_1", - "DSP_0_PCIN26", - "DSP_1_A22", - "DSP_0_D8", - "DSP_FAN5_4", - "DSP_1_C18", - "DSP_LOGIC_OUTS_B11_4", - "DSP_1_ACOUT4", - "DSP_1_ACIN5", - "DSP_0_PCOUT45", - "DSP_LH12_1", - "DSP_1_D16", - "DSP_1_PCIN1", - "DSP_PCOUT4", - "DSP_EE2BEG1_0", - "DSP_0_PCIN34", - "DSP_WW4END1_2", - "DSP_1_D20", - "DSP_IMUX29_1", - "DSP_IMUX21_2", - "DSP_WW4A3_1", - "DSP_LOGIC_OUTS_B19_0", - "DSP_EE4B0_0", - "DSP_1_PCIN37", - "DSP_LOGIC_OUTS_B20_4", - "DSP_BCOUT2", - "DSP_1_PCOUT1", - "DSP_FAN7_3", - "DSP_0_C4", - "DSP_1_C45", - "DSP_1_PCOUT29", - "DSP_WL1END1_2", - "DSP_1_C39", - "DSP_LH6_3", - "DSP_LH6_4", - "DSP_1_B2", - "DSP_MONITOR_N_4", - "DSP_NE2A1_0", - "DSP_0_RSTD", - "DSP_LH4_3", - "DSP_EE4C0_0", - "DSP_0_A3", - "DSP_LOGIC_OUTS_B13_1", - "DSP_1_P32", - "DSP_1_OPMODE1", - "DSP_1_CLK", - "DSP_MONITOR_N_3", - "DSP_0_PCOUT46", - "DSP_NW2A3_3", - "DSP_IMUX18_3", - "DSP_1_ACIN1", - "DSP_0_B0", - "DSP_BCOUT11", - "DSP_IMUX28_0", - "DSP_BYP4_3", - "DSP_1_PCOUT17", - "DSP_WW2A0_1", - "DSP_SW4A0_2", - "DSP_1_B12", - "DSP_WW2A3_0", - "DSP_1_C43", - "DSP_NE4C1_3", - "DSP_LOGIC_OUTS_B9_1", - "DSP_FAN0_3", - "DSP_NE4C3_0", - "DSP_SW2A2_1", - "DSP_LOGIC_OUTS_B0_2", - "DSP_IMUX18_2", - "DSP_0_BCOUT0", - "DSP_BCOUT7", - "DSP_ACOUT25", - "DSP_NW4A1_2", - "DSP_1_BCOUT8", - "DSP_IMUX37_1", - "DSP_1_PCIN23", - "DSP_1_CARRYIN", - "DSP_LOGIC_OUTS_B8_0", - "DSP_BYP3_3", - "DSP_SW4A1_4", - "DSP_SE2A0_2", - "DSP_0_P0", - "DSP_WW4C1_2", - "DSP_LOGIC_OUTS_B14_3", - "DSP_1_PCOUT5", - "DSP_BYP7_4", - "DSP_EE4C1_3", - "DSP_0_PCIN31", - "DSP_0_D23", - "DSP_0_A15", - "DSP_WW4END1_1", - "DSP_BCOUT17", - "DSP_LOGIC_OUTS_B22_3", - "DSP_0_B15", - "DSP_1_C4", - "DSP_IMUX43_0", - "DSP_IMUX35_1", - "DSP_CTRL1_0", - "DSP_WL1END1_0", - "DSP_EE2BEG2_3", - "DSP_WW2END0_1", - "DSP_1_D10", - "DSP_IMUX0_2", - "DSP_1_CARRYCASCOUT", - "DSP_WW2A3_4", - "DSP_1_C5", - "DSP_1_P2", - "DSP_NW2A0_3", - "DSP_1_PCOUT20", - "DSP_IMUX38_1", - "DSP_0_PCOUT27", - "DSP_EE2BEG3_3", - "DSP_WW2END1_1", - "DSP_LH1_0", - "DSP_1_RSTP", - "DSP_WW2A2_1", - "DSP_SE4C3_1", - "DSP_EE4A0_3", - "DSP_LOGIC_OUTS_B14_0", - "DSP_0_ACOUT15", - "DSP_0_PCIN17", - "DSP_EL1BEG0_0", - "DSP_0_BCOUT8", - "DSP_0_ACOUT5", - "DSP_0_D0", - "DSP_EE4B0_4", - "DSP_0_BCOUT15", - "DSP_0_C25", - "DSP_IMUX24_3", - "DSP_EE2A0_0", - "DSP_0_C1", - "DSP_WW4C2_1", - "DSP_NW2A1_2", - "DSP_SW4A1_2", - "DSP_IMUX9_1", - "DSP_ER1BEG0_2", - "DSP_0_D6", - "DSP_WL1END0_1", - "DSP_PCOUT14", - "DSP_IMUX13_3", - "DSP_PCOUT23", - "DSP_IMUX7_0", - "DSP_WW4C3_4", - "DSP_IMUX30_4", - "DSP_LOGIC_OUTS_B18_3", - "DSP_0_ACIN8", - "DSP_1_C17", - "DSP_LOGIC_OUTS_B12_4", - "DSP_CTRL1_3", - "DSP_SW4END3_2", - "DSP_LH12_2", - "DSP_BYP3_4", - "DSP_WW4B0_2", - "DSP_1_A11", - "DSP_LOGIC_OUTS_B1_0", - "DSP_IMUX27_3", - "DSP_LH1_3", - "DSP_1_PCOUT2", - "DSP_ACOUT13", - "DSP_NW4A3_2", - "DSP_1_PCIN14", - "DSP_0_D10", - "DSP_1_C3", - "DSP_EE4C0_4", - "DSP_1_D17", - "DSP_1_PCIN26", - "DSP_1_ACOUT20", - "DSP_NE4BEG2_1", - "DSP_0_C23", - "DSP_IMUX3_2", - "DSP_IMUX8_0", - "DSP_WW4END1_0", - "DSP_WW4C0_3", - "DSP_IMUX35_0", - "DSP_0_BCIN17", - "DSP_0_PCOUT34", - "DSP_IMUX35_4", - "DSP_0_B13", - "DSP_SW2A3_3", - "DSP_BLOCK_OUTS_B1_3", - "DSP_LH11_0", - "DSP_WW4END3_1", - "DSP_1_ACOUT27", - "DSP_0_B9", - "DSP_WL1END0_2", - "DSP_PCOUT0", - "DSP_NE2A0_0", - "DSP_0_C9", - "DSP_WW2A3_1", - "DSP_SW2A2_0", - "DSP_0_BCIN1", - "DSP_1_A3", - "DSP_IMUX1_4", - "DSP_SW4A0_1", - "DSP_LH1_4", - "DSP_0_C18", - "DSP_0_A23", - "DSP_1_A2", - "DSP_PCOUT34", - "DSP_MONITOR_P_2", - "DSP_0_BCIN12", - "DSP_WW2END2_0", - "DSP_0_A28", - "DSP_EL1BEG1_3", - "DSP_SW4END3_0", - "DSP_EE4C3_3", - "DSP_LOGIC_OUTS_B4_2", - "DSP_1_P33", - "DSP_NW4A3_1", - "DSP_FAN0_4", - "DSP_EE4BEG2_4", - "DSP_IMUX20_1", - "DSP_1_RSTALUMODE", - "DSP_1_PCIN25", - "DSP_0_D13", - "DSP_1_RSTALLCARRYIN", - "DSP_BYP0_2", - "DSP_ACOUT27", - "DSP_NW4END2_3", - "DSP_0_PCOUT40", - "DSP_FAN6_3", - "DSP_0_PCOUT8", - "DSP_LOGIC_OUTS_B13_0", - "DSP_1_PCIN40", - "DSP_WW4B0_1", - "DSP_EE4BEG3_3", - "DSP_LOGIC_OUTS_B12_1", - "DSP_1_D2", - "DSP_1_P11", - "DSP_1_ACOUT21", - "DSP_PCOUT20", - "DSP_FAN0_2", - "DSP_0_C31", - "DSP_LOGIC_OUTS_B23_3", - "DSP_0_RSTM", - "DSP_WW4B2_1", - "DSP_LOGIC_OUTS_B7_4", - "DSP_1_PCIN41", - "DSP_1_C21", - "DSP_NE2A2_3", - "DSP_IMUX13_0", - "DSP_MONITOR_N_1", - "DSP_WW4A0_4", - "DSP_WW4B3_2", - "DSP_1_P46", - "DSP_NW4END3_3", - "DSP_EE4BEG2_1", - "DSP_WL1END2_3", - "DSP_0_PCIN4", - "DSP_WW4C2_2", - "DSP_1_D23", - "DSP_WW4END1_4", - "DSP_IMUX31_1", - "DSP_BYP6_2", - "DSP_EE4BEG2_3", - "DSP_WW4END2_4", - "DSP_WW2END1_2", - "DSP_1_BCOUT3", - "DSP_0_BCIN0", - "DSP_1_A14", - "DSP_WW4END3_0", - "DSP_ER1BEG2_4", - "DSP_WW4C1_3", - "DSP_1_B14", - "DSP_1_ALUMODE0", - "DSP_0_D7", - "DSP_GND_R", - "DSP_SE4BEG2_2", - "DSP_EE4A0_0", - "DSP_0_P11", - "DSP_NW4A3_4", - "DSP_SW4A3_1", - "DSP_1_PCOUT46", - "DSP_PCOUT45", - "DSP_0_P45", - "DSP_1_P45", - "DSP_1_C42", - "DSP_1_BCOUT5", - "DSP_IMUX9_2", - "DSP_WW4A3_2", - "DSP_0_ACIN17", - "DSP_0_C0", - "DSP_EE2A0_3", - "DSP_1_P5", - "DSP_NW2A1_1", - "DSP_LH10_4", - "DSP_LOGIC_OUTS_B7_2", - "DSP_PCOUT46", - "DSP_1_PCIN18", - "DSP_0_B4", - "DSP_0_BCOUT6", - "DSP_FAN0_1", - "DSP_NE2A2_2", - "DSP_EL1BEG2_3", - "DSP_EL1BEG1_2", - "DSP_BLOCK_OUTS_B0_2", - "DSP_FAN1_0", - "DSP_0_BCOUT5", - "DSP_1_PCIN5", - "DSP_1_C12", - "DSP_IMUX3_1", - "DSP_SW4END2_3", - "DSP_1_OPMODE6", - "DSP_1_P37", - "DSP_1_B13", - "DSP_0_PCIN19", - "DSP_IMUX44_3", - "DSP_IMUX6_4", - "DSP_LOGIC_OUTS_B3_4", - "DSP_CLK0_3", - "DSP_1_BCIN8", - "DSP_MONITOR_P_1", - "DSP_WW4B2_3", - "DSP_0_A8", - "DSP_1_A23", - "DSP_0_D18", - "DSP_LOGIC_OUTS_B0_4", - "DSP_EE4A2_4", - "DSP_PCOUT38", - "DSP_BYP2_1", - "DSP_1_ACOUT17", - "DSP_EE2A3_1", - "DSP_0_A10", - "DSP_0_CEALUMODE", - "DSP_1_PCOUT38", - "DSP_1_ACOUT2", - "DSP_0_ACIN24", - "DSP_1_A18", - "DSP_1_P42", - "DSP_SW4A2_3", - "DSP_1_D21", - "DSP_0_B16", - "DSP_IMUX40_1", - "DSP_EE4C2_0", - "DSP_NE4C1_1", - "DSP_EE4BEG3_2", - "DSP_1_PCIN29", - "DSP_1_ACIN0", - "DSP_SE2A0_0", - "DSP_1_ACOUT24", - "DSP_EL1BEG0_1", - "DSP_BCOUT16", - "DSP_EE4B3_4", - "DSP_SW2A0_4", - "DSP_1_P14", - "DSP_0_OPMODE5", - "DSP_BLOCK_OUTS_B0_4", - "DSP_1_ACIN14", - "DSP_1_B9", - "DSP_SE4C2_2", - "DSP_IMUX47_2", - "DSP_BYP0_0", - "DSP_LOGIC_OUTS_B17_1", - "DSP_LH4_2", - "DSP_1_PCOUT37", - "DSP_LOGIC_OUTS_B21_2", - "DSP_1_BCIN14", - "DSP_ACOUT0", - "DSP_1_ACOUT18", - "DSP_0_ACOUT24", - "DSP_1_PCIN17", - "DSP_1_A24", - "DSP_1_ACOUT26", - "DSP_WW4C0_2", - "DSP_LOGIC_OUTS_B9_3", - "DSP_BLOCK_OUTS_B1_4", - "DSP_1_ACOUT10", - "DSP_IMUX34_4", - "DSP_ACOUT24", - "DSP_1_ACOUT0", - "DSP_WW2END2_3", - "DSP_IMUX18_4", - "DSP_WR1END1_0", - "DSP_EE4BEG3_0", - "DSP_EE2BEG0_1", - "DSP_WW4C2_0", - "DSP_WW4C3_0", - "DSP_WW2END2_1", - "DSP_1_C8", - "DSP_EE4C2_3", - "DSP_1_P39", - "DSP_BCOUT5", - "DSP_LOGIC_OUTS_B11_3", - "DSP_0_PCOUT30", - "DSP_IMUX4_3", - "DSP_IMUX37_4", - "DSP_0_ACIN28", - "DSP_1_PCIN10", - "DSP_SW2A0_3", - "DSP_EE4A0_4", - "DSP_IMUX6_1", - "DSP_1_CEM", - "DSP_IMUX11_3", - "DSP_IMUX43_4", - "DSP_LOGIC_OUTS_B20_2", - "DSP_0_PCIN44", - "DSP_1_P28", - "DSP_0_PCIN45", - "DSP_1_D7", - "DSP_WW4B1_2", - "DSP_EE4B0_2", - "DSP_IMUX8_1", - "DSP_0_C39", - "DSP_IMUX2_4", - "DSP_WR1END3_0", - "DSP_NW4END3_0", - "DSP_1_C26", - "DSP_BYP6_1", - "DSP_EE4B3_3", - "DSP_NE4BEG0_1", - "DSP_LOGIC_OUTS_B15_3", - "DSP_1_PCIN30", - "DSP_SW4A1_1", - "DSP_1_PCIN43", - "DSP_ER1BEG0_3", - "DSP_0_RSTCTRL", - "DSP_0_P41", - "DSP_1_A17", - "DSP_0_A26", - "DSP_LOGIC_OUTS_B20_1", - "DSP_PCOUT8", - "DSP_1_RSTD", - "DSP_NW2A2_2", - "DSP_IMUX30_1", - "DSP_NW4END0_0", - "DSP_IMUX44_0", - "DSP_1_D12", - "DSP_0_CEM", - "DSP_WW4C1_4", - "DSP_NW4A0_0", - "DSP_NW4END3_4", - "DSP_0_ALUMODE3", - "DSP_FAN5_3", - "DSP_ACOUT6", - "DSP_BYP5_4", - "DSP_LOGIC_OUTS_B2_0", + "DSP_1_PCOUT16", + "DSP_1_BCIN6", + "DSP_1_PCOUT4", + "DSP_FAN2_1", + "DSP_FAN3_3", "DSP_1_PCIN9", - "DSP_0_PCIN29", - "DSP_0_BCIN5", - "DSP_0_PCIN32", - "DSP_PCOUT33", - "DSP_PCOUT47", + "DSP_0_PCIN23", + "DSP_IMUX28_4", + "DSP_1_PCIN25", + "DSP_EE4BEG3_1", + "DSP_LH5_3", + "DSP_IMUX45_0", + "DSP_0_C16", + "DSP_BYP0_2", + "DSP_1_CARRYCASCOUT", + "DSP_BYP5_0", + "DSP_1_RSTM", + "DSP_LH7_1", + "DSP_LOGIC_OUTS_B14_0", + "DSP_0_CARRYCASCIN", + "DSP_LOGIC_OUTS_B18_2", + "DSP_BLOCK_OUTS_B0_4", + "DSP_IMUX11_0", + "DSP_0_PCIN34", + "DSP_0_RSTM", + "DSP_EE4A2_2", + "DSP_IMUX2_3", + "DSP_0_A13", + "DSP_0_ACOUT12", + "DSP_0_PCOUT20", + "DSP_BYP2_1", + "DSP_0_ACIN20", + "DSP_EL1BEG3_2", + "DSP_VCC_R", + "DSP_1_B11", + "DSP_WW4END3_3", + "DSP_NW4END0_0", + "DSP_SE4C1_4", "DSP_0_B5", - "DSP_EE4BEG2_0", - "DSP_WL1END0_0", - "DSP_SE2A0_1", + "DSP_WW4END1_2", + "DSP_ACOUT6", + "DSP_1_PCOUT43", + "DSP_NE4BEG1_2", + "DSP_1_C16", + "DSP_WW4C2_2", + "DSP_IMUX6_0", + "DSP_WW2A3_1", + "DSP_LOGIC_OUTS_B12_0", + "DSP_0_PCOUT8", + "DSP_SE4C3_1", + "DSP_IMUX34_0", + "DSP_1_P9", + "DSP_1_B8", + "DSP_IMUX27_0", + "DSP_WW4C2_3", + "DSP_1_C20", + "DSP_NE2A2_2", + "DSP_LH7_0", + "DSP_0_B16", + "DSP_0_B0", + "DSP_1_PCIN41", + "DSP_0_A27", + "DSP_NE4BEG2_2", + "DSP_WW4B2_4", + "DSP_BCOUT14", + "DSP_LH8_3", + "DSP_EE2BEG2_3", + "DSP_NE4C2_1", + "DSP_LH4_1", + "DSP_SE2A1_3", + "DSP_0_D21", + "DSP_0_PCOUT45", + "DSP_1_ACOUT15", + "DSP_1_INMODE0", + "DSP_PCOUT38", + "DSP_EE4BEG0_4", + "DSP_0_PCIN35", + "DSP_IMUX35_1", + "DSP_0_ACOUT10", + "DSP_0_A22", + "DSP_WW4C3_1", + "DSP_SE4BEG3_3", + "DSP_IMUX23_3", + "DSP_1_A11", + "DSP_NW4A2_4", + "DSP_1_BCIN16", + "DSP_0_ACIN27", + "DSP_0_RSTALLCARRYIN", + "DSP_1_OPMODE1", + "DSP_ACOUT26", + "DSP_LOGIC_OUTS_B8_0", + "DSP_0_RSTB", + "DSP_0_BCIN11", + "DSP_IMUX20_0", + "DSP_WW4END0_3", + "DSP_0_PCIN28", + "DSP_WW4B0_0", + "DSP_EE4A2_3", + "DSP_IMUX17_4", + "DSP_1_ACOUT9", + "DSP_0_PCOUT17", + "DSP_0_C22", + "DSP_WW4B2_1", + "DSP_EE2BEG1_0", + "DSP_1_CEA1", + "DSP_IMUX24_0", + "DSP_LH6_2", + "DSP_0_MULTSIGNOUT", + "DSP_0_A18", + "DSP_IMUX36_4", + "DSP_1_BCIN11", + "DSP_0_C36", + "DSP_PCOUT12", + "DSP_SE4BEG1_3", + "DSP_0_PCOUT35", + "DSP_LOGIC_OUTS_B12_1", + "DSP_LOGIC_OUTS_B17_4", + "DSP_LH11_0", + "DSP_WL1END1_1", + "DSP_0_C25", + "DSP_EE4B0_4", + "DSP_NW2A2_4", + "DSP_0_C44", + "DSP_ACOUT0", + "DSP_BLOCK_OUTS_B1_3", + "DSP_IMUX16_1", + "DSP_BLOCK_OUTS_B3_3", + "DSP_1_PCOUT7", + "DSP_EL1BEG1_3", + "DSP_0_PCOUT22", + "DSP_EE2BEG2_0", + "DSP_SW4END1_3", + "DSP_FAN7_3", + "DSP_0_D23", + "DSP_1_CARRYCASCIN", + "DSP_1_CLK", + "DSP_WW4A2_1", + "DSP_LH12_2", + "DSP_BYP7_4", + "DSP_0_BCIN17", + "DSP_IMUX30_2", + "DSP_BYP0_3", + "DSP_NE2A3_0", + "DSP_0_RSTA", + "DSP_0_PCOUT0", + "DSP_EE2A3_2", + "DSP_IMUX21_4", + "DSP_WL1END0_2", + "DSP_WW2END2_4", + "DSP_1_PCIN17", + "DSP_IMUX25_4", + "DSP_SW2A3_2", + "DSP_SE4C0_0", + "DSP_EE4A0_2", + "DSP_1_P22", + "DSP_IMUX0_0", + "DSP_NW4END1_3", + "DSP_BYP7_0", + "DSP_0_PCOUT16", + "DSP_1_ACIN19", + "DSP_1_BCOUT16", + "DSP_IMUX43_2", + "DSP_1_P36", + "DSP_IMUX39_1", + "DSP_WW4END0_4", + "DSP_IMUX32_4", + "DSP_1_PCIN6", + "DSP_FAN1_2", + "DSP_NW4END1_4", + "DSP_IMUX26_1", + "DSP_EE4A1_0", + "DSP_SE4C0_2", + "DSP_SE4C1_2", + "DSP_EE2A3_0", + "DSP_IMUX3_3", + "DSP_WW4C1_0", + "DSP_SW4A2_0", + "DSP_ER1BEG3_3", + "DSP_SE4C1_0", + "DSP_SW2A1_0", + "DSP_0_P5", + "DSP_0_P27", + "DSP_ACOUT10", + "DSP_WW4C1_2", + "DSP_0_OPMODE3", + "DSP_LOGIC_OUTS_B21_3", + "DSP_0_P7", + "DSP_NW4A2_3", + "DSP_ACOUT23", + "DSP_0_D19", + "DSP_1_C14", + "DSP_WW2END1_1", + "DSP_1_P10", + "DSP_IMUX24_2", + "DSP_SE4C1_3", + "DSP_FAN7_2", + "DSP_0_C11", + "DSP_GND_R", + "DSP_0_PCOUT15", + "DSP_0_ACOUT4", + "DSP_EE2A2_2", + "DSP_EL1BEG1_0", + "DSP_0_PCIN15", + "DSP_1_ACIN10", + "DSP_WW4C1_3", + "DSP_0_D14", + "DSP_0_ACIN13", + "DSP_0_B15", + "DSP_LH6_3", + "DSP_WW2END2_0", + "DSP_NE2A1_4", + "DSP_WW4C0_3", + "DSP_1_PCOUT33", + "DSP_1_ACOUT3", + "DSP_1_ACOUT21", + "DSP_PCOUT13", + "DSP_0_PCOUT31", + "DSP_1_PCIN10", + "DSP_0_PCOUT10", + "DSP_WR1END3_4", + "DSP_1_C15", + "DSP_1_ACIN3", + "DSP_0_A1", + "DSP_LH1_0", + "DSP_IMUX15_0", + "DSP_NW2A3_1", + "DSP_IMUX44_3", + "DSP_IMUX31_4", + "DSP_ER1BEG0_4", + "DSP_WW2A1_4", + "DSP_0_BCOUT15", + "DSP_EE2A2_3", + "DSP_SW4END2_1", + "DSP_WR1END3_3", + "DSP_1_ALUMODE3", + "DSP_1_ACOUT19", + "DSP_PCOUT42", + "DSP_LOGIC_OUTS_B14_1", + "DSP_LH6_4", + "DSP_SW4A2_2", + "DSP_BYP6_1", + "DSP_1_C39", + "DSP_EE4A1_1", + "DSP_NE4BEG3_1", + "DSP_IMUX13_1", + "DSP_EE4B1_4", + "DSP_NW2A2_2", + "DSP_0_P17", + "DSP_CLK0_2", + "DSP_LOGIC_OUTS_B22_2", + "DSP_1_P44", + "DSP_EE2BEG0_4", + "DSP_NE2A1_1", + "DSP_1_B4", + "DSP_0_A2", + "DSP_1_PCIN24", + "DSP_0_ACIN1", + "DSP_LOGIC_OUTS_B21_2", + "DSP_EE4A2_0", + "DSP_SW2A3_3", + "DSP_PCOUT15", + "DSP_LOGIC_OUTS_B20_1", + "DSP_1_C28", + "DSP_SW2A0_4", + "DSP_0_P8", + "DSP_0_ALUMODE3", + "DSP_IMUX8_3", + "DSP_BYP5_4", + "DSP_0_P9", + "DSP_0_BCIN14", + "DSP_WR1END1_2", + "DSP_1_P45", + "DSP_WW4B2_3", + "DSP_0_D5", + "DSP_WR1END2_3", + "DSP_1_ACOUT29", + "DSP_FAN4_1", + "DSP_1_ACIN14", + "DSP_0_D13", + "DSP_BCOUT8", + "DSP_1_C11", + "DSP_1_PCIN15", + "DSP_0_D24", + "DSP_0_C39", + "DSP_SE4BEG2_4", + "DSP_CLK1_0", + "DSP_WR1END1_0", + "DSP_BYP1_1", + "DSP_0_ACIN8", + "DSP_1_ACOUT2", + "DSP_BCOUT0", + "DSP_NE4C3_0", + "DSP_PCOUT19", + "DSP_FAN3_2", + "DSP_1_PCIN37", + "DSP_WW4END1_4", + "DSP_IMUX13_3", + "DSP_1_BCOUT14", + "DSP_LOGIC_OUTS_B3_0", + "DSP_FAN2_0", + "DSP_IMUX15_2", + "DSP_0_PCIN11", + "DSP_1_A10", + "DSP_BCOUT1", + "DSP_0_PATTERNDETECT", + "DSP_0_PCOUT34", + "DSP_IMUX11_2", + "DSP_0_PCIN12", + "DSP_WW2A1_0", + "DSP_1_OPMODE2", + "DSP_BCOUT12", + "DSP_SW4A0_4", + "DSP_1_RSTC", + "DSP_LOGIC_OUTS_B10_1", + "DSP_1_ACIN22", + "DSP_EE2BEG1_2", + "DSP_0_P6", + "DSP_EE4B1_3", + "DSP_LOGIC_OUTS_B11_1", + "DSP_ER1BEG0_3", + "DSP_IMUX12_1", + "DSP_1_P7", + "DSP_IMUX10_1", + "DSP_IMUX0_1", + "DSP_1_PCOUT8", + "DSP_WW2A2_4", + "DSP_LH3_4", + "DSP_1_CARRYOUT3", + "DSP_NE2A2_4", + "DSP_0_CARRYINSEL0", + "DSP_1_A14", + "DSP_ACOUT2", + "DSP_LOGIC_OUTS_B19_1", + "DSP_BYP6_2", + "DSP_SE2A2_0", + "DSP_NW2A3_0", + "DSP_0_C43", + "DSP_EE4A0_3", + "DSP_1_C35", + "DSP_IMUX5_3", + "DSP_EE4C3_2", + "DSP_IMUX22_4", + "DSP_1_P8", + "DSP_NE4BEG2_4", + "DSP_0_PCIN17", + "DSP_0_D12", + "DSP_WL1END1_4", + "DSP_BYP1_0", + "DSP_EE4C3_0", + "DSP_IMUX20_4", + "DSP_1_P11", + "DSP_0_A0", + "DSP_EE4BEG2_3", + "DSP_1_B12", + "DSP_LOGIC_OUTS_B18_4", + "DSP_NE4C0_4", + "DSP_0_PCOUT33", + "DSP_1_PCIN42", + "DSP_0_PCOUT46", + "DSP_1_PCIN2", + "DSP_1_A8", + "DSP_IMUX22_0", + "DSP_BYP0_1", + "DSP_WW4A0_4", + "DSP_IMUX20_2", + "DSP_0_C32", + "DSP_IMUX1_1", + "DSP_1_CARRYINSEL0", + "DSP_IMUX26_0", + "DSP_0_PCOUT19", + "DSP_0_B7", + "DSP_1_P43", + "DSP_1_D14", + "DSP_1_OPMODE3", + "DSP_EE4A3_1", + "DSP_SE4BEG2_3", + "DSP_SE4BEG1_4", + "DSP_1_A27", + "DSP_IMUX11_1", + "DSP_LOGIC_OUTS_B11_0", + "DSP_1_D9", + "DSP_1_C10", + "DSP_IMUX2_0", + "DSP_SW4END0_2", + "DSP_1_A4", + "DSP_WL1END2_1", + "DSP_0_PCOUT44", + "DSP_0_OPMODE2", + "DSP_EE2A1_1", + "DSP_LH3_1", + "DSP_0_C30", + "DSP_LOGIC_OUTS_B9_3", + "DSP_1_PCOUT1", + "DSP_1_C31", + "DSP_LH5_1", + "DSP_LOGIC_OUTS_B15_4", + "DSP_LH3_2", + "DSP_NW4END2_0", + "DSP_0_BCOUT4", + "DSP_WW4END2_0", + "DSP_BYP4_0", + "DSP_1_CARRYOUT1", + "DSP_LOGIC_OUTS_B11_3", + "DSP_0_PCOUT14", + "DSP_SE4C2_0", + "DSP_0_C35", + "DSP_1_ACIN6", + "DSP_EE2BEG3_0", + "DSP_IMUX31_2", + "DSP_1_ACIN26", + "DSP_0_PCIN25", + "DSP_IMUX15_1", + "DSP_1_ACIN0", + "DSP_IMUX13_4", + "DSP_0_PCIN27", + "DSP_NW4END2_4", + "DSP_0_ACOUT18", + "DSP_0_INMODE1", + "DSP_0_ACIN29", + "DSP_EL1BEG3_1", + "DSP_EE4BEG0_3", + "DSP_NE4C0_0", + "DSP_1_ACIN27", + "DSP_0_CEB1", + "DSP_EL1BEG3_4", + "DSP_IMUX17_3", + "DSP_1_OPMODE6", + "DSP_ER1BEG2_3", + "DSP_BCOUT7", + "DSP_SE2A1_1", + "DSP_0_OPMODE6", + "DSP_EL1BEG2_3", + "DSP_1_ALUMODE1", + "DSP_IMUX38_4", + "DSP_SE4BEG0_3", + "DSP_1_P34", + "DSP_1_P29", + "DSP_IMUX7_0", + "DSP_0_CARRYOUT3", + "DSP_IMUX26_4", + "DSP_LOGIC_OUTS_B16_1", + "DSP_LOGIC_OUTS_B4_2", + "DSP_1_ACOUT12", + "DSP_EL1BEG1_4", + "DSP_WW2END3_0", + "DSP_IMUX38_2", + "DSP_LH9_1", + "DSP_EL1BEG0_3", + "DSP_IMUX44_2", + "DSP_IMUX16_0", + "DSP_NW4END1_2", + "DSP_1_MULTSIGNOUT", + "DSP_ACOUT28", + "DSP_LH11_3", + "DSP_1_PCOUT38", + "DSP_EE4BEG3_0", + "DSP_NE4BEG2_3", + "DSP_1_PCOUT37", + "DSP_ACOUT24", + "DSP_PCOUT29", + "DSP_NW4A2_0", + "DSP_IMUX17_1", + "DSP_0_PCIN1", + "DSP_0_PCOUT24", + "DSP_LH8_0", + "DSP_1_P20", + "DSP_MONITOR_P_2", + "DSP_0_C5", + "DSP_WW2A2_2", + "DSP_WW2END2_2", + "DSP_0_PCOUT25", + "DSP_WR1END0_4", + "DSP_LH3_3", + "DSP_EE4C2_0", + "DSP_EL1BEG3_3", + "DSP_0_PCIN8", + "DSP_SW4A1_3", + "DSP_0_PCOUT29", + "DSP_IMUX29_0", + "DSP_1_C9", + "DSP_0_RSTCTRL", + "DSP_LOGIC_OUTS_B16_4", + "DSP_1_ACIN25", + "DSP_0_P35", + "DSP_1_CARRYOUT0", + "DSP_1_PCIN1", + "DSP_1_ACOUT17", + "DSP_BYP1_2", + "DSP_1_ACOUT28", + "DSP_CLK0_0", + "DSP_LH4_3", + "DSP_LOGIC_OUTS_B17_3", + "DSP_0_C47", + "DSP_0_D2", + "DSP_NE2A0_3", + "DSP_WW2END2_1", + "DSP_1_BCOUT0", + "DSP_LOGIC_OUTS_B5_0", + "DSP_1_A29", + "DSP_0_P15", + "DSP_SE2A2_3", + "DSP_IMUX9_0", + "DSP_0_PCOUT21", + "DSP_LOGIC_OUTS_B11_2", + "DSP_ACOUT11", + "DSP_1_C34", + "DSP_0_D11", + "DSP_0_C20", + "DSP_1_BCIN4", + "DSP_LH12_4", + "DSP_IMUX21_1", + "DSP_EE2BEG0_2", + "DSP_1_PCOUT15", + "DSP_0_PCOUT13", + "DSP_CLK1_4", + "DSP_MONITOR_P_0", + "DSP_PCOUT28", + "DSP_0_PCOUT12", + "DSP_ACOUT18", + "DSP_EE4A0_0", + "DSP_WL1END1_3", + "DSP_ER1BEG3_0", + "DSP_MULTSIGNOUT", + "DSP_1_ACIN23", + "DSP_PCOUT6", + "DSP_IMUX5_2", + "DSP_1_P15", + "DSP_IMUX29_4", + "DSP_1_PCOUT12", + "DSP_1_CARRYIN", + "DSP_NE4C0_3", + "DSP_IMUX40_1", + "DSP_IMUX30_3", + "DSP_1_D13", + "DSP_1_PCOUT10", + "DSP_IMUX2_4", + "DSP_0_ACIN23", + "DSP_BYP2_3", + "DSP_1_C18", + "DSP_0_CARRYINSEL1", + "DSP_LOGIC_OUTS_B21_0", + "DSP_0_BCOUT12", + "DSP_WW4B1_4", + "DSP_0_PCIN41", + "DSP_IMUX3_1", + "DSP_0_PCIN21", + "DSP_LH2_1", + "DSP_1_PCIN38", + "DSP_BLOCK_OUTS_B3_4", + "DSP_LOGIC_OUTS_B22_4", + "DSP_1_PCOUT35", + "DSP_LH1_1", + "DSP_1_INMODE1", + "DSP_NE4C1_1", + "DSP_0_P43", + "DSP_1_PCIN46", + "DSP_WW2END0_2", + "DSP_0_BCOUT9", + "DSP_PCOUT37", + "DSP_IMUX46_4", + "DSP_0_PCIN46", + "DSP_1_PCIN45", "DSP_0_PCOUT38", + "DSP_0_D9", + "DSP_1_B15", + "DSP_EE4B0_0", + "DSP_NW4A1_0", + "DSP_BCOUT15", + "DSP_IMUX41_0", + "DSP_1_PCOUT22", + "DSP_SW4A0_3", + "DSP_SW4END3_1", + "DSP_IMUX0_4", + "DSP_IMUX24_3", + "DSP_0_UNDERFLOW", + "DSP_0_ACOUT24", + "DSP_SE4BEG3_4", + "DSP_NW4A2_1", + "DSP_0_CEA1", + "DSP_LOGIC_OUTS_B6_3", + "DSP_IMUX4_0", + "DSP_SW4A3_3", + "DSP_0_B8", + "DSP_EE2A0_1", + "DSP_IMUX1_0", + "DSP_1_ACOUT6", + "DSP_LOGIC_OUTS_B6_4", + "DSP_CTRL0_0", + "DSP_WW2A3_0", + "DSP_EE4C2_3", + "DSP_1_ACIN18", + "DSP_NW4A0_3", + "DSP_LH7_3", + "DSP_1_BCOUT10", + "DSP_0_ACIN22", + "DSP_WW4B0_3", + "DSP_0_D6", + "DSP_1_CEM", + "DSP_1_A2", + "DSP_1_CEC", + "DSP_NE4C3_2", + "DSP_1_PCOUT5", + "DSP_1_PCIN31", + "DSP_0_D8", + "DSP_EL1BEG0_4", + "DSP_IMUX25_2", + "DSP_1_BCOUT17", + "DSP_0_P4", + "DSP_EL1BEG0_0", + "DSP_0_CEA2", + "DSP_1_PCOUT11", + "DSP_IMUX32_0", + "DSP_1_PCOUT31", + "DSP_1_PCIN35", + "DSP_1_D22", + "DSP_0_C4", + "DSP_CTRL0_2", + "DSP_LH8_1", + "DSP_1_D0", + "DSP_1_ACIN17", + "DSP_0_B1", + "DSP_1_BCIN3", + "DSP_EE4B1_2", + "DSP_WW4C3_3", + "DSP_BYP7_3", + "DSP_0_ACOUT6", + "DSP_SW4END2_2", + "DSP_BYP6_3", + "DSP_BLOCK_OUTS_B1_0", + "DSP_IMUX14_4", + "DSP_NE4C1_2", + "DSP_IMUX18_0", + "DSP_0_A5", + "DSP_0_C0", + "DSP_BYP3_0", + "DSP_PCOUT23", + "DSP_1_BCOUT9", + "DSP_1_RSTP", + "DSP_0_PCIN30", + "DSP_1_C23", + "DSP_PCOUT8", + "DSP_MONITOR_N_0", + "DSP_1_P0", + "DSP_0_P31", + "DSP_SE2A3_0", + "DSP_WR1END0_2", + "DSP_0_C14", + "DSP_0_C27", + "DSP_0_A7", + "DSP_IMUX18_3", + "DSP_ACOUT29", + "DSP_1_A5", + "DSP_1_P3", + "DSP_0_D20", + "DSP_IMUX19_2", + "DSP_SE4BEG1_0", + "DSP_0_A20", + "DSP_NE4C1_4", + "DSP_BYP3_4", + "DSP_1_A25", + "DSP_IMUX28_0", + "DSP_0_CEP", + "DSP_IMUX33_0", + "DSP_LOGIC_OUTS_B19_0", + "DSP_NW4A0_0", + "DSP_WL1END1_0", + "DSP_EE4C0_2", + "DSP_ER1BEG2_1", + "DSP_SE4BEG2_2", + "DSP_IMUX9_4", + "DSP_IMUX4_1", + "DSP_IMUX6_4", + "DSP_WW2A3_2", + "DSP_LOGIC_OUTS_B19_2", + "DSP_EE4BEG3_2", + "DSP_EE4B0_1", + "DSP_EE4C0_0", + "DSP_IMUX8_2", + "DSP_EL1BEG2_0", + "DSP_SE4C2_3", + "DSP_0_ACOUT26", + "DSP_NE4BEG1_0", + "DSP_WL1END3_1", + "DSP_SE2A1_2", + "DSP_1_D21", + "DSP_PCOUT43", + "DSP_LOGIC_OUTS_B13_2", + "DSP_1_P24", + "DSP_1_P41", + "DSP_SE4C2_1", + "DSP_SW4A3_4", + "DSP_SW4END2_3", + "DSP_0_PCIN42", + "DSP_ER1BEG2_2", + "DSP_CTRL0_4", + "DSP_1_PCOUT41", + "DSP_0_ACOUT27", + "DSP_SE4C2_4", + "DSP_FAN1_3", + "DSP_1_CECARRYIN", + "DSP_0_CARRYOUT2", + "DSP_ER1BEG2_4", + "DSP_0_ACIN7", + "DSP_IMUX36_0", + "DSP_IMUX34_3", + "DSP_1_BCOUT1", + "DSP_0_RSTP", + "DSP_IMUX18_1", + "DSP_PCOUT30", + "DSP_LH9_4", + "DSP_1_CEB2", + "DSP_SW2A0_1", + "DSP_0_C24", + "DSP_NE4C2_3", + "DSP_0_INMODE0", + "DSP_PCOUT3", + "DSP_IMUX37_1", + "DSP_IMUX27_2", + "DSP_NW4END3_0", + "DSP_WW4END2_3", + "DSP_BCOUT11", + "DSP_MONITOR_N_3", + "DSP_0_P3", + "DSP_EE2BEG3_4", + "DSP_LOGIC_OUTS_B9_4", + "DSP_1_ACIN4", + "DSP_SW4A3_2", + "DSP_IMUX40_0", + "DSP_1_A16", + "DSP_0_ACOUT22", + "DSP_SW4END3_0", + "DSP_0_PCOUT40", + "DSP_0_D1", + "DSP_IMUX37_4", + "DSP_BCOUT10", + "DSP_0_ACOUT29", + "DSP_1_B2", + "DSP_EE4C3_4", + "DSP_1_BCIN14", + "DSP_SW2A2_2", + "DSP_SW4A2_3", + "DSP_1_BCIN1", + "DSP_0_D16", + "DSP_SW4END3_2", + "DSP_IMUX17_2", + "DSP_FAN1_1", + "DSP_0_P29", + "DSP_0_PCIN4", + "DSP_1_A23", + "DSP_PCOUT21", + "DSP_IMUX47_4", + "DSP_EE4A2_4", + "DSP_1_A3", + "DSP_BYP1_4", + "DSP_NW4A1_2", + "DSP_WW4END0_1", + "DSP_EE2A1_3", + "DSP_BYP4_1", + "DSP_SE2A1_0", + "DSP_1_D1", + "DSP_0_D7", + "DSP_0_PCIN5", + "DSP_1_PCIN0", + "DSP_1_BCOUT15", + "DSP_IMUX43_1", + "DSP_1_OPMODE0", + "DSP_LOGIC_OUTS_B16_2", + "DSP_IMUX33_3", + "DSP_0_B9", + "DSP_IMUX42_0", + "DSP_ER1BEG0_0", + "DSP_0_D4", + "DSP_LH6_0", + "DSP_BLOCK_OUTS_B2_4", + "DSP_EE4A3_2", + "DSP_0_ACIN3", + "DSP_LOGIC_OUTS_B0_0", + "DSP_PCOUT14", + "DSP_PCOUT10", + "DSP_0_PCIN44", + "DSP_SE4BEG2_1", + "DSP_0_PCOUT41", + "DSP_0_PCIN38", + "DSP_1_PCOUT27", + "DSP_BLOCK_OUTS_B2_1", + "DSP_1_PCIN3", + "DSP_FAN6_2", + "DSP_1_ACOUT20", + "DSP_0_P37", + "DSP_IMUX44_0", + "DSP_0_P26", + "DSP_1_C1", + "DSP_0_CECARRYIN", + "DSP_EL1BEG1_2", + "DSP_BCOUT3", + "DSP_IMUX20_1", + "DSP_WW4END2_1", + "DSP_NE2A3_4", + "DSP_MONITOR_N_2", + "DSP_0_ACIN10", + "DSP_FAN6_4", + "DSP_NE4BEG0_4", + "DSP_1_D6", + "DSP_0_PCOUT28", + "DSP_EL1BEG2_2", + "DSP_WW4C1_1", + "DSP_LOGIC_OUTS_B20_0", + "DSP_PCOUT27", + "DSP_1_C19", + "DSP_1_ACOUT25", + "DSP_1_PCOUT3", + "DSP_IMUX3_2", + "DSP_FAN3_4", + "DSP_WW4A1_1", + "DSP_FAN0_4", + "DSP_0_ACIN9", + "DSP_EE4A2_1", + "DSP_1_PCIN20", + "DSP_NE4BEG1_1", + "DSP_LOGIC_OUTS_B20_2", + "DSP_WW2END0_0", + "DSP_0_PCOUT11", + "DSP_IMUX22_3", + "DSP_NE4C3_1", + "DSP_1_A28", + "DSP_WW4C2_0", + "DSP_CTRL1_4", + "DSP_1_PCIN39", + "DSP_FAN7_0", + "DSP_EE4C3_1", + "DSP_1_C40", + "DSP_IMUX4_4", + "DSP_0_C19", + "DSP_IMUX38_0", + "DSP_IMUX12_2", + "DSP_0_C1", + "DSP_LOGIC_OUTS_B23_2", + "DSP_FAN6_0", + "DSP_0_B13", + "DSP_EE4C0_3", + "DSP_0_ACIN16", + "DSP_0_PCIN36", + "DSP_IMUX30_0", + "DSP_SW4A3_1", + "DSP_1_PCIN30", + "DSP_PCOUT24", + "DSP_0_PCIN40", + "DSP_SW4A1_0", + "DSP_0_C12", + "DSP_BYP3_1", + "DSP_IMUX31_3", + "DSP_BLOCK_OUTS_B1_1", + "DSP_EE2BEG1_1", + "DSP_LH3_0", + "DSP_LOGIC_OUTS_B2_4", + "DSP_BCOUT5", + "DSP_1_PCOUT47", + "DSP_0_ACOUT15", + "DSP_1_PCIN23", + "DSP_WW2A0_2", + "DSP_1_ALUMODE2", + "DSP_1_D5", + "DSP_IMUX3_0", + "DSP_LOGIC_OUTS_B11_4", + "DSP_WL1END3_4", + "DSP_1_BCOUT12", + "DSP_IMUX2_1", + "DSP_PCOUT46", + "DSP_0_RSTC", + "DSP_IMUX41_1", + "DSP_LH2_4", + "DSP_WW2END1_0", + "DSP_WW4A3_4", + "DSP_WL1END3_3", + "DSP_IMUX9_1", + "DSP_0_PCOUT37", + "DSP_LOGIC_OUTS_B16_0", + "DSP_1_BCOUT11", + "DSP_NE4C1_3", + "DSP_ACOUT27", + "DSP_1_RSTALUMODE", "DSP_1_OPMODE5", + "DSP_0_BCIN8", + "DSP_0_CEC", + "DSP_0_D18", + "DSP_0_A9", + "DSP_0_BCOUT16", + "DSP_1_INMODE4", + "DSP_LH8_4", + "DSP_0_CED", + "DSP_LOGIC_OUTS_B22_0", + "DSP_1_D4", + "DSP_1_CEAD", + "DSP_BYP1_3", + "DSP_1_BCIN2", + "DSP_0_P38", + "DSP_0_C33", + "DSP_1_ACIN12", + "DSP_1_P28", + "DSP_0_PCIN29", + "DSP_SW2A1_1", + "DSP_1_A9", + "DSP_LOGIC_OUTS_B16_3", + "DSP_1_C2", + "DSP_ACOUT7", + "DSP_WW4C1_4", + "DSP_0_BCOUT7", + "DSP_EE2BEG2_1", + "DSP_SE4BEG2_0", + "DSP_BLOCK_OUTS_B3_0", + "DSP_PCOUT34", + "DSP_EE4B3_0", + "DSP_WW4B3_1", + "DSP_EE4B1_0", + "DSP_EE2BEG1_4", + "DSP_FAN2_3", + "DSP_WW4B3_3", + "DSP_WR1END1_1", + "DSP_LOGIC_OUTS_B5_3", + "DSP_NW4END0_4", + "DSP_0_OPMODE1", + "DSP_LH8_2", + "DSP_LH5_4", + "DSP_0_OPMODE0", + "DSP_LOGIC_OUTS_B0_4", + "DSP_NW4END3_3", + "DSP_1_C36", + "DSP_1_P6", + "DSP_NW4A3_3", + "DSP_1_P2", + "DSP_WL1END3_2", + "DSP_1_ACIN1", + "DSP_0_PCIN33", + "DSP_0_ACIN11", + "DSP_0_P25", + "DSP_0_INMODE2", + "DSP_0_BCIN2", + "DSP_ER1BEG1_4", + "DSP_0_CEINMODE", + "DSP_WL1END2_3", + "DSP_WW2END2_3", + "DSP_SW2A0_2", + "DSP_0_BCIN12", + "DSP_LH10_2", + "DSP_0_ACIN2", + "DSP_1_B9", + "DSP_0_ACOUT5", + "DSP_NW4END2_3", + "DSP_0_PCOUT27", + "DSP_IMUX14_2", + "DSP_WW4A3_0", + "DSP_1_PCOUT13", + "DSP_1_D20", + "DSP_FAN1_4", + "DSP_1_CEALUMODE", + "DSP_BCOUT6", + "DSP_IMUX5_0", + "DSP_1_D7", + "DSP_IMUX29_2", + "DSP_LH9_3", + "DSP_ACOUT17", + "DSP_NE4C2_4", + "DSP_1_P30", + "DSP_1_CEA2", + "DSP_IMUX33_2", + "DSP_1_P38", + "DSP_WL1END2_4", + "DSP_0_C10", + "DSP_0_P13", + "DSP_0_C2", + "DSP_LH10_1", + "DSP_1_C38", + "DSP_0_ALUMODE2", + "DSP_EE2A2_1", + "DSP_SE2A3_4", + "DSP_LOGIC_OUTS_B2_1", + "DSP_1_D19", + "DSP_1_C7", + "DSP_1_P12", + "DSP_0_BCOUT14", + "DSP_IMUX32_1", + "DSP_1_ACOUT5", + "DSP_SW4END3_3", + "DSP_IMUX31_0", + "DSP_1_PCIN22", + "DSP_1_B5", + "DSP_1_P32", + "DSP_BYP5_2", + "DSP_1_C17", + "DSP_0_P16", + "DSP_IMUX19_4", + "DSP_PCOUT39", + "DSP_FAN7_1", + "DSP_LOGIC_OUTS_B13_3", + "DSP_1_RSTD", + "DSP_WW4B3_2", + "DSP_WW4C0_1", + "DSP_0_PCIN13", + "DSP_LOGIC_OUTS_B7_0", + "DSP_IMUX28_2", + "DSP_0_PCOUT43", + "DSP_0_ACOUT8", + "DSP_NW4A0_2", + "DSP_SE2A2_4", + "DSP_1_C33", + "DSP_1_P5", + "DSP_NW4END2_2", + "DSP_LOGIC_OUTS_B3_2", + "DSP_1_ACOUT22", + "DSP_MONITOR_P_4", + "DSP_NE2A2_3", + "DSP_0_P47", + "DSP_IMUX6_3", + "DSP_0_CARRYINSEL2", + "DSP_0_A25", + "DSP_LH9_2", + "DSP_1_PCIN27", + "DSP_IMUX34_4", + "DSP_IMUX10_0", + "DSP_0_PCOUT30", + "DSP_IMUX25_1", + "DSP_0_P18", + "DSP_1_PCIN26", + "DSP_1_A13", + "DSP_1_ACOUT24", + "DSP_1_BCIN7", + "DSP_WW4B3_0", + "DSP_NE2A3_1", + "DSP_WW4C2_4", + "DSP_IMUX47_1", + "DSP_IMUX29_1", + "DSP_0_A6", + "DSP_1_PCIN5", + "DSP_LOGIC_OUTS_B23_4", + "DSP_1_PCOUT26", + "DSP_0_A8", + "DSP_0_B14", + "DSP_0_P2", + "DSP_EE4A3_3", + "DSP_IMUX8_0", + "DSP_0_PCOUT6", + "DSP_LOGIC_OUTS_B4_1", + "DSP_1_C47", + "DSP_ACOUT5", + "DSP_SW4A3_0", + "DSP_NE2A1_3", + "DSP_SW4END0_4", + "DSP_0_PCOUT23", + "DSP_BYP4_2", + "DSP_WL1END1_2", + "DSP_1_RSTB", + "DSP_0_BCIN0", + "DSP_EE4A1_2", + "DSP_1_CEB1", + "DSP_SW4END0_3", + "DSP_1_PCIN28", + "DSP_1_P25", + "DSP_IMUX23_1", + "DSP_1_PCOUT2", + "DSP_0_BCOUT17", + "DSP_WW4B0_2", + "DSP_0_P46", + "DSP_0_A17", + "DSP_ACOUT8", + "DSP_1_P23", + "DSP_0_P40", + "DSP_0_ACOUT17", + "DSP_1_C27", + "DSP_1_C24", + "DSP_NW2A3_3", + "DSP_EE2A2_0", + "DSP_WW4A1_4", + "DSP_1_ACOUT27", + "DSP_LOGIC_OUTS_B3_3", + "DSP_NE2A2_1", + "DSP_SE2A0_0", + "DSP_FAN0_2", + "DSP_PCOUT33", + "DSP_0_PCIN45", + "DSP_0_ACOUT25", + "DSP_BYP2_0", + "DSP_LOGIC_OUTS_B2_2", + "DSP_0_RSTD", + "DSP_0_C17", + "DSP_IMUX28_3", + "DSP_LH4_2", + "DSP_LOGIC_OUTS_B0_1", + "DSP_IMUX1_2", + "DSP_SE4C3_2", + "DSP_1_PCIN34", + "DSP_1_C30", + "DSP_IMUX1_3", + "DSP_1_D16", + "DSP_IMUX4_3", + "DSP_0_ACOUT1", + "DSP_BCOUT16", + "DSP_NW2A1_1", + "DSP_1_D15", + "DSP_EE4B2_0", + "DSP_WW4END3_2", + "DSP_0_ACIN25", + "DSP_1_PCIN33", + "DSP_0_C37", + "DSP_0_BCOUT13", + "DSP_0_INMODE3", + "DSP_WR1END1_3", + "DSP_1_D18", + "DSP_1_RSTA", + "DSP_PCOUT45", + "DSP_IMUX7_4", + "DSP_FAN4_2", + "DSP_EE4A0_4", + "DSP_IMUX5_1", + "DSP_SW2A1_4", + "DSP_WW2END1_2", + "DSP_PCOUT2", + "DSP_1_ACOUT11", + "DSP_LOGIC_OUTS_B14_4", + "DSP_SW4A0_2", + "DSP_1_ACIN20", + "DSP_LOGIC_OUTS_B14_2", + "DSP_WW2A0_1", + "DSP_1_P35", + "DSP_ACOUT20", + "DSP_SE4C3_4", + "DSP_0_P10", + "DSP_EE2A0_3", + "DSP_LH1_4", + "DSP_SW4A0_1", + "DSP_LH1_3", + "DSP_1_BCOUT4", + "DSP_IMUX35_3", + "DSP_NE4BEG1_3", + "DSP_EL1BEG0_1", + "DSP_PCOUT0", + "DSP_LH12_0", + "DSP_LH11_2", + "DSP_LOGIC_OUTS_B13_4", + "DSP_1_PCOUT45", + "DSP_LOGIC_OUTS_B22_3", + "DSP_SE4C3_3", + "DSP_LOGIC_OUTS_B2_0", + "DSP_LOGIC_OUTS_B8_2", + "DSP_0_CARRYOUT0", + "DSP_WR1END3_0", + "DSP_ACOUT25", + "DSP_EE4C2_1", + "DSP_LOGIC_OUTS_B18_1", + "DSP_1_B1", + "DSP_0_PCIN14", + "DSP_IMUX30_1", + "DSP_WR1END0_0", + "DSP_MONITOR_N_4", + "DSP_0_C41", + "DSP_NW4END3_1", + "DSP_WW2A3_3", + "DSP_EE2BEG2_2", + "DSP_PCOUT31", + "DSP_LH10_4", + "DSP_1_ACOUT13", + "DSP_0_PCIN43", + "DSP_FAN7_4", + "DSP_1_D17", + "DSP_CTRL1_0", + "DSP_LOGIC_OUTS_B4_3", + "DSP_WR1END2_2", + "DSP_EE4BEG2_4", + "DSP_CLK0_3", + "DSP_WL1END2_2", + "DSP_WW2END0_3", + "DSP_WW4A2_0", + "DSP_0_A21", + "DSP_LOGIC_OUTS_B10_2", + "DSP_0_D0", + "DSP_ACOUT4", + "DSP_WW4C3_0", + "DSP_NE2A1_0", + "DSP_0_C45", + "DSP_SE4BEG3_1", + "DSP_IMUX36_2", + "DSP_0_PCOUT26", + "DSP_0_D17", + "DSP_1_PCIN13", + "DSP_0_BCIN16", + "DSP_NW4A3_0", + "DSP_0_P0", + "DSP_IMUX32_2", + "DSP_0_ACOUT20", + "DSP_0_INMODE4", + "DSP_0_A23", + "DSP_0_PCOUT18", + "DSP_EE4BEG0_1", + "DSP_SW4A2_1", + "DSP_1_PCIN47", + "DSP_1_ACOUT26", + "DSP_1_MULTSIGNIN", + "DSP_0_A14", + "DSP_BLOCK_OUTS_B1_4", + "DSP_IMUX12_4", + "DSP_BYP5_1", + "DSP_NW2A3_2", + "DSP_1_C5", + "DSP_1_PCOUT40", + "DSP_BYP5_3", + "DSP_1_P33", + "DSP_EE4B3_4", + "DSP_EE2A0_2", + "DSP_0_PCIN7", + "DSP_EE4BEG2_1", + "DSP_NE4BEG1_4", + "DSP_IMUX46_0", + "DSP_IMUX0_2", + "DSP_WL1END0_1", + "DSP_0_P22", + "DSP_NW2A1_0", + "DSP_1_A7", + "DSP_0_PCIN9", + "DSP_NW4END0_1", + "DSP_NW4END1_0", + "DSP_0_C31", + "DSP_WW2A2_1", + "DSP_1_PCOUT46", + "DSP_SW4END0_0", + "DSP_BYP7_1", + "DSP_PCOUT17", + "DSP_ACOUT15", + "DSP_0_C13", + "DSP_IMUX38_1", + "DSP_0_ALUMODE1", + "DSP_IMUX18_4", + "DSP_SE2A0_1", + "DSP_WW4B1_1", + "DSP_NE4BEG3_0", + "DSP_0_ACOUT23", + "DSP_1_ACOUT0", + "DSP_1_B7", + "DSP_1_B14", + "DSP_WW4A1_3", + "DSP_WW2A1_3", + "DSP_BYP4_3", + "DSP_0_P23", + "DSP_1_PCOUT25", + "DSP_WW4A2_4", + "DSP_1_BCOUT7", + "DSP_0_ACIN26", + "DSP_0_ACIN4", + "DSP_0_PCOUT4", + "DSP_1_PCOUT42", + "DSP_BYP4_4", + "DSP_ACOUT9", + "DSP_1_BCOUT6", + "DSP_0_ACIN14", + "DSP_IMUX10_4", + "DSP_IMUX13_2", + "DSP_0_ACIN6", + "DSP_IMUX33_4", + "DSP_NW4A3_4", + "DSP_CTRL0_1", + "DSP_EE4B2_2", + "DSP_NE4BEG0_3", + "DSP_0_PCOUT7", + "DSP_WW2END1_3", + "DSP_NW4A3_1", + "DSP_1_CEP", + "DSP_1_P1", + "DSP_0_P28", + "DSP_SE2A2_2", + "DSP_EE4B0_2", + "DSP_0_P39", + "DSP_LOGIC_OUTS_B15_2", + "DSP_PCOUT40", + "DSP_1_B10", + "DSP_NW2A0_2", + "DSP_0_P1", + "DSP_FAN5_3", + "DSP_EE4C3_3", + "DSP_1_P47", + "DSP_EE4BEG2_2", + "DSP_1_P18", + "DSP_1_ACIN9", + "DSP_1_PCIN14", + "DSP_NW4END2_1", + "DSP_SW2A2_4", + "DSP_LH2_3", + "DSP_0_PCIN20", + "DSP_WW4END1_1", + "DSP_NE2A0_1", + "DSP_NW4A0_4", + "DSP_IMUX13_0", + "DSP_WW2A1_1", + "DSP_LOGIC_OUTS_B0_2", + "DSP_1_C32", + "DSP_WW4C0_0", + "DSP_0_A15", + "DSP_PCOUT11", + "DSP_0_ACOUT2", + "DSP_0_A11", + "DSP_IMUX12_3", + "DSP_1_PCOUT32", + "DSP_IMUX23_4", + "DSP_0_CLK", + "DSP_ER1BEG3_4", + "DSP_FAN5_1", + "DSP_1_PCOUT9", + "DSP_NW2A3_4", + "DSP_0_ACOUT28", + "DSP_0_D10", + "DSP_1_PCIN18", + "DSP_EE4BEG0_2", + "DSP_1_PCOUT19", + "DSP_NW4A1_3", + "DSP_1_C8", + "DSP_NE2A3_3", + "DSP_WW4A2_2", + "DSP_CLK1_1", + "DSP_1_A0", + "DSP_IMUX46_1", + "DSP_1_INMODE2", + "DSP_0_BCOUT5", + "DSP_SE4C0_3", + "DSP_1_CEINMODE", + "DSP_CLK1_3", + "DSP_SE2A1_4", + "DSP_1_PCOUT18", + "DSP_PCOUT41", + "DSP_0_BCIN13", + "DSP_IMUX3_4", + "DSP_EE4A1_4", + "DSP_WW4A0_2", + "DSP_ER1BEG1_0", + "DSP_1_PCOUT21", + "DSP_EE2A3_1", + "DSP_0_PCOUT1", + "DSP_WW2END3_4", + "DSP_0_P33", + "DSP_SE4C0_1", + "DSP_IMUX21_3", + "DSP_EE4B3_2", + "DSP_1_ACIN8", + "DSP_LOGIC_OUTS_B15_1", + "DSP_CTRL1_1", + "DSP_EE4C1_0", + "DSP_NE4BEG2_1", + "DSP_0_CEM", + "DSP_1_PCOUT36", + "DSP_1_C3", + "DSP_WW2A2_3", + "DSP_NE4C2_0", + "DSP_0_BCIN6", + "DSP_1_P27", + "DSP_PCOUT26", + "DSP_0_PCIN16", + "DSP_WW4C0_4", + "DSP_NE2A1_2", + "DSP_LH4_4", + "DSP_LOGIC_OUTS_B15_3", + "DSP_IMUX14_1", + "DSP_1_PCOUT30", + "DSP_WW2A2_0", + "DSP_BLOCK_OUTS_B0_0", + "DSP_IMUX37_2", + "DSP_IMUX40_2", + "DSP_SE2A3_3", + "DSP_IMUX17_0", + "DSP_SE2A0_3", + "DSP_WW4B1_2", + "DSP_NW2A0_0", + "DSP_0_PCIN39", + "DSP_EL1BEG3_0", + "DSP_LOGIC_OUTS_B9_2", + "DSP_1_D2", + "DSP_WR1END3_2", + "DSP_WW4END3_1", + "DSP_0_MULTSIGNIN", + "DSP_1_ACOUT7", + "DSP_LH5_2", + "DSP_WW4END1_0", + "DSP_0_ACOUT14", + "DSP_IMUX22_2", + "DSP_WR1END0_3", + "DSP_1_C25", + "DSP_1_ACOUT14", + "DSP_SE2A0_4", + "DSP_IMUX38_3", + "DSP_0_P24", + "DSP_PCOUT9", + "DSP_1_ACIN21", + "DSP_PCOUT22", + "DSP_0_P34", + "DSP_IMUX36_3", + "DSP_EE4C0_1", + "DSP_IMUX42_1", + "DSP_EL1BEG2_1", + "DSP_1_P14", + "DSP_WW4A3_2", + "DSP_IMUX15_4", + "DSP_FAN3_1", + "DSP_LH4_0", + "DSP_1_RSTCTRL", + "DSP_NW4A3_2", + "DSP_BLOCK_OUTS_B2_3", + "DSP_ACOUT3", + "DSP_1_PCIN4", + "DSP_1_ACIN29", + "DSP_NW2A2_0", + "DSP_SW2A1_3", + "DSP_IMUX29_3", + "DSP_SE4C2_2", + "DSP_IMUX2_2", + "DSP_ER1BEG3_2", + "DSP_LH10_3", + "DSP_0_ACOUT9", + "DSP_0_ACIN19", + "DSP_0_D22", + "DSP_LOGIC_OUTS_B17_0", + "DSP_EE4B3_1", + "DSP_IMUX4_2", + "DSP_NW2A0_3", + "DSP_1_P42", + "DSP_WW4END3_0", + "DSP_EE4BEG3_3", + "DSP_IMUX34_1", + "DSP_0_OPMODE4", + "DSP_1_A15", + "DSP_0_C6", + "DSP_SW4A0_0", + "DSP_CTRL1_3", + "DSP_0_C38", + "DSP_WW2END3_3", + "DSP_ER1BEG1_2", + "DSP_WR1END2_1", + "DSP_CARRYCASCOUT", + "DSP_0_ACOUT13", + "DSP_0_PCOUT32", + "DSP_IMUX41_4", + "DSP_1_A17", + "DSP_EE2BEG3_1", + "DSP_BYP2_4", + "DSP_SW2A3_4", + "DSP_IMUX25_0", + "DSP_1_C37", + "DSP_LOGIC_OUTS_B10_4", + "DSP_0_PCIN0", + "DSP_0_CARRYCASCOUT", + "DSP_ER1BEG1_3", + "DSP_LOGIC_OUTS_B5_4", + "DSP_0_BCIN7", + "DSP_1_C46", + "DSP_IMUX43_0", + "DSP_0_CEAD", + "DSP_1_B3", + "DSP_EE4B0_3", + "DSP_0_C40", + "DSP_IMUX45_2", + "DSP_0_BCOUT6", + "DSP_0_B12", + "DSP_PCOUT47", + "DSP_1_PCIN43", + "DSP_0_A16", + "DSP_LOGIC_OUTS_B5_1", + "DSP_FAN1_0", + "DSP_WW4A0_3", + "DSP_0_BCIN5", + "DSP_BYP7_2", + "DSP_EE2A0_0", + "DSP_WW4C3_2", + "DSP_IMUX37_3", + "DSP_0_B17", + "DSP_EE4BEG3_4", + "DSP_WW4B2_2", + "DSP_1_PATTERNBDETECT", + "DSP_1_C44", + "DSP_WW4B0_1", + "DSP_IMUX45_4", + "DSP_LH11_1", + "DSP_0_BCOUT8", + "DSP_EL1BEG0_2", + "DSP_1_BCIN15", + "DSP_0_PCIN10", + "DSP_NW4END0_2", + "DSP_NW4A0_1", + "DSP_0_ACIN12", + "DSP_0_PCIN47", + "DSP_NW2A1_3", + "DSP_LOGIC_OUTS_B5_2", + "DSP_BYP3_2", + "DSP_IMUX32_3", + "DSP_LOGIC_OUTS_B0_3", + "DSP_1_ACOUT8", + "DSP_1_PCOUT28", + "DSP_1_D12", + "DSP_0_P44", + "DSP_WW4END3_4", + "DSP_0_PCIN19", + "DSP_FAN0_3", + "DSP_SW2A3_1", + "DSP_WL1END0_3", + "DSP_0_PCOUT9", + "DSP_SW2A2_1", + "DSP_0_A4", + "DSP_IMUX35_0", + "DSP_IMUX42_4", + "DSP_1_BCOUT5", + "DSP_0_ALUMODE0", + "DSP_BYP0_0", + "DSP_EE4C1_2", + "DSP_1_P16", + "DSP_1_RSTINMODE", + "DSP_1_PCOUT17", + "DSP_0_CECTRL", + "DSP_LOGIC_OUTS_B22_1", + "DSP_LOGIC_OUTS_B4_4", + "DSP_WW4B2_0", + "DSP_IMUX27_4", + "DSP_0_OPMODE5", + "DSP_0_PCIN37", + "DSP_EE2BEG0_3", + "DSP_IMUX26_3", + "DSP_1_ACIN11", + "DSP_WR1END1_4", + "DSP_LOGIC_OUTS_B12_4", + "DSP_0_ACOUT16", + "DSP_0_ACIN17", + "DSP_EE4C0_4", + "DSP_BYP3_3", + "DSP_IMUX0_3", + "DSP_0_BCIN1", + "DSP_0_P14", + "DSP_1_BCIN12", + "DSP_NW2A2_3", + "DSP_WW4C0_2", + "DSP_WL1END3_0", + "DSP_EE2A1_2", + "DSP_IMUX44_4", + "DSP_IMUX10_3", + "DSP_WW4B0_4", + "DSP_1_BCIN10", + "DSP_1_C21", + "DSP_0_CEB2", + "DSP_EE2BEG3_2", + "DSP_LOGIC_OUTS_B9_1", + "DSP_1_BCOUT3", + "DSP_1_ACIN15", + "DSP_1_D23", + "DSP_1_RSTALLCARRYIN", + "DSP_IMUX14_3", + "DSP_0_B10", + "DSP_0_C42", + "DSP_NE4BEG3_2", + "DSP_ER1BEG0_2", + "DSP_1_PCOUT20", + "DSP_LOGIC_OUTS_B7_3", + "DSP_EE2A1_0", + "DSP_EE2BEG0_1", + "DSP_NW4A1_4", + "DSP_0_P11", + "DSP_0_ACIN24", + "DSP_IMUX35_2", + "DSP_IMUX45_3", + "DSP_1_P21", + "DSP_SW4END1_4", + "DSP_LOGIC_OUTS_B6_2", + "DSP_1_PCOUT6", + "DSP_ER1BEG3_1", + "DSP_WW4A1_2", + "DSP_IMUX8_1", + "DSP_SE4BEG1_2", + "DSP_0_C7", + "DSP_1_ACIN7", + "DSP_1_PCIN40", + "DSP_SW4END2_4", + "DSP_MONITOR_N_1", + "DSP_NE4C3_3", + "DSP_1_PCIN44", + "DSP_IMUX8_4", + "DSP_NW2A2_1", + "DSP_1_C12", + "DSP_EE4A0_1", + "DSP_0_A12", + "DSP_0_D15", + "DSP_EE4A3_0", + "DSP_SE4C1_1", + "DSP_WW2A3_4", + "DSP_0_A29", + "DSP_WR1END2_4", + "DSP_NE4BEG0_1", + "DSP_IMUX23_0", + "DSP_1_BCOUT8", + "DSP_IMUX1_4", + "DSP_NE4BEG0_2", + "DSP_1_D11", + "DSP_0_P36", + "DSP_SE4BEG0_4", + "DSP_1_ACOUT16", + "DSP_IMUX22_1", + "DSP_1_BCOUT2", + "DSP_1_ACIN13", + "DSP_0_C3", + "DSP_NE4C0_2", + "DSP_PCOUT7", + "DSP_1_B17", + "DSP_LOGIC_OUTS_B1_4", + "DSP_BLOCK_OUTS_B2_2", + "DSP_FAN4_3", + "DSP_NW4END3_4", + "DSP_IMUX10_2", + "DSP_IMUX7_1", + "DSP_0_C34", + "DSP_1_C42", + "DSP_WW4C2_1", + "DSP_1_BCIN9", + "DSP_0_ACOUT3", + "DSP_0_BCOUT2", + "DSP_SW4A1_4", + "DSP_1_PCIN36", + "DSP_ACOUT22", + "DSP_BCOUT9", + "DSP_1_ACOUT18", + "DSP_LH7_2", + "DSP_1_BCOUT13", + "DSP_0_PATTERNBDETECT", + "DSP_LOGIC_OUTS_B2_3", + "DSP_EE2BEG1_3", + "DSP_IMUX20_3", + "DSP_1_OPMODE4", + "DSP_EE4B2_3", + "DSP_LOGIC_OUTS_B20_4", + "DSP_WR1END2_0", + "DSP_IMUX42_2", + "DSP_PCOUT44", + "DSP_0_ACIN0", + "DSP_IMUX11_3", + "DSP_1_C4", + "DSP_BCOUT4", + "DSP_IMUX14_0", + "DSP_1_P13", + "DSP_SW4A1_2", + "DSP_EE4B3_3", + "DSP_1_B6", + "DSP_NE4BEG3_4", + "DSP_1_P17", + "DSP_PCOUT18", + "DSP_NW2A1_2", + "DSP_IMUX18_2", + "DSP_WW4A0_0", + "DSP_IMUX47_3", + "DSP_1_D10", + "DSP_NE2A3_2", + "DSP_SE4BEG0_0", + "DSP_1_D8", + "DSP_IMUX36_1", + "DSP_IMUX15_3", + "DSP_0_PCIN31", + "DSP_1_BCIN5", + "DSP_LOGIC_OUTS_B7_2", + "DSP_LOGIC_OUTS_B1_3", + "DSP_1_ACOUT10", + "DSP_0_C26", + "DSP_MONITOR_P_3", + "DSP_PCOUT36", + "DSP_NE4BEG0_0", + "DSP_0_ACIN21", + "DSP_WW4END0_0", + "DSP_LH7_4", + "DSP_0_ACIN28", + "DSP_EE4BEG1_4", + "DSP_1_PATTERNDETECT", + "DSP_IMUX6_1", + "DSP_ER1BEG1_1", + "DSP_LH9_0", + "DSP_CTRL1_2", + "DSP_0_C46", + "DSP_SW2A2_0", + "DSP_LOGIC_OUTS_B13_1", + "DSP_IMUX24_4", + "DSP_IMUX41_2", + "DSP_BYP0_4", + "DSP_NW4END1_1", + "DSP_0_BCOUT11", + "DSP_FAN0_0", + "DSP_1_CARRYINSEL2", + "DSP_IMUX39_0", + "DSP_0_PCIN26", + "DSP_1_C0", + "DSP_LOGIC_OUTS_B3_4", + "DSP_LH2_2", + "DSP_ER1BEG2_0", + "DSP_1_PCOUT29", + "DSP_1_ACOUT1", + "DSP_LOGIC_OUTS_B21_1", + "DSP_1_ACIN16", + "DSP_1_C13", + "DSP_1_P40", + "DSP_LOGIC_OUTS_B12_2", + "DSP_SW4END1_0", + "DSP_WW2A1_2", + "DSP_WW2END1_4", + "DSP_EE2BEG2_4", + "DSP_LOGIC_OUTS_B12_3", + "DSP_FAN5_4", + "DSP_EE4BEG0_0", + "DSP_0_PCOUT36", + "DSP_1_PCOUT23", + "DSP_LOGIC_OUTS_B17_1", + "DSP_PCOUT20", + "DSP_1_A22", + "DSP_1_A6", + "DSP_0_A10", + "DSP_1_C43", + "DSP_WW4END2_2", + "DSP_EE4A3_4", + "DSP_0_ACIN5", + "DSP_IMUX9_3", + "DSP_IMUX44_1", + "DSP_WW4END1_3", + "DSP_BLOCK_OUTS_B2_0", + "DSP_1_ACOUT4", + "DSP_IMUX6_2", + "DSP_BLOCK_OUTS_B0_1", + "DSP_0_P21", + "DSP_WW4B1_3", + "DSP_0_PCIN3", + "DSP_NW4A1_1", + "DSP_FAN5_0", + "DSP_1_BCIN13", + "DSP_WW2END3_1", + "DSP_1_P37", + "DSP_0_ACOUT0", + "DSP_FAN6_1", + "DSP_LH10_0", + "DSP_SE4C0_4", + "DSP_IMUX19_0", + "DSP_WW4C3_4", + "DSP_0_BCIN9", + "DSP_0_B11", + "DSP_LOGIC_OUTS_B17_2", + "DSP_IMUX39_4", + "DSP_BLOCK_OUTS_B0_2", + "DSP_EE4B2_1", + "DSP_LOGIC_OUTS_B8_3", + "DSP_IMUX35_4", + "DSP_IMUX25_3", + "DSP_0_C8", + "DSP_WL1END0_0", + "DSP_NE4C1_0", + "DSP_PCOUT5", + "DSP_SW2A2_3", + "DSP_1_CECTRL", + "DSP_LOGIC_OUTS_B23_3", + "DSP_EE2A0_4", + "DSP_0_PCOUT42", + "DSP_1_PCOUT44", + "DSP_NE4C0_1", + "DSP_LH12_3", + "DSP_WW2END0_4", + "DSP_SE2A0_2", + "DSP_FAN6_3", + "DSP_IMUX26_2", + "DSP_NW2A0_4", + "DSP_NE4C3_4", + "DSP_LOGIC_OUTS_B7_4", + "DSP_FAN3_0", + "DSP_1_D24", + "DSP_0_A26", + "DSP_1_PCIN16", + "DSP_1_P4", + "DSP_LOGIC_OUTS_B13_0", + "DSP_IMUX21_2", + "DSP_SW2A0_0", + "DSP_0_P12", + "DSP_SW4END2_0", + "DSP_BYP6_0", + "DSP_IMUX43_3", + "DSP_EE4BEG1_0", + "DSP_1_PCIN12", + "DSP_1_A21", + "DSP_WW4A3_1", + "DSP_PCOUT35", + "DSP_WL1END2_0", + "DSP_WW4B1_0", + "DSP_IMUX42_3", + "DSP_WW4END0_2", + "DSP_1_CARRYOUT2", + "DSP_BLOCK_OUTS_B3_2", + "DSP_LH11_4", + "DSP_LOGIC_OUTS_B9_0", + "DSP_0_B3", + "DSP_BYP6_4", + "DSP_SE4BEG3_0", + "DSP_EE4C1_3", + "DSP_1_P19", + "DSP_EE2A2_4", + "DSP_NW4END3_2", + "DSP_0_P42", + "DSP_EE4C2_4", + "DSP_LOGIC_OUTS_B1_1", + "DSP_0_A28", + "DSP_FAN4_4", + "DSP_WW2A0_0", + "DSP_ACOUT13", + "DSP_WW4A3_3", + "DSP_WW2END3_2", + "DSP_1_C41", + "DSP_IMUX37_0", + "DSP_LOGIC_OUTS_B10_3", + "DSP_0_BCIN4", + "DSP_IMUX9_2", + "DSP_EL1BEG1_1", + "DSP_IMUX7_2", + "DSP_1_BCIN8", + "DSP_LH5_0", + "DSP_FAN0_1", + "DSP_IMUX24_1", + "DSP_PCOUT25", + "DSP_1_CED", + "DSP_LOGIC_OUTS_B19_3", + "DSP_1_ACOUT23", + "DSP_LH2_0", + "DSP_1_PCOUT24", + "DSP_IMUX16_4", + "DSP_SE2A2_1", + "DSP_0_C28", + "DSP_PCOUT16", + "DSP_LOGIC_OUTS_B8_1", + "DSP_NE4C2_2", + "DSP_ACOUT19", + "DSP_1_PCOUT0", + "DSP_1_B13", + "DSP_1_PCOUT39", + "DSP_FAN4_0", + "DSP_0_ACOUT21", + "DSP_LOGIC_OUTS_B15_0", + "DSP_0_CEALUMODE", + "DSP_EE4BEG1_3", + "DSP_SW4END1_2", + "DSP_1_P31", + "DSP_EE4B1_1", + "DSP_IMUX7_3", + "DSP_0_PCOUT5", + "DSP_WL1END0_4", + "DSP_WR1END0_1", + "DSP_LOGIC_OUTS_B23_0", + "DSP_0_BCIN3", + "DSP_0_RSTALUMODE", + "DSP_IMUX40_4", + "DSP_0_P32", + "DSP_0_C18", + "DSP_SW4END0_1", + "DSP_CTRL0_3", + "DSP_1_A12", + "DSP_WW4A2_3", + "DSP_0_P20", + "DSP_IMUX40_3", + "DSP_PCOUT32", + "DSP_NW4END0_3", + "DSP_IMUX11_4", + "DSP_0_ACOUT11", + "DSP_WW2A0_4", + "DSP_0_A19", + "DSP_SW4A2_4", + "DSP_0_P30", + "DSP_EE2BEG0_0", + "DSP_SW2A0_3", + "DSP_ACOUT14", + "DSP_EE2A3_4", + "DSP_0_ACIN18", + "DSP_LOGIC_OUTS_B19_4", + "DSP_0_PCOUT2", + "DSP_0_PCOUT47", + "DSP_IMUX39_3", + "DSP_IMUX5_4", + "DSP_ACOUT21", + "DSP_LOGIC_OUTS_B4_0", + "DSP_IMUX45_1", + "DSP_1_PCIN29", + "DSP_1_PCIN7", + "DSP_EE4C2_2", + "DSP_0_P45", + "DSP_BYP2_2", + "DSP_1_PCIN8", + "DSP_1_C6", + "DSP_1_ACIN2", + "DSP_WW4A1_0", + "DSP_LOGIC_OUTS_B20_3", + "DSP_1_D3", + "DSP_IMUX41_3", + "DSP_SW4END3_4", + "DSP_0_PCOUT3", + "DSP_0_C9", + "DSP_BLOCK_OUTS_B0_3", + "DSP_IMUX28_1", + "DSP_BLOCK_OUTS_B1_2", + "DSP_0_BCOUT10", + "DSP_0_B6", + "DSP_BCOUT17", + "DSP_1_P39", + "DSP_WW4A0_1", + "DSP_0_PCIN22", + "DSP_ACOUT12", + "DSP_0_PCIN32", + "DSP_1_ALUMODE0", + "DSP_0_B2", + "DSP_PCOUT1", + "DSP_0_A3", + "DSP_1_C26", + "DSP_FAN2_4", + "DSP_IMUX19_1", + "DSP_EE4BEG1_1", + "DSP_LH12_1", + "DSP_IMUX34_2", + "DSP_1_P26", + "DSP_0_BCOUT1", + "DSP_EE4C1_4", + "DSP_1_PCIN11", + "DSP_IMUX31_1", + "DSP_SW2A3_0", + "DSP_0_PCIN18", + "DSP_SE4BEG3_2", + "DSP_LOGIC_OUTS_B7_1", + "DSP_IMUX47_2", + "DSP_1_ACIN24", + "DSP_IMUX46_3", + "DSP_1_A24", + "DSP_WW2END0_1", + "DSP_0_A24", + "DSP_0_PCOUT39", + "DSP_WW4B3_4", + "DSP_LOGIC_OUTS_B3_1", + "DSP_1_PCIN21", + "DSP_1_A1", + "DSP_NE2A0_2", + "DSP_IMUX21_0", + "DSP_CLK0_4", + "DSP_IMUX19_3", + "DSP_0_D3", + "DSP_EL1BEG2_4", + "DSP_FAN2_2", + "DSP_IMUX39_2", + "DSP_1_A20", + "DSP_EE4A1_3", + "DSP_LOGIC_OUTS_B23_1", + "DSP_1_PCIN32", + "DSP_IMUX16_2", + "DSP_NE2A2_0", + "DSP_IMUX27_3", + "DSP_IMUX16_3", + "DSP_0_ACOUT19", + "DSP_IMUX27_1", + "DSP_NE4BEG3_3", + "DSP_LH1_2", + "DSP_LOGIC_OUTS_B18_3", + "DSP_WW4END2_4", + "DSP_FAN5_2", + "DSP_EE2A3_3", + "DSP_0_ACOUT7", + "DSP_0_P41", + "DSP_1_A18", + "DSP_1_BCIN17", + "DSP_1_ACIN28", + "DSP_NW4A2_2", + "DSP_1_UNDERFLOW", + "DSP_SE4BEG0_2", + "DSP_LOGIC_OUTS_B21_4", + "DSP_0_C15", + "DSP_SW4END1_1", + "DSP_0_BCIN15", + "DSP_LOGIC_OUTS_B1_0", + "DSP_LOGIC_OUTS_B6_0", + "DSP_LOGIC_OUTS_B14_3", + "DSP_LOGIC_OUTS_B6_1", + "DSP_ACOUT1", + "DSP_0_C23", + "DSP_CLK0_1", + "DSP_CLK1_2", + "DSP_0_RSTINMODE", + "DSP_LOGIC_OUTS_B10_0", + "DSP_ACOUT16", + "DSP_SE4C3_0", + "DSP_1_ACIN5", + "DSP_1_BCIN0", + "DSP_EE2BEG3_3", + "DSP_1_C45", + "DSP_1_A26", + "DSP_0_CARRYOUT1", + "DSP_NE2A0_0", + "DSP_0_B4", + "DSP_LOGIC_OUTS_B8_4", + "DSP_IMUX43_4", + "DSP_0_P19", + "DSP_0_PCIN2", + "DSP_EE2A1_4", + "DSP_EE4B2_4", + "DSP_NW2A0_1", + "DSP_SE2A3_2", + "DSP_IMUX12_0", + "DSP_WR1END3_1", + "DSP_IMUX46_2", + "DSP_NE2A0_4", + "DSP_1_PCIN19", + "DSP_IMUX30_4", + "DSP_0_PCIN24", + "DSP_0_CARRYIN", + "DSP_0_BCOUT0", + "DSP_BLOCK_OUTS_B3_1", + "DSP_LOGIC_OUTS_B1_2", + "DSP_NW2A1_4", + "DSP_LH6_1", + "DSP_WW2A0_3", + "DSP_0_BCOUT3", + "DSP_1_A19", + "DSP_SW4A1_1", + "DSP_1_B0", + "DSP_0_ACIN15", + "DSP_0_C21", + "DSP_0_BCIN10", + "DSP_EE4BEG2_0", + "DSP_LOGIC_OUTS_B18_0", + "DSP_1_PCOUT34", + "DSP_1_C29", + "DSP_0_PCIN6", + "DSP_BCOUT13", + "DSP_SE2A3_1", + "DSP_EE4C1_1", + "DSP_1_P46", + "DSP_MONITOR_P_1", + "DSP_0_C29", + "DSP_1_OVERFLOW", + "DSP_ER1BEG0_1", + "DSP_1_PCOUT14", "DSP_NE4BEG2_0", "DSP_SE4BEG0_1", - "DSP_EE4A1_3", - "DSP_NE4BEG3_4", - "DSP_IMUX5_1", - "DSP_0_PCOUT32", - "DSP_1_A13", - "DSP_1_P8", - "DSP_1_A12", - "DSP_LOGIC_OUTS_B22_0", - "DSP_1_BCOUT9", - "DSP_1_PCOUT4", - "DSP_IMUX28_3", - "DSP_NE4C3_1", - "DSP_0_BCOUT7", - "DSP_1_PCOUT34", - "DSP_EE4C3_2", - "DSP_1_PCOUT7", - "DSP_PCOUT3", - "DSP_LOGIC_OUTS_B10_0", - "DSP_1_P44", - "DSP_SW4A1_3", - "DSP_IMUX25_2", - "DSP_BYP0_1", - "DSP_1_C6", - "DSP_1_PCOUT10", - "DSP_WW4A1_4", - "DSP_0_ACOUT29", - "DSP_IMUX27_2", - "DSP_SW4END3_1", - "DSP_IMUX28_4", - "DSP_IMUX16_4", - "DSP_SW4END2_2", - "DSP_IMUX46_1", - "DSP_FAN1_2", - "DSP_WW4END0_3", - "DSP_0_UNDERFLOW", - "DSP_LOGIC_OUTS_B17_2", - "DSP_0_PCIN20", - "DSP_NE2A3_4", - "DSP_WW4C1_1", - "DSP_0_BCOUT12", - "DSP_SW2A3_0", - "DSP_EE4C0_3", - "DSP_EL1BEG1_4", - "DSP_1_P29", - "DSP_0_P5", - "DSP_LH9_1", - "DSP_1_PCOUT0", - "DSP_WR1END1_1", - "DSP_NE4BEG1_1", - "DSP_0_C16", - "DSP_NE4BEG0_2", - "DSP_LH6_1", - "DSP_NW4A0_2", - "DSP_MONITOR_P_3", - "DSP_0_PATTERNDETECT", - "DSP_LH10_3", - "DSP_1_B6", - "DSP_1_P7", - "DSP_WW4C0_0", - "DSP_SW4A2_2", - "DSP_EL1BEG2_2", - "DSP_SW4A0_4", - "DSP_IMUX40_3", - "DSP_ACOUT12", - "DSP_FAN5_0", - "DSP_NE4BEG1_0", - "DSP_1_P15", - "DSP_0_CEB1", - "DSP_0_PCIN16", - "DSP_1_PCOUT39", - "DSP_0_P20", - "DSP_LOGIC_OUTS_B16_0", - "DSP_0_P42", - "DSP_IMUX21_4", - "DSP_IMUX36_0", - "DSP_IMUX0_1", - "DSP_SE2A0_3", - "DSP_0_PCIN10", - "DSP_0_P17", - "DSP_EE4C3_4", - "DSP_BYP3_2", - "DSP_LH5_3", - "DSP_EE4BEG1_2", - "DSP_0_P47", - "DSP_1_BCOUT2", - "DSP_IMUX24_0", - "DSP_WW4END3_3", - "DSP_1_A29", - "DSP_SW2A2_3", - "DSP_BLOCK_OUTS_B2_4", - "DSP_1_C41", - "DSP_PCOUT5", - "DSP_IMUX31_4", - "DSP_FAN3_1", - "DSP_BYP1_0", - "DSP_0_BCOUT9", - "DSP_1_BCOUT12", - "DSP_0_A11", - "DSP_0_P7", - "DSP_PCOUT31", - "DSP_1_D9", - "DSP_NE4BEG1_4", - "DSP_IMUX38_4", - "DSP_IMUX30_0", - "DSP_WL1END1_4", - "DSP_EE4B1_4", - "DSP_ER1BEG3_0", - "DSP_IMUX14_1", - "DSP_0_ACOUT9", - "DSP_EE4A2_1", - "DSP_1_BCOUT0", - "DSP_EE2BEG2_4", - "DSP_FAN6_1", - "DSP_1_OPMODE0", - "DSP_ER1BEG1_3", - "DSP_LOGIC_OUTS_B10_2", - "DSP_0_C19", - "DSP_SW4END2_1", - "DSP_PCOUT1", - "DSP_LH8_0", - "DSP_LH7_0", - "DSP_SE4BEG3_1", - "DSP_NE2A1_1", - "DSP_IMUX5_2", - "DSP_IMUX41_0", - "DSP_WW4END0_1", - "DSP_IMUX22_3", - "DSP_1_BCIN2", - "DSP_PCOUT40", - "DSP_1_CEP", - "DSP_SE4BEG2_3", - "DSP_0_BCOUT10", - "DSP_0_CARRYCASCOUT", - "DSP_1_B4", - "DSP_SW2A2_4", - "DSP_1_P43", - "DSP_1_P10", - "DSP_0_ACIN6", - "DSP_NE4C3_3", - "DSP_0_C14", - "DSP_LOGIC_OUTS_B13_2", - "DSP_LH9_2", - "DSP_SW2A1_1", - "DSP_WW2END3_3", - "DSP_1_ACOUT5", - "DSP_0_BCOUT1", - "DSP_EE4B2_0", - "DSP_EE4A2_3", - "DSP_WW2A3_3", - "DSP_NW4A1_0", - "DSP_IMUX2_1", - "DSP_0_PCOUT10", - "DSP_LOGIC_OUTS_B11_1", - "DSP_CLK0_0", - "DSP_IMUX32_1", - "DSP_IMUX10_1", - "DSP_0_B12", - "DSP_0_ACOUT4", - "DSP_WW4END2_0", - "DSP_0_P44", - "DSP_NE4C0_2", - "DSP_IMUX12_2", - "DSP_BLOCK_OUTS_B3_4", - "DSP_1_C11", - "DSP_ACOUT11", - "DSP_0_P15", - "DSP_LOGIC_OUTS_B22_2", - "DSP_0_D11", - "DSP_LOGIC_OUTS_B23_1", - "DSP_LOGIC_OUTS_B8_4", - "DSP_SE4C2_0", - "DSP_IMUX19_0", - "DSP_0_PCOUT22", - "DSP_0_A22", - "DSP_1_PCIN13", - "DSP_IMUX44_2", - "DSP_0_P26", - "DSP_EL1BEG2_4", - "DSP_BYP7_1", - "DSP_SW4A2_4", - "DSP_LH1_2", - "DSP_WR1END0_4", - "DSP_1_ACOUT23", - "DSP_1_PCOUT30", - "DSP_NE4C2_4", - "DSP_MONITOR_N_2", - "DSP_1_P40", - "DSP_0_P35", - "DSP_IMUX46_0", - "DSP_LOGIC_OUTS_B17_0", - "DSP_0_ACOUT3", - "DSP_1_ACIN21", - "DSP_1_OPMODE4", - "DSP_1_D14", - "DSP_IMUX7_4", - "DSP_NE2A2_0", - "DSP_WW4B0_3", - "DSP_WW4C1_0", - "DSP_IMUX45_2", - "DSP_BCOUT9", - "DSP_BCOUT4", - "DSP_1_C1", - "DSP_SE4C0_4", - "DSP_WW4C3_2", - "DSP_EE4C3_1", - "DSP_SW2A3_4", - "DSP_1_C20", - "DSP_LOGIC_OUTS_B2_1", - "DSP_1_C38", - "DSP_0_D17", - "DSP_0_P23", - "DSP_1_PCOUT14", - "DSP_IMUX9_4", - "DSP_1_P47", - "DSP_IMUX5_0", - "DSP_SE4C3_2", - "DSP_1_A7", - "DSP_1_RSTB", - "DSP_IMUX22_2", - "DSP_FAN1_3", - "DSP_1_A27", - "DSP_EE2A2_1", - "DSP_IMUX29_0", - "DSP_IMUX37_2", - "DSP_ACOUT20", - "DSP_0_MULTSIGNOUT", - "DSP_NE4BEG2_2", - "DSP_0_INMODE0", - "DSP_0_PCIN23", - "DSP_1_A1", - "DSP_ER1BEG3_2", - "DSP_NW4END3_2", - "DSP_LOGIC_OUTS_B9_2", - "DSP_0_B6", - "DSP_1_PCIN36", - "DSP_EE4A1_0", - "DSP_0_PCOUT13", - "DSP_0_ACIN5", - "DSP_1_BCIN11", - "DSP_BLOCK_OUTS_B0_1", - "DSP_EE4BEG2_2", - "DSP_1_ACIN12", - "DSP_LH7_2", - "DSP_NE2A0_3", - "DSP_0_C15", - "DSP_0_ACIN0", - "DSP_0_ACOUT2", - "DSP_0_A18", - "DSP_0_D5", - "DSP_SW4A3_3", - "DSP_1_D11", - "DSP_ER1BEG2_0", - "DSP_LOGIC_OUTS_B17_4", - "DSP_FAN3_2", - "DSP_EE4B1_1", - "DSP_WW4B0_0", - "DSP_MONITOR_P_4", - "DSP_SE4C0_0", - "DSP_LH2_3", - "DSP_0_D16", - "DSP_WW2A0_2", - "DSP_1_INMODE4", - "DSP_LOGIC_OUTS_B4_0", - "DSP_BYP6_4", - "DSP_0_PCOUT42", - "DSP_LH2_0", - "DSP_0_PCIN11", - "DSP_0_B14", - "DSP_0_ACIN23", - "DSP_0_CEA2", - "DSP_1_C31", - "DSP_NE4C1_0", - "DSP_0_PCIN22", - "DSP_BLOCK_OUTS_B2_3", - "DSP_IMUX34_3", - "DSP_EE4C0_1", - "DSP_IMUX1_3", - "DSP_WW4A1_3", - "DSP_0_P29", - "DSP_0_PCOUT4", - "DSP_WW4B3_4", - "DSP_LOGIC_OUTS_B12_0", - "DSP_0_ALUMODE2", - "DSP_SE4BEG1_0", - "DSP_1_PCOUT15", - "DSP_0_ACOUT13", - "DSP_CTRL1_4", - "DSP_IMUX41_1", - "DSP_EE2BEG0_3", - "DSP_0_PCOUT26", - "DSP_WW2A0_3", - "DSP_0_B8", - "DSP_NW4END2_4", - "DSP_IMUX20_4", - "DSP_IMUX37_3", - "DSP_BYP4_4", - "DSP_IMUX8_3", - "DSP_IMUX16_3", - "DSP_1_PCOUT26", - "DSP_SE4BEG1_2", - "DSP_0_OPMODE6", - "DSP_0_P36", - "DSP_IMUX36_1", - "DSP_1_ACOUT19", - "DSP_0_BCIN15", - "DSP_NE4BEG3_1", - "DSP_EE4A3_2", - "DSP_NW2A1_3", - "DSP_0_ALUMODE0", - "DSP_LH5_0", - "DSP_1_P18", - "DSP_0_C26", - "DSP_CTRL1_1", - "DSP_1_A4", - "DSP_1_ACOUT1", - "DSP_BYP3_1", - "DSP_IMUX7_1", - "DSP_WW4B1_4", - "DSP_0_A2", - "DSP_NW4END1_4", - "DSP_0_ACIN16", - "DSP_BCOUT3", - "DSP_IMUX13_1", - "DSP_1_CEB2", - "DSP_NW2A0_0", - "DSP_IMUX42_2", - "DSP_FAN6_0", - "DSP_0_ACIN14", - "DSP_WW4A2_2", - "DSP_IMUX42_0", - "DSP_0_PCIN43", - "DSP_1_ALUMODE3", - "DSP_EE2BEG0_0", - "DSP_FAN4_3", - "DSP_WW4C2_3", - "DSP_0_CEA1", - "DSP_1_OPMODE2", - "DSP_0_PCIN37", - "DSP_LOGIC_OUTS_B21_0", - "DSP_0_BCOUT2", - "DSP_1_D19", - "DSP_IMUX39_4", - "DSP_0_INMODE2", - "DSP_1_PATTERNDETECT", - "DSP_NW4END0_1", - "DSP_SW2A1_4", - "DSP_0_A27", - "DSP_WR1END3_4", - "DSP_LOGIC_OUTS_B17_3", - "DSP_1_PCIN46", - "DSP_1_RSTC", - "DSP_0_C28", - "DSP_EE2A3_0", - "DSP_0_OPMODE3", - "DSP_1_CARRYCASCIN", - "DSP_BYP6_0", - "DSP_WW4C2_4", - "DSP_1_C36", - "DSP_1_ACIN18", - "DSP_SE4C3_4", - "DSP_0_D21", - "DSP_1_ACIN9", - "DSP_WW4B3_3", - "DSP_NE4BEG0_4", - "DSP_0_INMODE4", - "DSP_NW4A2_2", - "DSP_EE2BEG1_4", - "DSP_1_BCOUT10", - "DSP_1_BCOUT7", - "DSP_LOGIC_OUTS_B19_1", - "DSP_1_ACIN16", - "DSP_0_PCIN35", - "DSP_IMUX9_3", - "DSP_SW4A0_0", - "DSP_WW4A2_0", - "DSP_WW2A1_3", - "DSP_1_D18", - "DSP_LOGIC_OUTS_B5_1", - "DSP_EE4A2_0", - "DSP_1_PCOUT22", - "DSP_IMUX20_2", - "DSP_1_CECTRL", - "DSP_SE4C0_2", - "DSP_1_BCOUT17", - "DSP_0_PCIN7", - "DSP_1_PCIN39", - "DSP_NW4A1_3", - "DSP_1_P24", - "DSP_1_PCIN35", - "DSP_0_PCOUT39", - "DSP_1_ACIN23", - "DSP_0_C2", - "DSP_ACOUT21", - "DSP_FAN5_1", - "DSP_1_ACIN20", - "DSP_1_A19", - "DSP_1_PCOUT28", - "DSP_IMUX17_3", - "DSP_IMUX15_4", - "DSP_PCOUT35", - "DSP_1_P17", - "DSP_1_C9", - "DSP_0_P13", - "DSP_0_PCIN30", - "DSP_BYP5_2", - "DSP_1_ACOUT11", - "DSP_WL1END2_0", - "DSP_1_P13", - "DSP_1_BCOUT16", - "DSP_0_C8", - "DSP_FAN0_0", - "DSP_IMUX26_4", - "DSP_0_PCIN28", - "DSP_WL1END3_4", - "DSP_0_BCIN9", - "DSP_LOGIC_OUTS_B15_2", - "DSP_WW2END0_0", - "DSP_IMUX10_0", - "DSP_NW2A2_1", - "DSP_0_ACOUT0", - "DSP_1_ACOUT12", - "DSP_WW4A3_3", - "DSP_0_A12", - "DSP_1_ACIN17", - "DSP_0_CARRYOUT3", - "DSP_SW4A0_3", - "DSP_LOGIC_OUTS_B4_1", - "DSP_0_B3", - "DSP_LOGIC_OUTS_B9_4", - "DSP_0_PCOUT24", - "DSP_SE4BEG1_3", - "DSP_IMUX42_3", - "DSP_WW2A1_2", - "DSP_IMUX45_3", - "DSP_0_BCOUT14", - "DSP_NW2A3_1", - "DSP_0_A21", - "DSP_0_P4", - "DSP_1_P19", - "DSP_LOGIC_OUTS_B1_1", - "DSP_0_RSTA", - "DSP_BYP1_4", - "DSP_WW4A0_1", - "DSP_ACOUT15", - "DSP_1_ACOUT29", - "DSP_1_B5", - "DSP_LOGIC_OUTS_B16_4", - "DSP_0_PCIN12", - "DSP_EE2A2_0", - "DSP_0_A16", - "DSP_PCOUT22", - "DSP_1_C37", - "DSP_1_P3", - "DSP_NE2A2_4", - "DSP_SW4A3_2", - "DSP_SE2A3_2", - "DSP_NW4A2_0", - "DSP_1_PCIN20", - "DSP_0_RSTALUMODE", - "DSP_EE4A3_0", - "DSP_0_ACOUT6", - "DSP_0_C12", - "DSP_0_P1", - "DSP_1_PCOUT11", - "DSP_LH2_2", - "DSP_WW4B1_3", - "DSP_LOGIC_OUTS_B6_4", - "DSP_CTRL0_1", - "DSP_EE4BEG0_0", - "DSP_LOGIC_OUTS_B15_4", - "DSP_IMUX38_3", - "DSP_WW4A1_2", - "DSP_NW4END1_1", - "DSP_0_BCOUT4", - "DSP_0_ACIN7", - "DSP_0_OPMODE4", - "DSP_1_PCOUT44", - "DSP_LOGIC_OUTS_B18_2", - "DSP_BCOUT12", - "DSP_0_PCOUT0", - "DSP_1_OPMODE3", - "DSP_IMUX6_0", - "DSP_SE2A2_1", - "DSP_1_ACOUT22", - "DSP_WW2A2_0", - "DSP_IMUX21_0", - "DSP_MULTSIGNOUT", - "DSP_WW4B0_4", - "DSP_EL1BEG3_2", - "DSP_1_C47", - "DSP_NE4BEG2_4", - "DSP_0_PCIN46", - "DSP_IMUX32_2", - "DSP_WW4A1_1", - "DSP_0_ACOUT10", - "DSP_1_BCIN5", - "DSP_1_BCOUT6", - "DSP_1_CEAD", - "DSP_0_C6", - "DSP_1_PCOUT21", - "DSP_LOGIC_OUTS_B6_1", - "DSP_0_PCIN39", - "DSP_FAN1_1", - "DSP_LOGIC_OUTS_B0_1", - "DSP_IMUX25_4", - "DSP_LOGIC_OUTS_B2_3", - "DSP_IMUX42_1", - "DSP_1_C24", - "DSP_1_BCOUT4", - "DSP_1_BCIN9", - "DSP_NE2A0_2", - "DSP_1_A6", - "DSP_SE4C0_3", - "DSP_EE4A1_4", - "DSP_0_PCIN27", - "DSP_WW2END0_3", - "DSP_0_ACOUT17", - "DSP_NE4C2_1", - "DSP_0_PCIN40", - "DSP_1_BCIN10", - "DSP_WL1END3_3", - "DSP_IMUX9_0", - "DSP_NW4A1_4", - "DSP_BYP2_2", - "DSP_IMUX29_2", - "DSP_0_ACIN20", - "DSP_LOGIC_OUTS_B9_0", - "DSP_1_C46", - "DSP_0_P12", - "DSP_0_P32", - "DSP_ACOUT3", - "DSP_EE4C1_4", - "DSP_WW2A1_4", - "DSP_EE2BEG1_3", - "DSP_LH12_0", - "DSP_0_P46", - "DSP_LOGIC_OUTS_B14_4", - "DSP_EE4C2_2", - "DSP_ACOUT29", - "DSP_NE4BEG3_2", - "DSP_1_ACOUT3", - "DSP_1_C10", - "DSP_NW4END1_0", - "DSP_1_BCOUT14", - "DSP_FAN2_4", - "DSP_SW2A0_2", - "DSP_1_INMODE3", - "DSP_0_ACOUT28", - "DSP_1_BCOUT13", - "DSP_IMUX27_0", - "DSP_MONITOR_N_0", - "DSP_0_OPMODE0", - "DSP_IMUX4_4", - "DSP_IMUX3_0", - "DSP_EE4B2_2", - "DSP_IMUX47_1", - "DSP_IMUX11_4", - "DSP_SE2A3_1", - "DSP_1_P9", - "DSP_SW4END0_2", - "DSP_EL1BEG3_1", - "DSP_0_C27", - "DSP_NE4BEG0_3", - "DSP_EE4C2_4", - "DSP_0_PCIN47", - "DSP_0_P18", - "DSP_WL1END1_1", - "DSP_0_CARRYIN", - "DSP_1_BCIN12", - "DSP_IMUX4_2", - "DSP_NW4A0_4", - "DSP_1_ACIN22", - "DSP_NE2A1_4", - "DSP_IMUX47_4", - "DSP_SE4C1_3", - "DSP_1_D0", - "DSP_WW2A2_2", - "DSP_WR1END0_2", - "DSP_0_D3", - "DSP_SW4END1_0", - "DSP_0_B2", - "DSP_1_INMODE1", - "DSP_NE4C0_0", - "DSP_0_P8", - "DSP_1_P38", - "DSP_SE4BEG3_2", - "DSP_0_PCIN1", - "DSP_SW2A0_0", - "DSP_ER1BEG1_1", - "DSP_EE4BEG1_1", - "DSP_1_C35", - "DSP_1_B16", - "DSP_1_C23", - "DSP_WW4END3_2", - "DSP_EE4B0_3", - "DSP_LOGIC_OUTS_B19_4", - "DSP_0_ACIN1", - "DSP_NE4C0_1", - "DSP_WW2A0_4", - "DSP_ER1BEG2_1", - "DSP_0_BCIN6", - "DSP_EE4B1_3", - "DSP_0_BCOUT3", - "DSP_IMUX24_1", - "DSP_0_P28", - "DSP_IMUX11_2", - "DSP_IMUX1_1", - "DSP_FAN2_0", - "DSP_WR1END2_0", - "DSP_SW2A3_2", - "DSP_CLK1_4", - "DSP_SE4C2_4", - "DSP_1_PCOUT6", - "DSP_SE4C1_1", - "DSP_0_P25", - "DSP_BLOCK_OUTS_B1_0", - "DSP_SE4C1_0", - "DSP_IMUX2_2", - "DSP_0_C41", - "DSP_1_D6", - "DSP_0_P27", - "DSP_1_PCOUT43", - "DSP_EE2BEG0_2", - "DSP_WW2END2_2", - "DSP_LH7_3", - "DSP_0_A25", - "DSP_SE2A3_4", - "DSP_0_C47", - "DSP_0_A0", - "DSP_0_PCIN38", - "DSP_ACOUT28", - "DSP_NE2A2_1", - "DSP_0_B7", - "DSP_IMUX39_3", - "DSP_MONITOR_P_0", - "DSP_IMUX1_2", - "DSP_1_BCOUT1", - "DSP_LOGIC_OUTS_B7_3", - "DSP_PCOUT16", - "DSP_LOGIC_OUTS_B11_0", - "DSP_IMUX33_2", - "DSP_PCOUT42", - "DSP_0_D20", - "DSP_1_C28", - "DSP_SE4BEG0_4", - "DSP_0_ACIN22", - "DSP_1_PCIN3", - "DSP_0_A5", - "DSP_LOGIC_OUTS_B13_4", - "DSP_IMUX17_0", - "DSP_EE4B3_0", - "DSP_1_C40", - "DSP_0_PCOUT37", - "DSP_IMUX5_4", - "DSP_IMUX22_0", - "DSP_0_C20", - "DSP_WW4C3_3", - "DSP_0_A1", - "DSP_1_PCIN24", - "DSP_ACOUT5", - "DSP_1_C13", - "DSP_IMUX11_1", - "DSP_EE4C0_2", - "DSP_EE2BEG3_4", - "DSP_0_OVERFLOW", - "DSP_LH5_1", - "DSP_1_B15", - "DSP_0_D1", - "DSP_NW2A2_0", - "DSP_CLK1_2", - "DSP_IMUX40_0", - "DSP_1_P6", - "DSP_SW4END0_0", - "DSP_IMUX46_3", - "DSP_0_ACIN3", - "DSP_1_ALUMODE2", - "DSP_IMUX41_4", - "DSP_LOGIC_OUTS_B5_4", - "DSP_IMUX11_0", - "DSP_IMUX40_4", - "DSP_FAN4_4", - "DSP_EE2A2_2", - "DSP_0_PCOUT9", - "DSP_SE4BEG0_3", - "DSP_IMUX16_1", - "DSP_0_ACIN18", - "DSP_0_CARRYOUT1", - "DSP_NE4C2_3", - "DSP_IMUX17_2", - "DSP_IMUX27_1", - "DSP_LOGIC_OUTS_B5_2", - "DSP_ACOUT7", - "DSP_0_D15", - "DSP_IMUX23_4", - "DSP_EE4B2_1", - "DSP_1_BCOUT15", - "DSP_LOGIC_OUTS_B1_3", - "DSP_0_ACOUT19", - "DSP_0_B17", - "DSP_SE2A2_3", - "DSP_WW4C0_4", - "DSP_ACOUT9", - "DSP_SW4END1_4", - "DSP_EE4A1_2", - "DSP_EE2A3_3", - "DSP_IMUX6_3", - "DSP_0_C33", - "DSP_LOGIC_OUTS_B21_3", - "DSP_1_PCOUT19", - "DSP_LOGIC_OUTS_B5_0", - "DSP_LH3_0", - "DSP_0_ACOUT23", - "DSP_IMUX36_4", - "DSP_WW2A1_1", - "DSP_NE2A3_1", - "DSP_SE4C1_2", - "DSP_LH2_4", - "DSP_SW2A1_2", - "DSP_LOGIC_OUTS_B16_2", - "DSP_WR1END1_3", - "DSP_SE2A1_3", - "DSP_LOGIC_OUTS_B15_0", - "DSP_IMUX2_0", - "DSP_LOGIC_OUTS_B5_3", - "DSP_WW2END1_4", - "DSP_PCOUT26", - "DSP_FAN2_3", - "DSP_EL1BEG1_0", - "DSP_EE4C2_1", - "DSP_0_P30", - "DSP_NE2A0_1", - "DSP_ACOUT1", - "DSP_1_A9", - "DSP_1_BCIN13", - "DSP_BYP3_0", - "DSP_0_PCOUT21", - "DSP_PCOUT10", - "DSP_1_ACIN4", - "DSP_BCOUT1", - "DSP_LH8_4", - "DSP_WW2END3_1", - "DSP_BLOCK_OUTS_B3_2", - "DSP_WL1END2_4", - "DSP_IMUX1_0", - "DSP_1_ACOUT25", - "DSP_1_PCIN0", - "DSP_0_C38", - "DSP_IMUX31_0", - "DSP_WR1END3_2", - "DSP_NW4A2_4", "DSP_1_CARRYINSEL1", - "DSP_WW4A3_0", - "DSP_BYP6_3", - "DSP_0_P16", - "DSP_0_RSTINMODE", - "DSP_FAN7_4", - "DSP_0_A7", - "DSP_FAN6_4", - "DSP_1_OVERFLOW", - "DSP_LH10_2", - "DSP_IMUX17_4", - "DSP_0_ACOUT27", - "DSP_1_D1", - "DSP_0_P19", - "DSP_0_PCIN41", - "DSP_BYP1_2", - "DSP_1_P23", - "DSP_SW4END1_2", - "DSP_1_P36", - "DSP_0_PCOUT2", - "DSP_0_ACIN9", - "DSP_1_CEINMODE", - "DSP_SE4BEG3_3", - "DSP_0_PCOUT7", - "DSP_WW2A3_2", - "DSP_WR1END2_4", - "DSP_IMUX7_2", - "DSP_0_P21", - "DSP_EE4A0_1", - "DSP_LH3_4", - "DSP_0_OPMODE1", - "DSP_IMUX27_4", - "DSP_LOGIC_OUTS_B23_0", - "DSP_1_D15", - "DSP_IMUX46_2", - "DSP_0_BCIN11", - "DSP_IMUX8_4", - "DSP_NW4END2_0", - "DSP_0_A24", - "DSP_0_P33", - "DSP_1_B17", - "DSP_SW4A2_0", - "DSP_WW4END0_2", - "DSP_IMUX26_2", - "DSP_WW2A1_0", - "DSP_NW2A1_0", - "DSP_1_PCOUT33", - "DSP_WR1END0_3", - "DSP_PCOUT6", - "DSP_WL1END0_3", - "DSP_0_MULTSIGNIN", - "DSP_0_P38", - "DSP_1_PCIN11", - "DSP_1_PCIN47", - "DSP_0_CARRYINSEL1", - "DSP_IMUX20_0", - "DSP_CTRL0_3", - "DSP_LOGIC_OUTS_B21_1", - "DSP_LH11_3", - "DSP_0_A4", - "DSP_1_P16", - "DSP_PCOUT28", - "DSP_0_PCIN24", - "DSP_WW2END3_4", - "DSP_0_C40", - "DSP_1_PCOUT18", - "DSP_1_INMODE2", - "DSP_1_PCOUT13", - "DSP_IMUX30_3", - "DSP_1_PCOUT16", - "DSP_EE4BEG0_2", - "DSP_0_PCOUT47", - "DSP_1_PCIN31", - "DSP_1_CEB1", - "DSP_WW2A0_0", - "DSP_PCOUT41", - "DSP_WW4A0_3", - "DSP_NW4A0_1", - "DSP_LH9_0", - "DSP_IMUX32_3", - "DSP_1_P31", - "DSP_0_PCOUT41", - "DSP_BCOUT0", - "DSP_1_C14", - "DSP_LOGIC_OUTS_B22_4", - "DSP_0_PCIN0", - "DSP_0_ACIN29", - "DSP_IMUX8_2", - "DSP_1_P25", - "DSP_EE4BEG1_4", - "DSP_1_BCIN7", - "DSP_IMUX35_2", - "DSP_ER1BEG1_0", - "DSP_0_P43", - "DSP_NE4C0_4", - "DSP_WW2END0_4", - "DSP_0_P10", - "DSP_0_OPMODE2", - "DSP_0_PCIN8", - "DSP_1_D22", - "DSP_0_BCIN4", - "DSP_0_P34", - "DSP_1_CARRYOUT1", - "DSP_WR1END3_3", + "DSP_SW2A1_2", "DSP_IMUX23_2", - "DSP_0_P39", - "DSP_1_BCIN1", - "DSP_1_PCOUT31", - "DSP_0_ACOUT25", - "DSP_IMUX35_3", - "DSP_FAN6_2", - "DSP_IMUX39_0", - "DSP_1_P21", - "DSP_LOGIC_OUTS_B3_2", - "DSP_EE4BEG3_4", - "DSP_0_D24", - "DSP_1_P1", - "DSP_0_ACOUT14", - "DSP_CTRL0_0", - "DSP_FAN4_1", - "DSP_FAN4_2", - "DSP_SE4C0_1", - "DSP_ACOUT16", - "DSP_1_PCOUT25", - "DSP_1_PCOUT35", - "DSP_IMUX28_2", - "DSP_0_ACOUT8", - "DSP_LH9_4", - "DSP_WW4B2_0", - "DSP_LOGIC_OUTS_B4_4", - "DSP_1_CARRYOUT3", - "DSP_1_C16", - "DSP_IMUX33_3", - "DSP_SE4C2_1", - "DSP_0_B1", - "DSP_1_PCIN22", - "DSP_1_C19", - "DSP_1_A8", - "DSP_IMUX40_2", - "DSP_1_ACOUT14", - "DSP_WW4END0_0", - "DSP_PCOUT17", - "DSP_IMUX16_2", - "DSP_0_PCIN13", - "DSP_BYP0_3", - "DSP_WW4C0_1", - "DSP_WR1END1_2", - "DSP_EE4B3_1", - "DSP_IMUX14_4", - "DSP_IMUX41_2", - "DSP_0_A9", - "DSP_WW2END0_2", - "DSP_NW2A1_4", - "DSP_LH8_3", - "DSP_1_C30", - "DSP_WW4END3_4", - "DSP_0_C21", - "DSP_WR1END2_2", - "DSP_0_PCIN21", - "DSP_IMUX36_3", - "DSP_1_ACIN2", - "DSP_1_PCIN45", - "DSP_PCOUT30", - "DSP_1_CECARRYIN", - "DSP_NW4A1_1", - "DSP_WW4B2_4", - "DSP_ACOUT18", - "DSP_1_ACIN13", - "DSP_WW2A2_3", - "DSP_IMUX29_4", - "DSP_0_PCIN14", - "DSP_LH4_1", - "DSP_0_C10", - "DSP_NE4BEG1_2", - "DSP_LOGIC_OUTS_B8_2", - "DSP_EE4A2_2", - "DSP_SW2A2_2", - "DSP_1_ACIN24", - "DSP_1_ACIN29", - "DSP_0_CARRYINSEL2", - "DSP_0_D2", - "DSP_BYP5_3", - "DSP_LH5_2", - "DSP_PCOUT32", - "DSP_SE4BEG1_4", - "DSP_0_BCIN14", - "DSP_BYP4_2", - "DSP_SE4BEG2_1", - "DSP_1_P4", - "DSP_LOGIC_OUTS_B20_3", - "DSP_WL1END2_2", - "DSP_1_PCIN42", - "DSP_LOGIC_OUTS_B12_3", - "DSP_1_C0", - "DSP_BYP5_1", - "DSP_ER1BEG3_3", - "DSP_SE2A2_0", - "DSP_1_ACOUT6", - "DSP_0_ACOUT20", - "DSP_EE4B3_2", - "DSP_CLK1_0", - "DSP_NE2A1_3", - "DSP_WW4END1_3", - "DSP_LOGIC_OUTS_B16_1", - "DSP_IMUX29_3", - "DSP_0_PCOUT23", - "DSP_0_CEAD", - "DSP_0_ACIN25", - "DSP_1_ACOUT28", - "DSP_WW2END3_2", - "DSP_1_CARRYOUT2", - "DSP_1_PCIN16", - "DSP_IMUX15_0", - "DSP_NE4BEG0_0", - "DSP_WR1END3_1", - "DSP_1_A0", - "DSP_1_PCIN7", - "DSP_EL1BEG0_4", - "DSP_LOGIC_OUTS_B19_2", - "DSP_EE2BEG2_0", - "DSP_IMUX15_1", - "DSP_1_CED", - "DSP_0_PCOUT44", - "DSP_1_BCIN4", - "DSP_NW4END0_2", - "DSP_0_C44", - "DSP_0_CARRYCASCIN", - "DSP_EE2BEG2_1", - "DSP_CARRYCASCOUT", - "DSP_PCOUT27", - "DSP_LOGIC_OUTS_B3_0", - "DSP_CLK1_1", - "DSP_NE2A3_2", - "DSP_1_PCOUT23", - "DSP_LOGIC_OUTS_B11_2", - "DSP_1_MULTSIGNOUT", - "DSP_ER1BEG1_2", - "DSP_LOGIC_OUTS_B1_4", - "DSP_LH10_1", - "DSP_IMUX34_1", - "DSP_0_PCOUT25", - "DSP_1_BCIN6", - "DSP_EE4A0_2", - "DSP_0_C29", - "DSP_IMUX13_2", - "DSP_LH1_1", - "DSP_0_A19", - "DSP_0_PCOUT43", - "DSP_0_RSTB", - "DSP_0_PCOUT15", - "DSP_BCOUT14", - "DSP_IMUX31_2", - "DSP_NE4C1_2", - "DSP_FAN3_0", - "DSP_0_P40", - "DSP_0_ACOUT11", - "DSP_1_C32", - "DSP_1_PCIN34", - "DSP_IMUX14_0", - "DSP_FAN3_3", - "DSP_0_ACIN21", - "DSP_0_PCOUT5", - "DSP_EE2BEG2_2", - "DSP_NE4BEG1_3", - "DSP_ER1BEG3_4", - "DSP_0_ACIN26", - "DSP_1_ACIN15", - "DSP_0_P37", - "DSP_FAN1_4", - "DSP_WW2END3_0", - "DSP_SW4END0_1", - "DSP_IMUX32_4", - "DSP_EE2A0_2", - "DSP_ACOUT2", - "DSP_EE4A3_4", - "DSP_0_ACOUT7", - "DSP_1_PCIN38", - "DSP_0_D12", - "DSP_ACOUT14", - "DSP_LOGIC_OUTS_B6_0", - "DSP_IMUX43_3", - "DSP_EE4A1_1", - "DSP_0_CARRYOUT0", - "DSP_WW4END2_2", - "DSP_1_PCOUT3", - "DSP_0_C24", - "DSP_1_P20", - "DSP_WR1END0_0", - "DSP_BLOCK_OUTS_B3_1", - "DSP_1_ACIN11", - "DSP_1_ALUMODE1", - "DSP_1_RSTA", - "DSP_CLK1_3", - "DSP_PCOUT15", - "DSP_EL1BEG3_4", - "DSP_0_CLK", - "DSP_1_RSTINMODE", - "DSP_LH7_1", - "DSP_1_D3", - "DSP_0_C35", - "DSP_PCOUT44", - "DSP_SE2A0_4", - "DSP_PCOUT7", - "DSP_WL1END1_3", - "DSP_NE2A3_3", - "DSP_NE4C3_2", - "DSP_1_B7", - "DSP_0_PCIN15", - "DSP_IMUX0_0", - "DSP_SE4C2_3", - "DSP_ER1BEG0_4", - "DSP_ACOUT17", - "DSP_FAN7_2", - "DSP_IMUX25_1", - "DSP_IMUX38_0", - "DSP_LOGIC_OUTS_B12_2", - "DSP_SW4A3_4", - "DSP_LOGIC_OUTS_B10_4", - "DSP_1_CEA2", - "DSP_1_P12", - "DSP_0_PCOUT1", - "DSP_LOGIC_OUTS_B6_3", - "DSP_LOGIC_OUTS_B0_3", - "DSP_1_D5", - "DSP_IMUX31_3", - "DSP_WW4A2_1", - "DSP_IMUX4_0", - "DSP_BYP7_3", - "DSP_1_C15", - "DSP_1_A5", - "DSP_IMUX42_4", - "DSP_IMUX16_0", - "DSP_BCOUT10", - "DSP_EE4C1_1", - "DSP_EL1BEG3_0", - "DSP_LH8_1", - "DSP_NW4A2_3", - "DSP_0_ACIN4", - "DSP_LH7_4", - "DSP_IMUX45_1", - "DSP_0_PCOUT36", - "DSP_ER1BEG1_4", - "DSP_ACOUT23", - "DSP_SW4END2_0", - "DSP_1_CARRYINSEL0", - "DSP_CLK0_1", - "DSP_LOGIC_OUTS_B3_3", - "DSP_WW4END0_4", - "DSP_1_PCIN32", - "DSP_1_ACIN28", - "DSP_1_P41", - "DSP_FAN7_1", - "DSP_1_MULTSIGNIN", - "DSP_0_CEC", - "DSP_EE4C1_0", - "DSP_EL1BEG0_3", - "DSP_1_C27", - "DSP_0_PCIN5", - "DSP_BYP1_1", - "DSP_1_PCOUT47", - "DSP_SE4C1_4", - "DSP_NW2A0_4", - "DSP_IMUX23_3", - "DSP_1_RSTCTRL", - "DSP_1_A28", - "DSP_WL1END2_1", - "DSP_EE4BEG0_3", - "DSP_IMUX39_2", - "DSP_0_C43", - "DSP_IMUX38_2", - "DSP_WR1END2_3", - "DSP_FAN7_0", - "DSP_NE4C2_0", - "DSP_0_CEP", - "DSP_SE4C3_0", - "DSP_0_C36", - "DSP_0_ALUMODE1", - "DSP_0_BCIN8", - "DSP_EE2BEG3_2", - "DSP_0_C22", - "DSP_EE2A1_4", - "DSP_LOGIC_OUTS_B0_0", - "DSP_0_PCOUT31", - "DSP_IMUX22_1", - "DSP_IMUX19_3", - "DSP_IMUX18_1", - "DSP_0_ACIN27", - "DSP_LOGIC_OUTS_B23_2", - "DSP_PCOUT12", - "DSP_LOGIC_OUTS_B7_1", - "DSP_1_ACOUT7", - "DSP_0_C37", - "DSP_LOGIC_OUTS_B1_2", - "DSP_1_D8", - "DSP_1_C2", - "DSP_IMUX2_3", - "DSP_CLK0_4", - "DSP_0_PCIN33", - "DSP_IMUX24_2", - "DSP_SE2A3_3", - "DSP_IMUX43_1", - "DSP_IMUX12_3", - "DSP_BLOCK_OUTS_B3_0", - "DSP_WW4B1_0", - "DSP_0_PCOUT19", - "DSP_LH12_3", - "DSP_FAN2_2", - "DSP_EE4BEG0_1", - "DSP_1_CEA1", - "DSP_0_PCOUT14", - "DSP_BLOCK_OUTS_B1_1", - "DSP_1_ACIN8", - "DSP_0_A6", - "DSP_0_PCOUT11", - "DSP_0_ACIN10", - "DSP_0_CARRYOUT2", - "DSP_0_BCOUT17", - "DSP_0_ACIN15", - "DSP_SE4BEG0_2", - "DSP_ACOUT10", - "DSP_0_CECTRL", - "DSP_1_INMODE0", - "DSP_SW4END1_3", - "DSP_LOGIC_OUTS_B23_4", - "DSP_0_CARRYINSEL0", - "DSP_NW4END1_3", - "DSP_IMUX22_4", - "DSP_NW4END0_3", - "DSP_EE4BEG1_0", - "DSP_IMUX19_2", - "DSP_LOGIC_OUTS_B21_4", - "DSP_LOGIC_OUTS_B18_4", - "DSP_0_INMODE1", - "DSP_1_ACOUT15", - "DSP_IMUX19_1", - "DSP_LOGIC_OUTS_B4_3", - "DSP_0_PCOUT29", - "DSP_LH8_2", - "DSP_1_PCOUT42", - "DSP_NE4C2_2", - "DSP_IMUX26_0", - "DSP_LH9_3", - "DSP_0_C5", - "DSP_0_ACOUT1", - "DSP_EL1BEG0_2", - "DSP_IMUX34_0", - "DSP_0_C46", - "DSP_IMUX4_1", - "DSP_WW4B3_0", - "DSP_NW4A3_3", - "DSP_EE4B2_4", - "DSP_NW4A3_0", - "DSP_NW4END2_2", - "DSP_LOGIC_OUTS_B13_3", - "DSP_1_PCOUT8", - "DSP_BYP1_3", - "DSP_LH12_4", - "DSP_LOGIC_OUTS_B8_3", - "DSP_1_P0", - "DSP_IMUX41_3", "DSP_IMUX33_1", - "DSP_IMUX45_0", - "DSP_IMUX12_4", - "DSP_0_BCIN13", - "DSP_SE2A3_0", - "DSP_1_PCOUT36", - "DSP_SE4BEG3_0", - "DSP_BLOCK_OUTS_B2_0", - "DSP_0_CEINMODE", - "DSP_EE2A0_4", - "DSP_1_ACIN27", - "DSP_1_P30", - "DSP_LH6_0", - "DSP_EE2BEG1_2", - "DSP_SW4END1_1", - "DSP_1_A26", - "DSP_BYP0_4", - "DSP_0_ACOUT21", - "DSP_BLOCK_OUTS_B0_0", - "DSP_LH10_0", - "DSP_0_PCOUT16", - "DSP_LOGIC_OUTS_B20_0", - "DSP_0_C42", - "DSP_IMUX0_4", - "DSP_BCOUT13", - "DSP_PCOUT9", - "DSP_1_PCIN8", - "DSP_1_PCOUT24", - "DSP_LOGIC_OUTS_B22_1", - "DSP_0_BCOUT13", - "DSP_0_A17", - "DSP_FAN2_1", - "DSP_IMUX33_0", - "DSP_IMUX37_0", - "DSP_1_B11", - "DSP_EL1BEG3_3", - "DSP_1_PCOUT9", - "DSP_LH3_1", - "DSP_1_A10", - "DSP_IMUX24_4", - "DSP_SE2A1_0", - "DSP_CLK0_2", - "DSP_SE2A2_4", - "DSP_ACOUT19", - "DSP_EE4BEG3_1", - "DSP_0_ACOUT12", - "DSP_0_P9", - "DSP_NW4END3_1", - "DSP_0_BCOUT16", - "DSP_IMUX33_4", - "DSP_SW4END2_4", - "DSP_SE4BEG0_0", - "DSP_1_RSTM", - "DSP_1_ACIN10", - "DSP_IMUX18_0", - "DSP_NW4END0_4", - "DSP_NW2A3_4", - "DSP_LH4_0", - "DSP_CTRL0_2", - "DSP_1_P27", - "DSP_LOGIC_OUTS_B14_2", - "DSP_IMUX32_0", - "DSP_0_BCIN10", - "DSP_WR1END2_1", - "DSP_SW2A1_3", - "DSP_WW4A2_4", - "DSP_1_A25", - "DSP_1_ACOUT9", - "DSP_1_ACIN26", - "DSP_IMUX15_3", - "DSP_IMUX12_1", - "DSP_FAN3_4", - "DSP_LOGIC_OUTS_B7_0", - "DSP_PCOUT37", - "DSP_1_ACIN3", - "DSP_ER1BEG3_1", - "DSP_LH11_1", - "DSP_NW2A2_3", - "DSP_PCOUT39", - "DSP_EE4B1_0", - "DSP_1_C29", - "DSP_IMUX43_2", - "DSP_0_P6", - "DSP_1_BCIN16", - "DSP_SW4END0_4", - "DSP_WW2END1_3", - "DSP_PCOUT19", - "DSP_NW4END2_1", - "DSP_PCOUT13", - "DSP_LOGIC_OUTS_B16_3", - "DSP_0_P3", - "DSP_IMUX47_3", - "DSP_0_D19", - "DSP_PCOUT24", - "DSP_IMUX14_3", - "DSP_1_P26", - "DSP_0_CED", - "DSP_EL1BEG2_0", - "DSP_0_P22", - "DSP_0_BCIN2", - "DSP_0_C7", - "DSP_SW4A2_1", - "DSP_1_PCOUT32", - "DSP_1_ACOUT13", - "DSP_BLOCK_OUTS_B3_3", - "DSP_IMUX44_4", - "DSP_BYP4_1", - "DSP_EE4A3_1", - "DSP_0_C32", - "DSP_1_C44", - "DSP_0_RSTP", - "DSP_1_PCIN19", - "DSP_LOGIC_OUTS_B18_1", - "DSP_ACOUT8", - "DSP_WW4A0_2", - "DSP_EE2A1_2", - "DSP_BYP2_0", - "DSP_IMUX23_1", - "DSP_1_ACIN7", - "DSP_IMUX30_2", - "DSP_NW2A0_2", - "DSP_0_BCIN7", - "DSP_LOGIC_OUTS_B10_3", - "DSP_IMUX20_3", - "DSP_IMUX25_3", - "DSP_0_ACIN12", - "DSP_LH11_4", - "DSP_1_BCIN0", - "DSP_0_P14", - "DSP_LH2_1", - "DSP_WW4END2_1", - "DSP_1_ACIN19", - "DSP_0_A13", - "DSP_IMUX46_4", - "DSP_FAN5_2", - "DSP_IMUX5_3", - "DSP_WW4B2_2", - "DSP_1_PCOUT27", - "DSP_1_PCOUT40", - "DSP_EE2BEG1_1", - "DSP_0_A29", - "DSP_ACOUT22", - "DSP_ACOUT26", - "DSP_1_C25", - "DSP_IMUX3_3", - "DSP_1_PCOUT12", - "DSP_WW2A2_4", - "DSP_0_C3", - "DSP_1_CEALUMODE", - "DSP_LH5_4", - "DSP_0_C13", - "DSP_0_B11", - "DSP_WL1END3_0", - "DSP_EL1BEG2_1", - "DSP_EE2A2_4", - "DSP_0_PCOUT33", - "DSP_1_PCIN4", - "DSP_NW2A3_2", - "DSP_1_P35", - "DSP_1_C33", - "DSP_0_A14", - "DSP_0_ACOUT22", - "DSP_BYP7_0", - "DSP_LOGIC_OUTS_B2_4", - "DSP_1_B3", - "DSP_WW4A3_4", - "DSP_SW2A1_0", - "DSP_PCOUT29", - "DSP_IMUX36_2", - "DSP_0_CECARRYIN", - "DSP_FAN4_0", - "DSP_0_D9", - "DSP_0_CEB2", - "DSP_IMUX10_3", - "DSP_PCOUT2", - "DSP_SE2A1_1", - "DSP_1_BCIN15", - "DSP_0_PCIN42", - "DSP_LOGIC_OUTS_B19_3", - "DSP_BYP5_0", - "DSP_1_PCIN27", - "DSP_0_C11", - "DSP_SE4BEG2_4", - "DSP_SW2A0_1", - "DSP_BCOUT6", - "DSP_SE2A1_4", - "DSP_NW4END1_2", - "DSP_0_PCIN6", - "DSP_1_PCIN15", + "DSP_IMUX47_0", + "DSP_1_INMODE3", + "DSP_0_OVERFLOW", + "DSP_BCOUT2", + "DSP_EE4BEG1_2", + "DSP_PCOUT4", + "DSP_1_B16", "DSP_1_C22", - "DSP_0_C30", - "DSP_WL1END3_1", - "DSP_1_PCIN33", - "DSP_LH6_2", - "DSP_NW2A0_1", - "DSP_LOGIC_OUTS_B6_2", - "DSP_1_ACOUT16", - "DSP_1_PCOUT41", - "DSP_IMUX7_3", - "DSP_EE4B2_3", - "DSP_0_D4", - "DSP_SE2A2_2", - "DSP_EE2A1_1", - "DSP_0_PCIN9", - "DSP_IMUX0_3", - "DSP_ER1BEG0_1", - "DSP_EE4C3_0", - "DSP_LOGIC_OUTS_B15_1", - "DSP_BYP4_0", - "DSP_NE4C1_4", - "DSP_0_ACIN13", - "DSP_IMUX26_1", - "DSP_PCOUT21", - "DSP_0_BCIN3", - "DSP_LOGIC_OUTS_B3_1", - "DSP_PCOUT36", - "DSP_1_A21", - "DSP_BYP7_2", - "DSP_WR1END1_4", - "DSP_NE4BEG3_0", - "DSP_1_PCIN12", - "DSP_IMUX6_2", - "DSP_0_PCOUT3", - "DSP_CTRL0_4", - "DSP_0_PCOUT20", - "DSP_WW4A1_0", - "DSP_1_CARRYOUT0", - "DSP_NE2A1_2", - "DSP_EE4B0_1", - "DSP_1_D24", - "DSP_LH4_4", - "DSP_SE4BEG3_4", - "DSP_1_ACOUT8", - "DSP_EE2BEG0_4", - "DSP_0_D14", - "DSP_SW4END3_4", - "DSP_WW4END2_3", - "DSP_1_D4", - "DSP_0_PCIN2", - "DSP_LOGIC_OUTS_B2_2", - "DSP_CTRL1_2", - "DSP_BLOCK_OUTS_B1_2", - "DSP_0_ACOUT18" + "DSP_SE4BEG1_1" ], + "tile_type": "DSP_R", "sites": [ { - "prefix": "DSP48", - "y_coord": 0, - "type": "DSP48E1", "site_pins": { - "BCOUT1": "DSP_0_BCOUT1", - "D0": "DSP_0_D0", - "B9": "DSP_0_B9", - "C5": "DSP_0_C5", - "B12": "DSP_0_B12", - "ACOUT12": "DSP_0_ACOUT12", - "C2": "DSP_0_C2", - "BCIN17": "DSP_0_BCIN17", - "CEINMODE": "DSP_0_CEINMODE", - "PCIN10": "DSP_0_PCIN10", - "D12": "DSP_0_D12", - "BCIN3": "DSP_0_BCIN3", - "BCIN5": "DSP_0_BCIN5", - "A9": "DSP_0_A9", - "CARRYCASCIN": "DSP_0_CARRYCASCIN", - "RSTCTRL": "DSP_0_RSTCTRL", - "PCIN41": "DSP_0_PCIN41", - "PCIN16": "DSP_0_PCIN16", - "ACOUT10": "DSP_0_ACOUT10", - "ACOUT0": "DSP_0_ACOUT0", - "ACIN10": "DSP_0_ACIN10", - "C25": "DSP_0_C25", - "PCOUT9": "DSP_0_PCOUT9", - "A10": "DSP_0_A10", - "PCIN3": "DSP_0_PCIN3", - "PCOUT14": "DSP_0_PCOUT14", - "BCIN16": "DSP_0_BCIN16", - "P44": "DSP_0_P44", - "P17": "DSP_0_P17", - "D5": "DSP_0_D5", - "A16": "DSP_0_A16", - "C4": "DSP_0_C4", - "D21": "DSP_0_D21", - "PCOUT43": "DSP_0_PCOUT43", - "ACOUT18": "DSP_0_ACOUT18", - "PCIN37": "DSP_0_PCIN37", - "ACIN0": "DSP_0_ACIN0", - "ACOUT23": "DSP_0_ACOUT23", - "A23": "DSP_0_A23", - "ACOUT28": "DSP_0_ACOUT28", - "RSTD": "DSP_0_RSTD", - "PCOUT36": "DSP_0_PCOUT36", - "CEA1": "DSP_0_CEA1", - "CEP": "DSP_0_CEP", - "C40": "DSP_0_C40", - "ACIN2": "DSP_0_ACIN2", - "BCIN1": "DSP_0_BCIN1", - "PCOUT17": "DSP_0_PCOUT17", - "C20": "DSP_0_C20", "P45": "DSP_0_P45", - "B4": "DSP_0_B4", - "PCIN1": "DSP_0_PCIN1", - "A20": "DSP_0_A20", - "B14": "DSP_0_B14", - "A25": "DSP_0_A25", - "BCOUT13": "DSP_0_BCOUT13", - "ACOUT27": "DSP_0_ACOUT27", - "CARRYOUT0": "DSP_0_CARRYOUT0", - "CARRYOUT2": "DSP_0_CARRYOUT2", - "PCIN0": "DSP_0_PCIN0", - "ACIN11": "DSP_0_ACIN11", - "A14": "DSP_0_A14", - "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", - "ACOUT26": "DSP_0_ACOUT26", - "PCOUT32": "DSP_0_PCOUT32", - "PCOUT40": "DSP_0_PCOUT40", - "ACIN7": "DSP_0_ACIN7", - "CEALUMODE": "DSP_0_CEALUMODE", - "C0": "DSP_0_C0", - "A7": "DSP_0_A7", - "ALUMODE1": "DSP_0_ALUMODE1", - "C8": "DSP_0_C8", - "OPMODE0": "DSP_0_OPMODE0", - "D22": "DSP_0_D22", - "A5": "DSP_0_A5", - "PCIN25": "DSP_0_PCIN25", - "CED": "DSP_0_CED", - "BCIN10": "DSP_0_BCIN10", - "P16": "DSP_0_P16", - "ACIN25": "DSP_0_ACIN25", - "ACOUT25": "DSP_0_ACOUT25", - "PCIN20": "DSP_0_PCIN20", - "CEB2": "DSP_0_CEB2", - "PCIN18": "DSP_0_PCIN18", - "PCIN17": "DSP_0_PCIN17", - "D13": "DSP_0_D13", - "PCOUT19": "DSP_0_PCOUT19", - "OPMODE6": "DSP_0_OPMODE6", - "ACOUT1": "DSP_0_ACOUT1", - "PCOUT7": "DSP_0_PCOUT7", - "P2": "DSP_0_P2", - "OPMODE3": "DSP_0_OPMODE3", - "D2": "DSP_0_D2", - "D24": "DSP_0_D24", - "C3": "DSP_0_C3", - "C32": "DSP_0_C32", - "BCOUT4": "DSP_0_BCOUT4", - "C12": "DSP_0_C12", - "BCOUT0": "DSP_0_BCOUT0", - "ACIN29": "DSP_0_ACIN29", - "A21": "DSP_0_A21", - "C28": "DSP_0_C28", - "PCIN7": "DSP_0_PCIN7", - "PCIN42": "DSP_0_PCIN42", - "BCIN9": "DSP_0_BCIN9", - "PCOUT23": "DSP_0_PCOUT23", - "PCIN36": "DSP_0_PCIN36", - "OPMODE2": "DSP_0_OPMODE2", - "D1": "DSP_0_D1", - "RSTALUMODE": "DSP_0_RSTALUMODE", - "C10": "DSP_0_C10", - "PCOUT4": "DSP_0_PCOUT4", - "C17": "DSP_0_C17", - "D18": "DSP_0_D18", - "C9": "DSP_0_C9", - "PCIN22": "DSP_0_PCIN22", - "PCOUT44": "DSP_0_PCOUT44", - "BCOUT5": "DSP_0_BCOUT5", - "B8": "DSP_0_B8", - "A15": "DSP_0_A15", - "C11": "DSP_0_C11", - "ACIN19": "DSP_0_ACIN19", - "ACOUT22": "DSP_0_ACOUT22", - "P37": "DSP_0_P37", - "D8": "DSP_0_D8", - "D17": "DSP_0_D17", - "PCOUT12": "DSP_0_PCOUT12", - "ACIN21": "DSP_0_ACIN21", - "ACIN26": "DSP_0_ACIN26", - "PCIN4": "DSP_0_PCIN4", - "B1": "DSP_0_B1", - "PCOUT46": "DSP_0_PCOUT46", - "PCIN13": "DSP_0_PCIN13", - "C21": "DSP_0_C21", - "ACIN12": "DSP_0_ACIN12", - "ACIN3": "DSP_0_ACIN3", - "A28": "DSP_0_A28", - "P13": "DSP_0_P13", - "C7": "DSP_0_C7", - "ACOUT2": "DSP_0_ACOUT2", - "PCIN27": "DSP_0_PCIN27", - "B2": "DSP_0_B2", - "PCIN11": "DSP_0_PCIN11", - "CARRYIN": "DSP_0_CARRYIN", - "P25": "DSP_0_P25", - "ACIN16": "DSP_0_ACIN16", - "PCIN14": "DSP_0_PCIN14", - "PCOUT31": "DSP_0_PCOUT31", - "PCIN6": "DSP_0_PCIN6", - "B5": "DSP_0_B5", - "PCIN28": "DSP_0_PCIN28", - "PCIN12": "DSP_0_PCIN12", - "RSTA": "DSP_0_RSTA", - "PCIN40": "DSP_0_PCIN40", - "PCOUT21": "DSP_0_PCOUT21", - "D11": "DSP_0_D11", - "B0": "DSP_0_B0", - "BCOUT3": "DSP_0_BCOUT3", - "BCIN12": "DSP_0_BCIN12", - "CEC": "DSP_0_CEC", - "PCIN45": "DSP_0_PCIN45", - "A8": "DSP_0_A8", - "C33": "DSP_0_C33", "BCIN8": "DSP_0_BCIN8", - "BCOUT11": "DSP_0_BCOUT11", - "OPMODE5": "DSP_0_OPMODE5", - "D9": "DSP_0_D9", - "P33": "DSP_0_P33", - "PCOUT0": "DSP_0_PCOUT0", - "BCIN7": "DSP_0_BCIN7", - "P7": "DSP_0_P7", - "P43": "DSP_0_P43", - "ACIN4": "DSP_0_ACIN4", - "BCOUT2": "DSP_0_BCOUT2", - "C16": "DSP_0_C16", - "PCOUT11": "DSP_0_PCOUT11", - "P4": "DSP_0_P4", - "INMODE1": "DSP_0_INMODE1", - "PCIN21": "DSP_0_PCIN21", - "C38": "DSP_0_C38", - "PCOUT27": "DSP_0_PCOUT27", - "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", - "PCOUT26": "DSP_0_PCOUT26", - "P40": "DSP_0_P40", - "BCOUT14": "DSP_0_BCOUT14", - "BCIN6": "DSP_0_BCIN6", - "D20": "DSP_0_D20", - "P31": "DSP_0_P31", - "D7": "DSP_0_D7", - "ALUMODE3": "DSP_0_ALUMODE3", - "P28": "DSP_0_P28", - "BCIN0": "DSP_0_BCIN0", - "INMODE2": "DSP_0_INMODE2", - "BCOUT17": "DSP_0_BCOUT17", - "ACIN23": "DSP_0_ACIN23", - "C23": "DSP_0_C23", - "ACOUT5": "DSP_0_ACOUT5", - "PCOUT20": "DSP_0_PCOUT20", - "ACIN6": "DSP_0_ACIN6", - "P32": "DSP_0_P32", - "PCOUT8": "DSP_0_PCOUT8", + "CECTRL": "DSP_0_CECTRL", + "PCIN6": "DSP_0_PCIN6", + "PCOUT46": "DSP_0_PCOUT46", + "ACIN22": "DSP_0_ACIN22", + "PCIN14": "DSP_0_PCIN14", + "OVERFLOW": "DSP_0_OVERFLOW", + "ACIN29": "DSP_0_ACIN29", + "A22": "DSP_0_A22", + "ACOUT24": "DSP_0_ACOUT24", "PCIN43": "DSP_0_PCIN43", - "P27": "DSP_0_P27", - "ACIN5": "DSP_0_ACIN5", - "BCOUT6": "DSP_0_BCOUT6", - "C41": "DSP_0_C41", - "D23": "DSP_0_D23", - "ACOUT14": "DSP_0_ACOUT14", - "PCIN47": "DSP_0_PCIN47", - "ACIN17": "DSP_0_ACIN17", - "CARRYOUT3": "DSP_0_CARRYOUT3", - "PCOUT41": "DSP_0_PCOUT41", - "BCOUT12": "DSP_0_BCOUT12", - "B11": "DSP_0_B11", - "PCIN33": "DSP_0_PCIN33", - "PCIN9": "DSP_0_PCIN9", - "PCIN31": "DSP_0_PCIN31", - "C42": "DSP_0_C42", - "ACIN8": "DSP_0_ACIN8", - "A19": "DSP_0_A19", - "PCOUT30": "DSP_0_PCOUT30", + "BCOUT0": "DSP_0_BCOUT0", + "A7": "DSP_0_A7", + "PCIN30": "DSP_0_PCIN30", + "A1": "DSP_0_A1", + "P9": "DSP_0_P9", + "P12": "DSP_0_P12", + "P7": "DSP_0_P7", + "BCIN15": "DSP_0_BCIN15", "PCOUT24": "DSP_0_PCOUT24", - "P41": "DSP_0_P41", - "CARRYINSEL2": "DSP_0_CARRYINSEL2", - "CARRYOUT1": "DSP_0_CARRYOUT1", - "D3": "DSP_0_D3", - "A2": "DSP_0_A2", - "ALUMODE2": "DSP_0_ALUMODE2", - "C6": "DSP_0_C6", - "P46": "DSP_0_P46", - "D14": "DSP_0_D14", - "P29": "DSP_0_P29", - "PCOUT3": "DSP_0_PCOUT3", - "A24": "DSP_0_A24", + "PCIN46": "DSP_0_PCIN46", + "P0": "DSP_0_P0", + "P18": "DSP_0_P18", + "P15": "DSP_0_P15", + "BCIN1": "DSP_0_BCIN1", + "B6": "DSP_0_B6", + "PCIN7": "DSP_0_PCIN7", + "ACIN17": "DSP_0_ACIN17", + "C18": "DSP_0_C18", + "P30": "DSP_0_P30", "C46": "DSP_0_C46", - "B10": "DSP_0_B10", - "BCIN14": "DSP_0_BCIN14", + "P36": "DSP_0_P36", + "C12": "DSP_0_C12", + "PCOUT11": "DSP_0_PCOUT11", + "C32": "DSP_0_C32", + "BCIN12": "DSP_0_BCIN12", + "B11": "DSP_0_B11", + "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", + "PCIN41": "DSP_0_PCIN41", + "P43": "DSP_0_P43", + "A27": "DSP_0_A27", + "C45": "DSP_0_C45", + "B12": "DSP_0_B12", + "ACIN3": "DSP_0_ACIN3", + "P44": "DSP_0_P44", + "PCOUT0": "DSP_0_PCOUT0", + "ACOUT9": "DSP_0_ACOUT9", + "C28": "DSP_0_C28", "ACOUT11": "DSP_0_ACOUT11", "C13": "DSP_0_C13", - "PCOUT16": "DSP_0_PCOUT16", - "BCOUT10": "DSP_0_BCOUT10", - "A22": "DSP_0_A22", - "PCOUT28": "DSP_0_PCOUT28", - "ACOUT6": "DSP_0_ACOUT6", - "BCOUT7": "DSP_0_BCOUT7", - "ACIN27": "DSP_0_ACIN27", - "ACOUT4": "DSP_0_ACOUT4", - "PCOUT39": "DSP_0_PCOUT39", - "P9": "DSP_0_P9", - "C14": "DSP_0_C14", - "PCOUT22": "DSP_0_PCOUT22", - "B13": "DSP_0_B13", - "P19": "DSP_0_P19", - "PCIN15": "DSP_0_PCIN15", - "ACOUT17": "DSP_0_ACOUT17", - "A1": "DSP_0_A1", - "B3": "DSP_0_B3", - "C24": "DSP_0_C24", - "P35": "DSP_0_P35", - "P38": "DSP_0_P38", - "INMODE0": "DSP_0_INMODE0", - "PCIN26": "DSP_0_PCIN26", - "BCOUT9": "DSP_0_BCOUT9", - "P3": "DSP_0_P3", - "ALUMODE0": "DSP_0_ALUMODE0", - "A6": "DSP_0_A6", - "A18": "DSP_0_A18", - "P34": "DSP_0_P34", - "RSTINMODE": "DSP_0_RSTINMODE", - "A0": "DSP_0_A0", - "ACIN22": "DSP_0_ACIN22", - "ACOUT13": "DSP_0_ACOUT13", - "A17": "DSP_0_A17", - "C34": "DSP_0_C34", - "P10": "DSP_0_P10", - "BCIN15": "DSP_0_BCIN15", - "PATTERNDETECT": "DSP_0_PATTERNDETECT", - "C45": "DSP_0_C45", - "PCIN19": "DSP_0_PCIN19", + "C7": "DSP_0_C7", + "BCOUT3": "DSP_0_BCOUT3", + "C40": "DSP_0_C40", + "PCIN24": "DSP_0_PCIN24", + "BCIN16": "DSP_0_BCIN16", + "B5": "DSP_0_B5", + "C15": "DSP_0_C15", + "PCIN23": "DSP_0_PCIN23", + "ACOUT18": "DSP_0_ACOUT18", "BCIN2": "DSP_0_BCIN2", - "CEAD": "DSP_0_CEAD", - "PCIN46": "DSP_0_PCIN46", - "INMODE3": "DSP_0_INMODE3", - "P24": "DSP_0_P24", - "PCIN32": "DSP_0_PCIN32", - "A12": "DSP_0_A12", - "PCOUT35": "DSP_0_PCOUT35", - "C37": "DSP_0_C37", - "P42": "DSP_0_P42", - "PCIN30": "DSP_0_PCIN30", - "P26": "DSP_0_P26", - "ACOUT3": "DSP_0_ACOUT3", - "B6": "DSP_0_B6", - "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", - "ACIN20": "DSP_0_ACIN20", + "C14": "DSP_0_C14", + "C9": "DSP_0_C9", + "D0": "DSP_0_D0", + "A4": "DSP_0_A4", + "ACOUT23": "DSP_0_ACOUT23", + "PCIN33": "DSP_0_PCIN33", + "ACOUT16": "DSP_0_ACOUT16", + "PCIN25": "DSP_0_PCIN25", + "B0": "DSP_0_B0", "CEB1": "DSP_0_CEB1", - "P0": "DSP_0_P0", + "RSTB": "DSP_0_RSTB", + "P16": "DSP_0_P16", + "PCIN18": "DSP_0_PCIN18", + "RSTM": "DSP_0_RSTM", + "PCOUT3": "DSP_0_PCOUT3", + "PCIN40": "DSP_0_PCIN40", + "CARRYOUT2": "DSP_0_CARRYOUT2", + "ALUMODE3": "DSP_0_ALUMODE3", + "C5": "DSP_0_C5", + "BCIN9": "DSP_0_BCIN9", + "D20": "DSP_0_D20", + "BCIN17": "DSP_0_BCIN17", + "C38": "DSP_0_C38", + "A6": "DSP_0_A6", + "A13": "DSP_0_A13", + "CARRYOUT1": "DSP_0_CARRYOUT1", + "P32": "DSP_0_P32", + "C19": "DSP_0_C19", + "C11": "DSP_0_C11", "PCOUT5": "DSP_0_PCOUT5", "PCOUT25": "DSP_0_PCOUT25", - "PCIN23": "DSP_0_PCIN23", - "A3": "DSP_0_A3", - "PCOUT18": "DSP_0_PCOUT18", - "BCOUT8": "DSP_0_BCOUT8", - "P11": "DSP_0_P11", - "ACIN18": "DSP_0_ACIN18", - "B16": "DSP_0_B16", - "MULTSIGNIN": "DSP_0_MULTSIGNIN", - "ACOUT21": "DSP_0_ACOUT21", - "PCIN38": "DSP_0_PCIN38", - "C30": "DSP_0_C30", - "CARRYINSEL0": "DSP_0_CARRYINSEL0", - "C29": "DSP_0_C29", - "C19": "DSP_0_C19", - "ACOUT8": "DSP_0_ACOUT8", - "ACIN13": "DSP_0_ACIN13", - "PCOUT38": "DSP_0_PCOUT38", - "OPMODE1": "DSP_0_OPMODE1", - "PCOUT45": "DSP_0_PCOUT45", - "ACIN24": "DSP_0_ACIN24", - "OPMODE4": "DSP_0_OPMODE4", - "PCIN5": "DSP_0_PCIN5", - "PCOUT6": "DSP_0_PCOUT6", - "D16": "DSP_0_D16", - "ACOUT15": "DSP_0_ACOUT15", - "P12": "DSP_0_P12", - "ACOUT29": "DSP_0_ACOUT29", - "INMODE4": "DSP_0_INMODE4", - "C15": "DSP_0_C15", - "PCIN44": "DSP_0_PCIN44", - "P36": "DSP_0_P36", - "PCOUT2": "DSP_0_PCOUT2", - "C27": "DSP_0_C27", - "P1": "DSP_0_P1", - "CARRYINSEL1": "DSP_0_CARRYINSEL1", - "P8": "DSP_0_P8", - "PCOUT47": "DSP_0_PCOUT47", - "RSTALLCARRYIN": "DSP_0_RSTALLCARRYIN", - "P18": "DSP_0_P18", - "PCOUT10": "DSP_0_PCOUT10", - "ACIN1": "DSP_0_ACIN1", - "C1": "DSP_0_C1", - "PCIN24": "DSP_0_PCIN24", - "RSTB": "DSP_0_RSTB", - "PCIN29": "DSP_0_PCIN29", - "P30": "DSP_0_P30", - "BCOUT15": "DSP_0_BCOUT15", - "P22": "DSP_0_P22", "BCIN13": "DSP_0_BCIN13", - "PCOUT34": "DSP_0_PCOUT34", - "BCIN11": "DSP_0_BCIN11", - "C18": "DSP_0_C18", - "A11": "DSP_0_A11", - "C43": "DSP_0_C43", - "C35": "DSP_0_C35", - "C47": "DSP_0_C47", - "PCIN34": "DSP_0_PCIN34", + "P38": "DSP_0_P38", + "ACOUT10": "DSP_0_ACOUT10", + "PCIN38": "DSP_0_PCIN38", + "C2": "DSP_0_C2", + "CEB2": "DSP_0_CEB2", "ACIN14": "DSP_0_ACIN14", - "PCIN8": "DSP_0_PCIN8", - "CEA2": "DSP_0_CEA2", - "A4": "DSP_0_A4", - "ACIN28": "DSP_0_ACIN28", - "A13": "DSP_0_A13", - "PCOUT42": "DSP_0_PCOUT42", - "PCOUT15": "DSP_0_PCOUT15", - "D10": "DSP_0_D10", - "CECTRL": "DSP_0_CECTRL", - "P6": "DSP_0_P6", - "ACOUT16": "DSP_0_ACOUT16", - "CEM": "DSP_0_CEM", - "A27": "DSP_0_A27", - "ACIN15": "DSP_0_ACIN15", - "D15": "DSP_0_D15", - "P23": "DSP_0_P23", - "UNDERFLOW": "DSP_0_UNDERFLOW", - "OVERFLOW": "DSP_0_OVERFLOW", - "RSTP": "DSP_0_RSTP", - "P39": "DSP_0_P39", - "CLK": "DSP_0_CLK", - "A29": "DSP_0_A29", - "P15": "DSP_0_P15", - "ACOUT24": "DSP_0_ACOUT24", - "ACOUT9": "DSP_0_ACOUT9", - "CECARRYIN": "DSP_0_CECARRYIN", + "ALUMODE1": "DSP_0_ALUMODE1", "P47": "DSP_0_P47", - "B7": "DSP_0_B7", - "BCOUT16": "DSP_0_BCOUT16", - "PCOUT13": "DSP_0_PCOUT13", - "ACIN9": "DSP_0_ACIN9", - "P14": "DSP_0_P14", - "ACOUT7": "DSP_0_ACOUT7", - "D4": "DSP_0_D4", - "C22": "DSP_0_C22", - "A26": "DSP_0_A26", - "P21": "DSP_0_P21", - "D6": "DSP_0_D6", - "D19": "DSP_0_D19", - "B17": "DSP_0_B17", - "P20": "DSP_0_P20", - "PCIN35": "DSP_0_PCIN35", - "PCIN39": "DSP_0_PCIN39", - "RSTC": "DSP_0_RSTC", - "B15": "DSP_0_B15", - "ACOUT19": "DSP_0_ACOUT19", - "PCOUT37": "DSP_0_PCOUT37", - "ACOUT20": "DSP_0_ACOUT20", + "PCOUT10": "DSP_0_PCOUT10", + "PCIN19": "DSP_0_PCIN19", + "P27": "DSP_0_P27", + "PCOUT39": "DSP_0_PCOUT39", + "P19": "DSP_0_P19", + "D12": "DSP_0_D12", + "ACOUT25": "DSP_0_ACOUT25", + "CEM": "DSP_0_CEM", + "P6": "DSP_0_P6", + "A25": "DSP_0_A25", + "BCIN6": "DSP_0_BCIN6", + "C47": "DSP_0_C47", + "PCIN2": "DSP_0_PCIN2", + "BCIN14": "DSP_0_BCIN14", + "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", + "D16": "DSP_0_D16", + "P2": "DSP_0_P2", + "ACOUT3": "DSP_0_ACOUT3", + "A11": "DSP_0_A11", + "PCIN8": "DSP_0_PCIN8", + "PCIN13": "DSP_0_PCIN13", + "P40": "DSP_0_P40", + "OPMODE3": "DSP_0_OPMODE3", + "BCOUT11": "DSP_0_BCOUT11", + "C4": "DSP_0_C4", + "PCIN4": "DSP_0_PCIN4", + "PCIN28": "DSP_0_PCIN28", + "ACOUT4": "DSP_0_ACOUT4", + "PCOUT2": "DSP_0_PCOUT2", + "BCIN0": "DSP_0_BCIN0", + "ACOUT26": "DSP_0_ACOUT26", + "ACOUT13": "DSP_0_ACOUT13", + "PCIN10": "DSP_0_PCIN10", + "PCOUT6": "DSP_0_PCOUT6", + "C43": "DSP_0_C43", + "A2": "DSP_0_A2", + "ACIN26": "DSP_0_ACIN26", + "CECARRYIN": "DSP_0_CECARRYIN", + "ACOUT15": "DSP_0_ACOUT15", + "PCOUT28": "DSP_0_PCOUT28", + "B2": "DSP_0_B2", + "ACIN1": "DSP_0_ACIN1", + "P23": "DSP_0_P23", + "PCIN0": "DSP_0_PCIN0", + "PCIN47": "DSP_0_PCIN47", + "BCOUT17": "DSP_0_BCOUT17", + "PCOUT42": "DSP_0_PCOUT42", + "D22": "DSP_0_D22", + "CED": "DSP_0_CED", + "ACIN23": "DSP_0_ACIN23", + "ACIN2": "DSP_0_ACIN2", + "A17": "DSP_0_A17", + "PCOUT20": "DSP_0_PCOUT20", + "BCIN7": "DSP_0_BCIN7", + "D14": "DSP_0_D14", + "P8": "DSP_0_P8", + "ALUMODE2": "DSP_0_ALUMODE2", + "D17": "DSP_0_D17", + "ACIN10": "DSP_0_ACIN10", + "OPMODE4": "DSP_0_OPMODE4", "C26": "DSP_0_C26", - "RSTM": "DSP_0_RSTM", - "PCOUT1": "DSP_0_PCOUT1", + "ACIN16": "DSP_0_ACIN16", + "PCIN5": "DSP_0_PCIN5", "C44": "DSP_0_C44", + "ACIN5": "DSP_0_ACIN5", + "PCIN37": "DSP_0_PCIN37", + "PCIN15": "DSP_0_PCIN15", + "PCOUT44": "DSP_0_PCOUT44", + "C22": "DSP_0_C22", + "A0": "DSP_0_A0", + "INMODE4": "DSP_0_INMODE4", + "B3": "DSP_0_B3", + "C0": "DSP_0_C0", + "P29": "DSP_0_P29", + "ACOUT21": "DSP_0_ACOUT21", + "PCIN1": "DSP_0_PCIN1", + "B15": "DSP_0_B15", + "PCIN39": "DSP_0_PCIN39", + "OPMODE1": "DSP_0_OPMODE1", + "ACIN12": "DSP_0_ACIN12", + "ACIN27": "DSP_0_ACIN27", + "PCOUT41": "DSP_0_PCOUT41", + "ACOUT2": "DSP_0_ACOUT2", + "ACIN8": "DSP_0_ACIN8", + "B13": "DSP_0_B13", + "A28": "DSP_0_A28", + "PCOUT8": "DSP_0_PCOUT8", + "P11": "DSP_0_P11", "P5": "DSP_0_P5", - "PCOUT33": "DSP_0_PCOUT33", + "CARRYOUT0": "DSP_0_CARRYOUT0", + "D7": "DSP_0_D7", + "CEC": "DSP_0_CEC", + "ACOUT12": "DSP_0_ACOUT12", + "A29": "DSP_0_A29", + "B1": "DSP_0_B1", + "C17": "DSP_0_C17", + "B4": "DSP_0_B4", + "C27": "DSP_0_C27", + "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", + "P28": "DSP_0_P28", + "A24": "DSP_0_A24", + "RSTINMODE": "DSP_0_RSTINMODE", + "P20": "DSP_0_P20", + "CEALUMODE": "DSP_0_CEALUMODE", + "ACOUT20": "DSP_0_ACOUT20", + "P14": "DSP_0_P14", + "C33": "DSP_0_C33", + "P34": "DSP_0_P34", + "C1": "DSP_0_C1", + "BCOUT13": "DSP_0_BCOUT13", + "PCIN42": "DSP_0_PCIN42", + "P39": "DSP_0_P39", + "B7": "DSP_0_B7", + "B10": "DSP_0_B10", + "PCIN16": "DSP_0_PCIN16", + "CARRYINSEL0": "DSP_0_CARRYINSEL0", + "PCOUT26": "DSP_0_PCOUT26", + "C6": "DSP_0_C6", + "CEA2": "DSP_0_CEA2", + "ACOUT5": "DSP_0_ACOUT5", + "PCOUT18": "DSP_0_PCOUT18", + "BCIN10": "DSP_0_BCIN10", + "PCOUT32": "DSP_0_PCOUT32", + "PCIN20": "DSP_0_PCIN20", + "OPMODE5": "DSP_0_OPMODE5", + "A26": "DSP_0_A26", + "PCOUT14": "DSP_0_PCOUT14", + "P13": "DSP_0_P13", + "BCOUT5": "DSP_0_BCOUT5", + "CEAD": "DSP_0_CEAD", + "MULTSIGNIN": "DSP_0_MULTSIGNIN", + "ACOUT14": "DSP_0_ACOUT14", + "D1": "DSP_0_D1", + "OPMODE2": "DSP_0_OPMODE2", + "A12": "DSP_0_A12", + "C41": "DSP_0_C41", + "C10": "DSP_0_C10", + "PCOUT9": "DSP_0_PCOUT9", + "D24": "DSP_0_D24", + "PCIN27": "DSP_0_PCIN27", + "ACOUT1": "DSP_0_ACOUT1", + "ACOUT29": "DSP_0_ACOUT29", + "ACIN25": "DSP_0_ACIN25", + "A3": "DSP_0_A3", + "B9": "DSP_0_B9", + "A21": "DSP_0_A21", + "PCOUT17": "DSP_0_PCOUT17", + "PCOUT34": "DSP_0_PCOUT34", + "PCOUT35": "DSP_0_PCOUT35", + "ACOUT27": "DSP_0_ACOUT27", + "D13": "DSP_0_D13", + "A15": "DSP_0_A15", + "P24": "DSP_0_P24", + "D5": "DSP_0_D5", + "BCOUT2": "DSP_0_BCOUT2", + "CARRYIN": "DSP_0_CARRYIN", + "C37": "DSP_0_C37", + "ACOUT22": "DSP_0_ACOUT22", "C36": "DSP_0_C36", + "ACOUT17": "DSP_0_ACOUT17", + "P1": "DSP_0_P1", + "PCOUT45": "DSP_0_PCOUT45", + "PCIN45": "DSP_0_PCIN45", + "P10": "DSP_0_P10", + "P33": "DSP_0_P33", + "B17": "DSP_0_B17", + "C16": "DSP_0_C16", + "A23": "DSP_0_A23", + "PCIN32": "DSP_0_PCIN32", + "PCOUT40": "DSP_0_PCOUT40", + "A5": "DSP_0_A5", + "INMODE2": "DSP_0_INMODE2", + "RSTA": "DSP_0_RSTA", + "A14": "DSP_0_A14", + "BCOUT7": "DSP_0_BCOUT7", + "ACIN0": "DSP_0_ACIN0", + "PCIN31": "DSP_0_PCIN31", + "PCIN22": "DSP_0_PCIN22", + "PCOUT13": "DSP_0_PCOUT13", + "PCOUT15": "DSP_0_PCOUT15", + "P17": "DSP_0_P17", + "ACIN4": "DSP_0_ACIN4", + "PCIN11": "DSP_0_PCIN11", + "A20": "DSP_0_A20", + "ACIN11": "DSP_0_ACIN11", + "BCOUT9": "DSP_0_BCOUT9", + "OPMODE0": "DSP_0_OPMODE0", + "PCIN12": "DSP_0_PCIN12", + "RSTD": "DSP_0_RSTD", + "A10": "DSP_0_A10", + "ACOUT19": "DSP_0_ACOUT19", + "C25": "DSP_0_C25", + "ACIN28": "DSP_0_ACIN28", + "D6": "DSP_0_D6", + "ACOUT0": "DSP_0_ACOUT0", + "BCOUT1": "DSP_0_BCOUT1", + "P46": "DSP_0_P46", + "P4": "DSP_0_P4", + "C35": "DSP_0_C35", + "D10": "DSP_0_D10", + "C42": "DSP_0_C42", + "P42": "DSP_0_P42", + "PCIN44": "DSP_0_PCIN44", + "PCOUT43": "DSP_0_PCOUT43", + "CEP": "DSP_0_CEP", + "C23": "DSP_0_C23", + "A8": "DSP_0_A8", + "A18": "DSP_0_A18", + "CARRYINSEL2": "DSP_0_CARRYINSEL2", + "ACOUT28": "DSP_0_ACOUT28", + "C29": "DSP_0_C29", + "BCOUT12": "DSP_0_BCOUT12", + "P35": "DSP_0_P35", + "ACOUT8": "DSP_0_ACOUT8", + "RSTP": "DSP_0_RSTP", + "ACIN24": "DSP_0_ACIN24", + "PCIN9": "DSP_0_PCIN9", + "ACIN6": "DSP_0_ACIN6", + "BCOUT14": "DSP_0_BCOUT14", + "P41": "DSP_0_P41", + "BCOUT16": "DSP_0_BCOUT16", + "RSTALUMODE": "DSP_0_RSTALUMODE", + "C8": "DSP_0_C8", + "PCOUT23": "DSP_0_PCOUT23", + "BCOUT8": "DSP_0_BCOUT8", + "C24": "DSP_0_C24", + "C30": "DSP_0_C30", + "ACIN21": "DSP_0_ACIN21", + "ACIN13": "DSP_0_ACIN13", + "PCOUT33": "DSP_0_PCOUT33", + "ACIN19": "DSP_0_ACIN19", + "D21": "DSP_0_D21", + "ACIN20": "DSP_0_ACIN20", + "D23": "DSP_0_D23", + "A19": "DSP_0_A19", + "B16": "DSP_0_B16", + "PCOUT4": "DSP_0_PCOUT4", + "PCOUT27": "DSP_0_PCOUT27", + "PCIN29": "DSP_0_PCIN29", + "CLK": "DSP_0_CLK", + "PCOUT19": "DSP_0_PCOUT19", + "PCOUT47": "DSP_0_PCOUT47", + "PCIN34": "DSP_0_PCIN34", + "D2": "DSP_0_D2", + "P25": "DSP_0_P25", + "ACIN9": "DSP_0_ACIN9", + "BCOUT6": "DSP_0_BCOUT6", + "PCIN21": "DSP_0_PCIN21", + "C3": "DSP_0_C3", + "PCOUT7": "DSP_0_PCOUT7", + "PCOUT31": "DSP_0_PCOUT31", + "PCOUT12": "DSP_0_PCOUT12", + "BCOUT4": "DSP_0_BCOUT4", + "B8": "DSP_0_B8", + "C34": "DSP_0_C34", + "BCIN3": "DSP_0_BCIN3", + "INMODE1": "DSP_0_INMODE1", + "PCIN26": "DSP_0_PCIN26", + "CARRYOUT3": "DSP_0_CARRYOUT3", + "D11": "DSP_0_D11", + "INMODE3": "DSP_0_INMODE3", + "BCOUT15": "DSP_0_BCOUT15", + "D3": "DSP_0_D3", + "P37": "DSP_0_P37", + "PCOUT16": "DSP_0_PCOUT16", + "D8": "DSP_0_D8", + "ACIN18": "DSP_0_ACIN18", + "C21": "DSP_0_C21", + "PCOUT36": "DSP_0_PCOUT36", + "BCIN11": "DSP_0_BCIN11", + "CARRYINSEL1": "DSP_0_CARRYINSEL1", + "D9": "DSP_0_D9", + "C20": "DSP_0_C20", + "ACOUT7": "DSP_0_ACOUT7", + "P26": "DSP_0_P26", + "RSTCTRL": "DSP_0_RSTCTRL", + "RSTC": "DSP_0_RSTC", + "D19": "DSP_0_D19", + "D18": "DSP_0_D18", + "ACIN7": "DSP_0_ACIN7", + "PCIN17": "DSP_0_PCIN17", + "D15": "DSP_0_D15", + "PCOUT1": "DSP_0_PCOUT1", + "RSTALLCARRYIN": "DSP_0_RSTALLCARRYIN", + "PCOUT21": "DSP_0_PCOUT21", + "A9": "DSP_0_A9", + "ALUMODE0": "DSP_0_ALUMODE0", + "BCOUT10": "DSP_0_BCOUT10", + "UNDERFLOW": "DSP_0_UNDERFLOW", + "PCIN35": "DSP_0_PCIN35", + "ACOUT6": "DSP_0_ACOUT6", "C31": "DSP_0_C31", "PCOUT29": "DSP_0_PCOUT29", - "C39": "DSP_0_C39", + "P31": "DSP_0_P31", + "INMODE0": "DSP_0_INMODE0", + "PCOUT22": "DSP_0_PCOUT22", + "PCOUT30": "DSP_0_PCOUT30", "BCIN4": "DSP_0_BCIN4", - "PCIN2": "DSP_0_PCIN2" + "D4": "DSP_0_D4", + "ACIN15": "DSP_0_ACIN15", + "PCIN36": "DSP_0_PCIN36", + "P3": "DSP_0_P3", + "PCIN3": "DSP_0_PCIN3", + "PCOUT37": "DSP_0_PCOUT37", + "OPMODE6": "DSP_0_OPMODE6", + "B14": "DSP_0_B14", + "C39": "DSP_0_C39", + "P22": "DSP_0_P22", + "CEA1": "DSP_0_CEA1", + "PATTERNDETECT": "DSP_0_PATTERNDETECT", + "A16": "DSP_0_A16", + "CARRYCASCIN": "DSP_0_CARRYCASCIN", + "CEINMODE": "DSP_0_CEINMODE", + "P21": "DSP_0_P21", + "BCIN5": "DSP_0_BCIN5", + "PCOUT38": "DSP_0_PCOUT38" }, + "type": "DSP48E1", + "prefix": "DSP48", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 }, { - "prefix": "DSP48", - "y_coord": 1, - "type": "DSP48E1", "site_pins": { - "BCOUT1": "DSP_1_BCOUT1", - "D0": "DSP_1_D0", - "B9": "DSP_1_B9", - "C5": "DSP_1_C5", - "B12": "DSP_1_B12", - "ACOUT12": "DSP_1_ACOUT12", - "C2": "DSP_1_C2", - "BCIN17": "DSP_1_BCIN17", - "CEINMODE": "DSP_1_CEINMODE", - "PCIN10": "DSP_1_PCIN10", - "D12": "DSP_1_D12", - "BCIN3": "DSP_1_BCIN3", - "BCIN5": "DSP_1_BCIN5", - "A9": "DSP_1_A9", - "CARRYCASCIN": "DSP_1_CARRYCASCIN", - "RSTCTRL": "DSP_1_RSTCTRL", - "PCIN41": "DSP_1_PCIN41", - "PCIN16": "DSP_1_PCIN16", - "ACOUT10": "DSP_1_ACOUT10", - "ACOUT0": "DSP_1_ACOUT0", - "ACIN10": "DSP_1_ACIN10", - "C25": "DSP_1_C25", - "PCOUT9": "DSP_1_PCOUT9", - "A10": "DSP_1_A10", - "PCIN3": "DSP_1_PCIN3", - "PCOUT14": "DSP_1_PCOUT14", - "BCIN16": "DSP_1_BCIN16", - "P44": "DSP_1_P44", - "P17": "DSP_1_P17", - "D5": "DSP_1_D5", - "A16": "DSP_1_A16", - "C4": "DSP_1_C4", - "D21": "DSP_1_D21", - "PCOUT43": "DSP_1_PCOUT43", - "ACOUT18": "DSP_1_ACOUT18", - "PCIN37": "DSP_1_PCIN37", - "ACIN0": "DSP_1_ACIN0", - "ACOUT23": "DSP_1_ACOUT23", - "A23": "DSP_1_A23", - "ACOUT28": "DSP_1_ACOUT28", - "RSTD": "DSP_1_RSTD", - "PCOUT36": "DSP_1_PCOUT36", - "CEA1": "DSP_1_CEA1", - "CEP": "DSP_1_CEP", - "C40": "DSP_1_C40", - "ACIN2": "DSP_1_ACIN2", - "BCIN1": "DSP_1_BCIN1", - "PCOUT17": "DSP_1_PCOUT17", - "C20": "DSP_1_C20", "P45": "DSP_1_P45", - "B4": "DSP_1_B4", - "PCIN1": "DSP_1_PCIN1", - "A20": "DSP_1_A20", - "B14": "DSP_1_B14", - "A25": "DSP_1_A25", - "BCOUT13": "DSP_1_BCOUT13", - "ACOUT27": "DSP_1_ACOUT27", - "CARRYOUT0": "DSP_1_CARRYOUT0", - "CARRYOUT2": "DSP_1_CARRYOUT2", - "PCIN0": "DSP_1_PCIN0", - "ACIN11": "DSP_1_ACIN11", - "A14": "DSP_1_A14", - "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", - "ACOUT26": "DSP_1_ACOUT26", - "PCOUT32": "DSP_1_PCOUT32", - "PCOUT40": "DSP_1_PCOUT40", - "ACIN7": "DSP_1_ACIN7", - "CEALUMODE": "DSP_1_CEALUMODE", - "C0": "DSP_1_C0", - "A7": "DSP_1_A7", - "ALUMODE1": "DSP_1_ALUMODE1", - "C8": "DSP_1_C8", - "OPMODE0": "DSP_1_OPMODE0", - "D22": "DSP_1_D22", - "A5": "DSP_1_A5", - "PCIN25": "DSP_1_PCIN25", - "CED": "DSP_1_CED", - "BCIN10": "DSP_1_BCIN10", - "P16": "DSP_1_P16", - "ACIN25": "DSP_1_ACIN25", - "ACOUT25": "DSP_1_ACOUT25", - "PCIN20": "DSP_1_PCIN20", - "CEB2": "DSP_1_CEB2", - "PCIN18": "DSP_1_PCIN18", - "PCIN17": "DSP_1_PCIN17", - "D13": "DSP_1_D13", - "PCOUT19": "DSP_1_PCOUT19", - "OPMODE6": "DSP_1_OPMODE6", - "ACOUT1": "DSP_1_ACOUT1", - "PCOUT7": "DSP_1_PCOUT7", - "P2": "DSP_1_P2", - "OPMODE3": "DSP_1_OPMODE3", - "D2": "DSP_1_D2", - "D24": "DSP_1_D24", - "C3": "DSP_1_C3", - "C32": "DSP_1_C32", - "BCOUT4": "DSP_1_BCOUT4", - "C12": "DSP_1_C12", - "BCOUT0": "DSP_1_BCOUT0", - "ACIN29": "DSP_1_ACIN29", - "A21": "DSP_1_A21", - "C28": "DSP_1_C28", - "PCIN7": "DSP_1_PCIN7", - "PCIN42": "DSP_1_PCIN42", - "BCIN9": "DSP_1_BCIN9", - "PCOUT23": "DSP_1_PCOUT23", - "PCIN36": "DSP_1_PCIN36", - "OPMODE2": "DSP_1_OPMODE2", - "D1": "DSP_1_D1", - "RSTALUMODE": "DSP_1_RSTALUMODE", - "C10": "DSP_1_C10", - "PCOUT4": "DSP_1_PCOUT4", - "C17": "DSP_1_C17", - "D18": "DSP_1_D18", - "C9": "DSP_1_C9", - "PCIN22": "DSP_1_PCIN22", - "PCOUT44": "DSP_1_PCOUT44", - "BCOUT5": "DSP_1_BCOUT5", - "B8": "DSP_1_B8", - "A15": "DSP_1_A15", - "C11": "DSP_1_C11", - "ACIN19": "DSP_1_ACIN19", - "ACOUT22": "DSP_1_ACOUT22", - "P37": "DSP_1_P37", - "D8": "DSP_1_D8", - "D17": "DSP_1_D17", - "PCOUT12": "DSP_1_PCOUT12", - "ACIN21": "DSP_1_ACIN21", - "ACIN26": "DSP_1_ACIN26", - "PCIN4": "DSP_1_PCIN4", - "B1": "DSP_1_B1", - "PCOUT46": "DSP_1_PCOUT46", - "PCIN13": "DSP_1_PCIN13", - "C21": "DSP_1_C21", - "ACIN12": "DSP_1_ACIN12", - "ACIN3": "DSP_1_ACIN3", - "A28": "DSP_1_A28", - "P13": "DSP_1_P13", - "C7": "DSP_1_C7", - "ACOUT2": "DSP_1_ACOUT2", - "PCIN27": "DSP_1_PCIN27", - "B2": "DSP_1_B2", - "PCIN11": "DSP_1_PCIN11", - "CARRYIN": "DSP_1_CARRYIN", - "P25": "DSP_1_P25", - "ACIN16": "DSP_1_ACIN16", - "PCIN14": "DSP_1_PCIN14", - "PCOUT31": "DSP_1_PCOUT31", - "PCIN6": "DSP_1_PCIN6", - "B5": "DSP_1_B5", - "PCIN28": "DSP_1_PCIN28", - "PCIN12": "DSP_1_PCIN12", - "RSTA": "DSP_1_RSTA", - "PCIN40": "DSP_1_PCIN40", - "PCOUT21": "DSP_1_PCOUT21", - "D11": "DSP_1_D11", - "B0": "DSP_1_B0", - "BCOUT3": "DSP_1_BCOUT3", - "BCIN12": "DSP_1_BCIN12", - "CEC": "DSP_1_CEC", - "PCIN45": "DSP_1_PCIN45", - "A8": "DSP_1_A8", - "C33": "DSP_1_C33", "BCIN8": "DSP_1_BCIN8", - "BCOUT11": "DSP_1_BCOUT11", - "OPMODE5": "DSP_1_OPMODE5", - "D9": "DSP_1_D9", - "P33": "DSP_1_P33", - "PCOUT0": "DSP_1_PCOUT0", - "BCIN7": "DSP_1_BCIN7", - "P7": "DSP_1_P7", - "P43": "DSP_1_P43", - "ACIN4": "DSP_1_ACIN4", - "BCOUT2": "DSP_1_BCOUT2", - "C16": "DSP_1_C16", - "PCOUT11": "DSP_1_PCOUT11", - "P4": "DSP_1_P4", - "INMODE1": "DSP_1_INMODE1", - "PCIN21": "DSP_1_PCIN21", - "C38": "DSP_1_C38", - "PCOUT27": "DSP_1_PCOUT27", - "CARRYCASCOUT": "DSP_1_CARRYCASCOUT", - "PCOUT26": "DSP_1_PCOUT26", - "P40": "DSP_1_P40", - "BCOUT14": "DSP_1_BCOUT14", - "BCIN6": "DSP_1_BCIN6", - "D20": "DSP_1_D20", - "P31": "DSP_1_P31", - "D7": "DSP_1_D7", - "ALUMODE3": "DSP_1_ALUMODE3", - "P28": "DSP_1_P28", - "BCIN0": "DSP_1_BCIN0", - "INMODE2": "DSP_1_INMODE2", - "BCOUT17": "DSP_1_BCOUT17", - "ACIN23": "DSP_1_ACIN23", - "C23": "DSP_1_C23", - "ACOUT5": "DSP_1_ACOUT5", - "PCOUT20": "DSP_1_PCOUT20", - "ACIN6": "DSP_1_ACIN6", - "P32": "DSP_1_P32", - "PCOUT8": "DSP_1_PCOUT8", + "CECTRL": "DSP_1_CECTRL", + "PCIN6": "DSP_1_PCIN6", + "PCOUT46": "DSP_1_PCOUT46", + "ACIN22": "DSP_1_ACIN22", + "PCIN14": "DSP_1_PCIN14", + "OVERFLOW": "DSP_1_OVERFLOW", + "ACIN29": "DSP_1_ACIN29", + "A22": "DSP_1_A22", + "ACOUT24": "DSP_1_ACOUT24", "PCIN43": "DSP_1_PCIN43", - "P27": "DSP_1_P27", - "ACIN5": "DSP_1_ACIN5", - "BCOUT6": "DSP_1_BCOUT6", - "C41": "DSP_1_C41", - "D23": "DSP_1_D23", - "ACOUT14": "DSP_1_ACOUT14", - "PCIN47": "DSP_1_PCIN47", - "ACIN17": "DSP_1_ACIN17", - "CARRYOUT3": "DSP_1_CARRYOUT3", - "PCOUT41": "DSP_1_PCOUT41", - "BCOUT12": "DSP_1_BCOUT12", - "B11": "DSP_1_B11", - "PCIN33": "DSP_1_PCIN33", - "PCIN9": "DSP_1_PCIN9", - "PCIN31": "DSP_1_PCIN31", - "C42": "DSP_1_C42", - "ACIN8": "DSP_1_ACIN8", - "A19": "DSP_1_A19", - "PCOUT30": "DSP_1_PCOUT30", + "BCOUT0": "DSP_1_BCOUT0", + "A7": "DSP_1_A7", + "PCIN30": "DSP_1_PCIN30", + "A1": "DSP_1_A1", + "P9": "DSP_1_P9", + "P12": "DSP_1_P12", + "P7": "DSP_1_P7", + "BCIN15": "DSP_1_BCIN15", "PCOUT24": "DSP_1_PCOUT24", - "P41": "DSP_1_P41", - "CARRYINSEL2": "DSP_1_CARRYINSEL2", - "CARRYOUT1": "DSP_1_CARRYOUT1", - "D3": "DSP_1_D3", - "A2": "DSP_1_A2", - "ALUMODE2": "DSP_1_ALUMODE2", - "C6": "DSP_1_C6", - "P46": "DSP_1_P46", - "D14": "DSP_1_D14", - "P29": "DSP_1_P29", - "PCOUT3": "DSP_1_PCOUT3", - "A24": "DSP_1_A24", + "PCIN46": "DSP_1_PCIN46", + "P0": "DSP_1_P0", + "P18": "DSP_1_P18", + "P15": "DSP_1_P15", + "BCIN1": "DSP_1_BCIN1", + "B6": "DSP_1_B6", + "PCIN7": "DSP_1_PCIN7", + "ACIN17": "DSP_1_ACIN17", + "C18": "DSP_1_C18", + "P30": "DSP_1_P30", "C46": "DSP_1_C46", - "B10": "DSP_1_B10", - "BCIN14": "DSP_1_BCIN14", + "P36": "DSP_1_P36", + "C12": "DSP_1_C12", + "PCOUT11": "DSP_1_PCOUT11", + "C32": "DSP_1_C32", + "BCIN12": "DSP_1_BCIN12", + "B11": "DSP_1_B11", + "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", + "PCIN41": "DSP_1_PCIN41", + "P43": "DSP_1_P43", + "A27": "DSP_1_A27", + "C45": "DSP_1_C45", + "B12": "DSP_1_B12", + "ACIN3": "DSP_1_ACIN3", + "P44": "DSP_1_P44", + "PCOUT0": "DSP_1_PCOUT0", + "ACOUT9": "DSP_1_ACOUT9", + "C28": "DSP_1_C28", "ACOUT11": "DSP_1_ACOUT11", "C13": "DSP_1_C13", - "PCOUT16": "DSP_1_PCOUT16", - "BCOUT10": "DSP_1_BCOUT10", - "A22": "DSP_1_A22", - "PCOUT28": "DSP_1_PCOUT28", - "ACOUT6": "DSP_1_ACOUT6", - "BCOUT7": "DSP_1_BCOUT7", - "ACIN27": "DSP_1_ACIN27", - "ACOUT4": "DSP_1_ACOUT4", - "PCOUT39": "DSP_1_PCOUT39", - "P9": "DSP_1_P9", - "C14": "DSP_1_C14", - "PCOUT22": "DSP_1_PCOUT22", - "B13": "DSP_1_B13", - "P19": "DSP_1_P19", - "PCIN15": "DSP_1_PCIN15", - "ACOUT17": "DSP_1_ACOUT17", - "A1": "DSP_1_A1", - "B3": "DSP_1_B3", - "C24": "DSP_1_C24", - "P35": "DSP_1_P35", - "P38": "DSP_1_P38", - "INMODE0": "DSP_1_INMODE0", - "PCIN26": "DSP_1_PCIN26", - "BCOUT9": "DSP_1_BCOUT9", - "P3": "DSP_1_P3", - "ALUMODE0": "DSP_1_ALUMODE0", - "A6": "DSP_1_A6", - "A18": "DSP_1_A18", - "P34": "DSP_1_P34", - "RSTINMODE": "DSP_1_RSTINMODE", - "A0": "DSP_1_A0", - "ACIN22": "DSP_1_ACIN22", - "ACOUT13": "DSP_1_ACOUT13", - "A17": "DSP_1_A17", - "C34": "DSP_1_C34", - "P10": "DSP_1_P10", - "BCIN15": "DSP_1_BCIN15", - "PATTERNDETECT": "DSP_1_PATTERNDETECT", - "C45": "DSP_1_C45", - "PCIN19": "DSP_1_PCIN19", + "C7": "DSP_1_C7", + "BCOUT3": "DSP_1_BCOUT3", + "C40": "DSP_1_C40", + "PCIN24": "DSP_1_PCIN24", + "BCIN16": "DSP_1_BCIN16", + "B5": "DSP_1_B5", + "C15": "DSP_1_C15", + "PCIN23": "DSP_1_PCIN23", + "ACOUT18": "DSP_1_ACOUT18", "BCIN2": "DSP_1_BCIN2", - "CEAD": "DSP_1_CEAD", - "PCIN46": "DSP_1_PCIN46", - "INMODE3": "DSP_1_INMODE3", - "P24": "DSP_1_P24", - "PCIN32": "DSP_1_PCIN32", - "A12": "DSP_1_A12", - "PCOUT35": "DSP_1_PCOUT35", - "C37": "DSP_1_C37", - "P42": "DSP_1_P42", - "PCIN30": "DSP_1_PCIN30", - "P26": "DSP_1_P26", - "ACOUT3": "DSP_1_ACOUT3", - "B6": "DSP_1_B6", - "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", - "ACIN20": "DSP_1_ACIN20", + "C14": "DSP_1_C14", + "C9": "DSP_1_C9", + "D0": "DSP_1_D0", + "A4": "DSP_1_A4", + "ACOUT23": "DSP_1_ACOUT23", + "PCIN33": "DSP_1_PCIN33", + "ACOUT16": "DSP_1_ACOUT16", + "PCIN25": "DSP_1_PCIN25", + "B0": "DSP_1_B0", "CEB1": "DSP_1_CEB1", - "P0": "DSP_1_P0", + "RSTB": "DSP_1_RSTB", + "P16": "DSP_1_P16", + "PCIN18": "DSP_1_PCIN18", + "RSTM": "DSP_1_RSTM", + "PCOUT3": "DSP_1_PCOUT3", + "PCIN40": "DSP_1_PCIN40", + "CARRYOUT2": "DSP_1_CARRYOUT2", + "ALUMODE3": "DSP_1_ALUMODE3", + "C5": "DSP_1_C5", + "BCIN9": "DSP_1_BCIN9", + "D20": "DSP_1_D20", + "BCIN17": "DSP_1_BCIN17", + "C38": "DSP_1_C38", + "A6": "DSP_1_A6", + "A13": "DSP_1_A13", + "CARRYOUT1": "DSP_1_CARRYOUT1", + "P32": "DSP_1_P32", + "C19": "DSP_1_C19", + "C11": "DSP_1_C11", "PCOUT5": "DSP_1_PCOUT5", "PCOUT25": "DSP_1_PCOUT25", - "PCIN23": "DSP_1_PCIN23", - "A3": "DSP_1_A3", - "PCOUT18": "DSP_1_PCOUT18", - "BCOUT8": "DSP_1_BCOUT8", - "P11": "DSP_1_P11", - "ACIN18": "DSP_1_ACIN18", - "B16": "DSP_1_B16", - "MULTSIGNIN": "DSP_1_MULTSIGNIN", - "ACOUT21": "DSP_1_ACOUT21", - "PCIN38": "DSP_1_PCIN38", - "C30": "DSP_1_C30", - "CARRYINSEL0": "DSP_1_CARRYINSEL0", - "C29": "DSP_1_C29", - "C19": "DSP_1_C19", - "ACOUT8": "DSP_1_ACOUT8", - "ACIN13": "DSP_1_ACIN13", - "PCOUT38": "DSP_1_PCOUT38", - "OPMODE1": "DSP_1_OPMODE1", - "PCOUT45": "DSP_1_PCOUT45", - "ACIN24": "DSP_1_ACIN24", - "OPMODE4": "DSP_1_OPMODE4", - "PCIN5": "DSP_1_PCIN5", - "PCOUT6": "DSP_1_PCOUT6", - "D16": "DSP_1_D16", - "ACOUT15": "DSP_1_ACOUT15", - "P12": "DSP_1_P12", - "ACOUT29": "DSP_1_ACOUT29", - "INMODE4": "DSP_1_INMODE4", - "C15": "DSP_1_C15", - "PCIN44": "DSP_1_PCIN44", - "P36": "DSP_1_P36", - "PCOUT2": "DSP_1_PCOUT2", - "C27": "DSP_1_C27", - "P1": "DSP_1_P1", - "CARRYINSEL1": "DSP_1_CARRYINSEL1", - "P8": "DSP_1_P8", - "PCOUT47": "DSP_1_PCOUT47", - "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", - "P18": "DSP_1_P18", - "PCOUT10": "DSP_1_PCOUT10", - "ACIN1": "DSP_1_ACIN1", - "C1": "DSP_1_C1", - "PCIN24": "DSP_1_PCIN24", - "RSTB": "DSP_1_RSTB", - "PCIN29": "DSP_1_PCIN29", - "P30": "DSP_1_P30", - "BCOUT15": "DSP_1_BCOUT15", - "P22": "DSP_1_P22", "BCIN13": "DSP_1_BCIN13", - "PCOUT34": "DSP_1_PCOUT34", - "BCIN11": "DSP_1_BCIN11", - "C18": "DSP_1_C18", - "A11": "DSP_1_A11", - "C43": "DSP_1_C43", - "C35": "DSP_1_C35", - "C47": "DSP_1_C47", - "PCIN34": "DSP_1_PCIN34", + "P38": "DSP_1_P38", + "ACOUT10": "DSP_1_ACOUT10", + "PCIN38": "DSP_1_PCIN38", + "C2": "DSP_1_C2", + "CEB2": "DSP_1_CEB2", "ACIN14": "DSP_1_ACIN14", - "PCIN8": "DSP_1_PCIN8", - "CEA2": "DSP_1_CEA2", - "A4": "DSP_1_A4", - "ACIN28": "DSP_1_ACIN28", - "A13": "DSP_1_A13", - "PCOUT42": "DSP_1_PCOUT42", - "PCOUT15": "DSP_1_PCOUT15", - "D10": "DSP_1_D10", - "CECTRL": "DSP_1_CECTRL", - "P6": "DSP_1_P6", - "ACOUT16": "DSP_1_ACOUT16", - "CEM": "DSP_1_CEM", - "A27": "DSP_1_A27", - "ACIN15": "DSP_1_ACIN15", - "D15": "DSP_1_D15", - "P23": "DSP_1_P23", - "UNDERFLOW": "DSP_1_UNDERFLOW", - "OVERFLOW": "DSP_1_OVERFLOW", - "RSTP": "DSP_1_RSTP", - "P39": "DSP_1_P39", - "CLK": "DSP_1_CLK", - "A29": "DSP_1_A29", - "P15": "DSP_1_P15", - "ACOUT24": "DSP_1_ACOUT24", - "ACOUT9": "DSP_1_ACOUT9", - "CECARRYIN": "DSP_1_CECARRYIN", + "ALUMODE1": "DSP_1_ALUMODE1", "P47": "DSP_1_P47", - "B7": "DSP_1_B7", - "BCOUT16": "DSP_1_BCOUT16", - "PCOUT13": "DSP_1_PCOUT13", - "ACIN9": "DSP_1_ACIN9", - "P14": "DSP_1_P14", - "ACOUT7": "DSP_1_ACOUT7", - "D4": "DSP_1_D4", - "C22": "DSP_1_C22", - "A26": "DSP_1_A26", - "P21": "DSP_1_P21", - "D6": "DSP_1_D6", - "D19": "DSP_1_D19", - "B17": "DSP_1_B17", - "P20": "DSP_1_P20", - "PCIN35": "DSP_1_PCIN35", - "PCIN39": "DSP_1_PCIN39", - "RSTC": "DSP_1_RSTC", - "B15": "DSP_1_B15", - "ACOUT19": "DSP_1_ACOUT19", - "PCOUT37": "DSP_1_PCOUT37", - "ACOUT20": "DSP_1_ACOUT20", + "PCOUT10": "DSP_1_PCOUT10", + "PCIN19": "DSP_1_PCIN19", + "P27": "DSP_1_P27", + "PCOUT39": "DSP_1_PCOUT39", + "P19": "DSP_1_P19", + "D12": "DSP_1_D12", + "ACOUT25": "DSP_1_ACOUT25", + "CEM": "DSP_1_CEM", + "P6": "DSP_1_P6", + "A25": "DSP_1_A25", + "BCIN6": "DSP_1_BCIN6", + "C47": "DSP_1_C47", + "PCIN2": "DSP_1_PCIN2", + "BCIN14": "DSP_1_BCIN14", + "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", + "D16": "DSP_1_D16", + "P2": "DSP_1_P2", + "ACOUT3": "DSP_1_ACOUT3", + "A11": "DSP_1_A11", + "PCIN8": "DSP_1_PCIN8", + "PCIN13": "DSP_1_PCIN13", + "P40": "DSP_1_P40", + "OPMODE3": "DSP_1_OPMODE3", + "BCOUT11": "DSP_1_BCOUT11", + "C4": "DSP_1_C4", + "PCIN4": "DSP_1_PCIN4", + "PCIN28": "DSP_1_PCIN28", + "ACOUT4": "DSP_1_ACOUT4", + "PCOUT2": "DSP_1_PCOUT2", + "BCIN0": "DSP_1_BCIN0", + "ACOUT26": "DSP_1_ACOUT26", + "ACOUT13": "DSP_1_ACOUT13", + "PCIN10": "DSP_1_PCIN10", + "PCOUT6": "DSP_1_PCOUT6", + "C43": "DSP_1_C43", + "A2": "DSP_1_A2", + "ACIN26": "DSP_1_ACIN26", + "CECARRYIN": "DSP_1_CECARRYIN", + "ACOUT15": "DSP_1_ACOUT15", + "PCOUT28": "DSP_1_PCOUT28", + "B2": "DSP_1_B2", + "ACIN1": "DSP_1_ACIN1", + "P23": "DSP_1_P23", + "PCIN0": "DSP_1_PCIN0", + "PCIN47": "DSP_1_PCIN47", + "BCOUT17": "DSP_1_BCOUT17", + "PCOUT42": "DSP_1_PCOUT42", + "D22": "DSP_1_D22", + "CED": "DSP_1_CED", + "ACIN23": "DSP_1_ACIN23", + "ACIN2": "DSP_1_ACIN2", + "A17": "DSP_1_A17", + "PCOUT20": "DSP_1_PCOUT20", + "BCIN7": "DSP_1_BCIN7", + "D14": "DSP_1_D14", + "P8": "DSP_1_P8", + "ALUMODE2": "DSP_1_ALUMODE2", + "D17": "DSP_1_D17", + "ACIN10": "DSP_1_ACIN10", + "OPMODE4": "DSP_1_OPMODE4", "C26": "DSP_1_C26", - "RSTM": "DSP_1_RSTM", - "PCOUT1": "DSP_1_PCOUT1", + "ACIN16": "DSP_1_ACIN16", + "PCIN5": "DSP_1_PCIN5", "C44": "DSP_1_C44", + "ACIN5": "DSP_1_ACIN5", + "PCIN37": "DSP_1_PCIN37", + "PCIN15": "DSP_1_PCIN15", + "PCOUT44": "DSP_1_PCOUT44", + "C22": "DSP_1_C22", + "A0": "DSP_1_A0", + "INMODE4": "DSP_1_INMODE4", + "B3": "DSP_1_B3", + "C0": "DSP_1_C0", + "P29": "DSP_1_P29", + "ACOUT21": "DSP_1_ACOUT21", + "PCIN1": "DSP_1_PCIN1", + "B15": "DSP_1_B15", + "PCIN39": "DSP_1_PCIN39", + "OPMODE1": "DSP_1_OPMODE1", + "ACIN12": "DSP_1_ACIN12", + "ACIN27": "DSP_1_ACIN27", + "PCOUT41": "DSP_1_PCOUT41", + "ACOUT2": "DSP_1_ACOUT2", + "ACIN8": "DSP_1_ACIN8", + "B13": "DSP_1_B13", + "A28": "DSP_1_A28", + "PCOUT8": "DSP_1_PCOUT8", + "P11": "DSP_1_P11", "P5": "DSP_1_P5", - "PCOUT33": "DSP_1_PCOUT33", + "CARRYOUT0": "DSP_1_CARRYOUT0", + "D7": "DSP_1_D7", + "CEC": "DSP_1_CEC", + "ACOUT12": "DSP_1_ACOUT12", + "A29": "DSP_1_A29", + "B1": "DSP_1_B1", + "C17": "DSP_1_C17", + "B4": "DSP_1_B4", + "C27": "DSP_1_C27", + "CARRYCASCOUT": "DSP_1_CARRYCASCOUT", + "P28": "DSP_1_P28", + "A24": "DSP_1_A24", + "RSTINMODE": "DSP_1_RSTINMODE", + "P20": "DSP_1_P20", + "CEALUMODE": "DSP_1_CEALUMODE", + "ACOUT20": "DSP_1_ACOUT20", + "P14": "DSP_1_P14", + "C33": "DSP_1_C33", + "P34": "DSP_1_P34", + "C1": "DSP_1_C1", + "BCOUT13": "DSP_1_BCOUT13", + "PCIN42": "DSP_1_PCIN42", + "P39": "DSP_1_P39", + "B7": "DSP_1_B7", + "B10": "DSP_1_B10", + "PCIN16": "DSP_1_PCIN16", + "CARRYINSEL0": "DSP_1_CARRYINSEL0", + "PCOUT26": "DSP_1_PCOUT26", + "C6": "DSP_1_C6", + "CEA2": "DSP_1_CEA2", + "ACOUT5": "DSP_1_ACOUT5", + "PCOUT18": "DSP_1_PCOUT18", + "BCIN10": "DSP_1_BCIN10", + "PCOUT32": "DSP_1_PCOUT32", + "PCIN20": "DSP_1_PCIN20", + "OPMODE5": "DSP_1_OPMODE5", + "A26": "DSP_1_A26", + "PCOUT14": "DSP_1_PCOUT14", + "P13": "DSP_1_P13", + "BCOUT5": "DSP_1_BCOUT5", + "CEAD": "DSP_1_CEAD", + "MULTSIGNIN": "DSP_1_MULTSIGNIN", + "ACOUT14": "DSP_1_ACOUT14", + "D1": "DSP_1_D1", + "OPMODE2": "DSP_1_OPMODE2", + "A12": "DSP_1_A12", + "C41": "DSP_1_C41", + "C10": "DSP_1_C10", + "PCOUT9": "DSP_1_PCOUT9", + "D24": "DSP_1_D24", + "PCIN27": "DSP_1_PCIN27", + "ACOUT1": "DSP_1_ACOUT1", + "ACOUT29": "DSP_1_ACOUT29", + "ACIN25": "DSP_1_ACIN25", + "A3": "DSP_1_A3", + "B9": "DSP_1_B9", + "A21": "DSP_1_A21", + "PCOUT17": "DSP_1_PCOUT17", + "PCOUT34": "DSP_1_PCOUT34", + "PCOUT35": "DSP_1_PCOUT35", + "ACOUT27": "DSP_1_ACOUT27", + "D13": "DSP_1_D13", + "A15": "DSP_1_A15", + "P24": "DSP_1_P24", + "D5": "DSP_1_D5", + "BCOUT2": "DSP_1_BCOUT2", + "CARRYIN": "DSP_1_CARRYIN", + "C37": "DSP_1_C37", + "ACOUT22": "DSP_1_ACOUT22", "C36": "DSP_1_C36", + "ACOUT17": "DSP_1_ACOUT17", + "P1": "DSP_1_P1", + "PCOUT45": "DSP_1_PCOUT45", + "PCIN45": "DSP_1_PCIN45", + "P10": "DSP_1_P10", + "P33": "DSP_1_P33", + "B17": "DSP_1_B17", + "C16": "DSP_1_C16", + "A23": "DSP_1_A23", + "PCIN32": "DSP_1_PCIN32", + "PCOUT40": "DSP_1_PCOUT40", + "A5": "DSP_1_A5", + "INMODE2": "DSP_1_INMODE2", + "RSTA": "DSP_1_RSTA", + "A14": "DSP_1_A14", + "BCOUT7": "DSP_1_BCOUT7", + "ACIN0": "DSP_1_ACIN0", + "PCIN31": "DSP_1_PCIN31", + "PCIN22": "DSP_1_PCIN22", + "PCOUT13": "DSP_1_PCOUT13", + "PCOUT15": "DSP_1_PCOUT15", + "P17": "DSP_1_P17", + "ACIN4": "DSP_1_ACIN4", + "PCIN11": "DSP_1_PCIN11", + "A20": "DSP_1_A20", + "ACIN11": "DSP_1_ACIN11", + "BCOUT9": "DSP_1_BCOUT9", + "OPMODE0": "DSP_1_OPMODE0", + "PCIN12": "DSP_1_PCIN12", + "RSTD": "DSP_1_RSTD", + "A10": "DSP_1_A10", + "ACOUT19": "DSP_1_ACOUT19", + "C25": "DSP_1_C25", + "ACIN28": "DSP_1_ACIN28", + "D6": "DSP_1_D6", + "ACOUT0": "DSP_1_ACOUT0", + "BCOUT1": "DSP_1_BCOUT1", + "P46": "DSP_1_P46", + "P4": "DSP_1_P4", + "C35": "DSP_1_C35", + "D10": "DSP_1_D10", + "C42": "DSP_1_C42", + "P42": "DSP_1_P42", + "PCIN44": "DSP_1_PCIN44", + "PCOUT43": "DSP_1_PCOUT43", + "CEP": "DSP_1_CEP", + "C23": "DSP_1_C23", + "A8": "DSP_1_A8", + "A18": "DSP_1_A18", + "CARRYINSEL2": "DSP_1_CARRYINSEL2", + "ACOUT28": "DSP_1_ACOUT28", + "C29": "DSP_1_C29", + "BCOUT12": "DSP_1_BCOUT12", + "P35": "DSP_1_P35", + "ACOUT8": "DSP_1_ACOUT8", + "RSTP": "DSP_1_RSTP", + "ACIN24": "DSP_1_ACIN24", + "PCIN9": "DSP_1_PCIN9", + "ACIN6": "DSP_1_ACIN6", + "BCOUT14": "DSP_1_BCOUT14", + "P41": "DSP_1_P41", + "BCOUT16": "DSP_1_BCOUT16", + "RSTALUMODE": "DSP_1_RSTALUMODE", + "C8": "DSP_1_C8", + "PCOUT23": "DSP_1_PCOUT23", + "BCOUT8": "DSP_1_BCOUT8", + "C24": "DSP_1_C24", + "C30": "DSP_1_C30", + "ACIN21": "DSP_1_ACIN21", + "ACIN13": "DSP_1_ACIN13", + "PCOUT33": "DSP_1_PCOUT33", + "ACIN19": "DSP_1_ACIN19", + "D21": "DSP_1_D21", + "ACIN20": "DSP_1_ACIN20", + "D23": "DSP_1_D23", + "A19": "DSP_1_A19", + "B16": "DSP_1_B16", + "PCOUT4": "DSP_1_PCOUT4", + "PCOUT27": "DSP_1_PCOUT27", + "PCIN29": "DSP_1_PCIN29", + "CLK": "DSP_1_CLK", + "PCOUT19": "DSP_1_PCOUT19", + "PCOUT47": "DSP_1_PCOUT47", + "PCIN34": "DSP_1_PCIN34", + "D2": "DSP_1_D2", + "P25": "DSP_1_P25", + "ACIN9": "DSP_1_ACIN9", + "BCOUT6": "DSP_1_BCOUT6", + "PCIN21": "DSP_1_PCIN21", + "C3": "DSP_1_C3", + "PCOUT7": "DSP_1_PCOUT7", + "PCOUT31": "DSP_1_PCOUT31", + "PCOUT12": "DSP_1_PCOUT12", + "BCOUT4": "DSP_1_BCOUT4", + "B8": "DSP_1_B8", + "C34": "DSP_1_C34", + "BCIN3": "DSP_1_BCIN3", + "INMODE1": "DSP_1_INMODE1", + "PCIN26": "DSP_1_PCIN26", + "CARRYOUT3": "DSP_1_CARRYOUT3", + "D11": "DSP_1_D11", + "INMODE3": "DSP_1_INMODE3", + "BCOUT15": "DSP_1_BCOUT15", + "D3": "DSP_1_D3", + "P37": "DSP_1_P37", + "PCOUT16": "DSP_1_PCOUT16", + "D8": "DSP_1_D8", + "ACIN18": "DSP_1_ACIN18", + "C21": "DSP_1_C21", + "PCOUT36": "DSP_1_PCOUT36", + "BCIN11": "DSP_1_BCIN11", + "CARRYINSEL1": "DSP_1_CARRYINSEL1", + "D9": "DSP_1_D9", + "C20": "DSP_1_C20", + "ACOUT7": "DSP_1_ACOUT7", + "P26": "DSP_1_P26", + "RSTCTRL": "DSP_1_RSTCTRL", + "RSTC": "DSP_1_RSTC", + "D19": "DSP_1_D19", + "D18": "DSP_1_D18", + "ACIN7": "DSP_1_ACIN7", + "PCIN17": "DSP_1_PCIN17", + "D15": "DSP_1_D15", + "PCOUT1": "DSP_1_PCOUT1", + "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", + "PCOUT21": "DSP_1_PCOUT21", + "A9": "DSP_1_A9", + "ALUMODE0": "DSP_1_ALUMODE0", + "BCOUT10": "DSP_1_BCOUT10", + "UNDERFLOW": "DSP_1_UNDERFLOW", + "PCIN35": "DSP_1_PCIN35", + "ACOUT6": "DSP_1_ACOUT6", "C31": "DSP_1_C31", "PCOUT29": "DSP_1_PCOUT29", - "C39": "DSP_1_C39", + "P31": "DSP_1_P31", + "INMODE0": "DSP_1_INMODE0", + "PCOUT22": "DSP_1_PCOUT22", + "PCOUT30": "DSP_1_PCOUT30", "BCIN4": "DSP_1_BCIN4", - "PCIN2": "DSP_1_PCIN2" + "D4": "DSP_1_D4", + "ACIN15": "DSP_1_ACIN15", + "PCIN36": "DSP_1_PCIN36", + "P3": "DSP_1_P3", + "PCIN3": "DSP_1_PCIN3", + "PCOUT37": "DSP_1_PCOUT37", + "OPMODE6": "DSP_1_OPMODE6", + "B14": "DSP_1_B14", + "C39": "DSP_1_C39", + "P22": "DSP_1_P22", + "CEA1": "DSP_1_CEA1", + "PATTERNDETECT": "DSP_1_PATTERNDETECT", + "A16": "DSP_1_A16", + "CARRYCASCIN": "DSP_1_CARRYCASCIN", + "CEINMODE": "DSP_1_CEINMODE", + "P21": "DSP_1_P21", + "BCIN5": "DSP_1_BCIN5", + "PCOUT38": "DSP_1_PCOUT38" }, + "type": "DSP48E1", + "prefix": "DSP48", + "name": "X0Y1", "x_coord": 0, - "name": "X0Y1" + "y_coord": 1 }, { - "prefix": "TIEOFF", - "y_coord": 87, - "type": "TIEOFF", "site_pins": { "HARD0": "DSP_GND_R", "HARD1": "DSP_VCC_R" }, + "type": "TIEOFF", + "prefix": "TIEOFF", + "name": "X10Y87", "x_coord": 10, - "name": "X10Y87" + "y_coord": 87 } - ], - "pips": { - "DSP_R.DSP_1_PCOUT7->DSP_PCOUT7": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT7", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT7", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX39_3->DSP_0_C12": { - "can_invert": "0", - "dst_wire": "DSP_0_C12", - "is_directional": "1", - "src_wire": "DSP_IMUX39_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT9->DSP_1_ACIN9": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN9", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT9", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX12_1->DSP_1_C26": { - "can_invert": "0", - "dst_wire": "DSP_1_C26", - "is_directional": "1", - "src_wire": "DSP_IMUX12_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_1_CEAD", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT47->DSP_PCOUT47": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT47", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT47", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D5": { - "can_invert": "0", - "dst_wire": "DSP_0_D5", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX5_1->DSP_1_A25": { - "can_invert": "0", - "dst_wire": "DSP_1_A25", - "is_directional": "1", - "src_wire": "DSP_IMUX5_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTD", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX45_3->DSP_1_A12": { - "can_invert": "0", - "dst_wire": "DSP_1_A12", - "is_directional": "1", - "src_wire": "DSP_IMUX45_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL1_2->DSP_1_RSTA": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTA", - "is_directional": "1", - "src_wire": "DSP_CTRL1_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D13": { - "can_invert": "0", - "dst_wire": "DSP_1_D13", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX33_1->DSP_0_C7": { - "can_invert": "0", - "dst_wire": "DSP_0_C7", - "is_directional": "1", - "src_wire": "DSP_IMUX33_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN0_2->DSP_1_D22": { - "can_invert": "0", - "dst_wire": "DSP_1_D22", - "is_directional": "1", - "src_wire": "DSP_FAN0_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX6_0->DSP_0_A23": { - "can_invert": "0", - "dst_wire": "DSP_0_A23", - "is_directional": "1", - "src_wire": "DSP_IMUX6_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT46->DSP_PCOUT46": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT46", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT46", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX44_4->DSP_1_A18": { - "can_invert": "0", - "dst_wire": "DSP_1_A18", - "is_directional": "1", - "src_wire": "DSP_IMUX44_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_3", - "is_directional": "1", - "src_wire": "DSP_0_P13", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX19_2->DSP_0_A9": { - "can_invert": "0", - "dst_wire": "DSP_0_A9", - "is_directional": "1", - "src_wire": "DSP_IMUX19_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX5_0->DSP_1_A21": { - "can_invert": "0", - "dst_wire": "DSP_1_A21", - "is_directional": "1", - "src_wire": "DSP_IMUX5_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT12->DSP_1_ACIN12": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN12", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT12", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D12": { - "can_invert": "0", - "dst_wire": "DSP_1_D12", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT33->DSP_1_PCIN33": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN33", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT33", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT3->DSP_BCOUT3": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT3", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT3", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D9": { - "can_invert": "0", - "dst_wire": "DSP_1_D9", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "DSP_1_P47", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D22": { - "can_invert": "0", - "dst_wire": "DSP_1_D22", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN0_0->DSP_0_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_FAN0_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP0_2->DSP_0_D22": { - "can_invert": "0", - "dst_wire": "DSP_0_D22", - "is_directional": "1", - "src_wire": "DSP_BYP0_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT35->DSP_1_PCIN35": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN35", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT35", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D24": { - "can_invert": "0", - "dst_wire": "DSP_1_D24", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT18->DSP_1_ACIN18": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN18", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT18", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT12->DSP_1_BCIN12": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN12", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT12", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX36_2->DSP_0_B10": { - "can_invert": "0", - "dst_wire": "DSP_0_B10", - "is_directional": "1", - "src_wire": "DSP_IMUX36_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX39_0->DSP_0_C0": { - "can_invert": "0", - "dst_wire": "DSP_0_C0", - "is_directional": "1", - "src_wire": "DSP_IMUX39_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX47_0->DSP_0_A20": { - "can_invert": "0", - "dst_wire": "DSP_0_A20", - "is_directional": "1", - "src_wire": "DSP_IMUX47_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX0_2->DSP_0_CECARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_0_CECARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX0_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D10": { - "can_invert": "0", - "dst_wire": "DSP_1_D10", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "DSP_1_CARRYOUT2", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN5_3->DSP_1_D14": { - "can_invert": "0", - "dst_wire": "DSP_1_D14", - "is_directional": "1", - "src_wire": "DSP_FAN5_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT20->DSP_PCOUT20": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT20", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT20", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D8": { - "can_invert": "0", - "dst_wire": "DSP_0_D8", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE3", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_CED": { - "can_invert": "0", - "dst_wire": "DSP_0_CED", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT18->DSP_ACOUT18": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT18", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT18", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE4", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "DSP_0_P40", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP5_2->DSP_0_D9": { - "can_invert": "0", - "dst_wire": "DSP_0_D9", - "is_directional": "1", - "src_wire": "DSP_BYP5_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT13->DSP_PCOUT13": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT13", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT13", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D4": { - "can_invert": "0", - "dst_wire": "DSP_1_D4", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT2->DSP_1_BCIN2": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN2", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT29->DSP_PCOUT29": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT29", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT29", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX3_1->DSP_0_RSTALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTALUMODE", - "is_directional": "1", - "src_wire": "DSP_IMUX3_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP4_1->DSP_0_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTD", - "is_directional": "1", - "src_wire": "DSP_BYP4_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX43_4->DSP_0_B16": { - "can_invert": "0", - "dst_wire": "DSP_0_B16", - "is_directional": "1", - "src_wire": "DSP_IMUX43_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT31->DSP_1_PCIN31": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN31", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT31", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE2", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT5->DSP_1_BCIN5": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN5", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT5", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT27->DSP_ACOUT27": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT27", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT27", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_2", - "is_directional": "1", - "src_wire": "DSP_0_P29", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D3": { - "can_invert": "0", - "dst_wire": "DSP_0_D3", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX2_2->DSP_0_C29": { - "can_invert": "0", - "dst_wire": "DSP_0_C29", - "is_directional": "1", - "src_wire": "DSP_IMUX2_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "DSP_0_P27", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX14_4->DSP_1_RSTCTRL": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTCTRL", - "is_directional": "1", - "src_wire": "DSP_IMUX14_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "DSP_0_P46", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D7": { - "can_invert": "0", - "dst_wire": "DSP_0_D7", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX18_2->DSP_0_B9": { - "can_invert": "0", - "dst_wire": "DSP_0_B9", - "is_directional": "1", - "src_wire": "DSP_IMUX18_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "DSP_0_PATTERNBDETECT", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D23": { - "can_invert": "0", - "dst_wire": "DSP_0_D23", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE1", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX1_2->DSP_0_CEM": { - "can_invert": "0", - "dst_wire": "DSP_0_CEM", - "is_directional": "1", - "src_wire": "DSP_IMUX1_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX9_3->DSP_1_CEA1": { - "can_invert": "0", - "dst_wire": "DSP_1_CEA1", - "is_directional": "1", - "src_wire": "DSP_IMUX9_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT28->DSP_1_PCIN28": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN28", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT28", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT45->DSP_1_PCIN45": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN45", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT45", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT37->DSP_PCOUT37": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT37", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT37", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX39_4->DSP_0_C16": { - "can_invert": "0", - "dst_wire": "DSP_0_C16", - "is_directional": "1", - "src_wire": "DSP_IMUX39_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_0", - "is_directional": "1", - "src_wire": "DSP_1_P3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX47_2->DSP_0_A28": { - "can_invert": "0", - "dst_wire": "DSP_0_A28", - "is_directional": "1", - "src_wire": "DSP_IMUX47_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "DSP_0_P14", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP3_1->DSP_0_D6": { - "can_invert": "0", - "dst_wire": "DSP_0_D6", - "is_directional": "1", - "src_wire": "DSP_BYP3_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT16->DSP_1_ACIN16": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN16", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT16", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D13": { - "can_invert": "0", - "dst_wire": "DSP_0_D13", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT18->DSP_PCOUT18": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT18", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT18", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX33_0->DSP_0_C43": { - "can_invert": "0", - "dst_wire": "DSP_0_C43", - "is_directional": "1", - "src_wire": "DSP_IMUX33_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D18": { - "can_invert": "0", - "dst_wire": "DSP_0_D18", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D21": { - "can_invert": "0", - "dst_wire": "DSP_1_D21", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT46->DSP_1_PCIN46": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN46", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT46", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX41_1->DSP_0_CEB1": { - "can_invert": "0", - "dst_wire": "DSP_0_CEB1", - "is_directional": "1", - "src_wire": "DSP_IMUX41_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT34->DSP_PCOUT34": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT34", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT34", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT39->DSP_1_PCIN39": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN39", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT39", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN7_4->DSP_1_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE2", - "is_directional": "1", - "src_wire": "DSP_FAN7_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "DSP_0_P24", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX25_3->DSP_1_C15": { - "can_invert": "0", - "dst_wire": "DSP_1_C15", - "is_directional": "1", - "src_wire": "DSP_IMUX25_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_4", - "is_directional": "1", - "src_wire": "DSP_0_P45", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT23->DSP_PCOUT23": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT23", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT23", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT13->DSP_1_ACIN13": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN13", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT13", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D4": { - "can_invert": "0", - "dst_wire": "DSP_0_D4", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "DSP_0_P15", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT11->DSP_1_ACIN11": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN11", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT11", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX6_4->DSP_0_A19": { - "can_invert": "0", - "dst_wire": "DSP_0_A19", - "is_directional": "1", - "src_wire": "DSP_IMUX6_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN2_3->DSP_1_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_FAN2_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT9->DSP_BCOUT9": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT9", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT9", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT11->DSP_BCOUT11": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT11", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT11", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT7->DSP_ACOUT7": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT7", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT7", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN5_4->DSP_1_D18": { - "can_invert": "0", - "dst_wire": "DSP_1_D18", - "is_directional": "1", - "src_wire": "DSP_FAN5_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "DSP_0_P6", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX16_3->DSP_1_CEB2": { - "can_invert": "0", - "dst_wire": "DSP_1_CEB2", - "is_directional": "1", - "src_wire": "DSP_IMUX16_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT15->DSP_1_PCIN15": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN15", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT15", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "DSP_0_CARRYOUT2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX10_3->DSP_1_C33": { - "can_invert": "0", - "dst_wire": "DSP_1_C33", - "is_directional": "1", - "src_wire": "DSP_IMUX10_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX47_3->DSP_0_A12": { - "can_invert": "0", - "dst_wire": "DSP_0_A12", - "is_directional": "1", - "src_wire": "DSP_IMUX47_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX3_4->DSP_0_B17": { - "can_invert": "0", - "dst_wire": "DSP_0_B17", - "is_directional": "1", - "src_wire": "DSP_IMUX3_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT32->DSP_PCOUT32": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT32", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT32", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT3->DSP_1_BCIN3": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN3", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX46_2->DSP_1_C28": { - "can_invert": "0", - "dst_wire": "DSP_1_C28", - "is_directional": "1", - "src_wire": "DSP_IMUX46_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT6->DSP_1_PCIN6": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN6", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT6", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_1", - "is_directional": "1", - "src_wire": "DSP_1_P26", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX32_4->DSP_0_C37": { - "can_invert": "0", - "dst_wire": "DSP_0_C37", - "is_directional": "1", - "src_wire": "DSP_IMUX32_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT11->DSP_PCOUT11": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT11", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT11", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP6_0->DSP_0_D20": { - "can_invert": "0", - "dst_wire": "DSP_0_D20", - "is_directional": "1", - "src_wire": "DSP_BYP6_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT29->DSP_1_PCIN29": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN29", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT29", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "DSP_1_UNDERFLOW", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT28->DSP_PCOUT28": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT28", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT28", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX18_0->DSP_0_C21": { - "can_invert": "0", - "dst_wire": "DSP_0_C21", - "is_directional": "1", - "src_wire": "DSP_IMUX18_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX13_4->DSP_1_C18": { - "can_invert": "0", - "dst_wire": "DSP_1_C18", - "is_directional": "1", - "src_wire": "DSP_IMUX13_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT27->DSP_1_ACIN27": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN27", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT27", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_2", - "is_directional": "1", - "src_wire": "DSP_1_P11", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT8->DSP_1_BCIN8": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN8", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT8", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "DSP_0_P37", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B8_4", - "is_directional": "1", - "src_wire": "DSP_0_P47", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_1", - "is_directional": "1", - "src_wire": "DSP_1_P24", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP1_2->DSP_0_D11": { - "can_invert": "0", - "dst_wire": "DSP_0_D11", - "is_directional": "1", - "src_wire": "DSP_BYP1_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN1_1->DSP_1_D21": { - "can_invert": "0", - "dst_wire": "DSP_1_D21", - "is_directional": "1", - "src_wire": "DSP_FAN1_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_1", - "is_directional": "1", - "src_wire": "DSP_0_CARRYOUT1", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D22": { - "can_invert": "0", - "dst_wire": "DSP_0_D22", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP6_4->DSP_1_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTD", - "is_directional": "1", - "src_wire": "DSP_BYP6_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT23->DSP_ACOUT23": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT23", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT23", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D1": { - "can_invert": "0", - "dst_wire": "DSP_1_D1", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN2_4->DSP_1_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_FAN2_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX42_0->DSP_0_C42": { - "can_invert": "0", - "dst_wire": "DSP_0_C42", - "is_directional": "1", - "src_wire": "DSP_IMUX42_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT1->DSP_1_BCIN1": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN1", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX11_0->DSP_1_A1": { - "can_invert": "0", - "dst_wire": "DSP_1_A1", - "is_directional": "1", - "src_wire": "DSP_IMUX11_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D6": { - "can_invert": "0", - "dst_wire": "DSP_0_D6", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT44->DSP_1_PCIN44": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN44", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT44", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP1_0->DSP_0_D3": { - "can_invert": "0", - "dst_wire": "DSP_0_D3", - "is_directional": "1", - "src_wire": "DSP_BYP1_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "DSP_0_P42", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT0->DSP_1_ACIN0": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN0", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT0", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D10": { - "can_invert": "0", - "dst_wire": "DSP_1_D10", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D19": { - "can_invert": "0", - "dst_wire": "DSP_1_D19", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B8_3", - "is_directional": "1", - "src_wire": "DSP_1_CARRYOUT0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_0", - "is_directional": "1", - "src_wire": "DSP_0_P0", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP1_1->DSP_0_D7": { - "can_invert": "0", - "dst_wire": "DSP_0_D7", - "is_directional": "1", - "src_wire": "DSP_BYP1_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "DSP_0_P23", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX26_3->DSP_1_CECARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_1_CECARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX26_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D2": { - "can_invert": "0", - "dst_wire": "DSP_0_D2", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN3_4->DSP_1_D16": { - "can_invert": "0", - "dst_wire": "DSP_1_D16", - "is_directional": "1", - "src_wire": "DSP_FAN3_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX44_0->DSP_1_A22": { - "can_invert": "0", - "dst_wire": "DSP_1_A22", - "is_directional": "1", - "src_wire": "DSP_IMUX44_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "DSP_0_P35", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D9": { - "can_invert": "0", - "dst_wire": "DSP_0_D9", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE1", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D14": { - "can_invert": "0", - "dst_wire": "DSP_1_D14", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT10->DSP_BCOUT10": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT10", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT10", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "DSP_1_P38", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT15->DSP_1_ACIN15": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN15", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT15", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX20_0->DSP_0_C22": { - "can_invert": "0", - "dst_wire": "DSP_0_C22", - "is_directional": "1", - "src_wire": "DSP_IMUX20_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "DSP_0_CARRYOUT3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT37->DSP_1_PCIN37": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN37", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT37", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT19->DSP_1_PCIN19": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN19", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT19", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX0_0->DSP_1_B3": { - "can_invert": "0", - "dst_wire": "DSP_1_B3", - "is_directional": "1", - "src_wire": "DSP_IMUX0_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT4->DSP_PCOUT4": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT4", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "DSP_0_P32", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT43->DSP_PCOUT43": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT43", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT43", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP0_3->DSP_1_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_1_CEAD", - "is_directional": "1", - "src_wire": "DSP_BYP0_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX12_0->DSP_1_C22": { - "can_invert": "0", - "dst_wire": "DSP_1_C22", - "is_directional": "1", - "src_wire": "DSP_IMUX12_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D7": { - "can_invert": "0", - "dst_wire": "DSP_0_D7", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT15->DSP_ACOUT15": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT15", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT15", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX29_0->DSP_1_C2": { - "can_invert": "0", - "dst_wire": "DSP_1_C2", - "is_directional": "1", - "src_wire": "DSP_IMUX29_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP4_2->DSP_1_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE0", - "is_directional": "1", - "src_wire": "DSP_BYP4_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP5_1->DSP_0_D5": { - "can_invert": "0", - "dst_wire": "DSP_0_D5", - "is_directional": "1", - "src_wire": "DSP_BYP5_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT22->DSP_1_PCIN22": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN22", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT22", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX11_2->DSP_1_A9": { - "can_invert": "0", - "dst_wire": "DSP_1_A9", - "is_directional": "1", - "src_wire": "DSP_IMUX11_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX44_2->DSP_1_B10": { - "can_invert": "0", - "dst_wire": "DSP_1_B10", - "is_directional": "1", - "src_wire": "DSP_IMUX44_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX38_3->DSP_0_C32": { - "can_invert": "0", - "dst_wire": "DSP_0_C32", - "is_directional": "1", - "src_wire": "DSP_IMUX38_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX5_3->DSP_1_A13": { - "can_invert": "0", - "dst_wire": "DSP_1_A13", - "is_directional": "1", - "src_wire": "DSP_IMUX5_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D8": { - "can_invert": "0", - "dst_wire": "DSP_0_D8", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D4": { - "can_invert": "0", - "dst_wire": "DSP_0_D4", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT17->DSP_ACOUT17": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT17", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT17", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX25_0->DSP_1_C43": { - "can_invert": "0", - "dst_wire": "DSP_1_C43", - "is_directional": "1", - "src_wire": "DSP_IMUX25_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_0", - "is_directional": "1", - "src_wire": "DSP_1_P1", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_CED": { - "can_invert": "0", - "dst_wire": "DSP_1_CED", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D12": { - "can_invert": "0", - "dst_wire": "DSP_0_D12", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT22->DSP_PCOUT22": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT22", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT22", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP7_0->DSP_0_D0": { - "can_invert": "0", - "dst_wire": "DSP_0_D0", - "is_directional": "1", - "src_wire": "DSP_BYP7_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX17_1->DSP_0_A7": { - "can_invert": "0", - "dst_wire": "DSP_0_A7", - "is_directional": "1", - "src_wire": "DSP_IMUX17_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX30_2->DSP_0_OPMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE1", - "is_directional": "1", - "src_wire": "DSP_IMUX30_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "DSP_1_PATTERNBDETECT", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX41_4->DSP_1_C19": { - "can_invert": "0", - "dst_wire": "DSP_1_C19", - "is_directional": "1", - "src_wire": "DSP_IMUX41_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT5->DSP_PCOUT5": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT5", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT5", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX9_2->DSP_1_A11": { - "can_invert": "0", - "dst_wire": "DSP_1_A11", - "is_directional": "1", - "src_wire": "DSP_IMUX9_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX24_4->DSP_1_C37": { - "can_invert": "0", - "dst_wire": "DSP_1_C37", - "is_directional": "1", - "src_wire": "DSP_IMUX24_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX43_3->DSP_0_B12": { - "can_invert": "0", - "dst_wire": "DSP_0_B12", - "is_directional": "1", - "src_wire": "DSP_IMUX43_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN4_1->DSP_1_D7": { - "can_invert": "0", - "dst_wire": "DSP_1_D7", - "is_directional": "1", - "src_wire": "DSP_FAN4_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX12_2->DSP_0_OPMODE5": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE5", - "is_directional": "1", - "src_wire": "DSP_IMUX12_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX34_3->DSP_1_CEC": { - "can_invert": "0", - "dst_wire": "DSP_1_CEC", - "is_directional": "1", - "src_wire": "DSP_IMUX34_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX9_4->DSP_1_OPMODE5": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE5", - "is_directional": "1", - "src_wire": "DSP_IMUX9_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D13": { - "can_invert": "0", - "dst_wire": "DSP_0_D13", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT16->DSP_1_BCIN16": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN16", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT16", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX10_0->DSP_1_C21": { - "can_invert": "0", - "dst_wire": "DSP_1_C21", - "is_directional": "1", - "src_wire": "DSP_IMUX10_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX19_0->DSP_0_A1": { - "can_invert": "0", - "dst_wire": "DSP_0_A1", - "is_directional": "1", - "src_wire": "DSP_IMUX19_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_4", - "is_directional": "1", - "src_wire": "DSP_1_P16", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX46_4->DSP_0_A18": { - "can_invert": "0", - "dst_wire": "DSP_0_A18", - "is_directional": "1", - "src_wire": "DSP_IMUX46_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D20": { - "can_invert": "0", - "dst_wire": "DSP_1_D20", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B9_4", - "is_directional": "1", - "src_wire": "DSP_0_P44", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX31_3->DSP_1_C12": { - "can_invert": "0", - "dst_wire": "DSP_1_C12", - "is_directional": "1", - "src_wire": "DSP_IMUX31_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT8->DSP_1_PCIN8": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN8", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT8", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_0", - "is_directional": "1", - "src_wire": "DSP_1_P22", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_3", - "is_directional": "1", - "src_wire": "DSP_1_P14", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D14": { - "can_invert": "0", - "dst_wire": "DSP_0_D14", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX21_1->DSP_0_A6": { - "can_invert": "0", - "dst_wire": "DSP_0_A6", - "is_directional": "1", - "src_wire": "DSP_IMUX21_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_4", - "is_directional": "1", - "src_wire": "DSP_1_P19", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "DSP_0_P41", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { - "can_invert": "0", - "dst_wire": "DSP_1_MULTSIGNIN", - "is_directional": "1", - "src_wire": "DSP_0_MULTSIGNOUT", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_1", - "is_directional": "1", - "src_wire": "DSP_1_P25", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT40->DSP_1_PCIN40": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN40", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT40", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT6->DSP_BCOUT6": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT6", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT6", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX20_3->DSP_0_C34": { - "can_invert": "0", - "dst_wire": "DSP_0_C34", - "is_directional": "1", - "src_wire": "DSP_IMUX20_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D3": { - "can_invert": "0", - "dst_wire": "DSP_1_D3", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_CED": { - "can_invert": "0", - "dst_wire": "DSP_0_CED", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT11->DSP_1_BCIN11": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN11", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT11", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX46_0->DSP_0_A22": { - "can_invert": "0", - "dst_wire": "DSP_0_A22", - "is_directional": "1", - "src_wire": "DSP_IMUX46_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN1_2->DSP_0_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE2", - "is_directional": "1", - "src_wire": "DSP_FAN1_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX43_0->DSP_1_C1": { - "can_invert": "0", - "dst_wire": "DSP_1_C1", - "is_directional": "1", - "src_wire": "DSP_IMUX43_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_0", - "is_directional": "1", - "src_wire": "DSP_1_P20", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_1", - "is_directional": "1", - "src_wire": "DSP_1_P7", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX16_0->DSP_0_C41": { - "can_invert": "0", - "dst_wire": "DSP_0_C41", - "is_directional": "1", - "src_wire": "DSP_IMUX16_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX29_1->DSP_1_C6": { - "can_invert": "0", - "dst_wire": "DSP_1_C6", - "is_directional": "1", - "src_wire": "DSP_IMUX29_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT12->DSP_PCOUT12": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT12", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT12", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT26->DSP_1_ACIN26": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN26", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT26", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX27_2->DSP_0_OPMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE2", - "is_directional": "1", - "src_wire": "DSP_IMUX27_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX45_0->DSP_1_A20": { - "can_invert": "0", - "dst_wire": "DSP_1_A20", - "is_directional": "1", - "src_wire": "DSP_IMUX45_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_1", - "is_directional": "1", - "src_wire": "DSP_0_P25", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX11_1->DSP_1_A5": { - "can_invert": "0", - "dst_wire": "DSP_1_A5", - "is_directional": "1", - "src_wire": "DSP_IMUX11_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_CED": { - "can_invert": "0", - "dst_wire": "DSP_1_CED", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_3", - "is_directional": "1", - "src_wire": "DSP_1_P13", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX35_3->DSP_0_C13": { - "can_invert": "0", - "dst_wire": "DSP_0_C13", - "is_directional": "1", - "src_wire": "DSP_IMUX35_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_1", - "is_directional": "1", - "src_wire": "DSP_1_P6", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX7_4->DSP_0_A17": { - "can_invert": "0", - "dst_wire": "DSP_0_A17", - "is_directional": "1", - "src_wire": "DSP_IMUX7_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "DSP_1_P37", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "DSP_0_P18", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D24": { - "can_invert": "0", - "dst_wire": "DSP_0_D24", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP3_4->DSP_0_D18": { - "can_invert": "0", - "dst_wire": "DSP_0_D18", - "is_directional": "1", - "src_wire": "DSP_BYP3_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "DSP_0_P21", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D20": { - "can_invert": "0", - "dst_wire": "DSP_1_D20", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP5_3->DSP_0_D13": { - "can_invert": "0", - "dst_wire": "DSP_0_D13", - "is_directional": "1", - "src_wire": "DSP_BYP5_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D9": { - "can_invert": "0", - "dst_wire": "DSP_1_D9", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX40_1->DSP_0_CEA1": { - "can_invert": "0", - "dst_wire": "DSP_0_CEA1", - "is_directional": "1", - "src_wire": "DSP_IMUX40_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_CLK0_3->DSP_1_CLK": { - "can_invert": "0", - "dst_wire": "DSP_1_CLK", - "is_directional": "1", - "src_wire": "DSP_CLK0_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP0_0->DSP_0_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_BYP0_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D1": { - "can_invert": "0", - "dst_wire": "DSP_0_D1", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX3_3->DSP_0_B13": { - "can_invert": "0", - "dst_wire": "DSP_0_B13", - "is_directional": "1", - "src_wire": "DSP_IMUX3_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D8": { - "can_invert": "0", - "dst_wire": "DSP_1_D8", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT1->DSP_PCOUT1": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT1", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT18->DSP_1_PCIN18": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN18", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT18", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX36_1->DSP_0_B6": { - "can_invert": "0", - "dst_wire": "DSP_0_B6", - "is_directional": "1", - "src_wire": "DSP_IMUX36_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D23": { - "can_invert": "0", - "dst_wire": "DSP_1_D23", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT28->DSP_ACOUT28": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT28", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT28", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT42->DSP_PCOUT42": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT42", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT42", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX28_1->DSP_1_B6": { - "can_invert": "0", - "dst_wire": "DSP_1_B6", - "is_directional": "1", - "src_wire": "DSP_IMUX28_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D17": { - "can_invert": "0", - "dst_wire": "DSP_1_D17", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX25_2->DSP_1_C11": { - "can_invert": "0", - "dst_wire": "DSP_1_C11", - "is_directional": "1", - "src_wire": "DSP_IMUX25_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT22->DSP_1_ACIN22": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN22", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT22", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX7_0->DSP_0_A21": { - "can_invert": "0", - "dst_wire": "DSP_0_A21", - "is_directional": "1", - "src_wire": "DSP_IMUX7_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX7_1->DSP_0_A25": { - "can_invert": "0", - "dst_wire": "DSP_0_A25", - "is_directional": "1", - "src_wire": "DSP_IMUX7_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX32_3->DSP_0_C35": { - "can_invert": "0", - "dst_wire": "DSP_0_C35", - "is_directional": "1", - "src_wire": "DSP_IMUX32_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX28_3->DSP_1_OPMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE0", - "is_directional": "1", - "src_wire": "DSP_IMUX28_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D16": { - "can_invert": "0", - "dst_wire": "DSP_0_D16", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL0_0->DSP_0_RSTP": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTP", - "is_directional": "1", - "src_wire": "DSP_CTRL0_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX17_2->DSP_0_A11": { - "can_invert": "0", - "dst_wire": "DSP_0_A11", - "is_directional": "1", - "src_wire": "DSP_IMUX17_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_2", - "is_directional": "1", - "src_wire": "DSP_0_P30", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT31->DSP_PCOUT31": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT31", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT31", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "DSP_1_P43", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN7_3->DSP_1_D23": { - "can_invert": "0", - "dst_wire": "DSP_1_D23", - "is_directional": "1", - "src_wire": "DSP_FAN7_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX14_1->DSP_1_C24": { - "can_invert": "0", - "dst_wire": "DSP_1_C24", - "is_directional": "1", - "src_wire": "DSP_IMUX14_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX37_0->DSP_0_C2": { - "can_invert": "0", - "dst_wire": "DSP_0_C2", - "is_directional": "1", - "src_wire": "DSP_IMUX37_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT45->DSP_PCOUT45": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT45", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT45", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_4", - "is_directional": "1", - "src_wire": "DSP_1_P17", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX3_2->DSP_0_C9": { - "can_invert": "0", - "dst_wire": "DSP_0_C9", - "is_directional": "1", - "src_wire": "DSP_IMUX3_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D11": { - "can_invert": "0", - "dst_wire": "DSP_0_D11", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D6": { - "can_invert": "0", - "dst_wire": "DSP_0_D6", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT34->DSP_1_PCIN34": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN34", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT34", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_2", - "is_directional": "1", - "src_wire": "DSP_1_P28", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN6_0->DSP_1_D1": { - "can_invert": "0", - "dst_wire": "DSP_1_D1", - "is_directional": "1", - "src_wire": "DSP_FAN6_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX23_1->DSP_0_A4": { - "can_invert": "0", - "dst_wire": "DSP_0_A4", - "is_directional": "1", - "src_wire": "DSP_IMUX23_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX34_4->DSP_0_C44": { - "can_invert": "0", - "dst_wire": "DSP_0_C44", - "is_directional": "1", - "src_wire": "DSP_IMUX34_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX38_4->DSP_0_C36": { - "can_invert": "0", - "dst_wire": "DSP_0_C36", - "is_directional": "1", - "src_wire": "DSP_IMUX38_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX22_0->DSP_0_B0": { - "can_invert": "0", - "dst_wire": "DSP_0_B0", - "is_directional": "1", - "src_wire": "DSP_IMUX22_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX44_3->DSP_1_A14": { - "can_invert": "0", - "dst_wire": "DSP_1_A14", - "is_directional": "1", - "src_wire": "DSP_IMUX44_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX4_1->DSP_1_A27": { - "can_invert": "0", - "dst_wire": "DSP_1_A27", - "is_directional": "1", - "src_wire": "DSP_IMUX4_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN5_0->DSP_1_D2": { - "can_invert": "0", - "dst_wire": "DSP_1_D2", - "is_directional": "1", - "src_wire": "DSP_FAN5_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT10->DSP_ACOUT10": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT10", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT10", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT4->DSP_1_PCIN4": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN4", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "DSP_0_P26", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D21": { - "can_invert": "0", - "dst_wire": "DSP_1_D21", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX13_1->DSP_1_A6": { - "can_invert": "0", - "dst_wire": "DSP_1_A6", - "is_directional": "1", - "src_wire": "DSP_IMUX13_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT0->DSP_1_BCIN0": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN0", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX45_1->DSP_1_A24": { - "can_invert": "0", - "dst_wire": "DSP_1_A24", - "is_directional": "1", - "src_wire": "DSP_IMUX45_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX41_3->DSP_1_B12": { - "can_invert": "0", - "dst_wire": "DSP_1_B12", - "is_directional": "1", - "src_wire": "DSP_IMUX41_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT3->DSP_1_PCIN3": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN3", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_3", - "is_directional": "1", - "src_wire": "DSP_1_P34", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN2_2->DSP_1_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE4", - "is_directional": "1", - "src_wire": "DSP_FAN2_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX42_2->DSP_1_B9": { - "can_invert": "0", - "dst_wire": "DSP_1_B9", - "is_directional": "1", - "src_wire": "DSP_IMUX42_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX4_3->DSP_1_A15": { - "can_invert": "0", - "dst_wire": "DSP_1_A15", - "is_directional": "1", - "src_wire": "DSP_IMUX4_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D1": { - "can_invert": "0", - "dst_wire": "DSP_0_D1", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX4_4->DSP_1_A19": { - "can_invert": "0", - "dst_wire": "DSP_1_A19", - "is_directional": "1", - "src_wire": "DSP_IMUX4_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_3", - "is_directional": "1", - "src_wire": "DSP_1_P35", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP4_3->DSP_1_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_BYP4_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX21_2->DSP_0_A10": { - "can_invert": "0", - "dst_wire": "DSP_0_A10", - "is_directional": "1", - "src_wire": "DSP_IMUX21_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_3", - "is_directional": "1", - "src_wire": "DSP_0_P33", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "DSP_1_P18", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX27_4->DSP_1_C17": { - "can_invert": "0", - "dst_wire": "DSP_1_C17", - "is_directional": "1", - "src_wire": "DSP_IMUX27_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT7->DSP_BCOUT7": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT7", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT7", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT25->DSP_ACOUT25": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT25", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT25", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE0", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTD", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX10_2->DSP_1_C29": { - "can_invert": "0", - "dst_wire": "DSP_1_C29", - "is_directional": "1", - "src_wire": "DSP_IMUX10_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT0->DSP_PCOUT0": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT0", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT0", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL0_2->DSP_0_RSTB": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTB", - "is_directional": "1", - "src_wire": "DSP_CTRL0_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX19_1->DSP_0_A5": { - "can_invert": "0", - "dst_wire": "DSP_0_A5", - "is_directional": "1", - "src_wire": "DSP_IMUX19_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX30_1->DSP_1_B4": { - "can_invert": "0", - "dst_wire": "DSP_1_B4", - "is_directional": "1", - "src_wire": "DSP_IMUX30_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX1_4->DSP_0_C19": { - "can_invert": "0", - "dst_wire": "DSP_0_C19", - "is_directional": "1", - "src_wire": "DSP_IMUX1_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE4", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D12": { - "can_invert": "0", - "dst_wire": "DSP_0_D12", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT14->DSP_PCOUT14": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT14", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT14", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_2", - "is_directional": "1", - "src_wire": "DSP_0_OVERFLOW", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT9->DSP_ACOUT9": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT9", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT9", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX34_0->DSP_0_B1": { - "can_invert": "0", - "dst_wire": "DSP_0_B1", - "is_directional": "1", - "src_wire": "DSP_IMUX34_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP2_4->DSP_1_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_BYP2_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D22": { - "can_invert": "0", - "dst_wire": "DSP_0_D22", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_4", - "is_directional": "1", - "src_wire": "DSP_1_P39", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D15": { - "can_invert": "0", - "dst_wire": "DSP_0_D15", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT26->DSP_ACOUT26": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT26", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT26", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX20_2->DSP_0_OPMODE4": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE4", - "is_directional": "1", - "src_wire": "DSP_IMUX20_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX43_2->DSP_1_C9": { - "can_invert": "0", - "dst_wire": "DSP_1_C9", - "is_directional": "1", - "src_wire": "DSP_IMUX43_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX32_1->DSP_0_C27": { - "can_invert": "0", - "dst_wire": "DSP_0_C27", - "is_directional": "1", - "src_wire": "DSP_IMUX32_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_0", - "is_directional": "1", - "src_wire": "DSP_1_P0", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D19": { - "can_invert": "0", - "dst_wire": "DSP_0_D19", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX6_1->DSP_0_A27": { - "can_invert": "0", - "dst_wire": "DSP_0_A27", - "is_directional": "1", - "src_wire": "DSP_IMUX6_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX32_2->DSP_0_C31": { - "can_invert": "0", - "dst_wire": "DSP_0_C31", - "is_directional": "1", - "src_wire": "DSP_IMUX32_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN3_2->DSP_1_D8": { - "can_invert": "0", - "dst_wire": "DSP_1_D8", - "is_directional": "1", - "src_wire": "DSP_FAN3_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT41->DSP_1_PCIN41": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN41", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT41", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D15": { - "can_invert": "0", - "dst_wire": "DSP_0_D15", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT24->DSP_1_ACIN24": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN24", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT24", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT12->DSP_ACOUT12": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT12", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT12", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT14->DSP_BCOUT14": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT14", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT14", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX26_2->DSP_1_CEP": { - "can_invert": "0", - "dst_wire": "DSP_1_CEP", - "is_directional": "1", - "src_wire": "DSP_IMUX26_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTD", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT27->DSP_PCOUT27": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT27", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT27", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX17_4->DSP_1_OPMODE4": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE4", - "is_directional": "1", - "src_wire": "DSP_IMUX17_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B2_2", - "is_directional": "1", - "src_wire": "DSP_1_P30", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX25_4->DSP_1_C47": { - "can_invert": "0", - "dst_wire": "DSP_1_C47", - "is_directional": "1", - "src_wire": "DSP_IMUX25_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D7": { - "can_invert": "0", - "dst_wire": "DSP_1_D7", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "DSP_1_P36", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX33_2->DSP_0_C11": { - "can_invert": "0", - "dst_wire": "DSP_0_C11", - "is_directional": "1", - "src_wire": "DSP_IMUX33_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D0": { - "can_invert": "0", - "dst_wire": "DSP_1_D0", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT9->DSP_1_BCIN9": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN9", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT9", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT25->DSP_1_PCIN25": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN25", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT25", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX8_3->DSP_1_CEB1": { - "can_invert": "0", - "dst_wire": "DSP_1_CEB1", - "is_directional": "1", - "src_wire": "DSP_IMUX8_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX34_2->DSP_0_CEP": { - "can_invert": "0", - "dst_wire": "DSP_0_CEP", - "is_directional": "1", - "src_wire": "DSP_IMUX34_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT15->DSP_1_BCIN15": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN15", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT15", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN0_4->DSP_1_ALUMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE2", - "is_directional": "1", - "src_wire": "DSP_FAN0_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "DSP_0_P43", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT10->DSP_PCOUT10": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT10", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT10", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT36->DSP_PCOUT36": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT36", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT36", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX7_2->DSP_0_A29": { - "can_invert": "0", - "dst_wire": "DSP_0_A29", - "is_directional": "1", - "src_wire": "DSP_IMUX7_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D9": { - "can_invert": "0", - "dst_wire": "DSP_0_D9", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP3_3->DSP_0_D14": { - "can_invert": "0", - "dst_wire": "DSP_0_D14", - "is_directional": "1", - "src_wire": "DSP_BYP3_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_0", - "is_directional": "1", - "src_wire": "DSP_0_P20", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT23->DSP_1_ACIN23": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN23", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT23", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "DSP_1_P44", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT4->DSP_1_BCIN4": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN4", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT3->DSP_PCOUT3": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT3", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT17->DSP_1_PCIN17": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN17", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT17", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT40->DSP_PCOUT40": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT40", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT40", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT14->DSP_1_PCIN14": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN14", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT14", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX38_2->DSP_0_OPMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE3", - "is_directional": "1", - "src_wire": "DSP_IMUX38_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT6->DSP_1_BCIN6": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN6", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT6", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT16->DSP_1_PCIN16": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN16", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT16", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT7->DSP_1_BCIN7": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN7", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT7", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_4", - "is_directional": "1", - "src_wire": "DSP_0_P17", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "DSP_1_P8", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D11": { - "can_invert": "0", - "dst_wire": "DSP_0_D11", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN1_3->DSP_0_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE4", - "is_directional": "1", - "src_wire": "DSP_FAN1_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX23_4->DSP_1_RSTINMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTINMODE", - "is_directional": "1", - "src_wire": "DSP_IMUX23_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D10": { - "can_invert": "0", - "dst_wire": "DSP_0_D10", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN1_0->DSP_1_D20": { - "can_invert": "0", - "dst_wire": "DSP_1_D20", - "is_directional": "1", - "src_wire": "DSP_FAN1_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT3->DSP_1_ACIN3": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN3", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT16->DSP_BCOUT16": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT16", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT16", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT17->DSP_PCOUT17": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT17", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT17", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX42_4->DSP_1_B16": { - "can_invert": "0", - "dst_wire": "DSP_1_B16", - "is_directional": "1", - "src_wire": "DSP_IMUX42_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTALLCARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX15_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT4->DSP_1_ACIN4": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN4", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT2->DSP_BCOUT2": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT2", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT2", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP5_4->DSP_0_D17": { - "can_invert": "0", - "dst_wire": "DSP_0_D17", - "is_directional": "1", - "src_wire": "DSP_BYP5_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT29->DSP_ACOUT29": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT29", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT29", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX20_4->DSP_0_C38": { - "can_invert": "0", - "dst_wire": "DSP_0_C38", - "is_directional": "1", - "src_wire": "DSP_IMUX20_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN6_3->DSP_1_D13": { - "can_invert": "0", - "dst_wire": "DSP_1_D13", - "is_directional": "1", - "src_wire": "DSP_FAN6_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX42_3->DSP_0_B14": { - "can_invert": "0", - "dst_wire": "DSP_0_B14", - "is_directional": "1", - "src_wire": "DSP_IMUX42_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_1", - "is_directional": "1", - "src_wire": "DSP_1_P5", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D23": { - "can_invert": "0", - "dst_wire": "DSP_0_D23", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "DSP_1_P40", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX23_2->DSP_0_A8": { - "can_invert": "0", - "dst_wire": "DSP_0_A8", - "is_directional": "1", - "src_wire": "DSP_IMUX23_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX37_2->DSP_0_C10": { - "can_invert": "0", - "dst_wire": "DSP_0_C10", - "is_directional": "1", - "src_wire": "DSP_IMUX37_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX26_0->DSP_1_B1": { - "can_invert": "0", - "dst_wire": "DSP_1_B1", - "is_directional": "1", - "src_wire": "DSP_IMUX26_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT2->DSP_1_ACIN2": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN2", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX16_2->DSP_0_B11": { - "can_invert": "0", - "dst_wire": "DSP_0_B11", - "is_directional": "1", - "src_wire": "DSP_IMUX16_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D23": { - "can_invert": "0", - "dst_wire": "DSP_1_D23", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT28->DSP_1_ACIN28": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN28", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT28", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D19": { - "can_invert": "0", - "dst_wire": "DSP_1_D19", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX41_2->DSP_0_CECTRL": { - "can_invert": "0", - "dst_wire": "DSP_0_CECTRL", - "is_directional": "1", - "src_wire": "DSP_IMUX41_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX0_3->DSP_1_B15": { - "can_invert": "0", - "dst_wire": "DSP_1_B15", - "is_directional": "1", - "src_wire": "DSP_IMUX0_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX14_2->DSP_1_B8": { - "can_invert": "0", - "dst_wire": "DSP_1_B8", - "is_directional": "1", - "src_wire": "DSP_IMUX14_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT35->DSP_PCOUT35": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT35", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT35", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT17->DSP_1_ACIN17": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN17", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT17", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX13_0->DSP_1_A2": { - "can_invert": "0", - "dst_wire": "DSP_1_A2", - "is_directional": "1", - "src_wire": "DSP_IMUX13_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX39_2->DSP_0_C8": { - "can_invert": "0", - "dst_wire": "DSP_0_C8", - "is_directional": "1", - "src_wire": "DSP_IMUX39_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "DSP_1_P12", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT14->DSP_1_ACIN14": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN14", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT14", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D18": { - "can_invert": "0", - "dst_wire": "DSP_1_D18", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT12->DSP_BCOUT12": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT12", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT12", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN6_2->DSP_1_D9": { - "can_invert": "0", - "dst_wire": "DSP_1_D9", - "is_directional": "1", - "src_wire": "DSP_FAN6_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX21_4->DSP_0_C18": { - "can_invert": "0", - "dst_wire": "DSP_0_C18", - "is_directional": "1", - "src_wire": "DSP_IMUX21_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX21_0->DSP_0_A2": { - "can_invert": "0", - "dst_wire": "DSP_0_A2", - "is_directional": "1", - "src_wire": "DSP_IMUX21_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX31_4->DSP_1_C16": { - "can_invert": "0", - "dst_wire": "DSP_1_C16", - "is_directional": "1", - "src_wire": "DSP_IMUX31_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX18_1->DSP_0_B5": { - "can_invert": "0", - "dst_wire": "DSP_0_B5", - "is_directional": "1", - "src_wire": "DSP_IMUX18_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE2", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT33->DSP_PCOUT33": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT33", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT33", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX36_3->DSP_1_OPMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE2", - "is_directional": "1", - "src_wire": "DSP_IMUX36_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN4_4->DSP_1_D19": { - "can_invert": "0", - "dst_wire": "DSP_1_D19", - "is_directional": "1", - "src_wire": "DSP_FAN4_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT22->DSP_ACOUT22": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT22", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT22", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX13_2->DSP_1_A10": { - "can_invert": "0", - "dst_wire": "DSP_1_A10", - "is_directional": "1", - "src_wire": "DSP_IMUX13_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D24": { - "can_invert": "0", - "dst_wire": "DSP_0_D24", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX16_4->DSP_1_OPMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE3", - "is_directional": "1", - "src_wire": "DSP_IMUX16_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX9_0->DSP_1_A3": { - "can_invert": "0", - "dst_wire": "DSP_1_A3", - "is_directional": "1", - "src_wire": "DSP_IMUX9_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX40_2->DSP_0_CEC": { - "can_invert": "0", - "dst_wire": "DSP_0_CEC", - "is_directional": "1", - "src_wire": "DSP_IMUX40_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE0", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_0_CEAD", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT20->DSP_1_PCIN20": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN20", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT20", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX31_2->DSP_1_C8": { - "can_invert": "0", - "dst_wire": "DSP_1_C8", - "is_directional": "1", - "src_wire": "DSP_IMUX31_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT16->DSP_PCOUT16": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT16", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT16", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT6->DSP_1_ACIN6": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN6", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT6", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX15_3->DSP_1_CARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX15_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "DSP_0_P19", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_3", - "is_directional": "1", - "src_wire": "DSP_0_P34", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX16_1->DSP_0_B7": { - "can_invert": "0", - "dst_wire": "DSP_0_B7", - "is_directional": "1", - "src_wire": "DSP_IMUX16_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP6_2->DSP_0_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE3", - "is_directional": "1", - "src_wire": "DSP_BYP6_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT9->DSP_1_PCIN9": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN9", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT9", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX33_4->DSP_0_C47": { - "can_invert": "0", - "dst_wire": "DSP_0_C47", - "is_directional": "1", - "src_wire": "DSP_IMUX33_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B1_2", - "is_directional": "1", - "src_wire": "DSP_1_P9", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX31_1->DSP_1_C4": { - "can_invert": "0", - "dst_wire": "DSP_1_C4", - "is_directional": "1", - "src_wire": "DSP_IMUX31_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_2", - "is_directional": "1", - "src_wire": "DSP_1_P29", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "DSP_0_P22", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX30_4->DSP_1_C36": { - "can_invert": "0", - "dst_wire": "DSP_1_C36", - "is_directional": "1", - "src_wire": "DSP_IMUX30_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT14->DSP_ACOUT14": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT14", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT14", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX1_1->DSP_0_CEB2": { - "can_invert": "0", - "dst_wire": "DSP_0_CEB2", - "is_directional": "1", - "src_wire": "DSP_IMUX1_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D17": { - "can_invert": "0", - "dst_wire": "DSP_0_D17", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX23_3->DSP_0_CARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX23_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX27_1->DSP_1_C5": { - "can_invert": "0", - "dst_wire": "DSP_1_C5", - "is_directional": "1", - "src_wire": "DSP_IMUX27_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN3_1->DSP_1_D4": { - "can_invert": "0", - "dst_wire": "DSP_1_D4", - "is_directional": "1", - "src_wire": "DSP_FAN3_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX14_0->DSP_1_B0": { - "can_invert": "0", - "dst_wire": "DSP_1_B0", - "is_directional": "1", - "src_wire": "DSP_IMUX14_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT26->DSP_1_PCIN26": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN26", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT26", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX12_4->DSP_1_C38": { - "can_invert": "0", - "dst_wire": "DSP_1_C38", - "is_directional": "1", - "src_wire": "DSP_IMUX12_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX5_4->DSP_1_A17": { - "can_invert": "0", - "dst_wire": "DSP_1_A17", - "is_directional": "1", - "src_wire": "DSP_IMUX5_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT0->DSP_ACOUT0": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT0", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT0", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL0_3->DSP_1_RSTC": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTC", - "is_directional": "1", - "src_wire": "DSP_CTRL0_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D14": { - "can_invert": "0", - "dst_wire": "DSP_0_D14", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT3->DSP_ACOUT3": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT3", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX41_0->DSP_1_C3": { - "can_invert": "0", - "dst_wire": "DSP_1_C3", - "is_directional": "1", - "src_wire": "DSP_IMUX41_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN7_0->DSP_1_D24": { - "can_invert": "0", - "dst_wire": "DSP_1_D24", - "is_directional": "1", - "src_wire": "DSP_FAN7_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT41->DSP_PCOUT41": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT41", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT41", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP2_3->DSP_0_D23": { - "can_invert": "0", - "dst_wire": "DSP_0_D23", - "is_directional": "1", - "src_wire": "DSP_BYP2_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE1", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX26_4->DSP_1_C44": { - "can_invert": "0", - "dst_wire": "DSP_1_C44", - "is_directional": "1", - "src_wire": "DSP_IMUX26_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP7_4->DSP_0_D16": { - "can_invert": "0", - "dst_wire": "DSP_0_D16", - "is_directional": "1", - "src_wire": "DSP_BYP7_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT1->DSP_1_PCIN1": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN1", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT1", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT36->DSP_1_PCIN36": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN36", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT36", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX40_4->DSP_1_ALUMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE1", - "is_directional": "1", - "src_wire": "DSP_IMUX40_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D8": { - "can_invert": "0", - "dst_wire": "DSP_1_D8", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT38->DSP_PCOUT38": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT38", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT38", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT5->DSP_ACOUT5": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT5", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT5", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYCASCIN", - "is_directional": "1", - "src_wire": "DSP_0_CARRYCASCOUT", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT23->DSP_1_PCIN23": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN23", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT23", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D21": { - "can_invert": "0", - "dst_wire": "DSP_0_D21", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX28_0->DSP_1_B2": { - "can_invert": "0", - "dst_wire": "DSP_1_B2", - "is_directional": "1", - "src_wire": "DSP_IMUX28_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX47_4->DSP_0_A16": { - "can_invert": "0", - "dst_wire": "DSP_0_A16", - "is_directional": "1", - "src_wire": "DSP_IMUX47_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D6": { - "can_invert": "0", - "dst_wire": "DSP_1_D6", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP2_0->DSP_0_D24": { - "can_invert": "0", - "dst_wire": "DSP_0_D24", - "is_directional": "1", - "src_wire": "DSP_BYP2_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { - "can_invert": "0", - "dst_wire": "DSP_CARRYCASCOUT", - "is_directional": "1", - "src_wire": "DSP_1_CARRYCASCOUT", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT2->DSP_1_PCIN2": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN2", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT2", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN6_1->DSP_1_D5": { - "can_invert": "0", - "dst_wire": "DSP_1_D5", - "is_directional": "1", - "src_wire": "DSP_FAN6_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT13->DSP_BCOUT13": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT13", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT13", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX46_1->DSP_0_A26": { - "can_invert": "0", - "dst_wire": "DSP_0_A26", - "is_directional": "1", - "src_wire": "DSP_IMUX46_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL1", - "is_directional": "1", - "src_wire": "DSP_IMUX28_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_RSTD": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTD", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D18": { - "can_invert": "0", - "dst_wire": "DSP_1_D18", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN0_1->DSP_0_CED": { - "can_invert": "0", - "dst_wire": "DSP_0_CED", - "is_directional": "1", - "src_wire": "DSP_FAN0_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D22": { - "can_invert": "0", - "dst_wire": "DSP_1_D22", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_4", - "is_directional": "1", - "src_wire": "DSP_1_P45", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL0_1->DSP_0_RSTC": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTC", - "is_directional": "1", - "src_wire": "DSP_CTRL0_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX2_0->DSP_1_C42": { - "can_invert": "0", - "dst_wire": "DSP_1_C42", - "is_directional": "1", - "src_wire": "DSP_IMUX2_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX44_1->DSP_1_A26": { - "can_invert": "0", - "dst_wire": "DSP_1_A26", - "is_directional": "1", - "src_wire": "DSP_IMUX44_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B8_2", - "is_directional": "1", - "src_wire": "DSP_1_OVERFLOW", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT2->DSP_PCOUT2": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT2", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT2", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE3", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX18_3->DSP_0_C33": { - "can_invert": "0", - "dst_wire": "DSP_0_C33", - "is_directional": "1", - "src_wire": "DSP_IMUX18_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX19_3->DSP_1_CEM": { - "can_invert": "0", - "dst_wire": "DSP_1_CEM", - "is_directional": "1", - "src_wire": "DSP_IMUX19_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE4", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX15_2->DSP_1_A8": { - "can_invert": "0", - "dst_wire": "DSP_1_A8", - "is_directional": "1", - "src_wire": "DSP_IMUX15_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT42->DSP_1_PCIN42": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN42", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT42", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "DSP_0_P36", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP5_0->DSP_0_D1": { - "can_invert": "0", - "dst_wire": "DSP_0_D1", - "is_directional": "1", - "src_wire": "DSP_BYP5_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D3": { - "can_invert": "0", - "dst_wire": "DSP_0_D3", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D20": { - "can_invert": "0", - "dst_wire": "DSP_0_D20", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT19->DSP_1_ACIN19": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN19", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT19", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE0", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX0_1->DSP_0_CEA2": { - "can_invert": "0", - "dst_wire": "DSP_0_CEA2", - "is_directional": "1", - "src_wire": "DSP_IMUX0_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D17": { - "can_invert": "0", - "dst_wire": "DSP_0_D17", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_1", - "is_directional": "1", - "src_wire": "DSP_0_P4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL1", - "is_directional": "1", - "src_wire": "DSP_IMUX14_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D10": { - "can_invert": "0", - "dst_wire": "DSP_0_D10", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX1_0->DSP_0_C3": { - "can_invert": "0", - "dst_wire": "DSP_0_C3", - "is_directional": "1", - "src_wire": "DSP_IMUX1_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE3", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTALLCARRYIN", - "is_directional": "1", - "src_wire": "DSP_IMUX2_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX2_4->DSP_1_B17": { - "can_invert": "0", - "dst_wire": "DSP_1_B17", - "is_directional": "1", - "src_wire": "DSP_IMUX2_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT10->DSP_1_PCIN10": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN10", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT10", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX22_2->DSP_0_B8": { - "can_invert": "0", - "dst_wire": "DSP_0_B8", - "is_directional": "1", - "src_wire": "DSP_IMUX22_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "DSP_1_P33", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX8_0->DSP_1_C41": { - "can_invert": "0", - "dst_wire": "DSP_1_C41", - "is_directional": "1", - "src_wire": "DSP_IMUX8_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_INMODE4": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE4", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT21->DSP_ACOUT21": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT21", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT21", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "DSP_1_P41", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN5_2->DSP_1_D10": { - "can_invert": "0", - "dst_wire": "DSP_1_D10", - "is_directional": "1", - "src_wire": "DSP_FAN5_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP1_3->DSP_0_D15": { - "can_invert": "0", - "dst_wire": "DSP_0_D15", - "is_directional": "1", - "src_wire": "DSP_BYP1_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT4->DSP_ACOUT4": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT4", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX37_3->DSP_0_C14": { - "can_invert": "0", - "dst_wire": "DSP_0_C14", - "is_directional": "1", - "src_wire": "DSP_IMUX37_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX24_3->DSP_1_C35": { - "can_invert": "0", - "dst_wire": "DSP_1_C35", - "is_directional": "1", - "src_wire": "DSP_IMUX24_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_0", - "is_directional": "1", - "src_wire": "DSP_0_P1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX15_1->DSP_1_A4": { - "can_invert": "0", - "dst_wire": "DSP_1_A4", - "is_directional": "1", - "src_wire": "DSP_IMUX15_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_0", - "is_directional": "1", - "src_wire": "DSP_1_P23", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT10->DSP_1_ACIN10": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN10", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT10", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX35_1->DSP_0_C5": { - "can_invert": "0", - "dst_wire": "DSP_0_C5", - "is_directional": "1", - "src_wire": "DSP_IMUX35_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D16": { - "can_invert": "0", - "dst_wire": "DSP_1_D16", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX34_1->DSP_0_C25": { - "can_invert": "0", - "dst_wire": "DSP_0_C25", - "is_directional": "1", - "src_wire": "DSP_IMUX34_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX11_3->DSP_1_CECTRL": { - "can_invert": "0", - "dst_wire": "DSP_1_CECTRL", - "is_directional": "1", - "src_wire": "DSP_IMUX11_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_2", - "is_directional": "1", - "src_wire": "DSP_0_P9", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT11->DSP_1_PCIN11": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN11", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT11", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT16->DSP_ACOUT16": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT16", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT16", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX43_1->DSP_0_RSTCTRL": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTCTRL", - "is_directional": "1", - "src_wire": "DSP_IMUX43_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "DSP_1_P46", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX24_2->DSP_1_C31": { - "can_invert": "0", - "dst_wire": "DSP_1_C31", - "is_directional": "1", - "src_wire": "DSP_IMUX24_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "DSP_0_CARRYOUT0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX9_1->DSP_1_A7": { - "can_invert": "0", - "dst_wire": "DSP_1_A7", - "is_directional": "1", - "src_wire": "DSP_IMUX9_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_2", - "is_directional": "1", - "src_wire": "DSP_0_PATTERNDETECT", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT30->DSP_1_PCIN30": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN30", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT30", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT6->DSP_PCOUT6": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT6", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT6", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX23_0->DSP_0_A0": { - "can_invert": "0", - "dst_wire": "DSP_0_A0", - "is_directional": "1", - "src_wire": "DSP_IMUX23_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN7_2->DSP_0_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_FAN7_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT13->DSP_ACOUT13": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT13", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT13", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX38_1->DSP_0_B4": { - "can_invert": "0", - "dst_wire": "DSP_0_B4", - "is_directional": "1", - "src_wire": "DSP_IMUX38_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT26->DSP_PCOUT26": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT26", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT26", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN2_0->DSP_0_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_FAN2_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT4->DSP_BCOUT4": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT4", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT4", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D5": { - "can_invert": "0", - "dst_wire": "DSP_1_D5", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_1_CEAD", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP2_2->DSP_0_CARRYINSEL2": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL2", - "is_directional": "1", - "src_wire": "DSP_BYP2_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT44->DSP_PCOUT44": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT44", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT44", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT17->DSP_1_BCIN17": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN17", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT17", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP2_1->DSP_1_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE1", - "is_directional": "1", - "src_wire": "DSP_BYP2_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE2", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT25->DSP_PCOUT25": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT25", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT25", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT7->DSP_1_ACIN7": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN7", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT7", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D15": { - "can_invert": "0", - "dst_wire": "DSP_1_D15", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT24->DSP_ACOUT24": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT24", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT24", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_1", - "is_directional": "1", - "src_wire": "DSP_1_P27", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D16": { - "can_invert": "0", - "dst_wire": "DSP_1_D16", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_2", - "is_directional": "1", - "src_wire": "DSP_0_P10", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX37_1->DSP_0_C6": { - "can_invert": "0", - "dst_wire": "DSP_0_C6", - "is_directional": "1", - "src_wire": "DSP_IMUX37_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_4", - "is_directional": "1", - "src_wire": "DSP_0_P16", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D5": { - "can_invert": "0", - "dst_wire": "DSP_0_D5", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "DSP_0_P7", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT47->DSP_1_PCIN47": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN47", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT47", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX24_1->DSP_1_C27": { - "can_invert": "0", - "dst_wire": "DSP_1_C27", - "is_directional": "1", - "src_wire": "DSP_IMUX24_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN4_2->DSP_1_D11": { - "can_invert": "0", - "dst_wire": "DSP_1_D11", - "is_directional": "1", - "src_wire": "DSP_FAN4_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX36_0->DSP_0_B2": { - "can_invert": "0", - "dst_wire": "DSP_0_B2", - "is_directional": "1", - "src_wire": "DSP_IMUX36_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT10->DSP_1_BCIN10": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN10", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT10", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP3_2->DSP_0_D10": { - "can_invert": "0", - "dst_wire": "DSP_0_D10", - "is_directional": "1", - "src_wire": "DSP_BYP3_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX7_3->DSP_0_A13": { - "can_invert": "0", - "dst_wire": "DSP_0_A13", - "is_directional": "1", - "src_wire": "DSP_IMUX7_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX28_2->DSP_1_C30": { - "can_invert": "0", - "dst_wire": "DSP_1_C30", - "is_directional": "1", - "src_wire": "DSP_IMUX28_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX18_4->DSP_0_C39": { - "can_invert": "0", - "dst_wire": "DSP_0_C39", - "is_directional": "1", - "src_wire": "DSP_IMUX18_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX25_1->DSP_1_C7": { - "can_invert": "0", - "dst_wire": "DSP_1_C7", - "is_directional": "1", - "src_wire": "DSP_IMUX25_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT15->DSP_BCOUT15": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT15", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT15", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D17": { - "can_invert": "0", - "dst_wire": "DSP_1_D17", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D11": { - "can_invert": "0", - "dst_wire": "DSP_1_D11", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP7_2->DSP_0_D8": { - "can_invert": "0", - "dst_wire": "DSP_0_D8", - "is_directional": "1", - "src_wire": "DSP_BYP7_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D19": { - "can_invert": "0", - "dst_wire": "DSP_0_D19", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX35_4->DSP_0_C17": { - "can_invert": "0", - "dst_wire": "DSP_0_C17", - "is_directional": "1", - "src_wire": "DSP_IMUX35_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_INMODE2": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE2", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX40_0->DSP_0_B3": { - "can_invert": "0", - "dst_wire": "DSP_0_B3", - "is_directional": "1", - "src_wire": "DSP_IMUX40_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B22_2", - "is_directional": "1", - "src_wire": "DSP_0_P31", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX4_2->DSP_0_C30": { - "can_invert": "0", - "dst_wire": "DSP_0_C30", - "is_directional": "1", - "src_wire": "DSP_IMUX4_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_2", - "is_directional": "1", - "src_wire": "DSP_0_P8", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_0_CEAD", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_D0": { - "can_invert": "0", - "dst_wire": "DSP_0_D0", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B11_3", - "is_directional": "1", - "src_wire": "DSP_1_CARRYOUT1", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D6": { - "can_invert": "0", - "dst_wire": "DSP_1_D6", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT43->DSP_1_PCIN43": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN43", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT43", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX1_3->DSP_1_B13": { - "can_invert": "0", - "dst_wire": "DSP_1_B13", - "is_directional": "1", - "src_wire": "DSP_IMUX1_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B7_3", - "is_directional": "1", - "src_wire": "DSP_1_P32", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT8->DSP_PCOUT8": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT8", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT8", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D2": { - "can_invert": "0", - "dst_wire": "DSP_0_D2", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_2", - "is_directional": "1", - "src_wire": "DSP_0_P11", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "DSP_1_P10", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE0", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "DSP_0_P2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "DSP_0_P3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT39->DSP_PCOUT39": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT39", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT39", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT5->DSP_BCOUT5": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT5", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT5", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN5_1->DSP_1_D6": { - "can_invert": "0", - "dst_wire": "DSP_1_D6", - "is_directional": "1", - "src_wire": "DSP_FAN5_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT20->DSP_1_ACIN20": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN20", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT20", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX10_4->DSP_1_C39": { - "can_invert": "0", - "dst_wire": "DSP_1_C39", - "is_directional": "1", - "src_wire": "DSP_IMUX10_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX4_0->DSP_1_A23": { - "can_invert": "0", - "dst_wire": "DSP_1_A23", - "is_directional": "1", - "src_wire": "DSP_IMUX4_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX27_3->DSP_1_C13": { - "can_invert": "0", - "dst_wire": "DSP_1_C13", - "is_directional": "1", - "src_wire": "DSP_IMUX27_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "DSP_1_P15", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B3_1", - "is_directional": "1", - "src_wire": "DSP_1_P4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX22_3->DSP_1_C32": { - "can_invert": "0", - "dst_wire": "DSP_1_C32", - "is_directional": "1", - "src_wire": "DSP_IMUX22_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D15": { - "can_invert": "0", - "dst_wire": "DSP_1_D15", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL1_3->DSP_1_RSTM": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTM", - "is_directional": "1", - "src_wire": "DSP_CTRL1_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D11": { - "can_invert": "0", - "dst_wire": "DSP_1_D11", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D3": { - "can_invert": "0", - "dst_wire": "DSP_1_D3", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D1": { - "can_invert": "0", - "dst_wire": "DSP_1_D1", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D2": { - "can_invert": "0", - "dst_wire": "DSP_1_D2", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT0->DSP_1_PCIN0": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN0", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT0", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D12": { - "can_invert": "0", - "dst_wire": "DSP_1_D12", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT7->DSP_1_PCIN7": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN7", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT7", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN3_3->DSP_1_D12": { - "can_invert": "0", - "dst_wire": "DSP_1_D12", - "is_directional": "1", - "src_wire": "DSP_FAN3_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX37_4->DSP_0_C45": { - "can_invert": "0", - "dst_wire": "DSP_0_C45", - "is_directional": "1", - "src_wire": "DSP_IMUX37_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX29_3->DSP_1_C14": { - "can_invert": "0", - "dst_wire": "DSP_1_C14", - "is_directional": "1", - "src_wire": "DSP_IMUX29_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D18": { - "can_invert": "0", - "dst_wire": "DSP_0_D18", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B0_2", - "is_directional": "1", - "src_wire": "DSP_1_P31", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT0->DSP_BCOUT0": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT0", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT0", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D4": { - "can_invert": "0", - "dst_wire": "DSP_1_D4", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX15_0->DSP_1_A0": { - "can_invert": "0", - "dst_wire": "DSP_1_A0", - "is_directional": "1", - "src_wire": "DSP_IMUX15_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX8_4->DSP_1_OPMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_OPMODE1", - "is_directional": "1", - "src_wire": "DSP_IMUX8_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_0_OPMODE6": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE6", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D14": { - "can_invert": "0", - "dst_wire": "DSP_1_D14", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX45_4->DSP_1_A16": { - "can_invert": "0", - "dst_wire": "DSP_1_A16", - "is_directional": "1", - "src_wire": "DSP_IMUX45_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT30->DSP_PCOUT30": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT30", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT30", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX21_3->DSP_0_ALUMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE0", - "is_directional": "1", - "src_wire": "DSP_IMUX21_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE1", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT38->DSP_1_PCIN38": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN38", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT38", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX32_0->DSP_0_C23": { - "can_invert": "0", - "dst_wire": "DSP_0_C23", - "is_directional": "1", - "src_wire": "DSP_IMUX32_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL1_4->DSP_1_RSTB": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTB", - "is_directional": "1", - "src_wire": "DSP_CTRL1_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT21->DSP_1_PCIN21": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN21", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT21", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT25->DSP_1_ACIN25": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN25", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT25", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN4_0->DSP_1_D3": { - "can_invert": "0", - "dst_wire": "DSP_1_D3", - "is_directional": "1", - "src_wire": "DSP_FAN4_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE3", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "DSP_1_CARRYOUT3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT17->DSP_BCOUT17": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT17", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT17", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX5_2->DSP_1_A29": { - "can_invert": "0", - "dst_wire": "DSP_1_A29", - "is_directional": "1", - "src_wire": "DSP_IMUX5_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT15->DSP_PCOUT15": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT15", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT15", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT1->DSP_ACOUT1": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT1", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX12_3->DSP_1_C34": { - "can_invert": "0", - "dst_wire": "DSP_1_C34", - "is_directional": "1", - "src_wire": "DSP_IMUX12_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN4_3->DSP_1_D15": { - "can_invert": "0", - "dst_wire": "DSP_1_D15", - "is_directional": "1", - "src_wire": "DSP_FAN4_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT20->DSP_ACOUT20": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT20", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT20", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT2->DSP_ACOUT2": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT2", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT2", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP1_4->DSP_0_D19": { - "can_invert": "0", - "dst_wire": "DSP_0_D19", - "is_directional": "1", - "src_wire": "DSP_BYP1_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX17_3->DSP_1_CEA2": { - "can_invert": "0", - "dst_wire": "DSP_1_CEA2", - "is_directional": "1", - "src_wire": "DSP_IMUX17_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX45_2->DSP_1_A28": { - "can_invert": "0", - "dst_wire": "DSP_1_A28", - "is_directional": "1", - "src_wire": "DSP_IMUX45_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_CLK0_1->DSP_0_CLK": { - "can_invert": "0", - "dst_wire": "DSP_0_CLK", - "is_directional": "1", - "src_wire": "DSP_CLK0_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT19->DSP_PCOUT19": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT19", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT19", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT14->DSP_1_BCIN14": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN14", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT14", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D0": { - "can_invert": "0", - "dst_wire": "DSP_0_D0", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT24->DSP_1_PCIN24": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN24", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT24", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT12->DSP_1_PCIN12": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN12", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT12", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT5->DSP_1_ACIN5": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN5", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT5", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX6_3->DSP_0_A15": { - "can_invert": "0", - "dst_wire": "DSP_0_A15", - "is_directional": "1", - "src_wire": "DSP_IMUX6_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX33_3->DSP_0_C15": { - "can_invert": "0", - "dst_wire": "DSP_0_C15", - "is_directional": "1", - "src_wire": "DSP_IMUX33_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B5_0", - "is_directional": "1", - "src_wire": "DSP_1_P21", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX40_3->DSP_1_B14": { - "can_invert": "0", - "dst_wire": "DSP_1_B14", - "is_directional": "1", - "src_wire": "DSP_IMUX40_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP0_1->DSP_0_CEAD": { - "can_invert": "0", - "dst_wire": "DSP_0_CEAD", - "is_directional": "1", - "src_wire": "DSP_BYP0_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX19_4->DSP_0_C46": { - "can_invert": "0", - "dst_wire": "DSP_0_C46", - "is_directional": "1", - "src_wire": "DSP_IMUX19_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX46_3->DSP_0_A14": { - "can_invert": "0", - "dst_wire": "DSP_0_A14", - "is_directional": "1", - "src_wire": "DSP_IMUX46_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX22_4->DSP_1_RSTALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTALUMODE", - "is_directional": "1", - "src_wire": "DSP_IMUX22_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT1->DSP_1_ACIN1": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN1", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { - "can_invert": "0", - "dst_wire": "DSP_0_CARRYINSEL0", - "is_directional": "1", - "src_wire": "DSP_IMUX30_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX17_0->DSP_0_A3": { - "can_invert": "0", - "dst_wire": "DSP_0_A3", - "is_directional": "1", - "src_wire": "DSP_IMUX17_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN0_3->DSP_1_CED": { - "can_invert": "0", - "dst_wire": "DSP_1_CED", - "is_directional": "1", - "src_wire": "DSP_FAN0_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_CEINMODE": { - "can_invert": "0", - "dst_wire": "DSP_1_CEINMODE", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX24_0->DSP_1_C23": { - "can_invert": "0", - "dst_wire": "DSP_1_C23", - "is_directional": "1", - "src_wire": "DSP_IMUX24_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX22_1->DSP_0_C24": { - "can_invert": "0", - "dst_wire": "DSP_0_C24", - "is_directional": "1", - "src_wire": "DSP_IMUX22_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX8_1->DSP_1_B7": { - "can_invert": "0", - "dst_wire": "DSP_1_B7", - "is_directional": "1", - "src_wire": "DSP_IMUX8_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "DSP_1_PATTERNDETECT", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B19_4", - "is_directional": "1", - "src_wire": "DSP_0_P39", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT8->DSP_1_ACIN8": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN8", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT8", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT29->DSP_1_ACIN29": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN29", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT29", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX2_3->DSP_0_B15": { - "can_invert": "0", - "dst_wire": "DSP_0_B15", - "is_directional": "1", - "src_wire": "DSP_IMUX2_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX13_3->DSP_0_ALUMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_ALUMODE1", - "is_directional": "1", - "src_wire": "DSP_IMUX13_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL0_4->DSP_1_RSTP": { - "can_invert": "0", - "dst_wire": "DSP_1_RSTP", - "is_directional": "1", - "src_wire": "DSP_CTRL0_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL1_1->DSP_0_RSTM": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTM", - "is_directional": "1", - "src_wire": "DSP_CTRL1_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D24": { - "can_invert": "0", - "dst_wire": "DSP_1_D24", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { - "can_invert": "0", - "dst_wire": "DSP_MULTSIGNOUT", - "is_directional": "1", - "src_wire": "DSP_1_MULTSIGNOUT", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX26_1->DSP_1_C25": { - "can_invert": "0", - "dst_wire": "DSP_1_C25", - "is_directional": "1", - "src_wire": "DSP_IMUX26_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX0_4->DSP_1_ALUMODE0": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE0", - "is_directional": "1", - "src_wire": "DSP_IMUX0_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D13": { - "can_invert": "0", - "dst_wire": "DSP_1_D13", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP4_4->DSP_1_INMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_INMODE3", - "is_directional": "1", - "src_wire": "DSP_BYP4_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D16": { - "can_invert": "0", - "dst_wire": "DSP_0_D16", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX42_1->DSP_0_RSTINMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTINMODE", - "is_directional": "1", - "src_wire": "DSP_IMUX42_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "DSP_0_P5", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT8->DSP_ACOUT8": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT8", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT8", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B9_2", - "is_directional": "1", - "src_wire": "DSP_0_UNDERFLOW", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN3_0->DSP_1_D0": { - "can_invert": "0", - "dst_wire": "DSP_1_D0", - "is_directional": "1", - "src_wire": "DSP_FAN3_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "DSP_1_P42", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D20": { - "can_invert": "0", - "dst_wire": "DSP_0_D20", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX3_0->DSP_0_C1": { - "can_invert": "0", - "dst_wire": "DSP_0_C1", - "is_directional": "1", - "src_wire": "DSP_IMUX3_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT11->DSP_ACOUT11": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT11", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT11", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { - "can_invert": "0", - "dst_wire": "DSP_1_CARRYINSEL0", - "is_directional": "1", - "src_wire": "DSP_IMUX36_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_BCOUT13->DSP_1_BCIN13": { - "can_invert": "0", - "dst_wire": "DSP_1_BCIN13", - "is_directional": "1", - "src_wire": "DSP_0_BCOUT13", - "is_pseudo": "0" - }, - "DSP_R.DSP_CTRL1_0->DSP_0_RSTA": { - "can_invert": "0", - "dst_wire": "DSP_0_RSTA", - "is_directional": "1", - "src_wire": "DSP_CTRL1_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP6_1->DSP_0_D21": { - "can_invert": "0", - "dst_wire": "DSP_0_D21", - "is_directional": "1", - "src_wire": "DSP_BYP6_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP6_3->DSP_0_INMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE0", - "is_directional": "1", - "src_wire": "DSP_BYP6_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP3_0->DSP_0_D2": { - "can_invert": "0", - "dst_wire": "DSP_0_D2", - "is_directional": "1", - "src_wire": "DSP_BYP3_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP4_0->DSP_0_CEALUMODE": { - "can_invert": "0", - "dst_wire": "DSP_0_CEALUMODE", - "is_directional": "1", - "src_wire": "DSP_BYP4_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP7_3->DSP_0_D12": { - "can_invert": "0", - "dst_wire": "DSP_0_D12", - "is_directional": "1", - "src_wire": "DSP_BYP7_3", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP7_1->DSP_0_D4": { - "can_invert": "0", - "dst_wire": "DSP_0_D4", - "is_directional": "1", - "src_wire": "DSP_BYP7_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT19->DSP_ACOUT19": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT19", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT19", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX10_1->DSP_1_B5": { - "can_invert": "0", - "dst_wire": "DSP_1_B5", - "is_directional": "1", - "src_wire": "DSP_IMUX10_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B6_0", - "is_directional": "1", - "src_wire": "DSP_1_P2", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT1->DSP_BCOUT1": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT1", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX29_4->DSP_1_C45": { - "can_invert": "0", - "dst_wire": "DSP_1_C45", - "is_directional": "1", - "src_wire": "DSP_IMUX29_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_0_D21": { - "can_invert": "0", - "dst_wire": "DSP_0_D21", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX47_1->DSP_0_A24": { - "can_invert": "0", - "dst_wire": "DSP_0_A24", - "is_directional": "1", - "src_wire": "DSP_IMUX47_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX39_1->DSP_0_C4": { - "can_invert": "0", - "dst_wire": "DSP_0_C4", - "is_directional": "1", - "src_wire": "DSP_IMUX39_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT32->DSP_1_PCIN32": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN32", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT32", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT9->DSP_PCOUT9": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT9", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT9", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D7": { - "can_invert": "0", - "dst_wire": "DSP_1_D7", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D5": { - "can_invert": "0", - "dst_wire": "DSP_1_D5", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "DSP_0_P38", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT27->DSP_1_PCIN27": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN27", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT27", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_ACOUT6->DSP_ACOUT6": { - "can_invert": "0", - "dst_wire": "DSP_ACOUT6", - "is_directional": "1", - "src_wire": "DSP_1_ACOUT6", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "DSP_0_P28", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX8_2->DSP_1_B11": { - "can_invert": "0", - "dst_wire": "DSP_1_B11", - "is_directional": "1", - "src_wire": "DSP_IMUX8_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { - "can_invert": "0", - "dst_wire": "DSP_LOGIC_OUTS_B21_3", - "is_directional": "1", - "src_wire": "DSP_0_P12", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX35_0->DSP_0_C40": { - "can_invert": "0", - "dst_wire": "DSP_0_C40", - "is_directional": "1", - "src_wire": "DSP_IMUX35_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_BCOUT8->DSP_BCOUT8": { - "can_invert": "0", - "dst_wire": "DSP_BCOUT8", - "is_directional": "1", - "src_wire": "DSP_1_BCOUT8", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX11_4->DSP_1_C46": { - "can_invert": "0", - "dst_wire": "DSP_1_C46", - "is_directional": "1", - "src_wire": "DSP_IMUX11_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_ACOUT21->DSP_1_ACIN21": { - "can_invert": "0", - "dst_wire": "DSP_1_ACIN21", - "is_directional": "1", - "src_wire": "DSP_0_ACOUT21", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX20_1->DSP_0_C26": { - "can_invert": "0", - "dst_wire": "DSP_0_C26", - "is_directional": "1", - "src_wire": "DSP_IMUX20_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN6_4->DSP_1_D17": { - "can_invert": "0", - "dst_wire": "DSP_1_D17", - "is_directional": "1", - "src_wire": "DSP_FAN6_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX27_0->DSP_1_C40": { - "can_invert": "0", - "dst_wire": "DSP_1_C40", - "is_directional": "1", - "src_wire": "DSP_IMUX27_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX35_2->DSP_0_OPMODE0": { - "can_invert": "0", - "dst_wire": "DSP_0_OPMODE0", - "is_directional": "1", - "src_wire": "DSP_IMUX35_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX38_0->DSP_0_C20": { - "can_invert": "0", - "dst_wire": "DSP_0_C20", - "is_directional": "1", - "src_wire": "DSP_IMUX38_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_BYP0_4->DSP_1_ALUMODE3": { - "can_invert": "0", - "dst_wire": "DSP_1_ALUMODE3", - "is_directional": "1", - "src_wire": "DSP_BYP0_4", - "is_pseudo": "0" - }, - "DSP_R.DSP_FAN7_1->DSP_0_INMODE1": { - "can_invert": "0", - "dst_wire": "DSP_0_INMODE1", - "is_directional": "1", - "src_wire": "DSP_FAN7_1", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT13->DSP_1_PCIN13": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN13", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT13", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX30_0->DSP_1_C20": { - "can_invert": "0", - "dst_wire": "DSP_1_C20", - "is_directional": "1", - "src_wire": "DSP_IMUX30_0", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT24->DSP_PCOUT24": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT24", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT24", - "is_pseudo": "0" - }, - "DSP_R.DSP_1_PCOUT21->DSP_PCOUT21": { - "can_invert": "0", - "dst_wire": "DSP_PCOUT21", - "is_directional": "1", - "src_wire": "DSP_1_PCOUT21", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX6_2->DSP_0_C28": { - "can_invert": "0", - "dst_wire": "DSP_0_C28", - "is_directional": "1", - "src_wire": "DSP_IMUX6_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_GND_R->DSP_1_D0": { - "can_invert": "0", - "dst_wire": "DSP_1_D0", - "is_directional": "1", - "src_wire": "DSP_GND_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX29_2->DSP_1_C10": { - "can_invert": "0", - "dst_wire": "DSP_1_C10", - "is_directional": "1", - "src_wire": "DSP_IMUX29_2", - "is_pseudo": "0" - }, - "DSP_R.DSP_0_PCOUT5->DSP_1_PCIN5": { - "can_invert": "0", - "dst_wire": "DSP_1_PCIN5", - "is_directional": "1", - "src_wire": "DSP_0_PCOUT5", - "is_pseudo": "0" - }, - "DSP_R.DSP_VCC_R->DSP_1_D2": { - "can_invert": "0", - "dst_wire": "DSP_1_D2", - "is_directional": "1", - "src_wire": "DSP_VCC_R", - "is_pseudo": "0" - }, - "DSP_R.DSP_IMUX31_0->DSP_1_C0": { - "can_invert": "0", - "dst_wire": "DSP_1_C0", - "is_directional": "1", - "src_wire": "DSP_IMUX31_0", - "is_pseudo": "0" - } - }, - "tile_type": "DSP_R" + ] } \ No newline at end of file diff --git a/artix7/tile_type_GTP_CHANNEL_0.json b/artix7/tile_type_GTP_CHANNEL_0.json index 23be5d2..2d791bc 100644 --- a/artix7/tile_type_GTP_CHANNEL_0.json +++ b/artix7/tile_type_GTP_CHANNEL_0.json @@ -1,5922 +1,5922 @@ { - "wires": [ - "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "GTPE2_IMUX18_2", - "GTPE2_LOGIC_OUTS_B1_3", - "GTPE2_IMUX26_4", - "GTPE2_CHANNEL_TXDATA13", - "GTPE2_CHANNEL_PMARSVDOUT0", - "GTPE2_FAN1_0", - "GTPE2_LOGIC_OUTS_B14_6", - "GTPE2_LOGIC_OUTS_B13_2", - "GTPE2_FAN3_5", - "GTPE2_IMUX16_6", - "GTPE2_CHANNEL_SETERRSTATUS", - "GTPE2_IMUX43_9", - "GTPE2_BYP5_3", - "GTPE2_LOGIC_OUTS_B19_5", - "GTPE2_IMUX34_0", - "GTPE2_LOGIC_OUTS_B10_3", - "GTPE2_LOGIC_OUTS_B5_1", - "GTPE2_IMUX18_1", - "GTPE2_IMUX6_4", - "GTPE2_IMUX21_5", - "GTPE2_CHANNEL_RXPHDLYPD", - "GTPE2_IMUX40_9", - "GTPE2_CHANNEL_TXMAINCURSOR3", - "GTPE2_CHANNEL_TSTCLK0", - "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "GTPE2_LOGIC_OUTS_B9_7", - "GTPE2_LOGIC_OUTS_B13_8", - "GTPE2_CHANNEL_RXDATAVALID0", - "GTPE2_CHANNEL_PCSRSVDOUT0", - "GTPE2_CHANNEL_RXSYNCMODE", - "GTPE2_LOGIC_OUTS_B10_0", - "GTPE2_CHANNEL_SCANOUT3", - "GTPE2_CHANNEL_RXOSOVRDEN", - "GTPE2_IMUX47_9", - "GTPE2_CHANNEL_RXCHBONDI1", - "GTPE2_CHANNEL_RXCHBONDI2", - "GTPE2_FAN2_1", - "GTPE2_CTRL1_2", - "GTPE2_CHANNEL_PCSRSVDOUT8", - "GTPE2_LOGIC_OUTS_B18_2", - "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "GTPE2_IMUX32_4", - "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "GTPE2_FAN1_8", - "GTPE2_CHANNEL_RXOUTCLK_3", - "GTPE2_CHANNEL_TXDATA11", - "GTPE2_LOGIC_OUTS_B15_5", - "GTPE2_IMUX15_8", - "GTPE2_CHANNEL_TXDATA21", - "GTPE2_CLK0_4", - "GTPE2_CHANNEL_RXPCSRESET", - "GTPE2_IMUX14_4", - "GTPE2_LOGIC_OUTS_B23_2", - "GTPE2_LOGIC_OUTS_B5_6", - "GTPE2_CHANNEL_PCSRSVDIN14", - "GTPE2_FAN2_5", - "GTPE2_CHANNEL_PCSRSVDOUT10", - "GTPE2_IMUX14_6", - "GTPE2_IMUX15_1", - "GTPE2_IMUX30_7", - "GTPE2_CHANNEL_PMASCANOUT4", - "GTPE2_CHANNEL_TXDATA2", - "GTPE2_IMUX41_6", - "GTPE2_IMUX47_4", - "GTPE2_FAN6_0", - "GTPE2_CHANNEL_TXPRECURSOR4", - "GTPE2_FAN3_3", - "GTPE2_CHANNEL_TX8B10BBYPASS0", - "GTPE2_CHANNEL_PMASCANOUT5", - "GTPE2_LOGIC_OUTS_B14_5", - "GTPE2_CHANNEL_TXDLYTESTENB", - "GTPE2_CHANNEL_RXVALID", - "GTPE2_BYP1_9", - "GTPE2_LOGIC_OUTS_B7_6", - "GTPE2_CHANNEL_RXDATA24", - "GTPE2_IMUX10_2", - "GTPE2_CHANNEL_DRPADDR4", - "GTPE2_IMUX2_1", - "GTPE2_IMUX4_4", - "GTPE2_CHANNEL_PMASCANIN0", - "GTPE2_FAN3_7", - "GTPE2_CHANNEL_TXPMARESETDONE", - "GTPE2_CHANNEL_RXSYNCIN", - "GTPE2_LOGIC_OUTS_B8_10", - "GTPE2_CHANNEL_RXRATEMODE", - "GTPE2_LOGIC_OUTS_B10_9", - "GTPE2_IMUX31_10", - "GTPE2_CHANNEL_DRPDO1", - "GTPE2_CTRL0_7", - "GTPE2_CHANNEL_PLLCLK1", - "GTPE2_IMUX29_3", - "GTPE2_BYP6_1", - "GTPE2_CHANNEL_RXCOMINITDET", - "GTPE2_CHANNEL_TXDIFFPD", - "GTPE2_IMUX27_2", - "GTPE2_CHANNEL_TXDIFFCTRL0", - "GTPE2_IMUX40_1", - "GTPE2_FAN6_2", - "GTPE2_CHANNEL_TXPOSTCURSOR3", - "GTPE2_IMUX37_10", - "GTPE2_LOGIC_OUTS_B15_4", - "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "GTPE2_CHANNEL_TXMAINCURSOR6", - "GTPE2_IMUX27_1", - "GTPE2_CTRL1_7", - "GTPE2_LOGIC_OUTS_B1_5", - "GTPE2_CHANNEL_TSTIN2", - "GTPE2_CHANNEL_RXDATA9", - "GTPE2_IMUX3_5", - "GTPE2_CHANNEL_RXPHALIGNDONE", - "GTPE2_CHANNEL_RXPHMONITOR3", - "GTPE2_LOGIC_OUTS_B2_9", - "GTPE2_IMUX31_1", - "GTPE2_IMUX17_10", - "GTPE2_CHANNEL_RXCHARISCOMMA0", - "GTPE2_LOGIC_OUTS_B8_4", - "GTPE2_FAN7_6", - "GTPE2_IMUX41_2", - "GTPE2_IMUX12_0", - "GTPE2_LOGIC_OUTS_B10_5", - "GTPE2_IMUX10_0", - "GTPE2_LOGIC_OUTS_B17_8", - "GTPE2_FAN3_9", - "GTPE2_CHANNEL_RXCHARISCOMMA1", - "GTPE2_IMUX33_7", - "GTPE2_LOGIC_OUTS_B5_9", - "GTPE2_IMUX36_7", - "GTPE2_IMUX3_7", - "GTPE2_LOGIC_OUTS_B12_9", - "GTPE2_IMUX16_1", - "GTPE2_LOGIC_OUTS_B23_5", - "GTPE2_FAN2_2", - "GTPE2_IMUX0_5", - "GTPE2_CHANNEL_TXOUTCLK_0", - "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "GTPE2_CHANNEL_PCSRSVDIN6", - "GTPE2_IMUX33_3", - "GTPE2_IMUX41_4", - "GTPE2_IMUX46_6", - "GTPE2_CHANNEL_TXHEADER0", - "GTPE2_BYP0_1", - "GTPE2_IMUX1_9", - "GTPE2_CHANNEL_PCSRSVDIN8", - "GTPE2_IMUX13_4", - "GTPE2_CHANNEL_RXADAPTSELTEST1", - "GTPE2_IMUX32_9", - "GTPE2_BYP4_5", - "GTPE2_CHANNEL_RXADAPTSELTEST8", - "GTPE2_CHANNEL_TXDLYUPDOWN", - "GTPE2_IMUX44_7", - "GTPE2_IMUX19_8", - "GTPE2_IMUX41_7", - "GTPE2_IMUX19_2", - "GTPE2_CHANNEL_GTRSVD8", - "GTPE2_IMUX4_0", - "GTPE2_BYP6_7", - "GTPE2_IMUX25_10", - "GTPE2_FAN7_3", - "GTPE2_CHANNEL_RXCHBONDSLAVE", - "GTPE2_IMUX24_3", - "GTPE2_LOGIC_OUTS_B5_8", - "GTPE2_FAN0_7", - "GTPE2_IMUX45_6", - "GTPE2_CTRL0_2", - "GTPE2_IMUX43_5", - "GTPE2_CHANNEL_PCSRSVDOUT13", - "GTPE2_IMUX17_4", - "GTPE2_BYP3_7", - "GTPE2_CHANNEL_SCANOUT0", - "GTPE2_IMUX43_1", - "GTPE2_CHANNEL_RXDISPERR2", - "GTPE2_CHANNEL_RXOUTCLK_1", - "GTPE2_CHANNEL_GTRSVD1", - "GTPE2_IMUX13_8", - "GTPE2_IMUX20_4", - "GTPE2_BYP0_8", - "GTPE2_IMUX0_2", - "GTPE2_IMUX29_2", - "GTPE2_IMUX6_5", - "GTPE2_LOGIC_OUTS_B2_0", - "GTPE2_LOGIC_OUTS_B1_2", - "GTPE2_IMUX18_6", - "GTPE2_LOGIC_OUTS_B15_7", - "GTPE2_LOGIC_OUTS_B1_6", - "GTPE2_LOGIC_OUTS_B16_8", - "GTPE2_IMUX44_3", - "GTPE2_CHANNEL_PMARSVDIN1", - "GTPE2_CHANNEL_TXDATA1", - "GTPE2_CHANNEL_RXOSINTID00", - "GTPE2_LOGIC_OUTS_B3_0", - "GTPE2_CHANNEL_RXCHBONDO1", - "GTPE2_IMUX2_3", - "GTPE2_CHANNEL_RXOSINTID03", - "GTPE2_CHANNEL_PMASCANOUT1", - "GTPE2_LOGIC_OUTS_B19_3", - "GTPE2_CHANNEL_TXHEADER2", - "GTPE2_LOGIC_OUTS_B10_2", - "GTPE2_IMUX45_0", - "GTPE2_CHANNEL_DMONITOROUT6", - "GTPE2_LOGIC_OUTS_B9_3", - "GTPE2_IMUX17_8", - "GTPE2_CHANNEL_SIGVALIDCLK", - "GTPE2_IMUX31_5", - "GTPE2_LOGIC_OUTS_B2_3", - "GTPE2_FAN7_2", - "GTPE2_CHANNEL_RXPRBSSEL1", - "GTPE2_IMUX19_1", - "GTPE2_CHANNEL_PMASCANRSTEN", - "GTPE2_IMUX5_6", - "GTPE2_LOGIC_OUTS_B4_9", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "GTPE2_CHANNEL_RXPRBSCNTRESET", - "GTPE2_IMUX29_1", - "GTPE2_CHANNEL_RXDATA29", - "GTPE2_CHANNEL_RXDATA27", - "GTPE2_CHANNEL_PCSRSVDIN2", - "GTPE2_CHANNEL_PCSRSVDIN3", - "GTPE2_IMUX10_6", - "GTPE2_IMUX32_3", - "GTPE2_CHANNEL_RXOSINTHOLD", - "GTPE2_CHANNEL_DRPWE", - "GTPE2_CHANNEL_DMONITORCLK", - "GTPE2_LOGIC_OUTS_B9_1", - "GTPE2_IMUX20_7", - "GTPE2_LOGIC_OUTS_B6_2", - "GTPE2_LOGIC_OUTS_B6_3", - "GTPE2_IMUX34_10", - "GTPE2_IMUX25_5", - "GTPE2_IMUX9_6", - "GTPE2_CHANNEL_TXBUFSTATUS1", - "GTPE2_IMUX30_6", - "GTPE2_LOGIC_OUTS_B22_1", - "GTPE2_IMUX46_10", - "GTPE2_IMUX11_10", - "GTPE2_IMUX31_6", - "GTPE2_IMUX42_2", - "GTPE2_IMUX34_5", - "GTPE2_LOGIC_OUTS_B2_4", - "GTPE2_CHANNEL_RXADAPTSELTEST7", - "GTPE2_IMUX14_10", - "GTPE2_FAN0_9", - "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "GTPE2_CTRL1_3", - "GTPE2_CHANNEL_SCANIN0", - "GTPE2_FAN6_1", - "GTPE2_IMUX46_3", - "GTPE2_CHANNEL_TXSEQUENCE0", - "GTPE2_IMUX2_0", - "GTPE2_LOGIC_OUTS_B13_6", - "GTPE2_BYP4_1", - "GTPE2_CHANNEL_TXPHALIGN", - "GTPE2_CHANNEL_GTRESETSEL", - "GTPE2_LOGIC_OUTS_B13_10", - "GTPE2_CHANNEL_PLL0REFCLK", - "GTPE2_LOGIC_OUTS_B8_1", - "GTPE2_IMUX12_6", - "GTPE2_CHANNEL_RXP_PAD", - "GTPE2_IMUX25_1", - "GTPE2_IMUX29_10", - "GTPE2_IMUX30_8", - "GTPE2_IMUX2_2", - "GTPE2_LOGIC_OUTS_B14_9", - "GTPE2_LOGIC_OUTS_B23_4", - "GTPE2_IMUX30_5", - "GTPE2_CLK1_5", - "GTPE2_IMUX31_7", - "GTPE2_CHANNEL_TXMAINCURSOR4", - "GTPE2_IMUX12_3", - "GTPE2_IMUX1_5", - "GTPE2_LOGIC_OUTS_B21_7", - "GTPE2_CHANNEL_TSTIN10", - "GTPE2_IMUX45_3", - "GTPE2_CHANNEL_TXPHALIGNDONE", - "GTPE2_CHANNEL_TXDIFFCTRL3", - "GTPE2_IMUX22_9", - "GTPE2_IMUX19_4", - "GTPE2_LOGIC_OUTS_B4_7", - "GTPE2_IMUX46_8", - "GTPE2_CHANNEL_RXADAPTSELTEST12", - "GTPE2_IMUX28_1", - "GTPE2_LOGIC_OUTS_B4_6", - "GTPE2_CHANNEL_TXDEEMPH", - "GTPE2_IMUX8_8", - "GTPE2_LOGIC_OUTS_B17_10", - "GTPE2_CHANNEL_PCSRSVDIN7", - "GTPE2_LOGIC_OUTS_B4_5", - "GTPE2_IMUX31_3", - "GTPE2_CHANNEL_RXBYTEISALIGNED", - "GTPE2_CHANNEL_TSTIN8", - "GTPE2_IMUX28_8", - "GTPE2_CHANNEL_TXUSERRDY", - "GTPE2_CHANNEL_SCANIN4", - "GTPE2_CHANNEL_RXLPMLFHOLD", - "GTPE2_CHANNEL_PMARSVDIN0", - "GTPE2_IMUX12_5", - "GTPE2_FAN2_8", - "GTPE2_CHANNEL_TXRATE2", - "GTPE2_LOGIC_OUTS_B20_6", - "GTPE2_CHANNEL_TXSYNCALLIN", - "GTPE2_LOGIC_OUTS_B19_9", - "GTPE2_IMUX13_1", - "GTPE2_FAN3_2", - "GTPE2_LOGIC_OUTS_B0_4", - "GTPE2_CHANNEL_TXCHARDISPVAL0", - "GTPE2_IMUX33_2", - "GTPE2_IMUX1_4", - "GTPE2_IMUX14_8", - "GTPE2_IMUX4_10", - "GTPE2_LOGIC_OUTS_B2_5", - "GTPE2_IMUX8_6", - "GTPE2_IMUX15_2", - "GTPE2_CHANNEL_TXRATE1", - "GTPE2_BYP6_3", - "GTPE2_CHANNEL_RXNOTINTABLE2", - "GTPE2_FAN4_4", - "GTPE2_LOGIC_OUTS_B9_9", - "GTPE2_CHANNEL_TXCHARDISPMODE0", - "GTPE2_IMUX16_8", - "GTPE2_LOGIC_OUTS_B18_3", - "GTPE2_IMUX36_3", - "GTPE2_CHANNEL_TXCOMFINISH", - "GTPE2_IMUX11_4", - "GTPE2_IMUX14_9", - "GTPE2_IMUX20_2", - "GTPE2_IMUX16_5", - "GTPE2_CHANNEL_RXOOBRESET", - "GTPE2_CHANNEL_RXOSHOLD", - "GTPE2_CHANNEL_GTRXRESET", - "GTPE2_CHANNEL_TXPHINIT", - "GTPE2_CHANNEL_RXADAPTSELTEST3", - "GTPE2_IMUX36_5", - "GTPE2_BYP2_5", - "GTPE2_CLK0_9", - "GTPE2_CHANNEL_DRPDO5", - "GTPE2_IMUX20_6", - "GTPE2_CHANNEL_SCANMODEB", - "GTPE2_IMUX36_4", - "GTPE2_CLK0_10", - "GTPE2_LOGIC_OUTS_B3_6", - "GTPE2_CHANNEL_TXDATA17", - "GTPE2_LOGIC_OUTS_B6_10", - "GTPE2_CHANNEL_RXPD0", - "GTPE2_IMUX1_2", - "GTPE2_IMUX44_2", - "GTPE2_CHANNEL_DRPDO7", - "GTPE2_LOGIC_OUTS_B23_3", - "GTPE2_IMUX47_6", - "GTPE2_CHANNEL_RXPHDLYRESET", - "GTPE2_LOGIC_OUTS_B2_1", - "GTPE2_LOGIC_OUTS_B10_8", - "GTPE2_IMUX44_0", - "GTPE2_CHANNEL_TXCOMSAS", - "GTPE2_CHANNEL_DMONITOROUT12", - "GTPE2_CHANNEL_RXDATA8", - "GTPE2_IMUX2_4", - "GTPE2_CHANNEL_PCSRSVDOUT7", - "GTPE2_LOGIC_OUTS_B11_0", - "GTPE2_LOGIC_OUTS_B8_3", - "GTPE2_CHANNEL_RXDATAVALID1", - "GTPE2_CHANNEL_GTRSVD9", - "GTPE2_CHANNEL_TSTIN15", - "GTPE2_CHANNEL_TXCHARISK0", - "GTPE2_LOGIC_OUTS_B6_5", - "GTPE2_IMUX29_0", - "GTPE2_CHANNEL_TXOUTCLK_2", - "GTPE2_CHANNEL_RXCHARISK3", - "GTPE2_FAN7_4", - "GTPE2_CLK0_8", - "GTPE2_CHANNEL_GTRSVD3", - "GTPE2_CHANNEL_RXCHANISALIGNED", - "GTPE2_CHANNEL_RXCHBONDO3", - "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "GTPE2_IMUX26_5", - "GTPE2_LOGIC_OUTS_B10_10", - "GTPE2_CHANNEL_RXDLYBYPASS", - "GTPE2_CHANNEL_TSTCLK1", - "GTPE2_CHANNEL_TXDATA12", - "GTPE2_CHANNEL_DRPDO14", - "GTPE2_IMUX28_9", - "GTPE2_IMUX21_7", - "GTPE2_IMUX5_8", - "GTPE2_FAN2_6", - "GTPE2_IMUX42_1", - "GTPE2_CHANNEL_DMONITOROUT13", - "GTPE2_IMUX31_9", - "GTPE2_FAN0_5", - "GTPE2_IMUX8_7", - "GTPE2_IMUX39_9", - "GTPE2_LOGIC_OUTS_B22_0", - "GTPE2_CHANNEL_PCSRSVDIN12", - "GTPE2_CHANNEL_TXUSRCLK2", - "GTPE2_CHANNEL_RXDISPERR1", - "GTPE2_CHANNEL_DMONITOROUT14", - "GTPE2_IMUX24_1", - "GTPE2_LOGIC_OUTS_B11_9", - "GTPE2_LOGIC_OUTS_B21_5", - "GTPE2_IMUX8_5", - "GTPE2_CHANNEL_RXUSRCLK", - "GTPE2_IMUX47_8", - "GTPE2_FAN4_8", - "GTPE2_CHANNEL_RXDATA1", - "GTPE2_IMUX19_3", - "GTPE2_CHANNEL_RXPHALIGN", - "GTPE2_CHANNEL_PMARSVDIN3", - "GTPE2_CHANNEL_RXDLYSRESETDONE", - "GTPE2_LOGIC_OUTS_B7_5", - "GTPE2_IMUX37_5", - "GTPE2_CHANNEL_RXPHMONITOR2", - "GTPE2_FAN1_10", - "GTPE2_CHANNEL_RXDISPERR3", - "GTPE2_BYP2_9", - "GTPE2_LOGIC_OUTS_B17_6", - "GTPE2_CHANNEL_RXRATE2", - "GTPE2_IMUX15_10", - "GTPE2_CHANNEL_PMASCANOUT3", - "GTPE2_IMUX30_4", - "GTPE2_CHANNEL_RXOUTCLKSEL1", - "GTPE2_CHANNEL_RXDDIEN", - "GTPE2_CHANNEL_TXCHARISK3", - "GTPE2_IMUX42_0", - "GTPE2_IMUX36_9", - "GTPE2_LOGIC_OUTS_B21_10", - "GTPE2_IMUX2_8", - "GTPE2_CHANNEL_TXRATE0", - "GTPE2_CHANNEL_RXOSINTPD", - "GTPE2_IMUX4_8", - "GTPE2_CLK0_0", - "GTPE2_CHANNEL_RXPRBSSEL0", - "GTPE2_LOGIC_OUTS_B18_6", - "GTPE2_CHANNEL_RXDATA21", - "GTPE2_CHANNEL_TXDATA4", - "GTPE2_CHANNEL_RESETOVRD", - "GTPE2_BYP7_2", - "GTPE2_LOGIC_OUTS_B17_7", - "GTPE2_CHANNEL_TXDATA0", - "GTPE2_LOGIC_OUTS_B15_0", - "GTPE2_IMUX7_5", - "GTPE2_IMUX24_4", - "GTPE2_IMUX7_7", - "GTPE2_LOGIC_OUTS_B3_9", - "GTPE2_LOGIC_OUTS_B17_4", - "GTPE2_FAN6_5", - "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "GTPE2_LOGIC_OUTS_B16_2", - "GTPE2_CHANNEL_TXMARGIN2", - "GTPE2_IMUX28_10", - "GTPE2_CHANNEL_DRPDI5", - "GTPE2_LOGIC_OUTS_B21_1", - "GTPE2_IMUX44_8", - "GTPE2_LOGIC_OUTS_B9_10", - "GTPE2_CHANNEL_TXCHARDISPVAL2", - "GTPE2_IMUX25_6", - "GTPE2_CHANNEL_SCANIN3", - "GTPE2_LOGIC_OUTS_B16_5", - "GTPE2_LOGIC_OUTS_B23_6", - "GTPE2_IMUX40_6", - "GTPE2_IMUX12_1", - "GTPE2_CHANNEL_DRPDO11", - "GTPE2_CHANNEL_RXADAPTSELTEST6", - "GTPE2_IMUX31_2", - "GTPE2_IMUX29_4", - "GTPE2_LOGIC_OUTS_B13_9", - "GTPE2_IMUX38_6", - "GTPE2_LOGIC_OUTS_B12_7", - "GTPE2_IMUX40_10", - "GTPE2_IMUX0_6", - "GTPE2_CHANNEL_TXPRECURSOR0", - "GTPE2_LOGIC_OUTS_B21_4", - "GTPE2_LOGIC_OUTS_B16_0", - "GTPE2_FAN7_1", - "GTPE2_CHANNEL_DRPDI14", - "GTPE2_LOGIC_OUTS_B5_7", - "GTPE2_IMUX39_1", - "GTPE2_IMUX15_7", - "GTPE2_IMUX6_1", - "GTPE2_CHANNEL_TXPD0", - "GTPE2_IMUX26_2", - "GTPE2_IMUX27_5", - "GTPE2_LOGIC_OUTS_B19_2", - "GTPE2_IMUX13_5", - "GTPE2_LOGIC_OUTS_B16_4", - "GTPE2_CHANNEL_TXHEADER1", - "GTPE2_CLK1_10", - "GTPE2_IMUX41_8", - "GTPE2_BYP4_9", - "GTPE2_IMUX5_7", - "GTPE2_CHANNEL_RXDATA15", - "GTPE2_BYP2_2", - "GTPE2_BYP7_10", - "GTPE2_LOGIC_OUTS_B22_6", - "GTPE2_IMUX16_4", - "GTPE2_BYP1_2", - "GTPE2_LOGIC_OUTS_B9_6", - "GTPE2_BYP1_4", - "GTPE2_IMUX23_2", - "GTPE2_IMUX1_1", - "GTPE2_IMUX0_8", - "GTPE2_LOGIC_OUTS_B13_5", - "GTPE2_CHANNEL_TXPHOVRDEN", - "GTPE2_LOGIC_OUTS_B7_2", - "GTPE2_CHANNEL_DMONITOROUT7", - "GTPE2_LOGIC_OUTS_B17_3", - "GTPE2_CHANNEL_RXELECIDLEMODE1", - "GTPE2_CHANNEL_RXDISPERR0", - "GTPE2_LOGIC_OUTS_B2_10", - "GTPE2_IMUX17_1", - "GTPE2_CHANNEL_TXDLYHOLD", - "GTPE2_BYP3_8", - "GTPE2_CHANNEL_RXOUTCLKPCS", - "GTPE2_IMUX32_8", - "GTPE2_CHANNEL_DRPADDR7", - "GTPE2_IMUX7_9", - "GTPE2_IMUX46_5", - "GTPE2_IMUX20_1", - "GTPE2_CHANNEL_DMONITOROUT9", - "GTPE2_CHANNEL_DRPDO15", - "GTPE2_IMUX23_0", - "GTPE2_IMUX15_3", - "GTPE2_CHANNEL_RXOSINTCFG3", - "GTPE2_CHANNEL_RXDATA0", - "GTPE2_IMUX36_1", - "GTPE2_LOGIC_OUTS_B23_8", - "GTPE2_IMUX37_2", - "GTPE2_CHANNEL_TXP_PAD", - "GTPE2_IMUX43_6", - "GTPE2_CHANNEL_RXDATA18", - "GTPE2_IMUX21_9", - "GTPE2_CLK1_4", - "GTPE2_CHANNEL_TXGEARBOXREADY", - "GTPE2_LOGIC_OUTS_B10_6", - "GTPE2_LOGIC_OUTS_B20_0", - "GTPE2_IMUX6_2", - "GTPE2_IMUX23_1", - "GTPE2_CHANNEL_TXPOSTCURSOR0", - "GTPE2_BYP5_4", - "GTPE2_CHANNEL_TXDATA14", - "GTPE2_CHANNEL_GTRSVD13", - "GTPE2_CHANNEL_TXSEQUENCE1", - "GTPE2_IMUX14_7", - "GTPE2_CHANNEL_TXPHINITDONE", - "GTPE2_CHANNEL_EYESCANMODE", - "GTPE2_CHANNEL_PLL0CLK", - "GTPE2_CHANNEL_TXDETECTRX", - "GTPE2_LOGIC_OUTS_B4_10", - "GTPE2_LOGIC_OUTS_B14_10", - "GTPE2_IMUX35_6", - "GTPE2_CHANNEL_TXOUTCLK_1", - "GTPE2_CHANNEL_RXDATA17", - "GTPE2_BYP7_7", - "GTPE2_CTRL0_8", - "GTPE2_CHANNEL_PLL1CLK", - "GTPE2_IMUX25_9", - "GTPE2_CHANNEL_CLKRSVD0", - "GTPE2_IMUX3_0", - "GTPE2_IMUX18_4", - "GTPE2_IMUX20_5", - "GTPE2_BYP1_5", - "GTPE2_IMUX42_4", - "GTPE2_LOGIC_OUTS_B22_10", - "GTPE2_IMUX7_0", - "GTPE2_CHANNEL_RXBYTEREALIGN", - "GTPE2_CHANNEL_RXDATA26", - "GTPE2_CHANNEL_RXPHMONITOR0", - "GTPE2_CHANNEL_PMASCANIN2", - "GTPE2_CHANNEL_RXPHALIGNEN", - "GTPE2_IMUX45_9", - "GTPE2_CTRL1_6", - "GTPE2_CHANNEL_RXOSINTNTRLEN", - "GTPE2_CHANNEL_SCANOUT5", - "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "GTPE2_CHANNEL_RXCOMSASDET", - "GTPE2_IMUX31_0", - "GTPE2_CHANNEL_TXDLYBYPASS", - "GTPE2_IMUX22_5", - "GTPE2_CHANNEL_RXDATA6", - "GTPE2_CHANNEL_TXPISOPD", - "GTPE2_CHANNEL_PCSRSVDIN15", - "GTPE2_IMUX3_8", - "GTPE2_CHANNEL_RXNOTINTABLE0", - "GTPE2_CHANNEL_RXADAPTSELTEST4", - "GTPE2_CHANNEL_TXMAINCURSOR0", - "GTPE2_CHANNEL_PCSRSVDOUT5", - "GTPE2_CHANNEL_TXDATA6", - "GTPE2_CHANNEL_RXOSINTSTARTED", - "GTPE2_IMUX10_10", - "GTPE2_LOGIC_OUTS_B2_8", - "GTPE2_LOGIC_OUTS_B4_8", - "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "GTPE2_BYP6_0", - "GTPE2_CHANNEL_RXOUTCLK_0", - "GTPE2_CHANNEL_RXOSINTCFG2", - "GTPE2_CHANNEL_GTRSVD4", - "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "GTPE2_LOGIC_OUTS_B14_2", - "GTPE2_CHANNEL_TSTIN14", - "GTPE2_CHANNEL_DMONITOROUT0", - "GTPE2_LOGIC_OUTS_B4_4", - "GTPE2_CHANNEL_DRPDO0", - "GTPE2_IMUX38_5", - "GTPE2_LOGIC_OUTS_B0_5", - "GTPE2_CHANNEL_RXRATE0", - "GTPE2_CHANNEL_RXCHANREALIGN", - "GTPE2_CHANNEL_RXCHBONDMASTER", - "GTPE2_FAN6_10", - "GTPE2_IMUX22_2", - "GTPE2_IMUX29_9", - "GTPE2_CHANNEL_RXDATA16", - "GTPE2_CHANNEL_RXADAPTSELTEST9", - "GTPE2_IMUX23_7", - "GTPE2_IMUX43_7", - "GTPE2_IMUX11_8", - "GTPE2_CHANNEL_TXDATA7", - "GTPE2_LOGIC_OUTS_B9_2", - "GTPE2_CHANNEL_TXPD1", - "GTPE2_FAN1_7", - "GTPE2_CHANNEL_RXDATA25", - "GTPE2_IMUX24_0", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "GTPE2_CHANNEL_SCANOUT2", - "GTPE2_IMUX10_8", - "GTPE2_CHANNEL_DRPDI0", - "GTPE2_CHANNEL_RXDATA5", - "GTPE2_CHANNEL_PCSRSVDIN4", - "GTPE2_BYP3_5", - "GTPE2_CHANNEL_DRPDO2", - "GTPE2_CHANNEL_DMONFIFORESET", - "GTPE2_IMUX39_3", - "GTPE2_LOGIC_OUTS_B10_7", - "GTPE2_BYP3_3", - "GTPE2_CHANNEL_TX8B10BBYPASS2", - "GTPE2_IMUX3_3", - "GTPE2_CHANNEL_RXDATA30", - "GTPE2_CHANNEL_TXOUTCLKSEL2", - "GTPE2_IMUX24_8", - "GTPE2_IMUX38_0", - "GTPE2_IMUX20_3", - "GTPE2_CHANNEL_TXRATEMODE", - "GTPE2_IMUX12_2", - "GTPE2_LOGIC_OUTS_B21_6", - "GTPE2_IMUX39_7", - "GTPE2_LOGIC_OUTS_B15_8", - "GTPE2_CHANNEL_RXPMARESETDONE", - "GTPE2_CHANNEL_RXPMARESET", - "GTPE2_IMUX39_8", - "GTPE2_IMUX6_6", - "GTPE2_CHANNEL_TXDATA22", - "GTPE2_CHANNEL_TXCHARISK1", - "GTPE2_FAN6_6", - "GTPE2_IMUX5_0", - "GTPE2_LOGIC_OUTS_B12_6", - "GTPE2_BYP4_0", - "GTPE2_CHANNEL_TSTIN12", - "GTPE2_IMUX11_6", - "GTPE2_LOGIC_OUTS_B3_1", - "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "GTPE2_IMUX45_8", - "GTPE2_FAN5_5", - "GTPE2_CHANNEL_TXOUTCLK_3", - "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "GTPE2_CHANNEL_PCSRSVDOUT4", - "GTPE2_IMUX9_2", - "GTPE2_IMUX35_10", - "GTPE2_CHANNEL_RX8B10BEN", - "GTPE2_CHANNEL_RXCDRFREQRESET", - "GTPE2_CHANNEL_RXGEARBOXSLIP", - "GTPE2_IMUX35_0", - "GTPE2_IMUX18_5", - "GTPE2_CHANNEL_RXCHARISCOMMA2", - "GTPE2_CHANNEL_SCANCLK", - "GTPE2_CHANNEL_TXDATA5", - "GTPE2_LOGIC_OUTS_B21_8", - "GTPE2_IMUX21_6", - "GTPE2_LOGIC_OUTS_B11_7", - "GTPE2_CHANNEL_RXPHOVRDEN", - "GTPE2_BYP4_4", - "GTPE2_IMUX5_5", - "GTPE2_LOGIC_OUTS_B3_5", - "GTPE2_LOGIC_OUTS_B17_9", - "GTPE2_FAN6_4", - "GTPE2_IMUX37_8", - "GTPE2_LOGIC_OUTS_B12_0", - "GTPE2_BYP2_6", - "GTPE2_IMUX7_2", - "GTPE2_CHANNEL_TSTPD4", - "GTPE2_CHANNEL_RXHEADER2", - "GTPE2_FAN7_7", - "GTPE2_IMUX26_0", - "GTPE2_CHANNEL_GTRSVD11", - "GTPE2_LOGIC_OUTS_B20_9", - "GTPE2_CHANNEL_TSTIN1", - "GTPE2_IMUX15_0", - "GTPE2_FAN0_6", - "GTPE2_CHANNEL_RXDATA14", - "GTPE2_LOGIC_OUTS_B22_2", - "GTPE2_IMUX5_3", - "GTPE2_IMUX41_3", - "GTPE2_LOGIC_OUTS_B9_8", - "GTPE2_CHANNEL_LOOPBACK0", - "GTPE2_LOGIC_OUTS_B18_7", - "GTPE2_LOGIC_OUTS_B16_1", - "GTPE2_IMUX38_8", - "GTPE2_IMUX15_5", - "GTPE2_CHANNEL_RXHEADER1", - "GTPE2_CHANNEL_TXPRBSSEL0", - "GTPE2_CHANNEL_RXLPMHFHOLD", - "GTPE2_LOGIC_OUTS_B8_9", - "GTPE2_BYP6_10", - "GTPE2_CLK1_7", - "GTPE2_CTRL1_1", - "GTPE2_CHANNEL_DRPADDR5", - "GTPE2_LOGIC_OUTS_B0_8", - "GTPE2_CHANNEL_TXDATA16", - "GTPE2_CHANNEL_GTRSVD6", - "GTPE2_CHANNEL_RXCHANBONDSEQ", - "GTPE2_IMUX18_7", - "GTPE2_LOGIC_OUTS_B5_2", - "GTPE2_BYP5_9", - "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "GTPE2_IMUX17_2", - "GTPE2_CHANNEL_TXSEQUENCE6", - "GTPE2_FAN6_8", - "GTPE2_IMUX34_9", - "GTPE2_CHANNEL_TXDLYEN", - "GTPE2_IMUX40_4", - "GTPE2_IMUX9_0", - "GTPE2_CHANNEL_TXDATA27", - "GTPE2_IMUX29_5", - "GTPE2_IMUX28_7", - "GTPE2_CHANNEL_PMASCANIN4", - "GTPE2_CHANNEL_PCSRSVDOUT6", - "GTPE2_IMUX43_8", - "GTPE2_IMUX40_7", - "GTPE2_LOGIC_OUTS_B23_10", - "GTPE2_IMUX45_5", - "GTPE2_IMUX4_1", - "GTPE2_IMUX10_1", - "GTPE2_IMUX37_0", - "GTPE2_BYP3_2", - "GTPE2_IMUX28_2", - "GTPE2_CHANNEL_TXDATA26", - "GTPE2_CHANNEL_TXDATA31", - "GTPE2_FAN0_10", - "GTPE2_LOGIC_OUTS_B7_9", - "GTPE2_BYP3_1", - "GTPE2_IMUX23_8", - "GTPE2_CHANNEL_RXCHARISK1", - "GTPE2_BYP5_6", - "GTPE2_CHANNEL_PHYSTATUS", - "GTPE2_CHANNEL_TXINHIBIT", - "GTPE2_CHANNEL_RXUSERRDY", - "GTPE2_IMUX24_6", - "GTPE2_CHANNEL_RXDATA23", - "GTPE2_IMUX13_10", - "GTPE2_IMUX34_3", - "GTPE2_CHANNEL_PMARSVDOUT1", - "GTPE2_IMUX5_4", - "GTPE2_CLK0_6", - "GTPE2_BYP5_8", - "GTPE2_IMUX18_10", - "GTPE2_FAN7_8", - "GTPE2_FAN5_2", - "GTPE2_CTRL0_6", - "GTPE2_CHANNEL_DRPDI10", - "GTPE2_FAN5_0", - "GTPE2_CHANNEL_RXCHARISK0", - "GTPE2_IMUX22_3", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "GTPE2_IMUX5_1", - "GTPE2_CHANNEL_DMONITOROUT1", - "GTPE2_IMUX33_5", - "GTPE2_CHANNEL_DRPDI9", - "GTPE2_CHANNEL_TXMARGIN1", - "GTPE2_IMUX10_3", - "GTPE2_CHANNEL_RXNOTINTABLE1", - "GTPE2_BYP6_9", - "GTPE2_IMUX5_2", - "GTPE2_IMUX38_4", - "GTPE2_IMUX46_4", - "GTPE2_CHANNEL_RXSYNCALLIN", - "GTPE2_CHANNEL_RXSTATUS1", - "GTPE2_IMUX12_7", - "GTPE2_FAN3_8", - "GTPE2_IMUX22_10", - "GTPE2_IMUX20_9", - "GTPE2_LOGIC_OUTS_B11_1", - "GTPE2_CHANNEL_PMASCANIN6", - "GTPE2_CHANNEL_TXSYNCIN", - "GTPE2_CHANNEL_TXSEQUENCE5", - "GTPE2_CHANNEL_TXDLYSRESETDONE", - "GTPE2_LOGIC_OUTS_B0_2", - "GTPE2_IMUX15_4", - "GTPE2_LOGIC_OUTS_B16_6", - "GTPE2_IMUX38_2", - "GTPE2_IMUX16_7", - "GTPE2_IMUX27_9", - "GTPE2_LOGIC_OUTS_B18_8", - "GTPE2_LOGIC_OUTS_B8_0", - "GTPE2_LOGIC_OUTS_B21_2", - "GTPE2_CHANNEL_GTRXOUTCLK_0", - "GTPE2_IMUX41_1", - "GTPE2_CHANNEL_TXUSRCLK", - "GTPE2_IMUX35_7", - "GTPE2_CHANNEL_TXMAINCURSOR5", - "GTPE2_CHANNEL_RXDLYSRESET", - "GTPE2_CHANNEL_DRPDI13", - "GTPE2_LOGIC_OUTS_B6_9", - "GTPE2_CHANNEL_RXOUTCLKSEL2", - "GTPE2_LOGIC_OUTS_B3_8", - "GTPE2_LOGIC_OUTS_B6_4", - "GTPE2_CHANNEL_DMONITOROUT11", - "GTPE2_LOGIC_OUTS_B2_7", - "GTPE2_IMUX6_3", - "GTPE2_IMUX20_0", - "GTPE2_IMUX12_10", - "GTPE2_CTRL0_10", - "GTPE2_CHANNEL_RXCOMMADET", - "GTPE2_CHANNEL_TXPOLARITY", - "GTPE2_CHANNEL_TXPRBSSEL2", - "GTPE2_LOGIC_OUTS_B5_4", - "GTPE2_IMUX37_1", - "GTPE2_CHANNEL_RXADAPTSELTEST13", - "GTPE2_IMUX27_7", - "GTPE2_IMUX44_9", - "GTPE2_IMUX36_10", - "GTPE2_FAN5_6", - "GTPE2_IMUX18_9", - "GTPE2_CLK1_3", - "GTPE2_IMUX26_10", - "GTPE2_IMUX32_6", - "GTPE2_IMUX36_6", - "GTPE2_IMUX14_5", - "GTPE2_LOGIC_OUTS_B18_1", - "GTPE2_IMUX46_9", - "GTPE2_CHANNEL_TXDLYSRESET", - "GTPE2_CHANNEL_RXCHARISK2", - "GTPE2_IMUX28_4", - "GTPE2_CHANNEL_PMARSVDIN2", - "GTPE2_CLK1_8", - "GTPE2_IMUX39_0", - "GTPE2_LOGIC_OUTS_B2_2", - "GTPE2_BYP6_4", - "GTPE2_IMUX30_2", - "GTPE2_LOGIC_OUTS_B10_4", - "GTPE2_CHANNEL_DRPADDR8", - "GTPE2_CHANNEL_DMONITOROUT4", - "GTPE2_IMUX19_6", - "GTPE2_FAN4_10", - "GTPE2_IMUX34_6", - "GTPE2_BYP4_3", - "GTPE2_CHANNEL_TX8B10BEN", - "GTPE2_LOGIC_OUTS_B11_6", - "GTPE2_IMUX28_6", - "GTPE2_CHANNEL_RXOSINTDONE", - "GTPE2_CHANNEL_TXOUTCLKSEL1", - "GTPE2_LOGIC_OUTS_B9_4", - "GTPE2_IMUX8_3", - "GTPE2_CHANNEL_DRPDI4", - "GTPE2_CHANNEL_TXSYSCLKSEL0", - "GTPE2_LOGIC_OUTS_B10_1", - "GTPE2_LOGIC_OUTS_B12_1", - "GTPE2_IMUX17_7", - "GTPE2_IMUX9_1", - "GTPE2_CHANNEL_PMASCANIN5", - "GTPE2_FAN0_3", - "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "GTPE2_BYP2_1", - "GTPE2_CHANNEL_RXOSINTSTROBE", - "GTPE2_IMUX40_8", - "GTPE2_IMUX3_10", - "GTPE2_CHANNEL_LOOPBACK2", - "GTPE2_IMUX35_1", - "GTPE2_LOGIC_OUTS_B19_6", - "GTPE2_CHANNEL_TXDATA25", - "GTPE2_IMUX40_2", - "GTPE2_IMUX8_2", - "GTPE2_CHANNEL_TXSYSCLKSEL1", - "GTPE2_IMUX36_2", - "GTPE2_CHANNEL_RXDLYOVRDEN", - "GTPE2_FAN3_0", - "GTPE2_CHANNEL_RXDATA20", - "GTPE2_IMUX22_7", - "GTPE2_IMUX35_8", - "GTPE2_CHANNEL_DRPDO3", - "GTPE2_CHANNEL_RXOUTCLKSEL0", - "GTPE2_LOGIC_OUTS_B11_3", - "GTPE2_CHANNEL_TXDIFFCTRL2", - "GTPE2_IMUX7_8", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "GTPE2_CHANNEL_RXDEBUGPULSE", - "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "GTPE2_CTRL0_1", - "GTPE2_CHANNEL_TXCHARDISPVAL3", - "GTPE2_LOGIC_OUTS_B2_6", - "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "GTPE2_BYP7_5", - "GTPE2_IMUX0_3", - "GTPE2_CHANNEL_TSTIN3", - "GTPE2_CHANNEL_DRPDI15", - "GTPE2_LOGIC_OUTS_B20_1", - "GTPE2_BYP2_7", - "GTPE2_CHANNEL_EYESCANDATAERROR", - "GTPE2_LOGIC_OUTS_B19_0", - "GTPE2_LOGIC_OUTS_B17_0", - "GTPE2_CHANNEL_RXOSINTCFG0", - "GTPE2_IMUX7_1", - "GTPE2_CHANNEL_RXELECIDLEMODE0", - "GTPE2_CHANNEL_DRPDO4", - "GTPE2_LOGIC_OUTS_B1_9", - "GTPE2_CHANNEL_RXSYNCDONE", - "GTPE2_CHANNEL_DRPADDR1", - "GTPE2_BYP6_8", - "GTPE2_IMUX0_1", - "GTPE2_CHANNEL_RXDATA28", - "GTPE2_IMUX6_8", - "GTPE2_IMUX10_4", - "GTPE2_IMUX46_2", - "GTPE2_IMUX35_2", - "GTPE2_IMUX33_6", - "GTPE2_IMUX7_10", - "GTPE2_CHANNEL_RXCDRRESETRSV", - "GTPE2_BYP7_1", - "GTPE2_CHANNEL_SCANENB", - "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "GTPE2_CHANNEL_TSTIN16", - "GTPE2_CHANNEL_TSTIN4", - "GTPE2_CHANNEL_TXDATA3", - "GTPE2_BYP5_7", - "GTPE2_LOGIC_OUTS_B20_10", - "GTPE2_IMUX33_8", - "GTPE2_CHANNEL_TSTPD2", - "GTPE2_IMUX27_8", - "GTPE2_CHANNEL_RXPHMONITOR4", - "GTPE2_CHANNEL_DRPDI8", - "GTPE2_LOGIC_OUTS_B19_10", - "GTPE2_CLK1_9", - "GTPE2_CHANNEL_TXRESETDONE", - "GTPE2_IMUX3_1", - "GTPE2_IMUX25_3", - "GTPE2_IMUX47_1", - "GTPE2_BYP5_0", - "GTPE2_CHANNEL_SCANIN2", - "GTPE2_IMUX33_1", - "GTPE2_LOGIC_OUTS_B14_3", - "GTPE2_CHANNEL_TXDATA20", - "GTPE2_IMUX26_7", - "GTPE2_LOGIC_OUTS_B4_1", - "GTPE2_BYP6_2", - "GTPE2_IMUX16_9", - "GTPE2_CHANNEL_RXSYSCLKSEL1", - "GTPE2_IMUX41_10", - "GTPE2_CHANNEL_RXCDRHOLD", - "GTPE2_BYP0_3", - "GTPE2_FAN2_9", - "GTPE2_CHANNEL_TXOUTCLKPCS", - "GTPE2_LOGIC_OUTS_B17_5", - "GTPE2_CHANNEL_PLLREFCLK0", - "GTPE2_LOGIC_OUTS_B16_9", - "GTPE2_IMUX37_6", - "GTPE2_CHANNEL_RXPRBSERR", - "GTPE2_LOGIC_OUTS_B11_4", - "GTPE2_IMUX14_0", - "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "GTPE2_CHANNEL_TXDATA29", - "GTPE2_LOGIC_OUTS_B14_7", - "GTPE2_LOGIC_OUTS_B1_1", - "GTPE2_IMUX17_9", - "GTPE2_IMUX21_3", - "GTPE2_LOGIC_OUTS_B14_4", - "GTPE2_CHANNEL_GTRSVD15", - "GTPE2_IMUX24_10", - "GTPE2_LOGIC_OUTS_B0_9", - "GTPE2_CHANNEL_PMASCANOUT6", - "GTPE2_IMUX4_6", - "GTPE2_CHANNEL_RXCHBONDO0", - "GTPE2_LOGIC_OUTS_B11_2", - "GTPE2_CHANNEL_RXADAPTSELTEST10", - "GTPE2_CHANNEL_RXOUTCLK_2", - "GTPE2_BYP4_8", - "GTPE2_CHANNEL_RXDATA4", - "GTPE2_CHANNEL_PCSRSVDIN0", - "GTPE2_CHANNEL_RXADAPTSELTEST2", - "GTPE2_LOGIC_OUTS_B14_1", - "GTPE2_CHANNEL_TXPRBSSEL1", - "GTPE2_LOGIC_OUTS_B15_3", - "GTPE2_LOGIC_OUTS_B13_0", - "GTPE2_CHANNEL_TXPRECURSORINV", - "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "GTPE2_CHANNEL_TXMAINCURSOR1", - "GTPE2_CHANNEL_RXOSINTOVRDEN", - "GTPE2_CHANNEL_TXDATA23", - "GTPE2_CHANNEL_TXRUNDISP0", - "GTPE2_LOGIC_OUTS_B4_2", - "GTPE2_BYP0_4", - "GTPE2_BYP3_6", - "GTPE2_LOGIC_OUTS_B9_5", - "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "GTPE2_CTRL1_10", - "GTPE2_CHANNEL_RXOSINTID02", - "GTPE2_IMUX16_2", - "GTPE2_CHANNEL_RXRATEDONE", - "GTPE2_BYP0_0", - "GTPE2_CHANNEL_TXCOMWAKE", - "GTPE2_IMUX43_3", - "GTPE2_LOGIC_OUTS_B13_7", - "GTPE2_CHANNEL_TXPOSTCURSOR4", - "GTPE2_IMUX22_4", - "GTPE2_IMUX21_1", - "GTPE2_FAN1_9", - "GTPE2_IMUX29_7", - "GTPE2_LOGIC_OUTS_B8_6", - "GTPE2_BYP7_8", - "GTPE2_IMUX23_5", - "GTPE2_CHANNEL_DRPDO10", - "GTPE2_CHANNEL_DRPDI6", - "GTPE2_IMUX32_1", - "GTPE2_IMUX22_8", - "GTPE2_FAN7_0", - "GTPE2_CHANNEL_RXLPMRESET", - "GTPE2_IMUX13_2", - "GTPE2_CHANNEL_PCSRSVDIN10", - "GTPE2_IMUX46_1", - "GTPE2_CHANNEL_TSTIN18", - "GTPE2_CHANNEL_TXPHDLYRESET", - "GTPE2_FAN6_3", - "GTPE2_CHANNEL_DMONITOROUT3", - "GTPE2_IMUX41_0", - "GTPE2_IMUX13_6", - "GTPE2_IMUX11_1", - "GTPE2_CHANNEL_PCSRSVDOUT9", - "GTPE2_CHANNEL_DRPEN", - "GTPE2_IMUX38_10", - "GTPE2_CHANNEL_TSTPDOVRDB", - "GTPE2_BYP2_8", - "GTPE2_CTRL1_0", - "GTPE2_IMUX2_5", - "GTPE2_CHANNEL_RXDLYEN", - "GTPE2_LOGIC_OUTS_B6_1", - "GTPE2_FAN7_10", - "GTPE2_IMUX17_0", - "GTPE2_CHANNEL_TSTIN19", - "GTPE2_IMUX29_8", - "GTPE2_IMUX11_5", - "GTPE2_LOGIC_OUTS_B22_5", - "GTPE2_CHANNEL_RXDATA3", - "GTPE2_CHANNEL_RXOSINTCFG1", - "GTPE2_IMUX24_5", - "GTPE2_CHANNEL_GTRSVD10", - "GTPE2_LOGIC_OUTS_B20_5", - "GTPE2_LOGIC_OUTS_B20_3", - "GTPE2_CHANNEL_TXSYNCDONE", - "GTPE2_BYP0_6", - "GTPE2_LOGIC_OUTS_B1_0", - "GTPE2_LOGIC_OUTS_B1_4", - "GTPE2_IMUX42_9", - "GTPE2_BYP6_5", - "GTPE2_IMUX47_5", - "GTPE2_CHANNEL_LOOPBACK1", - "GTPE2_IMUX13_9", - "GTPE2_CHANNEL_TXPHALIGNEN", - "GTPE2_IMUX12_4", - "GTPE2_CHANNEL_RXADAPTSELTEST11", - "GTPE2_IMUX44_6", - "GTPE2_CHANNEL_TXELECIDLE", - "GTPE2_CTRL0_0", - "GTPE2_LOGIC_OUTS_B3_7", - "GTPE2_IMUX35_4", - "GTPE2_CHANNEL_RXCHBONDI0", - "GTPE2_CHANNEL_TXCHARDISPMODE1", - "GTPE2_LOGIC_OUTS_B7_10", - "GTPE2_CHANNEL_RXOSINTEN", - "GTPE2_LOGIC_OUTS_B21_3", - "GTPE2_CHANNEL_TXDATA15", - "GTPE2_BYP0_7", - "GTPE2_IMUX2_6", - "GTPE2_BYP3_10", - "GTPE2_FAN1_1", - "GTPE2_CHANNEL_TSTIN6", - "GTPE2_FAN1_4", - "GTPE2_IMUX14_2", - "GTPE2_CHANNEL_PMASCANIN3", - "GTPE2_CHANNEL_TXDATA18", - "GTPE2_IMUX0_4", - "GTPE2_CHANNEL_TSTIN17", - "GTPE2_LOGIC_OUTS_B3_4", - "GTPE2_LOGIC_OUTS_B1_8", - "GTPE2_BYP1_8", - "GTPE2_CHANNEL_RXSTATUS2", - "GTPE2_BYP5_2", - "GTPE2_CHANNEL_PCSRSVDIN11", - "GTPE2_IMUX38_9", - "GTPE2_BYP7_6", - "GTPE2_CHANNEL_PMASCANCLK1", - "GTPE2_CHANNEL_RXBUFSTATUS0", - "GTPE2_IMUX11_0", - "GTPE2_FAN4_9", - "GTPE2_LOGIC_OUTS_B12_8", - "GTPE2_BYP1_3", - "GTPE2_BYP0_10", - "GTPE2_CHANNEL_RXOSCALRESET", - "GTPE2_IMUX6_0", - "GTPE2_CHANNEL_TSTIN11", - "GTPE2_CLK0_3", - "GTPE2_CHANNEL_CLKRSVD1", - "GTPE2_FAN3_10", - "GTPE2_IMUX19_0", - "GTPE2_CHANNEL_RXHEADER0", - "GTPE2_CHANNEL_TXPRBSFORCEERR", - "GTPE2_CHANNEL_PCSRSVDIN13", - "GTPE2_IMUX46_7", - "GTPE2_CHANNEL_PCSRSVDOUT14", - "GTPE2_LOGIC_OUTS_B15_10", - "GTPE2_CHANNEL_TSTPD3", - "GTPE2_LOGIC_OUTS_B12_2", - "GTPE2_IMUX45_1", - "GTPE2_IMUX0_0", - "GTPE2_IMUX39_10", - "GTPE2_CHANNEL_DMONITOROUT10", - "GTPE2_CHANNEL_RXCDRLOCK", - "GTPE2_IMUX4_2", - "GTPE2_CHANNEL_TXMAINCURSOR2", - "GTPE2_CHANNEL_PCSRSVDIN9", - "GTPE2_IMUX10_5", - "GTPE2_CHANNEL_PMASCANCLK0", - "GTPE2_IMUX18_8", - "GTPE2_CHANNEL_TXSYNCMODE", - "GTPE2_CHANNEL_TXN_PAD", - "GTPE2_CHANNEL_TXPMARESET", - "GTPE2_IMUX43_10", - "GTPE2_BYP5_10", - "GTPE2_CHANNEL_DRPADDR0", - "GTPE2_CHANNEL_PCSRSVDOUT1", - "GTPE2_CHANNEL_PMARSVDIN4", - "GTPE2_IMUX14_1", - "GTPE2_CHANNEL_SCANIN5", - "GTPE2_LOGIC_OUTS_B0_1", - "GTPE2_CHANNEL_PCSRSVDOUT12", - "GTPE2_CHANNEL_DRPDI7", - "GTPE2_IMUX26_6", - "GTPE2_IMUX17_6", - "GTPE2_LOGIC_OUTS_B1_7", - "GTPE2_CHANNEL_RXDATA7", - "GTPE2_CHANNEL_TXCHARDISPMODE3", - "GTPE2_IMUX26_8", - "GTPE2_IMUX0_9", - "GTPE2_FAN3_6", - "GTPE2_IMUX46_0", - "GTPE2_CHANNEL_TSTIN7", - "GTPE2_LOGIC_OUTS_B20_7", - "GTPE2_LOGIC_OUTS_B17_2", - "GTPE2_CHANNEL_TXCHARDISPVAL1", - "GTPE2_CHANNEL_TXSEQUENCE4", - "GTPE2_CHANNEL_TXPOSTCURSOR2", - "GTPE2_CHANNEL_DRPDI2", - "GTPE2_FAN2_10", - "GTPE2_CHANNEL_RXBUFSTATUS2", - "GTPE2_IMUX1_7", - "GTPE2_IMUX10_7", - "GTPE2_CHANNEL_SCANOUT4", - "GTPE2_LOGIC_OUTS_B18_0", - "GTPE2_CHANNEL_DRPDO9", - "GTPE2_FAN6_9", - "GTPE2_IMUX4_7", - "GTPE2_CHANNEL_TSTPD1", - "GTPE2_IMUX39_6", - "GTPE2_CHANNEL_TXPRECURSOR2", - "GTPE2_IMUX43_0", - "GTPE2_FAN1_6", - "GTPE2_BYP1_1", - "GTPE2_FAN5_3", - "GTPE2_CHANNEL_DMONITOROUT2", - "GTPE2_LOGIC_OUTS_B19_4", - "GTPE2_CHANNEL_PMASCANMODEB", - "GTPE2_IMUX37_9", - "GTPE2_LOGIC_OUTS_B22_3", - "GTPE2_FAN1_3", - "GTPE2_IMUX5_9", - "GTPE2_CHANNEL_RXELECIDLE", - "GTPE2_IMUX34_8", - "GTPE2_FAN2_4", - "GTPE2_IMUX24_2", - "GTPE2_CHANNEL_GTTXOUTCLK_0", - "GTPE2_LOGIC_OUTS_B22_4", - "GTPE2_IMUX34_4", - "GTPE2_LOGIC_OUTS_B0_10", - "GTPE2_IMUX29_6", - "GTPE2_IMUX45_10", - "GTPE2_CLK1_6", - "GTPE2_CHANNEL_PMASCANENB", - "GTPE2_CHANNEL_TXDATA8", - "GTPE2_CLK0_7", - "GTPE2_IMUX30_1", - "GTPE2_LOGIC_OUTS_B11_8", - "GTPE2_CHANNEL_RXHEADERVALID", - "GTPE2_FAN5_1", - "GTPE2_CHANNEL_PCSRSVDOUT3", - "GTPE2_IMUX2_9", - "GTPE2_CHANNEL_TXPIPPMPD", - "GTPE2_IMUX44_5", - "GTPE2_IMUX22_0", - "GTPE2_CHANNEL_TXPIPPMEN", - "GTPE2_FAN5_10", - "GTPE2_BYP1_0", - "GTPE2_IMUX11_7", - "GTPE2_CHANNEL_TXDATA10", - "GTPE2_IMUX34_2", - "GTPE2_LOGIC_OUTS_B4_0", - "GTPE2_CHANNEL_GTRSVD5", - "GTPE2_LOGIC_OUTS_B8_7", - "GTPE2_IMUX44_4", - "GTPE2_IMUX41_5", - "GTPE2_CHANNEL_TXDLYOVRDEN", - "GTPE2_IMUX37_4", - "GTPE2_BYP6_6", - "GTPE2_IMUX44_10", - "GTPE2_CHANNEL_DRPADDR2", - "GTPE2_CLK0_5", - "GTPE2_CHANNEL_DRPDI11", - "GTPE2_LOGIC_OUTS_B7_1", - "GTPE2_IMUX8_0", - "GTPE2_IMUX25_4", - "GTPE2_LOGIC_OUTS_B7_8", - "GTPE2_CHANNEL_TXBUFSTATUS0", - "GTPE2_IMUX30_3", - "GTPE2_IMUX27_4", - "GTPE2_LOGIC_OUTS_B8_8", - "GTPE2_CHANNEL_DRPADDR6", - "GTPE2_IMUX0_7", - "GTPE2_IMUX42_8", - "GTPE2_IMUX33_4", - "GTPE2_BYP0_9", - "GTPE2_LOGIC_OUTS_B6_0", - "GTPE2_LOGIC_OUTS_B22_8", - "GTPE2_CHANNEL_RXOSINTID01", - "GTPE2_IMUX40_5", - "GTPE2_CHANNEL_DRPDO6", - "GTPE2_CHANNEL_RXSYSCLKSEL0", - "GTPE2_CLK1_2", - "GTPE2_FAN5_9", - "GTPE2_IMUX6_10", - "GTPE2_LOGIC_OUTS_B12_4", - "GTPE2_IMUX13_7", - "GTPE2_IMUX25_7", - "GTPE2_IMUX7_3", - "GTPE2_BYP7_9", - "GTPE2_CHANNEL_RXCHBONDO2", - "GTPE2_LOGIC_OUTS_B17_1", - "GTPE2_LOGIC_OUTS_B15_2", - "GTPE2_CHANNEL_PCSRSVDIN5", - "GTPE2_LOGIC_OUTS_B5_0", - "GTPE2_LOGIC_OUTS_B3_10", - "GTPE2_CHANNEL_DRPDI12", - "GTPE2_IMUX23_9", - "GTPE2_LOGIC_OUTS_B9_0", - "GTPE2_IMUX7_4", - "GTPE2_CHANNEL_TSTIN0", - "GTPE2_FAN5_8", - "GTPE2_LOGIC_OUTS_B13_1", - "GTPE2_IMUX32_0", - "GTPE2_CHANNEL_RXPRBSSEL2", - "GTPE2_IMUX45_2", - "GTPE2_CHANNEL_DRPDI1", - "GTPE2_CHANNEL_TXDATA19", - "GTPE2_FAN6_7", - "GTPE2_CHANNEL_RXDATA11", - "GTPE2_CHANNEL_RXCOMMADETEN", - "GTPE2_CHANNEL_TXN", - "GTPE2_CHANNEL_TXRATEDONE", - "GTPE2_IMUX39_5", - "GTPE2_FAN0_2", - "GTPE2_IMUX18_0", - "GTPE2_IMUX16_10", - "GTPE2_CHANNEL_PMASCANOUT0", - "GTPE2_CHANNEL_PMASCANIN1", - "GTPE2_LOGIC_OUTS_B13_3", - "GTPE2_IMUX36_0", - "GTPE2_BYP7_4", - "GTPE2_CHANNEL_RXPOLARITY", - "GTPE2_LOGIC_OUTS_B7_0", - "GTPE2_CHANNEL_DRPDO8", - "GTPE2_LOGIC_OUTS_B0_0", - "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "GTPE2_IMUX4_3", - "GTPE2_CHANNEL_SCANOUT1", - "GTPE2_CHANNEL_PCSRSVDOUT15", - "GTPE2_CHANNEL_TXOUTCLKSEL0", - "GTPE2_CHANNEL_DRPCLK", - "GTPE2_LOGIC_OUTS_B20_4", - "GTPE2_LOGIC_OUTS_B15_6", - "GTPE2_LOGIC_OUTS_B13_4", - "GTPE2_BYP2_0", - "GTPE2_IMUX9_7", - "GTPE2_IMUX11_9", - "GTPE2_IMUX2_10", - "GTPE2_IMUX9_4", - "GTPE2_IMUX3_6", - "GTPE2_CHANNEL_RXDATA19", - "GTPE2_LOGIC_OUTS_B23_0", - "GTPE2_CHANNEL_SCANIN1", - "GTPE2_IMUX8_1", - "GTPE2_CHANNEL_TXPIPPMSEL", - "GTPE2_IMUX13_0", - "GTPE2_IMUX30_10", - "GTPE2_BYP4_7", - "GTPE2_LOGIC_OUTS_B23_7", - "GTPE2_CHANNEL_EYESCANRESET", - "GTPE2_IMUX30_9", - "GTPE2_IMUX37_7", - "GTPE2_IMUX25_8", - "GTPE2_FAN4_0", - "GTPE2_IMUX38_7", - "GTPE2_FAN5_4", - "GTPE2_FAN1_2", - "GTPE2_IMUX22_6", - "GTPE2_CHANNEL_TX8B10BBYPASS3", - "GTPE2_IMUX2_7", - "GTPE2_LOGIC_OUTS_B5_5", - "GTPE2_IMUX26_1", - "GTPE2_IMUX42_5", - "GTPE2_CHANNEL_TXMARGIN0", - "GTPE2_CHANNEL_RXDATA12", - "GTPE2_IMUX9_5", - "GTPE2_CHANNEL_TX8B10BBYPASS1", - "GTPE2_LOGIC_OUTS_B11_5", - "GTPE2_CLK0_1", - "GTPE2_IMUX31_8", - "GTPE2_LOGIC_OUTS_B18_9", - "GTPE2_FAN0_4", - "GTPE2_IMUX9_8", - "GTPE2_CHANNEL_DRPDI3", - "GTPE2_LOGIC_OUTS_B8_5", - "GTPE2_LOGIC_OUTS_B16_10", - "GTPE2_BYP1_6", - "GTPE2_IMUX47_0", - "GTPE2_CHANNEL_RXNOTINTABLE3", - "GTPE2_IMUX42_10", - "GTPE2_IMUX8_4", - "GTPE2_CHANNEL_RXDATA10", - "GTPE2_CHANNEL_RXRATE1", - "GTPE2_IMUX47_10", - "GTPE2_CHANNEL_TXSEQUENCE3", - "GTPE2_IMUX38_3", - "GTPE2_IMUX43_4", - "GTPE2_CHANNEL_TXRUNDISP1", - "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "GTPE2_BYP3_4", - "GTPE2_FAN4_5", - "GTPE2_BYP0_5", - "GTPE2_IMUX32_2", - "GTPE2_FAN4_7", - "GTPE2_IMUX3_4", - "GTPE2_CHANNEL_TXDATA9", - "GTPE2_FAN2_3", - "GTPE2_CHANNEL_PLLREFCLK1", - "GTPE2_LOGIC_OUTS_B0_6", - "GTPE2_LOGIC_OUTS_B23_1", - "GTPE2_IMUX45_4", - "GTPE2_CHANNEL_RXADAPTSELTEST0", - "GTPE2_LOGIC_OUTS_B15_1", - "GTPE2_BYP1_10", - "GTPE2_LOGIC_OUTS_B0_7", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", - "GTPE2_IMUX27_10", - "GTPE2_IMUX32_7", - "GTPE2_BYP3_9", - "GTPE2_CHANNEL_PMASCANCLK2", - "GTPE2_LOGIC_OUTS_B21_0", - "GTPE2_IMUX20_10", - "GTPE2_CHANNEL_RXPHMONITOR1", - "GTPE2_IMUX15_6", - "GTPE2_IMUX1_8", - "GTPE2_IMUX33_9", - "GTPE2_IMUX12_8", - "GTPE2_IMUX28_0", - "GTPE2_CHANNEL_RXDATA31", - "GTPE2_IMUX31_4", - "GTPE2_CTRL1_8", - "GTPE2_LOGIC_OUTS_B14_0", - "GTPE2_CHANNEL_RXDLYTESTENB", - "GTPE2_CHANNEL_TXP", - "GTPE2_IMUX33_10", - "GTPE2_IMUX9_10", - "GTPE2_IMUX34_1", - "GTPE2_LOGIC_OUTS_B18_5", - "GTPE2_FAN3_4", - "GTPE2_BYP5_5", - "GTPE2_CHANNEL_RXP", - "GTPE2_LOGIC_OUTS_B6_7", - "GTPE2_FAN3_1", - "GTPE2_IMUX8_10", - "GTPE2_IMUX26_9", - "GTPE2_FAN7_5", - "GTPE2_IMUX1_10", - "GTPE2_IMUX1_3", - "GTPE2_CHANNEL_RXDATA13", - "GTPE2_CHANNEL_TXSWING", - "GTPE2_CHANNEL_PLLCLK0", - "GTPE2_CHANNEL_PCSRSVDOUT11", - "GTPE2_FAN2_7", - "GTPE2_IMUX21_2", - "GTPE2_CHANNEL_RXCLKCORCNT1", - "GTPE2_CHANNEL_TXDIFFCTRL1", - "GTPE2_IMUX21_4", - "GTPE2_LOGIC_OUTS_B22_9", - "GTPE2_IMUX39_2", - "GTPE2_IMUX19_9", - "GTPE2_IMUX40_0", - "GTPE2_CHANNEL_TSTPD0", - "GTPE2_CHANNEL_TXCHARISK2", - "GTPE2_CHANNEL_RXSTATUS0", - "GTPE2_IMUX19_5", - "GTPE2_IMUX11_2", - "GTPE2_CHANNEL_PMASCANOUT2", - "GTPE2_LOGIC_OUTS_B11_10", - "GTPE2_IMUX38_1", - "GTPE2_CHANNEL_RXCOMWAKEDET", - "GTPE2_CHANNEL_TSTIN13", - "GTPE2_IMUX1_6", - "GTPE2_CHANNEL_RXCDROVRDEN", - "GTPE2_LOGIC_OUTS_B8_2", - "GTPE2_LOGIC_OUTS_B20_8", - "GTPE2_CHANNEL_DMONITOROUT5", - "GTPE2_IMUX35_9", - "GTPE2_IMUX27_0", - "GTPE2_LOGIC_OUTS_B7_4", - "GTPE2_IMUX30_0", - "GTPE2_IMUX23_3", - "GTPE2_CHANNEL_RXN", - "GTPE2_IMUX42_6", - "GTPE2_IMUX14_3", - "GTPE2_IMUX16_3", - "GTPE2_LOGIC_OUTS_B5_10", - "GTPE2_BYP4_10", - "GTPE2_CHANNEL_TXPOSTCURSORINV", - "GTPE2_CHANNEL_DRPDO12", - "GTPE2_IMUX35_5", - "GTPE2_IMUX21_10", - "GTPE2_BYP4_6", - "GTPE2_CHANNEL_RXADAPTSELTEST5", - "GTPE2_IMUX23_4", - "GTPE2_LOGIC_OUTS_B16_7", - "GTPE2_BYP2_4", - "GTPE2_IMUX27_3", - "GTPE2_CLK1_0", - "GTPE2_IMUX13_3", - "GTPE2_IMUX43_2", - "GTPE2_FAN2_0", - "GTPE2_CTRL0_4", - "GTPE2_IMUX21_0", - "GTPE2_LOGIC_OUTS_B12_5", - "GTPE2_CHANNEL_GTRSVD0", - "GTPE2_IMUX47_3", - "GTPE2_IMUX4_5", - "GTPE2_CHANNEL_TXPCSRESET", - "GTPE2_IMUX47_2", - "GTPE2_CLK0_2", - "GTPE2_CHANNEL_RXBUFSTATUS1", - "GTPE2_CTRL0_3", - "GTPE2_IMUX47_7", - "GTPE2_IMUX39_4", - "GTPE2_IMUX42_7", - "GTPE2_IMUX17_3", - "GTPE2_LOGIC_OUTS_B7_7", - "GTPE2_IMUX10_9", - "GTPE2_CHANNEL_TXSTARTSEQ", - "GTPE2_CHANNEL_TXSEQUENCE2", - "GTPE2_CHANNEL_GTTXRESET", - "GTPE2_IMUX21_8", - "GTPE2_CHANNEL_TXRUNDISP3", - "GTPE2_FAN4_6", - "GTPE2_CHANNEL_TXDATA28", - "GTPE2_CHANNEL_TSTIN9", - "GTPE2_CHANNEL_RXUSRCLK2", - "GTPE2_CHANNEL_RXCHARISCOMMA3", - "GTPE2_IMUX8_9", - "GTPE2_CHANNEL_RXPD1", - "GTPE2_LOGIC_OUTS_B7_3", - "GTPE2_CHANNEL_TXCOMINIT", - "GTPE2_LOGIC_OUTS_B15_9", - "GTPE2_FAN0_8", - "GTPE2_BYP3_0", - "GTPE2_IMUX6_9", - "GTPE2_CHANNEL_DRPDO13", - "GTPE2_CTRL1_9", - "GTPE2_LOGIC_OUTS_B22_7", - "GTPE2_IMUX40_3", - "GTPE2_LOGIC_OUTS_B20_2", - "GTPE2_FAN4_3", - "GTPE2_IMUX1_0", - "GTPE2_LOGIC_OUTS_B19_8", - "GTPE2_LOGIC_OUTS_B3_3", - "GTPE2_IMUX34_7", - "GTPE2_IMUX0_10", - "GTPE2_CHANNEL_TXRUNDISP2", - "GTPE2_IMUX19_7", - "GTPE2_LOGIC_OUTS_B19_7", - "GTPE2_CHANNEL_RXBUFRESET", - "GTPE2_CHANNEL_RXSYNCOUT", - "GTPE2_IMUX12_9", - "GTPE2_IMUX15_9", - "GTPE2_LOGIC_OUTS_B6_6", - "GTPE2_CTRL1_4", - "GTPE2_CTRL0_9", - "GTPE2_IMUX33_0", - "GTPE2_IMUX11_3", - "GTPE2_FAN0_1", - "GTPE2_IMUX32_5", - "GTPE2_IMUX42_3", - "GTPE2_LOGIC_OUTS_B14_8", - "GTPE2_CHANNEL_TXCHARDISPMODE2", - "GTPE2_IMUX7_6", - "GTPE2_FAN4_1", - "GTPE2_CHANNEL_RXN_PAD", - "GTPE2_CHANNEL_DRPADDR3", - "GTPE2_IMUX23_6", - "GTPE2_BYP7_3", - "GTPE2_BYP5_1", - "GTPE2_CHANNEL_TXPHDLYPD", - "GTPE2_IMUX41_9", - "GTPE2_BYP4_2", - "GTPE2_IMUX22_1", - "GTPE2_LOGIC_OUTS_B3_2", - "GTPE2_CHANNEL_DMONITOROUT8", - "GTPE2_CHANNEL_DRPRDY", - "GTPE2_IMUX45_7", - "GTPE2_BYP7_0", - "GTPE2_IMUX3_2", - "GTPE2_IMUX18_3", - "GTPE2_IMUX4_9", - "GTPE2_IMUX19_10", - "GTPE2_IMUX3_9", - "GTPE2_CHANNEL_RXDATA22", - "GTPE2_FAN4_2", - "GTPE2_IMUX17_5", - "GTPE2_CHANNEL_GTRSVD7", - "GTPE2_IMUX25_2", - "GTPE2_LOGIC_OUTS_B4_3", - "GTPE2_LOGIC_OUTS_B5_3", - "GTPE2_CHANNEL_CFGRESET", - "GTPE2_IMUX27_6", - "GTPE2_IMUX24_9", - "GTPE2_IMUX23_10", - "GTPE2_CHANNEL_TXPRECURSOR3", - "GTPE2_CHANNEL_PMASCANCLK3", - "GTPE2_BYP1_7", - "GTPE2_FAN1_5", - "GTPE2_LOGIC_OUTS_B0_3", - "GTPE2_LOGIC_OUTS_B18_10", - "GTPE2_CHANNEL_TXSYNCOUT", - "GTPE2_IMUX28_5", - "GTPE2_IMUX16_0", - "GTPE2_BYP2_10", - "GTPE2_IMUX36_8", - "GTPE2_CLK1_1", - "GTPE2_CHANNEL_TXDATA24", - "GTPE2_IMUX32_10", - "GTPE2_LOGIC_OUTS_B12_10", - "GTPE2_LOGIC_OUTS_B23_9", - "GTPE2_IMUX24_7", - "GTPE2_LOGIC_OUTS_B21_9", - "GTPE2_IMUX37_3", - "GTPE2_CHANNEL_RXCHBONDI3", - "GTPE2_LOGIC_OUTS_B6_8", - "GTPE2_LOGIC_OUTS_B16_3", - "GTPE2_FAN5_7", - "GTPE2_BYP0_2", - "GTPE2_CHANNEL_RXCHBONDEN", - "GTPE2_IMUX9_9", - "GTPE2_CHANNEL_TSTIN5", - "GTPE2_CHANNEL_PCSRSVDIN1", - "GTPE2_CHANNEL_RXSLIDE", - "GTPE2_IMUX25_0", - "GTPE2_CHANNEL_RXDATA2", - "GTPE2_IMUX5_10", - "GTPE2_CHANNEL_PLL1REFCLK", - "GTPE2_IMUX6_7", - "GTPE2_LOGIC_OUTS_B18_4", - "GTPE2_CHANNEL_RXRESETDONE", - "GTPE2_CHANNEL_GTRSVD2", - "GTPE2_CHANNEL_TXPOSTCURSOR1", - "GTPE2_CHANNEL_RXDFEXYDEN", - "GTPE2_IMUX44_1", - "GTPE2_LOGIC_OUTS_B19_1", - "GTPE2_IMUX28_3", - "GTPE2_IMUX9_3", - "GTPE2_BYP2_3", - "GTPE2_LOGIC_OUTS_B1_10", - "GTPE2_CHANNEL_GTRSVD14", - "GTPE2_CHANNEL_TXPRECURSOR1", - "GTPE2_CHANNEL_RXCLKCORCNT0", - "GTPE2_CTRL0_5", - "GTPE2_CHANNEL_PCSRSVDOUT2", - "GTPE2_FAN7_9", - "GTPE2_LOGIC_OUTS_B12_3", - "GTPE2_IMUX20_8", - "GTPE2_CHANNEL_GTRSVD12", - "GTPE2_IMUX35_3", - "GTPE2_CTRL1_5", - "GTPE2_CHANNEL_EYESCANTRIGGER", - "GTPE2_CHANNEL_TXDATA30", - "GTPE2_IMUX26_3", - "GTPE2_FAN0_0", - "GTPE2_CHANNEL_RXCDRRESET" - ], - "sites": [ - { - "prefix": "GTPE2_CHANNEL", - "y_coord": 0, - "type": "GTPE2_CHANNEL", - "site_pins": { - "RXCHARISCOMMA3": "GTPE2_CHANNEL_RXCHARISCOMMA3", - "RXSTATUS0": "GTPE2_CHANNEL_RXSTATUS0", - "DRPDO13": "GTPE2_CHANNEL_DRPDO13", - "TSTPD0": "GTPE2_CHANNEL_TSTPD0", - "RXBUFRESET": "GTPE2_CHANNEL_RXBUFRESET", - "RXVALID": "GTPE2_CHANNEL_RXVALID", - "SCANIN1": "GTPE2_CHANNEL_SCANIN1", - "RXCHBONDLEVEL2": "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "TXDATA25": "GTPE2_CHANNEL_TXDATA25", - "GTPRXN": "GTPE2_CHANNEL_RXN", - "PCSRSVDOUT6": "GTPE2_CHANNEL_PCSRSVDOUT6", - "TXDATA31": "GTPE2_CHANNEL_TXDATA31", - "CFGRESET": "GTPE2_CHANNEL_CFGRESET", - "GTPTXP": "GTPE2_CHANNEL_TXP", - "TXPIPPMEN": "GTPE2_CHANNEL_TXPIPPMEN", - "TXDATA14": "GTPE2_CHANNEL_TXDATA14", - "TXRATE0": "GTPE2_CHANNEL_TXRATE0", - "DMONITOROUT6": "GTPE2_CHANNEL_DMONITOROUT6", - "PMASCANOUT5": "GTPE2_CHANNEL_PMASCANOUT5", - "RXDATA28": "GTPE2_CHANNEL_RXDATA28", - "TXOUTCLK": "GTPE2_CHANNEL_GTTXOUTCLK_0", - "RXCHANBONDSEQ": "GTPE2_CHANNEL_RXCHANBONDSEQ", - "DRPDI4": "GTPE2_CHANNEL_DRPDI4", - "TXDATA15": "GTPE2_CHANNEL_TXDATA15", - "RXDATA26": "GTPE2_CHANNEL_RXDATA26", - "TXHEADER1": "GTPE2_CHANNEL_TXHEADER1", - "RXCHBONDLEVEL1": "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "RXNOTINTABLE1": "GTPE2_CHANNEL_RXNOTINTABLE1", - "RXPD0": "GTPE2_CHANNEL_RXPD0", - "DMONITOROUT14": "GTPE2_CHANNEL_DMONITOROUT14", - "TXBUFSTATUS1": "GTPE2_CHANNEL_TXBUFSTATUS1", - "TXCOMSAS": "GTPE2_CHANNEL_TXCOMSAS", - "RXCDRRESETRSV": "GTPE2_CHANNEL_RXCDRRESETRSV", - "RXSTATUS2": "GTPE2_CHANNEL_RXSTATUS2", - "RXOSINTCFG2": "GTPE2_CHANNEL_RXOSINTCFG2", - "PCSRSVDIN11": "GTPE2_CHANNEL_PCSRSVDIN11", - "PHYSTATUS": "GTPE2_CHANNEL_PHYSTATUS", - "RXGEARBOXSLIP": "GTPE2_CHANNEL_RXGEARBOXSLIP", - "DMONITOROUT3": "GTPE2_CHANNEL_DMONITOROUT3", - "TXMAINCURSOR1": "GTPE2_CHANNEL_TXMAINCURSOR1", - "GTRSVD11": "GTPE2_CHANNEL_GTRSVD11", - "DMONITOROUT7": "GTPE2_CHANNEL_DMONITOROUT7", - "TXSYNCDONE": "GTPE2_CHANNEL_TXSYNCDONE", - "PCSRSVDIN6": "GTPE2_CHANNEL_PCSRSVDIN6", - "RXBYTEISALIGNED": "GTPE2_CHANNEL_RXBYTEISALIGNED", - "PCSRSVDIN4": "GTPE2_CHANNEL_PCSRSVDIN4", - "RXOSINTCFG3": "GTPE2_CHANNEL_RXOSINTCFG3", - "TXCHARDISPVAL3": "GTPE2_CHANNEL_TXCHARDISPVAL3", - "TXCHARDISPMODE3": "GTPE2_CHANNEL_TXCHARDISPMODE3", - "RXDATA29": "GTPE2_CHANNEL_RXDATA29", - "TXOUTCLKPCS": "GTPE2_CHANNEL_TXOUTCLKPCS", - "RXCLKCORCNT1": "GTPE2_CHANNEL_RXCLKCORCNT1", - "RXADAPTSELTEST2": "GTPE2_CHANNEL_RXADAPTSELTEST2", - "TXINHIBIT": "GTPE2_CHANNEL_TXINHIBIT", - "TXDATA13": "GTPE2_CHANNEL_TXDATA13", - "TXPISOPD": "GTPE2_CHANNEL_TXPISOPD", - "RXPMARESET": "GTPE2_CHANNEL_RXPMARESET", - "TSTIN14": "GTPE2_CHANNEL_TSTIN14", - "PCSRSVDIN13": "GTPE2_CHANNEL_PCSRSVDIN13", - "PMASCANCLK3": "GTPE2_CHANNEL_PMASCANCLK3", - "TXDATA8": "GTPE2_CHANNEL_TXDATA8", - "PCSRSVDIN1": "GTPE2_CHANNEL_PCSRSVDIN1", - "DRPDI12": "GTPE2_CHANNEL_DRPDI12", - "RXOSINTID02": "GTPE2_CHANNEL_RXOSINTID02", - "PMARSVDOUT1": "GTPE2_CHANNEL_PMARSVDOUT1", - "RXCDRHOLD": "GTPE2_CHANNEL_RXCDRHOLD", - "TXDATA10": "GTPE2_CHANNEL_TXDATA10", - "DRPDI6": "GTPE2_CHANNEL_DRPDI6", - "TSTIN2": "GTPE2_CHANNEL_TSTIN2", - "DRPWE": "GTPE2_CHANNEL_DRPWE", - "RXOUTCLKSEL2": "GTPE2_CHANNEL_RXOUTCLKSEL2", - "DRPADDR5": "GTPE2_CHANNEL_DRPADDR5", - "TSTIN15": "GTPE2_CHANNEL_TSTIN15", - "RXPHSLIPMONITOR0": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "RXPHDLYRESET": "GTPE2_CHANNEL_RXPHDLYRESET", - "RXPHSLIPMONITOR1": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "TXPRBSFORCEERR": "GTPE2_CHANNEL_TXPRBSFORCEERR", - "TXHEADER2": "GTPE2_CHANNEL_TXHEADER2", - "PCSRSVDOUT0": "GTPE2_CHANNEL_PCSRSVDOUT0", - "TXPD0": "GTPE2_CHANNEL_TXPD0", - "RXDATA4": "GTPE2_CHANNEL_RXDATA4", - "RXHEADER1": "GTPE2_CHANNEL_RXHEADER1", - "RXOSINTID00": "GTPE2_CHANNEL_RXOSINTID00", - "RXSTARTOFSEQ1": "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "RXOSOVRDEN": "GTPE2_CHANNEL_RXOSOVRDEN", - "RXADAPTSELTEST11": "GTPE2_CHANNEL_RXADAPTSELTEST11", - "PCSRSVDOUT1": "GTPE2_CHANNEL_PCSRSVDOUT1", - "TXPIPPMPD": "GTPE2_CHANNEL_TXPIPPMPD", - "TXDLYOVRDEN": "GTPE2_CHANNEL_TXDLYOVRDEN", - "RXDATA21": "GTPE2_CHANNEL_RXDATA21", - "RXCHBONDO1": "GTPE2_CHANNEL_RXCHBONDO1", - "TXOUTCLKSEL0": "GTPE2_CHANNEL_TXOUTCLKSEL0", - "TXDEEMPH": "GTPE2_CHANNEL_TXDEEMPH", - "TXDATA5": "GTPE2_CHANNEL_TXDATA5", - "GTRSVD1": "GTPE2_CHANNEL_GTRSVD1", - "TSTPD3": "GTPE2_CHANNEL_TSTPD3", - "TXMAINCURSOR6": "GTPE2_CHANNEL_TXMAINCURSOR6", - "TSTIN5": "GTPE2_CHANNEL_TSTIN5", - "TXPRECURSOR2": "GTPE2_CHANNEL_TXPRECURSOR2", - "TXRATEMODE": "GTPE2_CHANNEL_TXRATEMODE", - "RXLPMLFOVRDEN": "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "RXOUTCLKSEL0": "GTPE2_CHANNEL_RXOUTCLKSEL0", - "TXUSRCLK2": "GTPE2_CHANNEL_TXUSRCLK2", - "RXPHDLYPD": "GTPE2_CHANNEL_RXPHDLYPD", - "RXOSINTID03": "GTPE2_CHANNEL_RXOSINTID03", - "RXDATA3": "GTPE2_CHANNEL_RXDATA3", - "DRPDO6": "GTPE2_CHANNEL_DRPDO6", - "TXPOSTCURSORINV": "GTPE2_CHANNEL_TXPOSTCURSORINV", - "TXMAINCURSOR2": "GTPE2_CHANNEL_TXMAINCURSOR2", - "TSTPD1": "GTPE2_CHANNEL_TSTPD1", - "RXPHMONITOR0": "GTPE2_CHANNEL_RXPHMONITOR0", - "TSTIN18": "GTPE2_CHANNEL_TSTIN18", - "DRPDO4": "GTPE2_CHANNEL_DRPDO4", - "RXOSCALRESET": "GTPE2_CHANNEL_RXOSCALRESET", - "RXCHARISCOMMA1": "GTPE2_CHANNEL_RXCHARISCOMMA1", - "RXADAPTSELTEST4": "GTPE2_CHANNEL_RXADAPTSELTEST4", - "RXMCOMMAALIGNEN": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "TXPHDLYPD": "GTPE2_CHANNEL_TXPHDLYPD", - "TXPOSTCURSOR2": "GTPE2_CHANNEL_TXPOSTCURSOR2", - "PMASCANCLK0": "GTPE2_CHANNEL_PMASCANCLK0", - "PCSRSVDOUT15": "GTPE2_CHANNEL_PCSRSVDOUT15", - "SCANIN3": "GTPE2_CHANNEL_SCANIN3", - "TXELECIDLE": "GTPE2_CHANNEL_TXELECIDLE", - "RXDATA27": "GTPE2_CHANNEL_RXDATA27", - "TXRATE2": "GTPE2_CHANNEL_TXRATE2", - "EYESCANRESET": "GTPE2_CHANNEL_EYESCANRESET", - "DRPDI13": "GTPE2_CHANNEL_DRPDI13", - "PMASCANCLK1": "GTPE2_CHANNEL_PMASCANCLK1", - "RXCHBONDLEVEL0": "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "RXPHMONITOR3": "GTPE2_CHANNEL_RXPHMONITOR3", - "TXSTARTSEQ": "GTPE2_CHANNEL_TXSTARTSEQ", - "RXRATE1": "GTPE2_CHANNEL_RXRATE1", - "DRPDO0": "GTPE2_CHANNEL_DRPDO0", - "TXBUFDIFFCTRL0": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "RXDATA18": "GTPE2_CHANNEL_RXDATA18", - "DRPDO1": "GTPE2_CHANNEL_DRPDO1", - "RXADAPTSELTEST10": "GTPE2_CHANNEL_RXADAPTSELTEST10", - "RXDLYBYPASS": "GTPE2_CHANNEL_RXDLYBYPASS", - "TXDIFFCTRL0": "GTPE2_CHANNEL_TXDIFFCTRL0", - "RXPRBSCNTRESET": "GTPE2_CHANNEL_RXPRBSCNTRESET", - "RXCLKCORCNT0": "GTPE2_CHANNEL_RXCLKCORCNT0", - "TSTCLK1": "GTPE2_CHANNEL_TSTCLK1", - "PLL1CLK": "GTPE2_CHANNEL_PLL1CLK", - "DMONITORCLK": "GTPE2_CHANNEL_DMONITORCLK", - "PLL0REFCLK": "GTPE2_CHANNEL_PLL0REFCLK", - "SCANMODEB": "GTPE2_CHANNEL_SCANMODEB", - "TSTIN12": "GTPE2_CHANNEL_TSTIN12", - "TSTIN7": "GTPE2_CHANNEL_TSTIN7", - "TXDATA19": "GTPE2_CHANNEL_TXDATA19", - "RXPCSRESET": "GTPE2_CHANNEL_RXPCSRESET", - "TXPRBSSEL2": "GTPE2_CHANNEL_TXPRBSSEL2", - "RXPHOVRDEN": "GTPE2_CHANNEL_RXPHOVRDEN", - "TSTIN11": "GTPE2_CHANNEL_TSTIN11", - "RXDATA6": "GTPE2_CHANNEL_RXDATA6", - "SETERRSTATUS": "GTPE2_CHANNEL_SETERRSTATUS", - "RXOSINTID01": "GTPE2_CHANNEL_RXOSINTID01", - "TXHEADER0": "GTPE2_CHANNEL_TXHEADER0", - "DRPDI8": "GTPE2_CHANNEL_DRPDI8", - "TXDIFFCTRL3": "GTPE2_CHANNEL_TXDIFFCTRL3", - "TXDATA18": "GTPE2_CHANNEL_TXDATA18", - "DMONITOROUT5": "GTPE2_CHANNEL_DMONITOROUT5", - "RXDATA1": "GTPE2_CHANNEL_RXDATA1", - "RX8B10BEN": "GTPE2_CHANNEL_RX8B10BEN", - "TXCHARDISPVAL1": "GTPE2_CHANNEL_TXCHARDISPVAL1", - "TXRATE1": "GTPE2_CHANNEL_TXRATE1", - "TXDATA21": "GTPE2_CHANNEL_TXDATA21", - "PMASCANOUT2": "GTPE2_CHANNEL_PMASCANOUT2", - "PCSRSVDIN10": "GTPE2_CHANNEL_PCSRSVDIN10", - "GTRSVD2": "GTPE2_CHANNEL_GTRSVD2", - "RXADAPTSELTEST5": "GTPE2_CHANNEL_RXADAPTSELTEST5", - "LOOPBACK0": "GTPE2_CHANNEL_LOOPBACK0", - "DRPADDR4": "GTPE2_CHANNEL_DRPADDR4", - "TXCHARDISPVAL0": "GTPE2_CHANNEL_TXCHARDISPVAL0", - "PMASCANIN4": "GTPE2_CHANNEL_PMASCANIN4", - "DRPADDR8": "GTPE2_CHANNEL_DRPADDR8", - "RXSYSCLKSEL1": "GTPE2_CHANNEL_RXSYSCLKSEL1", - "RXADAPTSELTEST8": "GTPE2_CHANNEL_RXADAPTSELTEST8", - "TXSYNCOUT": "GTPE2_CHANNEL_TXSYNCOUT", - "RXCHBONDMASTER": "GTPE2_CHANNEL_RXCHBONDMASTER", - "TXPRECURSORINV": "GTPE2_CHANNEL_TXPRECURSORINV", - "PCSRSVDOUT2": "GTPE2_CHANNEL_PCSRSVDOUT2", - "TXPOLARITY": "GTPE2_CHANNEL_TXPOLARITY", - "RXADAPTSELTEST9": "GTPE2_CHANNEL_RXADAPTSELTEST9", - "DMONITOROUT0": "GTPE2_CHANNEL_DMONITOROUT0", - "TXUSERRDY": "GTPE2_CHANNEL_TXUSERRDY", - "DMONITOROUT4": "GTPE2_CHANNEL_DMONITOROUT4", - "TXDLYEN": "GTPE2_CHANNEL_TXDLYEN", - "TSTIN10": "GTPE2_CHANNEL_TSTIN10", - "RXPHSLIPMONITOR4": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "RXCHBONDI3": "GTPE2_CHANNEL_RXCHBONDI3", - "TXPIPPMSTEPSIZE2": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "RXDDIEN": "GTPE2_CHANNEL_RXDDIEN", - "RXPRBSSEL1": "GTPE2_CHANNEL_RXPRBSSEL1", - "PCSRSVDIN5": "GTPE2_CHANNEL_PCSRSVDIN5", - "TXPMARESETDONE": "GTPE2_CHANNEL_TXPMARESETDONE", - "TXRUNDISP3": "GTPE2_CHANNEL_TXRUNDISP3", - "RXUSRCLK": "GTPE2_CHANNEL_RXUSRCLK", - "TXSEQUENCE4": "GTPE2_CHANNEL_TXSEQUENCE4", - "RXELECIDLEMODE1": "GTPE2_CHANNEL_RXELECIDLEMODE1", - "DRPDO9": "GTPE2_CHANNEL_DRPDO9", - "RXCOMMADETEN": "GTPE2_CHANNEL_RXCOMMADETEN", - "GTRESETSEL": "GTPE2_CHANNEL_GTRESETSEL", - "SCANCLK": "GTPE2_CHANNEL_SCANCLK", - "TXDLYHOLD": "GTPE2_CHANNEL_TXDLYHOLD", - "PMASCANIN0": "GTPE2_CHANNEL_PMASCANIN0", - "TXPRBSSEL1": "GTPE2_CHANNEL_TXPRBSSEL1", - "LOOPBACK2": "GTPE2_CHANNEL_LOOPBACK2", - "RXDATA2": "GTPE2_CHANNEL_RXDATA2", - "PCSRSVDOUT9": "GTPE2_CHANNEL_PCSRSVDOUT9", - "TXDATA7": "GTPE2_CHANNEL_TXDATA7", - "RXOSINTSTROBESTARTED": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "RXADAPTSELTEST13": "GTPE2_CHANNEL_RXADAPTSELTEST13", - "TXOUTCLKFABRIC": "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "TXBUFDIFFCTRL2": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "PCSRSVDOUT4": "GTPE2_CHANNEL_PCSRSVDOUT4", - "TXRUNDISP1": "GTPE2_CHANNEL_TXRUNDISP1", - "RXCHBONDO2": "GTPE2_CHANNEL_RXCHBONDO2", - "TXSEQUENCE5": "GTPE2_CHANNEL_TXSEQUENCE5", - "DRPADDR6": "GTPE2_CHANNEL_DRPADDR6", - "DRPADDR3": "GTPE2_CHANNEL_DRPADDR3", - "RXSTARTOFSEQ0": "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "TXUSRCLK": "GTPE2_CHANNEL_TXUSRCLK", - "TXDATA29": "GTPE2_CHANNEL_TXDATA29", - "RXPHALIGNDONE": "GTPE2_CHANNEL_RXPHALIGNDONE", - "TSTIN4": "GTPE2_CHANNEL_TSTIN4", - "GTRSVD5": "GTPE2_CHANNEL_GTRSVD5", - "PCSRSVDOUT7": "GTPE2_CHANNEL_PCSRSVDOUT7", - "RXADAPTSELTEST3": "GTPE2_CHANNEL_RXADAPTSELTEST3", - "PCSRSVDIN8": "GTPE2_CHANNEL_PCSRSVDIN8", - "TXPD1": "GTPE2_CHANNEL_TXPD1", - "GTRSVD9": "GTPE2_CHANNEL_GTRSVD9", - "RXDATA15": "GTPE2_CHANNEL_RXDATA15", - "RXCHARISK3": "GTPE2_CHANNEL_RXCHARISK3", - "TXPRECURSOR3": "GTPE2_CHANNEL_TXPRECURSOR3", - "RXPHMONITOR1": "GTPE2_CHANNEL_RXPHMONITOR1", - "RXRATE0": "GTPE2_CHANNEL_RXRATE0", - "RXOUTCLK": "GTPE2_CHANNEL_GTRXOUTCLK_0", - "RXOSINTDONE": "GTPE2_CHANNEL_RXOSINTDONE", - "RXDATAVALID1": "GTPE2_CHANNEL_RXDATAVALID1", - "RXNOTINTABLE0": "GTPE2_CHANNEL_RXNOTINTABLE0", - "RESETOVRD": "GTPE2_CHANNEL_RESETOVRD", - "TXDATA26": "GTPE2_CHANNEL_TXDATA26", - "RXDATAVALID0": "GTPE2_CHANNEL_RXDATAVALID0", - "PMASCANOUT3": "GTPE2_CHANNEL_PMASCANOUT3", - "TSTPD4": "GTPE2_CHANNEL_TSTPD4", - "PCSRSVDOUT13": "GTPE2_CHANNEL_PCSRSVDOUT13", - "GTRSVD13": "GTPE2_CHANNEL_GTRSVD13", - "TXDATA20": "GTPE2_CHANNEL_TXDATA20", - "TXDIFFPD": "GTPE2_CHANNEL_TXDIFFPD", - "RXSTATUS1": "GTPE2_CHANNEL_RXSTATUS1", - "RXCHARISK0": "GTPE2_CHANNEL_RXCHARISK0", - "TXBUFSTATUS0": "GTPE2_CHANNEL_TXBUFSTATUS0", - "TSTCLK0": "GTPE2_CHANNEL_TSTCLK0", - "DMONITOROUT8": "GTPE2_CHANNEL_DMONITOROUT8", - "SCANOUT4": "GTPE2_CHANNEL_SCANOUT4", - "RXELECIDLE": "GTPE2_CHANNEL_RXELECIDLE", - "PMASCANCLK2": "GTPE2_CHANNEL_PMASCANCLK2", - "RXDATA16": "GTPE2_CHANNEL_RXDATA16", - "RXCHBONDI1": "GTPE2_CHANNEL_RXCHBONDI1", - "RXCHANREALIGN": "GTPE2_CHANNEL_RXCHANREALIGN", - "RXDISPERR3": "GTPE2_CHANNEL_RXDISPERR3", - "PMASCANENB": "GTPE2_CHANNEL_PMASCANENB", - "TXDATA22": "GTPE2_CHANNEL_TXDATA22", - "PMASCANOUT0": "GTPE2_CHANNEL_PMASCANOUT0", - "TXPIPPMOVRDEN": "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "RXOSINTNTRLEN": "GTPE2_CHANNEL_RXOSINTNTRLEN", - "TXDATA17": "GTPE2_CHANNEL_TXDATA17", - "RXCOMMADET": "GTPE2_CHANNEL_RXCOMMADET", - "TXOUTCLKSEL2": "GTPE2_CHANNEL_TXOUTCLKSEL2", - "TXDLYSRESET": "GTPE2_CHANNEL_TXDLYSRESET", - "TXPHALIGNEN": "GTPE2_CHANNEL_TXPHALIGNEN", - "DRPDO2": "GTPE2_CHANNEL_DRPDO2", - "TXRATEDONE": "GTPE2_CHANNEL_TXRATEDONE", - "TXDATA6": "GTPE2_CHANNEL_TXDATA6", - "DRPDI1": "GTPE2_CHANNEL_DRPDI1", - "RXDISPERR0": "GTPE2_CHANNEL_RXDISPERR0", - "RXDATA13": "GTPE2_CHANNEL_RXDATA13", - "PMASCANIN1": "GTPE2_CHANNEL_PMASCANIN1", - "TXDATA3": "GTPE2_CHANNEL_TXDATA3", - "PCSRSVDIN12": "GTPE2_CHANNEL_PCSRSVDIN12", - "TXRUNDISP2": "GTPE2_CHANNEL_TXRUNDISP2", - "RXDEBUGPULSE": "GTPE2_CHANNEL_RXDEBUGPULSE", - "RXDATA20": "GTPE2_CHANNEL_RXDATA20", - "GTRSVD14": "GTPE2_CHANNEL_GTRSVD14", - "RXCHBONDO0": "GTPE2_CHANNEL_RXCHBONDO0", - "TXDATA23": "GTPE2_CHANNEL_TXDATA23", - "TXPDELECIDLEMODE": "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "TXMAINCURSOR3": "GTPE2_CHANNEL_TXMAINCURSOR3", - "RXLPMOSINTNTRLEN": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "RXDLYSRESET": "GTPE2_CHANNEL_RXDLYSRESET", - "GTRSVD15": "GTPE2_CHANNEL_GTRSVD15", - "RXLPMHFHOLD": "GTPE2_CHANNEL_RXLPMHFHOLD", - "RXDLYEN": "GTPE2_CHANNEL_RXDLYEN", - "TXPIPPMSEL": "GTPE2_CHANNEL_TXPIPPMSEL", - "PCSRSVDIN2": "GTPE2_CHANNEL_PCSRSVDIN2", - "GTRSVD7": "GTPE2_CHANNEL_GTRSVD7", - "DRPDI15": "GTPE2_CHANNEL_DRPDI15", - "RXCHBONDEN": "GTPE2_CHANNEL_RXCHBONDEN", - "TXMAINCURSOR5": "GTPE2_CHANNEL_TXMAINCURSOR5", - "TXGEARBOXREADY": "GTPE2_CHANNEL_TXGEARBOXREADY", - "TXSEQUENCE3": "GTPE2_CHANNEL_TXSEQUENCE3", - "DRPDI5": "GTPE2_CHANNEL_DRPDI5", - "TXCHARDISPMODE0": "GTPE2_CHANNEL_TXCHARDISPMODE0", - "TXDATA27": "GTPE2_CHANNEL_TXDATA27", - "RXSYNCALLIN": "GTPE2_CHANNEL_RXSYNCALLIN", - "EYESCANDATAERROR": "GTPE2_CHANNEL_EYESCANDATAERROR", - "SCANIN2": "GTPE2_CHANNEL_SCANIN2", - "GTRSVD10": "GTPE2_CHANNEL_GTRSVD10", - "RXPRBSSEL2": "GTPE2_CHANNEL_RXPRBSSEL2", - "RXCHBONDI0": "GTPE2_CHANNEL_RXCHBONDI0", - "TXBUFDIFFCTRL1": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "RXADAPTSELTEST6": "GTPE2_CHANNEL_RXADAPTSELTEST6", - "DRPDO8": "GTPE2_CHANNEL_DRPDO8", - "TXDLYBYPASS": "GTPE2_CHANNEL_TXDLYBYPASS", - "TX8B10BBYPASS3": "GTPE2_CHANNEL_TX8B10BBYPASS3", - "DMONFIFORESET": "GTPE2_CHANNEL_DMONFIFORESET", - "RXDATA30": "GTPE2_CHANNEL_RXDATA30", - "TXCHARDISPVAL2": "GTPE2_CHANNEL_TXCHARDISPVAL2", - "TSTIN8": "GTPE2_CHANNEL_TSTIN8", - "RXDATA24": "GTPE2_CHANNEL_RXDATA24", - "GTPTXN": "GTPE2_CHANNEL_TXN", - "RXSYNCMODE": "GTPE2_CHANNEL_RXSYNCMODE", - "TXDATA1": "GTPE2_CHANNEL_TXDATA1", - "TXPRECURSOR0": "GTPE2_CHANNEL_TXPRECURSOR0", - "RXSYNCOUT": "GTPE2_CHANNEL_RXSYNCOUT", - "TSTIN19": "GTPE2_CHANNEL_TSTIN19", - "RXRATEMODE": "GTPE2_CHANNEL_RXRATEMODE", - "DRPDI11": "GTPE2_CHANNEL_DRPDI11", - "RXCDRRESET": "GTPE2_CHANNEL_RXCDRRESET", - "RXOSINTCFG0": "GTPE2_CHANNEL_RXOSINTCFG0", - "PMASCANRSTEN": "GTPE2_CHANNEL_PMASCANRSTEN", - "CLKRSVD1": "GTPE2_CHANNEL_CLKRSVD1", - "TX8B10BBYPASS0": "GTPE2_CHANNEL_TX8B10BBYPASS0", - "PCSRSVDOUT14": "GTPE2_CHANNEL_PCSRSVDOUT14", - "RXNOTINTABLE2": "GTPE2_CHANNEL_RXNOTINTABLE2", - "PCSRSVDIN3": "GTPE2_CHANNEL_PCSRSVDIN3", - "RXOSINTPD": "GTPE2_CHANNEL_RXOSINTPD", - "DMONITOROUT12": "GTPE2_CHANNEL_DMONITOROUT12", - "TXPOSTCURSOR3": "GTPE2_CHANNEL_TXPOSTCURSOR3", - "TXPCSRESET": "GTPE2_CHANNEL_TXPCSRESET", - "TXPHDLYRESET": "GTPE2_CHANNEL_TXPHDLYRESET", - "RXOSINTHOLD": "GTPE2_CHANNEL_RXOSINTHOLD", - "TXPRECURSOR4": "GTPE2_CHANNEL_TXPRECURSOR4", - "RXBYTEREALIGN": "GTPE2_CHANNEL_RXBYTEREALIGN", - "TSTPD2": "GTPE2_CHANNEL_TSTPD2", - "TXSEQUENCE6": "GTPE2_CHANNEL_TXSEQUENCE6", - "TXCHARDISPMODE1": "GTPE2_CHANNEL_TXCHARDISPMODE1", - "RXPRBSSEL0": "GTPE2_CHANNEL_RXPRBSSEL0", - "TSTIN6": "GTPE2_CHANNEL_TSTIN6", - "DRPEN": "GTPE2_CHANNEL_DRPEN", - "TSTIN1": "GTPE2_CHANNEL_TSTIN1", - "DRPDO7": "GTPE2_CHANNEL_DRPDO7", - "PCSRSVDIN7": "GTPE2_CHANNEL_PCSRSVDIN7", - "DRPDI3": "GTPE2_CHANNEL_DRPDI3", - "TSTIN3": "GTPE2_CHANNEL_TSTIN3", - "RXDLYSRESETDONE": "GTPE2_CHANNEL_RXDLYSRESETDONE", - "RXCOMINITDET": "GTPE2_CHANNEL_RXCOMINITDET", - "DRPADDR7": "GTPE2_CHANNEL_DRPADDR7", - "RXLPMLFHOLD": "GTPE2_CHANNEL_RXLPMLFHOLD", - "TXPIPPMSTEPSIZE0": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "TXCHARISK2": "GTPE2_CHANNEL_TXCHARISK2", - "RXDATA9": "GTPE2_CHANNEL_RXDATA9", - "RXBUFSTATUS2": "GTPE2_CHANNEL_RXBUFSTATUS2", - "DRPDI0": "GTPE2_CHANNEL_DRPDI0", - "GTRSVD4": "GTPE2_CHANNEL_GTRSVD4", - "RXSYNCIN": "GTPE2_CHANNEL_RXSYNCIN", - "RXLPMHFOVRDEN": "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "SCANOUT0": "GTPE2_CHANNEL_SCANOUT0", - "TXPHALIGNDONE": "GTPE2_CHANNEL_TXPHALIGNDONE", - "TXDATA30": "GTPE2_CHANNEL_TXDATA30", - "RXCHBONDI2": "GTPE2_CHANNEL_RXCHBONDI2", - "TX8B10BEN": "GTPE2_CHANNEL_TX8B10BEN", - "DRPDO11": "GTPE2_CHANNEL_DRPDO11", - "RXCOMWAKEDET": "GTPE2_CHANNEL_RXCOMWAKEDET", - "RXDLYOVRDEN": "GTPE2_CHANNEL_RXDLYOVRDEN", - "PLL0CLK": "GTPE2_CHANNEL_PLL0CLK", - "RXOUTCLKSEL1": "GTPE2_CHANNEL_RXOUTCLKSEL1", - "PMASCANIN2": "GTPE2_CHANNEL_PMASCANIN2", - "TXDIFFCTRL1": "GTPE2_CHANNEL_TXDIFFCTRL1", - "SCANOUT3": "GTPE2_CHANNEL_SCANOUT3", - "RXOUTCLKPCS": "GTPE2_CHANNEL_RXOUTCLKPCS", - "LOOPBACK1": "GTPE2_CHANNEL_LOOPBACK1", - "DRPDO5": "GTPE2_CHANNEL_DRPDO5", - "SCANIN0": "GTPE2_CHANNEL_SCANIN0", - "DRPDO15": "GTPE2_CHANNEL_DRPDO15", - "DRPADDR1": "GTPE2_CHANNEL_DRPADDR1", - "RXOSINTTESTOVRDEN": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "TXPOSTCURSOR4": "GTPE2_CHANNEL_TXPOSTCURSOR4", - "DMONITOROUT9": "GTPE2_CHANNEL_DMONITOROUT9", - "RXDATA23": "GTPE2_CHANNEL_RXDATA23", - "TXDATA24": "GTPE2_CHANNEL_TXDATA24", - "RXDISPERR1": "GTPE2_CHANNEL_RXDISPERR1", - "RXSYNCDONE": "GTPE2_CHANNEL_RXSYNCDONE", - "TX8B10BBYPASS2": "GTPE2_CHANNEL_TX8B10BBYPASS2", - "TXDATA28": "GTPE2_CHANNEL_TXDATA28", - "PLL1REFCLK": "GTPE2_CHANNEL_PLL1REFCLK", - "TXRESETDONE": "GTPE2_CHANNEL_TXRESETDONE", - "TXDIFFCTRL2": "GTPE2_CHANNEL_TXDIFFCTRL2", - "RXOSINTSTROBEDONE": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "DRPDI10": "GTPE2_CHANNEL_DRPDI10", - "SCANOUT1": "GTPE2_CHANNEL_SCANOUT1", - "DRPDI14": "GTPE2_CHANNEL_DRPDI14", - "GTRSVD8": "GTPE2_CHANNEL_GTRSVD8", - "RXHEADER2": "GTPE2_CHANNEL_RXHEADER2", - "TXSYSCLKSEL1": "GTPE2_CHANNEL_TXSYSCLKSEL1", - "RXADAPTSELTEST1": "GTPE2_CHANNEL_RXADAPTSELTEST1", - "TXPHINITDONE": "GTPE2_CHANNEL_TXPHINITDONE", - "RXPOLARITY": "GTPE2_CHANNEL_RXPOLARITY", - "RXPHSLIPMONITOR3": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "RXOUTCLKFABRIC": "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "RXOSHOLD": "GTPE2_CHANNEL_RXOSHOLD", - "TXRUNDISP0": "GTPE2_CHANNEL_TXRUNDISP0", - "DMONITOROUT13": "GTPE2_CHANNEL_DMONITOROUT13", - "TXCHARDISPMODE2": "GTPE2_CHANNEL_TXCHARDISPMODE2", - "TXDATA16": "GTPE2_CHANNEL_TXDATA16", - "RXDFEXYDEN": "GTPE2_CHANNEL_RXDFEXYDEN", - "RXADAPTSELTEST0": "GTPE2_CHANNEL_RXADAPTSELTEST0", - "RXCHANISALIGNED": "GTPE2_CHANNEL_RXCHANISALIGNED", - "PCSRSVDOUT11": "GTPE2_CHANNEL_PCSRSVDOUT11", - "DRPRDY": "GTPE2_CHANNEL_DRPRDY", - "RXDATA25": "GTPE2_CHANNEL_RXDATA25", - "RXCHARISCOMMA2": "GTPE2_CHANNEL_RXCHARISCOMMA2", - "TXPHINIT": "GTPE2_CHANNEL_TXPHINIT", - "TXOUTCLKSEL1": "GTPE2_CHANNEL_TXOUTCLKSEL1", - "TX8B10BBYPASS1": "GTPE2_CHANNEL_TX8B10BBYPASS1", - "RXPHMONITOR2": "GTPE2_CHANNEL_RXPHMONITOR2", - "RXCHARISK1": "GTPE2_CHANNEL_RXCHARISK1", - "RXPHALIGNEN": "GTPE2_CHANNEL_RXPHALIGNEN", - "RXDATA12": "GTPE2_CHANNEL_RXDATA12", - "TSTIN16": "GTPE2_CHANNEL_TSTIN16", - "PCSRSVDOUT10": "GTPE2_CHANNEL_PCSRSVDOUT10", - "RXCDROVRDEN": "GTPE2_CHANNEL_RXCDROVRDEN", - "TXPIPPMSTEPSIZE4": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "RXDLYTESTENB": "GTPE2_CHANNEL_RXDLYTESTENB", - "RXOOBRESET": "GTPE2_CHANNEL_RXOOBRESET", - "PMASCANOUT6": "GTPE2_CHANNEL_PMASCANOUT6", - "TXCHARISK0": "GTPE2_CHANNEL_TXCHARISK0", - "TXDATA12": "GTPE2_CHANNEL_TXDATA12", - "EYESCANMODE": "GTPE2_CHANNEL_EYESCANMODE", - "DRPDI7": "GTPE2_CHANNEL_DRPDI7", - "RXLPMRESET": "GTPE2_CHANNEL_RXLPMRESET", - "RXDATA11": "GTPE2_CHANNEL_RXDATA11", - "TXPRECURSOR1": "GTPE2_CHANNEL_TXPRECURSOR1", - "TXCOMWAKE": "GTPE2_CHANNEL_TXCOMWAKE", - "TXCHARISK3": "GTPE2_CHANNEL_TXCHARISK3", - "TXSWING": "GTPE2_CHANNEL_TXSWING", - "SCANIN5": "GTPE2_CHANNEL_SCANIN5", - "SCANIN4": "GTPE2_CHANNEL_SCANIN4", - "TXPHALIGN": "GTPE2_CHANNEL_TXPHALIGN", - "TXMAINCURSOR4": "GTPE2_CHANNEL_TXMAINCURSOR4", - "DRPDO14": "GTPE2_CHANNEL_DRPDO14", - "DMONITOROUT2": "GTPE2_CHANNEL_DMONITOROUT2", - "RXCDRFREQRESET": "GTPE2_CHANNEL_RXCDRFREQRESET", - "GTRXRESET": "GTPE2_CHANNEL_GTRXRESET", - "TXSYNCMODE": "GTPE2_CHANNEL_TXSYNCMODE", - "TSTPDOVRDB": "GTPE2_CHANNEL_TSTPDOVRDB", - "RXCOMSASDET": "GTPE2_CHANNEL_RXCOMSASDET", - "PCSRSVDOUT3": "GTPE2_CHANNEL_PCSRSVDOUT3", - "RXOSINTSTROBE": "GTPE2_CHANNEL_RXOSINTSTROBE", - "PCSRSVDIN15": "GTPE2_CHANNEL_PCSRSVDIN15", - "PMASCANIN6": "GTPE2_CHANNEL_PMASCANIN6", - "TXCHARISK1": "GTPE2_CHANNEL_TXCHARISK1", - "PMASCANIN3": "GTPE2_CHANNEL_PMASCANIN3", - "TXPOSTCURSOR0": "GTPE2_CHANNEL_TXPOSTCURSOR0", - "EYESCANTRIGGER": "GTPE2_CHANNEL_EYESCANTRIGGER", - "TXSEQUENCE2": "GTPE2_CHANNEL_TXSEQUENCE2", - "GTRSVD0": "GTPE2_CHANNEL_GTRSVD0", - "CLKRSVD0": "GTPE2_CHANNEL_CLKRSVD0", - "RXPMARESETDONE": "GTPE2_CHANNEL_RXPMARESETDONE", - "DRPADDR0": "GTPE2_CHANNEL_DRPADDR0", - "TXPHDLYTSTCLK": "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "RXRATE2": "GTPE2_CHANNEL_RXRATE2", - "DMONITOROUT10": "GTPE2_CHANNEL_DMONITOROUT10", - "TXDATA0": "GTPE2_CHANNEL_TXDATA0", - "RXDATA22": "GTPE2_CHANNEL_RXDATA22", - "RXCHBONDSLAVE": "GTPE2_CHANNEL_RXCHBONDSLAVE", - "TXPMARESET": "GTPE2_CHANNEL_TXPMARESET", - "TXCOMFINISH": "GTPE2_CHANNEL_TXCOMFINISH", - "TXDETECTRX": "GTPE2_CHANNEL_TXDETECTRX", - "PMASCANIN5": "GTPE2_CHANNEL_PMASCANIN5", - "DRPADDR2": "GTPE2_CHANNEL_DRPADDR2", - "TSTIN17": "GTPE2_CHANNEL_TSTIN17", - "RXCHARISK2": "GTPE2_CHANNEL_RXCHARISK2", - "TXDLYUPDOWN": "GTPE2_CHANNEL_TXDLYUPDOWN", - "PMARSVDIN0": "GTPE2_CHANNEL_PMARSVDIN0", - "SIGVALIDCLK": "GTPE2_CHANNEL_SIGVALIDCLK", - "TXMARGIN0": "GTPE2_CHANNEL_TXMARGIN0", - "GTPRXP": "GTPE2_CHANNEL_RXP", - "DMONITOROUT11": "GTPE2_CHANNEL_DMONITOROUT11", - "RXDATA7": "GTPE2_CHANNEL_RXDATA7", - "TXDATA2": "GTPE2_CHANNEL_TXDATA2", - "DMONITOROUT1": "GTPE2_CHANNEL_DMONITOROUT1", - "TXCOMINIT": "GTPE2_CHANNEL_TXCOMINIT", - "RXRESETDONE": "GTPE2_CHANNEL_RXRESETDONE", - "TSTIN9": "GTPE2_CHANNEL_TSTIN9", - "TXSYSCLKSEL0": "GTPE2_CHANNEL_TXSYSCLKSEL0", - "TXDLYTESTENB": "GTPE2_CHANNEL_TXDLYTESTENB", - "PCSRSVDOUT5": "GTPE2_CHANNEL_PCSRSVDOUT5", - "RXCHARISCOMMA0": "GTPE2_CHANNEL_RXCHARISCOMMA0", - "RXOSINTOVRDEN": "GTPE2_CHANNEL_RXOSINTOVRDEN", - "RXCHBONDO3": "GTPE2_CHANNEL_RXCHBONDO3", - "PCSRSVDOUT12": "GTPE2_CHANNEL_PCSRSVDOUT12", - "DRPDI2": "GTPE2_CHANNEL_DRPDI2", - "TXPOSTCURSOR1": "GTPE2_CHANNEL_TXPOSTCURSOR1", - "PCSRSVDOUT8": "GTPE2_CHANNEL_PCSRSVDOUT8", - "GTRSVD6": "GTPE2_CHANNEL_GTRSVD6", - "DRPDO10": "GTPE2_CHANNEL_DRPDO10", - "GTTXRESET": "GTPE2_CHANNEL_GTTXRESET", - "RXDATA10": "GTPE2_CHANNEL_RXDATA10", - "RXRATEDONE": "GTPE2_CHANNEL_RXRATEDONE", - "TXDLYSRESETDONE": "GTPE2_CHANNEL_TXDLYSRESETDONE", - "RXOSINTCFG1": "GTPE2_CHANNEL_RXOSINTCFG1", - "RXDATA14": "GTPE2_CHANNEL_RXDATA14", - "RXPHSLIPMONITOR2": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "TXPIPPMSTEPSIZE1": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "RXPRBSERR": "GTPE2_CHANNEL_RXPRBSERR", - "TXSEQUENCE1": "GTPE2_CHANNEL_TXSEQUENCE1", - "DRPDO12": "GTPE2_CHANNEL_DRPDO12", - "GTRSVD12": "GTPE2_CHANNEL_GTRSVD12", - "RXOSINTEN": "GTPE2_CHANNEL_RXOSINTEN", - "RXDATA19": "GTPE2_CHANNEL_RXDATA19", - "RXDATA17": "GTPE2_CHANNEL_RXDATA17", - "TSTIN13": "GTPE2_CHANNEL_TSTIN13", - "RXHEADER0": "GTPE2_CHANNEL_RXHEADER0", - "PMARSVDIN3": "GTPE2_CHANNEL_PMARSVDIN3", - "RXBUFSTATUS1": "GTPE2_CHANNEL_RXBUFSTATUS1", - "PMASCANMODEB": "GTPE2_CHANNEL_PMASCANMODEB", - "DRPDO3": "GTPE2_CHANNEL_DRPDO3", - "PCSRSVDIN14": "GTPE2_CHANNEL_PCSRSVDIN14", - "TXDATA9": "GTPE2_CHANNEL_TXDATA9", - "PMARSVDOUT0": "GTPE2_CHANNEL_PMARSVDOUT0", - "RXUSERRDY": "GTPE2_CHANNEL_RXUSERRDY", - "RXDATA8": "GTPE2_CHANNEL_RXDATA8", - "RXDISPERR2": "GTPE2_CHANNEL_RXDISPERR2", - "RXSLIDE": "GTPE2_CHANNEL_RXSLIDE", - "TXPRBSSEL0": "GTPE2_CHANNEL_TXPRBSSEL0", - "RXOSINTSTARTED": "GTPE2_CHANNEL_RXOSINTSTARTED", - "TXMARGIN2": "GTPE2_CHANNEL_TXMARGIN2", - "SCANENB": "GTPE2_CHANNEL_SCANENB", - "RXDATA31": "GTPE2_CHANNEL_RXDATA31", - "PMARSVDIN4": "GTPE2_CHANNEL_PMARSVDIN4", - "PMASCANOUT1": "GTPE2_CHANNEL_PMASCANOUT1", - "RXPD1": "GTPE2_CHANNEL_RXPD1", - "TXDATA11": "GTPE2_CHANNEL_TXDATA11", - "PCSRSVDIN9": "GTPE2_CHANNEL_PCSRSVDIN9", - "TXDATA4": "GTPE2_CHANNEL_TXDATA4", - "PMARSVDIN1": "GTPE2_CHANNEL_PMARSVDIN1", - "RXADAPTSELTEST7": "GTPE2_CHANNEL_RXADAPTSELTEST7", - "DRPDI9": "GTPE2_CHANNEL_DRPDI9", - "RXSYSCLKSEL0": "GTPE2_CHANNEL_RXSYSCLKSEL0", - "RXADAPTSELTEST12": "GTPE2_CHANNEL_RXADAPTSELTEST12", - "TXSYNCALLIN": "GTPE2_CHANNEL_TXSYNCALLIN", - "RXBUFSTATUS0": "GTPE2_CHANNEL_RXBUFSTATUS0", - "TXPHOVRDEN": "GTPE2_CHANNEL_TXPHOVRDEN", - "RXPCOMMAALIGNEN": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "RXELECIDLEMODE0": "GTPE2_CHANNEL_RXELECIDLEMODE0", - "TXSYNCIN": "GTPE2_CHANNEL_TXSYNCIN", - "DRPCLK": "GTPE2_CHANNEL_DRPCLK", - "TXMAINCURSOR0": "GTPE2_CHANNEL_TXMAINCURSOR0", - "TXMARGIN1": "GTPE2_CHANNEL_TXMARGIN1", - "PCSRSVDIN0": "GTPE2_CHANNEL_PCSRSVDIN0", - "RXDATA5": "GTPE2_CHANNEL_RXDATA5", - "PMARSVDIN2": "GTPE2_CHANNEL_PMARSVDIN2", - "RXDATA0": "GTPE2_CHANNEL_RXDATA0", - "RXPHMONITOR4": "GTPE2_CHANNEL_RXPHMONITOR4", - "PMASCANOUT4": "GTPE2_CHANNEL_PMASCANOUT4", - "SCANOUT5": "GTPE2_CHANNEL_SCANOUT5", - "TSTIN0": "GTPE2_CHANNEL_TSTIN0", - "RXHEADERVALID": "GTPE2_CHANNEL_RXHEADERVALID", - "SCANOUT2": "GTPE2_CHANNEL_SCANOUT2", - "RXPHALIGN": "GTPE2_CHANNEL_RXPHALIGN", - "RXCDRLOCK": "GTPE2_CHANNEL_RXCDRLOCK", - "RXUSRCLK2": "GTPE2_CHANNEL_RXUSRCLK2", - "RXNOTINTABLE3": "GTPE2_CHANNEL_RXNOTINTABLE3", - "GTRSVD3": "GTPE2_CHANNEL_GTRSVD3", - "TXSEQUENCE0": "GTPE2_CHANNEL_TXSEQUENCE0", - "TXPIPPMSTEPSIZE3": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IPAD", - "y_coord": 6, - "type": "IPAD", - "site_pins": { - "O": "GTPE2_CHANNEL_RXN_PAD" - }, - "x_coord": 1, - "name": "X1Y6" - }, - { - "prefix": "IPAD", - "y_coord": 7, - "type": "IPAD", - "site_pins": { - "O": "GTPE2_CHANNEL_RXP_PAD" - }, - "x_coord": 1, - "name": "X1Y7" - }, - { - "prefix": "OPAD", - "y_coord": 0, - "type": "OPAD", - "site_pins": { - "I": "GTPE2_CHANNEL_TXN_PAD" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "OPAD", - "y_coord": 1, - "type": "OPAD", - "site_pins": { - "I": "GTPE2_CHANNEL_TXP_PAD" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "GTP_CHANNEL_0.GTPE2_IMUX2_4->GTPE2_CHANNEL_TXPOSTCURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX27_1->GTPE2_CHANNEL_TXSEQUENCE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CLK0_9->GTPE2_CHANNEL_DRPCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX25_9->GTPE2_CHANNEL_PCSRSVDIN6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX45_7->GTPE2_CHANNEL_TXPISOPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPISOPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_10->GTPE2_CHANNEL_TSTIN9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_GTTXOUTCLK_0->GTPE2_CHANNEL_TXOUTCLK_0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLK_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_GTTXOUTCLK_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX6_0->GTPE2_CHANNEL_RXUSERRDY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSERRDY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX9_7->GTPE2_CHANNEL_PCSRSVDIN12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX28_6->GTPE2_CHANNEL_RXDLYEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT14->GTPE2_LOGIC_OUTS_B10_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTDONE->GTPE2_LOGIC_OUTS_B3_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX28_10->GTPE2_CHANNEL_RXOSINTID01": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID01", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX44_0->GTPE2_CHANNEL_TXPHOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_0->GTPE2_CHANNEL_RXOSINTPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX25_10->GTPE2_CHANNEL_PCSRSVDIN7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX24_9->GTPE2_CHANNEL_TSTIN18": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN18", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL1_5->GTPE2_CHANNEL_CFGRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CFGRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHANBONDSEQ->GTPE2_LOGIC_OUTS_B8_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANBONDSEQ", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXP_PAD->GTPE2_CHANNEL_RXP": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXP", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXP_PAD", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX19_3->GTPE2_CHANNEL_TXDATA17": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA17", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX35_10->GTPE2_CHANNEL_RXOSINTCFG2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX37_3->GTPE2_CHANNEL_TXPHDLYPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR1->GTPE2_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISK0->GTPE2_LOGIC_OUTS_B12_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA25->GTPE2_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA25", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFSTATUS0->GTPE2_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT4->GTPE2_LOGIC_OUTS_B9_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX22_8->GTPE2_CHANNEL_RXPRBSSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT2->GTPE2_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTROBESTARTED->GTPE2_LOGIC_OUTS_B0_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATAVALID0->GTPE2_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATAVALID0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_0->GTPE2_CHANNEL_TXPIPPMEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX36_10->GTPE2_CHANNEL_DRPDI13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT10->GTPE2_LOGIC_OUTS_B21_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX32_5->GTPE2_CHANNEL_DRPDI11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATAVALID1->GTPE2_LOGIC_OUTS_B5_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATAVALID1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX25_8->GTPE2_CHANNEL_PCSRSVDIN5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX35_4->GTPE2_CHANNEL_TXMARGIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA20->GTPE2_LOGIC_OUTS_B3_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA20", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA21->GTPE2_LOGIC_OUTS_B7_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA21", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISK1->GTPE2_LOGIC_OUTS_B12_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX22_7->GTPE2_CHANNEL_TXDATA2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT8->GTPE2_LOGIC_OUTS_B21_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX36_2->GTPE2_CHANNEL_RXSYNCALLIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCALLIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX16_0->GTPE2_CHANNEL_TXSEQUENCE5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBYTEREALIGN->GTPE2_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBYTEREALIGN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBYTEISALIGNED->GTPE2_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBYTEISALIGNED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX4_7->GTPE2_CHANNEL_RXADAPTSELTEST2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX6_1->GTPE2_CHANNEL_RXGEARBOXSLIP": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXGEARBOXSLIP", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_5->GTPE2_CHANNEL_TSTIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX6_9->GTPE2_CHANNEL_DRPDI6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMMADET->GTPE2_LOGIC_OUTS_B19_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMMADET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX5_7->GTPE2_CHANNEL_RXADAPTSELTEST3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO12->GTPE2_LOGIC_OUTS_B7_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX2_7->GTPE2_CHANNEL_RXRATEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO1->GTPE2_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFSTATUS1->GTPE2_LOGIC_OUTS_B19_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX4_0->GTPE2_CHANNEL_RXCHBONDLEVEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX0_8->GTPE2_CHANNEL_RXADAPTSELTEST10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX41_10->GTPE2_CHANNEL_TXDATA25": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA25", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX47_9->GTPE2_CHANNEL_LOOPBACK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXELECIDLE->GTPE2_LOGIC_OUTS_B19_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXELECIDLE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXNOTINTABLE3->GTPE2_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX22_6->GTPE2_CHANNEL_TXPIPPMSTEPSIZE4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX23_9->GTPE2_CHANNEL_RXCHBONDI3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX21_4->GTPE2_CHANNEL_TXDATA15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_4->GTPE2_CHANNEL_TXCHARDISPVAL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO5->GTPE2_LOGIC_OUTS_B12_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX15_5->GTPE2_CHANNEL_TX8B10BBYPASS1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX23_7->GTPE2_CHANNEL_TXDATA3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXN->GTPE2_CHANNEL_TXN_PAD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXN_PAD", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX24_10->GTPE2_CHANNEL_TSTIN19": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN19", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX10_7->GTPE2_CHANNEL_TXBUFDIFFCTRL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_3->GTPE2_CHANNEL_GTRSVD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDO2->GTPE2_LOGIC_OUTS_B16_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX5_2->GTPE2_CHANNEL_PMARSVDIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX13_4->GTPE2_CHANNEL_TSTIN10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX43_10->GTPE2_CHANNEL_RXLPMHFHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMHFHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDO1->GTPE2_LOGIC_OUTS_B16_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX38_8->GTPE2_CHANNEL_RXPRBSSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_7->GTPE2_CHANNEL_TSTIN6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX44_1->GTPE2_CHANNEL_DMONFIFORESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DMONFIFORESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX7_1->GTPE2_CHANNEL_TXSYNCIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXHEADER0->GTPE2_LOGIC_OUTS_B19_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_9->GTPE2_CHANNEL_DRPDI7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX31_7->GTPE2_CHANNEL_TXCHARISK0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA18->GTPE2_LOGIC_OUTS_B4_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA18", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT15->GTPE2_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT0->GTPE2_LOGIC_OUTS_B9_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX13_10->GTPE2_CHANNEL_RXPRBSCNTRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSCNTRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX26_7->GTPE2_CHANNEL_GTRSVD12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTROBEDONE->GTPE2_LOGIC_OUTS_B0_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA19->GTPE2_LOGIC_OUTS_B0_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA19", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX35_6->GTPE2_CHANNEL_TXPD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT5->GTPE2_LOGIC_OUTS_B13_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL0_8->GTPE2_CHANNEL_GTRXRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRXRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX28_8->GTPE2_CHANNEL_RXPD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA26->GTPE2_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA26", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_8->GTPE2_CHANNEL_TSTIN7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX14_10->GTPE2_CHANNEL_RXPHOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHANREALIGN->GTPE2_LOGIC_OUTS_B23_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANREALIGN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKPCS->GTPE2_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXOUTCLKPCS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA30->GTPE2_LOGIC_OUTS_B1_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA30", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFSTATUS0->GTPE2_LOGIC_OUTS_B23_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_6->GTPE2_CHANNEL_TXCHARDISPVAL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA31->GTPE2_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA31", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX46_0->GTPE2_CHANNEL_TXPCSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPCSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL0_6->GTPE2_CHANNEL_RXDLYSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYSRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX38_5->GTPE2_CHANNEL_TXSWING": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSWING", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX19_9->GTPE2_CHANNEL_RXCHBONDI1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX5_0->GTPE2_CHANNEL_RXCHBONDLEVEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_8->GTPE2_CHANNEL_TXPRBSSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXP->GTPE2_CHANNEL_TXP_PAD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXP_PAD", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXP", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISCOMMA2->GTPE2_LOGIC_OUTS_B15_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX31_3->GTPE2_CHANNEL_TXCHARISK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFSTATUS1->GTPE2_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR4->GTPE2_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT9->GTPE2_LOGIC_OUTS_B21_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX37_8->GTPE2_CHANNEL_PMARSVDIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX17_8->GTPE2_CHANNEL_RXADAPTSELTEST11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX43_9->GTPE2_CHANNEL_LOOPBACK0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTARTOFSEQ0->GTPE2_LOGIC_OUTS_B18_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO14->GTPE2_LOGIC_OUTS_B12_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_3->GTPE2_CHANNEL_TXPIPPMSEL": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSEL", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCDONE->GTPE2_LOGIC_OUTS_B22_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXSYNCDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR3->GTPE2_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL1_7->GTPE2_CHANNEL_RXPMARESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPMARESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXNOTINTABLE1->GTPE2_LOGIC_OUTS_B14_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX35_8->GTPE2_CHANNEL_TXPIPPMSTEPSIZE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX47_6->GTPE2_CHANNEL_TXRATE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXPMARESETDONE->GTPE2_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPMARESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX17_1->GTPE2_CHANNEL_TXDATA29": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA29", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR3->GTPE2_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_0->GTPE2_CHANNEL_TXSEQUENCE6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX10_3->GTPE2_CHANNEL_TXPIPPMOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX38_10->GTPE2_CHANNEL_RXOSINTCFG0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL1_3->GTPE2_CHANNEL_TXPMARESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPMARESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B15_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHINITDONE->GTPE2_LOGIC_OUTS_B1_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPHINITDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX26_8->GTPE2_CHANNEL_GTRSVD13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA11->GTPE2_LOGIC_OUTS_B0_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX0_3->GTPE2_CHANNEL_TXMAINCURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL0_5->GTPE2_CHANNEL_GTTXRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTTXRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX39_0->GTPE2_CHANNEL_TXHEADER2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX6_7->GTPE2_CHANNEL_RXADAPTSELTEST5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_10->GTPE2_CHANNEL_GTRSVD7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX31_0->GTPE2_CHANNEL_TXUSERRDY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSERRDY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX25_7->GTPE2_CHANNEL_PCSRSVDIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_6->GTPE2_CHANNEL_TXPRECURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHANISALIGNED->GTPE2_LOGIC_OUTS_B18_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANISALIGNED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX13_0->GTPE2_CHANNEL_TXSYNCMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_5->GTPE2_CHANNEL_TXDIFFCTRL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX20_6->GTPE2_CHANNEL_TXDATA6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PHYSTATUS->GTPE2_LOGIC_OUTS_B10_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PHYSTATUS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT11->GTPE2_LOGIC_OUTS_B5_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX7_7->GTPE2_CHANNEL_TXPRECURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX25_4->GTPE2_CHANNEL_PCSRSVDIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_9->GTPE2_CHANNEL_GTRSVD6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX16_10->GTPE2_CHANNEL_DRPDI15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA16->GTPE2_LOGIC_OUTS_B6_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA16", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX7_9->GTPE2_CHANNEL_DRPDI4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX13_7->GTPE2_CHANNEL_TXBUFDIFFCTRL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_10->GTPE2_CHANNEL_RXLPMLFOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX6_10->GTPE2_CHANNEL_RXOSINTCFG1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX13_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX32_7->GTPE2_CHANNEL_TXPRECURSORINV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSORINV", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX1_10->GTPE2_CHANNEL_RXELECIDLEMODE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX11_7->GTPE2_CHANNEL_RXADAPTSELTEST9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B7_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PMARSVDOUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDISPERR2->GTPE2_LOGIC_OUTS_B22_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX24_8->GTPE2_CHANNEL_TSTIN17": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN17", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX29_2->GTPE2_CHANNEL_TXCHARDISPMODE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX32_9->GTPE2_CHANNEL_RXOSINTSTROBE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTSTROBE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX20_4->GTPE2_CHANNEL_TXDATA14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXHEADER1->GTPE2_LOGIC_OUTS_B23_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX10_10->GTPE2_CHANNEL_RXOSINTID02": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID02", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX15_10->GTPE2_CHANNEL_RXOSINTID00": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID00", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PLLREFCLK0->GTPE2_CHANNEL_PLL0REFCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL0REFCLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLREFCLK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL0_9->GTPE2_CHANNEL_RXLPMRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA9->GTPE2_LOGIC_OUTS_B2_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX5_5->GTPE2_CHANNEL_RXLPMLFHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMLFHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX38_2->GTPE2_CHANNEL_DRPADDR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDISPERR1->GTPE2_LOGIC_OUTS_B22_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO6->GTPE2_LOGIC_OUTS_B22_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX22_3->GTPE2_CHANNEL_TXDATA18": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA18", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDLYSRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX15_9->GTPE2_CHANNEL_RXOSINTEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX19_7->GTPE2_CHANNEL_TXDATA1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX20_2->GTPE2_CHANNEL_TXDATA22": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA22", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO13->GTPE2_LOGIC_OUTS_B15_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA1->GTPE2_LOGIC_OUTS_B2_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX11_6->GTPE2_CHANNEL_RXRATE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT6->GTPE2_LOGIC_OUTS_B9_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA28->GTPE2_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA28", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX6_8->GTPE2_CHANNEL_TXPRBSSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX1_7->GTPE2_CHANNEL_RXADAPTSELTEST1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX26_10->GTPE2_CHANNEL_GTRSVD15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX27_5->GTPE2_CHANNEL_TXPHINIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHINIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX25_6->GTPE2_CHANNEL_PCSRSVDIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX33_2->GTPE2_CHANNEL_TXPHALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX33_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA5->GTPE2_LOGIC_OUTS_B7_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX46_6->GTPE2_CHANNEL_TXRATE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX14_0->GTPE2_CHANNEL_TXPDELECIDLEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDISPERR3->GTPE2_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX28_5->GTPE2_CHANNEL_TXSYSCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX12_3->GTPE2_CHANNEL_TXCHARDISPMODE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX23_3->GTPE2_CHANNEL_TXDATA19": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA19", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPRDY->GTPE2_LOGIC_OUTS_B14_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPRDY", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX43_6->GTPE2_CHANNEL_TXRATE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CLK0_7->GTPE2_CHANNEL_RXUSRCLK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSRCLK2", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX30_7->GTPE2_CHANNEL_RXPD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_1->GTPE2_CHANNEL_TXCOMWAKE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMWAKE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX45_8->GTPE2_CHANNEL_EYESCANRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX45_6->GTPE2_CHANNEL_DRPDI0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA0->GTPE2_LOGIC_OUTS_B6_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCOUT->GTPE2_LOGIC_OUTS_B14_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXSYNCOUT", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX44_10->GTPE2_CHANNEL_TXDATA26": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA26", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA13->GTPE2_LOGIC_OUTS_B7_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX9_9->GTPE2_CHANNEL_PCSRSVDIN14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISCOMMA3->GTPE2_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX35_5->GTPE2_CHANNEL_TXDEEMPH": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDEEMPH", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA29->GTPE2_LOGIC_OUTS_B7_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA29", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT13->GTPE2_LOGIC_OUTS_B1_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMWAKEDET->GTPE2_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMWAKEDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO11->GTPE2_LOGIC_OUTS_B1_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX15_6->GTPE2_CHANNEL_RXRATE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX30_8->GTPE2_CHANNEL_RXCDRHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX9_8->GTPE2_CHANNEL_PCSRSVDIN13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRLOCK->GTPE2_LOGIC_OUTS_B17_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCDRLOCK", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX26_3->GTPE2_CHANNEL_GTRSVD8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX35_3->GTPE2_CHANNEL_DRPADDR6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_1->GTPE2_CHANNEL_RXPCOMMAALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA7->GTPE2_LOGIC_OUTS_B5_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA7", - "is_pseudo": "0" - }, "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA23->GTPE2_LOGIC_OUTS_B5_5": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_5", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_RXDATA23", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX14_5->GTPE2_CHANNEL_TXDLYEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYEN", "is_directional": "1", - "src_wire": "GTPE2_IMUX14_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISK2->GTPE2_LOGIC_OUTS_B12_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCLKCORCNT1->GTPE2_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PLLREFCLK1->GTPE2_CHANNEL_PLL1REFCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL1REFCLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLREFCLK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX15_3->GTPE2_CHANNEL_TX8B10BBYPASS2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX24_3->GTPE2_CHANNEL_TSTIN12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX22_9->GTPE2_CHANNEL_RXCHBONDI2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPHALIGNDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT14->GTPE2_LOGIC_OUTS_B5_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO3->GTPE2_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_GTRXOUTCLK_0->GTPE2_CHANNEL_RXOUTCLK_0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLK_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_GTRXOUTCLK_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX5_9->GTPE2_CHANNEL_RXOSINTTESTOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX30_9->GTPE2_CHANNEL_RXCHBONDMASTER": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDMASTER", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX21_1->GTPE2_CHANNEL_TXDATA31": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA31", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_7->GTPE2_CHANNEL_RXPHDLYPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHDLYPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX11_5->GTPE2_CHANNEL_TXDLYHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX25_3->GTPE2_CHANNEL_PCSRSVDIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX46_4->GTPE2_CHANNEL_TXCHARDISPVAL3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCOUT->GTPE2_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSYNCOUT", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_8->GTPE2_CHANNEL_GTRSVD5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX45_0->GTPE2_CHANNEL_RXDFEXYDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDFEXYDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX2_5->GTPE2_CHANNEL_TXDIFFCTRL3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX5_3->GTPE2_CHANNEL_TXMAINCURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_2->GTPE2_CHANNEL_PMARSVDIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX2_1->GTPE2_CHANNEL_TXCOMINIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMINIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX4_8->GTPE2_CHANNEL_TXOUTCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX29_8->GTPE2_CHANNEL_RXOSHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX43_5->GTPE2_CHANNEL_TXDLYUPDOWN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYUPDOWN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0->GTPE2_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX1_8->GTPE2_CHANNEL_TXOUTCLKSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX18_5->GTPE2_CHANNEL_TXDATA8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXCOMFINISH->GTPE2_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXCOMFINISH", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX29_6->GTPE2_CHANNEL_TXCHARDISPMODE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_4->GTPE2_CHANNEL_GTRSVD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX17_10->GTPE2_CHANNEL_DRPDI14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX38_3->GTPE2_CHANNEL_DRPADDR5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX28_3->GTPE2_CHANNEL_DRPWE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPWE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL1_8->GTPE2_CHANNEL_RXCDRRESETRSV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRRESETRSV", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1->GTPE2_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTATUS1->GTPE2_LOGIC_OUTS_B17_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX41_5->GTPE2_CHANNEL_RESETOVRD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RESETOVRD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHALIGNDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX5_10->GTPE2_CHANNEL_RXOUTCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX10_9->GTPE2_CHANNEL_PMARSVDIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX0_2->GTPE2_CHANNEL_TX8B10BEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX34_4->GTPE2_CHANNEL_SETERRSTATUS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_SETERRSTATUS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX0_9->GTPE2_CHANNEL_RXOSINTOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX44_7->GTPE2_CHANNEL_RXADAPTSELTEST7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX41_1->GTPE2_CHANNEL_RXMCOMMAALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR0->GTPE2_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CLK1_7->GTPE2_CHANNEL_CLKRSVD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CLKRSVD0", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_4->GTPE2_CHANNEL_TXPOSTCURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO9->GTPE2_LOGIC_OUTS_B4_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL1_9->GTPE2_CHANNEL_RXCDRRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX1_4->GTPE2_CHANNEL_TXMAINCURSOR6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX39_2->GTPE2_CHANNEL_DRPADDR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX9_6->GTPE2_CHANNEL_PCSRSVDIN11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX38_9->GTPE2_CHANNEL_DRPDI5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT5->GTPE2_LOGIC_OUTS_B9_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX37_10->GTPE2_CHANNEL_DRPDI12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT1->GTPE2_LOGIC_OUTS_B9_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT4->GTPE2_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXRESETDONE->GTPE2_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_3->GTPE2_CHANNEL_TSTIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX2_6->GTPE2_CHANNEL_TXPRECURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCLKCORCNT0->GTPE2_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX14_6->GTPE2_CHANNEL_RXRATE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX18_9->GTPE2_CHANNEL_RXCHBONDI0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX20_1->GTPE2_CHANNEL_TXDATA30": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA30", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX41_6->GTPE2_CHANNEL_RXPHALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX9_4->GTPE2_CHANNEL_PCSRSVDIN9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX24_6->GTPE2_CHANNEL_TSTIN15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT11->GTPE2_LOGIC_OUTS_B21_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTARTED->GTPE2_LOGIC_OUTS_B6_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTARTED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT12->GTPE2_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX1_3->GTPE2_CHANNEL_TXMAINCURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX36_8->GTPE2_CHANNEL_RXADAPTSELTEST12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXDLYSRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX12_5->GTPE2_CHANNEL_TXDLYOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CLK0_5->GTPE2_CHANNEL_TXUSRCLK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSRCLK2", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO2->GTPE2_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT13->GTPE2_LOGIC_OUTS_B9_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CLK1_2->GTPE2_CHANNEL_TXPHDLYTSTCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPMARESETDONE->GTPE2_LOGIC_OUTS_B12_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPMARESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CLK0_4->GTPE2_CHANNEL_TXUSRCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSRCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT2->GTPE2_LOGIC_OUTS_B9_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_9->GTPE2_CHANNEL_TSTIN8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCDONE->GTPE2_LOGIC_OUTS_B14_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSYNCDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX46_2->GTPE2_CHANNEL_RXOSCALRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSCALRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_5->GTPE2_CHANNEL_GTRSVD2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA15->GTPE2_LOGIC_OUTS_B5_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX36_7->GTPE2_CHANNEL_RXOSINTNTRLEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTNTRLEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX34_2->GTPE2_CHANNEL_DRPADDR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CLK1_4->GTPE2_CHANNEL_SIGVALIDCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_SIGVALIDCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_5" }, "GTP_CHANNEL_0.GTPE2_IMUX27_8->GTPE2_CHANNEL_TXCOMSAS": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMSAS", - "is_directional": "1", "src_wire": "GTPE2_IMUX27_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX39_4->GTPE2_CHANNEL_TXMARGIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN0", "is_directional": "1", - "src_wire": "GTPE2_IMUX39_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMSAS" }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2->GTPE2_LOGIC_OUTS_B9_0": { + "GTP_CHANNEL_0.GTPE2_IMUX22_8->GTPE2_CHANNEL_RXPRBSSEL0": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_0", + "src_wire": "GTPE2_IMUX22_8", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_4->GTPE2_CHANNEL_TSTIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX14_9->GTPE2_CHANNEL_RXPHALIGN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHALIGN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX25_5->GTPE2_CHANNEL_PCSRSVDIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX41_7->GTPE2_CHANNEL_RXADAPTSELTEST6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATEDONE->GTPE2_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXRATEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA8->GTPE2_LOGIC_OUTS_B6_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_1->GTPE2_CHANNEL_TXSEQUENCE4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX17_9->GTPE2_CHANNEL_RXCHBONDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISCOMMA0->GTPE2_LOGIC_OUTS_B15_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_8->GTPE2_CHANNEL_RXDDIEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDDIEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CLK1_5->GTPE2_CHANNEL_DMONITORCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DMONITORCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX26_5->GTPE2_CHANNEL_GTRSVD10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX26_9->GTPE2_CHANNEL_GTRSVD14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX34_6->GTPE2_CHANNEL_DRPDI8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT3->GTPE2_LOGIC_OUTS_B9_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX30_6->GTPE2_CHANNEL_TXPOSTCURSORINV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSORINV", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX45_1->GTPE2_CHANNEL_RX8B10BEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RX8B10BEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL0_7->GTPE2_CHANNEL_RXCDRFREQRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRFREQRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO7->GTPE2_LOGIC_OUTS_B4_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMINITDET->GTPE2_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMINITDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX31_5->GTPE2_CHANNEL_TXCHARISK1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX29_4->GTPE2_CHANNEL_TXCHARDISPMODE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX30_3->GTPE2_CHANNEL_TXPOLARITY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOLARITY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR4->GTPE2_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX27_0->GTPE2_CHANNEL_TXSEQUENCE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX5_8->GTPE2_CHANNEL_TXOUTCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX7_5->GTPE2_CHANNEL_TXDIFFCTRL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX23_5->GTPE2_CHANNEL_TXDATA11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX39_1->GTPE2_CHANNEL_TXHEADER0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX21_2->GTPE2_CHANNEL_TXDATA23": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA23", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX45_5->GTPE2_CHANNEL_DRPDI9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PLLCLK1->GTPE2_CHANNEL_PLL1CLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL1CLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLCLK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX25_2->GTPE2_CHANNEL_TXPHALIGN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHALIGN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX14_1->GTPE2_CHANNEL_TXPRBSFORCEERR": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSFORCEERR", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANDATAERROR->GTPE2_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_EYESCANDATAERROR", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX0_10->GTPE2_CHANNEL_RXELECIDLEMODE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX9_5->GTPE2_CHANNEL_PCSRSVDIN10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX34_3->GTPE2_CHANNEL_DRPADDR7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA6->GTPE2_LOGIC_OUTS_B1_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDISPERR0->GTPE2_LOGIC_OUTS_B22_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX7_0->GTPE2_CHANNEL_RXSYNCIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX17_4->GTPE2_CHANNEL_TXDATA13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX21_6->GTPE2_CHANNEL_TXDATA7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX23_8->GTPE2_CHANNEL_RXPRBSSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX17_6->GTPE2_CHANNEL_TXDATA5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX38_6->GTPE2_CHANNEL_TXPD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL0" }, "GTP_CHANNEL_0.GTPE2_IMUX9_3->GTPE2_CHANNEL_PCSRSVDIN8": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN8", - "is_directional": "1", "src_wire": "GTPE2_IMUX9_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX32_6->GTPE2_CHANNEL_DRPDI3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT9->GTPE2_LOGIC_OUTS_B13_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX31_4->GTPE2_CHANNEL_TX8B10BBYPASS3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX34_7->GTPE2_CHANNEL_RXADAPTSELTEST4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX27_7->GTPE2_CHANNEL_RXPOLARITY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPOLARITY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTATUS2->GTPE2_LOGIC_OUTS_B23_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX44_3->GTPE2_CHANNEL_DRPEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX35_1->GTPE2_CHANNEL_TXSEQUENCE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT7->GTPE2_LOGIC_OUTS_B13_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX6_5->GTPE2_CHANNEL_TXDIFFCTRL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_1->GTPE2_CHANNEL_RXSLIDE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSLIDE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX18_7->GTPE2_CHANNEL_TXDATA0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX33_5->GTPE2_CHANNEL_DRPDI10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX33_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX1_9->GTPE2_CHANNEL_RXOSINTHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX46_1->GTPE2_CHANNEL_RXPCSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPCSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX37_7->GTPE2_CHANNEL_PMARSVDIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_10->GTPE2_CHANNEL_TXDATA24": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA24", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATEDONE->GTPE2_LOGIC_OUTS_B23_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXRATEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_6->GTPE2_CHANNEL_TSTIN5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX11_3->GTPE2_CHANNEL_TXRATEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX11_10->GTPE2_CHANNEL_RXOSINTID03": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID03", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX29_7->GTPE2_CHANNEL_RXADAPTSELTEST8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX46_10->GTPE2_CHANNEL_RXOSINTCFG3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA10->GTPE2_LOGIC_OUTS_B4_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX13_6->GTPE2_CHANNEL_DRPDI2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX41_0->GTPE2_CHANNEL_RXDLYOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX13_8->GTPE2_CHANNEL_RXOSOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA3->GTPE2_LOGIC_OUTS_B0_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX39_6->GTPE2_CHANNEL_TXELECIDLE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXELECIDLE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX15_7->GTPE2_CHANNEL_TX8B10BBYPASS0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX46_3->GTPE2_CHANNEL_TXPIPPMPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT0->GTPE2_LOGIC_OUTS_B5_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX41_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX35_2->GTPE2_CHANNEL_DRPADDR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX3_3->GTPE2_CHANNEL_TXSTARTSEQ": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSTARTSEQ", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_2->GTPE2_CHANNEL_RXSYSCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDO3->GTPE2_LOGIC_OUTS_B16_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX21_8->GTPE2_CHANNEL_RXADAPTSELTEST13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX24_5->GTPE2_CHANNEL_TSTIN14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX26_4->GTPE2_CHANNEL_GTRSVD9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA24->GTPE2_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA24", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMSASDET->GTPE2_LOGIC_OUTS_B18_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMSASDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT8->GTPE2_LOGIC_OUTS_B13_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX45_3->GTPE2_CHANNEL_TXDLYSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFSTATUS2->GTPE2_LOGIC_OUTS_B17_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT6->GTPE2_LOGIC_OUTS_B13_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX7_4->GTPE2_CHANNEL_TXPOSTCURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PLLCLK0->GTPE2_CHANNEL_PLL0CLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL0CLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLCLK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_TXGEARBOXREADY->GTPE2_LOGIC_OUTS_B23_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXGEARBOXREADY", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA4->GTPE2_LOGIC_OUTS_B3_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX2_3->GTPE2_CHANNEL_DRPADDR8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA27->GTPE2_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA27", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKPCS->GTPE2_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOUTCLKPCS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX4_4->GTPE2_CHANNEL_TXMAINCURSOR5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX24_7->GTPE2_CHANNEL_TSTIN16": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN16", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO10->GTPE2_LOGIC_OUTS_B2_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXRESETDONE->GTPE2_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX31_1->GTPE2_CHANNEL_TXHEADER1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX31_8->GTPE2_CHANNEL_EYESCANTRIGGER": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANTRIGGER", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSERR->GTPE2_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPRBSERR", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX4_3->GTPE2_CHANNEL_TXMAINCURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX36_5->GTPE2_CHANNEL_TXPHDLYRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX2_10->GTPE2_CHANNEL_RXOUTCLKSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL1_6->GTPE2_CHANNEL_RXBUFRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXBUFRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXHEADERVALID->GTPE2_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADERVALID", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_7->GTPE2_CHANNEL_GTRSVD4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX44_9->GTPE2_CHANNEL_RXCOMMADETEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCOMMADETEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX7_6->GTPE2_CHANNEL_TXPRECURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR2->GTPE2_LOGIC_OUTS_B7_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX8_2->GTPE2_CHANNEL_TXCHARDISPVAL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT10->GTPE2_LOGIC_OUTS_B13_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX16_1->GTPE2_CHANNEL_TXDATA28": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA28", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXNOTINTABLE2->GTPE2_LOGIC_OUTS_B14_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT7->GTPE2_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXHEADER2->GTPE2_LOGIC_OUTS_B17_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTARTOFSEQ1->GTPE2_LOGIC_OUTS_B11_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX26_6->GTPE2_CHANNEL_GTRSVD11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX9_10->GTPE2_CHANNEL_PCSRSVDIN15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX32_2->GTPE2_CHANNEL_TXINHIBIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXINHIBIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX28_4->GTPE2_CHANNEL_TXSYSCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT1->GTPE2_LOGIC_OUTS_B0_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA22->GTPE2_LOGIC_OUTS_B1_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA22", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA14->GTPE2_LOGIC_OUTS_B1_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO8->GTPE2_LOGIC_OUTS_B12_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX10_6->GTPE2_CHANNEL_DRPDI1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_2->GTPE2_CHANNEL_TSTIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX7_3->GTPE2_CHANNEL_TXPOSTCURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT12->GTPE2_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX7_8->GTPE2_CHANNEL_TXPRBSSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT3->GTPE2_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX42_6->GTPE2_CHANNEL_GTRSVD3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX24_4->GTPE2_CHANNEL_TSTIN13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA12->GTPE2_LOGIC_OUTS_B3_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CLK1_8->GTPE2_CHANNEL_CLKRSVD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CLKRSVD1", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX47_4->GTPE2_CHANNEL_TXCHARISK3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISCOMMA1->GTPE2_LOGIC_OUTS_B15_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX45_2->GTPE2_CHANNEL_RXSYSCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX32_8->GTPE2_CHANNEL_RXDLYBYPASS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYBYPASS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX16_6->GTPE2_CHANNEL_TXDATA4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA17->GTPE2_LOGIC_OUTS_B2_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA17", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO4->GTPE2_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXNOTINTABLE0->GTPE2_LOGIC_OUTS_B14_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX44_5->GTPE2_CHANNEL_TXDLYBYPASS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYBYPASS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX1_0->GTPE2_CHANNEL_RXCHBONDLEVEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL0", "is_directional": "1", - "src_wire": "GTPE2_IMUX1_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN8" }, - "GTP_CHANNEL_0.GTPE2_IMUX12_7->GTPE2_CHANNEL_TXBUFDIFFCTRL0": { + "GTP_CHANNEL_0.GTPE2_IMUX7_9->GTPE2_CHANNEL_DRPDI4": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", + "src_wire": "GTPE2_IMUX7_9", "is_directional": "1", - "src_wire": "GTPE2_IMUX12_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI4" }, "GTP_CHANNEL_0.GTPE2_IMUX37_4->GTPE2_CHANNEL_TXDIFFPD": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFPD", - "is_directional": "1", "src_wire": "GTPE2_IMUX37_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX0_7->GTPE2_CHANNEL_RXADAPTSELTEST0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST0", "is_directional": "1", - "src_wire": "GTPE2_IMUX0_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFPD" }, - "GTP_CHANNEL_0.GTPE2_IMUX46_9->GTPE2_CHANNEL_LOOPBACK1": { + "GTP_CHANNEL_0.GTPE2_IMUX3_2->GTPE2_CHANNEL_PMARSVDIN4": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK1", + "src_wire": "GTPE2_IMUX3_2", "is_directional": "1", - "src_wire": "GTPE2_IMUX46_9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN4" }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA2->GTPE2_LOGIC_OUTS_B4_10": { + "GTP_CHANNEL_0.GTPE2_IMUX2_4->GTPE2_CHANNEL_TXPOSTCURSOR3": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_10", + "src_wire": "GTPE2_IMUX2_4", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX35_0->GTPE2_CHANNEL_TXSEQUENCE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX27_10->GTPE2_CHANNEL_RXLPMHFOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX24_2->GTPE2_CHANNEL_TSTIN11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX22_5->GTPE2_CHANNEL_TXDATA10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX6_4->GTPE2_CHANNEL_TXPOSTCURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX40_0->GTPE2_CHANNEL_RXSYNCMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX2_0->GTPE2_CHANNEL_EYESCANMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXN_PAD->GTPE2_CHANNEL_RXN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXN", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXN_PAD", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX45_4->GTPE2_CHANNEL_TSTIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDO0->GTPE2_LOGIC_OUTS_B16_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B15_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PMARSVDOUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTATUS0->GTPE2_LOGIC_OUTS_B21_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX29_10->GTPE2_CHANNEL_TXDATA27": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA27", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX6_6->GTPE2_CHANNEL_TXPRECURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR3" }, "GTP_CHANNEL_0.GTPE2_CLK0_6->GTPE2_CHANNEL_RXUSRCLK": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSRCLK", - "is_directional": "1", "src_wire": "GTPE2_CLK0_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_IMUX17_2->GTPE2_CHANNEL_TXDATA21": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA21", "is_directional": "1", - "src_wire": "GTPE2_IMUX17_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSRCLK" }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISK3->GTPE2_LOGIC_OUTS_B12_4": { + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT11->GTPE2_LOGIC_OUTS_B21_4": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_4", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT11", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_4" }, - "GTP_CHANNEL_0.GTPE2_IMUX16_4->GTPE2_CHANNEL_TXDATA12": { + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO12->GTPE2_LOGIC_OUTS_B7_8": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA12", + "src_wire": "GTPE2_CHANNEL_DRPDO12", "is_directional": "1", - "src_wire": "GTPE2_IMUX16_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_8" }, - "GTP_CHANNEL_0.GTPE2_IMUX18_3->GTPE2_CHANNEL_TXDATA16": { + "GTP_CHANNEL_0.GTPE2_IMUX8_8->GTPE2_CHANNEL_RXDDIEN": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA16", + "src_wire": "GTPE2_IMUX8_8", "is_directional": "1", - "src_wire": "GTPE2_IMUX18_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDDIEN" }, - "GTP_CHANNEL_0.GTPE2_IMUX38_4->GTPE2_CHANNEL_TXMARGIN1": { + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMINITDET->GTPE2_LOGIC_OUTS_B20_1": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN1", + "src_wire": "GTPE2_CHANNEL_RXCOMINITDET", "is_directional": "1", - "src_wire": "GTPE2_IMUX38_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_1" }, - "GTP_CHANNEL_0.GTPE2_IMUX7_2->GTPE2_CHANNEL_RXLPMOSINTNTRLEN": { + "GTP_CHANNEL_0.GTPE2_IMUX40_8->GTPE2_CHANNEL_TSTIN7": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", + "src_wire": "GTPE2_IMUX40_8", "is_directional": "1", - "src_wire": "GTPE2_IMUX7_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN7" }, - "GTP_CHANNEL_0.GTPE2_CTRL1_10->GTPE2_CHANNEL_RXOOBRESET": { + "GTP_CHANNEL_0.GTPE2_IMUX26_9->GTPE2_CHANNEL_GTRSVD14": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOOBRESET", + "src_wire": "GTPE2_IMUX26_9", "is_directional": "1", - "src_wire": "GTPE2_CTRL1_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD14" }, - "GTP_CHANNEL_0.GTPE2_IMUX14_8->GTPE2_CHANNEL_RXCDROVRDEN": { + "GTP_CHANNEL_0.GTPE2_IMUX8_2->GTPE2_CHANNEL_TXCHARDISPVAL2": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDROVRDEN", + "src_wire": "GTPE2_IMUX8_2", "is_directional": "1", - "src_wire": "GTPE2_IMUX14_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL2" }, - "GTP_CHANNEL_0.GTPE2_IMUX39_5->GTPE2_CHANNEL_TXDETECTRX": { + "GTP_CHANNEL_0.GTPE2_IMUX20_1->GTPE2_CHANNEL_TXDATA30": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDETECTRX", + "src_wire": "GTPE2_IMUX20_1", "is_directional": "1", - "src_wire": "GTPE2_IMUX39_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA30" }, - "GTP_CHANNEL_0.GTPE2_IMUX5_4->GTPE2_CHANNEL_TXMAINCURSOR4": { + "GTP_CHANNEL_0.GTPE2_IMUX3_10->GTPE2_CHANNEL_RXLPMLFOVRDEN": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR4", + "src_wire": "GTPE2_IMUX3_10", "is_directional": "1", - "src_wire": "GTPE2_IMUX5_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMLFOVRDEN" }, - "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO0->GTPE2_LOGIC_OUTS_B12_3": { + "GTP_CHANNEL_0.GTPE2_IMUX3_9->GTPE2_CHANNEL_DRPDI7": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_3", + "src_wire": "GTPE2_IMUX3_9", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI7" }, - "GTP_CHANNEL_0.GTPE2_CTRL1_4->GTPE2_CHANNEL_RXPHDLYRESET": { + "GTP_CHANNEL_0.GTPE2_IMUX44_10->GTPE2_CHANNEL_TXDATA26": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHDLYRESET", + "src_wire": "GTPE2_IMUX44_10", "is_directional": "1", - "src_wire": "GTPE2_CTRL1_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA26" + }, + "GTP_CHANNEL_0.GTPE2_IMUX4_8->GTPE2_CHANNEL_TXOUTCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX2_1->GTPE2_CHANNEL_TXCOMINIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMINIT" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT9->GTPE2_LOGIC_OUTS_B21_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_6" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCLKCORCNT1->GTPE2_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX31_3->GTPE2_CHANNEL_TXCHARISK2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX9_5->GTPE2_CHANNEL_PCSRSVDIN10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN10" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT1->GTPE2_LOGIC_OUTS_B9_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX9_7->GTPE2_CHANNEL_PCSRSVDIN12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN12" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_GTRXOUTCLK_0->GTPE2_CHANNEL_RXOUTCLK_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_GTRXOUTCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLK_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX34_2->GTPE2_CHANNEL_DRPADDR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCDONE->GTPE2_LOGIC_OUTS_B22_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXSYNCDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX45_5->GTPE2_CHANNEL_DRPDI9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX14_5->GTPE2_CHANNEL_TXDLYEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA31->GTPE2_LOGIC_OUTS_B5_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA26->GTPE2_LOGIC_OUTS_B4_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX44_5->GTPE2_CHANNEL_TXDLYBYPASS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYBYPASS" + }, + "GTP_CHANNEL_0.GTPE2_IMUX14_6->GTPE2_CHANNEL_RXRATE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX24_5->GTPE2_CHANNEL_TSTIN14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN14" + }, + "GTP_CHANNEL_0.GTPE2_IMUX29_8->GTPE2_CHANNEL_RXOSHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSHOLD" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDISPERR0->GTPE2_LOGIC_OUTS_B22_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX9_4->GTPE2_CHANNEL_PCSRSVDIN9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX6_1->GTPE2_CHANNEL_RXGEARBOXSLIP": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXGEARBOXSLIP" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PHYSTATUS->GTPE2_LOGIC_OUTS_B10_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PHYSTATUS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX9_9->GTPE2_CHANNEL_PCSRSVDIN14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN14" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTATUS1->GTPE2_LOGIC_OUTS_B17_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX2_0->GTPE2_CHANNEL_EYESCANMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANMODE" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISK1->GTPE2_LOGIC_OUTS_B12_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX34_3->GTPE2_CHANNEL_DRPADDR7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX12_5->GTPE2_CHANNEL_TXDLYOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYOVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX24_6->GTPE2_CHANNEL_TSTIN15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN15" + }, + "GTP_CHANNEL_0.GTPE2_IMUX2_5->GTPE2_CHANNEL_TXDIFFCTRL3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX27_7->GTPE2_CHANNEL_RXPOLARITY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPOLARITY" + }, + "GTP_CHANNEL_0.GTPE2_IMUX31_4->GTPE2_CHANNEL_TX8B10BBYPASS3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX25_2->GTPE2_CHANNEL_TXPHALIGN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHALIGN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO10->GTPE2_LOGIC_OUTS_B2_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_9" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B7_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PMARSVDOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_6" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT7->GTPE2_LOGIC_OUTS_B9_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMSASDET->GTPE2_LOGIC_OUTS_B18_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMSASDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_7" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA4->GTPE2_LOGIC_OUTS_B3_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX21_8->GTPE2_CHANNEL_RXADAPTSELTEST13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST13" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT8->GTPE2_LOGIC_OUTS_B13_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX4_3->GTPE2_CHANNEL_TXMAINCURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX41_7->GTPE2_CHANNEL_RXADAPTSELTEST6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX38_5->GTPE2_CHANNEL_TXSWING": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSWING" + }, + "GTP_CHANNEL_0.GTPE2_IMUX38_8->GTPE2_CHANNEL_RXPRBSSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBYTEISALIGNED->GTPE2_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBYTEISALIGNED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_0" + }, + "GTP_CHANNEL_0.GTPE2_CTRL1_3->GTPE2_CHANNEL_TXPMARESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPMARESET" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT4->GTPE2_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_4" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISK2->GTPE2_LOGIC_OUTS_B12_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX15_5->GTPE2_CHANNEL_TX8B10BBYPASS1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISCOMMA3->GTPE2_LOGIC_OUTS_B15_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX43_5->GTPE2_CHANNEL_TXDLYUPDOWN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYUPDOWN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA6->GTPE2_LOGIC_OUTS_B1_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX31_5->GTPE2_CHANNEL_TXCHARISK1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK1" + }, + "GTP_CHANNEL_0.GTPE2_CTRL0_7->GTPE2_CHANNEL_RXCDRFREQRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRFREQRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_10->GTPE2_CHANNEL_GTRSVD7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD7" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXHEADERVALID->GTPE2_LOGIC_OUTS_B14_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADERVALID", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX38_9->GTPE2_CHANNEL_DRPDI5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI5" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXHEADER0->GTPE2_LOGIC_OUTS_B19_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX3_5->GTPE2_CHANNEL_TXDIFFCTRL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR4->GTPE2_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO8->GTPE2_LOGIC_OUTS_B12_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX17_10->GTPE2_CHANNEL_DRPDI14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI14" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDO0->GTPE2_LOGIC_OUTS_B16_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_3->GTPE2_CHANNEL_GTRSVD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX34_7->GTPE2_CHANNEL_RXADAPTSELTEST4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST4" + }, + "GTP_CHANNEL_0.GTPE2_CTRL0_8->GTPE2_CHANNEL_GTRXRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRXRESET" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B15_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX36_8->GTPE2_CHANNEL_RXADAPTSELTEST12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST12" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA18->GTPE2_LOGIC_OUTS_B4_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX7_5->GTPE2_CHANNEL_TXDIFFCTRL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX28_5->GTPE2_CHANNEL_TXSYSCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX8_1->GTPE2_CHANNEL_TXSEQUENCE4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE4" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT5->GTPE2_LOGIC_OUTS_B9_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX45_1->GTPE2_CHANNEL_RX8B10BEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RX8B10BEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_9->GTPE2_CHANNEL_GTRSVD6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX32_7->GTPE2_CHANNEL_TXPRECURSORINV": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSORINV" }, "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO15->GTPE2_LOGIC_OUTS_B4_7": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_7", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_DRPDO15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_0.GTPE2_CTRL0_10->GTPE2_CHANNEL_GTRESETSEL": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRESETSEL", "is_directional": "1", - "src_wire": "GTPE2_CTRL0_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_7" }, - "GTP_CHANNEL_0.GTPE2_IMUX30_10->GTPE2_CHANNEL_RXCHBONDSLAVE": { + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHANREALIGN->GTPE2_LOGIC_OUTS_B23_9": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDSLAVE", + "src_wire": "GTPE2_CHANNEL_RXCHANREALIGN", "is_directional": "1", - "src_wire": "GTPE2_IMUX30_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_9" }, - "GTP_CHANNEL_0.GTPE2_IMUX39_3->GTPE2_CHANNEL_DRPADDR4": { + "GTP_CHANNEL_0.GTPE2_IMUX8_10->GTPE2_CHANNEL_TXDATA24": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR4", + "src_wire": "GTPE2_IMUX8_10", "is_directional": "1", - "src_wire": "GTPE2_IMUX39_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA24" }, - "GTP_CHANNEL_0.GTPE2_IMUX16_2->GTPE2_CHANNEL_TXDATA20": { + "GTP_CHANNEL_0.GTPE2_IMUX0_8->GTPE2_CHANNEL_RXADAPTSELTEST10": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA20", + "src_wire": "GTPE2_IMUX0_8", "is_directional": "1", - "src_wire": "GTPE2_IMUX16_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX16_6->GTPE2_CHANNEL_TXDATA4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX17_2->GTPE2_CHANNEL_TXDATA21": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA21" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_6->GTPE2_CHANNEL_GTRSVD3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTARTED->GTPE2_LOGIC_OUTS_B6_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTARTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_7" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFSTATUS0->GTPE2_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTROBESTARTED->GTPE2_LOGIC_OUTS_B0_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX18_5->GTPE2_CHANNEL_TXDATA8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA8" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO4->GTPE2_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX37_7->GTPE2_CHANNEL_PMARSVDIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDISPERR1->GTPE2_LOGIC_OUTS_B22_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX18_3->GTPE2_CHANNEL_TXDATA16": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA16" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B15_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PMARSVDOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX45_6->GTPE2_CHANNEL_DRPDI0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX39_0->GTPE2_CHANNEL_TXHEADER2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA8->GTPE2_LOGIC_OUTS_B6_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX44_1->GTPE2_CHANNEL_DMONFIFORESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DMONFIFORESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX3_0->GTPE2_CHANNEL_RXOSINTPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTPD" + }, + "GTP_CHANNEL_0.GTPE2_CTRL1_7->GTPE2_CHANNEL_RXPMARESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPMARESET" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBYTEREALIGN->GTPE2_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBYTEREALIGN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX17_1->GTPE2_CHANNEL_TXDATA29": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA29" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT8->GTPE2_LOGIC_OUTS_B21_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX25_6->GTPE2_CHANNEL_PCSRSVDIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT3->GTPE2_LOGIC_OUTS_B13_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX12_7->GTPE2_CHANNEL_TXBUFDIFFCTRL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT10->GTPE2_LOGIC_OUTS_B13_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX37_3->GTPE2_CHANNEL_TXPHDLYPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYPD" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTARTOFSEQ1->GTPE2_LOGIC_OUTS_B11_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX25_10->GTPE2_CHANNEL_PCSRSVDIN7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_4->GTPE2_CHANNEL_GTRSVD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXOUTCLKPCS->GTPE2_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXOUTCLKPCS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX12_3->GTPE2_CHANNEL_TXCHARDISPMODE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCOUT->GTPE2_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSYNCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXELECIDLE->GTPE2_LOGIC_OUTS_B19_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_8" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT10->GTPE2_LOGIC_OUTS_B21_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_5" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA28->GTPE2_LOGIC_OUTS_B3_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX45_4->GTPE2_CHANNEL_TSTIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO7->GTPE2_LOGIC_OUTS_B4_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_5" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR3->GTPE2_LOGIC_OUTS_B6_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX45_0->GTPE2_CHANNEL_RXDFEXYDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDFEXYDEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX41_1->GTPE2_CHANNEL_RXMCOMMAALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXMCOMMAALIGNEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX26_5->GTPE2_CHANNEL_GTRSVD10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD10" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR0->GTPE2_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX20_6->GTPE2_CHANNEL_TXDATA6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX46_2->GTPE2_CHANNEL_RXOSCALRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSCALRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX5_3->GTPE2_CHANNEL_TXMAINCURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_1->GTPE2_CHANNEL_RXPCOMMAALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPCOMMAALIGNEN" }, "GTP_CHANNEL_0.GTPE2_IMUX4_10->GTPE2_CHANNEL_RXOUTCLKSEL0": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL0", - "is_directional": "1", "src_wire": "GTPE2_IMUX4_10", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX38_6->GTPE2_CHANNEL_TXPD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPD0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX32_9->GTPE2_CHANNEL_RXOSINTSTROBE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTSTROBE" + }, + "GTP_CHANNEL_0.GTPE2_IMUX39_5->GTPE2_CHANNEL_TXDETECTRX": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDETECTRX" + }, + "GTP_CHANNEL_0.GTPE2_IMUX35_8->GTPE2_CHANNEL_TXPIPPMSTEPSIZE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA24->GTPE2_LOGIC_OUTS_B6_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX35_10->GTPE2_CHANNEL_RXOSINTCFG2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXHEADER1->GTPE2_LOGIC_OUTS_B23_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX13_4->GTPE2_CHANNEL_TSTIN10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX44_9->GTPE2_CHANNEL_RXCOMMADETEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCOMMADETEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDLYSRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT7->GTPE2_LOGIC_OUTS_B13_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX32_5->GTPE2_CHANNEL_DRPDI11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI11" + }, + "GTP_CHANNEL_0.GTPE2_IMUX28_10->GTPE2_CHANNEL_RXOSINTID01": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID01" + }, + "GTP_CHANNEL_0.GTPE2_IMUX6_7->GTPE2_CHANNEL_RXADAPTSELTEST5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX6_9->GTPE2_CHANNEL_DRPDI6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX34_6->GTPE2_CHANNEL_DRPDI8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI8" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT11->GTPE2_LOGIC_OUTS_B5_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_8" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT2->GTPE2_LOGIC_OUTS_B13_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX3_4->GTPE2_CHANNEL_TXPOSTCURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR2" + }, + "GTP_CHANNEL_0.GTPE2_CLK1_7->GTPE2_CHANNEL_CLKRSVD0": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CLKRSVD0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX16_2->GTPE2_CHANNEL_TXDATA20": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA20" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_EYESCANDATAERROR->GTPE2_LOGIC_OUTS_B18_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_EYESCANDATAERROR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX19_9->GTPE2_CHANNEL_RXCHBONDI1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMMADET->GTPE2_LOGIC_OUTS_B19_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMMADET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_1->GTPE2_CHANNEL_RXSLIDE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSLIDE" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PLLCLK1->GTPE2_CHANNEL_PLL1CLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL1CLK" + }, + "GTP_CHANNEL_0.GTPE2_IMUX22_5->GTPE2_CHANNEL_TXDATA10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX35_2->GTPE2_CHANNEL_DRPADDR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX16_0->GTPE2_CHANNEL_TXSEQUENCE5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX23_5->GTPE2_CHANNEL_TXDATA11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA11" + }, + "GTP_CHANNEL_0.GTPE2_IMUX15_10->GTPE2_CHANNEL_RXOSINTID00": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID00" + }, + "GTP_CHANNEL_0.GTPE2_IMUX3_6->GTPE2_CHANNEL_TXPRECURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT0->GTPE2_LOGIC_OUTS_B5_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX10_9->GTPE2_CHANNEL_PMARSVDIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX43_9->GTPE2_CHANNEL_LOOPBACK0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX39_6->GTPE2_CHANNEL_TXELECIDLE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXELECIDLE" + }, + "GTP_CHANNEL_0.GTPE2_IMUX10_3->GTPE2_CHANNEL_TXPIPPMOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMOVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX37_10->GTPE2_CHANNEL_DRPDI12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI12" + }, + "GTP_CHANNEL_0.GTPE2_IMUX43_10->GTPE2_CHANNEL_RXLPMHFHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMHFHOLD" + }, + "GTP_CHANNEL_0.GTPE2_IMUX13_10->GTPE2_CHANNEL_RXPRBSCNTRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSCNTRESET" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT0->GTPE2_LOGIC_OUTS_B9_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX26_6->GTPE2_CHANNEL_GTRSVD11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD11" }, "GTP_CHANNEL_0.GTPE2_IMUX19_5->GTPE2_CHANNEL_TXDATA9": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA9", - "is_directional": "1", "src_wire": "GTPE2_IMUX19_5", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX46_9->GTPE2_CHANNEL_LOOPBACK1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXHEADER2->GTPE2_LOGIC_OUTS_B17_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX17_4->GTPE2_CHANNEL_TXDATA13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA13" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXGEARBOXREADY->GTPE2_LOGIC_OUTS_B23_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXGEARBOXREADY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX25_5->GTPE2_CHANNEL_PCSRSVDIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX35_6->GTPE2_CHANNEL_TXPD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPD1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO0->GTPE2_LOGIC_OUTS_B12_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_3" + }, + "GTP_CHANNEL_0.GTPE2_CTRL0_5->GTPE2_CHANNEL_GTTXRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTTXRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX45_2->GTPE2_CHANNEL_RXSYSCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPRBSERR->GTPE2_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPRBSERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX18_9->GTPE2_CHANNEL_RXCHBONDI0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX30_8->GTPE2_CHANNEL_RXCDRHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRHOLD" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXRATEDONE->GTPE2_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXRATEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX35_3->GTPE2_CHANNEL_DRPADDR6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX6_5->GTPE2_CHANNEL_TXDIFFCTRL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX20_4->GTPE2_CHANNEL_TXDATA14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA14" + }, + "GTP_CHANNEL_0.GTPE2_IMUX17_9->GTPE2_CHANNEL_RXCHBONDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXNOTINTABLE1->GTPE2_LOGIC_OUTS_B14_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX9_8->GTPE2_CHANNEL_PCSRSVDIN13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN13" + }, + "GTP_CHANNEL_0.GTPE2_IMUX29_7->GTPE2_CHANNEL_RXADAPTSELTEST8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX21_6->GTPE2_CHANNEL_TXDATA7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX35_1->GTPE2_CHANNEL_TXSEQUENCE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX21_2->GTPE2_CHANNEL_TXDATA23": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA23" + }, + "GTP_CHANNEL_0.GTPE2_IMUX28_3->GTPE2_CHANNEL_DRPWE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPWE" + }, + "GTP_CHANNEL_0.GTPE2_IMUX28_4->GTPE2_CHANNEL_TXSYSCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHANBONDSEQ->GTPE2_LOGIC_OUTS_B8_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANBONDSEQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX36_7->GTPE2_CHANNEL_RXOSINTNTRLEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTNTRLEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXRATEDONE->GTPE2_LOGIC_OUTS_B23_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXRATEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX9_6->GTPE2_CHANNEL_PCSRSVDIN11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN11" + }, + "GTP_CHANNEL_0.GTPE2_IMUX16_10->GTPE2_CHANNEL_DRPDI15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI15" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISCOMMA2->GTPE2_LOGIC_OUTS_B15_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX26_7->GTPE2_CHANNEL_GTRSVD12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD12" + }, + "GTP_CHANNEL_0.GTPE2_IMUX34_4->GTPE2_CHANNEL_SETERRSTATUS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_SETERRSTATUS" + }, + "GTP_CHANNEL_0.GTPE2_IMUX46_4->GTPE2_CHANNEL_TXCHARDISPVAL3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX0_9->GTPE2_CHANNEL_RXOSINTOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTOVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA10->GTPE2_LOGIC_OUTS_B4_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX1_4->GTPE2_CHANNEL_TXMAINCURSOR6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX45_3->GTPE2_CHANNEL_TXDLYSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYSRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX25_4->GTPE2_CHANNEL_PCSRSVDIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX30_3->GTPE2_CHANNEL_TXPOLARITY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOLARITY" + }, + "GTP_CHANNEL_0.GTPE2_IMUX38_4->GTPE2_CHANNEL_TXMARGIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA15->GTPE2_LOGIC_OUTS_B5_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_7" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA7->GTPE2_LOGIC_OUTS_B5_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_9" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PLLREFCLK1->GTPE2_CHANNEL_PLL1REFCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLREFCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL1REFCLK" + }, + "GTP_CHANNEL_0.GTPE2_IMUX38_10->GTPE2_CHANNEL_RXOSINTCFG0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX13_8->GTPE2_CHANNEL_RXOSOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSOVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX6_10->GTPE2_CHANNEL_RXOSINTCFG1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX23_9->GTPE2_CHANNEL_RXCHBONDI3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_5->GTPE2_CHANNEL_TSTIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX44_0->GTPE2_CHANNEL_TXPHOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHOVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX11_5->GTPE2_CHANNEL_TXDLYHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYHOLD" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXRESETDONE->GTPE2_LOGIC_OUTS_B18_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX33_5->GTPE2_CHANNEL_DRPDI10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX33_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI10" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXSYNCOUT->GTPE2_LOGIC_OUTS_B14_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXSYNCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX22_3->GTPE2_CHANNEL_TXDATA18": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA18" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_10->GTPE2_CHANNEL_TSTIN9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX24_9->GTPE2_CHANNEL_TSTIN18": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN18" + }, + "GTP_CHANNEL_0.GTPE2_CLK1_8->GTPE2_CHANNEL_CLKRSVD1": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CLKRSVD1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX23_3->GTPE2_CHANNEL_TXDATA19": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA19" + }, + "GTP_CHANNEL_0.GTPE2_IMUX19_3->GTPE2_CHANNEL_TXDATA17": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA17" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT13->GTPE2_LOGIC_OUTS_B1_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_6" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXDLYSRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX15_3->GTPE2_CHANNEL_TX8B10BBYPASS2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX35_0->GTPE2_CHANNEL_TXSEQUENCE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX4_4->GTPE2_CHANNEL_TXMAINCURSOR5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX6_6->GTPE2_CHANNEL_TXPRECURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX4_0->GTPE2_CHANNEL_RXCHBONDLEVEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX2_10->GTPE2_CHANNEL_RXOUTCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX39_3->GTPE2_CHANNEL_DRPADDR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_6->GTPE2_CHANNEL_TSTIN5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX21_1->GTPE2_CHANNEL_TXDATA31": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA31" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA16->GTPE2_LOGIC_OUTS_B6_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX14_10->GTPE2_CHANNEL_RXPHOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHOVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_CLK1_4->GTPE2_CHANNEL_SIGVALIDCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_SIGVALIDCLK" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT12->GTPE2_LOGIC_OUTS_B7_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_2->GTPE2_CHANNEL_RXSYSCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX5_10->GTPE2_CHANNEL_RXOUTCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL1" + }, + "GTP_CHANNEL_0.GTPE2_CLK0_7->GTPE2_CHANNEL_RXUSRCLK2": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSRCLK2" + }, + "GTP_CHANNEL_0.GTPE2_CTRL1_6->GTPE2_CHANNEL_RXBUFRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXBUFRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX1_10->GTPE2_CHANNEL_RXELECIDLEMODE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX7_1->GTPE2_CHANNEL_TXSYNCIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCIN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX26_4->GTPE2_CHANNEL_GTRSVD9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD9" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO2->GTPE2_LOGIC_OUTS_B4_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFSTATUS2->GTPE2_LOGIC_OUTS_B17_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX7_8->GTPE2_CHANNEL_TXPRBSSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPHALIGNDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX2_3->GTPE2_CHANNEL_DRPADDR8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR8" }, "GTP_CHANNEL_0.GTPE2_IMUX44_2->GTPE2_CHANNEL_TXSYNCALLIN": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCALLIN", - "is_directional": "1", "src_wire": "GTPE2_IMUX44_2", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCALLIN" + }, + "GTP_CHANNEL_0.GTPE2_CLK0_5->GTPE2_CHANNEL_TXUSRCLK2": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSRCLK2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PLLREFCLK0->GTPE2_CHANNEL_PLL0REFCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLREFCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL0REFCLK" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTARTOFSEQ0->GTPE2_LOGIC_OUTS_B18_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX41_6->GTPE2_CHANNEL_RXPHALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHALIGNEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX35_5->GTPE2_CHANNEL_TXDEEMPH": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDEEMPH" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXP_PAD->GTPE2_CHANNEL_RXP": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXP_PAD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXP" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA22->GTPE2_LOGIC_OUTS_B1_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX44_3->GTPE2_CHANNEL_DRPEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR4->GTPE2_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX6_8->GTPE2_CHANNEL_TXPRBSSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA25->GTPE2_LOGIC_OUTS_B2_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX7_7->GTPE2_CHANNEL_TXPRECURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR4" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA5->GTPE2_LOGIC_OUTS_B7_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX16_4->GTPE2_CHANNEL_TXDATA12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA12" + }, + "GTP_CHANNEL_0.GTPE2_IMUX35_4->GTPE2_CHANNEL_TXMARGIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT3->GTPE2_LOGIC_OUTS_B9_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX16_1->GTPE2_CHANNEL_TXDATA28": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA28" + }, + "GTP_CHANNEL_0.GTPE2_IMUX36_2->GTPE2_CHANNEL_RXSYNCALLIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCALLIN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO11->GTPE2_LOGIC_OUTS_B1_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_8" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFSTATUS0->GTPE2_LOGIC_OUTS_B23_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_10" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA27->GTPE2_LOGIC_OUTS_B0_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_4" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT5->GTPE2_LOGIC_OUTS_B13_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX39_1->GTPE2_CHANNEL_TXHEADER0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX10_7->GTPE2_CHANNEL_TXBUFDIFFCTRL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX8_0->GTPE2_CHANNEL_TXSEQUENCE6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX0_2->GTPE2_CHANNEL_TX8B10BEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXBUFSTATUS1->GTPE2_LOGIC_OUTS_B19_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX2_6->GTPE2_CHANNEL_TXPRECURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX7_4->GTPE2_CHANNEL_TXPOSTCURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO9->GTPE2_LOGIC_OUTS_B4_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_9" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR1->GTPE2_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX8_3->GTPE2_CHANNEL_TXPIPPMSEL": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSEL" + }, + "GTP_CHANNEL_0.GTPE2_IMUX29_10->GTPE2_CHANNEL_TXDATA27": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA27" + }, + "GTP_CHANNEL_0.GTPE2_IMUX21_4->GTPE2_CHANNEL_TXDATA15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA15" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXBUFSTATUS1->GTPE2_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_3->GTPE2_CHANNEL_TSTIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX3_1->GTPE2_CHANNEL_TXCOMWAKE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMWAKE" + }, + "GTP_CHANNEL_0.GTPE2_IMUX30_6->GTPE2_CHANNEL_TXPOSTCURSORINV": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSORINV" + }, + "GTP_CHANNEL_0.GTPE2_IMUX6_0->GTPE2_CHANNEL_RXUSERRDY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSERRDY" + }, + "GTP_CHANNEL_0.GTPE2_IMUX11_10->GTPE2_CHANNEL_RXOSINTID03": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID03" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT9->GTPE2_LOGIC_OUTS_B13_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX18_7->GTPE2_CHANNEL_TXDATA0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA0" + }, + "GTP_CHANNEL_0.GTPE2_CLK0_9->GTPE2_CHANNEL_DRPCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPCLK" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCLKCORCNT0->GTPE2_LOGIC_OUTS_B11_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX0_10->GTPE2_CHANNEL_RXELECIDLEMODE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA21->GTPE2_LOGIC_OUTS_B7_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_5" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPMARESETDONE->GTPE2_LOGIC_OUTS_B12_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPMARESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX5_5->GTPE2_CHANNEL_RXLPMLFHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMLFHOLD" + }, + "GTP_CHANNEL_0.GTPE2_IMUX14_9->GTPE2_CHANNEL_RXPHALIGN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHALIGN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX25_8->GTPE2_CHANNEL_PCSRSVDIN5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_7->GTPE2_CHANNEL_TSTIN6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX41_5->GTPE2_CHANNEL_RESETOVRD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RESETOVRD" + }, + "GTP_CHANNEL_0.GTPE2_IMUX8_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX31_1->GTPE2_CHANNEL_TXHEADER1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPRDY->GTPE2_LOGIC_OUTS_B14_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX39_2->GTPE2_CHANNEL_DRPADDR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR0" + }, + "GTP_CHANNEL_0.GTPE2_CLK0_4->GTPE2_CHANNEL_TXUSRCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSRCLK" + }, + "GTP_CHANNEL_0.GTPE2_IMUX17_8->GTPE2_CHANNEL_RXADAPTSELTEST11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST11" + }, + "GTP_CHANNEL_0.GTPE2_IMUX0_7->GTPE2_CHANNEL_RXADAPTSELTEST0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO6->GTPE2_LOGIC_OUTS_B22_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_5" + }, + "GTP_CHANNEL_0.GTPE2_CTRL1_4->GTPE2_CHANNEL_RXPHDLYRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHDLYRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX7_0->GTPE2_CHANNEL_RXSYNCIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCIN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT4->GTPE2_LOGIC_OUTS_B9_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX41_0->GTPE2_CHANNEL_RXDLYOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYOVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCDRLOCK->GTPE2_LOGIC_OUTS_B17_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCDRLOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX5_0->GTPE2_CHANNEL_RXCHBONDLEVEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATAVALID0->GTPE2_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATAVALID0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX25_9->GTPE2_CHANNEL_PCSRSVDIN6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX32_2->GTPE2_CHANNEL_TXINHIBIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXINHIBIT" + }, + "GTP_CHANNEL_0.GTPE2_IMUX24_10->GTPE2_CHANNEL_TSTIN19": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN19" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXNOTINTABLE0->GTPE2_LOGIC_OUTS_B14_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX45_7->GTPE2_CHANNEL_TXPISOPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPISOPD" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_7->GTPE2_CHANNEL_GTRSVD4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX30_9->GTPE2_CHANNEL_RXCHBONDMASTER": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDMASTER" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXP->GTPE2_CHANNEL_TXP_PAD": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXP_PAD" + }, + "GTP_CHANNEL_0.GTPE2_IMUX26_8->GTPE2_CHANNEL_GTRSVD13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD13" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSYNCDONE->GTPE2_LOGIC_OUTS_B14_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSYNCDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX31_7->GTPE2_CHANNEL_TXCHARISK0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK0" + }, + "GTP_CHANNEL_0.GTPE2_CLK1_2->GTPE2_CHANNEL_TXPHDLYTSTCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYTSTCLK" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXNOTINTABLE2->GTPE2_LOGIC_OUTS_B14_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX38_2->GTPE2_CHANNEL_DRPADDR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX1_3->GTPE2_CHANNEL_TXMAINCURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX23_7->GTPE2_CHANNEL_TXDATA3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA3" + }, + "GTP_CHANNEL_0.GTPE2_CTRL0_10->GTPE2_CHANNEL_GTRESETSEL": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRESETSEL" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA30->GTPE2_LOGIC_OUTS_B1_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX44_7->GTPE2_CHANNEL_RXADAPTSELTEST7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX41_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDO2->GTPE2_LOGIC_OUTS_B16_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX32_6->GTPE2_CHANNEL_DRPDI3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO5->GTPE2_LOGIC_OUTS_B12_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_5" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTSTROBEDONE->GTPE2_LOGIC_OUTS_B0_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX30_10->GTPE2_CHANNEL_RXCHBONDSLAVE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDSLAVE" + }, + "GTP_CHANNEL_0.GTPE2_IMUX27_0->GTPE2_CHANNEL_TXSEQUENCE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA2->GTPE2_LOGIC_OUTS_B4_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_10" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA20->GTPE2_LOGIC_OUTS_B3_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_5" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT1->GTPE2_LOGIC_OUTS_B0_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX31_0->GTPE2_CHANNEL_TXUSERRDY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSERRDY" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT6->GTPE2_LOGIC_OUTS_B9_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX0_3->GTPE2_CHANNEL_TXMAINCURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX13_7->GTPE2_CHANNEL_TXBUFDIFFCTRL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISCOMMA1->GTPE2_LOGIC_OUTS_B15_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX24_4->GTPE2_CHANNEL_TSTIN13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN13" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATAVALID1->GTPE2_LOGIC_OUTS_B5_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATAVALID1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX39_4->GTPE2_CHANNEL_TXMARGIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX15_6->GTPE2_CHANNEL_RXRATE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_9->GTPE2_CHANNEL_TSTIN8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX13_0->GTPE2_CHANNEL_TXSYNCMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCMODE" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTATUS2->GTPE2_LOGIC_OUTS_B23_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX25_7->GTPE2_CHANNEL_PCSRSVDIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX7_2->GTPE2_CHANNEL_RXLPMOSINTNTRLEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDO1->GTPE2_LOGIC_OUTS_B16_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_9" + }, + "GTP_CHANNEL_0.GTPE2_CTRL0_6->GTPE2_CHANNEL_RXDLYSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYSRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_4->GTPE2_CHANNEL_TSTIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX46_0->GTPE2_CHANNEL_TXPCSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPCSRESET" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDISPERR2->GTPE2_LOGIC_OUTS_B22_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_5->GTPE2_CHANNEL_GTRSVD2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO1->GTPE2_LOGIC_OUTS_B22_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO14->GTPE2_LOGIC_OUTS_B12_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX15_7->GTPE2_CHANNEL_TX8B10BBYPASS0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXCOMFINISH->GTPE2_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXCOMFINISH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_8->GTPE2_CHANNEL_GTRSVD5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX24_7->GTPE2_CHANNEL_TSTIN16": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN16" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXN->GTPE2_CHANNEL_TXN_PAD": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXN_PAD" + }, + "GTP_CHANNEL_0.GTPE2_IMUX47_6->GTPE2_CHANNEL_TXRATE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA12->GTPE2_LOGIC_OUTS_B3_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX17_6->GTPE2_CHANNEL_TXDATA5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA5" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISK0->GTPE2_LOGIC_OUTS_B12_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX46_1->GTPE2_CHANNEL_RXPCSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPCSRESET" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA0->GTPE2_LOGIC_OUTS_B6_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_10" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO13->GTPE2_LOGIC_OUTS_B15_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_8" + }, + "GTP_CHANNEL_0.GTPE2_IMUX25_3->GTPE2_CHANNEL_PCSRSVDIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DRPDO3->GTPE2_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX22_6->GTPE2_CHANNEL_TXPIPPMSTEPSIZE4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX28_6->GTPE2_CHANNEL_RXDLYEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX46_3->GTPE2_CHANNEL_TXPIPPMPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMPD" + }, + "GTP_CHANNEL_0.GTPE2_IMUX36_10->GTPE2_CHANNEL_DRPDI13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI13" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKPCS->GTPE2_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOUTCLKPCS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT12->GTPE2_LOGIC_OUTS_B15_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_2" + }, + "GTP_CHANNEL_0.GTPE2_CTRL1_9->GTPE2_CHANNEL_RXCDRRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX36_5->GTPE2_CHANNEL_TXPHDLYRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX22_7->GTPE2_CHANNEL_TXDATA2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHANISALIGNED->GTPE2_LOGIC_OUTS_B18_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANISALIGNED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX24_8->GTPE2_CHANNEL_TSTIN17": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN17" + }, + "GTP_CHANNEL_0.GTPE2_CTRL0_9->GTPE2_CHANNEL_RXLPMRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX4_7->GTPE2_CHANNEL_RXADAPTSELTEST2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX27_5->GTPE2_CHANNEL_TXPHINIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHINIT" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXN_PAD->GTPE2_CHANNEL_RXN": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXN_PAD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX20_2->GTPE2_CHANNEL_TXDATA22": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA22" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA29->GTPE2_LOGIC_OUTS_B7_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_3" + }, + "GTP_CHANNEL_0.GTPE2_CTRL1_8->GTPE2_CHANNEL_RXCDRRESETRSV": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRRESETRSV" + }, + "GTP_CHANNEL_0.GTPE2_IMUX28_8->GTPE2_CHANNEL_RXPD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPD1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR1->GTPE2_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR3->GTPE2_LOGIC_OUTS_B3_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX14_0->GTPE2_CHANNEL_TXPDELECIDLEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPDELECIDLEMODE" + }, + "GTP_CHANNEL_0.GTPE2_IMUX46_6->GTPE2_CHANNEL_TXRATE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_GTTXOUTCLK_0->GTPE2_CHANNEL_TXOUTCLK_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_GTTXOUTCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLK_0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA9->GTPE2_LOGIC_OUTS_B2_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_8" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXSTATUS0->GTPE2_LOGIC_OUTS_B21_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_8" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT2->GTPE2_LOGIC_OUTS_B9_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_8" }, "GTP_CHANNEL_0.GTPE2_CHANNEL_RXVALID->GTPE2_LOGIC_OUTS_B20_9": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_9", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_RXVALID", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX11_6->GTPE2_CHANNEL_RXRATE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXPHINITDONE->GTPE2_LOGIC_OUTS_B1_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPHINITDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX38_3->GTPE2_CHANNEL_DRPADDR5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR5" + }, + "GTP_CHANNEL_0.GTPE2_IMUX8_4->GTPE2_CHANNEL_TXCHARDISPVAL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL1" + }, + "GTP_CHANNEL_0.GTPE2_CTRL1_5->GTPE2_CHANNEL_CFGRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CFGRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX26_10->GTPE2_CHANNEL_GTRSVD15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD15" + }, + "GTP_CHANNEL_0.GTPE2_IMUX42_0->GTPE2_CHANNEL_TXPIPPMEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX5_7->GTPE2_CHANNEL_RXADAPTSELTEST3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT15->GTPE2_LOGIC_OUTS_B15_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX37_8->GTPE2_CHANNEL_PMARSVDIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX31_8->GTPE2_CHANNEL_EYESCANTRIGGER": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANTRIGGER" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXPMARESETDONE->GTPE2_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPMARESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX27_10->GTPE2_CHANNEL_RXLPMHFOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMHFOVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCOMWAKEDET->GTPE2_LOGIC_OUTS_B12_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMWAKEDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_0->GTPE2_CHANNEL_RXSYNCMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCMODE" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHMONITOR2->GTPE2_LOGIC_OUTS_B7_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_2" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT13->GTPE2_LOGIC_OUTS_B9_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX19_7->GTPE2_CHANNEL_TXDATA1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX43_6->GTPE2_CHANNEL_TXRATE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX33_2->GTPE2_CHANNEL_TXPHALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX33_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHALIGNEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX1_8->GTPE2_CHANNEL_TXOUTCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX6_4->GTPE2_CHANNEL_TXPOSTCURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX8_6->GTPE2_CHANNEL_TXCHARDISPVAL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXNOTINTABLE3->GTPE2_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_4" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA17->GTPE2_LOGIC_OUTS_B2_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX11_3->GTPE2_CHANNEL_TXRATEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATEMODE" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISK3->GTPE2_LOGIC_OUTS_B12_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX14_8->GTPE2_CHANNEL_RXCDROVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDROVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA14->GTPE2_LOGIC_OUTS_B1_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX15_9->GTPE2_CHANNEL_RXOSINTEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTEN" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA13->GTPE2_LOGIC_OUTS_B7_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX32_8->GTPE2_CHANNEL_RXDLYBYPASS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYBYPASS" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA3->GTPE2_LOGIC_OUTS_B0_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX5_8->GTPE2_CHANNEL_TXOUTCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHALIGNDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX46_10->GTPE2_CHANNEL_RXOSINTCFG3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX3_8->GTPE2_CHANNEL_TXPRBSSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL0" + }, + "GTP_CHANNEL_0.GTPE2_CTRL1_10->GTPE2_CHANNEL_RXOOBRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOOBRESET" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_DMONITOROUT14->GTPE2_LOGIC_OUTS_B10_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_5" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA19->GTPE2_LOGIC_OUTS_B0_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX29_2->GTPE2_CHANNEL_TXCHARDISPMODE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX1_7->GTPE2_CHANNEL_RXADAPTSELTEST1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX13_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX29_4->GTPE2_CHANNEL_TXCHARDISPMODE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE1" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOSINTDONE->GTPE2_LOGIC_OUTS_B3_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_6" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR0->GTPE2_LOGIC_OUTS_B13_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX23_8->GTPE2_CHANNEL_RXPRBSSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX27_1->GTPE2_CHANNEL_TXSEQUENCE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX5_2->GTPE2_CHANNEL_PMARSVDIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN3" + }, + "GTP_CHANNEL_0.GTPE2_IMUX24_2->GTPE2_CHANNEL_TSTIN11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN11" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT14->GTPE2_LOGIC_OUTS_B5_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_6" + }, + "GTP_CHANNEL_0.GTPE2_IMUX45_8->GTPE2_CHANNEL_EYESCANRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANRESET" + }, + "GTP_CHANNEL_0.GTPE2_IMUX30_7->GTPE2_CHANNEL_RXPD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPD0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX10_10->GTPE2_CHANNEL_RXOSINTID02": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID02" + }, + "GTP_CHANNEL_0.GTPE2_IMUX5_9->GTPE2_CHANNEL_RXOSINTTESTOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN" + }, + "GTP_CHANNEL_0.GTPE2_IMUX47_9->GTPE2_CHANNEL_LOOPBACK2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX41_10->GTPE2_CHANNEL_TXDATA25": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA25" + }, + "GTP_CHANNEL_0.GTPE2_IMUX24_3->GTPE2_CHANNEL_TSTIN12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN12" + }, + "GTP_CHANNEL_0.GTPE2_IMUX9_10->GTPE2_CHANNEL_PCSRSVDIN15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN15" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX22_9->GTPE2_CHANNEL_RXCHBONDI2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI2" + }, + "GTP_CHANNEL_0.GTPE2_IMUX26_3->GTPE2_CHANNEL_GTRSVD8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD8" + }, + "GTP_CHANNEL_0.GTPE2_CLK1_5->GTPE2_CHANNEL_DMONITORCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DMONITORCLK" + }, + "GTP_CHANNEL_0.GTPE2_IMUX7_3->GTPE2_CHANNEL_TXPOSTCURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR4" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA1->GTPE2_LOGIC_OUTS_B2_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_10" + }, + "GTP_CHANNEL_0.GTPE2_IMUX1_0->GTPE2_CHANNEL_RXCHBONDLEVEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL0" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXPHSLIPMONITOR2->GTPE2_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX10_6->GTPE2_CHANNEL_DRPDI1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX7_6->GTPE2_CHANNEL_TXPRECURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX3_3->GTPE2_CHANNEL_TXSTARTSEQ": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSTARTSEQ" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PLLCLK0->GTPE2_CHANNEL_PLL0CLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL0CLK" + }, + "GTP_CHANNEL_0.GTPE2_IMUX2_7->GTPE2_CHANNEL_RXRATEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATEMODE" + }, + "GTP_CHANNEL_0.GTPE2_IMUX14_1->GTPE2_CHANNEL_TXPRBSFORCEERR": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSFORCEERR" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDISPERR3->GTPE2_LOGIC_OUTS_B22_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX40_2->GTPE2_CHANNEL_TSTIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN1" + }, + "GTP_CHANNEL_0.GTPE2_IMUX11_7->GTPE2_CHANNEL_RXADAPTSELTEST9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST9" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHBONDO3->GTPE2_LOGIC_OUTS_B16_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_7" + }, + "GTP_CHANNEL_0.GTPE2_IMUX8_7->GTPE2_CHANNEL_RXPHDLYPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHDLYPD" + }, + "GTP_CHANNEL_0.GTPE2_IMUX47_4->GTPE2_CHANNEL_TXCHARISK3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK3" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXDATA11->GTPE2_LOGIC_OUTS_B0_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_8" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_RXCHARISCOMMA0->GTPE2_LOGIC_OUTS_B15_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_9" + }, + "GTP_CHANNEL_0.GTPE2_IMUX5_4->GTPE2_CHANNEL_TXMAINCURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR4" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_PCSRSVDOUT6->GTPE2_LOGIC_OUTS_B13_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_6" + }, + "GTP_CHANNEL_0.GTPE2_CHANNEL_TXRESETDONE->GTPE2_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_4" + }, + "GTP_CHANNEL_0.GTPE2_IMUX29_6->GTPE2_CHANNEL_TXCHARDISPMODE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE0" + }, + "GTP_CHANNEL_0.GTPE2_IMUX1_9->GTPE2_CHANNEL_RXOSINTHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTHOLD" + }, + "GTP_CHANNEL_0.GTPE2_IMUX13_6->GTPE2_CHANNEL_DRPDI2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI2" } }, - "tile_type": "GTP_CHANNEL_0" + "wires": [ + "GTPE2_IMUX5_7", + "GTPE2_IMUX14_1", + "GTPE2_BYP0_6", + "GTPE2_IMUX23_2", + "GTPE2_BYP0_5", + "GTPE2_IMUX19_10", + "GTPE2_LOGIC_OUTS_B20_6", + "GTPE2_LOGIC_OUTS_B13_0", + "GTPE2_IMUX25_9", + "GTPE2_IMUX18_8", + "GTPE2_IMUX44_3", + "GTPE2_LOGIC_OUTS_B20_10", + "GTPE2_LOGIC_OUTS_B11_9", + "GTPE2_BYP1_10", + "GTPE2_IMUX26_0", + "GTPE2_LOGIC_OUTS_B19_5", + "GTPE2_IMUX5_2", + "GTPE2_CHANNEL_RXOSINTCFG3", + "GTPE2_IMUX30_3", + "GTPE2_CHANNEL_TXSEQUENCE6", + "GTPE2_LOGIC_OUTS_B9_4", + "GTPE2_IMUX18_1", + "GTPE2_CLK0_4", + "GTPE2_CHANNEL_DMONITOROUT2", + "GTPE2_IMUX42_3", + "GTPE2_CTRL1_5", + "GTPE2_IMUX22_3", + "GTPE2_CHANNEL_GTRSVD5", + "GTPE2_CHANNEL_RXLPMRESET", + "GTPE2_LOGIC_OUTS_B23_8", + "GTPE2_CHANNEL_TXPRBSFORCEERR", + "GTPE2_LOGIC_OUTS_B1_9", + "GTPE2_IMUX45_9", + "GTPE2_IMUX34_7", + "GTPE2_LOGIC_OUTS_B2_0", + "GTPE2_IMUX24_9", + "GTPE2_LOGIC_OUTS_B18_2", + "GTPE2_CLK1_1", + "GTPE2_CHANNEL_RXPOLARITY", + "GTPE2_CHANNEL_TSTIN14", + "GTPE2_LOGIC_OUTS_B22_9", + "GTPE2_CHANNEL_PCSRSVDOUT5", + "GTPE2_LOGIC_OUTS_B8_6", + "GTPE2_IMUX23_4", + "GTPE2_LOGIC_OUTS_B22_10", + "GTPE2_LOGIC_OUTS_B6_9", + "GTPE2_IMUX33_7", + "GTPE2_CHANNEL_RXRATE0", + "GTPE2_FAN5_8", + "GTPE2_IMUX25_3", + "GTPE2_IMUX23_5", + "GTPE2_BYP5_10", + "GTPE2_IMUX19_6", + "GTPE2_CHANNEL_RXP", + "GTPE2_CHANNEL_TXDATA11", + "GTPE2_FAN7_2", + "GTPE2_CHANNEL_TSTPDOVRDB", + "GTPE2_CHANNEL_RXOUTCLKSEL2", + "GTPE2_CHANNEL_RXSYNCALLIN", + "GTPE2_FAN3_3", + "GTPE2_CHANNEL_DRPDO6", + "GTPE2_IMUX2_4", + "GTPE2_IMUX37_6", + "GTPE2_IMUX17_2", + "GTPE2_IMUX6_6", + "GTPE2_CHANNEL_TSTCLK1", + "GTPE2_CHANNEL_TXDATA2", + "GTPE2_IMUX0_2", + "GTPE2_IMUX28_0", + "GTPE2_CHANNEL_RXCLKCORCNT1", + "GTPE2_LOGIC_OUTS_B21_1", + "GTPE2_LOGIC_OUTS_B16_9", + "GTPE2_IMUX33_10", + "GTPE2_IMUX42_4", + "GTPE2_CHANNEL_RXOSINTID01", + "GTPE2_IMUX26_8", + "GTPE2_IMUX0_9", + "GTPE2_BYP5_3", + "GTPE2_IMUX38_1", + "GTPE2_CHANNEL_RXSYNCMODE", + "GTPE2_FAN7_10", + "GTPE2_IMUX22_4", + "GTPE2_IMUX43_1", + "GTPE2_CHANNEL_RXDATA9", + "GTPE2_IMUX9_5", + "GTPE2_BYP1_3", + "GTPE2_CHANNEL_DMONFIFORESET", + "GTPE2_CHANNEL_DMONITOROUT11", + "GTPE2_IMUX16_3", + "GTPE2_CHANNEL_TXSEQUENCE3", + "GTPE2_CHANNEL_RXCHBONDI2", + "GTPE2_IMUX0_4", + "GTPE2_IMUX24_2", + "GTPE2_IMUX3_2", + "GTPE2_LOGIC_OUTS_B6_8", + "GTPE2_LOGIC_OUTS_B4_10", + "GTPE2_CHANNEL_RXSYNCOUT", + "GTPE2_LOGIC_OUTS_B13_10", + "GTPE2_IMUX34_8", + "GTPE2_LOGIC_OUTS_B0_1", + "GTPE2_IMUX40_6", + "GTPE2_IMUX7_0", + "GTPE2_IMUX34_9", + "GTPE2_IMUX26_10", + "GTPE2_IMUX37_7", + "GTPE2_CHANNEL_RXPRBSSEL1", + "GTPE2_IMUX19_1", + "GTPE2_CHANNEL_RXNOTINTABLE1", + "GTPE2_IMUX29_0", + "GTPE2_LOGIC_OUTS_B18_1", + "GTPE2_CHANNEL_PLLREFCLK1", + "GTPE2_IMUX37_0", + "GTPE2_FAN6_8", + "GTPE2_CHANNEL_TXSYNCMODE", + "GTPE2_CHANNEL_RXPHMONITOR4", + "GTPE2_CHANNEL_DRPDI10", + "GTPE2_IMUX20_8", + "GTPE2_LOGIC_OUTS_B5_3", + "GTPE2_LOGIC_OUTS_B9_10", + "GTPE2_CHANNEL_PMASCANIN0", + "GTPE2_CHANNEL_EYESCANTRIGGER", + "GTPE2_BYP0_3", + "GTPE2_FAN6_2", + "GTPE2_CTRL0_3", + "GTPE2_CHANNEL_RXDATA19", + "GTPE2_CTRL1_1", + "GTPE2_CHANNEL_PCSRSVDIN9", + "GTPE2_IMUX17_6", + "GTPE2_CHANNEL_DRPADDR5", + "GTPE2_CHANNEL_TSTIN2", + "GTPE2_IMUX25_10", + "GTPE2_LOGIC_OUTS_B5_9", + "GTPE2_IMUX16_4", + "GTPE2_LOGIC_OUTS_B10_5", + "GTPE2_LOGIC_OUTS_B18_7", + "GTPE2_IMUX11_9", + "GTPE2_CHANNEL_RXDATA4", + "GTPE2_IMUX13_7", + "GTPE2_IMUX9_0", + "GTPE2_LOGIC_OUTS_B14_3", + "GTPE2_CHANNEL_RXDATA2", + "GTPE2_IMUX2_1", + "GTPE2_CHANNEL_RXCHBONDO3", + "GTPE2_IMUX24_10", + "GTPE2_FAN1_1", + "GTPE2_CHANNEL_TXDLYOVRDEN", + "GTPE2_CHANNEL_TXDATA0", + "GTPE2_BYP3_6", + "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "GTPE2_IMUX42_5", + "GTPE2_CHANNEL_PMASCANMODEB", + "GTPE2_BYP0_4", + "GTPE2_LOGIC_OUTS_B12_9", + "GTPE2_CHANNEL_RXDATA25", + "GTPE2_CHANNEL_RXOSCALRESET", + "GTPE2_IMUX10_9", + "GTPE2_CTRL0_6", + "GTPE2_IMUX41_10", + "GTPE2_CLK1_6", + "GTPE2_IMUX8_10", + "GTPE2_IMUX14_3", + "GTPE2_CHANNEL_RXGEARBOXSLIP", + "GTPE2_CHANNEL_GTRSVD2", + "GTPE2_IMUX36_6", + "GTPE2_CHANNEL_TXCOMFINISH", + "GTPE2_CTRL1_10", + "GTPE2_IMUX2_7", + "GTPE2_CHANNEL_PCSRSVDOUT10", + "GTPE2_IMUX13_5", + "GTPE2_CHANNEL_GTRSVD14", + "GTPE2_LOGIC_OUTS_B16_1", + "GTPE2_BYP4_6", + "GTPE2_CHANNEL_RXOSINTHOLD", + "GTPE2_IMUX34_2", + "GTPE2_LOGIC_OUTS_B20_9", + "GTPE2_IMUX22_10", + "GTPE2_IMUX9_9", + "GTPE2_CHANNEL_RXSLIDE", + "GTPE2_CLK1_0", + "GTPE2_IMUX41_2", + "GTPE2_LOGIC_OUTS_B0_7", + "GTPE2_CHANNEL_RXADAPTSELTEST5", + "GTPE2_FAN4_5", + "GTPE2_FAN3_4", + "GTPE2_CHANNEL_RXCHBONDI1", + "GTPE2_CHANNEL_RXRESETDONE", + "GTPE2_CHANNEL_TXCOMSAS", + "GTPE2_IMUX20_4", + "GTPE2_IMUX25_7", + "GTPE2_FAN3_9", + "GTPE2_CHANNEL_RXCHBONDEN", + "GTPE2_IMUX1_9", + "GTPE2_BYP1_8", + "GTPE2_IMUX29_5", + "GTPE2_LOGIC_OUTS_B1_0", + "GTPE2_CHANNEL_GTRXOUTCLK_0", + "GTPE2_CHANNEL_TXMAINCURSOR2", + "GTPE2_CTRL1_6", + "GTPE2_IMUX32_4", + "GTPE2_LOGIC_OUTS_B6_2", + "GTPE2_CHANNEL_RXOSINTID02", + "GTPE2_CHANNEL_GTRSVD10", + "GTPE2_BYP4_5", + "GTPE2_IMUX35_6", + "GTPE2_IMUX36_10", + "GTPE2_IMUX31_9", + "GTPE2_IMUX1_7", + "GTPE2_CHANNEL_TXHEADER1", + "GTPE2_IMUX27_6", + "GTPE2_CHANNEL_DMONITOROUT1", + "GTPE2_IMUX26_1", + "GTPE2_IMUX25_4", + "GTPE2_IMUX15_5", + "GTPE2_CHANNEL_PCSRSVDOUT4", + "GTPE2_IMUX30_6", + "GTPE2_BYP3_0", + "GTPE2_CHANNEL_DRPDO0", + "GTPE2_IMUX36_9", + "GTPE2_CHANNEL_DRPDI8", + "GTPE2_IMUX38_7", + "GTPE2_BYP5_2", + "GTPE2_BYP7_0", + "GTPE2_CHANNEL_DRPADDR6", + "GTPE2_LOGIC_OUTS_B7_7", + "GTPE2_LOGIC_OUTS_B13_3", + "GTPE2_LOGIC_OUTS_B2_6", + "GTPE2_CHANNEL_RXOSINTID00", + "GTPE2_FAN0_2", + "GTPE2_CHANNEL_TXUSRCLK", + "GTPE2_CHANNEL_RXPD0", + "GTPE2_IMUX0_7", + "GTPE2_IMUX33_5", + "GTPE2_LOGIC_OUTS_B20_8", + "GTPE2_LOGIC_OUTS_B6_10", + "GTPE2_LOGIC_OUTS_B12_4", + "GTPE2_IMUX16_8", + "GTPE2_CHANNEL_RXDISPERR1", + "GTPE2_LOGIC_OUTS_B3_4", + "GTPE2_CLK1_5", + "GTPE2_CHANNEL_TXDATA19", + "GTPE2_IMUX22_8", + "GTPE2_IMUX30_7", + "GTPE2_FAN6_5", + "GTPE2_CHANNEL_RXPHMONITOR3", + "GTPE2_CHANNEL_TXMAINCURSOR4", + "GTPE2_CHANNEL_PMARSVDIN1", + "GTPE2_BYP3_8", + "GTPE2_CHANNEL_RXBUFSTATUS1", + "GTPE2_CHANNEL_RXHEADER1", + "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "GTPE2_CLK0_1", + "GTPE2_LOGIC_OUTS_B6_7", + "GTPE2_BYP3_4", + "GTPE2_CHANNEL_TXMARGIN2", + "GTPE2_IMUX40_2", + "GTPE2_LOGIC_OUTS_B6_6", + "GTPE2_IMUX26_4", + "GTPE2_CHANNEL_TXPHINIT", + "GTPE2_LOGIC_OUTS_B15_5", + "GTPE2_FAN3_5", + "GTPE2_IMUX11_8", + "GTPE2_FAN0_8", + "GTPE2_IMUX12_3", + "GTPE2_CHANNEL_TXP_PAD", + "GTPE2_IMUX3_0", + "GTPE2_IMUX5_8", + "GTPE2_LOGIC_OUTS_B3_5", + "GTPE2_IMUX34_10", + "GTPE2_IMUX46_2", + "GTPE2_CHANNEL_PLL0CLK", + "GTPE2_CHANNEL_TXCHARDISPVAL2", + "GTPE2_CHANNEL_TXPISOPD", + "GTPE2_CHANNEL_TX8B10BBYPASS3", + "GTPE2_IMUX46_0", + "GTPE2_BYP2_9", + "GTPE2_CHANNEL_TSTIN16", + "GTPE2_CHANNEL_GTRSVD7", + "GTPE2_FAN6_9", + "GTPE2_IMUX3_5", + "GTPE2_LOGIC_OUTS_B15_7", + "GTPE2_IMUX41_4", + "GTPE2_CHANNEL_RXLPMHFHOLD", + "GTPE2_IMUX23_9", + "GTPE2_CHANNEL_PCSRSVDIN5", + "GTPE2_CHANNEL_SCANIN0", + "GTPE2_LOGIC_OUTS_B13_2", + "GTPE2_IMUX8_5", + "GTPE2_IMUX39_0", + "GTPE2_IMUX42_10", + "GTPE2_IMUX14_2", + "GTPE2_CHANNEL_TXDATA24", + "GTPE2_BYP1_6", + "GTPE2_IMUX28_10", + "GTPE2_FAN5_6", + "GTPE2_BYP2_3", + "GTPE2_CHANNEL_RXDATA14", + "GTPE2_IMUX24_6", + "GTPE2_CHANNEL_RXOSINTNTRLEN", + "GTPE2_LOGIC_OUTS_B1_5", + "GTPE2_LOGIC_OUTS_B8_5", + "GTPE2_LOGIC_OUTS_B3_8", + "GTPE2_IMUX9_7", + "GTPE2_IMUX9_1", + "GTPE2_IMUX44_6", + "GTPE2_CHANNEL_TXDATA12", + "GTPE2_LOGIC_OUTS_B23_5", + "GTPE2_CHANNEL_PLLCLK0", + "GTPE2_CHANNEL_TXSEQUENCE0", + "GTPE2_CHANNEL_RXELECIDLE", + "GTPE2_CHANNEL_SIGVALIDCLK", + "GTPE2_CHANNEL_TXSEQUENCE2", + "GTPE2_FAN4_7", + "GTPE2_IMUX46_4", + "GTPE2_LOGIC_OUTS_B20_1", + "GTPE2_CHANNEL_RXOSINTCFG2", + "GTPE2_LOGIC_OUTS_B19_7", + "GTPE2_IMUX22_7", + "GTPE2_LOGIC_OUTS_B2_9", + "GTPE2_IMUX31_4", + "GTPE2_IMUX8_4", + "GTPE2_IMUX26_2", + "GTPE2_FAN1_10", + "GTPE2_LOGIC_OUTS_B18_0", + "GTPE2_CHANNEL_TXRATEMODE", + "GTPE2_CHANNEL_RXOSINTCFG1", + "GTPE2_CLK1_4", + "GTPE2_IMUX2_3", + "GTPE2_CHANNEL_RXSYSCLKSEL0", + "GTPE2_CHANNEL_TXCHARISK3", + "GTPE2_LOGIC_OUTS_B4_0", + "GTPE2_IMUX7_3", + "GTPE2_IMUX21_1", + "GTPE2_BYP2_8", + "GTPE2_IMUX11_4", + "GTPE2_LOGIC_OUTS_B0_10", + "GTPE2_IMUX27_3", + "GTPE2_FAN0_9", + "GTPE2_CHANNEL_DRPDI12", + "GTPE2_LOGIC_OUTS_B21_5", + "GTPE2_CHANNEL_RXDDIEN", + "GTPE2_FAN7_0", + "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "GTPE2_CHANNEL_PCSRSVDIN8", + "GTPE2_BYP4_7", + "GTPE2_LOGIC_OUTS_B19_6", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", + "GTPE2_CHANNEL_TXSEQUENCE1", + "GTPE2_IMUX29_7", + "GTPE2_LOGIC_OUTS_B10_8", + "GTPE2_LOGIC_OUTS_B20_0", + "GTPE2_IMUX24_8", + "GTPE2_CHANNEL_RXRATEMODE", + "GTPE2_IMUX46_3", + "GTPE2_LOGIC_OUTS_B10_0", + "GTPE2_LOGIC_OUTS_B22_5", + "GTPE2_IMUX37_8", + "GTPE2_FAN7_4", + "GTPE2_IMUX44_0", + "GTPE2_LOGIC_OUTS_B21_8", + "GTPE2_CHANNEL_DRPADDR0", + "GTPE2_CHANNEL_LOOPBACK0", + "GTPE2_CHANNEL_TXPIPPMSEL", + "GTPE2_CHANNEL_PCSRSVDOUT11", + "GTPE2_BYP6_9", + "GTPE2_LOGIC_OUTS_B0_6", + "GTPE2_LOGIC_OUTS_B5_10", + "GTPE2_IMUX38_5", + "GTPE2_LOGIC_OUTS_B1_1", + "GTPE2_IMUX10_10", + "GTPE2_LOGIC_OUTS_B18_9", + "GTPE2_IMUX2_6", + "GTPE2_IMUX45_6", + "GTPE2_CHANNEL_RXBYTEISALIGNED", + "GTPE2_CHANNEL_RXDATA17", + "GTPE2_BYP2_0", + "GTPE2_FAN0_1", + "GTPE2_IMUX28_1", + "GTPE2_CHANNEL_RXUSRCLK2", + "GTPE2_CHANNEL_DRPDO15", + "GTPE2_CHANNEL_RXDATA26", + "GTPE2_IMUX4_7", + "GTPE2_IMUX27_5", + "GTPE2_BYP7_7", + "GTPE2_CHANNEL_TXDATA8", + "GTPE2_IMUX44_2", + "GTPE2_IMUX44_10", + "GTPE2_FAN2_6", + "GTPE2_CHANNEL_TXDATA26", + "GTPE2_CHANNEL_TXPCSRESET", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", + "GTPE2_IMUX35_7", + "GTPE2_IMUX45_7", + "GTPE2_CHANNEL_TXRUNDISP1", + "GTPE2_BYP6_1", + "GTPE2_IMUX16_0", + "GTPE2_IMUX30_9", + "GTPE2_IMUX31_6", + "GTPE2_LOGIC_OUTS_B19_0", + "GTPE2_CHANNEL_RXNOTINTABLE2", + "GTPE2_LOGIC_OUTS_B14_7", + "GTPE2_IMUX8_2", + "GTPE2_LOGIC_OUTS_B21_7", + "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", + "GTPE2_CHANNEL_PCSRSVDOUT12", + "GTPE2_CHANNEL_RXELECIDLEMODE0", + "GTPE2_CHANNEL_RXOUTCLK_2", + "GTPE2_FAN2_7", + "GTPE2_LOGIC_OUTS_B22_6", + "GTPE2_CHANNEL_TXPHOVRDEN", + "GTPE2_CHANNEL_RXUSERRDY", + "GTPE2_CHANNEL_PMASCANIN1", + "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "GTPE2_LOGIC_OUTS_B0_3", + "GTPE2_CHANNEL_RXADAPTSELTEST8", + "GTPE2_LOGIC_OUTS_B20_3", + "GTPE2_IMUX6_1", + "GTPE2_IMUX45_1", + "GTPE2_LOGIC_OUTS_B7_10", + "GTPE2_IMUX16_9", + "GTPE2_LOGIC_OUTS_B9_3", + "GTPE2_LOGIC_OUTS_B10_1", + "GTPE2_CHANNEL_TXPHALIGNEN", + "GTPE2_IMUX1_5", + "GTPE2_FAN0_4", + "GTPE2_LOGIC_OUTS_B17_7", + "GTPE2_CTRL0_1", + "GTPE2_BYP6_3", + "GTPE2_BYP5_1", + "GTPE2_LOGIC_OUTS_B10_6", + "GTPE2_FAN7_7", + "GTPE2_CHANNEL_PLL1REFCLK", + "GTPE2_IMUX18_7", + "GTPE2_BYP2_10", + "GTPE2_CHANNEL_RXCOMSASDET", + "GTPE2_LOGIC_OUTS_B19_4", + "GTPE2_IMUX35_5", + "GTPE2_CHANNEL_PCSRSVDOUT2", + "GTPE2_CHANNEL_TXPOSTCURSOR0", + "GTPE2_CHANNEL_TXPDELECIDLEMODE", + "GTPE2_BYP7_2", + "GTPE2_CHANNEL_DRPDI14", + "GTPE2_CHANNEL_TSTIN0", + "GTPE2_CHANNEL_CLKRSVD1", + "GTPE2_IMUX25_0", + "GTPE2_LOGIC_OUTS_B10_4", + "GTPE2_IMUX33_9", + "GTPE2_CHANNEL_TSTPD1", + "GTPE2_CHANNEL_TSTIN18", + "GTPE2_CHANNEL_TXHEADER0", + "GTPE2_IMUX36_8", + "GTPE2_CHANNEL_GTRSVD9", + "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "GTPE2_FAN3_2", + "GTPE2_CHANNEL_GTRSVD6", + "GTPE2_IMUX27_7", + "GTPE2_CHANNEL_DRPDO13", + "GTPE2_CHANNEL_PMARSVDIN4", + "GTPE2_IMUX36_3", + "GTPE2_IMUX29_10", + "GTPE2_IMUX40_9", + "GTPE2_CHANNEL_EYESCANMODE", + "GTPE2_CHANNEL_RXCDRRESETRSV", + "GTPE2_IMUX44_8", + "GTPE2_CHANNEL_PMASCANOUT4", + "GTPE2_CHANNEL_RXDATA3", + "GTPE2_LOGIC_OUTS_B5_0", + "GTPE2_BYP5_0", + "GTPE2_CHANNEL_TX8B10BBYPASS0", + "GTPE2_LOGIC_OUTS_B15_9", + "GTPE2_IMUX0_0", + "GTPE2_IMUX24_3", + "GTPE2_CHANNEL_PMARSVDIN3", + "GTPE2_LOGIC_OUTS_B4_6", + "GTPE2_CHANNEL_RXDATA0", + "GTPE2_IMUX22_1", + "GTPE2_IMUX38_8", + "GTPE2_FAN3_10", + "GTPE2_CHANNEL_TXCOMINIT", + "GTPE2_IMUX15_10", + "GTPE2_IMUX39_4", + "GTPE2_CHANNEL_RXCLKCORCNT0", + "GTPE2_BYP1_1", + "GTPE2_IMUX31_1", + "GTPE2_IMUX20_0", + "GTPE2_BYP0_8", + "GTPE2_IMUX24_0", + "GTPE2_CHANNEL_TXDIFFCTRL0", + "GTPE2_BYP0_9", + "GTPE2_IMUX21_10", + "GTPE2_CHANNEL_TXSYNCDONE", + "GTPE2_CHANNEL_PMASCANIN2", + "GTPE2_LOGIC_OUTS_B8_4", + "GTPE2_CHANNEL_TSTIN3", + "GTPE2_CHANNEL_TXDATA15", + "GTPE2_IMUX13_8", + "GTPE2_IMUX11_3", + "GTPE2_IMUX27_1", + "GTPE2_LOGIC_OUTS_B1_4", + "GTPE2_CHANNEL_TXSEQUENCE4", + "GTPE2_IMUX44_5", + "GTPE2_CTRL0_2", + "GTPE2_LOGIC_OUTS_B18_8", + "GTPE2_CHANNEL_DMONITOROUT9", + "GTPE2_BYP4_0", + "GTPE2_FAN0_10", + "GTPE2_FAN1_2", + "GTPE2_CHANNEL_RXCOMMADET", + "GTPE2_IMUX22_6", + "GTPE2_BYP4_3", + "GTPE2_IMUX42_7", + "GTPE2_CHANNEL_TXSTARTSEQ", + "GTPE2_LOGIC_OUTS_B11_0", + "GTPE2_IMUX44_7", + "GTPE2_CHANNEL_PCSRSVDIN2", + "GTPE2_IMUX30_0", + "GTPE2_LOGIC_OUTS_B23_10", + "GTPE2_IMUX4_1", + "GTPE2_LOGIC_OUTS_B8_2", + "GTPE2_CHANNEL_RXDISPERR3", + "GTPE2_IMUX46_6", + "GTPE2_CTRL0_5", + "GTPE2_CHANNEL_RXCHARISK3", + "GTPE2_IMUX3_7", + "GTPE2_CHANNEL_DRPDO3", + "GTPE2_IMUX17_0", + "GTPE2_LOGIC_OUTS_B6_4", + "GTPE2_FAN2_10", + "GTPE2_CHANNEL_DRPDI0", + "GTPE2_BYP6_4", + "GTPE2_CLK0_5", + "GTPE2_FAN4_0", + "GTPE2_CHANNEL_SCANIN4", + "GTPE2_IMUX4_2", + "GTPE2_IMUX39_6", + "GTPE2_LOGIC_OUTS_B8_9", + "GTPE2_LOGIC_OUTS_B15_8", + "GTPE2_IMUX23_6", + "GTPE2_IMUX9_6", + "GTPE2_IMUX8_9", + "GTPE2_CTRL1_0", + "GTPE2_CLK1_10", + "GTPE2_CHANNEL_RXCDRLOCK", + "GTPE2_CHANNEL_PCSRSVDOUT6", + "GTPE2_IMUX33_0", + "GTPE2_IMUX30_4", + "GTPE2_IMUX43_8", + "GTPE2_CHANNEL_RXDFEXYDEN", + "GTPE2_IMUX32_3", + "GTPE2_IMUX34_1", + "GTPE2_CLK1_8", + "GTPE2_IMUX5_5", + "GTPE2_IMUX19_3", + "GTPE2_CHANNEL_TXMAINCURSOR1", + "GTPE2_IMUX6_0", + "GTPE2_IMUX41_9", + "GTPE2_LOGIC_OUTS_B17_5", + "GTPE2_IMUX41_3", + "GTPE2_LOGIC_OUTS_B7_6", + "GTPE2_CHANNEL_TXPMARESET", + "GTPE2_FAN1_0", + "GTPE2_LOGIC_OUTS_B17_2", + "GTPE2_CLK0_10", + "GTPE2_LOGIC_OUTS_B1_8", + "GTPE2_FAN7_8", + "GTPE2_CHANNEL_DRPADDR2", + "GTPE2_CHANNEL_DRPCLK", + "GTPE2_IMUX10_0", + "GTPE2_CHANNEL_RXCDROVRDEN", + "GTPE2_BYP0_2", + "GTPE2_LOGIC_OUTS_B15_4", + "GTPE2_IMUX10_7", + "GTPE2_FAN4_10", + "GTPE2_LOGIC_OUTS_B9_9", + "GTPE2_LOGIC_OUTS_B15_2", + "GTPE2_CHANNEL_TXOUTCLKSEL1", + "GTPE2_CHANNEL_TXCHARDISPMODE0", + "GTPE2_IMUX20_10", + "GTPE2_CHANNEL_RXHEADERVALID", + "GTPE2_IMUX15_8", + "GTPE2_CLK0_7", + "GTPE2_CHANNEL_RXOSINTDONE", + "GTPE2_CHANNEL_TXRATE1", + "GTPE2_CHANNEL_TXDATA9", + "GTPE2_LOGIC_OUTS_B17_4", + "GTPE2_IMUX29_1", + "GTPE2_IMUX42_0", + "GTPE2_IMUX39_3", + "GTPE2_IMUX18_3", + "GTPE2_LOGIC_OUTS_B12_1", + "GTPE2_LOGIC_OUTS_B21_6", + "GTPE2_CHANNEL_RXOUTCLK_3", + "GTPE2_IMUX26_3", + "GTPE2_LOGIC_OUTS_B6_5", + "GTPE2_IMUX8_3", + "GTPE2_BYP1_2", + "GTPE2_FAN4_6", + "GTPE2_CHANNEL_TXDATA17", + "GTPE2_IMUX29_9", + "GTPE2_BYP7_6", + "GTPE2_IMUX27_2", + "GTPE2_CHANNEL_RXDLYSRESETDONE", + "GTPE2_CHANNEL_TXPIPPMPD", + "GTPE2_IMUX39_8", + "GTPE2_CHANNEL_TSTIN11", + "GTPE2_IMUX6_4", + "GTPE2_BYP4_8", + "GTPE2_LOGIC_OUTS_B12_8", + "GTPE2_CHANNEL_TXPRECURSOR2", + "GTPE2_IMUX39_10", + "GTPE2_LOGIC_OUTS_B7_0", + "GTPE2_IMUX21_5", + "GTPE2_IMUX5_0", + "GTPE2_LOGIC_OUTS_B5_5", + "GTPE2_IMUX38_0", + "GTPE2_LOGIC_OUTS_B7_1", + "GTPE2_IMUX18_0", + "GTPE2_CHANNEL_RXPMARESET", + "GTPE2_IMUX29_4", + "GTPE2_CHANNEL_PCSRSVDOUT0", + "GTPE2_FAN4_2", + "GTPE2_IMUX11_2", + "GTPE2_CHANNEL_RXBUFSTATUS2", + "GTPE2_CHANNEL_GTRSVD0", + "GTPE2_CHANNEL_TXUSRCLK2", + "GTPE2_IMUX24_1", + "GTPE2_CHANNEL_SCANOUT5", + "GTPE2_IMUX15_2", + "GTPE2_LOGIC_OUTS_B7_4", + "GTPE2_CHANNEL_TSTIN17", + "GTPE2_CHANNEL_DMONITOROUT13", + "GTPE2_CTRL1_8", + "GTPE2_CHANNEL_RXCHBONDI0", + "GTPE2_LOGIC_OUTS_B20_4", + "GTPE2_CHANNEL_RXOSINTEN", + "GTPE2_CHANNEL_TXRATEDONE", + "GTPE2_CHANNEL_TXPOLARITY", + "GTPE2_IMUX20_2", + "GTPE2_LOGIC_OUTS_B9_0", + "GTPE2_CHANNEL_TXCHARDISPVAL1", + "GTPE2_CHANNEL_TSTIN7", + "GTPE2_LOGIC_OUTS_B20_5", + "GTPE2_LOGIC_OUTS_B23_6", + "GTPE2_IMUX12_2", + "GTPE2_CHANNEL_RXOSINTPD", + "GTPE2_LOGIC_OUTS_B2_2", + "GTPE2_FAN4_1", + "GTPE2_BYP5_4", + "GTPE2_IMUX36_2", + "GTPE2_CHANNEL_TXDATA5", + "GTPE2_CHANNEL_RXDATA24", + "GTPE2_IMUX33_4", + "GTPE2_CHANNEL_RXDATA21", + "GTPE2_BYP3_9", + "GTPE2_CHANNEL_TXPIPPMEN", + "GTPE2_IMUX17_8", + "GTPE2_IMUX23_7", + "GTPE2_FAN6_0", + "GTPE2_LOGIC_OUTS_B12_5", + "GTPE2_CLK1_9", + "GTPE2_CHANNEL_TXDATA4", + "GTPE2_BYP7_3", + "GTPE2_CHANNEL_RESETOVRD", + "GTPE2_IMUX2_5", + "GTPE2_IMUX10_1", + "GTPE2_LOGIC_OUTS_B9_5", + "GTPE2_IMUX36_4", + "GTPE2_IMUX46_10", + "GTPE2_CHANNEL_RXCDRHOLD", + "GTPE2_IMUX47_6", + "GTPE2_CTRL0_9", + "GTPE2_IMUX10_5", + "GTPE2_CHANNEL_DRPDO5", + "GTPE2_CHANNEL_RXADAPTSELTEST6", + "GTPE2_CHANNEL_RXBUFSTATUS0", + "GTPE2_CHANNEL_TXN_PAD", + "GTPE2_CHANNEL_TXSYNCALLIN", + "GTPE2_IMUX27_10", + "GTPE2_IMUX42_8", + "GTPE2_CHANNEL_RXDLYTESTENB", + "GTPE2_CHANNEL_TXOUTCLK_3", + "GTPE2_IMUX46_5", + "GTPE2_LOGIC_OUTS_B17_8", + "GTPE2_LOGIC_OUTS_B8_0", + "GTPE2_IMUX27_8", + "GTPE2_BYP7_9", + "GTPE2_CHANNEL_RXDATA7", + "GTPE2_CHANNEL_SETERRSTATUS", + "GTPE2_CHANNEL_TXSYNCOUT", + "GTPE2_FAN1_5", + "GTPE2_IMUX30_2", + "GTPE2_CHANNEL_DMONITOROUT0", + "GTPE2_CHANNEL_GTRSVD12", + "GTPE2_BYP6_5", + "GTPE2_LOGIC_OUTS_B2_4", + "GTPE2_IMUX7_6", + "GTPE2_BYP0_10", + "GTPE2_LOGIC_OUTS_B21_4", + "GTPE2_CHANNEL_TSTIN1", + "GTPE2_IMUX7_1", + "GTPE2_IMUX42_6", + "GTPE2_CHANNEL_TX8B10BBYPASS1", + "GTPE2_FAN3_1", + "GTPE2_LOGIC_OUTS_B9_7", + "GTPE2_CHANNEL_RXDATA18", + "GTPE2_IMUX41_6", + "GTPE2_CHANNEL_TXDLYTESTENB", + "GTPE2_IMUX27_4", + "GTPE2_CHANNEL_GTTXOUTCLK_0", + "GTPE2_IMUX31_8", + "GTPE2_IMUX5_9", + "GTPE2_IMUX12_0", + "GTPE2_IMUX32_7", + "GTPE2_IMUX1_1", + "GTPE2_IMUX25_1", + "GTPE2_CHANNEL_RXCHBONDI3", + "GTPE2_LOGIC_OUTS_B17_10", + "GTPE2_CHANNEL_RXSTATUS2", + "GTPE2_CHANNEL_SCANOUT2", + "GTPE2_LOGIC_OUTS_B9_1", + "GTPE2_LOGIC_OUTS_B11_3", + "GTPE2_IMUX39_1", + "GTPE2_CHANNEL_TXOUTCLK_1", + "GTPE2_IMUX6_2", + "GTPE2_FAN2_3", + "GTPE2_IMUX31_7", + "GTPE2_CHANNEL_RXCHBONDO1", + "GTPE2_CHANNEL_GTRSVD13", + "GTPE2_IMUX18_4", + "GTPE2_IMUX6_5", + "GTPE2_LOGIC_OUTS_B7_3", + "GTPE2_IMUX46_9", + "GTPE2_LOGIC_OUTS_B5_7", + "GTPE2_LOGIC_OUTS_B16_0", + "GTPE2_CHANNEL_DMONITOROUT8", + "GTPE2_CHANNEL_RXADAPTSELTEST11", + "GTPE2_LOGIC_OUTS_B0_8", + "GTPE2_IMUX43_4", + "GTPE2_CHANNEL_DMONITORCLK", + "GTPE2_IMUX35_2", + "GTPE2_LOGIC_OUTS_B22_7", + "GTPE2_IMUX7_4", + "GTPE2_CHANNEL_PLLCLK1", + "GTPE2_CTRL1_4", + "GTPE2_IMUX11_6", + "GTPE2_CHANNEL_CLKRSVD0", + "GTPE2_LOGIC_OUTS_B14_8", + "GTPE2_LOGIC_OUTS_B13_7", + "GTPE2_IMUX45_2", + "GTPE2_CHANNEL_RXCHARISCOMMA1", + "GTPE2_IMUX29_2", + "GTPE2_CHANNEL_PLLREFCLK0", + "GTPE2_IMUX38_6", + "GTPE2_CHANNEL_TXDATA1", + "GTPE2_CHANNEL_RXPHOVRDEN", + "GTPE2_CHANNEL_DMONITOROUT10", + "GTPE2_LOGIC_OUTS_B22_8", + "GTPE2_IMUX21_9", + "GTPE2_FAN4_4", + "GTPE2_CHANNEL_RXOSINTCFG0", + "GTPE2_IMUX1_8", + "GTPE2_IMUX12_8", + "GTPE2_LOGIC_OUTS_B4_3", + "GTPE2_BYP4_9", + "GTPE2_IMUX14_9", + "GTPE2_LOGIC_OUTS_B15_10", + "GTPE2_BYP0_1", + "GTPE2_LOGIC_OUTS_B21_0", + "GTPE2_CHANNEL_RXDATA8", + "GTPE2_IMUX25_6", + "GTPE2_CTRL1_2", + "GTPE2_IMUX40_10", + "GTPE2_CHANNEL_TXOUTCLK_2", + "GTPE2_CHANNEL_TSTPD3", + "GTPE2_IMUX24_7", + "GTPE2_IMUX15_1", + "GTPE2_LOGIC_OUTS_B3_6", + "GTPE2_IMUX35_1", + "GTPE2_CHANNEL_GTRSVD4", + "GTPE2_IMUX4_10", + "GTPE2_CHANNEL_TXDLYEN", + "GTPE2_LOGIC_OUTS_B10_10", + "GTPE2_IMUX9_3", + "GTPE2_CHANNEL_DRPDO2", + "GTPE2_LOGIC_OUTS_B6_3", + "GTPE2_CHANNEL_RXCOMWAKEDET", + "GTPE2_CHANNEL_PMASCANCLK3", + "GTPE2_CHANNEL_RXDATA23", + "GTPE2_CHANNEL_RXADAPTSELTEST0", + "GTPE2_CHANNEL_TXBUFDIFFCTRL0", + "GTPE2_CHANNEL_TXCOMWAKE", + "GTPE2_FAN0_3", + "GTPE2_LOGIC_OUTS_B13_1", + "GTPE2_CHANNEL_SCANIN5", + "GTPE2_LOGIC_OUTS_B4_7", + "GTPE2_CHANNEL_RXSYNCDONE", + "GTPE2_CHANNEL_TXCHARISK0", + "GTPE2_IMUX31_0", + "GTPE2_IMUX34_6", + "GTPE2_BYP3_7", + "GTPE2_IMUX46_7", + "GTPE2_CHANNEL_RXDISPERR0", + "GTPE2_IMUX1_3", + "GTPE2_IMUX0_10", + "GTPE2_IMUX32_8", + "GTPE2_LOGIC_OUTS_B7_8", + "GTPE2_BYP5_8", + "GTPE2_CHANNEL_TXPHALIGN", + "GTPE2_BYP1_4", + "GTPE2_CHANNEL_TSTIN19", + "GTPE2_CHANNEL_PCSRSVDOUT15", + "GTPE2_IMUX18_2", + "GTPE2_IMUX16_5", + "GTPE2_LOGIC_OUTS_B12_10", + "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "GTPE2_BYP6_0", + "GTPE2_LOGIC_OUTS_B17_3", + "GTPE2_IMUX7_2", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", + "GTPE2_IMUX33_8", + "GTPE2_IMUX34_5", + "GTPE2_CHANNEL_RXCHARISK2", + "GTPE2_IMUX25_5", + "GTPE2_IMUX18_5", + "GTPE2_CHANNEL_RXCHBONDSLAVE", + "GTPE2_CHANNEL_TXOUTCLK_0", + "GTPE2_CHANNEL_TXMAINCURSOR3", + "GTPE2_IMUX9_8", + "GTPE2_IMUX21_6", + "GTPE2_LOGIC_OUTS_B21_3", + "GTPE2_IMUX7_9", + "GTPE2_LOGIC_OUTS_B18_6", + "GTPE2_IMUX45_4", + "GTPE2_BYP7_5", + "GTPE2_CHANNEL_TXCHARDISPMODE2", + "GTPE2_CHANNEL_TXBUFDIFFCTRL1", + "GTPE2_IMUX25_2", + "GTPE2_IMUX28_8", + "GTPE2_CHANNEL_RXADAPTSELTEST7", + "GTPE2_CHANNEL_TXDLYHOLD", + "GTPE2_IMUX43_6", + "GTPE2_CHANNEL_TXDATA13", + "GTPE2_LOGIC_OUTS_B15_0", + "GTPE2_CHANNEL_RXMCOMMAALIGNEN", + "GTPE2_LOGIC_OUTS_B18_5", + "GTPE2_CHANNEL_RXOSHOLD", + "GTPE2_LOGIC_OUTS_B11_8", + "GTPE2_IMUX8_8", + "GTPE2_LOGIC_OUTS_B2_10", + "GTPE2_CHANNEL_RXP_PAD", + "GTPE2_IMUX20_3", + "GTPE2_IMUX38_2", + "GTPE2_FAN1_3", + "GTPE2_IMUX4_0", + "GTPE2_CHANNEL_GTTXRESET", + "GTPE2_BYP3_10", + "GTPE2_LOGIC_OUTS_B16_4", + "GTPE2_CHANNEL_PMASCANENB", + "GTPE2_CHANNEL_RXSYNCIN", + "GTPE2_LOGIC_OUTS_B19_8", + "GTPE2_CHANNEL_TXP", + "GTPE2_CHANNEL_RXHEADER2", + "GTPE2_CHANNEL_TXDATA25", + "GTPE2_LOGIC_OUTS_B14_1", + "GTPE2_IMUX13_3", + "GTPE2_IMUX1_4", + "GTPE2_CHANNEL_DRPDO7", + "GTPE2_BYP1_9", + "GTPE2_IMUX47_8", + "GTPE2_LOGIC_OUTS_B1_10", + "GTPE2_BYP4_4", + "GTPE2_CHANNEL_DRPDI5", + "GTPE2_CHANNEL_RXLPMLFHOLD", + "GTPE2_BYP6_2", + "GTPE2_IMUX21_7", + "GTPE2_CHANNEL_TXDLYSRESET", + "GTPE2_IMUX40_3", + "GTPE2_IMUX38_4", + "GTPE2_LOGIC_OUTS_B21_10", + "GTPE2_BYP3_3", + "GTPE2_FAN2_8", + "GTPE2_BYP6_8", + "GTPE2_CHANNEL_TXDATA27", + "GTPE2_FAN4_3", + "GTPE2_CHANNEL_TXPRBSSEL1", + "GTPE2_CHANNEL_PCSRSVDOUT8", + "GTPE2_CHANNEL_TXPD1", + "GTPE2_IMUX24_4", + "GTPE2_CHANNEL_RXRATEDONE", + "GTPE2_CHANNEL_RXPRBSCNTRESET", + "GTPE2_IMUX12_5", + "GTPE2_CHANNEL_RXDATAVALID1", + "GTPE2_CHANNEL_DRPDI13", + "GTPE2_FAN5_2", + "GTPE2_LOGIC_OUTS_B12_7", + "GTPE2_FAN7_3", + "GTPE2_IMUX41_5", + "GTPE2_CHANNEL_TXGEARBOXREADY", + "GTPE2_LOGIC_OUTS_B6_1", + "GTPE2_FAN1_7", + "GTPE2_CHANNEL_TXSYNCIN", + "GTPE2_LOGIC_OUTS_B17_1", + "GTPE2_IMUX9_4", + "GTPE2_CHANNEL_PMASCANIN4", + "GTPE2_CHANNEL_TXRATE2", + "GTPE2_CHANNEL_DRPDO9", + "GTPE2_BYP7_10", + "GTPE2_IMUX8_7", + "GTPE2_CHANNEL_TSTIN9", + "GTPE2_IMUX12_10", + "GTPE2_LOGIC_OUTS_B19_2", + "GTPE2_LOGIC_OUTS_B19_10", + "GTPE2_BYP1_0", + "GTPE2_LOGIC_OUTS_B15_6", + "GTPE2_IMUX26_5", + "GTPE2_IMUX7_7", + "GTPE2_CHANNEL_TXDIFFCTRL1", + "GTPE2_IMUX41_7", + "GTPE2_CHANNEL_PLL1CLK", + "GTPE2_IMUX33_2", + "GTPE2_CHANNEL_TSTPD4", + "GTPE2_CHANNEL_RXDLYSRESET", + "GTPE2_LOGIC_OUTS_B2_8", + "GTPE2_CHANNEL_RXRATE2", + "GTPE2_FAN5_0", + "GTPE2_CHANNEL_RXOUTCLKSEL0", + "GTPE2_CHANNEL_TXPHINITDONE", + "GTPE2_IMUX45_10", + "GTPE2_IMUX1_0", + "GTPE2_CHANNEL_EYESCANDATAERROR", + "GTPE2_CHANNEL_DRPDI7", + "GTPE2_CHANNEL_RXDATA10", + "GTPE2_CHANNEL_SCANMODEB", + "GTPE2_LOGIC_OUTS_B23_3", + "GTPE2_IMUX31_10", + "GTPE2_FAN6_10", + "GTPE2_IMUX35_10", + "GTPE2_CHANNEL_DMONITOROUT12", + "GTPE2_LOGIC_OUTS_B15_1", + "GTPE2_CHANNEL_TXDLYSRESETDONE", + "GTPE2_CHANNEL_RXDLYOVRDEN", + "GTPE2_IMUX47_2", + "GTPE2_IMUX40_0", + "GTPE2_CHANNEL_PCSRSVDIN1", + "GTPE2_IMUX12_4", + "GTPE2_CHANNEL_DMONITOROUT6", + "GTPE2_IMUX6_8", + "GTPE2_CHANNEL_RXOSOVRDEN", + "GTPE2_CHANNEL_TXDIFFPD", + "GTPE2_CHANNEL_RXCHARISCOMMA2", + "GTPE2_LOGIC_OUTS_B2_5", + "GTPE2_CLK0_3", + "GTPE2_LOGIC_OUTS_B14_0", + "GTPE2_IMUX4_5", + "GTPE2_FAN3_7", + "GTPE2_CHANNEL_TSTIN12", + "GTPE2_IMUX21_8", + "GTPE2_CHANNEL_RXELECIDLEMODE1", + "GTPE2_LOGIC_OUTS_B18_3", + "GTPE2_CHANNEL_RXPHMONITOR2", + "GTPE2_IMUX11_10", + "GTPE2_IMUX31_3", + "GTPE2_CLK1_7", + "GTPE2_CLK1_2", + "GTPE2_LOGIC_OUTS_B5_6", + "GTPE2_FAN6_4", + "GTPE2_IMUX11_7", + "GTPE2_BYP7_4", + "GTPE2_IMUX2_8", + "GTPE2_LOGIC_OUTS_B5_4", + "GTPE2_FAN2_0", + "GTPE2_IMUX32_5", + "GTPE2_LOGIC_OUTS_B16_5", + "GTPE2_LOGIC_OUTS_B18_4", + "GTPE2_BYP4_2", + "GTPE2_CHANNEL_TXPHDLYTSTCLK", + "GTPE2_CHANNEL_SCANIN2", + "GTPE2_IMUX37_5", + "GTPE2_BYP7_8", + "GTPE2_IMUX3_10", + "GTPE2_FAN7_9", + "GTPE2_LOGIC_OUTS_B7_2", + "GTPE2_LOGIC_OUTS_B4_9", + "GTPE2_LOGIC_OUTS_B13_5", + "GTPE2_CHANNEL_GTRSVD3", + "GTPE2_IMUX22_0", + "GTPE2_IMUX2_10", + "GTPE2_CHANNEL_GTRXRESET", + "GTPE2_IMUX35_3", + "GTPE2_IMUX14_6", + "GTPE2_IMUX44_1", + "GTPE2_IMUX38_9", + "GTPE2_CHANNEL_RXDATA28", + "GTPE2_CHANNEL_DRPDI1", + "GTPE2_LOGIC_OUTS_B23_0", + "GTPE2_IMUX10_6", + "GTPE2_CHANNEL_TXOUTCLKSEL0", + "GTPE2_IMUX0_8", + "GTPE2_LOGIC_OUTS_B11_10", + "GTPE2_LOGIC_OUTS_B2_3", + "GTPE2_IMUX15_7", + "GTPE2_IMUX36_1", + "GTPE2_CLK0_6", + "GTPE2_CHANNEL_RXNOTINTABLE3", + "GTPE2_CHANNEL_RXCHANISALIGNED", + "GTPE2_IMUX8_1", + "GTPE2_CHANNEL_TSTPD0", + "GTPE2_CHANNEL_TXDATA14", + "GTPE2_CHANNEL_RXN", + "GTPE2_IMUX14_5", + "GTPE2_IMUX44_4", + "GTPE2_IMUX20_7", + "GTPE2_FAN5_3", + "GTPE2_FAN2_9", + "GTPE2_CHANNEL_TSTIN13", + "GTPE2_CHANNEL_LOOPBACK1", + "GTPE2_IMUX43_2", + "GTPE2_BYP5_6", + "GTPE2_CHANNEL_RXDLYBYPASS", + "GTPE2_LOGIC_OUTS_B11_5", + "GTPE2_IMUX4_8", + "GTPE2_LOGIC_OUTS_B22_4", + "GTPE2_LOGIC_OUTS_B14_2", + "GTPE2_CHANNEL_TXHEADER2", + "GTPE2_IMUX6_7", + "GTPE2_CHANNEL_PCSRSVDOUT1", + "GTPE2_IMUX9_10", + "GTPE2_LOGIC_OUTS_B9_2", + "GTPE2_CHANNEL_PMASCANIN3", + "GTPE2_LOGIC_OUTS_B0_2", + "GTPE2_IMUX10_4", + "GTPE2_CHANNEL_PMASCANOUT5", + "GTPE2_LOGIC_OUTS_B4_5", + "GTPE2_IMUX22_5", + "GTPE2_CHANNEL_TXMARGIN1", + "GTPE2_IMUX43_5", + "GTPE2_LOGIC_OUTS_B17_9", + "GTPE2_CHANNEL_RXLPMLFOVRDEN", + "GTPE2_CHANNEL_RXRATE1", + "GTPE2_LOGIC_OUTS_B5_2", + "GTPE2_IMUX1_2", + "GTPE2_CHANNEL_PCSRSVDIN14", + "GTPE2_BYP6_6", + "GTPE2_CHANNEL_SCANENB", + "GTPE2_CHANNEL_PMASCANCLK0", + "GTPE2_IMUX5_6", + "GTPE2_LOGIC_OUTS_B16_10", + "GTPE2_IMUX47_0", + "GTPE2_LOGIC_OUTS_B3_1", + "GTPE2_LOGIC_OUTS_B21_2", + "GTPE2_CHANNEL_RXCHARISK1", + "GTPE2_IMUX36_7", + "GTPE2_CHANNEL_TXDETECTRX", + "GTPE2_IMUX23_3", + "GTPE2_IMUX20_1", + "GTPE2_IMUX30_8", + "GTPE2_CHANNEL_TXDATA29", + "GTPE2_CHANNEL_TXDATA31", + "GTPE2_CHANNEL_RXDATA5", + "GTPE2_FAN6_7", + "GTPE2_LOGIC_OUTS_B1_3", + "GTPE2_CHANNEL_SCANIN3", + "GTPE2_CHANNEL_RXADAPTSELTEST3", + "GTPE2_CHANNEL_TXRUNDISP2", + "GTPE2_CHANNEL_RXSYSCLKSEL1", + "GTPE2_CHANNEL_RXOSINTID03", + "GTPE2_CHANNEL_TXBUFSTATUS0", + "GTPE2_BYP6_7", + "GTPE2_CHANNEL_RXCHBONDMASTER", + "GTPE2_IMUX35_8", + "GTPE2_IMUX17_5", + "GTPE2_LOGIC_OUTS_B5_8", + "GTPE2_IMUX10_2", + "GTPE2_CHANNEL_TXPOSTCURSORINV", + "GTPE2_IMUX47_4", + "GTPE2_IMUX42_2", + "GTPE2_IMUX47_10", + "GTPE2_LOGIC_OUTS_B23_1", + "GTPE2_IMUX15_4", + "GTPE2_FAN4_9", + "GTPE2_CHANNEL_RXPRBSSEL2", + "GTPE2_LOGIC_OUTS_B14_10", + "GTPE2_IMUX35_9", + "GTPE2_CHANNEL_RXBUFRESET", + "GTPE2_CHANNEL_TXDATA22", + "GTPE2_CHANNEL_PMASCANOUT2", + "GTPE2_LOGIC_OUTS_B4_1", + "GTPE2_IMUX28_6", + "GTPE2_IMUX16_7", + "GTPE2_CHANNEL_DMONITOROUT3", + "GTPE2_LOGIC_OUTS_B20_7", + "GTPE2_LOGIC_OUTS_B12_3", + "GTPE2_LOGIC_OUTS_B23_9", + "GTPE2_IMUX28_4", + "GTPE2_CHANNEL_TXRATE0", + "GTPE2_CHANNEL_DRPDO8", + "GTPE2_CHANNEL_TXDEEMPH", + "GTPE2_LOGIC_OUTS_B2_1", + "GTPE2_LOGIC_OUTS_B1_2", + "GTPE2_LOGIC_OUTS_B16_8", + "GTPE2_CHANNEL_PCSRSVDIN6", + "GTPE2_IMUX0_5", + "GTPE2_CHANNEL_SCANCLK", + "GTPE2_CHANNEL_RXADAPTSELTEST10", + "GTPE2_CHANNEL_TSTIN5", + "GTPE2_IMUX38_3", + "GTPE2_FAN0_0", + "GTPE2_IMUX7_5", + "GTPE2_IMUX45_8", + "GTPE2_IMUX17_7", + "GTPE2_CHANNEL_TSTIN6", + "GTPE2_IMUX39_5", + "GTPE2_CHANNEL_RXPHMONITOR0", + "GTPE2_FAN2_4", + "GTPE2_LOGIC_OUTS_B11_7", + "GTPE2_CHANNEL_TXN", + "GTPE2_CHANNEL_CFGRESET", + "GTPE2_CHANNEL_TXPOSTCURSOR3", + "GTPE2_CHANNEL_RXADAPTSELTEST9", + "GTPE2_CHANNEL_TXPRECURSORINV", + "GTPE2_CHANNEL_DRPADDR1", + "GTPE2_CHANNEL_TXDATA18", + "GTPE2_FAN1_8", + "GTPE2_LOGIC_OUTS_B10_7", + "GTPE2_BYP1_7", + "GTPE2_BYP7_1", + "GTPE2_LOGIC_OUTS_B11_2", + "GTPE2_IMUX17_9", + "GTPE2_CHANNEL_RXCHBONDLEVEL2", + "GTPE2_BYP3_2", + "GTPE2_IMUX45_0", + "GTPE2_CHANNEL_TXPMARESETDONE", + "GTPE2_IMUX14_0", + "GTPE2_CHANNEL_PCSRSVDOUT3", + "GTPE2_CHANNEL_TXINHIBIT", + "GTPE2_LOGIC_OUTS_B14_5", + "GTPE2_IMUX19_2", + "GTPE2_CHANNEL_DRPDI3", + "GTPE2_IMUX28_2", + "GTPE2_IMUX18_6", + "GTPE2_CHANNEL_DRPADDR4", + "GTPE2_CHANNEL_TXPRECURSOR4", + "GTPE2_IMUX34_0", + "GTPE2_IMUX40_4", + "GTPE2_CHANNEL_TXPHALIGNDONE", + "GTPE2_LOGIC_OUTS_B3_3", + "GTPE2_LOGIC_OUTS_B23_2", + "GTPE2_FAN5_4", + "GTPE2_LOGIC_OUTS_B22_1", + "GTPE2_IMUX39_7", + "GTPE2_FAN6_6", + "GTPE2_IMUX13_9", + "GTPE2_CHANNEL_TXSYSCLKSEL0", + "GTPE2_CHANNEL_RXPHDLYRESET", + "GTPE2_LOGIC_OUTS_B19_1", + "GTPE2_CHANNEL_TXCHARDISPVAL3", + "GTPE2_IMUX37_9", + "GTPE2_IMUX13_6", + "GTPE2_FAN0_6", + "GTPE2_LOGIC_OUTS_B0_5", + "GTPE2_CHANNEL_TXPD0", + "GTPE2_CHANNEL_PCSRSVDIN15", + "GTPE2_IMUX47_3", + "GTPE2_CHANNEL_DRPEN", + "GTPE2_BYP4_1", + "GTPE2_IMUX3_9", + "GTPE2_BYP0_7", + "GTPE2_IMUX28_9", + "GTPE2_IMUX16_1", + "GTPE2_CHANNEL_RXDATA13", + "GTPE2_CHANNEL_PHYSTATUS", + "GTPE2_IMUX31_2", + "GTPE2_CHANNEL_TXDIFFCTRL3", + "GTPE2_IMUX8_6", + "GTPE2_LOGIC_OUTS_B3_0", + "GTPE2_IMUX28_7", + "GTPE2_IMUX8_0", + "GTPE2_FAN0_7", + "GTPE2_LOGIC_OUTS_B13_8", + "GTPE2_CHANNEL_TXMAINCURSOR6", + "GTPE2_CHANNEL_DRPWE", + "GTPE2_LOGIC_OUTS_B2_7", + "GTPE2_IMUX33_1", + "GTPE2_IMUX3_8", + "GTPE2_IMUX11_0", + "GTPE2_LOGIC_OUTS_B3_7", + "GTPE2_CLK0_8", + "GTPE2_IMUX36_5", + "GTPE2_IMUX11_5", + "GTPE2_CHANNEL_TXDATA23", + "GTPE2_IMUX19_4", + "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", + "GTPE2_IMUX23_10", + "GTPE2_CHANNEL_RXOUTCLK_1", + "GTPE2_IMUX40_5", + "GTPE2_FAN1_9", + "GTPE2_CHANNEL_RXADAPTSELTEST13", + "GTPE2_CHANNEL_RXN_PAD", + "GTPE2_CHANNEL_RXVALID", + "GTPE2_CHANNEL_TXDLYBYPASS", + "GTPE2_IMUX44_9", + "GTPE2_CHANNEL_TXOUTCLKPCS", + "GTPE2_CHANNEL_PMASCANOUT3", + "GTPE2_CHANNEL_DRPADDR7", + "GTPE2_CHANNEL_RXDATA16", + "GTPE2_IMUX39_9", + "GTPE2_LOGIC_OUTS_B10_3", + "GTPE2_IMUX21_0", + "GTPE2_BYP1_5", + "GTPE2_IMUX3_3", + "GTPE2_LOGIC_OUTS_B3_9", + "GTPE2_IMUX32_0", + "GTPE2_CHANNEL_TXPRBSSEL0", + "GTPE2_IMUX26_6", + "GTPE2_CHANNEL_RXPCOMMAALIGNEN", + "GTPE2_IMUX13_10", + "GTPE2_CHANNEL_RXPHALIGNDONE", + "GTPE2_LOGIC_OUTS_B9_6", + "GTPE2_LOGIC_OUTS_B17_0", + "GTPE2_CHANNEL_RXDATA22", + "GTPE2_CHANNEL_RXOUTCLK_0", + "GTPE2_IMUX13_4", + "GTPE2_CHANNEL_GTRSVD1", + "GTPE2_CHANNEL_RXDATA12", + "GTPE2_CHANNEL_SCANOUT3", + "GTPE2_CHANNEL_RXCDRRESET", + "GTPE2_IMUX1_6", + "GTPE2_CHANNEL_TXPRECURSOR3", + "GTPE2_CHANNEL_DRPDI9", + "GTPE2_LOGIC_OUTS_B9_8", + "GTPE2_FAN6_1", + "GTPE2_IMUX19_7", + "GTPE2_CHANNEL_TXCHARDISPMODE3", + "GTPE2_CHANNEL_PMASCANOUT1", + "GTPE2_IMUX37_10", + "GTPE2_CTRL1_3", + "GTPE2_LOGIC_OUTS_B16_2", + "GTPE2_IMUX45_5", + "GTPE2_CHANNEL_PCSRSVDIN12", + "GTPE2_IMUX19_5", + "GTPE2_CHANNEL_RXADAPTSELTEST12", + "GTPE2_IMUX13_0", + "GTPE2_CTRL0_7", + "GTPE2_LOGIC_OUTS_B18_10", + "GTPE2_IMUX0_3", + "GTPE2_IMUX34_3", + "GTPE2_CHANNEL_RXOSINTOVRDEN", + "GTPE2_CHANNEL_TXSEQUENCE5", + "GTPE2_LOGIC_OUTS_B22_3", + "GTPE2_CHANNEL_RXLPMHFOVRDEN", + "GTPE2_CHANNEL_TXDATA6", + "GTPE2_IMUX19_0", + "GTPE2_CHANNEL_RXDATA20", + "GTPE2_CHANNEL_SCANOUT0", + "GTPE2_CHANNEL_TXPOSTCURSOR4", + "GTPE2_CHANNEL_TXPOSTCURSOR1", + "GTPE2_LOGIC_OUTS_B23_4", + "GTPE2_CHANNEL_SCANIN1", + "GTPE2_FAN7_1", + "GTPE2_IMUX2_9", + "GTPE2_CHANNEL_RXPHALIGNEN", + "GTPE2_FAN2_1", + "GTPE2_CHANNEL_TXPHDLYRESET", + "GTPE2_CHANNEL_RXPD1", + "GTPE2_CHANNEL_RXPRBSERR", + "GTPE2_CHANNEL_PMARSVDOUT0", + "GTPE2_IMUX25_8", + "GTPE2_IMUX23_0", + "GTPE2_IMUX15_9", + "GTPE2_FAN5_5", + "GTPE2_CHANNEL_PMASCANRSTEN", + "GTPE2_CHANNEL_RXCHARISK0", + "GTPE2_LOGIC_OUTS_B21_9", + "GTPE2_IMUX7_8", + "GTPE2_IMUX14_8", + "GTPE2_FAN5_7", + "GTPE2_CHANNEL_TSTPD2", + "GTPE2_LOGIC_OUTS_B8_7", + "GTPE2_LOGIC_OUTS_B22_2", + "GTPE2_IMUX32_10", + "GTPE2_CHANNEL_TXPOSTCURSOR2", + "GTPE2_CHANNEL_DRPDO14", + "GTPE2_IMUX21_2", + "GTPE2_CLK1_3", + "GTPE2_CHANNEL_RXCOMMADETEN", + "GTPE2_IMUX16_2", + "GTPE2_CHANNEL_TXPRECURSOR1", + "GTPE2_IMUX32_6", + "GTPE2_IMUX3_6", + "GTPE2_CTRL1_7", + "GTPE2_CHANNEL_RXPHDLYPD", + "GTPE2_BYP2_7", + "GTPE2_CHANNEL_DMONITOROUT5", + "GTPE2_CTRL0_8", + "GTPE2_LOGIC_OUTS_B14_9", + "GTPE2_CHANNEL_TXRUNDISP0", + "GTPE2_IMUX3_4", + "GTPE2_IMUX18_10", + "GTPE2_CHANNEL_PCSRSVDIN10", + "GTPE2_IMUX20_5", + "GTPE2_IMUX29_6", + "GTPE2_IMUX42_9", + "GTPE2_IMUX28_5", + "GTPE2_LOGIC_OUTS_B11_6", + "GTPE2_CHANNEL_RXDATA30", + "GTPE2_LOGIC_OUTS_B1_6", + "GTPE2_IMUX2_2", + "GTPE2_CHANNEL_PMARSVDIN0", + "GTPE2_FAN6_3", + "GTPE2_CHANNEL_PMASCANIN6", + "GTPE2_FAN0_5", + "GTPE2_CHANNEL_TXCHARISK1", + "GTPE2_FAN4_8", + "GTPE2_BYP2_1", + "GTPE2_LOGIC_OUTS_B13_9", + "GTPE2_CHANNEL_RXCHARISCOMMA0", + "GTPE2_IMUX37_1", + "GTPE2_CHANNEL_RXSTATUS0", + "GTPE2_IMUX14_10", + "GTPE2_IMUX33_3", + "GTPE2_IMUX37_2", + "GTPE2_FAN1_6", + "GTPE2_CHANNEL_RXDATAVALID0", + "GTPE2_CHANNEL_PCSRSVDOUT9", + "GTPE2_IMUX19_9", + "GTPE2_IMUX47_1", + "GTPE2_IMUX47_7", + "GTPE2_CHANNEL_TXUSERRDY", + "GTPE2_LOGIC_OUTS_B7_5", + "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "GTPE2_CHANNEL_RXDATA31", + "GTPE2_CHANNEL_RXDISPERR2", + "GTPE2_CHANNEL_PCSRSVDOUT13", + "GTPE2_CHANNEL_DMONITOROUT14", + "GTPE2_CHANNEL_DRPDO11", + "GTPE2_CHANNEL_DRPDO4", + "GTPE2_LOGIC_OUTS_B10_9", + "GTPE2_IMUX17_4", + "GTPE2_LOGIC_OUTS_B14_6", + "GTPE2_CHANNEL_TXELECIDLE", + "GTPE2_FAN3_6", + "GTPE2_CHANNEL_TXDATA20", + "GTPE2_CHANNEL_DMONITOROUT7", + "GTPE2_IMUX17_3", + "GTPE2_LOGIC_OUTS_B8_1", + "GTPE2_LOGIC_OUTS_B5_1", + "GTPE2_CHANNEL_PMASCANOUT0", + "GTPE2_IMUX15_3", + "GTPE2_CHANNEL_TXMAINCURSOR5", + "GTPE2_IMUX43_7", + "GTPE2_BYP0_0", + "GTPE2_CHANNEL_PMARSVDIN2", + "GTPE2_IMUX0_6", + "GTPE2_CHANNEL_GTRESETSEL", + "GTPE2_IMUX20_9", + "GTPE2_CHANNEL_TSTIN10", + "GTPE2_CHANNEL_TXDATA28", + "GTPE2_CHANNEL_DRPDI6", + "GTPE2_CHANNEL_RXCHBONDO0", + "GTPE2_IMUX40_7", + "GTPE2_BYP5_7", + "GTPE2_CHANNEL_DRPADDR8", + "GTPE2_CHANNEL_TXDATA21", + "GTPE2_IMUX42_1", + "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "GTPE2_LOGIC_OUTS_B19_3", + "GTPE2_LOGIC_OUTS_B3_10", + "GTPE2_BYP3_5", + "GTPE2_IMUX43_0", + "GTPE2_CHANNEL_TXRESETDONE", + "GTPE2_CHANNEL_PMARSVDOUT1", + "GTPE2_IMUX13_1", + "GTPE2_CHANNEL_TSTIN4", + "GTPE2_BYP2_4", + "GTPE2_CHANNEL_RXADAPTSELTEST1", + "GTPE2_FAN2_2", + "GTPE2_IMUX13_2", + "GTPE2_CHANNEL_TXRUNDISP3", + "GTPE2_CHANNEL_TSTIN8", + "GTPE2_CHANNEL_RXDATA11", + "GTPE2_IMUX40_1", + "GTPE2_FAN7_6", + "GTPE2_LOGIC_OUTS_B0_4", + "GTPE2_CHANNEL_RXOSINTSTARTED", + "GTPE2_CHANNEL_TSTCLK0", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", + "GTPE2_IMUX1_10", + "GTPE2_IMUX5_10", + "GTPE2_CHANNEL_TXDATA30", + "GTPE2_IMUX43_3", + "GTPE2_LOGIC_OUTS_B0_0", + "GTPE2_IMUX46_8", + "GTPE2_IMUX10_8", + "GTPE2_CHANNEL_TXSWING", + "GTPE2_IMUX37_4", + "GTPE2_CHANNEL_TXDATA10", + "GTPE2_CHANNEL_SCANOUT4", + "GTPE2_IMUX6_3", + "GTPE2_BYP2_5", + "GTPE2_CHANNEL_RXNOTINTABLE0", + "GTPE2_IMUX6_9", + "GTPE2_IMUX40_8", + "GTPE2_IMUX0_1", + "GTPE2_IMUX4_6", + "GTPE2_CHANNEL_RXOSINTSTROBE", + "GTPE2_LOGIC_OUTS_B8_8", + "GTPE2_IMUX12_9", + "GTPE2_IMUX22_2", + "GTPE2_IMUX32_2", + "GTPE2_CHANNEL_RXCOMINITDET", + "GTPE2_LOGIC_OUTS_B14_4", + "GTPE2_CHANNEL_TXDLYUPDOWN", + "GTPE2_CHANNEL_DRPADDR3", + "GTPE2_CHANNEL_TXDATA7", + "GTPE2_CHANNEL_RXOUTCLKPCS", + "GTPE2_CHANNEL_RXADAPTSELTEST2", + "GTPE2_CHANNEL_RXDATA1", + "GTPE2_CHANNEL_DRPRDY", + "GTPE2_FAN3_8", + "GTPE2_CHANNEL_TXOUTCLKSEL2", + "GTPE2_IMUX12_1", + "GTPE2_CTRL0_4", + "GTPE2_IMUX23_8", + "GTPE2_CHANNEL_RXCDRFREQRESET", + "GTPE2_CHANNEL_PMASCANCLK2", + "GTPE2_IMUX32_1", + "GTPE2_CHANNEL_RXCHBONDLEVEL0", + "GTPE2_CHANNEL_TX8B10BBYPASS2", + "GTPE2_BYP5_9", + "GTPE2_CHANNEL_TXBUFDIFFCTRL2", + "GTPE2_CHANNEL_SCANOUT1", + "GTPE2_CHANNEL_RXOUTCLKSEL1", + "GTPE2_CHANNEL_TXDATA3", + "GTPE2_IMUX16_10", + "GTPE2_CHANNEL_RXCHBONDO2", + "GTPE2_FAN3_0", + "GTPE2_IMUX22_9", + "GTPE2_IMUX15_0", + "GTPE2_CHANNEL_GTRSVD11", + "GTPE2_LOGIC_OUTS_B13_4", + "GTPE2_IMUX43_10", + "GTPE2_CHANNEL_TXBUFSTATUS1", + "GTPE2_CHANNEL_RXBYTEREALIGN", + "GTPE2_CHANNEL_PCSRSVDIN11", + "GTPE2_CHANNEL_PCSRSVDOUT7", + "GTPE2_CHANNEL_GTRSVD15", + "GTPE2_CLK0_0", + "GTPE2_IMUX10_3", + "GTPE2_IMUX31_5", + "GTPE2_IMUX37_3", + "GTPE2_LOGIC_OUTS_B4_4", + "GTPE2_IMUX38_10", + "GTPE2_CHANNEL_PCSRSVDIN0", + "GTPE2_CHANNEL_TXSYSCLKSEL1", + "GTPE2_CHANNEL_PCSRSVDIN7", + "GTPE2_CHANNEL_DRPDI11", + "GTPE2_IMUX4_3", + "GTPE2_LOGIC_OUTS_B19_9", + "GTPE2_CHANNEL_RXPHALIGN", + "GTPE2_IMUX29_8", + "GTPE2_LOGIC_OUTS_B12_0", + "GTPE2_IMUX9_2", + "GTPE2_CHANNEL_PCSRSVDIN13", + "GTPE2_CHANNEL_RXUSRCLK", + "GTPE2_BYP5_5", + "GTPE2_LOGIC_OUTS_B4_2", + "GTPE2_CHANNEL_RXPRBSSEL0", + "GTPE2_CTRL0_0", + "GTPE2_FAN2_5", + "GTPE2_IMUX46_1", + "GTPE2_LOGIC_OUTS_B7_9", + "GTPE2_LOGIC_OUTS_B4_8", + "GTPE2_CHANNEL_RXCHANBONDSEQ", + "GTPE2_IMUX26_9", + "GTPE2_IMUX35_4", + "GTPE2_CHANNEL_TXPIPPMOVRDEN", + "GTPE2_IMUX27_9", + "GTPE2_IMUX30_10", + "GTPE2_LOGIC_OUTS_B17_6", + "GTPE2_CHANNEL_RXDATA27", + "GTPE2_IMUX12_6", + "GTPE2_IMUX41_0", + "GTPE2_IMUX12_7", + "GTPE2_CHANNEL_RXOOBRESET", + "GTPE2_CHANNEL_TX8B10BEN", + "GTPE2_LOGIC_OUTS_B3_2", + "GTPE2_IMUX5_3", + "GTPE2_CHANNEL_RXADAPTSELTEST4", + "GTPE2_CHANNEL_PMASCANOUT6", + "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "GTPE2_BYP4_10", + "GTPE2_CHANNEL_RXDATA29", + "GTPE2_IMUX5_1", + "GTPE2_IMUX14_7", + "GTPE2_CHANNEL_RXCHARISCOMMA3", + "GTPE2_BYP2_2", + "GTPE2_LOGIC_OUTS_B1_7", + "GTPE2_CHANNEL_GTRSVD8", + "GTPE2_CHANNEL_RXPCSRESET", + "GTPE2_CHANNEL_DMONITOROUT4", + "GTPE2_IMUX47_5", + "GTPE2_IMUX29_3", + "GTPE2_IMUX30_5", + "GTPE2_CTRL1_9", + "GTPE2_CTRL0_10", + "GTPE2_LOGIC_OUTS_B13_6", + "GTPE2_LOGIC_OUTS_B16_3", + "GTPE2_BYP6_10", + "GTPE2_CHANNEL_PCSRSVDIN4", + "GTPE2_IMUX20_6", + "GTPE2_IMUX21_4", + "GTPE2_CHANNEL_PCSRSVDIN3", + "GTPE2_IMUX33_6", + "GTPE2_CHANNEL_EYESCANRESET", + "GTPE2_IMUX41_8", + "GTPE2_IMUX3_1", + "GTPE2_IMUX26_7", + "GTPE2_BYP3_1", + "GTPE2_CLK0_9", + "GTPE2_BYP2_6", + "GTPE2_CHANNEL_RXPHMONITOR1", + "GTPE2_IMUX21_3", + "GTPE2_IMUX27_0", + "GTPE2_IMUX11_1", + "GTPE2_CHANNEL_DRPDO10", + "GTPE2_CHANNEL_RXHEADER0", + "GTPE2_CHANNEL_TSTIN15", + "GTPE2_LOGIC_OUTS_B11_1", + "GTPE2_LOGIC_OUTS_B16_7", + "GTPE2_IMUX6_10", + "GTPE2_CHANNEL_DRPDO12", + "GTPE2_IMUX36_0", + "GTPE2_IMUX47_9", + "GTPE2_LOGIC_OUTS_B6_0", + "GTPE2_CHANNEL_PLL0REFCLK", + "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "GTPE2_CHANNEL_RXDATA6", + "GTPE2_IMUX19_8", + "GTPE2_CHANNEL_RXSTATUS1", + "GTPE2_CHANNEL_RXPMARESETDONE", + "GTPE2_CHANNEL_TXDIFFCTRL2", + "GTPE2_LOGIC_OUTS_B16_6", + "GTPE2_CHANNEL_DRPDO1", + "GTPE2_CHANNEL_RXDLYEN", + "GTPE2_CLK0_2", + "GTPE2_IMUX17_10", + "GTPE2_CHANNEL_TXCHARDISPMODE1", + "GTPE2_CHANNEL_RXDATA15", + "GTPE2_CHANNEL_DRPDI15", + "GTPE2_IMUX15_6", + "GTPE2_IMUX14_4", + "GTPE2_FAN1_4", + "GTPE2_LOGIC_OUTS_B22_0", + "GTPE2_LOGIC_OUTS_B10_2", + "GTPE2_CHANNEL_RXCHANREALIGN", + "GTPE2_CHANNEL_LOOPBACK2", + "GTPE2_IMUX34_4", + "GTPE2_FAN5_10", + "GTPE2_IMUX2_0", + "GTPE2_LOGIC_OUTS_B8_10", + "GTPE2_IMUX7_10", + "GTPE2_CHANNEL_DRPDI4", + "GTPE2_CHANNEL_RXDEBUGPULSE", + "GTPE2_LOGIC_OUTS_B12_6", + "GTPE2_CHANNEL_PMASCANIN5", + "GTPE2_FAN7_5", + "GTPE2_CHANNEL_PMASCANCLK1", + "GTPE2_IMUX43_9", + "GTPE2_LOGIC_OUTS_B12_2", + "GTPE2_LOGIC_OUTS_B20_2", + "GTPE2_IMUX4_4", + "GTPE2_IMUX45_3", + "GTPE2_IMUX30_1", + "GTPE2_LOGIC_OUTS_B8_3", + "GTPE2_FAN5_1", + "GTPE2_CHANNEL_TXMAINCURSOR0", + "GTPE2_IMUX35_0", + "GTPE2_IMUX28_3", + "GTPE2_CHANNEL_RXCHBONDLEVEL1", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", + "GTPE2_CHANNEL_TXPRECURSOR0", + "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "GTPE2_CHANNEL_TXPRBSSEL2", + "GTPE2_LOGIC_OUTS_B15_3", + "GTPE2_IMUX4_9", + "GTPE2_IMUX39_2", + "GTPE2_CHANNEL_TXPHDLYPD", + "GTPE2_CHANNEL_TXCHARISK2", + "GTPE2_CHANNEL_PCSRSVDOUT14", + "GTPE2_IMUX17_1", + "GTPE2_LOGIC_OUTS_B23_7", + "GTPE2_LOGIC_OUTS_B11_4", + "GTPE2_IMUX18_9", + "GTPE2_CHANNEL_RX8B10BEN", + "GTPE2_CHANNEL_TXDATA16", + "GTPE2_IMUX32_9", + "GTPE2_IMUX5_4", + "GTPE2_CHANNEL_TXMARGIN0", + "GTPE2_CHANNEL_TXCHARDISPVAL0", + "GTPE2_IMUX16_6", + "GTPE2_IMUX41_1", + "GTPE2_FAN5_9", + "GTPE2_LOGIC_OUTS_B0_9", + "GTPE2_IMUX23_1", + "GTPE2_CHANNEL_DRPDI2", + "GTPE2_IMUX24_5" + ], + "tile_type": "GTP_CHANNEL_0", + "sites": [ + { + "site_pins": { + "TSTIN11": "GTPE2_CHANNEL_TSTIN11", + "TXCOMSAS": "GTPE2_CHANNEL_TXCOMSAS", + "RXPHDLYPD": "GTPE2_CHANNEL_RXPHDLYPD", + "TXSEQUENCE2": "GTPE2_CHANNEL_TXSEQUENCE2", + "TXCHARISK3": "GTPE2_CHANNEL_TXCHARISK3", + "TSTIN4": "GTPE2_CHANNEL_TSTIN4", + "PMASCANOUT1": "GTPE2_CHANNEL_PMASCANOUT1", + "TXDATA26": "GTPE2_CHANNEL_TXDATA26", + "GTRSVD12": "GTPE2_CHANNEL_GTRSVD12", + "TXDATA29": "GTPE2_CHANNEL_TXDATA29", + "PCSRSVDOUT13": "GTPE2_CHANNEL_PCSRSVDOUT13", + "DRPDI4": "GTPE2_CHANNEL_DRPDI4", + "RXNOTINTABLE3": "GTPE2_CHANNEL_RXNOTINTABLE3", + "RXADAPTSELTEST7": "GTPE2_CHANNEL_RXADAPTSELTEST7", + "PMARSVDIN3": "GTPE2_CHANNEL_PMARSVDIN3", + "TXCHARDISPMODE0": "GTPE2_CHANNEL_TXCHARDISPMODE0", + "PMASCANCLK2": "GTPE2_CHANNEL_PMASCANCLK2", + "DRPDI13": "GTPE2_CHANNEL_DRPDI13", + "RXADAPTSELTEST3": "GTPE2_CHANNEL_RXADAPTSELTEST3", + "RXCHARISK2": "GTPE2_CHANNEL_RXCHARISK2", + "RXCOMINITDET": "GTPE2_CHANNEL_RXCOMINITDET", + "TXMAINCURSOR1": "GTPE2_CHANNEL_TXMAINCURSOR1", + "RXUSRCLK": "GTPE2_CHANNEL_RXUSRCLK", + "PMASCANIN0": "GTPE2_CHANNEL_PMASCANIN0", + "RXCLKCORCNT0": "GTPE2_CHANNEL_RXCLKCORCNT0", + "RXDATA16": "GTPE2_CHANNEL_RXDATA16", + "CFGRESET": "GTPE2_CHANNEL_CFGRESET", + "TSTIN1": "GTPE2_CHANNEL_TSTIN1", + "TXPIPPMOVRDEN": "GTPE2_CHANNEL_TXPIPPMOVRDEN", + "TXPHINIT": "GTPE2_CHANNEL_TXPHINIT", + "EYESCANMODE": "GTPE2_CHANNEL_EYESCANMODE", + "TSTCLK1": "GTPE2_CHANNEL_TSTCLK1", + "RXBUFSTATUS1": "GTPE2_CHANNEL_RXBUFSTATUS1", + "TXPRBSSEL1": "GTPE2_CHANNEL_TXPRBSSEL1", + "LOOPBACK1": "GTPE2_CHANNEL_LOOPBACK1", + "TXMARGIN2": "GTPE2_CHANNEL_TXMARGIN2", + "TSTIN12": "GTPE2_CHANNEL_TSTIN12", + "TSTPD3": "GTPE2_CHANNEL_TSTPD3", + "GTRSVD15": "GTPE2_CHANNEL_GTRSVD15", + "TXDLYEN": "GTPE2_CHANNEL_TXDLYEN", + "TXBUFDIFFCTRL0": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", + "TXRUNDISP3": "GTPE2_CHANNEL_TXRUNDISP3", + "GTRSVD2": "GTPE2_CHANNEL_GTRSVD2", + "PCSRSVDIN9": "GTPE2_CHANNEL_PCSRSVDIN9", + "RXVALID": "GTPE2_CHANNEL_RXVALID", + "TXOUTCLKSEL1": "GTPE2_CHANNEL_TXOUTCLKSEL1", + "RXPCOMMAALIGNEN": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", + "RXDATA15": "GTPE2_CHANNEL_RXDATA15", + "TXELECIDLE": "GTPE2_CHANNEL_TXELECIDLE", + "TXDIFFCTRL3": "GTPE2_CHANNEL_TXDIFFCTRL3", + "PCSRSVDIN6": "GTPE2_CHANNEL_PCSRSVDIN6", + "RXCOMMADETEN": "GTPE2_CHANNEL_RXCOMMADETEN", + "TXSYSCLKSEL1": "GTPE2_CHANNEL_TXSYSCLKSEL1", + "DRPDO5": "GTPE2_CHANNEL_DRPDO5", + "TXDATA6": "GTPE2_CHANNEL_TXDATA6", + "GTRSVD0": "GTPE2_CHANNEL_GTRSVD0", + "GTRSVD8": "GTPE2_CHANNEL_GTRSVD8", + "TXUSRCLK2": "GTPE2_CHANNEL_TXUSRCLK2", + "TXRATE0": "GTPE2_CHANNEL_TXRATE0", + "TSTCLK0": "GTPE2_CHANNEL_TSTCLK0", + "PMASCANRSTEN": "GTPE2_CHANNEL_PMASCANRSTEN", + "TXDATA21": "GTPE2_CHANNEL_TXDATA21", + "RXCDROVRDEN": "GTPE2_CHANNEL_RXCDROVRDEN", + "TXDATA3": "GTPE2_CHANNEL_TXDATA3", + "RXNOTINTABLE0": "GTPE2_CHANNEL_RXNOTINTABLE0", + "TXPOSTCURSOR3": "GTPE2_CHANNEL_TXPOSTCURSOR3", + "RXSYNCOUT": "GTPE2_CHANNEL_RXSYNCOUT", + "RXCHBONDI3": "GTPE2_CHANNEL_RXCHBONDI3", + "RXCHANBONDSEQ": "GTPE2_CHANNEL_RXCHANBONDSEQ", + "TSTIN7": "GTPE2_CHANNEL_TSTIN7", + "RXPOLARITY": "GTPE2_CHANNEL_RXPOLARITY", + "TXMAINCURSOR3": "GTPE2_CHANNEL_TXMAINCURSOR3", + "DRPDI9": "GTPE2_CHANNEL_DRPDI9", + "RXHEADERVALID": "GTPE2_CHANNEL_RXHEADERVALID", + "PMARSVDOUT1": "GTPE2_CHANNEL_PMARSVDOUT1", + "DMONITOROUT13": "GTPE2_CHANNEL_DMONITOROUT13", + "RXSLIDE": "GTPE2_CHANNEL_RXSLIDE", + "LOOPBACK2": "GTPE2_CHANNEL_LOOPBACK2", + "PCSRSVDIN8": "GTPE2_CHANNEL_PCSRSVDIN8", + "RXCOMWAKEDET": "GTPE2_CHANNEL_RXCOMWAKEDET", + "RX8B10BEN": "GTPE2_CHANNEL_RX8B10BEN", + "RXOSINTCFG0": "GTPE2_CHANNEL_RXOSINTCFG0", + "TXMARGIN0": "GTPE2_CHANNEL_TXMARGIN0", + "PCSRSVDOUT2": "GTPE2_CHANNEL_PCSRSVDOUT2", + "TXPIPPMSTEPSIZE4": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", + "TXPIPPMPD": "GTPE2_CHANNEL_TXPIPPMPD", + "TXPD0": "GTPE2_CHANNEL_TXPD0", + "RXADAPTSELTEST0": "GTPE2_CHANNEL_RXADAPTSELTEST0", + "TXSYSCLKSEL0": "GTPE2_CHANNEL_TXSYSCLKSEL0", + "RXCHBONDO0": "GTPE2_CHANNEL_RXCHBONDO0", + "TXHEADER2": "GTPE2_CHANNEL_TXHEADER2", + "PCSRSVDOUT14": "GTPE2_CHANNEL_PCSRSVDOUT14", + "TXRATE2": "GTPE2_CHANNEL_TXRATE2", + "SCANOUT1": "GTPE2_CHANNEL_SCANOUT1", + "PCSRSVDIN12": "GTPE2_CHANNEL_PCSRSVDIN12", + "GTRSVD6": "GTPE2_CHANNEL_GTRSVD6", + "TXPD1": "GTPE2_CHANNEL_TXPD1", + "TXDLYHOLD": "GTPE2_CHANNEL_TXDLYHOLD", + "CLKRSVD1": "GTPE2_CHANNEL_CLKRSVD1", + "TXPHALIGNEN": "GTPE2_CHANNEL_TXPHALIGNEN", + "TXPHDLYPD": "GTPE2_CHANNEL_TXPHDLYPD", + "TXCHARDISPMODE3": "GTPE2_CHANNEL_TXCHARDISPMODE3", + "SCANOUT5": "GTPE2_CHANNEL_SCANOUT5", + "RXOUTCLKSEL1": "GTPE2_CHANNEL_RXOUTCLKSEL1", + "DRPDI10": "GTPE2_CHANNEL_DRPDI10", + "PCSRSVDOUT11": "GTPE2_CHANNEL_PCSRSVDOUT11", + "RXGEARBOXSLIP": "GTPE2_CHANNEL_RXGEARBOXSLIP", + "TXPHALIGNDONE": "GTPE2_CHANNEL_TXPHALIGNDONE", + "RXSYNCALLIN": "GTPE2_CHANNEL_RXSYNCALLIN", + "TXDATA2": "GTPE2_CHANNEL_TXDATA2", + "DMONITOROUT2": "GTPE2_CHANNEL_DMONITOROUT2", + "GTRXRESET": "GTPE2_CHANNEL_GTRXRESET", + "RXOSCALRESET": "GTPE2_CHANNEL_RXOSCALRESET", + "RXCHARISCOMMA0": "GTPE2_CHANNEL_RXCHARISCOMMA0", + "PCSRSVDIN11": "GTPE2_CHANNEL_PCSRSVDIN11", + "RXPRBSSEL1": "GTPE2_CHANNEL_RXPRBSSEL1", + "TXPHOVRDEN": "GTPE2_CHANNEL_TXPHOVRDEN", + "RXPHMONITOR2": "GTPE2_CHANNEL_RXPHMONITOR2", + "GTPRXP": "GTPE2_CHANNEL_RXP", + "TXDLYBYPASS": "GTPE2_CHANNEL_TXDLYBYPASS", + "TSTIN16": "GTPE2_CHANNEL_TSTIN16", + "TXPOSTCURSORINV": "GTPE2_CHANNEL_TXPOSTCURSORINV", + "RXCOMSASDET": "GTPE2_CHANNEL_RXCOMSASDET", + "DMONITOROUT9": "GTPE2_CHANNEL_DMONITOROUT9", + "RXDATA18": "GTPE2_CHANNEL_RXDATA18", + "GTRSVD9": "GTPE2_CHANNEL_GTRSVD9", + "SCANOUT0": "GTPE2_CHANNEL_SCANOUT0", + "RXADAPTSELTEST6": "GTPE2_CHANNEL_RXADAPTSELTEST6", + "RXDATA19": "GTPE2_CHANNEL_RXDATA19", + "RXCHBONDSLAVE": "GTPE2_CHANNEL_RXCHBONDSLAVE", + "DMONITOROUT7": "GTPE2_CHANNEL_DMONITOROUT7", + "RXCDRHOLD": "GTPE2_CHANNEL_RXCDRHOLD", + "TXMAINCURSOR0": "GTPE2_CHANNEL_TXMAINCURSOR0", + "RXOSINTCFG2": "GTPE2_CHANNEL_RXOSINTCFG2", + "PMARSVDIN4": "GTPE2_CHANNEL_PMARSVDIN4", + "TXMAINCURSOR5": "GTPE2_CHANNEL_TXMAINCURSOR5", + "TSTIN9": "GTPE2_CHANNEL_TSTIN9", + "TX8B10BBYPASS1": "GTPE2_CHANNEL_TX8B10BBYPASS1", + "RXPRBSSEL2": "GTPE2_CHANNEL_RXPRBSSEL2", + "RXADAPTSELTEST4": "GTPE2_CHANNEL_RXADAPTSELTEST4", + "TXCHARISK0": "GTPE2_CHANNEL_TXCHARISK0", + "PMARSVDIN0": "GTPE2_CHANNEL_PMARSVDIN0", + "TXPDELECIDLEMODE": "GTPE2_CHANNEL_TXPDELECIDLEMODE", + "RXADAPTSELTEST8": "GTPE2_CHANNEL_RXADAPTSELTEST8", + "TXCHARDISPMODE1": "GTPE2_CHANNEL_TXCHARDISPMODE1", + "TXPMARESETDONE": "GTPE2_CHANNEL_TXPMARESETDONE", + "RXBYTEISALIGNED": "GTPE2_CHANNEL_RXBYTEISALIGNED", + "DMONFIFORESET": "GTPE2_CHANNEL_DMONFIFORESET", + "RXPHSLIPMONITOR4": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "TXDIFFPD": "GTPE2_CHANNEL_TXDIFFPD", + "RXOSINTSTROBE": "GTPE2_CHANNEL_RXOSINTSTROBE", + "PLL0CLK": "GTPE2_CHANNEL_PLL0CLK", + "SETERRSTATUS": "GTPE2_CHANNEL_SETERRSTATUS", + "TXPIPPMSTEPSIZE3": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", + "RXSTATUS2": "GTPE2_CHANNEL_RXSTATUS2", + "TX8B10BEN": "GTPE2_CHANNEL_TX8B10BEN", + "DMONITOROUT5": "GTPE2_CHANNEL_DMONITOROUT5", + "RXLPMHFOVRDEN": "GTPE2_CHANNEL_RXLPMHFOVRDEN", + "PCSRSVDOUT9": "GTPE2_CHANNEL_PCSRSVDOUT9", + "RXOUTCLKFABRIC": "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "PCSRSVDOUT0": "GTPE2_CHANNEL_PCSRSVDOUT0", + "RXPHMONITOR4": "GTPE2_CHANNEL_RXPHMONITOR4", + "RXDATA3": "GTPE2_CHANNEL_RXDATA3", + "RXSYNCDONE": "GTPE2_CHANNEL_RXSYNCDONE", + "RXADAPTSELTEST9": "GTPE2_CHANNEL_RXADAPTSELTEST9", + "DRPADDR4": "GTPE2_CHANNEL_DRPADDR4", + "PCSRSVDOUT7": "GTPE2_CHANNEL_PCSRSVDOUT7", + "TXPIPPMSTEPSIZE1": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", + "RXPHMONITOR1": "GTPE2_CHANNEL_RXPHMONITOR1", + "TXPIPPMEN": "GTPE2_CHANNEL_TXPIPPMEN", + "TXCHARDISPVAL3": "GTPE2_CHANNEL_TXCHARDISPVAL3", + "RXUSRCLK2": "GTPE2_CHANNEL_RXUSRCLK2", + "RXDATAVALID1": "GTPE2_CHANNEL_RXDATAVALID1", + "RXLPMOSINTNTRLEN": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", + "GTRSVD5": "GTPE2_CHANNEL_GTRSVD5", + "DRPDO9": "GTPE2_CHANNEL_DRPDO9", + "EYESCANTRIGGER": "GTPE2_CHANNEL_EYESCANTRIGGER", + "SCANMODEB": "GTPE2_CHANNEL_SCANMODEB", + "DRPDO15": "GTPE2_CHANNEL_DRPDO15", + "TXPRBSSEL0": "GTPE2_CHANNEL_TXPRBSSEL0", + "DMONITOROUT3": "GTPE2_CHANNEL_DMONITOROUT3", + "TSTIN14": "GTPE2_CHANNEL_TSTIN14", + "TXUSERRDY": "GTPE2_CHANNEL_TXUSERRDY", + "DRPDO6": "GTPE2_CHANNEL_DRPDO6", + "RXDLYOVRDEN": "GTPE2_CHANNEL_RXDLYOVRDEN", + "DMONITOROUT6": "GTPE2_CHANNEL_DMONITOROUT6", + "RXLPMHFHOLD": "GTPE2_CHANNEL_RXLPMHFHOLD", + "RXCHARISK3": "GTPE2_CHANNEL_RXCHARISK3", + "PMASCANOUT3": "GTPE2_CHANNEL_PMASCANOUT3", + "TXDATA22": "GTPE2_CHANNEL_TXDATA22", + "RXDISPERR3": "GTPE2_CHANNEL_RXDISPERR3", + "TXOUTCLK": "GTPE2_CHANNEL_GTTXOUTCLK_0", + "RXCLKCORCNT1": "GTPE2_CHANNEL_RXCLKCORCNT1", + "RXOSINTID01": "GTPE2_CHANNEL_RXOSINTID01", + "GTRSVD10": "GTPE2_CHANNEL_GTRSVD10", + "TXCHARDISPVAL1": "GTPE2_CHANNEL_TXCHARDISPVAL1", + "RXCDRLOCK": "GTPE2_CHANNEL_RXCDRLOCK", + "RXPHALIGN": "GTPE2_CHANNEL_RXPHALIGN", + "RXNOTINTABLE1": "GTPE2_CHANNEL_RXNOTINTABLE1", + "PMASCANIN3": "GTPE2_CHANNEL_PMASCANIN3", + "RXCDRRESETRSV": "GTPE2_CHANNEL_RXCDRRESETRSV", + "RXBUFRESET": "GTPE2_CHANNEL_RXBUFRESET", + "RXPHMONITOR3": "GTPE2_CHANNEL_RXPHMONITOR3", + "TXPIPPMSEL": "GTPE2_CHANNEL_TXPIPPMSEL", + "RXDATA20": "GTPE2_CHANNEL_RXDATA20", + "DRPDO14": "GTPE2_CHANNEL_DRPDO14", + "TXSYNCDONE": "GTPE2_CHANNEL_TXSYNCDONE", + "PCSRSVDOUT4": "GTPE2_CHANNEL_PCSRSVDOUT4", + "RXELECIDLEMODE0": "GTPE2_CHANNEL_RXELECIDLEMODE0", + "PMASCANIN5": "GTPE2_CHANNEL_PMASCANIN5", + "TXCOMFINISH": "GTPE2_CHANNEL_TXCOMFINISH", + "TXDATA9": "GTPE2_CHANNEL_TXDATA9", + "DRPADDR1": "GTPE2_CHANNEL_DRPADDR1", + "TXDATA11": "GTPE2_CHANNEL_TXDATA11", + "TXRUNDISP0": "GTPE2_CHANNEL_TXRUNDISP0", + "TXBUFSTATUS0": "GTPE2_CHANNEL_TXBUFSTATUS0", + "RXPHSLIPMONITOR1": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "GTTXRESET": "GTPE2_CHANNEL_GTTXRESET", + "RXELECIDLEMODE1": "GTPE2_CHANNEL_RXELECIDLEMODE1", + "RXDATA13": "GTPE2_CHANNEL_RXDATA13", + "TXDATA27": "GTPE2_CHANNEL_TXDATA27", + "RXSYSCLKSEL0": "GTPE2_CHANNEL_RXSYSCLKSEL0", + "PMASCANCLK0": "GTPE2_CHANNEL_PMASCANCLK0", + "TXPRECURSOR2": "GTPE2_CHANNEL_TXPRECURSOR2", + "TXCOMWAKE": "GTPE2_CHANNEL_TXCOMWAKE", + "RXDATA0": "GTPE2_CHANNEL_RXDATA0", + "GTPTXN": "GTPE2_CHANNEL_TXN", + "TXDLYOVRDEN": "GTPE2_CHANNEL_TXDLYOVRDEN", + "RXOSHOLD": "GTPE2_CHANNEL_RXOSHOLD", + "RXLPMRESET": "GTPE2_CHANNEL_RXLPMRESET", + "PCSRSVDIN4": "GTPE2_CHANNEL_PCSRSVDIN4", + "TXSYNCIN": "GTPE2_CHANNEL_TXSYNCIN", + "RXCHBONDO3": "GTPE2_CHANNEL_RXCHBONDO3", + "PCSRSVDIN7": "GTPE2_CHANNEL_PCSRSVDIN7", + "TSTIN3": "GTPE2_CHANNEL_TSTIN3", + "TXGEARBOXREADY": "GTPE2_CHANNEL_TXGEARBOXREADY", + "GTRSVD1": "GTPE2_CHANNEL_GTRSVD1", + "RXDATA22": "GTPE2_CHANNEL_RXDATA22", + "SCANIN4": "GTPE2_CHANNEL_SCANIN4", + "DRPDI12": "GTPE2_CHANNEL_DRPDI12", + "TXDATA31": "GTPE2_CHANNEL_TXDATA31", + "RXSTARTOFSEQ1": "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "PMASCANIN6": "GTPE2_CHANNEL_PMASCANIN6", + "TXRESETDONE": "GTPE2_CHANNEL_TXRESETDONE", + "TXHEADER1": "GTPE2_CHANNEL_TXHEADER1", + "RXDATA2": "GTPE2_CHANNEL_RXDATA2", + "TXRUNDISP2": "GTPE2_CHANNEL_TXRUNDISP2", + "DRPADDR3": "GTPE2_CHANNEL_DRPADDR3", + "TXDATA13": "GTPE2_CHANNEL_TXDATA13", + "TXPMARESET": "GTPE2_CHANNEL_TXPMARESET", + "RXRATE2": "GTPE2_CHANNEL_RXRATE2", + "RXOOBRESET": "GTPE2_CHANNEL_RXOOBRESET", + "DRPADDR2": "GTPE2_CHANNEL_DRPADDR2", + "DRPDO0": "GTPE2_CHANNEL_DRPDO0", + "RXDATA21": "GTPE2_CHANNEL_RXDATA21", + "GTRSVD14": "GTPE2_CHANNEL_GTRSVD14", + "TXDATA23": "GTPE2_CHANNEL_TXDATA23", + "SIGVALIDCLK": "GTPE2_CHANNEL_SIGVALIDCLK", + "PCSRSVDOUT10": "GTPE2_CHANNEL_PCSRSVDOUT10", + "RXRATE1": "GTPE2_CHANNEL_RXRATE1", + "DRPCLK": "GTPE2_CHANNEL_DRPCLK", + "RXCHBONDO1": "GTPE2_CHANNEL_RXCHBONDO1", + "TXPRECURSOR0": "GTPE2_CHANNEL_TXPRECURSOR0", + "RXDATA25": "GTPE2_CHANNEL_RXDATA25", + "DMONITORCLK": "GTPE2_CHANNEL_DMONITORCLK", + "RXCHARISCOMMA3": "GTPE2_CHANNEL_RXCHARISCOMMA3", + "RXADAPTSELTEST12": "GTPE2_CHANNEL_RXADAPTSELTEST12", + "DRPRDY": "GTPE2_CHANNEL_DRPRDY", + "RXOUTCLKSEL2": "GTPE2_CHANNEL_RXOUTCLKSEL2", + "RXOSINTPD": "GTPE2_CHANNEL_RXOSINTPD", + "DMONITOROUT11": "GTPE2_CHANNEL_DMONITOROUT11", + "RXCHANREALIGN": "GTPE2_CHANNEL_RXCHANREALIGN", + "TXOUTCLKPCS": "GTPE2_CHANNEL_TXOUTCLKPCS", + "RXOSINTCFG3": "GTPE2_CHANNEL_RXOSINTCFG3", + "DRPDO4": "GTPE2_CHANNEL_DRPDO4", + "RXBUFSTATUS0": "GTPE2_CHANNEL_RXBUFSTATUS0", + "RXCHBONDI1": "GTPE2_CHANNEL_RXCHBONDI1", + "DRPDI5": "GTPE2_CHANNEL_DRPDI5", + "TXCHARISK2": "GTPE2_CHANNEL_TXCHARISK2", + "DMONITOROUT1": "GTPE2_CHANNEL_DMONITOROUT1", + "TXOUTCLKSEL2": "GTPE2_CHANNEL_TXOUTCLKSEL2", + "TXPOSTCURSOR4": "GTPE2_CHANNEL_TXPOSTCURSOR4", + "DRPADDR0": "GTPE2_CHANNEL_DRPADDR0", + "RXDLYSRESET": "GTPE2_CHANNEL_RXDLYSRESET", + "RXSTATUS1": "GTPE2_CHANNEL_RXSTATUS1", + "RXDFEXYDEN": "GTPE2_CHANNEL_RXDFEXYDEN", + "TXPHDLYTSTCLK": "GTPE2_CHANNEL_TXPHDLYTSTCLK", + "RXPRBSERR": "GTPE2_CHANNEL_RXPRBSERR", + "RXCOMMADET": "GTPE2_CHANNEL_RXCOMMADET", + "TXSYNCMODE": "GTPE2_CHANNEL_TXSYNCMODE", + "RXADAPTSELTEST10": "GTPE2_CHANNEL_RXADAPTSELTEST10", + "RXOSINTSTROBESTARTED": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "TXPCSRESET": "GTPE2_CHANNEL_TXPCSRESET", + "PCSRSVDIN13": "GTPE2_CHANNEL_PCSRSVDIN13", + "TXUSRCLK": "GTPE2_CHANNEL_TXUSRCLK", + "RXRATEDONE": "GTPE2_CHANNEL_RXRATEDONE", + "PLL1CLK": "GTPE2_CHANNEL_PLL1CLK", + "TXSYNCOUT": "GTPE2_CHANNEL_TXSYNCOUT", + "TSTPD0": "GTPE2_CHANNEL_TSTPD0", + "RXOUTCLKPCS": "GTPE2_CHANNEL_RXOUTCLKPCS", + "PMASCANIN4": "GTPE2_CHANNEL_PMASCANIN4", + "TXDATA14": "GTPE2_CHANNEL_TXDATA14", + "PCSRSVDOUT5": "GTPE2_CHANNEL_PCSRSVDOUT5", + "SCANIN2": "GTPE2_CHANNEL_SCANIN2", + "DRPDI15": "GTPE2_CHANNEL_DRPDI15", + "TSTIN8": "GTPE2_CHANNEL_TSTIN8", + "SCANOUT2": "GTPE2_CHANNEL_SCANOUT2", + "RXCHBONDI0": "GTPE2_CHANNEL_RXCHBONDI0", + "RXDISPERR2": "GTPE2_CHANNEL_RXDISPERR2", + "TXPRECURSOR3": "GTPE2_CHANNEL_TXPRECURSOR3", + "LOOPBACK0": "GTPE2_CHANNEL_LOOPBACK0", + "RXPD1": "GTPE2_CHANNEL_RXPD1", + "RXDLYSRESETDONE": "GTPE2_CHANNEL_RXDLYSRESETDONE", + "TXDETECTRX": "GTPE2_CHANNEL_TXDETECTRX", + "TXMAINCURSOR6": "GTPE2_CHANNEL_TXMAINCURSOR6", + "RXOSINTDONE": "GTPE2_CHANNEL_RXOSINTDONE", + "RXPHSLIPMONITOR2": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "RXHEADER2": "GTPE2_CHANNEL_RXHEADER2", + "RXDLYEN": "GTPE2_CHANNEL_RXDLYEN", + "RXOSINTTESTOVRDEN": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", + "RXDATA31": "GTPE2_CHANNEL_RXDATA31", + "GTRESETSEL": "GTPE2_CHANNEL_GTRESETSEL", + "TXPOLARITY": "GTPE2_CHANNEL_TXPOLARITY", + "RXDATA12": "GTPE2_CHANNEL_RXDATA12", + "DRPDI14": "GTPE2_CHANNEL_DRPDI14", + "RXDDIEN": "GTPE2_CHANNEL_RXDDIEN", + "RXOSINTSTROBEDONE": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "DRPEN": "GTPE2_CHANNEL_DRPEN", + "RXCDRFREQRESET": "GTPE2_CHANNEL_RXCDRFREQRESET", + "TXCHARDISPVAL2": "GTPE2_CHANNEL_TXCHARDISPVAL2", + "TXOUTCLKFABRIC": "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "RXSYNCMODE": "GTPE2_CHANNEL_RXSYNCMODE", + "DRPDI1": "GTPE2_CHANNEL_DRPDI1", + "PCSRSVDIN2": "GTPE2_CHANNEL_PCSRSVDIN2", + "RXOSINTID02": "GTPE2_CHANNEL_RXOSINTID02", + "TXMARGIN1": "GTPE2_CHANNEL_TXMARGIN1", + "TXDIFFCTRL0": "GTPE2_CHANNEL_TXDIFFCTRL0", + "RXBYTEREALIGN": "GTPE2_CHANNEL_RXBYTEREALIGN", + "RXDATA29": "GTPE2_CHANNEL_RXDATA29", + "TXMAINCURSOR2": "GTPE2_CHANNEL_TXMAINCURSOR2", + "RXPHSLIPMONITOR0": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "TSTIN18": "GTPE2_CHANNEL_TSTIN18", + "TXDATA18": "GTPE2_CHANNEL_TXDATA18", + "TXPOSTCURSOR1": "GTPE2_CHANNEL_TXPOSTCURSOR1", + "TSTPD1": "GTPE2_CHANNEL_TSTPD1", + "TXDATA5": "GTPE2_CHANNEL_TXDATA5", + "RXLPMLFOVRDEN": "GTPE2_CHANNEL_RXLPMLFOVRDEN", + "PCSRSVDIN3": "GTPE2_CHANNEL_PCSRSVDIN3", + "RXDLYTESTENB": "GTPE2_CHANNEL_RXDLYTESTENB", + "SCANENB": "GTPE2_CHANNEL_SCANENB", + "RXPCSRESET": "GTPE2_CHANNEL_RXPCSRESET", + "RXDATA14": "GTPE2_CHANNEL_RXDATA14", + "RXCHBONDLEVEL0": "GTPE2_CHANNEL_RXCHBONDLEVEL0", + "TSTIN2": "GTPE2_CHANNEL_TSTIN2", + "PHYSTATUS": "GTPE2_CHANNEL_PHYSTATUS", + "RXDATAVALID0": "GTPE2_CHANNEL_RXDATAVALID0", + "SCANOUT4": "GTPE2_CHANNEL_SCANOUT4", + "PMASCANMODEB": "GTPE2_CHANNEL_PMASCANMODEB", + "TXPISOPD": "GTPE2_CHANNEL_TXPISOPD", + "RXMCOMMAALIGNEN": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", + "TXDLYUPDOWN": "GTPE2_CHANNEL_TXDLYUPDOWN", + "EYESCANDATAERROR": "GTPE2_CHANNEL_EYESCANDATAERROR", + "TXDATA17": "GTPE2_CHANNEL_TXDATA17", + "DRPDO3": "GTPE2_CHANNEL_DRPDO3", + "PCSRSVDOUT8": "GTPE2_CHANNEL_PCSRSVDOUT8", + "TXCHARDISPVAL0": "GTPE2_CHANNEL_TXCHARDISPVAL0", + "RXDEBUGPULSE": "GTPE2_CHANNEL_RXDEBUGPULSE", + "PCSRSVDIN5": "GTPE2_CHANNEL_PCSRSVDIN5", + "PLL1REFCLK": "GTPE2_CHANNEL_PLL1REFCLK", + "DRPDI0": "GTPE2_CHANNEL_DRPDI0", + "TXDATA19": "GTPE2_CHANNEL_TXDATA19", + "RXELECIDLE": "GTPE2_CHANNEL_RXELECIDLE", + "TX8B10BBYPASS2": "GTPE2_CHANNEL_TX8B10BBYPASS2", + "PCSRSVDOUT6": "GTPE2_CHANNEL_PCSRSVDOUT6", + "TXPRECURSOR1": "GTPE2_CHANNEL_TXPRECURSOR1", + "RXADAPTSELTEST1": "GTPE2_CHANNEL_RXADAPTSELTEST1", + "RXLPMLFHOLD": "GTPE2_CHANNEL_RXLPMLFHOLD", + "TXDATA16": "GTPE2_CHANNEL_TXDATA16", + "GTRSVD7": "GTPE2_CHANNEL_GTRSVD7", + "TXDATA8": "GTPE2_CHANNEL_TXDATA8", + "SCANIN3": "GTPE2_CHANNEL_SCANIN3", + "TXPRBSFORCEERR": "GTPE2_CHANNEL_TXPRBSFORCEERR", + "TXRUNDISP1": "GTPE2_CHANNEL_TXRUNDISP1", + "TSTIN10": "GTPE2_CHANNEL_TSTIN10", + "DRPADDR8": "GTPE2_CHANNEL_DRPADDR8", + "RXSTATUS0": "GTPE2_CHANNEL_RXSTATUS0", + "TXSEQUENCE1": "GTPE2_CHANNEL_TXSEQUENCE1", + "GTRSVD3": "GTPE2_CHANNEL_GTRSVD3", + "RXDATA17": "GTPE2_CHANNEL_RXDATA17", + "RXPHOVRDEN": "GTPE2_CHANNEL_RXPHOVRDEN", + "TXSWING": "GTPE2_CHANNEL_TXSWING", + "PMASCANIN2": "GTPE2_CHANNEL_PMASCANIN2", + "PMASCANIN1": "GTPE2_CHANNEL_PMASCANIN1", + "RXRESETDONE": "GTPE2_CHANNEL_RXRESETDONE", + "TXDATA0": "GTPE2_CHANNEL_TXDATA0", + "RXCHBONDEN": "GTPE2_CHANNEL_RXCHBONDEN", + "RXDATA9": "GTPE2_CHANNEL_RXDATA9", + "RXCHARISK1": "GTPE2_CHANNEL_RXCHARISK1", + "DRPADDR6": "GTPE2_CHANNEL_DRPADDR6", + "TXRATEDONE": "GTPE2_CHANNEL_TXRATEDONE", + "RXOUTCLKSEL0": "GTPE2_CHANNEL_RXOUTCLKSEL0", + "TXDATA1": "GTPE2_CHANNEL_TXDATA1", + "TSTPD2": "GTPE2_CHANNEL_TSTPD2", + "RXRATEMODE": "GTPE2_CHANNEL_RXRATEMODE", + "RXOSINTEN": "GTPE2_CHANNEL_RXOSINTEN", + "PMASCANOUT0": "GTPE2_CHANNEL_PMASCANOUT0", + "DRPDO12": "GTPE2_CHANNEL_DRPDO12", + "TXPIPPMSTEPSIZE2": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", + "RXPHALIGNEN": "GTPE2_CHANNEL_RXPHALIGNEN", + "GTRSVD4": "GTPE2_CHANNEL_GTRSVD4", + "TSTIN17": "GTPE2_CHANNEL_TSTIN17", + "TXHEADER0": "GTPE2_CHANNEL_TXHEADER0", + "RXOSINTID00": "GTPE2_CHANNEL_RXOSINTID00", + "RXCHARISCOMMA2": "GTPE2_CHANNEL_RXCHARISCOMMA2", + "RXADAPTSELTEST5": "GTPE2_CHANNEL_RXADAPTSELTEST5", + "DRPDI7": "GTPE2_CHANNEL_DRPDI7", + "DRPDI6": "GTPE2_CHANNEL_DRPDI6", + "DMONITOROUT12": "GTPE2_CHANNEL_DMONITOROUT12", + "TXDATA10": "GTPE2_CHANNEL_TXDATA10", + "PMASCANENB": "GTPE2_CHANNEL_PMASCANENB", + "TXCHARDISPMODE2": "GTPE2_CHANNEL_TXCHARDISPMODE2", + "PMARSVDIN2": "GTPE2_CHANNEL_PMARSVDIN2", + "RXCHANISALIGNED": "GTPE2_CHANNEL_RXCHANISALIGNED", + "GTPTXP": "GTPE2_CHANNEL_TXP", + "RXBUFSTATUS2": "GTPE2_CHANNEL_RXBUFSTATUS2", + "RXPHDLYRESET": "GTPE2_CHANNEL_RXPHDLYRESET", + "PMASCANCLK1": "GTPE2_CHANNEL_PMASCANCLK1", + "TSTPD4": "GTPE2_CHANNEL_TSTPD4", + "TXPRECURSOR4": "GTPE2_CHANNEL_TXPRECURSOR4", + "DMONITOROUT10": "GTPE2_CHANNEL_DMONITOROUT10", + "DRPADDR7": "GTPE2_CHANNEL_DRPADDR7", + "DMONITOROUT0": "GTPE2_CHANNEL_DMONITOROUT0", + "TXDATA24": "GTPE2_CHANNEL_TXDATA24", + "TXDIFFCTRL1": "GTPE2_CHANNEL_TXDIFFCTRL1", + "TXDATA28": "GTPE2_CHANNEL_TXDATA28", + "TXSEQUENCE4": "GTPE2_CHANNEL_TXSEQUENCE4", + "DMONITOROUT4": "GTPE2_CHANNEL_DMONITOROUT4", + "TXBUFDIFFCTRL1": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", + "DRPDO7": "GTPE2_CHANNEL_DRPDO7", + "EYESCANRESET": "GTPE2_CHANNEL_EYESCANRESET", + "RXPD0": "GTPE2_CHANNEL_RXPD0", + "DRPADDR5": "GTPE2_CHANNEL_DRPADDR5", + "RXOUTCLK": "GTPE2_CHANNEL_GTRXOUTCLK_0", + "TXSYNCALLIN": "GTPE2_CHANNEL_TXSYNCALLIN", + "RXHEADER0": "GTPE2_CHANNEL_RXHEADER0", + "TSTIN0": "GTPE2_CHANNEL_TSTIN0", + "RXHEADER1": "GTPE2_CHANNEL_RXHEADER1", + "DRPDO2": "GTPE2_CHANNEL_DRPDO2", + "TXDLYSRESET": "GTPE2_CHANNEL_TXDLYSRESET", + "TX8B10BBYPASS0": "GTPE2_CHANNEL_TX8B10BBYPASS0", + "TSTIN5": "GTPE2_CHANNEL_TSTIN5", + "DRPDO8": "GTPE2_CHANNEL_DRPDO8", + "RXCHARISK0": "GTPE2_CHANNEL_RXCHARISK0", + "RXDATA10": "GTPE2_CHANNEL_RXDATA10", + "RXOSINTOVRDEN": "GTPE2_CHANNEL_RXOSINTOVRDEN", + "PMARSVDOUT0": "GTPE2_CHANNEL_PMARSVDOUT0", + "RXDATA27": "GTPE2_CHANNEL_RXDATA27", + "GTPRXN": "GTPE2_CHANNEL_RXN", + "DRPDO1": "GTPE2_CHANNEL_DRPDO1", + "PCSRSVDIN10": "GTPE2_CHANNEL_PCSRSVDIN10", + "DRPDO11": "GTPE2_CHANNEL_DRPDO11", + "DRPDI3": "GTPE2_CHANNEL_DRPDI3", + "GTRSVD13": "GTPE2_CHANNEL_GTRSVD13", + "TSTIN13": "GTPE2_CHANNEL_TSTIN13", + "TXDATA25": "GTPE2_CHANNEL_TXDATA25", + "TXINHIBIT": "GTPE2_CHANNEL_TXINHIBIT", + "PCSRSVDOUT1": "GTPE2_CHANNEL_PCSRSVDOUT1", + "PCSRSVDOUT15": "GTPE2_CHANNEL_PCSRSVDOUT15", + "RXCDRRESET": "GTPE2_CHANNEL_RXCDRRESET", + "TXBUFDIFFCTRL2": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", + "PCSRSVDOUT12": "GTPE2_CHANNEL_PCSRSVDOUT12", + "CLKRSVD0": "GTPE2_CHANNEL_CLKRSVD0", + "RXCHBONDMASTER": "GTPE2_CHANNEL_RXCHBONDMASTER", + "TXDIFFCTRL2": "GTPE2_CHANNEL_TXDIFFCTRL2", + "RXPHSLIPMONITOR3": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "TXSTARTSEQ": "GTPE2_CHANNEL_TXSTARTSEQ", + "TXCHARISK1": "GTPE2_CHANNEL_TXCHARISK1", + "RXCHBONDLEVEL1": "GTPE2_CHANNEL_RXCHBONDLEVEL1", + "DRPDO13": "GTPE2_CHANNEL_DRPDO13", + "SCANIN0": "GTPE2_CHANNEL_SCANIN0", + "TXDATA12": "GTPE2_CHANNEL_TXDATA12", + "RXDATA5": "GTPE2_CHANNEL_RXDATA5", + "TXPOSTCURSOR0": "GTPE2_CHANNEL_TXPOSTCURSOR0", + "RXPHMONITOR0": "GTPE2_CHANNEL_RXPHMONITOR0", + "TXSEQUENCE6": "GTPE2_CHANNEL_TXSEQUENCE6", + "RXCHARISCOMMA1": "GTPE2_CHANNEL_RXCHARISCOMMA1", + "RXDATA30": "GTPE2_CHANNEL_RXDATA30", + "RXCHBONDO2": "GTPE2_CHANNEL_RXCHBONDO2", + "RXDATA23": "GTPE2_CHANNEL_RXDATA23", + "TXRATE1": "GTPE2_CHANNEL_TXRATE1", + "RXADAPTSELTEST11": "GTPE2_CHANNEL_RXADAPTSELTEST11", + "PLL0REFCLK": "GTPE2_CHANNEL_PLL0REFCLK", + "RESETOVRD": "GTPE2_CHANNEL_RESETOVRD", + "TXBUFSTATUS1": "GTPE2_CHANNEL_TXBUFSTATUS1", + "RXSTARTOFSEQ0": "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "PMASCANOUT2": "GTPE2_CHANNEL_PMASCANOUT2", + "RXDATA11": "GTPE2_CHANNEL_RXDATA11", + "TXMAINCURSOR4": "GTPE2_CHANNEL_TXMAINCURSOR4", + "PMASCANOUT5": "GTPE2_CHANNEL_PMASCANOUT5", + "RXOSINTHOLD": "GTPE2_CHANNEL_RXOSINTHOLD", + "TXPHALIGN": "GTPE2_CHANNEL_TXPHALIGN", + "DRPDI2": "GTPE2_CHANNEL_DRPDI2", + "RXCHBONDI2": "GTPE2_CHANNEL_RXCHBONDI2", + "TXPHDLYRESET": "GTPE2_CHANNEL_TXPHDLYRESET", + "RXPMARESET": "GTPE2_CHANNEL_RXPMARESET", + "RXSYNCIN": "GTPE2_CHANNEL_RXSYNCIN", + "RXDATA8": "GTPE2_CHANNEL_RXDATA8", + "TXDEEMPH": "GTPE2_CHANNEL_TXDEEMPH", + "RXPHALIGNDONE": "GTPE2_CHANNEL_RXPHALIGNDONE", + "RXOSOVRDEN": "GTPE2_CHANNEL_RXOSOVRDEN", + "TSTIN19": "GTPE2_CHANNEL_TSTIN19", + "TXDATA15": "GTPE2_CHANNEL_TXDATA15", + "RXPMARESETDONE": "GTPE2_CHANNEL_RXPMARESETDONE", + "RXDISPERR0": "GTPE2_CHANNEL_RXDISPERR0", + "RXSYSCLKSEL1": "GTPE2_CHANNEL_RXSYSCLKSEL1", + "GTRSVD11": "GTPE2_CHANNEL_GTRSVD11", + "DRPDO10": "GTPE2_CHANNEL_DRPDO10", + "PCSRSVDOUT3": "GTPE2_CHANNEL_PCSRSVDOUT3", + "SCANOUT3": "GTPE2_CHANNEL_SCANOUT3", + "RXDATA7": "GTPE2_CHANNEL_RXDATA7", + "TXDLYTESTENB": "GTPE2_CHANNEL_TXDLYTESTENB", + "RXOSINTID03": "GTPE2_CHANNEL_RXOSINTID03", + "TXPRECURSORINV": "GTPE2_CHANNEL_TXPRECURSORINV", + "TXPIPPMSTEPSIZE0": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", + "TSTIN15": "GTPE2_CHANNEL_TSTIN15", + "PMASCANCLK3": "GTPE2_CHANNEL_PMASCANCLK3", + "PMARSVDIN1": "GTPE2_CHANNEL_PMARSVDIN1", + "RXCHBONDLEVEL2": "GTPE2_CHANNEL_RXCHBONDLEVEL2", + "PCSRSVDIN1": "GTPE2_CHANNEL_PCSRSVDIN1", + "RXNOTINTABLE2": "GTPE2_CHANNEL_RXNOTINTABLE2", + "TXDATA30": "GTPE2_CHANNEL_TXDATA30", + "TSTPDOVRDB": "GTPE2_CHANNEL_TSTPDOVRDB", + "RXOSINTSTARTED": "GTPE2_CHANNEL_RXOSINTSTARTED", + "TSTIN6": "GTPE2_CHANNEL_TSTIN6", + "PMASCANOUT6": "GTPE2_CHANNEL_PMASCANOUT6", + "TXSEQUENCE0": "GTPE2_CHANNEL_TXSEQUENCE0", + "SCANIN5": "GTPE2_CHANNEL_SCANIN5", + "RXDATA1": "GTPE2_CHANNEL_RXDATA1", + "RXADAPTSELTEST13": "GTPE2_CHANNEL_RXADAPTSELTEST13", + "RXDATA24": "GTPE2_CHANNEL_RXDATA24", + "TXDLYSRESETDONE": "GTPE2_CHANNEL_TXDLYSRESETDONE", + "TXDATA20": "GTPE2_CHANNEL_TXDATA20", + "SCANCLK": "GTPE2_CHANNEL_SCANCLK", + "RXPRBSSEL0": "GTPE2_CHANNEL_RXPRBSSEL0", + "TXCOMINIT": "GTPE2_CHANNEL_TXCOMINIT", + "RXUSERRDY": "GTPE2_CHANNEL_RXUSERRDY", + "TXSEQUENCE3": "GTPE2_CHANNEL_TXSEQUENCE3", + "TXOUTCLKSEL0": "GTPE2_CHANNEL_TXOUTCLKSEL0", + "PMASCANOUT4": "GTPE2_CHANNEL_PMASCANOUT4", + "TXDATA4": "GTPE2_CHANNEL_TXDATA4", + "TX8B10BBYPASS3": "GTPE2_CHANNEL_TX8B10BBYPASS3", + "SCANIN1": "GTPE2_CHANNEL_SCANIN1", + "DRPWE": "GTPE2_CHANNEL_DRPWE", + "TXDATA7": "GTPE2_CHANNEL_TXDATA7", + "TXPRBSSEL2": "GTPE2_CHANNEL_TXPRBSSEL2", + "RXDISPERR1": "GTPE2_CHANNEL_RXDISPERR1", + "PCSRSVDIN0": "GTPE2_CHANNEL_PCSRSVDIN0", + "TXRATEMODE": "GTPE2_CHANNEL_TXRATEMODE", + "RXRATE0": "GTPE2_CHANNEL_RXRATE0", + "RXOSINTNTRLEN": "GTPE2_CHANNEL_RXOSINTNTRLEN", + "TXSEQUENCE5": "GTPE2_CHANNEL_TXSEQUENCE5", + "RXDATA4": "GTPE2_CHANNEL_RXDATA4", + "TXPHINITDONE": "GTPE2_CHANNEL_TXPHINITDONE", + "DMONITOROUT8": "GTPE2_CHANNEL_DMONITOROUT8", + "RXDLYBYPASS": "GTPE2_CHANNEL_RXDLYBYPASS", + "RXPRBSCNTRESET": "GTPE2_CHANNEL_RXPRBSCNTRESET", + "RXOSINTCFG1": "GTPE2_CHANNEL_RXOSINTCFG1", + "DRPDI8": "GTPE2_CHANNEL_DRPDI8", + "PCSRSVDIN15": "GTPE2_CHANNEL_PCSRSVDIN15", + "RXDATA6": "GTPE2_CHANNEL_RXDATA6", + "RXDATA28": "GTPE2_CHANNEL_RXDATA28", + "TXPOSTCURSOR2": "GTPE2_CHANNEL_TXPOSTCURSOR2", + "DRPDI11": "GTPE2_CHANNEL_DRPDI11", + "RXADAPTSELTEST2": "GTPE2_CHANNEL_RXADAPTSELTEST2", + "PCSRSVDIN14": "GTPE2_CHANNEL_PCSRSVDIN14", + "RXDATA26": "GTPE2_CHANNEL_RXDATA26", + "DMONITOROUT14": "GTPE2_CHANNEL_DMONITOROUT14" + }, + "type": "GTPE2_CHANNEL", + "prefix": "GTPE2_CHANNEL", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "O": "GTPE2_CHANNEL_RXN_PAD" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y6", + "x_coord": 1, + "y_coord": 6 + }, + { + "site_pins": { + "O": "GTPE2_CHANNEL_RXP_PAD" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y7", + "x_coord": 1, + "y_coord": 7 + }, + { + "site_pins": { + "I": "GTPE2_CHANNEL_TXN_PAD" + }, + "type": "OPAD", + "prefix": "OPAD", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "I": "GTPE2_CHANNEL_TXP_PAD" + }, + "type": "OPAD", + "prefix": "OPAD", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_GTP_CHANNEL_1.json b/artix7/tile_type_GTP_CHANNEL_1.json index 5af332d..2fe6188 100644 --- a/artix7/tile_type_GTP_CHANNEL_1.json +++ b/artix7/tile_type_GTP_CHANNEL_1.json @@ -1,5922 +1,5922 @@ { - "wires": [ - "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "GTPE2_IMUX18_2", - "GTPE2_LOGIC_OUTS_B1_3", - "GTPE2_IMUX26_4", - "GTPE2_CHANNEL_TXDATA13", - "GTPE2_CHANNEL_PMARSVDOUT0", - "GTPE2_FAN1_0", - "GTPE2_LOGIC_OUTS_B14_6", - "GTPE2_LOGIC_OUTS_B13_2", - "GTPE2_FAN3_5", - "GTPE2_IMUX16_6", - "GTPE2_CHANNEL_SETERRSTATUS", - "GTPE2_IMUX43_9", - "GTPE2_BYP5_3", - "GTPE2_LOGIC_OUTS_B19_5", - "GTPE2_IMUX34_0", - "GTPE2_LOGIC_OUTS_B10_3", - "GTPE2_LOGIC_OUTS_B5_1", - "GTPE2_IMUX18_1", - "GTPE2_IMUX6_4", - "GTPE2_IMUX21_5", - "GTPE2_CHANNEL_RXPHDLYPD", - "GTPE2_IMUX40_9", - "GTPE2_CHANNEL_TXMAINCURSOR3", - "GTPE2_CHANNEL_TSTCLK0", - "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "GTPE2_LOGIC_OUTS_B9_7", - "GTPE2_LOGIC_OUTS_B13_8", - "GTPE2_CHANNEL_RXDATAVALID0", - "GTPE2_CHANNEL_PCSRSVDOUT0", - "GTPE2_CHANNEL_RXSYNCMODE", - "GTPE2_LOGIC_OUTS_B10_0", - "GTPE2_CHANNEL_SCANOUT3", - "GTPE2_CHANNEL_RXOSOVRDEN", - "GTPE2_IMUX47_9", - "GTPE2_CHANNEL_RXCHBONDI1", - "GTPE2_CHANNEL_RXCHBONDI2", - "GTPE2_FAN2_1", - "GTPE2_CTRL1_2", - "GTPE2_CHANNEL_PCSRSVDOUT8", - "GTPE2_LOGIC_OUTS_B18_2", - "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "GTPE2_IMUX32_4", - "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "GTPE2_FAN1_8", - "GTPE2_CHANNEL_RXOUTCLK_3", - "GTPE2_CHANNEL_TXDATA11", - "GTPE2_LOGIC_OUTS_B15_5", - "GTPE2_IMUX15_8", - "GTPE2_CHANNEL_TXDATA21", - "GTPE2_CLK0_4", - "GTPE2_CHANNEL_RXPCSRESET", - "GTPE2_IMUX14_4", - "GTPE2_LOGIC_OUTS_B23_2", - "GTPE2_LOGIC_OUTS_B5_6", - "GTPE2_CHANNEL_PCSRSVDIN14", - "GTPE2_FAN2_5", - "GTPE2_CHANNEL_PCSRSVDOUT10", - "GTPE2_IMUX14_6", - "GTPE2_IMUX15_1", - "GTPE2_IMUX30_7", - "GTPE2_CHANNEL_PMASCANOUT4", - "GTPE2_CHANNEL_TXDATA2", - "GTPE2_IMUX41_6", - "GTPE2_IMUX47_4", - "GTPE2_FAN6_0", - "GTPE2_CHANNEL_TXPRECURSOR4", - "GTPE2_FAN3_3", - "GTPE2_CHANNEL_TX8B10BBYPASS0", - "GTPE2_CHANNEL_PMASCANOUT5", - "GTPE2_LOGIC_OUTS_B14_5", - "GTPE2_CHANNEL_TXDLYTESTENB", - "GTPE2_CHANNEL_RXVALID", - "GTPE2_BYP1_9", - "GTPE2_LOGIC_OUTS_B7_6", - "GTPE2_CHANNEL_RXDATA24", - "GTPE2_IMUX10_2", - "GTPE2_CHANNEL_DRPADDR4", - "GTPE2_IMUX2_1", - "GTPE2_IMUX4_4", - "GTPE2_CHANNEL_PMASCANIN0", - "GTPE2_FAN3_7", - "GTPE2_CHANNEL_TXPMARESETDONE", - "GTPE2_CHANNEL_RXSYNCIN", - "GTPE2_LOGIC_OUTS_B8_10", - "GTPE2_CHANNEL_RXRATEMODE", - "GTPE2_LOGIC_OUTS_B10_9", - "GTPE2_IMUX31_10", - "GTPE2_CHANNEL_DRPDO1", - "GTPE2_CTRL0_7", - "GTPE2_CHANNEL_PLLCLK1", - "GTPE2_IMUX29_3", - "GTPE2_BYP6_1", - "GTPE2_CHANNEL_RXCOMINITDET", - "GTPE2_CHANNEL_TXDIFFPD", - "GTPE2_IMUX27_2", - "GTPE2_CHANNEL_TXDIFFCTRL0", - "GTPE2_IMUX40_1", - "GTPE2_FAN6_2", - "GTPE2_CHANNEL_TXPOSTCURSOR3", - "GTPE2_IMUX37_10", - "GTPE2_LOGIC_OUTS_B15_4", - "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "GTPE2_CHANNEL_TXMAINCURSOR6", - "GTPE2_IMUX27_1", - "GTPE2_CTRL1_7", - "GTPE2_LOGIC_OUTS_B1_5", - "GTPE2_CHANNEL_TSTIN2", - "GTPE2_CHANNEL_RXDATA9", - "GTPE2_IMUX3_5", - "GTPE2_CHANNEL_RXPHALIGNDONE", - "GTPE2_CHANNEL_RXPHMONITOR3", - "GTPE2_LOGIC_OUTS_B2_9", - "GTPE2_IMUX31_1", - "GTPE2_IMUX17_10", - "GTPE2_CHANNEL_RXCHARISCOMMA0", - "GTPE2_LOGIC_OUTS_B8_4", - "GTPE2_FAN7_6", - "GTPE2_IMUX41_2", - "GTPE2_IMUX12_0", - "GTPE2_LOGIC_OUTS_B10_5", - "GTPE2_IMUX10_0", - "GTPE2_LOGIC_OUTS_B17_8", - "GTPE2_FAN3_9", - "GTPE2_CHANNEL_RXCHARISCOMMA1", - "GTPE2_IMUX33_7", - "GTPE2_LOGIC_OUTS_B5_9", - "GTPE2_IMUX36_7", - "GTPE2_IMUX3_7", - "GTPE2_LOGIC_OUTS_B12_9", - "GTPE2_IMUX16_1", - "GTPE2_LOGIC_OUTS_B23_5", - "GTPE2_FAN2_2", - "GTPE2_IMUX0_5", - "GTPE2_CHANNEL_TXOUTCLK_0", - "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "GTPE2_CHANNEL_PCSRSVDIN6", - "GTPE2_IMUX33_3", - "GTPE2_IMUX41_4", - "GTPE2_IMUX46_6", - "GTPE2_CHANNEL_TXHEADER0", - "GTPE2_BYP0_1", - "GTPE2_IMUX1_9", - "GTPE2_CHANNEL_PCSRSVDIN8", - "GTPE2_IMUX13_4", - "GTPE2_CHANNEL_RXADAPTSELTEST1", - "GTPE2_IMUX32_9", - "GTPE2_BYP4_5", - "GTPE2_CHANNEL_RXADAPTSELTEST8", - "GTPE2_CHANNEL_TXDLYUPDOWN", - "GTPE2_IMUX44_7", - "GTPE2_IMUX19_8", - "GTPE2_IMUX41_7", - "GTPE2_IMUX19_2", - "GTPE2_CHANNEL_GTRSVD8", - "GTPE2_IMUX4_0", - "GTPE2_BYP6_7", - "GTPE2_IMUX25_10", - "GTPE2_FAN7_3", - "GTPE2_CHANNEL_RXCHBONDSLAVE", - "GTPE2_IMUX24_3", - "GTPE2_LOGIC_OUTS_B5_8", - "GTPE2_FAN0_7", - "GTPE2_IMUX45_6", - "GTPE2_CTRL0_2", - "GTPE2_IMUX43_5", - "GTPE2_CHANNEL_PCSRSVDOUT13", - "GTPE2_IMUX17_4", - "GTPE2_BYP3_7", - "GTPE2_CHANNEL_SCANOUT0", - "GTPE2_IMUX43_1", - "GTPE2_CHANNEL_RXOUTCLK_1", - "GTPE2_CHANNEL_RXDISPERR2", - "GTPE2_CHANNEL_GTRSVD1", - "GTPE2_IMUX13_8", - "GTPE2_IMUX20_4", - "GTPE2_BYP0_8", - "GTPE2_IMUX0_2", - "GTPE2_IMUX29_2", - "GTPE2_IMUX6_5", - "GTPE2_LOGIC_OUTS_B2_0", - "GTPE2_LOGIC_OUTS_B1_2", - "GTPE2_IMUX18_6", - "GTPE2_LOGIC_OUTS_B15_7", - "GTPE2_LOGIC_OUTS_B1_6", - "GTPE2_LOGIC_OUTS_B16_8", - "GTPE2_IMUX44_3", - "GTPE2_CHANNEL_PMARSVDIN1", - "GTPE2_CHANNEL_TXDATA1", - "GTPE2_CHANNEL_RXOSINTID00", - "GTPE2_LOGIC_OUTS_B3_0", - "GTPE2_CHANNEL_RXCHBONDO1", - "GTPE2_IMUX2_3", - "GTPE2_CHANNEL_RXOSINTID03", - "GTPE2_CHANNEL_PMASCANOUT1", - "GTPE2_LOGIC_OUTS_B19_3", - "GTPE2_CHANNEL_TXHEADER2", - "GTPE2_LOGIC_OUTS_B10_2", - "GTPE2_IMUX45_0", - "GTPE2_CHANNEL_DMONITOROUT6", - "GTPE2_LOGIC_OUTS_B9_3", - "GTPE2_IMUX17_8", - "GTPE2_CHANNEL_SIGVALIDCLK", - "GTPE2_IMUX31_5", - "GTPE2_LOGIC_OUTS_B2_3", - "GTPE2_FAN7_2", - "GTPE2_CHANNEL_RXPRBSSEL1", - "GTPE2_IMUX19_1", - "GTPE2_CHANNEL_PMASCANRSTEN", - "GTPE2_IMUX5_6", - "GTPE2_LOGIC_OUTS_B4_9", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "GTPE2_CHANNEL_RXPRBSCNTRESET", - "GTPE2_IMUX29_1", - "GTPE2_CHANNEL_RXDATA29", - "GTPE2_CHANNEL_RXDATA27", - "GTPE2_CHANNEL_PCSRSVDIN2", - "GTPE2_CHANNEL_GTRXOUTCLK_1", - "GTPE2_CHANNEL_PCSRSVDIN3", - "GTPE2_IMUX10_6", - "GTPE2_IMUX32_3", - "GTPE2_CHANNEL_RXOSINTHOLD", - "GTPE2_CHANNEL_DRPWE", - "GTPE2_CHANNEL_DMONITORCLK", - "GTPE2_LOGIC_OUTS_B9_1", - "GTPE2_IMUX20_7", - "GTPE2_LOGIC_OUTS_B6_2", - "GTPE2_LOGIC_OUTS_B6_3", - "GTPE2_IMUX34_10", - "GTPE2_IMUX25_5", - "GTPE2_IMUX9_6", - "GTPE2_CHANNEL_TXBUFSTATUS1", - "GTPE2_IMUX30_6", - "GTPE2_LOGIC_OUTS_B22_1", - "GTPE2_IMUX46_10", - "GTPE2_IMUX11_10", - "GTPE2_IMUX31_6", - "GTPE2_IMUX42_2", - "GTPE2_IMUX34_5", - "GTPE2_LOGIC_OUTS_B2_4", - "GTPE2_CHANNEL_RXADAPTSELTEST7", - "GTPE2_IMUX14_10", - "GTPE2_FAN0_9", - "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "GTPE2_CTRL1_3", - "GTPE2_CHANNEL_SCANIN0", - "GTPE2_FAN6_1", - "GTPE2_IMUX46_3", - "GTPE2_CHANNEL_TXSEQUENCE0", - "GTPE2_IMUX2_0", - "GTPE2_LOGIC_OUTS_B13_6", - "GTPE2_BYP4_1", - "GTPE2_CHANNEL_TXPHALIGN", - "GTPE2_CHANNEL_GTRESETSEL", - "GTPE2_LOGIC_OUTS_B13_10", - "GTPE2_CHANNEL_PLL0REFCLK", - "GTPE2_LOGIC_OUTS_B8_1", - "GTPE2_IMUX12_6", - "GTPE2_CHANNEL_RXP_PAD", - "GTPE2_IMUX25_1", - "GTPE2_IMUX29_10", - "GTPE2_IMUX30_8", - "GTPE2_IMUX2_2", - "GTPE2_LOGIC_OUTS_B14_9", - "GTPE2_LOGIC_OUTS_B23_4", - "GTPE2_IMUX30_5", - "GTPE2_CLK1_5", - "GTPE2_IMUX31_7", - "GTPE2_CHANNEL_TXMAINCURSOR4", - "GTPE2_IMUX12_3", - "GTPE2_IMUX1_5", - "GTPE2_LOGIC_OUTS_B21_7", - "GTPE2_CHANNEL_TSTIN10", - "GTPE2_IMUX45_3", - "GTPE2_CHANNEL_TXPHALIGNDONE", - "GTPE2_CHANNEL_TXDIFFCTRL3", - "GTPE2_IMUX22_9", - "GTPE2_IMUX19_4", - "GTPE2_LOGIC_OUTS_B4_7", - "GTPE2_IMUX46_8", - "GTPE2_CHANNEL_RXADAPTSELTEST12", - "GTPE2_IMUX28_1", - "GTPE2_LOGIC_OUTS_B4_6", - "GTPE2_CHANNEL_TXDEEMPH", - "GTPE2_IMUX8_8", - "GTPE2_LOGIC_OUTS_B17_10", - "GTPE2_CHANNEL_PCSRSVDIN7", - "GTPE2_LOGIC_OUTS_B4_5", - "GTPE2_IMUX31_3", - "GTPE2_CHANNEL_RXBYTEISALIGNED", - "GTPE2_CHANNEL_TSTIN8", - "GTPE2_IMUX28_8", - "GTPE2_CHANNEL_TXUSERRDY", - "GTPE2_CHANNEL_SCANIN4", - "GTPE2_CHANNEL_RXLPMLFHOLD", - "GTPE2_CHANNEL_PMARSVDIN0", - "GTPE2_IMUX12_5", - "GTPE2_FAN2_8", - "GTPE2_CHANNEL_TXRATE2", - "GTPE2_LOGIC_OUTS_B20_6", - "GTPE2_CHANNEL_TXSYNCALLIN", - "GTPE2_LOGIC_OUTS_B19_9", - "GTPE2_IMUX13_1", - "GTPE2_FAN3_2", - "GTPE2_LOGIC_OUTS_B0_4", - "GTPE2_CHANNEL_TXCHARDISPVAL0", - "GTPE2_IMUX33_2", - "GTPE2_IMUX1_4", - "GTPE2_IMUX14_8", - "GTPE2_IMUX4_10", - "GTPE2_LOGIC_OUTS_B2_5", - "GTPE2_IMUX8_6", - "GTPE2_IMUX15_2", - "GTPE2_CHANNEL_TXRATE1", - "GTPE2_BYP6_3", - "GTPE2_CHANNEL_RXNOTINTABLE2", - "GTPE2_FAN4_4", - "GTPE2_LOGIC_OUTS_B9_9", - "GTPE2_CHANNEL_TXCHARDISPMODE0", - "GTPE2_IMUX16_8", - "GTPE2_LOGIC_OUTS_B18_3", - "GTPE2_IMUX36_3", - "GTPE2_CHANNEL_TXCOMFINISH", - "GTPE2_IMUX11_4", - "GTPE2_IMUX14_9", - "GTPE2_IMUX20_2", - "GTPE2_IMUX16_5", - "GTPE2_CHANNEL_RXOOBRESET", - "GTPE2_CHANNEL_RXOSHOLD", - "GTPE2_CHANNEL_GTRXRESET", - "GTPE2_CHANNEL_TXPHINIT", - "GTPE2_CHANNEL_RXADAPTSELTEST3", - "GTPE2_IMUX36_5", - "GTPE2_BYP2_5", - "GTPE2_CLK0_9", - "GTPE2_CHANNEL_DRPDO5", - "GTPE2_IMUX20_6", - "GTPE2_CHANNEL_SCANMODEB", - "GTPE2_IMUX36_4", - "GTPE2_CLK0_10", - "GTPE2_LOGIC_OUTS_B3_6", - "GTPE2_CHANNEL_TXDATA17", - "GTPE2_LOGIC_OUTS_B6_10", - "GTPE2_CHANNEL_RXPD0", - "GTPE2_IMUX1_2", - "GTPE2_IMUX44_2", - "GTPE2_CHANNEL_DRPDO7", - "GTPE2_LOGIC_OUTS_B23_3", - "GTPE2_IMUX47_6", - "GTPE2_CHANNEL_RXPHDLYRESET", - "GTPE2_LOGIC_OUTS_B2_1", - "GTPE2_LOGIC_OUTS_B10_8", - "GTPE2_IMUX44_0", - "GTPE2_CHANNEL_TXCOMSAS", - "GTPE2_CHANNEL_DMONITOROUT12", - "GTPE2_CHANNEL_RXDATA8", - "GTPE2_IMUX2_4", - "GTPE2_CHANNEL_PCSRSVDOUT7", - "GTPE2_LOGIC_OUTS_B11_0", - "GTPE2_LOGIC_OUTS_B8_3", - "GTPE2_CHANNEL_RXDATAVALID1", - "GTPE2_CHANNEL_GTRSVD9", - "GTPE2_CHANNEL_TSTIN15", - "GTPE2_CHANNEL_TXCHARISK0", - "GTPE2_LOGIC_OUTS_B6_5", - "GTPE2_IMUX29_0", - "GTPE2_CHANNEL_TXOUTCLK_2", - "GTPE2_CHANNEL_RXCHARISK3", - "GTPE2_FAN7_4", - "GTPE2_CLK0_8", - "GTPE2_CHANNEL_GTRSVD3", - "GTPE2_CHANNEL_RXCHANISALIGNED", - "GTPE2_CHANNEL_RXCHBONDO3", - "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "GTPE2_IMUX26_5", - "GTPE2_LOGIC_OUTS_B10_10", - "GTPE2_CHANNEL_RXDLYBYPASS", - "GTPE2_CHANNEL_TSTCLK1", - "GTPE2_CHANNEL_TXDATA12", - "GTPE2_CHANNEL_DRPDO14", - "GTPE2_IMUX28_9", - "GTPE2_IMUX21_7", - "GTPE2_IMUX5_8", - "GTPE2_FAN2_6", - "GTPE2_IMUX42_1", - "GTPE2_CHANNEL_DMONITOROUT13", - "GTPE2_IMUX31_9", - "GTPE2_FAN0_5", - "GTPE2_IMUX8_7", - "GTPE2_IMUX39_9", - "GTPE2_LOGIC_OUTS_B22_0", - "GTPE2_CHANNEL_PCSRSVDIN12", - "GTPE2_CHANNEL_TXUSRCLK2", - "GTPE2_CHANNEL_RXDISPERR1", - "GTPE2_CHANNEL_DMONITOROUT14", - "GTPE2_IMUX24_1", - "GTPE2_LOGIC_OUTS_B11_9", - "GTPE2_LOGIC_OUTS_B21_5", - "GTPE2_IMUX8_5", - "GTPE2_CHANNEL_RXUSRCLK", - "GTPE2_IMUX47_8", - "GTPE2_FAN4_8", - "GTPE2_CHANNEL_RXDATA1", - "GTPE2_IMUX19_3", - "GTPE2_CHANNEL_RXPHALIGN", - "GTPE2_CHANNEL_PMARSVDIN3", - "GTPE2_CHANNEL_RXDLYSRESETDONE", - "GTPE2_LOGIC_OUTS_B7_5", - "GTPE2_IMUX37_5", - "GTPE2_CHANNEL_RXPHMONITOR2", - "GTPE2_FAN1_10", - "GTPE2_CHANNEL_RXDISPERR3", - "GTPE2_BYP2_9", - "GTPE2_LOGIC_OUTS_B17_6", - "GTPE2_CHANNEL_RXRATE2", - "GTPE2_IMUX15_10", - "GTPE2_CHANNEL_PMASCANOUT3", - "GTPE2_IMUX30_4", - "GTPE2_CHANNEL_RXOUTCLKSEL1", - "GTPE2_CHANNEL_RXDDIEN", - "GTPE2_CHANNEL_TXCHARISK3", - "GTPE2_IMUX42_0", - "GTPE2_IMUX36_9", - "GTPE2_LOGIC_OUTS_B21_10", - "GTPE2_IMUX2_8", - "GTPE2_CHANNEL_TXRATE0", - "GTPE2_CHANNEL_RXOSINTPD", - "GTPE2_IMUX4_8", - "GTPE2_CLK0_0", - "GTPE2_CHANNEL_RXPRBSSEL0", - "GTPE2_LOGIC_OUTS_B18_6", - "GTPE2_CHANNEL_RXDATA21", - "GTPE2_CHANNEL_TXDATA4", - "GTPE2_CHANNEL_RESETOVRD", - "GTPE2_BYP7_2", - "GTPE2_LOGIC_OUTS_B17_7", - "GTPE2_CHANNEL_TXDATA0", - "GTPE2_LOGIC_OUTS_B15_0", - "GTPE2_IMUX7_5", - "GTPE2_IMUX24_4", - "GTPE2_IMUX7_7", - "GTPE2_LOGIC_OUTS_B3_9", - "GTPE2_LOGIC_OUTS_B17_4", - "GTPE2_FAN6_5", - "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "GTPE2_LOGIC_OUTS_B16_2", - "GTPE2_CHANNEL_TXMARGIN2", - "GTPE2_IMUX28_10", - "GTPE2_CHANNEL_DRPDI5", - "GTPE2_LOGIC_OUTS_B21_1", - "GTPE2_IMUX44_8", - "GTPE2_LOGIC_OUTS_B9_10", - "GTPE2_CHANNEL_TXCHARDISPVAL2", - "GTPE2_IMUX25_6", - "GTPE2_CHANNEL_SCANIN3", - "GTPE2_LOGIC_OUTS_B16_5", - "GTPE2_LOGIC_OUTS_B23_6", - "GTPE2_IMUX40_6", - "GTPE2_IMUX12_1", - "GTPE2_CHANNEL_DRPDO11", - "GTPE2_CHANNEL_RXADAPTSELTEST6", - "GTPE2_IMUX31_2", - "GTPE2_IMUX29_4", - "GTPE2_LOGIC_OUTS_B13_9", - "GTPE2_IMUX38_6", - "GTPE2_LOGIC_OUTS_B12_7", - "GTPE2_IMUX40_10", - "GTPE2_IMUX0_6", - "GTPE2_CHANNEL_TXPRECURSOR0", - "GTPE2_LOGIC_OUTS_B21_4", - "GTPE2_LOGIC_OUTS_B16_0", - "GTPE2_FAN7_1", - "GTPE2_CHANNEL_DRPDI14", - "GTPE2_LOGIC_OUTS_B5_7", - "GTPE2_IMUX39_1", - "GTPE2_IMUX15_7", - "GTPE2_IMUX6_1", - "GTPE2_CHANNEL_TXPD0", - "GTPE2_IMUX26_2", - "GTPE2_IMUX27_5", - "GTPE2_LOGIC_OUTS_B19_2", - "GTPE2_IMUX13_5", - "GTPE2_LOGIC_OUTS_B16_4", - "GTPE2_CHANNEL_TXHEADER1", - "GTPE2_CLK1_10", - "GTPE2_IMUX41_8", - "GTPE2_BYP4_9", - "GTPE2_IMUX5_7", - "GTPE2_CHANNEL_RXDATA15", - "GTPE2_BYP2_2", - "GTPE2_BYP7_10", - "GTPE2_LOGIC_OUTS_B22_6", - "GTPE2_IMUX16_4", - "GTPE2_BYP1_2", - "GTPE2_LOGIC_OUTS_B9_6", - "GTPE2_BYP1_4", - "GTPE2_IMUX23_2", - "GTPE2_IMUX1_1", - "GTPE2_IMUX0_8", - "GTPE2_LOGIC_OUTS_B13_5", - "GTPE2_CHANNEL_TXPHOVRDEN", - "GTPE2_LOGIC_OUTS_B7_2", - "GTPE2_CHANNEL_DMONITOROUT7", - "GTPE2_LOGIC_OUTS_B17_3", - "GTPE2_CHANNEL_RXELECIDLEMODE1", - "GTPE2_CHANNEL_RXDISPERR0", - "GTPE2_LOGIC_OUTS_B2_10", - "GTPE2_IMUX17_1", - "GTPE2_CHANNEL_TXDLYHOLD", - "GTPE2_BYP3_8", - "GTPE2_CHANNEL_RXOUTCLKPCS", - "GTPE2_IMUX32_8", - "GTPE2_CHANNEL_DRPADDR7", - "GTPE2_IMUX7_9", - "GTPE2_IMUX46_5", - "GTPE2_IMUX20_1", - "GTPE2_CHANNEL_DMONITOROUT9", - "GTPE2_CHANNEL_DRPDO15", - "GTPE2_IMUX23_0", - "GTPE2_IMUX15_3", - "GTPE2_CHANNEL_RXOSINTCFG3", - "GTPE2_CHANNEL_RXDATA0", - "GTPE2_IMUX36_1", - "GTPE2_LOGIC_OUTS_B23_8", - "GTPE2_IMUX37_2", - "GTPE2_CHANNEL_TXP_PAD", - "GTPE2_IMUX43_6", - "GTPE2_CHANNEL_RXDATA18", - "GTPE2_IMUX21_9", - "GTPE2_CLK1_4", - "GTPE2_CHANNEL_TXGEARBOXREADY", - "GTPE2_LOGIC_OUTS_B10_6", - "GTPE2_LOGIC_OUTS_B20_0", - "GTPE2_IMUX6_2", - "GTPE2_IMUX23_1", - "GTPE2_CHANNEL_TXPOSTCURSOR0", - "GTPE2_BYP5_4", - "GTPE2_CHANNEL_TXDATA14", - "GTPE2_CHANNEL_GTRSVD13", - "GTPE2_CHANNEL_TXSEQUENCE1", - "GTPE2_IMUX14_7", - "GTPE2_CHANNEL_TXPHINITDONE", - "GTPE2_CHANNEL_EYESCANMODE", - "GTPE2_CHANNEL_PLL0CLK", - "GTPE2_CHANNEL_TXDETECTRX", - "GTPE2_LOGIC_OUTS_B4_10", - "GTPE2_LOGIC_OUTS_B14_10", - "GTPE2_IMUX35_6", - "GTPE2_CHANNEL_TXOUTCLK_1", - "GTPE2_CHANNEL_RXDATA17", - "GTPE2_BYP7_7", - "GTPE2_CTRL0_8", - "GTPE2_CHANNEL_PLL1CLK", - "GTPE2_IMUX25_9", - "GTPE2_CHANNEL_CLKRSVD0", - "GTPE2_IMUX3_0", - "GTPE2_IMUX18_4", - "GTPE2_IMUX20_5", - "GTPE2_BYP1_5", - "GTPE2_IMUX42_4", - "GTPE2_LOGIC_OUTS_B22_10", - "GTPE2_IMUX7_0", - "GTPE2_CHANNEL_RXBYTEREALIGN", - "GTPE2_CHANNEL_RXDATA26", - "GTPE2_CHANNEL_RXPHMONITOR0", - "GTPE2_CHANNEL_PMASCANIN2", - "GTPE2_CHANNEL_RXPHALIGNEN", - "GTPE2_IMUX45_9", - "GTPE2_CTRL1_6", - "GTPE2_CHANNEL_RXOSINTNTRLEN", - "GTPE2_CHANNEL_SCANOUT5", - "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "GTPE2_CHANNEL_RXCOMSASDET", - "GTPE2_IMUX31_0", - "GTPE2_CHANNEL_TXDLYBYPASS", - "GTPE2_IMUX22_5", - "GTPE2_CHANNEL_RXDATA6", - "GTPE2_CHANNEL_TXPISOPD", - "GTPE2_CHANNEL_PCSRSVDIN15", - "GTPE2_IMUX3_8", - "GTPE2_CHANNEL_RXNOTINTABLE0", - "GTPE2_CHANNEL_RXADAPTSELTEST4", - "GTPE2_CHANNEL_TXMAINCURSOR0", - "GTPE2_CHANNEL_PCSRSVDOUT5", - "GTPE2_CHANNEL_TXDATA6", - "GTPE2_CHANNEL_RXOSINTSTARTED", - "GTPE2_IMUX10_10", - "GTPE2_LOGIC_OUTS_B2_8", - "GTPE2_LOGIC_OUTS_B4_8", - "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "GTPE2_BYP6_0", - "GTPE2_CHANNEL_RXOUTCLK_0", - "GTPE2_CHANNEL_RXOSINTCFG2", - "GTPE2_CHANNEL_GTRSVD4", - "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "GTPE2_LOGIC_OUTS_B14_2", - "GTPE2_CHANNEL_TSTIN14", - "GTPE2_CHANNEL_DMONITOROUT0", - "GTPE2_LOGIC_OUTS_B4_4", - "GTPE2_CHANNEL_DRPDO0", - "GTPE2_IMUX38_5", - "GTPE2_LOGIC_OUTS_B0_5", - "GTPE2_CHANNEL_RXRATE0", - "GTPE2_CHANNEL_RXCHANREALIGN", - "GTPE2_CHANNEL_RXCHBONDMASTER", - "GTPE2_FAN6_10", - "GTPE2_IMUX22_2", - "GTPE2_IMUX29_9", - "GTPE2_CHANNEL_RXDATA16", - "GTPE2_CHANNEL_RXADAPTSELTEST9", - "GTPE2_IMUX23_7", - "GTPE2_IMUX43_7", - "GTPE2_IMUX11_8", - "GTPE2_CHANNEL_TXDATA7", - "GTPE2_LOGIC_OUTS_B9_2", - "GTPE2_CHANNEL_TXPD1", - "GTPE2_FAN1_7", - "GTPE2_CHANNEL_RXDATA25", - "GTPE2_IMUX24_0", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "GTPE2_CHANNEL_SCANOUT2", - "GTPE2_IMUX10_8", - "GTPE2_CHANNEL_DRPDI0", - "GTPE2_CHANNEL_RXDATA5", - "GTPE2_CHANNEL_PCSRSVDIN4", - "GTPE2_BYP3_5", - "GTPE2_CHANNEL_DRPDO2", - "GTPE2_CHANNEL_DMONFIFORESET", - "GTPE2_IMUX39_3", - "GTPE2_LOGIC_OUTS_B10_7", - "GTPE2_BYP3_3", - "GTPE2_CHANNEL_TX8B10BBYPASS2", - "GTPE2_IMUX3_3", - "GTPE2_CHANNEL_RXDATA30", - "GTPE2_CHANNEL_TXOUTCLKSEL2", - "GTPE2_IMUX24_8", - "GTPE2_IMUX38_0", - "GTPE2_IMUX20_3", - "GTPE2_CHANNEL_TXRATEMODE", - "GTPE2_IMUX12_2", - "GTPE2_LOGIC_OUTS_B21_6", - "GTPE2_IMUX39_7", - "GTPE2_LOGIC_OUTS_B15_8", - "GTPE2_CHANNEL_RXPMARESETDONE", - "GTPE2_CHANNEL_RXPMARESET", - "GTPE2_IMUX39_8", - "GTPE2_IMUX6_6", - "GTPE2_CHANNEL_TXDATA22", - "GTPE2_CHANNEL_TXCHARISK1", - "GTPE2_FAN6_6", - "GTPE2_IMUX5_0", - "GTPE2_LOGIC_OUTS_B12_6", - "GTPE2_BYP4_0", - "GTPE2_CHANNEL_TSTIN12", - "GTPE2_IMUX11_6", - "GTPE2_LOGIC_OUTS_B3_1", - "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "GTPE2_IMUX45_8", - "GTPE2_FAN5_5", - "GTPE2_CHANNEL_TXOUTCLK_3", - "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "GTPE2_CHANNEL_PCSRSVDOUT4", - "GTPE2_IMUX9_2", - "GTPE2_IMUX35_10", - "GTPE2_CHANNEL_RX8B10BEN", - "GTPE2_CHANNEL_RXCDRFREQRESET", - "GTPE2_CHANNEL_RXGEARBOXSLIP", - "GTPE2_IMUX35_0", - "GTPE2_IMUX18_5", - "GTPE2_CHANNEL_RXCHARISCOMMA2", - "GTPE2_CHANNEL_SCANCLK", - "GTPE2_CHANNEL_TXDATA5", - "GTPE2_LOGIC_OUTS_B21_8", - "GTPE2_IMUX21_6", - "GTPE2_LOGIC_OUTS_B11_7", - "GTPE2_CHANNEL_RXPHOVRDEN", - "GTPE2_BYP4_4", - "GTPE2_IMUX5_5", - "GTPE2_LOGIC_OUTS_B3_5", - "GTPE2_LOGIC_OUTS_B17_9", - "GTPE2_FAN6_4", - "GTPE2_IMUX37_8", - "GTPE2_LOGIC_OUTS_B12_0", - "GTPE2_BYP2_6", - "GTPE2_IMUX7_2", - "GTPE2_CHANNEL_TSTPD4", - "GTPE2_CHANNEL_RXHEADER2", - "GTPE2_FAN7_7", - "GTPE2_IMUX26_0", - "GTPE2_CHANNEL_GTRSVD11", - "GTPE2_LOGIC_OUTS_B20_9", - "GTPE2_CHANNEL_TSTIN1", - "GTPE2_IMUX15_0", - "GTPE2_FAN0_6", - "GTPE2_CHANNEL_RXDATA14", - "GTPE2_LOGIC_OUTS_B22_2", - "GTPE2_IMUX5_3", - "GTPE2_IMUX41_3", - "GTPE2_LOGIC_OUTS_B9_8", - "GTPE2_CHANNEL_LOOPBACK0", - "GTPE2_LOGIC_OUTS_B18_7", - "GTPE2_LOGIC_OUTS_B16_1", - "GTPE2_IMUX38_8", - "GTPE2_IMUX15_5", - "GTPE2_CHANNEL_RXHEADER1", - "GTPE2_CHANNEL_TXPRBSSEL0", - "GTPE2_CHANNEL_RXLPMHFHOLD", - "GTPE2_LOGIC_OUTS_B8_9", - "GTPE2_BYP6_10", - "GTPE2_CLK1_7", - "GTPE2_CTRL1_1", - "GTPE2_CHANNEL_DRPADDR5", - "GTPE2_LOGIC_OUTS_B0_8", - "GTPE2_CHANNEL_TXDATA16", - "GTPE2_CHANNEL_GTRSVD6", - "GTPE2_CHANNEL_RXCHANBONDSEQ", - "GTPE2_IMUX18_7", - "GTPE2_LOGIC_OUTS_B5_2", - "GTPE2_BYP5_9", - "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "GTPE2_IMUX17_2", - "GTPE2_CHANNEL_TXSEQUENCE6", - "GTPE2_FAN6_8", - "GTPE2_IMUX34_9", - "GTPE2_CHANNEL_TXDLYEN", - "GTPE2_IMUX40_4", - "GTPE2_IMUX9_0", - "GTPE2_CHANNEL_TXDATA27", - "GTPE2_IMUX29_5", - "GTPE2_IMUX28_7", - "GTPE2_CHANNEL_PMASCANIN4", - "GTPE2_CHANNEL_PCSRSVDOUT6", - "GTPE2_IMUX43_8", - "GTPE2_IMUX40_7", - "GTPE2_LOGIC_OUTS_B23_10", - "GTPE2_IMUX45_5", - "GTPE2_IMUX4_1", - "GTPE2_IMUX10_1", - "GTPE2_IMUX37_0", - "GTPE2_BYP3_2", - "GTPE2_IMUX28_2", - "GTPE2_CHANNEL_TXDATA26", - "GTPE2_CHANNEL_TXDATA31", - "GTPE2_FAN0_10", - "GTPE2_LOGIC_OUTS_B7_9", - "GTPE2_BYP3_1", - "GTPE2_IMUX23_8", - "GTPE2_CHANNEL_RXCHARISK1", - "GTPE2_BYP5_6", - "GTPE2_CHANNEL_PHYSTATUS", - "GTPE2_CHANNEL_TXINHIBIT", - "GTPE2_CHANNEL_RXUSERRDY", - "GTPE2_IMUX24_6", - "GTPE2_CHANNEL_RXDATA23", - "GTPE2_IMUX13_10", - "GTPE2_IMUX34_3", - "GTPE2_CHANNEL_PMARSVDOUT1", - "GTPE2_IMUX5_4", - "GTPE2_CLK0_6", - "GTPE2_BYP5_8", - "GTPE2_IMUX18_10", - "GTPE2_FAN7_8", - "GTPE2_FAN5_2", - "GTPE2_CTRL0_6", - "GTPE2_CHANNEL_DRPDI10", - "GTPE2_FAN5_0", - "GTPE2_CHANNEL_RXCHARISK0", - "GTPE2_IMUX22_3", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "GTPE2_IMUX5_1", - "GTPE2_CHANNEL_DMONITOROUT1", - "GTPE2_IMUX33_5", - "GTPE2_CHANNEL_DRPDI9", - "GTPE2_CHANNEL_TXMARGIN1", - "GTPE2_IMUX10_3", - "GTPE2_CHANNEL_RXNOTINTABLE1", - "GTPE2_BYP6_9", - "GTPE2_IMUX5_2", - "GTPE2_IMUX38_4", - "GTPE2_IMUX46_4", - "GTPE2_CHANNEL_RXSYNCALLIN", - "GTPE2_CHANNEL_RXSTATUS1", - "GTPE2_IMUX12_7", - "GTPE2_FAN3_8", - "GTPE2_IMUX22_10", - "GTPE2_IMUX20_9", - "GTPE2_LOGIC_OUTS_B11_1", - "GTPE2_CHANNEL_PMASCANIN6", - "GTPE2_CHANNEL_TXSYNCIN", - "GTPE2_CHANNEL_TXSEQUENCE5", - "GTPE2_CHANNEL_TXDLYSRESETDONE", - "GTPE2_LOGIC_OUTS_B0_2", - "GTPE2_IMUX15_4", - "GTPE2_LOGIC_OUTS_B16_6", - "GTPE2_IMUX38_2", - "GTPE2_IMUX16_7", - "GTPE2_IMUX27_9", - "GTPE2_LOGIC_OUTS_B18_8", - "GTPE2_LOGIC_OUTS_B8_0", - "GTPE2_LOGIC_OUTS_B21_2", - "GTPE2_IMUX41_1", - "GTPE2_CHANNEL_TXUSRCLK", - "GTPE2_IMUX35_7", - "GTPE2_CHANNEL_TXMAINCURSOR5", - "GTPE2_CHANNEL_RXDLYSRESET", - "GTPE2_CHANNEL_DRPDI13", - "GTPE2_LOGIC_OUTS_B6_9", - "GTPE2_CHANNEL_RXOUTCLKSEL2", - "GTPE2_LOGIC_OUTS_B3_8", - "GTPE2_LOGIC_OUTS_B6_4", - "GTPE2_CHANNEL_DMONITOROUT11", - "GTPE2_LOGIC_OUTS_B2_7", - "GTPE2_IMUX6_3", - "GTPE2_IMUX20_0", - "GTPE2_IMUX12_10", - "GTPE2_CTRL0_10", - "GTPE2_CHANNEL_RXCOMMADET", - "GTPE2_CHANNEL_TXPOLARITY", - "GTPE2_CHANNEL_TXPRBSSEL2", - "GTPE2_LOGIC_OUTS_B5_4", - "GTPE2_IMUX37_1", - "GTPE2_CHANNEL_RXADAPTSELTEST13", - "GTPE2_IMUX27_7", - "GTPE2_IMUX44_9", - "GTPE2_IMUX36_10", - "GTPE2_FAN5_6", - "GTPE2_IMUX18_9", - "GTPE2_CLK1_3", - "GTPE2_IMUX26_10", - "GTPE2_IMUX32_6", - "GTPE2_IMUX36_6", - "GTPE2_IMUX14_5", - "GTPE2_LOGIC_OUTS_B18_1", - "GTPE2_IMUX46_9", - "GTPE2_CHANNEL_TXDLYSRESET", - "GTPE2_CHANNEL_RXCHARISK2", - "GTPE2_IMUX28_4", - "GTPE2_CHANNEL_PMARSVDIN2", - "GTPE2_CLK1_8", - "GTPE2_IMUX39_0", - "GTPE2_LOGIC_OUTS_B2_2", - "GTPE2_BYP6_4", - "GTPE2_IMUX30_2", - "GTPE2_LOGIC_OUTS_B10_4", - "GTPE2_CHANNEL_DRPADDR8", - "GTPE2_CHANNEL_DMONITOROUT4", - "GTPE2_IMUX19_6", - "GTPE2_FAN4_10", - "GTPE2_IMUX34_6", - "GTPE2_BYP4_3", - "GTPE2_CHANNEL_TX8B10BEN", - "GTPE2_LOGIC_OUTS_B11_6", - "GTPE2_IMUX28_6", - "GTPE2_CHANNEL_RXOSINTDONE", - "GTPE2_CHANNEL_TXOUTCLKSEL1", - "GTPE2_LOGIC_OUTS_B9_4", - "GTPE2_IMUX8_3", - "GTPE2_CHANNEL_DRPDI4", - "GTPE2_CHANNEL_TXSYSCLKSEL0", - "GTPE2_LOGIC_OUTS_B10_1", - "GTPE2_LOGIC_OUTS_B12_1", - "GTPE2_IMUX17_7", - "GTPE2_IMUX9_1", - "GTPE2_CHANNEL_PMASCANIN5", - "GTPE2_FAN0_3", - "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "GTPE2_BYP2_1", - "GTPE2_CHANNEL_RXOSINTSTROBE", - "GTPE2_IMUX40_8", - "GTPE2_IMUX3_10", - "GTPE2_CHANNEL_LOOPBACK2", - "GTPE2_IMUX35_1", - "GTPE2_LOGIC_OUTS_B19_6", - "GTPE2_CHANNEL_TXDATA25", - "GTPE2_IMUX40_2", - "GTPE2_IMUX8_2", - "GTPE2_CHANNEL_TXSYSCLKSEL1", - "GTPE2_IMUX36_2", - "GTPE2_CHANNEL_RXDLYOVRDEN", - "GTPE2_FAN3_0", - "GTPE2_CHANNEL_RXDATA20", - "GTPE2_IMUX22_7", - "GTPE2_IMUX35_8", - "GTPE2_CHANNEL_DRPDO3", - "GTPE2_CHANNEL_RXOUTCLKSEL0", - "GTPE2_LOGIC_OUTS_B11_3", - "GTPE2_CHANNEL_TXDIFFCTRL2", - "GTPE2_IMUX7_8", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "GTPE2_CHANNEL_RXDEBUGPULSE", - "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "GTPE2_CTRL0_1", - "GTPE2_CHANNEL_TXCHARDISPVAL3", - "GTPE2_LOGIC_OUTS_B2_6", - "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "GTPE2_BYP7_5", - "GTPE2_IMUX0_3", - "GTPE2_CHANNEL_TSTIN3", - "GTPE2_CHANNEL_DRPDI15", - "GTPE2_LOGIC_OUTS_B20_1", - "GTPE2_BYP2_7", - "GTPE2_CHANNEL_EYESCANDATAERROR", - "GTPE2_LOGIC_OUTS_B19_0", - "GTPE2_LOGIC_OUTS_B17_0", - "GTPE2_CHANNEL_RXOSINTCFG0", - "GTPE2_IMUX7_1", - "GTPE2_CHANNEL_RXELECIDLEMODE0", - "GTPE2_CHANNEL_DRPDO4", - "GTPE2_LOGIC_OUTS_B1_9", - "GTPE2_CHANNEL_RXSYNCDONE", - "GTPE2_CHANNEL_DRPADDR1", - "GTPE2_BYP6_8", - "GTPE2_IMUX0_1", - "GTPE2_CHANNEL_RXDATA28", - "GTPE2_IMUX6_8", - "GTPE2_IMUX10_4", - "GTPE2_IMUX46_2", - "GTPE2_IMUX35_2", - "GTPE2_IMUX33_6", - "GTPE2_IMUX7_10", - "GTPE2_CHANNEL_RXCDRRESETRSV", - "GTPE2_BYP7_1", - "GTPE2_CHANNEL_SCANENB", - "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "GTPE2_CHANNEL_TSTIN16", - "GTPE2_CHANNEL_TSTIN4", - "GTPE2_CHANNEL_TXDATA3", - "GTPE2_BYP5_7", - "GTPE2_LOGIC_OUTS_B20_10", - "GTPE2_IMUX33_8", - "GTPE2_CHANNEL_TSTPD2", - "GTPE2_IMUX27_8", - "GTPE2_CHANNEL_RXPHMONITOR4", - "GTPE2_CHANNEL_DRPDI8", - "GTPE2_LOGIC_OUTS_B19_10", - "GTPE2_CLK1_9", - "GTPE2_CHANNEL_TXRESETDONE", - "GTPE2_IMUX3_1", - "GTPE2_IMUX25_3", - "GTPE2_IMUX47_1", - "GTPE2_BYP5_0", - "GTPE2_CHANNEL_SCANIN2", - "GTPE2_IMUX33_1", - "GTPE2_LOGIC_OUTS_B14_3", - "GTPE2_CHANNEL_TXDATA20", - "GTPE2_IMUX26_7", - "GTPE2_LOGIC_OUTS_B4_1", - "GTPE2_BYP6_2", - "GTPE2_IMUX16_9", - "GTPE2_CHANNEL_RXSYSCLKSEL1", - "GTPE2_IMUX41_10", - "GTPE2_CHANNEL_RXCDRHOLD", - "GTPE2_BYP0_3", - "GTPE2_FAN2_9", - "GTPE2_CHANNEL_TXOUTCLKPCS", - "GTPE2_LOGIC_OUTS_B17_5", - "GTPE2_CHANNEL_PLLREFCLK0", - "GTPE2_LOGIC_OUTS_B16_9", - "GTPE2_IMUX37_6", - "GTPE2_CHANNEL_RXPRBSERR", - "GTPE2_LOGIC_OUTS_B11_4", - "GTPE2_IMUX14_0", - "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "GTPE2_CHANNEL_TXDATA29", - "GTPE2_LOGIC_OUTS_B14_7", - "GTPE2_LOGIC_OUTS_B1_1", - "GTPE2_IMUX17_9", - "GTPE2_IMUX21_3", - "GTPE2_LOGIC_OUTS_B14_4", - "GTPE2_CHANNEL_GTRSVD15", - "GTPE2_IMUX24_10", - "GTPE2_LOGIC_OUTS_B0_9", - "GTPE2_CHANNEL_PMASCANOUT6", - "GTPE2_IMUX4_6", - "GTPE2_CHANNEL_RXCHBONDO0", - "GTPE2_LOGIC_OUTS_B11_2", - "GTPE2_CHANNEL_RXADAPTSELTEST10", - "GTPE2_CHANNEL_RXOUTCLK_2", - "GTPE2_BYP4_8", - "GTPE2_CHANNEL_RXDATA4", - "GTPE2_CHANNEL_PCSRSVDIN0", - "GTPE2_CHANNEL_RXADAPTSELTEST2", - "GTPE2_LOGIC_OUTS_B14_1", - "GTPE2_CHANNEL_TXPRBSSEL1", - "GTPE2_LOGIC_OUTS_B15_3", - "GTPE2_LOGIC_OUTS_B13_0", - "GTPE2_CHANNEL_TXPRECURSORINV", - "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "GTPE2_CHANNEL_TXMAINCURSOR1", - "GTPE2_CHANNEL_RXOSINTOVRDEN", - "GTPE2_CHANNEL_TXDATA23", - "GTPE2_CHANNEL_TXRUNDISP0", - "GTPE2_LOGIC_OUTS_B4_2", - "GTPE2_BYP0_4", - "GTPE2_BYP3_6", - "GTPE2_LOGIC_OUTS_B9_5", - "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "GTPE2_CTRL1_10", - "GTPE2_CHANNEL_RXOSINTID02", - "GTPE2_IMUX16_2", - "GTPE2_CHANNEL_RXRATEDONE", - "GTPE2_BYP0_0", - "GTPE2_CHANNEL_TXCOMWAKE", - "GTPE2_IMUX43_3", - "GTPE2_LOGIC_OUTS_B13_7", - "GTPE2_CHANNEL_TXPOSTCURSOR4", - "GTPE2_IMUX22_4", - "GTPE2_IMUX21_1", - "GTPE2_FAN1_9", - "GTPE2_IMUX29_7", - "GTPE2_LOGIC_OUTS_B8_6", - "GTPE2_BYP7_8", - "GTPE2_IMUX23_5", - "GTPE2_CHANNEL_DRPDO10", - "GTPE2_CHANNEL_DRPDI6", - "GTPE2_IMUX32_1", - "GTPE2_IMUX22_8", - "GTPE2_FAN7_0", - "GTPE2_CHANNEL_RXLPMRESET", - "GTPE2_IMUX13_2", - "GTPE2_CHANNEL_PCSRSVDIN10", - "GTPE2_IMUX46_1", - "GTPE2_CHANNEL_TSTIN18", - "GTPE2_CHANNEL_TXPHDLYRESET", - "GTPE2_FAN6_3", - "GTPE2_CHANNEL_DMONITOROUT3", - "GTPE2_IMUX41_0", - "GTPE2_IMUX13_6", - "GTPE2_IMUX11_1", - "GTPE2_CHANNEL_PCSRSVDOUT9", - "GTPE2_CHANNEL_DRPEN", - "GTPE2_IMUX38_10", - "GTPE2_CHANNEL_TSTPDOVRDB", - "GTPE2_BYP2_8", - "GTPE2_CTRL1_0", - "GTPE2_IMUX2_5", - "GTPE2_CHANNEL_RXDLYEN", - "GTPE2_LOGIC_OUTS_B6_1", - "GTPE2_FAN7_10", - "GTPE2_IMUX17_0", - "GTPE2_CHANNEL_TSTIN19", - "GTPE2_IMUX29_8", - "GTPE2_IMUX11_5", - "GTPE2_LOGIC_OUTS_B22_5", - "GTPE2_CHANNEL_RXDATA3", - "GTPE2_CHANNEL_RXOSINTCFG1", - "GTPE2_IMUX24_5", - "GTPE2_CHANNEL_GTRSVD10", - "GTPE2_LOGIC_OUTS_B20_5", - "GTPE2_LOGIC_OUTS_B20_3", - "GTPE2_CHANNEL_TXSYNCDONE", - "GTPE2_BYP0_6", - "GTPE2_LOGIC_OUTS_B1_0", - "GTPE2_LOGIC_OUTS_B1_4", - "GTPE2_IMUX42_9", - "GTPE2_BYP6_5", - "GTPE2_IMUX47_5", - "GTPE2_CHANNEL_LOOPBACK1", - "GTPE2_IMUX13_9", - "GTPE2_CHANNEL_TXPHALIGNEN", - "GTPE2_IMUX12_4", - "GTPE2_CHANNEL_RXADAPTSELTEST11", - "GTPE2_IMUX44_6", - "GTPE2_CHANNEL_TXELECIDLE", - "GTPE2_CTRL0_0", - "GTPE2_LOGIC_OUTS_B3_7", - "GTPE2_IMUX35_4", - "GTPE2_CHANNEL_RXCHBONDI0", - "GTPE2_CHANNEL_TXCHARDISPMODE1", - "GTPE2_LOGIC_OUTS_B7_10", - "GTPE2_CHANNEL_RXOSINTEN", - "GTPE2_LOGIC_OUTS_B21_3", - "GTPE2_CHANNEL_TXDATA15", - "GTPE2_BYP0_7", - "GTPE2_IMUX2_6", - "GTPE2_BYP3_10", - "GTPE2_FAN1_1", - "GTPE2_CHANNEL_TSTIN6", - "GTPE2_FAN1_4", - "GTPE2_IMUX14_2", - "GTPE2_CHANNEL_PMASCANIN3", - "GTPE2_CHANNEL_TXDATA18", - "GTPE2_IMUX0_4", - "GTPE2_CHANNEL_TSTIN17", - "GTPE2_LOGIC_OUTS_B3_4", - "GTPE2_LOGIC_OUTS_B1_8", - "GTPE2_BYP1_8", - "GTPE2_CHANNEL_RXSTATUS2", - "GTPE2_BYP5_2", - "GTPE2_CHANNEL_PCSRSVDIN11", - "GTPE2_IMUX38_9", - "GTPE2_BYP7_6", - "GTPE2_CHANNEL_PMASCANCLK1", - "GTPE2_CHANNEL_RXBUFSTATUS0", - "GTPE2_IMUX11_0", - "GTPE2_FAN4_9", - "GTPE2_LOGIC_OUTS_B12_8", - "GTPE2_BYP1_3", - "GTPE2_BYP0_10", - "GTPE2_CHANNEL_RXOSCALRESET", - "GTPE2_IMUX6_0", - "GTPE2_CHANNEL_TSTIN11", - "GTPE2_CLK0_3", - "GTPE2_CHANNEL_CLKRSVD1", - "GTPE2_FAN3_10", - "GTPE2_IMUX19_0", - "GTPE2_CHANNEL_RXHEADER0", - "GTPE2_CHANNEL_TXPRBSFORCEERR", - "GTPE2_CHANNEL_PCSRSVDIN13", - "GTPE2_IMUX46_7", - "GTPE2_CHANNEL_PCSRSVDOUT14", - "GTPE2_LOGIC_OUTS_B15_10", - "GTPE2_CHANNEL_TSTPD3", - "GTPE2_LOGIC_OUTS_B12_2", - "GTPE2_IMUX45_1", - "GTPE2_IMUX0_0", - "GTPE2_IMUX39_10", - "GTPE2_CHANNEL_DMONITOROUT10", - "GTPE2_CHANNEL_RXCDRLOCK", - "GTPE2_IMUX4_2", - "GTPE2_CHANNEL_TXMAINCURSOR2", - "GTPE2_CHANNEL_PCSRSVDIN9", - "GTPE2_IMUX10_5", - "GTPE2_CHANNEL_PMASCANCLK0", - "GTPE2_IMUX18_8", - "GTPE2_CHANNEL_TXSYNCMODE", - "GTPE2_CHANNEL_TXN_PAD", - "GTPE2_CHANNEL_TXPMARESET", - "GTPE2_IMUX43_10", - "GTPE2_BYP5_10", - "GTPE2_CHANNEL_DRPADDR0", - "GTPE2_CHANNEL_PCSRSVDOUT1", - "GTPE2_CHANNEL_PMARSVDIN4", - "GTPE2_IMUX14_1", - "GTPE2_CHANNEL_SCANIN5", - "GTPE2_LOGIC_OUTS_B0_1", - "GTPE2_CHANNEL_PCSRSVDOUT12", - "GTPE2_CHANNEL_DRPDI7", - "GTPE2_IMUX26_6", - "GTPE2_IMUX17_6", - "GTPE2_LOGIC_OUTS_B1_7", - "GTPE2_CHANNEL_RXDATA7", - "GTPE2_CHANNEL_TXCHARDISPMODE3", - "GTPE2_IMUX26_8", - "GTPE2_IMUX0_9", - "GTPE2_FAN3_6", - "GTPE2_IMUX46_0", - "GTPE2_CHANNEL_TSTIN7", - "GTPE2_LOGIC_OUTS_B20_7", - "GTPE2_LOGIC_OUTS_B17_2", - "GTPE2_CHANNEL_TXCHARDISPVAL1", - "GTPE2_CHANNEL_TXSEQUENCE4", - "GTPE2_CHANNEL_TXPOSTCURSOR2", - "GTPE2_CHANNEL_DRPDI2", - "GTPE2_FAN2_10", - "GTPE2_CHANNEL_RXBUFSTATUS2", - "GTPE2_IMUX1_7", - "GTPE2_CHANNEL_GTTXOUTCLK_1", - "GTPE2_CHANNEL_SCANOUT4", - "GTPE2_IMUX10_7", - "GTPE2_LOGIC_OUTS_B18_0", - "GTPE2_CHANNEL_DRPDO9", - "GTPE2_FAN6_9", - "GTPE2_IMUX4_7", - "GTPE2_CHANNEL_TSTPD1", - "GTPE2_IMUX39_6", - "GTPE2_CHANNEL_TXPRECURSOR2", - "GTPE2_IMUX43_0", - "GTPE2_FAN1_6", - "GTPE2_BYP1_1", - "GTPE2_FAN5_3", - "GTPE2_CHANNEL_DMONITOROUT2", - "GTPE2_LOGIC_OUTS_B19_4", - "GTPE2_CHANNEL_PMASCANMODEB", - "GTPE2_IMUX37_9", - "GTPE2_LOGIC_OUTS_B22_3", - "GTPE2_FAN1_3", - "GTPE2_IMUX5_9", - "GTPE2_CHANNEL_RXELECIDLE", - "GTPE2_IMUX34_8", - "GTPE2_FAN2_4", - "GTPE2_IMUX24_2", - "GTPE2_LOGIC_OUTS_B22_4", - "GTPE2_IMUX34_4", - "GTPE2_LOGIC_OUTS_B0_10", - "GTPE2_IMUX29_6", - "GTPE2_IMUX45_10", - "GTPE2_CLK1_6", - "GTPE2_CHANNEL_PMASCANENB", - "GTPE2_CHANNEL_TXDATA8", - "GTPE2_CLK0_7", - "GTPE2_IMUX30_1", - "GTPE2_LOGIC_OUTS_B11_8", - "GTPE2_CHANNEL_RXHEADERVALID", - "GTPE2_FAN5_1", - "GTPE2_CHANNEL_PCSRSVDOUT3", - "GTPE2_IMUX2_9", - "GTPE2_CHANNEL_TXPIPPMPD", - "GTPE2_IMUX44_5", - "GTPE2_IMUX22_0", - "GTPE2_CHANNEL_TXPIPPMEN", - "GTPE2_FAN5_10", - "GTPE2_BYP1_0", - "GTPE2_IMUX11_7", - "GTPE2_CHANNEL_TXDATA10", - "GTPE2_IMUX34_2", - "GTPE2_LOGIC_OUTS_B4_0", - "GTPE2_CHANNEL_GTRSVD5", - "GTPE2_LOGIC_OUTS_B8_7", - "GTPE2_IMUX44_4", - "GTPE2_IMUX41_5", - "GTPE2_CHANNEL_TXDLYOVRDEN", - "GTPE2_IMUX37_4", - "GTPE2_BYP6_6", - "GTPE2_IMUX44_10", - "GTPE2_CHANNEL_DRPADDR2", - "GTPE2_CLK0_5", - "GTPE2_CHANNEL_DRPDI11", - "GTPE2_LOGIC_OUTS_B7_1", - "GTPE2_IMUX8_0", - "GTPE2_IMUX25_4", - "GTPE2_LOGIC_OUTS_B7_8", - "GTPE2_CHANNEL_TXBUFSTATUS0", - "GTPE2_IMUX30_3", - "GTPE2_IMUX27_4", - "GTPE2_LOGIC_OUTS_B8_8", - "GTPE2_CHANNEL_DRPADDR6", - "GTPE2_IMUX0_7", - "GTPE2_IMUX42_8", - "GTPE2_IMUX33_4", - "GTPE2_BYP0_9", - "GTPE2_LOGIC_OUTS_B6_0", - "GTPE2_LOGIC_OUTS_B22_8", - "GTPE2_CHANNEL_RXOSINTID01", - "GTPE2_IMUX40_5", - "GTPE2_CHANNEL_DRPDO6", - "GTPE2_CHANNEL_RXSYSCLKSEL0", - "GTPE2_CLK1_2", - "GTPE2_FAN5_9", - "GTPE2_IMUX6_10", - "GTPE2_LOGIC_OUTS_B12_4", - "GTPE2_IMUX13_7", - "GTPE2_IMUX25_7", - "GTPE2_IMUX7_3", - "GTPE2_BYP7_9", - "GTPE2_CHANNEL_RXCHBONDO2", - "GTPE2_LOGIC_OUTS_B17_1", - "GTPE2_LOGIC_OUTS_B15_2", - "GTPE2_CHANNEL_PCSRSVDIN5", - "GTPE2_LOGIC_OUTS_B5_0", - "GTPE2_LOGIC_OUTS_B3_10", - "GTPE2_CHANNEL_DRPDI12", - "GTPE2_IMUX23_9", - "GTPE2_LOGIC_OUTS_B9_0", - "GTPE2_IMUX7_4", - "GTPE2_CHANNEL_TSTIN0", - "GTPE2_FAN5_8", - "GTPE2_LOGIC_OUTS_B13_1", - "GTPE2_IMUX32_0", - "GTPE2_CHANNEL_RXPRBSSEL2", - "GTPE2_IMUX45_2", - "GTPE2_CHANNEL_DRPDI1", - "GTPE2_CHANNEL_TXDATA19", - "GTPE2_FAN6_7", - "GTPE2_CHANNEL_RXDATA11", - "GTPE2_CHANNEL_RXCOMMADETEN", - "GTPE2_CHANNEL_TXN", - "GTPE2_CHANNEL_TXRATEDONE", - "GTPE2_IMUX39_5", - "GTPE2_FAN0_2", - "GTPE2_IMUX18_0", - "GTPE2_IMUX16_10", - "GTPE2_CHANNEL_PMASCANOUT0", - "GTPE2_CHANNEL_PMASCANIN1", - "GTPE2_LOGIC_OUTS_B13_3", - "GTPE2_IMUX36_0", - "GTPE2_BYP7_4", - "GTPE2_CHANNEL_RXPOLARITY", - "GTPE2_LOGIC_OUTS_B7_0", - "GTPE2_CHANNEL_DRPDO8", - "GTPE2_LOGIC_OUTS_B0_0", - "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "GTPE2_IMUX4_3", - "GTPE2_CHANNEL_SCANOUT1", - "GTPE2_CHANNEL_PCSRSVDOUT15", - "GTPE2_CHANNEL_TXOUTCLKSEL0", - "GTPE2_CHANNEL_DRPCLK", - "GTPE2_LOGIC_OUTS_B20_4", - "GTPE2_LOGIC_OUTS_B15_6", - "GTPE2_LOGIC_OUTS_B13_4", - "GTPE2_BYP2_0", - "GTPE2_IMUX9_7", - "GTPE2_IMUX11_9", - "GTPE2_IMUX2_10", - "GTPE2_IMUX9_4", - "GTPE2_IMUX3_6", - "GTPE2_CHANNEL_RXDATA19", - "GTPE2_LOGIC_OUTS_B23_0", - "GTPE2_CHANNEL_SCANIN1", - "GTPE2_IMUX8_1", - "GTPE2_CHANNEL_TXPIPPMSEL", - "GTPE2_IMUX13_0", - "GTPE2_IMUX30_10", - "GTPE2_BYP4_7", - "GTPE2_LOGIC_OUTS_B23_7", - "GTPE2_CHANNEL_EYESCANRESET", - "GTPE2_IMUX30_9", - "GTPE2_IMUX37_7", - "GTPE2_IMUX25_8", - "GTPE2_FAN4_0", - "GTPE2_IMUX38_7", - "GTPE2_FAN5_4", - "GTPE2_FAN1_2", - "GTPE2_IMUX22_6", - "GTPE2_CHANNEL_TX8B10BBYPASS3", - "GTPE2_IMUX2_7", - "GTPE2_LOGIC_OUTS_B5_5", - "GTPE2_IMUX26_1", - "GTPE2_IMUX42_5", - "GTPE2_CHANNEL_TXMARGIN0", - "GTPE2_CHANNEL_RXDATA12", - "GTPE2_IMUX9_5", - "GTPE2_CHANNEL_TX8B10BBYPASS1", - "GTPE2_LOGIC_OUTS_B11_5", - "GTPE2_CLK0_1", - "GTPE2_IMUX31_8", - "GTPE2_LOGIC_OUTS_B18_9", - "GTPE2_FAN0_4", - "GTPE2_IMUX9_8", - "GTPE2_CHANNEL_DRPDI3", - "GTPE2_LOGIC_OUTS_B8_5", - "GTPE2_LOGIC_OUTS_B16_10", - "GTPE2_BYP1_6", - "GTPE2_IMUX47_0", - "GTPE2_CHANNEL_RXNOTINTABLE3", - "GTPE2_IMUX42_10", - "GTPE2_IMUX8_4", - "GTPE2_CHANNEL_RXDATA10", - "GTPE2_CHANNEL_RXRATE1", - "GTPE2_IMUX47_10", - "GTPE2_CHANNEL_TXSEQUENCE3", - "GTPE2_IMUX38_3", - "GTPE2_IMUX43_4", - "GTPE2_CHANNEL_TXRUNDISP1", - "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "GTPE2_BYP3_4", - "GTPE2_FAN4_5", - "GTPE2_BYP0_5", - "GTPE2_IMUX32_2", - "GTPE2_FAN4_7", - "GTPE2_IMUX3_4", - "GTPE2_CHANNEL_TXDATA9", - "GTPE2_FAN2_3", - "GTPE2_CHANNEL_PLLREFCLK1", - "GTPE2_LOGIC_OUTS_B0_6", - "GTPE2_LOGIC_OUTS_B23_1", - "GTPE2_IMUX45_4", - "GTPE2_CHANNEL_RXADAPTSELTEST0", - "GTPE2_LOGIC_OUTS_B15_1", - "GTPE2_BYP1_10", - "GTPE2_LOGIC_OUTS_B0_7", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", - "GTPE2_IMUX27_10", - "GTPE2_IMUX32_7", - "GTPE2_BYP3_9", - "GTPE2_CHANNEL_PMASCANCLK2", - "GTPE2_LOGIC_OUTS_B21_0", - "GTPE2_IMUX20_10", - "GTPE2_CHANNEL_RXPHMONITOR1", - "GTPE2_IMUX15_6", - "GTPE2_IMUX1_8", - "GTPE2_IMUX33_9", - "GTPE2_IMUX12_8", - "GTPE2_IMUX28_0", - "GTPE2_CHANNEL_RXDATA31", - "GTPE2_IMUX31_4", - "GTPE2_CTRL1_8", - "GTPE2_LOGIC_OUTS_B14_0", - "GTPE2_CHANNEL_RXDLYTESTENB", - "GTPE2_CHANNEL_TXP", - "GTPE2_IMUX33_10", - "GTPE2_IMUX9_10", - "GTPE2_IMUX34_1", - "GTPE2_LOGIC_OUTS_B18_5", - "GTPE2_FAN3_4", - "GTPE2_BYP5_5", - "GTPE2_CHANNEL_RXP", - "GTPE2_LOGIC_OUTS_B6_7", - "GTPE2_FAN3_1", - "GTPE2_IMUX8_10", - "GTPE2_IMUX26_9", - "GTPE2_FAN7_5", - "GTPE2_IMUX1_10", - "GTPE2_IMUX1_3", - "GTPE2_CHANNEL_RXDATA13", - "GTPE2_CHANNEL_TXSWING", - "GTPE2_CHANNEL_PLLCLK0", - "GTPE2_CHANNEL_PCSRSVDOUT11", - "GTPE2_FAN2_7", - "GTPE2_IMUX21_2", - "GTPE2_CHANNEL_RXCLKCORCNT1", - "GTPE2_CHANNEL_TXDIFFCTRL1", - "GTPE2_IMUX21_4", - "GTPE2_LOGIC_OUTS_B22_9", - "GTPE2_IMUX39_2", - "GTPE2_IMUX19_9", - "GTPE2_IMUX40_0", - "GTPE2_CHANNEL_TSTPD0", - "GTPE2_CHANNEL_TXCHARISK2", - "GTPE2_CHANNEL_RXSTATUS0", - "GTPE2_IMUX19_5", - "GTPE2_IMUX11_2", - "GTPE2_CHANNEL_PMASCANOUT2", - "GTPE2_LOGIC_OUTS_B11_10", - "GTPE2_IMUX38_1", - "GTPE2_CHANNEL_RXCOMWAKEDET", - "GTPE2_CHANNEL_TSTIN13", - "GTPE2_IMUX1_6", - "GTPE2_CHANNEL_RXCDROVRDEN", - "GTPE2_LOGIC_OUTS_B8_2", - "GTPE2_LOGIC_OUTS_B20_8", - "GTPE2_CHANNEL_DMONITOROUT5", - "GTPE2_IMUX35_9", - "GTPE2_IMUX27_0", - "GTPE2_LOGIC_OUTS_B7_4", - "GTPE2_IMUX30_0", - "GTPE2_IMUX23_3", - "GTPE2_CHANNEL_RXN", - "GTPE2_IMUX42_6", - "GTPE2_IMUX14_3", - "GTPE2_IMUX16_3", - "GTPE2_LOGIC_OUTS_B5_10", - "GTPE2_BYP4_10", - "GTPE2_CHANNEL_TXPOSTCURSORINV", - "GTPE2_CHANNEL_DRPDO12", - "GTPE2_IMUX35_5", - "GTPE2_IMUX21_10", - "GTPE2_BYP4_6", - "GTPE2_CHANNEL_RXADAPTSELTEST5", - "GTPE2_IMUX23_4", - "GTPE2_LOGIC_OUTS_B16_7", - "GTPE2_BYP2_4", - "GTPE2_IMUX27_3", - "GTPE2_CLK1_0", - "GTPE2_IMUX13_3", - "GTPE2_IMUX43_2", - "GTPE2_FAN2_0", - "GTPE2_CTRL0_4", - "GTPE2_IMUX21_0", - "GTPE2_LOGIC_OUTS_B12_5", - "GTPE2_CHANNEL_GTRSVD0", - "GTPE2_IMUX47_3", - "GTPE2_IMUX4_5", - "GTPE2_CHANNEL_TXPCSRESET", - "GTPE2_IMUX47_2", - "GTPE2_CLK0_2", - "GTPE2_CHANNEL_RXBUFSTATUS1", - "GTPE2_CTRL0_3", - "GTPE2_IMUX47_7", - "GTPE2_IMUX39_4", - "GTPE2_IMUX42_7", - "GTPE2_IMUX17_3", - "GTPE2_LOGIC_OUTS_B7_7", - "GTPE2_IMUX10_9", - "GTPE2_CHANNEL_TXSTARTSEQ", - "GTPE2_CHANNEL_TXSEQUENCE2", - "GTPE2_CHANNEL_GTTXRESET", - "GTPE2_IMUX21_8", - "GTPE2_CHANNEL_TXRUNDISP3", - "GTPE2_FAN4_6", - "GTPE2_CHANNEL_TXDATA28", - "GTPE2_CHANNEL_TSTIN9", - "GTPE2_CHANNEL_RXUSRCLK2", - "GTPE2_CHANNEL_RXCHARISCOMMA3", - "GTPE2_IMUX8_9", - "GTPE2_CHANNEL_RXPD1", - "GTPE2_LOGIC_OUTS_B7_3", - "GTPE2_CHANNEL_TXCOMINIT", - "GTPE2_LOGIC_OUTS_B15_9", - "GTPE2_FAN0_8", - "GTPE2_BYP3_0", - "GTPE2_IMUX6_9", - "GTPE2_CHANNEL_DRPDO13", - "GTPE2_CTRL1_9", - "GTPE2_LOGIC_OUTS_B22_7", - "GTPE2_IMUX40_3", - "GTPE2_LOGIC_OUTS_B20_2", - "GTPE2_FAN4_3", - "GTPE2_IMUX1_0", - "GTPE2_LOGIC_OUTS_B19_8", - "GTPE2_LOGIC_OUTS_B3_3", - "GTPE2_IMUX34_7", - "GTPE2_IMUX0_10", - "GTPE2_CHANNEL_TXRUNDISP2", - "GTPE2_IMUX19_7", - "GTPE2_LOGIC_OUTS_B19_7", - "GTPE2_CHANNEL_RXBUFRESET", - "GTPE2_CHANNEL_RXSYNCOUT", - "GTPE2_IMUX12_9", - "GTPE2_IMUX15_9", - "GTPE2_LOGIC_OUTS_B6_6", - "GTPE2_CTRL1_4", - "GTPE2_CTRL0_9", - "GTPE2_IMUX33_0", - "GTPE2_IMUX11_3", - "GTPE2_FAN0_1", - "GTPE2_IMUX32_5", - "GTPE2_IMUX42_3", - "GTPE2_LOGIC_OUTS_B14_8", - "GTPE2_CHANNEL_TXCHARDISPMODE2", - "GTPE2_IMUX7_6", - "GTPE2_FAN4_1", - "GTPE2_CHANNEL_RXN_PAD", - "GTPE2_CHANNEL_DRPADDR3", - "GTPE2_IMUX23_6", - "GTPE2_BYP7_3", - "GTPE2_BYP5_1", - "GTPE2_CHANNEL_TXPHDLYPD", - "GTPE2_IMUX41_9", - "GTPE2_BYP4_2", - "GTPE2_IMUX22_1", - "GTPE2_LOGIC_OUTS_B3_2", - "GTPE2_CHANNEL_DMONITOROUT8", - "GTPE2_CHANNEL_DRPRDY", - "GTPE2_IMUX45_7", - "GTPE2_BYP7_0", - "GTPE2_IMUX3_2", - "GTPE2_IMUX18_3", - "GTPE2_IMUX4_9", - "GTPE2_IMUX19_10", - "GTPE2_IMUX3_9", - "GTPE2_CHANNEL_RXDATA22", - "GTPE2_FAN4_2", - "GTPE2_IMUX17_5", - "GTPE2_CHANNEL_GTRSVD7", - "GTPE2_IMUX25_2", - "GTPE2_LOGIC_OUTS_B4_3", - "GTPE2_LOGIC_OUTS_B5_3", - "GTPE2_CHANNEL_CFGRESET", - "GTPE2_IMUX27_6", - "GTPE2_IMUX24_9", - "GTPE2_IMUX23_10", - "GTPE2_CHANNEL_TXPRECURSOR3", - "GTPE2_CHANNEL_PMASCANCLK3", - "GTPE2_BYP1_7", - "GTPE2_FAN1_5", - "GTPE2_LOGIC_OUTS_B0_3", - "GTPE2_LOGIC_OUTS_B18_10", - "GTPE2_CHANNEL_TXSYNCOUT", - "GTPE2_IMUX28_5", - "GTPE2_IMUX16_0", - "GTPE2_BYP2_10", - "GTPE2_IMUX36_8", - "GTPE2_CLK1_1", - "GTPE2_CHANNEL_TXDATA24", - "GTPE2_IMUX32_10", - "GTPE2_LOGIC_OUTS_B12_10", - "GTPE2_LOGIC_OUTS_B23_9", - "GTPE2_IMUX24_7", - "GTPE2_LOGIC_OUTS_B21_9", - "GTPE2_IMUX37_3", - "GTPE2_CHANNEL_RXCHBONDI3", - "GTPE2_LOGIC_OUTS_B6_8", - "GTPE2_LOGIC_OUTS_B16_3", - "GTPE2_FAN5_7", - "GTPE2_BYP0_2", - "GTPE2_CHANNEL_RXCHBONDEN", - "GTPE2_IMUX9_9", - "GTPE2_CHANNEL_TSTIN5", - "GTPE2_CHANNEL_PCSRSVDIN1", - "GTPE2_CHANNEL_RXSLIDE", - "GTPE2_IMUX25_0", - "GTPE2_CHANNEL_RXDATA2", - "GTPE2_IMUX5_10", - "GTPE2_CHANNEL_PLL1REFCLK", - "GTPE2_IMUX6_7", - "GTPE2_LOGIC_OUTS_B18_4", - "GTPE2_CHANNEL_RXRESETDONE", - "GTPE2_CHANNEL_GTRSVD2", - "GTPE2_CHANNEL_TXPOSTCURSOR1", - "GTPE2_CHANNEL_RXDFEXYDEN", - "GTPE2_IMUX44_1", - "GTPE2_LOGIC_OUTS_B19_1", - "GTPE2_IMUX28_3", - "GTPE2_IMUX9_3", - "GTPE2_BYP2_3", - "GTPE2_LOGIC_OUTS_B1_10", - "GTPE2_CHANNEL_GTRSVD14", - "GTPE2_CHANNEL_TXPRECURSOR1", - "GTPE2_CHANNEL_RXCLKCORCNT0", - "GTPE2_CTRL0_5", - "GTPE2_CHANNEL_PCSRSVDOUT2", - "GTPE2_FAN7_9", - "GTPE2_LOGIC_OUTS_B12_3", - "GTPE2_IMUX20_8", - "GTPE2_CHANNEL_GTRSVD12", - "GTPE2_IMUX35_3", - "GTPE2_CTRL1_5", - "GTPE2_CHANNEL_EYESCANTRIGGER", - "GTPE2_CHANNEL_TXDATA30", - "GTPE2_IMUX26_3", - "GTPE2_FAN0_0", - "GTPE2_CHANNEL_RXCDRRESET" - ], - "sites": [ - { - "prefix": "GTPE2_CHANNEL", - "y_coord": 0, - "type": "GTPE2_CHANNEL", - "site_pins": { - "RXCHARISCOMMA3": "GTPE2_CHANNEL_RXCHARISCOMMA3", - "RXSTATUS0": "GTPE2_CHANNEL_RXSTATUS0", - "DRPDO13": "GTPE2_CHANNEL_DRPDO13", - "TSTPD0": "GTPE2_CHANNEL_TSTPD0", - "RXBUFRESET": "GTPE2_CHANNEL_RXBUFRESET", - "RXVALID": "GTPE2_CHANNEL_RXVALID", - "SCANIN1": "GTPE2_CHANNEL_SCANIN1", - "RXCHBONDLEVEL2": "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "TXDATA25": "GTPE2_CHANNEL_TXDATA25", - "GTPRXN": "GTPE2_CHANNEL_RXN", - "PCSRSVDOUT6": "GTPE2_CHANNEL_PCSRSVDOUT6", - "TXDATA31": "GTPE2_CHANNEL_TXDATA31", - "CFGRESET": "GTPE2_CHANNEL_CFGRESET", - "GTPTXP": "GTPE2_CHANNEL_TXP", - "TXPIPPMEN": "GTPE2_CHANNEL_TXPIPPMEN", - "TXDATA14": "GTPE2_CHANNEL_TXDATA14", - "TXRATE0": "GTPE2_CHANNEL_TXRATE0", - "DMONITOROUT6": "GTPE2_CHANNEL_DMONITOROUT6", - "PMASCANOUT5": "GTPE2_CHANNEL_PMASCANOUT5", - "RXDATA28": "GTPE2_CHANNEL_RXDATA28", - "TXOUTCLK": "GTPE2_CHANNEL_GTTXOUTCLK_1", - "RXCHANBONDSEQ": "GTPE2_CHANNEL_RXCHANBONDSEQ", - "DRPDI4": "GTPE2_CHANNEL_DRPDI4", - "TXDATA15": "GTPE2_CHANNEL_TXDATA15", - "RXDATA26": "GTPE2_CHANNEL_RXDATA26", - "TXHEADER1": "GTPE2_CHANNEL_TXHEADER1", - "RXCHBONDLEVEL1": "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "RXNOTINTABLE1": "GTPE2_CHANNEL_RXNOTINTABLE1", - "RXPD0": "GTPE2_CHANNEL_RXPD0", - "DMONITOROUT14": "GTPE2_CHANNEL_DMONITOROUT14", - "TXBUFSTATUS1": "GTPE2_CHANNEL_TXBUFSTATUS1", - "TXCOMSAS": "GTPE2_CHANNEL_TXCOMSAS", - "RXCDRRESETRSV": "GTPE2_CHANNEL_RXCDRRESETRSV", - "RXSTATUS2": "GTPE2_CHANNEL_RXSTATUS2", - "RXOSINTCFG2": "GTPE2_CHANNEL_RXOSINTCFG2", - "PCSRSVDIN11": "GTPE2_CHANNEL_PCSRSVDIN11", - "PHYSTATUS": "GTPE2_CHANNEL_PHYSTATUS", - "RXGEARBOXSLIP": "GTPE2_CHANNEL_RXGEARBOXSLIP", - "DMONITOROUT3": "GTPE2_CHANNEL_DMONITOROUT3", - "TXMAINCURSOR1": "GTPE2_CHANNEL_TXMAINCURSOR1", - "GTRSVD11": "GTPE2_CHANNEL_GTRSVD11", - "DMONITOROUT7": "GTPE2_CHANNEL_DMONITOROUT7", - "TXSYNCDONE": "GTPE2_CHANNEL_TXSYNCDONE", - "PCSRSVDIN6": "GTPE2_CHANNEL_PCSRSVDIN6", - "RXBYTEISALIGNED": "GTPE2_CHANNEL_RXBYTEISALIGNED", - "PCSRSVDIN4": "GTPE2_CHANNEL_PCSRSVDIN4", - "RXOSINTCFG3": "GTPE2_CHANNEL_RXOSINTCFG3", - "TXCHARDISPVAL3": "GTPE2_CHANNEL_TXCHARDISPVAL3", - "TXCHARDISPMODE3": "GTPE2_CHANNEL_TXCHARDISPMODE3", - "RXDATA29": "GTPE2_CHANNEL_RXDATA29", - "TXOUTCLKPCS": "GTPE2_CHANNEL_TXOUTCLKPCS", - "RXCLKCORCNT1": "GTPE2_CHANNEL_RXCLKCORCNT1", - "RXADAPTSELTEST2": "GTPE2_CHANNEL_RXADAPTSELTEST2", - "TXINHIBIT": "GTPE2_CHANNEL_TXINHIBIT", - "TXDATA13": "GTPE2_CHANNEL_TXDATA13", - "TXPISOPD": "GTPE2_CHANNEL_TXPISOPD", - "RXPMARESET": "GTPE2_CHANNEL_RXPMARESET", - "TSTIN14": "GTPE2_CHANNEL_TSTIN14", - "PCSRSVDIN13": "GTPE2_CHANNEL_PCSRSVDIN13", - "PMASCANCLK3": "GTPE2_CHANNEL_PMASCANCLK3", - "TXDATA8": "GTPE2_CHANNEL_TXDATA8", - "PCSRSVDIN1": "GTPE2_CHANNEL_PCSRSVDIN1", - "DRPDI12": "GTPE2_CHANNEL_DRPDI12", - "RXOSINTID02": "GTPE2_CHANNEL_RXOSINTID02", - "PMARSVDOUT1": "GTPE2_CHANNEL_PMARSVDOUT1", - "RXCDRHOLD": "GTPE2_CHANNEL_RXCDRHOLD", - "TXDATA10": "GTPE2_CHANNEL_TXDATA10", - "DRPDI6": "GTPE2_CHANNEL_DRPDI6", - "TSTIN2": "GTPE2_CHANNEL_TSTIN2", - "DRPWE": "GTPE2_CHANNEL_DRPWE", - "RXOUTCLKSEL2": "GTPE2_CHANNEL_RXOUTCLKSEL2", - "DRPADDR5": "GTPE2_CHANNEL_DRPADDR5", - "TSTIN15": "GTPE2_CHANNEL_TSTIN15", - "RXPHSLIPMONITOR0": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "RXPHDLYRESET": "GTPE2_CHANNEL_RXPHDLYRESET", - "RXPHSLIPMONITOR1": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "TXPRBSFORCEERR": "GTPE2_CHANNEL_TXPRBSFORCEERR", - "TXHEADER2": "GTPE2_CHANNEL_TXHEADER2", - "PCSRSVDOUT0": "GTPE2_CHANNEL_PCSRSVDOUT0", - "TXPD0": "GTPE2_CHANNEL_TXPD0", - "RXDATA4": "GTPE2_CHANNEL_RXDATA4", - "RXHEADER1": "GTPE2_CHANNEL_RXHEADER1", - "RXOSINTID00": "GTPE2_CHANNEL_RXOSINTID00", - "RXSTARTOFSEQ1": "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "RXOSOVRDEN": "GTPE2_CHANNEL_RXOSOVRDEN", - "RXADAPTSELTEST11": "GTPE2_CHANNEL_RXADAPTSELTEST11", - "PCSRSVDOUT1": "GTPE2_CHANNEL_PCSRSVDOUT1", - "TXPIPPMPD": "GTPE2_CHANNEL_TXPIPPMPD", - "TXDLYOVRDEN": "GTPE2_CHANNEL_TXDLYOVRDEN", - "RXDATA21": "GTPE2_CHANNEL_RXDATA21", - "RXCHBONDO1": "GTPE2_CHANNEL_RXCHBONDO1", - "TXOUTCLKSEL0": "GTPE2_CHANNEL_TXOUTCLKSEL0", - "TXDEEMPH": "GTPE2_CHANNEL_TXDEEMPH", - "TXDATA5": "GTPE2_CHANNEL_TXDATA5", - "GTRSVD1": "GTPE2_CHANNEL_GTRSVD1", - "TSTPD3": "GTPE2_CHANNEL_TSTPD3", - "TXMAINCURSOR6": "GTPE2_CHANNEL_TXMAINCURSOR6", - "TSTIN5": "GTPE2_CHANNEL_TSTIN5", - "TXPRECURSOR2": "GTPE2_CHANNEL_TXPRECURSOR2", - "TXRATEMODE": "GTPE2_CHANNEL_TXRATEMODE", - "RXLPMLFOVRDEN": "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "RXOUTCLKSEL0": "GTPE2_CHANNEL_RXOUTCLKSEL0", - "TXUSRCLK2": "GTPE2_CHANNEL_TXUSRCLK2", - "RXPHDLYPD": "GTPE2_CHANNEL_RXPHDLYPD", - "RXOSINTID03": "GTPE2_CHANNEL_RXOSINTID03", - "RXDATA3": "GTPE2_CHANNEL_RXDATA3", - "DRPDO6": "GTPE2_CHANNEL_DRPDO6", - "TXPOSTCURSORINV": "GTPE2_CHANNEL_TXPOSTCURSORINV", - "TXMAINCURSOR2": "GTPE2_CHANNEL_TXMAINCURSOR2", - "TSTPD1": "GTPE2_CHANNEL_TSTPD1", - "RXPHMONITOR0": "GTPE2_CHANNEL_RXPHMONITOR0", - "TSTIN18": "GTPE2_CHANNEL_TSTIN18", - "DRPDO4": "GTPE2_CHANNEL_DRPDO4", - "RXOSCALRESET": "GTPE2_CHANNEL_RXOSCALRESET", - "RXCHARISCOMMA1": "GTPE2_CHANNEL_RXCHARISCOMMA1", - "RXADAPTSELTEST4": "GTPE2_CHANNEL_RXADAPTSELTEST4", - "RXMCOMMAALIGNEN": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "TXPHDLYPD": "GTPE2_CHANNEL_TXPHDLYPD", - "TXPOSTCURSOR2": "GTPE2_CHANNEL_TXPOSTCURSOR2", - "PMASCANCLK0": "GTPE2_CHANNEL_PMASCANCLK0", - "PCSRSVDOUT15": "GTPE2_CHANNEL_PCSRSVDOUT15", - "SCANIN3": "GTPE2_CHANNEL_SCANIN3", - "TXELECIDLE": "GTPE2_CHANNEL_TXELECIDLE", - "RXDATA27": "GTPE2_CHANNEL_RXDATA27", - "TXRATE2": "GTPE2_CHANNEL_TXRATE2", - "EYESCANRESET": "GTPE2_CHANNEL_EYESCANRESET", - "DRPDI13": "GTPE2_CHANNEL_DRPDI13", - "PMASCANCLK1": "GTPE2_CHANNEL_PMASCANCLK1", - "RXCHBONDLEVEL0": "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "RXPHMONITOR3": "GTPE2_CHANNEL_RXPHMONITOR3", - "TXSTARTSEQ": "GTPE2_CHANNEL_TXSTARTSEQ", - "RXRATE1": "GTPE2_CHANNEL_RXRATE1", - "DRPDO0": "GTPE2_CHANNEL_DRPDO0", - "TXBUFDIFFCTRL0": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "RXDATA18": "GTPE2_CHANNEL_RXDATA18", - "DRPDO1": "GTPE2_CHANNEL_DRPDO1", - "RXADAPTSELTEST10": "GTPE2_CHANNEL_RXADAPTSELTEST10", - "RXDLYBYPASS": "GTPE2_CHANNEL_RXDLYBYPASS", - "TXDIFFCTRL0": "GTPE2_CHANNEL_TXDIFFCTRL0", - "RXPRBSCNTRESET": "GTPE2_CHANNEL_RXPRBSCNTRESET", - "RXCLKCORCNT0": "GTPE2_CHANNEL_RXCLKCORCNT0", - "TSTCLK1": "GTPE2_CHANNEL_TSTCLK1", - "PLL1CLK": "GTPE2_CHANNEL_PLL1CLK", - "DMONITORCLK": "GTPE2_CHANNEL_DMONITORCLK", - "PLL0REFCLK": "GTPE2_CHANNEL_PLL0REFCLK", - "SCANMODEB": "GTPE2_CHANNEL_SCANMODEB", - "TSTIN12": "GTPE2_CHANNEL_TSTIN12", - "TSTIN7": "GTPE2_CHANNEL_TSTIN7", - "TXDATA19": "GTPE2_CHANNEL_TXDATA19", - "RXPCSRESET": "GTPE2_CHANNEL_RXPCSRESET", - "TXPRBSSEL2": "GTPE2_CHANNEL_TXPRBSSEL2", - "RXPHOVRDEN": "GTPE2_CHANNEL_RXPHOVRDEN", - "TSTIN11": "GTPE2_CHANNEL_TSTIN11", - "RXDATA6": "GTPE2_CHANNEL_RXDATA6", - "SETERRSTATUS": "GTPE2_CHANNEL_SETERRSTATUS", - "RXOSINTID01": "GTPE2_CHANNEL_RXOSINTID01", - "TXHEADER0": "GTPE2_CHANNEL_TXHEADER0", - "DRPDI8": "GTPE2_CHANNEL_DRPDI8", - "TXDIFFCTRL3": "GTPE2_CHANNEL_TXDIFFCTRL3", - "TXDATA18": "GTPE2_CHANNEL_TXDATA18", - "DMONITOROUT5": "GTPE2_CHANNEL_DMONITOROUT5", - "RXDATA1": "GTPE2_CHANNEL_RXDATA1", - "RX8B10BEN": "GTPE2_CHANNEL_RX8B10BEN", - "TXCHARDISPVAL1": "GTPE2_CHANNEL_TXCHARDISPVAL1", - "TXRATE1": "GTPE2_CHANNEL_TXRATE1", - "TXDATA21": "GTPE2_CHANNEL_TXDATA21", - "PMASCANOUT2": "GTPE2_CHANNEL_PMASCANOUT2", - "PCSRSVDIN10": "GTPE2_CHANNEL_PCSRSVDIN10", - "GTRSVD2": "GTPE2_CHANNEL_GTRSVD2", - "RXADAPTSELTEST5": "GTPE2_CHANNEL_RXADAPTSELTEST5", - "LOOPBACK0": "GTPE2_CHANNEL_LOOPBACK0", - "DRPADDR4": "GTPE2_CHANNEL_DRPADDR4", - "TXCHARDISPVAL0": "GTPE2_CHANNEL_TXCHARDISPVAL0", - "PMASCANIN4": "GTPE2_CHANNEL_PMASCANIN4", - "DRPADDR8": "GTPE2_CHANNEL_DRPADDR8", - "RXSYSCLKSEL1": "GTPE2_CHANNEL_RXSYSCLKSEL1", - "RXADAPTSELTEST8": "GTPE2_CHANNEL_RXADAPTSELTEST8", - "TXSYNCOUT": "GTPE2_CHANNEL_TXSYNCOUT", - "RXCHBONDMASTER": "GTPE2_CHANNEL_RXCHBONDMASTER", - "TXPRECURSORINV": "GTPE2_CHANNEL_TXPRECURSORINV", - "PCSRSVDOUT2": "GTPE2_CHANNEL_PCSRSVDOUT2", - "TXPOLARITY": "GTPE2_CHANNEL_TXPOLARITY", - "RXADAPTSELTEST9": "GTPE2_CHANNEL_RXADAPTSELTEST9", - "DMONITOROUT0": "GTPE2_CHANNEL_DMONITOROUT0", - "TXUSERRDY": "GTPE2_CHANNEL_TXUSERRDY", - "DMONITOROUT4": "GTPE2_CHANNEL_DMONITOROUT4", - "TXDLYEN": "GTPE2_CHANNEL_TXDLYEN", - "TSTIN10": "GTPE2_CHANNEL_TSTIN10", - "RXPHSLIPMONITOR4": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "RXCHBONDI3": "GTPE2_CHANNEL_RXCHBONDI3", - "TXPIPPMSTEPSIZE2": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "RXDDIEN": "GTPE2_CHANNEL_RXDDIEN", - "RXPRBSSEL1": "GTPE2_CHANNEL_RXPRBSSEL1", - "PCSRSVDIN5": "GTPE2_CHANNEL_PCSRSVDIN5", - "TXPMARESETDONE": "GTPE2_CHANNEL_TXPMARESETDONE", - "TXRUNDISP3": "GTPE2_CHANNEL_TXRUNDISP3", - "RXUSRCLK": "GTPE2_CHANNEL_RXUSRCLK", - "TXSEQUENCE4": "GTPE2_CHANNEL_TXSEQUENCE4", - "RXELECIDLEMODE1": "GTPE2_CHANNEL_RXELECIDLEMODE1", - "DRPDO9": "GTPE2_CHANNEL_DRPDO9", - "RXCOMMADETEN": "GTPE2_CHANNEL_RXCOMMADETEN", - "GTRESETSEL": "GTPE2_CHANNEL_GTRESETSEL", - "SCANCLK": "GTPE2_CHANNEL_SCANCLK", - "TXDLYHOLD": "GTPE2_CHANNEL_TXDLYHOLD", - "PMASCANIN0": "GTPE2_CHANNEL_PMASCANIN0", - "TXPRBSSEL1": "GTPE2_CHANNEL_TXPRBSSEL1", - "LOOPBACK2": "GTPE2_CHANNEL_LOOPBACK2", - "RXDATA2": "GTPE2_CHANNEL_RXDATA2", - "PCSRSVDOUT9": "GTPE2_CHANNEL_PCSRSVDOUT9", - "TXDATA7": "GTPE2_CHANNEL_TXDATA7", - "RXOSINTSTROBESTARTED": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "RXADAPTSELTEST13": "GTPE2_CHANNEL_RXADAPTSELTEST13", - "TXOUTCLKFABRIC": "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "TXBUFDIFFCTRL2": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "PCSRSVDOUT4": "GTPE2_CHANNEL_PCSRSVDOUT4", - "TXRUNDISP1": "GTPE2_CHANNEL_TXRUNDISP1", - "RXCHBONDO2": "GTPE2_CHANNEL_RXCHBONDO2", - "TXSEQUENCE5": "GTPE2_CHANNEL_TXSEQUENCE5", - "DRPADDR6": "GTPE2_CHANNEL_DRPADDR6", - "DRPADDR3": "GTPE2_CHANNEL_DRPADDR3", - "RXSTARTOFSEQ0": "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "TXUSRCLK": "GTPE2_CHANNEL_TXUSRCLK", - "TXDATA29": "GTPE2_CHANNEL_TXDATA29", - "RXPHALIGNDONE": "GTPE2_CHANNEL_RXPHALIGNDONE", - "TSTIN4": "GTPE2_CHANNEL_TSTIN4", - "GTRSVD5": "GTPE2_CHANNEL_GTRSVD5", - "PCSRSVDOUT7": "GTPE2_CHANNEL_PCSRSVDOUT7", - "RXADAPTSELTEST3": "GTPE2_CHANNEL_RXADAPTSELTEST3", - "PCSRSVDIN8": "GTPE2_CHANNEL_PCSRSVDIN8", - "TXPD1": "GTPE2_CHANNEL_TXPD1", - "GTRSVD9": "GTPE2_CHANNEL_GTRSVD9", - "RXDATA15": "GTPE2_CHANNEL_RXDATA15", - "RXCHARISK3": "GTPE2_CHANNEL_RXCHARISK3", - "TXPRECURSOR3": "GTPE2_CHANNEL_TXPRECURSOR3", - "RXPHMONITOR1": "GTPE2_CHANNEL_RXPHMONITOR1", - "RXRATE0": "GTPE2_CHANNEL_RXRATE0", - "RXOUTCLK": "GTPE2_CHANNEL_GTRXOUTCLK_1", - "RXOSINTDONE": "GTPE2_CHANNEL_RXOSINTDONE", - "RXDATAVALID1": "GTPE2_CHANNEL_RXDATAVALID1", - "RXNOTINTABLE0": "GTPE2_CHANNEL_RXNOTINTABLE0", - "RESETOVRD": "GTPE2_CHANNEL_RESETOVRD", - "TXDATA26": "GTPE2_CHANNEL_TXDATA26", - "RXDATAVALID0": "GTPE2_CHANNEL_RXDATAVALID0", - "PMASCANOUT3": "GTPE2_CHANNEL_PMASCANOUT3", - "TSTPD4": "GTPE2_CHANNEL_TSTPD4", - "PCSRSVDOUT13": "GTPE2_CHANNEL_PCSRSVDOUT13", - "GTRSVD13": "GTPE2_CHANNEL_GTRSVD13", - "TXDATA20": "GTPE2_CHANNEL_TXDATA20", - "TXDIFFPD": "GTPE2_CHANNEL_TXDIFFPD", - "RXSTATUS1": "GTPE2_CHANNEL_RXSTATUS1", - "RXCHARISK0": "GTPE2_CHANNEL_RXCHARISK0", - "TXBUFSTATUS0": "GTPE2_CHANNEL_TXBUFSTATUS0", - "TSTCLK0": "GTPE2_CHANNEL_TSTCLK0", - "DMONITOROUT8": "GTPE2_CHANNEL_DMONITOROUT8", - "SCANOUT4": "GTPE2_CHANNEL_SCANOUT4", - "RXELECIDLE": "GTPE2_CHANNEL_RXELECIDLE", - "PMASCANCLK2": "GTPE2_CHANNEL_PMASCANCLK2", - "RXDATA16": "GTPE2_CHANNEL_RXDATA16", - "RXCHBONDI1": "GTPE2_CHANNEL_RXCHBONDI1", - "RXCHANREALIGN": "GTPE2_CHANNEL_RXCHANREALIGN", - "RXDISPERR3": "GTPE2_CHANNEL_RXDISPERR3", - "PMASCANENB": "GTPE2_CHANNEL_PMASCANENB", - "TXDATA22": "GTPE2_CHANNEL_TXDATA22", - "PMASCANOUT0": "GTPE2_CHANNEL_PMASCANOUT0", - "TXPIPPMOVRDEN": "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "RXOSINTNTRLEN": "GTPE2_CHANNEL_RXOSINTNTRLEN", - "TXDATA17": "GTPE2_CHANNEL_TXDATA17", - "RXCOMMADET": "GTPE2_CHANNEL_RXCOMMADET", - "TXOUTCLKSEL2": "GTPE2_CHANNEL_TXOUTCLKSEL2", - "TXDLYSRESET": "GTPE2_CHANNEL_TXDLYSRESET", - "TXPHALIGNEN": "GTPE2_CHANNEL_TXPHALIGNEN", - "DRPDO2": "GTPE2_CHANNEL_DRPDO2", - "TXRATEDONE": "GTPE2_CHANNEL_TXRATEDONE", - "TXDATA6": "GTPE2_CHANNEL_TXDATA6", - "DRPDI1": "GTPE2_CHANNEL_DRPDI1", - "RXDISPERR0": "GTPE2_CHANNEL_RXDISPERR0", - "RXDATA13": "GTPE2_CHANNEL_RXDATA13", - "PMASCANIN1": "GTPE2_CHANNEL_PMASCANIN1", - "TXDATA3": "GTPE2_CHANNEL_TXDATA3", - "PCSRSVDIN12": "GTPE2_CHANNEL_PCSRSVDIN12", - "TXRUNDISP2": "GTPE2_CHANNEL_TXRUNDISP2", - "RXDEBUGPULSE": "GTPE2_CHANNEL_RXDEBUGPULSE", - "RXDATA20": "GTPE2_CHANNEL_RXDATA20", - "GTRSVD14": "GTPE2_CHANNEL_GTRSVD14", - "RXCHBONDO0": "GTPE2_CHANNEL_RXCHBONDO0", - "TXDATA23": "GTPE2_CHANNEL_TXDATA23", - "TXPDELECIDLEMODE": "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "TXMAINCURSOR3": "GTPE2_CHANNEL_TXMAINCURSOR3", - "RXLPMOSINTNTRLEN": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "RXDLYSRESET": "GTPE2_CHANNEL_RXDLYSRESET", - "GTRSVD15": "GTPE2_CHANNEL_GTRSVD15", - "RXLPMHFHOLD": "GTPE2_CHANNEL_RXLPMHFHOLD", - "RXDLYEN": "GTPE2_CHANNEL_RXDLYEN", - "TXPIPPMSEL": "GTPE2_CHANNEL_TXPIPPMSEL", - "PCSRSVDIN2": "GTPE2_CHANNEL_PCSRSVDIN2", - "GTRSVD7": "GTPE2_CHANNEL_GTRSVD7", - "DRPDI15": "GTPE2_CHANNEL_DRPDI15", - "RXCHBONDEN": "GTPE2_CHANNEL_RXCHBONDEN", - "TXMAINCURSOR5": "GTPE2_CHANNEL_TXMAINCURSOR5", - "TXGEARBOXREADY": "GTPE2_CHANNEL_TXGEARBOXREADY", - "TXSEQUENCE3": "GTPE2_CHANNEL_TXSEQUENCE3", - "DRPDI5": "GTPE2_CHANNEL_DRPDI5", - "TXCHARDISPMODE0": "GTPE2_CHANNEL_TXCHARDISPMODE0", - "TXDATA27": "GTPE2_CHANNEL_TXDATA27", - "RXSYNCALLIN": "GTPE2_CHANNEL_RXSYNCALLIN", - "EYESCANDATAERROR": "GTPE2_CHANNEL_EYESCANDATAERROR", - "SCANIN2": "GTPE2_CHANNEL_SCANIN2", - "GTRSVD10": "GTPE2_CHANNEL_GTRSVD10", - "RXPRBSSEL2": "GTPE2_CHANNEL_RXPRBSSEL2", - "RXCHBONDI0": "GTPE2_CHANNEL_RXCHBONDI0", - "TXBUFDIFFCTRL1": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "RXADAPTSELTEST6": "GTPE2_CHANNEL_RXADAPTSELTEST6", - "DRPDO8": "GTPE2_CHANNEL_DRPDO8", - "TXDLYBYPASS": "GTPE2_CHANNEL_TXDLYBYPASS", - "TX8B10BBYPASS3": "GTPE2_CHANNEL_TX8B10BBYPASS3", - "DMONFIFORESET": "GTPE2_CHANNEL_DMONFIFORESET", - "RXDATA30": "GTPE2_CHANNEL_RXDATA30", - "TXCHARDISPVAL2": "GTPE2_CHANNEL_TXCHARDISPVAL2", - "TSTIN8": "GTPE2_CHANNEL_TSTIN8", - "RXDATA24": "GTPE2_CHANNEL_RXDATA24", - "GTPTXN": "GTPE2_CHANNEL_TXN", - "RXSYNCMODE": "GTPE2_CHANNEL_RXSYNCMODE", - "TXDATA1": "GTPE2_CHANNEL_TXDATA1", - "TXPRECURSOR0": "GTPE2_CHANNEL_TXPRECURSOR0", - "RXSYNCOUT": "GTPE2_CHANNEL_RXSYNCOUT", - "TSTIN19": "GTPE2_CHANNEL_TSTIN19", - "RXRATEMODE": "GTPE2_CHANNEL_RXRATEMODE", - "DRPDI11": "GTPE2_CHANNEL_DRPDI11", - "RXCDRRESET": "GTPE2_CHANNEL_RXCDRRESET", - "RXOSINTCFG0": "GTPE2_CHANNEL_RXOSINTCFG0", - "PMASCANRSTEN": "GTPE2_CHANNEL_PMASCANRSTEN", - "CLKRSVD1": "GTPE2_CHANNEL_CLKRSVD1", - "TX8B10BBYPASS0": "GTPE2_CHANNEL_TX8B10BBYPASS0", - "PCSRSVDOUT14": "GTPE2_CHANNEL_PCSRSVDOUT14", - "RXNOTINTABLE2": "GTPE2_CHANNEL_RXNOTINTABLE2", - "PCSRSVDIN3": "GTPE2_CHANNEL_PCSRSVDIN3", - "RXOSINTPD": "GTPE2_CHANNEL_RXOSINTPD", - "DMONITOROUT12": "GTPE2_CHANNEL_DMONITOROUT12", - "TXPOSTCURSOR3": "GTPE2_CHANNEL_TXPOSTCURSOR3", - "TXPCSRESET": "GTPE2_CHANNEL_TXPCSRESET", - "TXPHDLYRESET": "GTPE2_CHANNEL_TXPHDLYRESET", - "RXOSINTHOLD": "GTPE2_CHANNEL_RXOSINTHOLD", - "TXPRECURSOR4": "GTPE2_CHANNEL_TXPRECURSOR4", - "RXBYTEREALIGN": "GTPE2_CHANNEL_RXBYTEREALIGN", - "TSTPD2": "GTPE2_CHANNEL_TSTPD2", - "TXSEQUENCE6": "GTPE2_CHANNEL_TXSEQUENCE6", - "TXCHARDISPMODE1": "GTPE2_CHANNEL_TXCHARDISPMODE1", - "RXPRBSSEL0": "GTPE2_CHANNEL_RXPRBSSEL0", - "TSTIN6": "GTPE2_CHANNEL_TSTIN6", - "DRPEN": "GTPE2_CHANNEL_DRPEN", - "TSTIN1": "GTPE2_CHANNEL_TSTIN1", - "DRPDO7": "GTPE2_CHANNEL_DRPDO7", - "PCSRSVDIN7": "GTPE2_CHANNEL_PCSRSVDIN7", - "DRPDI3": "GTPE2_CHANNEL_DRPDI3", - "TSTIN3": "GTPE2_CHANNEL_TSTIN3", - "RXDLYSRESETDONE": "GTPE2_CHANNEL_RXDLYSRESETDONE", - "RXCOMINITDET": "GTPE2_CHANNEL_RXCOMINITDET", - "DRPADDR7": "GTPE2_CHANNEL_DRPADDR7", - "RXLPMLFHOLD": "GTPE2_CHANNEL_RXLPMLFHOLD", - "TXPIPPMSTEPSIZE0": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "TXCHARISK2": "GTPE2_CHANNEL_TXCHARISK2", - "RXDATA9": "GTPE2_CHANNEL_RXDATA9", - "RXBUFSTATUS2": "GTPE2_CHANNEL_RXBUFSTATUS2", - "DRPDI0": "GTPE2_CHANNEL_DRPDI0", - "GTRSVD4": "GTPE2_CHANNEL_GTRSVD4", - "RXSYNCIN": "GTPE2_CHANNEL_RXSYNCIN", - "RXLPMHFOVRDEN": "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "SCANOUT0": "GTPE2_CHANNEL_SCANOUT0", - "TXPHALIGNDONE": "GTPE2_CHANNEL_TXPHALIGNDONE", - "TXDATA30": "GTPE2_CHANNEL_TXDATA30", - "RXCHBONDI2": "GTPE2_CHANNEL_RXCHBONDI2", - "TX8B10BEN": "GTPE2_CHANNEL_TX8B10BEN", - "DRPDO11": "GTPE2_CHANNEL_DRPDO11", - "RXCOMWAKEDET": "GTPE2_CHANNEL_RXCOMWAKEDET", - "RXDLYOVRDEN": "GTPE2_CHANNEL_RXDLYOVRDEN", - "PLL0CLK": "GTPE2_CHANNEL_PLL0CLK", - "RXOUTCLKSEL1": "GTPE2_CHANNEL_RXOUTCLKSEL1", - "PMASCANIN2": "GTPE2_CHANNEL_PMASCANIN2", - "TXDIFFCTRL1": "GTPE2_CHANNEL_TXDIFFCTRL1", - "SCANOUT3": "GTPE2_CHANNEL_SCANOUT3", - "RXOUTCLKPCS": "GTPE2_CHANNEL_RXOUTCLKPCS", - "LOOPBACK1": "GTPE2_CHANNEL_LOOPBACK1", - "DRPDO5": "GTPE2_CHANNEL_DRPDO5", - "SCANIN0": "GTPE2_CHANNEL_SCANIN0", - "DRPDO15": "GTPE2_CHANNEL_DRPDO15", - "DRPADDR1": "GTPE2_CHANNEL_DRPADDR1", - "RXOSINTTESTOVRDEN": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "TXPOSTCURSOR4": "GTPE2_CHANNEL_TXPOSTCURSOR4", - "DMONITOROUT9": "GTPE2_CHANNEL_DMONITOROUT9", - "RXDATA23": "GTPE2_CHANNEL_RXDATA23", - "TXDATA24": "GTPE2_CHANNEL_TXDATA24", - "RXDISPERR1": "GTPE2_CHANNEL_RXDISPERR1", - "RXSYNCDONE": "GTPE2_CHANNEL_RXSYNCDONE", - "TX8B10BBYPASS2": "GTPE2_CHANNEL_TX8B10BBYPASS2", - "TXDATA28": "GTPE2_CHANNEL_TXDATA28", - "PLL1REFCLK": "GTPE2_CHANNEL_PLL1REFCLK", - "TXRESETDONE": "GTPE2_CHANNEL_TXRESETDONE", - "TXDIFFCTRL2": "GTPE2_CHANNEL_TXDIFFCTRL2", - "RXOSINTSTROBEDONE": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "DRPDI10": "GTPE2_CHANNEL_DRPDI10", - "SCANOUT1": "GTPE2_CHANNEL_SCANOUT1", - "DRPDI14": "GTPE2_CHANNEL_DRPDI14", - "GTRSVD8": "GTPE2_CHANNEL_GTRSVD8", - "RXHEADER2": "GTPE2_CHANNEL_RXHEADER2", - "TXSYSCLKSEL1": "GTPE2_CHANNEL_TXSYSCLKSEL1", - "RXADAPTSELTEST1": "GTPE2_CHANNEL_RXADAPTSELTEST1", - "TXPHINITDONE": "GTPE2_CHANNEL_TXPHINITDONE", - "RXPOLARITY": "GTPE2_CHANNEL_RXPOLARITY", - "RXPHSLIPMONITOR3": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "RXOUTCLKFABRIC": "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "RXOSHOLD": "GTPE2_CHANNEL_RXOSHOLD", - "TXRUNDISP0": "GTPE2_CHANNEL_TXRUNDISP0", - "DMONITOROUT13": "GTPE2_CHANNEL_DMONITOROUT13", - "TXCHARDISPMODE2": "GTPE2_CHANNEL_TXCHARDISPMODE2", - "TXDATA16": "GTPE2_CHANNEL_TXDATA16", - "RXDFEXYDEN": "GTPE2_CHANNEL_RXDFEXYDEN", - "RXADAPTSELTEST0": "GTPE2_CHANNEL_RXADAPTSELTEST0", - "RXCHANISALIGNED": "GTPE2_CHANNEL_RXCHANISALIGNED", - "PCSRSVDOUT11": "GTPE2_CHANNEL_PCSRSVDOUT11", - "DRPRDY": "GTPE2_CHANNEL_DRPRDY", - "RXDATA25": "GTPE2_CHANNEL_RXDATA25", - "RXCHARISCOMMA2": "GTPE2_CHANNEL_RXCHARISCOMMA2", - "TXPHINIT": "GTPE2_CHANNEL_TXPHINIT", - "TXOUTCLKSEL1": "GTPE2_CHANNEL_TXOUTCLKSEL1", - "TX8B10BBYPASS1": "GTPE2_CHANNEL_TX8B10BBYPASS1", - "RXPHMONITOR2": "GTPE2_CHANNEL_RXPHMONITOR2", - "RXCHARISK1": "GTPE2_CHANNEL_RXCHARISK1", - "RXPHALIGNEN": "GTPE2_CHANNEL_RXPHALIGNEN", - "RXDATA12": "GTPE2_CHANNEL_RXDATA12", - "TSTIN16": "GTPE2_CHANNEL_TSTIN16", - "PCSRSVDOUT10": "GTPE2_CHANNEL_PCSRSVDOUT10", - "RXCDROVRDEN": "GTPE2_CHANNEL_RXCDROVRDEN", - "TXPIPPMSTEPSIZE4": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "RXDLYTESTENB": "GTPE2_CHANNEL_RXDLYTESTENB", - "RXOOBRESET": "GTPE2_CHANNEL_RXOOBRESET", - "PMASCANOUT6": "GTPE2_CHANNEL_PMASCANOUT6", - "TXCHARISK0": "GTPE2_CHANNEL_TXCHARISK0", - "TXDATA12": "GTPE2_CHANNEL_TXDATA12", - "EYESCANMODE": "GTPE2_CHANNEL_EYESCANMODE", - "DRPDI7": "GTPE2_CHANNEL_DRPDI7", - "RXLPMRESET": "GTPE2_CHANNEL_RXLPMRESET", - "RXDATA11": "GTPE2_CHANNEL_RXDATA11", - "TXPRECURSOR1": "GTPE2_CHANNEL_TXPRECURSOR1", - "TXCOMWAKE": "GTPE2_CHANNEL_TXCOMWAKE", - "TXCHARISK3": "GTPE2_CHANNEL_TXCHARISK3", - "TXSWING": "GTPE2_CHANNEL_TXSWING", - "SCANIN5": "GTPE2_CHANNEL_SCANIN5", - "SCANIN4": "GTPE2_CHANNEL_SCANIN4", - "TXPHALIGN": "GTPE2_CHANNEL_TXPHALIGN", - "TXMAINCURSOR4": "GTPE2_CHANNEL_TXMAINCURSOR4", - "DRPDO14": "GTPE2_CHANNEL_DRPDO14", - "DMONITOROUT2": "GTPE2_CHANNEL_DMONITOROUT2", - "RXCDRFREQRESET": "GTPE2_CHANNEL_RXCDRFREQRESET", - "GTRXRESET": "GTPE2_CHANNEL_GTRXRESET", - "TXSYNCMODE": "GTPE2_CHANNEL_TXSYNCMODE", - "TSTPDOVRDB": "GTPE2_CHANNEL_TSTPDOVRDB", - "RXCOMSASDET": "GTPE2_CHANNEL_RXCOMSASDET", - "PCSRSVDOUT3": "GTPE2_CHANNEL_PCSRSVDOUT3", - "RXOSINTSTROBE": "GTPE2_CHANNEL_RXOSINTSTROBE", - "PCSRSVDIN15": "GTPE2_CHANNEL_PCSRSVDIN15", - "PMASCANIN6": "GTPE2_CHANNEL_PMASCANIN6", - "TXCHARISK1": "GTPE2_CHANNEL_TXCHARISK1", - "PMASCANIN3": "GTPE2_CHANNEL_PMASCANIN3", - "TXPOSTCURSOR0": "GTPE2_CHANNEL_TXPOSTCURSOR0", - "EYESCANTRIGGER": "GTPE2_CHANNEL_EYESCANTRIGGER", - "TXSEQUENCE2": "GTPE2_CHANNEL_TXSEQUENCE2", - "GTRSVD0": "GTPE2_CHANNEL_GTRSVD0", - "CLKRSVD0": "GTPE2_CHANNEL_CLKRSVD0", - "RXPMARESETDONE": "GTPE2_CHANNEL_RXPMARESETDONE", - "DRPADDR0": "GTPE2_CHANNEL_DRPADDR0", - "TXPHDLYTSTCLK": "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "RXRATE2": "GTPE2_CHANNEL_RXRATE2", - "DMONITOROUT10": "GTPE2_CHANNEL_DMONITOROUT10", - "TXDATA0": "GTPE2_CHANNEL_TXDATA0", - "RXDATA22": "GTPE2_CHANNEL_RXDATA22", - "RXCHBONDSLAVE": "GTPE2_CHANNEL_RXCHBONDSLAVE", - "TXPMARESET": "GTPE2_CHANNEL_TXPMARESET", - "TXCOMFINISH": "GTPE2_CHANNEL_TXCOMFINISH", - "TXDETECTRX": "GTPE2_CHANNEL_TXDETECTRX", - "PMASCANIN5": "GTPE2_CHANNEL_PMASCANIN5", - "DRPADDR2": "GTPE2_CHANNEL_DRPADDR2", - "TSTIN17": "GTPE2_CHANNEL_TSTIN17", - "RXCHARISK2": "GTPE2_CHANNEL_RXCHARISK2", - "TXDLYUPDOWN": "GTPE2_CHANNEL_TXDLYUPDOWN", - "PMARSVDIN0": "GTPE2_CHANNEL_PMARSVDIN0", - "SIGVALIDCLK": "GTPE2_CHANNEL_SIGVALIDCLK", - "TXMARGIN0": "GTPE2_CHANNEL_TXMARGIN0", - "GTPRXP": "GTPE2_CHANNEL_RXP", - "DMONITOROUT11": "GTPE2_CHANNEL_DMONITOROUT11", - "RXDATA7": "GTPE2_CHANNEL_RXDATA7", - "TXDATA2": "GTPE2_CHANNEL_TXDATA2", - "DMONITOROUT1": "GTPE2_CHANNEL_DMONITOROUT1", - "TXCOMINIT": "GTPE2_CHANNEL_TXCOMINIT", - "RXRESETDONE": "GTPE2_CHANNEL_RXRESETDONE", - "TSTIN9": "GTPE2_CHANNEL_TSTIN9", - "TXSYSCLKSEL0": "GTPE2_CHANNEL_TXSYSCLKSEL0", - "TXDLYTESTENB": "GTPE2_CHANNEL_TXDLYTESTENB", - "PCSRSVDOUT5": "GTPE2_CHANNEL_PCSRSVDOUT5", - "RXCHARISCOMMA0": "GTPE2_CHANNEL_RXCHARISCOMMA0", - "RXOSINTOVRDEN": "GTPE2_CHANNEL_RXOSINTOVRDEN", - "RXCHBONDO3": "GTPE2_CHANNEL_RXCHBONDO3", - "PCSRSVDOUT12": "GTPE2_CHANNEL_PCSRSVDOUT12", - "DRPDI2": "GTPE2_CHANNEL_DRPDI2", - "TXPOSTCURSOR1": "GTPE2_CHANNEL_TXPOSTCURSOR1", - "PCSRSVDOUT8": "GTPE2_CHANNEL_PCSRSVDOUT8", - "GTRSVD6": "GTPE2_CHANNEL_GTRSVD6", - "DRPDO10": "GTPE2_CHANNEL_DRPDO10", - "GTTXRESET": "GTPE2_CHANNEL_GTTXRESET", - "RXDATA10": "GTPE2_CHANNEL_RXDATA10", - "RXRATEDONE": "GTPE2_CHANNEL_RXRATEDONE", - "TXDLYSRESETDONE": "GTPE2_CHANNEL_TXDLYSRESETDONE", - "RXOSINTCFG1": "GTPE2_CHANNEL_RXOSINTCFG1", - "RXDATA14": "GTPE2_CHANNEL_RXDATA14", - "RXPHSLIPMONITOR2": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "TXPIPPMSTEPSIZE1": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "RXPRBSERR": "GTPE2_CHANNEL_RXPRBSERR", - "TXSEQUENCE1": "GTPE2_CHANNEL_TXSEQUENCE1", - "DRPDO12": "GTPE2_CHANNEL_DRPDO12", - "GTRSVD12": "GTPE2_CHANNEL_GTRSVD12", - "RXOSINTEN": "GTPE2_CHANNEL_RXOSINTEN", - "RXDATA19": "GTPE2_CHANNEL_RXDATA19", - "RXDATA17": "GTPE2_CHANNEL_RXDATA17", - "TSTIN13": "GTPE2_CHANNEL_TSTIN13", - "RXHEADER0": "GTPE2_CHANNEL_RXHEADER0", - "PMARSVDIN3": "GTPE2_CHANNEL_PMARSVDIN3", - "RXBUFSTATUS1": "GTPE2_CHANNEL_RXBUFSTATUS1", - "PMASCANMODEB": "GTPE2_CHANNEL_PMASCANMODEB", - "DRPDO3": "GTPE2_CHANNEL_DRPDO3", - "PCSRSVDIN14": "GTPE2_CHANNEL_PCSRSVDIN14", - "TXDATA9": "GTPE2_CHANNEL_TXDATA9", - "PMARSVDOUT0": "GTPE2_CHANNEL_PMARSVDOUT0", - "RXUSERRDY": "GTPE2_CHANNEL_RXUSERRDY", - "RXDATA8": "GTPE2_CHANNEL_RXDATA8", - "RXDISPERR2": "GTPE2_CHANNEL_RXDISPERR2", - "RXSLIDE": "GTPE2_CHANNEL_RXSLIDE", - "TXPRBSSEL0": "GTPE2_CHANNEL_TXPRBSSEL0", - "RXOSINTSTARTED": "GTPE2_CHANNEL_RXOSINTSTARTED", - "TXMARGIN2": "GTPE2_CHANNEL_TXMARGIN2", - "SCANENB": "GTPE2_CHANNEL_SCANENB", - "RXDATA31": "GTPE2_CHANNEL_RXDATA31", - "PMARSVDIN4": "GTPE2_CHANNEL_PMARSVDIN4", - "PMASCANOUT1": "GTPE2_CHANNEL_PMASCANOUT1", - "RXPD1": "GTPE2_CHANNEL_RXPD1", - "TXDATA11": "GTPE2_CHANNEL_TXDATA11", - "PCSRSVDIN9": "GTPE2_CHANNEL_PCSRSVDIN9", - "TXDATA4": "GTPE2_CHANNEL_TXDATA4", - "PMARSVDIN1": "GTPE2_CHANNEL_PMARSVDIN1", - "RXADAPTSELTEST7": "GTPE2_CHANNEL_RXADAPTSELTEST7", - "DRPDI9": "GTPE2_CHANNEL_DRPDI9", - "RXSYSCLKSEL0": "GTPE2_CHANNEL_RXSYSCLKSEL0", - "RXADAPTSELTEST12": "GTPE2_CHANNEL_RXADAPTSELTEST12", - "TXSYNCALLIN": "GTPE2_CHANNEL_TXSYNCALLIN", - "RXBUFSTATUS0": "GTPE2_CHANNEL_RXBUFSTATUS0", - "TXPHOVRDEN": "GTPE2_CHANNEL_TXPHOVRDEN", - "RXPCOMMAALIGNEN": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "RXELECIDLEMODE0": "GTPE2_CHANNEL_RXELECIDLEMODE0", - "TXSYNCIN": "GTPE2_CHANNEL_TXSYNCIN", - "DRPCLK": "GTPE2_CHANNEL_DRPCLK", - "TXMAINCURSOR0": "GTPE2_CHANNEL_TXMAINCURSOR0", - "TXMARGIN1": "GTPE2_CHANNEL_TXMARGIN1", - "PCSRSVDIN0": "GTPE2_CHANNEL_PCSRSVDIN0", - "RXDATA5": "GTPE2_CHANNEL_RXDATA5", - "PMARSVDIN2": "GTPE2_CHANNEL_PMARSVDIN2", - "RXDATA0": "GTPE2_CHANNEL_RXDATA0", - "RXPHMONITOR4": "GTPE2_CHANNEL_RXPHMONITOR4", - "PMASCANOUT4": "GTPE2_CHANNEL_PMASCANOUT4", - "SCANOUT5": "GTPE2_CHANNEL_SCANOUT5", - "TSTIN0": "GTPE2_CHANNEL_TSTIN0", - "RXHEADERVALID": "GTPE2_CHANNEL_RXHEADERVALID", - "SCANOUT2": "GTPE2_CHANNEL_SCANOUT2", - "RXPHALIGN": "GTPE2_CHANNEL_RXPHALIGN", - "RXCDRLOCK": "GTPE2_CHANNEL_RXCDRLOCK", - "RXUSRCLK2": "GTPE2_CHANNEL_RXUSRCLK2", - "RXNOTINTABLE3": "GTPE2_CHANNEL_RXNOTINTABLE3", - "GTRSVD3": "GTPE2_CHANNEL_GTRSVD3", - "TXSEQUENCE0": "GTPE2_CHANNEL_TXSEQUENCE0", - "TXPIPPMSTEPSIZE3": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IPAD", - "y_coord": 11, - "type": "IPAD", - "site_pins": { - "O": "GTPE2_CHANNEL_RXN_PAD" - }, - "x_coord": 1, - "name": "X1Y11" - }, - { - "prefix": "IPAD", - "y_coord": 12, - "type": "IPAD", - "site_pins": { - "O": "GTPE2_CHANNEL_RXP_PAD" - }, - "x_coord": 1, - "name": "X1Y12" - }, - { - "prefix": "OPAD", - "y_coord": 1, - "type": "OPAD", - "site_pins": { - "I": "GTPE2_CHANNEL_TXN_PAD" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "OPAD", - "y_coord": 2, - "type": "OPAD", - "site_pins": { - "I": "GTPE2_CHANNEL_TXP_PAD" - }, - "x_coord": 0, - "name": "X0Y2" - } - ], "pips": { - "GTP_CHANNEL_1.GTPE2_IMUX11_10->GTPE2_CHANNEL_RXOSINTID03": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID03", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA24->GTPE2_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA24", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_0->GTPE2_CHANNEL_TXSEQUENCE6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX4_7->GTPE2_CHANNEL_RXADAPTSELTEST2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXNOTINTABLE3->GTPE2_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT6->GTPE2_LOGIC_OUTS_B13_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX2_0->GTPE2_CHANNEL_EYESCANMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX2_6->GTPE2_CHANNEL_TXPRECURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA28->GTPE2_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA28", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXCOMFINISH->GTPE2_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXCOMFINISH", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDISPERR0->GTPE2_LOGIC_OUTS_B22_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX47_9->GTPE2_CHANNEL_LOOPBACK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDLYSRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX13_4->GTPE2_CHANNEL_TSTIN10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX30_9->GTPE2_CHANNEL_RXCHBONDMASTER": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDMASTER", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT12->GTPE2_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX1_0->GTPE2_CHANNEL_RXCHBONDLEVEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX9_10->GTPE2_CHANNEL_PCSRSVDIN15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL0_6->GTPE2_CHANNEL_RXDLYSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYSRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX14_1->GTPE2_CHANNEL_TXPRBSFORCEERR": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSFORCEERR", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_GTRXOUTCLK_1->GTPE2_CHANNEL_RXOUTCLK_1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLK_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_GTRXOUTCLK_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTATUS0->GTPE2_LOGIC_OUTS_B21_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX20_6->GTPE2_CHANNEL_TXDATA6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR2->GTPE2_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHANBONDSEQ->GTPE2_LOGIC_OUTS_B8_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANBONDSEQ", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTDONE->GTPE2_LOGIC_OUTS_B3_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMWAKEDET->GTPE2_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMWAKEDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX2_3->GTPE2_CHANNEL_DRPADDR8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXNOTINTABLE2->GTPE2_LOGIC_OUTS_B14_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO6->GTPE2_LOGIC_OUTS_B22_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPMARESETDONE->GTPE2_LOGIC_OUTS_B12_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPMARESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXPMARESETDONE->GTPE2_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPMARESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA5->GTPE2_LOGIC_OUTS_B7_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_1->GTPE2_CHANNEL_TXSEQUENCE4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISCOMMA0->GTPE2_LOGIC_OUTS_B15_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX25_10->GTPE2_CHANNEL_PCSRSVDIN7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATEDONE->GTPE2_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXRATEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT5->GTPE2_LOGIC_OUTS_B13_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX44_0->GTPE2_CHANNEL_TXPHOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA2->GTPE2_LOGIC_OUTS_B4_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX9_7->GTPE2_CHANNEL_PCSRSVDIN12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX5_8->GTPE2_CHANNEL_TXOUTCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX34_4->GTPE2_CHANNEL_SETERRSTATUS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_SETERRSTATUS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT14->GTPE2_LOGIC_OUTS_B10_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_6->GTPE2_CHANNEL_GTRSVD3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX5_4->GTPE2_CHANNEL_TXMAINCURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX22_8->GTPE2_CHANNEL_RXPRBSSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX7_7->GTPE2_CHANNEL_TXPRECURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX44_9->GTPE2_CHANNEL_RXCOMMADETEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCOMMADETEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT13->GTPE2_LOGIC_OUTS_B1_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO2->GTPE2_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA7->GTPE2_LOGIC_OUTS_B5_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX41_7->GTPE2_CHANNEL_RXADAPTSELTEST6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCOUT->GTPE2_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSYNCOUT", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX45_2->GTPE2_CHANNEL_RXSYSCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA8->GTPE2_LOGIC_OUTS_B6_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX32_6->GTPE2_CHANNEL_DRPDI3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX24_5->GTPE2_CHANNEL_TSTIN14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX41_5->GTPE2_CHANNEL_RESETOVRD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RESETOVRD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDO3->GTPE2_LOGIC_OUTS_B16_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX5_2->GTPE2_CHANNEL_PMARSVDIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT11->GTPE2_LOGIC_OUTS_B21_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX31_8->GTPE2_CHANNEL_EYESCANTRIGGER": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANTRIGGER", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL0_8->GTPE2_CHANNEL_GTRXRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRXRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX34_7->GTPE2_CHANNEL_RXADAPTSELTEST4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX35_6->GTPE2_CHANNEL_TXPD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO8->GTPE2_LOGIC_OUTS_B12_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX21_8->GTPE2_CHANNEL_RXADAPTSELTEST13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR4->GTPE2_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL0_7->GTPE2_CHANNEL_RXCDRFREQRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRFREQRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX6_1->GTPE2_CHANNEL_RXGEARBOXSLIP": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXGEARBOXSLIP", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX24_4->GTPE2_CHANNEL_TSTIN13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX45_0->GTPE2_CHANNEL_RXDFEXYDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDFEXYDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA31->GTPE2_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA31", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_4->GTPE2_CHANNEL_GTRSVD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B15_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXHEADER1->GTPE2_LOGIC_OUTS_B23_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CLK0_5->GTPE2_CHANNEL_TXUSRCLK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSRCLK2", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX7_1->GTPE2_CHANNEL_TXSYNCIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA27->GTPE2_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA27", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX31_3->GTPE2_CHANNEL_TXCHARISK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXDLYSRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO3->GTPE2_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX2_7->GTPE2_CHANNEL_RXRATEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX22_9->GTPE2_CHANNEL_RXCHBONDI2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL1_10->GTPE2_CHANNEL_RXOOBRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOOBRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX31_7->GTPE2_CHANNEL_TXCHARISK0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX18_7->GTPE2_CHANNEL_TXDATA0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXN->GTPE2_CHANNEL_TXN_PAD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXN_PAD", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX37_10->GTPE2_CHANNEL_DRPDI12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX35_1->GTPE2_CHANNEL_TXSEQUENCE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX29_8->GTPE2_CHANNEL_RXOSHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX34_3->GTPE2_CHANNEL_DRPADDR7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX2_10->GTPE2_CHANNEL_RXOUTCLKSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_3->GTPE2_CHANNEL_TSTIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX11_3->GTPE2_CHANNEL_TXRATEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDISPERR1->GTPE2_LOGIC_OUTS_B22_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX39_6->GTPE2_CHANNEL_TXELECIDLE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXELECIDLE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX29_4->GTPE2_CHANNEL_TXCHARDISPMODE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX46_1->GTPE2_CHANNEL_RXPCSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPCSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXHEADER2->GTPE2_LOGIC_OUTS_B17_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX2_1->GTPE2_CHANNEL_TXCOMINIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMINIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX41_1->GTPE2_CHANNEL_RXMCOMMAALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXNOTINTABLE0->GTPE2_LOGIC_OUTS_B14_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISK3->GTPE2_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISCOMMA1->GTPE2_LOGIC_OUTS_B15_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX7_4->GTPE2_CHANNEL_TXPOSTCURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX12_3->GTPE2_CHANNEL_TXCHARDISPMODE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR4->GTPE2_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX45_4->GTPE2_CHANNEL_TSTIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX24_6->GTPE2_CHANNEL_TSTIN15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX0_3->GTPE2_CHANNEL_TXMAINCURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX10_9->GTPE2_CHANNEL_PMARSVDIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX43_5->GTPE2_CHANNEL_TXDLYUPDOWN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYUPDOWN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO7->GTPE2_LOGIC_OUTS_B4_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX35_8->GTPE2_CHANNEL_TXPIPPMSTEPSIZE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX29_6->GTPE2_CHANNEL_TXCHARDISPMODE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX39_0->GTPE2_CHANNEL_TXHEADER2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR1->GTPE2_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_2->GTPE2_CHANNEL_TSTIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX6_5->GTPE2_CHANNEL_TXDIFFCTRL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CLK1_5->GTPE2_CHANNEL_DMONITORCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DMONITORCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXVALID->GTPE2_LOGIC_OUTS_B20_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXVALID", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATEDONE->GTPE2_LOGIC_OUTS_B23_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXRATEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO9->GTPE2_LOGIC_OUTS_B4_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX3_3->GTPE2_CHANNEL_TXSTARTSEQ": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSTARTSEQ", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXHEADER0->GTPE2_LOGIC_OUTS_B19_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTROBESTARTED->GTPE2_LOGIC_OUTS_B0_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX3_9->GTPE2_CHANNEL_DRPDI7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX26_5->GTPE2_CHANNEL_GTRSVD10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX4_3->GTPE2_CHANNEL_TXMAINCURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHINITDONE->GTPE2_LOGIC_OUTS_B1_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPHINITDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX32_5->GTPE2_CHANNEL_DRPDI11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX34_2->GTPE2_CHANNEL_DRPADDR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA14->GTPE2_LOGIC_OUTS_B1_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX17_1->GTPE2_CHANNEL_TXDATA29": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA29", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSERR->GTPE2_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPRBSERR", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX15_7->GTPE2_CHANNEL_TX8B10BBYPASS0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX43_6->GTPE2_CHANNEL_TXRATE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX15_10->GTPE2_CHANNEL_RXOSINTID00": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID00", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX6_4->GTPE2_CHANNEL_TXPOSTCURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT10->GTPE2_LOGIC_OUTS_B13_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT1->GTPE2_LOGIC_OUTS_B0_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CLK1_4->GTPE2_CHANNEL_SIGVALIDCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_SIGVALIDCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX22_7->GTPE2_CHANNEL_TXDATA2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX6_10->GTPE2_CHANNEL_RXOSINTCFG1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX21_2->GTPE2_CHANNEL_TXDATA23": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA23", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX11_5->GTPE2_CHANNEL_TXDLYHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_1->GTPE2_CHANNEL_RXPCOMMAALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX7_0->GTPE2_CHANNEL_RXSYNCIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKPCS->GTPE2_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOUTCLKPCS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX45_3->GTPE2_CHANNEL_TXDLYSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRLOCK->GTPE2_LOGIC_OUTS_B17_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCDRLOCK", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX1_10->GTPE2_CHANNEL_RXELECIDLEMODE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX32_8->GTPE2_CHANNEL_RXDLYBYPASS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYBYPASS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA0->GTPE2_LOGIC_OUTS_B6_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX37_4->GTPE2_CHANNEL_TXDIFFPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX26_6->GTPE2_CHANNEL_GTRSVD11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX28_6->GTPE2_CHANNEL_RXDLYEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PLLREFCLK0->GTPE2_CHANNEL_PLL0REFCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL0REFCLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLREFCLK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTARTED->GTPE2_LOGIC_OUTS_B6_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTARTED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT9->GTPE2_LOGIC_OUTS_B13_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA22->GTPE2_LOGIC_OUTS_B1_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA22", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX24_9->GTPE2_CHANNEL_TSTIN18": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN18", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX39_1->GTPE2_CHANNEL_TXHEADER0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX23_9->GTPE2_CHANNEL_RXCHBONDI3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX28_10->GTPE2_CHANNEL_RXOSINTID01": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID01", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA25->GTPE2_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA25", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCDONE->GTPE2_LOGIC_OUTS_B14_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSYNCDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX5_10->GTPE2_CHANNEL_RXOUTCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCOUT->GTPE2_LOGIC_OUTS_B14_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXSYNCOUT", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX27_8->GTPE2_CHANNEL_TXCOMSAS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMSAS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO14->GTPE2_LOGIC_OUTS_B12_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO5->GTPE2_LOGIC_OUTS_B12_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CLK1_2->GTPE2_CHANNEL_TXPHDLYTSTCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX16_6->GTPE2_CHANNEL_TXDATA4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX25_2->GTPE2_CHANNEL_TXPHALIGN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHALIGN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX46_2->GTPE2_CHANNEL_RXOSCALRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSCALRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA17->GTPE2_LOGIC_OUTS_B2_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA17", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXHEADERVALID->GTPE2_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADERVALID", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX30_7->GTPE2_CHANNEL_RXPD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX45_7->GTPE2_CHANNEL_TXPISOPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPISOPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX16_10->GTPE2_CHANNEL_DRPDI15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX3_5->GTPE2_CHANNEL_TXDIFFCTRL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX0_2->GTPE2_CHANNEL_TX8B10BEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR0->GTPE2_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISCOMMA2->GTPE2_LOGIC_OUTS_B15_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_10->GTPE2_CHANNEL_TXDATA24": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA24", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX9_3->GTPE2_CHANNEL_PCSRSVDIN8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX46_4->GTPE2_CHANNEL_TXCHARDISPVAL3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO10->GTPE2_LOGIC_OUTS_B2_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX31_4->GTPE2_CHANNEL_TX8B10BBYPASS3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX6_0->GTPE2_CHANNEL_RXUSERRDY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSERRDY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX38_5->GTPE2_CHANNEL_TXSWING": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSWING", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL0_9->GTPE2_CHANNEL_RXLPMRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX33_5->GTPE2_CHANNEL_DRPDI10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX33_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX24_2->GTPE2_CHANNEL_TSTIN11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX32_2->GTPE2_CHANNEL_TXINHIBIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXINHIBIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX17_6->GTPE2_CHANNEL_TXDATA5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX13_10->GTPE2_CHANNEL_RXPRBSCNTRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSCNTRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT0->GTPE2_LOGIC_OUTS_B9_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO13->GTPE2_LOGIC_OUTS_B15_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX35_10->GTPE2_CHANNEL_RXOSINTCFG2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX44_10->GTPE2_CHANNEL_TXDATA26": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA26", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX18_3->GTPE2_CHANNEL_TXDATA16": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA16", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX4_10->GTPE2_CHANNEL_RXOUTCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO0->GTPE2_LOGIC_OUTS_B12_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMMADET->GTPE2_LOGIC_OUTS_B19_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMMADET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX19_9->GTPE2_CHANNEL_RXCHBONDI1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBYTEISALIGNED->GTPE2_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBYTEISALIGNED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_7->GTPE2_CHANNEL_GTRSVD4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX27_1->GTPE2_CHANNEL_TXSEQUENCE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_2->GTPE2_CHANNEL_TXCHARDISPVAL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX43_10->GTPE2_CHANNEL_RXLPMHFHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMHFHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTROBEDONE->GTPE2_LOGIC_OUTS_B0_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX30_10->GTPE2_CHANNEL_RXCHBONDSLAVE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDSLAVE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX25_3->GTPE2_CHANNEL_PCSRSVDIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCDONE->GTPE2_LOGIC_OUTS_B22_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXSYNCDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX20_1->GTPE2_CHANNEL_TXDATA30": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA30", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX3_10->GTPE2_CHANNEL_RXLPMLFOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR0->GTPE2_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX36_2->GTPE2_CHANNEL_RXSYNCALLIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCALLIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX35_2->GTPE2_CHANNEL_DRPADDR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA4->GTPE2_LOGIC_OUTS_B3_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX17_9->GTPE2_CHANNEL_RXCHBONDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT8->GTPE2_LOGIC_OUTS_B21_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX28_3->GTPE2_CHANNEL_DRPWE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPWE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO11->GTPE2_LOGIC_OUTS_B1_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX0_7->GTPE2_CHANNEL_RXADAPTSELTEST0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX39_5->GTPE2_CHANNEL_TXDETECTRX": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDETECTRX", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX3_2->GTPE2_CHANNEL_PMARSVDIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX38_6->GTPE2_CHANNEL_TXPD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_7->GTPE2_CHANNEL_RXPHDLYPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHDLYPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B7_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PMARSVDOUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX23_8->GTPE2_CHANNEL_RXPRBSSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX10_6->GTPE2_CHANNEL_DRPDI1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_6", - "is_pseudo": "0" - }, "GTP_CHANNEL_1.GTPE2_IMUX29_7->GTPE2_CHANNEL_RXADAPTSELTEST8": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST8", - "is_directional": "1", "src_wire": "GTPE2_IMUX29_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX41_6->GTPE2_CHANNEL_RXPHALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHALIGNEN", "is_directional": "1", - "src_wire": "GTPE2_IMUX41_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_5->GTPE2_CHANNEL_TSTIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX23_3->GTPE2_CHANNEL_TXDATA19": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA19", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX7_6->GTPE2_CHANNEL_TXPRECURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX32_9->GTPE2_CHANNEL_RXOSINTSTROBE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTSTROBE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX27_7->GTPE2_CHANNEL_RXPOLARITY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPOLARITY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX21_4->GTPE2_CHANNEL_TXDATA15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX25_6->GTPE2_CHANNEL_PCSRSVDIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX9_9->GTPE2_CHANNEL_PCSRSVDIN14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_6->GTPE2_CHANNEL_TSTIN5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCLKCORCNT1->GTPE2_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_8->GTPE2_CHANNEL_GTRSVD5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL1_7->GTPE2_CHANNEL_RXPMARESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPMARESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA9->GTPE2_LOGIC_OUTS_B2_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX6_6->GTPE2_CHANNEL_TXPRECURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX32_7->GTPE2_CHANNEL_TXPRECURSORINV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSORINV", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_10->GTPE2_CHANNEL_GTRSVD7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_2->GTPE2_CHANNEL_RXSYSCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT8->GTPE2_LOGIC_OUTS_B13_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT7->GTPE2_LOGIC_OUTS_B13_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL1_6->GTPE2_CHANNEL_RXBUFRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXBUFRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX38_8->GTPE2_CHANNEL_RXPRBSSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXRESETDONE->GTPE2_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA10->GTPE2_LOGIC_OUTS_B4_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX44_5->GTPE2_CHANNEL_TXDLYBYPASS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYBYPASS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFSTATUS1->GTPE2_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX33_2->GTPE2_CHANNEL_TXPHALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX33_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATAVALID0->GTPE2_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATAVALID0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT5->GTPE2_LOGIC_OUTS_B9_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX39_3->GTPE2_CHANNEL_DRPADDR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_GTTXOUTCLK_1->GTPE2_CHANNEL_TXOUTCLK_1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLK_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_GTTXOUTCLK_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX4_0->GTPE2_CHANNEL_RXCHBONDLEVEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMSASDET->GTPE2_LOGIC_OUTS_B18_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMSASDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX46_9->GTPE2_CHANNEL_LOOPBACK1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CLK0_9->GTPE2_CHANNEL_DRPCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PLLCLK0->GTPE2_CHANNEL_PLL0CLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL0CLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLCLK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX45_1->GTPE2_CHANNEL_RX8B10BEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RX8B10BEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX22_3->GTPE2_CHANNEL_TXDATA18": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA18", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_3->GTPE2_CHANNEL_GTRSVD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX39_4->GTPE2_CHANNEL_TXMARGIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_4->GTPE2_CHANNEL_TSTIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDISPERR3->GTPE2_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX4_8->GTPE2_CHANNEL_TXOUTCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX7_8->GTPE2_CHANNEL_TXPRBSSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT12->GTPE2_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPRDY->GTPE2_LOGIC_OUTS_B14_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPRDY", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX5_0->GTPE2_CHANNEL_RXCHBONDLEVEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX21_6->GTPE2_CHANNEL_TXDATA7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX19_3->GTPE2_CHANNEL_TXDATA17": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA17", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISK2->GTPE2_LOGIC_OUTS_B12_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX36_7->GTPE2_CHANNEL_RXOSINTNTRLEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTNTRLEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_5->GTPE2_CHANNEL_GTRSVD2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT2->GTPE2_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX1_3->GTPE2_CHANNEL_TXMAINCURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX17_10->GTPE2_CHANNEL_DRPDI14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX10_10->GTPE2_CHANNEL_RXOSINTID02": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID02", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR1->GTPE2_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX38_2->GTPE2_CHANNEL_DRPADDR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX13_6->GTPE2_CHANNEL_DRPDI2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHANISALIGNED->GTPE2_LOGIC_OUTS_B18_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANISALIGNED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMINITDET->GTPE2_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMINITDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT0->GTPE2_LOGIC_OUTS_B5_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_0->GTPE2_CHANNEL_RXSYNCMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA1->GTPE2_LOGIC_OUTS_B2_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX38_10->GTPE2_CHANNEL_RXOSINTCFG0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX35_4->GTPE2_CHANNEL_TXMARGIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX0_8->GTPE2_CHANNEL_RXADAPTSELTEST10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX13_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL1_9->GTPE2_CHANNEL_RXCDRRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXP_PAD->GTPE2_CHANNEL_RXP": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXP", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXP_PAD", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT10->GTPE2_LOGIC_OUTS_B21_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX47_4->GTPE2_CHANNEL_TXCHARISK3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX6_9->GTPE2_CHANNEL_DRPDI6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX27_10->GTPE2_CHANNEL_RXLPMHFOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX1_4->GTPE2_CHANNEL_TXMAINCURSOR6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX44_7->GTPE2_CHANNEL_RXADAPTSELTEST7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX43_9->GTPE2_CHANNEL_LOOPBACK0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPHALIGNDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_8->GTPE2_CHANNEL_RXDDIEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDDIEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX39_2->GTPE2_CHANNEL_DRPADDR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT7->GTPE2_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX37_7->GTPE2_CHANNEL_PMARSVDIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT4->GTPE2_LOGIC_OUTS_B9_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA18->GTPE2_LOGIC_OUTS_B4_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA18", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA16->GTPE2_LOGIC_OUTS_B6_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA16", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTATUS2->GTPE2_LOGIC_OUTS_B23_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX16_0->GTPE2_CHANNEL_TXSEQUENCE5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL1_8->GTPE2_CHANNEL_RXCDRRESETRSV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRRESETRSV", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CLK0_6->GTPE2_CHANNEL_RXUSRCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSRCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_10->GTPE2_CHANNEL_TSTIN9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKPCS->GTPE2_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXOUTCLKPCS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL1_4->GTPE2_CHANNEL_RXPHDLYRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHDLYRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTARTOFSEQ0->GTPE2_LOGIC_OUTS_B18_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISK1->GTPE2_LOGIC_OUTS_B12_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX31_1->GTPE2_CHANNEL_TXHEADER1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO15->GTPE2_LOGIC_OUTS_B4_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL0_10->GTPE2_CHANNEL_GTRESETSEL": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRESETSEL", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX13_0->GTPE2_CHANNEL_TXSYNCMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX21_1->GTPE2_CHANNEL_TXDATA31": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA31", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANDATAERROR->GTPE2_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_EYESCANDATAERROR", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX45_6->GTPE2_CHANNEL_DRPDI0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT6->GTPE2_LOGIC_OUTS_B9_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO4->GTPE2_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX22_5->GTPE2_CHANNEL_TXDATA10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX36_8->GTPE2_CHANNEL_RXADAPTSELTEST12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX30_8->GTPE2_CHANNEL_RXCDRHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX17_2->GTPE2_CHANNEL_TXDATA21": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA21", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX45_8->GTPE2_CHANNEL_EYESCANRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCLKCORCNT0->GTPE2_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX44_3->GTPE2_CHANNEL_DRPEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX41_0->GTPE2_CHANNEL_RXDLYOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX14_9->GTPE2_CHANNEL_RXPHALIGN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHALIGN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_0->GTPE2_CHANNEL_TXPIPPMEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX1_7->GTPE2_CHANNEL_RXADAPTSELTEST1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX41_10->GTPE2_CHANNEL_TXDATA25": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA25", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX35_3->GTPE2_CHANNEL_DRPADDR6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX9_5->GTPE2_CHANNEL_PCSRSVDIN10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX18_9->GTPE2_CHANNEL_RXCHBONDI0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX46_6->GTPE2_CHANNEL_TXRATE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL0_5->GTPE2_CHANNEL_GTTXRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTTXRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFSTATUS2->GTPE2_LOGIC_OUTS_B17_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX10_7->GTPE2_CHANNEL_TXBUFDIFFCTRL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX14_5->GTPE2_CHANNEL_TXDLYEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX5_9->GTPE2_CHANNEL_RXOSINTTESTOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_6->GTPE2_CHANNEL_TXCHARDISPVAL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX28_5->GTPE2_CHANNEL_TXSYSCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX18_5->GTPE2_CHANNEL_TXDATA8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX24_7->GTPE2_CHANNEL_TSTIN16": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN16", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PLLREFCLK1->GTPE2_CHANNEL_PLL1REFCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL1REFCLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLREFCLK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX46_3->GTPE2_CHANNEL_TXPIPPMPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA12->GTPE2_LOGIC_OUTS_B3_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBYTEREALIGN->GTPE2_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBYTEREALIGN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT9->GTPE2_LOGIC_OUTS_B21_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX19_5->GTPE2_CHANNEL_TXDATA9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B15_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PMARSVDOUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR3->GTPE2_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX13_7->GTPE2_CHANNEL_TXBUFDIFFCTRL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX2_5->GTPE2_CHANNEL_TXDIFFCTRL3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXGEARBOXREADY->GTPE2_LOGIC_OUTS_B23_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXGEARBOXREADY", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CLK1_8->GTPE2_CHANNEL_CLKRSVD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CLKRSVD1", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISK0->GTPE2_LOGIC_OUTS_B12_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTATUS1->GTPE2_LOGIC_OUTS_B17_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX46_0->GTPE2_CHANNEL_TXPCSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPCSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_7->GTPE2_CHANNEL_TSTIN6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX36_10->GTPE2_CHANNEL_DRPDI13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX15_9->GTPE2_CHANNEL_RXOSINTEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX25_4->GTPE2_CHANNEL_PCSRSVDIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA11->GTPE2_LOGIC_OUTS_B0_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX38_3->GTPE2_CHANNEL_DRPADDR5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX17_4->GTPE2_CHANNEL_TXDATA13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX38_9->GTPE2_CHANNEL_DRPDI5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX24_8->GTPE2_CHANNEL_TSTIN17": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN17", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX35_0->GTPE2_CHANNEL_TXSEQUENCE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX16_1->GTPE2_CHANNEL_TXDATA28": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA28", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO1->GTPE2_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHALIGNDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXELECIDLE->GTPE2_LOGIC_OUTS_B19_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXELECIDLE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT14->GTPE2_LOGIC_OUTS_B5_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX1_9->GTPE2_CHANNEL_RXOSINTHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX38_4->GTPE2_CHANNEL_TXMARGIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX44_1->GTPE2_CHANNEL_DMONFIFORESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DMONFIFORESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX10_3->GTPE2_CHANNEL_TXPIPPMOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX27_5->GTPE2_CHANNEL_TXPHINIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHINIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_8->GTPE2_CHANNEL_TSTIN7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFSTATUS0->GTPE2_LOGIC_OUTS_B23_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT3->GTPE2_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX20_4->GTPE2_CHANNEL_TXDATA14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX30_6->GTPE2_CHANNEL_TXPOSTCURSORINV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSORINV", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX12_5->GTPE2_CHANNEL_TXDLYOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX37_3->GTPE2_CHANNEL_TXPHDLYPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CLK0_7->GTPE2_CHANNEL_RXUSRCLK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSRCLK2", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX2_4->GTPE2_CHANNEL_TXPOSTCURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDO2->GTPE2_LOGIC_OUTS_B16_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX3_1->GTPE2_CHANNEL_TXCOMWAKE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMWAKE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXP->GTPE2_CHANNEL_TXP_PAD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXP_PAD", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXP", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX23_7->GTPE2_CHANNEL_TXDATA3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT1->GTPE2_LOGIC_OUTS_B9_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CLK1_7->GTPE2_CHANNEL_CLKRSVD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CLKRSVD0", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX25_9->GTPE2_CHANNEL_PCSRSVDIN6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX9_6->GTPE2_CHANNEL_PCSRSVDIN11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX23_5->GTPE2_CHANNEL_TXDATA11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX15_5->GTPE2_CHANNEL_TX8B10BBYPASS1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX37_8->GTPE2_CHANNEL_PMARSVDIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT11->GTPE2_LOGIC_OUTS_B5_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA6->GTPE2_LOGIC_OUTS_B1_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX28_4->GTPE2_CHANNEL_TXSYSCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX15_3->GTPE2_CHANNEL_TX8B10BBYPASS2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX40_9->GTPE2_CHANNEL_TSTIN8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA3->GTPE2_LOGIC_OUTS_B0_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX14_8->GTPE2_CHANNEL_RXCDROVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDROVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX0_9->GTPE2_CHANNEL_RXOSINTOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDO1->GTPE2_LOGIC_OUTS_B16_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX27_0->GTPE2_CHANNEL_TXSEQUENCE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA15->GTPE2_LOGIC_OUTS_B5_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX15_6->GTPE2_CHANNEL_RXRATE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_9->GTPE2_CHANNEL_GTRSVD6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISCOMMA3->GTPE2_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX31_5->GTPE2_CHANNEL_TXCHARISK1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PHYSTATUS->GTPE2_LOGIC_OUTS_B10_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PHYSTATUS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX3_4->GTPE2_CHANNEL_TXPOSTCURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_4->GTPE2_CHANNEL_TXCHARDISPVAL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX46_10->GTPE2_CHANNEL_RXOSINTCFG3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX16_2->GTPE2_CHANNEL_TXDATA20": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA20", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDISPERR2->GTPE2_LOGIC_OUTS_B22_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX14_6->GTPE2_CHANNEL_RXRATE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTARTOFSEQ1->GTPE2_LOGIC_OUTS_B11_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST8" }, "GTP_CHANNEL_1.GTPE2_IMUX3_0->GTPE2_CHANNEL_RXOSINTPD": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTPD", - "is_directional": "1", "src_wire": "GTPE2_IMUX3_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA30->GTPE2_LOGIC_OUTS_B1_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_3", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA30", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTPD" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR2->GTPE2_LOGIC_OUTS_B7_2": { + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA9->GTPE2_LOGIC_OUTS_B2_8": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_2", + "src_wire": "GTPE2_CHANNEL_RXDATA9", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_8" }, - "GTP_CHANNEL_1.GTPE2_IMUX26_7->GTPE2_CHANNEL_GTRSVD12": { + "GTP_CHANNEL_1.GTPE2_IMUX42_2->GTPE2_CHANNEL_RXSYSCLKSEL1": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD12", + "src_wire": "GTPE2_IMUX42_2", "is_directional": "1", - "src_wire": "GTPE2_IMUX26_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL1" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXNOTINTABLE1->GTPE2_LOGIC_OUTS_B14_8": { + "GTP_CHANNEL_1.GTPE2_IMUX36_7->GTPE2_CHANNEL_RXOSINTNTRLEN": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_8", + "src_wire": "GTPE2_IMUX36_7", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTNTRLEN" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO12->GTPE2_LOGIC_OUTS_B7_8": { + "GTP_CHANNEL_1.GTPE2_IMUX31_5->GTPE2_CHANNEL_TXCHARISK1": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_8", + "src_wire": "GTPE2_IMUX31_5", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT3->GTPE2_LOGIC_OUTS_B9_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX4_4->GTPE2_CHANNEL_TXMAINCURSOR5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHANREALIGN->GTPE2_LOGIC_OUTS_B23_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANREALIGN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR3->GTPE2_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX35_5->GTPE2_CHANNEL_TXDEEMPH": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDEEMPH", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX17_8->GTPE2_CHANNEL_RXADAPTSELTEST11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA23->GTPE2_LOGIC_OUTS_B5_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA23", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX24_10->GTPE2_CHANNEL_TSTIN19": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN19", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX3_6->GTPE2_CHANNEL_TXPRECURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX36_5->GTPE2_CHANNEL_TXPHDLYRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX3_8->GTPE2_CHANNEL_TXPRBSSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX25_8->GTPE2_CHANNEL_PCSRSVDIN5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX29_10->GTPE2_CHANNEL_TXDATA27": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA27", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX25_5->GTPE2_CHANNEL_PCSRSVDIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX19_7->GTPE2_CHANNEL_TXDATA1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX8_3->GTPE2_CHANNEL_TXPIPPMSEL": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSEL", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX5_5->GTPE2_CHANNEL_RXLPMLFHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMLFHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX30_3->GTPE2_CHANNEL_TXPOLARITY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOLARITY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX26_8->GTPE2_CHANNEL_GTRSVD13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX41_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX13_8->GTPE2_CHANNEL_RXOSOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PLLCLK1->GTPE2_CHANNEL_PLL1CLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL1CLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLCLK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX47_6->GTPE2_CHANNEL_TXRATE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX26_3->GTPE2_CHANNEL_GTRSVD8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX34_6->GTPE2_CHANNEL_DRPDI8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX44_2->GTPE2_CHANNEL_TXSYNCALLIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCALLIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX7_9->GTPE2_CHANNEL_DRPDI4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFSTATUS0->GTPE2_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX22_6->GTPE2_CHANNEL_TXPIPPMSTEPSIZE4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX45_5->GTPE2_CHANNEL_DRPDI9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX7_2->GTPE2_CHANNEL_RXLPMOSINTNTRLEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX26_4->GTPE2_CHANNEL_GTRSVD9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX14_10->GTPE2_CHANNEL_RXPHOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXRESETDONE->GTPE2_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATAVALID1->GTPE2_LOGIC_OUTS_B5_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATAVALID1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX26_9->GTPE2_CHANNEL_GTRSVD14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX5_7->GTPE2_CHANNEL_RXADAPTSELTEST3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX42_1->GTPE2_CHANNEL_RXSLIDE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSLIDE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT2->GTPE2_LOGIC_OUTS_B9_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX12_7->GTPE2_CHANNEL_TXBUFDIFFCTRL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX20_2->GTPE2_CHANNEL_TXDATA22": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA22", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX9_8->GTPE2_CHANNEL_PCSRSVDIN13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX11_7->GTPE2_CHANNEL_RXADAPTSELTEST9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX25_7->GTPE2_CHANNEL_PCSRSVDIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA19->GTPE2_LOGIC_OUTS_B0_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA19", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX6_7->GTPE2_CHANNEL_RXADAPTSELTEST5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK1" }, "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA21->GTPE2_LOGIC_OUTS_B7_5": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_5", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_RXDATA21", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX0_10->GTPE2_CHANNEL_RXELECIDLEMODE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE0", "is_directional": "1", - "src_wire": "GTPE2_IMUX0_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_5" }, - "GTP_CHANNEL_1.GTPE2_IMUX16_4->GTPE2_CHANNEL_TXDATA12": { + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT8->GTPE2_LOGIC_OUTS_B13_8": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA12", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT8", "is_directional": "1", - "src_wire": "GTPE2_IMUX16_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_8" }, - "GTP_CHANNEL_1.GTPE2_IMUX14_0->GTPE2_CHANNEL_TXPDELECIDLEMODE": { + "GTP_CHANNEL_1.GTPE2_IMUX30_9->GTPE2_CHANNEL_RXCHBONDMASTER": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPDELECIDLEMODE", + "src_wire": "GTPE2_IMUX30_9", "is_directional": "1", - "src_wire": "GTPE2_IMUX14_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDMASTER" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT13->GTPE2_LOGIC_OUTS_B9_2": { + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT8->GTPE2_LOGIC_OUTS_B21_7": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_2", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT8", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_7" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA13->GTPE2_LOGIC_OUTS_B7_7": { + "GTP_CHANNEL_1.GTPE2_IMUX1_10->GTPE2_CHANNEL_RXELECIDLEMODE1": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_7", + "src_wire": "GTPE2_IMUX1_10", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE1" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA29->GTPE2_LOGIC_OUTS_B7_3": { + "GTP_CHANNEL_1.GTPE2_IMUX44_5->GTPE2_CHANNEL_TXDLYBYPASS": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_3", + "src_wire": "GTPE2_IMUX44_5", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA29", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYBYPASS" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA20->GTPE2_LOGIC_OUTS_B3_5": { + "GTP_CHANNEL_1.GTPE2_IMUX30_7->GTPE2_CHANNEL_RXPD0": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_5", + "src_wire": "GTPE2_IMUX30_7", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA20", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX31_0->GTPE2_CHANNEL_TXUSERRDY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSERRDY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX26_10->GTPE2_CHANNEL_GTRSVD15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA26->GTPE2_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA26", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXN_PAD->GTPE2_CHANNEL_RXN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXN", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXN_PAD", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDO0->GTPE2_LOGIC_OUTS_B16_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_CTRL1_3->GTPE2_CHANNEL_TXPMARESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPMARESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPD0" }, "GTP_CHANNEL_1.GTPE2_IMUX11_6->GTPE2_CHANNEL_RXRATE2": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE2", - "is_directional": "1", "src_wire": "GTPE2_IMUX11_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_1.GTPE2_IMUX9_4->GTPE2_CHANNEL_PCSRSVDIN9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN9", "is_directional": "1", - "src_wire": "GTPE2_IMUX9_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE2" }, - "GTP_CHANNEL_1.GTPE2_IMUX28_8->GTPE2_CHANNEL_RXPD1": { + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDO0->GTPE2_LOGIC_OUTS_B16_10": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPD1", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO0", "is_directional": "1", - "src_wire": "GTPE2_IMUX28_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_10" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT15->GTPE2_LOGIC_OUTS_B15_4": { + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT11->GTPE2_LOGIC_OUTS_B21_4": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_4", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT11", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT15", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_4" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT4->GTPE2_LOGIC_OUTS_B13_4": { + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTATUS0->GTPE2_LOGIC_OUTS_B21_8": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_4", + "src_wire": "GTPE2_CHANNEL_RXSTATUS0", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_8" }, - "GTP_CHANNEL_1.GTPE2_IMUX7_5->GTPE2_CHANNEL_TXDIFFCTRL0": { + "GTP_CHANNEL_1.GTPE2_IMUX42_7->GTPE2_CHANNEL_GTRSVD4": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL0", + "src_wire": "GTPE2_IMUX42_7", "is_directional": "1", - "src_wire": "GTPE2_IMUX7_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD4" }, - "GTP_CHANNEL_1.GTPE2_IMUX1_8->GTPE2_CHANNEL_TXOUTCLKSEL2": { + "GTP_CHANNEL_1.GTPE2_IMUX2_1->GTPE2_CHANNEL_TXCOMINIT": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL2", + "src_wire": "GTPE2_IMUX2_1", "is_directional": "1", - "src_wire": "GTPE2_IMUX1_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMINIT" }, - "GTP_CHANNEL_1.GTPE2_IMUX29_2->GTPE2_CHANNEL_TXCHARDISPMODE2": { + "GTP_CHANNEL_1.GTPE2_IMUX16_6->GTPE2_CHANNEL_TXDATA4": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE2", + "src_wire": "GTPE2_IMUX16_6", "is_directional": "1", - "src_wire": "GTPE2_IMUX29_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA4" }, - "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFSTATUS1->GTPE2_LOGIC_OUTS_B19_10": { + "GTP_CHANNEL_1.GTPE2_CTRL1_10->GTPE2_CHANNEL_RXOOBRESET": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_10", + "src_wire": "GTPE2_CTRL1_10", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOOBRESET" }, - "GTP_CHANNEL_1.GTPE2_IMUX6_8->GTPE2_CHANNEL_TXPRBSSEL1": { + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA29->GTPE2_LOGIC_OUTS_B7_3": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL1", + "src_wire": "GTPE2_CHANNEL_RXDATA29", "is_directional": "1", - "src_wire": "GTPE2_IMUX6_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_3" }, - "GTP_CHANNEL_1.GTPE2_IMUX5_3->GTPE2_CHANNEL_TXMAINCURSOR0": { + "GTP_CHANNEL_1.GTPE2_IMUX32_6->GTPE2_CHANNEL_DRPDI3": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR0", + "src_wire": "GTPE2_IMUX32_6", "is_directional": "1", - "src_wire": "GTPE2_IMUX5_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI3" }, - "GTP_CHANNEL_1.GTPE2_IMUX7_3->GTPE2_CHANNEL_TXPOSTCURSOR4": { + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATAVALID0->GTPE2_LOGIC_OUTS_B13_1": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR4", + "src_wire": "GTPE2_CHANNEL_RXDATAVALID0", "is_directional": "1", - "src_wire": "GTPE2_IMUX7_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_1" }, - "GTP_CHANNEL_1.GTPE2_CTRL1_5->GTPE2_CHANNEL_CFGRESET": { + "GTP_CHANNEL_1.GTPE2_IMUX14_9->GTPE2_CHANNEL_RXPHALIGN": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CFGRESET", + "src_wire": "GTPE2_IMUX14_9", "is_directional": "1", - "src_wire": "GTPE2_CTRL1_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHALIGN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX3_1->GTPE2_CHANNEL_TXCOMWAKE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMWAKE" + }, + "GTP_CHANNEL_1.GTPE2_IMUX42_4->GTPE2_CHANNEL_GTRSVD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX14_6->GTPE2_CHANNEL_RXRATE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT2->GTPE2_LOGIC_OUTS_B9_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX34_4->GTPE2_CHANNEL_SETERRSTATUS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_SETERRSTATUS" + }, + "GTP_CHANNEL_1.GTPE2_IMUX5_0->GTPE2_CHANNEL_RXCHBONDLEVEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX5_8->GTPE2_CHANNEL_TXOUTCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO7->GTPE2_LOGIC_OUTS_B4_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX15_9->GTPE2_CHANNEL_RXOSINTEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX27_1->GTPE2_CHANNEL_TXSEQUENCE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX39_6->GTPE2_CHANNEL_TXELECIDLE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXELECIDLE" + }, + "GTP_CHANNEL_1.GTPE2_IMUX30_3->GTPE2_CHANNEL_TXPOLARITY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOLARITY" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXHEADER2->GTPE2_LOGIC_OUTS_B17_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX14_10->GTPE2_CHANNEL_RXPHOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX10_3->GTPE2_CHANNEL_TXPIPPMOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX38_4->GTPE2_CHANNEL_TXMARGIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX31_8->GTPE2_CHANNEL_EYESCANTRIGGER": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANTRIGGER" + }, + "GTP_CHANNEL_1.GTPE2_IMUX25_6->GTPE2_CHANNEL_PCSRSVDIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX45_4->GTPE2_CHANNEL_TSTIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX5_4->GTPE2_CHANNEL_TXMAINCURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX44_10->GTPE2_CHANNEL_TXDATA26": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA26" + }, + "GTP_CHANNEL_1.GTPE2_IMUX35_0->GTPE2_CHANNEL_TXSEQUENCE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_4->GTPE2_CHANNEL_TSTIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTROBEDONE->GTPE2_LOGIC_OUTS_B0_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISK1->GTPE2_LOGIC_OUTS_B12_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX47_6->GTPE2_CHANNEL_TXRATE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX9_3->GTPE2_CHANNEL_PCSRSVDIN8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX19_3->GTPE2_CHANNEL_TXDATA17": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA17" + }, + "GTP_CHANNEL_1.GTPE2_IMUX43_9->GTPE2_CHANNEL_LOOPBACK0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX36_2->GTPE2_CHANNEL_RXSYNCALLIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCALLIN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX26_3->GTPE2_CHANNEL_GTRSVD8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX26_10->GTPE2_CHANNEL_GTRSVD15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD15" + }, + "GTP_CHANNEL_1.GTPE2_IMUX26_9->GTPE2_CHANNEL_GTRSVD14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD14" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_EYESCANDATAERROR->GTPE2_LOGIC_OUTS_B18_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_EYESCANDATAERROR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXN_PAD->GTPE2_CHANNEL_RXN": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXN_PAD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_3->GTPE2_CHANNEL_TSTIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_0->GTPE2_CHANNEL_RXSYNCIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCIN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX9_9->GTPE2_CHANNEL_PCSRSVDIN14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN14" + }, + "GTP_CHANNEL_1.GTPE2_IMUX44_7->GTPE2_CHANNEL_RXADAPTSELTEST7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX42_10->GTPE2_CHANNEL_GTRSVD7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX28_5->GTPE2_CHANNEL_TXSYSCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT11->GTPE2_LOGIC_OUTS_B5_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX36_10->GTPE2_CHANNEL_DRPDI13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI13" + }, + "GTP_CHANNEL_1.GTPE2_IMUX31_0->GTPE2_CHANNEL_TXUSERRDY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSERRDY" + }, + "GTP_CHANNEL_1.GTPE2_IMUX35_10->GTPE2_CHANNEL_RXOSINTCFG2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHANBONDSEQ->GTPE2_LOGIC_OUTS_B8_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANBONDSEQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT6->GTPE2_LOGIC_OUTS_B13_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX39_3->GTPE2_CHANNEL_DRPADDR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX32_8->GTPE2_CHANNEL_RXDLYBYPASS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYBYPASS" + }, + "GTP_CHANNEL_1.GTPE2_IMUX26_5->GTPE2_CHANNEL_GTRSVD10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD10" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PLLCLK0->GTPE2_CHANNEL_PLL0CLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL0CLK" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXPMARESETDONE->GTPE2_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPMARESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA17->GTPE2_LOGIC_OUTS_B2_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_6" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXRESETDONE->GTPE2_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX21_4->GTPE2_CHANNEL_TXDATA15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA15" + }, + "GTP_CHANNEL_1.GTPE2_IMUX44_2->GTPE2_CHANNEL_TXSYNCALLIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCALLIN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX41_0->GTPE2_CHANNEL_RXDLYOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX44_3->GTPE2_CHANNEL_DRPEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX18_9->GTPE2_CHANNEL_RXCHBONDI0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PLLREFCLK1->GTPE2_CHANNEL_PLL1REFCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLREFCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL1REFCLK" + }, + "GTP_CHANNEL_1.GTPE2_CTRL0_5->GTPE2_CHANNEL_GTTXRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTTXRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX15_7->GTPE2_CHANNEL_TX8B10BBYPASS0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX41_7->GTPE2_CHANNEL_RXADAPTSELTEST6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX4_7->GTPE2_CHANNEL_RXADAPTSELTEST2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT12->GTPE2_LOGIC_OUTS_B15_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX3_9->GTPE2_CHANNEL_DRPDI7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX39_0->GTPE2_CHANNEL_TXHEADER2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX22_8->GTPE2_CHANNEL_RXPRBSSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDO3->GTPE2_LOGIC_OUTS_B16_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX38_8->GTPE2_CHANNEL_RXPRBSSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX35_5->GTPE2_CHANNEL_TXDEEMPH": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDEEMPH" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO1->GTPE2_LOGIC_OUTS_B22_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA23->GTPE2_LOGIC_OUTS_B5_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO14->GTPE2_LOGIC_OUTS_B12_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX3_2->GTPE2_CHANNEL_PMARSVDIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX24_8->GTPE2_CHANNEL_TSTIN17": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN17" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA27->GTPE2_LOGIC_OUTS_B0_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_4" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPRDY->GTPE2_LOGIC_OUTS_B14_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA31->GTPE2_LOGIC_OUTS_B5_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX34_6->GTPE2_CHANNEL_DRPDI8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX1_3->GTPE2_CHANNEL_TXMAINCURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR2" + }, + "GTP_CHANNEL_1.GTPE2_CLK1_2->GTPE2_CHANNEL_TXPHDLYTSTCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYTSTCLK" + }, + "GTP_CHANNEL_1.GTPE2_IMUX35_4->GTPE2_CHANNEL_TXMARGIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCOUT->GTPE2_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSYNCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX10_6->GTPE2_CHANNEL_DRPDI1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B7_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PMARSVDOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_6" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFSTATUS2->GTPE2_LOGIC_OUTS_B17_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX15_6->GTPE2_CHANNEL_RXRATE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX18_3->GTPE2_CHANNEL_TXDATA16": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA16" + }, + "GTP_CHANNEL_1.GTPE2_IMUX31_1->GTPE2_CHANNEL_TXHEADER1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_2->GTPE2_CHANNEL_TSTIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN1" + }, + "GTP_CHANNEL_1.GTPE2_CTRL0_6->GTPE2_CHANNEL_RXDLYSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYSRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX14_0->GTPE2_CHANNEL_TXPDELECIDLEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPDELECIDLEMODE" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA11->GTPE2_LOGIC_OUTS_B0_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX35_8->GTPE2_CHANNEL_TXPIPPMSTEPSIZE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXNOTINTABLE3->GTPE2_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX23_9->GTPE2_CHANNEL_RXCHBONDI3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX19_7->GTPE2_CHANNEL_TXDATA1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_10->GTPE2_CHANNEL_TXDATA24": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA24" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_1->GTPE2_CHANNEL_TXSYNCIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCIN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX35_3->GTPE2_CHANNEL_DRPADDR6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR6" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO10->GTPE2_LOGIC_OUTS_B2_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_8->GTPE2_CHANNEL_RXDDIEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDDIEN" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA16->GTPE2_LOGIC_OUTS_B6_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX41_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX0_2->GTPE2_CHANNEL_TX8B10BEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BEN" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT9->GTPE2_LOGIC_OUTS_B13_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX13_6->GTPE2_CHANNEL_DRPDI2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX17_6->GTPE2_CHANNEL_TXDATA5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX25_9->GTPE2_CHANNEL_PCSRSVDIN6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX3_10->GTPE2_CHANNEL_RXLPMLFOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMLFOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_CLK0_7->GTPE2_CHANNEL_RXUSRCLK2": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSRCLK2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT13->GTPE2_LOGIC_OUTS_B1_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX15_10->GTPE2_CHANNEL_RXOSINTID00": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID00" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO12->GTPE2_LOGIC_OUTS_B7_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_8" }, "GTP_CHANNEL_1.GTPE2_CLK0_4->GTPE2_CHANNEL_TXUSRCLK": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSRCLK", - "is_directional": "1", "src_wire": "GTPE2_CLK0_4", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSRCLK" + }, + "GTP_CHANNEL_1.GTPE2_IMUX23_7->GTPE2_CHANNEL_TXDATA3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX31_7->GTPE2_CHANNEL_TXCHARISK0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR0->GTPE2_LOGIC_OUTS_B13_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_0" + }, + "GTP_CHANNEL_1.GTPE2_CTRL1_9->GTPE2_CHANNEL_RXCDRRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRRESET" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA3->GTPE2_LOGIC_OUTS_B0_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX2_0->GTPE2_CHANNEL_EYESCANMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANMODE" + }, + "GTP_CHANNEL_1.GTPE2_IMUX32_2->GTPE2_CHANNEL_TXINHIBIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXINHIBIT" + }, + "GTP_CHANNEL_1.GTPE2_IMUX5_9->GTPE2_CHANNEL_RXOSINTTESTOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDO2->GTPE2_LOGIC_OUTS_B16_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX36_5->GTPE2_CHANNEL_TXPHDLYRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX17_10->GTPE2_CHANNEL_DRPDI14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI14" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO2->GTPE2_LOGIC_OUTS_B4_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT10->GTPE2_LOGIC_OUTS_B21_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTARTED->GTPE2_LOGIC_OUTS_B6_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTARTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_7" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT12->GTPE2_LOGIC_OUTS_B7_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX13_4->GTPE2_CHANNEL_TSTIN10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX28_6->GTPE2_CHANNEL_RXDLYEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYEN" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT0->GTPE2_LOGIC_OUTS_B5_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX16_0->GTPE2_CHANNEL_TXSEQUENCE5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX41_6->GTPE2_CHANNEL_RXPHALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHALIGNEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX12_7->GTPE2_CHANNEL_TXBUFDIFFCTRL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_7->GTPE2_CHANNEL_RXPHDLYPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHDLYPD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX2_6->GTPE2_CHANNEL_TXPRECURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA22->GTPE2_LOGIC_OUTS_B1_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR3->GTPE2_LOGIC_OUTS_B6_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMMADET->GTPE2_LOGIC_OUTS_B19_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMMADET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_7" + }, + "GTP_CHANNEL_1.GTPE2_CTRL1_5->GTPE2_CHANNEL_CFGRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CFGRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX42_8->GTPE2_CHANNEL_GTRSVD5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR2->GTPE2_LOGIC_OUTS_B7_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX6_0->GTPE2_CHANNEL_RXUSERRDY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSERRDY" + }, + "GTP_CHANNEL_1.GTPE2_IMUX28_10->GTPE2_CHANNEL_RXOSINTID01": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID01" + }, + "GTP_CHANNEL_1.GTPE2_CTRL1_8->GTPE2_CHANNEL_RXCDRRESETRSV": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRRESETRSV" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPHALIGNDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX12_3->GTPE2_CHANNEL_TXCHARDISPMODE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX45_3->GTPE2_CHANNEL_TXDLYSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYSRESET" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT5->GTPE2_LOGIC_OUTS_B9_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX26_6->GTPE2_CHANNEL_GTRSVD11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD11" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXP_PAD->GTPE2_CHANNEL_RXP": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXP_PAD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXP" + }, + "GTP_CHANNEL_1.GTPE2_IMUX13_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTDONE->GTPE2_LOGIC_OUTS_B3_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX37_8->GTPE2_CHANNEL_PMARSVDIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXGEARBOXREADY->GTPE2_LOGIC_OUTS_B23_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXGEARBOXREADY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX22_7->GTPE2_CHANNEL_TXDATA2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX43_10->GTPE2_CHANNEL_RXLPMHFHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMHFHOLD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX35_6->GTPE2_CHANNEL_TXPD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPD1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX0_3->GTPE2_CHANNEL_TXMAINCURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO15->GTPE2_LOGIC_OUTS_B4_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX4_0->GTPE2_CHANNEL_RXCHBONDLEVEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA1->GTPE2_LOGIC_OUTS_B2_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX18_7->GTPE2_CHANNEL_TXDATA0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA20->GTPE2_LOGIC_OUTS_B3_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_5" + }, + "GTP_CHANNEL_1.GTPE2_CLK0_9->GTPE2_CHANNEL_DRPCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPCLK" + }, + "GTP_CHANNEL_1.GTPE2_IMUX20_2->GTPE2_CHANNEL_TXDATA22": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA22" + }, + "GTP_CHANNEL_1.GTPE2_CLK0_5->GTPE2_CHANNEL_TXUSRCLK2": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSRCLK2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX24_6->GTPE2_CHANNEL_TSTIN15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN15" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDISPERR1->GTPE2_LOGIC_OUTS_B22_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX42_0->GTPE2_CHANNEL_TXPIPPMEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX19_5->GTPE2_CHANNEL_TXDATA9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX22_5->GTPE2_CHANNEL_TXDATA10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX42_1->GTPE2_CHANNEL_RXSLIDE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSLIDE" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXDLYSRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX22_3->GTPE2_CHANNEL_TXDATA18": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA18" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT14->GTPE2_LOGIC_OUTS_B5_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX45_7->GTPE2_CHANNEL_TXPISOPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPISOPD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX46_4->GTPE2_CHANNEL_TXCHARDISPVAL3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX10_10->GTPE2_CHANNEL_RXOSINTID02": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID02" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT4->GTPE2_LOGIC_OUTS_B9_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_6" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCLKCORCNT1->GTPE2_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT4->GTPE2_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_4" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT13->GTPE2_LOGIC_OUTS_B9_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX42_3->GTPE2_CHANNEL_GTRSVD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX4_10->GTPE2_CHANNEL_RXOUTCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B15_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_1" + }, + "GTP_CHANNEL_1.GTPE2_CLK1_7->GTPE2_CHANNEL_CLKRSVD0": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CLKRSVD0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX35_2->GTPE2_CHANNEL_DRPADDR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX34_3->GTPE2_CHANNEL_DRPADDR7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR7" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISK3->GTPE2_LOGIC_OUTS_B12_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX1_7->GTPE2_CHANNEL_RXADAPTSELTEST1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX45_6->GTPE2_CHANNEL_DRPDI0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXHEADER1->GTPE2_LOGIC_OUTS_B23_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX24_5->GTPE2_CHANNEL_TSTIN14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN14" + }, + "GTP_CHANNEL_1.GTPE2_IMUX1_0->GTPE2_CHANNEL_RXCHBONDLEVEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX5_3->GTPE2_CHANNEL_TXMAINCURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX0_8->GTPE2_CHANNEL_RXADAPTSELTEST10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX2_7->GTPE2_CHANNEL_RXRATEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATEMODE" + }, + "GTP_CHANNEL_1.GTPE2_CTRL0_8->GTPE2_CHANNEL_GTRXRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRXRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_3->GTPE2_CHANNEL_TXPIPPMSEL": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSEL" + }, + "GTP_CHANNEL_1.GTPE2_IMUX4_8->GTPE2_CHANNEL_TXOUTCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PLLREFCLK0->GTPE2_CHANNEL_PLL0REFCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLREFCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL0REFCLK" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_7->GTPE2_CHANNEL_TXPRECURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX27_8->GTPE2_CHANNEL_TXCOMSAS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMSAS" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFSTATUS0->GTPE2_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX3_4->GTPE2_CHANNEL_TXPOSTCURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX2_4->GTPE2_CHANNEL_TXPOSTCURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX0_10->GTPE2_CHANNEL_RXELECIDLEMODE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHANISALIGNED->GTPE2_LOGIC_OUTS_B18_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANISALIGNED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX37_10->GTPE2_CHANNEL_DRPDI12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI12" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPMARESETDONE->GTPE2_LOGIC_OUTS_B12_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPMARESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR3->GTPE2_LOGIC_OUTS_B3_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOSINTSTROBESTARTED->GTPE2_LOGIC_OUTS_B0_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_2->GTPE2_CHANNEL_RXLPMOSINTNTRLEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX45_8->GTPE2_CHANNEL_EYESCANRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX11_10->GTPE2_CHANNEL_RXOSINTID03": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID03" + }, + "GTP_CHANNEL_1.GTPE2_IMUX39_1->GTPE2_CHANNEL_TXHEADER0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMINITDET->GTPE2_LOGIC_OUTS_B20_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMINITDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX19_9->GTPE2_CHANNEL_RXCHBONDI1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B15_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PMARSVDOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX28_4->GTPE2_CHANNEL_TXSYSCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX46_2->GTPE2_CHANNEL_RXOSCALRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSCALRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX1_9->GTPE2_CHANNEL_RXOSINTHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTHOLD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX6_7->GTPE2_CHANNEL_RXADAPTSELTEST5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX46_3->GTPE2_CHANNEL_TXPIPPMPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMPD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_10->GTPE2_CHANNEL_TSTIN9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_9->GTPE2_CHANNEL_DRPDI4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX6_10->GTPE2_CHANNEL_RXOSINTCFG1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX9_10->GTPE2_CHANNEL_PCSRSVDIN15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN15" + }, + "GTP_CHANNEL_1.GTPE2_IMUX25_4->GTPE2_CHANNEL_PCSRSVDIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_0->GTPE2_CHANNEL_RXSYNCMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCMODE" + }, + "GTP_CHANNEL_1.GTPE2_IMUX46_1->GTPE2_CHANNEL_RXPCSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPCSRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_8->GTPE2_CHANNEL_TSTIN7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN7" + }, + "GTP_CHANNEL_1.GTPE2_CLK1_4->GTPE2_CHANNEL_SIGVALIDCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_SIGVALIDCLK" + }, + "GTP_CHANNEL_1.GTPE2_IMUX17_2->GTPE2_CHANNEL_TXDATA21": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA21" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHANREALIGN->GTPE2_LOGIC_OUTS_B23_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANREALIGN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX18_5->GTPE2_CHANNEL_TXDATA8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_8->GTPE2_CHANNEL_TXPRBSSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX3_6->GTPE2_CHANNEL_TXPRECURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX45_0->GTPE2_CHANNEL_RXDFEXYDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDFEXYDEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX30_6->GTPE2_CHANNEL_TXPOSTCURSORINV": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSORINV" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT10->GTPE2_LOGIC_OUTS_B13_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX21_2->GTPE2_CHANNEL_TXDATA23": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA23" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXPHINITDONE->GTPE2_LOGIC_OUTS_B1_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPHINITDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_10" + }, + "GTP_CHANNEL_1.GTPE2_CTRL0_10->GTPE2_CHANNEL_GTRESETSEL": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRESETSEL" + }, + "GTP_CHANNEL_1.GTPE2_IMUX16_4->GTPE2_CHANNEL_TXDATA12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA12" + }, + "GTP_CHANNEL_1.GTPE2_IMUX25_10->GTPE2_CHANNEL_PCSRSVDIN7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX26_8->GTPE2_CHANNEL_GTRSVD13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD13" + }, + "GTP_CHANNEL_1.GTPE2_IMUX17_9->GTPE2_CHANNEL_RXCHBONDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX6_4->GTPE2_CHANNEL_TXPOSTCURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA0->GTPE2_LOGIC_OUTS_B6_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX13_8->GTPE2_CHANNEL_RXOSOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX1_8->GTPE2_CHANNEL_TXOUTCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX32_9->GTPE2_CHANNEL_RXOSINTSTROBE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTSTROBE" + }, + "GTP_CHANNEL_1.GTPE2_IMUX47_4->GTPE2_CHANNEL_TXCHARISK3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX38_10->GTPE2_CHANNEL_RXOSINTCFG0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX5_7->GTPE2_CHANNEL_RXADAPTSELTEST3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX37_3->GTPE2_CHANNEL_TXPHDLYPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYPD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX39_5->GTPE2_CHANNEL_TXDETECTRX": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDETECTRX" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR1->GTPE2_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBYTEISALIGNED->GTPE2_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBYTEISALIGNED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX2_10->GTPE2_CHANNEL_RXOUTCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX37_4->GTPE2_CHANNEL_TXDIFFPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFPD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX44_9->GTPE2_CHANNEL_RXCOMMADETEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCOMMADETEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX32_5->GTPE2_CHANNEL_DRPDI11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI11" + }, + "GTP_CHANNEL_1.GTPE2_IMUX3_8->GTPE2_CHANNEL_TXPRBSSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX15_5->GTPE2_CHANNEL_TX8B10BBYPASS1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX25_5->GTPE2_CHANNEL_PCSRSVDIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN2" + }, + "GTP_CHANNEL_1.GTPE2_CLK1_8->GTPE2_CHANNEL_CLKRSVD1": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CLKRSVD1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX42_5->GTPE2_CHANNEL_GTRSVD2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT14->GTPE2_LOGIC_OUTS_B10_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO3->GTPE2_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX6_1->GTPE2_CHANNEL_RXGEARBOXSLIP": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXGEARBOXSLIP" + }, + "GTP_CHANNEL_1.GTPE2_IMUX26_4->GTPE2_CHANNEL_GTRSVD9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_1->GTPE2_CHANNEL_TXSEQUENCE4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX34_7->GTPE2_CHANNEL_RXADAPTSELTEST4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX5_10->GTPE2_CHANNEL_RXOUTCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL1" + }, + "GTP_CHANNEL_1.GTPE2_CTRL1_3->GTPE2_CHANNEL_TXPMARESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPMARESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX9_7->GTPE2_CHANNEL_PCSRSVDIN12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN12" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCDRLOCK->GTPE2_LOGIC_OUTS_B17_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCDRLOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX38_6->GTPE2_CHANNEL_TXPD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPD0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFSTATUS0->GTPE2_LOGIC_OUTS_B23_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_10" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT1->GTPE2_LOGIC_OUTS_B9_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX33_5->GTPE2_CHANNEL_DRPDI10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX33_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX13_0->GTPE2_CHANNEL_TXSYNCMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCMODE" + }, + "GTP_CHANNEL_1.GTPE2_IMUX0_7->GTPE2_CHANNEL_RXADAPTSELTEST0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PLLCLK1->GTPE2_CHANNEL_PLL1CLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL1CLK" + }, + "GTP_CHANNEL_1.GTPE2_IMUX25_2->GTPE2_CHANNEL_TXPHALIGN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHALIGN" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDISPERR2->GTPE2_LOGIC_OUTS_B22_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX31_4->GTPE2_CHANNEL_TX8B10BBYPASS3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX10_7->GTPE2_CHANNEL_TXBUFDIFFCTRL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX16_10->GTPE2_CHANNEL_DRPDI15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI15" + }, + "GTP_CHANNEL_1.GTPE2_IMUX17_4->GTPE2_CHANNEL_TXDATA13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA13" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTATUS1->GTPE2_LOGIC_OUTS_B17_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX38_9->GTPE2_CHANNEL_DRPDI5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI5" + }, + "GTP_CHANNEL_1.GTPE2_CTRL0_7->GTPE2_CHANNEL_RXCDRFREQRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRFREQRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX14_5->GTPE2_CHANNEL_TXDLYEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX14_8->GTPE2_CHANNEL_RXCDROVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDROVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX9_4->GTPE2_CHANNEL_PCSRSVDIN9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX38_3->GTPE2_CHANNEL_DRPADDR5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXNOTINTABLE1->GTPE2_LOGIC_OUTS_B14_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_4->GTPE2_CHANNEL_TXPOSTCURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX34_2->GTPE2_CHANNEL_DRPADDR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX2_5->GTPE2_CHANNEL_TXDIFFCTRL3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_6->GTPE2_CHANNEL_TXPRECURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT2->GTPE2_LOGIC_OUTS_B13_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTARTOFSEQ0->GTPE2_LOGIC_OUTS_B18_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_8" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT3->GTPE2_LOGIC_OUTS_B13_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA7->GTPE2_LOGIC_OUTS_B5_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_9" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMWAKEDET->GTPE2_LOGIC_OUTS_B12_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMWAKEDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA24->GTPE2_LOGIC_OUTS_B6_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_9->GTPE2_CHANNEL_TSTIN8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_3->GTPE2_CHANNEL_TXPOSTCURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX3_5->GTPE2_CHANNEL_TXDIFFCTRL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX23_3->GTPE2_CHANNEL_TXDATA19": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA19" + }, + "GTP_CHANNEL_1.GTPE2_IMUX9_5->GTPE2_CHANNEL_PCSRSVDIN10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN10" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO13->GTPE2_LOGIC_OUTS_B15_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_8" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO5->GTPE2_LOGIC_OUTS_B12_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PHYSTATUS->GTPE2_LOGIC_OUTS_B10_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PHYSTATUS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_4->GTPE2_CHANNEL_TXCHARDISPVAL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT1->GTPE2_LOGIC_OUTS_B0_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX39_4->GTPE2_CHANNEL_TXMARGIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO6->GTPE2_LOGIC_OUTS_B22_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA4->GTPE2_LOGIC_OUTS_B3_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_9" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA25->GTPE2_LOGIC_OUTS_B2_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_4" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA19->GTPE2_LOGIC_OUTS_B0_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_6->GTPE2_CHANNEL_TXCHARDISPVAL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL0" + }, + "GTP_CHANNEL_1.GTPE2_CTRL0_9->GTPE2_CHANNEL_RXLPMRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMRESET" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_GTTXOUTCLK_1->GTPE2_CHANNEL_TXOUTCLK_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_GTTXOUTCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLK_1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDISPERR0->GTPE2_LOGIC_OUTS_B22_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX33_2->GTPE2_CHANNEL_TXPHALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX33_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHALIGNEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX39_2->GTPE2_CHANNEL_DRPADDR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO11->GTPE2_LOGIC_OUTS_B1_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX12_5->GTPE2_CHANNEL_TXDLYOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX6_8->GTPE2_CHANNEL_TXPRBSSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXVALID->GTPE2_LOGIC_OUTS_B20_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXVALID", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_9" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR4->GTPE2_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX20_6->GTPE2_CHANNEL_TXDATA6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX20_4->GTPE2_CHANNEL_TXDATA14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA14" + }, + "GTP_CHANNEL_1.GTPE2_IMUX27_0->GTPE2_CHANNEL_TXSEQUENCE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBYTEREALIGN->GTPE2_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBYTEREALIGN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISCOMMA1->GTPE2_LOGIC_OUTS_B15_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX22_9->GTPE2_CHANNEL_RXCHBONDI2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA30->GTPE2_LOGIC_OUTS_B1_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_1->GTPE2_CHANNEL_RXPCOMMAALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPCOMMAALIGNEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX37_7->GTPE2_CHANNEL_PMARSVDIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX29_6->GTPE2_CHANNEL_TXCHARDISPMODE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX22_6->GTPE2_CHANNEL_TXPIPPMSTEPSIZE4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX3_3->GTPE2_CHANNEL_TXSTARTSEQ": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSTARTSEQ" + }, + "GTP_CHANNEL_1.GTPE2_IMUX42_9->GTPE2_CHANNEL_GTRSVD6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD6" }, "GTP_CHANNEL_1.GTPE2_IMUX24_3->GTPE2_CHANNEL_TSTIN12": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN12", - "is_directional": "1", "src_wire": "GTPE2_IMUX24_3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN12" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO9->GTPE2_LOGIC_OUTS_B4_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX47_9->GTPE2_CHANNEL_LOOPBACK2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT7->GTPE2_LOGIC_OUTS_B13_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX17_1->GTPE2_CHANNEL_TXDATA29": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA29" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXBUFSTATUS1->GTPE2_LOGIC_OUTS_B19_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX45_5->GTPE2_CHANNEL_DRPDI9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI9" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXP->GTPE2_CHANNEL_TXP_PAD": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXP_PAD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX41_1->GTPE2_CHANNEL_RXMCOMMAALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXMCOMMAALIGNEN" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTARTOFSEQ1->GTPE2_LOGIC_OUTS_B11_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX4_4->GTPE2_CHANNEL_TXMAINCURSOR5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR5" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR1->GTPE2_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_GTRXOUTCLK_1->GTPE2_CHANNEL_RXOUTCLK_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_GTRXOUTCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLK_1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX29_4->GTPE2_CHANNEL_TXCHARDISPMODE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA8->GTPE2_LOGIC_OUTS_B6_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_8" + }, + "GTP_CHANNEL_1.GTPE2_IMUX9_8->GTPE2_CHANNEL_PCSRSVDIN13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN13" + }, + "GTP_CHANNEL_1.GTPE2_IMUX15_3->GTPE2_CHANNEL_TX8B10BBYPASS2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS2" + }, + "GTP_CHANNEL_1.GTPE2_CTRL1_7->GTPE2_CHANNEL_RXPMARESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPMARESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX23_8->GTPE2_CHANNEL_RXPRBSSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX27_5->GTPE2_CHANNEL_TXPHINIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHINIT" + }, + "GTP_CHANNEL_1.GTPE2_IMUX1_4->GTPE2_CHANNEL_TXMAINCURSOR6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX4_3->GTPE2_CHANNEL_TXMAINCURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHSLIPMONITOR2->GTPE2_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA2->GTPE2_LOGIC_OUTS_B4_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX45_2->GTPE2_CHANNEL_RXSYSCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX21_1->GTPE2_CHANNEL_TXDATA31": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA31" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR4->GTPE2_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX31_3->GTPE2_CHANNEL_TXCHARISK2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISCOMMA2->GTPE2_LOGIC_OUTS_B15_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX24_4->GTPE2_CHANNEL_TSTIN13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN13" + }, + "GTP_CHANNEL_1.GTPE2_IMUX25_7->GTPE2_CHANNEL_PCSRSVDIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX46_10->GTPE2_CHANNEL_RXOSINTCFG3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX17_8->GTPE2_CHANNEL_RXADAPTSELTEST11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST11" + }, + "GTP_CHANNEL_1.GTPE2_IMUX2_3->GTPE2_CHANNEL_DRPADDR8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR8" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA13->GTPE2_LOGIC_OUTS_B7_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_7" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA15->GTPE2_LOGIC_OUTS_B5_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX0_9->GTPE2_CHANNEL_RXOSINTOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX35_1->GTPE2_CHANNEL_TXSEQUENCE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXRATEDONE->GTPE2_LOGIC_OUTS_B23_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXRATEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX24_7->GTPE2_CHANNEL_TSTIN16": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN16" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA18->GTPE2_LOGIC_OUTS_B4_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_6" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT0->GTPE2_LOGIC_OUTS_B9_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_10" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT5->GTPE2_LOGIC_OUTS_B13_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_5" + }, + "GTP_CHANNEL_1.GTPE2_CLK1_5->GTPE2_CHANNEL_DMONITORCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DMONITORCLK" + }, + "GTP_CHANNEL_1.GTPE2_IMUX20_1->GTPE2_CHANNEL_TXDATA30": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA30" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT6->GTPE2_LOGIC_OUTS_B9_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX11_7->GTPE2_CHANNEL_RXADAPTSELTEST9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST9" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA12->GTPE2_LOGIC_OUTS_B3_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX16_1->GTPE2_CHANNEL_TXDATA28": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA28" + }, + "GTP_CHANNEL_1.GTPE2_IMUX6_6->GTPE2_CHANNEL_TXPRECURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDLYSRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXN->GTPE2_CHANNEL_TXN_PAD": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXN_PAD" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA14->GTPE2_LOGIC_OUTS_B1_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_7" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSTATUS2->GTPE2_LOGIC_OUTS_B23_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_8" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXRESETDONE->GTPE2_LOGIC_OUTS_B18_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_1" + }, + "GTP_CHANNEL_1.GTPE2_CTRL1_4->GTPE2_CHANNEL_RXPHDLYRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHDLYRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX21_6->GTPE2_CHANNEL_TXDATA7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX27_10->GTPE2_CHANNEL_RXLPMHFOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMHFOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISK2->GTPE2_LOGIC_OUTS_B12_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX24_9->GTPE2_CHANNEL_TSTIN18": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN18" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISK0->GTPE2_LOGIC_OUTS_B12_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX26_7->GTPE2_CHANNEL_GTRSVD12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD12" + }, + "GTP_CHANNEL_1.GTPE2_IMUX29_10->GTPE2_CHANNEL_TXDATA27": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA27" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_PCSRSVDOUT15->GTPE2_LOGIC_OUTS_B15_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_2->GTPE2_CHANNEL_TXCHARDISPVAL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX45_1->GTPE2_CHANNEL_RX8B10BEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RX8B10BEN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX46_9->GTPE2_CHANNEL_LOOPBACK1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX14_1->GTPE2_CHANNEL_TXPRBSFORCEERR": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSFORCEERR" + }, + "GTP_CHANNEL_1.GTPE2_IMUX44_1->GTPE2_CHANNEL_DMONFIFORESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DMONFIFORESET" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCOMSASDET->GTPE2_LOGIC_OUTS_B18_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMSASDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_7" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO8->GTPE2_LOGIC_OUTS_B12_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX11_5->GTPE2_CHANNEL_TXDLYHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYHOLD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX6_9->GTPE2_CHANNEL_DRPDI6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX30_10->GTPE2_CHANNEL_RXCHBONDSLAVE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDSLAVE" + }, + "GTP_CHANNEL_1.GTPE2_IMUX25_3->GTPE2_CHANNEL_PCSRSVDIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX46_0->GTPE2_CHANNEL_TXPCSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPCSRESET" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHMONITOR0->GTPE2_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXELECIDLE->GTPE2_LOGIC_OUTS_B19_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_8" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA5->GTPE2_LOGIC_OUTS_B7_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX28_8->GTPE2_CHANNEL_RXPD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPD1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX9_6->GTPE2_CHANNEL_PCSRSVDIN11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN11" + }, + "GTP_CHANNEL_1.GTPE2_IMUX30_8->GTPE2_CHANNEL_RXCDRHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRHOLD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX44_0->GTPE2_CHANNEL_TXPHOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHOVRDEN" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCDONE->GTPE2_LOGIC_OUTS_B22_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXSYNCDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX46_6->GTPE2_CHANNEL_TXRATE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHBONDO1->GTPE2_LOGIC_OUTS_B16_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_7->GTPE2_CHANNEL_TSTIN6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN6" + }, + "GTP_CHANNEL_1.GTPE2_CTRL1_6->GTPE2_CHANNEL_RXBUFRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXBUFRESET" + }, + "GTP_CHANNEL_1.GTPE2_IMUX29_8->GTPE2_CHANNEL_RXOSHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSHOLD" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA10->GTPE2_LOGIC_OUTS_B4_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_8" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXHEADERVALID->GTPE2_LOGIC_OUTS_B14_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADERVALID", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDISPERR3->GTPE2_LOGIC_OUTS_B22_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_4" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCLKCORCNT0->GTPE2_LOGIC_OUTS_B11_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX16_2->GTPE2_CHANNEL_TXDATA20": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA20" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHALIGNDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_4" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXOUTCLKPCS->GTPE2_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXOUTCLKPCS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_4" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXPRBSERR->GTPE2_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPRBSERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXCOMFINISH->GTPE2_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXCOMFINISH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX10_9->GTPE2_CHANNEL_PMARSVDIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN2" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO0->GTPE2_LOGIC_OUTS_B12_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_6->GTPE2_CHANNEL_TSTIN5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX24_2->GTPE2_CHANNEL_TSTIN11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN11" + }, + "GTP_CHANNEL_1.GTPE2_IMUX28_3->GTPE2_CHANNEL_DRPWE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPWE" + }, + "GTP_CHANNEL_1.GTPE2_IMUX6_5->GTPE2_CHANNEL_TXDIFFCTRL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXNOTINTABLE2->GTPE2_LOGIC_OUTS_B14_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_6" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT3->GTPE2_LOGIC_OUTS_B9_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_7" + }, + "GTP_CHANNEL_1.GTPE2_IMUX27_7->GTPE2_CHANNEL_RXPOLARITY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPOLARITY" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISCOMMA0->GTPE2_LOGIC_OUTS_B15_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_9" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXCHARISCOMMA3->GTPE2_LOGIC_OUTS_B15_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXRATEDONE->GTPE2_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXRATEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX13_7->GTPE2_CHANNEL_TXBUFDIFFCTRL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX13_10->GTPE2_CHANNEL_RXPRBSCNTRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSCNTRESET" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXHEADER0->GTPE2_LOGIC_OUTS_B19_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX29_2->GTPE2_CHANNEL_TXCHARDISPMODE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX41_5->GTPE2_CHANNEL_RESETOVRD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RESETOVRD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX23_5->GTPE2_CHANNEL_TXDATA11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA11" + }, + "GTP_CHANNEL_1.GTPE2_CLK0_6->GTPE2_CHANNEL_RXUSRCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSRCLK" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT9->GTPE2_LOGIC_OUTS_B21_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX38_2->GTPE2_CHANNEL_DRPADDR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXOUTCLKPCS->GTPE2_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOUTCLKPCS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_1" + }, + "GTP_CHANNEL_1.GTPE2_IMUX40_5->GTPE2_CHANNEL_TSTIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN4" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DMONITOROUT7->GTPE2_LOGIC_OUTS_B9_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX7_5->GTPE2_CHANNEL_TXDIFFCTRL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL0" + }, + "GTP_CHANNEL_1.GTPE2_IMUX8_0->GTPE2_CHANNEL_TXSEQUENCE6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE6" + }, + "GTP_CHANNEL_1.GTPE2_IMUX32_7->GTPE2_CHANNEL_TXPRECURSORINV": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSORINV" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATAVALID1->GTPE2_LOGIC_OUTS_B5_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATAVALID1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_1" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXSYNCOUT->GTPE2_LOGIC_OUTS_B14_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXSYNCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_7" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_TXBUFSTATUS1->GTPE2_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_0" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXNOTINTABLE0->GTPE2_LOGIC_OUTS_B14_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_10" + }, + "GTP_CHANNEL_1.GTPE2_IMUX5_5->GTPE2_CHANNEL_RXLPMLFHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMLFHOLD" + }, + "GTP_CHANNEL_1.GTPE2_IMUX43_6->GTPE2_CHANNEL_TXRATE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE2" + }, + "GTP_CHANNEL_1.GTPE2_IMUX36_8->GTPE2_CHANNEL_RXADAPTSELTEST12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST12" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA28->GTPE2_LOGIC_OUTS_B3_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXSYNCDONE->GTPE2_LOGIC_OUTS_B14_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSYNCDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_9" + }, + "GTP_CHANNEL_1.GTPE2_IMUX38_5->GTPE2_CHANNEL_TXSWING": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSWING" + }, + "GTP_CHANNEL_1.GTPE2_IMUX42_6->GTPE2_CHANNEL_GTRSVD3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX24_10->GTPE2_CHANNEL_TSTIN19": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN19" + }, + "GTP_CHANNEL_1.GTPE2_IMUX43_5->GTPE2_CHANNEL_TXDLYUPDOWN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYUPDOWN" + }, + "GTP_CHANNEL_1.GTPE2_IMUX11_3->GTPE2_CHANNEL_TXRATEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATEMODE" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA26->GTPE2_LOGIC_OUTS_B4_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_4" + }, + "GTP_CHANNEL_1.GTPE2_IMUX21_8->GTPE2_CHANNEL_RXADAPTSELTEST13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST13" + }, + "GTP_CHANNEL_1.GTPE2_IMUX41_10->GTPE2_CHANNEL_TXDATA25": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA25" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_DRPDO4->GTPE2_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_3" + }, + "GTP_CHANNEL_1.GTPE2_IMUX25_8->GTPE2_CHANNEL_PCSRSVDIN5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN5" + }, + "GTP_CHANNEL_1.GTPE2_IMUX5_2->GTPE2_CHANNEL_PMARSVDIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN3" + }, + "GTP_CHANNEL_1.GTPE2_CHANNEL_RXDATA6->GTPE2_LOGIC_OUTS_B1_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_9" } }, - "tile_type": "GTP_CHANNEL_1" + "wires": [ + "GTPE2_IMUX5_7", + "GTPE2_IMUX14_1", + "GTPE2_BYP0_6", + "GTPE2_IMUX23_2", + "GTPE2_BYP0_5", + "GTPE2_IMUX19_10", + "GTPE2_LOGIC_OUTS_B20_6", + "GTPE2_LOGIC_OUTS_B13_0", + "GTPE2_IMUX25_9", + "GTPE2_IMUX18_8", + "GTPE2_IMUX44_3", + "GTPE2_LOGIC_OUTS_B20_10", + "GTPE2_LOGIC_OUTS_B11_9", + "GTPE2_BYP1_10", + "GTPE2_IMUX26_0", + "GTPE2_LOGIC_OUTS_B19_5", + "GTPE2_IMUX5_2", + "GTPE2_CHANNEL_RXOSINTCFG3", + "GTPE2_IMUX30_3", + "GTPE2_CHANNEL_TXSEQUENCE6", + "GTPE2_LOGIC_OUTS_B9_4", + "GTPE2_IMUX18_1", + "GTPE2_CLK0_4", + "GTPE2_CHANNEL_DMONITOROUT2", + "GTPE2_IMUX42_3", + "GTPE2_CTRL1_5", + "GTPE2_IMUX22_3", + "GTPE2_CHANNEL_GTRSVD5", + "GTPE2_CHANNEL_RXLPMRESET", + "GTPE2_LOGIC_OUTS_B23_8", + "GTPE2_CHANNEL_TXPRBSFORCEERR", + "GTPE2_LOGIC_OUTS_B1_9", + "GTPE2_IMUX45_9", + "GTPE2_IMUX34_7", + "GTPE2_LOGIC_OUTS_B2_0", + "GTPE2_IMUX24_9", + "GTPE2_LOGIC_OUTS_B18_2", + "GTPE2_CLK1_1", + "GTPE2_CHANNEL_RXPOLARITY", + "GTPE2_CHANNEL_TSTIN14", + "GTPE2_LOGIC_OUTS_B22_9", + "GTPE2_CHANNEL_PCSRSVDOUT5", + "GTPE2_LOGIC_OUTS_B8_6", + "GTPE2_IMUX23_4", + "GTPE2_LOGIC_OUTS_B22_10", + "GTPE2_LOGIC_OUTS_B6_9", + "GTPE2_IMUX33_7", + "GTPE2_CHANNEL_RXRATE0", + "GTPE2_FAN5_8", + "GTPE2_IMUX25_3", + "GTPE2_IMUX23_5", + "GTPE2_BYP5_10", + "GTPE2_IMUX19_6", + "GTPE2_CHANNEL_RXP", + "GTPE2_CHANNEL_TXDATA11", + "GTPE2_FAN7_2", + "GTPE2_CHANNEL_TSTPDOVRDB", + "GTPE2_CHANNEL_RXOUTCLKSEL2", + "GTPE2_CHANNEL_RXSYNCALLIN", + "GTPE2_FAN3_3", + "GTPE2_CHANNEL_DRPDO6", + "GTPE2_IMUX2_4", + "GTPE2_IMUX37_6", + "GTPE2_IMUX17_2", + "GTPE2_IMUX6_6", + "GTPE2_CHANNEL_TSTCLK1", + "GTPE2_CHANNEL_TXDATA2", + "GTPE2_IMUX0_2", + "GTPE2_IMUX28_0", + "GTPE2_CHANNEL_RXCLKCORCNT1", + "GTPE2_LOGIC_OUTS_B21_1", + "GTPE2_LOGIC_OUTS_B16_9", + "GTPE2_IMUX33_10", + "GTPE2_IMUX42_4", + "GTPE2_CHANNEL_RXOSINTID01", + "GTPE2_IMUX26_8", + "GTPE2_IMUX0_9", + "GTPE2_BYP5_3", + "GTPE2_IMUX38_1", + "GTPE2_CHANNEL_RXSYNCMODE", + "GTPE2_FAN7_10", + "GTPE2_IMUX22_4", + "GTPE2_IMUX43_1", + "GTPE2_CHANNEL_RXDATA9", + "GTPE2_IMUX9_5", + "GTPE2_BYP1_3", + "GTPE2_CHANNEL_DMONFIFORESET", + "GTPE2_CHANNEL_DMONITOROUT11", + "GTPE2_IMUX16_3", + "GTPE2_CHANNEL_TXSEQUENCE3", + "GTPE2_CHANNEL_RXCHBONDI2", + "GTPE2_IMUX0_4", + "GTPE2_IMUX24_2", + "GTPE2_IMUX3_2", + "GTPE2_LOGIC_OUTS_B6_8", + "GTPE2_LOGIC_OUTS_B4_10", + "GTPE2_CHANNEL_RXSYNCOUT", + "GTPE2_LOGIC_OUTS_B13_10", + "GTPE2_IMUX34_8", + "GTPE2_LOGIC_OUTS_B0_1", + "GTPE2_IMUX40_6", + "GTPE2_IMUX7_0", + "GTPE2_IMUX34_9", + "GTPE2_IMUX26_10", + "GTPE2_IMUX37_7", + "GTPE2_CHANNEL_RXPRBSSEL1", + "GTPE2_IMUX19_1", + "GTPE2_CHANNEL_RXNOTINTABLE1", + "GTPE2_IMUX29_0", + "GTPE2_LOGIC_OUTS_B18_1", + "GTPE2_CHANNEL_PLLREFCLK1", + "GTPE2_IMUX37_0", + "GTPE2_FAN6_8", + "GTPE2_CHANNEL_TXSYNCMODE", + "GTPE2_CHANNEL_RXPHMONITOR4", + "GTPE2_CHANNEL_DRPDI10", + "GTPE2_IMUX20_8", + "GTPE2_LOGIC_OUTS_B5_3", + "GTPE2_LOGIC_OUTS_B9_10", + "GTPE2_CHANNEL_PMASCANIN0", + "GTPE2_CHANNEL_EYESCANTRIGGER", + "GTPE2_BYP0_3", + "GTPE2_FAN6_2", + "GTPE2_CTRL0_3", + "GTPE2_CHANNEL_RXDATA19", + "GTPE2_CTRL1_1", + "GTPE2_CHANNEL_PCSRSVDIN9", + "GTPE2_IMUX17_6", + "GTPE2_CHANNEL_DRPADDR5", + "GTPE2_CHANNEL_TSTIN2", + "GTPE2_IMUX25_10", + "GTPE2_LOGIC_OUTS_B5_9", + "GTPE2_IMUX16_4", + "GTPE2_LOGIC_OUTS_B10_5", + "GTPE2_LOGIC_OUTS_B18_7", + "GTPE2_IMUX11_9", + "GTPE2_CHANNEL_RXDATA4", + "GTPE2_IMUX13_7", + "GTPE2_IMUX9_0", + "GTPE2_LOGIC_OUTS_B14_3", + "GTPE2_CHANNEL_RXDATA2", + "GTPE2_IMUX2_1", + "GTPE2_CHANNEL_RXCHBONDO3", + "GTPE2_IMUX24_10", + "GTPE2_FAN1_1", + "GTPE2_CHANNEL_TXDLYOVRDEN", + "GTPE2_CHANNEL_TXDATA0", + "GTPE2_BYP3_6", + "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "GTPE2_IMUX42_5", + "GTPE2_CHANNEL_PMASCANMODEB", + "GTPE2_BYP0_4", + "GTPE2_LOGIC_OUTS_B12_9", + "GTPE2_CHANNEL_RXDATA25", + "GTPE2_CHANNEL_RXOSCALRESET", + "GTPE2_IMUX10_9", + "GTPE2_CTRL0_6", + "GTPE2_IMUX41_10", + "GTPE2_CLK1_6", + "GTPE2_IMUX8_10", + "GTPE2_IMUX14_3", + "GTPE2_CHANNEL_RXGEARBOXSLIP", + "GTPE2_CHANNEL_GTRSVD2", + "GTPE2_IMUX36_6", + "GTPE2_CHANNEL_TXCOMFINISH", + "GTPE2_CTRL1_10", + "GTPE2_IMUX2_7", + "GTPE2_CHANNEL_PCSRSVDOUT10", + "GTPE2_IMUX13_5", + "GTPE2_CHANNEL_GTRSVD14", + "GTPE2_LOGIC_OUTS_B16_1", + "GTPE2_BYP4_6", + "GTPE2_CHANNEL_RXOSINTHOLD", + "GTPE2_IMUX34_2", + "GTPE2_LOGIC_OUTS_B20_9", + "GTPE2_IMUX22_10", + "GTPE2_IMUX9_9", + "GTPE2_CHANNEL_RXSLIDE", + "GTPE2_CLK1_0", + "GTPE2_IMUX41_2", + "GTPE2_LOGIC_OUTS_B0_7", + "GTPE2_CHANNEL_RXADAPTSELTEST5", + "GTPE2_FAN4_5", + "GTPE2_FAN3_4", + "GTPE2_CHANNEL_RXCHBONDI1", + "GTPE2_CHANNEL_RXRESETDONE", + "GTPE2_CHANNEL_TXCOMSAS", + "GTPE2_IMUX20_4", + "GTPE2_IMUX25_7", + "GTPE2_FAN3_9", + "GTPE2_CHANNEL_RXCHBONDEN", + "GTPE2_IMUX1_9", + "GTPE2_BYP1_8", + "GTPE2_IMUX29_5", + "GTPE2_LOGIC_OUTS_B1_0", + "GTPE2_CHANNEL_TXMAINCURSOR2", + "GTPE2_CTRL1_6", + "GTPE2_IMUX32_4", + "GTPE2_LOGIC_OUTS_B6_2", + "GTPE2_CHANNEL_RXOSINTID02", + "GTPE2_CHANNEL_GTRSVD10", + "GTPE2_BYP4_5", + "GTPE2_IMUX35_6", + "GTPE2_IMUX36_10", + "GTPE2_IMUX31_9", + "GTPE2_IMUX1_7", + "GTPE2_CHANNEL_TXHEADER1", + "GTPE2_IMUX27_6", + "GTPE2_CHANNEL_DMONITOROUT1", + "GTPE2_IMUX26_1", + "GTPE2_IMUX25_4", + "GTPE2_IMUX15_5", + "GTPE2_CHANNEL_PCSRSVDOUT4", + "GTPE2_IMUX30_6", + "GTPE2_BYP3_0", + "GTPE2_CHANNEL_DRPDO0", + "GTPE2_IMUX36_9", + "GTPE2_CHANNEL_DRPDI8", + "GTPE2_IMUX38_7", + "GTPE2_BYP5_2", + "GTPE2_BYP7_0", + "GTPE2_CHANNEL_DRPADDR6", + "GTPE2_LOGIC_OUTS_B7_7", + "GTPE2_LOGIC_OUTS_B13_3", + "GTPE2_LOGIC_OUTS_B2_6", + "GTPE2_CHANNEL_RXOSINTID00", + "GTPE2_FAN0_2", + "GTPE2_CHANNEL_TXUSRCLK", + "GTPE2_CHANNEL_RXPD0", + "GTPE2_IMUX0_7", + "GTPE2_IMUX33_5", + "GTPE2_LOGIC_OUTS_B20_8", + "GTPE2_LOGIC_OUTS_B6_10", + "GTPE2_LOGIC_OUTS_B12_4", + "GTPE2_IMUX16_8", + "GTPE2_CHANNEL_RXDISPERR1", + "GTPE2_LOGIC_OUTS_B3_4", + "GTPE2_CLK1_5", + "GTPE2_CHANNEL_TXDATA19", + "GTPE2_IMUX22_8", + "GTPE2_IMUX30_7", + "GTPE2_FAN6_5", + "GTPE2_CHANNEL_RXPHMONITOR3", + "GTPE2_CHANNEL_TXMAINCURSOR4", + "GTPE2_CHANNEL_PMARSVDIN1", + "GTPE2_BYP3_8", + "GTPE2_CHANNEL_RXBUFSTATUS1", + "GTPE2_CHANNEL_RXHEADER1", + "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "GTPE2_CLK0_1", + "GTPE2_LOGIC_OUTS_B6_7", + "GTPE2_BYP3_4", + "GTPE2_CHANNEL_TXMARGIN2", + "GTPE2_IMUX40_2", + "GTPE2_LOGIC_OUTS_B6_6", + "GTPE2_IMUX26_4", + "GTPE2_CHANNEL_TXPHINIT", + "GTPE2_LOGIC_OUTS_B15_5", + "GTPE2_FAN3_5", + "GTPE2_IMUX11_8", + "GTPE2_FAN0_8", + "GTPE2_IMUX12_3", + "GTPE2_CHANNEL_TXP_PAD", + "GTPE2_IMUX3_0", + "GTPE2_IMUX5_8", + "GTPE2_LOGIC_OUTS_B3_5", + "GTPE2_IMUX34_10", + "GTPE2_IMUX46_2", + "GTPE2_CHANNEL_PLL0CLK", + "GTPE2_CHANNEL_TXCHARDISPVAL2", + "GTPE2_CHANNEL_TXPISOPD", + "GTPE2_CHANNEL_TX8B10BBYPASS3", + "GTPE2_IMUX46_0", + "GTPE2_BYP2_9", + "GTPE2_CHANNEL_TSTIN16", + "GTPE2_CHANNEL_GTRSVD7", + "GTPE2_FAN6_9", + "GTPE2_IMUX3_5", + "GTPE2_LOGIC_OUTS_B15_7", + "GTPE2_IMUX41_4", + "GTPE2_CHANNEL_RXLPMHFHOLD", + "GTPE2_IMUX23_9", + "GTPE2_CHANNEL_PCSRSVDIN5", + "GTPE2_CHANNEL_SCANIN0", + "GTPE2_LOGIC_OUTS_B13_2", + "GTPE2_IMUX8_5", + "GTPE2_IMUX39_0", + "GTPE2_IMUX42_10", + "GTPE2_IMUX14_2", + "GTPE2_CHANNEL_TXDATA24", + "GTPE2_BYP1_6", + "GTPE2_IMUX28_10", + "GTPE2_FAN5_6", + "GTPE2_BYP2_3", + "GTPE2_CHANNEL_RXDATA14", + "GTPE2_IMUX24_6", + "GTPE2_CHANNEL_RXOSINTNTRLEN", + "GTPE2_LOGIC_OUTS_B1_5", + "GTPE2_LOGIC_OUTS_B8_5", + "GTPE2_LOGIC_OUTS_B3_8", + "GTPE2_IMUX9_7", + "GTPE2_IMUX9_1", + "GTPE2_IMUX44_6", + "GTPE2_CHANNEL_TXDATA12", + "GTPE2_LOGIC_OUTS_B23_5", + "GTPE2_CHANNEL_PLLCLK0", + "GTPE2_CHANNEL_TXSEQUENCE0", + "GTPE2_CHANNEL_RXELECIDLE", + "GTPE2_CHANNEL_SIGVALIDCLK", + "GTPE2_CHANNEL_TXSEQUENCE2", + "GTPE2_FAN4_7", + "GTPE2_IMUX46_4", + "GTPE2_LOGIC_OUTS_B20_1", + "GTPE2_CHANNEL_RXOSINTCFG2", + "GTPE2_LOGIC_OUTS_B19_7", + "GTPE2_IMUX22_7", + "GTPE2_LOGIC_OUTS_B2_9", + "GTPE2_IMUX31_4", + "GTPE2_IMUX8_4", + "GTPE2_IMUX26_2", + "GTPE2_FAN1_10", + "GTPE2_LOGIC_OUTS_B18_0", + "GTPE2_CHANNEL_TXRATEMODE", + "GTPE2_CHANNEL_RXOSINTCFG1", + "GTPE2_CLK1_4", + "GTPE2_IMUX2_3", + "GTPE2_CHANNEL_RXSYSCLKSEL0", + "GTPE2_CHANNEL_TXCHARISK3", + "GTPE2_LOGIC_OUTS_B4_0", + "GTPE2_IMUX7_3", + "GTPE2_IMUX21_1", + "GTPE2_BYP2_8", + "GTPE2_IMUX11_4", + "GTPE2_LOGIC_OUTS_B0_10", + "GTPE2_IMUX27_3", + "GTPE2_FAN0_9", + "GTPE2_CHANNEL_DRPDI12", + "GTPE2_LOGIC_OUTS_B21_5", + "GTPE2_CHANNEL_RXDDIEN", + "GTPE2_FAN7_0", + "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "GTPE2_CHANNEL_PCSRSVDIN8", + "GTPE2_BYP4_7", + "GTPE2_LOGIC_OUTS_B19_6", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", + "GTPE2_CHANNEL_TXSEQUENCE1", + "GTPE2_IMUX29_7", + "GTPE2_LOGIC_OUTS_B10_8", + "GTPE2_LOGIC_OUTS_B20_0", + "GTPE2_IMUX24_8", + "GTPE2_CHANNEL_RXRATEMODE", + "GTPE2_IMUX46_3", + "GTPE2_LOGIC_OUTS_B10_0", + "GTPE2_LOGIC_OUTS_B22_5", + "GTPE2_IMUX37_8", + "GTPE2_FAN7_4", + "GTPE2_IMUX44_0", + "GTPE2_LOGIC_OUTS_B21_8", + "GTPE2_CHANNEL_DRPADDR0", + "GTPE2_CHANNEL_LOOPBACK0", + "GTPE2_CHANNEL_TXPIPPMSEL", + "GTPE2_CHANNEL_PCSRSVDOUT11", + "GTPE2_BYP6_9", + "GTPE2_LOGIC_OUTS_B0_6", + "GTPE2_LOGIC_OUTS_B5_10", + "GTPE2_IMUX38_5", + "GTPE2_LOGIC_OUTS_B1_1", + "GTPE2_IMUX10_10", + "GTPE2_LOGIC_OUTS_B18_9", + "GTPE2_IMUX2_6", + "GTPE2_IMUX45_6", + "GTPE2_CHANNEL_RXBYTEISALIGNED", + "GTPE2_CHANNEL_RXDATA17", + "GTPE2_BYP2_0", + "GTPE2_FAN0_1", + "GTPE2_IMUX28_1", + "GTPE2_CHANNEL_RXUSRCLK2", + "GTPE2_CHANNEL_DRPDO15", + "GTPE2_CHANNEL_RXDATA26", + "GTPE2_IMUX4_7", + "GTPE2_IMUX27_5", + "GTPE2_BYP7_7", + "GTPE2_CHANNEL_TXDATA8", + "GTPE2_IMUX44_2", + "GTPE2_IMUX44_10", + "GTPE2_FAN2_6", + "GTPE2_CHANNEL_TXDATA26", + "GTPE2_CHANNEL_TXPCSRESET", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", + "GTPE2_IMUX35_7", + "GTPE2_IMUX45_7", + "GTPE2_CHANNEL_TXRUNDISP1", + "GTPE2_BYP6_1", + "GTPE2_IMUX16_0", + "GTPE2_IMUX30_9", + "GTPE2_IMUX31_6", + "GTPE2_LOGIC_OUTS_B19_0", + "GTPE2_CHANNEL_RXNOTINTABLE2", + "GTPE2_LOGIC_OUTS_B14_7", + "GTPE2_IMUX8_2", + "GTPE2_LOGIC_OUTS_B21_7", + "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", + "GTPE2_CHANNEL_PCSRSVDOUT12", + "GTPE2_CHANNEL_RXELECIDLEMODE0", + "GTPE2_CHANNEL_RXOUTCLK_2", + "GTPE2_FAN2_7", + "GTPE2_LOGIC_OUTS_B22_6", + "GTPE2_CHANNEL_TXPHOVRDEN", + "GTPE2_CHANNEL_RXUSERRDY", + "GTPE2_CHANNEL_PMASCANIN1", + "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "GTPE2_LOGIC_OUTS_B0_3", + "GTPE2_CHANNEL_RXADAPTSELTEST8", + "GTPE2_LOGIC_OUTS_B20_3", + "GTPE2_IMUX6_1", + "GTPE2_IMUX45_1", + "GTPE2_LOGIC_OUTS_B7_10", + "GTPE2_IMUX16_9", + "GTPE2_LOGIC_OUTS_B9_3", + "GTPE2_LOGIC_OUTS_B10_1", + "GTPE2_CHANNEL_TXPHALIGNEN", + "GTPE2_IMUX1_5", + "GTPE2_FAN0_4", + "GTPE2_LOGIC_OUTS_B17_7", + "GTPE2_CTRL0_1", + "GTPE2_BYP6_3", + "GTPE2_BYP5_1", + "GTPE2_LOGIC_OUTS_B10_6", + "GTPE2_FAN7_7", + "GTPE2_CHANNEL_PLL1REFCLK", + "GTPE2_IMUX18_7", + "GTPE2_BYP2_10", + "GTPE2_CHANNEL_RXCOMSASDET", + "GTPE2_LOGIC_OUTS_B19_4", + "GTPE2_IMUX35_5", + "GTPE2_CHANNEL_PCSRSVDOUT2", + "GTPE2_CHANNEL_TXPOSTCURSOR0", + "GTPE2_CHANNEL_TXPDELECIDLEMODE", + "GTPE2_BYP7_2", + "GTPE2_CHANNEL_DRPDI14", + "GTPE2_CHANNEL_TSTIN0", + "GTPE2_CHANNEL_CLKRSVD1", + "GTPE2_IMUX25_0", + "GTPE2_LOGIC_OUTS_B10_4", + "GTPE2_IMUX33_9", + "GTPE2_CHANNEL_TSTPD1", + "GTPE2_CHANNEL_TSTIN18", + "GTPE2_CHANNEL_TXHEADER0", + "GTPE2_IMUX36_8", + "GTPE2_CHANNEL_GTRSVD9", + "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "GTPE2_FAN3_2", + "GTPE2_CHANNEL_GTRSVD6", + "GTPE2_IMUX27_7", + "GTPE2_CHANNEL_DRPDO13", + "GTPE2_CHANNEL_PMARSVDIN4", + "GTPE2_IMUX36_3", + "GTPE2_IMUX29_10", + "GTPE2_IMUX40_9", + "GTPE2_CHANNEL_EYESCANMODE", + "GTPE2_CHANNEL_RXCDRRESETRSV", + "GTPE2_IMUX44_8", + "GTPE2_CHANNEL_PMASCANOUT4", + "GTPE2_CHANNEL_RXDATA3", + "GTPE2_LOGIC_OUTS_B5_0", + "GTPE2_BYP5_0", + "GTPE2_CHANNEL_TX8B10BBYPASS0", + "GTPE2_LOGIC_OUTS_B15_9", + "GTPE2_IMUX0_0", + "GTPE2_IMUX24_3", + "GTPE2_CHANNEL_PMARSVDIN3", + "GTPE2_LOGIC_OUTS_B4_6", + "GTPE2_CHANNEL_RXDATA0", + "GTPE2_IMUX22_1", + "GTPE2_IMUX38_8", + "GTPE2_FAN3_10", + "GTPE2_CHANNEL_TXCOMINIT", + "GTPE2_IMUX15_10", + "GTPE2_IMUX39_4", + "GTPE2_CHANNEL_RXCLKCORCNT0", + "GTPE2_BYP1_1", + "GTPE2_IMUX31_1", + "GTPE2_IMUX20_0", + "GTPE2_BYP0_8", + "GTPE2_IMUX24_0", + "GTPE2_CHANNEL_TXDIFFCTRL0", + "GTPE2_BYP0_9", + "GTPE2_IMUX21_10", + "GTPE2_CHANNEL_TXSYNCDONE", + "GTPE2_CHANNEL_PMASCANIN2", + "GTPE2_LOGIC_OUTS_B8_4", + "GTPE2_CHANNEL_TSTIN3", + "GTPE2_CHANNEL_TXDATA15", + "GTPE2_IMUX13_8", + "GTPE2_IMUX11_3", + "GTPE2_IMUX27_1", + "GTPE2_LOGIC_OUTS_B1_4", + "GTPE2_CHANNEL_TXSEQUENCE4", + "GTPE2_IMUX44_5", + "GTPE2_CTRL0_2", + "GTPE2_LOGIC_OUTS_B18_8", + "GTPE2_CHANNEL_DMONITOROUT9", + "GTPE2_BYP4_0", + "GTPE2_FAN0_10", + "GTPE2_FAN1_2", + "GTPE2_CHANNEL_RXCOMMADET", + "GTPE2_IMUX22_6", + "GTPE2_BYP4_3", + "GTPE2_IMUX42_7", + "GTPE2_CHANNEL_TXSTARTSEQ", + "GTPE2_LOGIC_OUTS_B11_0", + "GTPE2_IMUX44_7", + "GTPE2_CHANNEL_PCSRSVDIN2", + "GTPE2_IMUX30_0", + "GTPE2_LOGIC_OUTS_B23_10", + "GTPE2_IMUX4_1", + "GTPE2_LOGIC_OUTS_B8_2", + "GTPE2_CHANNEL_RXDISPERR3", + "GTPE2_IMUX46_6", + "GTPE2_CTRL0_5", + "GTPE2_CHANNEL_RXCHARISK3", + "GTPE2_IMUX3_7", + "GTPE2_CHANNEL_DRPDO3", + "GTPE2_IMUX17_0", + "GTPE2_LOGIC_OUTS_B6_4", + "GTPE2_FAN2_10", + "GTPE2_CHANNEL_DRPDI0", + "GTPE2_BYP6_4", + "GTPE2_CLK0_5", + "GTPE2_FAN4_0", + "GTPE2_CHANNEL_SCANIN4", + "GTPE2_IMUX4_2", + "GTPE2_IMUX39_6", + "GTPE2_LOGIC_OUTS_B8_9", + "GTPE2_LOGIC_OUTS_B15_8", + "GTPE2_IMUX23_6", + "GTPE2_IMUX9_6", + "GTPE2_IMUX8_9", + "GTPE2_CTRL1_0", + "GTPE2_CLK1_10", + "GTPE2_CHANNEL_RXCDRLOCK", + "GTPE2_CHANNEL_PCSRSVDOUT6", + "GTPE2_IMUX33_0", + "GTPE2_IMUX30_4", + "GTPE2_IMUX43_8", + "GTPE2_CHANNEL_RXDFEXYDEN", + "GTPE2_IMUX32_3", + "GTPE2_IMUX34_1", + "GTPE2_CLK1_8", + "GTPE2_IMUX5_5", + "GTPE2_IMUX19_3", + "GTPE2_CHANNEL_TXMAINCURSOR1", + "GTPE2_IMUX6_0", + "GTPE2_IMUX41_9", + "GTPE2_LOGIC_OUTS_B17_5", + "GTPE2_IMUX41_3", + "GTPE2_LOGIC_OUTS_B7_6", + "GTPE2_CHANNEL_TXPMARESET", + "GTPE2_FAN1_0", + "GTPE2_LOGIC_OUTS_B17_2", + "GTPE2_CLK0_10", + "GTPE2_LOGIC_OUTS_B1_8", + "GTPE2_CHANNEL_GTRXOUTCLK_1", + "GTPE2_FAN7_8", + "GTPE2_CHANNEL_DRPADDR2", + "GTPE2_CHANNEL_DRPCLK", + "GTPE2_IMUX10_0", + "GTPE2_CHANNEL_RXCDROVRDEN", + "GTPE2_BYP0_2", + "GTPE2_LOGIC_OUTS_B15_4", + "GTPE2_IMUX10_7", + "GTPE2_FAN4_10", + "GTPE2_LOGIC_OUTS_B9_9", + "GTPE2_LOGIC_OUTS_B15_2", + "GTPE2_CHANNEL_TXOUTCLKSEL1", + "GTPE2_CHANNEL_TXCHARDISPMODE0", + "GTPE2_IMUX20_10", + "GTPE2_CHANNEL_RXHEADERVALID", + "GTPE2_IMUX15_8", + "GTPE2_CLK0_7", + "GTPE2_CHANNEL_RXOSINTDONE", + "GTPE2_CHANNEL_TXRATE1", + "GTPE2_CHANNEL_TXDATA9", + "GTPE2_LOGIC_OUTS_B17_4", + "GTPE2_IMUX29_1", + "GTPE2_IMUX42_0", + "GTPE2_IMUX39_3", + "GTPE2_IMUX18_3", + "GTPE2_LOGIC_OUTS_B12_1", + "GTPE2_LOGIC_OUTS_B21_6", + "GTPE2_CHANNEL_RXOUTCLK_3", + "GTPE2_IMUX26_3", + "GTPE2_LOGIC_OUTS_B6_5", + "GTPE2_IMUX8_3", + "GTPE2_BYP1_2", + "GTPE2_FAN4_6", + "GTPE2_CHANNEL_TXDATA17", + "GTPE2_IMUX29_9", + "GTPE2_BYP7_6", + "GTPE2_IMUX27_2", + "GTPE2_CHANNEL_RXDLYSRESETDONE", + "GTPE2_CHANNEL_TXPIPPMPD", + "GTPE2_IMUX39_8", + "GTPE2_CHANNEL_TSTIN11", + "GTPE2_IMUX6_4", + "GTPE2_BYP4_8", + "GTPE2_LOGIC_OUTS_B12_8", + "GTPE2_CHANNEL_TXPRECURSOR2", + "GTPE2_IMUX39_10", + "GTPE2_LOGIC_OUTS_B7_0", + "GTPE2_IMUX21_5", + "GTPE2_IMUX5_0", + "GTPE2_LOGIC_OUTS_B5_5", + "GTPE2_IMUX38_0", + "GTPE2_LOGIC_OUTS_B7_1", + "GTPE2_IMUX18_0", + "GTPE2_CHANNEL_RXPMARESET", + "GTPE2_IMUX29_4", + "GTPE2_CHANNEL_PCSRSVDOUT0", + "GTPE2_FAN4_2", + "GTPE2_IMUX11_2", + "GTPE2_CHANNEL_RXBUFSTATUS2", + "GTPE2_CHANNEL_GTRSVD0", + "GTPE2_CHANNEL_TXUSRCLK2", + "GTPE2_IMUX24_1", + "GTPE2_CHANNEL_SCANOUT5", + "GTPE2_IMUX15_2", + "GTPE2_LOGIC_OUTS_B7_4", + "GTPE2_CHANNEL_TSTIN17", + "GTPE2_CHANNEL_DMONITOROUT13", + "GTPE2_CTRL1_8", + "GTPE2_CHANNEL_RXCHBONDI0", + "GTPE2_LOGIC_OUTS_B20_4", + "GTPE2_CHANNEL_RXOSINTEN", + "GTPE2_CHANNEL_TXRATEDONE", + "GTPE2_CHANNEL_TXPOLARITY", + "GTPE2_IMUX20_2", + "GTPE2_LOGIC_OUTS_B9_0", + "GTPE2_CHANNEL_TXCHARDISPVAL1", + "GTPE2_CHANNEL_TSTIN7", + "GTPE2_LOGIC_OUTS_B20_5", + "GTPE2_LOGIC_OUTS_B23_6", + "GTPE2_IMUX12_2", + "GTPE2_CHANNEL_RXOSINTPD", + "GTPE2_LOGIC_OUTS_B2_2", + "GTPE2_FAN4_1", + "GTPE2_BYP5_4", + "GTPE2_IMUX36_2", + "GTPE2_CHANNEL_TXDATA5", + "GTPE2_CHANNEL_RXDATA24", + "GTPE2_IMUX33_4", + "GTPE2_CHANNEL_RXDATA21", + "GTPE2_BYP3_9", + "GTPE2_CHANNEL_TXPIPPMEN", + "GTPE2_IMUX17_8", + "GTPE2_IMUX23_7", + "GTPE2_FAN6_0", + "GTPE2_LOGIC_OUTS_B12_5", + "GTPE2_CLK1_9", + "GTPE2_CHANNEL_TXDATA4", + "GTPE2_BYP7_3", + "GTPE2_CHANNEL_RESETOVRD", + "GTPE2_IMUX2_5", + "GTPE2_IMUX10_1", + "GTPE2_LOGIC_OUTS_B9_5", + "GTPE2_IMUX36_4", + "GTPE2_IMUX46_10", + "GTPE2_CHANNEL_RXCDRHOLD", + "GTPE2_IMUX47_6", + "GTPE2_CTRL0_9", + "GTPE2_IMUX10_5", + "GTPE2_CHANNEL_DRPDO5", + "GTPE2_CHANNEL_RXADAPTSELTEST6", + "GTPE2_CHANNEL_RXBUFSTATUS0", + "GTPE2_CHANNEL_TXN_PAD", + "GTPE2_CHANNEL_TXSYNCALLIN", + "GTPE2_IMUX27_10", + "GTPE2_IMUX42_8", + "GTPE2_CHANNEL_RXDLYTESTENB", + "GTPE2_CHANNEL_TXOUTCLK_3", + "GTPE2_IMUX46_5", + "GTPE2_LOGIC_OUTS_B17_8", + "GTPE2_LOGIC_OUTS_B8_0", + "GTPE2_IMUX27_8", + "GTPE2_BYP7_9", + "GTPE2_CHANNEL_RXDATA7", + "GTPE2_CHANNEL_SETERRSTATUS", + "GTPE2_CHANNEL_TXSYNCOUT", + "GTPE2_FAN1_5", + "GTPE2_IMUX30_2", + "GTPE2_CHANNEL_DMONITOROUT0", + "GTPE2_CHANNEL_GTRSVD12", + "GTPE2_BYP6_5", + "GTPE2_LOGIC_OUTS_B2_4", + "GTPE2_IMUX7_6", + "GTPE2_BYP0_10", + "GTPE2_LOGIC_OUTS_B21_4", + "GTPE2_CHANNEL_TSTIN1", + "GTPE2_IMUX7_1", + "GTPE2_IMUX42_6", + "GTPE2_CHANNEL_TX8B10BBYPASS1", + "GTPE2_FAN3_1", + "GTPE2_LOGIC_OUTS_B9_7", + "GTPE2_CHANNEL_RXDATA18", + "GTPE2_IMUX41_6", + "GTPE2_CHANNEL_TXDLYTESTENB", + "GTPE2_IMUX27_4", + "GTPE2_IMUX31_8", + "GTPE2_IMUX5_9", + "GTPE2_IMUX12_0", + "GTPE2_IMUX32_7", + "GTPE2_IMUX1_1", + "GTPE2_IMUX25_1", + "GTPE2_CHANNEL_RXCHBONDI3", + "GTPE2_LOGIC_OUTS_B17_10", + "GTPE2_CHANNEL_RXSTATUS2", + "GTPE2_CHANNEL_SCANOUT2", + "GTPE2_LOGIC_OUTS_B9_1", + "GTPE2_LOGIC_OUTS_B11_3", + "GTPE2_IMUX39_1", + "GTPE2_CHANNEL_TXOUTCLK_1", + "GTPE2_IMUX6_2", + "GTPE2_FAN2_3", + "GTPE2_IMUX31_7", + "GTPE2_CHANNEL_RXCHBONDO1", + "GTPE2_CHANNEL_GTRSVD13", + "GTPE2_IMUX18_4", + "GTPE2_IMUX6_5", + "GTPE2_LOGIC_OUTS_B7_3", + "GTPE2_IMUX46_9", + "GTPE2_LOGIC_OUTS_B5_7", + "GTPE2_LOGIC_OUTS_B16_0", + "GTPE2_CHANNEL_DMONITOROUT8", + "GTPE2_CHANNEL_RXADAPTSELTEST11", + "GTPE2_LOGIC_OUTS_B0_8", + "GTPE2_IMUX43_4", + "GTPE2_CHANNEL_DMONITORCLK", + "GTPE2_IMUX35_2", + "GTPE2_LOGIC_OUTS_B22_7", + "GTPE2_IMUX7_4", + "GTPE2_CHANNEL_PLLCLK1", + "GTPE2_CTRL1_4", + "GTPE2_IMUX11_6", + "GTPE2_CHANNEL_CLKRSVD0", + "GTPE2_LOGIC_OUTS_B14_8", + "GTPE2_LOGIC_OUTS_B13_7", + "GTPE2_IMUX45_2", + "GTPE2_CHANNEL_RXCHARISCOMMA1", + "GTPE2_IMUX29_2", + "GTPE2_CHANNEL_PLLREFCLK0", + "GTPE2_IMUX38_6", + "GTPE2_CHANNEL_TXDATA1", + "GTPE2_CHANNEL_RXPHOVRDEN", + "GTPE2_CHANNEL_DMONITOROUT10", + "GTPE2_LOGIC_OUTS_B22_8", + "GTPE2_IMUX21_9", + "GTPE2_FAN4_4", + "GTPE2_CHANNEL_RXOSINTCFG0", + "GTPE2_IMUX1_8", + "GTPE2_IMUX12_8", + "GTPE2_LOGIC_OUTS_B4_3", + "GTPE2_BYP4_9", + "GTPE2_IMUX14_9", + "GTPE2_LOGIC_OUTS_B15_10", + "GTPE2_BYP0_1", + "GTPE2_LOGIC_OUTS_B21_0", + "GTPE2_CHANNEL_RXDATA8", + "GTPE2_IMUX25_6", + "GTPE2_CTRL1_2", + "GTPE2_IMUX40_10", + "GTPE2_CHANNEL_TXOUTCLK_2", + "GTPE2_CHANNEL_TSTPD3", + "GTPE2_IMUX24_7", + "GTPE2_IMUX15_1", + "GTPE2_LOGIC_OUTS_B3_6", + "GTPE2_IMUX35_1", + "GTPE2_CHANNEL_GTRSVD4", + "GTPE2_IMUX4_10", + "GTPE2_CHANNEL_TXDLYEN", + "GTPE2_LOGIC_OUTS_B10_10", + "GTPE2_IMUX9_3", + "GTPE2_CHANNEL_DRPDO2", + "GTPE2_LOGIC_OUTS_B6_3", + "GTPE2_CHANNEL_RXCOMWAKEDET", + "GTPE2_CHANNEL_PMASCANCLK3", + "GTPE2_CHANNEL_RXDATA23", + "GTPE2_CHANNEL_RXADAPTSELTEST0", + "GTPE2_CHANNEL_TXBUFDIFFCTRL0", + "GTPE2_CHANNEL_TXCOMWAKE", + "GTPE2_FAN0_3", + "GTPE2_LOGIC_OUTS_B13_1", + "GTPE2_CHANNEL_SCANIN5", + "GTPE2_LOGIC_OUTS_B4_7", + "GTPE2_CHANNEL_RXSYNCDONE", + "GTPE2_CHANNEL_TXCHARISK0", + "GTPE2_IMUX31_0", + "GTPE2_IMUX34_6", + "GTPE2_BYP3_7", + "GTPE2_IMUX46_7", + "GTPE2_CHANNEL_RXDISPERR0", + "GTPE2_IMUX1_3", + "GTPE2_IMUX0_10", + "GTPE2_IMUX32_8", + "GTPE2_LOGIC_OUTS_B7_8", + "GTPE2_BYP5_8", + "GTPE2_CHANNEL_TXPHALIGN", + "GTPE2_BYP1_4", + "GTPE2_CHANNEL_TSTIN19", + "GTPE2_CHANNEL_PCSRSVDOUT15", + "GTPE2_IMUX18_2", + "GTPE2_IMUX16_5", + "GTPE2_LOGIC_OUTS_B12_10", + "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "GTPE2_BYP6_0", + "GTPE2_LOGIC_OUTS_B17_3", + "GTPE2_IMUX7_2", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", + "GTPE2_IMUX33_8", + "GTPE2_IMUX34_5", + "GTPE2_CHANNEL_RXCHARISK2", + "GTPE2_IMUX25_5", + "GTPE2_IMUX18_5", + "GTPE2_CHANNEL_RXCHBONDSLAVE", + "GTPE2_CHANNEL_TXOUTCLK_0", + "GTPE2_CHANNEL_TXMAINCURSOR3", + "GTPE2_IMUX9_8", + "GTPE2_IMUX21_6", + "GTPE2_LOGIC_OUTS_B21_3", + "GTPE2_IMUX7_9", + "GTPE2_LOGIC_OUTS_B18_6", + "GTPE2_IMUX45_4", + "GTPE2_BYP7_5", + "GTPE2_CHANNEL_TXCHARDISPMODE2", + "GTPE2_CHANNEL_TXBUFDIFFCTRL1", + "GTPE2_IMUX25_2", + "GTPE2_IMUX28_8", + "GTPE2_CHANNEL_RXADAPTSELTEST7", + "GTPE2_CHANNEL_TXDLYHOLD", + "GTPE2_IMUX43_6", + "GTPE2_CHANNEL_TXDATA13", + "GTPE2_LOGIC_OUTS_B15_0", + "GTPE2_CHANNEL_RXMCOMMAALIGNEN", + "GTPE2_LOGIC_OUTS_B18_5", + "GTPE2_CHANNEL_RXOSHOLD", + "GTPE2_LOGIC_OUTS_B11_8", + "GTPE2_IMUX8_8", + "GTPE2_LOGIC_OUTS_B2_10", + "GTPE2_CHANNEL_RXP_PAD", + "GTPE2_IMUX20_3", + "GTPE2_IMUX38_2", + "GTPE2_FAN1_3", + "GTPE2_IMUX4_0", + "GTPE2_CHANNEL_GTTXRESET", + "GTPE2_BYP3_10", + "GTPE2_LOGIC_OUTS_B16_4", + "GTPE2_CHANNEL_PMASCANENB", + "GTPE2_CHANNEL_RXSYNCIN", + "GTPE2_LOGIC_OUTS_B19_8", + "GTPE2_CHANNEL_TXP", + "GTPE2_CHANNEL_RXHEADER2", + "GTPE2_CHANNEL_TXDATA25", + "GTPE2_LOGIC_OUTS_B14_1", + "GTPE2_IMUX13_3", + "GTPE2_IMUX1_4", + "GTPE2_CHANNEL_DRPDO7", + "GTPE2_BYP1_9", + "GTPE2_IMUX47_8", + "GTPE2_LOGIC_OUTS_B1_10", + "GTPE2_BYP4_4", + "GTPE2_CHANNEL_DRPDI5", + "GTPE2_CHANNEL_RXLPMLFHOLD", + "GTPE2_BYP6_2", + "GTPE2_IMUX21_7", + "GTPE2_CHANNEL_TXDLYSRESET", + "GTPE2_IMUX40_3", + "GTPE2_IMUX38_4", + "GTPE2_LOGIC_OUTS_B21_10", + "GTPE2_BYP3_3", + "GTPE2_FAN2_8", + "GTPE2_BYP6_8", + "GTPE2_CHANNEL_TXDATA27", + "GTPE2_FAN4_3", + "GTPE2_CHANNEL_TXPRBSSEL1", + "GTPE2_CHANNEL_PCSRSVDOUT8", + "GTPE2_CHANNEL_TXPD1", + "GTPE2_IMUX24_4", + "GTPE2_CHANNEL_RXRATEDONE", + "GTPE2_CHANNEL_RXPRBSCNTRESET", + "GTPE2_IMUX12_5", + "GTPE2_CHANNEL_RXDATAVALID1", + "GTPE2_CHANNEL_DRPDI13", + "GTPE2_FAN5_2", + "GTPE2_LOGIC_OUTS_B12_7", + "GTPE2_FAN7_3", + "GTPE2_IMUX41_5", + "GTPE2_CHANNEL_TXGEARBOXREADY", + "GTPE2_LOGIC_OUTS_B6_1", + "GTPE2_FAN1_7", + "GTPE2_CHANNEL_TXSYNCIN", + "GTPE2_LOGIC_OUTS_B17_1", + "GTPE2_IMUX9_4", + "GTPE2_CHANNEL_PMASCANIN4", + "GTPE2_CHANNEL_TXRATE2", + "GTPE2_CHANNEL_DRPDO9", + "GTPE2_BYP7_10", + "GTPE2_IMUX8_7", + "GTPE2_CHANNEL_TSTIN9", + "GTPE2_IMUX12_10", + "GTPE2_LOGIC_OUTS_B19_2", + "GTPE2_LOGIC_OUTS_B19_10", + "GTPE2_BYP1_0", + "GTPE2_LOGIC_OUTS_B15_6", + "GTPE2_IMUX26_5", + "GTPE2_IMUX7_7", + "GTPE2_CHANNEL_TXDIFFCTRL1", + "GTPE2_IMUX41_7", + "GTPE2_CHANNEL_PLL1CLK", + "GTPE2_IMUX33_2", + "GTPE2_CHANNEL_TSTPD4", + "GTPE2_CHANNEL_RXDLYSRESET", + "GTPE2_LOGIC_OUTS_B2_8", + "GTPE2_CHANNEL_RXRATE2", + "GTPE2_FAN5_0", + "GTPE2_CHANNEL_RXOUTCLKSEL0", + "GTPE2_CHANNEL_TXPHINITDONE", + "GTPE2_IMUX45_10", + "GTPE2_IMUX1_0", + "GTPE2_CHANNEL_EYESCANDATAERROR", + "GTPE2_CHANNEL_DRPDI7", + "GTPE2_CHANNEL_RXDATA10", + "GTPE2_CHANNEL_SCANMODEB", + "GTPE2_LOGIC_OUTS_B23_3", + "GTPE2_IMUX31_10", + "GTPE2_FAN6_10", + "GTPE2_IMUX35_10", + "GTPE2_CHANNEL_DMONITOROUT12", + "GTPE2_LOGIC_OUTS_B15_1", + "GTPE2_CHANNEL_TXDLYSRESETDONE", + "GTPE2_CHANNEL_RXDLYOVRDEN", + "GTPE2_IMUX47_2", + "GTPE2_IMUX40_0", + "GTPE2_CHANNEL_PCSRSVDIN1", + "GTPE2_IMUX12_4", + "GTPE2_CHANNEL_DMONITOROUT6", + "GTPE2_IMUX6_8", + "GTPE2_CHANNEL_RXOSOVRDEN", + "GTPE2_CHANNEL_TXDIFFPD", + "GTPE2_CHANNEL_RXCHARISCOMMA2", + "GTPE2_LOGIC_OUTS_B2_5", + "GTPE2_CLK0_3", + "GTPE2_LOGIC_OUTS_B14_0", + "GTPE2_IMUX4_5", + "GTPE2_FAN3_7", + "GTPE2_CHANNEL_TSTIN12", + "GTPE2_IMUX21_8", + "GTPE2_CHANNEL_RXELECIDLEMODE1", + "GTPE2_LOGIC_OUTS_B18_3", + "GTPE2_CHANNEL_RXPHMONITOR2", + "GTPE2_IMUX11_10", + "GTPE2_IMUX31_3", + "GTPE2_CLK1_7", + "GTPE2_CLK1_2", + "GTPE2_LOGIC_OUTS_B5_6", + "GTPE2_FAN6_4", + "GTPE2_IMUX11_7", + "GTPE2_BYP7_4", + "GTPE2_IMUX2_8", + "GTPE2_LOGIC_OUTS_B5_4", + "GTPE2_FAN2_0", + "GTPE2_IMUX32_5", + "GTPE2_LOGIC_OUTS_B16_5", + "GTPE2_LOGIC_OUTS_B18_4", + "GTPE2_BYP4_2", + "GTPE2_CHANNEL_TXPHDLYTSTCLK", + "GTPE2_CHANNEL_SCANIN2", + "GTPE2_IMUX37_5", + "GTPE2_BYP7_8", + "GTPE2_IMUX3_10", + "GTPE2_FAN7_9", + "GTPE2_LOGIC_OUTS_B7_2", + "GTPE2_LOGIC_OUTS_B4_9", + "GTPE2_LOGIC_OUTS_B13_5", + "GTPE2_CHANNEL_GTRSVD3", + "GTPE2_IMUX22_0", + "GTPE2_IMUX2_10", + "GTPE2_CHANNEL_GTRXRESET", + "GTPE2_IMUX35_3", + "GTPE2_IMUX14_6", + "GTPE2_IMUX44_1", + "GTPE2_IMUX38_9", + "GTPE2_CHANNEL_RXDATA28", + "GTPE2_CHANNEL_DRPDI1", + "GTPE2_LOGIC_OUTS_B23_0", + "GTPE2_IMUX10_6", + "GTPE2_CHANNEL_TXOUTCLKSEL0", + "GTPE2_IMUX0_8", + "GTPE2_LOGIC_OUTS_B11_10", + "GTPE2_LOGIC_OUTS_B2_3", + "GTPE2_IMUX15_7", + "GTPE2_IMUX36_1", + "GTPE2_CLK0_6", + "GTPE2_CHANNEL_RXNOTINTABLE3", + "GTPE2_CHANNEL_RXCHANISALIGNED", + "GTPE2_IMUX8_1", + "GTPE2_CHANNEL_TSTPD0", + "GTPE2_CHANNEL_TXDATA14", + "GTPE2_CHANNEL_RXN", + "GTPE2_IMUX14_5", + "GTPE2_IMUX44_4", + "GTPE2_IMUX20_7", + "GTPE2_FAN5_3", + "GTPE2_FAN2_9", + "GTPE2_CHANNEL_TSTIN13", + "GTPE2_CHANNEL_LOOPBACK1", + "GTPE2_IMUX43_2", + "GTPE2_BYP5_6", + "GTPE2_CHANNEL_RXDLYBYPASS", + "GTPE2_LOGIC_OUTS_B11_5", + "GTPE2_IMUX4_8", + "GTPE2_LOGIC_OUTS_B22_4", + "GTPE2_LOGIC_OUTS_B14_2", + "GTPE2_CHANNEL_TXHEADER2", + "GTPE2_IMUX6_7", + "GTPE2_CHANNEL_PCSRSVDOUT1", + "GTPE2_IMUX9_10", + "GTPE2_LOGIC_OUTS_B9_2", + "GTPE2_CHANNEL_PMASCANIN3", + "GTPE2_LOGIC_OUTS_B0_2", + "GTPE2_IMUX10_4", + "GTPE2_CHANNEL_PMASCANOUT5", + "GTPE2_LOGIC_OUTS_B4_5", + "GTPE2_IMUX22_5", + "GTPE2_CHANNEL_TXMARGIN1", + "GTPE2_IMUX43_5", + "GTPE2_LOGIC_OUTS_B17_9", + "GTPE2_CHANNEL_RXLPMLFOVRDEN", + "GTPE2_CHANNEL_RXRATE1", + "GTPE2_LOGIC_OUTS_B5_2", + "GTPE2_IMUX1_2", + "GTPE2_CHANNEL_PCSRSVDIN14", + "GTPE2_BYP6_6", + "GTPE2_CHANNEL_SCANENB", + "GTPE2_CHANNEL_PMASCANCLK0", + "GTPE2_IMUX5_6", + "GTPE2_LOGIC_OUTS_B16_10", + "GTPE2_IMUX47_0", + "GTPE2_LOGIC_OUTS_B3_1", + "GTPE2_LOGIC_OUTS_B21_2", + "GTPE2_CHANNEL_RXCHARISK1", + "GTPE2_IMUX36_7", + "GTPE2_CHANNEL_TXDETECTRX", + "GTPE2_IMUX23_3", + "GTPE2_IMUX20_1", + "GTPE2_IMUX30_8", + "GTPE2_CHANNEL_TXDATA29", + "GTPE2_CHANNEL_TXDATA31", + "GTPE2_CHANNEL_RXDATA5", + "GTPE2_FAN6_7", + "GTPE2_LOGIC_OUTS_B1_3", + "GTPE2_CHANNEL_SCANIN3", + "GTPE2_CHANNEL_RXADAPTSELTEST3", + "GTPE2_CHANNEL_TXRUNDISP2", + "GTPE2_CHANNEL_RXSYSCLKSEL1", + "GTPE2_CHANNEL_RXOSINTID03", + "GTPE2_CHANNEL_TXBUFSTATUS0", + "GTPE2_BYP6_7", + "GTPE2_CHANNEL_RXCHBONDMASTER", + "GTPE2_IMUX35_8", + "GTPE2_IMUX17_5", + "GTPE2_LOGIC_OUTS_B5_8", + "GTPE2_IMUX10_2", + "GTPE2_CHANNEL_TXPOSTCURSORINV", + "GTPE2_IMUX47_4", + "GTPE2_IMUX42_2", + "GTPE2_IMUX47_10", + "GTPE2_LOGIC_OUTS_B23_1", + "GTPE2_IMUX15_4", + "GTPE2_FAN4_9", + "GTPE2_CHANNEL_RXPRBSSEL2", + "GTPE2_LOGIC_OUTS_B14_10", + "GTPE2_IMUX35_9", + "GTPE2_CHANNEL_RXBUFRESET", + "GTPE2_CHANNEL_TXDATA22", + "GTPE2_CHANNEL_PMASCANOUT2", + "GTPE2_LOGIC_OUTS_B4_1", + "GTPE2_IMUX28_6", + "GTPE2_IMUX16_7", + "GTPE2_CHANNEL_DMONITOROUT3", + "GTPE2_LOGIC_OUTS_B20_7", + "GTPE2_LOGIC_OUTS_B12_3", + "GTPE2_LOGIC_OUTS_B23_9", + "GTPE2_IMUX28_4", + "GTPE2_CHANNEL_TXRATE0", + "GTPE2_CHANNEL_DRPDO8", + "GTPE2_CHANNEL_TXDEEMPH", + "GTPE2_LOGIC_OUTS_B2_1", + "GTPE2_LOGIC_OUTS_B1_2", + "GTPE2_LOGIC_OUTS_B16_8", + "GTPE2_CHANNEL_PCSRSVDIN6", + "GTPE2_IMUX0_5", + "GTPE2_CHANNEL_SCANCLK", + "GTPE2_CHANNEL_RXADAPTSELTEST10", + "GTPE2_CHANNEL_TSTIN5", + "GTPE2_IMUX38_3", + "GTPE2_FAN0_0", + "GTPE2_IMUX7_5", + "GTPE2_IMUX45_8", + "GTPE2_IMUX17_7", + "GTPE2_CHANNEL_TSTIN6", + "GTPE2_IMUX39_5", + "GTPE2_CHANNEL_RXPHMONITOR0", + "GTPE2_FAN2_4", + "GTPE2_LOGIC_OUTS_B11_7", + "GTPE2_CHANNEL_TXN", + "GTPE2_CHANNEL_CFGRESET", + "GTPE2_CHANNEL_TXPOSTCURSOR3", + "GTPE2_CHANNEL_RXADAPTSELTEST9", + "GTPE2_CHANNEL_TXPRECURSORINV", + "GTPE2_CHANNEL_DRPADDR1", + "GTPE2_CHANNEL_TXDATA18", + "GTPE2_FAN1_8", + "GTPE2_LOGIC_OUTS_B10_7", + "GTPE2_BYP1_7", + "GTPE2_BYP7_1", + "GTPE2_LOGIC_OUTS_B11_2", + "GTPE2_IMUX17_9", + "GTPE2_CHANNEL_RXCHBONDLEVEL2", + "GTPE2_BYP3_2", + "GTPE2_IMUX45_0", + "GTPE2_CHANNEL_TXPMARESETDONE", + "GTPE2_IMUX14_0", + "GTPE2_CHANNEL_PCSRSVDOUT3", + "GTPE2_CHANNEL_TXINHIBIT", + "GTPE2_LOGIC_OUTS_B14_5", + "GTPE2_IMUX19_2", + "GTPE2_CHANNEL_DRPDI3", + "GTPE2_IMUX28_2", + "GTPE2_IMUX18_6", + "GTPE2_CHANNEL_DRPADDR4", + "GTPE2_CHANNEL_TXPRECURSOR4", + "GTPE2_IMUX34_0", + "GTPE2_IMUX40_4", + "GTPE2_CHANNEL_TXPHALIGNDONE", + "GTPE2_LOGIC_OUTS_B3_3", + "GTPE2_LOGIC_OUTS_B23_2", + "GTPE2_FAN5_4", + "GTPE2_LOGIC_OUTS_B22_1", + "GTPE2_IMUX39_7", + "GTPE2_FAN6_6", + "GTPE2_IMUX13_9", + "GTPE2_CHANNEL_TXSYSCLKSEL0", + "GTPE2_CHANNEL_RXPHDLYRESET", + "GTPE2_LOGIC_OUTS_B19_1", + "GTPE2_CHANNEL_TXCHARDISPVAL3", + "GTPE2_IMUX37_9", + "GTPE2_IMUX13_6", + "GTPE2_FAN0_6", + "GTPE2_LOGIC_OUTS_B0_5", + "GTPE2_CHANNEL_TXPD0", + "GTPE2_CHANNEL_PCSRSVDIN15", + "GTPE2_IMUX47_3", + "GTPE2_CHANNEL_DRPEN", + "GTPE2_BYP4_1", + "GTPE2_IMUX3_9", + "GTPE2_BYP0_7", + "GTPE2_IMUX28_9", + "GTPE2_IMUX16_1", + "GTPE2_CHANNEL_RXDATA13", + "GTPE2_CHANNEL_PHYSTATUS", + "GTPE2_IMUX31_2", + "GTPE2_CHANNEL_TXDIFFCTRL3", + "GTPE2_IMUX8_6", + "GTPE2_LOGIC_OUTS_B3_0", + "GTPE2_IMUX28_7", + "GTPE2_IMUX8_0", + "GTPE2_FAN0_7", + "GTPE2_LOGIC_OUTS_B13_8", + "GTPE2_CHANNEL_TXMAINCURSOR6", + "GTPE2_CHANNEL_DRPWE", + "GTPE2_LOGIC_OUTS_B2_7", + "GTPE2_IMUX33_1", + "GTPE2_IMUX3_8", + "GTPE2_IMUX11_0", + "GTPE2_LOGIC_OUTS_B3_7", + "GTPE2_CLK0_8", + "GTPE2_IMUX36_5", + "GTPE2_IMUX11_5", + "GTPE2_CHANNEL_TXDATA23", + "GTPE2_IMUX19_4", + "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", + "GTPE2_IMUX23_10", + "GTPE2_CHANNEL_RXOUTCLK_1", + "GTPE2_IMUX40_5", + "GTPE2_FAN1_9", + "GTPE2_CHANNEL_RXADAPTSELTEST13", + "GTPE2_CHANNEL_RXN_PAD", + "GTPE2_CHANNEL_RXVALID", + "GTPE2_CHANNEL_TXDLYBYPASS", + "GTPE2_IMUX44_9", + "GTPE2_CHANNEL_TXOUTCLKPCS", + "GTPE2_CHANNEL_PMASCANOUT3", + "GTPE2_CHANNEL_DRPADDR7", + "GTPE2_CHANNEL_RXDATA16", + "GTPE2_IMUX39_9", + "GTPE2_LOGIC_OUTS_B10_3", + "GTPE2_IMUX21_0", + "GTPE2_BYP1_5", + "GTPE2_IMUX3_3", + "GTPE2_LOGIC_OUTS_B3_9", + "GTPE2_IMUX32_0", + "GTPE2_CHANNEL_TXPRBSSEL0", + "GTPE2_IMUX26_6", + "GTPE2_CHANNEL_RXPCOMMAALIGNEN", + "GTPE2_IMUX13_10", + "GTPE2_CHANNEL_RXPHALIGNDONE", + "GTPE2_LOGIC_OUTS_B9_6", + "GTPE2_LOGIC_OUTS_B17_0", + "GTPE2_CHANNEL_RXDATA22", + "GTPE2_CHANNEL_RXOUTCLK_0", + "GTPE2_IMUX13_4", + "GTPE2_CHANNEL_GTRSVD1", + "GTPE2_CHANNEL_RXDATA12", + "GTPE2_CHANNEL_SCANOUT3", + "GTPE2_CHANNEL_RXCDRRESET", + "GTPE2_IMUX1_6", + "GTPE2_CHANNEL_TXPRECURSOR3", + "GTPE2_CHANNEL_DRPDI9", + "GTPE2_LOGIC_OUTS_B9_8", + "GTPE2_FAN6_1", + "GTPE2_IMUX19_7", + "GTPE2_CHANNEL_TXCHARDISPMODE3", + "GTPE2_CHANNEL_PMASCANOUT1", + "GTPE2_IMUX37_10", + "GTPE2_CTRL1_3", + "GTPE2_LOGIC_OUTS_B16_2", + "GTPE2_IMUX45_5", + "GTPE2_CHANNEL_PCSRSVDIN12", + "GTPE2_IMUX19_5", + "GTPE2_CHANNEL_RXADAPTSELTEST12", + "GTPE2_IMUX13_0", + "GTPE2_CTRL0_7", + "GTPE2_LOGIC_OUTS_B18_10", + "GTPE2_IMUX0_3", + "GTPE2_IMUX34_3", + "GTPE2_CHANNEL_RXOSINTOVRDEN", + "GTPE2_CHANNEL_TXSEQUENCE5", + "GTPE2_LOGIC_OUTS_B22_3", + "GTPE2_CHANNEL_RXLPMHFOVRDEN", + "GTPE2_CHANNEL_TXDATA6", + "GTPE2_IMUX19_0", + "GTPE2_CHANNEL_RXDATA20", + "GTPE2_CHANNEL_SCANOUT0", + "GTPE2_CHANNEL_TXPOSTCURSOR4", + "GTPE2_CHANNEL_TXPOSTCURSOR1", + "GTPE2_LOGIC_OUTS_B23_4", + "GTPE2_CHANNEL_SCANIN1", + "GTPE2_FAN7_1", + "GTPE2_IMUX2_9", + "GTPE2_CHANNEL_RXPHALIGNEN", + "GTPE2_FAN2_1", + "GTPE2_CHANNEL_TXPHDLYRESET", + "GTPE2_CHANNEL_RXPD1", + "GTPE2_CHANNEL_RXPRBSERR", + "GTPE2_CHANNEL_PMARSVDOUT0", + "GTPE2_IMUX25_8", + "GTPE2_IMUX23_0", + "GTPE2_IMUX15_9", + "GTPE2_FAN5_5", + "GTPE2_CHANNEL_PMASCANRSTEN", + "GTPE2_CHANNEL_RXCHARISK0", + "GTPE2_LOGIC_OUTS_B21_9", + "GTPE2_IMUX7_8", + "GTPE2_IMUX14_8", + "GTPE2_FAN5_7", + "GTPE2_CHANNEL_TSTPD2", + "GTPE2_LOGIC_OUTS_B8_7", + "GTPE2_LOGIC_OUTS_B22_2", + "GTPE2_IMUX32_10", + "GTPE2_CHANNEL_TXPOSTCURSOR2", + "GTPE2_CHANNEL_DRPDO14", + "GTPE2_IMUX21_2", + "GTPE2_CLK1_3", + "GTPE2_CHANNEL_RXCOMMADETEN", + "GTPE2_IMUX16_2", + "GTPE2_CHANNEL_TXPRECURSOR1", + "GTPE2_IMUX32_6", + "GTPE2_IMUX3_6", + "GTPE2_CTRL1_7", + "GTPE2_CHANNEL_RXPHDLYPD", + "GTPE2_BYP2_7", + "GTPE2_CHANNEL_DMONITOROUT5", + "GTPE2_CTRL0_8", + "GTPE2_LOGIC_OUTS_B14_9", + "GTPE2_CHANNEL_TXRUNDISP0", + "GTPE2_IMUX3_4", + "GTPE2_IMUX18_10", + "GTPE2_CHANNEL_PCSRSVDIN10", + "GTPE2_IMUX20_5", + "GTPE2_IMUX29_6", + "GTPE2_IMUX42_9", + "GTPE2_IMUX28_5", + "GTPE2_LOGIC_OUTS_B11_6", + "GTPE2_CHANNEL_RXDATA30", + "GTPE2_LOGIC_OUTS_B1_6", + "GTPE2_IMUX2_2", + "GTPE2_CHANNEL_PMARSVDIN0", + "GTPE2_FAN6_3", + "GTPE2_CHANNEL_PMASCANIN6", + "GTPE2_FAN0_5", + "GTPE2_CHANNEL_TXCHARISK1", + "GTPE2_FAN4_8", + "GTPE2_BYP2_1", + "GTPE2_LOGIC_OUTS_B13_9", + "GTPE2_CHANNEL_RXCHARISCOMMA0", + "GTPE2_IMUX37_1", + "GTPE2_CHANNEL_RXSTATUS0", + "GTPE2_IMUX14_10", + "GTPE2_IMUX33_3", + "GTPE2_IMUX37_2", + "GTPE2_FAN1_6", + "GTPE2_CHANNEL_RXDATAVALID0", + "GTPE2_CHANNEL_PCSRSVDOUT9", + "GTPE2_IMUX19_9", + "GTPE2_IMUX47_1", + "GTPE2_IMUX47_7", + "GTPE2_CHANNEL_TXUSERRDY", + "GTPE2_LOGIC_OUTS_B7_5", + "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "GTPE2_CHANNEL_RXDATA31", + "GTPE2_CHANNEL_RXDISPERR2", + "GTPE2_CHANNEL_PCSRSVDOUT13", + "GTPE2_CHANNEL_DMONITOROUT14", + "GTPE2_CHANNEL_DRPDO11", + "GTPE2_CHANNEL_DRPDO4", + "GTPE2_LOGIC_OUTS_B10_9", + "GTPE2_IMUX17_4", + "GTPE2_LOGIC_OUTS_B14_6", + "GTPE2_CHANNEL_TXELECIDLE", + "GTPE2_FAN3_6", + "GTPE2_CHANNEL_TXDATA20", + "GTPE2_CHANNEL_DMONITOROUT7", + "GTPE2_IMUX17_3", + "GTPE2_LOGIC_OUTS_B8_1", + "GTPE2_LOGIC_OUTS_B5_1", + "GTPE2_CHANNEL_PMASCANOUT0", + "GTPE2_IMUX15_3", + "GTPE2_CHANNEL_TXMAINCURSOR5", + "GTPE2_IMUX43_7", + "GTPE2_BYP0_0", + "GTPE2_CHANNEL_PMARSVDIN2", + "GTPE2_IMUX0_6", + "GTPE2_CHANNEL_GTRESETSEL", + "GTPE2_IMUX20_9", + "GTPE2_CHANNEL_TSTIN10", + "GTPE2_CHANNEL_TXDATA28", + "GTPE2_CHANNEL_DRPDI6", + "GTPE2_CHANNEL_RXCHBONDO0", + "GTPE2_IMUX40_7", + "GTPE2_BYP5_7", + "GTPE2_CHANNEL_DRPADDR8", + "GTPE2_CHANNEL_TXDATA21", + "GTPE2_IMUX42_1", + "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "GTPE2_LOGIC_OUTS_B19_3", + "GTPE2_LOGIC_OUTS_B3_10", + "GTPE2_BYP3_5", + "GTPE2_IMUX43_0", + "GTPE2_CHANNEL_TXRESETDONE", + "GTPE2_CHANNEL_PMARSVDOUT1", + "GTPE2_IMUX13_1", + "GTPE2_CHANNEL_TSTIN4", + "GTPE2_BYP2_4", + "GTPE2_CHANNEL_RXADAPTSELTEST1", + "GTPE2_FAN2_2", + "GTPE2_IMUX13_2", + "GTPE2_CHANNEL_TXRUNDISP3", + "GTPE2_CHANNEL_TSTIN8", + "GTPE2_CHANNEL_RXDATA11", + "GTPE2_IMUX40_1", + "GTPE2_FAN7_6", + "GTPE2_LOGIC_OUTS_B0_4", + "GTPE2_CHANNEL_RXOSINTSTARTED", + "GTPE2_CHANNEL_TSTCLK0", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", + "GTPE2_IMUX1_10", + "GTPE2_IMUX5_10", + "GTPE2_CHANNEL_TXDATA30", + "GTPE2_IMUX43_3", + "GTPE2_LOGIC_OUTS_B0_0", + "GTPE2_IMUX46_8", + "GTPE2_IMUX10_8", + "GTPE2_CHANNEL_TXSWING", + "GTPE2_IMUX37_4", + "GTPE2_CHANNEL_TXDATA10", + "GTPE2_CHANNEL_SCANOUT4", + "GTPE2_IMUX6_3", + "GTPE2_BYP2_5", + "GTPE2_CHANNEL_RXNOTINTABLE0", + "GTPE2_IMUX6_9", + "GTPE2_IMUX40_8", + "GTPE2_IMUX0_1", + "GTPE2_IMUX4_6", + "GTPE2_CHANNEL_RXOSINTSTROBE", + "GTPE2_LOGIC_OUTS_B8_8", + "GTPE2_IMUX12_9", + "GTPE2_CHANNEL_GTTXOUTCLK_1", + "GTPE2_IMUX22_2", + "GTPE2_IMUX32_2", + "GTPE2_CHANNEL_RXCOMINITDET", + "GTPE2_LOGIC_OUTS_B14_4", + "GTPE2_CHANNEL_TXDLYUPDOWN", + "GTPE2_CHANNEL_DRPADDR3", + "GTPE2_CHANNEL_TXDATA7", + "GTPE2_CHANNEL_RXOUTCLKPCS", + "GTPE2_CHANNEL_RXADAPTSELTEST2", + "GTPE2_CHANNEL_RXDATA1", + "GTPE2_CHANNEL_DRPRDY", + "GTPE2_FAN3_8", + "GTPE2_CHANNEL_TXOUTCLKSEL2", + "GTPE2_IMUX12_1", + "GTPE2_CTRL0_4", + "GTPE2_IMUX23_8", + "GTPE2_CHANNEL_RXCDRFREQRESET", + "GTPE2_CHANNEL_PMASCANCLK2", + "GTPE2_IMUX32_1", + "GTPE2_CHANNEL_RXCHBONDLEVEL0", + "GTPE2_CHANNEL_TX8B10BBYPASS2", + "GTPE2_BYP5_9", + "GTPE2_CHANNEL_TXBUFDIFFCTRL2", + "GTPE2_CHANNEL_SCANOUT1", + "GTPE2_CHANNEL_RXOUTCLKSEL1", + "GTPE2_CHANNEL_TXDATA3", + "GTPE2_IMUX16_10", + "GTPE2_CHANNEL_RXCHBONDO2", + "GTPE2_FAN3_0", + "GTPE2_IMUX22_9", + "GTPE2_IMUX15_0", + "GTPE2_CHANNEL_GTRSVD11", + "GTPE2_LOGIC_OUTS_B13_4", + "GTPE2_IMUX43_10", + "GTPE2_CHANNEL_TXBUFSTATUS1", + "GTPE2_CHANNEL_RXBYTEREALIGN", + "GTPE2_CHANNEL_PCSRSVDIN11", + "GTPE2_CHANNEL_PCSRSVDOUT7", + "GTPE2_CHANNEL_GTRSVD15", + "GTPE2_CLK0_0", + "GTPE2_IMUX10_3", + "GTPE2_IMUX31_5", + "GTPE2_IMUX37_3", + "GTPE2_LOGIC_OUTS_B4_4", + "GTPE2_IMUX38_10", + "GTPE2_CHANNEL_PCSRSVDIN0", + "GTPE2_CHANNEL_TXSYSCLKSEL1", + "GTPE2_CHANNEL_PCSRSVDIN7", + "GTPE2_CHANNEL_DRPDI11", + "GTPE2_IMUX4_3", + "GTPE2_LOGIC_OUTS_B19_9", + "GTPE2_CHANNEL_RXPHALIGN", + "GTPE2_IMUX29_8", + "GTPE2_LOGIC_OUTS_B12_0", + "GTPE2_IMUX9_2", + "GTPE2_CHANNEL_PCSRSVDIN13", + "GTPE2_CHANNEL_RXUSRCLK", + "GTPE2_BYP5_5", + "GTPE2_LOGIC_OUTS_B4_2", + "GTPE2_CHANNEL_RXPRBSSEL0", + "GTPE2_CTRL0_0", + "GTPE2_FAN2_5", + "GTPE2_IMUX46_1", + "GTPE2_LOGIC_OUTS_B7_9", + "GTPE2_LOGIC_OUTS_B4_8", + "GTPE2_CHANNEL_RXCHANBONDSEQ", + "GTPE2_IMUX26_9", + "GTPE2_IMUX35_4", + "GTPE2_CHANNEL_TXPIPPMOVRDEN", + "GTPE2_IMUX27_9", + "GTPE2_IMUX30_10", + "GTPE2_LOGIC_OUTS_B17_6", + "GTPE2_CHANNEL_RXDATA27", + "GTPE2_IMUX12_6", + "GTPE2_IMUX41_0", + "GTPE2_IMUX12_7", + "GTPE2_CHANNEL_RXOOBRESET", + "GTPE2_CHANNEL_TX8B10BEN", + "GTPE2_LOGIC_OUTS_B3_2", + "GTPE2_IMUX5_3", + "GTPE2_CHANNEL_RXADAPTSELTEST4", + "GTPE2_CHANNEL_PMASCANOUT6", + "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "GTPE2_BYP4_10", + "GTPE2_CHANNEL_RXDATA29", + "GTPE2_IMUX5_1", + "GTPE2_IMUX14_7", + "GTPE2_CHANNEL_RXCHARISCOMMA3", + "GTPE2_BYP2_2", + "GTPE2_LOGIC_OUTS_B1_7", + "GTPE2_CHANNEL_GTRSVD8", + "GTPE2_CHANNEL_RXPCSRESET", + "GTPE2_CHANNEL_DMONITOROUT4", + "GTPE2_IMUX47_5", + "GTPE2_IMUX29_3", + "GTPE2_IMUX30_5", + "GTPE2_CTRL1_9", + "GTPE2_CTRL0_10", + "GTPE2_LOGIC_OUTS_B13_6", + "GTPE2_LOGIC_OUTS_B16_3", + "GTPE2_BYP6_10", + "GTPE2_CHANNEL_PCSRSVDIN4", + "GTPE2_IMUX20_6", + "GTPE2_IMUX21_4", + "GTPE2_CHANNEL_PCSRSVDIN3", + "GTPE2_IMUX33_6", + "GTPE2_CHANNEL_EYESCANRESET", + "GTPE2_IMUX41_8", + "GTPE2_IMUX3_1", + "GTPE2_IMUX26_7", + "GTPE2_BYP3_1", + "GTPE2_CLK0_9", + "GTPE2_BYP2_6", + "GTPE2_CHANNEL_RXPHMONITOR1", + "GTPE2_IMUX21_3", + "GTPE2_IMUX27_0", + "GTPE2_IMUX11_1", + "GTPE2_CHANNEL_DRPDO10", + "GTPE2_CHANNEL_RXHEADER0", + "GTPE2_CHANNEL_TSTIN15", + "GTPE2_LOGIC_OUTS_B11_1", + "GTPE2_LOGIC_OUTS_B16_7", + "GTPE2_IMUX6_10", + "GTPE2_CHANNEL_DRPDO12", + "GTPE2_IMUX36_0", + "GTPE2_IMUX47_9", + "GTPE2_LOGIC_OUTS_B6_0", + "GTPE2_CHANNEL_PLL0REFCLK", + "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "GTPE2_CHANNEL_RXDATA6", + "GTPE2_IMUX19_8", + "GTPE2_CHANNEL_RXSTATUS1", + "GTPE2_CHANNEL_RXPMARESETDONE", + "GTPE2_CHANNEL_TXDIFFCTRL2", + "GTPE2_LOGIC_OUTS_B16_6", + "GTPE2_CHANNEL_DRPDO1", + "GTPE2_CHANNEL_RXDLYEN", + "GTPE2_CLK0_2", + "GTPE2_IMUX17_10", + "GTPE2_CHANNEL_TXCHARDISPMODE1", + "GTPE2_CHANNEL_RXDATA15", + "GTPE2_CHANNEL_DRPDI15", + "GTPE2_IMUX15_6", + "GTPE2_IMUX14_4", + "GTPE2_FAN1_4", + "GTPE2_LOGIC_OUTS_B22_0", + "GTPE2_LOGIC_OUTS_B10_2", + "GTPE2_CHANNEL_RXCHANREALIGN", + "GTPE2_CHANNEL_LOOPBACK2", + "GTPE2_IMUX34_4", + "GTPE2_FAN5_10", + "GTPE2_IMUX2_0", + "GTPE2_LOGIC_OUTS_B8_10", + "GTPE2_IMUX7_10", + "GTPE2_CHANNEL_DRPDI4", + "GTPE2_CHANNEL_RXDEBUGPULSE", + "GTPE2_LOGIC_OUTS_B12_6", + "GTPE2_CHANNEL_PMASCANIN5", + "GTPE2_FAN7_5", + "GTPE2_CHANNEL_PMASCANCLK1", + "GTPE2_IMUX43_9", + "GTPE2_LOGIC_OUTS_B12_2", + "GTPE2_LOGIC_OUTS_B20_2", + "GTPE2_IMUX4_4", + "GTPE2_IMUX45_3", + "GTPE2_IMUX30_1", + "GTPE2_LOGIC_OUTS_B8_3", + "GTPE2_FAN5_1", + "GTPE2_CHANNEL_TXMAINCURSOR0", + "GTPE2_IMUX35_0", + "GTPE2_IMUX28_3", + "GTPE2_CHANNEL_RXCHBONDLEVEL1", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", + "GTPE2_CHANNEL_TXPRECURSOR0", + "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "GTPE2_CHANNEL_TXPRBSSEL2", + "GTPE2_LOGIC_OUTS_B15_3", + "GTPE2_IMUX4_9", + "GTPE2_IMUX39_2", + "GTPE2_CHANNEL_TXPHDLYPD", + "GTPE2_CHANNEL_TXCHARISK2", + "GTPE2_CHANNEL_PCSRSVDOUT14", + "GTPE2_IMUX17_1", + "GTPE2_LOGIC_OUTS_B23_7", + "GTPE2_LOGIC_OUTS_B11_4", + "GTPE2_IMUX18_9", + "GTPE2_CHANNEL_RX8B10BEN", + "GTPE2_CHANNEL_TXDATA16", + "GTPE2_IMUX32_9", + "GTPE2_IMUX5_4", + "GTPE2_CHANNEL_TXMARGIN0", + "GTPE2_CHANNEL_TXCHARDISPVAL0", + "GTPE2_IMUX16_6", + "GTPE2_IMUX41_1", + "GTPE2_FAN5_9", + "GTPE2_LOGIC_OUTS_B0_9", + "GTPE2_IMUX23_1", + "GTPE2_CHANNEL_DRPDI2", + "GTPE2_IMUX24_5" + ], + "tile_type": "GTP_CHANNEL_1", + "sites": [ + { + "site_pins": { + "TSTIN11": "GTPE2_CHANNEL_TSTIN11", + "TXCOMSAS": "GTPE2_CHANNEL_TXCOMSAS", + "RXPHDLYPD": "GTPE2_CHANNEL_RXPHDLYPD", + "TXSEQUENCE2": "GTPE2_CHANNEL_TXSEQUENCE2", + "TXCHARISK3": "GTPE2_CHANNEL_TXCHARISK3", + "TSTIN4": "GTPE2_CHANNEL_TSTIN4", + "PMASCANOUT1": "GTPE2_CHANNEL_PMASCANOUT1", + "TXDATA26": "GTPE2_CHANNEL_TXDATA26", + "GTRSVD12": "GTPE2_CHANNEL_GTRSVD12", + "TXDATA29": "GTPE2_CHANNEL_TXDATA29", + "PCSRSVDOUT13": "GTPE2_CHANNEL_PCSRSVDOUT13", + "DRPDI4": "GTPE2_CHANNEL_DRPDI4", + "RXNOTINTABLE3": "GTPE2_CHANNEL_RXNOTINTABLE3", + "RXADAPTSELTEST7": "GTPE2_CHANNEL_RXADAPTSELTEST7", + "PMARSVDIN3": "GTPE2_CHANNEL_PMARSVDIN3", + "TXCHARDISPMODE0": "GTPE2_CHANNEL_TXCHARDISPMODE0", + "PMASCANCLK2": "GTPE2_CHANNEL_PMASCANCLK2", + "DRPDI13": "GTPE2_CHANNEL_DRPDI13", + "RXADAPTSELTEST3": "GTPE2_CHANNEL_RXADAPTSELTEST3", + "RXCHARISK2": "GTPE2_CHANNEL_RXCHARISK2", + "RXCOMINITDET": "GTPE2_CHANNEL_RXCOMINITDET", + "TXMAINCURSOR1": "GTPE2_CHANNEL_TXMAINCURSOR1", + "RXUSRCLK": "GTPE2_CHANNEL_RXUSRCLK", + "PMASCANIN0": "GTPE2_CHANNEL_PMASCANIN0", + "RXCLKCORCNT0": "GTPE2_CHANNEL_RXCLKCORCNT0", + "RXDATA16": "GTPE2_CHANNEL_RXDATA16", + "CFGRESET": "GTPE2_CHANNEL_CFGRESET", + "TSTIN1": "GTPE2_CHANNEL_TSTIN1", + "TXPIPPMOVRDEN": "GTPE2_CHANNEL_TXPIPPMOVRDEN", + "TXPHINIT": "GTPE2_CHANNEL_TXPHINIT", + "EYESCANMODE": "GTPE2_CHANNEL_EYESCANMODE", + "TSTCLK1": "GTPE2_CHANNEL_TSTCLK1", + "RXBUFSTATUS1": "GTPE2_CHANNEL_RXBUFSTATUS1", + "TXPRBSSEL1": "GTPE2_CHANNEL_TXPRBSSEL1", + "LOOPBACK1": "GTPE2_CHANNEL_LOOPBACK1", + "TXMARGIN2": "GTPE2_CHANNEL_TXMARGIN2", + "TSTIN12": "GTPE2_CHANNEL_TSTIN12", + "TSTPD3": "GTPE2_CHANNEL_TSTPD3", + "GTRSVD15": "GTPE2_CHANNEL_GTRSVD15", + "TXDLYEN": "GTPE2_CHANNEL_TXDLYEN", + "TXBUFDIFFCTRL0": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", + "TXRUNDISP3": "GTPE2_CHANNEL_TXRUNDISP3", + "GTRSVD2": "GTPE2_CHANNEL_GTRSVD2", + "PCSRSVDIN9": "GTPE2_CHANNEL_PCSRSVDIN9", + "RXVALID": "GTPE2_CHANNEL_RXVALID", + "TXOUTCLKSEL1": "GTPE2_CHANNEL_TXOUTCLKSEL1", + "RXPCOMMAALIGNEN": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", + "RXDATA15": "GTPE2_CHANNEL_RXDATA15", + "TXELECIDLE": "GTPE2_CHANNEL_TXELECIDLE", + "TXDIFFCTRL3": "GTPE2_CHANNEL_TXDIFFCTRL3", + "PCSRSVDIN6": "GTPE2_CHANNEL_PCSRSVDIN6", + "RXCOMMADETEN": "GTPE2_CHANNEL_RXCOMMADETEN", + "TXSYSCLKSEL1": "GTPE2_CHANNEL_TXSYSCLKSEL1", + "DRPDO5": "GTPE2_CHANNEL_DRPDO5", + "TXDATA6": "GTPE2_CHANNEL_TXDATA6", + "GTRSVD0": "GTPE2_CHANNEL_GTRSVD0", + "GTRSVD8": "GTPE2_CHANNEL_GTRSVD8", + "TXUSRCLK2": "GTPE2_CHANNEL_TXUSRCLK2", + "TXRATE0": "GTPE2_CHANNEL_TXRATE0", + "TSTCLK0": "GTPE2_CHANNEL_TSTCLK0", + "PMASCANRSTEN": "GTPE2_CHANNEL_PMASCANRSTEN", + "TXDATA21": "GTPE2_CHANNEL_TXDATA21", + "RXCDROVRDEN": "GTPE2_CHANNEL_RXCDROVRDEN", + "TXDATA3": "GTPE2_CHANNEL_TXDATA3", + "RXNOTINTABLE0": "GTPE2_CHANNEL_RXNOTINTABLE0", + "TXPOSTCURSOR3": "GTPE2_CHANNEL_TXPOSTCURSOR3", + "RXSYNCOUT": "GTPE2_CHANNEL_RXSYNCOUT", + "RXCHBONDI3": "GTPE2_CHANNEL_RXCHBONDI3", + "RXCHANBONDSEQ": "GTPE2_CHANNEL_RXCHANBONDSEQ", + "TSTIN7": "GTPE2_CHANNEL_TSTIN7", + "RXPOLARITY": "GTPE2_CHANNEL_RXPOLARITY", + "TXMAINCURSOR3": "GTPE2_CHANNEL_TXMAINCURSOR3", + "DRPDI9": "GTPE2_CHANNEL_DRPDI9", + "RXHEADERVALID": "GTPE2_CHANNEL_RXHEADERVALID", + "PMARSVDOUT1": "GTPE2_CHANNEL_PMARSVDOUT1", + "DMONITOROUT13": "GTPE2_CHANNEL_DMONITOROUT13", + "RXSLIDE": "GTPE2_CHANNEL_RXSLIDE", + "LOOPBACK2": "GTPE2_CHANNEL_LOOPBACK2", + "PCSRSVDIN8": "GTPE2_CHANNEL_PCSRSVDIN8", + "RXCOMWAKEDET": "GTPE2_CHANNEL_RXCOMWAKEDET", + "RX8B10BEN": "GTPE2_CHANNEL_RX8B10BEN", + "RXOSINTCFG0": "GTPE2_CHANNEL_RXOSINTCFG0", + "TXMARGIN0": "GTPE2_CHANNEL_TXMARGIN0", + "PCSRSVDOUT2": "GTPE2_CHANNEL_PCSRSVDOUT2", + "TXPIPPMSTEPSIZE4": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", + "TXPIPPMPD": "GTPE2_CHANNEL_TXPIPPMPD", + "TXPD0": "GTPE2_CHANNEL_TXPD0", + "RXADAPTSELTEST0": "GTPE2_CHANNEL_RXADAPTSELTEST0", + "TXSYSCLKSEL0": "GTPE2_CHANNEL_TXSYSCLKSEL0", + "RXCHBONDO0": "GTPE2_CHANNEL_RXCHBONDO0", + "TXHEADER2": "GTPE2_CHANNEL_TXHEADER2", + "PCSRSVDOUT14": "GTPE2_CHANNEL_PCSRSVDOUT14", + "TXRATE2": "GTPE2_CHANNEL_TXRATE2", + "SCANOUT1": "GTPE2_CHANNEL_SCANOUT1", + "PCSRSVDIN12": "GTPE2_CHANNEL_PCSRSVDIN12", + "GTRSVD6": "GTPE2_CHANNEL_GTRSVD6", + "TXPD1": "GTPE2_CHANNEL_TXPD1", + "TXDLYHOLD": "GTPE2_CHANNEL_TXDLYHOLD", + "CLKRSVD1": "GTPE2_CHANNEL_CLKRSVD1", + "TXPHALIGNEN": "GTPE2_CHANNEL_TXPHALIGNEN", + "TXPHDLYPD": "GTPE2_CHANNEL_TXPHDLYPD", + "TXCHARDISPMODE3": "GTPE2_CHANNEL_TXCHARDISPMODE3", + "SCANOUT5": "GTPE2_CHANNEL_SCANOUT5", + "RXOUTCLKSEL1": "GTPE2_CHANNEL_RXOUTCLKSEL1", + "DRPDI10": "GTPE2_CHANNEL_DRPDI10", + "PCSRSVDOUT11": "GTPE2_CHANNEL_PCSRSVDOUT11", + "RXGEARBOXSLIP": "GTPE2_CHANNEL_RXGEARBOXSLIP", + "TXPHALIGNDONE": "GTPE2_CHANNEL_TXPHALIGNDONE", + "RXSYNCALLIN": "GTPE2_CHANNEL_RXSYNCALLIN", + "TXDATA2": "GTPE2_CHANNEL_TXDATA2", + "DMONITOROUT2": "GTPE2_CHANNEL_DMONITOROUT2", + "GTRXRESET": "GTPE2_CHANNEL_GTRXRESET", + "RXOSCALRESET": "GTPE2_CHANNEL_RXOSCALRESET", + "RXCHARISCOMMA0": "GTPE2_CHANNEL_RXCHARISCOMMA0", + "PCSRSVDIN11": "GTPE2_CHANNEL_PCSRSVDIN11", + "RXPRBSSEL1": "GTPE2_CHANNEL_RXPRBSSEL1", + "TXPHOVRDEN": "GTPE2_CHANNEL_TXPHOVRDEN", + "RXPHMONITOR2": "GTPE2_CHANNEL_RXPHMONITOR2", + "GTPRXP": "GTPE2_CHANNEL_RXP", + "TXDLYBYPASS": "GTPE2_CHANNEL_TXDLYBYPASS", + "TSTIN16": "GTPE2_CHANNEL_TSTIN16", + "TXPOSTCURSORINV": "GTPE2_CHANNEL_TXPOSTCURSORINV", + "RXCOMSASDET": "GTPE2_CHANNEL_RXCOMSASDET", + "DMONITOROUT9": "GTPE2_CHANNEL_DMONITOROUT9", + "RXDATA18": "GTPE2_CHANNEL_RXDATA18", + "GTRSVD9": "GTPE2_CHANNEL_GTRSVD9", + "SCANOUT0": "GTPE2_CHANNEL_SCANOUT0", + "RXADAPTSELTEST6": "GTPE2_CHANNEL_RXADAPTSELTEST6", + "RXDATA19": "GTPE2_CHANNEL_RXDATA19", + "RXCHBONDSLAVE": "GTPE2_CHANNEL_RXCHBONDSLAVE", + "DMONITOROUT7": "GTPE2_CHANNEL_DMONITOROUT7", + "RXCDRHOLD": "GTPE2_CHANNEL_RXCDRHOLD", + "TXMAINCURSOR0": "GTPE2_CHANNEL_TXMAINCURSOR0", + "RXOSINTCFG2": "GTPE2_CHANNEL_RXOSINTCFG2", + "PMARSVDIN4": "GTPE2_CHANNEL_PMARSVDIN4", + "TXMAINCURSOR5": "GTPE2_CHANNEL_TXMAINCURSOR5", + "TSTIN9": "GTPE2_CHANNEL_TSTIN9", + "TX8B10BBYPASS1": "GTPE2_CHANNEL_TX8B10BBYPASS1", + "RXPRBSSEL2": "GTPE2_CHANNEL_RXPRBSSEL2", + "RXADAPTSELTEST4": "GTPE2_CHANNEL_RXADAPTSELTEST4", + "TXCHARISK0": "GTPE2_CHANNEL_TXCHARISK0", + "PMARSVDIN0": "GTPE2_CHANNEL_PMARSVDIN0", + "TXPDELECIDLEMODE": "GTPE2_CHANNEL_TXPDELECIDLEMODE", + "RXADAPTSELTEST8": "GTPE2_CHANNEL_RXADAPTSELTEST8", + "TXCHARDISPMODE1": "GTPE2_CHANNEL_TXCHARDISPMODE1", + "TXPMARESETDONE": "GTPE2_CHANNEL_TXPMARESETDONE", + "RXBYTEISALIGNED": "GTPE2_CHANNEL_RXBYTEISALIGNED", + "DMONFIFORESET": "GTPE2_CHANNEL_DMONFIFORESET", + "RXPHSLIPMONITOR4": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "TXDIFFPD": "GTPE2_CHANNEL_TXDIFFPD", + "RXOSINTSTROBE": "GTPE2_CHANNEL_RXOSINTSTROBE", + "PLL0CLK": "GTPE2_CHANNEL_PLL0CLK", + "SETERRSTATUS": "GTPE2_CHANNEL_SETERRSTATUS", + "TXPIPPMSTEPSIZE3": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", + "RXSTATUS2": "GTPE2_CHANNEL_RXSTATUS2", + "TX8B10BEN": "GTPE2_CHANNEL_TX8B10BEN", + "DMONITOROUT5": "GTPE2_CHANNEL_DMONITOROUT5", + "RXLPMHFOVRDEN": "GTPE2_CHANNEL_RXLPMHFOVRDEN", + "PCSRSVDOUT9": "GTPE2_CHANNEL_PCSRSVDOUT9", + "RXOUTCLKFABRIC": "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "PCSRSVDOUT0": "GTPE2_CHANNEL_PCSRSVDOUT0", + "RXPHMONITOR4": "GTPE2_CHANNEL_RXPHMONITOR4", + "RXDATA3": "GTPE2_CHANNEL_RXDATA3", + "RXSYNCDONE": "GTPE2_CHANNEL_RXSYNCDONE", + "RXADAPTSELTEST9": "GTPE2_CHANNEL_RXADAPTSELTEST9", + "DRPADDR4": "GTPE2_CHANNEL_DRPADDR4", + "PCSRSVDOUT7": "GTPE2_CHANNEL_PCSRSVDOUT7", + "TXPIPPMSTEPSIZE1": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", + "RXPHMONITOR1": "GTPE2_CHANNEL_RXPHMONITOR1", + "TXPIPPMEN": "GTPE2_CHANNEL_TXPIPPMEN", + "TXCHARDISPVAL3": "GTPE2_CHANNEL_TXCHARDISPVAL3", + "RXUSRCLK2": "GTPE2_CHANNEL_RXUSRCLK2", + "RXDATAVALID1": "GTPE2_CHANNEL_RXDATAVALID1", + "RXLPMOSINTNTRLEN": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", + "GTRSVD5": "GTPE2_CHANNEL_GTRSVD5", + "DRPDO9": "GTPE2_CHANNEL_DRPDO9", + "EYESCANTRIGGER": "GTPE2_CHANNEL_EYESCANTRIGGER", + "SCANMODEB": "GTPE2_CHANNEL_SCANMODEB", + "DRPDO15": "GTPE2_CHANNEL_DRPDO15", + "TXPRBSSEL0": "GTPE2_CHANNEL_TXPRBSSEL0", + "DMONITOROUT3": "GTPE2_CHANNEL_DMONITOROUT3", + "TSTIN14": "GTPE2_CHANNEL_TSTIN14", + "TXUSERRDY": "GTPE2_CHANNEL_TXUSERRDY", + "DRPDO6": "GTPE2_CHANNEL_DRPDO6", + "RXDLYOVRDEN": "GTPE2_CHANNEL_RXDLYOVRDEN", + "DMONITOROUT6": "GTPE2_CHANNEL_DMONITOROUT6", + "RXLPMHFHOLD": "GTPE2_CHANNEL_RXLPMHFHOLD", + "RXCHARISK3": "GTPE2_CHANNEL_RXCHARISK3", + "PMASCANOUT3": "GTPE2_CHANNEL_PMASCANOUT3", + "TXDATA22": "GTPE2_CHANNEL_TXDATA22", + "RXDISPERR3": "GTPE2_CHANNEL_RXDISPERR3", + "TXOUTCLK": "GTPE2_CHANNEL_GTTXOUTCLK_1", + "RXCLKCORCNT1": "GTPE2_CHANNEL_RXCLKCORCNT1", + "RXOSINTID01": "GTPE2_CHANNEL_RXOSINTID01", + "GTRSVD10": "GTPE2_CHANNEL_GTRSVD10", + "TXCHARDISPVAL1": "GTPE2_CHANNEL_TXCHARDISPVAL1", + "RXCDRLOCK": "GTPE2_CHANNEL_RXCDRLOCK", + "RXPHALIGN": "GTPE2_CHANNEL_RXPHALIGN", + "RXNOTINTABLE1": "GTPE2_CHANNEL_RXNOTINTABLE1", + "PMASCANIN3": "GTPE2_CHANNEL_PMASCANIN3", + "RXCDRRESETRSV": "GTPE2_CHANNEL_RXCDRRESETRSV", + "RXBUFRESET": "GTPE2_CHANNEL_RXBUFRESET", + "RXPHMONITOR3": "GTPE2_CHANNEL_RXPHMONITOR3", + "TXPIPPMSEL": "GTPE2_CHANNEL_TXPIPPMSEL", + "RXDATA20": "GTPE2_CHANNEL_RXDATA20", + "DRPDO14": "GTPE2_CHANNEL_DRPDO14", + "TXSYNCDONE": "GTPE2_CHANNEL_TXSYNCDONE", + "PCSRSVDOUT4": "GTPE2_CHANNEL_PCSRSVDOUT4", + "RXELECIDLEMODE0": "GTPE2_CHANNEL_RXELECIDLEMODE0", + "PMASCANIN5": "GTPE2_CHANNEL_PMASCANIN5", + "TXCOMFINISH": "GTPE2_CHANNEL_TXCOMFINISH", + "TXDATA9": "GTPE2_CHANNEL_TXDATA9", + "DRPADDR1": "GTPE2_CHANNEL_DRPADDR1", + "TXDATA11": "GTPE2_CHANNEL_TXDATA11", + "TXRUNDISP0": "GTPE2_CHANNEL_TXRUNDISP0", + "TXBUFSTATUS0": "GTPE2_CHANNEL_TXBUFSTATUS0", + "RXPHSLIPMONITOR1": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "GTTXRESET": "GTPE2_CHANNEL_GTTXRESET", + "RXELECIDLEMODE1": "GTPE2_CHANNEL_RXELECIDLEMODE1", + "RXDATA13": "GTPE2_CHANNEL_RXDATA13", + "TXDATA27": "GTPE2_CHANNEL_TXDATA27", + "RXSYSCLKSEL0": "GTPE2_CHANNEL_RXSYSCLKSEL0", + "PMASCANCLK0": "GTPE2_CHANNEL_PMASCANCLK0", + "TXPRECURSOR2": "GTPE2_CHANNEL_TXPRECURSOR2", + "TXCOMWAKE": "GTPE2_CHANNEL_TXCOMWAKE", + "RXDATA0": "GTPE2_CHANNEL_RXDATA0", + "GTPTXN": "GTPE2_CHANNEL_TXN", + "TXDLYOVRDEN": "GTPE2_CHANNEL_TXDLYOVRDEN", + "RXOSHOLD": "GTPE2_CHANNEL_RXOSHOLD", + "RXLPMRESET": "GTPE2_CHANNEL_RXLPMRESET", + "PCSRSVDIN4": "GTPE2_CHANNEL_PCSRSVDIN4", + "TXSYNCIN": "GTPE2_CHANNEL_TXSYNCIN", + "RXCHBONDO3": "GTPE2_CHANNEL_RXCHBONDO3", + "PCSRSVDIN7": "GTPE2_CHANNEL_PCSRSVDIN7", + "TSTIN3": "GTPE2_CHANNEL_TSTIN3", + "TXGEARBOXREADY": "GTPE2_CHANNEL_TXGEARBOXREADY", + "GTRSVD1": "GTPE2_CHANNEL_GTRSVD1", + "RXDATA22": "GTPE2_CHANNEL_RXDATA22", + "SCANIN4": "GTPE2_CHANNEL_SCANIN4", + "DRPDI12": "GTPE2_CHANNEL_DRPDI12", + "TXDATA31": "GTPE2_CHANNEL_TXDATA31", + "RXSTARTOFSEQ1": "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "PMASCANIN6": "GTPE2_CHANNEL_PMASCANIN6", + "TXRESETDONE": "GTPE2_CHANNEL_TXRESETDONE", + "TXHEADER1": "GTPE2_CHANNEL_TXHEADER1", + "RXDATA2": "GTPE2_CHANNEL_RXDATA2", + "TXRUNDISP2": "GTPE2_CHANNEL_TXRUNDISP2", + "DRPADDR3": "GTPE2_CHANNEL_DRPADDR3", + "TXDATA13": "GTPE2_CHANNEL_TXDATA13", + "TXPMARESET": "GTPE2_CHANNEL_TXPMARESET", + "RXRATE2": "GTPE2_CHANNEL_RXRATE2", + "RXOOBRESET": "GTPE2_CHANNEL_RXOOBRESET", + "DRPADDR2": "GTPE2_CHANNEL_DRPADDR2", + "DRPDO0": "GTPE2_CHANNEL_DRPDO0", + "RXDATA21": "GTPE2_CHANNEL_RXDATA21", + "GTRSVD14": "GTPE2_CHANNEL_GTRSVD14", + "TXDATA23": "GTPE2_CHANNEL_TXDATA23", + "SIGVALIDCLK": "GTPE2_CHANNEL_SIGVALIDCLK", + "PCSRSVDOUT10": "GTPE2_CHANNEL_PCSRSVDOUT10", + "RXRATE1": "GTPE2_CHANNEL_RXRATE1", + "DRPCLK": "GTPE2_CHANNEL_DRPCLK", + "RXCHBONDO1": "GTPE2_CHANNEL_RXCHBONDO1", + "TXPRECURSOR0": "GTPE2_CHANNEL_TXPRECURSOR0", + "RXDATA25": "GTPE2_CHANNEL_RXDATA25", + "DMONITORCLK": "GTPE2_CHANNEL_DMONITORCLK", + "RXCHARISCOMMA3": "GTPE2_CHANNEL_RXCHARISCOMMA3", + "RXADAPTSELTEST12": "GTPE2_CHANNEL_RXADAPTSELTEST12", + "DRPRDY": "GTPE2_CHANNEL_DRPRDY", + "RXOUTCLKSEL2": "GTPE2_CHANNEL_RXOUTCLKSEL2", + "RXOSINTPD": "GTPE2_CHANNEL_RXOSINTPD", + "DMONITOROUT11": "GTPE2_CHANNEL_DMONITOROUT11", + "RXCHANREALIGN": "GTPE2_CHANNEL_RXCHANREALIGN", + "TXOUTCLKPCS": "GTPE2_CHANNEL_TXOUTCLKPCS", + "RXOSINTCFG3": "GTPE2_CHANNEL_RXOSINTCFG3", + "DRPDO4": "GTPE2_CHANNEL_DRPDO4", + "RXBUFSTATUS0": "GTPE2_CHANNEL_RXBUFSTATUS0", + "RXCHBONDI1": "GTPE2_CHANNEL_RXCHBONDI1", + "DRPDI5": "GTPE2_CHANNEL_DRPDI5", + "TXCHARISK2": "GTPE2_CHANNEL_TXCHARISK2", + "DMONITOROUT1": "GTPE2_CHANNEL_DMONITOROUT1", + "TXOUTCLKSEL2": "GTPE2_CHANNEL_TXOUTCLKSEL2", + "TXPOSTCURSOR4": "GTPE2_CHANNEL_TXPOSTCURSOR4", + "DRPADDR0": "GTPE2_CHANNEL_DRPADDR0", + "RXDLYSRESET": "GTPE2_CHANNEL_RXDLYSRESET", + "RXSTATUS1": "GTPE2_CHANNEL_RXSTATUS1", + "RXDFEXYDEN": "GTPE2_CHANNEL_RXDFEXYDEN", + "TXPHDLYTSTCLK": "GTPE2_CHANNEL_TXPHDLYTSTCLK", + "RXPRBSERR": "GTPE2_CHANNEL_RXPRBSERR", + "RXCOMMADET": "GTPE2_CHANNEL_RXCOMMADET", + "TXSYNCMODE": "GTPE2_CHANNEL_TXSYNCMODE", + "RXADAPTSELTEST10": "GTPE2_CHANNEL_RXADAPTSELTEST10", + "RXOSINTSTROBESTARTED": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "TXPCSRESET": "GTPE2_CHANNEL_TXPCSRESET", + "PCSRSVDIN13": "GTPE2_CHANNEL_PCSRSVDIN13", + "TXUSRCLK": "GTPE2_CHANNEL_TXUSRCLK", + "RXRATEDONE": "GTPE2_CHANNEL_RXRATEDONE", + "PLL1CLK": "GTPE2_CHANNEL_PLL1CLK", + "TXSYNCOUT": "GTPE2_CHANNEL_TXSYNCOUT", + "TSTPD0": "GTPE2_CHANNEL_TSTPD0", + "RXOUTCLKPCS": "GTPE2_CHANNEL_RXOUTCLKPCS", + "PMASCANIN4": "GTPE2_CHANNEL_PMASCANIN4", + "TXDATA14": "GTPE2_CHANNEL_TXDATA14", + "PCSRSVDOUT5": "GTPE2_CHANNEL_PCSRSVDOUT5", + "SCANIN2": "GTPE2_CHANNEL_SCANIN2", + "DRPDI15": "GTPE2_CHANNEL_DRPDI15", + "TSTIN8": "GTPE2_CHANNEL_TSTIN8", + "SCANOUT2": "GTPE2_CHANNEL_SCANOUT2", + "RXCHBONDI0": "GTPE2_CHANNEL_RXCHBONDI0", + "RXDISPERR2": "GTPE2_CHANNEL_RXDISPERR2", + "TXPRECURSOR3": "GTPE2_CHANNEL_TXPRECURSOR3", + "LOOPBACK0": "GTPE2_CHANNEL_LOOPBACK0", + "RXPD1": "GTPE2_CHANNEL_RXPD1", + "RXDLYSRESETDONE": "GTPE2_CHANNEL_RXDLYSRESETDONE", + "TXDETECTRX": "GTPE2_CHANNEL_TXDETECTRX", + "TXMAINCURSOR6": "GTPE2_CHANNEL_TXMAINCURSOR6", + "RXOSINTDONE": "GTPE2_CHANNEL_RXOSINTDONE", + "RXPHSLIPMONITOR2": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "RXHEADER2": "GTPE2_CHANNEL_RXHEADER2", + "RXDLYEN": "GTPE2_CHANNEL_RXDLYEN", + "RXOSINTTESTOVRDEN": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", + "RXDATA31": "GTPE2_CHANNEL_RXDATA31", + "GTRESETSEL": "GTPE2_CHANNEL_GTRESETSEL", + "TXPOLARITY": "GTPE2_CHANNEL_TXPOLARITY", + "RXDATA12": "GTPE2_CHANNEL_RXDATA12", + "DRPDI14": "GTPE2_CHANNEL_DRPDI14", + "RXDDIEN": "GTPE2_CHANNEL_RXDDIEN", + "RXOSINTSTROBEDONE": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "DRPEN": "GTPE2_CHANNEL_DRPEN", + "RXCDRFREQRESET": "GTPE2_CHANNEL_RXCDRFREQRESET", + "TXCHARDISPVAL2": "GTPE2_CHANNEL_TXCHARDISPVAL2", + "TXOUTCLKFABRIC": "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "RXSYNCMODE": "GTPE2_CHANNEL_RXSYNCMODE", + "DRPDI1": "GTPE2_CHANNEL_DRPDI1", + "PCSRSVDIN2": "GTPE2_CHANNEL_PCSRSVDIN2", + "RXOSINTID02": "GTPE2_CHANNEL_RXOSINTID02", + "TXMARGIN1": "GTPE2_CHANNEL_TXMARGIN1", + "TXDIFFCTRL0": "GTPE2_CHANNEL_TXDIFFCTRL0", + "RXBYTEREALIGN": "GTPE2_CHANNEL_RXBYTEREALIGN", + "RXDATA29": "GTPE2_CHANNEL_RXDATA29", + "TXMAINCURSOR2": "GTPE2_CHANNEL_TXMAINCURSOR2", + "RXPHSLIPMONITOR0": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "TSTIN18": "GTPE2_CHANNEL_TSTIN18", + "TXDATA18": "GTPE2_CHANNEL_TXDATA18", + "TXPOSTCURSOR1": "GTPE2_CHANNEL_TXPOSTCURSOR1", + "TSTPD1": "GTPE2_CHANNEL_TSTPD1", + "TXDATA5": "GTPE2_CHANNEL_TXDATA5", + "RXLPMLFOVRDEN": "GTPE2_CHANNEL_RXLPMLFOVRDEN", + "PCSRSVDIN3": "GTPE2_CHANNEL_PCSRSVDIN3", + "RXDLYTESTENB": "GTPE2_CHANNEL_RXDLYTESTENB", + "SCANENB": "GTPE2_CHANNEL_SCANENB", + "RXPCSRESET": "GTPE2_CHANNEL_RXPCSRESET", + "RXDATA14": "GTPE2_CHANNEL_RXDATA14", + "RXCHBONDLEVEL0": "GTPE2_CHANNEL_RXCHBONDLEVEL0", + "TSTIN2": "GTPE2_CHANNEL_TSTIN2", + "PHYSTATUS": "GTPE2_CHANNEL_PHYSTATUS", + "RXDATAVALID0": "GTPE2_CHANNEL_RXDATAVALID0", + "SCANOUT4": "GTPE2_CHANNEL_SCANOUT4", + "PMASCANMODEB": "GTPE2_CHANNEL_PMASCANMODEB", + "TXPISOPD": "GTPE2_CHANNEL_TXPISOPD", + "RXMCOMMAALIGNEN": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", + "TXDLYUPDOWN": "GTPE2_CHANNEL_TXDLYUPDOWN", + "EYESCANDATAERROR": "GTPE2_CHANNEL_EYESCANDATAERROR", + "TXDATA17": "GTPE2_CHANNEL_TXDATA17", + "DRPDO3": "GTPE2_CHANNEL_DRPDO3", + "PCSRSVDOUT8": "GTPE2_CHANNEL_PCSRSVDOUT8", + "TXCHARDISPVAL0": "GTPE2_CHANNEL_TXCHARDISPVAL0", + "RXDEBUGPULSE": "GTPE2_CHANNEL_RXDEBUGPULSE", + "PCSRSVDIN5": "GTPE2_CHANNEL_PCSRSVDIN5", + "PLL1REFCLK": "GTPE2_CHANNEL_PLL1REFCLK", + "DRPDI0": "GTPE2_CHANNEL_DRPDI0", + "TXDATA19": "GTPE2_CHANNEL_TXDATA19", + "RXELECIDLE": "GTPE2_CHANNEL_RXELECIDLE", + "TX8B10BBYPASS2": "GTPE2_CHANNEL_TX8B10BBYPASS2", + "PCSRSVDOUT6": "GTPE2_CHANNEL_PCSRSVDOUT6", + "TXPRECURSOR1": "GTPE2_CHANNEL_TXPRECURSOR1", + "RXADAPTSELTEST1": "GTPE2_CHANNEL_RXADAPTSELTEST1", + "RXLPMLFHOLD": "GTPE2_CHANNEL_RXLPMLFHOLD", + "TXDATA16": "GTPE2_CHANNEL_TXDATA16", + "GTRSVD7": "GTPE2_CHANNEL_GTRSVD7", + "TXDATA8": "GTPE2_CHANNEL_TXDATA8", + "SCANIN3": "GTPE2_CHANNEL_SCANIN3", + "TXPRBSFORCEERR": "GTPE2_CHANNEL_TXPRBSFORCEERR", + "TXRUNDISP1": "GTPE2_CHANNEL_TXRUNDISP1", + "TSTIN10": "GTPE2_CHANNEL_TSTIN10", + "DRPADDR8": "GTPE2_CHANNEL_DRPADDR8", + "RXSTATUS0": "GTPE2_CHANNEL_RXSTATUS0", + "TXSEQUENCE1": "GTPE2_CHANNEL_TXSEQUENCE1", + "GTRSVD3": "GTPE2_CHANNEL_GTRSVD3", + "RXDATA17": "GTPE2_CHANNEL_RXDATA17", + "RXPHOVRDEN": "GTPE2_CHANNEL_RXPHOVRDEN", + "TXSWING": "GTPE2_CHANNEL_TXSWING", + "PMASCANIN2": "GTPE2_CHANNEL_PMASCANIN2", + "PMASCANIN1": "GTPE2_CHANNEL_PMASCANIN1", + "RXRESETDONE": "GTPE2_CHANNEL_RXRESETDONE", + "TXDATA0": "GTPE2_CHANNEL_TXDATA0", + "RXCHBONDEN": "GTPE2_CHANNEL_RXCHBONDEN", + "RXDATA9": "GTPE2_CHANNEL_RXDATA9", + "RXCHARISK1": "GTPE2_CHANNEL_RXCHARISK1", + "DRPADDR6": "GTPE2_CHANNEL_DRPADDR6", + "TXRATEDONE": "GTPE2_CHANNEL_TXRATEDONE", + "RXOUTCLKSEL0": "GTPE2_CHANNEL_RXOUTCLKSEL0", + "TXDATA1": "GTPE2_CHANNEL_TXDATA1", + "TSTPD2": "GTPE2_CHANNEL_TSTPD2", + "RXRATEMODE": "GTPE2_CHANNEL_RXRATEMODE", + "RXOSINTEN": "GTPE2_CHANNEL_RXOSINTEN", + "PMASCANOUT0": "GTPE2_CHANNEL_PMASCANOUT0", + "DRPDO12": "GTPE2_CHANNEL_DRPDO12", + "TXPIPPMSTEPSIZE2": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", + "RXPHALIGNEN": "GTPE2_CHANNEL_RXPHALIGNEN", + "GTRSVD4": "GTPE2_CHANNEL_GTRSVD4", + "TSTIN17": "GTPE2_CHANNEL_TSTIN17", + "TXHEADER0": "GTPE2_CHANNEL_TXHEADER0", + "RXOSINTID00": "GTPE2_CHANNEL_RXOSINTID00", + "RXCHARISCOMMA2": "GTPE2_CHANNEL_RXCHARISCOMMA2", + "RXADAPTSELTEST5": "GTPE2_CHANNEL_RXADAPTSELTEST5", + "DRPDI7": "GTPE2_CHANNEL_DRPDI7", + "DRPDI6": "GTPE2_CHANNEL_DRPDI6", + "DMONITOROUT12": "GTPE2_CHANNEL_DMONITOROUT12", + "TXDATA10": "GTPE2_CHANNEL_TXDATA10", + "PMASCANENB": "GTPE2_CHANNEL_PMASCANENB", + "TXCHARDISPMODE2": "GTPE2_CHANNEL_TXCHARDISPMODE2", + "PMARSVDIN2": "GTPE2_CHANNEL_PMARSVDIN2", + "RXCHANISALIGNED": "GTPE2_CHANNEL_RXCHANISALIGNED", + "GTPTXP": "GTPE2_CHANNEL_TXP", + "RXBUFSTATUS2": "GTPE2_CHANNEL_RXBUFSTATUS2", + "RXPHDLYRESET": "GTPE2_CHANNEL_RXPHDLYRESET", + "PMASCANCLK1": "GTPE2_CHANNEL_PMASCANCLK1", + "TSTPD4": "GTPE2_CHANNEL_TSTPD4", + "TXPRECURSOR4": "GTPE2_CHANNEL_TXPRECURSOR4", + "DMONITOROUT10": "GTPE2_CHANNEL_DMONITOROUT10", + "DRPADDR7": "GTPE2_CHANNEL_DRPADDR7", + "DMONITOROUT0": "GTPE2_CHANNEL_DMONITOROUT0", + "TXDATA24": "GTPE2_CHANNEL_TXDATA24", + "TXDIFFCTRL1": "GTPE2_CHANNEL_TXDIFFCTRL1", + "TXDATA28": "GTPE2_CHANNEL_TXDATA28", + "TXSEQUENCE4": "GTPE2_CHANNEL_TXSEQUENCE4", + "DMONITOROUT4": "GTPE2_CHANNEL_DMONITOROUT4", + "TXBUFDIFFCTRL1": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", + "DRPDO7": "GTPE2_CHANNEL_DRPDO7", + "EYESCANRESET": "GTPE2_CHANNEL_EYESCANRESET", + "RXPD0": "GTPE2_CHANNEL_RXPD0", + "DRPADDR5": "GTPE2_CHANNEL_DRPADDR5", + "RXOUTCLK": "GTPE2_CHANNEL_GTRXOUTCLK_1", + "TXSYNCALLIN": "GTPE2_CHANNEL_TXSYNCALLIN", + "RXHEADER0": "GTPE2_CHANNEL_RXHEADER0", + "TSTIN0": "GTPE2_CHANNEL_TSTIN0", + "RXHEADER1": "GTPE2_CHANNEL_RXHEADER1", + "DRPDO2": "GTPE2_CHANNEL_DRPDO2", + "TXDLYSRESET": "GTPE2_CHANNEL_TXDLYSRESET", + "TX8B10BBYPASS0": "GTPE2_CHANNEL_TX8B10BBYPASS0", + "TSTIN5": "GTPE2_CHANNEL_TSTIN5", + "DRPDO8": "GTPE2_CHANNEL_DRPDO8", + "RXCHARISK0": "GTPE2_CHANNEL_RXCHARISK0", + "RXDATA10": "GTPE2_CHANNEL_RXDATA10", + "RXOSINTOVRDEN": "GTPE2_CHANNEL_RXOSINTOVRDEN", + "PMARSVDOUT0": "GTPE2_CHANNEL_PMARSVDOUT0", + "RXDATA27": "GTPE2_CHANNEL_RXDATA27", + "GTPRXN": "GTPE2_CHANNEL_RXN", + "DRPDO1": "GTPE2_CHANNEL_DRPDO1", + "PCSRSVDIN10": "GTPE2_CHANNEL_PCSRSVDIN10", + "DRPDO11": "GTPE2_CHANNEL_DRPDO11", + "DRPDI3": "GTPE2_CHANNEL_DRPDI3", + "GTRSVD13": "GTPE2_CHANNEL_GTRSVD13", + "TSTIN13": "GTPE2_CHANNEL_TSTIN13", + "TXDATA25": "GTPE2_CHANNEL_TXDATA25", + "TXINHIBIT": "GTPE2_CHANNEL_TXINHIBIT", + "PCSRSVDOUT1": "GTPE2_CHANNEL_PCSRSVDOUT1", + "PCSRSVDOUT15": "GTPE2_CHANNEL_PCSRSVDOUT15", + "RXCDRRESET": "GTPE2_CHANNEL_RXCDRRESET", + "TXBUFDIFFCTRL2": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", + "PCSRSVDOUT12": "GTPE2_CHANNEL_PCSRSVDOUT12", + "CLKRSVD0": "GTPE2_CHANNEL_CLKRSVD0", + "RXCHBONDMASTER": "GTPE2_CHANNEL_RXCHBONDMASTER", + "TXDIFFCTRL2": "GTPE2_CHANNEL_TXDIFFCTRL2", + "RXPHSLIPMONITOR3": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "TXSTARTSEQ": "GTPE2_CHANNEL_TXSTARTSEQ", + "TXCHARISK1": "GTPE2_CHANNEL_TXCHARISK1", + "RXCHBONDLEVEL1": "GTPE2_CHANNEL_RXCHBONDLEVEL1", + "DRPDO13": "GTPE2_CHANNEL_DRPDO13", + "SCANIN0": "GTPE2_CHANNEL_SCANIN0", + "TXDATA12": "GTPE2_CHANNEL_TXDATA12", + "RXDATA5": "GTPE2_CHANNEL_RXDATA5", + "TXPOSTCURSOR0": "GTPE2_CHANNEL_TXPOSTCURSOR0", + "RXPHMONITOR0": "GTPE2_CHANNEL_RXPHMONITOR0", + "TXSEQUENCE6": "GTPE2_CHANNEL_TXSEQUENCE6", + "RXCHARISCOMMA1": "GTPE2_CHANNEL_RXCHARISCOMMA1", + "RXDATA30": "GTPE2_CHANNEL_RXDATA30", + "RXCHBONDO2": "GTPE2_CHANNEL_RXCHBONDO2", + "RXDATA23": "GTPE2_CHANNEL_RXDATA23", + "TXRATE1": "GTPE2_CHANNEL_TXRATE1", + "RXADAPTSELTEST11": "GTPE2_CHANNEL_RXADAPTSELTEST11", + "PLL0REFCLK": "GTPE2_CHANNEL_PLL0REFCLK", + "RESETOVRD": "GTPE2_CHANNEL_RESETOVRD", + "TXBUFSTATUS1": "GTPE2_CHANNEL_TXBUFSTATUS1", + "RXSTARTOFSEQ0": "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "PMASCANOUT2": "GTPE2_CHANNEL_PMASCANOUT2", + "RXDATA11": "GTPE2_CHANNEL_RXDATA11", + "TXMAINCURSOR4": "GTPE2_CHANNEL_TXMAINCURSOR4", + "PMASCANOUT5": "GTPE2_CHANNEL_PMASCANOUT5", + "RXOSINTHOLD": "GTPE2_CHANNEL_RXOSINTHOLD", + "TXPHALIGN": "GTPE2_CHANNEL_TXPHALIGN", + "DRPDI2": "GTPE2_CHANNEL_DRPDI2", + "RXCHBONDI2": "GTPE2_CHANNEL_RXCHBONDI2", + "TXPHDLYRESET": "GTPE2_CHANNEL_TXPHDLYRESET", + "RXPMARESET": "GTPE2_CHANNEL_RXPMARESET", + "RXSYNCIN": "GTPE2_CHANNEL_RXSYNCIN", + "RXDATA8": "GTPE2_CHANNEL_RXDATA8", + "TXDEEMPH": "GTPE2_CHANNEL_TXDEEMPH", + "RXPHALIGNDONE": "GTPE2_CHANNEL_RXPHALIGNDONE", + "RXOSOVRDEN": "GTPE2_CHANNEL_RXOSOVRDEN", + "TSTIN19": "GTPE2_CHANNEL_TSTIN19", + "TXDATA15": "GTPE2_CHANNEL_TXDATA15", + "RXPMARESETDONE": "GTPE2_CHANNEL_RXPMARESETDONE", + "RXDISPERR0": "GTPE2_CHANNEL_RXDISPERR0", + "RXSYSCLKSEL1": "GTPE2_CHANNEL_RXSYSCLKSEL1", + "GTRSVD11": "GTPE2_CHANNEL_GTRSVD11", + "DRPDO10": "GTPE2_CHANNEL_DRPDO10", + "PCSRSVDOUT3": "GTPE2_CHANNEL_PCSRSVDOUT3", + "SCANOUT3": "GTPE2_CHANNEL_SCANOUT3", + "RXDATA7": "GTPE2_CHANNEL_RXDATA7", + "TXDLYTESTENB": "GTPE2_CHANNEL_TXDLYTESTENB", + "RXOSINTID03": "GTPE2_CHANNEL_RXOSINTID03", + "TXPRECURSORINV": "GTPE2_CHANNEL_TXPRECURSORINV", + "TXPIPPMSTEPSIZE0": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", + "TSTIN15": "GTPE2_CHANNEL_TSTIN15", + "PMASCANCLK3": "GTPE2_CHANNEL_PMASCANCLK3", + "PMARSVDIN1": "GTPE2_CHANNEL_PMARSVDIN1", + "RXCHBONDLEVEL2": "GTPE2_CHANNEL_RXCHBONDLEVEL2", + "PCSRSVDIN1": "GTPE2_CHANNEL_PCSRSVDIN1", + "RXNOTINTABLE2": "GTPE2_CHANNEL_RXNOTINTABLE2", + "TXDATA30": "GTPE2_CHANNEL_TXDATA30", + "TSTPDOVRDB": "GTPE2_CHANNEL_TSTPDOVRDB", + "RXOSINTSTARTED": "GTPE2_CHANNEL_RXOSINTSTARTED", + "TSTIN6": "GTPE2_CHANNEL_TSTIN6", + "PMASCANOUT6": "GTPE2_CHANNEL_PMASCANOUT6", + "TXSEQUENCE0": "GTPE2_CHANNEL_TXSEQUENCE0", + "SCANIN5": "GTPE2_CHANNEL_SCANIN5", + "RXDATA1": "GTPE2_CHANNEL_RXDATA1", + "RXADAPTSELTEST13": "GTPE2_CHANNEL_RXADAPTSELTEST13", + "RXDATA24": "GTPE2_CHANNEL_RXDATA24", + "TXDLYSRESETDONE": "GTPE2_CHANNEL_TXDLYSRESETDONE", + "TXDATA20": "GTPE2_CHANNEL_TXDATA20", + "SCANCLK": "GTPE2_CHANNEL_SCANCLK", + "RXPRBSSEL0": "GTPE2_CHANNEL_RXPRBSSEL0", + "TXCOMINIT": "GTPE2_CHANNEL_TXCOMINIT", + "RXUSERRDY": "GTPE2_CHANNEL_RXUSERRDY", + "TXSEQUENCE3": "GTPE2_CHANNEL_TXSEQUENCE3", + "TXOUTCLKSEL0": "GTPE2_CHANNEL_TXOUTCLKSEL0", + "PMASCANOUT4": "GTPE2_CHANNEL_PMASCANOUT4", + "TXDATA4": "GTPE2_CHANNEL_TXDATA4", + "TX8B10BBYPASS3": "GTPE2_CHANNEL_TX8B10BBYPASS3", + "SCANIN1": "GTPE2_CHANNEL_SCANIN1", + "DRPWE": "GTPE2_CHANNEL_DRPWE", + "TXDATA7": "GTPE2_CHANNEL_TXDATA7", + "TXPRBSSEL2": "GTPE2_CHANNEL_TXPRBSSEL2", + "RXDISPERR1": "GTPE2_CHANNEL_RXDISPERR1", + "PCSRSVDIN0": "GTPE2_CHANNEL_PCSRSVDIN0", + "TXRATEMODE": "GTPE2_CHANNEL_TXRATEMODE", + "RXRATE0": "GTPE2_CHANNEL_RXRATE0", + "RXOSINTNTRLEN": "GTPE2_CHANNEL_RXOSINTNTRLEN", + "TXSEQUENCE5": "GTPE2_CHANNEL_TXSEQUENCE5", + "RXDATA4": "GTPE2_CHANNEL_RXDATA4", + "TXPHINITDONE": "GTPE2_CHANNEL_TXPHINITDONE", + "DMONITOROUT8": "GTPE2_CHANNEL_DMONITOROUT8", + "RXDLYBYPASS": "GTPE2_CHANNEL_RXDLYBYPASS", + "RXPRBSCNTRESET": "GTPE2_CHANNEL_RXPRBSCNTRESET", + "RXOSINTCFG1": "GTPE2_CHANNEL_RXOSINTCFG1", + "DRPDI8": "GTPE2_CHANNEL_DRPDI8", + "PCSRSVDIN15": "GTPE2_CHANNEL_PCSRSVDIN15", + "RXDATA6": "GTPE2_CHANNEL_RXDATA6", + "RXDATA28": "GTPE2_CHANNEL_RXDATA28", + "TXPOSTCURSOR2": "GTPE2_CHANNEL_TXPOSTCURSOR2", + "DRPDI11": "GTPE2_CHANNEL_DRPDI11", + "RXADAPTSELTEST2": "GTPE2_CHANNEL_RXADAPTSELTEST2", + "PCSRSVDIN14": "GTPE2_CHANNEL_PCSRSVDIN14", + "RXDATA26": "GTPE2_CHANNEL_RXDATA26", + "DMONITOROUT14": "GTPE2_CHANNEL_DMONITOROUT14" + }, + "type": "GTPE2_CHANNEL", + "prefix": "GTPE2_CHANNEL", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "O": "GTPE2_CHANNEL_RXN_PAD" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y11", + "x_coord": 1, + "y_coord": 11 + }, + { + "site_pins": { + "O": "GTPE2_CHANNEL_RXP_PAD" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y12", + "x_coord": 1, + "y_coord": 12 + }, + { + "site_pins": { + "I": "GTPE2_CHANNEL_TXN_PAD" + }, + "type": "OPAD", + "prefix": "OPAD", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "I": "GTPE2_CHANNEL_TXP_PAD" + }, + "type": "OPAD", + "prefix": "OPAD", + "name": "X0Y2", + "x_coord": 0, + "y_coord": 2 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_GTP_CHANNEL_2.json b/artix7/tile_type_GTP_CHANNEL_2.json index c0ade03..1cc9afb 100644 --- a/artix7/tile_type_GTP_CHANNEL_2.json +++ b/artix7/tile_type_GTP_CHANNEL_2.json @@ -1,5922 +1,5922 @@ { - "wires": [ - "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "GTPE2_IMUX18_2", - "GTPE2_LOGIC_OUTS_B1_3", - "GTPE2_IMUX26_4", - "GTPE2_CHANNEL_TXDATA13", - "GTPE2_CHANNEL_GTRXOUTCLK_2", - "GTPE2_CHANNEL_PMARSVDOUT0", - "GTPE2_FAN1_0", - "GTPE2_LOGIC_OUTS_B14_6", - "GTPE2_LOGIC_OUTS_B13_2", - "GTPE2_FAN3_5", - "GTPE2_IMUX16_6", - "GTPE2_CHANNEL_SETERRSTATUS", - "GTPE2_IMUX43_9", - "GTPE2_BYP5_3", - "GTPE2_LOGIC_OUTS_B19_5", - "GTPE2_IMUX34_0", - "GTPE2_LOGIC_OUTS_B10_3", - "GTPE2_LOGIC_OUTS_B5_1", - "GTPE2_IMUX18_1", - "GTPE2_IMUX6_4", - "GTPE2_IMUX21_5", - "GTPE2_CHANNEL_RXPHDLYPD", - "GTPE2_IMUX40_9", - "GTPE2_CHANNEL_TXMAINCURSOR3", - "GTPE2_CHANNEL_TSTCLK0", - "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "GTPE2_LOGIC_OUTS_B9_7", - "GTPE2_LOGIC_OUTS_B13_8", - "GTPE2_CHANNEL_RXDATAVALID0", - "GTPE2_CHANNEL_PCSRSVDOUT0", - "GTPE2_CHANNEL_RXSYNCMODE", - "GTPE2_LOGIC_OUTS_B10_0", - "GTPE2_CHANNEL_SCANOUT3", - "GTPE2_CHANNEL_RXOSOVRDEN", - "GTPE2_IMUX47_9", - "GTPE2_CHANNEL_RXCHBONDI1", - "GTPE2_CHANNEL_RXCHBONDI2", - "GTPE2_FAN2_1", - "GTPE2_CTRL1_2", - "GTPE2_CHANNEL_PCSRSVDOUT8", - "GTPE2_LOGIC_OUTS_B18_2", - "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "GTPE2_IMUX32_4", - "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "GTPE2_FAN1_8", - "GTPE2_CHANNEL_RXOUTCLK_3", - "GTPE2_CHANNEL_TXDATA11", - "GTPE2_LOGIC_OUTS_B15_5", - "GTPE2_IMUX15_8", - "GTPE2_CHANNEL_TXDATA21", - "GTPE2_CLK0_4", - "GTPE2_CHANNEL_RXPCSRESET", - "GTPE2_IMUX14_4", - "GTPE2_LOGIC_OUTS_B23_2", - "GTPE2_LOGIC_OUTS_B5_6", - "GTPE2_CHANNEL_PCSRSVDIN14", - "GTPE2_FAN2_5", - "GTPE2_CHANNEL_PCSRSVDOUT10", - "GTPE2_IMUX14_6", - "GTPE2_IMUX15_1", - "GTPE2_IMUX30_7", - "GTPE2_CHANNEL_PMASCANOUT4", - "GTPE2_CHANNEL_TXDATA2", - "GTPE2_IMUX41_6", - "GTPE2_IMUX47_4", - "GTPE2_FAN6_0", - "GTPE2_CHANNEL_TXPRECURSOR4", - "GTPE2_FAN3_3", - "GTPE2_CHANNEL_TX8B10BBYPASS0", - "GTPE2_CHANNEL_PMASCANOUT5", - "GTPE2_LOGIC_OUTS_B14_5", - "GTPE2_CHANNEL_TXDLYTESTENB", - "GTPE2_CHANNEL_RXVALID", - "GTPE2_BYP1_9", - "GTPE2_LOGIC_OUTS_B7_6", - "GTPE2_CHANNEL_RXDATA24", - "GTPE2_IMUX10_2", - "GTPE2_CHANNEL_DRPADDR4", - "GTPE2_IMUX2_1", - "GTPE2_IMUX4_4", - "GTPE2_CHANNEL_PMASCANIN0", - "GTPE2_FAN3_7", - "GTPE2_CHANNEL_TXPMARESETDONE", - "GTPE2_CHANNEL_RXSYNCIN", - "GTPE2_LOGIC_OUTS_B8_10", - "GTPE2_CHANNEL_RXRATEMODE", - "GTPE2_LOGIC_OUTS_B10_9", - "GTPE2_IMUX31_10", - "GTPE2_CHANNEL_DRPDO1", - "GTPE2_CTRL0_7", - "GTPE2_CHANNEL_PLLCLK1", - "GTPE2_IMUX29_3", - "GTPE2_BYP6_1", - "GTPE2_CHANNEL_RXCOMINITDET", - "GTPE2_CHANNEL_TXDIFFPD", - "GTPE2_IMUX27_2", - "GTPE2_CHANNEL_TXDIFFCTRL0", - "GTPE2_IMUX40_1", - "GTPE2_FAN6_2", - "GTPE2_CHANNEL_TXPOSTCURSOR3", - "GTPE2_IMUX37_10", - "GTPE2_LOGIC_OUTS_B15_4", - "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "GTPE2_CHANNEL_TXMAINCURSOR6", - "GTPE2_IMUX27_1", - "GTPE2_CTRL1_7", - "GTPE2_LOGIC_OUTS_B1_5", - "GTPE2_CHANNEL_TSTIN2", - "GTPE2_CHANNEL_RXDATA9", - "GTPE2_IMUX3_5", - "GTPE2_CHANNEL_RXPHALIGNDONE", - "GTPE2_CHANNEL_RXPHMONITOR3", - "GTPE2_LOGIC_OUTS_B2_9", - "GTPE2_IMUX31_1", - "GTPE2_IMUX17_10", - "GTPE2_CHANNEL_RXCHARISCOMMA0", - "GTPE2_LOGIC_OUTS_B8_4", - "GTPE2_FAN7_6", - "GTPE2_IMUX41_2", - "GTPE2_IMUX12_0", - "GTPE2_LOGIC_OUTS_B10_5", - "GTPE2_IMUX10_0", - "GTPE2_LOGIC_OUTS_B17_8", - "GTPE2_FAN3_9", - "GTPE2_CHANNEL_RXCHARISCOMMA1", - "GTPE2_IMUX33_7", - "GTPE2_LOGIC_OUTS_B5_9", - "GTPE2_IMUX36_7", - "GTPE2_IMUX3_7", - "GTPE2_LOGIC_OUTS_B12_9", - "GTPE2_IMUX16_1", - "GTPE2_LOGIC_OUTS_B23_5", - "GTPE2_FAN2_2", - "GTPE2_IMUX0_5", - "GTPE2_CHANNEL_TXOUTCLK_0", - "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "GTPE2_CHANNEL_PCSRSVDIN6", - "GTPE2_IMUX33_3", - "GTPE2_IMUX41_4", - "GTPE2_IMUX46_6", - "GTPE2_CHANNEL_TXHEADER0", - "GTPE2_BYP0_1", - "GTPE2_IMUX1_9", - "GTPE2_CHANNEL_PCSRSVDIN8", - "GTPE2_IMUX13_4", - "GTPE2_CHANNEL_RXADAPTSELTEST1", - "GTPE2_IMUX32_9", - "GTPE2_BYP4_5", - "GTPE2_CHANNEL_GTTXOUTCLK_2", - "GTPE2_CHANNEL_RXADAPTSELTEST8", - "GTPE2_CHANNEL_TXDLYUPDOWN", - "GTPE2_IMUX44_7", - "GTPE2_IMUX19_8", - "GTPE2_IMUX41_7", - "GTPE2_IMUX19_2", - "GTPE2_CHANNEL_GTRSVD8", - "GTPE2_IMUX4_0", - "GTPE2_BYP6_7", - "GTPE2_IMUX25_10", - "GTPE2_FAN7_3", - "GTPE2_CHANNEL_RXCHBONDSLAVE", - "GTPE2_IMUX24_3", - "GTPE2_LOGIC_OUTS_B5_8", - "GTPE2_FAN0_7", - "GTPE2_IMUX45_6", - "GTPE2_CTRL0_2", - "GTPE2_IMUX43_5", - "GTPE2_CHANNEL_PCSRSVDOUT13", - "GTPE2_IMUX17_4", - "GTPE2_BYP3_7", - "GTPE2_CHANNEL_SCANOUT0", - "GTPE2_IMUX43_1", - "GTPE2_CHANNEL_RXDISPERR2", - "GTPE2_CHANNEL_RXOUTCLK_1", - "GTPE2_CHANNEL_GTRSVD1", - "GTPE2_IMUX13_8", - "GTPE2_IMUX20_4", - "GTPE2_BYP0_8", - "GTPE2_IMUX0_2", - "GTPE2_IMUX29_2", - "GTPE2_IMUX6_5", - "GTPE2_LOGIC_OUTS_B2_0", - "GTPE2_LOGIC_OUTS_B1_2", - "GTPE2_IMUX18_6", - "GTPE2_LOGIC_OUTS_B15_7", - "GTPE2_LOGIC_OUTS_B1_6", - "GTPE2_LOGIC_OUTS_B16_8", - "GTPE2_IMUX44_3", - "GTPE2_CHANNEL_PMARSVDIN1", - "GTPE2_CHANNEL_TXDATA1", - "GTPE2_CHANNEL_RXOSINTID00", - "GTPE2_LOGIC_OUTS_B3_0", - "GTPE2_CHANNEL_RXCHBONDO1", - "GTPE2_IMUX2_3", - "GTPE2_CHANNEL_RXOSINTID03", - "GTPE2_CHANNEL_PMASCANOUT1", - "GTPE2_LOGIC_OUTS_B19_3", - "GTPE2_CHANNEL_TXHEADER2", - "GTPE2_LOGIC_OUTS_B10_2", - "GTPE2_IMUX45_0", - "GTPE2_CHANNEL_DMONITOROUT6", - "GTPE2_LOGIC_OUTS_B9_3", - "GTPE2_IMUX17_8", - "GTPE2_CHANNEL_SIGVALIDCLK", - "GTPE2_IMUX31_5", - "GTPE2_LOGIC_OUTS_B2_3", - "GTPE2_FAN7_2", - "GTPE2_CHANNEL_RXPRBSSEL1", - "GTPE2_IMUX19_1", - "GTPE2_CHANNEL_PMASCANRSTEN", - "GTPE2_IMUX5_6", - "GTPE2_LOGIC_OUTS_B4_9", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "GTPE2_CHANNEL_RXPRBSCNTRESET", - "GTPE2_IMUX29_1", - "GTPE2_CHANNEL_RXDATA29", - "GTPE2_CHANNEL_RXDATA27", - "GTPE2_CHANNEL_PCSRSVDIN2", - "GTPE2_CHANNEL_PCSRSVDIN3", - "GTPE2_IMUX10_6", - "GTPE2_IMUX32_3", - "GTPE2_CHANNEL_RXOSINTHOLD", - "GTPE2_CHANNEL_DRPWE", - "GTPE2_CHANNEL_DMONITORCLK", - "GTPE2_LOGIC_OUTS_B9_1", - "GTPE2_IMUX20_7", - "GTPE2_LOGIC_OUTS_B6_2", - "GTPE2_LOGIC_OUTS_B6_3", - "GTPE2_IMUX34_10", - "GTPE2_IMUX25_5", - "GTPE2_IMUX9_6", - "GTPE2_CHANNEL_TXBUFSTATUS1", - "GTPE2_IMUX30_6", - "GTPE2_LOGIC_OUTS_B22_1", - "GTPE2_IMUX46_10", - "GTPE2_IMUX11_10", - "GTPE2_IMUX31_6", - "GTPE2_IMUX42_2", - "GTPE2_IMUX34_5", - "GTPE2_LOGIC_OUTS_B2_4", - "GTPE2_CHANNEL_RXADAPTSELTEST7", - "GTPE2_IMUX14_10", - "GTPE2_FAN0_9", - "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "GTPE2_CTRL1_3", - "GTPE2_CHANNEL_SCANIN0", - "GTPE2_FAN6_1", - "GTPE2_IMUX46_3", - "GTPE2_CHANNEL_TXSEQUENCE0", - "GTPE2_IMUX2_0", - "GTPE2_LOGIC_OUTS_B13_6", - "GTPE2_BYP4_1", - "GTPE2_CHANNEL_TXPHALIGN", - "GTPE2_CHANNEL_GTRESETSEL", - "GTPE2_LOGIC_OUTS_B13_10", - "GTPE2_CHANNEL_PLL0REFCLK", - "GTPE2_LOGIC_OUTS_B8_1", - "GTPE2_IMUX12_6", - "GTPE2_CHANNEL_RXP_PAD", - "GTPE2_IMUX25_1", - "GTPE2_IMUX29_10", - "GTPE2_IMUX30_8", - "GTPE2_IMUX2_2", - "GTPE2_LOGIC_OUTS_B14_9", - "GTPE2_LOGIC_OUTS_B23_4", - "GTPE2_IMUX30_5", - "GTPE2_CLK1_5", - "GTPE2_IMUX31_7", - "GTPE2_CHANNEL_TXMAINCURSOR4", - "GTPE2_IMUX12_3", - "GTPE2_IMUX1_5", - "GTPE2_LOGIC_OUTS_B21_7", - "GTPE2_CHANNEL_TSTIN10", - "GTPE2_IMUX45_3", - "GTPE2_CHANNEL_TXPHALIGNDONE", - "GTPE2_CHANNEL_TXDIFFCTRL3", - "GTPE2_IMUX22_9", - "GTPE2_IMUX19_4", - "GTPE2_LOGIC_OUTS_B4_7", - "GTPE2_IMUX46_8", - "GTPE2_CHANNEL_RXADAPTSELTEST12", - "GTPE2_IMUX28_1", - "GTPE2_LOGIC_OUTS_B4_6", - "GTPE2_CHANNEL_TXDEEMPH", - "GTPE2_IMUX8_8", - "GTPE2_LOGIC_OUTS_B17_10", - "GTPE2_CHANNEL_PCSRSVDIN7", - "GTPE2_LOGIC_OUTS_B4_5", - "GTPE2_IMUX31_3", - "GTPE2_CHANNEL_RXBYTEISALIGNED", - "GTPE2_CHANNEL_TSTIN8", - "GTPE2_IMUX28_8", - "GTPE2_CHANNEL_TXUSERRDY", - "GTPE2_CHANNEL_SCANIN4", - "GTPE2_CHANNEL_RXLPMLFHOLD", - "GTPE2_CHANNEL_PMARSVDIN0", - "GTPE2_IMUX12_5", - "GTPE2_FAN2_8", - "GTPE2_CHANNEL_TXRATE2", - "GTPE2_LOGIC_OUTS_B20_6", - "GTPE2_CHANNEL_TXSYNCALLIN", - "GTPE2_LOGIC_OUTS_B19_9", - "GTPE2_IMUX13_1", - "GTPE2_FAN3_2", - "GTPE2_LOGIC_OUTS_B0_4", - "GTPE2_CHANNEL_TXCHARDISPVAL0", - "GTPE2_IMUX33_2", - "GTPE2_IMUX1_4", - "GTPE2_IMUX14_8", - "GTPE2_IMUX4_10", - "GTPE2_LOGIC_OUTS_B2_5", - "GTPE2_IMUX8_6", - "GTPE2_IMUX15_2", - "GTPE2_CHANNEL_TXRATE1", - "GTPE2_BYP6_3", - "GTPE2_CHANNEL_RXNOTINTABLE2", - "GTPE2_FAN4_4", - "GTPE2_LOGIC_OUTS_B9_9", - "GTPE2_CHANNEL_TXCHARDISPMODE0", - "GTPE2_IMUX16_8", - "GTPE2_LOGIC_OUTS_B18_3", - "GTPE2_IMUX36_3", - "GTPE2_CHANNEL_TXCOMFINISH", - "GTPE2_IMUX11_4", - "GTPE2_IMUX14_9", - "GTPE2_IMUX20_2", - "GTPE2_IMUX16_5", - "GTPE2_CHANNEL_RXOOBRESET", - "GTPE2_CHANNEL_RXOSHOLD", - "GTPE2_CHANNEL_GTRXRESET", - "GTPE2_CHANNEL_TXPHINIT", - "GTPE2_CHANNEL_RXADAPTSELTEST3", - "GTPE2_IMUX36_5", - "GTPE2_BYP2_5", - "GTPE2_CLK0_9", - "GTPE2_CHANNEL_DRPDO5", - "GTPE2_IMUX20_6", - "GTPE2_CHANNEL_SCANMODEB", - "GTPE2_IMUX36_4", - "GTPE2_CLK0_10", - "GTPE2_LOGIC_OUTS_B3_6", - "GTPE2_CHANNEL_TXDATA17", - "GTPE2_LOGIC_OUTS_B6_10", - "GTPE2_CHANNEL_RXPD0", - "GTPE2_IMUX1_2", - "GTPE2_IMUX44_2", - "GTPE2_CHANNEL_DRPDO7", - "GTPE2_LOGIC_OUTS_B23_3", - "GTPE2_IMUX47_6", - "GTPE2_CHANNEL_RXPHDLYRESET", - "GTPE2_LOGIC_OUTS_B2_1", - "GTPE2_LOGIC_OUTS_B10_8", - "GTPE2_IMUX44_0", - "GTPE2_CHANNEL_TXCOMSAS", - "GTPE2_CHANNEL_DMONITOROUT12", - "GTPE2_CHANNEL_RXDATA8", - "GTPE2_IMUX2_4", - "GTPE2_CHANNEL_PCSRSVDOUT7", - "GTPE2_LOGIC_OUTS_B11_0", - "GTPE2_LOGIC_OUTS_B8_3", - "GTPE2_CHANNEL_RXDATAVALID1", - "GTPE2_CHANNEL_GTRSVD9", - "GTPE2_CHANNEL_TSTIN15", - "GTPE2_CHANNEL_TXCHARISK0", - "GTPE2_LOGIC_OUTS_B6_5", - "GTPE2_IMUX29_0", - "GTPE2_CHANNEL_TXOUTCLK_2", - "GTPE2_CHANNEL_RXCHARISK3", - "GTPE2_FAN7_4", - "GTPE2_CLK0_8", - "GTPE2_CHANNEL_GTRSVD3", - "GTPE2_CHANNEL_RXCHANISALIGNED", - "GTPE2_CHANNEL_RXCHBONDO3", - "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "GTPE2_IMUX26_5", - "GTPE2_LOGIC_OUTS_B10_10", - "GTPE2_CHANNEL_RXDLYBYPASS", - "GTPE2_CHANNEL_TSTCLK1", - "GTPE2_CHANNEL_TXDATA12", - "GTPE2_CHANNEL_DRPDO14", - "GTPE2_IMUX28_9", - "GTPE2_IMUX21_7", - "GTPE2_IMUX5_8", - "GTPE2_FAN2_6", - "GTPE2_IMUX42_1", - "GTPE2_CHANNEL_DMONITOROUT13", - "GTPE2_IMUX31_9", - "GTPE2_FAN0_5", - "GTPE2_IMUX8_7", - "GTPE2_IMUX39_9", - "GTPE2_LOGIC_OUTS_B22_0", - "GTPE2_CHANNEL_PCSRSVDIN12", - "GTPE2_CHANNEL_TXUSRCLK2", - "GTPE2_CHANNEL_RXDISPERR1", - "GTPE2_CHANNEL_DMONITOROUT14", - "GTPE2_IMUX24_1", - "GTPE2_LOGIC_OUTS_B11_9", - "GTPE2_LOGIC_OUTS_B21_5", - "GTPE2_IMUX8_5", - "GTPE2_CHANNEL_RXUSRCLK", - "GTPE2_IMUX47_8", - "GTPE2_FAN4_8", - "GTPE2_CHANNEL_RXDATA1", - "GTPE2_IMUX19_3", - "GTPE2_CHANNEL_RXPHALIGN", - "GTPE2_CHANNEL_PMARSVDIN3", - "GTPE2_CHANNEL_RXDLYSRESETDONE", - "GTPE2_LOGIC_OUTS_B7_5", - "GTPE2_IMUX37_5", - "GTPE2_CHANNEL_RXPHMONITOR2", - "GTPE2_FAN1_10", - "GTPE2_CHANNEL_RXDISPERR3", - "GTPE2_BYP2_9", - "GTPE2_LOGIC_OUTS_B17_6", - "GTPE2_CHANNEL_RXRATE2", - "GTPE2_IMUX15_10", - "GTPE2_CHANNEL_PMASCANOUT3", - "GTPE2_IMUX30_4", - "GTPE2_CHANNEL_RXOUTCLKSEL1", - "GTPE2_CHANNEL_RXDDIEN", - "GTPE2_CHANNEL_TXCHARISK3", - "GTPE2_IMUX42_0", - "GTPE2_IMUX36_9", - "GTPE2_LOGIC_OUTS_B21_10", - "GTPE2_IMUX2_8", - "GTPE2_CHANNEL_TXRATE0", - "GTPE2_CHANNEL_RXOSINTPD", - "GTPE2_IMUX4_8", - "GTPE2_CLK0_0", - "GTPE2_CHANNEL_RXPRBSSEL0", - "GTPE2_LOGIC_OUTS_B18_6", - "GTPE2_CHANNEL_RXDATA21", - "GTPE2_CHANNEL_TXDATA4", - "GTPE2_CHANNEL_RESETOVRD", - "GTPE2_BYP7_2", - "GTPE2_LOGIC_OUTS_B17_7", - "GTPE2_CHANNEL_TXDATA0", - "GTPE2_LOGIC_OUTS_B15_0", - "GTPE2_IMUX7_5", - "GTPE2_IMUX24_4", - "GTPE2_IMUX7_7", - "GTPE2_LOGIC_OUTS_B3_9", - "GTPE2_LOGIC_OUTS_B17_4", - "GTPE2_FAN6_5", - "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "GTPE2_LOGIC_OUTS_B16_2", - "GTPE2_CHANNEL_TXMARGIN2", - "GTPE2_IMUX28_10", - "GTPE2_CHANNEL_DRPDI5", - "GTPE2_LOGIC_OUTS_B21_1", - "GTPE2_IMUX44_8", - "GTPE2_LOGIC_OUTS_B9_10", - "GTPE2_CHANNEL_TXCHARDISPVAL2", - "GTPE2_IMUX25_6", - "GTPE2_CHANNEL_SCANIN3", - "GTPE2_LOGIC_OUTS_B16_5", - "GTPE2_LOGIC_OUTS_B23_6", - "GTPE2_IMUX40_6", - "GTPE2_IMUX12_1", - "GTPE2_CHANNEL_DRPDO11", - "GTPE2_CHANNEL_RXADAPTSELTEST6", - "GTPE2_IMUX31_2", - "GTPE2_IMUX29_4", - "GTPE2_LOGIC_OUTS_B13_9", - "GTPE2_IMUX38_6", - "GTPE2_LOGIC_OUTS_B12_7", - "GTPE2_IMUX40_10", - "GTPE2_IMUX0_6", - "GTPE2_CHANNEL_TXPRECURSOR0", - "GTPE2_LOGIC_OUTS_B21_4", - "GTPE2_LOGIC_OUTS_B16_0", - "GTPE2_FAN7_1", - "GTPE2_CHANNEL_DRPDI14", - "GTPE2_LOGIC_OUTS_B5_7", - "GTPE2_IMUX39_1", - "GTPE2_IMUX15_7", - "GTPE2_IMUX6_1", - "GTPE2_CHANNEL_TXPD0", - "GTPE2_IMUX26_2", - "GTPE2_IMUX27_5", - "GTPE2_LOGIC_OUTS_B19_2", - "GTPE2_IMUX13_5", - "GTPE2_LOGIC_OUTS_B16_4", - "GTPE2_CHANNEL_TXHEADER1", - "GTPE2_CLK1_10", - "GTPE2_IMUX41_8", - "GTPE2_BYP4_9", - "GTPE2_IMUX5_7", - "GTPE2_CHANNEL_RXDATA15", - "GTPE2_BYP2_2", - "GTPE2_BYP7_10", - "GTPE2_LOGIC_OUTS_B22_6", - "GTPE2_IMUX16_4", - "GTPE2_BYP1_2", - "GTPE2_LOGIC_OUTS_B9_6", - "GTPE2_BYP1_4", - "GTPE2_IMUX23_2", - "GTPE2_IMUX1_1", - "GTPE2_IMUX0_8", - "GTPE2_LOGIC_OUTS_B13_5", - "GTPE2_CHANNEL_TXPHOVRDEN", - "GTPE2_LOGIC_OUTS_B7_2", - "GTPE2_CHANNEL_DMONITOROUT7", - "GTPE2_LOGIC_OUTS_B17_3", - "GTPE2_CHANNEL_RXELECIDLEMODE1", - "GTPE2_CHANNEL_RXDISPERR0", - "GTPE2_LOGIC_OUTS_B2_10", - "GTPE2_IMUX17_1", - "GTPE2_CHANNEL_TXDLYHOLD", - "GTPE2_BYP3_8", - "GTPE2_CHANNEL_RXOUTCLKPCS", - "GTPE2_IMUX32_8", - "GTPE2_CHANNEL_DRPADDR7", - "GTPE2_IMUX7_9", - "GTPE2_IMUX46_5", - "GTPE2_IMUX20_1", - "GTPE2_CHANNEL_DMONITOROUT9", - "GTPE2_CHANNEL_DRPDO15", - "GTPE2_IMUX23_0", - "GTPE2_IMUX15_3", - "GTPE2_CHANNEL_RXOSINTCFG3", - "GTPE2_CHANNEL_RXDATA0", - "GTPE2_IMUX36_1", - "GTPE2_LOGIC_OUTS_B23_8", - "GTPE2_IMUX37_2", - "GTPE2_CHANNEL_TXP_PAD", - "GTPE2_IMUX43_6", - "GTPE2_CHANNEL_RXDATA18", - "GTPE2_IMUX21_9", - "GTPE2_CLK1_4", - "GTPE2_CHANNEL_TXGEARBOXREADY", - "GTPE2_LOGIC_OUTS_B10_6", - "GTPE2_LOGIC_OUTS_B20_0", - "GTPE2_IMUX6_2", - "GTPE2_IMUX23_1", - "GTPE2_CHANNEL_TXPOSTCURSOR0", - "GTPE2_BYP5_4", - "GTPE2_CHANNEL_TXDATA14", - "GTPE2_CHANNEL_GTRSVD13", - "GTPE2_CHANNEL_TXSEQUENCE1", - "GTPE2_IMUX14_7", - "GTPE2_CHANNEL_TXPHINITDONE", - "GTPE2_CHANNEL_EYESCANMODE", - "GTPE2_CHANNEL_PLL0CLK", - "GTPE2_CHANNEL_TXDETECTRX", - "GTPE2_LOGIC_OUTS_B4_10", - "GTPE2_LOGIC_OUTS_B14_10", - "GTPE2_IMUX35_6", - "GTPE2_CHANNEL_TXOUTCLK_1", - "GTPE2_CHANNEL_RXDATA17", - "GTPE2_BYP7_7", - "GTPE2_CTRL0_8", - "GTPE2_CHANNEL_PLL1CLK", - "GTPE2_IMUX25_9", - "GTPE2_CHANNEL_CLKRSVD0", - "GTPE2_IMUX3_0", - "GTPE2_IMUX18_4", - "GTPE2_IMUX20_5", - "GTPE2_BYP1_5", - "GTPE2_IMUX42_4", - "GTPE2_LOGIC_OUTS_B22_10", - "GTPE2_IMUX7_0", - "GTPE2_CHANNEL_RXBYTEREALIGN", - "GTPE2_CHANNEL_RXDATA26", - "GTPE2_CHANNEL_RXPHMONITOR0", - "GTPE2_CHANNEL_PMASCANIN2", - "GTPE2_CHANNEL_RXPHALIGNEN", - "GTPE2_IMUX45_9", - "GTPE2_CTRL1_6", - "GTPE2_CHANNEL_RXOSINTNTRLEN", - "GTPE2_CHANNEL_SCANOUT5", - "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "GTPE2_CHANNEL_RXCOMSASDET", - "GTPE2_IMUX31_0", - "GTPE2_CHANNEL_TXDLYBYPASS", - "GTPE2_IMUX22_5", - "GTPE2_CHANNEL_RXDATA6", - "GTPE2_CHANNEL_TXPISOPD", - "GTPE2_CHANNEL_PCSRSVDIN15", - "GTPE2_IMUX3_8", - "GTPE2_CHANNEL_RXNOTINTABLE0", - "GTPE2_CHANNEL_RXADAPTSELTEST4", - "GTPE2_CHANNEL_TXMAINCURSOR0", - "GTPE2_CHANNEL_PCSRSVDOUT5", - "GTPE2_CHANNEL_TXDATA6", - "GTPE2_CHANNEL_RXOSINTSTARTED", - "GTPE2_IMUX10_10", - "GTPE2_LOGIC_OUTS_B2_8", - "GTPE2_LOGIC_OUTS_B4_8", - "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "GTPE2_BYP6_0", - "GTPE2_CHANNEL_RXOUTCLK_0", - "GTPE2_CHANNEL_RXOSINTCFG2", - "GTPE2_CHANNEL_GTRSVD4", - "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "GTPE2_LOGIC_OUTS_B14_2", - "GTPE2_CHANNEL_TSTIN14", - "GTPE2_CHANNEL_DMONITOROUT0", - "GTPE2_LOGIC_OUTS_B4_4", - "GTPE2_CHANNEL_DRPDO0", - "GTPE2_IMUX38_5", - "GTPE2_LOGIC_OUTS_B0_5", - "GTPE2_CHANNEL_RXRATE0", - "GTPE2_CHANNEL_RXCHANREALIGN", - "GTPE2_CHANNEL_RXCHBONDMASTER", - "GTPE2_FAN6_10", - "GTPE2_IMUX22_2", - "GTPE2_IMUX29_9", - "GTPE2_CHANNEL_RXDATA16", - "GTPE2_CHANNEL_RXADAPTSELTEST9", - "GTPE2_IMUX23_7", - "GTPE2_IMUX43_7", - "GTPE2_IMUX11_8", - "GTPE2_CHANNEL_TXDATA7", - "GTPE2_LOGIC_OUTS_B9_2", - "GTPE2_CHANNEL_TXPD1", - "GTPE2_FAN1_7", - "GTPE2_CHANNEL_RXDATA25", - "GTPE2_IMUX24_0", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "GTPE2_CHANNEL_SCANOUT2", - "GTPE2_IMUX10_8", - "GTPE2_CHANNEL_DRPDI0", - "GTPE2_CHANNEL_RXDATA5", - "GTPE2_CHANNEL_PCSRSVDIN4", - "GTPE2_BYP3_5", - "GTPE2_CHANNEL_DRPDO2", - "GTPE2_CHANNEL_DMONFIFORESET", - "GTPE2_IMUX39_3", - "GTPE2_LOGIC_OUTS_B10_7", - "GTPE2_BYP3_3", - "GTPE2_CHANNEL_TX8B10BBYPASS2", - "GTPE2_IMUX3_3", - "GTPE2_CHANNEL_RXDATA30", - "GTPE2_CHANNEL_TXOUTCLKSEL2", - "GTPE2_IMUX24_8", - "GTPE2_IMUX38_0", - "GTPE2_IMUX20_3", - "GTPE2_CHANNEL_TXRATEMODE", - "GTPE2_IMUX12_2", - "GTPE2_LOGIC_OUTS_B21_6", - "GTPE2_IMUX39_7", - "GTPE2_LOGIC_OUTS_B15_8", - "GTPE2_CHANNEL_RXPMARESETDONE", - "GTPE2_CHANNEL_RXPMARESET", - "GTPE2_IMUX39_8", - "GTPE2_IMUX6_6", - "GTPE2_CHANNEL_TXDATA22", - "GTPE2_CHANNEL_TXCHARISK1", - "GTPE2_FAN6_6", - "GTPE2_IMUX5_0", - "GTPE2_LOGIC_OUTS_B12_6", - "GTPE2_BYP4_0", - "GTPE2_CHANNEL_TSTIN12", - "GTPE2_IMUX11_6", - "GTPE2_LOGIC_OUTS_B3_1", - "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "GTPE2_IMUX45_8", - "GTPE2_FAN5_5", - "GTPE2_CHANNEL_TXOUTCLK_3", - "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "GTPE2_CHANNEL_PCSRSVDOUT4", - "GTPE2_IMUX9_2", - "GTPE2_IMUX35_10", - "GTPE2_CHANNEL_RX8B10BEN", - "GTPE2_CHANNEL_RXCDRFREQRESET", - "GTPE2_CHANNEL_RXGEARBOXSLIP", - "GTPE2_IMUX35_0", - "GTPE2_IMUX18_5", - "GTPE2_CHANNEL_RXCHARISCOMMA2", - "GTPE2_CHANNEL_SCANCLK", - "GTPE2_CHANNEL_TXDATA5", - "GTPE2_LOGIC_OUTS_B21_8", - "GTPE2_IMUX21_6", - "GTPE2_LOGIC_OUTS_B11_7", - "GTPE2_CHANNEL_RXPHOVRDEN", - "GTPE2_BYP4_4", - "GTPE2_IMUX5_5", - "GTPE2_LOGIC_OUTS_B3_5", - "GTPE2_LOGIC_OUTS_B17_9", - "GTPE2_FAN6_4", - "GTPE2_IMUX37_8", - "GTPE2_LOGIC_OUTS_B12_0", - "GTPE2_BYP2_6", - "GTPE2_IMUX7_2", - "GTPE2_CHANNEL_TSTPD4", - "GTPE2_CHANNEL_RXHEADER2", - "GTPE2_FAN7_7", - "GTPE2_IMUX26_0", - "GTPE2_CHANNEL_GTRSVD11", - "GTPE2_LOGIC_OUTS_B20_9", - "GTPE2_CHANNEL_TSTIN1", - "GTPE2_IMUX15_0", - "GTPE2_FAN0_6", - "GTPE2_CHANNEL_RXDATA14", - "GTPE2_LOGIC_OUTS_B22_2", - "GTPE2_IMUX5_3", - "GTPE2_IMUX41_3", - "GTPE2_LOGIC_OUTS_B9_8", - "GTPE2_CHANNEL_LOOPBACK0", - "GTPE2_LOGIC_OUTS_B18_7", - "GTPE2_LOGIC_OUTS_B16_1", - "GTPE2_IMUX38_8", - "GTPE2_IMUX15_5", - "GTPE2_CHANNEL_RXHEADER1", - "GTPE2_CHANNEL_TXPRBSSEL0", - "GTPE2_CHANNEL_RXLPMHFHOLD", - "GTPE2_LOGIC_OUTS_B8_9", - "GTPE2_BYP6_10", - "GTPE2_CLK1_7", - "GTPE2_CTRL1_1", - "GTPE2_CHANNEL_DRPADDR5", - "GTPE2_LOGIC_OUTS_B0_8", - "GTPE2_CHANNEL_TXDATA16", - "GTPE2_CHANNEL_GTRSVD6", - "GTPE2_CHANNEL_RXCHANBONDSEQ", - "GTPE2_IMUX18_7", - "GTPE2_LOGIC_OUTS_B5_2", - "GTPE2_BYP5_9", - "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "GTPE2_IMUX17_2", - "GTPE2_CHANNEL_TXSEQUENCE6", - "GTPE2_FAN6_8", - "GTPE2_IMUX34_9", - "GTPE2_CHANNEL_TXDLYEN", - "GTPE2_IMUX40_4", - "GTPE2_IMUX9_0", - "GTPE2_CHANNEL_TXDATA27", - "GTPE2_IMUX29_5", - "GTPE2_IMUX28_7", - "GTPE2_CHANNEL_PMASCANIN4", - "GTPE2_CHANNEL_PCSRSVDOUT6", - "GTPE2_IMUX43_8", - "GTPE2_IMUX40_7", - "GTPE2_LOGIC_OUTS_B23_10", - "GTPE2_IMUX45_5", - "GTPE2_IMUX4_1", - "GTPE2_IMUX10_1", - "GTPE2_IMUX37_0", - "GTPE2_BYP3_2", - "GTPE2_IMUX28_2", - "GTPE2_CHANNEL_TXDATA26", - "GTPE2_CHANNEL_TXDATA31", - "GTPE2_FAN0_10", - "GTPE2_LOGIC_OUTS_B7_9", - "GTPE2_BYP3_1", - "GTPE2_IMUX23_8", - "GTPE2_CHANNEL_RXCHARISK1", - "GTPE2_BYP5_6", - "GTPE2_CHANNEL_PHYSTATUS", - "GTPE2_CHANNEL_TXINHIBIT", - "GTPE2_CHANNEL_RXUSERRDY", - "GTPE2_IMUX24_6", - "GTPE2_CHANNEL_RXDATA23", - "GTPE2_IMUX13_10", - "GTPE2_IMUX34_3", - "GTPE2_CHANNEL_PMARSVDOUT1", - "GTPE2_IMUX5_4", - "GTPE2_CLK0_6", - "GTPE2_BYP5_8", - "GTPE2_IMUX18_10", - "GTPE2_FAN7_8", - "GTPE2_FAN5_2", - "GTPE2_CTRL0_6", - "GTPE2_CHANNEL_DRPDI10", - "GTPE2_FAN5_0", - "GTPE2_CHANNEL_RXCHARISK0", - "GTPE2_IMUX22_3", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "GTPE2_IMUX5_1", - "GTPE2_CHANNEL_DMONITOROUT1", - "GTPE2_IMUX33_5", - "GTPE2_CHANNEL_DRPDI9", - "GTPE2_CHANNEL_TXMARGIN1", - "GTPE2_IMUX10_3", - "GTPE2_CHANNEL_RXNOTINTABLE1", - "GTPE2_BYP6_9", - "GTPE2_IMUX5_2", - "GTPE2_IMUX38_4", - "GTPE2_IMUX46_4", - "GTPE2_CHANNEL_RXSYNCALLIN", - "GTPE2_CHANNEL_RXSTATUS1", - "GTPE2_IMUX12_7", - "GTPE2_FAN3_8", - "GTPE2_IMUX22_10", - "GTPE2_IMUX20_9", - "GTPE2_LOGIC_OUTS_B11_1", - "GTPE2_CHANNEL_PMASCANIN6", - "GTPE2_CHANNEL_TXSYNCIN", - "GTPE2_CHANNEL_TXSEQUENCE5", - "GTPE2_CHANNEL_TXDLYSRESETDONE", - "GTPE2_LOGIC_OUTS_B0_2", - "GTPE2_IMUX15_4", - "GTPE2_LOGIC_OUTS_B16_6", - "GTPE2_IMUX38_2", - "GTPE2_IMUX16_7", - "GTPE2_IMUX27_9", - "GTPE2_LOGIC_OUTS_B18_8", - "GTPE2_LOGIC_OUTS_B8_0", - "GTPE2_LOGIC_OUTS_B21_2", - "GTPE2_IMUX41_1", - "GTPE2_CHANNEL_TXUSRCLK", - "GTPE2_IMUX35_7", - "GTPE2_CHANNEL_TXMAINCURSOR5", - "GTPE2_CHANNEL_RXDLYSRESET", - "GTPE2_CHANNEL_DRPDI13", - "GTPE2_LOGIC_OUTS_B6_9", - "GTPE2_CHANNEL_RXOUTCLKSEL2", - "GTPE2_LOGIC_OUTS_B3_8", - "GTPE2_LOGIC_OUTS_B6_4", - "GTPE2_CHANNEL_DMONITOROUT11", - "GTPE2_LOGIC_OUTS_B2_7", - "GTPE2_IMUX6_3", - "GTPE2_IMUX20_0", - "GTPE2_IMUX12_10", - "GTPE2_CTRL0_10", - "GTPE2_CHANNEL_RXCOMMADET", - "GTPE2_CHANNEL_TXPOLARITY", - "GTPE2_CHANNEL_TXPRBSSEL2", - "GTPE2_LOGIC_OUTS_B5_4", - "GTPE2_IMUX37_1", - "GTPE2_CHANNEL_RXADAPTSELTEST13", - "GTPE2_IMUX27_7", - "GTPE2_IMUX44_9", - "GTPE2_IMUX36_10", - "GTPE2_FAN5_6", - "GTPE2_IMUX18_9", - "GTPE2_CLK1_3", - "GTPE2_IMUX26_10", - "GTPE2_IMUX32_6", - "GTPE2_IMUX36_6", - "GTPE2_IMUX14_5", - "GTPE2_LOGIC_OUTS_B18_1", - "GTPE2_IMUX46_9", - "GTPE2_CHANNEL_TXDLYSRESET", - "GTPE2_CHANNEL_RXCHARISK2", - "GTPE2_IMUX28_4", - "GTPE2_CHANNEL_PMARSVDIN2", - "GTPE2_CLK1_8", - "GTPE2_IMUX39_0", - "GTPE2_LOGIC_OUTS_B2_2", - "GTPE2_BYP6_4", - "GTPE2_IMUX30_2", - "GTPE2_LOGIC_OUTS_B10_4", - "GTPE2_CHANNEL_DRPADDR8", - "GTPE2_CHANNEL_DMONITOROUT4", - "GTPE2_IMUX19_6", - "GTPE2_FAN4_10", - "GTPE2_IMUX34_6", - "GTPE2_BYP4_3", - "GTPE2_CHANNEL_TX8B10BEN", - "GTPE2_LOGIC_OUTS_B11_6", - "GTPE2_IMUX28_6", - "GTPE2_CHANNEL_RXOSINTDONE", - "GTPE2_CHANNEL_TXOUTCLKSEL1", - "GTPE2_LOGIC_OUTS_B9_4", - "GTPE2_IMUX8_3", - "GTPE2_CHANNEL_DRPDI4", - "GTPE2_CHANNEL_TXSYSCLKSEL0", - "GTPE2_LOGIC_OUTS_B10_1", - "GTPE2_LOGIC_OUTS_B12_1", - "GTPE2_IMUX17_7", - "GTPE2_IMUX9_1", - "GTPE2_CHANNEL_PMASCANIN5", - "GTPE2_FAN0_3", - "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "GTPE2_BYP2_1", - "GTPE2_CHANNEL_RXOSINTSTROBE", - "GTPE2_IMUX40_8", - "GTPE2_IMUX3_10", - "GTPE2_CHANNEL_LOOPBACK2", - "GTPE2_IMUX35_1", - "GTPE2_LOGIC_OUTS_B19_6", - "GTPE2_CHANNEL_TXDATA25", - "GTPE2_IMUX40_2", - "GTPE2_IMUX8_2", - "GTPE2_CHANNEL_TXSYSCLKSEL1", - "GTPE2_IMUX36_2", - "GTPE2_CHANNEL_RXDLYOVRDEN", - "GTPE2_FAN3_0", - "GTPE2_CHANNEL_RXDATA20", - "GTPE2_IMUX22_7", - "GTPE2_IMUX35_8", - "GTPE2_CHANNEL_DRPDO3", - "GTPE2_CHANNEL_RXOUTCLKSEL0", - "GTPE2_LOGIC_OUTS_B11_3", - "GTPE2_CHANNEL_TXDIFFCTRL2", - "GTPE2_IMUX7_8", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "GTPE2_CHANNEL_RXDEBUGPULSE", - "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "GTPE2_CTRL0_1", - "GTPE2_CHANNEL_TXCHARDISPVAL3", - "GTPE2_LOGIC_OUTS_B2_6", - "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "GTPE2_BYP7_5", - "GTPE2_IMUX0_3", - "GTPE2_CHANNEL_TSTIN3", - "GTPE2_CHANNEL_DRPDI15", - "GTPE2_LOGIC_OUTS_B20_1", - "GTPE2_BYP2_7", - "GTPE2_CHANNEL_EYESCANDATAERROR", - "GTPE2_LOGIC_OUTS_B19_0", - "GTPE2_LOGIC_OUTS_B17_0", - "GTPE2_CHANNEL_RXOSINTCFG0", - "GTPE2_IMUX7_1", - "GTPE2_CHANNEL_RXELECIDLEMODE0", - "GTPE2_CHANNEL_DRPDO4", - "GTPE2_LOGIC_OUTS_B1_9", - "GTPE2_CHANNEL_RXSYNCDONE", - "GTPE2_CHANNEL_DRPADDR1", - "GTPE2_BYP6_8", - "GTPE2_IMUX0_1", - "GTPE2_CHANNEL_RXDATA28", - "GTPE2_IMUX6_8", - "GTPE2_IMUX10_4", - "GTPE2_IMUX46_2", - "GTPE2_IMUX35_2", - "GTPE2_IMUX33_6", - "GTPE2_IMUX7_10", - "GTPE2_CHANNEL_RXCDRRESETRSV", - "GTPE2_BYP7_1", - "GTPE2_CHANNEL_SCANENB", - "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "GTPE2_CHANNEL_TSTIN16", - "GTPE2_CHANNEL_TSTIN4", - "GTPE2_CHANNEL_TXDATA3", - "GTPE2_BYP5_7", - "GTPE2_LOGIC_OUTS_B20_10", - "GTPE2_IMUX33_8", - "GTPE2_CHANNEL_TSTPD2", - "GTPE2_IMUX27_8", - "GTPE2_CHANNEL_RXPHMONITOR4", - "GTPE2_CHANNEL_DRPDI8", - "GTPE2_LOGIC_OUTS_B19_10", - "GTPE2_CLK1_9", - "GTPE2_CHANNEL_TXRESETDONE", - "GTPE2_IMUX3_1", - "GTPE2_IMUX25_3", - "GTPE2_IMUX47_1", - "GTPE2_BYP5_0", - "GTPE2_CHANNEL_SCANIN2", - "GTPE2_IMUX33_1", - "GTPE2_LOGIC_OUTS_B14_3", - "GTPE2_CHANNEL_TXDATA20", - "GTPE2_IMUX26_7", - "GTPE2_LOGIC_OUTS_B4_1", - "GTPE2_BYP6_2", - "GTPE2_IMUX16_9", - "GTPE2_CHANNEL_RXSYSCLKSEL1", - "GTPE2_IMUX41_10", - "GTPE2_CHANNEL_RXCDRHOLD", - "GTPE2_BYP0_3", - "GTPE2_FAN2_9", - "GTPE2_CHANNEL_TXOUTCLKPCS", - "GTPE2_LOGIC_OUTS_B17_5", - "GTPE2_CHANNEL_PLLREFCLK0", - "GTPE2_LOGIC_OUTS_B16_9", - "GTPE2_IMUX37_6", - "GTPE2_CHANNEL_RXPRBSERR", - "GTPE2_LOGIC_OUTS_B11_4", - "GTPE2_IMUX14_0", - "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "GTPE2_CHANNEL_TXDATA29", - "GTPE2_LOGIC_OUTS_B14_7", - "GTPE2_LOGIC_OUTS_B1_1", - "GTPE2_IMUX17_9", - "GTPE2_IMUX21_3", - "GTPE2_LOGIC_OUTS_B14_4", - "GTPE2_CHANNEL_GTRSVD15", - "GTPE2_IMUX24_10", - "GTPE2_LOGIC_OUTS_B0_9", - "GTPE2_CHANNEL_PMASCANOUT6", - "GTPE2_IMUX4_6", - "GTPE2_LOGIC_OUTS_B11_2", - "GTPE2_CHANNEL_RXCHBONDO0", - "GTPE2_CHANNEL_RXOUTCLK_2", - "GTPE2_CHANNEL_RXADAPTSELTEST10", - "GTPE2_BYP4_8", - "GTPE2_CHANNEL_RXDATA4", - "GTPE2_CHANNEL_PCSRSVDIN0", - "GTPE2_CHANNEL_RXADAPTSELTEST2", - "GTPE2_LOGIC_OUTS_B14_1", - "GTPE2_CHANNEL_TXPRBSSEL1", - "GTPE2_LOGIC_OUTS_B15_3", - "GTPE2_LOGIC_OUTS_B13_0", - "GTPE2_CHANNEL_TXPRECURSORINV", - "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "GTPE2_CHANNEL_TXMAINCURSOR1", - "GTPE2_CHANNEL_RXOSINTOVRDEN", - "GTPE2_CHANNEL_TXDATA23", - "GTPE2_CHANNEL_TXRUNDISP0", - "GTPE2_LOGIC_OUTS_B4_2", - "GTPE2_BYP0_4", - "GTPE2_BYP3_6", - "GTPE2_LOGIC_OUTS_B9_5", - "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "GTPE2_CTRL1_10", - "GTPE2_CHANNEL_RXOSINTID02", - "GTPE2_IMUX16_2", - "GTPE2_CHANNEL_RXRATEDONE", - "GTPE2_BYP0_0", - "GTPE2_CHANNEL_TXCOMWAKE", - "GTPE2_IMUX43_3", - "GTPE2_LOGIC_OUTS_B13_7", - "GTPE2_CHANNEL_TXPOSTCURSOR4", - "GTPE2_IMUX22_4", - "GTPE2_IMUX21_1", - "GTPE2_FAN1_9", - "GTPE2_IMUX29_7", - "GTPE2_LOGIC_OUTS_B8_6", - "GTPE2_BYP7_8", - "GTPE2_IMUX23_5", - "GTPE2_CHANNEL_DRPDO10", - "GTPE2_CHANNEL_DRPDI6", - "GTPE2_IMUX32_1", - "GTPE2_IMUX22_8", - "GTPE2_FAN7_0", - "GTPE2_CHANNEL_RXLPMRESET", - "GTPE2_IMUX13_2", - "GTPE2_CHANNEL_PCSRSVDIN10", - "GTPE2_IMUX46_1", - "GTPE2_CHANNEL_TSTIN18", - "GTPE2_CHANNEL_TXPHDLYRESET", - "GTPE2_FAN6_3", - "GTPE2_CHANNEL_DMONITOROUT3", - "GTPE2_IMUX41_0", - "GTPE2_IMUX13_6", - "GTPE2_IMUX11_1", - "GTPE2_CHANNEL_PCSRSVDOUT9", - "GTPE2_CHANNEL_DRPEN", - "GTPE2_IMUX38_10", - "GTPE2_CHANNEL_TSTPDOVRDB", - "GTPE2_BYP2_8", - "GTPE2_CTRL1_0", - "GTPE2_IMUX2_5", - "GTPE2_CHANNEL_RXDLYEN", - "GTPE2_LOGIC_OUTS_B6_1", - "GTPE2_FAN7_10", - "GTPE2_IMUX17_0", - "GTPE2_CHANNEL_TSTIN19", - "GTPE2_IMUX29_8", - "GTPE2_IMUX11_5", - "GTPE2_LOGIC_OUTS_B22_5", - "GTPE2_CHANNEL_RXDATA3", - "GTPE2_CHANNEL_RXOSINTCFG1", - "GTPE2_IMUX24_5", - "GTPE2_CHANNEL_GTRSVD10", - "GTPE2_LOGIC_OUTS_B20_5", - "GTPE2_LOGIC_OUTS_B20_3", - "GTPE2_CHANNEL_TXSYNCDONE", - "GTPE2_BYP0_6", - "GTPE2_LOGIC_OUTS_B1_0", - "GTPE2_LOGIC_OUTS_B1_4", - "GTPE2_IMUX42_9", - "GTPE2_BYP6_5", - "GTPE2_IMUX47_5", - "GTPE2_CHANNEL_LOOPBACK1", - "GTPE2_IMUX13_9", - "GTPE2_CHANNEL_TXPHALIGNEN", - "GTPE2_IMUX12_4", - "GTPE2_CHANNEL_RXADAPTSELTEST11", - "GTPE2_IMUX44_6", - "GTPE2_CHANNEL_TXELECIDLE", - "GTPE2_CTRL0_0", - "GTPE2_LOGIC_OUTS_B3_7", - "GTPE2_IMUX35_4", - "GTPE2_CHANNEL_RXCHBONDI0", - "GTPE2_CHANNEL_TXCHARDISPMODE1", - "GTPE2_LOGIC_OUTS_B7_10", - "GTPE2_CHANNEL_RXOSINTEN", - "GTPE2_LOGIC_OUTS_B21_3", - "GTPE2_CHANNEL_TXDATA15", - "GTPE2_BYP0_7", - "GTPE2_IMUX2_6", - "GTPE2_BYP3_10", - "GTPE2_FAN1_1", - "GTPE2_CHANNEL_TSTIN6", - "GTPE2_FAN1_4", - "GTPE2_IMUX14_2", - "GTPE2_CHANNEL_PMASCANIN3", - "GTPE2_CHANNEL_TXDATA18", - "GTPE2_IMUX0_4", - "GTPE2_CHANNEL_TSTIN17", - "GTPE2_LOGIC_OUTS_B3_4", - "GTPE2_LOGIC_OUTS_B1_8", - "GTPE2_BYP1_8", - "GTPE2_CHANNEL_RXSTATUS2", - "GTPE2_BYP5_2", - "GTPE2_CHANNEL_PCSRSVDIN11", - "GTPE2_IMUX38_9", - "GTPE2_BYP7_6", - "GTPE2_CHANNEL_PMASCANCLK1", - "GTPE2_CHANNEL_RXBUFSTATUS0", - "GTPE2_IMUX11_0", - "GTPE2_FAN4_9", - "GTPE2_LOGIC_OUTS_B12_8", - "GTPE2_BYP1_3", - "GTPE2_BYP0_10", - "GTPE2_CHANNEL_RXOSCALRESET", - "GTPE2_IMUX6_0", - "GTPE2_CHANNEL_TSTIN11", - "GTPE2_CLK0_3", - "GTPE2_CHANNEL_CLKRSVD1", - "GTPE2_FAN3_10", - "GTPE2_IMUX19_0", - "GTPE2_CHANNEL_RXHEADER0", - "GTPE2_CHANNEL_TXPRBSFORCEERR", - "GTPE2_CHANNEL_PCSRSVDIN13", - "GTPE2_IMUX46_7", - "GTPE2_CHANNEL_PCSRSVDOUT14", - "GTPE2_LOGIC_OUTS_B15_10", - "GTPE2_CHANNEL_TSTPD3", - "GTPE2_LOGIC_OUTS_B12_2", - "GTPE2_IMUX45_1", - "GTPE2_IMUX0_0", - "GTPE2_IMUX39_10", - "GTPE2_CHANNEL_DMONITOROUT10", - "GTPE2_CHANNEL_RXCDRLOCK", - "GTPE2_IMUX4_2", - "GTPE2_CHANNEL_TXMAINCURSOR2", - "GTPE2_CHANNEL_PCSRSVDIN9", - "GTPE2_IMUX10_5", - "GTPE2_CHANNEL_PMASCANCLK0", - "GTPE2_IMUX18_8", - "GTPE2_CHANNEL_TXSYNCMODE", - "GTPE2_CHANNEL_TXN_PAD", - "GTPE2_CHANNEL_TXPMARESET", - "GTPE2_IMUX43_10", - "GTPE2_BYP5_10", - "GTPE2_CHANNEL_DRPADDR0", - "GTPE2_CHANNEL_PCSRSVDOUT1", - "GTPE2_CHANNEL_PMARSVDIN4", - "GTPE2_IMUX14_1", - "GTPE2_CHANNEL_SCANIN5", - "GTPE2_LOGIC_OUTS_B0_1", - "GTPE2_CHANNEL_PCSRSVDOUT12", - "GTPE2_CHANNEL_DRPDI7", - "GTPE2_IMUX26_6", - "GTPE2_IMUX17_6", - "GTPE2_LOGIC_OUTS_B1_7", - "GTPE2_CHANNEL_RXDATA7", - "GTPE2_CHANNEL_TXCHARDISPMODE3", - "GTPE2_IMUX26_8", - "GTPE2_IMUX0_9", - "GTPE2_FAN3_6", - "GTPE2_IMUX46_0", - "GTPE2_CHANNEL_TSTIN7", - "GTPE2_LOGIC_OUTS_B20_7", - "GTPE2_LOGIC_OUTS_B17_2", - "GTPE2_CHANNEL_TXCHARDISPVAL1", - "GTPE2_CHANNEL_TXSEQUENCE4", - "GTPE2_CHANNEL_TXPOSTCURSOR2", - "GTPE2_CHANNEL_DRPDI2", - "GTPE2_FAN2_10", - "GTPE2_CHANNEL_RXBUFSTATUS2", - "GTPE2_IMUX1_7", - "GTPE2_IMUX10_7", - "GTPE2_CHANNEL_SCANOUT4", - "GTPE2_LOGIC_OUTS_B18_0", - "GTPE2_CHANNEL_DRPDO9", - "GTPE2_FAN6_9", - "GTPE2_IMUX4_7", - "GTPE2_CHANNEL_TSTPD1", - "GTPE2_IMUX39_6", - "GTPE2_CHANNEL_TXPRECURSOR2", - "GTPE2_IMUX43_0", - "GTPE2_FAN1_6", - "GTPE2_BYP1_1", - "GTPE2_FAN5_3", - "GTPE2_CHANNEL_DMONITOROUT2", - "GTPE2_LOGIC_OUTS_B19_4", - "GTPE2_CHANNEL_PMASCANMODEB", - "GTPE2_IMUX37_9", - "GTPE2_LOGIC_OUTS_B22_3", - "GTPE2_FAN1_3", - "GTPE2_IMUX5_9", - "GTPE2_CHANNEL_RXELECIDLE", - "GTPE2_IMUX34_8", - "GTPE2_FAN2_4", - "GTPE2_IMUX24_2", - "GTPE2_LOGIC_OUTS_B22_4", - "GTPE2_IMUX34_4", - "GTPE2_LOGIC_OUTS_B0_10", - "GTPE2_IMUX29_6", - "GTPE2_IMUX45_10", - "GTPE2_CLK1_6", - "GTPE2_CHANNEL_PMASCANENB", - "GTPE2_CHANNEL_TXDATA8", - "GTPE2_CLK0_7", - "GTPE2_IMUX30_1", - "GTPE2_LOGIC_OUTS_B11_8", - "GTPE2_CHANNEL_RXHEADERVALID", - "GTPE2_FAN5_1", - "GTPE2_CHANNEL_PCSRSVDOUT3", - "GTPE2_IMUX2_9", - "GTPE2_CHANNEL_TXPIPPMPD", - "GTPE2_IMUX44_5", - "GTPE2_IMUX22_0", - "GTPE2_CHANNEL_TXPIPPMEN", - "GTPE2_FAN5_10", - "GTPE2_BYP1_0", - "GTPE2_IMUX11_7", - "GTPE2_CHANNEL_TXDATA10", - "GTPE2_IMUX34_2", - "GTPE2_LOGIC_OUTS_B4_0", - "GTPE2_CHANNEL_GTRSVD5", - "GTPE2_LOGIC_OUTS_B8_7", - "GTPE2_IMUX44_4", - "GTPE2_IMUX41_5", - "GTPE2_CHANNEL_TXDLYOVRDEN", - "GTPE2_IMUX37_4", - "GTPE2_BYP6_6", - "GTPE2_IMUX44_10", - "GTPE2_CHANNEL_DRPADDR2", - "GTPE2_CLK0_5", - "GTPE2_CHANNEL_DRPDI11", - "GTPE2_LOGIC_OUTS_B7_1", - "GTPE2_IMUX8_0", - "GTPE2_IMUX25_4", - "GTPE2_LOGIC_OUTS_B7_8", - "GTPE2_CHANNEL_TXBUFSTATUS0", - "GTPE2_IMUX30_3", - "GTPE2_IMUX27_4", - "GTPE2_LOGIC_OUTS_B8_8", - "GTPE2_CHANNEL_DRPADDR6", - "GTPE2_IMUX0_7", - "GTPE2_IMUX42_8", - "GTPE2_IMUX33_4", - "GTPE2_BYP0_9", - "GTPE2_LOGIC_OUTS_B6_0", - "GTPE2_LOGIC_OUTS_B22_8", - "GTPE2_CHANNEL_RXOSINTID01", - "GTPE2_IMUX40_5", - "GTPE2_CHANNEL_DRPDO6", - "GTPE2_CHANNEL_RXSYSCLKSEL0", - "GTPE2_CLK1_2", - "GTPE2_FAN5_9", - "GTPE2_IMUX6_10", - "GTPE2_LOGIC_OUTS_B12_4", - "GTPE2_IMUX13_7", - "GTPE2_IMUX25_7", - "GTPE2_IMUX7_3", - "GTPE2_BYP7_9", - "GTPE2_CHANNEL_RXCHBONDO2", - "GTPE2_LOGIC_OUTS_B17_1", - "GTPE2_LOGIC_OUTS_B15_2", - "GTPE2_CHANNEL_PCSRSVDIN5", - "GTPE2_LOGIC_OUTS_B5_0", - "GTPE2_LOGIC_OUTS_B3_10", - "GTPE2_CHANNEL_DRPDI12", - "GTPE2_IMUX23_9", - "GTPE2_LOGIC_OUTS_B9_0", - "GTPE2_IMUX7_4", - "GTPE2_CHANNEL_TSTIN0", - "GTPE2_FAN5_8", - "GTPE2_LOGIC_OUTS_B13_1", - "GTPE2_IMUX32_0", - "GTPE2_CHANNEL_RXPRBSSEL2", - "GTPE2_IMUX45_2", - "GTPE2_CHANNEL_DRPDI1", - "GTPE2_CHANNEL_TXDATA19", - "GTPE2_FAN6_7", - "GTPE2_CHANNEL_RXDATA11", - "GTPE2_CHANNEL_RXCOMMADETEN", - "GTPE2_CHANNEL_TXN", - "GTPE2_CHANNEL_TXRATEDONE", - "GTPE2_IMUX39_5", - "GTPE2_FAN0_2", - "GTPE2_IMUX18_0", - "GTPE2_IMUX16_10", - "GTPE2_CHANNEL_PMASCANOUT0", - "GTPE2_CHANNEL_PMASCANIN1", - "GTPE2_LOGIC_OUTS_B13_3", - "GTPE2_IMUX36_0", - "GTPE2_BYP7_4", - "GTPE2_CHANNEL_RXPOLARITY", - "GTPE2_LOGIC_OUTS_B7_0", - "GTPE2_CHANNEL_DRPDO8", - "GTPE2_LOGIC_OUTS_B0_0", - "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "GTPE2_IMUX4_3", - "GTPE2_CHANNEL_SCANOUT1", - "GTPE2_CHANNEL_PCSRSVDOUT15", - "GTPE2_CHANNEL_TXOUTCLKSEL0", - "GTPE2_CHANNEL_DRPCLK", - "GTPE2_LOGIC_OUTS_B20_4", - "GTPE2_LOGIC_OUTS_B15_6", - "GTPE2_LOGIC_OUTS_B13_4", - "GTPE2_BYP2_0", - "GTPE2_IMUX9_7", - "GTPE2_IMUX11_9", - "GTPE2_IMUX2_10", - "GTPE2_IMUX9_4", - "GTPE2_IMUX3_6", - "GTPE2_CHANNEL_RXDATA19", - "GTPE2_LOGIC_OUTS_B23_0", - "GTPE2_CHANNEL_SCANIN1", - "GTPE2_IMUX8_1", - "GTPE2_CHANNEL_TXPIPPMSEL", - "GTPE2_IMUX13_0", - "GTPE2_IMUX30_10", - "GTPE2_BYP4_7", - "GTPE2_LOGIC_OUTS_B23_7", - "GTPE2_CHANNEL_EYESCANRESET", - "GTPE2_IMUX30_9", - "GTPE2_IMUX37_7", - "GTPE2_IMUX25_8", - "GTPE2_FAN4_0", - "GTPE2_IMUX38_7", - "GTPE2_FAN5_4", - "GTPE2_FAN1_2", - "GTPE2_IMUX22_6", - "GTPE2_CHANNEL_TX8B10BBYPASS3", - "GTPE2_IMUX2_7", - "GTPE2_LOGIC_OUTS_B5_5", - "GTPE2_IMUX26_1", - "GTPE2_IMUX42_5", - "GTPE2_CHANNEL_TXMARGIN0", - "GTPE2_CHANNEL_RXDATA12", - "GTPE2_IMUX9_5", - "GTPE2_CHANNEL_TX8B10BBYPASS1", - "GTPE2_LOGIC_OUTS_B11_5", - "GTPE2_CLK0_1", - "GTPE2_IMUX31_8", - "GTPE2_LOGIC_OUTS_B18_9", - "GTPE2_FAN0_4", - "GTPE2_IMUX9_8", - "GTPE2_CHANNEL_DRPDI3", - "GTPE2_LOGIC_OUTS_B8_5", - "GTPE2_LOGIC_OUTS_B16_10", - "GTPE2_BYP1_6", - "GTPE2_IMUX47_0", - "GTPE2_CHANNEL_RXNOTINTABLE3", - "GTPE2_IMUX42_10", - "GTPE2_IMUX8_4", - "GTPE2_CHANNEL_RXDATA10", - "GTPE2_CHANNEL_RXRATE1", - "GTPE2_IMUX47_10", - "GTPE2_CHANNEL_TXSEQUENCE3", - "GTPE2_IMUX38_3", - "GTPE2_IMUX43_4", - "GTPE2_CHANNEL_TXRUNDISP1", - "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "GTPE2_BYP3_4", - "GTPE2_FAN4_5", - "GTPE2_BYP0_5", - "GTPE2_IMUX32_2", - "GTPE2_FAN4_7", - "GTPE2_IMUX3_4", - "GTPE2_CHANNEL_TXDATA9", - "GTPE2_FAN2_3", - "GTPE2_CHANNEL_PLLREFCLK1", - "GTPE2_LOGIC_OUTS_B0_6", - "GTPE2_LOGIC_OUTS_B23_1", - "GTPE2_IMUX45_4", - "GTPE2_CHANNEL_RXADAPTSELTEST0", - "GTPE2_LOGIC_OUTS_B15_1", - "GTPE2_BYP1_10", - "GTPE2_LOGIC_OUTS_B0_7", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", - "GTPE2_IMUX27_10", - "GTPE2_IMUX32_7", - "GTPE2_BYP3_9", - "GTPE2_CHANNEL_PMASCANCLK2", - "GTPE2_LOGIC_OUTS_B21_0", - "GTPE2_IMUX20_10", - "GTPE2_CHANNEL_RXPHMONITOR1", - "GTPE2_IMUX15_6", - "GTPE2_IMUX1_8", - "GTPE2_IMUX33_9", - "GTPE2_IMUX12_8", - "GTPE2_IMUX28_0", - "GTPE2_CHANNEL_RXDATA31", - "GTPE2_IMUX31_4", - "GTPE2_CTRL1_8", - "GTPE2_LOGIC_OUTS_B14_0", - "GTPE2_CHANNEL_RXDLYTESTENB", - "GTPE2_CHANNEL_TXP", - "GTPE2_IMUX33_10", - "GTPE2_IMUX9_10", - "GTPE2_IMUX34_1", - "GTPE2_LOGIC_OUTS_B18_5", - "GTPE2_FAN3_4", - "GTPE2_BYP5_5", - "GTPE2_CHANNEL_RXP", - "GTPE2_LOGIC_OUTS_B6_7", - "GTPE2_FAN3_1", - "GTPE2_IMUX8_10", - "GTPE2_IMUX26_9", - "GTPE2_FAN7_5", - "GTPE2_IMUX1_10", - "GTPE2_IMUX1_3", - "GTPE2_CHANNEL_RXDATA13", - "GTPE2_CHANNEL_TXSWING", - "GTPE2_CHANNEL_PLLCLK0", - "GTPE2_CHANNEL_PCSRSVDOUT11", - "GTPE2_FAN2_7", - "GTPE2_IMUX21_2", - "GTPE2_CHANNEL_RXCLKCORCNT1", - "GTPE2_CHANNEL_TXDIFFCTRL1", - "GTPE2_IMUX21_4", - "GTPE2_LOGIC_OUTS_B22_9", - "GTPE2_IMUX39_2", - "GTPE2_IMUX19_9", - "GTPE2_IMUX40_0", - "GTPE2_CHANNEL_TSTPD0", - "GTPE2_CHANNEL_TXCHARISK2", - "GTPE2_CHANNEL_RXSTATUS0", - "GTPE2_IMUX19_5", - "GTPE2_IMUX11_2", - "GTPE2_CHANNEL_PMASCANOUT2", - "GTPE2_LOGIC_OUTS_B11_10", - "GTPE2_IMUX38_1", - "GTPE2_CHANNEL_RXCOMWAKEDET", - "GTPE2_CHANNEL_TSTIN13", - "GTPE2_IMUX1_6", - "GTPE2_CHANNEL_RXCDROVRDEN", - "GTPE2_LOGIC_OUTS_B8_2", - "GTPE2_LOGIC_OUTS_B20_8", - "GTPE2_CHANNEL_DMONITOROUT5", - "GTPE2_IMUX35_9", - "GTPE2_IMUX27_0", - "GTPE2_LOGIC_OUTS_B7_4", - "GTPE2_IMUX30_0", - "GTPE2_IMUX23_3", - "GTPE2_CHANNEL_RXN", - "GTPE2_IMUX42_6", - "GTPE2_IMUX14_3", - "GTPE2_IMUX16_3", - "GTPE2_LOGIC_OUTS_B5_10", - "GTPE2_BYP4_10", - "GTPE2_CHANNEL_TXPOSTCURSORINV", - "GTPE2_CHANNEL_DRPDO12", - "GTPE2_IMUX35_5", - "GTPE2_IMUX21_10", - "GTPE2_BYP4_6", - "GTPE2_CHANNEL_RXADAPTSELTEST5", - "GTPE2_IMUX23_4", - "GTPE2_LOGIC_OUTS_B16_7", - "GTPE2_BYP2_4", - "GTPE2_IMUX27_3", - "GTPE2_CLK1_0", - "GTPE2_IMUX13_3", - "GTPE2_IMUX43_2", - "GTPE2_FAN2_0", - "GTPE2_CTRL0_4", - "GTPE2_IMUX21_0", - "GTPE2_LOGIC_OUTS_B12_5", - "GTPE2_CHANNEL_GTRSVD0", - "GTPE2_IMUX47_3", - "GTPE2_IMUX4_5", - "GTPE2_CHANNEL_TXPCSRESET", - "GTPE2_IMUX47_2", - "GTPE2_CLK0_2", - "GTPE2_CHANNEL_RXBUFSTATUS1", - "GTPE2_CTRL0_3", - "GTPE2_IMUX47_7", - "GTPE2_IMUX39_4", - "GTPE2_IMUX42_7", - "GTPE2_IMUX17_3", - "GTPE2_LOGIC_OUTS_B7_7", - "GTPE2_IMUX10_9", - "GTPE2_CHANNEL_TXSTARTSEQ", - "GTPE2_CHANNEL_TXSEQUENCE2", - "GTPE2_CHANNEL_GTTXRESET", - "GTPE2_IMUX21_8", - "GTPE2_CHANNEL_TXRUNDISP3", - "GTPE2_FAN4_6", - "GTPE2_CHANNEL_TXDATA28", - "GTPE2_CHANNEL_TSTIN9", - "GTPE2_CHANNEL_RXUSRCLK2", - "GTPE2_CHANNEL_RXCHARISCOMMA3", - "GTPE2_IMUX8_9", - "GTPE2_CHANNEL_RXPD1", - "GTPE2_LOGIC_OUTS_B7_3", - "GTPE2_CHANNEL_TXCOMINIT", - "GTPE2_LOGIC_OUTS_B15_9", - "GTPE2_FAN0_8", - "GTPE2_BYP3_0", - "GTPE2_IMUX6_9", - "GTPE2_CHANNEL_DRPDO13", - "GTPE2_CTRL1_9", - "GTPE2_LOGIC_OUTS_B22_7", - "GTPE2_IMUX40_3", - "GTPE2_LOGIC_OUTS_B20_2", - "GTPE2_FAN4_3", - "GTPE2_IMUX1_0", - "GTPE2_LOGIC_OUTS_B19_8", - "GTPE2_LOGIC_OUTS_B3_3", - "GTPE2_IMUX34_7", - "GTPE2_IMUX0_10", - "GTPE2_CHANNEL_TXRUNDISP2", - "GTPE2_IMUX19_7", - "GTPE2_LOGIC_OUTS_B19_7", - "GTPE2_CHANNEL_RXBUFRESET", - "GTPE2_CHANNEL_RXSYNCOUT", - "GTPE2_IMUX12_9", - "GTPE2_IMUX15_9", - "GTPE2_LOGIC_OUTS_B6_6", - "GTPE2_CTRL1_4", - "GTPE2_CTRL0_9", - "GTPE2_IMUX33_0", - "GTPE2_IMUX11_3", - "GTPE2_FAN0_1", - "GTPE2_IMUX32_5", - "GTPE2_IMUX42_3", - "GTPE2_LOGIC_OUTS_B14_8", - "GTPE2_CHANNEL_TXCHARDISPMODE2", - "GTPE2_IMUX7_6", - "GTPE2_FAN4_1", - "GTPE2_CHANNEL_RXN_PAD", - "GTPE2_CHANNEL_DRPADDR3", - "GTPE2_IMUX23_6", - "GTPE2_BYP7_3", - "GTPE2_BYP5_1", - "GTPE2_CHANNEL_TXPHDLYPD", - "GTPE2_IMUX41_9", - "GTPE2_BYP4_2", - "GTPE2_IMUX22_1", - "GTPE2_LOGIC_OUTS_B3_2", - "GTPE2_CHANNEL_DMONITOROUT8", - "GTPE2_CHANNEL_DRPRDY", - "GTPE2_IMUX45_7", - "GTPE2_BYP7_0", - "GTPE2_IMUX3_2", - "GTPE2_IMUX18_3", - "GTPE2_IMUX4_9", - "GTPE2_IMUX19_10", - "GTPE2_IMUX3_9", - "GTPE2_CHANNEL_RXDATA22", - "GTPE2_FAN4_2", - "GTPE2_IMUX17_5", - "GTPE2_CHANNEL_GTRSVD7", - "GTPE2_IMUX25_2", - "GTPE2_LOGIC_OUTS_B4_3", - "GTPE2_LOGIC_OUTS_B5_3", - "GTPE2_CHANNEL_CFGRESET", - "GTPE2_IMUX27_6", - "GTPE2_IMUX24_9", - "GTPE2_IMUX23_10", - "GTPE2_CHANNEL_TXPRECURSOR3", - "GTPE2_CHANNEL_PMASCANCLK3", - "GTPE2_BYP1_7", - "GTPE2_FAN1_5", - "GTPE2_LOGIC_OUTS_B0_3", - "GTPE2_LOGIC_OUTS_B18_10", - "GTPE2_CHANNEL_TXSYNCOUT", - "GTPE2_IMUX28_5", - "GTPE2_IMUX16_0", - "GTPE2_BYP2_10", - "GTPE2_IMUX36_8", - "GTPE2_CLK1_1", - "GTPE2_CHANNEL_TXDATA24", - "GTPE2_IMUX32_10", - "GTPE2_LOGIC_OUTS_B12_10", - "GTPE2_LOGIC_OUTS_B23_9", - "GTPE2_IMUX24_7", - "GTPE2_LOGIC_OUTS_B21_9", - "GTPE2_IMUX37_3", - "GTPE2_CHANNEL_RXCHBONDI3", - "GTPE2_LOGIC_OUTS_B6_8", - "GTPE2_LOGIC_OUTS_B16_3", - "GTPE2_FAN5_7", - "GTPE2_BYP0_2", - "GTPE2_CHANNEL_RXCHBONDEN", - "GTPE2_IMUX9_9", - "GTPE2_CHANNEL_TSTIN5", - "GTPE2_CHANNEL_PCSRSVDIN1", - "GTPE2_CHANNEL_RXSLIDE", - "GTPE2_IMUX25_0", - "GTPE2_CHANNEL_RXDATA2", - "GTPE2_IMUX5_10", - "GTPE2_CHANNEL_PLL1REFCLK", - "GTPE2_IMUX6_7", - "GTPE2_LOGIC_OUTS_B18_4", - "GTPE2_CHANNEL_RXRESETDONE", - "GTPE2_CHANNEL_GTRSVD2", - "GTPE2_CHANNEL_TXPOSTCURSOR1", - "GTPE2_CHANNEL_RXDFEXYDEN", - "GTPE2_IMUX44_1", - "GTPE2_LOGIC_OUTS_B19_1", - "GTPE2_IMUX28_3", - "GTPE2_IMUX9_3", - "GTPE2_BYP2_3", - "GTPE2_LOGIC_OUTS_B1_10", - "GTPE2_CHANNEL_GTRSVD14", - "GTPE2_CHANNEL_TXPRECURSOR1", - "GTPE2_CHANNEL_RXCLKCORCNT0", - "GTPE2_CTRL0_5", - "GTPE2_CHANNEL_PCSRSVDOUT2", - "GTPE2_FAN7_9", - "GTPE2_LOGIC_OUTS_B12_3", - "GTPE2_IMUX20_8", - "GTPE2_CHANNEL_GTRSVD12", - "GTPE2_IMUX35_3", - "GTPE2_CTRL1_5", - "GTPE2_CHANNEL_EYESCANTRIGGER", - "GTPE2_CHANNEL_TXDATA30", - "GTPE2_IMUX26_3", - "GTPE2_FAN0_0", - "GTPE2_CHANNEL_RXCDRRESET" - ], - "sites": [ - { - "prefix": "GTPE2_CHANNEL", - "y_coord": 0, - "type": "GTPE2_CHANNEL", - "site_pins": { - "RXCHARISCOMMA3": "GTPE2_CHANNEL_RXCHARISCOMMA3", - "RXSTATUS0": "GTPE2_CHANNEL_RXSTATUS0", - "DRPDO13": "GTPE2_CHANNEL_DRPDO13", - "TSTPD0": "GTPE2_CHANNEL_TSTPD0", - "RXBUFRESET": "GTPE2_CHANNEL_RXBUFRESET", - "RXVALID": "GTPE2_CHANNEL_RXVALID", - "SCANIN1": "GTPE2_CHANNEL_SCANIN1", - "RXCHBONDLEVEL2": "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "TXDATA25": "GTPE2_CHANNEL_TXDATA25", - "GTPRXN": "GTPE2_CHANNEL_RXN", - "PCSRSVDOUT6": "GTPE2_CHANNEL_PCSRSVDOUT6", - "TXDATA31": "GTPE2_CHANNEL_TXDATA31", - "CFGRESET": "GTPE2_CHANNEL_CFGRESET", - "GTPTXP": "GTPE2_CHANNEL_TXP", - "TXPIPPMEN": "GTPE2_CHANNEL_TXPIPPMEN", - "TXDATA14": "GTPE2_CHANNEL_TXDATA14", - "TXRATE0": "GTPE2_CHANNEL_TXRATE0", - "DMONITOROUT6": "GTPE2_CHANNEL_DMONITOROUT6", - "PMASCANOUT5": "GTPE2_CHANNEL_PMASCANOUT5", - "RXDATA28": "GTPE2_CHANNEL_RXDATA28", - "TXOUTCLK": "GTPE2_CHANNEL_GTTXOUTCLK_2", - "RXCHANBONDSEQ": "GTPE2_CHANNEL_RXCHANBONDSEQ", - "DRPDI4": "GTPE2_CHANNEL_DRPDI4", - "TXDATA15": "GTPE2_CHANNEL_TXDATA15", - "RXDATA26": "GTPE2_CHANNEL_RXDATA26", - "TXHEADER1": "GTPE2_CHANNEL_TXHEADER1", - "RXCHBONDLEVEL1": "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "RXNOTINTABLE1": "GTPE2_CHANNEL_RXNOTINTABLE1", - "RXPD0": "GTPE2_CHANNEL_RXPD0", - "DMONITOROUT14": "GTPE2_CHANNEL_DMONITOROUT14", - "TXBUFSTATUS1": "GTPE2_CHANNEL_TXBUFSTATUS1", - "TXCOMSAS": "GTPE2_CHANNEL_TXCOMSAS", - "RXCDRRESETRSV": "GTPE2_CHANNEL_RXCDRRESETRSV", - "RXSTATUS2": "GTPE2_CHANNEL_RXSTATUS2", - "RXOSINTCFG2": "GTPE2_CHANNEL_RXOSINTCFG2", - "PCSRSVDIN11": "GTPE2_CHANNEL_PCSRSVDIN11", - "PHYSTATUS": "GTPE2_CHANNEL_PHYSTATUS", - "RXGEARBOXSLIP": "GTPE2_CHANNEL_RXGEARBOXSLIP", - "DMONITOROUT3": "GTPE2_CHANNEL_DMONITOROUT3", - "TXMAINCURSOR1": "GTPE2_CHANNEL_TXMAINCURSOR1", - "GTRSVD11": "GTPE2_CHANNEL_GTRSVD11", - "DMONITOROUT7": "GTPE2_CHANNEL_DMONITOROUT7", - "TXSYNCDONE": "GTPE2_CHANNEL_TXSYNCDONE", - "PCSRSVDIN6": "GTPE2_CHANNEL_PCSRSVDIN6", - "RXBYTEISALIGNED": "GTPE2_CHANNEL_RXBYTEISALIGNED", - "PCSRSVDIN4": "GTPE2_CHANNEL_PCSRSVDIN4", - "RXOSINTCFG3": "GTPE2_CHANNEL_RXOSINTCFG3", - "TXCHARDISPVAL3": "GTPE2_CHANNEL_TXCHARDISPVAL3", - "TXCHARDISPMODE3": "GTPE2_CHANNEL_TXCHARDISPMODE3", - "RXDATA29": "GTPE2_CHANNEL_RXDATA29", - "TXOUTCLKPCS": "GTPE2_CHANNEL_TXOUTCLKPCS", - "RXCLKCORCNT1": "GTPE2_CHANNEL_RXCLKCORCNT1", - "RXADAPTSELTEST2": "GTPE2_CHANNEL_RXADAPTSELTEST2", - "TXINHIBIT": "GTPE2_CHANNEL_TXINHIBIT", - "TXDATA13": "GTPE2_CHANNEL_TXDATA13", - "TXPISOPD": "GTPE2_CHANNEL_TXPISOPD", - "RXPMARESET": "GTPE2_CHANNEL_RXPMARESET", - "TSTIN14": "GTPE2_CHANNEL_TSTIN14", - "PCSRSVDIN13": "GTPE2_CHANNEL_PCSRSVDIN13", - "PMASCANCLK3": "GTPE2_CHANNEL_PMASCANCLK3", - "TXDATA8": "GTPE2_CHANNEL_TXDATA8", - "PCSRSVDIN1": "GTPE2_CHANNEL_PCSRSVDIN1", - "DRPDI12": "GTPE2_CHANNEL_DRPDI12", - "RXOSINTID02": "GTPE2_CHANNEL_RXOSINTID02", - "PMARSVDOUT1": "GTPE2_CHANNEL_PMARSVDOUT1", - "RXCDRHOLD": "GTPE2_CHANNEL_RXCDRHOLD", - "TXDATA10": "GTPE2_CHANNEL_TXDATA10", - "DRPDI6": "GTPE2_CHANNEL_DRPDI6", - "TSTIN2": "GTPE2_CHANNEL_TSTIN2", - "DRPWE": "GTPE2_CHANNEL_DRPWE", - "RXOUTCLKSEL2": "GTPE2_CHANNEL_RXOUTCLKSEL2", - "DRPADDR5": "GTPE2_CHANNEL_DRPADDR5", - "TSTIN15": "GTPE2_CHANNEL_TSTIN15", - "RXPHSLIPMONITOR0": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "RXPHDLYRESET": "GTPE2_CHANNEL_RXPHDLYRESET", - "RXPHSLIPMONITOR1": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "TXPRBSFORCEERR": "GTPE2_CHANNEL_TXPRBSFORCEERR", - "TXHEADER2": "GTPE2_CHANNEL_TXHEADER2", - "PCSRSVDOUT0": "GTPE2_CHANNEL_PCSRSVDOUT0", - "TXPD0": "GTPE2_CHANNEL_TXPD0", - "RXDATA4": "GTPE2_CHANNEL_RXDATA4", - "RXHEADER1": "GTPE2_CHANNEL_RXHEADER1", - "RXOSINTID00": "GTPE2_CHANNEL_RXOSINTID00", - "RXSTARTOFSEQ1": "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "RXOSOVRDEN": "GTPE2_CHANNEL_RXOSOVRDEN", - "RXADAPTSELTEST11": "GTPE2_CHANNEL_RXADAPTSELTEST11", - "PCSRSVDOUT1": "GTPE2_CHANNEL_PCSRSVDOUT1", - "TXPIPPMPD": "GTPE2_CHANNEL_TXPIPPMPD", - "TXDLYOVRDEN": "GTPE2_CHANNEL_TXDLYOVRDEN", - "RXDATA21": "GTPE2_CHANNEL_RXDATA21", - "RXCHBONDO1": "GTPE2_CHANNEL_RXCHBONDO1", - "TXOUTCLKSEL0": "GTPE2_CHANNEL_TXOUTCLKSEL0", - "TXDEEMPH": "GTPE2_CHANNEL_TXDEEMPH", - "TXDATA5": "GTPE2_CHANNEL_TXDATA5", - "GTRSVD1": "GTPE2_CHANNEL_GTRSVD1", - "TSTPD3": "GTPE2_CHANNEL_TSTPD3", - "TXMAINCURSOR6": "GTPE2_CHANNEL_TXMAINCURSOR6", - "TSTIN5": "GTPE2_CHANNEL_TSTIN5", - "TXPRECURSOR2": "GTPE2_CHANNEL_TXPRECURSOR2", - "TXRATEMODE": "GTPE2_CHANNEL_TXRATEMODE", - "RXLPMLFOVRDEN": "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "RXOUTCLKSEL0": "GTPE2_CHANNEL_RXOUTCLKSEL0", - "TXUSRCLK2": "GTPE2_CHANNEL_TXUSRCLK2", - "RXPHDLYPD": "GTPE2_CHANNEL_RXPHDLYPD", - "RXOSINTID03": "GTPE2_CHANNEL_RXOSINTID03", - "RXDATA3": "GTPE2_CHANNEL_RXDATA3", - "DRPDO6": "GTPE2_CHANNEL_DRPDO6", - "TXPOSTCURSORINV": "GTPE2_CHANNEL_TXPOSTCURSORINV", - "TXMAINCURSOR2": "GTPE2_CHANNEL_TXMAINCURSOR2", - "TSTPD1": "GTPE2_CHANNEL_TSTPD1", - "RXPHMONITOR0": "GTPE2_CHANNEL_RXPHMONITOR0", - "TSTIN18": "GTPE2_CHANNEL_TSTIN18", - "DRPDO4": "GTPE2_CHANNEL_DRPDO4", - "RXOSCALRESET": "GTPE2_CHANNEL_RXOSCALRESET", - "RXCHARISCOMMA1": "GTPE2_CHANNEL_RXCHARISCOMMA1", - "RXADAPTSELTEST4": "GTPE2_CHANNEL_RXADAPTSELTEST4", - "RXMCOMMAALIGNEN": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "TXPHDLYPD": "GTPE2_CHANNEL_TXPHDLYPD", - "TXPOSTCURSOR2": "GTPE2_CHANNEL_TXPOSTCURSOR2", - "PMASCANCLK0": "GTPE2_CHANNEL_PMASCANCLK0", - "PCSRSVDOUT15": "GTPE2_CHANNEL_PCSRSVDOUT15", - "SCANIN3": "GTPE2_CHANNEL_SCANIN3", - "TXELECIDLE": "GTPE2_CHANNEL_TXELECIDLE", - "RXDATA27": "GTPE2_CHANNEL_RXDATA27", - "TXRATE2": "GTPE2_CHANNEL_TXRATE2", - "EYESCANRESET": "GTPE2_CHANNEL_EYESCANRESET", - "DRPDI13": "GTPE2_CHANNEL_DRPDI13", - "PMASCANCLK1": "GTPE2_CHANNEL_PMASCANCLK1", - "RXCHBONDLEVEL0": "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "RXPHMONITOR3": "GTPE2_CHANNEL_RXPHMONITOR3", - "TXSTARTSEQ": "GTPE2_CHANNEL_TXSTARTSEQ", - "RXRATE1": "GTPE2_CHANNEL_RXRATE1", - "DRPDO0": "GTPE2_CHANNEL_DRPDO0", - "TXBUFDIFFCTRL0": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "RXDATA18": "GTPE2_CHANNEL_RXDATA18", - "DRPDO1": "GTPE2_CHANNEL_DRPDO1", - "RXADAPTSELTEST10": "GTPE2_CHANNEL_RXADAPTSELTEST10", - "RXDLYBYPASS": "GTPE2_CHANNEL_RXDLYBYPASS", - "TXDIFFCTRL0": "GTPE2_CHANNEL_TXDIFFCTRL0", - "RXPRBSCNTRESET": "GTPE2_CHANNEL_RXPRBSCNTRESET", - "RXCLKCORCNT0": "GTPE2_CHANNEL_RXCLKCORCNT0", - "TSTCLK1": "GTPE2_CHANNEL_TSTCLK1", - "PLL1CLK": "GTPE2_CHANNEL_PLL1CLK", - "DMONITORCLK": "GTPE2_CHANNEL_DMONITORCLK", - "PLL0REFCLK": "GTPE2_CHANNEL_PLL0REFCLK", - "SCANMODEB": "GTPE2_CHANNEL_SCANMODEB", - "TSTIN12": "GTPE2_CHANNEL_TSTIN12", - "TSTIN7": "GTPE2_CHANNEL_TSTIN7", - "TXDATA19": "GTPE2_CHANNEL_TXDATA19", - "RXPCSRESET": "GTPE2_CHANNEL_RXPCSRESET", - "TXPRBSSEL2": "GTPE2_CHANNEL_TXPRBSSEL2", - "RXPHOVRDEN": "GTPE2_CHANNEL_RXPHOVRDEN", - "TSTIN11": "GTPE2_CHANNEL_TSTIN11", - "RXDATA6": "GTPE2_CHANNEL_RXDATA6", - "SETERRSTATUS": "GTPE2_CHANNEL_SETERRSTATUS", - "RXOSINTID01": "GTPE2_CHANNEL_RXOSINTID01", - "TXHEADER0": "GTPE2_CHANNEL_TXHEADER0", - "DRPDI8": "GTPE2_CHANNEL_DRPDI8", - "TXDIFFCTRL3": "GTPE2_CHANNEL_TXDIFFCTRL3", - "TXDATA18": "GTPE2_CHANNEL_TXDATA18", - "DMONITOROUT5": "GTPE2_CHANNEL_DMONITOROUT5", - "RXDATA1": "GTPE2_CHANNEL_RXDATA1", - "RX8B10BEN": "GTPE2_CHANNEL_RX8B10BEN", - "TXCHARDISPVAL1": "GTPE2_CHANNEL_TXCHARDISPVAL1", - "TXRATE1": "GTPE2_CHANNEL_TXRATE1", - "TXDATA21": "GTPE2_CHANNEL_TXDATA21", - "PMASCANOUT2": "GTPE2_CHANNEL_PMASCANOUT2", - "PCSRSVDIN10": "GTPE2_CHANNEL_PCSRSVDIN10", - "GTRSVD2": "GTPE2_CHANNEL_GTRSVD2", - "RXADAPTSELTEST5": "GTPE2_CHANNEL_RXADAPTSELTEST5", - "LOOPBACK0": "GTPE2_CHANNEL_LOOPBACK0", - "DRPADDR4": "GTPE2_CHANNEL_DRPADDR4", - "TXCHARDISPVAL0": "GTPE2_CHANNEL_TXCHARDISPVAL0", - "PMASCANIN4": "GTPE2_CHANNEL_PMASCANIN4", - "DRPADDR8": "GTPE2_CHANNEL_DRPADDR8", - "RXSYSCLKSEL1": "GTPE2_CHANNEL_RXSYSCLKSEL1", - "RXADAPTSELTEST8": "GTPE2_CHANNEL_RXADAPTSELTEST8", - "TXSYNCOUT": "GTPE2_CHANNEL_TXSYNCOUT", - "RXCHBONDMASTER": "GTPE2_CHANNEL_RXCHBONDMASTER", - "TXPRECURSORINV": "GTPE2_CHANNEL_TXPRECURSORINV", - "PCSRSVDOUT2": "GTPE2_CHANNEL_PCSRSVDOUT2", - "TXPOLARITY": "GTPE2_CHANNEL_TXPOLARITY", - "RXADAPTSELTEST9": "GTPE2_CHANNEL_RXADAPTSELTEST9", - "DMONITOROUT0": "GTPE2_CHANNEL_DMONITOROUT0", - "TXUSERRDY": "GTPE2_CHANNEL_TXUSERRDY", - "DMONITOROUT4": "GTPE2_CHANNEL_DMONITOROUT4", - "TXDLYEN": "GTPE2_CHANNEL_TXDLYEN", - "TSTIN10": "GTPE2_CHANNEL_TSTIN10", - "RXPHSLIPMONITOR4": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "RXCHBONDI3": "GTPE2_CHANNEL_RXCHBONDI3", - "TXPIPPMSTEPSIZE2": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "RXDDIEN": "GTPE2_CHANNEL_RXDDIEN", - "RXPRBSSEL1": "GTPE2_CHANNEL_RXPRBSSEL1", - "PCSRSVDIN5": "GTPE2_CHANNEL_PCSRSVDIN5", - "TXPMARESETDONE": "GTPE2_CHANNEL_TXPMARESETDONE", - "TXRUNDISP3": "GTPE2_CHANNEL_TXRUNDISP3", - "RXUSRCLK": "GTPE2_CHANNEL_RXUSRCLK", - "TXSEQUENCE4": "GTPE2_CHANNEL_TXSEQUENCE4", - "RXELECIDLEMODE1": "GTPE2_CHANNEL_RXELECIDLEMODE1", - "DRPDO9": "GTPE2_CHANNEL_DRPDO9", - "RXCOMMADETEN": "GTPE2_CHANNEL_RXCOMMADETEN", - "GTRESETSEL": "GTPE2_CHANNEL_GTRESETSEL", - "SCANCLK": "GTPE2_CHANNEL_SCANCLK", - "TXDLYHOLD": "GTPE2_CHANNEL_TXDLYHOLD", - "PMASCANIN0": "GTPE2_CHANNEL_PMASCANIN0", - "TXPRBSSEL1": "GTPE2_CHANNEL_TXPRBSSEL1", - "LOOPBACK2": "GTPE2_CHANNEL_LOOPBACK2", - "RXDATA2": "GTPE2_CHANNEL_RXDATA2", - "PCSRSVDOUT9": "GTPE2_CHANNEL_PCSRSVDOUT9", - "TXDATA7": "GTPE2_CHANNEL_TXDATA7", - "RXOSINTSTROBESTARTED": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "RXADAPTSELTEST13": "GTPE2_CHANNEL_RXADAPTSELTEST13", - "TXOUTCLKFABRIC": "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "TXBUFDIFFCTRL2": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "PCSRSVDOUT4": "GTPE2_CHANNEL_PCSRSVDOUT4", - "TXRUNDISP1": "GTPE2_CHANNEL_TXRUNDISP1", - "RXCHBONDO2": "GTPE2_CHANNEL_RXCHBONDO2", - "TXSEQUENCE5": "GTPE2_CHANNEL_TXSEQUENCE5", - "DRPADDR6": "GTPE2_CHANNEL_DRPADDR6", - "DRPADDR3": "GTPE2_CHANNEL_DRPADDR3", - "RXSTARTOFSEQ0": "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "TXUSRCLK": "GTPE2_CHANNEL_TXUSRCLK", - "TXDATA29": "GTPE2_CHANNEL_TXDATA29", - "RXPHALIGNDONE": "GTPE2_CHANNEL_RXPHALIGNDONE", - "TSTIN4": "GTPE2_CHANNEL_TSTIN4", - "GTRSVD5": "GTPE2_CHANNEL_GTRSVD5", - "PCSRSVDOUT7": "GTPE2_CHANNEL_PCSRSVDOUT7", - "RXADAPTSELTEST3": "GTPE2_CHANNEL_RXADAPTSELTEST3", - "PCSRSVDIN8": "GTPE2_CHANNEL_PCSRSVDIN8", - "TXPD1": "GTPE2_CHANNEL_TXPD1", - "GTRSVD9": "GTPE2_CHANNEL_GTRSVD9", - "RXDATA15": "GTPE2_CHANNEL_RXDATA15", - "RXCHARISK3": "GTPE2_CHANNEL_RXCHARISK3", - "TXPRECURSOR3": "GTPE2_CHANNEL_TXPRECURSOR3", - "RXPHMONITOR1": "GTPE2_CHANNEL_RXPHMONITOR1", - "RXRATE0": "GTPE2_CHANNEL_RXRATE0", - "RXOUTCLK": "GTPE2_CHANNEL_GTRXOUTCLK_2", - "RXOSINTDONE": "GTPE2_CHANNEL_RXOSINTDONE", - "RXDATAVALID1": "GTPE2_CHANNEL_RXDATAVALID1", - "RXNOTINTABLE0": "GTPE2_CHANNEL_RXNOTINTABLE0", - "RESETOVRD": "GTPE2_CHANNEL_RESETOVRD", - "TXDATA26": "GTPE2_CHANNEL_TXDATA26", - "RXDATAVALID0": "GTPE2_CHANNEL_RXDATAVALID0", - "PMASCANOUT3": "GTPE2_CHANNEL_PMASCANOUT3", - "TSTPD4": "GTPE2_CHANNEL_TSTPD4", - "PCSRSVDOUT13": "GTPE2_CHANNEL_PCSRSVDOUT13", - "GTRSVD13": "GTPE2_CHANNEL_GTRSVD13", - "TXDATA20": "GTPE2_CHANNEL_TXDATA20", - "TXDIFFPD": "GTPE2_CHANNEL_TXDIFFPD", - "RXSTATUS1": "GTPE2_CHANNEL_RXSTATUS1", - "RXCHARISK0": "GTPE2_CHANNEL_RXCHARISK0", - "TXBUFSTATUS0": "GTPE2_CHANNEL_TXBUFSTATUS0", - "TSTCLK0": "GTPE2_CHANNEL_TSTCLK0", - "DMONITOROUT8": "GTPE2_CHANNEL_DMONITOROUT8", - "SCANOUT4": "GTPE2_CHANNEL_SCANOUT4", - "RXELECIDLE": "GTPE2_CHANNEL_RXELECIDLE", - "PMASCANCLK2": "GTPE2_CHANNEL_PMASCANCLK2", - "RXDATA16": "GTPE2_CHANNEL_RXDATA16", - "RXCHBONDI1": "GTPE2_CHANNEL_RXCHBONDI1", - "RXCHANREALIGN": "GTPE2_CHANNEL_RXCHANREALIGN", - "RXDISPERR3": "GTPE2_CHANNEL_RXDISPERR3", - "PMASCANENB": "GTPE2_CHANNEL_PMASCANENB", - "TXDATA22": "GTPE2_CHANNEL_TXDATA22", - "PMASCANOUT0": "GTPE2_CHANNEL_PMASCANOUT0", - "TXPIPPMOVRDEN": "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "RXOSINTNTRLEN": "GTPE2_CHANNEL_RXOSINTNTRLEN", - "TXDATA17": "GTPE2_CHANNEL_TXDATA17", - "RXCOMMADET": "GTPE2_CHANNEL_RXCOMMADET", - "TXOUTCLKSEL2": "GTPE2_CHANNEL_TXOUTCLKSEL2", - "TXDLYSRESET": "GTPE2_CHANNEL_TXDLYSRESET", - "TXPHALIGNEN": "GTPE2_CHANNEL_TXPHALIGNEN", - "DRPDO2": "GTPE2_CHANNEL_DRPDO2", - "TXRATEDONE": "GTPE2_CHANNEL_TXRATEDONE", - "TXDATA6": "GTPE2_CHANNEL_TXDATA6", - "DRPDI1": "GTPE2_CHANNEL_DRPDI1", - "RXDISPERR0": "GTPE2_CHANNEL_RXDISPERR0", - "RXDATA13": "GTPE2_CHANNEL_RXDATA13", - "PMASCANIN1": "GTPE2_CHANNEL_PMASCANIN1", - "TXDATA3": "GTPE2_CHANNEL_TXDATA3", - "PCSRSVDIN12": "GTPE2_CHANNEL_PCSRSVDIN12", - "TXRUNDISP2": "GTPE2_CHANNEL_TXRUNDISP2", - "RXDEBUGPULSE": "GTPE2_CHANNEL_RXDEBUGPULSE", - "RXDATA20": "GTPE2_CHANNEL_RXDATA20", - "GTRSVD14": "GTPE2_CHANNEL_GTRSVD14", - "RXCHBONDO0": "GTPE2_CHANNEL_RXCHBONDO0", - "TXDATA23": "GTPE2_CHANNEL_TXDATA23", - "TXPDELECIDLEMODE": "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "TXMAINCURSOR3": "GTPE2_CHANNEL_TXMAINCURSOR3", - "RXLPMOSINTNTRLEN": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "RXDLYSRESET": "GTPE2_CHANNEL_RXDLYSRESET", - "GTRSVD15": "GTPE2_CHANNEL_GTRSVD15", - "RXLPMHFHOLD": "GTPE2_CHANNEL_RXLPMHFHOLD", - "RXDLYEN": "GTPE2_CHANNEL_RXDLYEN", - "TXPIPPMSEL": "GTPE2_CHANNEL_TXPIPPMSEL", - "PCSRSVDIN2": "GTPE2_CHANNEL_PCSRSVDIN2", - "GTRSVD7": "GTPE2_CHANNEL_GTRSVD7", - "DRPDI15": "GTPE2_CHANNEL_DRPDI15", - "RXCHBONDEN": "GTPE2_CHANNEL_RXCHBONDEN", - "TXMAINCURSOR5": "GTPE2_CHANNEL_TXMAINCURSOR5", - "TXGEARBOXREADY": "GTPE2_CHANNEL_TXGEARBOXREADY", - "TXSEQUENCE3": "GTPE2_CHANNEL_TXSEQUENCE3", - "DRPDI5": "GTPE2_CHANNEL_DRPDI5", - "TXCHARDISPMODE0": "GTPE2_CHANNEL_TXCHARDISPMODE0", - "TXDATA27": "GTPE2_CHANNEL_TXDATA27", - "RXSYNCALLIN": "GTPE2_CHANNEL_RXSYNCALLIN", - "EYESCANDATAERROR": "GTPE2_CHANNEL_EYESCANDATAERROR", - "SCANIN2": "GTPE2_CHANNEL_SCANIN2", - "GTRSVD10": "GTPE2_CHANNEL_GTRSVD10", - "RXPRBSSEL2": "GTPE2_CHANNEL_RXPRBSSEL2", - "RXCHBONDI0": "GTPE2_CHANNEL_RXCHBONDI0", - "TXBUFDIFFCTRL1": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "RXADAPTSELTEST6": "GTPE2_CHANNEL_RXADAPTSELTEST6", - "DRPDO8": "GTPE2_CHANNEL_DRPDO8", - "TXDLYBYPASS": "GTPE2_CHANNEL_TXDLYBYPASS", - "TX8B10BBYPASS3": "GTPE2_CHANNEL_TX8B10BBYPASS3", - "DMONFIFORESET": "GTPE2_CHANNEL_DMONFIFORESET", - "RXDATA30": "GTPE2_CHANNEL_RXDATA30", - "TXCHARDISPVAL2": "GTPE2_CHANNEL_TXCHARDISPVAL2", - "TSTIN8": "GTPE2_CHANNEL_TSTIN8", - "RXDATA24": "GTPE2_CHANNEL_RXDATA24", - "GTPTXN": "GTPE2_CHANNEL_TXN", - "RXSYNCMODE": "GTPE2_CHANNEL_RXSYNCMODE", - "TXDATA1": "GTPE2_CHANNEL_TXDATA1", - "TXPRECURSOR0": "GTPE2_CHANNEL_TXPRECURSOR0", - "RXSYNCOUT": "GTPE2_CHANNEL_RXSYNCOUT", - "TSTIN19": "GTPE2_CHANNEL_TSTIN19", - "RXRATEMODE": "GTPE2_CHANNEL_RXRATEMODE", - "DRPDI11": "GTPE2_CHANNEL_DRPDI11", - "RXCDRRESET": "GTPE2_CHANNEL_RXCDRRESET", - "RXOSINTCFG0": "GTPE2_CHANNEL_RXOSINTCFG0", - "PMASCANRSTEN": "GTPE2_CHANNEL_PMASCANRSTEN", - "CLKRSVD1": "GTPE2_CHANNEL_CLKRSVD1", - "TX8B10BBYPASS0": "GTPE2_CHANNEL_TX8B10BBYPASS0", - "PCSRSVDOUT14": "GTPE2_CHANNEL_PCSRSVDOUT14", - "RXNOTINTABLE2": "GTPE2_CHANNEL_RXNOTINTABLE2", - "PCSRSVDIN3": "GTPE2_CHANNEL_PCSRSVDIN3", - "RXOSINTPD": "GTPE2_CHANNEL_RXOSINTPD", - "DMONITOROUT12": "GTPE2_CHANNEL_DMONITOROUT12", - "TXPOSTCURSOR3": "GTPE2_CHANNEL_TXPOSTCURSOR3", - "TXPCSRESET": "GTPE2_CHANNEL_TXPCSRESET", - "TXPHDLYRESET": "GTPE2_CHANNEL_TXPHDLYRESET", - "RXOSINTHOLD": "GTPE2_CHANNEL_RXOSINTHOLD", - "TXPRECURSOR4": "GTPE2_CHANNEL_TXPRECURSOR4", - "RXBYTEREALIGN": "GTPE2_CHANNEL_RXBYTEREALIGN", - "TSTPD2": "GTPE2_CHANNEL_TSTPD2", - "TXSEQUENCE6": "GTPE2_CHANNEL_TXSEQUENCE6", - "TXCHARDISPMODE1": "GTPE2_CHANNEL_TXCHARDISPMODE1", - "RXPRBSSEL0": "GTPE2_CHANNEL_RXPRBSSEL0", - "TSTIN6": "GTPE2_CHANNEL_TSTIN6", - "DRPEN": "GTPE2_CHANNEL_DRPEN", - "TSTIN1": "GTPE2_CHANNEL_TSTIN1", - "DRPDO7": "GTPE2_CHANNEL_DRPDO7", - "PCSRSVDIN7": "GTPE2_CHANNEL_PCSRSVDIN7", - "DRPDI3": "GTPE2_CHANNEL_DRPDI3", - "TSTIN3": "GTPE2_CHANNEL_TSTIN3", - "RXDLYSRESETDONE": "GTPE2_CHANNEL_RXDLYSRESETDONE", - "RXCOMINITDET": "GTPE2_CHANNEL_RXCOMINITDET", - "DRPADDR7": "GTPE2_CHANNEL_DRPADDR7", - "RXLPMLFHOLD": "GTPE2_CHANNEL_RXLPMLFHOLD", - "TXPIPPMSTEPSIZE0": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "TXCHARISK2": "GTPE2_CHANNEL_TXCHARISK2", - "RXDATA9": "GTPE2_CHANNEL_RXDATA9", - "RXBUFSTATUS2": "GTPE2_CHANNEL_RXBUFSTATUS2", - "DRPDI0": "GTPE2_CHANNEL_DRPDI0", - "GTRSVD4": "GTPE2_CHANNEL_GTRSVD4", - "RXSYNCIN": "GTPE2_CHANNEL_RXSYNCIN", - "RXLPMHFOVRDEN": "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "SCANOUT0": "GTPE2_CHANNEL_SCANOUT0", - "TXPHALIGNDONE": "GTPE2_CHANNEL_TXPHALIGNDONE", - "TXDATA30": "GTPE2_CHANNEL_TXDATA30", - "RXCHBONDI2": "GTPE2_CHANNEL_RXCHBONDI2", - "TX8B10BEN": "GTPE2_CHANNEL_TX8B10BEN", - "DRPDO11": "GTPE2_CHANNEL_DRPDO11", - "RXCOMWAKEDET": "GTPE2_CHANNEL_RXCOMWAKEDET", - "RXDLYOVRDEN": "GTPE2_CHANNEL_RXDLYOVRDEN", - "PLL0CLK": "GTPE2_CHANNEL_PLL0CLK", - "RXOUTCLKSEL1": "GTPE2_CHANNEL_RXOUTCLKSEL1", - "PMASCANIN2": "GTPE2_CHANNEL_PMASCANIN2", - "TXDIFFCTRL1": "GTPE2_CHANNEL_TXDIFFCTRL1", - "SCANOUT3": "GTPE2_CHANNEL_SCANOUT3", - "RXOUTCLKPCS": "GTPE2_CHANNEL_RXOUTCLKPCS", - "LOOPBACK1": "GTPE2_CHANNEL_LOOPBACK1", - "DRPDO5": "GTPE2_CHANNEL_DRPDO5", - "SCANIN0": "GTPE2_CHANNEL_SCANIN0", - "DRPDO15": "GTPE2_CHANNEL_DRPDO15", - "DRPADDR1": "GTPE2_CHANNEL_DRPADDR1", - "RXOSINTTESTOVRDEN": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "TXPOSTCURSOR4": "GTPE2_CHANNEL_TXPOSTCURSOR4", - "DMONITOROUT9": "GTPE2_CHANNEL_DMONITOROUT9", - "RXDATA23": "GTPE2_CHANNEL_RXDATA23", - "TXDATA24": "GTPE2_CHANNEL_TXDATA24", - "RXDISPERR1": "GTPE2_CHANNEL_RXDISPERR1", - "RXSYNCDONE": "GTPE2_CHANNEL_RXSYNCDONE", - "TX8B10BBYPASS2": "GTPE2_CHANNEL_TX8B10BBYPASS2", - "TXDATA28": "GTPE2_CHANNEL_TXDATA28", - "PLL1REFCLK": "GTPE2_CHANNEL_PLL1REFCLK", - "TXRESETDONE": "GTPE2_CHANNEL_TXRESETDONE", - "TXDIFFCTRL2": "GTPE2_CHANNEL_TXDIFFCTRL2", - "RXOSINTSTROBEDONE": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "DRPDI10": "GTPE2_CHANNEL_DRPDI10", - "SCANOUT1": "GTPE2_CHANNEL_SCANOUT1", - "DRPDI14": "GTPE2_CHANNEL_DRPDI14", - "GTRSVD8": "GTPE2_CHANNEL_GTRSVD8", - "RXHEADER2": "GTPE2_CHANNEL_RXHEADER2", - "TXSYSCLKSEL1": "GTPE2_CHANNEL_TXSYSCLKSEL1", - "RXADAPTSELTEST1": "GTPE2_CHANNEL_RXADAPTSELTEST1", - "TXPHINITDONE": "GTPE2_CHANNEL_TXPHINITDONE", - "RXPOLARITY": "GTPE2_CHANNEL_RXPOLARITY", - "RXPHSLIPMONITOR3": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "RXOUTCLKFABRIC": "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "RXOSHOLD": "GTPE2_CHANNEL_RXOSHOLD", - "TXRUNDISP0": "GTPE2_CHANNEL_TXRUNDISP0", - "DMONITOROUT13": "GTPE2_CHANNEL_DMONITOROUT13", - "TXCHARDISPMODE2": "GTPE2_CHANNEL_TXCHARDISPMODE2", - "TXDATA16": "GTPE2_CHANNEL_TXDATA16", - "RXDFEXYDEN": "GTPE2_CHANNEL_RXDFEXYDEN", - "RXADAPTSELTEST0": "GTPE2_CHANNEL_RXADAPTSELTEST0", - "RXCHANISALIGNED": "GTPE2_CHANNEL_RXCHANISALIGNED", - "PCSRSVDOUT11": "GTPE2_CHANNEL_PCSRSVDOUT11", - "DRPRDY": "GTPE2_CHANNEL_DRPRDY", - "RXDATA25": "GTPE2_CHANNEL_RXDATA25", - "RXCHARISCOMMA2": "GTPE2_CHANNEL_RXCHARISCOMMA2", - "TXPHINIT": "GTPE2_CHANNEL_TXPHINIT", - "TXOUTCLKSEL1": "GTPE2_CHANNEL_TXOUTCLKSEL1", - "TX8B10BBYPASS1": "GTPE2_CHANNEL_TX8B10BBYPASS1", - "RXPHMONITOR2": "GTPE2_CHANNEL_RXPHMONITOR2", - "RXCHARISK1": "GTPE2_CHANNEL_RXCHARISK1", - "RXPHALIGNEN": "GTPE2_CHANNEL_RXPHALIGNEN", - "RXDATA12": "GTPE2_CHANNEL_RXDATA12", - "TSTIN16": "GTPE2_CHANNEL_TSTIN16", - "PCSRSVDOUT10": "GTPE2_CHANNEL_PCSRSVDOUT10", - "RXCDROVRDEN": "GTPE2_CHANNEL_RXCDROVRDEN", - "TXPIPPMSTEPSIZE4": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "RXDLYTESTENB": "GTPE2_CHANNEL_RXDLYTESTENB", - "RXOOBRESET": "GTPE2_CHANNEL_RXOOBRESET", - "PMASCANOUT6": "GTPE2_CHANNEL_PMASCANOUT6", - "TXCHARISK0": "GTPE2_CHANNEL_TXCHARISK0", - "TXDATA12": "GTPE2_CHANNEL_TXDATA12", - "EYESCANMODE": "GTPE2_CHANNEL_EYESCANMODE", - "DRPDI7": "GTPE2_CHANNEL_DRPDI7", - "RXLPMRESET": "GTPE2_CHANNEL_RXLPMRESET", - "RXDATA11": "GTPE2_CHANNEL_RXDATA11", - "TXPRECURSOR1": "GTPE2_CHANNEL_TXPRECURSOR1", - "TXCOMWAKE": "GTPE2_CHANNEL_TXCOMWAKE", - "TXCHARISK3": "GTPE2_CHANNEL_TXCHARISK3", - "TXSWING": "GTPE2_CHANNEL_TXSWING", - "SCANIN5": "GTPE2_CHANNEL_SCANIN5", - "SCANIN4": "GTPE2_CHANNEL_SCANIN4", - "TXPHALIGN": "GTPE2_CHANNEL_TXPHALIGN", - "TXMAINCURSOR4": "GTPE2_CHANNEL_TXMAINCURSOR4", - "DRPDO14": "GTPE2_CHANNEL_DRPDO14", - "DMONITOROUT2": "GTPE2_CHANNEL_DMONITOROUT2", - "RXCDRFREQRESET": "GTPE2_CHANNEL_RXCDRFREQRESET", - "GTRXRESET": "GTPE2_CHANNEL_GTRXRESET", - "TXSYNCMODE": "GTPE2_CHANNEL_TXSYNCMODE", - "TSTPDOVRDB": "GTPE2_CHANNEL_TSTPDOVRDB", - "RXCOMSASDET": "GTPE2_CHANNEL_RXCOMSASDET", - "PCSRSVDOUT3": "GTPE2_CHANNEL_PCSRSVDOUT3", - "RXOSINTSTROBE": "GTPE2_CHANNEL_RXOSINTSTROBE", - "PCSRSVDIN15": "GTPE2_CHANNEL_PCSRSVDIN15", - "PMASCANIN6": "GTPE2_CHANNEL_PMASCANIN6", - "TXCHARISK1": "GTPE2_CHANNEL_TXCHARISK1", - "PMASCANIN3": "GTPE2_CHANNEL_PMASCANIN3", - "TXPOSTCURSOR0": "GTPE2_CHANNEL_TXPOSTCURSOR0", - "EYESCANTRIGGER": "GTPE2_CHANNEL_EYESCANTRIGGER", - "TXSEQUENCE2": "GTPE2_CHANNEL_TXSEQUENCE2", - "GTRSVD0": "GTPE2_CHANNEL_GTRSVD0", - "CLKRSVD0": "GTPE2_CHANNEL_CLKRSVD0", - "RXPMARESETDONE": "GTPE2_CHANNEL_RXPMARESETDONE", - "DRPADDR0": "GTPE2_CHANNEL_DRPADDR0", - "TXPHDLYTSTCLK": "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "RXRATE2": "GTPE2_CHANNEL_RXRATE2", - "DMONITOROUT10": "GTPE2_CHANNEL_DMONITOROUT10", - "TXDATA0": "GTPE2_CHANNEL_TXDATA0", - "RXDATA22": "GTPE2_CHANNEL_RXDATA22", - "RXCHBONDSLAVE": "GTPE2_CHANNEL_RXCHBONDSLAVE", - "TXPMARESET": "GTPE2_CHANNEL_TXPMARESET", - "TXCOMFINISH": "GTPE2_CHANNEL_TXCOMFINISH", - "TXDETECTRX": "GTPE2_CHANNEL_TXDETECTRX", - "PMASCANIN5": "GTPE2_CHANNEL_PMASCANIN5", - "DRPADDR2": "GTPE2_CHANNEL_DRPADDR2", - "TSTIN17": "GTPE2_CHANNEL_TSTIN17", - "RXCHARISK2": "GTPE2_CHANNEL_RXCHARISK2", - "TXDLYUPDOWN": "GTPE2_CHANNEL_TXDLYUPDOWN", - "PMARSVDIN0": "GTPE2_CHANNEL_PMARSVDIN0", - "SIGVALIDCLK": "GTPE2_CHANNEL_SIGVALIDCLK", - "TXMARGIN0": "GTPE2_CHANNEL_TXMARGIN0", - "GTPRXP": "GTPE2_CHANNEL_RXP", - "DMONITOROUT11": "GTPE2_CHANNEL_DMONITOROUT11", - "RXDATA7": "GTPE2_CHANNEL_RXDATA7", - "TXDATA2": "GTPE2_CHANNEL_TXDATA2", - "DMONITOROUT1": "GTPE2_CHANNEL_DMONITOROUT1", - "TXCOMINIT": "GTPE2_CHANNEL_TXCOMINIT", - "RXRESETDONE": "GTPE2_CHANNEL_RXRESETDONE", - "TSTIN9": "GTPE2_CHANNEL_TSTIN9", - "TXSYSCLKSEL0": "GTPE2_CHANNEL_TXSYSCLKSEL0", - "TXDLYTESTENB": "GTPE2_CHANNEL_TXDLYTESTENB", - "PCSRSVDOUT5": "GTPE2_CHANNEL_PCSRSVDOUT5", - "RXCHARISCOMMA0": "GTPE2_CHANNEL_RXCHARISCOMMA0", - "RXOSINTOVRDEN": "GTPE2_CHANNEL_RXOSINTOVRDEN", - "RXCHBONDO3": "GTPE2_CHANNEL_RXCHBONDO3", - "PCSRSVDOUT12": "GTPE2_CHANNEL_PCSRSVDOUT12", - "DRPDI2": "GTPE2_CHANNEL_DRPDI2", - "TXPOSTCURSOR1": "GTPE2_CHANNEL_TXPOSTCURSOR1", - "PCSRSVDOUT8": "GTPE2_CHANNEL_PCSRSVDOUT8", - "GTRSVD6": "GTPE2_CHANNEL_GTRSVD6", - "DRPDO10": "GTPE2_CHANNEL_DRPDO10", - "GTTXRESET": "GTPE2_CHANNEL_GTTXRESET", - "RXDATA10": "GTPE2_CHANNEL_RXDATA10", - "RXRATEDONE": "GTPE2_CHANNEL_RXRATEDONE", - "TXDLYSRESETDONE": "GTPE2_CHANNEL_TXDLYSRESETDONE", - "RXOSINTCFG1": "GTPE2_CHANNEL_RXOSINTCFG1", - "RXDATA14": "GTPE2_CHANNEL_RXDATA14", - "RXPHSLIPMONITOR2": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "TXPIPPMSTEPSIZE1": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "RXPRBSERR": "GTPE2_CHANNEL_RXPRBSERR", - "TXSEQUENCE1": "GTPE2_CHANNEL_TXSEQUENCE1", - "DRPDO12": "GTPE2_CHANNEL_DRPDO12", - "GTRSVD12": "GTPE2_CHANNEL_GTRSVD12", - "RXOSINTEN": "GTPE2_CHANNEL_RXOSINTEN", - "RXDATA19": "GTPE2_CHANNEL_RXDATA19", - "RXDATA17": "GTPE2_CHANNEL_RXDATA17", - "TSTIN13": "GTPE2_CHANNEL_TSTIN13", - "RXHEADER0": "GTPE2_CHANNEL_RXHEADER0", - "PMARSVDIN3": "GTPE2_CHANNEL_PMARSVDIN3", - "RXBUFSTATUS1": "GTPE2_CHANNEL_RXBUFSTATUS1", - "PMASCANMODEB": "GTPE2_CHANNEL_PMASCANMODEB", - "DRPDO3": "GTPE2_CHANNEL_DRPDO3", - "PCSRSVDIN14": "GTPE2_CHANNEL_PCSRSVDIN14", - "TXDATA9": "GTPE2_CHANNEL_TXDATA9", - "PMARSVDOUT0": "GTPE2_CHANNEL_PMARSVDOUT0", - "RXUSERRDY": "GTPE2_CHANNEL_RXUSERRDY", - "RXDATA8": "GTPE2_CHANNEL_RXDATA8", - "RXDISPERR2": "GTPE2_CHANNEL_RXDISPERR2", - "RXSLIDE": "GTPE2_CHANNEL_RXSLIDE", - "TXPRBSSEL0": "GTPE2_CHANNEL_TXPRBSSEL0", - "RXOSINTSTARTED": "GTPE2_CHANNEL_RXOSINTSTARTED", - "TXMARGIN2": "GTPE2_CHANNEL_TXMARGIN2", - "SCANENB": "GTPE2_CHANNEL_SCANENB", - "RXDATA31": "GTPE2_CHANNEL_RXDATA31", - "PMARSVDIN4": "GTPE2_CHANNEL_PMARSVDIN4", - "PMASCANOUT1": "GTPE2_CHANNEL_PMASCANOUT1", - "RXPD1": "GTPE2_CHANNEL_RXPD1", - "TXDATA11": "GTPE2_CHANNEL_TXDATA11", - "PCSRSVDIN9": "GTPE2_CHANNEL_PCSRSVDIN9", - "TXDATA4": "GTPE2_CHANNEL_TXDATA4", - "PMARSVDIN1": "GTPE2_CHANNEL_PMARSVDIN1", - "RXADAPTSELTEST7": "GTPE2_CHANNEL_RXADAPTSELTEST7", - "DRPDI9": "GTPE2_CHANNEL_DRPDI9", - "RXSYSCLKSEL0": "GTPE2_CHANNEL_RXSYSCLKSEL0", - "RXADAPTSELTEST12": "GTPE2_CHANNEL_RXADAPTSELTEST12", - "TXSYNCALLIN": "GTPE2_CHANNEL_TXSYNCALLIN", - "RXBUFSTATUS0": "GTPE2_CHANNEL_RXBUFSTATUS0", - "TXPHOVRDEN": "GTPE2_CHANNEL_TXPHOVRDEN", - "RXPCOMMAALIGNEN": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "RXELECIDLEMODE0": "GTPE2_CHANNEL_RXELECIDLEMODE0", - "TXSYNCIN": "GTPE2_CHANNEL_TXSYNCIN", - "DRPCLK": "GTPE2_CHANNEL_DRPCLK", - "TXMAINCURSOR0": "GTPE2_CHANNEL_TXMAINCURSOR0", - "TXMARGIN1": "GTPE2_CHANNEL_TXMARGIN1", - "PCSRSVDIN0": "GTPE2_CHANNEL_PCSRSVDIN0", - "RXDATA5": "GTPE2_CHANNEL_RXDATA5", - "PMARSVDIN2": "GTPE2_CHANNEL_PMARSVDIN2", - "RXDATA0": "GTPE2_CHANNEL_RXDATA0", - "RXPHMONITOR4": "GTPE2_CHANNEL_RXPHMONITOR4", - "PMASCANOUT4": "GTPE2_CHANNEL_PMASCANOUT4", - "SCANOUT5": "GTPE2_CHANNEL_SCANOUT5", - "TSTIN0": "GTPE2_CHANNEL_TSTIN0", - "RXHEADERVALID": "GTPE2_CHANNEL_RXHEADERVALID", - "SCANOUT2": "GTPE2_CHANNEL_SCANOUT2", - "RXPHALIGN": "GTPE2_CHANNEL_RXPHALIGN", - "RXCDRLOCK": "GTPE2_CHANNEL_RXCDRLOCK", - "RXUSRCLK2": "GTPE2_CHANNEL_RXUSRCLK2", - "RXNOTINTABLE3": "GTPE2_CHANNEL_RXNOTINTABLE3", - "GTRSVD3": "GTPE2_CHANNEL_GTRSVD3", - "TXSEQUENCE0": "GTPE2_CHANNEL_TXSEQUENCE0", - "TXPIPPMSTEPSIZE3": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IPAD", - "y_coord": 22, - "type": "IPAD", - "site_pins": { - "O": "GTPE2_CHANNEL_RXN_PAD" - }, - "x_coord": 1, - "name": "X1Y22" - }, - { - "prefix": "IPAD", - "y_coord": 23, - "type": "IPAD", - "site_pins": { - "O": "GTPE2_CHANNEL_RXP_PAD" - }, - "x_coord": 1, - "name": "X1Y23" - }, - { - "prefix": "OPAD", - "y_coord": 2, - "type": "OPAD", - "site_pins": { - "I": "GTPE2_CHANNEL_TXN_PAD" - }, - "x_coord": 0, - "name": "X0Y2" - }, - { - "prefix": "OPAD", - "y_coord": 3, - "type": "OPAD", - "site_pins": { - "I": "GTPE2_CHANNEL_TXP_PAD" - }, - "x_coord": 0, - "name": "X0Y3" - } - ], "pips": { - "GTP_CHANNEL_2.GTPE2_IMUX16_2->GTPE2_CHANNEL_TXDATA20": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA20", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX36_5->GTPE2_CHANNEL_TXPHDLYRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT4->GTPE2_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX14_0->GTPE2_CHANNEL_TXPDELECIDLEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX32_8->GTPE2_CHANNEL_RXDLYBYPASS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYBYPASS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX5_0->GTPE2_CHANNEL_RXCHBONDLEVEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATAVALID1->GTPE2_LOGIC_OUTS_B5_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATAVALID1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCDONE->GTPE2_LOGIC_OUTS_B14_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSYNCDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK1_8->GTPE2_CHANNEL_CLKRSVD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CLKRSVD1", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK1_2->GTPE2_CHANNEL_TXPHDLYTSTCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXP_PAD->GTPE2_CHANNEL_RXP": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXP", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXP_PAD", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXGEARBOXREADY->GTPE2_LOGIC_OUTS_B23_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXGEARBOXREADY", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_1->GTPE2_CHANNEL_RXSLIDE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSLIDE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX31_1->GTPE2_CHANNEL_TXHEADER1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA9->GTPE2_LOGIC_OUTS_B2_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA5->GTPE2_LOGIC_OUTS_B7_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO13->GTPE2_LOGIC_OUTS_B15_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX33_2->GTPE2_CHANNEL_TXPHALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX33_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXNOTINTABLE2->GTPE2_LOGIC_OUTS_B14_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFSTATUS0->GTPE2_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMSASDET->GTPE2_LOGIC_OUTS_B18_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMSASDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX26_4->GTPE2_CHANNEL_GTRSVD9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX1_8->GTPE2_CHANNEL_TXOUTCLKSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX18_3->GTPE2_CHANNEL_TXDATA16": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA16", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_5->GTPE2_CHANNEL_TSTIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX13_10->GTPE2_CHANNEL_RXPRBSCNTRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSCNTRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX4_0->GTPE2_CHANNEL_RXCHBONDLEVEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXHEADER2->GTPE2_LOGIC_OUTS_B17_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT5->GTPE2_LOGIC_OUTS_B9_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT5", - "is_pseudo": "0" - }, "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHMONITOR2->GTPE2_LOGIC_OUTS_B7_2": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_2", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_RXPHMONITOR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX39_5->GTPE2_CHANNEL_TXDETECTRX": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDETECTRX", "is_directional": "1", - "src_wire": "GTPE2_IMUX39_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX0_10->GTPE2_CHANNEL_RXELECIDLEMODE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHMONITOR1->GTPE2_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX30_3->GTPE2_CHANNEL_TXPOLARITY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOLARITY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX36_8->GTPE2_CHANNEL_RXADAPTSELTEST12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX15_9->GTPE2_CHANNEL_RXOSINTEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT5->GTPE2_LOGIC_OUTS_B13_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA7->GTPE2_LOGIC_OUTS_B5_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX28_8->GTPE2_CHANNEL_RXPD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX20_4->GTPE2_CHANNEL_TXDATA14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX47_4->GTPE2_CHANNEL_TXCHARISK3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO7->GTPE2_LOGIC_OUTS_B4_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA28->GTPE2_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA28", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL0_10->GTPE2_CHANNEL_GTRESETSEL": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRESETSEL", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATAVALID0->GTPE2_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATAVALID0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX47_9->GTPE2_CHANNEL_LOOPBACK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX35_5->GTPE2_CHANNEL_TXDEEMPH": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDEEMPH", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX35_6->GTPE2_CHANNEL_TXPD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX16_0->GTPE2_CHANNEL_TXSEQUENCE5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTARTOFSEQ0->GTPE2_LOGIC_OUTS_B18_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX39_0->GTPE2_CHANNEL_TXHEADER2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDO3->GTPE2_LOGIC_OUTS_B16_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX44_7->GTPE2_CHANNEL_RXADAPTSELTEST7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_3->GTPE2_CHANNEL_TXPIPPMSEL": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSEL", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX17_8->GTPE2_CHANNEL_RXADAPTSELTEST11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX22_3->GTPE2_CHANNEL_TXDATA18": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA18", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX4_4->GTPE2_CHANNEL_TXMAINCURSOR5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX23_3->GTPE2_CHANNEL_TXDATA19": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA19", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSERR->GTPE2_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPRBSERR", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHSLIPMONITOR2->GTPE2_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX31_5->GTPE2_CHANNEL_TXCHARISK1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX16_4->GTPE2_CHANNEL_TXDATA12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX0_7->GTPE2_CHANNEL_RXADAPTSELTEST0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHANISALIGNED->GTPE2_LOGIC_OUTS_B18_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANISALIGNED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX10_3->GTPE2_CHANNEL_TXPIPPMOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_9->GTPE2_CHANNEL_GTRSVD6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_3->GTPE2_CHANNEL_TXPOSTCURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO10->GTPE2_LOGIC_OUTS_B2_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX17_4->GTPE2_CHANNEL_TXDATA13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL0_6->GTPE2_CHANNEL_RXDLYSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYSRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_4->GTPE2_CHANNEL_TXPOSTCURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX24_2->GTPE2_CHANNEL_TSTIN11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_1->GTPE2_CHANNEL_RXPCOMMAALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_10->GTPE2_CHANNEL_RXLPMLFOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDISPERR3->GTPE2_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX20_1->GTPE2_CHANNEL_TXDATA30": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA30", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT7->GTPE2_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDISPERR1->GTPE2_LOGIC_OUTS_B22_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX30_7->GTPE2_CHANNEL_RXPD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA10->GTPE2_LOGIC_OUTS_B4_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX22_7->GTPE2_CHANNEL_TXDATA2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX29_6->GTPE2_CHANNEL_TXCHARDISPMODE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX24_6->GTPE2_CHANNEL_TSTIN15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT9->GTPE2_LOGIC_OUTS_B21_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX41_7->GTPE2_CHANNEL_RXADAPTSELTEST6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX2_1->GTPE2_CHANNEL_TXCOMINIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMINIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX25_8->GTPE2_CHANNEL_PCSRSVDIN5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX29_4->GTPE2_CHANNEL_TXCHARDISPMODE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA19->GTPE2_LOGIC_OUTS_B0_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA19", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX19_3->GTPE2_CHANNEL_TXDATA17": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA17", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDO1->GTPE2_LOGIC_OUTS_B16_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX0_9->GTPE2_CHANNEL_RXOSINTOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXCOMFINISH->GTPE2_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXCOMFINISH", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX34_4->GTPE2_CHANNEL_SETERRSTATUS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_SETERRSTATUS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXHEADER0->GTPE2_LOGIC_OUTS_B19_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHINITDONE->GTPE2_LOGIC_OUTS_B1_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPHINITDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKPCS->GTPE2_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOUTCLKPCS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_8->GTPE2_CHANNEL_GTRSVD5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX34_3->GTPE2_CHANNEL_DRPADDR7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_9->GTPE2_CHANNEL_TSTIN8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX36_7->GTPE2_CHANNEL_RXOSINTNTRLEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTNTRLEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT10->GTPE2_LOGIC_OUTS_B13_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX27_8->GTPE2_CHANNEL_TXCOMSAS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMSAS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_3->GTPE2_CHANNEL_TXSTARTSEQ": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSTARTSEQ", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX2_3->GTPE2_CHANNEL_DRPADDR8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX46_9->GTPE2_CHANNEL_LOOPBACK1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBYTEISALIGNED->GTPE2_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBYTEISALIGNED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXRESETDONE->GTPE2_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL1_5->GTPE2_CHANNEL_CFGRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CFGRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX21_2->GTPE2_CHANNEL_TXDATA23": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA23", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX0_2->GTPE2_CHANNEL_TX8B10BEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX1_3->GTPE2_CHANNEL_TXMAINCURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX29_7->GTPE2_CHANNEL_RXADAPTSELTEST8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK1_5->GTPE2_CHANNEL_DMONITORCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DMONITORCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX46_3->GTPE2_CHANNEL_TXPIPPMPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX13_0->GTPE2_CHANNEL_TXSYNCMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX23_9->GTPE2_CHANNEL_RXCHBONDI3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX21_8->GTPE2_CHANNEL_RXADAPTSELTEST13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXN->GTPE2_CHANNEL_TXN_PAD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXN_PAD", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX6_1->GTPE2_CHANNEL_RXGEARBOXSLIP": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXGEARBOXSLIP", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTDONE->GTPE2_LOGIC_OUTS_B3_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_2->GTPE2_CHANNEL_PMARSVDIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_2" }, "GTP_CHANNEL_2.GTPE2_CHANNEL_GTTXOUTCLK_2->GTPE2_CHANNEL_TXOUTCLK_2": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLK_2", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_GTTXOUTCLK_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX14_9->GTPE2_CHANNEL_RXPHALIGN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHALIGN", "is_directional": "1", - "src_wire": "GTPE2_IMUX14_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX26_3->GTPE2_CHANNEL_GTRSVD8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX10_6->GTPE2_CHANNEL_DRPDI1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA21->GTPE2_LOGIC_OUTS_B7_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA21", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCOUT->GTPE2_LOGIC_OUTS_B14_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXSYNCOUT", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX37_3->GTPE2_CHANNEL_TXPHDLYPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX9_8->GTPE2_CHANNEL_PCSRSVDIN13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX6_6->GTPE2_CHANNEL_TXPRECURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX35_4->GTPE2_CHANNEL_TXMARGIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX30_8->GTPE2_CHANNEL_RXCDRHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX45_2->GTPE2_CHANNEL_RXSYSCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX39_4->GTPE2_CHANNEL_TXMARGIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX25_2->GTPE2_CHANNEL_TXPHALIGN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHALIGN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_8->GTPE2_CHANNEL_TSTIN7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX31_4->GTPE2_CHANNEL_TX8B10BBYPASS3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX44_9->GTPE2_CHANNEL_RXCOMMADETEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCOMMADETEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFSTATUS1->GTPE2_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX27_0->GTPE2_CHANNEL_TXSEQUENCE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX1_4->GTPE2_CHANNEL_TXMAINCURSOR6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX2_0->GTPE2_CHANNEL_EYESCANMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX14_1->GTPE2_CHANNEL_TXPRBSFORCEERR": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSFORCEERR", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL1_6->GTPE2_CHANNEL_RXBUFRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXBUFRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX5_3->GTPE2_CHANNEL_TXMAINCURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX5_7->GTPE2_CHANNEL_RXADAPTSELTEST3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXNOTINTABLE1->GTPE2_LOGIC_OUTS_B14_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISCOMMA0->GTPE2_LOGIC_OUTS_B15_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISK0->GTPE2_LOGIC_OUTS_B12_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX5_4->GTPE2_CHANNEL_TXMAINCURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT14->GTPE2_LOGIC_OUTS_B10_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX9_4->GTPE2_CHANNEL_PCSRSVDIN9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX21_4->GTPE2_CHANNEL_TXDATA15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX28_10->GTPE2_CHANNEL_RXOSINTID01": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID01", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX17_10->GTPE2_CHANNEL_DRPDI14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX24_9->GTPE2_CHANNEL_TSTIN18": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN18", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX38_10->GTPE2_CHANNEL_RXOSINTCFG0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX5_8->GTPE2_CHANNEL_TXOUTCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA18->GTPE2_LOGIC_OUTS_B4_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA18", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX38_3->GTPE2_CHANNEL_DRPADDR5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX28_4->GTPE2_CHANNEL_TXSYSCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_0->GTPE2_CHANNEL_RXSYNCIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMINITDET->GTPE2_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMINITDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO6->GTPE2_LOGIC_OUTS_B22_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX45_4->GTPE2_CHANNEL_TSTIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_6->GTPE2_CHANNEL_TXPRECURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTATUS0->GTPE2_LOGIC_OUTS_B21_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA12->GTPE2_LOGIC_OUTS_B3_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX19_9->GTPE2_CHANNEL_RXCHBONDI1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX30_10->GTPE2_CHANNEL_RXCHBONDSLAVE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDSLAVE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX6_10->GTPE2_CHANNEL_RXOSINTCFG1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX37_4->GTPE2_CHANNEL_TXDIFFPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX15_10->GTPE2_CHANNEL_RXOSINTID00": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID00", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA11->GTPE2_LOGIC_OUTS_B0_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX38_2->GTPE2_CHANNEL_DRPADDR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX37_7->GTPE2_CHANNEL_PMARSVDIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX35_3->GTPE2_CHANNEL_DRPADDR6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXPMARESETDONE->GTPE2_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPMARESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX44_3->GTPE2_CHANNEL_DRPEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA30->GTPE2_LOGIC_OUTS_B1_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA30", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX22_5->GTPE2_CHANNEL_TXDATA10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX45_0->GTPE2_CHANNEL_RXDFEXYDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDFEXYDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX46_2->GTPE2_CHANNEL_RXOSCALRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSCALRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHSLIPMONITOR4->GTPE2_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX17_2->GTPE2_CHANNEL_TXDATA21": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA21", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO11->GTPE2_LOGIC_OUTS_B1_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTARTED->GTPE2_LOGIC_OUTS_B6_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTARTED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX37_8->GTPE2_CHANNEL_PMARSVDIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX4_3->GTPE2_CHANNEL_TXMAINCURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX29_2->GTPE2_CHANNEL_TXCHARDISPMODE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL0_5->GTPE2_CHANNEL_GTTXRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTTXRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT6->GTPE2_LOGIC_OUTS_B9_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX39_6->GTPE2_CHANNEL_TXELECIDLE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXELECIDLE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX12_3->GTPE2_CHANNEL_TXCHARDISPMODE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B15_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANDATAERROR->GTPE2_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_EYESCANDATAERROR", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX29_10->GTPE2_CHANNEL_TXDATA27": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA27", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT2->GTPE2_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX20_2->GTPE2_CHANNEL_TXDATA22": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA22", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT7->GTPE2_LOGIC_OUTS_B13_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO12->GTPE2_LOGIC_OUTS_B7_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX28_3->GTPE2_CHANNEL_DRPWE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPWE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX38_8->GTPE2_CHANNEL_RXPRBSSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX45_7->GTPE2_CHANNEL_TXPISOPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPISOPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX20_6->GTPE2_CHANNEL_TXDATA6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX35_8->GTPE2_CHANNEL_TXPIPPMSTEPSIZE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFSTATUS1->GTPE2_LOGIC_OUTS_B19_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_4->GTPE2_CHANNEL_GTRSVD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCDONE->GTPE2_LOGIC_OUTS_B22_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXSYNCDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA25->GTPE2_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA25", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX9_10->GTPE2_CHANNEL_PCSRSVDIN15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX41_0->GTPE2_CHANNEL_RXDLYOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX15_3->GTPE2_CHANNEL_TX8B10BBYPASS2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX38_4->GTPE2_CHANNEL_TXMARGIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMWAKEDET->GTPE2_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMWAKEDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISCOMMA1->GTPE2_LOGIC_OUTS_B15_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX11_7->GTPE2_CHANNEL_RXADAPTSELTEST9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX41_5->GTPE2_CHANNEL_RESETOVRD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RESETOVRD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT13->GTPE2_LOGIC_OUTS_B1_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO1->GTPE2_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX24_7->GTPE2_CHANNEL_TSTIN16": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN16", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT3->GTPE2_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA29->GTPE2_LOGIC_OUTS_B7_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA29", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHANBONDSEQ->GTPE2_LOGIC_OUTS_B8_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANBONDSEQ", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX0_8->GTPE2_CHANNEL_RXADAPTSELTEST10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPHALIGNDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO4->GTPE2_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX38_9->GTPE2_CHANNEL_DRPDI5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXRESETDONE->GTPE2_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX44_5->GTPE2_CHANNEL_TXDLYBYPASS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYBYPASS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX10_9->GTPE2_CHANNEL_PMARSVDIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX44_10->GTPE2_CHANNEL_TXDATA26": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA26", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_0->GTPE2_CHANNEL_RXOSINTPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHMONITOR4->GTPE2_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX13_8->GTPE2_CHANNEL_RXOSOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMMADET->GTPE2_LOGIC_OUTS_B19_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMMADET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX46_6->GTPE2_CHANNEL_TXRATE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_10->GTPE2_CHANNEL_GTRSVD7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO3->GTPE2_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISK1->GTPE2_LOGIC_OUTS_B12_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX22_8->GTPE2_CHANNEL_RXPRBSSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX23_8->GTPE2_CHANNEL_RXPRBSSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX2_5->GTPE2_CHANNEL_TXDIFFCTRL3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL0_8->GTPE2_CHANNEL_GTRXRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRXRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCOUT->GTPE2_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSYNCOUT", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX21_1->GTPE2_CHANNEL_TXDATA31": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA31", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX24_3->GTPE2_CHANNEL_TSTIN12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_0->GTPE2_CHANNEL_RXSYNCMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL1_8->GTPE2_CHANNEL_RXCDRRESETRSV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRRESETRSV", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT11->GTPE2_LOGIC_OUTS_B21_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL1_3->GTPE2_CHANNEL_TXPMARESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPMARESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA2->GTPE2_LOGIC_OUTS_B4_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX39_2->GTPE2_CHANNEL_DRPADDR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_3->GTPE2_CHANNEL_TSTIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX26_10->GTPE2_CHANNEL_GTRSVD15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX9_3->GTPE2_CHANNEL_PCSRSVDIN8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX1_0->GTPE2_CHANNEL_RXCHBONDLEVEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDLYSRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX31_0->GTPE2_CHANNEL_TXUSERRDY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSERRDY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA24->GTPE2_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA24", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL1_9->GTPE2_CHANNEL_RXCDRRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_2->GTPE2_CHANNEL_RXSYSCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX16_1->GTPE2_CHANNEL_TXDATA28": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA28", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL1_7->GTPE2_CHANNEL_RXPMARESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPMARESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX46_0->GTPE2_CHANNEL_TXPCSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPCSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX32_2->GTPE2_CHANNEL_TXINHIBIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXINHIBIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX26_9->GTPE2_CHANNEL_GTRSVD14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDO2->GTPE2_LOGIC_OUTS_B16_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT9->GTPE2_LOGIC_OUTS_B13_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT1->GTPE2_LOGIC_OUTS_B0_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTROBESTARTED->GTPE2_LOGIC_OUTS_B0_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISCOMMA3->GTPE2_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRLOCK->GTPE2_LOGIC_OUTS_B17_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCDRLOCK", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK0_7->GTPE2_CHANNEL_RXUSRCLK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSRCLK2", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_5->GTPE2_CHANNEL_TXDIFFCTRL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXP->GTPE2_CHANNEL_TXP_PAD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXP_PAD", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXP", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKPCS->GTPE2_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXOUTCLKPCS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX31_8->GTPE2_CHANNEL_EYESCANTRIGGER": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANTRIGGER", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX31_7->GTPE2_CHANNEL_TXCHARISK0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX25_6->GTPE2_CHANNEL_PCSRSVDIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA15->GTPE2_LOGIC_OUTS_B5_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT6->GTPE2_LOGIC_OUTS_B13_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_0->GTPE2_CHANNEL_TXSEQUENCE6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX33_5->GTPE2_CHANNEL_DRPDI10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX33_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX24_8->GTPE2_CHANNEL_TSTIN17": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN17", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX38_5->GTPE2_CHANNEL_TXSWING": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSWING", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX15_7->GTPE2_CHANNEL_TX8B10BBYPASS0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_9->GTPE2_CHANNEL_DRPDI7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX19_5->GTPE2_CHANNEL_TXDATA9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA17->GTPE2_LOGIC_OUTS_B2_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA17", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATEDONE->GTPE2_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXRATEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX35_10->GTPE2_CHANNEL_RXOSINTCFG2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX2_4->GTPE2_CHANNEL_TXPOSTCURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA26->GTPE2_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA26", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXDLYSRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX23_5->GTPE2_CHANNEL_TXDATA11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX38_6->GTPE2_CHANNEL_TXPD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX29_8->GTPE2_CHANNEL_RXOSHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX30_9->GTPE2_CHANNEL_RXCHBONDMASTER": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDMASTER", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX35_2->GTPE2_CHANNEL_DRPADDR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXN_PAD->GTPE2_CHANNEL_RXN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXN", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXN_PAD", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PLLCLK0->GTPE2_CHANNEL_PLL0CLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL0CLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLCLK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX1_9->GTPE2_CHANNEL_RXOSINTHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA13->GTPE2_LOGIC_OUTS_B7_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX26_5->GTPE2_CHANNEL_GTRSVD10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX41_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX13_4->GTPE2_CHANNEL_TSTIN10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_7->GTPE2_CHANNEL_TXPRECURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX17_1->GTPE2_CHANNEL_TXDATA29": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA29", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX2_6->GTPE2_CHANNEL_TXPRECURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX24_5->GTPE2_CHANNEL_TSTIN14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_6->GTPE2_CHANNEL_TXPRECURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA31->GTPE2_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA31", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_8->GTPE2_CHANNEL_RXDDIEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDDIEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXHEADER1->GTPE2_LOGIC_OUTS_B23_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX28_5->GTPE2_CHANNEL_TXSYSCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX18_5->GTPE2_CHANNEL_TXDATA8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBYTEREALIGN->GTPE2_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBYTEREALIGN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_4->GTPE2_CHANNEL_TXCHARDISPVAL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX30_6->GTPE2_CHANNEL_TXPOSTCURSORINV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSORINV", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDISPERR0->GTPE2_LOGIC_OUTS_B22_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX44_1->GTPE2_CHANNEL_DMONFIFORESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DMONFIFORESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK1_7->GTPE2_CHANNEL_CLKRSVD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CLKRSVD0", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX39_3->GTPE2_CHANNEL_DRPADDR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX39_1->GTPE2_CHANNEL_TXHEADER0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PLLREFCLK0->GTPE2_CHANNEL_PLL0REFCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL0REFCLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLREFCLK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_7->GTPE2_CHANNEL_GTRSVD4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFSTATUS2->GTPE2_LOGIC_OUTS_B17_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX9_5->GTPE2_CHANNEL_PCSRSVDIN10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_8->GTPE2_CHANNEL_TXPRBSSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PHYSTATUS->GTPE2_LOGIC_OUTS_B10_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PHYSTATUS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX14_8->GTPE2_CHANNEL_RXCDROVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDROVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX22_6->GTPE2_CHANNEL_TXPIPPMSTEPSIZE4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX41_1->GTPE2_CHANNEL_RXMCOMMAALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_7->GTPE2_CHANNEL_TSTIN6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL1_4->GTPE2_CHANNEL_RXPHDLYRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHDLYRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX25_10->GTPE2_CHANNEL_PCSRSVDIN7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_3->GTPE2_CHANNEL_GTRSVD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK0_5->GTPE2_CHANNEL_TXUSRCLK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSRCLK2", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX18_9->GTPE2_CHANNEL_RXCHBONDI0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTROBEDONE->GTPE2_LOGIC_OUTS_B0_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX25_7->GTPE2_CHANNEL_PCSRSVDIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA6->GTPE2_LOGIC_OUTS_B1_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT4->GTPE2_LOGIC_OUTS_B9_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT12->GTPE2_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_4->GTPE2_CHANNEL_TSTIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_7->GTPE2_CHANNEL_RXPHDLYPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHDLYPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX19_7->GTPE2_CHANNEL_TXDATA1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX44_0->GTPE2_CHANNEL_TXPHOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX45_5->GTPE2_CHANNEL_DRPDI9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX0_3->GTPE2_CHANNEL_TXMAINCURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_6->GTPE2_CHANNEL_TXCHARDISPVAL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCLKCORCNT1->GTPE2_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX45_6->GTPE2_CHANNEL_DRPDI0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHMONITOR0->GTPE2_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT0->GTPE2_LOGIC_OUTS_B9_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO0->GTPE2_LOGIC_OUTS_B12_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX32_9->GTPE2_CHANNEL_RXOSINTSTROBE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTSTROBE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3->GTPE2_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_1->GTPE2_CHANNEL_TXSEQUENCE4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX14_6->GTPE2_CHANNEL_RXRATE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX15_6->GTPE2_CHANNEL_RXRATE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT0->GTPE2_LOGIC_OUTS_B5_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX5_2->GTPE2_CHANNEL_PMARSVDIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL1_10->GTPE2_CHANNEL_RXOOBRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOOBRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX27_5->GTPE2_CHANNEL_TXPHINIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHINIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_0->GTPE2_CHANNEL_TXPIPPMEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX2_10->GTPE2_CHANNEL_RXOUTCLKSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX23_7->GTPE2_CHANNEL_TXDATA3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCLKCORCNT0->GTPE2_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX32_6->GTPE2_CHANNEL_DRPDI3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO2->GTPE2_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPRDY->GTPE2_LOGIC_OUTS_B14_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPRDY", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT3->GTPE2_LOGIC_OUTS_B9_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX11_10->GTPE2_CHANNEL_RXOSINTID03": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID03", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX26_6->GTPE2_CHANNEL_GTRSVD11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX34_2->GTPE2_CHANNEL_DRPADDR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISCOMMA2->GTPE2_LOGIC_OUTS_B15_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO9->GTPE2_LOGIC_OUTS_B4_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX24_4->GTPE2_CHANNEL_TSTIN13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX44_2->GTPE2_CHANNEL_TXSYNCALLIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCALLIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX6_0->GTPE2_CHANNEL_RXUSERRDY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSERRDY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B7_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PMARSVDOUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX17_9->GTPE2_CHANNEL_RXCHBONDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL0_9->GTPE2_CHANNEL_RXLPMRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHANREALIGN->GTPE2_LOGIC_OUTS_B23_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANREALIGN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXELECIDLE->GTPE2_LOGIC_OUTS_B19_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXELECIDLE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX16_10->GTPE2_CHANNEL_DRPDI15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT13->GTPE2_LOGIC_OUTS_B9_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX32_7->GTPE2_CHANNEL_TXPRECURSORINV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSORINV", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX21_6->GTPE2_CHANNEL_TXDATA7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHSLIPMONITOR1->GTPE2_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK1_4->GTPE2_CHANNEL_SIGVALIDCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_SIGVALIDCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_6->GTPE2_CHANNEL_TSTIN5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA0->GTPE2_LOGIC_OUTS_B6_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX6_4->GTPE2_CHANNEL_TXPOSTCURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX34_6->GTPE2_CHANNEL_DRPDI8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFSTATUS0->GTPE2_LOGIC_OUTS_B23_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_GTRXOUTCLK_2->GTPE2_CHANNEL_RXOUTCLK_2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLK_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_GTRXOUTCLK_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_10->GTPE2_CHANNEL_TSTIN9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_4->GTPE2_CHANNEL_TXPOSTCURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISK2->GTPE2_LOGIC_OUTS_B12_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX9_6->GTPE2_CHANNEL_PCSRSVDIN11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX11_5->GTPE2_CHANNEL_TXDLYHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX35_0->GTPE2_CHANNEL_TXSEQUENCE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLK_2" }, "GTP_CHANNEL_2.GTPE2_IMUX12_7->GTPE2_CHANNEL_TXBUFDIFFCTRL0": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "is_directional": "1", "src_wire": "GTPE2_IMUX12_7", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX45_2->GTPE2_CHANNEL_RXSYSCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL0" }, "GTP_CHANNEL_2.GTPE2_IMUX27_7->GTPE2_CHANNEL_RXPOLARITY": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPOLARITY", - "is_directional": "1", "src_wire": "GTPE2_IMUX27_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT2->GTPE2_LOGIC_OUTS_B9_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_8", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPOLARITY" }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXVALID->GTPE2_LOGIC_OUTS_B20_9": { + "GTP_CHANNEL_2.GTPE2_IMUX3_4->GTPE2_CHANNEL_TXPOSTCURSOR2": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_9", + "src_wire": "GTPE2_IMUX3_4", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXVALID", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR2" }, - "GTP_CHANNEL_2.GTPE2_IMUX43_9->GTPE2_CHANNEL_LOOPBACK0": { + "GTP_CHANNEL_2.GTPE2_IMUX21_6->GTPE2_CHANNEL_TXDATA7": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK0", + "src_wire": "GTPE2_IMUX21_6", "is_directional": "1", - "src_wire": "GTPE2_IMUX43_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXHEADERVALID->GTPE2_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADERVALID", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX5_9->GTPE2_CHANNEL_RXOSINTTESTOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX47_6->GTPE2_CHANNEL_TXRATE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX14_10->GTPE2_CHANNEL_RXPHOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX24_10->GTPE2_CHANNEL_TSTIN19": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN19", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTATUS2->GTPE2_LOGIC_OUTS_B23_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT1->GTPE2_LOGIC_OUTS_B9_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX25_5->GTPE2_CHANNEL_PCSRSVDIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK0_4->GTPE2_CHANNEL_TXUSRCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSRCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT10->GTPE2_LOGIC_OUTS_B21_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA20->GTPE2_LOGIC_OUTS_B3_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA20", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX4_8->GTPE2_CHANNEL_TXOUTCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX43_6->GTPE2_CHANNEL_TXRATE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATEDONE->GTPE2_LOGIC_OUTS_B23_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXRATEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA8->GTPE2_LOGIC_OUTS_B6_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX12_5->GTPE2_CHANNEL_TXDLYOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHMONITOR3->GTPE2_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX45_1->GTPE2_CHANNEL_RX8B10BEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RX8B10BEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX41_10->GTPE2_CHANNEL_TXDATA25": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA25", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX28_6->GTPE2_CHANNEL_RXDLYEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT14->GTPE2_LOGIC_OUTS_B5_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_1->GTPE2_CHANNEL_TXSYNCIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXNOTINTABLE3->GTPE2_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX4_7->GTPE2_CHANNEL_RXADAPTSELTEST2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX27_1->GTPE2_CHANNEL_TXSEQUENCE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX36_2->GTPE2_CHANNEL_RXSYNCALLIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCALLIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX1_7->GTPE2_CHANNEL_RXADAPTSELTEST1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_6->GTPE2_CHANNEL_GTRSVD3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISK3->GTPE2_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_8->GTPE2_CHANNEL_TXPRBSSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX9_7->GTPE2_CHANNEL_PCSRSVDIN12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B15_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PMARSVDOUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX6_9->GTPE2_CHANNEL_DRPDI6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX43_10->GTPE2_CHANNEL_RXLPMHFHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMHFHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX6_5->GTPE2_CHANNEL_TXDIFFCTRL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX45_3->GTPE2_CHANNEL_TXDLYSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK0_6->GTPE2_CHANNEL_RXUSRCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSRCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT11->GTPE2_LOGIC_OUTS_B5_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHALIGNDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPMARESETDONE->GTPE2_LOGIC_OUTS_B12_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPMARESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTATUS1->GTPE2_LOGIC_OUTS_B17_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA14->GTPE2_LOGIC_OUTS_B1_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDISPERR2->GTPE2_LOGIC_OUTS_B22_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA27->GTPE2_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA27", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_2->GTPE2_CHANNEL_TXCHARDISPVAL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX36_10->GTPE2_CHANNEL_DRPDI13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA4->GTPE2_LOGIC_OUTS_B3_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO15->GTPE2_LOGIC_OUTS_B4_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX31_3->GTPE2_CHANNEL_TXCHARISK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_1->GTPE2_CHANNEL_TXCOMWAKE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMWAKE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PLLCLK1->GTPE2_CHANNEL_PLL1CLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL1CLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLCLK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX3_5->GTPE2_CHANNEL_TXDIFFCTRL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT15->GTPE2_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA16->GTPE2_LOGIC_OUTS_B6_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA16", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX37_10->GTPE2_CHANNEL_DRPDI12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX16_6->GTPE2_CHANNEL_TXDATA4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX40_2->GTPE2_CHANNEL_TSTIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA7" }, "GTP_CHANNEL_2.GTPE2_IMUX25_3->GTPE2_CHANNEL_PCSRSVDIN0": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN0", - "is_directional": "1", "src_wire": "GTPE2_IMUX25_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX5_5->GTPE2_CHANNEL_RXLPMLFHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMLFHOLD", "is_directional": "1", - "src_wire": "GTPE2_IMUX5_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN0" }, - "GTP_CHANNEL_2.GTPE2_IMUX35_1->GTPE2_CHANNEL_TXSEQUENCE0": { + "GTP_CHANNEL_2.GTPE2_IMUX44_2->GTPE2_CHANNEL_TXSYNCALLIN": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE0", + "src_wire": "GTPE2_IMUX44_2", "is_directional": "1", - "src_wire": "GTPE2_IMUX35_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCALLIN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_1->GTPE2_CHANNEL_TXSEQUENCE4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE4" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDO3->GTPE2_LOGIC_OUTS_B16_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_1->GTPE2_CHANNEL_RXPCOMMAALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPCOMMAALIGNEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX13_8->GTPE2_CHANNEL_RXOSOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHSLIPMONITOR1->GTPE2_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_0" + }, + "GTP_CHANNEL_2.GTPE2_CLK1_4->GTPE2_CHANNEL_SIGVALIDCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_SIGVALIDCLK" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATAVALID0->GTPE2_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATAVALID0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_3->GTPE2_CHANNEL_TSTIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX35_10->GTPE2_CHANNEL_RXOSINTCFG2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG2" + }, + "GTP_CHANNEL_2.GTPE2_CLK0_6->GTPE2_CHANNEL_RXUSRCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSRCLK" + }, + "GTP_CHANNEL_2.GTPE2_IMUX16_10->GTPE2_CHANNEL_DRPDI15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI15" + }, + "GTP_CHANNEL_2.GTPE2_IMUX20_4->GTPE2_CHANNEL_TXDATA14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA14" }, "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHSLIPMONITOR0->GTPE2_LOGIC_OUTS_B13_0": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_0", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX11_6->GTPE2_CHANNEL_RXRATE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE2", "is_directional": "1", - "src_wire": "GTPE2_IMUX11_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_0" }, - "GTP_CHANNEL_2.GTPE2_IMUX45_8->GTPE2_CHANNEL_EYESCANRESET": { + "GTP_CHANNEL_2.GTPE2_CLK0_4->GTPE2_CHANNEL_TXUSRCLK": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANRESET", + "src_wire": "GTPE2_CLK0_4", "is_directional": "1", - "src_wire": "GTPE2_IMUX45_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX10_7->GTPE2_CHANNEL_TXBUFDIFFCTRL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA22->GTPE2_LOGIC_OUTS_B1_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA22", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX34_7->GTPE2_CHANNEL_RXADAPTSELTEST4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX43_5->GTPE2_CHANNEL_TXDLYUPDOWN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYUPDOWN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT8->GTPE2_LOGIC_OUTS_B21_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO14->GTPE2_LOGIC_OUTS_B12_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX22_9->GTPE2_CHANNEL_RXCHBONDI2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX2_7->GTPE2_CHANNEL_RXRATEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO5->GTPE2_LOGIC_OUTS_B12_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX13_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX46_10->GTPE2_CHANNEL_RXOSINTCFG3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX17_6->GTPE2_CHANNEL_TXDATA5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT12->GTPE2_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX14_5->GTPE2_CHANNEL_TXDLYEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDO0->GTPE2_LOGIC_OUTS_B16_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX46_4->GTPE2_CHANNEL_TXCHARDISPVAL3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA1->GTPE2_LOGIC_OUTS_B2_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PLLREFCLK1->GTPE2_CHANNEL_PLL1REFCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL1REFCLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLREFCLK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX13_7->GTPE2_CHANNEL_TXBUFDIFFCTRL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT8->GTPE2_LOGIC_OUTS_B13_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX18_7->GTPE2_CHANNEL_TXDATA0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CTRL0_7->GTPE2_CHANNEL_RXCDRFREQRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRFREQRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX26_8->GTPE2_CHANNEL_GTRSVD13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX9_9->GTPE2_CHANNEL_PCSRSVDIN14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX4_10->GTPE2_CHANNEL_RXOUTCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX6_8->GTPE2_CHANNEL_TXPRBSSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX13_6->GTPE2_CHANNEL_DRPDI2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX25_4->GTPE2_CHANNEL_PCSRSVDIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXNOTINTABLE0->GTPE2_LOGIC_OUTS_B14_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX8_10->GTPE2_CHANNEL_TXDATA24": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA24", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX41_6->GTPE2_CHANNEL_RXPHALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_2->GTPE2_CHANNEL_RXLPMOSINTNTRLEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTARTOFSEQ1->GTPE2_LOGIC_OUTS_B11_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX25_9->GTPE2_CHANNEL_PCSRSVDIN6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX10_10->GTPE2_CHANNEL_RXOSINTID02": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID02", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX5_10->GTPE2_CHANNEL_RXOUTCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX26_7->GTPE2_CHANNEL_GTRSVD12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX46_1->GTPE2_CHANNEL_RXPCSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPCSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CLK0_9->GTPE2_CHANNEL_DRPCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX6_7->GTPE2_CHANNEL_RXADAPTSELTEST5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO8->GTPE2_LOGIC_OUTS_B12_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA23->GTPE2_LOGIC_OUTS_B5_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA23", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX32_5->GTPE2_CHANNEL_DRPDI11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX11_3->GTPE2_CHANNEL_TXRATEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX7_9->GTPE2_CHANNEL_DRPDI4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX15_5->GTPE2_CHANNEL_TX8B10BBYPASS1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX27_10->GTPE2_CHANNEL_RXLPMHFOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSRCLK" }, "GTP_CHANNEL_2.GTPE2_IMUX1_10->GTPE2_CHANNEL_RXELECIDLEMODE1": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE1", - "is_directional": "1", "src_wire": "GTPE2_IMUX1_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_2.GTPE2_IMUX42_5->GTPE2_CHANNEL_GTRSVD2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD2", "is_directional": "1", - "src_wire": "GTPE2_IMUX42_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX35_3->GTPE2_CHANNEL_DRPADDR6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX35_8->GTPE2_CHANNEL_TXPIPPMSTEPSIZE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA16->GTPE2_LOGIC_OUTS_B6_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT13->GTPE2_LOGIC_OUTS_B9_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA28->GTPE2_LOGIC_OUTS_B3_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXRATEDONE->GTPE2_LOGIC_OUTS_B23_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXRATEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX41_10->GTPE2_CHANNEL_TXDATA25": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA25" + }, + "GTP_CHANNEL_2.GTPE2_IMUX1_8->GTPE2_CHANNEL_TXOUTCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX24_9->GTPE2_CHANNEL_TSTIN18": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN18" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA5->GTPE2_LOGIC_OUTS_B7_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_3->GTPE2_CHANNEL_TXPOSTCURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX1_4->GTPE2_CHANNEL_TXMAINCURSOR6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR6" + }, + "GTP_CHANNEL_2.GTPE2_CLK1_5->GTPE2_CHANNEL_DMONITORCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DMONITORCLK" + }, + "GTP_CHANNEL_2.GTPE2_IMUX17_1->GTPE2_CHANNEL_TXDATA29": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA29" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT11->GTPE2_LOGIC_OUTS_B21_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX6_9->GTPE2_CHANNEL_DRPDI6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX16_6->GTPE2_CHANNEL_TXDATA4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_9->GTPE2_CHANNEL_TSTIN8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX5_5->GTPE2_CHANNEL_RXLPMLFHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMLFHOLD" + }, + "GTP_CHANNEL_2.GTPE2_IMUX6_4->GTPE2_CHANNEL_TXPOSTCURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX9_3->GTPE2_CHANNEL_PCSRSVDIN8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX6_5->GTPE2_CHANNEL_TXDIFFCTRL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX26_9->GTPE2_CHANNEL_GTRSVD14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD14" + }, + "GTP_CHANNEL_2.GTPE2_IMUX14_9->GTPE2_CHANNEL_RXPHALIGN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHALIGN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B15_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PMARSVDOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDISPERR2->GTPE2_LOGIC_OUTS_B22_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX2_3->GTPE2_CHANNEL_DRPADDR8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR8" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA11->GTPE2_LOGIC_OUTS_B0_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_10->GTPE2_CHANNEL_GTRSVD7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD7" + }, + "GTP_CHANNEL_2.GTPE2_CTRL1_3->GTPE2_CHANNEL_TXPMARESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPMARESET" + }, + "GTP_CHANNEL_2.GTPE2_CTRL0_8->GTPE2_CHANNEL_GTRXRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRXRESET" + }, + "GTP_CHANNEL_2.GTPE2_IMUX35_4->GTPE2_CHANNEL_TXMARGIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX3_10->GTPE2_CHANNEL_RXLPMLFOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMLFOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX2_0->GTPE2_CHANNEL_EYESCANMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANMODE" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_5->GTPE2_CHANNEL_TSTIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX36_5->GTPE2_CHANNEL_TXPHDLYRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYRESET" + }, + "GTP_CHANNEL_2.GTPE2_CLK1_7->GTPE2_CHANNEL_CLKRSVD0": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CLKRSVD0" + }, + "GTP_CHANNEL_2.GTPE2_CTRL1_8->GTPE2_CHANNEL_RXCDRRESETRSV": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRRESETRSV" + }, + "GTP_CHANNEL_2.GTPE2_IMUX26_10->GTPE2_CHANNEL_GTRSVD15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD15" + }, + "GTP_CHANNEL_2.GTPE2_IMUX5_10->GTPE2_CHANNEL_RXOUTCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCDONE->GTPE2_LOGIC_OUTS_B22_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXSYNCDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX35_6->GTPE2_CHANNEL_TXPD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPD1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX44_0->GTPE2_CHANNEL_TXPHOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_2->GTPE2_CHANNEL_TSTIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX46_2->GTPE2_CHANNEL_RXOSCALRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSCALRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA8->GTPE2_LOGIC_OUTS_B6_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_8" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISCOMMA3->GTPE2_LOGIC_OUTS_B15_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX4_8->GTPE2_CHANNEL_TXOUTCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT12->GTPE2_LOGIC_OUTS_B15_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_10->GTPE2_CHANNEL_TSTIN9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN9" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHANISALIGNED->GTPE2_LOGIC_OUTS_B18_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANISALIGNED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX11_6->GTPE2_CHANNEL_RXRATE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX29_10->GTPE2_CHANNEL_TXDATA27": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA27" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PLLREFCLK0->GTPE2_CHANNEL_PLL0REFCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLREFCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL0REFCLK" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHANREALIGN->GTPE2_LOGIC_OUTS_B23_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANREALIGN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_9" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHMONITOR0->GTPE2_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B7_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PMARSVDOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX10_10->GTPE2_CHANNEL_RXOSINTID02": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID02" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXNOTINTABLE0->GTPE2_LOGIC_OUTS_B14_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_10" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA30->GTPE2_LOGIC_OUTS_B1_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX13_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX30_3->GTPE2_CHANNEL_TXPOLARITY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOLARITY" + }, + "GTP_CHANNEL_2.GTPE2_IMUX39_4->GTPE2_CHANNEL_TXMARGIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX15_10->GTPE2_CHANNEL_RXOSINTID00": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID00" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT1->GTPE2_LOGIC_OUTS_B0_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX36_10->GTPE2_CHANNEL_DRPDI13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI13" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHMONITOR4->GTPE2_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX41_0->GTPE2_CHANNEL_RXDLYOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_CTRL0_10->GTPE2_CHANNEL_GTRESETSEL": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRESETSEL" + }, + "GTP_CHANNEL_2.GTPE2_IMUX11_7->GTPE2_CHANNEL_RXADAPTSELTEST9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX35_1->GTPE2_CHANNEL_TXSEQUENCE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA10->GTPE2_LOGIC_OUTS_B4_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_8" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PLLCLK1->GTPE2_CHANNEL_PLL1CLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL1CLK" + }, + "GTP_CHANNEL_2.GTPE2_IMUX14_10->GTPE2_CHANNEL_RXPHOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX30_6->GTPE2_CHANNEL_TXPOSTCURSORINV": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSORINV" + }, + "GTP_CHANNEL_2.GTPE2_IMUX4_4->GTPE2_CHANNEL_TXMAINCURSOR5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_7->GTPE2_CHANNEL_RXPHDLYPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHDLYPD" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA27->GTPE2_LOGIC_OUTS_B0_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX6_8->GTPE2_CHANNEL_TXPRBSSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTDONE->GTPE2_LOGIC_OUTS_B3_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXNOTINTABLE3->GTPE2_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_4" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO3->GTPE2_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX32_8->GTPE2_CHANNEL_RXDLYBYPASS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYBYPASS" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO0->GTPE2_LOGIC_OUTS_B12_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX4_10->GTPE2_CHANNEL_RXOUTCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX31_5->GTPE2_CHANNEL_TXCHARISK1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX37_4->GTPE2_CHANNEL_TXDIFFPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFPD" + }, + "GTP_CHANNEL_2.GTPE2_IMUX30_8->GTPE2_CHANNEL_RXCDRHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRHOLD" + }, + "GTP_CHANNEL_2.GTPE2_IMUX47_4->GTPE2_CHANNEL_TXCHARISK3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX9_8->GTPE2_CHANNEL_PCSRSVDIN13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN13" + }, + "GTP_CHANNEL_2.GTPE2_IMUX20_6->GTPE2_CHANNEL_TXDATA6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXCOMFINISH->GTPE2_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXCOMFINISH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX6_1->GTPE2_CHANNEL_RXGEARBOXSLIP": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXGEARBOXSLIP" + }, + "GTP_CHANNEL_2.GTPE2_IMUX15_5->GTPE2_CHANNEL_TX8B10BBYPASS1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX30_10->GTPE2_CHANNEL_RXCHBONDSLAVE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDSLAVE" + }, + "GTP_CHANNEL_2.GTPE2_IMUX46_10->GTPE2_CHANNEL_RXOSINTCFG3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT10->GTPE2_LOGIC_OUTS_B21_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_5" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT7->GTPE2_LOGIC_OUTS_B13_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX31_4->GTPE2_CHANNEL_TX8B10BBYPASS3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXNOTINTABLE2->GTPE2_LOGIC_OUTS_B14_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX9_5->GTPE2_CHANNEL_PCSRSVDIN10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX39_5->GTPE2_CHANNEL_TXDETECTRX": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDETECTRX" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA31->GTPE2_LOGIC_OUTS_B5_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT6->GTPE2_LOGIC_OUTS_B9_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX22_9->GTPE2_CHANNEL_RXCHBONDI2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXGEARBOXREADY->GTPE2_LOGIC_OUTS_B23_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXGEARBOXREADY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX39_3->GTPE2_CHANNEL_DRPADDR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX22_7->GTPE2_CHANNEL_TXDATA2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXHEADER1->GTPE2_LOGIC_OUTS_B23_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX6_6->GTPE2_CHANNEL_TXPRECURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXN_PAD->GTPE2_CHANNEL_RXN": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXN_PAD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX19_3->GTPE2_CHANNEL_TXDATA17": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA17" + }, + "GTP_CHANNEL_2.GTPE2_IMUX29_2->GTPE2_CHANNEL_TXCHARDISPMODE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT12->GTPE2_LOGIC_OUTS_B7_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX31_7->GTPE2_CHANNEL_TXCHARISK0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA4->GTPE2_LOGIC_OUTS_B3_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX47_9->GTPE2_CHANNEL_LOOPBACK2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCDONE->GTPE2_LOGIC_OUTS_B14_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSYNCDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX21_8->GTPE2_CHANNEL_RXADAPTSELTEST13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST13" + }, + "GTP_CHANNEL_2.GTPE2_IMUX31_0->GTPE2_CHANNEL_TXUSERRDY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSERRDY" + }, + "GTP_CHANNEL_2.GTPE2_IMUX37_7->GTPE2_CHANNEL_PMARSVDIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX17_4->GTPE2_CHANNEL_TXDATA13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA13" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXP_PAD->GTPE2_CHANNEL_RXP": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXP_PAD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXP" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKPCS->GTPE2_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOUTCLKPCS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX1_7->GTPE2_CHANNEL_RXADAPTSELTEST1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX36_8->GTPE2_CHANNEL_RXADAPTSELTEST12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST12" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_10->GTPE2_CHANNEL_TXDATA24": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA24" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA24->GTPE2_LOGIC_OUTS_B6_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX10_9->GTPE2_CHANNEL_PMARSVDIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX45_3->GTPE2_CHANNEL_TXDLYSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYSRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHMONITOR1->GTPE2_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDO2->GTPE2_LOGIC_OUTS_B16_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_8" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHSLIPMONITOR3->GTPE2_LOGIC_OUTS_B6_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX17_8->GTPE2_CHANNEL_RXADAPTSELTEST11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST11" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_7->GTPE2_CHANNEL_GTRSVD4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX6_7->GTPE2_CHANNEL_RXADAPTSELTEST5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX6_0->GTPE2_CHANNEL_RXUSERRDY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSERRDY" + }, + "GTP_CHANNEL_2.GTPE2_IMUX24_2->GTPE2_CHANNEL_TSTIN11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN11" + }, + "GTP_CHANNEL_2.GTPE2_IMUX38_10->GTPE2_CHANNEL_RXOSINTCFG0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX24_4->GTPE2_CHANNEL_TSTIN13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN13" + }, + "GTP_CHANNEL_2.GTPE2_IMUX38_2->GTPE2_CHANNEL_DRPADDR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX3_5->GTPE2_CHANNEL_TXDIFFCTRL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX24_8->GTPE2_CHANNEL_TSTIN17": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN17" + }, + "GTP_CHANNEL_2.GTPE2_IMUX26_5->GTPE2_CHANNEL_GTRSVD10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX0_10->GTPE2_CHANNEL_RXELECIDLEMODE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXHEADER0->GTPE2_LOGIC_OUTS_B19_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX19_7->GTPE2_CHANNEL_TXDATA1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHINITDONE->GTPE2_LOGIC_OUTS_B1_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPHINITDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX35_5->GTPE2_CHANNEL_TXDEEMPH": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDEEMPH" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO10->GTPE2_LOGIC_OUTS_B2_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX28_3->GTPE2_CHANNEL_DRPWE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPWE" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXNOTINTABLE1->GTPE2_LOGIC_OUTS_B14_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX24_6->GTPE2_CHANNEL_TSTIN15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN15" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_9->GTPE2_CHANNEL_DRPDI4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX0_8->GTPE2_CHANNEL_RXADAPTSELTEST10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST10" + }, + "GTP_CHANNEL_2.GTPE2_CLK0_9->GTPE2_CHANNEL_DRPCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPCLK" + }, + "GTP_CHANNEL_2.GTPE2_IMUX22_8->GTPE2_CHANNEL_RXPRBSSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX29_7->GTPE2_CHANNEL_RXADAPTSELTEST8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST8" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDISPERR1->GTPE2_LOGIC_OUTS_B22_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX47_6->GTPE2_CHANNEL_TXRATE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX10_7->GTPE2_CHANNEL_TXBUFDIFFCTRL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX34_3->GTPE2_CHANNEL_DRPADDR7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX1_3->GTPE2_CHANNEL_TXMAINCURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR2" + }, + "GTP_CHANNEL_2.GTPE2_CTRL0_5->GTPE2_CHANNEL_GTTXRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTTXRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA2->GTPE2_LOGIC_OUTS_B4_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX46_4->GTPE2_CHANNEL_TXCHARDISPVAL3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX34_4->GTPE2_CHANNEL_SETERRSTATUS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_SETERRSTATUS" + }, + "GTP_CHANNEL_2.GTPE2_IMUX4_7->GTPE2_CHANNEL_RXADAPTSELTEST2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX22_6->GTPE2_CHANNEL_TXPIPPMSTEPSIZE4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT0->GTPE2_LOGIC_OUTS_B9_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_7->GTPE2_CHANNEL_TXPRECURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX45_5->GTPE2_CHANNEL_DRPDI9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX32_9->GTPE2_CHANNEL_RXOSINTSTROBE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTSTROBE" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA9->GTPE2_LOGIC_OUTS_B2_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX28_10->GTPE2_CHANNEL_RXOSINTID01": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID01" + }, + "GTP_CHANNEL_2.GTPE2_IMUX46_1->GTPE2_CHANNEL_RXPCSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPCSRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B15_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX23_5->GTPE2_CHANNEL_TXDATA11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA11" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO14->GTPE2_LOGIC_OUTS_B12_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_0->GTPE2_CHANNEL_TXSEQUENCE6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX10_6->GTPE2_CHANNEL_DRPDI1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX1_0->GTPE2_CHANNEL_RXCHBONDLEVEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX28_8->GTPE2_CHANNEL_RXPD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPD1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO8->GTPE2_LOGIC_OUTS_B12_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX25_5->GTPE2_CHANNEL_PCSRSVDIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX39_6->GTPE2_CHANNEL_TXELECIDLE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXELECIDLE" + }, + "GTP_CHANNEL_2.GTPE2_IMUX38_5->GTPE2_CHANNEL_TXSWING": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSWING" + }, + "GTP_CHANNEL_2.GTPE2_IMUX24_5->GTPE2_CHANNEL_TSTIN14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN14" + }, + "GTP_CHANNEL_2.GTPE2_IMUX44_1->GTPE2_CHANNEL_DMONFIFORESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DMONFIFORESET" + }, + "GTP_CHANNEL_2.GTPE2_CTRL1_10->GTPE2_CHANNEL_RXOOBRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOOBRESET" + }, + "GTP_CHANNEL_2.GTPE2_IMUX23_7->GTPE2_CHANNEL_TXDATA3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX5_0->GTPE2_CHANNEL_RXCHBONDLEVEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_0->GTPE2_CHANNEL_RXSYNCIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCIN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO15->GTPE2_LOGIC_OUTS_B4_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_7" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISK2->GTPE2_LOGIC_OUTS_B12_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA7->GTPE2_LOGIC_OUTS_B5_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX18_9->GTPE2_CHANNEL_RXCHBONDI0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX43_6->GTPE2_CHANNEL_TXRATE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX21_2->GTPE2_CHANNEL_TXDATA23": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA23" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA15->GTPE2_LOGIC_OUTS_B5_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_7" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT9->GTPE2_LOGIC_OUTS_B13_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_9" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCLKCORCNT1->GTPE2_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX38_8->GTPE2_CHANNEL_RXPRBSSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT14->GTPE2_LOGIC_OUTS_B10_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX46_0->GTPE2_CHANNEL_TXPCSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPCSRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA22->GTPE2_LOGIC_OUTS_B1_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_5" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMWAKEDET->GTPE2_LOGIC_OUTS_B12_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMWAKEDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPHALIGNDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX3_1->GTPE2_CHANNEL_TXCOMWAKE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMWAKE" + }, + "GTP_CHANNEL_2.GTPE2_IMUX23_9->GTPE2_CHANNEL_RXCHBONDI3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX3_0->GTPE2_CHANNEL_RXOSINTPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTPD" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT15->GTPE2_LOGIC_OUTS_B15_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_4" + }, + "GTP_CHANNEL_2.GTPE2_CLK0_7->GTPE2_CHANNEL_RXUSRCLK2": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSRCLK2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX39_1->GTPE2_CHANNEL_TXHEADER0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX3_8->GTPE2_CHANNEL_TXPRBSSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX13_6->GTPE2_CHANNEL_DRPDI2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX38_4->GTPE2_CHANNEL_TXMARGIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX35_0->GTPE2_CHANNEL_TXSEQUENCE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO2->GTPE2_LOGIC_OUTS_B4_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT2->GTPE2_LOGIC_OUTS_B9_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX12_5->GTPE2_CHANNEL_TXDLYOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXSYNCOUT->GTPE2_LOGIC_OUTS_B14_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXSYNCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX3_2->GTPE2_CHANNEL_PMARSVDIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX5_8->GTPE2_CHANNEL_TXOUTCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX45_4->GTPE2_CHANNEL_TSTIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX25_9->GTPE2_CHANNEL_PCSRSVDIN6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_8->GTPE2_CHANNEL_TXPRBSSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX36_7->GTPE2_CHANNEL_RXOSINTNTRLEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTNTRLEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXRATEDONE->GTPE2_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXRATEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX27_0->GTPE2_CHANNEL_TXSEQUENCE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX13_0->GTPE2_CHANNEL_TXSYNCMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCMODE" + }, + "GTP_CHANNEL_2.GTPE2_IMUX30_7->GTPE2_CHANNEL_RXPD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPD0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA17->GTPE2_LOGIC_OUTS_B2_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX43_5->GTPE2_CHANNEL_TXDLYUPDOWN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYUPDOWN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT4->GTPE2_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX5_2->GTPE2_CHANNEL_PMARSVDIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX23_8->GTPE2_CHANNEL_RXPRBSSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCLKCORCNT0->GTPE2_LOGIC_OUTS_B11_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX45_7->GTPE2_CHANNEL_TXPISOPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPISOPD" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFSTATUS1->GTPE2_LOGIC_OUTS_B19_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_10" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDO0->GTPE2_LOGIC_OUTS_B16_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_10" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXPMARESETDONE->GTPE2_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPMARESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT4->GTPE2_LOGIC_OUTS_B9_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX45_6->GTPE2_CHANNEL_DRPDI0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX34_2->GTPE2_CHANNEL_DRPADDR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMMADET->GTPE2_LOGIC_OUTS_B19_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMMADET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_7->GTPE2_CHANNEL_TSTIN6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXRESETDONE->GTPE2_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_4" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO11->GTPE2_LOGIC_OUTS_B1_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX22_5->GTPE2_CHANNEL_TXDATA10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA10" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO13->GTPE2_LOGIC_OUTS_B15_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_8" + }, + "GTP_CHANNEL_2.GTPE2_CTRL1_5->GTPE2_CHANNEL_CFGRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CFGRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT1->GTPE2_LOGIC_OUTS_B9_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_4->GTPE2_CHANNEL_TSTIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO5->GTPE2_LOGIC_OUTS_B12_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX25_10->GTPE2_CHANNEL_PCSRSVDIN7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN7" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA0->GTPE2_LOGIC_OUTS_B6_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_10" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT14->GTPE2_LOGIC_OUTS_B5_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO4->GTPE2_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX37_8->GTPE2_CHANNEL_PMARSVDIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX35_2->GTPE2_CHANNEL_DRPADDR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX28_6->GTPE2_CHANNEL_RXDLYEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX24_7->GTPE2_CHANNEL_TSTIN16": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN16" + }, + "GTP_CHANNEL_2.GTPE2_IMUX15_9->GTPE2_CHANNEL_RXOSINTEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTEN" + }, + "GTP_CHANNEL_2.GTPE2_CTRL1_6->GTPE2_CHANNEL_RXBUFRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXBUFRESET" + }, + "GTP_CHANNEL_2.GTPE2_IMUX39_0->GTPE2_CHANNEL_TXHEADER2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX17_6->GTPE2_CHANNEL_TXDATA5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA5" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTATUS2->GTPE2_LOGIC_OUTS_B23_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX17_9->GTPE2_CHANNEL_RXCHBONDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA13->GTPE2_LOGIC_OUTS_B7_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_7" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA29->GTPE2_LOGIC_OUTS_B7_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT0->GTPE2_LOGIC_OUTS_B5_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_10" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPMARESETDONE->GTPE2_LOGIC_OUTS_B12_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPMARESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX18_3->GTPE2_CHANNEL_TXDATA16": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA16" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA14->GTPE2_LOGIC_OUTS_B1_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX1_9->GTPE2_CHANNEL_RXOSINTHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTHOLD" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBYTEISALIGNED->GTPE2_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBYTEISALIGNED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX14_8->GTPE2_CHANNEL_RXCDROVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDROVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA18->GTPE2_LOGIC_OUTS_B4_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX41_6->GTPE2_CHANNEL_RXPHALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHALIGNEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX15_3->GTPE2_CHANNEL_TX8B10BBYPASS2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS2" + }, + "GTP_CHANNEL_2.GTPE2_CTRL1_9->GTPE2_CHANNEL_RXCDRRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRRESET" + }, + "GTP_CHANNEL_2.GTPE2_IMUX44_5->GTPE2_CHANNEL_TXDLYBYPASS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYBYPASS" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_0->GTPE2_CHANNEL_RXSYNCMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCMODE" + }, + "GTP_CHANNEL_2.GTPE2_IMUX11_3->GTPE2_CHANNEL_TXRATEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATEMODE" + }, + "GTP_CHANNEL_2.GTPE2_IMUX41_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX3_9->GTPE2_CHANNEL_DRPDI7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX27_5->GTPE2_CHANNEL_TXPHINIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHINIT" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISCOMMA1->GTPE2_LOGIC_OUTS_B15_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX44_3->GTPE2_CHANNEL_DRPEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTATUS0->GTPE2_LOGIC_OUTS_B21_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX9_9->GTPE2_CHANNEL_PCSRSVDIN14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN14" + }, + "GTP_CHANNEL_2.GTPE2_IMUX43_9->GTPE2_CHANNEL_LOOPBACK0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHMONITOR3->GTPE2_LOGIC_OUTS_B3_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT3->GTPE2_LOGIC_OUTS_B13_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA6->GTPE2_LOGIC_OUTS_B1_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_9" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA25->GTPE2_LOGIC_OUTS_B2_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_4" + }, + "GTP_CHANNEL_2.GTPE2_CTRL0_7->GTPE2_CHANNEL_RXCDRFREQRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRFREQRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PHYSTATUS->GTPE2_LOGIC_OUTS_B10_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PHYSTATUS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_8->GTPE2_CHANNEL_RXDDIEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDDIEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTARTED->GTPE2_LOGIC_OUTS_B6_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTARTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_7" + }, + "GTP_CHANNEL_2.GTPE2_CTRL0_9->GTPE2_CHANNEL_RXLPMRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMRESET" + }, + "GTP_CHANNEL_2.GTPE2_CLK1_2->GTPE2_CHANNEL_TXPHDLYTSTCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYTSTCLK" + }, + "GTP_CHANNEL_2.GTPE2_IMUX2_5->GTPE2_CHANNEL_TXDIFFCTRL3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX10_3->GTPE2_CHANNEL_TXPIPPMOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX24_3->GTPE2_CHANNEL_TSTIN12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN12" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISK3->GTPE2_LOGIC_OUTS_B12_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_4" + }, + "GTP_CHANNEL_2.GTPE2_CTRL0_6->GTPE2_CHANNEL_RXDLYSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYSRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA1->GTPE2_LOGIC_OUTS_B2_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_2->GTPE2_CHANNEL_RXLPMOSINTNTRLEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTARTOFSEQ0->GTPE2_LOGIC_OUTS_B18_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX26_3->GTPE2_CHANNEL_GTRSVD8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX9_10->GTPE2_CHANNEL_PCSRSVDIN15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN15" + }, + "GTP_CHANNEL_2.GTPE2_IMUX31_1->GTPE2_CHANNEL_TXHEADER1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX45_8->GTPE2_CHANNEL_EYESCANRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX25_4->GTPE2_CHANNEL_PCSRSVDIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_6->GTPE2_CHANNEL_TXPRECURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX20_1->GTPE2_CHANNEL_TXDATA30": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA30" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTROBESTARTED->GTPE2_LOGIC_OUTS_B0_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX27_1->GTPE2_CHANNEL_TXSEQUENCE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX4_3->GTPE2_CHANNEL_TXMAINCURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_2->GTPE2_CHANNEL_TXCHARDISPVAL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX39_2->GTPE2_CHANNEL_DRPADDR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX19_9->GTPE2_CHANNEL_RXCHBONDI1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXOUTCLKPCS->GTPE2_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXOUTCLKPCS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX29_6->GTPE2_CHANNEL_TXCHARDISPMODE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTATUS1->GTPE2_LOGIC_OUTS_B17_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_8" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXHEADERVALID->GTPE2_LOGIC_OUTS_B14_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADERVALID", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX23_3->GTPE2_CHANNEL_TXDATA19": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA19" + }, + "GTP_CHANNEL_2.GTPE2_IMUX38_6->GTPE2_CHANNEL_TXPD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPD0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA21->GTPE2_LOGIC_OUTS_B7_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_5" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISCOMMA2->GTPE2_LOGIC_OUTS_B15_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_5" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO9->GTPE2_LOGIC_OUTS_B4_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX32_6->GTPE2_CHANNEL_DRPDI3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXOSINTSTROBEDONE->GTPE2_LOGIC_OUTS_B0_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX2_7->GTPE2_CHANNEL_RXRATEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATEMODE" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHANBONDSEQ->GTPE2_LOGIC_OUTS_B8_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANBONDSEQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX14_0->GTPE2_CHANNEL_TXPDELECIDLEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPDELECIDLEMODE" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXHEADER2->GTPE2_LOGIC_OUTS_B17_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_6->GTPE2_CHANNEL_TSTIN5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN5" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT10->GTPE2_LOGIC_OUTS_B13_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX28_4->GTPE2_CHANNEL_TXSYSCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX34_6->GTPE2_CHANNEL_DRPDI8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX29_8->GTPE2_CHANNEL_RXOSHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSHOLD" + }, + "GTP_CHANNEL_2.GTPE2_IMUX44_9->GTPE2_CHANNEL_RXCOMMADETEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCOMMADETEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO12->GTPE2_LOGIC_OUTS_B7_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_8" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT8->GTPE2_LOGIC_OUTS_B13_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_8" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT7->GTPE2_LOGIC_OUTS_B9_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX25_7->GTPE2_CHANNEL_PCSRSVDIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN4" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT3->GTPE2_LOGIC_OUTS_B9_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_7" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PLLREFCLK1->GTPE2_CHANNEL_PLL1REFCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLREFCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL1REFCLK" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PLLCLK0->GTPE2_CHANNEL_PLL0CLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL0CLK" + }, + "GTP_CHANNEL_2.GTPE2_IMUX16_1->GTPE2_CHANNEL_TXDATA28": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA28" }, "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA3->GTPE2_LOGIC_OUTS_B0_10": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_10", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_RXDATA3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_5->GTPE2_CHANNEL_GTRSVD2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD2" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT5->GTPE2_LOGIC_OUTS_B13_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX3_3->GTPE2_CHANNEL_TXSTARTSEQ": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSTARTSEQ" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHSLIPMONITOR2->GTPE2_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_0" + }, + "GTP_CHANNEL_2.GTPE2_CTRL1_4->GTPE2_CHANNEL_RXPHDLYRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHDLYRESET" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXRESETDONE->GTPE2_LOGIC_OUTS_B18_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX37_10->GTPE2_CHANNEL_DRPDI12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI12" + }, + "GTP_CHANNEL_2.GTPE2_IMUX2_10->GTPE2_CHANNEL_RXOUTCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX6_10->GTPE2_CHANNEL_RXOSINTCFG1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMINITDET->GTPE2_LOGIC_OUTS_B20_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMINITDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX0_7->GTPE2_CHANNEL_RXADAPTSELTEST0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX36_2->GTPE2_CHANNEL_RXSYNCALLIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCALLIN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX18_5->GTPE2_CHANNEL_TXDATA8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX0_9->GTPE2_CHANNEL_RXOSINTOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX40_8->GTPE2_CHANNEL_TSTIN7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN7" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSTARTOFSEQ1->GTPE2_LOGIC_OUTS_B11_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_10" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT6->GTPE2_LOGIC_OUTS_B13_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_4->GTPE2_CHANNEL_GTRSVD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX25_2->GTPE2_CHANNEL_TXPHALIGN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHALIGN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX26_4->GTPE2_CHANNEL_GTRSVD9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD9" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFSTATUS0->GTPE2_LOGIC_OUTS_B23_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX20_2->GTPE2_CHANNEL_TXDATA22": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA22" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA12->GTPE2_LOGIC_OUTS_B3_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_7" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISCOMMA0->GTPE2_LOGIC_OUTS_B15_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX41_7->GTPE2_CHANNEL_RXADAPTSELTEST6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCDRLOCK->GTPE2_LOGIC_OUTS_B17_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCDRLOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_5" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISK0->GTPE2_LOGIC_OUTS_B12_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_10" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHSLIPMONITOR4->GTPE2_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX32_2->GTPE2_CHANNEL_TXINHIBIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXINHIBIT" + }, + "GTP_CHANNEL_2.GTPE2_IMUX14_1->GTPE2_CHANNEL_TXPRBSFORCEERR": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSFORCEERR" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_3->GTPE2_CHANNEL_GTRSVD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX11_5->GTPE2_CHANNEL_TXDLYHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYHOLD" + }, + "GTP_CHANNEL_2.GTPE2_IMUX46_9->GTPE2_CHANNEL_LOOPBACK1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT8->GTPE2_LOGIC_OUTS_B21_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_7" + }, + "GTP_CHANNEL_2.GTPE2_CLK1_8->GTPE2_CHANNEL_CLKRSVD1": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CLKRSVD1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX16_4->GTPE2_CHANNEL_TXDATA12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA12" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_EYESCANDATAERROR->GTPE2_LOGIC_OUTS_B18_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_EYESCANDATAERROR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHARISK1->GTPE2_LOGIC_OUTS_B12_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX24_10->GTPE2_CHANNEL_TSTIN19": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN19" + }, + "GTP_CHANNEL_2.GTPE2_IMUX26_7->GTPE2_CHANNEL_GTRSVD12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD12" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCHBONDO1->GTPE2_LOGIC_OUTS_B16_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_9" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDISPERR0->GTPE2_LOGIC_OUTS_B22_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_10" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_GTRXOUTCLK_2->GTPE2_CHANNEL_RXOUTCLK_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_GTRXOUTCLK_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLK_2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX13_10->GTPE2_CHANNEL_RXPRBSCNTRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSCNTRESET" + }, + "GTP_CHANNEL_2.GTPE2_IMUX46_3->GTPE2_CHANNEL_TXPIPPMPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMPD" + }, + "GTP_CHANNEL_2.GTPE2_IMUX46_6->GTPE2_CHANNEL_TXRATE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX19_5->GTPE2_CHANNEL_TXDATA9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX11_10->GTPE2_CHANNEL_RXOSINTID03": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID03" + }, + "GTP_CHANNEL_2.GTPE2_IMUX14_6->GTPE2_CHANNEL_RXRATE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX9_7->GTPE2_CHANNEL_PCSRSVDIN12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN12" + }, + "GTP_CHANNEL_2.GTPE2_IMUX17_10->GTPE2_CHANNEL_DRPDI14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI14" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_1->GTPE2_CHANNEL_RXSLIDE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSLIDE" + }, + "GTP_CHANNEL_2.GTPE2_IMUX30_9->GTPE2_CHANNEL_RXCHBONDMASTER": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDMASTER" + }, + "GTP_CHANNEL_2.GTPE2_IMUX41_1->GTPE2_CHANNEL_RXMCOMMAALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXMCOMMAALIGNEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDISPERR3->GTPE2_LOGIC_OUTS_B22_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_9->GTPE2_CHANNEL_GTRSVD6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_6->GTPE2_CHANNEL_GTRSVD3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX3_6->GTPE2_CHANNEL_TXPRECURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX37_3->GTPE2_CHANNEL_TXPHDLYPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYPD" + }, + "GTP_CHANNEL_2.GTPE2_IMUX25_8->GTPE2_CHANNEL_PCSRSVDIN5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX2_1->GTPE2_CHANNEL_TXCOMINIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMINIT" + }, + "GTP_CHANNEL_2.GTPE2_IMUX32_5->GTPE2_CHANNEL_DRPDI11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI11" + }, + "GTP_CHANNEL_2.GTPE2_IMUX4_0->GTPE2_CHANNEL_RXCHBONDLEVEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX12_3->GTPE2_CHANNEL_TXCHARDISPMODE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX33_2->GTPE2_CHANNEL_TXPHALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX33_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHALIGNEN" + }, + "GTP_CHANNEL_2.GTPE2_CLK0_5->GTPE2_CHANNEL_TXUSRCLK2": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSRCLK2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_2->GTPE2_CHANNEL_RXSYSCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPRBSERR->GTPE2_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPRBSERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA26->GTPE2_LOGIC_OUTS_B4_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_0->GTPE2_CHANNEL_TXPIPPMEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXN->GTPE2_CHANNEL_TXN_PAD": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXN_PAD" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFSTATUS1->GTPE2_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX5_7->GTPE2_CHANNEL_RXADAPTSELTEST3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT5->GTPE2_LOGIC_OUTS_B9_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX44_7->GTPE2_CHANNEL_RXADAPTSELTEST7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST7" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXDLYSRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX9_4->GTPE2_CHANNEL_PCSRSVDIN9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX31_8->GTPE2_CHANNEL_EYESCANTRIGGER": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANTRIGGER" + }, + "GTP_CHANNEL_2.GTPE2_IMUX28_5->GTPE2_CHANNEL_TXSYSCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX41_5->GTPE2_CHANNEL_RESETOVRD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RESETOVRD" + }, + "GTP_CHANNEL_2.GTPE2_IMUX13_4->GTPE2_CHANNEL_TSTIN10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX15_6->GTPE2_CHANNEL_RXRATE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX25_6->GTPE2_CHANNEL_PCSRSVDIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX0_3->GTPE2_CHANNEL_TXMAINCURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA20->GTPE2_LOGIC_OUTS_B3_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX27_10->GTPE2_CHANNEL_RXLPMHFOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMHFOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX2_4->GTPE2_CHANNEL_TXPOSTCURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR3" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATAVALID1->GTPE2_LOGIC_OUTS_B5_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATAVALID1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_1" + }, + "GTP_CHANNEL_2.GTPE2_IMUX43_10->GTPE2_CHANNEL_RXLPMHFHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMHFHOLD" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO6->GTPE2_LOGIC_OUTS_B22_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX34_7->GTPE2_CHANNEL_RXADAPTSELTEST4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST4" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT2->GTPE2_LOGIC_OUTS_B13_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX5_3->GTPE2_CHANNEL_TXMAINCURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_5->GTPE2_CHANNEL_TXDIFFCTRL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT9->GTPE2_LOGIC_OUTS_B21_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBYTEREALIGN->GTPE2_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBYTEREALIGN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX44_10->GTPE2_CHANNEL_TXDATA26": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA26" + }, + "GTP_CHANNEL_2.GTPE2_IMUX21_4->GTPE2_CHANNEL_TXDATA15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA15" + }, + "GTP_CHANNEL_2.GTPE2_IMUX22_3->GTPE2_CHANNEL_TXDATA18": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA18" + }, + "GTP_CHANNEL_2.GTPE2_IMUX0_2->GTPE2_CHANNEL_TX8B10BEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO1->GTPE2_LOGIC_OUTS_B22_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_6->GTPE2_CHANNEL_TXCHARDISPVAL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_PCSRSVDOUT11->GTPE2_LOGIC_OUTS_B5_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_8" + }, + "GTP_CHANNEL_2.GTPE2_IMUX42_8->GTPE2_CHANNEL_GTRSVD5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX26_6->GTPE2_CHANNEL_GTRSVD11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD11" + }, + "GTP_CHANNEL_2.GTPE2_IMUX31_3->GTPE2_CHANNEL_TXCHARISK2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX21_1->GTPE2_CHANNEL_TXDATA31": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA31" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXBUFSTATUS2->GTPE2_LOGIC_OUTS_B17_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX15_7->GTPE2_CHANNEL_TX8B10BBYPASS0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_3->GTPE2_CHANNEL_TXPIPPMSEL": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSEL" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXSYNCOUT->GTPE2_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSYNCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXVALID->GTPE2_LOGIC_OUTS_B20_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXVALID", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_9" + }, + "GTP_CHANNEL_2.GTPE2_IMUX2_6->GTPE2_CHANNEL_TXPRECURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR3" + }, + "GTP_CHANNEL_2.GTPE2_IMUX5_9->GTPE2_CHANNEL_RXOSINTTESTOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX45_0->GTPE2_CHANNEL_RXDFEXYDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDFEXYDEN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX45_1->GTPE2_CHANNEL_RX8B10BEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RX8B10BEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DMONITOROUT13->GTPE2_LOGIC_OUTS_B1_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_6" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXELECIDLE->GTPE2_LOGIC_OUTS_B19_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_8" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA19->GTPE2_LOGIC_OUTS_B0_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_6" + }, + "GTP_CHANNEL_2.GTPE2_IMUX29_4->GTPE2_CHANNEL_TXCHARDISPMODE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXCOMSASDET->GTPE2_LOGIC_OUTS_B18_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMSASDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_7" + }, + "GTP_CHANNEL_2.GTPE2_IMUX38_3->GTPE2_CHANNEL_DRPADDR5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX38_9->GTPE2_CHANNEL_DRPDI5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX13_7->GTPE2_CHANNEL_TXBUFDIFFCTRL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL1" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDATA23->GTPE2_LOGIC_OUTS_B5_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_1->GTPE2_CHANNEL_TXSYNCIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCIN" + }, + "GTP_CHANNEL_2.GTPE2_IMUX17_2->GTPE2_CHANNEL_TXDATA21": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA21" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXBUFSTATUS0->GTPE2_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_2" + }, + "GTP_CHANNEL_2.GTPE2_IMUX14_5->GTPE2_CHANNEL_TXDLYEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYEN" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPRDY->GTPE2_LOGIC_OUTS_B14_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX33_5->GTPE2_CHANNEL_DRPDI10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX33_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI10" + }, + "GTP_CHANNEL_2.GTPE2_IMUX32_7->GTPE2_CHANNEL_TXPRECURSORINV": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSORINV" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_TXP->GTPE2_CHANNEL_TXP_PAD": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXP_PAD" + }, + "GTP_CHANNEL_2.GTPE2_IMUX7_4->GTPE2_CHANNEL_TXPOSTCURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR0" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_DRPDO7->GTPE2_LOGIC_OUTS_B4_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_5" + }, + "GTP_CHANNEL_2.GTPE2_IMUX5_4->GTPE2_CHANNEL_TXMAINCURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX26_8->GTPE2_CHANNEL_GTRSVD13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD13" + }, + "GTP_CHANNEL_2.GTPE2_IMUX16_2->GTPE2_CHANNEL_TXDATA20": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA20" + }, + "GTP_CHANNEL_2.GTPE2_CTRL1_7->GTPE2_CHANNEL_RXPMARESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPMARESET" + }, + "GTP_CHANNEL_2.GTPE2_IMUX18_7->GTPE2_CHANNEL_TXDATA0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX27_8->GTPE2_CHANNEL_TXCOMSAS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMSAS" + }, + "GTP_CHANNEL_2.GTPE2_IMUX16_0->GTPE2_CHANNEL_TXSEQUENCE5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE5" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDLYSRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_0" + }, + "GTP_CHANNEL_2.GTPE2_IMUX9_6->GTPE2_CHANNEL_PCSRSVDIN11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN11" + }, + "GTP_CHANNEL_2.GTPE2_CHANNEL_RXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHALIGNDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_4" + }, + "GTP_CHANNEL_2.GTPE2_IMUX8_4->GTPE2_CHANNEL_TXCHARDISPVAL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL1" } }, - "tile_type": "GTP_CHANNEL_2" + "wires": [ + "GTPE2_IMUX5_7", + "GTPE2_IMUX14_1", + "GTPE2_BYP0_6", + "GTPE2_IMUX23_2", + "GTPE2_BYP0_5", + "GTPE2_IMUX19_10", + "GTPE2_LOGIC_OUTS_B20_6", + "GTPE2_LOGIC_OUTS_B13_0", + "GTPE2_IMUX25_9", + "GTPE2_IMUX18_8", + "GTPE2_IMUX44_3", + "GTPE2_LOGIC_OUTS_B20_10", + "GTPE2_LOGIC_OUTS_B11_9", + "GTPE2_BYP1_10", + "GTPE2_IMUX26_0", + "GTPE2_LOGIC_OUTS_B19_5", + "GTPE2_IMUX5_2", + "GTPE2_CHANNEL_RXOSINTCFG3", + "GTPE2_IMUX30_3", + "GTPE2_CHANNEL_TXSEQUENCE6", + "GTPE2_LOGIC_OUTS_B9_4", + "GTPE2_IMUX18_1", + "GTPE2_CLK0_4", + "GTPE2_CHANNEL_DMONITOROUT2", + "GTPE2_IMUX42_3", + "GTPE2_CTRL1_5", + "GTPE2_IMUX22_3", + "GTPE2_CHANNEL_GTRSVD5", + "GTPE2_CHANNEL_RXLPMRESET", + "GTPE2_LOGIC_OUTS_B23_8", + "GTPE2_CHANNEL_TXPRBSFORCEERR", + "GTPE2_LOGIC_OUTS_B1_9", + "GTPE2_IMUX45_9", + "GTPE2_IMUX34_7", + "GTPE2_LOGIC_OUTS_B2_0", + "GTPE2_IMUX24_9", + "GTPE2_LOGIC_OUTS_B18_2", + "GTPE2_CLK1_1", + "GTPE2_CHANNEL_RXPOLARITY", + "GTPE2_CHANNEL_TSTIN14", + "GTPE2_LOGIC_OUTS_B22_9", + "GTPE2_CHANNEL_PCSRSVDOUT5", + "GTPE2_LOGIC_OUTS_B8_6", + "GTPE2_IMUX23_4", + "GTPE2_LOGIC_OUTS_B22_10", + "GTPE2_LOGIC_OUTS_B6_9", + "GTPE2_IMUX33_7", + "GTPE2_CHANNEL_RXRATE0", + "GTPE2_FAN5_8", + "GTPE2_IMUX25_3", + "GTPE2_IMUX23_5", + "GTPE2_BYP5_10", + "GTPE2_IMUX19_6", + "GTPE2_CHANNEL_RXP", + "GTPE2_CHANNEL_TXDATA11", + "GTPE2_FAN7_2", + "GTPE2_CHANNEL_TSTPDOVRDB", + "GTPE2_CHANNEL_RXOUTCLKSEL2", + "GTPE2_CHANNEL_RXSYNCALLIN", + "GTPE2_FAN3_3", + "GTPE2_CHANNEL_DRPDO6", + "GTPE2_IMUX2_4", + "GTPE2_IMUX37_6", + "GTPE2_IMUX17_2", + "GTPE2_IMUX6_6", + "GTPE2_CHANNEL_TSTCLK1", + "GTPE2_CHANNEL_TXDATA2", + "GTPE2_IMUX0_2", + "GTPE2_IMUX28_0", + "GTPE2_CHANNEL_RXCLKCORCNT1", + "GTPE2_LOGIC_OUTS_B21_1", + "GTPE2_LOGIC_OUTS_B16_9", + "GTPE2_IMUX33_10", + "GTPE2_IMUX42_4", + "GTPE2_CHANNEL_RXOSINTID01", + "GTPE2_IMUX26_8", + "GTPE2_IMUX0_9", + "GTPE2_BYP5_3", + "GTPE2_IMUX38_1", + "GTPE2_CHANNEL_RXSYNCMODE", + "GTPE2_FAN7_10", + "GTPE2_IMUX22_4", + "GTPE2_IMUX43_1", + "GTPE2_CHANNEL_RXDATA9", + "GTPE2_IMUX9_5", + "GTPE2_BYP1_3", + "GTPE2_CHANNEL_DMONFIFORESET", + "GTPE2_CHANNEL_DMONITOROUT11", + "GTPE2_IMUX16_3", + "GTPE2_CHANNEL_TXSEQUENCE3", + "GTPE2_CHANNEL_RXCHBONDI2", + "GTPE2_IMUX0_4", + "GTPE2_IMUX24_2", + "GTPE2_IMUX3_2", + "GTPE2_LOGIC_OUTS_B6_8", + "GTPE2_LOGIC_OUTS_B4_10", + "GTPE2_CHANNEL_RXSYNCOUT", + "GTPE2_LOGIC_OUTS_B13_10", + "GTPE2_IMUX34_8", + "GTPE2_LOGIC_OUTS_B0_1", + "GTPE2_IMUX40_6", + "GTPE2_IMUX7_0", + "GTPE2_IMUX34_9", + "GTPE2_IMUX26_10", + "GTPE2_IMUX37_7", + "GTPE2_CHANNEL_RXPRBSSEL1", + "GTPE2_IMUX19_1", + "GTPE2_CHANNEL_RXNOTINTABLE1", + "GTPE2_IMUX29_0", + "GTPE2_LOGIC_OUTS_B18_1", + "GTPE2_CHANNEL_PLLREFCLK1", + "GTPE2_IMUX37_0", + "GTPE2_FAN6_8", + "GTPE2_CHANNEL_TXSYNCMODE", + "GTPE2_CHANNEL_RXPHMONITOR4", + "GTPE2_CHANNEL_DRPDI10", + "GTPE2_IMUX20_8", + "GTPE2_LOGIC_OUTS_B5_3", + "GTPE2_LOGIC_OUTS_B9_10", + "GTPE2_CHANNEL_PMASCANIN0", + "GTPE2_CHANNEL_EYESCANTRIGGER", + "GTPE2_BYP0_3", + "GTPE2_FAN6_2", + "GTPE2_CTRL0_3", + "GTPE2_CHANNEL_RXDATA19", + "GTPE2_CTRL1_1", + "GTPE2_CHANNEL_PCSRSVDIN9", + "GTPE2_IMUX17_6", + "GTPE2_CHANNEL_DRPADDR5", + "GTPE2_CHANNEL_TSTIN2", + "GTPE2_IMUX25_10", + "GTPE2_LOGIC_OUTS_B5_9", + "GTPE2_IMUX16_4", + "GTPE2_LOGIC_OUTS_B10_5", + "GTPE2_LOGIC_OUTS_B18_7", + "GTPE2_IMUX11_9", + "GTPE2_CHANNEL_RXDATA4", + "GTPE2_IMUX13_7", + "GTPE2_CHANNEL_GTTXOUTCLK_2", + "GTPE2_IMUX9_0", + "GTPE2_LOGIC_OUTS_B14_3", + "GTPE2_CHANNEL_RXDATA2", + "GTPE2_IMUX2_1", + "GTPE2_CHANNEL_RXCHBONDO3", + "GTPE2_IMUX24_10", + "GTPE2_FAN1_1", + "GTPE2_CHANNEL_TXDLYOVRDEN", + "GTPE2_CHANNEL_TXDATA0", + "GTPE2_BYP3_6", + "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "GTPE2_IMUX42_5", + "GTPE2_CHANNEL_PMASCANMODEB", + "GTPE2_BYP0_4", + "GTPE2_LOGIC_OUTS_B12_9", + "GTPE2_CHANNEL_RXDATA25", + "GTPE2_CHANNEL_RXOSCALRESET", + "GTPE2_IMUX10_9", + "GTPE2_CTRL0_6", + "GTPE2_IMUX41_10", + "GTPE2_CLK1_6", + "GTPE2_IMUX8_10", + "GTPE2_IMUX14_3", + "GTPE2_CHANNEL_RXGEARBOXSLIP", + "GTPE2_CHANNEL_GTRSVD2", + "GTPE2_IMUX36_6", + "GTPE2_CHANNEL_TXCOMFINISH", + "GTPE2_CTRL1_10", + "GTPE2_IMUX2_7", + "GTPE2_CHANNEL_PCSRSVDOUT10", + "GTPE2_IMUX13_5", + "GTPE2_CHANNEL_GTRSVD14", + "GTPE2_LOGIC_OUTS_B16_1", + "GTPE2_BYP4_6", + "GTPE2_CHANNEL_RXOSINTHOLD", + "GTPE2_IMUX34_2", + "GTPE2_LOGIC_OUTS_B20_9", + "GTPE2_IMUX22_10", + "GTPE2_IMUX9_9", + "GTPE2_CHANNEL_RXSLIDE", + "GTPE2_CLK1_0", + "GTPE2_IMUX41_2", + "GTPE2_LOGIC_OUTS_B0_7", + "GTPE2_CHANNEL_RXADAPTSELTEST5", + "GTPE2_FAN4_5", + "GTPE2_FAN3_4", + "GTPE2_CHANNEL_RXCHBONDI1", + "GTPE2_CHANNEL_RXRESETDONE", + "GTPE2_CHANNEL_TXCOMSAS", + "GTPE2_IMUX20_4", + "GTPE2_IMUX25_7", + "GTPE2_FAN3_9", + "GTPE2_CHANNEL_RXCHBONDEN", + "GTPE2_IMUX1_9", + "GTPE2_BYP1_8", + "GTPE2_IMUX29_5", + "GTPE2_LOGIC_OUTS_B1_0", + "GTPE2_CHANNEL_TXMAINCURSOR2", + "GTPE2_CTRL1_6", + "GTPE2_IMUX32_4", + "GTPE2_LOGIC_OUTS_B6_2", + "GTPE2_CHANNEL_RXOSINTID02", + "GTPE2_CHANNEL_GTRSVD10", + "GTPE2_BYP4_5", + "GTPE2_IMUX35_6", + "GTPE2_IMUX36_10", + "GTPE2_IMUX31_9", + "GTPE2_IMUX1_7", + "GTPE2_CHANNEL_TXHEADER1", + "GTPE2_IMUX27_6", + "GTPE2_CHANNEL_DMONITOROUT1", + "GTPE2_IMUX26_1", + "GTPE2_IMUX25_4", + "GTPE2_IMUX15_5", + "GTPE2_CHANNEL_PCSRSVDOUT4", + "GTPE2_IMUX30_6", + "GTPE2_BYP3_0", + "GTPE2_CHANNEL_DRPDO0", + "GTPE2_IMUX36_9", + "GTPE2_CHANNEL_DRPDI8", + "GTPE2_IMUX38_7", + "GTPE2_BYP5_2", + "GTPE2_BYP7_0", + "GTPE2_CHANNEL_DRPADDR6", + "GTPE2_LOGIC_OUTS_B7_7", + "GTPE2_LOGIC_OUTS_B13_3", + "GTPE2_LOGIC_OUTS_B2_6", + "GTPE2_CHANNEL_RXOSINTID00", + "GTPE2_FAN0_2", + "GTPE2_CHANNEL_TXUSRCLK", + "GTPE2_CHANNEL_RXPD0", + "GTPE2_IMUX0_7", + "GTPE2_IMUX33_5", + "GTPE2_LOGIC_OUTS_B20_8", + "GTPE2_LOGIC_OUTS_B6_10", + "GTPE2_LOGIC_OUTS_B12_4", + "GTPE2_IMUX16_8", + "GTPE2_CHANNEL_RXDISPERR1", + "GTPE2_LOGIC_OUTS_B3_4", + "GTPE2_CLK1_5", + "GTPE2_CHANNEL_TXDATA19", + "GTPE2_IMUX22_8", + "GTPE2_IMUX30_7", + "GTPE2_FAN6_5", + "GTPE2_CHANNEL_RXPHMONITOR3", + "GTPE2_CHANNEL_TXMAINCURSOR4", + "GTPE2_CHANNEL_PMARSVDIN1", + "GTPE2_BYP3_8", + "GTPE2_CHANNEL_RXBUFSTATUS1", + "GTPE2_CHANNEL_RXHEADER1", + "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "GTPE2_CLK0_1", + "GTPE2_LOGIC_OUTS_B6_7", + "GTPE2_BYP3_4", + "GTPE2_CHANNEL_TXMARGIN2", + "GTPE2_IMUX40_2", + "GTPE2_LOGIC_OUTS_B6_6", + "GTPE2_IMUX26_4", + "GTPE2_CHANNEL_TXPHINIT", + "GTPE2_LOGIC_OUTS_B15_5", + "GTPE2_FAN3_5", + "GTPE2_IMUX11_8", + "GTPE2_FAN0_8", + "GTPE2_IMUX12_3", + "GTPE2_CHANNEL_TXP_PAD", + "GTPE2_IMUX3_0", + "GTPE2_IMUX5_8", + "GTPE2_LOGIC_OUTS_B3_5", + "GTPE2_IMUX34_10", + "GTPE2_IMUX46_2", + "GTPE2_CHANNEL_PLL0CLK", + "GTPE2_CHANNEL_TXCHARDISPVAL2", + "GTPE2_CHANNEL_TXPISOPD", + "GTPE2_CHANNEL_TX8B10BBYPASS3", + "GTPE2_IMUX46_0", + "GTPE2_BYP2_9", + "GTPE2_CHANNEL_TSTIN16", + "GTPE2_CHANNEL_GTRSVD7", + "GTPE2_FAN6_9", + "GTPE2_IMUX3_5", + "GTPE2_LOGIC_OUTS_B15_7", + "GTPE2_IMUX41_4", + "GTPE2_CHANNEL_RXLPMHFHOLD", + "GTPE2_IMUX23_9", + "GTPE2_CHANNEL_PCSRSVDIN5", + "GTPE2_CHANNEL_SCANIN0", + "GTPE2_LOGIC_OUTS_B13_2", + "GTPE2_IMUX8_5", + "GTPE2_IMUX39_0", + "GTPE2_IMUX42_10", + "GTPE2_IMUX14_2", + "GTPE2_CHANNEL_TXDATA24", + "GTPE2_BYP1_6", + "GTPE2_IMUX28_10", + "GTPE2_FAN5_6", + "GTPE2_BYP2_3", + "GTPE2_CHANNEL_RXDATA14", + "GTPE2_IMUX24_6", + "GTPE2_CHANNEL_RXOSINTNTRLEN", + "GTPE2_LOGIC_OUTS_B1_5", + "GTPE2_LOGIC_OUTS_B8_5", + "GTPE2_LOGIC_OUTS_B3_8", + "GTPE2_IMUX9_7", + "GTPE2_IMUX9_1", + "GTPE2_IMUX44_6", + "GTPE2_CHANNEL_TXDATA12", + "GTPE2_LOGIC_OUTS_B23_5", + "GTPE2_CHANNEL_PLLCLK0", + "GTPE2_CHANNEL_TXSEQUENCE0", + "GTPE2_CHANNEL_RXELECIDLE", + "GTPE2_CHANNEL_SIGVALIDCLK", + "GTPE2_CHANNEL_TXSEQUENCE2", + "GTPE2_FAN4_7", + "GTPE2_IMUX46_4", + "GTPE2_LOGIC_OUTS_B20_1", + "GTPE2_CHANNEL_RXOSINTCFG2", + "GTPE2_LOGIC_OUTS_B19_7", + "GTPE2_IMUX22_7", + "GTPE2_LOGIC_OUTS_B2_9", + "GTPE2_IMUX31_4", + "GTPE2_IMUX8_4", + "GTPE2_IMUX26_2", + "GTPE2_FAN1_10", + "GTPE2_LOGIC_OUTS_B18_0", + "GTPE2_CHANNEL_TXRATEMODE", + "GTPE2_CHANNEL_RXOSINTCFG1", + "GTPE2_CLK1_4", + "GTPE2_IMUX2_3", + "GTPE2_CHANNEL_RXSYSCLKSEL0", + "GTPE2_CHANNEL_TXCHARISK3", + "GTPE2_LOGIC_OUTS_B4_0", + "GTPE2_IMUX7_3", + "GTPE2_IMUX21_1", + "GTPE2_BYP2_8", + "GTPE2_IMUX11_4", + "GTPE2_LOGIC_OUTS_B0_10", + "GTPE2_IMUX27_3", + "GTPE2_FAN0_9", + "GTPE2_CHANNEL_DRPDI12", + "GTPE2_LOGIC_OUTS_B21_5", + "GTPE2_CHANNEL_RXDDIEN", + "GTPE2_FAN7_0", + "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "GTPE2_CHANNEL_PCSRSVDIN8", + "GTPE2_BYP4_7", + "GTPE2_LOGIC_OUTS_B19_6", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", + "GTPE2_CHANNEL_TXSEQUENCE1", + "GTPE2_IMUX29_7", + "GTPE2_LOGIC_OUTS_B10_8", + "GTPE2_LOGIC_OUTS_B20_0", + "GTPE2_IMUX24_8", + "GTPE2_CHANNEL_RXRATEMODE", + "GTPE2_IMUX46_3", + "GTPE2_LOGIC_OUTS_B10_0", + "GTPE2_LOGIC_OUTS_B22_5", + "GTPE2_IMUX37_8", + "GTPE2_FAN7_4", + "GTPE2_IMUX44_0", + "GTPE2_LOGIC_OUTS_B21_8", + "GTPE2_CHANNEL_DRPADDR0", + "GTPE2_CHANNEL_LOOPBACK0", + "GTPE2_CHANNEL_TXPIPPMSEL", + "GTPE2_CHANNEL_PCSRSVDOUT11", + "GTPE2_BYP6_9", + "GTPE2_LOGIC_OUTS_B0_6", + "GTPE2_LOGIC_OUTS_B5_10", + "GTPE2_IMUX38_5", + "GTPE2_LOGIC_OUTS_B1_1", + "GTPE2_IMUX10_10", + "GTPE2_LOGIC_OUTS_B18_9", + "GTPE2_IMUX2_6", + "GTPE2_IMUX45_6", + "GTPE2_CHANNEL_RXBYTEISALIGNED", + "GTPE2_CHANNEL_RXDATA17", + "GTPE2_BYP2_0", + "GTPE2_FAN0_1", + "GTPE2_IMUX28_1", + "GTPE2_CHANNEL_RXUSRCLK2", + "GTPE2_CHANNEL_DRPDO15", + "GTPE2_CHANNEL_RXDATA26", + "GTPE2_IMUX4_7", + "GTPE2_IMUX27_5", + "GTPE2_BYP7_7", + "GTPE2_CHANNEL_TXDATA8", + "GTPE2_IMUX44_2", + "GTPE2_IMUX44_10", + "GTPE2_FAN2_6", + "GTPE2_CHANNEL_TXDATA26", + "GTPE2_CHANNEL_TXPCSRESET", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", + "GTPE2_IMUX35_7", + "GTPE2_IMUX45_7", + "GTPE2_CHANNEL_TXRUNDISP1", + "GTPE2_BYP6_1", + "GTPE2_IMUX16_0", + "GTPE2_IMUX30_9", + "GTPE2_IMUX31_6", + "GTPE2_LOGIC_OUTS_B19_0", + "GTPE2_CHANNEL_RXNOTINTABLE2", + "GTPE2_LOGIC_OUTS_B14_7", + "GTPE2_IMUX8_2", + "GTPE2_LOGIC_OUTS_B21_7", + "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", + "GTPE2_CHANNEL_PCSRSVDOUT12", + "GTPE2_CHANNEL_RXOUTCLK_2", + "GTPE2_CHANNEL_RXELECIDLEMODE0", + "GTPE2_FAN2_7", + "GTPE2_LOGIC_OUTS_B22_6", + "GTPE2_CHANNEL_TXPHOVRDEN", + "GTPE2_CHANNEL_RXUSERRDY", + "GTPE2_CHANNEL_PMASCANIN1", + "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "GTPE2_LOGIC_OUTS_B0_3", + "GTPE2_CHANNEL_RXADAPTSELTEST8", + "GTPE2_LOGIC_OUTS_B20_3", + "GTPE2_IMUX6_1", + "GTPE2_IMUX45_1", + "GTPE2_LOGIC_OUTS_B7_10", + "GTPE2_IMUX16_9", + "GTPE2_LOGIC_OUTS_B9_3", + "GTPE2_LOGIC_OUTS_B10_1", + "GTPE2_CHANNEL_TXPHALIGNEN", + "GTPE2_IMUX1_5", + "GTPE2_FAN0_4", + "GTPE2_LOGIC_OUTS_B17_7", + "GTPE2_CTRL0_1", + "GTPE2_BYP6_3", + "GTPE2_BYP5_1", + "GTPE2_LOGIC_OUTS_B10_6", + "GTPE2_FAN7_7", + "GTPE2_CHANNEL_PLL1REFCLK", + "GTPE2_IMUX18_7", + "GTPE2_BYP2_10", + "GTPE2_CHANNEL_RXCOMSASDET", + "GTPE2_LOGIC_OUTS_B19_4", + "GTPE2_IMUX35_5", + "GTPE2_CHANNEL_PCSRSVDOUT2", + "GTPE2_CHANNEL_TXPOSTCURSOR0", + "GTPE2_CHANNEL_TXPDELECIDLEMODE", + "GTPE2_BYP7_2", + "GTPE2_CHANNEL_DRPDI14", + "GTPE2_CHANNEL_TSTIN0", + "GTPE2_CHANNEL_CLKRSVD1", + "GTPE2_IMUX25_0", + "GTPE2_LOGIC_OUTS_B10_4", + "GTPE2_IMUX33_9", + "GTPE2_CHANNEL_TSTPD1", + "GTPE2_CHANNEL_TSTIN18", + "GTPE2_CHANNEL_TXHEADER0", + "GTPE2_IMUX36_8", + "GTPE2_CHANNEL_GTRSVD9", + "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "GTPE2_FAN3_2", + "GTPE2_CHANNEL_GTRSVD6", + "GTPE2_IMUX27_7", + "GTPE2_CHANNEL_DRPDO13", + "GTPE2_CHANNEL_PMARSVDIN4", + "GTPE2_IMUX36_3", + "GTPE2_IMUX29_10", + "GTPE2_IMUX40_9", + "GTPE2_CHANNEL_EYESCANMODE", + "GTPE2_CHANNEL_RXCDRRESETRSV", + "GTPE2_IMUX44_8", + "GTPE2_CHANNEL_PMASCANOUT4", + "GTPE2_CHANNEL_RXDATA3", + "GTPE2_LOGIC_OUTS_B5_0", + "GTPE2_BYP5_0", + "GTPE2_CHANNEL_TX8B10BBYPASS0", + "GTPE2_LOGIC_OUTS_B15_9", + "GTPE2_IMUX0_0", + "GTPE2_IMUX24_3", + "GTPE2_CHANNEL_PMARSVDIN3", + "GTPE2_LOGIC_OUTS_B4_6", + "GTPE2_CHANNEL_RXDATA0", + "GTPE2_IMUX22_1", + "GTPE2_IMUX38_8", + "GTPE2_FAN3_10", + "GTPE2_CHANNEL_TXCOMINIT", + "GTPE2_IMUX15_10", + "GTPE2_IMUX39_4", + "GTPE2_CHANNEL_RXCLKCORCNT0", + "GTPE2_BYP1_1", + "GTPE2_IMUX31_1", + "GTPE2_IMUX20_0", + "GTPE2_BYP0_8", + "GTPE2_IMUX24_0", + "GTPE2_CHANNEL_TXDIFFCTRL0", + "GTPE2_BYP0_9", + "GTPE2_IMUX21_10", + "GTPE2_CHANNEL_TXSYNCDONE", + "GTPE2_CHANNEL_PMASCANIN2", + "GTPE2_LOGIC_OUTS_B8_4", + "GTPE2_CHANNEL_TSTIN3", + "GTPE2_CHANNEL_TXDATA15", + "GTPE2_IMUX13_8", + "GTPE2_IMUX11_3", + "GTPE2_IMUX27_1", + "GTPE2_LOGIC_OUTS_B1_4", + "GTPE2_CHANNEL_TXSEQUENCE4", + "GTPE2_IMUX44_5", + "GTPE2_CTRL0_2", + "GTPE2_LOGIC_OUTS_B18_8", + "GTPE2_CHANNEL_DMONITOROUT9", + "GTPE2_BYP4_0", + "GTPE2_FAN0_10", + "GTPE2_FAN1_2", + "GTPE2_CHANNEL_RXCOMMADET", + "GTPE2_IMUX22_6", + "GTPE2_BYP4_3", + "GTPE2_IMUX42_7", + "GTPE2_CHANNEL_TXSTARTSEQ", + "GTPE2_LOGIC_OUTS_B11_0", + "GTPE2_IMUX44_7", + "GTPE2_CHANNEL_PCSRSVDIN2", + "GTPE2_IMUX30_0", + "GTPE2_LOGIC_OUTS_B23_10", + "GTPE2_IMUX4_1", + "GTPE2_LOGIC_OUTS_B8_2", + "GTPE2_CHANNEL_RXDISPERR3", + "GTPE2_IMUX46_6", + "GTPE2_CTRL0_5", + "GTPE2_CHANNEL_RXCHARISK3", + "GTPE2_IMUX3_7", + "GTPE2_CHANNEL_DRPDO3", + "GTPE2_IMUX17_0", + "GTPE2_LOGIC_OUTS_B6_4", + "GTPE2_FAN2_10", + "GTPE2_CHANNEL_DRPDI0", + "GTPE2_BYP6_4", + "GTPE2_CLK0_5", + "GTPE2_FAN4_0", + "GTPE2_CHANNEL_SCANIN4", + "GTPE2_IMUX4_2", + "GTPE2_IMUX39_6", + "GTPE2_LOGIC_OUTS_B8_9", + "GTPE2_LOGIC_OUTS_B15_8", + "GTPE2_IMUX23_6", + "GTPE2_IMUX9_6", + "GTPE2_IMUX8_9", + "GTPE2_CTRL1_0", + "GTPE2_CLK1_10", + "GTPE2_CHANNEL_RXCDRLOCK", + "GTPE2_CHANNEL_PCSRSVDOUT6", + "GTPE2_IMUX33_0", + "GTPE2_IMUX30_4", + "GTPE2_IMUX43_8", + "GTPE2_CHANNEL_RXDFEXYDEN", + "GTPE2_IMUX32_3", + "GTPE2_IMUX34_1", + "GTPE2_CLK1_8", + "GTPE2_IMUX5_5", + "GTPE2_IMUX19_3", + "GTPE2_CHANNEL_TXMAINCURSOR1", + "GTPE2_IMUX6_0", + "GTPE2_IMUX41_9", + "GTPE2_LOGIC_OUTS_B17_5", + "GTPE2_IMUX41_3", + "GTPE2_LOGIC_OUTS_B7_6", + "GTPE2_CHANNEL_TXPMARESET", + "GTPE2_FAN1_0", + "GTPE2_LOGIC_OUTS_B17_2", + "GTPE2_CLK0_10", + "GTPE2_LOGIC_OUTS_B1_8", + "GTPE2_FAN7_8", + "GTPE2_CHANNEL_DRPADDR2", + "GTPE2_CHANNEL_DRPCLK", + "GTPE2_IMUX10_0", + "GTPE2_CHANNEL_RXCDROVRDEN", + "GTPE2_BYP0_2", + "GTPE2_LOGIC_OUTS_B15_4", + "GTPE2_IMUX10_7", + "GTPE2_FAN4_10", + "GTPE2_LOGIC_OUTS_B9_9", + "GTPE2_LOGIC_OUTS_B15_2", + "GTPE2_CHANNEL_TXOUTCLKSEL1", + "GTPE2_CHANNEL_TXCHARDISPMODE0", + "GTPE2_IMUX20_10", + "GTPE2_CHANNEL_RXHEADERVALID", + "GTPE2_IMUX15_8", + "GTPE2_CLK0_7", + "GTPE2_CHANNEL_RXOSINTDONE", + "GTPE2_CHANNEL_TXRATE1", + "GTPE2_CHANNEL_TXDATA9", + "GTPE2_LOGIC_OUTS_B17_4", + "GTPE2_IMUX29_1", + "GTPE2_IMUX42_0", + "GTPE2_IMUX39_3", + "GTPE2_IMUX18_3", + "GTPE2_LOGIC_OUTS_B12_1", + "GTPE2_LOGIC_OUTS_B21_6", + "GTPE2_CHANNEL_RXOUTCLK_3", + "GTPE2_IMUX26_3", + "GTPE2_LOGIC_OUTS_B6_5", + "GTPE2_IMUX8_3", + "GTPE2_BYP1_2", + "GTPE2_FAN4_6", + "GTPE2_CHANNEL_TXDATA17", + "GTPE2_IMUX29_9", + "GTPE2_BYP7_6", + "GTPE2_IMUX27_2", + "GTPE2_CHANNEL_RXDLYSRESETDONE", + "GTPE2_CHANNEL_TXPIPPMPD", + "GTPE2_IMUX39_8", + "GTPE2_CHANNEL_TSTIN11", + "GTPE2_IMUX6_4", + "GTPE2_BYP4_8", + "GTPE2_LOGIC_OUTS_B12_8", + "GTPE2_CHANNEL_TXPRECURSOR2", + "GTPE2_IMUX39_10", + "GTPE2_LOGIC_OUTS_B7_0", + "GTPE2_IMUX21_5", + "GTPE2_IMUX5_0", + "GTPE2_LOGIC_OUTS_B5_5", + "GTPE2_IMUX38_0", + "GTPE2_LOGIC_OUTS_B7_1", + "GTPE2_IMUX18_0", + "GTPE2_CHANNEL_RXPMARESET", + "GTPE2_IMUX29_4", + "GTPE2_CHANNEL_PCSRSVDOUT0", + "GTPE2_FAN4_2", + "GTPE2_IMUX11_2", + "GTPE2_CHANNEL_RXBUFSTATUS2", + "GTPE2_CHANNEL_GTRSVD0", + "GTPE2_CHANNEL_TXUSRCLK2", + "GTPE2_IMUX24_1", + "GTPE2_CHANNEL_SCANOUT5", + "GTPE2_IMUX15_2", + "GTPE2_LOGIC_OUTS_B7_4", + "GTPE2_CHANNEL_TSTIN17", + "GTPE2_CHANNEL_DMONITOROUT13", + "GTPE2_CTRL1_8", + "GTPE2_CHANNEL_RXCHBONDI0", + "GTPE2_LOGIC_OUTS_B20_4", + "GTPE2_CHANNEL_RXOSINTEN", + "GTPE2_CHANNEL_TXRATEDONE", + "GTPE2_CHANNEL_TXPOLARITY", + "GTPE2_IMUX20_2", + "GTPE2_LOGIC_OUTS_B9_0", + "GTPE2_CHANNEL_TXCHARDISPVAL1", + "GTPE2_CHANNEL_TSTIN7", + "GTPE2_LOGIC_OUTS_B20_5", + "GTPE2_LOGIC_OUTS_B23_6", + "GTPE2_IMUX12_2", + "GTPE2_CHANNEL_RXOSINTPD", + "GTPE2_LOGIC_OUTS_B2_2", + "GTPE2_FAN4_1", + "GTPE2_BYP5_4", + "GTPE2_IMUX36_2", + "GTPE2_CHANNEL_TXDATA5", + "GTPE2_CHANNEL_RXDATA24", + "GTPE2_IMUX33_4", + "GTPE2_CHANNEL_RXDATA21", + "GTPE2_BYP3_9", + "GTPE2_CHANNEL_TXPIPPMEN", + "GTPE2_IMUX17_8", + "GTPE2_IMUX23_7", + "GTPE2_FAN6_0", + "GTPE2_LOGIC_OUTS_B12_5", + "GTPE2_CLK1_9", + "GTPE2_CHANNEL_TXDATA4", + "GTPE2_BYP7_3", + "GTPE2_CHANNEL_RESETOVRD", + "GTPE2_IMUX2_5", + "GTPE2_IMUX10_1", + "GTPE2_LOGIC_OUTS_B9_5", + "GTPE2_IMUX36_4", + "GTPE2_IMUX46_10", + "GTPE2_CHANNEL_RXCDRHOLD", + "GTPE2_IMUX47_6", + "GTPE2_CTRL0_9", + "GTPE2_IMUX10_5", + "GTPE2_CHANNEL_DRPDO5", + "GTPE2_CHANNEL_RXADAPTSELTEST6", + "GTPE2_CHANNEL_RXBUFSTATUS0", + "GTPE2_CHANNEL_TXN_PAD", + "GTPE2_CHANNEL_TXSYNCALLIN", + "GTPE2_IMUX27_10", + "GTPE2_IMUX42_8", + "GTPE2_CHANNEL_RXDLYTESTENB", + "GTPE2_CHANNEL_TXOUTCLK_3", + "GTPE2_IMUX46_5", + "GTPE2_LOGIC_OUTS_B17_8", + "GTPE2_LOGIC_OUTS_B8_0", + "GTPE2_IMUX27_8", + "GTPE2_BYP7_9", + "GTPE2_CHANNEL_RXDATA7", + "GTPE2_CHANNEL_SETERRSTATUS", + "GTPE2_CHANNEL_TXSYNCOUT", + "GTPE2_FAN1_5", + "GTPE2_IMUX30_2", + "GTPE2_CHANNEL_DMONITOROUT0", + "GTPE2_CHANNEL_GTRSVD12", + "GTPE2_BYP6_5", + "GTPE2_LOGIC_OUTS_B2_4", + "GTPE2_IMUX7_6", + "GTPE2_BYP0_10", + "GTPE2_LOGIC_OUTS_B21_4", + "GTPE2_CHANNEL_TSTIN1", + "GTPE2_IMUX7_1", + "GTPE2_IMUX42_6", + "GTPE2_CHANNEL_TX8B10BBYPASS1", + "GTPE2_FAN3_1", + "GTPE2_LOGIC_OUTS_B9_7", + "GTPE2_CHANNEL_RXDATA18", + "GTPE2_IMUX41_6", + "GTPE2_CHANNEL_TXDLYTESTENB", + "GTPE2_IMUX27_4", + "GTPE2_IMUX31_8", + "GTPE2_IMUX5_9", + "GTPE2_IMUX12_0", + "GTPE2_IMUX32_7", + "GTPE2_IMUX1_1", + "GTPE2_IMUX25_1", + "GTPE2_CHANNEL_RXCHBONDI3", + "GTPE2_LOGIC_OUTS_B17_10", + "GTPE2_CHANNEL_RXSTATUS2", + "GTPE2_CHANNEL_SCANOUT2", + "GTPE2_LOGIC_OUTS_B9_1", + "GTPE2_LOGIC_OUTS_B11_3", + "GTPE2_IMUX39_1", + "GTPE2_CHANNEL_TXOUTCLK_1", + "GTPE2_IMUX6_2", + "GTPE2_FAN2_3", + "GTPE2_IMUX31_7", + "GTPE2_CHANNEL_RXCHBONDO1", + "GTPE2_CHANNEL_GTRSVD13", + "GTPE2_IMUX18_4", + "GTPE2_IMUX6_5", + "GTPE2_LOGIC_OUTS_B7_3", + "GTPE2_IMUX46_9", + "GTPE2_LOGIC_OUTS_B5_7", + "GTPE2_LOGIC_OUTS_B16_0", + "GTPE2_CHANNEL_DMONITOROUT8", + "GTPE2_CHANNEL_RXADAPTSELTEST11", + "GTPE2_LOGIC_OUTS_B0_8", + "GTPE2_IMUX43_4", + "GTPE2_CHANNEL_DMONITORCLK", + "GTPE2_IMUX35_2", + "GTPE2_LOGIC_OUTS_B22_7", + "GTPE2_IMUX7_4", + "GTPE2_CHANNEL_PLLCLK1", + "GTPE2_CTRL1_4", + "GTPE2_IMUX11_6", + "GTPE2_CHANNEL_CLKRSVD0", + "GTPE2_LOGIC_OUTS_B14_8", + "GTPE2_LOGIC_OUTS_B13_7", + "GTPE2_IMUX45_2", + "GTPE2_CHANNEL_RXCHARISCOMMA1", + "GTPE2_IMUX29_2", + "GTPE2_CHANNEL_PLLREFCLK0", + "GTPE2_IMUX38_6", + "GTPE2_CHANNEL_TXDATA1", + "GTPE2_CHANNEL_RXPHOVRDEN", + "GTPE2_CHANNEL_DMONITOROUT10", + "GTPE2_LOGIC_OUTS_B22_8", + "GTPE2_IMUX21_9", + "GTPE2_FAN4_4", + "GTPE2_CHANNEL_RXOSINTCFG0", + "GTPE2_IMUX1_8", + "GTPE2_IMUX12_8", + "GTPE2_LOGIC_OUTS_B4_3", + "GTPE2_BYP4_9", + "GTPE2_IMUX14_9", + "GTPE2_LOGIC_OUTS_B15_10", + "GTPE2_BYP0_1", + "GTPE2_LOGIC_OUTS_B21_0", + "GTPE2_CHANNEL_RXDATA8", + "GTPE2_IMUX25_6", + "GTPE2_CTRL1_2", + "GTPE2_IMUX40_10", + "GTPE2_CHANNEL_TXOUTCLK_2", + "GTPE2_CHANNEL_TSTPD3", + "GTPE2_IMUX24_7", + "GTPE2_IMUX15_1", + "GTPE2_LOGIC_OUTS_B3_6", + "GTPE2_IMUX35_1", + "GTPE2_CHANNEL_GTRSVD4", + "GTPE2_IMUX4_10", + "GTPE2_CHANNEL_TXDLYEN", + "GTPE2_LOGIC_OUTS_B10_10", + "GTPE2_IMUX9_3", + "GTPE2_CHANNEL_DRPDO2", + "GTPE2_LOGIC_OUTS_B6_3", + "GTPE2_CHANNEL_RXCOMWAKEDET", + "GTPE2_CHANNEL_PMASCANCLK3", + "GTPE2_CHANNEL_RXDATA23", + "GTPE2_CHANNEL_RXADAPTSELTEST0", + "GTPE2_CHANNEL_TXBUFDIFFCTRL0", + "GTPE2_CHANNEL_TXCOMWAKE", + "GTPE2_FAN0_3", + "GTPE2_LOGIC_OUTS_B13_1", + "GTPE2_CHANNEL_SCANIN5", + "GTPE2_LOGIC_OUTS_B4_7", + "GTPE2_CHANNEL_RXSYNCDONE", + "GTPE2_CHANNEL_TXCHARISK0", + "GTPE2_IMUX31_0", + "GTPE2_IMUX34_6", + "GTPE2_BYP3_7", + "GTPE2_IMUX46_7", + "GTPE2_CHANNEL_RXDISPERR0", + "GTPE2_IMUX1_3", + "GTPE2_IMUX0_10", + "GTPE2_IMUX32_8", + "GTPE2_LOGIC_OUTS_B7_8", + "GTPE2_BYP5_8", + "GTPE2_CHANNEL_TXPHALIGN", + "GTPE2_BYP1_4", + "GTPE2_CHANNEL_TSTIN19", + "GTPE2_CHANNEL_PCSRSVDOUT15", + "GTPE2_IMUX18_2", + "GTPE2_IMUX16_5", + "GTPE2_LOGIC_OUTS_B12_10", + "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "GTPE2_BYP6_0", + "GTPE2_LOGIC_OUTS_B17_3", + "GTPE2_IMUX7_2", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", + "GTPE2_IMUX33_8", + "GTPE2_IMUX34_5", + "GTPE2_CHANNEL_RXCHARISK2", + "GTPE2_IMUX25_5", + "GTPE2_IMUX18_5", + "GTPE2_CHANNEL_RXCHBONDSLAVE", + "GTPE2_CHANNEL_TXOUTCLK_0", + "GTPE2_CHANNEL_TXMAINCURSOR3", + "GTPE2_IMUX9_8", + "GTPE2_IMUX21_6", + "GTPE2_LOGIC_OUTS_B21_3", + "GTPE2_IMUX7_9", + "GTPE2_LOGIC_OUTS_B18_6", + "GTPE2_IMUX45_4", + "GTPE2_BYP7_5", + "GTPE2_CHANNEL_TXCHARDISPMODE2", + "GTPE2_CHANNEL_TXBUFDIFFCTRL1", + "GTPE2_IMUX25_2", + "GTPE2_IMUX28_8", + "GTPE2_CHANNEL_RXADAPTSELTEST7", + "GTPE2_CHANNEL_TXDLYHOLD", + "GTPE2_IMUX43_6", + "GTPE2_CHANNEL_TXDATA13", + "GTPE2_LOGIC_OUTS_B15_0", + "GTPE2_CHANNEL_RXMCOMMAALIGNEN", + "GTPE2_LOGIC_OUTS_B18_5", + "GTPE2_CHANNEL_RXOSHOLD", + "GTPE2_LOGIC_OUTS_B11_8", + "GTPE2_IMUX8_8", + "GTPE2_LOGIC_OUTS_B2_10", + "GTPE2_CHANNEL_RXP_PAD", + "GTPE2_IMUX20_3", + "GTPE2_IMUX38_2", + "GTPE2_FAN1_3", + "GTPE2_IMUX4_0", + "GTPE2_CHANNEL_GTTXRESET", + "GTPE2_BYP3_10", + "GTPE2_LOGIC_OUTS_B16_4", + "GTPE2_CHANNEL_PMASCANENB", + "GTPE2_CHANNEL_RXSYNCIN", + "GTPE2_LOGIC_OUTS_B19_8", + "GTPE2_CHANNEL_TXP", + "GTPE2_CHANNEL_RXHEADER2", + "GTPE2_CHANNEL_TXDATA25", + "GTPE2_LOGIC_OUTS_B14_1", + "GTPE2_IMUX13_3", + "GTPE2_IMUX1_4", + "GTPE2_CHANNEL_DRPDO7", + "GTPE2_BYP1_9", + "GTPE2_IMUX47_8", + "GTPE2_LOGIC_OUTS_B1_10", + "GTPE2_BYP4_4", + "GTPE2_CHANNEL_DRPDI5", + "GTPE2_CHANNEL_RXLPMLFHOLD", + "GTPE2_BYP6_2", + "GTPE2_IMUX21_7", + "GTPE2_CHANNEL_TXDLYSRESET", + "GTPE2_IMUX40_3", + "GTPE2_IMUX38_4", + "GTPE2_LOGIC_OUTS_B21_10", + "GTPE2_BYP3_3", + "GTPE2_FAN2_8", + "GTPE2_BYP6_8", + "GTPE2_CHANNEL_TXDATA27", + "GTPE2_FAN4_3", + "GTPE2_CHANNEL_TXPRBSSEL1", + "GTPE2_CHANNEL_PCSRSVDOUT8", + "GTPE2_CHANNEL_TXPD1", + "GTPE2_IMUX24_4", + "GTPE2_CHANNEL_RXRATEDONE", + "GTPE2_CHANNEL_RXPRBSCNTRESET", + "GTPE2_IMUX12_5", + "GTPE2_CHANNEL_RXDATAVALID1", + "GTPE2_CHANNEL_DRPDI13", + "GTPE2_FAN5_2", + "GTPE2_LOGIC_OUTS_B12_7", + "GTPE2_FAN7_3", + "GTPE2_IMUX41_5", + "GTPE2_CHANNEL_TXGEARBOXREADY", + "GTPE2_LOGIC_OUTS_B6_1", + "GTPE2_FAN1_7", + "GTPE2_CHANNEL_TXSYNCIN", + "GTPE2_LOGIC_OUTS_B17_1", + "GTPE2_IMUX9_4", + "GTPE2_CHANNEL_PMASCANIN4", + "GTPE2_CHANNEL_TXRATE2", + "GTPE2_CHANNEL_DRPDO9", + "GTPE2_BYP7_10", + "GTPE2_IMUX8_7", + "GTPE2_CHANNEL_TSTIN9", + "GTPE2_IMUX12_10", + "GTPE2_LOGIC_OUTS_B19_2", + "GTPE2_LOGIC_OUTS_B19_10", + "GTPE2_BYP1_0", + "GTPE2_LOGIC_OUTS_B15_6", + "GTPE2_IMUX26_5", + "GTPE2_IMUX7_7", + "GTPE2_CHANNEL_TXDIFFCTRL1", + "GTPE2_IMUX41_7", + "GTPE2_CHANNEL_PLL1CLK", + "GTPE2_IMUX33_2", + "GTPE2_CHANNEL_TSTPD4", + "GTPE2_CHANNEL_RXDLYSRESET", + "GTPE2_LOGIC_OUTS_B2_8", + "GTPE2_CHANNEL_RXRATE2", + "GTPE2_FAN5_0", + "GTPE2_CHANNEL_RXOUTCLKSEL0", + "GTPE2_CHANNEL_TXPHINITDONE", + "GTPE2_IMUX45_10", + "GTPE2_IMUX1_0", + "GTPE2_CHANNEL_EYESCANDATAERROR", + "GTPE2_CHANNEL_DRPDI7", + "GTPE2_CHANNEL_RXDATA10", + "GTPE2_CHANNEL_SCANMODEB", + "GTPE2_LOGIC_OUTS_B23_3", + "GTPE2_IMUX31_10", + "GTPE2_FAN6_10", + "GTPE2_IMUX35_10", + "GTPE2_CHANNEL_DMONITOROUT12", + "GTPE2_LOGIC_OUTS_B15_1", + "GTPE2_CHANNEL_TXDLYSRESETDONE", + "GTPE2_CHANNEL_RXDLYOVRDEN", + "GTPE2_IMUX47_2", + "GTPE2_IMUX40_0", + "GTPE2_CHANNEL_PCSRSVDIN1", + "GTPE2_IMUX12_4", + "GTPE2_CHANNEL_DMONITOROUT6", + "GTPE2_IMUX6_8", + "GTPE2_CHANNEL_RXOSOVRDEN", + "GTPE2_CHANNEL_TXDIFFPD", + "GTPE2_CHANNEL_RXCHARISCOMMA2", + "GTPE2_LOGIC_OUTS_B2_5", + "GTPE2_CLK0_3", + "GTPE2_LOGIC_OUTS_B14_0", + "GTPE2_IMUX4_5", + "GTPE2_FAN3_7", + "GTPE2_CHANNEL_TSTIN12", + "GTPE2_IMUX21_8", + "GTPE2_CHANNEL_RXELECIDLEMODE1", + "GTPE2_LOGIC_OUTS_B18_3", + "GTPE2_CHANNEL_RXPHMONITOR2", + "GTPE2_IMUX11_10", + "GTPE2_IMUX31_3", + "GTPE2_CLK1_7", + "GTPE2_CLK1_2", + "GTPE2_LOGIC_OUTS_B5_6", + "GTPE2_FAN6_4", + "GTPE2_IMUX11_7", + "GTPE2_BYP7_4", + "GTPE2_IMUX2_8", + "GTPE2_LOGIC_OUTS_B5_4", + "GTPE2_FAN2_0", + "GTPE2_IMUX32_5", + "GTPE2_LOGIC_OUTS_B16_5", + "GTPE2_LOGIC_OUTS_B18_4", + "GTPE2_BYP4_2", + "GTPE2_CHANNEL_TXPHDLYTSTCLK", + "GTPE2_CHANNEL_SCANIN2", + "GTPE2_IMUX37_5", + "GTPE2_BYP7_8", + "GTPE2_IMUX3_10", + "GTPE2_FAN7_9", + "GTPE2_LOGIC_OUTS_B7_2", + "GTPE2_LOGIC_OUTS_B4_9", + "GTPE2_LOGIC_OUTS_B13_5", + "GTPE2_CHANNEL_GTRSVD3", + "GTPE2_IMUX22_0", + "GTPE2_IMUX2_10", + "GTPE2_CHANNEL_GTRXRESET", + "GTPE2_IMUX35_3", + "GTPE2_IMUX14_6", + "GTPE2_IMUX44_1", + "GTPE2_IMUX38_9", + "GTPE2_CHANNEL_RXDATA28", + "GTPE2_CHANNEL_DRPDI1", + "GTPE2_LOGIC_OUTS_B23_0", + "GTPE2_IMUX10_6", + "GTPE2_CHANNEL_TXOUTCLKSEL0", + "GTPE2_IMUX0_8", + "GTPE2_LOGIC_OUTS_B11_10", + "GTPE2_LOGIC_OUTS_B2_3", + "GTPE2_IMUX15_7", + "GTPE2_IMUX36_1", + "GTPE2_CLK0_6", + "GTPE2_CHANNEL_RXNOTINTABLE3", + "GTPE2_CHANNEL_RXCHANISALIGNED", + "GTPE2_IMUX8_1", + "GTPE2_CHANNEL_TSTPD0", + "GTPE2_CHANNEL_TXDATA14", + "GTPE2_CHANNEL_RXN", + "GTPE2_IMUX14_5", + "GTPE2_IMUX44_4", + "GTPE2_IMUX20_7", + "GTPE2_FAN5_3", + "GTPE2_FAN2_9", + "GTPE2_CHANNEL_TSTIN13", + "GTPE2_CHANNEL_LOOPBACK1", + "GTPE2_IMUX43_2", + "GTPE2_BYP5_6", + "GTPE2_CHANNEL_RXDLYBYPASS", + "GTPE2_LOGIC_OUTS_B11_5", + "GTPE2_IMUX4_8", + "GTPE2_LOGIC_OUTS_B22_4", + "GTPE2_LOGIC_OUTS_B14_2", + "GTPE2_CHANNEL_TXHEADER2", + "GTPE2_IMUX6_7", + "GTPE2_CHANNEL_PCSRSVDOUT1", + "GTPE2_IMUX9_10", + "GTPE2_LOGIC_OUTS_B9_2", + "GTPE2_CHANNEL_PMASCANIN3", + "GTPE2_LOGIC_OUTS_B0_2", + "GTPE2_IMUX10_4", + "GTPE2_CHANNEL_PMASCANOUT5", + "GTPE2_LOGIC_OUTS_B4_5", + "GTPE2_IMUX22_5", + "GTPE2_CHANNEL_TXMARGIN1", + "GTPE2_IMUX43_5", + "GTPE2_LOGIC_OUTS_B17_9", + "GTPE2_CHANNEL_RXLPMLFOVRDEN", + "GTPE2_CHANNEL_RXRATE1", + "GTPE2_LOGIC_OUTS_B5_2", + "GTPE2_IMUX1_2", + "GTPE2_CHANNEL_PCSRSVDIN14", + "GTPE2_BYP6_6", + "GTPE2_CHANNEL_SCANENB", + "GTPE2_CHANNEL_PMASCANCLK0", + "GTPE2_IMUX5_6", + "GTPE2_LOGIC_OUTS_B16_10", + "GTPE2_IMUX47_0", + "GTPE2_LOGIC_OUTS_B3_1", + "GTPE2_LOGIC_OUTS_B21_2", + "GTPE2_CHANNEL_RXCHARISK1", + "GTPE2_IMUX36_7", + "GTPE2_CHANNEL_TXDETECTRX", + "GTPE2_IMUX23_3", + "GTPE2_IMUX20_1", + "GTPE2_IMUX30_8", + "GTPE2_CHANNEL_TXDATA29", + "GTPE2_CHANNEL_TXDATA31", + "GTPE2_CHANNEL_RXDATA5", + "GTPE2_FAN6_7", + "GTPE2_LOGIC_OUTS_B1_3", + "GTPE2_CHANNEL_SCANIN3", + "GTPE2_CHANNEL_RXADAPTSELTEST3", + "GTPE2_CHANNEL_TXRUNDISP2", + "GTPE2_CHANNEL_RXSYSCLKSEL1", + "GTPE2_CHANNEL_RXOSINTID03", + "GTPE2_CHANNEL_TXBUFSTATUS0", + "GTPE2_BYP6_7", + "GTPE2_CHANNEL_RXCHBONDMASTER", + "GTPE2_IMUX35_8", + "GTPE2_IMUX17_5", + "GTPE2_LOGIC_OUTS_B5_8", + "GTPE2_IMUX10_2", + "GTPE2_CHANNEL_TXPOSTCURSORINV", + "GTPE2_IMUX47_4", + "GTPE2_IMUX42_2", + "GTPE2_IMUX47_10", + "GTPE2_LOGIC_OUTS_B23_1", + "GTPE2_IMUX15_4", + "GTPE2_FAN4_9", + "GTPE2_CHANNEL_RXPRBSSEL2", + "GTPE2_LOGIC_OUTS_B14_10", + "GTPE2_IMUX35_9", + "GTPE2_CHANNEL_RXBUFRESET", + "GTPE2_CHANNEL_TXDATA22", + "GTPE2_CHANNEL_PMASCANOUT2", + "GTPE2_LOGIC_OUTS_B4_1", + "GTPE2_IMUX28_6", + "GTPE2_IMUX16_7", + "GTPE2_CHANNEL_DMONITOROUT3", + "GTPE2_LOGIC_OUTS_B20_7", + "GTPE2_LOGIC_OUTS_B12_3", + "GTPE2_LOGIC_OUTS_B23_9", + "GTPE2_IMUX28_4", + "GTPE2_CHANNEL_TXRATE0", + "GTPE2_CHANNEL_DRPDO8", + "GTPE2_CHANNEL_TXDEEMPH", + "GTPE2_LOGIC_OUTS_B2_1", + "GTPE2_LOGIC_OUTS_B1_2", + "GTPE2_LOGIC_OUTS_B16_8", + "GTPE2_CHANNEL_PCSRSVDIN6", + "GTPE2_IMUX0_5", + "GTPE2_CHANNEL_SCANCLK", + "GTPE2_CHANNEL_RXADAPTSELTEST10", + "GTPE2_CHANNEL_TSTIN5", + "GTPE2_IMUX38_3", + "GTPE2_FAN0_0", + "GTPE2_IMUX7_5", + "GTPE2_IMUX45_8", + "GTPE2_IMUX17_7", + "GTPE2_CHANNEL_TSTIN6", + "GTPE2_IMUX39_5", + "GTPE2_CHANNEL_RXPHMONITOR0", + "GTPE2_FAN2_4", + "GTPE2_LOGIC_OUTS_B11_7", + "GTPE2_CHANNEL_TXN", + "GTPE2_CHANNEL_CFGRESET", + "GTPE2_CHANNEL_TXPOSTCURSOR3", + "GTPE2_CHANNEL_RXADAPTSELTEST9", + "GTPE2_CHANNEL_TXPRECURSORINV", + "GTPE2_CHANNEL_DRPADDR1", + "GTPE2_CHANNEL_TXDATA18", + "GTPE2_FAN1_8", + "GTPE2_LOGIC_OUTS_B10_7", + "GTPE2_BYP1_7", + "GTPE2_BYP7_1", + "GTPE2_LOGIC_OUTS_B11_2", + "GTPE2_IMUX17_9", + "GTPE2_CHANNEL_RXCHBONDLEVEL2", + "GTPE2_BYP3_2", + "GTPE2_IMUX45_0", + "GTPE2_CHANNEL_TXPMARESETDONE", + "GTPE2_IMUX14_0", + "GTPE2_CHANNEL_PCSRSVDOUT3", + "GTPE2_CHANNEL_TXINHIBIT", + "GTPE2_LOGIC_OUTS_B14_5", + "GTPE2_IMUX19_2", + "GTPE2_CHANNEL_DRPDI3", + "GTPE2_IMUX28_2", + "GTPE2_IMUX18_6", + "GTPE2_CHANNEL_DRPADDR4", + "GTPE2_CHANNEL_TXPRECURSOR4", + "GTPE2_IMUX34_0", + "GTPE2_IMUX40_4", + "GTPE2_CHANNEL_TXPHALIGNDONE", + "GTPE2_LOGIC_OUTS_B3_3", + "GTPE2_LOGIC_OUTS_B23_2", + "GTPE2_FAN5_4", + "GTPE2_LOGIC_OUTS_B22_1", + "GTPE2_IMUX39_7", + "GTPE2_FAN6_6", + "GTPE2_IMUX13_9", + "GTPE2_CHANNEL_TXSYSCLKSEL0", + "GTPE2_CHANNEL_RXPHDLYRESET", + "GTPE2_LOGIC_OUTS_B19_1", + "GTPE2_CHANNEL_TXCHARDISPVAL3", + "GTPE2_IMUX37_9", + "GTPE2_IMUX13_6", + "GTPE2_FAN0_6", + "GTPE2_LOGIC_OUTS_B0_5", + "GTPE2_CHANNEL_TXPD0", + "GTPE2_CHANNEL_PCSRSVDIN15", + "GTPE2_IMUX47_3", + "GTPE2_CHANNEL_DRPEN", + "GTPE2_BYP4_1", + "GTPE2_IMUX3_9", + "GTPE2_BYP0_7", + "GTPE2_IMUX28_9", + "GTPE2_IMUX16_1", + "GTPE2_CHANNEL_RXDATA13", + "GTPE2_CHANNEL_PHYSTATUS", + "GTPE2_IMUX31_2", + "GTPE2_CHANNEL_TXDIFFCTRL3", + "GTPE2_IMUX8_6", + "GTPE2_LOGIC_OUTS_B3_0", + "GTPE2_IMUX28_7", + "GTPE2_IMUX8_0", + "GTPE2_FAN0_7", + "GTPE2_LOGIC_OUTS_B13_8", + "GTPE2_CHANNEL_TXMAINCURSOR6", + "GTPE2_CHANNEL_DRPWE", + "GTPE2_LOGIC_OUTS_B2_7", + "GTPE2_IMUX33_1", + "GTPE2_IMUX3_8", + "GTPE2_IMUX11_0", + "GTPE2_LOGIC_OUTS_B3_7", + "GTPE2_CLK0_8", + "GTPE2_IMUX36_5", + "GTPE2_IMUX11_5", + "GTPE2_CHANNEL_TXDATA23", + "GTPE2_IMUX19_4", + "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", + "GTPE2_IMUX23_10", + "GTPE2_CHANNEL_RXOUTCLK_1", + "GTPE2_IMUX40_5", + "GTPE2_FAN1_9", + "GTPE2_CHANNEL_RXADAPTSELTEST13", + "GTPE2_CHANNEL_RXN_PAD", + "GTPE2_CHANNEL_RXVALID", + "GTPE2_CHANNEL_TXDLYBYPASS", + "GTPE2_IMUX44_9", + "GTPE2_CHANNEL_TXOUTCLKPCS", + "GTPE2_CHANNEL_PMASCANOUT3", + "GTPE2_CHANNEL_DRPADDR7", + "GTPE2_CHANNEL_RXDATA16", + "GTPE2_IMUX39_9", + "GTPE2_LOGIC_OUTS_B10_3", + "GTPE2_IMUX21_0", + "GTPE2_BYP1_5", + "GTPE2_IMUX3_3", + "GTPE2_LOGIC_OUTS_B3_9", + "GTPE2_IMUX32_0", + "GTPE2_CHANNEL_TXPRBSSEL0", + "GTPE2_IMUX26_6", + "GTPE2_CHANNEL_RXPCOMMAALIGNEN", + "GTPE2_IMUX13_10", + "GTPE2_CHANNEL_RXPHALIGNDONE", + "GTPE2_LOGIC_OUTS_B9_6", + "GTPE2_LOGIC_OUTS_B17_0", + "GTPE2_CHANNEL_RXDATA22", + "GTPE2_CHANNEL_RXOUTCLK_0", + "GTPE2_IMUX13_4", + "GTPE2_CHANNEL_GTRSVD1", + "GTPE2_CHANNEL_RXDATA12", + "GTPE2_CHANNEL_SCANOUT3", + "GTPE2_CHANNEL_RXCDRRESET", + "GTPE2_IMUX1_6", + "GTPE2_CHANNEL_TXPRECURSOR3", + "GTPE2_CHANNEL_DRPDI9", + "GTPE2_LOGIC_OUTS_B9_8", + "GTPE2_FAN6_1", + "GTPE2_IMUX19_7", + "GTPE2_CHANNEL_TXCHARDISPMODE3", + "GTPE2_CHANNEL_PMASCANOUT1", + "GTPE2_IMUX37_10", + "GTPE2_CTRL1_3", + "GTPE2_LOGIC_OUTS_B16_2", + "GTPE2_IMUX45_5", + "GTPE2_CHANNEL_PCSRSVDIN12", + "GTPE2_IMUX19_5", + "GTPE2_CHANNEL_RXADAPTSELTEST12", + "GTPE2_IMUX13_0", + "GTPE2_CTRL0_7", + "GTPE2_LOGIC_OUTS_B18_10", + "GTPE2_IMUX0_3", + "GTPE2_IMUX34_3", + "GTPE2_CHANNEL_RXOSINTOVRDEN", + "GTPE2_CHANNEL_TXSEQUENCE5", + "GTPE2_LOGIC_OUTS_B22_3", + "GTPE2_CHANNEL_RXLPMHFOVRDEN", + "GTPE2_CHANNEL_TXDATA6", + "GTPE2_IMUX19_0", + "GTPE2_CHANNEL_RXDATA20", + "GTPE2_CHANNEL_SCANOUT0", + "GTPE2_CHANNEL_TXPOSTCURSOR4", + "GTPE2_CHANNEL_TXPOSTCURSOR1", + "GTPE2_LOGIC_OUTS_B23_4", + "GTPE2_CHANNEL_SCANIN1", + "GTPE2_FAN7_1", + "GTPE2_IMUX2_9", + "GTPE2_CHANNEL_RXPHALIGNEN", + "GTPE2_FAN2_1", + "GTPE2_CHANNEL_TXPHDLYRESET", + "GTPE2_CHANNEL_RXPD1", + "GTPE2_CHANNEL_RXPRBSERR", + "GTPE2_CHANNEL_PMARSVDOUT0", + "GTPE2_IMUX25_8", + "GTPE2_IMUX23_0", + "GTPE2_IMUX15_9", + "GTPE2_FAN5_5", + "GTPE2_CHANNEL_PMASCANRSTEN", + "GTPE2_CHANNEL_RXCHARISK0", + "GTPE2_LOGIC_OUTS_B21_9", + "GTPE2_IMUX7_8", + "GTPE2_IMUX14_8", + "GTPE2_FAN5_7", + "GTPE2_CHANNEL_TSTPD2", + "GTPE2_LOGIC_OUTS_B8_7", + "GTPE2_LOGIC_OUTS_B22_2", + "GTPE2_IMUX32_10", + "GTPE2_CHANNEL_TXPOSTCURSOR2", + "GTPE2_CHANNEL_DRPDO14", + "GTPE2_IMUX21_2", + "GTPE2_CLK1_3", + "GTPE2_CHANNEL_RXCOMMADETEN", + "GTPE2_IMUX16_2", + "GTPE2_CHANNEL_TXPRECURSOR1", + "GTPE2_IMUX32_6", + "GTPE2_IMUX3_6", + "GTPE2_CTRL1_7", + "GTPE2_CHANNEL_RXPHDLYPD", + "GTPE2_BYP2_7", + "GTPE2_CHANNEL_DMONITOROUT5", + "GTPE2_CTRL0_8", + "GTPE2_LOGIC_OUTS_B14_9", + "GTPE2_CHANNEL_TXRUNDISP0", + "GTPE2_IMUX3_4", + "GTPE2_IMUX18_10", + "GTPE2_CHANNEL_PCSRSVDIN10", + "GTPE2_IMUX20_5", + "GTPE2_IMUX29_6", + "GTPE2_IMUX42_9", + "GTPE2_IMUX28_5", + "GTPE2_LOGIC_OUTS_B11_6", + "GTPE2_CHANNEL_RXDATA30", + "GTPE2_LOGIC_OUTS_B1_6", + "GTPE2_IMUX2_2", + "GTPE2_CHANNEL_PMARSVDIN0", + "GTPE2_FAN6_3", + "GTPE2_CHANNEL_PMASCANIN6", + "GTPE2_FAN0_5", + "GTPE2_CHANNEL_TXCHARISK1", + "GTPE2_FAN4_8", + "GTPE2_BYP2_1", + "GTPE2_LOGIC_OUTS_B13_9", + "GTPE2_CHANNEL_RXCHARISCOMMA0", + "GTPE2_IMUX37_1", + "GTPE2_CHANNEL_RXSTATUS0", + "GTPE2_IMUX14_10", + "GTPE2_IMUX33_3", + "GTPE2_IMUX37_2", + "GTPE2_FAN1_6", + "GTPE2_CHANNEL_GTRXOUTCLK_2", + "GTPE2_CHANNEL_RXDATAVALID0", + "GTPE2_CHANNEL_PCSRSVDOUT9", + "GTPE2_IMUX19_9", + "GTPE2_IMUX47_1", + "GTPE2_IMUX47_7", + "GTPE2_CHANNEL_TXUSERRDY", + "GTPE2_LOGIC_OUTS_B7_5", + "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "GTPE2_CHANNEL_RXDATA31", + "GTPE2_CHANNEL_RXDISPERR2", + "GTPE2_CHANNEL_PCSRSVDOUT13", + "GTPE2_CHANNEL_DMONITOROUT14", + "GTPE2_CHANNEL_DRPDO11", + "GTPE2_CHANNEL_DRPDO4", + "GTPE2_LOGIC_OUTS_B10_9", + "GTPE2_IMUX17_4", + "GTPE2_LOGIC_OUTS_B14_6", + "GTPE2_CHANNEL_TXELECIDLE", + "GTPE2_FAN3_6", + "GTPE2_CHANNEL_TXDATA20", + "GTPE2_CHANNEL_DMONITOROUT7", + "GTPE2_IMUX17_3", + "GTPE2_LOGIC_OUTS_B8_1", + "GTPE2_LOGIC_OUTS_B5_1", + "GTPE2_CHANNEL_PMASCANOUT0", + "GTPE2_IMUX15_3", + "GTPE2_CHANNEL_TXMAINCURSOR5", + "GTPE2_IMUX43_7", + "GTPE2_BYP0_0", + "GTPE2_CHANNEL_PMARSVDIN2", + "GTPE2_IMUX0_6", + "GTPE2_CHANNEL_GTRESETSEL", + "GTPE2_IMUX20_9", + "GTPE2_CHANNEL_TSTIN10", + "GTPE2_CHANNEL_TXDATA28", + "GTPE2_CHANNEL_DRPDI6", + "GTPE2_CHANNEL_RXCHBONDO0", + "GTPE2_IMUX40_7", + "GTPE2_BYP5_7", + "GTPE2_CHANNEL_DRPADDR8", + "GTPE2_CHANNEL_TXDATA21", + "GTPE2_IMUX42_1", + "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "GTPE2_LOGIC_OUTS_B19_3", + "GTPE2_LOGIC_OUTS_B3_10", + "GTPE2_BYP3_5", + "GTPE2_IMUX43_0", + "GTPE2_CHANNEL_TXRESETDONE", + "GTPE2_CHANNEL_PMARSVDOUT1", + "GTPE2_IMUX13_1", + "GTPE2_CHANNEL_TSTIN4", + "GTPE2_BYP2_4", + "GTPE2_CHANNEL_RXADAPTSELTEST1", + "GTPE2_FAN2_2", + "GTPE2_IMUX13_2", + "GTPE2_CHANNEL_TXRUNDISP3", + "GTPE2_CHANNEL_TSTIN8", + "GTPE2_CHANNEL_RXDATA11", + "GTPE2_IMUX40_1", + "GTPE2_FAN7_6", + "GTPE2_LOGIC_OUTS_B0_4", + "GTPE2_CHANNEL_RXOSINTSTARTED", + "GTPE2_CHANNEL_TSTCLK0", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", + "GTPE2_IMUX1_10", + "GTPE2_IMUX5_10", + "GTPE2_CHANNEL_TXDATA30", + "GTPE2_IMUX43_3", + "GTPE2_LOGIC_OUTS_B0_0", + "GTPE2_IMUX46_8", + "GTPE2_IMUX10_8", + "GTPE2_CHANNEL_TXSWING", + "GTPE2_IMUX37_4", + "GTPE2_CHANNEL_TXDATA10", + "GTPE2_CHANNEL_SCANOUT4", + "GTPE2_IMUX6_3", + "GTPE2_BYP2_5", + "GTPE2_CHANNEL_RXNOTINTABLE0", + "GTPE2_IMUX6_9", + "GTPE2_IMUX40_8", + "GTPE2_IMUX0_1", + "GTPE2_IMUX4_6", + "GTPE2_CHANNEL_RXOSINTSTROBE", + "GTPE2_LOGIC_OUTS_B8_8", + "GTPE2_IMUX12_9", + "GTPE2_IMUX22_2", + "GTPE2_IMUX32_2", + "GTPE2_CHANNEL_RXCOMINITDET", + "GTPE2_LOGIC_OUTS_B14_4", + "GTPE2_CHANNEL_TXDLYUPDOWN", + "GTPE2_CHANNEL_DRPADDR3", + "GTPE2_CHANNEL_TXDATA7", + "GTPE2_CHANNEL_RXOUTCLKPCS", + "GTPE2_CHANNEL_RXADAPTSELTEST2", + "GTPE2_CHANNEL_RXDATA1", + "GTPE2_CHANNEL_DRPRDY", + "GTPE2_FAN3_8", + "GTPE2_CHANNEL_TXOUTCLKSEL2", + "GTPE2_IMUX12_1", + "GTPE2_CTRL0_4", + "GTPE2_IMUX23_8", + "GTPE2_CHANNEL_RXCDRFREQRESET", + "GTPE2_CHANNEL_PMASCANCLK2", + "GTPE2_IMUX32_1", + "GTPE2_CHANNEL_RXCHBONDLEVEL0", + "GTPE2_CHANNEL_TX8B10BBYPASS2", + "GTPE2_BYP5_9", + "GTPE2_CHANNEL_TXBUFDIFFCTRL2", + "GTPE2_CHANNEL_SCANOUT1", + "GTPE2_CHANNEL_RXOUTCLKSEL1", + "GTPE2_CHANNEL_TXDATA3", + "GTPE2_IMUX16_10", + "GTPE2_CHANNEL_RXCHBONDO2", + "GTPE2_FAN3_0", + "GTPE2_IMUX22_9", + "GTPE2_IMUX15_0", + "GTPE2_CHANNEL_GTRSVD11", + "GTPE2_LOGIC_OUTS_B13_4", + "GTPE2_IMUX43_10", + "GTPE2_CHANNEL_TXBUFSTATUS1", + "GTPE2_CHANNEL_RXBYTEREALIGN", + "GTPE2_CHANNEL_PCSRSVDIN11", + "GTPE2_CHANNEL_PCSRSVDOUT7", + "GTPE2_CHANNEL_GTRSVD15", + "GTPE2_CLK0_0", + "GTPE2_IMUX10_3", + "GTPE2_IMUX31_5", + "GTPE2_IMUX37_3", + "GTPE2_LOGIC_OUTS_B4_4", + "GTPE2_IMUX38_10", + "GTPE2_CHANNEL_PCSRSVDIN0", + "GTPE2_CHANNEL_TXSYSCLKSEL1", + "GTPE2_CHANNEL_PCSRSVDIN7", + "GTPE2_CHANNEL_DRPDI11", + "GTPE2_IMUX4_3", + "GTPE2_LOGIC_OUTS_B19_9", + "GTPE2_CHANNEL_RXPHALIGN", + "GTPE2_IMUX29_8", + "GTPE2_LOGIC_OUTS_B12_0", + "GTPE2_IMUX9_2", + "GTPE2_CHANNEL_PCSRSVDIN13", + "GTPE2_CHANNEL_RXUSRCLK", + "GTPE2_BYP5_5", + "GTPE2_LOGIC_OUTS_B4_2", + "GTPE2_CHANNEL_RXPRBSSEL0", + "GTPE2_CTRL0_0", + "GTPE2_FAN2_5", + "GTPE2_IMUX46_1", + "GTPE2_LOGIC_OUTS_B7_9", + "GTPE2_LOGIC_OUTS_B4_8", + "GTPE2_CHANNEL_RXCHANBONDSEQ", + "GTPE2_IMUX26_9", + "GTPE2_IMUX35_4", + "GTPE2_CHANNEL_TXPIPPMOVRDEN", + "GTPE2_IMUX27_9", + "GTPE2_IMUX30_10", + "GTPE2_LOGIC_OUTS_B17_6", + "GTPE2_CHANNEL_RXDATA27", + "GTPE2_IMUX12_6", + "GTPE2_IMUX41_0", + "GTPE2_IMUX12_7", + "GTPE2_CHANNEL_RXOOBRESET", + "GTPE2_CHANNEL_TX8B10BEN", + "GTPE2_LOGIC_OUTS_B3_2", + "GTPE2_IMUX5_3", + "GTPE2_CHANNEL_RXADAPTSELTEST4", + "GTPE2_CHANNEL_PMASCANOUT6", + "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "GTPE2_BYP4_10", + "GTPE2_CHANNEL_RXDATA29", + "GTPE2_IMUX5_1", + "GTPE2_IMUX14_7", + "GTPE2_CHANNEL_RXCHARISCOMMA3", + "GTPE2_BYP2_2", + "GTPE2_LOGIC_OUTS_B1_7", + "GTPE2_CHANNEL_GTRSVD8", + "GTPE2_CHANNEL_RXPCSRESET", + "GTPE2_CHANNEL_DMONITOROUT4", + "GTPE2_IMUX47_5", + "GTPE2_IMUX29_3", + "GTPE2_IMUX30_5", + "GTPE2_CTRL1_9", + "GTPE2_CTRL0_10", + "GTPE2_LOGIC_OUTS_B13_6", + "GTPE2_LOGIC_OUTS_B16_3", + "GTPE2_BYP6_10", + "GTPE2_CHANNEL_PCSRSVDIN4", + "GTPE2_IMUX20_6", + "GTPE2_IMUX21_4", + "GTPE2_CHANNEL_PCSRSVDIN3", + "GTPE2_IMUX33_6", + "GTPE2_CHANNEL_EYESCANRESET", + "GTPE2_IMUX41_8", + "GTPE2_IMUX3_1", + "GTPE2_IMUX26_7", + "GTPE2_BYP3_1", + "GTPE2_CLK0_9", + "GTPE2_BYP2_6", + "GTPE2_CHANNEL_RXPHMONITOR1", + "GTPE2_IMUX21_3", + "GTPE2_IMUX27_0", + "GTPE2_IMUX11_1", + "GTPE2_CHANNEL_DRPDO10", + "GTPE2_CHANNEL_RXHEADER0", + "GTPE2_CHANNEL_TSTIN15", + "GTPE2_LOGIC_OUTS_B11_1", + "GTPE2_LOGIC_OUTS_B16_7", + "GTPE2_IMUX6_10", + "GTPE2_CHANNEL_DRPDO12", + "GTPE2_IMUX36_0", + "GTPE2_IMUX47_9", + "GTPE2_LOGIC_OUTS_B6_0", + "GTPE2_CHANNEL_PLL0REFCLK", + "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "GTPE2_CHANNEL_RXDATA6", + "GTPE2_IMUX19_8", + "GTPE2_CHANNEL_RXSTATUS1", + "GTPE2_CHANNEL_RXPMARESETDONE", + "GTPE2_CHANNEL_TXDIFFCTRL2", + "GTPE2_LOGIC_OUTS_B16_6", + "GTPE2_CHANNEL_DRPDO1", + "GTPE2_CHANNEL_RXDLYEN", + "GTPE2_CLK0_2", + "GTPE2_IMUX17_10", + "GTPE2_CHANNEL_TXCHARDISPMODE1", + "GTPE2_CHANNEL_RXDATA15", + "GTPE2_CHANNEL_DRPDI15", + "GTPE2_IMUX15_6", + "GTPE2_IMUX14_4", + "GTPE2_FAN1_4", + "GTPE2_LOGIC_OUTS_B22_0", + "GTPE2_LOGIC_OUTS_B10_2", + "GTPE2_CHANNEL_RXCHANREALIGN", + "GTPE2_CHANNEL_LOOPBACK2", + "GTPE2_IMUX34_4", + "GTPE2_FAN5_10", + "GTPE2_IMUX2_0", + "GTPE2_LOGIC_OUTS_B8_10", + "GTPE2_IMUX7_10", + "GTPE2_CHANNEL_DRPDI4", + "GTPE2_CHANNEL_RXDEBUGPULSE", + "GTPE2_LOGIC_OUTS_B12_6", + "GTPE2_CHANNEL_PMASCANIN5", + "GTPE2_FAN7_5", + "GTPE2_CHANNEL_PMASCANCLK1", + "GTPE2_IMUX43_9", + "GTPE2_LOGIC_OUTS_B12_2", + "GTPE2_LOGIC_OUTS_B20_2", + "GTPE2_IMUX4_4", + "GTPE2_IMUX45_3", + "GTPE2_IMUX30_1", + "GTPE2_LOGIC_OUTS_B8_3", + "GTPE2_FAN5_1", + "GTPE2_CHANNEL_TXMAINCURSOR0", + "GTPE2_IMUX35_0", + "GTPE2_IMUX28_3", + "GTPE2_CHANNEL_RXCHBONDLEVEL1", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", + "GTPE2_CHANNEL_TXPRECURSOR0", + "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "GTPE2_CHANNEL_TXPRBSSEL2", + "GTPE2_LOGIC_OUTS_B15_3", + "GTPE2_IMUX4_9", + "GTPE2_IMUX39_2", + "GTPE2_CHANNEL_TXPHDLYPD", + "GTPE2_CHANNEL_TXCHARISK2", + "GTPE2_CHANNEL_PCSRSVDOUT14", + "GTPE2_IMUX17_1", + "GTPE2_LOGIC_OUTS_B23_7", + "GTPE2_LOGIC_OUTS_B11_4", + "GTPE2_IMUX18_9", + "GTPE2_CHANNEL_RX8B10BEN", + "GTPE2_CHANNEL_TXDATA16", + "GTPE2_IMUX32_9", + "GTPE2_IMUX5_4", + "GTPE2_CHANNEL_TXMARGIN0", + "GTPE2_CHANNEL_TXCHARDISPVAL0", + "GTPE2_IMUX16_6", + "GTPE2_IMUX41_1", + "GTPE2_FAN5_9", + "GTPE2_LOGIC_OUTS_B0_9", + "GTPE2_IMUX23_1", + "GTPE2_CHANNEL_DRPDI2", + "GTPE2_IMUX24_5" + ], + "tile_type": "GTP_CHANNEL_2", + "sites": [ + { + "site_pins": { + "TSTIN11": "GTPE2_CHANNEL_TSTIN11", + "TXCOMSAS": "GTPE2_CHANNEL_TXCOMSAS", + "RXPHDLYPD": "GTPE2_CHANNEL_RXPHDLYPD", + "TXSEQUENCE2": "GTPE2_CHANNEL_TXSEQUENCE2", + "TXCHARISK3": "GTPE2_CHANNEL_TXCHARISK3", + "TSTIN4": "GTPE2_CHANNEL_TSTIN4", + "PMASCANOUT1": "GTPE2_CHANNEL_PMASCANOUT1", + "TXDATA26": "GTPE2_CHANNEL_TXDATA26", + "GTRSVD12": "GTPE2_CHANNEL_GTRSVD12", + "TXDATA29": "GTPE2_CHANNEL_TXDATA29", + "PCSRSVDOUT13": "GTPE2_CHANNEL_PCSRSVDOUT13", + "DRPDI4": "GTPE2_CHANNEL_DRPDI4", + "RXNOTINTABLE3": "GTPE2_CHANNEL_RXNOTINTABLE3", + "RXADAPTSELTEST7": "GTPE2_CHANNEL_RXADAPTSELTEST7", + "PMARSVDIN3": "GTPE2_CHANNEL_PMARSVDIN3", + "TXCHARDISPMODE0": "GTPE2_CHANNEL_TXCHARDISPMODE0", + "PMASCANCLK2": "GTPE2_CHANNEL_PMASCANCLK2", + "DRPDI13": "GTPE2_CHANNEL_DRPDI13", + "RXADAPTSELTEST3": "GTPE2_CHANNEL_RXADAPTSELTEST3", + "RXCHARISK2": "GTPE2_CHANNEL_RXCHARISK2", + "RXCOMINITDET": "GTPE2_CHANNEL_RXCOMINITDET", + "TXMAINCURSOR1": "GTPE2_CHANNEL_TXMAINCURSOR1", + "RXUSRCLK": "GTPE2_CHANNEL_RXUSRCLK", + "PMASCANIN0": "GTPE2_CHANNEL_PMASCANIN0", + "RXCLKCORCNT0": "GTPE2_CHANNEL_RXCLKCORCNT0", + "RXDATA16": "GTPE2_CHANNEL_RXDATA16", + "CFGRESET": "GTPE2_CHANNEL_CFGRESET", + "TSTIN1": "GTPE2_CHANNEL_TSTIN1", + "TXPIPPMOVRDEN": "GTPE2_CHANNEL_TXPIPPMOVRDEN", + "TXPHINIT": "GTPE2_CHANNEL_TXPHINIT", + "EYESCANMODE": "GTPE2_CHANNEL_EYESCANMODE", + "TSTCLK1": "GTPE2_CHANNEL_TSTCLK1", + "RXBUFSTATUS1": "GTPE2_CHANNEL_RXBUFSTATUS1", + "TXPRBSSEL1": "GTPE2_CHANNEL_TXPRBSSEL1", + "LOOPBACK1": "GTPE2_CHANNEL_LOOPBACK1", + "TXMARGIN2": "GTPE2_CHANNEL_TXMARGIN2", + "TSTIN12": "GTPE2_CHANNEL_TSTIN12", + "TSTPD3": "GTPE2_CHANNEL_TSTPD3", + "GTRSVD15": "GTPE2_CHANNEL_GTRSVD15", + "TXDLYEN": "GTPE2_CHANNEL_TXDLYEN", + "TXBUFDIFFCTRL0": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", + "TXRUNDISP3": "GTPE2_CHANNEL_TXRUNDISP3", + "GTRSVD2": "GTPE2_CHANNEL_GTRSVD2", + "PCSRSVDIN9": "GTPE2_CHANNEL_PCSRSVDIN9", + "RXVALID": "GTPE2_CHANNEL_RXVALID", + "TXOUTCLKSEL1": "GTPE2_CHANNEL_TXOUTCLKSEL1", + "RXPCOMMAALIGNEN": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", + "RXDATA15": "GTPE2_CHANNEL_RXDATA15", + "TXELECIDLE": "GTPE2_CHANNEL_TXELECIDLE", + "TXDIFFCTRL3": "GTPE2_CHANNEL_TXDIFFCTRL3", + "PCSRSVDIN6": "GTPE2_CHANNEL_PCSRSVDIN6", + "RXCOMMADETEN": "GTPE2_CHANNEL_RXCOMMADETEN", + "TXSYSCLKSEL1": "GTPE2_CHANNEL_TXSYSCLKSEL1", + "DRPDO5": "GTPE2_CHANNEL_DRPDO5", + "TXDATA6": "GTPE2_CHANNEL_TXDATA6", + "GTRSVD0": "GTPE2_CHANNEL_GTRSVD0", + "GTRSVD8": "GTPE2_CHANNEL_GTRSVD8", + "TXUSRCLK2": "GTPE2_CHANNEL_TXUSRCLK2", + "TXRATE0": "GTPE2_CHANNEL_TXRATE0", + "TSTCLK0": "GTPE2_CHANNEL_TSTCLK0", + "PMASCANRSTEN": "GTPE2_CHANNEL_PMASCANRSTEN", + "TXDATA21": "GTPE2_CHANNEL_TXDATA21", + "RXCDROVRDEN": "GTPE2_CHANNEL_RXCDROVRDEN", + "TXDATA3": "GTPE2_CHANNEL_TXDATA3", + "RXNOTINTABLE0": "GTPE2_CHANNEL_RXNOTINTABLE0", + "TXPOSTCURSOR3": "GTPE2_CHANNEL_TXPOSTCURSOR3", + "RXSYNCOUT": "GTPE2_CHANNEL_RXSYNCOUT", + "RXCHBONDI3": "GTPE2_CHANNEL_RXCHBONDI3", + "RXCHANBONDSEQ": "GTPE2_CHANNEL_RXCHANBONDSEQ", + "TSTIN7": "GTPE2_CHANNEL_TSTIN7", + "RXPOLARITY": "GTPE2_CHANNEL_RXPOLARITY", + "TXMAINCURSOR3": "GTPE2_CHANNEL_TXMAINCURSOR3", + "DRPDI9": "GTPE2_CHANNEL_DRPDI9", + "RXHEADERVALID": "GTPE2_CHANNEL_RXHEADERVALID", + "PMARSVDOUT1": "GTPE2_CHANNEL_PMARSVDOUT1", + "DMONITOROUT13": "GTPE2_CHANNEL_DMONITOROUT13", + "RXSLIDE": "GTPE2_CHANNEL_RXSLIDE", + "LOOPBACK2": "GTPE2_CHANNEL_LOOPBACK2", + "PCSRSVDIN8": "GTPE2_CHANNEL_PCSRSVDIN8", + "RXCOMWAKEDET": "GTPE2_CHANNEL_RXCOMWAKEDET", + "RX8B10BEN": "GTPE2_CHANNEL_RX8B10BEN", + "RXOSINTCFG0": "GTPE2_CHANNEL_RXOSINTCFG0", + "TXMARGIN0": "GTPE2_CHANNEL_TXMARGIN0", + "PCSRSVDOUT2": "GTPE2_CHANNEL_PCSRSVDOUT2", + "TXPIPPMSTEPSIZE4": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", + "TXPIPPMPD": "GTPE2_CHANNEL_TXPIPPMPD", + "TXPD0": "GTPE2_CHANNEL_TXPD0", + "RXADAPTSELTEST0": "GTPE2_CHANNEL_RXADAPTSELTEST0", + "TXSYSCLKSEL0": "GTPE2_CHANNEL_TXSYSCLKSEL0", + "RXCHBONDO0": "GTPE2_CHANNEL_RXCHBONDO0", + "TXHEADER2": "GTPE2_CHANNEL_TXHEADER2", + "PCSRSVDOUT14": "GTPE2_CHANNEL_PCSRSVDOUT14", + "TXRATE2": "GTPE2_CHANNEL_TXRATE2", + "SCANOUT1": "GTPE2_CHANNEL_SCANOUT1", + "PCSRSVDIN12": "GTPE2_CHANNEL_PCSRSVDIN12", + "GTRSVD6": "GTPE2_CHANNEL_GTRSVD6", + "TXPD1": "GTPE2_CHANNEL_TXPD1", + "TXDLYHOLD": "GTPE2_CHANNEL_TXDLYHOLD", + "CLKRSVD1": "GTPE2_CHANNEL_CLKRSVD1", + "TXPHALIGNEN": "GTPE2_CHANNEL_TXPHALIGNEN", + "TXPHDLYPD": "GTPE2_CHANNEL_TXPHDLYPD", + "TXCHARDISPMODE3": "GTPE2_CHANNEL_TXCHARDISPMODE3", + "SCANOUT5": "GTPE2_CHANNEL_SCANOUT5", + "RXOUTCLKSEL1": "GTPE2_CHANNEL_RXOUTCLKSEL1", + "DRPDI10": "GTPE2_CHANNEL_DRPDI10", + "PCSRSVDOUT11": "GTPE2_CHANNEL_PCSRSVDOUT11", + "RXGEARBOXSLIP": "GTPE2_CHANNEL_RXGEARBOXSLIP", + "TXPHALIGNDONE": "GTPE2_CHANNEL_TXPHALIGNDONE", + "RXSYNCALLIN": "GTPE2_CHANNEL_RXSYNCALLIN", + "TXDATA2": "GTPE2_CHANNEL_TXDATA2", + "DMONITOROUT2": "GTPE2_CHANNEL_DMONITOROUT2", + "GTRXRESET": "GTPE2_CHANNEL_GTRXRESET", + "RXOSCALRESET": "GTPE2_CHANNEL_RXOSCALRESET", + "RXCHARISCOMMA0": "GTPE2_CHANNEL_RXCHARISCOMMA0", + "PCSRSVDIN11": "GTPE2_CHANNEL_PCSRSVDIN11", + "RXPRBSSEL1": "GTPE2_CHANNEL_RXPRBSSEL1", + "TXPHOVRDEN": "GTPE2_CHANNEL_TXPHOVRDEN", + "RXPHMONITOR2": "GTPE2_CHANNEL_RXPHMONITOR2", + "GTPRXP": "GTPE2_CHANNEL_RXP", + "TXDLYBYPASS": "GTPE2_CHANNEL_TXDLYBYPASS", + "TSTIN16": "GTPE2_CHANNEL_TSTIN16", + "TXPOSTCURSORINV": "GTPE2_CHANNEL_TXPOSTCURSORINV", + "RXCOMSASDET": "GTPE2_CHANNEL_RXCOMSASDET", + "DMONITOROUT9": "GTPE2_CHANNEL_DMONITOROUT9", + "RXDATA18": "GTPE2_CHANNEL_RXDATA18", + "GTRSVD9": "GTPE2_CHANNEL_GTRSVD9", + "SCANOUT0": "GTPE2_CHANNEL_SCANOUT0", + "RXADAPTSELTEST6": "GTPE2_CHANNEL_RXADAPTSELTEST6", + "RXDATA19": "GTPE2_CHANNEL_RXDATA19", + "RXCHBONDSLAVE": "GTPE2_CHANNEL_RXCHBONDSLAVE", + "DMONITOROUT7": "GTPE2_CHANNEL_DMONITOROUT7", + "RXCDRHOLD": "GTPE2_CHANNEL_RXCDRHOLD", + "TXMAINCURSOR0": "GTPE2_CHANNEL_TXMAINCURSOR0", + "RXOSINTCFG2": "GTPE2_CHANNEL_RXOSINTCFG2", + "PMARSVDIN4": "GTPE2_CHANNEL_PMARSVDIN4", + "TXMAINCURSOR5": "GTPE2_CHANNEL_TXMAINCURSOR5", + "TSTIN9": "GTPE2_CHANNEL_TSTIN9", + "TX8B10BBYPASS1": "GTPE2_CHANNEL_TX8B10BBYPASS1", + "RXPRBSSEL2": "GTPE2_CHANNEL_RXPRBSSEL2", + "RXADAPTSELTEST4": "GTPE2_CHANNEL_RXADAPTSELTEST4", + "TXCHARISK0": "GTPE2_CHANNEL_TXCHARISK0", + "PMARSVDIN0": "GTPE2_CHANNEL_PMARSVDIN0", + "TXPDELECIDLEMODE": "GTPE2_CHANNEL_TXPDELECIDLEMODE", + "RXADAPTSELTEST8": "GTPE2_CHANNEL_RXADAPTSELTEST8", + "TXCHARDISPMODE1": "GTPE2_CHANNEL_TXCHARDISPMODE1", + "TXPMARESETDONE": "GTPE2_CHANNEL_TXPMARESETDONE", + "RXBYTEISALIGNED": "GTPE2_CHANNEL_RXBYTEISALIGNED", + "DMONFIFORESET": "GTPE2_CHANNEL_DMONFIFORESET", + "RXPHSLIPMONITOR4": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "TXDIFFPD": "GTPE2_CHANNEL_TXDIFFPD", + "RXOSINTSTROBE": "GTPE2_CHANNEL_RXOSINTSTROBE", + "PLL0CLK": "GTPE2_CHANNEL_PLL0CLK", + "SETERRSTATUS": "GTPE2_CHANNEL_SETERRSTATUS", + "TXPIPPMSTEPSIZE3": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", + "RXSTATUS2": "GTPE2_CHANNEL_RXSTATUS2", + "TX8B10BEN": "GTPE2_CHANNEL_TX8B10BEN", + "DMONITOROUT5": "GTPE2_CHANNEL_DMONITOROUT5", + "RXLPMHFOVRDEN": "GTPE2_CHANNEL_RXLPMHFOVRDEN", + "PCSRSVDOUT9": "GTPE2_CHANNEL_PCSRSVDOUT9", + "RXOUTCLKFABRIC": "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "PCSRSVDOUT0": "GTPE2_CHANNEL_PCSRSVDOUT0", + "RXPHMONITOR4": "GTPE2_CHANNEL_RXPHMONITOR4", + "RXDATA3": "GTPE2_CHANNEL_RXDATA3", + "RXSYNCDONE": "GTPE2_CHANNEL_RXSYNCDONE", + "RXADAPTSELTEST9": "GTPE2_CHANNEL_RXADAPTSELTEST9", + "DRPADDR4": "GTPE2_CHANNEL_DRPADDR4", + "PCSRSVDOUT7": "GTPE2_CHANNEL_PCSRSVDOUT7", + "TXPIPPMSTEPSIZE1": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", + "RXPHMONITOR1": "GTPE2_CHANNEL_RXPHMONITOR1", + "TXPIPPMEN": "GTPE2_CHANNEL_TXPIPPMEN", + "TXCHARDISPVAL3": "GTPE2_CHANNEL_TXCHARDISPVAL3", + "RXUSRCLK2": "GTPE2_CHANNEL_RXUSRCLK2", + "RXDATAVALID1": "GTPE2_CHANNEL_RXDATAVALID1", + "RXLPMOSINTNTRLEN": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", + "GTRSVD5": "GTPE2_CHANNEL_GTRSVD5", + "DRPDO9": "GTPE2_CHANNEL_DRPDO9", + "EYESCANTRIGGER": "GTPE2_CHANNEL_EYESCANTRIGGER", + "SCANMODEB": "GTPE2_CHANNEL_SCANMODEB", + "DRPDO15": "GTPE2_CHANNEL_DRPDO15", + "TXPRBSSEL0": "GTPE2_CHANNEL_TXPRBSSEL0", + "DMONITOROUT3": "GTPE2_CHANNEL_DMONITOROUT3", + "TSTIN14": "GTPE2_CHANNEL_TSTIN14", + "TXUSERRDY": "GTPE2_CHANNEL_TXUSERRDY", + "DRPDO6": "GTPE2_CHANNEL_DRPDO6", + "RXDLYOVRDEN": "GTPE2_CHANNEL_RXDLYOVRDEN", + "DMONITOROUT6": "GTPE2_CHANNEL_DMONITOROUT6", + "RXLPMHFHOLD": "GTPE2_CHANNEL_RXLPMHFHOLD", + "RXCHARISK3": "GTPE2_CHANNEL_RXCHARISK3", + "PMASCANOUT3": "GTPE2_CHANNEL_PMASCANOUT3", + "TXDATA22": "GTPE2_CHANNEL_TXDATA22", + "RXDISPERR3": "GTPE2_CHANNEL_RXDISPERR3", + "TXOUTCLK": "GTPE2_CHANNEL_GTTXOUTCLK_2", + "RXCLKCORCNT1": "GTPE2_CHANNEL_RXCLKCORCNT1", + "RXOSINTID01": "GTPE2_CHANNEL_RXOSINTID01", + "GTRSVD10": "GTPE2_CHANNEL_GTRSVD10", + "TXCHARDISPVAL1": "GTPE2_CHANNEL_TXCHARDISPVAL1", + "RXCDRLOCK": "GTPE2_CHANNEL_RXCDRLOCK", + "RXPHALIGN": "GTPE2_CHANNEL_RXPHALIGN", + "RXNOTINTABLE1": "GTPE2_CHANNEL_RXNOTINTABLE1", + "PMASCANIN3": "GTPE2_CHANNEL_PMASCANIN3", + "RXCDRRESETRSV": "GTPE2_CHANNEL_RXCDRRESETRSV", + "RXBUFRESET": "GTPE2_CHANNEL_RXBUFRESET", + "RXPHMONITOR3": "GTPE2_CHANNEL_RXPHMONITOR3", + "TXPIPPMSEL": "GTPE2_CHANNEL_TXPIPPMSEL", + "RXDATA20": "GTPE2_CHANNEL_RXDATA20", + "DRPDO14": "GTPE2_CHANNEL_DRPDO14", + "TXSYNCDONE": "GTPE2_CHANNEL_TXSYNCDONE", + "PCSRSVDOUT4": "GTPE2_CHANNEL_PCSRSVDOUT4", + "RXELECIDLEMODE0": "GTPE2_CHANNEL_RXELECIDLEMODE0", + "PMASCANIN5": "GTPE2_CHANNEL_PMASCANIN5", + "TXCOMFINISH": "GTPE2_CHANNEL_TXCOMFINISH", + "TXDATA9": "GTPE2_CHANNEL_TXDATA9", + "DRPADDR1": "GTPE2_CHANNEL_DRPADDR1", + "TXDATA11": "GTPE2_CHANNEL_TXDATA11", + "TXRUNDISP0": "GTPE2_CHANNEL_TXRUNDISP0", + "TXBUFSTATUS0": "GTPE2_CHANNEL_TXBUFSTATUS0", + "RXPHSLIPMONITOR1": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "GTTXRESET": "GTPE2_CHANNEL_GTTXRESET", + "RXELECIDLEMODE1": "GTPE2_CHANNEL_RXELECIDLEMODE1", + "RXDATA13": "GTPE2_CHANNEL_RXDATA13", + "TXDATA27": "GTPE2_CHANNEL_TXDATA27", + "RXSYSCLKSEL0": "GTPE2_CHANNEL_RXSYSCLKSEL0", + "PMASCANCLK0": "GTPE2_CHANNEL_PMASCANCLK0", + "TXPRECURSOR2": "GTPE2_CHANNEL_TXPRECURSOR2", + "TXCOMWAKE": "GTPE2_CHANNEL_TXCOMWAKE", + "RXDATA0": "GTPE2_CHANNEL_RXDATA0", + "GTPTXN": "GTPE2_CHANNEL_TXN", + "TXDLYOVRDEN": "GTPE2_CHANNEL_TXDLYOVRDEN", + "RXOSHOLD": "GTPE2_CHANNEL_RXOSHOLD", + "RXLPMRESET": "GTPE2_CHANNEL_RXLPMRESET", + "PCSRSVDIN4": "GTPE2_CHANNEL_PCSRSVDIN4", + "TXSYNCIN": "GTPE2_CHANNEL_TXSYNCIN", + "RXCHBONDO3": "GTPE2_CHANNEL_RXCHBONDO3", + "PCSRSVDIN7": "GTPE2_CHANNEL_PCSRSVDIN7", + "TSTIN3": "GTPE2_CHANNEL_TSTIN3", + "TXGEARBOXREADY": "GTPE2_CHANNEL_TXGEARBOXREADY", + "GTRSVD1": "GTPE2_CHANNEL_GTRSVD1", + "RXDATA22": "GTPE2_CHANNEL_RXDATA22", + "SCANIN4": "GTPE2_CHANNEL_SCANIN4", + "DRPDI12": "GTPE2_CHANNEL_DRPDI12", + "TXDATA31": "GTPE2_CHANNEL_TXDATA31", + "RXSTARTOFSEQ1": "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "PMASCANIN6": "GTPE2_CHANNEL_PMASCANIN6", + "TXRESETDONE": "GTPE2_CHANNEL_TXRESETDONE", + "TXHEADER1": "GTPE2_CHANNEL_TXHEADER1", + "RXDATA2": "GTPE2_CHANNEL_RXDATA2", + "TXRUNDISP2": "GTPE2_CHANNEL_TXRUNDISP2", + "DRPADDR3": "GTPE2_CHANNEL_DRPADDR3", + "TXDATA13": "GTPE2_CHANNEL_TXDATA13", + "TXPMARESET": "GTPE2_CHANNEL_TXPMARESET", + "RXRATE2": "GTPE2_CHANNEL_RXRATE2", + "RXOOBRESET": "GTPE2_CHANNEL_RXOOBRESET", + "DRPADDR2": "GTPE2_CHANNEL_DRPADDR2", + "DRPDO0": "GTPE2_CHANNEL_DRPDO0", + "RXDATA21": "GTPE2_CHANNEL_RXDATA21", + "GTRSVD14": "GTPE2_CHANNEL_GTRSVD14", + "TXDATA23": "GTPE2_CHANNEL_TXDATA23", + "SIGVALIDCLK": "GTPE2_CHANNEL_SIGVALIDCLK", + "PCSRSVDOUT10": "GTPE2_CHANNEL_PCSRSVDOUT10", + "RXRATE1": "GTPE2_CHANNEL_RXRATE1", + "DRPCLK": "GTPE2_CHANNEL_DRPCLK", + "RXCHBONDO1": "GTPE2_CHANNEL_RXCHBONDO1", + "TXPRECURSOR0": "GTPE2_CHANNEL_TXPRECURSOR0", + "RXDATA25": "GTPE2_CHANNEL_RXDATA25", + "DMONITORCLK": "GTPE2_CHANNEL_DMONITORCLK", + "RXCHARISCOMMA3": "GTPE2_CHANNEL_RXCHARISCOMMA3", + "RXADAPTSELTEST12": "GTPE2_CHANNEL_RXADAPTSELTEST12", + "DRPRDY": "GTPE2_CHANNEL_DRPRDY", + "RXOUTCLKSEL2": "GTPE2_CHANNEL_RXOUTCLKSEL2", + "RXOSINTPD": "GTPE2_CHANNEL_RXOSINTPD", + "DMONITOROUT11": "GTPE2_CHANNEL_DMONITOROUT11", + "RXCHANREALIGN": "GTPE2_CHANNEL_RXCHANREALIGN", + "TXOUTCLKPCS": "GTPE2_CHANNEL_TXOUTCLKPCS", + "RXOSINTCFG3": "GTPE2_CHANNEL_RXOSINTCFG3", + "DRPDO4": "GTPE2_CHANNEL_DRPDO4", + "RXBUFSTATUS0": "GTPE2_CHANNEL_RXBUFSTATUS0", + "RXCHBONDI1": "GTPE2_CHANNEL_RXCHBONDI1", + "DRPDI5": "GTPE2_CHANNEL_DRPDI5", + "TXCHARISK2": "GTPE2_CHANNEL_TXCHARISK2", + "DMONITOROUT1": "GTPE2_CHANNEL_DMONITOROUT1", + "TXOUTCLKSEL2": "GTPE2_CHANNEL_TXOUTCLKSEL2", + "TXPOSTCURSOR4": "GTPE2_CHANNEL_TXPOSTCURSOR4", + "DRPADDR0": "GTPE2_CHANNEL_DRPADDR0", + "RXDLYSRESET": "GTPE2_CHANNEL_RXDLYSRESET", + "RXSTATUS1": "GTPE2_CHANNEL_RXSTATUS1", + "RXDFEXYDEN": "GTPE2_CHANNEL_RXDFEXYDEN", + "TXPHDLYTSTCLK": "GTPE2_CHANNEL_TXPHDLYTSTCLK", + "RXPRBSERR": "GTPE2_CHANNEL_RXPRBSERR", + "RXCOMMADET": "GTPE2_CHANNEL_RXCOMMADET", + "TXSYNCMODE": "GTPE2_CHANNEL_TXSYNCMODE", + "RXADAPTSELTEST10": "GTPE2_CHANNEL_RXADAPTSELTEST10", + "RXOSINTSTROBESTARTED": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "TXPCSRESET": "GTPE2_CHANNEL_TXPCSRESET", + "PCSRSVDIN13": "GTPE2_CHANNEL_PCSRSVDIN13", + "TXUSRCLK": "GTPE2_CHANNEL_TXUSRCLK", + "RXRATEDONE": "GTPE2_CHANNEL_RXRATEDONE", + "PLL1CLK": "GTPE2_CHANNEL_PLL1CLK", + "TXSYNCOUT": "GTPE2_CHANNEL_TXSYNCOUT", + "TSTPD0": "GTPE2_CHANNEL_TSTPD0", + "RXOUTCLKPCS": "GTPE2_CHANNEL_RXOUTCLKPCS", + "PMASCANIN4": "GTPE2_CHANNEL_PMASCANIN4", + "TXDATA14": "GTPE2_CHANNEL_TXDATA14", + "PCSRSVDOUT5": "GTPE2_CHANNEL_PCSRSVDOUT5", + "SCANIN2": "GTPE2_CHANNEL_SCANIN2", + "DRPDI15": "GTPE2_CHANNEL_DRPDI15", + "TSTIN8": "GTPE2_CHANNEL_TSTIN8", + "SCANOUT2": "GTPE2_CHANNEL_SCANOUT2", + "RXCHBONDI0": "GTPE2_CHANNEL_RXCHBONDI0", + "RXDISPERR2": "GTPE2_CHANNEL_RXDISPERR2", + "TXPRECURSOR3": "GTPE2_CHANNEL_TXPRECURSOR3", + "LOOPBACK0": "GTPE2_CHANNEL_LOOPBACK0", + "RXPD1": "GTPE2_CHANNEL_RXPD1", + "RXDLYSRESETDONE": "GTPE2_CHANNEL_RXDLYSRESETDONE", + "TXDETECTRX": "GTPE2_CHANNEL_TXDETECTRX", + "TXMAINCURSOR6": "GTPE2_CHANNEL_TXMAINCURSOR6", + "RXOSINTDONE": "GTPE2_CHANNEL_RXOSINTDONE", + "RXPHSLIPMONITOR2": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "RXHEADER2": "GTPE2_CHANNEL_RXHEADER2", + "RXDLYEN": "GTPE2_CHANNEL_RXDLYEN", + "RXOSINTTESTOVRDEN": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", + "RXDATA31": "GTPE2_CHANNEL_RXDATA31", + "GTRESETSEL": "GTPE2_CHANNEL_GTRESETSEL", + "TXPOLARITY": "GTPE2_CHANNEL_TXPOLARITY", + "RXDATA12": "GTPE2_CHANNEL_RXDATA12", + "DRPDI14": "GTPE2_CHANNEL_DRPDI14", + "RXDDIEN": "GTPE2_CHANNEL_RXDDIEN", + "RXOSINTSTROBEDONE": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "DRPEN": "GTPE2_CHANNEL_DRPEN", + "RXCDRFREQRESET": "GTPE2_CHANNEL_RXCDRFREQRESET", + "TXCHARDISPVAL2": "GTPE2_CHANNEL_TXCHARDISPVAL2", + "TXOUTCLKFABRIC": "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "RXSYNCMODE": "GTPE2_CHANNEL_RXSYNCMODE", + "DRPDI1": "GTPE2_CHANNEL_DRPDI1", + "PCSRSVDIN2": "GTPE2_CHANNEL_PCSRSVDIN2", + "RXOSINTID02": "GTPE2_CHANNEL_RXOSINTID02", + "TXMARGIN1": "GTPE2_CHANNEL_TXMARGIN1", + "TXDIFFCTRL0": "GTPE2_CHANNEL_TXDIFFCTRL0", + "RXBYTEREALIGN": "GTPE2_CHANNEL_RXBYTEREALIGN", + "RXDATA29": "GTPE2_CHANNEL_RXDATA29", + "TXMAINCURSOR2": "GTPE2_CHANNEL_TXMAINCURSOR2", + "RXPHSLIPMONITOR0": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "TSTIN18": "GTPE2_CHANNEL_TSTIN18", + "TXDATA18": "GTPE2_CHANNEL_TXDATA18", + "TXPOSTCURSOR1": "GTPE2_CHANNEL_TXPOSTCURSOR1", + "TSTPD1": "GTPE2_CHANNEL_TSTPD1", + "TXDATA5": "GTPE2_CHANNEL_TXDATA5", + "RXLPMLFOVRDEN": "GTPE2_CHANNEL_RXLPMLFOVRDEN", + "PCSRSVDIN3": "GTPE2_CHANNEL_PCSRSVDIN3", + "RXDLYTESTENB": "GTPE2_CHANNEL_RXDLYTESTENB", + "SCANENB": "GTPE2_CHANNEL_SCANENB", + "RXPCSRESET": "GTPE2_CHANNEL_RXPCSRESET", + "RXDATA14": "GTPE2_CHANNEL_RXDATA14", + "RXCHBONDLEVEL0": "GTPE2_CHANNEL_RXCHBONDLEVEL0", + "TSTIN2": "GTPE2_CHANNEL_TSTIN2", + "PHYSTATUS": "GTPE2_CHANNEL_PHYSTATUS", + "RXDATAVALID0": "GTPE2_CHANNEL_RXDATAVALID0", + "SCANOUT4": "GTPE2_CHANNEL_SCANOUT4", + "PMASCANMODEB": "GTPE2_CHANNEL_PMASCANMODEB", + "TXPISOPD": "GTPE2_CHANNEL_TXPISOPD", + "RXMCOMMAALIGNEN": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", + "TXDLYUPDOWN": "GTPE2_CHANNEL_TXDLYUPDOWN", + "EYESCANDATAERROR": "GTPE2_CHANNEL_EYESCANDATAERROR", + "TXDATA17": "GTPE2_CHANNEL_TXDATA17", + "DRPDO3": "GTPE2_CHANNEL_DRPDO3", + "PCSRSVDOUT8": "GTPE2_CHANNEL_PCSRSVDOUT8", + "TXCHARDISPVAL0": "GTPE2_CHANNEL_TXCHARDISPVAL0", + "RXDEBUGPULSE": "GTPE2_CHANNEL_RXDEBUGPULSE", + "PCSRSVDIN5": "GTPE2_CHANNEL_PCSRSVDIN5", + "PLL1REFCLK": "GTPE2_CHANNEL_PLL1REFCLK", + "DRPDI0": "GTPE2_CHANNEL_DRPDI0", + "TXDATA19": "GTPE2_CHANNEL_TXDATA19", + "RXELECIDLE": "GTPE2_CHANNEL_RXELECIDLE", + "TX8B10BBYPASS2": "GTPE2_CHANNEL_TX8B10BBYPASS2", + "PCSRSVDOUT6": "GTPE2_CHANNEL_PCSRSVDOUT6", + "TXPRECURSOR1": "GTPE2_CHANNEL_TXPRECURSOR1", + "RXADAPTSELTEST1": "GTPE2_CHANNEL_RXADAPTSELTEST1", + "RXLPMLFHOLD": "GTPE2_CHANNEL_RXLPMLFHOLD", + "TXDATA16": "GTPE2_CHANNEL_TXDATA16", + "GTRSVD7": "GTPE2_CHANNEL_GTRSVD7", + "TXDATA8": "GTPE2_CHANNEL_TXDATA8", + "SCANIN3": "GTPE2_CHANNEL_SCANIN3", + "TXPRBSFORCEERR": "GTPE2_CHANNEL_TXPRBSFORCEERR", + "TXRUNDISP1": "GTPE2_CHANNEL_TXRUNDISP1", + "TSTIN10": "GTPE2_CHANNEL_TSTIN10", + "DRPADDR8": "GTPE2_CHANNEL_DRPADDR8", + "RXSTATUS0": "GTPE2_CHANNEL_RXSTATUS0", + "TXSEQUENCE1": "GTPE2_CHANNEL_TXSEQUENCE1", + "GTRSVD3": "GTPE2_CHANNEL_GTRSVD3", + "RXDATA17": "GTPE2_CHANNEL_RXDATA17", + "RXPHOVRDEN": "GTPE2_CHANNEL_RXPHOVRDEN", + "TXSWING": "GTPE2_CHANNEL_TXSWING", + "PMASCANIN2": "GTPE2_CHANNEL_PMASCANIN2", + "PMASCANIN1": "GTPE2_CHANNEL_PMASCANIN1", + "RXRESETDONE": "GTPE2_CHANNEL_RXRESETDONE", + "TXDATA0": "GTPE2_CHANNEL_TXDATA0", + "RXCHBONDEN": "GTPE2_CHANNEL_RXCHBONDEN", + "RXDATA9": "GTPE2_CHANNEL_RXDATA9", + "RXCHARISK1": "GTPE2_CHANNEL_RXCHARISK1", + "DRPADDR6": "GTPE2_CHANNEL_DRPADDR6", + "TXRATEDONE": "GTPE2_CHANNEL_TXRATEDONE", + "RXOUTCLKSEL0": "GTPE2_CHANNEL_RXOUTCLKSEL0", + "TXDATA1": "GTPE2_CHANNEL_TXDATA1", + "TSTPD2": "GTPE2_CHANNEL_TSTPD2", + "RXRATEMODE": "GTPE2_CHANNEL_RXRATEMODE", + "RXOSINTEN": "GTPE2_CHANNEL_RXOSINTEN", + "PMASCANOUT0": "GTPE2_CHANNEL_PMASCANOUT0", + "DRPDO12": "GTPE2_CHANNEL_DRPDO12", + "TXPIPPMSTEPSIZE2": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", + "RXPHALIGNEN": "GTPE2_CHANNEL_RXPHALIGNEN", + "GTRSVD4": "GTPE2_CHANNEL_GTRSVD4", + "TSTIN17": "GTPE2_CHANNEL_TSTIN17", + "TXHEADER0": "GTPE2_CHANNEL_TXHEADER0", + "RXOSINTID00": "GTPE2_CHANNEL_RXOSINTID00", + "RXCHARISCOMMA2": "GTPE2_CHANNEL_RXCHARISCOMMA2", + "RXADAPTSELTEST5": "GTPE2_CHANNEL_RXADAPTSELTEST5", + "DRPDI7": "GTPE2_CHANNEL_DRPDI7", + "DRPDI6": "GTPE2_CHANNEL_DRPDI6", + "DMONITOROUT12": "GTPE2_CHANNEL_DMONITOROUT12", + "TXDATA10": "GTPE2_CHANNEL_TXDATA10", + "PMASCANENB": "GTPE2_CHANNEL_PMASCANENB", + "TXCHARDISPMODE2": "GTPE2_CHANNEL_TXCHARDISPMODE2", + "PMARSVDIN2": "GTPE2_CHANNEL_PMARSVDIN2", + "RXCHANISALIGNED": "GTPE2_CHANNEL_RXCHANISALIGNED", + "GTPTXP": "GTPE2_CHANNEL_TXP", + "RXBUFSTATUS2": "GTPE2_CHANNEL_RXBUFSTATUS2", + "RXPHDLYRESET": "GTPE2_CHANNEL_RXPHDLYRESET", + "PMASCANCLK1": "GTPE2_CHANNEL_PMASCANCLK1", + "TSTPD4": "GTPE2_CHANNEL_TSTPD4", + "TXPRECURSOR4": "GTPE2_CHANNEL_TXPRECURSOR4", + "DMONITOROUT10": "GTPE2_CHANNEL_DMONITOROUT10", + "DRPADDR7": "GTPE2_CHANNEL_DRPADDR7", + "DMONITOROUT0": "GTPE2_CHANNEL_DMONITOROUT0", + "TXDATA24": "GTPE2_CHANNEL_TXDATA24", + "TXDIFFCTRL1": "GTPE2_CHANNEL_TXDIFFCTRL1", + "TXDATA28": "GTPE2_CHANNEL_TXDATA28", + "TXSEQUENCE4": "GTPE2_CHANNEL_TXSEQUENCE4", + "DMONITOROUT4": "GTPE2_CHANNEL_DMONITOROUT4", + "TXBUFDIFFCTRL1": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", + "DRPDO7": "GTPE2_CHANNEL_DRPDO7", + "EYESCANRESET": "GTPE2_CHANNEL_EYESCANRESET", + "RXPD0": "GTPE2_CHANNEL_RXPD0", + "DRPADDR5": "GTPE2_CHANNEL_DRPADDR5", + "RXOUTCLK": "GTPE2_CHANNEL_GTRXOUTCLK_2", + "TXSYNCALLIN": "GTPE2_CHANNEL_TXSYNCALLIN", + "RXHEADER0": "GTPE2_CHANNEL_RXHEADER0", + "TSTIN0": "GTPE2_CHANNEL_TSTIN0", + "RXHEADER1": "GTPE2_CHANNEL_RXHEADER1", + "DRPDO2": "GTPE2_CHANNEL_DRPDO2", + "TXDLYSRESET": "GTPE2_CHANNEL_TXDLYSRESET", + "TX8B10BBYPASS0": "GTPE2_CHANNEL_TX8B10BBYPASS0", + "TSTIN5": "GTPE2_CHANNEL_TSTIN5", + "DRPDO8": "GTPE2_CHANNEL_DRPDO8", + "RXCHARISK0": "GTPE2_CHANNEL_RXCHARISK0", + "RXDATA10": "GTPE2_CHANNEL_RXDATA10", + "RXOSINTOVRDEN": "GTPE2_CHANNEL_RXOSINTOVRDEN", + "PMARSVDOUT0": "GTPE2_CHANNEL_PMARSVDOUT0", + "RXDATA27": "GTPE2_CHANNEL_RXDATA27", + "GTPRXN": "GTPE2_CHANNEL_RXN", + "DRPDO1": "GTPE2_CHANNEL_DRPDO1", + "PCSRSVDIN10": "GTPE2_CHANNEL_PCSRSVDIN10", + "DRPDO11": "GTPE2_CHANNEL_DRPDO11", + "DRPDI3": "GTPE2_CHANNEL_DRPDI3", + "GTRSVD13": "GTPE2_CHANNEL_GTRSVD13", + "TSTIN13": "GTPE2_CHANNEL_TSTIN13", + "TXDATA25": "GTPE2_CHANNEL_TXDATA25", + "TXINHIBIT": "GTPE2_CHANNEL_TXINHIBIT", + "PCSRSVDOUT1": "GTPE2_CHANNEL_PCSRSVDOUT1", + "PCSRSVDOUT15": "GTPE2_CHANNEL_PCSRSVDOUT15", + "RXCDRRESET": "GTPE2_CHANNEL_RXCDRRESET", + "TXBUFDIFFCTRL2": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", + "PCSRSVDOUT12": "GTPE2_CHANNEL_PCSRSVDOUT12", + "CLKRSVD0": "GTPE2_CHANNEL_CLKRSVD0", + "RXCHBONDMASTER": "GTPE2_CHANNEL_RXCHBONDMASTER", + "TXDIFFCTRL2": "GTPE2_CHANNEL_TXDIFFCTRL2", + "RXPHSLIPMONITOR3": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "TXSTARTSEQ": "GTPE2_CHANNEL_TXSTARTSEQ", + "TXCHARISK1": "GTPE2_CHANNEL_TXCHARISK1", + "RXCHBONDLEVEL1": "GTPE2_CHANNEL_RXCHBONDLEVEL1", + "DRPDO13": "GTPE2_CHANNEL_DRPDO13", + "SCANIN0": "GTPE2_CHANNEL_SCANIN0", + "TXDATA12": "GTPE2_CHANNEL_TXDATA12", + "RXDATA5": "GTPE2_CHANNEL_RXDATA5", + "TXPOSTCURSOR0": "GTPE2_CHANNEL_TXPOSTCURSOR0", + "RXPHMONITOR0": "GTPE2_CHANNEL_RXPHMONITOR0", + "TXSEQUENCE6": "GTPE2_CHANNEL_TXSEQUENCE6", + "RXCHARISCOMMA1": "GTPE2_CHANNEL_RXCHARISCOMMA1", + "RXDATA30": "GTPE2_CHANNEL_RXDATA30", + "RXCHBONDO2": "GTPE2_CHANNEL_RXCHBONDO2", + "RXDATA23": "GTPE2_CHANNEL_RXDATA23", + "TXRATE1": "GTPE2_CHANNEL_TXRATE1", + "RXADAPTSELTEST11": "GTPE2_CHANNEL_RXADAPTSELTEST11", + "PLL0REFCLK": "GTPE2_CHANNEL_PLL0REFCLK", + "RESETOVRD": "GTPE2_CHANNEL_RESETOVRD", + "TXBUFSTATUS1": "GTPE2_CHANNEL_TXBUFSTATUS1", + "RXSTARTOFSEQ0": "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "PMASCANOUT2": "GTPE2_CHANNEL_PMASCANOUT2", + "RXDATA11": "GTPE2_CHANNEL_RXDATA11", + "TXMAINCURSOR4": "GTPE2_CHANNEL_TXMAINCURSOR4", + "PMASCANOUT5": "GTPE2_CHANNEL_PMASCANOUT5", + "RXOSINTHOLD": "GTPE2_CHANNEL_RXOSINTHOLD", + "TXPHALIGN": "GTPE2_CHANNEL_TXPHALIGN", + "DRPDI2": "GTPE2_CHANNEL_DRPDI2", + "RXCHBONDI2": "GTPE2_CHANNEL_RXCHBONDI2", + "TXPHDLYRESET": "GTPE2_CHANNEL_TXPHDLYRESET", + "RXPMARESET": "GTPE2_CHANNEL_RXPMARESET", + "RXSYNCIN": "GTPE2_CHANNEL_RXSYNCIN", + "RXDATA8": "GTPE2_CHANNEL_RXDATA8", + "TXDEEMPH": "GTPE2_CHANNEL_TXDEEMPH", + "RXPHALIGNDONE": "GTPE2_CHANNEL_RXPHALIGNDONE", + "RXOSOVRDEN": "GTPE2_CHANNEL_RXOSOVRDEN", + "TSTIN19": "GTPE2_CHANNEL_TSTIN19", + "TXDATA15": "GTPE2_CHANNEL_TXDATA15", + "RXPMARESETDONE": "GTPE2_CHANNEL_RXPMARESETDONE", + "RXDISPERR0": "GTPE2_CHANNEL_RXDISPERR0", + "RXSYSCLKSEL1": "GTPE2_CHANNEL_RXSYSCLKSEL1", + "GTRSVD11": "GTPE2_CHANNEL_GTRSVD11", + "DRPDO10": "GTPE2_CHANNEL_DRPDO10", + "PCSRSVDOUT3": "GTPE2_CHANNEL_PCSRSVDOUT3", + "SCANOUT3": "GTPE2_CHANNEL_SCANOUT3", + "RXDATA7": "GTPE2_CHANNEL_RXDATA7", + "TXDLYTESTENB": "GTPE2_CHANNEL_TXDLYTESTENB", + "RXOSINTID03": "GTPE2_CHANNEL_RXOSINTID03", + "TXPRECURSORINV": "GTPE2_CHANNEL_TXPRECURSORINV", + "TXPIPPMSTEPSIZE0": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", + "TSTIN15": "GTPE2_CHANNEL_TSTIN15", + "PMASCANCLK3": "GTPE2_CHANNEL_PMASCANCLK3", + "PMARSVDIN1": "GTPE2_CHANNEL_PMARSVDIN1", + "RXCHBONDLEVEL2": "GTPE2_CHANNEL_RXCHBONDLEVEL2", + "PCSRSVDIN1": "GTPE2_CHANNEL_PCSRSVDIN1", + "RXNOTINTABLE2": "GTPE2_CHANNEL_RXNOTINTABLE2", + "TXDATA30": "GTPE2_CHANNEL_TXDATA30", + "TSTPDOVRDB": "GTPE2_CHANNEL_TSTPDOVRDB", + "RXOSINTSTARTED": "GTPE2_CHANNEL_RXOSINTSTARTED", + "TSTIN6": "GTPE2_CHANNEL_TSTIN6", + "PMASCANOUT6": "GTPE2_CHANNEL_PMASCANOUT6", + "TXSEQUENCE0": "GTPE2_CHANNEL_TXSEQUENCE0", + "SCANIN5": "GTPE2_CHANNEL_SCANIN5", + "RXDATA1": "GTPE2_CHANNEL_RXDATA1", + "RXADAPTSELTEST13": "GTPE2_CHANNEL_RXADAPTSELTEST13", + "RXDATA24": "GTPE2_CHANNEL_RXDATA24", + "TXDLYSRESETDONE": "GTPE2_CHANNEL_TXDLYSRESETDONE", + "TXDATA20": "GTPE2_CHANNEL_TXDATA20", + "SCANCLK": "GTPE2_CHANNEL_SCANCLK", + "RXPRBSSEL0": "GTPE2_CHANNEL_RXPRBSSEL0", + "TXCOMINIT": "GTPE2_CHANNEL_TXCOMINIT", + "RXUSERRDY": "GTPE2_CHANNEL_RXUSERRDY", + "TXSEQUENCE3": "GTPE2_CHANNEL_TXSEQUENCE3", + "TXOUTCLKSEL0": "GTPE2_CHANNEL_TXOUTCLKSEL0", + "PMASCANOUT4": "GTPE2_CHANNEL_PMASCANOUT4", + "TXDATA4": "GTPE2_CHANNEL_TXDATA4", + "TX8B10BBYPASS3": "GTPE2_CHANNEL_TX8B10BBYPASS3", + "SCANIN1": "GTPE2_CHANNEL_SCANIN1", + "DRPWE": "GTPE2_CHANNEL_DRPWE", + "TXDATA7": "GTPE2_CHANNEL_TXDATA7", + "TXPRBSSEL2": "GTPE2_CHANNEL_TXPRBSSEL2", + "RXDISPERR1": "GTPE2_CHANNEL_RXDISPERR1", + "PCSRSVDIN0": "GTPE2_CHANNEL_PCSRSVDIN0", + "TXRATEMODE": "GTPE2_CHANNEL_TXRATEMODE", + "RXRATE0": "GTPE2_CHANNEL_RXRATE0", + "RXOSINTNTRLEN": "GTPE2_CHANNEL_RXOSINTNTRLEN", + "TXSEQUENCE5": "GTPE2_CHANNEL_TXSEQUENCE5", + "RXDATA4": "GTPE2_CHANNEL_RXDATA4", + "TXPHINITDONE": "GTPE2_CHANNEL_TXPHINITDONE", + "DMONITOROUT8": "GTPE2_CHANNEL_DMONITOROUT8", + "RXDLYBYPASS": "GTPE2_CHANNEL_RXDLYBYPASS", + "RXPRBSCNTRESET": "GTPE2_CHANNEL_RXPRBSCNTRESET", + "RXOSINTCFG1": "GTPE2_CHANNEL_RXOSINTCFG1", + "DRPDI8": "GTPE2_CHANNEL_DRPDI8", + "PCSRSVDIN15": "GTPE2_CHANNEL_PCSRSVDIN15", + "RXDATA6": "GTPE2_CHANNEL_RXDATA6", + "RXDATA28": "GTPE2_CHANNEL_RXDATA28", + "TXPOSTCURSOR2": "GTPE2_CHANNEL_TXPOSTCURSOR2", + "DRPDI11": "GTPE2_CHANNEL_DRPDI11", + "RXADAPTSELTEST2": "GTPE2_CHANNEL_RXADAPTSELTEST2", + "PCSRSVDIN14": "GTPE2_CHANNEL_PCSRSVDIN14", + "RXDATA26": "GTPE2_CHANNEL_RXDATA26", + "DMONITOROUT14": "GTPE2_CHANNEL_DMONITOROUT14" + }, + "type": "GTPE2_CHANNEL", + "prefix": "GTPE2_CHANNEL", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "O": "GTPE2_CHANNEL_RXN_PAD" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y22", + "x_coord": 1, + "y_coord": 22 + }, + { + "site_pins": { + "O": "GTPE2_CHANNEL_RXP_PAD" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y23", + "x_coord": 1, + "y_coord": 23 + }, + { + "site_pins": { + "I": "GTPE2_CHANNEL_TXN_PAD" + }, + "type": "OPAD", + "prefix": "OPAD", + "name": "X0Y2", + "x_coord": 0, + "y_coord": 2 + }, + { + "site_pins": { + "I": "GTPE2_CHANNEL_TXP_PAD" + }, + "type": "OPAD", + "prefix": "OPAD", + "name": "X0Y3", + "x_coord": 0, + "y_coord": 3 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_GTP_CHANNEL_3.json b/artix7/tile_type_GTP_CHANNEL_3.json index c79ff57..af29ca6 100644 --- a/artix7/tile_type_GTP_CHANNEL_3.json +++ b/artix7/tile_type_GTP_CHANNEL_3.json @@ -1,5922 +1,5922 @@ { - "wires": [ - "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "GTPE2_IMUX18_2", - "GTPE2_LOGIC_OUTS_B1_3", - "GTPE2_IMUX26_4", - "GTPE2_CHANNEL_TXDATA13", - "GTPE2_CHANNEL_PMARSVDOUT0", - "GTPE2_FAN1_0", - "GTPE2_LOGIC_OUTS_B14_6", - "GTPE2_LOGIC_OUTS_B13_2", - "GTPE2_FAN3_5", - "GTPE2_IMUX16_6", - "GTPE2_CHANNEL_SETERRSTATUS", - "GTPE2_IMUX43_9", - "GTPE2_BYP5_3", - "GTPE2_LOGIC_OUTS_B19_5", - "GTPE2_IMUX34_0", - "GTPE2_LOGIC_OUTS_B10_3", - "GTPE2_LOGIC_OUTS_B5_1", - "GTPE2_IMUX18_1", - "GTPE2_IMUX6_4", - "GTPE2_IMUX21_5", - "GTPE2_CHANNEL_RXPHDLYPD", - "GTPE2_IMUX40_9", - "GTPE2_CHANNEL_TXMAINCURSOR3", - "GTPE2_CHANNEL_TSTCLK0", - "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "GTPE2_LOGIC_OUTS_B9_7", - "GTPE2_LOGIC_OUTS_B13_8", - "GTPE2_CHANNEL_RXDATAVALID0", - "GTPE2_CHANNEL_PCSRSVDOUT0", - "GTPE2_CHANNEL_RXSYNCMODE", - "GTPE2_LOGIC_OUTS_B10_0", - "GTPE2_CHANNEL_SCANOUT3", - "GTPE2_CHANNEL_GTTXOUTCLK_3", - "GTPE2_CHANNEL_RXOSOVRDEN", - "GTPE2_IMUX47_9", - "GTPE2_CHANNEL_RXCHBONDI1", - "GTPE2_CHANNEL_RXCHBONDI2", - "GTPE2_FAN2_1", - "GTPE2_CTRL1_2", - "GTPE2_CHANNEL_PCSRSVDOUT8", - "GTPE2_LOGIC_OUTS_B18_2", - "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "GTPE2_IMUX32_4", - "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "GTPE2_FAN1_8", - "GTPE2_CHANNEL_RXOUTCLK_3", - "GTPE2_CHANNEL_TXDATA11", - "GTPE2_LOGIC_OUTS_B15_5", - "GTPE2_IMUX15_8", - "GTPE2_CHANNEL_TXDATA21", - "GTPE2_CLK0_4", - "GTPE2_CHANNEL_RXPCSRESET", - "GTPE2_IMUX14_4", - "GTPE2_LOGIC_OUTS_B23_2", - "GTPE2_LOGIC_OUTS_B5_6", - "GTPE2_CHANNEL_PCSRSVDIN14", - "GTPE2_FAN2_5", - "GTPE2_CHANNEL_PCSRSVDOUT10", - "GTPE2_IMUX14_6", - "GTPE2_IMUX15_1", - "GTPE2_IMUX30_7", - "GTPE2_CHANNEL_PMASCANOUT4", - "GTPE2_CHANNEL_TXDATA2", - "GTPE2_IMUX41_6", - "GTPE2_IMUX47_4", - "GTPE2_FAN6_0", - "GTPE2_CHANNEL_TXPRECURSOR4", - "GTPE2_FAN3_3", - "GTPE2_CHANNEL_TX8B10BBYPASS0", - "GTPE2_CHANNEL_PMASCANOUT5", - "GTPE2_LOGIC_OUTS_B14_5", - "GTPE2_CHANNEL_TXDLYTESTENB", - "GTPE2_CHANNEL_RXVALID", - "GTPE2_BYP1_9", - "GTPE2_LOGIC_OUTS_B7_6", - "GTPE2_CHANNEL_RXDATA24", - "GTPE2_IMUX10_2", - "GTPE2_CHANNEL_DRPADDR4", - "GTPE2_IMUX2_1", - "GTPE2_IMUX4_4", - "GTPE2_CHANNEL_PMASCANIN0", - "GTPE2_FAN3_7", - "GTPE2_CHANNEL_TXPMARESETDONE", - "GTPE2_CHANNEL_RXSYNCIN", - "GTPE2_LOGIC_OUTS_B8_10", - "GTPE2_CHANNEL_RXRATEMODE", - "GTPE2_LOGIC_OUTS_B10_9", - "GTPE2_IMUX31_10", - "GTPE2_CHANNEL_DRPDO1", - "GTPE2_CTRL0_7", - "GTPE2_CHANNEL_PLLCLK1", - "GTPE2_IMUX29_3", - "GTPE2_BYP6_1", - "GTPE2_CHANNEL_RXCOMINITDET", - "GTPE2_CHANNEL_TXDIFFPD", - "GTPE2_IMUX27_2", - "GTPE2_CHANNEL_TXDIFFCTRL0", - "GTPE2_IMUX40_1", - "GTPE2_FAN6_2", - "GTPE2_CHANNEL_TXPOSTCURSOR3", - "GTPE2_IMUX37_10", - "GTPE2_LOGIC_OUTS_B15_4", - "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "GTPE2_CHANNEL_TXMAINCURSOR6", - "GTPE2_IMUX27_1", - "GTPE2_CTRL1_7", - "GTPE2_LOGIC_OUTS_B1_5", - "GTPE2_CHANNEL_TSTIN2", - "GTPE2_CHANNEL_RXDATA9", - "GTPE2_IMUX3_5", - "GTPE2_CHANNEL_RXPHALIGNDONE", - "GTPE2_CHANNEL_RXPHMONITOR3", - "GTPE2_LOGIC_OUTS_B2_9", - "GTPE2_IMUX31_1", - "GTPE2_IMUX17_10", - "GTPE2_CHANNEL_RXCHARISCOMMA0", - "GTPE2_LOGIC_OUTS_B8_4", - "GTPE2_FAN7_6", - "GTPE2_IMUX41_2", - "GTPE2_IMUX12_0", - "GTPE2_LOGIC_OUTS_B10_5", - "GTPE2_IMUX10_0", - "GTPE2_LOGIC_OUTS_B17_8", - "GTPE2_FAN3_9", - "GTPE2_CHANNEL_RXCHARISCOMMA1", - "GTPE2_IMUX33_7", - "GTPE2_LOGIC_OUTS_B5_9", - "GTPE2_IMUX36_7", - "GTPE2_IMUX3_7", - "GTPE2_LOGIC_OUTS_B12_9", - "GTPE2_IMUX16_1", - "GTPE2_LOGIC_OUTS_B23_5", - "GTPE2_FAN2_2", - "GTPE2_IMUX0_5", - "GTPE2_CHANNEL_TXOUTCLK_0", - "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "GTPE2_CHANNEL_PCSRSVDIN6", - "GTPE2_IMUX33_3", - "GTPE2_IMUX41_4", - "GTPE2_IMUX46_6", - "GTPE2_CHANNEL_TXHEADER0", - "GTPE2_BYP0_1", - "GTPE2_IMUX1_9", - "GTPE2_CHANNEL_PCSRSVDIN8", - "GTPE2_IMUX13_4", - "GTPE2_CHANNEL_RXADAPTSELTEST1", - "GTPE2_IMUX32_9", - "GTPE2_BYP4_5", - "GTPE2_CHANNEL_RXADAPTSELTEST8", - "GTPE2_CHANNEL_TXDLYUPDOWN", - "GTPE2_IMUX44_7", - "GTPE2_IMUX19_8", - "GTPE2_IMUX41_7", - "GTPE2_IMUX19_2", - "GTPE2_CHANNEL_GTRSVD8", - "GTPE2_IMUX4_0", - "GTPE2_BYP6_7", - "GTPE2_IMUX25_10", - "GTPE2_FAN7_3", - "GTPE2_CHANNEL_RXCHBONDSLAVE", - "GTPE2_IMUX24_3", - "GTPE2_LOGIC_OUTS_B5_8", - "GTPE2_FAN0_7", - "GTPE2_IMUX45_6", - "GTPE2_CTRL0_2", - "GTPE2_IMUX43_5", - "GTPE2_CHANNEL_PCSRSVDOUT13", - "GTPE2_IMUX17_4", - "GTPE2_BYP3_7", - "GTPE2_CHANNEL_SCANOUT0", - "GTPE2_IMUX43_1", - "GTPE2_CHANNEL_RXDISPERR2", - "GTPE2_CHANNEL_RXOUTCLK_1", - "GTPE2_CHANNEL_GTRSVD1", - "GTPE2_IMUX13_8", - "GTPE2_IMUX20_4", - "GTPE2_BYP0_8", - "GTPE2_IMUX0_2", - "GTPE2_IMUX29_2", - "GTPE2_IMUX6_5", - "GTPE2_LOGIC_OUTS_B2_0", - "GTPE2_LOGIC_OUTS_B1_2", - "GTPE2_IMUX18_6", - "GTPE2_LOGIC_OUTS_B15_7", - "GTPE2_LOGIC_OUTS_B1_6", - "GTPE2_LOGIC_OUTS_B16_8", - "GTPE2_IMUX44_3", - "GTPE2_CHANNEL_PMARSVDIN1", - "GTPE2_CHANNEL_TXDATA1", - "GTPE2_CHANNEL_RXOSINTID00", - "GTPE2_LOGIC_OUTS_B3_0", - "GTPE2_CHANNEL_RXCHBONDO1", - "GTPE2_IMUX2_3", - "GTPE2_CHANNEL_RXOSINTID03", - "GTPE2_CHANNEL_PMASCANOUT1", - "GTPE2_LOGIC_OUTS_B19_3", - "GTPE2_CHANNEL_TXHEADER2", - "GTPE2_LOGIC_OUTS_B10_2", - "GTPE2_IMUX45_0", - "GTPE2_CHANNEL_DMONITOROUT6", - "GTPE2_LOGIC_OUTS_B9_3", - "GTPE2_IMUX17_8", - "GTPE2_CHANNEL_SIGVALIDCLK", - "GTPE2_IMUX31_5", - "GTPE2_LOGIC_OUTS_B2_3", - "GTPE2_FAN7_2", - "GTPE2_CHANNEL_RXPRBSSEL1", - "GTPE2_IMUX19_1", - "GTPE2_CHANNEL_PMASCANRSTEN", - "GTPE2_IMUX5_6", - "GTPE2_LOGIC_OUTS_B4_9", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "GTPE2_CHANNEL_RXPRBSCNTRESET", - "GTPE2_IMUX29_1", - "GTPE2_CHANNEL_RXDATA29", - "GTPE2_CHANNEL_RXDATA27", - "GTPE2_CHANNEL_PCSRSVDIN2", - "GTPE2_CHANNEL_PCSRSVDIN3", - "GTPE2_IMUX10_6", - "GTPE2_IMUX32_3", - "GTPE2_CHANNEL_RXOSINTHOLD", - "GTPE2_CHANNEL_DRPWE", - "GTPE2_CHANNEL_DMONITORCLK", - "GTPE2_LOGIC_OUTS_B9_1", - "GTPE2_IMUX20_7", - "GTPE2_LOGIC_OUTS_B6_2", - "GTPE2_LOGIC_OUTS_B6_3", - "GTPE2_IMUX34_10", - "GTPE2_IMUX25_5", - "GTPE2_IMUX9_6", - "GTPE2_CHANNEL_TXBUFSTATUS1", - "GTPE2_IMUX30_6", - "GTPE2_LOGIC_OUTS_B22_1", - "GTPE2_IMUX46_10", - "GTPE2_IMUX11_10", - "GTPE2_IMUX31_6", - "GTPE2_IMUX42_2", - "GTPE2_IMUX34_5", - "GTPE2_LOGIC_OUTS_B2_4", - "GTPE2_CHANNEL_RXADAPTSELTEST7", - "GTPE2_IMUX14_10", - "GTPE2_FAN0_9", - "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "GTPE2_CTRL1_3", - "GTPE2_CHANNEL_SCANIN0", - "GTPE2_FAN6_1", - "GTPE2_IMUX46_3", - "GTPE2_CHANNEL_TXSEQUENCE0", - "GTPE2_IMUX2_0", - "GTPE2_LOGIC_OUTS_B13_6", - "GTPE2_BYP4_1", - "GTPE2_CHANNEL_TXPHALIGN", - "GTPE2_CHANNEL_GTRESETSEL", - "GTPE2_LOGIC_OUTS_B13_10", - "GTPE2_CHANNEL_PLL0REFCLK", - "GTPE2_LOGIC_OUTS_B8_1", - "GTPE2_IMUX12_6", - "GTPE2_CHANNEL_RXP_PAD", - "GTPE2_IMUX25_1", - "GTPE2_IMUX29_10", - "GTPE2_IMUX30_8", - "GTPE2_IMUX2_2", - "GTPE2_LOGIC_OUTS_B14_9", - "GTPE2_LOGIC_OUTS_B23_4", - "GTPE2_IMUX30_5", - "GTPE2_CLK1_5", - "GTPE2_IMUX31_7", - "GTPE2_CHANNEL_TXMAINCURSOR4", - "GTPE2_IMUX12_3", - "GTPE2_IMUX1_5", - "GTPE2_LOGIC_OUTS_B21_7", - "GTPE2_CHANNEL_TSTIN10", - "GTPE2_IMUX45_3", - "GTPE2_CHANNEL_TXPHALIGNDONE", - "GTPE2_CHANNEL_TXDIFFCTRL3", - "GTPE2_IMUX22_9", - "GTPE2_IMUX19_4", - "GTPE2_LOGIC_OUTS_B4_7", - "GTPE2_IMUX46_8", - "GTPE2_CHANNEL_RXADAPTSELTEST12", - "GTPE2_IMUX28_1", - "GTPE2_LOGIC_OUTS_B4_6", - "GTPE2_CHANNEL_TXDEEMPH", - "GTPE2_IMUX8_8", - "GTPE2_LOGIC_OUTS_B17_10", - "GTPE2_CHANNEL_PCSRSVDIN7", - "GTPE2_LOGIC_OUTS_B4_5", - "GTPE2_IMUX31_3", - "GTPE2_CHANNEL_RXBYTEISALIGNED", - "GTPE2_CHANNEL_TSTIN8", - "GTPE2_IMUX28_8", - "GTPE2_CHANNEL_TXUSERRDY", - "GTPE2_CHANNEL_SCANIN4", - "GTPE2_CHANNEL_RXLPMLFHOLD", - "GTPE2_CHANNEL_PMARSVDIN0", - "GTPE2_IMUX12_5", - "GTPE2_FAN2_8", - "GTPE2_CHANNEL_TXRATE2", - "GTPE2_LOGIC_OUTS_B20_6", - "GTPE2_CHANNEL_TXSYNCALLIN", - "GTPE2_LOGIC_OUTS_B19_9", - "GTPE2_IMUX13_1", - "GTPE2_FAN3_2", - "GTPE2_LOGIC_OUTS_B0_4", - "GTPE2_CHANNEL_TXCHARDISPVAL0", - "GTPE2_IMUX33_2", - "GTPE2_IMUX1_4", - "GTPE2_IMUX14_8", - "GTPE2_IMUX4_10", - "GTPE2_LOGIC_OUTS_B2_5", - "GTPE2_IMUX8_6", - "GTPE2_IMUX15_2", - "GTPE2_CHANNEL_TXRATE1", - "GTPE2_BYP6_3", - "GTPE2_CHANNEL_RXNOTINTABLE2", - "GTPE2_FAN4_4", - "GTPE2_LOGIC_OUTS_B9_9", - "GTPE2_CHANNEL_TXCHARDISPMODE0", - "GTPE2_IMUX16_8", - "GTPE2_LOGIC_OUTS_B18_3", - "GTPE2_IMUX36_3", - "GTPE2_CHANNEL_TXCOMFINISH", - "GTPE2_IMUX11_4", - "GTPE2_IMUX14_9", - "GTPE2_IMUX20_2", - "GTPE2_IMUX16_5", - "GTPE2_CHANNEL_RXOOBRESET", - "GTPE2_CHANNEL_RXOSHOLD", - "GTPE2_CHANNEL_GTRXRESET", - "GTPE2_CHANNEL_TXPHINIT", - "GTPE2_CHANNEL_RXADAPTSELTEST3", - "GTPE2_IMUX36_5", - "GTPE2_BYP2_5", - "GTPE2_CLK0_9", - "GTPE2_CHANNEL_DRPDO5", - "GTPE2_IMUX20_6", - "GTPE2_CHANNEL_SCANMODEB", - "GTPE2_IMUX36_4", - "GTPE2_CLK0_10", - "GTPE2_LOGIC_OUTS_B3_6", - "GTPE2_CHANNEL_TXDATA17", - "GTPE2_LOGIC_OUTS_B6_10", - "GTPE2_CHANNEL_RXPD0", - "GTPE2_IMUX1_2", - "GTPE2_IMUX44_2", - "GTPE2_CHANNEL_DRPDO7", - "GTPE2_LOGIC_OUTS_B23_3", - "GTPE2_IMUX47_6", - "GTPE2_CHANNEL_RXPHDLYRESET", - "GTPE2_LOGIC_OUTS_B2_1", - "GTPE2_LOGIC_OUTS_B10_8", - "GTPE2_IMUX44_0", - "GTPE2_CHANNEL_TXCOMSAS", - "GTPE2_CHANNEL_DMONITOROUT12", - "GTPE2_CHANNEL_RXDATA8", - "GTPE2_IMUX2_4", - "GTPE2_CHANNEL_PCSRSVDOUT7", - "GTPE2_LOGIC_OUTS_B11_0", - "GTPE2_LOGIC_OUTS_B8_3", - "GTPE2_CHANNEL_RXDATAVALID1", - "GTPE2_CHANNEL_GTRSVD9", - "GTPE2_CHANNEL_TSTIN15", - "GTPE2_CHANNEL_TXCHARISK0", - "GTPE2_LOGIC_OUTS_B6_5", - "GTPE2_IMUX29_0", - "GTPE2_CHANNEL_TXOUTCLK_2", - "GTPE2_CHANNEL_RXCHARISK3", - "GTPE2_FAN7_4", - "GTPE2_CLK0_8", - "GTPE2_CHANNEL_GTRSVD3", - "GTPE2_CHANNEL_RXCHANISALIGNED", - "GTPE2_CHANNEL_RXCHBONDO3", - "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "GTPE2_IMUX26_5", - "GTPE2_LOGIC_OUTS_B10_10", - "GTPE2_CHANNEL_RXDLYBYPASS", - "GTPE2_CHANNEL_TSTCLK1", - "GTPE2_CHANNEL_TXDATA12", - "GTPE2_CHANNEL_DRPDO14", - "GTPE2_IMUX28_9", - "GTPE2_IMUX21_7", - "GTPE2_IMUX5_8", - "GTPE2_FAN2_6", - "GTPE2_IMUX42_1", - "GTPE2_CHANNEL_DMONITOROUT13", - "GTPE2_IMUX31_9", - "GTPE2_FAN0_5", - "GTPE2_IMUX8_7", - "GTPE2_IMUX39_9", - "GTPE2_LOGIC_OUTS_B22_0", - "GTPE2_CHANNEL_PCSRSVDIN12", - "GTPE2_CHANNEL_TXUSRCLK2", - "GTPE2_CHANNEL_RXDISPERR1", - "GTPE2_CHANNEL_DMONITOROUT14", - "GTPE2_IMUX24_1", - "GTPE2_LOGIC_OUTS_B11_9", - "GTPE2_LOGIC_OUTS_B21_5", - "GTPE2_IMUX8_5", - "GTPE2_CHANNEL_RXUSRCLK", - "GTPE2_IMUX47_8", - "GTPE2_FAN4_8", - "GTPE2_CHANNEL_RXDATA1", - "GTPE2_IMUX19_3", - "GTPE2_CHANNEL_RXPHALIGN", - "GTPE2_CHANNEL_PMARSVDIN3", - "GTPE2_CHANNEL_RXDLYSRESETDONE", - "GTPE2_LOGIC_OUTS_B7_5", - "GTPE2_IMUX37_5", - "GTPE2_CHANNEL_RXPHMONITOR2", - "GTPE2_FAN1_10", - "GTPE2_CHANNEL_RXDISPERR3", - "GTPE2_BYP2_9", - "GTPE2_LOGIC_OUTS_B17_6", - "GTPE2_CHANNEL_RXRATE2", - "GTPE2_IMUX15_10", - "GTPE2_CHANNEL_PMASCANOUT3", - "GTPE2_IMUX30_4", - "GTPE2_CHANNEL_RXOUTCLKSEL1", - "GTPE2_CHANNEL_GTRXOUTCLK_3", - "GTPE2_CHANNEL_RXDDIEN", - "GTPE2_CHANNEL_TXCHARISK3", - "GTPE2_IMUX42_0", - "GTPE2_IMUX36_9", - "GTPE2_LOGIC_OUTS_B21_10", - "GTPE2_IMUX2_8", - "GTPE2_CHANNEL_TXRATE0", - "GTPE2_CHANNEL_RXOSINTPD", - "GTPE2_IMUX4_8", - "GTPE2_CLK0_0", - "GTPE2_CHANNEL_RXPRBSSEL0", - "GTPE2_LOGIC_OUTS_B18_6", - "GTPE2_CHANNEL_RXDATA21", - "GTPE2_CHANNEL_TXDATA4", - "GTPE2_CHANNEL_RESETOVRD", - "GTPE2_BYP7_2", - "GTPE2_LOGIC_OUTS_B17_7", - "GTPE2_CHANNEL_TXDATA0", - "GTPE2_LOGIC_OUTS_B15_0", - "GTPE2_IMUX7_5", - "GTPE2_IMUX24_4", - "GTPE2_IMUX7_7", - "GTPE2_LOGIC_OUTS_B3_9", - "GTPE2_LOGIC_OUTS_B17_4", - "GTPE2_FAN6_5", - "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "GTPE2_LOGIC_OUTS_B16_2", - "GTPE2_CHANNEL_TXMARGIN2", - "GTPE2_IMUX28_10", - "GTPE2_CHANNEL_DRPDI5", - "GTPE2_LOGIC_OUTS_B21_1", - "GTPE2_IMUX44_8", - "GTPE2_LOGIC_OUTS_B9_10", - "GTPE2_CHANNEL_TXCHARDISPVAL2", - "GTPE2_IMUX25_6", - "GTPE2_CHANNEL_SCANIN3", - "GTPE2_LOGIC_OUTS_B16_5", - "GTPE2_LOGIC_OUTS_B23_6", - "GTPE2_IMUX40_6", - "GTPE2_IMUX12_1", - "GTPE2_CHANNEL_DRPDO11", - "GTPE2_CHANNEL_RXADAPTSELTEST6", - "GTPE2_IMUX31_2", - "GTPE2_IMUX29_4", - "GTPE2_LOGIC_OUTS_B13_9", - "GTPE2_IMUX38_6", - "GTPE2_LOGIC_OUTS_B12_7", - "GTPE2_IMUX40_10", - "GTPE2_IMUX0_6", - "GTPE2_CHANNEL_TXPRECURSOR0", - "GTPE2_LOGIC_OUTS_B21_4", - "GTPE2_LOGIC_OUTS_B16_0", - "GTPE2_FAN7_1", - "GTPE2_CHANNEL_DRPDI14", - "GTPE2_LOGIC_OUTS_B5_7", - "GTPE2_IMUX39_1", - "GTPE2_IMUX15_7", - "GTPE2_IMUX6_1", - "GTPE2_CHANNEL_TXPD0", - "GTPE2_IMUX26_2", - "GTPE2_IMUX27_5", - "GTPE2_LOGIC_OUTS_B19_2", - "GTPE2_IMUX13_5", - "GTPE2_LOGIC_OUTS_B16_4", - "GTPE2_CHANNEL_TXHEADER1", - "GTPE2_CLK1_10", - "GTPE2_IMUX41_8", - "GTPE2_BYP4_9", - "GTPE2_IMUX5_7", - "GTPE2_CHANNEL_RXDATA15", - "GTPE2_BYP2_2", - "GTPE2_BYP7_10", - "GTPE2_LOGIC_OUTS_B22_6", - "GTPE2_IMUX16_4", - "GTPE2_BYP1_2", - "GTPE2_LOGIC_OUTS_B9_6", - "GTPE2_BYP1_4", - "GTPE2_IMUX23_2", - "GTPE2_IMUX1_1", - "GTPE2_IMUX0_8", - "GTPE2_LOGIC_OUTS_B13_5", - "GTPE2_CHANNEL_TXPHOVRDEN", - "GTPE2_LOGIC_OUTS_B7_2", - "GTPE2_CHANNEL_DMONITOROUT7", - "GTPE2_LOGIC_OUTS_B17_3", - "GTPE2_CHANNEL_RXELECIDLEMODE1", - "GTPE2_CHANNEL_RXDISPERR0", - "GTPE2_LOGIC_OUTS_B2_10", - "GTPE2_IMUX17_1", - "GTPE2_CHANNEL_TXDLYHOLD", - "GTPE2_BYP3_8", - "GTPE2_CHANNEL_RXOUTCLKPCS", - "GTPE2_IMUX32_8", - "GTPE2_CHANNEL_DRPADDR7", - "GTPE2_IMUX7_9", - "GTPE2_IMUX46_5", - "GTPE2_IMUX20_1", - "GTPE2_CHANNEL_DMONITOROUT9", - "GTPE2_CHANNEL_DRPDO15", - "GTPE2_IMUX23_0", - "GTPE2_IMUX15_3", - "GTPE2_CHANNEL_RXOSINTCFG3", - "GTPE2_CHANNEL_RXDATA0", - "GTPE2_IMUX36_1", - "GTPE2_LOGIC_OUTS_B23_8", - "GTPE2_IMUX37_2", - "GTPE2_CHANNEL_TXP_PAD", - "GTPE2_IMUX43_6", - "GTPE2_CHANNEL_RXDATA18", - "GTPE2_IMUX21_9", - "GTPE2_CLK1_4", - "GTPE2_CHANNEL_TXGEARBOXREADY", - "GTPE2_LOGIC_OUTS_B10_6", - "GTPE2_LOGIC_OUTS_B20_0", - "GTPE2_IMUX6_2", - "GTPE2_IMUX23_1", - "GTPE2_CHANNEL_TXPOSTCURSOR0", - "GTPE2_BYP5_4", - "GTPE2_CHANNEL_TXDATA14", - "GTPE2_CHANNEL_GTRSVD13", - "GTPE2_CHANNEL_TXSEQUENCE1", - "GTPE2_IMUX14_7", - "GTPE2_CHANNEL_TXPHINITDONE", - "GTPE2_CHANNEL_EYESCANMODE", - "GTPE2_CHANNEL_PLL0CLK", - "GTPE2_CHANNEL_TXDETECTRX", - "GTPE2_LOGIC_OUTS_B4_10", - "GTPE2_LOGIC_OUTS_B14_10", - "GTPE2_IMUX35_6", - "GTPE2_CHANNEL_TXOUTCLK_1", - "GTPE2_CHANNEL_RXDATA17", - "GTPE2_BYP7_7", - "GTPE2_CTRL0_8", - "GTPE2_CHANNEL_PLL1CLK", - "GTPE2_IMUX25_9", - "GTPE2_CHANNEL_CLKRSVD0", - "GTPE2_IMUX3_0", - "GTPE2_IMUX18_4", - "GTPE2_IMUX20_5", - "GTPE2_BYP1_5", - "GTPE2_IMUX42_4", - "GTPE2_LOGIC_OUTS_B22_10", - "GTPE2_IMUX7_0", - "GTPE2_CHANNEL_RXBYTEREALIGN", - "GTPE2_CHANNEL_RXDATA26", - "GTPE2_CHANNEL_RXPHMONITOR0", - "GTPE2_CHANNEL_PMASCANIN2", - "GTPE2_CHANNEL_RXPHALIGNEN", - "GTPE2_IMUX45_9", - "GTPE2_CTRL1_6", - "GTPE2_CHANNEL_RXOSINTNTRLEN", - "GTPE2_CHANNEL_SCANOUT5", - "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "GTPE2_CHANNEL_RXCOMSASDET", - "GTPE2_IMUX31_0", - "GTPE2_CHANNEL_TXDLYBYPASS", - "GTPE2_IMUX22_5", - "GTPE2_CHANNEL_RXDATA6", - "GTPE2_CHANNEL_TXPISOPD", - "GTPE2_CHANNEL_PCSRSVDIN15", - "GTPE2_IMUX3_8", - "GTPE2_CHANNEL_RXNOTINTABLE0", - "GTPE2_CHANNEL_RXADAPTSELTEST4", - "GTPE2_CHANNEL_TXMAINCURSOR0", - "GTPE2_CHANNEL_PCSRSVDOUT5", - "GTPE2_CHANNEL_TXDATA6", - "GTPE2_CHANNEL_RXOSINTSTARTED", - "GTPE2_IMUX10_10", - "GTPE2_LOGIC_OUTS_B2_8", - "GTPE2_LOGIC_OUTS_B4_8", - "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "GTPE2_BYP6_0", - "GTPE2_CHANNEL_RXOUTCLK_0", - "GTPE2_CHANNEL_RXOSINTCFG2", - "GTPE2_CHANNEL_GTRSVD4", - "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "GTPE2_LOGIC_OUTS_B14_2", - "GTPE2_CHANNEL_TSTIN14", - "GTPE2_CHANNEL_DMONITOROUT0", - "GTPE2_LOGIC_OUTS_B4_4", - "GTPE2_CHANNEL_DRPDO0", - "GTPE2_IMUX38_5", - "GTPE2_LOGIC_OUTS_B0_5", - "GTPE2_CHANNEL_RXRATE0", - "GTPE2_CHANNEL_RXCHANREALIGN", - "GTPE2_CHANNEL_RXCHBONDMASTER", - "GTPE2_FAN6_10", - "GTPE2_IMUX22_2", - "GTPE2_IMUX29_9", - "GTPE2_CHANNEL_RXDATA16", - "GTPE2_CHANNEL_RXADAPTSELTEST9", - "GTPE2_IMUX23_7", - "GTPE2_IMUX43_7", - "GTPE2_IMUX11_8", - "GTPE2_CHANNEL_TXDATA7", - "GTPE2_LOGIC_OUTS_B9_2", - "GTPE2_CHANNEL_TXPD1", - "GTPE2_FAN1_7", - "GTPE2_CHANNEL_RXDATA25", - "GTPE2_IMUX24_0", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "GTPE2_CHANNEL_SCANOUT2", - "GTPE2_IMUX10_8", - "GTPE2_CHANNEL_DRPDI0", - "GTPE2_CHANNEL_RXDATA5", - "GTPE2_CHANNEL_PCSRSVDIN4", - "GTPE2_BYP3_5", - "GTPE2_CHANNEL_DRPDO2", - "GTPE2_CHANNEL_DMONFIFORESET", - "GTPE2_IMUX39_3", - "GTPE2_LOGIC_OUTS_B10_7", - "GTPE2_BYP3_3", - "GTPE2_CHANNEL_TX8B10BBYPASS2", - "GTPE2_IMUX3_3", - "GTPE2_CHANNEL_RXDATA30", - "GTPE2_CHANNEL_TXOUTCLKSEL2", - "GTPE2_IMUX24_8", - "GTPE2_IMUX38_0", - "GTPE2_IMUX20_3", - "GTPE2_CHANNEL_TXRATEMODE", - "GTPE2_IMUX12_2", - "GTPE2_LOGIC_OUTS_B21_6", - "GTPE2_IMUX39_7", - "GTPE2_LOGIC_OUTS_B15_8", - "GTPE2_CHANNEL_RXPMARESETDONE", - "GTPE2_CHANNEL_RXPMARESET", - "GTPE2_IMUX39_8", - "GTPE2_IMUX6_6", - "GTPE2_CHANNEL_TXDATA22", - "GTPE2_CHANNEL_TXCHARISK1", - "GTPE2_FAN6_6", - "GTPE2_IMUX5_0", - "GTPE2_LOGIC_OUTS_B12_6", - "GTPE2_BYP4_0", - "GTPE2_CHANNEL_TSTIN12", - "GTPE2_IMUX11_6", - "GTPE2_LOGIC_OUTS_B3_1", - "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "GTPE2_IMUX45_8", - "GTPE2_FAN5_5", - "GTPE2_CHANNEL_TXOUTCLK_3", - "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "GTPE2_CHANNEL_PCSRSVDOUT4", - "GTPE2_IMUX9_2", - "GTPE2_IMUX35_10", - "GTPE2_CHANNEL_RX8B10BEN", - "GTPE2_CHANNEL_RXCDRFREQRESET", - "GTPE2_CHANNEL_RXGEARBOXSLIP", - "GTPE2_IMUX35_0", - "GTPE2_IMUX18_5", - "GTPE2_CHANNEL_RXCHARISCOMMA2", - "GTPE2_CHANNEL_SCANCLK", - "GTPE2_CHANNEL_TXDATA5", - "GTPE2_LOGIC_OUTS_B21_8", - "GTPE2_IMUX21_6", - "GTPE2_LOGIC_OUTS_B11_7", - "GTPE2_CHANNEL_RXPHOVRDEN", - "GTPE2_BYP4_4", - "GTPE2_IMUX5_5", - "GTPE2_LOGIC_OUTS_B3_5", - "GTPE2_LOGIC_OUTS_B17_9", - "GTPE2_FAN6_4", - "GTPE2_IMUX37_8", - "GTPE2_LOGIC_OUTS_B12_0", - "GTPE2_BYP2_6", - "GTPE2_IMUX7_2", - "GTPE2_CHANNEL_TSTPD4", - "GTPE2_CHANNEL_RXHEADER2", - "GTPE2_FAN7_7", - "GTPE2_IMUX26_0", - "GTPE2_CHANNEL_GTRSVD11", - "GTPE2_LOGIC_OUTS_B20_9", - "GTPE2_CHANNEL_TSTIN1", - "GTPE2_IMUX15_0", - "GTPE2_FAN0_6", - "GTPE2_CHANNEL_RXDATA14", - "GTPE2_LOGIC_OUTS_B22_2", - "GTPE2_IMUX5_3", - "GTPE2_IMUX41_3", - "GTPE2_LOGIC_OUTS_B9_8", - "GTPE2_CHANNEL_LOOPBACK0", - "GTPE2_LOGIC_OUTS_B18_7", - "GTPE2_LOGIC_OUTS_B16_1", - "GTPE2_IMUX38_8", - "GTPE2_IMUX15_5", - "GTPE2_CHANNEL_RXHEADER1", - "GTPE2_CHANNEL_TXPRBSSEL0", - "GTPE2_CHANNEL_RXLPMHFHOLD", - "GTPE2_LOGIC_OUTS_B8_9", - "GTPE2_BYP6_10", - "GTPE2_CLK1_7", - "GTPE2_CTRL1_1", - "GTPE2_CHANNEL_DRPADDR5", - "GTPE2_LOGIC_OUTS_B0_8", - "GTPE2_CHANNEL_TXDATA16", - "GTPE2_CHANNEL_GTRSVD6", - "GTPE2_CHANNEL_RXCHANBONDSEQ", - "GTPE2_IMUX18_7", - "GTPE2_LOGIC_OUTS_B5_2", - "GTPE2_BYP5_9", - "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "GTPE2_IMUX17_2", - "GTPE2_CHANNEL_TXSEQUENCE6", - "GTPE2_FAN6_8", - "GTPE2_IMUX34_9", - "GTPE2_CHANNEL_TXDLYEN", - "GTPE2_IMUX40_4", - "GTPE2_IMUX9_0", - "GTPE2_CHANNEL_TXDATA27", - "GTPE2_IMUX29_5", - "GTPE2_IMUX28_7", - "GTPE2_CHANNEL_PMASCANIN4", - "GTPE2_CHANNEL_PCSRSVDOUT6", - "GTPE2_IMUX43_8", - "GTPE2_IMUX40_7", - "GTPE2_LOGIC_OUTS_B23_10", - "GTPE2_IMUX45_5", - "GTPE2_IMUX4_1", - "GTPE2_IMUX10_1", - "GTPE2_IMUX37_0", - "GTPE2_BYP3_2", - "GTPE2_IMUX28_2", - "GTPE2_CHANNEL_TXDATA26", - "GTPE2_CHANNEL_TXDATA31", - "GTPE2_FAN0_10", - "GTPE2_LOGIC_OUTS_B7_9", - "GTPE2_BYP3_1", - "GTPE2_IMUX23_8", - "GTPE2_CHANNEL_RXCHARISK1", - "GTPE2_BYP5_6", - "GTPE2_CHANNEL_PHYSTATUS", - "GTPE2_CHANNEL_TXINHIBIT", - "GTPE2_CHANNEL_RXUSERRDY", - "GTPE2_IMUX24_6", - "GTPE2_CHANNEL_RXDATA23", - "GTPE2_IMUX13_10", - "GTPE2_IMUX34_3", - "GTPE2_CHANNEL_PMARSVDOUT1", - "GTPE2_IMUX5_4", - "GTPE2_CLK0_6", - "GTPE2_BYP5_8", - "GTPE2_IMUX18_10", - "GTPE2_FAN7_8", - "GTPE2_FAN5_2", - "GTPE2_CTRL0_6", - "GTPE2_CHANNEL_DRPDI10", - "GTPE2_FAN5_0", - "GTPE2_CHANNEL_RXCHARISK0", - "GTPE2_IMUX22_3", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "GTPE2_IMUX5_1", - "GTPE2_CHANNEL_DMONITOROUT1", - "GTPE2_IMUX33_5", - "GTPE2_CHANNEL_DRPDI9", - "GTPE2_CHANNEL_TXMARGIN1", - "GTPE2_IMUX10_3", - "GTPE2_CHANNEL_RXNOTINTABLE1", - "GTPE2_BYP6_9", - "GTPE2_IMUX5_2", - "GTPE2_IMUX38_4", - "GTPE2_IMUX46_4", - "GTPE2_CHANNEL_RXSYNCALLIN", - "GTPE2_CHANNEL_RXSTATUS1", - "GTPE2_IMUX12_7", - "GTPE2_FAN3_8", - "GTPE2_IMUX22_10", - "GTPE2_IMUX20_9", - "GTPE2_LOGIC_OUTS_B11_1", - "GTPE2_CHANNEL_PMASCANIN6", - "GTPE2_CHANNEL_TXSYNCIN", - "GTPE2_CHANNEL_TXSEQUENCE5", - "GTPE2_CHANNEL_TXDLYSRESETDONE", - "GTPE2_LOGIC_OUTS_B0_2", - "GTPE2_IMUX15_4", - "GTPE2_LOGIC_OUTS_B16_6", - "GTPE2_IMUX38_2", - "GTPE2_IMUX16_7", - "GTPE2_IMUX27_9", - "GTPE2_LOGIC_OUTS_B18_8", - "GTPE2_LOGIC_OUTS_B8_0", - "GTPE2_LOGIC_OUTS_B21_2", - "GTPE2_IMUX41_1", - "GTPE2_CHANNEL_TXUSRCLK", - "GTPE2_IMUX35_7", - "GTPE2_CHANNEL_TXMAINCURSOR5", - "GTPE2_CHANNEL_RXDLYSRESET", - "GTPE2_CHANNEL_DRPDI13", - "GTPE2_LOGIC_OUTS_B6_9", - "GTPE2_CHANNEL_RXOUTCLKSEL2", - "GTPE2_LOGIC_OUTS_B3_8", - "GTPE2_LOGIC_OUTS_B6_4", - "GTPE2_CHANNEL_DMONITOROUT11", - "GTPE2_LOGIC_OUTS_B2_7", - "GTPE2_IMUX6_3", - "GTPE2_IMUX20_0", - "GTPE2_IMUX12_10", - "GTPE2_CTRL0_10", - "GTPE2_CHANNEL_RXCOMMADET", - "GTPE2_CHANNEL_TXPOLARITY", - "GTPE2_CHANNEL_TXPRBSSEL2", - "GTPE2_LOGIC_OUTS_B5_4", - "GTPE2_IMUX37_1", - "GTPE2_CHANNEL_RXADAPTSELTEST13", - "GTPE2_IMUX27_7", - "GTPE2_IMUX44_9", - "GTPE2_IMUX36_10", - "GTPE2_FAN5_6", - "GTPE2_IMUX18_9", - "GTPE2_CLK1_3", - "GTPE2_IMUX26_10", - "GTPE2_IMUX32_6", - "GTPE2_IMUX36_6", - "GTPE2_IMUX14_5", - "GTPE2_LOGIC_OUTS_B18_1", - "GTPE2_IMUX46_9", - "GTPE2_CHANNEL_TXDLYSRESET", - "GTPE2_CHANNEL_RXCHARISK2", - "GTPE2_IMUX28_4", - "GTPE2_CHANNEL_PMARSVDIN2", - "GTPE2_CLK1_8", - "GTPE2_IMUX39_0", - "GTPE2_LOGIC_OUTS_B2_2", - "GTPE2_BYP6_4", - "GTPE2_IMUX30_2", - "GTPE2_LOGIC_OUTS_B10_4", - "GTPE2_CHANNEL_DRPADDR8", - "GTPE2_CHANNEL_DMONITOROUT4", - "GTPE2_IMUX19_6", - "GTPE2_FAN4_10", - "GTPE2_IMUX34_6", - "GTPE2_BYP4_3", - "GTPE2_CHANNEL_TX8B10BEN", - "GTPE2_LOGIC_OUTS_B11_6", - "GTPE2_IMUX28_6", - "GTPE2_CHANNEL_RXOSINTDONE", - "GTPE2_CHANNEL_TXOUTCLKSEL1", - "GTPE2_LOGIC_OUTS_B9_4", - "GTPE2_IMUX8_3", - "GTPE2_CHANNEL_DRPDI4", - "GTPE2_CHANNEL_TXSYSCLKSEL0", - "GTPE2_LOGIC_OUTS_B10_1", - "GTPE2_LOGIC_OUTS_B12_1", - "GTPE2_IMUX17_7", - "GTPE2_IMUX9_1", - "GTPE2_CHANNEL_PMASCANIN5", - "GTPE2_FAN0_3", - "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "GTPE2_BYP2_1", - "GTPE2_CHANNEL_RXOSINTSTROBE", - "GTPE2_IMUX40_8", - "GTPE2_IMUX3_10", - "GTPE2_CHANNEL_LOOPBACK2", - "GTPE2_IMUX35_1", - "GTPE2_LOGIC_OUTS_B19_6", - "GTPE2_CHANNEL_TXDATA25", - "GTPE2_IMUX40_2", - "GTPE2_IMUX8_2", - "GTPE2_CHANNEL_TXSYSCLKSEL1", - "GTPE2_IMUX36_2", - "GTPE2_CHANNEL_RXDLYOVRDEN", - "GTPE2_FAN3_0", - "GTPE2_CHANNEL_RXDATA20", - "GTPE2_IMUX22_7", - "GTPE2_IMUX35_8", - "GTPE2_CHANNEL_DRPDO3", - "GTPE2_CHANNEL_RXOUTCLKSEL0", - "GTPE2_LOGIC_OUTS_B11_3", - "GTPE2_CHANNEL_TXDIFFCTRL2", - "GTPE2_IMUX7_8", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "GTPE2_CHANNEL_RXDEBUGPULSE", - "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "GTPE2_CTRL0_1", - "GTPE2_CHANNEL_TXCHARDISPVAL3", - "GTPE2_LOGIC_OUTS_B2_6", - "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "GTPE2_BYP7_5", - "GTPE2_IMUX0_3", - "GTPE2_CHANNEL_TSTIN3", - "GTPE2_CHANNEL_DRPDI15", - "GTPE2_LOGIC_OUTS_B20_1", - "GTPE2_BYP2_7", - "GTPE2_CHANNEL_EYESCANDATAERROR", - "GTPE2_LOGIC_OUTS_B19_0", - "GTPE2_LOGIC_OUTS_B17_0", - "GTPE2_CHANNEL_RXOSINTCFG0", - "GTPE2_IMUX7_1", - "GTPE2_CHANNEL_RXELECIDLEMODE0", - "GTPE2_CHANNEL_DRPDO4", - "GTPE2_LOGIC_OUTS_B1_9", - "GTPE2_CHANNEL_RXSYNCDONE", - "GTPE2_CHANNEL_DRPADDR1", - "GTPE2_BYP6_8", - "GTPE2_IMUX0_1", - "GTPE2_CHANNEL_RXDATA28", - "GTPE2_IMUX6_8", - "GTPE2_IMUX10_4", - "GTPE2_IMUX46_2", - "GTPE2_IMUX35_2", - "GTPE2_IMUX33_6", - "GTPE2_IMUX7_10", - "GTPE2_CHANNEL_RXCDRRESETRSV", - "GTPE2_BYP7_1", - "GTPE2_CHANNEL_SCANENB", - "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "GTPE2_CHANNEL_TSTIN16", - "GTPE2_CHANNEL_TSTIN4", - "GTPE2_CHANNEL_TXDATA3", - "GTPE2_BYP5_7", - "GTPE2_LOGIC_OUTS_B20_10", - "GTPE2_IMUX33_8", - "GTPE2_CHANNEL_TSTPD2", - "GTPE2_IMUX27_8", - "GTPE2_CHANNEL_RXPHMONITOR4", - "GTPE2_CHANNEL_DRPDI8", - "GTPE2_LOGIC_OUTS_B19_10", - "GTPE2_CLK1_9", - "GTPE2_CHANNEL_TXRESETDONE", - "GTPE2_IMUX3_1", - "GTPE2_IMUX25_3", - "GTPE2_IMUX47_1", - "GTPE2_BYP5_0", - "GTPE2_CHANNEL_SCANIN2", - "GTPE2_IMUX33_1", - "GTPE2_LOGIC_OUTS_B14_3", - "GTPE2_CHANNEL_TXDATA20", - "GTPE2_IMUX26_7", - "GTPE2_LOGIC_OUTS_B4_1", - "GTPE2_BYP6_2", - "GTPE2_IMUX16_9", - "GTPE2_CHANNEL_RXSYSCLKSEL1", - "GTPE2_IMUX41_10", - "GTPE2_CHANNEL_RXCDRHOLD", - "GTPE2_BYP0_3", - "GTPE2_FAN2_9", - "GTPE2_CHANNEL_TXOUTCLKPCS", - "GTPE2_LOGIC_OUTS_B17_5", - "GTPE2_CHANNEL_PLLREFCLK0", - "GTPE2_LOGIC_OUTS_B16_9", - "GTPE2_IMUX37_6", - "GTPE2_CHANNEL_RXPRBSERR", - "GTPE2_LOGIC_OUTS_B11_4", - "GTPE2_IMUX14_0", - "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "GTPE2_CHANNEL_TXDATA29", - "GTPE2_LOGIC_OUTS_B14_7", - "GTPE2_LOGIC_OUTS_B1_1", - "GTPE2_IMUX17_9", - "GTPE2_IMUX21_3", - "GTPE2_LOGIC_OUTS_B14_4", - "GTPE2_CHANNEL_GTRSVD15", - "GTPE2_IMUX24_10", - "GTPE2_LOGIC_OUTS_B0_9", - "GTPE2_CHANNEL_PMASCANOUT6", - "GTPE2_IMUX4_6", - "GTPE2_CHANNEL_RXCHBONDO0", - "GTPE2_LOGIC_OUTS_B11_2", - "GTPE2_CHANNEL_RXADAPTSELTEST10", - "GTPE2_CHANNEL_RXOUTCLK_2", - "GTPE2_BYP4_8", - "GTPE2_CHANNEL_RXDATA4", - "GTPE2_CHANNEL_PCSRSVDIN0", - "GTPE2_CHANNEL_RXADAPTSELTEST2", - "GTPE2_LOGIC_OUTS_B14_1", - "GTPE2_CHANNEL_TXPRBSSEL1", - "GTPE2_LOGIC_OUTS_B15_3", - "GTPE2_LOGIC_OUTS_B13_0", - "GTPE2_CHANNEL_TXPRECURSORINV", - "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "GTPE2_CHANNEL_TXMAINCURSOR1", - "GTPE2_CHANNEL_RXOSINTOVRDEN", - "GTPE2_CHANNEL_TXDATA23", - "GTPE2_CHANNEL_TXRUNDISP0", - "GTPE2_LOGIC_OUTS_B4_2", - "GTPE2_BYP0_4", - "GTPE2_BYP3_6", - "GTPE2_LOGIC_OUTS_B9_5", - "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "GTPE2_CTRL1_10", - "GTPE2_CHANNEL_RXOSINTID02", - "GTPE2_IMUX16_2", - "GTPE2_CHANNEL_RXRATEDONE", - "GTPE2_BYP0_0", - "GTPE2_CHANNEL_TXCOMWAKE", - "GTPE2_IMUX43_3", - "GTPE2_LOGIC_OUTS_B13_7", - "GTPE2_CHANNEL_TXPOSTCURSOR4", - "GTPE2_IMUX22_4", - "GTPE2_IMUX21_1", - "GTPE2_FAN1_9", - "GTPE2_IMUX29_7", - "GTPE2_LOGIC_OUTS_B8_6", - "GTPE2_BYP7_8", - "GTPE2_IMUX23_5", - "GTPE2_CHANNEL_DRPDO10", - "GTPE2_CHANNEL_DRPDI6", - "GTPE2_IMUX32_1", - "GTPE2_IMUX22_8", - "GTPE2_FAN7_0", - "GTPE2_CHANNEL_RXLPMRESET", - "GTPE2_IMUX13_2", - "GTPE2_CHANNEL_PCSRSVDIN10", - "GTPE2_IMUX46_1", - "GTPE2_CHANNEL_TSTIN18", - "GTPE2_CHANNEL_TXPHDLYRESET", - "GTPE2_FAN6_3", - "GTPE2_CHANNEL_DMONITOROUT3", - "GTPE2_IMUX41_0", - "GTPE2_IMUX13_6", - "GTPE2_IMUX11_1", - "GTPE2_CHANNEL_PCSRSVDOUT9", - "GTPE2_CHANNEL_DRPEN", - "GTPE2_IMUX38_10", - "GTPE2_CHANNEL_TSTPDOVRDB", - "GTPE2_BYP2_8", - "GTPE2_CTRL1_0", - "GTPE2_IMUX2_5", - "GTPE2_CHANNEL_RXDLYEN", - "GTPE2_LOGIC_OUTS_B6_1", - "GTPE2_FAN7_10", - "GTPE2_IMUX17_0", - "GTPE2_CHANNEL_TSTIN19", - "GTPE2_IMUX29_8", - "GTPE2_IMUX11_5", - "GTPE2_LOGIC_OUTS_B22_5", - "GTPE2_CHANNEL_RXDATA3", - "GTPE2_CHANNEL_RXOSINTCFG1", - "GTPE2_IMUX24_5", - "GTPE2_CHANNEL_GTRSVD10", - "GTPE2_LOGIC_OUTS_B20_5", - "GTPE2_LOGIC_OUTS_B20_3", - "GTPE2_CHANNEL_TXSYNCDONE", - "GTPE2_BYP0_6", - "GTPE2_LOGIC_OUTS_B1_0", - "GTPE2_LOGIC_OUTS_B1_4", - "GTPE2_IMUX42_9", - "GTPE2_BYP6_5", - "GTPE2_IMUX47_5", - "GTPE2_CHANNEL_LOOPBACK1", - "GTPE2_IMUX13_9", - "GTPE2_CHANNEL_TXPHALIGNEN", - "GTPE2_IMUX12_4", - "GTPE2_CHANNEL_RXADAPTSELTEST11", - "GTPE2_IMUX44_6", - "GTPE2_CHANNEL_TXELECIDLE", - "GTPE2_CTRL0_0", - "GTPE2_LOGIC_OUTS_B3_7", - "GTPE2_IMUX35_4", - "GTPE2_CHANNEL_RXCHBONDI0", - "GTPE2_CHANNEL_TXCHARDISPMODE1", - "GTPE2_LOGIC_OUTS_B7_10", - "GTPE2_CHANNEL_RXOSINTEN", - "GTPE2_LOGIC_OUTS_B21_3", - "GTPE2_CHANNEL_TXDATA15", - "GTPE2_BYP0_7", - "GTPE2_IMUX2_6", - "GTPE2_BYP3_10", - "GTPE2_FAN1_1", - "GTPE2_CHANNEL_TSTIN6", - "GTPE2_FAN1_4", - "GTPE2_IMUX14_2", - "GTPE2_CHANNEL_PMASCANIN3", - "GTPE2_CHANNEL_TXDATA18", - "GTPE2_IMUX0_4", - "GTPE2_CHANNEL_TSTIN17", - "GTPE2_LOGIC_OUTS_B3_4", - "GTPE2_LOGIC_OUTS_B1_8", - "GTPE2_BYP1_8", - "GTPE2_CHANNEL_RXSTATUS2", - "GTPE2_BYP5_2", - "GTPE2_CHANNEL_PCSRSVDIN11", - "GTPE2_IMUX38_9", - "GTPE2_BYP7_6", - "GTPE2_CHANNEL_PMASCANCLK1", - "GTPE2_CHANNEL_RXBUFSTATUS0", - "GTPE2_IMUX11_0", - "GTPE2_FAN4_9", - "GTPE2_LOGIC_OUTS_B12_8", - "GTPE2_BYP1_3", - "GTPE2_BYP0_10", - "GTPE2_CHANNEL_RXOSCALRESET", - "GTPE2_IMUX6_0", - "GTPE2_CHANNEL_TSTIN11", - "GTPE2_CLK0_3", - "GTPE2_CHANNEL_CLKRSVD1", - "GTPE2_FAN3_10", - "GTPE2_IMUX19_0", - "GTPE2_CHANNEL_RXHEADER0", - "GTPE2_CHANNEL_TXPRBSFORCEERR", - "GTPE2_CHANNEL_PCSRSVDIN13", - "GTPE2_IMUX46_7", - "GTPE2_CHANNEL_PCSRSVDOUT14", - "GTPE2_LOGIC_OUTS_B15_10", - "GTPE2_CHANNEL_TSTPD3", - "GTPE2_LOGIC_OUTS_B12_2", - "GTPE2_IMUX45_1", - "GTPE2_IMUX0_0", - "GTPE2_IMUX39_10", - "GTPE2_CHANNEL_DMONITOROUT10", - "GTPE2_CHANNEL_RXCDRLOCK", - "GTPE2_IMUX4_2", - "GTPE2_CHANNEL_TXMAINCURSOR2", - "GTPE2_CHANNEL_PCSRSVDIN9", - "GTPE2_IMUX10_5", - "GTPE2_CHANNEL_PMASCANCLK0", - "GTPE2_IMUX18_8", - "GTPE2_CHANNEL_TXSYNCMODE", - "GTPE2_CHANNEL_TXN_PAD", - "GTPE2_CHANNEL_TXPMARESET", - "GTPE2_IMUX43_10", - "GTPE2_BYP5_10", - "GTPE2_CHANNEL_DRPADDR0", - "GTPE2_CHANNEL_PCSRSVDOUT1", - "GTPE2_CHANNEL_PMARSVDIN4", - "GTPE2_IMUX14_1", - "GTPE2_CHANNEL_SCANIN5", - "GTPE2_LOGIC_OUTS_B0_1", - "GTPE2_CHANNEL_PCSRSVDOUT12", - "GTPE2_CHANNEL_DRPDI7", - "GTPE2_IMUX26_6", - "GTPE2_IMUX17_6", - "GTPE2_LOGIC_OUTS_B1_7", - "GTPE2_CHANNEL_RXDATA7", - "GTPE2_CHANNEL_TXCHARDISPMODE3", - "GTPE2_IMUX26_8", - "GTPE2_IMUX0_9", - "GTPE2_FAN3_6", - "GTPE2_IMUX46_0", - "GTPE2_CHANNEL_TSTIN7", - "GTPE2_LOGIC_OUTS_B20_7", - "GTPE2_LOGIC_OUTS_B17_2", - "GTPE2_CHANNEL_TXCHARDISPVAL1", - "GTPE2_CHANNEL_TXSEQUENCE4", - "GTPE2_CHANNEL_TXPOSTCURSOR2", - "GTPE2_CHANNEL_DRPDI2", - "GTPE2_FAN2_10", - "GTPE2_CHANNEL_RXBUFSTATUS2", - "GTPE2_IMUX1_7", - "GTPE2_IMUX10_7", - "GTPE2_CHANNEL_SCANOUT4", - "GTPE2_LOGIC_OUTS_B18_0", - "GTPE2_CHANNEL_DRPDO9", - "GTPE2_FAN6_9", - "GTPE2_IMUX4_7", - "GTPE2_CHANNEL_TSTPD1", - "GTPE2_IMUX39_6", - "GTPE2_CHANNEL_TXPRECURSOR2", - "GTPE2_IMUX43_0", - "GTPE2_FAN1_6", - "GTPE2_BYP1_1", - "GTPE2_FAN5_3", - "GTPE2_CHANNEL_DMONITOROUT2", - "GTPE2_LOGIC_OUTS_B19_4", - "GTPE2_CHANNEL_PMASCANMODEB", - "GTPE2_IMUX37_9", - "GTPE2_LOGIC_OUTS_B22_3", - "GTPE2_FAN1_3", - "GTPE2_IMUX5_9", - "GTPE2_CHANNEL_RXELECIDLE", - "GTPE2_IMUX34_8", - "GTPE2_FAN2_4", - "GTPE2_IMUX24_2", - "GTPE2_LOGIC_OUTS_B22_4", - "GTPE2_IMUX34_4", - "GTPE2_LOGIC_OUTS_B0_10", - "GTPE2_IMUX29_6", - "GTPE2_IMUX45_10", - "GTPE2_CLK1_6", - "GTPE2_CHANNEL_PMASCANENB", - "GTPE2_CHANNEL_TXDATA8", - "GTPE2_CLK0_7", - "GTPE2_IMUX30_1", - "GTPE2_LOGIC_OUTS_B11_8", - "GTPE2_CHANNEL_RXHEADERVALID", - "GTPE2_FAN5_1", - "GTPE2_CHANNEL_PCSRSVDOUT3", - "GTPE2_IMUX2_9", - "GTPE2_CHANNEL_TXPIPPMPD", - "GTPE2_IMUX44_5", - "GTPE2_IMUX22_0", - "GTPE2_CHANNEL_TXPIPPMEN", - "GTPE2_FAN5_10", - "GTPE2_BYP1_0", - "GTPE2_IMUX11_7", - "GTPE2_CHANNEL_TXDATA10", - "GTPE2_IMUX34_2", - "GTPE2_LOGIC_OUTS_B4_0", - "GTPE2_CHANNEL_GTRSVD5", - "GTPE2_LOGIC_OUTS_B8_7", - "GTPE2_IMUX44_4", - "GTPE2_IMUX41_5", - "GTPE2_CHANNEL_TXDLYOVRDEN", - "GTPE2_IMUX37_4", - "GTPE2_BYP6_6", - "GTPE2_IMUX44_10", - "GTPE2_CHANNEL_DRPADDR2", - "GTPE2_CLK0_5", - "GTPE2_CHANNEL_DRPDI11", - "GTPE2_LOGIC_OUTS_B7_1", - "GTPE2_IMUX8_0", - "GTPE2_IMUX25_4", - "GTPE2_LOGIC_OUTS_B7_8", - "GTPE2_CHANNEL_TXBUFSTATUS0", - "GTPE2_IMUX30_3", - "GTPE2_IMUX27_4", - "GTPE2_LOGIC_OUTS_B8_8", - "GTPE2_CHANNEL_DRPADDR6", - "GTPE2_IMUX0_7", - "GTPE2_IMUX42_8", - "GTPE2_IMUX33_4", - "GTPE2_BYP0_9", - "GTPE2_LOGIC_OUTS_B6_0", - "GTPE2_LOGIC_OUTS_B22_8", - "GTPE2_CHANNEL_RXOSINTID01", - "GTPE2_IMUX40_5", - "GTPE2_CHANNEL_DRPDO6", - "GTPE2_CHANNEL_RXSYSCLKSEL0", - "GTPE2_CLK1_2", - "GTPE2_FAN5_9", - "GTPE2_IMUX6_10", - "GTPE2_LOGIC_OUTS_B12_4", - "GTPE2_IMUX13_7", - "GTPE2_IMUX25_7", - "GTPE2_IMUX7_3", - "GTPE2_BYP7_9", - "GTPE2_CHANNEL_RXCHBONDO2", - "GTPE2_LOGIC_OUTS_B17_1", - "GTPE2_LOGIC_OUTS_B15_2", - "GTPE2_CHANNEL_PCSRSVDIN5", - "GTPE2_LOGIC_OUTS_B5_0", - "GTPE2_LOGIC_OUTS_B3_10", - "GTPE2_CHANNEL_DRPDI12", - "GTPE2_IMUX23_9", - "GTPE2_LOGIC_OUTS_B9_0", - "GTPE2_IMUX7_4", - "GTPE2_CHANNEL_TSTIN0", - "GTPE2_FAN5_8", - "GTPE2_LOGIC_OUTS_B13_1", - "GTPE2_IMUX32_0", - "GTPE2_CHANNEL_RXPRBSSEL2", - "GTPE2_IMUX45_2", - "GTPE2_CHANNEL_DRPDI1", - "GTPE2_CHANNEL_TXDATA19", - "GTPE2_FAN6_7", - "GTPE2_CHANNEL_RXDATA11", - "GTPE2_CHANNEL_RXCOMMADETEN", - "GTPE2_CHANNEL_TXN", - "GTPE2_CHANNEL_TXRATEDONE", - "GTPE2_IMUX39_5", - "GTPE2_FAN0_2", - "GTPE2_IMUX18_0", - "GTPE2_IMUX16_10", - "GTPE2_CHANNEL_PMASCANOUT0", - "GTPE2_CHANNEL_PMASCANIN1", - "GTPE2_LOGIC_OUTS_B13_3", - "GTPE2_IMUX36_0", - "GTPE2_BYP7_4", - "GTPE2_CHANNEL_RXPOLARITY", - "GTPE2_LOGIC_OUTS_B7_0", - "GTPE2_CHANNEL_DRPDO8", - "GTPE2_LOGIC_OUTS_B0_0", - "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "GTPE2_IMUX4_3", - "GTPE2_CHANNEL_SCANOUT1", - "GTPE2_CHANNEL_PCSRSVDOUT15", - "GTPE2_CHANNEL_TXOUTCLKSEL0", - "GTPE2_CHANNEL_DRPCLK", - "GTPE2_LOGIC_OUTS_B20_4", - "GTPE2_LOGIC_OUTS_B15_6", - "GTPE2_LOGIC_OUTS_B13_4", - "GTPE2_BYP2_0", - "GTPE2_IMUX9_7", - "GTPE2_IMUX11_9", - "GTPE2_IMUX2_10", - "GTPE2_IMUX9_4", - "GTPE2_IMUX3_6", - "GTPE2_CHANNEL_RXDATA19", - "GTPE2_LOGIC_OUTS_B23_0", - "GTPE2_CHANNEL_SCANIN1", - "GTPE2_IMUX8_1", - "GTPE2_CHANNEL_TXPIPPMSEL", - "GTPE2_IMUX13_0", - "GTPE2_IMUX30_10", - "GTPE2_BYP4_7", - "GTPE2_LOGIC_OUTS_B23_7", - "GTPE2_CHANNEL_EYESCANRESET", - "GTPE2_IMUX30_9", - "GTPE2_IMUX37_7", - "GTPE2_IMUX25_8", - "GTPE2_FAN4_0", - "GTPE2_IMUX38_7", - "GTPE2_FAN5_4", - "GTPE2_FAN1_2", - "GTPE2_IMUX22_6", - "GTPE2_CHANNEL_TX8B10BBYPASS3", - "GTPE2_IMUX2_7", - "GTPE2_LOGIC_OUTS_B5_5", - "GTPE2_IMUX26_1", - "GTPE2_IMUX42_5", - "GTPE2_CHANNEL_TXMARGIN0", - "GTPE2_CHANNEL_RXDATA12", - "GTPE2_IMUX9_5", - "GTPE2_CHANNEL_TX8B10BBYPASS1", - "GTPE2_LOGIC_OUTS_B11_5", - "GTPE2_CLK0_1", - "GTPE2_IMUX31_8", - "GTPE2_LOGIC_OUTS_B18_9", - "GTPE2_FAN0_4", - "GTPE2_IMUX9_8", - "GTPE2_CHANNEL_DRPDI3", - "GTPE2_LOGIC_OUTS_B8_5", - "GTPE2_LOGIC_OUTS_B16_10", - "GTPE2_BYP1_6", - "GTPE2_IMUX47_0", - "GTPE2_CHANNEL_RXNOTINTABLE3", - "GTPE2_IMUX42_10", - "GTPE2_IMUX8_4", - "GTPE2_CHANNEL_RXDATA10", - "GTPE2_CHANNEL_RXRATE1", - "GTPE2_IMUX47_10", - "GTPE2_CHANNEL_TXSEQUENCE3", - "GTPE2_IMUX38_3", - "GTPE2_IMUX43_4", - "GTPE2_CHANNEL_TXRUNDISP1", - "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "GTPE2_BYP3_4", - "GTPE2_FAN4_5", - "GTPE2_BYP0_5", - "GTPE2_IMUX32_2", - "GTPE2_FAN4_7", - "GTPE2_IMUX3_4", - "GTPE2_CHANNEL_TXDATA9", - "GTPE2_FAN2_3", - "GTPE2_CHANNEL_PLLREFCLK1", - "GTPE2_LOGIC_OUTS_B0_6", - "GTPE2_LOGIC_OUTS_B23_1", - "GTPE2_IMUX45_4", - "GTPE2_CHANNEL_RXADAPTSELTEST0", - "GTPE2_LOGIC_OUTS_B15_1", - "GTPE2_BYP1_10", - "GTPE2_LOGIC_OUTS_B0_7", - "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", - "GTPE2_IMUX27_10", - "GTPE2_IMUX32_7", - "GTPE2_BYP3_9", - "GTPE2_CHANNEL_PMASCANCLK2", - "GTPE2_LOGIC_OUTS_B21_0", - "GTPE2_IMUX20_10", - "GTPE2_CHANNEL_RXPHMONITOR1", - "GTPE2_IMUX15_6", - "GTPE2_IMUX1_8", - "GTPE2_IMUX33_9", - "GTPE2_IMUX12_8", - "GTPE2_IMUX28_0", - "GTPE2_CHANNEL_RXDATA31", - "GTPE2_IMUX31_4", - "GTPE2_CTRL1_8", - "GTPE2_LOGIC_OUTS_B14_0", - "GTPE2_CHANNEL_RXDLYTESTENB", - "GTPE2_CHANNEL_TXP", - "GTPE2_IMUX33_10", - "GTPE2_IMUX9_10", - "GTPE2_IMUX34_1", - "GTPE2_LOGIC_OUTS_B18_5", - "GTPE2_FAN3_4", - "GTPE2_BYP5_5", - "GTPE2_CHANNEL_RXP", - "GTPE2_LOGIC_OUTS_B6_7", - "GTPE2_FAN3_1", - "GTPE2_IMUX8_10", - "GTPE2_IMUX26_9", - "GTPE2_FAN7_5", - "GTPE2_IMUX1_10", - "GTPE2_IMUX1_3", - "GTPE2_CHANNEL_RXDATA13", - "GTPE2_CHANNEL_TXSWING", - "GTPE2_CHANNEL_PLLCLK0", - "GTPE2_CHANNEL_PCSRSVDOUT11", - "GTPE2_FAN2_7", - "GTPE2_IMUX21_2", - "GTPE2_CHANNEL_RXCLKCORCNT1", - "GTPE2_CHANNEL_TXDIFFCTRL1", - "GTPE2_IMUX21_4", - "GTPE2_LOGIC_OUTS_B22_9", - "GTPE2_IMUX39_2", - "GTPE2_IMUX19_9", - "GTPE2_IMUX40_0", - "GTPE2_CHANNEL_TSTPD0", - "GTPE2_CHANNEL_TXCHARISK2", - "GTPE2_CHANNEL_RXSTATUS0", - "GTPE2_IMUX19_5", - "GTPE2_IMUX11_2", - "GTPE2_CHANNEL_PMASCANOUT2", - "GTPE2_LOGIC_OUTS_B11_10", - "GTPE2_IMUX38_1", - "GTPE2_CHANNEL_RXCOMWAKEDET", - "GTPE2_CHANNEL_TSTIN13", - "GTPE2_IMUX1_6", - "GTPE2_CHANNEL_RXCDROVRDEN", - "GTPE2_LOGIC_OUTS_B8_2", - "GTPE2_LOGIC_OUTS_B20_8", - "GTPE2_CHANNEL_DMONITOROUT5", - "GTPE2_IMUX35_9", - "GTPE2_IMUX27_0", - "GTPE2_LOGIC_OUTS_B7_4", - "GTPE2_IMUX30_0", - "GTPE2_IMUX23_3", - "GTPE2_CHANNEL_RXN", - "GTPE2_IMUX42_6", - "GTPE2_IMUX14_3", - "GTPE2_IMUX16_3", - "GTPE2_LOGIC_OUTS_B5_10", - "GTPE2_BYP4_10", - "GTPE2_CHANNEL_TXPOSTCURSORINV", - "GTPE2_CHANNEL_DRPDO12", - "GTPE2_IMUX35_5", - "GTPE2_IMUX21_10", - "GTPE2_BYP4_6", - "GTPE2_CHANNEL_RXADAPTSELTEST5", - "GTPE2_IMUX23_4", - "GTPE2_LOGIC_OUTS_B16_7", - "GTPE2_BYP2_4", - "GTPE2_IMUX27_3", - "GTPE2_CLK1_0", - "GTPE2_IMUX13_3", - "GTPE2_IMUX43_2", - "GTPE2_FAN2_0", - "GTPE2_CTRL0_4", - "GTPE2_IMUX21_0", - "GTPE2_LOGIC_OUTS_B12_5", - "GTPE2_CHANNEL_GTRSVD0", - "GTPE2_IMUX47_3", - "GTPE2_IMUX4_5", - "GTPE2_CHANNEL_TXPCSRESET", - "GTPE2_IMUX47_2", - "GTPE2_CLK0_2", - "GTPE2_CHANNEL_RXBUFSTATUS1", - "GTPE2_CTRL0_3", - "GTPE2_IMUX47_7", - "GTPE2_IMUX39_4", - "GTPE2_IMUX42_7", - "GTPE2_IMUX17_3", - "GTPE2_LOGIC_OUTS_B7_7", - "GTPE2_IMUX10_9", - "GTPE2_CHANNEL_TXSTARTSEQ", - "GTPE2_CHANNEL_TXSEQUENCE2", - "GTPE2_CHANNEL_GTTXRESET", - "GTPE2_IMUX21_8", - "GTPE2_CHANNEL_TXRUNDISP3", - "GTPE2_FAN4_6", - "GTPE2_CHANNEL_TXDATA28", - "GTPE2_CHANNEL_TSTIN9", - "GTPE2_CHANNEL_RXUSRCLK2", - "GTPE2_CHANNEL_RXCHARISCOMMA3", - "GTPE2_IMUX8_9", - "GTPE2_CHANNEL_RXPD1", - "GTPE2_LOGIC_OUTS_B7_3", - "GTPE2_CHANNEL_TXCOMINIT", - "GTPE2_LOGIC_OUTS_B15_9", - "GTPE2_FAN0_8", - "GTPE2_BYP3_0", - "GTPE2_IMUX6_9", - "GTPE2_CHANNEL_DRPDO13", - "GTPE2_CTRL1_9", - "GTPE2_LOGIC_OUTS_B22_7", - "GTPE2_IMUX40_3", - "GTPE2_LOGIC_OUTS_B20_2", - "GTPE2_FAN4_3", - "GTPE2_IMUX1_0", - "GTPE2_LOGIC_OUTS_B19_8", - "GTPE2_LOGIC_OUTS_B3_3", - "GTPE2_IMUX34_7", - "GTPE2_IMUX0_10", - "GTPE2_CHANNEL_TXRUNDISP2", - "GTPE2_IMUX19_7", - "GTPE2_LOGIC_OUTS_B19_7", - "GTPE2_CHANNEL_RXBUFRESET", - "GTPE2_CHANNEL_RXSYNCOUT", - "GTPE2_IMUX12_9", - "GTPE2_IMUX15_9", - "GTPE2_LOGIC_OUTS_B6_6", - "GTPE2_CTRL1_4", - "GTPE2_CTRL0_9", - "GTPE2_IMUX33_0", - "GTPE2_IMUX11_3", - "GTPE2_FAN0_1", - "GTPE2_IMUX32_5", - "GTPE2_IMUX42_3", - "GTPE2_LOGIC_OUTS_B14_8", - "GTPE2_CHANNEL_TXCHARDISPMODE2", - "GTPE2_IMUX7_6", - "GTPE2_FAN4_1", - "GTPE2_CHANNEL_RXN_PAD", - "GTPE2_CHANNEL_DRPADDR3", - "GTPE2_IMUX23_6", - "GTPE2_BYP7_3", - "GTPE2_BYP5_1", - "GTPE2_CHANNEL_TXPHDLYPD", - "GTPE2_IMUX41_9", - "GTPE2_BYP4_2", - "GTPE2_IMUX22_1", - "GTPE2_LOGIC_OUTS_B3_2", - "GTPE2_CHANNEL_DMONITOROUT8", - "GTPE2_CHANNEL_DRPRDY", - "GTPE2_IMUX45_7", - "GTPE2_BYP7_0", - "GTPE2_IMUX3_2", - "GTPE2_IMUX18_3", - "GTPE2_IMUX4_9", - "GTPE2_IMUX19_10", - "GTPE2_IMUX3_9", - "GTPE2_CHANNEL_RXDATA22", - "GTPE2_FAN4_2", - "GTPE2_IMUX17_5", - "GTPE2_CHANNEL_GTRSVD7", - "GTPE2_IMUX25_2", - "GTPE2_LOGIC_OUTS_B4_3", - "GTPE2_LOGIC_OUTS_B5_3", - "GTPE2_CHANNEL_CFGRESET", - "GTPE2_IMUX27_6", - "GTPE2_IMUX24_9", - "GTPE2_IMUX23_10", - "GTPE2_CHANNEL_TXPRECURSOR3", - "GTPE2_CHANNEL_PMASCANCLK3", - "GTPE2_BYP1_7", - "GTPE2_FAN1_5", - "GTPE2_LOGIC_OUTS_B0_3", - "GTPE2_LOGIC_OUTS_B18_10", - "GTPE2_CHANNEL_TXSYNCOUT", - "GTPE2_IMUX28_5", - "GTPE2_IMUX16_0", - "GTPE2_BYP2_10", - "GTPE2_IMUX36_8", - "GTPE2_CLK1_1", - "GTPE2_CHANNEL_TXDATA24", - "GTPE2_IMUX32_10", - "GTPE2_LOGIC_OUTS_B12_10", - "GTPE2_LOGIC_OUTS_B23_9", - "GTPE2_IMUX24_7", - "GTPE2_LOGIC_OUTS_B21_9", - "GTPE2_IMUX37_3", - "GTPE2_CHANNEL_RXCHBONDI3", - "GTPE2_LOGIC_OUTS_B6_8", - "GTPE2_LOGIC_OUTS_B16_3", - "GTPE2_FAN5_7", - "GTPE2_BYP0_2", - "GTPE2_CHANNEL_RXCHBONDEN", - "GTPE2_IMUX9_9", - "GTPE2_CHANNEL_TSTIN5", - "GTPE2_CHANNEL_PCSRSVDIN1", - "GTPE2_CHANNEL_RXSLIDE", - "GTPE2_IMUX25_0", - "GTPE2_CHANNEL_RXDATA2", - "GTPE2_IMUX5_10", - "GTPE2_CHANNEL_PLL1REFCLK", - "GTPE2_IMUX6_7", - "GTPE2_LOGIC_OUTS_B18_4", - "GTPE2_CHANNEL_RXRESETDONE", - "GTPE2_CHANNEL_GTRSVD2", - "GTPE2_CHANNEL_TXPOSTCURSOR1", - "GTPE2_CHANNEL_RXDFEXYDEN", - "GTPE2_IMUX44_1", - "GTPE2_LOGIC_OUTS_B19_1", - "GTPE2_IMUX28_3", - "GTPE2_IMUX9_3", - "GTPE2_BYP2_3", - "GTPE2_LOGIC_OUTS_B1_10", - "GTPE2_CHANNEL_GTRSVD14", - "GTPE2_CHANNEL_TXPRECURSOR1", - "GTPE2_CHANNEL_RXCLKCORCNT0", - "GTPE2_CTRL0_5", - "GTPE2_CHANNEL_PCSRSVDOUT2", - "GTPE2_FAN7_9", - "GTPE2_LOGIC_OUTS_B12_3", - "GTPE2_IMUX20_8", - "GTPE2_CHANNEL_GTRSVD12", - "GTPE2_IMUX35_3", - "GTPE2_CTRL1_5", - "GTPE2_CHANNEL_EYESCANTRIGGER", - "GTPE2_CHANNEL_TXDATA30", - "GTPE2_IMUX26_3", - "GTPE2_FAN0_0", - "GTPE2_CHANNEL_RXCDRRESET" - ], - "sites": [ - { - "prefix": "GTPE2_CHANNEL", - "y_coord": 0, - "type": "GTPE2_CHANNEL", - "site_pins": { - "RXCHARISCOMMA3": "GTPE2_CHANNEL_RXCHARISCOMMA3", - "RXSTATUS0": "GTPE2_CHANNEL_RXSTATUS0", - "DRPDO13": "GTPE2_CHANNEL_DRPDO13", - "TSTPD0": "GTPE2_CHANNEL_TSTPD0", - "RXBUFRESET": "GTPE2_CHANNEL_RXBUFRESET", - "RXVALID": "GTPE2_CHANNEL_RXVALID", - "SCANIN1": "GTPE2_CHANNEL_SCANIN1", - "RXCHBONDLEVEL2": "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "TXDATA25": "GTPE2_CHANNEL_TXDATA25", - "GTPRXN": "GTPE2_CHANNEL_RXN", - "PCSRSVDOUT6": "GTPE2_CHANNEL_PCSRSVDOUT6", - "TXDATA31": "GTPE2_CHANNEL_TXDATA31", - "CFGRESET": "GTPE2_CHANNEL_CFGRESET", - "GTPTXP": "GTPE2_CHANNEL_TXP", - "TXPIPPMEN": "GTPE2_CHANNEL_TXPIPPMEN", - "TXDATA14": "GTPE2_CHANNEL_TXDATA14", - "TXRATE0": "GTPE2_CHANNEL_TXRATE0", - "DMONITOROUT6": "GTPE2_CHANNEL_DMONITOROUT6", - "PMASCANOUT5": "GTPE2_CHANNEL_PMASCANOUT5", - "RXDATA28": "GTPE2_CHANNEL_RXDATA28", - "TXOUTCLK": "GTPE2_CHANNEL_GTTXOUTCLK_3", - "RXCHANBONDSEQ": "GTPE2_CHANNEL_RXCHANBONDSEQ", - "DRPDI4": "GTPE2_CHANNEL_DRPDI4", - "TXDATA15": "GTPE2_CHANNEL_TXDATA15", - "RXDATA26": "GTPE2_CHANNEL_RXDATA26", - "TXHEADER1": "GTPE2_CHANNEL_TXHEADER1", - "RXCHBONDLEVEL1": "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "RXNOTINTABLE1": "GTPE2_CHANNEL_RXNOTINTABLE1", - "RXPD0": "GTPE2_CHANNEL_RXPD0", - "DMONITOROUT14": "GTPE2_CHANNEL_DMONITOROUT14", - "TXBUFSTATUS1": "GTPE2_CHANNEL_TXBUFSTATUS1", - "TXCOMSAS": "GTPE2_CHANNEL_TXCOMSAS", - "RXCDRRESETRSV": "GTPE2_CHANNEL_RXCDRRESETRSV", - "RXSTATUS2": "GTPE2_CHANNEL_RXSTATUS2", - "RXOSINTCFG2": "GTPE2_CHANNEL_RXOSINTCFG2", - "PCSRSVDIN11": "GTPE2_CHANNEL_PCSRSVDIN11", - "PHYSTATUS": "GTPE2_CHANNEL_PHYSTATUS", - "RXGEARBOXSLIP": "GTPE2_CHANNEL_RXGEARBOXSLIP", - "DMONITOROUT3": "GTPE2_CHANNEL_DMONITOROUT3", - "TXMAINCURSOR1": "GTPE2_CHANNEL_TXMAINCURSOR1", - "GTRSVD11": "GTPE2_CHANNEL_GTRSVD11", - "DMONITOROUT7": "GTPE2_CHANNEL_DMONITOROUT7", - "TXSYNCDONE": "GTPE2_CHANNEL_TXSYNCDONE", - "PCSRSVDIN6": "GTPE2_CHANNEL_PCSRSVDIN6", - "RXBYTEISALIGNED": "GTPE2_CHANNEL_RXBYTEISALIGNED", - "PCSRSVDIN4": "GTPE2_CHANNEL_PCSRSVDIN4", - "RXOSINTCFG3": "GTPE2_CHANNEL_RXOSINTCFG3", - "TXCHARDISPVAL3": "GTPE2_CHANNEL_TXCHARDISPVAL3", - "TXCHARDISPMODE3": "GTPE2_CHANNEL_TXCHARDISPMODE3", - "RXDATA29": "GTPE2_CHANNEL_RXDATA29", - "TXOUTCLKPCS": "GTPE2_CHANNEL_TXOUTCLKPCS", - "RXCLKCORCNT1": "GTPE2_CHANNEL_RXCLKCORCNT1", - "RXADAPTSELTEST2": "GTPE2_CHANNEL_RXADAPTSELTEST2", - "TXINHIBIT": "GTPE2_CHANNEL_TXINHIBIT", - "TXDATA13": "GTPE2_CHANNEL_TXDATA13", - "TXPISOPD": "GTPE2_CHANNEL_TXPISOPD", - "RXPMARESET": "GTPE2_CHANNEL_RXPMARESET", - "TSTIN14": "GTPE2_CHANNEL_TSTIN14", - "PCSRSVDIN13": "GTPE2_CHANNEL_PCSRSVDIN13", - "PMASCANCLK3": "GTPE2_CHANNEL_PMASCANCLK3", - "TXDATA8": "GTPE2_CHANNEL_TXDATA8", - "PCSRSVDIN1": "GTPE2_CHANNEL_PCSRSVDIN1", - "DRPDI12": "GTPE2_CHANNEL_DRPDI12", - "RXOSINTID02": "GTPE2_CHANNEL_RXOSINTID02", - "PMARSVDOUT1": "GTPE2_CHANNEL_PMARSVDOUT1", - "RXCDRHOLD": "GTPE2_CHANNEL_RXCDRHOLD", - "TXDATA10": "GTPE2_CHANNEL_TXDATA10", - "DRPDI6": "GTPE2_CHANNEL_DRPDI6", - "TSTIN2": "GTPE2_CHANNEL_TSTIN2", - "DRPWE": "GTPE2_CHANNEL_DRPWE", - "RXOUTCLKSEL2": "GTPE2_CHANNEL_RXOUTCLKSEL2", - "DRPADDR5": "GTPE2_CHANNEL_DRPADDR5", - "TSTIN15": "GTPE2_CHANNEL_TSTIN15", - "RXPHSLIPMONITOR0": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "RXPHDLYRESET": "GTPE2_CHANNEL_RXPHDLYRESET", - "RXPHSLIPMONITOR1": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "TXPRBSFORCEERR": "GTPE2_CHANNEL_TXPRBSFORCEERR", - "TXHEADER2": "GTPE2_CHANNEL_TXHEADER2", - "PCSRSVDOUT0": "GTPE2_CHANNEL_PCSRSVDOUT0", - "TXPD0": "GTPE2_CHANNEL_TXPD0", - "RXDATA4": "GTPE2_CHANNEL_RXDATA4", - "RXHEADER1": "GTPE2_CHANNEL_RXHEADER1", - "RXOSINTID00": "GTPE2_CHANNEL_RXOSINTID00", - "RXSTARTOFSEQ1": "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "RXOSOVRDEN": "GTPE2_CHANNEL_RXOSOVRDEN", - "RXADAPTSELTEST11": "GTPE2_CHANNEL_RXADAPTSELTEST11", - "PCSRSVDOUT1": "GTPE2_CHANNEL_PCSRSVDOUT1", - "TXPIPPMPD": "GTPE2_CHANNEL_TXPIPPMPD", - "TXDLYOVRDEN": "GTPE2_CHANNEL_TXDLYOVRDEN", - "RXDATA21": "GTPE2_CHANNEL_RXDATA21", - "RXCHBONDO1": "GTPE2_CHANNEL_RXCHBONDO1", - "TXOUTCLKSEL0": "GTPE2_CHANNEL_TXOUTCLKSEL0", - "TXDEEMPH": "GTPE2_CHANNEL_TXDEEMPH", - "TXDATA5": "GTPE2_CHANNEL_TXDATA5", - "GTRSVD1": "GTPE2_CHANNEL_GTRSVD1", - "TSTPD3": "GTPE2_CHANNEL_TSTPD3", - "TXMAINCURSOR6": "GTPE2_CHANNEL_TXMAINCURSOR6", - "TSTIN5": "GTPE2_CHANNEL_TSTIN5", - "TXPRECURSOR2": "GTPE2_CHANNEL_TXPRECURSOR2", - "TXRATEMODE": "GTPE2_CHANNEL_TXRATEMODE", - "RXLPMLFOVRDEN": "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "RXOUTCLKSEL0": "GTPE2_CHANNEL_RXOUTCLKSEL0", - "TXUSRCLK2": "GTPE2_CHANNEL_TXUSRCLK2", - "RXPHDLYPD": "GTPE2_CHANNEL_RXPHDLYPD", - "RXOSINTID03": "GTPE2_CHANNEL_RXOSINTID03", - "RXDATA3": "GTPE2_CHANNEL_RXDATA3", - "DRPDO6": "GTPE2_CHANNEL_DRPDO6", - "TXPOSTCURSORINV": "GTPE2_CHANNEL_TXPOSTCURSORINV", - "TXMAINCURSOR2": "GTPE2_CHANNEL_TXMAINCURSOR2", - "TSTPD1": "GTPE2_CHANNEL_TSTPD1", - "RXPHMONITOR0": "GTPE2_CHANNEL_RXPHMONITOR0", - "TSTIN18": "GTPE2_CHANNEL_TSTIN18", - "DRPDO4": "GTPE2_CHANNEL_DRPDO4", - "RXOSCALRESET": "GTPE2_CHANNEL_RXOSCALRESET", - "RXCHARISCOMMA1": "GTPE2_CHANNEL_RXCHARISCOMMA1", - "RXADAPTSELTEST4": "GTPE2_CHANNEL_RXADAPTSELTEST4", - "RXMCOMMAALIGNEN": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "TXPHDLYPD": "GTPE2_CHANNEL_TXPHDLYPD", - "TXPOSTCURSOR2": "GTPE2_CHANNEL_TXPOSTCURSOR2", - "PMASCANCLK0": "GTPE2_CHANNEL_PMASCANCLK0", - "PCSRSVDOUT15": "GTPE2_CHANNEL_PCSRSVDOUT15", - "SCANIN3": "GTPE2_CHANNEL_SCANIN3", - "TXELECIDLE": "GTPE2_CHANNEL_TXELECIDLE", - "RXDATA27": "GTPE2_CHANNEL_RXDATA27", - "TXRATE2": "GTPE2_CHANNEL_TXRATE2", - "EYESCANRESET": "GTPE2_CHANNEL_EYESCANRESET", - "DRPDI13": "GTPE2_CHANNEL_DRPDI13", - "PMASCANCLK1": "GTPE2_CHANNEL_PMASCANCLK1", - "RXCHBONDLEVEL0": "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "RXPHMONITOR3": "GTPE2_CHANNEL_RXPHMONITOR3", - "TXSTARTSEQ": "GTPE2_CHANNEL_TXSTARTSEQ", - "RXRATE1": "GTPE2_CHANNEL_RXRATE1", - "DRPDO0": "GTPE2_CHANNEL_DRPDO0", - "TXBUFDIFFCTRL0": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "RXDATA18": "GTPE2_CHANNEL_RXDATA18", - "DRPDO1": "GTPE2_CHANNEL_DRPDO1", - "RXADAPTSELTEST10": "GTPE2_CHANNEL_RXADAPTSELTEST10", - "RXDLYBYPASS": "GTPE2_CHANNEL_RXDLYBYPASS", - "TXDIFFCTRL0": "GTPE2_CHANNEL_TXDIFFCTRL0", - "RXPRBSCNTRESET": "GTPE2_CHANNEL_RXPRBSCNTRESET", - "RXCLKCORCNT0": "GTPE2_CHANNEL_RXCLKCORCNT0", - "TSTCLK1": "GTPE2_CHANNEL_TSTCLK1", - "PLL1CLK": "GTPE2_CHANNEL_PLL1CLK", - "DMONITORCLK": "GTPE2_CHANNEL_DMONITORCLK", - "PLL0REFCLK": "GTPE2_CHANNEL_PLL0REFCLK", - "SCANMODEB": "GTPE2_CHANNEL_SCANMODEB", - "TSTIN12": "GTPE2_CHANNEL_TSTIN12", - "TSTIN7": "GTPE2_CHANNEL_TSTIN7", - "TXDATA19": "GTPE2_CHANNEL_TXDATA19", - "RXPCSRESET": "GTPE2_CHANNEL_RXPCSRESET", - "TXPRBSSEL2": "GTPE2_CHANNEL_TXPRBSSEL2", - "RXPHOVRDEN": "GTPE2_CHANNEL_RXPHOVRDEN", - "TSTIN11": "GTPE2_CHANNEL_TSTIN11", - "RXDATA6": "GTPE2_CHANNEL_RXDATA6", - "SETERRSTATUS": "GTPE2_CHANNEL_SETERRSTATUS", - "RXOSINTID01": "GTPE2_CHANNEL_RXOSINTID01", - "TXHEADER0": "GTPE2_CHANNEL_TXHEADER0", - "DRPDI8": "GTPE2_CHANNEL_DRPDI8", - "TXDIFFCTRL3": "GTPE2_CHANNEL_TXDIFFCTRL3", - "TXDATA18": "GTPE2_CHANNEL_TXDATA18", - "DMONITOROUT5": "GTPE2_CHANNEL_DMONITOROUT5", - "RXDATA1": "GTPE2_CHANNEL_RXDATA1", - "RX8B10BEN": "GTPE2_CHANNEL_RX8B10BEN", - "TXCHARDISPVAL1": "GTPE2_CHANNEL_TXCHARDISPVAL1", - "TXRATE1": "GTPE2_CHANNEL_TXRATE1", - "TXDATA21": "GTPE2_CHANNEL_TXDATA21", - "PMASCANOUT2": "GTPE2_CHANNEL_PMASCANOUT2", - "PCSRSVDIN10": "GTPE2_CHANNEL_PCSRSVDIN10", - "GTRSVD2": "GTPE2_CHANNEL_GTRSVD2", - "RXADAPTSELTEST5": "GTPE2_CHANNEL_RXADAPTSELTEST5", - "LOOPBACK0": "GTPE2_CHANNEL_LOOPBACK0", - "DRPADDR4": "GTPE2_CHANNEL_DRPADDR4", - "TXCHARDISPVAL0": "GTPE2_CHANNEL_TXCHARDISPVAL0", - "PMASCANIN4": "GTPE2_CHANNEL_PMASCANIN4", - "DRPADDR8": "GTPE2_CHANNEL_DRPADDR8", - "RXSYSCLKSEL1": "GTPE2_CHANNEL_RXSYSCLKSEL1", - "RXADAPTSELTEST8": "GTPE2_CHANNEL_RXADAPTSELTEST8", - "TXSYNCOUT": "GTPE2_CHANNEL_TXSYNCOUT", - "RXCHBONDMASTER": "GTPE2_CHANNEL_RXCHBONDMASTER", - "TXPRECURSORINV": "GTPE2_CHANNEL_TXPRECURSORINV", - "PCSRSVDOUT2": "GTPE2_CHANNEL_PCSRSVDOUT2", - "TXPOLARITY": "GTPE2_CHANNEL_TXPOLARITY", - "RXADAPTSELTEST9": "GTPE2_CHANNEL_RXADAPTSELTEST9", - "DMONITOROUT0": "GTPE2_CHANNEL_DMONITOROUT0", - "TXUSERRDY": "GTPE2_CHANNEL_TXUSERRDY", - "DMONITOROUT4": "GTPE2_CHANNEL_DMONITOROUT4", - "TXDLYEN": "GTPE2_CHANNEL_TXDLYEN", - "TSTIN10": "GTPE2_CHANNEL_TSTIN10", - "RXPHSLIPMONITOR4": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "RXCHBONDI3": "GTPE2_CHANNEL_RXCHBONDI3", - "TXPIPPMSTEPSIZE2": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "RXDDIEN": "GTPE2_CHANNEL_RXDDIEN", - "RXPRBSSEL1": "GTPE2_CHANNEL_RXPRBSSEL1", - "PCSRSVDIN5": "GTPE2_CHANNEL_PCSRSVDIN5", - "TXPMARESETDONE": "GTPE2_CHANNEL_TXPMARESETDONE", - "TXRUNDISP3": "GTPE2_CHANNEL_TXRUNDISP3", - "RXUSRCLK": "GTPE2_CHANNEL_RXUSRCLK", - "TXSEQUENCE4": "GTPE2_CHANNEL_TXSEQUENCE4", - "RXELECIDLEMODE1": "GTPE2_CHANNEL_RXELECIDLEMODE1", - "DRPDO9": "GTPE2_CHANNEL_DRPDO9", - "RXCOMMADETEN": "GTPE2_CHANNEL_RXCOMMADETEN", - "GTRESETSEL": "GTPE2_CHANNEL_GTRESETSEL", - "SCANCLK": "GTPE2_CHANNEL_SCANCLK", - "TXDLYHOLD": "GTPE2_CHANNEL_TXDLYHOLD", - "PMASCANIN0": "GTPE2_CHANNEL_PMASCANIN0", - "TXPRBSSEL1": "GTPE2_CHANNEL_TXPRBSSEL1", - "LOOPBACK2": "GTPE2_CHANNEL_LOOPBACK2", - "RXDATA2": "GTPE2_CHANNEL_RXDATA2", - "PCSRSVDOUT9": "GTPE2_CHANNEL_PCSRSVDOUT9", - "TXDATA7": "GTPE2_CHANNEL_TXDATA7", - "RXOSINTSTROBESTARTED": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "RXADAPTSELTEST13": "GTPE2_CHANNEL_RXADAPTSELTEST13", - "TXOUTCLKFABRIC": "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "TXBUFDIFFCTRL2": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "PCSRSVDOUT4": "GTPE2_CHANNEL_PCSRSVDOUT4", - "TXRUNDISP1": "GTPE2_CHANNEL_TXRUNDISP1", - "RXCHBONDO2": "GTPE2_CHANNEL_RXCHBONDO2", - "TXSEQUENCE5": "GTPE2_CHANNEL_TXSEQUENCE5", - "DRPADDR6": "GTPE2_CHANNEL_DRPADDR6", - "DRPADDR3": "GTPE2_CHANNEL_DRPADDR3", - "RXSTARTOFSEQ0": "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "TXUSRCLK": "GTPE2_CHANNEL_TXUSRCLK", - "TXDATA29": "GTPE2_CHANNEL_TXDATA29", - "RXPHALIGNDONE": "GTPE2_CHANNEL_RXPHALIGNDONE", - "TSTIN4": "GTPE2_CHANNEL_TSTIN4", - "GTRSVD5": "GTPE2_CHANNEL_GTRSVD5", - "PCSRSVDOUT7": "GTPE2_CHANNEL_PCSRSVDOUT7", - "RXADAPTSELTEST3": "GTPE2_CHANNEL_RXADAPTSELTEST3", - "PCSRSVDIN8": "GTPE2_CHANNEL_PCSRSVDIN8", - "TXPD1": "GTPE2_CHANNEL_TXPD1", - "GTRSVD9": "GTPE2_CHANNEL_GTRSVD9", - "RXDATA15": "GTPE2_CHANNEL_RXDATA15", - "RXCHARISK3": "GTPE2_CHANNEL_RXCHARISK3", - "TXPRECURSOR3": "GTPE2_CHANNEL_TXPRECURSOR3", - "RXPHMONITOR1": "GTPE2_CHANNEL_RXPHMONITOR1", - "RXRATE0": "GTPE2_CHANNEL_RXRATE0", - "RXOUTCLK": "GTPE2_CHANNEL_GTRXOUTCLK_3", - "RXOSINTDONE": "GTPE2_CHANNEL_RXOSINTDONE", - "RXDATAVALID1": "GTPE2_CHANNEL_RXDATAVALID1", - "RXNOTINTABLE0": "GTPE2_CHANNEL_RXNOTINTABLE0", - "RESETOVRD": "GTPE2_CHANNEL_RESETOVRD", - "TXDATA26": "GTPE2_CHANNEL_TXDATA26", - "RXDATAVALID0": "GTPE2_CHANNEL_RXDATAVALID0", - "PMASCANOUT3": "GTPE2_CHANNEL_PMASCANOUT3", - "TSTPD4": "GTPE2_CHANNEL_TSTPD4", - "PCSRSVDOUT13": "GTPE2_CHANNEL_PCSRSVDOUT13", - "GTRSVD13": "GTPE2_CHANNEL_GTRSVD13", - "TXDATA20": "GTPE2_CHANNEL_TXDATA20", - "TXDIFFPD": "GTPE2_CHANNEL_TXDIFFPD", - "RXSTATUS1": "GTPE2_CHANNEL_RXSTATUS1", - "RXCHARISK0": "GTPE2_CHANNEL_RXCHARISK0", - "TXBUFSTATUS0": "GTPE2_CHANNEL_TXBUFSTATUS0", - "TSTCLK0": "GTPE2_CHANNEL_TSTCLK0", - "DMONITOROUT8": "GTPE2_CHANNEL_DMONITOROUT8", - "SCANOUT4": "GTPE2_CHANNEL_SCANOUT4", - "RXELECIDLE": "GTPE2_CHANNEL_RXELECIDLE", - "PMASCANCLK2": "GTPE2_CHANNEL_PMASCANCLK2", - "RXDATA16": "GTPE2_CHANNEL_RXDATA16", - "RXCHBONDI1": "GTPE2_CHANNEL_RXCHBONDI1", - "RXCHANREALIGN": "GTPE2_CHANNEL_RXCHANREALIGN", - "RXDISPERR3": "GTPE2_CHANNEL_RXDISPERR3", - "PMASCANENB": "GTPE2_CHANNEL_PMASCANENB", - "TXDATA22": "GTPE2_CHANNEL_TXDATA22", - "PMASCANOUT0": "GTPE2_CHANNEL_PMASCANOUT0", - "TXPIPPMOVRDEN": "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "RXOSINTNTRLEN": "GTPE2_CHANNEL_RXOSINTNTRLEN", - "TXDATA17": "GTPE2_CHANNEL_TXDATA17", - "RXCOMMADET": "GTPE2_CHANNEL_RXCOMMADET", - "TXOUTCLKSEL2": "GTPE2_CHANNEL_TXOUTCLKSEL2", - "TXDLYSRESET": "GTPE2_CHANNEL_TXDLYSRESET", - "TXPHALIGNEN": "GTPE2_CHANNEL_TXPHALIGNEN", - "DRPDO2": "GTPE2_CHANNEL_DRPDO2", - "TXRATEDONE": "GTPE2_CHANNEL_TXRATEDONE", - "TXDATA6": "GTPE2_CHANNEL_TXDATA6", - "DRPDI1": "GTPE2_CHANNEL_DRPDI1", - "RXDISPERR0": "GTPE2_CHANNEL_RXDISPERR0", - "RXDATA13": "GTPE2_CHANNEL_RXDATA13", - "PMASCANIN1": "GTPE2_CHANNEL_PMASCANIN1", - "TXDATA3": "GTPE2_CHANNEL_TXDATA3", - "PCSRSVDIN12": "GTPE2_CHANNEL_PCSRSVDIN12", - "TXRUNDISP2": "GTPE2_CHANNEL_TXRUNDISP2", - "RXDEBUGPULSE": "GTPE2_CHANNEL_RXDEBUGPULSE", - "RXDATA20": "GTPE2_CHANNEL_RXDATA20", - "GTRSVD14": "GTPE2_CHANNEL_GTRSVD14", - "RXCHBONDO0": "GTPE2_CHANNEL_RXCHBONDO0", - "TXDATA23": "GTPE2_CHANNEL_TXDATA23", - "TXPDELECIDLEMODE": "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "TXMAINCURSOR3": "GTPE2_CHANNEL_TXMAINCURSOR3", - "RXLPMOSINTNTRLEN": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "RXDLYSRESET": "GTPE2_CHANNEL_RXDLYSRESET", - "GTRSVD15": "GTPE2_CHANNEL_GTRSVD15", - "RXLPMHFHOLD": "GTPE2_CHANNEL_RXLPMHFHOLD", - "RXDLYEN": "GTPE2_CHANNEL_RXDLYEN", - "TXPIPPMSEL": "GTPE2_CHANNEL_TXPIPPMSEL", - "PCSRSVDIN2": "GTPE2_CHANNEL_PCSRSVDIN2", - "GTRSVD7": "GTPE2_CHANNEL_GTRSVD7", - "DRPDI15": "GTPE2_CHANNEL_DRPDI15", - "RXCHBONDEN": "GTPE2_CHANNEL_RXCHBONDEN", - "TXMAINCURSOR5": "GTPE2_CHANNEL_TXMAINCURSOR5", - "TXGEARBOXREADY": "GTPE2_CHANNEL_TXGEARBOXREADY", - "TXSEQUENCE3": "GTPE2_CHANNEL_TXSEQUENCE3", - "DRPDI5": "GTPE2_CHANNEL_DRPDI5", - "TXCHARDISPMODE0": "GTPE2_CHANNEL_TXCHARDISPMODE0", - "TXDATA27": "GTPE2_CHANNEL_TXDATA27", - "RXSYNCALLIN": "GTPE2_CHANNEL_RXSYNCALLIN", - "EYESCANDATAERROR": "GTPE2_CHANNEL_EYESCANDATAERROR", - "SCANIN2": "GTPE2_CHANNEL_SCANIN2", - "GTRSVD10": "GTPE2_CHANNEL_GTRSVD10", - "RXPRBSSEL2": "GTPE2_CHANNEL_RXPRBSSEL2", - "RXCHBONDI0": "GTPE2_CHANNEL_RXCHBONDI0", - "TXBUFDIFFCTRL1": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "RXADAPTSELTEST6": "GTPE2_CHANNEL_RXADAPTSELTEST6", - "DRPDO8": "GTPE2_CHANNEL_DRPDO8", - "TXDLYBYPASS": "GTPE2_CHANNEL_TXDLYBYPASS", - "TX8B10BBYPASS3": "GTPE2_CHANNEL_TX8B10BBYPASS3", - "DMONFIFORESET": "GTPE2_CHANNEL_DMONFIFORESET", - "RXDATA30": "GTPE2_CHANNEL_RXDATA30", - "TXCHARDISPVAL2": "GTPE2_CHANNEL_TXCHARDISPVAL2", - "TSTIN8": "GTPE2_CHANNEL_TSTIN8", - "RXDATA24": "GTPE2_CHANNEL_RXDATA24", - "GTPTXN": "GTPE2_CHANNEL_TXN", - "RXSYNCMODE": "GTPE2_CHANNEL_RXSYNCMODE", - "TXDATA1": "GTPE2_CHANNEL_TXDATA1", - "TXPRECURSOR0": "GTPE2_CHANNEL_TXPRECURSOR0", - "RXSYNCOUT": "GTPE2_CHANNEL_RXSYNCOUT", - "TSTIN19": "GTPE2_CHANNEL_TSTIN19", - "RXRATEMODE": "GTPE2_CHANNEL_RXRATEMODE", - "DRPDI11": "GTPE2_CHANNEL_DRPDI11", - "RXCDRRESET": "GTPE2_CHANNEL_RXCDRRESET", - "RXOSINTCFG0": "GTPE2_CHANNEL_RXOSINTCFG0", - "PMASCANRSTEN": "GTPE2_CHANNEL_PMASCANRSTEN", - "CLKRSVD1": "GTPE2_CHANNEL_CLKRSVD1", - "TX8B10BBYPASS0": "GTPE2_CHANNEL_TX8B10BBYPASS0", - "PCSRSVDOUT14": "GTPE2_CHANNEL_PCSRSVDOUT14", - "RXNOTINTABLE2": "GTPE2_CHANNEL_RXNOTINTABLE2", - "PCSRSVDIN3": "GTPE2_CHANNEL_PCSRSVDIN3", - "RXOSINTPD": "GTPE2_CHANNEL_RXOSINTPD", - "DMONITOROUT12": "GTPE2_CHANNEL_DMONITOROUT12", - "TXPOSTCURSOR3": "GTPE2_CHANNEL_TXPOSTCURSOR3", - "TXPCSRESET": "GTPE2_CHANNEL_TXPCSRESET", - "TXPHDLYRESET": "GTPE2_CHANNEL_TXPHDLYRESET", - "RXOSINTHOLD": "GTPE2_CHANNEL_RXOSINTHOLD", - "TXPRECURSOR4": "GTPE2_CHANNEL_TXPRECURSOR4", - "RXBYTEREALIGN": "GTPE2_CHANNEL_RXBYTEREALIGN", - "TSTPD2": "GTPE2_CHANNEL_TSTPD2", - "TXSEQUENCE6": "GTPE2_CHANNEL_TXSEQUENCE6", - "TXCHARDISPMODE1": "GTPE2_CHANNEL_TXCHARDISPMODE1", - "RXPRBSSEL0": "GTPE2_CHANNEL_RXPRBSSEL0", - "TSTIN6": "GTPE2_CHANNEL_TSTIN6", - "DRPEN": "GTPE2_CHANNEL_DRPEN", - "TSTIN1": "GTPE2_CHANNEL_TSTIN1", - "DRPDO7": "GTPE2_CHANNEL_DRPDO7", - "PCSRSVDIN7": "GTPE2_CHANNEL_PCSRSVDIN7", - "DRPDI3": "GTPE2_CHANNEL_DRPDI3", - "TSTIN3": "GTPE2_CHANNEL_TSTIN3", - "RXDLYSRESETDONE": "GTPE2_CHANNEL_RXDLYSRESETDONE", - "RXCOMINITDET": "GTPE2_CHANNEL_RXCOMINITDET", - "DRPADDR7": "GTPE2_CHANNEL_DRPADDR7", - "RXLPMLFHOLD": "GTPE2_CHANNEL_RXLPMLFHOLD", - "TXPIPPMSTEPSIZE0": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "TXCHARISK2": "GTPE2_CHANNEL_TXCHARISK2", - "RXDATA9": "GTPE2_CHANNEL_RXDATA9", - "RXBUFSTATUS2": "GTPE2_CHANNEL_RXBUFSTATUS2", - "DRPDI0": "GTPE2_CHANNEL_DRPDI0", - "GTRSVD4": "GTPE2_CHANNEL_GTRSVD4", - "RXSYNCIN": "GTPE2_CHANNEL_RXSYNCIN", - "RXLPMHFOVRDEN": "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "SCANOUT0": "GTPE2_CHANNEL_SCANOUT0", - "TXPHALIGNDONE": "GTPE2_CHANNEL_TXPHALIGNDONE", - "TXDATA30": "GTPE2_CHANNEL_TXDATA30", - "RXCHBONDI2": "GTPE2_CHANNEL_RXCHBONDI2", - "TX8B10BEN": "GTPE2_CHANNEL_TX8B10BEN", - "DRPDO11": "GTPE2_CHANNEL_DRPDO11", - "RXCOMWAKEDET": "GTPE2_CHANNEL_RXCOMWAKEDET", - "RXDLYOVRDEN": "GTPE2_CHANNEL_RXDLYOVRDEN", - "PLL0CLK": "GTPE2_CHANNEL_PLL0CLK", - "RXOUTCLKSEL1": "GTPE2_CHANNEL_RXOUTCLKSEL1", - "PMASCANIN2": "GTPE2_CHANNEL_PMASCANIN2", - "TXDIFFCTRL1": "GTPE2_CHANNEL_TXDIFFCTRL1", - "SCANOUT3": "GTPE2_CHANNEL_SCANOUT3", - "RXOUTCLKPCS": "GTPE2_CHANNEL_RXOUTCLKPCS", - "LOOPBACK1": "GTPE2_CHANNEL_LOOPBACK1", - "DRPDO5": "GTPE2_CHANNEL_DRPDO5", - "SCANIN0": "GTPE2_CHANNEL_SCANIN0", - "DRPDO15": "GTPE2_CHANNEL_DRPDO15", - "DRPADDR1": "GTPE2_CHANNEL_DRPADDR1", - "RXOSINTTESTOVRDEN": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "TXPOSTCURSOR4": "GTPE2_CHANNEL_TXPOSTCURSOR4", - "DMONITOROUT9": "GTPE2_CHANNEL_DMONITOROUT9", - "RXDATA23": "GTPE2_CHANNEL_RXDATA23", - "TXDATA24": "GTPE2_CHANNEL_TXDATA24", - "RXDISPERR1": "GTPE2_CHANNEL_RXDISPERR1", - "RXSYNCDONE": "GTPE2_CHANNEL_RXSYNCDONE", - "TX8B10BBYPASS2": "GTPE2_CHANNEL_TX8B10BBYPASS2", - "TXDATA28": "GTPE2_CHANNEL_TXDATA28", - "PLL1REFCLK": "GTPE2_CHANNEL_PLL1REFCLK", - "TXRESETDONE": "GTPE2_CHANNEL_TXRESETDONE", - "TXDIFFCTRL2": "GTPE2_CHANNEL_TXDIFFCTRL2", - "RXOSINTSTROBEDONE": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "DRPDI10": "GTPE2_CHANNEL_DRPDI10", - "SCANOUT1": "GTPE2_CHANNEL_SCANOUT1", - "DRPDI14": "GTPE2_CHANNEL_DRPDI14", - "GTRSVD8": "GTPE2_CHANNEL_GTRSVD8", - "RXHEADER2": "GTPE2_CHANNEL_RXHEADER2", - "TXSYSCLKSEL1": "GTPE2_CHANNEL_TXSYSCLKSEL1", - "RXADAPTSELTEST1": "GTPE2_CHANNEL_RXADAPTSELTEST1", - "TXPHINITDONE": "GTPE2_CHANNEL_TXPHINITDONE", - "RXPOLARITY": "GTPE2_CHANNEL_RXPOLARITY", - "RXPHSLIPMONITOR3": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "RXOUTCLKFABRIC": "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "RXOSHOLD": "GTPE2_CHANNEL_RXOSHOLD", - "TXRUNDISP0": "GTPE2_CHANNEL_TXRUNDISP0", - "DMONITOROUT13": "GTPE2_CHANNEL_DMONITOROUT13", - "TXCHARDISPMODE2": "GTPE2_CHANNEL_TXCHARDISPMODE2", - "TXDATA16": "GTPE2_CHANNEL_TXDATA16", - "RXDFEXYDEN": "GTPE2_CHANNEL_RXDFEXYDEN", - "RXADAPTSELTEST0": "GTPE2_CHANNEL_RXADAPTSELTEST0", - "RXCHANISALIGNED": "GTPE2_CHANNEL_RXCHANISALIGNED", - "PCSRSVDOUT11": "GTPE2_CHANNEL_PCSRSVDOUT11", - "DRPRDY": "GTPE2_CHANNEL_DRPRDY", - "RXDATA25": "GTPE2_CHANNEL_RXDATA25", - "RXCHARISCOMMA2": "GTPE2_CHANNEL_RXCHARISCOMMA2", - "TXPHINIT": "GTPE2_CHANNEL_TXPHINIT", - "TXOUTCLKSEL1": "GTPE2_CHANNEL_TXOUTCLKSEL1", - "TX8B10BBYPASS1": "GTPE2_CHANNEL_TX8B10BBYPASS1", - "RXPHMONITOR2": "GTPE2_CHANNEL_RXPHMONITOR2", - "RXCHARISK1": "GTPE2_CHANNEL_RXCHARISK1", - "RXPHALIGNEN": "GTPE2_CHANNEL_RXPHALIGNEN", - "RXDATA12": "GTPE2_CHANNEL_RXDATA12", - "TSTIN16": "GTPE2_CHANNEL_TSTIN16", - "PCSRSVDOUT10": "GTPE2_CHANNEL_PCSRSVDOUT10", - "RXCDROVRDEN": "GTPE2_CHANNEL_RXCDROVRDEN", - "TXPIPPMSTEPSIZE4": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", - "RXDLYTESTENB": "GTPE2_CHANNEL_RXDLYTESTENB", - "RXOOBRESET": "GTPE2_CHANNEL_RXOOBRESET", - "PMASCANOUT6": "GTPE2_CHANNEL_PMASCANOUT6", - "TXCHARISK0": "GTPE2_CHANNEL_TXCHARISK0", - "TXDATA12": "GTPE2_CHANNEL_TXDATA12", - "EYESCANMODE": "GTPE2_CHANNEL_EYESCANMODE", - "DRPDI7": "GTPE2_CHANNEL_DRPDI7", - "RXLPMRESET": "GTPE2_CHANNEL_RXLPMRESET", - "RXDATA11": "GTPE2_CHANNEL_RXDATA11", - "TXPRECURSOR1": "GTPE2_CHANNEL_TXPRECURSOR1", - "TXCOMWAKE": "GTPE2_CHANNEL_TXCOMWAKE", - "TXCHARISK3": "GTPE2_CHANNEL_TXCHARISK3", - "TXSWING": "GTPE2_CHANNEL_TXSWING", - "SCANIN5": "GTPE2_CHANNEL_SCANIN5", - "SCANIN4": "GTPE2_CHANNEL_SCANIN4", - "TXPHALIGN": "GTPE2_CHANNEL_TXPHALIGN", - "TXMAINCURSOR4": "GTPE2_CHANNEL_TXMAINCURSOR4", - "DRPDO14": "GTPE2_CHANNEL_DRPDO14", - "DMONITOROUT2": "GTPE2_CHANNEL_DMONITOROUT2", - "RXCDRFREQRESET": "GTPE2_CHANNEL_RXCDRFREQRESET", - "GTRXRESET": "GTPE2_CHANNEL_GTRXRESET", - "TXSYNCMODE": "GTPE2_CHANNEL_TXSYNCMODE", - "TSTPDOVRDB": "GTPE2_CHANNEL_TSTPDOVRDB", - "RXCOMSASDET": "GTPE2_CHANNEL_RXCOMSASDET", - "PCSRSVDOUT3": "GTPE2_CHANNEL_PCSRSVDOUT3", - "RXOSINTSTROBE": "GTPE2_CHANNEL_RXOSINTSTROBE", - "PCSRSVDIN15": "GTPE2_CHANNEL_PCSRSVDIN15", - "PMASCANIN6": "GTPE2_CHANNEL_PMASCANIN6", - "TXCHARISK1": "GTPE2_CHANNEL_TXCHARISK1", - "PMASCANIN3": "GTPE2_CHANNEL_PMASCANIN3", - "TXPOSTCURSOR0": "GTPE2_CHANNEL_TXPOSTCURSOR0", - "EYESCANTRIGGER": "GTPE2_CHANNEL_EYESCANTRIGGER", - "TXSEQUENCE2": "GTPE2_CHANNEL_TXSEQUENCE2", - "GTRSVD0": "GTPE2_CHANNEL_GTRSVD0", - "CLKRSVD0": "GTPE2_CHANNEL_CLKRSVD0", - "RXPMARESETDONE": "GTPE2_CHANNEL_RXPMARESETDONE", - "DRPADDR0": "GTPE2_CHANNEL_DRPADDR0", - "TXPHDLYTSTCLK": "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "RXRATE2": "GTPE2_CHANNEL_RXRATE2", - "DMONITOROUT10": "GTPE2_CHANNEL_DMONITOROUT10", - "TXDATA0": "GTPE2_CHANNEL_TXDATA0", - "RXDATA22": "GTPE2_CHANNEL_RXDATA22", - "RXCHBONDSLAVE": "GTPE2_CHANNEL_RXCHBONDSLAVE", - "TXPMARESET": "GTPE2_CHANNEL_TXPMARESET", - "TXCOMFINISH": "GTPE2_CHANNEL_TXCOMFINISH", - "TXDETECTRX": "GTPE2_CHANNEL_TXDETECTRX", - "PMASCANIN5": "GTPE2_CHANNEL_PMASCANIN5", - "DRPADDR2": "GTPE2_CHANNEL_DRPADDR2", - "TSTIN17": "GTPE2_CHANNEL_TSTIN17", - "RXCHARISK2": "GTPE2_CHANNEL_RXCHARISK2", - "TXDLYUPDOWN": "GTPE2_CHANNEL_TXDLYUPDOWN", - "PMARSVDIN0": "GTPE2_CHANNEL_PMARSVDIN0", - "SIGVALIDCLK": "GTPE2_CHANNEL_SIGVALIDCLK", - "TXMARGIN0": "GTPE2_CHANNEL_TXMARGIN0", - "GTPRXP": "GTPE2_CHANNEL_RXP", - "DMONITOROUT11": "GTPE2_CHANNEL_DMONITOROUT11", - "RXDATA7": "GTPE2_CHANNEL_RXDATA7", - "TXDATA2": "GTPE2_CHANNEL_TXDATA2", - "DMONITOROUT1": "GTPE2_CHANNEL_DMONITOROUT1", - "TXCOMINIT": "GTPE2_CHANNEL_TXCOMINIT", - "RXRESETDONE": "GTPE2_CHANNEL_RXRESETDONE", - "TSTIN9": "GTPE2_CHANNEL_TSTIN9", - "TXSYSCLKSEL0": "GTPE2_CHANNEL_TXSYSCLKSEL0", - "TXDLYTESTENB": "GTPE2_CHANNEL_TXDLYTESTENB", - "PCSRSVDOUT5": "GTPE2_CHANNEL_PCSRSVDOUT5", - "RXCHARISCOMMA0": "GTPE2_CHANNEL_RXCHARISCOMMA0", - "RXOSINTOVRDEN": "GTPE2_CHANNEL_RXOSINTOVRDEN", - "RXCHBONDO3": "GTPE2_CHANNEL_RXCHBONDO3", - "PCSRSVDOUT12": "GTPE2_CHANNEL_PCSRSVDOUT12", - "DRPDI2": "GTPE2_CHANNEL_DRPDI2", - "TXPOSTCURSOR1": "GTPE2_CHANNEL_TXPOSTCURSOR1", - "PCSRSVDOUT8": "GTPE2_CHANNEL_PCSRSVDOUT8", - "GTRSVD6": "GTPE2_CHANNEL_GTRSVD6", - "DRPDO10": "GTPE2_CHANNEL_DRPDO10", - "GTTXRESET": "GTPE2_CHANNEL_GTTXRESET", - "RXDATA10": "GTPE2_CHANNEL_RXDATA10", - "RXRATEDONE": "GTPE2_CHANNEL_RXRATEDONE", - "TXDLYSRESETDONE": "GTPE2_CHANNEL_TXDLYSRESETDONE", - "RXOSINTCFG1": "GTPE2_CHANNEL_RXOSINTCFG1", - "RXDATA14": "GTPE2_CHANNEL_RXDATA14", - "RXPHSLIPMONITOR2": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "TXPIPPMSTEPSIZE1": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "RXPRBSERR": "GTPE2_CHANNEL_RXPRBSERR", - "TXSEQUENCE1": "GTPE2_CHANNEL_TXSEQUENCE1", - "DRPDO12": "GTPE2_CHANNEL_DRPDO12", - "GTRSVD12": "GTPE2_CHANNEL_GTRSVD12", - "RXOSINTEN": "GTPE2_CHANNEL_RXOSINTEN", - "RXDATA19": "GTPE2_CHANNEL_RXDATA19", - "RXDATA17": "GTPE2_CHANNEL_RXDATA17", - "TSTIN13": "GTPE2_CHANNEL_TSTIN13", - "RXHEADER0": "GTPE2_CHANNEL_RXHEADER0", - "PMARSVDIN3": "GTPE2_CHANNEL_PMARSVDIN3", - "RXBUFSTATUS1": "GTPE2_CHANNEL_RXBUFSTATUS1", - "PMASCANMODEB": "GTPE2_CHANNEL_PMASCANMODEB", - "DRPDO3": "GTPE2_CHANNEL_DRPDO3", - "PCSRSVDIN14": "GTPE2_CHANNEL_PCSRSVDIN14", - "TXDATA9": "GTPE2_CHANNEL_TXDATA9", - "PMARSVDOUT0": "GTPE2_CHANNEL_PMARSVDOUT0", - "RXUSERRDY": "GTPE2_CHANNEL_RXUSERRDY", - "RXDATA8": "GTPE2_CHANNEL_RXDATA8", - "RXDISPERR2": "GTPE2_CHANNEL_RXDISPERR2", - "RXSLIDE": "GTPE2_CHANNEL_RXSLIDE", - "TXPRBSSEL0": "GTPE2_CHANNEL_TXPRBSSEL0", - "RXOSINTSTARTED": "GTPE2_CHANNEL_RXOSINTSTARTED", - "TXMARGIN2": "GTPE2_CHANNEL_TXMARGIN2", - "SCANENB": "GTPE2_CHANNEL_SCANENB", - "RXDATA31": "GTPE2_CHANNEL_RXDATA31", - "PMARSVDIN4": "GTPE2_CHANNEL_PMARSVDIN4", - "PMASCANOUT1": "GTPE2_CHANNEL_PMASCANOUT1", - "RXPD1": "GTPE2_CHANNEL_RXPD1", - "TXDATA11": "GTPE2_CHANNEL_TXDATA11", - "PCSRSVDIN9": "GTPE2_CHANNEL_PCSRSVDIN9", - "TXDATA4": "GTPE2_CHANNEL_TXDATA4", - "PMARSVDIN1": "GTPE2_CHANNEL_PMARSVDIN1", - "RXADAPTSELTEST7": "GTPE2_CHANNEL_RXADAPTSELTEST7", - "DRPDI9": "GTPE2_CHANNEL_DRPDI9", - "RXSYSCLKSEL0": "GTPE2_CHANNEL_RXSYSCLKSEL0", - "RXADAPTSELTEST12": "GTPE2_CHANNEL_RXADAPTSELTEST12", - "TXSYNCALLIN": "GTPE2_CHANNEL_TXSYNCALLIN", - "RXBUFSTATUS0": "GTPE2_CHANNEL_RXBUFSTATUS0", - "TXPHOVRDEN": "GTPE2_CHANNEL_TXPHOVRDEN", - "RXPCOMMAALIGNEN": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "RXELECIDLEMODE0": "GTPE2_CHANNEL_RXELECIDLEMODE0", - "TXSYNCIN": "GTPE2_CHANNEL_TXSYNCIN", - "DRPCLK": "GTPE2_CHANNEL_DRPCLK", - "TXMAINCURSOR0": "GTPE2_CHANNEL_TXMAINCURSOR0", - "TXMARGIN1": "GTPE2_CHANNEL_TXMARGIN1", - "PCSRSVDIN0": "GTPE2_CHANNEL_PCSRSVDIN0", - "RXDATA5": "GTPE2_CHANNEL_RXDATA5", - "PMARSVDIN2": "GTPE2_CHANNEL_PMARSVDIN2", - "RXDATA0": "GTPE2_CHANNEL_RXDATA0", - "RXPHMONITOR4": "GTPE2_CHANNEL_RXPHMONITOR4", - "PMASCANOUT4": "GTPE2_CHANNEL_PMASCANOUT4", - "SCANOUT5": "GTPE2_CHANNEL_SCANOUT5", - "TSTIN0": "GTPE2_CHANNEL_TSTIN0", - "RXHEADERVALID": "GTPE2_CHANNEL_RXHEADERVALID", - "SCANOUT2": "GTPE2_CHANNEL_SCANOUT2", - "RXPHALIGN": "GTPE2_CHANNEL_RXPHALIGN", - "RXCDRLOCK": "GTPE2_CHANNEL_RXCDRLOCK", - "RXUSRCLK2": "GTPE2_CHANNEL_RXUSRCLK2", - "RXNOTINTABLE3": "GTPE2_CHANNEL_RXNOTINTABLE3", - "GTRSVD3": "GTPE2_CHANNEL_GTRSVD3", - "TXSEQUENCE0": "GTPE2_CHANNEL_TXSEQUENCE0", - "TXPIPPMSTEPSIZE3": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IPAD", - "y_coord": 27, - "type": "IPAD", - "site_pins": { - "O": "GTPE2_CHANNEL_RXN_PAD" - }, - "x_coord": 1, - "name": "X1Y27" - }, - { - "prefix": "IPAD", - "y_coord": 28, - "type": "IPAD", - "site_pins": { - "O": "GTPE2_CHANNEL_RXP_PAD" - }, - "x_coord": 1, - "name": "X1Y28" - }, - { - "prefix": "OPAD", - "y_coord": 3, - "type": "OPAD", - "site_pins": { - "I": "GTPE2_CHANNEL_TXN_PAD" - }, - "x_coord": 0, - "name": "X0Y3" - }, - { - "prefix": "OPAD", - "y_coord": 4, - "type": "OPAD", - "site_pins": { - "I": "GTPE2_CHANNEL_TXP_PAD" - }, - "x_coord": 0, - "name": "X0Y4" - } - ], "pips": { - "GTP_CHANNEL_3.GTPE2_IMUX9_3->GTPE2_CHANNEL_PCSRSVDIN8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTDONE->GTPE2_LOGIC_OUTS_B3_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO12->GTPE2_LOGIC_OUTS_B7_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX26_9->GTPE2_CHANNEL_GTRSVD14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX6_9->GTPE2_CHANNEL_DRPDI6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX41_10->GTPE2_CHANNEL_TXDATA25": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA25", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL0_9->GTPE2_CHANNEL_RXLPMRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_1->GTPE2_CHANNEL_TXCOMWAKE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMWAKE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX26_10->GTPE2_CHANNEL_GTRSVD15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO14->GTPE2_LOGIC_OUTS_B12_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX21_4->GTPE2_CHANNEL_TXDATA15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISCOMMA0->GTPE2_LOGIC_OUTS_B15_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCOUT->GTPE2_LOGIC_OUTS_B14_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXSYNCOUT", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX9_5->GTPE2_CHANNEL_PCSRSVDIN10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFSTATUS0->GTPE2_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK1_7->GTPE2_CHANNEL_CLKRSVD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CLKRSVD0", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR1->GTPE2_LOGIC_OUTS_B19_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX34_7->GTPE2_CHANNEL_RXADAPTSELTEST4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_2->GTPE2_CHANNEL_RXLPMOSINTNTRLEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA24->GTPE2_LOGIC_OUTS_B6_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA24", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHANISALIGNED->GTPE2_LOGIC_OUTS_B18_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANISALIGNED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA31->GTPE2_LOGIC_OUTS_B5_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA31", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX28_8->GTPE2_CHANNEL_RXPD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXP->GTPE2_CHANNEL_TXP_PAD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXP_PAD", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXP", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_GTRXOUTCLK_3->GTPE2_CHANNEL_RXOUTCLK_3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLK_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_GTRXOUTCLK_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX37_10->GTPE2_CHANNEL_DRPDI12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTARTED->GTPE2_LOGIC_OUTS_B6_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTARTED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX33_5->GTPE2_CHANNEL_DRPDI10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX33_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX45_5->GTPE2_CHANNEL_DRPDI9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX32_7->GTPE2_CHANNEL_TXPRECURSORINV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSORINV", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX38_8->GTPE2_CHANNEL_RXPRBSSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBYTEISALIGNED->GTPE2_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBYTEISALIGNED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATAVALID0->GTPE2_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATAVALID0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX6_5->GTPE2_CHANNEL_TXDIFFCTRL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_8->GTPE2_CHANNEL_RXDDIEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDDIEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA11->GTPE2_LOGIC_OUTS_B0_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX1_0->GTPE2_CHANNEL_RXCHBONDLEVEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXHEADERVALID->GTPE2_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADERVALID", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDLYSRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX33_2->GTPE2_CHANNEL_TXPHALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX33_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX0_2->GTPE2_CHANNEL_TX8B10BEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX21_2->GTPE2_CHANNEL_TXDATA23": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA23", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_2", - "is_pseudo": "0" - }, "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA10->GTPE2_LOGIC_OUTS_B4_8": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_8", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_RXDATA10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX22_6->GTPE2_CHANNEL_TXPIPPMSTEPSIZE4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", "is_directional": "1", - "src_wire": "GTPE2_IMUX22_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX41_1->GTPE2_CHANNEL_RXMCOMMAALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX37_3->GTPE2_CHANNEL_TXPHDLYPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX45_0->GTPE2_CHANNEL_RXDFEXYDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDFEXYDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX27_5->GTPE2_CHANNEL_TXPHINIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHINIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX41_5->GTPE2_CHANNEL_RESETOVRD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RESETOVRD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX28_4->GTPE2_CHANNEL_TXSYSCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX2_7->GTPE2_CHANNEL_RXRATEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX17_1->GTPE2_CHANNEL_TXDATA29": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA29", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT15->GTPE2_LOGIC_OUTS_B15_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX2_3->GTPE2_CHANNEL_DRPADDR8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX17_6->GTPE2_CHANNEL_TXDATA5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO11->GTPE2_LOGIC_OUTS_B1_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDO2->GTPE2_LOGIC_OUTS_B16_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCOUT->GTPE2_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSYNCOUT", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX14_5->GTPE2_CHANNEL_TXDLYEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX20_2->GTPE2_CHANNEL_TXDATA22": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA22", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX46_2->GTPE2_CHANNEL_RXOSCALRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSCALRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX0_10->GTPE2_CHANNEL_RXELECIDLEMODE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX26_6->GTPE2_CHANNEL_GTRSVD11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX46_6->GTPE2_CHANNEL_TXRATE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PLLCLK1->GTPE2_CHANNEL_PLL1CLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL1CLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLCLK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX28_3->GTPE2_CHANNEL_DRPWE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPWE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDO0->GTPE2_LOGIC_OUTS_B16_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT1->GTPE2_LOGIC_OUTS_B0_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA25->GTPE2_LOGIC_OUTS_B2_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA25", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDO1->GTPE2_LOGIC_OUTS_B16_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX39_0->GTPE2_CHANNEL_TXHEADER2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXN->GTPE2_CHANNEL_TXN_PAD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXN_PAD", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX16_0->GTPE2_CHANNEL_TXSEQUENCE5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX32_9->GTPE2_CHANNEL_RXOSINTSTROBE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTSTROBE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT14->GTPE2_LOGIC_OUTS_B5_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX13_6->GTPE2_CHANNEL_DRPDI2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT3->GTPE2_LOGIC_OUTS_B9_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX4_3->GTPE2_CHANNEL_TXMAINCURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_1->GTPE2_CHANNEL_RXSLIDE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSLIDE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR3->GTPE2_LOGIC_OUTS_B3_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_8->GTPE2_CHANNEL_TXPRBSSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX10_3->GTPE2_CHANNEL_TXPIPPMOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX34_2->GTPE2_CHANNEL_DRPADDR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCLKCORCNT1->GTPE2_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX38_9->GTPE2_CHANNEL_DRPDI5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX27_8->GTPE2_CHANNEL_TXCOMSAS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMSAS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA28->GTPE2_LOGIC_OUTS_B3_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA28", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR2->GTPE2_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO6->GTPE2_LOGIC_OUTS_B22_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX43_10->GTPE2_CHANNEL_RXLPMHFHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMHFHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX12_7->GTPE2_CHANNEL_TXBUFDIFFCTRL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_7->GTPE2_CHANNEL_TSTIN6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX9_6->GTPE2_CHANNEL_PCSRSVDIN11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA8->GTPE2_LOGIC_OUTS_B6_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA2->GTPE2_LOGIC_OUTS_B4_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTARTOFSEQ1->GTPE2_LOGIC_OUTS_B11_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX35_4->GTPE2_CHANNEL_TXMARGIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX29_10->GTPE2_CHANNEL_TXDATA27": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA27", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT4->GTPE2_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR0->GTPE2_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_5->GTPE2_CHANNEL_TSTIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDO3->GTPE2_LOGIC_OUTS_B16_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHBONDO3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX4_8->GTPE2_CHANNEL_TXOUTCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_3->GTPE2_CHANNEL_GTRSVD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX10_6->GTPE2_CHANNEL_DRPDI1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA17->GTPE2_LOGIC_OUTS_B2_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA17", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX46_1->GTPE2_CHANNEL_RXPCSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPCSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_6->GTPE2_CHANNEL_GTRSVD3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXPMARESETDONE->GTPE2_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPMARESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX5_0->GTPE2_CHANNEL_RXCHBONDLEVEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX11_3->GTPE2_CHANNEL_TXRATEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT3->GTPE2_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX31_0->GTPE2_CHANNEL_TXUSERRDY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSERRDY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXRESETDONE->GTPE2_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL1_5->GTPE2_CHANNEL_CFGRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CFGRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT13->GTPE2_LOGIC_OUTS_B9_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_4->GTPE2_CHANNEL_TXCHARDISPVAL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISK3->GTPE2_LOGIC_OUTS_B12_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT1->GTPE2_LOGIC_OUTS_B9_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA5->GTPE2_LOGIC_OUTS_B7_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX2_1->GTPE2_CHANNEL_TXCOMINIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCOMINIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_1->GTPE2_CHANNEL_TXSYNCIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX2_10->GTPE2_CHANNEL_RXOUTCLKSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX15_9->GTPE2_CHANNEL_RXOSINTEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX30_8->GTPE2_CHANNEL_RXCDRHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX38_2->GTPE2_CHANNEL_DRPADDR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO8->GTPE2_LOGIC_OUTS_B12_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX13_10->GTPE2_CHANNEL_RXPRBSCNTRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSCNTRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX27_10->GTPE2_CHANNEL_RXLPMHFOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMHFOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX9_4->GTPE2_CHANNEL_PCSRSVDIN9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX35_10->GTPE2_CHANNEL_RXOSINTCFG2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRLOCK->GTPE2_LOGIC_OUTS_B17_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCDRLOCK", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX34_6->GTPE2_CHANNEL_DRPDI8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX1_8->GTPE2_CHANNEL_TXOUTCLKSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX31_7->GTPE2_CHANNEL_TXCHARISK0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSERR->GTPE2_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPRBSERR", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX46_4->GTPE2_CHANNEL_TXCHARDISPVAL3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX26_3->GTPE2_CHANNEL_GTRSVD8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX37_7->GTPE2_CHANNEL_PMARSVDIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_0->GTPE2_CHANNEL_RXOSINTPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX34_4->GTPE2_CHANNEL_SETERRSTATUS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_SETERRSTATUS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATEDONE->GTPE2_LOGIC_OUTS_B23_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXRATEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXELECIDLE->GTPE2_LOGIC_OUTS_B19_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXELECIDLE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX18_5->GTPE2_CHANNEL_TXDATA8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX41_7->GTPE2_CHANNEL_RXADAPTSELTEST6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX15_5->GTPE2_CHANNEL_TX8B10BBYPASS1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX1_4->GTPE2_CHANNEL_TXMAINCURSOR6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_9->GTPE2_CHANNEL_GTRSVD6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL0_10->GTPE2_CHANNEL_GTRESETSEL": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRESETSEL", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_2->GTPE2_CHANNEL_RXSYSCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX43_6->GTPE2_CHANNEL_TXRATE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX45_8->GTPE2_CHANNEL_EYESCANRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX2_0->GTPE2_CHANNEL_EYESCANMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO5->GTPE2_LOGIC_OUTS_B12_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO7->GTPE2_LOGIC_OUTS_B4_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT14->GTPE2_LOGIC_OUTS_B10_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX46_10->GTPE2_CHANNEL_RXOSINTCFG3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_0->GTPE2_CHANNEL_TXSEQUENCE6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO2->GTPE2_LOGIC_OUTS_B4_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX31_4->GTPE2_CHANNEL_TX8B10BBYPASS3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_4->GTPE2_CHANNEL_TXPOSTCURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PLLCLK0->GTPE2_CHANNEL_PLL0CLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL0CLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLCLK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_8->GTPE2_CHANNEL_TSTIN7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B7_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PMARSVDOUT1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL1_7->GTPE2_CHANNEL_RXPMARESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPMARESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_10->GTPE2_CHANNEL_RXLPMLFOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMLFOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR0->GTPE2_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX24_3->GTPE2_CHANNEL_TSTIN12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX36_2->GTPE2_CHANNEL_RXSYNCALLIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCALLIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX5_8->GTPE2_CHANNEL_TXOUTCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX5_4->GTPE2_CHANNEL_TXMAINCURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX23_9->GTPE2_CHANNEL_RXCHBONDI3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXRESETDONE->GTPE2_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR3->GTPE2_LOGIC_OUTS_B6_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX14_6->GTPE2_CHANNEL_RXRATE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA1->GTPE2_LOGIC_OUTS_B2_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDISPERR3->GTPE2_LOGIC_OUTS_B22_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX5_5->GTPE2_CHANNEL_RXLPMLFHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXLPMLFHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO1->GTPE2_LOGIC_OUTS_B22_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX15_3->GTPE2_CHANNEL_TX8B10BBYPASS2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFSTATUS1->GTPE2_LOGIC_OUTS_B19_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATEDONE->GTPE2_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXRATEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX31_8->GTPE2_CHANNEL_EYESCANTRIGGER": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_EYESCANTRIGGER", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK0_5->GTPE2_CHANNEL_TXUSRCLK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSRCLK2", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX6_7->GTPE2_CHANNEL_RXADAPTSELTEST5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_4->GTPE2_CHANNEL_GTRSVD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX24_6->GTPE2_CHANNEL_TSTIN15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX14_1->GTPE2_CHANNEL_TXPRBSFORCEERR": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSFORCEERR", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B15_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXOUTCLKFABRIC", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX25_10->GTPE2_CHANNEL_PCSRSVDIN7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX41_0->GTPE2_CHANNEL_RXDLYOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX23_8->GTPE2_CHANNEL_RXPRBSSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX30_10->GTPE2_CHANNEL_RXCHBONDSLAVE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDSLAVE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX22_3->GTPE2_CHANNEL_TXDATA18": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA18", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX26_7->GTPE2_CHANNEL_GTRSVD12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_4->GTPE2_CHANNEL_TSTIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX15_7->GTPE2_CHANNEL_TX8B10BBYPASS0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX24_5->GTPE2_CHANNEL_TSTIN14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX13_4->GTPE2_CHANNEL_TSTIN10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK1_5->GTPE2_CHANNEL_DMONITORCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DMONITORCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX45_3->GTPE2_CHANNEL_TXDLYSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXNOTINTABLE0->GTPE2_LOGIC_OUTS_B14_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISCOMMA2->GTPE2_LOGIC_OUTS_B15_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR4->GTPE2_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_9->GTPE2_CHANNEL_TSTIN8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_5->GTPE2_CHANNEL_TXDIFFCTRL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_6->GTPE2_CHANNEL_TXPRECURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT2->GTPE2_LOGIC_OUTS_B9_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA7->GTPE2_LOGIC_OUTS_B5_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX32_8->GTPE2_CHANNEL_RXDLYBYPASS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYBYPASS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA15->GTPE2_LOGIC_OUTS_B5_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX1_9->GTPE2_CHANNEL_RXOSINTHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX47_9->GTPE2_CHANNEL_LOOPBACK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX26_4->GTPE2_CHANNEL_GTRSVD9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX46_9->GTPE2_CHANNEL_LOOPBACK1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT7->GTPE2_LOGIC_OUTS_B13_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX38_6->GTPE2_CHANNEL_TXPD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX14_0->GTPE2_CHANNEL_TXPDELECIDLEMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPDELECIDLEMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK0_6->GTPE2_CHANNEL_RXUSRCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSRCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX32_5->GTPE2_CHANNEL_DRPDI11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX22_5->GTPE2_CHANNEL_TXDATA10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX24_7->GTPE2_CHANNEL_TSTIN16": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN16", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT6->GTPE2_LOGIC_OUTS_B13_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA4->GTPE2_LOGIC_OUTS_B3_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX0_7->GTPE2_CHANNEL_RXADAPTSELTEST0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX13_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX25_8->GTPE2_CHANNEL_PCSRSVDIN5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT2->GTPE2_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHINITDONE->GTPE2_LOGIC_OUTS_B1_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPHINITDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT5->GTPE2_LOGIC_OUTS_B9_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_5->GTPE2_CHANNEL_GTRSVD2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL0_8->GTPE2_CHANNEL_GTRXRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRXRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX46_0->GTPE2_CHANNEL_TXPCSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPCSRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXDLYSRESETDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXNOTINTABLE3->GTPE2_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA23->GTPE2_LOGIC_OUTS_B5_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA23", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX23_3->GTPE2_CHANNEL_TXDATA19": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA19", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA14->GTPE2_LOGIC_OUTS_B1_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA14", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX24_9->GTPE2_CHANNEL_TSTIN18": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN18", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX30_7->GTPE2_CHANNEL_RXPD0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO3->GTPE2_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT13->GTPE2_LOGIC_OUTS_B1_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX27_7->GTPE2_CHANNEL_RXPOLARITY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPOLARITY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_9->GTPE2_CHANNEL_DRPDI4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFSTATUS0->GTPE2_LOGIC_OUTS_B23_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISCOMMA3->GTPE2_LOGIC_OUTS_B15_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFSTATUS1->GTPE2_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX41_6->GTPE2_CHANNEL_RXPHALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX16_1->GTPE2_CHANNEL_TXDATA28": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA28", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXPHALIGNDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT9->GTPE2_LOGIC_OUTS_B21_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX35_6->GTPE2_CHANNEL_TXPD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX30_3->GTPE2_CHANNEL_TXPOLARITY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOLARITY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL1_9->GTPE2_CHANNEL_RXCDRRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR1->GTPE2_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX28_10->GTPE2_CHANNEL_RXOSINTID01": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID01", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISK2->GTPE2_LOGIC_OUTS_B12_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT8->GTPE2_LOGIC_OUTS_B13_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDISPERR1->GTPE2_LOGIC_OUTS_B22_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX5_2->GTPE2_CHANNEL_PMARSVDIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX44_9->GTPE2_CHANNEL_RXCOMMADETEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCOMMADETEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX29_2->GTPE2_CHANNEL_TXCHARDISPMODE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXHEADER0->GTPE2_LOGIC_OUTS_B19_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX22_8->GTPE2_CHANNEL_RXPRBSSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX2_4->GTPE2_CHANNEL_TXPOSTCURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX35_3->GTPE2_CHANNEL_DRPADDR6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX38_4->GTPE2_CHANNEL_TXMARGIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_7->GTPE2_CHANNEL_RXPHDLYPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHDLYPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT11->GTPE2_LOGIC_OUTS_B5_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT8->GTPE2_LOGIC_OUTS_B21_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_3->GTPE2_CHANNEL_TXSTARTSEQ": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSTARTSEQ", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA6->GTPE2_LOGIC_OUTS_B1_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX39_3->GTPE2_CHANNEL_DRPADDR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PLLREFCLK1->GTPE2_CHANNEL_PLL1REFCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL1REFCLK", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLREFCLK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA0->GTPE2_LOGIC_OUTS_B6_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX0_8->GTPE2_CHANNEL_RXADAPTSELTEST10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX6_8->GTPE2_CHANNEL_TXPRBSSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX17_10->GTPE2_CHANNEL_DRPDI14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL1_10->GTPE2_CHANNEL_RXOOBRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOOBRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_6->GTPE2_CHANNEL_TXPRECURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX44_7->GTPE2_CHANNEL_RXADAPTSELTEST7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPRDY->GTPE2_LOGIC_OUTS_B14_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPRDY", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX35_1->GTPE2_CHANNEL_TXSEQUENCE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX45_7->GTPE2_CHANNEL_TXPISOPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPISOPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX37_4->GTPE2_CHANNEL_TXDIFFPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX41_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX20_4->GTPE2_CHANNEL_TXDATA14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX35_0->GTPE2_CHANNEL_TXSEQUENCE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDISPERR2->GTPE2_LOGIC_OUTS_B22_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX12_5->GTPE2_CHANNEL_TXDLYOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX26_5->GTPE2_CHANNEL_GTRSVD10": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT10->GTPE2_LOGIC_OUTS_B13_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_0->GTPE2_CHANNEL_RXSYNCIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCDONE->GTPE2_LOGIC_OUTS_B14_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSYNCDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX31_1->GTPE2_CHANNEL_TXHEADER1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX29_8->GTPE2_CHANNEL_RXOSHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX25_7->GTPE2_CHANNEL_PCSRSVDIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX17_4->GTPE2_CHANNEL_TXDATA13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX19_7->GTPE2_CHANNEL_TXDATA1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX13_0->GTPE2_CHANNEL_TXSYNCMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX43_5->GTPE2_CHANNEL_TXDLYUPDOWN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYUPDOWN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX44_10->GTPE2_CHANNEL_TXDATA26": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA26", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL1_6->GTPE2_CHANNEL_RXBUFRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXBUFRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTROBESTARTED->GTPE2_LOGIC_OUTS_B0_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX11_7->GTPE2_CHANNEL_RXADAPTSELTEST9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA9->GTPE2_LOGIC_OUTS_B2_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX18_7->GTPE2_CHANNEL_TXDATA0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX17_8->GTPE2_CHANNEL_RXADAPTSELTEST11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL0_5->GTPE2_CHANNEL_GTTXRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTTXRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXVALID->GTPE2_LOGIC_OUTS_B20_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXVALID", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX25_5->GTPE2_CHANNEL_PCSRSVDIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_9->GTPE2_CHANNEL_DRPDI7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX21_8->GTPE2_CHANNEL_RXADAPTSELTEST13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX31_3->GTPE2_CHANNEL_TXCHARISK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX6_6->GTPE2_CHANNEL_TXPRECURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_1->GTPE2_CHANNEL_RXPCOMMAALIGNEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX37_8->GTPE2_CHANNEL_PMARSVDIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX37_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX22_7->GTPE2_CHANNEL_TXDATA2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX21_6->GTPE2_CHANNEL_TXDATA7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA12->GTPE2_LOGIC_OUTS_B3_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX25_4->GTPE2_CHANNEL_PCSRSVDIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX47_6->GTPE2_CHANNEL_TXRATE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXRATE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBYTEREALIGN->GTPE2_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBYTEREALIGN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_6->GTPE2_CHANNEL_TSTIN5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX35_2->GTPE2_CHANNEL_DRPADDR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_8->GTPE2_CHANNEL_GTRSVD5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA29->GTPE2_LOGIC_OUTS_B7_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA29", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT4->GTPE2_LOGIC_OUTS_B9_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_2->GTPE2_CHANNEL_TXCHARDISPVAL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX35_5->GTPE2_CHANNEL_TXDEEMPH": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDEEMPH", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFSTATUS2->GTPE2_LOGIC_OUTS_B17_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX9_9->GTPE2_CHANNEL_PCSRSVDIN14": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX27_1->GTPE2_CHANNEL_TXSEQUENCE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXNOTINTABLE2->GTPE2_LOGIC_OUTS_B14_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_0->GTPE2_CHANNEL_RXSYNCMODE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYNCMODE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX34_3->GTPE2_CHANNEL_DRPADDR7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX34_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_7->GTPE2_CHANNEL_TXPRECURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT5->GTPE2_LOGIC_OUTS_B13_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX25_6->GTPE2_CHANNEL_PCSRSVDIN3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX16_4->GTPE2_CHANNEL_TXDATA12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT6->GTPE2_LOGIC_OUTS_B9_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX0_3->GTPE2_CHANNEL_TXMAINCURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX0_9->GTPE2_CHANNEL_RXOSINTOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX20_6->GTPE2_CHANNEL_TXDATA6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX13_8->GTPE2_CHANNEL_RXOSOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX19_3->GTPE2_CHANNEL_TXDATA17": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA17", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX43_9->GTPE2_CHANNEL_LOOPBACK0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_LOOPBACK0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX43_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK1_2->GTPE2_CHANNEL_TXPHDLYTSTCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYTSTCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX20_1->GTPE2_CHANNEL_TXDATA30": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA30", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX24_4->GTPE2_CHANNEL_TSTIN13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX11_5->GTPE2_CHANNEL_TXDLYHOLD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYHOLD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR2->GTPE2_LOGIC_OUTS_B7_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_2", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHMONITOR2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK0_9->GTPE2_CHANNEL_DRPCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_2->GTPE2_CHANNEL_TSTIN1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX16_2->GTPE2_CHANNEL_TXDATA20": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA20", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX44_2->GTPE2_CHANNEL_TXSYNCALLIN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYNCALLIN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHALIGNDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX44_0->GTPE2_CHANNEL_TXPHOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO0->GTPE2_LOGIC_OUTS_B12_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA19->GTPE2_LOGIC_OUTS_B0_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA19", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXN_PAD->GTPE2_CHANNEL_RXN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXN", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXN_PAD", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXHEADER2->GTPE2_LOGIC_OUTS_B17_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX21_1->GTPE2_CHANNEL_TXDATA31": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA31", - "is_directional": "1", - "src_wire": "GTPE2_IMUX21_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK1_8->GTPE2_CHANNEL_CLKRSVD1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_CLKRSVD1", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX45_2->GTPE2_CHANNEL_RXSYSCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL0_6->GTPE2_CHANNEL_RXDLYSRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYSRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX5_7->GTPE2_CHANNEL_RXADAPTSELTEST3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX4_0->GTPE2_CHANNEL_RXCHBONDLEVEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX44_1->GTPE2_CHANNEL_DMONFIFORESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DMONFIFORESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX4_10->GTPE2_CHANNEL_RXOUTCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISK0->GTPE2_LOGIC_OUTS_B12_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXNOTINTABLE1->GTPE2_LOGIC_OUTS_B14_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_5->GTPE2_CHANNEL_TXDIFFCTRL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCLKCORCNT0->GTPE2_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMINITDET->GTPE2_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMINITDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B15_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PMARSVDOUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX12_3->GTPE2_CHANNEL_TXCHARDISPMODE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX12_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX32_6->GTPE2_CHANNEL_DRPDI3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX45_4->GTPE2_CHANNEL_TSTIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4->GTPE2_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTARTOFSEQ0->GTPE2_LOGIC_OUTS_B18_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXHEADER1->GTPE2_LOGIC_OUTS_B23_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXHEADER1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX6_4->GTPE2_CHANNEL_TXPOSTCURSOR1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX36_7->GTPE2_CHANNEL_RXOSINTNTRLEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTNTRLEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX2_6->GTPE2_CHANNEL_TXPRECURSOR3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA22->GTPE2_LOGIC_OUTS_B1_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA22", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_0->GTPE2_CHANNEL_TXPIPPMEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX39_6->GTPE2_CHANNEL_TXELECIDLE": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXELECIDLE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO15->GTPE2_LOGIC_OUTS_B4_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO15", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX23_7->GTPE2_CHANNEL_TXDATA3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX47_4->GTPE2_CHANNEL_TXCHARISK3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX47_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL1_3->GTPE2_CHANNEL_TXPMARESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPMARESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX23_5->GTPE2_CHANNEL_TXDATA11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX23_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX9_8->GTPE2_CHANNEL_PCSRSVDIN13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX24_2->GTPE2_CHANNEL_TSTIN11": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX2_5->GTPE2_CHANNEL_TXDIFFCTRL3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX45_1->GTPE2_CHANNEL_RX8B10BEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RX8B10BEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX27_0->GTPE2_CHANNEL_TXSEQUENCE3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX18_3->GTPE2_CHANNEL_TXDATA16": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA16", - "is_directional": "1", - "src_wire": "GTPE2_IMUX18_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX4_7->GTPE2_CHANNEL_RXADAPTSELTEST2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA30->GTPE2_LOGIC_OUTS_B1_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B1_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA30", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX14_9->GTPE2_CHANNEL_RXPHALIGN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHALIGN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHANBONDSEQ->GTPE2_LOGIC_OUTS_B8_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANBONDSEQ", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA3->GTPE2_LOGIC_OUTS_B0_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_6->GTPE2_CHANNEL_TXCHARDISPVAL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMSASDET->GTPE2_LOGIC_OUTS_B18_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMSASDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX38_3->GTPE2_CHANNEL_DRPADDR5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXP_PAD->GTPE2_CHANNEL_RXP": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXP", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXP_PAD", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA26->GTPE2_LOGIC_OUTS_B4_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA26", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX29_6->GTPE2_CHANNEL_TXCHARDISPMODE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_10->GTPE2_CHANNEL_TXDATA24": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA24", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX15_6->GTPE2_CHANNEL_RXRATE0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX39_5->GTPE2_CHANNEL_TXDETECTRX": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDETECTRX", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_10->GTPE2_CHANNEL_GTRSVD7": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCDONE->GTPE2_LOGIC_OUTS_B22_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXSYNCDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX16_10->GTPE2_CHANNEL_DRPDI15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO13->GTPE2_LOGIC_OUTS_B15_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANDATAERROR->GTPE2_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_EYESCANDATAERROR", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX9_10->GTPE2_CHANNEL_PCSRSVDIN15": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX9_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PHYSTATUS->GTPE2_LOGIC_OUTS_B10_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PHYSTATUS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_3->GTPE2_CHANNEL_TSTIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT7->GTPE2_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX31_5->GTPE2_CHANNEL_TXCHARISK1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARISK1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX31_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX4_4->GTPE2_CHANNEL_TXMAINCURSOR5": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX4_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX24_8->GTPE2_CHANNEL_TSTIN17": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN17", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL1_4->GTPE2_CHANNEL_RXPHDLYRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHDLYRESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_1->GTPE2_CHANNEL_TXSEQUENCE4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_8->GTPE2_CHANNEL_TXPRBSSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX22_9->GTPE2_CHANNEL_RXCHBONDI2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX29_4->GTPE2_CHANNEL_TXCHARDISPMODE1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE->GTPE2_LOGIC_OUTS_B0_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX30_9->GTPE2_CHANNEL_RXCHBONDMASTER": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDMASTER", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX25_2->GTPE2_CHANNEL_TXPHALIGN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHALIGN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX44_5->GTPE2_CHANNEL_TXDLYBYPASS": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDLYBYPASS", - "is_directional": "1", - "src_wire": "GTPE2_IMUX44_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX19_5->GTPE2_CHANNEL_TXDATA9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO4->GTPE2_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK0_7->GTPE2_CHANNEL_RXUSRCLK2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSRCLK2", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_GTTXOUTCLK_3->GTPE2_CHANNEL_TXOUTCLK_3": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXOUTCLK_3", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_GTTXOUTCLK_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX38_5->GTPE2_CHANNEL_TXSWING": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSWING", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX26_8->GTPE2_CHANNEL_GTRSVD13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX26_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX36_10->GTPE2_CHANNEL_DRPDI13": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT12->GTPE2_LOGIC_OUTS_B7_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX36_5->GTPE2_CHANNEL_TXPHDLYRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPHDLYRESET", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX11_6->GTPE2_CHANNEL_RXRATE2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXRATE2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX6_10->GTPE2_CHANNEL_RXOSINTCFG1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKPCS->GTPE2_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXOUTCLKPCS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX14_8->GTPE2_CHANNEL_RXCDROVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDROVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT11->GTPE2_LOGIC_OUTS_B21_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT11", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX10_10->GTPE2_CHANNEL_RXOSINTID02": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID02", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX5_10->GTPE2_CHANNEL_RXOUTCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX10_7->GTPE2_CHANNEL_TXBUFDIFFCTRL2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_8" }, "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT12->GTPE2_LOGIC_OUTS_B15_2": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_2", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_DMONITOROUT12", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX24_10->GTPE2_CHANNEL_TSTIN19": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN19", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX19_9->GTPE2_CHANNEL_RXCHBONDI1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX19_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX17_2->GTPE2_CHANNEL_TXDATA21": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA21", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX25_9->GTPE2_CHANNEL_PCSRSVDIN6": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX25_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX8_3->GTPE2_CHANNEL_TXPIPPMSEL": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSEL", - "is_directional": "1", - "src_wire": "GTPE2_IMUX8_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX14_10->GTPE2_CHANNEL_RXPHOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXPHOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_3->GTPE2_CHANNEL_TXPOSTCURSOR4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT0->GTPE2_LOGIC_OUTS_B9_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX30_6->GTPE2_CHANNEL_TXPOSTCURSORINV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSORINV", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA21->GTPE2_LOGIC_OUTS_B7_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA21", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX7_4->GTPE2_CHANNEL_TXPOSTCURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX7_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX5_3->GTPE2_CHANNEL_TXMAINCURSOR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMMADET->GTPE2_LOGIC_OUTS_B19_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMMADET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO10->GTPE2_LOGIC_OUTS_B2_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B2_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA16->GTPE2_LOGIC_OUTS_B6_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B6_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA16", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA18->GTPE2_LOGIC_OUTS_B4_6": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_6", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA18", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX42_7->GTPE2_CHANNEL_GTRSVD4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_GTRSVD4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA20->GTPE2_LOGIC_OUTS_B3_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B3_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA20", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX36_8->GTPE2_CHANNEL_RXADAPTSELTEST12": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX36_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX16_6->GTPE2_CHANNEL_TXDATA4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXDATA4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX16_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISK1->GTPE2_LOGIC_OUTS_B12_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISK1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMWAKEDET->GTPE2_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCOMWAKEDET", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX32_2->GTPE2_CHANNEL_TXINHIBIT": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXINHIBIT", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK1_4->GTPE2_CHANNEL_SIGVALIDCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_SIGVALIDCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDISPERR0->GTPE2_LOGIC_OUTS_B22_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDISPERR0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX5_9->GTPE2_CHANNEL_RXOSINTTESTOVRDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTATUS0->GTPE2_LOGIC_OUTS_B21_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX13_7->GTPE2_CHANNEL_TXBUFDIFFCTRL1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX13_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX28_5->GTPE2_CHANNEL_TXSYSCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_5", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX17_9->GTPE2_CHANNEL_RXCHBONDEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX17_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL1_8->GTPE2_CHANNEL_RXCDRRESETRSV": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRRESETRSV", - "is_directional": "1", - "src_wire": "GTPE2_CTRL1_8", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX28_6->GTPE2_CHANNEL_RXDLYEN": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXDLYEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX28_6", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX3_2->GTPE2_CHANNEL_PMARSVDIN4": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHANREALIGN->GTPE2_LOGIC_OUTS_B23_9": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_9", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHANREALIGN", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA27->GTPE2_LOGIC_OUTS_B0_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B0_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA27", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKPCS->GTPE2_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOUTCLKPCS", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATAVALID1->GTPE2_LOGIC_OUTS_B5_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATAVALID1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX6_1->GTPE2_CHANNEL_RXGEARBOXSLIP": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXGEARBOXSLIP", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXGEARBOXREADY->GTPE2_LOGIC_OUTS_B23_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_4", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXGEARBOXREADY", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX40_10->GTPE2_CHANNEL_TSTIN9": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TSTIN9", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX11_10->GTPE2_CHANNEL_RXOSINTID03": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID03", - "is_directional": "1", - "src_wire": "GTPE2_IMUX11_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXOUTCLKFABRIC", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX10_9->GTPE2_CHANNEL_PMARSVDIN2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PMARSVDIN2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX10_9", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX39_4->GTPE2_CHANNEL_TXMARGIN0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMARGIN0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX6_0->GTPE2_CHANNEL_RXUSERRDY": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXUSERRDY", - "is_directional": "1", - "src_wire": "GTPE2_IMUX6_0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX39_2->GTPE2_CHANNEL_DRPADDR0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPADDR0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX39_1->GTPE2_CHANNEL_TXHEADER0": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXHEADER0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX39_1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_TXCOMFINISH->GTPE2_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_TXCOMFINISH", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CLK0_4->GTPE2_CHANNEL_TXUSRCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXUSRCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_4", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX1_3->GTPE2_CHANNEL_TXMAINCURSOR2": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTATUS1->GTPE2_LOGIC_OUTS_B17_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS1", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX29_7->GTPE2_CHANNEL_RXADAPTSELTEST8": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX29_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT0->GTPE2_LOGIC_OUTS_B5_10": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B5_10", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT0", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT10->GTPE2_LOGIC_OUTS_B21_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B21_5", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DMONITOROUT10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA13->GTPE2_LOGIC_OUTS_B7_7": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B7_7", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXDATA13", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX46_3->GTPE2_CHANNEL_TXPIPPMPD": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMPD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX46_3", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX15_10->GTPE2_CHANNEL_RXOSINTID00": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTID00", - "is_directional": "1", - "src_wire": "GTPE2_IMUX15_10", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTATUS2->GTPE2_LOGIC_OUTS_B23_8": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B23_8", - "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXSTATUS2", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_IMUX1_7->GTPE2_CHANNEL_RXADAPTSELTEST1": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX1_7", - "is_pseudo": "0" - }, - "GTP_CHANNEL_3.GTPE2_CTRL0_7->GTPE2_CHANNEL_RXCDRFREQRESET": { - "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCDRFREQRESET", "is_directional": "1", - "src_wire": "GTPE2_CTRL0_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_2" }, - "GTP_CHANNEL_3.GTPE2_IMUX44_3->GTPE2_CHANNEL_DRPEN": { + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO1->GTPE2_LOGIC_OUTS_B22_3": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPEN", + "src_wire": "GTPE2_CHANNEL_DRPDO1", "is_directional": "1", - "src_wire": "GTPE2_IMUX44_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_3" }, - "GTP_CHANNEL_3.GTPE2_IMUX38_10->GTPE2_CHANNEL_RXOSINTCFG0": { + "GTP_CHANNEL_3.GTPE2_IMUX31_1->GTPE2_CHANNEL_TXHEADER1": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG0", + "src_wire": "GTPE2_IMUX31_1", "is_directional": "1", - "src_wire": "GTPE2_IMUX38_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER1" }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PLLREFCLK0->GTPE2_CHANNEL_PLL0REFCLK": { + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA11->GTPE2_LOGIC_OUTS_B0_8": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PLL0REFCLK", + "src_wire": "GTPE2_CHANNEL_RXDATA11", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PLLREFCLK0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_8" }, - "GTP_CHANNEL_3.GTPE2_IMUX45_6->GTPE2_CHANNEL_DRPDI0": { + "GTP_CHANNEL_3.GTPE2_IMUX12_5->GTPE2_CHANNEL_TXDLYOVRDEN": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_DRPDI0", + "src_wire": "GTPE2_IMUX12_5", "is_directional": "1", - "src_wire": "GTPE2_IMUX45_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYOVRDEN" }, - "GTP_CHANNEL_3.GTPE2_IMUX35_8->GTPE2_CHANNEL_TXPIPPMSTEPSIZE3": { + "GTP_CHANNEL_3.GTPE2_IMUX38_5->GTPE2_CHANNEL_TXSWING": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", + "src_wire": "GTPE2_IMUX38_5", "is_directional": "1", - "src_wire": "GTPE2_IMUX35_8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSWING" }, - "GTP_CHANNEL_3.GTPE2_IMUX9_7->GTPE2_CHANNEL_PCSRSVDIN12": { + "GTP_CHANNEL_3.GTPE2_CTRL0_5->GTPE2_CHANNEL_GTTXRESET": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN12", + "src_wire": "GTPE2_CTRL0_5", "is_directional": "1", - "src_wire": "GTPE2_IMUX9_7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTTXRESET" }, - "GTP_CHANNEL_3.GTPE2_IMUX1_10->GTPE2_CHANNEL_RXELECIDLEMODE1": { + "GTP_CHANNEL_3.GTPE2_IMUX18_5->GTPE2_CHANNEL_TXDATA8": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE1", + "src_wire": "GTPE2_IMUX18_5", "is_directional": "1", - "src_wire": "GTPE2_IMUX1_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA8" }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO9->GTPE2_LOGIC_OUTS_B4_9": { + "GTP_CHANNEL_3.GTPE2_IMUX29_4->GTPE2_CHANNEL_TXCHARDISPMODE1": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B4_9", + "src_wire": "GTPE2_IMUX29_4", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_DRPDO9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE1" }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT9->GTPE2_LOGIC_OUTS_B13_9": { + "GTP_CHANNEL_3.GTPE2_IMUX5_10->GTPE2_CHANNEL_RXOUTCLKSEL1": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_9", + "src_wire": "GTPE2_IMUX5_10", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL1" }, - "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISCOMMA1->GTPE2_LOGIC_OUTS_B15_7": { + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO7->GTPE2_LOGIC_OUTS_B4_5": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B15_7", + "src_wire": "GTPE2_CHANNEL_DRPDO7", "is_directional": "1", - "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_5" }, - "GTP_CHANNEL_3.GTPE2_IMUX18_9->GTPE2_CHANNEL_RXCHBONDI0": { + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO15->GTPE2_LOGIC_OUTS_B4_7": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_RXCHBONDI0", + "src_wire": "GTPE2_CHANNEL_DRPDO15", "is_directional": "1", - "src_wire": "GTPE2_IMUX18_9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_7" }, "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPMARESETDONE->GTPE2_LOGIC_OUTS_B12_2": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B12_2", - "is_directional": "1", "src_wire": "GTPE2_CHANNEL_RXPMARESETDONE", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMMADET->GTPE2_LOGIC_OUTS_B19_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMMADET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT3->GTPE2_LOGIC_OUTS_B13_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTROBEDONE->GTPE2_LOGIC_OUTS_B0_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX17_9->GTPE2_CHANNEL_RXCHBONDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDEN" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO6->GTPE2_LOGIC_OUTS_B22_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX6_10->GTPE2_CHANNEL_RXOSINTCFG1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX43_6->GTPE2_CHANNEL_TXRATE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX15_6->GTPE2_CHANNEL_RXRATE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA9->GTPE2_LOGIC_OUTS_B2_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX45_8->GTPE2_CHANNEL_EYESCANRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANRESET" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXDLYSRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX32_7->GTPE2_CHANNEL_TXPRECURSORINV": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSORINV" + }, + "GTP_CHANNEL_3.GTPE2_CLK1_8->GTPE2_CHANNEL_CLKRSVD1": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CLKRSVD1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX39_1->GTPE2_CHANNEL_TXHEADER0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX23_3->GTPE2_CHANNEL_TXDATA19": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA19" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXHEADERVALID->GTPE2_LOGIC_OUTS_B14_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADERVALID", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX26_10->GTPE2_CHANNEL_GTRSVD15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD15" + }, + "GTP_CHANNEL_3.GTPE2_IMUX45_3->GTPE2_CHANNEL_TXDLYSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYSRESET" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PLLCLK1->GTPE2_CHANNEL_PLL1CLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL1CLK" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR4->GTPE2_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO13->GTPE2_LOGIC_OUTS_B15_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_8" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA18->GTPE2_LOGIC_OUTS_B4_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_10->GTPE2_CHANNEL_GTRSVD7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX26_9->GTPE2_CHANNEL_GTRSVD14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD14" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA2->GTPE2_LOGIC_OUTS_B4_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX15_7->GTPE2_CHANNEL_TX8B10BBYPASS0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX38_2->GTPE2_CHANNEL_DRPADDR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX1_10->GTPE2_CHANNEL_RXELECIDLEMODE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO10->GTPE2_LOGIC_OUTS_B2_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX9_6->GTPE2_CHANNEL_PCSRSVDIN11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN11" + }, + "GTP_CHANNEL_3.GTPE2_IMUX27_1->GTPE2_CHANNEL_TXSEQUENCE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX5_0->GTPE2_CHANNEL_RXCHBONDLEVEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX44_9->GTPE2_CHANNEL_RXCOMMADETEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCOMMADETEN" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA19->GTPE2_LOGIC_OUTS_B0_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFSTATUS0->GTPE2_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX25_10->GTPE2_CHANNEL_PCSRSVDIN7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO3->GTPE2_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_8->GTPE2_CHANNEL_TXPRBSSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT13->GTPE2_LOGIC_OUTS_B9_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX46_3->GTPE2_CHANNEL_TXPIPPMPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMPD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX6_9->GTPE2_CHANNEL_DRPDI6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_6->GTPE2_CHANNEL_GTRSVD3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX14_0->GTPE2_CHANNEL_TXPDELECIDLEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPDELECIDLEMODE" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_7->GTPE2_CHANNEL_RXPHDLYPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHDLYPD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX33_5->GTPE2_CHANNEL_DRPDI10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX33_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX38_6->GTPE2_CHANNEL_TXPD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPD0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_8->GTPE2_CHANNEL_TXPRBSSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX46_4->GTPE2_CHANNEL_TXCHARDISPVAL3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCLKCORCNT1->GTPE2_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISCOMMA2->GTPE2_LOGIC_OUTS_B15_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX44_7->GTPE2_CHANNEL_RXADAPTSELTEST7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX27_5->GTPE2_CHANNEL_TXPHINIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHINIT" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCLKCORCNT0->GTPE2_LOGIC_OUTS_B11_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCLKCORCNT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX9_8->GTPE2_CHANNEL_PCSRSVDIN13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN13" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_6->GTPE2_CHANNEL_TXPRECURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX6_5->GTPE2_CHANNEL_TXDIFFCTRL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX24_2->GTPE2_CHANNEL_TSTIN11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN11" + }, + "GTP_CHANNEL_3.GTPE2_IMUX19_9->GTPE2_CHANNEL_RXCHBONDI1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX16_1->GTPE2_CHANNEL_TXDATA28": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA28" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXRESETDONE->GTPE2_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX13_4->GTPE2_CHANNEL_TSTIN10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX34_4->GTPE2_CHANNEL_SETERRSTATUS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_SETERRSTATUS" + }, + "GTP_CHANNEL_3.GTPE2_IMUX35_10->GTPE2_CHANNEL_RXOSINTCFG2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX30_10->GTPE2_CHANNEL_RXCHBONDSLAVE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDSLAVE" + }, + "GTP_CHANNEL_3.GTPE2_IMUX6_6->GTPE2_CHANNEL_TXPRECURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR2->GTPE2_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT5->GTPE2_LOGIC_OUTS_B9_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX47_4->GTPE2_CHANNEL_TXCHARISK3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHANREALIGN->GTPE2_LOGIC_OUTS_B23_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANREALIGN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX39_0->GTPE2_CHANNEL_TXHEADER2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXHEADER2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_1->GTPE2_CHANNEL_TXSEQUENCE4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX45_5->GTPE2_CHANNEL_DRPDI9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX9_7->GTPE2_CHANNEL_PCSRSVDIN12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN12" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_2->GTPE2_CHANNEL_TXCHARDISPVAL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX43_5->GTPE2_CHANNEL_TXDLYUPDOWN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYUPDOWN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX22_8->GTPE2_CHANNEL_RXPRBSSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKPCS->GTPE2_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOUTCLKPCS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX1_0->GTPE2_CHANNEL_RXCHBONDLEVEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX21_2->GTPE2_CHANNEL_TXDATA23": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA23" + }, + "GTP_CHANNEL_3.GTPE2_IMUX31_3->GTPE2_CHANNEL_TXCHARISK2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX35_1->GTPE2_CHANNEL_TXSEQUENCE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFSTATUS2->GTPE2_LOGIC_OUTS_B17_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX10_7->GTPE2_CHANNEL_TXBUFDIFFCTRL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXELECIDLE->GTPE2_LOGIC_OUTS_B19_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_8" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDO2->GTPE2_LOGIC_OUTS_B16_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX35_0->GTPE2_CHANNEL_TXSEQUENCE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT8->GTPE2_LOGIC_OUTS_B13_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_8" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXN_PAD->GTPE2_CHANNEL_RXN": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXN_PAD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXN" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISK0->GTPE2_LOGIC_OUTS_B12_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_10" + }, + "GTP_CHANNEL_3.GTPE2_CTRL0_9->GTPE2_CHANNEL_RXLPMRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMRESET" + }, + "GTP_CHANNEL_3.GTPE2_IMUX9_10->GTPE2_CHANNEL_PCSRSVDIN15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN15" + }, + "GTP_CHANNEL_3.GTPE2_IMUX2_10->GTPE2_CHANNEL_RXOUTCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL2" + }, + "GTP_CHANNEL_3.GTPE2_CTRL1_10->GTPE2_CHANNEL_RXOOBRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOOBRESET" + }, + "GTP_CHANNEL_3.GTPE2_CLK1_5->GTPE2_CHANNEL_DMONITORCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DMONITORCLK" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT0->GTPE2_LOGIC_OUTS_B5_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_10" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B15_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISK1->GTPE2_LOGIC_OUTS_B12_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX26_5->GTPE2_CHANNEL_GTRSVD10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_0->GTPE2_CHANNEL_RXOSINTPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTPD" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO12->GTPE2_LOGIC_OUTS_B7_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX5_4->GTPE2_CHANNEL_TXMAINCURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA22->GTPE2_LOGIC_OUTS_B1_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX18_9->GTPE2_CHANNEL_RXCHBONDI0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT4->GTPE2_LOGIC_OUTS_B9_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX28_3->GTPE2_CHANNEL_DRPWE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPWE" + }, + "GTP_CHANNEL_3.GTPE2_IMUX41_1->GTPE2_CHANNEL_RXMCOMMAALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXMCOMMAALIGNEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX6_1->GTPE2_CHANNEL_RXGEARBOXSLIP": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXGEARBOXSLIP" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXP_PAD->GTPE2_CHANNEL_RXP": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXP_PAD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXP" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTARTED->GTPE2_LOGIC_OUTS_B6_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTARTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX11_5->GTPE2_CHANNEL_TXDLYHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYHOLD" + }, + "GTP_CHANNEL_3.GTPE2_CTRL0_10->GTPE2_CHANNEL_GTRESETSEL": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRESETSEL" + }, + "GTP_CHANNEL_3.GTPE2_IMUX26_3->GTPE2_CHANNEL_GTRSVD8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX5_8->GTPE2_CHANNEL_TXOUTCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_3->GTPE2_CHANNEL_TXSTARTSEQ": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSTARTSEQ" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA17->GTPE2_LOGIC_OUTS_B2_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX43_9->GTPE2_CHANNEL_LOOPBACK0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX21_4->GTPE2_CHANNEL_TXDATA15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA15" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA27->GTPE2_LOGIC_OUTS_B0_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_2->GTPE2_CHANNEL_TSTIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA5->GTPE2_LOGIC_OUTS_B7_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_9" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA1->GTPE2_LOGIC_OUTS_B2_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX14_5->GTPE2_CHANNEL_TXDLYEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX1_9->GTPE2_CHANNEL_RXOSINTHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTHOLD" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT5->GTPE2_LOGIC_OUTS_B13_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_5" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTATUS2->GTPE2_LOGIC_OUTS_B23_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_8" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT7->GTPE2_LOGIC_OUTS_B9_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX11_10->GTPE2_CHANNEL_RXOSINTID03": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID03" + }, + "GTP_CHANNEL_3.GTPE2_CLK0_7->GTPE2_CHANNEL_RXUSRCLK2": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSRCLK2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT4->GTPE2_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR0->GTPE2_LOGIC_OUTS_B13_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX2_7->GTPE2_CHANNEL_RXRATEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATEMODE" + }, + "GTP_CHANNEL_3.GTPE2_IMUX30_3->GTPE2_CHANNEL_TXPOLARITY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOLARITY" + }, + "GTP_CHANNEL_3.GTPE2_IMUX22_5->GTPE2_CHANNEL_TXDATA10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_0->GTPE2_CHANNEL_TXSEQUENCE6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX14_10->GTPE2_CHANNEL_RXPHOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHOVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX10_10->GTPE2_CHANNEL_RXOSINTID02": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID02" + }, + "GTP_CHANNEL_3.GTPE2_IMUX9_5->GTPE2_CHANNEL_PCSRSVDIN10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX39_5->GTPE2_CHANNEL_TXDETECTRX": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDETECTRX" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_4->GTPE2_CHANNEL_TXCHARDISPVAL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX24_7->GTPE2_CHANNEL_TSTIN16": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN16" + }, + "GTP_CHANNEL_3.GTPE2_IMUX27_7->GTPE2_CHANNEL_RXPOLARITY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPOLARITY" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_7->GTPE2_CHANNEL_TSTIN6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXHEADER2->GTPE2_LOGIC_OUTS_B17_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR3->GTPE2_LOGIC_OUTS_B6_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX32_6->GTPE2_CHANNEL_DRPDI3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX22_3->GTPE2_CHANNEL_TXDATA18": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA18" + }, + "GTP_CHANNEL_3.GTPE2_CTRL1_4->GTPE2_CHANNEL_RXPHDLYRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHDLYRESET" + }, + "GTP_CHANNEL_3.GTPE2_IMUX4_10->GTPE2_CHANNEL_RXOUTCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLKSEL0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX46_0->GTPE2_CHANNEL_TXPCSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPCSRESET" + }, + "GTP_CHANNEL_3.GTPE2_IMUX11_6->GTPE2_CHANNEL_RXRATE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_6->GTPE2_CHANNEL_TXCHARDISPVAL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPVAL0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO5->GTPE2_LOGIC_OUTS_B12_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX44_10->GTPE2_CHANNEL_TXDATA26": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA26" + }, + "GTP_CHANNEL_3.GTPE2_IMUX25_6->GTPE2_CHANNEL_PCSRSVDIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_3->GTPE2_CHANNEL_TXPIPPMSEL": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSEL" + }, + "GTP_CHANNEL_3.GTPE2_IMUX39_6->GTPE2_CHANNEL_TXELECIDLE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXELECIDLE" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT6->GTPE2_LOGIC_OUTS_B13_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX44_2->GTPE2_CHANNEL_TXSYNCALLIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCALLIN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_10->GTPE2_CHANNEL_RXLPMLFOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMLFOVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX25_9->GTPE2_CHANNEL_PCSRSVDIN6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PLLCLK0->GTPE2_CHANNEL_PLL0CLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL0CLK" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATAVALID0->GTPE2_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATAVALID0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX19_5->GTPE2_CHANNEL_TXDATA9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA9" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHALIGNDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX28_6->GTPE2_CHANNEL_RXDLYEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYEN" + }, + "GTP_CHANNEL_3.GTPE2_CTRL1_8->GTPE2_CHANNEL_RXCDRRESETRSV": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRRESETRSV" + }, + "GTP_CHANNEL_3.GTPE2_IMUX23_7->GTPE2_CHANNEL_TXDATA3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBYTEISALIGNED->GTPE2_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBYTEISALIGNED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PHYSTATUS->GTPE2_LOGIC_OUTS_B10_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PHYSTATUS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX32_2->GTPE2_CHANNEL_TXINHIBIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXINHIBIT" + }, + "GTP_CHANNEL_3.GTPE2_IMUX0_3->GTPE2_CHANNEL_TXMAINCURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX10_6->GTPE2_CHANNEL_DRPDI1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA0->GTPE2_LOGIC_OUTS_B6_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_10" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISCOMMA1->GTPE2_LOGIC_OUTS_B15_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX2_5->GTPE2_CHANNEL_TXDIFFCTRL3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTATUS1->GTPE2_LOGIC_OUTS_B17_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX16_0->GTPE2_CHANNEL_TXSEQUENCE5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX12_7->GTPE2_CHANNEL_TXBUFDIFFCTRL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTDONE->GTPE2_LOGIC_OUTS_B3_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_8->GTPE2_CHANNEL_TSTIN7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX10_9->GTPE2_CHANNEL_PMARSVDIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX29_10->GTPE2_CHANNEL_TXDATA27": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA27" + }, + "GTP_CHANNEL_3.GTPE2_IMUX19_3->GTPE2_CHANNEL_TXDATA17": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA17" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_GTTXOUTCLK_3->GTPE2_CHANNEL_TXOUTCLK_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_GTTXOUTCLK_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLK_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX1_4->GTPE2_CHANNEL_TXMAINCURSOR6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX34_2->GTPE2_CHANNEL_DRPADDR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX30_7->GTPE2_CHANNEL_RXPD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPD0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA16->GTPE2_LOGIC_OUTS_B6_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX5_9->GTPE2_CHANNEL_RXOSINTTESTOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX17_6->GTPE2_CHANNEL_TXDATA5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX41_5->GTPE2_CHANNEL_RESETOVRD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RESETOVRD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX20_2->GTPE2_CHANNEL_TXDATA22": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA22" + }, + "GTP_CHANNEL_3.GTPE2_IMUX24_3->GTPE2_CHANNEL_TSTIN12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN12" + }, + "GTP_CHANNEL_3.GTPE2_IMUX15_9->GTPE2_CHANNEL_RXOSINTEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX4_8->GTPE2_CHANNEL_TXOUTCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT9->GTPE2_LOGIC_OUTS_B21_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFSTATUS1->GTPE2_LOGIC_OUTS_B19_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX4_7->GTPE2_CHANNEL_RXADAPTSELTEST2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMSASDET->GTPE2_LOGIC_OUTS_B18_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMSASDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR3->GTPE2_LOGIC_OUTS_B3_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_2" + }, + "GTP_CHANNEL_3.GTPE2_CLK1_2->GTPE2_CHANNEL_TXPHDLYTSTCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYTSTCLK" + }, + "GTP_CHANNEL_3.GTPE2_IMUX32_5->GTPE2_CHANNEL_DRPDI11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI11" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR1->GTPE2_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX37_7->GTPE2_CHANNEL_PMARSVDIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR2->GTPE2_LOGIC_OUTS_B7_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX6_4->GTPE2_CHANNEL_TXPOSTCURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA13->GTPE2_LOGIC_OUTS_B7_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_7" + }, + "GTP_CHANNEL_3.GTPE2_CTRL1_6->GTPE2_CHANNEL_RXBUFRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXBUFRESET" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT9->GTPE2_LOGIC_OUTS_B13_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX12_3->GTPE2_CHANNEL_TXCHARDISPMODE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX12_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX13_6->GTPE2_CHANNEL_DRPDI2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX4_3->GTPE2_CHANNEL_TXMAINCURSOR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_7->GTPE2_CHANNEL_TXPRECURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDISPERR0->GTPE2_LOGIC_OUTS_B22_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_10" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO8->GTPE2_LOGIC_OUTS_B12_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_9" + }, + "GTP_CHANNEL_3.GTPE2_CTRL1_3->GTPE2_CHANNEL_TXPMARESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPMARESET" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDISPERR1->GTPE2_LOGIC_OUTS_B22_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_8" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMINITDET->GTPE2_LOGIC_OUTS_B20_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMINITDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTARTOFSEQ1->GTPE2_LOGIC_OUTS_B11_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX30_6->GTPE2_CHANNEL_TXPOSTCURSORINV": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSORINV" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA4->GTPE2_LOGIC_OUTS_B3_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_9" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDISPERR2->GTPE2_LOGIC_OUTS_B22_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOUTCLKFABRIC->GTPE2_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_0" + }, + "GTP_CHANNEL_3.GTPE2_CLK1_4->GTPE2_CHANNEL_SIGVALIDCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_SIGVALIDCLK" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT2->GTPE2_LOGIC_OUTS_B13_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_7->GTPE2_CHANNEL_GTRSVD4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTARTOFSEQ0->GTPE2_LOGIC_OUTS_B18_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX9_9->GTPE2_CHANNEL_PCSRSVDIN14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN14" + }, + "GTP_CHANNEL_3.GTPE2_IMUX20_4->GTPE2_CHANNEL_TXDATA14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA14" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B7_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PMARSVDOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX1_3->GTPE2_CHANNEL_TXMAINCURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR2" + }, + "GTP_CHANNEL_3.GTPE2_CTRL0_7->GTPE2_CHANNEL_RXCDRFREQRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRFREQRESET" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT11->GTPE2_LOGIC_OUTS_B21_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATAVALID1->GTPE2_LOGIC_OUTS_B5_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATAVALID1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX23_5->GTPE2_CHANNEL_TXDATA11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA11" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCDONE->GTPE2_LOGIC_OUTS_B14_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSYNCDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX44_1->GTPE2_CHANNEL_DMONFIFORESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DMONFIFORESET" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_3->GTPE2_CHANNEL_TSTIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX13_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX38_10->GTPE2_CHANNEL_RXOSINTCFG0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX1_8->GTPE2_CHANNEL_TXOUTCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXOUTCLKSEL2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX24_9->GTPE2_CHANNEL_TSTIN18": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN18" + }, + "GTP_CHANNEL_3.GTPE2_IMUX22_9->GTPE2_CHANNEL_RXCHBONDI2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX25_5->GTPE2_CHANNEL_PCSRSVDIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX28_4->GTPE2_CHANNEL_TXSYSCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX16_6->GTPE2_CHANNEL_TXDATA4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX4_4->GTPE2_CHANNEL_TXMAINCURSOR5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX17_10->GTPE2_CHANNEL_DRPDI14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI14" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBYTEREALIGN->GTPE2_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBYTEREALIGN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX0_9->GTPE2_CHANNEL_RXOSINTOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTOVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX23_8->GTPE2_CHANNEL_RXPRBSSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHMONITOR0->GTPE2_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHMONITOR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_0" }, "GTP_CHANNEL_3.GTPE2_IMUX25_3->GTPE2_CHANNEL_PCSRSVDIN0": { "can_invert": "0", - "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN0", - "is_directional": "1", "src_wire": "GTPE2_IMUX25_3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX13_7->GTPE2_CHANNEL_TXBUFDIFFCTRL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXBUFDIFFCTRL1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_9->GTPE2_CHANNEL_GTRSVD6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B15_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PMARSVDOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX41_10->GTPE2_CHANNEL_TXDATA25": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA25" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT1->GTPE2_LOGIC_OUTS_B9_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX44_5->GTPE2_CHANNEL_TXDLYBYPASS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDLYBYPASS" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT12->GTPE2_LOGIC_OUTS_B7_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXNOTINTABLE2->GTPE2_LOGIC_OUTS_B14_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSYNCOUT->GTPE2_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSYNCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_GTRXOUTCLK_3->GTPE2_CHANNEL_RXOUTCLK_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_GTRXOUTCLK_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOUTCLK_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX0_10->GTPE2_CHANNEL_RXELECIDLEMODE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXELECIDLEMODE0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX30_8->GTPE2_CHANNEL_RXCDRHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRHOLD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX36_5->GTPE2_CHANNEL_TXPHDLYRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYRESET" + }, + "GTP_CHANNEL_3.GTPE2_IMUX35_2->GTPE2_CHANNEL_DRPADDR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX6_0->GTPE2_CHANNEL_RXUSERRDY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSERRDY" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXHEADER0->GTPE2_LOGIC_OUTS_B19_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_0->GTPE2_CHANNEL_TXPIPPMEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX35_4->GTPE2_CHANNEL_TXMARGIN2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_4->GTPE2_CHANNEL_TXPOSTCURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX46_2->GTPE2_CHANNEL_RXOSCALRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSCALRESET" + }, + "GTP_CHANNEL_3.GTPE2_IMUX2_4->GTPE2_CHANNEL_TXPOSTCURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_6->GTPE2_CHANNEL_TXPRECURSOR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX45_6->GTPE2_CHANNEL_DRPDI0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXN->GTPE2_CHANNEL_TXN_PAD": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXN_PAD" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXNOTINTABLE1->GTPE2_LOGIC_OUTS_B14_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX14_1->GTPE2_CHANNEL_TXPRBSFORCEERR": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSFORCEERR" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO4->GTPE2_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_4->GTPE2_CHANNEL_TSTIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA15->GTPE2_LOGIC_OUTS_B5_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA7->GTPE2_LOGIC_OUTS_B5_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX14_8->GTPE2_CHANNEL_RXCDROVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDROVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT13->GTPE2_LOGIC_OUTS_B1_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCDONE->GTPE2_LOGIC_OUTS_B22_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXSYNCDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_9" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO0->GTPE2_LOGIC_OUTS_B12_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA3->GTPE2_LOGIC_OUTS_B0_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX20_1->GTPE2_CHANNEL_TXDATA30": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA30" + }, + "GTP_CHANNEL_3.GTPE2_IMUX39_2->GTPE2_CHANNEL_DRPADDR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX6_8->GTPE2_CHANNEL_TXPRBSSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRBSSEL1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDO3->GTPE2_LOGIC_OUTS_B16_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA28->GTPE2_LOGIC_OUTS_B3_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX17_8->GTPE2_CHANNEL_RXADAPTSELTEST11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST11" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT7->GTPE2_LOGIC_OUTS_B13_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX5_5->GTPE2_CHANNEL_RXLPMLFHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMLFHOLD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_1->GTPE2_CHANNEL_RXSLIDE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSLIDE" + }, + "GTP_CHANNEL_3.GTPE2_IMUX11_7->GTPE2_CHANNEL_RXADAPTSELTEST9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX27_10->GTPE2_CHANNEL_RXLPMHFOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMHFOVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX46_10->GTPE2_CHANNEL_RXOSINTCFG3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTCFG3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXCOMFINISH->GTPE2_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXCOMFINISH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX13_10->GTPE2_CHANNEL_RXPRBSCNTRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSCNTRESET" + }, + "GTP_CHANNEL_3.GTPE2_IMUX14_9->GTPE2_CHANNEL_RXPHALIGN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHALIGN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_2->GTPE2_CHANNEL_RXLPMOSINTNTRLEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX36_8->GTPE2_CHANNEL_RXADAPTSELTEST12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST12" + }, + "GTP_CHANNEL_3.GTPE2_IMUX46_1->GTPE2_CHANNEL_RXPCSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPCSRESET" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXSYNCOUT->GTPE2_LOGIC_OUTS_B14_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXSYNCOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX26_4->GTPE2_CHANNEL_GTRSVD9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX18_3->GTPE2_CHANNEL_TXDATA16": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA16" + }, + "GTP_CHANNEL_3.GTPE2_CTRL1_5->GTPE2_CHANNEL_CFGRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CFGRESET" + }, + "GTP_CHANNEL_3.GTPE2_IMUX47_9->GTPE2_CHANNEL_LOOPBACK2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX2_1->GTPE2_CHANNEL_TXCOMINIT": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMINIT" + }, + "GTP_CHANNEL_3.GTPE2_CLK0_4->GTPE2_CHANNEL_TXUSRCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSRCLK" + }, + "GTP_CHANNEL_3.GTPE2_IMUX31_8->GTPE2_CHANNEL_EYESCANTRIGGER": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANTRIGGER" + }, + "GTP_CHANNEL_3.GTPE2_IMUX16_10->GTPE2_CHANNEL_DRPDI15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI15" + }, + "GTP_CHANNEL_3.GTPE2_IMUX25_8->GTPE2_CHANNEL_PCSRSVDIN5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX31_4->GTPE2_CHANNEL_TX8B10BBYPASS3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_9->GTPE2_CHANNEL_DRPDI4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX25_4->GTPE2_CHANNEL_PCSRSVDIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX35_3->GTPE2_CHANNEL_DRPADDR6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX39_3->GTPE2_CHANNEL_DRPADDR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX36_2->GTPE2_CHANNEL_RXSYNCALLIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCALLIN" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT6->GTPE2_LOGIC_OUTS_B9_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_1->GTPE2_CHANNEL_RXPCOMMAALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPCOMMAALIGNEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX36_7->GTPE2_CHANNEL_RXOSINTNTRLEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTNTRLEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX15_3->GTPE2_CHANNEL_TX8B10BBYPASS2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX2_0->GTPE2_CHANNEL_EYESCANMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_EYESCANMODE" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_2->GTPE2_CHANNEL_PMARSVDIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX45_0->GTPE2_CHANNEL_RXDFEXYDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDFEXYDEN" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA8->GTPE2_LOGIC_OUTS_B6_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_8" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT0->GTPE2_LOGIC_OUTS_B9_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_10" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA25->GTPE2_LOGIC_OUTS_B2_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B2_4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT8->GTPE2_LOGIC_OUTS_B21_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX39_4->GTPE2_CHANNEL_TXMARGIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX39_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX32_9->GTPE2_CHANNEL_RXOSINTSTROBE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTSTROBE" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXHEADER1->GTPE2_LOGIC_OUTS_B23_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXHEADER1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX17_1->GTPE2_CHANNEL_TXDATA29": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA29" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDO1->GTPE2_LOGIC_OUTS_B16_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_0->GTPE2_CHANNEL_RXSYNCMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCMODE" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT10->GTPE2_LOGIC_OUTS_B21_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX46_9->GTPE2_CHANNEL_LOOPBACK1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_LOOPBACK1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX23_9->GTPE2_CHANNEL_RXCHBONDI3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX23_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDI3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX30_9->GTPE2_CHANNEL_RXCHBONDMASTER": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDMASTER" + }, + "GTP_CHANNEL_3.GTPE2_IMUX0_7->GTPE2_CHANNEL_RXADAPTSELTEST0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA29->GTPE2_LOGIC_OUTS_B7_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX35_5->GTPE2_CHANNEL_TXDEEMPH": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDEEMPH" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXBUFSTATUS0->GTPE2_LOGIC_OUTS_B23_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXBUFSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_10" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXOUTCLKPCS->GTPE2_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXOUTCLKPCS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX31_0->GTPE2_CHANNEL_TXUSERRDY": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSERRDY" + }, + "GTP_CHANNEL_3.GTPE2_CTRL1_7->GTPE2_CHANNEL_RXPMARESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPMARESET" + }, + "GTP_CHANNEL_3.GTPE2_CTRL0_6->GTPE2_CHANNEL_RXDLYSRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYSRESET" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISCOMMA0->GTPE2_LOGIC_OUTS_B15_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX29_2->GTPE2_CHANNEL_TXCHARDISPMODE2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHINITDONE->GTPE2_LOGIC_OUTS_B1_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPHINITDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX46_6->GTPE2_CHANNEL_TXRATE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX46_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT11->GTPE2_LOGIC_OUTS_B5_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_8" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA14->GTPE2_LOGIC_OUTS_B1_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX4_0->GTPE2_CHANNEL_RXCHBONDLEVEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCHBONDLEVEL1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX45_2->GTPE2_CHANNEL_RXSYSCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPRDY->GTPE2_LOGIC_OUTS_B14_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_5" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXRATEDONE->GTPE2_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXRATEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX5_7->GTPE2_CHANNEL_RXADAPTSELTEST3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA30->GTPE2_LOGIC_OUTS_B1_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT14->GTPE2_LOGIC_OUTS_B5_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO9->GTPE2_LOGIC_OUTS_B4_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX43_10->GTPE2_CHANNEL_RXLPMHFHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX43_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXLPMHFHOLD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX9_4->GTPE2_CHANNEL_PCSRSVDIN9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_10->GTPE2_CHANNEL_TXDATA24": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA24" + }, + "GTP_CHANNEL_3.GTPE2_IMUX16_4->GTPE2_CHANNEL_TXDATA12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA12" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_0->GTPE2_CHANNEL_RXSYNCIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYNCIN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX24_5->GTPE2_CHANNEL_TSTIN14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN14" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO14->GTPE2_LOGIC_OUTS_B12_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX15_5->GTPE2_CHANNEL_TX8B10BBYPASS1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BBYPASS1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX1_7->GTPE2_CHANNEL_RXADAPTSELTEST1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_5->GTPE2_CHANNEL_TSTIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX5_2->GTPE2_CHANNEL_PMARSVDIN3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX22_7->GTPE2_CHANNEL_TXDATA2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA21->GTPE2_LOGIC_OUTS_B7_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B7_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX20_6->GTPE2_CHANNEL_TXDATA6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA6" + }, + "GTP_CHANNEL_3.GTPE2_IMUX24_10->GTPE2_CHANNEL_TSTIN19": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN19" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_1->GTPE2_CHANNEL_TXSYNCIN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCIN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX13_8->GTPE2_CHANNEL_RXOSOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSOVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX26_6->GTPE2_CHANNEL_GTRSVD11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD11" + }, + "GTP_CHANNEL_3.GTPE2_CLK0_5->GTPE2_CHANNEL_TXUSRCLK2": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXUSRCLK2" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR1->GTPE2_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX9_3->GTPE2_CHANNEL_PCSRSVDIN8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX9_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX41_6->GTPE2_CHANNEL_RXPHALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPHALIGNEN" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISCOMMA3->GTPE2_LOGIC_OUTS_B15_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISCOMMA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX0_2->GTPE2_CHANNEL_TX8B10BEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TX8B10BEN" + }, + "GTP_CHANNEL_3.GTPE2_CTRL1_9->GTPE2_CHANNEL_RXCDRRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXCDRRESET" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXBUFSTATUS1->GTPE2_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXBUFSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISK3->GTPE2_LOGIC_OUTS_B12_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX38_8->GTPE2_CHANNEL_RXPRBSSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPRBSSEL1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX17_4->GTPE2_CHANNEL_TXDATA13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA13" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDLYSRESETDONE->GTPE2_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDLYSRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO11->GTPE2_LOGIC_OUTS_B1_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_8->GTPE2_CHANNEL_GTRSVD5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX44_0->GTPE2_CHANNEL_TXPHOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHOVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX21_8->GTPE2_CHANNEL_RXADAPTSELTEST13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST13" + }, + "GTP_CHANNEL_3.GTPE2_IMUX28_10->GTPE2_CHANNEL_RXOSINTID01": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID01" + }, + "GTP_CHANNEL_3.GTPE2_IMUX19_7->GTPE2_CHANNEL_TXDATA1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX19_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX28_5->GTPE2_CHANNEL_TXSYSCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYSCLKSEL0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX45_7->GTPE2_CHANNEL_TXPISOPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPISOPD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX11_3->GTPE2_CHANNEL_TXRATEMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX11_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATEMODE" + }, + "GTP_CHANNEL_3.GTPE2_IMUX22_6->GTPE2_CHANNEL_TXPIPPMSTEPSIZE4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX44_3->GTPE2_CHANNEL_DRPEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX44_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_9->GTPE2_CHANNEL_TSTIN8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX38_3->GTPE2_CHANNEL_DRPADDR5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX26_8->GTPE2_CHANNEL_GTRSVD13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD13" + }, + "GTP_CHANNEL_3.GTPE2_IMUX31_7->GTPE2_CHANNEL_TXCHARISK0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_5->GTPE2_CHANNEL_GTRSVD2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX13_0->GTPE2_CHANNEL_TXSYNCMODE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSYNCMODE" + }, + "GTP_CHANNEL_3.GTPE2_IMUX21_1->GTPE2_CHANNEL_TXDATA31": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA31" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHANBONDSEQ->GTPE2_LOGIC_OUTS_B8_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANBONDSEQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX29_6->GTPE2_CHANNEL_TXCHARDISPMODE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARDISPMODE0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXNOTINTABLE3->GTPE2_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA26->GTPE2_LOGIC_OUTS_B4_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_1->GTPE2_CHANNEL_TXCOMWAKE": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMWAKE" + }, + "GTP_CHANNEL_3.GTPE2_IMUX29_7->GTPE2_CHANNEL_RXADAPTSELTEST8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_5->GTPE2_CHANNEL_TXDIFFCTRL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_2->GTPE2_CHANNEL_RXSYSCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXSYSCLKSEL1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA6->GTPE2_LOGIC_OUTS_B1_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B1_9" + }, + "GTP_CHANNEL_3.GTPE2_CLK1_7->GTPE2_CHANNEL_CLKRSVD0": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_CLKRSVD0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX2_6->GTPE2_CHANNEL_TXPRECURSOR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPRECURSOR3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DRPDO2->GTPE2_LOGIC_OUTS_B4_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DRPDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B4_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX34_3->GTPE2_CHANNEL_DRPADDR7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXGEARBOXREADY->GTPE2_LOGIC_OUTS_B23_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXGEARBOXREADY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX32_8->GTPE2_CHANNEL_RXDLYBYPASS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYBYPASS" + }, + "GTP_CHANNEL_3.GTPE2_IMUX47_6->GTPE2_CHANNEL_TXRATE0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX47_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXRATE0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT3->GTPE2_LOGIC_OUTS_B9_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPRBSERR->GTPE2_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPRBSERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_6->GTPE2_CHANNEL_TSTIN5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN5" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA31->GTPE2_LOGIC_OUTS_B5_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX18_7->GTPE2_CHANNEL_TXDATA0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX18_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX29_8->GTPE2_CHANNEL_RXOSHOLD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX29_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSHOLD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX40_10->GTPE2_CHANNEL_TSTIN9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN9" + }, + "GTP_CHANNEL_3.GTPE2_IMUX37_8->GTPE2_CHANNEL_PMARSVDIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PMARSVDIN0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX31_5->GTPE2_CHANNEL_TXCHARISK1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX31_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCHARISK1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX2_3->GTPE2_CHANNEL_DRPADDR8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPADDR8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX5_3->GTPE2_CHANNEL_TXMAINCURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMAINCURSOR0" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT15->GTPE2_LOGIC_OUTS_B15_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B15_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX24_4->GTPE2_CHANNEL_TSTIN13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN13" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_5->GTPE2_CHANNEL_TXDIFFCTRL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFCTRL2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX37_3->GTPE2_CHANNEL_TXPHDLYPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHDLYPD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX25_7->GTPE2_CHANNEL_PCSRSVDIN4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PCSRSVDIN4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDISPERR3->GTPE2_LOGIC_OUTS_B22_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDISPERR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B22_4" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PLLREFCLK1->GTPE2_CHANNEL_PLL1REFCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLREFCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL1REFCLK" + }, + "GTP_CHANNEL_3.GTPE2_IMUX34_6->GTPE2_CHANNEL_DRPDI8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI8" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA12->GTPE2_LOGIC_OUTS_B3_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHARISK2->GTPE2_LOGIC_OUTS_B12_6": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHARISK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXPMARESETDONE->GTPE2_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPMARESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_2" + }, + "GTP_CHANNEL_3.GTPE2_IMUX33_2->GTPE2_CHANNEL_TXPHALIGNEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX33_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHALIGNEN" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT10->GTPE2_LOGIC_OUTS_B13_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_10" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXSTATUS0->GTPE2_LOGIC_OUTS_B21_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B21_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX35_8->GTPE2_CHANNEL_TXPIPPMSTEPSIZE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHANISALIGNED->GTPE2_LOGIC_OUTS_B18_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHANISALIGNED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_9" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXPHSLIPMONITOR4->GTPE2_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX38_4->GTPE2_CHANNEL_TXMARGIN1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXMARGIN1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX34_7->GTPE2_CHANNEL_RXADAPTSELTEST4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX34_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX26_7->GTPE2_CHANNEL_GTRSVD12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX26_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD12" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXRATEDONE->GTPE2_LOGIC_OUTS_B23_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXRATEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B23_5" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA23->GTPE2_LOGIC_OUTS_B5_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B5_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX6_7->GTPE2_CHANNEL_RXADAPTSELTEST5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX6_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX45_4->GTPE2_CHANNEL_TSTIN0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_4->GTPE2_CHANNEL_GTRSVD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX3_9->GTPE2_CHANNEL_DRPDI7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI7" + }, + "GTP_CHANNEL_3.GTPE2_IMUX41_0->GTPE2_CHANNEL_RXDLYOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDLYOVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX41_7->GTPE2_CHANNEL_RXADAPTSELTEST6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST6" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT2->GTPE2_LOGIC_OUTS_B9_8": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_8" + }, + "GTP_CHANNEL_3.GTPE2_IMUX10_3->GTPE2_CHANNEL_TXPIPPMOVRDEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX10_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMOVRDEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX37_10->GTPE2_CHANNEL_DRPDI12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI12" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXP->GTPE2_CHANNEL_TXP_PAD": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXP_PAD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX25_2->GTPE2_CHANNEL_TXPHALIGN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX25_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPHALIGN" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXVALID->GTPE2_LOGIC_OUTS_B20_9": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXVALID", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_9" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_TXPHALIGNDONE->GTPE2_LOGIC_OUTS_B18_3": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_TXPHALIGNDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_3" + }, + "GTP_CHANNEL_3.GTPE2_IMUX35_6->GTPE2_CHANNEL_TXPD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPD1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PLLREFCLK0->GTPE2_CHANNEL_PLL0REFCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PLLREFCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_PLL0REFCLK" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_PCSRSVDOUT1->GTPE2_LOGIC_OUTS_B0_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_PCSRSVDOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX14_6->GTPE2_CHANNEL_RXRATE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXRATE1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX16_2->GTPE2_CHANNEL_TXDATA20": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX16_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA20" + }, + "GTP_CHANNEL_3.GTPE2_IMUX36_10->GTPE2_CHANNEL_DRPDI13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX36_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI13" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_3->GTPE2_CHANNEL_TXPOSTCURSOR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX0_8->GTPE2_CHANNEL_RXADAPTSELTEST10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXADAPTSELTEST10" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA20->GTPE2_LOGIC_OUTS_B3_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B3_5" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXDATA24->GTPE2_LOGIC_OUTS_B6_4": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXDATA24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B6_4" + }, + "GTP_CHANNEL_3.GTPE2_IMUX8_8->GTPE2_CHANNEL_RXDDIEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX8_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXDDIEN" + }, + "GTP_CHANNEL_3.GTPE2_IMUX41_9->GTPE2_CHANNEL_TXPIPPMSTEPSIZE1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_DMONITOROUT14->GTPE2_LOGIC_OUTS_B10_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_DMONITOROUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_5" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_EYESCANDATAERROR->GTPE2_LOGIC_OUTS_B18_0": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_EYESCANDATAERROR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX24_8->GTPE2_CHANNEL_TSTIN17": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN17" + }, + "GTP_CHANNEL_3.GTPE2_IMUX28_8->GTPE2_CHANNEL_RXPD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX28_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXPD1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX7_4->GTPE2_CHANNEL_TXPOSTCURSOR0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX7_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXPOSTCURSOR0" + }, + "GTP_CHANNEL_3.GTPE2_IMUX21_6->GTPE2_CHANNEL_TXDATA7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX21_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCDRLOCK->GTPE2_LOGIC_OUTS_B17_5": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCDRLOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_5" + }, + "GTP_CHANNEL_3.GTPE2_IMUX27_8->GTPE2_CHANNEL_TXCOMSAS": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXCOMSAS" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCOMWAKEDET->GTPE2_LOGIC_OUTS_B12_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCOMWAKEDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B12_1" + }, + "GTP_CHANNEL_3.GTPE2_IMUX27_0->GTPE2_CHANNEL_TXSEQUENCE3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXSEQUENCE3" + }, + "GTP_CHANNEL_3.GTPE2_CLK0_6->GTPE2_CHANNEL_RXUSRCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXUSRCLK" + }, + "GTP_CHANNEL_3.GTPE2_IMUX38_9->GTPE2_CHANNEL_DRPDI5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPDI5" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXOSINTSTROBESTARTED->GTPE2_LOGIC_OUTS_B0_7": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B0_7" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXNOTINTABLE0->GTPE2_LOGIC_OUTS_B14_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXNOTINTABLE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX24_6->GTPE2_CHANNEL_TSTIN15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TSTIN15" + }, + "GTP_CHANNEL_3.GTPE2_IMUX17_2->GTPE2_CHANNEL_TXDATA21": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX17_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDATA21" + }, + "GTP_CHANNEL_3.GTPE2_IMUX15_10->GTPE2_CHANNEL_RXOSINTID00": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX15_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RXOSINTID00" + }, + "GTP_CHANNEL_3.GTPE2_IMUX37_4->GTPE2_CHANNEL_TXDIFFPD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX37_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_TXDIFFPD" + }, + "GTP_CHANNEL_3.GTPE2_IMUX45_1->GTPE2_CHANNEL_RX8B10BEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_RX8B10BEN" + }, + "GTP_CHANNEL_3.GTPE2_CLK0_9->GTPE2_CHANNEL_DRPCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_DRPCLK" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXCHBONDO0->GTPE2_LOGIC_OUTS_B16_10": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXCHBONDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_10" + }, + "GTP_CHANNEL_3.GTPE2_IMUX42_3->GTPE2_CHANNEL_GTRSVD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRSVD0" + }, + "GTP_CHANNEL_3.GTPE2_CTRL0_8->GTPE2_CHANNEL_GTRXRESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_CHANNEL_GTRXRESET" + }, + "GTP_CHANNEL_3.GTPE2_CHANNEL_RXRESETDONE->GTPE2_LOGIC_OUTS_B18_1": { + "can_invert": "0", + "src_wire": "GTPE2_CHANNEL_RXRESETDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_1" } }, - "tile_type": "GTP_CHANNEL_3" + "wires": [ + "GTPE2_IMUX5_7", + "GTPE2_IMUX14_1", + "GTPE2_BYP0_6", + "GTPE2_IMUX23_2", + "GTPE2_BYP0_5", + "GTPE2_IMUX19_10", + "GTPE2_LOGIC_OUTS_B20_6", + "GTPE2_LOGIC_OUTS_B13_0", + "GTPE2_IMUX25_9", + "GTPE2_IMUX18_8", + "GTPE2_IMUX44_3", + "GTPE2_LOGIC_OUTS_B20_10", + "GTPE2_LOGIC_OUTS_B11_9", + "GTPE2_BYP1_10", + "GTPE2_IMUX26_0", + "GTPE2_LOGIC_OUTS_B19_5", + "GTPE2_IMUX5_2", + "GTPE2_CHANNEL_RXOSINTCFG3", + "GTPE2_IMUX30_3", + "GTPE2_CHANNEL_TXSEQUENCE6", + "GTPE2_LOGIC_OUTS_B9_4", + "GTPE2_IMUX18_1", + "GTPE2_CLK0_4", + "GTPE2_CHANNEL_DMONITOROUT2", + "GTPE2_IMUX42_3", + "GTPE2_CTRL1_5", + "GTPE2_IMUX22_3", + "GTPE2_CHANNEL_GTRSVD5", + "GTPE2_CHANNEL_RXLPMRESET", + "GTPE2_LOGIC_OUTS_B23_8", + "GTPE2_CHANNEL_TXPRBSFORCEERR", + "GTPE2_LOGIC_OUTS_B1_9", + "GTPE2_IMUX45_9", + "GTPE2_IMUX34_7", + "GTPE2_LOGIC_OUTS_B2_0", + "GTPE2_IMUX24_9", + "GTPE2_LOGIC_OUTS_B18_2", + "GTPE2_CLK1_1", + "GTPE2_CHANNEL_RXPOLARITY", + "GTPE2_CHANNEL_TSTIN14", + "GTPE2_LOGIC_OUTS_B22_9", + "GTPE2_CHANNEL_PCSRSVDOUT5", + "GTPE2_LOGIC_OUTS_B8_6", + "GTPE2_IMUX23_4", + "GTPE2_LOGIC_OUTS_B22_10", + "GTPE2_LOGIC_OUTS_B6_9", + "GTPE2_IMUX33_7", + "GTPE2_CHANNEL_RXRATE0", + "GTPE2_FAN5_8", + "GTPE2_IMUX25_3", + "GTPE2_IMUX23_5", + "GTPE2_BYP5_10", + "GTPE2_IMUX19_6", + "GTPE2_CHANNEL_RXP", + "GTPE2_CHANNEL_TXDATA11", + "GTPE2_FAN7_2", + "GTPE2_CHANNEL_TSTPDOVRDB", + "GTPE2_CHANNEL_RXOUTCLKSEL2", + "GTPE2_CHANNEL_RXSYNCALLIN", + "GTPE2_FAN3_3", + "GTPE2_CHANNEL_DRPDO6", + "GTPE2_IMUX2_4", + "GTPE2_IMUX37_6", + "GTPE2_IMUX17_2", + "GTPE2_IMUX6_6", + "GTPE2_CHANNEL_TSTCLK1", + "GTPE2_CHANNEL_TXDATA2", + "GTPE2_IMUX0_2", + "GTPE2_IMUX28_0", + "GTPE2_CHANNEL_RXCLKCORCNT1", + "GTPE2_LOGIC_OUTS_B21_1", + "GTPE2_LOGIC_OUTS_B16_9", + "GTPE2_IMUX33_10", + "GTPE2_IMUX42_4", + "GTPE2_CHANNEL_RXOSINTID01", + "GTPE2_IMUX26_8", + "GTPE2_IMUX0_9", + "GTPE2_BYP5_3", + "GTPE2_IMUX38_1", + "GTPE2_CHANNEL_RXSYNCMODE", + "GTPE2_FAN7_10", + "GTPE2_IMUX22_4", + "GTPE2_IMUX43_1", + "GTPE2_CHANNEL_RXDATA9", + "GTPE2_IMUX9_5", + "GTPE2_BYP1_3", + "GTPE2_CHANNEL_DMONFIFORESET", + "GTPE2_CHANNEL_DMONITOROUT11", + "GTPE2_IMUX16_3", + "GTPE2_CHANNEL_TXSEQUENCE3", + "GTPE2_CHANNEL_RXCHBONDI2", + "GTPE2_IMUX0_4", + "GTPE2_IMUX24_2", + "GTPE2_IMUX3_2", + "GTPE2_LOGIC_OUTS_B6_8", + "GTPE2_LOGIC_OUTS_B4_10", + "GTPE2_CHANNEL_RXSYNCOUT", + "GTPE2_LOGIC_OUTS_B13_10", + "GTPE2_IMUX34_8", + "GTPE2_LOGIC_OUTS_B0_1", + "GTPE2_IMUX40_6", + "GTPE2_IMUX7_0", + "GTPE2_IMUX34_9", + "GTPE2_IMUX26_10", + "GTPE2_IMUX37_7", + "GTPE2_CHANNEL_RXPRBSSEL1", + "GTPE2_IMUX19_1", + "GTPE2_CHANNEL_RXNOTINTABLE1", + "GTPE2_IMUX29_0", + "GTPE2_LOGIC_OUTS_B18_1", + "GTPE2_CHANNEL_PLLREFCLK1", + "GTPE2_IMUX37_0", + "GTPE2_FAN6_8", + "GTPE2_CHANNEL_TXSYNCMODE", + "GTPE2_CHANNEL_RXPHMONITOR4", + "GTPE2_CHANNEL_DRPDI10", + "GTPE2_IMUX20_8", + "GTPE2_LOGIC_OUTS_B5_3", + "GTPE2_LOGIC_OUTS_B9_10", + "GTPE2_CHANNEL_PMASCANIN0", + "GTPE2_CHANNEL_EYESCANTRIGGER", + "GTPE2_BYP0_3", + "GTPE2_FAN6_2", + "GTPE2_CTRL0_3", + "GTPE2_CHANNEL_RXDATA19", + "GTPE2_CTRL1_1", + "GTPE2_CHANNEL_PCSRSVDIN9", + "GTPE2_IMUX17_6", + "GTPE2_CHANNEL_DRPADDR5", + "GTPE2_CHANNEL_TSTIN2", + "GTPE2_IMUX25_10", + "GTPE2_LOGIC_OUTS_B5_9", + "GTPE2_IMUX16_4", + "GTPE2_LOGIC_OUTS_B10_5", + "GTPE2_LOGIC_OUTS_B18_7", + "GTPE2_IMUX11_9", + "GTPE2_CHANNEL_RXDATA4", + "GTPE2_IMUX13_7", + "GTPE2_IMUX9_0", + "GTPE2_LOGIC_OUTS_B14_3", + "GTPE2_CHANNEL_RXDATA2", + "GTPE2_IMUX2_1", + "GTPE2_CHANNEL_RXCHBONDO3", + "GTPE2_IMUX24_10", + "GTPE2_FAN1_1", + "GTPE2_CHANNEL_TXDLYOVRDEN", + "GTPE2_CHANNEL_TXDATA0", + "GTPE2_BYP3_6", + "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "GTPE2_IMUX42_5", + "GTPE2_CHANNEL_PMASCANMODEB", + "GTPE2_BYP0_4", + "GTPE2_LOGIC_OUTS_B12_9", + "GTPE2_CHANNEL_RXDATA25", + "GTPE2_CHANNEL_RXOSCALRESET", + "GTPE2_IMUX10_9", + "GTPE2_CTRL0_6", + "GTPE2_IMUX41_10", + "GTPE2_CLK1_6", + "GTPE2_IMUX8_10", + "GTPE2_IMUX14_3", + "GTPE2_CHANNEL_RXGEARBOXSLIP", + "GTPE2_CHANNEL_GTRSVD2", + "GTPE2_IMUX36_6", + "GTPE2_CHANNEL_TXCOMFINISH", + "GTPE2_CTRL1_10", + "GTPE2_IMUX2_7", + "GTPE2_CHANNEL_PCSRSVDOUT10", + "GTPE2_IMUX13_5", + "GTPE2_CHANNEL_GTRSVD14", + "GTPE2_LOGIC_OUTS_B16_1", + "GTPE2_BYP4_6", + "GTPE2_CHANNEL_RXOSINTHOLD", + "GTPE2_IMUX34_2", + "GTPE2_LOGIC_OUTS_B20_9", + "GTPE2_IMUX22_10", + "GTPE2_IMUX9_9", + "GTPE2_CHANNEL_RXSLIDE", + "GTPE2_CLK1_0", + "GTPE2_IMUX41_2", + "GTPE2_LOGIC_OUTS_B0_7", + "GTPE2_CHANNEL_RXADAPTSELTEST5", + "GTPE2_FAN4_5", + "GTPE2_FAN3_4", + "GTPE2_CHANNEL_RXCHBONDI1", + "GTPE2_CHANNEL_RXRESETDONE", + "GTPE2_CHANNEL_TXCOMSAS", + "GTPE2_IMUX20_4", + "GTPE2_IMUX25_7", + "GTPE2_FAN3_9", + "GTPE2_CHANNEL_RXCHBONDEN", + "GTPE2_IMUX1_9", + "GTPE2_BYP1_8", + "GTPE2_IMUX29_5", + "GTPE2_LOGIC_OUTS_B1_0", + "GTPE2_CHANNEL_TXMAINCURSOR2", + "GTPE2_CTRL1_6", + "GTPE2_IMUX32_4", + "GTPE2_LOGIC_OUTS_B6_2", + "GTPE2_CHANNEL_RXOSINTID02", + "GTPE2_CHANNEL_GTRSVD10", + "GTPE2_BYP4_5", + "GTPE2_IMUX35_6", + "GTPE2_IMUX36_10", + "GTPE2_IMUX31_9", + "GTPE2_IMUX1_7", + "GTPE2_CHANNEL_TXHEADER1", + "GTPE2_IMUX27_6", + "GTPE2_CHANNEL_DMONITOROUT1", + "GTPE2_IMUX26_1", + "GTPE2_IMUX25_4", + "GTPE2_IMUX15_5", + "GTPE2_CHANNEL_PCSRSVDOUT4", + "GTPE2_IMUX30_6", + "GTPE2_BYP3_0", + "GTPE2_CHANNEL_DRPDO0", + "GTPE2_IMUX36_9", + "GTPE2_CHANNEL_DRPDI8", + "GTPE2_IMUX38_7", + "GTPE2_BYP5_2", + "GTPE2_BYP7_0", + "GTPE2_CHANNEL_DRPADDR6", + "GTPE2_LOGIC_OUTS_B7_7", + "GTPE2_LOGIC_OUTS_B13_3", + "GTPE2_LOGIC_OUTS_B2_6", + "GTPE2_CHANNEL_RXOSINTID00", + "GTPE2_FAN0_2", + "GTPE2_CHANNEL_TXUSRCLK", + "GTPE2_CHANNEL_RXPD0", + "GTPE2_IMUX0_7", + "GTPE2_IMUX33_5", + "GTPE2_LOGIC_OUTS_B20_8", + "GTPE2_LOGIC_OUTS_B6_10", + "GTPE2_LOGIC_OUTS_B12_4", + "GTPE2_IMUX16_8", + "GTPE2_CHANNEL_RXDISPERR1", + "GTPE2_LOGIC_OUTS_B3_4", + "GTPE2_CLK1_5", + "GTPE2_CHANNEL_TXDATA19", + "GTPE2_IMUX22_8", + "GTPE2_IMUX30_7", + "GTPE2_FAN6_5", + "GTPE2_CHANNEL_RXPHMONITOR3", + "GTPE2_CHANNEL_TXMAINCURSOR4", + "GTPE2_CHANNEL_PMARSVDIN1", + "GTPE2_BYP3_8", + "GTPE2_CHANNEL_RXBUFSTATUS1", + "GTPE2_CHANNEL_RXHEADER1", + "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "GTPE2_CLK0_1", + "GTPE2_LOGIC_OUTS_B6_7", + "GTPE2_BYP3_4", + "GTPE2_CHANNEL_TXMARGIN2", + "GTPE2_IMUX40_2", + "GTPE2_LOGIC_OUTS_B6_6", + "GTPE2_IMUX26_4", + "GTPE2_CHANNEL_TXPHINIT", + "GTPE2_LOGIC_OUTS_B15_5", + "GTPE2_FAN3_5", + "GTPE2_IMUX11_8", + "GTPE2_FAN0_8", + "GTPE2_IMUX12_3", + "GTPE2_CHANNEL_TXP_PAD", + "GTPE2_IMUX3_0", + "GTPE2_IMUX5_8", + "GTPE2_LOGIC_OUTS_B3_5", + "GTPE2_IMUX34_10", + "GTPE2_IMUX46_2", + "GTPE2_CHANNEL_PLL0CLK", + "GTPE2_CHANNEL_TXCHARDISPVAL2", + "GTPE2_CHANNEL_TXPISOPD", + "GTPE2_CHANNEL_TX8B10BBYPASS3", + "GTPE2_IMUX46_0", + "GTPE2_BYP2_9", + "GTPE2_CHANNEL_TSTIN16", + "GTPE2_CHANNEL_GTRSVD7", + "GTPE2_FAN6_9", + "GTPE2_IMUX3_5", + "GTPE2_LOGIC_OUTS_B15_7", + "GTPE2_IMUX41_4", + "GTPE2_CHANNEL_RXLPMHFHOLD", + "GTPE2_IMUX23_9", + "GTPE2_CHANNEL_PCSRSVDIN5", + "GTPE2_CHANNEL_SCANIN0", + "GTPE2_LOGIC_OUTS_B13_2", + "GTPE2_IMUX8_5", + "GTPE2_IMUX39_0", + "GTPE2_IMUX42_10", + "GTPE2_IMUX14_2", + "GTPE2_CHANNEL_TXDATA24", + "GTPE2_BYP1_6", + "GTPE2_IMUX28_10", + "GTPE2_FAN5_6", + "GTPE2_BYP2_3", + "GTPE2_CHANNEL_RXDATA14", + "GTPE2_IMUX24_6", + "GTPE2_CHANNEL_RXOSINTNTRLEN", + "GTPE2_LOGIC_OUTS_B1_5", + "GTPE2_LOGIC_OUTS_B8_5", + "GTPE2_LOGIC_OUTS_B3_8", + "GTPE2_IMUX9_7", + "GTPE2_IMUX9_1", + "GTPE2_IMUX44_6", + "GTPE2_CHANNEL_TXDATA12", + "GTPE2_LOGIC_OUTS_B23_5", + "GTPE2_CHANNEL_PLLCLK0", + "GTPE2_CHANNEL_TXSEQUENCE0", + "GTPE2_CHANNEL_RXELECIDLE", + "GTPE2_CHANNEL_SIGVALIDCLK", + "GTPE2_CHANNEL_TXSEQUENCE2", + "GTPE2_FAN4_7", + "GTPE2_IMUX46_4", + "GTPE2_LOGIC_OUTS_B20_1", + "GTPE2_CHANNEL_RXOSINTCFG2", + "GTPE2_LOGIC_OUTS_B19_7", + "GTPE2_IMUX22_7", + "GTPE2_LOGIC_OUTS_B2_9", + "GTPE2_IMUX31_4", + "GTPE2_IMUX8_4", + "GTPE2_IMUX26_2", + "GTPE2_FAN1_10", + "GTPE2_LOGIC_OUTS_B18_0", + "GTPE2_CHANNEL_TXRATEMODE", + "GTPE2_CHANNEL_RXOSINTCFG1", + "GTPE2_CLK1_4", + "GTPE2_IMUX2_3", + "GTPE2_CHANNEL_RXSYSCLKSEL0", + "GTPE2_CHANNEL_TXCHARISK3", + "GTPE2_LOGIC_OUTS_B4_0", + "GTPE2_IMUX7_3", + "GTPE2_IMUX21_1", + "GTPE2_BYP2_8", + "GTPE2_IMUX11_4", + "GTPE2_LOGIC_OUTS_B0_10", + "GTPE2_IMUX27_3", + "GTPE2_FAN0_9", + "GTPE2_CHANNEL_DRPDI12", + "GTPE2_LOGIC_OUTS_B21_5", + "GTPE2_CHANNEL_RXDDIEN", + "GTPE2_FAN7_0", + "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "GTPE2_CHANNEL_PCSRSVDIN8", + "GTPE2_BYP4_7", + "GTPE2_LOGIC_OUTS_B19_6", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", + "GTPE2_CHANNEL_TXSEQUENCE1", + "GTPE2_IMUX29_7", + "GTPE2_LOGIC_OUTS_B10_8", + "GTPE2_LOGIC_OUTS_B20_0", + "GTPE2_IMUX24_8", + "GTPE2_CHANNEL_RXRATEMODE", + "GTPE2_IMUX46_3", + "GTPE2_LOGIC_OUTS_B10_0", + "GTPE2_LOGIC_OUTS_B22_5", + "GTPE2_IMUX37_8", + "GTPE2_FAN7_4", + "GTPE2_IMUX44_0", + "GTPE2_LOGIC_OUTS_B21_8", + "GTPE2_CHANNEL_DRPADDR0", + "GTPE2_CHANNEL_LOOPBACK0", + "GTPE2_CHANNEL_TXPIPPMSEL", + "GTPE2_CHANNEL_PCSRSVDOUT11", + "GTPE2_BYP6_9", + "GTPE2_LOGIC_OUTS_B0_6", + "GTPE2_LOGIC_OUTS_B5_10", + "GTPE2_IMUX38_5", + "GTPE2_LOGIC_OUTS_B1_1", + "GTPE2_IMUX10_10", + "GTPE2_LOGIC_OUTS_B18_9", + "GTPE2_IMUX2_6", + "GTPE2_IMUX45_6", + "GTPE2_CHANNEL_RXBYTEISALIGNED", + "GTPE2_CHANNEL_RXDATA17", + "GTPE2_BYP2_0", + "GTPE2_FAN0_1", + "GTPE2_IMUX28_1", + "GTPE2_CHANNEL_RXUSRCLK2", + "GTPE2_CHANNEL_DRPDO15", + "GTPE2_CHANNEL_RXDATA26", + "GTPE2_IMUX4_7", + "GTPE2_IMUX27_5", + "GTPE2_BYP7_7", + "GTPE2_CHANNEL_TXDATA8", + "GTPE2_IMUX44_2", + "GTPE2_IMUX44_10", + "GTPE2_FAN2_6", + "GTPE2_CHANNEL_TXDATA26", + "GTPE2_CHANNEL_TXPCSRESET", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", + "GTPE2_IMUX35_7", + "GTPE2_IMUX45_7", + "GTPE2_CHANNEL_TXRUNDISP1", + "GTPE2_BYP6_1", + "GTPE2_IMUX16_0", + "GTPE2_IMUX30_9", + "GTPE2_IMUX31_6", + "GTPE2_LOGIC_OUTS_B19_0", + "GTPE2_CHANNEL_RXNOTINTABLE2", + "GTPE2_LOGIC_OUTS_B14_7", + "GTPE2_IMUX8_2", + "GTPE2_LOGIC_OUTS_B21_7", + "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", + "GTPE2_CHANNEL_PCSRSVDOUT12", + "GTPE2_CHANNEL_RXELECIDLEMODE0", + "GTPE2_CHANNEL_RXOUTCLK_2", + "GTPE2_FAN2_7", + "GTPE2_LOGIC_OUTS_B22_6", + "GTPE2_CHANNEL_TXPHOVRDEN", + "GTPE2_CHANNEL_RXUSERRDY", + "GTPE2_CHANNEL_PMASCANIN1", + "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "GTPE2_LOGIC_OUTS_B0_3", + "GTPE2_CHANNEL_RXADAPTSELTEST8", + "GTPE2_LOGIC_OUTS_B20_3", + "GTPE2_IMUX6_1", + "GTPE2_IMUX45_1", + "GTPE2_LOGIC_OUTS_B7_10", + "GTPE2_IMUX16_9", + "GTPE2_LOGIC_OUTS_B9_3", + "GTPE2_LOGIC_OUTS_B10_1", + "GTPE2_CHANNEL_TXPHALIGNEN", + "GTPE2_IMUX1_5", + "GTPE2_FAN0_4", + "GTPE2_LOGIC_OUTS_B17_7", + "GTPE2_CTRL0_1", + "GTPE2_BYP6_3", + "GTPE2_BYP5_1", + "GTPE2_LOGIC_OUTS_B10_6", + "GTPE2_FAN7_7", + "GTPE2_CHANNEL_PLL1REFCLK", + "GTPE2_IMUX18_7", + "GTPE2_BYP2_10", + "GTPE2_CHANNEL_RXCOMSASDET", + "GTPE2_LOGIC_OUTS_B19_4", + "GTPE2_IMUX35_5", + "GTPE2_CHANNEL_PCSRSVDOUT2", + "GTPE2_CHANNEL_TXPOSTCURSOR0", + "GTPE2_CHANNEL_TXPDELECIDLEMODE", + "GTPE2_BYP7_2", + "GTPE2_CHANNEL_DRPDI14", + "GTPE2_CHANNEL_TSTIN0", + "GTPE2_CHANNEL_CLKRSVD1", + "GTPE2_IMUX25_0", + "GTPE2_LOGIC_OUTS_B10_4", + "GTPE2_IMUX33_9", + "GTPE2_CHANNEL_TSTPD1", + "GTPE2_CHANNEL_TSTIN18", + "GTPE2_CHANNEL_TXHEADER0", + "GTPE2_IMUX36_8", + "GTPE2_CHANNEL_GTRSVD9", + "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "GTPE2_FAN3_2", + "GTPE2_CHANNEL_GTRSVD6", + "GTPE2_IMUX27_7", + "GTPE2_CHANNEL_DRPDO13", + "GTPE2_CHANNEL_PMARSVDIN4", + "GTPE2_IMUX36_3", + "GTPE2_IMUX29_10", + "GTPE2_IMUX40_9", + "GTPE2_CHANNEL_EYESCANMODE", + "GTPE2_CHANNEL_RXCDRRESETRSV", + "GTPE2_IMUX44_8", + "GTPE2_CHANNEL_PMASCANOUT4", + "GTPE2_CHANNEL_RXDATA3", + "GTPE2_LOGIC_OUTS_B5_0", + "GTPE2_BYP5_0", + "GTPE2_CHANNEL_TX8B10BBYPASS0", + "GTPE2_LOGIC_OUTS_B15_9", + "GTPE2_IMUX0_0", + "GTPE2_IMUX24_3", + "GTPE2_CHANNEL_PMARSVDIN3", + "GTPE2_LOGIC_OUTS_B4_6", + "GTPE2_CHANNEL_RXDATA0", + "GTPE2_IMUX22_1", + "GTPE2_IMUX38_8", + "GTPE2_FAN3_10", + "GTPE2_CHANNEL_TXCOMINIT", + "GTPE2_IMUX15_10", + "GTPE2_IMUX39_4", + "GTPE2_CHANNEL_RXCLKCORCNT0", + "GTPE2_BYP1_1", + "GTPE2_IMUX31_1", + "GTPE2_IMUX20_0", + "GTPE2_BYP0_8", + "GTPE2_IMUX24_0", + "GTPE2_CHANNEL_TXDIFFCTRL0", + "GTPE2_BYP0_9", + "GTPE2_IMUX21_10", + "GTPE2_CHANNEL_TXSYNCDONE", + "GTPE2_CHANNEL_PMASCANIN2", + "GTPE2_LOGIC_OUTS_B8_4", + "GTPE2_CHANNEL_TSTIN3", + "GTPE2_CHANNEL_TXDATA15", + "GTPE2_IMUX13_8", + "GTPE2_IMUX11_3", + "GTPE2_IMUX27_1", + "GTPE2_LOGIC_OUTS_B1_4", + "GTPE2_CHANNEL_TXSEQUENCE4", + "GTPE2_IMUX44_5", + "GTPE2_CTRL0_2", + "GTPE2_LOGIC_OUTS_B18_8", + "GTPE2_CHANNEL_DMONITOROUT9", + "GTPE2_BYP4_0", + "GTPE2_FAN0_10", + "GTPE2_FAN1_2", + "GTPE2_CHANNEL_RXCOMMADET", + "GTPE2_IMUX22_6", + "GTPE2_BYP4_3", + "GTPE2_IMUX42_7", + "GTPE2_CHANNEL_TXSTARTSEQ", + "GTPE2_LOGIC_OUTS_B11_0", + "GTPE2_IMUX44_7", + "GTPE2_CHANNEL_PCSRSVDIN2", + "GTPE2_IMUX30_0", + "GTPE2_LOGIC_OUTS_B23_10", + "GTPE2_IMUX4_1", + "GTPE2_LOGIC_OUTS_B8_2", + "GTPE2_CHANNEL_RXDISPERR3", + "GTPE2_IMUX46_6", + "GTPE2_CTRL0_5", + "GTPE2_CHANNEL_RXCHARISK3", + "GTPE2_IMUX3_7", + "GTPE2_CHANNEL_DRPDO3", + "GTPE2_IMUX17_0", + "GTPE2_LOGIC_OUTS_B6_4", + "GTPE2_FAN2_10", + "GTPE2_CHANNEL_DRPDI0", + "GTPE2_BYP6_4", + "GTPE2_CLK0_5", + "GTPE2_FAN4_0", + "GTPE2_CHANNEL_SCANIN4", + "GTPE2_IMUX4_2", + "GTPE2_IMUX39_6", + "GTPE2_LOGIC_OUTS_B8_9", + "GTPE2_LOGIC_OUTS_B15_8", + "GTPE2_IMUX23_6", + "GTPE2_IMUX9_6", + "GTPE2_IMUX8_9", + "GTPE2_CTRL1_0", + "GTPE2_CLK1_10", + "GTPE2_CHANNEL_RXCDRLOCK", + "GTPE2_CHANNEL_PCSRSVDOUT6", + "GTPE2_IMUX33_0", + "GTPE2_IMUX30_4", + "GTPE2_IMUX43_8", + "GTPE2_CHANNEL_RXDFEXYDEN", + "GTPE2_IMUX32_3", + "GTPE2_IMUX34_1", + "GTPE2_CLK1_8", + "GTPE2_IMUX5_5", + "GTPE2_IMUX19_3", + "GTPE2_CHANNEL_TXMAINCURSOR1", + "GTPE2_IMUX6_0", + "GTPE2_IMUX41_9", + "GTPE2_LOGIC_OUTS_B17_5", + "GTPE2_IMUX41_3", + "GTPE2_LOGIC_OUTS_B7_6", + "GTPE2_CHANNEL_TXPMARESET", + "GTPE2_FAN1_0", + "GTPE2_LOGIC_OUTS_B17_2", + "GTPE2_CLK0_10", + "GTPE2_LOGIC_OUTS_B1_8", + "GTPE2_FAN7_8", + "GTPE2_CHANNEL_DRPADDR2", + "GTPE2_CHANNEL_DRPCLK", + "GTPE2_IMUX10_0", + "GTPE2_CHANNEL_RXCDROVRDEN", + "GTPE2_BYP0_2", + "GTPE2_LOGIC_OUTS_B15_4", + "GTPE2_IMUX10_7", + "GTPE2_FAN4_10", + "GTPE2_LOGIC_OUTS_B9_9", + "GTPE2_LOGIC_OUTS_B15_2", + "GTPE2_CHANNEL_TXOUTCLKSEL1", + "GTPE2_CHANNEL_TXCHARDISPMODE0", + "GTPE2_IMUX20_10", + "GTPE2_CHANNEL_RXHEADERVALID", + "GTPE2_IMUX15_8", + "GTPE2_CLK0_7", + "GTPE2_CHANNEL_RXOSINTDONE", + "GTPE2_CHANNEL_TXRATE1", + "GTPE2_CHANNEL_TXDATA9", + "GTPE2_LOGIC_OUTS_B17_4", + "GTPE2_IMUX29_1", + "GTPE2_IMUX42_0", + "GTPE2_IMUX39_3", + "GTPE2_IMUX18_3", + "GTPE2_LOGIC_OUTS_B12_1", + "GTPE2_LOGIC_OUTS_B21_6", + "GTPE2_CHANNEL_RXOUTCLK_3", + "GTPE2_IMUX26_3", + "GTPE2_LOGIC_OUTS_B6_5", + "GTPE2_IMUX8_3", + "GTPE2_BYP1_2", + "GTPE2_FAN4_6", + "GTPE2_CHANNEL_GTRXOUTCLK_3", + "GTPE2_CHANNEL_TXDATA17", + "GTPE2_IMUX29_9", + "GTPE2_BYP7_6", + "GTPE2_IMUX27_2", + "GTPE2_CHANNEL_RXDLYSRESETDONE", + "GTPE2_CHANNEL_TXPIPPMPD", + "GTPE2_IMUX39_8", + "GTPE2_CHANNEL_TSTIN11", + "GTPE2_IMUX6_4", + "GTPE2_BYP4_8", + "GTPE2_LOGIC_OUTS_B12_8", + "GTPE2_CHANNEL_TXPRECURSOR2", + "GTPE2_IMUX39_10", + "GTPE2_LOGIC_OUTS_B7_0", + "GTPE2_IMUX21_5", + "GTPE2_IMUX5_0", + "GTPE2_LOGIC_OUTS_B5_5", + "GTPE2_IMUX38_0", + "GTPE2_LOGIC_OUTS_B7_1", + "GTPE2_IMUX18_0", + "GTPE2_CHANNEL_RXPMARESET", + "GTPE2_IMUX29_4", + "GTPE2_CHANNEL_PCSRSVDOUT0", + "GTPE2_FAN4_2", + "GTPE2_IMUX11_2", + "GTPE2_CHANNEL_RXBUFSTATUS2", + "GTPE2_CHANNEL_GTRSVD0", + "GTPE2_CHANNEL_TXUSRCLK2", + "GTPE2_IMUX24_1", + "GTPE2_CHANNEL_SCANOUT5", + "GTPE2_IMUX15_2", + "GTPE2_LOGIC_OUTS_B7_4", + "GTPE2_CHANNEL_TSTIN17", + "GTPE2_CHANNEL_DMONITOROUT13", + "GTPE2_CTRL1_8", + "GTPE2_CHANNEL_RXCHBONDI0", + "GTPE2_LOGIC_OUTS_B20_4", + "GTPE2_CHANNEL_RXOSINTEN", + "GTPE2_CHANNEL_TXRATEDONE", + "GTPE2_CHANNEL_TXPOLARITY", + "GTPE2_IMUX20_2", + "GTPE2_LOGIC_OUTS_B9_0", + "GTPE2_CHANNEL_TXCHARDISPVAL1", + "GTPE2_CHANNEL_TSTIN7", + "GTPE2_LOGIC_OUTS_B20_5", + "GTPE2_LOGIC_OUTS_B23_6", + "GTPE2_IMUX12_2", + "GTPE2_CHANNEL_RXOSINTPD", + "GTPE2_LOGIC_OUTS_B2_2", + "GTPE2_FAN4_1", + "GTPE2_BYP5_4", + "GTPE2_IMUX36_2", + "GTPE2_CHANNEL_TXDATA5", + "GTPE2_CHANNEL_RXDATA24", + "GTPE2_IMUX33_4", + "GTPE2_CHANNEL_RXDATA21", + "GTPE2_BYP3_9", + "GTPE2_CHANNEL_TXPIPPMEN", + "GTPE2_IMUX17_8", + "GTPE2_IMUX23_7", + "GTPE2_FAN6_0", + "GTPE2_LOGIC_OUTS_B12_5", + "GTPE2_CLK1_9", + "GTPE2_CHANNEL_TXDATA4", + "GTPE2_BYP7_3", + "GTPE2_CHANNEL_RESETOVRD", + "GTPE2_IMUX2_5", + "GTPE2_IMUX10_1", + "GTPE2_LOGIC_OUTS_B9_5", + "GTPE2_IMUX36_4", + "GTPE2_IMUX46_10", + "GTPE2_CHANNEL_RXCDRHOLD", + "GTPE2_IMUX47_6", + "GTPE2_CTRL0_9", + "GTPE2_IMUX10_5", + "GTPE2_CHANNEL_DRPDO5", + "GTPE2_CHANNEL_RXADAPTSELTEST6", + "GTPE2_CHANNEL_RXBUFSTATUS0", + "GTPE2_CHANNEL_TXN_PAD", + "GTPE2_CHANNEL_TXSYNCALLIN", + "GTPE2_IMUX27_10", + "GTPE2_IMUX42_8", + "GTPE2_CHANNEL_RXDLYTESTENB", + "GTPE2_CHANNEL_TXOUTCLK_3", + "GTPE2_IMUX46_5", + "GTPE2_LOGIC_OUTS_B17_8", + "GTPE2_LOGIC_OUTS_B8_0", + "GTPE2_IMUX27_8", + "GTPE2_BYP7_9", + "GTPE2_CHANNEL_RXDATA7", + "GTPE2_CHANNEL_SETERRSTATUS", + "GTPE2_CHANNEL_TXSYNCOUT", + "GTPE2_FAN1_5", + "GTPE2_IMUX30_2", + "GTPE2_CHANNEL_DMONITOROUT0", + "GTPE2_CHANNEL_GTRSVD12", + "GTPE2_BYP6_5", + "GTPE2_LOGIC_OUTS_B2_4", + "GTPE2_IMUX7_6", + "GTPE2_BYP0_10", + "GTPE2_LOGIC_OUTS_B21_4", + "GTPE2_CHANNEL_TSTIN1", + "GTPE2_IMUX7_1", + "GTPE2_IMUX42_6", + "GTPE2_CHANNEL_TX8B10BBYPASS1", + "GTPE2_FAN3_1", + "GTPE2_LOGIC_OUTS_B9_7", + "GTPE2_CHANNEL_RXDATA18", + "GTPE2_IMUX41_6", + "GTPE2_CHANNEL_TXDLYTESTENB", + "GTPE2_IMUX27_4", + "GTPE2_IMUX31_8", + "GTPE2_IMUX5_9", + "GTPE2_IMUX12_0", + "GTPE2_IMUX32_7", + "GTPE2_IMUX1_1", + "GTPE2_IMUX25_1", + "GTPE2_CHANNEL_RXCHBONDI3", + "GTPE2_LOGIC_OUTS_B17_10", + "GTPE2_CHANNEL_RXSTATUS2", + "GTPE2_CHANNEL_SCANOUT2", + "GTPE2_LOGIC_OUTS_B9_1", + "GTPE2_LOGIC_OUTS_B11_3", + "GTPE2_IMUX39_1", + "GTPE2_CHANNEL_TXOUTCLK_1", + "GTPE2_IMUX6_2", + "GTPE2_FAN2_3", + "GTPE2_IMUX31_7", + "GTPE2_CHANNEL_RXCHBONDO1", + "GTPE2_CHANNEL_GTRSVD13", + "GTPE2_IMUX18_4", + "GTPE2_IMUX6_5", + "GTPE2_LOGIC_OUTS_B7_3", + "GTPE2_IMUX46_9", + "GTPE2_LOGIC_OUTS_B5_7", + "GTPE2_LOGIC_OUTS_B16_0", + "GTPE2_CHANNEL_DMONITOROUT8", + "GTPE2_CHANNEL_RXADAPTSELTEST11", + "GTPE2_LOGIC_OUTS_B0_8", + "GTPE2_IMUX43_4", + "GTPE2_CHANNEL_DMONITORCLK", + "GTPE2_IMUX35_2", + "GTPE2_LOGIC_OUTS_B22_7", + "GTPE2_IMUX7_4", + "GTPE2_CHANNEL_PLLCLK1", + "GTPE2_CTRL1_4", + "GTPE2_IMUX11_6", + "GTPE2_CHANNEL_CLKRSVD0", + "GTPE2_LOGIC_OUTS_B14_8", + "GTPE2_LOGIC_OUTS_B13_7", + "GTPE2_IMUX45_2", + "GTPE2_CHANNEL_RXCHARISCOMMA1", + "GTPE2_IMUX29_2", + "GTPE2_CHANNEL_PLLREFCLK0", + "GTPE2_IMUX38_6", + "GTPE2_CHANNEL_TXDATA1", + "GTPE2_CHANNEL_RXPHOVRDEN", + "GTPE2_CHANNEL_DMONITOROUT10", + "GTPE2_LOGIC_OUTS_B22_8", + "GTPE2_IMUX21_9", + "GTPE2_FAN4_4", + "GTPE2_CHANNEL_RXOSINTCFG0", + "GTPE2_IMUX1_8", + "GTPE2_IMUX12_8", + "GTPE2_LOGIC_OUTS_B4_3", + "GTPE2_BYP4_9", + "GTPE2_IMUX14_9", + "GTPE2_LOGIC_OUTS_B15_10", + "GTPE2_BYP0_1", + "GTPE2_LOGIC_OUTS_B21_0", + "GTPE2_CHANNEL_RXDATA8", + "GTPE2_IMUX25_6", + "GTPE2_CTRL1_2", + "GTPE2_IMUX40_10", + "GTPE2_CHANNEL_TXOUTCLK_2", + "GTPE2_CHANNEL_TSTPD3", + "GTPE2_IMUX24_7", + "GTPE2_IMUX15_1", + "GTPE2_LOGIC_OUTS_B3_6", + "GTPE2_IMUX35_1", + "GTPE2_CHANNEL_GTRSVD4", + "GTPE2_IMUX4_10", + "GTPE2_CHANNEL_TXDLYEN", + "GTPE2_LOGIC_OUTS_B10_10", + "GTPE2_IMUX9_3", + "GTPE2_CHANNEL_DRPDO2", + "GTPE2_LOGIC_OUTS_B6_3", + "GTPE2_CHANNEL_RXCOMWAKEDET", + "GTPE2_CHANNEL_PMASCANCLK3", + "GTPE2_CHANNEL_RXDATA23", + "GTPE2_CHANNEL_RXADAPTSELTEST0", + "GTPE2_CHANNEL_TXBUFDIFFCTRL0", + "GTPE2_CHANNEL_TXCOMWAKE", + "GTPE2_FAN0_3", + "GTPE2_LOGIC_OUTS_B13_1", + "GTPE2_CHANNEL_SCANIN5", + "GTPE2_LOGIC_OUTS_B4_7", + "GTPE2_CHANNEL_RXSYNCDONE", + "GTPE2_CHANNEL_TXCHARISK0", + "GTPE2_IMUX31_0", + "GTPE2_IMUX34_6", + "GTPE2_BYP3_7", + "GTPE2_IMUX46_7", + "GTPE2_CHANNEL_RXDISPERR0", + "GTPE2_IMUX1_3", + "GTPE2_IMUX0_10", + "GTPE2_IMUX32_8", + "GTPE2_LOGIC_OUTS_B7_8", + "GTPE2_BYP5_8", + "GTPE2_CHANNEL_TXPHALIGN", + "GTPE2_BYP1_4", + "GTPE2_CHANNEL_TSTIN19", + "GTPE2_CHANNEL_PCSRSVDOUT15", + "GTPE2_IMUX18_2", + "GTPE2_IMUX16_5", + "GTPE2_LOGIC_OUTS_B12_10", + "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "GTPE2_BYP6_0", + "GTPE2_LOGIC_OUTS_B17_3", + "GTPE2_IMUX7_2", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", + "GTPE2_IMUX33_8", + "GTPE2_IMUX34_5", + "GTPE2_CHANNEL_RXCHARISK2", + "GTPE2_IMUX25_5", + "GTPE2_IMUX18_5", + "GTPE2_CHANNEL_RXCHBONDSLAVE", + "GTPE2_CHANNEL_TXOUTCLK_0", + "GTPE2_CHANNEL_TXMAINCURSOR3", + "GTPE2_IMUX9_8", + "GTPE2_IMUX21_6", + "GTPE2_LOGIC_OUTS_B21_3", + "GTPE2_IMUX7_9", + "GTPE2_LOGIC_OUTS_B18_6", + "GTPE2_IMUX45_4", + "GTPE2_BYP7_5", + "GTPE2_CHANNEL_TXCHARDISPMODE2", + "GTPE2_CHANNEL_TXBUFDIFFCTRL1", + "GTPE2_IMUX25_2", + "GTPE2_IMUX28_8", + "GTPE2_CHANNEL_RXADAPTSELTEST7", + "GTPE2_CHANNEL_TXDLYHOLD", + "GTPE2_IMUX43_6", + "GTPE2_CHANNEL_TXDATA13", + "GTPE2_LOGIC_OUTS_B15_0", + "GTPE2_CHANNEL_RXMCOMMAALIGNEN", + "GTPE2_LOGIC_OUTS_B18_5", + "GTPE2_CHANNEL_RXOSHOLD", + "GTPE2_LOGIC_OUTS_B11_8", + "GTPE2_IMUX8_8", + "GTPE2_LOGIC_OUTS_B2_10", + "GTPE2_CHANNEL_RXP_PAD", + "GTPE2_IMUX20_3", + "GTPE2_IMUX38_2", + "GTPE2_FAN1_3", + "GTPE2_IMUX4_0", + "GTPE2_CHANNEL_GTTXRESET", + "GTPE2_BYP3_10", + "GTPE2_LOGIC_OUTS_B16_4", + "GTPE2_CHANNEL_PMASCANENB", + "GTPE2_CHANNEL_RXSYNCIN", + "GTPE2_LOGIC_OUTS_B19_8", + "GTPE2_CHANNEL_TXP", + "GTPE2_CHANNEL_RXHEADER2", + "GTPE2_CHANNEL_TXDATA25", + "GTPE2_LOGIC_OUTS_B14_1", + "GTPE2_IMUX13_3", + "GTPE2_IMUX1_4", + "GTPE2_CHANNEL_DRPDO7", + "GTPE2_BYP1_9", + "GTPE2_IMUX47_8", + "GTPE2_LOGIC_OUTS_B1_10", + "GTPE2_BYP4_4", + "GTPE2_CHANNEL_DRPDI5", + "GTPE2_CHANNEL_RXLPMLFHOLD", + "GTPE2_BYP6_2", + "GTPE2_IMUX21_7", + "GTPE2_CHANNEL_TXDLYSRESET", + "GTPE2_IMUX40_3", + "GTPE2_IMUX38_4", + "GTPE2_LOGIC_OUTS_B21_10", + "GTPE2_BYP3_3", + "GTPE2_FAN2_8", + "GTPE2_BYP6_8", + "GTPE2_CHANNEL_TXDATA27", + "GTPE2_FAN4_3", + "GTPE2_CHANNEL_TXPRBSSEL1", + "GTPE2_CHANNEL_PCSRSVDOUT8", + "GTPE2_CHANNEL_TXPD1", + "GTPE2_IMUX24_4", + "GTPE2_CHANNEL_RXRATEDONE", + "GTPE2_CHANNEL_RXPRBSCNTRESET", + "GTPE2_IMUX12_5", + "GTPE2_CHANNEL_RXDATAVALID1", + "GTPE2_CHANNEL_DRPDI13", + "GTPE2_FAN5_2", + "GTPE2_LOGIC_OUTS_B12_7", + "GTPE2_FAN7_3", + "GTPE2_IMUX41_5", + "GTPE2_CHANNEL_TXGEARBOXREADY", + "GTPE2_LOGIC_OUTS_B6_1", + "GTPE2_FAN1_7", + "GTPE2_CHANNEL_TXSYNCIN", + "GTPE2_LOGIC_OUTS_B17_1", + "GTPE2_IMUX9_4", + "GTPE2_CHANNEL_PMASCANIN4", + "GTPE2_CHANNEL_TXRATE2", + "GTPE2_CHANNEL_DRPDO9", + "GTPE2_BYP7_10", + "GTPE2_IMUX8_7", + "GTPE2_CHANNEL_TSTIN9", + "GTPE2_IMUX12_10", + "GTPE2_LOGIC_OUTS_B19_2", + "GTPE2_LOGIC_OUTS_B19_10", + "GTPE2_BYP1_0", + "GTPE2_LOGIC_OUTS_B15_6", + "GTPE2_IMUX26_5", + "GTPE2_IMUX7_7", + "GTPE2_CHANNEL_TXDIFFCTRL1", + "GTPE2_IMUX41_7", + "GTPE2_CHANNEL_PLL1CLK", + "GTPE2_IMUX33_2", + "GTPE2_CHANNEL_TSTPD4", + "GTPE2_CHANNEL_RXDLYSRESET", + "GTPE2_LOGIC_OUTS_B2_8", + "GTPE2_CHANNEL_RXRATE2", + "GTPE2_FAN5_0", + "GTPE2_CHANNEL_RXOUTCLKSEL0", + "GTPE2_CHANNEL_TXPHINITDONE", + "GTPE2_IMUX45_10", + "GTPE2_IMUX1_0", + "GTPE2_CHANNEL_EYESCANDATAERROR", + "GTPE2_CHANNEL_DRPDI7", + "GTPE2_CHANNEL_RXDATA10", + "GTPE2_CHANNEL_SCANMODEB", + "GTPE2_LOGIC_OUTS_B23_3", + "GTPE2_IMUX31_10", + "GTPE2_FAN6_10", + "GTPE2_IMUX35_10", + "GTPE2_CHANNEL_DMONITOROUT12", + "GTPE2_LOGIC_OUTS_B15_1", + "GTPE2_CHANNEL_TXDLYSRESETDONE", + "GTPE2_CHANNEL_RXDLYOVRDEN", + "GTPE2_IMUX47_2", + "GTPE2_IMUX40_0", + "GTPE2_CHANNEL_PCSRSVDIN1", + "GTPE2_IMUX12_4", + "GTPE2_CHANNEL_DMONITOROUT6", + "GTPE2_IMUX6_8", + "GTPE2_CHANNEL_RXOSOVRDEN", + "GTPE2_CHANNEL_TXDIFFPD", + "GTPE2_CHANNEL_RXCHARISCOMMA2", + "GTPE2_LOGIC_OUTS_B2_5", + "GTPE2_CLK0_3", + "GTPE2_LOGIC_OUTS_B14_0", + "GTPE2_IMUX4_5", + "GTPE2_FAN3_7", + "GTPE2_CHANNEL_TSTIN12", + "GTPE2_IMUX21_8", + "GTPE2_CHANNEL_RXELECIDLEMODE1", + "GTPE2_LOGIC_OUTS_B18_3", + "GTPE2_CHANNEL_RXPHMONITOR2", + "GTPE2_IMUX11_10", + "GTPE2_IMUX31_3", + "GTPE2_CLK1_7", + "GTPE2_CLK1_2", + "GTPE2_LOGIC_OUTS_B5_6", + "GTPE2_FAN6_4", + "GTPE2_IMUX11_7", + "GTPE2_BYP7_4", + "GTPE2_IMUX2_8", + "GTPE2_LOGIC_OUTS_B5_4", + "GTPE2_FAN2_0", + "GTPE2_IMUX32_5", + "GTPE2_LOGIC_OUTS_B16_5", + "GTPE2_LOGIC_OUTS_B18_4", + "GTPE2_BYP4_2", + "GTPE2_CHANNEL_TXPHDLYTSTCLK", + "GTPE2_CHANNEL_SCANIN2", + "GTPE2_IMUX37_5", + "GTPE2_BYP7_8", + "GTPE2_IMUX3_10", + "GTPE2_FAN7_9", + "GTPE2_LOGIC_OUTS_B7_2", + "GTPE2_LOGIC_OUTS_B4_9", + "GTPE2_LOGIC_OUTS_B13_5", + "GTPE2_CHANNEL_GTRSVD3", + "GTPE2_IMUX22_0", + "GTPE2_IMUX2_10", + "GTPE2_CHANNEL_GTRXRESET", + "GTPE2_IMUX35_3", + "GTPE2_IMUX14_6", + "GTPE2_IMUX44_1", + "GTPE2_IMUX38_9", + "GTPE2_CHANNEL_RXDATA28", + "GTPE2_CHANNEL_DRPDI1", + "GTPE2_LOGIC_OUTS_B23_0", + "GTPE2_IMUX10_6", + "GTPE2_CHANNEL_TXOUTCLKSEL0", + "GTPE2_IMUX0_8", + "GTPE2_LOGIC_OUTS_B11_10", + "GTPE2_LOGIC_OUTS_B2_3", + "GTPE2_IMUX15_7", + "GTPE2_IMUX36_1", + "GTPE2_CLK0_6", + "GTPE2_CHANNEL_RXNOTINTABLE3", + "GTPE2_CHANNEL_RXCHANISALIGNED", + "GTPE2_IMUX8_1", + "GTPE2_CHANNEL_TSTPD0", + "GTPE2_CHANNEL_TXDATA14", + "GTPE2_CHANNEL_RXN", + "GTPE2_IMUX14_5", + "GTPE2_IMUX44_4", + "GTPE2_IMUX20_7", + "GTPE2_FAN5_3", + "GTPE2_FAN2_9", + "GTPE2_CHANNEL_TSTIN13", + "GTPE2_CHANNEL_LOOPBACK1", + "GTPE2_IMUX43_2", + "GTPE2_BYP5_6", + "GTPE2_CHANNEL_RXDLYBYPASS", + "GTPE2_LOGIC_OUTS_B11_5", + "GTPE2_IMUX4_8", + "GTPE2_LOGIC_OUTS_B22_4", + "GTPE2_LOGIC_OUTS_B14_2", + "GTPE2_CHANNEL_TXHEADER2", + "GTPE2_IMUX6_7", + "GTPE2_CHANNEL_PCSRSVDOUT1", + "GTPE2_IMUX9_10", + "GTPE2_LOGIC_OUTS_B9_2", + "GTPE2_CHANNEL_PMASCANIN3", + "GTPE2_LOGIC_OUTS_B0_2", + "GTPE2_IMUX10_4", + "GTPE2_CHANNEL_PMASCANOUT5", + "GTPE2_LOGIC_OUTS_B4_5", + "GTPE2_IMUX22_5", + "GTPE2_CHANNEL_TXMARGIN1", + "GTPE2_IMUX43_5", + "GTPE2_LOGIC_OUTS_B17_9", + "GTPE2_CHANNEL_RXLPMLFOVRDEN", + "GTPE2_CHANNEL_RXRATE1", + "GTPE2_LOGIC_OUTS_B5_2", + "GTPE2_IMUX1_2", + "GTPE2_CHANNEL_PCSRSVDIN14", + "GTPE2_BYP6_6", + "GTPE2_CHANNEL_SCANENB", + "GTPE2_CHANNEL_PMASCANCLK0", + "GTPE2_IMUX5_6", + "GTPE2_LOGIC_OUTS_B16_10", + "GTPE2_IMUX47_0", + "GTPE2_LOGIC_OUTS_B3_1", + "GTPE2_LOGIC_OUTS_B21_2", + "GTPE2_CHANNEL_RXCHARISK1", + "GTPE2_IMUX36_7", + "GTPE2_CHANNEL_TXDETECTRX", + "GTPE2_IMUX23_3", + "GTPE2_IMUX20_1", + "GTPE2_IMUX30_8", + "GTPE2_CHANNEL_TXDATA29", + "GTPE2_CHANNEL_TXDATA31", + "GTPE2_CHANNEL_RXDATA5", + "GTPE2_FAN6_7", + "GTPE2_LOGIC_OUTS_B1_3", + "GTPE2_CHANNEL_SCANIN3", + "GTPE2_CHANNEL_RXADAPTSELTEST3", + "GTPE2_CHANNEL_TXRUNDISP2", + "GTPE2_CHANNEL_RXSYSCLKSEL1", + "GTPE2_CHANNEL_RXOSINTID03", + "GTPE2_CHANNEL_TXBUFSTATUS0", + "GTPE2_BYP6_7", + "GTPE2_CHANNEL_RXCHBONDMASTER", + "GTPE2_IMUX35_8", + "GTPE2_IMUX17_5", + "GTPE2_LOGIC_OUTS_B5_8", + "GTPE2_IMUX10_2", + "GTPE2_CHANNEL_TXPOSTCURSORINV", + "GTPE2_IMUX47_4", + "GTPE2_IMUX42_2", + "GTPE2_IMUX47_10", + "GTPE2_LOGIC_OUTS_B23_1", + "GTPE2_IMUX15_4", + "GTPE2_FAN4_9", + "GTPE2_CHANNEL_RXPRBSSEL2", + "GTPE2_LOGIC_OUTS_B14_10", + "GTPE2_IMUX35_9", + "GTPE2_CHANNEL_RXBUFRESET", + "GTPE2_CHANNEL_TXDATA22", + "GTPE2_CHANNEL_PMASCANOUT2", + "GTPE2_LOGIC_OUTS_B4_1", + "GTPE2_IMUX28_6", + "GTPE2_IMUX16_7", + "GTPE2_CHANNEL_DMONITOROUT3", + "GTPE2_LOGIC_OUTS_B20_7", + "GTPE2_LOGIC_OUTS_B12_3", + "GTPE2_LOGIC_OUTS_B23_9", + "GTPE2_IMUX28_4", + "GTPE2_CHANNEL_TXRATE0", + "GTPE2_CHANNEL_DRPDO8", + "GTPE2_CHANNEL_TXDEEMPH", + "GTPE2_LOGIC_OUTS_B2_1", + "GTPE2_LOGIC_OUTS_B1_2", + "GTPE2_LOGIC_OUTS_B16_8", + "GTPE2_CHANNEL_PCSRSVDIN6", + "GTPE2_IMUX0_5", + "GTPE2_CHANNEL_SCANCLK", + "GTPE2_CHANNEL_RXADAPTSELTEST10", + "GTPE2_CHANNEL_TSTIN5", + "GTPE2_IMUX38_3", + "GTPE2_FAN0_0", + "GTPE2_IMUX7_5", + "GTPE2_IMUX45_8", + "GTPE2_IMUX17_7", + "GTPE2_CHANNEL_TSTIN6", + "GTPE2_IMUX39_5", + "GTPE2_CHANNEL_RXPHMONITOR0", + "GTPE2_FAN2_4", + "GTPE2_LOGIC_OUTS_B11_7", + "GTPE2_CHANNEL_TXN", + "GTPE2_CHANNEL_CFGRESET", + "GTPE2_CHANNEL_TXPOSTCURSOR3", + "GTPE2_CHANNEL_RXADAPTSELTEST9", + "GTPE2_CHANNEL_TXPRECURSORINV", + "GTPE2_CHANNEL_DRPADDR1", + "GTPE2_CHANNEL_TXDATA18", + "GTPE2_FAN1_8", + "GTPE2_LOGIC_OUTS_B10_7", + "GTPE2_BYP1_7", + "GTPE2_BYP7_1", + "GTPE2_LOGIC_OUTS_B11_2", + "GTPE2_IMUX17_9", + "GTPE2_CHANNEL_RXCHBONDLEVEL2", + "GTPE2_BYP3_2", + "GTPE2_IMUX45_0", + "GTPE2_CHANNEL_TXPMARESETDONE", + "GTPE2_IMUX14_0", + "GTPE2_CHANNEL_PCSRSVDOUT3", + "GTPE2_CHANNEL_TXINHIBIT", + "GTPE2_LOGIC_OUTS_B14_5", + "GTPE2_IMUX19_2", + "GTPE2_CHANNEL_DRPDI3", + "GTPE2_IMUX28_2", + "GTPE2_IMUX18_6", + "GTPE2_CHANNEL_DRPADDR4", + "GTPE2_CHANNEL_TXPRECURSOR4", + "GTPE2_IMUX34_0", + "GTPE2_IMUX40_4", + "GTPE2_CHANNEL_TXPHALIGNDONE", + "GTPE2_LOGIC_OUTS_B3_3", + "GTPE2_LOGIC_OUTS_B23_2", + "GTPE2_FAN5_4", + "GTPE2_LOGIC_OUTS_B22_1", + "GTPE2_IMUX39_7", + "GTPE2_FAN6_6", + "GTPE2_IMUX13_9", + "GTPE2_CHANNEL_TXSYSCLKSEL0", + "GTPE2_CHANNEL_RXPHDLYRESET", + "GTPE2_LOGIC_OUTS_B19_1", + "GTPE2_CHANNEL_TXCHARDISPVAL3", + "GTPE2_IMUX37_9", + "GTPE2_IMUX13_6", + "GTPE2_FAN0_6", + "GTPE2_LOGIC_OUTS_B0_5", + "GTPE2_CHANNEL_TXPD0", + "GTPE2_CHANNEL_PCSRSVDIN15", + "GTPE2_IMUX47_3", + "GTPE2_CHANNEL_DRPEN", + "GTPE2_BYP4_1", + "GTPE2_IMUX3_9", + "GTPE2_BYP0_7", + "GTPE2_IMUX28_9", + "GTPE2_IMUX16_1", + "GTPE2_CHANNEL_RXDATA13", + "GTPE2_CHANNEL_PHYSTATUS", + "GTPE2_IMUX31_2", + "GTPE2_CHANNEL_TXDIFFCTRL3", + "GTPE2_IMUX8_6", + "GTPE2_LOGIC_OUTS_B3_0", + "GTPE2_IMUX28_7", + "GTPE2_IMUX8_0", + "GTPE2_FAN0_7", + "GTPE2_LOGIC_OUTS_B13_8", + "GTPE2_CHANNEL_TXMAINCURSOR6", + "GTPE2_CHANNEL_DRPWE", + "GTPE2_LOGIC_OUTS_B2_7", + "GTPE2_IMUX33_1", + "GTPE2_IMUX3_8", + "GTPE2_IMUX11_0", + "GTPE2_LOGIC_OUTS_B3_7", + "GTPE2_CLK0_8", + "GTPE2_IMUX36_5", + "GTPE2_IMUX11_5", + "GTPE2_CHANNEL_TXDATA23", + "GTPE2_IMUX19_4", + "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", + "GTPE2_IMUX23_10", + "GTPE2_CHANNEL_RXOUTCLK_1", + "GTPE2_IMUX40_5", + "GTPE2_FAN1_9", + "GTPE2_CHANNEL_RXADAPTSELTEST13", + "GTPE2_CHANNEL_RXN_PAD", + "GTPE2_CHANNEL_RXVALID", + "GTPE2_CHANNEL_TXDLYBYPASS", + "GTPE2_IMUX44_9", + "GTPE2_CHANNEL_TXOUTCLKPCS", + "GTPE2_CHANNEL_PMASCANOUT3", + "GTPE2_CHANNEL_DRPADDR7", + "GTPE2_CHANNEL_RXDATA16", + "GTPE2_IMUX39_9", + "GTPE2_LOGIC_OUTS_B10_3", + "GTPE2_IMUX21_0", + "GTPE2_BYP1_5", + "GTPE2_IMUX3_3", + "GTPE2_LOGIC_OUTS_B3_9", + "GTPE2_IMUX32_0", + "GTPE2_CHANNEL_TXPRBSSEL0", + "GTPE2_IMUX26_6", + "GTPE2_CHANNEL_RXPCOMMAALIGNEN", + "GTPE2_IMUX13_10", + "GTPE2_CHANNEL_RXPHALIGNDONE", + "GTPE2_LOGIC_OUTS_B9_6", + "GTPE2_LOGIC_OUTS_B17_0", + "GTPE2_CHANNEL_RXDATA22", + "GTPE2_CHANNEL_RXOUTCLK_0", + "GTPE2_IMUX13_4", + "GTPE2_CHANNEL_GTRSVD1", + "GTPE2_CHANNEL_RXDATA12", + "GTPE2_CHANNEL_SCANOUT3", + "GTPE2_CHANNEL_RXCDRRESET", + "GTPE2_IMUX1_6", + "GTPE2_CHANNEL_TXPRECURSOR3", + "GTPE2_CHANNEL_DRPDI9", + "GTPE2_LOGIC_OUTS_B9_8", + "GTPE2_FAN6_1", + "GTPE2_IMUX19_7", + "GTPE2_CHANNEL_TXCHARDISPMODE3", + "GTPE2_CHANNEL_PMASCANOUT1", + "GTPE2_IMUX37_10", + "GTPE2_CTRL1_3", + "GTPE2_LOGIC_OUTS_B16_2", + "GTPE2_IMUX45_5", + "GTPE2_CHANNEL_PCSRSVDIN12", + "GTPE2_IMUX19_5", + "GTPE2_CHANNEL_RXADAPTSELTEST12", + "GTPE2_IMUX13_0", + "GTPE2_CTRL0_7", + "GTPE2_LOGIC_OUTS_B18_10", + "GTPE2_IMUX0_3", + "GTPE2_IMUX34_3", + "GTPE2_CHANNEL_RXOSINTOVRDEN", + "GTPE2_CHANNEL_TXSEQUENCE5", + "GTPE2_LOGIC_OUTS_B22_3", + "GTPE2_CHANNEL_RXLPMHFOVRDEN", + "GTPE2_CHANNEL_TXDATA6", + "GTPE2_IMUX19_0", + "GTPE2_CHANNEL_RXDATA20", + "GTPE2_CHANNEL_SCANOUT0", + "GTPE2_CHANNEL_TXPOSTCURSOR4", + "GTPE2_CHANNEL_TXPOSTCURSOR1", + "GTPE2_LOGIC_OUTS_B23_4", + "GTPE2_CHANNEL_SCANIN1", + "GTPE2_FAN7_1", + "GTPE2_IMUX2_9", + "GTPE2_CHANNEL_RXPHALIGNEN", + "GTPE2_FAN2_1", + "GTPE2_CHANNEL_TXPHDLYRESET", + "GTPE2_CHANNEL_RXPD1", + "GTPE2_CHANNEL_RXPRBSERR", + "GTPE2_CHANNEL_PMARSVDOUT0", + "GTPE2_IMUX25_8", + "GTPE2_IMUX23_0", + "GTPE2_IMUX15_9", + "GTPE2_FAN5_5", + "GTPE2_CHANNEL_PMASCANRSTEN", + "GTPE2_CHANNEL_RXCHARISK0", + "GTPE2_LOGIC_OUTS_B21_9", + "GTPE2_IMUX7_8", + "GTPE2_IMUX14_8", + "GTPE2_FAN5_7", + "GTPE2_CHANNEL_TSTPD2", + "GTPE2_LOGIC_OUTS_B8_7", + "GTPE2_LOGIC_OUTS_B22_2", + "GTPE2_IMUX32_10", + "GTPE2_CHANNEL_TXPOSTCURSOR2", + "GTPE2_CHANNEL_DRPDO14", + "GTPE2_IMUX21_2", + "GTPE2_CLK1_3", + "GTPE2_CHANNEL_RXCOMMADETEN", + "GTPE2_IMUX16_2", + "GTPE2_CHANNEL_TXPRECURSOR1", + "GTPE2_IMUX32_6", + "GTPE2_IMUX3_6", + "GTPE2_CTRL1_7", + "GTPE2_CHANNEL_RXPHDLYPD", + "GTPE2_BYP2_7", + "GTPE2_CHANNEL_DMONITOROUT5", + "GTPE2_CTRL0_8", + "GTPE2_LOGIC_OUTS_B14_9", + "GTPE2_CHANNEL_TXRUNDISP0", + "GTPE2_IMUX3_4", + "GTPE2_IMUX18_10", + "GTPE2_CHANNEL_PCSRSVDIN10", + "GTPE2_IMUX20_5", + "GTPE2_IMUX29_6", + "GTPE2_IMUX42_9", + "GTPE2_IMUX28_5", + "GTPE2_LOGIC_OUTS_B11_6", + "GTPE2_CHANNEL_RXDATA30", + "GTPE2_LOGIC_OUTS_B1_6", + "GTPE2_IMUX2_2", + "GTPE2_CHANNEL_PMARSVDIN0", + "GTPE2_FAN6_3", + "GTPE2_CHANNEL_PMASCANIN6", + "GTPE2_FAN0_5", + "GTPE2_CHANNEL_TXCHARISK1", + "GTPE2_FAN4_8", + "GTPE2_BYP2_1", + "GTPE2_LOGIC_OUTS_B13_9", + "GTPE2_CHANNEL_RXCHARISCOMMA0", + "GTPE2_IMUX37_1", + "GTPE2_CHANNEL_RXSTATUS0", + "GTPE2_IMUX14_10", + "GTPE2_IMUX33_3", + "GTPE2_IMUX37_2", + "GTPE2_FAN1_6", + "GTPE2_CHANNEL_RXDATAVALID0", + "GTPE2_CHANNEL_PCSRSVDOUT9", + "GTPE2_IMUX19_9", + "GTPE2_IMUX47_1", + "GTPE2_IMUX47_7", + "GTPE2_CHANNEL_TXUSERRDY", + "GTPE2_LOGIC_OUTS_B7_5", + "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "GTPE2_CHANNEL_RXDATA31", + "GTPE2_CHANNEL_RXDISPERR2", + "GTPE2_CHANNEL_PCSRSVDOUT13", + "GTPE2_CHANNEL_DMONITOROUT14", + "GTPE2_CHANNEL_DRPDO11", + "GTPE2_CHANNEL_DRPDO4", + "GTPE2_LOGIC_OUTS_B10_9", + "GTPE2_IMUX17_4", + "GTPE2_LOGIC_OUTS_B14_6", + "GTPE2_CHANNEL_TXELECIDLE", + "GTPE2_FAN3_6", + "GTPE2_CHANNEL_TXDATA20", + "GTPE2_CHANNEL_DMONITOROUT7", + "GTPE2_IMUX17_3", + "GTPE2_LOGIC_OUTS_B8_1", + "GTPE2_LOGIC_OUTS_B5_1", + "GTPE2_CHANNEL_PMASCANOUT0", + "GTPE2_IMUX15_3", + "GTPE2_CHANNEL_TXMAINCURSOR5", + "GTPE2_IMUX43_7", + "GTPE2_BYP0_0", + "GTPE2_CHANNEL_PMARSVDIN2", + "GTPE2_IMUX0_6", + "GTPE2_CHANNEL_GTRESETSEL", + "GTPE2_IMUX20_9", + "GTPE2_CHANNEL_TSTIN10", + "GTPE2_CHANNEL_TXDATA28", + "GTPE2_CHANNEL_DRPDI6", + "GTPE2_CHANNEL_RXCHBONDO0", + "GTPE2_IMUX40_7", + "GTPE2_BYP5_7", + "GTPE2_CHANNEL_DRPADDR8", + "GTPE2_CHANNEL_TXDATA21", + "GTPE2_IMUX42_1", + "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "GTPE2_LOGIC_OUTS_B19_3", + "GTPE2_LOGIC_OUTS_B3_10", + "GTPE2_BYP3_5", + "GTPE2_IMUX43_0", + "GTPE2_CHANNEL_TXRESETDONE", + "GTPE2_CHANNEL_PMARSVDOUT1", + "GTPE2_IMUX13_1", + "GTPE2_CHANNEL_TSTIN4", + "GTPE2_BYP2_4", + "GTPE2_CHANNEL_RXADAPTSELTEST1", + "GTPE2_FAN2_2", + "GTPE2_IMUX13_2", + "GTPE2_CHANNEL_TXRUNDISP3", + "GTPE2_CHANNEL_TSTIN8", + "GTPE2_CHANNEL_RXDATA11", + "GTPE2_IMUX40_1", + "GTPE2_FAN7_6", + "GTPE2_LOGIC_OUTS_B0_4", + "GTPE2_CHANNEL_RXOSINTSTARTED", + "GTPE2_CHANNEL_TSTCLK0", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", + "GTPE2_IMUX1_10", + "GTPE2_IMUX5_10", + "GTPE2_CHANNEL_TXDATA30", + "GTPE2_IMUX43_3", + "GTPE2_LOGIC_OUTS_B0_0", + "GTPE2_IMUX46_8", + "GTPE2_IMUX10_8", + "GTPE2_CHANNEL_TXSWING", + "GTPE2_IMUX37_4", + "GTPE2_CHANNEL_TXDATA10", + "GTPE2_CHANNEL_SCANOUT4", + "GTPE2_IMUX6_3", + "GTPE2_BYP2_5", + "GTPE2_CHANNEL_RXNOTINTABLE0", + "GTPE2_IMUX6_9", + "GTPE2_IMUX40_8", + "GTPE2_IMUX0_1", + "GTPE2_IMUX4_6", + "GTPE2_CHANNEL_RXOSINTSTROBE", + "GTPE2_LOGIC_OUTS_B8_8", + "GTPE2_IMUX12_9", + "GTPE2_IMUX22_2", + "GTPE2_IMUX32_2", + "GTPE2_CHANNEL_RXCOMINITDET", + "GTPE2_LOGIC_OUTS_B14_4", + "GTPE2_CHANNEL_TXDLYUPDOWN", + "GTPE2_CHANNEL_DRPADDR3", + "GTPE2_CHANNEL_TXDATA7", + "GTPE2_CHANNEL_RXOUTCLKPCS", + "GTPE2_CHANNEL_RXADAPTSELTEST2", + "GTPE2_CHANNEL_RXDATA1", + "GTPE2_CHANNEL_DRPRDY", + "GTPE2_FAN3_8", + "GTPE2_CHANNEL_TXOUTCLKSEL2", + "GTPE2_IMUX12_1", + "GTPE2_CTRL0_4", + "GTPE2_IMUX23_8", + "GTPE2_CHANNEL_RXCDRFREQRESET", + "GTPE2_CHANNEL_PMASCANCLK2", + "GTPE2_IMUX32_1", + "GTPE2_CHANNEL_RXCHBONDLEVEL0", + "GTPE2_CHANNEL_TX8B10BBYPASS2", + "GTPE2_BYP5_9", + "GTPE2_CHANNEL_TXBUFDIFFCTRL2", + "GTPE2_CHANNEL_SCANOUT1", + "GTPE2_CHANNEL_RXOUTCLKSEL1", + "GTPE2_CHANNEL_TXDATA3", + "GTPE2_IMUX16_10", + "GTPE2_CHANNEL_RXCHBONDO2", + "GTPE2_FAN3_0", + "GTPE2_IMUX22_9", + "GTPE2_IMUX15_0", + "GTPE2_CHANNEL_GTRSVD11", + "GTPE2_LOGIC_OUTS_B13_4", + "GTPE2_IMUX43_10", + "GTPE2_CHANNEL_TXBUFSTATUS1", + "GTPE2_CHANNEL_RXBYTEREALIGN", + "GTPE2_CHANNEL_PCSRSVDIN11", + "GTPE2_CHANNEL_PCSRSVDOUT7", + "GTPE2_CHANNEL_GTRSVD15", + "GTPE2_CLK0_0", + "GTPE2_IMUX10_3", + "GTPE2_IMUX31_5", + "GTPE2_IMUX37_3", + "GTPE2_LOGIC_OUTS_B4_4", + "GTPE2_IMUX38_10", + "GTPE2_CHANNEL_PCSRSVDIN0", + "GTPE2_CHANNEL_TXSYSCLKSEL1", + "GTPE2_CHANNEL_PCSRSVDIN7", + "GTPE2_CHANNEL_DRPDI11", + "GTPE2_IMUX4_3", + "GTPE2_LOGIC_OUTS_B19_9", + "GTPE2_CHANNEL_RXPHALIGN", + "GTPE2_IMUX29_8", + "GTPE2_LOGIC_OUTS_B12_0", + "GTPE2_IMUX9_2", + "GTPE2_CHANNEL_PCSRSVDIN13", + "GTPE2_CHANNEL_RXUSRCLK", + "GTPE2_BYP5_5", + "GTPE2_LOGIC_OUTS_B4_2", + "GTPE2_CHANNEL_RXPRBSSEL0", + "GTPE2_CTRL0_0", + "GTPE2_FAN2_5", + "GTPE2_IMUX46_1", + "GTPE2_LOGIC_OUTS_B7_9", + "GTPE2_LOGIC_OUTS_B4_8", + "GTPE2_CHANNEL_RXCHANBONDSEQ", + "GTPE2_IMUX26_9", + "GTPE2_IMUX35_4", + "GTPE2_CHANNEL_TXPIPPMOVRDEN", + "GTPE2_IMUX27_9", + "GTPE2_IMUX30_10", + "GTPE2_LOGIC_OUTS_B17_6", + "GTPE2_CHANNEL_RXDATA27", + "GTPE2_IMUX12_6", + "GTPE2_IMUX41_0", + "GTPE2_IMUX12_7", + "GTPE2_CHANNEL_RXOOBRESET", + "GTPE2_CHANNEL_TX8B10BEN", + "GTPE2_LOGIC_OUTS_B3_2", + "GTPE2_IMUX5_3", + "GTPE2_CHANNEL_RXADAPTSELTEST4", + "GTPE2_CHANNEL_PMASCANOUT6", + "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "GTPE2_BYP4_10", + "GTPE2_CHANNEL_RXDATA29", + "GTPE2_IMUX5_1", + "GTPE2_IMUX14_7", + "GTPE2_CHANNEL_RXCHARISCOMMA3", + "GTPE2_BYP2_2", + "GTPE2_LOGIC_OUTS_B1_7", + "GTPE2_CHANNEL_GTRSVD8", + "GTPE2_CHANNEL_RXPCSRESET", + "GTPE2_CHANNEL_DMONITOROUT4", + "GTPE2_IMUX47_5", + "GTPE2_CHANNEL_GTTXOUTCLK_3", + "GTPE2_IMUX29_3", + "GTPE2_IMUX30_5", + "GTPE2_CTRL1_9", + "GTPE2_CTRL0_10", + "GTPE2_LOGIC_OUTS_B13_6", + "GTPE2_LOGIC_OUTS_B16_3", + "GTPE2_BYP6_10", + "GTPE2_CHANNEL_PCSRSVDIN4", + "GTPE2_IMUX20_6", + "GTPE2_IMUX21_4", + "GTPE2_CHANNEL_PCSRSVDIN3", + "GTPE2_IMUX33_6", + "GTPE2_CHANNEL_EYESCANRESET", + "GTPE2_IMUX41_8", + "GTPE2_IMUX3_1", + "GTPE2_IMUX26_7", + "GTPE2_BYP3_1", + "GTPE2_CLK0_9", + "GTPE2_BYP2_6", + "GTPE2_CHANNEL_RXPHMONITOR1", + "GTPE2_IMUX21_3", + "GTPE2_IMUX27_0", + "GTPE2_IMUX11_1", + "GTPE2_CHANNEL_DRPDO10", + "GTPE2_CHANNEL_RXHEADER0", + "GTPE2_CHANNEL_TSTIN15", + "GTPE2_LOGIC_OUTS_B11_1", + "GTPE2_LOGIC_OUTS_B16_7", + "GTPE2_IMUX6_10", + "GTPE2_CHANNEL_DRPDO12", + "GTPE2_IMUX36_0", + "GTPE2_IMUX47_9", + "GTPE2_LOGIC_OUTS_B6_0", + "GTPE2_CHANNEL_PLL0REFCLK", + "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "GTPE2_CHANNEL_RXDATA6", + "GTPE2_IMUX19_8", + "GTPE2_CHANNEL_RXSTATUS1", + "GTPE2_CHANNEL_RXPMARESETDONE", + "GTPE2_CHANNEL_TXDIFFCTRL2", + "GTPE2_LOGIC_OUTS_B16_6", + "GTPE2_CHANNEL_DRPDO1", + "GTPE2_CHANNEL_RXDLYEN", + "GTPE2_CLK0_2", + "GTPE2_IMUX17_10", + "GTPE2_CHANNEL_TXCHARDISPMODE1", + "GTPE2_CHANNEL_RXDATA15", + "GTPE2_CHANNEL_DRPDI15", + "GTPE2_IMUX15_6", + "GTPE2_IMUX14_4", + "GTPE2_FAN1_4", + "GTPE2_LOGIC_OUTS_B22_0", + "GTPE2_LOGIC_OUTS_B10_2", + "GTPE2_CHANNEL_RXCHANREALIGN", + "GTPE2_CHANNEL_LOOPBACK2", + "GTPE2_IMUX34_4", + "GTPE2_FAN5_10", + "GTPE2_IMUX2_0", + "GTPE2_LOGIC_OUTS_B8_10", + "GTPE2_IMUX7_10", + "GTPE2_CHANNEL_DRPDI4", + "GTPE2_CHANNEL_RXDEBUGPULSE", + "GTPE2_LOGIC_OUTS_B12_6", + "GTPE2_CHANNEL_PMASCANIN5", + "GTPE2_FAN7_5", + "GTPE2_CHANNEL_PMASCANCLK1", + "GTPE2_IMUX43_9", + "GTPE2_LOGIC_OUTS_B12_2", + "GTPE2_LOGIC_OUTS_B20_2", + "GTPE2_IMUX4_4", + "GTPE2_IMUX45_3", + "GTPE2_IMUX30_1", + "GTPE2_LOGIC_OUTS_B8_3", + "GTPE2_FAN5_1", + "GTPE2_CHANNEL_TXMAINCURSOR0", + "GTPE2_IMUX35_0", + "GTPE2_IMUX28_3", + "GTPE2_CHANNEL_RXCHBONDLEVEL1", + "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", + "GTPE2_CHANNEL_TXPRECURSOR0", + "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "GTPE2_CHANNEL_TXPRBSSEL2", + "GTPE2_LOGIC_OUTS_B15_3", + "GTPE2_IMUX4_9", + "GTPE2_IMUX39_2", + "GTPE2_CHANNEL_TXPHDLYPD", + "GTPE2_CHANNEL_TXCHARISK2", + "GTPE2_CHANNEL_PCSRSVDOUT14", + "GTPE2_IMUX17_1", + "GTPE2_LOGIC_OUTS_B23_7", + "GTPE2_LOGIC_OUTS_B11_4", + "GTPE2_IMUX18_9", + "GTPE2_CHANNEL_RX8B10BEN", + "GTPE2_CHANNEL_TXDATA16", + "GTPE2_IMUX32_9", + "GTPE2_IMUX5_4", + "GTPE2_CHANNEL_TXMARGIN0", + "GTPE2_CHANNEL_TXCHARDISPVAL0", + "GTPE2_IMUX16_6", + "GTPE2_IMUX41_1", + "GTPE2_FAN5_9", + "GTPE2_LOGIC_OUTS_B0_9", + "GTPE2_IMUX23_1", + "GTPE2_CHANNEL_DRPDI2", + "GTPE2_IMUX24_5" + ], + "tile_type": "GTP_CHANNEL_3", + "sites": [ + { + "site_pins": { + "TSTIN11": "GTPE2_CHANNEL_TSTIN11", + "TXCOMSAS": "GTPE2_CHANNEL_TXCOMSAS", + "RXPHDLYPD": "GTPE2_CHANNEL_RXPHDLYPD", + "TXSEQUENCE2": "GTPE2_CHANNEL_TXSEQUENCE2", + "TXCHARISK3": "GTPE2_CHANNEL_TXCHARISK3", + "TSTIN4": "GTPE2_CHANNEL_TSTIN4", + "PMASCANOUT1": "GTPE2_CHANNEL_PMASCANOUT1", + "TXDATA26": "GTPE2_CHANNEL_TXDATA26", + "GTRSVD12": "GTPE2_CHANNEL_GTRSVD12", + "TXDATA29": "GTPE2_CHANNEL_TXDATA29", + "PCSRSVDOUT13": "GTPE2_CHANNEL_PCSRSVDOUT13", + "DRPDI4": "GTPE2_CHANNEL_DRPDI4", + "RXNOTINTABLE3": "GTPE2_CHANNEL_RXNOTINTABLE3", + "RXADAPTSELTEST7": "GTPE2_CHANNEL_RXADAPTSELTEST7", + "PMARSVDIN3": "GTPE2_CHANNEL_PMARSVDIN3", + "TXCHARDISPMODE0": "GTPE2_CHANNEL_TXCHARDISPMODE0", + "PMASCANCLK2": "GTPE2_CHANNEL_PMASCANCLK2", + "DRPDI13": "GTPE2_CHANNEL_DRPDI13", + "RXADAPTSELTEST3": "GTPE2_CHANNEL_RXADAPTSELTEST3", + "RXCHARISK2": "GTPE2_CHANNEL_RXCHARISK2", + "RXCOMINITDET": "GTPE2_CHANNEL_RXCOMINITDET", + "TXMAINCURSOR1": "GTPE2_CHANNEL_TXMAINCURSOR1", + "RXUSRCLK": "GTPE2_CHANNEL_RXUSRCLK", + "PMASCANIN0": "GTPE2_CHANNEL_PMASCANIN0", + "RXCLKCORCNT0": "GTPE2_CHANNEL_RXCLKCORCNT0", + "RXDATA16": "GTPE2_CHANNEL_RXDATA16", + "CFGRESET": "GTPE2_CHANNEL_CFGRESET", + "TSTIN1": "GTPE2_CHANNEL_TSTIN1", + "TXPIPPMOVRDEN": "GTPE2_CHANNEL_TXPIPPMOVRDEN", + "TXPHINIT": "GTPE2_CHANNEL_TXPHINIT", + "EYESCANMODE": "GTPE2_CHANNEL_EYESCANMODE", + "TSTCLK1": "GTPE2_CHANNEL_TSTCLK1", + "RXBUFSTATUS1": "GTPE2_CHANNEL_RXBUFSTATUS1", + "TXPRBSSEL1": "GTPE2_CHANNEL_TXPRBSSEL1", + "LOOPBACK1": "GTPE2_CHANNEL_LOOPBACK1", + "TXMARGIN2": "GTPE2_CHANNEL_TXMARGIN2", + "TSTIN12": "GTPE2_CHANNEL_TSTIN12", + "TSTPD3": "GTPE2_CHANNEL_TSTPD3", + "GTRSVD15": "GTPE2_CHANNEL_GTRSVD15", + "TXDLYEN": "GTPE2_CHANNEL_TXDLYEN", + "TXBUFDIFFCTRL0": "GTPE2_CHANNEL_TXBUFDIFFCTRL0", + "TXRUNDISP3": "GTPE2_CHANNEL_TXRUNDISP3", + "GTRSVD2": "GTPE2_CHANNEL_GTRSVD2", + "PCSRSVDIN9": "GTPE2_CHANNEL_PCSRSVDIN9", + "RXVALID": "GTPE2_CHANNEL_RXVALID", + "TXOUTCLKSEL1": "GTPE2_CHANNEL_TXOUTCLKSEL1", + "RXPCOMMAALIGNEN": "GTPE2_CHANNEL_RXPCOMMAALIGNEN", + "RXDATA15": "GTPE2_CHANNEL_RXDATA15", + "TXELECIDLE": "GTPE2_CHANNEL_TXELECIDLE", + "TXDIFFCTRL3": "GTPE2_CHANNEL_TXDIFFCTRL3", + "PCSRSVDIN6": "GTPE2_CHANNEL_PCSRSVDIN6", + "RXCOMMADETEN": "GTPE2_CHANNEL_RXCOMMADETEN", + "TXSYSCLKSEL1": "GTPE2_CHANNEL_TXSYSCLKSEL1", + "DRPDO5": "GTPE2_CHANNEL_DRPDO5", + "TXDATA6": "GTPE2_CHANNEL_TXDATA6", + "GTRSVD0": "GTPE2_CHANNEL_GTRSVD0", + "GTRSVD8": "GTPE2_CHANNEL_GTRSVD8", + "TXUSRCLK2": "GTPE2_CHANNEL_TXUSRCLK2", + "TXRATE0": "GTPE2_CHANNEL_TXRATE0", + "TSTCLK0": "GTPE2_CHANNEL_TSTCLK0", + "PMASCANRSTEN": "GTPE2_CHANNEL_PMASCANRSTEN", + "TXDATA21": "GTPE2_CHANNEL_TXDATA21", + "RXCDROVRDEN": "GTPE2_CHANNEL_RXCDROVRDEN", + "TXDATA3": "GTPE2_CHANNEL_TXDATA3", + "RXNOTINTABLE0": "GTPE2_CHANNEL_RXNOTINTABLE0", + "TXPOSTCURSOR3": "GTPE2_CHANNEL_TXPOSTCURSOR3", + "RXSYNCOUT": "GTPE2_CHANNEL_RXSYNCOUT", + "RXCHBONDI3": "GTPE2_CHANNEL_RXCHBONDI3", + "RXCHANBONDSEQ": "GTPE2_CHANNEL_RXCHANBONDSEQ", + "TSTIN7": "GTPE2_CHANNEL_TSTIN7", + "RXPOLARITY": "GTPE2_CHANNEL_RXPOLARITY", + "TXMAINCURSOR3": "GTPE2_CHANNEL_TXMAINCURSOR3", + "DRPDI9": "GTPE2_CHANNEL_DRPDI9", + "RXHEADERVALID": "GTPE2_CHANNEL_RXHEADERVALID", + "PMARSVDOUT1": "GTPE2_CHANNEL_PMARSVDOUT1", + "DMONITOROUT13": "GTPE2_CHANNEL_DMONITOROUT13", + "RXSLIDE": "GTPE2_CHANNEL_RXSLIDE", + "LOOPBACK2": "GTPE2_CHANNEL_LOOPBACK2", + "PCSRSVDIN8": "GTPE2_CHANNEL_PCSRSVDIN8", + "RXCOMWAKEDET": "GTPE2_CHANNEL_RXCOMWAKEDET", + "RX8B10BEN": "GTPE2_CHANNEL_RX8B10BEN", + "RXOSINTCFG0": "GTPE2_CHANNEL_RXOSINTCFG0", + "TXMARGIN0": "GTPE2_CHANNEL_TXMARGIN0", + "PCSRSVDOUT2": "GTPE2_CHANNEL_PCSRSVDOUT2", + "TXPIPPMSTEPSIZE4": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE4", + "TXPIPPMPD": "GTPE2_CHANNEL_TXPIPPMPD", + "TXPD0": "GTPE2_CHANNEL_TXPD0", + "RXADAPTSELTEST0": "GTPE2_CHANNEL_RXADAPTSELTEST0", + "TXSYSCLKSEL0": "GTPE2_CHANNEL_TXSYSCLKSEL0", + "RXCHBONDO0": "GTPE2_CHANNEL_RXCHBONDO0", + "TXHEADER2": "GTPE2_CHANNEL_TXHEADER2", + "PCSRSVDOUT14": "GTPE2_CHANNEL_PCSRSVDOUT14", + "TXRATE2": "GTPE2_CHANNEL_TXRATE2", + "SCANOUT1": "GTPE2_CHANNEL_SCANOUT1", + "PCSRSVDIN12": "GTPE2_CHANNEL_PCSRSVDIN12", + "GTRSVD6": "GTPE2_CHANNEL_GTRSVD6", + "TXPD1": "GTPE2_CHANNEL_TXPD1", + "TXDLYHOLD": "GTPE2_CHANNEL_TXDLYHOLD", + "CLKRSVD1": "GTPE2_CHANNEL_CLKRSVD1", + "TXPHALIGNEN": "GTPE2_CHANNEL_TXPHALIGNEN", + "TXPHDLYPD": "GTPE2_CHANNEL_TXPHDLYPD", + "TXCHARDISPMODE3": "GTPE2_CHANNEL_TXCHARDISPMODE3", + "SCANOUT5": "GTPE2_CHANNEL_SCANOUT5", + "RXOUTCLKSEL1": "GTPE2_CHANNEL_RXOUTCLKSEL1", + "DRPDI10": "GTPE2_CHANNEL_DRPDI10", + "PCSRSVDOUT11": "GTPE2_CHANNEL_PCSRSVDOUT11", + "RXGEARBOXSLIP": "GTPE2_CHANNEL_RXGEARBOXSLIP", + "TXPHALIGNDONE": "GTPE2_CHANNEL_TXPHALIGNDONE", + "RXSYNCALLIN": "GTPE2_CHANNEL_RXSYNCALLIN", + "TXDATA2": "GTPE2_CHANNEL_TXDATA2", + "DMONITOROUT2": "GTPE2_CHANNEL_DMONITOROUT2", + "GTRXRESET": "GTPE2_CHANNEL_GTRXRESET", + "RXOSCALRESET": "GTPE2_CHANNEL_RXOSCALRESET", + "RXCHARISCOMMA0": "GTPE2_CHANNEL_RXCHARISCOMMA0", + "PCSRSVDIN11": "GTPE2_CHANNEL_PCSRSVDIN11", + "RXPRBSSEL1": "GTPE2_CHANNEL_RXPRBSSEL1", + "TXPHOVRDEN": "GTPE2_CHANNEL_TXPHOVRDEN", + "RXPHMONITOR2": "GTPE2_CHANNEL_RXPHMONITOR2", + "GTPRXP": "GTPE2_CHANNEL_RXP", + "TXDLYBYPASS": "GTPE2_CHANNEL_TXDLYBYPASS", + "TSTIN16": "GTPE2_CHANNEL_TSTIN16", + "TXPOSTCURSORINV": "GTPE2_CHANNEL_TXPOSTCURSORINV", + "RXCOMSASDET": "GTPE2_CHANNEL_RXCOMSASDET", + "DMONITOROUT9": "GTPE2_CHANNEL_DMONITOROUT9", + "RXDATA18": "GTPE2_CHANNEL_RXDATA18", + "GTRSVD9": "GTPE2_CHANNEL_GTRSVD9", + "SCANOUT0": "GTPE2_CHANNEL_SCANOUT0", + "RXADAPTSELTEST6": "GTPE2_CHANNEL_RXADAPTSELTEST6", + "RXDATA19": "GTPE2_CHANNEL_RXDATA19", + "RXCHBONDSLAVE": "GTPE2_CHANNEL_RXCHBONDSLAVE", + "DMONITOROUT7": "GTPE2_CHANNEL_DMONITOROUT7", + "RXCDRHOLD": "GTPE2_CHANNEL_RXCDRHOLD", + "TXMAINCURSOR0": "GTPE2_CHANNEL_TXMAINCURSOR0", + "RXOSINTCFG2": "GTPE2_CHANNEL_RXOSINTCFG2", + "PMARSVDIN4": "GTPE2_CHANNEL_PMARSVDIN4", + "TXMAINCURSOR5": "GTPE2_CHANNEL_TXMAINCURSOR5", + "TSTIN9": "GTPE2_CHANNEL_TSTIN9", + "TX8B10BBYPASS1": "GTPE2_CHANNEL_TX8B10BBYPASS1", + "RXPRBSSEL2": "GTPE2_CHANNEL_RXPRBSSEL2", + "RXADAPTSELTEST4": "GTPE2_CHANNEL_RXADAPTSELTEST4", + "TXCHARISK0": "GTPE2_CHANNEL_TXCHARISK0", + "PMARSVDIN0": "GTPE2_CHANNEL_PMARSVDIN0", + "TXPDELECIDLEMODE": "GTPE2_CHANNEL_TXPDELECIDLEMODE", + "RXADAPTSELTEST8": "GTPE2_CHANNEL_RXADAPTSELTEST8", + "TXCHARDISPMODE1": "GTPE2_CHANNEL_TXCHARDISPMODE1", + "TXPMARESETDONE": "GTPE2_CHANNEL_TXPMARESETDONE", + "RXBYTEISALIGNED": "GTPE2_CHANNEL_RXBYTEISALIGNED", + "DMONFIFORESET": "GTPE2_CHANNEL_DMONFIFORESET", + "RXPHSLIPMONITOR4": "GTPE2_CHANNEL_RXPHSLIPMONITOR4", + "TXDIFFPD": "GTPE2_CHANNEL_TXDIFFPD", + "RXOSINTSTROBE": "GTPE2_CHANNEL_RXOSINTSTROBE", + "PLL0CLK": "GTPE2_CHANNEL_PLL0CLK", + "SETERRSTATUS": "GTPE2_CHANNEL_SETERRSTATUS", + "TXPIPPMSTEPSIZE3": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE3", + "RXSTATUS2": "GTPE2_CHANNEL_RXSTATUS2", + "TX8B10BEN": "GTPE2_CHANNEL_TX8B10BEN", + "DMONITOROUT5": "GTPE2_CHANNEL_DMONITOROUT5", + "RXLPMHFOVRDEN": "GTPE2_CHANNEL_RXLPMHFOVRDEN", + "PCSRSVDOUT9": "GTPE2_CHANNEL_PCSRSVDOUT9", + "RXOUTCLKFABRIC": "GTPE2_CHANNEL_RXOUTCLKFABRIC", + "PCSRSVDOUT0": "GTPE2_CHANNEL_PCSRSVDOUT0", + "RXPHMONITOR4": "GTPE2_CHANNEL_RXPHMONITOR4", + "RXDATA3": "GTPE2_CHANNEL_RXDATA3", + "RXSYNCDONE": "GTPE2_CHANNEL_RXSYNCDONE", + "RXADAPTSELTEST9": "GTPE2_CHANNEL_RXADAPTSELTEST9", + "DRPADDR4": "GTPE2_CHANNEL_DRPADDR4", + "PCSRSVDOUT7": "GTPE2_CHANNEL_PCSRSVDOUT7", + "TXPIPPMSTEPSIZE1": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE1", + "RXPHMONITOR1": "GTPE2_CHANNEL_RXPHMONITOR1", + "TXPIPPMEN": "GTPE2_CHANNEL_TXPIPPMEN", + "TXCHARDISPVAL3": "GTPE2_CHANNEL_TXCHARDISPVAL3", + "RXUSRCLK2": "GTPE2_CHANNEL_RXUSRCLK2", + "RXDATAVALID1": "GTPE2_CHANNEL_RXDATAVALID1", + "RXLPMOSINTNTRLEN": "GTPE2_CHANNEL_RXLPMOSINTNTRLEN", + "GTRSVD5": "GTPE2_CHANNEL_GTRSVD5", + "DRPDO9": "GTPE2_CHANNEL_DRPDO9", + "EYESCANTRIGGER": "GTPE2_CHANNEL_EYESCANTRIGGER", + "SCANMODEB": "GTPE2_CHANNEL_SCANMODEB", + "DRPDO15": "GTPE2_CHANNEL_DRPDO15", + "TXPRBSSEL0": "GTPE2_CHANNEL_TXPRBSSEL0", + "DMONITOROUT3": "GTPE2_CHANNEL_DMONITOROUT3", + "TSTIN14": "GTPE2_CHANNEL_TSTIN14", + "TXUSERRDY": "GTPE2_CHANNEL_TXUSERRDY", + "DRPDO6": "GTPE2_CHANNEL_DRPDO6", + "RXDLYOVRDEN": "GTPE2_CHANNEL_RXDLYOVRDEN", + "DMONITOROUT6": "GTPE2_CHANNEL_DMONITOROUT6", + "RXLPMHFHOLD": "GTPE2_CHANNEL_RXLPMHFHOLD", + "RXCHARISK3": "GTPE2_CHANNEL_RXCHARISK3", + "PMASCANOUT3": "GTPE2_CHANNEL_PMASCANOUT3", + "TXDATA22": "GTPE2_CHANNEL_TXDATA22", + "RXDISPERR3": "GTPE2_CHANNEL_RXDISPERR3", + "TXOUTCLK": "GTPE2_CHANNEL_GTTXOUTCLK_3", + "RXCLKCORCNT1": "GTPE2_CHANNEL_RXCLKCORCNT1", + "RXOSINTID01": "GTPE2_CHANNEL_RXOSINTID01", + "GTRSVD10": "GTPE2_CHANNEL_GTRSVD10", + "TXCHARDISPVAL1": "GTPE2_CHANNEL_TXCHARDISPVAL1", + "RXCDRLOCK": "GTPE2_CHANNEL_RXCDRLOCK", + "RXPHALIGN": "GTPE2_CHANNEL_RXPHALIGN", + "RXNOTINTABLE1": "GTPE2_CHANNEL_RXNOTINTABLE1", + "PMASCANIN3": "GTPE2_CHANNEL_PMASCANIN3", + "RXCDRRESETRSV": "GTPE2_CHANNEL_RXCDRRESETRSV", + "RXBUFRESET": "GTPE2_CHANNEL_RXBUFRESET", + "RXPHMONITOR3": "GTPE2_CHANNEL_RXPHMONITOR3", + "TXPIPPMSEL": "GTPE2_CHANNEL_TXPIPPMSEL", + "RXDATA20": "GTPE2_CHANNEL_RXDATA20", + "DRPDO14": "GTPE2_CHANNEL_DRPDO14", + "TXSYNCDONE": "GTPE2_CHANNEL_TXSYNCDONE", + "PCSRSVDOUT4": "GTPE2_CHANNEL_PCSRSVDOUT4", + "RXELECIDLEMODE0": "GTPE2_CHANNEL_RXELECIDLEMODE0", + "PMASCANIN5": "GTPE2_CHANNEL_PMASCANIN5", + "TXCOMFINISH": "GTPE2_CHANNEL_TXCOMFINISH", + "TXDATA9": "GTPE2_CHANNEL_TXDATA9", + "DRPADDR1": "GTPE2_CHANNEL_DRPADDR1", + "TXDATA11": "GTPE2_CHANNEL_TXDATA11", + "TXRUNDISP0": "GTPE2_CHANNEL_TXRUNDISP0", + "TXBUFSTATUS0": "GTPE2_CHANNEL_TXBUFSTATUS0", + "RXPHSLIPMONITOR1": "GTPE2_CHANNEL_RXPHSLIPMONITOR1", + "GTTXRESET": "GTPE2_CHANNEL_GTTXRESET", + "RXELECIDLEMODE1": "GTPE2_CHANNEL_RXELECIDLEMODE1", + "RXDATA13": "GTPE2_CHANNEL_RXDATA13", + "TXDATA27": "GTPE2_CHANNEL_TXDATA27", + "RXSYSCLKSEL0": "GTPE2_CHANNEL_RXSYSCLKSEL0", + "PMASCANCLK0": "GTPE2_CHANNEL_PMASCANCLK0", + "TXPRECURSOR2": "GTPE2_CHANNEL_TXPRECURSOR2", + "TXCOMWAKE": "GTPE2_CHANNEL_TXCOMWAKE", + "RXDATA0": "GTPE2_CHANNEL_RXDATA0", + "GTPTXN": "GTPE2_CHANNEL_TXN", + "TXDLYOVRDEN": "GTPE2_CHANNEL_TXDLYOVRDEN", + "RXOSHOLD": "GTPE2_CHANNEL_RXOSHOLD", + "RXLPMRESET": "GTPE2_CHANNEL_RXLPMRESET", + "PCSRSVDIN4": "GTPE2_CHANNEL_PCSRSVDIN4", + "TXSYNCIN": "GTPE2_CHANNEL_TXSYNCIN", + "RXCHBONDO3": "GTPE2_CHANNEL_RXCHBONDO3", + "PCSRSVDIN7": "GTPE2_CHANNEL_PCSRSVDIN7", + "TSTIN3": "GTPE2_CHANNEL_TSTIN3", + "TXGEARBOXREADY": "GTPE2_CHANNEL_TXGEARBOXREADY", + "GTRSVD1": "GTPE2_CHANNEL_GTRSVD1", + "RXDATA22": "GTPE2_CHANNEL_RXDATA22", + "SCANIN4": "GTPE2_CHANNEL_SCANIN4", + "DRPDI12": "GTPE2_CHANNEL_DRPDI12", + "TXDATA31": "GTPE2_CHANNEL_TXDATA31", + "RXSTARTOFSEQ1": "GTPE2_CHANNEL_RXSTARTOFSEQ1", + "PMASCANIN6": "GTPE2_CHANNEL_PMASCANIN6", + "TXRESETDONE": "GTPE2_CHANNEL_TXRESETDONE", + "TXHEADER1": "GTPE2_CHANNEL_TXHEADER1", + "RXDATA2": "GTPE2_CHANNEL_RXDATA2", + "TXRUNDISP2": "GTPE2_CHANNEL_TXRUNDISP2", + "DRPADDR3": "GTPE2_CHANNEL_DRPADDR3", + "TXDATA13": "GTPE2_CHANNEL_TXDATA13", + "TXPMARESET": "GTPE2_CHANNEL_TXPMARESET", + "RXRATE2": "GTPE2_CHANNEL_RXRATE2", + "RXOOBRESET": "GTPE2_CHANNEL_RXOOBRESET", + "DRPADDR2": "GTPE2_CHANNEL_DRPADDR2", + "DRPDO0": "GTPE2_CHANNEL_DRPDO0", + "RXDATA21": "GTPE2_CHANNEL_RXDATA21", + "GTRSVD14": "GTPE2_CHANNEL_GTRSVD14", + "TXDATA23": "GTPE2_CHANNEL_TXDATA23", + "SIGVALIDCLK": "GTPE2_CHANNEL_SIGVALIDCLK", + "PCSRSVDOUT10": "GTPE2_CHANNEL_PCSRSVDOUT10", + "RXRATE1": "GTPE2_CHANNEL_RXRATE1", + "DRPCLK": "GTPE2_CHANNEL_DRPCLK", + "RXCHBONDO1": "GTPE2_CHANNEL_RXCHBONDO1", + "TXPRECURSOR0": "GTPE2_CHANNEL_TXPRECURSOR0", + "RXDATA25": "GTPE2_CHANNEL_RXDATA25", + "DMONITORCLK": "GTPE2_CHANNEL_DMONITORCLK", + "RXCHARISCOMMA3": "GTPE2_CHANNEL_RXCHARISCOMMA3", + "RXADAPTSELTEST12": "GTPE2_CHANNEL_RXADAPTSELTEST12", + "DRPRDY": "GTPE2_CHANNEL_DRPRDY", + "RXOUTCLKSEL2": "GTPE2_CHANNEL_RXOUTCLKSEL2", + "RXOSINTPD": "GTPE2_CHANNEL_RXOSINTPD", + "DMONITOROUT11": "GTPE2_CHANNEL_DMONITOROUT11", + "RXCHANREALIGN": "GTPE2_CHANNEL_RXCHANREALIGN", + "TXOUTCLKPCS": "GTPE2_CHANNEL_TXOUTCLKPCS", + "RXOSINTCFG3": "GTPE2_CHANNEL_RXOSINTCFG3", + "DRPDO4": "GTPE2_CHANNEL_DRPDO4", + "RXBUFSTATUS0": "GTPE2_CHANNEL_RXBUFSTATUS0", + "RXCHBONDI1": "GTPE2_CHANNEL_RXCHBONDI1", + "DRPDI5": "GTPE2_CHANNEL_DRPDI5", + "TXCHARISK2": "GTPE2_CHANNEL_TXCHARISK2", + "DMONITOROUT1": "GTPE2_CHANNEL_DMONITOROUT1", + "TXOUTCLKSEL2": "GTPE2_CHANNEL_TXOUTCLKSEL2", + "TXPOSTCURSOR4": "GTPE2_CHANNEL_TXPOSTCURSOR4", + "DRPADDR0": "GTPE2_CHANNEL_DRPADDR0", + "RXDLYSRESET": "GTPE2_CHANNEL_RXDLYSRESET", + "RXSTATUS1": "GTPE2_CHANNEL_RXSTATUS1", + "RXDFEXYDEN": "GTPE2_CHANNEL_RXDFEXYDEN", + "TXPHDLYTSTCLK": "GTPE2_CHANNEL_TXPHDLYTSTCLK", + "RXPRBSERR": "GTPE2_CHANNEL_RXPRBSERR", + "RXCOMMADET": "GTPE2_CHANNEL_RXCOMMADET", + "TXSYNCMODE": "GTPE2_CHANNEL_TXSYNCMODE", + "RXADAPTSELTEST10": "GTPE2_CHANNEL_RXADAPTSELTEST10", + "RXOSINTSTROBESTARTED": "GTPE2_CHANNEL_RXOSINTSTROBESTARTED", + "TXPCSRESET": "GTPE2_CHANNEL_TXPCSRESET", + "PCSRSVDIN13": "GTPE2_CHANNEL_PCSRSVDIN13", + "TXUSRCLK": "GTPE2_CHANNEL_TXUSRCLK", + "RXRATEDONE": "GTPE2_CHANNEL_RXRATEDONE", + "PLL1CLK": "GTPE2_CHANNEL_PLL1CLK", + "TXSYNCOUT": "GTPE2_CHANNEL_TXSYNCOUT", + "TSTPD0": "GTPE2_CHANNEL_TSTPD0", + "RXOUTCLKPCS": "GTPE2_CHANNEL_RXOUTCLKPCS", + "PMASCANIN4": "GTPE2_CHANNEL_PMASCANIN4", + "TXDATA14": "GTPE2_CHANNEL_TXDATA14", + "PCSRSVDOUT5": "GTPE2_CHANNEL_PCSRSVDOUT5", + "SCANIN2": "GTPE2_CHANNEL_SCANIN2", + "DRPDI15": "GTPE2_CHANNEL_DRPDI15", + "TSTIN8": "GTPE2_CHANNEL_TSTIN8", + "SCANOUT2": "GTPE2_CHANNEL_SCANOUT2", + "RXCHBONDI0": "GTPE2_CHANNEL_RXCHBONDI0", + "RXDISPERR2": "GTPE2_CHANNEL_RXDISPERR2", + "TXPRECURSOR3": "GTPE2_CHANNEL_TXPRECURSOR3", + "LOOPBACK0": "GTPE2_CHANNEL_LOOPBACK0", + "RXPD1": "GTPE2_CHANNEL_RXPD1", + "RXDLYSRESETDONE": "GTPE2_CHANNEL_RXDLYSRESETDONE", + "TXDETECTRX": "GTPE2_CHANNEL_TXDETECTRX", + "TXMAINCURSOR6": "GTPE2_CHANNEL_TXMAINCURSOR6", + "RXOSINTDONE": "GTPE2_CHANNEL_RXOSINTDONE", + "RXPHSLIPMONITOR2": "GTPE2_CHANNEL_RXPHSLIPMONITOR2", + "RXHEADER2": "GTPE2_CHANNEL_RXHEADER2", + "RXDLYEN": "GTPE2_CHANNEL_RXDLYEN", + "RXOSINTTESTOVRDEN": "GTPE2_CHANNEL_RXOSINTTESTOVRDEN", + "RXDATA31": "GTPE2_CHANNEL_RXDATA31", + "GTRESETSEL": "GTPE2_CHANNEL_GTRESETSEL", + "TXPOLARITY": "GTPE2_CHANNEL_TXPOLARITY", + "RXDATA12": "GTPE2_CHANNEL_RXDATA12", + "DRPDI14": "GTPE2_CHANNEL_DRPDI14", + "RXDDIEN": "GTPE2_CHANNEL_RXDDIEN", + "RXOSINTSTROBEDONE": "GTPE2_CHANNEL_RXOSINTSTROBEDONE", + "DRPEN": "GTPE2_CHANNEL_DRPEN", + "RXCDRFREQRESET": "GTPE2_CHANNEL_RXCDRFREQRESET", + "TXCHARDISPVAL2": "GTPE2_CHANNEL_TXCHARDISPVAL2", + "TXOUTCLKFABRIC": "GTPE2_CHANNEL_TXOUTCLKFABRIC", + "RXSYNCMODE": "GTPE2_CHANNEL_RXSYNCMODE", + "DRPDI1": "GTPE2_CHANNEL_DRPDI1", + "PCSRSVDIN2": "GTPE2_CHANNEL_PCSRSVDIN2", + "RXOSINTID02": "GTPE2_CHANNEL_RXOSINTID02", + "TXMARGIN1": "GTPE2_CHANNEL_TXMARGIN1", + "TXDIFFCTRL0": "GTPE2_CHANNEL_TXDIFFCTRL0", + "RXBYTEREALIGN": "GTPE2_CHANNEL_RXBYTEREALIGN", + "RXDATA29": "GTPE2_CHANNEL_RXDATA29", + "TXMAINCURSOR2": "GTPE2_CHANNEL_TXMAINCURSOR2", + "RXPHSLIPMONITOR0": "GTPE2_CHANNEL_RXPHSLIPMONITOR0", + "TSTIN18": "GTPE2_CHANNEL_TSTIN18", + "TXDATA18": "GTPE2_CHANNEL_TXDATA18", + "TXPOSTCURSOR1": "GTPE2_CHANNEL_TXPOSTCURSOR1", + "TSTPD1": "GTPE2_CHANNEL_TSTPD1", + "TXDATA5": "GTPE2_CHANNEL_TXDATA5", + "RXLPMLFOVRDEN": "GTPE2_CHANNEL_RXLPMLFOVRDEN", + "PCSRSVDIN3": "GTPE2_CHANNEL_PCSRSVDIN3", + "RXDLYTESTENB": "GTPE2_CHANNEL_RXDLYTESTENB", + "SCANENB": "GTPE2_CHANNEL_SCANENB", + "RXPCSRESET": "GTPE2_CHANNEL_RXPCSRESET", + "RXDATA14": "GTPE2_CHANNEL_RXDATA14", + "RXCHBONDLEVEL0": "GTPE2_CHANNEL_RXCHBONDLEVEL0", + "TSTIN2": "GTPE2_CHANNEL_TSTIN2", + "PHYSTATUS": "GTPE2_CHANNEL_PHYSTATUS", + "RXDATAVALID0": "GTPE2_CHANNEL_RXDATAVALID0", + "SCANOUT4": "GTPE2_CHANNEL_SCANOUT4", + "PMASCANMODEB": "GTPE2_CHANNEL_PMASCANMODEB", + "TXPISOPD": "GTPE2_CHANNEL_TXPISOPD", + "RXMCOMMAALIGNEN": "GTPE2_CHANNEL_RXMCOMMAALIGNEN", + "TXDLYUPDOWN": "GTPE2_CHANNEL_TXDLYUPDOWN", + "EYESCANDATAERROR": "GTPE2_CHANNEL_EYESCANDATAERROR", + "TXDATA17": "GTPE2_CHANNEL_TXDATA17", + "DRPDO3": "GTPE2_CHANNEL_DRPDO3", + "PCSRSVDOUT8": "GTPE2_CHANNEL_PCSRSVDOUT8", + "TXCHARDISPVAL0": "GTPE2_CHANNEL_TXCHARDISPVAL0", + "RXDEBUGPULSE": "GTPE2_CHANNEL_RXDEBUGPULSE", + "PCSRSVDIN5": "GTPE2_CHANNEL_PCSRSVDIN5", + "PLL1REFCLK": "GTPE2_CHANNEL_PLL1REFCLK", + "DRPDI0": "GTPE2_CHANNEL_DRPDI0", + "TXDATA19": "GTPE2_CHANNEL_TXDATA19", + "RXELECIDLE": "GTPE2_CHANNEL_RXELECIDLE", + "TX8B10BBYPASS2": "GTPE2_CHANNEL_TX8B10BBYPASS2", + "PCSRSVDOUT6": "GTPE2_CHANNEL_PCSRSVDOUT6", + "TXPRECURSOR1": "GTPE2_CHANNEL_TXPRECURSOR1", + "RXADAPTSELTEST1": "GTPE2_CHANNEL_RXADAPTSELTEST1", + "RXLPMLFHOLD": "GTPE2_CHANNEL_RXLPMLFHOLD", + "TXDATA16": "GTPE2_CHANNEL_TXDATA16", + "GTRSVD7": "GTPE2_CHANNEL_GTRSVD7", + "TXDATA8": "GTPE2_CHANNEL_TXDATA8", + "SCANIN3": "GTPE2_CHANNEL_SCANIN3", + "TXPRBSFORCEERR": "GTPE2_CHANNEL_TXPRBSFORCEERR", + "TXRUNDISP1": "GTPE2_CHANNEL_TXRUNDISP1", + "TSTIN10": "GTPE2_CHANNEL_TSTIN10", + "DRPADDR8": "GTPE2_CHANNEL_DRPADDR8", + "RXSTATUS0": "GTPE2_CHANNEL_RXSTATUS0", + "TXSEQUENCE1": "GTPE2_CHANNEL_TXSEQUENCE1", + "GTRSVD3": "GTPE2_CHANNEL_GTRSVD3", + "RXDATA17": "GTPE2_CHANNEL_RXDATA17", + "RXPHOVRDEN": "GTPE2_CHANNEL_RXPHOVRDEN", + "TXSWING": "GTPE2_CHANNEL_TXSWING", + "PMASCANIN2": "GTPE2_CHANNEL_PMASCANIN2", + "PMASCANIN1": "GTPE2_CHANNEL_PMASCANIN1", + "RXRESETDONE": "GTPE2_CHANNEL_RXRESETDONE", + "TXDATA0": "GTPE2_CHANNEL_TXDATA0", + "RXCHBONDEN": "GTPE2_CHANNEL_RXCHBONDEN", + "RXDATA9": "GTPE2_CHANNEL_RXDATA9", + "RXCHARISK1": "GTPE2_CHANNEL_RXCHARISK1", + "DRPADDR6": "GTPE2_CHANNEL_DRPADDR6", + "TXRATEDONE": "GTPE2_CHANNEL_TXRATEDONE", + "RXOUTCLKSEL0": "GTPE2_CHANNEL_RXOUTCLKSEL0", + "TXDATA1": "GTPE2_CHANNEL_TXDATA1", + "TSTPD2": "GTPE2_CHANNEL_TSTPD2", + "RXRATEMODE": "GTPE2_CHANNEL_RXRATEMODE", + "RXOSINTEN": "GTPE2_CHANNEL_RXOSINTEN", + "PMASCANOUT0": "GTPE2_CHANNEL_PMASCANOUT0", + "DRPDO12": "GTPE2_CHANNEL_DRPDO12", + "TXPIPPMSTEPSIZE2": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE2", + "RXPHALIGNEN": "GTPE2_CHANNEL_RXPHALIGNEN", + "GTRSVD4": "GTPE2_CHANNEL_GTRSVD4", + "TSTIN17": "GTPE2_CHANNEL_TSTIN17", + "TXHEADER0": "GTPE2_CHANNEL_TXHEADER0", + "RXOSINTID00": "GTPE2_CHANNEL_RXOSINTID00", + "RXCHARISCOMMA2": "GTPE2_CHANNEL_RXCHARISCOMMA2", + "RXADAPTSELTEST5": "GTPE2_CHANNEL_RXADAPTSELTEST5", + "DRPDI7": "GTPE2_CHANNEL_DRPDI7", + "DRPDI6": "GTPE2_CHANNEL_DRPDI6", + "DMONITOROUT12": "GTPE2_CHANNEL_DMONITOROUT12", + "TXDATA10": "GTPE2_CHANNEL_TXDATA10", + "PMASCANENB": "GTPE2_CHANNEL_PMASCANENB", + "TXCHARDISPMODE2": "GTPE2_CHANNEL_TXCHARDISPMODE2", + "PMARSVDIN2": "GTPE2_CHANNEL_PMARSVDIN2", + "RXCHANISALIGNED": "GTPE2_CHANNEL_RXCHANISALIGNED", + "GTPTXP": "GTPE2_CHANNEL_TXP", + "RXBUFSTATUS2": "GTPE2_CHANNEL_RXBUFSTATUS2", + "RXPHDLYRESET": "GTPE2_CHANNEL_RXPHDLYRESET", + "PMASCANCLK1": "GTPE2_CHANNEL_PMASCANCLK1", + "TSTPD4": "GTPE2_CHANNEL_TSTPD4", + "TXPRECURSOR4": "GTPE2_CHANNEL_TXPRECURSOR4", + "DMONITOROUT10": "GTPE2_CHANNEL_DMONITOROUT10", + "DRPADDR7": "GTPE2_CHANNEL_DRPADDR7", + "DMONITOROUT0": "GTPE2_CHANNEL_DMONITOROUT0", + "TXDATA24": "GTPE2_CHANNEL_TXDATA24", + "TXDIFFCTRL1": "GTPE2_CHANNEL_TXDIFFCTRL1", + "TXDATA28": "GTPE2_CHANNEL_TXDATA28", + "TXSEQUENCE4": "GTPE2_CHANNEL_TXSEQUENCE4", + "DMONITOROUT4": "GTPE2_CHANNEL_DMONITOROUT4", + "TXBUFDIFFCTRL1": "GTPE2_CHANNEL_TXBUFDIFFCTRL1", + "DRPDO7": "GTPE2_CHANNEL_DRPDO7", + "EYESCANRESET": "GTPE2_CHANNEL_EYESCANRESET", + "RXPD0": "GTPE2_CHANNEL_RXPD0", + "DRPADDR5": "GTPE2_CHANNEL_DRPADDR5", + "RXOUTCLK": "GTPE2_CHANNEL_GTRXOUTCLK_3", + "TXSYNCALLIN": "GTPE2_CHANNEL_TXSYNCALLIN", + "RXHEADER0": "GTPE2_CHANNEL_RXHEADER0", + "TSTIN0": "GTPE2_CHANNEL_TSTIN0", + "RXHEADER1": "GTPE2_CHANNEL_RXHEADER1", + "DRPDO2": "GTPE2_CHANNEL_DRPDO2", + "TXDLYSRESET": "GTPE2_CHANNEL_TXDLYSRESET", + "TX8B10BBYPASS0": "GTPE2_CHANNEL_TX8B10BBYPASS0", + "TSTIN5": "GTPE2_CHANNEL_TSTIN5", + "DRPDO8": "GTPE2_CHANNEL_DRPDO8", + "RXCHARISK0": "GTPE2_CHANNEL_RXCHARISK0", + "RXDATA10": "GTPE2_CHANNEL_RXDATA10", + "RXOSINTOVRDEN": "GTPE2_CHANNEL_RXOSINTOVRDEN", + "PMARSVDOUT0": "GTPE2_CHANNEL_PMARSVDOUT0", + "RXDATA27": "GTPE2_CHANNEL_RXDATA27", + "GTPRXN": "GTPE2_CHANNEL_RXN", + "DRPDO1": "GTPE2_CHANNEL_DRPDO1", + "PCSRSVDIN10": "GTPE2_CHANNEL_PCSRSVDIN10", + "DRPDO11": "GTPE2_CHANNEL_DRPDO11", + "DRPDI3": "GTPE2_CHANNEL_DRPDI3", + "GTRSVD13": "GTPE2_CHANNEL_GTRSVD13", + "TSTIN13": "GTPE2_CHANNEL_TSTIN13", + "TXDATA25": "GTPE2_CHANNEL_TXDATA25", + "TXINHIBIT": "GTPE2_CHANNEL_TXINHIBIT", + "PCSRSVDOUT1": "GTPE2_CHANNEL_PCSRSVDOUT1", + "PCSRSVDOUT15": "GTPE2_CHANNEL_PCSRSVDOUT15", + "RXCDRRESET": "GTPE2_CHANNEL_RXCDRRESET", + "TXBUFDIFFCTRL2": "GTPE2_CHANNEL_TXBUFDIFFCTRL2", + "PCSRSVDOUT12": "GTPE2_CHANNEL_PCSRSVDOUT12", + "CLKRSVD0": "GTPE2_CHANNEL_CLKRSVD0", + "RXCHBONDMASTER": "GTPE2_CHANNEL_RXCHBONDMASTER", + "TXDIFFCTRL2": "GTPE2_CHANNEL_TXDIFFCTRL2", + "RXPHSLIPMONITOR3": "GTPE2_CHANNEL_RXPHSLIPMONITOR3", + "TXSTARTSEQ": "GTPE2_CHANNEL_TXSTARTSEQ", + "TXCHARISK1": "GTPE2_CHANNEL_TXCHARISK1", + "RXCHBONDLEVEL1": "GTPE2_CHANNEL_RXCHBONDLEVEL1", + "DRPDO13": "GTPE2_CHANNEL_DRPDO13", + "SCANIN0": "GTPE2_CHANNEL_SCANIN0", + "TXDATA12": "GTPE2_CHANNEL_TXDATA12", + "RXDATA5": "GTPE2_CHANNEL_RXDATA5", + "TXPOSTCURSOR0": "GTPE2_CHANNEL_TXPOSTCURSOR0", + "RXPHMONITOR0": "GTPE2_CHANNEL_RXPHMONITOR0", + "TXSEQUENCE6": "GTPE2_CHANNEL_TXSEQUENCE6", + "RXCHARISCOMMA1": "GTPE2_CHANNEL_RXCHARISCOMMA1", + "RXDATA30": "GTPE2_CHANNEL_RXDATA30", + "RXCHBONDO2": "GTPE2_CHANNEL_RXCHBONDO2", + "RXDATA23": "GTPE2_CHANNEL_RXDATA23", + "TXRATE1": "GTPE2_CHANNEL_TXRATE1", + "RXADAPTSELTEST11": "GTPE2_CHANNEL_RXADAPTSELTEST11", + "PLL0REFCLK": "GTPE2_CHANNEL_PLL0REFCLK", + "RESETOVRD": "GTPE2_CHANNEL_RESETOVRD", + "TXBUFSTATUS1": "GTPE2_CHANNEL_TXBUFSTATUS1", + "RXSTARTOFSEQ0": "GTPE2_CHANNEL_RXSTARTOFSEQ0", + "PMASCANOUT2": "GTPE2_CHANNEL_PMASCANOUT2", + "RXDATA11": "GTPE2_CHANNEL_RXDATA11", + "TXMAINCURSOR4": "GTPE2_CHANNEL_TXMAINCURSOR4", + "PMASCANOUT5": "GTPE2_CHANNEL_PMASCANOUT5", + "RXOSINTHOLD": "GTPE2_CHANNEL_RXOSINTHOLD", + "TXPHALIGN": "GTPE2_CHANNEL_TXPHALIGN", + "DRPDI2": "GTPE2_CHANNEL_DRPDI2", + "RXCHBONDI2": "GTPE2_CHANNEL_RXCHBONDI2", + "TXPHDLYRESET": "GTPE2_CHANNEL_TXPHDLYRESET", + "RXPMARESET": "GTPE2_CHANNEL_RXPMARESET", + "RXSYNCIN": "GTPE2_CHANNEL_RXSYNCIN", + "RXDATA8": "GTPE2_CHANNEL_RXDATA8", + "TXDEEMPH": "GTPE2_CHANNEL_TXDEEMPH", + "RXPHALIGNDONE": "GTPE2_CHANNEL_RXPHALIGNDONE", + "RXOSOVRDEN": "GTPE2_CHANNEL_RXOSOVRDEN", + "TSTIN19": "GTPE2_CHANNEL_TSTIN19", + "TXDATA15": "GTPE2_CHANNEL_TXDATA15", + "RXPMARESETDONE": "GTPE2_CHANNEL_RXPMARESETDONE", + "RXDISPERR0": "GTPE2_CHANNEL_RXDISPERR0", + "RXSYSCLKSEL1": "GTPE2_CHANNEL_RXSYSCLKSEL1", + "GTRSVD11": "GTPE2_CHANNEL_GTRSVD11", + "DRPDO10": "GTPE2_CHANNEL_DRPDO10", + "PCSRSVDOUT3": "GTPE2_CHANNEL_PCSRSVDOUT3", + "SCANOUT3": "GTPE2_CHANNEL_SCANOUT3", + "RXDATA7": "GTPE2_CHANNEL_RXDATA7", + "TXDLYTESTENB": "GTPE2_CHANNEL_TXDLYTESTENB", + "RXOSINTID03": "GTPE2_CHANNEL_RXOSINTID03", + "TXPRECURSORINV": "GTPE2_CHANNEL_TXPRECURSORINV", + "TXPIPPMSTEPSIZE0": "GTPE2_CHANNEL_TXPIPPMSTEPSIZE0", + "TSTIN15": "GTPE2_CHANNEL_TSTIN15", + "PMASCANCLK3": "GTPE2_CHANNEL_PMASCANCLK3", + "PMARSVDIN1": "GTPE2_CHANNEL_PMARSVDIN1", + "RXCHBONDLEVEL2": "GTPE2_CHANNEL_RXCHBONDLEVEL2", + "PCSRSVDIN1": "GTPE2_CHANNEL_PCSRSVDIN1", + "RXNOTINTABLE2": "GTPE2_CHANNEL_RXNOTINTABLE2", + "TXDATA30": "GTPE2_CHANNEL_TXDATA30", + "TSTPDOVRDB": "GTPE2_CHANNEL_TSTPDOVRDB", + "RXOSINTSTARTED": "GTPE2_CHANNEL_RXOSINTSTARTED", + "TSTIN6": "GTPE2_CHANNEL_TSTIN6", + "PMASCANOUT6": "GTPE2_CHANNEL_PMASCANOUT6", + "TXSEQUENCE0": "GTPE2_CHANNEL_TXSEQUENCE0", + "SCANIN5": "GTPE2_CHANNEL_SCANIN5", + "RXDATA1": "GTPE2_CHANNEL_RXDATA1", + "RXADAPTSELTEST13": "GTPE2_CHANNEL_RXADAPTSELTEST13", + "RXDATA24": "GTPE2_CHANNEL_RXDATA24", + "TXDLYSRESETDONE": "GTPE2_CHANNEL_TXDLYSRESETDONE", + "TXDATA20": "GTPE2_CHANNEL_TXDATA20", + "SCANCLK": "GTPE2_CHANNEL_SCANCLK", + "RXPRBSSEL0": "GTPE2_CHANNEL_RXPRBSSEL0", + "TXCOMINIT": "GTPE2_CHANNEL_TXCOMINIT", + "RXUSERRDY": "GTPE2_CHANNEL_RXUSERRDY", + "TXSEQUENCE3": "GTPE2_CHANNEL_TXSEQUENCE3", + "TXOUTCLKSEL0": "GTPE2_CHANNEL_TXOUTCLKSEL0", + "PMASCANOUT4": "GTPE2_CHANNEL_PMASCANOUT4", + "TXDATA4": "GTPE2_CHANNEL_TXDATA4", + "TX8B10BBYPASS3": "GTPE2_CHANNEL_TX8B10BBYPASS3", + "SCANIN1": "GTPE2_CHANNEL_SCANIN1", + "DRPWE": "GTPE2_CHANNEL_DRPWE", + "TXDATA7": "GTPE2_CHANNEL_TXDATA7", + "TXPRBSSEL2": "GTPE2_CHANNEL_TXPRBSSEL2", + "RXDISPERR1": "GTPE2_CHANNEL_RXDISPERR1", + "PCSRSVDIN0": "GTPE2_CHANNEL_PCSRSVDIN0", + "TXRATEMODE": "GTPE2_CHANNEL_TXRATEMODE", + "RXRATE0": "GTPE2_CHANNEL_RXRATE0", + "RXOSINTNTRLEN": "GTPE2_CHANNEL_RXOSINTNTRLEN", + "TXSEQUENCE5": "GTPE2_CHANNEL_TXSEQUENCE5", + "RXDATA4": "GTPE2_CHANNEL_RXDATA4", + "TXPHINITDONE": "GTPE2_CHANNEL_TXPHINITDONE", + "DMONITOROUT8": "GTPE2_CHANNEL_DMONITOROUT8", + "RXDLYBYPASS": "GTPE2_CHANNEL_RXDLYBYPASS", + "RXPRBSCNTRESET": "GTPE2_CHANNEL_RXPRBSCNTRESET", + "RXOSINTCFG1": "GTPE2_CHANNEL_RXOSINTCFG1", + "DRPDI8": "GTPE2_CHANNEL_DRPDI8", + "PCSRSVDIN15": "GTPE2_CHANNEL_PCSRSVDIN15", + "RXDATA6": "GTPE2_CHANNEL_RXDATA6", + "RXDATA28": "GTPE2_CHANNEL_RXDATA28", + "TXPOSTCURSOR2": "GTPE2_CHANNEL_TXPOSTCURSOR2", + "DRPDI11": "GTPE2_CHANNEL_DRPDI11", + "RXADAPTSELTEST2": "GTPE2_CHANNEL_RXADAPTSELTEST2", + "PCSRSVDIN14": "GTPE2_CHANNEL_PCSRSVDIN14", + "RXDATA26": "GTPE2_CHANNEL_RXDATA26", + "DMONITOROUT14": "GTPE2_CHANNEL_DMONITOROUT14" + }, + "type": "GTPE2_CHANNEL", + "prefix": "GTPE2_CHANNEL", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "O": "GTPE2_CHANNEL_RXN_PAD" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y27", + "x_coord": 1, + "y_coord": 27 + }, + { + "site_pins": { + "O": "GTPE2_CHANNEL_RXP_PAD" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y28", + "x_coord": 1, + "y_coord": 28 + }, + { + "site_pins": { + "I": "GTPE2_CHANNEL_TXN_PAD" + }, + "type": "OPAD", + "prefix": "OPAD", + "name": "X0Y3", + "x_coord": 0, + "y_coord": 3 + }, + { + "site_pins": { + "I": "GTPE2_CHANNEL_TXP_PAD" + }, + "type": "OPAD", + "prefix": "OPAD", + "name": "X0Y4", + "x_coord": 0, + "y_coord": 4 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_GTP_COMMON.json b/artix7/tile_type_GTP_COMMON.json index df48913..28416e9 100644 --- a/artix7/tile_type_GTP_COMMON.json +++ b/artix7/tile_type_GTP_COMMON.json @@ -1,2125 +1,2125 @@ { - "wires": [ - "GTPE2_COMMON_PMASCANOUT0", - "GTPE2_LOGIC_OUTS_B5_4", - "GTPE2_IMUX18_2", - "GTPE2_LOGIC_OUTS_B1_3", - "GTPE2_IMUX26_4", - "GTPE2_IMUX37_1", - "GTPE2_COMMON_PMARSVDOUT5", - "GTPE2_COMMON_PLL0PD", - "GTPE2_COMMON_DRPADDR3", - "GTPE2_FAN1_0", - "GTPE2_CLK1_3", - "GTPE2_COMMON_DRPDO15", - "GTPE2_IMUX14_5", - "GTPE2_LOGIC_OUTS_B13_2", - "GTPE2_LOGIC_OUTS_B18_1", - "GTPE2_FAN3_5", - "GTPE2_COMMON_PLL0REFCLKLOST", - "GTPE2_BYP5_3", - "GTPE2_LOGIC_OUTS_B19_5", - "GTPE2_COMMON_PLL1LOCKDETCLK", - "GTPE2_COMMON_BGRCALOVRD1", - "GTPE2_IMUX28_4", - "GTPE2_IMUX34_0", - "GTPE2_IMUX39_0", - "GTPE2_LOGIC_OUTS_B10_3", - "GTPE2_BYP6_4", - "GTPE2_LOGIC_OUTS_B2_2", - "GTPE2_COMMON_DRPDO5", - "GTPE2_LOGIC_OUTS_B5_1", - "GTPE2_COMMON_TXOUTCLK_3", - "GTPE2_IMUX30_2", - "GTPE2_LOGIC_OUTS_B10_4", - "GTPE2_IMUX18_1", - "GTPE2_COMMON_BGBYPASSB", - "GTPE2_IMUX6_4", - "GTPE2_IMUX21_5", - "GTPE2_COMMON_MGT_CLK9", - "GTPE2_BYP4_3", - "GTPE2_COMMON_PLL1LOCK", - "GTPE2_LOGIC_OUTS_B10_0", - "GTPE2_LOGIC_OUTS_B9_4", - "GTPE2_IMUX8_3", - "GTPE2_FAN2_1", - "GTPE2_LOGIC_OUTS_B10_1", - "GTPE2_CTRL1_2", - "GTPE2_LOGIC_OUTS_B18_2", - "GTPE2_IMUX32_4", - "GTPE2_COMMON_PLLRSVD19", - "GTPE2_LOGIC_OUTS_B12_1", - "GTPE2_COMMON_PLLRSVD24", - "GTPE2_IMUX9_1", - "GTPE2_COMMON_DRPDO12", - "GTPE2_LOGIC_OUTS_B15_5", - "GTPE2_FAN0_3", - "GTPE2_CLK0_4", - "GTPE2_COMMON_PMARSVDOUT14", - "GTPE2_BYP2_1", - "GTPE2_IMUX14_4", - "GTPE2_LOGIC_OUTS_B23_2", - "GTPE2_FAN2_5", - "GTPE2_COMMON_DMONITOROUT1", - "GTPE2_IMUX15_1", - "GTPE2_COMMON_DRPDO6", - "GTPE2_IMUX35_1", - "GTPE2_COMMON_PMARSVDOUT9", - "GTPE2_IMUX40_2", - "GTPE2_IMUX8_2", - "GTPE2_IMUX47_4", - "GTPE2_FAN3_0", - "GTPE2_COMMON_DRPADDR4", - "GTPE2_FAN6_0", - "GTPE2_IMUX36_2", - "GTPE2_FAN3_3", - "GTPE2_LOGIC_OUTS_B11_3", - "GTPE2_LOGIC_OUTS_B14_5", - "GTPE2_CTRL0_1", - "GTPE2_COMMON_PMARSVDOUT0", - "GTPE2_IMUX10_2", - "GTPE2_IMUX2_1", - "GTPE2_COMMON_DRPDI13", - "GTPE2_IMUX0_3", - "GTPE2_BYP7_5", - "GTPE2_COMMON_PLLRSVD110", - "GTPE2_IMUX4_4", - "GTPE2_LOGIC_OUTS_B20_1", - "GTPE2_LOGIC_OUTS_B19_0", - "GTPE2_LOGIC_OUTS_B17_0", - "GTPE2_IMUX7_1", - "GTPE2_BYP6_1", - "GTPE2_IMUX29_3", - "GTPE2_COMMON_DRPDI1", - "GTPE2_IMUX27_2", - "GTPE2_IMUX0_1", - "GTPE2_IMUX46_2", - "GTPE2_IMUX10_4", - "GTPE2_IMUX40_1", - "GTPE2_FAN6_2", - "GTPE2_IMUX35_2", - "GTPE2_LOGIC_OUTS_B15_4", - "GTPE2_IMUX27_1", - "GTPE2_COMMON_DRPDO14", - "GTPE2_COMMON_BGRCALOVRDENB", - "GTPE2_BYP7_1", - "GTPE2_LOGIC_OUTS_B1_5", - "GTPE2_IMUX3_5", - "GTPE2_COMMON_GTGREFCLK0", - "GTPE2_COMMON_BGMONITORENB", - "GTPE2_IMUX31_1", - "GTPE2_COMMON_PLL0REFCLK", - "GTPE2_COMMON_DRPDO0", - "GTPE2_COMMON_PLL1REFCLKSEL0", - "GTPE2_LOGIC_OUTS_B8_4", - "GTPE2_COMMON_RXOUTCLK_2", - "GTPE2_IMUX3_1", - "GTPE2_BYP5_0", - "GTPE2_IMUX47_1", - "GTPE2_IMUX25_3", - "GTPE2_IMUX33_1", - "GTPE2_IMUX41_2", - "GTPE2_LOGIC_OUTS_B14_3", - "GTPE2_IMUX12_0", - "GTPE2_LOGIC_OUTS_B10_5", - "GTPE2_IMUX10_0", - "GTPE2_LOGIC_OUTS_B4_1", - "GTPE2_BYP6_2", - "GTPE2_COMMON_PMARSVD6", - "GTPE2_BYP0_3", - "GTPE2_LOGIC_OUTS_B23_5", - "IBUFDS_GTPE2_1_CEB", - "GTPE2_IMUX16_1", - "GTPE2_COMMON_DRPDI2", - "GTPE2_IMUX0_5", - "GTPE2_FAN2_2", - "GTPE2_COMMON_PLLRSVD20", - "IBUFDS_GTPE2_1_IB", - "GTPE2_LOGIC_OUTS_B17_5", - "GTPE2_IMUX41_4", - "GTPE2_IMUX33_3", - "GTPE2_BYP0_1", - "GTPE2_IMUX13_4", - "GTPE2_LOGIC_OUTS_B11_4", - "GTPE2_IMUX14_0", - "GTPE2_BYP4_5", - "GTPE2_LOGIC_OUTS_B1_1", - "GTPE2_COMMON_DMONITOROUT4", - "GTPE2_IMUX21_3", - "GTPE2_LOGIC_OUTS_B14_4", - "GTPE2_COMMON_BGRCALOVRD4", - "GTPE2_COMMON_PMARSVDOUT12", - "GTPE2_IMUX19_2", - "GTPE2_COMMON_BGPDB", - "GTPE2_LOGIC_OUTS_B11_2", - "GTPE2_IMUX4_0", - "GTPE2_FAN7_3", - "GTPE2_IMUX24_3", - "GTPE2_CTRL0_2", - "GTPE2_LOGIC_OUTS_B14_1", - "GTPE2_IMUX43_5", - "GTPE2_LOGIC_OUTS_B15_3", - "GTPE2_LOGIC_OUTS_B13_0", - "GTPE2_IMUX17_4", - "GTPE2_IMUX43_1", - "GTPE2_LOGIC_OUTS_B4_2", - "GTPE2_COMMON_DRPDI7", - "GTPE2_BYP0_4", - "GTPE2_COMMON_PMARSVDOUT7", - "GTPE2_LOGIC_OUTS_B9_5", - "GTPE2_IMUX20_4", - "GTPE2_IMUX0_2", - "GTPE2_IMUX29_2", - "GTPE2_IMUX6_5", - "GTPE2_LOGIC_OUTS_B2_0", - "GTPE2_LOGIC_OUTS_B1_2", - "GTPE2_IMUX16_2", - "GTPE2_BYP0_0", - "GTPE2_IMUX43_3", - "GTPE2_IMUX44_3", - "IBUFDS_GTPE2_1_MGTCLKOUT", - "GTPE2_COMMON_PLLRSVD111", - "GTPE2_COMMON_PLL0REFCLKSEL2", - "GTPE2_IMUX22_4", - "GTPE2_IMUX21_1", - "GTPE2_LOGIC_OUTS_B3_0", - "GTPE2_COMMON_MGT_CLK8", - "GTPE2_IMUX23_5", - "GTPE2_IMUX2_3", - "IBUFDS_GTPE2_1_IB_SEG", - "GTPE2_LOGIC_OUTS_B19_3", - "GTPE2_IMUX32_1", - "GTPE2_FAN7_0", - "GTPE2_LOGIC_OUTS_B10_2", - "GTPE2_COMMON_DRPADDR5", - "GTPE2_IMUX13_2", - "GTPE2_COMMON_DRPEN", - "GTPE2_IMUX45_0", - "GTPE2_LOGIC_OUTS_B9_3", - "GTPE2_IMUX46_1", - "GTPE2_COMMON_GTWESTREFCLK1_STUB", - "GTPE2_FAN7_2", - "GTPE2_LOGIC_OUTS_B2_3", - "IBUFDS_GTPE2_1_CLKTESTSIG", - "GTPE2_IMUX19_1", - "GTPE2_IMUX31_5", - "GTPE2_COMMON_DRPDO2", - "GTPE2_FAN6_3", - "GTPE2_IMUX41_0", - "GTPE2_IMUX11_1", - "GTPE2_IMUX29_1", - "GTPE2_COMMON_PLL1FBCLKLOST", - "GTPE2_COMMON_PLL0REFCLKSEL0", - "GTPE2_COMMON_MGT_CLK3", - "IBUFDS_GTPE2_1_I", - "GTPE2_COMMON_GTEASTREFCLK0_STUB", - "GTPE2_IMUX32_3", - "GTPE2_IMUX2_5", - "GTPE2_CTRL1_0", - "GTPE2_LOGIC_OUTS_B9_1", - "GTPE2_LOGIC_OUTS_B6_1", - "GTPE2_IMUX17_0", - "GTPE2_IMUX11_5", - "GTPE2_LOGIC_OUTS_B6_2", - "GTPE2_LOGIC_OUTS_B6_3", - "GTPE2_COMMON_PLLRSVD113", - "GTPE2_LOGIC_OUTS_B22_5", - "GTPE2_IMUX25_5", - "GTPE2_LOGIC_OUTS_B22_1", - "GTPE2_COMMON_DRPDO11", - "GTPE2_IMUX24_5", - "GTPE2_LOGIC_OUTS_B20_5", - "GTPE2_LOGIC_OUTS_B20_3", - "GTPE2_IMUX42_2", - "GTPE2_LOGIC_OUTS_B1_4", - "GTPE2_IMUX47_5", - "GTPE2_LOGIC_OUTS_B1_0", - "GTPE2_COMMON_PMASCANIN3", - "GTPE2_BYP6_5", - "GTPE2_IMUX34_5", - "GTPE2_LOGIC_OUTS_B2_4", - "GTPE2_COMMON_DRPRDY", - "GTPE2_IMUX12_4", - "GTPE2_CTRL1_3", - "GTPE2_FAN6_1", - "GTPE2_IMUX46_3", - "GTPE2_IMUX2_0", - "GTPE2_CTRL0_0", - "GTPE2_IMUX35_4", - "GTPE2_COMMON_GTREFCLK1", - "GTPE2_BYP4_1", - "GTPE2_COMMON_DMONITOROUT0", - "GTPE2_LOGIC_OUTS_B21_3", - "GTPE2_COMMON_RXOUTCLK_0", - "GTPE2_COMMON_DRPDI8", - "GTPE2_COMMON_PMARSVD4", - "GTPE2_LOGIC_OUTS_B8_1", - "GTPE2_FAN1_1", - "GTPE2_IMUX14_2", - "GTPE2_FAN1_4", - "GTPE2_COMMON_DRPDI5", - "GTPE2_COMMON_REFCLKOUTMONITOR1", - "GTPE2_COMMON_DMONITOROUT5", - "GTPE2_IMUX0_4", - "GTPE2_IMUX25_1", - "GTPE2_IMUX2_2", - "GTPE2_LOGIC_OUTS_B23_4", - "GTPE2_IMUX30_5", - "GTPE2_LOGIC_OUTS_B3_4", - "IBUFDS_GTPE2_1_I_SEG", - "GTPE2_CLK1_5", - "IBUFDS_GTPE2_0_I_SEG", - "GTPE2_BYP5_2", - "GTPE2_IMUX12_3", - "GTPE2_COMMON_PMASCANENB", - "GTPE2_COMMON_DRPDI15", - "GTPE2_IMUX11_0", - "GTPE2_IMUX1_5", - "GTPE2_IMUX45_3", - "GTPE2_BYP1_3", - "IBUFDS_GTPE2_1_CLKTESTSIG_SEG", - "GTPE2_COMMON_PMARSVDOUT11", - "GTPE2_IMUX19_4", - "GTPE2_IMUX28_1", - "GTPE2_IMUX6_0", - "GTPE2_COMMON_PMASCANOUT3", - "GTPE2_COMMON_DRPDI11", - "GTPE2_LOGIC_OUTS_B4_5", - "GTPE2_CLK0_3", - "GTPE2_COMMON_RXOUTCLK_1", - "GTPE2_IMUX31_3", - "GTPE2_IMUX19_0", - "GTPE2_IMUX12_5", - "GTPE2_COMMON_PLLRSVD114", - "GTPE2_IMUX45_1", - "GTPE2_LOGIC_OUTS_B12_2", - "GTPE2_IMUX0_0", - "GTPE2_IMUX13_1", - "GTPE2_FAN3_2", - "GTPE2_IMUX4_2", - "GTPE2_LOGIC_OUTS_B0_4", - "GTPE2_IMUX10_5", - "GTPE2_IMUX1_4", - "GTPE2_IMUX33_2", - "IBUFDS_GTPE2_0_I", - "GTPE2_LOGIC_OUTS_B2_5", - "GTPE2_IMUX15_2", - "GTPE2_COMMON_PLL1REFCLKLOST", - "GTPE2_BYP6_3", - "GTPE2_COMMON_PMARSVDOUT4", - "GTPE2_COMMON_PLL0LOCKEN", - "GTPE2_FAN4_4", - "GTPE2_IMUX14_1", - "GTPE2_LOGIC_OUTS_B0_1", - "GTPE2_LOGIC_OUTS_B18_3", - "GTPE2_IMUX36_3", - "GTPE2_IMUX11_4", - "GTPE2_IMUX20_2", - "GTPE2_COMMON_DRPDI4", - "GTPE2_IMUX16_5", - "GTPE2_COMMON_PLLRSVD115", - "GTPE2_IMUX46_0", - "GTPE2_COMMON_PLL1REFCLKSEL1", - "GTPE2_COMMON_PLLRSVD17", - "GTPE2_LOGIC_OUTS_B17_2", - "GTPE2_IMUX36_5", - "GTPE2_COMMON_DMONITOROUT3", - "GTPE2_BYP2_5", - "GTPE2_IMUX36_4", - "GTPE2_IMUX1_2", - "GTPE2_LOGIC_OUTS_B18_0", - "GTPE2_IMUX44_2", - "GTPE2_LOGIC_OUTS_B23_3", - "GTPE2_LOGIC_OUTS_B2_1", - "GTPE2_COMMON_PLL1RESET", - "GTPE2_IMUX44_0", - "GTPE2_IMUX43_0", - "GTPE2_BYP1_1", - "GTPE2_IMUX2_4", - "GTPE2_LOGIC_OUTS_B8_3", - "GTPE2_LOGIC_OUTS_B11_0", - "GTPE2_FAN5_3", - "GTPE2_LOGIC_OUTS_B19_4", - "GTPE2_COMMON_PLL1PD", - "GTPE2_COMMON_PLL0FBCLKLOST", - "GTPE2_LOGIC_OUTS_B6_5", - "GTPE2_LOGIC_OUTS_B22_3", - "GTPE2_FAN1_3", - "GTPE2_COMMON_PLL1REFCLK", - "GTPE2_COMMON_PLLRSVD12", - "GTPE2_IMUX29_0", - "GTPE2_COMMON_QDPMASCANMODEB", - "GTPE2_COMMON_DRPDI3", - "GTPE2_COMMON_MGT_CLK6", - "GTPE2_FAN7_4", - "GTPE2_FAN2_4", - "GTPE2_COMMON_DRPADDR1", - "GTPE2_IMUX24_2", - "GTPE2_LOGIC_OUTS_B22_4", - "GTPE2_IMUX34_4", - "GTPE2_IMUX26_5", - "GTPE2_COMMON_MGT_CLK4", - "IBUFDS_GTPE2_0_ODIV2", - "GTPE2_COMMON_PLLRSVD112", - "GTPE2_COMMON_PMASCANCLK1", - "GTPE2_COMMON_PMARSVD7", - "GTPE2_IMUX30_1", - "GTPE2_COMMON_DRPDI0", - "GTPE2_COMMON_PLL0RESET", - "GTPE2_FAN5_1", - "GTPE2_IMUX42_1", - "GTPE2_FAN0_5", - "GTPE2_LOGIC_OUTS_B22_0", - "GTPE2_IMUX44_5", - "GTPE2_IMUX24_1", - "GTPE2_IMUX22_0", - "GTPE2_IMUX8_5", - "GTPE2_LOGIC_OUTS_B21_5", - "GTPE2_BYP1_0", - "GTPE2_COMMON_DRPDI9", - "GTPE2_COMMON_PLLRSVD23", - "GTPE2_IMUX34_2", - "GTPE2_COMMON_PLLREFCLK0", - "GTPE2_IMUX19_3", - "GTPE2_LOGIC_OUTS_B4_0", - "GTPE2_IMUX44_4", - "GTPE2_COMMON_PMARSVDOUT10", - "GTPE2_IMUX41_5", - "GTPE2_IMUX37_4", - "GTPE2_LOGIC_OUTS_B7_5", - "GTPE2_IMUX37_5", - "GTPE2_CLK0_5", - "GTPE2_COMMON_PMASCANOUT1", - "GTPE2_COMMON_PLLCLKSPARE", - "GTPE2_LOGIC_OUTS_B7_1", - "GTPE2_COMMON_DRPCLK", - "GTPE2_COMMON_DRPWE", - "GTPE2_IMUX30_4", - "GTPE2_IMUX8_0", - "GTPE2_COMMON_PMARSVD0", - "GTPE2_IMUX25_4", - "GTPE2_IMUX42_0", - "GTPE2_COMMON_DRPDO9", - "GTPE2_IMUX27_4", - "GTPE2_IMUX30_3", - "GTPE2_CLK0_0", - "GTPE2_COMMON_PLLRSVD15", - "GTPE2_IMUX33_4", - "GTPE2_LOGIC_OUTS_B6_0", - "GTPE2_COMMON_MGT_CLK7", - "GTPE2_COMMON_MGT_CLK0", - "IBUFDS_GTPE2_1_ODIV2", - "GTPE2_IMUX40_5", - "GTPE2_BYP7_2", - "GTPE2_CLK1_2", - "GTPE2_LOGIC_OUTS_B15_0", - "GTPE2_IMUX24_4", - "GTPE2_IMUX7_5", - "GTPE2_LOGIC_OUTS_B17_4", - "GTPE2_COMMON_PMARSVDOUT15", - "GTPE2_LOGIC_OUTS_B12_4", - "GTPE2_IMUX7_3", - "GTPE2_COMMON_PMARSVDOUT2", - "GTPE2_LOGIC_OUTS_B17_1", - "GTPE2_COMMON_DMONITOROUT6", - "GTPE2_COMMON_PLL0LOCK", - "GTPE2_COMMON_PLL1LOCKEN", - "GTPE2_LOGIC_OUTS_B15_2", - "GTPE2_FAN6_5", - "GTPE2_LOGIC_OUTS_B5_0", - "GTPE2_LOGIC_OUTS_B16_2", - "GTPE2_COMMON_DRPDO13", - "GTPE2_LOGIC_OUTS_B21_1", - "GTPE2_LOGIC_OUTS_B9_0", - "GTPE2_IMUX7_4", - "GTPE2_COMMON_DRPDO7", - "GTPE2_LOGIC_OUTS_B13_1", - "GTPE2_COMMON_PMARSVDOUT1", - "GTPE2_COMMON_DRPDI14", - "GTPE2_IMUX45_2", - "GTPE2_COMMON_TXOUTCLK_1", - "GTPE2_IMUX32_0", - "GTPE2_LOGIC_OUTS_B16_5", - "GTPE2_COMMON_DRPDO10", - "GTPE2_IMUX12_1", - "IBUFDS_GTPE2_0_CLKTESTSIG", - "GTPE2_IMUX39_5", - "GTPE2_FAN0_2", - "GTPE2_IMUX31_2", - "GTPE2_COMMON_REFCLK1", - "GTPE2_IMUX29_4", - "GTPE2_IMUX18_0", - "GTPE2_LOGIC_OUTS_B13_3", - "GTPE2_IMUX36_0", - "GTPE2_BYP7_4", - "GTPE2_LOGIC_OUTS_B7_0", - "IBUFDS_GTPE2_0_MGTCLKOUT", - "GTPE2_LOGIC_OUTS_B0_0", - "GTPE2_LOGIC_OUTS_B21_4", - "GTPE2_IMUX4_3", - "GTPE2_LOGIC_OUTS_B16_0", - "GTPE2_FAN7_1", - "GTPE2_LOGIC_OUTS_B20_4", - "GTPE2_IMUX39_1", - "GTPE2_LOGIC_OUTS_B13_4", - "GTPE2_BYP2_0", - "GTPE2_COMMON_TXOUTCLK_0", - "GTPE2_COMMON_DMONITOROUT2", - "GTPE2_IMUX9_4", - "GTPE2_IMUX6_1", - "GTPE2_LOGIC_OUTS_B23_0", - "GTPE2_IMUX26_2", - "GTPE2_IMUX27_5", - "GTPE2_LOGIC_OUTS_B19_2", - "GTPE2_IMUX13_5", - "GTPE2_LOGIC_OUTS_B16_4", - "GTPE2_IMUX8_1", - "GTPE2_COMMON_DRPDO4", - "GTPE2_COMMON_PMARSVD2", - "GTPE2_IMUX13_0", - "GTPE2_COMMON_DRPADDR6", - "GTPE2_COMMON_DRPDI10", - "GTPE2_BYP2_2", - "GTPE2_BYP1_2", - "GTPE2_COMMON_BGRCALOVRD2", - "GTPE2_IMUX16_4", - "GTPE2_FAN4_0", - "GTPE2_FAN5_4", - "GTPE2_BYP1_4", - "GTPE2_IMUX23_2", - "IBUFDS_GTPE2_0_IB", - "GTPE2_COMMON_PMASCANIN1", - "GTPE2_IMUX1_1", - "GTPE2_FAN1_2", - "GTPE2_LOGIC_OUTS_B13_5", - "GTPE2_IMUX42_5", - "GTPE2_LOGIC_OUTS_B7_2", - "GTPE2_LOGIC_OUTS_B5_5", - "GTPE2_IMUX26_1", - "GTPE2_COMMON_PMARSVD3", - "GTPE2_LOGIC_OUTS_B17_3", - "GTPE2_IMUX9_5", - "GTPE2_IMUX17_1", - "GTPE2_LOGIC_OUTS_B11_5", - "GTPE2_COMMON_TXOUTCLK_2", - "GTPE2_CLK0_1", - "GTPE2_COMMON_PLLREFCLK1", - "GTPE2_FAN0_4", - "GTPE2_IMUX46_5", - "GTPE2_IMUX20_1", - "GTPE2_LOGIC_OUTS_B8_5", - "GTPE2_COMMON_GTWESTREFCLK0_STUB", - "GTPE2_IMUX47_0", - "GTPE2_IMUX23_0", - "GTPE2_COMMON_PMARSVDOUT13", - "GTPE2_IMUX15_3", - "GTPE2_IMUX8_4", - "GTPE2_COMMON_PLLRSVD22", - "GTPE2_IMUX38_3", - "GTPE2_IMUX43_4", - "GTPE2_IMUX36_1", - "GTPE2_BYP3_4", - "GTPE2_FAN4_5", - "GTPE2_IMUX37_2", - "GTPE2_BYP0_5", - "GTPE2_IMUX32_2", - "GTPE2_COMMON_PLLRSVD16", - "GTPE2_COMMON_PLL1REFCLKSEL2", - "GTPE2_IMUX3_4", - "GTPE2_CLK1_4", - "GTPE2_COMMON_PLL1OUTCLK", - "GTPE2_FAN2_3", - "GTPE2_LOGIC_OUTS_B20_0", - "GTPE2_LOGIC_OUTS_B23_1", - "GTPE2_IMUX6_2", - "GTPE2_COMMON_PLLRSVD14", - "GTPE2_IMUX45_4", - "GTPE2_COMMON_PMASCANIN4", - "GTPE2_IMUX23_1", - "GTPE2_LOGIC_OUTS_B15_1", - "GTPE2_BYP5_4", - "GTPE2_LOGIC_OUTS_B21_0", - "GTPE2_IMUX3_0", - "GTPE2_IMUX18_4", - "GTPE2_COMMON_PMARSVD1", - "GTPE2_IMUX20_5", - "GTPE2_IMUX28_0", - "GTPE2_BYP1_5", - "GTPE2_IMUX42_4", - "GTPE2_IMUX31_4", - "GTPE2_COMMON_MGT_CLK2", - "GTPE2_COMMON_DRPDI6", - "GTPE2_LOGIC_OUTS_B14_0", - "GTPE2_IMUX7_0", - "GTPE2_BYP5_5", - "GTPE2_IMUX34_1", - "GTPE2_LOGIC_OUTS_B18_5", - "GTPE2_FAN3_4", - "GTPE2_COMMON_PLLRSVD11", - "GTPE2_FAN3_1", - "GTPE2_FAN7_5", - "GTPE2_IMUX1_3", - "IBUFDS_GTPE2_1_O", - "GTPE2_IMUX31_0", - "GTPE2_IMUX22_5", - "GTPE2_IMUX21_2", - "GTPE2_IMUX21_4", - "GTPE2_IMUX39_2", - "GTPE2_COMMON_DRPDI12", - "GTPE2_IMUX40_0", - "GTPE2_COMMON_PMASCANIN2", - "GTPE2_IMUX19_5", - "GTPE2_IMUX11_2", - "GTPE2_IMUX38_1", - "GTPE2_BYP6_0", - "GTPE2_LOGIC_OUTS_B8_2", - "GTPE2_LOGIC_OUTS_B14_2", - "GTPE2_LOGIC_OUTS_B4_4", - "GTPE2_LOGIC_OUTS_B0_5", - "IBUFDS_GTPE2_0_O", - "GTPE2_IMUX38_5", - "GTPE2_LOGIC_OUTS_B7_4", - "GTPE2_IMUX27_0", - "GTPE2_IMUX22_2", - "GTPE2_COMMON_PMARSVDOUT8", - "GTPE2_IMUX30_0", - "GTPE2_IMUX23_3", - "GTPE2_IMUX14_3", - "GTPE2_IMUX16_3", - "GTPE2_COMMON_GTEASTREFCLK1_STUB", - "GTPE2_LOGIC_OUTS_B9_2", - "GTPE2_IMUX24_0", - "GTPE2_IMUX35_5", - "GTPE2_IMUX23_4", - "GTPE2_COMMON_PLLOUTCLK0", - "GTPE2_IMUX27_3", - "GTPE2_CLK1_0", - "GTPE2_COMMON_PMASCANOUT2", - "GTPE2_BYP2_4", - "GTPE2_IMUX13_3", - "GTPE2_IMUX43_2", - "GTPE2_FAN2_0", - "GTPE2_BYP3_5", - "GTPE2_CTRL0_4", - "GTPE2_IMUX21_0", - "GTPE2_IMUX39_3", - "GTPE2_COMMON_PLLRSVD10", - "GTPE2_LOGIC_OUTS_B12_5", - "GTPE2_BYP3_3", - "GTPE2_IMUX3_3", - "GTPE2_IMUX47_3", - "GTPE2_IMUX4_5", - "GTPE2_IMUX47_2", - "GTPE2_CLK0_2", - "GTPE2_CTRL0_3", - "GTPE2_COMMON_RXOUTCLK_3", - "GTPE2_IMUX38_0", - "GTPE2_IMUX20_3", - "GTPE2_IMUX12_2", - "GTPE2_IMUX39_4", - "GTPE2_IMUX17_3", - "GTPE2_IMUX5_0", - "GTPE2_BYP4_0", - "GTPE2_LOGIC_OUTS_B3_1", - "GTPE2_FAN5_5", - "GTPE2_IMUX9_2", - "GTPE2_IMUX35_0", - "GTPE2_LOGIC_OUTS_B7_3", - "GTPE2_IMUX18_5", - "GTPE2_BYP3_0", - "GTPE2_COMMON_PLL0LOCKDETCLK", - "GTPE2_LOGIC_OUTS_B20_2", - "GTPE2_IMUX5_5", - "GTPE2_BYP4_4", - "GTPE2_LOGIC_OUTS_B3_5", - "GTPE2_IMUX40_3", - "GTPE2_FAN4_3", - "GTPE2_IMUX1_0", - "GTPE2_FAN6_4", - "GTPE2_LOGIC_OUTS_B3_3", - "GTPE2_LOGIC_OUTS_B12_0", - "GTPE2_COMMON_PLLRSVD18", - "GTPE2_IMUX7_2", - "GTPE2_CTRL1_4", - "GTPE2_IMUX26_0", - "IBUFDS_GTPE2_0_IB_SEG", - "GTPE2_IMUX15_0", - "GTPE2_COMMON_DRPADDR2", - "GTPE2_IMUX33_0", - "GTPE2_COMMON_PLL0OUTCLK", - "GTPE2_IMUX11_3", - "GTPE2_LOGIC_OUTS_B22_2", - "GTPE2_FAN0_1", - "GTPE2_IMUX32_5", - "GTPE2_IMUX5_3", - "GTPE2_IMUX41_3", - "GTPE2_IMUX42_3", - "GTPE2_LOGIC_OUTS_B16_1", - "GTPE2_FAN4_1", - "GTPE2_IMUX15_5", - "GTPE2_COMMON_PLLRSVD21", - "GTPE2_BYP7_3", - "GTPE2_BYP5_1", - "GTPE2_CTRL1_1", - "GTPE2_BYP4_2", - "GTPE2_COMMON_DRPDO1", - "GTPE2_IMUX22_1", - "GTPE2_LOGIC_OUTS_B3_2", - "GTPE2_LOGIC_OUTS_B5_2", - "GTPE2_BYP7_0", - "GTPE2_IMUX3_2", - "GTPE2_IMUX17_2", - "GTPE2_IMUX18_3", - "GTPE2_COMMON_DMONITOROUT7", - "GTPE2_COMMON_DRPADDR0", - "GTPE2_IMUX40_4", - "GTPE2_IMUX9_0", - "GTPE2_IMUX29_5", - "GTPE2_IMUX17_5", - "GTPE2_FAN4_2", - "IBUFDS_GTPE2_0_CLKTESTSIG_SEG", - "GTPE2_COMMON_DRPADDR7", - "GTPE2_COMMON_REFCLKOUTMONITOR0", - "GTPE2_LOGIC_OUTS_B4_3", - "GTPE2_IMUX25_2", - "GTPE2_IMUX45_5", - "GTPE2_LOGIC_OUTS_B5_3", - "GTPE2_IMUX4_1", - "GTPE2_IMUX10_1", - "GTPE2_IMUX37_0", - "GTPE2_BYP3_2", - "GTPE2_COMMON_GTGREFCLK1", - "GTPE2_IMUX28_2", - "GTPE2_COMMON_DRPDO3", - "GTPE2_BYP3_1", - "GTPE2_COMMON_MGT_CLK1", - "GTPE2_FAN1_5", - "GTPE2_LOGIC_OUTS_B0_3", - "GTPE2_IMUX28_5", - "GTPE2_IMUX16_0", - "GTPE2_IMUX34_3", - "GTPE2_COMMON_PLLOUTCLK1", - "GTPE2_IMUX5_4", - "GTPE2_CLK1_1", - "GTPE2_COMMON_PMARSVDOUT6", - "GTPE2_COMMON_PMASCANIN0", - "GTPE2_FAN5_2", - "GTPE2_FAN5_0", - "GTPE2_COMMON_PMASCANOUT4", - "GTPE2_IMUX5_1", - "GTPE2_COMMON_MGT_CLK5", - "GTPE2_COMMON_BGRCALOVRD3", - "GTPE2_IMUX22_3", - "GTPE2_COMMON_PLLRSVD13", - "GTPE2_IMUX37_3", - "GTPE2_IMUX33_5", - "GTPE2_LOGIC_OUTS_B16_3", - "GTPE2_IMUX10_3", - "GTPE2_BYP0_2", - "GTPE2_COMMON_BGRCALOVRD0", - "GTPE2_IMUX5_2", - "GTPE2_IMUX38_4", - "GTPE2_IMUX46_4", - "GTPE2_IMUX25_0", - "GTPE2_COMMON_PMARSVD5", - "GTPE2_LOGIC_OUTS_B11_1", - "GTPE2_COMMON_PMARSVDOUT3", - "IBUFDS_GTPE2_0_CEB", - "GTPE2_COMMON_PLL0REFCLKSEL1", - "GTPE2_IMUX15_4", - "GTPE2_LOGIC_OUTS_B0_2", - "GTPE2_LOGIC_OUTS_B18_4", - "GTPE2_COMMON_QDPMASCANRSTEN", - "GTPE2_IMUX44_1", - "GTPE2_COMMON_GTREFCLK0", - "GTPE2_IMUX38_2", - "GTPE2_LOGIC_OUTS_B19_1", - "GTPE2_LOGIC_OUTS_B8_0", - "GTPE2_IMUX28_3", - "GTPE2_IMUX9_3", - "GTPE2_BYP2_3", - "GTPE2_LOGIC_OUTS_B21_2", - "GTPE2_IMUX41_1", - "GTPE2_COMMON_REFCLK0", - "GTPE2_COMMON_RCALENB", - "GTPE2_CTRL0_5", - "GTPE2_LOGIC_OUTS_B12_3", - "GTPE2_LOGIC_OUTS_B6_4", - "GTPE2_IMUX35_3", - "GTPE2_CTRL1_5", - "GTPE2_IMUX26_3", - "GTPE2_FAN0_0", - "GTPE2_COMMON_PMASCANCLK0", - "GTPE2_IMUX6_3", - "GTPE2_IMUX20_0", - "GTPE2_COMMON_DRPDO8" - ], - "sites": [ - { - "prefix": "GTPE2_COMMON", - "y_coord": 0, - "type": "GTPE2_COMMON", - "site_pins": { - "PLL0LOCK": "GTPE2_COMMON_PLL0LOCK", - "DRPDO13": "GTPE2_COMMON_DRPDO13", - "PLL1REFCLKSEL1": "GTPE2_COMMON_PLL1REFCLKSEL1", - "PMARSVDOUT3": "GTPE2_COMMON_PMARSVDOUT3", - "BGPDB": "GTPE2_COMMON_BGPDB", - "PMARSVD6": "GTPE2_COMMON_PMARSVD6", - "PMARSVD3": "GTPE2_COMMON_PMARSVD3", - "GTGREFCLK0": "GTPE2_COMMON_GTGREFCLK0", - "PLLRSVD22": "GTPE2_COMMON_PLLRSVD22", - "DRPDO5": "GTPE2_COMMON_DRPDO5", - "DMONITOROUT5": "GTPE2_COMMON_DMONITOROUT5", - "PMARSVD1": "GTPE2_COMMON_PMARSVD1", - "PMARSVDOUT2": "GTPE2_COMMON_PMARSVDOUT2", - "PLL0LOCKDETCLK": "GTPE2_COMMON_PLL0LOCKDETCLK", - "PMARSVDOUT7": "GTPE2_COMMON_PMARSVDOUT7", - "DMONITOROUT6": "GTPE2_COMMON_DMONITOROUT6", - "DRPDI10": "GTPE2_COMMON_DRPDI10", - "DRPDI4": "GTPE2_COMMON_DRPDI4", - "DRPDI5": "GTPE2_COMMON_DRPDI5", - "PMARSVDOUT9": "GTPE2_COMMON_PMARSVDOUT9", - "DRPDO14": "GTPE2_COMMON_DRPDO14", - "DMONITOROUT2": "GTPE2_COMMON_DMONITOROUT2", - "DRPDI7": "GTPE2_COMMON_DRPDI7", - "DRPADDR4": "GTPE2_COMMON_DRPADDR4", - "PLL1OUTREFCLK": "GTPE2_COMMON_PLL1REFCLK", - "DRPDO3": "GTPE2_COMMON_DRPDO3", - "QDPMASCANMODEB": "GTPE2_COMMON_QDPMASCANMODEB", - "DRPDO8": "GTPE2_COMMON_DRPDO8", - "PLLRSVD111": "GTPE2_COMMON_PLLRSVD111", - "PLL0LOCKEN": "GTPE2_COMMON_PLL0LOCKEN", - "PLLRSVD21": "GTPE2_COMMON_PLLRSVD21", - "PMARSVDOUT15": "GTPE2_COMMON_PMARSVDOUT15", - "PLL1FBCLKLOST": "GTPE2_COMMON_PLL1FBCLKLOST", - "DRPADDR5": "GTPE2_COMMON_DRPADDR5", - "PLL1OUTCLK": "GTPE2_COMMON_PLL1OUTCLK", - "PMASCANCLK1": "GTPE2_COMMON_PMASCANCLK1", - "PLL0REFCLKSEL0": "GTPE2_COMMON_PLL0REFCLKSEL0", - "PLLRSVD18": "GTPE2_COMMON_PLLRSVD18", - "BGRCALOVRD4": "GTPE2_COMMON_BGRCALOVRD4", - "PLLRSVD112": "GTPE2_COMMON_PLLRSVD112", - "GTEASTREFCLK1": null, - "DRPDI11": "GTPE2_COMMON_DRPDI11", - "BGRCALOVRD0": "GTPE2_COMMON_BGRCALOVRD0", - "DMONITOROUT0": "GTPE2_COMMON_DMONITOROUT0", - "PLLRSVD23": "GTPE2_COMMON_PLLRSVD23", - "DMONITOROUT4": "GTPE2_COMMON_DMONITOROUT4", - "DMONITOROUT3": "GTPE2_COMMON_DMONITOROUT3", - "QDPMASCANRSTEN": "GTPE2_COMMON_QDPMASCANRSTEN", - "DMONITOROUT7": "GTPE2_COMMON_DMONITOROUT7", - "PLLCLKSPARE": "GTPE2_COMMON_PLLCLKSPARE", - "PLLRSVD16": "GTPE2_COMMON_PLLRSVD16", - "PLLRSVD13": "GTPE2_COMMON_PLLRSVD13", - "PLLRSVD12": "GTPE2_COMMON_PLLRSVD12", - "PLL1RESET": "GTPE2_COMMON_PLL1RESET", - "DRPADDR2": "GTPE2_COMMON_DRPADDR2", - "DRPDO9": "GTPE2_COMMON_DRPDO9", - "PMARSVDOUT4": "GTPE2_COMMON_PMARSVDOUT4", - "PLL0REFCLKLOST": "GTPE2_COMMON_PLL0REFCLKLOST", - "PLLRSVD19": "GTPE2_COMMON_PLLRSVD19", - "DRPDO7": "GTPE2_COMMON_DRPDO7", - "PMASCANIN0": "GTPE2_COMMON_PMASCANIN0", - "BGMONITORENB": "GTPE2_COMMON_BGMONITORENB", - "DMONITOROUT1": "GTPE2_COMMON_DMONITOROUT1", - "PLL0OUTCLK": "GTPE2_COMMON_PLL0OUTCLK", - "PLL0RESET": "GTPE2_COMMON_PLL0RESET", - "REFCLKOUTMONITOR1": "GTPE2_COMMON_REFCLKOUTMONITOR1", - "DRPADDR1": "GTPE2_COMMON_DRPADDR1", - "GTGREFCLK1": "GTPE2_COMMON_GTGREFCLK1", - "BGRCALOVRDENB": "GTPE2_COMMON_BGRCALOVRDENB", - "DRPEN": "GTPE2_COMMON_DRPEN", - "BGRCALOVRD2": "GTPE2_COMMON_BGRCALOVRD2", - "PMARSVDOUT8": "GTPE2_COMMON_PMARSVDOUT8", - "PMARSVDOUT6": "GTPE2_COMMON_PMARSVDOUT6", - "PLLRSVD10": "GTPE2_COMMON_PLLRSVD10", - "PLL1REFCLKLOST": "GTPE2_COMMON_PLL1REFCLKLOST", - "PMARSVDOUT13": "GTPE2_COMMON_PMARSVDOUT13", - "DRPDI12": "GTPE2_COMMON_DRPDI12", - "DRPDI8": "GTPE2_COMMON_DRPDI8", - "DRPADDR7": "GTPE2_COMMON_DRPADDR7", - "PLL1REFCLKSEL0": "GTPE2_COMMON_PLL1REFCLKSEL0", - "PMARSVDOUT1": "GTPE2_COMMON_PMARSVDOUT1", - "PLLRSVD24": "GTPE2_COMMON_PLLRSVD24", - "DRPDI6": "GTPE2_COMMON_DRPDI6", - "PLLRSVD20": "GTPE2_COMMON_PLLRSVD20", - "PLLRSVD114": "GTPE2_COMMON_PLLRSVD114", - "DRPDI0": "GTPE2_COMMON_DRPDI0", - "DRPADDR6": "GTPE2_COMMON_DRPADDR6", - "GTWESTREFCLK0": null, - "GTREFCLK1": "GTPE2_COMMON_GTREFCLK1", - "DRPADDR3": "GTPE2_COMMON_DRPADDR3", - "PLL0PD": "GTPE2_COMMON_PLL0PD", - "PMARSVDOUT10": "GTPE2_COMMON_PMARSVDOUT10", - "PLLRSVD110": "GTPE2_COMMON_PLLRSVD110", - "DRPDO10": "GTPE2_COMMON_DRPDO10", - "PMARSVD2": "GTPE2_COMMON_PMARSVD2", - "PLL1PD": "GTPE2_COMMON_PLL1PD", - "PMARSVD5": "GTPE2_COMMON_PMARSVD5", - "DRPDI15": "GTPE2_COMMON_DRPDI15", - "PMARSVDOUT5": "GTPE2_COMMON_PMARSVDOUT5", - "PMASCANIN2": "GTPE2_COMMON_PMASCANIN2", - "DRPDO12": "GTPE2_COMMON_DRPDO12", - "PMARSVDOUT12": "GTPE2_COMMON_PMARSVDOUT12", - "PLLRSVD115": "GTPE2_COMMON_PLLRSVD115", - "BGRCALOVRD3": "GTPE2_COMMON_BGRCALOVRD3", - "PMASCANIN4": "GTPE2_COMMON_PMASCANIN4", - "DRPDO11": "GTPE2_COMMON_DRPDO11", - "PLL1LOCKDETCLK": "GTPE2_COMMON_PLL1LOCKDETCLK", - "GTREFCLK0": "GTPE2_COMMON_GTREFCLK0", - "PLL1LOCK": "GTPE2_COMMON_PLL1LOCK", - "PLL0FBCLKLOST": "GTPE2_COMMON_PLL0FBCLKLOST", - "DRPDO15": "GTPE2_COMMON_DRPDO15", - "PLL1REFCLKSEL2": "GTPE2_COMMON_PLL1REFCLKSEL2", - "PMARSVDOUT0": "GTPE2_COMMON_PMARSVDOUT0", - "BGBYPASSB": "GTPE2_COMMON_BGBYPASSB", - "PMASCANOUT3": "GTPE2_COMMON_PMASCANOUT3", - "PLL0REFCLKSEL2": "GTPE2_COMMON_PLL0REFCLKSEL2", - "PMARSVD0": "GTPE2_COMMON_PMARSVD0", - "DRPWE": "GTPE2_COMMON_DRPWE", - "PLLRSVD17": "GTPE2_COMMON_PLLRSVD17", - "DRPDO6": "GTPE2_COMMON_DRPDO6", - "PMARSVD4": "GTPE2_COMMON_PMARSVD4", - "PLL1LOCKEN": "GTPE2_COMMON_PLL1LOCKEN", - "PMASCANOUT1": "GTPE2_COMMON_PMASCANOUT1", - "DRPDO4": "GTPE2_COMMON_DRPDO4", - "DRPDI14": "GTPE2_COMMON_DRPDI14", - "PLL0OUTREFCLK": "GTPE2_COMMON_PLL0REFCLK", - "PLL0REFCLKSEL1": "GTPE2_COMMON_PLL0REFCLKSEL1", - "DRPADDR0": "GTPE2_COMMON_DRPADDR0", - "PMASCANCLK0": "GTPE2_COMMON_PMASCANCLK0", - "PMARSVD7": "GTPE2_COMMON_PMARSVD7", - "DRPDI9": "GTPE2_COMMON_DRPDI9", - "PMASCANOUT2": "GTPE2_COMMON_PMASCANOUT2", - "PMARSVDOUT11": "GTPE2_COMMON_PMARSVDOUT11", - "PLLRSVD15": "GTPE2_COMMON_PLLRSVD15", - "PMASCANENB": "GTPE2_COMMON_PMASCANENB", - "DRPDI13": "GTPE2_COMMON_DRPDI13", - "PMASCANIN3": "GTPE2_COMMON_PMASCANIN3", - "PMASCANOUT0": "GTPE2_COMMON_PMASCANOUT0", - "PMARSVDOUT14": "GTPE2_COMMON_PMARSVDOUT14", - "GTEASTREFCLK0": null, - "DRPCLK": "GTPE2_COMMON_DRPCLK", - "DRPDI3": "GTPE2_COMMON_DRPDI3", - "GTWESTREFCLK1": null, - "REFCLKOUTMONITOR0": "GTPE2_COMMON_REFCLKOUTMONITOR0", - "DRPDO0": "GTPE2_COMMON_DRPDO0", - "BGRCALOVRD1": "GTPE2_COMMON_BGRCALOVRD1", - "DRPDI2": "GTPE2_COMMON_DRPDI2", - "PLLRSVD113": "GTPE2_COMMON_PLLRSVD113", - "PLLRSVD11": "GTPE2_COMMON_PLLRSVD11", - "DRPDO2": "GTPE2_COMMON_DRPDO2", - "DRPDO1": "GTPE2_COMMON_DRPDO1", - "DRPRDY": "GTPE2_COMMON_DRPRDY", - "PMASCANOUT4": "GTPE2_COMMON_PMASCANOUT4", - "RCALENB": "GTPE2_COMMON_RCALENB", - "DRPDI1": "GTPE2_COMMON_DRPDI1", - "PMASCANIN1": "GTPE2_COMMON_PMASCANIN1", - "PLLRSVD14": "GTPE2_COMMON_PLLRSVD14" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IPAD", - "y_coord": 15, - "type": "IPAD", - "site_pins": { - "O": "IBUFDS_GTPE2_0_IB" - }, - "x_coord": 1, - "name": "X1Y15" - }, - { - "prefix": "IPAD", - "y_coord": 14, - "type": "IPAD", - "site_pins": { - "O": "IBUFDS_GTPE2_0_I" - }, - "x_coord": 1, - "name": "X1Y14" - }, - { - "prefix": "IPAD", - "y_coord": 17, - "type": "IPAD", - "site_pins": { - "O": "IBUFDS_GTPE2_1_IB" - }, - "x_coord": 1, - "name": "X1Y17" - }, - { - "prefix": "IPAD", - "y_coord": 16, - "type": "IPAD", - "site_pins": { - "O": "IBUFDS_GTPE2_1_I" - }, - "x_coord": 1, - "name": "X1Y16" - }, - { - "prefix": "IBUFDS_GTE2", - "y_coord": 0, - "type": "IBUFDS_GTE2", - "site_pins": { - "ODIV2": "IBUFDS_GTPE2_0_ODIV2", - "O": "IBUFDS_GTPE2_0_O", - "CEB": "IBUFDS_GTPE2_0_CEB", - "I": "IBUFDS_GTPE2_0_I_SEG", - "CLKTESTSIG": "IBUFDS_GTPE2_0_CLKTESTSIG", - "IB": "IBUFDS_GTPE2_0_IB_SEG" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IBUFDS_GTE2", - "y_coord": 1, - "type": "IBUFDS_GTE2", - "site_pins": { - "ODIV2": "IBUFDS_GTPE2_1_ODIV2", - "O": "IBUFDS_GTPE2_1_O", - "CEB": "IBUFDS_GTPE2_1_CEB", - "I": "IBUFDS_GTPE2_1_I_SEG", - "CLKTESTSIG": "IBUFDS_GTPE2_1_CLKTESTSIG", - "IB": "IBUFDS_GTPE2_1_IB_SEG" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "GTP_COMMON.GTPE2_IMUX3_1->IBUFDS_GTPE2_0_CEB": { + "GTP_COMMON.GTPE2_COMMON_PLL1REFCLK->GTPE2_COMMON_PLLREFCLK1": { "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_0_CEB", + "src_wire": "GTPE2_COMMON_PLL1REFCLK", "is_directional": "1", - "src_wire": "GTPE2_IMUX3_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT15->GTPE2_LOGIC_OUTS_B18_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT15", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B13_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DMONITOROUT4->GTPE2_LOGIC_OUTS_B8_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DMONITOROUT4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX35_2->GTPE2_COMMON_DRPADDR6": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPADDR6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_2", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_0_O->GTPE2_COMMON_REFCLK0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_REFCLK0", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_0_O", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL1OUTCLK->GTPE2_COMMON_PLLOUTCLK1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLOUTCLK1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL1OUTCLK", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DMONITOROUT1->GTPE2_LOGIC_OUTS_B8_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DMONITOROUT1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO12->GTPE2_LOGIC_OUTS_B10_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO12", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX41_3->GTPE2_COMMON_PLL1REFCLKSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL1REFCLKSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX45_4->GTPE2_COMMON_BGRCALOVRD1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_BGRCALOVRD1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DMONITOROUT2->GTPE2_LOGIC_OUTS_B8_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DMONITOROUT2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_RXOUTCLK_2->>GTPE2_COMMON_MGT_CLK6": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK6", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_RXOUTCLK_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX38_4->GTPE2_COMMON_DRPDI2": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX38_5->GTPE2_COMMON_DRPDI0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX22_4->GTPE2_COMMON_DRPDI14": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DMONITOROUT7->GTPE2_LOGIC_OUTS_B14_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DMONITOROUT7", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO2->GTPE2_LOGIC_OUTS_B9_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_TXOUTCLK_0->>GTPE2_COMMON_MGT_CLK2": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK2", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_TXOUTCLK_0", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_CLK0_5->GTPE2_COMMON_GTGREFCLK0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_GTGREFCLK0", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO1->GTPE2_LOGIC_OUTS_B9_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX32_3->GTPE2_COMMON_PLLRSVD14": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD14", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT12->GTPE2_LOGIC_OUTS_B20_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT12", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX42_3->GTPE2_COMMON_PLL0PD": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL0PD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX2_5->GTPE2_COMMON_PLL0REFCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL0REFCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO8->GTPE2_LOGIC_OUTS_B16_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_2", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO8", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_REFCLKOUTMONITOR1->GTPE2_LOGIC_OUTS_B18_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_2", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_REFCLKOUTMONITOR1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT2->GTPE2_LOGIC_OUTS_B13_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX0_4->GTPE2_COMMON_PLLRSVD113": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD113", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT4->GTPE2_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_REFCLK0->>GTPE2_COMMON_GTREFCLK0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_GTREFCLK0", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_REFCLK0", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX2_2->GTPE2_COMMON_PLL1REFCLKSEL0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL1REFCLKSEL0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX42_2->GTPE2_COMMON_PLL1LOCKEN": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL1LOCKEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX5_4->GTPE2_COMMON_PLLRSVD21": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD21", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_4", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_1_CLKTESTSIG_SEG->IBUFDS_GTPE2_1_CLKTESTSIG": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_1_CLKTESTSIG", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_1_CLKTESTSIG_SEG", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO14->GTPE2_LOGIC_OUTS_B10_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO14", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX27_2->GTPE2_COMMON_DRPADDR7": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPADDR7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_CLK1_5->GTPE2_COMMON_DRPCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DMONITOROUT5->GTPE2_LOGIC_OUTS_B14_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DMONITOROUT5", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_0_MGTCLKOUT->>GTPE2_COMMON_MGT_CLK4": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK4", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT5->GTPE2_LOGIC_OUTS_B19_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX45_3->GTPE2_COMMON_BGRCALOVRD2": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_BGRCALOVRD2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_3", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_0_CLKTESTSIG_SEG->IBUFDS_GTPE2_0_CLKTESTSIG": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_0_CLKTESTSIG", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_0_CLKTESTSIG_SEG", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX5_2->GTPE2_COMMON_PLLRSVD23": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD23", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX38_3->GTPE2_COMMON_DRPDI4": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL0REFCLK->GTPE2_COMMON_PLLREFCLK0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLREFCLK0", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL0REFCLK", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT6->GTPE2_LOGIC_OUTS_B19_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT6", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO11->GTPE2_LOGIC_OUTS_B10_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO11", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX27_4->GTPE2_COMMON_DRPADDR3": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPADDR3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_4", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_0_O->IBUFDS_GTPE2_0_MGTCLKOUT": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_0_MGTCLKOUT", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_0_O", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL0LOCK->GTPE2_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL0LOCK", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX35_1->GTPE2_COMMON_DRPWE": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPWE", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX41_2->GTPE2_COMMON_PMARSVD7": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PMARSVD7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO0->GTPE2_LOGIC_OUTS_B9_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO0", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPRDY->GTPE2_LOGIC_OUTS_B17_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPRDY", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLREFCLK1" }, "GTP_COMMON.GTPE2_IMUX24_3->GTPE2_COMMON_PLLRSVD15": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD15", - "is_directional": "1", "src_wire": "GTPE2_IMUX24_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX14_5->GTPE2_COMMON_DRPDI13": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX22_1->GTPE2_COMMON_BGMONITORENB": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_BGMONITORENB", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL0REFCLKLOST->GTPE2_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL0REFCLKLOST", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_RXOUTCLK_3->>GTPE2_COMMON_MGT_CLK7": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK7", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_RXOUTCLK_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX41_5->GTPE2_COMMON_PMARSVD5": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PMARSVD5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX41_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX20_1->GTPE2_COMMON_PMARSVD4": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PMARSVD4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX32_4->GTPE2_COMMON_PLLRSVD12": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT11->GTPE2_LOGIC_OUTS_B20_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT11", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DMONITOROUT3->GTPE2_LOGIC_OUTS_B8_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_2", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DMONITOROUT3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX2_4->GTPE2_COMMON_PLL0REFCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL0REFCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO7->GTPE2_LOGIC_OUTS_B16_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO7", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO3->GTPE2_LOGIC_OUTS_B9_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_2", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_REFCLK1->>GTPE2_COMMON_GTREFCLK1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_GTREFCLK1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_REFCLK1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX22_5->GTPE2_COMMON_DRPDI12": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI12", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_CTRL0_3->GTPE2_COMMON_PLL0RESET": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL0RESET", - "is_directional": "1", - "src_wire": "GTPE2_CTRL0_3", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_0_I->IBUFDS_GTPE2_0_I_SEG": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_0_I_SEG", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_0_I", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX0_2->GTPE2_COMMON_PLLRSVD115": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD115", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO6->GTPE2_LOGIC_OUTS_B16_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO6", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX30_3->GTPE2_COMMON_DRPDI5": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT3->GTPE2_LOGIC_OUTS_B13_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_2", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL1REFCLK->GTPE2_COMMON_PLLREFCLK1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLREFCLK1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL1REFCLK", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX40_5->GTPE2_COMMON_PLLRSVD110": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD110", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO15->GTPE2_LOGIC_OUTS_B18_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO15", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL0OUTCLK->GTPE2_COMMON_PLLOUTCLK0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLOUTCLK0", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL0OUTCLK", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX32_1->GTPE2_COMMON_PLLRSVD18": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD18", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX27_1->GTPE2_COMMON_BGBYPASSB": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_BGBYPASSB", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL0FBCLKLOST->GTPE2_LOGIC_OUTS_B17_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL0FBCLKLOST", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL1REFCLKLOST->GTPE2_LOGIC_OUTS_B11_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL1REFCLKLOST", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX30_5->GTPE2_COMMON_DRPDI1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX45_5->GTPE2_COMMON_BGRCALOVRD0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_BGRCALOVRD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX45_2->GTPE2_COMMON_BGRCALOVRD3": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_BGRCALOVRD3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_2", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_0_IB->IBUFDS_GTPE2_0_IB_SEG": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_0_IB_SEG", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_0_IB", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX38_2->GTPE2_COMMON_DRPDI6": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI6", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX3_5->GTPE2_COMMON_RCALENB": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_RCALENB", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX14_2->GTPE2_COMMON_DRPDI11": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX24_2->GTPE2_COMMON_PLLRSVD17": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD17", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX24_5->GTPE2_COMMON_PLLRSVD11": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD11", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO9->GTPE2_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO9", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX20_5->GTPE2_COMMON_PMARSVD0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PMARSVD0", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX27_5->GTPE2_COMMON_DRPADDR1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPADDR1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX24_1->GTPE2_COMMON_PLLRSVD19": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD19", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL1LOCK->GTPE2_LOGIC_OUTS_B11_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B11_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL1LOCK", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PLL1FBCLKLOST->GTPE2_LOGIC_OUTS_B18_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B18_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PLL1FBCLKLOST", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT7->GTPE2_LOGIC_OUTS_B19_3": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT7", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_REFCLKOUTMONITOR0->GTPE2_LOGIC_OUTS_B17_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B17_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_REFCLKOUTMONITOR0", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_TXOUTCLK_2->>GTPE2_COMMON_MGT_CLK8": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK8", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_TXOUTCLK_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT10->GTPE2_LOGIC_OUTS_B20_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT10", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT13->GTPE2_LOGIC_OUTS_B20_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_2", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT13", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_1_ODIV2->IBUFDS_GTPE2_1_MGTCLKOUT": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_1_MGTCLKOUT", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_1_ODIV2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX42_4->GTPE2_COMMON_PLL0LOCKEN": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL0LOCKEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_RXOUTCLK_1->>GTPE2_COMMON_MGT_CLK1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_RXOUTCLK_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX42_1->GTPE2_COMMON_PLL1PD": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL1PD", - "is_directional": "1", - "src_wire": "GTPE2_IMUX42_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX0_3->GTPE2_COMMON_PLLRSVD114": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD114", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_CLK0_1->GTPE2_COMMON_PLL0LOCKDETCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL0LOCKDETCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK0_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO5->GTPE2_LOGIC_OUTS_B16_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B16_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO10->GTPE2_LOGIC_OUTS_B10_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO10", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX38_1->GTPE2_COMMON_DRPDI8": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI8", - "is_directional": "1", - "src_wire": "GTPE2_IMUX38_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_CLK1_1->GTPE2_COMMON_PLL1LOCKDETCLK": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL1LOCKDETCLK", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX2_3->GTPE2_COMMON_PLL0REFCLKSEL2": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL0REFCLKSEL2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_3", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_0_ODIV2->IBUFDS_GTPE2_0_MGTCLKOUT": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_0_MGTCLKOUT", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_0_ODIV2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX27_3->GTPE2_COMMON_DRPADDR5": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPADDR5", - "is_directional": "1", - "src_wire": "GTPE2_IMUX27_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT9->GTPE2_LOGIC_OUTS_B19_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT9", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT8->GTPE2_LOGIC_OUTS_B19_2": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B19_2", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT8", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX32_5->GTPE2_COMMON_PLLRSVD10": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD10", - "is_directional": "1", - "src_wire": "GTPE2_IMUX32_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_TXOUTCLK_1->>GTPE2_COMMON_MGT_CLK3": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK3", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_TXOUTCLK_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX30_2->GTPE2_COMMON_DRPDI7": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI7", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX45_1->GTPE2_COMMON_BGRCALOVRD4": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_BGRCALOVRD4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX45_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX35_3->GTPE2_COMMON_DRPADDR4": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPADDR4", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX22_3->GTPE2_COMMON_DRPEN": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPEN", - "is_directional": "1", - "src_wire": "GTPE2_IMUX22_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX5_5->GTPE2_COMMON_PLLRSVD20": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD20", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_5", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_1_O->GTPE2_COMMON_REFCLK1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_REFCLK1", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_1_O", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX5_3->GTPE2_COMMON_PLLRSVD22": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD22", - "is_directional": "1", - "src_wire": "GTPE2_IMUX5_3", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_1_IB->IBUFDS_GTPE2_1_IB_SEG": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_1_IB_SEG", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_1_IB", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_1_MGTCLKOUT->>GTPE2_COMMON_MGT_CLK5": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK5", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX3_3->GTPE2_COMMON_BGPDB": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_BGPDB", - "is_directional": "1", - "src_wire": "GTPE2_IMUX3_3", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX35_4->GTPE2_COMMON_DRPADDR2": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPADDR2", - "is_directional": "1", - "src_wire": "GTPE2_IMUX35_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX40_4->GTPE2_COMMON_PLLRSVD111": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD111", - "is_directional": "1", - "src_wire": "GTPE2_IMUX40_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX0_5->GTPE2_COMMON_PLLRSVD112": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD112", - "is_directional": "1", - "src_wire": "GTPE2_IMUX0_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DRPDO4->GTPE2_LOGIC_OUTS_B9_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B9_1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DRPDO4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_RXOUTCLK_0->>GTPE2_COMMON_MGT_CLK0": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK0", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_RXOUTCLK_0", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX24_4->GTPE2_COMMON_PLLRSVD13": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD13", - "is_directional": "1", - "src_wire": "GTPE2_IMUX24_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX20_2->GTPE2_COMMON_PMARSVD3": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PMARSVD3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX20_2", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_CLK1_4->GTPE2_COMMON_GTGREFCLK1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_GTGREFCLK1", - "is_directional": "1", - "src_wire": "GTPE2_CLK1_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX14_4->GTPE2_COMMON_DRPDI15": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI15", - "is_directional": "1", - "src_wire": "GTPE2_IMUX14_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX2_1->GTPE2_COMMON_PLL1REFCLKSEL1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL1REFCLKSEL1", - "is_directional": "1", - "src_wire": "GTPE2_IMUX2_1", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX20_4->GTPE2_COMMON_PMARSVD1": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PMARSVD1", "is_directional": "1", - "src_wire": "GTPE2_IMUX20_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD15" }, - "GTP_COMMON.GTPE2_COMMON_TXOUTCLK_3->>GTPE2_COMMON_MGT_CLK9": { + "GTP_COMMON.GTPE2_IMUX35_1->GTPE2_COMMON_DRPWE": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_MGT_CLK9", + "src_wire": "GTPE2_IMUX35_1", "is_directional": "1", - "src_wire": "GTPE2_COMMON_TXOUTCLK_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPWE" }, - "GTP_COMMON.GTPE2_IMUX32_2->GTPE2_COMMON_PLLRSVD16": { + "GTP_COMMON.IBUFDS_GTPE2_0_MGTCLKOUT->>GTPE2_COMMON_MGT_CLK4": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD16", + "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT", "is_directional": "1", - "src_wire": "GTPE2_IMUX32_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK4" }, - "GTP_COMMON.GTPE2_IMUX30_1->GTPE2_COMMON_DRPDI9": { + "GTP_COMMON.GTPE2_IMUX42_2->GTPE2_COMMON_PLL1LOCKEN": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI9", + "src_wire": "GTPE2_IMUX42_2", "is_directional": "1", - "src_wire": "GTPE2_IMUX30_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL1LOCKEN" }, "GTP_COMMON.GTPE2_IMUX20_3->GTPE2_COMMON_PMARSVD2": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PMARSVD2", - "is_directional": "1", "src_wire": "GTPE2_IMUX20_3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PMARSVD2" + }, + "GTP_COMMON.GTPE2_IMUX5_4->GTPE2_COMMON_PLLRSVD21": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD21" }, "GTP_COMMON.GTPE2_IMUX35_5->GTPE2_COMMON_DRPADDR0": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPADDR0", - "is_directional": "1", "src_wire": "GTPE2_IMUX35_5", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX41_4->GTPE2_COMMON_PMARSVD6": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PMARSVD6", "is_directional": "1", - "src_wire": "GTPE2_IMUX41_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPADDR0" }, - "GTP_COMMON.GTPE2_IMUX5_1->GTPE2_COMMON_PLLRSVD24": { + "GTP_COMMON.GTPE2_COMMON_DMONITOROUT3->GTPE2_LOGIC_OUTS_B8_2": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLLRSVD24", + "src_wire": "GTPE2_COMMON_DMONITOROUT3", "is_directional": "1", - "src_wire": "GTPE2_IMUX5_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_2" }, - "GTP_COMMON.GTPE2_IMUX22_2->GTPE2_COMMON_DRPDI10": { + "GTP_COMMON.IBUFDS_GTPE2_1_MGTCLKOUT->>GTPE2_COMMON_MGT_CLK5": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI10", + "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT", "is_directional": "1", - "src_wire": "GTPE2_IMUX22_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK5" }, - "GTP_COMMON.IBUFDS_GTPE2_1_I->IBUFDS_GTPE2_1_I_SEG": { + "GTP_COMMON.GTPE2_IMUX42_4->GTPE2_COMMON_PLL0LOCKEN": { "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_1_I_SEG", + "src_wire": "GTPE2_IMUX42_4", "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_1_I", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DMONITOROUT6->GTPE2_LOGIC_OUTS_B14_4": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B14_4", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DMONITOROUT6", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B13_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B13_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT0", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX30_4->GTPE2_COMMON_DRPDI3": { - "can_invert": "0", - "dst_wire": "GTPE2_COMMON_DRPDI3", - "is_directional": "1", - "src_wire": "GTPE2_IMUX30_4", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT14->GTPE2_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_PMARSVDOUT14", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_COMMON_DMONITOROUT0->GTPE2_LOGIC_OUTS_B8_5": { - "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B8_5", - "is_directional": "1", - "src_wire": "GTPE2_COMMON_DMONITOROUT0", - "is_pseudo": "0" - }, - "GTP_COMMON.IBUFDS_GTPE2_1_O->IBUFDS_GTPE2_1_MGTCLKOUT": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_1_MGTCLKOUT", - "is_directional": "1", - "src_wire": "IBUFDS_GTPE2_1_O", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL0LOCKEN" }, "GTP_COMMON.GTPE2_COMMON_DRPDO13->GTPE2_LOGIC_OUTS_B10_2": { "can_invert": "0", - "dst_wire": "GTPE2_LOGIC_OUTS_B10_2", - "is_directional": "1", "src_wire": "GTPE2_COMMON_DRPDO13", - "is_pseudo": "0" - }, - "GTP_COMMON.GTPE2_IMUX0_1->IBUFDS_GTPE2_1_CEB": { - "can_invert": "0", - "dst_wire": "IBUFDS_GTPE2_1_CEB", "is_directional": "1", - "src_wire": "GTPE2_IMUX0_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_2" }, - "GTP_COMMON.GTPE2_CTRL1_3->GTPE2_COMMON_PLL1RESET": { + "GTP_COMMON.GTPE2_COMMON_TXOUTCLK_1->>GTPE2_COMMON_MGT_CLK3": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_PLL1RESET", + "src_wire": "GTPE2_COMMON_TXOUTCLK_1", "is_directional": "1", - "src_wire": "GTPE2_CTRL1_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK3" + }, + "GTP_COMMON.GTPE2_CLK0_1->GTPE2_COMMON_PLL0LOCKDETCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL0LOCKDETCLK" + }, + "GTP_COMMON.GTPE2_IMUX32_5->GTPE2_COMMON_PLLRSVD10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD10" + }, + "GTP_COMMON.GTPE2_COMMON_REFCLK0->>GTPE2_COMMON_GTREFCLK0": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_REFCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_GTREFCLK0" + }, + "GTP_COMMON.GTPE2_IMUX27_5->GTPE2_COMMON_DRPADDR1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPADDR1" + }, + "GTP_COMMON.GTPE2_IMUX41_5->GTPE2_COMMON_PMARSVD5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PMARSVD5" + }, + "GTP_COMMON.GTPE2_IMUX30_2->GTPE2_COMMON_DRPDI7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI7" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT8->GTPE2_LOGIC_OUTS_B19_2": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_2" + }, + "GTP_COMMON.IBUFDS_GTPE2_1_ODIV2->IBUFDS_GTPE2_1_MGTCLKOUT": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_1_ODIV2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_1_MGTCLKOUT" + }, + "GTP_COMMON.GTPE2_COMMON_DRPRDY->GTPE2_LOGIC_OUTS_B17_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_5" + }, + "GTP_COMMON.GTPE2_CLK0_5->GTPE2_COMMON_GTGREFCLK0": { + "can_invert": "0", + "src_wire": "GTPE2_CLK0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_GTGREFCLK0" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT12->GTPE2_LOGIC_OUTS_B20_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_3" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO6->GTPE2_LOGIC_OUTS_B16_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_4" + }, + "GTP_COMMON.GTPE2_IMUX3_1->IBUFDS_GTPE2_0_CEB": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_0_CEB" + }, + "GTP_COMMON.GTPE2_IMUX38_2->GTPE2_COMMON_DRPDI6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI6" + }, + "GTP_COMMON.GTPE2_IMUX0_3->GTPE2_COMMON_PLLRSVD114": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD114" + }, + "GTP_COMMON.GTPE2_COMMON_PLL0REFCLK->GTPE2_COMMON_PLLREFCLK0": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PLL0REFCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLREFCLK0" + }, + "GTP_COMMON.GTPE2_COMMON_REFCLK1->>GTPE2_COMMON_GTREFCLK1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_REFCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_GTREFCLK1" + }, + "GTP_COMMON.GTPE2_CTRL0_3->GTPE2_COMMON_PLL0RESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL0_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL0RESET" + }, + "GTP_COMMON.GTPE2_IMUX22_3->GTPE2_COMMON_DRPEN": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPEN" + }, + "GTP_COMMON.GTPE2_IMUX42_3->GTPE2_COMMON_PLL0PD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL0PD" + }, + "GTP_COMMON.IBUFDS_GTPE2_0_IB->IBUFDS_GTPE2_0_IB_SEG": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_0_IB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_0_IB_SEG" + }, + "GTP_COMMON.GTPE2_IMUX14_5->GTPE2_COMMON_DRPDI13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI13" + }, + "GTP_COMMON.GTPE2_COMMON_REFCLKOUTMONITOR1->GTPE2_LOGIC_OUTS_B18_2": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_REFCLKOUTMONITOR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_2" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO7->GTPE2_LOGIC_OUTS_B16_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_3" + }, + "GTP_COMMON.GTPE2_COMMON_DMONITOROUT1->GTPE2_LOGIC_OUTS_B8_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DMONITOROUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_4" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO8->GTPE2_LOGIC_OUTS_B16_2": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_2" + }, + "GTP_COMMON.GTPE2_IMUX22_2->GTPE2_COMMON_DRPDI10": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI10" + }, + "GTP_COMMON.GTPE2_COMMON_RXOUTCLK_1->>GTPE2_COMMON_MGT_CLK1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_RXOUTCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK1" + }, + "GTP_COMMON.GTPE2_IMUX2_5->GTPE2_COMMON_PLL0REFCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL0REFCLKSEL0" + }, + "GTP_COMMON.GTPE2_IMUX24_5->GTPE2_COMMON_PLLRSVD11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD11" + }, + "GTP_COMMON.GTPE2_IMUX0_5->GTPE2_COMMON_PLLRSVD112": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD112" + }, + "GTP_COMMON.GTPE2_IMUX14_2->GTPE2_COMMON_DRPDI11": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI11" + }, + "GTP_COMMON.GTPE2_COMMON_REFCLKOUTMONITOR0->GTPE2_LOGIC_OUTS_B17_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_REFCLKOUTMONITOR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_4" + }, + "GTP_COMMON.GTPE2_IMUX30_3->GTPE2_COMMON_DRPDI5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI5" + }, + "GTP_COMMON.GTPE2_COMMON_PLL1FBCLKLOST->GTPE2_LOGIC_OUTS_B18_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PLL1FBCLKLOST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_5" + }, + "GTP_COMMON.GTPE2_IMUX27_3->GTPE2_COMMON_DRPADDR5": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPADDR5" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO11->GTPE2_LOGIC_OUTS_B10_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_4" + }, + "GTP_COMMON.IBUFDS_GTPE2_1_O->IBUFDS_GTPE2_1_MGTCLKOUT": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_1_MGTCLKOUT" + }, + "GTP_COMMON.GTPE2_IMUX32_4->GTPE2_COMMON_PLLRSVD12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD12" + }, + "GTP_COMMON.GTPE2_COMMON_PLL1REFCLKLOST->GTPE2_LOGIC_OUTS_B11_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PLL1REFCLKLOST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_4" + }, + "GTP_COMMON.GTPE2_COMMON_TXOUTCLK_0->>GTPE2_COMMON_MGT_CLK2": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_TXOUTCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK2" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT9->GTPE2_LOGIC_OUTS_B19_1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_1" + }, + "GTP_COMMON.GTPE2_IMUX30_5->GTPE2_COMMON_DRPDI1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI1" + }, + "GTP_COMMON.GTPE2_COMMON_DMONITOROUT0->GTPE2_LOGIC_OUTS_B8_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DMONITOROUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_5" + }, + "GTP_COMMON.IBUFDS_GTPE2_0_ODIV2->IBUFDS_GTPE2_0_MGTCLKOUT": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_0_ODIV2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_0_MGTCLKOUT" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO14->GTPE2_LOGIC_OUTS_B10_1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_1" + }, + "GTP_COMMON.GTPE2_IMUX27_1->GTPE2_COMMON_BGBYPASSB": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_BGBYPASSB" + }, + "GTP_COMMON.GTPE2_IMUX14_4->GTPE2_COMMON_DRPDI15": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX14_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI15" + }, + "GTP_COMMON.GTPE2_IMUX32_2->GTPE2_COMMON_PLLRSVD16": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD16" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO10->GTPE2_LOGIC_OUTS_B10_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_5" + }, + "GTP_COMMON.GTPE2_IMUX22_4->GTPE2_COMMON_DRPDI14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI14" }, "GTP_COMMON.GTPE2_IMUX42_5->GTPE2_COMMON_BGRCALOVRDENB": { "can_invert": "0", - "dst_wire": "GTPE2_COMMON_BGRCALOVRDENB", - "is_directional": "1", "src_wire": "GTPE2_IMUX42_5", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_BGRCALOVRDENB" + }, + "GTP_COMMON.GTPE2_COMMON_TXOUTCLK_3->>GTPE2_COMMON_MGT_CLK9": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_TXOUTCLK_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK9" + }, + "GTP_COMMON.GTPE2_COMMON_RXOUTCLK_3->>GTPE2_COMMON_MGT_CLK7": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_RXOUTCLK_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK7" + }, + "GTP_COMMON.GTPE2_IMUX35_4->GTPE2_COMMON_DRPADDR2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPADDR2" + }, + "GTP_COMMON.GTPE2_IMUX0_4->GTPE2_COMMON_PLLRSVD113": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD113" + }, + "GTP_COMMON.GTPE2_CLK1_1->GTPE2_COMMON_PLL1LOCKDETCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL1LOCKDETCLK" + }, + "GTP_COMMON.GTPE2_CLK1_5->GTPE2_COMMON_DRPCLK": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPCLK" + }, + "GTP_COMMON.GTPE2_COMMON_PLL0FBCLKLOST->GTPE2_LOGIC_OUTS_B17_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PLL0FBCLKLOST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_3" + }, + "GTP_COMMON.GTPE2_COMMON_PLL0REFCLKLOST->GTPE2_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PLL0REFCLKLOST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_1" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT7->GTPE2_LOGIC_OUTS_B19_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_3" + }, + "GTP_COMMON.GTPE2_IMUX30_4->GTPE2_COMMON_DRPDI3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI3" + }, + "GTP_COMMON.IBUFDS_GTPE2_1_CLKTESTSIG_SEG->IBUFDS_GTPE2_1_CLKTESTSIG": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_1_CLKTESTSIG_SEG", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_1_CLKTESTSIG" + }, + "GTP_COMMON.GTPE2_IMUX20_1->GTPE2_COMMON_PMARSVD4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PMARSVD4" + }, + "GTP_COMMON.GTPE2_IMUX5_2->GTPE2_COMMON_PLLRSVD23": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD23" + }, + "GTP_COMMON.GTPE2_IMUX40_4->GTPE2_COMMON_PLLRSVD111": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD111" + }, + "GTP_COMMON.GTPE2_COMMON_PLL1LOCK->GTPE2_LOGIC_OUTS_B11_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PLL1LOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B11_5" + }, + "GTP_COMMON.GTPE2_IMUX38_3->GTPE2_COMMON_DRPDI4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI4" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT2->GTPE2_LOGIC_OUTS_B13_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_3" + }, + "GTP_COMMON.GTPE2_IMUX38_4->GTPE2_COMMON_DRPDI2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI2" + }, + "GTP_COMMON.GTPE2_IMUX32_3->GTPE2_COMMON_PLLRSVD14": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD14" + }, + "GTP_COMMON.GTPE2_CTRL1_3->GTPE2_COMMON_PLL1RESET": { + "can_invert": "0", + "src_wire": "GTPE2_CTRL1_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL1RESET" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT11->GTPE2_LOGIC_OUTS_B20_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_4" + }, + "GTP_COMMON.GTPE2_IMUX2_1->GTPE2_COMMON_PLL1REFCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL1REFCLKSEL1" + }, + "GTP_COMMON.GTPE2_COMMON_PLL1OUTCLK->GTPE2_COMMON_PLLOUTCLK1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PLL1OUTCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLOUTCLK1" + }, + "GTP_COMMON.GTPE2_IMUX38_1->GTPE2_COMMON_DRPDI8": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI8" + }, + "GTP_COMMON.GTPE2_IMUX2_2->GTPE2_COMMON_PLL1REFCLKSEL0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL1REFCLKSEL0" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO0->GTPE2_LOGIC_OUTS_B9_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_5" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO4->GTPE2_LOGIC_OUTS_B9_1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_1" + }, + "GTP_COMMON.GTPE2_IMUX22_1->GTPE2_COMMON_BGMONITORENB": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_BGMONITORENB" + }, + "GTP_COMMON.GTPE2_IMUX27_4->GTPE2_COMMON_DRPADDR3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPADDR3" + }, + "GTP_COMMON.GTPE2_IMUX41_3->GTPE2_COMMON_PLL1REFCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL1REFCLKSEL2" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO5->GTPE2_LOGIC_OUTS_B16_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_5" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT5->GTPE2_LOGIC_OUTS_B19_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_5" + }, + "GTP_COMMON.GTPE2_IMUX45_4->GTPE2_COMMON_BGRCALOVRD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_BGRCALOVRD1" + }, + "GTP_COMMON.GTPE2_IMUX0_1->IBUFDS_GTPE2_1_CEB": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_1_CEB" + }, + "GTP_COMMON.IBUFDS_GTPE2_1_I->IBUFDS_GTPE2_1_I_SEG": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_1_I", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_1_I_SEG" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO9->GTPE2_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B16_1" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO1->GTPE2_LOGIC_OUTS_B9_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_4" + }, + "GTP_COMMON.GTPE2_COMMON_RXOUTCLK_0->>GTPE2_COMMON_MGT_CLK0": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_RXOUTCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK0" + }, + "GTP_COMMON.GTPE2_COMMON_PLL0OUTCLK->GTPE2_COMMON_PLLOUTCLK0": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PLL0OUTCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLOUTCLK0" + }, + "GTP_COMMON.IBUFDS_GTPE2_1_O->GTPE2_COMMON_REFCLK1": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_REFCLK1" + }, + "GTP_COMMON.IBUFDS_GTPE2_0_O->IBUFDS_GTPE2_0_MGTCLKOUT": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_0_MGTCLKOUT" + }, + "GTP_COMMON.GTPE2_IMUX40_5->GTPE2_COMMON_PLLRSVD110": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX40_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD110" + }, + "GTP_COMMON.IBUFDS_GTPE2_0_I->IBUFDS_GTPE2_0_I_SEG": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_0_I", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_0_I_SEG" + }, + "GTP_COMMON.GTPE2_IMUX24_1->GTPE2_COMMON_PLLRSVD19": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD19" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT14->GTPE2_LOGIC_OUTS_B20_1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_1" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT15->GTPE2_LOGIC_OUTS_B18_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_4" + }, + "GTP_COMMON.GTPE2_CLK1_4->GTPE2_COMMON_GTGREFCLK1": { + "can_invert": "0", + "src_wire": "GTPE2_CLK1_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_GTGREFCLK1" + }, + "GTP_COMMON.GTPE2_COMMON_DMONITOROUT2->GTPE2_LOGIC_OUTS_B8_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DMONITOROUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_3" + }, + "GTP_COMMON.GTPE2_COMMON_PLL0LOCK->GTPE2_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PLL0LOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B17_2" + }, + "GTP_COMMON.GTPE2_IMUX32_1->GTPE2_COMMON_PLLRSVD18": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD18" + }, + "GTP_COMMON.GTPE2_IMUX0_2->GTPE2_COMMON_PLLRSVD115": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX0_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD115" + }, + "GTP_COMMON.GTPE2_IMUX45_2->GTPE2_COMMON_BGRCALOVRD3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_BGRCALOVRD3" + }, + "GTP_COMMON.GTPE2_IMUX38_5->GTPE2_COMMON_DRPDI0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX38_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI0" + }, + "GTP_COMMON.GTPE2_COMMON_DMONITOROUT6->GTPE2_LOGIC_OUTS_B14_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DMONITOROUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_4" + }, + "GTP_COMMON.GTPE2_COMMON_RXOUTCLK_2->>GTPE2_COMMON_MGT_CLK6": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_RXOUTCLK_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK6" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO12->GTPE2_LOGIC_OUTS_B10_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B10_3" + }, + "GTP_COMMON.GTPE2_IMUX3_3->GTPE2_COMMON_BGPDB": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_BGPDB" + }, + "GTP_COMMON.GTPE2_IMUX5_1->GTPE2_COMMON_PLLRSVD24": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD24" + }, + "GTP_COMMON.GTPE2_IMUX30_1->GTPE2_COMMON_DRPDI9": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI9" + }, + "GTP_COMMON.GTPE2_IMUX2_3->GTPE2_COMMON_PLL0REFCLKSEL2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL0REFCLKSEL2" + }, + "GTP_COMMON.IBUFDS_GTPE2_0_CLKTESTSIG_SEG->IBUFDS_GTPE2_0_CLKTESTSIG": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_0_CLKTESTSIG_SEG", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_0_CLKTESTSIG" + }, + "GTP_COMMON.GTPE2_IMUX20_2->GTPE2_COMMON_PMARSVD3": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PMARSVD3" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT4->GTPE2_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_1" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B13_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_4" + }, + "GTP_COMMON.GTPE2_IMUX20_4->GTPE2_COMMON_PMARSVD1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PMARSVD1" + }, + "GTP_COMMON.GTPE2_COMMON_DMONITOROUT5->GTPE2_LOGIC_OUTS_B14_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DMONITOROUT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_5" + }, + "GTP_COMMON.GTPE2_IMUX35_2->GTPE2_COMMON_DRPADDR6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPADDR6" + }, + "GTP_COMMON.IBUFDS_GTPE2_0_O->GTPE2_COMMON_REFCLK0": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_REFCLK0" + }, + "GTP_COMMON.GTPE2_IMUX45_1->GTPE2_COMMON_BGRCALOVRD4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_BGRCALOVRD4" + }, + "GTP_COMMON.GTPE2_IMUX2_4->GTPE2_COMMON_PLL0REFCLKSEL1": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX2_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL0REFCLKSEL1" + }, + "GTP_COMMON.GTPE2_COMMON_DMONITOROUT4->GTPE2_LOGIC_OUTS_B8_1": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DMONITOROUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B8_1" + }, + "GTP_COMMON.GTPE2_COMMON_TXOUTCLK_2->>GTPE2_COMMON_MGT_CLK8": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_TXOUTCLK_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_MGT_CLK8" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT3->GTPE2_LOGIC_OUTS_B13_2": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_2" + }, + "GTP_COMMON.GTPE2_IMUX41_2->GTPE2_COMMON_PMARSVD7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PMARSVD7" + }, + "GTP_COMMON.GTPE2_IMUX24_2->GTPE2_COMMON_PLLRSVD17": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD17" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT13->GTPE2_LOGIC_OUTS_B20_2": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_2" + }, + "GTP_COMMON.IBUFDS_GTPE2_1_IB->IBUFDS_GTPE2_1_IB_SEG": { + "can_invert": "0", + "src_wire": "IBUFDS_GTPE2_1_IB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IBUFDS_GTPE2_1_IB_SEG" + }, + "GTP_COMMON.GTPE2_IMUX5_5->GTPE2_COMMON_PLLRSVD20": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD20" + }, + "GTP_COMMON.GTPE2_IMUX42_1->GTPE2_COMMON_PLL1PD": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLL1PD" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B13_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B13_5" + }, + "GTP_COMMON.GTPE2_IMUX35_3->GTPE2_COMMON_DRPADDR4": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX35_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPADDR4" + }, + "GTP_COMMON.GTPE2_IMUX20_5->GTPE2_COMMON_PMARSVD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX20_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PMARSVD0" + }, + "GTP_COMMON.GTPE2_IMUX45_3->GTPE2_COMMON_BGRCALOVRD2": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_BGRCALOVRD2" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO15->GTPE2_LOGIC_OUTS_B18_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B18_3" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO2->GTPE2_LOGIC_OUTS_B9_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_3" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT10->GTPE2_LOGIC_OUTS_B20_5": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B20_5" + }, + "GTP_COMMON.GTPE2_IMUX5_3->GTPE2_COMMON_PLLRSVD22": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX5_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD22" + }, + "GTP_COMMON.GTPE2_COMMON_PMARSVDOUT6->GTPE2_LOGIC_OUTS_B19_4": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_PMARSVDOUT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B19_4" + }, + "GTP_COMMON.GTPE2_COMMON_DMONITOROUT7->GTPE2_LOGIC_OUTS_B14_3": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DMONITOROUT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B14_3" + }, + "GTP_COMMON.GTPE2_IMUX45_5->GTPE2_COMMON_BGRCALOVRD0": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX45_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_BGRCALOVRD0" + }, + "GTP_COMMON.GTPE2_IMUX3_5->GTPE2_COMMON_RCALENB": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX3_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_RCALENB" + }, + "GTP_COMMON.GTPE2_IMUX41_4->GTPE2_COMMON_PMARSVD6": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX41_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PMARSVD6" + }, + "GTP_COMMON.GTPE2_IMUX24_4->GTPE2_COMMON_PLLRSVD13": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX24_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_PLLRSVD13" + }, + "GTP_COMMON.GTPE2_IMUX27_2->GTPE2_COMMON_DRPADDR7": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX27_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPADDR7" + }, + "GTP_COMMON.GTPE2_IMUX22_5->GTPE2_COMMON_DRPDI12": { + "can_invert": "0", + "src_wire": "GTPE2_IMUX22_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_COMMON_DRPDI12" + }, + "GTP_COMMON.GTPE2_COMMON_DRPDO3->GTPE2_LOGIC_OUTS_B9_2": { + "can_invert": "0", + "src_wire": "GTPE2_COMMON_DRPDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_LOGIC_OUTS_B9_2" } }, - "tile_type": "GTP_COMMON" + "wires": [ + "GTPE2_IMUX14_1", + "GTPE2_IMUX35_1", + "GTPE2_IMUX23_2", + "GTPE2_COMMON_DMONITOROUT6", + "GTPE2_BYP0_5", + "GTPE2_IMUX9_3", + "GTPE2_LOGIC_OUTS_B13_0", + "GTPE2_LOGIC_OUTS_B6_3", + "GTPE2_IMUX44_3", + "GTPE2_FAN0_3", + "GTPE2_IMUX26_0", + "GTPE2_LOGIC_OUTS_B13_1", + "GTPE2_COMMON_DRPDO7", + "GTPE2_LOGIC_OUTS_B19_5", + "GTPE2_IMUX5_2", + "IBUFDS_GTPE2_0_IB", + "GTPE2_IMUX31_0", + "GTPE2_IMUX30_3", + "GTPE2_LOGIC_OUTS_B9_4", + "GTPE2_IMUX18_1", + "GTPE2_COMMON_BGMONITORENB", + "GTPE2_CLK0_4", + "GTPE2_COMMON_DMONITOROUT2", + "GTPE2_COMMON_DMONITOROUT1", + "GTPE2_COMMON_PMARSVDOUT0", + "GTPE2_IMUX42_3", + "GTPE2_IMUX1_3", + "GTPE2_CTRL1_5", + "GTPE2_IMUX22_3", + "GTPE2_COMMON_PLLREFCLK1", + "GTPE2_BYP1_4", + "GTPE2_IMUX18_2", + "GTPE2_LOGIC_OUTS_B2_0", + "GTPE2_COMMON_PMARSVD5", + "IBUFDS_GTPE2_1_CLKTESTSIG_SEG", + "GTPE2_LOGIC_OUTS_B18_2", + "GTPE2_IMUX16_5", + "GTPE2_CLK1_1", + "GTPE2_BYP6_0", + "GTPE2_LOGIC_OUTS_B17_3", + "GTPE2_IMUX7_2", + "GTPE2_COMMON_PLL0FBCLKLOST", + "GTPE2_IMUX34_5", + "GTPE2_IMUX25_5", + "GTPE2_COMMON_DRPDI9", + "GTPE2_COMMON_PMASCANOUT1", + "GTPE2_IMUX23_4", + "GTPE2_IMUX18_5", + "GTPE2_IMUX25_3", + "GTPE2_IMUX23_5", + "GTPE2_COMMON_PMASCANIN0", + "GTPE2_FAN7_2", + "GTPE2_FAN3_3", + "GTPE2_LOGIC_OUTS_B21_3", + "GTPE2_IMUX2_4", + "GTPE2_IMUX17_2", + "GTPE2_IMUX0_2", + "IBUFDS_GTPE2_1_I_SEG", + "GTPE2_COMMON_TXOUTCLK_0", + "GTPE2_COMMON_PLL1REFCLKSEL2", + "GTPE2_IMUX28_0", + "GTPE2_IMUX45_4", + "GTPE2_BYP7_5", + "GTPE2_LOGIC_OUTS_B21_1", + "GTPE2_IMUX25_2", + "GTPE2_IMUX42_4", + "GTPE2_COMMON_PLL1LOCKDETCLK", + "GTPE2_LOGIC_OUTS_B18_5", + "GTPE2_LOGIC_OUTS_B15_0", + "GTPE2_BYP5_3", + "GTPE2_IMUX38_1", + "GTPE2_COMMON_PMARSVDOUT7", + "GTPE2_IMUX22_4", + "GTPE2_IMUX43_1", + "GTPE2_IMUX9_5", + "GTPE2_BYP1_3", + "GTPE2_IMUX16_3", + "GTPE2_COMMON_PMARSVDOUT8", + "GTPE2_IMUX20_3", + "GTPE2_IMUX0_4", + "GTPE2_IMUX24_2", + "GTPE2_IMUX3_2", + "GTPE2_IMUX38_2", + "GTPE2_FAN1_3", + "GTPE2_IMUX4_0", + "GTPE2_COMMON_DRPDO6", + "GTPE2_LOGIC_OUTS_B16_4", + "GTPE2_COMMON_PLL0PD", + "GTPE2_LOGIC_OUTS_B0_1", + "IBUFDS_GTPE2_0_MGTCLKOUT", + "GTPE2_IMUX7_0", + "GTPE2_IMUX19_1", + "GTPE2_COMMON_PMASCANENB", + "GTPE2_IMUX29_0", + "GTPE2_LOGIC_OUTS_B18_1", + "GTPE2_LOGIC_OUTS_B14_1", + "GTPE2_IMUX13_3", + "GTPE2_IMUX1_4", + "GTPE2_IMUX37_0", + "GTPE2_BYP4_4", + "GTPE2_BYP6_2", + "GTPE2_LOGIC_OUTS_B5_3", + "GTPE2_BYP0_3", + "GTPE2_COMMON_DRPADDR4", + "GTPE2_CTRL0_3", + "GTPE2_FAN6_2", + "GTPE2_IMUX40_3", + "GTPE2_COMMON_MGT_CLK3", + "GTPE2_IMUX38_4", + "GTPE2_COMMON_REFCLKOUTMONITOR1", + "GTPE2_COMMON_DMONITOROUT0", + "GTPE2_COMMON_PLLRSVD21", + "GTPE2_CTRL1_1", + "GTPE2_BYP3_3", + "GTPE2_IMUX16_4", + "GTPE2_COMMON_DRPDI2", + "GTPE2_LOGIC_OUTS_B10_5", + "GTPE2_FAN4_3", + "GTPE2_IMUX24_4", + "GTPE2_COMMON_DRPDI13", + "GTPE2_IMUX2_1", + "GTPE2_LOGIC_OUTS_B14_3", + "GTPE2_IMUX9_0", + "GTPE2_COMMON_PMARSVD3", + "GTPE2_IMUX12_5", + "GTPE2_FAN1_1", + "GTPE2_IMUX42_5", + "GTPE2_FAN5_2", + "GTPE2_FAN7_3", + "GTPE2_IMUX41_5", + "GTPE2_LOGIC_OUTS_B6_1", + "GTPE2_BYP0_4", + "GTPE2_COMMON_PLL0REFCLKSEL2", + "GTPE2_LOGIC_OUTS_B17_1", + "GTPE2_IMUX9_4", + "GTPE2_IMUX14_3", + "GTPE2_IMUX13_5", + "GTPE2_LOGIC_OUTS_B16_1", + "GTPE2_LOGIC_OUTS_B19_2", + "GTPE2_BYP1_0", + "GTPE2_IMUX34_2", + "GTPE2_IMUX26_5", + "GTPE2_COMMON_PMARSVD7", + "GTPE2_IMUX33_2", + "GTPE2_COMMON_DRPDO10", + "GTPE2_COMMON_DRPDI6", + "GTPE2_COMMON_DMONITOROUT7", + "GTPE2_COMMON_PLL1FBCLKLOST", + "GTPE2_FAN5_0", + "GTPE2_CLK1_0", + "GTPE2_IMUX41_2", + "GTPE2_FAN4_5", + "GTPE2_COMMON_PLLRSVD23", + "GTPE2_COMMON_PLL1PD", + "GTPE2_COMMON_PLL0REFCLK", + "GTPE2_FAN3_4", + "GTPE2_IMUX1_0", + "GTPE2_LOGIC_OUTS_B23_3", + "GTPE2_COMMON_DRPDI14", + "GTPE2_IMUX20_4", + "IBUFDS_GTPE2_0_ODIV2", + "GTPE2_LOGIC_OUTS_B15_1", + "GTPE2_COMMON_BGBYPASSB", + "GTPE2_COMMON_PMARSVDOUT12", + "GTPE2_IMUX29_5", + "GTPE2_COMMON_PMASCANOUT4", + "GTPE2_LOGIC_OUTS_B1_0", + "GTPE2_IMUX47_2", + "GTPE2_IMUX40_0", + "GTPE2_IMUX12_4", + "GTPE2_IMUX32_4", + "GTPE2_COMMON_DRPDI8", + "GTPE2_LOGIC_OUTS_B6_2", + "GTPE2_BYP4_5", + "GTPE2_CLK0_3", + "GTPE2_LOGIC_OUTS_B14_0", + "GTPE2_IMUX4_5", + "GTPE2_LOGIC_OUTS_B2_5", + "GTPE2_LOGIC_OUTS_B18_3", + "GTPE2_IMUX26_1", + "GTPE2_IMUX25_4", + "IBUFDS_GTPE2_1_CLKTESTSIG", + "GTPE2_IMUX31_3", + "GTPE2_COMMON_PLL0REFCLKSEL1", + "GTPE2_CLK1_2", + "GTPE2_COMMON_PMARSVDOUT5", + "GTPE2_COMMON_PMASCANOUT3", + "GTPE2_BYP7_4", + "GTPE2_IMUX15_5", + "GTPE2_BYP3_0", + "GTPE2_COMMON_PLLRSVD14", + "GTPE2_FAN6_4", + "GTPE2_LOGIC_OUTS_B5_4", + "GTPE2_FAN2_0", + "GTPE2_LOGIC_OUTS_B16_5", + "GTPE2_COMMON_PLL1REFCLKLOST", + "GTPE2_IMUX32_5", + "GTPE2_LOGIC_OUTS_B18_4", + "GTPE2_BYP4_2", + "IBUFDS_GTPE2_0_O", + "GTPE2_BYP5_2", + "GTPE2_IMUX37_5", + "GTPE2_BYP7_0", + "GTPE2_LOGIC_OUTS_B7_2", + "GTPE2_LOGIC_OUTS_B13_5", + "GTPE2_COMMON_PMARSVDOUT3", + "GTPE2_LOGIC_OUTS_B13_3", + "GTPE2_FAN0_2", + "GTPE2_COMMON_PMARSVDOUT10", + "GTPE2_IMUX22_0", + "GTPE2_IMUX33_5", + "GTPE2_COMMON_TXOUTCLK_2", + "GTPE2_LOGIC_OUTS_B12_4", + "GTPE2_IMUX35_3", + "GTPE2_IMUX44_1", + "GTPE2_COMMON_DRPDO14", + "GTPE2_LOGIC_OUTS_B3_4", + "GTPE2_CLK1_5", + "GTPE2_LOGIC_OUTS_B23_0", + "GTPE2_COMMON_PMARSVDOUT2", + "GTPE2_COMMON_DRPDO8", + "GTPE2_LOGIC_OUTS_B2_3", + "GTPE2_FAN6_5", + "GTPE2_IMUX36_1", + "GTPE2_IMUX8_1", + "GTPE2_COMMON_PLL1LOCK", + "GTPE2_IMUX14_5", + "GTPE2_IMUX44_4", + "GTPE2_COMMON_PMARSVDOUT4", + "GTPE2_CLK0_1", + "GTPE2_FAN5_3", + "GTPE2_BYP3_4", + "GTPE2_COMMON_PLLRSVD17", + "GTPE2_IMUX40_2", + "GTPE2_COMMON_PLLRSVD16", + "GTPE2_IMUX43_2", + "GTPE2_IMUX26_4", + "GTPE2_LOGIC_OUTS_B15_5", + "GTPE2_FAN3_5", + "GTPE2_IMUX12_3", + "GTPE2_IMUX3_0", + "GTPE2_LOGIC_OUTS_B11_5", + "GTPE2_COMMON_PMASCANIN1", + "GTPE2_COMMON_PLL1REFCLKSEL0", + "GTPE2_COMMON_PLLRSVD13", + "GTPE2_LOGIC_OUTS_B22_4", + "GTPE2_COMMON_DRPDO9", + "GTPE2_LOGIC_OUTS_B14_2", + "GTPE2_LOGIC_OUTS_B3_5", + "GTPE2_IMUX46_2", + "GTPE2_LOGIC_OUTS_B9_2", + "GTPE2_COMMON_MGT_CLK8", + "GTPE2_IMUX46_0", + "GTPE2_LOGIC_OUTS_B0_2", + "GTPE2_IMUX10_4", + "GTPE2_LOGIC_OUTS_B4_5", + "GTPE2_IMUX22_5", + "GTPE2_IMUX43_5", + "GTPE2_LOGIC_OUTS_B5_2", + "GTPE2_COMMON_DRPDI4", + "GTPE2_IMUX3_5", + "GTPE2_IMUX41_4", + "GTPE2_IMUX1_2", + "GTPE2_COMMON_DRPADDR3", + "GTPE2_COMMON_MGT_CLK1", + "IBUFDS_GTPE2_1_IB_SEG", + "GTPE2_IMUX47_0", + "GTPE2_LOGIC_OUTS_B13_2", + "GTPE2_LOGIC_OUTS_B21_2", + "GTPE2_LOGIC_OUTS_B3_1", + "GTPE2_IMUX8_5", + "GTPE2_IMUX39_0", + "GTPE2_IMUX14_2", + "GTPE2_COMMON_PLLRSVD10", + "GTPE2_COMMON_MGT_CLK6", + "GTPE2_COMMON_PLLRSVD110", + "GTPE2_IMUX23_3", + "GTPE2_BYP2_3", + "GTPE2_IMUX20_1", + "GTPE2_LOGIC_OUTS_B1_5", + "GTPE2_LOGIC_OUTS_B8_5", + "GTPE2_LOGIC_OUTS_B1_3", + "GTPE2_IMUX9_1", + "GTPE2_LOGIC_OUTS_B23_5", + "GTPE2_COMMON_PLLRSVD113", + "GTPE2_COMMON_GTWESTREFCLK1_STUB", + "GTPE2_IMUX17_5", + "GTPE2_COMMON_BGRCALOVRD2", + "GTPE2_IMUX46_4", + "GTPE2_COMMON_PLLRSVD111", + "GTPE2_LOGIC_OUTS_B20_1", + "GTPE2_IMUX10_2", + "GTPE2_IMUX47_4", + "GTPE2_IMUX42_2", + "GTPE2_LOGIC_OUTS_B23_1", + "GTPE2_IMUX15_4", + "GTPE2_IMUX31_4", + "GTPE2_IMUX8_4", + "GTPE2_IMUX26_2", + "GTPE2_COMMON_PMARSVDOUT1", + "GTPE2_IMUX2_3", + "GTPE2_LOGIC_OUTS_B18_0", + "GTPE2_CLK1_4", + "GTPE2_LOGIC_OUTS_B4_1", + "GTPE2_LOGIC_OUTS_B4_0", + "GTPE2_IMUX7_3", + "GTPE2_LOGIC_OUTS_B12_3", + "GTPE2_IMUX11_4", + "GTPE2_IMUX21_1", + "GTPE2_IMUX28_4", + "GTPE2_IMUX27_3", + "GTPE2_COMMON_DRPDO1", + "GTPE2_LOGIC_OUTS_B1_2", + "GTPE2_LOGIC_OUTS_B2_1", + "GTPE2_LOGIC_OUTS_B21_5", + "GTPE2_FAN7_0", + "GTPE2_IMUX0_5", + "GTPE2_IMUX38_3", + "GTPE2_FAN0_0", + "GTPE2_IMUX7_5", + "GTPE2_LOGIC_OUTS_B20_0", + "GTPE2_IMUX39_5", + "GTPE2_IMUX46_3", + "GTPE2_LOGIC_OUTS_B10_0", + "GTPE2_FAN2_4", + "GTPE2_LOGIC_OUTS_B22_5", + "GTPE2_FAN7_4", + "GTPE2_COMMON_QDPMASCANRSTEN", + "GTPE2_IMUX44_0", + "GTPE2_COMMON_DRPWE", + "GTPE2_COMMON_DMONITOROUT3", + "GTPE2_COMMON_PMARSVD4", + "GTPE2_IMUX38_5", + "GTPE2_COMMON_BGRCALOVRD3", + "GTPE2_LOGIC_OUTS_B1_1", + "GTPE2_LOGIC_OUTS_B11_2", + "GTPE2_BYP7_1", + "GTPE2_BYP3_2", + "GTPE2_COMMON_PLL1OUTCLK", + "GTPE2_BYP2_0", + "GTPE2_FAN0_1", + "GTPE2_IMUX45_0", + "GTPE2_IMUX28_1", + "GTPE2_IMUX14_0", + "GTPE2_COMMON_PLLRSVD19", + "GTPE2_IMUX27_5", + "GTPE2_LOGIC_OUTS_B14_5", + "GTPE2_COMMON_PMARSVDOUT6", + "GTPE2_IMUX44_2", + "GTPE2_IMUX19_2", + "GTPE2_IMUX28_2", + "GTPE2_COMMON_PLLRSVD20", + "GTPE2_IMUX34_0", + "GTPE2_IMUX40_4", + "GTPE2_COMMON_MGT_CLK4", + "GTPE2_BYP6_1", + "GTPE2_IMUX16_0", + "GTPE2_LOGIC_OUTS_B3_3", + "GTPE2_LOGIC_OUTS_B23_2", + "GTPE2_FAN5_4", + "GTPE2_LOGIC_OUTS_B22_1", + "GTPE2_LOGIC_OUTS_B19_0", + "GTPE2_LOGIC_OUTS_B19_1", + "GTPE2_IMUX8_2", + "GTPE2_LOGIC_OUTS_B0_5", + "GTPE2_COMMON_PMARSVD6", + "GTPE2_COMMON_PLL0LOCKEN", + "GTPE2_IMUX47_3", + "GTPE2_BYP4_1", + "GTPE2_COMMON_PLLRSVD24", + "GTPE2_COMMON_DRPDO13", + "GTPE2_COMMON_RXOUTCLK_1", + "GTPE2_IMUX16_1", + "GTPE2_COMMON_PMASCANOUT0", + "GTPE2_COMMON_BGRCALOVRD1", + "GTPE2_LOGIC_OUTS_B0_3", + "GTPE2_LOGIC_OUTS_B20_3", + "GTPE2_IMUX6_1", + "GTPE2_IMUX45_1", + "GTPE2_IMUX31_2", + "GTPE2_COMMON_PMASCANIN3", + "GTPE2_LOGIC_OUTS_B9_3", + "GTPE2_LOGIC_OUTS_B10_1", + "GTPE2_COMMON_DRPCLK", + "IBUFDS_GTPE2_0_CLKTESTSIG", + "GTPE2_IMUX8_0", + "GTPE2_LOGIC_OUTS_B3_0", + "GTPE2_IMUX1_5", + "GTPE2_FAN0_4", + "GTPE2_CTRL0_1", + "GTPE2_IMUX33_1", + "GTPE2_COMMON_DRPDI3", + "GTPE2_BYP6_3", + "GTPE2_IMUX11_0", + "GTPE2_BYP5_1", + "GTPE2_COMMON_PMARSVDOUT13", + "GTPE2_COMMON_PMASCANCLK1", + "GTPE2_IMUX36_5", + "GTPE2_IMUX11_5", + "GTPE2_COMMON_PMARSVDOUT11", + "GTPE2_IMUX19_4", + "GTPE2_IMUX40_5", + "GTPE2_LOGIC_OUTS_B19_4", + "GTPE2_IMUX35_5", + "GTPE2_COMMON_DRPADDR2", + "GTPE2_BYP7_2", + "GTPE2_IMUX25_0", + "GTPE2_LOGIC_OUTS_B10_4", + "GTPE2_LOGIC_OUTS_B10_3", + "GTPE2_IMUX21_0", + "GTPE2_BYP1_5", + "GTPE2_COMMON_GTGREFCLK1", + "GTPE2_COMMON_BGPDB", + "GTPE2_IMUX3_3", + "GTPE2_FAN3_2", + "GTPE2_IMUX32_0", + "GTPE2_COMMON_PLLRSVD115", + "GTPE2_IMUX36_3", + "GTPE2_COMMON_PMASCANIN2", + "GTPE2_LOGIC_OUTS_B17_0", + "GTPE2_LOGIC_OUTS_B5_0", + "GTPE2_BYP5_0", + "GTPE2_COMMON_DRPADDR7", + "GTPE2_IMUX13_4", + "GTPE2_COMMON_PMARSVDOUT14", + "GTPE2_IMUX0_0", + "GTPE2_IMUX24_3", + "GTPE2_FAN6_1", + "IBUFDS_GTPE2_1_IB", + "GTPE2_COMMON_RXOUTCLK_3", + "GTPE2_CTRL1_3", + "GTPE2_LOGIC_OUTS_B16_2", + "GTPE2_IMUX45_5", + "GTPE2_COMMON_PLLREFCLK0", + "GTPE2_IMUX22_1", + "GTPE2_COMMON_RXOUTCLK_2", + "GTPE2_IMUX19_5", + "GTPE2_COMMON_DRPDI10", + "GTPE2_COMMON_PLLRSVD11", + "GTPE2_IMUX0_3", + "GTPE2_IMUX13_0", + "GTPE2_IMUX34_3", + "GTPE2_IMUX39_4", + "IBUFDS_GTPE2_0_CLKTESTSIG_SEG", + "GTPE2_COMMON_MGT_CLK5", + "GTPE2_COMMON_DRPDO12", + "GTPE2_BYP1_1", + "GTPE2_COMMON_PLLOUTCLK0", + "GTPE2_IMUX31_1", + "GTPE2_LOGIC_OUTS_B22_3", + "GTPE2_IMUX20_0", + "GTPE2_IMUX24_0", + "GTPE2_IMUX19_0", + "GTPE2_LOGIC_OUTS_B8_4", + "GTPE2_LOGIC_OUTS_B23_4", + "GTPE2_COMMON_PLL0REFCLKLOST", + "GTPE2_FAN7_1", + "GTPE2_COMMON_DRPDI7", + "GTPE2_COMMON_DRPDO11", + "GTPE2_IMUX11_3", + "GTPE2_FAN2_1", + "GTPE2_IMUX27_1", + "IBUFDS_GTPE2_1_I", + "GTPE2_COMMON_BGRCALOVRD4", + "GTPE2_LOGIC_OUTS_B1_4", + "GTPE2_COMMON_DRPDI5", + "GTPE2_IMUX23_0", + "GTPE2_COMMON_PLL1RESET", + "GTPE2_COMMON_DRPADDR6", + "GTPE2_IMUX44_5", + "GTPE2_COMMON_PLLOUTCLK1", + "GTPE2_CTRL0_2", + "GTPE2_FAN5_5", + "GTPE2_COMMON_DMONITOROUT5", + "GTPE2_BYP4_0", + "GTPE2_FAN1_2", + "GTPE2_COMMON_MGT_CLK9", + "GTPE2_COMMON_PMARSVD1", + "GTPE2_COMMON_GTREFCLK0", + "GTPE2_COMMON_PLL0RESET", + "GTPE2_BYP4_3", + "GTPE2_COMMON_PMASCANCLK0", + "GTPE2_LOGIC_OUTS_B11_0", + "GTPE2_LOGIC_OUTS_B22_2", + "GTPE2_IMUX30_0", + "GTPE2_IMUX4_1", + "GTPE2_IMUX16_2", + "GTPE2_LOGIC_OUTS_B8_2", + "GTPE2_CLK1_3", + "GTPE2_IMUX21_2", + "GTPE2_CTRL0_5", + "GTPE2_IMUX17_0", + "GTPE2_LOGIC_OUTS_B6_4", + "GTPE2_COMMON_PLL1REFCLKSEL1", + "GTPE2_COMMON_GTGREFCLK0", + "GTPE2_BYP6_4", + "GTPE2_CLK0_5", + "GTPE2_COMMON_MGT_CLK0", + "GTPE2_COMMON_DRPDO0", + "GTPE2_IMUX3_4", + "GTPE2_COMMON_PMARSVD2", + "GTPE2_FAN4_0", + "GTPE2_IMUX20_5", + "GTPE2_IMUX4_2", + "GTPE2_IMUX28_5", + "GTPE2_COMMON_REFCLK0", + "GTPE2_CTRL1_0", + "GTPE2_IMUX2_2", + "GTPE2_FAN6_3", + "GTPE2_IMUX33_0", + "GTPE2_FAN0_5", + "GTPE2_IMUX30_4", + "GTPE2_IMUX32_3", + "GTPE2_BYP2_1", + "GTPE2_IMUX37_1", + "GTPE2_IMUX34_1", + "GTPE2_IMUX19_3", + "GTPE2_IMUX5_5", + "GTPE2_IMUX6_0", + "GTPE2_IMUX33_3", + "GTPE2_IMUX37_2", + "GTPE2_COMMON_PMARSVD0", + "GTPE2_COMMON_DRPADDR0", + "GTPE2_LOGIC_OUTS_B17_5", + "GTPE2_COMMON_REFCLK1", + "GTPE2_IMUX41_3", + "GTPE2_IMUX47_1", + "IBUFDS_GTPE2_1_CEB", + "GTPE2_COMMON_PLL1LOCKEN", + "GTPE2_COMMON_REFCLKOUTMONITOR0", + "GTPE2_FAN1_0", + "GTPE2_COMMON_PLLRSVD12", + "GTPE2_LOGIC_OUTS_B7_5", + "GTPE2_LOGIC_OUTS_B17_2", + "GTPE2_COMMON_PLLRSVD112", + "GTPE2_IMUX10_0", + "GTPE2_BYP0_2", + "GTPE2_LOGIC_OUTS_B15_4", + "GTPE2_IMUX17_4", + "GTPE2_LOGIC_OUTS_B15_2", + "GTPE2_COMMON_TXOUTCLK_3", + "GTPE2_IMUX17_3", + "GTPE2_LOGIC_OUTS_B8_1", + "GTPE2_LOGIC_OUTS_B5_1", + "GTPE2_IMUX15_3", + "GTPE2_BYP0_0", + "GTPE2_LOGIC_OUTS_B17_4", + "GTPE2_IMUX29_1", + "GTPE2_IMUX39_3", + "GTPE2_IMUX42_0", + "GTPE2_IMUX18_3", + "GTPE2_LOGIC_OUTS_B12_1", + "GTPE2_COMMON_GTEASTREFCLK1_STUB", + "GTPE2_IMUX26_3", + "GTPE2_IMUX42_1", + "GTPE2_LOGIC_OUTS_B6_5", + "GTPE2_IMUX8_3", + "GTPE2_BYP1_2", + "GTPE2_LOGIC_OUTS_B19_3", + "GTPE2_IMUX27_2", + "GTPE2_BYP3_5", + "GTPE2_IMUX43_0", + "GTPE2_COMMON_PLL0REFCLKSEL0", + "GTPE2_IMUX13_1", + "GTPE2_IMUX13_2", + "GTPE2_COMMON_TXOUTCLK_1", + "GTPE2_BYP2_4", + "GTPE2_FAN2_2", + "GTPE2_COMMON_DMONITOROUT4", + "GTPE2_COMMON_PMASCANOUT2", + "GTPE2_IMUX6_4", + "GTPE2_IMUX40_1", + "GTPE2_LOGIC_OUTS_B0_4", + "GTPE2_IMUX43_3", + "GTPE2_LOGIC_OUTS_B0_0", + "GTPE2_IMUX37_4", + "GTPE2_COMMON_DRPDO15", + "GTPE2_LOGIC_OUTS_B7_0", + "GTPE2_COMMON_PLLRSVD22", + "GTPE2_IMUX6_3", + "GTPE2_IMUX5_0", + "GTPE2_BYP2_5", + "GTPE2_COMMON_PMARSVDOUT9", + "GTPE2_LOGIC_OUTS_B5_5", + "GTPE2_IMUX21_5", + "GTPE2_LOGIC_OUTS_B7_1", + "GTPE2_IMUX18_0", + "GTPE2_IMUX38_0", + "GTPE2_IMUX0_1", + "GTPE2_COMMON_PLLCLKSPARE", + "GTPE2_IMUX29_4", + "GTPE2_COMMON_DRPDI1", + "GTPE2_IMUX11_2", + "GTPE2_IMUX22_2", + "GTPE2_FAN4_2", + "GTPE2_IMUX32_2", + "GTPE2_IMUX24_1", + "GTPE2_LOGIC_OUTS_B14_4", + "GTPE2_IMUX15_2", + "GTPE2_LOGIC_OUTS_B7_4", + "GTPE2_LOGIC_OUTS_B20_4", + "GTPE2_IMUX12_1", + "GTPE2_CTRL0_4", + "IBUFDS_GTPE2_0_I_SEG", + "GTPE2_IMUX32_1", + "GTPE2_IMUX20_2", + "GTPE2_COMMON_RXOUTCLK_0", + "GTPE2_LOGIC_OUTS_B9_0", + "GTPE2_LOGIC_OUTS_B20_5", + "GTPE2_IMUX12_2", + "GTPE2_LOGIC_OUTS_B2_2", + "GTPE2_FAN4_1", + "GTPE2_BYP5_4", + "GTPE2_FAN3_0", + "GTPE2_IMUX33_4", + "GTPE2_IMUX36_2", + "GTPE2_IMUX15_0", + "GTPE2_COMMON_BGRCALOVRD0", + "GTPE2_LOGIC_OUTS_B12_5", + "GTPE2_LOGIC_OUTS_B13_4", + "GTPE2_FAN6_0", + "GTPE2_COMMON_DRPDI12", + "GTPE2_CLK0_0", + "GTPE2_IMUX10_3", + "GTPE2_IMUX31_5", + "GTPE2_BYP7_3", + "GTPE2_COMMON_MGT_CLK7", + "GTPE2_COMMON_DRPADDR5", + "GTPE2_COMMON_PMARSVDOUT15", + "GTPE2_IMUX2_5", + "GTPE2_LOGIC_OUTS_B4_4", + "GTPE2_IMUX10_1", + "GTPE2_IMUX37_3", + "GTPE2_LOGIC_OUTS_B9_5", + "GTPE2_IMUX36_4", + "GTPE2_COMMON_DRPDO5", + "GTPE2_IMUX4_3", + "GTPE2_COMMON_PMASCANIN4", + "GTPE2_IMUX10_5", + "GTPE2_LOGIC_OUTS_B12_0", + "GTPE2_IMUX9_2", + "GTPE2_BYP5_5", + "GTPE2_LOGIC_OUTS_B4_2", + "GTPE2_CTRL0_0", + "GTPE2_FAN2_5", + "GTPE2_IMUX46_1", + "GTPE2_IMUX35_4", + "GTPE2_COMMON_MGT_CLK2", + "IBUFDS_GTPE2_0_I", + "GTPE2_IMUX46_5", + "GTPE2_IMUX41_0", + "GTPE2_COMMON_PLLRSVD114", + "IBUFDS_GTPE2_1_MGTCLKOUT", + "GTPE2_LOGIC_OUTS_B8_0", + "GTPE2_LOGIC_OUTS_B3_2", + "GTPE2_IMUX5_3", + "GTPE2_IMUX5_1", + "GTPE2_COMMON_DRPRDY", + "GTPE2_BYP2_2", + "GTPE2_IMUX30_2", + "GTPE2_FAN1_5", + "GTPE2_IMUX47_5", + "GTPE2_BYP6_5", + "GTPE2_LOGIC_OUTS_B2_4", + "GTPE2_IMUX30_5", + "GTPE2_LOGIC_OUTS_B21_4", + "GTPE2_IMUX29_3", + "GTPE2_IMUX7_1", + "GTPE2_LOGIC_OUTS_B16_3", + "GTPE2_FAN3_1", + "IBUFDS_GTPE2_0_CEB", + "GTPE2_COMMON_QDPMASCANMODEB", + "GTPE2_COMMON_DRPDO4", + "GTPE2_IMUX27_4", + "GTPE2_COMMON_RCALENB", + "GTPE2_IMUX21_4", + "GTPE2_IMUX12_0", + "GTPE2_IMUX1_1", + "GTPE2_IMUX25_1", + "GTPE2_COMMON_DRPDO2", + "GTPE2_IMUX3_1", + "GTPE2_BYP3_1", + "GTPE2_IMUX21_3", + "GTPE2_IMUX27_0", + "GTPE2_IMUX11_1", + "IBUFDS_GTPE2_1_O", + "GTPE2_LOGIC_OUTS_B11_1", + "GTPE2_LOGIC_OUTS_B11_3", + "GTPE2_LOGIC_OUTS_B9_1", + "GTPE2_IMUX36_0", + "GTPE2_IMUX39_1", + "GTPE2_LOGIC_OUTS_B6_0", + "GTPE2_COMMON_DRPDO3", + "GTPE2_IMUX6_2", + "GTPE2_FAN2_3", + "GTPE2_IMUX18_4", + "GTPE2_IMUX6_5", + "GTPE2_CLK0_2", + "GTPE2_LOGIC_OUTS_B7_3", + "GTPE2_COMMON_PLL0OUTCLK", + "GTPE2_IMUX14_4", + "GTPE2_COMMON_DRPDI11", + "GTPE2_FAN1_4", + "GTPE2_LOGIC_OUTS_B22_0", + "GTPE2_LOGIC_OUTS_B10_2", + "GTPE2_IMUX34_4", + "GTPE2_LOGIC_OUTS_B16_0", + "GTPE2_IMUX2_0", + "GTPE2_COMMON_PLLRSVD18", + "GTPE2_IMUX43_4", + "GTPE2_IMUX35_2", + "GTPE2_IMUX7_4", + "GTPE2_CTRL1_4", + "GTPE2_COMMON_GTREFCLK1", + "GTPE2_FAN7_5", + "GTPE2_IMUX45_2", + "GTPE2_LOGIC_OUTS_B20_2", + "IBUFDS_GTPE2_0_IB_SEG", + "GTPE2_LOGIC_OUTS_B12_2", + "GTPE2_COMMON_DRPDI0", + "GTPE2_IMUX29_2", + "GTPE2_IMUX4_4", + "GTPE2_IMUX45_3", + "GTPE2_LOGIC_OUTS_B8_3", + "GTPE2_IMUX30_1", + "GTPE2_COMMON_PLL1REFCLK", + "GTPE2_FAN5_1", + "GTPE2_IMUX35_0", + "GTPE2_IMUX28_3", + "GTPE2_COMMON_BGRCALOVRDENB", + "GTPE2_COMMON_PLL0LOCK", + "IBUFDS_GTPE2_1_ODIV2", + "GTPE2_LOGIC_OUTS_B15_3", + "GTPE2_IMUX39_2", + "GTPE2_COMMON_DRPADDR1", + "GTPE2_COMMON_PLL0LOCKDETCLK", + "GTPE2_IMUX17_1", + "GTPE2_FAN4_4", + "GTPE2_LOGIC_OUTS_B11_4", + "GTPE2_LOGIC_OUTS_B4_3", + "GTPE2_IMUX5_4", + "GTPE2_COMMON_DRPEN", + "GTPE2_BYP0_1", + "GTPE2_LOGIC_OUTS_B21_0", + "GTPE2_IMUX41_1", + "GTPE2_COMMON_PLLRSVD15", + "GTPE2_CTRL1_2", + "GTPE2_COMMON_GTEASTREFCLK0_STUB", + "GTPE2_IMUX23_1", + "GTPE2_COMMON_GTWESTREFCLK0_STUB", + "GTPE2_COMMON_DRPDI15", + "GTPE2_IMUX24_5", + "GTPE2_IMUX15_1" + ], + "tile_type": "GTP_COMMON", + "sites": [ + { + "site_pins": { + "GTEASTREFCLK0": null, + "PLL0LOCKEN": "GTPE2_COMMON_PLL0LOCKEN", + "DMONITOROUT4": "GTPE2_COMMON_DMONITOROUT4", + "DRPDO7": "GTPE2_COMMON_DRPDO7", + "PLL0REFCLKSEL0": "GTPE2_COMMON_PLL0REFCLKSEL0", + "PMASCANOUT1": "GTPE2_COMMON_PMASCANOUT1", + "PLLRSVD23": "GTPE2_COMMON_PLLRSVD23", + "DRPADDR5": "GTPE2_COMMON_DRPADDR5", + "PLL0OUTCLK": "GTPE2_COMMON_PLL0OUTCLK", + "GTWESTREFCLK0": null, + "QDPMASCANMODEB": "GTPE2_COMMON_QDPMASCANMODEB", + "DRPDI4": "GTPE2_COMMON_DRPDI4", + "DRPDO2": "GTPE2_COMMON_DRPDO2", + "DRPDO1": "GTPE2_COMMON_DRPDO1", + "PMASCANIN4": "GTPE2_COMMON_PMASCANIN4", + "DMONITOROUT5": "GTPE2_COMMON_DMONITOROUT5", + "PLLRSVD10": "GTPE2_COMMON_PLLRSVD10", + "DRPDO14": "GTPE2_COMMON_DRPDO14", + "DRPDO8": "GTPE2_COMMON_DRPDO8", + "DRPDI15": "GTPE2_COMMON_DRPDI15", + "PMARSVD0": "GTPE2_COMMON_PMARSVD0", + "DRPDI13": "GTPE2_COMMON_DRPDI13", + "PMARSVDOUT0": "GTPE2_COMMON_PMARSVDOUT0", + "DRPADDR2": "GTPE2_COMMON_DRPADDR2", + "DRPADDR4": "GTPE2_COMMON_DRPADDR4", + "BGMONITORENB": "GTPE2_COMMON_BGMONITORENB", + "DRPDO11": "GTPE2_COMMON_DRPDO11", + "DRPDI3": "GTPE2_COMMON_DRPDI3", + "GTGREFCLK1": "GTPE2_COMMON_GTGREFCLK1", + "PMASCANIN0": "GTPE2_COMMON_PMASCANIN0", + "PMARSVD3": "GTPE2_COMMON_PMARSVD3", + "PMARSVDOUT7": "GTPE2_COMMON_PMARSVDOUT7", + "PLLRSVD18": "GTPE2_COMMON_PLLRSVD18", + "PLLRSVD13": "GTPE2_COMMON_PLLRSVD13", + "REFCLKOUTMONITOR0": "GTPE2_COMMON_REFCLKOUTMONITOR0", + "PLLRSVD17": "GTPE2_COMMON_PLLRSVD17", + "GTEASTREFCLK1": null, + "GTGREFCLK0": "GTPE2_COMMON_GTGREFCLK0", + "BGRCALOVRDENB": "GTPE2_COMMON_BGRCALOVRDENB", + "DRPRDY": "GTPE2_COMMON_DRPRDY", + "PMARSVDOUT2": "GTPE2_COMMON_PMARSVDOUT2", + "PLLRSVD20": "GTPE2_COMMON_PLLRSVD20", + "DRPDI14": "GTPE2_COMMON_DRPDI14", + "DRPDO15": "GTPE2_COMMON_DRPDO15", + "PMARSVDOUT5": "GTPE2_COMMON_PMARSVDOUT5", + "DRPEN": "GTPE2_COMMON_DRPEN", + "DRPDO13": "GTPE2_COMMON_DRPDO13", + "PMARSVDOUT12": "GTPE2_COMMON_PMARSVDOUT12", + "DMONITOROUT3": "GTPE2_COMMON_DMONITOROUT3", + "DRPDI1": "GTPE2_COMMON_DRPDI1", + "DRPDI6": "GTPE2_COMMON_DRPDI6", + "PMARSVD4": "GTPE2_COMMON_PMARSVD4", + "PMARSVDOUT4": "GTPE2_COMMON_PMARSVDOUT4", + "DRPDO6": "GTPE2_COMMON_DRPDO6", + "BGRCALOVRD0": "GTPE2_COMMON_BGRCALOVRD0", + "PLL0RESET": "GTPE2_COMMON_PLL0RESET", + "DRPDO10": "GTPE2_COMMON_DRPDO10", + "DRPDO9": "GTPE2_COMMON_DRPDO9", + "PLLRSVD111": "GTPE2_COMMON_PLLRSVD111", + "PMASCANOUT3": "GTPE2_COMMON_PMASCANOUT3", + "PMARSVD5": "GTPE2_COMMON_PMARSVD5", + "DRPDO5": "GTPE2_COMMON_DRPDO5", + "BGRCALOVRD1": "GTPE2_COMMON_BGRCALOVRD1", + "PLLRSVD19": "GTPE2_COMMON_PLLRSVD19", + "PMASCANOUT2": "GTPE2_COMMON_PMASCANOUT2", + "PLL1REFCLKSEL1": "GTPE2_COMMON_PLL1REFCLKSEL1", + "PLL1RESET": "GTPE2_COMMON_PLL1RESET", + "PLL1OUTCLK": "GTPE2_COMMON_PLL1OUTCLK", + "PLL1PD": "GTPE2_COMMON_PLL1PD", + "PMARSVD6": "GTPE2_COMMON_PMARSVD6", + "PLL0FBCLKLOST": "GTPE2_COMMON_PLL0FBCLKLOST", + "GTREFCLK0": "GTPE2_COMMON_GTREFCLK0", + "PMARSVD1": "GTPE2_COMMON_PMARSVD1", + "PMARSVDOUT14": "GTPE2_COMMON_PMARSVDOUT14", + "DRPDI2": "GTPE2_COMMON_DRPDI2", + "BGPDB": "GTPE2_COMMON_BGPDB", + "PMARSVDOUT11": "GTPE2_COMMON_PMARSVDOUT11", + "PLL1FBCLKLOST": "GTPE2_COMMON_PLL1FBCLKLOST", + "PLLRSVD113": "GTPE2_COMMON_PLLRSVD113", + "PLL0REFCLKSEL1": "GTPE2_COMMON_PLL0REFCLKSEL1", + "PLLRSVD14": "GTPE2_COMMON_PLLRSVD14", + "PLLRSVD16": "GTPE2_COMMON_PLLRSVD16", + "DRPDI9": "GTPE2_COMMON_DRPDI9", + "PMARSVDOUT1": "GTPE2_COMMON_PMARSVDOUT1", + "DRPDO3": "GTPE2_COMMON_DRPDO3", + "PLL0LOCK": "GTPE2_COMMON_PLL0LOCK", + "PMARSVDOUT6": "GTPE2_COMMON_PMARSVDOUT6", + "DRPADDR1": "GTPE2_COMMON_DRPADDR1", + "DRPDI0": "GTPE2_COMMON_DRPDI0", + "PLL0OUTREFCLK": "GTPE2_COMMON_PLL0REFCLK", + "PLLRSVD21": "GTPE2_COMMON_PLLRSVD21", + "PMARSVDOUT9": "GTPE2_COMMON_PMARSVDOUT9", + "PLL0PD": "GTPE2_COMMON_PLL0PD", + "PMARSVDOUT13": "GTPE2_COMMON_PMARSVDOUT13", + "PMASCANCLK0": "GTPE2_COMMON_PMASCANCLK0", + "DRPDO4": "GTPE2_COMMON_DRPDO4", + "PLL1REFCLKSEL0": "GTPE2_COMMON_PLL1REFCLKSEL0", + "PLLRSVD12": "GTPE2_COMMON_PLLRSVD12", + "PLLRSVD22": "GTPE2_COMMON_PLLRSVD22", + "PMARSVD2": "GTPE2_COMMON_PMARSVD2", + "DRPDI5": "GTPE2_COMMON_DRPDI5", + "PLLRSVD110": "GTPE2_COMMON_PLLRSVD110", + "PMASCANCLK1": "GTPE2_COMMON_PMASCANCLK1", + "DRPDI12": "GTPE2_COMMON_DRPDI12", + "DRPDI10": "GTPE2_COMMON_DRPDI10", + "PMASCANIN2": "GTPE2_COMMON_PMASCANIN2", + "PMASCANIN1": "GTPE2_COMMON_PMASCANIN1", + "PLL1REFCLKLOST": "GTPE2_COMMON_PLL1REFCLKLOST", + "DMONITOROUT2": "GTPE2_COMMON_DMONITOROUT2", + "PLL1OUTREFCLK": "GTPE2_COMMON_PLL1REFCLK", + "DRPADDR3": "GTPE2_COMMON_DRPADDR3", + "DRPADDR6": "GTPE2_COMMON_DRPADDR6", + "PMARSVD7": "GTPE2_COMMON_PMARSVD7", + "PLL0REFCLKSEL2": "GTPE2_COMMON_PLL0REFCLKSEL2", + "RCALENB": "GTPE2_COMMON_RCALENB", + "BGRCALOVRD4": "GTPE2_COMMON_BGRCALOVRD4", + "BGRCALOVRD2": "GTPE2_COMMON_BGRCALOVRD2", + "PMASCANOUT4": "GTPE2_COMMON_PMASCANOUT4", + "PLLRSVD11": "GTPE2_COMMON_PLLRSVD11", + "PLL0REFCLKLOST": "GTPE2_COMMON_PLL0REFCLKLOST", + "DRPDO0": "GTPE2_COMMON_DRPDO0", + "PLL1LOCKEN": "GTPE2_COMMON_PLL1LOCKEN", + "PMASCANOUT0": "GTPE2_COMMON_PMASCANOUT0", + "DRPDO12": "GTPE2_COMMON_DRPDO12", + "PMARSVDOUT8": "GTPE2_COMMON_PMARSVDOUT8", + "PLL0LOCKDETCLK": "GTPE2_COMMON_PLL0LOCKDETCLK", + "DRPCLK": "GTPE2_COMMON_DRPCLK", + "BGBYPASSB": "GTPE2_COMMON_BGBYPASSB", + "PLL1REFCLKSEL2": "GTPE2_COMMON_PLL1REFCLKSEL2", + "BGRCALOVRD3": "GTPE2_COMMON_BGRCALOVRD3", + "PLLRSVD114": "GTPE2_COMMON_PLLRSVD114", + "PLLRSVD115": "GTPE2_COMMON_PLLRSVD115", + "PLL1LOCK": "GTPE2_COMMON_PLL1LOCK", + "PMARSVDOUT10": "GTPE2_COMMON_PMARSVDOUT10", + "REFCLKOUTMONITOR1": "GTPE2_COMMON_REFCLKOUTMONITOR1", + "PLLRSVD15": "GTPE2_COMMON_PLLRSVD15", + "DRPDI7": "GTPE2_COMMON_DRPDI7", + "QDPMASCANRSTEN": "GTPE2_COMMON_QDPMASCANRSTEN", + "PMASCANENB": "GTPE2_COMMON_PMASCANENB", + "PMASCANIN3": "GTPE2_COMMON_PMASCANIN3", + "PMARSVDOUT15": "GTPE2_COMMON_PMARSVDOUT15", + "PLLRSVD24": "GTPE2_COMMON_PLLRSVD24", + "PMARSVDOUT3": "GTPE2_COMMON_PMARSVDOUT3", + "DRPWE": "GTPE2_COMMON_DRPWE", + "DRPDI8": "GTPE2_COMMON_DRPDI8", + "DMONITOROUT7": "GTPE2_COMMON_DMONITOROUT7", + "DMONITOROUT6": "GTPE2_COMMON_DMONITOROUT6", + "DRPDI11": "GTPE2_COMMON_DRPDI11", + "PLLCLKSPARE": "GTPE2_COMMON_PLLCLKSPARE", + "DMONITOROUT1": "GTPE2_COMMON_DMONITOROUT1", + "DRPADDR7": "GTPE2_COMMON_DRPADDR7", + "PLL1LOCKDETCLK": "GTPE2_COMMON_PLL1LOCKDETCLK", + "DMONITOROUT0": "GTPE2_COMMON_DMONITOROUT0", + "GTREFCLK1": "GTPE2_COMMON_GTREFCLK1", + "GTWESTREFCLK1": null, + "DRPADDR0": "GTPE2_COMMON_DRPADDR0", + "PLLRSVD112": "GTPE2_COMMON_PLLRSVD112" + }, + "type": "GTPE2_COMMON", + "prefix": "GTPE2_COMMON", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "O": "IBUFDS_GTPE2_0_IB" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y15", + "x_coord": 1, + "y_coord": 15 + }, + { + "site_pins": { + "O": "IBUFDS_GTPE2_0_I" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y14", + "x_coord": 1, + "y_coord": 14 + }, + { + "site_pins": { + "O": "IBUFDS_GTPE2_1_IB" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y17", + "x_coord": 1, + "y_coord": 17 + }, + { + "site_pins": { + "O": "IBUFDS_GTPE2_1_I" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X1Y16", + "x_coord": 1, + "y_coord": 16 + }, + { + "site_pins": { + "I": "IBUFDS_GTPE2_0_I_SEG", + "IB": "IBUFDS_GTPE2_0_IB_SEG", + "CEB": "IBUFDS_GTPE2_0_CEB", + "ODIV2": "IBUFDS_GTPE2_0_ODIV2", + "O": "IBUFDS_GTPE2_0_O", + "CLKTESTSIG": "IBUFDS_GTPE2_0_CLKTESTSIG" + }, + "type": "IBUFDS_GTE2", + "prefix": "IBUFDS_GTE2", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "I": "IBUFDS_GTPE2_1_I_SEG", + "IB": "IBUFDS_GTPE2_1_IB_SEG", + "CEB": "IBUFDS_GTPE2_1_CEB", + "ODIV2": "IBUFDS_GTPE2_1_ODIV2", + "O": "IBUFDS_GTPE2_1_O", + "CLKTESTSIG": "IBUFDS_GTPE2_1_CLKTESTSIG" + }, + "type": "IBUFDS_GTE2", + "prefix": "IBUFDS_GTE2", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_GTP_INT_INTERFACE.json b/artix7/tile_type_GTP_INT_INTERFACE.json index f99afc6..e656a24 100644 --- a/artix7/tile_type_GTP_INT_INTERFACE.json +++ b/artix7/tile_type_GTP_INT_INTERFACE.json @@ -1,1526 +1,1526 @@ { - "wires": [ - "INT_INTERFACE_BYP5", - "GTPE2_INT_INTERFACE_IMUX36", - "GTPE2_INT_INTERFACE_IMUX_DELAY25", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_EE4B2", - "GTPE2_INT_INTERFACE_IMUX_DELAY19", - "GTPE2_INT_INTERFACE_IMUX_OUT33", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_LOGIC_OUTS17", - "GTPE2_INT_INTERFACE_IMUX_OUT17", - "GTPE2_INT_INTERFACE_IMUX_DELAY4", - "GTPE2_INT_INTERFACE_IMUX5", - "GTPE2_INT_INTERFACE_IMUX32", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_LOGIC_OUTS16", - "INT_INTERFACE_LH10", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_SW4A0", - "GTPE2_INT_INTERFACE_IMUX_DELAY14", - "GTPE2_INT_INTERFACE_IMUX_DELAY36", - "INT_INTERFACE_BLOCK_OUTS_B0", - "INT_INTERFACE_LH1", - "INT_INTERFACE_LOGIC_OUTS7", - "GTPE2_INT_INTERFACE_IMUX46", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_LH6", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_BLOCK_OUTS_B2", - "GTPE2_INT_INTERFACE_IMUX_OUT2", - "GTPE2_INT_INTERFACE_IMUX_DELAY12", - "GTPE2_INT_INTERFACE_IMUX_OUT39", - "GTPE2_INT_INTERFACE_IMUX_DELAY40", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_WW4A2", - "GTPE2_INT_INTERFACE_IMUX33", - "GTPE2_INT_INTERFACE_IMUX16", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_MONITOR_N", - "GTPE2_INT_INTERFACE_IMUX_OUT15", - "GTPE2_INT_INTERFACE_IMUX_DELAY5", - "GTPE2_INT_INTERFACE_IMUX_OUT35", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_LH4", - "GTPE2_INT_INTERFACE_IMUX11", - "INT_INTERFACE_FAN2", - "GTPE2_INT_INTERFACE_IMUX_DELAY10", - "GTPE2_INT_INTERFACE_IMUX_DELAY39", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_LOGIC_OUTS_B23", - "GTPE2_INT_INTERFACE_IMUX22", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_LOGIC_OUTS20", - "INT_INTERFACE_SW4END0", - "GTPE2_INT_INTERFACE_IMUX_DELAY13", - "INT_INTERFACE_WW2A1", - "GTPE2_INT_INTERFACE_IMUX_OUT9", - "INT_INTERFACE_SE4C3", - "GTPE2_INT_INTERFACE_IMUX27", - "GTPE2_INT_INTERFACE_IMUX_OUT34", - "INT_INTERFACE_WR1END3", - "GTPE2_INT_INTERFACE_IMUX_DELAY15", - "GTPE2_INT_INTERFACE_IMUX_DELAY17", - "GTPE2_INT_INTERFACE_IMUX37", - "GTPE2_INT_INTERFACE_IMUX_DELAY30", - "INT_INTERFACE_LOGIC_OUTS4", - "INT_INTERFACE_LH8", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_FAN1", - "GTPE2_INT_INTERFACE_IMUX26", - "GTPE2_INT_INTERFACE_IMUX_DELAY43", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_LOGIC_OUTS_B4", - "GTPE2_INT_INTERFACE_IMUX_DELAY44", - "GTPE2_INT_INTERFACE_IMUX40", - "GTPE2_INT_INTERFACE_IMUX28", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS_B5", - "GTPE2_INT_INTERFACE_IMUX_DELAY9", - "INT_INTERFACE_NE4BEG3", - "GTPE2_INT_INTERFACE_IMUX_DELAY31", - "GTPE2_INT_INTERFACE_IMUX_DELAY7", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_LH5", - "GTPE2_INT_INTERFACE_IMUX_DELAY1", - "GTPE2_INT_INTERFACE_IMUX_OUT25", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_LOGIC_OUTS22", - "GTPE2_INT_INTERFACE_IMUX_OUT23", - "INT_INTERFACE_WR1END1", - "GTPE2_INT_INTERFACE_IMUX_DELAY24", - "INT_INTERFACE_EE4B0", - "GTPE2_INT_INTERFACE_IMUX39", - "GTPE2_INT_INTERFACE_IMUX_OUT41", - "INT_INTERFACE_CTRL1", - "GTPE2_INT_INTERFACE_IMUX_DELAY20", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_LOGIC_OUTS_B6", - "GTPE2_INT_INTERFACE_IMUX0", - "INT_INTERFACE_LOGIC_OUTS0", - "GTPE2_INT_INTERFACE_IMUX17", - "GTPE2_INT_INTERFACE_IMUX_OUT18", - "INT_INTERFACE_LH2", - "GTPE2_INT_INTERFACE_IMUX_OUT47", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_SE2A2", - "GTPE2_INT_INTERFACE_IMUX_OUT45", - "INT_INTERFACE_EE4C1", - "GTPE2_INT_INTERFACE_IMUX_DELAY33", - "INT_INTERFACE_EL1BEG1", - "GTPE2_INT_INTERFACE_IMUX_DELAY16", - "INT_INTERFACE_LOGIC_OUTS9", - "INT_INTERFACE_SW2A1", - "GTPE2_INT_INTERFACE_IMUX_DELAY41", - "INT_INTERFACE_NE4C1", - "GTPE2_INT_INTERFACE_IMUX38", - "INT_INTERFACE_LOGIC_OUTS15", - "GTPE2_INT_INTERFACE_IMUX_OUT43", - "GTPE2_INT_INTERFACE_IMUX35", - "INT_INTERFACE_SE2A3", - "GTPE2_INT_INTERFACE_IMUX_DELAY35", - "GTPE2_INT_INTERFACE_IMUX4", - "INT_INTERFACE_SE2A0", - "GTPE2_INT_INTERFACE_IMUX19", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_EE4B3", - "GTPE2_INT_INTERFACE_IMUX34", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_LOGIC_OUTS19", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_LOGIC_OUTS_B14", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_ER1BEG1", - "GTPE2_INT_INTERFACE_IMUX_DELAY3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_LH3", - "GTPE2_INT_INTERFACE_IMUX24", - "GTPE2_INT_INTERFACE_IMUX_OUT19", - "GTPE2_INT_INTERFACE_IMUX_DELAY42", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_NW4A1", - "GTPE2_INT_INTERFACE_IMUX_OUT31", - "GTPE2_INT_INTERFACE_IMUX_OUT3", - "GTPE2_INT_INTERFACE_IMUX_OUT26", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "GTPE2_INT_INTERFACE_IMUX_DELAY34", - "GTPE2_INT_INTERFACE_IMUX_DELAY8", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE2A1", - "GTPE2_INT_INTERFACE_IMUX3", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_FAN5", - "GTPE2_INT_INTERFACE_IMUX_OUT14", - "GTPE2_INT_INTERFACE_IMUX_DELAY47", - "GTPE2_INT_INTERFACE_IMUX_OUT1", - "GTPE2_INT_INTERFACE_IMUX_OUT42", - "INT_INTERFACE_LOGIC_OUTS10", - "INT_INTERFACE_CLK0", - "GTPE2_INT_INTERFACE_IMUX44", - "GTPE2_INT_INTERFACE_IMUX_DELAY0", - "GTPE2_INT_INTERFACE_IMUX31", - "GTPE2_INT_INTERFACE_IMUX_DELAY29", - "GTPE2_INT_INTERFACE_IMUX9", - "INT_INTERFACE_LOGIC_OUTS_B1", - "INT_INTERFACE_LOGIC_OUTS5", - "GTPE2_INT_INTERFACE_IMUX_DELAY18", - "GTPE2_INT_INTERFACE_IMUX_OUT5", - "INT_INTERFACE_SE4BEG1", - "GTPE2_INT_INTERFACE_IMUX_DELAY38", - "GTPE2_INT_INTERFACE_IMUX_DELAY26", - "INT_INTERFACE_LOGIC_OUTS_B9", - "INT_INTERFACE_NE4BEG2", - "GTPE2_INT_INTERFACE_IMUX_DELAY6", - "INT_INTERFACE_LOGIC_OUTS_B18", - "GTPE2_INT_INTERFACE_IMUX_OUT46", - "GTPE2_INT_INTERFACE_IMUX_DELAY21", - "INT_INTERFACE_LOGIC_OUTS_B21", - "GTPE2_INT_INTERFACE_IMUX_OUT20", - "GTPE2_INT_INTERFACE_IMUX29", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS21", - "GTPE2_INT_INTERFACE_IMUX_DELAY45", - "INT_INTERFACE_NE2A3", - "GTPE2_INT_INTERFACE_IMUX_OUT7", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_NW2A2", - "GTPE2_INT_INTERFACE_IMUX13", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_SW2A0", - "GTPE2_INT_INTERFACE_IMUX_DELAY32", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_EE2A0", - "INT_INTERFACE_LOGIC_OUTS1", - "GTPE2_INT_INTERFACE_IMUX_OUT36", - "GTPE2_INT_INTERFACE_IMUX_DELAY28", - "INT_INTERFACE_LOGIC_OUTS3", - "INT_INTERFACE_WR1END2", - "GTPE2_INT_INTERFACE_IMUX_DELAY37", - "GTPE2_INT_INTERFACE_IMUX_OUT38", - "GTPE2_INT_INTERFACE_IMUX30", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_SW4END3", - "GTPE2_INT_INTERFACE_IMUX_DELAY11", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_WL1END0", - "GTPE2_INT_INTERFACE_IMUX_OUT6", - "INT_INTERFACE_BYP1", - "GTPE2_INT_INTERFACE_IMUX_OUT27", - "GTPE2_INT_INTERFACE_IMUX8", - "INT_INTERFACE_WW4C3", - "GTPE2_INT_INTERFACE_IMUX47", - "INT_INTERFACE_LOGIC_OUTS12", - "INT_INTERFACE_CLK1", - "GTPE2_INT_INTERFACE_IMUX12", - "GTPE2_INT_INTERFACE_IMUX_OUT32", - "GTPE2_INT_INTERFACE_IMUX_DELAY22", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_LH7", - "GTPE2_INT_INTERFACE_IMUX_DELAY46", - "GTPE2_INT_INTERFACE_IMUX18", - "GTPE2_INT_INTERFACE_IMUX14", - "GTPE2_INT_INTERFACE_IMUX15", - "INT_INTERFACE_LOGIC_OUTS11", - "GTPE2_INT_INTERFACE_IMUX45", - "INT_INTERFACE_BLOCK_OUTS_B3", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_SW4A1", - "GTPE2_INT_INTERFACE_IMUX43", - "GTPE2_INT_INTERFACE_IMUX_OUT37", - "INT_INTERFACE_LOGIC_OUTS18", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_BYP2", - "GTPE2_INT_INTERFACE_IMUX25", - "GTPE2_INT_INTERFACE_IMUX1", - "INT_INTERFACE_LOGIC_OUTS_B12", - "GTPE2_INT_INTERFACE_IMUX_OUT22", - "GTPE2_INT_INTERFACE_IMUX41", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_WR1END0", - "GTPE2_INT_INTERFACE_IMUX_DELAY2", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_EE2BEG3", - "GTPE2_INT_INTERFACE_IMUX10", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_EE2BEG0", - "GTPE2_INT_INTERFACE_IMUX_OUT40", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_WW2END3", - "GTPE2_INT_INTERFACE_IMUX_OUT44", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_SE4BEG3", - "GTPE2_INT_INTERFACE_IMUX2", - "INT_INTERFACE_LOGIC_OUTS13", - "GTPE2_INT_INTERFACE_IMUX_OUT21", - "GTPE2_INT_INTERFACE_IMUX_OUT13", - "INT_INTERFACE_LOGIC_OUTS6", - "GTPE2_INT_INTERFACE_IMUX_OUT8", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_NE4BEG0", - "GTPE2_INT_INTERFACE_IMUX_OUT12", - "GTPE2_INT_INTERFACE_IMUX_OUT11", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH9", - "GTPE2_INT_INTERFACE_IMUX23", - "GTPE2_INT_INTERFACE_IMUX20", - "INT_INTERFACE_NW4END3", - "GTPE2_INT_INTERFACE_IMUX_OUT10", - "GTPE2_INT_INTERFACE_IMUX_OUT24", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WW4C2", - "GTPE2_INT_INTERFACE_IMUX_DELAY27", - "GTPE2_INT_INTERFACE_IMUX7", - "GTPE2_INT_INTERFACE_IMUX_OUT4", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW4END3", - "INT_INTERFACE_LH11", - "INT_INTERFACE_WW4C1", - "GTPE2_INT_INTERFACE_IMUX21", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_LOGIC_OUTS2", - "GTPE2_INT_INTERFACE_IMUX_OUT0", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_LOGIC_OUTS23", - "GTPE2_INT_INTERFACE_IMUX_DELAY23", - "INT_INTERFACE_EE2A2", - "GTPE2_INT_INTERFACE_IMUX_OUT28", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_LOGIC_OUTS14", - "GTPE2_INT_INTERFACE_IMUX_OUT30", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_LOGIC_OUTS_B2", - "INT_INTERFACE_NE2A1", - "GTPE2_INT_INTERFACE_IMUX42", - "GTPE2_INT_INTERFACE_IMUX6", - "INT_INTERFACE_LOGIC_OUTS_B11", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_WW4A1", - "GTPE2_INT_INTERFACE_IMUX_OUT29", - "INT_INTERFACE_WW4A0", - "GTPE2_INT_INTERFACE_IMUX_OUT16", - "INT_INTERFACE_BLOCK_OUTS_B1" - ], - "sites": [], "pips": { - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX13->>GTPE2_INT_INTERFACE_IMUX_DELAY13": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY13", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX13", - "is_pseudo": "0" - }, - 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- }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX5->>GTPE2_INT_INTERFACE_IMUX_OUT5": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT5", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX5", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX20->>GTPE2_INT_INTERFACE_IMUX_OUT20": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT20", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX20", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX29->>GTPE2_INT_INTERFACE_IMUX_DELAY29": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY29", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX29", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS18", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18", - "is_pseudo": "0" - }, - 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"is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY4->>GTPE2_INT_INTERFACE_IMUX_OUT4": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT4", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY4", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY9->>GTPE2_INT_INTERFACE_IMUX_OUT9": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT9", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY9", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS11", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY37->>GTPE2_INT_INTERFACE_IMUX_OUT37": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT37", - "is_directional": "1", - "src_wire": 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"src_wire": "GTPE2_INT_INTERFACE_IMUX31", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX35->>GTPE2_INT_INTERFACE_IMUX_DELAY35": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY35", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX35", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS2", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS12", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX18->>GTPE2_INT_INTERFACE_IMUX_OUT18": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT18", - "is_directional": "1", - "src_wire": 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"GTPE2_INT_INTERFACE_IMUX13", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX37->>GTPE2_INT_INTERFACE_IMUX_OUT37": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT37", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX37", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY12->>GTPE2_INT_INTERFACE_IMUX_OUT12": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT12", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY12", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS3", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B3", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY20->>GTPE2_INT_INTERFACE_IMUX_OUT20": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT20", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY20", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX11->>GTPE2_INT_INTERFACE_IMUX_OUT11": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT11", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX11", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX44->>GTPE2_INT_INTERFACE_IMUX_DELAY44": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY44", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX44", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX7->>GTPE2_INT_INTERFACE_IMUX_OUT7": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT7", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX7", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY14->>GTPE2_INT_INTERFACE_IMUX_OUT14": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT14", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY14", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY27->>GTPE2_INT_INTERFACE_IMUX_OUT27": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT27", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY27", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX0->>GTPE2_INT_INTERFACE_IMUX_DELAY0": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY0", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX0", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS23", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY12" }, "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX41->>GTPE2_INT_INTERFACE_IMUX_DELAY41": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY41", - "is_directional": "1", "src_wire": "GTPE2_INT_INTERFACE_IMUX41", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY32->>GTPE2_INT_INTERFACE_IMUX_OUT32": { "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT32", "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY32", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS10", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX21->>GTPE2_INT_INTERFACE_IMUX_OUT21": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT21", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX21", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX30->>GTPE2_INT_INTERFACE_IMUX_DELAY30": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY30", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX30", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY41" }, "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX11->>GTPE2_INT_INTERFACE_IMUX_DELAY11": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY11", - "is_directional": "1", "src_wire": "GTPE2_INT_INTERFACE_IMUX11", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": { "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS8", "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY11" }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX14->>GTPE2_INT_INTERFACE_IMUX_DELAY14": { + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX33->>GTPE2_INT_INTERFACE_IMUX_OUT33": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX33", "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY14", "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT33" }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX34->>GTPE2_INT_INTERFACE_IMUX_OUT34": { + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX13->>GTPE2_INT_INTERFACE_IMUX_OUT13": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX13", "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT34", "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX34", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY33->>GTPE2_INT_INTERFACE_IMUX_OUT33": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT33", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY33", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY10->>GTPE2_INT_INTERFACE_IMUX_OUT10": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT10", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY10", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX47->>GTPE2_INT_INTERFACE_IMUX_OUT47": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT47", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX47", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX18->>GTPE2_INT_INTERFACE_IMUX_DELAY18": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY18", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX18", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY35->>GTPE2_INT_INTERFACE_IMUX_OUT35": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT35", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY35", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX38->>GTPE2_INT_INTERFACE_IMUX_DELAY38": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY38", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX38", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX30->>GTPE2_INT_INTERFACE_IMUX_OUT30": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT30", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX30", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY44->>GTPE2_INT_INTERFACE_IMUX_OUT44": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT44", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY44", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX45->>GTPE2_INT_INTERFACE_IMUX_DELAY45": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY45", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX45", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX42->>GTPE2_INT_INTERFACE_IMUX_DELAY42": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY42", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX42", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS16", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX36->>GTPE2_INT_INTERFACE_IMUX_DELAY36": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY36", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX36", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX28->>GTPE2_INT_INTERFACE_IMUX_OUT28": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT28", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX28", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX36->>GTPE2_INT_INTERFACE_IMUX_OUT36": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT36", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX36", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX9->>GTPE2_INT_INTERFACE_IMUX_OUT9": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT9", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX9", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX43->>GTPE2_INT_INTERFACE_IMUX_DELAY43": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY43", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX43", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX44->>GTPE2_INT_INTERFACE_IMUX_OUT44": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT44", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX44", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX24->>GTPE2_INT_INTERFACE_IMUX_DELAY24": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY24", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX24", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX8->>GTPE2_INT_INTERFACE_IMUX_DELAY8": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY8", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX8", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX7->>GTPE2_INT_INTERFACE_IMUX_DELAY7": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY7", - "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT13" }, "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX37->>GTPE2_INT_INTERFACE_IMUX_DELAY37": { - "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY37", - "is_directional": "1", "src_wire": "GTPE2_INT_INTERFACE_IMUX37", - "is_pseudo": "0" - }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX22->>GTPE2_INT_INTERFACE_IMUX_DELAY22": { "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY22", "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX22", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY37" }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX39->>GTPE2_INT_INTERFACE_IMUX_OUT39": { + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX5->>GTPE2_INT_INTERFACE_IMUX_DELAY5": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX5", "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT39", "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX39", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY5" }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY31->>GTPE2_INT_INTERFACE_IMUX_OUT31": { + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX2->>GTPE2_INT_INTERFACE_IMUX_OUT2": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX2", "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT31", "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY31", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT2" }, - "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX1->>GTPE2_INT_INTERFACE_IMUX_DELAY1": { + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX33->>GTPE2_INT_INTERFACE_IMUX_DELAY33": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX33", "can_invert": "0", - "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY1", "is_directional": "1", - "src_wire": "GTPE2_INT_INTERFACE_IMUX1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY33" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX36->>GTPE2_INT_INTERFACE_IMUX_DELAY36": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX36", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY36" + }, + "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS16" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX15->>GTPE2_INT_INTERFACE_IMUX_DELAY15": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY15" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX7->>GTPE2_INT_INTERFACE_IMUX_DELAY7": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY7" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX17->>GTPE2_INT_INTERFACE_IMUX_DELAY17": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY17" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX14->>GTPE2_INT_INTERFACE_IMUX_OUT14": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT14" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY17->>GTPE2_INT_INTERFACE_IMUX_OUT17": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT17" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX37->>GTPE2_INT_INTERFACE_IMUX_OUT37": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX37", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT37" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY30->>GTPE2_INT_INTERFACE_IMUX_OUT30": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY30", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT30" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX46->>GTPE2_INT_INTERFACE_IMUX_DELAY46": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX46", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY46" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX32->>GTPE2_INT_INTERFACE_IMUX_DELAY32": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX32", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY32" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX4->>GTPE2_INT_INTERFACE_IMUX_OUT4": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT4" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY34->>GTPE2_INT_INTERFACE_IMUX_OUT34": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY34", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT34" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY4->>GTPE2_INT_INTERFACE_IMUX_OUT4": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT4" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX26->>GTPE2_INT_INTERFACE_IMUX_OUT26": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX26", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT26" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY35->>GTPE2_INT_INTERFACE_IMUX_OUT35": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY35", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT35" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX19->>GTPE2_INT_INTERFACE_IMUX_OUT19": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT19" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX32->>GTPE2_INT_INTERFACE_IMUX_OUT32": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX32", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT32" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX30->>GTPE2_INT_INTERFACE_IMUX_DELAY30": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX30", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY30" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX25->>GTPE2_INT_INTERFACE_IMUX_OUT25": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX25", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT25" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX36->>GTPE2_INT_INTERFACE_IMUX_OUT36": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX36", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT36" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX44->>GTPE2_INT_INTERFACE_IMUX_DELAY44": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX44", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY44" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX41->>GTPE2_INT_INTERFACE_IMUX_OUT41": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX41", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT41" }, "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY36->>GTPE2_INT_INTERFACE_IMUX_OUT36": { - "can_invert": "0", - "dst_wire": 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}, + "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS23" + }, + "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS12" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX16->>GTPE2_INT_INTERFACE_IMUX_DELAY16": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY16" + }, + "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS5" + }, + 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"is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT38" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX21->>GTPE2_INT_INTERFACE_IMUX_DELAY21": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY21" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX12->>GTPE2_INT_INTERFACE_IMUX_OUT12": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT12" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX17->>GTPE2_INT_INTERFACE_IMUX_OUT17": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT17" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX11->>GTPE2_INT_INTERFACE_IMUX_OUT11": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX11", + "can_invert": "0", + "is_directional": "1", + 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"can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT21" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX47->>GTPE2_INT_INTERFACE_IMUX_DELAY47": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX47", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY47" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY41->>GTPE2_INT_INTERFACE_IMUX_OUT41": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY41", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT41" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY26->>GTPE2_INT_INTERFACE_IMUX_OUT26": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY26", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT26" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX19->>GTPE2_INT_INTERFACE_IMUX_DELAY19": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY19" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX14->>GTPE2_INT_INTERFACE_IMUX_DELAY14": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY14" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX38->>GTPE2_INT_INTERFACE_IMUX_DELAY38": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX38", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY38" + }, + "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS17" + }, + "GTP_INT_INTERFACE.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS15" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX39->>GTPE2_INT_INTERFACE_IMUX_DELAY39": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX39", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY39" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY16->>GTPE2_INT_INTERFACE_IMUX_OUT16": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT16" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY40->>GTPE2_INT_INTERFACE_IMUX_OUT40": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY40", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT40" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY13->>GTPE2_INT_INTERFACE_IMUX_OUT13": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT13" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY25->>GTPE2_INT_INTERFACE_IMUX_OUT25": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY25", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT25" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX35->>GTPE2_INT_INTERFACE_IMUX_DELAY35": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX35", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY35" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY43->>GTPE2_INT_INTERFACE_IMUX_OUT43": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY43", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT43" + }, + "GTP_INT_INTERFACE.GTPE2_INT_INTERFACE_IMUX_DELAY47->>GTPE2_INT_INTERFACE_IMUX_OUT47": { + "src_wire": "GTPE2_INT_INTERFACE_IMUX_DELAY47", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GTPE2_INT_INTERFACE_IMUX_OUT47" } }, - "tile_type": "GTP_INT_INTERFACE" + "wires": [ + "INT_INTERFACE_SE4BEG1", + "GTPE2_INT_INTERFACE_IMUX_OUT27", + "INT_INTERFACE_WL1END2", + "GTPE2_INT_INTERFACE_IMUX21", + "INT_INTERFACE_LOGIC_OUTS_B12", + "GTPE2_INT_INTERFACE_IMUX_DELAY22", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_LOGIC_OUTS_B10", + "GTPE2_INT_INTERFACE_IMUX1", + "INT_INTERFACE_SW2A3", + "GTPE2_INT_INTERFACE_IMUX_DELAY46", + "GTPE2_INT_INTERFACE_IMUX_DELAY42", + "INT_INTERFACE_LOGIC_OUTS_B22", + "INT_INTERFACE_LOGIC_OUTS4", + "INT_INTERFACE_WW2A2", + "GTPE2_INT_INTERFACE_IMUX_OUT17", + "INT_INTERFACE_LOGIC_OUTS_B11", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_LOGIC_OUTS18", + "GTPE2_INT_INTERFACE_IMUX43", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE2BEG3", + "GTPE2_INT_INTERFACE_IMUX_OUT19", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_LH11", + "GTPE2_INT_INTERFACE_IMUX_DELAY3", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_BYP7", + "GTPE2_INT_INTERFACE_IMUX_OUT14", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END1", + "GTPE2_INT_INTERFACE_IMUX2", + "INT_INTERFACE_NE2A0", + "GTPE2_INT_INTERFACE_IMUX6", + "GTPE2_INT_INTERFACE_IMUX_DELAY32", + "GTPE2_INT_INTERFACE_IMUX_DELAY15", + "INT_INTERFACE_LOGIC_OUTS_B7", + "INT_INTERFACE_EL1BEG0", + "GTPE2_INT_INTERFACE_IMUX38", + "GTPE2_INT_INTERFACE_IMUX_DELAY33", + "GTPE2_INT_INTERFACE_IMUX35", + "INT_INTERFACE_CLK0", + "GTPE2_INT_INTERFACE_IMUX_DELAY18", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_BYP0", + "GTPE2_INT_INTERFACE_IMUX_OUT29", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_FAN6", + "GTPE2_INT_INTERFACE_IMUX_DELAY39", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_SW4END0", + "GTPE2_INT_INTERFACE_IMUX_OUT34", + "INT_INTERFACE_WW4C2", + "GTPE2_INT_INTERFACE_IMUX_DELAY45", + "INT_INTERFACE_EE4C2", + "GTPE2_INT_INTERFACE_IMUX_DELAY29", + "GTPE2_INT_INTERFACE_IMUX4", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_EL1BEG1", + "GTPE2_INT_INTERFACE_IMUX8", + "GTPE2_INT_INTERFACE_IMUX_DELAY8", + "INT_INTERFACE_LH6", + "GTPE2_INT_INTERFACE_IMUX_DELAY9", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_LOGIC_OUTS14", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_LOGIC_OUTS11", + "GTPE2_INT_INTERFACE_IMUX_OUT20", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_LOGIC_OUTS10", + "INT_INTERFACE_FAN7", + "GTPE2_INT_INTERFACE_IMUX_DELAY40", + "INT_INTERFACE_LH4", + "INT_INTERFACE_LH12", + "GTPE2_INT_INTERFACE_IMUX_OUT11", + "GTPE2_INT_INTERFACE_IMUX_OUT30", + "INT_INTERFACE_LOGIC_OUTS23", + "GTPE2_INT_INTERFACE_IMUX_OUT37", + "INT_INTERFACE_WW4END1", + "GTPE2_INT_INTERFACE_IMUX11", + "GTPE2_INT_INTERFACE_IMUX_OUT16", + "GTPE2_INT_INTERFACE_IMUX27", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_FAN4", + "GTPE2_INT_INTERFACE_IMUX_OUT47", + "INT_INTERFACE_BYP3", + "GTPE2_INT_INTERFACE_IMUX_DELAY12", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_BYP5", + "GTPE2_INT_INTERFACE_IMUX_OUT40", + "GTPE2_INT_INTERFACE_IMUX_DELAY5", + "GTPE2_INT_INTERFACE_IMUX_OUT9", + "GTPE2_INT_INTERFACE_IMUX_OUT45", + "GTPE2_INT_INTERFACE_IMUX_OUT44", + "GTPE2_INT_INTERFACE_IMUX29", + "GTPE2_INT_INTERFACE_IMUX19", + "GTPE2_INT_INTERFACE_IMUX_DELAY23", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_NE2A3", + "GTPE2_INT_INTERFACE_IMUX9", + "GTPE2_INT_INTERFACE_IMUX_OUT46", + "INT_INTERFACE_SE2A2", + "GTPE2_INT_INTERFACE_IMUX_DELAY43", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_LOGIC_OUTS_B4", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_LOGIC_OUTS_B17", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_LOGIC_OUTS7", + "GTPE2_INT_INTERFACE_IMUX_OUT15", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_FAN5", + "GTPE2_INT_INTERFACE_IMUX_OUT2", + "GTPE2_INT_INTERFACE_IMUX20", + "GTPE2_INT_INTERFACE_IMUX_DELAY14", + "GTPE2_INT_INTERFACE_IMUX32", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_LH9", + "GTPE2_INT_INTERFACE_IMUX_DELAY6", + "GTPE2_INT_INTERFACE_IMUX24", + "INT_INTERFACE_LH3", + "INT_INTERFACE_NW4END1", + "GTPE2_INT_INTERFACE_IMUX_OUT24", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_LOGIC_OUTS22", + "INT_INTERFACE_WW2A0", + "GTPE2_INT_INTERFACE_IMUX_DELAY34", + "INT_INTERFACE_NE4C3", + "GTPE2_INT_INTERFACE_IMUX31", + "GTPE2_INT_INTERFACE_IMUX39", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_B15", + "GTPE2_INT_INTERFACE_IMUX34", + "INT_INTERFACE_LOGIC_OUTS13", + "GTPE2_INT_INTERFACE_IMUX_DELAY1", + "INT_INTERFACE_WR1END1", + "GTPE2_INT_INTERFACE_IMUX_OUT33", + "INT_INTERFACE_LOGIC_OUTS_B9", + "INT_INTERFACE_BLOCK_OUTS_B3", + "GTPE2_INT_INTERFACE_IMUX_DELAY7", + "GTPE2_INT_INTERFACE_IMUX_DELAY47", + "GTPE2_INT_INTERFACE_IMUX41", + "INT_INTERFACE_WW4A1", + "GTPE2_INT_INTERFACE_IMUX10", + "INT_INTERFACE_SW2A2", + "GTPE2_INT_INTERFACE_IMUX_OUT41", + "GTPE2_INT_INTERFACE_IMUX_DELAY2", + "GTPE2_INT_INTERFACE_IMUX_DELAY30", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LH8", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_WW4B1", + "GTPE2_INT_INTERFACE_IMUX7", + "INT_INTERFACE_LOGIC_OUTS1", + "GTPE2_INT_INTERFACE_IMUX_DELAY38", + "INT_INTERFACE_LOGIC_OUTS0", + "GTPE2_INT_INTERFACE_IMUX33", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS20", + "INT_INTERFACE_LOGIC_OUTS_B20", + "INT_INTERFACE_NE4BEG2", + "GTPE2_INT_INTERFACE_IMUX_DELAY37", + "GTPE2_INT_INTERFACE_IMUX_DELAY26", + "INT_INTERFACE_LOGIC_OUTS3", + "GTPE2_INT_INTERFACE_IMUX_DELAY24", + "INT_INTERFACE_LOGIC_OUTS_B14", + "INT_INTERFACE_BLOCK_OUTS_B2", + "GTPE2_INT_INTERFACE_IMUX_DELAY35", + "INT_INTERFACE_LOGIC_OUTS_B1", + "INT_INTERFACE_WW2END2", + "GTPE2_INT_INTERFACE_IMUX_DELAY16", + "INT_INTERFACE_LOGIC_OUTS2", + "GTPE2_INT_INTERFACE_IMUX_DELAY13", + "INT_INTERFACE_FAN0", + "GTPE2_INT_INTERFACE_IMUX26", + "INT_INTERFACE_EE2BEG1", + "GTPE2_INT_INTERFACE_IMUX47", + "GTPE2_INT_INTERFACE_IMUX22", + "GTPE2_INT_INTERFACE_IMUX_OUT10", + "INT_INTERFACE_MONITOR_P", + "GTPE2_INT_INTERFACE_IMUX_OUT6", + "INT_INTERFACE_LOGIC_OUTS16", + "INT_INTERFACE_NW4A1", + "GTPE2_INT_INTERFACE_IMUX_DELAY17", + "GTPE2_INT_INTERFACE_IMUX45", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_LOGIC_OUTS8", + "GTPE2_INT_INTERFACE_IMUX_OUT4", + "INT_INTERFACE_LOGIC_OUTS9", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "GTPE2_INT_INTERFACE_IMUX_DELAY10", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_EE4C3", + "GTPE2_INT_INTERFACE_IMUX_OUT7", + "GTPE2_INT_INTERFACE_IMUX13", + "GTPE2_INT_INTERFACE_IMUX5", + "GTPE2_INT_INTERFACE_IMUX_OUT8", + "GTPE2_INT_INTERFACE_IMUX_DELAY27", + "INT_INTERFACE_WL1END3", + "GTPE2_INT_INTERFACE_IMUX_OUT32", + "INT_INTERFACE_SW4A2", + "GTPE2_INT_INTERFACE_IMUX_DELAY41", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_LOGIC_OUTS_B18", + "GTPE2_INT_INTERFACE_IMUX37", + "GTPE2_INT_INTERFACE_IMUX_OUT18", + "INT_INTERFACE_SE2A0", + "GTPE2_INT_INTERFACE_IMUX_OUT42", + "INT_INTERFACE_NW2A1", + "GTPE2_INT_INTERFACE_IMUX_OUT31", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_LH5", + "INT_INTERFACE_LOGIC_OUTS_B3", + "GTPE2_INT_INTERFACE_IMUX30", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_NW2A3", + "GTPE2_INT_INTERFACE_IMUX_DELAY4", + "INT_INTERFACE_LOGIC_OUTS19", + "GTPE2_INT_INTERFACE_IMUX_DELAY31", + "INT_INTERFACE_LOGIC_OUTS_B5", + "GTPE2_INT_INTERFACE_IMUX_OUT25", + "GTPE2_INT_INTERFACE_IMUX_OUT28", + "GTPE2_INT_INTERFACE_IMUX_OUT22", + "INT_INTERFACE_EL1BEG3", + "GTPE2_INT_INTERFACE_IMUX15", + "GTPE2_INT_INTERFACE_IMUX_DELAY0", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS_B6", + "INT_INTERFACE_LOGIC_OUTS_B2", + "GTPE2_INT_INTERFACE_IMUX23", + "INT_INTERFACE_LOGIC_OUTS_B19", + "INT_INTERFACE_SE4BEG3", + "GTPE2_INT_INTERFACE_IMUX_OUT13", + "GTPE2_INT_INTERFACE_IMUX_OUT5", + "GTPE2_INT_INTERFACE_IMUX_OUT39", + "GTPE2_INT_INTERFACE_IMUX16", + "GTPE2_INT_INTERFACE_IMUX_DELAY36", + "INT_INTERFACE_NE4C2", + "GTPE2_INT_INTERFACE_IMUX_DELAY44", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_LOGIC_OUTS_B13", + "GTPE2_INT_INTERFACE_IMUX14", + "GTPE2_INT_INTERFACE_IMUX18", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_EE2A3", + "GTPE2_INT_INTERFACE_IMUX3", + "GTPE2_INT_INTERFACE_IMUX_OUT1", + "INT_INTERFACE_WW4A0", + "GTPE2_INT_INTERFACE_IMUX12", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_MONITOR_N", + "GTPE2_INT_INTERFACE_IMUX_OUT35", + "GTPE2_INT_INTERFACE_IMUX44", + "INT_INTERFACE_LH7", + "GTPE2_INT_INTERFACE_IMUX_DELAY19", + "GTPE2_INT_INTERFACE_IMUX_OUT0", + "GTPE2_INT_INTERFACE_IMUX_DELAY11", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_WW2A1", + "GTPE2_INT_INTERFACE_IMUX25", + "INT_INTERFACE_LOGIC_OUTS21", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_NW4END2", + "GTPE2_INT_INTERFACE_IMUX_DELAY21", + "GTPE2_INT_INTERFACE_IMUX_OUT38", + "INT_INTERFACE_LOGIC_OUTS12", + "INT_INTERFACE_EE4B3", + "GTPE2_INT_INTERFACE_IMUX46", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_WW4END3", + "GTPE2_INT_INTERFACE_IMUX_DELAY20", + "GTPE2_INT_INTERFACE_IMUX_OUT23", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_LH2", + "INT_INTERFACE_SW2A1", + "GTPE2_INT_INTERFACE_IMUX_DELAY28", + "GTPE2_INT_INTERFACE_IMUX_DELAY25", + "GTPE2_INT_INTERFACE_IMUX28", + "INT_INTERFACE_WW4B2", + "GTPE2_INT_INTERFACE_IMUX0", + "INT_INTERFACE_EE4C0", + "GTPE2_INT_INTERFACE_IMUX_OUT3", + "GTPE2_INT_INTERFACE_IMUX_OUT36", + "GTPE2_INT_INTERFACE_IMUX36", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_WW4END0", + "GTPE2_INT_INTERFACE_IMUX_OUT21", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS15", + "GTPE2_INT_INTERFACE_IMUX40", + "INT_INTERFACE_LOGIC_OUTS6", + "GTPE2_INT_INTERFACE_IMUX_OUT12", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_EE2A0", + "GTPE2_INT_INTERFACE_IMUX42", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_LOGIC_OUTS_B16", + "GTPE2_INT_INTERFACE_IMUX_OUT43", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_BLOCK_OUTS_B0", + "GTPE2_INT_INTERFACE_IMUX_OUT26", + "INT_INTERFACE_BLOCK_OUTS_B1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_ER1BEG1", + "GTPE2_INT_INTERFACE_IMUX17" + ], + "tile_type": "GTP_INT_INTERFACE", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_BRAM.json b/artix7/tile_type_HCLK_BRAM.json index 93604a6..b3e45ed 100644 --- a/artix7/tile_type_HCLK_BRAM.json +++ b/artix7/tile_type_HCLK_BRAM.json @@ -1,108 +1,108 @@ { - "wires": [ - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11", - "HCLK_BRAM_PMVBRAM_SELECT2", - "HCLK_BRAM_CK_IN10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14", - "HCLK_BRAM_CK_IN11", - "HCLK_BRAM_CK_BUFHCLK3", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14", - "HCLK_BRAM_CK_BUFHCLK5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0", - "HCLK_BRAM_CK_IN3", - "HCLK_BRAM_CK_IN2", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13", - "HCLK_BRAM_PMVBRAM_ODIV2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11", - "HCLK_BRAM_CK_BUFHCLK8", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13", - "HCLK_BRAM_PMVBRAM_SELECT4", - "HCLK_BRAM_CK_BUFHCLK10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14", - "HCLK_BRAM_CK_BUFHCLK6", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4", - "HCLK_BRAM_CK_BUFRCLK3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5", - "HCLK_BRAM_CK_IN9", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13", - "HCLK_BRAM_CK_IN4", - "HCLK_BRAM_CASCADEB_R", - "HCLK_BRAM_CK_BUFHCLK7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7", - "HCLK_BRAM_CK_BUFRCLK0", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0", - "HCLK_BRAM_CASCADEB_L", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12", - "HCLK_BRAM_CK_IN12", - "HCLK_BRAM_PMVBRAM_SELECT3", - "HCLK_BRAM_CK_BUFHCLK4", - "HCLK_BRAM_CK_BUFRCLK2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0", - "HCLK_BRAM_CK_BUFHCLK1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4", - "HCLK_BRAM_CK_IN8", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3", - "HCLK_BRAM_CK_IN1", - "HCLK_BRAM_CK_IN0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2", - "HCLK_BRAM_CK_BUFRCLK1", - "HCLK_BRAM_CASCADEA_R", - "HCLK_BRAM_CK_BUFHCLK9", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0", - "HCLK_BRAM_CK_IN13", - "HCLK_BRAM_CASCADEA_L", - "HCLK_BRAM_CK_BUFHCLK2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11", - "HCLK_BRAM_PMVBRAM_ODIV4", - "HCLK_BRAM_PMVBRAM_O", - "HCLK_BRAM_CK_IN7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7", - "HCLK_BRAM_CK_BUFHCLK0", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6", - "HCLK_BRAM_CK_IN5", - "HCLK_BRAM_CK_BUFHCLK11", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9", - "HCLK_BRAM_CK_IN6", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6", - "HCLK_BRAM_PMVBRAM_SELECT1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" - ], - "sites": [], "pips": {}, - "tile_type": "HCLK_BRAM" + "wires": [ + "HCLK_BRAM_CK_BUFRCLK0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7", + "HCLK_BRAM_CK_IN3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8", + "HCLK_BRAM_CK_IN10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13", + "HCLK_BRAM_CK_BUFRCLK3", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1", + "HCLK_BRAM_CK_BUFHCLK5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4", + "HCLK_BRAM_CK_BUFHCLK0", + "HCLK_BRAM_CASCADEB_L", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13", + "HCLK_BRAM_CK_BUFHCLK3", + "HCLK_BRAM_CK_BUFHCLK9", + "HCLK_BRAM_CK_IN6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1", + "HCLK_BRAM_PMVBRAM_SELECT4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9", + "HCLK_BRAM_CK_BUFRCLK2", + "HCLK_BRAM_PMVBRAM_O", + "HCLK_BRAM_CK_BUFHCLK1", + "HCLK_BRAM_CASCADEA_L", + "HCLK_BRAM_CASCADEB_R", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3", + "HCLK_BRAM_CK_BUFHCLK10", + "HCLK_BRAM_PMVBRAM_SELECT3", + "HCLK_BRAM_CK_IN9", + "HCLK_BRAM_PMVBRAM_ODIV2", + "HCLK_BRAM_CK_IN11", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6", + "HCLK_BRAM_PMVBRAM_SELECT2", + "HCLK_BRAM_CK_IN8", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9", + "HCLK_BRAM_CK_BUFHCLK4", + "HCLK_BRAM_CK_IN13", + "HCLK_BRAM_CK_BUFHCLK8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6", + "HCLK_BRAM_CK_IN1", + "HCLK_BRAM_CK_BUFRCLK1", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11", + "HCLK_BRAM_PMVBRAM_ODIV4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5", + "HCLK_BRAM_CK_BUFHCLK2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10", + "HCLK_BRAM_CK_IN2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4", + "HCLK_BRAM_CK_BUFHCLK7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2", + "HCLK_BRAM_CK_IN7", + "HCLK_BRAM_PMVBRAM_SELECT1", + "HCLK_BRAM_CK_IN5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14", + "HCLK_BRAM_CK_IN0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10", + "HCLK_BRAM_CK_IN12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0", + "HCLK_BRAM_CK_IN4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14", + "HCLK_BRAM_CASCADEA_R", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7", + "HCLK_BRAM_CK_BUFHCLK6", + "HCLK_BRAM_CK_BUFHCLK11", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" + ], + "tile_type": "HCLK_BRAM", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_CLB.json b/artix7/tile_type_HCLK_CLB.json index 58fd4e3..e4978dd 100644 --- a/artix7/tile_type_HCLK_CLB.json +++ b/artix7/tile_type_HCLK_CLB.json @@ -1,49 +1,49 @@ { + "pips": {}, "wires": [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_CLB_CK_IN0", - "HCLK_CLB_CK_IN3", - "HCLK_CLB_CK_IN7", - "HCLK_CLB_PERFCLK0", - "HCLK_CLB_CK_IN5", - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CLB_CK_IN12", - "HCLK_CLB_CK_IN2", - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_CLB_REFCK_EASTCLK1", - "HCLK_CLB_COUT1_L", - "HCLK_CLB_CK_IN10", - "HCLK_CLB_REFCK_WESTCLK1", - "HCLK_CLB_PERFCLK1", - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CLB_CK_IN4", - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CLB_CK_IN1", - "HCLK_CLB_PERFCLK2", - "HCLK_CLB_PERFCLK3", - "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CLB_COUT1_R", "HCLK_CLB_CK_BUFHCLK0", - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CLB_CK_IN8", + "HCLK_CLB_CK_IN1", + "HCLK_CLB_CK_IN3", + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CLB_CK_IN13", "HCLK_CLB_CK_BUFHCLK10", - "HCLK_CLB_CK_IN6", - "HCLK_CLB_REFCK_EASTCLK0", + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CLB_CK_BUFRCLK1", "HCLK_CLB_REFCK_WESTCLK0", + "HCLK_CLB_COUT1_L", "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CLB_REFCK_EASTCLK1", + "HCLK_CLB_PERFCLK2", + "HCLK_CLB_REFCK_EASTCLK0", + "HCLK_CLB_CK_IN2", + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CLB_CK_IN8", + "HCLK_CLB_PERFCLK1", + "HCLK_CLB_CK_IN12", + "HCLK_CLB_CK_IN6", + "HCLK_CLB_CK_IN10", + "HCLK_CLB_PERFCLK3", + "HCLK_CLB_CK_BUFHCLK3", "HCLK_CLB_CK_IN11", "HCLK_CLB_COUT0_R", + "HCLK_CLB_PERFCLK0", + "HCLK_CLB_CK_BUFRCLK2", "HCLK_CLB_CK_IN9", - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_CLB_CK_IN13", - "HCLK_CLB_COUT0_L", - "HCLK_CLB_COUT1_R" + "HCLK_CLB_CK_IN0", + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CLB_CK_IN7", + "HCLK_CLB_CK_IN4", + "HCLK_CLB_CK_IN5", + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CLB_REFCK_WESTCLK1", + "HCLK_CLB_COUT0_L" ], - "sites": [], - "pips": {}, - "tile_type": "HCLK_CLB" + "tile_type": "HCLK_CLB", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_CMT.json b/artix7/tile_type_HCLK_CMT.json index 60d698e..e779277 100644 --- a/artix7/tile_type_HCLK_CMT.json +++ b/artix7/tile_type_HCLK_CMT.json @@ -1,7067 +1,7067 @@ { - "wires": [ - "HCLK_CMT_PHY_CONTROL_IRANKA1", - "HCLK_CMT_MUX_CLK_MMCM5", - "HCLK_CMT_PHASEREF_BELOW0", - "HCLK_CMT_MUX_CLK_MMCM2", - "HCLK_CMT_MUX_CLK_LEAF_UP1", - "HCLK_CMT_CK_IN10", - "HCLK_CMT_MUX_CLKINT_3", - "HCLK_CMT_BUFMRCE_CEINP0", - "HCLK_CMT_PHASERINB_ICLK", - "HCLK_CMT_CK_IN9", - "HCLK_CMT_CK_IN8", - "HCLK_CMT_CK_IN2", - "HCLK_CMT_PHASERINC_ICLKDIV", - "HCLK_CMT_ECALIB1", - "HCLK_CMT_MUX_CLK_MMCM7", - "HCLK_CMT_CK_BUFRCLK3", - "HCLK_CMT_FREQ_REF_NS0", - "HCLK_CMT_MUX_CLK_MMCM13", - "HCLK_CMT_MUX_CLK_11", - "HCLK_CMT_MUX_MMCM_CLKIN2", - "HCLK_CMT_BUFMR_CE1", - "HCLK_CMT_MUX_CLK_8", - "HCLK_CMT_PHY_SYNC_BB", - "HCLK_CMT_OBURSTPENDING0", - "HCLK_CMT_PHASEREF_ABOVE1", - "HCLK_CMT_MUX_CLK_MMCM11", - "HCLK_CMT_PHASEROUTD_OCLK", - "HCLK_CMT_MUX_CLK_PLL0", - "HCLK_CMT_BUFMR_PHASEREF0", - "HCLK_CMT_IBURSTPENDING0", - "HCLK_CMT_MUX_CLKINT_0", - "HCLK_CMT_BUFMR_CE0", - "HCLK_CMT_PHASEROUTC_OCLK", - "HCLK_CMT_PHASERINA_ICLK", - "HCLK_CMT_MUX_MMCM_CLKIN1", - "HCLK_CMT_CK_BUFHCLK2", - "HCLK_CMT_MUX_PHSR_PERFCLK3", - "HCLK_CMT_PHY_CONTROL_IRANKB0", - "HCLK_CMT_MUX_PHSR_PERFCLK0", - "HCLK_CMT_CCIO1", - "HCLK_CMT_PHY_CONTROL_IRANKB1", - "HCLK_CMT_MUX_CLK_LEAF_DN1", - "HCLK_CMT_CCIO0", - "HCLK_CMT_MUX_MMCM_MUXED3", - "HCLK_CMT_CK_IN0", - "HCLK_CMT_MUX_CLK_PLL6", - "HCLK_CMT_CK_IN6", - "HCLK_CMT_PHASEROUTA_OCLK1X_90", - "HCLK_CMT_CK_IN3", - "HCLK_CMT_MUX_CLK_9", - "HCLK_CMT_MUX_MMCM_MUXED2", - "HCLK_CMT_BUFMRCE_O0", - "HCLK_CMT_MUX_OUT_FREQ_REF0", - "HCLK_CMT_FREQ_REF_NS3", - "HCLK_CMT_MUX_CLK_PLL2", - "HCLK_CMT_PHASEREF_BELOW1", - "HCLK_CMT_CK_BUFHCLK3", - "HCLK_CMT_PREF_BOUNCE3", - "HCLK_CMT_MUX_CLK_MMCM8", - "HCLK_CMT_MUX_PLLE2_CLKIN1", - "HCLK_CMT_PHASEROUTC_OCLKDIV", - "HCLK_CMT_MUX_MMCM_MUXED0", - "HCLK_CMT_PREF_CLKOUT", - "HCLK_CMT_MUX_CLK_MMCM6", - "HCLK_CMT_PREF_BOUNCE2", - "HCLK_CMT_MUX_CLK_4", - "HCLK_CMT_CK_BUFRCLK1", - "HCLK_CMT_CK_IN13", - "HCLK_CMT_MUX_CLK_13", - "HCLK_CMT_MUX_CLK_MMCM9", - "HCLK_CMT_MUX_CLK_3", - "HCLK_CMT_IBURST1", - "HCLK_CMT_OBURSTPENDING1", - "HCLK_CMT_FREQ_PHASER_REFMUX_1", - "HCLK_CMT_BUFMRCE_CEINP1", - "HCLK_CMT_MUX_MMCM_MUXED1", - "HCLK_CMT_PHASEROUTA_OCLK", - "HCLK_CMT_MUX_OUT_FREQ_REF2", - "HCLK_CMT_MUX_CLK_MMCM3", - "HCLK_CMT_CCIO2", - "HCLK_CMT_MUX_PHSR_PERFCLK1", - "HCLK_CMT_FREQ_REF_NS1", - "HCLK_CMT_PHASERIN_RCLK3", - "HCLK_CMT_CK_BUFHCLK6", - "HCLK_CMT_MUX_CLK_5", - "HCLK_CMT_PHASEROUTB_OCLK", - "HCLK_CMT_MUX_CLK_PLL5", - "HCLK_CMT_PREF_TMUXOUT", - "HCLK_CMT_MUX_CLK_10", - "HCLK_CMT_MUX_CLKINT_1", - "HCLK_CMT_MUX_CLK_2", - "HCLK_CMT_MUX_CLK_MMCM0", - "HCLK_CMT_FREQ_PHASER_REFMUX_2", - "HCLK_CMT_FREQ_PHASER_REFMUX_0", - "HCLK_CMT_CK_BUFHCLK0", - "HCLK_CMT_MUX_CLK_0", - "HCLK_CMT_CK_BUFHCLK11", - "HCLK_CMT_MUX_MMCM_CLKFBIN", - "HCLK_CMT_MUX_CLKINT_2", - "HCLK_CMT_PHASEROUTB_OCLK1X_90", - "HCLK_CMT_PREF_BOUNCE1", - "HCLK_CMT_IBURSTPENDING1", - "HCLK_CMT_MUX_CLK_PLL4", - "HCLK_CMT_MUX_CLK_PLL1", - "HCLK_CMT_CCIO3", - "HCLK_CMT_MUX_CLK_PLL3", - "HCLK_CMT_MUX_CLK_7", - "HCLK_CMT_PHASEROUTD_OCLKDIV", - "HCLK_CMT_PHASEROUTB_OCLKDIV", - "HCLK_CMT_MUX_OUT_FREQ_REF1", - "HCLK_CMT_MUX_PHSR_PERFCLK2", - "HCLK_CMT_PHASEREF_ABOVE0", - "HCLK_CMT_CK_BUFRCLK0", - "HCLK_CMT_MUX_CLK_MMCM12", - "HCLK_CMT_PHASERINA_ICLKDIV", - "HCLK_CMT_PHASERINB_ICLKDIV", - "HCLK_CMT_CK_BUFHCLK10", - "HCLK_CMT_CK_IN1", - "HCLK_CMT_PHASEROUTD_OCLK1X_90", - "HCLK_CMT_CK_BUFRCLK2", - "HCLK_CMT_MUX_CLK_1", - "HCLK_CMT_PHASERIND_ICLK", - "HCLK_CMT_BUFMR_PHASEREF1", - "HCLK_CMT_CK_BUFHCLK1", - "HCLK_CMT_PHASEROUTA_OCLKDIV", - "HCLK_CMT_CK_IN12", - "HCLK_CMT_CK_BUFHCLK7", - "HCLK_CMT_PHASERIN_RCLK0", - "HCLK_CMT_PHASERIN_RCLK1", - "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "HCLK_CMT_MUX_CLK_6", - "HCLK_CMT_MUX_CLK_12", - "HCLK_CMT_CK_BUFHCLK4", - "HCLK_CMT_PREF_BOUNCE0", - "HCLK_CMT_CK_BUFHCLK8", - "HCLK_CMT_CK_IN11", - "HCLK_CMT_MUX_CLK_MMCM10", - "HCLK_CMT_PHY_CONTROL_IRANKA0", - "HCLK_CMT_MUX_PLLE2_CLKIN2", - "HCLK_CMT_MUX_CLK_MMCM1", - "HCLK_CMT_FREQ_REF_NS2", - "HCLK_CMT_IBURST0", - "HCLK_CMT_PHASEROUTC_OCLK1X_90", - "HCLK_CMT_MUX_CLK_PLL7", - "HCLK_CMT_BUFMRCE_O1", - "HCLK_CMT_CK_IN5", - "HCLK_CMT_CK_BUFHCLK5", - "HCLK_CMT_PHASERINC_ICLK", - "HCLK_CMT_MUX_CLK_MMCM4", - "HCLK_CMT_MUX_OUT_FREQ_REF3", - "HCLK_CMT_BUFMR_INP0", - "HCLK_CMT_PHASERIND_ICLKDIV", - "HCLK_CMT_BUFMR_INP1", - "HCLK_CMT_MUX_CLK_LEAF_UP0", - "HCLK_CMT_ECALIB0", - "HCLK_CMT_PHASERIN_RCLK2", - "HCLK_CMT_CK_BUFHCLK9", - "HCLK_CMT_CK_IN7", - "HCLK_CMT_CK_IN4", - "HCLK_CMT_MUX_CLK_LEAF_DN0" - ], - "sites": [ - { - "prefix": "BUFMRCE", - "y_coord": 1, - "type": "BUFMRCE", - "site_pins": { - "I": "HCLK_CMT_BUFMR_INP1", - "O": "HCLK_CMT_BUFMRCE_O1", - "CE": "HCLK_CMT_BUFMRCE_CEINP1" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "BUFMRCE", - "y_coord": 0, - "type": "BUFMRCE", - "site_pins": { - "I": "HCLK_CMT_BUFMR_INP0", - "O": "HCLK_CMT_BUFMRCE_O0", - "CE": "HCLK_CMT_BUFMRCE_CEINP0" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_12": { + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_FREQ_REF_NS0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_BUFMR_CE0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLKINT_2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0", - "is_directional": "1", - "src_wire": "HCLK_CMT_BUFMRCE_O0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_BUFMR_CE1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_FREQ_REF_NS1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_FREQ_REF_NS2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_9": { + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", + "src_wire": "HCLK_CMT_CCIO2", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1", - "is_directional": "1", - "src_wire": "HCLK_CMT_BUFMRCE_O1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_9": { + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLKINT_3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", + "src_wire": "HCLK_CMT_CCIO2", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" }, - "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN5", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_FREQ_REF_NS3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_IN9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_7": { + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_1", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN12", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN8", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_IN11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_11": { + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_10": { + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", + "src_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_9": { + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", + "src_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_10": { + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_10", + "src_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_3": { + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", + "src_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_2": { + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", - "is_directional": "1", "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_8": { + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_8", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" }, - "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" }, - "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_11": { + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_3": { + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_3", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" }, - "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_9": { + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_9", + "src_wire": "HCLK_CMT_CCIO3", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_BUFMRCE_O0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_0", - "is_directional": "1", "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_BUFMRCE_O1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_BUFMR_CE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_6", - "is_directional": "1", "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_4", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_BUFMR_CE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_IN10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_IN5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_7" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN4->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_5" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_1" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_12" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_4" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_IN6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_IN8->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN7->>HCLK_CMT_MUX_CLK_0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_0" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN9->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_9" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_6" + }, + "HCLK_CMT.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_CLK_11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_11" + }, + "HCLK_CMT.HCLK_CMT_CK_IN13->>HCLK_CMT_MUX_CLK_8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_8" + }, + "HCLK_CMT.HCLK_CMT_CK_IN11->>HCLK_CMT_MUX_CLK_10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_10" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_3" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS3" + }, + "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT.HCLK_CMT_CK_IN12->>HCLK_CMT_MUX_CLK_13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_IN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_13" + }, + "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" } }, - "tile_type": "HCLK_CMT" + "wires": [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_CMT_MUX_CLK_MMCM11", + "HCLK_CMT_MUX_CLK_5", + "HCLK_CMT_PHASEROUTD_OCLK1X_90", + "HCLK_CMT_MUX_CLK_10", + "HCLK_CMT_MUX_MMCM_MUXED0", + "HCLK_CMT_CK_IN2", + "HCLK_CMT_MUX_MMCM_CLKIN2", + "HCLK_CMT_MUX_CLK_1", + "HCLK_CMT_PHASERIN_RCLK3", + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_CMT_MUX_CLKINT_2", + "HCLK_CMT_PHASEROUTA_OCLK", + "HCLK_CMT_CCIO2", + "HCLK_CMT_PHASEROUTA_OCLKDIV", + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_CMT_PREF_BOUNCE2", + "HCLK_CMT_MUX_CLK_MMCM3", + "HCLK_CMT_MUX_CLK_MMCM4", + "HCLK_CMT_MUX_CLK_MMCM2", + "HCLK_CMT_MUX_MMCM_MUXED2", + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_CMT_MUX_MMCM_MUXED1", + "HCLK_CMT_BUFMR_CE1", + "HCLK_CMT_PHASERIND_ICLK", + "HCLK_CMT_MUX_MMCM_CLKFBIN", + "HCLK_CMT_IBURSTPENDING0", + "HCLK_CMT_PHASEREF_ABOVE1", + "HCLK_CMT_MUX_CLK_PLL5", + "HCLK_CMT_MUX_OUT_FREQ_REF3", + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_CMT_MUX_CLK_MMCM0", + "HCLK_CMT_PHASEROUTC_OCLK1X_90", + "HCLK_CMT_MUX_CLK_11", + "HCLK_CMT_MUX_CLKINT_1", + "HCLK_CMT_PHASEROUTC_OCLK", + "HCLK_CMT_MUX_CLK_6", + "HCLK_CMT_PHASEROUTD_OCLK", + "HCLK_CMT_CK_IN6", + "HCLK_CMT_MUX_CLK_PLL6", + "HCLK_CMT_PHASERIN_RCLK2", + "HCLK_CMT_CK_IN1", + "HCLK_CMT_PHASERINC_ICLKDIV", + "HCLK_CMT_MUX_CLK_4", + "HCLK_CMT_CK_IN9", + "HCLK_CMT_CK_IN5", + "HCLK_CMT_CK_IN0", + "HCLK_CMT_MUX_MMCM_CLKIN1", + "HCLK_CMT_MUX_CLK_0", + "HCLK_CMT_MUX_CLKINT_3", + "HCLK_CMT_ECALIB0", + "HCLK_CMT_PHASERINA_ICLK", + "HCLK_CMT_BUFMRCE_CEINP0", + "HCLK_CMT_CK_IN8", + "HCLK_CMT_PHASERINB_ICLKDIV", + "HCLK_CMT_MUX_CLK_PLL1", + "HCLK_CMT_MUX_CLK_2", + "HCLK_CMT_IBURST0", + "HCLK_CMT_PREF_BOUNCE3", + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_CMT_MUX_MMCM_MUXED3", + "HCLK_CMT_BUFMRCE_O1", + "HCLK_CMT_MUX_CLK_PLL4", + "HCLK_CMT_PHASEROUTD_OCLKDIV", + "HCLK_CMT_PREF_TMUXOUT", + "HCLK_CMT_PHASEREF_BELOW0", + "HCLK_CMT_PHY_SYNC_BB", + "HCLK_CMT_PREF_BOUNCE1", + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_CMT_MUX_CLK_PLL0", + "HCLK_CMT_PHASEROUTB_OCLK1X_90", + "HCLK_CMT_BUFMR_INP0", + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_CMT_BUFMR_CE0", + "HCLK_CMT_CCIO0", + "HCLK_CMT_PHASERIND_ICLKDIV", + "HCLK_CMT_FREQ_REF_NS0", + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_CMT_MUX_CLK_7", + "HCLK_CMT_PHASEREF_BELOW1", + "HCLK_CMT_MUX_CLK_MMCM5", + "HCLK_CMT_IBURSTPENDING1", + "HCLK_CMT_CK_IN12", + "HCLK_CMT_PHY_CONTROL_IRANKA0", + "HCLK_CMT_MUX_OUT_FREQ_REF0", + "HCLK_CMT_MUX_CLK_9", + "HCLK_CMT_PREF_BOUNCE0", + "HCLK_CMT_OBURSTPENDING0", + "HCLK_CMT_MUX_CLK_MMCM10", + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_CMT_CCIO3", + "HCLK_CMT_PHASERIN_RCLK1", + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_CMT_CK_IN7", + "HCLK_CMT_PHASEROUTA_OCLK1X_90", + "HCLK_CMT_PHY_CONTROL_IRANKB1", + "HCLK_CMT_MUX_CLK_MMCM8", + "HCLK_CMT_CK_IN13", + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_CMT_PHASEROUTB_OCLK", + "HCLK_CMT_MUX_OUT_FREQ_REF2", + "HCLK_CMT_MUX_CLK_MMCM13", + "HCLK_CMT_MUX_CLK_PLL3", + "HCLK_CMT_MUX_CLK_MMCM6", + "HCLK_CMT_BUFMRCE_CEINP1", + "HCLK_CMT_FREQ_PHASER_REFMUX_2", + "HCLK_CMT_MUX_CLK_LEAF_UP0", + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_CMT_FREQ_REF_NS1", + "HCLK_CMT_FREQ_PHASER_REFMUX_1", + "HCLK_CMT_ECALIB1", + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_CMT_MUX_CLK_8", + "HCLK_CMT_MUX_CLK_MMCM12", + "HCLK_CMT_OBURSTPENDING1", + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_CMT_FREQ_REF_NS3", + "HCLK_CMT_CCIO1", + "HCLK_CMT_MUX_CLK_13", + "HCLK_CMT_PHASERINC_ICLK", + "HCLK_CMT_CK_IN4", + "HCLK_CMT_PREF_CLKOUT", + "HCLK_CMT_PHY_CONTROL_IRANKA1", + "HCLK_CMT_PHASEROUTB_OCLKDIV", + "HCLK_CMT_MUX_CLK_MMCM9", + "HCLK_CMT_MUX_PLLE2_CLKIN2", + "HCLK_CMT_FREQ_PHASER_REFMUX_0", + "HCLK_CMT_MUX_CLK_LEAF_DN0", + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_CMT_MUX_CLK_PLL2", + "HCLK_CMT_PHASERINA_ICLKDIV", + "HCLK_CMT_MUX_OUT_FREQ_REF1", + "HCLK_CMT_CK_IN3", + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_CMT_FREQ_REF_NS2", + "HCLK_CMT_CK_IN10", + "HCLK_CMT_BUFMR_PHASEREF1", + "HCLK_CMT_PHY_CONTROL_IRANKB0", + "HCLK_CMT_IBURST1", + "HCLK_CMT_PHASERINB_ICLK", + "HCLK_CMT_CK_IN11", + "HCLK_CMT_PHASERIN_RCLK0", + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_CMT_PHASEROUTC_OCLKDIV", + "HCLK_CMT_MUX_CLKINT_0", + "HCLK_CMT_BUFMR_PHASEREF0", + "HCLK_CMT_BUFMRCE_O0", + "HCLK_CMT_MUX_CLK_3", + "HCLK_CMT_MUX_PLLE2_CLKIN1", + "HCLK_CMT_PHASEREF_ABOVE0", + "HCLK_CMT_MUX_CLK_MMCM7", + "HCLK_CMT_BUFMR_INP1", + "HCLK_CMT_MUX_CLK_PLL7", + "HCLK_CMT_MUX_CLK_LEAF_UP1", + "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "HCLK_CMT_MUX_CLK_LEAF_DN1", + "HCLK_CMT_MUX_CLK_MMCM1", + "HCLK_CMT_MUX_CLK_12" + ], + "tile_type": "HCLK_CMT", + "sites": [ + { + "site_pins": { + "I": "HCLK_CMT_BUFMR_INP1", + "CE": "HCLK_CMT_BUFMRCE_CEINP1", + "O": "HCLK_CMT_BUFMRCE_O1" + }, + "type": "BUFMRCE", + "prefix": "BUFMRCE", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "I": "HCLK_CMT_BUFMR_INP0", + "CE": "HCLK_CMT_BUFMRCE_CEINP0", + "O": "HCLK_CMT_BUFMRCE_O0" + }, + "type": "BUFMRCE", + "prefix": "BUFMRCE", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_CMT_L.json b/artix7/tile_type_HCLK_CMT_L.json index cdb6fd5..626a71c 100644 --- a/artix7/tile_type_HCLK_CMT_L.json +++ b/artix7/tile_type_HCLK_CMT_L.json @@ -1,7047 +1,7047 @@ { - "wires": [ - "HCLK_CMT_PHY_CONTROL_IRANKA1", - "HCLK_CMT_MUX_CLK_MMCM5", - "HCLK_CMT_PHASEREF_BELOW0", - "HCLK_CMT_MUX_CLK_MMCM2", - "HCLK_CMT_MUX_CLK_LEAF_UP1", - "HCLK_CMT_CK_IN10", - "HCLK_CMT_MUX_CLKINT_3", - "HCLK_CMT_BUFMRCE_CEINP0", - "HCLK_CMT_CK_IN9", - "HCLK_CMT_CK_IN2", - "HCLK_CMT_CK_IN8", - "HCLK_CMT_ECALIB1", - "HCLK_CMT_MUX_CLK_MMCM7", - "HCLK_CMT_CK_BUFRCLK3", - "HCLK_CMT_FREQ_REF_NS0", - "HCLK_CMT_MUX_CLK_MMCM13", - "HCLK_CMT_MUX_CLK_11", - "HCLK_CMT_MUX_MMCM_CLKIN2", - "HCLK_CMT_BUFMR_CE1", - "HCLK_CMT_MUX_CLK_8", - "HCLK_CMT_PHY_SYNC_BB", - "HCLK_CMT_PHASEREF_ABOVE1", - "HCLK_CMT_OBURSTPENDING0", - "HCLK_CMT_MUX_CLK_MMCM11", - "HCLK_CMT_MUX_CLK_PLL0", - "HCLK_CMT_BUFMR_PHASEREF0", - "HCLK_CMT_IBURSTPENDING0", - "HCLK_CMT_MUX_CLKINT_0", - "HCLK_CMT_BUFMR_CE0", - "HCLK_CMT_MUX_MMCM_CLKIN1", - "HCLK_CMT_CK_BUFHCLK2", - "HCLK_CMT_MUX_PHSR_PERFCLK3", - "HCLK_CMT_PHY_CONTROL_IRANKB0", - "HCLK_CMT_MUX_PHSR_PERFCLK0", - "HCLK_CMT_CCIO1", - "HCLK_CMT_PHY_CONTROL_IRANKB1", - "HCLK_CMT_MUX_CLK_LEAF_DN1", - "HCLK_CMT_CCIO0", - "HCLK_CMT_MUX_MMCM_MUXED3", - "HCLK_CMT_CK_IN0", - "HCLK_CMT_MUX_CLK_PLL6", - "HCLK_CMT_CK_IN6", - "HCLK_CMT_CK_IN3", - "HCLK_CMT_MUX_CLK_9", - "HCLK_CMT_MUX_MMCM_MUXED2", - "HCLK_CMT_BUFMRCE_O0", - "HCLK_CMT_MUX_OUT_FREQ_REF0", - "HCLK_CMT_FREQ_REF_NS3", - "HCLK_CMT_MUX_CLK_PLL2", - "HCLK_CMT_PHASEREF_BELOW1", - "HCLK_CMT_CK_BUFHCLK3", - "HCLK_CMT_PREF_BOUNCE3", - "HCLK_CMT_MUX_CLK_MMCM8", - "HCLK_CMT_MUX_PLLE2_CLKIN1", - "HCLK_CMT_MUX_MMCM_MUXED0", - "HCLK_CMT_PREF_CLKOUT", - "HCLK_CMT_MUX_CLK_MMCM6", - "HCLK_CMT_PREF_BOUNCE2", - "HCLK_CMT_MUX_CLK_4", - "HCLK_CMT_CK_BUFRCLK1", - "HCLK_CMT_CK_IN13", - "HCLK_CMT_MUX_CLK_13", - "HCLK_CMT_MUX_CLK_MMCM9", - "HCLK_CMT_MUX_CLK_3", - "HCLK_CMT_IBURST1", - "HCLK_CMT_OBURSTPENDING1", - "HCLK_CMT_FREQ_PHASER_REFMUX_1", - "HCLK_CMT_BUFMRCE_CEINP1", - "HCLK_CMT_MUX_MMCM_MUXED1", - "HCLK_CMT_MUX_OUT_FREQ_REF2", - "HCLK_CMT_MUX_CLK_MMCM3", - "HCLK_CMT_CCIO2", - "HCLK_CMT_MUX_PHSR_PERFCLK1", - "HCLK_CMT_FREQ_REF_NS1", - "HCLK_CMT_PHASERIN_RCLK3", - "HCLK_CMT_CK_BUFHCLK6", - "HCLK_CMT_MUX_CLK_5", - "HCLK_CMT_MUX_CLK_PLL5", - "HCLK_CMT_PREF_TMUXOUT", - "HCLK_CMT_MUX_CLK_10", - "HCLK_CMT_MUX_CLKINT_1", - "HCLK_CMT_MUX_CLK_2", - "HCLK_CMT_MUX_CLK_MMCM0", - "HCLK_CMT_FREQ_PHASER_REFMUX_2", - "HCLK_CMT_FREQ_PHASER_REFMUX_0", - "HCLK_CMT_CK_BUFHCLK0", - "HCLK_CMT_MUX_CLK_0", - "HCLK_CMT_CK_BUFHCLK11", - "HCLK_CMT_MUX_MMCM_CLKFBIN", - "HCLK_CMT_MUX_CLKINT_2", - "HCLK_CMT_IBURSTPENDING1", - "HCLK_CMT_PREF_BOUNCE1", - "HCLK_CMT_MUX_CLK_PLL4", - "HCLK_CMT_MUX_CLK_PLL1", - "HCLK_CMT_CCIO3", - "HCLK_CMT_MUX_CLK_PLL3", - "HCLK_CMT_MUX_CLK_7", - "HCLK_CMT_MUX_OUT_FREQ_REF1", - "HCLK_CMT_MUX_PHSR_PERFCLK2", - "HCLK_CMT_PHASEREF_ABOVE0", - "HCLK_CMT_CK_BUFRCLK0", - "HCLK_CMT_MUX_CLK_MMCM12", - "HCLK_CMT_CK_IN1", - "HCLK_CMT_CK_BUFHCLK10", - "HCLK_CMT_CK_BUFRCLK2", - "HCLK_CMT_MUX_CLK_1", - "HCLK_CMT_BUFMR_PHASEREF1", - "HCLK_CMT_CK_BUFHCLK1", - "HCLK_CMT_CK_IN12", - "HCLK_CMT_CK_BUFHCLK7", - "HCLK_CMT_PHASERIN_RCLK0", - "HCLK_CMT_PHASERIN_RCLK1", - "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "HCLK_CMT_MUX_CLK_6", - "HCLK_CMT_MUX_CLK_12", - "HCLK_CMT_CK_BUFHCLK4", - "HCLK_CMT_PREF_BOUNCE0", - "HCLK_CMT_CK_IN11", - "HCLK_CMT_CK_BUFHCLK8", - "HCLK_CMT_MUX_CLK_MMCM10", - "HCLK_CMT_PHY_CONTROL_IRANKA0", - "HCLK_CMT_MUX_PLLE2_CLKIN2", - "HCLK_CMT_MUX_CLK_MMCM1", - "HCLK_CMT_FREQ_REF_NS2", - "HCLK_CMT_IBURST0", - "HCLK_CMT_MUX_CLK_PLL7", - "HCLK_CMT_BUFMRCE_O1", - "HCLK_CMT_CK_IN5", - "HCLK_CMT_CK_BUFHCLK5", - "HCLK_CMT_MUX_CLK_MMCM4", - "HCLK_CMT_MUX_OUT_FREQ_REF3", - "HCLK_CMT_BUFMR_INP0", - "HCLK_CMT_BUFMR_INP1", - "HCLK_CMT_MUX_CLK_LEAF_UP0", - "HCLK_CMT_ECALIB0", - "HCLK_CMT_PHASERIN_RCLK2", - "HCLK_CMT_CK_IN7", - "HCLK_CMT_CK_BUFHCLK9", - "HCLK_CMT_CK_IN4", - "HCLK_CMT_MUX_CLK_LEAF_DN0" - ], - "sites": [ - { - "prefix": "BUFMRCE", - "y_coord": 1, - "type": "BUFMRCE", - "site_pins": { - "I": "HCLK_CMT_BUFMR_INP1", - "O": "HCLK_CMT_BUFMRCE_O1", - "CE": "HCLK_CMT_BUFMRCE_CEINP1" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "BUFMRCE", - "y_coord": 0, - "type": "BUFMRCE", - "site_pins": { - "I": "HCLK_CMT_BUFMR_INP0", - "O": "HCLK_CMT_BUFMRCE_O0", - "CE": "HCLK_CMT_BUFMRCE_CEINP0" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN9": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0", - "is_directional": "1", - "src_wire": "HCLK_CMT_BUFMRCE_O0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_BUFMR_CE1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN3": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN9": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_BUFMR_CE0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_FREQ_REF_NS2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_FREQ_REF_NS3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_FREQ_REF_NS0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLKINT_3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_BUFMR_INP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_FREQ_REF_NS1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1", - "is_directional": "1", - "src_wire": "HCLK_CMT_BUFMRCE_O1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", - "is_directional": "1", - "src_wire": "HCLK_CMT_PHASERIN_RCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN3": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN5": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN13": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_BUFMR_INP1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_BUFMR_INP1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN7": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO2", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN10": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN10", - "is_directional": "1", - "src_wire": "HCLK_CMT_CCIO1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN11": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP0": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", - "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN4": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN4", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_12", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", - "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN3": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN3", - "is_directional": "1", "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN12": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN5": { + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN5", + "src_wire": "HCLK_CMT_CCIO3", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN7": { + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", + "src_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN0": { + "can_invert": "0", "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN6": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN13": { + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN8": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN13", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN2": { + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", + "src_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN2": { + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN2", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN11": { + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN7": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN4": { + "can_invert": "0", "src_wire": "HCLK_CMT_MUX_CLK_8", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN1": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN12": { + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN12", + "src_wire": "HCLK_CMT_CCIO0", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_PLL5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN1": { + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN13": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN1", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", "src_wire": "HCLK_CMT_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN9": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", - "src_wire": "HCLK_CMT_MUX_CLK_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_BUFMR_CE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_BUFMRCE_O0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN8": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN7": { + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN12": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN7", + "src_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN2": { + "can_invert": "0", "src_wire": "HCLK_CMT_CK_BUFHCLK9", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN6": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN6", - "is_directional": "1", "src_wire": "HCLK_CMT_MUX_CLK_6", - "is_pseudo": "0" - }, - "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { - "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", - "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1" + }, + "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_BUFMRCE_O1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN11": { "can_invert": "0", - "dst_wire": "HCLK_CMT_CK_IN11", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFHCLK3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_FREQ_REF_NS0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", - "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", - "is_directional": "1", "src_wire": "HCLK_CMT_CK_BUFRCLK3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN10": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN10" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN7": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN7" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_BUFMR_CE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLKINT_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN12": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN12" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_PHASERIN_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_PLL5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN11": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN11" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN3": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN3" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_BUFMR_INP0": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_BUFMR_INP0" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN1": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN1" + }, + "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN13": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CCIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN13" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN9": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN9" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN8": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN8" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN4": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN4" + }, + "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN5": { + "can_invert": "0", + "src_wire": "HCLK_CMT_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN5" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN2": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_MMCM2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN2" + }, + "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN6": { + "can_invert": "0", + "src_wire": "HCLK_CMT_MUX_CLK_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CMT_CK_IN6" } }, - "tile_type": "HCLK_CMT_L" + "wires": [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_CMT_MUX_CLK_MMCM11", + "HCLK_CMT_MUX_CLK_5", + "HCLK_CMT_MUX_CLK_10", + "HCLK_CMT_MUX_MMCM_MUXED0", + "HCLK_CMT_CK_IN2", + "HCLK_CMT_MUX_MMCM_CLKIN2", + "HCLK_CMT_PHASERIN_RCLK3", + "HCLK_CMT_MUX_CLKINT_2", + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_CMT_MUX_CLK_1", + "HCLK_CMT_CCIO2", + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_CMT_PREF_BOUNCE2", + "HCLK_CMT_MUX_CLK_MMCM3", + "HCLK_CMT_MUX_CLK_MMCM4", + "HCLK_CMT_MUX_CLK_MMCM2", + "HCLK_CMT_MUX_MMCM_MUXED2", + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_CMT_MUX_MMCM_MUXED1", + "HCLK_CMT_BUFMR_CE1", + "HCLK_CMT_MUX_MMCM_CLKFBIN", + "HCLK_CMT_IBURSTPENDING0", + "HCLK_CMT_PHASEREF_ABOVE1", + "HCLK_CMT_MUX_CLK_PLL5", + "HCLK_CMT_MUX_OUT_FREQ_REF3", + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_CMT_MUX_CLK_MMCM0", + "HCLK_CMT_MUX_CLK_11", + "HCLK_CMT_MUX_CLKINT_1", + "HCLK_CMT_MUX_CLK_6", + "HCLK_CMT_CK_IN1", + "HCLK_CMT_CK_IN6", + "HCLK_CMT_MUX_CLK_PLL6", + "HCLK_CMT_PHASERIN_RCLK2", + "HCLK_CMT_MUX_CLK_4", + "HCLK_CMT_CK_IN9", + "HCLK_CMT_CK_IN5", + "HCLK_CMT_CK_IN0", + "HCLK_CMT_MUX_MMCM_CLKIN1", + "HCLK_CMT_MUX_CLK_0", + "HCLK_CMT_MUX_CLKINT_3", + "HCLK_CMT_ECALIB0", + "HCLK_CMT_CK_IN8", + "HCLK_CMT_BUFMRCE_CEINP0", + "HCLK_CMT_MUX_CLK_PLL1", + "HCLK_CMT_MUX_CLK_2", + "HCLK_CMT_IBURST0", + "HCLK_CMT_PREF_BOUNCE3", + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_CMT_MUX_MMCM_MUXED3", + "HCLK_CMT_BUFMRCE_O1", + "HCLK_CMT_MUX_CLK_PLL4", + "HCLK_CMT_PREF_TMUXOUT", + "HCLK_CMT_PHASEREF_BELOW0", + "HCLK_CMT_PHY_SYNC_BB", + "HCLK_CMT_PREF_BOUNCE1", + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_CMT_MUX_CLK_PLL0", + "HCLK_CMT_BUFMR_INP0", + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_CMT_BUFMR_CE0", + "HCLK_CMT_CCIO0", + "HCLK_CMT_FREQ_REF_NS0", + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_CMT_MUX_CLK_7", + "HCLK_CMT_PHASEREF_BELOW1", + "HCLK_CMT_MUX_CLK_MMCM5", + "HCLK_CMT_IBURSTPENDING1", + "HCLK_CMT_CK_IN12", + "HCLK_CMT_PHY_CONTROL_IRANKA0", + "HCLK_CMT_MUX_OUT_FREQ_REF0", + "HCLK_CMT_MUX_CLK_9", + "HCLK_CMT_PREF_BOUNCE0", + "HCLK_CMT_OBURSTPENDING0", + "HCLK_CMT_MUX_CLK_MMCM10", + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_CMT_CCIO3", + "HCLK_CMT_PHASERIN_RCLK1", + "HCLK_CMT_CK_IN7", + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_CMT_PHY_CONTROL_IRANKB1", + "HCLK_CMT_MUX_CLK_MMCM8", + "HCLK_CMT_CK_IN13", + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_CMT_MUX_OUT_FREQ_REF2", + "HCLK_CMT_MUX_CLK_PLL3", + "HCLK_CMT_MUX_CLK_MMCM13", + "HCLK_CMT_MUX_CLK_MMCM6", + "HCLK_CMT_BUFMRCE_CEINP1", + "HCLK_CMT_FREQ_PHASER_REFMUX_2", + "HCLK_CMT_MUX_CLK_LEAF_UP0", + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_CMT_FREQ_REF_NS1", + "HCLK_CMT_FREQ_PHASER_REFMUX_1", + "HCLK_CMT_ECALIB1", + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_CMT_MUX_CLK_8", + "HCLK_CMT_MUX_CLK_MMCM12", + "HCLK_CMT_OBURSTPENDING1", + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_CMT_FREQ_REF_NS3", + "HCLK_CMT_CCIO1", + "HCLK_CMT_MUX_CLK_13", + "HCLK_CMT_CK_IN4", + "HCLK_CMT_PREF_CLKOUT", + "HCLK_CMT_PHY_CONTROL_IRANKA1", + "HCLK_CMT_MUX_CLK_MMCM9", + "HCLK_CMT_MUX_PLLE2_CLKIN2", + "HCLK_CMT_FREQ_PHASER_REFMUX_0", + "HCLK_CMT_MUX_CLK_LEAF_DN0", + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_CMT_MUX_CLK_PLL2", + "HCLK_CMT_MUX_OUT_FREQ_REF1", + "HCLK_CMT_CK_IN3", + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_CMT_FREQ_REF_NS2", + "HCLK_CMT_CK_IN10", + "HCLK_CMT_BUFMR_PHASEREF1", + "HCLK_CMT_PHY_CONTROL_IRANKB0", + "HCLK_CMT_IBURST1", + "HCLK_CMT_CK_IN11", + "HCLK_CMT_PHASERIN_RCLK0", + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_CMT_MUX_CLKINT_0", + "HCLK_CMT_BUFMR_PHASEREF0", + "HCLK_CMT_BUFMRCE_O0", + "HCLK_CMT_MUX_PLLE2_CLKIN1", + "HCLK_CMT_MUX_CLK_3", + "HCLK_CMT_PHASEREF_ABOVE0", + "HCLK_CMT_MUX_CLK_MMCM7", + "HCLK_CMT_BUFMR_INP1", + "HCLK_CMT_MUX_CLK_PLL7", + "HCLK_CMT_MUX_CLK_LEAF_UP1", + "HCLK_CMT_MUX_PLLE2_CLKFBIN", + "HCLK_CMT_MUX_CLK_LEAF_DN1", + "HCLK_CMT_MUX_CLK_MMCM1", + "HCLK_CMT_MUX_CLK_12" + ], + "tile_type": "HCLK_CMT_L", + "sites": [ + { + "site_pins": { + "I": "HCLK_CMT_BUFMR_INP1", + "CE": "HCLK_CMT_BUFMRCE_CEINP1", + "O": "HCLK_CMT_BUFMRCE_O1" + }, + "type": "BUFMRCE", + "prefix": "BUFMRCE", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "I": "HCLK_CMT_BUFMR_INP0", + "CE": "HCLK_CMT_BUFMRCE_CEINP0", + "O": "HCLK_CMT_BUFMRCE_O0" + }, + "type": "BUFMRCE", + "prefix": "BUFMRCE", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_DSP_L.json b/artix7/tile_type_HCLK_DSP_L.json index 862ea3a..0e814ad 100644 --- a/artix7/tile_type_HCLK_DSP_L.json +++ b/artix7/tile_type_HCLK_DSP_L.json @@ -1,135 +1,135 @@ { - "wires": [ - "HCLK_DSP_PCIN27", - "HCLK_DSP_BCIN6", - "HCLK_DSP_PCIN46", - "HCLK_DSP_PCIN34", - "HCLK_DSP_ACIN1", - "HCLK_DSP_CK_IN8", - "HCLK_DSP_ACIN8", - "HCLK_DSP_BCIN13", - "HCLK_DSP_ACIN27", - "HCLK_DSP_CK_IN9", - "HCLK_DSP_PCIN31", - "HCLK_DSP_MULTSIGNIN", - "HCLK_DSP_BCIN11", - "HCLK_DSP_PCIN14", - "HCLK_DSP_ACIN0", - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_DSP_PCIN33", - "HCLK_DSP_BCIN1", - "HCLK_DSP_PCIN9", - "HCLK_DSP_PCIN29", - "HCLK_DSP_PCIN30", - "HCLK_DSP_BCIN16", - "HCLK_DSP_ACIN29", - "HCLK_DSP_PCIN22", - "HCLK_DSP_ACIN19", - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_DSP_ACIN13", - "HCLK_DSP_BCIN15", - "HCLK_DSP_CK_IN1", - "HCLK_DSP_PCIN17", - "HCLK_DSP_PCIN45", - "HCLK_DSP_BCIN12", - "HCLK_DSP_BCIN10", - "HCLK_DSP_ACIN6", - "HCLK_DSP_PCIN23", - "HCLK_DSP_PCIN44", - "HCLK_DSP_ACIN28", - "HCLK_DSP_PCIN28", - "HCLK_DSP_CK_IN13", - "HCLK_DSP_CK_IN7", - "HCLK_DSP_ACIN18", - "HCLK_DSP_ACIN2", - "HCLK_DSP_PCIN47", - "HCLK_DSP_BCIN5", - "HCLK_DSP_CK_IN12", - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_DSP_PCIN13", - "HCLK_DSP_PCIN25", - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_DSP_PCIN8", - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_DSP_ACIN24", - "HCLK_DSP_ACIN10", - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_DSP_ACIN25", - "HCLK_DSP_PCIN16", - "HCLK_DSP_ACIN15", - "HCLK_DSP_CK_IN2", - "HCLK_DSP_ACIN14", - "HCLK_DSP_ACIN16", - "HCLK_DSP_PCIN32", - "HCLK_DSP_BCIN3", - "HCLK_DSP_BCIN0", - "HCLK_DSP_CK_IN6", - "HCLK_DSP_CK_IN3", - "HCLK_DSP_PCIN5", - "HCLK_DSP_BCIN4", - "HCLK_DSP_PCIN15", - "HCLK_DSP_PCIN1", - "HCLK_DSP_PCIN18", - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_DSP_PCIN43", - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_DSP_CK_IN11", - "HCLK_DSP_BCIN2", - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_DSP_PCIN12", - "HCLK_DSP_BCIN7", - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_DSP_PCIN19", - "HCLK_DSP_CK_IN4", - "HCLK_DSP_PCIN39", - "HCLK_DSP_ACIN20", - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_DSP_CK_IN10", - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_DSP_PCIN37", - "HCLK_DSP_PCIN7", - "HCLK_DSP_ACIN5", - "HCLK_DSP_BCIN14", - "HCLK_DSP_PCIN41", - "HCLK_DSP_ACIN26", - "HCLK_DSP_PCIN35", - "HCLK_DSP_PCIN40", - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_DSP_CK_IN0", - "HCLK_DSP_PCIN20", - "HCLK_DSP_ACIN12", - "HCLK_DSP_BCIN8", - "HCLK_DSP_BCIN9", - "HCLK_DSP_CARRYCASCIN", - "HCLK_DSP_PCIN4", - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_DSP_ACIN22", - "HCLK_DSP_PCIN36", - "HCLK_DSP_PCIN42", - "HCLK_DSP_PCIN0", - "HCLK_DSP_ACIN11", - "HCLK_DSP_CK_IN5", - "HCLK_DSP_PCIN3", - "HCLK_DSP_PCIN26", - "HCLK_DSP_PCIN11", - "HCLK_DSP_PCIN21", - "HCLK_DSP_ACIN17", - "HCLK_DSP_PCIN38", - "HCLK_DSP_PCIN10", - "HCLK_DSP_PCIN2", - "HCLK_DSP_PCIN6", - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_DSP_ACIN9", - "HCLK_DSP_BCIN17", - "HCLK_DSP_ACIN23", - "HCLK_DSP_ACIN21", - "HCLK_DSP_ACIN7", - "HCLK_DSP_ACIN3", - "HCLK_DSP_ACIN4", - "HCLK_DSP_PCIN24" - ], - "sites": [], "pips": {}, - "tile_type": "HCLK_DSP_L" + "wires": [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_DSP_BCIN9", + "HCLK_DSP_PCIN45", + "HCLK_DSP_PCIN19", + "HCLK_DSP_PCIN27", + "HCLK_DSP_BCIN5", + "HCLK_DSP_BCIN7", + "HCLK_DSP_PCIN11", + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_DSP_CK_IN1", + "HCLK_DSP_PCIN41", + "HCLK_DSP_PCIN40", + "HCLK_DSP_ACIN1", + "HCLK_DSP_CK_IN10", + "HCLK_DSP_PCIN46", + "HCLK_DSP_ACIN12", + "HCLK_DSP_PCIN17", + "HCLK_DSP_ACIN29", + "HCLK_DSP_BCIN17", + "HCLK_DSP_PCIN2", + "HCLK_DSP_BCIN8", + "HCLK_DSP_CK_IN12", + "HCLK_DSP_BCIN6", + "HCLK_DSP_BCIN14", + "HCLK_DSP_PCIN32", + "HCLK_DSP_PCIN23", + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_DSP_BCIN2", + "HCLK_DSP_CK_IN0", + "HCLK_DSP_ACIN28", + "HCLK_DSP_BCIN16", + "HCLK_DSP_PCIN34", + "HCLK_DSP_PCIN5", + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_DSP_ACIN15", + "HCLK_DSP_ACIN13", + "HCLK_DSP_PCIN20", + "HCLK_DSP_ACIN24", + "HCLK_DSP_PCIN4", + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_DSP_BCIN3", + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_DSP_CK_IN3", + "HCLK_DSP_ACIN25", + "HCLK_DSP_ACIN21", + "HCLK_DSP_PCIN13", + "HCLK_DSP_BCIN4", + "HCLK_DSP_MULTSIGNIN", + "HCLK_DSP_PCIN24", + "HCLK_DSP_CK_IN8", + "HCLK_DSP_CK_IN7", + "HCLK_DSP_CK_IN9", + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_DSP_PCIN28", + "HCLK_DSP_PCIN31", + "HCLK_DSP_BCIN13", + "HCLK_DSP_ACIN18", + "HCLK_DSP_PCIN10", + "HCLK_DSP_PCIN42", + "HCLK_DSP_PCIN37", + "HCLK_DSP_PCIN35", + "HCLK_DSP_PCIN21", + "HCLK_DSP_PCIN1", + "HCLK_DSP_ACIN3", + "HCLK_DSP_PCIN26", + "HCLK_DSP_PCIN29", + "HCLK_DSP_PCIN3", + "HCLK_DSP_ACIN19", + "HCLK_DSP_BCIN1", + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_DSP_ACIN0", + "HCLK_DSP_CK_IN2", + "HCLK_DSP_PCIN39", + "HCLK_DSP_PCIN25", + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_DSP_PCIN6", + "HCLK_DSP_BCIN15", + "HCLK_DSP_ACIN9", + "HCLK_DSP_CK_IN6", + "HCLK_DSP_ACIN17", + "HCLK_DSP_PCIN18", + "HCLK_DSP_ACIN27", + "HCLK_DSP_ACIN23", + "HCLK_DSP_PCIN44", + "HCLK_DSP_PCIN15", + "HCLK_DSP_ACIN4", + "HCLK_DSP_PCIN16", + "HCLK_DSP_ACIN10", + "HCLK_DSP_ACIN26", + "HCLK_DSP_ACIN22", + "HCLK_DSP_PCIN8", + "HCLK_DSP_PCIN38", + "HCLK_DSP_ACIN20", + "HCLK_DSP_PCIN33", + "HCLK_DSP_CK_IN5", + "HCLK_DSP_BCIN11", + "HCLK_DSP_PCIN0", + "HCLK_DSP_PCIN30", + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_DSP_PCIN7", + "HCLK_DSP_BCIN12", + "HCLK_DSP_ACIN11", + "HCLK_DSP_ACIN14", + "HCLK_DSP_CK_IN4", + "HCLK_DSP_ACIN5", + "HCLK_DSP_CARRYCASCIN", + "HCLK_DSP_PCIN9", + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_DSP_PCIN22", + "HCLK_DSP_PCIN12", + "HCLK_DSP_PCIN47", + "HCLK_DSP_BCIN10", + "HCLK_DSP_PCIN36", + "HCLK_DSP_ACIN2", + "HCLK_DSP_PCIN14", + "HCLK_DSP_PCIN43", + "HCLK_DSP_ACIN16", + "HCLK_DSP_BCIN0", + "HCLK_DSP_CK_IN13", + "HCLK_DSP_ACIN6", + "HCLK_DSP_CK_IN11", + "HCLK_DSP_ACIN7", + "HCLK_DSP_ACIN8" + ], + "tile_type": "HCLK_DSP_L", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_DSP_R.json b/artix7/tile_type_HCLK_DSP_R.json index 22fbce8..cdff171 100644 --- a/artix7/tile_type_HCLK_DSP_R.json +++ b/artix7/tile_type_HCLK_DSP_R.json @@ -1,135 +1,135 @@ { - "wires": [ - "HCLK_DSP_PCIN27", - "HCLK_DSP_BCIN6", - "HCLK_DSP_PCIN46", - "HCLK_DSP_PCIN34", - "HCLK_DSP_ACIN1", - "HCLK_DSP_CK_IN8", - "HCLK_DSP_ACIN8", - "HCLK_DSP_BCIN13", - "HCLK_DSP_ACIN27", - "HCLK_DSP_CK_IN9", - "HCLK_DSP_PCIN31", - "HCLK_DSP_MULTSIGNIN", - "HCLK_DSP_BCIN11", - "HCLK_DSP_PCIN14", - "HCLK_DSP_ACIN0", - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_DSP_PCIN33", - "HCLK_DSP_BCIN1", - "HCLK_DSP_PCIN9", - "HCLK_DSP_PCIN29", - "HCLK_DSP_PCIN30", - "HCLK_DSP_BCIN16", - "HCLK_DSP_ACIN29", - "HCLK_DSP_PCIN22", - "HCLK_DSP_ACIN19", - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_DSP_ACIN13", - "HCLK_DSP_BCIN15", - "HCLK_DSP_CK_IN1", - "HCLK_DSP_PCIN17", - "HCLK_DSP_PCIN45", - "HCLK_DSP_BCIN12", - "HCLK_DSP_BCIN10", - "HCLK_DSP_ACIN6", - "HCLK_DSP_PCIN23", - "HCLK_DSP_PCIN44", - "HCLK_DSP_ACIN28", - "HCLK_DSP_PCIN28", - "HCLK_DSP_CK_IN13", - "HCLK_DSP_CK_IN7", - "HCLK_DSP_ACIN18", - "HCLK_DSP_ACIN2", - "HCLK_DSP_PCIN47", - "HCLK_DSP_BCIN5", - "HCLK_DSP_CK_IN12", - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_DSP_PCIN13", - "HCLK_DSP_PCIN25", - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_DSP_PCIN8", - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_DSP_ACIN24", - "HCLK_DSP_ACIN10", - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_DSP_ACIN25", - "HCLK_DSP_PCIN16", - "HCLK_DSP_ACIN15", - "HCLK_DSP_CK_IN2", - "HCLK_DSP_ACIN14", - "HCLK_DSP_ACIN16", - "HCLK_DSP_PCIN32", - "HCLK_DSP_BCIN3", - "HCLK_DSP_BCIN0", - "HCLK_DSP_CK_IN6", - "HCLK_DSP_CK_IN3", - "HCLK_DSP_PCIN5", - "HCLK_DSP_BCIN4", - "HCLK_DSP_PCIN15", - "HCLK_DSP_PCIN1", - "HCLK_DSP_PCIN18", - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_DSP_PCIN43", - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_DSP_CK_IN11", - "HCLK_DSP_BCIN2", - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_DSP_PCIN12", - "HCLK_DSP_BCIN7", - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_DSP_PCIN19", - "HCLK_DSP_CK_IN4", - "HCLK_DSP_PCIN39", - "HCLK_DSP_ACIN20", - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_DSP_CK_IN10", - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_DSP_PCIN37", - "HCLK_DSP_PCIN7", - "HCLK_DSP_ACIN5", - "HCLK_DSP_BCIN14", - "HCLK_DSP_PCIN41", - "HCLK_DSP_ACIN26", - "HCLK_DSP_PCIN35", - "HCLK_DSP_PCIN40", - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_DSP_CK_IN0", - "HCLK_DSP_PCIN20", - "HCLK_DSP_ACIN12", - "HCLK_DSP_BCIN8", - "HCLK_DSP_BCIN9", - "HCLK_DSP_CARRYCASCIN", - "HCLK_DSP_PCIN4", - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_DSP_ACIN22", - "HCLK_DSP_PCIN36", - "HCLK_DSP_PCIN42", - "HCLK_DSP_PCIN0", - "HCLK_DSP_ACIN11", - "HCLK_DSP_CK_IN5", - "HCLK_DSP_PCIN3", - "HCLK_DSP_PCIN26", - "HCLK_DSP_PCIN11", - "HCLK_DSP_PCIN21", - "HCLK_DSP_ACIN17", - "HCLK_DSP_PCIN38", - "HCLK_DSP_PCIN10", - "HCLK_DSP_PCIN2", - "HCLK_DSP_PCIN6", - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_DSP_ACIN9", - "HCLK_DSP_BCIN17", - "HCLK_DSP_ACIN23", - "HCLK_DSP_ACIN21", - "HCLK_DSP_ACIN7", - "HCLK_DSP_ACIN3", - "HCLK_DSP_ACIN4", - "HCLK_DSP_PCIN24" - ], - "sites": [], "pips": {}, - "tile_type": "HCLK_DSP_R" + "wires": [ + "HCLK_DSP_CK_BUFRCLK3", + "HCLK_DSP_CK_BUFHCLK9", + "HCLK_DSP_BCIN9", + "HCLK_DSP_PCIN45", + "HCLK_DSP_PCIN19", + "HCLK_DSP_PCIN27", + "HCLK_DSP_BCIN5", + "HCLK_DSP_BCIN7", + "HCLK_DSP_PCIN11", + "HCLK_DSP_CK_BUFRCLK2", + "HCLK_DSP_CK_BUFHCLK5", + "HCLK_DSP_CK_IN1", + "HCLK_DSP_PCIN41", + "HCLK_DSP_PCIN40", + "HCLK_DSP_ACIN1", + "HCLK_DSP_CK_IN10", + "HCLK_DSP_PCIN46", + "HCLK_DSP_ACIN12", + "HCLK_DSP_PCIN17", + "HCLK_DSP_ACIN29", + "HCLK_DSP_BCIN17", + "HCLK_DSP_PCIN2", + "HCLK_DSP_BCIN8", + "HCLK_DSP_CK_IN12", + "HCLK_DSP_BCIN6", + "HCLK_DSP_BCIN14", + "HCLK_DSP_PCIN32", + "HCLK_DSP_PCIN23", + "HCLK_DSP_CK_BUFHCLK10", + "HCLK_DSP_CK_BUFHCLK8", + "HCLK_DSP_BCIN2", + "HCLK_DSP_CK_IN0", + "HCLK_DSP_ACIN28", + "HCLK_DSP_BCIN16", + "HCLK_DSP_PCIN34", + "HCLK_DSP_PCIN5", + "HCLK_DSP_CK_BUFHCLK3", + "HCLK_DSP_ACIN15", + "HCLK_DSP_ACIN13", + "HCLK_DSP_PCIN20", + "HCLK_DSP_ACIN24", + "HCLK_DSP_PCIN4", + "HCLK_DSP_CK_BUFHCLK0", + "HCLK_DSP_BCIN3", + "HCLK_DSP_CK_BUFHCLK11", + "HCLK_DSP_CK_IN3", + "HCLK_DSP_ACIN25", + "HCLK_DSP_ACIN21", + "HCLK_DSP_PCIN13", + "HCLK_DSP_BCIN4", + "HCLK_DSP_MULTSIGNIN", + "HCLK_DSP_PCIN24", + "HCLK_DSP_CK_IN8", + "HCLK_DSP_CK_IN7", + "HCLK_DSP_CK_IN9", + "HCLK_DSP_CK_BUFHCLK4", + "HCLK_DSP_PCIN28", + "HCLK_DSP_PCIN31", + "HCLK_DSP_BCIN13", + "HCLK_DSP_ACIN18", + "HCLK_DSP_PCIN10", + "HCLK_DSP_PCIN42", + "HCLK_DSP_PCIN37", + "HCLK_DSP_PCIN35", + "HCLK_DSP_PCIN21", + "HCLK_DSP_PCIN1", + "HCLK_DSP_ACIN3", + "HCLK_DSP_PCIN26", + "HCLK_DSP_PCIN29", + "HCLK_DSP_PCIN3", + "HCLK_DSP_ACIN19", + "HCLK_DSP_BCIN1", + "HCLK_DSP_CK_BUFRCLK0", + "HCLK_DSP_CK_BUFRCLK1", + "HCLK_DSP_CK_BUFHCLK1", + "HCLK_DSP_ACIN0", + "HCLK_DSP_CK_IN2", + "HCLK_DSP_PCIN39", + "HCLK_DSP_PCIN25", + "HCLK_DSP_CK_BUFHCLK2", + "HCLK_DSP_PCIN6", + "HCLK_DSP_BCIN15", + "HCLK_DSP_ACIN9", + "HCLK_DSP_CK_IN6", + "HCLK_DSP_ACIN17", + "HCLK_DSP_PCIN18", + "HCLK_DSP_ACIN27", + "HCLK_DSP_ACIN23", + "HCLK_DSP_PCIN44", + "HCLK_DSP_PCIN15", + "HCLK_DSP_ACIN4", + "HCLK_DSP_PCIN16", + "HCLK_DSP_ACIN10", + "HCLK_DSP_ACIN26", + "HCLK_DSP_ACIN22", + "HCLK_DSP_PCIN8", + "HCLK_DSP_PCIN38", + "HCLK_DSP_ACIN20", + "HCLK_DSP_PCIN33", + "HCLK_DSP_CK_IN5", + "HCLK_DSP_BCIN11", + "HCLK_DSP_PCIN0", + "HCLK_DSP_PCIN30", + "HCLK_DSP_CK_BUFHCLK6", + "HCLK_DSP_PCIN7", + "HCLK_DSP_BCIN12", + "HCLK_DSP_ACIN11", + "HCLK_DSP_ACIN14", + "HCLK_DSP_CK_IN4", + "HCLK_DSP_ACIN5", + "HCLK_DSP_CARRYCASCIN", + "HCLK_DSP_PCIN9", + "HCLK_DSP_CK_BUFHCLK7", + "HCLK_DSP_PCIN22", + "HCLK_DSP_PCIN12", + "HCLK_DSP_PCIN47", + "HCLK_DSP_BCIN10", + "HCLK_DSP_PCIN36", + "HCLK_DSP_ACIN2", + "HCLK_DSP_PCIN14", + "HCLK_DSP_PCIN43", + "HCLK_DSP_ACIN16", + "HCLK_DSP_BCIN0", + "HCLK_DSP_CK_IN13", + "HCLK_DSP_ACIN6", + "HCLK_DSP_CK_IN11", + "HCLK_DSP_ACIN7", + "HCLK_DSP_ACIN8" + ], + "tile_type": "HCLK_DSP_R", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_FEEDTHRU_1.json b/artix7/tile_type_HCLK_FEEDTHRU_1.json index 978bcf6..31e35b3 100644 --- a/artix7/tile_type_HCLK_FEEDTHRU_1.json +++ b/artix7/tile_type_HCLK_FEEDTHRU_1.json @@ -1,37 +1,37 @@ { - "wires": [ - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_FEEDTHRU_1_CK_IN9", - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_FEEDTHRU_1_CK_BUFHCLK11" - ], - "sites": [], "pips": {}, - "tile_type": "HCLK_FEEDTHRU_1" + "wires": [ + "HCLK_FEEDTHRU_1_CK_BUFRCLK0", + "HCLK_FEEDTHRU_1_CK_IN7", + "HCLK_FEEDTHRU_1_CK_BUFHCLK3", + "HCLK_FEEDTHRU_1_CK_IN5", + "HCLK_FEEDTHRU_1_CK_IN4", + "HCLK_FEEDTHRU_1_CK_IN10", + "HCLK_FEEDTHRU_1_CK_BUFRCLK1", + "HCLK_FEEDTHRU_1_CK_BUFHCLK5", + "HCLK_FEEDTHRU_1_CK_BUFHCLK8", + "HCLK_FEEDTHRU_1_CK_IN8", + "HCLK_FEEDTHRU_1_CK_BUFRCLK3", + "HCLK_FEEDTHRU_1_CK_BUFHCLK2", + "HCLK_FEEDTHRU_1_CK_IN11", + "HCLK_FEEDTHRU_1_CK_IN2", + "HCLK_FEEDTHRU_1_CK_IN0", + "HCLK_FEEDTHRU_1_CK_IN9", + "HCLK_FEEDTHRU_1_CK_BUFHCLK1", + "HCLK_FEEDTHRU_1_CK_BUFHCLK0", + "HCLK_FEEDTHRU_1_CK_BUFHCLK11", + "HCLK_FEEDTHRU_1_CK_BUFRCLK2", + "HCLK_FEEDTHRU_1_CK_BUFHCLK6", + "HCLK_FEEDTHRU_1_CK_BUFHCLK4", + "HCLK_FEEDTHRU_1_CK_IN12", + "HCLK_FEEDTHRU_1_CK_BUFHCLK9", + "HCLK_FEEDTHRU_1_CK_IN3", + "HCLK_FEEDTHRU_1_CK_BUFHCLK7", + "HCLK_FEEDTHRU_1_CK_BUFHCLK10", + "HCLK_FEEDTHRU_1_CK_IN6", + "HCLK_FEEDTHRU_1_CK_IN1", + "HCLK_FEEDTHRU_1_CK_IN13" + ], + "tile_type": "HCLK_FEEDTHRU_1", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_FEEDTHRU_2.json b/artix7/tile_type_HCLK_FEEDTHRU_2.json index 5a0abc2..608bc7d 100644 --- a/artix7/tile_type_HCLK_FEEDTHRU_2.json +++ b/artix7/tile_type_HCLK_FEEDTHRU_2.json @@ -1,37 +1,37 @@ { + "pips": {}, "wires": [ - "HCLK_FEEDTHRU_2_CK_BUFRCLK3", + "HCLK_FEEDTHRU_2_CK_IN1", + "HCLK_FEEDTHRU_2_CK_BUFHCLK1", + "HCLK_FEEDTHRU_2_CK_BUFHCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK4", "HCLK_FEEDTHRU_2_CK_IN9", - "HCLK_FEEDTHRU_2_CK_BUFHCLK6", - "HCLK_FEEDTHRU_2_CK_IN7", "HCLK_FEEDTHRU_2_CK_IN6", + "HCLK_FEEDTHRU_2_CK_IN7", + "HCLK_FEEDTHRU_2_CK_IN2", + "HCLK_FEEDTHRU_2_CK_BUFHCLK7", + "HCLK_FEEDTHRU_2_CK_BUFHCLK2", + "HCLK_FEEDTHRU_2_CK_IN13", "HCLK_FEEDTHRU_2_CK_BUFHCLK10", "HCLK_FEEDTHRU_2_CK_IN5", - "HCLK_FEEDTHRU_2_CK_BUFRCLK0", - "HCLK_FEEDTHRU_2_CK_BUFRCLK1", - "HCLK_FEEDTHRU_2_CK_IN13", - "HCLK_FEEDTHRU_2_CK_BUFHCLK2", - "HCLK_FEEDTHRU_2_CK_BUFHCLK0", - "HCLK_FEEDTHRU_2_CK_IN11", - "HCLK_FEEDTHRU_2_CK_BUFHCLK9", - "HCLK_FEEDTHRU_2_CK_BUFHCLK4", - "HCLK_FEEDTHRU_2_CK_IN4", - "HCLK_FEEDTHRU_2_CK_IN12", - "HCLK_FEEDTHRU_2_CK_IN10", - "HCLK_FEEDTHRU_2_CK_BUFHCLK7", - "HCLK_FEEDTHRU_2_CK_BUFHCLK3", - "HCLK_FEEDTHRU_2_CK_IN0", - "HCLK_FEEDTHRU_2_CK_IN3", - "HCLK_FEEDTHRU_2_CK_BUFHCLK11", - "HCLK_FEEDTHRU_2_CK_IN1", - "HCLK_FEEDTHRU_2_CK_IN8", - "HCLK_FEEDTHRU_2_CK_BUFHCLK1", - "HCLK_FEEDTHRU_2_CK_IN2", - "HCLK_FEEDTHRU_2_CK_BUFHCLK5", "HCLK_FEEDTHRU_2_CK_BUFHCLK8", - "HCLK_FEEDTHRU_2_CK_BUFRCLK2" + "HCLK_FEEDTHRU_2_CK_BUFHCLK6", + "HCLK_FEEDTHRU_2_CK_IN4", + "HCLK_FEEDTHRU_2_CK_BUFHCLK9", + "HCLK_FEEDTHRU_2_CK_BUFHCLK3", + "HCLK_FEEDTHRU_2_CK_IN11", + "HCLK_FEEDTHRU_2_CK_IN3", + "HCLK_FEEDTHRU_2_CK_BUFRCLK1", + "HCLK_FEEDTHRU_2_CK_BUFRCLK0", + "HCLK_FEEDTHRU_2_CK_BUFHCLK11", + "HCLK_FEEDTHRU_2_CK_BUFRCLK2", + "HCLK_FEEDTHRU_2_CK_IN12", + "HCLK_FEEDTHRU_2_CK_IN0", + "HCLK_FEEDTHRU_2_CK_BUFRCLK3", + "HCLK_FEEDTHRU_2_CK_IN10", + "HCLK_FEEDTHRU_2_CK_BUFHCLK5", + "HCLK_FEEDTHRU_2_CK_IN8" ], - "sites": [], - "pips": {}, - "tile_type": "HCLK_FEEDTHRU_2" + "tile_type": "HCLK_FEEDTHRU_2", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_FIFO_L.json b/artix7/tile_type_HCLK_FIFO_L.json index d4084b3..c726a06 100644 --- a/artix7/tile_type_HCLK_FIFO_L.json +++ b/artix7/tile_type_HCLK_FIFO_L.json @@ -1,45 +1,45 @@ { - "wires": [ - "HCLK_FIFO_CK_IN3", - "HCLK_FIFO_CK_BUFHCLK5", - "HCLK_FIFO_CK_BUFRCLK0", - "HCLK_FIFO_CK_IN2", - "HCLK_FIFO_CK_BUFHCLK0", - "HCLK_FIFO_CK_BUFRCLK2", - "HCLK_FIFO_CCIO3", - "HCLK_FIFO_CK_IN5", - "HCLK_FIFO_CK_BUFRCLK3", - "HCLK_FIFO_CK_IN8", - "HCLK_FIFO_PERFCLK2", - "HCLK_FIFO_CK_IN13", - "HCLK_FIFO_CK_BUFHCLK2", - "HCLK_FIFO_CK_BUFHCLK3", - "HCLK_FIFO_CK_BUFHCLK8", - "HCLK_FIFO_CCIO2", - "HCLK_FIFO_CK_IN9", - "HCLK_FIFO_CK_IN10", - "HCLK_FIFO_CK_IN7", - "HCLK_FIFO_CK_IN11", - "HCLK_FIFO_CCIO0", - "HCLK_FIFO_CK_BUFHCLK11", - "HCLK_FIFO_CK_IN1", - "HCLK_FIFO_PERFCLK0", - "HCLK_FIFO_CK_IN4", - "HCLK_FIFO_CK_BUFHCLK1", - "HCLK_FIFO_CCIO1", - "HCLK_FIFO_CK_BUFHCLK10", - "HCLK_FIFO_CK_IN0", - "HCLK_FIFO_PERFCLK1", - "HCLK_FIFO_CK_BUFHCLK9", - "HCLK_FIFO_CK_BUFRCLK1", - "HCLK_FIFO_CK_BUFHCLK7", - "HCLK_FIFO_CK_IN6", - "HCLK_FIFO_CK_BUFHCLK4", - "HCLK_FIFO_CK_IN12", - "HCLK_FIFO_PERFCLK3", - "HCLK_FIFO_CK_BUFHCLK6" - ], - "sites": [], "pips": {}, - "tile_type": "HCLK_FIFO_L" + "wires": [ + "HCLK_FIFO_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK4", + "HCLK_FIFO_PERFCLK1", + "HCLK_FIFO_CCIO2", + "HCLK_FIFO_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK8", + "HCLK_FIFO_CK_IN4", + "HCLK_FIFO_CK_IN1", + "HCLK_FIFO_CK_BUFHCLK10", + "HCLK_FIFO_CK_IN8", + "HCLK_FIFO_CK_IN7", + "HCLK_FIFO_CK_IN0", + "HCLK_FIFO_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFRCLK0", + "HCLK_FIFO_CK_IN3", + "HCLK_FIFO_CCIO3", + "HCLK_FIFO_PERFCLK0", + "HCLK_FIFO_CCIO1", + "HCLK_FIFO_CK_IN12", + "HCLK_FIFO_CK_IN9", + "HCLK_FIFO_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFRCLK1", + "HCLK_FIFO_CK_IN13", + "HCLK_FIFO_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFHCLK0", + "HCLK_FIFO_CCIO0", + "HCLK_FIFO_CK_IN11", + "HCLK_FIFO_CK_BUFRCLK2", + "HCLK_FIFO_PERFCLK3", + "HCLK_FIFO_CK_IN10", + "HCLK_FIFO_CK_IN6", + "HCLK_FIFO_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK1", + "HCLK_FIFO_CK_IN2", + "HCLK_FIFO_CK_IN5", + "HCLK_FIFO_PERFCLK2" + ], + "tile_type": "HCLK_FIFO_L", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_GTX.json b/artix7/tile_type_HCLK_GTX.json index 05f8c6d..fdd8b8b 100644 --- a/artix7/tile_type_HCLK_GTX.json +++ b/artix7/tile_type_HCLK_GTX.json @@ -1,21 +1,21 @@ { + "pips": {}, "wires": [ - "HCLK_GTX_CK_IN11", "HCLK_GTX_CK_IN6", - "HCLK_GTX_CK_IN12", - "HCLK_GTX_CK_IN4", - "HCLK_GTX_CK_IN9", + "HCLK_GTX_CK_IN7", "HCLK_GTX_CK_IN3", - "HCLK_GTX_CK_IN5", "HCLK_GTX_CK_IN1", - "HCLK_GTX_CK_IN8", + "HCLK_GTX_CK_IN5", + "HCLK_GTX_CK_IN9", + "HCLK_GTX_CK_IN12", "HCLK_GTX_CK_IN13", - "HCLK_GTX_CK_IN0", + "HCLK_GTX_CK_IN11", "HCLK_GTX_CK_IN2", "HCLK_GTX_CK_IN10", - "HCLK_GTX_CK_IN7" + "HCLK_GTX_CK_IN4", + "HCLK_GTX_CK_IN0", + "HCLK_GTX_CK_IN8" ], - "sites": [], - "pips": {}, - "tile_type": "HCLK_GTX" + "tile_type": "HCLK_GTX", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_INT_INTERFACE.json b/artix7/tile_type_HCLK_INT_INTERFACE.json index 8d9c6c6..127fa9c 100644 --- a/artix7/tile_type_HCLK_INT_INTERFACE.json +++ b/artix7/tile_type_HCLK_INT_INTERFACE.json @@ -1,49 +1,49 @@ { + "pips": {}, "wires": [ - "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_INT_INTERFACE_PERFCLK3", + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_REFCK_WESTCLK1", + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_INT_INTERFACE_PERFCLK1", + "HCLK_INT_INTERFACE_CCIO3", + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_REFCK_WESTCLK0", + "HCLK_INT_INTERFACE_CK_IN3", + "HCLK_INT_INTERFACE_CK_IN6", + "HCLK_INT_INTERFACE_REFCK_EASTCLK0", "HCLK_INT_INTERFACE_REFCK_EASTCLK1", + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_INT_INTERFACE_PERFCLK0", + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_INT_INTERFACE_CCIO1", + "HCLK_INT_INTERFACE_CK_BUFHCLK0", + "HCLK_INT_INTERFACE_CK_IN9", + "HCLK_INT_INTERFACE_CK_BUFHCLK5", "HCLK_INT_INTERFACE_CCIO0", "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_INT_INTERFACE_CK_IN2", - "HCLK_INT_INTERFACE_PERFCLK1", "HCLK_INT_INTERFACE_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN7", - "HCLK_INT_INTERFACE_REFCK_WESTCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_IN3", - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_IN0", - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN1", "HCLK_INT_INTERFACE_CK_IN4", - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_INT_INTERFACE_REFCK_WESTCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_IN6", - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_INT_INTERFACE_CK_IN1", + "HCLK_INT_INTERFACE_PERFCLK2", "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_INT_INTERFACE_CK_BUFHCLK6", + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_INT_INTERFACE_CK_BUFHCLK2", + "HCLK_INT_INTERFACE_CK_IN12", + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_INT_INTERFACE_CK_IN10", + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_INT_INTERFACE_CK_IN7", + "HCLK_INT_INTERFACE_CK_IN8", "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_INT_INTERFACE_REFCK_EASTCLK0", + "HCLK_INT_INTERFACE_CCIO2", "HCLK_INT_INTERFACE_CK_BUFRCLK3" ], - "sites": [], - "pips": {}, - "tile_type": "HCLK_INT_INTERFACE" + "tile_type": "HCLK_INT_INTERFACE", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_IOB.json b/artix7/tile_type_HCLK_IOB.json index e16811d..e3b5102 100644 --- a/artix7/tile_type_HCLK_IOB.json +++ b/artix7/tile_type_HCLK_IOB.json @@ -1,41 +1,41 @@ { + "pips": {}, "wires": [ - "HCLK_IOB_CK_BUFRCLK2", - "HCLK_IOB_CK_BUFHCLK2", - "HCLK_IOB_PERFCLK0", - "HCLK_IOB_CK_BUFHCLK5", - "HCLK_IOB_CK_BUFHCLK7", "HCLK_IOB_CK_BUFHCLK4", - "HCLK_IOB_PERFCLK2", "HCLK_IOB_CK_BUFRCLK0", - "HCLK_IOB_CK_IN12", - "HCLK_IOB_CK_BUFHCLK10", - "HCLK_IOB_CK_IN0", - "HCLK_IOB_PERFCLK3", - "HCLK_IOB_CK_IN4", - "HCLK_IOB_CK_BUFRCLK3", - "HCLK_IOB_CK_IN6", - "HCLK_IOB_CK_IN10", - "HCLK_IOB_PERFCLK1", - "HCLK_IOB_CK_BUFRCLK1", - "HCLK_IOB_CK_IN5", - "HCLK_IOB_CK_BUFHCLK3", - "HCLK_IOB_CK_BUFHCLK11", - "HCLK_IOB_CK_IN11", - "HCLK_IOB_CK_BUFHCLK6", - "HCLK_IOB_CK_IN2", "HCLK_IOB_CK_BUFHCLK9", - "HCLK_IOB_CK_BUFHCLK1", - "HCLK_IOB_CK_BUFHCLK0", "HCLK_IOB_CK_IN3", - "HCLK_IOB_CK_IN13", + "HCLK_IOB_CK_IN5", + "HCLK_IOB_CK_IN2", "HCLK_IOB_CK_BUFHCLK8", "HCLK_IOB_CK_IN1", - "HCLK_IOB_CK_IN8", + "HCLK_IOB_PERFCLK1", + "HCLK_IOB_PERFCLK2", + "HCLK_IOB_CK_IN6", + "HCLK_IOB_CK_IN11", + "HCLK_IOB_PERFCLK0", + "HCLK_IOB_CK_BUFHCLK7", + "HCLK_IOB_CK_IN10", + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOB_CK_IN4", + "HCLK_IOB_CK_BUFHCLK5", + "HCLK_IOB_CK_BUFHCLK1", "HCLK_IOB_CK_IN9", - "HCLK_IOB_CK_IN7" + "HCLK_IOB_CK_BUFHCLK2", + "HCLK_IOB_PERFCLK3", + "HCLK_IOB_CK_BUFHCLK3", + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOB_CK_IN7", + "HCLK_IOB_CK_IN13", + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOB_CK_IN8", + "HCLK_IOB_CK_IN12", + "HCLK_IOB_CK_BUFHCLK6", + "HCLK_IOB_CK_IN0", + "HCLK_IOB_CK_BUFRCLK3" ], - "sites": [], - "pips": {}, - "tile_type": "HCLK_IOB" + "tile_type": "HCLK_IOB", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_IOI3.json b/artix7/tile_type_HCLK_IOI3.json index 03e4a13..335a22a 100644 --- a/artix7/tile_type_HCLK_IOI3.json +++ b/artix7/tile_type_HCLK_IOI3.json @@ -1,1954 +1,1954 @@ { + "pips": { + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CE0->HCLK_IOI_BUFR0_CE": { + "can_invert": "0", + "src_wire": "HCLK_RCLK_DIV_CE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR0_CE" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_IO_PLL_CLK0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK0" + }, + "HCLK_IOI3.HCLK_IOI_BUFIO_O2->>HCLK_IOI_IOCLK2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_BUFIO_O2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CLR2->HCLK_IOI_BUFR2_CLR": { + "can_invert": "0", + "src_wire": "HCLK_RCLK_DIV_CLR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR2_CLR" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT2->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_RCLK1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP2->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT0->>HCLK_IOI_IO_PLL_CLK2_DMUX": { + "can_invert": "0", + "src_wire": "HCLK_IOI_I2IOCLK_BOT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" + }, + "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3->>HCLK_IOI_RCLK_OUT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP3->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK9->>HCLK_IOI_CK_IGCLK9": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK9" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK4->>HCLK_IOI_CK_IGCLK4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK4" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0->>HCLK_IOI_RCLK2IO0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_RCLK2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV0->>HCLK_IOI_RCLK_OUT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK6->>HCLK_IOI_CK_IGCLK6": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK6" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2RCLK0->>HCLK_IOI_CK_BUFRCLK0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK2RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_RCLK3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK3" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2RCLK2->>HCLK_IOI_CK_BUFRCLK2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK2RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_IOCLK_PLL0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IOCLK_PLL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_IOCLK_PLL1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IOCLK_PLL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "HCLK_IOI3.HCLK_IOI_IOCLK_PLL2->>HCLK_IOI_IO_PLL_CLK2_DMUX": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IOCLK_PLL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK1->>HCLK_IOI_CK_IGCLK1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3->>HCLK_IOI_RCLK2IO3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_IO_PLL_CLK1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CE1->HCLK_IOI_BUFR1_CE": { + "can_invert": "0", + "src_wire": "HCLK_RCLK_DIV_CE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR1_CE" + }, + "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { + "can_invert": "0", + "src_wire": "HCLK_IOI_I2IOCLK_TOP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" + }, + "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_IOCLK_PLL3->>HCLK_IOI_IO_PLL_CLK3_DMUX": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IOCLK_PLL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1->>HCLK_IOI_RCLK2IO1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV1->>HCLK_IOI_RCLK_OUT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT1" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT4->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK7->>HCLK_IOI_CK_IGCLK7": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK7" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_BUFIO_O3->>HCLK_IOI_IOCLK3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_BUFIO_O3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_OUT1->>HCLK_IOI_RCLK2RCLK1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_OUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK1" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2RCLK1->>HCLK_IOI_CK_BUFRCLK1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK2RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT1->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK3->>HCLK_IOI_CK_IGCLK3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK0->>HCLK_IOI_CK_IGCLK0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP1->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK10->>HCLK_IOI_CK_IGCLK10": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK10" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK8->>HCLK_IOI_CK_IGCLK8": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK8" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_BUFIO_O0->>HCLK_IOI_IOCLK0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_BUFIO_O0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK0" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK11->>HCLK_IOI_CK_IGCLK11": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK11" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK5->>HCLK_IOI_CK_IGCLK5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK5" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP5->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2->>HCLK_IOI_RCLK2IO2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2IO2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK2->>HCLK_IOI_CK_IGCLK2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_IGCLK2" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CLR3->HCLK_IOI_BUFR3_CLR": { + "can_invert": "0", + "src_wire": "HCLK_RCLK_DIV_CLR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR3_CLR" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_IO_PLL_CLK3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV2->>HCLK_IOI_RCLK_OUT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "HCLK_IOI_RCLK_OUT2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT1->>HCLK_IOI_IO_PLL_CLK3_DMUX": { + "can_invert": "0", + "src_wire": "HCLK_IOI_I2IOCLK_BOT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CLR0->HCLK_IOI_BUFR0_CLR": { + "can_invert": "0", + "src_wire": "HCLK_RCLK_DIV_CLR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR0_CLR" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CE2->HCLK_IOI_BUFR2_CE": { + "can_invert": "0", + "src_wire": "HCLK_RCLK_DIV_CE2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR2_CE" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT5->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_BUFIO_O1->>HCLK_IOI_IOCLK1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_BUFIO_O1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IOCLK1" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_OUT2->>HCLK_IOI_RCLK2RCLK2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_OUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK2" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT3->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { + "can_invert": "0", + "src_wire": "HCLK_IOI_I2IOCLK_TOP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_IO_PLL_CLK2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IO_PLL_CLK2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP0->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT0->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_BOT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_OUT0->>HCLK_IOI_RCLK2RCLK0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_OUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2" + }, + "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_RCLK0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CE3->HCLK_IOI_BUFR3_CE": { + "can_invert": "0", + "src_wire": "HCLK_RCLK_DIV_CE3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR3_CE" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1" + }, + "HCLK_IOI3.HCLK_RCLK_DIV_CLR1->HCLK_IOI_BUFR1_CLR": { + "can_invert": "0", + "src_wire": "HCLK_RCLK_DIV_CLR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_BUFR1_CLR" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP4->>HCLK_IOI_IDELAYCTRL_REFCLK": { + "can_invert": "0", + "src_wire": "HCLK_IOI_LEAF_GCLK_TOP4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2RCLK3->>HCLK_IOI_CK_BUFRCLK3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK2RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_CK_BUFRCLK3" + }, + "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_OUT3->>HCLK_IOI_RCLK2RCLK3": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_OUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK2RCLK3" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT5": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1" + }, + "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_IOI_CK_IGCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4" + }, + "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK_IMUX2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV0": { + "can_invert": "0", + "src_wire": "HCLK_IOI_RCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + } + }, "wires": [ - "HCLK_IOI_BUFR1_CLR", - "HCLK_IOI_BUFIO_O0", - "HCLK_IOI_IO_PLL_CLK3_DMUX", - "HCLK_IOI_RCLK_OUT0", - "HCLK_IOI_CK_BUFHCLK6", - "HCLK_IOI_LEAF_GCLK_BOT1", - "HCLK_IOI_BUFR1_CE", - "HCLK_IOI_LEAF_GCLK_BOT3", - "HCLK_IOI_IO_PLL_CLK0", - "HCLK_IOI_IOCLK2", - "HCLK_IOI_CK_IN5", - "HCLK_IOI_LEAF_GCLK_BOT0", - "HCLK_IOI_LEAF_GCLK_TOP4", - "HCLK_IOI_CK_IN1", - "HCLK_IOI_CK_BUFRCLK3", - "HCLK_IOI_CK_BUFHCLK9", - "HCLK_IOI_BUFIO_O2", - "HCLK_IOI_RCLK_IMUX0", - "HCLK_IOI_RCLK2IO0", - "HCLK_IOI_BUFR2_CLR", - "HCLK_IOI_IDELAYCTRL_REFCLK", - "HCLK_IOI_IO_PLL_CLK3", - "HCLK_RCLK_DIV_CE1", - "HCLK_IOI_LEAF_GCLK_TOP0", - "HCLK_RCLK_DIV_CLR3", - "HCLK_IOI_CK_BUFHCLK11", - "HCLK_IOI_CK_BUFHCLK0", - "HCLK_IOI_IO_PLL_CLK1", - "HCLK_IOI_IOCLK3", - "HCLK_IOI_LEAF_GCLK_TOP3", - "HCLK_IOI_CK_IN0", - "HCLK_IOI_CK_IN10", - "HCLK_IOI_CK_IGCLK2", - "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", - "HCLK_IOI_CK_IGCLK9", - "HCLK_IOI_IOCLK0", - "HCLK_IOI_RCLK_BEFORE_DIV2", - "HCLK_IOI_RCLK2", - "HCLK_IOI_LEAF_GCLK_BOT2", - "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", - "HCLK_IOI_I2IOCLK_TOP1", - "HCLK_RCLK_DIV_CLR0", - "HCLK_IOI_BUFR2_CE", - "HCLK_IOI_IDELAYCTRL_OUTN1", - "HCLK_IOI_CK_IGCLK3", - "HCLK_IOI_CK_BUFHCLK2", - "HCLK_IOI_RCLK_OUT1", - "HCLK_IOI_CK_IN7", - "HCLK_IOI_CK_IN12", - "HCLK_IOI_CK_BUFHCLK1", - "HCLK_IOI_LEAF_GCLK_TOP5", "HCLK_IOI_CK_IGCLK11", - "HCLK_IOI_IOCLK1", - "HCLK_IOI_LEAF_GCLK_TOP2", - "HCLK_IOI_RCLK_IMUX2", - "HCLK_IOI_BUFR3_CLR", - "HCLK_IOI_RCLK_BEFORE_DIV0", - "HCLK_IOI_I2IOCLK_BOT0", - "HCLK_IOI_BUFIO_O3", - "HCLK_IOI_CK_IGCLK6", - "HCLK_IOI_I2IOCLK_TOP0", - "HCLK_IOI_RCLK2RCLK3", - "HCLK_IOI_IO_PLL_CLK2_DMUX", "HCLK_IOI_IO_PLL_CLK1_DMUX", - "HCLK_IOI_CK_IGCLK7", - "HCLK_RCLK_DIV_CLR2", - "HCLK_RCLK_DIV_CLR1", - "HCLK_IOI_CK_IN9", - "HCLK_IOI_RCLK2IO2", - "HCLK_IOI_RCLK_OUT3", - "HCLK_IOI_CK_BUFHCLK7", - "HCLK_IOI_CK_IGCLK5", - "HCLK_IOI_CK_BUFHCLK8", - "HCLK_IOI_CK_BUFRCLK1", - "HCLK_IOI_RCLK_BEFORE_DIV1", - "HCLK_IOI_BUFR0_CE", - "HCLK_IOI_BUFR3_CE", - "HCLK_IOI_IOCLK_PLL0", - "HCLK_IOI_IOCLK_PLL2", - "HCLK_IOI_I2IOCLK_BOT1", - "HCLK_IOI_CK_IN3", - "HCLK_IOI_RCLK0", - "HCLK_IOI_IDELAYCTRL_RST", - "HCLK_IOI_BUFIO_O1", - "HCLK_IOI_IOCLK_PLL3", - "HCLK_IOI_CK_IGCLK8", - "HCLK_IOI_CK_IGCLK0", - "HCLK_IOI_RCLK_IMUX3", - "HCLK_IOI_LEAF_GCLK_TOP1", - "HCLK_IOI_RCLK2RCLK1", - "HCLK_IOI_CK_BUFHCLK4", - "HCLK_IOI_LEAF_GCLK_BOT4", - "HCLK_IOI_CK_BUFHCLK3", - "HCLK_IOI_CK_IGCLK4", - "HCLK_IOI_IDELAYCTRL_RDY", - "HCLK_IOI_RCLK_OUT2", - "HCLK_IOI_CK_BUFHCLK10", - "HCLK_IOI_RCLK_BEFORE_DIV3", - "HCLK_IOI_CK_IN6", - "HCLK_IOI_LEAF_GCLK_BOT5", - "HCLK_IOI_IO_PLL_CLK2", - "HCLK_IOI_IO_PLL_CLK0_DMUX", - "HCLK_IOI_BUFR0_CLR", - "HCLK_IOI_IDELAYCTRL_OUTN65", - "HCLK_IOI_CK_IN11", - "HCLK_IOI_CK_IN4", - "HCLK_IOI_RCLK1", - "HCLK_IOI_CK_IGCLK10", - "HCLK_IOI_CK_IN13", - "HCLK_IOI_CK_IN8", - "HCLK_IOI_RCLK2IO1", - "HCLK_IOI_CK_BUFRCLK2", - "HCLK_IOI_CK_BUFHCLK5", - "HCLK_IOI_CK_IGCLK1", - "HCLK_IOI_RCLK2RCLK2", - "HCLK_IOI_CK_IN2", - "HCLK_RCLK_DIV_CE2", - "HCLK_RCLK_DIV_CE3", - "HCLK_IOI_RCLK3", - "HCLK_IOI_RCLK2IO3", - "HCLK_RCLK_DIV_CE0", - "HCLK_IOI_CK_BUFRCLK0", + "HCLK_RCLK_DIV_CLR3", "HCLK_IOI_IOCLK_PLL1", + "HCLK_IOI_CK_IGCLK7", + "HCLK_IOI_IO_PLL_CLK3_DMUX", + "HCLK_IOI_LEAF_GCLK_BOT4", + "HCLK_IOI_RCLK_BEFORE_DIV2", + "HCLK_IOI_RCLK_BEFORE_DIV0", + "HCLK_IOI_RCLK2RCLK3", + "HCLK_IOI_BUFR3_CLR", + "HCLK_RCLK_DIV_CLR2", + "HCLK_IOI_CK_BUFHCLK10", + "HCLK_IOI_LEAF_GCLK_TOP2", + "HCLK_IOI_BUFIO_O0", + "HCLK_IOI_IDELAYCTRL_RDY", + "HCLK_RCLK_DIV_CE0", + "HCLK_IOI_RCLK2RCLK1", + "HCLK_IOI_BUFR2_CE", + "HCLK_IOI_IOCLK_PLL3", + "HCLK_IOI_CK_IGCLK10", + "HCLK_IOI_LEAF_GCLK_TOP3", + "HCLK_IOI_RCLK2", + "HCLK_IOI_RCLK2IO3", + "HCLK_IOI_CK_BUFRCLK2", + "HCLK_IOI_LEAF_GCLK_TOP0", + "HCLK_IOI_IO_PLL_CLK0", + "HCLK_RCLK_DIV_CLR0", + "HCLK_IOI_CK_IN1", + "HCLK_IOI_CK_IN12", + "HCLK_IOI_CK_IN9", + "HCLK_IOI_CK_BUFHCLK5", + "HCLK_IOI_IDELAYCTRL_OUTN65", + "HCLK_IOI_CK_IGCLK1", + "HCLK_IOI_IOCLK_PLL2", + "HCLK_IOI_RCLK_OUT0", + "HCLK_IOI_IOCLK_PLL0", + "HCLK_IOI_CK_BUFHCLK1", + "HCLK_IOI_BUFR3_CE", + "HCLK_IOI_CK_IN6", + "HCLK_IOI_CK_IN3", + "HCLK_IOI_IDELAYCTRL_OUTN1", + "HCLK_IOI_I2IOCLK_TOP1", + "HCLK_IOI_IOCLK0", + "HCLK_IOI_CK_IN7", + "HCLK_IOI_CK_BUFHCLK6", + "HCLK_IOI_BUFR1_CE", "HCLK_IOI_RCLK2RCLK0", - "HCLK_IOI_RCLK_IMUX1" + "HCLK_IOI_BUFR1_CLR", + "HCLK_IOI_CK_BUFHCLK0", + "HCLK_IOI_BUFR0_CE", + "HCLK_IOI_RCLK3", + "HCLK_IOI_RCLK_OUT2", + "HCLK_IOI_CK_IGCLK6", + "HCLK_IOI_LEAF_GCLK_TOP1", + "HCLK_IOI_CK_BUFHCLK7", + "HCLK_IOI_IOCLK3", + "HCLK_IOI_BUFIO_O2", + "HCLK_RCLK_DIV_CE1", + "HCLK_IOI_I2IOCLK_BOT0", + "HCLK_IOI_RCLK_IMUX2", + "HCLK_IOI_BUFR2_CLR", + "HCLK_IOI_CK_BUFHCLK11", + "HCLK_IOI_IOCLK1", + "HCLK_IOI_CK_IGCLK3", + "HCLK_IOI_IO_PLL_CLK0_DMUX", + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "HCLK_IOI_CK_IGCLK0", + "HCLK_IOI_IO_PLL_CLK3", + "HCLK_IOI_CK_BUFRCLK3", + "HCLK_IOI_RCLK_IMUX3", + "HCLK_IOI_LEAF_GCLK_BOT2", + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", + "HCLK_IOI_IO_PLL_CLK2_DMUX", + "HCLK_IOI_RCLK2IO1", + "HCLK_IOI_I2IOCLK_TOP0", + "HCLK_IOI_CK_BUFHCLK4", + "HCLK_IOI_IO_PLL_CLK2", + "HCLK_IOI_CK_IN4", + "HCLK_IOI_RCLK_BEFORE_DIV1", + "HCLK_IOI_CK_IGCLK4", + "HCLK_IOI_LEAF_GCLK_TOP5", + "HCLK_RCLK_DIV_CLR1", + "HCLK_IOI_CK_IN0", + "HCLK_IOI_IDELAYCTRL_RST", + "HCLK_IOI_LEAF_GCLK_BOT5", + "HCLK_IOI_RCLK2RCLK2", + "HCLK_IOI_BUFIO_O3", + "HCLK_IOI_LEAF_GCLK_BOT1", + "HCLK_IOI_I2IOCLK_BOT1", + "HCLK_IOI_RCLK0", + "HCLK_IOI_CK_IGCLK8", + "HCLK_IOI_CK_IN5", + "HCLK_IOI_CK_IN2", + "HCLK_RCLK_DIV_CE3", + "HCLK_IOI_CK_IGCLK9", + "HCLK_IOI_CK_BUFHCLK2", + "HCLK_IOI_LEAF_GCLK_BOT3", + "HCLK_IOI_RCLK_IMUX1", + "HCLK_IOI_LEAF_GCLK_TOP4", + "HCLK_IOI_CK_IN11", + "HCLK_IOI_CK_IN8", + "HCLK_IOI_RCLK_OUT3", + "HCLK_IOI_LEAF_GCLK_BOT0", + "HCLK_IOI_RCLK_BEFORE_DIV3", + "HCLK_IOI_RCLK2IO2", + "HCLK_IOI_RCLK2IO0", + "HCLK_RCLK_DIV_CE2", + "HCLK_IOI_CK_IGCLK5", + "HCLK_IOI_BUFR0_CLR", + "HCLK_IOI_CK_IN10", + "HCLK_IOI_CK_BUFHCLK3", + "HCLK_IOI_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFHCLK8", + "HCLK_IOI_RCLK1", + "HCLK_IOI_RCLK_OUT1", + "HCLK_IOI_CK_IGCLK2", + "HCLK_IOI_CK_BUFRCLK0", + "HCLK_IOI_IDELAYCTRL_REFCLK", + "HCLK_IOI_BUFIO_O1", + "HCLK_IOI_IO_PLL_CLK1", + "HCLK_IOI_IOCLK2", + "HCLK_IOI_CK_IN13", + "HCLK_IOI_RCLK_IMUX0", + "HCLK_IOI_CK_BUFHCLK9" ], + "tile_type": "HCLK_IOI3", "sites": [ { - "prefix": "BUFIO", - "y_coord": 7, - "type": "BUFIO", "site_pins": { "I": "HCLK_IOI_IO_PLL_CLK3", "O": "HCLK_IOI_BUFIO_O3" }, + "type": "BUFIO", + "prefix": "BUFIO", + "name": "X0Y7", "x_coord": 0, - "name": "X0Y7" + "y_coord": 7 }, { - "prefix": "BUFIO", - "y_coord": 6, - "type": "BUFIO", "site_pins": { "I": "HCLK_IOI_IO_PLL_CLK2", "O": "HCLK_IOI_BUFIO_O2" }, + "type": "BUFIO", + "prefix": "BUFIO", + "name": "X0Y6", "x_coord": 0, - "name": "X0Y6" + "y_coord": 6 }, { - "prefix": "BUFIO", - "y_coord": 9, - "type": "BUFIO", "site_pins": { "I": "HCLK_IOI_IO_PLL_CLK1", "O": "HCLK_IOI_BUFIO_O1" }, + "type": "BUFIO", + "prefix": "BUFIO", + "name": "X0Y9", "x_coord": 0, - "name": "X0Y9" + "y_coord": 9 }, { - "prefix": "BUFIO", - "y_coord": 8, - "type": "BUFIO", "site_pins": { "I": "HCLK_IOI_IO_PLL_CLK0", "O": "HCLK_IOI_BUFIO_O0" }, + "type": "BUFIO", + "prefix": "BUFIO", + "name": "X0Y8", "x_coord": 0, - "name": "X0Y8" + "y_coord": 8 }, { - "prefix": "BUFR", - "y_coord": 7, - "type": "BUFR", "site_pins": { + "CLR": "HCLK_IOI_BUFR3_CLR", "I": "HCLK_IOI_RCLK_BEFORE_DIV3", - "O": "HCLK_IOI_RCLK_OUT3", "CE": "HCLK_IOI_BUFR3_CE", - "CLR": "HCLK_IOI_BUFR3_CLR" + "O": "HCLK_IOI_RCLK_OUT3" }, + "type": "BUFR", + "prefix": "BUFR", + "name": "X0Y7", "x_coord": 0, - "name": "X0Y7" + "y_coord": 7 }, { - "prefix": "BUFR", - "y_coord": 6, - "type": "BUFR", "site_pins": { + "CLR": "HCLK_IOI_BUFR2_CLR", "I": "HCLK_IOI_RCLK_BEFORE_DIV2", - "O": "HCLK_IOI_RCLK_OUT2", "CE": "HCLK_IOI_BUFR2_CE", - "CLR": "HCLK_IOI_BUFR2_CLR" + "O": "HCLK_IOI_RCLK_OUT2" }, + "type": "BUFR", + "prefix": "BUFR", + "name": "X0Y6", "x_coord": 0, - "name": "X0Y6" + "y_coord": 6 }, { - "prefix": "BUFR", - "y_coord": 9, - "type": "BUFR", "site_pins": { + "CLR": "HCLK_IOI_BUFR1_CLR", "I": "HCLK_IOI_RCLK_BEFORE_DIV1", - "O": "HCLK_IOI_RCLK_OUT1", "CE": "HCLK_IOI_BUFR1_CE", - "CLR": "HCLK_IOI_BUFR1_CLR" + "O": "HCLK_IOI_RCLK_OUT1" }, - "x_coord": 0, - "name": "X0Y9" - }, - { - "prefix": "BUFR", - "y_coord": 8, "type": "BUFR", - "site_pins": { - "I": "HCLK_IOI_RCLK_BEFORE_DIV0", - "O": "HCLK_IOI_RCLK_OUT0", - "CE": "HCLK_IOI_BUFR0_CE", - "CLR": "HCLK_IOI_BUFR0_CLR" - }, + "prefix": "BUFR", + "name": "X0Y9", "x_coord": 0, - "name": "X0Y8" + "y_coord": 9 }, { - "prefix": "IDELAYCTRL", - "y_coord": 0, - "type": "IDELAYCTRL", "site_pins": { - "UPPULSEOUT": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", - "RDY": "HCLK_IOI_IDELAYCTRL_RDY", - "OUTN1": "HCLK_IOI_IDELAYCTRL_OUTN1", - "REFCLK": "HCLK_IOI_IDELAYCTRL_REFCLK", - "DNPULSEOUT": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", - "OUTN65": "HCLK_IOI_IDELAYCTRL_OUTN65", - "RST": "HCLK_IOI_IDELAYCTRL_RST" + "CLR": "HCLK_IOI_BUFR0_CLR", + "I": "HCLK_IOI_RCLK_BEFORE_DIV0", + "CE": "HCLK_IOI_BUFR0_CE", + "O": "HCLK_IOI_RCLK_OUT0" }, + "type": "BUFR", + "prefix": "BUFR", + "name": "X0Y8", "x_coord": 0, - "name": "X0Y0" + "y_coord": 8 + }, + { + "site_pins": { + "OUTN1": "HCLK_IOI_IDELAYCTRL_OUTN1", + "RST": "HCLK_IOI_IDELAYCTRL_RST", + "DNPULSEOUT": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", + "REFCLK": "HCLK_IOI_IDELAYCTRL_REFCLK", + "RDY": "HCLK_IOI_IDELAYCTRL_RDY", + "OUTN65": "HCLK_IOI_IDELAYCTRL_OUTN65", + "UPPULSEOUT": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT" + }, + "type": "IDELAYCTRL", + "prefix": "IDELAYCTRL", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 } - ], - "pips": { - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV0->>HCLK_IOI_RCLK_OUT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_OUT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", - "is_pseudo": "1" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IOCLK_PLL0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", - "is_directional": "1", - "src_wire": "HCLK_IOI_IOCLK_PLL0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1->>HCLK_IOI_RCLK2IO1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK2IO1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP0->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK6->>HCLK_IOI_CK_IGCLK6": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK6", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT1->>HCLK_IOI_IO_PLL_CLK3_DMUX": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", - "is_directional": "1", - "src_wire": "HCLK_IOI_I2IOCLK_BOT1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3->>HCLK_IOI_RCLK2IO3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK2IO3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_IO_PLL_CLK1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK1", - "is_directional": "1", - "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_RCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK3", - "is_directional": "1", - "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT3->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_BUFIO_O3->>HCLK_IOI_IOCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IOCLK3", - "is_directional": "1", - "src_wire": "HCLK_IOI_BUFIO_O3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP5->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_RCLK_DIV_CE3->HCLK_IOI_BUFR3_CE": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_BUFR3_CE", - "is_directional": "1", - "src_wire": "HCLK_RCLK_DIV_CE3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK2RCLK0->>HCLK_IOI_CK_BUFRCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_BUFRCLK0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK2RCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_IO_PLL_CLK2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK2", - "is_directional": "1", - "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2->>HCLK_IOI_RCLK2IO2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK2IO2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_OUT0->>HCLK_IOI_RCLK2RCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK2RCLK0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_OUT0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV1->>HCLK_IOI_RCLK_OUT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_OUT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", - "is_pseudo": "1" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_OUT1->>HCLK_IOI_RCLK2RCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK2RCLK1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_OUT1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT0->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_BUFIO_O0->>HCLK_IOI_IOCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IOCLK0", - "is_directional": "1", - "src_wire": "HCLK_IOI_BUFIO_O0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP4->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP2->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK7->>HCLK_IOI_CK_IGCLK7": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK7", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT1->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP3->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT4->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT5->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV2->>HCLK_IOI_RCLK_OUT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_OUT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", - "is_pseudo": "1" - }, - "HCLK_IOI3.HCLK_IOI_BUFIO_O1->>HCLK_IOI_IOCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IOCLK1", - "is_directional": "1", - "src_wire": "HCLK_IOI_BUFIO_O1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_RCLK_DIV_CLR2->HCLK_IOI_BUFR2_CLR": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_BUFR2_CLR", - "is_directional": "1", - "src_wire": "HCLK_RCLK_DIV_CLR2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK2RCLK2->>HCLK_IOI_CK_BUFRCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_BUFRCLK2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK2RCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_OUT3->>HCLK_IOI_RCLK2RCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK2RCLK3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_OUT3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK8->>HCLK_IOI_CK_IGCLK8": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK8", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_OUT2->>HCLK_IOI_RCLK2RCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK2RCLK2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_OUT2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_RCLK_DIV_CE1->HCLK_IOI_BUFR1_CE": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_BUFR1_CE", - "is_directional": "1", - "src_wire": "HCLK_RCLK_DIV_CE1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_IO_PLL_CLK3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK3", - "is_directional": "1", - "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK11->>HCLK_IOI_CK_IGCLK11": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK11", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_RCLK_DIV_CLR0->HCLK_IOI_BUFR0_CLR": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_BUFR0_CLR", - "is_directional": "1", - "src_wire": "HCLK_RCLK_DIV_CLR0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK2RCLK1->>HCLK_IOI_CK_BUFRCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_BUFRCLK1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK2RCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK3->>HCLK_IOI_CK_IGCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_RCLK_DIV_CE0->HCLK_IOI_BUFR0_CE": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_BUFR0_CE", - "is_directional": "1", - "src_wire": "HCLK_RCLK_DIV_CE0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IOCLK_PLL3->>HCLK_IOI_IO_PLL_CLK3_DMUX": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", - "is_directional": "1", - "src_wire": "HCLK_IOI_IOCLK_PLL3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_RCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK0", - "is_directional": "1", - "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_IO_PLL_CLK0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK0", - "is_directional": "1", - "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK0->>HCLK_IOI_CK_IGCLK0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_BEFORE_DIV3->>HCLK_IOI_RCLK_OUT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_OUT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", - "is_pseudo": "1" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT0->>HCLK_IOI_IO_PLL_CLK2_DMUX": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", - "is_directional": "1", - "src_wire": "HCLK_IOI_I2IOCLK_BOT0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT2->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK1->>HCLK_IOI_CK_IGCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_RCLK1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK1", - "is_directional": "1", - "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK8", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_BUFIO_O2->>HCLK_IOI_IOCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IOCLK2", - "is_directional": "1", - "src_wire": "HCLK_IOI_BUFIO_O2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK4->>HCLK_IOI_CK_IGCLK4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK2RCLK3->>HCLK_IOI_CK_BUFRCLK3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_BUFRCLK3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK2RCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_RCLK_DIV_CLR1->HCLK_IOI_BUFR1_CLR": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_BUFR1_CLR", - "is_directional": "1", - "src_wire": "HCLK_RCLK_DIV_CLR1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", - "is_directional": "1", - "src_wire": "HCLK_IOI_I2IOCLK_TOP1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP1->>HCLK_IOI_IDELAYCTRL_REFCLK": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", - "is_directional": "1", - "src_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", - "is_directional": "1", - "src_wire": "HCLK_IOI_I2IOCLK_TOP0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV1": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK10->>HCLK_IOI_CK_IGCLK10": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK10", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK9->>HCLK_IOI_CK_IGCLK9": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK9", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_RCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK2", - "is_directional": "1", - "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK10", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_RCLK_DIV_CE2->HCLK_IOI_BUFR2_CE": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_BUFR2_CE", - "is_directional": "1", - "src_wire": "HCLK_RCLK_DIV_CE2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK5->>HCLK_IOI_CK_IGCLK5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK4", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK2->>HCLK_IOI_CK_IGCLK2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_CK_IGCLK2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK11", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IOCLK_PLL2->>HCLK_IOI_IO_PLL_CLK2_DMUX": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", - "is_directional": "1", - "src_wire": "HCLK_IOI_IOCLK_PLL2", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0->>HCLK_IOI_RCLK2IO0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK2IO0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_IOCLK_PLL1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", - "is_directional": "1", - "src_wire": "HCLK_IOI_IOCLK_PLL1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK6", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX0", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK7", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_RCLK_DIV_CLR3->HCLK_IOI_BUFR3_CLR": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_BUFR3_CLR", - "is_directional": "1", - "src_wire": "HCLK_RCLK_DIV_CLR3", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK9", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", - "is_directional": "1", - "src_wire": "HCLK_IOI_CK_IGCLK1", - "is_pseudo": "0" - }, - "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV0": { - "can_invert": "0", - "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", - "is_directional": "1", - "src_wire": "HCLK_IOI_RCLK_IMUX3", - "is_pseudo": "0" - } - }, - "tile_type": "HCLK_IOI3" + ] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_L.json b/artix7/tile_type_HCLK_L.json index 57fa49a..617a363 100644 --- a/artix7/tile_type_HCLK_L.json +++ b/artix7/tile_type_HCLK_L.json @@ -1,1695 +1,1695 @@ { - "wires": [ - "HCLK_CK_IN12", - "HCLK_SS6E3", - "HCLK_LVB12", - "HCLK_LVB9", - "HCLK_SS2A3", - "HCLK_SE2A0", - "HCLK_FAN_BOUNCE_S3_0", - "HCLK_LEAF_CLK_B_TOPL3", - "HCLK_CK_OUTIN_L3", - "HCLK_NL1BEG1", - "HCLK_NE6C0", - "HCLK_NE2BEG3", - "HCLK_NR1BEG1", - "HCLK_LEAF_CLK_B_TOPL1", - "HCLK_SS6C1", - "HCLK_REFCK_WESTCLK0", - "HCLK_NN6BEG2", - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK4", - "HCLK_NW6C1", - "HCLK_INT_PERFCLK3", - "HCLK_LV1", - "HCLK_NN6D3", - "HCLK_SE2A3", - "HCLK_CK_OUTIN_L5", - "HCLK_CK_OUTIN_L0", - "HCLK_SW2END1", - "HCLK_FAN_BOUNCE_S3_2", - "HCLK_LEAF_CLK_B_BOTL1", - "HCLK_CK_IN13", - "HCLK_WR1END_S1_0", - "HCLK_CK_OUTIN_L6", - "HCLK_NN6BEG0", - "HCLK_WL1BEG3", - "HCLK_NN6D0", - "HCLK_SL1END3", - "HCLK_LEAF_CLK_B_TOPL2", - "HCLK_NN6BEG1", - "HCLK_REFCK_WESTCLK1", - "HCLK_NE2END_S3_0", - "HCLK_SR1END_N3_3", - "HCLK_CK_INOUT_L1", - "HCLK_NW6A1", - "HCLK_CK_BUFHCLK10", - "HCLK_SW6E1", - "HCLK_SE6C1", - "HCLK_NR1BEG0", - "HCLK_SW6END3", - "HCLK_SS6C3", - "HCLK_CK_OUTIN_L4", - "HCLK_SW2END_N0_3", - "HCLK_SR1BEG3", - "HCLK_NW2A0", - "HCLK_LEAF_CLK_B_BOTL3", - "HCLK_SS6A2", - "HCLK_CK_INOUT_L6", - "HCLK_NN6B0", - "HCLK_LVB10", - "HCLK_FAN_BOUNCE_S3_4", - "HCLK_NN6B2", - "HCLK_SS6A1", - "HCLK_WW4END_S0_0", - "HCLK_LV5", - "HCLK_NE6D3", - "HCLK_LEAF_CLK_B_BOTL5", - "HCLK_NE6A3", - "HCLK_NE6D0", - "HCLK_NN2BEG0", - "HCLK_NN6E0", - "HCLK_WR1BEG_S0", - "HCLK_NN6E1", - "HCLK_NW6C2", - "HCLK_NN2A0", - "HCLK_SS2END2", - "HCLK_NW6D1", - "HCLK_CK_IN6", - "HCLK_NW6B1", - "HCLK_SL1END1", - "HCLK_REFCK_EASTCLK1", - "HCLK_LV0", - "HCLK_SW6B0", - "HCLK_CK_IN5", - "HCLK_LVB7", - "HCLK_NW6D0", - "HCLK_SE6E0", - "HCLK_WW2END3", - "HCLK_SW6D2", - "HCLK_SW6E2", - "HCLK_SW2END2", - "HCLK_NN6E2", - "HCLK_LV4", - "HCLK_LV10", - "HCLK_BYP_BOUNCE7", - "HCLK_NN2A1", - "HCLK_LV12", - "HCLK_SS2A1", - "HCLK_INT_PERFCLK1", - "HCLK_LEAF_CLK_B_TOPL5", - "HCLK_SE6D2", - "HCLK_SW6B2", - "HCLK_CK_IN9", - "HCLK_BYP_BOUNCE6", - "HCLK_NL1END_S3_0", - "HCLK_CK_OUTIN_L2", - "HCLK_CCIO0", - "HCLK_NW6B0", - "HCLK_SR1END2", - "HCLK_LVB6", - "HCLK_NE6B0", - "HCLK_LV14", - "HCLK_SW6D0", - "HCLK_SS6END1", - "HCLK_CK_OUTIN_L1", - "HCLK_CK_BUFHCLK5", - "HCLK_SE6D0", - "HCLK_SS6E1", - "HCLK_SE6B0", - "HCLK_SE6D3", - "HCLK_LV15", - "HCLK_CK_IN7", - "HCLK_LEAF_CLK_B_BOTL4", - "HCLK_CK_IN4", - "HCLK_SW6E3", - "HCLK_NN6C1", - "HCLK_SS6C2", - "HCLK_LV2", - "HCLK_SS6D0", - "HCLK_NN6BEG3", - "HCLK_SE6C2", - "HCLK_CK_INOUT_L4", - "HCLK_SE6B2", - "HCLK_SW6C2", - "HCLK_SS6A0", - "HCLK_CK_IN3", - "HCLK_SS6B3", - "HCLK_LVB1", - "HCLK_SS6D1", - "HCLK_NW6D2", - "HCLK_REFCK_EASTCLK0", - "HCLK_NR1BEG2", - "HCLK_NL1BEG0", - "HCLK_SE6E2", - "HCLK_NE2BEG0", - "HCLK_NW6A2", - "HCLK_NN2BEG1", - "HCLK_NW6A3", - "HCLK_LEAF_CLK_B_BOTL2", - "HCLK_NE6B3", - "HCLK_CK_IN1", - "HCLK_SS6END_N0_3", - "HCLK_NN6A1", - "HCLK_NE2BEG1", - "HCLK_NN2BEG2", - "HCLK_SW6C1", - "HCLK_NW2A1", - "HCLK_SS6A3", - "HCLK_CK_BUFHCLK1", - "HCLK_LV16", - "HCLK_NN6A3", - "HCLK_SS2BEG3", - "HCLK_BYP_BOUNCE3", - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK0", - "HCLK_LV6", - "HCLK_SW6C3", - "HCLK_SS6D3", - "HCLK_NE6D1", - "HCLK_LVB4", - "HCLK_SS2END0", - "HCLK_NN6C0", - "HCLK_NE6C3", - "HCLK_SE6E1", - "HCLK_SW6C0", - "HCLK_NW2END_S0_0", - "HCLK_NW6END_S0_0", - "HCLK_LV7", - "HCLK_NN6B1", - "HCLK_NE6D2", - "HCLK_SS6END2", - "HCLK_NE6A1", - "HCLK_SW6E0", - "HCLK_SW2END0", - "HCLK_LEAF_CLK_B_BOTL0", - "HCLK_ER1END3", - "HCLK_SW6B1", - "HCLK_CK_INOUT_L2", - "HCLK_NN2END_S2_0", - "HCLK_LV3", - "HCLK_SE6C3", - "HCLK_NE6A2", - "HCLK_SW6D1", - "HCLK_NW2A3", - "HCLK_NN6C2", - "HCLK_NE6C1", - "HCLK_NR1BEG3", - "HCLK_NN6C3", - "HCLK_NE6B2", - "HCLK_CK_BUFHCLK8", - "HCLK_CK_OUTIN_L7", - "HCLK_EL1END_S3_0", - "HCLK_NN6A0", - "HCLK_CK_INOUT_L3", - "HCLK_NW6B2", - "HCLK_SS2END1", - "HCLK_SW2A3", - "HCLK_SS6D2", - "HCLK_SS2END_N0_3", - "HCLK_NW6C3", - "HCLK_CCIO2", - "HCLK_NE2BEG2", - "HCLK_CK_BUFHCLK6", - "HCLK_NN2BEG3", - "HCLK_NN6A2", - "HCLK_SS6E0", - "HCLK_SE6B1", - "HCLK_SE2A1", - "HCLK_NW6C0", - "HCLK_NL1BEG2", - "HCLK_CK_IN8", - "HCLK_WL1END3", - "HCLK_LV9", - "HCLK_CK_INOUT_L7", - "HCLK_LVB8", - "HCLK_BYP_BOUNCE2", - "HCLK_SS6B1", - "HCLK_SE6B3", - "HCLK_LEAF_CLK_B_TOPL4", - "HCLK_SS6B2", - "HCLK_SS2A2", - "HCLK_NW6B3", - "HCLK_NW2A2", - "HCLK_SS2A0", - "HCLK_SE2A2", - "HCLK_SE6E3", - "HCLK_SW6B3", - "HCLK_LVB11", - "HCLK_CK_IN0", - "HCLK_CK_BUFRCLK3", - "HCLK_INT_PERFCLK0", - "HCLK_NN6D1", - "HCLK_NN2A2", - "HCLK_CCIO3", - "HCLK_NW6D3", - "HCLK_LVB3", - "HCLK_SS6E2", - "HCLK_CK_BUFHCLK7", - "HCLK_CK_IN2", - "HCLK_CK_BUFHCLK2", - "HCLK_SS6END3", - "HCLK_NE6A0", - "HCLK_SE6D1", - "HCLK_NE6C2", - "HCLK_NN2A3", - "HCLK_SE6C0", - "HCLK_EL1BEG3", - "HCLK_CK_IN11", - "HCLK_ER1BEG_S0", - "HCLK_LV8", - "HCLK_NN6B3", - "HCLK_LVB5", - "HCLK_SL1END0", - "HCLK_INT_PERFCLK2", - "HCLK_CK_IN10", - "HCLK_CCIO1", - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK1", - "HCLK_FAN_BOUNCE_S3_6", - "HCLK_LV17", - "HCLK_SS6B0", - "HCLK_LEAF_CLK_B_TOPL0", - "HCLK_LVB2", - "HCLK_NN6END_S1_0", - "HCLK_SS6END0", - "HCLK_NN6E3", - "HCLK_SW6D3", - "HCLK_CK_INOUT_L5", - "HCLK_CK_BUFRCLK0", - "HCLK_LV13", - "HCLK_NE6B1", - "HCLK_SS6C0", - "HCLK_LV11", - "HCLK_NW6A0", - "HCLK_CK_INOUT_L0", - "HCLK_SR1END1", - "HCLK_SL1END2", - "HCLK_CK_BUFHCLK9", - "HCLK_NN6D2" - ], - "sites": [], "pips": { - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_CK_INOUT_L3": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_CK_INOUT_L0": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_CK_INOUT_L4": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_CK_INOUT_L1": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_CK_INOUT_L7": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L7", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_CK_INOUT_L2": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_CK_INOUT_L6": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L6", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_CK_INOUT_L5": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_CK_INOUT_L6": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L6" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_CK_INOUT_L4": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L4" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_CK_INOUT_L2": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L2" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_CK_INOUT_L0": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_CK_INOUT_L3": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L3" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_CK_INOUT_L1": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L1" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_CK_INOUT_L7": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L7" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL3": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_CK_INOUT_L5": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L5" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL1": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFHCLK9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_BUFHCLK11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL2": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL2" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL1": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL1" + }, + "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_BUFRCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_BUFRCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL0": { + "src_wire": "HCLK_CK_OUTIN_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL4": { + "src_wire": "HCLK_CK_OUTIN_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL5": { + "src_wire": "HCLK_CK_BUFRCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL5" + }, + "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL0": { + "src_wire": "HCLK_CK_OUTIN_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL4": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOTL4" + }, + "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_OUTIN_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL2": { + "src_wire": "HCLK_CK_BUFHCLK10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL5": { + "src_wire": "HCLK_CK_OUTIN_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL3": { + "src_wire": "HCLK_CK_BUFRCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" } }, - "tile_type": "HCLK_L" + "wires": [ + "HCLK_SE6D1", + "HCLK_LV10", + "HCLK_SS2END_N0_3", + "HCLK_NE6B2", + "HCLK_INT_PERFCLK1", + "HCLK_NN2A0", + "HCLK_SS2A0", + "HCLK_NW6A0", + "HCLK_SE6B0", + "HCLK_NW2A2", + "HCLK_CK_IN3", + "HCLK_SW6E1", + "HCLK_SS2END2", + "HCLK_BYP_BOUNCE7", + "HCLK_NN2A3", + "HCLK_NE2END_S3_0", + "HCLK_SW6C3", + "HCLK_SS6B1", + "HCLK_SS2END1", + "HCLK_SW6D0", + "HCLK_NE6B3", + "HCLK_CK_INOUT_L2", + "HCLK_NN2A2", + "HCLK_INT_PERFCLK0", + "HCLK_CCIO3", + "HCLK_CK_BUFHCLK3", + "HCLK_NE6A3", + "HCLK_NE6B0", + "HCLK_SE6C0", + "HCLK_SL1END1", + "HCLK_LEAF_CLK_B_BOTL4", + "HCLK_NN6B3", + "HCLK_NE2BEG1", + "HCLK_SE6B3", + "HCLK_LEAF_CLK_B_TOPL5", + "HCLK_SW6D3", + "HCLK_NL1BEG0", + "HCLK_SW2END1", + "HCLK_NN6BEG3", + "HCLK_SW6C1", + "HCLK_FAN_BOUNCE_S3_6", + "HCLK_NW6D1", + "HCLK_CK_IN13", + "HCLK_SS6END0", + "HCLK_SW6E2", + "HCLK_LV16", + "HCLK_LVB4", + "HCLK_CK_INOUT_L6", + "HCLK_NE6A0", + "HCLK_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK8", + "HCLK_NR1BEG0", + "HCLK_LV9", + "HCLK_SE6D3", + "HCLK_LV8", + "HCLK_EL1BEG3", + "HCLK_NN6BEG1", + "HCLK_NE6A1", + "HCLK_CK_IN0", + "HCLK_CK_IN5", + "HCLK_NN6D1", + "HCLK_NN2A1", + "HCLK_NW6B0", + "HCLK_INT_PERFCLK2", + "HCLK_SS6D0", + "HCLK_NN6B2", + "HCLK_WR1BEG_S0", + "HCLK_CK_INOUT_L7", + "HCLK_SW6C2", + "HCLK_SE2A0", + "HCLK_NW2A0", + "HCLK_SW2END2", + "HCLK_LV12", + "HCLK_CK_BUFRCLK2", + "HCLK_SW6B3", + "HCLK_NW6A1", + "HCLK_SS6END_N0_3", + "HCLK_CK_BUFHCLK0", + "HCLK_LV17", + "HCLK_CK_OUTIN_L7", + "HCLK_LV6", + "HCLK_SS6A0", + "HCLK_NW6D3", + "HCLK_ER1END3", + "HCLK_SW2A3", + "HCLK_NN6D0", + "HCLK_NN6A0", + "HCLK_NW6D0", + "HCLK_SW6D2", + "HCLK_NN2BEG2", + "HCLK_SS6E0", + "HCLK_NN6D3", + "HCLK_SS6END2", + "HCLK_CK_OUTIN_L3", + "HCLK_SS6D2", + "HCLK_CK_BUFHCLK7", + "HCLK_LVB2", + "HCLK_SS6END3", + "HCLK_LEAF_CLK_B_TOPL3", + "HCLK_WL1BEG3", + "HCLK_CK_BUFRCLK0", + "HCLK_NE2BEG0", + "HCLK_CK_BUFRCLK1", + "HCLK_SE6D0", + "HCLK_SS6A2", + "HCLK_SL1END2", + "HCLK_NN6A1", + "HCLK_SS6D1", + "HCLK_CK_BUFHCLK6", + "HCLK_NN2END_S2_0", + "HCLK_NN6C1", + "HCLK_LEAF_CLK_B_TOPL4", + "HCLK_LEAF_CLK_B_BOTL2", + "HCLK_NR1BEG1", + "HCLK_SE6B1", + "HCLK_CK_OUTIN_L4", + "HCLK_REFCK_WESTCLK1", + "HCLK_CK_IN11", + "HCLK_WR1END_S1_0", + "HCLK_LEAF_CLK_B_BOTL1", + "HCLK_CK_IN10", + "HCLK_NN6BEG0", + "HCLK_CK_IN7", + "HCLK_SE6E0", + "HCLK_SS2BEG3", + "HCLK_LVB5", + "HCLK_NN6B0", + "HCLK_LV13", + "HCLK_SS6B3", + "HCLK_LV0", + "HCLK_SW6B1", + "HCLK_NN2BEG0", + "HCLK_LV1", + "HCLK_SR1END2", + "HCLK_LVB6", + "HCLK_CK_OUTIN_L1", + "HCLK_SL1END0", + "HCLK_SS6C1", + "HCLK_NW6A2", + "HCLK_LVB8", + "HCLK_NW6B1", + "HCLK_SW6END3", + "HCLK_NE2BEG2", + "HCLK_CK_INOUT_L1", + "HCLK_CK_IN12", + "HCLK_SW6B0", + "HCLK_SS2A3", + "HCLK_NN6E0", + "HCLK_NN6A3", + "HCLK_SS6E2", + "HCLK_NW6C2", + "HCLK_LVB12", + "HCLK_SS2A1", + "HCLK_LV15", + "HCLK_NL1BEG2", + "HCLK_NN6END_S1_0", + "HCLK_LV5", + "HCLK_NN6BEG2", + "HCLK_CK_OUTIN_L6", + "HCLK_LEAF_CLK_B_TOPL0", + "HCLK_LEAF_CLK_B_BOTL5", + "HCLK_SW6D1", + "HCLK_CCIO0", + "HCLK_LV4", + "HCLK_CK_OUTIN_L5", + "HCLK_SR1BEG3", + "HCLK_SS6E1", + "HCLK_CK_BUFHCLK9", + "HCLK_SE6E3", + "HCLK_NN6D2", + "HCLK_NW6C0", + "HCLK_LEAF_CLK_B_BOTL0", + "HCLK_LVB3", + "HCLK_SS6E3", + "HCLK_SS6A3", + "HCLK_SE6D2", + "HCLK_SE6C1", + "HCLK_SS6B2", + "HCLK_SS6A1", + "HCLK_SS2A2", + "HCLK_SW2END_N0_3", + "HCLK_NW2END_S0_0", + "HCLK_CK_IN6", + "HCLK_LEAF_CLK_B_TOPL1", + "HCLK_SS6END1", + "HCLK_NN6E3", + "HCLK_NW6A3", + "HCLK_SS6B0", + "HCLK_FAN_BOUNCE_S3_2", + "HCLK_REFCK_EASTCLK1", + "HCLK_NR1BEG2", + "HCLK_BYP_BOUNCE3", + "HCLK_INT_PERFCLK3", + "HCLK_SS6C3", + "HCLK_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK10", + "HCLK_NN6E2", + "HCLK_LVB11", + "HCLK_NE6C0", + "HCLK_CK_BUFHCLK11", + "HCLK_SS2END0", + "HCLK_NN6C3", + "HCLK_SE6E2", + "HCLK_NE6D2", + "HCLK_SE6B2", + "HCLK_NN6C0", + "HCLK_NE6A2", + "HCLK_BYP_BOUNCE2", + "HCLK_LVB7", + "HCLK_NW6END_S0_0", + "HCLK_NN2BEG3", + "HCLK_SR1END1", + "HCLK_SE6C2", + "HCLK_SS6C2", + "HCLK_NE6C2", + "HCLK_CCIO1", + "HCLK_NW2A3", + "HCLK_FAN_BOUNCE_S3_0", + "HCLK_LEAF_CLK_B_BOTL3", + "HCLK_NL1END_S3_0", + "HCLK_NE6D0", + "HCLK_CK_IN2", + "HCLK_LV7", + "HCLK_WL1END3", + "HCLK_CK_IN4", + "HCLK_NE6B1", + "HCLK_NL1BEG1", + "HCLK_SW6E0", + "HCLK_NW2A1", + "HCLK_LVB9", + "HCLK_CK_BUFHCLK5", + "HCLK_NW6C3", + "HCLK_LVB10", + "HCLK_NE2BEG3", + "HCLK_NE6D1", + "HCLK_SW6C0", + "HCLK_SE2A2", + "HCLK_CK_IN8", + "HCLK_NN6C2", + "HCLK_CK_IN1", + "HCLK_NW6D2", + "HCLK_REFCK_EASTCLK0", + "HCLK_NN2BEG1", + "HCLK_LV11", + "HCLK_NE6C1", + "HCLK_SS6D3", + "HCLK_CK_INOUT_L4", + "HCLK_BYP_BOUNCE6", + "HCLK_NR1BEG3", + "HCLK_NW6B3", + "HCLK_LV3", + "HCLK_CK_OUTIN_L0", + "HCLK_CK_OUTIN_L2", + "HCLK_SW6E3", + "HCLK_WW4END_S0_0", + "HCLK_CCIO2", + "HCLK_SE2A1", + "HCLK_SL1END3", + "HCLK_LEAF_CLK_B_TOPL2", + "HCLK_NW6B2", + "HCLK_WW2END3", + "HCLK_SS6C0", + "HCLK_CK_INOUT_L3", + "HCLK_LV14", + "HCLK_NE6C3", + "HCLK_LV2", + "HCLK_NN6E1", + "HCLK_NE6D3", + "HCLK_CK_IN9", + "HCLK_SE6C3", + "HCLK_CK_BUFHCLK2", + "HCLK_CK_BUFRCLK3", + "HCLK_FAN_BOUNCE_S3_4", + "HCLK_SR1END_N3_3", + "HCLK_SE2A3", + "HCLK_SW6B2", + "HCLK_NN6A2", + "HCLK_LVB1", + "HCLK_REFCK_WESTCLK0", + "HCLK_SE6E1", + "HCLK_CK_INOUT_L0", + "HCLK_SW2END0", + "HCLK_NW6C1", + "HCLK_ER1BEG_S0", + "HCLK_CK_INOUT_L5", + "HCLK_NN6B1", + "HCLK_EL1END_S3_0" + ], + "tile_type": "HCLK_L", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_L_BOT_UTURN.json b/artix7/tile_type_HCLK_L_BOT_UTURN.json index e49be2c..7f1a75d 100644 --- a/artix7/tile_type_HCLK_L_BOT_UTURN.json +++ b/artix7/tile_type_HCLK_L_BOT_UTURN.json @@ -1,908 +1,908 @@ { - "wires": [ - "B_TERM_UTURN_INT_WR1BEG0", - "B_TERM_UTURN_INT_LV_L6", - "B_TERM_UTURN_INT_ER1END_N3_3", - "B_TERM_UTURN_INT_SW6A2", - "HCLK_CK_IN12", - "B_TERM_UTURN_INT_LV4", - "B_TERM_UTURN_INT_SS2A1", - "B_TERM_UTURN_INT_LV3", - "HCLK_CK_IN1", - "B_TERM_UTURN_INT_SS6D3", - "HCLK_CK_BUFHCLK1", - "HCLK_LEAF_CLK_B_TOPL3", - "HCLK_CK_OUTIN_L3", - "B_TERM_UTURN_INT_LV_L3", - "B_TERM_UTURN_INT_LV2", - "B_TERM_UTURN_INT_SS6B3", - "B_TERM_UTURN_INT_LV_L4", - "HCLK_CK_BUFHCLK3", - "B_TERM_UTURN_INT_SW6B3", - "B_TERM_UTURN_INT_SS6C1", - "HCLK_CK_BUFHCLK0", - "B_TERM_UTURN_INT_SS6A3", - "B_TERM_UTURN_INT_SS6D1", - "B_TERM_UTURN_INT_ER1BEG0", - "B_TERM_UTURN_INT_SW6D2", - "HCLK_LEAF_CLK_B_TOPL1", - "B_TERM_UTURN_INT_LVB_L5", - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK4", - "B_TERM_UTURN_INT_SW6D3", - "HCLK_INT_PERFCLK3", - "B_TERM_UTURN_INT_SE6D0", - "B_TERM_UTURN_INT_SL1BEG1", - "HCLK_CK_OUTIN_L5", - "HCLK_CK_OUTIN_L0", - "B_TERM_UTURN_INT_SE2BEG2", - "B_TERM_UTURN_INT_SS6B0", - "B_TERM_UTURN_INT_SW6A3", - "HCLK_CK_IN13", - "B_TERM_UTURN_INT_SS6C3", - "B_TERM_UTURN_INT_LV_L5", - "B_TERM_UTURN_INT_LV_L18", - "B_TERM_UTURN_INT_SE6A1", - "HCLK_CK_OUTIN_L6", - "B_TERM_UTURN_INT_SS6A0", - "B_TERM_UTURN_INT_SW6C0", - "B_TERM_UTURN_INT_SS6C0", - "HCLK_LEAF_CLK_B_TOPL2", - "B_TERM_UTURN_INT_SW6B1", - "B_TERM_UTURN_INT_SS6B1", - "B_TERM_UTURN_INT_SW6D1", - "B_TERM_UTURN_INT_SS6E0", - "B_TERM_UTURN_INT_SS6BEG0", - "B_TERM_UTURN_INT_SW6A1", - "B_TERM_UTURN_INT_FAN_BOUNCE0", - "HCLK_CK_INOUT_L1", - "B_TERM_UTURN_INT_SS2A0", - "HCLK_CK_BUFHCLK10", - "HCLK_CK_INOUT_L2", - "B_TERM_UTURN_INT_SW2BEG0", - "B_TERM_UTURN_INT_SW6C3", - "B_TERM_UTURN_INT_LV_L8", - "B_TERM_UTURN_INT_SE6B1", - "B_TERM_UTURN_INT_SS2BEG3", - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "B_TERM_UTURN_INT_SE6D2", - "B_TERM_UTURN_INT_SE2BEG0", - "B_TERM_UTURN_INT_SS6C2", - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "HCLK_CK_OUTIN_L4", - "B_TERM_UTURN_INT_SW6B2", - "B_TERM_UTURN_INT_WR1END0", - "B_TERM_UTURN_INT_SS6B2", - "B_TERM_UTURN_INT_SE6C0", - "HCLK_CK_BUFHCLK8", - "HCLK_CK_OUTIN_L7", - "HCLK_CK_INOUT_L3", - "B_TERM_UTURN_INT_SE6B3", - "B_TERM_UTURN_INT_SE6A0", - "B_TERM_UTURN_INT_SW2BEG3", - "B_TERM_UTURN_INT_LV8", - "HCLK_CK_INOUT_L6", - "B_TERM_UTURN_INT_SS6BEG2", - "B_TERM_UTURN_INT_SS6E3", - "B_TERM_UTURN_INT_SW2BEG1", - "B_TERM_UTURN_INT_SS6E1", - "B_TERM_UTURN_INT_SL1BEG2", - "HCLK_CCIO2", - "HCLK_CK_BUFHCLK6", - "B_TERM_UTURN_INT_SS6BEG3", - "B_TERM_UTURN_INT_SS6BEG1", - "B_TERM_UTURN_INT_SE2BEG1", - "B_TERM_UTURN_INT_SS2A2", - "B_TERM_UTURN_INT_SS6E2", - "B_TERM_UTURN_INT_LV_L9", - "B_TERM_UTURN_INT_SW6A0", - "B_TERM_UTURN_INT_SW6END_N0_3", - "HCLK_CK_IN8", - "B_TERM_UTURN_INT_SE6A3", - "B_TERM_UTURN_INT_SE6B2", - "B_TERM_UTURN_INT_SE6D1", - "B_TERM_UTURN_INT_SW6B0", - "HCLK_CK_INOUT_L7", - "HCLK_CK_IN6", - "HCLK_LEAF_CLK_B_TOPL4", - "B_TERM_UTURN_INT_SR1BEG2", - "B_TERM_UTURN_INT_SE6A2", - "HCLK_CK_IN5", - "B_TERM_UTURN_INT_LV7", - "B_TERM_UTURN_INT_SW6C2", - "HCLK_CK_IN0", - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "B_TERM_UTURN_INT_LVB_L4", - "B_TERM_UTURN_INT_SS2BEG1", - "HCLK_CK_BUFRCLK3", - "HCLK_INT_PERFCLK0", - "B_TERM_UTURN_INT_LVB_L3", - "B_TERM_UTURN_INT_SE6D3", - "B_TERM_UTURN_INT_LV9", - "HCLK_CCIO3", - "B_TERM_UTURN_INT_LV_L7", - "HCLK_CK_BUFHCLK7", - "HCLK_CK_IN2", - "HCLK_INT_PERFCLK1", - "B_TERM_UTURN_INT_SE6C3", - "HCLK_LEAF_CLK_B_TOPL5", - "HCLK_CK_BUFHCLK2", - "B_TERM_UTURN_INT_SW6C1", - "HCLK_CK_IN9", - "B_TERM_UTURN_INT_SE2BEG3", - "HCLK_CK_OUTIN_L2", - "B_TERM_UTURN_INT_SS6A1", - "B_TERM_UTURN_INT_LV_L2", - "B_TERM_UTURN_INT_LVB_L0", - "HCLK_CCIO0", - "B_TERM_UTURN_INT_SS2BEG2", - "B_TERM_UTURN_INT_SR1BEG1", - "HCLK_CK_IN11", - "B_TERM_UTURN_INT_SE6B0", - "B_TERM_UTURN_INT_LVB_L1", - "B_TERM_UTURN_INT_SS6D0", - "HCLK_CK_OUTIN_L1", - "HCLK_CK_BUFHCLK5", - "B_TERM_UTURN_INT_SS2BEG0", - "HCLK_INT_PERFCLK2", - "HCLK_CK_IN10", - "HCLK_CCIO1", - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK1", - "B_TERM_UTURN_INT_SE6C1", - "B_TERM_UTURN_INT_SS6D2", - "B_TERM_UTURN_INT_SW6D0", - "HCLK_LEAF_CLK_B_TOPL0", - "HCLK_CK_IN7", - "B_TERM_UTURN_INT_SL1BEG0", - "B_TERM_UTURN_INT_LV6", - "HCLK_CK_IN4", - "B_TERM_UTURN_INT_LV18", - "B_TERM_UTURN_INT_LV5", - "HCLK_CK_INOUT_L5", - "HCLK_CK_BUFRCLK0", - "B_TERM_UTURN_INT_SR1BEG3", - "B_TERM_UTURN_INT_LVB_L2", - "B_TERM_UTURN_INT_SL1BEG3", - "HCLK_CK_INOUT_L0", - "B_TERM_UTURN_INT_SW2BEG2", - "HCLK_CK_INOUT_L4", - "HCLK_CK_IN3", - "B_TERM_UTURN_INT_SS6A2", - "B_TERM_UTURN_INT_SS2A3", - "HCLK_CK_BUFHCLK9", - "B_TERM_UTURN_INT_SE6C2" - ], - "sites": [], "pips": { - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_CK_INOUT_L3": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_CK_INOUT_L0": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_CK_INOUT_L1": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_CK_INOUT_L7": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L7", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_CK_INOUT_L5": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_CK_INOUT_L6": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L6", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L7", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_CK_INOUT_L4": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L4", "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL0": { + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "src_wire": "HCLK_CK_BUFHCLK8", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_CK_INOUT_L3": { + "can_invert": "0", "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL3": { + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", + "src_wire": "HCLK_CK_BUFRCLK0", "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" }, "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", - "is_directional": "1", "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL4": { + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", + "src_wire": "HCLK_CK_OUTIN_L6", "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL0": { + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "src_wire": "HCLK_CK_OUTIN_L7", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL2": { + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "src_wire": "HCLK_CK_BUFHCLK9", "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", "src_wire": "HCLK_CK_BUFRCLK2", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" }, "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL1": { + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", + "src_wire": "HCLK_CK_OUTIN_L3", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL4": { + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L5", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", "src_wire": "HCLK_CK_OUTIN_L0", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK11", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL0": { + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", + "src_wire": "HCLK_CK_BUFRCLK2", "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL2": { + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_CK_INOUT_L6": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "src_wire": "HCLK_CK_BUFRCLK2", "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_L1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L6" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" }, "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", - "is_directional": "1", "src_wire": "HCLK_CK_OUTIN_L6", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_CK_INOUT_L5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", "src_wire": "HCLK_CK_OUTIN_L4", - "is_pseudo": "0" - }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" }, - "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL2": { + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", + "src_wire": "HCLK_CK_OUTIN_L3", "is_directional": "1", - "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_CK_INOUT_L2": { "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_L2", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK10", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_CK_INOUT_L4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", - "is_directional": "1", "src_wire": "HCLK_CK_BUFRCLK3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_CK_INOUT_L7": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L7" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_CK_INOUT_L1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_CK_INOUT_L0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_L0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL1" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL2" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL4" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL3" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL5" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFRCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" + }, + "HCLK_L_BOT_UTURN.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_L0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOPL0" } }, - "tile_type": "HCLK_L_BOT_UTURN" + "wires": [ + "B_TERM_UTURN_INT_SW6C0", + "B_TERM_UTURN_INT_LVB_L0", + "B_TERM_UTURN_INT_SE6D3", + "B_TERM_UTURN_INT_LV4", + "B_TERM_UTURN_INT_SS2BEG3", + "HCLK_INT_PERFCLK1", + "B_TERM_UTURN_INT_SE2BEG0", + "B_TERM_UTURN_INT_SS6B1", + "B_TERM_UTURN_INT_LV_L5", + "B_TERM_UTURN_INT_SE6D1", + "HCLK_CK_IN3", + "B_TERM_UTURN_INT_LV2", + "B_TERM_UTURN_INT_LVB_L2", + "HCLK_CK_OUTIN_L6", + "B_TERM_UTURN_INT_SS6BEG3", + "B_TERM_UTURN_INT_SL1BEG1", + "B_TERM_UTURN_INT_SL1BEG2", + "HCLK_LEAF_CLK_B_TOPL0", + "HCLK_CCIO0", + "B_TERM_UTURN_INT_SS6BEG1", + "HCLK_CK_INOUT_L2", + "HCLK_CK_OUTIN_L5", + "HCLK_INT_PERFCLK0", + "B_TERM_UTURN_INT_SE6A2", + "B_TERM_UTURN_INT_SS6D3", + "HCLK_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK3", + "HCLK_CCIO3", + "B_TERM_UTURN_INT_SS6BEG0", + "B_TERM_UTURN_INT_LV9", + "HCLK_LEAF_CLK_B_TOPL5", + "B_TERM_UTURN_INT_SE2BEG2", + "B_TERM_UTURN_INT_LV_L2", + "B_TERM_UTURN_INT_SE6B2", + "B_TERM_UTURN_INT_LVB_L3", + "B_TERM_UTURN_INT_LV7", + "B_TERM_UTURN_INT_SS6D2", + "B_TERM_UTURN_INT_LVB_L4", + "B_TERM_UTURN_INT_SW6C2", + "HCLK_CK_IN13", + "B_TERM_UTURN_INT_SS6B3", + "B_TERM_UTURN_INT_SS2A1", + "HCLK_CK_INOUT_L6", + "HCLK_CK_IN6", + "HCLK_LEAF_CLK_B_TOPL1", + "B_TERM_UTURN_INT_SE2BEG1", + "HCLK_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK8", + "B_TERM_UTURN_INT_SS6A2", + "HCLK_CK_IN5", + "HCLK_CK_IN0", + "B_TERM_UTURN_INT_SE6A0", + "HCLK_INT_PERFCLK3", + "HCLK_CK_BUFHCLK1", + "B_TERM_UTURN_INT_LV6", + "B_TERM_UTURN_INT_LV_L6", + "HCLK_CK_BUFHCLK10", + "B_TERM_UTURN_INT_SS2A2", + "B_TERM_UTURN_INT_WR1BEG0", + "B_TERM_UTURN_INT_SE6B0", + "B_TERM_UTURN_INT_SL1BEG0", + "B_TERM_UTURN_INT_SW6A3", + "HCLK_CK_BUFHCLK11", + "B_TERM_UTURN_INT_LVB_L1", + "B_TERM_UTURN_INT_SE6C0", + "HCLK_INT_PERFCLK2", + "B_TERM_UTURN_INT_LV_L9", + "B_TERM_UTURN_INT_SW6B2", + "HCLK_CK_INOUT_L7", + "B_TERM_UTURN_INT_SW2BEG0", + "B_TERM_UTURN_INT_SW6A1", + "B_TERM_UTURN_INT_SE6D2", + "B_TERM_UTURN_INT_LV_L3", + "B_TERM_UTURN_INT_SR1BEG3", + "HCLK_CCIO1", + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "B_TERM_UTURN_INT_SW6END_N0_3", + "B_TERM_UTURN_INT_SE6B1", + "B_TERM_UTURN_INT_LV5", + "B_TERM_UTURN_INT_SR1BEG2", + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "HCLK_CK_BUFRCLK2", + "B_TERM_UTURN_INT_SW6A2", + "B_TERM_UTURN_INT_SS2BEG2", + "HCLK_CK_BUFHCLK0", + "HCLK_CK_IN2", + "HCLK_CK_OUTIN_L7", + "B_TERM_UTURN_INT_SS6D0", + "HCLK_CK_IN4", + "B_TERM_UTURN_INT_SE6A1", + "B_TERM_UTURN_INT_SS6A0", + "B_TERM_UTURN_INT_SS2BEG1", + "B_TERM_UTURN_INT_SE6C3", + "HCLK_CK_BUFHCLK5", + "B_TERM_UTURN_INT_SS6C2", + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "B_TERM_UTURN_INT_SS6A3", + "B_TERM_UTURN_INT_SW6D2", + "HCLK_CK_OUTIN_L3", + "HCLK_CK_IN8", + "B_TERM_UTURN_INT_SS6E3", + "HCLK_CK_BUFHCLK7", + "B_TERM_UTURN_INT_SW2BEG2", + "HCLK_CK_IN1", + "B_TERM_UTURN_INT_LV_L8", + "HCLK_LEAF_CLK_B_TOPL3", + "B_TERM_UTURN_INT_SW2BEG1", + "B_TERM_UTURN_INT_SW6B1", + "B_TERM_UTURN_INT_SW6B3", + "B_TERM_UTURN_INT_SR1BEG1", + "B_TERM_UTURN_INT_SE6C2", + "B_TERM_UTURN_INT_SS2BEG0", + "B_TERM_UTURN_INT_SW2BEG3", + "HCLK_CK_BUFRCLK0", + "B_TERM_UTURN_INT_WR1END0", + "B_TERM_UTURN_INT_LV_L7", + "B_TERM_UTURN_INT_SW6D1", + "B_TERM_UTURN_INT_LVB_L5", + "HCLK_CK_BUFRCLK1", + "B_TERM_UTURN_INT_SE6C1", + "B_TERM_UTURN_INT_LV18", + "B_TERM_UTURN_INT_SW6D3", + "B_TERM_UTURN_INT_SL1BEG3", + "HCLK_CK_INOUT_L4", + "B_TERM_UTURN_INT_SS6E1", + "B_TERM_UTURN_INT_SW6C3", + "HCLK_CK_BUFHCLK6", + "HCLK_LEAF_CLK_B_TOPL4", + "B_TERM_UTURN_INT_SS6E0", + "HCLK_CK_OUTIN_L0", + "HCLK_CK_OUTIN_L2", + "B_TERM_UTURN_INT_SS2A3", + "B_TERM_UTURN_INT_ER1BEG0", + "HCLK_CK_OUTIN_L4", + "HCLK_CK_IN11", + "B_TERM_UTURN_INT_ER1END_N3_3", + "HCLK_CK_IN10", + "HCLK_CCIO2", + "B_TERM_UTURN_INT_SE6B3", + "B_TERM_UTURN_INT_SS6B2", + "HCLK_CK_IN7", + "HCLK_LEAF_CLK_B_TOPL2", + "B_TERM_UTURN_INT_SW6B0", + "B_TERM_UTURN_INT_SW6A0", + "HCLK_CK_INOUT_L3", + "B_TERM_UTURN_INT_LV3", + "B_TERM_UTURN_INT_SS6C3", + "B_TERM_UTURN_INT_SE6A3", + "B_TERM_UTURN_INT_LV8", + "HCLK_CK_IN9", + "HCLK_CK_OUTIN_L1", + "HCLK_CK_BUFHCLK2", + "B_TERM_UTURN_INT_SS6C1", + "B_TERM_UTURN_INT_SS6B0", + "B_TERM_UTURN_INT_SS6C0", + "HCLK_CK_BUFRCLK3", + "B_TERM_UTURN_INT_SW6C1", + "B_TERM_UTURN_INT_SS6D1", + "B_TERM_UTURN_INT_LV_L4", + "B_TERM_UTURN_INT_SS2A0", + "B_TERM_UTURN_INT_SS6A1", + "B_TERM_UTURN_INT_SS6BEG2", + "B_TERM_UTURN_INT_SS6E2", + "B_TERM_UTURN_INT_SW6D0", + "B_TERM_UTURN_INT_SE6D0", + "B_TERM_UTURN_INT_LV_L18", + "HCLK_CK_INOUT_L0", + "HCLK_CK_INOUT_L1", + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "B_TERM_UTURN_INT_SE2BEG3", + "HCLK_CK_INOUT_L5", + "HCLK_CK_IN12" + ], + "tile_type": "HCLK_L_BOT_UTURN", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_R.json b/artix7/tile_type_HCLK_R.json index fd179fe..e30c4d3 100644 --- a/artix7/tile_type_HCLK_R.json +++ b/artix7/tile_type_HCLK_R.json @@ -1,1695 +1,1695 @@ { - "wires": [ - "HCLK_CK_INOUT_R5", - "HCLK_CK_IN12", - "HCLK_SS6E3", - "HCLK_LVB12", - "HCLK_LVB9", - "HCLK_SS2A3", - "HCLK_SE2A0", - "HCLK_FAN_BOUNCE_S3_0", - "HCLK_NL1BEG1", - "HCLK_NE6C0", - "HCLK_NE2BEG3", - "HCLK_NR1BEG1", - "HCLK_SS6C1", - "HCLK_REFCK_WESTCLK0", - "HCLK_NN6BEG2", - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK4", - "HCLK_NW6C1", - "HCLK_INT_PERFCLK3", - "HCLK_LV1", - "HCLK_NN6D3", - "HCLK_SE2A3", - "HCLK_SW2END1", - "HCLK_FAN_BOUNCE_S3_2", - "HCLK_CK_IN13", - "HCLK_WR1END_S1_0", - "HCLK_NN6BEG0", - "HCLK_WL1BEG3", - "HCLK_NN6D0", - "HCLK_SL1END3", - "HCLK_NN6BEG1", - "HCLK_LEAF_CLK_B_TOP5", - "HCLK_REFCK_WESTCLK1", - "HCLK_LEAF_CLK_B_BOT0", - "HCLK_NE2END_S3_0", - "HCLK_SR1END_N3_3", - "HCLK_CK_INOUT_R2", - "HCLK_NW6A1", - "HCLK_CK_BUFHCLK10", - "HCLK_SW6E1", - "HCLK_SE6C1", - "HCLK_NR1BEG0", - "HCLK_SW6END3", - "HCLK_SS6C3", - "HCLK_LEAF_CLK_B_BOT5", - "HCLK_SW2END_N0_3", - "HCLK_SR1BEG3", - "HCLK_NW2A0", - "HCLK_CK_INOUT_R0", - "HCLK_SS6A2", - "HCLK_NN6B0", - "HCLK_LVB10", - "HCLK_FAN_BOUNCE_S3_4", - "HCLK_NN6B2", - "HCLK_SS6A1", - "HCLK_WW4END_S0_0", - "HCLK_CK_OUTIN_R2", - "HCLK_LV5", - "HCLK_NE6D3", - "HCLK_NE6A3", - "HCLK_NE6D0", - "HCLK_NN2BEG0", - "HCLK_NN6E0", - "HCLK_WR1BEG_S0", - "HCLK_NN6E1", - "HCLK_NW6C2", - "HCLK_NN2A0", - "HCLK_SS2END2", - "HCLK_NW6D1", - "HCLK_CK_IN6", - "HCLK_NW6B1", - "HCLK_SL1END1", - "HCLK_REFCK_EASTCLK1", - "HCLK_LV0", - "HCLK_SW6B0", - "HCLK_CK_IN5", - "HCLK_LVB7", - "HCLK_CK_OUTIN_R1", - "HCLK_NW6D0", - "HCLK_SE6E0", - "HCLK_WW2END3", - "HCLK_SW6D2", - "HCLK_SW6E2", - "HCLK_SW2END2", - "HCLK_NN6E2", - "HCLK_LV4", - "HCLK_LV10", - "HCLK_BYP_BOUNCE7", - "HCLK_NN2A1", - "HCLK_LV12", - "HCLK_SS2A1", - "HCLK_INT_PERFCLK1", - "HCLK_SW6B2", - "HCLK_SE6D2", - "HCLK_CK_IN9", - "HCLK_CK_OUTIN_R3", - "HCLK_BYP_BOUNCE6", - "HCLK_NL1END_S3_0", - "HCLK_CCIO0", - "HCLK_NW6B0", - "HCLK_SR1END2", - "HCLK_LVB6", - "HCLK_NE6B0", - "HCLK_LV14", - "HCLK_SW6D0", - "HCLK_SS6END1", - "HCLK_CK_BUFHCLK5", - "HCLK_SE6D0", - "HCLK_SS6E1", - "HCLK_SE6B0", - "HCLK_SE6D3", - "HCLK_LV15", - "HCLK_LEAF_CLK_B_BOT2", - "HCLK_CK_IN7", - "HCLK_CK_IN4", - "HCLK_CK_INOUT_R3", - "HCLK_SW6E3", - "HCLK_NN6C1", - "HCLK_SS6C2", - "HCLK_LV2", - "HCLK_LEAF_CLK_B_TOP1", - "HCLK_SS6D0", - "HCLK_NN6BEG3", - "HCLK_LEAF_CLK_B_TOP3", - "HCLK_SE6C2", - "HCLK_SE6B2", - "HCLK_SW6C2", - "HCLK_SS6A0", - "HCLK_CK_IN3", - "HCLK_SS6B3", - "HCLK_LEAF_CLK_B_TOP2", - "HCLK_LEAF_CLK_B_BOT4", - "HCLK_LVB1", - "HCLK_SS6D1", - "HCLK_NW6D2", - "HCLK_REFCK_EASTCLK0", - "HCLK_NR1BEG2", - "HCLK_NL1BEG0", - "HCLK_SE6E2", - "HCLK_NE2BEG0", - "HCLK_NW6A2", - "HCLK_NN2BEG1", - "HCLK_NW6A3", - "HCLK_NE6B3", - "HCLK_CK_IN1", - "HCLK_SS6END_N0_3", - "HCLK_NN6A1", - "HCLK_NE2BEG1", - "HCLK_NN2BEG2", - "HCLK_SW6C1", - "HCLK_LEAF_CLK_B_TOP4", - "HCLK_NW2A1", - "HCLK_SS6A3", - "HCLK_CK_BUFHCLK1", - "HCLK_LV16", - "HCLK_NN6A3", - "HCLK_CK_OUTIN_R0", - "HCLK_CK_BUFHCLK3", - "HCLK_CK_OUTIN_R6", - "HCLK_SS2BEG3", - "HCLK_CK_BUFHCLK0", - "HCLK_BYP_BOUNCE3", - "HCLK_LV6", - "HCLK_SW6C3", - "HCLK_CK_INOUT_R1", - "HCLK_SS6D3", - "HCLK_NE6D1", - "HCLK_LVB4", - "HCLK_SS2END0", - "HCLK_NN6C0", - "HCLK_CK_OUTIN_R4", - "HCLK_NE6C3", - "HCLK_CK_INOUT_R4", - "HCLK_SE6E1", - "HCLK_SW6C0", - "HCLK_NW2END_S0_0", - "HCLK_NW6END_S0_0", - "HCLK_LV7", - "HCLK_NN6B1", - "HCLK_NE6D2", - "HCLK_SS6END2", - "HCLK_NE6A1", - "HCLK_SW6E0", - "HCLK_LEAF_CLK_B_BOT1", - "HCLK_SW2END0", - "HCLK_ER1END3", - "HCLK_SW6B1", - "HCLK_NN2END_S2_0", - "HCLK_LV3", - "HCLK_SE6C3", - "HCLK_NE6A2", - "HCLK_SW6D1", - "HCLK_NW2A3", - "HCLK_NN6C2", - "HCLK_NE6C1", - "HCLK_NR1BEG3", - "HCLK_NN6C3", - "HCLK_NE6B2", - "HCLK_CK_BUFHCLK8", - "HCLK_EL1END_S3_0", - "HCLK_NN6A0", - "HCLK_NW6B2", - "HCLK_SS2END1", - "HCLK_SW2A3", - "HCLK_SS6D2", - "HCLK_SS2END_N0_3", - "HCLK_NW6C3", - "HCLK_CCIO2", - "HCLK_NE2BEG2", - "HCLK_CK_BUFHCLK6", - "HCLK_NN2BEG3", - "HCLK_NN6A2", - "HCLK_SS6E0", - "HCLK_SE6B1", - "HCLK_SE2A1", - "HCLK_NW6C0", - "HCLK_NL1BEG2", - "HCLK_CK_IN8", - "HCLK_WL1END3", - "HCLK_LV9", - "HCLK_CK_OUTIN_R7", - "HCLK_LVB8", - "HCLK_BYP_BOUNCE2", - "HCLK_SS6B1", - "HCLK_SE6B3", - "HCLK_SS6B2", - "HCLK_SS2A2", - "HCLK_NW6B3", - "HCLK_NW2A2", - "HCLK_SS2A0", - "HCLK_SE2A2", - "HCLK_SE6E3", - "HCLK_LEAF_CLK_B_BOT3", - "HCLK_SW6B3", - "HCLK_CK_IN0", - "HCLK_LVB11", - "HCLK_INT_PERFCLK0", - "HCLK_CK_BUFRCLK3", - "HCLK_NN6D1", - "HCLK_NN2A2", - "HCLK_CK_INOUT_R7", - "HCLK_CCIO3", - "HCLK_NW6D3", - "HCLK_LVB3", - "HCLK_SS6E2", - "HCLK_CK_BUFHCLK7", - "HCLK_CK_IN2", - "HCLK_CK_BUFHCLK2", - "HCLK_SS6END3", - "HCLK_NE6A0", - "HCLK_SE6D1", - "HCLK_NE6C2", - "HCLK_NN2A3", - "HCLK_SE6C0", - "HCLK_EL1BEG3", - "HCLK_CK_IN11", - "HCLK_ER1BEG_S0", - "HCLK_LV8", - "HCLK_NN6B3", - "HCLK_LVB5", - "HCLK_SL1END0", - "HCLK_CK_INOUT_R6", - "HCLK_INT_PERFCLK2", - "HCLK_CK_IN10", - "HCLK_CCIO1", - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK1", - "HCLK_FAN_BOUNCE_S3_6", - "HCLK_LV17", - "HCLK_SS6B0", - "HCLK_LVB2", - "HCLK_NN6END_S1_0", - "HCLK_SS6END0", - "HCLK_NN6E3", - "HCLK_SW6D3", - "HCLK_CK_BUFRCLK0", - "HCLK_LV13", - "HCLK_NE6B1", - "HCLK_SS6C0", - "HCLK_LV11", - "HCLK_NW6A0", - "HCLK_LEAF_CLK_B_TOP0", - "HCLK_CK_OUTIN_R5", - "HCLK_SR1END1", - "HCLK_SL1END2", - "HCLK_CK_BUFHCLK9", - "HCLK_NN6D2" - ], - "sites": [], "pips": { - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP3": { "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" }, "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_CK_INOUT_R6": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R6", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_CK_INOUT_R4": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" }, "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT4": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT2": { "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_CK_INOUT_R0": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_CK_INOUT_R2": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_CK_INOUT_R1": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_CK_INOUT_R5": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_CK_INOUT_R7": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R7", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_CK_INOUT_R3": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" }, "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_CK_INOUT_R7": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R7" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_CK_INOUT_R2": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R2" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_CK_INOUT_R3": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R3" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_CK_INOUT_R0": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R0" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_CK_INOUT_R1": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R1" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" }, "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_BOT4", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_CK_INOUT_R4": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R4" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT2": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT2" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_BOT0": { + "src_wire": "HCLK_CK_OUTIN_R1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT0" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_OUTIN_R4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT3": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT3" + }, + "HCLK_R.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP0": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_CK_INOUT_R5": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R5" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_BUFHCLK7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK6->>HCLK_CK_INOUT_R6": { + "src_wire": "HCLK_CK_BUFHCLK6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R6" + }, + "HCLK_R.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP3": { + "src_wire": "HCLK_CK_OUTIN_R3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_BOT4": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT4" + }, + "HCLK_R.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP5": { + "src_wire": "HCLK_CK_BUFHCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_BOT1": { + "src_wire": "HCLK_CK_OUTIN_R0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT1" + }, + "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_OUTIN_R5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT5": { + "src_wire": "HCLK_CK_OUTIN_R6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_BOT5" + }, + "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP4": { + "src_wire": "HCLK_CK_BUFHCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP1": { + "src_wire": "HCLK_CK_BUFHCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP2": { + "src_wire": "HCLK_CK_BUFHCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" } }, - "tile_type": "HCLK_R" + "wires": [ + "HCLK_SE6D1", + "HCLK_LV10", + "HCLK_NE6B2", + "HCLK_SS2END_N0_3", + "HCLK_INT_PERFCLK1", + "HCLK_NN2A0", + "HCLK_CK_INOUT_R2", + "HCLK_SS2A0", + "HCLK_NW6A0", + "HCLK_LEAF_CLK_B_BOT2", + "HCLK_SE6B0", + "HCLK_NW2A2", + "HCLK_CK_IN3", + "HCLK_SW6E1", + "HCLK_SS2END2", + "HCLK_BYP_BOUNCE7", + "HCLK_NN2A3", + "HCLK_NE2END_S3_0", + "HCLK_SW6C3", + "HCLK_SS6B1", + "HCLK_SS2END1", + "HCLK_SW6D0", + "HCLK_NE6B3", + "HCLK_CK_INOUT_R4", + "HCLK_NN2A2", + "HCLK_INT_PERFCLK0", + "HCLK_CK_BUFHCLK3", + "HCLK_CCIO3", + "HCLK_NE6A3", + "HCLK_NE6B0", + "HCLK_SE6C0", + "HCLK_SL1END1", + "HCLK_NN6B3", + "HCLK_NE2BEG1", + "HCLK_SE6B3", + "HCLK_LEAF_CLK_B_TOP2", + "HCLK_SW6D3", + "HCLK_NL1BEG0", + "HCLK_NN6BEG3", + "HCLK_SW2END1", + "HCLK_SW6C1", + "HCLK_FAN_BOUNCE_S3_6", + "HCLK_NW6D1", + "HCLK_CK_IN13", + "HCLK_SS6END0", + "HCLK_SW6E2", + "HCLK_LV16", + "HCLK_LVB4", + "HCLK_NE6A0", + "HCLK_CK_OUTIN_R4", + "HCLK_CK_BUFHCLK4", + "HCLK_NR1BEG0", + "HCLK_CK_BUFHCLK8", + "HCLK_LV9", + "HCLK_SE6D3", + "HCLK_LV8", + "HCLK_EL1BEG3", + "HCLK_NN6BEG1", + "HCLK_NE6A1", + "HCLK_CK_IN0", + "HCLK_CK_IN5", + "HCLK_CK_INOUT_R5", + "HCLK_NN6D1", + "HCLK_NN2A1", + "HCLK_LEAF_CLK_B_BOT0", + "HCLK_NW6B0", + "HCLK_INT_PERFCLK2", + "HCLK_SS6D0", + "HCLK_NN6B2", + "HCLK_WR1BEG_S0", + "HCLK_SW6C2", + "HCLK_SE2A0", + "HCLK_NW2A0", + "HCLK_SW2END2", + "HCLK_LV12", + "HCLK_CK_BUFRCLK2", + "HCLK_SW6B3", + "HCLK_CK_BUFHCLK0", + "HCLK_NW6A1", + "HCLK_SS6END_N0_3", + "HCLK_LV17", + "HCLK_LV6", + "HCLK_SS6A0", + "HCLK_LEAF_CLK_B_TOP1", + "HCLK_NW6D3", + "HCLK_ER1END3", + "HCLK_SW2A3", + "HCLK_NN6D0", + "HCLK_NN6A0", + "HCLK_NW6D0", + "HCLK_SW6D2", + "HCLK_NN2BEG2", + "HCLK_SS6E0", + "HCLK_NN6D3", + "HCLK_SS6END2", + "HCLK_CK_BUFHCLK7", + "HCLK_SS6D2", + "HCLK_LVB2", + "HCLK_SS6END3", + "HCLK_WL1BEG3", + "HCLK_CK_BUFRCLK0", + "HCLK_NE2BEG0", + "HCLK_CK_BUFRCLK1", + "HCLK_SE6D0", + "HCLK_SS6A2", + "HCLK_SL1END2", + "HCLK_CK_OUTIN_R1", + "HCLK_NN6A1", + "HCLK_CK_BUFHCLK6", + "HCLK_SS6D1", + "HCLK_NN2END_S2_0", + "HCLK_NN6C1", + "HCLK_CK_INOUT_R3", + "HCLK_NR1BEG1", + "HCLK_SE6B1", + "HCLK_REFCK_WESTCLK1", + "HCLK_CK_IN11", + "HCLK_WR1END_S1_0", + "HCLK_CK_IN10", + "HCLK_NN6BEG0", + "HCLK_CK_IN7", + "HCLK_SE6E0", + "HCLK_SS2BEG3", + "HCLK_LVB5", + "HCLK_CK_INOUT_R6", + "HCLK_LV13", + "HCLK_NN6B0", + "HCLK_SS6B3", + "HCLK_LV0", + "HCLK_SW6B1", + "HCLK_NN2BEG0", + "HCLK_LV1", + "HCLK_SR1END2", + "HCLK_LVB6", + "HCLK_CK_OUTIN_R2", + "HCLK_SL1END0", + "HCLK_SS6C1", + "HCLK_NW6A2", + "HCLK_LVB8", + "HCLK_NW6B1", + "HCLK_SW6END3", + "HCLK_LEAF_CLK_B_BOT5", + "HCLK_CK_INOUT_R0", + "HCLK_NE2BEG2", + "HCLK_CK_IN12", + "HCLK_SW6B0", + "HCLK_SS2A3", + "HCLK_NN6E0", + "HCLK_NN6A3", + "HCLK_SS6E2", + "HCLK_NW6C2", + "HCLK_LVB12", + "HCLK_SS2A1", + "HCLK_CK_OUTIN_R6", + "HCLK_LV15", + "HCLK_NL1BEG2", + "HCLK_NN6END_S1_0", + "HCLK_LV5", + "HCLK_NN6BEG2", + "HCLK_SW6D1", + "HCLK_CCIO0", + "HCLK_LV4", + "HCLK_SR1BEG3", + "HCLK_SS6E1", + "HCLK_CK_BUFHCLK9", + "HCLK_SE6E3", + "HCLK_NN6D2", + "HCLK_NW6C0", + "HCLK_LEAF_CLK_B_TOP0", + "HCLK_LVB3", + "HCLK_SS6E3", + "HCLK_SS6A3", + "HCLK_SE6D2", + "HCLK_CK_INOUT_R7", + "HCLK_SE6C1", + "HCLK_LEAF_CLK_B_TOP4", + "HCLK_SS6A1", + "HCLK_SS6B2", + "HCLK_SS2A2", + "HCLK_SW2END_N0_3", + "HCLK_NW2END_S0_0", + "HCLK_CK_IN6", + "HCLK_SS6END1", + "HCLK_NN6E3", + "HCLK_NW6A3", + "HCLK_SS6B0", + "HCLK_FAN_BOUNCE_S3_2", + "HCLK_REFCK_EASTCLK1", + "HCLK_NR1BEG2", + "HCLK_BYP_BOUNCE3", + "HCLK_INT_PERFCLK3", + "HCLK_SS6C3", + "HCLK_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK10", + "HCLK_CK_OUTIN_R7", + "HCLK_NN6E2", + "HCLK_LVB11", + "HCLK_NE6C0", + "HCLK_SS2END0", + "HCLK_CK_BUFHCLK11", + "HCLK_NN6C3", + "HCLK_SE6E2", + "HCLK_NE6D2", + "HCLK_SE6B2", + "HCLK_NN6C0", + "HCLK_CK_OUTIN_R3", + "HCLK_NE6A2", + "HCLK_BYP_BOUNCE2", + "HCLK_LVB7", + "HCLK_NW6END_S0_0", + "HCLK_NN2BEG3", + "HCLK_SR1END1", + "HCLK_SE6C2", + "HCLK_SS6C2", + "HCLK_NE6C2", + "HCLK_CCIO1", + "HCLK_NW2A3", + "HCLK_FAN_BOUNCE_S3_0", + "HCLK_CK_INOUT_R1", + "HCLK_NL1END_S3_0", + "HCLK_LEAF_CLK_B_TOP3", + "HCLK_NE6D0", + "HCLK_CK_IN2", + "HCLK_CK_OUTIN_R0", + "HCLK_LV7", + "HCLK_WL1END3", + "HCLK_CK_IN4", + "HCLK_NE6B1", + "HCLK_LEAF_CLK_B_BOT3", + "HCLK_NL1BEG1", + "HCLK_SW6E0", + "HCLK_NW2A1", + "HCLK_LVB9", + "HCLK_CK_BUFHCLK5", + "HCLK_NW6C3", + "HCLK_LVB10", + "HCLK_NE2BEG3", + "HCLK_NE6D1", + "HCLK_SW6C0", + "HCLK_SE2A2", + "HCLK_CK_IN8", + "HCLK_NN6C2", + "HCLK_CK_IN1", + "HCLK_NW6D2", + "HCLK_REFCK_EASTCLK0", + "HCLK_NN2BEG1", + "HCLK_LV11", + "HCLK_NE6C1", + "HCLK_SS6D3", + "HCLK_BYP_BOUNCE6", + "HCLK_NR1BEG3", + "HCLK_NW6B3", + "HCLK_LV3", + "HCLK_SW6E3", + "HCLK_LEAF_CLK_B_TOP5", + "HCLK_WW4END_S0_0", + "HCLK_CCIO2", + "HCLK_SE2A1", + "HCLK_SL1END3", + "HCLK_NW6B2", + "HCLK_WW2END3", + "HCLK_SS6C0", + "HCLK_LV14", + "HCLK_NE6C3", + "HCLK_LV2", + "HCLK_NN6E1", + "HCLK_NE6D3", + "HCLK_CK_IN9", + "HCLK_CK_BUFHCLK2", + "HCLK_SE6C3", + "HCLK_LEAF_CLK_B_BOT1", + "HCLK_LEAF_CLK_B_BOT4", + "HCLK_CK_BUFRCLK3", + "HCLK_FAN_BOUNCE_S3_4", + "HCLK_SR1END_N3_3", + "HCLK_SE2A3", + "HCLK_SW6B2", + "HCLK_NN6A2", + "HCLK_LVB1", + "HCLK_REFCK_WESTCLK0", + "HCLK_SE6E1", + "HCLK_SW2END0", + "HCLK_NW6C1", + "HCLK_ER1BEG_S0", + "HCLK_CK_OUTIN_R5", + "HCLK_NN6B1", + "HCLK_EL1END_S3_0" + ], + "tile_type": "HCLK_R", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_R_BOT_UTURN.json b/artix7/tile_type_HCLK_R_BOT_UTURN.json index faf93ba..c794b63 100644 --- a/artix7/tile_type_HCLK_R_BOT_UTURN.json +++ b/artix7/tile_type_HCLK_R_BOT_UTURN.json @@ -1,908 +1,908 @@ { - "wires": [ - "B_TERM_UTURN_INT_WR1BEG0", - "B_TERM_UTURN_INT_LV_L6", - "B_TERM_UTURN_INT_ER1END_N3_3", - "B_TERM_UTURN_INT_LVB4", - "HCLK_CK_INOUT_R5", - "B_TERM_UTURN_INT_SW6A2", - "HCLK_CK_IN12", - "B_TERM_UTURN_INT_LV4", - "B_TERM_UTURN_INT_SS2A1", - "B_TERM_UTURN_INT_LV3", - "HCLK_CK_IN1", - "HCLK_LEAF_CLK_B_TOP4", - "B_TERM_UTURN_INT_SS6D3", - "HCLK_CK_BUFHCLK1", - "B_TERM_UTURN_INT_LV_L3", - "B_TERM_UTURN_INT_LV2", - "B_TERM_UTURN_INT_SS6B3", - "HCLK_CK_OUTIN_R0", - "HCLK_CK_BUFHCLK3", - "HCLK_CK_OUTIN_R6", - "B_TERM_UTURN_INT_SW6B3", - "HCLK_CK_BUFHCLK0", - "B_TERM_UTURN_INT_LV_L4", - "B_TERM_UTURN_INT_SS6A3", - "B_TERM_UTURN_INT_SS6C1", - "B_TERM_UTURN_INT_SS6D1", - "B_TERM_UTURN_INT_ER1BEG0", - "B_TERM_UTURN_INT_SW6D2", - "HCLK_CK_INOUT_R1", - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK4", - "B_TERM_UTURN_INT_SW6D3", - "HCLK_INT_PERFCLK3", - "B_TERM_UTURN_INT_SE6D0", - "B_TERM_UTURN_INT_SL1BEG1", - "HCLK_CK_OUTIN_R4", - "B_TERM_UTURN_INT_SE2BEG2", - "B_TERM_UTURN_INT_SS6B0", - "B_TERM_UTURN_INT_SW6A3", - "HCLK_CK_IN13", - "B_TERM_UTURN_INT_LVB5", - "HCLK_CK_INOUT_R4", - "B_TERM_UTURN_INT_LV_L5", - "B_TERM_UTURN_INT_LV_L18", - "B_TERM_UTURN_INT_SE6A1", - "B_TERM_UTURN_INT_SS6C3", - "B_TERM_UTURN_INT_SS6A0", - "B_TERM_UTURN_INT_SW6C0", - "B_TERM_UTURN_INT_SS6C0", - "HCLK_LEAF_CLK_B_TOP5", - "B_TERM_UTURN_INT_SW6B1", - "B_TERM_UTURN_INT_SS6B1", - "B_TERM_UTURN_INT_SW6D1", - "B_TERM_UTURN_INT_SS6E0", - "B_TERM_UTURN_INT_LVB3", - "B_TERM_UTURN_INT_SS6BEG0", - "B_TERM_UTURN_INT_SW6A1", - "HCLK_CK_INOUT_R2", - "B_TERM_UTURN_INT_FAN_BOUNCE0", - "B_TERM_UTURN_INT_SS2A0", - "HCLK_CK_BUFHCLK10", - "B_TERM_UTURN_INT_LV_L8", - "B_TERM_UTURN_INT_SW2BEG0", - "B_TERM_UTURN_INT_SW6C3", - "B_TERM_UTURN_INT_SE6B1", - "B_TERM_UTURN_INT_SS2BEG3", - "B_TERM_UTURN_INT_SE6D2", - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "B_TERM_UTURN_INT_SE2BEG0", - "B_TERM_UTURN_INT_SS6C2", - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "B_TERM_UTURN_INT_SW6B2", - "B_TERM_UTURN_INT_WR1END0", - "B_TERM_UTURN_INT_SS6B2", - "B_TERM_UTURN_INT_SE6C0", - "HCLK_CK_BUFHCLK8", - "HCLK_CK_INOUT_R0", - "B_TERM_UTURN_INT_SE6B3", - "B_TERM_UTURN_INT_SE6A0", - "B_TERM_UTURN_INT_SW2BEG3", - "B_TERM_UTURN_INT_LV8", - "B_TERM_UTURN_INT_SS6BEG2", - "B_TERM_UTURN_INT_SS6E3", - "B_TERM_UTURN_INT_SW2BEG1", - "B_TERM_UTURN_INT_SS6E1", - "B_TERM_UTURN_INT_SL1BEG2", - "HCLK_CCIO2", - "HCLK_CK_BUFHCLK6", - "B_TERM_UTURN_INT_SS6BEG3", - "B_TERM_UTURN_INT_SS6BEG1", - "B_TERM_UTURN_INT_SE2BEG1", - "B_TERM_UTURN_INT_SS2A2", - "B_TERM_UTURN_INT_SS6E2", - "B_TERM_UTURN_INT_LV_L9", - "B_TERM_UTURN_INT_SW6A0", - "B_TERM_UTURN_INT_SW6END_N0_3", - "HCLK_CK_OUTIN_R2", - "HCLK_CK_IN8", - "B_TERM_UTURN_INT_SE6A3", - "B_TERM_UTURN_INT_SE6B2", - "B_TERM_UTURN_INT_SE6D1", - "HCLK_CK_OUTIN_R7", - "B_TERM_UTURN_INT_SW6B0", - "HCLK_CK_IN6", - "B_TERM_UTURN_INT_SR1BEG2", - "B_TERM_UTURN_INT_SE6A2", - "HCLK_CK_IN5", - "HCLK_CK_OUTIN_R1", - "B_TERM_UTURN_INT_LV7", - "B_TERM_UTURN_INT_SW6C2", - "HCLK_CK_IN0", - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "B_TERM_UTURN_INT_SS2BEG1", - "HCLK_INT_PERFCLK0", - "HCLK_CK_BUFRCLK3", - "B_TERM_UTURN_INT_SE6D3", - "B_TERM_UTURN_INT_LV9", - "HCLK_CK_INOUT_R7", - "HCLK_CCIO3", - "B_TERM_UTURN_INT_LV_L7", - "HCLK_CK_BUFHCLK7", - "HCLK_CK_IN2", - "HCLK_INT_PERFCLK1", - "B_TERM_UTURN_INT_SE6C3", - "HCLK_CK_BUFHCLK2", - "B_TERM_UTURN_INT_SW6C1", - "HCLK_CK_IN9", - "HCLK_CK_OUTIN_R3", - "B_TERM_UTURN_INT_SE2BEG3", - "B_TERM_UTURN_INT_SS6A1", - "B_TERM_UTURN_INT_LV_L2", - "HCLK_CCIO0", - "B_TERM_UTURN_INT_SS2BEG2", - "B_TERM_UTURN_INT_SR1BEG1", - "B_TERM_UTURN_INT_LVB1", - "HCLK_CK_IN11", - "B_TERM_UTURN_INT_SE6B0", - "B_TERM_UTURN_INT_SS6D0", - "HCLK_CK_BUFHCLK5", - "B_TERM_UTURN_INT_LVB2", - "HCLK_CK_INOUT_R6", - "B_TERM_UTURN_INT_SS2BEG0", - "HCLK_INT_PERFCLK2", - "HCLK_CK_IN10", - "B_TERM_UTURN_INT_LVB0", - "HCLK_CCIO1", - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK1", - "B_TERM_UTURN_INT_SE6C1", - "B_TERM_UTURN_INT_SS6D2", - "B_TERM_UTURN_INT_SW6D0", - "HCLK_CK_IN7", - "B_TERM_UTURN_INT_SL1BEG0", - "B_TERM_UTURN_INT_LV6", - "HCLK_CK_IN4", - "HCLK_CK_INOUT_R3", - "B_TERM_UTURN_INT_LV18", - "B_TERM_UTURN_INT_LV5", - "HCLK_LEAF_CLK_B_TOP1", - "HCLK_CK_BUFRCLK0", - "B_TERM_UTURN_INT_SR1BEG3", - "HCLK_LEAF_CLK_B_TOP0", - "B_TERM_UTURN_INT_SL1BEG3", - "HCLK_CK_OUTIN_R5", - "B_TERM_UTURN_INT_SW2BEG2", - "HCLK_LEAF_CLK_B_TOP3", - "HCLK_CK_IN3", - "B_TERM_UTURN_INT_SS6A2", - "HCLK_LEAF_CLK_B_TOP2", - "B_TERM_UTURN_INT_SS2A3", - "HCLK_CK_BUFHCLK9", - "B_TERM_UTURN_INT_SE6C2" - ], - "sites": [], "pips": { - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_CK_INOUT_R0": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_CK_INOUT_R2": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_CK_INOUT_R3": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_CK_INOUT_R1": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" }, "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_CK_INOUT_R5": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP3": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP1": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP1", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK5", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" }, "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", "src_wire": "HCLK_CK_OUTIN_R7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP0": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP5": { + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R4", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP4": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP4", - "is_directional": "1", - "src_wire": "HCLK_CK_OUTIN_R6", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_CK_INOUT_R6": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R6", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", "src_wire": "HCLK_CK_BUFHCLK6", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_CK_INOUT_R7": { - "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R7", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP2": { + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", + "src_wire": "HCLK_CK_OUTIN_R2", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP2": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" - }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP5": { - "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP0": { + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP0", + "src_wire": "HCLK_CK_OUTIN_R4", "is_directional": "1", - "src_wire": "HCLK_CK_BUFHCLK7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" }, - "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP5": { + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP5", + "src_wire": "HCLK_CK_BUFHCLK0", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", "src_wire": "HCLK_CK_BUFHCLK1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_CK_INOUT_R3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_CK_INOUT_R1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_CK_INOUT_R4": { "can_invert": "0", - "dst_wire": "HCLK_CK_INOUT_R4", - "is_directional": "1", "src_wire": "HCLK_CK_BUFHCLK4", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_CK_INOUT_R2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_CK_INOUT_R7": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R7" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R5->>HCLK_LEAF_CLK_B_TOP3": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" }, "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", - "dst_wire": "HCLK_LEAF_CLK_B_TOP3", - "is_directional": "1", "src_wire": "HCLK_CK_OUTIN_R1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP3" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_CK_INOUT_R5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R2->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK6->>HCLK_CK_INOUT_R6": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R6" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_CK_INOUT_R0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_CK_INOUT_R0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R4->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP4": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP4" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP5": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP5" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP1": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP1" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_TOP0": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP0" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R3->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_OUTIN_R3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" + }, + "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP2": { + "can_invert": "0", + "src_wire": "HCLK_CK_BUFHCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "HCLK_LEAF_CLK_B_TOP2" } }, - "tile_type": "HCLK_R_BOT_UTURN" + "wires": [ + "B_TERM_UTURN_INT_SW6C0", + "B_TERM_UTURN_INT_LVB5", + "B_TERM_UTURN_INT_SE6D3", + "B_TERM_UTURN_INT_LV4", + "B_TERM_UTURN_INT_SS2BEG3", + "HCLK_INT_PERFCLK1", + "HCLK_CK_INOUT_R2", + "B_TERM_UTURN_INT_SE2BEG0", + "B_TERM_UTURN_INT_SS6B1", + "B_TERM_UTURN_INT_LV_L5", + "B_TERM_UTURN_INT_SE6D1", + "HCLK_CK_IN3", + "HCLK_CK_OUTIN_R6", + "B_TERM_UTURN_INT_LV2", + "B_TERM_UTURN_INT_LVB1", + "B_TERM_UTURN_INT_SS6BEG3", + "B_TERM_UTURN_INT_SL1BEG1", + "B_TERM_UTURN_INT_SL1BEG2", + "HCLK_CCIO0", + "B_TERM_UTURN_INT_SS6BEG1", + "HCLK_CK_INOUT_R4", + "B_TERM_UTURN_INT_LVB2", + "HCLK_INT_PERFCLK0", + "B_TERM_UTURN_INT_SE6A2", + "B_TERM_UTURN_INT_SS6D3", + "HCLK_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK9", + "HCLK_CCIO3", + "B_TERM_UTURN_INT_SS6BEG0", + "B_TERM_UTURN_INT_LV9", + "HCLK_LEAF_CLK_B_TOP0", + "HCLK_LEAF_CLK_B_TOP2", + "B_TERM_UTURN_INT_SE2BEG2", + "B_TERM_UTURN_INT_LV_L2", + "B_TERM_UTURN_INT_SE6B2", + "B_TERM_UTURN_INT_LV7", + "HCLK_CK_INOUT_R7", + "HCLK_LEAF_CLK_B_TOP4", + "B_TERM_UTURN_INT_SS6D2", + "B_TERM_UTURN_INT_SW6C2", + "HCLK_CK_IN13", + "B_TERM_UTURN_INT_SS6B3", + "B_TERM_UTURN_INT_SS2A1", + "B_TERM_UTURN_INT_SE2BEG1", + "HCLK_CK_OUTIN_R4", + "HCLK_CK_IN6", + "HCLK_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK8", + "B_TERM_UTURN_INT_SS6A2", + "HCLK_CK_IN5", + "HCLK_CK_IN0", + "B_TERM_UTURN_INT_SE6A0", + "HCLK_CK_INOUT_R5", + "HCLK_INT_PERFCLK3", + "HCLK_CK_BUFHCLK1", + "B_TERM_UTURN_INT_LV6", + "B_TERM_UTURN_INT_LV_L6", + "HCLK_CK_BUFHCLK10", + "B_TERM_UTURN_INT_SS2A2", + "B_TERM_UTURN_INT_WR1BEG0", + "B_TERM_UTURN_INT_SE6B0", + "HCLK_CK_OUTIN_R7", + "B_TERM_UTURN_INT_SL1BEG0", + "B_TERM_UTURN_INT_SW6A3", + "HCLK_CK_BUFHCLK11", + "B_TERM_UTURN_INT_LVB0", + "B_TERM_UTURN_INT_SE6C0", + "HCLK_INT_PERFCLK2", + "B_TERM_UTURN_INT_LV_L9", + "B_TERM_UTURN_INT_SW6B2", + "HCLK_CK_OUTIN_R3", + "B_TERM_UTURN_INT_LVB3", + "B_TERM_UTURN_INT_SW2BEG0", + "B_TERM_UTURN_INT_SW6A1", + "B_TERM_UTURN_INT_SE6D2", + "B_TERM_UTURN_INT_LV_L3", + "B_TERM_UTURN_INT_SR1BEG3", + "HCLK_CCIO1", + "B_TERM_UTURN_INT_FAN_BOUNCE6", + "B_TERM_UTURN_INT_SW6END_N0_3", + "B_TERM_UTURN_INT_SE6B1", + "B_TERM_UTURN_INT_LV5", + "B_TERM_UTURN_INT_SE2BEG3", + "B_TERM_UTURN_INT_SR1BEG2", + "B_TERM_UTURN_INT_FAN_BOUNCE2", + "HCLK_CK_INOUT_R1", + "B_TERM_UTURN_INT_SW6A2", + "HCLK_CK_BUFRCLK2", + "B_TERM_UTURN_INT_SS2BEG2", + "HCLK_LEAF_CLK_B_TOP3", + "HCLK_CK_BUFHCLK0", + "HCLK_CK_IN2", + "B_TERM_UTURN_INT_SS6D0", + "HCLK_CK_OUTIN_R0", + "HCLK_LEAF_CLK_B_TOP1", + "HCLK_CK_IN4", + "B_TERM_UTURN_INT_SE6A1", + "B_TERM_UTURN_INT_SS6A0", + "B_TERM_UTURN_INT_SS2BEG1", + "B_TERM_UTURN_INT_SE6C3", + "HCLK_CK_BUFHCLK5", + "B_TERM_UTURN_INT_SS6C2", + "B_TERM_UTURN_INT_FAN_BOUNCE4", + "B_TERM_UTURN_INT_SS6A3", + "B_TERM_UTURN_INT_SW6D2", + "HCLK_CK_IN8", + "B_TERM_UTURN_INT_SS6E3", + "HCLK_CK_BUFHCLK7", + "B_TERM_UTURN_INT_SW2BEG2", + "HCLK_CK_IN1", + "B_TERM_UTURN_INT_LV_L8", + "B_TERM_UTURN_INT_SW2BEG1", + "B_TERM_UTURN_INT_SW6B1", + "B_TERM_UTURN_INT_SW6B3", + "B_TERM_UTURN_INT_LVB4", + "B_TERM_UTURN_INT_SR1BEG1", + "B_TERM_UTURN_INT_SE6C2", + "B_TERM_UTURN_INT_SS2BEG0", + "B_TERM_UTURN_INT_SW2BEG3", + "HCLK_CK_BUFRCLK0", + "B_TERM_UTURN_INT_WR1END0", + "B_TERM_UTURN_INT_LV_L7", + "B_TERM_UTURN_INT_SW6D1", + "HCLK_CK_BUFRCLK1", + "B_TERM_UTURN_INT_SE6C1", + "B_TERM_UTURN_INT_LV18", + "B_TERM_UTURN_INT_SW6D3", + "B_TERM_UTURN_INT_SL1BEG3", + "HCLK_CK_OUTIN_R1", + "B_TERM_UTURN_INT_SS6E1", + "B_TERM_UTURN_INT_SW6C3", + "HCLK_CK_BUFHCLK6", + "HCLK_CK_INOUT_R3", + "B_TERM_UTURN_INT_SS6E0", + "B_TERM_UTURN_INT_SS2A3", + "HCLK_LEAF_CLK_B_TOP5", + "B_TERM_UTURN_INT_ER1BEG0", + "HCLK_CK_IN11", + "B_TERM_UTURN_INT_ER1END_N3_3", + "HCLK_CK_IN10", + "HCLK_CCIO2", + "B_TERM_UTURN_INT_SE6B3", + "B_TERM_UTURN_INT_SS6B2", + "HCLK_CK_IN7", + "B_TERM_UTURN_INT_SW6B0", + "HCLK_CK_INOUT_R6", + "B_TERM_UTURN_INT_SW6A0", + "B_TERM_UTURN_INT_LV3", + "B_TERM_UTURN_INT_SS6C3", + "B_TERM_UTURN_INT_SE6A3", + "B_TERM_UTURN_INT_LV8", + "HCLK_CK_IN9", + "HCLK_CK_OUTIN_R2", + "HCLK_CK_BUFHCLK2", + "B_TERM_UTURN_INT_SS6C1", + "B_TERM_UTURN_INT_SS6B0", + "B_TERM_UTURN_INT_SS6C0", + "HCLK_CK_BUFRCLK3", + "B_TERM_UTURN_INT_SW6C1", + "B_TERM_UTURN_INT_SS6D1", + "B_TERM_UTURN_INT_LV_L4", + "B_TERM_UTURN_INT_SS2A0", + "B_TERM_UTURN_INT_SS6A1", + "HCLK_CK_INOUT_R0", + "B_TERM_UTURN_INT_SS6E2", + "B_TERM_UTURN_INT_SW6D0", + "B_TERM_UTURN_INT_SS6BEG2", + "B_TERM_UTURN_INT_LV_L18", + "B_TERM_UTURN_INT_SE6D0", + "B_TERM_UTURN_INT_FAN_BOUNCE0", + "HCLK_CK_OUTIN_R5", + "HCLK_CK_IN12" + ], + "tile_type": "HCLK_R_BOT_UTURN", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_TERM.json b/artix7/tile_type_HCLK_TERM.json index 3b2d954..7d9a6ff 100644 --- a/artix7/tile_type_HCLK_TERM.json +++ b/artix7/tile_type_HCLK_TERM.json @@ -1,45 +1,45 @@ { + "pips": {}, "wires": [ - "HCLK_TERM_CK_BUFHCLK0", - "HCLK_TERM_CK_BUFHCLK10", - "HCLK_TERM_CK_IN4", - "HCLK_TERM_CK_IN13", - "HCLK_TERM_CCIO2", - "HCLK_TERM_CK_IN2", - "HCLK_TERM_CK_IN1", "HCLK_TERM_CK_BUFHCLK4", + "HCLK_TERM_CK_IN5", + "HCLK_TERM_CK_BUFHCLK10", + "HCLK_TERM_CK_BUFRCLK2", + "HCLK_TERM_CCIO0", + "HCLK_TERM_CK_IN12", + "HCLK_TERM_PERFCLK0", "HCLK_TERM_CK_BUFHCLK1", + "HCLK_TERM_CK_IN8", + "HCLK_TERM_CK_IN1", + "HCLK_TERM_CK_BUFHCLK6", + "HCLK_TERM_CK_BUFHCLK3", + "HCLK_TERM_CK_BUFHCLK5", "HCLK_TERM_CK_BUFHCLK7", + "HCLK_TERM_CK_IN2", + "HCLK_TERM_CK_IN4", + "HCLK_TERM_CK_BUFHCLK9", + "HCLK_TERM_CK_IN9", + "HCLK_TERM_CK_BUFHCLK0", + "HCLK_TERM_CK_IN3", + "HCLK_TERM_CK_BUFRCLK0", + "HCLK_TERM_CK_IN0", "HCLK_TERM_CK_BUFHCLK2", "HCLK_TERM_CK_BUFRCLK1", - "HCLK_TERM_CK_BUFRCLK2", - "HCLK_TERM_CK_BUFHCLK5", - "HCLK_TERM_CK_IN0", - "HCLK_TERM_CK_BUFHCLK11", - "HCLK_TERM_CK_IN9", - "HCLK_TERM_PERFCLK1", - "HCLK_TERM_CK_IN12", - "HCLK_TERM_CK_BUFRCLK0", - "HCLK_TERM_CK_IN11", - "HCLK_TERM_CK_BUFHCLK9", - "HCLK_TERM_CK_IN5", - "HCLK_TERM_PERFCLK3", - "HCLK_TERM_PERFCLK2", - "HCLK_TERM_CK_BUFHCLK6", - "HCLK_TERM_CK_IN3", "HCLK_TERM_CCIO1", - "HCLK_TERM_PERFCLK0", - "HCLK_TERM_CCIO0", - "HCLK_TERM_CCIO3", - "HCLK_TERM_CK_BUFRCLK3", - "HCLK_TERM_CK_BUFHCLK8", - "HCLK_TERM_CK_IN8", - "HCLK_TERM_CK_BUFHCLK3", - "HCLK_TERM_CK_IN10", + "HCLK_TERM_CCIO2", "HCLK_TERM_CK_IN7", - "HCLK_TERM_CK_IN6" + "HCLK_TERM_CK_BUFHCLK11", + "HCLK_TERM_CK_BUFHCLK8", + "HCLK_TERM_CK_IN6", + "HCLK_TERM_PERFCLK1", + "HCLK_TERM_CCIO3", + "HCLK_TERM_CK_IN10", + "HCLK_TERM_CK_IN11", + "HCLK_TERM_PERFCLK3", + "HCLK_TERM_CK_IN13", + "HCLK_TERM_CK_BUFRCLK3", + "HCLK_TERM_PERFCLK2" ], - "sites": [], - "pips": {}, - "tile_type": "HCLK_TERM" + "tile_type": "HCLK_TERM", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_TERM_GTX.json b/artix7/tile_type_HCLK_TERM_GTX.json index dd49684..65d3f46 100644 --- a/artix7/tile_type_HCLK_TERM_GTX.json +++ b/artix7/tile_type_HCLK_TERM_GTX.json @@ -1,21 +1,21 @@ { + "pips": {}, "wires": [ - "HCLK_TERM_GTX_CK_IN5", - "HCLK_TERM_GTX_CK_IN4", - "HCLK_TERM_GTX_CK_IN3", - "HCLK_TERM_GTX_CK_IN11", - "HCLK_TERM_GTX_CK_IN9", - "HCLK_TERM_GTX_CK_IN2", - "HCLK_TERM_GTX_CK_IN6", - "HCLK_TERM_GTX_CK_IN1", "HCLK_TERM_GTX_CK_IN0", + "HCLK_TERM_GTX_CK_IN7", + "HCLK_TERM_GTX_CK_IN12", + "HCLK_TERM_GTX_CK_IN11", + "HCLK_TERM_GTX_CK_IN3", + "HCLK_TERM_GTX_CK_IN5", + "HCLK_TERM_GTX_CK_IN6", + "HCLK_TERM_GTX_CK_IN9", "HCLK_TERM_GTX_CK_IN8", "HCLK_TERM_GTX_CK_IN13", - "HCLK_TERM_GTX_CK_IN7", + "HCLK_TERM_GTX_CK_IN2", "HCLK_TERM_GTX_CK_IN10", - "HCLK_TERM_GTX_CK_IN12" + "HCLK_TERM_GTX_CK_IN4", + "HCLK_TERM_GTX_CK_IN1" ], - "sites": [], - "pips": {}, - "tile_type": "HCLK_TERM_GTX" + "tile_type": "HCLK_TERM_GTX", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_VBRK.json b/artix7/tile_type_HCLK_VBRK.json index 4ed797a..503c7ab 100644 --- a/artix7/tile_type_HCLK_VBRK.json +++ b/artix7/tile_type_HCLK_VBRK.json @@ -1,45 +1,45 @@ { - "wires": [ - "HCLK_VBRK_MUX_CLK11", - "HCLK_VBRK_MUX_CLK3", - "HCLK_VBRK_REFCK_WESTCLK1", - "HCLK_VBRK_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK0", - "HCLK_VBRK_MUX_CLK1", - "HCLK_VBRK_REFCK_EASTCLK0", - "HCLK_VBRK_REFCK_WESTCLK0", - "HCLK_VBRK_CK_BUFRCLK2", - "HCLK_VBRK_MUX_CLK10", - "HCLK_VBRK_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK11", - "HCLK_VBRK_REFCK_EASTCLK1", - "HCLK_VBRK_MUX_CLK2", - "HCLK_VBRK_PHSR_PERFCLK2", - "HCLK_VBRK_CK_BUFHCLK10", - "HCLK_VBRK_MUX_CLK6", - "HCLK_VBRK_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFHCLK1", - "HCLK_VBRK_MUX_CLK7", - "HCLK_VBRK_PHSR_PERFCLK1", - "HCLK_VBRK_CK_BUFHCLK6", - "HCLK_VBRK_MUX_CLK13", - "HCLK_VBRK_MUX_CLK8", - "HCLK_VBRK_CK_BUFHCLK8", - "HCLK_VBRK_PHSR_PERFCLK0", - "HCLK_VBRK_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK2", - "HCLK_VBRK_MUX_CLK12", - "HCLK_VBRK_MUX_CLK0", - "HCLK_VBRK_CK_BUFRCLK1", - "HCLK_VBRK_MUX_CLK4", - "HCLK_VBRK_MUX_CLK5", - "HCLK_VBRK_MUX_CLK9", - "HCLK_VBRK_PHSR_PERFCLK3" - ], - "sites": [], "pips": {}, - "tile_type": "HCLK_VBRK" + "wires": [ + "HCLK_VBRK_REFCK_WESTCLK0", + "HCLK_VBRK_MUX_CLK2", + "HCLK_VBRK_CK_BUFRCLK1", + "HCLK_VBRK_MUX_CLK3", + "HCLK_VBRK_MUX_CLK6", + "HCLK_VBRK_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK2", + "HCLK_VBRK_MUX_CLK9", + "HCLK_VBRK_MUX_CLK7", + "HCLK_VBRK_MUX_CLK12", + "HCLK_VBRK_CK_BUFHCLK10", + "HCLK_VBRK_PHSR_PERFCLK1", + "HCLK_VBRK_REFCK_EASTCLK0", + "HCLK_VBRK_CK_BUFHCLK7", + "HCLK_VBRK_MUX_CLK1", + "HCLK_VBRK_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK0", + "HCLK_VBRK_MUX_CLK10", + "HCLK_VBRK_PHSR_PERFCLK2", + "HCLK_VBRK_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK0", + "HCLK_VBRK_MUX_CLK0", + "HCLK_VBRK_REFCK_WESTCLK1", + "HCLK_VBRK_MUX_CLK5", + "HCLK_VBRK_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFRCLK3", + "HCLK_VBRK_MUX_CLK8", + "HCLK_VBRK_CK_BUFHCLK1", + "HCLK_VBRK_MUX_CLK13", + "HCLK_VBRK_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFHCLK3", + "HCLK_VBRK_REFCK_EASTCLK1", + "HCLK_VBRK_MUX_CLK4", + "HCLK_VBRK_MUX_CLK11" + ], + "tile_type": "HCLK_VBRK", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_HCLK_VFRAME.json b/artix7/tile_type_HCLK_VFRAME.json index c3d132f..ff70091 100644 --- a/artix7/tile_type_HCLK_VFRAME.json +++ b/artix7/tile_type_HCLK_VFRAME.json @@ -1,37 +1,37 @@ { + "pips": {}, "wires": [ - "HCLK_VFRAME_CK_BUFRCLK3", - "HCLK_VFRAME_CK_BUFHCLK11", - "HCLK_VFRAME_CK_IN6", - "HCLK_VFRAME_CK_BUFHCLK9", - "HCLK_VFRAME_CK_BUFHCLK0", - "HCLK_VFRAME_CK_IN11", - "HCLK_VFRAME_CK_IN0", - "HCLK_VFRAME_CK_IN13", "HCLK_VFRAME_CK_BUFHCLK3", - "HCLK_VFRAME_CK_IN7", - "HCLK_VFRAME_CK_IN10", - "HCLK_VFRAME_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFHCLK5", + "HCLK_VFRAME_CK_IN11", + "HCLK_VFRAME_CK_BUFHCLK0", + "HCLK_VFRAME_CK_IN9", + "HCLK_VFRAME_CK_IN0", + "HCLK_VFRAME_CK_BUFHCLK11", "HCLK_VFRAME_CK_IN8", - "HCLK_VFRAME_CK_BUFHCLK7", + "HCLK_VFRAME_CK_IN6", + "HCLK_VFRAME_CK_IN7", + "HCLK_VFRAME_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK6", + "HCLK_VFRAME_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFRCLK1", + "HCLK_VFRAME_CK_BUFHCLK8", + "HCLK_VFRAME_CK_IN2", + "HCLK_VFRAME_CK_IN10", + "HCLK_VFRAME_CK_IN12", + "HCLK_VFRAME_CK_IN13", "HCLK_VFRAME_CK_IN1", "HCLK_VFRAME_CK_BUFHCLK2", - "HCLK_VFRAME_CK_IN2", - "HCLK_VFRAME_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK10", - "HCLK_VFRAME_CK_BUFHCLK1", - "HCLK_VFRAME_CK_IN12", + "HCLK_VFRAME_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK2", "HCLK_VFRAME_CK_IN3", "HCLK_VFRAME_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFHCLK9", + "HCLK_VFRAME_CK_IN4", + "HCLK_VFRAME_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK1", "HCLK_VFRAME_CK_IN5", - "HCLK_VFRAME_CK_BUFHCLK6", - "HCLK_VFRAME_CK_IN9", - "HCLK_VFRAME_CK_BUFRCLK2", - "HCLK_VFRAME_CK_IN4" + "HCLK_VFRAME_CK_BUFHCLK4" ], - "sites": [], - "pips": {}, - "tile_type": "HCLK_VFRAME" + "tile_type": "HCLK_VFRAME", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_INT_FEEDTHRU_1.json b/artix7/tile_type_INT_FEEDTHRU_1.json index 2e49d80..37ddd87 100644 --- a/artix7/tile_type_INT_FEEDTHRU_1.json +++ b/artix7/tile_type_INT_FEEDTHRU_1.json @@ -1,133 +1,133 @@ { + "pips": {}, "wires": [ - "INT_FEEDTHRU_1_SE2A0", + "INT_FEEDTHRU_1_NW4A3", + "INT_FEEDTHRU_1_SE4BEG3", "INT_FEEDTHRU_1_WW4C0", - "INT_FEEDTHRU_1_SE2A3", - "INT_FEEDTHRU_1_WW4END0", - "INT_FEEDTHRU_1_WL1END2", - "INT_FEEDTHRU_1_EE2A0", - "INT_FEEDTHRU_1_LH6", - "INT_FEEDTHRU_1_LH5", - "INT_FEEDTHRU_1_WW4C3", - "INT_FEEDTHRU_1_NW4END3", + "INT_FEEDTHRU_1_SW4END3", + "INT_FEEDTHRU_1_EL1BEG3", "INT_FEEDTHRU_1_WW4B3", - "INT_FEEDTHRU_1_EE4B3", - "INT_FEEDTHRU_1_SW4A0", - "INT_FEEDTHRU_1_SW4A2", + "INT_FEEDTHRU_1_SE4C3", + "INT_FEEDTHRU_1_SW4END0", + "INT_FEEDTHRU_1_ER1BEG2", + "INT_FEEDTHRU_1_NE2A3", + "INT_FEEDTHRU_1_WR1END0", + "INT_FEEDTHRU_1_EL1BEG1", "INT_FEEDTHRU_1_WL1END0", "INT_FEEDTHRU_1_SW4END1", - "INT_FEEDTHRU_1_SW2A3", - "INT_FEEDTHRU_1_NE4C1", - "INT_FEEDTHRU_1_LH8", - "INT_FEEDTHRU_1_SE2A1", - "INT_FEEDTHRU_1_NW4A0", - "INT_FEEDTHRU_1_NW2A0", - "INT_FEEDTHRU_1_WW4END3", - "INT_FEEDTHRU_1_EE2BEG0", - "INT_FEEDTHRU_1_WR1END0", - "INT_FEEDTHRU_1_SE2A2", - "INT_FEEDTHRU_1_EE4B1", - "INT_FEEDTHRU_1_EE2BEG3", - "INT_FEEDTHRU_1_SW4END0", - "INT_FEEDTHRU_1_LH10", - "INT_FEEDTHRU_1_LH1", - "INT_FEEDTHRU_1_EE4BEG0", - "INT_FEEDTHRU_1_NE4BEG0", - "INT_FEEDTHRU_1_NE4C3", - "INT_FEEDTHRU_1_EE4A2", - "INT_FEEDTHRU_1_NE4BEG1", - "INT_FEEDTHRU_1_WW4A0", - "INT_FEEDTHRU_1_ER1BEG3", - "INT_FEEDTHRU_1_WL1END1", - "INT_FEEDTHRU_1_SW2A0", - "INT_FEEDTHRU_1_WW4A2", - "INT_FEEDTHRU_1_NE2A2", - "INT_FEEDTHRU_1_MONITOR_P", - "INT_FEEDTHRU_1_EL1BEG1", - "INT_FEEDTHRU_1_EE4A3", - "INT_FEEDTHRU_1_WW2A1", - "INT_FEEDTHRU_1_NW4A1", - "INT_FEEDTHRU_1_SE4C2", - "INT_FEEDTHRU_1_NW4A2", - "INT_FEEDTHRU_1_EE2BEG2", - "INT_FEEDTHRU_1_NW4A3", - "INT_FEEDTHRU_1_EE4BEG2", - "INT_FEEDTHRU_1_WL1END3", - "INT_FEEDTHRU_1_NE2A0", - "INT_FEEDTHRU_1_EE4B2", - "INT_FEEDTHRU_1_WW4A3", - "INT_FEEDTHRU_1_EE4C3", - "INT_FEEDTHRU_1_SE4C1", - "INT_FEEDTHRU_1_WW2A0", - "INT_FEEDTHRU_1_LH3", - "INT_FEEDTHRU_1_MONITOR_N", - "INT_FEEDTHRU_1_EE4A1", - "INT_FEEDTHRU_1_SE4BEG0", - "INT_FEEDTHRU_1_SE4C3", - "INT_FEEDTHRU_1_NE2A1", + "INT_FEEDTHRU_1_SE4BEG1", + "INT_FEEDTHRU_1_WW2END3", + "INT_FEEDTHRU_1_EE2BEG1", "INT_FEEDTHRU_1_EE4BEG3", + "INT_FEEDTHRU_1_SW2A0", + "INT_FEEDTHRU_1_EE2A3", + "INT_FEEDTHRU_1_NW2A2", + "INT_FEEDTHRU_1_NW2A1", + "INT_FEEDTHRU_1_ER1BEG1", + "INT_FEEDTHRU_1_LH6", + "INT_FEEDTHRU_1_SE2A3", + "INT_FEEDTHRU_1_EE4C1", + "INT_FEEDTHRU_1_WW2A1", + "INT_FEEDTHRU_1_SW2A3", + "INT_FEEDTHRU_1_NW4A0", + "INT_FEEDTHRU_1_NW4END3", + "INT_FEEDTHRU_1_NW4END1", + "INT_FEEDTHRU_1_WW2A0", + "INT_FEEDTHRU_1_WL1END1", + "INT_FEEDTHRU_1_EE2A0", + "INT_FEEDTHRU_1_NE2A1", + "INT_FEEDTHRU_1_NE2A0", + "INT_FEEDTHRU_1_SW4END2", + "INT_FEEDTHRU_1_LH3", + "INT_FEEDTHRU_1_WR1END2", + "INT_FEEDTHRU_1_LH1", + "INT_FEEDTHRU_1_EE4A1", + "INT_FEEDTHRU_1_EE2A1", + "INT_FEEDTHRU_1_SE4BEG2", + "INT_FEEDTHRU_1_EE4B1", + "INT_FEEDTHRU_1_WW4END3", + "INT_FEEDTHRU_1_NE2A2", + "INT_FEEDTHRU_1_WL1END3", + "INT_FEEDTHRU_1_LH9", + "INT_FEEDTHRU_1_SW2A2", + "INT_FEEDTHRU_1_EE4BEG0", + "INT_FEEDTHRU_1_WL1END2", + "INT_FEEDTHRU_1_SW4A2", + "INT_FEEDTHRU_1_MONITOR_N", + "INT_FEEDTHRU_1_MONITOR_P", + "INT_FEEDTHRU_1_EE4A3", + "INT_FEEDTHRU_1_NW2A3", + "INT_FEEDTHRU_1_WW4B0", + "INT_FEEDTHRU_1_WW2END1", + "INT_FEEDTHRU_1_LH7", + "INT_FEEDTHRU_1_WW4C2", + "INT_FEEDTHRU_1_WW4END2", + "INT_FEEDTHRU_1_LH2", + "INT_FEEDTHRU_1_EE4C3", + "INT_FEEDTHRU_1_EE4B0", + "INT_FEEDTHRU_1_LH12", + "INT_FEEDTHRU_1_NW4END2", + "INT_FEEDTHRU_1_LH10", + "INT_FEEDTHRU_1_NW4A2", + "INT_FEEDTHRU_1_EE4A0", + "INT_FEEDTHRU_1_WW4A2", + "INT_FEEDTHRU_1_NE4BEG0", + "INT_FEEDTHRU_1_SW2A1", + "INT_FEEDTHRU_1_NW2A0", + "INT_FEEDTHRU_1_WW2A3", + "INT_FEEDTHRU_1_LH5", + "INT_FEEDTHRU_1_NW4END0", + "INT_FEEDTHRU_1_NE4BEG2", + "INT_FEEDTHRU_1_SE4C0", + "INT_FEEDTHRU_1_SW4A0", + "INT_FEEDTHRU_1_NW4A1", + "INT_FEEDTHRU_1_EE4C2", + "INT_FEEDTHRU_1_NE4C0", + "INT_FEEDTHRU_1_SE4BEG0", + "INT_FEEDTHRU_1_EL1BEG2", + "INT_FEEDTHRU_1_WW2END2", + "INT_FEEDTHRU_1_ER1BEG0", + "INT_FEEDTHRU_1_EE2BEG0", + "INT_FEEDTHRU_1_NE4C2", + "INT_FEEDTHRU_1_WW2END0", + "INT_FEEDTHRU_1_EE2BEG3", + "INT_FEEDTHRU_1_WW4C3", + "INT_FEEDTHRU_1_EE4B3", + "INT_FEEDTHRU_1_EE2A2", + "INT_FEEDTHRU_1_EE4C0", + "INT_FEEDTHRU_1_EE4B2", + "INT_FEEDTHRU_1_NE4BEG3", + "INT_FEEDTHRU_1_LH8", + "INT_FEEDTHRU_1_WR1END3", + "INT_FEEDTHRU_1_SW4A1", + "INT_FEEDTHRU_1_EE4BEG2", + "INT_FEEDTHRU_1_WW4A0", + "INT_FEEDTHRU_1_NE4C1", + "INT_FEEDTHRU_1_SE2A2", + "INT_FEEDTHRU_1_WW4END0", + "INT_FEEDTHRU_1_SE2A1", + "INT_FEEDTHRU_1_WW4B2", + "INT_FEEDTHRU_1_SE2A0", + "INT_FEEDTHRU_1_WW4END1", + "INT_FEEDTHRU_1_WR1END1", + "INT_FEEDTHRU_1_LH11", + "INT_FEEDTHRU_1_SE4C2", + "INT_FEEDTHRU_1_EE2BEG2", "INT_FEEDTHRU_1_WW2A2", "INT_FEEDTHRU_1_LH4", - "INT_FEEDTHRU_1_WW4A1", - "INT_FEEDTHRU_1_LH9", - "INT_FEEDTHRU_1_ER1BEG0", - "INT_FEEDTHRU_1_LH2", - "INT_FEEDTHRU_1_EE4B0", - "INT_FEEDTHRU_1_ER1BEG2", - "INT_FEEDTHRU_1_WW2A3", - "INT_FEEDTHRU_1_SE4C0", - "INT_FEEDTHRU_1_WR1END3", - "INT_FEEDTHRU_1_EE2A2", - "INT_FEEDTHRU_1_NW2A2", - "INT_FEEDTHRU_1_EL1BEG2", - "INT_FEEDTHRU_1_EE4C0", - "INT_FEEDTHRU_1_WR1END2", - "INT_FEEDTHRU_1_NW4END2", - "INT_FEEDTHRU_1_NE4C0", - "INT_FEEDTHRU_1_EL1BEG0", - "INT_FEEDTHRU_1_SW4A1", - "INT_FEEDTHRU_1_NE2A3", + "INT_FEEDTHRU_1_NE4BEG1", "INT_FEEDTHRU_1_WW4B1", - "INT_FEEDTHRU_1_EE4C2", - "INT_FEEDTHRU_1_SW2A2", - "INT_FEEDTHRU_1_SE4BEG1", + "INT_FEEDTHRU_1_EL1BEG0", + "INT_FEEDTHRU_1_NE4C3", + "INT_FEEDTHRU_1_WW4A1", "INT_FEEDTHRU_1_EE4BEG1", - "INT_FEEDTHRU_1_NE4BEG2", - "INT_FEEDTHRU_1_NW4END0", - "INT_FEEDTHRU_1_WW4C2", - "INT_FEEDTHRU_1_WW4END1", - "INT_FEEDTHRU_1_EE2A3", "INT_FEEDTHRU_1_WW4C1", - "INT_FEEDTHRU_1_WW4B2", - "INT_FEEDTHRU_1_SW4END3", - "INT_FEEDTHRU_1_NW2A1", - "INT_FEEDTHRU_1_NE4C2", - "INT_FEEDTHRU_1_SE4BEG3", + "INT_FEEDTHRU_1_EE4A2", + "INT_FEEDTHRU_1_WW4A3", "INT_FEEDTHRU_1_SW4A3", - "INT_FEEDTHRU_1_LH12", - "INT_FEEDTHRU_1_EL1BEG3", - "INT_FEEDTHRU_1_SW4END2", - "INT_FEEDTHRU_1_NW2A3", - "INT_FEEDTHRU_1_LH7", - "INT_FEEDTHRU_1_NW4END1", - "INT_FEEDTHRU_1_EE4A0", - "INT_FEEDTHRU_1_WW2END3", - "INT_FEEDTHRU_1_SE4BEG2", - "INT_FEEDTHRU_1_WR1END1", - "INT_FEEDTHRU_1_EE2A1", - "INT_FEEDTHRU_1_ER1BEG1", - "INT_FEEDTHRU_1_NE4BEG3", - "INT_FEEDTHRU_1_EE2BEG1", - "INT_FEEDTHRU_1_WW4B0", - "INT_FEEDTHRU_1_LH11", - "INT_FEEDTHRU_1_SW2A1", - "INT_FEEDTHRU_1_WW2END0", - "INT_FEEDTHRU_1_WW2END2", - "INT_FEEDTHRU_1_WW4END2", - "INT_FEEDTHRU_1_WW2END1", - "INT_FEEDTHRU_1_EE4C1" + "INT_FEEDTHRU_1_ER1BEG3", + "INT_FEEDTHRU_1_SE4C1" ], - "sites": [], - "pips": {}, - "tile_type": "INT_FEEDTHRU_1" + "tile_type": "INT_FEEDTHRU_1", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_INT_FEEDTHRU_2.json b/artix7/tile_type_INT_FEEDTHRU_2.json index 9d7fc0e..f309617 100644 --- a/artix7/tile_type_INT_FEEDTHRU_2.json +++ b/artix7/tile_type_INT_FEEDTHRU_2.json @@ -1,133 +1,133 @@ { + "pips": {}, "wires": [ - "INT_FEEDTHRU_2_WR1END3", - "INT_FEEDTHRU_2_WW4A3", - "INT_FEEDTHRU_2_NW4END2", - "INT_FEEDTHRU_2_WL1END2", - "INT_FEEDTHRU_2_NE4C3", - "INT_FEEDTHRU_2_NE4BEG1", - "INT_FEEDTHRU_2_WW2END1", - "INT_FEEDTHRU_2_NW4A0", - "INT_FEEDTHRU_2_WL1END3", - "INT_FEEDTHRU_2_LH3", - "INT_FEEDTHRU_2_WW4B2", - "INT_FEEDTHRU_2_EE4A3", - "INT_FEEDTHRU_2_LH12", - "INT_FEEDTHRU_2_EE4B0", - "INT_FEEDTHRU_2_ER1BEG1", - "INT_FEEDTHRU_2_WR1END0", - "INT_FEEDTHRU_2_EL1BEG2", - "INT_FEEDTHRU_2_SE4BEG2", - "INT_FEEDTHRU_2_WW4A1", - "INT_FEEDTHRU_2_EE4C2", - "INT_FEEDTHRU_2_SE2A1", - "INT_FEEDTHRU_2_SE4C0", - "INT_FEEDTHRU_2_EE4A1", - "INT_FEEDTHRU_2_WW2END0", - "INT_FEEDTHRU_2_LH5", - "INT_FEEDTHRU_2_NE4BEG3", - "INT_FEEDTHRU_2_MONITOR_P", - "INT_FEEDTHRU_2_WW4B3", - "INT_FEEDTHRU_2_NE4C1", "INT_FEEDTHRU_2_LH9", - "INT_FEEDTHRU_2_EE2A3", - "INT_FEEDTHRU_2_LH8", - "INT_FEEDTHRU_2_LH6", - "INT_FEEDTHRU_2_SE4BEG0", - "INT_FEEDTHRU_2_SW4END1", - "INT_FEEDTHRU_2_SW4END2", - "INT_FEEDTHRU_2_SE4BEG1", + "INT_FEEDTHRU_2_WL1END3", + "INT_FEEDTHRU_2_EL1BEG1", + "INT_FEEDTHRU_2_WW2END0", + "INT_FEEDTHRU_2_NW4END2", + "INT_FEEDTHRU_2_WW4END2", "INT_FEEDTHRU_2_NE4C0", + "INT_FEEDTHRU_2_SW4A1", + "INT_FEEDTHRU_2_EE2BEG3", + "INT_FEEDTHRU_2_EE2A2", + "INT_FEEDTHRU_2_EE4C2", "INT_FEEDTHRU_2_SW2A0", - "INT_FEEDTHRU_2_NW2A2", - "INT_FEEDTHRU_2_NW4END0", + "INT_FEEDTHRU_2_SE2A0", + "INT_FEEDTHRU_2_NE4C2", + "INT_FEEDTHRU_2_EE2A0", + "INT_FEEDTHRU_2_NW4END1", + "INT_FEEDTHRU_2_EL1BEG3", + "INT_FEEDTHRU_2_EE4A3", + "INT_FEEDTHRU_2_WW4B2", + "INT_FEEDTHRU_2_EE4BEG1", + "INT_FEEDTHRU_2_EL1BEG2", + "INT_FEEDTHRU_2_WW4END3", + "INT_FEEDTHRU_2_LH8", + "INT_FEEDTHRU_2_ER1BEG0", + "INT_FEEDTHRU_2_LH5", + "INT_FEEDTHRU_2_NE2A1", + "INT_FEEDTHRU_2_EE4B3", + "INT_FEEDTHRU_2_WW4A3", + "INT_FEEDTHRU_2_EE4BEG0", + "INT_FEEDTHRU_2_SE4BEG2", + "INT_FEEDTHRU_2_WL1END0", + "INT_FEEDTHRU_2_WW2END2", + "INT_FEEDTHRU_2_SW4END0", + "INT_FEEDTHRU_2_EE4B1", + "INT_FEEDTHRU_2_SE4BEG3", + "INT_FEEDTHRU_2_WW4B1", + "INT_FEEDTHRU_2_EL1BEG0", + "INT_FEEDTHRU_2_NE2A2", + "INT_FEEDTHRU_2_NE4BEG2", "INT_FEEDTHRU_2_WW4C3", "INT_FEEDTHRU_2_EE4C1", - "INT_FEEDTHRU_2_EE2BEG3", - "INT_FEEDTHRU_2_SW4A1", - "INT_FEEDTHRU_2_ER1BEG3", - "INT_FEEDTHRU_2_EE4BEG1", + "INT_FEEDTHRU_2_NW4A0", + "INT_FEEDTHRU_2_NE2A0", + "INT_FEEDTHRU_2_NW4A1", + "INT_FEEDTHRU_2_SE2A1", + "INT_FEEDTHRU_2_EE2BEG2", + "INT_FEEDTHRU_2_LH6", + "INT_FEEDTHRU_2_WW2A1", + "INT_FEEDTHRU_2_WR1END0", + "INT_FEEDTHRU_2_EE4B0", + "INT_FEEDTHRU_2_LH3", "INT_FEEDTHRU_2_WW4END0", - "INT_FEEDTHRU_2_NW4A2", - "INT_FEEDTHRU_2_SW2A3", - "INT_FEEDTHRU_2_SE4C3", - "INT_FEEDTHRU_2_LH10", - "INT_FEEDTHRU_2_EL1BEG0", - "INT_FEEDTHRU_2_NE2A1", - "INT_FEEDTHRU_2_SE4C2", - "INT_FEEDTHRU_2_WW4END1", - "INT_FEEDTHRU_2_EE4C0", - "INT_FEEDTHRU_2_ER1BEG0", - "INT_FEEDTHRU_2_WW4B0", - "INT_FEEDTHRU_2_ER1BEG2", - "INT_FEEDTHRU_2_EE2BEG1", - "INT_FEEDTHRU_2_WR1END1", + "INT_FEEDTHRU_2_NE4BEG3", + "INT_FEEDTHRU_2_SW4A3", + "INT_FEEDTHRU_2_WL1END1", + "INT_FEEDTHRU_2_WL1END2", + "INT_FEEDTHRU_2_EE4C3", + "INT_FEEDTHRU_2_NE4C1", + "INT_FEEDTHRU_2_LH12", + "INT_FEEDTHRU_2_MONITOR_N", + "INT_FEEDTHRU_2_LH7", + "INT_FEEDTHRU_2_LH11", + "INT_FEEDTHRU_2_SW4END3", + "INT_FEEDTHRU_2_SE4BEG0", "INT_FEEDTHRU_2_NE2A3", - "INT_FEEDTHRU_2_SW4A0", + "INT_FEEDTHRU_2_SE4C3", + "INT_FEEDTHRU_2_SE4C0", + "INT_FEEDTHRU_2_LH1", + "INT_FEEDTHRU_2_EE4BEG3", + "INT_FEEDTHRU_2_SW2A1", + "INT_FEEDTHRU_2_EE4C0", + "INT_FEEDTHRU_2_NW4A2", + "INT_FEEDTHRU_2_NW2A3", + "INT_FEEDTHRU_2_EE2A3", + "INT_FEEDTHRU_2_WW4END1", + "INT_FEEDTHRU_2_EE4A1", + "INT_FEEDTHRU_2_NW4END3", + "INT_FEEDTHRU_2_WW4A2", + "INT_FEEDTHRU_2_WW2A3", + "INT_FEEDTHRU_2_NE4BEG0", + "INT_FEEDTHRU_2_NW2A1", + "INT_FEEDTHRU_2_NW4END0", + "INT_FEEDTHRU_2_EE4A2", + "INT_FEEDTHRU_2_LH4", + "INT_FEEDTHRU_2_WW4C0", + "INT_FEEDTHRU_2_SW4A2", + "INT_FEEDTHRU_2_NW4A3", + "INT_FEEDTHRU_2_WW2A0", + "INT_FEEDTHRU_2_EE4BEG2", + "INT_FEEDTHRU_2_WR1END1", + "INT_FEEDTHRU_2_EE2BEG1", + "INT_FEEDTHRU_2_NE4BEG1", + "INT_FEEDTHRU_2_EE2A1", + "INT_FEEDTHRU_2_EE2BEG0", + "INT_FEEDTHRU_2_WR1END2", + "INT_FEEDTHRU_2_SE4C1", + "INT_FEEDTHRU_2_WW4B3", + "INT_FEEDTHRU_2_WW4B0", + "INT_FEEDTHRU_2_WW2A2", + "INT_FEEDTHRU_2_NW2A2", + "INT_FEEDTHRU_2_SE4C2", + "INT_FEEDTHRU_2_WR1END3", + "INT_FEEDTHRU_2_SE2A3", + "INT_FEEDTHRU_2_SE4BEG1", + "INT_FEEDTHRU_2_SW4END1", + "INT_FEEDTHRU_2_NE4C3", + "INT_FEEDTHRU_2_EE4A0", + "INT_FEEDTHRU_2_LH10", + "INT_FEEDTHRU_2_WW4A1", + "INT_FEEDTHRU_2_EE4B2", + "INT_FEEDTHRU_2_WW4C1", + "INT_FEEDTHRU_2_WW4A0", + "INT_FEEDTHRU_2_ER1BEG2", "INT_FEEDTHRU_2_SE2A2", "INT_FEEDTHRU_2_WW4C2", - "INT_FEEDTHRU_2_LH2", - "INT_FEEDTHRU_2_NE4BEG0", - "INT_FEEDTHRU_2_LH4", - "INT_FEEDTHRU_2_EL1BEG1", - "INT_FEEDTHRU_2_WW4A2", - "INT_FEEDTHRU_2_EE2BEG0", - "INT_FEEDTHRU_2_EE2A0", - "INT_FEEDTHRU_2_WW4B1", - "INT_FEEDTHRU_2_NE4C2", - "INT_FEEDTHRU_2_NW2A0", - "INT_FEEDTHRU_2_WW4C1", - "INT_FEEDTHRU_2_NW4A3", - "INT_FEEDTHRU_2_EE4BEG3", - "INT_FEEDTHRU_2_NE2A2", - "INT_FEEDTHRU_2_WR1END2", - "INT_FEEDTHRU_2_NW4END1", - "INT_FEEDTHRU_2_EE4A0", - "INT_FEEDTHRU_2_WW4C0", - "INT_FEEDTHRU_2_EE2A2", - "INT_FEEDTHRU_2_EE4A2", - "INT_FEEDTHRU_2_SE4BEG3", - "INT_FEEDTHRU_2_EE4BEG2", - "INT_FEEDTHRU_2_NW4END3", - "INT_FEEDTHRU_2_SW4END0", - "INT_FEEDTHRU_2_SW4A3", - "INT_FEEDTHRU_2_LH1", - "INT_FEEDTHRU_2_SW4A2", - "INT_FEEDTHRU_2_EE4C3", - "INT_FEEDTHRU_2_EE4B1", - "INT_FEEDTHRU_2_WW2A2", - "INT_FEEDTHRU_2_WW2END3", - "INT_FEEDTHRU_2_SE4C1", "INT_FEEDTHRU_2_SW2A2", - "INT_FEEDTHRU_2_EL1BEG3", - "INT_FEEDTHRU_2_SW2A1", - "INT_FEEDTHRU_2_SW4END3", - "INT_FEEDTHRU_2_EE2BEG2", - "INT_FEEDTHRU_2_WW4END2", - "INT_FEEDTHRU_2_WW2END2", - "INT_FEEDTHRU_2_NW2A3", - "INT_FEEDTHRU_2_WW2A3", - "INT_FEEDTHRU_2_WL1END0", - "INT_FEEDTHRU_2_EE2A1", - "INT_FEEDTHRU_2_NW2A1", - "INT_FEEDTHRU_2_LH11", - "INT_FEEDTHRU_2_MONITOR_N", - "INT_FEEDTHRU_2_EE4B3", - "INT_FEEDTHRU_2_NE2A0", - "INT_FEEDTHRU_2_WW4A0", - "INT_FEEDTHRU_2_EE4BEG0", - "INT_FEEDTHRU_2_NW4A1", - "INT_FEEDTHRU_2_WW2A0", - "INT_FEEDTHRU_2_SE2A0", - "INT_FEEDTHRU_2_LH7", - "INT_FEEDTHRU_2_WW2A1", - "INT_FEEDTHRU_2_EE4B2", - "INT_FEEDTHRU_2_WW4END3", - "INT_FEEDTHRU_2_NE4BEG2", - "INT_FEEDTHRU_2_WL1END1", - "INT_FEEDTHRU_2_SE2A3" + "INT_FEEDTHRU_2_ER1BEG3", + "INT_FEEDTHRU_2_NW2A0", + "INT_FEEDTHRU_2_SW4END2", + "INT_FEEDTHRU_2_SW2A3", + "INT_FEEDTHRU_2_SW4A0", + "INT_FEEDTHRU_2_WW2END3", + "INT_FEEDTHRU_2_LH2", + "INT_FEEDTHRU_2_WW2END1", + "INT_FEEDTHRU_2_MONITOR_P", + "INT_FEEDTHRU_2_ER1BEG1" ], - "sites": [], - "pips": {}, - "tile_type": "INT_FEEDTHRU_2" + "tile_type": "INT_FEEDTHRU_2", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_INT_INTERFACE_L.json b/artix7/tile_type_INT_INTERFACE_L.json index 0d145ce..8d53e45 100644 --- a/artix7/tile_type_INT_INTERFACE_L.json +++ b/artix7/tile_type_INT_INTERFACE_L.json @@ -1,428 +1,428 @@ { - "wires": [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "INT_INTERFACE_BYP5", - "INT_INTERFACE_IMUX45", - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_IMUX27", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "INT_INTERFACE_IMUX1", - "INT_INTERFACE_IMUX7", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_IMUX47", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_IMUX18", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_LH10", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "INT_INTERFACE_IMUX28", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_LOGIC_OUTS_L19", - "INT_INTERFACE_LH1", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_IMUX16", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_CLK0", - "INT_INTERFACE_LOGIC_OUTS_L22", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_LOGIC_OUTS_L4", - "INT_INTERFACE_LH6", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_IMUX44", - "INT_INTERFACE_IMUX43", - "INT_INTERFACE_IMUX10", - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "INT_INTERFACE_IMUX26", - "INT_INTERFACE_LOGIC_OUTS_L13", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_IMUX42", - "INT_INTERFACE_BLOCK_OUTS_L_B2", - "INT_INTERFACE_IMUX39", - "INT_INTERFACE_IMUX22", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_LOGIC_OUTS_L1", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_IMUX25", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_LOGIC_OUTS_L5", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_LOGIC_OUTS_L3", - "INT_INTERFACE_IMUX19", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_LOGIC_OUTS_L7", - "INT_INTERFACE_LOGIC_OUTS_L0", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "INT_INTERFACE_EE2A0", - "L_INT_INTER_DQS_IOTOPHASER", - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_IMUX4", - "INT_INTERFACE_IMUX12", - "INT_INTERFACE_LOGIC_OUTS_L21", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_LOGIC_OUTS_L18", - "INT_INTERFACE_LOGIC_OUTS_L14", - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "INT_INTERFACE_LOGIC_OUTS_L11", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_IMUX3", - "INT_INTERFACE_IMUX13", - "INT_INTERFACE_IMUX17", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_IMUX29", - "INT_INTERFACE_BYP1", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_LOGIC_OUTS_L23", - "INT_INTERFACE_LH8", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_IMUX31", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_LOGIC_OUTS_L_B14", - "INT_INTERFACE_IMUX0", - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "INT_INTERFACE_LOGIC_OUTS_L8", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_IMUX14", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_LH7", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_LOGIC_OUTS_L20", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_LH5", - "INT_INTERFACE_IMUX35", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_IMUX11", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_IMUX21", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "INT_INTERFACE_LOGIC_OUTS_L2", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_BYP2", - "INT_INTERFACE_IMUX38", - "INT_INTERFACE_IMUX23", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_LOGIC_OUTS_L10", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_IMUX24", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_IMUX41", - "INT_INTERFACE_IMUX40", - "INT_INTERFACE_IMUX8", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_LH2", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_IMUX20", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_IMUX36", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH9", - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "INT_INTERFACE_LOGIC_OUTS_L6", - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "INT_INTERFACE_IMUX32", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_BLOCK_OUTS_L_B0", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_IMUX37", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_IMUX33", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_IMUX6", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_LOGIC_OUTS_L12", - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW4END3", - "INT_INTERFACE_LH11", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "INT_INTERFACE_IMUX9", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_IMUX5", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_LOGIC_OUTS_L15", - "INT_INTERFACE_BLOCK_OUTS_L_B1", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_IMUX15", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_LOGIC_OUTS_L16", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_IMUX30", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_BLOCK_OUTS_L_B3", - "INT_INTERFACE_ER1BEG1", - "INT_INTERFACE_IMUX2", - "INT_INTERFACE_LOGIC_OUTS_L17", - "INT_INTERFACE_IMUX46", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_LH3", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_IMUX34", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_LOGIC_OUTS_L9" - ], - "sites": [], "pips": { - "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5", - "is_pseudo": "0" - }, - "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13", - "is_pseudo": "0" - }, - "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22", - "is_pseudo": "0" - }, "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { - "can_invert": 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"INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18" }, "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23", - "is_directional": "1", "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13" + }, + "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7" } }, - "tile_type": "INT_INTERFACE_L" + "wires": [ + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_IMUX28", + "INT_INTERFACE_IMUX15", + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "INT_INTERFACE_LOGIC_OUTS_L13", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_LOGIC_OUTS_L19", + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_LOGIC_OUTS_L1", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_IMUX23", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LH8", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_BLOCK_OUTS_L_B0", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_IMUX37", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_IMUX24", + "INT_INTERFACE_IMUX22", + "INT_INTERFACE_IMUX4", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_IMUX44", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_IMUX33", + "INT_INTERFACE_IMUX17", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_LOGIC_OUTS_L8", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_IMUX12", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "INT_INTERFACE_IMUX47", + "INT_INTERFACE_IMUX46", + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "INT_INTERFACE_LOGIC_OUTS_L5", + "INT_INTERFACE_IMUX13", + "INT_INTERFACE_IMUX1", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_IMUX0", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_BLOCK_OUTS_L_B2", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_IMUX25", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_IMUX29", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_IMUX21", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_LOGIC_OUTS_L22", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_LOGIC_OUTS_L3", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_BLOCK_OUTS_L_B1", + "INT_INTERFACE_LOGIC_OUTS_L23", + "INT_INTERFACE_LOGIC_OUTS_L11", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_IMUX36", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_IMUX10", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_LH6", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_IMUX3", + "INT_INTERFACE_IMUX11", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_IMUX8", + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_IMUX2", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_IMUX18", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LH5", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LH12", + "INT_INTERFACE_LH4", + "INT_INTERFACE_LOGIC_OUTS_L18", + "INT_INTERFACE_IMUX34", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_LOGIC_OUTS_L16", + "INT_INTERFACE_IMUX35", + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "INT_INTERFACE_LOGIC_OUTS_L2", + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "INT_INTERFACE_EL1BEG3", + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "INT_INTERFACE_IMUX5", + "INT_INTERFACE_BLOCK_OUTS_L_B3", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_IMUX32", + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_IMUX30", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_IMUX42", + "INT_INTERFACE_IMUX20", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_IMUX39", + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_LOGIC_OUTS_L10", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_LH7", + "INT_INTERFACE_IMUX14", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_LOGIC_OUTS_L9", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_IMUX6", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_IMUX45", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_LOGIC_OUTS_L15", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_IMUX38", + "INT_INTERFACE_IMUX43", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_LH2", + "INT_INTERFACE_LOGIC_OUTS_L21", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_IMUX41", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_LOGIC_OUTS_L20", + "INT_INTERFACE_LOGIC_OUTS_L14", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_LH9", + "INT_INTERFACE_LOGIC_OUTS_L17", + "INT_INTERFACE_LOGIC_OUTS_L0", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_IMUX27", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_IMUX26", + "INT_INTERFACE_LOGIC_OUTS_L12", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_LOGIC_OUTS_L6", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_LH3", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_IMUX19", + "INT_INTERFACE_IMUX7", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_L4", + "INT_INTERFACE_IMUX40", + "INT_INTERFACE_IMUX16", + "INT_INTERFACE_IMUX31", + "INT_INTERFACE_IMUX9", + "INT_INTERFACE_LOGIC_OUTS_L7", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + "tile_type": "INT_INTERFACE_L", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_INT_INTERFACE_R.json b/artix7/tile_type_INT_INTERFACE_R.json index 32ee628..e0eff4e 100644 --- a/artix7/tile_type_INT_INTERFACE_R.json +++ b/artix7/tile_type_INT_INTERFACE_R.json @@ -1,428 +1,428 @@ { - "wires": [ - "INT_INTERFACE_BYP5", - "INT_INTERFACE_IMUX45", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_IMUX27", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_IMUX1", - "INT_INTERFACE_IMUX7", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_IMUX47", - "INT_INTERFACE_LOGIC_OUTS17", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_IMUX18", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_LOGIC_OUTS16", - "INT_INTERFACE_LH10", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_BLOCK_OUTS_B0", - "INT_INTERFACE_IMUX28", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_LH1", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_IMUX16", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_LOGIC_OUTS10", - "INT_INTERFACE_CLK0", - "INT_INTERFACE_LOGIC_OUTS7", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_LOGIC_OUTS_B1", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_LOGIC_OUTS5", - "INT_INTERFACE_LH6", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_BLOCK_OUTS_B2", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_IMUX44", - "INT_INTERFACE_IMUX43", - "INT_INTERFACE_IMUX10", - "INT_INTERFACE_IMUX26", - "INT_INTERFACE_LOGIC_OUTS_B9", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_IMUX42", - "INT_INTERFACE_LOGIC_OUTS_B18", - "INT_INTERFACE_IMUX39", - "INT_INTERFACE_IMUX22", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_LOGIC_OUTS_B21", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS21", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_IMUX25", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_IMUX19", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_EE2A0", - "L_INT_INTER_DQS_IOTOPHASER", - "INT_INTERFACE_LOGIC_OUTS1", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_LOGIC_OUTS3", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_IMUX4", - "INT_INTERFACE_IMUX12", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_LOGIC_OUTS_B23", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_LOGIC_OUTS20", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_IMUX3", - "INT_INTERFACE_IMUX13", - "INT_INTERFACE_IMUX17", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_IMUX29", - "INT_INTERFACE_BYP1", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_LOGIC_OUTS4", - "INT_INTERFACE_LH8", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_IMUX31", - "INT_INTERFACE_LOGIC_OUTS12", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_LOGIC_OUTS_B4", - "INT_INTERFACE_IMUX0", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS_B5", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_IMUX14", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_LH7", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_LOGIC_OUTS11", - "INT_INTERFACE_LH5", - "INT_INTERFACE_IMUX35", - "INT_INTERFACE_BLOCK_OUTS_B3", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_IMUX11", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_IMUX21", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_LOGIC_OUTS18", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_BYP2", - "INT_INTERFACE_IMUX38", - "INT_INTERFACE_IMUX23", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_LOGIC_OUTS_B12", - "INT_INTERFACE_LOGIC_OUTS22", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_IMUX24", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_IMUX41", - "INT_INTERFACE_IMUX40", - "INT_INTERFACE_LOGIC_OUTS_B6", - "INT_INTERFACE_IMUX8", - "INT_INTERFACE_LOGIC_OUTS0", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_LH2", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_LOGIC_OUTS13", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_LOGIC_OUTS6", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_IMUX20", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_IMUX36", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_LOGIC_OUTS9", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH9", - "INT_INTERFACE_IMUX32", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_IMUX37", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_IMUX33", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_IMUX6", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW4END3", - "INT_INTERFACE_LOGIC_OUTS15", - "INT_INTERFACE_LH11", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_IMUX9", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_LOGIC_OUTS2", - "INT_INTERFACE_IMUX5", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_LOGIC_OUTS23", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_LOGIC_OUTS14", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_IMUX15", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_LOGIC_OUTS_B2", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_LOGIC_OUTS19", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_IMUX30", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_LOGIC_OUTS_B11", - "INT_INTERFACE_LOGIC_OUTS_B14", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_ER1BEG1", - "INT_INTERFACE_IMUX2", - "INT_INTERFACE_IMUX46", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_LH3", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_IMUX34", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_BLOCK_OUTS_B1" - ], - "sites": [], "pips": { - "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS13", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13", - "is_pseudo": "0" - }, - "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS5", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B5", - "is_pseudo": "0" - }, - "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS9", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B9", - "is_pseudo": "0" - }, - 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"INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS14" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS1" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS3" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS20" + }, + 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"INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS16" + }, + "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS23" } }, - "tile_type": "INT_INTERFACE_R" + "wires": [ + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_LOGIC_OUTS_B9", + "INT_INTERFACE_IMUX28", + "INT_INTERFACE_LOGIC_OUTS_B12", + "INT_INTERFACE_IMUX15", + "INT_INTERFACE_BLOCK_OUTS_B3", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_LOGIC_OUTS_B10", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_IMUX23", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LH8", + "INT_INTERFACE_LOGIC_OUTS_B22", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_LOGIC_OUTS4", + "INT_INTERFACE_LOGIC_OUTS1", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_IMUX37", + "INT_INTERFACE_LOGIC_OUTS0", + "INT_INTERFACE_LOGIC_OUTS_B11", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS20", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_LOGIC_OUTS18", + "INT_INTERFACE_IMUX24", + "INT_INTERFACE_LOGIC_OUTS_B20", + "INT_INTERFACE_IMUX22", + "INT_INTERFACE_IMUX4", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LOGIC_OUTS3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_IMUX44", + "INT_INTERFACE_LOGIC_OUTS_B14", + "INT_INTERFACE_BLOCK_OUTS_B2", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_IMUX33", + "INT_INTERFACE_IMUX17", + "INT_INTERFACE_LOGIC_OUTS_B1", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_IMUX12", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_LOGIC_OUTS2", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_IMUX47", + "INT_INTERFACE_IMUX46", + "INT_INTERFACE_IMUX13", + "INT_INTERFACE_IMUX1", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_LOGIC_OUTS_B7", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_IMUX0", + "INT_INTERFACE_LOGIC_OUTS16", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_IMUX25", + "INT_INTERFACE_LOGIC_OUTS8", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_LOGIC_OUTS9", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_IMUX29", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_IMUX21", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_IMUX36", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_LH6", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_IMUX3", + "INT_INTERFACE_IMUX11", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_IMUX8", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_LOGIC_OUTS14", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_LOGIC_OUTS11", + "INT_INTERFACE_LOGIC_OUTS_B18", + "INT_INTERFACE_IMUX2", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_LOGIC_OUTS10", + "INT_INTERFACE_IMUX18", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_LH5", + "INT_INTERFACE_LOGIC_OUTS_B3", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LH12", + "INT_INTERFACE_LH4", + "INT_INTERFACE_IMUX34", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_LOGIC_OUTS19", + "INT_INTERFACE_IMUX35", + "INT_INTERFACE_LOGIC_OUTS_B5", + "INT_INTERFACE_EL1BEG3", + "INT_INTERFACE_LOGIC_OUTS23", + "INT_INTERFACE_IMUX5", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS_B6", + "INT_INTERFACE_LOGIC_OUTS_B2", + "INT_INTERFACE_LOGIC_OUTS_B19", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_IMUX32", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_IMUX30", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_IMUX42", + "INT_INTERFACE_IMUX20", + "INT_INTERFACE_IMUX39", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_LOGIC_OUTS_B13", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_LH7", + "INT_INTERFACE_IMUX14", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_LOGIC_OUTS21", + "INT_INTERFACE_IMUX6", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_IMUX45", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_LOGIC_OUTS12", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_IMUX38", + "INT_INTERFACE_IMUX43", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_LH2", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_LOGIC_OUTS_B4", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_IMUX41", + "INT_INTERFACE_LOGIC_OUTS_B17", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_LOGIC_OUTS7", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS15", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_LH9", + "INT_INTERFACE_LOGIC_OUTS6", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_IMUX27", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_IMUX26", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_LOGIC_OUTS_B16", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_LH3", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_LOGIC_OUTS22", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_BLOCK_OUTS_B0", + "INT_INTERFACE_IMUX19", + "INT_INTERFACE_IMUX7", + "INT_INTERFACE_BLOCK_OUTS_B1", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_B15", + "INT_INTERFACE_IMUX40", + "INT_INTERFACE_IMUX16", + "INT_INTERFACE_IMUX31", + "INT_INTERFACE_IMUX9", + "INT_INTERFACE_LOGIC_OUTS13", + "INT_INTERFACE_IMUX10" + ], + "tile_type": "INT_INTERFACE_R", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_INT_L.json b/artix7/tile_type_INT_L.json index 6d65bb7..f3217be 100644 --- a/artix7/tile_type_INT_L.json +++ b/artix7/tile_type_INT_L.json @@ -1,26779 +1,26779 @@ { + "pips": { + "INT_L.SS6END2->>SW6BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.FAN_BOUNCE5->>BYP_ALT1": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.WW4END1->>NW6BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.NE6END0->>EL1BEG_N3": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L22->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.LOGIC_OUTS_L6->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.EE2END3->>BYP_ALT6": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.LOGIC_OUTS_L3->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.EE4END0->>SE6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.EE4END1->>WR1BEG2": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.NN2END2->>IMUX_L36": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.NN2END0->>NW6BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.LOGIC_OUTS_L9->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.SW2END_N0_3->>FAN_ALT0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.NL1END0->>IMUX_L32": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.EE2END1->>EL1BEG0": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L25": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NR1END1->>IMUX_L19": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.LOGIC_OUTS_L23->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.GCLK_L_B1->>CLK_L0": { + "src_wire": "GCLK_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.FAN_ALT4->>FAN_BOUNCE4": { + "src_wire": "FAN_ALT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE4" + }, + "INT_L.SE2END3->>IMUX_L6": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NW2END3->>LH12": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L25": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NN2END3->>FAN_ALT1": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.LOGIC_OUTS_L1->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L8": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.EL1END0->>IMUX_L1": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.NW2END_S0_0->>FAN_ALT3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L18": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L16": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.GCLK_L_B2->>GFAN0": { + "src_wire": "GCLK_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.NN2END0->>FAN_ALT0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.LOGIC_OUTS_L14->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.LOGIC_OUTS_L19->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.LOGIC_OUTS_L23->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.SW6END0->>EE4BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.SR1BEG_S0->>WW2BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.NW2END1->>NE2BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.EL1END2->>IMUX_L43": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.SR1END3->>BYP_ALT7": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.SL1END1->>IMUX_L2": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L16": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.NE6END3->>EE2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.WL1END0->>IMUX_L32": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.LH12->>SS6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.NN6END3->>NE6BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.NW6END1->>SW6BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.SS2END3->>IMUX_L31": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.SS2END1->>SS6BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.SE6END1->>SS6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.NW2END_S0_0->>SS6BEG3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.LV_L18->>SW6BEG3": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.LOGIC_OUTS_L0->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.ER1END2->>ER1BEG3": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.LOGIC_OUTS_L16->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.LOGIC_OUTS_L15->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.SL1END0->>BYP_ALT0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NR1END3->>IMUX_L23": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.NN6END0->>LV_L0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L16": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.SL1END0->>IMUX_L8": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.WR1END1->>IMUX_L11": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.SE2END1->>EL1BEG0": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.LV_L0->>SS6BEG0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.NL1BEG_N3->>IMUX_L6": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.BYP_ALT7->>BYP_BOUNCE7": { + "src_wire": "BYP_ALT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE7" + }, + "INT_L.WW2END2->>BYP_ALT6": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SL1END1->>IMUX_L3": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.EL1END0->>EL1BEG_N3": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.LV_L0->>EE4BEG0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.EE4END1->>NN2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.LOGIC_OUTS_L3->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.LOGIC_OUTS_L9->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.SS2END3->>IMUX_L30": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.NW6END1->>NW2BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.EE4END3->>LH0": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L30": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L45": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.NN2END0->>EE4BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.NE2END1->>SE2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.EE2END0->>SL1BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.NN6END3->>NW6BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.WL1END3->>WW2BEG3": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.WW2END2->>NW6BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.NE2END3->>IMUX_L6": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NE2END2->>IMUX_L43": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.VCC_WIRE->>IMUX_L9": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L15": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L7": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.FAN_ALT6->>FAN_L6": { + "src_wire": "FAN_ALT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_L6" + }, + "INT_L.NW6END2->>NW2BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.NN2END1->>NW6BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L8": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.SS2END1->>WW2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.NW2END3->>NN6BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.SE2END2->>SS6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.EE2END0->>IMUX_L24": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.EL1END3->>EL1BEG2": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.BYP_BOUNCE0->>BYP_ALT1": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.LOGIC_OUTS_L10->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.LOGIC_OUTS_L12->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.LOGIC_OUTS_L16->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.NR1END0->>NL1BEG_N3": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.WW2END3->>SW2BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.EL1END0->>BYP_ALT0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.LOGIC_OUTS_L1->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.WR1END3->>IMUX_L15": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.LOGIC_OUTS_L11->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.SR1BEG_S0->>IMUX_L41": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.NW6END3->>SW2BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.SS6END3->>SS6BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L46": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.NL1END2->>IMUX_L28": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L23": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.GCLK_L_B11_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B11_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.LOGIC_OUTS_L0->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.SE6END2->>NE6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.LOGIC_OUTS_L15->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.NW2END3->>SW2BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.LOGIC_OUTS_L16->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.ER1END0->>SS2BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.LOGIC_OUTS_L10->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.LOGIC_OUTS_L3->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.LOGIC_OUTS_L21->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L45": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L2": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.EL1END2->>IMUX_L20": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.LOGIC_OUTS_L14->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.LOGIC_OUTS_L14->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.LOGIC_OUTS_L14->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SW2END1->>WW4BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.NR1END1->>EL1BEG0": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.NE6END0->>WR1BEG1": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.WR1END2->>CTRL_L1": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.LOGIC_OUTS_L11->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.LOGIC_OUTS_L9->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.EL1END1->>IMUX_L10": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.VCC_WIRE->>IMUX_L43": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L44": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.LOGIC_OUTS_L20->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.EE4END0->>NE6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.SR1END2->>IMUX_L46": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.NE2END0->>IMUX_L9": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.SW6END1->>NL1BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.NR1END0->>NN2BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.NW2END3->>SW6BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.EE2END0->>SE6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.LOGIC_OUTS_L9->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.NL1END2->>IMUX_L43": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.LOGIC_OUTS_L18->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.SS2END3->>IMUX_L47": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.NL1END0->>NW2BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L35": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.ER1END0->>IMUX_L24": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.LOGIC_OUTS_L21->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.SW2END2->>SW2BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.LOGIC_OUTS_L10->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.NE6END2->>NR1BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.EL1END1->>IMUX_L42": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.WL1END2->>IMUX_L45": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L15": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.NW6END3->>NW2BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.SE2END1->>NE2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.WW4END_S0_0->>SS6BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.EL1END0->>NR1BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.NW2END2->>IMUX_L44": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.NE6END1->>NL1BEG0": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.LOGIC_OUTS_L20->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.WW2END2->>WL1BEG1": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.LOGIC_OUTS_L11->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L33": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.WR1END1->>CLK_L1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.NE6END3->>LH0": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.SL1END0->>SE2BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.NW6END1->>NN6BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.BYP_BOUNCE4->>CTRL_L1": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.SL1END2->>IMUX_L29": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.NE2END2->>IMUX_L12": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.GFAN1->>IMUX_L47": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.SR1END2->>IMUX_L29": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.NW2END2->>IMUX_L4": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.LOGIC_OUTS_L21->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.LOGIC_OUTS_L19->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.NN6END0->>EE2BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.SE2END1->>IMUX_L35": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.WR1END1->>NW2BEG1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.NE2END3->>FAN_ALT1": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.NN6END3->>LVB_L12": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.NN2END0->>SE6BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.SW2END2->>IMUX_L28": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.NE2END0->>FAN_ALT0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.NE6END2->>SL1BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.LOGIC_OUTS_L16->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.EE2END3->>IMUX_L38": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.GFAN1->>IMUX_L37": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.NN6END0->>WW4BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L4": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.SS6END1->>WW2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.GFAN1->>CTRL_L1": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.VCC_WIRE->>FAN_ALT1": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.LOGIC_OUTS_L3->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.LOGIC_OUTS_L0->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.SW2END3->>SS2BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.WW4END2->>SW2BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.NN6END2->>WW2BEG1": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.ER1END1->>IMUX_L19": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.SS2END_N0_3->>IMUX_L8": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.LOGIC_OUTS_L23->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.BYP_BOUNCE_N3_7->>FAN_ALT6": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.NN2END3->>IMUX_L7": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.SE2END3->>IMUX_L22": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.EL1END2->>IMUX_L12": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.SE2END3->>SL1BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.WL1END1->>IMUX_L12": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.ER1END2->>CTRL_L0": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.NN2END_S2_0->>IMUX_L47": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.SE2END3->>IMUX_L30": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.SE2END0->>IMUX_L41": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SE2END1->>IMUX_L11": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.GFAN1->>BYP_ALT6": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.LOGIC_OUTS_L8->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.NW2END3->>WW2BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L46": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.SE2END3->>NE6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.SE6END2->>NR1BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.ER1END1->>IMUX_L35": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L36": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.NW2END0->>NE6BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.WW4END2->>WL1BEG0": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.LOGIC_OUTS_L7->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.GFAN0->>BYP_ALT0": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NE2END2->>IMUX_L27": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.LOGIC_OUTS_L1->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L47": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.WR1END2->>IMUX_L13": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.EL1END2->>IMUX_L35": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.LOGIC_OUTS_L18->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.WW2END3->>SS6BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.EL1END2->>IMUX_L28": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.ER1END3->>SS2BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.GCLK_L_B3->>GFAN0": { + "src_wire": "GCLK_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.WW4END0->>NN2BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.EE2END2->>EL1BEG1": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.LOGIC_OUTS_L9->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.SL1END2->>IMUX_L20": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.GCLK_L_B5->>CLK_L0": { + "src_wire": "GCLK_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.BYP_BOUNCE3->>BYP_ALT6": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.LOGIC_OUTS_L10->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.EE2END1->>SL1BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.ER1END2->>IMUX_L45": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.EL1END1->>IMUX_L41": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.NL1END1->>IMUX_L2": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.LV_L9->>NN6BEG1": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L2": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.NW2END1->>NN6BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.LOGIC_OUTS_L1->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.GFAN0->>FAN_ALT6": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.LOGIC_OUTS_L3->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.SS6END3->>SE6BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.WR1END3->>FAN_ALT1": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.SW2END0->>SS2BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.FAN_BOUNCE1->>FAN_ALT6": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.SW6END3->>SS2BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.BYP_BOUNCE4->>CTRL_L0": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.EE4END2->>CTRL_L0": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.SW2END3->>IMUX_L15": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.EE2END2->>IMUX_L13": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.LOGIC_OUTS_L6->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L13": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.SR1BEG_S0->>SR1BEG1": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.SS2END3->>FAN_ALT3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.SE2END0->>SS2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.LOGIC_OUTS_L13->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.GCLK_L_B2->>GFAN1": { + "src_wire": "GCLK_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.SL1END3->>SW2BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.LOGIC_OUTS_L7->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.NW2END3->>NW2BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.SW2END_N0_3->>IMUX_L8": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.ER1END1->>IMUX_L20": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.VCC_WIRE->>FAN_ALT6": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.NE2END0->>NN6BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.NW6END0->>NE6BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.FAN_BOUNCE1->>BYP_ALT2": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.SW6END2->>SS2BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.SL1END3->>IMUX_L22": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.NW2END0->>NW6BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.LOGIC_OUTS_L17->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.WW2END0->>SW6BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.LH0->>NW6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.GFAN1->>IMUX_L28": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.SW6END2->>NW2BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.WR1END2->>IMUX_L5": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.LOGIC_OUTS_L13->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.NN2END3->>SR1BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L8": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.NN6END2->>NN2BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.NL1END0->>EL1BEG_N3": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.SS6END0->>SW6BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.SS6END2->>EE2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.NE2END3->>NN6BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.GFAN1->>CTRL_L0": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.BYP_BOUNCE4->>FAN_ALT7": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.SW2END0->>NW6BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.SW6END3->>EE4BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.LOGIC_OUTS_L7->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.WW4END1->>NN6BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.LOGIC_OUTS_L8->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.NE6END0->>EE4BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.SR1END_N3_3->>IMUX_L16": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.VCC_WIRE->>IMUX_L27": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.LOGIC_OUTS_L22->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.NN2END2->>IMUX_L21": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.SW2END0->>FAN_ALT4": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.SR1END1->>BYP_ALT2": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.SE6END0->>ER1BEG1": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L18": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.EE2END0->>IMUX_L0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.NN2END0->>NR1BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.LOGIC_OUTS_L13->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.ER1END3->>IMUX_L47": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.WW4END3->>SR1BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.NW2END3->>BYP_ALT6": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.LOGIC_OUTS_L15->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.LOGIC_OUTS_L9->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.SR1BEG_S0->>IMUX_L10": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.WL1END1->>IMUX_L26": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L34": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.ER1END0->>IMUX_L1": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.NN2END3->>NE2BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.EE2END1->>IMUX_L19": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.LOGIC_OUTS_L12->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.NR1END3->>LVB_L12": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.NR1END1->>NN2BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.EE4END0->>SL1BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.SL1END3->>SS2BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.SE2END0->>WL1BEG_N3": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.NN2END1->>NE6BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.SW2END2->>SR1BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.EE2END3->>IMUX_L46": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L12": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.LOGIC_OUTS_L17->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.SW2END2->>SS6BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.SW6END3->>SS6BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.NL1END2->>NE2BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.LOGIC_OUTS_L14->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.WR1END0->>IMUX_L24": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.LOGIC_OUTS_L23->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.LOGIC_OUTS_L11->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.LOGIC_OUTS_L23->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.SL1END0->>IMUX_L0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.WR1END2->>SR1BEG2": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.WL1END2->>WW2BEG2": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.LOGIC_OUTS_L5->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.SS2END1->>NW6BEG2": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.LOGIC_OUTS_L1->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.NN2END1->>FAN_ALT2": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.SE2END1->>EE4BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.NE2END1->>IMUX_L10": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.LOGIC_OUTS_L17->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.SW2END1->>WW2BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.NL1END1->>IMUX_L18": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L1": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.SW6END2->>WW4BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.NE2END2->>IMUX_L20": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.SW2END1->>IMUX_L11": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.SE2END0->>EE4BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.NE2END2->>IMUX_L36": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.EE2END0->>NN2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.NR1END1->>IMUX_L34": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.SE2END1->>SL1BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.EE2END2->>NE6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.LV_L9->>SS6BEG1": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L24": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.WL1END0->>SR1BEG1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.SS6END1->>SW6BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L6": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.LOGIC_OUTS_L14->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.LOGIC_OUTS_L4->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.NR1END0->>NR1BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.NN6END1->>WW4BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.SE2END1->>SW6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.FAN_BOUNCE_S3_4->>BYP_ALT3": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.SW2END2->>IMUX_L6": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.LOGIC_OUTS_L7->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.SW6END1->>SE6BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.NN2END0->>WR1BEG1": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L33": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.VCC_WIRE->>IMUX_L45": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.EE2END1->>BYP_ALT4": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.SS2END1->>SL1BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.SL1END2->>IMUX_L4": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.NE2END2->>EE4BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L11": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.WL1END1->>IMUX_L43": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.SR1END2->>BYP_ALT3": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.SL1END2->>SW2BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.EE4END1->>SS6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.NE2END3->>IMUX_L7": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.WR1END0->>NL1BEG_N3": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L18->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L20": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.EE2END0->>NN6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.GCLK_L_B3->>GFAN1": { + "src_wire": "GCLK_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.LOGIC_OUTS_L19->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.SW2END3->>EE4BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.EE2END0->>IMUX_L32": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.LOGIC_OUTS_L3->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.NW2END3->>WL1BEG1": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.NW2END3->>SR1BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.NE6END1->>EL1BEG0": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.LOGIC_OUTS_L3->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.GCLK_L_B7_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B7_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.EE4END1->>EE2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.NN6END2->>NW6BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.SR1BEG_S0->>IMUX_L33": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.FAN_BOUNCE1->>FAN_ALT5": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L31": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.EL1END3->>ER1BEG_S0": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.SR1END2->>WW2BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.LOGIC_OUTS_L12->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.EE4END2->>NE2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.EE2END2->>BYP_ALT2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.ER1END1->>IMUX_L42": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.EE4END2->>NE6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L44": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.NW6END0->>NW6BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.SS6END0->>SS6BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.GCLK_L_B2->>CLK_L1": { + "src_wire": "GCLK_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.LOGIC_OUTS_L6->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L29": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.NW6END_S0_0->>SS6BEG3": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.EE2END3->>IMUX_L31": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.EE2END0->>FAN_ALT4": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.NE2END3->>IMUX_L14": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.NW2END0->>IMUX_L0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.NR1END1->>NL1BEG0": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.SS6END2->>SS2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L32": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.LOGIC_OUTS_L12->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.VCC_WIRE->>BYP_ALT3": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.SE2END2->>IMUX_L5": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.SL1END2->>WL1BEG1": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L39": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.SW6END2->>WL1BEG1": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.SW2END2->>NW6BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.LOGIC_OUTS_L13->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.LOGIC_OUTS_L19->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.NN2END_S2_0->>SR1BEG_S0": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.VCC_WIRE->>FAN_ALT4": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.NW2END1->>IMUX_L17": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.SR1BEG_S0->>ER1BEG1": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.NN2END3->>IMUX_L38": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.LOGIC_OUTS_L4->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.SS2END0->>IMUX_L18": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.WL1END2->>SW2BEG2": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.EE2END0->>BYP_ALT0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.LOGIC_OUTS_L16->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.NW2END3->>IMUX_L46": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.NE2END1->>IMUX_L34": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L6->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L35": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.SR1END_N3_3->>FAN_ALT0": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.BYP_BOUNCE_N3_7->>BYP_ALT4": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.WW4END1->>NL1BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.NE6END1->>NN2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.NR1END3->>NR1BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.LOGIC_OUTS_L4->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.SE6END2->>WL1BEG1": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.SS2END3->>IMUX_L15": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.SE2END3->>SW2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.NN6END2->>NE6BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.WW2END0->>WW2BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L23": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.SE2END2->>EE4BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.ER1END1->>CLK_L0": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.FAN_ALT7->>FAN_L7": { + "src_wire": "FAN_ALT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_L7" + }, + "INT_L.NE2END1->>NW2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.SS2END2->>IMUX_L36": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.WW2END1->>IMUX_L19": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.WR1END3->>SR1BEG3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.FAN_BOUNCE1->>CTRL_L1": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.WL1END0->>WL1BEG_N3": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.NE2END_S3_0->>IMUX_L39": { + "src_wire": "NE2END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.NE2END2->>IMUX_L5": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.LOGIC_OUTS_L2->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.SE2END3->>ER1BEG_S0": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.NW2END1->>EL1BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.EL1END1->>IMUX_L18": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.EE2END3->>WR1BEG_S0": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.LOGIC_OUTS_L11->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.LOGIC_OUTS_L9->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.LH12->>WW4BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.EE2END0->>ER1BEG1": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.NR1END2->>IMUX_L37": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.NN6END3->>WW4BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.SR1END_N3_3->>IMUX_L24": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.EL1END1->>IMUX_L2": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.SR1BEG_S0->>BYP_ALT1": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.WR1END0->>LV_L18": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.NN2END1->>NL1BEG0": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.ER1END0->>BYP_ALT1": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.LOGIC_OUTS_L7->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.FAN_BOUNCE2->>FAN_ALT4": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.GFAN0->>IMUX_L41": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SW2END2->>NL1BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.LOGIC_OUTS_L18->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.SS2END0->>IMUX_L1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.LOGIC_OUTS_L13->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.SE2END3->>NN6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.LOGIC_OUTS_L14->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.LOGIC_OUTS_L20->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.GFAN0->>IMUX_L17": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.LOGIC_OUTS_L0->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.NN2END0->>IMUX_L9": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.NE6END3->>NE6BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.NW2END_S0_0->>WW2BEG3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.LOGIC_OUTS_L21->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.GFAN0->>IMUX_L11": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.NL1END_S3_0->>IMUX_L31": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.LOGIC_OUTS_L9->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.NE6END1->>WR1BEG2": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.NW2END1->>BYP_ALT4": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.SE6END0->>NE6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.LOGIC_OUTS_L14->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.SW6END2->>WW2BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.LVB_L12->>EE4BEG2": { + "src_wire": "LVB_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.SS2END2->>SE6BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.BYP_BOUNCE2->>BYP_ALT7": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.SE2END1->>SS6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.GFAN1->>FAN_ALT7": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.SE2END2->>SE6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.WL1END3->>IMUX_L30": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.SE6END1->>NN6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L41": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.LOGIC_OUTS_L10->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.LOGIC_OUTS_L10->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.SW6END0->>SL1BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.EE2END2->>IMUX_L29": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.LV_L0->>NE6BEG0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.WW2END0->>IMUX_L41": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.LOGIC_OUTS_L19->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.LOGIC_OUTS_L6->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.NE6END2->>WR1BEG3": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.SW2END1->>SE2BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.SS2END1->>IMUX_L20": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.SS6END2->>WW4BEG3": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.LOGIC_OUTS_L8->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.NN6END3->>WR1BEG_S0": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L27": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.SE2END3->>SE2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L40": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NN2END0->>NL1BEG_N3": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.SR1END_N3_3->>IMUX_L8": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.SL1END0->>IMUX_L24": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.SE6END0->>SW6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.VCC_WIRE->>IMUX_L26": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.NE6END1->>SL1BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.WR1END2->>NL1BEG1": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L23": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.NR1END3->>IMUX_L46": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.LOGIC_OUTS_L2->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L35": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.ER1END0->>EL1BEG_N3": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.EE4END1->>NN6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.NW6END3->>SS6BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L9": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.ER1END2->>NR1BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L17": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.LV_L18->>WW4BEG3": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.GFAN0->>IMUX_L24": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.SE6END2->>EE2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.WR1END3->>IMUX_L6": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.SE2END2->>WL1BEG1": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.NN6END2->>SE6BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.NW6END0->>EL1BEG_N3": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L5": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.EE2END3->>NN2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.BYP_BOUNCE4->>BYP_ALT5": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.ER1END0->>FAN_ALT4": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.LOGIC_OUTS_L23->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.LOGIC_OUTS_L5->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L5": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.SW6END3->>LH12": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.ER1END0->>SE2BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.LOGIC_OUTS_L6->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.EE2END0->>IMUX_L33": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.SE2END0->>IMUX_L32": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.NW2END1->>SW6BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.SR1END1->>IMUX_L44": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.NE2END2->>IMUX_L28": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.SS2END3->>BYP_ALT6": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SW6END0->>ER1BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.EL1END0->>IMUX_L32": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.SR1END2->>IMUX_L38": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.EE2END0->>IMUX_L17": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.NE2END1->>NE2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.SR1END_N3_3->>BYP_ALT0": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.LOGIC_OUTS_L14->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.NN2END1->>IMUX_L3": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.LOGIC_OUTS_L11->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.ER1END0->>IMUX_L9": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.NL1BEG_N3->>IMUX_L38": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.ER1END0->>IMUX_L41": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SS6END1->>NR1BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.NL1END1->>IMUX_L42": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.SE6END1->>SE6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.SS2END0->>FAN_ALT4": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.SS6END0->>SL1BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.NW2END0->>FAN_ALT0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.LOGIC_OUTS_L15->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.LOGIC_OUTS_L0->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.EL1END3->>IMUX_L30": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.NE6END2->>WW4BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.SR1END1->>IMUX_L19": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.VCC_WIRE->>IMUX_L3": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.NN2END2->>NE6BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L14": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.NE6END1->>SE6BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.WL1END_N1_3->>IMUX_L0": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.EE2END3->>FAN_ALT3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.SW6END3->>LH0": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.SE2END3->>IMUX_L14": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LOGIC_OUTS_L7->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.WW2END3->>SW6BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.EE4END2->>SL1BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.WR1END1->>IMUX_L19": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.SS6END3->>SS2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.LOGIC_OUTS_L19->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.NL1END2->>IMUX_L20": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.NR1END3->>NL1BEG2": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.WL1END2->>WR1BEG_S0": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.LH12->>LVB_L12": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.LH6->>NE6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.FAN_BOUNCE_S3_0->>BYP_ALT6": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.NN2END0->>IMUX_L40": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L4": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.GCLK_L_B8_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B8_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.LOGIC_OUTS_L12->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.SW6END3->>WL1BEG2": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.LOGIC_OUTS_L11->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.NL1END1->>IMUX_L26": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.NN2END2->>NN2BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.LOGIC_OUTS_L0->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.NR1END0->>IMUX_L41": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SS2END2->>SE2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.NE2END1->>IMUX_L42": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.NL1END1->>IMUX_L17": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.WW2END0->>SS2BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.NL1BEG_N3->>IMUX_L14": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.NR1END3->>IMUX_L6": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NE6END1->>NW2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.SL1END1->>BYP_ALT5": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.LOGIC_OUTS_L11->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.SE2END2->>IMUX_L45": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.SE2END1->>SS2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.LOGIC_OUTS_L4->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.LOGIC_OUTS_L9->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.SS6END2->>NW6BEG3": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.SW2END2->>BYP_ALT2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.SR1END2->>IMUX_L13": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.WW2END0->>IMUX_L10": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.SE2END3->>FAN_ALT1": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.SL1END0->>SW2BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.NN2END1->>IMUX_L18": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.SS2END1->>NR1BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.LH6->>NN6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.LOGIC_OUTS_L11->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.VCC_WIRE->>FAN_ALT3": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.NE6END2->>SE2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.LOGIC_OUTS_L9->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.SE2END3->>WL1BEG2": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.LOGIC_OUTS_L1->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.NN2END3->>EL1BEG2": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.SR1END2->>FAN_ALT5": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.NR1END2->>IMUX_L4": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.SW2END3->>WW2BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.NW2END3->>NE6BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.LOGIC_OUTS_L3->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.EE2END2->>SS6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.SR1END1->>IMUX_L4": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.LOGIC_OUTS_L22->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.NL1BEG_N3->>NR1BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.NN6END0->>NW6BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.NE2END0->>EE4BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.EE4END1->>NE6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.EE2END3->>BYP_ALT7": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.EL1END0->>FAN_ALT0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L23": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.NN2END1->>IMUX_L11": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.GFAN1->>IMUX_L46": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.LOGIC_OUTS_L18->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.NE6END0->>NW6BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.SW6END2->>LVB_L12": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.SW2END3->>IMUX_L7": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.GCLK_L_B1->>GFAN0": { + "src_wire": "GCLK_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.NR1END3->>IMUX_L22": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.NE2END1->>NW6BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.SW2END2->>WW2BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.LV_L18->>NE6BEG3": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.LOGIC_OUTS_L14->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.LOGIC_OUTS_L7->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.GFAN1->>IMUX_L4": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.NE2END1->>IMUX_L11": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.NN2END0->>EE2BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.NL1BEG_N3->>IMUX_L29": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.SE6END3->>EE2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.LOGIC_OUTS_L0->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.WR1END_S1_0->>BYP_ALT7": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.SL1END0->>SR1BEG1": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.FAN_ALT7->>FAN_BOUNCE7": { + "src_wire": "FAN_ALT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE7" + }, + "INT_L.SL1END2->>SS2BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.GFAN0->>IMUX_L9": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.SS6END_N0_3->>NW6BEG0": { + "src_wire": "SS6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.LOGIC_OUTS_L22->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L3": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.LOGIC_OUTS_L11->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.WL1END0->>FAN_ALT2": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.LOGIC_OUTS_L6->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L1": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.NW2END3->>IMUX_L5": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.LOGIC_OUTS_L7->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.WL1END_N1_3->>NN2BEG0": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.NL1END1->>NN2BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L43": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.LOGIC_OUTS_L20->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.FAN_ALT3->>FAN_BOUNCE3": { + "src_wire": "FAN_ALT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE3" + }, + "INT_L.SW2END1->>IMUX_L20": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.SL1END1->>SL1BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.LOGIC_OUTS_L22->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.SW6END0->>NW6BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.LOGIC_OUTS_L14->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.LOGIC_OUTS_L13->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.NW6END1->>SR1BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.SS2END_N0_3->>NW6BEG0": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.EE2END3->>SW6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.NE2END0->>FAN_ALT4": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.NN2END2->>BYP_ALT2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.NE2END3->>SL1BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L34": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L17->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.SW6END1->>CTRL_L0": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.WW2END1->>IMUX_L3": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.NW2END1->>IMUX_L26": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.SE6END1->>EL1BEG0": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.NN2END0->>NW2BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.SW2END3->>IMUX_L38": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.LOGIC_OUTS_L17->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.NW2END0->>IMUX_L16": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.GFAN1->>BYP_ALT3": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.NL1END1->>IMUX_L10": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.LOGIC_OUTS_L12->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.WW2END_N0_3->>IMUX_L0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.NE6END0->>SE6BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.SE6END2->>ER1BEG3": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SE6END3->>SS2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.NW2END3->>IMUX_L30": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.WR1END0->>IMUX_L16": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.SL1END1->>SS2BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.SE6END2->>SE6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.EE2END3->>NE6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.SE2END0->>EL1BEG_N3": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.SS6END1->>WL1BEG0": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.NE6END3->>NL1BEG2": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.WL1END1->>BYP_ALT4": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.LOGIC_OUTS_L18->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.NL1END1->>IMUX_L1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.NE2END1->>BYP_ALT4": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.GCLK_L_B5->>GFAN1": { + "src_wire": "GCLK_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.LOGIC_OUTS_L22->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L11": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.GCLK_L_B10->>GCLK_L_B10_EAST": { + "src_wire": "GCLK_L_B10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B10_EAST" + }, + "INT_L.FAN_ALT1->>FAN_BOUNCE1": { + "src_wire": "FAN_ALT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE1" + }, + "INT_L.WL1END1->>IMUX_L11": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.WL1END_N1_3->>IMUX_L8": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.WW4END1->>SR1BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.LOGIC_OUTS_L15->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.WW4END_S0_0->>WW2BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.NL1END2->>IMUX_L11": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.WW2END2->>IMUX_L45": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.NL1BEG_N3->>WR1BEG_S0": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.LV_L0->>NN6BEG0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.NW2END1->>WW2BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.NW6END0->>NN2BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L41": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.FAN_BOUNCE3->>BYP_ALT3": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.VCC_WIRE->>IMUX_L2": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.WW2END2->>IMUX_L5": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.NN6END2->>NL1BEG1": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.LOGIC_OUTS_L15->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.SW6END3->>SE2BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.NR1END2->>IMUX_L36": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.BYP_BOUNCE1->>BYP_ALT4": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.NW2END1->>WR1BEG2": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L40": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.WW2END2->>IMUX_L14": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.BYP_ALT3->>BYP_L3": { + "src_wire": "BYP_ALT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_L3" + }, + "INT_L.SW2END0->>SE2BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.LOGIC_OUTS_L17->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.SS2END2->>FAN_ALT1": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.NW6END0->>NL1BEG_N3": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.NW2END1->>IMUX_L2": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.NW6END_S0_0->>WL1BEG2": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.NL1END1->>BYP_ALT1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.SS2END1->>WL1BEG0": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.SE2END2->>BYP_ALT3": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.NN6END1->>WR1BEG2": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.SL1END0->>ER1BEG1": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.SE2END3->>EL1BEG2": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.SL1END2->>IMUX_L13": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.NL1END0->>IMUX_L8": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.NE2END2->>NW2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.SR1END1->>IMUX_L35": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.WW4END3->>SW6BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.BYP_BOUNCE2->>BYP_ALT3": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.WR1END1->>IMUX_L2": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.LOGIC_OUTS_L16->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.BYP_BOUNCE_N3_2->>FAN_ALT0": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.NN6END3->>WW2BEG2": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L10": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L44": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.NN2END2->>SR1BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.NR1END0->>IMUX_L9": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.LOGIC_OUTS_L17->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.SR1END2->>IMUX_L30": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.ER1END3->>ER1BEG_S0": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.LOGIC_OUTS_L2->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.NW6END3->>WR1BEG_S0": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.SL1END0->>IMUX_L1": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.LOGIC_OUTS_L23->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.ER1END0->>IMUX_L25": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.LOGIC_OUTS_L5->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.WW2END0->>NL1BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.NL1END0->>WR1BEG1": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.LOGIC_OUTS_L17->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L2": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.WW2END1->>ER1BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.NW2END2->>BYP_ALT2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L27": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.EE2END0->>IMUX_L9": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L6": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NE6END0->>NN2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.WL1END1->>NL1BEG1": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.SL1END1->>ER1BEG2": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.SE2END1->>SW2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.LOGIC_OUTS_L7->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.EL1END1->>IMUX_L11": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.SE6END1->>SS2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.NL1END2->>NR1BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.WW2END1->>NL1BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.EE2END1->>SS2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.SE2END2->>SL1BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.ER1END0->>FAN_ALT2": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.LV_L0->>SW6BEG0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L22": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.LOGIC_OUTS_L12->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.NE6END3->>NW6BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.SS2END0->>WW2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.NN2END3->>IMUX_L6": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.SL1END3->>IMUX_L15": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.EE4END3->>NE6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.GND_WIRE->>GFAN1": { + "src_wire": "GND_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.SS6END0->>SW2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.NE2END1->>EL1BEG0": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.SW6END3->>SW2BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.SS6END2->>SW2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.WR1END0->>NN2BEG0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.LOGIC_OUTS_L8->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.EL1END3->>IMUX_L22": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.LOGIC_OUTS_L1->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.LH12->>LVB_L0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.LOGIC_OUTS_L17->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.LOGIC_OUTS_L4->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.BYP_BOUNCE0->>FAN_ALT2": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L8": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.EE2END1->>IMUX_L35": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.WR1END3->>IMUX_L38": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L40": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.LOGIC_OUTS_L2->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.NW2END1->>FAN_ALT2": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.LOGIC_OUTS_L10->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.NW2END2->>NW6BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.WL1END2->>BYP_ALT3": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.NR1END3->>IMUX_L7": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.SE2END0->>NE6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.NE2END2->>IMUX_L13": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.NE2END2->>BYP_ALT2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.FAN_BOUNCE1->>CTRL_L0": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.SE6END3->>SE2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.NE2END3->>NR1BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L5": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.WL1END0->>IMUX_L40": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NR1END2->>FAN_ALT5": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.WW2END2->>IMUX_L6": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.EE4END2->>CTRL_L1": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.SS2END3->>IMUX_L23": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.WW4END_S0_0->>SW6BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.NW6END3->>WW2BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.NN2END2->>NL1BEG1": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.SR1BEG_S0->>FAN_ALT2": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.SS2END0->>BYP_ALT0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.LOGIC_OUTS_L10->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L13": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.NW2END_S0_0->>IMUX_L7": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.LOGIC_OUTS_L17->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.LOGIC_OUTS_L5->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.LOGIC_OUTS_L2->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.LOGIC_OUTS_L20->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.LOGIC_OUTS_L21->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.EE2END2->>WR1BEG3": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.NW2END1->>IMUX_L25": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L18": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.EE2END3->>SL1BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.WW2END1->>SW2BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.BYP_BOUNCE4->>BYP_ALT3": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.GFAN1->>IMUX_L5": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.WW2END2->>IMUX_L30": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.SE2END1->>WL1BEG0": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L4": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.EE2END0->>IMUX_L8": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.VCC_WIRE->>IMUX_L37": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.LOGIC_OUTS_L14->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.NN2END1->>EL1BEG0": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.SS2END2->>FAN_ALT5": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.SE6END0->>SL1BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L26": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L21": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.LOGIC_OUTS_L11->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L46": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.LOGIC_OUTS_L13->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.NR1END0->>IMUX_L8": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.WW4END0->>NW6BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.LOGIC_OUTS_L20->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.EE2END2->>IMUX_L12": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.WW2END3->>FAN_ALT3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.SE6END3->>NN6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.NE2END_S3_0->>IMUX_L31": { + "src_wire": "NE2END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.EE4END2->>SE6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L9": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.LOGIC_OUTS_L11->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.LOGIC_OUTS_L17->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.LOGIC_OUTS_L21->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.NE2END2->>NN2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L23": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.SE2END1->>IMUX_L18": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.NE2END2->>NR1BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.BYP_ALT4->>BYP_BOUNCE4": { + "src_wire": "BYP_ALT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE4" + }, + "INT_L.SR1END3->>WW2BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.NR1END1->>BYP_ALT5": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.SS2END1->>FAN_ALT7": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.VCC_WIRE->>IMUX_L41": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L21": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.ER1END2->>IMUX_L29": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L30": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.LOGIC_OUTS_L10->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.LOGIC_OUTS_L4->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.NW6END2->>WR1BEG3": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.NL1END_S3_0->>IMUX_L15": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L25": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NR1END3->>LVB_L0": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.SE2END1->>EE2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.EL1END1->>BYP_ALT1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.NW2END0->>WR1BEG1": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.WR1END_S1_0->>IMUX_L47": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.LOGIC_OUTS_L17->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.NN2END3->>NW2BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.SE2END3->>LVB_L12": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L10": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.FAN_BOUNCE7->>FAN_ALT6": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L11": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.SE2END2->>IMUX_L12": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.NN2END0->>WW4BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.SE6END3->>SW6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.SW2END0->>WW4BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.EE2END0->>EE2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L18": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.NE2END1->>IMUX_L41": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SR1END_N3_3->>IMUX_L0": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.LOGIC_OUTS_L2->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L37": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.GFAN0->>IMUX_L34": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L23->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.SW6END1->>SE2BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.SE2END0->>SW6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.EL1END_S3_0->>IMUX_L47": { + "src_wire": "EL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.LOGIC_OUTS_L3->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.NL1END1->>WR1BEG2": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.LV_L18->>LVB_L0": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.EL1END2->>ER1BEG3": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.WW2END2->>SS6BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.EE2END2->>IMUX_L4": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.LV_L9->>NW6BEG1": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.WL1END1->>IMUX_L34": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L21->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.LOGIC_OUTS_L9->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.NE6END2->>NE6BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.LOGIC_OUTS_L14->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.LOGIC_OUTS_L23->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.WL1END2->>IMUX_L44": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.VCC_WIRE->>IMUX_L47": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.LOGIC_OUTS_L15->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L39": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.SR1END1->>CLK_L0": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.FAN_BOUNCE5->>FAN_ALT2": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.LOGIC_OUTS_L13->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.SE6END2->>SS6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.NN2END1->>NN2BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.NR1END3->>NE2BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.LOGIC_OUTS_L19->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.NW6END3->>NL1BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.EE2END1->>WR1BEG2": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.NR1END0->>IMUX_L1": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.GFAN1->>IMUX_L36": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.BYP_BOUNCE5->>BYP_ALT2": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.SW2END1->>IMUX_L12": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.SW6END1->>SR1BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.NE6END2->>EL1BEG1": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.LOGIC_OUTS_L21->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.NE2END2->>IMUX_L4": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.NE2END3->>BYP_ALT3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.EE2END1->>IMUX_L43": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.SR1END2->>CTRL_L0": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.GCLK_L_B8->>GCLK_L_B8_EAST": { + "src_wire": "GCLK_L_B8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B8_EAST" + }, + "INT_L.NE2END1->>FAN_ALT2": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.SS2END1->>EE2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.LOGIC_OUTS_L3->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.NW2END1->>IMUX_L1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.LOGIC_OUTS_L22->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.ER1END2->>IMUX_L44": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.NL1BEG_N3->>EE2BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.SW2END1->>NW6BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.EL1END0->>SS2BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.SS2END_N0_3->>IMUX_L16": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.LOGIC_OUTS_L10->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.LOGIC_OUTS_L16->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.NN6END0->>NE6BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L14": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LOGIC_OUTS_L17->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.LOGIC_OUTS_L8->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.NN2END3->>IMUX_L23": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.NN6END1->>EE2BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.SR1BEG_S0->>SE2BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.GCLK_L_B8_WEST->>GFAN0": { + "src_wire": "GCLK_L_B8_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.NW6END_S0_0->>SW2BEG3": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.SR1END2->>SR1BEG3": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L20": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.EE2END0->>BYP_ALT1": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.NW6END1->>WL1BEG_N3": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L12->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.LH0->>NE6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.WW4END0->>WR1BEG1": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.LH12->>SE6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.VCC_WIRE->>IMUX_L1": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.SS6END2->>CTRL_L1": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L0": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.EL1END2->>NR1BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.WW2END0->>FAN_ALT2": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.GFAN0->>IMUX_L1": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.SW6END3->>ER1BEG_S0": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.SL1END1->>SW2BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.VCC_WIRE->>IMUX_L44": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.GFAN1->>IMUX_L45": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.NE2END0->>NW6BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.NW2END_S0_0->>IMUX_L47": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.NW2END2->>IMUX_L35": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.LOGIC_OUTS_L4->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.EL1END2->>FAN_ALT7": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.EE2END1->>IMUX_L11": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.SE6END3->>SL1BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.NE6END3->>EL1BEG2": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L13": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.LOGIC_OUTS_L13->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.SS2END0->>IMUX_L10": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.NN2END3->>IMUX_L22": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.FAN_BOUNCE_S3_0->>FAN_ALT3": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L45": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.SR1END3->>IMUX_L31": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.NE6END2->>NN6BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.EE2END0->>IMUX_L25": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NE2END1->>IMUX_L19": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.NW2END2->>NL1BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.SL1END3->>IMUX_L23": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.NR1END2->>IMUX_L21": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.NN6END0->>NL1BEG_N3": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.GCLK_L_B11_WEST->>GFAN1": { + "src_wire": "GCLK_L_B11_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.SL1END0->>IMUX_L32": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.SS6END3->>LH0": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.LH12->>NN6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.EE2END1->>IMUX_L34": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.WL1END_N1_3->>WR1BEG1": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.EE4END1->>SE6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L41": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.LOGIC_OUTS_L21->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.LV_L18->>LVB_L12": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.LOGIC_OUTS_L8->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.SE2END1->>IMUX_L10": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.NR1END0->>FAN_ALT0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.LVB_L0->>SW6BEG2": { + "src_wire": "LVB_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L31": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.SE6END3->>EE4BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.SS2END1->>IMUX_L19": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.SS2END1->>IMUX_L11": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.LOGIC_OUTS_L2->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.SW6END2->>LVB_L0": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.NR1END2->>NL1BEG1": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.EE2END3->>IMUX_L22": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.SS2END1->>IMUX_L26": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.SS6END0->>EE2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L38": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.SW2END0->>NL1BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.NW2END3->>NE2BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.LOGIC_OUTS_L6->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.GFAN0->>IMUX_L26": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.LOGIC_OUTS_L22->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.NN2END3->>NR1BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.GFAN1->>IMUX_L21": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.NL1END0->>BYP_ALT0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NN2END2->>IMUX_L12": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.NN2END1->>NE2BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.WW2END0->>SS6BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.LOGIC_OUTS_L9->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.SS2END1->>SS2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L7": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L32": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.EL1END2->>BYP_ALT2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.LOGIC_OUTS_L19->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.NL1END1->>IMUX_L33": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.NR1END0->>BYP_ALT0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.EE4END3->>NR1BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.ER1END1->>IMUX_L43": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.NW2END1->>SS6BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.NR1END0->>IMUX_L0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.NR1END3->>IMUX_L15": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L45": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.NR1END2->>IMUX_L20": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.BYP_BOUNCE_N3_6->>FAN_ALT2": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.NE2END2->>FAN_ALT5": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.LOGIC_OUTS_L3->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.SS6END1->>SS2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.LH0->>LVB_L0": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.LOGIC_OUTS_L16->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.WR1END2->>SW2BEG1": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.NR1END3->>BYP_ALT7": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.EL1END2->>SS2BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.LOGIC_OUTS_L7->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.NL1END2->>WR1BEG3": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.SR1END1->>SW2BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L3": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.GND_WIRE->>GFAN0": { + "src_wire": "GND_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.VCC_WIRE->>IMUX_L35": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.LOGIC_OUTS_L13->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.NE6END3->>NN2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.ER1END1->>CLK_L1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.EE2END2->>NR1BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.SE2END1->>BYP_ALT5": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.EE2END3->>ER1BEG_S0": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.SS2END2->>IMUX_L45": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.SE2END0->>IMUX_L0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.NE2END2->>BYP_ALT5": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.SW2END1->>SE6BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.LOGIC_OUTS_L2->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.LOGIC_OUTS_L19->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.SE6END2->>CTRL_L0": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.LOGIC_OUTS_L18->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.SE2END1->>FAN_ALT6": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.LOGIC_OUTS_L15->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.NW2END3->>NN2BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.LOGIC_OUTS_L5->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.SW2END2->>IMUX_L36": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.EE2END0->>SW6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.LVB_L0->>NW6BEG2": { + "src_wire": "LVB_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.WW4END_S0_0->>ER1BEG_S0": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.LOGIC_OUTS_L6->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L16": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.SE2END2->>SW6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.LOGIC_OUTS_L12->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.NE6END1->>NR1BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.LOGIC_OUTS_L23->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.NN6END2->>NR1BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.NW6END2->>CTRL_L0": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.EL1END0->>NE2BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.WW4END1->>WL1BEG_N3": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.BYP_BOUNCE_N3_3->>FAN_ALT4": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L38": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.ER1END3->>BYP_ALT7": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.SS2END3->>IMUX_L46": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.WR1END2->>IMUX_L12": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.LOGIC_OUTS_L8->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L42": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.WW2END2->>SS2BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.SW2END1->>NW2BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.NW2END3->>BYP_ALT3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.GCLK_L_B9_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B9_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.SL1END3->>WW2BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.SE6END3->>EL1BEG2": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.LOGIC_OUTS_L4->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.LH6->>EE4BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L20": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.WW4END3->>NE6BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.NL1BEG_N3->>IMUX_L46": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.WR1END3->>FAN_ALT3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.WW2END2->>IMUX_L29": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.BYP_BOUNCE0->>BYP_ALT5": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.SW6END0->>NW2BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.EL1END0->>SL1BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L29": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.SR1BEG_S0->>IMUX_L34": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L19->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.SW2END1->>IMUX_L27": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.SW2END0->>IMUX_L24": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L35": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.WL1END2->>IMUX_L22": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L1": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.NN2END1->>BYP_ALT4": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.GCLK_L_B10_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B10_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.LOGIC_OUTS_L16->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.LOGIC_OUTS_L18->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.SE2END0->>SL1BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.NE2END3->>IMUX_L38": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.GFAN0->>IMUX_L3": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.LOGIC_OUTS_L21->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.LOGIC_OUTS_L22->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.WW4END_S0_0->>SS2BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.SL1END0->>IMUX_L9": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.WW4END3->>LVB_L0": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.GFAN0->>IMUX_L33": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.WL1END0->>SW2BEG0": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.NN2END0->>IMUX_L8": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.SE2END3->>SS6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.LOGIC_OUTS_L11->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.LOGIC_OUTS_L0->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.LOGIC_OUTS_L17->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.LOGIC_OUTS_L4->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.SS6END2->>SE6BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.LOGIC_OUTS_L6->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.NE2END2->>IMUX_L44": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.SR1END3->>SW2BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L20": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.SS2END0->>SS6BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.EL1END2->>IMUX_L13": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.EE2END0->>SS2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.LOGIC_OUTS_L21->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.SS2END_N0_3->>WW4BEG0": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.SL1END2->>IMUX_L36": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.BYP_BOUNCE5->>FAN_ALT3": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.NN2END3->>WW4BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.NL1END0->>IMUX_L0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.NN6END_S1_0->>SR1BEG_S0": { + "src_wire": "NN6END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.LOGIC_OUTS_L17->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.NW2END1->>NE6BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.GFAN1->>FAN_ALT5": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.NN6END_S1_0->>WW2BEG3": { + "src_wire": "NN6END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.EE2END2->>BYP_ALT3": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.FAN_ALT2->>FAN_BOUNCE2": { + "src_wire": "FAN_ALT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE2" + }, + "INT_L.SL1END1->>WL1BEG0": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.NL1END1->>IMUX_L25": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.LOGIC_OUTS_L16->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.SW2END_N0_3->>NL1BEG_N3": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.EE2END2->>FAN_ALT5": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.NE2END0->>IMUX_L17": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.LOGIC_OUTS_L16->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L16": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L41": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SS6END1->>SW2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.LOGIC_OUTS_L10->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.LOGIC_OUTS_L19->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.EL1END0->>IMUX_L40": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L24": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.WW2END_N0_3->>NW6BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.NN6END0->>LV_L18": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.LOGIC_OUTS_L8->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.EL1END0->>IMUX_L9": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.LOGIC_OUTS_L5->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.SL1END0->>FAN_ALT4": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.NE2END0->>NW2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.NN6END3->>NL1BEG2": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.NL1BEG_N3->>IMUX_L22": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L39": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.LOGIC_OUTS_L18->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.LOGIC_OUTS_L12->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L16": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.NE2END2->>LVB_L0": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.EL1END2->>EL1BEG1": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.NR1END3->>WR1BEG_S0": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.LOGIC_OUTS_L13->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.ER1END2->>IMUX_L28": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.NE6END1->>EE4BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.ER1END2->>EE2BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.NE2END2->>SE6BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.NL1END0->>IMUX_L16": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.WR1END1->>IMUX_L41": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.NW2END2->>IMUX_L11": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.LOGIC_OUTS_L20->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.WL1END3->>BYP_ALT6": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.EE4END0->>NR1BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.SR1END1->>CLK_L1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.VCC_WIRE->>IMUX_L14": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.SR1BEG_S0->>BYP_ALT4": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.LOGIC_OUTS_L7->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.NL1END_S3_0->>IMUX_L7": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.LOGIC_OUTS_L15->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.SE2END2->>EL1BEG1": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.NW2END2->>NE6BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.WL1END1->>IMUX_L42": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.EL1END_S3_0->>IMUX_L31": { + "src_wire": "EL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.SL1END1->>SE2BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.LOGIC_OUTS_L9->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.SS2END1->>SE6BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L36": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.BYP_ALT6->>BYP_L6": { + "src_wire": "BYP_ALT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_L6" + }, + "INT_L.SE6END0->>NN6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L9": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.WL1END1->>IMUX_L20": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.LOGIC_OUTS_L3->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.SR1END1->>IMUX_L43": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L26": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.SE6END2->>CTRL_L1": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.NL1END2->>NN2BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.NR1END2->>IMUX_L45": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.EE2END2->>IMUX_L21": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.SR1BEG_S0->>IMUX_L26": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L33": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.LOGIC_OUTS_L12->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.NR1END1->>GFAN0": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.EE4END0->>SE2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.NL1END0->>FAN_ALT0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.LVB_L0->>EE4BEG2": { + "src_wire": "LVB_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.LV_L9->>LH0": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.ER1END0->>IMUX_L32": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.ER1END2->>SL1BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.EE4END3->>SS2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.NN6END3->>NN6BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.NR1END2->>IMUX_L13": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.NN2END1->>EE4BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.EE2END3->>IMUX_L14": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LOGIC_OUTS_L15->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.SR1END1->>IMUX_L28": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.SS2END0->>WL1BEG_N3": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.SW2END2->>SS2BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.EL1END1->>BYP_ALT4": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.SL1END0->>IMUX_L16": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L8": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L31": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.NW2END1->>BYP_ALT1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.LOGIC_OUTS_L20->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.GCLK_L_B5->>GFAN0": { + "src_wire": "GCLK_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.ER1END0->>ER1BEG1": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.SW6END1->>SW6BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L18": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.NR1END1->>IMUX_L18": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.SR1END1->>FAN_ALT7": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.NE2END0->>BYP_ALT0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NN6END1->>NN2BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.LOGIC_OUTS_L2->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.NE6END3->>EE4BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.NW2END3->>IMUX_L13": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.SR1END2->>IMUX_L22": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.LOGIC_OUTS_L21->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.SW2END2->>SW6BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L30": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L46": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.LOGIC_OUTS_L19->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.EE2END2->>NE2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.NN2END2->>NN6BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.NW6END1->>NN2BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.GCLK_L_B0->>CLK_L0": { + "src_wire": "GCLK_L_B0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.WR1END2->>IMUX_L43": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.SS2END0->>WW4BEG1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.LOGIC_OUTS_L6->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L12": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.LOGIC_OUTS_L14->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.SL1END3->>FAN_ALT1": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.WR1END2->>NN2BEG2": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.SS6END0->>SE2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.NW2END3->>IMUX_L21": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.NL1BEG_N3->>IMUX_L13": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.LOGIC_OUTS_L8->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.WW4END3->>NW6BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.LOGIC_OUTS_L23->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.NL1BEG_N3->>IMUX_L45": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.SR1BEG_S0->>IMUX_L2": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.EE2END2->>NN6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.NN2END1->>WR1BEG2": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.GCLK_L_B6_WEST->>GFAN1": { + "src_wire": "GCLK_L_B6_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.EE4END3->>NE2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.LOGIC_OUTS_L2->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.SS2END2->>ER1BEG3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SR1END3->>SE2BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.SS2END1->>SW6BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.NL1END2->>IMUX_L36": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.NR1END3->>IMUX_L31": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.EE2END3->>SE6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.EE2END2->>EE2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.NW6END0->>WR1BEG1": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.LOGIC_OUTS_L18->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.SE6END1->>WL1BEG0": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.SE6END2->>SW6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.WR1END2->>WW2BEG1": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.NE2END2->>EL1BEG1": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.EL1END1->>IMUX_L3": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.WW4END3->>SW2BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.NE2END_S3_0->>BYP_ALT7": { + "src_wire": "NE2END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.GFAN1->>IMUX_L38": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.ER1END2->>IMUX_L5": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.NL1END1->>NL1BEG0": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.NR1END1->>NW2BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.NW6END_S0_0->>WW2BEG3": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.LOGIC_OUTS_L20->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.WR1END0->>NW2BEG0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.NW6END2->>NL1BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.LOGIC_OUTS_L11->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.ER1END_N3_3->>IMUX_L8": { + "src_wire": "ER1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.EE2END3->>FAN_ALT1": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.FAN_ALT0->>FAN_L0": { + "src_wire": "FAN_ALT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_L0" + }, + "INT_L.ER1END2->>FAN_ALT1": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.FAN_ALT6->>FAN_BOUNCE6": { + "src_wire": "FAN_ALT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE6" + }, + "INT_L.WR1END0->>IMUX_L40": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.LOGIC_OUTS_L18->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.BYP_BOUNCE_N3_3->>BYP_ALT0": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NN2END2->>WW2BEG1": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.LOGIC_OUTS_L7->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.WW2END2->>WR1BEG_S0": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.SE2END0->>ER1BEG1": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.VCC_WIRE->>IMUX_L12": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.SE2END0->>IMUX_L1": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.SE2END2->>NE2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L21": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.BYP_BOUNCE_N3_6->>FAN_ALT0": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.SR1END_N3_3->>IMUX_L40": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NW2END0->>IMUX_L8": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.SS2END2->>IMUX_L5": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.NL1END0->>IMUX_L40": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L45": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.GCLK_L_B6->>GCLK_L_B6_EAST": { + "src_wire": "GCLK_L_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B6_EAST" + }, + "INT_L.ER1END1->>SE2BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.LOGIC_OUTS_L21->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.WW4END1->>GFAN1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.NN2END0->>NE6BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L3": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.NE6END3->>SL1BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.NE2END2->>FAN_ALT7": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.LOGIC_OUTS_L14->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.NN2END3->>BYP_ALT3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L37": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.LOGIC_OUTS_L4->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.BYP_ALT0->>BYP_BOUNCE0": { + "src_wire": "BYP_ALT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE0" + }, + "INT_L.SR1END1->>IMUX_L3": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.LH12->>SW6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L28": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.LOGIC_OUTS_L17->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.LOGIC_OUTS_L10->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.EE4END3->>SW6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L27": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.NL1END2->>IMUX_L19": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.LVB_L0->>NN6BEG2": { + "src_wire": "LVB_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.NE2END1->>IMUX_L2": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.VCC_WIRE->>BYP_ALT1": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.BYP_BOUNCE_N3_6->>BYP_ALT1": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.GFAN1->>IMUX_L31": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.EE4END2->>NN2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L19": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.LOGIC_OUTS_L0->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.NE2END2->>IMUX_L21": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.EE4END0->>EE4BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.LOGIC_OUTS_L19->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.FAN_BOUNCE3->>FAN_ALT1": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.NW2END3->>IMUX_L37": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.NW6END2->>NE2BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.SW2END_N0_3->>IMUX_L0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.ER1END3->>LH12": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.NR1END3->>IMUX_L39": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.BYP_ALT7->>BYP_L7": { + "src_wire": "BYP_ALT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_L7" + }, + "INT_L.EE2END3->>EE4BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.GFAN0->>IMUX_L27": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.LOGIC_OUTS_L12->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.LOGIC_OUTS_L19->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.NW2END2->>IMUX_L27": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.SR1END1->>IMUX_L11": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.WR1END0->>IMUX_L17": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.SW2END1->>SS2BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.NE2END0->>IMUX_L40": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.WL1END1->>NW2BEG2": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L45": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.EE4END0->>NN2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.LOGIC_OUTS_L5->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.NW2END3->>SS6BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.EE4END3->>SL1BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.LOGIC_OUTS_L5->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.EE4END0->>NE2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.LOGIC_OUTS_L23->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.EE2END2->>IMUX_L37": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.SS6END3->>SL1BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.SS2END1->>IMUX_L27": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.SS6END2->>SR1BEG3": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.LOGIC_OUTS_L1->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.LOGIC_OUTS_L4->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.SL1END1->>FAN_ALT6": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.WR1END3->>BYP_ALT3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.WW4END0->>LV_L18": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.WL1END2->>FAN_ALT1": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.NE6END3->>SE2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.NW2END0->>IMUX_L24": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.SL1END3->>FAN_ALT3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.WR1END1->>NL1BEG0": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.LOGIC_OUTS_L3->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.SW2END0->>EE4BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.VCC_WIRE->>IMUX_L5": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.LOGIC_OUTS_L14->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.NE2END3->>BYP_ALT6": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SS6END1->>NW6BEG2": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.SL1END3->>IMUX_L14": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.SW2END0->>ER1BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.GFAN0->>IMUX_L32": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.SE6END0->>SE6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.WW4END2->>ER1BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L42": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.LOGIC_OUTS_L7->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.LOGIC_OUTS_L23->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L32": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.LV_L18->>EE4BEG3": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.NL1BEG_N3->>IMUX_L5": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.WL1END1->>WR1BEG3": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.SE2END3->>SE6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.SW6END2->>SL1BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.ER1END0->>IMUX_L2": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.LOGIC_OUTS_L0->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.NE2END1->>IMUX_L26": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.ER1END0->>IMUX_L33": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.SE2END0->>BYP_ALT1": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.SR1END2->>IMUX_L6": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.LOGIC_OUTS_L7->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.NW2END3->>LH0": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.WL1END1->>SR1BEG2": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.SW6END2->>SR1BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.WW2END_N0_3->>WW4BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.NW2END0->>NN6BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.LV_L18->>NN6BEG3": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.SS2END1->>BYP_ALT4": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.SW2END1->>IMUX_L35": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.GCLK_L_B11_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B11_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.WW2END_N0_3->>IMUX_L40": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NN2END1->>SR1BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.NN2END0->>NE2BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.NW2END2->>NN6BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.LOGIC_OUTS_L10->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.SE6END1->>NE2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L9": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.LOGIC_OUTS_L7->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.NW2END2->>LVB_L0": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.NN2END1->>NR1BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.SS6END0->>WW4BEG1": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.LOGIC_OUTS_L9->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.SL1END2->>SR1BEG3": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.SL1END0->>SL1BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.ER1END1->>IMUX_L34": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.NN2END1->>NN6BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.WW2END3->>SS2BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.LOGIC_OUTS_L0->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.WW2END1->>IMUX_L11": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.WL1END3->>WL1BEG2": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.EL1END3->>IMUX_L23": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.FAN_ALT4->>FAN_L4": { + "src_wire": "FAN_ALT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_L4" + }, + "INT_L.LH6->>SW6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.LOGIC_OUTS_L15->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.NN2END2->>FAN_ALT7": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.EE4END1->>EE4BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.NW2END3->>IMUX_L45": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.EE4END0->>SW6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.WR1END3->>IMUX_L22": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L34": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L19->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.WR1END0->>FAN_ALT4": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.LOGIC_OUTS_L2->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L17": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.GCLK_L_B8->>GCLK_L_B8_WEST": { + "src_wire": "GCLK_L_B8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B8_WEST" + }, + "INT_L.WW2END0->>IMUX_L2": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.SL1END3->>BYP_ALT7": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.WW4END2->>WW4BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.SW2END3->>IMUX_L23": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.LVB_L0->>SE6BEG2": { + "src_wire": "LVB_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.SW2END1->>IMUX_L43": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.WW2END1->>WR1BEG3": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.NR1END2->>IMUX_L28": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.WR1END2->>IMUX_L21": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.NL1END2->>IMUX_L27": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.VCC_WIRE->>IMUX_L36": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.ER1END0->>LV_L18": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.GCLK_L_B7_WEST->>GFAN1": { + "src_wire": "GCLK_L_B7_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.WW4END2->>NW2BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.EE2END2->>SE6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.NN2END_S2_0->>IMUX_L39": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.LOGIC_OUTS_L2->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L2": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.SS6END0->>NW6BEG1": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.NE6END3->>LH12": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.SS2END3->>SL1BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.SE2END2->>SS2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.NR1END2->>NN2BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.SS2END0->>IMUX_L17": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.VCC_WIRE->>IMUX_L4": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.EE2END0->>NE2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.SE2END1->>SE2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.NW2END0->>IMUX_L40": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.WW2END0->>WL1BEG_N3": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.NE2END0->>WW4BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.NE2END3->>IMUX_L15": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.LOGIC_OUTS_L13->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.LOGIC_OUTS_L2->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L28": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.NE6END1->>NE6BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.WW2END_N0_3->>FAN_ALT0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.WW4END3->>WW4BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.LOGIC_OUTS_L10->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.EE2END1->>IMUX_L27": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.WL1END0->>NW2BEG1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.NN2END2->>IMUX_L27": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.NN2END_S2_0->>WW2BEG3": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L47": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.LH6->>NW6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.WL1END1->>IMUX_L35": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.SR1END2->>ER1BEG3": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.EE4END2->>NR1BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.SE2END0->>IMUX_L24": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.SW6END1->>WL1BEG0": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.SE2END2->>IMUX_L28": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.WW2END1->>IMUX_L36": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.SW2END3->>IMUX_L30": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.SE2END0->>EE2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.LOGIC_OUTS_L7->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.LOGIC_OUTS_L3->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.VCC_WIRE->>IMUX_L0": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.SE6END3->>NE2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.EL1END3->>IMUX_L38": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.EE2END2->>SL1BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.NN2END2->>WR1BEG3": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.SW6END0->>LV_L18": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.NE2END0->>SE6BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.VCC_WIRE->>IMUX_L18": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.SL1END1->>IMUX_L11": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.SW2END2->>IMUX_L14": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.ER1END_N3_3->>IMUX_L16": { + "src_wire": "ER1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.FAN_BOUNCE_S3_0->>FAN_ALT5": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.EL1END3->>NE2BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.SS2END0->>FAN_ALT2": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L21": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.BYP_BOUNCE3->>FAN_ALT3": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L14": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LOGIC_OUTS_L6->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.LOGIC_OUTS_L11->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.EL1END1->>IMUX_L25": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.LOGIC_OUTS_L20->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.NL1END_S3_0->>IMUX_L39": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L28": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.ER1END2->>IMUX_L37": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.NE2END1->>NN2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.NW6END0->>LV_L0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L0" + }, + "INT_L.NR1END1->>IMUX_L43": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.SS2END1->>BYP_ALT5": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.SW2END1->>FAN_ALT6": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.ER1END0->>IMUX_L18": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.SS2END0->>IMUX_L32": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.SE6END0->>SS2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.NL1END0->>NE2BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.WW4END2->>SS6BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.SW2END3->>SS6BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.EE2END3->>IMUX_L7": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.SS2END2->>IMUX_L6": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.SS2END3->>IMUX_L7": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.WW2END1->>IMUX_L4": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.WL1END0->>WW2BEG0": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.NR1END1->>IMUX_L2": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.EE4END1->>SW6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.LOGIC_OUTS_L21->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.WR1END1->>IMUX_L25": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.LOGIC_OUTS_L17->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.EL1END0->>EE2BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.LV_L0<<->>LH12": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.LOGIC_OUTS_L8->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.EE2END0->>IMUX_L41": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SL1END3->>SE2BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.WL1END3->>IMUX_L15": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.SS2END2->>IMUX_L37": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L6": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.WW2END3->>WW2BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.WR1END3->>IMUX_L14": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LOGIC_OUTS_L15->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.EE2END2->>IMUX_L45": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.VCC_WIRE->>IMUX_L13": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L15": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.SW2END1->>BYP_ALT5": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.NN6END0->>WR1BEG1": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.SS6END2->>SL1BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L7": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.WW2END0->>SR1BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.WW2END_N0_3->>WR1BEG1": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.LOGIC_OUTS_L14->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L19": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.FAN_BOUNCE_S3_2->>BYP_ALT6": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L21": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.LOGIC_OUTS_L11->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.SS2END1->>EE4BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L0": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.SE2END3->>IMUX_L7": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.SW6END2->>SE2BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.LH0->>NN6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.WL1END1->>SW2BEG1": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.NL1END0->>NR1BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.WL1END_N1_3->>NW2BEG0": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.WL1END_N1_3->>NL1BEG_N3": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.NL1END1->>EL1BEG0": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L24": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.ER1END3->>IMUX_L7": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L3": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.SE2END3->>IMUX_L31": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.NW6END3->>NE2BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.LV_L0->>LVB_L0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L11": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.NW6END3->>SW6BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.NR1END0->>NW2BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.SS2END1->>FAN_ALT6": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.LOGIC_OUTS_L1->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.NW2END2->>IMUX_L3": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.NE2END0->>WR1BEG1": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.NR1END1->>FAN_ALT2": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L34": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.SE6END1->>NR1BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.LOGIC_OUTS_L9->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.LOGIC_OUTS_L14->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.NL1END2->>EL1BEG1": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.SW2END2->>IMUX_L5": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.LOGIC_OUTS_L14->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L15": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.LOGIC_OUTS_L11->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.GCLK_L_B6->>GCLK_L_B6_WEST": { + "src_wire": "GCLK_L_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B6_WEST" + }, + "INT_L.SW2END_N0_3->>IMUX_L16": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.NE6END1->>EE2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.WW2END1->>IMUX_L27": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.SS2END0->>IMUX_L9": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.SS2END3->>NR1BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.SS2END2->>SR1BEG3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.LOGIC_OUTS_L18->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.NW2END3->>IMUX_L14": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.NN2END3->>IMUX_L46": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.VCC_WIRE->>IMUX_L22": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.LOGIC_OUTS_L23->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.NL1END2->>IMUX_L44": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.LOGIC_OUTS_L8->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.NN2END0->>NN6BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.NW2END2->>SR1BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.WW4END3->>NW2BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.SL1END3->>IMUX_L46": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.LOGIC_OUTS_L20->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.VCC_WIRE->>IMUX_L15": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.SE6END3->>LVB_L12": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.VCC_WIRE->>FAN_ALT5": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L26": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.LOGIC_OUTS_L17->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.NN2END0->>IMUX_L32": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.SE6END3->>SS6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L27": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.SW2END2->>WL1BEG1": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.EE2END3->>NN6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.SS6END3->>SR1BEG_S0": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.GCLK_L_B8_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B8_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.LOGIC_OUTS_L5->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.GCLK_L_B11->>GCLK_L_B11_WEST": { + "src_wire": "GCLK_L_B11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B11_WEST" + }, + "INT_L.NE2END1->>IMUX_L33": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.NN2END2->>NE2BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.NN2END1->>FAN_ALT6": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.NN2END0->>NN2BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.NE2END1->>BYP_ALT1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.SE2END3->>LVB_L0": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.NE2END3->>EL1BEG2": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.LOGIC_OUTS_L6->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.NN6END0->>NW2BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.NL1END1->>BYP_ALT4": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.NW2END2->>IMUX_L36": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.EE2END3->>NE2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L8": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.SL1END3->>IMUX_L39": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.SS6END3->>SW6BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.SW2END3->>ER1BEG_S0": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.SE2END0->>FAN_ALT4": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.SE6END3->>SW2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.LOGIC_OUTS_L9->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.SE2END2->>NE6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L20": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.SW2END3->>SW6BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.ER1END3->>LH0": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.NE2END3->>IMUX_L37": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.NL1END2->>NL1BEG1": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L12": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.LOGIC_OUTS_L18->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.EE2END1->>NE2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.SS6END0->>SS2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.LOGIC_OUTS_L15->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L6": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NN2END_S2_0->>IMUX_L31": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L12": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.NE2END3->>FAN_ALT3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.SE2END1->>BYP_ALT4": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.LOGIC_OUTS_L22->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.SE6END1->>SW2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.LOGIC_OUTS_L23->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.BYP_BOUNCE_N3_7->>FAN_ALT4": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.ER1END0->>NE2BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.EE2END1->>SW6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.WW2END1->>FAN_ALT7": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.WW4END2->>SW6BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.VCC_WIRE->>IMUX_L28": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.FAN_BOUNCE2->>IMUX_L0": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.SW2END1->>IMUX_L42": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.BYP_ALT2->>BYP_BOUNCE2": { + "src_wire": "BYP_ALT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE2" + }, + "INT_L.EL1END0->>IMUX_L24": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.WW2END0->>ER1BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.NW2END0->>EL1BEG_N3": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.VCC_WIRE->>IMUX_L42": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.NW6END1->>NL1BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.NR1END1->>IMUX_L26": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L42": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.LOGIC_OUTS_L10->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L47": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.SL1END0->>IMUX_L41": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.BYP_BOUNCE1->>GFAN1": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.GFAN0->>IMUX_L19": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.LH6->>LV_L18": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.SW6END2->>SS6BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.LOGIC_OUTS_L8->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.NW2END1->>IMUX_L41": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SW6END2->>EE4BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.ER1END3->>EE2BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.WL1END3->>SR1BEG_S0": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.SS6END2->>SS6BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.NN6END2->>NN6BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.VCC_WIRE->>IMUX_L20": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.SW2END1->>IMUX_L19": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.SE6END1->>SW6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.SE6END2->>EE4BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.GFAN1->>IMUX_L14": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LOGIC_OUTS_L22->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L19": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.GCLK_L_B4->>CLK_L0": { + "src_wire": "GCLK_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.SE2END2->>IMUX_L29": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.NE6END0->>SL1BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.ER1END2->>IMUX_L13": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.LOGIC_OUTS_L2->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.SW2END1->>BYP_ALT4": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.NL1BEG_N3->>NL1BEG2": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.NE6END1->>SE2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.NW2END2->>BYP_ALT5": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.LOGIC_OUTS_L4->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.EE4END1->>SS2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L36": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.LOGIC_OUTS_L7->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.EL1END3->>IMUX_L37": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.LOGIC_OUTS_L1->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.NE6END1->>WW4BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.WR1END1->>WW2BEG0": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.LOGIC_OUTS_L5->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.VCC_WIRE->>IMUX_L24": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.NL1BEG_N3->>NN2BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.NE6END2->>NN2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.NW6END3->>NN2BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.NR1END3->>IMUX_L30": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.SE2END3->>BYP_ALT6": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.NN2END3->>WR1BEG_S0": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.GFAN0->>CTRL_L0": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.SS2END3->>WL1BEG2": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.LOGIC_OUTS_L11->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.GCLK_L_B7_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B7_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L34": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.NE2END1->>IMUX_L25": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NW6END2->>SW2BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.NN2END1->>BYP_ALT1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.SE2END3->>FAN_ALT3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.EE4END2->>EL1BEG1": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.NW2END1->>IMUX_L9": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.NN2END3->>IMUX_L30": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.WL1END0->>BYP_ALT1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.WR1END3->>IMUX_L37": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.WL1END3->>IMUX_L47": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.GCLK_L_B7->>GCLK_L_B7_EAST": { + "src_wire": "GCLK_L_B7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B7_EAST" + }, + "INT_L.LOGIC_OUTS_L0->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.EE4END2->>SS6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.NR1END1->>IMUX_L35": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.EE4END2->>SW6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.EL1END0->>ER1BEG1": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.SE2END2->>SW2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.SE2END3->>EE4BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.NN6END3->>NE2BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.WW2END1->>SS2BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.GCLK_L_B9_WEST->>GFAN1": { + "src_wire": "GCLK_L_B9_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.SE2END1->>IMUX_L19": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.SE6END0->>EE4BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.WR1END1->>IMUX_L3": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.WL1END3->>IMUX_L7": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L47": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.LOGIC_OUTS_L13->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.NW6END3->>LVB_L12": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.LOGIC_OUTS_L5->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.LOGIC_OUTS_L22->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.NN2END2->>IMUX_L44": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L5": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.LOGIC_OUTS_L6->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.FAN_BOUNCE5->>CLK_L0": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.LOGIC_OUTS_L16->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.NW2END1->>IMUX_L34": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.SS2END3->>SW6BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.LOGIC_OUTS_L18->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.FAN_ALT5->>FAN_L5": { + "src_wire": "FAN_ALT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_L5" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L37": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.SL1END2->>WW2BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.VCC_WIRE->>IMUX_L21": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.ER1END3->>IMUX_L30": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L4": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.LOGIC_OUTS_L18->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.NN2END2->>IMUX_L5": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.SR1END1->>SR1BEG2": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.LOGIC_OUTS_L13->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.WL1END2->>SR1BEG3": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.SS2END2->>SL1BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.NR1END0->>EL1BEG_N3": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.SL1END0->>BYP_ALT1": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.NW2END1->>SW2BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.NW2END3->>IMUX_L29": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L33": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.FAN_BOUNCE_S3_6->>IMUX_L39": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.WL1END0->>IMUX_L9": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.EE2END1->>NN2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.NE2END1->>NE6BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.NE2END1->>IMUX_L18": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.NR1END1->>IMUX_L27": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.LOGIC_OUTS_L23->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L3": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.LOGIC_OUTS_L13->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.SE2END3->>SW6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.NW6END0->>LV_L18": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.SL1END1->>IMUX_L19": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.SW2END2->>IMUX_L22": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.BYP_BOUNCE5->>FAN_ALT5": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.WR1END_S1_0->>SW2BEG3": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.GCLK_L_B11_WEST->>GFAN0": { + "src_wire": "GCLK_L_B11_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.NN2END2->>IMUX_L13": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.SW2END0->>IMUX_L25": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.SL1END2->>FAN_ALT7": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.NL1END1->>NW2BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.NW2END3->>IMUX_L22": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.WW2END3->>WL1BEG2": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.SR1BEG_S0->>LV_L18": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.LOGIC_OUTS_L21->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.SW2END0->>SW6BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.SW6END1->>ER1BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.NL1END2->>FAN_ALT6": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.NW6END2->>SW6BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L12": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.LOGIC_OUTS_L1->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.LOGIC_OUTS_L8->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.EL1END1->>SL1BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.LOGIC_OUTS_L6->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.NW2END2->>IMUX_L19": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.SW6END_N0_3->>NW6BEG0": { + "src_wire": "SW6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L21": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.SR1END2->>SS2BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.WR1END3->>IMUX_L30": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L29": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.GCLK_L_B10_WEST->>GFAN1": { + "src_wire": "GCLK_L_B10_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.SR1END2->>SL1BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L41": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.NL1END2->>BYP_ALT2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.WR1END1->>WL1BEG_N3": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.EE4END1->>SE2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.NE2END0->>SE2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.NN2END3->>IMUX_L14": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.SE2END3->>BYP_ALT7": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.SL1END1->>IMUX_L43": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.NW2END0->>NW2BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.EE4END0->>EE2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.SL1END1->>IMUX_L34": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.NN2END3->>NE6BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.SE2END0->>BYP_ALT0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NW2END1->>NL1BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.SE2END0->>IMUX_L40": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NE2END1->>EE2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.GCLK_L_B10_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B10_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.WL1END1->>IMUX_L4": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.LOGIC_OUTS_L16->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.EL1END2->>EE2BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.SS6END3->>WW2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.NE2END3->>NE6BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.SR1END1->>IMUX_L36": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.SE2END1->>IMUX_L3": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.SR1END3->>WL1BEG2": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.WW4END1->>SW2BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.LOGIC_OUTS_L9->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.NN2END1->>IMUX_L19": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.FAN_ALT2->>FAN_L2": { + "src_wire": "FAN_ALT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_L2" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L9": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.SS6END0->>SE6BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.LOGIC_OUTS_L2->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.SE6END2->>EL1BEG1": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.NN2END2->>IMUX_L43": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L24": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.WL1END2->>BYP_ALT2": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.ER1END1->>NR1BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.SW2END3->>BYP_ALT7": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.NR1END1->>IMUX_L42": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.ER1END2->>IMUX_L22": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.EE2END1->>EE2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.EL1END0->>IMUX_L17": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.NW6END3->>LVB_L0": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.WL1END2->>IMUX_L28": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.SE6END1->>EE2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L1": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.LOGIC_OUTS_L2->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.LOGIC_OUTS_L23->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.NN2END0->>IMUX_L16": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.NW2END3->>WR1BEG_S0": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.NN2END2->>IMUX_L35": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.SE2END2->>IMUX_L13": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.LH0->>SW6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.NN2END1->>WW4BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.SS2END0->>SS2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.GFAN1->>IMUX_L20": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.LOGIC_OUTS_L0->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.SE6END0->>SE2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.SS2END2->>BYP_ALT2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.FAN_BOUNCE_S3_4->>FAN_ALT1": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.GFAN0->>IMUX_L2": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.SE2END1->>IMUX_L34": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.ER1END2->>BYP_ALT3": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.ER1END3->>FAN_ALT3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.WL1END0->>IMUX_L10": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.ER1END3->>IMUX_L38": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L42": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.WW2END1->>IMUX_L12": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L33": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L2": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.WW2END0->>IMUX_L18": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L22": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.GFAN0->>FAN_ALT4": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.LOGIC_OUTS_L21->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L27": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.NL1END0->>NL1BEG_N3": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.WW2END0->>IMUX_L34": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.NL1END0->>IMUX_L24": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.LH6->>LV_L0": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L0" + }, + "INT_L.EE2END2->>NN2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.NE2END3->>IMUX_L23": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.LOGIC_OUTS_L21->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.WL1END0->>IMUX_L24": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.NE2END3->>IMUX_L30": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.NE6END0->>WW4BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.SE2END3->>IMUX_L39": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.WL1END2->>IMUX_L29": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.NE6END2->>CTRL_L1": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.GCLK_L_B0->>GFAN1": { + "src_wire": "GCLK_L_B0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.ER1END1->>IMUX_L12": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.NW2END2->>IMUX_L20": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L5": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L10": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.ER1END1->>IMUX_L4": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.SW6END2->>ER1BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.LOGIC_OUTS_L15->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.NW2END_S0_0->>IMUX_L23": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.NW2END3->>IMUX_L38": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.LOGIC_OUTS_L3->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.GCLK_L_B9_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B9_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.NW2END1->>NW2BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.EE2END2->>SW6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.WW2END1->>IMUX_L28": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.EL1END3->>IMUX_L46": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.WR1END1->>IMUX_L26": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.SS6END3->>NR1BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.NR1END0->>IMUX_L32": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.NL1END2->>EE2BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.NW2END3->>FAN_ALT1": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.NE6END1->>NW6BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.NW2END2->>SS6BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.VCC_WIRE->>IMUX_L19": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.SR1BEG_S0->>IMUX_L17": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.SW2END3->>LVB_L12": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.SS6END2->>EE4BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.LV_L0->>WW4BEG0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.WW4END1->>NW2BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.WW2END2->>NW2BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.LOGIC_OUTS_L2->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.EE4END3->>SE2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L36": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.NW6END2->>WW4BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.SE2END1->>ER1BEG2": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L46": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.WR1END0->>IMUX_L0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.SE2END0->>SW2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L44": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L6": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.ER1END3->>BYP_ALT6": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.LOGIC_OUTS_L7->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.NE2END3->>IMUX_L22": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.ER1END1->>SL1BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.SS2END3->>SE2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.LV_L0->>LVB_L12": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.GCLK_L_B2->>CLK_L0": { + "src_wire": "GCLK_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.WW2END2->>SW6BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.SS2END3->>SS2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L13": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.SW6END0->>NL1BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L31": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.SL1END3->>IMUX_L47": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.ER1END3->>IMUX_L15": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.SS2END1->>SE2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.ER1END2->>IMUX_L21": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.SR1BEG_S0->>IMUX_L25": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.WR1END3->>NL1BEG2": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.WL1END0->>FAN_ALT4": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.SL1END1->>WW2BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.WW4END2->>NN2BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.LVB_L12->>SW6BEG2": { + "src_wire": "LVB_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.NR1END0->>IMUX_L16": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.EE2END3->>EL1BEG2": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.NL1BEG_N3->>FAN_ALT1": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.WR1END2->>BYP_ALT2": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.SR1BEG_S0->>LV_L0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L0" + }, + "INT_L.SR1END3->>LH0": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.NR1END0->>IMUX_L17": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.LOGIC_OUTS_L0->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.NN6END1->>EL1BEG0": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.NE2END3->>NE2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.WL1END3->>IMUX_L46": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.NN2END1->>SE6BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.WW2END0->>NE6BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.WW4END1->>SS2BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.EE2END0->>IMUX_L40": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NW2END1->>IMUX_L18": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.GFAN1->>IMUX_L15": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.WR1END3->>BYP_ALT6": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L35": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.LOGIC_OUTS_L10->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.LH12->>NW6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.LOGIC_OUTS_L7->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.SL1END0->>IMUX_L17": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.WW4END1->>WW4BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.SE2END2->>NR1BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.NW2END2->>WW2BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.WR1END0->>BYP_ALT0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NN2END3->>SE6BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.LOGIC_OUTS_L10->>EE2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L22": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.EL1END1->>IMUX_L34": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.GFAN1->>IMUX_L7": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.EL1END_S3_0->>BYP_ALT7": { + "src_wire": "EL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.SE6END1->>NE6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L20": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.NE6END0->>NW2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.LOGIC_OUTS_L1->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L7": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.LOGIC_OUTS_L19->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.NN2END2->>EE4BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.LOGIC_OUTS_L6->>SS2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.NE2END0->>IMUX_L0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.WR1END2->>IMUX_L20": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.LOGIC_OUTS_L23->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.EL1END1->>IMUX_L19": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.EL1END2->>FAN_ALT5": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.NE2END0->>IMUX_L32": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.WR1END0->>IMUX_L1": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.GCLK_L_B3->>CLK_L1": { + "src_wire": "GCLK_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.NR1END0->>EE2BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.SS2END1->>IMUX_L35": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.LOGIC_OUTS_L3->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.SR1END3->>SR1BEG_S0": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.EE2END2->>FAN_ALT7": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.SE2END1->>NR1BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.LOGIC_OUTS_L12->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.WR1END_S1_0->>IMUX_L31": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L46": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.WW4END2->>NL1BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.SW6END1->>CTRL_L1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.WR1END2->>IMUX_L35": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.EL1END1->>FAN_ALT2": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.WR1END1->>BYP_ALT1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.NL1END1->>EE2BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.LOGIC_OUTS_L15->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.WW2END1->>FAN_ALT6": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.SS2END1->>IMUX_L43": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.NL1END2->>BYP_ALT5": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.SR1BEG_S0->>IMUX_L1": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.LOGIC_OUTS_L16->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.SR1END1->>IMUX_L27": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.WW2END2->>NN6BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.LOGIC_OUTS_L10->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.SE6END0->>NE2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.LOGIC_OUTS_L1->>NR1BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.NE2END3->>WW4BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.NW2END_S0_0->>IMUX_L31": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.NN2END1->>IMUX_L33": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.WW4END2->>CTRL_L0": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.LH6->>WW4BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.NL1END2->>FAN_ALT7": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.NE2END0->>EE2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.LOGIC_OUTS_L21->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.BYP_BOUNCE2->>FAN_ALT1": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.NN2END0->>IMUX_L0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.EE2END0->>FAN_ALT0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.NN2END2->>NW6BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L18": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.BYP_ALT4->>BYP_L4": { + "src_wire": "BYP_ALT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_L4" + }, + "INT_L.WW4END0->>NN6BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.GFAN0->>BYP_ALT4": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.GFAN0->>IMUX_L43": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.ER1END3->>SE2BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.SW6END0->>LV_L0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L0" + }, + "INT_L.NW2END_S0_0->>IMUX_L39": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.WW4END_S0_0->>SR1BEG_S0": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.EL1END3->>FAN_ALT1": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.WL1END_N1_3->>IMUX_L16": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.WL1END0->>NL1BEG0": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.SW6END0->>WW2BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.SR1END1->>IMUX_L20": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.SE6END0->>NR1BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.LOGIC_OUTS_L22->>IMUX_L40": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.LOGIC_OUTS_L20->>NR1BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.NW2END2->>SW2BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.EE2END3->>EE2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.SW6END1->>NW2BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L18": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.VCC_WIRE->>IMUX_L6": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NR1END3->>IMUX_L14": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.WL1END_N1_3->>FAN_ALT0": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.NE2END3->>NL1BEG2": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.GCLK_L_B1->>CLK_L1": { + "src_wire": "GCLK_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.NE2END_S3_0->>IMUX_L47": { + "src_wire": "NE2END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.SE2END0->>IMUX_L25": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NL1BEG_N3->>IMUX_L21": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.EL1END3->>SL1BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.NE2END1->>SL1BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.SS6END0->>WW2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.LOGIC_OUTS_L12->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.SW2END0->>IMUX_L2": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.LOGIC_OUTS_L5->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.BYP_ALT2->>BYP_L2": { + "src_wire": "BYP_ALT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_L2" + }, + "INT_L.FAN_BOUNCE4->>FAN_ALT0": { + "src_wire": "FAN_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.LOGIC_OUTS_L4->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.SE2END3->>IMUX_L38": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.ER1END1->>FAN_ALT7": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.EL1END3->>IMUX_L29": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.SS6END1->>SL1BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.EE2END2->>EE4BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.LOGIC_OUTS_L21->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.LOGIC_OUTS_L0->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.LV_L9->>SW6BEG1": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.LOGIC_OUTS_L9->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.NR1END2->>IMUX_L29": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L6": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NR1END2->>NR1BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.SW2END1->>IMUX_L34": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.NW2END1->>SR1BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.NW2END2->>WW4BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L24": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.SS2END2->>SS6BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.LOGIC_OUTS_L23->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.EL1END2->>IMUX_L5": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.NN2END2->>SE6BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.NR1END0->>NE2BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.NE2END1->>NL1BEG0": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.WL1END3->>FAN_ALT3": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.LOGIC_OUTS_L3->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.EE2END3->>IMUX_L6": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NN6END1->>NE2BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.NN6END1->>WW2BEG0": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L17": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.NW2END_S0_0->>BYP_ALT7": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.WR1END2->>BYP_ALT5": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.SR1END2->>IMUX_L37": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.LOGIC_OUTS_L13->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.NR1END0->>LV_L18": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.WW2END2->>IMUX_L46": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.SW2END3->>SE6BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.SW6END0->>SR1BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.GFAN0->>IMUX_L42": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.LOGIC_OUTS_L11->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.LVB_L0->>SS6BEG2": { + "src_wire": "LVB_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.LOGIC_OUTS_L20->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.ER1END3->>NE2BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L42": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.LOGIC_OUTS_L23->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.NW6END1->>NE6BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.LOGIC_OUTS_L6->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.BYP_ALT6->>BYP_BOUNCE6": { + "src_wire": "BYP_ALT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE6" + }, + "INT_L.NW6END2->>WW2BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L43": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.SW6END3->>SE6BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.SE2END3->>EE2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.WW2END1->>WL1BEG0": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.NW6END1->>SW2BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L10": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.EE2END3->>IMUX_L47": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.NR1END0->>IMUX_L24": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.SE2END0->>IMUX_L9": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.WL1END2->>IMUX_L37": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.LOGIC_OUTS_L12->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.WR1END0->>WR1BEG1": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.NL1END1->>IMUX_L34": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.SW6END0->>SS2BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.GCLK_L_B6_WEST->>GFAN0": { + "src_wire": "GCLK_L_B6_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.NN2END2->>BYP_ALT5": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.SS2END0->>NR1BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.FAN_BOUNCE3->>FAN_ALT7": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.ER1END0->>BYP_ALT0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NW6END3->>NW6BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L1": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.ER1END0->>EE2BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.WR1END1->>SW2BEG0": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.LOGIC_OUTS_L15->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.LVB_L12->>NN6BEG2": { + "src_wire": "LVB_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.EL1END2->>IMUX_L21": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.SW2END0->>BYP_ALT0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.FAN_BOUNCE6->>BYP_ALT1": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.LOGIC_OUTS_L17->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.LH0->>LVB_L12": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.NR1END3->>FAN_ALT1": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.LOGIC_OUTS_L0->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.NW2END2->>FAN_ALT7": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.NW6END1->>EL1BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.WW2END_N0_3->>IMUX_L8": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.SR1BEG_S0->>SL1BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.NL1BEG_N3->>BYP_ALT6": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.NR1END0->>IMUX_L33": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.SS2END2->>EE2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.SS2END0->>IMUX_L41": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SW2END2->>SE6BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.NW6END0->>NW2BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.SS6END0->>EE4BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.EE2END2->>ER1BEG3": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SE2END0->>IMUX_L17": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.LOGIC_OUTS_L2->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.FAN_BOUNCE5->>BYP_ALT5": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.NL1END2->>IMUX_L3": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.LOGIC_OUTS_L7->>SS2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.EE2END0->>NE6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.LOGIC_OUTS_L5->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.NN6END0->>EE4BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.LOGIC_OUTS_L19->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.EL1END3->>FAN_ALT3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.SE2END1->>SE6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.SS2END3->>IMUX_L38": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.LOGIC_OUTS_L5->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.NE2END2->>LVB_L12": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.SE2END0->>SS6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.GFAN1->>IMUX_L30": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.GFAN0->>IMUX_L18": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L28": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L40": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NN2END3->>IMUX_L37": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.NN2END3->>EE4BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.LOGIC_OUTS_L18->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L39": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.NE6END0->>NE2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.LOGIC_OUTS_L10->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.WL1END1->>IMUX_L27": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.NW6END2->>NE6BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.FAN_ALT0->>FAN_BOUNCE0": { + "src_wire": "FAN_ALT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE0" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L21": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.LV_L0<<->>LH0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.LOGIC_OUTS_L6->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.NN2END2->>IMUX_L4": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.WW2END0->>BYP_ALT1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.NW6END1->>SS6BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.WL1END0->>IMUX_L2": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.EE4END1->>NE2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.NE2END0->>IMUX_L1": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.LOGIC_OUTS_L19->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.ER1END2->>IMUX_L36": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.NN6END3->>NN2BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.LOGIC_OUTS_L6->>IMUX_L29": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.SE6END2->>SL1BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.NE6END3->>SE6BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.WR1END1->>FAN_ALT2": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.SS2END0->>SL1BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.WW2END0->>IMUX_L9": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.LOGIC_OUTS_L20->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.LOGIC_OUTS_L2->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L38": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L41": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.LOGIC_OUTS_L9->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.WL1END1->>WW2BEG1": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.NE2END0->>NE2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.LOGIC_OUTS_L18->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.NW2END3->>IMUX_L6": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.WW4END3->>SS6BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.NN6END3->>NR1BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.LV_L9->>LH12": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.SS2END2->>BYP_ALT3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.NN2END3->>NL1BEG2": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.NW2END1->>IMUX_L10": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.SR1END1->>IMUX_L12": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.EL1END1->>IMUX_L26": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L11": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.EL1END3->>BYP_ALT6": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SW2END_N0_3->>NW2BEG0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L14": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LOGIC_OUTS_L16->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.EL1END1->>SS2BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.LV_L9->>NE6BEG1": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.VCC_WIRE->>BYP_ALT6": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.LV_L0->>NW6BEG0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.EE2END2->>IMUX_L36": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.LOGIC_OUTS_L17->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.SS6END2->>WL1BEG1": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.NR1END3->>IMUX_L47": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.NN6END3->>NW2BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L32": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.NN6END3->>EE2BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.SR1BEG_S0->>IMUX_L18": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.WR1END2->>NW2BEG2": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.EL1END3->>EE2BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.SS2END1->>IMUX_L12": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.NR1END2->>IMUX_L12": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.WW2END3->>IMUX_L39": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.WW2END0->>NW2BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.LOGIC_OUTS_L9->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.VCC_WIRE->>IMUX_L40": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.LOGIC_OUTS_L23->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.LOGIC_OUTS_L22->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L15": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.LOGIC_OUTS_L23->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L38": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.SL1END3->>SL1BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.SR1END3->>IMUX_L47": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.LOGIC_OUTS_L1->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.LH0->>SE6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.LOGIC_OUTS_L18->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.LOGIC_OUTS_L8->>SE2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L24": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.LOGIC_OUTS_L15->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.LOGIC_OUTS_L10->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.SS2END2->>NR1BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.WW2END1->>IMUX_L20": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.LOGIC_OUTS_L13->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.LOGIC_OUTS_L16->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L28": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.LOGIC_OUTS_L1->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L45": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.LOGIC_OUTS_L21->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.LOGIC_OUTS_L22->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.NE2END3->>SE6BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.SS6END1->>SE2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L30": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.NW2END0->>BYP_ALT0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.SW2END2->>IMUX_L21": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.WR1END3->>LVB_L12": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.LOGIC_OUTS_L20->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.WW4END1->>WR1BEG2": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.LOGIC_OUTS_L8->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.NW2END0->>NE2BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.EE2END3->>SS6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.EE4END2->>EE2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.WR1END1->>NN2BEG1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.NW2END_S0_0->>WL1BEG2": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.LOGIC_OUTS_L5->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.WW4END2->>NN6BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.NE2END1->>WW4BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.EE2END1->>IMUX_L18": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.NW6END0->>NE2BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.VCC_WIRE->>IMUX_L23": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.EL1END3->>SE2BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.LV_L9->>EE4BEG1": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.WR1END3->>SW2BEG2": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.EE2END3->>SE2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.SS2END3->>EE2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.SS2END3->>SR1BEG_S0": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.SE6END3->>WL1BEG2": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.EE2END3->>IMUX_L39": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.LOGIC_OUTS_L16->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.EL1END2->>SE2BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.WW2END2->>NL1BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.WW4END1->>NE6BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.SE2END2->>IMUX_L21": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.LOGIC_OUTS_L7->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.NE2END3->>NN2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.ER1END3->>EL1BEG2": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.NN6END2->>EE2BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L43": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.SW2END2->>ER1BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SS2END2->>IMUX_L29": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.NE2END3->>LH0": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.WW2END1->>IMUX_L44": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.SR1END3->>LH12": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.SS2END3->>SS6BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.NL1END2->>IMUX_L12": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.WR1END3->>IMUX_L7": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.ER1END2->>CTRL_L1": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.NE2END0->>NE6BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.WR1END3->>WL1BEG1": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.LOGIC_OUTS_L8->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.SW2END1->>SS6BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.NR1END2->>EE2BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.LOGIC_OUTS_L11->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.LOGIC_OUTS_L21->>IMUX_L31": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.LOGIC_OUTS_L20->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.LH0->>WW4BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.SE6END2->>SW2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.SL1END1->>IMUX_L27": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L12": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.EE4END1->>ER1BEG2": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.EE2END3->>IMUX_L23": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.NE6END0->>NE6BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.SW2END_N0_3->>WW4BEG0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L34": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L0->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.LOGIC_OUTS_L2->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.EE4END2->>EE4BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.SE2END3->>NE2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.WW4END2->>NE6BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.LOGIC_OUTS_L10->>NN2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.NN6END2->>NE2BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.WW2END1->>IMUX_L35": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.NL1END0->>EE2BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.SE2END1->>NE6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.NR1END3->>NW2BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.FAN_BOUNCE_S3_2->>FAN_ALT3": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.SE2END3->>SS2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L33": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.NW2END3->>NL1BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.SW2END3->>SE2BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.LOGIC_OUTS_L0->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.NW6END_S0_0->>SW6BEG3": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.WW2END0->>SW2BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.LOGIC_OUTS_L14->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.NE2END0->>IMUX_L24": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L13": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.NL1END_S3_0->>IMUX_L23": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.SW6END0->>WW4BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.NE2END2->>NE2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.EL1END2->>IMUX_L44": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.SS6END1->>ER1BEG2": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.SS2END0->>BYP_ALT1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.LOGIC_OUTS_L0->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.LOGIC_OUTS_L20->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.FAN_BOUNCE5->>CLK_L1": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.ER1END2->>IMUX_L14": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LOGIC_OUTS_L15->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.EE4END2->>SE2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.EE2END3->>SS2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.NW2END1->>IMUX_L33": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L22": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.SW2END0->>IMUX_L41": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.NE6END3->>NR1BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.NE6END3->>NE2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.NW2END0->>IMUX_L32": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.SE2END2->>FAN_ALT7": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.SS2END2->>WL1BEG1": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.NN6END1->>NN6BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.SR1END2->>SW2BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.WR1END1->>IMUX_L42": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.VCC_WIRE->>BYP_ALT4": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.WW2END_N0_3->>IMUX_L16": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.LOGIC_OUTS_L17->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.NN2END1->>IMUX_L41": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.ER1END1->>SS2BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.NN2END3->>BYP_ALT6": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SS2END0->>IMUX_L40": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NE2END2->>WR1BEG3": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.GCLK_L_B6_WEST->>CLK_L0": { + "src_wire": "GCLK_L_B6_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.SE2END1->>IMUX_L26": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.LOGIC_OUTS_L8->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.VCC_WIRE->>IMUX_L17": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.GCLK_L_B10->>GCLK_L_B10_WEST": { + "src_wire": "GCLK_L_B10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B10_WEST" + }, + "INT_L.SE2END2->>NN6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.LOGIC_OUTS_L21->>NE2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.SS2END2->>WW4BEG3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.NE2END3->>IMUX_L46": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.NN2END3->>FAN_ALT3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.NN2END1->>WW2BEG0": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.NW6END1->>WW2BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.WR1END_S1_0->>SR1BEG_S0": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.WW2END3->>ER1BEG_S0": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.WW2END1->>NE6BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.ER1END2->>EL1BEG1": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.EE2END1->>EE4BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.SE6END2->>SE2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.EL1END0->>FAN_ALT4": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.LH0->>EE4BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.LOGIC_OUTS_L3->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.WW4END1->>GFAN0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.SW2END2->>IMUX_L29": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.LOGIC_OUTS_L18->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.SE2END0->>IMUX_L33": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.EE2END1->>IMUX_L26": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.SS2END2->>SW6BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L11": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.SW2END2->>FAN_ALT1": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L28": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.NN2END2->>FAN_ALT5": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.EE2END2->>SS2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.EL1END2->>IMUX_L27": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.SL1END3->>BYP_ALT6": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SE2END2->>IMUX_L4": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.NW2END_S0_0->>SW2BEG3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.SW6END3->>SR1BEG_S0": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L19": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.LV_L18->>NW6BEG3": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.NE2END0->>NL1BEG_N3": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.EL1END1->>ER1BEG2": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.GFAN1->>BYP_ALT7": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.EL1END2->>BYP_ALT5": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L0": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.WW4END_S0_0->>SW2BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.NE6END0->>NN6BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.LOGIC_OUTS_L6->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.NW6END2->>NN6BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.NE6END3->>NW2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.SW6END1->>WW4BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.LOGIC_OUTS_L17->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.LOGIC_OUTS_L19->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.SE6END1->>EE4BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.SW2END0->>WL1BEG_N3": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.NW2END1->>NW6BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.NW2END_S0_0->>SR1BEG_S0": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.SL1END0->>WL1BEG_N3": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.BYP_BOUNCE1->>FAN_ALT6": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.SW2END1->>SW6BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.NN2END3->>NN2BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.LV_L0->>SE6BEG0": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.NN2END1->>IMUX_L26": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.LOGIC_OUTS_L1->>NW2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.LOGIC_OUTS_L4->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.LOGIC_OUTS_L20->>SE2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.LOGIC_OUTS_L22->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.GFAN0->>FAN_ALT0": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.SS2END0->>NW6BEG1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.NR1END1->>EE2BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.SR1BEG_S0->>IMUX_L42": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.LOGIC_OUTS_L2->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.NW2END0->>NL1BEG_N3": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.NR1END1->>GFAN1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.GCLK_L_B9->>GCLK_L_B9_WEST": { + "src_wire": "GCLK_L_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B9_WEST" + }, + "INT_L.LOGIC_OUTS_L23->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.EL1END3->>IMUX_L45": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.SS2END2->>IMUX_L44": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L26": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.NN6END0->>EL1BEG_N3": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.SE6END1->>SE2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.LOGIC_OUTS_L20->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.WW2END_N0_3->>IMUX_L32": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.NW2END1->>NN2BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.WW2END2->>IMUX_L13": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.NN2END1->>IMUX_L34": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.NR1END2->>EL1BEG1": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.WW2END2->>IMUX_L37": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.EE2END0->>IMUX_L16": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.EE2END3->>NR1BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.LOGIC_OUTS_L20->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L47": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.LOGIC_OUTS_L23->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.WW2END1->>WW4BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L43": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.LOGIC_OUTS_L1->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L30": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.LH6->>LVB_L0": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.LOGIC_OUTS_L4->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L36": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.LOGIC_OUTS_L18->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.NW2END0->>WW4BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.SL1END2->>IMUX_L44": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.SE2END3->>IMUX_L15": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.SS6END0->>WL1BEG_N3": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.LV_L9->>SE6BEG1": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.LOGIC_OUTS_L4->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L29": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.EE2END2->>IMUX_L44": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.NE2END0->>SL1BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.LOGIC_OUTS_L18->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.SR1END3->>SS2BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.EL1END1->>EE2BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.SS2END0->>SW6BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.EE2END3->>IMUX_L30": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.LOGIC_OUTS_L3->>SE6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.NE6END2->>NL1BEG1": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.WW4END2->>SS2BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L32": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.WW4END1->>ER1BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.EL1END1->>IMUX_L33": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.WW4END3->>ER1BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.GCLK_L_B4->>CLK_L1": { + "src_wire": "GCLK_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.NE2END3->>IMUX_L29": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.NE6END0->>EE2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.LOGIC_OUTS_L4->>SW6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.WW2END0->>IMUX_L42": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.LOGIC_OUTS_L18->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.EL1END0->>IMUX_L0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.SS6END3->>SE2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.SW2END0->>SS6BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.SW2END3->>IMUX_L47": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.LOGIC_OUTS_L1->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.WW2END0->>IMUX_L1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.LOGIC_OUTS_L19->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.SR1END1->>SS2BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.LOGIC_OUTS_L6->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L25": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NR1END1->>NE2BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.SW2END2->>IMUX_L13": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.SL1END0->>IMUX_L40": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.LOGIC_OUTS_L19->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.SW2END1->>NL1BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.NW6END1->>WR1BEG2": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.LOGIC_OUTS_L8->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L19->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L47": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.NN2END3->>NW6BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.NE2END2->>NW6BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.GCLK_L_B11->>GCLK_L_B11_EAST": { + "src_wire": "GCLK_L_B11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B11_EAST" + }, + "INT_L.NW2END3->>FAN_ALT5": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.LOGIC_OUTS_L10->>NE6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L32": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.LOGIC_OUTS_L12->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NW6END2->>SR1BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.SS6END0->>NR1BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L22": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.LOGIC_OUTS_L18->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.SW6END_N0_3->>NL1BEG_N3": { + "src_wire": "SW6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L3->>NR1BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.SW2END2->>NW2BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.SL1END1->>IMUX_L10": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.NW6END1->>NE2BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.NW2END1->>WL1BEG_N3": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.NR1END2->>IMUX_L5": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.EE2END1->>NN6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.WL1END2->>FAN_ALT5": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.BYP_ALT3->>BYP_BOUNCE3": { + "src_wire": "BYP_ALT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE3" + }, + "INT_L.NE2END2->>SE2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.WW2END1->>BYP_ALT5": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.WW2END2->>IMUX_L21": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.SS6END3->>LH12": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.BYP_BOUNCE1->>BYP_ALT2": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.LOGIC_OUTS_L12->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.WW4END1->>SW6BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.LOGIC_OUTS_L11->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.EE2END1->>NE6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.SW2END0->>IMUX_L1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.SW2END3->>SW2BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.SW6END2->>SW2BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.WW2END3->>IMUX_L47": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.EE4END3->>SE6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L19": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.LOGIC_OUTS_L7->>NN2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.NN6END2->>WR1BEG3": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.LOGIC_OUTS_L12->>IMUX_L0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.SS2END3->>WW2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.WW4END3->>NL1BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.WW4END2->>WW2BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.WR1END_S1_0->>IMUX_L39": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.EE4END1->>SL1BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.LOGIC_OUTS_L0->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.NE2END1->>NN6BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.SW2END1->>WL1BEG0": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.LOGIC_OUTS_L9->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.GFAN0->>IMUX_L0": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.LOGIC_OUTS_L9->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.SW6END1->>SW2BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.LOGIC_OUTS_L5->>EE2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.NE6END3->>WR1BEG_S0": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.NE2END0->>IMUX_L8": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.SW2END2->>IMUX_L37": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.SS6END2->>CTRL_L0": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.WW2END1->>SS6BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.SS2END1->>IMUX_L42": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.SE2END2->>SE2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.FAN_BOUNCE7->>BYP_ALT0": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.SR1END2->>SE2BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.NN6END1->>NW6BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.WR1END1->>WR1BEG2": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.BYP_ALT1->>BYP_BOUNCE1": { + "src_wire": "BYP_ALT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE1" + }, + "INT_L.LOGIC_OUTS_L0->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.EE4END0->>NN6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.SR1END1->>WW2BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.SS2END3->>IMUX_L39": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.BYP_BOUNCE1->>GFAN0": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.SL1END2->>BYP_ALT3": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L47": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.BYP_BOUNCE4->>FAN_ALT1": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.LOGIC_OUTS_L11->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.GCLK_L_B4->>GFAN1": { + "src_wire": "GCLK_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.WR1END2->>IMUX_L28": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.SL1END1->>IMUX_L35": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.WW2END2->>ER1BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SS6END_N0_3->>WW4BEG0": { + "src_wire": "SS6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.LOGIC_OUTS_L14->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.NL1END1->>FAN_ALT2": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.LOGIC_OUTS_L4->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.SL1END2->>BYP_ALT2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.SS6END3->>ER1BEG_S0": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.NE2END2->>WW4BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.EL1END2->>NE2BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.VCC_WIRE->>IMUX_L38": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.NN6END2->>EE4BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.LOGIC_OUTS_L1->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.NW6END_S0_0->>SR1BEG_S0": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.SW6END3->>WW2BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.NN6END2->>CTRL_L1": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L36": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.GCLK_L_B7_WEST->>GFAN0": { + "src_wire": "GCLK_L_B7_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.EL1END0->>IMUX_L16": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.LOGIC_OUTS_L15->>NW2BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.LOGIC_OUTS_L4->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.NW2END1->>IMUX_L42": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.SE2END3->>IMUX_L47": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.EL1END3->>IMUX_L14": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.SL1END2->>IMUX_L5": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.NN2END1->>IMUX_L25": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.LOGIC_OUTS_L12->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.SS2END_N0_3->>FAN_ALT0": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.NR1END1->>IMUX_L11": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.NW2END2->>NN2BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.SW2END0->>SL1BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.LOGIC_OUTS_L8->>NW2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.LOGIC_OUTS_L15->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.ER1END2->>SE2BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.LOGIC_OUTS_L18->>SE6BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.GCLK_L_B0->>GFAN0": { + "src_wire": "GCLK_L_B0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.LOGIC_OUTS_L6->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.SL1END2->>FAN_ALT5": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.NN6END3->>LVB_L0": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.SE6END3->>NR1BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.LOGIC_OUTS_L2->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SS2END0->>EE4BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L6": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NW6END3->>SR1BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.SR1END3->>IMUX_L23": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.LOGIC_OUTS_L8->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.NN6END2->>EL1BEG1": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.NL1BEG_N3->>BYP_ALT3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.SS6END1->>SE6BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.SE6END0->>WL1BEG_N3": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.SE2END0->>NN6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.SL1END1->>IMUX_L26": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L4": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.SS6END2->>ER1BEG3": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L2": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.LOGIC_OUTS_L5->>NE2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.SL1END1->>IMUX_L18": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.SL1END0->>IMUX_L25": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.SL1END0->>SS2BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.LOGIC_OUTS_L7->>SW6BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.VCC_WIRE->>IMUX_L29": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.WR1END1->>IMUX_L33": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.ER1END0->>IMUX_L17": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.ER1END1->>IMUX_L26": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L17": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.WW2END1->>NN6BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.NE6END3->>WW4BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.SS2END2->>IMUX_L14": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.NR1END3->>NN2BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.WR1END2->>IMUX_L27": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.FAN_BOUNCE5->>FAN_ALT7": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L5": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.NE2END3->>EE2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.EE2END0->>EE4BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.WR1END1->>IMUX_L34": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L2->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.EE4END0->>SS6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.WR1END3->>NW2BEG3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.LOGIC_OUTS_L9->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.WW2END0->>IMUX_L33": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.NN6END1->>NL1BEG0": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L29": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.SS6END2->>SE2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.NE2END3->>LH12": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.WW4END1->>SS6BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.VCC_WIRE->>BYP_ALT7": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.GFAN0->>BYP_ALT5": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.NW6END3->>NN6BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.SL1END3->>IMUX_L7": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.GFAN0->>IMUX_L35": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.LOGIC_OUTS_L16->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.SE2END1->>IMUX_L42": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.LOGIC_OUTS_L1->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.NR1END2->>BYP_ALT2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.SL1END3->>IMUX_L31": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.LOGIC_OUTS_L10->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.WL1END3->>IMUX_L38": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.ER1END3->>IMUX_L39": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.NW2END2->>IMUX_L43": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.EE2END0->>WR1BEG1": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.NN6END3->>SR1BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L27": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.SW2END2->>LVB_L12": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.LOGIC_OUTS_L16->>SW6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.LOGIC_OUTS_L17->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.WR1END3->>LVB_L0": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.SW6END1->>NW6BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.NL1BEG_N3->>NE2BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_L.SS2END0->>IMUX_L33": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.WL1END2->>WL1BEG1": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.LOGIC_OUTS_L16->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L11": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.LOGIC_OUTS_L19->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.GFAN1->>IMUX_L22": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.WL1END0->>IMUX_L33": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.ER1END1->>BYP_ALT4": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.WL1END1->>IMUX_L19": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.SL1END2->>IMUX_L28": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.WL1END2->>IMUX_L5": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.NR1END0->>WR1BEG1": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.SE6END2->>NN6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.LOGIC_OUTS_L17->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.SE2END1->>NN6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.NR1END0->>BYP_ALT1": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.GCLK_L_B1->>GFAN1": { + "src_wire": "GCLK_L_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.SS6END2->>WW2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.LOGIC_OUTS_L22->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.LVB_L0->>NE6BEG2": { + "src_wire": "LVB_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.EE4END3->>LH12": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.LVB_L0<<->>LVB_L12": { + "src_wire": "LVB_L0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.NN6END0->>NR1BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.ER1END1->>ER1BEG2": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.EE4END1->>NR1BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.LV_L9->>WW4BEG1": { + "src_wire": "LV_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.ER1END1->>IMUX_L11": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.WW4END0->>NW2BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.EL1END3->>BYP_ALT3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.LOGIC_OUTS_L20->>SW2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.NR1END3->>BYP_ALT6": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.NL1BEG_N3->>IMUX_L30": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.VCC_WIRE->>IMUX_L7": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.EE4END0->>EL1BEG_N3": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L16->>SS6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.SL1END3->>IMUX_L38": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.SW2END3->>IMUX_L39": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.SE2END3->>NR1BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.LOGIC_OUTS_L6->>WW4BEG2": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.ER1END0->>IMUX_L40": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.LOGIC_OUTS_L1->>NN2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.LOGIC_OUTS_L3->>SE2BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.NR1END2->>CTRL_L1": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.LOGIC_OUTS_L22->>NE2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.EL1END1->>NE2BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.EE4END3->>EL1BEG2": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.SS6END1->>WW4BEG2": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.SE2END2->>BYP_ALT2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.LOGIC_OUTS_L16->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.LOGIC_OUTS_L8->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.SR1END3->>IMUX_L39": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.LOGIC_OUTS_L4->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.WW2END0->>IMUX_L17": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L41": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.WL1END0->>WR1BEG2": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.WW4END3->>SS2BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.SE2END3->>IMUX_L23": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.LOGIC_OUTS_L19->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L30": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.WR1END1->>SR1BEG1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.WL1END0->>IMUX_L18": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.NE2END1->>FAN_ALT6": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.ER1END3->>IMUX_L23": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.NN2END1->>IMUX_L10": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.WW2END2->>NE6BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L30": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.GFAN1->>IMUX_L23": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L7": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L38": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.SW6END2->>SE6BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.GFAN1->>BYP_ALT2": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.LOGIC_OUTS_L15->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.WW2END2->>IMUX_L22": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.FAN_BOUNCE7->>BYP_ALT4": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.SL1END2->>IMUX_L12": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.WW2END0->>NN6BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L31": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.SR1END2->>BYP_ALT6": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SL1END1->>SR1BEG2": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.LOGIC_OUTS_L8->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L7": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.GFAN1->>FAN_ALT1": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.LOGIC_OUTS_L12->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.LOGIC_OUTS_L13->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.SW6END3->>SL1BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.ER1END1->>EE2BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.NE2END0->>EL1BEG_N3": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L46": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.EL1END1->>FAN_ALT6": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.SS2END2->>EE4BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.ER1END3->>NR1BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.NN2END3->>WW2BEG2": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.LOGIC_OUTS_L5->>SW2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.LOGIC_OUTS_L16->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.NN6END3->>SE6BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.WR1END3->>NN2BEG3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L26": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.EE2END2->>IMUX_L20": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.LOGIC_OUTS_L20->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.SW6END1->>SS6BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.SW6END2->>NL1BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.ER1END2->>SS2BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.LH12->>EE4BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.NR1END1->>IMUX_L10": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.SR1END3->>ER1BEG_S0": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.SW2END3->>IMUX_L46": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.EL1END3->>SS2BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_L.WR1END0->>IMUX_L9": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L9": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.LOGIC_OUTS_L21->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.LOGIC_OUTS_L12->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.WW4END0->>WW4BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.NL1END_S3_0->>BYP_ALT7": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.LV_L18->>SS6BEG3": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.NE6END1->>NE2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.GFAN0->>BYP_ALT1": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.SW2END0->>IMUX_L32": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.NW2END2->>IMUX_L28": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.WW4END2->>SR1BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.WW2END1->>NW6BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.LOGIC_OUTS_L7->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.NL1END2->>NW2BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.NN2END0->>EL1BEG_N3": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.WW2END0->>IMUX_L26": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.SW6END_N0_3->>NW2BEG0": { + "src_wire": "SW6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.LOGIC_OUTS_L12->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.LOGIC_OUTS_L12->>WR1BEG1": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.NW2END2->>WR1BEG3": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.SR1BEG_S0->>IMUX_L9": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.NR1END0->>FAN_ALT4": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L39": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.WR1END1->>IMUX_L18": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.NR1END2->>CTRL_L0": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.EE4END2->>NN6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.LOGIC_OUTS_L0->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.NN6END0->>NN6BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.LOGIC_OUTS_L8->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.SS6END3->>EE2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.SL1END3->>IMUX_L30": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.SL1END1->>BYP_ALT4": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.NN2END0->>IMUX_L24": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.ER1END_N3_3->>FAN_ALT0": { + "src_wire": "ER1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.NN2END3->>EE2BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.LOGIC_OUTS_L3->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.BYP_BOUNCE1->>IMUX_L19": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.WL1END0->>IMUX_L1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.NE2END3->>WR1BEG_S0": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.EL1END3->>IMUX_L15": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.WW4END0->>NE6BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.GCLK_L_B9->>GCLK_L_B9_EAST": { + "src_wire": "GCLK_L_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B9_EAST" + }, + "INT_L.ER1END2->>FAN_ALT5": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.GFAN0->>IMUX_L16": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.LOGIC_OUTS_L2->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.NE2END2->>IMUX_L35": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.NN2END1->>IMUX_L42": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.VCC_WIRE->>IMUX_L8": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.NE2END0->>IMUX_L16": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.SW2END_N0_3->>NW6BEG0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.LOGIC_OUTS_L8->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.NR1END2->>FAN_ALT7": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.WW2END1->>SR1BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.ER1END0->>SL1BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.LOGIC_OUTS_L15->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.NW2END2->>NW2BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.LOGIC_OUTS_L17->>EE2BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.NW2END2->>WL1BEG0": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L34": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L9->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.LVB_L12->>NE6BEG2": { + "src_wire": "LVB_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.WW4END0->>NL1BEG_N3": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.NN6END2->>WW4BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.NE2END2->>NN6BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.EE4END3->>WR1BEG_S0": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.NN6END1->>NR1BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.WL1END1->>FAN_ALT6": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.WL1END0->>IMUX_L25": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NN2END1->>NW2BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.WW2END0->>NW6BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.NL1BEG_N3->>NW2BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.EE4END0->>WR1BEG1": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_L.LOGIC_OUTS_L9->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.ER1END2->>IMUX_L6": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NN6END1->>SE6BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.EE2END2->>IMUX_L5": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.SW2END3->>IMUX_L31": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.EL1END3->>IMUX_L6": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NW6END2->>EL1BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.EL1END_S3_0->>IMUX_L39": { + "src_wire": "EL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.LOGIC_OUTS_L2->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.SW2END0->>BYP_ALT1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_L.LOGIC_OUTS_L3->>EE4BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.LOGIC_OUTS_L15->>SS6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.WL1END2->>IMUX_L13": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.LOGIC_OUTS_L6->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.LOGIC_OUTS_L19->>WL1BEG0": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.LVB_L12->>SS6BEG2": { + "src_wire": "LVB_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_L.EL1END1->>NR1BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.BYP_BOUNCE6->>BYP_ALT7": { + "src_wire": "BYP_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.LOGIC_OUTS_L5->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.LOGIC_OUTS_L12->>NW6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_L.LV_L18->>SE6BEG3": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.EL1END2->>IMUX_L4": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.SW2END0->>SW2BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.SR1END3->>FAN_ALT3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.SS2END0->>SE2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.GCLK_L_B9_WEST->>GFAN0": { + "src_wire": "GCLK_L_B9_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.VCC_WIRE->>IMUX_L31": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.SS2END3->>ER1BEG_S0": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.GFAN1->>FAN_ALT3": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.VCC_WIRE->>IMUX_L39": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.SL1END0->>FAN_ALT0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.NN2END0->>IMUX_L17": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.NE2END1->>IMUX_L3": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.GCLK_L_B0->>CLK_L1": { + "src_wire": "GCLK_L_B0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.LOGIC_OUTS_L15->>NN6BEG3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.ER1END0->>LV_L0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L0" + }, + "INT_L.LOGIC_OUTS_L3->>WW4BEG3": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.NR1END1->>WR1BEG2": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.LOGIC_OUTS_L5->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.LOGIC_OUTS_L5->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L9": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.ER1END2->>NE2BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.FAN_BOUNCE_S3_4->>BYP_ALT7": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L17": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.NN2END1->>EE2BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.LOGIC_OUTS_L11->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.EE4END1->>EL1BEG0": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L36": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.LOGIC_OUTS_L7->>WW2BEG3": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.SS2END1->>IMUX_L4": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.LOGIC_OUTS_L0->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.FAN_BOUNCE_S3_0->>IMUX_L20": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.SS6END0->>ER1BEG1": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.LH6->>SE6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.LOGIC_OUTS_L22->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.NR1END0->>IMUX_L25": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.WW2END2->>NN2BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.SW2END3->>LVB_L0": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.SS2END3->>EE4BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.SR1END1->>SE2BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.NN6END3->>EE4BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.WW2END3->>IMUX_L23": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.SR1BEG_S0->>SW2BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.SW6END1->>SL1BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.LOGIC_OUTS_L5->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L4": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.ER1END0->>IMUX_L10": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.EE2END3->>IMUX_L15": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.VCC_WIRE->>BYP_ALT2": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L42": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.WR1END2->>CTRL_L0": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.WW2END_N0_3->>NL1BEG_N3": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.WR1END3->>IMUX_L29": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.SR1END1->>ER1BEG2": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.SW2END1->>ER1BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.NN2END2->>WW4BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.WW2END0->>WR1BEG2": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.ER1END0->>NR1BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.LOGIC_OUTS_L6->>WR1BEG3": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.WW2END1->>IMUX_L43": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.SE6END3->>SE6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.EE2END0->>SE2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L25": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NE2END1->>EE4BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.EL1END0->>IMUX_L8": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.FAN_BOUNCE6->>IMUX_L1": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.WL1END0->>NN2BEG1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L7": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.NE2END3->>NW6BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.NE2END2->>NL1BEG1": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.SW2END3->>BYP_ALT6": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SR1END2->>IMUX_L21": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.LOGIC_OUTS_L15->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.LOGIC_OUTS_L13->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.EL1END1->>EL1BEG0": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.LOGIC_OUTS_L19->>WR1BEG2": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.WW2END2->>FAN_ALT1": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.GCLK_L_B8_WEST->>GFAN1": { + "src_wire": "GCLK_L_B8_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_L.SS2END2->>SS2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.SL1END0->>WW2BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.VCC_WIRE->>FAN_ALT0": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.SR1END1->>WL1BEG0": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.LOGIC_OUTS_L22->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.LOGIC_OUTS_L5->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.SW2END0->>IMUX_L10": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.SL1END3->>IMUX_L6": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.EE4END3->>EE4BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.WW2END0->>BYP_ALT4": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.LOGIC_OUTS_L4->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.GCLK_L_B10_WEST->>GFAN0": { + "src_wire": "GCLK_L_B10_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.NW6END1->>NW6BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.NN2END2->>IMUX_L20": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.NE6END2->>CTRL_L0": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.LOGIC_OUTS_L21->>NL1BEG2": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L1": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.LOGIC_OUTS_L1->>SS2BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.SE2END0->>SE2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.GCLK_L_B3->>CLK_L0": { + "src_wire": "GCLK_L_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.VCC_WIRE->>IMUX_L34": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.VCC_WIRE->>IMUX_L46": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.VCC_WIRE->>IMUX_L25": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.SW6END1->>WW2BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.SW6END0->>SW6BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_L.LOGIC_OUTS_L21->>SW2BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.NW2END_S0_0->>SW6BEG3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.FAN_ALT5->>FAN_BOUNCE5": { + "src_wire": "FAN_ALT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE5" + }, + "INT_L.SS6END3->>SW2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.LV_L0<<->>LV_L18": { + "src_wire": "LV_L0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LV_L18" + }, + "INT_L.SW2END0->>WW2BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.WL1END1->>FAN_ALT7": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.NR1END3->>IMUX_L38": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.LOGIC_OUTS_L1->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.SE6END3->>ER1BEG_S0": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.LOGIC_OUTS_L20->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.ER1END1->>IMUX_L3": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L37": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.BYP_ALT1->>BYP_L1": { + "src_wire": "BYP_ALT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_L1" + }, + "INT_L.LOGIC_OUTS_L5->>IMUX_L10": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.SS2END2->>IMUX_L22": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.WW4END2->>WR1BEG3": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L13": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.SW2END1->>SL1BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.NE6END2->>NE2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.WW4END1->>NN2BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.SW6END0->>WL1BEG_N3": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L8": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.GFAN1->>IMUX_L6": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NN6END0->>NN2BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.LOGIC_OUTS_L8->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.SE6END0->>SW2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L19": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L19" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L27": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.SR1END_N3_3->>IMUX_L32": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.LOGIC_OUTS_L10->>IMUX_L37": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.SE2END0->>NR1BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.LOGIC_OUTS_L1->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.NE2END1->>SE6BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.WW2END1->>WW2BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.NN2END0->>IMUX_L1": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L17": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.LOGIC_OUTS_L10->>NW2BEG2": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.SE6END2->>SS2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.LOGIC_OUTS_L7->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SL1END1->>FAN_ALT2": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.NN2END3->>IMUX_L15": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.BYP_BOUNCE0->>FAN_ALT7": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.WW2END3->>IMUX_L15": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.WW4END3->>NN6BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.WR1END3->>IMUX_L23": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.GFAN0->>IMUX_L8": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.WL1END0->>IMUX_L41": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SE6END0->>EL1BEG_N3": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.FAN_BOUNCE7->>FAN_ALT4": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.NL1END1->>IMUX_L9": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.LVB_L12->>SE6BEG2": { + "src_wire": "LVB_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.WL1END1->>BYP_ALT5": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.SW2END2->>WW4BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.SL1END2->>SE2BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.SW6END1->>EE4BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.SS6END1->>EE2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_L.BYP_BOUNCE4->>IMUX_L14": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LVB_L0->>WW4BEG2": { + "src_wire": "LVB_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.WL1END3->>BYP_ALT7": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.LOGIC_OUTS_L17->>IMUX_L14": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.LOGIC_OUTS_L20->>EE4BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L5": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.LV_L18<<->>LH0": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_L.SS2END2->>NW6BEG3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.NW6END3->>WL1BEG1": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.LOGIC_OUTS_L20->>IMUX_L12": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.WL1END2->>NN2BEG3": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.NN2END0->>FAN_ALT4": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.NW2END1->>FAN_ALT4": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.LOGIC_OUTS_L16->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.SR1END2->>FAN_ALT1": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.VCC_WIRE->>FAN_ALT2": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.NE6END0->>SE2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.WW2END1->>NW2BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.WW2END0->>FAN_ALT4": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.EE2END2->>IMUX_L28": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.EL1END2->>IMUX_L36": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.LOGIC_OUTS_L8->>SS2BEG0": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.EE2END1->>FAN_ALT6": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.SS2END1->>WW4BEG2": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.WW2END2->>SW2BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.SW2END1->>SW2BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.LOGIC_OUTS_L0->>IMUX_L32": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.NL1BEG_N3->>EL1BEG2": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.FAN_BOUNCE6->>FAN_ALT0": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.SW6END0->>SE2BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.GFAN1->>IMUX_L12": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.WW4END2->>CTRL_L1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.LOGIC_OUTS_L13->>IMUX_L43": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.NW6END3->>WW4BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.EE4END0->>SS2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.WL1END1->>IMUX_L3": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.EE4END3->>SS6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.WW2END0->>NN2BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_L.WW4END3->>NN2BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.NR1END1->>IMUX_L3": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.NW2END2->>EL1BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.SW2END2->>IMUX_L44": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.SE6END0->>SS6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.NN2END_S2_0->>BYP_ALT7": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.SW2END3->>SL1BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.EE2END1->>SE2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.LOGIC_OUTS_L14->>IMUX_L44": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.SL1END2->>ER1BEG3": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.NW6END1->>WW4BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.BYP_BOUNCE_N3_2->>IMUX_L16": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.WW2END1->>SW6BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L26": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.NL1END1->>NR1BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.WW2END_N0_3->>BYP_ALT0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.WW2END_N0_3->>NE6BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.WR1END_S1_0->>WW2BEG3": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_L.VCC_WIRE->>IMUX_L16": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.LOGIC_OUTS_L5->>NL1BEG0": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_L.EE2END1->>IMUX_L10": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.SS2END2->>IMUX_L13": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.NL1END2->>IMUX_L35": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.BYP_BOUNCE_N3_3->>IMUX_L17": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.NN6END0->>NE2BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.EL1END3->>IMUX_L7": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.WW2END_N0_3->>IMUX_L24": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.LOGIC_OUTS_L12->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.SS6END0->>SR1BEG1": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L10": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.SS2END0->>SE6BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.SW6END0->>SW2BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.SW2END0->>IMUX_L40": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NW2END0->>NN2BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.SE2END2->>IMUX_L44": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.SR1END3->>SL1BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L4": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.NW2END2->>NE2BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.NW6END0->>WW4BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.WW2END2->>BYP_ALT3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.WW2END2->>WW4BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.NE6END0->>NR1BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L40": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.SS2END1->>IMUX_L34": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L34" + }, + "INT_L.LOGIC_OUTS_L18->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.NN2END2->>IMUX_L28": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.SS2END1->>SR1BEG2": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.LOGIC_OUTS_L11->>NE6BEG3": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.LOGIC_OUTS_L17->>SL1BEG3": { + "src_wire": "LOGIC_OUTS_L17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.LOGIC_OUTS_L19->>IMUX_L26": { + "src_wire": "LOGIC_OUTS_L19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.NN6END0->>SE6BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.FAN_ALT3->>FAN_L3": { + "src_wire": "FAN_ALT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_L3" + }, + "INT_L.NW6END3->>NE6BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.SW6END3->>SW6BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_L.VCC_WIRE->>IMUX_L32": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.SE6END1->>ER1BEG2": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.NR1END0->>IMUX_L40": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.NN6END2->>SR1BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.ER1END1->>IMUX_L27": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.WW2END1->>BYP_ALT2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.WW2END_N0_3->>NW2BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_L.SR1END2->>IMUX_L45": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.NN2END3->>IMUX_L29": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.VCC_WIRE->>BYP_ALT5": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.NW2END2->>FAN_ALT6": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.LOGIC_OUTS_L11->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.EL1END0->>SE2BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_L.LOGIC_OUTS_L0->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.GFAN0->>FAN_ALT2": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.FAN_BOUNCE3->>BYP_ALT5": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.NE2END1->>NR1BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.LOGIC_OUTS_L16->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SL1END3->>SR1BEG_S0": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.WR1END2->>IMUX_L36": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.WL1END3->>SW2BEG3": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.WL1END2->>NL1BEG2": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_L.NN2END2->>NR1BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.VCC_WIRE->>IMUX_L30": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L30" + }, + "INT_L.NE6END1->>NN6BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.SS6END1->>SR1BEG2": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.NW6END2->>WL1BEG0": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.SS2END3->>BYP_ALT7": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.NR1END1->>FAN_ALT6": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.EE4END3->>NN2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_L.NR1END2->>WR1BEG3": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.WR1END1->>IMUX_L10": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.SS6END1->>SS6BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.SE2END2->>FAN_ALT5": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.WW4END2->>NW6BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.EE4END0->>ER1BEG1": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.EE2END1->>IMUX_L42": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.NR1END2->>NE2BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.WL1END0->>BYP_ALT0": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.LOGIC_OUTS_L0->>NR1BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L28": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.LOGIC_OUTS_L16->>NE2BEG2": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.WR1END3->>IMUX_L46": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.WW2END2->>WW2BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.SW2END0->>IMUX_L33": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.SS2END0->>IMUX_L25": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.NN2END3->>IMUX_L45": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.NW2END3->>WW4BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_L.LOGIC_OUTS_L1->>IMUX_L43": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.GFAN0->>CTRL_L1": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.LOGIC_OUTS_L3->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.SW2END0->>SE6BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.BYP_BOUNCE_N3_6->>IMUX_L24": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L39": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.LH6->>SS6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.NE6END2->>NW6BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.GFAN1->>IMUX_L29": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.EE2END1->>SE6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.SL1END2->>IMUX_L45": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.BYP_BOUNCE5->>IMUX_L15": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.ER1END1->>BYP_ALT5": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.LOGIC_OUTS_L22->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.NE2END2->>EE2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.NW6END3->>EL1BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L35": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.SW2END0->>SR1BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.EL1END1->>SE2BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.EE4END2->>WR1BEG3": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.FAN_BOUNCE2->>BYP_ALT0": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.BYP_ALT5->>BYP_BOUNCE5": { + "src_wire": "BYP_ALT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE5" + }, + "INT_L.WW4END0->>LV_L0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L0" + }, + "INT_L.NE6END2->>SE6BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.SE6END3->>LVB_L0": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.EE2END1->>SS6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.NN6END3->>EL1BEG2": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.SW6END1->>SS2BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_L.NE2END1->>WR1BEG2": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_L.WL1END2->>IMUX_L14": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.WR1END2->>WL1BEG0": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.WW2END2->>SR1BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.NW6END0->>NN6BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.WR1END2->>FAN_ALT7": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.WL1END2->>IMUX_L6": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L6" + }, + "INT_L.NE6END3->>NN6BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.NW6END2->>NN2BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.SR1END1->>BYP_ALT5": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.NN6END1->>EE4BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.NW2END_S0_0->>IMUX_L15": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.SR1END3->>IMUX_L15": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.NW2END2->>IMUX_L12": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L12" + }, + "INT_L.SE2END1->>IMUX_L2": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.SL1END2->>SL1BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.LOGIC_OUTS_L4->>IMUX_L33": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.ER1END2->>BYP_ALT2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.SW6END0->>SE6BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.WR1END_S1_0->>WL1BEG2": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.NW2END2->>LVB_L12": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.WW2END0->>IMUX_L25": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.WL1END1->>NN2BEG2": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.NR1END1->>NR1BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.SS2END_N0_3->>IMUX_L0": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.SR1END3->>IMUX_L7": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.GCLK_L_B6_WEST->>CLK_L1": { + "src_wire": "GCLK_L_B6_WEST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.NN6END1->>SR1BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.WR1END1->>FAN_ALT6": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.EE2END0->>EL1BEG_N3": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_L.EE2END1->>FAN_ALT2": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.LOGIC_OUTS_L9->>SE6BEG1": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_L.VCC_WIRE->>FAN_ALT7": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.FAN_BOUNCE5->>IMUX_L35": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L35" + }, + "INT_L.WR1END0->>IMUX_L8": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.ER1END1->>NE2BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.LOGIC_OUTS_L10->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.SS2END1->>ER1BEG2": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.LOGIC_OUTS_L21->>EL1BEG2": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.LOGIC_OUTS_L22->>SS6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.NW2END3->>NW6BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.SR1BEG_S0->>SS2BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_L.WW4END3->>WL1BEG1": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.NR1END3->>FAN_ALT3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.GCLK_L_B5->>CLK_L1": { + "src_wire": "GCLK_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L1" + }, + "INT_L.LOGIC_OUTS_L22->>WW4BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.EE2END2->>SE2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.LOGIC_OUTS_L18->>IMUX_L25": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.LOGIC_OUTS_L5->>ER1BEG2": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.SL1END3->>ER1BEG_S0": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.GFAN0->>IMUX_L10": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.WL1END3->>IMUX_L31": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.LOGIC_OUTS_L23->>NN6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_L.WR1END2->>FAN_ALT5": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.VCC_WIRE->>BYP_ALT0": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.SS2END0->>IMUX_L2": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.BYP_BOUNCE2->>IMUX_L22": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.WW2END1->>NN2BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_L.VCC_WIRE->>IMUX_L10": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.SS2END1->>IMUX_L3": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.WW2END3->>IMUX_L7": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L7" + }, + "INT_L.WW2END2->>FAN_ALT5": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.WL1END0->>IMUX_L17": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.SW2END2->>SE2BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_L.SW2END0->>IMUX_L9": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L9" + }, + "INT_L.NE2END3->>IMUX_L45": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.NN2END2->>NW2BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.SS6END2->>NR1BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_L.NL1BEG_N3->>IMUX_L37": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.SS2END2->>SW2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_L.SE2END2->>EE2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.SE6END0->>EE2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.WL1END3->>IMUX_L39": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.LOGIC_OUTS_L2->>IMUX_L44": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.WL1END3->>IMUX_L23": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.LOGIC_OUTS_L8->>IMUX_L25": { + "src_wire": "LOGIC_OUTS_L8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.SS2END0->>ER1BEG1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.SE6END3->>NE6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_L.EE2END1->>ER1BEG2": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_L.LOGIC_OUTS_L20->>SL1BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.NR1END1->>BYP_ALT4": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L3": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.NL1END0->>NN2BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.LOGIC_OUTS_L14->>NL1BEG1": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_L.EE2END1->>IMUX_L2": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.NE6END2->>EE4BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.LOGIC_OUTS_L22->>NN6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.SR1END2->>CTRL_L1": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.NE6END2->>NW2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.NW2END3->>EL1BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.SS2END0->>SW2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.WW2END3->>BYP_ALT7": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.LH0<<->>LH12": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.SW2END3->>SR1BEG_S0": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.NN2END2->>EE2BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.SR1END2->>IMUX_L14": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.SW6END2->>SW6BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_L.LOGIC_OUTS_L3->>IMUX_L23": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L42": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.NR1END0->>LV_L0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L0" + }, + "INT_L.NN2END1->>IMUX_L2": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.SL1END1->>IMUX_L42": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L42" + }, + "INT_L.NL1END1->>NE2BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L31": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.GFAN1->>IMUX_L13": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.WR1END3->>WR1BEG_S0": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.LOGIC_OUTS_L1->>EL1BEG0": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.EE4END3->>NN6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.ER1END3->>IMUX_L31": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.SW2END3->>FAN_ALT3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.EE2END1->>BYP_ALT5": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_L.ER1END1->>EL1BEG0": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_L.LOGIC_OUTS_L14->>NN6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_L.SS2END0->>SR1BEG1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.WR1END2->>IMUX_L4": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.SE2END3->>IMUX_L46": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.NN6END2->>NW2BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.SS2END0->>IMUX_L24": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L24" + }, + "INT_L.LOGIC_OUTS_L9->>IMUX_L2": { + "src_wire": "LOGIC_OUTS_L9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L2" + }, + "INT_L.NL1END2->>IMUX_L4": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.ER1END1->>FAN_ALT6": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.SS6END1->>EE4BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.LOGIC_OUTS_L13->>NW6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_L.SW2END2->>IMUX_L45": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.GFAN0->>IMUX_L25": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L25" + }, + "INT_L.FAN_BOUNCE1->>BYP_ALT4": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.LH12->>NE6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.SE2END1->>IMUX_L27": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L27" + }, + "INT_L.NL1END1->>FAN_ALT4": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.SR1END1->>SL1BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.WW2END2->>IMUX_L38": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.NN6END2->>CTRL_L0": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L0" + }, + "INT_L.VCC_WIRE->>IMUX_L11": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L11" + }, + "INT_L.LOGIC_OUTS_L13->>WW2BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_L.LOGIC_OUTS_L7->>IMUX_L38": { + "src_wire": "LOGIC_OUTS_L7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.VCC_WIRE->>IMUX_L33": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.LOGIC_OUTS_L13->>WW4BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.LOGIC_OUTS_L12->>EE4BEG0": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_L.ER1END3->>SL1BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_L.LOGIC_OUTS_L14->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.NL1END_S3_0->>IMUX_L47": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L47" + }, + "INT_L.EL1END2->>SL1BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.LOGIC_OUTS_L3->>WL1BEG2": { + "src_wire": "LOGIC_OUTS_L3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.SW2END1->>EE4BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.BYP_ALT5->>BYP_L5": { + "src_wire": "BYP_ALT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_L5" + }, + "INT_L.LOGIC_OUTS_L22->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.LOGIC_OUTS_L22->>NE6BEG0": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_L.WR1END2->>IMUX_L44": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.WW2END_N0_3->>NN6BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_L.WW2END0->>WW4BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.FAN_BOUNCE7->>IMUX_L40": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.GCLK_L_B7->>GCLK_L_B7_WEST": { + "src_wire": "GCLK_L_B7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_L_B7_WEST" + }, + "INT_L.EE2END0->>IMUX_L1": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L1" + }, + "INT_L.LOGIC_OUTS_L13->>NE6BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.SS2END1->>SW2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_L.NR1END3->>EL1BEG2": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_L.NW6END2->>NW6BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.WL1END2->>IMUX_L21": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.FAN_BOUNCE_S3_2->>IMUX_L22": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L22" + }, + "INT_L.SS2END2->>WW2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.SW2END1->>FAN_ALT7": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_L.GCLK_L_B4->>GFAN0": { + "src_wire": "GCLK_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_L.SW6END0->>SS6BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.SR1BEG_S0->>FAN_ALT4": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_L.SR1END2->>IMUX_L5": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L5" + }, + "INT_L.SW2END3->>WL1BEG2": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L14": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L14" + }, + "INT_L.WW2END_N0_3->>NN2BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.SR1END2->>WL1BEG1": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.LOGIC_OUTS_L0->>SL1BEG0": { + "src_wire": "LOGIC_OUTS_L0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_L.LOGIC_OUTS_L15->>IMUX_L15": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L15" + }, + "INT_L.SE2END2->>IMUX_L37": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.NE2END3->>EE4BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.SE6END2->>NE2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_L.LOGIC_OUTS_L23->>IMUX_L43": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.BYP_BOUNCE_N3_7->>BYP_ALT0": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.SW2END2->>BYP_ALT3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.SE2END2->>ER1BEG3": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SW6END_N0_3->>WW4BEG0": { + "src_wire": "SW6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_L.SS2END3->>SW2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_L.LOGIC_OUTS_L16->>IMUX_L29": { + "src_wire": "LOGIC_OUTS_L16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L29" + }, + "INT_L.SL1END2->>IMUX_L37": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.BYP_ALT0->>BYP_L0": { + "src_wire": "BYP_ALT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_L0" + }, + "INT_L.EE2END1->>NR1BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_L.BYP_BOUNCE0->>IMUX_L44": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.GFAN1->>IMUX_L44": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.WR1END0->>IMUX_L32": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L32" + }, + "INT_L.FAN_BOUNCE1->>IMUX_L10": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L10" + }, + "INT_L.NE2END0->>NN2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.ER1END_N3_3->>IMUX_L0": { + "src_wire": "ER1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L0" + }, + "INT_L.EE2END0->>SS6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_L.SW2END1->>IMUX_L3": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.LOGIC_OUTS_L15->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS_L15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.WW4END_S0_0->>WL1BEG2": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.LOGIC_OUTS_L6->>WL1BEG1": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_L.EE4END3->>EE2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.NE2END3->>NW2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.WL1END2->>IMUX_L36": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.SE2END0->>SE6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_L.WR1END0->>FAN_ALT0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.EE2END0->>NR1BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.SE2END2->>IMUX_L20": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L20" + }, + "INT_L.SW2END0->>IMUX_L18": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L18" + }, + "INT_L.SW2END1->>IMUX_L26": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L26" + }, + "INT_L.NL1BEG_N3->>FAN_ALT5": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.LV_L18<<->>LH12": { + "src_wire": "LV_L18", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_L.BYP_BOUNCE3->>IMUX_L23": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L23" + }, + "INT_L.SS2END0->>EE2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.SW2END1->>SR1BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.NL1END1->>IMUX_L41": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L41" + }, + "INT_L.SW2END0->>IMUX_L17": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L17" + }, + "INT_L.SE2END2->>IMUX_L36": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L36" + }, + "INT_L.NW6END2->>CTRL_L1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL_L1" + }, + "INT_L.LOGIC_OUTS_L4->>WW2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.SL1END0->>IMUX_L33": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L33" + }, + "INT_L.LOGIC_OUTS_L1->>SW6BEG1": { + "src_wire": "LOGIC_OUTS_L1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.SS2END2->>IMUX_L28": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L28" + }, + "INT_L.LOGIC_OUTS_L18->>SW2BEG0": { + "src_wire": "LOGIC_OUTS_L18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_L.NR1END3->>EE2BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_L.SR1BEG_S0->>WL1BEG_N3": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.NW2END2->>SW6BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_L.LOGIC_OUTS_L13->>SL1BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.LH6->>LVB_L12": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.GFAN1->>IMUX_L39": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L39" + }, + "INT_L.NW6END2->>SS6BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_L.LOGIC_OUTS_L21->>NW6BEG3": { + "src_wire": "LOGIC_OUTS_L21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.SW6END2->>NW6BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_L.NE2END3->>SE2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_L.LOGIC_OUTS_L13->>EE4BEG1": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_L.FAN_BOUNCE6->>FAN_ALT2": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.FAN_BOUNCE3->>IMUX_L37": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L13": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L13" + }, + "INT_L.WW2END3->>SR1BEG_S0": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_L.SW2END2->>FAN_ALT5": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.LOGIC_OUTS_L11->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_L.BYP_BOUNCE5->>BYP_ALT6": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_L.SW2END2->>SL1BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.LH0->>SS6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_L.SS2END3->>SE6BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_L.LOGIC_OUTS_L22->>SR1BEG1": { + "src_wire": "LOGIC_OUTS_L22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_L.LVB_L12->>WW4BEG2": { + "src_wire": "LVB_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_L.FAN_ALT1->>FAN_L1": { + "src_wire": "FAN_ALT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_L1" + }, + "INT_L.LOGIC_OUTS_L14->>SE6BEG2": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_L.NR1END2->>BYP_ALT3": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_L.NN2END0->>BYP_ALT0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_L.WR1END0->>LV_L0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV_L0" + }, + "INT_L.BYP_BOUNCE1->>FAN_ALT5": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_L.NN2END2->>EL1BEG1": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.SW2END2->>LVB_L0": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L0" + }, + "INT_L.SW2END0->>NW2BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.WR1END3->>IMUX_L45": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L45" + }, + "INT_L.NE2END2->>SL1BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_L.SL1END3->>WL1BEG2": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.ER1END3->>IMUX_L46": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L46" + }, + "INT_L.SW2END1->>IMUX_L4": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L4" + }, + "INT_L.NR1END2->>NW2BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_L.NE6END0->>NL1BEG_N3": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_L.NN6END1->>NE6BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_L.EE4END3->>ER1BEG_S0": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_L.SW2END0->>FAN_ALT2": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.WR1END2->>WR1BEG3": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_L.WR1END1->>CLK_L0": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK_L0" + }, + "INT_L.NE2END2->>NE6BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_L.FAN_BOUNCE_S3_4->>IMUX_L37": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L37" + }, + "INT_L.EE4END2->>SS2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_L.WW4END3->>WW2BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.NR1END2->>IMUX_L44": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L44" + }, + "INT_L.WL1END1->>WL1BEG0": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_L.WR1END1->>BYP_ALT4": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_L.LOGIC_OUTS_L4->>NN2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_L.SE2END0->>IMUX_L8": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L8" + }, + "INT_L.LVB_L12->>NW6BEG2": { + "src_wire": "LVB_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.WW4END1->>WW2BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_L.FAN_BOUNCE_S3_0->>BYP_ALT2": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_L.EL1END3->>NR1BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_L.SS6END3->>EE4BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_L.LOGIC_OUTS_L4->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.NL1END_S3_0->>FAN_ALT3": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_L.LOGIC_OUTS_L4->>ER1BEG1": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_L.NE2END0->>NR1BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_L.NW2END1->>WW4BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_L.SE6END1->>SL1BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_L.SE2END0->>IMUX_L16": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L16" + }, + "INT_L.SE2END0->>NE2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_L.LOGIC_OUTS_L6->>ER1BEG3": { + "src_wire": "LOGIC_OUTS_L6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.SE2END1->>IMUX_L43": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L43" + }, + "INT_L.WL1END2->>NW2BEG3": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_L.EE2END1->>IMUX_L3": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.WW2END3->>IMUX_L31": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L31" + }, + "INT_L.WW4END3->>LVB_L12": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB_L12" + }, + "INT_L.WW4END3->>WR1BEG_S0": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_L.NN6END1->>NW2BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_L.NN2END3->>NN6BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_L.LOGIC_OUTS_L13->>SR1BEG2": { + "src_wire": "LOGIC_OUTS_L13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_L.NE6END2->>EE2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_L.SS6END3->>WL1BEG2": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_L.LOGIC_OUTS_L14->>EL1BEG1": { + "src_wire": "LOGIC_OUTS_L14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_L.SE2END0->>FAN_ALT0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_L.LOGIC_OUTS_L12->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS_L12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_L.LOGIC_OUTS_L4->>EE2BEG0": { + "src_wire": "LOGIC_OUTS_L4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_L.LOGIC_OUTS_L10->>SR1BEG3": { + "src_wire": "LOGIC_OUTS_L10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_L.LOGIC_OUTS_L2->>WW2BEG2": { + "src_wire": "LOGIC_OUTS_L2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.FAN_BOUNCE_S3_6->>BYP_ALT7": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_L.LOGIC_OUTS_L20->>NW6BEG2": { + "src_wire": "LOGIC_OUTS_L20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_L.SW2END2->>EE4BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_L.SR1END1->>FAN_ALT6": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_L.SS2END2->>IMUX_L21": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.BYP_BOUNCE_N3_7->>IMUX_L3": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L3" + }, + "INT_L.LOGIC_OUTS_L5->>SE2BEG1": { + "src_wire": "LOGIC_OUTS_L5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_L.WR1END3->>WW2BEG2": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_L.SE2END1->>FAN_ALT2": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_L.EE4END2->>ER1BEG3": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_L.LOGIC_OUTS_L11->>IMUX_L38": { + "src_wire": "LOGIC_OUTS_L11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L38" + }, + "INT_L.SL1END2->>IMUX_L21": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L21" + }, + "INT_L.GFAN0->>IMUX_L40": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX_L40" + }, + "INT_L.LOGIC_OUTS_L23->>SS6BEG1": { + "src_wire": "LOGIC_OUTS_L23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + } + }, "wires": [ - "IMUX_L1", - "NR1BEG1", - "SW2A1", - "SE2END1", - "IMUX_L42", - "NN6BEG3", - "EE4A2", - "LV_L8", - "NL1END0", - "NL1END_S3_0", - "WL1END1", - "BYP_BOUNCE6", - "NE6E1", - "LOGIC_OUTS_L5", - "LVB_L5", - "SS2END2", - "EE2END3", - "NN6A3", - "GCLK_L_B8", - "WW2A2", - "EL1END0", - "WR1END_S1_0", - "NE6D0", - "NE6B3", - "WW2A3", - "BYP_L6", - "MONITOR_N", - "ER1END3", - "SW2BEG0", - "ER1BEG3", - "IMUX_L24", - "NN6C2", - "BYP_BOUNCE_N3_7", - "LOGIC_OUTS_L2", - "LOGIC_OUTS_L20", - "LV_L15", - "ER1BEG0", - "IMUX_L28", - "LH11", - "NE6E3", - "EE2END1", - "NW6C2", - "GCLK_L_B11", - "NE6END2", - "WW2END3", - "EE2BEG1", - "SS2END_N0_3", - "SR1BEG3", - "IMUX_L39", - "EE2BEG3", - "NW6B0", - "SE6E1", - "NW2BEG1", - "FAN_L0", - "NN6BEG0", - "SW2BEG2", - "SE6BEG1", - "SR1END2", - "SS6BEG2", - "SW6END3", - "WW4BEG3", - "LOGIC_OUTS_L23", - "NN6B2", - "BYP_BOUNCE5", - "LV_L14", - "IMUX_L46", - "BYP_ALT6", - "EE4A3", - "BYP_L2", - "SS6B0", - "NW6END_S0_0", - "IMUX_L4", - "NW6END3", - "SS6E3", - "BYP_L1", - "SL1BEG0", - "EE4A1", - "SR1END3", - "LOGIC_OUTS_L8", - "LH12", - "WL1BEG_N3", - "SL1BEG3", - "LVB_L7", - "SE6B2", - "NN6A2", - "NN6D0", - "FAN_BOUNCE_S3_2", - "EE2A2", - "LOGIC_OUTS_L4", - "IMUX_L2", - "SE6C2", - "WW2BEG2", - "EE2END0", - "EL1END1", - "NN2END_S2_0", - "SE6D3", - "WL1BEG3", - "NN6C0", - "CTRL_L0", - "IMUX_L7", - "NN2END0", - "NN2A3", - "EE4C3", - "SS6C1", - "IMUX_L40", - "LV_L7", - "CLK_L1", - "SS6C2", - "SR1BEG1", - "NW6A3", - "SS6A3", - "WW4B3", - "LOGIC_OUTS_L1", - "SE6C1", - "SS2END0", - "SE2END2", - "WL1BEG1", - "BYP_BOUNCE1", - "LVB_L12", - "FAN_BOUNCE2", - "NE2BEG3", - "WR1END1", - "EE2A1", - "SS2BEG3", - "SS6END1", - "IMUX_L29", - "SW6C2", - "WW4BEG1", - "SE6C3", - "LVB_L0", - "WW4C2", - "NW2END_S0_0", - "INT_DQS_IOTOPHASER", - "WW4A2", - "NN6E0", - "NL1END1", - "WL1BEG0", - "NN6END0", - "NN6A0", - "LOGIC_OUTS_L22", - "SW6A1", - "SL1END2", - "IMUX_L15", - "GFAN0", - "GCLK_L_B7", - "SW6D0", - "NE2BEG1", - "IMUX_L13", - "NW6END0", - "LH3", - "SS6A2", - "GCLK_L_B2", - "BYP_L7", - "NE6BEG3", - "SS6B1", - "NE2A1", - "IMUX_L23", - "IMUX_L34", - "VCC_WIRE", - "NE6C2", - "WR1BEG0", - "GCLK_L_B5", - "NE2BEG2", - "FAN_BOUNCE0", - "BYP_L0", - "SW6E2", - "ER1BEG1", - "FAN_L2", - "SE6A1", - "WW2END2", - "NW6D1", - "SS2END3", - "IMUX_L35", - "BYP_BOUNCE2", - "SE6B3", - "WL1END2", - "GCLK_L_B7_EAST", - "GCLK_L_B6", - "IMUX_L33", - "NN6END2", - "LOGIC_OUTS_L12", - "WW4END3", - "FAN_BOUNCE_S3_0", - "SS6END0", - "LVB_L3", - "EE2A0", - "IMUX_L43", - "EL1END_S3_0", - "SL1END0", - "LV_L9", - "LOGIC_OUTS_L9", - "EL1BEG0", - "NR1END1", - "SE2BEG1", - "SR1END1", - "SW6B0", - "NW6D2", - "SS6D1", - "EE4BEG0", - "NW6C0", - "SE2A3", - "FAN_L7", - "LOGIC_OUTS_L11", - "SE6A2", - "SW2END0", - "LH2", - "NE2END3", - "IMUX_L26", - "BYP_BOUNCE3", - "INT_PHASER_TO_IO_ICLK", - "ER1BEG_S0", - "NN2END3", - "BYP_L5", - "WL1END_N1_3", - "INT_PHASER_TO_IO_ICLKDIV", - "SE6E0", - "BYP_BOUNCE4", - "WR1BEG_S0", - "EE4BEG2", - "IMUX_L5", - "LH5", - "LV_L1", - "GCLK_L_B11_WEST", - "LH8", - "LOGIC_OUTS_L21", - "NN2BEG1", - "GCLK_L_B10_WEST", - "BYP_ALT1", - "SS6D3", - "LV_L6", - "FAN_ALT2", - "LVB_L1", - "NE2END1", - "GCLK_L_B8_WEST", - "WW2END_N0_3", - "WW4END0", - "IMUX_L32", - "NW6D3", - "IMUX_L14", - "NL1BEG_N3", - "NW6E0", - "LVB_L2", - "SW2END_N0_3", - "NE6BEG0", - "CTRL_L1", - "GCLK_L_B6_EAST", - "SE6END0", - "LH0", - "SW6END2", - "FAN_L1", - "SW6B2", - "WW4B1", - "SW6END_N0_3", - "NR1BEG2", - "WW2A0", - "WW4C3", - "LOGIC_OUTS_L10", - "NN6E2", - "WW4A1", - "SE2BEG3", - "BYP_ALT2", - "SW6BEG1", - "NE2A0", - "NE2A3", - "NE6END1", - "SS6E1", - "ER1END_N3_3", - "BYP_ALT3", - "SW6D1", - "NE6A0", - "SS6BEG1", - "SR1BEG_S0", - "WW2END1", - "SW6A0", - "NL1BEG0", - "EE4END1", - "FAN_L4", - "IMUX_L31", - "WW2BEG3", - "SL1BEG1", - "SW6C0", - "WR1BEG2", - "NW2A3", - "NE6D2", - "SS6C3", - "SE6END1", - "EE4B1", - "SS2A2", - "LV_L18", - "LV_L13", - "LOGIC_OUTS_L14", - "EE2BEG2", - "FAN_BOUNCE1", - "NN2A0", - "FAN_ALT7", - "WW4B2", - "SS6BEG3", - "LH7", - "LVB_L6", - "WW2BEG1", - "LOGIC_OUTS_L6", - "SE6END3", - "LH1", - "EE4B3", - "IMUX_L19", - "LOGIC_OUTS_L17", - "SW2END1", - "NW6A0", - "NL1END2", - "SS6D2", - "IMUX_L16", - "SS6END_N0_3", - "LV_L12", - "NE6END0", - "BYP_BOUNCE0", - "LOGIC_OUTS_L18", - "IMUX_L17", - "NN6B3", - "NW2A0", - "SE6BEG3", - "NN6C1", - "IMUX_L8", - "NN6A1", - "LV_L4", - "WR1END2", - "SW6D3", - "FAN_BOUNCE_S3_6", - "NW6E2", - "EE4A0", - "NW6B3", - "WW4END2", - "GCLK_L_B7_WEST", - "NW2END2", - "LVB_L8", - "EL1END2", - "SL1END3", - "SS2BEG1", - "ER1END1", - "IMUX_L0", - "FAN_BOUNCE5", - "CLK_L0", - "SR1BEG2", - "GCLK_L_B11_EAST", - "LVB_L4", - "FAN_BOUNCE4", - "GCLK_L_B1", - "LV_L2", - "NN6E1", - "EE4C2", - "FAN_ALT4", - "SE6B1", - "SW2BEG3", - "GCLK_L_B9", - "LV_L17", - "SE6B0", - "SS6E0", - "LV_L0", - "WL1END3", - "IMUX_L41", - "NR1END0", - "SW6A3", - "SE6END2", - "LOGIC_OUTS_L0", - "NE6A1", - "NN6D1", - "FAN_ALT5", - "SE6BEG0", - "NW6B1", - "NE6D1", - "SW6A2", - "BYP_L3", - "ER1END0", - "NW6A2", - "SE6D2", - "SW6E1", - "SW6END1", - "IMUX_L21", - "EE4END0", - "WW2BEG0", - "WW4A0", - "IMUX_L12", - "LH6", - "GCLK_L_B9_WEST", - "LOGIC_OUTS_L13", - "WW4END_S0_0", - "SS6BEG0", - "SS6E2", - "WW4C1", - "SW2A2", - "EE4C1", - "NR1END3", - "EE4B0", - "SW6C1", - "NN6END1", - "NW6BEG2", - "NW2BEG2", - "BYP_BOUNCE_N3_6", - "NE6B0", - "IMUX_L6", - "BYP_ALT7", - "FAN_BOUNCE3", - "SW6E3", - "SE6BEG2", - "SS6B2", - "SS2BEG2", - "SW6BEG3", - "GCLK_L_B8_EAST", - "IMUX_L44", - "GCLK_L_B9_EAST", - "NE2END2", - "EL1BEG1", - "SW2A3", - "EE2BEG0", - "LOGIC_OUTS_L16", - "SE6E2", - "SE2END3", - "WW4END1", - "NW2BEG0", - "LH10", - "SS6C0", - "SW6BEG2", - "NE6B2", - "SW6B1", - "WW4BEG2", - "BYP_BOUNCE7", - "NN6C3", - "INT_PHASER_TO_IO_OCLK", - "NE2A2", - "NL1BEG2", - "NN2BEG0", - "FAN_L5", - "NN6BEG2", - "SS6D0", - "NE6E0", - "IMUX_L27", - "NE6E2", - "WL1BEG2", - "NN2A1", - "SL1END1", - "SE6A3", - "GCLK_L_B10_EAST", - "NW6BEG0", - "FAN_BOUNCE7", - "NE6BEG1", - "IMUX_L47", - "LV_L16", - "LVB_L11", - "LH4", - "NW6BEG1", - "FAN_L3", - "NW6D0", - "WW4BEG0", - "SS2A0", - "FAN_ALT6", - "IMUX_L37", - "NE6END3", - "NN2END1", - "NW6A1", - "GCLK_L_B4", - "NR1BEG3", - "WW4A3", - "SE2END0", - "SE2BEG2", - "NW6END1", - "SE6A0", - "SS6A1", - "NW6C1", - "IMUX_L9", - "LOGIC_OUTS_L15", - "SW6B3", - "SS6A0", - "SE6D0", - "BYP_L4", - "SW6END0", - "LOGIC_OUTS_L7", - "NW2END1", - "SR1END_N3_3", - "MONITOR_P", - "NN6BEG1", - "BYP_ALT5", - "INT_PHASER_TO_IO_OCLK1X_90", - "GFAN1", - "NW2A1", - "NW6B2", - "EL1BEG3", - "EE4BEG3", - "INT_PHASER_TO_IO_OCLKDIV", - "SS6END2", - "LH9", - "SS6B3", - "NW6E3", - "NE6A3", - "NW2BEG3", - "NN6D3", - "SW6D2", - "NE6D3", - "FAN_ALT1", - "WW4B0", - "GCLK_L_B3", - "LVB_L9", - "LVB_L10", - "SS6END3", - "BYP_ALT4", - "FAN_L6", - "EE2END2", - "BYP_BOUNCE_N3_2", - "IMUX_L3", - "WR1END3", - "LV_L11", - "FAN_ALT3", - "NN6END_S1_0", - "SE6E3", - "IMUX_L10", "NE6C0", - "SL1BEG2", - "IMUX_L45", - "IMUX_L20", - "IMUX_L30", - "WR1BEG1", - "SE2A0", - "NR1END2", - "SE2A2", - "NR1BEG0", - "GCLK_L_B0", - "IMUX_L25", - "SE6D1", - "NW6BEG3", - "GCLK_L_B10", - "IMUX_L36", - "IMUX_L18", - "SW2BEG1", - "LOGIC_OUTS_L3", - "NN6B0", - "SS2A1", - "NN2BEG3", - "NW2A2", - "FAN_ALT0", - "NN6B1", - "ER1END2", - "SW6BEG0", - "FAN_BOUNCE6", - "NN2BEG2", - "NW2END0", - "EE4END3", - "EE4B2", - "WW4C0", - "BYP_ALT0", - "NE6B1", - "NE6A2", - "SS2BEG0", - "FAN_BOUNCE_S3_4", - "NN6E3", - "WR1BEG3", - "NE2BEG0", - "NE6C1", - "SE6C0", - "NW2END3", - "EE4BEG1", - "EL1BEG_N3", - "NL1BEG1", - "NN2END2", - "ER1BEG2", - "NN6D2", - "EL1END3", - "WW2A1", - "NE6BEG2", - "SS2END1", - "BYP_BOUNCE_N3_3", - "SE2A1", - "EE2A3", - "EE4END2", - "SS2A3", + "LVB_L3", "NN6END3", - "LV_L3", - "SE2BEG0", - "WR1END0", - "NW6C3", - "LV_L5", - "LOGIC_OUTS_L19", - "LV_L10", - "GCLK_L_B6_WEST", - "IMUX_L38", - "NW6END2", - "NW6E1", + "EE2END2", + "LVB_L10", + "LV_L4", + "SE6B0", + "NN6END1", + "BYP_ALT6", + "SL1BEG1", + "SE6B1", + "EE2BEG1", + "NW2BEG2", + "SW6A0", + "FAN_BOUNCE_S3_2", + "GCLK_L_B11", + "BYP_BOUNCE_N3_3", + "NR1BEG2", + "IMUX_L15", + "SE6BEG0", "NE2END_S3_0", - "GND_WIRE", - "NE2END0", + "SW2END_N0_3", + "NE6END2", + "GCLK_L_B7_EAST", + "NN6A1", + "EE2END3", + "WW4A3", + "NN6C0", + "NW6BEG3", + "NN6D0", + "SL1END0", + "NE2BEG2", + "WR1END_S1_0", + "NN6A3", + "WW4C3", + "NW6BEG2", + "WR1END0", + "SS2BEG2", + "NW6END3", + "GCLK_L_B10_WEST", + "NL1END2", + "NN6E3", + "NN6END_S1_0", + "SW6B2", + "SS6A2", + "SS6BEG2", + "BYP_BOUNCE0", + "WL1BEG0", + "EE2A3", + "NE6A2", + "LH4", + "SS6C3", + "SL1BEG0", + "SW6B1", + "NN6B1", + "NR1END3", + "FAN_L5", + "ER1END3", + "FAN_ALT4", + "IMUX_L43", + "FAN_BOUNCE2", + "LH1", + "LH10", + "NN6C3", + "SW6END1", + "SE6E1", + "BYP_BOUNCE5", + "SE6A2", + "NN2A0", + "GCLK_L_B0", + "WW2A0", + "LOGIC_OUTS_L3", + "FAN_BOUNCE7", + "NN2END0", + "BYP_L7", + "NR1BEG0", + "WW4BEG3", + "WW2END_N0_3", + "LOGIC_OUTS_L16", + "SS6C2", + "LV_L18", + "IMUX_L34", + "FAN_ALT3", + "EE4A1", + "MONITOR_N", + "FAN_ALT6", + "GCLK_L_B4", "SW2END3", - "SW6C3", - "NE6C3", - "WL1END0", + "WW4B2", + "WW2END1", + "IMUX_L29", + "NN6C1", + "EE4END2", + "EE2END1", + "NW6B1", + "LV_L8", + "ER1END0", + "NE2BEG3", + "IMUX_L19", + "LOGIC_OUTS_L1", + "SW2END0", + "BYP_L1", + "VCC_WIRE", + "LOGIC_OUTS_L13", + "WW2BEG1", + "GCLK_L_B1", + "WL1END2", + "EE2BEG3", + "FAN_ALT0", + "EE4END1", + "LV_L3", + "NR1END2", + "SS6D3", + "LOGIC_OUTS_L22", + "SE6B2", + "NW2BEG0", + "NR1END0", + "SE6C3", + "NW2A3", + "IMUX_L18", + "NN6E0", + "SW2A1", "IMUX_L11", - "WW2END0", + "NL1BEG_N3", + "NE2END2", + "SW2BEG0", + "ER1END1", + "SW6E2", + "SS6C0", + "LOGIC_OUTS_L8", + "NE6D0", + "NW2BEG1", + "BYP_L0", + "NW6C1", + "NE6E3", + "NW2A1", + "FAN_BOUNCE3", + "NW6D2", "SW6E0", - "SW2A0", - "EE4C0", - "NN2A2", - "IMUX_L22", + "SE6E0", + "EE4A2", + "IMUX_L10", + "ER1BEG3", + "NL1BEG0", "EL1BEG2", - "SW2END2" + "SS6D2", + "SW2BEG1", + "SS6A1", + "WR1BEG2", + "LV_L9", + "SS6B0", + "BYP_BOUNCE_N3_2", + "WW4END0", + "WW2END3", + "WR1BEG_S0", + "WR1BEG3", + "LOGIC_OUTS_L23", + "LV_L17", + "IMUX_L21", + "SW6A1", + "SW6END2", + "SS6END1", + "SS2END3", + "GCLK_L_B10_EAST", + "SL1BEG2", + "SW6BEG1", + "BYP_BOUNCE6", + "SS6BEG1", + "NW6C2", + "NN2A3", + "NE6D2", + "IMUX_L27", + "IMUX_L25", + "LOGIC_OUTS_L6", + "EE4C2", + "IMUX_L28", + "WW4B3", + "EE4B3", + "BYP_ALT1", + "SE2BEG1", + "SE6END1", + "SS6BEG0", + "NW6E3", + "SS2END_N0_3", + "BYP_L2", + "FAN_BOUNCE5", + "LOGIC_OUTS_L21", + "WW2END2", + "SR1END_N3_3", + "INT_PHASER_TO_IO_OCLKDIV", + "NN2END2", + "SW6D2", + "CTRL_L0", + "BYP_BOUNCE2", + "LH3", + "NW6D0", + "NE2A2", + "LOGIC_OUTS_L17", + "NE6E2", + "SW6END3", + "NE6END3", + "WL1END1", + "IMUX_L24", + "FAN_BOUNCE_S3_0", + "BYP_L6", + "EE4B0", + "GCLK_L_B7", + "BYP_BOUNCE7", + "NE6A3", + "SS6B2", + "ER1BEG_S0", + "BYP_L5", + "WW2BEG2", + "LH11", + "NN2A1", + "NE6D3", + "EE4BEG2", + "NW6END2", + "WW4C2", + "WW4B0", + "WR1BEG1", + "NN6A2", + "NW6D3", + "INT_DQS_IOTOPHASER", + "EE2A0", + "ER1BEG0", + "LOGIC_OUTS_L2", + "NE6B3", + "GCLK_L_B10", + "LH6", + "NN6A0", + "WW4BEG1", + "EE4BEG1", + "IMUX_L1", + "SW6BEG0", + "IMUX_L40", + "EE4C1", + "SW6END_N0_3", + "CLK_L0", + "IMUX_L32", + "LH5", + "LOGIC_OUTS_L11", + "LV_L12", + "INT_PHASER_TO_IO_ICLK", + "SW6C2", + "LV_L13", + "WW2A2", + "SW2A2", + "BYP_ALT3", + "WW4END1", + "SS2BEG1", + "SS6A3", + "IMUX_L45", + "SE6BEG3", + "LH9", + "LV_L1", + "FAN_L2", + "SL1BEG3", + "NW6A0", + "LVB_L7", + "IMUX_L0", + "LOGIC_OUTS_L5", + "GCLK_L_B9_WEST", + "BYP_BOUNCE4", + "WR1BEG0", + "SR1BEG2", + "NW2END0", + "GCLK_L_B5", + "BYP_ALT2", + "SW2END2", + "NE6B1", + "NW6END0", + "NN6BEG2", + "SS6E2", + "EE4BEG0", + "SE6END2", + "FAN_BOUNCE0", + "SL1END1", + "INT_PHASER_TO_IO_OCLK", + "SR1BEG3", + "NW6A1", + "LVB_L5", + "WW4A0", + "EE2A1", + "SS6D1", + "GFAN0", + "FAN_BOUNCE1", + "BYP_BOUNCE1", + "IMUX_L20", + "SE6END3", + "SR1BEG1", + "SE2END2", + "WR1END2", + "NW6BEG0", + "LH2", + "SS2END2", + "SE2A2", + "SW6A2", + "SR1END3", + "NW6END_S0_0", + "WW4A1", + "SW2END1", + "SE6BEG2", + "SE6BEG1", + "WW4BEG2", + "SS2A1", + "ER1END2", + "SW6E3", + "GCLK_L_B8_EAST", + "FAN_BOUNCE_S3_4", + "IMUX_L6", + "ER1END_N3_3", + "IMUX_L3", + "LVB_L1", + "LV_L5", + "IMUX_L38", + "NN6C2", + "FAN_L1", + "SE6E3", + "IMUX_L17", + "NN6D2", + "LV_L14", + "LVB_L8", + "WW4C1", + "LH12", + "SS2END1", + "FAN_L4", + "BYP_L3", + "IMUX_L2", + "NL1END_S3_0", + "IMUX_L5", + "SW6C0", + "WL1BEG_N3", + "SR1END1", + "IMUX_L42", + "LOGIC_OUTS_L19", + "NN2BEG2", + "SE6C0", + "IMUX_L37", + "IMUX_L16", + "EL1END2", + "NN6E2", + "SS6D0", + "FAN_L6", + "SS6END3", + "BYP_BOUNCE_N3_7", + "WW2A1", + "SL1END2", + "NL1END1", + "NN6D3", + "SW6D1", + "NW2A0", + "SE6C2", + "SE6END0", + "SW2A0", + "WW4C0", + "EE4C3", + "NW6D1", + "BYP_ALT4", + "NN6END2", + "WW4END2", + "WW4END_S0_0", + "NN2END1", + "LH8", + "SE6D2", + "NR1BEG1", + "NE2A3", + "EE4B2", + "NN6D1", + "CLK_L1", + "LOGIC_OUTS_L15", + "LOGIC_OUTS_L7", + "LOGIC_OUTS_L12", + "FAN_ALT5", + "EL1END3", + "EL1BEG3", + "LOGIC_OUTS_L18", + "NN6B3", + "FAN_L7", + "SE2END0", + "BYP_ALT5", + "FAN_ALT1", + "SW2A3", + "SS2A0", + "FAN_BOUNCE_S3_6", + "LV_L6", + "WL1BEG2", + "FAN_ALT7", + "NW2BEG3", + "NW2END2", + "NE6C3", + "GFAN1", + "LV_L11", + "EE4END3", + "NE2BEG0", + "WW4BEG0", + "WR1END3", + "SE2BEG3", + "LVB_L0", + "SS2END0", + "INT_PHASER_TO_IO_OCLK1X_90", + "SS6E1", + "BYP_L4", + "SE2BEG0", + "LVB_L4", + "SW6A3", + "EL1BEG1", + "SW6E1", + "ER1BEG1", + "SW6B3", + "NE2A1", + "LOGIC_OUTS_L9", + "NW6A3", + "IMUX_L47", + "GND_WIRE", + "SW6D3", + "NW6C0", + "SS6END_N0_3", + "EE2A2", + "LVB_L11", + "NE6D1", + "FAN_BOUNCE4", + "SE2END3", + "NW2END_S0_0", + "EE4A3", + "LV_L15", + "IMUX_L36", + "SS6B3", + "NN6BEG1", + "LH7", + "SE2A0", + "LVB_L2", + "NE6B0", + "NL1BEG1", + "GCLK_L_B9_EAST", + "LOGIC_OUTS_L20", + "FAN_L0", + "WW2END0", + "NR1BEG3", + "LVB_L9", + "SS6E3", + "IMUX_L44", + "SS2A2", + "GCLK_L_B6", + "NE2END1", + "SE6E2", + "EL1END_S3_0", + "NE6BEG1", + "NL1BEG2", + "WW4A2", + "GCLK_L_B3", + "LV_L7", + "ER1BEG2", + "NL1END0", + "SS6C1", + "GCLK_L_B9", + "IMUX_L12", + "NN2BEG1", + "NE6BEG2", + "WW4B1", + "SE6D0", + "NN2BEG3", + "NE6E0", + "IMUX_L41", + "EL1BEG0", + "EL1END1", + "NE2BEG1", + "NN6END0", + "GCLK_L_B7_WEST", + "LV_L0", + "SW6C1", + "LOGIC_OUTS_L0", + "NN6E1", + "NN6B0", + "NE6B2", + "MONITOR_P", + "NW6BEG1", + "SW2BEG3", + "FAN_BOUNCE6", + "NW6B2", + "LOGIC_OUTS_L14", + "NW6B3", + "NN2BEG0", + "LOGIC_OUTS_L10", + "WW4END3", + "SS6END0", + "NE6E1", + "INT_PHASER_TO_IO_ICLKDIV", + "IMUX_L26", + "SS6E0", + "SS2BEG0", + "SE6C1", + "SW6END0", + "BYP_BOUNCE_N3_6", + "SE6D3", + "NE6END1", + "IMUX_L14", + "IMUX_L31", + "GCLK_L_B8", + "SE2BEG2", + "EE2BEG2", + "NW6A2", + "SR1END2", + "EE4C0", + "NE6A0", + "NW6E2", + "NN2END3", + "IMUX_L39", + "EE4B1", + "EE4A0", + "NW2A2", + "LH0", + "SE2END1", + "IMUX_L46", + "NE2END0", + "SL1END3", + "SE6A1", + "WL1END0", + "WL1END_N1_3", + "WR1END1", + "GCLK_L_B6_EAST", + "SE6B3", + "IMUX_L7", + "NN6BEG0", + "SS2A3", + "WW2A3", + "LV_L10", + "NW6E1", + "IMUX_L33", + "WL1BEG3", + "EE4BEG3", + "IMUX_L35", + "IMUX_L22", + "SW6BEG2", + "EL1BEG_N3", + "SW6D0", + "NN6B2", + "BYP_BOUNCE3", + "SE6D1", + "NE6C2", + "IMUX_L8", + "NW6B0", + "SS6BEG3", + "NW6END1", + "FAN_L3", + "GCLK_L_B11_WEST", + "NE2END3", + "GCLK_L_B2", + "NW2END1", + "SW6C3", + "SS2BEG3", + "NE6BEG3", + "NE2A0", + "BYP_ALT0", + "LVB_L12", + "NW6C3", + "GCLK_L_B11_EAST", + "SS6END2", + "LV_L2", + "SW2BEG2", + "NE6A1", + "GCLK_L_B8_WEST", + "SE2A1", + "EE2END0", + "LOGIC_OUTS_L4", + "EE4END0", + "NN6BEG3", + "SW6BEG3", + "IMUX_L4", + "WW2BEG3", + "NR1END1", + "FAN_ALT2", + "WW2BEG0", + "IMUX_L23", + "NW2END3", + "IMUX_L9", + "LV_L16", + "IMUX_L13", + "WL1END3", + "NE6BEG0", + "IMUX_L30", + "LVB_L6", + "SR1BEG_S0", + "CTRL_L1", + "EL1END0", + "NW6E0", + "SW6B0", + "SS6A0", + "SE2A3", + "NE6C1", + "SS6B1", + "GCLK_L_B6_WEST", + "EE2BEG0", + "NN2A2", + "SE6A0", + "NE6END0", + "NN2END_S2_0", + "BYP_ALT7", + "WL1BEG1", + "SE6A3" ], + "tile_type": "INT_L", "sites": [ { - "prefix": "TIEOFF", - "y_coord": 0, - "type": "TIEOFF", "site_pins": { "HARD0": "GND_WIRE", "HARD1": "VCC_WIRE" }, + "type": "TIEOFF", + "prefix": "TIEOFF", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 } - ], - "pips": { - "INT_L.SE6END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_3->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_2->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT3->>FAN_BOUNCE3": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE3", - "is_directional": "1", - "src_wire": "FAN_ALT3", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.WW4END_S0_0->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.LVB_L12->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LVB_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.NW6END_S0_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.SR1END_N3_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT5->>FAN_L5": { - "can_invert": "0", - "dst_wire": "FAN_L5", - "is_directional": "1", - "src_wire": "FAN_ALT5", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.WW4END_S0_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B11_WEST->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B11_WEST", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_2->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.NN2END_S2_0->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_3->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_6->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_3->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE2->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.LH0->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SS6END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "SS6END_N0_3", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.ER1END_N3_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "ER1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>LV_L0": { - "can_invert": "0", - "dst_wire": "LV_L0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.LVB_L12->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LVB_L12", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B10_WEST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B10_WEST", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.NL1END_S3_0->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.WR1END_S1_0->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B8_WEST->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B8_WEST", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_6->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT4->>FAN_L4": { - "can_invert": "0", - "dst_wire": "FAN_L4", - "is_directional": "1", - "src_wire": "FAN_ALT4", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B10_WEST->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B10_WEST", - "is_pseudo": "0" - }, - "INT_L.NL1END_S3_0->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B9->>GCLK_L_B9_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B9_EAST", - "is_directional": "1", - "src_wire": "GCLK_L_B9", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE6->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.WL1END_N1_3->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.SW6END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "SW6END_N0_3", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE6->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT4->>BYP_BOUNCE4": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE4", - "is_directional": "1", - "src_wire": "BYP_ALT4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.LH6->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.SS2END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_3->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.LH0->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.LH6->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT2->>BYP_BOUNCE2": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE2", - "is_directional": "1", - "src_wire": "BYP_ALT2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE2->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>LV_L0": { - "can_invert": "0", - "dst_wire": "LV_L0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B7_WEST->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B7_WEST", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B5->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B5", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT3->>BYP_L3": { - "can_invert": "0", - "dst_wire": "BYP_L3", - "is_directional": "1", - "src_wire": "BYP_ALT3", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.LVB_L0->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LVB_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.SW6END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "SW6END_N0_3", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_6->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE2->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.SS2END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B11_WEST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B11_WEST", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B6->>GCLK_L_B6_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B6_WEST", - "is_directional": "1", - "src_wire": "GCLK_L_B6", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT7->>FAN_BOUNCE7": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE7", - "is_directional": "1", - "src_wire": "FAN_ALT7", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B4->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B4", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT1->>FAN_BOUNCE1": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE1", - "is_directional": "1", - "src_wire": "FAN_ALT1", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_2->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SW2END_N0_3->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_2->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B6_WEST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B6_WEST", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B0->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B0", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.SR1END_N3_3->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.WL1END_N1_3->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_2->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B11_WEST->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B11_WEST", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B10->>GCLK_L_B10_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B10_WEST", - "is_directional": "1", - "src_wire": "GCLK_L_B10", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.LH12->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B11->>GCLK_L_B11_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B11_WEST", - "is_directional": "1", - "src_wire": "GCLK_L_B11", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_2->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.WR1END_S1_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.LH12->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT3->>FAN_L3": { - "can_invert": "0", - "dst_wire": "FAN_L3", - "is_directional": "1", - "src_wire": "FAN_ALT3", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B5->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B5", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE2->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B8_WEST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B8_WEST", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE6->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.WR1END_S1_0->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_2->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT3->>BYP_BOUNCE3": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE3", - "is_directional": "1", - "src_wire": "BYP_ALT3", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.WL1END_N1_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_L.SW2END_N0_3->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.LH6->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT7->>FAN_L7": { - "can_invert": "0", - "dst_wire": "FAN_L7", - "is_directional": "1", - "src_wire": "FAN_ALT7", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.LV_L0<<->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "0", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LH0->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE6->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_3->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B9_WEST->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B9_WEST", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.NL1END_S3_0->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE2->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT1->>BYP_BOUNCE1": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE1", - "is_directional": "1", - "src_wire": "BYP_ALT1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.SR1END_N3_3->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.LV_L0<<->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "0", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE4->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B8->>GCLK_L_B8_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B8_WEST", - "is_directional": "1", - "src_wire": "GCLK_L_B8", - "is_pseudo": "0" - }, - "INT_L.LH0->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_2->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>LV_L0": { - "can_invert": "0", - "dst_wire": "LV_L0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.LH6->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.WW4END_S0_0->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.GND_WIRE->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GND_WIRE", - "is_pseudo": "0" - }, - "INT_L.EL1END_S3_0->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "EL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT5->>FAN_BOUNCE5": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE5", - "is_directional": "1", - "src_wire": "FAN_ALT5", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B11->>GCLK_L_B11_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B11_EAST", - "is_directional": "1", - "src_wire": "GCLK_L_B11", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_2->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.LVB_L12->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LVB_L12", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B5->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B5", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.LVB_L0->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LVB_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B6_WEST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B6_WEST", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.SR1END_N3_3->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B7->>GCLK_L_B7_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B7_EAST", - "is_directional": "1", - "src_wire": "GCLK_L_B7", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.WR1END_S1_0->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B11_WEST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B11_WEST", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_3->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B6_WEST->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B6_WEST", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.GND_WIRE->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GND_WIRE", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B4->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_2->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.NN6END_S1_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "NN6END_S1_0", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B2->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.NN2END_S2_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_2->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE2->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.LH6->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT0->>BYP_BOUNCE0": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE0", - "is_directional": "1", - "src_wire": "BYP_ALT0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE2->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.LH0<<->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "0", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT6->>BYP_BOUNCE6": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE6", - "is_directional": "1", - "src_wire": "BYP_ALT6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.WL1END_N1_3->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.ER1END_N3_3->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "ER1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT5->>BYP_L5": { - "can_invert": "0", - "dst_wire": "BYP_L5", - "is_directional": "1", - "src_wire": "BYP_ALT5", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.SS2END_N0_3->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NW6END_S0_0->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LH0->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.NN2END_S2_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.LVB_L0<<->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "0", - "src_wire": "LVB_L0", - "is_pseudo": "0" - }, - "INT_L.LVB_L0->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LVB_L0", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.LVB_L0->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LVB_L0", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B10_WEST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B10_WEST", - "is_pseudo": "0" - }, - "INT_L.EL1END_S3_0->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "EL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NE2END_S3_0->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "NE2END_S3_0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B5->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B5", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B7->>GCLK_L_B7_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B7_WEST", - "is_directional": "1", - "src_wire": "GCLK_L_B7", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B10->>GCLK_L_B10_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B10_EAST", - "is_directional": "1", - "src_wire": "GCLK_L_B10", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.LH12->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.NW6END_S0_0->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT6->>BYP_L6": { - "can_invert": "0", - "dst_wire": "BYP_L6", - "is_directional": "1", - "src_wire": "BYP_ALT6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.LVB_L12->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LVB_L12", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.NE2END_S3_0->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "NE2END_S3_0", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.LH6->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.LH12->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.SS2END_N0_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>LV_L0": { - "can_invert": "0", - "dst_wire": "LV_L0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.WR1END_S1_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.SS2END_N0_3->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.WW4END_S0_0->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE6->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LVB_L12->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LVB_L12", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.EL1END_S3_0->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "EL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.NN6END_S1_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "NN6END_S1_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT1->>BYP_L1": { - "can_invert": "0", - "dst_wire": "BYP_L1", - "is_directional": "1", - "src_wire": "BYP_ALT1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B4->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.WW4END_S0_0->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SR1END_N3_3->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_2->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.LV_L0<<->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "0", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.WR1END_S1_0->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.NW6END_S0_0->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT2->>BYP_L2": { - "can_invert": "0", - "dst_wire": "BYP_L2", - "is_directional": "1", - "src_wire": "BYP_ALT2", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.LH0->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B7_WEST->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B7_WEST", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B10_WEST->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B10_WEST", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SW6END_N0_3->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "SW6END_N0_3", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT4->>FAN_BOUNCE4": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE4", - "is_directional": "1", - "src_wire": "FAN_ALT4", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_2->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>LV_L0": { - "can_invert": "0", - "dst_wire": "LV_L0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_3->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT0->>FAN_L0": { - "can_invert": "0", - "dst_wire": "FAN_L0", - "is_directional": "1", - "src_wire": "FAN_ALT0", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B9_WEST->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B9_WEST", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.WL1END_N1_3->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_2->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.LH12->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NL1END_S3_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.LH0->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT2->>FAN_BOUNCE2": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE2", - "is_directional": "1", - "src_wire": "FAN_ALT2", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.NE2END_S3_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NE2END_S3_0", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B1->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.WR1END_S1_0->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT1->>FAN_L1": { - "can_invert": "0", - "dst_wire": "FAN_L1", - "is_directional": "1", - "src_wire": "FAN_ALT1", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>LV_L0": { - "can_invert": "0", - "dst_wire": "LV_L0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_3->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B9_WEST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B9_WEST", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.LV_L9->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LV_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.LV_L18<<->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "0", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B7_WEST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B7_WEST", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B9->>GCLK_L_B9_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B9_WEST", - "is_directional": "1", - "src_wire": "GCLK_L_B9", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B1->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B1", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.NL1END_S3_0->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.SS6END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "SS6END_N0_3", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.SW2END_N0_3->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.LVB_L0->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LVB_L0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B2->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B2", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.LH12->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.SR1END_N3_3->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.WW4END_S0_0->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.LH6->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B3->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B3", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_2->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B0->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B0", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.SW2END_N0_3->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE2->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT4->>BYP_L4": { - "can_invert": "0", - "dst_wire": "BYP_L4", - "is_directional": "1", - "src_wire": "BYP_ALT4", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.LH12->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LH0->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.SW2END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE6->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.NN2END_S2_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B1->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B7_WEST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B7_WEST", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.LVB_L12->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LVB_L12", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.LH12->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_6->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.WR1END_S1_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.LH6->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE6->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B8_WEST->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B8_WEST", - "is_pseudo": "0" - }, - "INT_L.LH6->>LV_L0": { - "can_invert": "0", - "dst_wire": "LV_L0", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.WW4END_S0_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT0->>BYP_L0": { - "can_invert": "0", - "dst_wire": "BYP_L0", - "is_directional": "1", - "src_wire": "BYP_ALT0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.NN2END_S2_0->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.WL1END_N1_3->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END_N0_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE2->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.SW2END_N0_3->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.WW4END_S0_0->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.LH12->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT2->>FAN_L2": { - "can_invert": "0", - "dst_wire": "FAN_L2", - "is_directional": "1", - "src_wire": "FAN_ALT2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.SW6END_N0_3->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "SW6END_N0_3", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.LV_L18<<->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "0", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B8->>GCLK_L_B8_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B8_EAST", - "is_directional": "1", - "src_wire": "GCLK_L_B8", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.LVB_L12->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LVB_L12", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B3->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.LVB_L12->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LVB_L12", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B4->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B4", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B2->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT6->>FAN_BOUNCE6": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE6", - "is_directional": "1", - "src_wire": "FAN_ALT6", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NL1END_S3_0->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.LV_L18->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LV_L18", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.EE4END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NW6END_S0_0->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.LH6->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LVB_L0->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LVB_L0", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.WL1END_N1_3->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END_S3_0->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "NE2END_S3_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.WL1END_N1_3->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.SL1END3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT0->>FAN_BOUNCE0": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE0", - "is_directional": "1", - "src_wire": "FAN_ALT0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE6->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LH6->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B8_WEST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B8_WEST", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.EL1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE2->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.LVB_L0->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LVB_L0", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.NN6END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B6_WEST->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B6_WEST", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B6->>GCLK_L_B6_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_L_B6_EAST", - "is_directional": "1", - "src_wire": "GCLK_L_B6", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.LH0->>LVB_L12": { - "can_invert": "0", - "dst_wire": "LVB_L12", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NE6END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_L.NW2END_S0_0->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.ER1END_N3_3->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "ER1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B3->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B9_WEST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_L_B9_WEST", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.SR1END_N3_3->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.ER1END_N3_3->>IMUX_L0": { - "can_invert": "0", - "dst_wire": "IMUX_L0", - "is_directional": "1", - "src_wire": "ER1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.NN2END_S2_0->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT7->>BYP_BOUNCE7": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE7", - "is_directional": "1", - "src_wire": "BYP_ALT7", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_4->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE6->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.NL1END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.NE2END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.SE2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE6->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE6", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.NE6END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B3->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B3", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.SL1END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.EL1END0->>IMUX_L17": { - "can_invert": "0", - "dst_wire": "IMUX_L17", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.SE6END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NW6END_S0_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.LH0->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>IMUX_L10": { - "can_invert": "0", - "dst_wire": "IMUX_L10", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L4->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L4", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.ER1END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_6->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE2->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L21->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L21", - "is_pseudo": "0" - }, - "INT_L.SE6END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.SS6END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NW6END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.SW2END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.NL1END_S3_0->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NN2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.SR1BEG_S0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.ER1END0->>LV_L0": { - "can_invert": "0", - "dst_wire": "LV_L0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_L.ER1END2->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>CTRL_L1": { - "can_invert": "0", - "dst_wire": "CTRL_L1", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B0->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "GCLK_L_B0", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.LH12->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.NE6END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L10->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L10", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.SS6END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L9->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L9", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.EL1END1->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.SE6END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L30": { - "can_invert": "0", - "dst_wire": "IMUX_L30", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L28": { - "can_invert": "0", - "dst_wire": "IMUX_L28", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE5->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.FAN_ALT6->>FAN_L6": { - "can_invert": "0", - "dst_wire": "FAN_L6", - "is_directional": "1", - "src_wire": "FAN_ALT6", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.NE2END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>IMUX_L44": { - "can_invert": "0", - "dst_wire": "IMUX_L44", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L7->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L7", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE2->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SS6END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.NN6END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>IMUX_L39": { - "can_invert": "0", - "dst_wire": "IMUX_L39", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L14->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L14", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.NN6END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>CLK_L0": { - "can_invert": "0", - "dst_wire": "CLK_L0", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L18": { - "can_invert": "0", - "dst_wire": "IMUX_L18", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>LV_L0": { - "can_invert": "0", - "dst_wire": "LV_L0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L38": { - "can_invert": "0", - "dst_wire": "IMUX_L38", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L13->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L13", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L3": { - "can_invert": "0", - "dst_wire": "IMUX_L3", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L47": { - "can_invert": "0", - "dst_wire": "IMUX_L47", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.SW6END0->>LV_L18": { - "can_invert": "0", - "dst_wire": "LV_L18", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_7->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_L.SE2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L17->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L17", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.NL1END_S3_0->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L27": { - "can_invert": "0", - "dst_wire": "IMUX_L27", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.SE2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_L.SS2END_N0_3->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>IMUX_L36": { - "can_invert": "0", - "dst_wire": "IMUX_L36", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE7->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_L.SS6END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NE2END3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_6->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.WW4END2->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L41": { - "can_invert": "0", - "dst_wire": "IMUX_L41", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.SR1END_N3_3->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_L.NN6END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_L.WR1END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L16->>IMUX_L21": { - "can_invert": "0", - "dst_wire": "IMUX_L21", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L16", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L20->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L20", - "is_pseudo": "0" - }, - "INT_L.NL1END2->>IMUX_L20": { - "can_invert": "0", - "dst_wire": "IMUX_L20", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_L.NR1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE2->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L3", - "is_pseudo": "0" - }, - "INT_L.NR1END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.SW2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.NE2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_L.SR1END2->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.WW2END1->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.SR1END1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.WR1END2->>IMUX_L13": { - "can_invert": "0", - "dst_wire": "IMUX_L13", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L18->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L18", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L33": { - "can_invert": "0", - "dst_wire": "IMUX_L33", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B2->>CLK_L1": { - "can_invert": "0", - "dst_wire": "CLK_L1", - "is_directional": "1", - "src_wire": "GCLK_L_B2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L29": { - "can_invert": "0", - "dst_wire": "IMUX_L29", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.SW2END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L15->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L15", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L2", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>LVB_L0": { - "can_invert": "0", - "dst_wire": "LVB_L0", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE2->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.NW6END3->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>IMUX_L7": { - "can_invert": "0", - "dst_wire": "IMUX_L7", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.WL1END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NW2END1->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.WW2END_N0_3->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_L.LVB_L0->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LVB_L0", - "is_pseudo": "0" - }, - "INT_L.EE4END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>IMUX_L32": { - "can_invert": "0", - "dst_wire": "IMUX_L32", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.WL1END2->>IMUX_L37": { - "can_invert": "0", - "dst_wire": "IMUX_L37", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_L.EE2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L1": { - "can_invert": "0", - "dst_wire": "IMUX_L1", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.WW4END1->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_L.WW2END2->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_L.LH6->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_L.NW6END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_L.SS2END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_L.EE2END1->>IMUX_L42": { - "can_invert": "0", - "dst_wire": "IMUX_L42", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_L.LV_L0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LV_L0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.WR1END3->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B1->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B1", - "is_pseudo": "0" - }, - "INT_L.SE6END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_L.SL1END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_L.NW6END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE0->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_L.NW2END0->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L5->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L5", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L6->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L6", - "is_pseudo": "0" - }, - "INT_L.NL1BEG_N3->>IMUX_L45": { - "can_invert": "0", - "dst_wire": "IMUX_L45", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L23->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L23", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L22->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L22", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE_N3_6->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_L.WW4END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE4->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L46": { - "can_invert": "0", - "dst_wire": "IMUX_L46", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NR1END1->>IMUX_L2": { - "can_invert": "0", - "dst_wire": "IMUX_L2", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_L.NR1END3->>IMUX_L31": { - "can_invert": "0", - "dst_wire": "IMUX_L31", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.SE2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_L.SW6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_6->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.NN2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_L.EE4END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_L.WW2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_L.NE6END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_L.WR1END0->>IMUX_L16": { - "can_invert": "0", - "dst_wire": "IMUX_L16", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE_S3_0->>IMUX_L14": { - "can_invert": "0", - "dst_wire": "IMUX_L14", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_L.GCLK_L_B0->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_L_B0", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT5->>BYP_BOUNCE5": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE5", - "is_directional": "1", - "src_wire": "BYP_ALT5", - "is_pseudo": "0" - }, - "INT_L.EL1END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L12": { - "can_invert": "0", - "dst_wire": "IMUX_L12", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE3->>IMUX_L11": { - "can_invert": "0", - "dst_wire": "IMUX_L11", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_L.SW2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.NN2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.NN2END3->>IMUX_L6": { - "can_invert": "0", - "dst_wire": "IMUX_L6", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_L.WW4END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.ER1END1->>IMUX_L43": { - "can_invert": "0", - "dst_wire": "IMUX_L43", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_L.SS2END0->>IMUX_L40": { - "can_invert": "0", - "dst_wire": "IMUX_L40", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE5->>IMUX_L9": { - "can_invert": "0", - "dst_wire": "IMUX_L9", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_L.GFAN1->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.SR1END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L8->>IMUX_L25": { - "can_invert": "0", - "dst_wire": "IMUX_L25", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L8", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L1->>IMUX_L19": { - "can_invert": "0", - "dst_wire": "IMUX_L19", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L1", - "is_pseudo": "0" - }, - "INT_L.WW2END3->>IMUX_L23": { - "can_invert": "0", - "dst_wire": "IMUX_L23", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_L.EE4END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_L.SW6END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_L.SW2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.SS2END2->>IMUX_L22": { - "can_invert": "0", - "dst_wire": "IMUX_L22", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.GFAN0->>CTRL_L0": { - "can_invert": "0", - "dst_wire": "CTRL_L0", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_L.SL1END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>IMUX_L26": { - "can_invert": "0", - "dst_wire": "IMUX_L26", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.SW6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L19->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L19", - "is_pseudo": "0" - }, - "INT_L.NW2END3->>IMUX_L5": { - "can_invert": "0", - "dst_wire": "IMUX_L5", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_L.EE2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_L.BYP_BOUNCE1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.VCC_WIRE->>IMUX_L24": { - "can_invert": "0", - "dst_wire": "IMUX_L24", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_L.SS2END1->>IMUX_L4": { - "can_invert": "0", - "dst_wire": "IMUX_L4", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_L.WL1END3->>IMUX_L15": { - "can_invert": "0", - "dst_wire": "IMUX_L15", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_L.WL1END1->>IMUX_L35": { - "can_invert": "0", - "dst_wire": "IMUX_L35", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_L.FAN_BOUNCE2->>IMUX_L8": { - "can_invert": "0", - "dst_wire": "IMUX_L8", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_L.NW2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_L.BYP_ALT7->>BYP_L7": { - "can_invert": "0", - "dst_wire": "BYP_L7", - "is_directional": "1", - "src_wire": "BYP_ALT7", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L12->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L12", - "is_pseudo": "0" - }, - "INT_L.LOGIC_OUTS_L11->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS_L11", - "is_pseudo": "0" - }, - "INT_L.EL1END_S3_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "EL1END_S3_0", - "is_pseudo": "0" - }, - "INT_L.NL1END1->>IMUX_L34": { - "can_invert": "0", - "dst_wire": "IMUX_L34", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - } - }, - "tile_type": "INT_L" + ] } \ No newline at end of file diff --git a/artix7/tile_type_INT_R.json b/artix7/tile_type_INT_R.json index 7bc1cdb..26f9221 100644 --- a/artix7/tile_type_INT_R.json +++ b/artix7/tile_type_INT_R.json @@ -1,26779 +1,26779 @@ { + "pips": { + "INT_R.SS2END2->>BYP_ALT2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.LOGIC_OUTS3->>WL1BEG2": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.NN2END_S2_0->>SR1BEG_S0": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.LOGIC_OUTS20->>IMUX12": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.NR1END3->>IMUX31": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.LOGIC_OUTS0->>SW2BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.SW2END3->>SR1BEG_S0": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.SE2END3->>IMUX15": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.NW6END2->>WL1BEG0": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.NL1END_S3_0->>IMUX15": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.NE2END2->>NW6BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.LOGIC_OUTS9->>SW2BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.LOGIC_OUTS18->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.EL1END0->>IMUX32": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.GCLK_B0->>GCLK_B0_EAST": { + "src_wire": "GCLK_B0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B0_EAST" + }, + "INT_R.SR1END1->>BYP_ALT2": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.LOGIC_OUTS9->>ER1BEG2": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.SE6END2->>NE6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.LOGIC_OUTS17->>NW6BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.NL1END_S3_0->>FAN_ALT3": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.NW2END_S0_0->>SS6BEG3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.SW2END0->>BYP_ALT0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.ER1END2->>CTRL1": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.WW2END_N0_3->>IMUX16": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.ER1END2->>IMUX29": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.LOGIC_OUTS20->>NR1BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.WW2END_N0_3->>NN6BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.SS2END0->>WL1BEG_N3": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.GCLK_B7->>GFAN0": { + "src_wire": "GCLK_B7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.LOGIC_OUTS11->>IMUX14": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.NE2END0->>FAN_ALT4": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.WW4END3->>NN2BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.LOGIC_OUTS15->>EE2BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.NR1END3->>NR1BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.LOGIC_OUTS6->>SS2BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.NN2END2->>BYP_ALT2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.EL1END_S3_0->>IMUX47": { + "src_wire": "EL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.ER1END1->>IMUX34": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LH6->>LV18": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.EE2END0->>IMUX40": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.LOGIC_OUTS22->>SE2BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.WL1END1->>NW2BEG2": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.FAN_ALT1->>FAN_BOUNCE1": { + "src_wire": "FAN_ALT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE1" + }, + "INT_R.LOGIC_OUTS4->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.SL1END3->>SE2BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.NN2END1->>BYP_ALT1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.BYP_BOUNCE2->>IMUX22": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.NR1END0->>LV0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV0" + }, + "INT_R.LOGIC_OUTS0->>SE6BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.EL1END2->>IMUX21": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.NN2END3->>EL1BEG2": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.EE4END0->>SS6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.WW2END3->>IMUX47": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.EE2END2->>EE4BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.FAN_BOUNCE7->>BYP_ALT0": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.WW2END2->>IMUX45": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.LOGIC_OUTS8->>NE2BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.VCC_WIRE->>BYP_ALT1": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.SL1END1->>FAN_ALT2": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.LOGIC_OUTS21->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.BYP_ALT1->>BYP_BOUNCE1": { + "src_wire": "BYP_ALT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE1" + }, + "INT_R.SE2END1->>NN6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.SW2END2->>IMUX29": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.WL1END3->>WL1BEG2": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.SS2END0->>IMUX18": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.SL1END2->>ER1BEG3": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.SS2END3->>ER1BEG_S0": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.NE2END1->>IMUX26": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.NE2END1->>IMUX18": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.EL1END3->>IMUX6": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.FAN_BOUNCE3->>IMUX45": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.LOGIC_OUTS5->>NE6BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.LOGIC_OUTS11->>IMUX30": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.GCLK_B4->>GCLK_B4_EAST": { + "src_wire": "GCLK_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B4_EAST" + }, + "INT_R.NR1END3->>IMUX6": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.SW2END0->>NW6BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.NN2END0->>IMUX40": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.NR1END1->>NL1BEG0": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.WW2END3->>IMUX39": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.LH0->>NE6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.NE6END0->>SL1BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX31": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.WL1END1->>WL1BEG0": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.NE2END_S3_0->>IMUX31": { + "src_wire": "NE2END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.LOGIC_OUTS2->>NW2BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.GCLK_B4->>GCLK_B4_WEST": { + "src_wire": "GCLK_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B4_WEST" + }, + "INT_R.NE2END3->>WW4BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.BYP_ALT4->>BYP_BOUNCE4": { + "src_wire": "BYP_ALT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE4" + }, + "INT_R.VCC_WIRE->>IMUX2": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.BYP_BOUNCE_N3_3->>FAN_ALT4": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.GFAN0->>IMUX34": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LOGIC_OUTS1->>EE4BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.EE2END1->>WR1BEG2": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX15": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.FAN_BOUNCE2->>IMUX24": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.WL1END2->>IMUX5": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.NL1END2->>NE2BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.LOGIC_OUTS17->>NW2BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.EE2END3->>EE4BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.WW2END0->>IMUX1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.NE6END3->>SE6BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.SW2END0->>SW2BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.FAN_BOUNCE3->>IMUX3": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.FAN_BOUNCE1->>CTRL0": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.SR1END1->>SR1BEG2": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.LOGIC_OUTS0->>WR1BEG1": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.ER1END1->>IMUX35": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.LOGIC_OUTS10->>SS2BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.NR1END3->>EL1BEG2": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.NN6END0->>EE4BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.ER1END0->>SE2BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.NW2END0->>IMUX24": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.SS6END2->>SE2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.LV0->>LVB12": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.EL1END3->>IMUX45": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.NN2END2->>NW6BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.NW6END3->>WL1BEG1": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.EE2END2->>SW6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.ER1END3->>IMUX15": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.GFAN0->>FAN_ALT2": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.EE4END1->>SE6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.WR1END2->>IMUX4": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.LOGIC_OUTS1->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.SE2END1->>IMUX3": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.SE6END2->>EE4BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.SE2END2->>IMUX13": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.LOGIC_OUTS2->>WW4BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.NW2END1->>IMUX9": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SL1END1->>WL1BEG0": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.LH6->>EE4BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.SS2END1->>IMUX20": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.LOGIC_OUTS12->>SW6BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.SW2END1->>WW4BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.EL1END0->>BYP_ALT0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.LOGIC_OUTS5->>IMUX34": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.EL1END1->>SE2BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.NN2END3->>NE6BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX35": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.NN2END1->>NL1BEG0": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.WW2END0->>IMUX42": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.WL1END2->>NW2BEG3": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.FAN_ALT2->>FAN_BOUNCE2": { + "src_wire": "FAN_ALT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE2" + }, + "INT_R.NN6END_S1_0->>SR1BEG_S0": { + "src_wire": "NN6END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.NN6END1->>EE2BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.SL1END1->>IMUX18": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.LOGIC_OUTS8->>IMUX25": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.SS2END1->>FAN_ALT7": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.NR1END0->>IMUX33": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.NN2END3->>FAN_ALT1": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.SL1END3->>IMUX23": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.NW6END0->>WR1BEG1": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.ER1END2->>SS2BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.WW2END1->>IMUX43": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.BYP_BOUNCE1->>IMUX27": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.NE2END0->>BYP_ALT0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.GCLK_B6->>GFAN1": { + "src_wire": "GCLK_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.ER1END3->>IMUX47": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.NE6END3->>LH0": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.SE6END0->>SE2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.BYP_BOUNCE1->>FAN_ALT6": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NE6END1->>NL1BEG0": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.WW4END3->>WR1BEG_S0": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.EE2END3->>IMUX23": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.LOGIC_OUTS8->>WW2BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.SE2END3->>SE6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.WW2END0->>IMUX41": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.NE6END2->>SE6BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.WW4END0->>WW4BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.NW6END1->>WW4BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.NR1END2->>IMUX21": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SL1END2->>BYP_ALT3": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.WL1END0->>BYP_ALT1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.LOGIC_OUTS19->>SR1BEG2": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.LV0->>NN6BEG0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.SE2END2->>NR1BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.GCLK_B3_EAST->>CLK0": { + "src_wire": "GCLK_B3_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.SE6END2->>NN6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.SE6END0->>SS2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.EE2END1->>SL1BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.LOGIC_OUTS3->>IMUX23": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX0": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.BYP_BOUNCE0->>IMUX12": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.LOGIC_OUTS4->>WW2BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.NL1BEG_N3->>EE2BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.SS2END3->>IMUX38": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.LOGIC_OUTS17->>IMUX30": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.SW2END3->>IMUX39": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.BYP_ALT4->>BYP4": { + "src_wire": "BYP_ALT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP4" + }, + "INT_R.NE6END2->>CTRL0": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.FAN_BOUNCE6->>IMUX17": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.EE2END3->>NN6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.NR1END1->>IMUX42": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.LOGIC_OUTS12->>NE2BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.EL1END1->>IMUX34": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX46": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.SE6END1->>SL1BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.NN2END2->>IMUX13": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.SL1END3->>SW2BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.LOGIC_OUTS11->>WW4BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.LOGIC_OUTS2->>IMUX28": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.SR1END1->>CLK0": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.SE6END1->>EE2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.LOGIC_OUTS13->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.LOGIC_OUTS12->>SS6BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.LOGIC_OUTS13->>EE2BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.LOGIC_OUTS2->>ER1BEG3": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.NW2END0->>WR1BEG1": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.LOGIC_OUTS13->>SE6BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.EE2END3->>IMUX7": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.GCLK_B1_EAST->>CLK1": { + "src_wire": "GCLK_B1_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.SS6END3->>SW2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.LH6->>LVB12": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.NW2END0->>IMUX8": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.LH6->>WW4BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.LOGIC_OUTS16->>IMUX13": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.NW2END2->>IMUX4": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.VCC_WIRE->>IMUX35": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.SR1END1->>SE2BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.LOGIC_OUTS19->>NN2BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.SL1END1->>IMUX42": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.NW2END_S0_0->>IMUX39": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.NE2END0->>IMUX9": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.NE2END2->>EL1BEG1": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.SW2END_N0_3->>IMUX16": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.LH0->>WW4BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.SL1END2->>BYP_ALT2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.NE6END0->>NR1BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.WL1END1->>IMUX3": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.NE6END1->>EE2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.NN2END2->>NN6BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.EE2END0->>ER1BEG1": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.EL1END0->>IMUX1": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.NL1END0->>IMUX40": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.LOGIC_OUTS4->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.LOGIC_OUTS11->>IMUX22": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.NE2END3->>NL1BEG2": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.SW2END3->>IMUX38": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.ER1END0->>ER1BEG1": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.NW6END1->>NN6BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.EE2END2->>IMUX37": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.BYP_BOUNCE0->>IMUX2": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.LOGIC_OUTS22->>WW4BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.NW2END3->>BYP_ALT6": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NR1END1->>IMUX2": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.NN2END2->>SR1BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.SE6END1->>EL1BEG0": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.LH0->>EE4BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.LOGIC_OUTS14->>NL1BEG1": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.EL1END3->>SE2BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.NL1BEG_N3->>IMUX5": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.LOGIC_OUTS1->>WL1BEG0": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.EL1END1->>IMUX19": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.NR1END3->>IMUX38": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.SR1BEG_S0->>IMUX9": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SR1END1->>WW2BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.WW2END1->>BYP_ALT2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.NL1END0->>FAN_ALT0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.SL1END3->>SR1BEG_S0": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.NR1END3->>IMUX23": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.ER1END_N3_3->>IMUX0": { + "src_wire": "ER1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.NL1END1->>BYP_ALT4": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.LOGIC_OUTS9->>NE2BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.NE6END1->>WW4BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.LV18->>LVB12": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.SE2END0->>BYP_ALT0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.SE2END1->>FAN_ALT6": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NW2END3->>WL1BEG1": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.NR1END3->>NN2BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.LOGIC_OUTS13->>SE2BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.NW2END1->>IMUX17": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.SW6END1->>SS2BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.EE2END2->>IMUX36": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.LOGIC_OUTS16->>WW2BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.ER1END0->>IMUX17": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.LOGIC_OUTS22->>EE4BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.SL1END2->>IMUX4": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX27": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.SW2END0->>ER1BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.LOGIC_OUTS12->>EE2BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.LOGIC_OUTS3->>EL1BEG2": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.LOGIC_OUTS22->>WW2BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.EE2END0->>IMUX25": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.SE2END2->>NE2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.SS2END1->>SS2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.NE2END3->>NN2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.NN2END3->>IMUX29": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.NN2END1->>FAN_ALT6": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NN6END2->>NE2BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.VCC_WIRE->>IMUX15": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.NN2END3->>WW4BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.SS6END2->>SW2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.SE2END0->>SE6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.GCLK_B0_EAST->>CLK1": { + "src_wire": "GCLK_B0_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.SW6END0->>SR1BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.NE2END3->>NN6BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.SR1END2->>IMUX22": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.ER1END1->>NR1BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.LOGIC_OUTS8->>SR1BEG1": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.SS6END3->>SL1BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.NE2END2->>NR1BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.NN2END2->>IMUX27": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.NN2END0->>IMUX17": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.EE2END2->>WR1BEG3": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.SL1END1->>IMUX43": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.FAN_BOUNCE3->>IMUX13": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.WW4END_S0_0->>WW2BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.SW6END1->>WW4BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.NW2END3->>FAN_ALT1": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.LOGIC_OUTS19->>ER1BEG2": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.LOGIC_OUTS6->>IMUX5": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.BYP_BOUNCE_N3_7->>BYP_ALT4": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.WL1END_N1_3->>FAN_ALT0": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.LOGIC_OUTS6->>NE2BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.GCLK_B5_EAST->>CLK1": { + "src_wire": "GCLK_B5_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.SW2END1->>SS2BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.LOGIC_OUTS11->>IMUX6": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.LV18->>SW6BEG3": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.LOGIC_OUTS12->>SL1BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.WR1END3->>LVB12": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.VCC_WIRE->>IMUX16": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.NE6END3->>EE2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.SW2END2->>NW2BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.SE2END1->>FAN_ALT2": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.NR1END2->>IMUX37": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.EE2END1->>IMUX3": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS5->>NN6BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.LOGIC_OUTS14->>NW6BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.LOGIC_OUTS23->>NN2BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.NR1END2->>NL1BEG1": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.LH12->>LVB0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.EL1END1->>IMUX41": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.SE2END2->>IMUX12": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.SE6END1->>NE6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.BYP_BOUNCE2->>BYP_ALT7": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.NN2END2->>EE4BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.LOGIC_OUTS7->>NE2BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.WR1END3->>IMUX37": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.SW2END3->>SW6BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.NN6END1->>SR1BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.GCLK_B2_EAST->>CLK1": { + "src_wire": "GCLK_B2_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.NN2END1->>EE2BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.NE6END0->>EE2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.EL1END1->>NR1BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.EE2END0->>EE4BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.NN6END0->>NE2BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.WW4END_S0_0->>SR1BEG_S0": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.NW6END3->>NN2BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.NW6END3->>NE2BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.LV0<<->>LV18": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.SW2END_N0_3->>WW4BEG0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.SE2END3->>NN6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.FAN_BOUNCE1->>IMUX42": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.SW2END0->>BYP_ALT1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.SE2END3->>IMUX46": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.WR1END1->>BYP_ALT1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.NL1END1->>NR1BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.SS6END2->>SE6BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.NR1END0->>IMUX0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX6": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.LOGIC_OUTS9->>EE4BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX7": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.SE2END3->>EL1BEG2": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.NN2END2->>NL1BEG1": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.NN2END1->>SE6BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.WW2END0->>BYP_ALT1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.NN2END_S2_0->>WW2BEG3": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.LOGIC_OUTS0->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.EE4END3->>ER1BEG_S0": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.LOGIC_OUTS17->>EL1BEG2": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.LOGIC_OUTS20->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.SE6END0->>ER1BEG1": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.LOGIC_OUTS9->>IMUX26": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.NW6END2->>WW4BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.SS6END1->>WL1BEG0": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.NE6END0->>SE2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.NW2END2->>IMUX44": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.SS2END0->>WW2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.BYP_BOUNCE4->>BYP_ALT3": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.EE2END1->>FAN_ALT6": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NL1END2->>IMUX20": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.SW2END1->>EE4BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.BYP_BOUNCE1->>IMUX19": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.VCC_WIRE->>IMUX33": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.LOGIC_OUTS3->>IMUX31": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.NL1END1->>FAN_ALT2": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.BYP_ALT0->>BYP0": { + "src_wire": "BYP_ALT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP0" + }, + "INT_R.LOGIC_OUTS0->>NN2BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.FAN_BOUNCE5->>IMUX27": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.LOGIC_OUTS19->>SS2BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.LOGIC_OUTS0->>SS2BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.ER1END0->>SL1BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.NN2END0->>FAN_ALT4": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.NN2END1->>WR1BEG2": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.SS2END1->>IMUX27": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.LOGIC_OUTS6->>NW6BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.WL1END2->>IMUX44": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.SE2END0->>IMUX9": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.FAN_ALT6->>FAN6": { + "src_wire": "FAN_ALT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN6" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX25": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.LOGIC_OUTS14->>WL1BEG1": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.NW2END3->>WW2BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.NR1END2->>IMUX36": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.NW6END1->>NW6BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.NW2END3->>IMUX21": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX32": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.NN2END1->>NN6BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.LOGIC_OUTS13->>IMUX11": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.WW4END2->>NW2BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.SS2END0->>SE6BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.LOGIC_OUTS0->>SS6BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.SR1END_N3_3->>IMUX24": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.SW6END_N0_3->>NW6BEG0": { + "src_wire": "SW6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.WW2END3->>SS2BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.VCC_WIRE->>IMUX7": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.EE2END3->>BYP_ALT7": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.EE2END0->>IMUX32": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.NR1END1->>NW2BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.EL1END3->>BYP_ALT3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.LOGIC_OUTS7->>IMUX6": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.LOGIC_OUTS4->>WR1BEG1": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.ER1END2->>IMUX36": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.LOGIC_OUTS8->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.SE2END3->>SW6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.NW2END0->>NL1BEG_N3": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.WW2END3->>IMUX31": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.ER1END1->>IMUX27": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.LOGIC_OUTS6->>IMUX45": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.SW2END2->>SS2BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.NE2END2->>IMUX12": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.LOGIC_OUTS17->>WW2BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.NW2END3->>NE2BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.WL1END0->>IMUX24": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX20": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.NW6END1->>NL1BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.WW2END2->>BYP_ALT6": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NE2END1->>SE2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.NL1END1->>EL1BEG0": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.EL1END3->>IMUX46": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.LOGIC_OUTS9->>WW4BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.WL1END3->>SR1BEG_S0": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.SS6END2->>SS2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.SE2END3->>IMUX6": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.NR1END2->>EE2BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.EE4END1->>EE4BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.WR1END1->>IMUX26": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.NN2END0->>NE2BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.LOGIC_OUTS13->>SL1BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.NN6END0->>LV0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV0" + }, + "INT_R.ER1END2->>IMUX22": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.EE2END3->>IMUX14": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.EL1END2->>IMUX43": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.LOGIC_OUTS14->>IMUX28": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.LOGIC_OUTS9->>NN2BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.SL1END0->>IMUX41": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.NL1END1->>NE2BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.WW2END2->>IMUX37": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.GFAN0->>IMUX1": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.EE2END2->>SE6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.LOGIC_OUTS17->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.LOGIC_OUTS2->>SS6BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.WL1END2->>WL1BEG1": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.NN2END3->>NN2BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.NN2END2->>WW4BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.SS6END1->>WW4BEG2": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.FAN_BOUNCE5->>IMUX19": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.SE2END1->>IMUX18": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.NW2END_S0_0->>SW2BEG3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.SE2END0->>NR1BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.NW2END1->>NW6BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.SR1END1->>IMUX4": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.LOGIC_OUTS5->>EE2BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.LOGIC_OUTS6->>EL1BEG1": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.NE2END1->>NW6BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.VCC_WIRE->>IMUX20": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.SR1END2->>WW2BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.WW2END2->>SS6BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.NN6END3->>EE2BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.EE2END3->>WR1BEG_S0": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.EE4END2->>EE4BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.FAN_ALT4->>FAN4": { + "src_wire": "FAN_ALT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN4" + }, + "INT_R.EL1END3->>BYP_ALT6": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NE2END3->>IMUX45": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.LOGIC_OUTS8->>NR1BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.NN6END2->>SE6BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.NL1END0->>EE2BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.EL1END0->>NE2BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.FAN_BOUNCE7->>IMUX2": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.SL1END3->>BYP_ALT7": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.SE6END3->>SE2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.SE2END1->>SW6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SW6END2->>ER1BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.SE2END1->>EE4BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.EL1END3->>IMUX29": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.NR1END2->>NN2BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.NR1END2->>IMUX4": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.SS2END0->>ER1BEG1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.SE2END2->>IMUX5": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.LOGIC_OUTS15->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.SE6END2->>SE2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.SW2END3->>IMUX15": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.LOGIC_OUTS21->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.SL1END3->>IMUX38": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.NE2END3->>IMUX6": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.LH0->>LVB0": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.LOGIC_OUTS5->>IMUX26": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.LOGIC_OUTS7->>IMUX22": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.LOGIC_OUTS20->>SE2BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.EE4END1->>NE6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.LOGIC_OUTS8->>EE2BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.WW2END_N0_3->>WW4BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.LOGIC_OUTS15->>NN6BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.LOGIC_OUTS11->>NE2BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.SW6END2->>NL1BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.SW6END2->>NW2BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.LOGIC_OUTS12->>NN2BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.WW4END2->>SW6BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.EE2END0->>IMUX1": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.LV0->>WW4BEG0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.SE2END3->>SW2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.SW2END3->>EE4BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.EE2END2->>IMUX29": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.EE2END0->>SL1BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX40": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.GCLK_B8->>GFAN0": { + "src_wire": "GCLK_B8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.SL1END2->>SS2BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.LOGIC_OUTS14->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.LV0->>NW6BEG0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.LV0->>SS6BEG0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.GCLK_B3->>GCLK_B3_EAST": { + "src_wire": "GCLK_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B3_EAST" + }, + "INT_R.ER1END_N3_3->>FAN_ALT0": { + "src_wire": "ER1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.LOGIC_OUTS20->>NL1BEG1": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.EL1END2->>FAN_ALT5": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.WR1END2->>IMUX35": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.SE2END2->>SW2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.ER1END1->>SS2BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.EE2END0->>IMUX41": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.NW6END2->>SS6BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.SR1BEG_S0->>SL1BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.EE4END2->>ER1BEG3": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.WW4END1->>WW2BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.VCC_WIRE->>IMUX0": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.WR1END_S1_0->>WL1BEG2": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.ER1END1->>IMUX26": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.EL1END2->>IMUX20": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.EE2END1->>BYP_ALT5": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.WW4END1->>WL1BEG_N3": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.SW2END1->>BYP_ALT5": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.LOGIC_OUTS4->>SE2BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.LOGIC_OUTS15->>NE6BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.NL1END1->>IMUX10": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.SW6END3->>SS2BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.BYP_BOUNCE1->>IMUX11": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.LOGIC_OUTS13->>WW2BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.FAN_BOUNCE3->>IMUX5": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.WW4END2->>CTRL1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.LV18->>NE6BEG3": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.LOGIC_OUTS21->>NR1BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.LV18->>LVB0": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.LOGIC_OUTS3->>SS6BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.WW4END3->>LVB0": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.EE4END1->>EL1BEG0": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.ER1END3->>EE2BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.SE2END1->>IMUX35": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.LOGIC_OUTS3->>IMUX7": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.LH0->>LVB12": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.NW2END2->>NE6BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.LOGIC_OUTS3->>NL1BEG2": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.LOGIC_OUTS16->>IMUX29": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.SR1BEG_S0->>IMUX18": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.SE2END3->>BYP_ALT7": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.WW2END3->>IMUX23": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.SL1END3->>WL1BEG2": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.VCC_WIRE->>FAN_ALT2": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.WR1END2->>FAN_ALT5": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.LH6->>SS6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.NW2END2->>IMUX3": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.NE2END0->>IMUX8": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.NN6END0->>NN2BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.WR1END0->>IMUX17": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.FAN_BOUNCE3->>IMUX37": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.GCLK_B11->>GFAN0": { + "src_wire": "GCLK_B11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.SE6END0->>WL1BEG_N3": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.SE2END3->>IMUX39": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.NE6END2->>NN2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.LOGIC_OUTS19->>WL1BEG0": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.LOGIC_OUTS8->>ER1BEG1": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.EE2END1->>FAN_ALT2": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.EL1END3->>IMUX30": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.WL1END2->>IMUX36": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.NN2END3->>IMUX46": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.SR1END2->>SR1BEG3": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.FAN_BOUNCE_S3_4->>BYP_ALT3": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.LOGIC_OUTS5->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.WW4END3->>NE6BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.NN6END3->>WR1BEG_S0": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.NW2END0->>NN6BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.LOGIC_OUTS17->>EE4BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.EE4END3->>NN6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.NE2END2->>EE4BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.NR1END2->>IMUX5": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX39": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.LOGIC_OUTS6->>IMUX21": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.EL1END2->>EE2BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.WL1END0->>NW2BEG1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.LOGIC_OUTS9->>SS2BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.SL1END0->>SL1BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.GFAN1->>IMUX21": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SW6END2->>WL1BEG1": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.LOGIC_OUTS21->>NE2BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.NE6END2->>NE6BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.SW2END3->>WW2BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.ER1END3->>IMUX7": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.LOGIC_OUTS4->>IMUX17": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.SS2END3->>SS6BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.LOGIC_OUTS2->>NR1BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.NN6END1->>NR1BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.LOGIC_OUTS13->>NE2BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.LOGIC_OUTS11->>WW2BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.EE2END1->>IMUX34": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.NW2END3->>NN6BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.LOGIC_OUTS11->>NW2BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.LOGIC_OUTS4->>NE2BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.GCLK_B4_EAST->>CLK1": { + "src_wire": "GCLK_B4_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.WR1END_S1_0->>SW2BEG3": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX42": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.LOGIC_OUTS12->>ER1BEG1": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.SE6END1->>NE2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.WL1END1->>IMUX42": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.NL1END_S3_0->>IMUX31": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.GCLK_B11->>CLK1": { + "src_wire": "GCLK_B11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.NE6END3->>NW2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.FAN_BOUNCE1->>IMUX20": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.LOGIC_OUTS3->>NN2BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.WW4END_S0_0->>SS6BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.SE6END2->>SS2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.NR1END3->>LVB0": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.ER1END0->>IMUX41": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.LOGIC_OUTS22->>SS6BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.LOGIC_OUTS23->>IMUX19": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.NR1END1->>IMUX27": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.WR1END3->>WW2BEG2": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.LOGIC_OUTS5->>IMUX10": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.LH12->>SE6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.BYP_BOUNCE2->>IMUX30": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.WW4END3->>NN6BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.NN6END3->>NE6BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.LOGIC_OUTS17->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.WW2END1->>NW6BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.WR1END1->>FAN_ALT6": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.GCLK_B7->>GFAN1": { + "src_wire": "GCLK_B7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.VCC_WIRE->>IMUX11": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.FAN_BOUNCE1->>IMUX2": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX24": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.NE2END0->>FAN_ALT0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.NN2END2->>IMUX43": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NE2END2->>NN2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.LH6->>NN6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX34": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.ER1END0->>IMUX10": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.BYP_BOUNCE5->>IMUX13": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.EE2END1->>SS6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.LOGIC_OUTS14->>NN6BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.GCLK_B10->>GFAN1": { + "src_wire": "GCLK_B10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.LOGIC_OUTS14->>NE6BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.NN6END2->>NL1BEG1": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.LOGIC_OUTS22->>WR1BEG1": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.SW2END2->>IMUX28": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.LOGIC_OUTS7->>WW2BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.ER1END1->>FAN_ALT6": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.LVB0->>EE4BEG2": { + "src_wire": "LVB0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.VCC_WIRE->>IMUX45": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.FAN_BOUNCE5->>IMUX11": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.EE2END3->>SL1BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.SW2END1->>IMUX4": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.LOGIC_OUTS10->>WW2BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.BYP_BOUNCE3->>IMUX7": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.SE2END1->>IMUX42": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.NW2END1->>NW2BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.EE2END3->>FAN_ALT1": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.NW6END_S0_0->>WL1BEG2": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.WW4END1->>SW2BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.NE2END3->>EE4BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.LOGIC_OUTS16->>SW2BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.LOGIC_OUTS13->>IMUX43": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.LOGIC_OUTS12->>EE4BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.WW2END0->>SW6BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.SE2END1->>EL1BEG0": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.LOGIC_OUTS19->>NW6BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.LOGIC_OUTS11->>SW2BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.SS2END1->>EE2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.EE4END3->>NR1BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.GCLK_B0->>GCLK_B0_WEST": { + "src_wire": "GCLK_B0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B0_WEST" + }, + "INT_R.NN2END3->>IMUX15": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.NR1END0->>NE2BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.WL1END1->>FAN_ALT6": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.LOGIC_OUTS15->>EL1BEG2": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.EE2END2->>EE2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.LOGIC_OUTS22->>IMUX8": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.WW4END2->>NN2BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.LOGIC_OUTS9->>IMUX2": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.NN6END3->>NN6BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.LOGIC_OUTS23->>SR1BEG2": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.BYP_BOUNCE_N3_2->>FAN_ALT0": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.WW2END0->>IMUX26": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.EL1END2->>IMUX4": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.LOGIC_OUTS19->>SW2BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.SL1END1->>WW2BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.BYP_ALT7->>BYP_BOUNCE7": { + "src_wire": "BYP_ALT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE7" + }, + "INT_R.LOGIC_OUTS0->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.ER1END0->>SS2BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.SS6END2->>SS6BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.NW2END0->>NW6BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.LV18<<->>LH12": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.SS6END2->>WL1BEG1": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.SE6END3->>SL1BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.WR1END3->>FAN_ALT1": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.SE2END3->>IMUX14": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.EE4END0->>EE2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.NE6END1->>SL1BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.SS2END3->>IMUX47": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.LOGIC_OUTS23->>NE2BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.NL1END2->>WR1BEG3": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.BYP_BOUNCE0->>IMUX18": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX36": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.ER1END3->>IMUX38": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.GFAN1->>IMUX29": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.NE2END3->>EE2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.WR1END2->>IMUX43": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.LOGIC_OUTS5->>SE2BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.SW6END0->>SE2BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.LOGIC_OUTS4->>ER1BEG1": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.WL1END_N1_3->>IMUX16": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.SR1END3->>IMUX47": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.NE2END0->>NN6BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.BYP_BOUNCE3->>IMUX15": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.LOGIC_OUTS23->>NL1BEG0": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.LOGIC_OUTS23->>SW2BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.NW2END2->>LVB12": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.NR1END0->>WR1BEG1": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.GCLK_B9->>GFAN1": { + "src_wire": "GCLK_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.SS6END3->>NR1BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.LVB0->>NW6BEG2": { + "src_wire": "LVB0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.WW4END2->>NL1BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.EE4END1->>SE2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.NR1END0->>IMUX25": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.SS6END2->>NW6BEG3": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.NW2END1->>EL1BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.LOGIC_OUTS4->>NE6BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.LOGIC_OUTS9->>EE2BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.LOGIC_OUTS18->>NW2BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.SW2END1->>NW6BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.BYP_BOUNCE5->>IMUX23": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.SE6END0->>SW6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.LOGIC_OUTS15->>NE2BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.ER1END2->>FAN_ALT5": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.SE2END3->>SE2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.EE4END2->>EE2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.EE4END0->>SW6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.LVB12->>NW6BEG2": { + "src_wire": "LVB12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.LOGIC_OUTS22->>NE2BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.NE2END3->>IMUX22": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.NW2END1->>NN6BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.WW2END2->>IMUX46": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.LOGIC_OUTS11->>SE6BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.LV18->>NW6BEG3": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.VCC_WIRE->>FAN_ALT3": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.SR1END2->>IMUX21": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.NE2END1->>NN6BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.NR1END1->>IMUX3": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS0->>SR1BEG1": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.SS2END0->>IMUX17": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.LOGIC_OUTS19->>IMUX10": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.WW4END2->>WW2BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.NR1END3->>IMUX22": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.NW2END3->>SW2BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.NR1END3->>FAN_ALT3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.WR1END3->>IMUX15": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.GND_WIRE->>GFAN1": { + "src_wire": "GND_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.FAN_BOUNCE7->>FAN_ALT4": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.SE6END2->>SL1BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.SL1END3->>SS2BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.NN6END3->>WW2BEG2": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.SW2END1->>WL1BEG0": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.LOGIC_OUTS15->>SE2BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.EE2END2->>IMUX28": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.EE2END0->>NR1BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.WR1END3->>NW2BEG3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX8": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.LH6->>LVB0": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.NR1END2->>NR1BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.LOGIC_OUTS3->>NE6BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.SL1END1->>SE2BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.NE2END0->>IMUX40": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.NN2END3->>EE4BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.NN2END2->>IMUX12": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.SE6END3->>ER1BEG_S0": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.SS2END0->>NW6BEG1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.VCC_WIRE->>IMUX19": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.GFAN1->>BYP_ALT7": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.SE2END3->>SS2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.WW2END1->>IMUX20": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.BYP_BOUNCE5->>IMUX21": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SW2END0->>SE6BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.LOGIC_OUTS4->>IMUX9": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.NN2END3->>NW6BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.LOGIC_OUTS13->>NW2BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.GCLK_B1->>GCLK_B1_EAST": { + "src_wire": "GCLK_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B1_EAST" + }, + "INT_R.NN2END1->>IMUX34": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LOGIC_OUTS20->>IMUX20": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.WW2END0->>IMUX33": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.NW2END0->>IMUX32": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.ER1END2->>IMUX14": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.WW4END0->>WR1BEG1": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.WW2END_N0_3->>BYP_ALT0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.LOGIC_OUTS20->>ER1BEG3": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.GCLK_B1_EAST->>GFAN0": { + "src_wire": "GCLK_B1_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.NW6END2->>NL1BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.ER1END2->>IMUX6": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.EE2END2->>IMUX13": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.WW2END2->>NN6BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.LOGIC_OUTS20->>EE4BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.LH12->>SS6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.WR1END0->>LV0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV0" + }, + "INT_R.NL1BEG_N3->>BYP_ALT3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.EE2END2->>BYP_ALT3": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.SW6END1->>SR1BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.SE2END2->>SS6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.SR1END_N3_3->>IMUX16": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.SS2END0->>SR1BEG1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.NR1END2->>FAN_ALT5": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.LOGIC_OUTS21->>WW4BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.SS6END0->>SS2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.SE2END3->>SL1BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.LOGIC_OUTS6->>SS6BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.SS2END2->>WL1BEG1": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.NN2END0->>NN2BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.SS6END0->>EE2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.GFAN0->>IMUX3": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS22->>SS2BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.NE6END0->>EL1BEG_N3": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.SR1BEG_S0->>IMUX34": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.NN2END1->>BYP_ALT4": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.SR1END2->>IMUX29": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.EE2END1->>SE6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.LOGIC_OUTS20->>SL1BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.LOGIC_OUTS12->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.LOGIC_OUTS14->>ER1BEG3": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.LOGIC_OUTS22->>IMUX24": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.SS2END1->>IMUX4": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.WW4END2->>WR1BEG3": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.BYP_BOUNCE0->>BYP_ALT1": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX21": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SS2END2->>BYP_ALT3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.NE2END3->>FAN_ALT1": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.NE2END1->>NL1BEG0": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.WL1END2->>IMUX6": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.GFAN0->>IMUX17": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.NW2END_S0_0->>WW2BEG3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.LOGIC_OUTS1->>WW4BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX5": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.WL1END3->>IMUX30": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.LOGIC_OUTS23->>NE6BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.LOGIC_OUTS4->>SL1BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.NN2END0->>SE6BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.EE2END1->>EL1BEG0": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.LOGIC_OUTS19->>IMUX34": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.GFAN1->>FAN_ALT3": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.WW4END1->>NW6BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.SR1BEG_S0->>IMUX2": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.NW2END3->>NE6BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.LOGIC_OUTS1->>SR1BEG2": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.NN6END1->>EL1BEG0": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.SW6END1->>EE4BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.BYP_ALT7->>BYP7": { + "src_wire": "BYP_ALT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP7" + }, + "INT_R.NE2END1->>IMUX42": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.LOGIC_OUTS9->>IMUX42": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.LOGIC_OUTS23->>SE6BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.SE2END2->>EL1BEG1": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.LOGIC_OUTS21->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.SS6END3->>SW6BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX24": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.LOGIC_OUTS18->>SW6BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.NE6END0->>NN2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.LOGIC_OUTS19->>NL1BEG0": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.NE2END_S3_0->>IMUX47": { + "src_wire": "NE2END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.LOGIC_OUTS2->>WW2BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.LOGIC_OUTS10->>SR1BEG3": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.LOGIC_OUTS12->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.FAN_BOUNCE7->>IMUX24": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.SW2END1->>SW2BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.SE6END1->>WL1BEG0": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.LOGIC_OUTS21->>SS2BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.LOGIC_OUTS21->>SE2BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.SS2END_N0_3->>FAN_ALT0": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.NW2END3->>IMUX6": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.SS6END2->>NR1BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.SW2END0->>IMUX2": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.NN2END2->>NN2BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.WW2END3->>SR1BEG_S0": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.SW2END2->>WL1BEG1": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.NE2END3->>BYP_ALT3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.SL1END3->>IMUX22": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.SL1END0->>FAN_ALT0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.EE2END2->>NR1BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX33": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.WR1END2->>WR1BEG3": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.LOGIC_OUTS15->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.LOGIC_OUTS17->>IMUX22": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.SS2END1->>IMUX26": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.LOGIC_OUTS9->>WR1BEG2": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.NE6END3->>EE4BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.LOGIC_OUTS20->>SW2BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.SE2END2->>FAN_ALT7": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.SR1END3->>FAN_ALT3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.NN2END3->>IMUX30": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.NW2END2->>IMUX20": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.SR1END3->>BYP_ALT7": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.NW6END2->>SW6BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SR1END1->>IMUX27": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.LOGIC_OUTS13->>NE6BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.FAN_BOUNCE7->>IMUX8": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.SW6END_N0_3->>NL1BEG_N3": { + "src_wire": "SW6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.LOGIC_OUTS5->>NE2BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.SR1END2->>BYP_ALT3": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.SE2END1->>SL1BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.NE6END3->>EL1BEG2": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.WW4END0->>NL1BEG_N3": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.NW6END2->>WW2BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.NR1END3->>IMUX30": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.SL1END0->>IMUX1": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.LOGIC_OUTS9->>SE2BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.WL1END0->>WW2BEG0": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.WW2END_N0_3->>WR1BEG1": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.GFAN1->>CTRL0": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.NW6END0->>NL1BEG_N3": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.LOGIC_OUTS21->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.NN2END1->>NR1BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.NN6END1->>NW6BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.NW6END3->>WW2BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.LOGIC_OUTS13->>EE4BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.LOGIC_OUTS1->>SE2BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.LOGIC_OUTS10->>EL1BEG1": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.BYP_BOUNCE0->>FAN_ALT2": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.SR1END1->>IMUX12": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.EE4END2->>SW6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.NR1END2->>NW2BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.LOGIC_OUTS2->>EL1BEG1": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.LOGIC_OUTS5->>WW4BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.EL1END3->>IMUX15": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.WR1END0->>LV18": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.LOGIC_OUTS16->>WL1BEG1": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.NN6END2->>CTRL0": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.LOGIC_OUTS9->>SL1BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.LVB12->>SW6BEG2": { + "src_wire": "LVB12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.LOGIC_OUTS12->>NE6BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.LOGIC_OUTS11->>IMUX46": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.EE4END3->>LH12": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.LOGIC_OUTS6->>SE2BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.NW2END2->>BYP_ALT2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.GFAN0->>IMUX25": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.GFAN1->>BYP_ALT3": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.NE6END1->>NR1BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.LOGIC_OUTS17->>SW2BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.SS2END2->>IMUX14": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.SW2END3->>SE6BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.NL1END0->>NR1BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.NL1END1->>BYP_ALT1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.SS2END0->>SW2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.NE2END3->>EL1BEG2": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.BYP_BOUNCE4->>IMUX12": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.WW2END0->>IMUX25": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.SE2END2->>IMUX36": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.BYP_BOUNCE4->>IMUX20": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.LOGIC_OUTS19->>IMUX2": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.BYP_BOUNCE5->>BYP_ALT6": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.EL1END1->>IMUX10": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.SE2END1->>NE6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.WL1END0->>IMUX18": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.FAN_BOUNCE7->>IMUX40": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.SE2END1->>WL1BEG0": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.LOGIC_OUTS15->>SL1BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.LOGIC_OUTS10->>NN6BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.SS2END1->>WL1BEG0": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.FAN_BOUNCE7->>IMUX32": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.SS6END1->>SW2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.LOGIC_OUTS14->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.NW2END1->>BYP_ALT1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.NE6END2->>EE4BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.WR1END1->>BYP_ALT4": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.SL1END3->>WW2BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.SR1BEG_S0->>IMUX26": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.WW4END_S0_0->>SW6BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.EE4END1->>EE2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.EE4END1->>SW6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.NE2END2->>EE2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.SE2END2->>ER1BEG3": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.EE4END0->>SE2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.FAN_ALT2->>FAN2": { + "src_wire": "FAN_ALT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN2" + }, + "INT_R.EE4END0->>SL1BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.WW2END1->>IMUX44": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.LOGIC_OUTS19->>NW2BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.LV9->>SW6BEG1": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.NN6END0->>WW4BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.SR1END3->>IMUX39": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.SS2END_N0_3->>IMUX8": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.BYP_BOUNCE4->>IMUX46": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.NE6END3->>SE2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.FAN_BOUNCE7->>IMUX0": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.BYP_BOUNCE_N3_6->>BYP_ALT1": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.EL1END0->>EE2BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.FAN_ALT6->>FAN_BOUNCE6": { + "src_wire": "FAN_ALT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE6" + }, + "INT_R.LOGIC_OUTS5->>WL1BEG0": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.SE2END0->>IMUX8": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.EE4END3->>SL1BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.EL1END2->>EL1BEG1": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.LOGIC_OUTS20->>WL1BEG1": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.LOGIC_OUTS2->>IMUX4": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.EE2END0->>FAN_ALT4": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.NE2END0->>IMUX32": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.BYP_BOUNCE2->>IMUX14": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.NE6END2->>CTRL1": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.SW2END1->>NL1BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.SE2END2->>SL1BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.SS6END_N0_3->>NW6BEG0": { + "src_wire": "SS6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.SW2END2->>LVB12": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.FAN_BOUNCE2->>IMUX8": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.LV18->>EE4BEG3": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.SL1END0->>IMUX40": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.SE6END3->>SW2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.LOGIC_OUTS9->>SR1BEG2": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.LOGIC_OUTS1->>ER1BEG2": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.SE6END1->>NN6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.NN2END2->>IMUX21": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.NW6END_S0_0->>SS6BEG3": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.LOGIC_OUTS2->>EE4BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.LOGIC_OUTS19->>NN6BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.LOGIC_OUTS12->>WW4BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.WL1END3->>IMUX46": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.SS6END1->>EE4BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.LOGIC_OUTS8->>NN6BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.SE2END0->>IMUX40": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.LOGIC_OUTS18->>SS2BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.FAN_BOUNCE1->>IMUX28": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.LOGIC_OUTS19->>IMUX18": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.LOGIC_OUTS22->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.NN2END0->>IMUX1": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.NL1END1->>IMUX17": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.SW2END0->>IMUX10": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.SR1END1->>CLK1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.ER1END0->>BYP_ALT0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.WL1END0->>IMUX41": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.BYP_BOUNCE4->>IMUX36": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.WW2END1->>WW4BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.SW2END2->>ER1BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.BYP_BOUNCE4->>IMUX22": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.NR1END3->>WR1BEG_S0": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.LOGIC_OUTS9->>SS6BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.LOGIC_OUTS14->>WW4BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.LOGIC_OUTS1->>NW6BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.LOGIC_OUTS21->>SL1BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.LOGIC_OUTS6->>NN6BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.WR1END1->>NL1BEG0": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.LOGIC_OUTS17->>IMUX6": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.SW2END1->>FAN_ALT7": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.GCLK_B8->>GFAN1": { + "src_wire": "GCLK_B8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.NN6END1->>NE2BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.NW6END1->>SR1BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.NN2END1->>FAN_ALT2": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.NW2END2->>BYP_ALT5": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.EE4END0->>WR1BEG1": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.LOGIC_OUTS15->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.SE2END2->>IMUX45": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.NL1BEG_N3->>NR1BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.ER1END2->>IMUX13": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.LOGIC_OUTS17->>SS2BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.LOGIC_OUTS7->>NL1BEG2": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.NE6END2->>NR1BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.GCLK_B4_EAST->>GFAN0": { + "src_wire": "GCLK_B4_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.NL1BEG_N3->>NW2BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.NL1BEG_N3->>IMUX29": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.LOGIC_OUTS6->>EE2BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.WL1END3->>IMUX31": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX22": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.SL1END0->>WL1BEG_N3": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.LOGIC_OUTS10->>WW4BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.SW2END2->>SL1BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.BYP_BOUNCE3->>BYP_ALT6": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NN6END0->>NR1BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.WR1END1->>WR1BEG2": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.NN2END3->>SR1BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.NW6END0->>NW2BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.ER1END0->>IMUX24": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.EE2END1->>IMUX18": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.LOGIC_OUTS0->>NE2BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.BYP_BOUNCE4->>IMUX38": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.NE2END0->>WW4BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.LOGIC_OUTS15->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.SL1END2->>SW2BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.NN2END3->>IMUX45": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.LOGIC_OUTS1->>WW2BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.EE2END3->>FAN_ALT3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.NW6END2->>SW2BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.EE2END2->>IMUX20": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.LV0->>NE6BEG0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.NW2END3->>IMUX46": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX46": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.LOGIC_OUTS20->>NW6BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.LOGIC_OUTS22->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.EE2END3->>NE2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.SS6END0->>WL1BEG_N3": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX33": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.NW2END2->>IMUX43": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NL1END1->>IMUX42": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.VCC_WIRE->>IMUX25": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.SR1END2->>IMUX45": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.NR1END3->>BYP_ALT6": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NN2END3->>IMUX23": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.SL1END0->>IMUX9": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SE2END0->>SS6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.EE2END2->>NN2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.LOGIC_OUTS9->>WW2BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.LOGIC_OUTS14->>SW6BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.EL1END_S3_0->>IMUX31": { + "src_wire": "EL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.LVB12->>EE4BEG2": { + "src_wire": "LVB12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.EL1END0->>IMUX9": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SL1END3->>IMUX7": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.SR1END2->>IMUX38": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.SR1BEG_S0->>WW2BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.EE4END3->>NE2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.WW2END2->>IMUX6": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.WW2END2->>IMUX38": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.LOGIC_OUTS1->>SW6BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SW2END2->>IMUX37": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.SW6END2->>LVB0": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.NL1BEG_N3->>NE2BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.ER1END1->>IMUX3": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS5->>SS2BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.NE2END0->>EL1BEG_N3": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.LOGIC_OUTS19->>SL1BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.LOGIC_OUTS15->>NR1BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.VCC_WIRE->>BYP_ALT3": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.SS6END2->>CTRL1": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.FAN_BOUNCE1->>IMUX10": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.NW6END3->>NN6BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.NR1END2->>IMUX45": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.NR1END2->>WR1BEG3": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.EE2END3->>IMUX6": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.WW4END3->>LVB12": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.NN2END3->>IMUX38": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.SE2END1->>IMUX34": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.SW6END3->>SW2BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.ER1END3->>NR1BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.SR1BEG_S0->>BYP_ALT4": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.FAN_BOUNCE1->>BYP_ALT2": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.ER1END0->>BYP_ALT1": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.EL1END1->>IMUX42": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.EL1END3->>FAN_ALT3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.LOGIC_OUTS11->>SS6BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.LOGIC_OUTS17->>NN6BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.SS2END1->>SW6BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.LOGIC_OUTS14->>SL1BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.LOGIC_OUTS6->>ER1BEG3": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX1": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.SR1END1->>IMUX35": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.ER1END1->>IMUX43": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.SW2END0->>EE4BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.SS2END1->>IMUX34": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LOGIC_OUTS23->>WW2BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.SW2END0->>IMUX40": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.NN2END2->>IMUX20": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.NN6END1->>NN6BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.LH6->>LV0": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV0" + }, + "INT_R.EE2END3->>NE6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.WR1END1->>IMUX2": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.BYP_BOUNCE1->>IMUX43": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NL1END2->>IMUX19": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.EE2END1->>BYP_ALT4": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.SW6END1->>SE2BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.GFAN1->>IMUX22": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.VCC_WIRE->>IMUX36": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.SL1END1->>IMUX34": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LOGIC_OUTS0->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.WR1END2->>IMUX44": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.EE2END0->>SE6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.NW2END3->>NL1BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.LOGIC_OUTS23->>WL1BEG0": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.NW6END0->>NN2BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.GCLK_B0_EAST->>GFAN0": { + "src_wire": "GCLK_B0_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.LOGIC_OUTS16->>IMUX5": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.NW2END2->>SR1BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.FAN_BOUNCE_S3_0->>BYP_ALT6": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.LOGIC_OUTS12->>SS2BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.LOGIC_OUTS16->>NL1BEG1": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.SE6END2->>SE6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.NW6END1->>NE2BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.SR1END1->>FAN_ALT7": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.NW6END0->>EL1BEG_N3": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.GCLK_B10->>CLK1": { + "src_wire": "GCLK_B10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.SR1END1->>IMUX19": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.NN2END1->>IMUX2": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.SW2END0->>IMUX24": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.LH6->>SW6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.BYP_BOUNCE5->>IMUX45": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.EE2END1->>EE2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.LOGIC_OUTS23->>SS2BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.SR1BEG_S0->>LV18": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.LOGIC_OUTS15->>IMUX47": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.WL1END0->>FAN_ALT2": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.LV0->>LVB0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.GCLK_B11->>CLK0": { + "src_wire": "GCLK_B11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.FAN_BOUNCE3->>FAN_ALT1": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.SW2END_N0_3->>IMUX0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.SW2END0->>SS2BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.NN2END_S2_0->>IMUX47": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.VCC_WIRE->>IMUX12": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.NN6END3->>NW2BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.NE2END2->>IMUX21": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SW2END3->>BYP_ALT7": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.LOGIC_OUTS12->>SE6BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.BYP_BOUNCE0->>FAN_ALT7": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.SS2END1->>ER1BEG2": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.WR1END2->>FAN_ALT7": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.ER1END2->>IMUX45": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.EE2END0->>FAN_ALT0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.BYP_BOUNCE0->>BYP_ALT5": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.NW2END2->>SS6BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.EE4END2->>NN2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.BYP_BOUNCE0->>IMUX20": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.LOGIC_OUTS21->>SS6BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.SW2END3->>BYP_ALT6": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NE2END2->>IMUX28": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.NW2END2->>NN6BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.LOGIC_OUTS3->>SE6BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.NE2END3->>SE2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.LOGIC_OUTS3->>NW2BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.WR1END1->>IMUX11": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.EL1END_S3_0->>BYP_ALT7": { + "src_wire": "EL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.LOGIC_OUTS23->>WW4BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.LV9->>SS6BEG1": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.NN2END3->>IMUX7": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.SL1END0->>SR1BEG1": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.BYP_BOUNCE1->>IMUX29": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.NE2END0->>NL1BEG_N3": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.SE2END0->>WL1BEG_N3": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.BYP_BOUNCE2->>IMUX6": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.VCC_WIRE->>FAN_ALT7": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.VCC_WIRE->>IMUX10": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.LOGIC_OUTS15->>NL1BEG2": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.SE6END3->>LVB12": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.LOGIC_OUTS7->>EE2BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.LOGIC_OUTS14->>IMUX12": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.LOGIC_OUTS5->>IMUX2": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.GCLK_B7->>CLK0": { + "src_wire": "GCLK_B7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.BYP_BOUNCE0->>IMUX4": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.NE2END2->>SE6BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.WW2END0->>SS6BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.GFAN1->>IMUX20": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.NE2END1->>IMUX34": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.SS2END3->>EE2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.NR1END0->>IMUX8": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.LOGIC_OUTS2->>IMUX36": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.VCC_WIRE->>IMUX23": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.VCC_WIRE->>FAN_ALT5": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.FAN_BOUNCE7->>IMUX18": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.WR1END3->>IMUX38": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.WW2END0->>NL1BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.WW2END1->>IMUX27": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.SE6END2->>ER1BEG3": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.LOGIC_OUTS19->>NE6BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.LOGIC_OUTS7->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.NN2END0->>BYP_ALT0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.WL1END3->>IMUX23": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.EL1END3->>IMUX7": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.LOGIC_OUTS7->>WL1BEG2": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.NW6END1->>WR1BEG2": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.NR1END1->>NE2BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.LV18<<->>LH0": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.LOGIC_OUTS10->>NR1BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.SW6END2->>SE6BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.SS2END2->>SS2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.NW6END0->>WW4BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.LOGIC_OUTS10->>IMUX21": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.WW2END3->>SW6BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.LOGIC_OUTS13->>IMUX19": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.SW2END2->>BYP_ALT3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.WW2END1->>IMUX12": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.LOGIC_OUTS14->>NR1BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.FAN_BOUNCE_S3_0->>FAN_ALT5": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.LOGIC_OUTS23->>NR1BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.EE2END2->>SS6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.LOGIC_OUTS7->>NN6BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.LOGIC_OUTS3->>IMUX15": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.NN2END2->>NR1BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.SW2END0->>SL1BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.SE2END3->>NE6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.LOGIC_OUTS16->>EE4BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.SS2END_N0_3->>IMUX16": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.LVB0->>SE6BEG2": { + "src_wire": "LVB0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.SE6END3->>EL1BEG2": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.GFAN1->>IMUX31": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.LOGIC_OUTS9->>NL1BEG0": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.GFAN0->>CTRL0": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.SW2END2->>IMUX21": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.LOGIC_OUTS7->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.NN6END2->>SR1BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.LOGIC_OUTS5->>IMUX18": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.LOGIC_OUTS17->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.SE6END2->>CTRL1": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.NN2END0->>NL1BEG_N3": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.LOGIC_OUTS7->>SW2BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.NE2END2->>FAN_ALT5": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.EE2END0->>NE2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.LOGIC_OUTS0->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.SE2END0->>NN6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.NN2END0->>WW4BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.FAN_BOUNCE_S3_4->>FAN_ALT1": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.SS6END1->>EE2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.VCC_WIRE->>IMUX8": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.NW2END0->>EL1BEG_N3": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.NW6END1->>WL1BEG_N3": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.NN2END3->>SE6BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.LOGIC_OUTS2->>SE2BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.SL1END3->>IMUX30": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.SW6END1->>CTRL0": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.LOGIC_OUTS0->>WW4BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.LOGIC_OUTS9->>EL1BEG0": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.LOGIC_OUTS10->>WR1BEG3": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.EL1END3->>SS2BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.VCC_WIRE->>IMUX41": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.SW2END2->>SE6BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.LOGIC_OUTS3->>SE2BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.VCC_WIRE->>BYP_ALT0": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.LOGIC_OUTS22->>SW2BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.SE2END0->>IMUX25": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.WW2END0->>FAN_ALT4": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.NL1END0->>BYP_ALT0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.NE2END0->>IMUX17": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.SS2END3->>SW6BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.SL1END0->>SS2BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.BYP_BOUNCE0->>IMUX34": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LOGIC_OUTS23->>SS6BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.WL1END3->>BYP_ALT6": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.SE2END2->>BYP_ALT3": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.SL1END1->>SS2BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.LVB0->>WW4BEG2": { + "src_wire": "LVB0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.WL1END0->>IMUX32": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.LOGIC_OUTS0->>IMUX24": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.SS2END3->>SL1BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.SR1END_N3_3->>BYP_ALT0": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.EE2END2->>BYP_ALT2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.ER1END3->>LH12": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.SR1BEG_S0->>ER1BEG1": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.NR1END3->>IMUX46": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.LOGIC_OUTS15->>SS2BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.LOGIC_OUTS7->>SW6BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.NN6END1->>NN2BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.SE6END0->>NE6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.SW2END3->>SL1BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.SS6END2->>SR1BEG3": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.SS2END1->>WW4BEG2": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.NL1END0->>NE2BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.LOGIC_OUTS5->>NL1BEG0": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.EL1END3->>NE2BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.NN6END0->>EE2BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.SE6END0->>EE4BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.SL1END1->>SR1BEG2": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.GCLK_B4_EAST->>GFAN1": { + "src_wire": "GCLK_B4_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.SS2END3->>SW2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.LOGIC_OUTS3->>IMUX47": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.LOGIC_OUTS10->>NL1BEG1": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.SE2END1->>IMUX27": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.LOGIC_OUTS4->>SE6BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.LOGIC_OUTS0->>SW6BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.LOGIC_OUTS0->>EE2BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX25": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.EE2END1->>IMUX10": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.SE2END0->>EE2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.WL1END_N1_3->>NW2BEG0": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.WR1END0->>IMUX24": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.EE2END0->>IMUX8": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.SR1BEG_S0->>BYP_ALT1": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.NE2END0->>EE4BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.EL1END1->>ER1BEG2": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.WR1END2->>IMUX36": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.EE2END1->>NN2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.LOGIC_OUTS23->>IMUX35": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.SS6END0->>SE2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.NL1END2->>IMUX27": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.SL1END3->>IMUX6": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.FAN_BOUNCE2->>BYP_ALT0": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.SS6END2->>ER1BEG3": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.BYP_BOUNCE0->>IMUX28": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.WR1END0->>IMUX0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.SE2END1->>BYP_ALT5": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.LOGIC_OUTS7->>NE6BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.EE4END2->>SS2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.NE2END3->>IMUX30": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.NL1END2->>IMUX3": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.EE2END3->>SE6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX26": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.ER1END3->>IMUX39": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.LOGIC_OUTS9->>NN6BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.FAN_BOUNCE1->>CTRL1": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.NE2END3->>NR1BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.NE2END2->>SL1BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.NW6END3->>SW6BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.EL1END3->>IMUX23": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.WL1END_N1_3->>NL1BEG_N3": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.SL1END2->>SE2BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.LOGIC_OUTS23->>NN6BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.SS6END0->>EE4BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.FAN_BOUNCE5->>IMUX9": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SR1END1->>IMUX43": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.FAN_ALT5->>FAN5": { + "src_wire": "FAN_ALT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN5" + }, + "INT_R.EE2END2->>IMUX5": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.LOGIC_OUTS3->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.NW6END0->>NE6BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.BYP_BOUNCE1->>GFAN0": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.GFAN0->>IMUX33": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.SL1END1->>IMUX19": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.SL1END3->>SL1BEG3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.NE6END2->>NW6BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.LVB12->>NN6BEG2": { + "src_wire": "LVB12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.SS2END3->>BYP_ALT7": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.NW2END1->>IMUX1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.VCC_WIRE->>BYP_ALT4": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.WL1END3->>IMUX7": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.LOGIC_OUTS8->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.SS2END3->>IMUX46": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.SE6END1->>SE2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.SS2END1->>IMUX43": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.WR1END2->>BYP_ALT2": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.NW2END2->>FAN_ALT7": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.LOGIC_OUTS1->>SW2BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.LOGIC_OUTS20->>NE2BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.NN2END3->>BYP_ALT3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.NR1END0->>EE2BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.LOGIC_OUTS13->>NW6BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.FAN_BOUNCE_S3_0->>BYP_ALT2": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.NW6END0->>NW6BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.NN2END1->>IMUX25": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.WW2END_N0_3->>NE6BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.LOGIC_OUTS23->>BYP_ALT5": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.NW2END2->>IMUX27": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.FAN_BOUNCE7->>IMUX26": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.WL1END0->>IMUX1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.SW6END3->>WW2BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.NW6END1->>NN2BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.NE2END_S3_0->>IMUX39": { + "src_wire": "NE2END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.NL1END2->>IMUX44": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.NL1END2->>IMUX12": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.LOGIC_OUTS4->>SS6BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.LOGIC_OUTS3->>SW2BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.LOGIC_OUTS20->>IMUX4": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.LOGIC_OUTS8->>NE6BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.NE6END1->>WR1BEG2": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.NW2END1->>IMUX34": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.SW2END2->>SS6BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.LOGIC_OUTS18->>IMUX17": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.EE2END3->>SW6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.SS6END3->>SR1BEG_S0": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.GFAN0->>IMUX18": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.LOGIC_OUTS16->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.NW2END3->>SW6BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.SW6END0->>NW2BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.NW2END2->>IMUX35": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.NE2END2->>IMUX5": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.SR1BEG_S0->>IMUX42": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.NE2END2->>WR1BEG3": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.WR1END0->>IMUX1": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.ER1END0->>LV18": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.GCLK_B5_EAST->>GFAN1": { + "src_wire": "GCLK_B5_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.WW2END3->>SS6BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.LOGIC_OUTS6->>WW2BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.EE2END1->>IMUX35": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.EE2END0->>IMUX33": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.VCC_WIRE->>IMUX44": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.ER1END1->>SL1BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.NN6END0->>NN6BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.SR1END2->>FAN_ALT5": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.NN6END0->>NE6BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.LOGIC_OUTS6->>IMUX37": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.NW2END0->>WW4BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.NE2END_S3_0->>BYP_ALT7": { + "src_wire": "NE2END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.WW4END1->>GFAN0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.WL1END1->>WR1BEG3": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.WW2END0->>WR1BEG2": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.WW4END2->>SW2BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.NW6END3->>NE6BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.VCC_WIRE->>IMUX43": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.LOGIC_OUTS21->>EL1BEG2": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.NE2END2->>LVB0": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.NW6END_S0_0->>WW2BEG3": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.NW2END_S0_0->>IMUX23": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.NW2END1->>FAN_ALT2": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.WL1END1->>IMUX19": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.SW6END0->>SE6BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.SW6END0->>NW6BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.LOGIC_OUTS4->>SW6BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.BYP_BOUNCE_N3_6->>FAN_ALT0": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.SW6END3->>LH0": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.WR1END3->>IMUX14": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.LOGIC_OUTS16->>SE2BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.EL1END0->>FAN_ALT4": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.GFAN1->>IMUX46": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.SS6END2->>WW4BEG3": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.NN2END0->>FAN_ALT0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.EE2END1->>NE6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX37": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.LOGIC_OUTS13->>IMUX35": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.SW6END3->>SE6BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.SE2END2->>IMUX21": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SR1END_N3_3->>IMUX8": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.LOGIC_OUTS4->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.NE2END1->>IMUX3": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.SW6END1->>ER1BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.NW6END2->>NN2BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.SW6END1->>SL1BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.SR1END3->>LH0": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.NR1END1->>EL1BEG0": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.EE4END3->>SS2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.NN6END2->>EL1BEG1": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.NN2END3->>WW2BEG2": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.SE6END3->>EE4BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.SW6END1->>SS6BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.WW2END1->>SW6BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SR1END2->>SS2BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.FAN_BOUNCE_S3_2->>FAN_ALT3": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.NR1END2->>BYP_ALT2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.LOGIC_OUTS18->>SR1BEG1": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX44": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.NW6END1->>NE6BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.NE6END2->>NW2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.SS6END3->>SE2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.EL1END0->>IMUX40": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.WL1END0->>IMUX9": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.NR1END0->>NW2BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.EE4END3->>SE2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.NE6END1->>EE4BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.NE6END0->>NN6BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.SW6END1->>SE6BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.BYP_BOUNCE4->>FAN_ALT7": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.NN2END2->>IMUX44": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.SW6END0->>EE4BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.LOGIC_OUTS10->>NE6BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.LOGIC_OUTS14->>EL1BEG1": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.SS2END0->>FAN_ALT4": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.NE2END3->>SE6BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.SL1END3->>IMUX47": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.SS2END1->>SS6BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.VCC_WIRE->>BYP_ALT2": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.NW2END1->>BYP_ALT4": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.LOGIC_OUTS10->>IMUX29": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.LOGIC_OUTS12->>SW2BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.LOGIC_OUTS11->>NN6BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.SE2END0->>SS2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.NR1END1->>IMUX11": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.NR1END2->>FAN_ALT7": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.SS2END0->>SL1BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.LOGIC_OUTS16->>SL1BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.BYP_BOUNCE1->>IMUX37": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.EE4END2->>NN6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.LOGIC_OUTS10->>SE2BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.LOGIC_OUTS1->>IMUX3": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS6->>EE4BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.EE4END3->>NE6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.LOGIC_OUTS4->>WW4BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.ER1END0->>IMUX18": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX23": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.SS2END_N0_3->>WW4BEG0": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.BYP_BOUNCE_N3_6->>FAN_ALT2": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.SE2END2->>EE2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.SW6END2->>LVB12": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.NN2END1->>IMUX33": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX8": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.SS2END3->>WW2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.NE6END0->>NE6BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.SR1BEG_S0->>LV0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV0" + }, + "INT_R.NN2END1->>IMUX42": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.WW4END3->>NW2BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.SS6END0->>NR1BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.EE2END0->>IMUX9": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SE2END1->>NR1BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.LOGIC_OUTS21->>SW2BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.LOGIC_OUTS17->>SL1BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.NW2END0->>NE2BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.WW2END0->>ER1BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.WW2END1->>WR1BEG3": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.ER1END2->>NR1BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.NE2END0->>SE2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.SS6END2->>EE2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.LOGIC_OUTS16->>NN6BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.LOGIC_OUTS17->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.LVB0->>SS6BEG2": { + "src_wire": "LVB0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.SS2END2->>SS6BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.EE2END3->>IMUX47": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.SS2END2->>IMUX21": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SS6END0->>NW6BEG1": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.EE2END0->>EL1BEG_N3": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.SE2END3->>IMUX31": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.WL1END3->>WW2BEG3": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.NE2END3->>IMUX46": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.FAN_BOUNCE5->>BYP_ALT5": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.WW2END2->>IMUX13": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.FAN_BOUNCE1->>FAN_ALT6": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.LOGIC_OUTS7->>NW6BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.FAN_BOUNCE5->>CLK0": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.NR1END1->>WR1BEG2": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.SW2END0->>WW2BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.EE2END1->>IMUX19": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.SW6END3->>SR1BEG_S0": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.LOGIC_OUTS10->>IMUX13": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.NR1END2->>IMUX12": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.SS6END1->>WW2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.LOGIC_OUTS16->>NN2BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.WR1END0->>IMUX32": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.NR1END1->>EE2BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.LH6->>NW6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.NN2END0->>WR1BEG1": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.NE2END2->>BYP_ALT5": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.BYP_BOUNCE0->>IMUX36": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.NR1END3->>IMUX14": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.LOGIC_OUTS23->>EL1BEG0": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.NR1END1->>IMUX34": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.EE2END0->>BYP_ALT1": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.LOGIC_OUTS7->>NN2BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.WW4END3->>SR1BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX6": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.LOGIC_OUTS18->>IMUX33": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.SW2END2->>SR1BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.LOGIC_OUTS9->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.NL1END2->>NL1BEG1": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.SL1END0->>ER1BEG1": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.WR1END1->>CLK0": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.SS2END3->>IMUX7": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.SS6END0->>SL1BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.FAN_BOUNCE2->>IMUX40": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.ER1END0->>NE2BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.WL1END_N1_3->>IMUX8": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.NL1END1->>IMUX1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.NN2END2->>EE2BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.NE6END2->>NE2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.ER1END0->>IMUX2": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.SL1END3->>IMUX39": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.WW4END0->>NE6BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.LOGIC_OUTS2->>SW2BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.SR1END3->>SW2BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.BYP_BOUNCE3->>IMUX39": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.LOGIC_OUTS0->>IMUX40": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.SE2END1->>SE6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.LOGIC_OUTS8->>IMUX1": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.WW2END2->>WW4BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.EL1END0->>IMUX24": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.LVB12->>SE6BEG2": { + "src_wire": "LVB12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.EE4END1->>SS6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.LOGIC_OUTS3->>BYP_ALT7": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.SE2END3->>NR1BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.EL1END3->>SL1BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.NR1END0->>IMUX40": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.FAN_BOUNCE6->>IMUX1": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.NW2END1->>IMUX18": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.EE4END2->>CTRL1": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.WW2END1->>SW2BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.EE2END0->>NE6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.NE2END1->>NW2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.EE2END0->>SS6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.WR1END_S1_0->>SR1BEG_S0": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.LOGIC_OUTS15->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.NW2END3->>WW4BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.NE2END3->>WR1BEG_S0": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.SW2END_N0_3->>NL1BEG_N3": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.LOGIC_OUTS8->>IMUX33": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.SW2END2->>IMUX44": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.LOGIC_OUTS14->>SS6BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.NW2END2->>NL1BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.LOGIC_OUTS19->>NE2BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.NL1END1->>IMUX18": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.NR1END3->>EE2BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.WL1END1->>IMUX34": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.EL1END1->>SS2BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.SW6END2->>SR1BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.SL1END2->>IMUX12": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.WL1END1->>SR1BEG2": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.WR1END_S1_0->>WW2BEG3": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.BYP_BOUNCE3->>IMUX23": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.BYP_BOUNCE4->>IMUX30": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.LOGIC_OUTS7->>NR1BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.NE2END3->>FAN_ALT3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.SL1END3->>IMUX31": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.LVB0->>SW6BEG2": { + "src_wire": "LVB0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.NN2END3->>EE2BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.NN2END3->>WR1BEG_S0": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.NW2END0->>IMUX0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.GFAN0->>IMUX26": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.EL1END3->>IMUX14": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.BYP_BOUNCE0->>IMUX44": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.NL1END1->>NW2BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.NW2END1->>WR1BEG2": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.FAN_BOUNCE1->>IMUX18": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.LOGIC_OUTS9->>NE6BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX13": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.NL1END0->>IMUX16": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.LOGIC_OUTS22->>SE6BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.WL1END2->>WR1BEG_S0": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.NE2END2->>IMUX35": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.SE2END3->>FAN_ALT3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.SS2END_N0_3->>IMUX0": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.NW6END3->>NL1BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.NW6END2->>NE6BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.NN2END3->>BYP_ALT6": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NN6END2->>NN2BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.LOGIC_OUTS11->>WL1BEG2": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.NN2END3->>IMUX14": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.SS2END3->>NR1BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.NE2END1->>EL1BEG0": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.NE2END1->>EE2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.LOGIC_OUTS16->>NE2BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.BYP_BOUNCE5->>IMUX47": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.SL1END1->>SL1BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.GFAN0->>IMUX8": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.SL1END2->>IMUX28": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.NW2END2->>NW2BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.SS2END0->>WW4BEG1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.GFAN0->>FAN_ALT6": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NN6END3->>NR1BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.GCLK_B5_EAST->>CLK0": { + "src_wire": "GCLK_B5_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.EL1END2->>SE2BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.BYP_BOUNCE0->>IMUX26": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.NW2END2->>SW2BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.NE2END1->>EE4BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.EE2END2->>SL1BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.NE2END3->>LH0": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.LOGIC_OUTS13->>SS2BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.EE2END3->>IMUX46": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.WW4END2->>NN6BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.GFAN0->>FAN_ALT4": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.SW6END0->>LV18": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.NL1BEG_N3->>BYP_ALT6": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.EL1END3->>IMUX22": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.EL1END1->>IMUX18": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.NE6END1->>NN6BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.NW2END1->>WW2BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.LOGIC_OUTS22->>NN6BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.NW2END1->>WL1BEG_N3": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.LOGIC_OUTS1->>IMUX43": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NN2END3->>NE2BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.NE2END1->>BYP_ALT4": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.EE2END3->>IMUX15": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.SW6END1->>NW2BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.NR1END0->>BYP_ALT0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.LOGIC_OUTS13->>SR1BEG2": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.SR1END1->>IMUX3": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.EE2END1->>NE2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.SE6END3->>SS6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.LOGIC_OUTS18->>IMUX41": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.ER1END2->>IMUX21": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.LOGIC_OUTS8->>WW4BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.NE6END0->>NL1BEG_N3": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.LOGIC_OUTS5->>IMUX42": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.LOGIC_OUTS0->>WW2BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.NW2END1->>SW2BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.WR1END1->>SR1BEG1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.EE4END2->>SS6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.SW6END0->>WW2BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.SE2END0->>ER1BEG1": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.NN6END1->>NE6BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.NL1END0->>IMUX0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.LOGIC_OUTS4->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.NE2END1->>FAN_ALT6": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.LOGIC_OUTS22->>NN2BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.LH12->>WW4BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.LOGIC_OUTS3->>NE2BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.NE6END2->>NL1BEG1": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.GFAN1->>IMUX15": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.SE6END1->>SW2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.LOGIC_OUTS8->>NW6BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.SS2END2->>IMUX22": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.WL1END3->>IMUX38": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.NE2END0->>NW2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.NE2END1->>IMUX2": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.EE2END1->>ER1BEG2": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.SW6END2->>NW6BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.LOGIC_OUTS8->>SL1BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.WW2END_N0_3->>FAN_ALT0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX1": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.SW6END_N0_3->>NW2BEG0": { + "src_wire": "SW6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.NW6END3->>LVB0": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.EL1END3->>IMUX37": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.NN6END3->>EL1BEG2": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.GFAN1->>BYP_ALT6": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.WL1END2->>BYP_ALT3": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.LOGIC_OUTS3->>NW6BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.SW6END0->>SL1BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.NE6END1->>NE6BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX22": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.VCC_WIRE->>IMUX21": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.LOGIC_OUTS13->>NN2BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.WW2END_N0_3->>NN2BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX10": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.NW2END0->>BYP_ALT0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.NE2END1->>IMUX10": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.EL1END1->>SL1BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.LOGIC_OUTS1->>NR1BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX38": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.EL1END0->>SL1BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.SE2END2->>EE4BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.LV18->>WW4BEG3": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.LOGIC_OUTS21->>IMUX39": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.WW2END2->>NE6BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.NL1END1->>NL1BEG0": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.SE6END1->>SS6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.LOGIC_OUTS18->>IMUX1": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.LOGIC_OUTS18->>SL1BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.LOGIC_OUTS10->>NN2BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX9": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.LV0->>SW6BEG0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.SS2END2->>FAN_ALT1": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.WL1END2->>WW2BEG2": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.LOGIC_OUTS9->>IMUX10": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.BYP_BOUNCE1->>IMUX5": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.NR1END2->>EL1BEG1": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.NE2END3->>IMUX23": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.EE2END3->>NR1BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.GCLK_B1_EAST->>GFAN1": { + "src_wire": "GCLK_B1_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.WR1END3->>SR1BEG3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.LOGIC_OUTS17->>WW4BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.FAN_BOUNCE7->>IMUX42": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.SE6END3->>NE6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.NR1END0->>IMUX32": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.WR1END3->>WR1BEG_S0": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.SE2END0->>EE4BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.LOGIC_OUTS9->>NW6BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.LOGIC_OUTS21->>IMUX7": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.NR1END3->>IMUX47": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.LOGIC_OUTS19->>WW2BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.SW2END0->>WL1BEG_N3": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.GCLK_B6->>GFAN0": { + "src_wire": "GCLK_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.SS2END2->>IMUX36": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.SW2END1->>IMUX35": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.NL1BEG_N3->>IMUX37": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.NN6END_S1_0->>WW2BEG3": { + "src_wire": "NN6END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.SS6END3->>EE4BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.EE4END3->>WR1BEG_S0": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.LOGIC_OUTS13->>NL1BEG0": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.NE2END0->>IMUX24": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.WR1END1->>IMUX33": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.GCLK_B8->>CLK0": { + "src_wire": "GCLK_B8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.LOGIC_OUTS18->>WR1BEG1": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.LOGIC_OUTS19->>NR1BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.LH12->>NN6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.ER1END2->>IMUX44": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.NW2END3->>IMUX14": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.LV9->>SE6BEG1": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.LOGIC_OUTS22->>SW6BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.WW4END_S0_0->>SW2BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.NR1END0->>FAN_ALT4": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.NE6END2->>EE2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.NE6END2->>SL1BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.LOGIC_OUTS23->>IMUX43": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.BYP_BOUNCE5->>FAN_ALT5": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.WW2END0->>FAN_ALT2": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.SE6END2->>EE2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.SR1END2->>FAN_ALT1": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.WW4END3->>SS6BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.FAN_ALT3->>FAN_BOUNCE3": { + "src_wire": "FAN_ALT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE3" + }, + "INT_R.LOGIC_OUTS18->>EE2BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.BYP_BOUNCE5->>IMUX15": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.FAN_BOUNCE1->>IMUX12": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.LOGIC_OUTS18->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.SE2END2->>IMUX4": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.LOGIC_OUTS14->>IMUX44": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.WW2END0->>IMUX17": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.NW2END1->>IMUX26": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.GCLK_B2_EAST->>CLK0": { + "src_wire": "GCLK_B2_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.LOGIC_OUTS3->>EE2BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX11": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.LVB0<<->>LVB12": { + "src_wire": "LVB0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.SE2END3->>IMUX38": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.LOGIC_OUTS14->>WR1BEG3": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.WL1END0->>WL1BEG_N3": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.ER1END2->>EL1BEG1": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.WL1END1->>IMUX20": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.EE4END0->>SE6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.LOGIC_OUTS22->>IMUX16": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.LOGIC_OUTS20->>SS6BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.LOGIC_OUTS1->>EL1BEG0": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.ER1END1->>IMUX42": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.WW4END3->>ER1BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.WL1END1->>FAN_ALT7": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.NW2END1->>IMUX42": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.GFAN1->>FAN_ALT5": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.EE2END3->>BYP_ALT6": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.BYP_BOUNCE5->>IMUX7": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.BYP_BOUNCE1->>IMUX35": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.LOGIC_OUTS10->>SS6BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX7": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.LOGIC_OUTS11->>NL1BEG2": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.WW2END1->>BYP_ALT5": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.SW2END2->>IMUX13": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.ER1END_N3_3->>IMUX8": { + "src_wire": "ER1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.WW2END3->>IMUX15": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.LOGIC_OUTS20->>SR1BEG3": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.EE4END2->>CTRL0": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.FAN_BOUNCE7->>IMUX16": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.LOGIC_OUTS12->>SE2BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.SS2END0->>SW6BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.GCLK_B5->>GCLK_B5_EAST": { + "src_wire": "GCLK_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B5_EAST" + }, + "INT_R.FAN_BOUNCE6->>IMUX41": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.EL1END1->>IMUX33": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.SW6END3->>ER1BEG_S0": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.LOGIC_OUTS0->>SE2BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.LOGIC_OUTS12->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.GCLK_B2_EAST->>GFAN0": { + "src_wire": "GCLK_B2_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.SE2END0->>FAN_ALT4": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.LOGIC_OUTS17->>EE2BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.NE2END2->>IMUX27": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.EE2END3->>SS6BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.EE2END3->>EE2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.NN2END_S2_0->>IMUX39": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.SW6END0->>WL1BEG_N3": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.LOGIC_OUTS22->>BYP_ALT0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.WR1END3->>BYP_ALT6": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.WL1END0->>IMUX25": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.WR1END_S1_0->>IMUX39": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.NW6END3->>SR1BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.LOGIC_OUTS5->>NR1BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.LOGIC_OUTS22->>NE6BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.LOGIC_OUTS19->>SW6BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SR1END3->>ER1BEG_S0": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.LOGIC_OUTS14->>NW2BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.WW2END1->>NW2BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.BYP_BOUNCE_N3_3->>BYP_ALT0": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.SR1END1->>IMUX44": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.EE2END3->>EL1BEG2": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.SS6END_N0_3->>WW4BEG0": { + "src_wire": "SS6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.SL1END0->>SE2BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.LOGIC_OUTS17->>SW6BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.NE2END1->>IMUX33": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.VCC_WIRE->>IMUX29": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.LH12->>NE6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.LV0->>SE6BEG0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.ER1END1->>CLK1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.NW2END3->>NW6BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.LOGIC_OUTS11->>SW6BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.LOGIC_OUTS4->>IMUX41": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.WW2END1->>NE6BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.SL1END3->>FAN_ALT3": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.NL1END2->>IMUX11": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.NW2END3->>IMUX29": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.BYP_BOUNCE3->>IMUX47": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.SW2END1->>ER1BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.SW2END1->>SW6BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SR1BEG_S0->>IMUX25": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.SE2END0->>NE2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.SR1BEG_S0->>IMUX1": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.SE2END0->>NE6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.SL1END2->>IMUX29": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.LOGIC_OUTS4->>SW2BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.WR1END2->>SW2BEG1": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.LOGIC_OUTS1->>NW2BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.WW4END2->>SS6BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.ER1END2->>FAN_ALT1": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.LOGIC_OUTS12->>NN6BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.LOGIC_OUTS20->>NE6BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.NN6END3->>LVB12": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.NE2END2->>BYP_ALT2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.WR1END1->>CLK1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.NW6END_S0_0->>SW2BEG3": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.SL1END2->>FAN_ALT7": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.SW6END0->>ER1BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.SS6END3->>WL1BEG2": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.EE2END0->>WR1BEG1": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.LOGIC_OUTS4->>NW6BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.LOGIC_OUTS20->>WW2BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.WL1END2->>IMUX22": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.EE4END2->>SE2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.NL1END0->>IMUX8": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.WL1END1->>WW2BEG1": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.SW2END2->>IMUX22": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.LOGIC_OUTS12->>WW2BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.EE2END0->>EE2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.FAN_ALT5->>FAN_BOUNCE5": { + "src_wire": "FAN_ALT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE5" + }, + "INT_R.SL1END0->>BYP_ALT0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.SE6END0->>SS6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.BYP_BOUNCE2->>IMUX46": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.EE2END0->>BYP_ALT0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.SL1END2->>IMUX13": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.NR1END0->>NL1BEG_N3": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.SE6END3->>SE6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.WL1END0->>SR1BEG1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.LOGIC_OUTS14->>SE6BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.LOGIC_OUTS16->>EE2BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.EL1END1->>FAN_ALT6": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.WW2END2->>SR1BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.FAN_ALT3->>FAN3": { + "src_wire": "FAN_ALT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN3" + }, + "INT_R.NE2END1->>SL1BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.SW6END2->>SW2BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.GCLK_B5->>GCLK_B5_WEST": { + "src_wire": "GCLK_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B5_WEST" + }, + "INT_R.NR1END2->>IMUX13": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.WL1END_N1_3->>IMUX0": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.SS2END0->>BYP_ALT1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.LV9->>NN6BEG1": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.WR1END2->>NL1BEG1": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.SS6END3->>ER1BEG_S0": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.SL1END2->>SL1BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.NL1BEG_N3->>IMUX46": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.LOGIC_OUTS23->>EE2BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.WR1END0->>WR1BEG1": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.NW2END1->>SR1BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.NW2END1->>IMUX25": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.ER1END1->>IMUX19": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.LOGIC_OUTS4->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.SW2END2->>NW6BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.NN2END2->>FAN_ALT5": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.FAN_BOUNCE2->>IMUX0": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.LOGIC_OUTS20->>WW4BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.NE6END0->>NW6BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.LH0->>SS6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.NE2END3->>IMUX14": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX45": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.SS6END3->>LH12": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.NW2END1->>SS6BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.WW2END0->>IMUX9": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SS6END0->>WW4BEG1": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.NW6END3->>NW2BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.SE2END2->>WL1BEG1": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.WL1END2->>IMUX21": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX38": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.LOGIC_OUTS22->>NW6BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.BYP_ALT5->>BYP5": { + "src_wire": "BYP_ALT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP5" + }, + "INT_R.NE2END0->>IMUX1": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.EE4END3->>EL1BEG2": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.WR1END3->>FAN_ALT3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.SW2END2->>SW2BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.NN2END1->>WW4BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.NL1END1->>IMUX2": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.BYP_BOUNCE4->>IMUX6": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.SL1END0->>WW2BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.EL1END2->>IMUX27": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.ER1END1->>FAN_ALT7": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.NL1END2->>IMUX43": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NW2END0->>IMUX40": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.LOGIC_OUTS0->>IMUX16": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.LH0->>NW6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.SS2END3->>WL1BEG2": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX16": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.NW2END1->>IMUX2": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.EE4END2->>NE2BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.LOGIC_OUTS7->>EE4BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.SE6END2->>CTRL0": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.NN6END0->>EL1BEG_N3": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.SW2END2->>NL1BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.LOGIC_OUTS16->>NW6BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.SW2END0->>IMUX18": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.LOGIC_OUTS13->>WL1BEG0": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.SS2END1->>FAN_ALT6": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NW2END3->>WR1BEG_S0": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.NE6END2->>EL1BEG1": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.NE6END3->>NL1BEG2": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.NL1END0->>NL1BEG_N3": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.WW2END0->>NW6BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.LOGIC_OUTS14->>NE2BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.SR1BEG_S0->>SS2BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.ER1END3->>BYP_ALT7": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.SS6END0->>ER1BEG1": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.EL1END1->>FAN_ALT2": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.SS2END1->>BYP_ALT4": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.WW2END0->>BYP_ALT4": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.LOGIC_OUTS4->>NW2BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.SS6END3->>SE6BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.NN6END1->>WR1BEG2": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.LOGIC_OUTS19->>SE2BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.NN2END1->>NE6BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.LVB12->>WW4BEG2": { + "src_wire": "LVB12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.GFAN0->>IMUX43": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.BYP_BOUNCE2->>BYP_ALT3": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.WL1END2->>NL1BEG2": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.NN2END3->>NR1BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.SE6END1->>SS2BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.NR1END1->>GFAN0": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.SE6END2->>NR1BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.FAN_BOUNCE1->>IMUX4": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.SW6END1->>NW6BEG2": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.SW2END1->>NW2BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.NE2END0->>NE6BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.SW2END2->>WW4BEG3": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.SE2END0->>IMUX32": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.SW2END0->>IMUX32": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.NL1END2->>IMUX4": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.EE2END2->>EL1BEG1": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.WR1END1->>IMUX42": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.NL1END_S3_0->>IMUX7": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.LOGIC_OUTS15->>WL1BEG2": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.NL1BEG_N3->>IMUX30": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.NW2END3->>IMUX5": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.LOGIC_OUTS13->>WW4BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.NE2END3->>IMUX15": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.NL1BEG_N3->>FAN_ALT1": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX2": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.LV9->>EE4BEG1": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.LOGIC_OUTS15->>SW2BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.SE2END3->>LVB12": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.BYP_BOUNCE4->>IMUX44": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.LOGIC_OUTS19->>SS6BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.WW2END0->>SS2BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.NL1END1->>FAN_ALT4": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.NE2END0->>IMUX16": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.NN6END3->>LVB0": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.LOGIC_OUTS3->>SS2BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.FAN_ALT0->>FAN0": { + "src_wire": "FAN_ALT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN0" + }, + "INT_R.GND_WIRE->>GFAN0": { + "src_wire": "GND_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.NN2END0->>IMUX32": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.GCLK_B10->>GFAN0": { + "src_wire": "GCLK_B10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.LVB12->>NE6BEG2": { + "src_wire": "LVB12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.SE2END2->>IMUX29": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.ER1END1->>IMUX4": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.WL1END0->>IMUX2": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.SW2END2->>IMUX5": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.NE2END2->>NW2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.NE6END3->>NN6BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.NL1END2->>NN2BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.SS6END2->>SL1BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.SS2END2->>FAN_ALT5": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.SS2END1->>IMUX19": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.LOGIC_OUTS2->>NN2BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.LOGIC_OUTS2->>SW6BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.ER1END2->>SL1BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.WR1END3->>IMUX23": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.LOGIC_OUTS16->>SW6BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.LOGIC_OUTS2->>SS2BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.ER1END1->>SE2BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.NE6END2->>WR1BEG3": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.LH6->>SE6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.NE2END1->>NE6BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.ER1END0->>FAN_ALT4": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.NN2END2->>WR1BEG3": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.EL1END2->>IMUX12": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.WW4END3->>SS2BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.EL1END0->>EL1BEG_N3": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.SE6END1->>EE4BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.WW2END1->>WW2BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.LOGIC_OUTS10->>EE2BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.LOGIC_OUTS19->>EL1BEG0": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.ER1END0->>LV0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV0" + }, + "INT_R.LVB0->>NN6BEG2": { + "src_wire": "LVB0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.SS6END0->>SW2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.GCLK_B2->>GCLK_B2_EAST": { + "src_wire": "GCLK_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B2_EAST" + }, + "INT_R.EL1END2->>IMUX35": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.SE2END1->>SE2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.WR1END3->>IMUX6": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.LOGIC_OUTS17->>IMUX46": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.NN6END2->>NW6BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.SS2END2->>EE4BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.WW2END_N0_3->>IMUX8": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.EE4END2->>NE6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.NN2END0->>IMUX8": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.NE2END2->>NL1BEG1": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.VCC_WIRE->>FAN_ALT4": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.NE2END1->>IMUX25": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.LOGIC_OUTS11->>SE2BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.NN2END0->>NR1BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.SW2END2->>SW6BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.LOGIC_OUTS16->>NR1BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.NE2END1->>WW4BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.EL1END2->>IMUX5": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.SE2END0->>IMUX41": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.LOGIC_OUTS0->>IMUX32": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.SE2END1->>IMUX11": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.LOGIC_OUTS7->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.LOGIC_OUTS0->>NR1BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.SS2END1->>IMUX35": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.NN6END3->>NN2BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.SR1END1->>ER1BEG2": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.EE2END2->>IMUX12": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.LOGIC_OUTS16->>WR1BEG3": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.ER1END_N3_3->>IMUX16": { + "src_wire": "ER1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.EE2END2->>SS2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.WW2END2->>IMUX14": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.LOGIC_OUTS2->>NE6BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.WW4END1->>NW2BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.NN6END2->>NN6BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.WW2END0->>NN6BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.LOGIC_OUTS4->>IMUX33": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.FAN_BOUNCE3->>IMUX21": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SE2END0->>EL1BEG_N3": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.LOGIC_OUTS16->>IMUX37": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.LOGIC_OUTS21->>EE2BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.SS6END1->>ER1BEG2": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.FAN_BOUNCE6->>BYP_ALT1": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.ER1END2->>IMUX28": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.LOGIC_OUTS17->>IMUX38": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.WW4END1->>WR1BEG2": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.LH12->>SW6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.LOGIC_OUTS22->>SL1BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.LOGIC_OUTS15->>NN2BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.NR1END2->>IMUX29": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.LOGIC_OUTS16->>SE6BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.SE2END0->>IMUX0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.NE2END3->>NW2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.WW2END2->>NW6BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.NR1END1->>BYP_ALT4": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.NR1END1->>NR1BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.LOGIC_OUTS5->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.NW2END3->>NN2BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.NR1END3->>IMUX15": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.ER1END3->>SS2BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.NR1END0->>IMUX9": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SW2END1->>IMUX43": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.LOGIC_OUTS18->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.WW4END2->>SR1BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.GFAN1->>IMUX30": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.WR1END2->>SR1BEG2": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.NW6END3->>LVB12": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.WW4END0->>LV18": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.VCC_WIRE->>IMUX22": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.GFAN1->>IMUX36": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.GCLK_B9->>CLK1": { + "src_wire": "GCLK_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.LV9->>WW4BEG1": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.GFAN1->>IMUX47": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.LOGIC_OUTS9->>IMUX34": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX9": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.LOGIC_OUTS21->>NN6BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX31": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.GFAN0->>BYP_ALT1": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.LOGIC_OUTS8->>SE2BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX28": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.LOGIC_OUTS14->>IMUX20": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.SE2END2->>SW6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.WW2END_N0_3->>IMUX24": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.BYP_BOUNCE4->>BYP_ALT5": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.GFAN1->>IMUX39": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.LOGIC_OUTS20->>EE2BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.NW6END0->>LV0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV0" + }, + "INT_R.LOGIC_OUTS13->>ER1BEG2": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.WL1END0->>IMUX40": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.ER1END3->>NE2BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.SW2END2->>BYP_ALT2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.WW2END2->>IMUX22": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.SR1END3->>IMUX31": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.WW2END_N0_3->>NL1BEG_N3": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.SR1BEG_S0->>IMUX33": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.SS2END0->>IMUX40": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.NE2END0->>NW6BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.WW2END1->>SS6BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.SW2END3->>SS2BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.NR1END2->>IMUX28": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.SL1END0->>IMUX17": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.EL1END1->>IMUX26": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.FAN_BOUNCE5->>IMUX33": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.LOGIC_OUTS21->>IMUX31": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.LOGIC_OUTS11->>SL1BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.LV9->>NE6BEG1": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.SW6END_N0_3->>WW4BEG0": { + "src_wire": "SW6END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.LOGIC_OUTS22->>EE2BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.EL1END0->>IMUX17": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.LOGIC_OUTS1->>NE6BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.BYP_BOUNCE5->>FAN_ALT3": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.SR1END1->>SS2BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.SS2END1->>IMUX11": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.NW2END1->>IMUX10": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.NL1END2->>IMUX28": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.SR1END3->>SS2BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.NW2END3->>IMUX38": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.WW2END2->>FAN_ALT1": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.SL1END0->>SW2BEG0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.EE2END3->>NN2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.VCC_WIRE->>IMUX14": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.WR1END2->>NW2BEG2": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.LOGIC_OUTS7->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.NN2END2->>NW2BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.LOGIC_OUTS7->>WW4BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.NW6END2->>NE2BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.LOGIC_OUTS3->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.LOGIC_OUTS19->>SE6BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.NN2END1->>EE4BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.LOGIC_OUTS8->>IMUX9": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SL1END1->>IMUX26": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.GCLK_B3->>GCLK_B3_WEST": { + "src_wire": "GCLK_B3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B3_WEST" + }, + "INT_R.LOGIC_OUTS1->>IMUX19": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.SE2END2->>SS2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.BYP_ALT1->>BYP1": { + "src_wire": "BYP_ALT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP1" + }, + "INT_R.LOGIC_OUTS23->>IMUX3": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.NN2END2->>FAN_ALT7": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.BYP_BOUNCE1->>IMUX45": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.LH12->>EE4BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.LOGIC_OUTS3->>SW6BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.LOGIC_OUTS13->>NR1BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.NN6END3->>WW4BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.NE2END3->>NE2BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.NN6END3->>EE4BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.NR1END1->>BYP_ALT5": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.SE2END1->>IMUX10": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.NE6END3->>NN2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.LOGIC_OUTS23->>IMUX27": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.LV18->>NN6BEG3": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.NN6END2->>CTRL1": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.LOGIC_OUTS4->>EE4BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.NE6END1->>SE6BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.WW4END0->>NN6BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.LOGIC_OUTS20->>IMUX36": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.VCC_WIRE->>IMUX28": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.SE6END3->>NR1BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.NN2END1->>NW6BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.NE6END1->>NE2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.FAN_BOUNCE5->>CLK1": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.NW2END2->>LVB0": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.SR1END_N3_3->>IMUX40": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.NW2END1->>WW4BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.FAN_BOUNCE2->>IMUX16": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.LOGIC_OUTS15->>NW6BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.SE2END0->>SW6BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.WW2END1->>SR1BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.GCLK_B3_EAST->>CLK1": { + "src_wire": "GCLK_B3_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.NR1END1->>GFAN1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.BYP_BOUNCE1->>GFAN1": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.SW6END3->>SW6BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.WL1END1->>NL1BEG1": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.NE2END2->>SE2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.SW2END1->>FAN_ALT6": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.ER1END0->>IMUX32": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.SE6END3->>WL1BEG2": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.LOGIC_OUTS22->>NW2BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.NN2END1->>NN2BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.NR1END3->>BYP_ALT7": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.NE2END3->>IMUX7": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.LOGIC_OUTS1->>NN6BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.LOGIC_OUTS1->>NE2BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.LOGIC_OUTS2->>IMUX44": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.WL1END2->>IMUX13": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.SR1END1->>FAN_ALT6": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NW2END_S0_0->>IMUX31": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.SR1END1->>IMUX28": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.SE2END0->>BYP_ALT1": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.FAN_BOUNCE5->>FAN_ALT7": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.LOGIC_OUTS21->>WL1BEG2": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.WR1END1->>IMUX41": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.EE4END1->>SS2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.NE2END3->>NE6BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.WW4END2->>NW6BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.EE4END3->>NN2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.LVB0->>NE6BEG2": { + "src_wire": "LVB0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.LOGIC_OUTS22->>IMUX0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.WW2END1->>FAN_ALT6": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.GCLK_B3_EAST->>GFAN1": { + "src_wire": "GCLK_B3_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.LOGIC_OUTS23->>NW6BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.LOGIC_OUTS0->>IMUX0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX30": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.LOGIC_OUTS18->>EE4BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.SS2END0->>IMUX1": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.NW2END_S0_0->>SR1BEG_S0": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.ER1END0->>EL1BEG_N3": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.SS2END2->>NR1BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.LOGIC_OUTS10->>IMUX37": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.LOGIC_OUTS0->>IMUX8": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.SW6END2->>WW2BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.WW2END2->>ER1BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.LOGIC_OUTS14->>SW2BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.NW2END2->>FAN_ALT6": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NE2END2->>FAN_ALT7": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.ER1END1->>NE2BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.WW2END2->>WW2BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.EE4END2->>WR1BEG3": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.LOGIC_OUTS8->>NN2BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.SE6END0->>EE2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.LOGIC_OUTS19->>IMUX42": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.LOGIC_OUTS16->>SR1BEG3": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.NW2END_S0_0->>IMUX47": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.SR1BEG_S0->>IMUX17": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.NE2END3->>SL1BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.SR1END2->>IMUX37": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.ER1END3->>LH0": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.LOGIC_OUTS11->>SR1BEG_S0": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.NN2END0->>IMUX9": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.NL1END1->>IMUX41": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.LOGIC_OUTS18->>FAN_ALT4": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.SS6END1->>SS2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.LOGIC_OUTS10->>IMUX45": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.VCC_WIRE->>FAN_ALT6": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NW6END3->>EL1BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.SL1END1->>ER1BEG2": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.WR1END3->>WL1BEG1": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.NN2END1->>IMUX19": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.GFAN0->>BYP_ALT0": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.LOGIC_OUTS10->>SW6BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.LOGIC_OUTS2->>SE6BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.WW4END2->>SS2BEG1": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.SE2END2->>FAN_ALT5": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.BYP_BOUNCE4->>IMUX4": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.WL1END1->>IMUX35": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.LOGIC_OUTS2->>NW6BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.GFAN0->>IMUX9": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.FAN_BOUNCE5->>IMUX25": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.EE2END0->>IMUX17": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.FAN_BOUNCE3->>IMUX11": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.GFAN0->>IMUX2": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.LOGIC_OUTS4->>NN6BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.ER1END3->>ER1BEG_S0": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.NE2END3->>IMUX38": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.WR1END1->>NN2BEG1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.VCC_WIRE->>IMUX6": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.LOGIC_OUTS5->>SE6BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.SL1END0->>IMUX24": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.LOGIC_OUTS18->>NN6BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.SS2END2->>IMUX37": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.NE6END3->>NR1BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.LOGIC_OUTS11->>NW6BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.SL1END1->>BYP_ALT4": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.EE4END0->>NR1BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.LOGIC_OUTS17->>WL1BEG2": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.LOGIC_OUTS4->>SR1BEG1": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.BYP_BOUNCE4->>FAN_ALT1": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.NE6END3->>NE2BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.LOGIC_OUTS0->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.GCLK_B2_EAST->>GFAN1": { + "src_wire": "GCLK_B2_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.SW6END1->>SW6BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.FAN_BOUNCE2->>FAN_ALT4": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.EL1END2->>IMUX36": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.FAN_BOUNCE_S3_2->>BYP_ALT6": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.SE2END2->>IMUX44": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.SR1END2->>SE2BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.WW2END_N0_3->>NW2BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.SS6END1->>SE6BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.LOGIC_OUTS20->>SE6BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.LOGIC_OUTS10->>EE4BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.SS6END2->>CTRL0": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.SS6END3->>SS6BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.WW2END1->>FAN_ALT7": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.NE2END3->>LH12": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.NN6END3->>SR1BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.WW2END2->>SW2BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.GCLK_B11->>GFAN1": { + "src_wire": "GCLK_B11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.SL1END3->>BYP_ALT6": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.LV18->>SE6BEG3": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.GCLK_B4_EAST->>CLK0": { + "src_wire": "GCLK_B4_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.VCC_WIRE->>IMUX30": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.GFAN0->>CTRL1": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.ER1END0->>IMUX40": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.ER1END0->>IMUX1": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.SS2END0->>IMUX32": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.NW2END3->>LH12": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.SR1BEG_S0->>FAN_ALT4": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.LV0->>EE4BEG0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.SS2END2->>IMUX13": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.LOGIC_OUTS2->>WL1BEG1": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.VCC_WIRE->>IMUX26": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.NW2END2->>SW6BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.NN6END1->>NW2BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.LOGIC_OUTS12->>SR1BEG1": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.SS2END0->>IMUX24": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.SS6END0->>SE6BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.SW6END1->>WL1BEG0": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.SL1END3->>IMUX46": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.NE6END2->>NN6BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.NN2END0->>NW6BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.EE2END2->>ER1BEG3": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.NE2END0->>NR1BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.BYP_BOUNCE1->>BYP_ALT2": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.WW2END1->>IMUX28": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.WW2END2->>FAN_ALT5": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.VCC_WIRE->>IMUX24": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.EL1END1->>IMUX25": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.WW2END0->>WW4BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.LOGIC_OUTS10->>WL1BEG1": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.LOGIC_OUTS6->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.LOGIC_OUTS6->>WL1BEG1": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.WR1END1->>FAN_ALT2": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.LOGIC_OUTS17->>NE2BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.SW6END0->>SS6BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.SL1END1->>IMUX2": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.SE6END0->>SE6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.EE2END1->>SE2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.SS6END0->>WW2BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.LOGIC_OUTS0->>SL1BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.SW2END2->>IMUX14": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.SE2END3->>IMUX7": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.EE2END2->>IMUX44": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.SW6END1->>NL1BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.WR1END2->>IMUX21": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SW2END3->>ER1BEG_S0": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.EL1END3->>ER1BEG_S0": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.LOGIC_OUTS16->>WW4BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.VCC_WIRE->>IMUX38": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.FAN_BOUNCE2->>IMUX32": { + "src_wire": "FAN_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.SS6END0->>SR1BEG1": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.NR1END3->>NL1BEG2": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.WR1END3->>IMUX29": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.ER1END3->>EL1BEG2": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.LOGIC_OUTS6->>SW2BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.ER1END1->>CLK0": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.SS2END1->>WW2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.LOGIC_OUTS2->>IMUX12": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.WW2END3->>FAN_ALT3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.SE2END3->>SS6BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.NN2END3->>IMUX6": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.NE2END0->>NN2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.EE4END1->>NN2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.SW2END3->>IMUX47": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.NL1BEG_N3->>IMUX21": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.NW6END1->>NW2BEG1": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.NE2END3->>NW6BEG3": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.NN2END3->>NL1BEG2": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.EL1END2->>ER1BEG3": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.SE6END0->>NN6BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.WR1END1->>WL1BEG_N3": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.LOGIC_OUTS10->>IMUX5": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.SE2END0->>IMUX24": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.WL1END0->>SW2BEG0": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.SL1END3->>IMUX15": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.EE2END1->>IMUX11": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.LOGIC_OUTS18->>WW2BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.EL1END0->>ER1BEG1": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.WW2END_N0_3->>IMUX32": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.NN2END1->>IMUX10": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.NE2END2->>WW4BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.SE2END2->>BYP_ALT2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.FAN_ALT1->>FAN1": { + "src_wire": "FAN_ALT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN1" + }, + "INT_R.SS2END1->>SE6BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.BYP_BOUNCE5->>IMUX5": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.LOGIC_OUTS18->>SE6BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.NN2END2->>NE2BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.SL1END1->>IMUX27": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.SS2END3->>IMUX39": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.SW2END3->>WL1BEG2": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.LOGIC_OUTS15->>IMUX15": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.NW2END1->>IMUX33": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.GFAN0->>FAN_ALT0": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.NN6END3->>NW6BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.LOGIC_OUTS11->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NL1END1->>NN2BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.LOGIC_OUTS6->>NR1BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.SR1END2->>IMUX46": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.SE2END2->>NE6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.LOGIC_OUTS8->>BYP_ALT1": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.LOGIC_OUTS7->>IMUX46": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.LOGIC_OUTS20->>SW6BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.FAN_BOUNCE6->>IMUX25": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.LOGIC_OUTS7->>NW2BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.NN6END2->>WW4BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.LOGIC_OUTS5->>WW2BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.LOGIC_OUTS21->>SE6BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.NN2END2->>IMUX28": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.FAN_BOUNCE5->>FAN_ALT2": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.SE6END0->>NR1BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.NN2END2->>IMUX5": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.NR1END1->>IMUX43": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NW2END3->>SR1BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.LOGIC_OUTS12->>IMUX0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.SE6END3->>NE2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.EE2END2->>NE6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.WW2END2->>WR1BEG_S0": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.ER1END0->>EE2BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.SW6END1->>CTRL1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.NR1END0->>BYP_ALT1": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.EE2END2->>NN6BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.GFAN0->>BYP_ALT5": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.LOGIC_OUTS19->>WR1BEG2": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.WW2END2->>SW6BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.LOGIC_OUTS6->>NL1BEG1": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.SW2END0->>SR1BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.FAN_BOUNCE3->>BYP_ALT3": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.BYP_BOUNCE5->>IMUX39": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.NW2END_S0_0->>IMUX7": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.NL1END1->>IMUX34": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LOGIC_OUTS16->>IMUX45": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.EL1END2->>BYP_ALT2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.LOGIC_OUTS5->>SL1BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.EE2END0->>IMUX16": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.NE6END1->>EL1BEG0": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.SW2END1->>SE2BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.NE6END0->>EE4BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.LOGIC_OUTS23->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.LOGIC_OUTS11->>EL1BEG2": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.NW6END0->>NN6BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX17": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.LOGIC_OUTS7->>IMUX38": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.NL1BEG_N3->>IMUX45": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.ER1END1->>IMUX11": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.SE2END2->>IMUX20": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.BYP_ALT0->>BYP_BOUNCE0": { + "src_wire": "BYP_ALT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE0" + }, + "INT_R.SL1END2->>IMUX5": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.NW2END0->>IMUX16": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.WW2END2->>NW2BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.LOGIC_OUTS8->>WL1BEG_N3": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.NN2END0->>NN6BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.SS2END2->>WW4BEG3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.NW6END1->>EL1BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.WL1END3->>IMUX47": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.LOGIC_OUTS22->>NR1BEG0": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.LOGIC_OUTS18->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.WL1END1->>SW2BEG1": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.EE2END1->>NR1BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.NE6END2->>WW4BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.LOGIC_OUTS13->>SW2BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.BYP_BOUNCE1->>BYP_ALT4": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.EE4END0->>NN6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.SE2END1->>NE2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.FAN_BOUNCE1->>IMUX44": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.NN2END_S2_0->>BYP_ALT7": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.EE2END1->>IMUX26": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.NW2END2->>IMUX12": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.LOGIC_OUTS20->>SS2BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.NW2END0->>NW2BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.NR1END3->>NE2BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.LOGIC_OUTS9->>IMUX18": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.NN2END0->>EE4BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.EL1END2->>IMUX44": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.NL1BEG_N3->>IMUX13": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.GFAN1->>IMUX44": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.NN2END1->>IMUX18": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.SL1END0->>IMUX32": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.GFAN1->>IMUX7": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.FAN_BOUNCE3->>IMUX29": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.SW2END1->>IMUX19": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.SW2END3->>FAN_ALT3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.NN2END0->>IMUX16": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.EE4END3->>SS6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.SS2END1->>SR1BEG2": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.BYP_BOUNCE6->>BYP_ALT7": { + "src_wire": "BYP_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.NL1END1->>IMUX33": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.SE2END0->>SL1BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.LOGIC_OUTS2->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.GFAN1->>IMUX23": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.WW2END2->>NN2BEG3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.ER1END1->>IMUX12": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.EL1END0->>NR1BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.NL1END2->>FAN_ALT6": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.LOGIC_OUTS9->>SW6BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX14": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.WR1END_S1_0->>IMUX31": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.LOGIC_OUTS11->>ER1BEG_S0": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.NN2END0->>NE6BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.WR1END2->>CTRL0": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.NL1END2->>IMUX35": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.WL1END3->>FAN_ALT3": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.SE2END2->>IMUX37": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.EL1END2->>NE2BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.WW4END3->>WW4BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.FAN_BOUNCE3->>IMUX43": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.LOGIC_OUTS11->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.LOGIC_OUTS14->>EE2BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.NL1END2->>EE2BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.EE4END3->>EE2BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.SW2END2->>FAN_ALT5": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.NW6END1->>SW6BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.NN6END1->>WW2BEG0": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.NE2END2->>LVB12": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.SS2END0->>EE4BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.SR1END1->>IMUX11": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.LOGIC_OUTS17->>SE2BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.SE2END1->>IMUX19": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.LOGIC_OUTS21->>IMUX23": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.NL1END2->>NW2BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.LV9->>LH0": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.LOGIC_OUTS18->>NE2BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.WW2END1->>SS2BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.FAN_BOUNCE6->>FAN_ALT0": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.WW2END1->>IMUX3": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.SE2END0->>IMUX16": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.WW2END_N0_3->>IMUX40": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.VCC_WIRE->>IMUX31": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.EE4END2->>SE6BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.EL1END3->>NR1BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.FAN_BOUNCE5->>IMUX3": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.EE2END2->>IMUX45": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.SS2END1->>SW2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.LOGIC_OUTS4->>SS2BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.EE2END2->>IMUX4": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.FAN_BOUNCE3->>IMUX35": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.NW6END2->>CTRL0": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.SL1END2->>IMUX37": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.SS6END1->>NR1BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.LOGIC_OUTS1->>SE6BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.SE2END2->>SE2BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.NW2END3->>IMUX45": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.NN6END2->>NR1BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.EL1END2->>FAN_ALT7": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.EE4END0->>NE2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.LOGIC_OUTS19->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.BYP_BOUNCE2->>IMUX38": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.WR1END2->>IMUX28": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.LOGIC_OUTS17->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX43": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NW2END2->>NN2BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.SE6END2->>EL1BEG1": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.NR1END2->>IMUX20": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.SL1END1->>SW2BEG1": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.NE6END1->>NW6BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.LOGIC_OUTS21->>SW6BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.LOGIC_OUTS0->>EE4BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.EE2END3->>SE2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.SL1END3->>IMUX14": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.EL1END1->>NE2BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.WW2END2->>BYP_ALT3": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.LOGIC_OUTS2->>NL1BEG1": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.WL1END1->>BYP_ALT5": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.BYP_BOUNCE0->>IMUX10": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.EE2END1->>NN6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.EL1END3->>EL1BEG2": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.NE6END0->>NW2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.SS2END0->>NR1BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.NW2END1->>NN2BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.NN2END2->>IMUX36": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.NE2END1->>NR1BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.NW6END2->>NW6BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.NW2END2->>EL1BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.LOGIC_OUTS1->>IMUX27": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.NR1END2->>IMUX44": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.GCLK_B0_EAST->>CLK0": { + "src_wire": "GCLK_B0_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.SW2END1->>BYP_ALT4": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.LVB12->>SS6BEG2": { + "src_wire": "LVB12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.SW2END3->>LVB12": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.SR1END2->>SL1BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.NW2END3->>IMUX22": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.SE2END1->>IMUX43": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NL1END1->>IMUX9": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SW6END0->>NL1BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.SR1END3->>WW2BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.NE2END2->>IMUX4": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.EL1END0->>IMUX0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.NL1END0->>IMUX24": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.LH0<<->>LH12": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.WR1END0->>NW2BEG0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.VCC_WIRE->>IMUX9": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SL1END3->>FAN_ALT1": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.NN6END1->>NL1BEG0": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.LOGIC_OUTS18->>NR1BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.NN2END3->>FAN_ALT3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.ER1END0->>NR1BEG0": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.SS2END0->>SS6BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.LOGIC_OUTS8->>NW2BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.SW2END1->>IMUX3": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS10->>NW2BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.LOGIC_OUTS8->>WR1BEG1": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.NE6END1->>NN2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.NR1END1->>IMUX10": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.FAN_ALT7->>FAN7": { + "src_wire": "FAN_ALT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN7" + }, + "INT_R.LOGIC_OUTS6->>NN2BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.WR1END2->>IMUX20": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.SS2END3->>SE2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.SW2END1->>SL1BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.SE6END1->>NR1BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.SW2END3->>LVB0": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.WR1END1->>IMUX34": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LOGIC_OUTS23->>SW6BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SS2END2->>SW6BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.SS2END3->>EE4BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.SW2END0->>IMUX1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.NW6END3->>SW2BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.NW6END_S0_0->>SW6BEG3": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.LOGIC_OUTS16->>IMUX21": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.ER1END1->>BYP_ALT4": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.LOGIC_OUTS6->>IMUX13": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.SR1END1->>IMUX20": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.BYP_BOUNCE_N3_7->>FAN_ALT6": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.VCC_WIRE->>IMUX18": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.NL1END0->>IMUX32": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.SW2END2->>WW2BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.NW2END_S0_0->>IMUX15": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.VCC_WIRE->>IMUX40": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.LOGIC_OUTS4->>IMUX1": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.LOGIC_OUTS18->>NE6BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.ER1END3->>SL1BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.LOGIC_OUTS11->>NN2BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.WW4END_S0_0->>ER1BEG_S0": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.SW2END1->>IMUX42": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.SS2END0->>EE2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.NL1END1->>WR1BEG2": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.NN2END2->>IMUX35": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.NL1END1->>IMUX25": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.WR1END0->>FAN_ALT0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.WR1END3->>NN2BEG3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.FAN_BOUNCE1->>IMUX34": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.FAN_BOUNCE5->>IMUX43": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.SS2END2->>IMUX45": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.LOGIC_OUTS5->>NN2BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.NN6END0->>LV18": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.LOGIC_OUTS4->>IMUX25": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.NR1END1->>FAN_ALT6": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.FAN_BOUNCE1->>IMUX26": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.LOGIC_OUTS5->>WR1BEG2": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.LOGIC_OUTS0->>NW6BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.GCLK_B1_EAST->>CLK0": { + "src_wire": "GCLK_B1_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.GFAN0->>IMUX41": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.NE2END2->>IMUX36": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.SR1BEG_S0->>IMUX41": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.EL1END0->>IMUX8": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.BYP_ALT6->>BYP_BOUNCE6": { + "src_wire": "BYP_ALT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE6" + }, + "INT_R.WW2END0->>WW2BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.EE4END0->>ER1BEG1": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.NW2END2->>NE2BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.LOGIC_OUTS3->>IMUX39": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.GCLK_B9->>CLK0": { + "src_wire": "GCLK_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.WR1END0->>NL1BEG_N3": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.NW2END3->>EL1BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.SE6END1->>SW6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SS6END2->>SW6BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.NN2END2->>BYP_ALT5": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.EL1END0->>SS2BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.ER1END1->>ER1BEG2": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.NN6END2->>WR1BEG3": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.LOGIC_OUTS23->>ER1BEG2": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX32": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.LOGIC_OUTS22->>SR1BEG1": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.BYP_ALT2->>BYP_BOUNCE2": { + "src_wire": "BYP_ALT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE2" + }, + "INT_R.NE2END1->>IMUX19": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.VCC_WIRE->>IMUX32": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.LOGIC_OUTS18->>SW2BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.EE4END1->>NN6BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.SS6END0->>SW6BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.LOGIC_OUTS21->>NW2BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.FAN_BOUNCE5->>BYP_ALT1": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.SE2END1->>IMUX2": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.SR1END3->>WL1BEG2": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.NW2END1->>NE6BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.NR1END1->>IMUX18": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.NW2END0->>NE6BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.WR1END2->>IMUX12": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.WR1END3->>IMUX30": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.GFAN1->>FAN_ALT1": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.FAN_BOUNCE7->>BYP_ALT4": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.SE2END3->>BYP_ALT6": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.WW4END2->>WL1BEG0": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.LOGIC_OUTS14->>WW2BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.SW2END0->>NL1BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.LOGIC_OUTS3->>NN6BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.NN6END0->>NW6BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.WL1END1->>IMUX12": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX19": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.EE2END3->>IMUX22": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.BYP_BOUNCE1->>IMUX3": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS0->>ER1BEG1": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.EL1END0->>SE2BEG0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.WW2END_N0_3->>NW6BEG0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.LOGIC_OUTS1->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.LOGIC_OUTS15->>NW2BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.LOGIC_OUTS16->>ER1BEG3": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.SW2END2->>FAN_ALT1": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.SR1END3->>SE2BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.NW2END1->>SW6BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.SE6END2->>SW2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.SR1BEG_S0->>SE2BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.ER1END2->>ER1BEG3": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.SL1END0->>FAN_ALT4": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX0": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.SW6END2->>SS2BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.WW2END2->>WL1BEG1": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.GFAN1->>IMUX5": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.NR1END1->>IMUX26": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.SE6END2->>SW6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.WW2END1->>NN2BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.SR1END2->>IMUX30": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.BYP_BOUNCE4->>IMUX28": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.NR1END0->>IMUX1": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.WR1END_S1_0->>BYP_ALT7": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.VCC_WIRE->>IMUX37": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.NW2END2->>IMUX11": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.NE2END1->>NE2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.BYP_BOUNCE4->>CTRL0": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.SS6END0->>SS6BEG0": { + "src_wire": "SS6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX29": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.SS2END1->>SL1BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.FAN_ALT4->>FAN_BOUNCE4": { + "src_wire": "FAN_ALT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE4" + }, + "INT_R.EE4END0->>EE4BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.NL1END1->>EE2BEG1": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.GFAN0->>IMUX10": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.NL1END_S3_0->>BYP_ALT7": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.EE2END0->>IMUX0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.NW2END3->>IMUX30": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.EE4END2->>NR1BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.LOGIC_OUTS15->>IMUX31": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.SE2END3->>NE2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.SW2END3->>IMUX46": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.GFAN1->>IMUX38": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.SL1END1->>IMUX10": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.NW2END_S0_0->>WL1BEG2": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.EE2END1->>IMUX43": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NR1END1->>FAN_ALT2": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.NW6END_S0_0->>SR1BEG_S0": { + "src_wire": "NW6END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.NR1END0->>LV18": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.SS2END0->>IMUX10": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.WL1END2->>FAN_ALT5": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.GFAN0->>BYP_ALT4": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.SR1END2->>IMUX13": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.NN6END3->>NL1BEG2": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.ER1END3->>BYP_ALT6": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NE2END3->>IMUX29": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.SE2END3->>IMUX47": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.SS6END2->>EE4BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.NW2END3->>LH0": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.LOGIC_OUTS13->>EL1BEG0": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.SR1END3->>IMUX23": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.GCLK_B2->>GCLK_B2_WEST": { + "src_wire": "GCLK_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B2_WEST" + }, + "INT_R.LOGIC_OUTS14->>EE4BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.EE2END3->>IMUX38": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.NE2END1->>IMUX41": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.ER1END3->>IMUX30": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.SS2END1->>IMUX42": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.SE2END1->>EE2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.SW2END_N0_3->>NW6BEG0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.LOGIC_OUTS12->>IMUX40": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.SE2END3->>IMUX23": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.WW4END1->>NN6BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.NN2END3->>NW2BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.WW2END3->>ER1BEG_S0": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.EE2END2->>NE2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.NE2END3->>IMUX37": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.NN2END3->>IMUX22": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.SW2END0->>IMUX9": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.VCC_WIRE->>IMUX34": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LOGIC_OUTS3->>WW2BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.SS2END0->>IMUX2": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.FAN_BOUNCE3->>BYP_ALT5": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.SE6END0->>SW2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.SW2END2->>IMUX6": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.LOGIC_OUTS4->>NR1BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.LOGIC_OUTS14->>NN2BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.LOGIC_OUTS11->>EE4BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.EE4END3->>LH0": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.EE4END3->>SW6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.SL1END2->>SR1BEG3": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.ER1END1->>BYP_ALT5": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.EE4END3->>SE6BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.VCC_WIRE->>IMUX42": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.WL1END2->>SW2BEG2": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.WW4END1->>GFAN1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.NW2END3->>BYP_ALT3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.SW2END1->>SE6BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.NR1END3->>FAN_ALT1": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.SE6END1->>ER1BEG2": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.SE2END3->>LVB0": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.WW4END1->>SS6BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.WW4END2->>CTRL0": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.LOGIC_OUTS6->>SE6BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.GFAN0->>IMUX35": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.EE2END2->>IMUX21": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.LOGIC_OUTS11->>EE2BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.NN2END0->>IMUX0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.FAN_ALT7->>FAN_BOUNCE7": { + "src_wire": "FAN_ALT7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE7" + }, + "INT_R.LOGIC_OUTS17->>SS6BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.SL1END0->>IMUX8": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.WL1END1->>IMUX11": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.SW2END3->>IMUX31": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.LOGIC_OUTS7->>SS2BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.LOGIC_OUTS12->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.LOGIC_OUTS13->>SS6BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.LOGIC_OUTS13->>IMUX27": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.ER1END3->>FAN_ALT3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.LOGIC_OUTS15->>SS6BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.VCC_WIRE->>IMUX46": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.FAN_BOUNCE6->>IMUX9": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.LOGIC_OUTS13->>NN6BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG1" + }, + "INT_R.NR1END1->>IMUX19": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.SS2END2->>SL1BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.LOGIC_OUTS15->>WW2BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.ER1END1->>IMUX20": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.LOGIC_OUTS15->>SW6BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.NR1END2->>NE2BEG2": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.NW2END0->>FAN_ALT0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.LOGIC_OUTS7->>IMUX30": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.SW2END0->>IMUX17": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.SE2END1->>SS2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.SS2END1->>NR1BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.SE2END1->>SW2BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.ER1END0->>IMUX9": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SR1END2->>IMUX5": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.LOGIC_OUTS8->>IMUX17": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.NE6END3->>NE6BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.LOGIC_OUTS16->>SS2BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.ER1END2->>BYP_ALT2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.SS2END0->>IMUX9": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.SS6END1->>SS6BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.SE2END1->>BYP_ALT4": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.SE2END1->>IMUX26": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.NE6END0->>WR1BEG1": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.FAN_BOUNCE3->>FAN_ALT7": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.WW4END1->>SS2BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.SE2END3->>IMUX30": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.ER1END3->>IMUX46": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.NN2END2->>IMUX4": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.SS2END3->>SR1BEG_S0": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.SE2END0->>FAN_ALT0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.LOGIC_OUTS10->>BYP_ALT3": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.WW4END2->>WW4BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.NL1END2->>BYP_ALT5": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.LOGIC_OUTS6->>WW4BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.WW4END1->>NL1BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.SE2END2->>IMUX28": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.NN2END2->>WW2BEG1": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.LOGIC_OUTS18->>IMUX9": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.WW2END2->>NL1BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.SW2END0->>IMUX33": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.LOGIC_OUTS4->>EE2BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.NW2END1->>IMUX41": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.BYP_BOUNCE3->>FAN_ALT3": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.LOGIC_OUTS5->>SR1BEG2": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.SS6END1->>SL1BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.LOGIC_OUTS15->>IMUX7": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.LOGIC_OUTS3->>WW4BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.LOGIC_OUTS19->>EE2BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX40": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.SS2END2->>SE2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.WR1END1->>WW2BEG0": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.ER1END2->>NE2BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.ER1END0->>IMUX33": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.WR1END_S1_0->>IMUX47": { + "src_wire": "WR1END_S1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.LOGIC_OUTS22->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.LOGIC_OUTS15->>SE6BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.EE2END1->>EE4BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.SW2END1->>IMUX12": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.SS2END1->>EE4BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.SR1END2->>WL1BEG1": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.SR1END3->>IMUX7": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.LH6->>NE6BEG1": { + "src_wire": "LH6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.LOGIC_OUTS21->>EE4BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.LOGIC_OUTS7->>SE6BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.NN2END0->>NW2BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.BYP_BOUNCE1->>IMUX13": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.SL1END1->>IMUX11": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.LOGIC_OUTS1->>IMUX11": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.WR1END2->>NN2BEG2": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.LOGIC_OUTS2->>SL1BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.SE2END3->>WL1BEG2": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.WW2END0->>IMUX18": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.GCLK_B8->>CLK1": { + "src_wire": "GCLK_B8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.LOGIC_OUTS10->>SE6BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.SW2END0->>SE2BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.NE6END3->>WW4BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.NW2END3->>SS6BEG2": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.LOGIC_OUTS17->>NE6BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX17": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.NN2END1->>WW2BEG0": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.NW2END1->>FAN_ALT4": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.BYP_BOUNCE_N3_7->>BYP_ALT0": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.LOGIC_OUTS3->>NR1BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.VCC_WIRE->>IMUX3": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.ER1END1->>EE2BEG1": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.BYP_ALT6->>BYP6": { + "src_wire": "BYP_ALT6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP6" + }, + "INT_R.NR1END3->>LVB12": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.NW2END2->>WW2BEG1": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.LOGIC_OUTS23->>SE2BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.LOGIC_OUTS6->>SL1BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.SE2END3->>ER1BEG_S0": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.WW2END2->>IMUX30": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.LOGIC_OUTS16->>SS6BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.EL1END0->>FAN_ALT0": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.GFAN1->>IMUX45": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.EL1END0->>IMUX16": { + "src_wire": "EL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.WW2END1->>IMUX35": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.LOGIC_OUTS18->>SS6BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.NW6END3->>WW4BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.SE2END0->>IMUX33": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.NN6END3->>SE6BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.SS6END1->>SW6BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.ER1END2->>BYP_ALT3": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.BYP_ALT5->>BYP_BOUNCE5": { + "src_wire": "BYP_ALT5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE5" + }, + "INT_R.ER1END2->>SE2BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.SL1END2->>WL1BEG1": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.NE2END3->>BYP_ALT6": { + "src_wire": "NE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.NN6END2->>NE6BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.SL1END1->>BYP_ALT5": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.NN6END3->>NE2BEG3": { + "src_wire": "NN6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG3" + }, + "INT_R.WW2END2->>SS2BEG2": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.EL1END2->>SL1BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.SE6END1->>SE6BEG1": { + "src_wire": "SE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.WL1END1->>IMUX4": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.NN2END2->>NE6BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.WR1END1->>IMUX10": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.GCLK_B6->>CLK0": { + "src_wire": "GCLK_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.WL1END_N1_3->>NN2BEG0": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.SS2END2->>EE2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.SW2END1->>SR1BEG2": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.NL1BEG_N3->>NL1BEG2": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.NL1BEG_N3->>IMUX14": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.SW6END2->>EE4BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.SW2END1->>SS6BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.WR1END3->>NL1BEG2": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.NW2END3->>NW2BEG3": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.GFAN0->>IMUX19": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.SR1END1->>IMUX36": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.WR1END2->>IMUX27": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.WW2END1->>NL1BEG1": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG1" + }, + "INT_R.EE4END3->>EE4BEG3": { + "src_wire": "EE4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.LOGIC_OUTS8->>SS2BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.LOGIC_OUTS9->>SE6BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.NE6END0->>SE6BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.WL1END2->>IMUX45": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.LOGIC_OUTS5->>SW2BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.EE4END0->>SS2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.FAN_BOUNCE_S3_6->>IMUX47": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.WL1END1->>IMUX26": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.NN2END0->>IMUX24": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX41": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.NN2END1->>SR1BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.LOGIC_OUTS21->>NE6BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.LOGIC_OUTS6->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.LOGIC_OUTS11->>NR1BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.SS2END3->>SE6BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.SW6END2->>SS6BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.NW2END2->>IMUX19": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.WR1END2->>CTRL1": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.LOGIC_OUTS22->>EL1BEG_N3": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.SS2END2->>IMUX28": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.WW2END1->>IMUX4": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.ER1END0->>IMUX25": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.LOGIC_OUTS11->>NE6BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG3" + }, + "INT_R.LOGIC_OUTS15->>WW4BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.SS2END2->>IMUX5": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.LOGIC_OUTS8->>NL1BEG_N3": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.EE2END3->>IMUX39": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.FAN_BOUNCE3->>IMUX27": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.SE6END0->>SL1BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.LOGIC_OUTS20->>NW2BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.LOGIC_OUTS15->>IMUX23": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.WR1END0->>IMUX40": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.EE2END0->>NN2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.LOGIC_OUTS16->>NW2BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.NN6END2->>EE4BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.SE6END3->>LVB0": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.WW2END2->>IMUX21": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.SE6END2->>NE2BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.GFAN1->>BYP_ALT2": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.LOGIC_OUTS7->>SE2BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.NL1BEG_N3->>WR1BEG_S0": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.EL1END1->>IMUX11": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.SL1END2->>IMUX45": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.GCLK_B3_EAST->>GFAN0": { + "src_wire": "GCLK_B3_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.LOGIC_OUTS1->>SL1BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.SW6END2->>SL1BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.SS6END1->>NW6BEG2": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.LOGIC_OUTS17->>NN2BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.LOGIC_OUTS0->>NE6BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.WL1END2->>IMUX37": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.EE2END0->>IMUX24": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.EE4END2->>SL1BEG2": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.NR1END0->>EL1BEG_N3": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.NW6END2->>NW2BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.LOGIC_OUTS10->>SW2BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.NL1BEG_N3->>IMUX22": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.WR1END2->>IMUX13": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.GCLK_B5_EAST->>GFAN0": { + "src_wire": "GCLK_B5_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.WR1END3->>SW2BEG2": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.LV0<<->>LH12": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.SE2END0->>IMUX1": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.VCC_WIRE->>IMUX39": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.SR1END1->>BYP_ALT5": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.NL1END2->>IMUX36": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.GFAN1->>CTRL1": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.NE2END0->>SL1BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG0" + }, + "INT_R.EE2END0->>NN6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.LOGIC_OUTS2->>BYP_ALT2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.NN2END0->>EL1BEG_N3": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.SS2END3->>IMUX31": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.FAN_BOUNCE7->>FAN_ALT6": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.LOGIC_OUTS14->>IMUX4": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.GFAN0->>IMUX40": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.LOGIC_OUTS23->>EE4BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.SL1END2->>IMUX36": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.GFAN1->>IMUX13": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.LOGIC_OUTS15->>EE4BEG3": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.LOGIC_OUTS1->>SS6BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.NR1END2->>CTRL0": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.SE6END3->>NN6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.EL1END2->>IMUX13": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.LOGIC_OUTS1->>IMUX35": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.LOGIC_OUTS7->>BYP_ALT6": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.WW2END1->>WL1BEG0": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.FAN_BOUNCE5->>IMUX41": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.SS6END1->>SR1BEG2": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.SW6END2->>SW6BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.NW6END3->>SS6BEG2": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.LOGIC_OUTS5->>SS6BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.LOGIC_OUTS4->>NN2BEG0": { + "src_wire": "LOGIC_OUTS4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.NW2END3->>IMUX37": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.SW6END3->>SE2BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.SR1END1->>WL1BEG0": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.EL1END2->>BYP_ALT5": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.GFAN1->>IMUX12": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.LOGIC_OUTS1->>SS2BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.LOGIC_OUTS22->>IMUX32": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.NE2END1->>IMUX11": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.LOGIC_OUTS5->>NW2BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.NW2END_S0_0->>FAN_ALT3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.LOGIC_OUTS23->>WR1BEG2": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.VCC_WIRE->>BYP_ALT5": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.LOGIC_OUTS5->>NW6BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.FAN_BOUNCE6->>FAN_ALT2": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.EE4END1->>NR1BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.WR1END1->>IMUX19": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.NL1END0->>EL1BEG_N3": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.WW2END3->>IMUX7": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.SW2END2->>IMUX45": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.LOGIC_OUTS2->>EE2BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.LOGIC_OUTS21->>NL1BEG2": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.NE6END1->>NW2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.NW2END2->>NW6BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.LOGIC_OUTS12->>IMUX8": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.EE4END0->>NE6BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG0" + }, + "INT_R.WR1END3->>IMUX45": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX45" + }, + "INT_R.SR1BEG_S0->>IMUX10": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.NR1END1->>IMUX35": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.BYP_BOUNCE_N3_3->>IMUX41": { + "src_wire": "BYP_BOUNCE_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.LOGIC_OUTS8->>SW6BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.SR1BEG_S0->>FAN_ALT2": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.BYP_BOUNCE1->>IMUX21": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.WL1END0->>WR1BEG2": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.LOGIC_OUTS20->>NN2BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.VCC_WIRE->>BYP_ALT6": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.SW2END0->>WW4BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.SW6END2->>WW4BEG3": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG3" + }, + "INT_R.BYP_BOUNCE0->>IMUX42": { + "src_wire": "BYP_BOUNCE0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.SS2END3->>FAN_ALT3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.EL1END2->>SS2BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.LOGIC_OUTS18->>SE2BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.WR1END0->>IMUX16": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.LOGIC_OUTS3->>EE4BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.NN2END1->>NE2BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.BYP_ALT3->>BYP3": { + "src_wire": "BYP_ALT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP3" + }, + "INT_R.NW2END1->>NL1BEG0": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.NL1END0->>NN2BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.WR1END3->>BYP_ALT3": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.NE2END0->>SE6BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.SW2END3->>IMUX23": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.FAN_BOUNCE1->>IMUX36": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.NR1END0->>NN2BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.LOGIC_OUTS20->>FAN_ALT7": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.WL1END3->>SW2BEG3": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.EE2END0->>SS2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.LOGIC_OUTS5->>SW6BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SR1END3->>SR1BEG_S0": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG_S0" + }, + "INT_R.NN6END1->>WW4BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.NW2END2->>WW4BEG2": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG2" + }, + "INT_R.VCC_WIRE->>FAN_ALT1": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.ER1END3->>IMUX23": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX15": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.FAN_BOUNCE5->>IMUX35": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.SE2END2->>NN6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.NL1END2->>NR1BEG2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.WL1END0->>FAN_ALT4": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.SW2END0->>NW2BEG1": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.LOGIC_OUTS19->>WW4BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.WW4END0->>NW2BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.ER1END1->>EL1BEG0": { + "src_wire": "ER1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.NN2END1->>IMUX3": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS17->>SE6BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.SW6END0->>SS2BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.EL1END1->>BYP_ALT4": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.WW4END_S0_0->>SS2BEG3": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.WR1END3->>IMUX22": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.NL1END_S3_0->>IMUX39": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.SW2END3->>SW2BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.SW2END1->>IMUX26": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.EE2END3->>IMUX31": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.SS2END2->>WW2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.NE2END1->>BYP_ALT1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.WL1END0->>IMUX33": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.NE2END1->>NN2BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.SW2END3->>IMUX7": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.NL1BEG_N3->>FAN_ALT5": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.NE2END0->>IMUX0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.LOGIC_OUTS21->>IMUX47": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.SR1END2->>CTRL1": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.SS2END3->>IMUX15": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.WW4END1->>WW4BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.NW6END1->>SS6BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.NW2END3->>FAN_ALT5": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.ER1END2->>EE2BEG2": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.SS2END1->>NW6BEG2": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.SW6END3->>SS6BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.BYP_BOUNCE_N3_7->>FAN_ALT4": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.SE2END0->>SW2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.EL1END3->>IMUX38": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.LOGIC_OUTS15->>IMUX39": { + "src_wire": "LOGIC_OUTS15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.GCLK_B6->>CLK1": { + "src_wire": "GCLK_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.WW2END1->>NN6BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.LOGIC_OUTS18->>ER1BEG1": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.LOGIC_OUTS20->>IMUX28": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.SR1BEG_S0->>WL1BEG_N3": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.SR1END2->>CTRL0": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.SE2END3->>FAN_ALT1": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.LOGIC_OUTS20->>WR1BEG3": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.NN2END3->>IMUX37": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.LOGIC_OUTS14->>SS2BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG2" + }, + "INT_R.SS2END1->>IMUX12": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.GFAN0->>IMUX24": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.GCLK_B10->>CLK0": { + "src_wire": "GCLK_B10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK0" + }, + "INT_R.SS6END3->>LH0": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.SL1END2->>WW2BEG2": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.EL1END1->>IMUX2": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.LOGIC_OUTS10->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.SW2END_N0_3->>IMUX8": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.GFAN1->>IMUX6": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.WW2END3->>WL1BEG2": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.NR1END2->>BYP_ALT3": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT3" + }, + "INT_R.SW2END_N0_3->>NW2BEG0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.EL1END3->>FAN_ALT1": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.SW6END0->>WW4BEG1": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG1" + }, + "INT_R.NW6END1->>WW2BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG0" + }, + "INT_R.WL1END1->>IMUX43": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.GCLK_B9->>GFAN0": { + "src_wire": "GCLK_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN0" + }, + "INT_R.LOGIC_OUTS9->>NW2BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.LOGIC_OUTS1->>EE2BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.WR1END1->>IMUX18": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.BYP_ALT3->>BYP_BOUNCE3": { + "src_wire": "BYP_ALT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_BOUNCE3" + }, + "INT_R.LOGIC_OUTS18->>IMUX25": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.EE2END3->>IMUX30": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.NR1END0->>IMUX16": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.WW4END3->>WL1BEG1": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.WR1END1->>SW2BEG0": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.SW6END0->>SW2BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.NE6END1->>SE2BEG1": { + "src_wire": "NE6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.LOGIC_OUTS2->>NE2BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.GFAN0->>IMUX42": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.FAN_BOUNCE7->>IMUX34": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.LOGIC_OUTS2->>SR1BEG3": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.EE4END1->>SL1BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.NW2END0->>NN2BEG0": { + "src_wire": "NW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.NW6END2->>CTRL1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.LOGIC_OUTS10->>NW6BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG2" + }, + "INT_R.ER1END2->>IMUX5": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.LOGIC_OUTS21->>NW6BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.LOGIC_OUTS11->>FAN_ALT1": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.BYP_BOUNCE5->>IMUX29": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.SL1END1->>IMUX35": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX35" + }, + "INT_R.WL1END0->>NN2BEG1": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.LOGIC_OUTS20->>NN6BEG2": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.VCC_WIRE->>IMUX4": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.SE2END3->>IMUX22": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX22" + }, + "INT_R.WW4END3->>NW6BEG3": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.WL1END0->>NL1BEG0": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.LOGIC_OUTS20->>IMUX44": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.LOGIC_OUTS5->>EL1BEG0": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.LOGIC_OUTS17->>IMUX14": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.SS2END1->>SE2BEG1": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.FAN_BOUNCE4->>FAN_ALT0": { + "src_wire": "FAN_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.WL1END2->>IMUX28": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.GFAN0->>IMUX16": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.WR1END0->>IMUX9": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX9" + }, + "INT_R.NW2END2->>WR1BEG3": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.WL1END2->>FAN_ALT1": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.WW2END1->>IMUX11": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.NW6END0->>LV18": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV18" + }, + "INT_R.SW2END2->>IMUX36": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.NN2END1->>IMUX11": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.WW2END3->>SW2BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG3" + }, + "INT_R.NE6END2->>SE2BEG2": { + "src_wire": "NE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.LOGIC_OUTS21->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX30": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.LH12->>LVB12": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB12" + }, + "INT_R.EE4END0->>EL1BEG_N3": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.LOGIC_OUTS12->>IMUX16": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.SE2END3->>EE4BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.WL1END2->>SR1BEG3": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.LOGIC_OUTS10->>ER1BEG3": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.GFAN0->>IMUX11": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.NE2END0->>NE2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.BYP_BOUNCE_N3_2->>IMUX16": { + "src_wire": "BYP_BOUNCE_N3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.SL1END3->>ER1BEG_S0": { + "src_wire": "SL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.SW2END3->>SS6BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.LOGIC_OUTS1->>NN2BEG1": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.BYP_BOUNCE4->>IMUX14": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.EE4END1->>NE2BEG1": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.WW2END0->>NE6BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.WW2END0->>NW2BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.EL1END3->>EE2BEG3": { + "src_wire": "EL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.LOGIC_OUTS18->>NN2BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.LOGIC_OUTS12->>WR1BEG1": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.NN2END_S2_0->>IMUX31": { + "src_wire": "NN2END_S2_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.ER1END0->>FAN_ALT2": { + "src_wire": "ER1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.LOGIC_OUTS0->>NW2BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.VCC_WIRE->>IMUX13": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.LOGIC_OUTS19->>FAN_ALT2": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.SW6END0->>SW6BEG0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.WL1END2->>BYP_ALT2": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.LOGIC_OUTS10->>SL1BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG2" + }, + "INT_R.FAN_BOUNCE_S3_2->>IMUX14": { + "src_wire": "FAN_BOUNCE_S3_2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.FAN_BOUNCE5->>IMUX1": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.LOGIC_OUTS2->>WR1BEG3": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.LH12->>NW6BEG0": { + "src_wire": "LH12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.WR1END3->>IMUX46": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX46" + }, + "INT_R.SR1END1->>SL1BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.LOGIC_OUTS12->>NW6BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.FAN_ALT0->>FAN_BOUNCE0": { + "src_wire": "FAN_ALT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_BOUNCE0" + }, + "INT_R.FAN_BOUNCE7->>IMUX10": { + "src_wire": "FAN_BOUNCE7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.LOGIC_OUTS3->>SL1BEG3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.SR1END3->>LH12": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.NL1END2->>BYP_ALT2": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.SS2END2->>IMUX6": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.NW2END2->>WL1BEG0": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.NW6END2->>NN6BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.VCC_WIRE->>IMUX47": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.VCC_WIRE->>IMUX1": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX1" + }, + "INT_R.LOGIC_OUTS8->>SS6BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.SL1END0->>BYP_ALT1": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.SW2END1->>IMUX11": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.SS2END0->>SE2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.LOGIC_OUTS21->>IMUX15": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.LOGIC_OUTS22->>IMUX40": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX40" + }, + "INT_R.WR1END0->>FAN_ALT4": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.NL1END_S3_0->>IMUX23": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.SW2END1->>IMUX27": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.SW6END3->>SL1BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.SR1END2->>ER1BEG3": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.LOGIC_OUTS16->>NE6BEG2": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.GCLK_B0_EAST->>GFAN1": { + "src_wire": "GCLK_B0_EAST", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GFAN1" + }, + "INT_R.WL1END2->>IMUX29": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.NL1END0->>NW2BEG0": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.NE2END1->>SE6BEG1": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.LOGIC_OUTS1->>NL1BEG0": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG0" + }, + "INT_R.LOGIC_OUTS3->>WR1BEG_S0": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.SW2END0->>IMUX25": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.LOGIC_OUTS12->>NW2BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.EE2END1->>IMUX27": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.GFAN0->>IMUX27": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.NE2END0->>EE2BEG0": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.WR1END2->>WL1BEG0": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.SW2END2->>LVB0": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.FAN_BOUNCE_S3_0->>FAN_ALT3": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.BYP_BOUNCE4->>CTRL1": { + "src_wire": "BYP_BOUNCE4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.NW2END2->>IMUX36": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.WL1END2->>IMUX14": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.LOGIC_OUTS6->>NW2BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.NE2END2->>IMUX13": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.LV18->>SS6BEG3": { + "src_wire": "LV18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.LH0->>NN6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.WW2END1->>IMUX36": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.NL1BEG_N3->>IMUX38": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.SS2END0->>FAN_ALT2": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.NW6END3->>NW6BEG3": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.NE2END0->>WR1BEG1": { + "src_wire": "NE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.NN2END1->>EL1BEG0": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.SS6END3->>SS2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.WW4END0->>LV0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV0" + }, + "INT_R.NN6END2->>EE2BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG2" + }, + "INT_R.SE6END3->>SW6BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.GFAN1->>IMUX37": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.WL1END1->>NN2BEG2": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG2" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX47": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.LOGIC_OUTS17->>NR1BEG3": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG3" + }, + "INT_R.SR1END_N3_3->>IMUX0": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.LOGIC_OUTS13->>FAN_ALT6": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.NR1END0->>IMUX17": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.SR1END_N3_3->>FAN_ALT0": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.SR1END2->>IMUX6": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.NL1BEG_N3->>EL1BEG2": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.SL1END2->>FAN_ALT5": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.NL1END_S3_0->>IMUX47": { + "src_wire": "NL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX47" + }, + "INT_R.BYP_BOUNCE5->>IMUX31": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.SE6END2->>WL1BEG1": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG1" + }, + "INT_R.SE2END3->>EE2BEG3": { + "src_wire": "SE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.BYP_BOUNCE1->>FAN_ALT5": { + "src_wire": "BYP_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.WR1END0->>NN2BEG0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.NE2END2->>NE2BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.NE2END2->>IMUX20": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.NR1END3->>IMUX7": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.EE2END2->>FAN_ALT5": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.NN6END2->>NW2BEG2": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG2" + }, + "INT_R.EE2END0->>SW6BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.WW4END2->>NE6BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.WR1END2->>WW2BEG1": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.LOGIC_OUTS7->>IMUX14": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.WW2END3->>BYP_ALT7": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.SW6END1->>WW2BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.LOGIC_OUTS12->>IMUX24": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.BYP_ALT2->>BYP2": { + "src_wire": "BYP_ALT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP2" + }, + "INT_R.SR1END3->>IMUX15": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.WR1END3->>LVB0": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LVB0" + }, + "INT_R.LOGIC_OUTS8->>IMUX41": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.WW4END3->>SW6BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.SR1END3->>SL1BEG3": { + "src_wire": "SR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.LOGIC_OUTS19->>IMUX26": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.SR1BEG_S0->>SW2BEG0": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.WW4END1->>NN2BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.NE6END3->>NW6BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.FAN_BOUNCE_S3_4->>BYP_ALT7": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.EL1END_S3_0->>IMUX39": { + "src_wire": "EL1END_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.LOGIC_OUTS7->>SL1BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.SW6END3->>WL1BEG2": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + }, + "INT_R.SS2END0->>BYP_ALT0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.WR1END3->>IMUX7": { + "src_wire": "WR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX7" + }, + "INT_R.NW6END2->>SR1BEG2": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG2" + }, + "INT_R.EE4END1->>WR1BEG2": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.LOGIC_OUTS7->>SS6BEG3": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG3" + }, + "INT_R.EL1END1->>BYP_ALT1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT1" + }, + "INT_R.SW2END0->>FAN_ALT4": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT4" + }, + "INT_R.FAN_BOUNCE1->>BYP_ALT4": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.EE4END2->>EL1BEG1": { + "src_wire": "EE4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.SS2END3->>BYP_ALT6": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.LOGIC_OUTS1->>WR1BEG2": { + "src_wire": "LOGIC_OUTS1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.LV9->>LH12": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.LOGIC_OUTS22->>ER1BEG1": { + "src_wire": "LOGIC_OUTS22", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.NE2END1->>FAN_ALT2": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.NW6END0->>NE2BEG0": { + "src_wire": "NW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.NW6END1->>SW2BEG0": { + "src_wire": "NW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.SS6END3->>WW2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.NN2END1->>NW2BEG1": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.ER1END3->>IMUX31": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.WW2END2->>IMUX5": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.NR1END0->>IMUX24": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX24" + }, + "INT_R.GFAN1->>IMUX14": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.NN6END0->>NW2BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG0" + }, + "INT_R.SR1BEG_S0->>SR1BEG1": { + "src_wire": "SR1BEG_S0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.WL1END0->>IMUX10": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.NR1END0->>FAN_ALT0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.EE2END2->>SE2BEG2": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.SL1END1->>IMUX3": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS7->>EL1BEG2": { + "src_wire": "LOGIC_OUTS7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG2" + }, + "INT_R.GFAN1->>FAN_ALT7": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.LOGIC_OUTS14->>SR1BEG3": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.SE6END0->>EL1BEG_N3": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG_N3" + }, + "INT_R.NN2END2->>EL1BEG1": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.LH0->>SW6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.NN6END1->>EE4BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.SS2END2->>IMUX44": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.NW6END3->>WR1BEG_S0": { + "src_wire": "NW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.LV9->>NW6BEG1": { + "src_wire": "LV9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG1" + }, + "INT_R.LOGIC_OUTS11->>IMUX38": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX38" + }, + "INT_R.FAN_BOUNCE5->>IMUX17": { + "src_wire": "FAN_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.NL1END1->>IMUX26": { + "src_wire": "NL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.LOGIC_OUTS6->>NE6BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.EE2END2->>FAN_ALT7": { + "src_wire": "EE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.LOGIC_OUTS12->>NR1BEG0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.LOGIC_OUTS6->>IMUX29": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX4": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.NW2END1->>NE2BEG1": { + "src_wire": "NW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG1" + }, + "INT_R.LOGIC_OUTS18->>WW4BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.EL1END1->>EL1BEG0": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG0" + }, + "INT_R.LOGIC_OUTS12->>IMUX32": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.EL1END2->>IMUX28": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.NR1END2->>CTRL1": { + "src_wire": "NR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL1" + }, + "INT_R.EE2END3->>ER1BEG_S0": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG_S0" + }, + "INT_R.GCLK_B1->>GCLK_B1_WEST": { + "src_wire": "GCLK_B1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "GCLK_B1_WEST" + }, + "INT_R.WL1END2->>NN2BEG3": { + "src_wire": "WL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.LOGIC_OUTS6->>SW6BEG2": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG2" + }, + "INT_R.BYP_BOUNCE_N3_6->>IMUX18": { + "src_wire": "BYP_BOUNCE_N3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX18" + }, + "INT_R.SS2END3->>IMUX30": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.WW2END3->>WW2BEG3": { + "src_wire": "WW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.NE2END2->>IMUX44": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.LOGIC_OUTS19->>EE4BEG1": { + "src_wire": "LOGIC_OUTS19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.WR1END0->>BYP_ALT0": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.EL1END1->>EE2BEG1": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG1" + }, + "INT_R.SS2END3->>SS2BEG3": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.SR1END2->>IMUX14": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX14" + }, + "INT_R.LOGIC_OUTS9->>BYP_ALT4": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.LOGIC_OUTS23->>SL1BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG1" + }, + "INT_R.NE6END3->>WR1BEG_S0": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG_S0" + }, + "INT_R.SS2END2->>ER1BEG3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG3" + }, + "INT_R.WW4END3->>SW2BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.LOGIC_OUTS9->>WL1BEG0": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG0" + }, + "INT_R.SS2END2->>IMUX29": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.WW4END0->>NN2BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.LOGIC_OUTS23->>IMUX11": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX11" + }, + "INT_R.WW4END0->>NW6BEG0": { + "src_wire": "WW4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.SW2END0->>SS6BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG0" + }, + "INT_R.NN6END1->>SE6BEG1": { + "src_wire": "NN6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG1" + }, + "INT_R.LOGIC_OUTS12->>FAN_ALT0": { + "src_wire": "LOGIC_OUTS12", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.WL1END1->>IMUX27": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.SL1END0->>IMUX0": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.LOGIC_OUTS2->>NN6BEG2": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.SW6END2->>SE2BEG2": { + "src_wire": "SW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.LOGIC_OUTS5->>EE4BEG1": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG1" + }, + "INT_R.NN2END0->>EE2BEG0": { + "src_wire": "NN2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG0" + }, + "INT_R.SE6END3->>SS2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.SS2END2->>SR1BEG3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.SW2END0->>IMUX41": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.NE2END2->>NE6BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG2" + }, + "INT_R.LOGIC_OUTS23->>NW2BEG1": { + "src_wire": "LOGIC_OUTS23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.ER1END3->>SE2BEG3": { + "src_wire": "ER1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.SS2END2->>NW6BEG3": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG3" + }, + "INT_R.NL1BEG_N3->>IMUX6": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX6" + }, + "INT_R.WL1END0->>IMUX17": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.SW2END0->>SW6BEG0": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.BYP_BOUNCE_N3_7->>IMUX3": { + "src_wire": "BYP_BOUNCE_N3_7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.WR1END0->>IMUX8": { + "src_wire": "WR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX8" + }, + "INT_R.LOGIC_OUTS13->>WR1BEG2": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.LOGIC_OUTS17->>NL1BEG2": { + "src_wire": "LOGIC_OUTS17", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.LOGIC_OUTS14->>IMUX36": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX36" + }, + "INT_R.NN6END0->>WR1BEG1": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.WW2END2->>IMUX29": { + "src_wire": "WW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX29" + }, + "INT_R.NW2END_S0_0->>SW6BEG3": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG3" + }, + "INT_R.NN6END0->>NL1BEG_N3": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG_N3" + }, + "INT_R.SL1END2->>IMUX20": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.WR1END1->>IMUX3": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.VCC_WIRE->>IMUX27": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX27" + }, + "INT_R.SW6END0->>LV0": { + "src_wire": "SW6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LV0" + }, + "INT_R.LOGIC_OUTS6->>SR1BEG3": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG3" + }, + "INT_R.LOGIC_OUTS13->>IMUX3": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.LOGIC_OUTS13->>SW6BEG1": { + "src_wire": "LOGIC_OUTS13", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.VCC_WIRE->>BYP_ALT7": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.SR1END_N3_3->>IMUX32": { + "src_wire": "SR1END_N3_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.LOGIC_OUTS2->>IMUX20": { + "src_wire": "LOGIC_OUTS2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.EE2END1->>IMUX42": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX42" + }, + "INT_R.SW2END1->>WW2BEG1": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.VCC_WIRE->>FAN_ALT0": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.SS2END0->>IMUX33": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.GFAN1->>IMUX4": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX4" + }, + "INT_R.WW4END1->>ER1BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG1" + }, + "INT_R.WW4END1->>SR1BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.SE6END0->>NE2BEG0": { + "src_wire": "SE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.LOGIC_OUTS9->>NR1BEG1": { + "src_wire": "LOGIC_OUTS9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG1" + }, + "INT_R.WR1END1->>IMUX25": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.SW2END2->>EE4BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG2" + }, + "INT_R.SW2END_N0_3->>FAN_ALT0": { + "src_wire": "SW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT0" + }, + "INT_R.WL1END3->>IMUX15": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX15" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX39": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.LOGIC_OUTS8->>EE4BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG0" + }, + "INT_R.SS2END1->>IMUX3": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.FAN_BOUNCE1->>FAN_ALT5": { + "src_wire": "FAN_BOUNCE1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.GCLK_B7->>CLK1": { + "src_wire": "GCLK_B7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CLK1" + }, + "INT_R.NN6END0->>SE6BEG0": { + "src_wire": "NN6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.BYP_BOUNCE5->>BYP_ALT2": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT2" + }, + "INT_R.FAN_BOUNCE_S3_4->>IMUX23": { + "src_wire": "FAN_BOUNCE_S3_4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.EE4END0->>NN2BEG0": { + "src_wire": "EE4END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG0" + }, + "INT_R.LOGIC_OUTS14->>SE2BEG2": { + "src_wire": "LOGIC_OUTS14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.VCC_WIRE->>IMUX5": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.SE6END3->>EE2BEG3": { + "src_wire": "SE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.SW2END1->>IMUX20": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX20" + }, + "INT_R.NW2END_S0_0->>BYP_ALT7": { + "src_wire": "NW2END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.NL1END0->>WR1BEG1": { + "src_wire": "NL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.SW6END3->>EE4BEG3": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE4BEG3" + }, + "INT_R.EL1END1->>IMUX3": { + "src_wire": "EL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX3" + }, + "INT_R.WR1END2->>BYP_ALT5": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.GFAN0->>IMUX32": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX32" + }, + "INT_R.SW2END3->>SE2BEG3": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG3" + }, + "INT_R.LOGIC_OUTS8->>SW2BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.NE6END0->>WW4BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW4BEG0" + }, + "INT_R.SS2END1->>BYP_ALT5": { + "src_wire": "SS2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT5" + }, + "INT_R.NR1END0->>IMUX41": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.LOGIC_OUTS6->>WR1BEG3": { + "src_wire": "LOGIC_OUTS6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.SS2END3->>IMUX23": { + "src_wire": "SS2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX23" + }, + "INT_R.SS2END0->>IMUX25": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.SW2END3->>IMUX30": { + "src_wire": "SW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX30" + }, + "INT_R.SS6END3->>EE2BEG3": { + "src_wire": "SS6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EE2BEG3" + }, + "INT_R.BYP_BOUNCE3->>IMUX31": { + "src_wire": "BYP_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX31" + }, + "INT_R.NE2END2->>NN6BEG2": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG2" + }, + "INT_R.NL1END2->>FAN_ALT7": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT7" + }, + "INT_R.SE2END1->>SS6BEG1": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG1" + }, + "INT_R.NR1END3->>NW2BEG3": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG3" + }, + "INT_R.WW4END1->>SW6BEG0": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG0" + }, + "INT_R.WL1END3->>BYP_ALT7": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.WW2END1->>ER1BEG2": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.EE2END0->>SE2BEG0": { + "src_wire": "EE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.SW6END1->>SW2BEG1": { + "src_wire": "SW6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.SR1END1->>SW2BEG1": { + "src_wire": "SR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG1" + }, + "INT_R.EE2END1->>IMUX2": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.NN2END1->>IMUX26": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX26" + }, + "INT_R.NR1END1->>NN2BEG1": { + "src_wire": "NR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.NE2END1->>WR1BEG2": { + "src_wire": "NE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG2" + }, + "INT_R.NR1END3->>IMUX39": { + "src_wire": "NR1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.LOGIC_OUTS21->>WW2BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG3" + }, + "INT_R.SR1END2->>SW2BEG2": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.FAN_BOUNCE3->>IMUX19": { + "src_wire": "FAN_BOUNCE3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.WW2END0->>SW2BEG0": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG0" + }, + "INT_R.SR1END2->>BYP_ALT6": { + "src_wire": "SR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT6" + }, + "INT_R.SL1END2->>IMUX44": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX44" + }, + "INT_R.WR1END1->>NW2BEG1": { + "src_wire": "WR1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW2BEG1" + }, + "INT_R.NE6END0->>NE2BEG0": { + "src_wire": "NE6END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG0" + }, + "INT_R.SL1END1->>FAN_ALT6": { + "src_wire": "SL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT6" + }, + "INT_R.SS6END1->>SE2BEG1": { + "src_wire": "SS6END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG1" + }, + "INT_R.WW4END3->>NL1BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NL1BEG2" + }, + "INT_R.SW2END1->>IMUX34": { + "src_wire": "SW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.NW2END3->>IMUX13": { + "src_wire": "NW2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX13" + }, + "INT_R.WL1END_N1_3->>WR1BEG1": { + "src_wire": "WL1END_N1_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG1" + }, + "INT_R.WW2END_N0_3->>IMUX0": { + "src_wire": "WW2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.LOGIC_OUTS18->>NW6BEG0": { + "src_wire": "LOGIC_OUTS18", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.BYP_BOUNCE2->>FAN_ALT1": { + "src_wire": "BYP_BOUNCE2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT1" + }, + "INT_R.EL1END2->>NR1BEG2": { + "src_wire": "EL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG2" + }, + "INT_R.SE6END2->>SS6BEG2": { + "src_wire": "SE6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS6BEG2" + }, + "INT_R.LOGIC_OUTS3->>FAN_ALT3": { + "src_wire": "LOGIC_OUTS3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT3" + }, + "INT_R.WL1END1->>BYP_ALT4": { + "src_wire": "WL1END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT4" + }, + "INT_R.FAN_BOUNCE_S3_0->>IMUX12": { + "src_wire": "FAN_BOUNCE_S3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX12" + }, + "INT_R.SS2END2->>SW2BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW2BEG2" + }, + "INT_R.SE2END1->>ER1BEG2": { + "src_wire": "SE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.GFAN0->>IMUX0": { + "src_wire": "GFAN0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX0" + }, + "INT_R.WW4END1->>NE6BEG1": { + "src_wire": "WW4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE6BEG1" + }, + "INT_R.SS2END2->>SE6BEG2": { + "src_wire": "SS2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.NE6END3->>LH12": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.SL1END0->>IMUX33": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.LH0->>SE6BEG3": { + "src_wire": "LH0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG3" + }, + "INT_R.NN2END1->>IMUX41": { + "src_wire": "NN2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.SE2END0->>SE2BEG0": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG0" + }, + "INT_R.NW6END2->>WR1BEG3": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WR1BEG3" + }, + "INT_R.BYP_BOUNCE5->>IMUX37": { + "src_wire": "BYP_BOUNCE5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.WL1END3->>IMUX39": { + "src_wire": "WL1END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX39" + }, + "INT_R.WL1END0->>BYP_ALT0": { + "src_wire": "WL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT0" + }, + "INT_R.NL1BEG_N3->>NN2BEG3": { + "src_wire": "NL1BEG_N3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.NE6END3->>SL1BEG3": { + "src_wire": "NE6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SL1BEG3" + }, + "INT_R.WW2END0->>IMUX2": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX2" + }, + "INT_R.LOGIC_OUTS16->>EL1BEG1": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.WW2END0->>NN2BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG1" + }, + "INT_R.SW2END0->>FAN_ALT2": { + "src_wire": "SW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT2" + }, + "INT_R.WW2END0->>IMUX34": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX34" + }, + "INT_R.EE2END1->>SW6BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SW6BEG1" + }, + "INT_R.SL1END0->>IMUX25": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX25" + }, + "INT_R.EE2END1->>SS2BEG1": { + "src_wire": "EE2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG1" + }, + "INT_R.ER1END2->>CTRL0": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "CTRL0" + }, + "INT_R.LOGIC_OUTS0->>NN6BEG0": { + "src_wire": "LOGIC_OUTS0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG0" + }, + "INT_R.SL1END0->>IMUX16": { + "src_wire": "SL1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX16" + }, + "INT_R.NL1END2->>EL1BEG1": { + "src_wire": "NL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.WW2END0->>WL1BEG_N3": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG_N3" + }, + "INT_R.SE2END2->>SE6BEG2": { + "src_wire": "SE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.VCC_WIRE->>IMUX17": { + "src_wire": "VCC_WIRE", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.WR1END2->>IMUX5": { + "src_wire": "WR1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX5" + }, + "INT_R.ER1END2->>IMUX37": { + "src_wire": "ER1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX37" + }, + "INT_R.LOGIC_OUTS16->>FAN_ALT5": { + "src_wire": "LOGIC_OUTS16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "FAN_ALT5" + }, + "INT_R.SW6END3->>LH12": { + "src_wire": "SW6END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LH12" + }, + "INT_R.SE2END0->>IMUX17": { + "src_wire": "SE2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX17" + }, + "INT_R.NN2END3->>NN6BEG3": { + "src_wire": "NN2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN6BEG3" + }, + "INT_R.NN2END2->>SE6BEG2": { + "src_wire": "NN2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG2" + }, + "INT_R.LOGIC_OUTS20->>EL1BEG1": { + "src_wire": "LOGIC_OUTS20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.SS2END0->>IMUX41": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX41" + }, + "INT_R.SW2END2->>SE2BEG2": { + "src_wire": "SW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE2BEG2" + }, + "INT_R.NE2END2->>IMUX43": { + "src_wire": "NE2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX43" + }, + "INT_R.NW2END2->>IMUX28": { + "src_wire": "NW2END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.NN6END2->>WW2BEG1": { + "src_wire": "NN6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG1" + }, + "INT_R.FAN_BOUNCE_S3_6->>BYP_ALT7": { + "src_wire": "FAN_BOUNCE_S3_6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "BYP_ALT7" + }, + "INT_R.WW2END0->>SR1BEG1": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SR1BEG1" + }, + "INT_R.WW4END3->>WW2BEG2": { + "src_wire": "WW4END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.LOGIC_OUTS5->>ER1BEG2": { + "src_wire": "LOGIC_OUTS5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.LOGIC_OUTS11->>SS2BEG3": { + "src_wire": "LOGIC_OUTS11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.SS2END0->>SS2BEG0": { + "src_wire": "SS2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG0" + }, + "INT_R.LOGIC_OUTS21->>NN2BEG3": { + "src_wire": "LOGIC_OUTS21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NN2BEG3" + }, + "INT_R.SS2END_N0_3->>NW6BEG0": { + "src_wire": "SS2END_N0_3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NW6BEG0" + }, + "INT_R.WW2END1->>IMUX19": { + "src_wire": "WW2END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX19" + }, + "INT_R.EE2END3->>SS2BEG3": { + "src_wire": "EE2END3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SS2BEG3" + }, + "INT_R.WW4END2->>ER1BEG2": { + "src_wire": "WW4END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.EE4END1->>ER1BEG2": { + "src_wire": "EE4END1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "ER1BEG2" + }, + "INT_R.SL1END2->>IMUX21": { + "src_wire": "SL1END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX21" + }, + "INT_R.LV0<<->>LH0": { + "src_wire": "LV0", + "can_invert": "0", + "is_directional": "0", + "is_pseudo": "0", + "dst_wire": "LH0" + }, + "INT_R.FAN_BOUNCE6->>IMUX33": { + "src_wire": "FAN_BOUNCE6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX33" + }, + "INT_R.LOGIC_OUTS10->>NE2BEG2": { + "src_wire": "LOGIC_OUTS10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NE2BEG2" + }, + "INT_R.NR1END0->>NR1BEG0": { + "src_wire": "NR1END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "NR1BEG0" + }, + "INT_R.SS6END2->>WW2BEG2": { + "src_wire": "SS6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WW2BEG2" + }, + "INT_R.WW2END0->>IMUX10": { + "src_wire": "WW2END0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX10" + }, + "INT_R.GFAN1->>IMUX28": { + "src_wire": "GFAN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IMUX28" + }, + "INT_R.LOGIC_OUTS8->>SE6BEG0": { + "src_wire": "LOGIC_OUTS8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "SE6BEG0" + }, + "INT_R.NW6END2->>EL1BEG1": { + "src_wire": "NW6END2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "EL1BEG1" + }, + "INT_R.WW4END_S0_0->>WL1BEG2": { + "src_wire": "WW4END_S0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "WL1BEG2" + } + }, "wires": [ - "NR1BEG1", - "SW2A1", - "BYP0", - "SE2END1", - "NN6BEG3", - "EE4A2", - "LVB7", - "NL1END0", - "NL1END_S3_0", - "WL1END1", - "BYP_BOUNCE6", - "LOGIC_OUTS13", - "LVB4", - "NE6E1", - "LV4", - "SS2END2", - "EE2END3", - "LOGIC_OUTS6", - "NN6A3", - "GCLK_B1_WEST", - "WW2A2", - "EL1END0", - "WR1END_S1_0", - "NE6D0", - "NE6B3", - "WW2A3", - "LVB8", - "MONITOR_N", - "LV0", - "ER1END3", - "SW2BEG0", - "ER1BEG3", - "FAN5", - "NN6C2", - "BYP_BOUNCE_N3_7", - "GCLK_B7", - "LOGIC_OUTS19", - "GCLK_B5_EAST", - "ER1BEG0", - "LH11", - "LOGIC_OUTS20", - "GCLK_B5_WEST", - "NE6E3", - "EE2END1", - "NW6C2", - "GCLK_B2", - "IMUX42", - "NE6END2", - "WW2END3", - "EE2BEG1", - "GCLK_B1", - "SS2END_N0_3", - "SR1BEG3", - "LV18", - "EE2BEG3", - "NW6B0", - "SE6E1", - "NW2BEG1", - "NN6BEG0", - "SW2BEG2", - "IMUX26", - "BYP3", - "SE6BEG1", - "SR1END2", - "SS6BEG2", - "SW6END3", - "WW4BEG3", - "NN6B2", - "BYP_BOUNCE5", - "LV6", - "BYP_ALT6", - "GCLK_B3_EAST", - "EE4A3", - "SS6B0", - "IMUX3", - "IMUX28", - "NW6END_S0_0", - "NW6END3", - "SS6E3", - "SL1BEG0", - "EE4A1", - "SR1END3", - "CLK0", - "LH12", - "SE6B2", - "WL1BEG_N3", - "SL1BEG3", - "NN6A2", - "NN6D0", - "FAN_BOUNCE_S3_2", - "EE2A2", - "SE6C2", - "WW2BEG2", - "EE2END0", - "EL1END1", - "NN2END_S2_0", - "SE6D3", - "IMUX8", - "WL1BEG3", - "NN6C0", - "NN2END0", - "LV11", - "NN2A3", - "LV15", - "EE4C3", - "CTRL1", - "SS6C1", - "CTRL0", - "FAN6", - "SS6C2", - "SR1BEG1", - "LOGIC_OUTS4", - "NW6A3", - "SS6A3", - "WW4B3", - "FAN3", - "SE6C1", - "SS2END0", - "SE2END2", - "LOGIC_OUTS3", - "WL1BEG1", - "BYP_BOUNCE1", - "FAN_BOUNCE2", - "LOGIC_OUTS23", - "NE2BEG3", - "WR1END1", - "EE2A1", - "LV7", - "SS2BEG3", - "SS6END1", - "SW6C2", - "WW4BEG1", - "SE6C3", - "LOGIC_OUTS18", - "WW4C2", - "NW2END_S0_0", - "LV1", - "INT_DQS_IOTOPHASER", - "WW4A2", - "NN6E0", - "NL1END1", - "WL1BEG0", - "NN6END0", - "NN6A0", - "SW6A1", - "SL1END2", - "GFAN0", - "IMUX24", - "SW6D0", - "GCLK_B5", - "NE2BEG1", - "NW6END0", - "LH3", - "SS6A2", - "IMUX13", - "NE6BEG3", - "CLK1", - "SS6B1", - "NE2A1", - "LOGIC_OUTS15", - "IMUX14", - "VCC_WIRE", - "NE6C2", - "WR1BEG0", - "NE2BEG2", - "FAN_BOUNCE0", - "IMUX39", - "SW6E2", - "ER1BEG1", - "GCLK_B6", - "LOGIC_OUTS0", - "SE6A1", - "WW2END2", - "NW6D1", - "SS2END3", - "LOGIC_OUTS12", - "IMUX32", - "IMUX11", - "BYP_BOUNCE2", - "SE6B3", - "WL1END2", - "NN6END2", - "WW4END3", - "FAN_BOUNCE_S3_0", - "SS6END0", - "EE2A0", - "IMUX6", - "EL1END_S3_0", - "SL1END0", - "IMUX45", - "IMUX36", - "IMUX2", - "EL1BEG0", - "FAN4", - "NR1END1", - "SE2BEG1", - "SR1END1", - "SW6B0", - "FAN7", - "LV12", - "NW6D2", - "GCLK_B0", - "SS6D1", - "IMUX10", - "EE4BEG0", - "NW6C0", - "SE2A3", - "SE6A2", - "FAN1", - "SW2END0", - "LH2", - "NE2END3", - "LOGIC_OUTS11", - "INT_PHASER_TO_IO_ICLK", - "BYP_BOUNCE3", - "ER1BEG_S0", - "LVB5", - "NN2END3", - "IMUX29", - "WL1END_N1_3", - "GCLK_B2_EAST", - "INT_PHASER_TO_IO_ICLKDIV", - "SE6E0", - "BYP_BOUNCE4", - "WR1BEG_S0", - "EE4BEG2", - "LH5", - "LV16", - "LH8", - "IMUX21", - "GCLK_B10", - "NN2BEG1", - "BYP_ALT1", - "IMUX27", - "IMUX18", - "SS6D3", - "FAN_ALT2", - "NE2END1", - "WW2END_N0_3", - "WW4END0", - "GCLK_B3_WEST", - "BYP1", - "NW6D3", - "NW6E0", - "NL1BEG_N3", - "SW2END_N0_3", - "NE6BEG0", - "BYP2", - "SE6END0", - "LH0", - "SW6END2", - "SW6B2", - "WW4B1", - "SW6END_N0_3", - "IMUX22", - "NR1BEG2", - "WW2A0", - "WW4C3", - "IMUX19", - "NN6E2", - "WW4A1", - "LVB6", - "SE2BEG3", - "BYP_ALT2", - "GCLK_B1_EAST", - "IMUX25", - "SW6BEG1", - "NE2A0", - "NE2A3", - "IMUX37", - "LOGIC_OUTS22", - "NE6END1", - "SS6E1", - "ER1END_N3_3", - "NE6A0", - "IMUX38", - "BYP_ALT3", - "SW6D1", - "SS6BEG1", - "SR1BEG_S0", - "WW2END1", - "SW6A0", - "NL1BEG0", - "EE4END1", - "BYP7", - "WW2BEG3", - "SL1BEG1", - "SW6C0", - "WR1BEG2", - "NW2A3", - "NE6D2", - "SS6C3", - "SE6END1", - "EE4B1", - "SS2A2", - "BYP4", - "EE2BEG2", - "LOGIC_OUTS17", - "IMUX34", - "FAN_BOUNCE1", - "NN2A0", - "IMUX47", - "IMUX9", - "LVB2", - "FAN_ALT7", - "WW4B2", - "SS6BEG3", - "IMUX35", - "LOGIC_OUTS21", - "LH7", - "LVB10", - "WW2BEG1", - "SE6END3", - "LH1", - "EE4B3", - "SW2END1", - "NW6A0", - "GCLK_B11", - "LV9", - "NL1END2", - "SS6D2", - "SS6END_N0_3", - "NE6END0", - "LOGIC_OUTS2", - "BYP_BOUNCE0", - "NN6B3", - "NW2A0", - "SE6BEG3", - "NN6C1", - "GCLK_B2_WEST", - "NN6A1", - "WR1END2", - "LOGIC_OUTS10", - "SW6D3", - "FAN_BOUNCE_S3_6", - "NW6E2", - "EE4A0", - "NW6B3", - "WW4END2", - "NW2END2", - "IMUX31", - "EL1END2", - "SL1END3", - "SS2BEG1", - "IMUX41", - "IMUX43", - "ER1END1", - "FAN_BOUNCE5", - "SR1BEG2", - "FAN_BOUNCE4", - "NN6E1", - "IMUX16", - "EE4C2", - "FAN_ALT4", - "IMUX7", - "SW2BEG3", - "SE6B0", - "SE6B1", - "SS6E0", - "WL1END3", - "GCLK_B3", - "NR1END0", - "SW6A3", - "SE6END2", - "NE6A1", - "NN6D1", - "IMUX5", - "FAN_ALT5", - "SE6BEG0", - "NW6B1", - "NE6D1", - "SW6A2", - "NW6A2", - "ER1END0", - "SE6D2", - "SW6E1", - "SW6END1", - "EE4END0", - "LVB11", - "WW2BEG0", - "LV17", - "WW4A0", - "LH6", - "WW4C1", - "SS6E2", - "WW4END_S0_0", - "SS6BEG0", - "SW2A2", - "LV13", - "EE4C1", - "NR1END3", - "EE4B0", - "SW6C1", - "NN6END1", - "NW6BEG2", - "NW2BEG2", - "BYP_BOUNCE_N3_6", - "LOGIC_OUTS8", - "NE6B0", - "FAN_BOUNCE3", - "BYP_ALT7", - "SW6E3", - "SE6BEG2", - "SS6B2", - "SS2BEG2", - "SW6BEG3", - "NE2END2", - "EL1BEG1", - "SW2A3", - "LOGIC_OUTS7", - "EE2BEG0", - "SE6E2", - "GCLK_B4_WEST", - "SE2END3", - "IMUX15", - "WW4END1", - "NW2BEG0", - "LH10", - "SS6C0", - "SW6BEG2", - "LV5", - "LVB0", - "SW6B1", - "NE6B2", - "LOGIC_OUTS16", - "WW4BEG2", - "BYP_BOUNCE7", - "NN6C3", - "INT_PHASER_TO_IO_OCLK", - "NE2A2", - "NL1BEG2", - "LVB9", - "NN2BEG0", - "FAN0", - "LV14", - "NN6BEG2", - "LV2", - "SS6D0", - "NE6E0", - "GCLK_B0_EAST", - "IMUX33", - "NE6E2", - "WL1BEG2", - "NN2A1", - "SL1END1", - "SE6A3", - "GCLK_B4_EAST", - "NW6BEG0", - "FAN_BOUNCE7", - "NE6BEG1", - "GCLK_B4", - "LH4", - "NW6BEG1", - "NW6D0", - "WW4BEG0", - "SS2A0", - "IMUX46", - "FAN_ALT6", - "NE6END3", - "NN2END1", - "NW6A1", - "NR1BEG3", - "WW4A3", - "SE2END0", - "SE2BEG2", - "LOGIC_OUTS1", - "NW6END1", - "SE6A0", - "LVB12", - "SS6A1", - "LOGIC_OUTS14", - "NW6C1", - "LOGIC_OUTS5", - "SW6B3", - "SS6A0", - "SE6D0", - "IMUX17", - "SW6END0", - "NW2END1", - "SR1END_N3_3", - "MONITOR_P", - "NN6BEG1", - "IMUX12", - "BYP_ALT5", - "INT_PHASER_TO_IO_OCLK1X_90", - "GFAN1", - "NW2A1", - "NW6B2", - "EL1BEG3", - "EE4BEG3", - "INT_PHASER_TO_IO_OCLKDIV", - "SS6END2", - "LH9", - "SS6B3", - "NW6E3", - "NE6A3", - "NW2BEG3", - "GCLK_B0_WEST", - "NN6D3", - "SW6D2", - "IMUX20", - "FAN_ALT1", - "WW4B0", - "NE6D3", - "LVB3", - "SS6END3", - "BYP_ALT4", - "IMUX4", - "EE2END2", - "BYP_BOUNCE_N3_2", - "LV8", - "WR1END3", - "FAN_ALT3", - "NN6END_S1_0", - "SE6E3", - "BYP6", "NE6C0", - "SL1BEG2", - "IMUX40", - "GCLK_B9", - "WR1BEG1", - "SE2A0", - "NR1END2", - "SE2A2", - "NR1BEG0", - "SE6D1", - "NW6BEG3", - "LV10", - "SW2BEG1", - "NN6B0", - "SS2A1", - "NN2BEG3", - "NW2A2", - "FAN_ALT0", - "NN6B1", - "ER1END2", - "IMUX44", - "SW6BEG0", - "FAN_BOUNCE6", - "NN2BEG2", - "NW2END0", - "EE4END3", - "EE4B2", - "WW4C0", - "BYP_ALT0", - "NE6B1", - "NE6A2", - "SS2BEG0", - "FAN_BOUNCE_S3_4", - "BYP5", - "NN6E3", - "WR1BEG3", - "NE2BEG0", - "NE6C1", - "SE6C0", - "NW2END3", - "EE4BEG1", - "IMUX0", - "LOGIC_OUTS9", - "EL1BEG_N3", - "NL1BEG1", - "NN2END2", - "ER1BEG2", - "NN6D2", - "EL1END3", - "LV3", - "WW2A1", - "NE6BEG2", - "SS2END1", - "BYP_BOUNCE_N3_3", - "SE2A1", - "GCLK_B8", - "EE2A3", - "EE4END2", - "SS2A3", "NN6END3", - "SE2BEG0", - "FAN2", - "WR1END0", - "NW6C3", - "NW6END2", - "NW6E1", + "EE2END2", + "SE6B0", + "NN6END1", + "BYP_ALT6", + "SL1BEG1", + "SE6B1", + "EE2BEG1", + "NW2BEG2", + "IMUX18", + "SW6A0", + "FAN5", + "FAN_BOUNCE_S3_2", + "BYP_BOUNCE_N3_3", + "NR1BEG2", + "SE6BEG0", "NE2END_S3_0", - "GND_WIRE", - "NE2END0", + "IMUX6", + "SW2END_N0_3", + "NE6END2", + "NN6A1", + "EE2END3", + "WW4A3", + "NN6C0", + "NW6BEG3", + "NN6D0", + "SL1END0", + "NE2BEG2", + "LOGIC_OUTS6", + "WR1END_S1_0", + "NN6A3", + "WW4C3", + "NW6BEG2", + "WR1END0", + "SS2BEG2", + "NW6END3", + "NL1END2", + "NN6E3", + "NN6END_S1_0", + "FAN1", + "SW6B2", + "SS6A2", + "SS6BEG2", + "GCLK_B2_WEST", + "IMUX10", + "BYP_BOUNCE0", + "WL1BEG0", + "EE2A3", + "NE6A2", + "LH4", + "IMUX12", + "SL1BEG0", + "GCLK_B9", + "SW6B1", + "SS6C3", + "NN6B1", + "IMUX44", + "NR1END3", + "ER1END3", + "FAN_ALT4", + "IMUX5", + "FAN_BOUNCE2", + "IMUX24", + "LH1", + "BYP6", + "LH10", + "NN6C3", + "SW6END1", + "SE6E1", + "BYP_BOUNCE5", + "LV11", + "NN2A0", + "LOGIC_OUTS13", + "LOGIC_OUTS5", + "WW2A0", + "SE6A2", + "FAN_BOUNCE7", + "NN2END0", + "NR1BEG0", + "WW4BEG3", + "WW2END_N0_3", + "SS6C2", + "FAN_ALT3", + "EE4A1", + "IMUX39", + "LV10", + "MONITOR_N", + "LOGIC_OUTS11", + "FAN_ALT6", + "GCLK_B2", + "GCLK_B1_EAST", + "BYP2", + "IMUX8", + "LV12", "SW2END3", - "IMUX23", - "LVB1", - "SW6C3", - "NE6C3", - "WL1END0", - "WW2END0", + "WW4B2", + "GCLK_B3_EAST", + "WW2END1", + "NN6C1", + "EE4END2", + "FAN6", + "EE2END1", + "NW6B1", + "ER1END0", + "NE2BEG3", + "SW2END0", + "VCC_WIRE", + "BYP7", + "WW2BEG1", + "WL1END2", + "EE2BEG3", + "FAN_ALT0", + "EE4END1", + "NR1END2", + "SS6D3", + "SE6B2", + "NW2BEG0", + "NR1END0", + "SE6C3", + "NW2A3", + "NN6E0", + "SW2A1", + "NL1BEG_N3", + "NE2END2", + "SW2BEG0", + "ER1END1", + "SW6E2", + "IMUX43", + "SS6C0", + "NE6D0", + "LOGIC_OUTS20", + "NW2BEG1", + "NW6C1", + "NE6E3", + "NW2A1", + "FAN_BOUNCE3", + "NW6D2", + "LOGIC_OUTS21", "SW6E0", - "SW2A0", - "EE4C0", - "NN2A2", + "SE6E0", + "EE4A2", + "LV0", + "ER1BEG3", + "NL1BEG0", "EL1BEG2", + "LV8", + "SS6D2", + "FAN0", + "SW2BEG1", + "SS6A1", + "GCLK_B2_EAST", + "IMUX32", + "IMUX33", + "BYP1", + "IMUX42", + "WR1BEG2", + "LOGIC_OUTS0", + "SS6B0", + "BYP_BOUNCE_N3_2", + "WW4END0", + "IMUX36", + "IMUX28", + "WW2END3", + "WR1BEG_S0", + "WR1BEG3", + "SW6A1", + "SW6END2", + "SS6END1", + "SS2END3", + "SL1BEG2", + "SW6BEG1", + "BYP_BOUNCE6", + "GCLK_B0", + "LVB0", + "SS6BEG1", + "NW6C2", + "FAN4", + "GCLK_B5", + "NE6D2", + "NN2A3", + "GCLK_B11", + "EE4C2", + "IMUX47", + "GCLK_B5_EAST", + "WW4B3", + "EE4B3", + "BYP_ALT1", + "SE2BEG1", + "LOGIC_OUTS17", + "SE6END1", + "SS6BEG0", + "IMUX34", + "NW6E3", + "SS2END_N0_3", + "IMUX21", + "FAN_BOUNCE5", + "WW2END2", + "GCLK_B4_EAST", + "SR1END_N3_3", + "INT_PHASER_TO_IO_OCLKDIV", + "LV18", + "NN2END2", + "SW6D2", + "BYP_BOUNCE2", + "LH3", + "NW6D0", + "NE2A2", + "NE6E2", + "SW6END3", + "NE6END3", + "WL1END1", + "LOGIC_OUTS22", + "FAN_BOUNCE_S3_0", + "LVB12", + "FAN2", + "EE4B0", + "BYP_BOUNCE7", + "GCLK_B4_WEST", + "NE6A3", + "SS6B2", + "IMUX29", + "ER1BEG_S0", + "WW2BEG2", + "IMUX7", + "LH11", + "LV4", + "NN2A1", + "NE6D3", + "LOGIC_OUTS15", + "EE4BEG2", + "NW6END2", + "WW4C2", + "WW4B0", + "WR1BEG1", + "NN6A2", + "LOGIC_OUTS9", + "NW6D3", + "INT_DQS_IOTOPHASER", + "EE2A0", + "ER1BEG0", + "NE6B3", + "LH6", + "NN6A0", + "LOGIC_OUTS16", + "WW4BEG1", + "EE4BEG1", + "IMUX20", + "IMUX45", + "SW6BEG0", + "IMUX25", + "EE4C1", + "CLK1", + "SW6END_N0_3", + "LH5", + "CLK0", + "INT_PHASER_TO_IO_ICLK", + "FAN3", + "SW6C2", + "WW2A2", + "SW2A2", + "BYP_ALT3", + "WW4END1", + "SS2BEG1", + "SS6A3", + "SE6BEG3", + "LH9", + "SL1BEG3", + "GCLK_B8", + "NW6A0", + "GCLK_B3_WEST", + "LOGIC_OUTS18", "IMUX1", + "BYP_BOUNCE4", + "WR1BEG0", + "SR1BEG2", + "GCLK_B5_WEST", + "NW2END0", + "BYP_ALT2", + "SW2END2", + "IMUX3", + "LV16", + "NE6B1", + "NW6END0", + "NN6BEG2", + "SS6E2", + "IMUX41", + "EE4BEG0", + "SE6END2", + "FAN_BOUNCE0", + "SL1END1", + "INT_PHASER_TO_IO_OCLK", + "SR1BEG3", + "NW6A1", + "WW4A0", + "EE2A1", + "GFAN0", + "SS6D1", + "FAN_BOUNCE1", + "BYP_BOUNCE1", + "EL1BEG3", + "SE6END3", + "SR1BEG1", + "SE2END2", + "WR1END2", + "LH2", + "NW6BEG0", + "SS2END2", + "SE2A2", + "BYP4", + "SW6A2", + "SR1END3", + "NW6END_S0_0", + "WW4A1", + "SW2END1", + "SE6BEG2", + "SE6BEG1", + "WW4BEG2", + "SS2A1", + "ER1END2", + "SW6E3", + "FAN_BOUNCE_S3_4", + "LV15", + "ER1END_N3_3", + "NN6C2", + "IMUX0", + "SE6E3", + "BYP5", + "NN6D2", + "WW4C1", + "LH12", + "SS2END1", + "NL1END_S3_0", + "LV1", + "SW6C0", + "WL1BEG_N3", + "SR1END1", + "FAN7", + "NN2BEG2", + "SE6C0", + "LVB5", + "EL1END2", + "GCLK_B4", + "NN6E2", + "SS6D0", + "SS6END3", + "IMUX4", + "BYP_BOUNCE_N3_7", + "WW2A1", + "SL1END2", + "NL1END1", + "NN6D3", + "LV17", + "SW6D1", + "NW2A0", + "SE6C2", + "SE6END0", + "SW2A0", + "LV5", + "LVB3", + "WW4C0", + "LOGIC_OUTS8", + "EE4C3", + "BYP0", + "NW6D1", + "BYP_ALT4", + "NN6END2", + "WW4END2", + "IMUX16", + "LOGIC_OUTS12", + "WW4END_S0_0", + "NN2END1", + "LH8", + "SE6D2", + "NR1BEG1", + "NE2A3", + "IMUX15", + "EE4B2", + "LVB8", + "NN6D1", + "IMUX2", + "LOGIC_OUTS14", + "FAN_ALT5", + "LVB10", + "EL1END3", + "LV6", + "LVB4", + "LOGIC_OUTS1", + "IMUX11", + "NN6B3", + "SE2END0", + "BYP_ALT5", + "FAN_ALT1", + "SW2A3", + "SS2A0", + "FAN_BOUNCE_S3_6", + "WL1BEG2", + "FAN_ALT7", + "NW2BEG3", + "NW2END2", + "IMUX22", + "NE6C3", + "GFAN1", + "IMUX27", + "EE4END3", + "NE2BEG0", + "WW4BEG0", + "WR1END3", + "SE2BEG3", + "SS2END0", + "INT_PHASER_TO_IO_OCLK1X_90", + "SS6E1", + "SE2BEG0", + "SW6A3", + "EL1BEG1", + "SW6E1", + "ER1BEG1", + "SW6B3", + "NE2A1", + "LVB2", + "GCLK_B0_EAST", + "NW6A3", + "LV7", + "LOGIC_OUTS4", + "LV13", + "GND_WIRE", + "LOGIC_OUTS2", + "SW6D3", + "NW6C0", + "SS6END_N0_3", + "EE2A2", + "NE6D1", + "FAN_BOUNCE4", + "SE2END3", + "NW2END_S0_0", + "LOGIC_OUTS10", + "EE4A3", + "SS6B3", + "NN6BEG1", + "LH7", + "CTRL0", + "SE2A0", + "IMUX19", + "BYP3", + "NE6B0", + "NL1BEG1", + "WW2END0", + "NR1BEG3", + "SS6E3", + "SS2A2", + "IMUX31", + "NE2END1", + "SE6E2", + "EL1END_S3_0", + "NE6BEG1", + "NL1BEG2", + "WW4A2", + "ER1BEG2", + "NL1END0", + "IMUX9", + "GCLK_B6", + "SS6C1", + "WW4B1", + "NN2BEG1", + "NE6BEG2", + "SE6D0", + "NN2BEG3", + "NE6E0", + "EL1BEG0", + "EL1END1", + "NE2BEG1", + "NN6END0", + "CTRL1", + "SW6C1", + "NN6E1", + "NN6B0", + "NE6B2", + "MONITOR_P", + "NW6BEG1", + "SW2BEG3", + "IMUX46", + "FAN_BOUNCE6", + "NW6B2", + "NW6B3", + "NN2BEG0", + "WW4END3", + "SS6END0", + "NE6E1", + "INT_PHASER_TO_IO_ICLKDIV", + "SS6E0", + "SS2BEG0", + "SE6C1", + "SW6END0", + "BYP_BOUNCE_N3_6", + "SE6D3", + "NE6END1", + "LVB1", + "SE2BEG2", + "EE2BEG2", + "NW6A2", + "SR1END2", + "EE4C0", + "NE6A0", + "NW6E2", + "NN2END3", + "EE4B1", + "GCLK_B10", + "EE4A0", + "NW2A2", + "LH0", + "SE2END1", + "LOGIC_OUTS7", + "NE2END0", + "LV3", + "LVB6", + "SL1END3", + "SE6A1", + "WL1END0", + "WL1END_N1_3", + "LVB7", + "GCLK_B0_WEST", + "WR1END1", + "LOGIC_OUTS19", + "SE6B3", + "NN6BEG0", + "SS2A3", + "WW2A3", + "NW6E1", + "IMUX40", + "WL1BEG3", + "EE4BEG3", + "LVB9", + "SW6BEG2", + "EL1BEG_N3", + "IMUX23", + "SW6D0", + "NN6B2", + "BYP_BOUNCE3", + "SE6D1", + "NE6C2", + "NW6B0", + "SS6BEG3", + "NW6END1", + "IMUX35", + "GCLK_B7", + "NE2END3", + "LV14", + "NW2END1", + "SW6C3", + "SS2BEG3", + "NE6BEG3", + "IMUX26", + "NE2A0", + "BYP_ALT0", + "NW6C3", + "SS6END2", + "SW2BEG2", + "NE6A1", + "LOGIC_OUTS3", + "IMUX38", + "SE2A1", "IMUX30", - "SW2END2" + "EE2END0", + "IMUX37", + "GCLK_B1", + "EE4END0", + "NN6BEG3", + "SW6BEG3", + "WW2BEG3", + "NR1END1", + "FAN_ALT2", + "WW2BEG0", + "NW2END3", + "GCLK_B1_WEST", + "WL1END3", + "NE6BEG0", + "GCLK_B3", + "LVB11", + "IMUX13", + "SR1BEG_S0", + "EL1END0", + "NW6E0", + "IMUX17", + "SW6B0", + "SS6A0", + "SE2A3", + "LOGIC_OUTS23", + "NE6C1", + "LV9", + "SS6B1", + "EE2BEG0", + "NN2A2", + "SE6A0", + "NE6END0", + "NN2END_S2_0", + "IMUX14", + "LV2", + "BYP_ALT7", + "WL1BEG1", + "SE6A3" ], + "tile_type": "INT_R", "sites": [ { - "prefix": "TIEOFF", - "y_coord": 0, - "type": "TIEOFF", "site_pins": { "HARD0": "GND_WIRE", "HARD1": "VCC_WIRE" }, + "type": "TIEOFF", + "prefix": "TIEOFF", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 } - ], - "pips": { - "INT_R.NE2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B8->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B8", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.LVB0->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LVB0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>LV0": { - "can_invert": "0", - "dst_wire": "LV0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.LV18->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.LH12->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B5->>GCLK_B5_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_B5_WEST", - "is_directional": "1", - "src_wire": "GCLK_B5", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.GND_WIRE->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GND_WIRE", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT0->>FAN_BOUNCE0": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE0", - "is_directional": "1", - "src_wire": "FAN_ALT0", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.LH0->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B11->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B11", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT7->>FAN_BOUNCE7": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE7", - "is_directional": "1", - "src_wire": "FAN_ALT7", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B11->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B11", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.WW4END_S0_0->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_6->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LH6->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE2->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B4_EAST->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B4_EAST", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.LV9->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT3->>BYP3": { - "can_invert": "0", - "dst_wire": "BYP3", - "is_directional": "1", - "src_wire": "BYP_ALT3", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.NL1END_S3_0->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.WL1END_N1_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.SR1END_N3_3->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B7->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B7", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.NW6END_S0_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_2->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.LVB12->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LVB12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_3->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B10->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B10", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B6->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B6", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.WR1END_S1_0->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B0_EAST->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B0_EAST", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT0->>BYP_BOUNCE0": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE0", - "is_directional": "1", - "src_wire": "BYP_ALT0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_6->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LH0->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT7->>BYP_BOUNCE7": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE7", - "is_directional": "1", - "src_wire": "BYP_ALT7", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.LV0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B7->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B7", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.WL1END_N1_3->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.LH12->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.NN2END_S2_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.EL1END_S3_0->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "EL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_2->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT4->>FAN_BOUNCE4": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE4", - "is_directional": "1", - "src_wire": "FAN_ALT4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT0->>FAN0": { - "can_invert": "0", - "dst_wire": "FAN0", - "is_directional": "1", - "src_wire": "FAN_ALT0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B9->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT5->>FAN5": { - "can_invert": "0", - "dst_wire": "FAN5", - "is_directional": "1", - "src_wire": "FAN_ALT5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B0->>GCLK_B0_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_B0_WEST", - "is_directional": "1", - "src_wire": "GCLK_B0", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.SS2END_N0_3->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.LH6->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.LV18<<->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "0", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.LV18->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_6->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.LV18->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT2->>BYP2": { - "can_invert": "0", - "dst_wire": "BYP2", - "is_directional": "1", - "src_wire": "BYP_ALT2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.NN2END_S2_0->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B8->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B8", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.ER1END_N3_3->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "ER1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE2->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.LVB0->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LVB0", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.LH12->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.SR1END_N3_3->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.EL1END_S3_0->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "EL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT6->>FAN_BOUNCE6": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE6", - "is_directional": "1", - "src_wire": "FAN_ALT6", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.LVB12->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LVB12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B2_EAST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B2_EAST", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE2->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>LV0": { - "can_invert": "0", - "dst_wire": "LV0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B5_EAST->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B5_EAST", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B11->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B11", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_2->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B4->>GCLK_B4_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_B4_WEST", - "is_directional": "1", - "src_wire": "GCLK_B4", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_2->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_2->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B3_EAST->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B3_EAST", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>LV0": { - "can_invert": "0", - "dst_wire": "LV0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.LV9->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.LH12->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.SW2END_N0_3->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.LV0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.NL1END_S3_0->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_2->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.SR1END_N3_3->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT5->>FAN_BOUNCE5": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE5", - "is_directional": "1", - "src_wire": "FAN_ALT5", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT3->>FAN_BOUNCE3": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE3", - "is_directional": "1", - "src_wire": "FAN_ALT3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_6->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.WW4END_S0_0->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END_N1_3->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_R.LH0->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.SS2END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.SW6END_N0_3->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "SW6END_N0_3", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B5_EAST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B5_EAST", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_3->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_R.WL1END_N1_3->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT2->>FAN2": { - "can_invert": "0", - "dst_wire": "FAN2", - "is_directional": "1", - "src_wire": "FAN_ALT2", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT7->>FAN7": { - "can_invert": "0", - "dst_wire": "FAN7", - "is_directional": "1", - "src_wire": "FAN_ALT7", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_3->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B0_EAST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B0_EAST", - "is_pseudo": "0" - }, - "INT_R.GCLK_B0_EAST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B0_EAST", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.LV0<<->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "0", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.LVB12->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LVB12", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.NW6END_S0_0->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B1_EAST->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B1_EAST", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.GCLK_B3_EAST->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B3_EAST", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.GCLK_B1->>GCLK_B1_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_B1_WEST", - "is_directional": "1", - "src_wire": "GCLK_B1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE2->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B4_EAST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B4_EAST", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.EL1END_S3_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "EL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.WW4END_S0_0->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.SW2END_N0_3->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.GCLK_B3_EAST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B3_EAST", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.LV0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NE2END_S3_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NE2END_S3_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.LH12->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.LV9->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.LH0->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.LV0<<->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "0", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.NL1END_S3_0->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.LH6->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT6->>BYP6": { - "can_invert": "0", - "dst_wire": "BYP6", - "is_directional": "1", - "src_wire": "BYP_ALT6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE2->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B4_EAST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B4_EAST", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.LH6->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.LH6->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT2->>BYP_BOUNCE2": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE2", - "is_directional": "1", - "src_wire": "BYP_ALT2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B2->>GCLK_B2_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_B2_EAST", - "is_directional": "1", - "src_wire": "GCLK_B2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LVB0->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LVB0", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B3_EAST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B3_EAST", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END_N0_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE2->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.WR1END_S1_0->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.SS2END_N0_3->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.LVB0->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LVB0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B1_EAST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B1_EAST", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.ER1END_N3_3->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "ER1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE6->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_6->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.NN2END_S2_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.LH12->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.GCLK_B8->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B8", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE4->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT1->>BYP_BOUNCE1": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE1", - "is_directional": "1", - "src_wire": "BYP_ALT1", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE2->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE2->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.WR1END_S1_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>LV0": { - "can_invert": "0", - "dst_wire": "LV0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_3->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_R.LVB0->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LVB0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LV9->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B4->>GCLK_B4_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_B4_EAST", - "is_directional": "1", - "src_wire": "GCLK_B4", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.LH6->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LV18->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT3->>FAN3": { - "can_invert": "0", - "dst_wire": "FAN3", - "is_directional": "1", - "src_wire": "FAN_ALT3", - "is_pseudo": "0" - }, - "INT_R.NE2END_S3_0->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "NE2END_S3_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT7->>BYP7": { - "can_invert": "0", - "dst_wire": "BYP7", - "is_directional": "1", - "src_wire": "BYP_ALT7", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.LH12->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT4->>BYP4": { - "can_invert": "0", - "dst_wire": "BYP4", - "is_directional": "1", - "src_wire": "BYP_ALT4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.SW6END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "SW6END_N0_3", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.LV0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_3->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.LV9->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END_S2_0->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT5->>BYP5": { - "can_invert": "0", - "dst_wire": "BYP5", - "is_directional": "1", - "src_wire": "BYP_ALT5", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_3->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_R.LV0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.LVB12->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LVB12", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.GCLK_B1_EAST->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B1_EAST", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT6->>BYP_BOUNCE6": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE6", - "is_directional": "1", - "src_wire": "BYP_ALT6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B9->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B9", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.NW6END_S0_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.GCLK_B10->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B10", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B1->>GCLK_B1_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_B1_EAST", - "is_directional": "1", - "src_wire": "GCLK_B1", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B9->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE6->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.LV9->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT1->>BYP1": { - "can_invert": "0", - "dst_wire": "BYP1", - "is_directional": "1", - "src_wire": "BYP_ALT1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B2_EAST->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B2_EAST", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_2->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_2->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE6->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.SW2END_N0_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.NW6END_S0_0->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LV18->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.NL1END_S3_0->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.LVB12->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LVB12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>LV0": { - "can_invert": "0", - "dst_wire": "LV0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B10->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B10", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LV9->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE6->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LV18<<->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "0", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.GCLK_B4_EAST->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B4_EAST", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.LV18->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.NW6END_S0_0->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_R.NN6END_S1_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "NN6END_S1_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.SW2END_N0_3->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.ER1END_N3_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "ER1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE2->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.NN6END_S1_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "NN6END_S1_0", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.LV9->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_2->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.LVB0->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LVB0", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.SW2END_N0_3->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LV18->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE6->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE2->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.WW4END_S0_0->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LH0->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_2->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B6->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.SR1END_N3_3->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LV18->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_2->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B6->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B6", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>LV0": { - "can_invert": "0", - "dst_wire": "LV0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>SL1BEG2": { - "can_invert": "0", - "dst_wire": "SL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B6->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B6", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE2->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.LVB0->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LVB0", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.LH12->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.LV0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.NW6END_S0_0->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "NW6END_S0_0", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.WR1END_S1_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LH0->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_6->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.LH0->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B3->>GCLK_B3_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_B3_WEST", - "is_directional": "1", - "src_wire": "GCLK_B3", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.LV0->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE6->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NL1END_S3_0->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LH0->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NN2END_S2_0->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT4->>BYP_BOUNCE4": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE4", - "is_directional": "1", - "src_wire": "BYP_ALT4", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT6->>FAN6": { - "can_invert": "0", - "dst_wire": "FAN6", - "is_directional": "1", - "src_wire": "FAN_ALT6", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.LVB0<<->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "0", - "src_wire": "LVB0", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WR1END_S1_0->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.WW4END_S0_0->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.LVB12->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LVB12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE2->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LH6->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE6->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE2->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.NL1END_S3_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.EL1END_S3_0->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "EL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.WL1END_N1_3->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_R.SW2END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT1->>FAN1": { - "can_invert": "0", - "dst_wire": "FAN1", - "is_directional": "1", - "src_wire": "FAN_ALT1", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.SR1END_N3_3->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.LH0<<->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "0", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>SW6BEG0": { - "can_invert": "0", - "dst_wire": "SW6BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B0->>GCLK_B0_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_B0_EAST", - "is_directional": "1", - "src_wire": "GCLK_B0", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>LV0": { - "can_invert": "0", - "dst_wire": "LV0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE6->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B2_EAST->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B2_EAST", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.WW4END_S0_0->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LV18->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.LH6->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.WL1END_N1_3->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.SS6END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "SS6END_N0_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>SE6BEG0": { - "can_invert": "0", - "dst_wire": "SE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SS6END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "SS6END_N0_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.WW4END_S0_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.SW6END_N0_3->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "SW6END_N0_3", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.LH6->>LV0": { - "can_invert": "0", - "dst_wire": "LV0", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT0->>BYP0": { - "can_invert": "0", - "dst_wire": "BYP0", - "is_directional": "1", - "src_wire": "BYP_ALT0", - "is_pseudo": "0" - }, - "INT_R.WW4END_S0_0->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "WW4END_S0_0", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>LV0": { - "can_invert": "0", - "dst_wire": "LV0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B5_EAST->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B5_EAST", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.WL1END_N1_3->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LH6->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>EL1BEG_N3": { - "can_invert": "0", - "dst_wire": "EL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE2->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LV9->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.NN6END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NN6END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B7->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>SE6BEG3": { - "can_invert": "0", - "dst_wire": "SE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>WW2BEG3": { - "can_invert": "0", - "dst_wire": "WW2BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.LH6->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>NE6BEG1": { - "can_invert": "0", - "dst_wire": "NE6BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.NE2END_S3_0->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "NE2END_S3_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.SS2END_N0_3->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_2->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END_N0_3->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>NN2BEG1": { - "can_invert": "0", - "dst_wire": "NN2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS16->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS16", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.LVB12->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LVB12", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>NR1BEG1": { - "can_invert": "0", - "dst_wire": "NR1BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_2->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "BYP_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_6->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_6", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.NN6END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NN6END0", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT2->>FAN_BOUNCE2": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE2", - "is_directional": "1", - "src_wire": "FAN_ALT2", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B5->>GCLK_B5_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_B5_EAST", - "is_directional": "1", - "src_wire": "GCLK_B5", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT4->>FAN4": { - "can_invert": "0", - "dst_wire": "FAN4", - "is_directional": "1", - "src_wire": "FAN_ALT4", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE6->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>SW2BEG2": { - "can_invert": "0", - "dst_wire": "SW2BEG2", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.SL1END0->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "SL1END0", - "is_pseudo": "0" - }, - "INT_R.LV0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX4": { - "can_invert": "0", - "dst_wire": "IMUX4", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>SW2BEG1": { - "can_invert": "0", - "dst_wire": "SW2BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LH0->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.FAN_ALT1->>FAN_BOUNCE1": { - "can_invert": "0", - "dst_wire": "FAN_BOUNCE1", - "is_directional": "1", - "src_wire": "FAN_ALT1", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX3": { - "can_invert": "0", - "dst_wire": "IMUX3", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END_S3_0->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "NE2END_S3_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.NL1END_S3_0->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE6->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "FAN_BOUNCE6", - "is_pseudo": "0" - }, - "INT_R.LVB12->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "LVB12", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX22": { - "can_invert": "0", - "dst_wire": "IMUX22", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX13": { - "can_invert": "0", - "dst_wire": "IMUX13", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B9->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B9", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.NW2END0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "NW2END0", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.ER1END1->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "ER1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE2->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE2", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE5->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "BYP_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.LV0->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>NW2BEG2": { - "can_invert": "0", - "dst_wire": "NW2BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B0_EAST->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B0_EAST", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.LVB0->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LVB0", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SE2END3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B3->>GCLK_B3_EAST": { - "can_invert": "0", - "dst_wire": "GCLK_B3_EAST", - "is_directional": "1", - "src_wire": "GCLK_B3", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX2": { - "can_invert": "0", - "dst_wire": "IMUX2", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.LH12->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.NE6END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "NE6END1", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>IMUX29": { - "can_invert": "0", - "dst_wire": "IMUX29", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "NR1END3", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.NN6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "NN6END2", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.GCLK_B10->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B10", - "is_pseudo": "0" - }, - "INT_R.LH0->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "LH0", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.SW2END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "SW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.NW2END_S0_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "NW2END_S0_0", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.SR1END_N3_3->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.SS6END2->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "SS6END2", - "is_pseudo": "0" - }, - "INT_R.GCLK_B8->>CLK0": { - "can_invert": "0", - "dst_wire": "CLK0", - "is_directional": "1", - "src_wire": "GCLK_B8", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>NW2BEG0": { - "can_invert": "0", - "dst_wire": "NW2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS17->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS17", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX11": { - "can_invert": "0", - "dst_wire": "IMUX11", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>NW6BEG1": { - "can_invert": "0", - "dst_wire": "NW6BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX19": { - "can_invert": "0", - "dst_wire": "IMUX19", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>NL1BEG0": { - "can_invert": "0", - "dst_wire": "NL1BEG0", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.NR1END1->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "NR1END1", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS19->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "LOGIC_OUTS19", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.NN2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "NN2END0", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT5->>BYP_BOUNCE5": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE5", - "is_directional": "1", - "src_wire": "BYP_ALT5", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_3->>BYP_ALT0": { - "can_invert": "0", - "dst_wire": "BYP_ALT0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.ER1END_N3_3->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "ER1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>IMUX9": { - "can_invert": "0", - "dst_wire": "IMUX9", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SR1END_N3_3->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>SE2BEG2": { - "can_invert": "0", - "dst_wire": "SE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS0->>NE2BEG0": { - "can_invert": "0", - "dst_wire": "NE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS0", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_6->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_6", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.ER1END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "ER1END2", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>SL1BEG1": { - "can_invert": "0", - "dst_wire": "SL1BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>SS6BEG3": { - "can_invert": "0", - "dst_wire": "SS6BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE4->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "BYP_BOUNCE4", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>ER1BEG_S0": { - "can_invert": "0", - "dst_wire": "ER1BEG_S0", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_2->>IMUX6": { - "can_invert": "0", - "dst_wire": "IMUX6", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_2", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.SS2END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "SS2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.SL1END2->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "SL1END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>LV18": { - "can_invert": "0", - "dst_wire": "LV18", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.WW4END0->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "WW4END0", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>WW4BEG2": { - "can_invert": "0", - "dst_wire": "WW4BEG2", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>IMUX1": { - "can_invert": "0", - "dst_wire": "IMUX1", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.NW6END2->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "NW6END2", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX44": { - "can_invert": "0", - "dst_wire": "IMUX44", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.SE6END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "SE6END2", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "BYP_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.EL1END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "EL1END1", - "is_pseudo": "0" - }, - "INT_R.LH6->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "LH6", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.LV0<<->>LH0": { - "can_invert": "0", - "dst_wire": "LH0", - "is_directional": "0", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>NE2BEG2": { - "can_invert": "0", - "dst_wire": "NE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.EL1END0->>IMUX40": { - "can_invert": "0", - "dst_wire": "IMUX40", - "is_directional": "1", - "src_wire": "EL1END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS15->>WL1BEG2": { - "can_invert": "0", - "dst_wire": "WL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS15", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.NN2END3->>IMUX23": { - "can_invert": "0", - "dst_wire": "IMUX23", - "is_directional": "1", - "src_wire": "NN2END3", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>NN6BEG1": { - "can_invert": "0", - "dst_wire": "NN6BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.SS6END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "SS6END3", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>BYP_ALT6": { - "can_invert": "0", - "dst_wire": "BYP_ALT6", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END_S2_0->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "NN2END_S2_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "LOGIC_OUTS3", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.BYP_ALT3->>BYP_BOUNCE3": { - "can_invert": "0", - "dst_wire": "BYP_BOUNCE3", - "is_directional": "1", - "src_wire": "BYP_ALT3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE3->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "FAN_BOUNCE3", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.VCC_WIRE->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "VCC_WIRE", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.EL1END3->>IMUX30": { - "can_invert": "0", - "dst_wire": "IMUX30", - "is_directional": "1", - "src_wire": "EL1END3", - "is_pseudo": "0" - }, - "INT_R.NN6END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NN6END1", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>BYP_ALT2": { - "can_invert": "0", - "dst_wire": "BYP_ALT2", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>WW2BEG0": { - "can_invert": "0", - "dst_wire": "WW2BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>SL1BEG3": { - "can_invert": "0", - "dst_wire": "SL1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>IMUX26": { - "can_invert": "0", - "dst_wire": "IMUX26", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END2->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "SE2END2", - "is_pseudo": "0" - }, - "INT_R.WR1END_S1_0->>BYP_ALT7": { - "can_invert": "0", - "dst_wire": "BYP_ALT7", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>SL1BEG0": { - "can_invert": "0", - "dst_wire": "SL1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NW2END2->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "NW2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>SR1BEG3": { - "can_invert": "0", - "dst_wire": "SR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.SR1END_N3_3->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "SR1END_N3_3", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.WR1END_S1_0->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_3->>IMUX25": { - "can_invert": "0", - "dst_wire": "IMUX25", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_3", - "is_pseudo": "0" - }, - "INT_R.GND_WIRE->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GND_WIRE", - "is_pseudo": "0" - }, - "INT_R.LV9->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LV9", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>IMUX20": { - "can_invert": "0", - "dst_wire": "IMUX20", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS20->>NN6BEG2": { - "can_invert": "0", - "dst_wire": "NN6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS20", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.LH12->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "LH12", - "is_pseudo": "0" - }, - "INT_R.ER1END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "ER1END0", - "is_pseudo": "0" - }, - "INT_R.SR1END1->>BYP_ALT5": { - "can_invert": "0", - "dst_wire": "BYP_ALT5", - "is_directional": "1", - "src_wire": "SR1END1", - "is_pseudo": "0" - }, - "INT_R.NR1END2->>IMUX45": { - "can_invert": "0", - "dst_wire": "IMUX45", - "is_directional": "1", - "src_wire": "NR1END2", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.SR1END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "SR1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS21->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS21", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE5->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "FAN_BOUNCE5", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX43": { - "can_invert": "0", - "dst_wire": "IMUX43", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.SS2END_N0_3->>WW4BEG0": { - "can_invert": "0", - "dst_wire": "WW4BEG0", - "is_directional": "1", - "src_wire": "SS2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.WL1END_N1_3->>NN2BEG0": { - "can_invert": "0", - "dst_wire": "NN2BEG0", - "is_directional": "1", - "src_wire": "WL1END_N1_3", - "is_pseudo": "0" - }, - "INT_R.GFAN0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "GFAN0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>NR1BEG0": { - "can_invert": "0", - "dst_wire": "NR1BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS6->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS6", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>NN6BEG3": { - "can_invert": "0", - "dst_wire": "NN6BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS4->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS4", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>SS2BEG3": { - "can_invert": "0", - "dst_wire": "SS2BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>SW2BEG0": { - "can_invert": "0", - "dst_wire": "SW2BEG0", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>SR1BEG2": { - "can_invert": "0", - "dst_wire": "SR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.SW6END_N0_3->>NW6BEG0": { - "can_invert": "0", - "dst_wire": "NW6BEG0", - "is_directional": "1", - "src_wire": "SW6END_N0_3", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>WW2BEG1": { - "can_invert": "0", - "dst_wire": "WW2BEG1", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX33": { - "can_invert": "0", - "dst_wire": "IMUX33", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B7->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B7", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_7->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_7", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>NW2BEG1": { - "can_invert": "0", - "dst_wire": "NW2BEG1", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX42": { - "can_invert": "0", - "dst_wire": "IMUX42", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS7->>NR1BEG3": { - "can_invert": "0", - "dst_wire": "NR1BEG3", - "is_directional": "1", - "src_wire": "LOGIC_OUTS7", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>NW2BEG3": { - "can_invert": "0", - "dst_wire": "NW2BEG3", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>WW4BEG1": { - "can_invert": "0", - "dst_wire": "WW4BEG1", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.EE4END2->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "EE4END2", - "is_pseudo": "0" - }, - "INT_R.NL1END0->>IMUX8": { - "can_invert": "0", - "dst_wire": "IMUX8", - "is_directional": "1", - "src_wire": "NL1END0", - "is_pseudo": "0" - }, - "INT_R.NE2END2->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "NE2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>SE6BEG1": { - "can_invert": "0", - "dst_wire": "SE6BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.NL1END2->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "NL1END2", - "is_pseudo": "0" - }, - "INT_R.SE2END0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "SE2END0", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "WW2END2", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>CTRL1": { - "can_invert": "0", - "dst_wire": "CTRL1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.WL1END3->>IMUX47": { - "can_invert": "0", - "dst_wire": "IMUX47", - "is_directional": "1", - "src_wire": "WL1END3", - "is_pseudo": "0" - }, - "INT_R.WL1END1->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "WL1END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.EE4END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "EE4END0", - "is_pseudo": "0" - }, - "INT_R.NE6END2->>EE2BEG2": { - "can_invert": "0", - "dst_wire": "EE2BEG2", - "is_directional": "1", - "src_wire": "NE6END2", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.SW6END0->>SS2BEG0": { - "can_invert": "0", - "dst_wire": "SS2BEG0", - "is_directional": "1", - "src_wire": "SW6END0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.SE2END1->>IMUX27": { - "can_invert": "0", - "dst_wire": "IMUX27", - "is_directional": "1", - "src_wire": "SE2END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>NW6BEG2": { - "can_invert": "0", - "dst_wire": "NW6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.SW2END1->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "SW2END1", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>NE6BEG2": { - "can_invert": "0", - "dst_wire": "NE6BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>LVB0": { - "can_invert": "0", - "dst_wire": "LVB0", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.WW2END1->>NN2BEG2": { - "can_invert": "0", - "dst_wire": "NN2BEG2", - "is_directional": "1", - "src_wire": "WW2END1", - "is_pseudo": "0" - }, - "INT_R.NR1END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "NR1END0", - "is_pseudo": "0" - }, - "INT_R.LV0->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "LV0", - "is_pseudo": "0" - }, - "INT_R.WW2END0->>IMUX17": { - "can_invert": "0", - "dst_wire": "IMUX17", - "is_directional": "1", - "src_wire": "WW2END0", - "is_pseudo": "0" - }, - "INT_R.SS6END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SS6END0", - "is_pseudo": "0" - }, - "INT_R.EE2END2->>WR1BEG3": { - "can_invert": "0", - "dst_wire": "WR1BEG3", - "is_directional": "1", - "src_wire": "EE2END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>FAN_ALT7": { - "can_invert": "0", - "dst_wire": "FAN_ALT7", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>WL1BEG1": { - "can_invert": "0", - "dst_wire": "WL1BEG1", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.NN2END1->>NE2BEG1": { - "can_invert": "0", - "dst_wire": "NE2BEG1", - "is_directional": "1", - "src_wire": "NN2END1", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>IMUX28": { - "can_invert": "0", - "dst_wire": "IMUX28", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>EE2BEG3": { - "can_invert": "0", - "dst_wire": "EE2BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>SW6BEG2": { - "can_invert": "0", - "dst_wire": "SW6BEG2", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.EE4END3->>SE2BEG3": { - "can_invert": "0", - "dst_wire": "SE2BEG3", - "is_directional": "1", - "src_wire": "EE4END3", - "is_pseudo": "0" - }, - "INT_R.LV18->>SW6BEG3": { - "can_invert": "0", - "dst_wire": "SW6BEG3", - "is_directional": "1", - "src_wire": "LV18", - "is_pseudo": "0" - }, - "INT_R.SW2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SW2END2", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>IMUX21": { - "can_invert": "0", - "dst_wire": "IMUX21", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.WR1END1->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "WR1END1", - "is_pseudo": "0" - }, - "INT_R.SR1BEG_S0->>IMUX34": { - "can_invert": "0", - "dst_wire": "IMUX34", - "is_directional": "1", - "src_wire": "SR1BEG_S0", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>SE6BEG2": { - "can_invert": "0", - "dst_wire": "SE6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS12->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "LOGIC_OUTS12", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>NL1BEG_N3": { - "can_invert": "0", - "dst_wire": "NL1BEG_N3", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.WW4END1->>ER1BEG1": { - "can_invert": "0", - "dst_wire": "ER1BEG1", - "is_directional": "1", - "src_wire": "WW4END1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>SS6BEG2": { - "can_invert": "0", - "dst_wire": "SS6BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>SR1BEG1": { - "can_invert": "0", - "dst_wire": "SR1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.SS2END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SS2END1", - "is_pseudo": "0" - }, - "INT_R.EE2END0->>FAN_ALT0": { - "can_invert": "0", - "dst_wire": "FAN_ALT0", - "is_directional": "1", - "src_wire": "EE2END0", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>BYP_ALT3": { - "can_invert": "0", - "dst_wire": "BYP_ALT3", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX12": { - "can_invert": "0", - "dst_wire": "IMUX12", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.NE6END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NE6END0", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS14->>NR1BEG2": { - "can_invert": "0", - "dst_wire": "NR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS14", - "is_pseudo": "0" - }, - "INT_R.SS6END1->>EE4BEG1": { - "can_invert": "0", - "dst_wire": "EE4BEG1", - "is_directional": "1", - "src_wire": "SS6END1", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>WR1BEG1": { - "can_invert": "0", - "dst_wire": "WR1BEG1", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.NE6END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "NE6END3", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE1->>IMUX36": { - "can_invert": "0", - "dst_wire": "IMUX36", - "is_directional": "1", - "src_wire": "FAN_BOUNCE1", - "is_pseudo": "0" - }, - "INT_R.SW6END2->>WW4BEG3": { - "can_invert": "0", - "dst_wire": "WW4BEG3", - "is_directional": "1", - "src_wire": "SW6END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>NL1BEG2": { - "can_invert": "0", - "dst_wire": "NL1BEG2", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS2->>EL1BEG1": { - "can_invert": "0", - "dst_wire": "EL1BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS2", - "is_pseudo": "0" - }, - "INT_R.EE4END1->>SW6BEG1": { - "can_invert": "0", - "dst_wire": "SW6BEG1", - "is_directional": "1", - "src_wire": "EE4END1", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE_N3_2->>IMUX0": { - "can_invert": "0", - "dst_wire": "IMUX0", - "is_directional": "1", - "src_wire": "BYP_BOUNCE_N3_2", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>LH12": { - "can_invert": "0", - "dst_wire": "LH12", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.EL1END2->>ER1BEG3": { - "can_invert": "0", - "dst_wire": "ER1BEG3", - "is_directional": "1", - "src_wire": "EL1END2", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE7->>FAN_ALT4": { - "can_invert": "0", - "dst_wire": "FAN_ALT4", - "is_directional": "1", - "src_wire": "FAN_BOUNCE7", - "is_pseudo": "0" - }, - "INT_R.GCLK_B2->>GCLK_B2_WEST": { - "can_invert": "0", - "dst_wire": "GCLK_B2_WEST", - "is_directional": "1", - "src_wire": "GCLK_B2", - "is_pseudo": "0" - }, - "INT_R.WR1END_S1_0->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "WR1END_S1_0", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>LVB12": { - "can_invert": "0", - "dst_wire": "LVB12", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.WW2END3->>IMUX39": { - "can_invert": "0", - "dst_wire": "IMUX39", - "is_directional": "1", - "src_wire": "WW2END3", - "is_pseudo": "0" - }, - "INT_R.NL1END1->>IMUX10": { - "can_invert": "0", - "dst_wire": "IMUX10", - "is_directional": "1", - "src_wire": "NL1END1", - "is_pseudo": "0" - }, - "INT_R.NW2END1->>WL1BEG_N3": { - "can_invert": "0", - "dst_wire": "WL1BEG_N3", - "is_directional": "1", - "src_wire": "NW2END1", - "is_pseudo": "0" - }, - "INT_R.NW6END1->>SS6BEG0": { - "can_invert": "0", - "dst_wire": "SS6BEG0", - "is_directional": "1", - "src_wire": "NW6END1", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>SS6BEG1": { - "can_invert": "0", - "dst_wire": "SS6BEG1", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B1_EAST->>CLK1": { - "can_invert": "0", - "dst_wire": "CLK1", - "is_directional": "1", - "src_wire": "GCLK_B1_EAST", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>ER1BEG2": { - "can_invert": "0", - "dst_wire": "ER1BEG2", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_4->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_4", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS5->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS5", - "is_pseudo": "0" - }, - "INT_R.EE2END1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "EE2END1", - "is_pseudo": "0" - }, - "INT_R.SE6END0->>EE2BEG0": { - "can_invert": "0", - "dst_wire": "EE2BEG0", - "is_directional": "1", - "src_wire": "SE6END0", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>NW6BEG3": { - "can_invert": "0", - "dst_wire": "NW6BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.NW6END3->>WR1BEG_S0": { - "can_invert": "0", - "dst_wire": "WR1BEG_S0", - "is_directional": "1", - "src_wire": "NW6END3", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>FAN_ALT1": { - "can_invert": "0", - "dst_wire": "FAN_ALT1", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.WW4END2->>NL1BEG1": { - "can_invert": "0", - "dst_wire": "NL1BEG1", - "is_directional": "1", - "src_wire": "WW4END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS1->>EE2BEG1": { - "can_invert": "0", - "dst_wire": "EE2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS1", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS10->>IMUX5": { - "can_invert": "0", - "dst_wire": "IMUX5", - "is_directional": "1", - "src_wire": "LOGIC_OUTS10", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.WR1END0->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "WR1END0", - "is_pseudo": "0" - }, - "INT_R.NE2END3->>EE4BEG3": { - "can_invert": "0", - "dst_wire": "EE4BEG3", - "is_directional": "1", - "src_wire": "NE2END3", - "is_pseudo": "0" - }, - "INT_R.WR1END2->>CTRL0": { - "can_invert": "0", - "dst_wire": "CTRL0", - "is_directional": "1", - "src_wire": "WR1END2", - "is_pseudo": "0" - }, - "INT_R.BYP_BOUNCE0->>FAN_ALT2": { - "can_invert": "0", - "dst_wire": "FAN_ALT2", - "is_directional": "1", - "src_wire": "BYP_BOUNCE0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>EE4BEG2": { - "can_invert": "0", - "dst_wire": "EE4BEG2", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.SW6END1->>SE2BEG1": { - "can_invert": "0", - "dst_wire": "SE2BEG1", - "is_directional": "1", - "src_wire": "SW6END1", - "is_pseudo": "0" - }, - "INT_R.FAN_BOUNCE_S3_0->>IMUX14": { - "can_invert": "0", - "dst_wire": "IMUX14", - "is_directional": "1", - "src_wire": "FAN_BOUNCE_S3_0", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX32": { - "can_invert": "0", - "dst_wire": "IMUX32", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.NL1END_S3_0->>IMUX7": { - "can_invert": "0", - "dst_wire": "IMUX7", - "is_directional": "1", - "src_wire": "NL1END_S3_0", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.NE2END1->>WR1BEG2": { - "can_invert": "0", - "dst_wire": "WR1BEG2", - "is_directional": "1", - "src_wire": "NE2END1", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX18": { - "can_invert": "0", - "dst_wire": "IMUX18", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SL1END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SL1END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS11->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "LOGIC_OUTS11", - "is_pseudo": "0" - }, - "INT_R.ER1END3->>IMUX31": { - "can_invert": "0", - "dst_wire": "IMUX31", - "is_directional": "1", - "src_wire": "ER1END3", - "is_pseudo": "0" - }, - "INT_R.SR1END2->>SS2BEG2": { - "can_invert": "0", - "dst_wire": "SS2BEG2", - "is_directional": "1", - "src_wire": "SR1END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS13->>SS2BEG1": { - "can_invert": "0", - "dst_wire": "SS2BEG1", - "is_directional": "1", - "src_wire": "LOGIC_OUTS13", - "is_pseudo": "0" - }, - "INT_R.NL1BEG_N3->>IMUX37": { - "can_invert": "0", - "dst_wire": "IMUX37", - "is_directional": "1", - "src_wire": "NL1BEG_N3", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>NE6BEG3": { - "can_invert": "0", - "dst_wire": "NE6BEG3", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS9->>BYP_ALT4": { - "can_invert": "0", - "dst_wire": "BYP_ALT4", - "is_directional": "1", - "src_wire": "LOGIC_OUTS9", - "is_pseudo": "0" - }, - "INT_R.NE2END0->>NE6BEG0": { - "can_invert": "0", - "dst_wire": "NE6BEG0", - "is_directional": "1", - "src_wire": "NE2END0", - "is_pseudo": "0" - }, - "INT_R.SS2END2->>FAN_ALT5": { - "can_invert": "0", - "dst_wire": "FAN_ALT5", - "is_directional": "1", - "src_wire": "SS2END2", - "is_pseudo": "0" - }, - "INT_R.SS2END3->>FAN_ALT3": { - "can_invert": "0", - "dst_wire": "FAN_ALT3", - "is_directional": "1", - "src_wire": "SS2END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS22->>IMUX16": { - "can_invert": "0", - "dst_wire": "IMUX16", - "is_directional": "1", - "src_wire": "LOGIC_OUTS22", - "is_pseudo": "0" - }, - "INT_R.WR1END3->>IMUX46": { - "can_invert": "0", - "dst_wire": "IMUX46", - "is_directional": "1", - "src_wire": "WR1END3", - "is_pseudo": "0" - }, - "INT_R.SE6END3->>EL1BEG2": { - "can_invert": "0", - "dst_wire": "EL1BEG2", - "is_directional": "1", - "src_wire": "SE6END3", - "is_pseudo": "0" - }, - "INT_R.WW2END_N0_3->>IMUX24": { - "can_invert": "0", - "dst_wire": "IMUX24", - "is_directional": "1", - "src_wire": "WW2END_N0_3", - "is_pseudo": "0" - }, - "INT_R.WL1END2->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "WL1END2", - "is_pseudo": "0" - }, - "INT_R.EE2END3->>NN2BEG3": { - "can_invert": "0", - "dst_wire": "NN2BEG3", - "is_directional": "1", - "src_wire": "EE2END3", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>IMUX38": { - "can_invert": "0", - "dst_wire": "IMUX38", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - }, - "INT_R.NN2END2->>IMUX35": { - "can_invert": "0", - "dst_wire": "IMUX35", - "is_directional": "1", - "src_wire": "NN2END2", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS23->>FAN_ALT6": { - "can_invert": "0", - "dst_wire": "FAN_ALT6", - "is_directional": "1", - "src_wire": "LOGIC_OUTS23", - "is_pseudo": "0" - }, - "INT_R.WL1END0->>BYP_ALT1": { - "can_invert": "0", - "dst_wire": "BYP_ALT1", - "is_directional": "1", - "src_wire": "WL1END0", - "is_pseudo": "0" - }, - "INT_R.SL1END1->>WL1BEG0": { - "can_invert": "0", - "dst_wire": "WL1BEG0", - "is_directional": "1", - "src_wire": "SL1END1", - "is_pseudo": "0" - }, - "INT_R.NW6END0->>NN6BEG0": { - "can_invert": "0", - "dst_wire": "NN6BEG0", - "is_directional": "1", - "src_wire": "NW6END0", - "is_pseudo": "0" - }, - "INT_R.SE6END1->>EL1BEG0": { - "can_invert": "0", - "dst_wire": "EL1BEG0", - "is_directional": "1", - "src_wire": "SE6END1", - "is_pseudo": "0" - }, - "INT_R.GCLK_B5_EAST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B5_EAST", - "is_pseudo": "0" - }, - "INT_R.GCLK_B11->>GFAN1": { - "can_invert": "0", - "dst_wire": "GFAN1", - "is_directional": "1", - "src_wire": "GCLK_B11", - "is_pseudo": "0" - }, - "INT_R.WW4END3->>WW2BEG2": { - "can_invert": "0", - "dst_wire": "WW2BEG2", - "is_directional": "1", - "src_wire": "WW4END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS18->>IMUX41": { - "can_invert": "0", - "dst_wire": "IMUX41", - "is_directional": "1", - "src_wire": "LOGIC_OUTS18", - "is_pseudo": "0" - }, - "INT_R.GFAN1->>IMUX15": { - "can_invert": "0", - "dst_wire": "IMUX15", - "is_directional": "1", - "src_wire": "GFAN1", - "is_pseudo": "0" - }, - "INT_R.SW2END0->>SE2BEG0": { - "can_invert": "0", - "dst_wire": "SE2BEG0", - "is_directional": "1", - "src_wire": "SW2END0", - "is_pseudo": "0" - }, - "INT_R.SW6END3->>SR1BEG_S0": { - "can_invert": "0", - "dst_wire": "SR1BEG_S0", - "is_directional": "1", - "src_wire": "SW6END3", - "is_pseudo": "0" - }, - "INT_R.LOGIC_OUTS8->>EE4BEG0": { - "can_invert": "0", - "dst_wire": "EE4BEG0", - "is_directional": "1", - "src_wire": "LOGIC_OUTS8", - "is_pseudo": "0" - }, - "INT_R.SW2END3->>SW2BEG3": { - "can_invert": "0", - "dst_wire": "SW2BEG3", - "is_directional": "1", - "src_wire": "SW2END3", - "is_pseudo": "0" - }, - "INT_R.GCLK_B2_EAST->>GFAN0": { - "can_invert": "0", - "dst_wire": "GFAN0", - "is_directional": "1", - "src_wire": "GCLK_B2_EAST", - "is_pseudo": "0" - }, - "INT_R.NW2END3->>NE2BEG3": { - "can_invert": "0", - "dst_wire": "NE2BEG3", - "is_directional": "1", - "src_wire": "NW2END3", - "is_pseudo": "0" - } - }, - "tile_type": "INT_R" + ] } \ No newline at end of file diff --git a/artix7/tile_type_IO_INT_INTERFACE_L.json b/artix7/tile_type_IO_INT_INTERFACE_L.json index 401dc8a..5d185c2 100644 --- a/artix7/tile_type_IO_INT_INTERFACE_L.json +++ b/artix7/tile_type_IO_INT_INTERFACE_L.json @@ -1,428 +1,428 @@ { - "wires": [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "INT_INTERFACE_BYP5", - "INT_INTERFACE_IMUX45", - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_IMUX27", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "INT_INTERFACE_IMUX1", - "INT_INTERFACE_IMUX7", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_IMUX47", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_IMUX18", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_LH10", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "INT_INTERFACE_IMUX28", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_LOGIC_OUTS_L19", - "INT_INTERFACE_LH1", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_IMUX16", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_CLK0", - "INT_INTERFACE_LOGIC_OUTS_L22", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_LOGIC_OUTS_L4", - "INT_INTERFACE_LH6", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_IMUX44", - "INT_INTERFACE_IMUX43", - "INT_INTERFACE_IMUX10", - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "INT_INTERFACE_IMUX26", - "INT_INTERFACE_LOGIC_OUTS_L13", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_IMUX42", - "INT_INTERFACE_BLOCK_OUTS_L_B2", - "INT_INTERFACE_IMUX39", - "INT_INTERFACE_IMUX22", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_LOGIC_OUTS_L1", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_IMUX25", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_LOGIC_OUTS_L5", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_LOGIC_OUTS_L3", - "INT_INTERFACE_IMUX19", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_LOGIC_OUTS_L7", - "INT_INTERFACE_LOGIC_OUTS_L0", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "INT_INTERFACE_EE2A0", - "L_INT_INTER_DQS_IOTOPHASER", - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_IMUX4", - "INT_INTERFACE_IMUX12", - "INT_INTERFACE_LOGIC_OUTS_L21", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_LOGIC_OUTS_L18", - "INT_INTERFACE_LOGIC_OUTS_L14", - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "INT_INTERFACE_LOGIC_OUTS_L11", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_IMUX3", - "INT_INTERFACE_IMUX13", - "INT_INTERFACE_IMUX17", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_IMUX29", - "INT_INTERFACE_BYP1", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_LOGIC_OUTS_L23", - "INT_INTERFACE_LH8", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_IMUX31", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_LOGIC_OUTS_L_B14", - "INT_INTERFACE_IMUX0", - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "INT_INTERFACE_LOGIC_OUTS_L8", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_IMUX14", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_LH7", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_LOGIC_OUTS_L20", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_LH5", - "INT_INTERFACE_IMUX35", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_IMUX11", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_IMUX21", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "INT_INTERFACE_LOGIC_OUTS_L2", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_BYP2", - "INT_INTERFACE_IMUX38", - "INT_INTERFACE_IMUX23", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_LOGIC_OUTS_L10", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_IMUX24", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_IMUX41", - "INT_INTERFACE_IMUX40", - "INT_INTERFACE_IMUX8", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_LH2", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_IMUX20", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_IMUX36", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH9", - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "INT_INTERFACE_LOGIC_OUTS_L6", - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "INT_INTERFACE_IMUX32", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_BLOCK_OUTS_L_B0", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_IMUX37", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_IMUX33", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_IMUX6", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_LOGIC_OUTS_L12", - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW4END3", - "INT_INTERFACE_LH11", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "INT_INTERFACE_IMUX9", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_IMUX5", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_LOGIC_OUTS_L15", - "INT_INTERFACE_BLOCK_OUTS_L_B1", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_IMUX15", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_LOGIC_OUTS_L16", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_IMUX30", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_BLOCK_OUTS_L_B3", - "INT_INTERFACE_ER1BEG1", - "INT_INTERFACE_IMUX2", - "INT_INTERFACE_LOGIC_OUTS_L17", - "INT_INTERFACE_IMUX46", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_LH3", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_IMUX34", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_LOGIC_OUTS_L9" - ], - "sites": [], "pips": { - "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18", "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4", "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", - "is_pseudo": "0" - }, - "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { - "can_invert": "0", - "dst_wire": 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"INT_INTERFACE_LOGIC_OUTS_L22" }, "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1", - "is_directional": "1", "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1" }, "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17", - "is_directional": "1", "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14" + }, + "IO_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": { + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23" } }, - "tile_type": "IO_INT_INTERFACE_L" + "wires": [ + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_WR1END1", + "INT_INTERFACE_IMUX28", + "INT_INTERFACE_IMUX15", + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "INT_INTERFACE_LOGIC_OUTS_L13", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_LOGIC_OUTS_L19", + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_LOGIC_OUTS_L1", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_IMUX23", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LH8", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_BLOCK_OUTS_L_B0", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_IMUX37", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_IMUX24", + "INT_INTERFACE_IMUX22", + "INT_INTERFACE_IMUX4", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_IMUX44", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_IMUX33", + "INT_INTERFACE_IMUX17", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_LOGIC_OUTS_L8", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_IMUX12", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "INT_INTERFACE_IMUX47", + "INT_INTERFACE_IMUX46", + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "INT_INTERFACE_LOGIC_OUTS_L5", + "INT_INTERFACE_IMUX13", + "INT_INTERFACE_IMUX1", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_IMUX0", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_BLOCK_OUTS_L_B2", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_IMUX25", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_IMUX29", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_IMUX21", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_LOGIC_OUTS_L22", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_LOGIC_OUTS_L3", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_BLOCK_OUTS_L_B1", + "INT_INTERFACE_LOGIC_OUTS_L23", + "INT_INTERFACE_LOGIC_OUTS_L11", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_IMUX36", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_IMUX10", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_LH6", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_IMUX3", + "INT_INTERFACE_IMUX11", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_IMUX8", + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_IMUX2", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_IMUX18", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LH5", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LH12", + "INT_INTERFACE_LH4", + "INT_INTERFACE_LOGIC_OUTS_L18", + "INT_INTERFACE_IMUX34", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_LOGIC_OUTS_L16", + "INT_INTERFACE_IMUX35", + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "INT_INTERFACE_LOGIC_OUTS_L2", + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "INT_INTERFACE_EL1BEG3", + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "INT_INTERFACE_IMUX5", + "INT_INTERFACE_BLOCK_OUTS_L_B3", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_IMUX32", + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_IMUX30", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_IMUX42", + "INT_INTERFACE_IMUX20", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_IMUX39", + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_LOGIC_OUTS_L10", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_LH7", + "INT_INTERFACE_IMUX14", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_LOGIC_OUTS_L9", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_IMUX6", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_IMUX45", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_LOGIC_OUTS_L15", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_IMUX38", + "INT_INTERFACE_IMUX43", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_LH2", + "INT_INTERFACE_LOGIC_OUTS_L21", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_IMUX41", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_LOGIC_OUTS_L20", + "INT_INTERFACE_LOGIC_OUTS_L14", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_LH9", + "INT_INTERFACE_LOGIC_OUTS_L17", + "INT_INTERFACE_LOGIC_OUTS_L0", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_IMUX27", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_IMUX26", + "INT_INTERFACE_LOGIC_OUTS_L12", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_LOGIC_OUTS_L6", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_LH3", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_IMUX19", + "INT_INTERFACE_IMUX7", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_L4", + "INT_INTERFACE_IMUX40", + "INT_INTERFACE_IMUX16", + "INT_INTERFACE_IMUX31", + "INT_INTERFACE_IMUX9", + "INT_INTERFACE_LOGIC_OUTS_L7", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + "tile_type": "IO_INT_INTERFACE_L", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_IO_INT_INTERFACE_R.json b/artix7/tile_type_IO_INT_INTERFACE_R.json index 69151b7..cc28707 100644 --- a/artix7/tile_type_IO_INT_INTERFACE_R.json +++ b/artix7/tile_type_IO_INT_INTERFACE_R.json @@ -1,428 +1,428 @@ { - "wires": [ - "INT_INTERFACE_BYP5", - "INT_INTERFACE_IMUX45", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_IMUX27", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_IMUX1", - "INT_INTERFACE_IMUX7", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_IMUX47", - "INT_INTERFACE_LOGIC_OUTS17", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_IMUX18", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_LOGIC_OUTS16", - "INT_INTERFACE_LH10", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_BLOCK_OUTS_B0", - "INT_INTERFACE_IMUX28", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_LH1", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_IMUX16", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_LOGIC_OUTS10", - "INT_INTERFACE_CLK0", - "INT_INTERFACE_LOGIC_OUTS7", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_LOGIC_OUTS_B1", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_LOGIC_OUTS5", - "INT_INTERFACE_LH6", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_BLOCK_OUTS_B2", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_IMUX44", - "INT_INTERFACE_IMUX43", - "INT_INTERFACE_IMUX10", - "INT_INTERFACE_IMUX26", - "INT_INTERFACE_LOGIC_OUTS_B9", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_IMUX42", - "INT_INTERFACE_LOGIC_OUTS_B18", - "INT_INTERFACE_IMUX39", - "INT_INTERFACE_IMUX22", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_LOGIC_OUTS_B21", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS21", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_IMUX25", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_IMUX19", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_EE2A0", - "L_INT_INTER_DQS_IOTOPHASER", - "INT_INTERFACE_LOGIC_OUTS1", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_LOGIC_OUTS3", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_IMUX4", - "INT_INTERFACE_IMUX12", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_LOGIC_OUTS_B23", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_LOGIC_OUTS20", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_IMUX3", - "INT_INTERFACE_IMUX13", - "INT_INTERFACE_IMUX17", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_IMUX29", - "INT_INTERFACE_BYP1", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_LOGIC_OUTS4", - "INT_INTERFACE_LH8", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_IMUX31", - "INT_INTERFACE_LOGIC_OUTS12", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_LOGIC_OUTS_B4", - "INT_INTERFACE_IMUX0", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS_B5", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_IMUX14", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_LH7", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_LOGIC_OUTS11", - "INT_INTERFACE_LH5", - "INT_INTERFACE_IMUX35", - "INT_INTERFACE_BLOCK_OUTS_B3", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_IMUX11", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_IMUX21", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_LOGIC_OUTS18", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_BYP2", - "INT_INTERFACE_IMUX38", - "INT_INTERFACE_IMUX23", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_LOGIC_OUTS_B12", - "INT_INTERFACE_LOGIC_OUTS22", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_IMUX24", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_IMUX41", - "INT_INTERFACE_IMUX40", - "INT_INTERFACE_LOGIC_OUTS_B6", - "INT_INTERFACE_IMUX8", - "INT_INTERFACE_LOGIC_OUTS0", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_LH2", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_LOGIC_OUTS13", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_LOGIC_OUTS6", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_IMUX20", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_IMUX36", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_LOGIC_OUTS9", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH9", - "INT_INTERFACE_IMUX32", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_IMUX37", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_IMUX33", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_IMUX6", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW4END3", - "INT_INTERFACE_LOGIC_OUTS15", - "INT_INTERFACE_LH11", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_IMUX9", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_LOGIC_OUTS2", - "INT_INTERFACE_IMUX5", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_LOGIC_OUTS23", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_LOGIC_OUTS14", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_IMUX15", - "INT_INTERFACE_WW4B2", - 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"INT_INTERFACE_BLOCK_OUTS_B3", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_WW4A1", + "INT_INTERFACE_SW2A2", + "INT_INTERFACE_LOGIC_OUTS_B10", + "INT_INTERFACE_SW2A3", + "INT_INTERFACE_IMUX23", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LH8", + "INT_INTERFACE_LOGIC_OUTS_B22", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_WW4B1", + "INT_INTERFACE_LOGIC_OUTS4", + "INT_INTERFACE_LOGIC_OUTS1", + "INT_INTERFACE_WW2A2", + "INT_INTERFACE_IMUX37", + "INT_INTERFACE_LOGIC_OUTS0", + "INT_INTERFACE_LOGIC_OUTS_B11", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS20", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_EE4C1", + "INT_INTERFACE_LOGIC_OUTS18", + "INT_INTERFACE_IMUX24", + "INT_INTERFACE_LOGIC_OUTS_B20", + "INT_INTERFACE_IMUX22", + "INT_INTERFACE_IMUX4", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LOGIC_OUTS3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_IMUX44", + "INT_INTERFACE_LOGIC_OUTS_B14", + "INT_INTERFACE_BLOCK_OUTS_B2", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_IMUX33", + "INT_INTERFACE_IMUX17", + "INT_INTERFACE_LOGIC_OUTS_B1", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_WW2END2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_IMUX12", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_LOGIC_OUTS2", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_IMUX47", + "INT_INTERFACE_IMUX46", + "INT_INTERFACE_IMUX13", + "INT_INTERFACE_IMUX1", + "INT_INTERFACE_EE2BEG1", + "INT_INTERFACE_LOGIC_OUTS_B7", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_IMUX0", + "INT_INTERFACE_LOGIC_OUTS16", + "INT_INTERFACE_CLK0", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_NW4END0", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_IMUX25", + "INT_INTERFACE_LOGIC_OUTS8", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_LOGIC_OUTS9", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_IMUX29", + "INT_INTERFACE_SW2A0", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_IMUX21", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_EE4C2", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_EE4C3", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_WW4C1", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_IMUX36", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_ER1BEG3", + "INT_INTERFACE_LH6", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_IMUX3", + "INT_INTERFACE_IMUX11", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_IMUX8", + "INT_INTERFACE_WW4B0", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_LOGIC_OUTS14", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_LOGIC_OUTS11", + "INT_INTERFACE_LOGIC_OUTS_B18", + "INT_INTERFACE_IMUX2", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_PHASER_TO_IO_ICLK", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_NE2A2", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_NW2A1", + "INT_INTERFACE_LOGIC_OUTS10", + "INT_INTERFACE_IMUX18", + "INT_INTERFACE_FAN7", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LH1", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_LH5", + "INT_INTERFACE_LOGIC_OUTS_B3", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LH12", + "INT_INTERFACE_LH4", + "INT_INTERFACE_IMUX34", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_LOGIC_OUTS19", + "INT_INTERFACE_IMUX35", + "INT_INTERFACE_LOGIC_OUTS_B5", + "INT_INTERFACE_EL1BEG3", + "INT_INTERFACE_LOGIC_OUTS23", + "INT_INTERFACE_IMUX5", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS_B6", + "INT_INTERFACE_LOGIC_OUTS_B2", + "INT_INTERFACE_LOGIC_OUTS_B19", + "INT_INTERFACE_SE4BEG3", + "INT_INTERFACE_IMUX32", + "INT_INTERFACE_WW4END1", + "INT_INTERFACE_IMUX30", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_IMUX42", + "INT_INTERFACE_IMUX20", + "INT_INTERFACE_IMUX39", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_LOGIC_OUTS_B13", + "INT_INTERFACE_PHASER_TO_IO_OCLK", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_EE2A3", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_FAN3", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_NW4A3", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_LH7", + "INT_INTERFACE_IMUX14", + "INT_INTERFACE_BYP5", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_WW2A1", + "INT_INTERFACE_LOGIC_OUTS21", + "INT_INTERFACE_IMUX6", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_IMUX45", + "INT_INTERFACE_NW4END2", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_LOGIC_OUTS12", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_NW4A0", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_WR1END2", + "INT_INTERFACE_IMUX38", + "INT_INTERFACE_IMUX43", + "INT_INTERFACE_BYP4", + "INT_INTERFACE_LH2", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_LOGIC_OUTS_B4", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_IMUX41", + "INT_INTERFACE_LOGIC_OUTS_B17", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_LOGIC_OUTS7", + "INT_INTERFACE_WW4B2", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_FAN5", + "INT_INTERFACE_EE4C0", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS15", + "INT_INTERFACE_WW4C3", + "INT_INTERFACE_LH9", + "INT_INTERFACE_LOGIC_OUTS6", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_IMUX27", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_IMUX26", + "L_INT_INTER_DQS_IOTOPHASER", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_LOGIC_OUTS_B16", + "INT_INTERFACE_EE2A1", + "INT_INTERFACE_LH3", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_LOGIC_OUTS22", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_BLOCK_OUTS_B0", + "INT_INTERFACE_IMUX19", + "INT_INTERFACE_IMUX7", + "INT_INTERFACE_BLOCK_OUTS_B1", + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_LH10", + "INT_INTERFACE_LOGIC_OUTS_B15", + "INT_INTERFACE_IMUX40", + "INT_INTERFACE_IMUX16", + "INT_INTERFACE_IMUX31", + "INT_INTERFACE_IMUX9", + "INT_INTERFACE_LOGIC_OUTS13", + "INT_INTERFACE_IMUX10" + ], + "tile_type": "IO_INT_INTERFACE_R", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_LIOB33.json b/artix7/tile_type_LIOB33.json index f8c86bd..e69ea3a 100644 --- a/artix7/tile_type_LIOB33.json +++ b/artix7/tile_type_LIOB33.json @@ -1,415 +1,415 @@ { - "wires": [ - "LIOB_LH6_0", - "LIOB_SW4END0_1", - "LIOB_EE4A0_1", - "LIOB_LH2_0", - "LIOB_NW2A0_1", - "LIOB_SW4A0_0", - "LIOB_SE4BEG3_0", - "LIOB_EE4B0_1", - "IOB_PADOUT1", - "LIOB_LH6_1", - "IOB_IBUF_DISABLE1", - "LIOB_SW2A2_1", - "LIOB_NE4BEG3_0", - "LIOB_SW2A0_1", - "LIOB_NW4A3_1", - "IOB_KEEPER_INT_EN_1", - "LIOB_EE4C2_1", - "LIOB_WW4C1_0", - "LIOB_EE2BEG3_1", - "LIOB_SE4C1_1", - "LIOB_SW4END2_0", - "LIOB_WR1END1_1", - "LIOB_WW4END2_0", - "LIOB_EL1BEG2_1", - "LIOB_NW4A1_1", - "LIOB_NW4END1_0", - "LIOB_NW4END2_0", - "LIOB_WW2A0_1", - "LIOB_EE4BEG1_0", - "IOB_DIFFI_IN1", - "LIOB_WR1END3_0", - "LIOB_LH11_0", - "LIOB_WW2A1_1", - "LIOB_LH7_1", - "LIOB_EE2A0_0", - "LIOB_WW4END0_1", - "LIOB_EE2A2_0", - "LIOB_LH11_1", - "LIOB_SE4C2_1", - "LIOB_EE4B3_1", - "LIOB_NE2A3_1", - "LIOB_LH10_1", - "LIOB_EE4A0_0", - "LIOB_NW2A0_0", - "LIOB_WW2A1_0", - "LIOB_SE4C2_0", - "IOB_DIFF_TERM_INT_EN_STUB", - "LIOB_WL1END3_0", - "LIOB_NE2A1_1", - "LIOB_NW4END3_0", - "LIOB_NE4C0_1", - "LIOB_LH4_1", - "LIOB_EE4C0_0", - "LIOB_WR1END2_1", - "IOB_T_OUT0", - "LIOB_EL1BEG1_1", - "LIOB_EE2BEG3_0", - "LIOB_WW4END1_0", - "LIOB_ER1BEG3_1", - "LIOB_EL1BEG1_0", - "IOB_O1", - "LIOB_SE2A1_0", - "IOB_IBUF0", - "LIOB_NW4A1_0", - "LIOB_WW4B2_1", - "LIOB_EL1BEG0_1", - "IOB_DIFFO_OUT1", - "LIOB_WW4B2_0", - "LIOB_NW4A2_1", - "LIOB_SE4BEG0_1", - "LIOB_EL1BEG0_0", - "LIOB_EE4BEG3_0", - "LIOB_MONITOR_N", - "LIOB_ER1BEG1_1", - "LIOB_NE4C2_0", - "LIOB_NW2A2_1", - "LIOB_LH5_1", - "LIOB_EE4B1_0", - "LIOB_NW4A3_0", - "LIOB_NW4A0_0", - "IOB_KEEPER_INT_EN_0", - "LIOB_SE2A2_0", - "IOB_T_IN1", - "LIOB_EE2BEG1_0", - "LIOB_SW2A3_0", - "LIOB_SE4C3_0", - "LIOB_EE4A2_1", - "LIOB_LH1_1", - "LIOB_NE4BEG1_0", - "LIOB_WW2END0_0", - "LIOB_NE4BEG3_1", - "LIOB_WW4A0_1", - "LIOB_IN_TERM0", - "LIOB_EE2BEG0_0", - "LIOB_SE2A3_1", - "LIOB_SE4BEG0_0", - "LIOB_LH10_0", - "LIOB_NE2A1_0", - "IOB_IBUF1", - "LIOB_EL1BEG3_1", - "LIOB_WW4C1_1", - "LIOB_SE4C3_1", - "LIOB_WL1END1_1", - "LIOB_WW4C2_1", - "LIOB_SW4A0_1", - "LIOB_WW4C2_0", - "LIOB_NE4C0_0", - "LIOB_SE2A0_0", - "LIOB_NE4C3_0", - "LIOB_IN_TERM1", - "LIOB_SE4C1_0", - "LIOB_EE4C1_0", - "LIOB_NW2A3_1", - "LIOB_SE2A3_0", - "LIOB_EE4A3_0", - "LIOB_WW2A0_0", - "LIOB_NE4BEG0_0", - "LIOB_EE4B1_1", - "LIOB_WW4END3_1", - "LIOB_WW4A2_1", - "LIOB_ER1BEG3_0", - "LIOB_NW4END0_0", - "LIOB_WW2END0_1", - "LIOB_WW4B1_0", - "LIOB_ER1BEG0_0", - "LIOB_ER1BEG1_0", - "LIOB_EE4A1_0", - "LIOB_SW2A1_0", - "LIOB_NE4BEG2_0", - "IOB_O_OUT1", - "LIOB_EE4C1_1", - "LIOB_NW4END1_1", - "IOB_O0", - "LIOB_NE4C2_1", - "LIOB_EE4BEG0_1", - "LIOB_WW2END1_0", - "LIOB_SW2A1_1", - "LIOB_WW4A3_0", - "IOB_DIFFO_OUT0", - "LIOB_NE4C1_0", - "LIOB_LH2_1", - "LIOB_SE4BEG2_0", - "LIOB_WW2END2_0", - "LIOB_LH9_1", - "LIOB_EE4BEG2_1", - "LIOB_SW4END2_1", - "IOB_T0", - "LIOB_SW4A3_0", - "LIOB_NE4C1_1", - "LIOB_EE4C0_1", - "LIOB_WL1END2_1", - "IOB_PADOUT0", - "LIOB_WW4C0_1", - "IOB_O_IN0", - "LIOB_SW4END3_0", - "LIOB_WL1END1_0", - "IOB_T1", - "LIOB_WW2A2_1", - "LIOB_NE2A3_0", - "LIOB_EE4A2_0", - "LIOB_SW4A2_1", - "IOB_DIFFO_IN0", - "LIOB_EE2A3_0", - "LIOB_EE2A1_0", - "LIOB_SW2A3_1", - "LIOB_EE4A3_1", - "IOB_T_IN0", - "LIOB_NW2A2_0", - "LIOB_SW4A2_0", - "LIOB_WL1END0_0", - "LIOB_SW4A3_1", - "LIOB_EE4B0_0", - "LIOB_NE4BEG1_1", - "LIOB_LH4_0", - "LIOB_SW4END1_0", - "LIOB_WR1END2_0", - "LIOB_WW2A2_0", - "LIOB_SW4A1_1", - "LIOB_NE2A0_1", - "LIOB_WL1END0_1", - "LIOB_WL1END3_1", - "LIOB_EE4C3_0", - "IOB_DIFFO_IN1", - "LIOB_WW4C3_0", - "IOB_DIFFI_IN0", - "LIOB_WW2END3_0", - "LIOB_WR1END1_0", - "LIOB_SE4C0_0", - "LIOB_SE2A2_1", - "LIOB_WW4B0_1", - "LIOB_SE4BEG2_1", - "LIOB_EE4BEG1_1", - "LIOB_WW2END1_1", - "LIOB_LH3_1", - "LIOB_EE2A1_1", - "IOB_O_OUT0", - "LIOB_SW4END0_0", - "LIOB_WR1END0_1", - "LIOB_SE2A1_1", - "LIOB_WW4B3_0", - "LIOB_SE4BEG1_1", - "LIOB_WW4END2_1", - "LIOB_NW2A3_0", - "IOB_PU_INT_EN_0", - "LIOB_EE2BEG2_0", - "LIOB_NE4C3_1", - "IOB_PD_INT_EN_1", - "LIOB_NE2A2_1", - "LIOB_SW2A2_0", - "LIOB_LH5_0", - "LIOB_MONITOR_P", - "LIOB_EE4C2_0", - "LIOB_WR1END0_0", - "LIOB_EE4B3_0", - "LIOB_ER1BEG2_0", - "LIOB_EL1BEG3_0", - "LIOB_WW4A1_1", - "LIOB_WW2A3_1", - "LIOB_SW2A0_0", - "LIOB_SW4END3_1", - "IOB_O_IN1", - "LIOB_LH1_0", - "LIOB_NW4END2_1", - "LIOB_NW2A1_1", - "IOB_T_OUT1", - "LIOB_WW4B3_1", - "LIOB_EE2A2_1", - "LIOB_EE2BEG0_1", - "LIOB_EE2A3_1", - "LIOB_EE4BEG3_1", - "LIOB_NW2A1_0", - "IOB_DIFF_TERM_INT_EN", - "LIOB_LH8_0", - "LIOB_EE4B2_0", - "LIOB_WW4END3_0", - "LIOB_WW4B1_1", - "IOB_PU_INT_EN_1", - "LIOB_SW4A1_0", - "LIOB_LH12_0", - "LIOB_WW4END0_0", - "LIOB_WW4A2_0", - "LIOB_EE2BEG1_1", - "LIOB_WW4A1_0", - "LIOB_ER1BEG0_1", - "LIOB_WW4C3_1", - "LIOB_EE4B2_1", - "LIOB_WW4C0_0", - "LIOB_SE2A0_1", - "LIOB_WW2END2_1", - "IOB_PD_INT_EN_0", - "LIOB_LH12_1", - "LIOB_LH9_0", - "LIOB_EE2A0_1", - "LIOB_EE4A1_1", - "LIOB_WW4A3_1", - "LIOB_WL1END2_0", - "LIOB_NE2A0_0", - "LIOB_NE2A2_0", - "LIOB_ER1BEG2_1", - "IOB_IBUF_DISABLE0", - "LIOB_LH3_0", - "LIOB_WW4END1_1", - "LIOB_SE4C0_1", - "LIOB_EE4BEG0_0", - "LIOB_WW2END3_1", - "LIOB_LH7_0", - "LIOB_NW4A2_0", - "LIOB_NE4BEG0_1", - "LIOB_NW4END0_1", - "LIOB_EE4BEG2_0", - "LIOB_WR1END3_1", - "LIOB_LH8_1", - "LIOB_WW4A0_0", - "LIOB_NE4BEG2_1", - "LIOB_NW4A0_1", - "LIOB_EE2BEG2_1", - "LIOB_WW2A3_0", - "LIOB_NW4END3_1", - "LIOB_SE4BEG1_0", - "LIOB_SE4BEG3_1", - "LIOB_SW4END1_1", - "LIOB_EL1BEG2_0", - "LIOB_EE4C3_1", - "LIOB_WW4B0_0" - ], - "sites": [ - { - "prefix": "IOB", - "y_coord": 0, - "type": "IOB33S", - "site_pins": { - "O": "IOB_O1", - "O_IN": "IOB_O_IN1", - "O_OUT": "IOB_O_OUT1", - "DIFFI_IN": "IOB_DIFFI_IN1", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_0", - "PADOUT": "IOB_PADOUT1", - "T_IN": "IOB_T_IN1", - "PU_INT_EN": "IOB_PU_INT_EN_0", - "IBUFDISABLE": "IOB_IBUF_DISABLE1", - "I": "IOB_IBUF1", - "DIFFO_OUT": "IOB_DIFFO_OUT1", - "T": "IOB_T1", - "T_OUT": "IOB_T_OUT1", - "INTERMDISABLE": "LIOB_IN_TERM1", - "PD_INT_EN": "IOB_PD_INT_EN_0", - "DIFFO_IN": "IOB_DIFFO_IN1", - "DIFF_TERM_INT_EN": "IOB_DIFF_TERM_INT_EN" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IOB", - "y_coord": 1, - "type": "IOB33M", - "site_pins": { - "O": "IOB_O0", - "O_IN": null, - "O_OUT": "IOB_O_OUT0", - "DIFFI_IN": "IOB_DIFFI_IN0", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "PADOUT": "IOB_PADOUT0", - "T_IN": null, - "PU_INT_EN": "IOB_PU_INT_EN_1", - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "I": "IOB_IBUF0", - "DIFFO_OUT": "IOB_DIFFO_OUT0", - "T": "IOB_T0", - "T_OUT": "IOB_T_OUT0", - "INTERMDISABLE": "LIOB_IN_TERM0", - "PD_INT_EN": "IOB_PD_INT_EN_1", - "DIFFO_IN": null, - "DIFF_TERM_INT_EN": null - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "LIOB33.IOB_PADOUT1->IOB_DIFFI_IN0": { + "LIOB33.IOB_O_OUT0->IOB_O_IN1": { + "src_wire": "IOB_O_OUT0", "can_invert": "0", - "dst_wire": "IOB_DIFFI_IN0", "is_directional": "1", - "src_wire": "IOB_PADOUT1", - "is_pseudo": "0" - }, - "LIOB33.IOB_O0->>IOB_O_OUT0": { - "can_invert": "0", - "dst_wire": "IOB_O_OUT0", - "is_directional": "1", - "src_wire": "IOB_O0", - "is_pseudo": "1" - }, - "LIOB33.IOB_PADOUT0->LIOB_MONITOR_P": { - "can_invert": "0", - "dst_wire": "LIOB_MONITOR_P", - "is_directional": "1", - "src_wire": "IOB_PADOUT0", - "is_pseudo": "0" - }, - "LIOB33.IOB_DIFFO_IN1->>IOB_PADOUT1": { - "can_invert": "0", - "dst_wire": "IOB_PADOUT1", - "is_directional": "1", - "src_wire": "IOB_DIFFO_IN1", - "is_pseudo": "1" - }, - "LIOB33.IOB_DIFFO_OUT0->IOB_DIFFO_IN1": { - "can_invert": "0", - "dst_wire": "IOB_DIFFO_IN1", - "is_directional": "1", - "src_wire": "IOB_DIFFO_OUT0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOB_O_IN1" }, "LIOB33.IOB_PADOUT1->LIOB_MONITOR_N": { - "can_invert": "0", - "dst_wire": "LIOB_MONITOR_N", - "is_directional": "1", "src_wire": "IOB_PADOUT1", - "is_pseudo": "0" - }, - "LIOB33.IOB_T0->>IOB_T_OUT0": { "can_invert": "0", - "dst_wire": "IOB_T_OUT0", "is_directional": "1", - "src_wire": "IOB_T0", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "LIOB_MONITOR_N" }, - "LIOB33.IOB_O_OUT0->IOB_O_IN1": { + "LIOB33.IOB_O0->>IOB_O_OUT0": { + "src_wire": "IOB_O0", "can_invert": "0", - "dst_wire": "IOB_O_IN1", "is_directional": "1", - "src_wire": "IOB_O_OUT0", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "IOB_O_OUT0" + }, + "LIOB33.IOB_PADOUT0->LIOB_MONITOR_P": { + "src_wire": "IOB_PADOUT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOB_MONITOR_P" }, "LIOB33.IOB_T_OUT0->IOB_T_IN1": { - "can_invert": "0", - "dst_wire": "IOB_T_IN1", - "is_directional": "1", "src_wire": "IOB_T_OUT0", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOB_T_IN1" + }, + "LIOB33.IOB_DIFFO_IN1->>IOB_PADOUT1": { + "src_wire": "IOB_DIFFO_IN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOB_PADOUT1" + }, + "LIOB33.IOB_PADOUT1->IOB_DIFFI_IN0": { + "src_wire": "IOB_PADOUT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFI_IN0" }, "LIOB33.IOB_PADOUT0->IOB_DIFFI_IN1": { - "can_invert": "0", - "dst_wire": "IOB_DIFFI_IN1", - "is_directional": "1", "src_wire": "IOB_PADOUT0", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFI_IN1" + }, + "LIOB33.IOB_DIFFO_OUT0->IOB_DIFFO_IN1": { + "src_wire": "IOB_DIFFO_OUT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFO_IN1" + }, + "LIOB33.IOB_T0->>IOB_T_OUT0": { + "src_wire": "IOB_T0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOB_T_OUT0" } }, - "tile_type": "LIOB33" + "wires": [ + "IOB_DIFFO_OUT0", + "LIOB_LH3_1", + "LIOB_ER1BEG2_0", + "LIOB_NW4A0_1", + "LIOB_WW4B3_0", + "IOB_DIFFI_IN1", + "LIOB_WW4B1_0", + "LIOB_SE2A3_1", + "LIOB_SW2A2_0", + "LIOB_WW2A3_1", + "LIOB_EL1BEG2_1", + "IOB_DIFFO_IN1", + "LIOB_EL1BEG2_0", + "LIOB_NW4A2_1", + "LIOB_EE2A0_0", + "LIOB_NE4BEG1_0", + "LIOB_ER1BEG3_0", + "IOB_O_IN1", + "LIOB_EE4A2_0", + "LIOB_SW4A0_1", + "LIOB_NE2A3_0", + "LIOB_EE4A0_0", + "LIOB_NW4END0_0", + "LIOB_SE2A0_0", + "LIOB_EE2A0_1", + "LIOB_SE4BEG0_0", + "LIOB_SW2A3_1", + "IOB_IBUF0", + "LIOB_WW2A1_1", + "LIOB_LH9_1", + "IOB_IBUF_DISABLE0", + "LIOB_NE4BEG0_1", + "LIOB_WW4A2_1", + "LIOB_NE4C2_1", + "LIOB_EE4A1_0", + "LIOB_SW2A0_0", + "LIOB_NW2A0_0", + "LIOB_WW2A2_0", + "LIOB_SW4END3_1", + "LIOB_WW4A1_1", + "LIOB_EE2A3_0", + "LIOB_LH12_1", + "LIOB_NE2A2_1", + "LIOB_WW4C0_1", + "LIOB_EE4A3_0", + "LIOB_EE4B2_1", + "LIOB_SW2A1_0", + "LIOB_EE4B1_1", + "LIOB_ER1BEG2_1", + "LIOB_EE2BEG3_0", + "LIOB_WR1END0_1", + "LIOB_WW2A0_1", + "LIOB_NW4A3_0", + "LIOB_EL1BEG3_0", + "LIOB_EE4C3_1", + "IOB_O_OUT0", + "LIOB_SW2A2_1", + "LIOB_EE4C0_0", + "IOB_DIFFO_OUT1", + "LIOB_EE4B1_0", + "LIOB_EL1BEG3_1", + "IOB_DIFF_TERM_INT_EN_STUB", + "LIOB_SE4C3_0", + "LIOB_NW4A2_0", + "LIOB_MONITOR_N", + "LIOB_SW2A3_0", + "LIOB_EL1BEG0_1", + "LIOB_WW4A2_0", + "LIOB_LH6_1", + "IOB_IBUF1", + "LIOB_NE4C3_0", + "LIOB_NE4C0_0", + "LIOB_SE2A1_0", + "LIOB_EE4A3_1", + "LIOB_NE4C1_1", + "LIOB_EE4BEG1_1", + "LIOB_SE4BEG1_1", + "LIOB_NW4A1_1", + "LIOB_NW2A2_0", + "LIOB_NE2A2_0", + "LIOB_LH2_1", + "LIOB_SW4A3_1", + "LIOB_SW4A1_1", + "LIOB_ER1BEG0_0", + "LIOB_EE4BEG0_0", + "LIOB_LH2_0", + "LIOB_EE4B0_0", + "LIOB_LH6_0", + "LIOB_WW4B2_1", + "LIOB_SE2A0_1", + "LIOB_NE4BEG2_0", + "LIOB_SE4BEG3_1", + "IOB_DIFF_TERM_INT_EN", + "LIOB_WW2END0_0", + "LIOB_EE4B3_0", + "LIOB_EL1BEG1_0", + "LIOB_NE4BEG2_1", + "LIOB_EE4B3_1", + "LIOB_EE4BEG0_1", + "LIOB_EE4C1_0", + "LIOB_EE4C2_0", + "LIOB_WW2A1_0", + "LIOB_EE4BEG2_0", + "LIOB_NE4BEG1_1", + "LIOB_EE4BEG3_0", + "LIOB_NE4C3_1", + "IOB_PD_INT_EN_0", + "LIOB_SW4END3_0", + "LIOB_SE4C1_0", + "LIOB_WW4C1_1", + "LIOB_WW2END2_1", + "LIOB_WW4A1_0", + "LIOB_EE4B2_0", + "LIOB_WW4C1_0", + "IOB_KEEPER_INT_EN_0", + "LIOB_SE4BEG2_0", + "LIOB_LH8_1", + "LIOB_LH11_0", + "LIOB_SE4BEG2_1", + "LIOB_IN_TERM0", + "LIOB_EE4C3_0", + "LIOB_EE2BEG0_0", + "LIOB_WW4END3_0", + "LIOB_WW2A0_0", + "LIOB_LH10_1", + "LIOB_EE2BEG2_0", + "LIOB_SE4C3_1", + "LIOB_SE4BEG0_1", + "LIOB_SW4END1_1", + "LIOB_WW4B1_1", + "LIOB_WW2A2_1", + "LIOB_WW4A3_0", + "LIOB_SE4BEG1_0", + "LIOB_EE4BEG2_1", + "LIOB_NE2A3_1", + "LIOB_NW4A3_1", + "LIOB_WL1END0_1", + "IOB_T_IN1", + "LIOB_WR1END1_0", + "LIOB_WW4C2_1", + "LIOB_WR1END3_1", + "LIOB_WW4C3_1", + "LIOB_WW2END3_1", + "LIOB_WW4END2_0", + "IOB_KEEPER_INT_EN_1", + "LIOB_NW2A3_0", + "LIOB_NE2A0_1", + "LIOB_WW4END1_0", + "LIOB_NW4END2_0", + "LIOB_SW4A2_0", + "LIOB_SE4C0_1", + "LIOB_WW4C0_0", + "LIOB_NE4C0_1", + "LIOB_NE4C2_0", + "LIOB_NW4END0_1", + "LIOB_WR1END3_0", + "LIOB_EE2A1_1", + "LIOB_ER1BEG3_1", + "IOB_T_OUT0", + "LIOB_WW4END2_1", + "IOB_DIFFI_IN0", + "LIOB_LH12_0", + "LIOB_NE4BEG0_0", + "LIOB_WW4B0_0", + "LIOB_WW4B2_0", + "LIOB_LH3_0", + "LIOB_LH7_1", + "LIOB_EE2BEG1_0", + "LIOB_NE2A1_0", + "LIOB_SW2A0_1", + "LIOB_NW4END3_0", + "LIOB_EL1BEG1_1", + "LIOB_EE4A2_1", + "LIOB_SE2A1_1", + "IOB_PU_INT_EN_0", + "LIOB_SE4C2_0", + "LIOB_EE2BEG3_1", + "IOB_T1", + "LIOB_WW4END0_1", + "LIOB_EE4C1_1", + "LIOB_WW4END0_0", + "LIOB_NE4BEG3_1", + "LIOB_NW4END2_1", + "LIOB_WW4A0_1", + "LIOB_ER1BEG1_1", + "LIOB_WW2END1_0", + "LIOB_LH1_0", + "LIOB_EE2A3_1", + "LIOB_WW4A3_1", + "LIOB_WW2A3_0", + "LIOB_NW4A1_0", + "LIOB_NE4BEG3_0", + "LIOB_LH8_0", + "LIOB_SE4BEG3_0", + "LIOB_NE2A1_1", + "LIOB_SW4A2_1", + "LIOB_LH9_0", + "LIOB_SE2A3_0", + "LIOB_WW4B3_1", + "LIOB_NW4END1_0", + "IOB_IBUF_DISABLE1", + "LIOB_WL1END1_0", + "LIOB_SW4END0_1", + "LIOB_NW2A1_1", + "LIOB_NE2A0_0", + "LIOB_SE4C2_1", + "LIOB_WW4C3_0", + "LIOB_WW4A0_0", + "LIOB_LH5_0", + "IOB_O_OUT1", + "LIOB_EE4A0_1", + "LIOB_EL1BEG0_0", + "LIOB_EE4C0_1", + "LIOB_SW4END2_0", + "LIOB_WW4C2_0", + "LIOB_SW4END2_1", + "LIOB_NW4END1_1", + "LIOB_EE2A2_1", + "LIOB_ER1BEG0_1", + "IOB_O0", + "IOB_T0", + "LIOB_WW4END3_1", + "LIOB_WW2END2_0", + "LIOB_WW2END1_1", + "LIOB_SW4END1_0", + "LIOB_LH4_0", + "LIOB_WW2END3_0", + "LIOB_MONITOR_P", + "LIOB_WL1END0_0", + "LIOB_EE4B0_1", + "LIOB_WL1END1_1", + "LIOB_SE4C1_1", + "LIOB_SE2A2_1", + "IOB_PD_INT_EN_1", + "LIOB_SW4A0_0", + "LIOB_NW2A3_1", + "LIOB_LH7_0", + "LIOB_LH4_1", + "LIOB_EE4BEG1_0", + "LIOB_IN_TERM1", + "IOB_T_IN0", + "LIOB_EE4BEG3_1", + "LIOB_WW4B0_1", + "LIOB_WR1END2_0", + "LIOB_EE2A1_0", + "LIOB_WW2END0_1", + "LIOB_WR1END0_0", + "LIOB_WL1END2_0", + "IOB_DIFFO_IN0", + "LIOB_WL1END3_1", + "LIOB_EE2BEG1_1", + "IOB_PU_INT_EN_1", + "LIOB_SW4A1_0", + "LIOB_SW4A3_0", + "LIOB_ER1BEG1_0", + "IOB_O_IN0", + "LIOB_EE4A1_1", + "LIOB_LH5_1", + "LIOB_EE2A2_0", + "LIOB_WL1END2_1", + "LIOB_NE4C1_0", + "IOB_PADOUT0", + "LIOB_NW2A1_0", + "LIOB_NW2A2_1", + "LIOB_WL1END3_0", + "LIOB_EE2BEG0_1", + "LIOB_SE2A2_0", + "LIOB_WW4END1_1", + "LIOB_SW4END0_0", + "LIOB_EE4C2_1", + "LIOB_NW4A0_0", + "LIOB_EE2BEG2_1", + "IOB_O1", + "LIOB_SW2A1_1", + "LIOB_NW4END3_1", + "LIOB_LH10_0", + "LIOB_WR1END2_1", + "LIOB_LH11_1", + "LIOB_NW2A0_1", + "LIOB_WR1END1_1", + "LIOB_LH1_1", + "LIOB_SE4C0_0", + "IOB_PADOUT1", + "IOB_T_OUT1" + ], + "tile_type": "LIOB33", + "sites": [ + { + "site_pins": { + "I": "IOB_IBUF1", + "DIFFO_OUT": "IOB_DIFFO_OUT1", + "INTERMDISABLE": "LIOB_IN_TERM1", + "DIFF_TERM_INT_EN": "IOB_DIFF_TERM_INT_EN", + "T": "IOB_T1", + "O_IN": "IOB_O_IN1", + "DIFFO_IN": "IOB_DIFFO_IN1", + "DIFFI_IN": "IOB_DIFFI_IN1", + "PD_INT_EN": "IOB_PD_INT_EN_0", + "IBUFDISABLE": "IOB_IBUF_DISABLE1", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_0", + "T_OUT": "IOB_T_OUT1", + "PADOUT": "IOB_PADOUT1", + "PU_INT_EN": "IOB_PU_INT_EN_0", + "O_OUT": "IOB_O_OUT1", + "O": "IOB_O1", + "T_IN": "IOB_T_IN1" + }, + "type": "IOB33S", + "prefix": "IOB", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "I": "IOB_IBUF0", + "DIFFO_OUT": "IOB_DIFFO_OUT0", + "INTERMDISABLE": "LIOB_IN_TERM0", + "DIFF_TERM_INT_EN": null, + "T": "IOB_T0", + "O_IN": null, + "DIFFO_IN": null, + "DIFFI_IN": "IOB_DIFFI_IN0", + "PD_INT_EN": "IOB_PD_INT_EN_1", + "IBUFDISABLE": "IOB_IBUF_DISABLE0", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", + "T_OUT": "IOB_T_OUT0", + "PADOUT": "IOB_PADOUT0", + "PU_INT_EN": "IOB_PU_INT_EN_1", + "O_OUT": "IOB_O_OUT0", + "O": "IOB_O0", + "T_IN": null + }, + "type": "IOB33M", + "prefix": "IOB", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_LIOB33_SING.json b/artix7/tile_type_LIOB33_SING.json index ddaf1ae..675eead 100644 --- a/artix7/tile_type_LIOB33_SING.json +++ b/artix7/tile_type_LIOB33_SING.json @@ -1,175 +1,175 @@ { + "pips": {}, "wires": [ - "LIOB_LH6_0", - "IOB_T0", - "LIOB_SW4A3_0", - "LIOB_LH2_0", - "IOB_PADOUT0", - "LIOB_SW4A0_0", - "LIOB_SE4BEG3_0", - "IOB_O_IN0", - "LIOB_SW4END3_0", - "LIOB_WL1END1_0", - "LIOB_NE2A3_0", - "LIOB_EE4A2_0", - "LIOB_NE4BEG3_0", - "IOB_DIFFO_IN0", - "LIOB_EE2A3_0", - "LIOB_EE2A1_0", - "IOB_KEEPER_INT_EN_1", - "LIOB_WW4C1_0", - "IOB_T_IN0", - "LIOB_NW2A2_0", - "LIOB_SW4END2_0", - "LIOB_SW4A2_0", - "LIOB_WW4END2_0", - "LIOB_NW4END1_0", - "LIOB_NW4END2_0", - "LIOB_WL1END0_0", - "LIOB_EE4BEG1_0", - "LIOB_EE4B0_0", - "LIOB_WR1END3_0", - "LIOB_LH4_0", - "LIOB_SW4END1_0", - "LIOB_LH11_0", - "LIOB_WR1END2_0", - "LIOB_WW2A2_0", - "LIOB_EE2A0_0", - "LIOB_EE2A2_0", - "LIOB_EE4A0_0", - "LIOB_EE4C3_0", - "LIOB_NW2A0_0", - "LIOB_WW2A1_0", - "LIOB_WW4C3_0", - "LIOB_SE4C2_0", - "IOB_DIFF_TERM_INT_EN_STUB", - "LIOB_WL1END3_0", - "IOB_DIFFI_IN0", - "LIOB_NW4END3_0", - "LIOB_WW2END3_0", - "LIOB_SE4C0_0", - "LIOB_WR1END1_0", - "LIOB_EE4C0_0", - "IOB_T_OUT0", - "LIOB_EE2BEG3_0", - "LIOB_WW4END1_0", - "LIOB_EL1BEG1_0", - "LIOB_SE2A1_0", - "IOB_O_OUT0", - "IOB_IBUF0", - "LIOB_SW4END0_0", - "LIOB_NW4A1_0", - "LIOB_WW4B3_0", - "LIOB_WW4B2_0", - "LIOB_NW2A3_0", - "LIOB_EL1BEG0_0", - "LIOB_EE2BEG2_0", - "LIOB_EE4BEG3_0", - "LIOB_NE4C2_0", - "IOB_PD_INT_EN_1", - "LIOB_SW2A2_0", - "LIOB_LH5_0", - "LIOB_EE4B1_0", - "LIOB_EE4C2_0", - "LIOB_NW4A3_0", - "LIOB_WR1END0_0", - "LIOB_EE4B3_0", - "LIOB_NW4A0_0", - "LIOB_SE2A2_0", + "IOB_DIFFO_OUT0", "LIOB_ER1BEG2_0", - "LIOB_EE2BEG1_0", - "LIOB_EL1BEG3_0", - "LIOB_SW2A3_0", - "LIOB_SE4C3_0", - "LIOB_SW2A0_0", + "LIOB_WW4B3_0", + "LIOB_WW4B1_0", + "LIOB_WW4A3_0", + "LIOB_SE4BEG1_0", + "LIOB_SW2A2_0", + "LIOB_WR1END1_0", + "LIOB_WW4END2_0", + "LIOB_NW2A3_0", + "IOB_KEEPER_INT_EN_1", + "LIOB_WW4END1_0", + "LIOB_NW4END2_0", + "LIOB_SW4A2_0", + "LIOB_WW4C0_0", + "LIOB_EL1BEG2_0", + "LIOB_NE4C2_0", + "LIOB_WR1END3_0", + "LIOB_EE2A0_0", "LIOB_NE4BEG1_0", - "LIOB_WW2END0_0", - "LIOB_IN_TERM0", - "LIOB_LH1_0", - "LIOB_EE2BEG0_0", - "LIOB_SE4BEG0_0", - "LIOB_LH10_0", - "LIOB_NE2A1_0", - "LIOB_NW2A1_0", - "LIOB_LH8_0", - "LIOB_WW4C2_0", - "LIOB_EE4B2_0", - "LIOB_NE4C0_0", - "LIOB_WW4END3_0", - "LIOB_SE2A0_0", - "LIOB_NE4C3_0", - "IOB_PU_INT_EN_1", - "LIOB_SE4C1_0", - "LIOB_EE4C1_0", - "LIOB_SE2A3_0", - "LIOB_SW4A1_0", - "LIOB_WW2A0_0", - "LIOB_EE4A3_0", + "LIOB_ER1BEG3_0", + "IOB_T_OUT0", + "LIOB_EE4A2_0", + "IOB_DIFFI_IN0", + "LIOB_NE2A3_0", + "LIOB_WW4B0_0", + "LIOB_EE4A0_0", "LIOB_NE4BEG0_0", "LIOB_LH12_0", - "LIOB_WW4END0_0", - "LIOB_WW4A2_0", - "LIOB_WW4A1_0", - "LIOB_WW4C0_0", - "LIOB_ER1BEG3_0", "LIOB_NW4END0_0", - "LIOB_ER1BEG0_0", - "LIOB_WW4B1_0", - "LIOB_ER1BEG1_0", - "LIOB_EE4A1_0", - "LIOB_SW2A1_0", - "LIOB_NE4BEG2_0", - "IOB_O0", - "LIOB_LH9_0", - "LIOB_WL1END2_0", - "LIOB_NE2A0_0", - "LIOB_NE2A2_0", - "IOB_IBUF_DISABLE0", - "LIOB_WW2END1_0", + "LIOB_WW4B2_0", + "LIOB_SE2A0_0", "LIOB_LH3_0", - "LIOB_EE4BEG0_0", - "LIOB_LH7_0", - "LIOB_NW4A2_0", - "LIOB_WW4A3_0", - "LIOB_EE4BEG2_0", - "IOB_DIFFO_OUT0", - "LIOB_NE4C1_0", - "LIOB_WW4A0_0", - "LIOB_SE4BEG2_0", + "LIOB_SE4BEG0_0", + "LIOB_EE2BEG1_0", + "LIOB_NE2A1_0", + "IOB_IBUF0", + "LIOB_NW4END3_0", + "LIOB_SE4C2_0", + "IOB_IBUF_DISABLE0", + "LIOB_WW4END0_0", + "LIOB_WW2END1_0", + "LIOB_LH1_0", + "LIOB_EE4A1_0", + "LIOB_SW2A0_0", "LIOB_WW2A3_0", - "LIOB_SE4BEG1_0", + "LIOB_NW2A0_0", + "LIOB_NW4A1_0", + "LIOB_WW2A2_0", + "LIOB_NE4BEG3_0", + "LIOB_LH8_0", + "LIOB_SE4BEG3_0", + "LIOB_LH9_0", + "LIOB_SE2A3_0", + "LIOB_NW4END1_0", + "LIOB_WL1END1_0", + "LIOB_NE2A0_0", + "LIOB_EE2A3_0", + "LIOB_WW4C3_0", + "LIOB_WW4A0_0", + "LIOB_EE4A3_0", + "LIOB_LH5_0", + "LIOB_EL1BEG0_0", + "LIOB_SW4END2_0", + "LIOB_WW4C2_0", + "LIOB_SW2A1_0", + "IOB_O0", + "IOB_T0", + "LIOB_EE2BEG3_0", "LIOB_WW2END2_0", - "LIOB_EL1BEG2_0", - "LIOB_WW4B0_0" + "LIOB_SW4END1_0", + "LIOB_LH4_0", + "LIOB_WW2END3_0", + "LIOB_NW4A3_0", + "LIOB_EL1BEG3_0", + "IOB_O_OUT0", + "LIOB_WL1END0_0", + "IOB_PD_INT_EN_1", + "LIOB_SW4A0_0", + "LIOB_EE4C0_0", + "LIOB_EE4B1_0", + "LIOB_LH7_0", + "IOB_DIFF_TERM_INT_EN_STUB", + "LIOB_SE4C3_0", + "LIOB_EE4BEG1_0", + "LIOB_NW4A2_0", + "IOB_T_IN0", + "LIOB_SW2A3_0", + "LIOB_WW4A2_0", + "LIOB_WR1END2_0", + "LIOB_NE4C3_0", + "LIOB_EE2A1_0", + "LIOB_NE4C0_0", + "LIOB_SE2A1_0", + "LIOB_WR1END0_0", + "LIOB_WL1END2_0", + "IOB_DIFFO_IN0", + "IOB_PU_INT_EN_1", + "LIOB_SW4A1_0", + "LIOB_SW4A3_0", + "LIOB_NW2A2_0", + "LIOB_ER1BEG1_0", + "IOB_O_IN0", + "LIOB_NE2A2_0", + "LIOB_ER1BEG0_0", + "LIOB_EE4BEG0_0", + "LIOB_LH6_0", + "LIOB_EE4B0_0", + "LIOB_LH2_0", + "LIOB_EE2A2_0", + "LIOB_NE4BEG2_0", + "LIOB_NE4C1_0", + "IOB_PADOUT0", + "LIOB_NW2A1_0", + "LIOB_WW2END0_0", + "LIOB_EL1BEG1_0", + "LIOB_WL1END3_0", + "LIOB_EE4B3_0", + "LIOB_SE2A2_0", + "LIOB_SW4END0_0", + "LIOB_EE4C1_0", + "LIOB_EE4C2_0", + "LIOB_WW2A1_0", + "LIOB_EE4BEG2_0", + "LIOB_NW4A0_0", + "LIOB_LH10_0", + "LIOB_EE4BEG3_0", + "LIOB_SW4END3_0", + "LIOB_SE4C1_0", + "LIOB_EE4B2_0", + "LIOB_WW4A1_0", + "LIOB_WW4C1_0", + "LIOB_SE4BEG2_0", + "LIOB_LH11_0", + "LIOB_IN_TERM0", + "LIOB_EE4C3_0", + "LIOB_EE2BEG0_0", + "LIOB_SE4C0_0", + "LIOB_WW4END3_0", + "LIOB_WW2A0_0", + "LIOB_EE2BEG2_0" ], + "tile_type": "LIOB33_SING", "sites": [ { - "prefix": "IOB", - "y_coord": 0, - "type": "IOB33", "site_pins": { - "DIFFI_IN": null, - "DIFFO_OUT": "IOB_DIFFO_OUT0", - "PADOUT": "IOB_PADOUT0", - "T_IN": null, - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "O_OUT": "IOB_O_OUT0", - "T": "IOB_T0", - "O": "IOB_O0", - "O_IN": null, - "DIFFO_IN": null, - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "T_OUT": "IOB_T_OUT0", - "PU_INT_EN": "IOB_PU_INT_EN_1", "I": "IOB_IBUF0", "DIFF_TERM_INT_EN": null, + "T": "IOB_T0", + "O_IN": null, + "PU_INT_EN": "IOB_PU_INT_EN_1", + "DIFFI_IN": null, "PD_INT_EN": "IOB_PD_INT_EN_1", - "INTERMDISABLE": "LIOB_IN_TERM0" + "PADOUT": "IOB_PADOUT0", + "DIFFO_IN": null, + "O": "IOB_O0", + "INTERMDISABLE": "LIOB_IN_TERM0", + "O_OUT": "IOB_O_OUT0", + "T_IN": null, + "IBUFDISABLE": "IOB_IBUF_DISABLE0", + "T_OUT": "IOB_T_OUT0", + "DIFFO_OUT": "IOB_DIFFO_OUT0", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1" }, + "type": "IOB33", + "prefix": "IOB", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 } - ], - "pips": {}, - "tile_type": "LIOB33_SING" + ] } \ No newline at end of file diff --git a/artix7/tile_type_LIOI3.json b/artix7/tile_type_LIOI3.json index f191d30..e5a1388 100644 --- a/artix7/tile_type_LIOI3.json +++ b/artix7/tile_type_LIOI3.json @@ -1,3928 +1,3928 @@ { - "wires": [ - "IOI_LOGIC_OUTS17_1", - "IOI_WW2END3_1", - "IOI_SE4BEG2_0", - "IOI_NW4A2_0", - "IOI_NW4END1_0", - "IOI_IMUX21_1", - "IOI_WR1END3_0", - "IOI_NE2A2_0", - "IOI_IMUX20_0", - "IOI_EE2BEG2_0", - "IOI_BYP3_1", - "IOI_OLOGIC1_D8", - "LIOI_ILOGIC0_TFB", - "LIOI_OLOGIC0_OFB", - "IOI_CLK1_1", - "IOI_ODELAY0_C", - "IOI_IMUX3_1", - "IOI_WR1END3_1", - "IOI_NW4END1_1", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_WW4END0_1", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_EE2A3_1", - "IOI_OLOGIC1_D6", - "IOI_IMUX9_1", - "IOI_IMUX35_0", - "IOI_BLOCK_OUTS3_1", - "IOI_OLOGIC0_D2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_OLOGIC0_CLKDIV", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_RCLK_DIV_CE2", - "IOI_SW2A2_1", - "IOI_WW4END1_1", - "IOI_ODELAY0_CE", - "IOI_NE2A1_0", - "IOI_IMUX0_0", - "IOI_ER1BEG0_0", - "LIOI_ILOGIC1_TFB", - "IOI_IMUX10_1", - "IOI_ILOGIC0_BITSLIP", - "IOI_NE4C3_0", - "IOI_IMUX10_0", - "IOI_EE4B3_0", - "IOI_IMUX45_1", - "IOI_LH4_0", - "IOI_NW4END2_0", - "IOI_OLOGIC0_SR", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_LH1_0", - "IOI_EE4A1_1", - "LIOI_IBUF_DISABLE1", - "IOI_LOGIC_OUTS2_1", - "IOI_BLOCK_OUTS1_0", - "IOI_WW4B1_0", - "LIOI_KEEPER_INT_EN_1", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_IDELAYCTRL_OUTN1", - "IOI_LH2_0", - "IOI_FAN4_1", - "IOI_IMUX12_1", - "IOI_OLOGIC1_TBYTEIN", - "IOI_IMUX1_1", - "IOI_IMUX8_0", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_CTRL0_0", - "IOI_IDELAY1_INC", - "IOI_IMUX24_1", - "IOI_SW2A2_0", - "IOI_NW4A2_1", - "IOI_LOGIC_OUTS12_1", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_INC", - "IOI_OLOGIC0_T4", - "IOI_ER1BEG1_0", - "LIOI_ISIN21", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_IMUX14_1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_ILOGIC1_Q1", - "IOI_EL1BEG2_0", - "IOI_ILOGIC1_SR", - "LIOI_ODELAY1_OFDLY2", - "IOI_NE4BEG2_0", - "IOI_EL1BEG3_1", - "IOI_SW2A0_0", - "IOI_IMUX36_1", - "IOI_IMUX24_0", - "IOI_NW4END3_1", - "IOI_OLOGIC1_D2", - "IOI_EE4C1_1", - "IOI_LOGIC_OUTS21_0", - "IOI_IMUX4_1", - "IOI_WW4C3_0", - "IOI_OLOGIC0_D7", - "IOI_EE2A1_1", - "IOI_IMUX37_0", - "IOI_IDELAY1_CE", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_WW2A2_0", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_BYP4_1", - "IOI_IMUX42_1", - "IOI_OLOGIC1_TBYTEOUT", - "LIOI3_IDELAY0_IFDLY1", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_IMUX35_1", - "IOI_IMUX30_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LH8_1", - "IOI_IMUX33_0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_EE4BEG3_1", - "IOI_NE2A2_1", - "LIOI_ISIN10", - "IOI_ILOGIC0_Q2", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_BYP7_0", - "IOI_TBYTEIN", - "IOI_IMUX42_0", - "IOI_SW4A2_0", - "IOI_WR1END0_1", - "IOI_WW2A2_1", - "IOI_MONITOR_P", - "IOI_NE4C1_0", - "IOI_IMUX29_0", - "IOI_OCLKM_1", - "IOI_WW4B2_1", - "IOI_OLOGIC0_REV", - "IOI_WW4END3_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LH7_1", - "IOI_NW2A3_1", - "IOI_LH12_1", - "IOI_EE4BEG2_0", - "IOI_LH7_0", - "IOI_ER1BEG3_0", - "IOI_IMUX0_1", - "IOI_LOGIC_OUTS7_1", - "IOI_ILOGIC0_Q3", - "IOI_IDELAY0_LDPIPEEN", - "IOI_WW2END2_0", - "IOI_LH11_1", - "IOI_IDELAY1_CINVCTRL", - "IOI_NW4A3_1", - "IOI_IMUX23_0", - "IOI_IMUX37_1", - "IOI_LOGIC_OUTS3_0", - "LIOI_OLOGIC1_CLKDIVF", - "IOI_WW4A0_0", - "IOI_IOCLK0", - "IOI_WW2END3_0", - "LIOI_IDELAY1_IDATAIN", - "LIOI_OLOGIC1_TFB_LOCAL", - "IOI_NE4BEG3_0", - "IOI_SE2A2_1", - "IOI_LEAF_GCLK0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IMUX18_1", - "IOI_IDELAY0_CE", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_NW4END3_0", - "LIOI_ODELAY1_ODATAIN", - "IOI_WW4C0_1", - "IOI_SE4C3_0", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IMUX39_1", - "IOI_NW4A1_0", - "IOI_NE4BEG2_1", - "IOI_SE4BEG0_0", - "IOI_IMUX14_0", - "IOI_IMUX22_1", - "LIOI_O0", - "IOI_CLK1_0", - "IOI_SE4BEG3_0", - "LIOI_I2GCLK_TOP0", - "IOI_OLOGIC0_D6", - "IOI_WW2A1_1", - "IOI_EE2A3_0", - "IOI_IMUX28_0", - "IOI_OCLK_0", - "IOI_IMUX18_0", - "IOI_NW2A1_1", - "IOI_IDELAY1_C", - "IOI_WW4A2_0", - "IOI_NE4C0_0", - "IOI_NW2A1_0", - "IOI_IMUX2_1", - "IOI_LOGIC_OUTS9_0", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_IMUX16_0", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_BLOCK_OUTS2_1", - "IOI_WL1END3_0", - "IOI_LOGIC_OUTS7_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_IDELAYCTRL_RDY", - "IOI_RCLK_DIV_CLR2", - "IOI_IMUX11_0", - "IOI_LOGIC_OUTS16_1", - "IOI_RCLK_DIV_CE3", - "IOI_WR1END2_0", - "IOI_LOGIC_OUTS18_1", - "IOI_SW4A0_0", - "LIOI_OLOGIC0_TFB", - "IOI_NE4BEG1_1", - "IOI_WR1END1_0", - "IOI_OLOGIC1_CLK", - "IOI_EE4B0_0", - "IOI_WW4A3_1", - "IOI_RCLK_DIV_CLR1", - "IOI_LOGIC_OUTS15_0", - "IOI_WW4B0_0", - "IOI_OLOGIC1_D3", - "IOI_ODELAY1_LD", - "LIOI3_IDELAY1_IFDLY2", - "IOI_NW4END2_1", - "IOI_LOGIC_OUTS10_1", - "LIOI_PU_INT_EN_1", - "IOI_NE2A3_1", - "IOI_NW2A0_0", - "IOI_WW4END3_0", - "IOI_IOCLK3", - "LIOI_I0", - "IOI_SE2A3_0", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_WW2A3_0", - "IOI_ILOGIC0_CE1", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_BYP1_1", - "IOI_SE4C1_1", - "IOI_SW4A3_1", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IMUX38_1", - "IOI_ER1BEG2_0", - "IOI_WW4C0_0", - "IOI_IMUX25_0", - "IOI_NE4BEG0_0", - "IOI_IMUX7_1", - "IOI_FAN3_1", - "IOI_OLOGIC1_SR", - "IOI_SW4END1_0", - "IOI_ILOGIC1_CE2", - "IOI_WW4END0_0", - "IOI_FAN7_0", - "IOI_LOGIC_OUTS1_0", - "LIOI_ILOGIC0_DDLY", - "IOI_EE2BEG0_0", - "IOI_SE4C0_1", - "IOI_OLOGIC1_T3", - "LIOI_ILOGIC0_D", - "IOI_IMUX43_1", - "IOI_EE2BEG3_1", - "IOI_NE4C3_1", - "IOI_IMUX34_1", - "IOI_IMUX46_0", - "IOI_IMUX27_0", - "IOI_DCI_TSTCLK", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_D8", - "IOI_ODELAY1_CNTVALUEOUT2", - "LIOI3_IDELAY1_IFDLY1", - "IOI_EE4C2_0", - "IOI_IMUX11_1", - "IOI_CTRL1_0", - "IOI_DCI_TSTHLP", - "LIOI_OLOGIC0_TQ", - "IOI_EE4A3_0", - "LIOI_ODELAY0_OFDLY2", - "IOI_OLOGIC0_CLKB", - "IOI_WW4C3_1", - "IOI_IMUX40_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_IMUX47_0", - "IOI_OLOGIC1_CLKDIV", - "IOI_LOGIC_OUTS5_1", - "LIOI_I2GCLK_TOP1", - "IOI_BYP7_1", - "IOI_LOGIC_OUTS12_0", - "IOI_SE4BEG0_1", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_LOGIC_OUTS5_0", - "IOI_FAN4_0", - "IOI_WW4B0_1", - "IOI_WL1END0_1", - "IOI_IMUX2_0", - "IOI_WW2END0_0", - "IOI_LH2_1", - "IOI_WW4A1_1", - "IOI_WW4C1_1", - "IOI_ER1BEG2_1", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_OLOGIC0_T1", - "LIOI_I2GCLK_BOT1", - "IOI_IMUX3_0", - "IOI_EE2BEG1_0", - "IOI_IMUX29_1", - "IOI_WW2END0_1", - "IOI_OCLK_1", - "IOI_WW2A0_0", - "IOI_ER1BEG1_1", - "IOI_RCLK_FORIO2", - "IOI_PHASER_TO_IO_ICLK", - "IOI_NE4C2_0", - "IOI_BYP2_1", - "IOI_WR1END1_1", - "IOI_FAN3_0", - "IOI_ILOGIC1_BITSLIP", - "LIOI3_IDELAY0_IFDLY0", - "IOI_ODELAY0_LDPIPEEN", - "IOI_IMUX44_1", - "IOI_NE2A1_1", - "IOI_LOGIC_OUTS1_1", - "IOI_EE4B0_1", - "IOI_OLOGIC1_CLKB", - "LIOI_OLOGIC1_OQ", - "IOI_RCLK_DIV_CLR0", - "IOI_ILOGIC1_CLKDIV", - "IOI_DCI_TSTHLN", - "IOI_OLOGIC1_D5", - "IOI_SW2A3_0", - "IOI_IDELAY1_REGRST", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_LOGIC_OUTS19_0", - "IOI_IMUX32_1", - "LIOI_ISIN11", - "IOI_SE2A1_1", - "IOI_LOGIC_OUTS21_1", - "IOI_EE2A2_0", - "IOI_ODELAY1_REGRST", - "IOI_LH9_0", - "IOI_FAN5_1", - "IOI_LH6_0", - "IOI_ODELAY1_C", - "IOI_IMUX19_0", - "IOI_OLOGIC1_D4", - "IOI_LOGIC_OUTS10_0", - "IOI_ILOGIC0_OCLK", - "LIOI_OLOGIC1_TFB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_INT_DCI_EN", - "IOI_EL1BEG0_1", - "IOI_SW2A1_0", - "IOI_OLOGIC1_D1", - "IOI_DCI_TSTRST0", - "IOI_OLOGIC0_T2", - "IOI_BLOCK_OUTS0_0", - "LIOI_DCI_T_TERM0", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_EE4BEG2_1", - "LIOI_IDELAY1_DATAOUT", - "IOI_SE4BEG3_1", - "LIOI_DIFF_TERM_INT_EN", - "LIOI_ISOUT11", - "IOI_OLOGIC1_T2", - "IOI_WW4A0_1", - "IOI_IMUX26_0", - "IOI_IMUX45_0", - "IOI_MONITOR_N", - "IOI_IMUX8_1", - "IOI_RCLK_DIV_CLR3", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY1_CE", - "LIOI_DCI_T_TERM1", - "IOI_LH6_1", - "IOI_IOCLK1", - "IOI_FAN7_1", - "LIOI_ODELAY0_OFDLY1", - "IOI_RCLK_DIV_CLR0_1", - "IOI_LOGIC_OUTS2_0", - "IOI_WW4A1_0", - "IOI_IMUX7_0", - "LIOI_ODELAY1_OFDLY1", - "IOI_ODELAY1_INC", - "IOI_ILOGIC0_CLK", - "IOI_IMUX20_1", - "IOI_WW2END1_1", - "IOI_LOGIC_OUTS11_0", - "IOI_SE4C0_0", - "IOI_LOGIC_OUTS17_0", - "IOI_ER1BEG3_1", - "IOI_ILOGIC0_CLKDIV", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_REV", - "LIOI_OLOGIC0_CLKDIVF", - "IOI_FAN1_1", - "IOI_LH10_0", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC0_CE2", - "IOI_FAN6_1", - "LIOI_ODELAY0_OFDLY0", - "IOI_IDELAY1_CNTVALUEOUT0", - "LIOI_KEEPER_INT_EN_0", - "LIOI_OSOUT21", - "IOI_IMUX5_0", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_SW4END0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_ILOGIC1_Q5", - "IOI_NE4BEG0_1", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_WW4B3_0", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_EE4BEG0_1", - "IOI_EE2BEG2_1", - "IOI_OLOGIC1_T1", - "IOI_IMUX6_1", - "IOI_EL1BEG2_1", - "IOI_SE4C1_0", - "IOI_NW4END0_1", - "IOI_IMUX1_0", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_REV", - "IOI_SE4C2_1", - "IOI_SE4BEG2_1", - "IOI_EE4A0_1", - "IOI_IMUX36_0", - "IOI_EE2BEG0_1", - "IOI_NW4A0_1", - "IOI_WW4END2_1", - "IOI_IMUX46_1", - "IOI_EE4A3_1", - "IOI_LOGIC_OUTS20_0", - "IOI_WL1END1_1", - "LIOI_OSIN21", - "IOI_SW4END1_1", - "LIOI3_IDELAY1_IFDLY0", - "IOI_IMUX13_1", - "IOI_ODELAY0_LD", - "IOI_ILOGIC1_Q8", - "IOI_IMUX23_1", - "IOI_IMUX_RC3", - "IOI_IMUX31_1", - "IOI_WW4A3_0", - "IOI_OLOGIC0_OCE", - "IOI_LOGIC_OUTS3_1", - "IOI_EE2A2_1", - "IOI_LOGIC_OUTS8_0", - "IOI_ILOGIC0_CLKB", - "IOI_IMUX27_1", - "IOI_NE2A0_1", - "IOI_RCLK_DIV_CE1", - "LIOI_O1", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_NE2A0_0", - "IOI_IDELAY0_REGRST", - "LIOI_OSOUT11", - "LIOI_OLOGIC0_OQ", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_SE4BEG1_1", - "IOI_IMUX_RC2", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_ILOGIC0_O", - "IOI_EE4A1_0", - "IOI_IDELAYCTRL_RST", - "IOI_SW4A1_0", - "IOI_EE4A2_1", - "IOI_LOGIC_OUTS9_1", - "IOI_WW4A2_1", - "IOI_FAN2_1", - "LIOI_OSOUT20", - "IOI_FAN5_0", - "IOI_IMUX16_1", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_IOCLK2", - "IOI_OLOGIC1_D7", - "IOI_IMUX6_0", - "IOI_LOGIC_OUTS4_0", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC1_Q4", - "IOI_NW4END0_0", - "IOI_FAN0_1", - "IOI_BLOCK_OUTS3_0", - "IOI_IMUX38_0", - "IOI_IDELAY0_CINVCTRL", - "LIOI_IBUF_DISABLE0", - "LIOI_OLOGIC0_TFB_LOCAL", - "IOI_OLOGIC1_OCE", - "LIOI_IDELAY0_IDATAIN", - "IOI_EE4A2_0", - "IOI_BLOCK_OUTS0_1", - "IOI_IMUX4_0", - "IOI_OLOGIC1_CLKDIVB", - "LIOI_PD_INT_EN_1", - "IOI_SW4END2_0", - "IOI_BYP0_1", - "IOI_IMUX_RC0", - "IOI_IMUX31_0", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IMUX15_0", - "IOI_EE4C3_0", - "IOI_LOGIC_OUTS11_1", - "IOI_NE4BEG1_0", - "IOI_SW4END2_1", - "IOI_PHASER_TO_IO_ICLKDIV", - "LIOI_OLOGIC1_OFB", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS4_1", - "IOI_WR1END0_0", - "LIOI_OSOUT10", - "LIOI_ILOGIC1_D", - "IOI_IDELAY0_C", - "IOI_SE2A2_0", - "IOI_LOGIC_OUTS13_0", - "IOI_ILOGIC1_OCLK", - "IOI_BYP4_0", - "IOI_WW2A1_0", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_IDELAY0_DATAIN", - "IOI_EE4B2_1", - "IOI_IMUX28_1", - "IOI_LEAF_GCLK5", - "IOI_SW4A3_0", - "IOI_BLOCK_OUTS1_1", - "IOI_WW4C1_0", - "IOI_IMUX9_0", - "IOI_BYP5_0", - "IOI_LOGIC_OUTS18_0", - "IOI_NW4A0_0", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_LH10_1", - "IOI_IMUX12_0", - "IOI_LOGIC_OUTS23_0", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_DCI_DCIDONE", - "IOI_SE2A0_0", - "IOI_IMUX21_0", - "IOI_EE4B1_1", - "IOI_RCLK_DIV_CE3_1", - "IOI_EE4BEG0_0", - "LIOI_ODELAY0_DATAOUT", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ILOGIC1_CLK", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_LOGIC_OUTS14_1", - "IOI_BYP3_0", - "IOI_EE2A0_1", - "IOI_LEAF_GCLK4", - "IOI_SW4A2_1", - "IOI_OLOGIC1_T4", - "IOI_LOGIC_OUTS0_0", - "IOI_WW2END1_0", - "IOI_BYP5_1", - "IOI_ER1BEG0_1", - "IOI_LOGIC_OUTS16_0", - "IOI_IMUX5_1", - "IOI_NW4A3_0", - "IOI_EE4BEG1_1", - "IOI_SW2A1_1", - "IOI_IDELAY0_LD", - "IOI_EE2A0_0", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_CLK0_1", - "IOI_RCLK_FORIO3", - "IOI_IMUX44_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_ILOGIC1_O", - "IOI_SE2A3_1", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ILOGIC1_REV", - "IOI_EE2A1_0", - "IOI_IMUX17_1", - "IOI_FAN1_0", - "IOI_EE4A0_0", - "IOI_LOGIC_OUTS22_0", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_RCLK_DIV_CE0", - "IOI_WW4C2_0", - "IOI_NW2A3_0", - "IOI_IMUX34_0", - "LIOI_ILOGIC0_OFB", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_NE4C2_1", - "IOI_IMUX22_0", - "IOI_OLOGIC0_T3", - "IOI_ODELAY1_CINVCTRL", - "IOI_IMUX17_0", - "LIOI_ISIN20", - "IOI_WW4B2_0", - "IOI_FAN6_0", - "IOI_IDELAY1_LDPIPEEN", - "LIOI_PU_INT_EN_0", - "IOI_WL1END0_0", - "IOI_OCLKM_0", - "IOI_IMUX15_1", - "IOI_CLK0_0", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IMUX25_1", - "IOI_EL1BEG0_0", - "IOI_OLOGIC0_CLK", - "IOI_IMUX39_0", - "IOI_WL1END1_0", - "IOI_WL1END2_0", - "IOI_IMUX41_0", - "IOI_CTRL0_1", - "IOI_EE4C0_0", - "IOI_ILOGIC1_Q6", - "IOI_NW2A0_1", - "IOI_EE2BEG1_1", - "IOI_ILOGIC1_Q2", - "IOI_CTRL1_1", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_OLOGIC0_D4", - "IOI_SE4BEG1_0", - "LIOI_ISOUT20", - "IOI_LOGIC_OUTS15_1", - "IOI_EE2BEG3_0", - "IOI_SW4A1_1", - "IOI_EL1BEG1_0", - "IOI_DCI_TSTRST", - "LIOI_ISOUT21", - "IOI_SW2A3_1", - "IOI_NE4C0_1", - "IOI_ILOGIC1_CLKDIVP", - "IOI_IMUX30_1", - "LIOI_ODELAY0_ODATAIN", - "IOI_ILOGIC0_Q5", - "IOI_IDELAYCTRL_OUTN65", - "IOI_WR1END2_1", - "IOI_WW4B1_1", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_EE4BEG3_0", - "IOI_SE2A0_1", - "IOI_FAN0_0", - "IOI_EE4BEG1_0", - "LIOI_OSIN10", - "IOI_IMUX47_1", - "IOI_LH1_1", - "LIOI_ISOUT10", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC0_OCLKB", - "LIOI_IBUF1", - "IOI_RCLK_DIV_CE2_1", - "IOI_BYP2_0", - "IOI_EE4C1_0", - "LIOI_IBUF0", - "IOI_WW2END2_1", - "IOI_IMUX43_0", - "IOI_BYP6_1", - "IOI_RCLK_FORIO1", - "IOI_ILOGIC1_OCLKB", - "IOI_LEAF_GCLK1", - "IOI_NW2A2_0", - "IOI_IMUX33_1", - "IOI_LH11_0", - "IOI_ILOGIC0_Q6", - "IOI_SW4END3_1", - "IOI_ODELAY1_CLKIN", - "IOI_NW2A2_1", - "IOI_LH9_1", - "LIOI_OLOGIC1_TQ", - "IOI_PHASER_TO_IO_OCLK", - "IOI_EE4B3_1", - "LIOI_OSIN20", - "IOI_WW4B3_1", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_Q3", - "IOI_FAN2_0", - "IOI_WW4C2_1", - "LIOI_I1", - "LIOI_ODELAY1_DATAOUT", - "LIOI_T1", - "IOI_WL1END2_1", - "IOI_RCLK_FORIO0", - "IOI_SW4A0_1", - "IOI_NW4A1_1", - "IOI_IMUX41_1", - "IOI_LOGIC_OUTS13_1", - "LIOI_PD_INT_EN_0", - "IOI_BLOCK_OUTS2_0", - "IOI_WW4END1_0", - "IOI_IMUX40_1", - "IOI_IMUX19_1", - "IOI_EE4B1_0", - "IOI_WL1END3_1", - "IOI_LEAF_GCLK2", - "IOI_ODELAY0_CLKIN", - "IOI_EE4B2_0", - "IOI_SE2A1_0", - "IOI_BYP6_0", - "IOI_IMUX32_0", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_DATAIN", - "IOI_EE4C2_1", - "IOI_LH5_1", - "IOI_ILOGIC0_Q7", - "LIOI_OSIN11", - "IOI_IMUX_RC1", - "IOI_EL1BEG3_0", - "IOI_WW2A3_1", - "IOI_NE4C1_1", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_SW4END3_0", - "LIOI3_IDELAY0_IFDLY2", - "IOI_WW2A0_1", - "LIOI_ILOGIC1_DDLY", - "IOI_NE4BEG3_1", - "IOI_SE4C2_0", - "LIOI_ODELAY1_OFDLY0", - "IOI_ODELAY0_INC", - "IOI_LOGIC_OUTS6_1", - "IOI_BYP1_0", - "IOI_NE2A3_0", - "IOI_ILOGIC1_Q7", - "LIOI_ILOGIC1_OFB", - "IOI_ODELAY0_REGRST", - "IOI_ILOGIC0_CLKDIVP", - "IOI_EE4C3_1", - "IOI_SE4C3_1", - "IOI_ILOGIC1_CLKB", - "IOI_LOGIC_OUTS23_1", - "IOI_OLOGIC0_D1", - "IOI_EE4C0_1", - "IOI_LOGIC_OUTS22_1", - "IOI_OLOGIC1_TCE", - "IOI_LH8_0", - "IOI_SW2A0_1", - "IOI_SW4END0_1", - "LIOI_IDELAY0_DATAOUT", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_LOGIC_OUTS14_0", - "IOI_ODELAY1_LDPIPEEN", - "IOI_LH12_0", - "IOI_IMUX13_0", - "IOI_LEAF_GCLK3", - "IOI_BYP0_0", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ILOGIC0_Q4", - "LIOI_T0", - "IOI_EL1BEG1_1", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_WW4END2_0", - "IOI_IMUX26_1", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_TBYTEIN", - "IOI_LOGIC_OUTS20_1" - ], - "sites": [ - { - "prefix": "OLOGIC", - "y_coord": 0, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC1_D1", - "D3": "IOI_OLOGIC1_D3", - "SR": "IOI_OLOGIC1_SR", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "OFB": "LIOI_OLOGIC1_OFB", - "D4": "IOI_OLOGIC1_D4", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "TFB": "LIOI_OLOGIC1_TFB", - "D2": "IOI_OLOGIC1_D2", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TQ": "LIOI_OLOGIC1_TQ", - "CLKB": "IOI_OLOGIC1_CLKB", - "T3": "IOI_OLOGIC1_T3", - "SHIFTIN2": null, - "CLK": "IOI_OLOGIC1_CLK", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "T4": "IOI_OLOGIC1_T4", - "OQ": "LIOI_OLOGIC1_OQ", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "SHIFTIN1": null, - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "TCE": "IOI_OLOGIC1_TCE", - "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", - "T1": "IOI_OLOGIC1_T1", - "OCE": "IOI_OLOGIC1_OCE", - "D5": "IOI_OLOGIC1_D5", - "SHIFTOUT1": "LIOI_OSOUT11", - "T2": "IOI_OLOGIC1_T2", - "SHIFTOUT2": "LIOI_OSOUT21", - "REV": null, - "CLKDIV": "IOI_OLOGIC1_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "ILOGIC", - "y_coord": 0, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q1": "IOI_ILOGIC1_Q1", - "SHIFTOUT1": "LIOI_ISOUT11", - "SR": "IOI_ILOGIC1_SR", - "D": "LIOI_ILOGIC1_D", - "DDLY": "LIOI_ILOGIC1_DDLY", - "SHIFTIN2": "LIOI_ISIN21", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "Q3": "IOI_ILOGIC1_Q3", - "Q8": "IOI_ILOGIC1_Q8", - "TFB": "LIOI_ILOGIC1_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC1_CE1", - "Q2": "IOI_ILOGIC1_Q2", - "OCLK": "IOI_ILOGIC1_OCLK", - "Q6": "IOI_ILOGIC1_Q6", - "CLKB": "IOI_ILOGIC1_CLKB", - "Q7": "IOI_ILOGIC1_Q7", - "O": "IOI_ILOGIC1_O", - "CLK": "IOI_ILOGIC1_CLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "SHIFTIN1": "LIOI_ISIN11", - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "OFB": "LIOI_ILOGIC1_OFB", - "CE2": "IOI_ILOGIC1_CE2", - "SHIFTOUT2": "LIOI_ISOUT21", - "REV": null, - "CLKDIV": "IOI_ILOGIC1_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "OLOGIC", - "y_coord": 1, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC0_D1", - "D3": "IOI_OLOGIC0_D3", - "SR": "IOI_OLOGIC0_SR", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "OFB": "LIOI_OLOGIC0_OFB", - "D4": "IOI_OLOGIC0_D4", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "TFB": "LIOI_OLOGIC0_TFB", - "D2": "IOI_OLOGIC0_D2", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TQ": "LIOI_OLOGIC0_TQ", - "CLKB": "IOI_OLOGIC0_CLKB", - "T3": "IOI_OLOGIC0_T3", - "SHIFTIN2": "LIOI_OSIN20", - "CLK": "IOI_OLOGIC0_CLK", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "T4": "IOI_OLOGIC0_T4", - "OQ": "LIOI_OLOGIC0_OQ", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "SHIFTIN1": "LIOI_OSIN10", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "TCE": "IOI_OLOGIC0_TCE", - "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", - "T1": "IOI_OLOGIC0_T1", - "OCE": "IOI_OLOGIC0_OCE", - "D5": "IOI_OLOGIC0_D5", - "SHIFTOUT1": "LIOI_OSOUT10", - "T2": "IOI_OLOGIC0_T2", - "SHIFTOUT2": "LIOI_OSOUT20", - "REV": null, - "CLKDIV": "IOI_OLOGIC0_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "ILOGIC", - "y_coord": 1, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q1": "IOI_ILOGIC0_Q1", - "SHIFTOUT1": "LIOI_ISOUT10", - "SR": "IOI_ILOGIC0_SR", - "D": "LIOI_ILOGIC0_D", - "DDLY": "LIOI_ILOGIC0_DDLY", - "SHIFTIN2": null, - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "Q3": "IOI_ILOGIC0_Q3", - "Q8": "IOI_ILOGIC0_Q8", - "TFB": "LIOI_ILOGIC0_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC0_CE1", - "Q2": "IOI_ILOGIC0_Q2", - "OCLK": "IOI_ILOGIC0_OCLK", - "Q6": "IOI_ILOGIC0_Q6", - "CLKB": "IOI_ILOGIC0_CLKB", - "Q7": "IOI_ILOGIC0_Q7", - "O": "IOI_ILOGIC0_O", - "CLK": "IOI_ILOGIC0_CLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "SHIFTIN1": null, - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "OFB": "LIOI_ILOGIC0_OFB", - "CE2": "IOI_ILOGIC0_CE2", - "SHIFTOUT2": "LIOI_ISOUT20", - "REV": null, - "CLKDIV": "IOI_ILOGIC0_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "IDELAY", - "y_coord": 0, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "IFDLY1": "LIOI3_IDELAY1_IFDLY1", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CE": "IOI_IDELAY1_CE", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "DATAOUT": "LIOI_IDELAY1_DATAOUT", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "LD": "IOI_IDELAY1_LD", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "IFDLY0": "LIOI3_IDELAY1_IFDLY0", - "IFDLY2": "LIOI3_IDELAY1_IFDLY2", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "INC": "IOI_IDELAY1_INC", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY1_DATAIN", - "C": "IOI_IDELAY1_C", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "IDATAIN": "LIOI_IDELAY1_IDATAIN", - "REGRST": "IOI_IDELAY1_REGRST", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IDELAY", - "y_coord": 1, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "IFDLY1": "LIOI3_IDELAY0_IFDLY1", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CE": "IOI_IDELAY0_CE", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "DATAOUT": "LIOI_IDELAY0_DATAOUT", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "LD": "IOI_IDELAY0_LD", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "IFDLY0": "LIOI3_IDELAY0_IFDLY0", - "IFDLY2": "LIOI3_IDELAY0_IFDLY2", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "INC": "IOI_IDELAY0_INC", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY0_DATAIN", - "C": "IOI_IDELAY0_C", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "IDATAIN": "LIOI_IDELAY0_IDATAIN", - "REGRST": "IOI_IDELAY0_REGRST", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "LIOI3.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "LIOI_I2GCLK_TOP0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY1_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { - "can_invert": "0", - "dst_wire": "LIOI_IBUF_DISABLE0", - "is_directional": "1", - "src_wire": "IOI_IMUX9_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR2", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, "LIOI3.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_0", - "is_directional": "1", "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", - "dst_wire": "IOI_OCLK_0", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_1", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX31_1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS13_0", - "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT", - "is_pseudo": "0" - }, - "LIOI3.IOI_CTRL0_0->IOI_OLOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_CTRL1_1->IOI_ILOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX26_1->IOI_IDELAY0_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY1_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_I0->LIOI_IDELAY0_IDATAIN": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY0_IDATAIN", - "is_directional": "1", - "src_wire": "LIOI_I0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "LIOI3.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS22_1", - "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_RDY", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX30_0->IOI_IDELAY1_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX30_1->IOI_IDELAY0_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { - "can_invert": "0", - "dst_wire": "LIOI_IBUF_DISABLE1", - "is_directional": "1", - "src_wire": "IOI_IMUX9_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "LIOI3.IOI_IMUX13_0->IOI_OLOGIC1_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX42_0->IOI_OLOGIC1_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX7_1->IOI_OLOGIC0_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_DDLY", - "is_directional": "1", - "src_wire": "LIOI_IDELAY0_DATAOUT", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS16_0", - "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP3_0->IOI_IMUX_RC0": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC0", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAYCTRL_RST", - "is_directional": "1", - "src_wire": "IOI_IMUX24_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_T0": { - "can_invert": "0", - "dst_wire": "LIOI_T0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TQ", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "LIOI3.IOI_IMUX31_0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX40_0->IOI_OLOGIC1_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_CLK1_0->IOI_IDELAY1_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { - "can_invert": "0", - "dst_wire": "LIOI_DCI_T_TERM1", - "is_directional": "1", - "src_wire": "IOI_IMUX6_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_O1": { - "can_invert": "0", - "dst_wire": "LIOI_O1", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_OQ", - "is_pseudo": "0" - }, - "LIOI3.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC1_DDLY", - "is_pseudo": "1" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX45_1->IOI_OLOGIC0_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q4", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_1", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY1_DATAOUT", - "is_directional": "1", - "src_wire": "LIOI_IDELAY1_IDATAIN", - "is_pseudo": "1" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY1_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE2_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX46_0->IOI_OLOGIC1_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "LIOI3.LIOI_ISOUT20->LIOI_ISIN21": { - "can_invert": "0", - "dst_wire": "LIOI_ISIN21", - "is_directional": "1", - "src_wire": "LIOI_ISOUT20", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q7", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX42_1->IOI_OLOGIC0_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q7", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE0", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q6", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP4_0->IOI_IMUX_RC1": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q5", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_O", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX44_1->IOI_OLOGIC0_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX31_1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX43_1->IOI_OLOGIC0_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_1", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX21_1->IOI_OLOGIC0_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS16_1", - "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_OUTN65", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX32_1->IOI_IDELAY0_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX7_0->IOI_OLOGIC1_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX21_0->IOI_OLOGIC1_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX46_1->IOI_OLOGIC0_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_1", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TFB", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC0_DDLY", - "is_pseudo": "1" - }, - "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR1_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX47_1->IOI_OLOGIC0_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "LIOI3.IOI_CTRL0_1->IOI_OLOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q4", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OFB", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX43_0->IOI_OLOGIC1_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.LIOI_IBUF1->LIOI_I1": { - "can_invert": "0", - "dst_wire": "LIOI_I1", - "is_directional": "1", - "src_wire": "LIOI_IBUF1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX40_1->IOI_OLOGIC0_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "LIOI3.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC1_D", - "is_pseudo": "1" - }, - "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX45_0->IOI_OLOGIC1_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "LIOI3.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_CLK1_1->IOI_IDELAY0_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_I1->LIOI_ILOGIC1_D": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_D", - "is_directional": "1", - "src_wire": "LIOI_I1", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OSOUT11->LIOI_OSIN10": { - "can_invert": "0", - "dst_wire": "LIOI_OSIN10", - "is_directional": "1", - "src_wire": "LIOI_OSOUT11", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR3", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX31_0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TQ", - "is_pseudo": "1" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX15_0->IOI_OLOGIC1_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_T1": { - "can_invert": "0", - "dst_wire": "LIOI_T1", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TQ", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX15_1->IOI_OLOGIC0_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q6", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS13_1", - "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_OUTN1", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP4_1->IOI_IMUX_RC2": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC2", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q5", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR0_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_DDLY", - "is_directional": "1", - "src_wire": "LIOI_IDELAY1_DATAOUT", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q1", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_OQ", - "is_pseudo": "1" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.LIOI_ISOUT10->LIOI_ISIN11": { - "can_invert": "0", - "dst_wire": "LIOI_ISIN11", - "is_directional": "1", - "src_wire": "LIOI_ISOUT10", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY0_DATAOUT", - "is_directional": "1", - "src_wire": "LIOI_IDELAY0_IDATAIN", - "is_pseudo": "1" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE3_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX44_0->IOI_OLOGIC1_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OQ", - "is_pseudo": "1" - }, - "LIOI3.IOI_BYP3_1->IOI_IMUX_RC3": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC3", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX32_0->IOI_IDELAY1_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX34_0->IOI_OLOGIC1_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q8", - "is_pseudo": "0" - }, - "LIOI3.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC0_D", - "is_pseudo": "1" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX34_1->IOI_OLOGIC0_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_IBUF0->LIOI_I0": { - "can_invert": "0", - "dst_wire": "LIOI_I0", - "is_directional": "1", - "src_wire": "LIOI_IBUF0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_CTRL1_0->IOI_ILOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TQ", - "is_pseudo": "1" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q8", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_1", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX47_0->IOI_OLOGIC1_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3.LIOI_I0->LIOI_ILOGIC0_D": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_D", - "is_directional": "1", - "src_wire": "LIOI_I0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX26_0->IOI_IDELAY1_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_IOCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_O0": { - "can_invert": "0", - "dst_wire": "LIOI_O0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OQ", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX13_1->IOI_OLOGIC0_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" }, "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" }, - "LIOI3.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { + "LIOI3.IOI_IOCLK1->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK1", "can_invert": "0", - "dst_wire": "LIOI_DCI_T_TERM0", "is_directional": "1", - "src_wire": "IOI_IMUX6_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" }, - "LIOI3.LIOI_I1->LIOI_IDELAY1_IDATAIN": { + "LIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", "can_invert": "0", - "dst_wire": "LIOI_IDELAY1_IDATAIN", "is_directional": "1", - "src_wire": "LIOI_I1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" }, - "LIOI3.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", - "src_wire": "IOI_IMUX29_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" }, - "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" }, - "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" }, - "LIOI3.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "LIOI3.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_1", "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1" }, - "LIOI3.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { + "LIOI3.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_OFB", "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_OFB", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" }, - "LIOI3.LIOI_OSOUT21->LIOI_OSIN20": { + "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", "can_invert": "0", - "dst_wire": "LIOI_OSIN20", "is_directional": "1", - "src_wire": "LIOI_OSOUT21", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "src_wire": "IOI_IMUX42_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4" + }, + "LIOI3.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.LIOI_IBUF1->LIOI_I1": { + "src_wire": "LIOI_IBUF1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_I1" }, "LIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { "can_invert": "0", - "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_IMUX8_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "src_wire": "IOI_IMUX34_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1" + }, + "LIOI3.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "src_wire": "LIOI_ILOGIC1_DDLY", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_CLK1_1->IOI_IDELAY0_C": { + "src_wire": "IOI_CLK1_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C" + }, + "LIOI3.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "src_wire": "IOI_IMUX15_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1" + }, + "LIOI3.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { + "src_wire": "IOI_FAN4_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY0" + }, + "LIOI3.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { + "src_wire": "IOI_IDELAYCTRL_RDY", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS22_1" + }, + "LIOI3.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "src_wire": "IOI_CTRL1_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "src_wire": "IOI_IMUX13_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "src_wire": "IOI_IMUX40_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2" + }, + "LIOI3.LIOI_I1->LIOI_IDELAY1_IDATAIN": { + "src_wire": "LIOI_I1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY1_IDATAIN" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { + "src_wire": "IOI_BYP7_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY2" + }, + "LIOI3.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "src_wire": "IOI_IMUX40_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2" + }, + "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_O1": { + "src_wire": "LIOI_OLOGIC1_OQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_O1" + }, + "LIOI3.IOI_IOCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { + "src_wire": "LIOI_IDELAY1_DATAOUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_DDLY" + }, + "LIOI3.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "src_wire": "IOI_IMUX25_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN" + }, + "LIOI3.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "src_wire": "IOI_IMUX30_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_IOCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_IMUX8_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "src_wire": "IOI_IMUX34_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_IOCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "src_wire": "IOI_BYP4_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2" + }, + "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX20_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "src_wire": "IOI_IMUX5_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1" + }, + "LIOI3.IOI_IMUX31_1->>IOI_OCLK_0": { + "src_wire": "IOI_IMUX31_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_BYP4_1->IOI_IMUX_RC2": { + "src_wire": "IOI_BYP4_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2" + }, + "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "src_wire": "IOI_BYP6_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "src_wire": "IOI_IMUX33_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "src_wire": "IOI_CLK0_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "src_wire": "IOI_ILOGIC0_O", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1" + }, + "LIOI3.IOI_BYP3_1->IOI_IMUX_RC3": { + "src_wire": "IOI_BYP3_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3" + }, + "LIOI3.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "src_wire": "IOI_IMUX21_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { + "src_wire": "IOI_IDELAYCTRL_OUTN65", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS16_1" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0" + }, + "LIOI3.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLKM_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "LIOI3.IOI_IMUX31_0->>IOI_OCLK_1": { + "src_wire": "IOI_IMUX31_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "src_wire": "IOI_IMUX26_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC" + }, + "LIOI3.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "src_wire": "IOI_IMUX47_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8" + }, + "LIOI3.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "src_wire": "IOI_ILOGIC0_Q3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "src_wire": "IOI_IMUX21_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4" + }, + "LIOI3.IOI_IOCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "src_wire": "IOI_CTRL1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR" + }, + "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "src_wire": "IOI_OCLK_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK" + }, + "LIOI3.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0" + }, + "LIOI3.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "src_wire": "IOI_IMUX43_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5" + }, + "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "src_wire": "IOI_BYP3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3" + }, + "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { + "src_wire": "IOI_OLOGIC0_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB" + }, + "LIOI3.IOI_IMUX31_1->>IOI_OCLKM_0": { + "src_wire": "IOI_IMUX31_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { + "src_wire": "IOI_IMUX9_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE0" + }, + "LIOI3.LIOI_ISOUT20->LIOI_ISIN21": { + "src_wire": "LIOI_ISOUT20", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN21" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "src_wire": "IOI_IMUX26_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { + "src_wire": "IOI_OLOGIC1_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OQ" + }, + "LIOI3.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_IMUX8_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "src_wire": "IOI_IMUX5_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX20_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "src_wire": "IOI_IMUX33_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { + "src_wire": "IOI_ILOGIC0_O", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_I2GCLK_TOP0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "src_wire": "IOI_IMUX43_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_IOCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "LIOI3.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "src_wire": "IOI_ILOGIC0_Q4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1" + }, + "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "src_wire": "IOI_OCLK_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK" + }, + "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { + "src_wire": "IOI_IMUX6_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM0" + }, + "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX22_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_IMUX8_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLK_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "LIOI3.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "src_wire": "IOI_ILOGIC1_Q8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OFB", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_OFB" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "src_wire": "IOI_IMUX7_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { + "src_wire": "IOI_OLOGIC0_T1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { + "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS13_0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_IOCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { + "src_wire": "LIOI_OLOGIC1_OQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB" + }, + "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "src_wire": "IOI_ILOGIC0_Q7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1" + }, + "LIOI3.IOI_IOCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_CLK0_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_BYP4_0->IOI_IMUX_RC1": { + "src_wire": "IOI_BYP4_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.IOI_IOCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_T1": { + "src_wire": "LIOI_OLOGIC1_TQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_T1" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "src_wire": "IOI_OCLKM_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_IOCLK1->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "src_wire": "IOI_OCLK_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK" + }, + "LIOI3.IOI_IOCLK2->>IOI_OCLKM_0": { + "src_wire": "IOI_IOCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "src_wire": "IOI_ILOGIC0_Q5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "LIOI3.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { + "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS16_0" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.LIOI_I0->LIOI_IDELAY0_IDATAIN": { + "src_wire": "LIOI_I0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY0_IDATAIN" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "src_wire": "IOI_BYP4_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1" + }, + "LIOI3.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "src_wire": "IOI_ILOGIC0_Q8", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1" + }, + "LIOI3.IOI_IOCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "src_wire": "IOI_IMUX32_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE" + }, + "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { + "src_wire": "IOI_OLOGIC1_T1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLKM_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_DDLY", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" }, "LIOI3.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_1", - "is_directional": "1", "src_wire": "IOI_ILOGIC0_Q1", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1" + }, + "LIOI3.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "src_wire": "IOI_IMUX44_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3" + }, + "LIOI3.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3.IOI_IOCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_IOCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "src_wire": "IOI_IMUX7_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2" + }, + "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "src_wire": "IOI_BYP3_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0" + }, + "LIOI3.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "src_wire": "IOI_ILOGIC1_Q7", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1" + }, + "LIOI3.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_IMUX8_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_O0": { + "src_wire": "LIOI_OLOGIC0_OQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_O0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLKM_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1" + }, + "LIOI3.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "src_wire": "IOI_IMUX36_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "LIOI3.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "src_wire": "IOI_IMUX47_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8" + }, + "LIOI3.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "src_wire": "IOI_IMUX14_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2" + }, + "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX22_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "src_wire": "IOI_BYP3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1" + }, + "LIOI3.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "src_wire": "IOI_IMUX44_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3" + }, + "LIOI3.IOI_IOCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_IOCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.LIOI_ISOUT10->LIOI_ISIN11": { + "src_wire": "LIOI_ISOUT10", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN11" + }, + "LIOI3.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "src_wire": "IOI_IMUX25_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN" + }, + "LIOI3.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0" + }, + "LIOI3.IOI_IMUX31_0->>IOI_OCLKM_1": { + "src_wire": "IOI_IMUX31_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { + "src_wire": "IOI_IMUX6_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM1" + }, + "LIOI3.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "src_wire": "IOI_IMUX30_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD" + }, + "LIOI3.LIOI_OSOUT11->LIOI_OSIN10": { + "src_wire": "LIOI_OSOUT11", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN10" + }, + "LIOI3.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { + "src_wire": "LIOI_OLOGIC1_OFB", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_OFB" + }, + "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { + "src_wire": "LIOI_OLOGIC1_TQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB" + }, + "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { + "src_wire": "IOI_OLOGIC1_T1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TQ" + }, + "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "src_wire": "IOI_OCLK_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "LIOI3.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "src_wire": "IOI_IMUX41_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "src_wire": "IOI_ILOGIC0_Q2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "src_wire": "IOI_IMUX12_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "src_wire": "IOI_IMUX1_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE" + }, + "LIOI3.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "src_wire": "IOI_IMUX46_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7" + }, + "LIOI3.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "src_wire": "IOI_IMUX42_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4" + }, + "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IOCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "src_wire": "IOI_ILOGIC1_O", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "src_wire": "IOI_BYP4_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1" + }, + "LIOI3.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "src_wire": "IOI_ILOGIC1_Q4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0" + }, + "LIOI3.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "src_wire": "IOI_ILOGIC1_Q3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0" + }, + "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_TFB" + }, + "LIOI3.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "src_wire": "IOI_ILOGIC1_Q5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0" + }, + "LIOI3.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { + "src_wire": "IOI_FAN4_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY0" + }, + "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "src_wire": "IOI_OCLK_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK" + }, + "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_IMUX8_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "src_wire": "IOI_CTRL0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR" + }, + "LIOI3.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "src_wire": "IOI_IMUX38_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.LIOI_I1->LIOI_ILOGIC1_D": { + "src_wire": "LIOI_I1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_D" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3.IOI_IOCLK0->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IMUX22_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "src_wire": "IOI_IMUX45_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6" + }, + "LIOI3.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "src_wire": "IOI_IMUX10_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_T0": { + "src_wire": "LIOI_OLOGIC0_TQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_T0" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { + "src_wire": "IOI_TBYTEIN", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "src_wire": "IOI_IMUX0_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP" + }, + "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { + "src_wire": "IOI_OLOGIC0_T1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TQ" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IMUX22_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { + "src_wire": "IOI_IMUX24_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAYCTRL_RST" + }, + "LIOI3.IOI_CLK1_0->IOI_IDELAY1_C": { + "src_wire": "IOI_CLK1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C" + }, + "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_IOCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { + "src_wire": "IOI_FAN5_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY1" + }, + "LIOI3.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "src_wire": "IOI_IMUX39_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "LIOI3.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "src_wire": "IOI_IMUX1_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.LIOI_OSOUT21->LIOI_OSIN20": { + "src_wire": "LIOI_OSOUT21", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN20" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "src_wire": "IOI_BYP3_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "src_wire": "IOI_IMUX15_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "src_wire": "IOI_IMUX14_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2" + }, + "LIOI3.IOI_BYP3_0->IOI_IMUX_RC0": { + "src_wire": "IOI_BYP3_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0" + }, + "LIOI3.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "src_wire": "IOI_IMUX29_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1" + }, + "LIOI3.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "src_wire": "IOI_ILOGIC1_Q6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0" + }, + "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { + "src_wire": "IOI_OLOGIC1_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB" + }, + "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "src_wire": "IOI_OCLK_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { + "src_wire": "IOI_BYP7_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY2" + }, + "LIOI3.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "src_wire": "IOI_BYP4_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1" + }, + "LIOI3.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.IOI_IOCLK3->>IOI_OCLKM_1": { + "src_wire": "IOI_IOCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { + "src_wire": "IOI_FAN5_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY1" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { + "src_wire": "IOI_OLOGIC0_D1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OQ" + }, + "LIOI3.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { + "src_wire": "IOI_IMUX9_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE1" + }, + "LIOI3.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "src_wire": "IOI_IMUX12_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { + "src_wire": "LIOI_OLOGIC1_TFB", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL" + }, + "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "src_wire": "IOI_OCLK_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IMUX20_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "src_wire": "IOI_IMUX45_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { + "src_wire": "IOI_IDELAYCTRL_OUTN1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS13_1" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "src_wire": "LIOI_ILOGIC0_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "LIOI3.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "src_wire": "IOI_IMUX32_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE" + }, + "LIOI3.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "src_wire": "IOI_ILOGIC1_Q1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0" + }, + "LIOI3.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "src_wire": "IOI_IMUX13_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3" + }, + "LIOI3.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0" + }, + "LIOI3.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { + "src_wire": "LIOI_IDELAY0_IDATAIN", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY0_DATAOUT" + }, + "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_TFB" + }, + "LIOI3.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "src_wire": "LIOI_ILOGIC1_D", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "LIOI3.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "src_wire": "IOI_BYP6_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL" + }, + "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "src_wire": "IOI_LEAF_GCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "src_wire": "IOI_CTRL0_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR" + }, + "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_IMUX8_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "src_wire": "IOI_CLK0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV" + }, + "LIOI3.LIOI_I0->LIOI_ILOGIC0_D": { + "src_wire": "LIOI_I0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_D" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_IOCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "src_wire": "IOI_IMUX46_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7" + }, + "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "src_wire": "IOI_IOCLK0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "src_wire": "IOI_RCLK_FORIO3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { + "src_wire": "LIOI_IDELAY0_DATAOUT", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_DDLY" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "src_wire": "IOI_LEAF_GCLK5", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_IMUX20_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "src_wire": "IOI_CLK0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { + "src_wire": "LIOI_OLOGIC0_TFB", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL" + }, + "LIOI3.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "src_wire": "IOI_ILOGIC1_Q2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0" + }, + "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { + "src_wire": "LIOI_OLOGIC0_OQ", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB" + }, + "LIOI3.LIOI_IBUF0->LIOI_I0": { + "src_wire": "LIOI_IBUF0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_I0" + }, + "LIOI3.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "src_wire": "IOI_IMUX35_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "LIOI3.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "src_wire": "IOI_IMUX4_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "LIOI3.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "src_wire": "IOI_IMUX0_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP" + }, + "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "src_wire": "IOI_RCLK_FORIO2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_IMUX8_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "src_wire": "IOI_LEAF_GCLK4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "src_wire": "IOI_RCLK_FORIO0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "src_wire": "IOI_ILOGIC0_Q6", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1" + }, + "LIOI3.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { + "src_wire": "LIOI_IDELAY1_IDATAIN", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY1_DATAOUT" + }, + "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "src_wire": "IOI_LEAF_GCLK3", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0" + }, + "LIOI3.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "src_wire": "IOI_IMUX29_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE" + }, + "LIOI3.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "src_wire": "IOI_IMUX37_1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "src_wire": "IOI_LEAF_GCLK2", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" } }, - "tile_type": "LIOI3" + "wires": [ + "IOI_BYP5_1", + "IOI_IMUX26_1", + "IOI_NW4END3_1", + "IOI_ILOGIC1_REV", + "IOI_IMUX42_0", + "IOI_EE4A1_1", + "IOI_IMUX22_1", + "IOI_ILOGIC0_CE2", + "IOI_IMUX5_0", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "LIOI3_IDELAY1_IFDLY1", + "IOI_OLOGIC1_CLKB", + "IOI_WW4C1_1", + "IOI_ER1BEG0_1", + "IOI_IMUX23_0", + "IOI_RCLK_DIV_CLR0_1", + "IOI_OLOGIC1_T1", + "IOI_IOCLK3", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_RCLK_DIV_CE2_1", + "IOI_DCI_TSTRST", + "IOI_OLOGIC1_REV", + "IOI_WW4END1_0", + "IOI_CTRL0_1", + "IOI_MONITOR_N", + "IOI_ILOGIC1_Q7", + "IOI_IMUX38_0", + "LIOI_ISOUT21", + "IOI_WW4B1_1", + "IOI_EE4C1_1", + "IOI_IOCLK2", + "IOI_OLOGIC1_D8", + "IOI_LEAF_GCLK4", + "IOI_WW2END2_1", + "IOI_BYP2_0", + "IOI_ILOGIC1_Q1", + "IOI_IMUX36_1", + "IOI_LEAF_GCLK3", + "IOI_SW2A0_1", + "IOI_IMUX16_1", + "IOI_FAN2_1", + "IOI_IMUX27_0", + "IOI_IMUX22_0", + "IOI_EL1BEG2_1", + "IOI_NW4A1_0", + "IOI_BLOCK_OUTS0_1", + "IOI_SE2A1_0", + "LIOI_OSIN21", + "IOI_IMUX4_1", + "IOI_EL1BEG2_0", + "IOI_WW4B0_1", + "IOI_NE4BEG3_1", + "LIOI_ISIN11", + "IOI_SW4A3_1", + "IOI_SW4A1_0", + "IOI_ODELAY0_LDPIPEEN", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_EE4B3_1", + "IOI_NE4C0_1", + "IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_BYP4_1", + "IOI_EE2BEG1_0", + "IOI_LOGIC_OUTS20_0", + "LIOI_T1", + "IOI_SE4C3_1", + "IOI_WL1END2_0", + "IOI_CTRL1_1", + "IOI_FAN5_0", + "IOI_EE2A2_0", + "IOI_WW4END2_1", + "IOI_WW4C0_0", + "IOI_IDELAY1_REGRST", + "IOI_PHASER_TO_IO_OCLK", + "IOI_SW4A0_1", + "IOI_IDELAY1_CNTVALUEIN0", + "LIOI_I1", + "IOI_OLOGIC0_CLKDIV", + "LIOI_I0", + "IOI_IMUX17_0", + "LIOI_ISIN20", + "IOI_WW2END2_0", + "IOI_FAN3_0", + "IOI_LOGIC_OUTS14_0", + "IOI_DCI_TSTCLK", + "IOI_FAN0_0", + "IOI_ODELAY1_CINVCTRL", + "IOI_SE4BEG0_0", + "IOI_IMUX20_1", + "IOI_EE2BEG3_0", + "IOI_LH7_0", + "IOI_IMUX15_1", + "IOI_ILOGIC0_Q3", + "IOI_EE4A1_0", + "IOI_ILOGIC1_Q8", + "LIOI_PU_INT_EN_0", + "IOI_IDELAY1_C", + "IOI_BYP7_0", + "IOI_IMUX25_0", + "IOI_IDELAY0_REGRST", + "IOI_BYP3_1", + "IOI_NE2A0_1", + "IOI_IMUX11_1", + "IOI_SE4BEG0_1", + "IOI_ILOGIC0_OCLKB", + "IOI_IMUX47_0", + "IOI_OLOGIC0_D4", + "IOI_SE2A0_0", + "IOI_SE4BEG1_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_SW4END3_0", + "IOI_EE4BEG3_0", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLKB", + "IOI_LOGIC_OUTS19_1", + "IOI_EL1BEG1_1", + "IOI_OLOGIC0_D3", + "IOI_EE4C0_0", + "IOI_OLOGIC0_TCE", + "IOI_WW2A0_0", + "LIOI3_IDELAY1_IFDLY0", + "LIOI_I2GCLK_TOP1", + "IOI_ODELAY0_CLKIN", + "IOI_DCI_TSTHLN", + "IOI_IMUX15_0", + "IOI_WW2END1_1", + "IOI_NE4C3_1", + "IOI_ILOGIC0_O", + "LIOI3_IDELAY0_IFDLY1", + "IOI_RCLK_DIV_CE3", + "IOI_BLOCK_OUTS0_0", + "IOI_SE4C3_0", + "IOI_ILOGIC1_CLKDIV", + "IOI_BYP0_1", + "IOI_IMUX32_0", + "IOI_OLOGIC1_D5", + "LIOI_ODELAY1_OFDLY1", + "IOI_LH4_0", + "IOI_RCLK_DIV_CLR1", + "LIOI_ODELAY1_OFDLY2", + "LIOI_PD_INT_EN_1", + "IOI_IMUX10_0", + "IOI_NW2A0_1", + "IOI_ILOGIC0_REV", + "LIOI_ILOGIC1_DDLY", + "IOI_ODELAY0_CNTVALUEIN4", + "LIOI_IDELAY1_IDATAIN", + "IOI_LOGIC_OUTS1_1", + "IOI_OLOGIC0_T1", + "IOI_EE4BEG1_0", + "IOI_IMUX41_0", + "IOI_WW4C3_0", + "IOI_LOGIC_OUTS23_0", + "IOI_RCLK_DIV_CE0", + "LIOI3_IDELAY0_IFDLY0", + "IOI_SW2A3_1", + "IOI_EE4B3_0", + "IOI_IOCLK0", + "IOI_EE4BEG0_0", + "IOI_ODELAY0_INC", + "IOI_IMUX6_0", + "LIOI_ODELAY1_ODATAIN", + "LIOI_ILOGIC1_D", + "IOI_WR1END3_0", + "IOI_IMUX10_1", + "IOI_IMUX40_0", + "IOI_IMUX37_1", + "IOI_OLOGIC0_REV", + "IOI_OLOGIC0_D1", + "IOI_IOCLK1", + "IOI_RCLK_FORIO1", + "IOI_ODELAY1_LD", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_WW4A1_1", + "IOI_NE4C0_0", + "LIOI_ISOUT10", + "IOI_NW4A2_1", + "LIOI_DCI_T_TERM0", + "IOI_LOGIC_OUTS6_1", + "LIOI_I2GCLK_TOP0", + "IOI_LH3_1", + "IOI_IMUX33_0", + "IOI_IMUX13_0", + "IOI_IMUX9_0", + "IOI_EE4BEG0_1", + "IOI_WW2A2_1", + "IOI_WR1END0_1", + "IOI_OLOGIC0_T3", + "IOI_EE4A2_0", + "IOI_IMUX26_0", + "IOI_IMUX0_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX3_0", + "IOI_EE4B2_0", + "IOI_SW2A2_1", + "LIOI_IBUF_DISABLE0", + "IOI_OLOGIC0_OCE", + "IOI_ILOGIC0_CE1", + "LIOI_OSIN11", + "LIOI_ILOGIC0_OFB", + "IOI_LOGIC_OUTS8_0", + "IOI_SE2A2_1", + "IOI_WW2END0_0", + "LIOI_IDELAY0_IDATAIN", + "IOI_SW2A1_0", + "IOI_RCLK_FORIO2", + "IOI_LH3_0", + "IOI_EE4B1_0", + "LIOI_ILOGIC0_D", + "IOI_SW4END1_0", + "IOI_WW4A2_0", + "IOI_ER1BEG3_0", + "IOI_LH6_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_IMUX40_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IMUX2_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_BYP1_1", + "IOI_SW4END1_1", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_IDELAYCTRL_RDY", + "IOI_ODELAY1_CNTVALUEOUT0", + "LIOI_OSOUT11", + "IOI_IMUX44_0", + "IOI_NW2A2_0", + "IOI_OLOGIC1_D4", + "IOI_SW4A1_1", + "IOI_LOGIC_OUTS22_1", + "IOI_RCLK_DIV_CE3_1", + "LIOI_ISIN21", + "IOI_OLOGIC0_D6", + "IOI_IDELAY0_CINVCTRL", + "IOI_IMUX25_1", + "IOI_WW4END1_1", + "IOI_WW4END0_1", + "LIOI_OLOGIC0_CLKDIVF", + "IOI_SE4BEG2_0", + "IOI_LOGIC_OUTS16_0", + "IOI_NW4END3_0", + "IOI_NE4BEG2_0", + "IOI_DCI_DCIDONE", + "LIOI_DCI_T_TERM1", + "IOI_ILOGIC0_CLKDIVP", + "IOI_OLOGIC1_TBYTEIN", + "IOI_IMUX13_1", + "IOI_LOGIC_OUTS7_0", + "IOI_IMUX_RC1", + "IOI_CLK0_1", + "IOI_NE2A3_1", + "IOI_DCI_TSTRST0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS13_0", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_IDELAY1_INC", + "IOI_OLOGIC1_OCE", + "IOI_LEAF_GCLK2", + "IOI_CLK1_1", + "IOI_NE4C2_1", + "IOI_WW4B0_0", + "IOI_ODELAY1_CNTVALUEIN0", + "IOI_WL1END3_1", + "IOI_IMUX28_0", + "IOI_NW4END1_0", + "LIOI3_IDELAY0_IFDLY2", + "IOI_OLOGIC1_D7", + "IOI_LOGIC_OUTS11_0", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_IMUX18_1", + "IOI_WW4A0_1", + "IOI_OLOGIC0_D8", + "IOI_IMUX38_1", + "IOI_IMUX21_0", + "IOI_EE2BEG1_1", + "IOI_EE4B0_0", + "IOI_FAN4_0", + "IOI_IDELAYCTRL_RST", + "IOI_SW4A2_0", + "IOI_NW2A0_0", + "IOI_OCLKM_0", + "IOI_EE2BEG0_1", + "IOI_LOGIC_OUTS14_1", + "LIOI_OLOGIC0_OFB", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS21_0", + "IOI_ODELAY1_CNTVALUEIN1", + "IOI_ILOGIC1_OCLK", + "IOI_IMUX17_1", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_SW4END3_1", + "IOI_ODELAY1_CLKIN", + "IOI_NE2A1_0", + "IOI_EE4A2_1", + "IOI_OCLKM_1", + "IOI_IMUX43_0", + "LIOI_I2GCLK_BOT1", + "IOI_LH8_1", + "IOI_RCLK_DIV_CE1", + "IOI_LOGIC_OUTS17_0", + "IOI_SE2A3_0", + "IOI_ILOGIC1_Q6", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LH9_0", + "IOI_OLOGIC0_D2", + "IOI_OLOGIC0_CLKDIVB", + "IOI_IMUX30_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_LOGIC_OUTS0_0", + "IOI_WW2A1_0", + "IOI_BYP7_1", + "IOI_SE4C1_0", + "IOI_IMUX39_1", + "IOI_OCLK_1", + "IOI_EL1BEG0_1", + "IOI_ILOGIC0_Q4", + "IOI_IMUX45_1", + "IOI_IMUX20_0", + "IOI_ODELAY1_REGRST", + "IOI_OLOGIC0_D5", + "IOI_ODELAY1_INC", + "IOI_ODELAY1_CNTVALUEIN3", + "IOI_WW2A0_1", + "IOI_NW2A1_0", + "IOI_WW2A2_0", + "IOI_EE2BEG3_1", + "IOI_ILOGIC0_Q8", + "IOI_IMUX24_0", + "IOI_OLOGIC0_T2", + "IOI_IDELAY0_LD", + "IOI_FAN5_1", + "LIOI_O1", + "IOI_OLOGIC1_T2", + "IOI_LOGIC_OUTS3_1", + "IOI_FAN3_1", + "IOI_BYP0_0", + "IOI_IMUX35_1", + "IOI_ILOGIC1_OCLKB", + "IOI_IMUX27_1", + "IOI_WW4END3_1", + "IOI_BLOCK_OUTS2_1", + "LIOI_OSOUT20", + "IOI_EE2BEG2_0", + "IOI_NE2A3_0", + "IOI_SE2A1_1", + "IOI_NE4BEG3_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_LH12_0", + "IOI_LH2_1", + "IOI_ER1BEG3_1", + "IOI_LH1_1", + "IOI_ILOGIC1_CE2", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_FAN4_1", + "IOI_IDELAY0_CE", + "LIOI_OSIN10", + "IOI_EE4C2_1", + "IOI_OLOGIC0_CLK", + "IOI_LOGIC_OUTS12_1", + "IOI_SW2A3_0", + "LIOI_IBUF0", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_ODELAY1_CNTVALUEIN2", + "LIOI_OLOGIC1_TFB_LOCAL", + "IOI_SW2A1_1", + "LIOI_OLOGIC0_TFB_LOCAL", + "IOI_LH1_0", + "IOI_FAN1_1", + "LIOI_OSOUT21", + "LIOI3_IDELAY1_IFDLY2", + "IOI_LOGIC_OUTS10_1", + "IOI_LOGIC_OUTS22_0", + "IOI_IMUX34_1", + "IOI_WW4A1_0", + "IOI_FAN7_0", + "IOI_IDELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OCLK_0", + "IOI_ODELAY0_REGRST", + "IOI_LOGIC_OUTS15_0", + "IOI_LEAF_GCLK0", + "LIOI_ILOGIC1_OFB", + "IOI_EE2A0_1", + "IOI_IMUX12_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_IMUX23_1", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_LOGIC_OUTS15_1", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_EL1BEG3_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IMUX39_0", + "IOI_WR1END0_0", + "IOI_ODELAY1_CNTVALUEIN4", + "IOI_IMUX19_0", + "IOI_RCLK_FORIO3", + "IOI_BYP1_0", + "IOI_ILOGIC0_Q2", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_NW2A3_1", + "IOI_IDELAY0_C", + "IOI_NW2A2_1", + "IOI_SW4END2_0", + "IOI_SW4END0_0", + "IOI_IMUX32_1", + "IOI_IMUX19_1", + "IOI_SW2A0_0", + "IOI_IMUX46_0", + "IOI_WR1END1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_LOGIC_OUTS1_0", + "IOI_IMUX8_0", + "IOI_WW4C2_1", + "LIOI_ISOUT20", + "LIOI_OLOGIC1_OFB", + "IOI_WW2END3_1", + "IOI_WW4C3_1", + "IOI_LH5_1", + "IOI_ODELAY1_CE", + "IOI_ILOGIC1_CLKDIVP", + "IOI_OLOGIC0_T4", + "IOI_NE4C2_0", + "IOI_IMUX31_1", + "IOI_NE4C3_0", + "IOI_NW4END2_1", + "IOI_IMUX7_1", + "IOI_IDELAY1_LD", + "IOI_LOGIC_OUTS23_1", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_LOGIC_OUTS9_0", + "IOI_EE2A0_0", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_WW4A3_1", + "IOI_IMUX9_1", + "IOI_NW2A1_1", + "IOI_IMUX1_0", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS9_1", + "IOI_IMUX42_1", + "IOI_RCLK_DIV_CLR3", + "IOI_IMUX21_1", + "IOI_EE2BEG0_0", + "IOI_IMUX1_1", + "IOI_OLOGIC1_T4", + "IOI_LH7_1", + "IOI_ILOGIC1_O", + "IOI_LOGIC_OUTS0_1", + "LIOI_IDELAY1_DATAOUT", + "LIOI_ODELAY0_OFDLY2", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_LOGIC_OUTS2_0", + "IOI_FAN0_1", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_ILOGIC0_OCLK", + "IOI_IMUX30_0", + "IOI_SE4C1_1", + "IOI_NE4BEG0_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LOGIC_OUTS4_1", + "LIOI_ISIN10", + "IOI_WL1END2_1", + "IOI_LEAF_GCLK5", + "IOI_IMUX43_1", + "LIOI_ODELAY1_DATAOUT", + "LIOI_OLOGIC1_TQ", + "LIOI_ISOUT11", + "IOI_EE2BEG2_1", + "IOI_NW4A2_0", + "IOI_ER1BEG1_1", + "IOI_NW4END0_0", + "IOI_BYP5_0", + "IOI_ILOGIC1_Q3", + "IOI_LH4_1", + "IOI_IMUX37_0", + "IOI_IDELAY1_DATAIN", + "IOI_IMUX_RC3", + "IOI_ILOGIC0_CLKB", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IDELAY1_CNTVALUEIN3", + "IOI_IDELAY1_CNTVALUEIN2", + "IOI_IMUX16_0", + "LIOI_O0", + "IOI_SW4A2_1", + "IOI_WW4END0_0", + "IOI_BLOCK_OUTS2_0", + "IOI_EE4BEG2_1", + "LIOI_ODELAY0_OFDLY0", + "IOI_NW2A3_0", + "IOI_IMUX_RC0", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WR1END3_1", + "IOI_NW4END1_1", + "LIOI_OSOUT10", + "IOI_SE2A2_0", + "LIOI_OLOGIC0_OQ", + "IOI_ILOGIC0_Q6", + "IOI_NW4A3_1", + "IOI_EE4B2_1", + "IOI_SE4BEG3_0", + "LIOI_OSIN20", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_IMUX36_0", + "IOI_LOGIC_OUTS5_0", + "IOI_LH8_0", + "IOI_IMUX12_0", + "IOI_EE4C3_0", + "IOI_ODELAY1_CNTVALUEOUT2", + "IOI_SW4END0_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_OLOGIC1_CLKDIVFB", + "IOI_IMUX0_1", + "IOI_CLK1_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_OLOGIC0_D7", + "IOI_BLOCK_OUTS3_1", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_WW4END3_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_OLOGIC1_D6", + "IOI_IMUX29_0", + "IOI_LOGIC_OUTS18_0", + "IOI_WL1END1_0", + "IOI_LH6_1", + "IOI_EL1BEG0_0", + "IOI_ILOGIC1_Q2", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_LEAF_GCLK1", + "IOI_EE2A1_0", + "IOI_WW4B1_0", + "IOI_DCI_TSTHLP", + "IOI_EE4A0_0", + "IOI_BYP3_0", + "IOI_FAN6_0", + "IOI_LOGIC_OUTS10_0", + "IOI_SE4BEG2_1", + "IOI_IMUX29_1", + "IOI_IDELAY0_LDPIPEEN", + "IOI_ILOGIC0_SR", + "IOI_WW4A0_0", + "IOI_NE4BEG2_1", + "IOI_IDELAY1_CE", + "IOI_WL1END0_0", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IDELAY0_INC", + "IOI_SE4C0_1", + "IOI_OLOGIC1_T3", + "IOI_LH10_0", + "IOI_EE4A3_0", + "LIOI_OLOGIC1_OQ", + "IOI_ILOGIC1_CE1", + "IOI_FAN7_1", + "IOI_WW4B3_0", + "LIOI_PD_INT_EN_0", + "LIOI_T0", + "IOI_WL1END0_1", + "IOI_IMUX45_0", + "IOI_ODELAY1_C", + "IOI_LH12_1", + "IOI_WW2END3_0", + "IOI_WR1END2_0", + "IOI_IMUX11_0", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_NE2A0_0", + "IOI_NW4END0_1", + "IOI_WW4A2_1", + "IOI_EL1BEG3_1", + "LIOI_PU_INT_EN_1", + "IOI_EE2A3_1", + "LIOI_ILOGIC0_DDLY", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_WR1END2_1", + "IOI_ODELAY0_LD", + "IOI_MONITOR_P", + "IOI_EE4BEG3_1", + "IOI_WW2END0_1", + "IOI_OLOGIC0_CLKB", + "IOI_RCLK_DIV_CE2", + "IOI_OLOGIC1_D2", + "IOI_LH11_1", + "IOI_IMUX34_0", + "IOI_LH9_1", + "IOI_BYP6_0", + "IOI_ILOGIC1_BITSLIP", + "LIOI_ILOGIC1_TFB", + "IOI_SE4BEG3_1", + "IOI_TBYTEIN", + "IOI_WW4B2_1", + "IOI_ODELAY1_CNTVALUEOUT4", + "IOI_IMUX14_0", + "LIOI_ILOGIC0_TFB", + "LIOI_OLOGIC0_TFB", + "IOI_LOGIC_OUTS12_0", + "IOI_NW4A3_0", + "IOI_SE4C0_0", + "IOI_NE2A1_1", + "IOI_LOGIC_OUTS20_1", + "IOI_SW4A3_0", + "IOI_SE4C2_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_BLOCK_OUTS1_1", + "IOI_EE4A0_1", + "IOI_WL1END3_0", + "IOI_WW2A3_0", + "IOI_CLK0_0", + "LIOI_DIFF_TERM_INT_EN", + "IOI_NE4BEG1_0", + "IOI_OLOGIC1_TCE", + "IOI_OLOGIC1_D3", + "IOI_LOGIC_OUTS6_0", + "IOI_IMUX2_1", + "LIOI_IDELAY0_DATAOUT", + "IOI_ODELAY1_CNTVALUEOUT1", + "IOI_IMUX44_1", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE4A3_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX5_1", + "IOI_EE2A1_1", + "IOI_WW4B3_1", + "IOI_ILOGIC1_Q4", + "LIOI_ODELAY1_OFDLY0", + "IOI_WW2A1_1", + "IOI_INT_DCI_EN", + "IOI_IMUX47_1", + "IOI_IMUX3_1", + "IOI_IMUX6_1", + "LIOI_ODELAY0_OFDLY1", + "IOI_NE2A2_0", + "IOI_WW4B2_0", + "IOI_FAN6_1", + "IOI_BLOCK_OUTS3_0", + "IOI_IDELAY0_DATAIN", + "IOI_EE4B0_1", + "IOI_LOGIC_OUTS13_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_LH11_0", + "IOI_LH10_1", + "IOI_NW4A0_0", + "IOI_BYP2_1", + "IOI_LOGIC_OUTS5_1", + "IOI_NW4END2_0", + "IOI_WW4C1_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WR1END1_1", + "IOI_LOGIC_OUTS16_1", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC1_CLK", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_IMUX7_0", + "IOI_FAN1_0", + "IOI_IMUX41_1", + "IOI_WW2A3_1", + "IOI_SE2A3_1", + "LIOI_ODELAY0_ODATAIN", + "IOI_LOGIC_OUTS2_1", + "IOI_CTRL1_0", + "IOI_RCLK_FORIO0", + "IOI_IMUX8_1", + "IOI_SW4A0_0", + "IOI_BLOCK_OUTS1_0", + "IOI_WW4A3_0", + "IOI_ER1BEG0_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_RCLK_DIV_CLR1_1", + "LIOI_KEEPER_INT_EN_0", + "IOI_RCLK_DIV_CLR2", + "IOI_NW4A1_1", + "IOI_EL1BEG1_0", + "LIOI_ODELAY0_DATAOUT", + "LIOI_OLOGIC1_CLKDIVF", + "IOI_FAN2_0", + "IOI_CTRL0_0", + "IOI_ILOGIC1_Q5", + "IOI_SE4BEG1_0", + "IOI_OLOGIC0_SR", + "IOI_ODELAY1_LDPIPEEN", + "IOI_LH2_0", + "IOI_EE4C3_1", + "IOI_ODELAY0_CE", + "IOI_EE2A3_0", + "IOI_OLOGIC1_D1", + "IOI_NW4A0_1", + "IOI_LOGIC_OUTS3_0", + "IOI_EE4C0_1", + "IOI_ILOGIC1_CLK", + "IOI_SW4END2_1", + "IOI_WW4C2_0", + "IOI_IMUX33_1", + "IOI_WW2END1_0", + "LIOI_KEEPER_INT_EN_1", + "LIOI_OLOGIC0_TQ", + "IOI_SE2A0_1", + "IOI_LOGIC_OUTS8_1", + "IOI_LH5_0", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_ILOGIC0_Q1", + "IOI_OLOGIC1_CLKDIVB", + "IOI_NE4C1_1", + "IOI_NE4BEG0_1", + "IOI_OLOGIC1_SR", + "IOI_EE4B1_1", + "IOI_IMUX14_1", + "IOI_ODELAY0_C", + "IOI_IMUX35_0", + "IOI_RCLK_DIV_CLR0", + "IOI_ILOGIC1_SR", + "LIOI_IBUF_DISABLE1", + "IOI_NE4BEG1_1", + "IOI_BYP6_1", + "IOI_ER1BEG2_1", + "IOI_IMUX4_0", + "IOI_EE4BEG2_0", + "IOI_LOGIC_OUTS4_0", + "IOI_NE2A2_1", + "LIOI_IBUF1", + "IOI_LOGIC_OUTS7_1", + "IOI_IMUX24_1", + "IOI_IMUX18_0", + "IOI_NE4C1_0", + "IOI_EE4BEG1_1", + "IOI_BYP4_0", + "IOI_EE2A2_1", + "IOI_ER1BEG1_0", + "IOI_WL1END1_1", + "IOI_IMUX31_0", + "IOI_ER1BEG2_0", + "IOI_IMUX28_1", + "IOI_WW4C0_1", + "IOI_SE4C2_0", + "IOI_LOGIC_OUTS17_1", + "IOI_ODELAY0_CNTVALUEIN0", + "LIOI_OLOGIC1_TFB", + "IOI_IMUX_RC2", + "IOI_WW4END2_0" + ], + "tile_type": "LIOI3", + "sites": [ + { + "site_pins": { + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "T2": "IOI_OLOGIC1_T2", + "T4": "IOI_OLOGIC1_T4", + "OFB": "LIOI_OLOGIC1_OFB", + "D1": "IOI_OLOGIC1_D1", + "CLK": "IOI_OLOGIC1_CLK", + "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", + "D8": "IOI_OLOGIC1_D8", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "SR": "IOI_OLOGIC1_SR", + "T1": "IOI_OLOGIC1_T1", + "D5": "IOI_OLOGIC1_D5", + "D4": "IOI_OLOGIC1_D4", + "TCE": "IOI_OLOGIC1_TCE", + "SHIFTIN1": null, + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "OQ": "LIOI_OLOGIC1_OQ", + "SHIFTOUT2": "LIOI_OSOUT21", + "OCE": "IOI_OLOGIC1_OCE", + "TFB": "LIOI_OLOGIC1_TFB", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "D7": "IOI_OLOGIC1_D7", + "CLKB": "IOI_OLOGIC1_CLKB", + "D2": "IOI_OLOGIC1_D2", + "T3": "IOI_OLOGIC1_T3", + "D6": "IOI_OLOGIC1_D6", + "D3": "IOI_OLOGIC1_D3", + "TQ": "LIOI_OLOGIC1_TQ", + "SHIFTOUT1": "LIOI_OSOUT11", + "REV": null, + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "SHIFTIN2": null, + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "CLK": "IOI_ILOGIC1_CLK", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "Q3": "IOI_ILOGIC1_Q3", + "CE1": "IOI_ILOGIC1_CE1", + "D": "LIOI_ILOGIC1_D", + "SR": "IOI_ILOGIC1_SR", + "TFB": "LIOI_ILOGIC1_TFB", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "Q8": "IOI_ILOGIC1_Q8", + "Q7": "IOI_ILOGIC1_Q7", + "Q2": "IOI_ILOGIC1_Q2", + "CE2": "IOI_ILOGIC1_CE2", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "SHIFTOUT2": "LIOI_ISOUT21", + "O": "IOI_ILOGIC1_O", + "OFB": "LIOI_ILOGIC1_OFB", + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "Q4": "IOI_ILOGIC1_Q4", + "CLKB": "IOI_ILOGIC1_CLKB", + "Q1": "IOI_ILOGIC1_Q1", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN1": "LIOI_ISIN11", + "Q6": "IOI_ILOGIC1_Q6", + "DDLY": "LIOI_ILOGIC1_DDLY", + "SHIFTOUT1": "LIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "REV": null, + "SHIFTIN2": "LIOI_ISIN21", + "OCLKB": "IOI_ILOGIC1_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "T2": "IOI_OLOGIC0_T2", + "T4": "IOI_OLOGIC0_T4", + "OFB": "LIOI_OLOGIC0_OFB", + "D1": "IOI_OLOGIC0_D1", + "CLK": "IOI_OLOGIC0_CLK", + "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", + "D8": "IOI_OLOGIC0_D8", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "SR": "IOI_OLOGIC0_SR", + "T1": "IOI_OLOGIC0_T1", + "D5": "IOI_OLOGIC0_D5", + "D4": "IOI_OLOGIC0_D4", + "TCE": "IOI_OLOGIC0_TCE", + "SHIFTIN1": "LIOI_OSIN10", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "OQ": "LIOI_OLOGIC0_OQ", + "SHIFTOUT2": "LIOI_OSOUT20", + "OCE": "IOI_OLOGIC0_OCE", + "TFB": "LIOI_OLOGIC0_TFB", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "D7": "IOI_OLOGIC0_D7", + "CLKB": "IOI_OLOGIC0_CLKB", + "D2": "IOI_OLOGIC0_D2", + "T3": "IOI_OLOGIC0_T3", + "D6": "IOI_OLOGIC0_D6", + "D3": "IOI_OLOGIC0_D3", + "TQ": "LIOI_OLOGIC0_TQ", + "SHIFTOUT1": "LIOI_OSOUT10", + "REV": null, + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "SHIFTIN2": "LIOI_OSIN20", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "CLK": "IOI_ILOGIC0_CLK", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "Q3": "IOI_ILOGIC0_Q3", + "CE1": "IOI_ILOGIC0_CE1", + "D": "LIOI_ILOGIC0_D", + "SR": "IOI_ILOGIC0_SR", + "TFB": "LIOI_ILOGIC0_TFB", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "Q8": "IOI_ILOGIC0_Q8", + "Q7": "IOI_ILOGIC0_Q7", + "Q2": "IOI_ILOGIC0_Q2", + "CE2": "IOI_ILOGIC0_CE2", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "SHIFTOUT2": "LIOI_ISOUT20", + "O": "IOI_ILOGIC0_O", + "OFB": "LIOI_ILOGIC0_OFB", + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "Q4": "IOI_ILOGIC0_Q4", + "CLKB": "IOI_ILOGIC0_CLKB", + "Q1": "IOI_ILOGIC0_Q1", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN1": null, + "Q6": "IOI_ILOGIC0_Q6", + "DDLY": "LIOI_ILOGIC0_DDLY", + "SHIFTOUT1": "LIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "REV": null, + "SHIFTIN2": null, + "OCLKB": "IOI_ILOGIC0_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "IFDLY0": "LIOI3_IDELAY1_IFDLY0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", + "LD": "IOI_IDELAY1_LD", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "IDATAIN": "LIOI_IDELAY1_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY1_DATAIN", + "DATAOUT": "LIOI_IDELAY1_DATAOUT", + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "IFDLY2": "LIOI3_IDELAY1_IFDLY2", + "C": "IOI_IDELAY1_C", + "IFDLY1": "LIOI3_IDELAY1_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "CE": "IOI_IDELAY1_CE" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "IFDLY0": "LIOI3_IDELAY0_IFDLY0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", + "LD": "IOI_IDELAY0_LD", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "IDATAIN": "LIOI_IDELAY0_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY0_DATAIN", + "DATAOUT": "LIOI_IDELAY0_DATAOUT", + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "IFDLY2": "LIOI3_IDELAY0_IFDLY2", + "C": "IOI_IDELAY0_C", + "IFDLY1": "LIOI3_IDELAY0_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "CE": "IOI_IDELAY0_CE" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_LIOI3_SING.json b/artix7/tile_type_LIOI3_SING.json index 233f430..4fcf6e5 100644 --- a/artix7/tile_type_LIOI3_SING.json +++ b/artix7/tile_type_LIOI3_SING.json @@ -1,1878 +1,1878 @@ { - "wires": [ - "IOI_LOGIC_OUTS2_0", - "IOI_WW4A1_0", - "IOI_IMUX7_0", - "IOI_SE4BEG2_0", - "IOI_ILOGIC0_CLK", - "IOI_SING_RCLK_FORIO3", - "IOI_NW4A2_0", - "IOI_NW4END1_0", - "IOI_LOGIC_OUTS11_0", - "IOI_SE4C0_0", - "IOI_LOGIC_OUTS17_0", - "IOI_WR1END3_0", - "IOI_NE2A2_0", - "IOI_ILOGIC0_CLKDIV", - "IOI_IMUX20_0", - "IOI_OLOGIC0_TCE", - "IOI_EE2BEG2_0", - "LIOI_OLOGIC0_CLKDIVF", - "IOI_LH10_0", - "LIOI_ILOGIC0_TFB", - "LIOI_OLOGIC0_OFB", - "IOI_ILOGIC0_CE2", - "IOI_ODELAY0_C", - "LIOI_ODELAY0_OFDLY0", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_SING_LEAF_GCLK4", - "IOI_IMUX5_0", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_SW4END0_0", - "IOI_IMUX35_0", - "IOI_WW4B3_0", - "IOI_OLOGIC0_D2", - "IOI_SING_TBYTEIN", - "IOI_OLOGIC0_CLKDIV", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_SE4C1_0", - "IOI_ODELAY0_CE", - "IOI_NE2A1_0", - "IOI_IMUX1_0", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_REV", - "IOI_IMUX0_0", - "IOI_ER1BEG0_0", - "IOI_IMUX36_0", - "IOI_ILOGIC0_BITSLIP", - "IOI_NE4C3_0", - "IOI_IMUX10_0", - "IOI_EE4B3_0", - "IOI_LH4_0", - "IOI_LOGIC_OUTS20_0", - "IOI_NW4END2_0", - "IOI_OLOGIC0_SR", - "IOI_LH1_0", - "IOI_BLOCK_OUTS1_0", - "IOI_WW4B1_0", - "LIOI_KEEPER_INT_EN_1", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_LH2_0", - "IOI_ODELAY0_LD", - "IOI_WW4A3_0", - "IOI_OLOGIC0_OCE", - "IOI_IMUX8_0", - "IOI_CTRL0_0", - "IOI_LOGIC_OUTS8_0", - "IOI_ILOGIC0_CLKB", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_SW2A2_0", - "IOI_NE2A0_0", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_INC", - "IOI_OLOGIC0_T4", - "IOI_ER1BEG1_0", - "LIOI_OLOGIC0_OQ", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ILOGIC0_O", - "IOI_EL1BEG2_0", - "IOI_EE4A1_0", - "IOI_SW4A1_0", - "IOI_NE4BEG2_0", - "IOI_SW2A0_0", - "IOI_IMUX24_0", - "LIOI_OSOUT20", - "IOI_FAN5_0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_LOGIC_OUTS21_0", - "IOI_WW4C3_0", - "IOI_OLOGIC0_D7", - "IOI_IMUX37_0", - "IOI_IMUX6_0", - "IOI_LOGIC_OUTS4_0", - "IOI_ILOGIC0_Q8", - "IOI_WW2A2_0", - "IOI_NW4END0_0", - "IOI_BLOCK_OUTS3_0", - "IOI_IMUX38_0", - "IOI_IDELAY0_CINVCTRL", - "LIOI_IBUF_DISABLE0", - "LIOI_OLOGIC0_TFB_LOCAL", - "LIOI3_IDELAY0_IFDLY1", - "IOI_IMUX30_0", - "LIOI_IDELAY0_IDATAIN", - "IOI_IMUX33_0", - "IOI_EE4A2_0", - "IOI_IMUX4_0", - "IOI_SW4END2_0", - "LIOI_PD_INT_EN_1", - "IOI_IMUX31_0", - "IOI_IMUX15_0", - "LIOI_ISIN10", - "IOI_ILOGIC0_Q2", - "IOI_EE4C3_0", - "IOI_NE4BEG1_0", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_BYP7_0", - "IOI_SW4A2_0", - "IOI_IMUX42_0", - "IOI_SING_LEAF_GCLK5", - "IOI_WR1END0_0", - "LIOI_OSOUT10", - "IOI_NE4C1_0", - "IOI_IDELAY0_C", - "IOI_IMUX29_0", - "IOI_SE2A2_0", - "IOI_LOGIC_OUTS13_0", - "IOI_BYP4_0", - "IOI_OLOGIC0_REV", - "IOI_LOGIC_OUTS6_0", - "IOI_WW2A1_0", - "IOI_SING_IOCLK1", - "IOI_IDELAY0_DATAIN", - "IOI_SW4A3_0", - "IOI_EE4BEG2_0", - "IOI_LH7_0", - "IOI_WW4C1_0", - "IOI_IMUX9_0", - "IOI_BYP5_0", - "IOI_ER1BEG3_0", - "IOI_LOGIC_OUTS18_0", - "IOI_NW4A0_0", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ILOGIC0_Q3", - "IOI_IDELAY0_LDPIPEEN", - "IOI_WW2END2_0", - "IOI_IMUX12_0", - "IOI_IMUX23_0", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS23_0", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_WW4A0_0", - "IOI_SE2A0_0", - "IOI_WW2END3_0", - "IOI_IMUX21_0", - "IOI_SING_IOCLK2", - "IOI_NE4BEG3_0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_EE4BEG0_0", - "LIOI_ODELAY0_DATAOUT", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CE", - "IOI_NW4END3_0", - "IOI_SE4C3_0", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_BYP3_0", - "IOI_NW4A1_0", - "IOI_SE4BEG0_0", - "IOI_IMUX14_0", - "LIOI_O0", - "IOI_CLK1_0", - "IOI_SE4BEG3_0", - "IOI_LOGIC_OUTS0_0", - "IOI_WW2END1_0", - "IOI_OLOGIC0_D6", - "IOI_EE2A3_0", - "IOI_IMUX28_0", - "IOI_OCLK_0", - "IOI_LOGIC_OUTS16_0", - "IOI_IMUX18_0", - "IOI_NW4A3_0", - "IOI_WW4A2_0", - "IOI_NE4C0_0", - "IOI_IDELAY0_LD", - "IOI_EE2A0_0", - "IOI_NW2A1_0", - "IOI_IMUX44_0", - "IOI_LOGIC_OUTS9_0", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_IMUX16_0", - "IOI_WL1END3_0", - "IOI_EE2A1_0", - "IOI_FAN1_0", - "IOI_LOGIC_OUTS7_0", - "IOI_EE4A0_0", - "IOI_LOGIC_OUTS22_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_SING_LEAF_GCLK2", - "IOI_IMUX11_0", - "IOI_WW4C2_0", - "IOI_NW2A3_0", - "IOI_IMUX34_0", - "IOI_WR1END2_0", - "LIOI_ILOGIC0_OFB", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_SW4A0_0", - "IOI_IMUX22_0", - "LIOI_OLOGIC0_TFB", - "IOI_WR1END1_0", - "IOI_OLOGIC0_T3", - "IOI_IMUX17_0", - "IOI_EE4B0_0", - "LIOI_ISIN20", - "IOI_WW4B2_0", - "IOI_FAN6_0", - "IOI_WL1END0_0", - "IOI_OCLKM_0", - "IOI_SING_LEAF_GCLK1", - "IOI_CLK0_0", - "IOI_EL1BEG0_0", - "IOI_LOGIC_OUTS15_0", - "IOI_OLOGIC0_CLK", - "IOI_IMUX39_0", - "IOI_WL1END1_0", - "IOI_WW4B0_0", - "IOI_WL1END2_0", - "IOI_IMUX41_0", - "IOI_EE4C0_0", - "IOI_SING_RCLK_FORIO0", - "LIOI_PU_INT_EN_1", - "IOI_NW2A0_0", - "IOI_WW4END3_0", - "LIOI_I0", - "IOI_SE2A3_0", - "IOI_WW2A3_0", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_OLOGIC0_D4", - "IOI_ILOGIC0_CE1", - "IOI_SE4BEG1_0", - "LIOI_ISOUT20", - "IOI_EE2BEG3_0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_EL1BEG1_0", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_ER1BEG2_0", - "LIOI_ODELAY0_ODATAIN", - "IOI_WW4C0_0", - "IOI_ILOGIC0_Q5", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_EE4BEG3_0", - "IOI_IMUX25_0", - "IOI_NE4BEG0_0", - "IOI_SW4END1_0", - "IOI_FAN0_0", - "IOI_WW4END0_0", - "IOI_EE4BEG1_0", - "LIOI_OSIN10", - "IOI_FAN7_0", - "IOI_LOGIC_OUTS1_0", - "LIOI_ILOGIC0_DDLY", - "IOI_EE2BEG0_0", - "LIOI_ISOUT10", - "LIOI_ILOGIC0_D", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC0_OCLKB", - "IOI_EE4C1_0", - "IOI_BYP2_0", - "LIOI_IBUF0", - "IOI_SING_LEAF_GCLK0", - "IOI_IMUX43_0", - "IOI_IMUX46_0", - "IOI_IMUX27_0", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_D8", - "IOI_NW2A2_0", - "IOI_EE4C2_0", - "IOI_LH11_0", - "IOI_ILOGIC0_Q6", - "IOI_CTRL1_0", - "IOI_SING_IOCLK3", - "LIOI_OLOGIC0_TQ", - "IOI_EE4A3_0", - "LIOI_ODELAY0_OFDLY2", - "IOI_OLOGIC0_CLKB", - "IOI_IMUX40_0", - "IOI_LH5_0", - "IOI_IMUX47_0", - "IOI_PHASER_TO_IO_OCLK", - "LIOI_OSIN20", - "IOI_LOGIC_OUTS12_0", - "IOI_FAN2_0", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_LOGIC_OUTS5_0", - "IOI_SING_LEAF_GCLK3", - "IOI_FAN4_0", - "IOI_IMUX2_0", - "IOI_WW2END0_0", - "IOI_BLOCK_OUTS2_0", - "IOI_WW4END1_0", - "IOI_EE4B1_0", - "IOI_OLOGIC0_T1", - "IOI_IMUX3_0", - "IOI_ODELAY0_CLKIN", - "IOI_EE4B2_0", - "IOI_SE2A1_0", - "IOI_SING_RCLK_FORIO1", - "IOI_BYP6_0", - "IOI_EE2BEG1_0", - "IOI_IMUX32_0", - "IOI_WW2A0_0", - "IOI_ILOGIC0_Q7", - "IOI_PHASER_TO_IO_ICLK", - "IOI_NE4C2_0", - "IOI_EL1BEG3_0", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_FAN3_0", - "IOI_SW4END3_0", - "LIOI3_IDELAY0_IFDLY0", - "IOI_ODELAY0_LDPIPEEN", - "LIOI3_IDELAY0_IFDLY2", - "IOI_SE4C2_0", - "IOI_ODELAY0_INC", - "IOI_BYP1_0", - "IOI_NE2A3_0", - "IOI_ODELAY0_REGRST", - "IOI_SING_RCLK_FORIO2", - "IOI_SW2A3_0", - "IOI_ILOGIC0_CLKDIVP", - "IOI_LOGIC_OUTS19_0", - "IOI_EE2A2_0", - "IOI_OLOGIC0_D1", - "IOI_LH9_0", - "IOI_LH6_0", - "IOI_IMUX19_0", - "IOI_LH8_0", - "IOI_LOGIC_OUTS10_0", - "IOI_ILOGIC0_OCLK", - "IOI_OLOGIC0_CLKDIVFB", - "LIOI_IDELAY0_DATAOUT", - "IOI_SW2A1_0", - "IOI_LOGIC_OUTS14_0", - "IOI_OLOGIC0_T2", - "IOI_BLOCK_OUTS0_0", - "LIOI_DCI_T_TERM0", - "IOI_LH3_0", - "IOI_LH12_0", - "IOI_SING_IOCLK0", - "IOI_IMUX26_0", - "IOI_IMUX45_0", - "IOI_IMUX13_0", - "IOI_ODELAY0_CINVCTRL", - "IOI_BYP0_0", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ILOGIC0_Q4", - "LIOI_T0", - "IOI_WW4END2_0", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_TBYTEIN", - "LIOI_ODELAY0_OFDLY1" - ], - "sites": [ - { - "prefix": "OLOGIC", - "y_coord": 0, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC0_D1", - "D3": "IOI_OLOGIC0_D3", - "SR": "IOI_OLOGIC0_SR", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "TFB": "LIOI_OLOGIC0_TFB", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLK": "IOI_OLOGIC0_CLK", - "T4": "IOI_OLOGIC0_T4", - "OQ": "LIOI_OLOGIC0_OQ", - "D8": "IOI_OLOGIC0_D8", - "T1": "IOI_OLOGIC0_T1", - "D5": "IOI_OLOGIC0_D5", - "SHIFTOUT1": "LIOI_OSOUT10", - "T2": "IOI_OLOGIC0_T2", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "D4": "IOI_OLOGIC0_D4", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D2": "IOI_OLOGIC0_D2", - "TQ": "LIOI_OLOGIC0_TQ", - "T3": "IOI_OLOGIC0_T3", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "OCE": "IOI_OLOGIC0_OCE", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "SHIFTIN1": null, - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "TCE": "IOI_OLOGIC0_TCE", - "OFB": "LIOI_OLOGIC0_OFB", - "SHIFTIN2": null, - "SHIFTOUT2": "LIOI_OSOUT20", - "REV": null, - "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "ILOGIC", - "y_coord": 0, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q1": "IOI_ILOGIC0_Q1", - "SR": "IOI_ILOGIC0_SR", - "D": "LIOI_ILOGIC0_D", - "DDLY": "LIOI_ILOGIC0_DDLY", - "SHIFTIN2": null, - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "Q3": "IOI_ILOGIC0_Q3", - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "Q8": "IOI_ILOGIC0_Q8", - "TFB": "LIOI_ILOGIC0_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC0_CE1", - "Q2": "IOI_ILOGIC0_Q2", - "Q6": "IOI_ILOGIC0_Q6", - "CLKB": "IOI_ILOGIC0_CLKB", - "Q7": "IOI_ILOGIC0_Q7", - "O": "IOI_ILOGIC0_O", - "CLK": "IOI_ILOGIC0_CLK", - "CE2": "IOI_ILOGIC0_CE2", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "SHIFTIN1": null, - "OCLK": "IOI_ILOGIC0_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "OFB": "LIOI_ILOGIC0_OFB", - "SHIFTOUT1": "LIOI_ISOUT10", - "SHIFTOUT2": "LIOI_ISOUT20", - "REV": null, - "CLKDIV": "IOI_ILOGIC0_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IDELAY", - "y_coord": 0, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CE": "IOI_IDELAY0_CE", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "IFDLY2": "LIOI3_IDELAY0_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "LD": "IOI_IDELAY0_LD", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "IFDLY0": "LIOI3_IDELAY0_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "INC": "IOI_IDELAY0_INC", - "DATAOUT": "LIOI_IDELAY0_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY0_DATAIN", - "C": "IOI_IDELAY0_C", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "IDATAIN": "LIOI_IDELAY0_IDATAIN", - "REGRST": "IOI_IDELAY0_REGRST", - "IFDLY1": "LIOI3_IDELAY0_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "LIOI3_SING.IOI_SING_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_FAN4_0->LIOI3_IDELAY0_IFDLY0": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q4", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OFB", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_FAN5_0->LIOI3_IDELAY0_IFDLY1": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_0", - "is_pseudo": "0" - }, "LIOI3_SING.IOI_IMUX31_0->>IOI_OCLKM_0": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", - "src_wire": "IOI_SING_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX6_0->LIOI_DCI_T_TERM0": { - "can_invert": "0", - "dst_wire": "LIOI_DCI_T_TERM0", - "is_directional": "1", - "src_wire": "IOI_IMUX6_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_OLOGIC0_TQ->>LIOI_T0": { - "can_invert": "0", - "dst_wire": "LIOI_T0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TQ", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY0_DATAOUT", - "is_directional": "1", - "src_wire": "LIOI_IDELAY0_IDATAIN", - "is_pseudo": "1" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q6", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_0", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_I0->LIOI_ILOGIC0_D": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_D", - "is_directional": "1", - "src_wire": "LIOI_I0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "LIOI3_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX31_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q5", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q7", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX35_0->IOI_IDELAY0_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_SING_TBYTEIN", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC0_DDLY", - "is_pseudo": "1" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "LIOI3_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_IBUF0->LIOI_I0": { - "can_invert": "0", - "dst_wire": "LIOI_I0", - "is_directional": "1", - "src_wire": "LIOI_IBUF0", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TQ", - "is_pseudo": "1" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_BYP7_0->LIOI3_IDELAY0_IFDLY2": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OQ", - "is_pseudo": "1" - }, - "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC0_D", - "is_pseudo": "1" - }, - "LIOI3_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q8", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX8_0->LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_0", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_OLOGIC0_OQ->>LIOI_O0": { - "can_invert": "0", - "dst_wire": "LIOI_O0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OQ", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" }, "LIOI3_SING.IOI_IMUX26_0->IOI_IDELAY0_INC": { "can_invert": "0", - "dst_wire": "IOI_IDELAY0_INC", - "is_directional": "1", "src_wire": "IOI_IMUX26_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", - "src_wire": "IOI_SING_IOCLK1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" }, - "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", - "dst_wire": "IOI_OCLK_0", + "src_wire": "IOI_SING_LEAF_GCLK0", "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" }, - "LIOI3_SING.IOI_CLK1_0->IOI_IDELAY0_C": { + "LIOI3_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", - "dst_wire": "IOI_IDELAY0_C", + "src_wire": "IOI_ILOGIC0_Q5", "is_directional": "1", - "src_wire": "IOI_CLK1_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_0", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_DDLY", - "is_directional": "1", - "src_wire": "LIOI_IDELAY0_DATAOUT", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX9_0->LIOI_IBUF_DISABLE0": { - "can_invert": "0", - "dst_wire": "LIOI_IBUF_DISABLE0", - "is_directional": "1", - "src_wire": "IOI_IMUX9_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" }, - "LIOI3_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { + "LIOI3_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_0", + "src_wire": "IOI_IMUX45_0", "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6" }, - "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { + "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", + "src_wire": "IOI_SING_IOCLK0", "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" }, "LIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", "src_wire": "IOI_SING_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" }, - "LIOI3_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLK_0": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T1", + "src_wire": "IOI_SING_RCLK_FORIO2", "is_directional": "1", - "src_wire": "IOI_IMUX15_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" }, - "LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { + "LIOI3_SING.LIOI_OLOGIC0_TQ->>LIOI_T0": { "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_TFB", + "src_wire": "LIOI_OLOGIC0_TQ", "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "LIOI_T0" }, - "LIOI3_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_SING.LIOI_I0->LIOI_IDELAY0_IDATAIN": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY0_IDATAIN", - "is_directional": "1", - "src_wire": "LIOI_I0", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_SING.IOI_SING_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL" + }, + "LIOI3_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "LIOI3_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD" + }, + "LIOI3_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP" + }, + "LIOI3_SING.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY0_DATAOUT" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1" + }, + "LIOI3_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2" + }, + "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK" + }, + "LIOI3_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "LIOI3_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "LIOI3_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "LIOI3_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.LIOI_IBUF0->LIOI_I0": { + "can_invert": "0", + "src_wire": "LIOI_IBUF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_I0" + }, + "LIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_IMUX35_0->IOI_IDELAY0_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0" + }, + "LIOI3_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { + "can_invert": "0", + "src_wire": "IOI_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OQ" + }, + "LIOI3_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "LIOI_ILOGIC0_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5" + }, + "LIOI3_SING.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB" + }, + "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3" + }, + "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.LIOI_OLOGIC0_OQ->>LIOI_O0": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_O0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_DDLY" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_IMUX6_0->LIOI_DCI_T_TERM0": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8" + }, + "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_IMUX9_0->LIOI_IBUF_DISABLE0": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE0" + }, + "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB" + }, + "LIOI3_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4" + }, + "LIOI3_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0" + }, + "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0" + }, + "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL" + }, + "LIOI3_SING.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "LIOI_ILOGIC0_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_IMUX8_0->LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0" + }, + "LIOI3_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_SING_TBYTEIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0" + }, + "LIOI3_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4" + }, + "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE" + }, + "LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_TFB" + }, + "LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.LIOI_I0->LIOI_ILOGIC0_D": { + "can_invert": "0", + "src_wire": "LIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_D" + }, + "LIOI3_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE" + }, + "LIOI3_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3" + }, + "LIOI3_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0" + }, + "LIOI3_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "LIOI3_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR" + }, + "LIOI3_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN" + }, + "LIOI3_SING.IOI_FAN4_0->LIOI3_IDELAY0_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK" + }, + "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_BYP7_0->LIOI3_IDELAY0_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY2" + }, + "LIOI3_SING.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_OFB" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_SING.IOI_FAN5_0->LIOI3_IDELAY0_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY1" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_CLK1_0->IOI_IDELAY0_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C" + }, + "LIOI3_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE" + }, + "LIOI3_SING.LIOI_I0->LIOI_IDELAY0_IDATAIN": { + "can_invert": "0", + "src_wire": "LIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY0_IDATAIN" + }, + "LIOI3_SING.IOI_IMUX31_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TQ" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1" + }, + "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1" } }, - "tile_type": "LIOI3_SING" + "wires": [ + "IOI_IMUX42_0", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_EL1BEG3_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_ILOGIC0_CE2", + "IOI_IMUX39_0", + "IOI_SING_IOCLK2", + "IOI_WR1END0_0", + "IOI_IMUX5_0", + "IOI_IMUX19_0", + "IOI_BYP1_0", + "IOI_ILOGIC0_Q2", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_IMUX23_0", + "IOI_SING_LEAF_GCLK4", + "IOI_IDELAY0_C", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_SW4END2_0", + "IOI_SW4END0_0", + "IOI_WW4END1_0", + "IOI_IMUX38_0", + "IOI_SW2A0_0", + "IOI_IMUX46_0", + "IOI_WR1END1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_LOGIC_OUTS1_0", + "IOI_IMUX8_0", + "IOI_BYP2_0", + "LIOI_ISOUT20", + "IOI_OLOGIC0_T4", + "IOI_NE4C2_0", + "IOI_NE4C3_0", + "IOI_IMUX27_0", + "IOI_IMUX22_0", + "IOI_NW4A1_0", + "IOI_SE2A1_0", + "IOI_EL1BEG2_0", + "IOI_SW4A1_0", + "IOI_LOGIC_OUTS9_0", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_ODELAY0_LDPIPEEN", + "IOI_EE2A0_0", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_IMUX1_0", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_EE4C2_0", + "IOI_EE2BEG1_0", + "IOI_LOGIC_OUTS20_0", + "IOI_WL1END2_0", + "IOI_EE2BEG0_0", + "IOI_FAN5_0", + "IOI_EE2A2_0", + "IOI_WW4C0_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_OLOGIC0_CLKDIV", + "LIOI_I0", + "LIOI_ODELAY0_OFDLY2", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_LOGIC_OUTS2_0", + "IOI_IMUX17_0", + "LIOI_ISIN20", + "IOI_WW2END2_0", + "IOI_FAN3_0", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_LOGIC_OUTS14_0", + "IOI_ILOGIC0_OCLK", + "IOI_IMUX30_0", + "IOI_NE4BEG0_0", + "IOI_FAN0_0", + "IOI_SE4BEG0_0", + "LIOI_ISIN10", + "IOI_EE2BEG3_0", + "IOI_LH7_0", + "IOI_ILOGIC0_Q3", + "IOI_EE4A1_0", + "IOI_BYP7_0", + "IOI_IMUX25_0", + "IOI_IDELAY0_REGRST", + "IOI_NW4A2_0", + "IOI_NW4END0_0", + "IOI_BYP5_0", + "IOI_ILOGIC0_OCLKB", + "IOI_IMUX37_0", + "IOI_IMUX47_0", + "IOI_OLOGIC0_D4", + "IOI_SE2A0_0", + "IOI_ILOGIC0_CLKB", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_SW4END3_0", + "IOI_EE4BEG3_0", + "IOI_ILOGIC0_Q7", + "IOI_IMUX16_0", + "LIOI_O0", + "IOI_WW4END0_0", + "IOI_BLOCK_OUTS2_0", + "LIOI_ODELAY0_OFDLY0", + "IOI_NW2A3_0", + "IOI_SING_LEAF_GCLK1", + "IOI_SING_RCLK_FORIO3", + "IOI_OLOGIC0_D3", + "IOI_EE4C0_0", + "IOI_ODELAY0_CNTVALUEOUT2", + "LIOI_OSOUT10", + "IOI_SE2A2_0", + "LIOI_OLOGIC0_OQ", + "IOI_ILOGIC0_Q6", + "IOI_OLOGIC0_TCE", + "IOI_WW2A0_0", + "IOI_SE4BEG3_0", + "LIOI_OSIN20", + "IOI_EE4C1_0", + "IOI_ODELAY0_CLKIN", + "IOI_IMUX36_0", + "IOI_LOGIC_OUTS5_0", + "IOI_LH8_0", + "IOI_IMUX15_0", + "IOI_IMUX12_0", + "IOI_EE4C3_0", + "IOI_ILOGIC0_O", + "LIOI3_IDELAY0_IFDLY1", + "IOI_BLOCK_OUTS0_0", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_SE4C3_0", + "IOI_IMUX32_0", + "IOI_CLK1_0", + "IOI_LH4_0", + "IOI_OLOGIC0_D7", + "LIOI_PD_INT_EN_1", + "IOI_IMUX10_0", + "IOI_WW4END3_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_ILOGIC0_REV", + "IOI_SING_LEAF_GCLK0", + "IOI_IMUX29_0", + "IOI_LOGIC_OUTS18_0", + "IOI_WL1END1_0", + "IOI_EL1BEG0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_OLOGIC0_T1", + "IOI_EE4BEG1_0", + "IOI_EE2A1_0", + "IOI_IMUX41_0", + "IOI_WW4C3_0", + "IOI_LOGIC_OUTS23_0", + "IOI_WW4B1_0", + "IOI_EE4A0_0", + "IOI_BYP3_0", + "IOI_FAN6_0", + "IOI_LOGIC_OUTS10_0", + "IOI_SING_IOCLK1", + "LIOI3_IDELAY0_IFDLY0", + "IOI_EE4B3_0", + "IOI_EE4BEG0_0", + "IOI_ODELAY0_INC", + "IOI_IMUX6_0", + "IOI_IDELAY0_LDPIPEEN", + "IOI_ILOGIC0_SR", + "IOI_IMUX40_0", + "IOI_WW4A0_0", + "IOI_WR1END3_0", + "IOI_WL1END0_0", + "IOI_OLOGIC0_REV", + "IOI_IDELAY0_INC", + "IOI_OLOGIC0_D1", + "IOI_LH10_0", + "IOI_EE4A3_0", + "IOI_WW4B3_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_NE4C0_0", + "LIOI_ISOUT10", + "LIOI_DCI_T_TERM0", + "LIOI_T0", + "IOI_SING_LEAF_GCLK3", + "IOI_IMUX45_0", + "IOI_IMUX33_0", + "IOI_IMUX13_0", + "IOI_IMUX9_0", + "IOI_OLOGIC0_T3", + "IOI_WW2END3_0", + "IOI_EE4A2_0", + "IOI_WR1END2_0", + "IOI_IMUX26_0", + "IOI_IMUX11_0", + "IOI_IMUX0_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX3_0", + "IOI_EE4B2_0", + "IOI_NE2A0_0", + "LIOI_IBUF_DISABLE0", + "IOI_OLOGIC0_OCE", + "IOI_ILOGIC0_CE1", + "LIOI_PU_INT_EN_1", + "LIOI_ILOGIC0_DDLY", + "LIOI_ILOGIC0_OFB", + "IOI_LOGIC_OUTS8_0", + "IOI_WW2END0_0", + "LIOI_IDELAY0_IDATAIN", + "IOI_SW2A1_0", + "IOI_ODELAY0_LD", + "IOI_SING_RCLK_FORIO0", + "IOI_LH3_0", + "IOI_OLOGIC0_CLKB", + "IOI_EE4B1_0", + "LIOI_ILOGIC0_D", + "IOI_SW4END1_0", + "IOI_WW4A2_0", + "IOI_ER1BEG3_0", + "IOI_LH6_0", + "IOI_IMUX34_0", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_BYP6_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_IMUX2_0", + "IOI_SING_LEAF_GCLK5", + "IOI_IMUX14_0", + "IOI_IDELAY0_CNTVALUEIN2", + "LIOI_ILOGIC0_TFB", + "IOI_IMUX44_0", + "IOI_NW2A2_0", + "LIOI_OLOGIC0_TFB", + "IOI_LOGIC_OUTS12_0", + "IOI_NW4A3_0", + "IOI_SE4C0_0", + "IOI_SING_IOCLK3", + "IOI_OLOGIC0_D6", + "IOI_IDELAY0_CINVCTRL", + "IOI_SW4A3_0", + "IOI_ODELAY0_CINVCTRL", + "IOI_WL1END3_0", + "LIOI_OLOGIC0_CLKDIVF", + "IOI_WW2A3_0", + "IOI_SE4BEG2_0", + "IOI_LOGIC_OUTS16_0", + "IOI_NW4END3_0", + "IOI_CLK0_0", + "IOI_NE4BEG1_0", + "IOI_NE4BEG2_0", + "IOI_ILOGIC0_CLKDIVP", + "IOI_LOGIC_OUTS7_0", + "IOI_LOGIC_OUTS6_0", + "LIOI_IDELAY0_DATAOUT", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS13_0", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_SING_RCLK_FORIO1", + "IOI_WW4B0_0", + "IOI_IMUX28_0", + "IOI_NW4END1_0", + "LIOI3_IDELAY0_IFDLY2", + "IOI_LOGIC_OUTS11_0", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_OLOGIC0_D8", + "LIOI_ODELAY0_OFDLY1", + "IOI_NE2A2_0", + "IOI_WW4B2_0", + "IOI_BLOCK_OUTS3_0", + "IOI_IMUX21_0", + "IOI_IDELAY0_DATAIN", + "IOI_EE4B0_0", + "IOI_FAN4_0", + "IOI_OLOGIC0_TBYTEIN", + "IOI_LH11_0", + "IOI_NW4A0_0", + "IOI_SW4A2_0", + "IOI_NW2A0_0", + "IOI_OCLKM_0", + "IOI_NW4END2_0", + "IOI_WW4C1_0", + "IOI_ILOGIC0_DYNCLKSEL", + "LIOI_OLOGIC0_OFB", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS21_0", + "IOI_IMUX7_0", + "IOI_FAN1_0", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "LIOI_ODELAY0_ODATAIN", + "IOI_NE2A1_0", + "IOI_IMUX43_0", + "IOI_CTRL1_0", + "IOI_LOGIC_OUTS17_0", + "IOI_SE2A3_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LH9_0", + "IOI_OLOGIC0_D2", + "IOI_OLOGIC0_CLKDIVB", + "IOI_SW4A0_0", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_BLOCK_OUTS1_0", + "IOI_LOGIC_OUTS0_0", + "IOI_WW2A1_0", + "IOI_WW4A3_0", + "IOI_SE4C1_0", + "IOI_ER1BEG0_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_ILOGIC0_Q4", + "IOI_IMUX20_0", + "IOI_OLOGIC0_D5", + "IOI_EL1BEG1_0", + "LIOI_ODELAY0_DATAOUT", + "IOI_FAN2_0", + "IOI_NW2A1_0", + "IOI_CTRL0_0", + "IOI_SE4BEG1_0", + "IOI_OLOGIC0_SR", + "IOI_LH2_0", + "IOI_WW2A2_0", + "IOI_ODELAY0_CE", + "IOI_EE2A3_0", + "IOI_ILOGIC0_Q8", + "IOI_IMUX24_0", + "IOI_OLOGIC0_T2", + "IOI_IDELAY0_LD", + "IOI_LOGIC_OUTS3_0", + "IOI_BYP0_0", + "IOI_WW4C2_0", + "IOI_WW2END1_0", + "LIOI_KEEPER_INT_EN_1", + "LIOI_OSOUT20", + "LIOI_OLOGIC0_TQ", + "IOI_EE2BEG2_0", + "IOI_NE2A3_0", + "IOI_NE4BEG3_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_LH5_0", + "IOI_LH12_0", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_ILOGIC0_Q1", + "IOI_IDELAY0_CE", + "IOI_SING_LEAF_GCLK2", + "LIOI_OSIN10", + "IOI_OLOGIC0_CLK", + "IOI_SW2A3_0", + "LIOI_IBUF0", + "IOI_ODELAY0_C", + "IOI_IMUX35_0", + "LIOI_OLOGIC0_TFB_LOCAL", + "IOI_SING_IOCLK0", + "IOI_LH1_0", + "IOI_IMUX4_0", + "IOI_EE4BEG2_0", + "IOI_LOGIC_OUTS4_0", + "IOI_SING_TBYTEIN", + "IOI_LOGIC_OUTS22_0", + "IOI_IMUX18_0", + "IOI_NE4C1_0", + "IOI_WW4A1_0", + "IOI_FAN7_0", + "IOI_BYP4_0", + "IOI_SING_RCLK_FORIO2", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_ER1BEG1_0", + "IOI_OCLK_0", + "IOI_ODELAY0_REGRST", + "IOI_IMUX31_0", + "IOI_ER1BEG2_0", + "IOI_LOGIC_OUTS15_0", + "IOI_SE4C2_0", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_WW4END2_0", + "IOI_ODELAY0_CNTVALUEIN2" + ], + "tile_type": "LIOI3_SING", + "sites": [ + { + "site_pins": { + "T2": "IOI_OLOGIC0_T2", + "D5": "IOI_OLOGIC0_D5", + "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", + "D8": "IOI_OLOGIC0_D8", + "SR": "IOI_OLOGIC0_SR", + "SHIFTOUT1": "LIOI_OSOUT10", + "T4": "IOI_OLOGIC0_T4", + "SHIFTIN1": null, + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "OCE": "IOI_OLOGIC0_OCE", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "CLKB": "IOI_OLOGIC0_CLKB", + "OQ": "LIOI_OLOGIC0_OQ", + "D3": "IOI_OLOGIC0_D3", + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "SHIFTIN2": null, + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "D1": "IOI_OLOGIC0_D1", + "CLK": "IOI_OLOGIC0_CLK", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "T1": "IOI_OLOGIC0_T1", + "D4": "IOI_OLOGIC0_D4", + "TCE": "IOI_OLOGIC0_TCE", + "D2": "IOI_OLOGIC0_D2", + "SHIFTOUT2": "LIOI_OSOUT20", + "OFB": "LIOI_OLOGIC0_OFB", + "TFB": "LIOI_OLOGIC0_TFB", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "T3": "IOI_OLOGIC0_T3", + "D6": "IOI_OLOGIC0_D6", + "TQ": "LIOI_OLOGIC0_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "CLK": "IOI_ILOGIC0_CLK", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "Q3": "IOI_ILOGIC0_Q3", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "D": "LIOI_ILOGIC0_D", + "SR": "IOI_ILOGIC0_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC0_CE1", + "Q8": "IOI_ILOGIC0_Q8", + "SHIFTIN2": null, + "Q2": "IOI_ILOGIC0_Q2", + "CE2": "IOI_ILOGIC0_CE2", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "SHIFTOUT2": "LIOI_ISOUT20", + "O": "IOI_ILOGIC0_O", + "OFB": "LIOI_ILOGIC0_OFB", + "TFB": "LIOI_ILOGIC0_TFB", + "Q4": "IOI_ILOGIC0_Q4", + "CLKB": "IOI_ILOGIC0_CLKB", + "Q1": "IOI_ILOGIC0_Q1", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN1": null, + "Q6": "IOI_ILOGIC0_Q6", + "DDLY": "LIOI_ILOGIC0_DDLY", + "SHIFTOUT1": "LIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC0_Q7", + "OCLKB": "IOI_ILOGIC0_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "IFDLY0": "LIOI3_IDELAY0_IFDLY0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", + "LD": "IOI_IDELAY0_LD", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "IDATAIN": "LIOI_IDELAY0_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "IFDLY2": "LIOI3_IDELAY0_IFDLY2", + "C": "IOI_IDELAY0_C", + "IFDLY1": "LIOI3_IDELAY0_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "DATAOUT": "LIOI_IDELAY0_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_LIOI3_TBYTESRC.json b/artix7/tile_type_LIOI3_TBYTESRC.json index 118c982..efd9458 100644 --- a/artix7/tile_type_LIOI3_TBYTESRC.json +++ b/artix7/tile_type_LIOI3_TBYTESRC.json @@ -1,3893 +1,3893 @@ { - "wires": [ - "IOI_LOGIC_OUTS17_1", - "IOI_WW2END3_1", - "IOI_SE4BEG2_0", - "IOI_NW4A2_0", - "IOI_NW4END1_0", - "IOI_IMUX21_1", - "IOI_WR1END3_0", - "IOI_NE2A2_0", - "IOI_IMUX20_0", - "IOI_EE2BEG2_0", - "IOI_BYP3_1", - "IOI_OLOGIC1_D8", - "LIOI_ILOGIC0_TFB", - "LIOI_OLOGIC0_OFB", - "IOI_CLK1_1", - "IOI_ODELAY0_C", - "IOI_IMUX3_1", - "IOI_WR1END3_1", - "IOI_NW4END1_1", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_WW4END0_1", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_EE2A3_1", - "IOI_OLOGIC1_D6", - "IOI_IMUX9_1", - "IOI_IMUX35_0", - "IOI_BLOCK_OUTS3_1", - "IOI_OLOGIC0_D2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_OLOGIC0_CLKDIV", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_RCLK_DIV_CE2", - "IOI_SW2A2_1", - "IOI_WW4END1_1", - "IOI_ODELAY0_CE", - "IOI_NE2A1_0", - "IOI_IMUX0_0", - "IOI_ER1BEG0_0", - "LIOI_ILOGIC1_TFB", - "IOI_IMUX10_1", - "IOI_ILOGIC0_BITSLIP", - "IOI_NE4C3_0", - "IOI_IMUX10_0", - "IOI_EE4B3_0", - "IOI_IMUX45_1", - "IOI_LH4_0", - "IOI_NW4END2_0", - "IOI_OLOGIC0_SR", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_LH1_0", - "IOI_EE4A1_1", - "LIOI_IBUF_DISABLE1", - "IOI_LOGIC_OUTS2_1", - "IOI_BLOCK_OUTS1_0", - "IOI_WW4B1_0", - "LIOI_KEEPER_INT_EN_1", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_LH2_0", - "IOI_IDELAYCTRL_OUTN1", - "IOI_FAN4_1", - "IOI_IMUX12_1", - "IOI_OLOGIC1_TBYTEIN", - "IOI_IMUX1_1", - "IOI_IMUX8_0", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_CTRL0_0", - "IOI_IDELAY1_INC", - "IOI_IMUX24_1", - "IOI_SW2A2_0", - "IOI_NW4A2_1", - "IOI_LOGIC_OUTS12_1", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_INC", - "IOI_OLOGIC0_T4", - "IOI_ER1BEG1_0", - "LIOI_ISIN21", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_IMUX14_1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_ILOGIC1_Q1", - "IOI_EL1BEG2_0", - "IOI_ILOGIC1_SR", - "LIOI_ODELAY1_OFDLY2", - "IOI_NE4BEG2_0", - "IOI_EL1BEG3_1", - "IOI_SW2A0_0", - "IOI_IMUX36_1", - "IOI_IMUX24_0", - "IOI_NW4END3_1", - "IOI_OLOGIC1_D2", - "IOI_EE4C1_1", - "IOI_LOGIC_OUTS21_0", - "IOI_IMUX4_1", - "IOI_WW4C3_0", - "IOI_OLOGIC0_D7", - "IOI_EE2A1_1", - "IOI_IMUX37_0", - "IOI_IDELAY1_CE", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_WW2A2_0", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_BYP4_1", - "IOI_IMUX42_1", - "IOI_OLOGIC1_TBYTEOUT", - "LIOI3_IDELAY0_IFDLY1", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_IMUX30_0", - "IOI_IMUX35_1", - "IOI_LOGIC_OUTS19_1", - "IOI_LH8_1", - "IOI_IMUX33_0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_EE4BEG3_1", - "IOI_NE2A2_1", - "LIOI_ISIN10", - "IOI_ILOGIC0_Q2", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_BYP7_0", - "IOI_TBYTEIN", - "IOI_IMUX42_0", - "IOI_SW4A2_0", - "IOI_WR1END0_1", - "IOI_WW2A2_1", - "IOI_MONITOR_P", - "IOI_NE4C1_0", - "IOI_IMUX29_0", - "IOI_OCLKM_1", - "IOI_WW4B2_1", - "IOI_OLOGIC0_REV", - "IOI_WW4END3_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LH7_1", - "IOI_NW2A3_1", - "IOI_LH12_1", - "IOI_EE4BEG2_0", - "IOI_LH7_0", - "IOI_ER1BEG3_0", - "IOI_IMUX0_1", - "IOI_LOGIC_OUTS7_1", - "IOI_ILOGIC0_Q3", - "IOI_IDELAY0_LDPIPEEN", - "IOI_WW2END2_0", - "IOI_LH11_1", - "IOI_IDELAY1_CINVCTRL", - "IOI_NW4A3_1", - "IOI_IMUX23_0", - "IOI_IMUX37_1", - "IOI_LOGIC_OUTS3_0", - "LIOI_OLOGIC1_CLKDIVF", - "IOI_WW4A0_0", - "IOI_IOCLK0", - "IOI_WW2END3_0", - "LIOI_IDELAY1_IDATAIN", - "LIOI_OLOGIC1_TFB_LOCAL", - "IOI_NE4BEG3_0", - "IOI_SE2A2_1", - "IOI_LEAF_GCLK0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IMUX18_1", - "IOI_IDELAY0_CE", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_NW4END3_0", - "LIOI_ODELAY1_ODATAIN", - "IOI_WW4C0_1", - "IOI_SE4C3_0", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IMUX39_1", - "IOI_NW4A1_0", - "IOI_NE4BEG2_1", - "IOI_SE4BEG0_0", - "IOI_IMUX14_0", - "IOI_IMUX22_1", - "LIOI_O0", - "IOI_CLK1_0", - "IOI_SE4BEG3_0", - "LIOI_I2GCLK_TOP0", - "IOI_OLOGIC0_D6", - "IOI_WW2A1_1", - "IOI_EE2A3_0", - "IOI_IMUX28_0", - "IOI_OCLK_0", - "IOI_IMUX18_0", - "IOI_NW2A1_1", - "IOI_IDELAY1_C", - "IOI_WW4A2_0", - "IOI_NE4C0_0", - "IOI_NW2A1_0", - "IOI_IMUX2_1", - "IOI_LOGIC_OUTS9_0", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_IMUX16_0", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_BLOCK_OUTS2_1", - "IOI_WL1END3_0", - "IOI_LOGIC_OUTS7_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_IDELAYCTRL_RDY", - "IOI_RCLK_DIV_CLR2", - "IOI_IMUX11_0", - "IOI_LOGIC_OUTS16_1", - "IOI_RCLK_DIV_CE3", - "IOI_WR1END2_0", - "IOI_LOGIC_OUTS18_1", - "IOI_SW4A0_0", - "LIOI_OLOGIC0_TFB", - "IOI_NE4BEG1_1", - "IOI_WR1END1_0", - "IOI_OLOGIC1_CLK", - "IOI_EE4B0_0", - "IOI_WW4A3_1", - "IOI_RCLK_DIV_CLR1", - "IOI_LOGIC_OUTS15_0", - "IOI_WW4B0_0", - "IOI_OLOGIC1_D3", - "IOI_ODELAY1_LD", - "LIOI3_IDELAY1_IFDLY2", - "IOI_NW4END2_1", - "IOI_LOGIC_OUTS10_1", - "LIOI_PU_INT_EN_1", - "IOI_NE2A3_1", - "IOI_NW2A0_0", - "IOI_WW4END3_0", - "IOI_IOCLK3", - "LIOI_I0", - "IOI_SE2A3_0", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_WW2A3_0", - "IOI_ILOGIC0_CE1", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_BYP1_1", - "IOI_SE4C1_1", - "IOI_SW4A3_1", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IMUX38_1", - "IOI_ER1BEG2_0", - "IOI_WW4C0_0", - "IOI_IMUX25_0", - "IOI_NE4BEG0_0", - "IOI_IMUX7_1", - "IOI_FAN3_1", - "IOI_OLOGIC1_SR", - "IOI_SW4END1_0", - "IOI_ILOGIC1_CE2", - "IOI_WW4END0_0", - "IOI_FAN7_0", - "IOI_LOGIC_OUTS1_0", - "LIOI_ILOGIC0_DDLY", - "IOI_EE2BEG0_0", - "IOI_SE4C0_1", - "IOI_OLOGIC1_T3", - "LIOI_ILOGIC0_D", - "IOI_IMUX43_1", - "IOI_EE2BEG3_1", - "IOI_NE4C3_1", - "IOI_IMUX34_1", - "IOI_IMUX46_0", - "IOI_IMUX27_0", - "IOI_DCI_TSTCLK", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_D8", - "IOI_ODELAY1_CNTVALUEOUT2", - "LIOI3_IDELAY1_IFDLY1", - "IOI_EE4C2_0", - "IOI_IMUX11_1", - "IOI_CTRL1_0", - "IOI_DCI_TSTHLP", - "LIOI_OLOGIC0_TQ", - "IOI_EE4A3_0", - "LIOI_ODELAY0_OFDLY2", - "IOI_OLOGIC0_CLKB", - "IOI_WW4C3_1", - "IOI_IMUX40_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_IMUX47_0", - "IOI_OLOGIC1_CLKDIV", - "IOI_LOGIC_OUTS5_1", - "LIOI_I2GCLK_TOP1", - "IOI_BYP7_1", - "IOI_LOGIC_OUTS12_0", - "IOI_SE4BEG0_1", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_LOGIC_OUTS5_0", - "IOI_FAN4_0", - "IOI_WW4B0_1", - "IOI_WL1END0_1", - "IOI_IMUX2_0", - "IOI_WW2END0_0", - "IOI_LH2_1", - "IOI_WW4A1_1", - "IOI_WW4C1_1", - "IOI_ER1BEG2_1", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_OLOGIC0_T1", - "LIOI_I2GCLK_BOT1", - "IOI_IMUX3_0", - "IOI_EE2BEG1_0", - "IOI_IMUX29_1", - "IOI_WW2END0_1", - "IOI_OCLK_1", - "IOI_WW2A0_0", - "IOI_ER1BEG1_1", - "IOI_RCLK_FORIO2", - "IOI_PHASER_TO_IO_ICLK", - "IOI_NE4C2_0", - "IOI_BYP2_1", - "IOI_WR1END1_1", - "IOI_FAN3_0", - "IOI_ILOGIC1_BITSLIP", - "LIOI3_IDELAY0_IFDLY0", - "IOI_ODELAY0_LDPIPEEN", - "IOI_IMUX44_1", - "IOI_NE2A1_1", - "IOI_LOGIC_OUTS1_1", - "IOI_EE4B0_1", - "IOI_OLOGIC1_CLKB", - "LIOI_OLOGIC1_OQ", - "IOI_RCLK_DIV_CLR0", - "IOI_ILOGIC1_CLKDIV", - "IOI_DCI_TSTHLN", - "IOI_OLOGIC1_D5", - "IOI_SW2A3_0", - "IOI_IDELAY1_REGRST", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_LOGIC_OUTS19_0", - "IOI_IMUX32_1", - "LIOI_ISIN11", - "IOI_SE2A1_1", - "IOI_LOGIC_OUTS21_1", - "IOI_EE2A2_0", - "IOI_ODELAY1_REGRST", - "IOI_LH9_0", - "IOI_FAN5_1", - "IOI_LH6_0", - "IOI_ODELAY1_C", - "IOI_IMUX19_0", - "IOI_OLOGIC1_D4", - "IOI_LOGIC_OUTS10_0", - "IOI_ILOGIC0_OCLK", - "LIOI_OLOGIC1_TFB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_INT_DCI_EN", - "IOI_EL1BEG0_1", - "IOI_SW2A1_0", - "IOI_OLOGIC1_D1", - "IOI_DCI_TSTRST0", - "IOI_OLOGIC0_T2", - "IOI_BLOCK_OUTS0_0", - "LIOI_DCI_T_TERM0", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_EE4BEG2_1", - "LIOI_IDELAY1_DATAOUT", - "IOI_SE4BEG3_1", - "LIOI_DIFF_TERM_INT_EN", - "LIOI_ISOUT11", - "IOI_OLOGIC1_T2", - "IOI_WW4A0_1", - "IOI_IMUX26_0", - "IOI_IMUX45_0", - "IOI_MONITOR_N", - "IOI_IMUX8_1", - "IOI_RCLK_DIV_CLR3", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY1_CE", - "LIOI_DCI_T_TERM1", - "IOI_LH6_1", - "IOI_IOCLK1", - "IOI_FAN7_1", - "LIOI_ODELAY0_OFDLY1", - "IOI_RCLK_DIV_CLR0_1", - "IOI_LOGIC_OUTS2_0", - "IOI_WW4A1_0", - "IOI_IMUX7_0", - "LIOI_ODELAY1_OFDLY1", - "IOI_ODELAY1_INC", - "IOI_ILOGIC0_CLK", - "IOI_IMUX20_1", - "IOI_WW2END1_1", - "IOI_LOGIC_OUTS11_0", - "IOI_SE4C0_0", - "IOI_LOGIC_OUTS17_0", - "IOI_ER1BEG3_1", - "IOI_ILOGIC0_CLKDIV", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_REV", - "LIOI_OLOGIC0_CLKDIVF", - "IOI_FAN1_1", - "IOI_LH10_0", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC0_CE2", - "IOI_FAN6_1", - "LIOI_ODELAY0_OFDLY0", - "IOI_IDELAY1_CNTVALUEOUT0", - "LIOI_KEEPER_INT_EN_0", - "LIOI_OSOUT21", - "IOI_IMUX5_0", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_SW4END0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_ILOGIC1_Q5", - "IOI_NE4BEG0_1", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_WW4B3_0", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_EE4BEG0_1", - "IOI_EE2BEG2_1", - "IOI_OLOGIC1_T1", - "IOI_IMUX6_1", - "IOI_EL1BEG2_1", - "IOI_SE4C1_0", - "IOI_NW4END0_1", - "IOI_IMUX1_0", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_REV", - "IOI_SE4C2_1", - "IOI_SE4BEG2_1", - "IOI_EE4A0_1", - "IOI_IMUX36_0", - "IOI_EE2BEG0_1", - "IOI_NW4A0_1", - "IOI_WW4END2_1", - "IOI_IMUX46_1", - "IOI_EE4A3_1", - "IOI_LOGIC_OUTS20_0", - "IOI_WL1END1_1", - "LIOI_OSIN21", - "IOI_SW4END1_1", - "LIOI3_IDELAY1_IFDLY0", - "IOI_IMUX13_1", - "IOI_ODELAY0_LD", - "IOI_ILOGIC1_Q8", - "IOI_IMUX23_1", - "IOI_IMUX_RC3", - "IOI_IMUX31_1", - "IOI_WW4A3_0", - "IOI_OLOGIC0_OCE", - "IOI_LOGIC_OUTS3_1", - "IOI_EE2A2_1", - "IOI_LOGIC_OUTS8_0", - "IOI_ILOGIC0_CLKB", - "IOI_IMUX27_1", - "IOI_NE2A0_1", - "IOI_RCLK_DIV_CE1", - "LIOI_O1", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_NE2A0_0", - "IOI_IDELAY0_REGRST", - "LIOI_OSOUT11", - "LIOI_OLOGIC0_OQ", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_SE4BEG1_1", - "IOI_IMUX_RC2", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_ILOGIC0_O", - "IOI_EE4A1_0", - "IOI_IDELAYCTRL_RST", - "IOI_SW4A1_0", - "IOI_EE4A2_1", - "IOI_LOGIC_OUTS9_1", - "IOI_WW4A2_1", - "IOI_FAN2_1", - "LIOI_OSOUT20", - "IOI_FAN5_0", - "IOI_IMUX16_1", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_IOCLK2", - "IOI_OLOGIC1_D7", - "IOI_IMUX6_0", - "IOI_LOGIC_OUTS4_0", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC1_Q4", - "IOI_NW4END0_0", - "IOI_FAN0_1", - "IOI_BLOCK_OUTS3_0", - "IOI_IMUX38_0", - "IOI_IDELAY0_CINVCTRL", - "LIOI_OLOGIC0_TFB_LOCAL", - "LIOI_IBUF_DISABLE0", - "IOI_OLOGIC1_OCE", - "LIOI_IDELAY0_IDATAIN", - "IOI_EE4A2_0", - "IOI_BLOCK_OUTS0_1", - "IOI_IMUX4_0", - "IOI_OLOGIC1_CLKDIVB", - "LIOI_PD_INT_EN_1", - "IOI_SW4END2_0", - "IOI_BYP0_1", - "IOI_IMUX_RC0", - "IOI_IMUX31_0", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IMUX15_0", - "IOI_EE4C3_0", - "IOI_LOGIC_OUTS11_1", - "IOI_NE4BEG1_0", - "IOI_SW4END2_1", - "IOI_PHASER_TO_IO_ICLKDIV", - "LIOI_OLOGIC1_OFB", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS4_1", - "IOI_WR1END0_0", - "LIOI_OSOUT10", - "LIOI_ILOGIC1_D", - "IOI_IDELAY0_C", - "IOI_SE2A2_0", - "IOI_LOGIC_OUTS13_0", - "IOI_ILOGIC1_OCLK", - "IOI_BYP4_0", - "IOI_WW2A1_0", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_IDELAY0_DATAIN", - "IOI_EE4B2_1", - "IOI_IMUX28_1", - "IOI_LEAF_GCLK5", - "IOI_SW4A3_0", - "IOI_BLOCK_OUTS1_1", - "IOI_WW4C1_0", - "IOI_IMUX9_0", - "IOI_BYP5_0", - "IOI_LOGIC_OUTS18_0", - "IOI_NW4A0_0", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_LH10_1", - "IOI_IMUX12_0", - "IOI_LOGIC_OUTS23_0", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_DCI_DCIDONE", - "IOI_SE2A0_0", - "IOI_IMUX21_0", - "IOI_EE4B1_1", - "IOI_RCLK_DIV_CE3_1", - "IOI_EE4BEG0_0", - "LIOI_ODELAY0_DATAOUT", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ILOGIC1_CLK", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_LOGIC_OUTS14_1", - "IOI_BYP3_0", - "IOI_EE2A0_1", - "IOI_LEAF_GCLK4", - "IOI_SW4A2_1", - "IOI_OLOGIC1_T4", - "IOI_LOGIC_OUTS0_0", - "IOI_WW2END1_0", - "IOI_BYP5_1", - "IOI_ER1BEG0_1", - "IOI_LOGIC_OUTS16_0", - "IOI_IMUX5_1", - "IOI_NW4A3_0", - "IOI_EE4BEG1_1", - "IOI_SW2A1_1", - "IOI_IDELAY0_LD", - "IOI_EE2A0_0", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_CLK0_1", - "IOI_RCLK_FORIO3", - "IOI_IMUX44_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_ILOGIC1_O", - "IOI_SE2A3_1", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ILOGIC1_REV", - "IOI_EE2A1_0", - "IOI_IMUX17_1", - "IOI_FAN1_0", - "IOI_EE4A0_0", - "IOI_LOGIC_OUTS22_0", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_RCLK_DIV_CE0", - "IOI_WW4C2_0", - "IOI_NW2A3_0", - "IOI_IMUX34_0", - "LIOI_ILOGIC0_OFB", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_NE4C2_1", - "IOI_IMUX22_0", - "IOI_OLOGIC0_T3", - "IOI_ODELAY1_CINVCTRL", - "IOI_IMUX17_0", - "LIOI_ISIN20", - "IOI_WW4B2_0", - "IOI_FAN6_0", - "IOI_IDELAY1_LDPIPEEN", - "LIOI_PU_INT_EN_0", - "IOI_WL1END0_0", - "IOI_OCLKM_0", - "IOI_IMUX15_1", - "IOI_CLK0_0", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IMUX25_1", - "IOI_EL1BEG0_0", - "IOI_OLOGIC0_CLK", - "IOI_IMUX39_0", - "IOI_WL1END1_0", - "IOI_WL1END2_0", - "IOI_IMUX41_0", - "IOI_CTRL0_1", - "IOI_EE4C0_0", - "IOI_ILOGIC1_Q6", - "IOI_NW2A0_1", - "IOI_EE2BEG1_1", - "IOI_ILOGIC1_Q2", - "IOI_CTRL1_1", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_OLOGIC0_D4", - "IOI_SE4BEG1_0", - "LIOI_ISOUT20", - "IOI_LOGIC_OUTS15_1", - "IOI_EE2BEG3_0", - "IOI_SW4A1_1", - "IOI_EL1BEG1_0", - "IOI_DCI_TSTRST", - "LIOI_ISOUT21", - "IOI_SW2A3_1", - "IOI_NE4C0_1", - "IOI_ILOGIC1_CLKDIVP", - "IOI_IMUX30_1", - "LIOI_ODELAY0_ODATAIN", - "IOI_ILOGIC0_Q5", - "IOI_IDELAYCTRL_OUTN65", - "IOI_WR1END2_1", - "IOI_WW4B1_1", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_EE4BEG3_0", - "IOI_SE2A0_1", - "IOI_FAN0_0", - "IOI_EE4BEG1_0", - "LIOI_OSIN10", - "IOI_IMUX47_1", - "IOI_LH1_1", - "LIOI_ISOUT10", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC0_OCLKB", - "LIOI_IBUF1", - "IOI_RCLK_DIV_CE2_1", - "IOI_BYP2_0", - "IOI_EE4C1_0", - "LIOI_IBUF0", - "IOI_WW2END2_1", - "IOI_IMUX43_0", - "IOI_BYP6_1", - "IOI_RCLK_FORIO1", - "IOI_ILOGIC1_OCLKB", - "IOI_LEAF_GCLK1", - "IOI_NW2A2_0", - "IOI_IMUX33_1", - "IOI_LH11_0", - "IOI_ILOGIC0_Q6", - "IOI_SW4END3_1", - "IOI_ODELAY1_CLKIN", - "IOI_NW2A2_1", - "IOI_LH9_1", - "LIOI_OLOGIC1_TQ", - "IOI_PHASER_TO_IO_OCLK", - "IOI_EE4B3_1", - "LIOI_OSIN20", - "IOI_WW4B3_1", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_Q3", - "IOI_FAN2_0", - "IOI_WW4C2_1", - "LIOI_I1", - "LIOI_ODELAY1_DATAOUT", - "LIOI_T1", - "IOI_WL1END2_1", - "IOI_RCLK_FORIO0", - "IOI_SW4A0_1", - "IOI_NW4A1_1", - "IOI_IMUX41_1", - "IOI_LOGIC_OUTS13_1", - "LIOI_PD_INT_EN_0", - "IOI_BLOCK_OUTS2_0", - "IOI_WW4END1_0", - "IOI_IMUX40_1", - "IOI_IMUX19_1", - "IOI_EE4B1_0", - "IOI_WL1END3_1", - "IOI_LEAF_GCLK2", - "IOI_ODELAY0_CLKIN", - "IOI_EE4B2_0", - "IOI_SE2A1_0", - "IOI_BYP6_0", - "IOI_IMUX32_0", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_DATAIN", - "IOI_EE4C2_1", - "IOI_LH5_1", - "IOI_ILOGIC0_Q7", - "LIOI_OSIN11", - "IOI_IMUX_RC1", - "IOI_EL1BEG3_0", - "IOI_WW2A3_1", - "IOI_NE4C1_1", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_SW4END3_0", - "LIOI3_IDELAY0_IFDLY2", - "IOI_WW2A0_1", - "LIOI_ILOGIC1_DDLY", - "IOI_NE4BEG3_1", - "IOI_SE4C2_0", - "LIOI_ODELAY1_OFDLY0", - "IOI_ODELAY0_INC", - "IOI_LOGIC_OUTS6_1", - "IOI_BYP1_0", - "IOI_NE2A3_0", - "IOI_ILOGIC1_Q7", - "LIOI_ILOGIC1_OFB", - "IOI_ODELAY0_REGRST", - "IOI_ILOGIC0_CLKDIVP", - "IOI_EE4C3_1", - "IOI_SE4C3_1", - "IOI_ILOGIC1_CLKB", - "IOI_LOGIC_OUTS23_1", - "IOI_OLOGIC0_D1", - "IOI_EE4C0_1", - "IOI_LOGIC_OUTS22_1", - "IOI_OLOGIC1_TCE", - "IOI_LH8_0", - "IOI_SW2A0_1", - "IOI_SW4END0_1", - "LIOI_IDELAY0_DATAOUT", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_LOGIC_OUTS14_0", - "IOI_ODELAY1_LDPIPEEN", - "IOI_LH12_0", - "IOI_IMUX13_0", - "IOI_LEAF_GCLK3", - "IOI_BYP0_0", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ILOGIC0_Q4", - "LIOI_T0", - "IOI_EL1BEG1_1", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_WW4END2_0", - "IOI_IMUX26_1", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_TBYTEIN", - "IOI_LOGIC_OUTS20_1" - ], - "sites": [ - { - "prefix": "OLOGIC", - "y_coord": 0, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC1_D1", - "D3": "IOI_OLOGIC1_D3", - "SR": "IOI_OLOGIC1_SR", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "TFB": "LIOI_OLOGIC1_TFB", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLK": "IOI_OLOGIC1_CLK", - "T4": "IOI_OLOGIC1_T4", - "OQ": "LIOI_OLOGIC1_OQ", - "D8": "IOI_OLOGIC1_D8", - "T1": "IOI_OLOGIC1_T1", - "D5": "IOI_OLOGIC1_D5", - "SHIFTOUT1": "LIOI_OSOUT11", - "T2": "IOI_OLOGIC1_T2", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "D4": "IOI_OLOGIC1_D4", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D2": "IOI_OLOGIC1_D2", - "TQ": "LIOI_OLOGIC1_TQ", - "T3": "IOI_OLOGIC1_T3", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "OCE": "IOI_OLOGIC1_OCE", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "SHIFTIN1": null, - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "TCE": "IOI_OLOGIC1_TCE", - "OFB": "LIOI_OLOGIC1_OFB", - "SHIFTIN2": null, - "SHIFTOUT2": "LIOI_OSOUT21", - "REV": null, - "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "ILOGIC", - "y_coord": 0, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q1": "IOI_ILOGIC1_Q1", - "SR": "IOI_ILOGIC1_SR", - "D": "LIOI_ILOGIC1_D", - "DDLY": "LIOI_ILOGIC1_DDLY", - "SHIFTIN2": "LIOI_ISIN21", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "Q3": "IOI_ILOGIC1_Q3", - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "Q8": "IOI_ILOGIC1_Q8", - "TFB": "LIOI_ILOGIC1_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC1_CE1", - "Q2": "IOI_ILOGIC1_Q2", - "Q6": "IOI_ILOGIC1_Q6", - "CLKB": "IOI_ILOGIC1_CLKB", - "Q7": "IOI_ILOGIC1_Q7", - "O": "IOI_ILOGIC1_O", - "CLK": "IOI_ILOGIC1_CLK", - "CE2": "IOI_ILOGIC1_CE2", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "SHIFTIN1": "LIOI_ISIN11", - "OCLK": "IOI_ILOGIC1_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "OFB": "LIOI_ILOGIC1_OFB", - "SHIFTOUT1": "LIOI_ISOUT11", - "SHIFTOUT2": "LIOI_ISOUT21", - "REV": null, - "CLKDIV": "IOI_ILOGIC1_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "OLOGIC", - "y_coord": 1, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC0_D1", - "D3": "IOI_OLOGIC0_D3", - "SR": "IOI_OLOGIC0_SR", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "TFB": "LIOI_OLOGIC0_TFB", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLK": "IOI_OLOGIC0_CLK", - "T4": "IOI_OLOGIC0_T4", - "OQ": "LIOI_OLOGIC0_OQ", - "D8": "IOI_OLOGIC0_D8", - "T1": "IOI_OLOGIC0_T1", - "D5": "IOI_OLOGIC0_D5", - "SHIFTOUT1": "LIOI_OSOUT10", - "T2": "IOI_OLOGIC0_T2", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "D4": "IOI_OLOGIC0_D4", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D2": "IOI_OLOGIC0_D2", - "TQ": "LIOI_OLOGIC0_TQ", - "T3": "IOI_OLOGIC0_T3", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "OCE": "IOI_OLOGIC0_OCE", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "SHIFTIN1": "LIOI_OSIN10", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "TCE": "IOI_OLOGIC0_TCE", - "OFB": "LIOI_OLOGIC0_OFB", - "SHIFTIN2": "LIOI_OSIN20", - "SHIFTOUT2": "LIOI_OSOUT20", - "REV": null, - "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "ILOGIC", - "y_coord": 1, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q1": "IOI_ILOGIC0_Q1", - "SR": "IOI_ILOGIC0_SR", - "D": "LIOI_ILOGIC0_D", - "DDLY": "LIOI_ILOGIC0_DDLY", - "SHIFTIN2": null, - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "Q3": "IOI_ILOGIC0_Q3", - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "Q8": "IOI_ILOGIC0_Q8", - "TFB": "LIOI_ILOGIC0_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC0_CE1", - "Q2": "IOI_ILOGIC0_Q2", - "Q6": "IOI_ILOGIC0_Q6", - "CLKB": "IOI_ILOGIC0_CLKB", - "Q7": "IOI_ILOGIC0_Q7", - "O": "IOI_ILOGIC0_O", - "CLK": "IOI_ILOGIC0_CLK", - "CE2": "IOI_ILOGIC0_CE2", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "SHIFTIN1": null, - "OCLK": "IOI_ILOGIC0_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "OFB": "LIOI_ILOGIC0_OFB", - "SHIFTOUT1": "LIOI_ISOUT10", - "SHIFTOUT2": "LIOI_ISOUT20", - "REV": null, - "CLKDIV": "IOI_ILOGIC0_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "IDELAY", - "y_coord": 0, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CE": "IOI_IDELAY1_CE", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "IFDLY2": "LIOI3_IDELAY1_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "LD": "IOI_IDELAY1_LD", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "IFDLY0": "LIOI3_IDELAY1_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "INC": "IOI_IDELAY1_INC", - "DATAOUT": "LIOI_IDELAY1_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY1_DATAIN", - "C": "IOI_IDELAY1_C", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "IDATAIN": "LIOI_IDELAY1_IDATAIN", - "REGRST": "IOI_IDELAY1_REGRST", - "IFDLY1": "LIOI3_IDELAY1_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IDELAY", - "y_coord": 1, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CE": "IOI_IDELAY0_CE", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "IFDLY2": "LIOI3_IDELAY0_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "LD": "IOI_IDELAY0_LD", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "IFDLY0": "LIOI3_IDELAY0_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "INC": "IOI_IDELAY0_INC", - "DATAOUT": "LIOI_IDELAY0_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY0_DATAIN", - "C": "IOI_IDELAY0_C", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "IDATAIN": "LIOI_IDELAY0_IDATAIN", - "REGRST": "IOI_IDELAY0_REGRST", - "IFDLY1": "LIOI3_IDELAY0_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "LIOI3_TBYTESRC.LIOI_IBUF1->LIOI_I1": { + "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", - "dst_wire": "LIOI_I1", - "is_directional": "1", - "src_wire": "LIOI_IBUF1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX46_1->IOI_OLOGIC0_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC0", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX40_1->IOI_OLOGIC0_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OSOUT11->LIOI_OSIN10": { - "can_invert": "0", - "dst_wire": "LIOI_OSIN10", - "is_directional": "1", - "src_wire": "LIOI_OSOUT11", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX45_1->IOI_OLOGIC0_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_DDLY", - "is_directional": "1", - "src_wire": "LIOI_IDELAY1_DATAOUT", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR1_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TQ", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC2", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TFB", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_OQ", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.LIOI_I1->LIOI_IDELAY1_IDATAIN": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY1_IDATAIN", - "is_directional": "1", - "src_wire": "LIOI_I1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC0_OQ->>LIOI_O0": { - "can_invert": "0", - "dst_wire": "LIOI_O0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OQ", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_I0->LIOI_ILOGIC0_D": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_D", - "is_directional": "1", - "src_wire": "LIOI_I0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEOUT->>IOI_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_TBYTEOUT", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX43_1->IOI_OLOGIC0_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC1_D", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.LIOI_ISOUT10->LIOI_ISIN11": { - "can_invert": "0", - "dst_wire": "LIOI_ISIN11", - "is_directional": "1", - "src_wire": "LIOI_ISOUT10", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { - "can_invert": "0", - "dst_wire": "LIOI_IBUF_DISABLE0", - "is_directional": "1", - "src_wire": "IOI_IMUX9_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_1", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_I0->LIOI_IDELAY0_IDATAIN": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY0_IDATAIN", - "is_directional": "1", - "src_wire": "LIOI_I0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX21_0->IOI_OLOGIC1_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX44_0->IOI_OLOGIC1_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC1_OQ->>LIOI_O1": { - "can_invert": "0", - "dst_wire": "LIOI_O1", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_OQ", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TQ", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "LIOI_I2GCLK_TOP0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY1_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX42_1->IOI_OLOGIC0_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_1", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY0_DATAOUT", - "is_directional": "1", - "src_wire": "LIOI_IDELAY0_IDATAIN", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { - "can_invert": "0", - "dst_wire": "LIOI_IBUF_DISABLE1", - "is_directional": "1", - "src_wire": "IOI_IMUX9_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY1_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_O", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX46_0->IOI_OLOGIC1_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_I1->LIOI_ILOGIC1_D": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_D", - "is_directional": "1", - "src_wire": "LIOI_I1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX45_0->IOI_OLOGIC1_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY1_DATAOUT", - "is_directional": "1", - "src_wire": "LIOI_IDELAY1_IDATAIN", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX43_0->IOI_OLOGIC1_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q7", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE0", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q6", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR0_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_OFB", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE2_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC0_DDLY", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR3", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OQ", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_ISOUT20->LIOI_ISIN21": { - "can_invert": "0", - "dst_wire": "LIOI_ISIN21", - "is_directional": "1", - "src_wire": "LIOI_ISOUT20", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OSOUT21->LIOI_OSIN20": { - "can_invert": "0", - "dst_wire": "LIOI_OSIN20", - "is_directional": "1", - "src_wire": "LIOI_OSOUT21", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX42_0->IOI_OLOGIC1_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { - "can_invert": "0", - "dst_wire": "LIOI_DCI_T_TERM0", - "is_directional": "1", - "src_wire": "IOI_IMUX6_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX32_0->IOI_IDELAY1_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX47_0->IOI_OLOGIC1_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_DDLY", - "is_directional": "1", - "src_wire": "LIOI_IDELAY0_DATAOUT", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY1_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC1_DDLY", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q6", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q8", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q8", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC0_TQ->>LIOI_T0": { - "can_invert": "0", - "dst_wire": "LIOI_T0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TQ", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE3_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_IBUF0->LIOI_I0": { - "can_invert": "0", - "dst_wire": "LIOI_I0", - "is_directional": "1", - "src_wire": "LIOI_IBUF0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q7", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC1_TQ->>LIOI_T1": { - "can_invert": "0", - "dst_wire": "LIOI_T1", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TQ", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" }, - "LIOI3_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "LIOI3_TBYTESRC.LIOI_IBUF1->LIOI_I1": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_BITSLIP", + "src_wire": "LIOI_IBUF1", "is_directional": "1", - "src_wire": "IOI_IMUX0_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "LIOI_I1" }, - "LIOI3_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "LIOI3_TBYTESRC.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_BITSLIP", + "src_wire": "IOI_IMUX46_1", "is_directional": "1", - "src_wire": "IOI_IMUX0_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR2", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX44_1->IOI_OLOGIC0_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" }, - "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_0": { + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", - "dst_wire": "IOI_OCLK_0", + "src_wire": "IOI_LEAF_GCLK4", "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "LIOI3_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", + "src_wire": "IOI_IMUX38_0", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3" }, - "LIOI3_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", + "src_wire": "IOI_RCLK_FORIO1", "is_directional": "1", - "src_wire": "IOI_IMUX36_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" }, - "LIOI3_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE2", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", "is_directional": "1", - "src_wire": "IOI_IMUX14_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" }, - "LIOI3_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "LIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEOUT->>IOI_TBYTEIN": { "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", + "src_wire": "IOI_OLOGIC1_TBYTEOUT", "is_directional": "1", - "src_wire": "IOI_IMUX35_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX47_1->IOI_OLOGIC0_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OFB", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_TBYTEIN" }, "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" }, - "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "LIOI3_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", + "src_wire": "IOI_BYP6_0", "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL" }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { - "can_invert": "0", - "dst_wire": "LIOI_DCI_T_TERM1", - "is_directional": "1", - "src_wire": "IOI_IMUX6_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC3", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV" }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "LIOI3_TBYTESRC.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", + "src_wire": "IOI_IMUX44_1", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_OFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_OFB" + }, + "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR" }, "LIOI3_TBYTESRC.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", "src_wire": "LIOI_ILOGIC0_D", - "is_pseudo": "1" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_OFB", "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.LIOI_I1->LIOI_ILOGIC1_D": { + "can_invert": "0", + "src_wire": "LIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_D" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2" + }, + "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1" + }, + "LIOI3_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB" + }, + "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TQ->>LIOI_T0": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_T0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_OQ->>LIOI_O0": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_O0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB" + }, + "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.LIOI_IBUF0->LIOI_I0": { + "can_invert": "0", + "src_wire": "LIOI_IBUF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_I0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.LIOI_OSOUT21->LIOI_OSIN20": { + "can_invert": "0", + "src_wire": "LIOI_OSOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN20" + }, + "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.LIOI_ISOUT10->LIOI_ISIN11": { + "can_invert": "0", + "src_wire": "LIOI_ISOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN11" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN" + }, + "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE" + }, + "LIOI3_TBYTESRC.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "LIOI3_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OQ" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1" + }, + "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "LIOI3_TBYTESRC.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1" + }, + "LIOI3_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY1_DATAOUT" + }, + "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN" + }, + "LIOI3_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE" }, "LIOI3_TBYTESRC.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D2", - "is_directional": "1", "src_wire": "IOI_IMUX40_0", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_TFB" + }, + "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_I2GCLK_TOP0" + }, + "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "LIOI_ILOGIC1_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "LIOI_ILOGIC0_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0" + }, + "LIOI3_TBYTESRC.LIOI_I0->LIOI_IDELAY0_IDATAIN": { + "can_invert": "0", + "src_wire": "LIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY0_IDATAIN" + }, + "LIOI3_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.LIOI_I1->LIOI_IDELAY1_IDATAIN": { + "can_invert": "0", + "src_wire": "LIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY1_IDATAIN" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TQ" + }, + "LIOI3_TBYTESRC.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB" + }, + "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD" + }, + "LIOI3_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC" + }, + "LIOI3_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1" + }, + "LIOI3_TBYTESRC.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_DDLY" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY2" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_OFB" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1" + }, + "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1" + }, + "LIOI3_TBYTESRC.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5" + }, + "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0" + }, + "LIOI3_TBYTESRC.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY0_DATAOUT" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE" + }, + "LIOI3_TBYTESRC.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE1" + }, + "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1" + }, + "LIOI3_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_TFB" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OQ" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "LIOI_ILOGIC1_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL" + }, + "LIOI3_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C" + }, + "LIOI3_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TQ" + }, + "LIOI3_TBYTESRC.LIOI_OSOUT11->LIOI_OSIN10": { + "can_invert": "0", + "src_wire": "LIOI_OSOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN10" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4" + }, + "LIOI3_TBYTESRC.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM1" + }, + "LIOI3_TBYTESRC.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB" + }, + "LIOI3_TBYTESRC.LIOI_ISOUT20->LIOI_ISIN21": { + "can_invert": "0", + "src_wire": "LIOI_ISOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN21" + }, + "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2" + }, + "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_OQ->>LIOI_O1": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_O1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1" + }, + "LIOI3_TBYTESRC.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD" + }, + "LIOI3_TBYTESRC.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE0" + }, + "LIOI3_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY1" + }, + "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2" + }, + "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1" + }, + "LIOI3_TBYTESRC.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_DDLY" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP" + }, + "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0" + }, + "LIOI3_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1" + }, + "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "can_invert": "0", + "src_wire": "IOI_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC1_TQ->>LIOI_T1": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_T1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR" + }, + "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1" + }, + "LIOI3_TBYTESRC.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY1" + }, + "LIOI3_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "LIOI3_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1" + }, + "LIOI3_TBYTESRC.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY2" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTESRC.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2" + }, + "LIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTESRC.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB" + }, + "LIOI3_TBYTESRC.LIOI_I0->LIOI_ILOGIC0_D": { + "can_invert": "0", + "src_wire": "LIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_D" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" } }, - "tile_type": "LIOI3_TBYTESRC" + "wires": [ + "IOI_BYP5_1", + "IOI_IMUX26_1", + "IOI_NW4END3_1", + "IOI_ILOGIC1_REV", + "IOI_IMUX42_0", + "IOI_EE4A1_1", + "IOI_IMUX22_1", + "IOI_ILOGIC0_CE2", + "IOI_IMUX5_0", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "LIOI3_IDELAY1_IFDLY1", + "IOI_OLOGIC1_CLKB", + "IOI_WW4C1_1", + "IOI_ER1BEG0_1", + "IOI_IMUX23_0", + "IOI_RCLK_DIV_CLR0_1", + "IOI_OLOGIC1_T1", + "IOI_IOCLK3", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_RCLK_DIV_CE2_1", + "IOI_DCI_TSTRST", + "IOI_OLOGIC1_REV", + "IOI_WW4END1_0", + "IOI_CTRL0_1", + "IOI_MONITOR_N", + "IOI_ILOGIC1_Q7", + "IOI_IMUX38_0", + "LIOI_ISOUT21", + "IOI_WW4B1_1", + "IOI_EE4C1_1", + "IOI_IOCLK2", + "IOI_OLOGIC1_D8", + "IOI_LEAF_GCLK4", + "IOI_WW2END2_1", + "IOI_BYP2_0", + "IOI_ILOGIC1_Q1", + "IOI_IMUX36_1", + "IOI_LEAF_GCLK3", + "IOI_SW2A0_1", + "IOI_IMUX16_1", + "IOI_FAN2_1", + "IOI_IMUX27_0", + "IOI_IMUX22_0", + "IOI_EL1BEG2_1", + "IOI_NW4A1_0", + "IOI_BLOCK_OUTS0_1", + "IOI_SE2A1_0", + "LIOI_OSIN21", + "IOI_IMUX4_1", + "IOI_EL1BEG2_0", + "IOI_WW4B0_1", + "IOI_NE4BEG3_1", + "LIOI_ISIN11", + "IOI_SW4A3_1", + "IOI_SW4A1_0", + "IOI_ODELAY0_LDPIPEEN", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_EE4B3_1", + "IOI_NE4C0_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_IDELAYCTRL_OUTN65", + "IOI_BYP4_1", + "IOI_EE2BEG1_0", + "IOI_LOGIC_OUTS20_0", + "LIOI_T1", + "IOI_SE4C3_1", + "IOI_WL1END2_0", + "IOI_CTRL1_1", + "IOI_FAN5_0", + "IOI_EE2A2_0", + "IOI_WW4END2_1", + "IOI_WW4C0_0", + "IOI_IDELAY1_REGRST", + "IOI_PHASER_TO_IO_OCLK", + "IOI_SW4A0_1", + "IOI_IDELAY1_CNTVALUEIN0", + "LIOI_I1", + "IOI_OLOGIC0_CLKDIV", + "LIOI_I0", + "IOI_IMUX17_0", + "LIOI_ISIN20", + "IOI_WW2END2_0", + "IOI_FAN3_0", + "IOI_LOGIC_OUTS14_0", + "IOI_DCI_TSTCLK", + "IOI_FAN0_0", + "IOI_ODELAY1_CINVCTRL", + "IOI_SE4BEG0_0", + "IOI_IMUX20_1", + "IOI_EE2BEG3_0", + "IOI_LH7_0", + "IOI_IMUX15_1", + "IOI_ILOGIC0_Q3", + "IOI_EE4A1_0", + "IOI_ILOGIC1_Q8", + "LIOI_PU_INT_EN_0", + "IOI_IDELAY1_C", + "IOI_BYP7_0", + "IOI_IMUX25_0", + "IOI_IDELAY0_REGRST", + "IOI_BYP3_1", + "IOI_NE2A0_1", + "IOI_IMUX11_1", + "IOI_SE4BEG0_1", + "IOI_ILOGIC0_OCLKB", + "IOI_IMUX47_0", + "IOI_OLOGIC0_D4", + "IOI_SE2A0_0", + "IOI_SE4BEG1_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_SW4END3_0", + "IOI_EE4BEG3_0", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLKB", + "IOI_LOGIC_OUTS19_1", + "IOI_EL1BEG1_1", + "IOI_OLOGIC0_D3", + "IOI_EE4C0_0", + "IOI_OLOGIC0_TCE", + "IOI_WW2A0_0", + "LIOI3_IDELAY1_IFDLY0", + "LIOI_I2GCLK_TOP1", + "IOI_ODELAY0_CLKIN", + "IOI_DCI_TSTHLN", + "IOI_IMUX15_0", + "IOI_WW2END1_1", + "IOI_NE4C3_1", + "IOI_ILOGIC0_O", + "LIOI3_IDELAY0_IFDLY1", + "IOI_RCLK_DIV_CE3", + "IOI_BLOCK_OUTS0_0", + "IOI_SE4C3_0", + "IOI_ILOGIC1_CLKDIV", + "IOI_BYP0_1", + "IOI_IMUX32_0", + "IOI_OLOGIC1_D5", + "LIOI_ODELAY1_OFDLY1", + "IOI_LH4_0", + "IOI_RCLK_DIV_CLR1", + "LIOI_ODELAY1_OFDLY2", + "LIOI_PD_INT_EN_1", + "IOI_IMUX10_0", + "IOI_NW2A0_1", + "IOI_ILOGIC0_REV", + "LIOI_ILOGIC1_DDLY", + "IOI_ODELAY0_CNTVALUEIN4", + "LIOI_IDELAY1_IDATAIN", + "IOI_LOGIC_OUTS1_1", + "IOI_OLOGIC0_T1", + "IOI_EE4BEG1_0", + "IOI_IMUX41_0", + "IOI_WW4C3_0", + "IOI_LOGIC_OUTS23_0", + "IOI_RCLK_DIV_CE0", + "LIOI3_IDELAY0_IFDLY0", + "IOI_SW2A3_1", + "IOI_EE4B3_0", + "IOI_IOCLK0", + "IOI_EE4BEG0_0", + "IOI_ODELAY0_INC", + "IOI_IMUX6_0", + "LIOI_ODELAY1_ODATAIN", + "LIOI_ILOGIC1_D", + "IOI_IMUX10_1", + "IOI_IMUX40_0", + "IOI_WR1END3_0", + "IOI_IMUX37_1", + "IOI_OLOGIC0_REV", + "IOI_OLOGIC0_D1", + "IOI_IOCLK1", + "IOI_RCLK_FORIO1", + "IOI_ODELAY1_LD", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_WW4A1_1", + "IOI_NE4C0_0", + "LIOI_ISOUT10", + "IOI_NW4A2_1", + "LIOI_DCI_T_TERM0", + "IOI_LOGIC_OUTS6_1", + "LIOI_I2GCLK_TOP0", + "IOI_LH3_1", + "IOI_IMUX33_0", + "IOI_IMUX13_0", + "IOI_IMUX9_0", + "IOI_EE4BEG0_1", + "IOI_WW2A2_1", + "IOI_WR1END0_1", + "IOI_OLOGIC0_T3", + "IOI_EE4A2_0", + "IOI_IMUX26_0", + "IOI_IMUX0_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX3_0", + "IOI_EE4B2_0", + "IOI_SW2A2_1", + "LIOI_IBUF_DISABLE0", + "IOI_OLOGIC0_OCE", + "IOI_ILOGIC0_CE1", + "LIOI_OSIN11", + "LIOI_ILOGIC0_OFB", + "IOI_LOGIC_OUTS8_0", + "IOI_SE2A2_1", + "IOI_WW2END0_0", + "LIOI_IDELAY0_IDATAIN", + "IOI_SW2A1_0", + "IOI_RCLK_FORIO2", + "IOI_LH3_0", + "IOI_EE4B1_0", + "LIOI_ILOGIC0_D", + "IOI_SW4END1_0", + "IOI_WW4A2_0", + "IOI_ER1BEG3_0", + "IOI_LH6_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_IMUX40_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IMUX2_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_BYP1_1", + "IOI_SW4END1_1", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_IDELAYCTRL_RDY", + "IOI_ODELAY1_CNTVALUEOUT0", + "LIOI_OSOUT11", + "IOI_IMUX44_0", + "IOI_NW2A2_0", + "IOI_OLOGIC1_D4", + "IOI_SW4A1_1", + "IOI_LOGIC_OUTS22_1", + "IOI_RCLK_DIV_CE3_1", + "LIOI_ISIN21", + "IOI_OLOGIC0_D6", + "IOI_IDELAY0_CINVCTRL", + "IOI_IMUX25_1", + "IOI_WW4END1_1", + "IOI_WW4END0_1", + "LIOI_OLOGIC0_CLKDIVF", + "IOI_SE4BEG2_0", + "IOI_LOGIC_OUTS16_0", + "IOI_NW4END3_0", + "IOI_NE4BEG2_0", + "IOI_DCI_DCIDONE", + "LIOI_DCI_T_TERM1", + "IOI_OLOGIC1_TBYTEIN", + "IOI_ILOGIC0_CLKDIVP", + "IOI_IMUX13_1", + "IOI_LOGIC_OUTS7_0", + "IOI_IMUX_RC1", + "IOI_CLK0_1", + "IOI_NE2A3_1", + "IOI_DCI_TSTRST0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_LEAF_GCLK2", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_IDELAY1_INC", + "IOI_OLOGIC1_OCE", + "IOI_LOGIC_OUTS13_0", + "IOI_CLK1_1", + "IOI_NE4C2_1", + "IOI_WW4B0_0", + "IOI_ODELAY1_CNTVALUEIN0", + "IOI_WL1END3_1", + "IOI_IMUX28_0", + "IOI_NW4END1_0", + "LIOI3_IDELAY0_IFDLY2", + "IOI_OLOGIC1_D7", + "IOI_LOGIC_OUTS11_0", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_IMUX18_1", + "IOI_WW4A0_1", + "IOI_OLOGIC0_D8", + "IOI_IMUX38_1", + "IOI_IMUX21_0", + "IOI_EE2BEG1_1", + "IOI_EE4B0_0", + "IOI_FAN4_0", + "IOI_IDELAYCTRL_RST", + "IOI_SW4A2_0", + "IOI_NW2A0_0", + "IOI_OCLKM_0", + "IOI_EE2BEG0_1", + "IOI_LOGIC_OUTS14_1", + "LIOI_OLOGIC0_OFB", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_ODELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_0", + "IOI_ILOGIC1_OCLK", + "IOI_IMUX17_1", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_SW4END3_1", + "IOI_ODELAY1_CLKIN", + "IOI_NE2A1_0", + "IOI_EE4A2_1", + "IOI_OCLKM_1", + "IOI_IMUX43_0", + "LIOI_I2GCLK_BOT1", + "IOI_LH8_1", + "IOI_RCLK_DIV_CE1", + "IOI_LOGIC_OUTS17_0", + "IOI_SE2A3_0", + "IOI_ILOGIC1_Q6", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LH9_0", + "IOI_OLOGIC0_D2", + "IOI_OLOGIC0_CLKDIVB", + "IOI_IMUX30_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_LOGIC_OUTS0_0", + "IOI_WW2A1_0", + "IOI_BYP7_1", + "IOI_SE4C1_0", + "IOI_IMUX39_1", + "IOI_OCLK_1", + "IOI_EL1BEG0_1", + "IOI_ILOGIC0_Q4", + "IOI_IMUX45_1", + "IOI_IMUX20_0", + "IOI_ODELAY1_REGRST", + "IOI_OLOGIC0_D5", + "IOI_ODELAY1_INC", + "IOI_ODELAY1_CNTVALUEIN3", + "IOI_WW2A0_1", + "IOI_NW2A1_0", + "IOI_WW2A2_0", + "IOI_EE2BEG3_1", + "IOI_ILOGIC0_Q8", + "IOI_IMUX24_0", + "IOI_OLOGIC0_T2", + "IOI_IDELAY0_LD", + "IOI_FAN5_1", + "LIOI_O1", + "IOI_OLOGIC1_T2", + "IOI_LOGIC_OUTS3_1", + "IOI_FAN3_1", + "IOI_BYP0_0", + "IOI_IMUX35_1", + "IOI_ILOGIC1_OCLKB", + "IOI_IMUX27_1", + "IOI_WW4END3_1", + "IOI_BLOCK_OUTS2_1", + "LIOI_OSOUT20", + "IOI_EE2BEG2_0", + "IOI_NE2A3_0", + "IOI_SE2A1_1", + "IOI_NE4BEG3_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_LH12_0", + "IOI_LH2_1", + "IOI_ER1BEG3_1", + "IOI_LH1_1", + "IOI_ILOGIC1_CE2", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_FAN4_1", + "IOI_IDELAY0_CE", + "LIOI_OSIN10", + "IOI_EE4C2_1", + "IOI_OLOGIC0_CLK", + "IOI_LOGIC_OUTS12_1", + "IOI_SW2A3_0", + "LIOI_IBUF0", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_ODELAY1_CNTVALUEIN2", + "LIOI_OLOGIC1_TFB_LOCAL", + "IOI_SW2A1_1", + "LIOI_OLOGIC0_TFB_LOCAL", + "IOI_LH1_0", + "IOI_FAN1_1", + "LIOI_OSOUT21", + "LIOI3_IDELAY1_IFDLY2", + "IOI_LOGIC_OUTS10_1", + "IOI_LOGIC_OUTS22_0", + "IOI_IMUX34_1", + "IOI_WW4A1_0", + "IOI_FAN7_0", + "IOI_IDELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OCLK_0", + "IOI_ODELAY0_REGRST", + "IOI_LOGIC_OUTS15_0", + "IOI_LEAF_GCLK0", + "LIOI_ILOGIC1_OFB", + "IOI_EE2A0_1", + "IOI_IMUX12_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_IMUX23_1", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_LOGIC_OUTS15_1", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_EL1BEG3_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IMUX39_0", + "IOI_WR1END0_0", + "IOI_ODELAY1_CNTVALUEIN4", + "IOI_IMUX19_0", + "IOI_RCLK_FORIO3", + "IOI_BYP1_0", + "IOI_ILOGIC0_Q2", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_NW2A3_1", + "IOI_IDELAY0_C", + "IOI_NW2A2_1", + "IOI_SW4END2_0", + "IOI_SW4END0_0", + "IOI_IMUX32_1", + "IOI_IMUX19_1", + "IOI_SW2A0_0", + "IOI_IMUX46_0", + "IOI_WR1END1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_LOGIC_OUTS1_0", + "IOI_IMUX8_0", + "IOI_WW4C2_1", + "LIOI_ISOUT20", + "LIOI_OLOGIC1_OFB", + "IOI_WW2END3_1", + "IOI_WW4C3_1", + "IOI_LH5_1", + "IOI_ODELAY1_CE", + "IOI_ILOGIC1_CLKDIVP", + "IOI_OLOGIC0_T4", + "IOI_NE4C2_0", + "IOI_IMUX31_1", + "IOI_NE4C3_0", + "IOI_NW4END2_1", + "IOI_IMUX7_1", + "IOI_IDELAY1_LD", + "IOI_LOGIC_OUTS23_1", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_LOGIC_OUTS9_0", + "IOI_EE2A0_0", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_WW4A3_1", + "IOI_IMUX9_1", + "IOI_NW2A1_1", + "IOI_IMUX1_0", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS9_1", + "IOI_IMUX42_1", + "IOI_RCLK_DIV_CLR3", + "IOI_IMUX21_1", + "IOI_EE2BEG0_0", + "IOI_IMUX1_1", + "IOI_OLOGIC1_T4", + "IOI_LH7_1", + "IOI_LOGIC_OUTS0_1", + "IOI_ILOGIC1_O", + "LIOI_IDELAY1_DATAOUT", + "LIOI_ODELAY0_OFDLY2", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_LOGIC_OUTS2_0", + "IOI_FAN0_1", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_ILOGIC0_OCLK", + "IOI_IMUX30_0", + "IOI_SE4C1_1", + "IOI_NE4BEG0_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LOGIC_OUTS4_1", + "LIOI_ISIN10", + "IOI_WL1END2_1", + "IOI_LEAF_GCLK5", + "IOI_IMUX43_1", + "LIOI_ODELAY1_DATAOUT", + "LIOI_OLOGIC1_TQ", + "LIOI_ISOUT11", + "IOI_EE2BEG2_1", + "IOI_NW4A2_0", + "IOI_ER1BEG1_1", + "IOI_NW4END0_0", + "IOI_BYP5_0", + "IOI_ILOGIC1_Q3", + "IOI_LH4_1", + "IOI_IMUX37_0", + "IOI_IDELAY1_DATAIN", + "IOI_IMUX_RC3", + "IOI_ILOGIC0_CLKB", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IDELAY1_CNTVALUEIN3", + "IOI_IDELAY1_CNTVALUEIN2", + "IOI_IMUX16_0", + "LIOI_O0", + "IOI_SW4A2_1", + "IOI_WW4END0_0", + "IOI_BLOCK_OUTS2_0", + "IOI_EE4BEG2_1", + "LIOI_ODELAY0_OFDLY0", + "IOI_NW2A3_0", + "IOI_IMUX_RC0", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WR1END3_1", + "IOI_NW4END1_1", + "LIOI_OSOUT10", + "IOI_SE2A2_0", + "LIOI_OLOGIC0_OQ", + "IOI_ILOGIC0_Q6", + "IOI_NW4A3_1", + "IOI_EE4B2_1", + "IOI_SE4BEG3_0", + "LIOI_OSIN20", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_IMUX36_0", + "IOI_LOGIC_OUTS5_0", + "IOI_LH8_0", + "IOI_IMUX12_0", + "IOI_EE4C3_0", + "IOI_ODELAY1_CNTVALUEOUT2", + "IOI_SW4END0_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_OLOGIC1_CLKDIVFB", + "IOI_IMUX0_1", + "IOI_CLK1_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_OLOGIC0_D7", + "IOI_BLOCK_OUTS3_1", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_WW4END3_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_OLOGIC1_D6", + "IOI_IMUX29_0", + "IOI_LOGIC_OUTS18_0", + "IOI_WL1END1_0", + "IOI_LH6_1", + "IOI_EL1BEG0_0", + "IOI_ILOGIC1_Q2", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_LEAF_GCLK1", + "IOI_EE2A1_0", + "IOI_WW4B1_0", + "IOI_DCI_TSTHLP", + "IOI_EE4A0_0", + "IOI_BYP3_0", + "IOI_FAN6_0", + "IOI_LOGIC_OUTS10_0", + "IOI_SE4BEG2_1", + "IOI_IMUX29_1", + "IOI_IDELAY0_LDPIPEEN", + "IOI_ILOGIC0_SR", + "IOI_WW4A0_0", + "IOI_NE4BEG2_1", + "IOI_IDELAY1_CE", + "IOI_WL1END0_0", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IDELAY0_INC", + "IOI_SE4C0_1", + "IOI_OLOGIC1_T3", + "IOI_LH10_0", + "IOI_EE4A3_0", + "LIOI_OLOGIC1_OQ", + "IOI_ILOGIC1_CE1", + "IOI_FAN7_1", + "IOI_WW4B3_0", + "LIOI_PD_INT_EN_0", + "LIOI_T0", + "IOI_WL1END0_1", + "IOI_IMUX45_0", + "IOI_ODELAY1_C", + "IOI_LH12_1", + "IOI_WW2END3_0", + "IOI_WR1END2_0", + "IOI_IMUX11_0", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_NE2A0_0", + "IOI_NW4END0_1", + "IOI_WW4A2_1", + "IOI_EL1BEG3_1", + "LIOI_PU_INT_EN_1", + "IOI_EE2A3_1", + "LIOI_ILOGIC0_DDLY", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_WR1END2_1", + "IOI_ODELAY0_LD", + "IOI_MONITOR_P", + "IOI_EE4BEG3_1", + "IOI_WW2END0_1", + "IOI_OLOGIC0_CLKB", + "IOI_RCLK_DIV_CE2", + "IOI_OLOGIC1_D2", + "IOI_LH11_1", + "IOI_IMUX34_0", + "IOI_LH9_1", + "IOI_BYP6_0", + "IOI_ILOGIC1_BITSLIP", + "LIOI_ILOGIC1_TFB", + "IOI_SE4BEG3_1", + "IOI_TBYTEIN", + "IOI_WW4B2_1", + "IOI_ODELAY1_CNTVALUEOUT4", + "IOI_IMUX14_0", + "LIOI_ILOGIC0_TFB", + "LIOI_OLOGIC0_TFB", + "IOI_LOGIC_OUTS12_0", + "IOI_NW4A3_0", + "IOI_SE4C0_0", + "IOI_NE2A1_1", + "IOI_LOGIC_OUTS20_1", + "IOI_SW4A3_0", + "IOI_SE4C2_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_BLOCK_OUTS1_1", + "IOI_EE4A0_1", + "IOI_WL1END3_0", + "IOI_WW2A3_0", + "IOI_CLK0_0", + "LIOI_DIFF_TERM_INT_EN", + "IOI_NE4BEG1_0", + "IOI_OLOGIC1_TCE", + "IOI_OLOGIC1_D3", + "IOI_LOGIC_OUTS6_0", + "IOI_IMUX2_1", + "LIOI_IDELAY0_DATAOUT", + "IOI_ODELAY1_CNTVALUEOUT1", + "IOI_IMUX44_1", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE4A3_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX5_1", + "IOI_EE2A1_1", + "IOI_WW4B3_1", + "IOI_ILOGIC1_Q4", + "LIOI_ODELAY1_OFDLY0", + "IOI_WW2A1_1", + "IOI_INT_DCI_EN", + "IOI_IMUX47_1", + "IOI_IMUX3_1", + "IOI_IMUX6_1", + "LIOI_ODELAY0_OFDLY1", + "IOI_NE2A2_0", + "IOI_WW4B2_0", + "IOI_FAN6_1", + "IOI_BLOCK_OUTS3_0", + "IOI_IDELAY0_DATAIN", + "IOI_EE4B0_1", + "IOI_LOGIC_OUTS13_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_LH11_0", + "IOI_LH10_1", + "IOI_NW4A0_0", + "IOI_BYP2_1", + "IOI_LOGIC_OUTS5_1", + "IOI_NW4END2_0", + "IOI_WW4C1_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WR1END1_1", + "IOI_LOGIC_OUTS16_1", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC1_CLK", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_IMUX7_0", + "IOI_FAN1_0", + "IOI_IMUX41_1", + "IOI_WW2A3_1", + "IOI_SE2A3_1", + "LIOI_ODELAY0_ODATAIN", + "IOI_LOGIC_OUTS2_1", + "IOI_CTRL1_0", + "IOI_RCLK_FORIO0", + "IOI_IMUX8_1", + "IOI_SW4A0_0", + "IOI_BLOCK_OUTS1_0", + "IOI_WW4A3_0", + "IOI_ER1BEG0_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_RCLK_DIV_CLR1_1", + "LIOI_KEEPER_INT_EN_0", + "IOI_RCLK_DIV_CLR2", + "IOI_NW4A1_1", + "IOI_EL1BEG1_0", + "LIOI_ODELAY0_DATAOUT", + "LIOI_OLOGIC1_CLKDIVF", + "IOI_FAN2_0", + "IOI_CTRL0_0", + "IOI_ILOGIC1_Q5", + "IOI_SE4BEG1_0", + "IOI_OLOGIC0_SR", + "IOI_ODELAY1_LDPIPEEN", + "IOI_LH2_0", + "IOI_EE4C3_1", + "IOI_ODELAY0_CE", + "IOI_EE2A3_0", + "IOI_OLOGIC1_D1", + "IOI_NW4A0_1", + "IOI_LOGIC_OUTS3_0", + "IOI_EE4C0_1", + "IOI_ILOGIC1_CLK", + "IOI_SW4END2_1", + "IOI_WW4C2_0", + "IOI_IMUX33_1", + "IOI_WW2END1_0", + "LIOI_KEEPER_INT_EN_1", + "LIOI_OLOGIC0_TQ", + "IOI_SE2A0_1", + "IOI_LOGIC_OUTS8_1", + "IOI_LH5_0", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_ILOGIC0_Q1", + "IOI_OLOGIC1_CLKDIVB", + "IOI_NE4C1_1", + "IOI_NE4BEG0_1", + "IOI_OLOGIC1_SR", + "IOI_EE4B1_1", + "IOI_IMUX14_1", + "IOI_ODELAY0_C", + "IOI_IMUX35_0", + "IOI_RCLK_DIV_CLR0", + "IOI_ILOGIC1_SR", + "LIOI_IBUF_DISABLE1", + "IOI_NE4BEG1_1", + "IOI_BYP6_1", + "IOI_ER1BEG2_1", + "IOI_IMUX4_0", + "IOI_EE4BEG2_0", + "IOI_LOGIC_OUTS4_0", + "IOI_NE2A2_1", + "LIOI_IBUF1", + "IOI_LOGIC_OUTS7_1", + "IOI_IMUX24_1", + "IOI_IMUX18_0", + "IOI_NE4C1_0", + "IOI_EE4BEG1_1", + "IOI_BYP4_0", + "IOI_EE2A2_1", + "IOI_ER1BEG1_0", + "IOI_WL1END1_1", + "IOI_IMUX31_0", + "IOI_ER1BEG2_0", + "IOI_IMUX28_1", + "IOI_WW4C0_1", + "IOI_SE4C2_0", + "IOI_LOGIC_OUTS17_1", + "IOI_ODELAY0_CNTVALUEIN0", + "LIOI_OLOGIC1_TFB", + "IOI_IMUX_RC2", + "IOI_WW4END2_0" + ], + "tile_type": "LIOI3_TBYTESRC", + "sites": [ + { + "site_pins": { + "T2": "IOI_OLOGIC1_T2", + "D5": "IOI_OLOGIC1_D5", + "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", + "D8": "IOI_OLOGIC1_D8", + "SR": "IOI_OLOGIC1_SR", + "SHIFTOUT1": "LIOI_OSOUT11", + "T4": "IOI_OLOGIC1_T4", + "SHIFTIN1": null, + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "OCE": "IOI_OLOGIC1_OCE", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "CLKB": "IOI_OLOGIC1_CLKB", + "OQ": "LIOI_OLOGIC1_OQ", + "D3": "IOI_OLOGIC1_D3", + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "SHIFTIN2": null, + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "D1": "IOI_OLOGIC1_D1", + "CLK": "IOI_OLOGIC1_CLK", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "T1": "IOI_OLOGIC1_T1", + "D4": "IOI_OLOGIC1_D4", + "TCE": "IOI_OLOGIC1_TCE", + "D2": "IOI_OLOGIC1_D2", + "SHIFTOUT2": "LIOI_OSOUT21", + "OFB": "LIOI_OLOGIC1_OFB", + "TFB": "LIOI_OLOGIC1_TFB", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "T3": "IOI_OLOGIC1_T3", + "D6": "IOI_OLOGIC1_D6", + "TQ": "LIOI_OLOGIC1_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "CLK": "IOI_ILOGIC1_CLK", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "Q3": "IOI_ILOGIC1_Q3", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "D": "LIOI_ILOGIC1_D", + "SR": "IOI_ILOGIC1_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC1_CE1", + "Q8": "IOI_ILOGIC1_Q8", + "SHIFTIN2": "LIOI_ISIN21", + "Q2": "IOI_ILOGIC1_Q2", + "CE2": "IOI_ILOGIC1_CE2", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "SHIFTOUT2": "LIOI_ISOUT21", + "O": "IOI_ILOGIC1_O", + "OFB": "LIOI_ILOGIC1_OFB", + "TFB": "LIOI_ILOGIC1_TFB", + "Q4": "IOI_ILOGIC1_Q4", + "CLKB": "IOI_ILOGIC1_CLKB", + "Q1": "IOI_ILOGIC1_Q1", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN1": "LIOI_ISIN11", + "Q6": "IOI_ILOGIC1_Q6", + "DDLY": "LIOI_ILOGIC1_DDLY", + "SHIFTOUT1": "LIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC1_Q7", + "OCLKB": "IOI_ILOGIC1_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "T2": "IOI_OLOGIC0_T2", + "D5": "IOI_OLOGIC0_D5", + "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", + "D8": "IOI_OLOGIC0_D8", + "SR": "IOI_OLOGIC0_SR", + "SHIFTOUT1": "LIOI_OSOUT10", + "T4": "IOI_OLOGIC0_T4", + "SHIFTIN1": "LIOI_OSIN10", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "OCE": "IOI_OLOGIC0_OCE", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "CLKB": "IOI_OLOGIC0_CLKB", + "OQ": "LIOI_OLOGIC0_OQ", + "D3": "IOI_OLOGIC0_D3", + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "SHIFTIN2": "LIOI_OSIN20", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "D1": "IOI_OLOGIC0_D1", + "CLK": "IOI_OLOGIC0_CLK", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "T1": "IOI_OLOGIC0_T1", + "D4": "IOI_OLOGIC0_D4", + "TCE": "IOI_OLOGIC0_TCE", + "D2": "IOI_OLOGIC0_D2", + "SHIFTOUT2": "LIOI_OSOUT20", + "OFB": "LIOI_OLOGIC0_OFB", + "TFB": "LIOI_OLOGIC0_TFB", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "T3": "IOI_OLOGIC0_T3", + "D6": "IOI_OLOGIC0_D6", + "TQ": "LIOI_OLOGIC0_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "CLK": "IOI_ILOGIC0_CLK", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "Q3": "IOI_ILOGIC0_Q3", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "D": "LIOI_ILOGIC0_D", + "SR": "IOI_ILOGIC0_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC0_CE1", + "Q8": "IOI_ILOGIC0_Q8", + "SHIFTIN2": null, + "Q2": "IOI_ILOGIC0_Q2", + "CE2": "IOI_ILOGIC0_CE2", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "SHIFTOUT2": "LIOI_ISOUT20", + "O": "IOI_ILOGIC0_O", + "OFB": "LIOI_ILOGIC0_OFB", + "TFB": "LIOI_ILOGIC0_TFB", + "Q4": "IOI_ILOGIC0_Q4", + "CLKB": "IOI_ILOGIC0_CLKB", + "Q1": "IOI_ILOGIC0_Q1", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN1": null, + "Q6": "IOI_ILOGIC0_Q6", + "DDLY": "LIOI_ILOGIC0_DDLY", + "SHIFTOUT1": "LIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC0_Q7", + "OCLKB": "IOI_ILOGIC0_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "IFDLY0": "LIOI3_IDELAY1_IFDLY0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", + "LD": "IOI_IDELAY1_LD", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "IDATAIN": "LIOI_IDELAY1_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "IFDLY2": "LIOI3_IDELAY1_IFDLY2", + "C": "IOI_IDELAY1_C", + "IFDLY1": "LIOI3_IDELAY1_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "DATAOUT": "LIOI_IDELAY1_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "IFDLY0": "LIOI3_IDELAY0_IFDLY0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", + "LD": "IOI_IDELAY0_LD", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "IDATAIN": "LIOI_IDELAY0_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "IFDLY2": "LIOI3_IDELAY0_IFDLY2", + "C": "IOI_IDELAY0_C", + "IFDLY1": "LIOI3_IDELAY0_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "DATAOUT": "LIOI_IDELAY0_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_LIOI3_TBYTETERM.json b/artix7/tile_type_LIOI3_TBYTETERM.json index a32589e..aa86cdd 100644 --- a/artix7/tile_type_LIOI3_TBYTETERM.json +++ b/artix7/tile_type_LIOI3_TBYTETERM.json @@ -1,3879 +1,3879 @@ { - "wires": [ - "IOI_LOGIC_OUTS17_1", - "IOI_WW2END3_1", - "IOI_SE4BEG2_0", - "IOI_NW4A2_0", - "IOI_NW4END1_0", - "IOI_IMUX21_1", - "IOI_WR1END3_0", - "IOI_NE2A2_0", - "IOI_IMUX20_0", - "IOI_EE2BEG2_0", - "IOI_BYP3_1", - "IOI_OLOGIC1_D8", - "LIOI_ILOGIC0_TFB", - "LIOI_OLOGIC0_OFB", - "IOI_CLK1_1", - "IOI_ODELAY0_C", - "IOI_IMUX3_1", - "IOI_WR1END3_1", - "IOI_NW4END1_1", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_WW4END0_1", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_EE2A3_1", - "IOI_OLOGIC1_D6", - "IOI_IMUX9_1", - "IOI_IMUX35_0", - "IOI_BLOCK_OUTS3_1", - "IOI_OLOGIC0_D2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_OLOGIC0_CLKDIV", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_RCLK_DIV_CE2", - "IOI_SW2A2_1", - "IOI_WW4END1_1", - "IOI_ODELAY0_CE", - "IOI_NE2A1_0", - "IOI_IMUX0_0", - "IOI_ER1BEG0_0", - "LIOI_ILOGIC1_TFB", - "IOI_IMUX10_1", - "IOI_ILOGIC0_BITSLIP", - "IOI_NE4C3_0", - "IOI_IMUX10_0", - "IOI_EE4B3_0", - "IOI_IMUX45_1", - "IOI_LH4_0", - "IOI_NW4END2_0", - "IOI_OLOGIC0_SR", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_LH1_0", - "IOI_EE4A1_1", - "LIOI_IBUF_DISABLE1", - "IOI_LOGIC_OUTS2_1", - "IOI_BLOCK_OUTS1_0", - "IOI_WW4B1_0", - "LIOI_KEEPER_INT_EN_1", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_LH2_0", - "IOI_IDELAYCTRL_OUTN1", - "IOI_FAN4_1", - "IOI_IMUX12_1", - "IOI_OLOGIC1_TBYTEIN", - "IOI_IMUX1_1", - "IOI_IMUX8_0", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_CTRL0_0", - "IOI_IDELAY1_INC", - "IOI_IMUX24_1", - "IOI_SW2A2_0", - "IOI_NW4A2_1", - "IOI_LOGIC_OUTS12_1", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_INC", - "IOI_OLOGIC0_T4", - "IOI_ER1BEG1_0", - "LIOI_ISIN21", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_IMUX14_1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_ILOGIC1_Q1", - "IOI_EL1BEG2_0", - "IOI_ILOGIC1_SR", - "LIOI_ODELAY1_OFDLY2", - "IOI_NE4BEG2_0", - "IOI_EL1BEG3_1", - "IOI_TBYTEIN_TERM", - "IOI_SW2A0_0", - "IOI_IMUX36_1", - "IOI_IMUX24_0", - "IOI_NW4END3_1", - "IOI_OLOGIC1_D2", - "IOI_EE4C1_1", - "IOI_LOGIC_OUTS21_0", - "IOI_IMUX4_1", - "IOI_WW4C3_0", - "IOI_OLOGIC0_D7", - "IOI_EE2A1_1", - "IOI_IMUX37_0", - "IOI_IDELAY1_CE", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_WW2A2_0", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_BYP4_1", - "IOI_IMUX42_1", - "IOI_OLOGIC1_TBYTEOUT", - "LIOI3_IDELAY0_IFDLY1", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_IMUX30_0", - "IOI_IMUX35_1", - "IOI_LOGIC_OUTS19_1", - "IOI_LH8_1", - "IOI_IMUX33_0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_EE4BEG3_1", - "IOI_NE2A2_1", - "LIOI_ISIN10", - "IOI_ILOGIC0_Q2", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_BYP7_0", - "IOI_SW4A2_0", - "IOI_IMUX42_0", - "IOI_WR1END0_1", - "IOI_WW2A2_1", - "IOI_MONITOR_P", - "IOI_NE4C1_0", - "IOI_IMUX29_0", - "IOI_OCLKM_1", - "IOI_WW4B2_1", - "IOI_OLOGIC0_REV", - "IOI_WW4END3_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LH7_1", - "IOI_NW2A3_1", - "IOI_LH12_1", - "IOI_EE4BEG2_0", - "IOI_LH7_0", - "IOI_ER1BEG3_0", - "IOI_IMUX0_1", - "IOI_LOGIC_OUTS7_1", - "IOI_ILOGIC0_Q3", - "IOI_IDELAY0_LDPIPEEN", - "IOI_WW2END2_0", - "IOI_LH11_1", - "IOI_IDELAY1_CINVCTRL", - "IOI_NW4A3_1", - "IOI_IMUX23_0", - "IOI_IMUX37_1", - "IOI_LOGIC_OUTS3_0", - "LIOI_OLOGIC1_CLKDIVF", - "IOI_WW4A0_0", - "IOI_IOCLK0", - "IOI_WW2END3_0", - "LIOI_IDELAY1_IDATAIN", - "LIOI_OLOGIC1_TFB_LOCAL", - "IOI_NE4BEG3_0", - "IOI_SE2A2_1", - "IOI_LEAF_GCLK0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IMUX18_1", - "IOI_IDELAY0_CE", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_NW4END3_0", - "LIOI_ODELAY1_ODATAIN", - "IOI_WW4C0_1", - "IOI_SE4C3_0", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IMUX39_1", - "IOI_NW4A1_0", - "IOI_NE4BEG2_1", - "IOI_SE4BEG0_0", - "IOI_IMUX14_0", - "IOI_IMUX22_1", - "LIOI_O0", - "IOI_CLK1_0", - "IOI_SE4BEG3_0", - "LIOI_I2GCLK_TOP0", - "IOI_OLOGIC0_D6", - "IOI_WW2A1_1", - "IOI_EE2A3_0", - "IOI_IMUX28_0", - "IOI_OCLK_0", - "IOI_IMUX18_0", - "IOI_NW2A1_1", - "IOI_IDELAY1_C", - "IOI_WW4A2_0", - "IOI_NE4C0_0", - "IOI_NW2A1_0", - "IOI_IMUX2_1", - "IOI_LOGIC_OUTS9_0", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_IMUX16_0", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_BLOCK_OUTS2_1", - "IOI_WL1END3_0", - "IOI_LOGIC_OUTS7_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_IDELAYCTRL_RDY", - "IOI_RCLK_DIV_CLR2", - "IOI_IMUX11_0", - "IOI_LOGIC_OUTS16_1", - "IOI_RCLK_DIV_CE3", - "IOI_WR1END2_0", - "IOI_LOGIC_OUTS18_1", - "IOI_SW4A0_0", - "LIOI_OLOGIC0_TFB", - "IOI_NE4BEG1_1", - "IOI_WR1END1_0", - "IOI_OLOGIC1_CLK", - "IOI_EE4B0_0", - "IOI_WW4A3_1", - "IOI_RCLK_DIV_CLR1", - "IOI_LOGIC_OUTS15_0", - "IOI_WW4B0_0", - "IOI_OLOGIC1_D3", - "IOI_ODELAY1_LD", - "LIOI3_IDELAY1_IFDLY2", - "IOI_NW4END2_1", - "IOI_LOGIC_OUTS10_1", - "LIOI_PU_INT_EN_1", - "IOI_NE2A3_1", - "IOI_NW2A0_0", - "IOI_WW4END3_0", - "IOI_IOCLK3", - "LIOI_I0", - "IOI_SE2A3_0", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_WW2A3_0", - "IOI_ILOGIC0_CE1", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_BYP1_1", - "IOI_SE4C1_1", - "IOI_SW4A3_1", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IMUX38_1", - "IOI_ER1BEG2_0", - "IOI_WW4C0_0", - "IOI_IMUX25_0", - "IOI_NE4BEG0_0", - "IOI_IMUX7_1", - "IOI_FAN3_1", - "IOI_OLOGIC1_SR", - "IOI_SW4END1_0", - "IOI_ILOGIC1_CE2", - "IOI_WW4END0_0", - "IOI_FAN7_0", - "IOI_LOGIC_OUTS1_0", - "LIOI_ILOGIC0_DDLY", - "IOI_EE2BEG0_0", - "IOI_SE4C0_1", - "IOI_OLOGIC1_T3", - "LIOI_ILOGIC0_D", - "IOI_IMUX43_1", - "IOI_EE2BEG3_1", - "IOI_NE4C3_1", - "IOI_IMUX46_0", - "IOI_IMUX34_1", - "IOI_IMUX27_0", - "IOI_DCI_TSTCLK", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_D8", - "IOI_ODELAY1_CNTVALUEOUT2", - "LIOI3_IDELAY1_IFDLY1", - "IOI_EE4C2_0", - "IOI_IMUX11_1", - "IOI_CTRL1_0", - "IOI_DCI_TSTHLP", - "LIOI_OLOGIC0_TQ", - "IOI_EE4A3_0", - "LIOI_ODELAY0_OFDLY2", - "IOI_OLOGIC0_CLKB", - "IOI_WW4C3_1", - "IOI_IMUX40_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_IMUX47_0", - "IOI_OLOGIC1_CLKDIV", - "IOI_LOGIC_OUTS5_1", - "LIOI_I2GCLK_TOP1", - "IOI_BYP7_1", - "IOI_LOGIC_OUTS12_0", - "IOI_SE4BEG0_1", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_LOGIC_OUTS5_0", - "IOI_FAN4_0", - "IOI_WW4B0_1", - "IOI_WL1END0_1", - "IOI_IMUX2_0", - "IOI_WW2END0_0", - "IOI_LH2_1", - "IOI_WW4A1_1", - "IOI_WW4C1_1", - "IOI_ER1BEG2_1", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_OLOGIC0_T1", - "LIOI_I2GCLK_BOT1", - "IOI_IMUX3_0", - "IOI_EE2BEG1_0", - "IOI_IMUX29_1", - "IOI_WW2END0_1", - "IOI_OCLK_1", - "IOI_WW2A0_0", - "IOI_ER1BEG1_1", - "IOI_RCLK_FORIO2", - "IOI_PHASER_TO_IO_ICLK", - "IOI_NE4C2_0", - "IOI_BYP2_1", - "IOI_WR1END1_1", - "IOI_FAN3_0", - "IOI_ILOGIC1_BITSLIP", - "LIOI3_IDELAY0_IFDLY0", - "IOI_ODELAY0_LDPIPEEN", - "IOI_IMUX44_1", - "IOI_NE2A1_1", - "IOI_LOGIC_OUTS1_1", - "IOI_EE4B0_1", - "IOI_OLOGIC1_CLKB", - "LIOI_OLOGIC1_OQ", - "IOI_RCLK_DIV_CLR0", - "IOI_ILOGIC1_CLKDIV", - "IOI_DCI_TSTHLN", - "IOI_OLOGIC1_D5", - "IOI_SW2A3_0", - "IOI_IDELAY1_REGRST", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_LOGIC_OUTS19_0", - "IOI_IMUX32_1", - "LIOI_ISIN11", - "IOI_SE2A1_1", - "IOI_LOGIC_OUTS21_1", - "IOI_EE2A2_0", - "IOI_ODELAY1_REGRST", - "IOI_LH9_0", - "IOI_FAN5_1", - "IOI_LH6_0", - "IOI_ODELAY1_C", - "IOI_IMUX19_0", - "IOI_OLOGIC1_D4", - "IOI_LOGIC_OUTS10_0", - "IOI_ILOGIC0_OCLK", - "LIOI_OLOGIC1_TFB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_INT_DCI_EN", - "IOI_EL1BEG0_1", - "IOI_SW2A1_0", - "IOI_OLOGIC1_D1", - "IOI_DCI_TSTRST0", - "IOI_OLOGIC0_T2", - "IOI_BLOCK_OUTS0_0", - "LIOI_DCI_T_TERM0", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_EE4BEG2_1", - "LIOI_IDELAY1_DATAOUT", - "IOI_SE4BEG3_1", - "LIOI_DIFF_TERM_INT_EN", - "LIOI_ISOUT11", - "IOI_OLOGIC1_T2", - "IOI_WW4A0_1", - "IOI_IMUX26_0", - "IOI_IMUX45_0", - "IOI_MONITOR_N", - "IOI_IMUX8_1", - "IOI_RCLK_DIV_CLR3", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY1_CE", - "LIOI_DCI_T_TERM1", - "IOI_LH6_1", - "IOI_IOCLK1", - "IOI_FAN7_1", - "LIOI_ODELAY0_OFDLY1", - "IOI_RCLK_DIV_CLR0_1", - "IOI_LOGIC_OUTS2_0", - "IOI_WW4A1_0", - "IOI_IMUX7_0", - "LIOI_ODELAY1_OFDLY1", - "IOI_ODELAY1_INC", - "IOI_ILOGIC0_CLK", - "IOI_IMUX20_1", - "IOI_WW2END1_1", - "IOI_LOGIC_OUTS11_0", - "IOI_SE4C0_0", - "IOI_LOGIC_OUTS17_0", - "IOI_ER1BEG3_1", - "IOI_ILOGIC0_CLKDIV", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_REV", - "LIOI_OLOGIC0_CLKDIVF", - "IOI_FAN1_1", - "IOI_LH10_0", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC0_CE2", - "IOI_FAN6_1", - "LIOI_ODELAY0_OFDLY0", - "IOI_IDELAY1_CNTVALUEOUT0", - "LIOI_KEEPER_INT_EN_0", - "LIOI_OSOUT21", - "IOI_IMUX5_0", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_SW4END0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_ILOGIC1_Q5", - "IOI_NE4BEG0_1", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_WW4B3_0", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_EE4BEG0_1", - "IOI_EE2BEG2_1", - "IOI_OLOGIC1_T1", - "IOI_IMUX6_1", - "IOI_EL1BEG2_1", - "IOI_SE4C1_0", - "IOI_NW4END0_1", - "IOI_IMUX1_0", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_REV", - "IOI_SE4C2_1", - "IOI_SE4BEG2_1", - "IOI_EE4A0_1", - "IOI_IMUX36_0", - "IOI_EE2BEG0_1", - "IOI_NW4A0_1", - "IOI_WW4END2_1", - "IOI_IMUX46_1", - "IOI_EE4A3_1", - "IOI_LOGIC_OUTS20_0", - "IOI_WL1END1_1", - "LIOI_OSIN21", - "IOI_SW4END1_1", - "LIOI3_IDELAY1_IFDLY0", - "IOI_IMUX13_1", - "IOI_ODELAY0_LD", - "IOI_ILOGIC1_Q8", - "IOI_IMUX23_1", - "IOI_IMUX_RC3", - "IOI_IMUX31_1", - "IOI_WW4A3_0", - "IOI_OLOGIC0_OCE", - "IOI_LOGIC_OUTS3_1", - "IOI_EE2A2_1", - "IOI_LOGIC_OUTS8_0", - "IOI_ILOGIC0_CLKB", - "IOI_IMUX27_1", - "IOI_NE2A0_1", - "IOI_RCLK_DIV_CE1", - "LIOI_O1", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_NE2A0_0", - "IOI_IDELAY0_REGRST", - "LIOI_OSOUT11", - "LIOI_OLOGIC0_OQ", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_SE4BEG1_1", - "IOI_IMUX_RC2", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_ILOGIC0_O", - "IOI_EE4A1_0", - "IOI_IDELAYCTRL_RST", - "IOI_SW4A1_0", - "IOI_EE4A2_1", - "IOI_LOGIC_OUTS9_1", - "IOI_WW4A2_1", - "IOI_FAN2_1", - "LIOI_OSOUT20", - "IOI_FAN5_0", - "IOI_IMUX16_1", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_IOCLK2", - "IOI_OLOGIC1_D7", - "IOI_IMUX6_0", - "IOI_LOGIC_OUTS4_0", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC1_Q4", - "IOI_NW4END0_0", - "IOI_FAN0_1", - "IOI_BLOCK_OUTS3_0", - "IOI_IMUX38_0", - "IOI_IDELAY0_CINVCTRL", - "LIOI_OLOGIC0_TFB_LOCAL", - "LIOI_IBUF_DISABLE0", - "IOI_OLOGIC1_OCE", - "LIOI_IDELAY0_IDATAIN", - "IOI_EE4A2_0", - "IOI_BLOCK_OUTS0_1", - "IOI_IMUX4_0", - "IOI_OLOGIC1_CLKDIVB", - "LIOI_PD_INT_EN_1", - "IOI_SW4END2_0", - "IOI_BYP0_1", - "IOI_IMUX_RC0", - "IOI_IMUX31_0", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IMUX15_0", - "IOI_EE4C3_0", - "IOI_LOGIC_OUTS11_1", - "IOI_NE4BEG1_0", - "IOI_SW4END2_1", - "IOI_PHASER_TO_IO_ICLKDIV", - "LIOI_OLOGIC1_OFB", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS4_1", - "IOI_WR1END0_0", - "LIOI_OSOUT10", - "LIOI_ILOGIC1_D", - "IOI_IDELAY0_C", - "IOI_SE2A2_0", - "IOI_LOGIC_OUTS13_0", - "IOI_ILOGIC1_OCLK", - "IOI_BYP4_0", - "IOI_WW2A1_0", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_IDELAY0_DATAIN", - "IOI_EE4B2_1", - "IOI_IMUX28_1", - "IOI_LEAF_GCLK5", - "IOI_SW4A3_0", - "IOI_BLOCK_OUTS1_1", - "IOI_WW4C1_0", - "IOI_IMUX9_0", - "IOI_BYP5_0", - "IOI_LOGIC_OUTS18_0", - "IOI_NW4A0_0", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_LH10_1", - "IOI_IMUX12_0", - "IOI_LOGIC_OUTS23_0", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_DCI_DCIDONE", - "IOI_SE2A0_0", - "IOI_IMUX21_0", - "IOI_EE4B1_1", - "IOI_RCLK_DIV_CE3_1", - "IOI_EE4BEG0_0", - "LIOI_ODELAY0_DATAOUT", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ILOGIC1_CLK", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_LOGIC_OUTS14_1", - "IOI_BYP3_0", - "IOI_EE2A0_1", - "IOI_LEAF_GCLK4", - "IOI_SW4A2_1", - "IOI_OLOGIC1_T4", - "IOI_LOGIC_OUTS0_0", - "IOI_WW2END1_0", - "IOI_BYP5_1", - "IOI_ER1BEG0_1", - "IOI_LOGIC_OUTS16_0", - "IOI_IMUX5_1", - "IOI_NW4A3_0", - "IOI_EE4BEG1_1", - "IOI_SW2A1_1", - "IOI_IDELAY0_LD", - "IOI_EE2A0_0", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_CLK0_1", - "IOI_RCLK_FORIO3", - "IOI_IMUX44_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_ILOGIC1_O", - "IOI_SE2A3_1", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ILOGIC1_REV", - "IOI_EE2A1_0", - "IOI_IMUX17_1", - "IOI_FAN1_0", - "IOI_EE4A0_0", - "IOI_LOGIC_OUTS22_0", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_RCLK_DIV_CE0", - "IOI_WW4C2_0", - "IOI_NW2A3_0", - "IOI_IMUX34_0", - "LIOI_ILOGIC0_OFB", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_NE4C2_1", - "IOI_IMUX22_0", - "IOI_OLOGIC0_T3", - "IOI_ODELAY1_CINVCTRL", - "IOI_IMUX17_0", - "LIOI_ISIN20", - "IOI_WW4B2_0", - "IOI_FAN6_0", - "IOI_IDELAY1_LDPIPEEN", - "LIOI_PU_INT_EN_0", - "IOI_WL1END0_0", - "IOI_OCLKM_0", - "IOI_IMUX15_1", - "IOI_CLK0_0", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IMUX25_1", - "IOI_EL1BEG0_0", - "IOI_OLOGIC0_CLK", - "IOI_IMUX39_0", - "IOI_WL1END1_0", - "IOI_WL1END2_0", - "IOI_IMUX41_0", - "IOI_CTRL0_1", - "IOI_EE4C0_0", - "IOI_ILOGIC1_Q6", - "IOI_NW2A0_1", - "IOI_EE2BEG1_1", - "IOI_ILOGIC1_Q2", - "IOI_CTRL1_1", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_OLOGIC0_D4", - "IOI_SE4BEG1_0", - "LIOI_ISOUT20", - "IOI_LOGIC_OUTS15_1", - "IOI_EE2BEG3_0", - "IOI_SW4A1_1", - "IOI_EL1BEG1_0", - "IOI_DCI_TSTRST", - "LIOI_ISOUT21", - "IOI_SW2A3_1", - "IOI_NE4C0_1", - "IOI_ILOGIC1_CLKDIVP", - "IOI_IMUX30_1", - "LIOI_ODELAY0_ODATAIN", - "IOI_ILOGIC0_Q5", - "IOI_IDELAYCTRL_OUTN65", - "IOI_WR1END2_1", - "IOI_WW4B1_1", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_EE4BEG3_0", - "IOI_SE2A0_1", - "IOI_FAN0_0", - "IOI_EE4BEG1_0", - "LIOI_OSIN10", - "IOI_IMUX47_1", - "IOI_LH1_1", - "LIOI_ISOUT10", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC0_OCLKB", - "LIOI_IBUF1", - "IOI_RCLK_DIV_CE2_1", - "IOI_BYP2_0", - "IOI_EE4C1_0", - "LIOI_IBUF0", - "IOI_WW2END2_1", - "IOI_IMUX43_0", - "IOI_BYP6_1", - "IOI_RCLK_FORIO1", - "IOI_ILOGIC1_OCLKB", - "IOI_LEAF_GCLK1", - "IOI_NW2A2_0", - "IOI_IMUX33_1", - "IOI_LH11_0", - "IOI_ILOGIC0_Q6", - "IOI_SW4END3_1", - "IOI_ODELAY1_CLKIN", - "IOI_NW2A2_1", - "IOI_LH9_1", - "LIOI_OLOGIC1_TQ", - "IOI_PHASER_TO_IO_OCLK", - "IOI_EE4B3_1", - "LIOI_OSIN20", - "IOI_WW4B3_1", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_Q3", - "IOI_FAN2_0", - "IOI_WW4C2_1", - "LIOI_I1", - "LIOI_ODELAY1_DATAOUT", - "LIOI_T1", - "IOI_WL1END2_1", - "IOI_RCLK_FORIO0", - "IOI_SW4A0_1", - "IOI_NW4A1_1", - "IOI_IMUX41_1", - "IOI_LOGIC_OUTS13_1", - "LIOI_PD_INT_EN_0", - "IOI_BLOCK_OUTS2_0", - "IOI_WW4END1_0", - "IOI_IMUX40_1", - "IOI_IMUX19_1", - "IOI_EE4B1_0", - "IOI_WL1END3_1", - "IOI_LEAF_GCLK2", - "IOI_ODELAY0_CLKIN", - "IOI_EE4B2_0", - "IOI_SE2A1_0", - "IOI_BYP6_0", - "IOI_IMUX32_0", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_DATAIN", - "IOI_EE4C2_1", - "IOI_LH5_1", - "IOI_ILOGIC0_Q7", - "LIOI_OSIN11", - "IOI_IMUX_RC1", - "IOI_EL1BEG3_0", - "IOI_WW2A3_1", - "IOI_NE4C1_1", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_SW4END3_0", - "LIOI3_IDELAY0_IFDLY2", - "IOI_WW2A0_1", - "LIOI_ILOGIC1_DDLY", - "IOI_NE4BEG3_1", - "IOI_SE4C2_0", - "LIOI_ODELAY1_OFDLY0", - "IOI_ODELAY0_INC", - "IOI_LOGIC_OUTS6_1", - "IOI_BYP1_0", - "IOI_NE2A3_0", - "IOI_ILOGIC1_Q7", - "LIOI_ILOGIC1_OFB", - "IOI_ODELAY0_REGRST", - "IOI_ILOGIC0_CLKDIVP", - "IOI_EE4C3_1", - "IOI_SE4C3_1", - "IOI_ILOGIC1_CLKB", - "IOI_LOGIC_OUTS23_1", - "IOI_OLOGIC0_D1", - "IOI_EE4C0_1", - "IOI_LOGIC_OUTS22_1", - "IOI_OLOGIC1_TCE", - "IOI_LH8_0", - "IOI_SW2A0_1", - "IOI_SW4END0_1", - "LIOI_IDELAY0_DATAOUT", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_LOGIC_OUTS14_0", - "IOI_ODELAY1_LDPIPEEN", - "IOI_LH12_0", - "IOI_IMUX13_0", - "IOI_LEAF_GCLK3", - "IOI_BYP0_0", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ILOGIC0_Q4", - "LIOI_T0", - "IOI_EL1BEG1_1", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_WW4END2_0", - "IOI_IMUX26_1", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_TBYTEIN", - "IOI_LOGIC_OUTS20_1" - ], - "sites": [ - { - "prefix": "OLOGIC", - "y_coord": 0, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC1_D1", - "D3": "IOI_OLOGIC1_D3", - "SR": "IOI_OLOGIC1_SR", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "TFB": "LIOI_OLOGIC1_TFB", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLK": "IOI_OLOGIC1_CLK", - "T4": "IOI_OLOGIC1_T4", - "OQ": "LIOI_OLOGIC1_OQ", - "D8": "IOI_OLOGIC1_D8", - "T1": "IOI_OLOGIC1_T1", - "D5": "IOI_OLOGIC1_D5", - "SHIFTOUT1": "LIOI_OSOUT11", - "T2": "IOI_OLOGIC1_T2", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "D4": "IOI_OLOGIC1_D4", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D2": "IOI_OLOGIC1_D2", - "TQ": "LIOI_OLOGIC1_TQ", - "T3": "IOI_OLOGIC1_T3", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "OCE": "IOI_OLOGIC1_OCE", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "SHIFTIN1": null, - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "TCE": "IOI_OLOGIC1_TCE", - "OFB": "LIOI_OLOGIC1_OFB", - "SHIFTIN2": null, - "SHIFTOUT2": "LIOI_OSOUT21", - "REV": null, - "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "ILOGIC", - "y_coord": 0, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q1": "IOI_ILOGIC1_Q1", - "SR": "IOI_ILOGIC1_SR", - "D": "LIOI_ILOGIC1_D", - "DDLY": "LIOI_ILOGIC1_DDLY", - "SHIFTIN2": "LIOI_ISIN21", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "Q3": "IOI_ILOGIC1_Q3", - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "Q8": "IOI_ILOGIC1_Q8", - "TFB": "LIOI_ILOGIC1_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC1_CE1", - "Q2": "IOI_ILOGIC1_Q2", - "Q6": "IOI_ILOGIC1_Q6", - "CLKB": "IOI_ILOGIC1_CLKB", - "Q7": "IOI_ILOGIC1_Q7", - "O": "IOI_ILOGIC1_O", - "CLK": "IOI_ILOGIC1_CLK", - "CE2": "IOI_ILOGIC1_CE2", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "SHIFTIN1": "LIOI_ISIN11", - "OCLK": "IOI_ILOGIC1_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "OFB": "LIOI_ILOGIC1_OFB", - "SHIFTOUT1": "LIOI_ISOUT11", - "SHIFTOUT2": "LIOI_ISOUT21", - "REV": null, - "CLKDIV": "IOI_ILOGIC1_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "OLOGIC", - "y_coord": 1, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC0_D1", - "D3": "IOI_OLOGIC0_D3", - "SR": "IOI_OLOGIC0_SR", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "TFB": "LIOI_OLOGIC0_TFB", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLK": "IOI_OLOGIC0_CLK", - "T4": "IOI_OLOGIC0_T4", - "OQ": "LIOI_OLOGIC0_OQ", - "D8": "IOI_OLOGIC0_D8", - "T1": "IOI_OLOGIC0_T1", - "D5": "IOI_OLOGIC0_D5", - "SHIFTOUT1": "LIOI_OSOUT10", - "T2": "IOI_OLOGIC0_T2", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "D4": "IOI_OLOGIC0_D4", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D2": "IOI_OLOGIC0_D2", - "TQ": "LIOI_OLOGIC0_TQ", - "T3": "IOI_OLOGIC0_T3", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "OCE": "IOI_OLOGIC0_OCE", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "SHIFTIN1": "LIOI_OSIN10", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "TCE": "IOI_OLOGIC0_TCE", - "OFB": "LIOI_OLOGIC0_OFB", - "SHIFTIN2": "LIOI_OSIN20", - "SHIFTOUT2": "LIOI_OSOUT20", - "REV": null, - "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "ILOGIC", - "y_coord": 1, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q1": "IOI_ILOGIC0_Q1", - "SR": "IOI_ILOGIC0_SR", - "D": "LIOI_ILOGIC0_D", - "DDLY": "LIOI_ILOGIC0_DDLY", - "SHIFTIN2": null, - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "Q3": "IOI_ILOGIC0_Q3", - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "Q8": "IOI_ILOGIC0_Q8", - "TFB": "LIOI_ILOGIC0_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC0_CE1", - "Q2": "IOI_ILOGIC0_Q2", - "Q6": "IOI_ILOGIC0_Q6", - "CLKB": "IOI_ILOGIC0_CLKB", - "Q7": "IOI_ILOGIC0_Q7", - "O": "IOI_ILOGIC0_O", - "CLK": "IOI_ILOGIC0_CLK", - "CE2": "IOI_ILOGIC0_CE2", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "SHIFTIN1": null, - "OCLK": "IOI_ILOGIC0_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "OFB": "LIOI_ILOGIC0_OFB", - "SHIFTOUT1": "LIOI_ISOUT10", - "SHIFTOUT2": "LIOI_ISOUT20", - "REV": null, - "CLKDIV": "IOI_ILOGIC0_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "IDELAY", - "y_coord": 0, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CE": "IOI_IDELAY1_CE", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "IFDLY2": "LIOI3_IDELAY1_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "LD": "IOI_IDELAY1_LD", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "IFDLY0": "LIOI3_IDELAY1_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "INC": "IOI_IDELAY1_INC", - "DATAOUT": "LIOI_IDELAY1_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY1_DATAIN", - "C": "IOI_IDELAY1_C", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "IDATAIN": "LIOI_IDELAY1_IDATAIN", - "REGRST": "IOI_IDELAY1_REGRST", - "IFDLY1": "LIOI3_IDELAY1_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IDELAY", - "y_coord": 1, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CE": "IOI_IDELAY0_CE", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "IFDLY2": "LIOI3_IDELAY0_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "LD": "IOI_IDELAY0_LD", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "IFDLY0": "LIOI3_IDELAY0_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "INC": "IOI_IDELAY0_INC", - "DATAOUT": "LIOI_IDELAY0_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY0_DATAIN", - "C": "IOI_IDELAY0_C", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "IDATAIN": "LIOI_IDELAY0_IDATAIN", - "REGRST": "IOI_IDELAY0_REGRST", - "IFDLY1": "LIOI3_IDELAY0_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "LIOI3_TBYTETERM.IOI_IMUX44_1->IOI_OLOGIC0_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC0_D", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_CTRL0_0->IOI_OLOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX26_1->IOI_IDELAY0_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_CLK1_1->IOI_IDELAY0_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_O", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX45_1->IOI_OLOGIC0_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX30_0->IOI_IDELAY1_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY1_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { - "can_invert": "0", - "dst_wire": "LIOI_IBUF_DISABLE0", - "is_directional": "1", - "src_wire": "IOI_IMUX9_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TQ", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q7", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX7_0->IOI_OLOGIC1_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE0", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX45_0->IOI_OLOGIC1_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR0_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX42_0->IOI_OLOGIC1_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX46_0->IOI_OLOGIC1_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC0_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN_TERM", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX32_0->IOI_IDELAY1_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC0_DDLY", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, "LIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_I0->LIOI_IDELAY0_IDATAIN": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY0_IDATAIN", - "is_directional": "1", - "src_wire": "LIOI_I0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC1_DDLY", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE2_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC1_TQ->>LIOI_T1": { - "can_invert": "0", - "dst_wire": "LIOI_T1", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TQ", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_ISOUT10->LIOI_ISIN11": { - "can_invert": "0", - "dst_wire": "LIOI_ISIN11", - "is_directional": "1", - "src_wire": "LIOI_ISOUT10", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX15_0->IOI_OLOGIC1_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q7", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_I1->LIOI_IDELAY1_IDATAIN": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY1_IDATAIN", - "is_directional": "1", - "src_wire": "LIOI_I1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC1_OQ->>LIOI_O1": { - "can_invert": "0", - "dst_wire": "LIOI_O1", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_OQ", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TFB", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX26_0->IOI_IDELAY1_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY1_DATAOUT", - "is_directional": "1", - "src_wire": "LIOI_IDELAY1_IDATAIN", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC0_OQ->>LIOI_O0": { - "can_invert": "0", - "dst_wire": "LIOI_O0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OQ", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX34_0->IOI_OLOGIC1_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_DDLY", - "is_directional": "1", - "src_wire": "LIOI_IDELAY1_DATAOUT", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX47_0->IOI_OLOGIC1_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX46_1->IOI_OLOGIC0_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_I1->LIOI_ILOGIC1_D": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_D", - "is_directional": "1", - "src_wire": "LIOI_I1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.LIOI_ISOUT20->LIOI_ISIN21": { - "can_invert": "0", - "dst_wire": "LIOI_ISIN21", - "is_directional": "1", - "src_wire": "LIOI_ISOUT20", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_1", - "is_directional": "1", "src_wire": "IOI_ILOGIC0_Q6", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_TFB", "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_IMUX21_1->IOI_OLOGIC0_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY1_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX44_0->IOI_OLOGIC1_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX40_1->IOI_OLOGIC0_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX13_1->IOI_OLOGIC0_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { - "can_invert": "0", - "dst_wire": "LIOI_DCI_T_TERM1", - "is_directional": "1", - "src_wire": "IOI_IMUX6_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_IMUX_RC1": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_1", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX30_1->IOI_IDELAY0_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC1_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN_TERM", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1" }, "LIOI3_TBYTETERM.LIOI_IBUF0->LIOI_I0": { "can_invert": "0", - "dst_wire": "LIOI_I0", - "is_directional": "1", "src_wire": "LIOI_IBUF0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { - "can_invert": "0", - "dst_wire": "LIOI_IDELAY0_DATAOUT", - "is_directional": "1", - "src_wire": "LIOI_IDELAY0_IDATAIN", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR1_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX32_1->IOI_IDELAY0_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_CTRL0_1->IOI_OLOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OSOUT11->LIOI_OSIN10": { - "can_invert": "0", - "dst_wire": "LIOI_OSIN10", - "is_directional": "1", - "src_wire": "LIOI_OSOUT11", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OSOUT21->LIOI_OSIN20": { - "can_invert": "0", - "dst_wire": "LIOI_OSIN20", - "is_directional": "1", - "src_wire": "LIOI_OSOUT21", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_CTRL1_0->IOI_ILOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR3", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE3_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "LIOI_I0" }, "LIOI3_TBYTETERM.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", - "is_directional": "1", "src_wire": "IOI_IMUX38_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3" }, - "LIOI3_TBYTETERM.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_IBUF1->LIOI_I1": { - "can_invert": "0", - "dst_wire": "LIOI_I1", - "is_directional": "1", - "src_wire": "LIOI_IBUF1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_1", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_OQ", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "LIOI_ILOGIC1_D", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX34_1->IOI_OLOGIC0_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", - "src_wire": "IOI_IMUX34_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" }, - "LIOI3_TBYTETERM.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_OQ", + "src_wire": "IOI_ILOGIC0_Q4", "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1" }, - "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "LIOI3_TBYTETERM.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", + "src_wire": "IOI_IMUX39_1", "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4" }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC1_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC1_OFB", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_CLK1_0->IOI_IDELAY1_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX42_1->IOI_OLOGIC0_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX13_0->IOI_OLOGIC1_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_IMUX_RC3": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC3", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY1_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_CTRL1_1->IOI_ILOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX21_0->IOI_OLOGIC1_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_IMUX_RC2": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC2", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q8", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q6", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_I0->LIOI_ILOGIC0_D": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_D", - "is_directional": "1", - "src_wire": "LIOI_I0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" }, "LIOI3_TBYTETERM.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D5", - "is_directional": "1", "src_wire": "IOI_IMUX43_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { - "can_invert": "0", - "dst_wire": "LIOI3_IDELAY0_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q8", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC0_TQ->>LIOI_T0": { - "can_invert": "0", - "dst_wire": "LIOI_T0", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TQ", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OQ", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX15_1->IOI_OLOGIC0_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_TQ", - "is_pseudo": "1" - }, - "LIOI3_TBYTETERM.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { - "can_invert": "0", - "dst_wire": "LIOI_IBUF_DISABLE1", - "is_directional": "1", - "src_wire": "IOI_IMUX9_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_OFB", - "is_directional": "1", - "src_wire": "LIOI_OLOGIC0_OFB", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { - "can_invert": "0", - "dst_wire": "LIOI_ILOGIC0_DDLY", - "is_directional": "1", - "src_wire": "LIOI_IDELAY0_DATAOUT", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { - "can_invert": "0", - "dst_wire": "LIOI_DCI_T_TERM0", - "is_directional": "1", - "src_wire": "IOI_IMUX6_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX47_1->IOI_OLOGIC0_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "LIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX7_1->IOI_OLOGIC0_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX40_0->IOI_OLOGIC1_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5" }, "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", - "dst_wire": "IOI_IMUX_RC0", - "is_directional": "1", "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "LIOI3_TBYTETERM.IOI_IMUX43_0->IOI_OLOGIC1_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", - "src_wire": "IOI_IMUX43_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" }, - "LIOI3_TBYTETERM.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_1", + "src_wire": "IOI_LEAF_GCLK2", "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" }, - "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR2", + "src_wire": "IOI_LEAF_GCLK4", "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" }, - "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "LIOI3_TBYTETERM.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", + "src_wire": "IOI_IMUX10_0", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" }, - "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", + "src_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL" }, - "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "LIOI3_TBYTETERM.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_0", + "src_wire": "IOI_IMUX21_1", "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.LIOI_I1->LIOI_IDELAY1_IDATAIN": { + "can_invert": "0", + "src_wire": "LIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY1_IDATAIN" + }, + "LIOI3_TBYTETERM.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TQ" + }, + "LIOI3_TBYTETERM.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "LIOI_ILOGIC1_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_TFB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "LIOI3_TBYTETERM.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "LIOI3_TBYTETERM.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_OFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_OFB" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB" + }, + "LIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.LIOI_ISOUT20->LIOI_ISIN21": { + "can_invert": "0", + "src_wire": "LIOI_ISOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN21" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY1" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "LIOI3_TBYTETERM.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR" + }, + "LIOI3_TBYTETERM.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TFB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1" + }, + "LIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1" + }, + "LIOI3_TBYTETERM.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2" + }, + "LIOI3_TBYTETERM.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "LIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_CLK1_0->IOI_IDELAY1_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C" + }, + "LIOI3_TBYTETERM.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "LIOI_ILOGIC0_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TQ->>LIOI_T0": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_T0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY1" + }, + "LIOI3_TBYTETERM.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY2" + }, + "LIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC0_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN_TERM", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0" + }, + "LIOI3_TBYTETERM.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.LIOI_I1->LIOI_ILOGIC1_D": { + "can_invert": "0", + "src_wire": "LIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_D" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "LIOI3_TBYTETERM.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY0_DATAOUT" + }, + "LIOI3_TBYTETERM.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_IMUX_RC2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE" + }, + "LIOI3_TBYTETERM.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "LIOI_ILOGIC1_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "LIOI3_TBYTETERM.LIOI_IBUF1->LIOI_I1": { + "can_invert": "0", + "src_wire": "LIOI_IBUF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_I1" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_TFB" + }, + "LIOI3_TBYTETERM.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB" + }, + "LIOI3_TBYTETERM.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM0" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1" + }, + "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY2" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "LIOI3_TBYTETERM.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN" + }, + "LIOI3_TBYTETERM.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_DDLY" + }, + "LIOI3_TBYTETERM.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_IMUX_RC3": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3" + }, + "LIOI3_TBYTETERM.LIOI_I0->LIOI_IDELAY0_IDATAIN": { + "can_invert": "0", + "src_wire": "LIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IDELAY0_IDATAIN" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_IMUX_RC1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OQ" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_IBUF_DISABLE1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP" + }, + "LIOI3_TBYTETERM.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY0_IFDLY0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OFB" + }, + "LIOI3_TBYTETERM.IOI_CLK1_1->IOI_IDELAY0_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C" + }, + "LIOI3_TBYTETERM.LIOI_I0->LIOI_ILOGIC0_D": { + "can_invert": "0", + "src_wire": "LIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_D" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "LIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_OQ->>LIOI_O1": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_O1" + }, + "LIOI3_TBYTETERM.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC0_DDLY" + }, + "LIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "can_invert": "0", + "src_wire": "IOI_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "LIOI3_TBYTETERM.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI3_IDELAY1_IFDLY0" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_OFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ILOGIC1_OFB" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_OFB" + }, + "LIOI3_TBYTETERM.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE" + }, + "LIOI3_TBYTETERM.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "LIOI3_TBYTETERM.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4" + }, + "LIOI3_TBYTETERM.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1" + }, + "LIOI3_TBYTETERM.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL" + }, + "LIOI3_TBYTETERM.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { + "can_invert": "0", + "src_wire": "LIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_IDELAY1_DATAOUT" + }, + "LIOI3_TBYTETERM.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST" + }, + "LIOI3_TBYTETERM.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.LIOI_OSOUT21->LIOI_OSIN20": { + "can_invert": "0", + "src_wire": "LIOI_OSOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN20" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2" + }, + "LIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC0_OQ->>LIOI_O0": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_O0" + }, + "LIOI3_TBYTETERM.LIOI_OSOUT11->LIOI_OSIN10": { + "can_invert": "0", + "src_wire": "LIOI_OSOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OSIN10" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_TQ" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE" + }, + "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "LIOI_ILOGIC0_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "LIOI3_TBYTETERM.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.LIOI_ISOUT10->LIOI_ISIN11": { + "can_invert": "0", + "src_wire": "LIOI_ISOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_ISIN11" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC1_TFB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TQ->>LIOI_T1": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_T1" + }, + "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "can_invert": "0", + "src_wire": "LIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC1_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN_TERM", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN" + }, + "LIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_DCI_T_TERM1" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1" + }, + "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1" + }, + "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "LIOI3_TBYTETERM.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "LIOI_OLOGIC0_OQ" + }, + "LIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" } }, - "tile_type": "LIOI3_TBYTETERM" + "wires": [ + "IOI_BYP5_1", + "IOI_IMUX26_1", + "IOI_NW4END3_1", + "IOI_ILOGIC1_REV", + "IOI_IMUX42_0", + "IOI_EE4A1_1", + "IOI_IMUX22_1", + "IOI_ILOGIC0_CE2", + "IOI_IMUX5_0", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "LIOI3_IDELAY1_IFDLY1", + "IOI_OLOGIC1_CLKB", + "IOI_WW4C1_1", + "IOI_ER1BEG0_1", + "IOI_IMUX23_0", + "IOI_RCLK_DIV_CLR0_1", + "IOI_OLOGIC1_T1", + "IOI_IOCLK3", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_RCLK_DIV_CE2_1", + "IOI_DCI_TSTRST", + "IOI_OLOGIC1_REV", + "IOI_WW4END1_0", + "IOI_CTRL0_1", + "IOI_MONITOR_N", + "IOI_ILOGIC1_Q7", + "IOI_IMUX38_0", + "LIOI_ISOUT21", + "IOI_WW4B1_1", + "IOI_EE4C1_1", + "IOI_IOCLK2", + "IOI_OLOGIC1_D8", + "IOI_LEAF_GCLK4", + "IOI_WW2END2_1", + "IOI_BYP2_0", + "IOI_ILOGIC1_Q1", + "IOI_IMUX36_1", + "IOI_LEAF_GCLK3", + "IOI_SW2A0_1", + "IOI_IMUX16_1", + "IOI_FAN2_1", + "IOI_IMUX27_0", + "IOI_IMUX22_0", + "IOI_EL1BEG2_1", + "IOI_NW4A1_0", + "IOI_BLOCK_OUTS0_1", + "IOI_SE2A1_0", + "LIOI_OSIN21", + "IOI_IMUX4_1", + "IOI_EL1BEG2_0", + "IOI_WW4B0_1", + "IOI_NE4BEG3_1", + "LIOI_ISIN11", + "IOI_SW4A3_1", + "IOI_SW4A1_0", + "IOI_ODELAY0_LDPIPEEN", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_EE4B3_1", + "IOI_NE4C0_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_IDELAYCTRL_OUTN65", + "IOI_BYP4_1", + "IOI_EE2BEG1_0", + "IOI_LOGIC_OUTS20_0", + "LIOI_T1", + "IOI_SE4C3_1", + "IOI_WL1END2_0", + "IOI_CTRL1_1", + "IOI_FAN5_0", + "IOI_EE2A2_0", + "IOI_WW4END2_1", + "IOI_WW4C0_0", + "IOI_IDELAY1_REGRST", + "IOI_PHASER_TO_IO_OCLK", + "IOI_SW4A0_1", + "IOI_IDELAY1_CNTVALUEIN0", + "LIOI_I1", + "IOI_OLOGIC0_CLKDIV", + "LIOI_I0", + "IOI_IMUX17_0", + "LIOI_ISIN20", + "IOI_WW2END2_0", + "IOI_FAN3_0", + "IOI_LOGIC_OUTS14_0", + "IOI_DCI_TSTCLK", + "IOI_FAN0_0", + "IOI_ODELAY1_CINVCTRL", + "IOI_SE4BEG0_0", + "IOI_IMUX20_1", + "IOI_EE2BEG3_0", + "IOI_LH7_0", + "IOI_IMUX15_1", + "IOI_ILOGIC0_Q3", + "IOI_EE4A1_0", + "IOI_ILOGIC1_Q8", + "LIOI_PU_INT_EN_0", + "IOI_IDELAY1_C", + "IOI_BYP7_0", + "IOI_IMUX25_0", + "IOI_IDELAY0_REGRST", + "IOI_BYP3_1", + "IOI_NE2A0_1", + "IOI_IMUX11_1", + "IOI_SE4BEG0_1", + "IOI_ILOGIC0_OCLKB", + "IOI_IMUX47_0", + "IOI_OLOGIC0_D4", + "IOI_SE2A0_0", + "IOI_SE4BEG1_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_SW4END3_0", + "IOI_EE4BEG3_0", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLKB", + "IOI_LOGIC_OUTS19_1", + "IOI_EL1BEG1_1", + "IOI_OLOGIC0_D3", + "IOI_EE4C0_0", + "IOI_TBYTEIN_TERM", + "IOI_OLOGIC0_TCE", + "IOI_WW2A0_0", + "LIOI3_IDELAY1_IFDLY0", + "LIOI_I2GCLK_TOP1", + "IOI_ODELAY0_CLKIN", + "IOI_DCI_TSTHLN", + "IOI_IMUX15_0", + "IOI_WW2END1_1", + "IOI_NE4C3_1", + "IOI_ILOGIC0_O", + "LIOI3_IDELAY0_IFDLY1", + "IOI_RCLK_DIV_CE3", + "IOI_BLOCK_OUTS0_0", + "IOI_SE4C3_0", + "IOI_ILOGIC1_CLKDIV", + "IOI_BYP0_1", + "IOI_IMUX32_0", + "IOI_OLOGIC1_D5", + "LIOI_ODELAY1_OFDLY1", + "IOI_LH4_0", + "IOI_RCLK_DIV_CLR1", + "LIOI_ODELAY1_OFDLY2", + "LIOI_PD_INT_EN_1", + "IOI_IMUX10_0", + "IOI_NW2A0_1", + "IOI_ILOGIC0_REV", + "LIOI_ILOGIC1_DDLY", + "IOI_ODELAY0_CNTVALUEIN4", + "LIOI_IDELAY1_IDATAIN", + "IOI_LOGIC_OUTS1_1", + "IOI_OLOGIC0_T1", + "IOI_EE4BEG1_0", + "IOI_IMUX41_0", + "IOI_WW4C3_0", + "IOI_LOGIC_OUTS23_0", + "IOI_RCLK_DIV_CE0", + "LIOI3_IDELAY0_IFDLY0", + "IOI_SW2A3_1", + "IOI_EE4B3_0", + "IOI_IOCLK0", + "IOI_EE4BEG0_0", + "IOI_ODELAY0_INC", + "IOI_IMUX6_0", + "LIOI_ODELAY1_ODATAIN", + "LIOI_ILOGIC1_D", + "IOI_IMUX10_1", + "IOI_IMUX40_0", + "IOI_WR1END3_0", + "IOI_IMUX37_1", + "IOI_OLOGIC0_REV", + "IOI_OLOGIC0_D1", + "IOI_IOCLK1", + "IOI_RCLK_FORIO1", + "IOI_ODELAY1_LD", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_WW4A1_1", + "IOI_NE4C0_0", + "LIOI_ISOUT10", + "IOI_NW4A2_1", + "LIOI_DCI_T_TERM0", + "IOI_LOGIC_OUTS6_1", + "LIOI_I2GCLK_TOP0", + "IOI_LH3_1", + "IOI_IMUX33_0", + "IOI_IMUX13_0", + "IOI_IMUX9_0", + "IOI_EE4BEG0_1", + "IOI_WW2A2_1", + "IOI_WR1END0_1", + "IOI_OLOGIC0_T3", + "IOI_EE4A2_0", + "IOI_IMUX26_0", + "IOI_IMUX0_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX3_0", + "IOI_EE4B2_0", + "IOI_SW2A2_1", + "LIOI_IBUF_DISABLE0", + "IOI_OLOGIC0_OCE", + "IOI_ILOGIC0_CE1", + "LIOI_OSIN11", + "LIOI_ILOGIC0_OFB", + "IOI_LOGIC_OUTS8_0", + "IOI_SE2A2_1", + "IOI_WW2END0_0", + "LIOI_IDELAY0_IDATAIN", + "IOI_SW2A1_0", + "IOI_RCLK_FORIO2", + "IOI_LH3_0", + "IOI_EE4B1_0", + "LIOI_ILOGIC0_D", + "IOI_SW4END1_0", + "IOI_WW4A2_0", + "IOI_ER1BEG3_0", + "IOI_LH6_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_IMUX40_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IMUX2_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_BYP1_1", + "IOI_SW4END1_1", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_IDELAYCTRL_RDY", + "IOI_ODELAY1_CNTVALUEOUT0", + "LIOI_OSOUT11", + "IOI_IMUX44_0", + "IOI_NW2A2_0", + "IOI_OLOGIC1_D4", + "IOI_SW4A1_1", + "IOI_LOGIC_OUTS22_1", + "IOI_RCLK_DIV_CE3_1", + "LIOI_ISIN21", + "IOI_OLOGIC0_D6", + "IOI_IDELAY0_CINVCTRL", + "IOI_IMUX25_1", + "IOI_WW4END1_1", + "IOI_WW4END0_1", + "LIOI_OLOGIC0_CLKDIVF", + "IOI_SE4BEG2_0", + "IOI_LOGIC_OUTS16_0", + "IOI_NW4END3_0", + "IOI_NE4BEG2_0", + "IOI_DCI_DCIDONE", + "LIOI_DCI_T_TERM1", + "IOI_ILOGIC0_CLKDIVP", + "IOI_OLOGIC1_TBYTEIN", + "IOI_IMUX13_1", + "IOI_LOGIC_OUTS7_0", + "IOI_IMUX_RC1", + "IOI_CLK0_1", + "IOI_NE2A3_1", + "IOI_DCI_TSTRST0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_LEAF_GCLK2", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_IDELAY1_INC", + "IOI_OLOGIC1_OCE", + "IOI_LOGIC_OUTS13_0", + "IOI_CLK1_1", + "IOI_NE4C2_1", + "IOI_WW4B0_0", + "IOI_ODELAY1_CNTVALUEIN0", + "IOI_WL1END3_1", + "IOI_IMUX28_0", + "IOI_NW4END1_0", + "LIOI3_IDELAY0_IFDLY2", + "IOI_OLOGIC1_D7", + "IOI_LOGIC_OUTS11_0", + "IOI_IDELAY0_CNTVALUEIN0", + "IOI_IMUX18_1", + "IOI_WW4A0_1", + "IOI_OLOGIC0_D8", + "IOI_IMUX38_1", + "IOI_IMUX21_0", + "IOI_EE2BEG1_1", + "IOI_EE4B0_0", + "IOI_FAN4_0", + "IOI_IDELAYCTRL_RST", + "IOI_SW4A2_0", + "IOI_NW2A0_0", + "IOI_OCLKM_0", + "IOI_EE2BEG0_1", + "IOI_LOGIC_OUTS14_1", + "LIOI_OLOGIC0_OFB", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_ODELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_0", + "IOI_ILOGIC1_OCLK", + "IOI_IMUX17_1", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_SW4END3_1", + "IOI_ODELAY1_CLKIN", + "IOI_NE2A1_0", + "IOI_EE4A2_1", + "IOI_OCLKM_1", + "IOI_IMUX43_0", + "LIOI_I2GCLK_BOT1", + "IOI_LH8_1", + "IOI_RCLK_DIV_CE1", + "IOI_LOGIC_OUTS17_0", + "IOI_SE2A3_0", + "IOI_ILOGIC1_Q6", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LH9_0", + "IOI_OLOGIC0_D2", + "IOI_OLOGIC0_CLKDIVB", + "IOI_IMUX30_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_LOGIC_OUTS0_0", + "IOI_WW2A1_0", + "IOI_BYP7_1", + "IOI_SE4C1_0", + "IOI_IMUX39_1", + "IOI_OCLK_1", + "IOI_EL1BEG0_1", + "IOI_ILOGIC0_Q4", + "IOI_IMUX45_1", + "IOI_IMUX20_0", + "IOI_ODELAY1_REGRST", + "IOI_OLOGIC0_D5", + "IOI_ODELAY1_INC", + "IOI_ODELAY1_CNTVALUEIN3", + "IOI_WW2A0_1", + "IOI_NW2A1_0", + "IOI_WW2A2_0", + "IOI_EE2BEG3_1", + "IOI_ILOGIC0_Q8", + "IOI_IMUX24_0", + "IOI_OLOGIC0_T2", + "IOI_IDELAY0_LD", + "IOI_FAN5_1", + "LIOI_O1", + "IOI_OLOGIC1_T2", + "IOI_LOGIC_OUTS3_1", + "IOI_FAN3_1", + "IOI_BYP0_0", + "IOI_IMUX35_1", + "IOI_ILOGIC1_OCLKB", + "IOI_IMUX27_1", + "IOI_WW4END3_1", + "IOI_BLOCK_OUTS2_1", + "LIOI_OSOUT20", + "IOI_EE2BEG2_0", + "IOI_NE2A3_0", + "IOI_SE2A1_1", + "IOI_NE4BEG3_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_LH12_0", + "IOI_LH2_1", + "IOI_ER1BEG3_1", + "IOI_LH1_1", + "IOI_ILOGIC1_CE2", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_FAN4_1", + "IOI_IDELAY0_CE", + "LIOI_OSIN10", + "IOI_EE4C2_1", + "IOI_OLOGIC0_CLK", + "IOI_LOGIC_OUTS12_1", + "IOI_SW2A3_0", + "LIOI_IBUF0", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_ODELAY1_CNTVALUEIN2", + "LIOI_OLOGIC1_TFB_LOCAL", + "IOI_SW2A1_1", + "LIOI_OLOGIC0_TFB_LOCAL", + "IOI_LH1_0", + "IOI_FAN1_1", + "LIOI_OSOUT21", + "LIOI3_IDELAY1_IFDLY2", + "IOI_LOGIC_OUTS10_1", + "IOI_LOGIC_OUTS22_0", + "IOI_IMUX34_1", + "IOI_WW4A1_0", + "IOI_FAN7_0", + "IOI_IDELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OCLK_0", + "IOI_ODELAY0_REGRST", + "IOI_LOGIC_OUTS15_0", + "IOI_LEAF_GCLK0", + "LIOI_ILOGIC1_OFB", + "IOI_EE2A0_1", + "IOI_IMUX12_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_IMUX23_1", + "IOI_ODELAY0_CNTVALUEIN2", + "IOI_LOGIC_OUTS15_1", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_EL1BEG3_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IMUX39_0", + "IOI_WR1END0_0", + "IOI_ODELAY1_CNTVALUEIN4", + "IOI_IMUX19_0", + "IOI_RCLK_FORIO3", + "IOI_BYP1_0", + "IOI_ILOGIC0_Q2", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_NW2A3_1", + "IOI_IDELAY0_C", + "IOI_NW2A2_1", + "IOI_SW4END2_0", + "IOI_SW4END0_0", + "IOI_IMUX32_1", + "IOI_IMUX19_1", + "IOI_SW2A0_0", + "IOI_IMUX46_0", + "IOI_WR1END1_0", + "IOI_LOGIC_OUTS19_0", + "IOI_LOGIC_OUTS1_0", + "IOI_IMUX8_0", + "IOI_WW4C2_1", + "LIOI_ISOUT20", + "LIOI_OLOGIC1_OFB", + "IOI_WW2END3_1", + "IOI_WW4C3_1", + "IOI_LH5_1", + "IOI_ODELAY1_CE", + "IOI_ILOGIC1_CLKDIVP", + "IOI_OLOGIC0_T4", + "IOI_NE4C2_0", + "IOI_IMUX31_1", + "IOI_NE4C3_0", + "IOI_NW4END2_1", + "IOI_IMUX7_1", + "IOI_IDELAY1_LD", + "IOI_LOGIC_OUTS23_1", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_LOGIC_OUTS9_0", + "IOI_EE2A0_0", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_WW4A3_1", + "IOI_IMUX9_1", + "IOI_NW2A1_1", + "IOI_IMUX1_0", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS9_1", + "IOI_IMUX42_1", + "IOI_RCLK_DIV_CLR3", + "IOI_IMUX21_1", + "IOI_EE2BEG0_0", + "IOI_IMUX1_1", + "IOI_OLOGIC1_T4", + "IOI_LH7_1", + "IOI_ILOGIC1_O", + "IOI_LOGIC_OUTS0_1", + "LIOI_IDELAY1_DATAOUT", + "LIOI_ODELAY0_OFDLY2", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_LOGIC_OUTS2_0", + "IOI_FAN0_1", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_ILOGIC0_OCLK", + "IOI_IMUX30_0", + "IOI_SE4C1_1", + "IOI_NE4BEG0_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LOGIC_OUTS4_1", + "LIOI_ISIN10", + "IOI_WL1END2_1", + "IOI_LEAF_GCLK5", + "IOI_IMUX43_1", + "LIOI_ODELAY1_DATAOUT", + "LIOI_OLOGIC1_TQ", + "LIOI_ISOUT11", + "IOI_EE2BEG2_1", + "IOI_NW4A2_0", + "IOI_ER1BEG1_1", + "IOI_NW4END0_0", + "IOI_BYP5_0", + "IOI_ILOGIC1_Q3", + "IOI_LH4_1", + "IOI_IMUX37_0", + "IOI_IDELAY1_DATAIN", + "IOI_IMUX_RC3", + "IOI_ILOGIC0_CLKB", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IDELAY1_CNTVALUEIN3", + "IOI_IDELAY1_CNTVALUEIN2", + "IOI_IMUX16_0", + "LIOI_O0", + "IOI_SW4A2_1", + "IOI_WW4END0_0", + "IOI_BLOCK_OUTS2_0", + "IOI_EE4BEG2_1", + "LIOI_ODELAY0_OFDLY0", + "IOI_NW2A3_0", + "IOI_IMUX_RC0", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WR1END3_1", + "IOI_NW4END1_1", + "LIOI_OSOUT10", + "IOI_SE2A2_0", + "LIOI_OLOGIC0_OQ", + "IOI_ILOGIC0_Q6", + "IOI_NW4A3_1", + "IOI_EE4B2_1", + "IOI_SE4BEG3_0", + "LIOI_OSIN20", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_IMUX36_0", + "IOI_LOGIC_OUTS5_0", + "IOI_LH8_0", + "IOI_IMUX12_0", + "IOI_EE4C3_0", + "IOI_ODELAY1_CNTVALUEOUT2", + "IOI_SW4END0_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_OLOGIC1_CLKDIVFB", + "IOI_IMUX0_1", + "IOI_CLK1_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_OLOGIC0_D7", + "IOI_BLOCK_OUTS3_1", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_WW4END3_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_OLOGIC1_D6", + "IOI_IMUX29_0", + "IOI_LOGIC_OUTS18_0", + "IOI_WL1END1_0", + "IOI_LH6_1", + "IOI_EL1BEG0_0", + "IOI_ILOGIC1_Q2", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_LEAF_GCLK1", + "IOI_EE2A1_0", + "IOI_WW4B1_0", + "IOI_DCI_TSTHLP", + "IOI_EE4A0_0", + "IOI_BYP3_0", + "IOI_FAN6_0", + "IOI_LOGIC_OUTS10_0", + "IOI_SE4BEG2_1", + "IOI_IMUX29_1", + "IOI_IDELAY0_LDPIPEEN", + "IOI_ILOGIC0_SR", + "IOI_WW4A0_0", + "IOI_NE4BEG2_1", + "IOI_IDELAY1_CE", + "IOI_WL1END0_0", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IDELAY0_INC", + "IOI_SE4C0_1", + "IOI_OLOGIC1_T3", + "IOI_LH10_0", + "IOI_EE4A3_0", + "LIOI_OLOGIC1_OQ", + "IOI_ILOGIC1_CE1", + "IOI_FAN7_1", + "IOI_WW4B3_0", + "LIOI_PD_INT_EN_0", + "LIOI_T0", + "IOI_WL1END0_1", + "IOI_IMUX45_0", + "IOI_ODELAY1_C", + "IOI_LH12_1", + "IOI_WW2END3_0", + "IOI_WR1END2_0", + "IOI_IMUX11_0", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_NE2A0_0", + "IOI_NW4END0_1", + "IOI_WW4A2_1", + "IOI_EL1BEG3_1", + "LIOI_PU_INT_EN_1", + "IOI_EE2A3_1", + "LIOI_ILOGIC0_DDLY", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_WR1END2_1", + "IOI_ODELAY0_LD", + "IOI_MONITOR_P", + "IOI_EE4BEG3_1", + "IOI_WW2END0_1", + "IOI_OLOGIC0_CLKB", + "IOI_RCLK_DIV_CE2", + "IOI_OLOGIC1_D2", + "IOI_LH11_1", + "IOI_IMUX34_0", + "IOI_LH9_1", + "IOI_BYP6_0", + "IOI_ILOGIC1_BITSLIP", + "LIOI_ILOGIC1_TFB", + "IOI_SE4BEG3_1", + "IOI_WW4B2_1", + "IOI_ODELAY1_CNTVALUEOUT4", + "IOI_IMUX14_0", + "LIOI_ILOGIC0_TFB", + "LIOI_OLOGIC0_TFB", + "IOI_LOGIC_OUTS12_0", + "IOI_NW4A3_0", + "IOI_SE4C0_0", + "IOI_NE2A1_1", + "IOI_LOGIC_OUTS20_1", + "IOI_SW4A3_0", + "IOI_SE4C2_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_BLOCK_OUTS1_1", + "IOI_EE4A0_1", + "IOI_WL1END3_0", + "IOI_WW2A3_0", + "IOI_CLK0_0", + "LIOI_DIFF_TERM_INT_EN", + "IOI_NE4BEG1_0", + "IOI_OLOGIC1_TCE", + "IOI_OLOGIC1_D3", + "IOI_LOGIC_OUTS6_0", + "IOI_IMUX2_1", + "LIOI_IDELAY0_DATAOUT", + "IOI_ODELAY1_CNTVALUEOUT1", + "IOI_IMUX44_1", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE4A3_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX5_1", + "IOI_EE2A1_1", + "IOI_WW4B3_1", + "IOI_ILOGIC1_Q4", + "LIOI_ODELAY1_OFDLY0", + "IOI_WW2A1_1", + "IOI_INT_DCI_EN", + "IOI_IMUX47_1", + "IOI_IMUX3_1", + "IOI_IMUX6_1", + "LIOI_ODELAY0_OFDLY1", + "IOI_NE2A2_0", + "IOI_WW4B2_0", + "IOI_FAN6_1", + "IOI_BLOCK_OUTS3_0", + "IOI_IDELAY0_DATAIN", + "IOI_EE4B0_1", + "IOI_LOGIC_OUTS13_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_LH11_0", + "IOI_LH10_1", + "IOI_NW4A0_0", + "IOI_BYP2_1", + "IOI_LOGIC_OUTS5_1", + "IOI_NW4END2_0", + "IOI_WW4C1_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WR1END1_1", + "IOI_LOGIC_OUTS16_1", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC1_CLK", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_IMUX7_0", + "IOI_FAN1_0", + "IOI_IMUX41_1", + "IOI_WW2A3_1", + "IOI_SE2A3_1", + "LIOI_ODELAY0_ODATAIN", + "IOI_LOGIC_OUTS2_1", + "IOI_CTRL1_0", + "IOI_RCLK_FORIO0", + "IOI_IMUX8_1", + "IOI_SW4A0_0", + "IOI_BLOCK_OUTS1_0", + "IOI_WW4A3_0", + "IOI_ER1BEG0_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_RCLK_DIV_CLR1_1", + "LIOI_KEEPER_INT_EN_0", + "IOI_RCLK_DIV_CLR2", + "IOI_NW4A1_1", + "IOI_EL1BEG1_0", + "LIOI_ODELAY0_DATAOUT", + "LIOI_OLOGIC1_CLKDIVF", + "IOI_FAN2_0", + "IOI_CTRL0_0", + "IOI_ILOGIC1_Q5", + "IOI_SE4BEG1_0", + "IOI_OLOGIC0_SR", + "IOI_ODELAY1_LDPIPEEN", + "IOI_LH2_0", + "IOI_EE4C3_1", + "IOI_ODELAY0_CE", + "IOI_EE2A3_0", + "IOI_OLOGIC1_D1", + "IOI_NW4A0_1", + "IOI_LOGIC_OUTS3_0", + "IOI_EE4C0_1", + "IOI_ILOGIC1_CLK", + "IOI_SW4END2_1", + "IOI_WW4C2_0", + "IOI_IMUX33_1", + "IOI_WW2END1_0", + "LIOI_KEEPER_INT_EN_1", + "LIOI_OLOGIC0_TQ", + "IOI_SE2A0_1", + "IOI_LOGIC_OUTS8_1", + "IOI_LH5_0", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_ILOGIC0_Q1", + "IOI_OLOGIC1_CLKDIVB", + "IOI_NE4C1_1", + "IOI_NE4BEG0_1", + "IOI_OLOGIC1_SR", + "IOI_EE4B1_1", + "IOI_IMUX14_1", + "IOI_ODELAY0_C", + "IOI_IMUX35_0", + "IOI_RCLK_DIV_CLR0", + "IOI_ILOGIC1_SR", + "LIOI_IBUF_DISABLE1", + "IOI_NE4BEG1_1", + "IOI_BYP6_1", + "IOI_ER1BEG2_1", + "IOI_IMUX4_0", + "IOI_EE4BEG2_0", + "IOI_LOGIC_OUTS4_0", + "IOI_NE2A2_1", + "LIOI_IBUF1", + "IOI_LOGIC_OUTS7_1", + "IOI_IMUX24_1", + "IOI_IMUX18_0", + "IOI_NE4C1_0", + "IOI_EE4BEG1_1", + "IOI_BYP4_0", + "IOI_EE2A2_1", + "IOI_ER1BEG1_0", + "IOI_WL1END1_1", + "IOI_IMUX31_0", + "IOI_ER1BEG2_0", + "IOI_IMUX28_1", + "IOI_WW4C0_1", + "IOI_SE4C2_0", + "IOI_LOGIC_OUTS17_1", + "IOI_ODELAY0_CNTVALUEIN0", + "LIOI_OLOGIC1_TFB", + "IOI_IMUX_RC2", + "IOI_WW4END2_0" + ], + "tile_type": "LIOI3_TBYTETERM", + "sites": [ + { + "site_pins": { + "T2": "IOI_OLOGIC1_T2", + "D5": "IOI_OLOGIC1_D5", + "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", + "D8": "IOI_OLOGIC1_D8", + "SR": "IOI_OLOGIC1_SR", + "SHIFTOUT1": "LIOI_OSOUT11", + "T4": "IOI_OLOGIC1_T4", + "SHIFTIN1": null, + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "OCE": "IOI_OLOGIC1_OCE", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "CLKB": "IOI_OLOGIC1_CLKB", + "OQ": "LIOI_OLOGIC1_OQ", + "D3": "IOI_OLOGIC1_D3", + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "SHIFTIN2": null, + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "D1": "IOI_OLOGIC1_D1", + "CLK": "IOI_OLOGIC1_CLK", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "T1": "IOI_OLOGIC1_T1", + "D4": "IOI_OLOGIC1_D4", + "TCE": "IOI_OLOGIC1_TCE", + "D2": "IOI_OLOGIC1_D2", + "SHIFTOUT2": "LIOI_OSOUT21", + "OFB": "LIOI_OLOGIC1_OFB", + "TFB": "LIOI_OLOGIC1_TFB", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "T3": "IOI_OLOGIC1_T3", + "D6": "IOI_OLOGIC1_D6", + "TQ": "LIOI_OLOGIC1_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "CLK": "IOI_ILOGIC1_CLK", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "Q3": "IOI_ILOGIC1_Q3", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "D": "LIOI_ILOGIC1_D", + "SR": "IOI_ILOGIC1_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC1_CE1", + "Q8": "IOI_ILOGIC1_Q8", + "SHIFTIN2": "LIOI_ISIN21", + "Q2": "IOI_ILOGIC1_Q2", + "CE2": "IOI_ILOGIC1_CE2", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "SHIFTOUT2": "LIOI_ISOUT21", + "O": "IOI_ILOGIC1_O", + "OFB": "LIOI_ILOGIC1_OFB", + "TFB": "LIOI_ILOGIC1_TFB", + "Q4": "IOI_ILOGIC1_Q4", + "CLKB": "IOI_ILOGIC1_CLKB", + "Q1": "IOI_ILOGIC1_Q1", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN1": "LIOI_ISIN11", + "Q6": "IOI_ILOGIC1_Q6", + "DDLY": "LIOI_ILOGIC1_DDLY", + "SHIFTOUT1": "LIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC1_Q7", + "OCLKB": "IOI_ILOGIC1_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "T2": "IOI_OLOGIC0_T2", + "D5": "IOI_OLOGIC0_D5", + "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", + "D8": "IOI_OLOGIC0_D8", + "SR": "IOI_OLOGIC0_SR", + "SHIFTOUT1": "LIOI_OSOUT10", + "T4": "IOI_OLOGIC0_T4", + "SHIFTIN1": "LIOI_OSIN10", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "OCE": "IOI_OLOGIC0_OCE", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "CLKB": "IOI_OLOGIC0_CLKB", + "OQ": "LIOI_OLOGIC0_OQ", + "D3": "IOI_OLOGIC0_D3", + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "SHIFTIN2": "LIOI_OSIN20", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "D1": "IOI_OLOGIC0_D1", + "CLK": "IOI_OLOGIC0_CLK", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "T1": "IOI_OLOGIC0_T1", + "D4": "IOI_OLOGIC0_D4", + "TCE": "IOI_OLOGIC0_TCE", + "D2": "IOI_OLOGIC0_D2", + "SHIFTOUT2": "LIOI_OSOUT20", + "OFB": "LIOI_OLOGIC0_OFB", + "TFB": "LIOI_OLOGIC0_TFB", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "T3": "IOI_OLOGIC0_T3", + "D6": "IOI_OLOGIC0_D6", + "TQ": "LIOI_OLOGIC0_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "CLK": "IOI_ILOGIC0_CLK", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "Q3": "IOI_ILOGIC0_Q3", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "D": "LIOI_ILOGIC0_D", + "SR": "IOI_ILOGIC0_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC0_CE1", + "Q8": "IOI_ILOGIC0_Q8", + "SHIFTIN2": null, + "Q2": "IOI_ILOGIC0_Q2", + "CE2": "IOI_ILOGIC0_CE2", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "SHIFTOUT2": "LIOI_ISOUT20", + "O": "IOI_ILOGIC0_O", + "OFB": "LIOI_ILOGIC0_OFB", + "TFB": "LIOI_ILOGIC0_TFB", + "Q4": "IOI_ILOGIC0_Q4", + "CLKB": "IOI_ILOGIC0_CLKB", + "Q1": "IOI_ILOGIC0_Q1", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN1": null, + "Q6": "IOI_ILOGIC0_Q6", + "DDLY": "LIOI_ILOGIC0_DDLY", + "SHIFTOUT1": "LIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC0_Q7", + "OCLKB": "IOI_ILOGIC0_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "IFDLY0": "LIOI3_IDELAY1_IFDLY0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", + "LD": "IOI_IDELAY1_LD", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "IDATAIN": "LIOI_IDELAY1_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "IFDLY2": "LIOI3_IDELAY1_IFDLY2", + "C": "IOI_IDELAY1_C", + "IFDLY1": "LIOI3_IDELAY1_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "DATAOUT": "LIOI_IDELAY1_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "IFDLY0": "LIOI3_IDELAY0_IFDLY0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", + "LD": "IOI_IDELAY0_LD", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "IDATAIN": "LIOI_IDELAY0_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "IFDLY2": "LIOI3_IDELAY0_IFDLY2", + "C": "IOI_IDELAY0_C", + "IFDLY1": "LIOI3_IDELAY0_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "DATAOUT": "LIOI_IDELAY0_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_L_TERM_INT.json b/artix7/tile_type_L_TERM_INT.json index 780e58a..336291a 100644 --- a/artix7/tile_type_L_TERM_INT.json +++ b/artix7/tile_type_L_TERM_INT.json @@ -1,173 +1,173 @@ { - "wires": [ - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "TERM_INT_IMUX5", - "TERM_INT_IMUX46", - "TERM_INT_IMUX28", - "TERM_INT_LOGIC_OUTS_L_B6", - "L_TERM_INT_WR1BEG3", - "L_TERM_INT_NW4BEG3", - "TERM_INT_FAN1", - "L_TERM_INT_WW4BEG1", - "TERM_INT_IMUX6", - "TERM_INT_IMUX19", - "TERM_INT_LOGIC_OUTS_L_B9", - "L_TERM_INT_WW4C2", - "L_TERM_INT_WW2BEG3", - "L_TERM_INT_NW4C1", - "TERM_INT_BYP4", - "TERM_INT_MONITOR_P", - "TERM_INT_IMUX26", - "TERM_INT_BYP2", - "TERM_INT_FAN0", - "L_TERM_INT_WW4A2", - "TERM_INT_LOGIC_OUTS_L_B15", - "L_TERM_INT_WW2A3", - "TERM_INT_BLOCK_OUTS_L_B2", - "L_TERM_INT_NW2BEG3", - "L_TERM_INT_NW4BEG2", - "TERM_INT_IMUX17", - "TERM_INT_IMUX45", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "L_TERM_INT_WW4C1", - "TERM_INT_IMUX39", - "TERM_INT_IMUX0", - "TERM_INT_IMUX31", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV", - "TERM_INT_CTRL0", - "L_TERM_INT_WW4A3", - "TERM_INT_IMUX35", - "TERM_INT_IMUX43", - "TERM_INT_IMUX10", - "TERM_INT_FAN6", - "TERM_INT_LOGIC_OUTS_L_B22", - "L_TERM_INT_WW2BEG0", - "L_TERM_INT_WL1BEG1", - "TERM_INT_LOGIC_OUTS_L_B11", - "TERM_INT_BYP6", - "TERM_INT_LOGIC_OUTS_L_B12", - "TERM_INT_CLK0", - "TERM_INT_MONITOR_N", - "L_TERM_INT_WW4B2", - "L_TERM_INT_LH0", - "TERM_INT_LOGIC_OUTS_L_B3", - "TERM_INT_IMUX20", - "TERM_INT_IMUX33", - "TERM_INT_IMUX40", - "L_TERM_INT_WW4BEG0", - "TERM_INT_LOGIC_OUTS_L_B0", - "TERM_INT_LOGIC_OUTS_L_B1", - "L_TERM_INT_WW4A0", - "TERM_INT_FAN5", - "TERM_INT_LOGIC_OUTS_L_B16", - "TERM_INT_IMUX22", - "TERM_INT_BYP5", - "L_TERM_INT_WW4BEG2", - "TERM_INT_IMUX30", - "TERM_INT_IMUX11", - "TERM_INT_IMUX2", - "TERM_INT_LOGIC_OUTS_L_B14", - "TERM_INT_BLOCK_OUTS_L_B3", - "TERM_INT_IMUX42", - "TERM_INT_IMUX15", - "TERM_INT_IMUX27", - "L_TERM_INT_NW4BEG0", - "TERM_INT_IMUX44", - "L_TERM_INT_SW2BEG0", - "L_TERM_INT_SW4BEG1", - "TERM_INT_IMUX23", - "L_TERM_INT_SW4BEG2", - "L_TERM_INT_WL1BEG0", - "L_TERM_INT_NW2BEG0", - "TERM_INT_LOGIC_OUTS_L_B13", - "L_TERM_INT_SW2BEG3", - "TERM_INT_LOGIC_OUTS_L_B21", - "L_TERM_INT_LH4", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "TERM_INT_CLK1", - "TERM_INT_IMUX24", - "TERM_INT_IMUX14", - "TERM_INT_LOGIC_OUTS_L_B4", - "L_TERM_INT_SW4BEG3", - "TERM_INT_IMUX1", - "L_TERM_INT_WR1BEG1", - "TERM_INT_LOGIC_OUTS_L_B19", - "L_TERM_INT_WW2A2", - "TERM_INT_LOGIC_OUTS_L_B23", - "L_TERM_INT_LH2", - "TERM_INT_IMUX3", - "L_TERM_INT_WW4C3", - "L_TERM_INT_NW2BEG1", - "TERM_INT_FAN7", - "TERM_INT_BYP7", - "TERM_INT_FAN4", - "L_TERM_INT_NW4C2", - "TERM_INT_IMUX38", - "L_TERM_INT_DQS_IOTOPHASER", - "TERM_INT_LOGIC_OUTS_L_B17", - "L_TERM_INT_WW4B0", - "L_TERM_INT_WW4A1", - "TERM_INT_LOGIC_OUTS_L_B5", - "L_TERM_INT_LH5", - "TERM_INT_BYP1", - "TERM_INT_IMUX13", - "L_TERM_INT_SW4C1", - "TERM_INT_IMUX7", - "L_TERM_INT_WW2A1", - "TERM_INT_LOGIC_OUTS_L_B10", - "TERM_INT_BYP3", - "L_TERM_INT_WR1BEG0", - "TERM_INT_IMUX12", - "TERM_INT_BYP0", - "TERM_INT_LOGIC_OUTS_L_B8", - "L_TERM_INT_LH1", - "L_TERM_INT_WW2A0", - "L_TERM_INT_NW4C0", - "L_TERM_INT_NW4BEG1", - "TERM_INT_BLOCK_OUTS_L_B1", - "L_TERM_INT_SW4C2", - "L_TERM_INT_WW4BEG3", - "TERM_INT_LOGIC_OUTS_L_B2", - "TERM_INT_IMUX47", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", - "TERM_INT_IMUX18", - "TERM_INT_IMUX32", - "TERM_INT_CTRL1", - "TERM_INT_BLOCK_OUTS_L_B0", - "L_TERM_INT_WW4B1", - "TERM_INT_LOGIC_OUTS_L_B20", - "TERM_INT_IMUX37", - "TERM_INT_IMUX36", - "L_TERM_INT_WW4B3", - "TERM_INT_IMUX4", - "TERM_INT_FAN3", - "TERM_INT_IMUX9", - "L_TERM_INT_SW4C0", - "L_TERM_INT_WR1BEG2", - "L_TERM_INT_WW4C0", - "TERM_INT_IMUX41", - "L_TERM_INT_SW4BEG0", - "L_TERM_INT_WL1BEG2", - "L_TERM_INT_SW2BEG2", - "TERM_INT_IMUX8", - "L_TERM_INT_WW2BEG1", - "TERM_INT_IMUX21", - "L_TERM_INT_WL1BEG3", - "TERM_INT_LOGIC_OUTS_L_B18", - "TERM_INT_IMUX34", - "L_TERM_INT_SW2BEG1", - "L_TERM_INT_SW4C3", - "TERM_INT_IMUX25", - "L_TERM_INT_NW2BEG2", - "TERM_INT_IMUX16", - "TERM_INT_IMUX29", - "TERM_INT_FAN2", - "TERM_INT_LOGIC_OUTS_L_B7", - "L_TERM_INT_WW2BEG2", - "L_TERM_INT_LH3", - "L_TERM_INT_NW4C3" - ], - "sites": [], "pips": {}, - "tile_type": "L_TERM_INT" + "wires": [ + "TERM_INT_BYP0", + "L_TERM_INT_WW4A3", + "TERM_INT_IMUX8", + "L_TERM_INT_NW2BEG1", + "TERM_INT_IMUX27", + "L_TERM_INT_WL1BEG0", + "L_TERM_INT_NW4C1", + "TERM_INT_LOGIC_OUTS_L_B14", + "TERM_INT_IMUX17", + "L_TERM_INT_WW4C2", + "TERM_INT_LOGIC_OUTS_L_B9", + "L_TERM_INT_LH0", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "L_TERM_INT_SW2BEG1", + "L_TERM_INT_WW4B3", + "L_TERM_INT_WW4BEG0", + "L_TERM_INT_SW2BEG0", + "TERM_INT_CLK0", + "L_TERM_INT_NW4BEG0", + "TERM_INT_IMUX30", + "L_TERM_INT_NW4C2", + "L_TERM_INT_SW4BEG1", + "TERM_INT_IMUX35", + "TERM_INT_LOGIC_OUTS_L_B15", + "TERM_INT_LOGIC_OUTS_L_B16", + "TERM_INT_IMUX38", + "TERM_INT_IMUX6", + "TERM_INT_IMUX36", + "TERM_INT_CTRL1", + "TERM_INT_FAN5", + "L_TERM_INT_SW4BEG3", + "L_TERM_INT_WW2BEG1", + "L_TERM_INT_WW2BEG3", + "TERM_INT_IMUX26", + "TERM_INT_LOGIC_OUTS_L_B20", + "L_TERM_INT_LH1", + "L_TERM_INT_LH3", + "L_TERM_INT_WW2A1", + "L_TERM_INT_WW2A2", + "TERM_INT_LOGIC_OUTS_L_B1", + "L_TERM_INT_WW4BEG2", + "L_TERM_INT_WW4B0", + "L_TERM_INT_WL1BEG3", + "TERM_INT_IMUX13", + "TERM_INT_BYP5", + "TERM_INT_BLOCK_OUTS_L_B2", + "TERM_INT_IMUX42", + "TERM_INT_IMUX19", + "TERM_INT_IMUX3", + "TERM_INT_BYP3", + "TERM_INT_IMUX2", + "TERM_INT_FAN6", + "TERM_INT_FAN3", + "TERM_INT_LOGIC_OUTS_L_B12", + "TERM_INT_LOGIC_OUTS_L_B11", + "TERM_INT_LOGIC_OUTS_L_B3", + "L_TERM_INT_NW2BEG0", + "L_TERM_INT_WW4B1", + "TERM_INT_BLOCK_OUTS_L_B3", + "L_TERM_INT_WL1BEG2", + "L_TERM_INT_WW2BEG2", + "L_TERM_INT_WW2BEG0", + "L_TERM_INT_SW4BEG0", + "L_TERM_INT_NW2BEG2", + "L_TERM_INT_WW4C0", + "TERM_INT_BYP6", + "L_TERM_INT_LH4", + "TERM_INT_IMUX1", + "TERM_INT_IMUX12", + "TERM_INT_IMUX10", + "TERM_INT_BLOCK_OUTS_L_B1", + "L_TERM_INT_WW4B2", + "TERM_INT_IMUX23", + "L_TERM_INT_WW2A0", + "L_TERM_INT_SW4C2", + "TERM_INT_IMUX14", + "TERM_INT_CLK1", + "TERM_INT_IMUX25", + "TERM_INT_LOGIC_OUTS_L_B0", + "TERM_INT_BYP1", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "TERM_INT_IMUX22", + "TERM_INT_FAN7", + "TERM_INT_MONITOR_N", + "TERM_INT_IMUX4", + "L_TERM_INT_SW4BEG2", + "TERM_INT_LOGIC_OUTS_L_B10", + "TERM_INT_IMUX45", + "L_TERM_INT_WR1BEG0", + "L_TERM_INT_NW2BEG3", + "TERM_INT_FAN1", + "L_TERM_INT_WW2A3", + "TERM_INT_FAN0", + "L_TERM_INT_NW4C0", + "TERM_INT_IMUX29", + "TERM_INT_IMUX5", + "L_TERM_INT_WW4A1", + "TERM_INT_IMUX41", + "L_TERM_INT_PHASER_TO_IO_OCLK", + "TERM_INT_BLOCK_OUTS_L_B0", + "L_TERM_INT_WR1BEG3", + "TERM_INT_IMUX46", + "TERM_INT_LOGIC_OUTS_L_B21", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", + "L_TERM_INT_SW4C1", + "TERM_INT_IMUX16", + "TERM_INT_BYP4", + "L_TERM_INT_WW4A2", + "L_TERM_INT_SW4C3", + "TERM_INT_IMUX37", + "TERM_INT_IMUX32", + "L_TERM_INT_WW4C3", + "TERM_INT_IMUX28", + "TERM_INT_IMUX15", + "TERM_INT_FAN4", + "TERM_INT_IMUX44", + "L_TERM_INT_SW2BEG3", + "TERM_INT_IMUX47", + "TERM_INT_LOGIC_OUTS_L_B6", + "TERM_INT_IMUX20", + "TERM_INT_IMUX40", + "L_TERM_INT_SW4C0", + "L_TERM_INT_DQS_IOTOPHASER", + "L_TERM_INT_LH5", + "TERM_INT_IMUX43", + "TERM_INT_LOGIC_OUTS_L_B19", + "TERM_INT_IMUX39", + "L_TERM_INT_SW2BEG2", + "TERM_INT_IMUX33", + "TERM_INT_LOGIC_OUTS_L_B8", + "TERM_INT_IMUX18", + "TERM_INT_MONITOR_P", + "TERM_INT_IMUX24", + "L_TERM_INT_WW4BEG1", + "TERM_INT_IMUX9", + "L_TERM_INT_WW4A0", + "L_TERM_INT_WR1BEG2", + "TERM_INT_BYP2", + "TERM_INT_IMUX0", + "TERM_INT_LOGIC_OUTS_L_B7", + "TERM_INT_LOGIC_OUTS_L_B17", + "TERM_INT_LOGIC_OUTS_L_B23", + "L_TERM_INT_WW4BEG3", + "TERM_INT_CTRL0", + "TERM_INT_LOGIC_OUTS_L_B13", + "TERM_INT_LOGIC_OUTS_L_B5", + "L_TERM_INT_WW4C1", + "L_TERM_INT_WR1BEG1", + "TERM_INT_IMUX21", + "TERM_INT_BYP7", + "L_TERM_INT_NW4BEG3", + "TERM_INT_IMUX11", + "TERM_INT_IMUX34", + "TERM_INT_FAN2", + "TERM_INT_IMUX7", + "TERM_INT_LOGIC_OUTS_L_B18", + "TERM_INT_LOGIC_OUTS_L_B4", + "L_TERM_INT_LH2", + "L_TERM_INT_NW4BEG1", + "L_TERM_INT_WL1BEG1", + "L_TERM_INT_NW4C3", + "TERM_INT_LOGIC_OUTS_L_B22", + "TERM_INT_LOGIC_OUTS_L_B2", + "TERM_INT_IMUX31", + "L_TERM_INT_PHASER_TO_IO_ICLK", + "L_TERM_INT_NW4BEG2" + ], + "tile_type": "L_TERM_INT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_MONITOR_BOT.json b/artix7/tile_type_MONITOR_BOT.json index 8013c74..f06b289 100644 --- a/artix7/tile_type_MONITOR_BOT.json +++ b/artix7/tile_type_MONITOR_BOT.json @@ -1,3543 +1,3543 @@ { - "wires": [ - "MONITOR_EE4BEG2_8", - "MONITOR_LOGIC_OUTS_B22_3", - "MONITOR_IMUX9_7", - "MONITOR_TESTADCOUT0", - "MONITOR_EE4B1_3", - "MONITOR_WW4B2_5", - "MONITOR_EE4BEG0_2", - "MONITOR_FAN0_6", - "MONITOR_LOGIC_OUTS_B16_2", - "MONITOR_WW4C2_3", - "MONITOR_NW4A0_4", - "MONITOR_HORIZ_VAUXN14", - "MONITOR_NW4A3_2", - "MONITOR_WW2END2_0", - "MONITOR_BLOCK_OUTS_B3_0", - "MONITOR_IMUX5_8", - "MONITOR_IMUX25_0", - "MONITOR_ER1BEG2_4", - "MONITOR_VERT_VAUXN14", - "MONITOR_IMUX38_5", - "MONITOR_NE2A1_8", - "MONITOR_SW4A3_6", - "MONITOR_LH3_5", - "MONITOR_LOGIC_OUTS_B17_6", - "MONITOR_SE4BEG0_5", - "MONITOR_TESTADCIN21", - "MONITOR_WW4C0_1", - "MONITOR_CLK1_0", - "MONITOR_LH12_0", - "MONITOR_VERT_VAUXP9", - "MONITOR_WW2A1_3", - "MONITOR_IMUX46_9", - "MONITOR_SE4BEG2_1", - "MONITOR_LOGIC_OUTS_B4_7", - "MONITOR_TESTDB8", - "MONITOR_IMUX43_6", - "MONITOR_IMUX23_0", - "MONITOR_DO14", - "MONITOR_TESTADCIN0", - "MONITOR_SE2A2_9", - "MONITOR_LOGIC_OUTS_B0_8", - "MONITOR_EE4B0_4", - "MONITOR_LH4_5", - "MONITOR_IMUX12_7", - "MONITOR_IMUX47_8", - "MONITOR_LH6_1", - "MONITOR_IMUX2_7", - "MONITOR_TESTADCIN11", - "MONITOR_EE4B2_1", - "MONITOR_BYP5_4", - "MONITOR_SW4A2_8", - "MONITOR_NW4END1_9", - "MONITOR_LOGIC_OUTS_B12_8", - "MONITOR_VAUXP11", - "MONITOR_EE4C3_6", - "MONITOR_LOGIC_OUTS_B5_1", - "MONITOR_MUXADDR0", - "MONITOR_NE4C0_8", - "MONITOR_IMUX18_0", - "MONITOR_IMUX3_2", - "MONITOR_NW4A1_2", - "MONITOR_WW2A2_5", - "MONITOR_LOGIC_OUTS_B11_9", - "MONITOR_BLOCK_OUTS_B1_3", - "MONITOR_NW2A0_6", - "MONITOR_WR1END0_8", - "MONITOR_FAN0_7", - "MONITOR_EL1BEG0_1", - "MONITOR_TESTRST", - "MONITOR_LOGIC_OUTS_B16_0", - "MONITOR_EE4BEG2_5", - "MONITOR_LOGIC_OUTS_B3_0", - "MONITOR_LOGIC_OUTS_B11_6", - "MONITOR_IMUX8_8", - "MONITOR_IMUX19_6", - "MONITOR_LOGIC_OUTS_B16_4", - "MONITOR_EE4B1_2", - "MONITOR_WW4B2_2", - "MONITOR_SW4END3_6", - "MONITOR_EE4A3_7", - "MONITOR_JTAGBUSY", - "MONITOR_SW4END1_2", - "MONITOR_WW4END3_8", - "MONITOR_IMUX10_8", - "MONITOR_IMUX30_0", - "MONITOR_EE2A1_5", - "MONITOR_NW4END0_9", - "MONITOR_NE4C2_1", - "MONITOR_SW4END2_5", - "MONITOR_IMUX0_4", - "MONITOR_WW4A1_6", - "MONITOR_EE4A3_3", - "MONITOR_WW4C0_6", - "MONITOR_TESTDB0", - "MONITOR_ER1BEG2_5", - "MONITOR_LH11_9", - "MONITOR_BYP2_7", - "MONITOR_IMUX6_5", - "MONITOR_WW4END3_4", - "MONITOR_LOGIC_OUTS_B19_2", - "MONITOR_WL1END2_0", - "MONITOR_TESTDB12", - "MONITOR_LOGIC_OUTS_B21_0", - "MONITOR_IMUX31_1", - "MONITOR_WR1END0_3", - "MONITOR_LH1_5", - "MONITOR_BYP0_3", - "MONITOR_IMUX24_2", - "MONITOR_LOGIC_OUTS_B20_2", - "MONITOR_ER1BEG1_4", - "MONITOR_LH1_9", - "MONITOR_BLOCK_OUTS_B1_7", - "MONITOR_WL1END1_6", - "MONITOR_EE4A0_0", - "MONITOR_FAN0_1", - "MONITOR_WL1END1_2", - "MONITOR_EE4C1_1", - "MONITOR_IMUX5_0", - "MONITOR_EE4BEG3_6", - "MONITOR_EL1BEG1_6", - "MONITOR_EE4B2_9", - "MONITOR_SE4C0_4", - "MONITOR_LOGIC_OUTS_B2_8", - "MONITOR_IMUX26_9", - "MONITOR_WW2A3_8", - "MONITOR_LOGIC_OUTS_B15_9", - "MONITOR_WL1END3_6", - "MONITOR_ALM6", - "MONITOR_BYP3_6", - "MONITOR_IMUX28_3", - "MONITOR_SW4A0_4", - "MONITOR_FAN7_6", - "MONITOR_SW4END1_9", - "MONITOR_IMUX35_7", - "MONITOR_BLOCK_OUTS_B3_9", - "MONITOR_EOC", - "MONITOR_EE4BEG3_9", - "MONITOR_TESTSI2", - "MONITOR_LH10_4", - "MONITOR_ER1BEG3_5", - "MONITOR_SE4C2_0", - "MONITOR_WW4END2_6", - "MONITOR_LH10_2", - "MONITOR_SW4END1_7", - "MONITOR_IMUX35_6", - "MONITOR_LOGIC_OUTS_B23_6", - "MONITOR_WR1END0_7", - "MONITOR_BUSY", - "MONITOR_EE4B3_0", - "MONITOR_NW2A0_2", - "MONITOR_VERT_VAUXP13", - "MONITOR_ALM2", - "MONITOR_EE2BEG3_0", - "MONITOR_TESTADCIN4", - "MONITOR_FAN1_0", - "MONITOR_IMUX42_5", - "MONITOR_WW4END0_9", - "MONITOR_WW4END3_7", - "MONITOR_EE4BEG0_7", - "MONITOR_IMUX40_8", - "MONITOR_EE4C0_5", - "MONITOR_SW4A0_6", - "MONITOR_LOGIC_OUTS_B1_0", - "MONITOR_IMUX28_4", - "MONITOR_WW4B3_8", - "MONITOR_EE4C1_3", - "MONITOR_EE2A1_2", - "MONITOR_WW4B1_2", - "MONITOR_BYP0_6", - "MONITOR_WW2END2_3", - "MONITOR_WW4END1_5", - "MONITOR_BLOCK_OUTS_B2_5", - "MONITOR_DI3", - "MONITOR_BYP1_8", - "MONITOR_LOGIC_OUTS_B3_6", - "MONITOR_FAN6_2", - "MONITOR_EE4BEG1_9", - "MONITOR_WW4A3_4", - "MONITOR_LOGIC_OUTS_B10_2", - "MONITOR_LH2_9", - "MONITOR_LH1_0", - "MONITOR_EE2A1_0", - "MONITOR_WW2END3_7", - "MONITOR_WW4A2_6", - "MONITOR_BLOCK_OUTS_B1_2", - "MONITOR_IMUX11_0", - "MONITOR_NW2A2_1", - "MONITOR_ER1BEG1_5", - "MONITOR_FAN1_4", - "MONITOR_DRDY", - "MONITOR_CLK1_5", - "MONITOR_IMUX46_7", - "MONITOR_NE4BEG1_1", - "MONITOR_TESTADCOUT15", - "MONITOR_EL1BEG2_9", - "MONITOR_BLOCK_OUTS_B3_2", - "MONITOR_IMUX6_6", - "MONITOR_WW4END3_9", - "MONITOR_NW2A1_2", - "MONITOR_WW4END1_4", - "MONITOR_TESTADCIN219", - "MONITOR_TESTENJTAG", - "MONITOR_HORIZ_VAUXN7", - "MONITOR_CTRL0_9", - "MONITOR_SW4END0_4", - "MONITOR_EE4B1_4", - "MONITOR_NW4A0_1", - "MONITOR_LH8_8", - "MONITOR_HORIZ_VAUXN11", - "MONITOR_IMUX21_1", - "MONITOR_LOGIC_OUTS_B1_5", - "MONITOR_EE2BEG0_0", - "MONITOR_IMUX46_1", - "MONITOR_DI8", - "MONITOR_NW4END3_2", - "MONITOR_NE4BEG0_9", - "MONITOR_EL1BEG1_9", - "MONITOR_VERT_VAUXP11", - "MONITOR_WR1END1_8", - "MONITOR_SE2A0_8", - "MONITOR_WR1END3_4", - "MONITOR_IMUX27_7", - "MONITOR_SE4C0_3", - "MONITOR_BYP2_6", - "MONITOR_LOGIC_OUTS_B15_4", - "MONITOR_SE2A1_4", - "MONITOR_WW2END1_4", - "MONITOR_SW4A2_5", - "MONITOR_IMUX3_8", - "MONITOR_TESTADCIN12", - "MONITOR_NW2A3_1", - "MONITOR_NE4BEG3_2", - "MONITOR_SW2A3_7", - "MONITOR_LOGIC_OUTS_B18_8", - "MONITOR_TESTSI1", - "MONITOR_LH6_3", - "MONITOR_NW2A1_3", - "MONITOR_IMUX19_0", - "MONITOR_NE2A1_2", - "MONITOR_EE4B3_5", - "MONITOR_LOGIC_OUTS_B23_5", - "MONITOR_NW4END1_0", - "MONITOR_LOGIC_OUTS_B6_8", - "MONITOR_WW2END0_9", - "MONITOR_NE4C1_8", - "MONITOR_LOGIC_OUTS_B0_3", - "MONITOR_EE4B1_7", - "MONITOR_WW4C2_1", - "MONITOR_BYP3_7", - "MONITOR_IMUX30_2", - "MONITOR_ALM3", - "MONITOR_NE4BEG2_1", - "MONITOR_WR1END0_1", - "MONITOR_EE2A3_5", - "MONITOR_SE4C2_9", - "MONITOR_IMUX24_0", - "MONITOR_LOGIC_OUTS_B2_5", - "MONITOR_WW4A3_0", - "MONITOR_EE2A2_8", - "MONITOR_TESTADCOUT10", - "MONITOR_LOGIC_OUTS_B6_5", - "MONITOR_IMUX46_5", - "MONITOR_EE2BEG0_5", - "MONITOR_LOGIC_OUTS_B6_2", - "MONITOR_LOGIC_OUTS_B2_6", - "MONITOR_IMUX40_3", - "MONITOR_ER1BEG0_3", - "MONITOR_NW2A0_1", - "MONITOR_VERT_VAUXP12", - "MONITOR_IMUX45_6", - "MONITOR_EE4B2_6", - "MONITOR_IMUX35_5", - "MONITOR_NW4END3_7", - "MONITOR_LOGIC_OUTS_B11_7", - "MONITOR_IMUX7_6", - "MONITOR_SW4A1_7", - "MONITOR_WW2A0_0", - "MONITOR_NW4END0_6", - "MONITOR_SW4END0_5", - "MONITOR_SW4A2_7", - "MONITOR_IMUX18_6", - "MONITOR_HORIZ_VAUXP14", - "MONITOR_NE4BEG0_3", - "MONITOR_NW4A1_8", - "MONITOR_LOGIC_OUTS_B12_2", - "MONITOR_SE4BEG1_9", - "MONITOR_LOGIC_OUTS_B1_2", - "MONITOR_NW4END0_1", - "MONITOR_WW4A2_2", - "MONITOR_SW4END3_7", - "MONITOR_IMUX32_2", - "MONITOR_NE4BEG2_9", - "MONITOR_SW4A2_6", - "MONITOR_BYP1_3", - "MONITOR_EE2A3_2", - "MONITOR_IMUX12_4", - "MONITOR_SE2A0_4", - "MONITOR_TESTADCOUT7", - "MONITOR_EE4A2_1", - "MONITOR_NW2A2_5", - "MONITOR_IMUX30_9", - "MONITOR_WL1END2_5", - "MONITOR_IMUX7_3", - "MONITOR_IMUX29_3", - "MONITOR_NW2A2_9", - "MONITOR_SE4C2_6", - "MONITOR_FAN4_9", - "MONITOR_IMUX27_4", - "MONITOR_IMUX10_1", - "MONITOR_IMUX36_2", - "MONITOR_WR1END2_2", - "MONITOR_TESTDB4", - "MONITOR_IMUX10_2", - "MONITOR_DO1", - "MONITOR_WW2A0_7", - "MONITOR_IMUX18_2", - "MONITOR_WW2A2_9", - "MONITOR_CTRL1_6", - "MONITOR_TESTDB1", - "MONITOR_LOGIC_OUTS_B11_8", - "MONITOR_BLOCK_OUTS_B2_3", - "MONITOR_MUXADDR4", - "MONITOR_CLK1_2", - "MONITOR_EE4A2_9", - "MONITOR_NE4C2_3", - "MONITOR_SW4A1_6", - "MONITOR_WW2A2_0", - "MONITOR_EL1BEG3_1", - "MONITOR_IMUX43_1", - "MONITOR_LH7_6", - "MONITOR_SE4C0_6", - "MONITOR_WW4B3_3", - "MONITOR_CLK0_1", - "MONITOR_TESTADCIN9", - "MONITOR_IMUX31_8", - "MONITOR_SE4C2_5", - "MONITOR_SE2A0_0", - "MONITOR_IMUX3_3", - "MONITOR_VERT_VAUXN8", - "MONITOR_SE4BEG1_3", - "MONITOR_SE4C1_6", - "MONITOR_VERT_VAUXN5", - "MONITOR_SW2A1_8", - "MONITOR_IMUX8_7", - "MONITOR_LOGIC_OUTS_B9_5", - "MONITOR_IMUX41_7", - "MONITOR_VERT_VAUXN12", - "MONITOR_NE4BEG0_5", - "MONITOR_WW4B0_4", - "MONITOR_EE4BEG2_3", - "MONITOR_EE4C3_7", - "MONITOR_SE4C3_0", - "MONITOR_IMUX32_1", - "MONITOR_WR1END3_1", - "MONITOR_WW2END2_8", - "MONITOR_IMUX21_7", - "MONITOR_DADDR3", - "MONITOR_WW4B3_6", - "MONITOR_LOGIC_OUTS_B12_1", - "MONITOR_WW2END3_3", - "MONITOR_WW4A0_1", - "MONITOR_FAN6_6", - "MONITOR_VERT_VAUXP4", - "MONITOR_SE2A1_8", - "MONITOR_IMUX23_9", - "MONITOR_ER1BEG3_3", - "MONITOR_IMUX3_6", - "MONITOR_EE4BEG1_8", - "MONITOR_WR1END1_2", - "MONITOR_SE4C1_7", - "MONITOR_FAN4_2", - "MONITOR_WW4B2_7", - "MONITOR_TESTTDI", - "MONITOR_EE4A0_1", - "MONITOR_EE2A3_7", - "MONITOR_LOGIC_OUTS_B7_2", - "MONITOR_EE2A3_9", - "MONITOR_LOGIC_OUTS_B18_5", - "MONITOR_IMUX36_4", - "MONITOR_VERT_VAUXP7", - "MONITOR_SW2A1_6", - "MONITOR_EE2BEG1_6", - "MONITOR_DI12", - "MONITOR_LOGIC_OUTS_B4_5", - "MONITOR_LOGIC_OUTS_B8_4", - "MONITOR_IMUX47_2", - "MONITOR_LH7_3", - "MONITOR_EE4A2_8", - "MONITOR_IMUX36_6", - "MONITOR_NW4A3_1", - "MONITOR_IMUX37_9", - "MONITOR_IMUX40_2", - "MONITOR_NW4END0_8", - "MONITOR_NE2A0_9", - "MONITOR_WR1END0_9", - "MONITOR_IMUX25_8", - "MONITOR_LOGIC_OUTS_B15_6", - "MONITOR_WL1END0_9", - "MONITOR_TESTADCCLK3", - "MONITOR_FAN1_9", - "MONITOR_LOGIC_OUTS_B2_1", - "MONITOR_CHANNEL2", - "MONITOR_IMUX4_2", - "MONITOR_LH5_3", - "MONITOR_IMUX7_8", - "MONITOR_LOGIC_OUTS_B1_8", - "MONITOR_LOGIC_OUTS_B10_5", - "MONITOR_IMUX27_5", - "MONITOR_IMUX42_2", - "MONITOR_WW4C3_7", - "MONITOR_IMUX4_7", - "MONITOR_LOGIC_OUTS_B5_2", - "MONITOR_WW2A1_9", - "MONITOR_IMUX14_6", - "MONITOR_WW4A3_6", - "MONITOR_SE4C3_9", - "MONITOR_WW2END3_4", - "MONITOR_IMUX27_2", - "MONITOR_NE2A1_3", - "MONITOR_IMUX43_8", - "MONITOR_OT", - "MONITOR_IMUX11_1", - "MONITOR_IMUX1_8", - "MONITOR_IMUX12_0", - "MONITOR_FAN7_7", - "MONITOR_BYP6_0", - "MONITOR_IMUX13_1", - "MONITOR_LOGIC_OUTS_B11_4", - "MONITOR_LOGIC_OUTS_B11_0", - "MONITOR_LOGIC_OUTS_B9_3", - "MONITOR_FAN2_3", - "MONITOR_VAUXP2", - "MONITOR_NW4END1_6", - "MONITOR_WL1END3_9", - "MONITOR_BYP2_9", - "MONITOR_IMUX17_6", - "MONITOR_FAN5_7", - "MONITOR_WW4B1_4", - "MONITOR_LH6_9", - "MONITOR_SE4C1_1", - "MONITOR_ER1BEG1_6", - "MONITOR_IMUX27_3", - "MONITOR_WL1END1_0", - "MONITOR_WL1END3_7", - "MONITOR_IMUX24_4", - "MONITOR_SW2A0_2", - "MONITOR_EE4A0_5", - "MONITOR_EE4C2_7", - "MONITOR_IMUX2_5", - "MONITOR_BLOCK_OUTS_B2_4", - "MONITOR_LH9_5", - "MONITOR_SE4C2_3", - "MONITOR_EE4C1_9", - "MONITOR_SW4END3_2", - "MONITOR_BYP1_6", - "MONITOR_IMUX17_0", - "MONITOR_LOGIC_OUTS_B16_1", - "MONITOR_LOGIC_OUTS_B23_4", - "MONITOR_LOGIC_OUTS_B6_6", - "MONITOR_IMUX43_0", - "MONITOR_IMUX6_9", - "MONITOR_NW2A2_3", - "MONITOR_LOGIC_OUTS_B19_6", - "MONITOR_IMUX8_0", - "MONITOR_LOGIC_OUTS_B3_2", - "MONITOR_SW2A2_5", - "MONITOR_IMUX9_6", - "MONITOR_TESTSO1", - "MONITOR_LOGIC_OUTS_B5_3", - "MONITOR_LOGIC_OUTS_B15_2", - "MONITOR_TESTADCIN26", - "MONITOR_WR1END0_2", - "MONITOR_IMUX23_2", - "MONITOR_SE4C0_7", - "MONITOR_WW4END0_4", - "MONITOR_WW2END1_2", - "MONITOR_IMUX30_3", - "MONITOR_IMUX45_2", - "MONITOR_NE4C3_2", - "MONITOR_LH7_1", - "MONITOR_WW4A1_8", - "MONITOR_BLOCK_OUTS_B0_5", - "MONITOR_NE4C2_7", - "MONITOR_EE2A1_8", - "MONITOR_LOGIC_OUTS_B20_9", - "MONITOR_SE2A3_4", - "MONITOR_CTRL1_1", - "MONITOR_VAUXN10", - "MONITOR_EE4A2_7", - "MONITOR_EE2A2_2", - "MONITOR_WR1END1_0", - "MONITOR_IMUX6_8", - "MONITOR_IMUX28_9", - "MONITOR_WW4C3_4", - "MONITOR_NE4BEG1_6", - "MONITOR_CHANNEL0", - "MONITOR_EE4A1_0", - "MONITOR_BYP6_9", - "MONITOR_LOGIC_OUTS_B17_7", - "MONITOR_IMUX23_1", - "MONITOR_NW4END0_3", - "MONITOR_NE4BEG0_1", - "MONITOR_LOGIC_OUTS_B7_5", - "MONITOR_WR1END3_0", - "MONITOR_SE2A1_6", - "MONITOR_NE2A1_0", - "MONITOR_FAN7_8", - "MONITOR_NW2A3_0", - "MONITOR_SE2A1_1", - "MONITOR_NW4END3_9", - "MONITOR_NE2A1_6", - "MONITOR_WW4B0_1", - "MONITOR_SE2A2_2", - "MONITOR_IMUX47_0", - "MONITOR_ER1BEG1_3", - "MONITOR_WR1END2_3", - "MONITOR_DI9", - "MONITOR_IMUX29_7", - "MONITOR_EE4BEG0_8", - "MONITOR_IMUX9_4", - "MONITOR_SW4END1_8", - "MONITOR_LH2_8", - "MONITOR_SE4BEG3_5", - "MONITOR_IMUX4_1", - "MONITOR_WW2A0_1", - "MONITOR_WW4C1_2", - "MONITOR_CLK1_3", - "MONITOR_DO7", - "MONITOR_IMUX19_8", - "MONITOR_NE4BEG2_5", - "MONITOR_LH2_0", - "MONITOR_WW4B0_8", - "MONITOR_IMUX47_5", - "MONITOR_EE2BEG1_3", - "MONITOR_IMUX40_6", - "MONITOR_IMUX15_4", - "MONITOR_NE4BEG1_0", - "MONITOR_LH10_7", - "MONITOR_SE4C3_2", - "MONITOR_CTRL0_6", - "MONITOR_LOGIC_OUTS_B15_0", - "MONITOR_FAN7_4", - "MONITOR_NE4C0_0", - "MONITOR_CLK0_3", - "MONITOR_IMUX13_7", - "MONITOR_LH4_4", - "MONITOR_NE4C1_1", - "MONITOR_WW4C3_0", - "MONITOR_SE4BEG3_7", - "MONITOR_VAUXP5", - "MONITOR_VAUXN15", - "MONITOR_WW4B1_3", - "MONITOR_HORIZ_VAUXP7", - "MONITOR_SW2A1_5", - "MONITOR_IMUX6_4", - "MONITOR_NE2A0_4", - "MONITOR_LOGIC_OUTS_B10_4", - "MONITOR_LOGIC_OUTS_B21_9", - "MONITOR_CTRL0_1", - "MONITOR_IMUX16_5", - "MONITOR_WL1END1_5", - "MONITOR_TESTDB9", - "MONITOR_EE2A2_7", - "MONITOR_IMUX25_2", - "MONITOR_WW2A3_9", - "MONITOR_SW2A3_9", - "MONITOR_IMUX19_4", - "MONITOR_CLK0_5", - "MONITOR_LOGIC_OUTS_B4_6", - "MONITOR_IMUX21_3", - "MONITOR_TESTSI4", - "MONITOR_IMUX14_1", - "MONITOR_EE2BEG3_5", - "MONITOR_BYP5_6", - "MONITOR_LOGIC_OUTS_B20_8", - "MONITOR_EE4BEG1_0", - "MONITOR_HORIZ_VAUXP10", - "MONITOR_IMUX30_6", - "MONITOR_FAN3_9", - "MONITOR_FAN0_9", - "MONITOR_NW4END1_3", - "MONITOR_LOGIC_OUTS_B23_7", - "MONITOR_BYP2_0", - "MONITOR_SW4END2_8", - "MONITOR_WW4B0_2", - "MONITOR_SW2A0_9", - "MONITOR_BYP7_2", - "MONITOR_VAUXP0", - "MONITOR_SE4BEG1_8", - "MONITOR_EE2BEG1_8", - "MONITOR_EE2A1_1", - "MONITOR_LH12_7", - "MONITOR_IMUX41_9", - "MONITOR_WW4B2_9", - "MONITOR_LOGIC_OUTS_B19_0", - "MONITOR_VERT_VAUXP8", - "MONITOR_TESTSO2", - "MONITOR_IMUX8_4", - "MONITOR_SW4A3_3", - "MONITOR_LOGIC_OUTS_B9_0", - "MONITOR_LH6_6", - "MONITOR_SW4A0_7", - "MONITOR_LOGIC_OUTS_B21_6", - "MONITOR_EE4C2_8", - "MONITOR_CTRL0_3", - "MONITOR_LH9_2", - "MONITOR_LOGIC_OUTS_B19_7", - "MONITOR_WL1END2_8", - "MONITOR_DADDR6", - "MONITOR_BYP7_3", - "MONITOR_EL1BEG0_7", - "MONITOR_LOGIC_OUTS_B7_8", - "MONITOR_EE2A0_1", - "MONITOR_ER1BEG2_3", - "MONITOR_EE4C1_6", - "MONITOR_SW4END0_7", - "MONITOR_NE4C0_4", - "MONITOR_WW4A3_5", - "MONITOR_SE4C2_7", - "MONITOR_BYP4_8", - "MONITOR_IMUX15_3", - "MONITOR_NE4BEG3_0", - "MONITOR_EE4A0_2", - "MONITOR_LOGIC_OUTS_B13_9", - "MONITOR_CLK0_7", - "MONITOR_NE4C2_9", - "MONITOR_SW4END3_1", - "MONITOR_SE4C3_7", - "MONITOR_IMUX14_4", - "MONITOR_FAN4_7", - "MONITOR_LH11_8", - "MONITOR_EE4C0_8", - "MONITOR_JTAGLOCKED", - "MONITOR_ER1BEG2_2", - "MONITOR_ALM7", - "MONITOR_IMUX45_5", - "MONITOR_NW2A3_4", - "MONITOR_NW4A0_8", - "MONITOR_WW4C1_7", - "MONITOR_SW2A2_9", - "MONITOR_IMUX31_3", - "MONITOR_WR1END2_9", - "MONITOR_EL1BEG0_9", - "MONITOR_NW4A2_8", - "MONITOR_NE4BEG1_8", - "MONITOR_SW4END3_3", - "MONITOR_LOGIC_OUTS_B8_6", - "MONITOR_BYP7_1", - "MONITOR_LOGIC_OUTS_B14_5", - "MONITOR_WW2A1_7", - "MONITOR_FAN3_2", - "MONITOR_EE4C2_9", - "MONITOR_ER1BEG3_7", - "MONITOR_FAN2_4", - "MONITOR_LOGIC_OUTS_B13_5", - "MONITOR_IMUX4_4", - "MONITOR_TESTADCIN23", - "MONITOR_FAN1_8", - "MONITOR_LH5_4", - "MONITOR_IMUX33_1", - "MONITOR_DADDR2", - "MONITOR_NW4A3_0", - "MONITOR_LH5_7", - "MONITOR_IMUX24_9", - "MONITOR_IMUX32_8", - "MONITOR_NW4END0_2", - "MONITOR_TESTSCANMODE4", - "MONITOR_WW4B1_6", - "MONITOR_TESTSCANCLK4", - "MONITOR_IMUX17_2", - "MONITOR_IMUX42_8", - "MONITOR_SW2A2_6", - "MONITOR_IMUX17_9", - "MONITOR_WR1END1_1", - "MONITOR_IMUX2_0", - "MONITOR_EE2A0_7", - "MONITOR_LH11_1", - "MONITOR_WR1END1_5", - "MONITOR_SE2A1_3", - "MONITOR_CTRL1_3", - "MONITOR_EE4B3_8", - "MONITOR_NW4END3_4", - "MONITOR_SE4BEG0_6", - "MONITOR_SW2A1_9", - "MONITOR_LOGIC_OUTS_B22_0", - "MONITOR_ER1BEG0_6", - "MONITOR_IMUX46_3", - "MONITOR_WL1END3_4", - "MONITOR_IMUX18_5", - "MONITOR_WW4END3_0", - "MONITOR_LH11_6", - "MONITOR_LOGIC_OUTS_B12_3", - "MONITOR_EE4C1_0", - "MONITOR_EE4B3_1", - "MONITOR_LH6_4", - "MONITOR_LH2_6", - "MONITOR_WW4C3_8", - "MONITOR_EE2A0_2", - "MONITOR_FAN6_5", - "MONITOR_VERT_VAUXN7", - "MONITOR_IMUX3_0", - "MONITOR_IMUX47_3", - "MONITOR_VERT_VAUXN4", - "MONITOR_WR1END2_4", - "MONITOR_SW4A1_9", - "MONITOR_TESTADCIN212", - "MONITOR_IMUX6_1", - "MONITOR_IMUX33_7", - "MONITOR_TESTDB6", - "MONITOR_IMUX31_7", - "MONITOR_WL1END0_7", - "MONITOR_IMUX23_6", - "MONITOR_WW4END2_2", - "MONITOR_ER1BEG1_2", - "MONITOR_NW2A0_8", - "MONITOR_WW4END0_1", - "MONITOR_LH8_2", - "MONITOR_SE2A0_1", - "MONITOR_LOGIC_OUTS_B17_8", - "MONITOR_VERT_VAUXN11", - "MONITOR_NW2A1_1", - "MONITOR_WW4C2_5", - "MONITOR_DADDR4", - "MONITOR_EL1BEG1_5", - "MONITOR_EE4C2_1", - "MONITOR_ALM4", - "MONITOR_LOGIC_OUTS_B1_7", - "MONITOR_WW4B0_5", - "MONITOR_EE4B2_7", - "MONITOR_EE4C1_5", - "MONITOR_EE2A0_8", - "MONITOR_BLOCK_OUTS_B0_9", - "MONITOR_IMUX12_5", - "MONITOR_IMUX18_4", - "MONITOR_FAN2_0", - "MONITOR_EE4A2_6", - "MONITOR_TESTDRCK", - "MONITOR_FAN5_9", - "MONITOR_WW2END0_5", - "MONITOR_SE2A0_9", - "MONITOR_BYP5_8", - "MONITOR_WW2END1_8", - "MONITOR_EE4A3_4", - "MONITOR_FAN3_3", - "MONITOR_SE2A3_5", - "MONITOR_LOGIC_OUTS_B22_2", - "MONITOR_ER1BEG0_8", - "MONITOR_FAN4_3", - "MONITOR_IMUX20_6", - "MONITOR_VAUXP13", - "MONITOR_IMUX15_0", - "MONITOR_IMUX35_2", - "MONITOR_WW4END2_7", - "MONITOR_EE2BEG3_6", - "MONITOR_HORIZ_VAUXP3", - "MONITOR_IMUX39_4", - "MONITOR_BYP1_1", - "MONITOR_SE4BEG3_4", - "MONITOR_IMUX18_7", - "MONITOR_LOGIC_OUTS_B4_2", - "MONITOR_SE4C0_1", - "MONITOR_EE4B1_0", - "MONITOR_NE4C3_4", - "MONITOR_WL1END1_3", - "MONITOR_DI10", - "MONITOR_ER1BEG1_1", - "MONITOR_VP", - "MONITOR_BLOCK_OUTS_B0_4", - "MONITOR_TESTADCOUT17", - "MONITOR_SW2A1_2", - "MONITOR_LOGIC_OUTS_B7_9", - "MONITOR_VAUXP14", - "MONITOR_IMUX1_9", - "MONITOR_TESTADCIN6", - "MONITOR_EE2BEG3_2", - "MONITOR_NW4A3_3", - "MONITOR_LH9_6", - "MONITOR_LH5_6", - "MONITOR_LOGIC_OUTS_B19_5", - "MONITOR_BLOCK_OUTS_B3_1", - "MONITOR_BYP3_2", - "MONITOR_CTRL0_0", - "MONITOR_LOGIC_OUTS_B8_2", - "MONITOR_WW2A2_2", - "MONITOR_WW2END3_9", - "MONITOR_IMUX40_5", - "MONITOR_BLOCK_OUTS_B3_7", - "MONITOR_VAUXN8", - "MONITOR_WR1END0_4", - "MONITOR_EE4A3_5", - "MONITOR_DO10", - "MONITOR_EL1BEG0_5", - "MONITOR_SW4A1_4", - "MONITOR_ER1BEG2_7", - "MONITOR_NE4BEG2_3", - "MONITOR_EE4A1_7", - "MONITOR_IMUX27_8", - "MONITOR_EE4A2_3", - "MONITOR_LOGIC_OUTS_B19_1", - "MONITOR_EE2BEG0_8", - "MONITOR_SW4END0_2", - "MONITOR_HORIZ_VAUXN3", - "MONITOR_TESTADCCLK2", - "MONITOR_NE4BEG0_6", - "MONITOR_WL1END0_6", - "MONITOR_SE2A0_3", - "MONITOR_VN", - "MONITOR_LOGIC_OUTS_B3_5", - "MONITOR_IMUX16_3", - "MONITOR_WW2END3_2", - "MONITOR_WR1END2_8", - "MONITOR_IMUX32_3", - "MONITOR_IMUX20_3", - "MONITOR_IMUX4_6", - "MONITOR_SE4C2_4", - "MONITOR_BYP2_1", - "MONITOR_LH11_2", - "MONITOR_LOGIC_OUTS_B14_9", - "MONITOR_IMUX20_7", - "MONITOR_BYP0_7", - "MONITOR_BYP4_7", - "MONITOR_TESTDB7", - "MONITOR_LOGIC_OUTS_B17_3", - "MONITOR_TESTADCCLK0", - "MONITOR_IMUX34_9", - "MONITOR_SE2A3_7", - "MONITOR_IMUX3_5", - "MONITOR_LH1_6", - "MONITOR_IMUX41_0", - "MONITOR_NE2A2_5", - "MONITOR_IMUX42_0", - "MONITOR_BYP4_2", - "MONITOR_WW4A3_7", - "MONITOR_FAN2_2", - "MONITOR_NW4A0_3", - "MONITOR_FAN7_3", - "MONITOR_VAUXN9", - "MONITOR_WL1END1_8", - "MONITOR_SW2A3_5", - "MONITOR_LOGIC_OUTS_B21_2", - "MONITOR_LOGIC_OUTS_B6_0", - "MONITOR_BYP3_0", - "MONITOR_IMUX33_4", - "MONITOR_IMUX5_7", - "MONITOR_WW2A3_7", - "MONITOR_EE4BEG3_8", - "MONITOR_TESTCAPTURE", - "MONITOR_NE4C2_2", - "MONITOR_WW4A3_1", - "MONITOR_IMUX24_7", - "MONITOR_BYP2_4", - "MONITOR_IMUX21_5", - "MONITOR_NE4C3_9", - "MONITOR_TESTTDO", - "MONITOR_IMUX10_6", - "MONITOR_LOGIC_OUTS_B16_6", - "MONITOR_NE2A2_6", - "MONITOR_IMUX45_3", - "MONITOR_IMUX11_3", - "MONITOR_IMUX14_3", - "MONITOR_SW4A2_0", - "MONITOR_IMUX35_4", - "MONITOR_WW4END2_0", - "MONITOR_CLK0_9", - "MONITOR_SE4BEG0_0", - "MONITOR_NE4C1_7", - "MONITOR_IMUX42_3", - "MONITOR_MUXADDR3", - "MONITOR_EE4A2_5", - "MONITOR_SW2A3_4", - "MONITOR_NW2A3_6", - "MONITOR_WL1END2_4", - "MONITOR_EE4BEG1_3", - "MONITOR_IMUX37_8", - "MONITOR_SE4BEG1_0", - "MONITOR_WL1END2_7", - "MONITOR_WW2END3_8", - "MONITOR_IMUX42_1", - "MONITOR_EE4B3_7", - "MONITOR_WW4C0_7", - "MONITOR_IMUX9_9", - "MONITOR_BLOCK_OUTS_B1_1", - "MONITOR_NW4A2_6", - "MONITOR_DI11", - "MONITOR_LOGIC_OUTS_B7_4", - "MONITOR_CTRL1_9", - "MONITOR_FAN6_3", - "MONITOR_BLOCK_OUTS_B1_4", - "MONITOR_IMUX38_0", - "MONITOR_NW2A1_6", - "MONITOR_EE4A1_9", - "MONITOR_SW4A2_1", - "MONITOR_EE2A3_8", - "MONITOR_WL1END3_2", - "MONITOR_NW4END2_1", - "MONITOR_LH10_6", - "MONITOR_WL1END0_3", - "MONITOR_BYP0_5", - "MONITOR_LOGIC_OUTS_B0_6", - "MONITOR_VAUXN6", - "MONITOR_ER1BEG1_8", - "MONITOR_SE4C0_2", - "MONITOR_IMUX1_0", - "MONITOR_LH4_3", - "MONITOR_SW2A3_3", - "MONITOR_IMUX4_8", - "MONITOR_IMUX12_2", - "MONITOR_NW4A3_6", - "MONITOR_SW2A0_3", - "MONITOR_EE4A1_8", - "MONITOR_IMUX39_2", - "MONITOR_LH3_9", - "MONITOR_IMUX12_6", - "MONITOR_IMUX7_7", - "MONITOR_LOGIC_OUTS_B16_8", - "MONITOR_FAN0_5", - "MONITOR_SW4END0_1", - "MONITOR_VAUXN0", - "MONITOR_BYP1_7", - "MONITOR_LH6_8", - "MONITOR_EL1BEG3_9", - "MONITOR_IMUX15_6", - "MONITOR_DO0", - "MONITOR_IMUX10_4", - "MONITOR_LOGIC_OUTS_B6_1", - "MONITOR_WW2A1_6", - "MONITOR_EE4A0_9", - "MONITOR_LH2_3", - "MONITOR_LOGIC_OUTS_B18_7", - "MONITOR_TESTADCCLK1", - "MONITOR_HORIZ_VAUXP15", - "MONITOR_TESTSO0", - "MONITOR_TESTDB10", - "MONITOR_NE2A3_1", - "MONITOR_VAUXP10", - "MONITOR_IMUX47_7", - "MONITOR_NW4END2_5", - "MONITOR_WW4B0_0", - "MONITOR_WW2A3_6", - "MONITOR_WW2END1_3", - "MONITOR_EE4A2_2", - "MONITOR_BYP3_9", - "MONITOR_LH9_9", - "MONITOR_LH6_2", - "MONITOR_EE4C1_4", - "MONITOR_IMUX38_1", - "MONITOR_NE4BEG3_8", - "MONITOR_SE2A0_5", - "MONITOR_EE4B0_2", - "MONITOR_CONVSTCLK", - "MONITOR_WW4A1_7", - "MONITOR_BLOCK_OUTS_B0_2", - "MONITOR_FAN1_5", - "MONITOR_LOGIC_OUTS_B23_3", - "MONITOR_LH5_5", - "MONITOR_IMUX44_5", - "MONITOR_WW4C0_4", - "MONITOR_SW2A0_0", - "MONITOR_SW2A2_4", - "MONITOR_BLOCK_OUTS_B2_1", - "MONITOR_WW2A2_4", - "MONITOR_WW4C1_0", - "MONITOR_TESTSHIFT", - "MONITOR_LH11_3", - "MONITOR_IMUX8_6", - "MONITOR_NW4A1_9", - "MONITOR_LOGIC_OUTS_B18_2", - "MONITOR_WW2A0_8", - "MONITOR_DADDR0", - "MONITOR_LOGIC_OUTS_B8_1", - "MONITOR_FAN4_6", - "MONITOR_IMUX24_3", - "MONITOR_SW4A2_3", - "MONITOR_TESTSE4", - "MONITOR_IMUX14_8", - "MONITOR_IMUX42_6", - "MONITOR_VERT_VAUXN0", - "MONITOR_WW4C1_1", - "MONITOR_LOGIC_OUTS_B9_4", - "MONITOR_IMUX34_7", - "MONITOR_NE4C0_6", - "MONITOR_EL1BEG3_0", - "MONITOR_WW4B0_7", - "MONITOR_LH10_0", - "MONITOR_BLOCK_OUTS_B0_8", - "MONITOR_NW2A3_2", - "MONITOR_EE2A0_0", - "MONITOR_NW4A1_7", - "MONITOR_IMUX46_6", - "MONITOR_BLOCK_OUTS_B1_5", - "MONITOR_EL1BEG3_3", - "MONITOR_WW4A1_0", - "MONITOR_CLK1_6", - "MONITOR_TESTADCIN25", - "MONITOR_IMUX24_5", - "MONITOR_ALM5", - "MONITOR_IMUX8_2", - "MONITOR_LH5_9", - "MONITOR_WR1END3_2", - "MONITOR_IMUX8_3", - "MONITOR_TESTADCIN2", - "MONITOR_LOGIC_OUTS_B8_5", - "MONITOR_DO8", - "MONITOR_LH4_0", - "MONITOR_WR1END1_3", - "MONITOR_SW4A0_0", - "MONITOR_WR1END1_6", - "MONITOR_VERT_VAUXN3", - "MONITOR_NW4END1_8", - "MONITOR_WL1END0_4", - "MONITOR_SW4A3_1", - "MONITOR_EL1BEG2_4", - "MONITOR_EE4BEG0_3", - "MONITOR_NW4A3_8", - "MONITOR_LOGIC_OUTS_B10_1", - "MONITOR_WW2A3_1", - "MONITOR_EE2BEG1_7", - "MONITOR_BLOCK_OUTS_B2_2", - "MONITOR_ER1BEG3_8", - "MONITOR_WW4A1_1", - "MONITOR_SW4END1_0", - "MONITOR_LH8_9", - "MONITOR_LOGIC_OUTS_B14_2", - "MONITOR_SW2A1_7", - "MONITOR_IMUX2_9", - "MONITOR_WL1END0_5", - "MONITOR_VERT_VAUXP2", - "MONITOR_EL1BEG0_4", - "MONITOR_LOGIC_OUTS_B8_0", - "MONITOR_IMUX37_7", - "MONITOR_IMUX30_8", - "MONITOR_IMUX34_4", - "MONITOR_IMUX18_3", - "MONITOR_IMUX33_6", - "MONITOR_WW4END2_8", - "MONITOR_NE4C1_9", - "MONITOR_IMUX13_5", - "MONITOR_NW4END2_3", - "MONITOR_IMUX35_9", - "MONITOR_EL1BEG2_0", - "MONITOR_IMUX29_8", - "MONITOR_ER1BEG2_8", - "MONITOR_IMUX6_2", - "MONITOR_IMUX38_2", - "MONITOR_SW2A3_8", - "MONITOR_TESTSE1", - "MONITOR_EL1BEG2_6", - "MONITOR_IMUX47_9", - "MONITOR_BLOCK_OUTS_B3_8", - "MONITOR_EE4A3_1", - "MONITOR_BYP0_4", - "MONITOR_IMUX36_5", - "MONITOR_LOGIC_OUTS_B7_7", - "MONITOR_NW2A0_5", - "MONITOR_EE4A2_4", - "MONITOR_LOGIC_OUTS_B9_9", - "MONITOR_DO13", - "MONITOR_IMUX35_8", - "MONITOR_IMUX42_4", - "MONITOR_LOGIC_OUTS_B5_5", - "MONITOR_IMUX47_4", - "MONITOR_EE4B0_8", - "MONITOR_NE2A0_8", - "MONITOR_TESTADCIN216", - "MONITOR_EE4C1_8", - "MONITOR_SE4C1_3", - "MONITOR_FAN6_7", - "MONITOR_BYP6_8", - "MONITOR_WW4END1_3", - "MONITOR_EE4BEG2_6", - "MONITOR_IMUX14_0", - "MONITOR_WR1END0_0", - "MONITOR_CLK1_8", - "MONITOR_IMUX0_9", - "MONITOR_SW4A2_4", - "MONITOR_LOGIC_OUTS_B19_3", - "MONITOR_TESTSE0", - "MONITOR_LOGIC_OUTS_B18_9", - "MONITOR_IMUX36_1", - "MONITOR_WW2END2_9", - "MONITOR_SW4A0_1", - "MONITOR_NE4BEG3_1", - "MONITOR_SW2A0_8", - "MONITOR_SE2A1_9", - "MONITOR_SW4END2_1", - "MONITOR_SW2A1_3", - "MONITOR_LOGIC_OUTS_B6_3", - "MONITOR_WW4A2_1", - "MONITOR_FAN3_7", - "MONITOR_TESTADCIN8", - "MONITOR_SE4BEG2_6", - "MONITOR_SE4BEG1_5", - "MONITOR_IMUX33_5", - "MONITOR_WW2END1_5", - "MONITOR_IMUX34_1", - "MONITOR_CHANNEL1", - "MONITOR_IMUX9_0", - "MONITOR_EE4A3_8", - "MONITOR_EE4B0_6", - "MONITOR_NW4END1_5", - "MONITOR_LOGIC_OUTS_B10_7", - "MONITOR_IMUX31_9", - "MONITOR_WW4C2_9", - "MONITOR_BLOCK_OUTS_B0_7", - "MONITOR_EL1BEG1_1", - "MONITOR_LOGIC_OUTS_B16_3", - "MONITOR_EE4C2_5", - "MONITOR_LH11_0", - "MONITOR_IMUX39_9", - "MONITOR_WL1END2_2", - "MONITOR_WR1END1_9", - "MONITOR_IMUX22_7", - "MONITOR_NE4C3_8", - "MONITOR_NE4C2_6", - "MONITOR_ER1BEG1_0", - "MONITOR_IMUX42_7", - "MONITOR_IMUX3_9", - "MONITOR_IMUX35_3", - "MONITOR_WW2END0_4", - "MONITOR_BYP6_3", - "MONITOR_IMUX26_8", - "MONITOR_SE4BEG1_7", - "MONITOR_EE4BEG2_2", - "MONITOR_HORIZ_VAUXN15", - "MONITOR_EE2A3_6", - "MONITOR_EE2BEG3_9", - "MONITOR_LOGIC_OUTS_B4_4", - "MONITOR_TESTDB5", - "MONITOR_WW4C3_6", - "MONITOR_ER1BEG2_6", - "MONITOR_IMUX12_9", - "MONITOR_BLOCK_OUTS_B1_0", - "MONITOR_IMUX9_2", - "MONITOR_IMUX33_2", - "MONITOR_CTRL0_4", - "MONITOR_EE4C0_4", - "MONITOR_IMUX26_2", - "MONITOR_LH9_1", - "MONITOR_WW4A3_8", - "MONITOR_IMUX40_0", - "MONITOR_SE2A1_2", - "MONITOR_IMUX46_2", - "MONITOR_EE4C3_0", - "MONITOR_FAN3_1", - "MONITOR_LOGIC_OUTS_B0_5", - "MONITOR_EE2A3_0", - "MONITOR_EE4B0_5", - "MONITOR_WW2A1_8", - "MONITOR_EE4B2_4", - "MONITOR_WW4B0_9", - "MONITOR_VERT_VAUXP14", - "MONITOR_BYP5_3", - "MONITOR_BYP7_4", - "MONITOR_EL1BEG2_2", - "MONITOR_TESTSO4", - "MONITOR_IMUX39_8", - "MONITOR_NE4C1_5", - "MONITOR_NW4END1_2", - "MONITOR_IMUX0_7", - "MONITOR_IMUX10_7", - "MONITOR_IMUX16_6", - "MONITOR_IMUX28_8", - "MONITOR_EE4A0_4", - "MONITOR_WL1END2_6", - "MONITOR_IMUX28_7", - "MONITOR_LH9_7", - "MONITOR_WW4B1_0", - "MONITOR_LOGIC_OUTS_B22_1", - "MONITOR_NW4A0_7", - "MONITOR_NE4BEG1_9", - "MONITOR_IMUX22_2", - "MONITOR_IMUX6_0", - "MONITOR_TESTADCIN210", - "MONITOR_LOGIC_OUTS_B22_8", - "MONITOR_LH3_2", - "MONITOR_LH7_9", - "MONITOR_FAN6_8", - "MONITOR_LH3_6", - "MONITOR_TESTADCIN18", - "MONITOR_WW4C0_8", - "MONITOR_BYP4_6", - "MONITOR_NE4C0_9", - "MONITOR_EE2BEG2_8", - "MONITOR_IMUX28_6", - "MONITOR_IMUX1_5", - "MONITOR_WW2A1_4", - "MONITOR_IMUX7_5", - "MONITOR_IMUX22_9", - "MONITOR_IMUX0_3", - "MONITOR_IMUX39_0", - "MONITOR_LOGIC_OUTS_B11_1", - "MONITOR_IMUX31_5", - "MONITOR_EE2A2_3", - "MONITOR_IMUX5_2", - "MONITOR_EE2A2_4", - "MONITOR_IMUX37_0", - "MONITOR_EE2BEG1_9", - "MONITOR_DADDR1", - "MONITOR_LOGIC_OUTS_B15_7", - "MONITOR_NE4C2_4", - "MONITOR_NE4C0_2", - "MONITOR_SW4A3_7", - "MONITOR_IMUX24_6", - "MONITOR_NW2A2_2", - "MONITOR_FAN2_7", - "MONITOR_EE4A1_5", - "MONITOR_IMUX18_9", - "MONITOR_VAUXN11", - "MONITOR_IMUX2_4", - "MONITOR_IMUX43_5", - "MONITOR_SE4BEG2_7", - "MONITOR_SW4A0_3", - "MONITOR_NW4A1_6", - "MONITOR_DI15", - "MONITOR_LOGIC_OUTS_B4_8", - "MONITOR_EE4A3_9", - "MONITOR_NW4END3_1", - "MONITOR_EE2A1_7", - "MONITOR_LOGIC_OUTS_B2_2", - "MONITOR_SE2A2_7", - "MONITOR_LOGIC_OUTS_B8_3", - "MONITOR_IMUX0_0", - "MONITOR_IMUX20_1", - "MONITOR_LOGIC_OUTS_B19_9", - "MONITOR_SW2A2_3", - "MONITOR_NW2A2_7", - "MONITOR_WW4A1_9", - "MONITOR_IMUX38_9", - "MONITOR_BYP5_5", - "MONITOR_DI0", - "MONITOR_EE4BEG0_6", - "MONITOR_BYP6_4", - "MONITOR_WW4C3_9", - "MONITOR_SW2A1_1", - "MONITOR_SW4END1_6", - "MONITOR_FAN1_2", - "MONITOR_TESTADCIN14", - "MONITOR_BYP4_0", - "MONITOR_BYP6_6", - "MONITOR_IMUX25_5", - "MONITOR_IMUX11_9", - "MONITOR_LOGIC_OUTS_B0_0", - "MONITOR_WL1END0_0", - "MONITOR_WW2A0_2", - "MONITOR_IMUX0_2", - "MONITOR_EE4B2_8", - "MONITOR_LH9_3", - "MONITOR_LOGIC_OUTS_B1_9", - "MONITOR_TESTADCIN10", - "MONITOR_FAN6_0", - "MONITOR_FAN3_4", - "MONITOR_IMUX38_3", - "MONITOR_EE4BEG3_5", - "MONITOR_LH7_7", - "MONITOR_TESTSCANCLK2", - "MONITOR_NW2A0_0", - "MONITOR_IMUX25_3", - "MONITOR_LOGIC_OUTS_B1_4", - "MONITOR_BLOCK_OUTS_B0_1", - "MONITOR_IMUX46_4", - "MONITOR_NW4A2_3", - "MONITOR_WL1END3_3", - "MONITOR_NW4A1_1", - "MONITOR_IMUX2_3", - "MONITOR_SE2A3_2", - "MONITOR_VAUXN12", - "MONITOR_IMUX29_0", - "MONITOR_BYP3_3", - "MONITOR_EE4A1_1", - "MONITOR_NE2A3_5", - "MONITOR_SW4END2_3", - "MONITOR_LOGIC_OUTS_B3_1", - "MONITOR_ER1BEG3_1", - "MONITOR_IMUX36_7", - "MONITOR_WW2END0_0", - "MONITOR_LH3_7", - "MONITOR_WL1END3_0", - "MONITOR_IMUX36_8", - "MONITOR_WW4END1_8", - "MONITOR_IMUX13_9", - "MONITOR_TESTADCOUT4", - "MONITOR_EE4B1_6", - "MONITOR_IMUX44_3", - "MONITOR_EE4BEG0_9", - "MONITOR_WW4A1_3", - "MONITOR_FAN2_6", - "MONITOR_IMUX22_0", - "MONITOR_TESTADCOUT3", - "MONITOR_VAUXN3", - "MONITOR_NE4BEG3_4", - "MONITOR_IMUX10_5", - "MONITOR_WR1END1_7", - "MONITOR_WW4A3_2", - "MONITOR_NW4END2_7", - "MONITOR_EE4B0_7", - "MONITOR_IMUX41_8", - "MONITOR_LOGIC_OUTS_B6_9", - "MONITOR_IMUX32_5", - "MONITOR_IMUX7_4", - "MONITOR_NE4BEG2_2", - "MONITOR_VERT_VAUXN9", - "MONITOR_EE2BEG0_4", - "MONITOR_IMUX28_2", - "MONITOR_IMUX29_5", - "MONITOR_IMUX31_0", - "MONITOR_NE2A3_9", - "MONITOR_IMUX20_0", - "MONITOR_IMUX38_6", - "MONITOR_LOGIC_OUTS_B5_8", - "MONITOR_BLOCK_OUTS_B3_4", - "MONITOR_SE4BEG0_2", - "MONITOR_NW4A2_7", - "MONITOR_CLK1_9", - "MONITOR_NW4A3_9", - "MONITOR_WR1END3_8", - "MONITOR_VERT_VAUXP6", - "MONITOR_SE2A3_6", - "MONITOR_NE2A2_9", - "MONITOR_VERT_VAUXN1", - "MONITOR_ER1BEG0_4", - "MONITOR_NE4C1_3", - "MONITOR_WW4C1_5", - "MONITOR_JTAGMODIFIED", - "MONITOR_SW4END3_0", - "MONITOR_NW2A3_7", - "MONITOR_LOGIC_OUTS_B9_7", - "MONITOR_ER1BEG1_9", - "MONITOR_IMUX27_9", - "MONITOR_IMUX33_8", - "MONITOR_FAN0_4", - "MONITOR_IMUX9_1", - "MONITOR_LOGIC_OUTS_B0_2", - "MONITOR_SE4BEG2_2", - "MONITOR_EE2A0_6", - "MONITOR_IMUX26_0", - "MONITOR_WW2A1_0", - "MONITOR_DCLK", - "MONITOR_WW4B3_9", - "MONITOR_LOGIC_OUTS_B18_0", - "MONITOR_EE4BEG1_1", - "MONITOR_NW4END2_0", - "MONITOR_WW4A2_8", - "MONITOR_LH9_4", - "MONITOR_EE2BEG2_4", - "MONITOR_NW2A2_6", - "MONITOR_NE2A2_4", - "MONITOR_LH6_7", - "MONITOR_BLOCK_OUTS_B3_5", - "MONITOR_IMUX19_2", - "MONITOR_IMUX13_0", - "MONITOR_LOGIC_OUTS_B2_0", - "MONITOR_SW4END0_6", - "MONITOR_LOGIC_OUTS_B20_1", - "MONITOR_SE2A2_8", - "MONITOR_SW4A2_2", - "MONITOR_BYP0_0", - "MONITOR_LOGIC_OUTS_B17_1", - "MONITOR_NE4BEG3_6", - "MONITOR_IMUX4_3", - "MONITOR_EE4C0_3", - "MONITOR_EE2BEG3_1", - "MONITOR_EE4BEG1_7", - "MONITOR_IMUX37_1", - "MONITOR_IMUX34_0", - "MONITOR_EE2BEG1_1", - "MONITOR_WW4A0_3", - "MONITOR_IMUX9_3", - "MONITOR_IMUX46_8", - "MONITOR_NW4A3_4", - "MONITOR_SW4END1_3", - "MONITOR_SE2A3_0", - "MONITOR_IMUX10_3", - "MONITOR_WW4A3_3", - "MONITOR_IMUX22_1", - "MONITOR_DI13", - "MONITOR_WW4END2_9", - "MONITOR_SE4C0_9", - "MONITOR_EL1BEG3_7", - "MONITOR_IMUX43_4", - "MONITOR_SW2A3_0", - "MONITOR_WW2END1_6", - "MONITOR_TESTSEL", - "MONITOR_SE2A3_8", - "MONITOR_EE4B1_5", - "MONITOR_IMUX25_6", - "MONITOR_IMUX36_0", - "MONITOR_IMUX28_0", - "MONITOR_WR1END3_6", - "MONITOR_WW4C1_4", - "MONITOR_EE4C3_2", - "MONITOR_NW4END1_1", - "MONITOR_WW4B2_8", - "MONITOR_SW4A1_2", - "MONITOR_LH7_4", - "MONITOR_IMUX7_0", - "MONITOR_HORIZ_VAUXP11", - "MONITOR_SE4C0_5", - "MONITOR_SE2A3_1", - "MONITOR_WW2END3_6", - "MONITOR_IMUX20_2", - "MONITOR_CLK0_4", - "MONITOR_LH12_4", - "MONITOR_IMUX36_9", - "MONITOR_LH12_9", - "MONITOR_IMUX45_0", - "MONITOR_VAUXP1", - "MONITOR_EE4BEG3_2", - "MONITOR_LH4_6", - "MONITOR_IMUX43_3", - "MONITOR_WW2A3_0", - "MONITOR_WL1END3_8", - "MONITOR_IMUX5_1", - "MONITOR_BYP1_2", - "MONITOR_EE4BEG3_3", - "MONITOR_FAN1_7", - "MONITOR_IMUX21_9", - "MONITOR_FAN7_5", - "MONITOR_SW4END0_9", - "MONITOR_EE4C2_4", - "MONITOR_DI14", - "MONITOR_DI4", - "MONITOR_WW4C0_3", - "MONITOR_FAN5_1", - "MONITOR_EE2BEG0_6", - "MONITOR_IMUX35_0", - "MONITOR_IMUX7_1", - "MONITOR_IMUX19_7", - "MONITOR_LOGIC_OUTS_B12_7", - "MONITOR_NW4END1_4", - "MONITOR_WW4B3_7", - "MONITOR_EE4C3_8", - "MONITOR_NW2A0_3", - "MONITOR_NW2A1_8", - "MONITOR_SW4END3_8", - "MONITOR_EE2A1_3", - "MONITOR_LOGIC_OUTS_B13_0", - "MONITOR_IMUX14_9", - "MONITOR_LH6_5", - "MONITOR_SW2A0_1", - "MONITOR_BLOCK_OUTS_B3_3", - "MONITOR_LOGIC_OUTS_B14_6", - "MONITOR_EE2BEG1_2", - "MONITOR_IMUX41_1", - "MONITOR_NW4END0_4", - "MONITOR_IMUX9_8", - "MONITOR_ALM0", - "MONITOR_EE2BEG0_7", - "MONITOR_DO2", - "MONITOR_IMUX17_1", - "MONITOR_NE2A1_4", - "MONITOR_IMUX45_9", - "MONITOR_IMUX44_1", - "MONITOR_NW4END1_7", - "MONITOR_DO11", - "MONITOR_VAUXN13", - "MONITOR_SEG_VP", - "MONITOR_IMUX44_0", - "MONITOR_IMUX19_9", - "MONITOR_NW4END3_6", - "MONITOR_LH12_2", - "MONITOR_LOGIC_OUTS_B3_9", - "MONITOR_LOGIC_OUTS_B9_6", - "MONITOR_IMUX47_6", - "MONITOR_LOGIC_OUTS_B13_7", - "MONITOR_EE2BEG0_3", - "MONITOR_WW2END3_1", - "MONITOR_LOGIC_OUTS_B18_4", - "MONITOR_EE4B2_5", - "MONITOR_SE4C3_3", - "MONITOR_WW2A3_4", - "MONITOR_LOGIC_OUTS_B9_2", - "MONITOR_TESTSCANMODE3", - "MONITOR_WR1END3_9", - "MONITOR_LOGIC_OUTS_B10_3", - "MONITOR_IMUX39_5", - "MONITOR_BYP6_1", - "MONITOR_LH2_7", - "MONITOR_SW4A1_3", - "MONITOR_DWE", - "MONITOR_IMUX8_9", - "MONITOR_IMUX4_9", - "MONITOR_LOGIC_OUTS_B18_1", - "MONITOR_LOGIC_OUTS_B22_9", - "MONITOR_WW4C3_5", - "MONITOR_LH8_5", - "MONITOR_BYP2_5", - "MONITOR_NW2A2_4", - "MONITOR_IMUX11_8", - "MONITOR_IMUX30_5", - "MONITOR_CLK0_8", - "MONITOR_WW2END0_6", - "MONITOR_WR1END2_0", - "MONITOR_IMUX20_5", - "MONITOR_WW4B3_4", - "MONITOR_SW4END2_2", - "MONITOR_LH10_8", - "MONITOR_EL1BEG0_0", - "MONITOR_WW4A1_2", - "MONITOR_LOGIC_OUTS_B14_8", - "MONITOR_LOGIC_OUTS_B8_9", - "MONITOR_BYP0_2", - "MONITOR_NE4BEG0_0", - "MONITOR_LH8_0", - "MONITOR_EE4BEG1_2", - "MONITOR_WW4C2_8", - "MONITOR_LOGIC_OUTS_B18_6", - "MONITOR_IMUX6_7", - "MONITOR_CTRL0_8", - "MONITOR_IMUX41_5", - "MONITOR_FAN4_8", - "MONITOR_TESTSCANCLK0", - "MONITOR_NE4BEG2_8", - "MONITOR_SE4C2_1", - "MONITOR_IMUX10_0", - "MONITOR_LOGIC_OUTS_B22_5", - "MONITOR_FAN2_1", - "MONITOR_TESTADCIN20", - "MONITOR_WW4B2_1", - "MONITOR_SW4END1_5", - "MONITOR_FAN1_1", - "MONITOR_BYP1_9", - "MONITOR_LOGIC_OUTS_B15_3", - "MONITOR_NE4BEG1_2", - "MONITOR_CONVST", - "MONITOR_NW4A1_0", - "MONITOR_LH10_3", - "MONITOR_IMUX43_9", - "MONITOR_BYP4_1", - "MONITOR_NE2A2_7", - "MONITOR_EE2A3_1", - "MONITOR_SE4C2_8", - "MONITOR_BYP1_4", - "MONITOR_CLK0_2", - "MONITOR_EE2A2_6", - "MONITOR_SE4BEG2_4", - "MONITOR_SE4C2_2", - "MONITOR_ER1BEG0_5", - "MONITOR_IMUX7_2", - "MONITOR_IMUX16_4", - "MONITOR_EE4B3_6", - "MONITOR_WW4END1_6", - "MONITOR_EE4C0_2", - "MONITOR_LOGIC_OUTS_B20_6", - "MONITOR_EE2A3_3", - "MONITOR_IMUX25_7", - "MONITOR_NW4A2_0", - "MONITOR_NW4A0_2", - "MONITOR_SE4BEG1_2", - "MONITOR_WL1END0_2", - "MONITOR_FAN0_2", - "MONITOR_EE4BEG3_1", - "MONITOR_WW4C2_7", - "MONITOR_LOGIC_OUTS_B7_6", - "MONITOR_LOGIC_OUTS_B1_3", - "MONITOR_IMUX5_9", - "MONITOR_ER1BEG1_7", - "MONITOR_IMUX19_3", - "MONITOR_BYP5_2", - "MONITOR_NW4END3_5", - "MONITOR_NE2A1_5", - "MONITOR_WW2A0_4", - "MONITOR_WL1END2_9", - "MONITOR_NW4END2_6", - "MONITOR_IMUX25_9", - "MONITOR_WL1END3_1", - "MONITOR_EE4BEG2_0", - "MONITOR_IMUX40_1", - "MONITOR_IMUX32_6", - "MONITOR_WW2A0_3", - "MONITOR_LOGIC_OUTS_B14_4", - "MONITOR_NE4BEG3_3", - "MONITOR_LH10_1", - "MONITOR_FAN7_2", - "MONITOR_EL1BEG0_3", - "MONITOR_CTRL0_2", - "MONITOR_LH8_6", - "MONITOR_SE2A2_0", - "MONITOR_BYP3_1", - "MONITOR_NE2A3_8", - "MONITOR_LOGIC_OUTS_B5_0", - "MONITOR_SW4A1_0", - "MONITOR_LH9_8", - "MONITOR_IMUX37_4", - "MONITOR_NE2A3_0", - "MONITOR_WW2END2_2", - "MONITOR_TESTDB3", - "MONITOR_WW4C3_3", - "MONITOR_IMUX38_7", - "MONITOR_IMUX16_1", - "MONITOR_NE2A0_5", - "MONITOR_SW4END1_4", - "MONITOR_NW2A0_4", - "MONITOR_EE4A3_0", - "MONITOR_NE4C1_6", - "MONITOR_EE4C0_9", - "MONITOR_LH12_6", - "MONITOR_SW2A3_1", - "MONITOR_ER1BEG3_4", - "MONITOR_EE2A1_4", - "MONITOR_LOGIC_OUTS_B15_5", - "MONITOR_LOGIC_OUTS_B8_8", - "MONITOR_WR1END3_3", - "MONITOR_LH3_1", - "MONITOR_TESTSE3", - "MONITOR_NE4C3_1", - "MONITOR_WW2A2_7", - "MONITOR_LOGIC_OUTS_B22_6", - "MONITOR_FAN5_6", - "MONITOR_TESTADCOUT11", - "MONITOR_SW4END2_7", - "MONITOR_FAN5_5", - "MONITOR_FAN6_1", - "MONITOR_IMUX22_3", - "MONITOR_BYP4_5", - "MONITOR_EL1BEG1_8", - "MONITOR_ER1BEG0_2", - "MONITOR_EE4A2_0", - "MONITOR_CTRL1_4", - "MONITOR_LOGIC_OUTS_B15_8", - "MONITOR_IMUX12_8", - "MONITOR_WW4B2_6", - "MONITOR_FAN4_5", - "MONITOR_WW4C2_6", - "MONITOR_IMUX14_7", - "MONITOR_IMUX29_2", - "MONITOR_SE4BEG3_6", - "MONITOR_WW4END1_9", - "MONITOR_LOGIC_OUTS_B11_2", - "MONITOR_LH1_8", - "MONITOR_IMUX39_1", - "MONITOR_TESTADCIN22", - "MONITOR_EE2BEG2_6", - "MONITOR_LH11_7", - "MONITOR_NE4C2_0", - "MONITOR_WW4A0_9", - "MONITOR_SW4END2_0", - "MONITOR_SE2A0_7", - "MONITOR_EL1BEG1_0", - "MONITOR_EE2BEG2_1", - "MONITOR_IMUX24_8", - "MONITOR_FAN5_0", - "MONITOR_IMUX22_8", - "MONITOR_NW2A1_5", - "MONITOR_EE4BEG1_6", - "MONITOR_DO5", - "MONITOR_TESTADCIN15", - "MONITOR_LOGIC_OUTS_B9_1", - "MONITOR_NE4C2_5", - "MONITOR_BYP0_8", - "MONITOR_WW4END3_3", - "MONITOR_IMUX22_5", - "MONITOR_IMUX26_4", - "MONITOR_DI5", - "MONITOR_IMUX5_5", - "MONITOR_IMUX3_1", - "MONITOR_EE4BEG1_4", - "MONITOR_DO4", - "MONITOR_VERT_VAUXN13", - "MONITOR_IMUX40_7", - "MONITOR_EE4B0_1", - "MONITOR_EE4C1_7", - "MONITOR_LOGIC_OUTS_B3_4", - "MONITOR_TESTSCANMODE0", - "MONITOR_LOGIC_OUTS_B20_4", - "MONITOR_WL1END0_8", - "MONITOR_FAN5_8", - "MONITOR_IMUX36_3", - "MONITOR_LOGIC_OUTS_B4_3", - "MONITOR_LOGIC_OUTS_B6_7", - "MONITOR_EE2A1_9", - "MONITOR_IMUX17_3", - "MONITOR_BYP6_2", - "MONITOR_NW2A1_7", - "MONITOR_BYP7_7", - "MONITOR_BYP3_4", - "MONITOR_WW2END2_4", - "MONITOR_LH1_7", - "MONITOR_IMUX20_4", - "MONITOR_IMUX1_6", - "MONITOR_WR1END2_6", - "MONITOR_LH10_9", - "MONITOR_WW2END0_8", - "MONITOR_TESTSO3", - "MONITOR_IMUX29_9", - "MONITOR_RESET", - "MONITOR_LH12_3", - "MONITOR_WR1END0_5", - "MONITOR_NW4A1_5", - "MONITOR_WR1END2_5", - "MONITOR_IMUX21_4", - "MONITOR_SE2A1_0", - "MONITOR_EL1BEG1_7", - "MONITOR_FAN2_5", - "MONITOR_NW4END2_4", - "MONITOR_WR1END2_1", - "MONITOR_NW2A1_9", - "MONITOR_IMUX0_1", - "MONITOR_ER1BEG0_9", - "MONITOR_FAN0_8", - "MONITOR_LOGIC_OUTS_B23_9", - "MONITOR_SE4BEG3_8", - "MONITOR_NW4END2_2", - "MONITOR_WW2END1_7", - "MONITOR_TESTADCIN217", - "MONITOR_SE4C1_2", - "MONITOR_BLOCK_OUTS_B1_6", - "MONITOR_NE4C3_0", - "MONITOR_SE4BEG1_6", - "MONITOR_LH6_0", - "MONITOR_IMUX41_4", - "MONITOR_EE2A0_5", - "MONITOR_IMUX6_3", - "MONITOR_SW4END3_5", - "MONITOR_LOGIC_OUTS_B20_3", - "MONITOR_BLOCK_OUTS_B3_6", - "MONITOR_BYP1_0", - "MONITOR_LOGIC_OUTS_B13_6", - "MONITOR_LOGIC_OUTS_B13_4", - "MONITOR_SE4C1_8", - "MONITOR_NW4A3_7", - "MONITOR_IMUX18_8", - "MONITOR_LOGIC_OUTS_B14_3", - "MONITOR_SW2A3_6", - "MONITOR_NE4C3_7", - "MONITOR_IMUX16_7", - "MONITOR_IMUX38_8", - "MONITOR_SW4A3_2", - "MONITOR_FAN2_9", - "MONITOR_NE4BEG1_5", - "MONITOR_LOGIC_OUTS_B14_1", - "MONITOR_TESTSCANCLK3", - "MONITOR_VAUXP3", - "MONITOR_DI6", - "MONITOR_FAN3_5", - "MONITOR_LOGIC_OUTS_B12_5", - "MONITOR_BLOCK_OUTS_B2_8", - "MONITOR_NE4BEG1_4", - "MONITOR_IMUX13_6", - "MONITOR_WW2END1_0", - "MONITOR_WW2A0_6", - "MONITOR_IMUX26_1", - "MONITOR_IMUX0_5", - "MONITOR_NE4C0_7", - "MONITOR_WW2A2_3", - "MONITOR_EE4C3_9", - "MONITOR_VAUXP4", - "MONITOR_IMUX45_8", - "MONITOR_EE4B3_2", - "MONITOR_NE4C1_4", - "MONITOR_EE4C3_5", - "MONITOR_SE2A2_5", - "MONITOR_EE4A3_6", - "MONITOR_NW4A1_4", - "MONITOR_EL1BEG3_2", - "MONITOR_ER1BEG0_0", - "MONITOR_LOGIC_OUTS_B22_4", - "MONITOR_ER1BEG2_9", - "MONITOR_WW4B3_0", - "MONITOR_TESTADCIN1", - "MONITOR_NE4BEG1_7", - "MONITOR_WW2END3_0", - "MONITOR_FAN3_0", - "MONITOR_SE4BEG0_7", - "MONITOR_IMUX24_1", - "MONITOR_SE4BEG3_3", - "MONITOR_NW4END2_8", - "MONITOR_VAUXN5", - "MONITOR_IMUX14_5", - "MONITOR_IMUX2_2", - "MONITOR_IMUX41_2", - "MONITOR_IMUX16_8", - "MONITOR_EE2A0_9", - "MONITOR_IMUX8_5", - "MONITOR_IMUX20_8", - "MONITOR_WW4B1_7", - "MONITOR_EL1BEG2_3", - "MONITOR_LH3_0", - "MONITOR_SW4END0_8", - "MONITOR_LOGIC_OUTS_B5_9", - "MONITOR_NE4C0_1", - "MONITOR_IMUX27_0", - "MONITOR_NW4A2_9", - "MONITOR_ALM1", - "MONITOR_NE2A0_0", - "MONITOR_EE2BEG2_0", - "MONITOR_SW2A0_5", - "MONITOR_NE4C0_3", - "MONITOR_EOS", - "MONITOR_SE4BEG0_4", - "MONITOR_LOGIC_OUTS_B4_0", - "MONITOR_EE2BEG2_5", - "MONITOR_IMUX37_5", - "MONITOR_LOGIC_OUTS_B0_9", - "MONITOR_LH4_9", - "MONITOR_IMUX0_8", - "MONITOR_EE4BEG0_4", - "MONITOR_CTRL1_2", - "MONITOR_EE2A3_4", - "MONITOR_SE4BEG2_3", - "MONITOR_TESTDB14", - "MONITOR_CLK1_1", - "MONITOR_EE4A1_4", - "MONITOR_NW2A1_0", - "MONITOR_WW4END2_4", - "MONITOR_IMUX15_2", - "MONITOR_LOGIC_OUTS_B11_5", - "MONITOR_TESTADCOUT12", - "MONITOR_BYP5_7", - "MONITOR_NE2A3_6", - "MONITOR_EE4BEG0_0", - "MONITOR_ER1BEG2_0", - "MONITOR_WW4C0_9", - "MONITOR_IMUX5_3", - "MONITOR_LOGIC_OUTS_B21_1", - "MONITOR_IMUX30_4", - "MONITOR_IMUX26_6", - "MONITOR_IMUX31_4", - "MONITOR_NE4BEG0_8", - "MONITOR_WW2A0_9", - "MONITOR_TESTADCOUT9", - "MONITOR_EE2A2_5", - "MONITOR_SEG_VN", - "MONITOR_BLOCK_OUTS_B0_0", - "MONITOR_WW4C1_3", - "MONITOR_WW4A3_9", - "MONITOR_WW4A2_3", - "MONITOR_NW2A2_0", - "MONITOR_LH2_2", - "MONITOR_IMUX2_1", - "MONITOR_IMUX17_7", - "MONITOR_DO6", - "MONITOR_FAN0_0", - "MONITOR_IMUX21_2", - "MONITOR_LOGIC_OUTS_B21_8", - "MONITOR_IMUX34_2", - "MONITOR_WW4A2_4", - "MONITOR_IMUX37_3", - "MONITOR_NE2A3_2", - "MONITOR_FAN7_9", - "MONITOR_LOGIC_OUTS_B2_3", - "MONITOR_IMUX12_3", - "MONITOR_NE2A2_1", - "MONITOR_LH12_1", - "MONITOR_NE2A0_6", - "MONITOR_NE2A2_8", - "MONITOR_NE2A3_7", - "MONITOR_WW4END0_2", - "MONITOR_IMUX0_6", - "MONITOR_TESTSI0", - "MONITOR_IMUX15_1", - "MONITOR_LOGIC_OUTS_B23_2", - "MONITOR_LOGIC_OUTS_B13_1", - "MONITOR_LOGIC_OUTS_B5_4", - "MONITOR_LOGIC_OUTS_B17_9", - "MONITOR_LH11_5", - "MONITOR_IMUX35_1", - "MONITOR_IMUX40_9", - "MONITOR_IMUX15_5", - "MONITOR_NW2A1_4", - "MONITOR_TESTADCIN7", - "MONITOR_DO12", - "MONITOR_DO3", - "MONITOR_SE4BEG2_0", - "MONITOR_IMUX32_4", - "MONITOR_LOGIC_OUTS_B15_1", - "MONITOR_WW4B1_8", - "MONITOR_NE4BEG3_7", - "MONITOR_HORIZ_VAUXN10", - "MONITOR_FAN5_4", - "MONITOR_SW2A2_2", - "MONITOR_VAUXP15", - "MONITOR_EE2A1_6", - "MONITOR_VERT_VAUXP3", - "MONITOR_WW4A0_2", - "MONITOR_LH12_5", - "MONITOR_LH1_3", - "MONITOR_TESTADCIN16", - "MONITOR_WW4B3_2", - "MONITOR_SW2A2_1", - "MONITOR_TESTSE2", - "MONITOR_SE2A0_6", - "MONITOR_LH8_4", - "MONITOR_VAUXN7", - "MONITOR_EE4C0_1", - "MONITOR_VERT_VAUXP10", - "MONITOR_SW4A3_5", - "MONITOR_IMUX11_5", - "MONITOR_EE4BEG0_5", - "MONITOR_NE4BEG2_4", - "MONITOR_IMUX21_6", - "MONITOR_VERT_VAUXP1", - "MONITOR_NE4BEG3_9", - "MONITOR_LH2_1", - "MONITOR_TESTADCOUT8", - "MONITOR_IMUX23_5", - "MONITOR_IMUX29_1", - "MONITOR_NW4A0_0", - "MONITOR_LOGIC_OUTS_B16_7", - "MONITOR_WW2END0_1", - "MONITOR_SW4END2_9", - "MONITOR_LOGIC_OUTS_B17_4", - "MONITOR_IMUX17_8", - "MONITOR_WW4B2_0", - "MONITOR_WW4C0_2", - "MONITOR_EE2BEG2_3", - "MONITOR_IMUX16_9", - "MONITOR_NE4C3_5", - "MONITOR_WR1END1_4", - "MONITOR_BYP2_2", - "MONITOR_IMUX37_2", - "MONITOR_FAN5_3", - "MONITOR_WW4B2_4", - "MONITOR_LOGIC_OUTS_B12_9", - "MONITOR_SW2A1_4", - "MONITOR_IMUX11_6", - "MONITOR_LOGIC_OUTS_B12_0", - "MONITOR_LH7_2", - "MONITOR_DO9", - "MONITOR_IMUX5_6", - "MONITOR_LOGIC_OUTS_B19_8", - "MONITOR_WW4A2_0", - "MONITOR_IMUX26_7", - "MONITOR_LOGIC_OUTS_B3_8", - "MONITOR_VAUXN1", - "MONITOR_WW4C2_4", - "MONITOR_SW4A3_8", - "MONITOR_WW4B3_1", - "MONITOR_IMUX41_3", - "MONITOR_TESTADCIN214", - "MONITOR_IMUX30_7", - "MONITOR_NW2A3_3", - "MONITOR_EE4B1_8", - "MONITOR_NW4END3_3", - "MONITOR_BLOCK_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B21_5", - "MONITOR_LOGIC_OUTS_B10_0", - "MONITOR_TESTDB15", - "MONITOR_NW4A0_5", - "MONITOR_IMUX33_3", - "MONITOR_TESTADCOUT19", - "MONITOR_TESTADCOUT16", - "MONITOR_LH5_8", - "MONITOR_VAUXN14", - "MONITOR_WW4END1_1", - "MONITOR_IMUX13_8", - "MONITOR_CTRL0_5", - "MONITOR_WR1END3_7", - "MONITOR_NW4A2_5", - "MONITOR_SW4A2_9", - "MONITOR_BYP7_9", - "MONITOR_IMUX34_8", - "MONITOR_LOGIC_OUTS_B2_4", - "MONITOR_VAUXP8", - "MONITOR_LOGIC_OUTS_B0_7", - "MONITOR_BLOCK_OUTS_B0_6", - "MONITOR_IMUX33_0", - "MONITOR_TESTADCOUT18", - "MONITOR_NW4A2_1", - "MONITOR_VERT_VAUXP5", - "MONITOR_NW2A3_5", - "MONITOR_SW4A3_0", - "MONITOR_FAN5_2", - "MONITOR_WW4B2_3", - "MONITOR_SE4BEG0_1", - "MONITOR_WW2A1_1", - "MONITOR_WW4B0_3", - "MONITOR_WL1END2_1", - "MONITOR_NE4C1_0", - "MONITOR_LOGIC_OUTS_B0_4", - "MONITOR_WW2A3_5", - "MONITOR_FAN4_1", - "MONITOR_NE2A3_3", - "MONITOR_FAN6_4", - "MONITOR_LH2_4", - "MONITOR_IMUX44_7", - "MONITOR_IMUX13_4", - "MONITOR_BYP5_0", - "MONITOR_IMUX39_7", - "MONITOR_EE4C0_7", - "MONITOR_IMUX26_3", - "MONITOR_WW2END0_7", - "MONITOR_WL1END1_7", - "MONITOR_LOGIC_OUTS_B5_7", - "MONITOR_BYP7_5", - "MONITOR_WW4END3_1", - "MONITOR_FAN3_8", - "MONITOR_LH5_1", - "MONITOR_IMUX26_5", - "MONITOR_IMUX3_4", - "MONITOR_VAUXP7", - "MONITOR_IMUX41_6", - "MONITOR_NW4END3_8", - "MONITOR_NE4BEG0_4", - "MONITOR_WW4END2_5", - "MONITOR_DO15", - "MONITOR_LOGIC_OUTS_B16_5", - "MONITOR_LOGIC_OUTS_B17_5", - "MONITOR_WW2END1_1", - "MONITOR_ER1BEG2_1", - "MONITOR_BYP3_5", - "MONITOR_EE4B2_3", - "MONITOR_EL1BEG1_3", - "MONITOR_WW2END2_6", - "MONITOR_FAN4_4", - "MONITOR_EE2BEG3_3", - "MONITOR_ER1BEG0_1", - "MONITOR_NE2A2_0", - "MONITOR_WW2END3_5", - "MONITOR_EE2BEG1_5", - "MONITOR_IMUX23_7", - "MONITOR_TESTADCIN215", - "MONITOR_TESTADCOUT5", - "MONITOR_SW2A0_7", - "MONITOR_EE2BEG0_2", - "MONITOR_WW2END2_1", - "MONITOR_EE4BEG3_4", - "MONITOR_SE2A3_3", - "MONITOR_SE4C1_9", - "MONITOR_SW4A0_5", - "MONITOR_TESTADCOUT1", - "MONITOR_IMUX18_1", - "MONITOR_LOGIC_OUTS_B10_8", - "MONITOR_IMUX27_1", - "MONITOR_IMUX8_1", - "MONITOR_BLOCK_OUTS_B2_0", - "MONITOR_TESTSCANMODE1", - "MONITOR_LOGIC_OUTS_B21_3", - "MONITOR_EE4BEG2_9", - "MONITOR_SW2A0_4", - "MONITOR_SW4A1_5", - "MONITOR_FAN1_6", - "MONITOR_WW4B1_5", - "MONITOR_IMUX39_6", - "MONITOR_IMUX15_8", - "MONITOR_BLOCK_OUTS_B2_6", - "MONITOR_SE4BEG2_9", - "MONITOR_NW4A0_9", - "MONITOR_NE2A0_7", - "MONITOR_LOGIC_OUTS_B12_4", - "MONITOR_EE4A0_3", - "MONITOR_LOGIC_OUTS_B12_6", - "MONITOR_IMUX39_3", - "MONITOR_WW2END0_3", - "MONITOR_NW4END2_9", - "MONITOR_EE4B1_1", - "MONITOR_NW2A2_8", - "MONITOR_BYP5_9", - "MONITOR_IMUX16_2", - "MONITOR_LOGIC_OUTS_B3_3", - "MONITOR_SE4BEG1_1", - "MONITOR_IMUX23_3", - "MONITOR_SE4BEG0_3", - "MONITOR_IMUX42_9", - "MONITOR_EE4B0_3", - "MONITOR_TESTADCIN27", - "MONITOR_WW2END2_5", - "MONITOR_WL1END1_1", - "MONITOR_WW4A0_0", - "MONITOR_NW4A0_6", - "MONITOR_WW4A2_9", - "MONITOR_NW2A0_7", - "MONITOR_NW4A2_2", - "MONITOR_SE4C1_4", - "MONITOR_BYP3_8", - "MONITOR_WW4END0_7", - "MONITOR_SE4C3_8", - "MONITOR_EE4BEG2_1", - "MONITOR_LH4_8", - "MONITOR_CHANNEL4", - "MONITOR_TESTADCIN19", - "MONITOR_CTRL1_5", - "MONITOR_NE4C2_8", - "MONITOR_NW4A2_4", - "MONITOR_EL1BEG0_8", - "MONITOR_LH8_1", - "MONITOR_WW4C2_0", - "MONITOR_LOGIC_OUTS_B6_4", - "MONITOR_SE4C3_1", - "MONITOR_TESTADCOUT13", - "MONITOR_IMUX1_7", - "MONITOR_SW4END1_1", - "MONITOR_EE4C3_4", - "MONITOR_IMUX29_4", - "MONITOR_IMUX44_4", - "MONITOR_SE4C1_5", - "MONITOR_NW2A3_8", - "MONITOR_SE4C0_0", - "MONITOR_SW4END2_4", - "MONITOR_TESTADCIN24", - "MONITOR_LOGIC_OUTS_B7_1", - "MONITOR_EE4A1_3", - "MONITOR_IMUX38_4", - "MONITOR_BLOCK_OUTS_B1_9", - "MONITOR_IMUX45_1", - "MONITOR_WR1END2_7", - "MONITOR_CHANNEL3", - "MONITOR_LOGIC_OUTS_B10_9", - "MONITOR_VERT_VAUXP15", - "MONITOR_EE4C2_2", - "MONITOR_EE2BEG3_7", - "MONITOR_IMUX32_7", - "MONITOR_EL1BEG2_5", - "MONITOR_LOGIC_OUTS_B17_0", - "MONITOR_WW2A1_2", - "MONITOR_EE4A0_7", - "MONITOR_IMUX19_5", - "MONITOR_EE4C0_0", - "MONITOR_VAUXP6", - "MONITOR_IMUX12_1", - "MONITOR_CLK0_6", - "MONITOR_IMUX21_8", - "MONITOR_EL1BEG2_1", - "MONITOR_BYP0_1", - "MONITOR_SE4C3_5", - "MONITOR_VERT_VAUXN6", - "MONITOR_EE2BEG2_7", - "MONITOR_LOGIC_OUTS_B11_3", - "MONITOR_WW4C3_1", - "MONITOR_LH7_8", - "MONITOR_EE4C3_1", - "MONITOR_IMUX44_8", - "MONITOR_IMUX22_6", - "MONITOR_IMUX40_4", - "MONITOR_WW4C0_5", - "MONITOR_TESTDB13", - "MONITOR_WW2A2_8", - "MONITOR_IMUX44_9", - "MONITOR_LH9_0", - "MONITOR_CLK0_0", - "MONITOR_NW2A3_9", - "MONITOR_IMUX21_0", - "MONITOR_NE4BEG2_0", - "MONITOR_BYP7_6", - "MONITOR_CTRL1_8", - "MONITOR_LH4_1", - "MONITOR_LH11_4", - "MONITOR_LH7_0", - "MONITOR_TESTADCOUT6", - "MONITOR_WW2END1_9", - "MONITOR_IMUX27_6", - "MONITOR_LOGIC_OUTS_B13_2", - "MONITOR_WR1END0_6", - "MONITOR_TESTSCANMODE2", - "MONITOR_NE2A2_3", - "MONITOR_WW4END2_1", - "MONITOR_IMUX44_6", - "MONITOR_EE4B2_2", - "MONITOR_LOGIC_OUTS_B19_4", - "MONITOR_TESTSCANCLK1", - "MONITOR_WW4END1_7", - "MONITOR_WW2END0_2", - "MONITOR_EL1BEG2_7", - "MONITOR_ER1BEG3_2", - "MONITOR_FAN2_8", - "MONITOR_TESTADCIN218", - "MONITOR_IMUX31_2", - "MONITOR_LOGIC_OUTS_B21_7", - "MONITOR_IMUX1_2", - "MONITOR_LH1_2", - "MONITOR_NE4BEG2_7", - "MONITOR_EE2BEG0_9", - "MONITOR_IMUX32_9", - "MONITOR_LOGIC_OUTS_B1_1", - "MONITOR_IMUX16_0", - "MONITOR_WW4END2_3", - "MONITOR_WW2A3_3", - "MONITOR_EL1BEG1_2", - "MONITOR_BLOCK_OUTS_B2_9", - "MONITOR_NE2A0_1", - "MONITOR_BYP7_0", - "MONITOR_TESTADCIN13", - "MONITOR_DI1", - "MONITOR_SW2A2_8", - "MONITOR_NE4BEG2_6", - "MONITOR_EE2A0_3", - "MONITOR_EE4B0_0", - "MONITOR_WW4A0_7", - "MONITOR_BYP0_9", - "MONITOR_IMUX15_7", - "MONITOR_LOGIC_OUTS_B5_6", - "MONITOR_WL1END1_4", - "MONITOR_EL1BEG2_8", - "MONITOR_FAN1_3", - "MONITOR_EE4C0_6", - "MONITOR_IMUX23_8", - "MONITOR_WW4END0_0", - "MONITOR_NE4BEG1_3", - "MONITOR_LOGIC_OUTS_B2_7", - "MONITOR_EE4B3_9", - "MONITOR_EE4A1_6", - "MONITOR_EL1BEG3_8", - "MONITOR_WW4A0_8", - "MONITOR_LOGIC_OUTS_B17_2", - "MONITOR_CLK1_7", - "MONITOR_WW2A2_1", - "MONITOR_WW4C2_2", - "MONITOR_EE2BEG1_4", - "MONITOR_IMUX34_6", - "MONITOR_SE2A0_2", - "MONITOR_LOGIC_OUTS_B20_7", - "MONITOR_BYP6_5", - "MONITOR_NE2A1_7", - "MONITOR_WW4B0_6", - "MONITOR_LH4_2", - "MONITOR_WW2A1_5", - "MONITOR_EE4BEG0_1", - "MONITOR_SE4BEG0_8", - "MONITOR_BYP4_9", - "MONITOR_IMUX1_1", - "MONITOR_EE2A2_9", - "MONITOR_WW4A0_4", - "MONITOR_WW4A1_5", - "MONITOR_SE2A2_4", - "MONITOR_NW2A0_9", - "MONITOR_SW2A3_2", - "MONITOR_LOGIC_OUTS_B21_4", - "MONITOR_EE4A0_8", - "MONITOR_SE4C3_4", - "MONITOR_EE4B3_4", - "MONITOR_EE2BEG2_9", - "MONITOR_WW4END0_3", - "MONITOR_LOGIC_OUTS_B23_0", - "MONITOR_EL1BEG3_4", - "MONITOR_SW4A3_9", - "MONITOR_CTRL1_7", - "MONITOR_IMUX17_4", - "MONITOR_LOGIC_OUTS_B2_9", - "MONITOR_EE4C3_3", - "MONITOR_BYP4_4", - "MONITOR_IMUX13_3", - "MONITOR_IMUX4_0", - "MONITOR_NE4C0_5", - "MONITOR_IMUX14_2", - "MONITOR_SW4END3_4", - "MONITOR_NE2A1_9", - "MONITOR_LOGIC_OUTS_B7_3", - "MONITOR_TESTSI3", - "MONITOR_EE4A1_2", - "MONITOR_LOGIC_OUTS_B18_3", - "MONITOR_EL1BEG3_6", - "MONITOR_SE4BEG2_8", - "MONITOR_ER1BEG3_6", - "MONITOR_IMUX43_2", - "MONITOR_TESTADCOUT2", - "MONITOR_SE4BEG3_1", - "MONITOR_SW4A0_2", - "MONITOR_SE2A1_5", - "MONITOR_NE2A3_4", - "MONITOR_LH3_3", - "MONITOR_IMUX47_1", - "MONITOR_IMUX22_4", - "MONITOR_LOGIC_OUTS_B13_8", - "MONITOR_WW4A0_6", - "MONITOR_WW4C0_0", - "MONITOR_IMUX13_2", - "MONITOR_IMUX33_9", - "MONITOR_TESTADCIN29", - "MONITOR_NE4C1_2", - "MONITOR_IMUX32_0", - "MONITOR_NE2A0_3", - "MONITOR_BYP5_1", - "MONITOR_IMUX25_4", - "MONITOR_EE4C2_6", - "MONITOR_BYP7_8", - "MONITOR_TESTADCIN211", - "MONITOR_WW4A2_5", - "MONITOR_NE4BEG0_2", - "MONITOR_SW2A2_7", - "MONITOR_EE4BEG3_0", - "MONITOR_WW4B1_9", - "MONITOR_WW2END2_7", - "MONITOR_EE4C2_3", - "MONITOR_IMUX1_3", - "MONITOR_IMUX1_4", - "MONITOR_SE2A2_6", - "MONITOR_IMUX15_9", - "MONITOR_WW4END3_2", - "MONITOR_WL1END1_9", - "MONITOR_LH12_8", - "MONITOR_SE4BEG3_9", - "MONITOR_WW4C1_8", - "MONITOR_WW2A2_6", - "MONITOR_IMUX37_6", - "MONITOR_TESTADCIN5", - "MONITOR_LH8_7", - "MONITOR_SW4A1_8", - "MONITOR_NE2A2_2", - "MONITOR_LOGIC_OUTS_B22_7", - "MONITOR_SW4A0_9", - "MONITOR_IMUX29_6", - "MONITOR_NE4BEG3_5", - "MONITOR_WW4A0_5", - "MONITOR_WW4B3_5", - "MONITOR_LH3_8", - "MONITOR_IMUX23_4", - "MONITOR_TESTADCIN213", - "MONITOR_MUXADDR1", - "MONITOR_EE4C2_0", - "MONITOR_LOGIC_OUTS_B3_7", - "MONITOR_BLOCK_OUTS_B1_8", - "MONITOR_EE4BEG2_4", - "MONITOR_IMUX44_2", - "MONITOR_NE4C3_3", - "MONITOR_WW4END1_0", - "MONITOR_DADDR5", - "MONITOR_LOGIC_OUTS_B13_3", - "MONITOR_WW4END3_5", - "MONITOR_IMUX2_8", - "MONITOR_LOGIC_OUTS_B0_1", - "MONITOR_LOGIC_OUTS_B14_7", - "MONITOR_SW2A0_6", - "MONITOR_BYP2_8", - "MONITOR_NW4END0_7", - "MONITOR_WR1END3_5", - "MONITOR_EE2BEG3_4", - "MONITOR_SW4A0_8", - "MONITOR_WL1END3_5", - "MONITOR_SW4END0_0", - "MONITOR_LH5_2", - "MONITOR_EE4BEG2_7", - "MONITOR_LH8_3", - "MONITOR_NW4A1_3", - "MONITOR_EE4B3_3", - "MONITOR_EE4BEG1_5", - "MONITOR_NW4END0_0", - "MONITOR_EE2BEG1_0", - "MONITOR_IMUX11_2", - "MONITOR_WW4END0_8", - "MONITOR_NW4A3_5", - "MONITOR_EE4BEG3_7", - "MONITOR_FAN7_0", - "MONITOR_BYP2_3", - "MONITOR_EE4A0_6", - "MONITOR_TESTADCOUT14", - "MONITOR_BYP4_3", - "MONITOR_SE4BEG3_2", - "MONITOR_WW4A2_7", - "MONITOR_IMUX20_9", - "MONITOR_FAN0_3", - "MONITOR_IMUX7_9", - "MONITOR_VERT_VAUXN15", - "MONITOR_LOGIC_OUTS_B16_9", - "MONITOR_LOGIC_OUTS_B4_1", - "MONITOR_VERT_VAUXP0", - "MONITOR_IMUX9_5", - "MONITOR_EE2A2_0", - "MONITOR_NW4END3_0", - "MONITOR_VAUXN4", - "MONITOR_TESTDB2", - "MONITOR_CTRL1_0", - "MONITOR_IMUX5_4", - "MONITOR_IMUX11_4", - "MONITOR_IMUX2_6", - "MONITOR_EE2BEG3_8", - "MONITOR_EL1BEG3_5", - "MONITOR_ER1BEG3_0", - "MONITOR_EE2A2_1", - "MONITOR_IMUX43_7", - "MONITOR_DI2", - "MONITOR_WW4C1_9", - "MONITOR_IMUX45_4", - "MONITOR_LH3_4", - "MONITOR_NE2A0_2", - "MONITOR_EE4B2_0", - "MONITOR_TESTSCANRESET", - "MONITOR_SE4C3_6", - "MONITOR_WW4END1_2", - "MONITOR_SE4C1_0", - "MONITOR_IMUX25_1", - "MONITOR_VERT_VAUXN10", - "MONITOR_NE2A1_1", - "MONITOR_SW2A1_0", - "MONITOR_SE2A2_1", - "MONITOR_SW4A1_1", - "MONITOR_LOGIC_OUTS_B9_8", - "MONITOR_TESTUPDATE", - "MONITOR_LOGIC_OUTS_B8_7", - "MONITOR_SW4END3_9", - "MONITOR_SW4END0_3", - "MONITOR_EE4C1_2", - "MONITOR_EL1BEG0_6", - "MONITOR_EE4A3_2", - "MONITOR_LH5_0", - "MONITOR_SW4A3_4", - "MONITOR_IMUX31_6", - "MONITOR_IMUX17_5", - "MONITOR_IMUX34_3", - "MONITOR_SE4BEG3_0", - "MONITOR_FAN7_1", - "MONITOR_LH10_5", - "MONITOR_LH7_5", - "MONITOR_MUXADDR2", - "MONITOR_LOGIC_OUTS_B1_6", - "MONITOR_IMUX3_7", - "MONITOR_DEN", - "MONITOR_WW4END3_6", - "MONITOR_SW4END2_6", - "MONITOR_LOGIC_OUTS_B14_0", - "MONITOR_WW2A0_5", - "MONITOR_TESTADCIN28", - "MONITOR_LH2_5", - "MONITOR_SW2A2_0", - "MONITOR_VERT_VAUXN2", - "MONITOR_SE2A2_3", - "MONITOR_IMUX30_1", - "MONITOR_IMUX28_5", - "MONITOR_SE2A3_9", - "MONITOR_EE2A0_4", - "MONITOR_EE2BEG2_2", - "MONITOR_WW4B1_1", - "MONITOR_EL1BEG0_2", - "MONITOR_ER1BEG0_7", - "MONITOR_LOGIC_OUTS_B23_1", - "MONITOR_NW4END0_5", - "MONITOR_WL1END2_3", - "MONITOR_WW4END0_5", - "MONITOR_WW2A3_2", - "MONITOR_BYP1_5", - "MONITOR_WW4C1_6", - "MONITOR_VAUXP12", - "MONITOR_LH4_7", - "MONITOR_VAUXN2", - "MONITOR_LOGIC_OUTS_B23_8", - "MONITOR_DI7", - "MONITOR_WL1END0_1", - "MONITOR_TESTADCIN17", - "MONITOR_TESTADCIN3", - "MONITOR_IMUX45_7", - "MONITOR_FAN6_9", - "MONITOR_EE2BEG0_1", - "MONITOR_SE4BEG2_5", - "MONITOR_TESTDB11", - "MONITOR_LOGIC_OUTS_B20_5", - "MONITOR_WW4A1_4", - "MONITOR_ER1BEG3_9", - "MONITOR_CTRL0_7", - "MONITOR_WW4C3_2", - "MONITOR_SE4BEG0_9", - "MONITOR_EE4B1_9", - "MONITOR_LH1_4", - "MONITOR_EE4B0_9", - "MONITOR_LOGIC_OUTS_B10_6", - "MONITOR_LH1_1", - "MONITOR_SE2A1_7", - "MONITOR_IMUX46_0", - "MONITOR_FAN4_0", - "MONITOR_LOGIC_OUTS_B7_0", - "MONITOR_EL1BEG1_4", - "MONITOR_CLK1_4", - "MONITOR_BLOCK_OUTS_B2_7", - "MONITOR_IMUX28_1", - "MONITOR_VAUXP9", - "MONITOR_LOGIC_OUTS_B20_0", - "MONITOR_IMUX10_9", - "MONITOR_NE4C3_6", - "MONITOR_NE4BEG0_7", - "MONITOR_IMUX11_7", - "MONITOR_LOGIC_OUTS_B4_9", - "MONITOR_IMUX34_5", - "MONITOR_WW4END0_6", - "MONITOR_IMUX4_5", - "MONITOR_IMUX19_1", - "MONITOR_BYP6_7", - "MONITOR_FAN3_6", - "MONITOR_SE4BEG1_4", - "MONITOR_SE4C0_8" - ], - "sites": [ - { - "prefix": "IPAD", - "y_coord": 1, - "type": "IPAD", - "site_pins": { - "O": "MONITOR_SEG_VN" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "IPAD", - "y_coord": 0, - "type": "IPAD", - "site_pins": { - "O": "MONITOR_SEG_VP" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "XADC", - "y_coord": 0, - "type": "XADC", - "site_pins": { - "VAUXP8": "MONITOR_VAUXP8", - "VP": "MONITOR_VP", - "DI10": "MONITOR_DI10", - "TESTSCANMODE2": "MONITOR_TESTSCANMODE2", - "MUXADDR2": "MONITOR_MUXADDR2", - "DO8": "MONITOR_DO8", - "DADDR0": "MONITOR_DADDR0", - "ALM6": "MONITOR_ALM6", - "TESTADCIN0": "MONITOR_TESTADCIN0", - "TESTENJTAG": "MONITOR_TESTENJTAG", - "DI1": "MONITOR_DI1", - "TESTADCOUT10": "MONITOR_TESTADCOUT10", - "TESTDB15": "MONITOR_TESTDB15", - "TESTADCOUT7": "MONITOR_TESTADCOUT7", - "TESTADCIN20": "MONITOR_TESTADCIN20", - "TESTADCIN2": "MONITOR_TESTADCIN2", - "TESTADCIN23": "MONITOR_TESTADCIN23", - "VAUXP2": "MONITOR_VAUXP2", - "VAUXN1": "MONITOR_VAUXN1", - "TESTADCOUT19": "MONITOR_TESTADCOUT19", - "DADDR5": "MONITOR_DADDR5", - "TESTADCIN214": "MONITOR_TESTADCIN214", - "DO15": "MONITOR_DO15", - "DI8": "MONITOR_DI8", - "DI15": "MONITOR_DI15", - "DI13": "MONITOR_DI13", - "TESTDB2": "MONITOR_TESTDB2", - "TESTADCIN12": "MONITOR_TESTADCIN12", - "TESTADCIN21": "MONITOR_TESTADCIN21", - "TESTSCANMODE4": "MONITOR_TESTSCANMODE4", - "TESTADCOUT2": "MONITOR_TESTADCOUT2", - "CHANNEL2": "MONITOR_CHANNEL2", - "TESTADCIN18": "MONITOR_TESTADCIN18", - "VAUXN11": "MONITOR_VAUXN11", - "VAUXP1": "MONITOR_VAUXP1", - "CONVST": "MONITOR_CONVST", - "TESTSI2": "MONITOR_TESTSI2", - "TESTADCIN27": "MONITOR_TESTADCIN27", - "TESTADCIN6": "MONITOR_TESTADCIN6", - "VAUXP14": "MONITOR_VAUXP14", - "TESTADCIN215": "MONITOR_TESTADCIN215", - "TESTADCOUT14": "MONITOR_TESTADCOUT14", - "TESTSE0": "MONITOR_TESTSE0", - "TESTDB6": "MONITOR_TESTDB6", - "VAUXN15": "MONITOR_VAUXN15", - "BUSY": "MONITOR_BUSY", - "DI3": "MONITOR_DI3", - "DI9": "MONITOR_DI9", - "DEN": "MONITOR_DEN", - "TESTADCOUT1": "MONITOR_TESTADCOUT1", - "TESTADCOUT8": "MONITOR_TESTADCOUT8", - "TESTSE3": "MONITOR_TESTSE3", - "TESTSE1": "MONITOR_TESTSE1", - "VAUXN12": "MONITOR_VAUXN12", - "TESTADCOUT0": "MONITOR_TESTADCOUT0", - "TESTDB13": "MONITOR_TESTDB13", - "DO10": "MONITOR_DO10", - "MUXADDR1": "MONITOR_MUXADDR1", - "VAUXP0": "MONITOR_VAUXP0", - "VAUXP15": "MONITOR_VAUXP15", - "TESTADCOUT17": "MONITOR_TESTADCOUT17", - "DO11": "MONITOR_DO11", - "VAUXN5": "MONITOR_VAUXN5", - "DI11": "MONITOR_DI11", - "TESTADCIN26": "MONITOR_TESTADCIN26", - "TESTSCANMODE3": "MONITOR_TESTSCANMODE3", - "VAUXN8": "MONITOR_VAUXN8", - "TESTDB1": "MONITOR_TESTDB1", - "TESTSEL": "MONITOR_TESTSEL", - "TESTSCANMODE0": "MONITOR_TESTSCANMODE0", - "DO6": "MONITOR_DO6", - "VAUXN6": "MONITOR_VAUXN6", - "TESTSE2": "MONITOR_TESTSE2", - "VAUXN3": "MONITOR_VAUXN3", - "TESTADCIN1": "MONITOR_TESTADCIN1", - "TESTADCIN211": "MONITOR_TESTADCIN211", - "TESTADCCLK2": "MONITOR_TESTADCCLK2", - "TESTSCANCLK0": "MONITOR_TESTSCANCLK0", - "DI14": "MONITOR_DI14", - "VAUXN2": "MONITOR_VAUXN2", - "TESTSCANCLK4": "MONITOR_TESTSCANCLK4", - "TESTSHIFT": "MONITOR_TESTSHIFT", - "DADDR6": "MONITOR_DADDR6", - "EOS": "MONITOR_EOS", - "DADDR4": "MONITOR_DADDR4", - "TESTDB4": "MONITOR_TESTDB4", - "DADDR1": "MONITOR_DADDR1", - "TESTSCANCLK2": "MONITOR_TESTSCANCLK2", - "VAUXP9": "MONITOR_VAUXP9", - "DO7": "MONITOR_DO7", - "VAUXN4": "MONITOR_VAUXN4", - "VAUXN13": "MONITOR_VAUXN13", - "TESTDB7": "MONITOR_TESTDB7", - "TESTADCIN8": "MONITOR_TESTADCIN8", - "ALM7": "MONITOR_ALM7", - "TESTSCANMODE1": "MONITOR_TESTSCANMODE1", - "VAUXP12": "MONITOR_VAUXP12", - "DI0": "MONITOR_DI0", - "MUXADDR4": "MONITOR_MUXADDR4", - "TESTDB3": "MONITOR_TESTDB3", - "CONVSTCLK": "MONITOR_CONVSTCLK", - "TESTADCIN13": "MONITOR_TESTADCIN13", - "VAUXN14": "MONITOR_VAUXN14", - "TESTTDO": "MONITOR_TESTTDO", - "TESTSO0": "MONITOR_TESTSO0", - "TESTADCIN218": "MONITOR_TESTADCIN218", - "TESTADCIN3": "MONITOR_TESTADCIN3", - "TESTADCIN5": "MONITOR_TESTADCIN5", - "DO3": "MONITOR_DO3", - "DO4": "MONITOR_DO4", - "TESTDB10": "MONITOR_TESTDB10", - "TESTADCCLK0": "MONITOR_TESTADCCLK0", - "VAUXP3": "MONITOR_VAUXP3", - "TESTADCOUT13": "MONITOR_TESTADCOUT13", - "DI2": "MONITOR_DI2", - "VAUXP7": "MONITOR_VAUXP7", - "DRDY": "MONITOR_DRDY", - "DCLK": "MONITOR_DCLK", - "CHANNEL3": "MONITOR_CHANNEL3", - "DI7": "MONITOR_DI7", - "TESTADCIN19": "MONITOR_TESTADCIN19", - "DO0": "MONITOR_DO0", - "TESTADCOUT18": "MONITOR_TESTADCOUT18", - "DI4": "MONITOR_DI4", - "VN": "MONITOR_VN", - "TESTSO4": "MONITOR_TESTSO4", - "TESTSE4": "MONITOR_TESTSE4", - "CHANNEL4": "MONITOR_CHANNEL4", - "TESTADCIN14": "MONITOR_TESTADCIN14", - "TESTADCIN29": "MONITOR_TESTADCIN29", - "TESTSI4": "MONITOR_TESTSI4", - "TESTADCOUT6": "MONITOR_TESTADCOUT6", - "VAUXP13": "MONITOR_VAUXP13", - "JTAGBUSY": "MONITOR_JTAGBUSY", - "VAUXP10": "MONITOR_VAUXP10", - "VAUXN7": "MONITOR_VAUXN7", - "TESTRST": "MONITOR_TESTRST", - "TESTADCOUT12": "MONITOR_TESTADCOUT12", - "DO2": "MONITOR_DO2", - "DO1": "MONITOR_DO1", - "ALM1": "MONITOR_ALM1", - "DO5": "MONITOR_DO5", - "DI6": "MONITOR_DI6", - "TESTADCIN210": "MONITOR_TESTADCIN210", - "ALM0": "MONITOR_ALM0", - "TESTADCOUT4": "MONITOR_TESTADCOUT4", - "DADDR3": "MONITOR_DADDR3", - "TESTADCIN10": "MONITOR_TESTADCIN10", - "TESTADCCLK1": "MONITOR_TESTADCCLK1", - "MUXADDR3": "MONITOR_MUXADDR3", - "TESTSI3": "MONITOR_TESTSI3", - "TESTADCCLK3": "MONITOR_TESTADCCLK3", - "DWE": "MONITOR_DWE", - "MUXADDR0": "MONITOR_MUXADDR0", - "TESTSO3": "MONITOR_TESTSO3", - "TESTADCIN4": "MONITOR_TESTADCIN4", - "JTAGMODIFIED": "MONITOR_JTAGMODIFIED", - "DI12": "MONITOR_DI12", - "DI5": "MONITOR_DI5", - "TESTADCOUT3": "MONITOR_TESTADCOUT3", - "ALM2": "MONITOR_ALM2", - "VAUXN0": "MONITOR_VAUXN0", - "TESTSO2": "MONITOR_TESTSO2", - "TESTADCIN17": "MONITOR_TESTADCIN17", - "OT": "MONITOR_OT", - "EOC": "MONITOR_EOC", - "TESTADCOUT5": "MONITOR_TESTADCOUT5", - "TESTDB0": "MONITOR_TESTDB0", - "TESTADCIN217": "MONITOR_TESTADCIN217", - "TESTADCOUT16": "MONITOR_TESTADCOUT16", - "TESTTDI": "MONITOR_TESTTDI", - "TESTDB14": "MONITOR_TESTDB14", - "TESTADCIN216": "MONITOR_TESTADCIN216", - "DO12": "MONITOR_DO12", - "TESTADCIN15": "MONITOR_TESTADCIN15", - "TESTADCIN28": "MONITOR_TESTADCIN28", - "VAUXP11": "MONITOR_VAUXP11", - "TESTADCOUT9": "MONITOR_TESTADCOUT9", - "DO14": "MONITOR_DO14", - "TESTADCIN24": "MONITOR_TESTADCIN24", - "VAUXP4": "MONITOR_VAUXP4", - "TESTDB5": "MONITOR_TESTDB5", - "TESTSCANRESET": "MONITOR_TESTSCANRESET", - "TESTDRCK": "MONITOR_TESTDRCK", - "TESTCAPTURE": "MONITOR_TESTCAPTURE", - "TESTADCIN9": "MONITOR_TESTADCIN9", - "TESTDB8": "MONITOR_TESTDB8", - "TESTSI1": "MONITOR_TESTSI1", - "VAUXN10": "MONITOR_VAUXN10", - "CHANNEL1": "MONITOR_CHANNEL1", - "VAUXN9": "MONITOR_VAUXN9", - "TESTUPDATE": "MONITOR_TESTUPDATE", - "JTAGLOCKED": "MONITOR_JTAGLOCKED", - "ALM5": "MONITOR_ALM5", - "TESTADCIN219": "MONITOR_TESTADCIN219", - "TESTDB11": "MONITOR_TESTDB11", - "TESTDB12": "MONITOR_TESTDB12", - "VAUXP6": "MONITOR_VAUXP6", - "CHANNEL0": "MONITOR_CHANNEL0", - "TESTDB9": "MONITOR_TESTDB9", - "ALM3": "MONITOR_ALM3", - "ALM4": "MONITOR_ALM4", - "TESTSCANCLK1": "MONITOR_TESTSCANCLK1", - "VAUXP5": "MONITOR_VAUXP5", - "TESTSCANCLK3": "MONITOR_TESTSCANCLK3", - "TESTADCIN11": "MONITOR_TESTADCIN11", - "DO9": "MONITOR_DO9", - "TESTADCOUT15": "MONITOR_TESTADCOUT15", - "TESTADCIN22": "MONITOR_TESTADCIN22", - "TESTADCIN212": "MONITOR_TESTADCIN212", - "TESTADCIN7": "MONITOR_TESTADCIN7", - "TESTADCIN25": "MONITOR_TESTADCIN25", - "TESTSI0": "MONITOR_TESTSI0", - "TESTADCIN213": "MONITOR_TESTADCIN213", - "DADDR2": "MONITOR_DADDR2", - "TESTADCIN16": "MONITOR_TESTADCIN16", - "DO13": "MONITOR_DO13", - "RESET": "MONITOR_RESET", - "TESTADCOUT11": "MONITOR_TESTADCOUT11", - "TESTSO1": "MONITOR_TESTSO1" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "MONITOR_BOT.MONITOR_EOC->MONITOR_LOGIC_OUTS_B22_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B22_1", - "is_directional": "1", - "src_wire": "MONITOR_EOC", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_ALM6->MONITOR_LOGIC_OUTS_B17_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B17_2", - "is_directional": "1", - "src_wire": "MONITOR_ALM6", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP5->MONITOR_VAUXP5": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP5", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP5", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO2->MONITOR_LOGIC_OUTS_B10_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B10_0", - "is_directional": "1", - "src_wire": "MONITOR_DO2", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_CHANNEL0->MONITOR_LOGIC_OUTS_B15_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B15_1", - "is_directional": "1", - "src_wire": "MONITOR_CHANNEL0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX39_0->MONITOR_DI11": { - "can_invert": "0", - "dst_wire": "MONITOR_DI11", - "is_directional": "1", - "src_wire": "MONITOR_IMUX39_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DRDY->MONITOR_LOGIC_OUTS_B14_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B14_1", - "is_directional": "1", - "src_wire": "MONITOR_DRDY", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_CHANNEL1->MONITOR_LOGIC_OUTS_B16_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B16_1", - "is_directional": "1", - "src_wire": "MONITOR_CHANNEL1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX41_0->MONITOR_DI13": { - "can_invert": "0", - "dst_wire": "MONITOR_DI13", - "is_directional": "1", - "src_wire": "MONITOR_IMUX41_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_CLK1_0->MONITOR_DCLK": { - "can_invert": "0", - "dst_wire": "MONITOR_DCLK", - "is_directional": "1", - "src_wire": "MONITOR_CLK1_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX37_0->MONITOR_DI9": { - "can_invert": "0", - "dst_wire": "MONITOR_DI9", - "is_directional": "1", - "src_wire": "MONITOR_IMUX37_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN1->MONITOR_VAUXN1": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN1", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX35_1->MONITOR_DADDR1": { - "can_invert": "0", - "dst_wire": "MONITOR_DADDR1", - "is_directional": "1", - "src_wire": "MONITOR_IMUX35_1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN2->MONITOR_VAUXN2": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN2", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN2", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX41_1->MONITOR_DEN": { - "can_invert": "0", - "dst_wire": "MONITOR_DEN", - "is_directional": "1", - "src_wire": "MONITOR_IMUX41_1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP4->MONITOR_VAUXP4": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP4", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP4", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXN10->MONITOR_VERT_VAUXN10": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN10", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN10", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX39_1->MONITOR_DADDR5": { - "can_invert": "0", - "dst_wire": "MONITOR_DADDR5", - "is_directional": "1", - "src_wire": "MONITOR_IMUX39_1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX29_0->MONITOR_DI1": { - "can_invert": "0", - "dst_wire": "MONITOR_DI1", - "is_directional": "1", - "src_wire": "MONITOR_IMUX29_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_MUXADDR1->MONITOR_LOGIC_OUTS_B20_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B20_2", - "is_directional": "1", - "src_wire": "MONITOR_MUXADDR1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO4->MONITOR_LOGIC_OUTS_B12_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B12_0", - "is_directional": "1", - "src_wire": "MONITOR_DO4", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXN3->MONITOR_VERT_VAUXN3": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN3", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN3", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_CHANNEL2->MONITOR_LOGIC_OUTS_B17_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B17_1", - "is_directional": "1", - "src_wire": "MONITOR_CHANNEL2", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO8->MONITOR_LOGIC_OUTS_B16_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B16_0", - "is_directional": "1", - "src_wire": "MONITOR_DO8", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_SEG_VN->MONITOR_VN": { - "can_invert": "0", - "dst_wire": "MONITOR_VN", - "is_directional": "1", - "src_wire": "MONITOR_SEG_VN", - "is_pseudo": "0" - }, "MONITOR_BOT.MONITOR_IMUX28_0->MONITOR_DI0": { "can_invert": "0", - "dst_wire": "MONITOR_DI0", - "is_directional": "1", "src_wire": "MONITOR_IMUX28_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX34_0->MONITOR_DI6": { - "can_invert": "0", - "dst_wire": "MONITOR_DI6", "is_directional": "1", - "src_wire": "MONITOR_IMUX34_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP3->MONITOR_VAUXP3": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP3", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP3", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO0->MONITOR_LOGIC_OUTS_B8_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B8_0", - "is_directional": "1", - "src_wire": "MONITOR_DO0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXP11->MONITOR_VERT_VAUXP11": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP11", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP11", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX43_1->MONITOR_CONVST": { - "can_invert": "0", - "dst_wire": "MONITOR_CONVST", - "is_directional": "1", - "src_wire": "MONITOR_IMUX43_1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN15->MONITOR_VAUXN15": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN15", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN15", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_BUSY->MONITOR_LOGIC_OUTS_B20_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B20_1", - "is_directional": "1", - "src_wire": "MONITOR_BUSY", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN11->MONITOR_VAUXN11": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN11", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN11", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX40_1->MONITOR_DADDR6": { - "can_invert": "0", - "dst_wire": "MONITOR_DADDR6", - "is_directional": "1", - "src_wire": "MONITOR_IMUX40_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_DI0" }, "MONITOR_BOT.MONITOR_HORIZ_VAUXN14->MONITOR_VERT_VAUXN14": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN14", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXN14", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN10->MONITOR_VAUXN10": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN10", "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN10", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXP14->MONITOR_VERT_VAUXP14": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP14", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP14", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX38_0->MONITOR_DI10": { - "can_invert": "0", - "dst_wire": "MONITOR_DI10", - "is_directional": "1", - "src_wire": "MONITOR_IMUX38_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP0->MONITOR_VAUXP0": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP0", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN0->MONITOR_VAUXN0": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN0", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXN11->MONITOR_VERT_VAUXN11": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN11", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN11", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN12->MONITOR_VAUXN12": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN12", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN12", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX42_1->MONITOR_DWE": { - "can_invert": "0", - "dst_wire": "MONITOR_DWE", - "is_directional": "1", - "src_wire": "MONITOR_IMUX42_1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX34_1->MONITOR_DADDR0": { - "can_invert": "0", - "dst_wire": "MONITOR_DADDR0", - "is_directional": "1", - "src_wire": "MONITOR_IMUX34_1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX33_0->MONITOR_DI5": { - "can_invert": "0", - "dst_wire": "MONITOR_DI5", - "is_directional": "1", - "src_wire": "MONITOR_IMUX33_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO9->MONITOR_LOGIC_OUTS_B17_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B17_0", - "is_directional": "1", - "src_wire": "MONITOR_DO9", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_ALM5->MONITOR_LOGIC_OUTS_B16_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B16_2", - "is_directional": "1", - "src_wire": "MONITOR_ALM5", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP10->MONITOR_VAUXP10": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP10", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN14" }, "MONITOR_BOT.MONITOR_VERT_VAUXP8->MONITOR_VAUXP8": { "can_invert": "0", - "dst_wire": "MONITOR_VAUXP8", - "is_directional": "1", "src_wire": "MONITOR_VERT_VAUXP8", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_CHANNEL4->MONITOR_LOGIC_OUTS_B19_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B19_1", "is_directional": "1", - "src_wire": "MONITOR_CHANNEL4", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP11->MONITOR_VAUXP11": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP11", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP11", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP2->MONITOR_VAUXP2": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP2", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP2", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP12->MONITOR_VAUXP12": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP12", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP12", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_CLK1_1->MONITOR_CONVSTCLK": { - "can_invert": "0", - "dst_wire": "MONITOR_CONVSTCLK", - "is_directional": "1", - "src_wire": "MONITOR_CLK1_1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP9->MONITOR_VAUXP9": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP9", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP9", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN13->MONITOR_VAUXN13": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN13", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN13", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX38_1->MONITOR_DADDR4": { - "can_invert": "0", - "dst_wire": "MONITOR_DADDR4", - "is_directional": "1", - "src_wire": "MONITOR_IMUX38_1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXN15->MONITOR_VERT_VAUXN15": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN15", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN15", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN7->MONITOR_VAUXN7": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN7", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN7", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP7->MONITOR_VAUXP7": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP7", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP7", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO10->MONITOR_LOGIC_OUTS_B18_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B18_0", - "is_directional": "1", - "src_wire": "MONITOR_DO10", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_ALM4->MONITOR_LOGIC_OUTS_B15_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B15_2", - "is_directional": "1", - "src_wire": "MONITOR_ALM4", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXN7->MONITOR_VERT_VAUXN7": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN7", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN7", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_MUXADDR3->MONITOR_LOGIC_OUTS_B22_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B22_2", - "is_directional": "1", - "src_wire": "MONITOR_MUXADDR3", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN5->MONITOR_VAUXN5": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN5", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN5", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_OT->MONITOR_LOGIC_OUTS_B21_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B21_1", - "is_directional": "1", - "src_wire": "MONITOR_OT", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN3->MONITOR_VAUXN3": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN3", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN3", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_MUXADDR0->MONITOR_LOGIC_OUTS_B19_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B19_2", - "is_directional": "1", - "src_wire": "MONITOR_MUXADDR0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP13->MONITOR_VAUXP13": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP13", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP13", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP15->MONITOR_VAUXP15": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP15", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP15", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXP3->MONITOR_VERT_VAUXP3": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP3", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP3", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_SEG_VP->MONITOR_VP": { - "can_invert": "0", - "dst_wire": "MONITOR_VP", - "is_directional": "1", - "src_wire": "MONITOR_SEG_VP", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX43_0->MONITOR_DI15": { - "can_invert": "0", - "dst_wire": "MONITOR_DI15", - "is_directional": "1", - "src_wire": "MONITOR_IMUX43_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_EOS->MONITOR_LOGIC_OUTS_B23_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B23_1", - "is_directional": "1", - "src_wire": "MONITOR_EOS", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP14->MONITOR_VAUXP14": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP14", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP14", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN4->MONITOR_VAUXN4": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN4", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN4", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO6->MONITOR_LOGIC_OUTS_B14_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B14_0", - "is_directional": "1", - "src_wire": "MONITOR_DO6", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN9->MONITOR_VAUXN9": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN9", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN9", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_ALM0->MONITOR_LOGIC_OUTS_B11_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B11_2", - "is_directional": "1", - "src_wire": "MONITOR_ALM0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXP10->MONITOR_VERT_VAUXP10": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP10", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP10", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO12->MONITOR_LOGIC_OUTS_B20_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B20_0", - "is_directional": "1", - "src_wire": "MONITOR_DO12", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX30_0->MONITOR_DI2": { - "can_invert": "0", - "dst_wire": "MONITOR_DI2", - "is_directional": "1", - "src_wire": "MONITOR_IMUX30_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_JTAGBUSY->MONITOR_LOGIC_OUTS_B13_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B13_1", - "is_directional": "1", - "src_wire": "MONITOR_JTAGBUSY", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX32_0->MONITOR_DI4": { - "can_invert": "0", - "dst_wire": "MONITOR_DI4", - "is_directional": "1", - "src_wire": "MONITOR_IMUX32_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX35_0->MONITOR_DI7": { - "can_invert": "0", - "dst_wire": "MONITOR_DI7", - "is_directional": "1", - "src_wire": "MONITOR_IMUX35_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO14->MONITOR_LOGIC_OUTS_B22_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B22_0", - "is_directional": "1", - "src_wire": "MONITOR_DO14", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO1->MONITOR_LOGIC_OUTS_B9_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B9_0", - "is_directional": "1", - "src_wire": "MONITOR_DO1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_CHANNEL3->MONITOR_LOGIC_OUTS_B18_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B18_1", - "is_directional": "1", - "src_wire": "MONITOR_CHANNEL3", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP1->MONITOR_VAUXP1": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP1", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXP6->MONITOR_VAUXP6": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXP6", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXP6", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO15->MONITOR_LOGIC_OUTS_B23_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B23_0", - "is_directional": "1", - "src_wire": "MONITOR_DO15", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_ALM1->MONITOR_LOGIC_OUTS_B12_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B12_2", - "is_directional": "1", - "src_wire": "MONITOR_ALM1", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_MUXADDR2->MONITOR_LOGIC_OUTS_B21_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B21_2", - "is_directional": "1", - "src_wire": "MONITOR_MUXADDR2", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN6->MONITOR_VAUXN6": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN6", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN6", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX36_0->MONITOR_DI8": { - "can_invert": "0", - "dst_wire": "MONITOR_DI8", - "is_directional": "1", - "src_wire": "MONITOR_IMUX36_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_MUXADDR4->MONITOR_LOGIC_OUTS_B23_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B23_2", - "is_directional": "1", - "src_wire": "MONITOR_MUXADDR4", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO5->MONITOR_LOGIC_OUTS_B13_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B13_0", - "is_directional": "1", - "src_wire": "MONITOR_DO5", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_HORIZ_VAUXP7->MONITOR_VERT_VAUXP7": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP7", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP7", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_JTAGMODIFIED->MONITOR_LOGIC_OUTS_B12_1": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B12_1", - "is_directional": "1", - "src_wire": "MONITOR_JTAGMODIFIED", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO13->MONITOR_LOGIC_OUTS_B21_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B21_0", - "is_directional": "1", - "src_wire": "MONITOR_DO13", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_ALM3->MONITOR_LOGIC_OUTS_B14_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B14_2", - "is_directional": "1", - "src_wire": "MONITOR_ALM3", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO3->MONITOR_LOGIC_OUTS_B11_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B11_0", - "is_directional": "1", - "src_wire": "MONITOR_DO3", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN14->MONITOR_VAUXN14": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN14", - "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN14", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX40_0->MONITOR_DI12": { - "can_invert": "0", - "dst_wire": "MONITOR_DI12", - "is_directional": "1", - "src_wire": "MONITOR_IMUX40_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX31_0->MONITOR_DI3": { - "can_invert": "0", - "dst_wire": "MONITOR_DI3", - "is_directional": "1", - "src_wire": "MONITOR_IMUX31_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_DO7->MONITOR_LOGIC_OUTS_B15_0": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B15_0", - "is_directional": "1", - "src_wire": "MONITOR_DO7", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX42_0->MONITOR_DI14": { - "can_invert": "0", - "dst_wire": "MONITOR_DI14", - "is_directional": "1", - "src_wire": "MONITOR_IMUX42_0", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_IMUX36_1->MONITOR_DADDR2": { - "can_invert": "0", - "dst_wire": "MONITOR_DADDR2", - "is_directional": "1", - "src_wire": "MONITOR_IMUX36_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP8" }, "MONITOR_BOT.MONITOR_ALM2->MONITOR_LOGIC_OUTS_B13_2": { "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B13_2", - "is_directional": "1", "src_wire": "MONITOR_ALM2", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_VERT_VAUXN8->MONITOR_VAUXN8": { - "can_invert": "0", - "dst_wire": "MONITOR_VAUXN8", "is_directional": "1", - "src_wire": "MONITOR_VERT_VAUXN8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B13_2" }, - "MONITOR_BOT.MONITOR_IMUX37_1->MONITOR_DADDR3": { + "MONITOR_BOT.MONITOR_VERT_VAUXP5->MONITOR_VAUXP5": { "can_invert": "0", - "dst_wire": "MONITOR_DADDR3", + "src_wire": "MONITOR_VERT_VAUXP5", "is_directional": "1", - "src_wire": "MONITOR_IMUX37_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP5" }, - "MONITOR_BOT.MONITOR_DO11->MONITOR_LOGIC_OUTS_B19_0": { + "MONITOR_BOT.MONITOR_BUSY->MONITOR_LOGIC_OUTS_B20_1": { "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B19_0", + "src_wire": "MONITOR_BUSY", "is_directional": "1", - "src_wire": "MONITOR_DO11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B20_1" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN3->MONITOR_VAUXN3": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN3" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP7->MONITOR_VAUXP7": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP7" + }, + "MONITOR_BOT.MONITOR_DO3->MONITOR_LOGIC_OUTS_B11_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B11_0" }, "MONITOR_BOT.MONITOR_HORIZ_VAUXP15->MONITOR_VERT_VAUXP15": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP15", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXP15", - "is_pseudo": "0" - }, - "MONITOR_BOT.MONITOR_ALM7->MONITOR_LOGIC_OUTS_B18_2": { - "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B18_2", "is_directional": "1", - "src_wire": "MONITOR_ALM7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP15" + }, + "MONITOR_BOT.MONITOR_IMUX43_0->MONITOR_DI15": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI15" + }, + "MONITOR_BOT.MONITOR_IMUX33_0->MONITOR_DI5": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI5" }, "MONITOR_BOT.MONITOR_JTAGLOCKED->MONITOR_LOGIC_OUTS_B11_1": { "can_invert": "0", - "dst_wire": "MONITOR_LOGIC_OUTS_B11_1", - "is_directional": "1", "src_wire": "MONITOR_JTAGLOCKED", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B11_1" + }, + "MONITOR_BOT.MONITOR_EOC->MONITOR_LOGIC_OUTS_B22_1": { + "can_invert": "0", + "src_wire": "MONITOR_EOC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B22_1" + }, + "MONITOR_BOT.MONITOR_CHANNEL1->MONITOR_LOGIC_OUTS_B16_1": { + "can_invert": "0", + "src_wire": "MONITOR_CHANNEL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B16_1" + }, + "MONITOR_BOT.MONITOR_DO15->MONITOR_LOGIC_OUTS_B23_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B23_0" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP11->MONITOR_VAUXP11": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP11" + }, + "MONITOR_BOT.MONITOR_IMUX34_1->MONITOR_DADDR0": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR0" + }, + "MONITOR_BOT.MONITOR_DO7->MONITOR_LOGIC_OUTS_B15_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B15_0" + }, + "MONITOR_BOT.MONITOR_MUXADDR0->MONITOR_LOGIC_OUTS_B19_2": { + "can_invert": "0", + "src_wire": "MONITOR_MUXADDR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B19_2" + }, + "MONITOR_BOT.MONITOR_OT->MONITOR_LOGIC_OUTS_B21_1": { + "can_invert": "0", + "src_wire": "MONITOR_OT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B21_1" + }, + "MONITOR_BOT.MONITOR_SEG_VP->MONITOR_VP": { + "can_invert": "0", + "src_wire": "MONITOR_SEG_VP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VP" + }, + "MONITOR_BOT.MONITOR_CHANNEL0->MONITOR_LOGIC_OUTS_B15_1": { + "can_invert": "0", + "src_wire": "MONITOR_CHANNEL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B15_1" + }, + "MONITOR_BOT.MONITOR_DO2->MONITOR_LOGIC_OUTS_B10_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B10_0" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP9->MONITOR_VAUXP9": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP9" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP13->MONITOR_VAUXP13": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP13" + }, + "MONITOR_BOT.MONITOR_MUXADDR1->MONITOR_LOGIC_OUTS_B20_2": { + "can_invert": "0", + "src_wire": "MONITOR_MUXADDR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B20_2" + }, + "MONITOR_BOT.MONITOR_IMUX38_1->MONITOR_DADDR4": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR4" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP4->MONITOR_VAUXP4": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP4" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXN7->MONITOR_VERT_VAUXN7": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN7" + }, + "MONITOR_BOT.MONITOR_DO11->MONITOR_LOGIC_OUTS_B19_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B19_0" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXP3->MONITOR_VERT_VAUXP3": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP3" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN0->MONITOR_VAUXN0": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN0" + }, + "MONITOR_BOT.MONITOR_IMUX40_0->MONITOR_DI12": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI12" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXN11->MONITOR_VERT_VAUXN11": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN11" + }, + "MONITOR_BOT.MONITOR_IMUX35_0->MONITOR_DI7": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI7" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN8->MONITOR_VAUXN8": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN8" + }, + "MONITOR_BOT.MONITOR_ALM5->MONITOR_LOGIC_OUTS_B16_2": { + "can_invert": "0", + "src_wire": "MONITOR_ALM5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B16_2" + }, + "MONITOR_BOT.MONITOR_IMUX43_1->MONITOR_CONVST": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX43_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_CONVST" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXP10->MONITOR_VERT_VAUXP10": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP10" + }, + "MONITOR_BOT.MONITOR_CHANNEL2->MONITOR_LOGIC_OUTS_B17_1": { + "can_invert": "0", + "src_wire": "MONITOR_CHANNEL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B17_1" + }, + "MONITOR_BOT.MONITOR_EOS->MONITOR_LOGIC_OUTS_B23_1": { + "can_invert": "0", + "src_wire": "MONITOR_EOS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B23_1" + }, + "MONITOR_BOT.MONITOR_IMUX38_0->MONITOR_DI10": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI10" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN6->MONITOR_VAUXN6": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN6" + }, + "MONITOR_BOT.MONITOR_IMUX34_0->MONITOR_DI6": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI6" }, "MONITOR_BOT.MONITOR_CTRL1_2->MONITOR_RESET": { "can_invert": "0", - "dst_wire": "MONITOR_RESET", - "is_directional": "1", "src_wire": "MONITOR_CTRL1_2", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_RESET" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN13->MONITOR_VAUXN13": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN13" + }, + "MONITOR_BOT.MONITOR_IMUX32_0->MONITOR_DI4": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI4" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN4->MONITOR_VAUXN4": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN4" + }, + "MONITOR_BOT.MONITOR_IMUX42_0->MONITOR_DI14": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI14" + }, + "MONITOR_BOT.MONITOR_DO10->MONITOR_LOGIC_OUTS_B18_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B18_0" + }, + "MONITOR_BOT.MONITOR_IMUX36_0->MONITOR_DI8": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI8" + }, + "MONITOR_BOT.MONITOR_DO14->MONITOR_LOGIC_OUTS_B22_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B22_0" + }, + "MONITOR_BOT.MONITOR_DO12->MONITOR_LOGIC_OUTS_B20_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B20_0" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP2->MONITOR_VAUXP2": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP2" + }, + "MONITOR_BOT.MONITOR_JTAGBUSY->MONITOR_LOGIC_OUTS_B13_1": { + "can_invert": "0", + "src_wire": "MONITOR_JTAGBUSY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B13_1" + }, + "MONITOR_BOT.MONITOR_CLK1_1->MONITOR_CONVSTCLK": { + "can_invert": "0", + "src_wire": "MONITOR_CLK1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_CONVSTCLK" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN7->MONITOR_VAUXN7": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN7" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN2->MONITOR_VAUXN2": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN2" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXN10->MONITOR_VERT_VAUXN10": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN10" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP0->MONITOR_VAUXP0": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP0" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXN3->MONITOR_VERT_VAUXN3": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN3" + }, + "MONITOR_BOT.MONITOR_ALM4->MONITOR_LOGIC_OUTS_B15_2": { + "can_invert": "0", + "src_wire": "MONITOR_ALM4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B15_2" + }, + "MONITOR_BOT.MONITOR_IMUX30_0->MONITOR_DI2": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI2" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN15->MONITOR_VAUXN15": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN15" + }, + "MONITOR_BOT.MONITOR_CLK1_0->MONITOR_DCLK": { + "can_invert": "0", + "src_wire": "MONITOR_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DCLK" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP1->MONITOR_VAUXP1": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP1" + }, + "MONITOR_BOT.MONITOR_ALM7->MONITOR_LOGIC_OUTS_B18_2": { + "can_invert": "0", + "src_wire": "MONITOR_ALM7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B18_2" + }, + "MONITOR_BOT.MONITOR_MUXADDR4->MONITOR_LOGIC_OUTS_B23_2": { + "can_invert": "0", + "src_wire": "MONITOR_MUXADDR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B23_2" + }, + "MONITOR_BOT.MONITOR_DO8->MONITOR_LOGIC_OUTS_B16_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B16_0" + }, + "MONITOR_BOT.MONITOR_ALM0->MONITOR_LOGIC_OUTS_B11_2": { + "can_invert": "0", + "src_wire": "MONITOR_ALM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B11_2" + }, + "MONITOR_BOT.MONITOR_DRDY->MONITOR_LOGIC_OUTS_B14_1": { + "can_invert": "0", + "src_wire": "MONITOR_DRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B14_1" + }, + "MONITOR_BOT.MONITOR_IMUX37_1->MONITOR_DADDR3": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX37_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR3" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN12->MONITOR_VAUXN12": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN12" + }, + "MONITOR_BOT.MONITOR_DO1->MONITOR_LOGIC_OUTS_B9_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B9_0" + }, + "MONITOR_BOT.MONITOR_DO0->MONITOR_LOGIC_OUTS_B8_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B8_0" + }, + "MONITOR_BOT.MONITOR_IMUX41_0->MONITOR_DI13": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI13" + }, + "MONITOR_BOT.MONITOR_ALM3->MONITOR_LOGIC_OUTS_B14_2": { + "can_invert": "0", + "src_wire": "MONITOR_ALM3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B14_2" + }, + "MONITOR_BOT.MONITOR_ALM6->MONITOR_LOGIC_OUTS_B17_2": { + "can_invert": "0", + "src_wire": "MONITOR_ALM6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B17_2" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP6->MONITOR_VAUXP6": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP6" + }, + "MONITOR_BOT.MONITOR_CHANNEL3->MONITOR_LOGIC_OUTS_B18_1": { + "can_invert": "0", + "src_wire": "MONITOR_CHANNEL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B18_1" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN9->MONITOR_VAUXN9": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN9" + }, + "MONITOR_BOT.MONITOR_IMUX36_1->MONITOR_DADDR2": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR2" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN10->MONITOR_VAUXN10": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN10" + }, + "MONITOR_BOT.MONITOR_IMUX42_1->MONITOR_DWE": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DWE" + }, + "MONITOR_BOT.MONITOR_IMUX35_1->MONITOR_DADDR1": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR1" + }, + "MONITOR_BOT.MONITOR_IMUX40_1->MONITOR_DADDR6": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR6" + }, + "MONITOR_BOT.MONITOR_IMUX39_0->MONITOR_DI11": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI11" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP15->MONITOR_VAUXP15": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP15" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN1->MONITOR_VAUXN1": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN1" + }, + "MONITOR_BOT.MONITOR_IMUX39_1->MONITOR_DADDR5": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DADDR5" + }, + "MONITOR_BOT.MONITOR_DO4->MONITOR_LOGIC_OUTS_B12_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B12_0" + }, + "MONITOR_BOT.MONITOR_IMUX31_0->MONITOR_DI3": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI3" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP14->MONITOR_VAUXP14": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP14" + }, + "MONITOR_BOT.MONITOR_IMUX41_1->MONITOR_DEN": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DEN" + }, + "MONITOR_BOT.MONITOR_DO9->MONITOR_LOGIC_OUTS_B17_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B17_0" + }, + "MONITOR_BOT.MONITOR_DO5->MONITOR_LOGIC_OUTS_B13_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B13_0" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXP14->MONITOR_VERT_VAUXP14": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP14" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN5->MONITOR_VAUXN5": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN5" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN11->MONITOR_VAUXN11": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN11" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXN14->MONITOR_VAUXN14": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXN14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXN14" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP10->MONITOR_VAUXP10": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP10" + }, + "MONITOR_BOT.MONITOR_IMUX37_0->MONITOR_DI9": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI9" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP12->MONITOR_VAUXP12": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP12" + }, + "MONITOR_BOT.MONITOR_IMUX29_0->MONITOR_DI1": { + "can_invert": "0", + "src_wire": "MONITOR_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_DI1" + }, + "MONITOR_BOT.MONITOR_DO6->MONITOR_LOGIC_OUTS_B14_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B14_0" + }, + "MONITOR_BOT.MONITOR_MUXADDR3->MONITOR_LOGIC_OUTS_B22_2": { + "can_invert": "0", + "src_wire": "MONITOR_MUXADDR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B22_2" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXP11->MONITOR_VERT_VAUXP11": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP11" + }, + "MONITOR_BOT.MONITOR_DO13->MONITOR_LOGIC_OUTS_B21_0": { + "can_invert": "0", + "src_wire": "MONITOR_DO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B21_0" + }, + "MONITOR_BOT.MONITOR_JTAGMODIFIED->MONITOR_LOGIC_OUTS_B12_1": { + "can_invert": "0", + "src_wire": "MONITOR_JTAGMODIFIED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B12_1" + }, + "MONITOR_BOT.MONITOR_MUXADDR2->MONITOR_LOGIC_OUTS_B21_2": { + "can_invert": "0", + "src_wire": "MONITOR_MUXADDR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B21_2" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXN15->MONITOR_VERT_VAUXN15": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN15" + }, + "MONITOR_BOT.MONITOR_SEG_VN->MONITOR_VN": { + "can_invert": "0", + "src_wire": "MONITOR_SEG_VN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VN" + }, + "MONITOR_BOT.MONITOR_ALM1->MONITOR_LOGIC_OUTS_B12_2": { + "can_invert": "0", + "src_wire": "MONITOR_ALM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B12_2" + }, + "MONITOR_BOT.MONITOR_HORIZ_VAUXP7->MONITOR_VERT_VAUXP7": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP7" + }, + "MONITOR_BOT.MONITOR_CHANNEL4->MONITOR_LOGIC_OUTS_B19_1": { + "can_invert": "0", + "src_wire": "MONITOR_CHANNEL4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_LOGIC_OUTS_B19_1" + }, + "MONITOR_BOT.MONITOR_VERT_VAUXP3->MONITOR_VAUXP3": { + "can_invert": "0", + "src_wire": "MONITOR_VERT_VAUXP3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VAUXP3" } }, - "tile_type": "MONITOR_BOT" + "wires": [ + "MONITOR_SW4END3_2", + "MONITOR_WW4B1_3", + "MONITOR_IMUX4_1", + "MONITOR_NW4END2_9", + "MONITOR_FAN0_2", + "MONITOR_WW4END3_0", + "MONITOR_EE2A2_7", + "MONITOR_NE4C3_1", + "MONITOR_LH2_3", + "MONITOR_IMUX23_6", + "MONITOR_LOGIC_OUTS_B19_7", + "MONITOR_CLK0_0", + "MONITOR_IMUX42_3", + "MONITOR_NW2A1_0", + "MONITOR_NW4END1_9", + "MONITOR_SE4BEG3_2", + "MONITOR_IMUX24_0", + "MONITOR_IMUX4_2", + "MONITOR_EE2A0_6", + "MONITOR_IMUX37_3", + "MONITOR_CONVST", + "MONITOR_WW2END3_8", + "MONITOR_LH6_2", + "MONITOR_LOGIC_OUTS_B0_3", + "MONITOR_WW4C1_3", + "MONITOR_IMUX3_9", + "MONITOR_LOGIC_OUTS_B14_6", + "MONITOR_LH4_6", + "MONITOR_LH6_9", + "MONITOR_LOGIC_OUTS_B23_4", + "MONITOR_LOGIC_OUTS_B4_2", + "MONITOR_SW4A2_3", + "MONITOR_NW4A2_1", + "MONITOR_LOGIC_OUTS_B9_6", + "MONITOR_EE4C0_7", + "MONITOR_VAUXN4", + "MONITOR_IMUX6_0", + "MONITOR_MUXADDR4", + "MONITOR_CLK1_5", + "MONITOR_SW4A2_2", + "MONITOR_EE4C2_0", + "MONITOR_LH6_1", + "MONITOR_IMUX35_5", + "MONITOR_BYP7_8", + "MONITOR_WR1END1_2", + "MONITOR_ALM6", + "MONITOR_IMUX32_6", + "MONITOR_BYP6_3", + "MONITOR_LH4_5", + "MONITOR_TESTCAPTURE", + "MONITOR_WW4C2_3", + "MONITOR_FAN3_9", + "MONITOR_HORIZ_VAUXP3", + "MONITOR_LOGIC_OUTS_B16_0", + "MONITOR_IMUX4_0", + "MONITOR_SE4BEG3_6", + "MONITOR_IMUX1_3", + "MONITOR_WW4A0_6", + "MONITOR_VERT_VAUXP7", + "MONITOR_LOGIC_OUTS_B6_6", + "MONITOR_NW2A1_6", + "MONITOR_ALM1", + "MONITOR_HORIZ_VAUXN11", + "MONITOR_IMUX14_3", + "MONITOR_TESTADCOUT4", + "MONITOR_DO3", + "MONITOR_WW4C0_8", + "MONITOR_IMUX41_2", + "MONITOR_IMUX27_0", + "MONITOR_LH10_2", + "MONITOR_IMUX12_3", + "MONITOR_SE4C1_3", + "MONITOR_VAUXN3", + "MONITOR_EE4B2_5", + "MONITOR_DI5", + "MONITOR_SE4BEG0_5", + "MONITOR_WW4B3_4", + "MONITOR_BYP5_6", + "MONITOR_BYP7_6", + "MONITOR_WW4END1_7", + "MONITOR_WR1END1_1", + "MONITOR_EE4BEG1_8", + "MONITOR_NE2A3_8", + "MONITOR_IMUX31_6", + "MONITOR_LOGIC_OUTS_B4_9", + "MONITOR_BLOCK_OUTS_B1_0", + "MONITOR_IMUX41_4", + "MONITOR_NE4BEG2_2", + "MONITOR_BYP5_4", + "MONITOR_NW4A3_6", + "MONITOR_IMUX11_3", + "MONITOR_IMUX20_1", + "MONITOR_NW2A3_7", + "MONITOR_CLK0_5", + "MONITOR_WW4C3_6", + "MONITOR_CTRL1_6", + "MONITOR_EE2BEG0_3", + "MONITOR_IMUX19_3", + "MONITOR_WW2A0_3", + "MONITOR_IMUX5_6", + "MONITOR_BYP0_5", + "MONITOR_WW2A1_4", + "MONITOR_BYP4_4", + "MONITOR_SW2A2_2", + "MONITOR_NW4A2_9", + "MONITOR_SE2A0_2", + "MONITOR_SW4END1_7", + "MONITOR_TESTADCIN7", + "MONITOR_EE4A0_4", + "MONITOR_SE2A3_4", + "MONITOR_WR1END0_4", + "MONITOR_SE4C0_9", + "MONITOR_SE4BEG1_8", + "MONITOR_LOGIC_OUTS_B20_2", + "MONITOR_SE4C2_0", + "MONITOR_TESTADCOUT6", + "MONITOR_HORIZ_VAUXN7", + "MONITOR_EE4B0_4", + "MONITOR_BYP7_9", + "MONITOR_EE4BEG3_9", + "MONITOR_WW4C1_8", + "MONITOR_EE2A1_2", + "MONITOR_IMUX27_1", + "MONITOR_EE2BEG3_6", + "MONITOR_EE4C3_0", + "MONITOR_IMUX18_4", + "MONITOR_EE2BEG2_7", + "MONITOR_EE4A1_7", + "MONITOR_TESTADCIN23", + "MONITOR_WW2A3_1", + "MONITOR_FAN7_5", + "MONITOR_EE2A0_2", + "MONITOR_EE4BEG1_4", + "MONITOR_VERT_VAUXN1", + "MONITOR_SW4A3_6", + "MONITOR_NE4C2_2", + "MONITOR_SW4A1_7", + "MONITOR_FAN1_2", + "MONITOR_BLOCK_OUTS_B0_2", + "MONITOR_IMUX29_1", + "MONITOR_LH4_7", + "MONITOR_IMUX24_8", + "MONITOR_TESTADCIN17", + "MONITOR_FAN1_0", + "MONITOR_IMUX38_7", + "MONITOR_NE4C1_8", + "MONITOR_SW2A1_2", + "MONITOR_LOGIC_OUTS_B1_2", + "MONITOR_IMUX3_8", + "MONITOR_WW4B1_2", + "MONITOR_EE4A3_2", + "MONITOR_IMUX31_1", + "MONITOR_FAN6_9", + "MONITOR_IMUX34_2", + "MONITOR_NE2A3_6", + "MONITOR_SW4A1_9", + "MONITOR_VAUXP9", + "MONITOR_NE2A1_7", + "MONITOR_SE4BEG3_4", + "MONITOR_VP", + "MONITOR_IMUX20_3", + "MONITOR_DO9", + "MONITOR_TESTDB5", + "MONITOR_FAN5_9", + "MONITOR_BYP4_8", + "MONITOR_LOGIC_OUTS_B7_5", + "MONITOR_IMUX25_2", + "MONITOR_LH11_8", + "MONITOR_EE4A3_4", + "MONITOR_SE4C0_5", + "MONITOR_NW4END2_2", + "MONITOR_WL1END2_9", + "MONITOR_TESTADCOUT9", + "MONITOR_LOGIC_OUTS_B7_2", + "MONITOR_WR1END1_8", + "MONITOR_IMUX21_1", + "MONITOR_SE4BEG1_4", + "MONITOR_TESTSI2", + "MONITOR_EL1BEG0_2", + "MONITOR_BLOCK_OUTS_B3_4", + "MONITOR_DO13", + "MONITOR_TESTDB3", + "MONITOR_LOGIC_OUTS_B18_3", + "MONITOR_NW4A2_4", + "MONITOR_LOGIC_OUTS_B21_6", + "MONITOR_IMUX23_4", + "MONITOR_LOGIC_OUTS_B5_5", + "MONITOR_SE2A2_4", + "MONITOR_EE4C2_6", + "MONITOR_EE4C3_3", + "MONITOR_TESTADCIN11", + "MONITOR_IMUX26_9", + "MONITOR_EL1BEG3_8", + "MONITOR_LOGIC_OUTS_B5_4", + "MONITOR_IMUX40_1", + "MONITOR_SW4END3_1", + "MONITOR_SE4C3_3", + "MONITOR_LOGIC_OUTS_B15_4", + "MONITOR_IMUX40_7", + "MONITOR_EE4BEG0_3", + "MONITOR_EE4B1_6", + "MONITOR_LH11_1", + "MONITOR_WW2A0_6", + "MONITOR_LOGIC_OUTS_B16_1", + "MONITOR_LH1_3", + "MONITOR_IMUX1_5", + "MONITOR_FAN5_4", + "MONITOR_FAN3_3", + "MONITOR_LOGIC_OUTS_B16_2", + "MONITOR_WW4A0_5", + "MONITOR_JTAGMODIFIED", + "MONITOR_EE4BEG0_4", + "MONITOR_DO4", + "MONITOR_SE2A1_9", + "MONITOR_NW2A3_6", + "MONITOR_LH8_6", + "MONITOR_IMUX45_9", + "MONITOR_LH2_0", + "MONITOR_LH1_2", + "MONITOR_IMUX31_4", + "MONITOR_FAN0_0", + "MONITOR_BLOCK_OUTS_B3_8", + "MONITOR_IMUX13_6", + "MONITOR_NE4C2_5", + "MONITOR_SW4A2_0", + "MONITOR_LOGIC_OUTS_B11_8", + "MONITOR_NE4C3_4", + "MONITOR_IMUX32_9", + "MONITOR_NE4C3_6", + "MONITOR_LH12_4", + "MONITOR_BYP7_4", + "MONITOR_WW2END0_1", + "MONITOR_EE2A1_7", + "MONITOR_NW2A2_1", + "MONITOR_SE2A3_2", + "MONITOR_VERT_VAUXP6", + "MONITOR_WW2A0_8", + "MONITOR_WW4C3_0", + "MONITOR_NE4BEG2_0", + "MONITOR_WW4END1_3", + "MONITOR_WW4C0_4", + "MONITOR_TESTDB0", + "MONITOR_IMUX4_8", + "MONITOR_EE4BEG1_5", + "MONITOR_EE4B0_8", + "MONITOR_IMUX19_4", + "MONITOR_NE4BEG2_4", + "MONITOR_IMUX0_6", + "MONITOR_RESET", + "MONITOR_CLK1_9", + "MONITOR_BLOCK_OUTS_B2_9", + "MONITOR_IMUX23_5", + "MONITOR_NW4END3_6", + "MONITOR_BLOCK_OUTS_B1_3", + "MONITOR_IMUX30_8", + "MONITOR_NE4C3_7", + "MONITOR_IMUX3_4", + "MONITOR_SE4C3_7", + "MONITOR_FAN7_0", + "MONITOR_EE4B0_1", + "MONITOR_LOGIC_OUTS_B5_0", + "MONITOR_LOGIC_OUTS_B21_2", + "MONITOR_NE4C0_3", + "MONITOR_IMUX38_0", + "MONITOR_SW4A1_0", + "MONITOR_CTRL0_3", + "MONITOR_FAN5_6", + "MONITOR_EE4BEG1_2", + "MONITOR_EE4B0_7", + "MONITOR_IMUX4_7", + "MONITOR_NE4BEG2_3", + "MONITOR_NE4BEG3_5", + "MONITOR_NE2A0_7", + "MONITOR_IMUX43_3", + "MONITOR_EL1BEG3_2", + "MONITOR_TESTADCOUT16", + "MONITOR_NW4A0_3", + "MONITOR_WW4A2_2", + "MONITOR_IMUX36_3", + "MONITOR_LH7_2", + "MONITOR_FAN7_4", + "MONITOR_LOGIC_OUTS_B3_2", + "MONITOR_LH4_2", + "MONITOR_WW4END3_6", + "MONITOR_NE4C2_7", + "MONITOR_ER1BEG2_2", + "MONITOR_SW4A2_7", + "MONITOR_IMUX5_0", + "MONITOR_NW4A1_2", + "MONITOR_SW2A3_7", + "MONITOR_CTRL1_7", + "MONITOR_IMUX34_4", + "MONITOR_LOGIC_OUTS_B5_2", + "MONITOR_SE4C0_3", + "MONITOR_EE4A1_1", + "MONITOR_LH5_9", + "MONITOR_IMUX34_3", + "MONITOR_NE4BEG3_7", + "MONITOR_NW4A3_0", + "MONITOR_LOGIC_OUTS_B10_4", + "MONITOR_IMUX21_2", + "MONITOR_IMUX2_2", + "MONITOR_EE2A0_9", + "MONITOR_IMUX36_0", + "MONITOR_IMUX40_2", + "MONITOR_NE2A1_8", + "MONITOR_WW2END3_2", + "MONITOR_IMUX36_6", + "MONITOR_LH5_1", + "MONITOR_SE4BEG3_8", + "MONITOR_IMUX39_9", + "MONITOR_DO14", + "MONITOR_WL1END3_3", + "MONITOR_LOGIC_OUTS_B1_9", + "MONITOR_BYP5_7", + "MONITOR_WW4A0_3", + "MONITOR_EE4B0_5", + "MONITOR_EL1BEG1_2", + "MONITOR_EL1BEG1_0", + "MONITOR_IMUX46_9", + "MONITOR_SE4C2_1", + "MONITOR_EE4BEG2_0", + "MONITOR_BYP1_6", + "MONITOR_IMUX31_3", + "MONITOR_NE4C3_3", + "MONITOR_LOGIC_OUTS_B10_0", + "MONITOR_TESTADCIN15", + "MONITOR_LOGIC_OUTS_B7_6", + "MONITOR_EE4BEG3_3", + "MONITOR_WW4END0_1", + "MONITOR_SW4END3_9", + "MONITOR_IMUX12_6", + "MONITOR_NE4BEG0_2", + "MONITOR_WL1END3_9", + "MONITOR_EE2BEG3_4", + "MONITOR_IMUX34_7", + "MONITOR_LH2_4", + "MONITOR_EL1BEG3_0", + "MONITOR_IMUX14_5", + "MONITOR_IMUX35_4", + "MONITOR_NW4END3_0", + "MONITOR_IMUX45_4", + "MONITOR_IMUX27_4", + "MONITOR_IMUX19_9", + "MONITOR_LOGIC_OUTS_B17_7", + "MONITOR_EE4A3_9", + "MONITOR_WW4B3_5", + "MONITOR_WW4A2_1", + "MONITOR_LH11_0", + "MONITOR_SE2A0_0", + "MONITOR_WW4A1_8", + "MONITOR_EE2A2_8", + "MONITOR_SW4END3_0", + "MONITOR_SW4A3_9", + "MONITOR_EE4A2_3", + "MONITOR_BYP0_2", + "MONITOR_IMUX29_4", + "MONITOR_NE4BEG0_7", + "MONITOR_NW4END1_2", + "MONITOR_VERT_VAUXN10", + "MONITOR_ALM4", + "MONITOR_WW4END2_0", + "MONITOR_WW4A3_6", + "MONITOR_NW2A1_2", + "MONITOR_BYP3_0", + "MONITOR_NE4C0_8", + "MONITOR_NE4BEG2_8", + "MONITOR_LOGIC_OUTS_B23_2", + "MONITOR_WL1END2_7", + "MONITOR_LH4_9", + "MONITOR_SE2A3_0", + "MONITOR_TESTADCIN1", + "MONITOR_WR1END2_1", + "MONITOR_WW4A3_2", + "MONITOR_LH11_3", + "MONITOR_IMUX30_0", + "MONITOR_EE4B1_2", + "MONITOR_LOGIC_OUTS_B16_3", + "MONITOR_LOGIC_OUTS_B3_6", + "MONITOR_NE4BEG0_8", + "MONITOR_LH11_4", + "MONITOR_WW4C1_6", + "MONITOR_EE2BEG3_2", + "MONITOR_NW4A3_4", + "MONITOR_LOGIC_OUTS_B6_5", + "MONITOR_WW4B2_1", + "MONITOR_VAUXP0", + "MONITOR_ER1BEG1_7", + "MONITOR_WW2END1_8", + "MONITOR_IMUX1_0", + "MONITOR_TESTDB10", + "MONITOR_ER1BEG2_5", + "MONITOR_TESTADCOUT13", + "MONITOR_IMUX46_6", + "MONITOR_IMUX16_5", + "MONITOR_IMUX17_2", + "MONITOR_IMUX11_2", + "MONITOR_BYP5_8", + "MONITOR_IMUX21_8", + "MONITOR_LOGIC_OUTS_B14_5", + "MONITOR_WR1END3_2", + "MONITOR_SE4BEG1_1", + "MONITOR_IMUX32_4", + "MONITOR_LOGIC_OUTS_B1_3", + "MONITOR_IMUX33_2", + "MONITOR_FAN6_1", + "MONITOR_LOGIC_OUTS_B17_4", + "MONITOR_NW2A2_7", + "MONITOR_IMUX27_2", + "MONITOR_WR1END3_5", + "MONITOR_SW4A1_2", + "MONITOR_DI2", + "MONITOR_WW4END2_8", + "MONITOR_SW4END0_2", + "MONITOR_LOGIC_OUTS_B4_7", + "MONITOR_EE4B3_5", + "MONITOR_FAN2_4", + "MONITOR_LH1_1", + "MONITOR_SE2A2_6", + "MONITOR_SW4A2_5", + "MONITOR_IMUX30_1", + "MONITOR_ER1BEG2_8", + "MONITOR_LH9_5", + "MONITOR_NW2A2_3", + "MONITOR_LH1_0", + "MONITOR_LOGIC_OUTS_B2_3", + "MONITOR_LOGIC_OUTS_B7_3", + "MONITOR_EE4C0_9", + "MONITOR_SW2A2_9", + "MONITOR_SW4END3_7", + "MONITOR_WW2END2_3", + "MONITOR_SW4END1_2", + "MONITOR_LOGIC_OUTS_B8_6", + "MONITOR_LOGIC_OUTS_B18_1", + "MONITOR_LOGIC_OUTS_B3_0", + "MONITOR_IMUX33_5", + "MONITOR_BYP6_0", + "MONITOR_IMUX32_8", + "MONITOR_WL1END1_3", + "MONITOR_TESTSE3", + "MONITOR_WW4END1_4", + "MONITOR_IMUX21_5", + "MONITOR_BYP0_0", + "MONITOR_BYP7_0", + "MONITOR_FAN1_6", + "MONITOR_SW4A2_4", + "MONITOR_CTRL1_4", + "MONITOR_LOGIC_OUTS_B14_0", + "MONITOR_WW2END3_5", + "MONITOR_IMUX20_2", + "MONITOR_WR1END2_8", + "MONITOR_SE4C1_2", + "MONITOR_IMUX39_4", + "MONITOR_SW2A3_0", + "MONITOR_BLOCK_OUTS_B2_4", + "MONITOR_IMUX40_8", + "MONITOR_ER1BEG3_1", + "MONITOR_EE4A1_3", + "MONITOR_IMUX44_2", + "MONITOR_IMUX43_5", + "MONITOR_SE2A2_8", + "MONITOR_EE2BEG1_6", + "MONITOR_IMUX40_5", + "MONITOR_IMUX4_9", + "MONITOR_LOGIC_OUTS_B11_5", + "MONITOR_IMUX35_6", + "MONITOR_EE4C1_5", + "MONITOR_FAN3_6", + "MONITOR_HORIZ_VAUXN15", + "MONITOR_TESTADCIN18", + "MONITOR_SE4C2_6", + "MONITOR_EE4C3_7", + "MONITOR_IMUX1_7", + "MONITOR_BYP3_4", + "MONITOR_LOGIC_OUTS_B22_6", + "MONITOR_FAN3_7", + "MONITOR_CLK0_2", + "MONITOR_NE4BEG0_1", + "MONITOR_DO5", + "MONITOR_DI8", + "MONITOR_IMUX0_0", + "MONITOR_EE4C1_2", + "MONITOR_SW2A0_7", + "MONITOR_EE2BEG2_2", + "MONITOR_TESTDB13", + "MONITOR_FAN2_5", + "MONITOR_IMUX28_1", + "MONITOR_MUXADDR0", + "MONITOR_NE2A3_5", + "MONITOR_WW4B0_4", + "MONITOR_VAUXP11", + "MONITOR_LOGIC_OUTS_B2_2", + "MONITOR_IMUX22_5", + "MONITOR_IMUX35_3", + "MONITOR_NE2A0_9", + "MONITOR_WR1END0_3", + "MONITOR_IMUX10_9", + "MONITOR_CLK1_7", + "MONITOR_SE2A3_8", + "MONITOR_EE2A3_9", + "MONITOR_EE4A1_4", + "MONITOR_WW4C1_0", + "MONITOR_NE4BEG1_3", + "MONITOR_EL1BEG1_6", + "MONITOR_EL1BEG1_8", + "MONITOR_EE2A3_0", + "MONITOR_IMUX28_8", + "MONITOR_LOGIC_OUTS_B8_5", + "MONITOR_IMUX33_7", + "MONITOR_WW2A2_6", + "MONITOR_WW2A3_5", + "MONITOR_WL1END3_6", + "MONITOR_LH1_4", + "MONITOR_BLOCK_OUTS_B0_5", + "MONITOR_CLK1_6", + "MONITOR_SW4END3_4", + "MONITOR_WW2A1_3", + "MONITOR_SE4C1_5", + "MONITOR_EE2A1_6", + "MONITOR_NW4A2_5", + "MONITOR_EE4B3_4", + "MONITOR_IMUX17_7", + "MONITOR_TESTSCANMODE0", + "MONITOR_TESTADCIN13", + "MONITOR_LOGIC_OUTS_B13_6", + "MONITOR_TESTADCOUT17", + "MONITOR_IMUX28_4", + "MONITOR_EE4B3_3", + "MONITOR_SW2A3_6", + "MONITOR_CTRL0_6", + "MONITOR_IMUX46_4", + "MONITOR_EE2BEG0_0", + "MONITOR_NW2A1_9", + "MONITOR_DI0", + "MONITOR_SW4END1_0", + "MONITOR_EE2A3_4", + "MONITOR_WW2A2_1", + "MONITOR_ER1BEG2_4", + "MONITOR_LOGIC_OUTS_B18_7", + "MONITOR_WW2END1_7", + "MONITOR_SE4BEG2_6", + "MONITOR_IMUX0_3", + "MONITOR_WR1END3_3", + "MONITOR_IMUX16_8", + "MONITOR_LH3_8", + "MONITOR_WW4B2_2", + "MONITOR_SE4C0_0", + "MONITOR_VAUXN5", + "MONITOR_IMUX38_4", + "MONITOR_EE4A0_6", + "MONITOR_VAUXN0", + "MONITOR_IMUX5_5", + "MONITOR_WL1END3_8", + "MONITOR_NW4A1_0", + "MONITOR_LOGIC_OUTS_B9_0", + "MONITOR_ER1BEG1_0", + "MONITOR_SE2A1_2", + "MONITOR_IMUX46_3", + "MONITOR_IMUX46_8", + "MONITOR_TESTSCANMODE1", + "MONITOR_WW4END1_5", + "MONITOR_EE4BEG3_5", + "MONITOR_NE4BEG3_0", + "MONITOR_LH12_5", + "MONITOR_IMUX21_0", + "MONITOR_IMUX13_4", + "MONITOR_SE2A1_1", + "MONITOR_NE4C3_8", + "MONITOR_WW2A3_9", + "MONITOR_BLOCK_OUTS_B3_6", + "MONITOR_SE2A0_3", + "MONITOR_NW2A2_8", + "MONITOR_BLOCK_OUTS_B2_3", + "MONITOR_BYP4_0", + "MONITOR_LH9_8", + "MONITOR_LOGIC_OUTS_B17_8", + "MONITOR_WW2END3_9", + "MONITOR_IMUX23_8", + "MONITOR_WL1END2_2", + "MONITOR_IMUX8_3", + "MONITOR_LOGIC_OUTS_B2_0", + "MONITOR_TESTSO1", + "MONITOR_WR1END1_3", + "MONITOR_IMUX47_5", + "MONITOR_NW4A0_8", + "MONITOR_IMUX20_0", + "MONITOR_TESTADCIN3", + "MONITOR_WW2END1_9", + "MONITOR_WW4A2_9", + "MONITOR_LH12_1", + "MONITOR_MUXADDR2", + "MONITOR_DADDR6", + "MONITOR_WW4C2_7", + "MONITOR_EE2A2_5", + "MONITOR_BYP2_2", + "MONITOR_TESTADCIN215", + "MONITOR_IMUX42_4", + "MONITOR_IMUX43_1", + "MONITOR_WL1END1_2", + "MONITOR_NW4A3_2", + "MONITOR_DI10", + "MONITOR_VAUXP14", + "MONITOR_VAUXN15", + "MONITOR_BYP3_7", + "MONITOR_CTRL0_5", + "MONITOR_IMUX23_9", + "MONITOR_FAN2_2", + "MONITOR_IMUX15_9", + "MONITOR_WR1END3_4", + "MONITOR_SE4BEG2_3", + "MONITOR_EE4B1_8", + "MONITOR_FAN5_5", + "MONITOR_TESTADCIN8", + "MONITOR_SE4C2_4", + "MONITOR_WW2END2_2", + "MONITOR_WW2A0_7", + "MONITOR_SW4A1_1", + "MONITOR_LOGIC_OUTS_B1_5", + "MONITOR_LOGIC_OUTS_B12_1", + "MONITOR_EL1BEG2_3", + "MONITOR_LOGIC_OUTS_B16_6", + "MONITOR_NE2A0_0", + "MONITOR_DI14", + "MONITOR_FAN3_4", + "MONITOR_IMUX23_7", + "MONITOR_TESTADCOUT19", + "MONITOR_EE4B2_1", + "MONITOR_SW2A1_9", + "MONITOR_BYP5_2", + "MONITOR_LH5_5", + "MONITOR_TESTENJTAG", + "MONITOR_LOGIC_OUTS_B21_7", + "MONITOR_TESTSCANCLK4", + "MONITOR_WW4B3_9", + "MONITOR_LOGIC_OUTS_B21_0", + "MONITOR_EE4B3_8", + "MONITOR_FAN2_0", + "MONITOR_NW2A3_2", + "MONITOR_DI6", + "MONITOR_IMUX22_1", + "MONITOR_VERT_VAUXP4", + "MONITOR_NW2A0_7", + "MONITOR_WW4END3_7", + "MONITOR_IMUX9_0", + "MONITOR_EE4BEG0_7", + "MONITOR_CLK0_3", + "MONITOR_WW4C1_4", + "MONITOR_SW4END2_0", + "MONITOR_WR1END1_9", + "MONITOR_SW2A1_4", + "MONITOR_BLOCK_OUTS_B1_6", + "MONITOR_TESTADCOUT12", + "MONITOR_IMUX17_3", + "MONITOR_LOGIC_OUTS_B18_6", + "MONITOR_LOGIC_OUTS_B2_9", + "MONITOR_WW4C3_7", + "MONITOR_BLOCK_OUTS_B3_5", + "MONITOR_LH10_4", + "MONITOR_LOGIC_OUTS_B4_4", + "MONITOR_TESTADCOUT3", + "MONITOR_VERT_VAUXP15", + "MONITOR_LOGIC_OUTS_B16_4", + "MONITOR_SE2A1_5", + "MONITOR_WW4B1_6", + "MONITOR_FAN2_3", + "MONITOR_EE4C1_9", + "MONITOR_SE2A0_8", + "MONITOR_IMUX21_3", + "MONITOR_ER1BEG2_7", + "MONITOR_IMUX14_9", + "MONITOR_EE2A0_8", + "MONITOR_IMUX39_7", + "MONITOR_NW2A2_4", + "MONITOR_NW4A2_0", + "MONITOR_IMUX25_7", + "MONITOR_EE4B2_7", + "MONITOR_VAUXN9", + "MONITOR_NW4A0_6", + "MONITOR_EE4BEG1_9", + "MONITOR_WW2A3_3", + "MONITOR_EE4B3_2", + "MONITOR_VERT_VAUXN4", + "MONITOR_VAUXN8", + "MONITOR_IMUX27_5", + "MONITOR_SW2A2_0", + "MONITOR_WL1END2_6", + "MONITOR_IMUX29_7", + "MONITOR_TESTADCIN6", + "MONITOR_EE4A2_0", + "MONITOR_FAN4_5", + "MONITOR_FAN1_1", + "MONITOR_WW4B2_4", + "MONITOR_SE2A0_9", + "MONITOR_HORIZ_VAUXP11", + "MONITOR_IMUX34_6", + "MONITOR_WW2END2_6", + "MONITOR_LOGIC_OUTS_B2_6", + "MONITOR_CTRL0_9", + "MONITOR_WW2A2_7", + "MONITOR_FAN6_5", + "MONITOR_IMUX9_9", + "MONITOR_FAN7_3", + "MONITOR_IMUX47_4", + "MONITOR_IMUX46_0", + "MONITOR_NW4A2_6", + "MONITOR_EE4C1_0", + "MONITOR_NW4A0_1", + "MONITOR_LOGIC_OUTS_B16_5", + "MONITOR_IMUX10_4", + "MONITOR_LOGIC_OUTS_B3_3", + "MONITOR_SE4BEG3_0", + "MONITOR_EE4BEG2_7", + "MONITOR_IMUX44_7", + "MONITOR_WL1END3_7", + "MONITOR_DO2", + "MONITOR_IMUX13_2", + "MONITOR_IMUX19_1", + "MONITOR_IMUX40_6", + "MONITOR_IMUX30_7", + "MONITOR_IMUX8_8", + "MONITOR_IMUX28_2", + "MONITOR_SW2A2_3", + "MONITOR_TESTADCIN2", + "MONITOR_IMUX26_1", + "MONITOR_NW4END0_6", + "MONITOR_IMUX25_9", + "MONITOR_SW2A1_6", + "MONITOR_ER1BEG0_0", + "MONITOR_WW2END1_5", + "MONITOR_TESTDB4", + "MONITOR_SE2A0_6", + "MONITOR_WR1END3_1", + "MONITOR_NW4END0_1", + "MONITOR_LOGIC_OUTS_B18_4", + "MONITOR_NE4C0_4", + "MONITOR_SE4C2_3", + "MONITOR_BYP0_1", + "MONITOR_LH12_6", + "MONITOR_ER1BEG3_5", + "MONITOR_IMUX16_9", + "MONITOR_SW2A0_8", + "MONITOR_LH2_1", + "MONITOR_LOGIC_OUTS_B23_7", + "MONITOR_NW2A2_2", + "MONITOR_BYP6_4", + "MONITOR_IMUX19_2", + "MONITOR_WR1END0_2", + "MONITOR_IMUX45_3", + "MONITOR_LOGIC_OUTS_B12_3", + "MONITOR_VAUXP6", + "MONITOR_SW4A0_3", + "MONITOR_WL1END1_9", + "MONITOR_CLK0_8", + "MONITOR_LH6_4", + "MONITOR_SW4A0_4", + "MONITOR_SW4END3_8", + "MONITOR_LH3_2", + "MONITOR_DI4", + "MONITOR_NW4A1_4", + "MONITOR_IMUX31_9", + "MONITOR_NW4END0_4", + "MONITOR_NE2A3_7", + "MONITOR_WW2END3_7", + "MONITOR_EE4BEG2_9", + "MONITOR_NE4BEG2_1", + "MONITOR_LOGIC_OUTS_B15_8", + "MONITOR_LH8_5", + "MONITOR_SE4BEG3_9", + "MONITOR_MUXADDR1", + "MONITOR_IMUX10_1", + "MONITOR_WW2A2_3", + "MONITOR_IMUX30_2", + "MONITOR_WW4END3_5", + "MONITOR_LOGIC_OUTS_B12_7", + "MONITOR_FAN1_5", + "MONITOR_EE2BEG0_9", + "MONITOR_IMUX12_8", + "MONITOR_FAN0_5", + "MONITOR_IMUX12_5", + "MONITOR_BLOCK_OUTS_B2_2", + "MONITOR_WW4C2_6", + "MONITOR_SE4C2_2", + "MONITOR_LOGIC_OUTS_B21_3", + "MONITOR_WW4B3_3", + "MONITOR_WW4END0_0", + "MONITOR_CHANNEL2", + "MONITOR_LOGIC_OUTS_B12_4", + "MONITOR_NE2A2_5", + "MONITOR_SW4END3_6", + "MONITOR_IMUX9_3", + "MONITOR_HORIZ_VAUXN14", + "MONITOR_SW2A2_5", + "MONITOR_WW4B1_8", + "MONITOR_CLK0_1", + "MONITOR_FAN2_8", + "MONITOR_LOGIC_OUTS_B4_1", + "MONITOR_LOGIC_OUTS_B11_1", + "MONITOR_DADDR1", + "MONITOR_BYP6_6", + "MONITOR_LOGIC_OUTS_B6_1", + "MONITOR_IMUX26_8", + "MONITOR_WL1END2_4", + "MONITOR_SE2A1_6", + "MONITOR_WW2END2_8", + "MONITOR_HORIZ_VAUXP15", + "MONITOR_TESTADCOUT15", + "MONITOR_BYP1_5", + "MONITOR_FAN3_1", + "MONITOR_IMUX45_5", + "MONITOR_WW4END3_2", + "MONITOR_EE2A2_1", + "MONITOR_CTRL0_4", + "MONITOR_LOGIC_OUTS_B3_8", + "MONITOR_IMUX22_7", + "MONITOR_LOGIC_OUTS_B4_8", + "MONITOR_NE4BEG1_9", + "MONITOR_WW4C3_5", + "MONITOR_IMUX14_8", + "MONITOR_EE4BEG3_0", + "MONITOR_IMUX36_4", + "MONITOR_IMUX12_0", + "MONITOR_IMUX22_9", + "MONITOR_SE4C3_5", + "MONITOR_WW4B0_8", + "MONITOR_IMUX23_3", + "MONITOR_EE4B0_9", + "MONITOR_EL1BEG3_5", + "MONITOR_OT", + "MONITOR_IMUX44_4", + "MONITOR_LOGIC_OUTS_B20_3", + "MONITOR_EE2A1_4", + "MONITOR_VAUXP15", + "MONITOR_VAUXN14", + "MONITOR_IMUX10_8", + "MONITOR_NW4END0_3", + "MONITOR_NW4A1_3", + "MONITOR_LOGIC_OUTS_B0_8", + "MONITOR_IMUX15_0", + "MONITOR_EL1BEG2_7", + "MONITOR_IMUX44_0", + "MONITOR_SW4END1_5", + "MONITOR_SE4C0_2", + "MONITOR_IMUX27_3", + "MONITOR_LOGIC_OUTS_B2_4", + "MONITOR_WW4END3_4", + "MONITOR_NW2A3_9", + "MONITOR_WL1END3_5", + "MONITOR_LH3_1", + "MONITOR_LOGIC_OUTS_B15_0", + "MONITOR_SW4A1_6", + "MONITOR_EE2BEG2_3", + "MONITOR_IMUX14_4", + "MONITOR_SE4C1_4", + "MONITOR_LOGIC_OUTS_B7_1", + "MONITOR_IMUX0_1", + "MONITOR_IMUX7_4", + "MONITOR_LOGIC_OUTS_B5_7", + "MONITOR_SW4END1_6", + "MONITOR_IMUX6_4", + "MONITOR_IMUX32_5", + "MONITOR_LH4_8", + "MONITOR_IMUX38_9", + "MONITOR_IMUX11_8", + "MONITOR_TESTADCIN212", + "MONITOR_EE2BEG1_1", + "MONITOR_WW2A2_5", + "MONITOR_EE2BEG2_0", + "MONITOR_NE4C0_9", + "MONITOR_VERT_VAUXN12", + "MONITOR_CTRL0_0", + "MONITOR_EE4C0_1", + "MONITOR_LOGIC_OUTS_B12_8", + "MONITOR_EL1BEG0_7", + "MONITOR_FAN4_4", + "MONITOR_IMUX29_3", + "MONITOR_WW4C2_1", + "MONITOR_IMUX11_9", + "MONITOR_SE4C2_7", + "MONITOR_VERT_VAUXP9", + "MONITOR_BUSY", + "MONITOR_LOGIC_OUTS_B11_3", + "MONITOR_LOGIC_OUTS_B15_7", + "MONITOR_HORIZ_VAUXP7", + "MONITOR_NE4C3_2", + "MONITOR_LH7_1", + "MONITOR_IMUX18_9", + "MONITOR_FAN6_8", + "MONITOR_VERT_VAUXP5", + "MONITOR_WR1END2_6", + "MONITOR_LOGIC_OUTS_B18_5", + "MONITOR_IMUX4_6", + "MONITOR_IMUX31_8", + "MONITOR_VN", + "MONITOR_TESTADCOUT5", + "MONITOR_WW4B2_0", + "MONITOR_ER1BEG0_1", + "MONITOR_IMUX18_5", + "MONITOR_LH7_9", + "MONITOR_IMUX27_8", + "MONITOR_ER1BEG2_1", + "MONITOR_LOGIC_OUTS_B1_4", + "MONITOR_IMUX19_0", + "MONITOR_EE4A0_8", + "MONITOR_DO10", + "MONITOR_LH12_2", + "MONITOR_NW4A1_9", + "MONITOR_WW2END0_3", + "MONITOR_EE4B1_7", + "MONITOR_SW4A3_2", + "MONITOR_NW4A3_1", + "MONITOR_IMUX42_8", + "MONITOR_WW4B3_6", + "MONITOR_NE4C3_9", + "MONITOR_SW4A2_1", + "MONITOR_IMUX6_5", + "MONITOR_NE4C0_0", + "MONITOR_WW4END3_9", + "MONITOR_EL1BEG2_6", + "MONITOR_BYP1_4", + "MONITOR_SE4C2_9", + "MONITOR_DO1", + "MONITOR_EE4C0_6", + "MONITOR_VAUXP1", + "MONITOR_BYP0_7", + "MONITOR_WW4B2_8", + "MONITOR_IMUX9_2", + "MONITOR_SE2A0_5", + "MONITOR_TESTADCIN22", + "MONITOR_NW4A0_7", + "MONITOR_BYP1_9", + "MONITOR_SW4END0_4", + "MONITOR_LH12_3", + "MONITOR_IMUX19_6", + "MONITOR_TESTSE4", + "MONITOR_EE4C2_7", + "MONITOR_EE2A1_3", + "MONITOR_IMUX28_0", + "MONITOR_EE2BEG0_2", + "MONITOR_NE4C2_6", + "MONITOR_LOGIC_OUTS_B6_0", + "MONITOR_CHANNEL0", + "MONITOR_IMUX6_8", + "MONITOR_LH9_6", + "MONITOR_LOGIC_OUTS_B23_5", + "MONITOR_EE2A2_0", + "MONITOR_EL1BEG1_7", + "MONITOR_IMUX16_2", + "MONITOR_IMUX18_6", + "MONITOR_LOGIC_OUTS_B8_4", + "MONITOR_WW4C0_0", + "MONITOR_BYP6_2", + "MONITOR_LOGIC_OUTS_B12_0", + "MONITOR_EE4BEG0_2", + "MONITOR_EE2BEG2_1", + "MONITOR_IMUX6_1", + "MONITOR_IMUX1_6", + "MONITOR_EL1BEG3_1", + "MONITOR_NW4END0_7", + "MONITOR_IMUX11_7", + "MONITOR_NW4END3_2", + "MONITOR_NW4END2_4", + "MONITOR_IMUX20_8", + "MONITOR_EE4B2_2", + "MONITOR_WW4C0_9", + "MONITOR_IMUX37_6", + "MONITOR_BYP0_6", + "MONITOR_SW4END0_8", + "MONITOR_WL1END0_7", + "MONITOR_LH4_4", + "MONITOR_SE2A3_1", + "MONITOR_TESTADCIN213", + "MONITOR_NE2A3_2", + "MONITOR_BYP5_5", + "MONITOR_LH10_8", + "MONITOR_IMUX38_5", + "MONITOR_EE2BEG1_9", + "MONITOR_EE4C2_3", + "MONITOR_LOGIC_OUTS_B0_0", + "MONITOR_IMUX31_7", + "MONITOR_EE4BEG2_6", + "MONITOR_EOS", + "MONITOR_WW2A0_0", + "MONITOR_TESTSE2", + "MONITOR_WL1END1_8", + "MONITOR_WW4END1_8", + "MONITOR_VAUXN6", + "MONITOR_BYP0_9", + "MONITOR_EE2BEG1_0", + "MONITOR_EE4A3_5", + "MONITOR_LOGIC_OUTS_B18_0", + "MONITOR_WW4END0_3", + "MONITOR_WR1END1_5", + "MONITOR_SE2A3_6", + "MONITOR_IMUX4_4", + "MONITOR_LH5_3", + "MONITOR_IMUX44_9", + "MONITOR_BYP4_1", + "MONITOR_SW4END2_8", + "MONITOR_WR1END1_7", + "MONITOR_IMUX5_8", + "MONITOR_EE2BEG3_8", + "MONITOR_LOGIC_OUTS_B10_1", + "MONITOR_LOGIC_OUTS_B5_8", + "MONITOR_IMUX40_3", + "MONITOR_NW4A3_9", + "MONITOR_WW4B0_9", + "MONITOR_NE4C2_3", + "MONITOR_NE2A2_0", + "MONITOR_EE2BEG3_3", + "MONITOR_EE2BEG3_5", + "MONITOR_EE4A1_2", + "MONITOR_LOGIC_OUTS_B13_0", + "MONITOR_SE2A2_3", + "MONITOR_IMUX20_5", + "MONITOR_NW4END3_8", + "MONITOR_TESTADCIN16", + "MONITOR_WW2END0_5", + "MONITOR_SE2A2_0", + "MONITOR_BYP2_5", + "MONITOR_IMUX3_5", + "MONITOR_IMUX31_2", + "MONITOR_LOGIC_OUTS_B20_4", + "MONITOR_LOGIC_OUTS_B23_9", + "MONITOR_EE2A3_2", + "MONITOR_WW4A0_8", + "MONITOR_LH11_7", + "MONITOR_LOGIC_OUTS_B23_6", + "MONITOR_TESTADCIN218", + "MONITOR_CTRL1_9", + "MONITOR_JTAGLOCKED", + "MONITOR_LOGIC_OUTS_B22_4", + "MONITOR_ER1BEG3_4", + "MONITOR_NW2A3_0", + "MONITOR_LOGIC_OUTS_B12_9", + "MONITOR_NE4BEG0_0", + "MONITOR_BYP2_4", + "MONITOR_EE2BEG3_7", + "MONITOR_NE2A1_3", + "MONITOR_SE4C3_6", + "MONITOR_IMUX45_1", + "MONITOR_IMUX2_9", + "MONITOR_SE4C0_7", + "MONITOR_IMUX10_2", + "MONITOR_FAN4_0", + "MONITOR_ER1BEG1_8", + "MONITOR_EL1BEG0_1", + "MONITOR_NE2A0_6", + "MONITOR_IMUX13_7", + "MONITOR_EE4A0_3", + "MONITOR_NW4END1_5", + "MONITOR_WW4A0_7", + "MONITOR_TESTADCIN0", + "MONITOR_LOGIC_OUTS_B21_4", + "MONITOR_FAN3_0", + "MONITOR_LOGIC_OUTS_B6_7", + "MONITOR_WW4C0_2", + "MONITOR_TESTADCIN19", + "MONITOR_WW2A1_6", + "MONITOR_VAUXP7", + "MONITOR_EE4A1_8", + "MONITOR_IMUX29_6", + "MONITOR_WR1END2_9", + "MONITOR_LH7_4", + "MONITOR_TESTSI4", + "MONITOR_LH10_6", + "MONITOR_BLOCK_OUTS_B2_7", + "MONITOR_IMUX15_1", + "MONITOR_EE4BEG3_1", + "MONITOR_WW4A2_4", + "MONITOR_DO8", + "MONITOR_EE4B2_6", + "MONITOR_LH11_9", + "MONITOR_TESTADCIN210", + "MONITOR_VAUXP12", + "MONITOR_EL1BEG0_5", + "MONITOR_NE2A0_3", + "MONITOR_LH3_5", + "MONITOR_LOGIC_OUTS_B21_1", + "MONITOR_EE4C1_3", + "MONITOR_FAN4_8", + "MONITOR_VERT_VAUXN9", + "MONITOR_IMUX47_2", + "MONITOR_EE2BEG3_9", + "MONITOR_IMUX0_8", + "MONITOR_TESTADCOUT14", + "MONITOR_LH5_2", + "MONITOR_NW2A3_4", + "MONITOR_WR1END0_6", + "MONITOR_BLOCK_OUTS_B1_8", + "MONITOR_EE4C2_5", + "MONITOR_LOGIC_OUTS_B17_0", + "MONITOR_IMUX36_8", + "MONITOR_BLOCK_OUTS_B1_7", + "MONITOR_IMUX24_2", + "MONITOR_NE4BEG3_1", + "MONITOR_BLOCK_OUTS_B3_3", + "MONITOR_WR1END3_6", + "MONITOR_SW4A3_0", + "MONITOR_BYP3_5", + "MONITOR_WR1END1_6", + "MONITOR_ER1BEG1_4", + "MONITOR_IMUX47_0", + "MONITOR_EE4C2_9", + "MONITOR_WW2A1_7", + "MONITOR_SW2A0_9", + "MONITOR_NW2A0_9", + "MONITOR_WW4C3_2", + "MONITOR_IMUX29_8", + "MONITOR_WW2A2_2", + "MONITOR_EE2A1_8", + "MONITOR_IMUX24_6", + "MONITOR_IMUX43_4", + "MONITOR_IMUX45_2", + "MONITOR_IMUX17_4", + "MONITOR_EL1BEG1_9", + "MONITOR_FAN1_9", + "MONITOR_EE4BEG3_7", + "MONITOR_EE4A2_6", + "MONITOR_LOGIC_OUTS_B22_5", + "MONITOR_SE4C1_6", + "MONITOR_WW2END2_0", + "MONITOR_EE2A2_3", + "MONITOR_EE2BEG0_1", + "MONITOR_IMUX40_4", + "MONITOR_LH6_6", + "MONITOR_EE4BEG0_0", + "MONITOR_FAN2_1", + "MONITOR_VAUXN1", + "MONITOR_SE2A2_1", + "MONITOR_WW4C1_9", + "MONITOR_TESTSI0", + "MONITOR_IMUX16_3", + "MONITOR_DI9", + "MONITOR_LOGIC_OUTS_B7_7", + "MONITOR_EE4C3_5", + "MONITOR_IMUX42_9", + "MONITOR_IMUX13_5", + "MONITOR_VAUXP13", + "MONITOR_LH3_3", + "MONITOR_WW2END0_2", + "MONITOR_IMUX19_8", + "MONITOR_WR1END1_0", + "MONITOR_IMUX1_8", + "MONITOR_SW2A0_6", + "MONITOR_LOGIC_OUTS_B2_5", + "MONITOR_SW2A0_4", + "MONITOR_LOGIC_OUTS_B19_4", + "MONITOR_EE2BEG3_0", + "MONITOR_LH1_6", + "MONITOR_LOGIC_OUTS_B11_7", + "MONITOR_SW2A1_1", + "MONITOR_EE4C1_4", + "MONITOR_LOGIC_OUTS_B1_0", + "MONITOR_SE4BEG2_1", + "MONITOR_VERT_VAUXN6", + "MONITOR_WW2A3_8", + "MONITOR_LH9_3", + "MONITOR_LH9_4", + "MONITOR_WW4A2_7", + "MONITOR_EE4C3_2", + "MONITOR_EE4B2_4", + "MONITOR_LH7_5", + "MONITOR_WL1END1_0", + "MONITOR_IMUX16_4", + "MONITOR_IMUX35_2", + "MONITOR_EL1BEG3_6", + "MONITOR_TESTADCOUT0", + "MONITOR_NE4C0_1", + "MONITOR_LH1_7", + "MONITOR_TESTADCCLK3", + "MONITOR_FAN1_7", + "MONITOR_BYP6_9", + "MONITOR_WW4END3_8", + "MONITOR_NW4END2_5", + "MONITOR_WR1END0_7", + "MONITOR_NE4C1_3", + "MONITOR_LOGIC_OUTS_B0_1", + "MONITOR_NW4END2_0", + "MONITOR_LOGIC_OUTS_B8_9", + "MONITOR_TESTADCIN24", + "MONITOR_IMUX17_8", + "MONITOR_SW4A2_9", + "MONITOR_LOGIC_OUTS_B14_9", + "MONITOR_NW4A3_3", + "MONITOR_LOGIC_OUTS_B0_5", + "MONITOR_TESTADCOUT2", + "MONITOR_EE4A2_9", + "MONITOR_WW2A2_8", + "MONITOR_LOGIC_OUTS_B13_9", + "MONITOR_SE4BEG1_5", + "MONITOR_SE4BEG2_4", + "MONITOR_IMUX37_4", + "MONITOR_WW4END1_1", + "MONITOR_EE4A1_5", + "MONITOR_NE4BEG2_7", + "MONITOR_IMUX14_0", + "MONITOR_VAUXN10", + "MONITOR_NW2A0_8", + "MONITOR_ER1BEG1_1", + "MONITOR_IMUX2_8", + "MONITOR_SW2A2_4", + "MONITOR_IMUX17_5", + "MONITOR_IMUX13_3", + "MONITOR_LOGIC_OUTS_B12_5", + "MONITOR_LOGIC_OUTS_B19_5", + "MONITOR_WW4B0_2", + "MONITOR_WW4B1_1", + "MONITOR_IMUX45_0", + "MONITOR_IMUX24_5", + "MONITOR_IMUX12_7", + "MONITOR_IMUX25_4", + "MONITOR_WW4B2_7", + "MONITOR_LOGIC_OUTS_B17_3", + "MONITOR_VAUXN7", + "MONITOR_IMUX7_3", + "MONITOR_SE2A2_9", + "MONITOR_EE4C3_4", + "MONITOR_WW4END1_9", + "MONITOR_NW2A0_4", + "MONITOR_IMUX33_9", + "MONITOR_CTRL0_1", + "MONITOR_WW4A0_0", + "MONITOR_TESTDB7", + "MONITOR_BLOCK_OUTS_B0_7", + "MONITOR_CTRL0_8", + "MONITOR_WW4B1_4", + "MONITOR_BYP3_9", + "MONITOR_VERT_VAUXN5", + "MONITOR_EE4BEG1_0", + "MONITOR_IMUX12_2", + "MONITOR_LOGIC_OUTS_B22_1", + "MONITOR_IMUX45_6", + "MONITOR_FAN0_4", + "MONITOR_WL1END0_4", + "MONITOR_EE4C2_2", + "MONITOR_FAN4_9", + "MONITOR_LOGIC_OUTS_B4_3", + "MONITOR_NW4END0_9", + "MONITOR_LH7_6", + "MONITOR_SE4C1_9", + "MONITOR_IMUX41_1", + "MONITOR_WW2END0_7", + "MONITOR_LH4_3", + "MONITOR_VERT_VAUXN2", + "MONITOR_IMUX37_0", + "MONITOR_CONVSTCLK", + "MONITOR_WW4C1_5", + "MONITOR_WW4C3_1", + "MONITOR_IMUX9_1", + "MONITOR_SE4BEG0_4", + "MONITOR_HORIZ_VAUXN3", + "MONITOR_ALM5", + "MONITOR_IMUX14_7", + "MONITOR_TESTADCCLK2", + "MONITOR_VERT_VAUXN13", + "MONITOR_IMUX8_1", + "MONITOR_SW2A3_2", + "MONITOR_LOGIC_OUTS_B15_3", + "MONITOR_DO0", + "MONITOR_LH6_5", + "MONITOR_EE4B1_4", + "MONITOR_IMUX32_1", + "MONITOR_LH2_5", + "MONITOR_EE4B1_0", + "MONITOR_DO7", + "MONITOR_WW4END0_6", + "MONITOR_SW4A1_4", + "MONITOR_NE2A3_4", + "MONITOR_WW4C2_8", + "MONITOR_TESTADCOUT1", + "MONITOR_TESTSCANCLK2", + "MONITOR_WW4END1_6", + "MONITOR_EE4C3_9", + "MONITOR_LH8_8", + "MONITOR_TESTUPDATE", + "MONITOR_WW4A2_5", + "MONITOR_EL1BEG2_1", + "MONITOR_NW2A0_1", + "MONITOR_CTRL1_8", + "MONITOR_IMUX34_9", + "MONITOR_EL1BEG2_9", + "MONITOR_WW4A2_6", + "MONITOR_NE4BEG3_3", + "MONITOR_ER1BEG0_3", + "MONITOR_HORIZ_VAUXP14", + "MONITOR_IMUX42_1", + "MONITOR_SW4A0_5", + "MONITOR_WW4END2_4", + "MONITOR_IMUX13_0", + "MONITOR_BYP6_5", + "MONITOR_SW4END0_3", + "MONITOR_EL1BEG1_5", + "MONITOR_WW4C3_3", + "MONITOR_WW4C2_2", + "MONITOR_WW4END2_2", + "MONITOR_LOGIC_OUTS_B9_7", + "MONITOR_WL1END3_0", + "MONITOR_EE4B3_9", + "MONITOR_IMUX44_8", + "MONITOR_IMUX2_7", + "MONITOR_TESTDB2", + "MONITOR_NW2A2_0", + "MONITOR_LH7_3", + "MONITOR_EE2A0_7", + "MONITOR_LH10_0", + "MONITOR_WW4B3_2", + "MONITOR_IMUX43_0", + "MONITOR_IMUX39_3", + "MONITOR_SW4END0_6", + "MONITOR_EL1BEG2_0", + "MONITOR_IMUX1_2", + "MONITOR_TESTADCOUT7", + "MONITOR_IMUX3_0", + "MONITOR_WW4C2_9", + "MONITOR_LH5_7", + "MONITOR_EE4A2_5", + "MONITOR_IMUX0_9", + "MONITOR_HORIZ_VAUXN10", + "MONITOR_FAN7_7", + "MONITOR_IMUX36_9", + "MONITOR_WW2END3_6", + "MONITOR_FAN0_3", + "MONITOR_LOGIC_OUTS_B23_1", + "MONITOR_LOGIC_OUTS_B20_0", + "MONITOR_WW2END3_4", + "MONITOR_FAN2_6", + "MONITOR_WR1END1_4", + "MONITOR_LOGIC_OUTS_B22_2", + "MONITOR_IMUX17_0", + "MONITOR_FAN7_6", + "MONITOR_EE2A0_5", + "MONITOR_WW2A2_0", + "MONITOR_DADDR0", + "MONITOR_IMUX18_8", + "MONITOR_NW4END3_3", + "MONITOR_SE4BEG2_7", + "MONITOR_BLOCK_OUTS_B3_0", + "MONITOR_BLOCK_OUTS_B3_7", + "MONITOR_WW4C0_1", + "MONITOR_SW4END2_2", + "MONITOR_LH3_9", + "MONITOR_LOGIC_OUTS_B9_4", + "MONITOR_SW4END1_8", + "MONITOR_EL1BEG0_0", + "MONITOR_WW2END3_0", + "MONITOR_TESTSO4", + "MONITOR_FAN5_7", + "MONITOR_WW4B1_5", + "MONITOR_EE4C0_2", + "MONITOR_TESTADCIN14", + "MONITOR_WW2A3_0", + "MONITOR_WR1END3_9", + "MONITOR_SW2A3_5", + "MONITOR_EE4B0_6", + "MONITOR_BYP7_5", + "MONITOR_IMUX12_4", + "MONITOR_LOGIC_OUTS_B2_8", + "MONITOR_EE4B0_2", + "MONITOR_FAN1_4", + "MONITOR_FAN0_1", + "MONITOR_WW4B0_5", + "MONITOR_NE2A2_8", + "MONITOR_EE4A0_1", + "MONITOR_BYP2_8", + "MONITOR_LOGIC_OUTS_B4_5", + "MONITOR_VAUXN13", + "MONITOR_WW4END0_8", + "MONITOR_TESTSCANCLK3", + "MONITOR_LH6_7", + "MONITOR_IMUX44_3", + "MONITOR_LH7_7", + "MONITOR_EE4B3_7", + "MONITOR_ER1BEG0_4", + "MONITOR_SW2A1_8", + "MONITOR_SE2A1_8", + "MONITOR_SE4BEG0_1", + "MONITOR_WW4A3_3", + "MONITOR_WW4END1_0", + "MONITOR_NE4BEG3_8", + "MONITOR_EE4BEG0_6", + "MONITOR_IMUX25_1", + "MONITOR_LOGIC_OUTS_B15_1", + "MONITOR_NE2A2_2", + "MONITOR_NE4C2_4", + "MONITOR_TESTADCIN12", + "MONITOR_FAN7_8", + "MONITOR_VERT_VAUXP2", + "MONITOR_IMUX42_7", + "MONITOR_WW2END2_9", + "MONITOR_LOGIC_OUTS_B21_8", + "MONITOR_IMUX34_5", + "MONITOR_BYP4_9", + "MONITOR_IMUX47_8", + "MONITOR_EE4A2_2", + "MONITOR_WW4A3_4", + "MONITOR_NW4A2_2", + "MONITOR_EE2BEG2_8", + "MONITOR_IMUX1_9", + "MONITOR_ER1BEG2_6", + "MONITOR_FAN5_3", + "MONITOR_BYP4_3", + "MONITOR_NW2A1_1", + "MONITOR_NE2A3_1", + "MONITOR_NW4END3_7", + "MONITOR_IMUX46_5", + "MONITOR_SE2A3_9", + "MONITOR_EE4B1_5", + "MONITOR_SE4BEG3_1", + "MONITOR_NW4END2_6", + "MONITOR_LH6_0", + "MONITOR_NW2A3_5", + "MONITOR_SE4C3_8", + "MONITOR_TESTADCIN9", + "MONITOR_VERT_VAUXP13", + "MONITOR_EE2BEG2_4", + "MONITOR_IMUX20_6", + "MONITOR_EE4B2_9", + "MONITOR_LOGIC_OUTS_B6_8", + "MONITOR_WW4END0_2", + "MONITOR_BLOCK_OUTS_B0_1", + "MONITOR_LOGIC_OUTS_B0_4", + "MONITOR_WW4B3_7", + "MONITOR_IMUX14_6", + "MONITOR_LOGIC_OUTS_B2_7", + "MONITOR_EE4A3_7", + "MONITOR_NW4A3_5", + "MONITOR_EE4BEG1_7", + "MONITOR_CTRL1_2", + "MONITOR_EL1BEG1_4", + "MONITOR_LOGIC_OUTS_B13_1", + "MONITOR_IMUX7_5", + "MONITOR_SW4A2_8", + "MONITOR_EE4BEG1_1", + "MONITOR_WW2A1_2", + "MONITOR_CLK1_1", + "MONITOR_IMUX36_7", + "MONITOR_NW4END0_5", + "MONITOR_LOGIC_OUTS_B10_5", + "MONITOR_VAUXN11", + "MONITOR_FAN6_7", + "MONITOR_BYP4_6", + "MONITOR_SE4C3_0", + "MONITOR_WW4B1_9", + "MONITOR_NE2A1_2", + "MONITOR_IMUX45_7", + "MONITOR_NE4C0_5", + "MONITOR_EE4C2_8", + "MONITOR_TESTSO3", + "MONITOR_EE4BEG0_8", + "MONITOR_EE4BEG0_5", + "MONITOR_IMUX43_6", + "MONITOR_LOGIC_OUTS_B10_2", + "MONITOR_NW4END1_3", + "MONITOR_SE4C0_8", + "MONITOR_LH4_1", + "MONITOR_IMUX5_3", + "MONITOR_LOGIC_OUTS_B22_9", + "MONITOR_SW2A3_4", + "MONITOR_EE4C0_0", + "MONITOR_LOGIC_OUTS_B11_2", + "MONITOR_SE2A3_7", + "MONITOR_TESTSEL", + "MONITOR_ER1BEG1_5", + "MONITOR_ER1BEG0_6", + "MONITOR_IMUX20_4", + "MONITOR_LH10_1", + "MONITOR_WL1END2_8", + "MONITOR_FAN5_2", + "MONITOR_IMUX18_0", + "MONITOR_NW2A0_6", + "MONITOR_EE4B1_3", + "MONITOR_CLK1_2", + "MONITOR_NW2A1_4", + "MONITOR_WL1END3_4", + "MONITOR_EE2A3_3", + "MONITOR_BYP7_7", + "MONITOR_SE4BEG2_2", + "MONITOR_IMUX29_0", + "MONITOR_BYP7_2", + "MONITOR_CLK1_0", + "MONITOR_LOGIC_OUTS_B3_9", + "MONITOR_BLOCK_OUTS_B1_4", + "MONITOR_SW4END3_5", + "MONITOR_WL1END0_3", + "MONITOR_NE2A1_4", + "MONITOR_IMUX22_2", + "MONITOR_NW4END2_1", + "MONITOR_CHANNEL4", + "MONITOR_LOGIC_OUTS_B0_9", + "MONITOR_IMUX24_9", + "MONITOR_CHANNEL3", + "MONITOR_LOGIC_OUTS_B7_9", + "MONITOR_WW2A1_0", + "MONITOR_SE2A1_7", + "MONITOR_BLOCK_OUTS_B0_4", + "MONITOR_LOGIC_OUTS_B5_3", + "MONITOR_SW4A3_1", + "MONITOR_LH1_8", + "MONITOR_IMUX11_5", + "MONITOR_LOGIC_OUTS_B9_5", + "MONITOR_IMUX3_1", + "MONITOR_IMUX24_3", + "MONITOR_IMUX43_2", + "MONITOR_IMUX0_4", + "MONITOR_WW2A1_5", + "MONITOR_LOGIC_OUTS_B9_2", + "MONITOR_TESTSCANRESET", + "MONITOR_WR1END2_5", + "MONITOR_IMUX35_0", + "MONITOR_LOGIC_OUTS_B9_3", + "MONITOR_EL1BEG0_4", + "MONITOR_SE2A0_1", + "MONITOR_LOGIC_OUTS_B15_6", + "MONITOR_IMUX44_5", + "MONITOR_NE4BEG1_6", + "MONITOR_WW4A3_8", + "MONITOR_WW2END0_9", + "MONITOR_CLK0_4", + "MONITOR_NE2A0_1", + "MONITOR_LOGIC_OUTS_B8_7", + "MONITOR_JTAGBUSY", + "MONITOR_EE4C1_6", + "MONITOR_WW4END0_5", + "MONITOR_LOGIC_OUTS_B13_8", + "MONITOR_IMUX30_5", + "MONITOR_LOGIC_OUTS_B6_3", + "MONITOR_ER1BEG0_2", + "MONITOR_SW4A0_2", + "MONITOR_SW4END1_4", + "MONITOR_IMUX43_9", + "MONITOR_SW4END2_3", + "MONITOR_IMUX13_1", + "MONITOR_LOGIC_OUTS_B20_6", + "MONITOR_WW4A2_3", + "MONITOR_IMUX6_9", + "MONITOR_SE4C2_5", + "MONITOR_LOGIC_OUTS_B14_3", + "MONITOR_LOGIC_OUTS_B23_0", + "MONITOR_LOGIC_OUTS_B10_6", + "MONITOR_IMUX10_7", + "MONITOR_LH1_9", + "MONITOR_BYP7_1", + "MONITOR_WW4A1_0", + "MONITOR_FAN0_6", + "MONITOR_NE4BEG1_1", + "MONITOR_SW4END2_1", + "MONITOR_LOGIC_OUTS_B16_7", + "MONITOR_NE4C1_1", + "MONITOR_WW4A2_0", + "MONITOR_SW2A0_3", + "MONITOR_IMUX27_6", + "MONITOR_EL1BEG3_3", + "MONITOR_WW4END2_3", + "MONITOR_WL1END1_7", + "MONITOR_WW4C1_7", + "MONITOR_TESTSO2", + "MONITOR_IMUX38_1", + "MONITOR_LH11_5", + "MONITOR_FAN7_1", + "MONITOR_VAUXP10", + "MONITOR_SE4BEG2_8", + "MONITOR_SW4A3_8", + "MONITOR_TESTADCIN20", + "MONITOR_DI3", + "MONITOR_EE4B3_6", + "MONITOR_EE2A1_9", + "MONITOR_LOGIC_OUTS_B1_8", + "MONITOR_IMUX33_1", + "MONITOR_NW4A0_9", + "MONITOR_CLK0_6", + "MONITOR_FAN6_0", + "MONITOR_BLOCK_OUTS_B1_9", + "MONITOR_BYP6_7", + "MONITOR_WL1END0_5", + "MONITOR_EE4BEG3_6", + "MONITOR_EE2A3_8", + "MONITOR_LOGIC_OUTS_B5_1", + "MONITOR_NW4A1_6", + "MONITOR_IMUX37_7", + "MONITOR_IMUX8_4", + "MONITOR_BYP0_3", + "MONITOR_BYP0_4", + "MONITOR_IMUX22_6", + "MONITOR_LOGIC_OUTS_B14_8", + "MONITOR_IMUX16_0", + "MONITOR_LOGIC_OUTS_B3_4", + "MONITOR_IMUX26_2", + "MONITOR_LH8_2", + "MONITOR_SE4BEG1_7", + "MONITOR_IMUX2_6", + "MONITOR_WW2A3_6", + "MONITOR_IMUX9_5", + "MONITOR_SE4BEG3_7", + "MONITOR_IMUX14_1", + "MONITOR_TESTDB11", + "MONITOR_LOGIC_OUTS_B19_2", + "MONITOR_NE4BEG0_4", + "MONITOR_EE4A0_5", + "MONITOR_NW4END0_8", + "MONITOR_VERT_VAUXP10", + "MONITOR_NE2A3_9", + "MONITOR_LOGIC_OUTS_B5_9", + "MONITOR_WL1END0_2", + "MONITOR_ER1BEG1_6", + "MONITOR_DO15", + "MONITOR_LOGIC_OUTS_B13_4", + "MONITOR_TESTSE0", + "MONITOR_IMUX42_5", + "MONITOR_EE4B1_9", + "MONITOR_LOGIC_OUTS_B22_3", + "MONITOR_WW4END3_3", + "MONITOR_NW4A1_8", + "MONITOR_DEN", + "MONITOR_FAN7_2", + "MONITOR_IMUX18_7", + "MONITOR_EE4A0_9", + "MONITOR_SW2A2_7", + "MONITOR_DWE", + "MONITOR_BYP4_7", + "MONITOR_EE4C2_1", + "MONITOR_SE4C1_1", + "MONITOR_TESTTDO", + "MONITOR_WW4A1_9", + "MONITOR_IMUX46_2", + "MONITOR_TESTSO0", + "MONITOR_SW2A1_3", + "MONITOR_IMUX17_1", + "MONITOR_LOGIC_OUTS_B12_2", + "MONITOR_LH3_4", + "MONITOR_IMUX33_4", + "MONITOR_IMUX15_3", + "MONITOR_BLOCK_OUTS_B2_1", + "MONITOR_WR1END0_5", + "MONITOR_VERT_VAUXN14", + "MONITOR_SE4BEG3_3", + "MONITOR_FAN4_3", + "MONITOR_LOGIC_OUTS_B15_5", + "MONITOR_IMUX17_6", + "MONITOR_LOGIC_OUTS_B10_8", + "MONITOR_WW4A1_4", + "MONITOR_WW4A0_9", + "MONITOR_BYP5_9", + "MONITOR_LOGIC_OUTS_B22_8", + "MONITOR_SW4END1_1", + "MONITOR_WR1END3_7", + "MONITOR_NW4A2_8", + "MONITOR_IMUX32_2", + "MONITOR_LH9_2", + "MONITOR_IMUX37_1", + "MONITOR_LOGIC_OUTS_B8_8", + "MONITOR_SE2A1_0", + "MONITOR_WW2A3_4", + "MONITOR_IMUX11_1", + "MONITOR_SW4A0_6", + "MONITOR_EL1BEG0_6", + "MONITOR_NW4END3_4", + "MONITOR_ER1BEG0_8", + "MONITOR_LH3_0", + "MONITOR_SW2A1_7", + "MONITOR_TESTSHIFT", + "MONITOR_LOGIC_OUTS_B23_3", + "MONITOR_LOGIC_OUTS_B17_2", + "MONITOR_BYP6_8", + "MONITOR_EE4BEG1_3", + "MONITOR_LOGIC_OUTS_B10_3", + "MONITOR_WR1END3_8", + "MONITOR_TESTADCIN4", + "MONITOR_EE4C2_4", + "MONITOR_IMUX3_3", + "MONITOR_VAUXP2", + "MONITOR_IMUX4_5", + "MONITOR_VAUXP4", + "MONITOR_DADDR4", + "MONITOR_WL1END0_8", + "MONITOR_FAN5_8", + "MONITOR_NW2A1_8", + "MONITOR_SE4BEG0_0", + "MONITOR_NW2A2_9", + "MONITOR_ER1BEG1_9", + "MONITOR_WW4A0_1", + "MONITOR_IMUX2_3", + "MONITOR_LOGIC_OUTS_B8_0", + "MONITOR_EE4A3_1", + "MONITOR_WW4B0_0", + "MONITOR_SE4BEG2_0", + "MONITOR_IMUX45_8", + "MONITOR_LOGIC_OUTS_B6_4", + "MONITOR_CTRL0_7", + "MONITOR_IMUX6_2", + "MONITOR_IMUX43_8", + "MONITOR_EE2A2_4", + "MONITOR_LH12_9", + "MONITOR_SE4BEG0_9", + "MONITOR_EE4C3_1", + "MONITOR_WR1END0_0", + "MONITOR_WR1END2_7", + "MONITOR_SE4C2_8", + "MONITOR_SW4END2_9", + "MONITOR_EE4B0_0", + "MONITOR_LOGIC_OUTS_B8_3", + "MONITOR_LOGIC_OUTS_B19_8", + "MONITOR_ER1BEG2_3", + "MONITOR_NW2A2_5", + "MONITOR_EE2BEG1_8", + "MONITOR_LH2_7", + "MONITOR_LOGIC_OUTS_B19_0", + "MONITOR_EE4BEG3_4", + "MONITOR_IMUX10_0", + "MONITOR_IMUX32_0", + "MONITOR_IMUX17_9", + "MONITOR_FAN6_3", + "MONITOR_IMUX15_6", + "MONITOR_LH10_7", + "MONITOR_VERT_VAUXP1", + "MONITOR_CLK1_4", + "MONITOR_ER1BEG3_0", + "MONITOR_IMUX9_8", + "MONITOR_EE2A0_1", + "MONITOR_IMUX40_9", + "MONITOR_NW2A3_1", + "MONITOR_BLOCK_OUTS_B3_1", + "MONITOR_WW4B0_3", + "MONITOR_LH8_7", + "MONITOR_NW4END2_3", + "MONITOR_SW4A1_5", + "MONITOR_EL1BEG0_3", + "MONITOR_BLOCK_OUTS_B0_0", + "MONITOR_IMUX38_8", + "MONITOR_NE4C1_4", + "MONITOR_WW4C0_3", + "MONITOR_TESTDB8", + "MONITOR_ER1BEG2_0", + "MONITOR_BYP1_0", + "MONITOR_EE4A2_1", + "MONITOR_SE4C3_1", + "MONITOR_NE4BEG2_6", + "MONITOR_IMUX21_7", + "MONITOR_NE2A2_7", + "MONITOR_IMUX41_8", + "MONITOR_SE4C0_6", + "MONITOR_ALM2", + "MONITOR_WL1END1_6", + "MONITOR_EL1BEG0_9", + "MONITOR_IMUX8_7", + "MONITOR_IMUX30_3", + "MONITOR_EE4A2_8", + "MONITOR_IMUX8_0", + "MONITOR_IMUX7_0", + "MONITOR_LOGIC_OUTS_B11_9", + "MONITOR_IMUX28_5", + "MONITOR_SW4A2_6", + "MONITOR_NW2A3_8", + "MONITOR_LH8_9", + "MONITOR_ER1BEG0_5", + "MONITOR_LOGIC_OUTS_B18_9", + "MONITOR_IMUX46_1", + "MONITOR_EE4BEG2_8", + "MONITOR_IMUX30_9", + "MONITOR_FAN2_9", + "MONITOR_ER1BEG1_3", + "MONITOR_WW4A3_9", + "MONITOR_BYP3_6", + "MONITOR_LOGIC_OUTS_B5_6", + "MONITOR_IMUX28_6", + "MONITOR_WW4C2_4", + "MONITOR_LH7_8", + "MONITOR_DI13", + "MONITOR_IMUX47_9", + "MONITOR_DO12", + "MONITOR_EE2A1_1", + "MONITOR_LOGIC_OUTS_B17_5", + "MONITOR_ER1BEG3_7", + "MONITOR_IMUX41_0", + "MONITOR_WW4END3_1", + "MONITOR_WW2END1_2", + "MONITOR_EE4A3_8", + "MONITOR_WW2END1_3", + "MONITOR_WW2END2_1", + "MONITOR_WW2A0_5", + "MONITOR_NW2A3_3", + "MONITOR_IMUX10_5", + "MONITOR_BYP2_3", + "MONITOR_WW4END0_9", + "MONITOR_DI1", + "MONITOR_NW4A3_8", + "MONITOR_LH8_3", + "MONITOR_EE4A2_4", + "MONITOR_WL1END0_6", + "MONITOR_TESTTDI", + "MONITOR_IMUX26_5", + "MONITOR_EE4C1_1", + "MONITOR_NE4C3_5", + "MONITOR_SW2A3_8", + "MONITOR_IMUX2_5", + "MONITOR_LOGIC_OUTS_B3_7", + "MONITOR_VAUXN12", + "MONITOR_WW4END2_6", + "MONITOR_EL1BEG1_3", + "MONITOR_IMUX41_7", + "MONITOR_LOGIC_OUTS_B15_9", + "MONITOR_SW2A2_8", + "MONITOR_EE4BEG1_6", + "MONITOR_EE2A3_1", + "MONITOR_IMUX7_9", + "MONITOR_IMUX19_5", + "MONITOR_SW4END1_3", + "MONITOR_LOGIC_OUTS_B0_6", + "MONITOR_WL1END1_5", + "MONITOR_LOGIC_OUTS_B19_9", + "MONITOR_BYP2_0", + "MONITOR_IMUX5_7", + "MONITOR_IMUX23_2", + "MONITOR_LOGIC_OUTS_B14_2", + "MONITOR_WW2END1_0", + "MONITOR_IMUX36_1", + "MONITOR_SE4C3_4", + "MONITOR_CTRL1_1", + "MONITOR_EE4B0_3", + "MONITOR_WW4A1_1", + "MONITOR_TESTADCCLK1", + "MONITOR_WW2END1_4", + "MONITOR_IMUX32_3", + "MONITOR_SE4BEG1_6", + "MONITOR_WL1END2_0", + "MONITOR_IMUX40_0", + "MONITOR_WW4B2_9", + "MONITOR_LH12_7", + "MONITOR_IMUX41_5", + "MONITOR_LH10_3", + "MONITOR_BYP1_1", + "MONITOR_LOGIC_OUTS_B22_0", + "MONITOR_ALM0", + "MONITOR_EL1BEG2_4", + "MONITOR_IMUX6_7", + "MONITOR_NW2A0_5", + "MONITOR_NE4BEG1_5", + "MONITOR_NW4END1_8", + "MONITOR_NW4A0_2", + "MONITOR_WW4B2_3", + "MONITOR_NE2A1_9", + "MONITOR_IMUX41_6", + "MONITOR_NE4BEG3_6", + "MONITOR_BLOCK_OUTS_B0_6", + "MONITOR_SE4C1_7", + "MONITOR_IMUX35_1", + "MONITOR_SW4END2_4", + "MONITOR_LOGIC_OUTS_B14_7", + "MONITOR_SEG_VN", + "MONITOR_DO11", + "MONITOR_WW4A1_6", + "MONITOR_LOGIC_OUTS_B19_3", + "MONITOR_TESTDB12", + "MONITOR_LH4_0", + "MONITOR_LOGIC_OUTS_B15_2", + "MONITOR_IMUX39_0", + "MONITOR_WL1END0_9", + "MONITOR_LOGIC_OUTS_B16_9", + "MONITOR_WW4B3_1", + "MONITOR_NE4C1_5", + "MONITOR_BYP0_8", + "MONITOR_IMUX33_0", + "MONITOR_EE4A0_0", + "MONITOR_SE2A0_7", + "MONITOR_IMUX34_1", + "MONITOR_TESTSCANMODE4", + "MONITOR_CLK1_3", + "MONITOR_LH9_9", + "MONITOR_WW2END2_4", + "MONITOR_NW4END1_4", + "MONITOR_NE4C3_0", + "MONITOR_FAN0_7", + "MONITOR_IMUX5_4", + "MONITOR_WW4END2_1", + "MONITOR_IMUX34_8", + "MONITOR_VERT_VAUXP3", + "MONITOR_SE4BEG1_9", + "MONITOR_IMUX35_7", + "MONITOR_NW4END1_6", + "MONITOR_SE4BEG2_9", + "MONITOR_WW4END1_2", + "MONITOR_FAN4_7", + "MONITOR_LH6_3", + "MONITOR_EE4A2_7", + "MONITOR_LOGIC_OUTS_B18_2", + "MONITOR_DCLK", + "MONITOR_NE4BEG0_9", + "MONITOR_ER1BEG3_6", + "MONITOR_EE4A0_2", + "MONITOR_LOGIC_OUTS_B20_8", + "MONITOR_WR1END0_1", + "MONITOR_SW4A3_7", + "MONITOR_BLOCK_OUTS_B3_2", + "MONITOR_EE2BEG1_4", + "MONITOR_SW4END0_0", + "MONITOR_BLOCK_OUTS_B2_8", + "MONITOR_NE2A0_2", + "MONITOR_SE4BEG1_2", + "MONITOR_EE4C0_3", + "MONITOR_IMUX2_0", + "MONITOR_LOGIC_OUTS_B3_5", + "MONITOR_TESTSE1", + "MONITOR_TESTADCIN219", + "MONITOR_IMUX20_9", + "MONITOR_SW4END0_7", + "MONITOR_TESTADCIN25", + "MONITOR_EE2BEG2_5", + "MONITOR_FAN6_4", + "MONITOR_LOGIC_OUTS_B2_1", + "MONITOR_EE2A1_5", + "MONITOR_LH7_0", + "MONITOR_NE4C1_2", + "MONITOR_EE4C0_4", + "MONITOR_WL1END2_1", + "MONITOR_IMUX28_7", + "MONITOR_IMUX7_8", + "MONITOR_LH11_6", + "MONITOR_WR1END3_0", + "MONITOR_HORIZ_VAUXP10", + "MONITOR_SW4A0_8", + "MONITOR_IMUX15_8", + "MONITOR_WW2A1_8", + "MONITOR_WW2A3_2", + "MONITOR_IMUX47_3", + "MONITOR_IMUX30_6", + "MONITOR_IMUX5_2", + "MONITOR_IMUX29_9", + "MONITOR_WL1END3_2", + "MONITOR_BYP3_2", + "MONITOR_TESTDB6", + "MONITOR_LOGIC_OUTS_B6_2", + "MONITOR_CTRL1_5", + "MONITOR_NE4BEG3_4", + "MONITOR_SE4BEG0_8", + "MONITOR_EE4BEG2_3", + "MONITOR_LOGIC_OUTS_B10_9", + "MONITOR_IMUX18_1", + "MONITOR_CHANNEL1", + "MONITOR_EE4C1_7", + "MONITOR_WW2END2_7", + "MONITOR_LH9_0", + "MONITOR_SE4C0_4", + "MONITOR_BYP2_7", + "MONITOR_EL1BEG2_5", + "MONITOR_EE4BEG0_1", + "MONITOR_LH8_1", + "MONITOR_SW4A1_8", + "MONITOR_TESTADCOUT18", + "MONITOR_IMUX29_2", + "MONITOR_DADDR5", + "MONITOR_LH1_5", + "MONITOR_WW4A1_2", + "MONITOR_LOGIC_OUTS_B11_6", + "MONITOR_EE2A0_3", + "MONITOR_IMUX35_9", + "MONITOR_TESTDB14", + "MONITOR_IMUX8_2", + "MONITOR_IMUX44_6", + "MONITOR_WW4A1_3", + "MONITOR_LH5_8", + "MONITOR_VAUXP8", + "MONITOR_CTRL1_3", + "MONITOR_WW4C2_5", + "MONITOR_WW4B0_6", + "MONITOR_SW4END2_5", + "MONITOR_IMUX5_1", + "MONITOR_NE2A2_3", + "MONITOR_IMUX26_4", + "MONITOR_LH12_0", + "MONITOR_TESTSCANCLK1", + "MONITOR_EE2A1_0", + "MONITOR_IMUX25_3", + "MONITOR_NE4C2_8", + "MONITOR_ALM3", + "MONITOR_IMUX2_1", + "MONITOR_IMUX22_0", + "MONITOR_WW4END2_9", + "MONITOR_DI15", + "MONITOR_EE2A2_6", + "MONITOR_EL1BEG3_7", + "MONITOR_IMUX39_2", + "MONITOR_TESTADCIN28", + "MONITOR_BLOCK_OUTS_B3_9", + "MONITOR_LOGIC_OUTS_B4_6", + "MONITOR_EE2A0_4", + "MONITOR_EE4C0_5", + "MONITOR_NW4END1_1", + "MONITOR_SW2A0_1", + "MONITOR_EE4B1_1", + "MONITOR_NE2A0_4", + "MONITOR_LOGIC_OUTS_B1_1", + "MONITOR_IMUX2_4", + "MONITOR_EE2BEG0_5", + "MONITOR_WW4A3_0", + "MONITOR_IMUX28_3", + "MONITOR_DI7", + "MONITOR_WW4A1_7", + "MONITOR_SW2A3_9", + "MONITOR_NE4C2_1", + "MONITOR_EE2BEG0_7", + "MONITOR_BYP1_8", + "MONITOR_IMUX25_0", + "MONITOR_TESTADCIN26", + "MONITOR_SE4C3_9", + "MONITOR_IMUX35_8", + "MONITOR_IMUX8_9", + "MONITOR_NE4C0_7", + "MONITOR_NE2A2_9", + "MONITOR_SW4END3_3", + "MONITOR_IMUX25_5", + "MONITOR_TESTSCANMODE2", + "MONITOR_WW4END2_7", + "MONITOR_EE4A3_3", + "MONITOR_ER1BEG2_9", + "MONITOR_DRDY", + "MONITOR_NE2A1_0", + "MONITOR_WW4B1_0", + "MONITOR_EE2BEG0_4", + "MONITOR_BYP1_3", + "MONITOR_SW4A1_3", + "MONITOR_IMUX37_2", + "MONITOR_TESTADCOUT11", + "MONITOR_LOGIC_OUTS_B1_6", + "MONITOR_NE4BEG1_4", + "MONITOR_EE2BEG0_6", + "MONITOR_IMUX36_2", + "MONITOR_BYP2_6", + "MONITOR_IMUX42_0", + "MONITOR_NW4END3_1", + "MONITOR_WW2A0_1", + "MONITOR_IMUX25_8", + "MONITOR_TESTADCIN27", + "MONITOR_WW4C3_4", + "MONITOR_NE4BEG1_8", + "MONITOR_SW2A0_0", + "MONITOR_WW2A1_1", + "MONITOR_IMUX7_1", + "MONITOR_EL1BEG3_9", + "MONITOR_NE4C1_6", + "MONITOR_IMUX1_1", + "MONITOR_SW4A3_4", + "MONITOR_WR1END2_2", + "MONITOR_NE2A1_1", + "MONITOR_TESTADCIN214", + "MONITOR_WW4B0_7", + "MONITOR_WW4B2_5", + "MONITOR_IMUX42_6", + "MONITOR_LOGIC_OUTS_B10_7", + "MONITOR_EE4BEG3_8", + "MONITOR_NW4A1_7", + "MONITOR_EE2BEG1_7", + "MONITOR_EE2BEG1_2", + "MONITOR_NW4END2_8", + "MONITOR_ER1BEG1_2", + "MONITOR_WW4C3_8", + "MONITOR_DADDR2", + "MONITOR_SW2A2_1", + "MONITOR_LOGIC_OUTS_B20_7", + "MONITOR_EE4BEG2_1", + "MONITOR_EE4C3_6", + "MONITOR_WR1END0_8", + "MONITOR_EE2A2_2", + "MONITOR_WW2END0_0", + "MONITOR_WW4C0_6", + "MONITOR_NE4BEG0_5", + "MONITOR_SW2A0_5", + "MONITOR_IMUX36_5", + "MONITOR_IMUX10_6", + "MONITOR_IMUX12_1", + "MONITOR_LOGIC_OUTS_B11_0", + "MONITOR_VAUXP5", + "MONITOR_IMUX24_7", + "MONITOR_TESTADCIN10", + "MONITOR_WR1END2_3", + "MONITOR_BYP5_0", + "MONITOR_IMUX16_6", + "MONITOR_IMUX18_2", + "MONITOR_BYP7_3", + "MONITOR_IMUX42_2", + "MONITOR_NE4BEG0_6", + "MONITOR_LH3_7", + "MONITOR_FAN1_8", + "MONITOR_LOGIC_OUTS_B3_1", + "MONITOR_EE4BEG0_9", + "MONITOR_WW4B1_7", + "MONITOR_IMUX11_0", + "MONITOR_LOGIC_OUTS_B23_8", + "MONITOR_LH2_6", + "MONITOR_SE4C1_0", + "MONITOR_BLOCK_OUTS_B2_5", + "MONITOR_IMUX12_9", + "MONITOR_LH10_9", + "MONITOR_LH3_6", + "MONITOR_NE4BEG3_9", + "MONITOR_SW4END0_9", + "MONITOR_LOGIC_OUTS_B1_7", + "MONITOR_SW4A0_7", + "MONITOR_TESTSI1", + "MONITOR_BLOCK_OUTS_B0_9", + "MONITOR_IMUX33_8", + "MONITOR_SE4BEG3_5", + "MONITOR_CLK0_7", + "MONITOR_LH5_6", + "MONITOR_LOGIC_OUTS_B9_9", + "MONITOR_IMUX16_7", + "MONITOR_WW4B3_8", + "MONITOR_WR1END2_4", + "MONITOR_IMUX20_7", + "MONITOR_SE4C0_1", + "MONITOR_FAN0_9", + "MONITOR_DO6", + "MONITOR_FAN3_8", + "MONITOR_NE4BEG1_2", + "MONITOR_TESTRST", + "MONITOR_EE2BEG1_5", + "MONITOR_IMUX26_3", + "MONITOR_NW4END1_7", + "MONITOR_IMUX23_0", + "MONITOR_IMUX41_9", + "MONITOR_SE4C1_8", + "MONITOR_SW4END2_7", + "MONITOR_FAN3_5", + "MONITOR_IMUX1_4", + "MONITOR_WW4A2_8", + "MONITOR_SE4BEG0_3", + "MONITOR_IMUX5_9", + "MONITOR_SE2A2_7", + "MONITOR_TESTADCIN216", + "MONITOR_IMUX8_5", + "MONITOR_LOGIC_OUTS_B14_1", + "MONITOR_EE4A1_6", + "MONITOR_EE4A0_7", + "MONITOR_LOGIC_OUTS_B11_4", + "MONITOR_IMUX13_9", + "MONITOR_EE4B2_0", + "MONITOR_LH2_8", + "MONITOR_IMUX0_7", + "MONITOR_WL1END0_0", + "MONITOR_SE4BEG1_3", + "MONITOR_NW4A3_7", + "MONITOR_WW2A0_4", + "MONITOR_IMUX24_4", + "MONITOR_SW4A3_3", + "MONITOR_SW2A1_5", + "MONITOR_EL1BEG2_2", + "MONITOR_WW4C1_2", + "MONITOR_LOGIC_OUTS_B16_8", + "MONITOR_TESTADCIN29", + "MONITOR_FAN4_2", + "MONITOR_IMUX7_7", + "MONITOR_IMUX0_5", + "MONITOR_WW4B3_0", + "MONITOR_IMUX26_7", + "MONITOR_WW2A0_9", + "MONITOR_SW4A3_5", + "MONITOR_IMUX22_4", + "MONITOR_WW2END2_5", + "MONITOR_NW4A0_0", + "MONITOR_IMUX37_5", + "MONITOR_SE2A1_3", + "MONITOR_BYP4_2", + "MONITOR_WW4C3_9", + "MONITOR_EE4A1_9", + "MONITOR_IMUX23_1", + "MONITOR_IMUX47_6", + "MONITOR_LH8_4", + "MONITOR_TESTSCANCLK0", + "MONITOR_NW4A1_5", + "MONITOR_ER1BEG0_7", + "MONITOR_SW4END2_6", + "MONITOR_IMUX31_5", + "MONITOR_LOGIC_OUTS_B17_9", + "MONITOR_WL1END1_4", + "MONITOR_IMUX15_4", + "MONITOR_NE2A2_1", + "MONITOR_NE4BEG0_3", + "MONITOR_WW2END1_6", + "MONITOR_SEG_VP", + "MONITOR_LOGIC_OUTS_B8_2", + "MONITOR_EE4A1_0", + "MONITOR_WW2A3_7", + "MONITOR_IMUX47_1", + "MONITOR_TESTADCIN21", + "MONITOR_NE4C1_0", + "MONITOR_IMUX15_5", + "MONITOR_EE4B3_0", + "MONITOR_IMUX9_6", + "MONITOR_LH5_0", + "MONITOR_WW4A0_4", + "MONITOR_IMUX7_6", + "MONITOR_NE4BEG2_9", + "MONITOR_WW4A0_2", + "MONITOR_LH12_8", + "MONITOR_SE2A2_2", + "MONITOR_IMUX4_3", + "MONITOR_EE2BEG2_6", + "MONITOR_WL1END1_1", + "MONITOR_LH9_7", + "MONITOR_IMUX9_4", + "MONITOR_EE2BEG1_3", + "MONITOR_IMUX9_7", + "MONITOR_IMUX18_3", + "MONITOR_IMUX15_2", + "MONITOR_WW2END3_1", + "MONITOR_FAN5_0", + "MONITOR_LOGIC_OUTS_B19_6", + "MONITOR_LOGIC_OUTS_B7_4", + "MONITOR_IMUX0_2", + "MONITOR_WW4END0_7", + "MONITOR_SW4A0_1", + "MONITOR_EOC", + "MONITOR_IMUX15_7", + "MONITOR_BYP1_2", + "MONITOR_SW2A2_6", + "MONITOR_NE2A2_6", + "MONITOR_LOGIC_OUTS_B6_9", + "MONITOR_SE2A3_5", + "MONITOR_CTRL0_2", + "MONITOR_WW2A2_4", + "MONITOR_LH5_4", + "MONITOR_EE4BEG2_2", + "MONITOR_LOGIC_OUTS_B0_2", + "MONITOR_NW2A0_2", + "MONITOR_EE4BEG2_4", + "MONITOR_TESTADCOUT8", + "MONITOR_EE4B2_3", + "MONITOR_IMUX14_2", + "MONITOR_LOGIC_OUTS_B8_1", + "MONITOR_SE2A3_3", + "MONITOR_SE2A2_5", + "MONITOR_EE2A3_5", + "MONITOR_WW4C0_7", + "MONITOR_FAN7_9", + "MONITOR_EL1BEG3_4", + "MONITOR_LOGIC_OUTS_B13_7", + "MONITOR_IMUX24_1", + "MONITOR_WW4C1_1", + "MONITOR_LOGIC_OUTS_B17_6", + "MONITOR_BYP2_1", + "MONITOR_IMUX11_6", + "MONITOR_LOGIC_OUTS_B7_0", + "MONITOR_EE2BEG0_8", + "MONITOR_NE4BEG1_0", + "MONITOR_ALM7", + "MONITOR_TESTDRCK", + "MONITOR_NE2A2_4", + "MONITOR_IMUX3_6", + "MONITOR_NE4C2_0", + "MONITOR_IMUX39_6", + "MONITOR_NE4BEG2_5", + "MONITOR_FAN3_2", + "MONITOR_WW2END1_1", + "MONITOR_BLOCK_OUTS_B0_3", + "MONITOR_NW2A1_5", + "MONITOR_SW4END1_9", + "MONITOR_IMUX25_6", + "MONITOR_IMUX26_0", + "MONITOR_WW2END3_3", + "MONITOR_TESTDB15", + "MONITOR_FAN4_6", + "MONITOR_SW4A0_9", + "MONITOR_NW4END3_9", + "MONITOR_WW2END0_4", + "MONITOR_EE2A3_6", + "MONITOR_BYP3_3", + "MONITOR_EE4C1_8", + "MONITOR_EE2BEG3_1", + "MONITOR_TESTDB1", + "MONITOR_TESTADCIN5", + "MONITOR_IMUX3_2", + "MONITOR_CLK0_9", + "MONITOR_TESTADCOUT10", + "MONITOR_DADDR3", + "MONITOR_IMUX22_3", + "MONITOR_WW4A3_5", + "MONITOR_SW4A0_0", + "MONITOR_BLOCK_OUTS_B2_6", + "MONITOR_WL1END2_5", + "MONITOR_EE2A2_9", + "MONITOR_IMUX8_6", + "MONITOR_SW4END0_1", + "MONITOR_NW4END2_7", + "MONITOR_LOGIC_OUTS_B20_5", + "MONITOR_ER1BEG3_9", + "MONITOR_FAN2_7", + "MONITOR_EL1BEG2_8", + "MONITOR_CTRL1_0", + "MONITOR_LH8_0", + "MONITOR_LOGIC_OUTS_B9_1", + "MONITOR_FAN0_8", + "MONITOR_EE4BEG3_2", + "MONITOR_IMUX21_9", + "MONITOR_WW4A1_5", + "MONITOR_NW2A0_3", + "MONITOR_EE4C0_8", + "MONITOR_FAN6_2", + "MONITOR_NW4A2_7", + "MONITOR_IMUX26_6", + "MONITOR_NE2A0_8", + "MONITOR_NE2A0_5", + "MONITOR_WW2A0_2", + "MONITOR_WW2END0_6", + "MONITOR_IMUX39_1", + "MONITOR_BYP5_3", + "MONITOR_IMUX11_4", + "MONITOR_IMUX39_8", + "MONITOR_VERT_VAUXP8", + "MONITOR_NW4END0_2", + "MONITOR_NW4A1_1", + "MONITOR_SW2A0_2", + "MONITOR_VERT_VAUXP11", + "MONITOR_VERT_VAUXN8", + "MONITOR_LOGIC_OUTS_B22_7", + "MONITOR_IMUX27_7", + "MONITOR_VERT_VAUXN3", + "MONITOR_LOGIC_OUTS_B19_1", + "MONITOR_BYP4_5", + "MONITOR_IMUX16_1", + "MONITOR_EE4A3_6", + "MONITOR_NE2A3_0", + "MONITOR_WW4C0_5", + "MONITOR_WW4END0_4", + "MONITOR_IMUX6_3", + "MONITOR_WW4C2_0", + "MONITOR_SE2A0_4", + "MONITOR_LOGIC_OUTS_B20_1", + "MONITOR_WW4A3_7", + "MONITOR_EE2BEG2_9", + "MONITOR_SE4BEG1_0", + "MONITOR_ER1BEG3_3", + "MONITOR_IMUX37_9", + "MONITOR_WW2A2_9", + "MONITOR_VAUXP3", + "MONITOR_IMUX29_5", + "MONITOR_EE2A0_0", + "MONITOR_BLOCK_OUTS_B1_2", + "MONITOR_LOGIC_OUTS_B0_7", + "MONITOR_NW2A0_0", + "MONITOR_IMUX13_8", + "MONITOR_DI12", + "MONITOR_NW2A1_7", + "MONITOR_TESTADCIN211", + "MONITOR_IMUX39_5", + "MONITOR_EL1BEG1_1", + "MONITOR_FAN5_1", + "MONITOR_EL1BEG0_8", + "MONITOR_LH6_8", + "MONITOR_IMUX38_3", + "MONITOR_BYP3_1", + "MONITOR_LH9_1", + "MONITOR_IMUX6_6", + "MONITOR_DI11", + "MONITOR_FAN6_6", + "MONITOR_LOGIC_OUTS_B20_9", + "MONITOR_SW2A1_0", + "MONITOR_WL1END3_1", + "MONITOR_IMUX38_6", + "MONITOR_IMUX47_7", + "MONITOR_IMUX32_7", + "MONITOR_IMUX22_8", + "MONITOR_IMUX7_2", + "MONITOR_ER1BEG3_2", + "MONITOR_FAN1_3", + "MONITOR_LH2_9", + "MONITOR_BYP1_7", + "MONITOR_LOGIC_OUTS_B4_0", + "MONITOR_SE4BEG0_7", + "MONITOR_EE4C3_8", + "MONITOR_LH11_2", + "MONITOR_BLOCK_OUTS_B1_1", + "MONITOR_IMUX19_7", + "MONITOR_TESTADCIN217", + "MONITOR_IMUX34_0", + "MONITOR_SE4BEG0_6", + "MONITOR_IMUX27_9", + "MONITOR_NE2A1_5", + "MONITOR_NE4C1_7", + "MONITOR_SE2A1_4", + "MONITOR_NE4C1_9", + "MONITOR_LH10_5", + "MONITOR_NW4A0_5", + "MONITOR_TESTSCANMODE3", + "MONITOR_NE4BEG1_7", + "MONITOR_WW2END0_8", + "MONITOR_IMUX10_3", + "MONITOR_WW4A3_1", + "MONITOR_SE4BEG2_5", + "MONITOR_WL1END2_3", + "MONITOR_NW4A0_4", + "MONITOR_NW4END1_0", + "MONITOR_IMUX28_9", + "MONITOR_LOGIC_OUTS_B21_5", + "MONITOR_LOGIC_OUTS_B18_8", + "MONITOR_ER1BEG3_8", + "MONITOR_FAN4_1", + "MONITOR_WW2A1_9", + "MONITOR_LOGIC_OUTS_B12_6", + "MONITOR_LOGIC_OUTS_B21_9", + "MONITOR_VERT_VAUXP0", + "MONITOR_VERT_VAUXN7", + "MONITOR_MUXADDR3", + "MONITOR_BYP2_9", + "MONITOR_BYP3_8", + "MONITOR_WW4END2_5", + "MONITOR_NW2A2_6", + "MONITOR_CLK1_8", + "MONITOR_NE2A1_6", + "MONITOR_EE4A3_0", + "MONITOR_NE4C2_9", + "MONITOR_IMUX33_6", + "MONITOR_SW2A3_1", + "MONITOR_SW2A3_3", + "MONITOR_NW2A1_3", + "MONITOR_EE4BEG2_5", + "MONITOR_EE4B2_8", + "MONITOR_NW4END0_0", + "MONITOR_LOGIC_OUTS_B9_8", + "MONITOR_ER1BEG0_9", + "MONITOR_LOGIC_OUTS_B7_8", + "MONITOR_WL1END0_1", + "MONITOR_VERT_VAUXN15", + "MONITOR_WR1END0_9", + "MONITOR_WR1END2_0", + "MONITOR_IMUX21_6", + "MONITOR_TESTADCCLK0", + "MONITOR_SE4BEG0_2", + "MONITOR_SE4C3_2", + "MONITOR_NE2A3_3", + "MONITOR_TESTSI3", + "MONITOR_VERT_VAUXN0", + "MONITOR_IMUX31_0", + "MONITOR_LH2_2", + "MONITOR_TESTDB9", + "MONITOR_IMUX41_3", + "MONITOR_LOGIC_OUTS_B13_5", + "MONITOR_NE4C0_6", + "MONITOR_VERT_VAUXN11", + "MONITOR_IMUX46_7", + "MONITOR_BLOCK_OUTS_B2_0", + "MONITOR_NW4A2_3", + "MONITOR_IMUX21_4", + "MONITOR_NE4C0_2", + "MONITOR_BYP5_1", + "MONITOR_EE4B3_1", + "MONITOR_LOGIC_OUTS_B17_1", + "MONITOR_VERT_VAUXP14", + "MONITOR_VAUXN2", + "MONITOR_IMUX30_4", + "MONITOR_IMUX44_1", + "MONITOR_IMUX37_8", + "MONITOR_IMUX3_7", + "MONITOR_EE2A3_7", + "MONITOR_SW4END0_5", + "MONITOR_BLOCK_OUTS_B0_8", + "MONITOR_LOGIC_OUTS_B14_4", + "MONITOR_WW4B0_1", + "MONITOR_IMUX43_7", + "MONITOR_NW4END3_5", + "MONITOR_IMUX38_2", + "MONITOR_NE4BEG3_2", + "MONITOR_VERT_VAUXP12", + "MONITOR_WW4B2_6", + "MONITOR_BYP6_1", + "MONITOR_LOGIC_OUTS_B13_3", + "MONITOR_BLOCK_OUTS_B1_5", + "MONITOR_LOGIC_OUTS_B13_2", + "MONITOR_IMUX33_3" + ], + "tile_type": "MONITOR_BOT", + "sites": [ + { + "site_pins": { + "O": "MONITOR_SEG_VN" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "O": "MONITOR_SEG_VP" + }, + "type": "IPAD", + "prefix": "IPAD", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "TESTADCOUT15": "MONITOR_TESTADCOUT15", + "DADDR2": "MONITOR_DADDR2", + "DADDR5": "MONITOR_DADDR5", + "VAUXP2": "MONITOR_VAUXP2", + "TESTSCANMODE2": "MONITOR_TESTSCANMODE2", + "VAUXP11": "MONITOR_VAUXP11", + "RESET": "MONITOR_RESET", + "TESTDB1": "MONITOR_TESTDB1", + "VAUXP4": "MONITOR_VAUXP4", + "ALM2": "MONITOR_ALM2", + "VAUXP7": "MONITOR_VAUXP7", + "TESTSE0": "MONITOR_TESTSE0", + "TESTENJTAG": "MONITOR_TESTENJTAG", + "TESTADCIN9": "MONITOR_TESTADCIN9", + "TESTSE3": "MONITOR_TESTSE3", + "DI10": "MONITOR_DI10", + "DO8": "MONITOR_DO8", + "TESTADCIN11": "MONITOR_TESTADCIN11", + "TESTSCANMODE1": "MONITOR_TESTSCANMODE1", + "DO12": "MONITOR_DO12", + "CONVST": "MONITOR_CONVST", + "TESTSE1": "MONITOR_TESTSE1", + "DO10": "MONITOR_DO10", + "VAUXN11": "MONITOR_VAUXN11", + "TESTADCIN213": "MONITOR_TESTADCIN213", + "VAUXN12": "MONITOR_VAUXN12", + "DI3": "MONITOR_DI3", + "VAUXP9": "MONITOR_VAUXP9", + "TESTADCIN14": "MONITOR_TESTADCIN14", + "TESTSO1": "MONITOR_TESTSO1", + "TESTADCCLK3": "MONITOR_TESTADCCLK3", + "TESTDRCK": "MONITOR_TESTDRCK", + "TESTADCIN17": "MONITOR_TESTADCIN17", + "TESTCAPTURE": "MONITOR_TESTCAPTURE", + "DI15": "MONITOR_DI15", + "DCLK": "MONITOR_DCLK", + "TESTADCIN215": "MONITOR_TESTADCIN215", + "DI9": "MONITOR_DI9", + "TESTSE4": "MONITOR_TESTSE4", + "TESTADCIN214": "MONITOR_TESTADCIN214", + "TESTADCCLK1": "MONITOR_TESTADCCLK1", + "TESTDB9": "MONITOR_TESTDB9", + "TESTADCIN27": "MONITOR_TESTADCIN27", + "DO0": "MONITOR_DO0", + "TESTSCANMODE4": "MONITOR_TESTSCANMODE4", + "TESTSCANMODE0": "MONITOR_TESTSCANMODE0", + "DO3": "MONITOR_DO3", + "TESTDB2": "MONITOR_TESTDB2", + "TESTADCIN3": "MONITOR_TESTADCIN3", + "TESTSHIFT": "MONITOR_TESTSHIFT", + "DI0": "MONITOR_DI0", + "TESTADCOUT18": "MONITOR_TESTADCOUT18", + "DI7": "MONITOR_DI7", + "DO14": "MONITOR_DO14", + "TESTSI0": "MONITOR_TESTSI0", + "TESTADCOUT1": "MONITOR_TESTADCOUT1", + "VAUXN9": "MONITOR_VAUXN9", + "DADDR3": "MONITOR_DADDR3", + "TESTADCIN19": "MONITOR_TESTADCIN19", + "CONVSTCLK": "MONITOR_CONVSTCLK", + "TESTSCANCLK3": "MONITOR_TESTSCANCLK3", + "TESTADCOUT6": "MONITOR_TESTADCOUT6", + "MUXADDR1": "MONITOR_MUXADDR1", + "TESTDB13": "MONITOR_TESTDB13", + "VAUXN8": "MONITOR_VAUXN8", + "DADDR6": "MONITOR_DADDR6", + "TESTADCOUT13": "MONITOR_TESTADCOUT13", + "MUXADDR2": "MONITOR_MUXADDR2", + "TESTADCOUT2": "MONITOR_TESTADCOUT2", + "TESTADCIN15": "MONITOR_TESTADCIN15", + "ALM1": "MONITOR_ALM1", + "ALM4": "MONITOR_ALM4", + "VN": "MONITOR_VN", + "TESTADCIN21": "MONITOR_TESTADCIN21", + "TESTSI4": "MONITOR_TESTSI4", + "VAUXP5": "MONITOR_VAUXP5", + "TESTADCIN18": "MONITOR_TESTADCIN18", + "TESTSCANCLK0": "MONITOR_TESTSCANCLK0", + "TESTADCIN25": "MONITOR_TESTADCIN25", + "TESTADCOUT3": "MONITOR_TESTADCOUT3", + "CHANNEL4": "MONITOR_CHANNEL4", + "TESTDB10": "MONITOR_TESTDB10", + "ALM7": "MONITOR_ALM7", + "TESTADCIN26": "MONITOR_TESTADCIN26", + "VP": "MONITOR_VP", + "TESTADCIN211": "MONITOR_TESTADCIN211", + "TESTADCOUT9": "MONITOR_TESTADCOUT9", + "VAUXN6": "MONITOR_VAUXN6", + "DI13": "MONITOR_DI13", + "TESTUPDATE": "MONITOR_TESTUPDATE", + "DO1": "MONITOR_DO1", + "VAUXP1": "MONITOR_VAUXP1", + "DADDR4": "MONITOR_DADDR4", + "TESTADCIN24": "MONITOR_TESTADCIN24", + "DI14": "MONITOR_DI14", + "VAUXP15": "MONITOR_VAUXP15", + "DI2": "MONITOR_DI2", + "DADDR0": "MONITOR_DADDR0", + "TESTADCCLK0": "MONITOR_TESTADCCLK0", + "TESTADCOUT4": "MONITOR_TESTADCOUT4", + "DI12": "MONITOR_DI12", + "TESTADCCLK2": "MONITOR_TESTADCCLK2", + "VAUXN13": "MONITOR_VAUXN13", + "TESTADCIN219": "MONITOR_TESTADCIN219", + "DI6": "MONITOR_DI6", + "VAUXN5": "MONITOR_VAUXN5", + "TESTADCOUT19": "MONITOR_TESTADCOUT19", + "DI5": "MONITOR_DI5", + "VAUXP6": "MONITOR_VAUXP6", + "VAUXP14": "MONITOR_VAUXP14", + "TESTADCIN12": "MONITOR_TESTADCIN12", + "TESTSO4": "MONITOR_TESTSO4", + "DI11": "MONITOR_DI11", + "VAUXN4": "MONITOR_VAUXN4", + "DADDR1": "MONITOR_DADDR1", + "VAUXP3": "MONITOR_VAUXP3", + "TESTADCOUT8": "MONITOR_TESTADCOUT8", + "TESTSI1": "MONITOR_TESTSI1", + "TESTTDI": "MONITOR_TESTTDI", + "JTAGLOCKED": "MONITOR_JTAGLOCKED", + "VAUXN2": "MONITOR_VAUXN2", + "VAUXN10": "MONITOR_VAUXN10", + "TESTSCANRESET": "MONITOR_TESTSCANRESET", + "MUXADDR0": "MONITOR_MUXADDR0", + "DO9": "MONITOR_DO9", + "TESTADCIN8": "MONITOR_TESTADCIN8", + "TESTDB7": "MONITOR_TESTDB7", + "TESTDB5": "MONITOR_TESTDB5", + "TESTSCANCLK2": "MONITOR_TESTSCANCLK2", + "DWE": "MONITOR_DWE", + "VAUXN1": "MONITOR_VAUXN1", + "TESTADCOUT7": "MONITOR_TESTADCOUT7", + "TESTRST": "MONITOR_TESTRST", + "TESTADCIN2": "MONITOR_TESTADCIN2", + "CHANNEL2": "MONITOR_CHANNEL2", + "TESTADCIN4": "MONITOR_TESTADCIN4", + "TESTDB4": "MONITOR_TESTDB4", + "DO15": "MONITOR_DO15", + "VAUXN14": "MONITOR_VAUXN14", + "TESTDB6": "MONITOR_TESTDB6", + "TESTADCIN216": "MONITOR_TESTADCIN216", + "TESTTDO": "MONITOR_TESTTDO", + "VAUXP0": "MONITOR_VAUXP0", + "ALM0": "MONITOR_ALM0", + "DO5": "MONITOR_DO5", + "TESTADCIN218": "MONITOR_TESTADCIN218", + "TESTDB15": "MONITOR_TESTDB15", + "TESTADCIN212": "MONITOR_TESTADCIN212", + "TESTADCIN29": "MONITOR_TESTADCIN29", + "CHANNEL1": "MONITOR_CHANNEL1", + "CHANNEL0": "MONITOR_CHANNEL0", + "VAUXN7": "MONITOR_VAUXN7", + "TESTADCOUT11": "MONITOR_TESTADCOUT11", + "TESTADCOUT12": "MONITOR_TESTADCOUT12", + "EOS": "MONITOR_EOS", + "DO13": "MONITOR_DO13", + "MUXADDR4": "MONITOR_MUXADDR4", + "TESTADCOUT10": "MONITOR_TESTADCOUT10", + "DRDY": "MONITOR_DRDY", + "TESTDB3": "MONITOR_TESTDB3", + "BUSY": "MONITOR_BUSY", + "ALM5": "MONITOR_ALM5", + "DO7": "MONITOR_DO7", + "CHANNEL3": "MONITOR_CHANNEL3", + "TESTADCIN5": "MONITOR_TESTADCIN5", + "DI1": "MONITOR_DI1", + "TESTDB0": "MONITOR_TESTDB0", + "TESTSCANMODE3": "MONITOR_TESTSCANMODE3", + "VAUXN0": "MONITOR_VAUXN0", + "TESTSCANCLK1": "MONITOR_TESTSCANCLK1", + "ALM3": "MONITOR_ALM3", + "TESTADCIN217": "MONITOR_TESTADCIN217", + "TESTDB12": "MONITOR_TESTDB12", + "TESTADCIN13": "MONITOR_TESTADCIN13", + "TESTSI2": "MONITOR_TESTSI2", + "VAUXP8": "MONITOR_VAUXP8", + "TESTADCIN210": "MONITOR_TESTADCIN210", + "OT": "MONITOR_OT", + "TESTDB8": "MONITOR_TESTDB8", + "TESTADCIN28": "MONITOR_TESTADCIN28", + "VAUXP12": "MONITOR_VAUXP12", + "DO2": "MONITOR_DO2", + "TESTSEL": "MONITOR_TESTSEL", + "TESTADCOUT17": "MONITOR_TESTADCOUT17", + "MUXADDR3": "MONITOR_MUXADDR3", + "DI8": "MONITOR_DI8", + "TESTADCIN22": "MONITOR_TESTADCIN22", + "DO11": "MONITOR_DO11", + "TESTADCIN20": "MONITOR_TESTADCIN20", + "TESTSE2": "MONITOR_TESTSE2", + "ALM6": "MONITOR_ALM6", + "EOC": "MONITOR_EOC", + "TESTSI3": "MONITOR_TESTSI3", + "DEN": "MONITOR_DEN", + "DI4": "MONITOR_DI4", + "TESTADCIN1": "MONITOR_TESTADCIN1", + "TESTADCIN7": "MONITOR_TESTADCIN7", + "VAUXN3": "MONITOR_VAUXN3", + "TESTSO2": "MONITOR_TESTSO2", + "TESTADCOUT0": "MONITOR_TESTADCOUT0", + "VAUXN15": "MONITOR_VAUXN15", + "VAUXP10": "MONITOR_VAUXP10", + "TESTDB14": "MONITOR_TESTDB14", + "TESTADCIN0": "MONITOR_TESTADCIN0", + "TESTADCIN23": "MONITOR_TESTADCIN23", + "TESTADCIN6": "MONITOR_TESTADCIN6", + "JTAGMODIFIED": "MONITOR_JTAGMODIFIED", + "TESTADCIN16": "MONITOR_TESTADCIN16", + "TESTSO0": "MONITOR_TESTSO0", + "TESTDB11": "MONITOR_TESTDB11", + "JTAGBUSY": "MONITOR_JTAGBUSY", + "VAUXP13": "MONITOR_VAUXP13", + "TESTSCANCLK4": "MONITOR_TESTSCANCLK4", + "TESTADCIN10": "MONITOR_TESTADCIN10", + "TESTADCOUT16": "MONITOR_TESTADCOUT16", + "TESTADCOUT14": "MONITOR_TESTADCOUT14", + "DO4": "MONITOR_DO4", + "TESTADCOUT5": "MONITOR_TESTADCOUT5", + "TESTSO3": "MONITOR_TESTSO3", + "DO6": "MONITOR_DO6" + }, + "type": "XADC", + "prefix": "XADC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_MONITOR_MID.json b/artix7/tile_type_MONITOR_MID.json index c588632..70a9f7e 100644 --- a/artix7/tile_type_MONITOR_MID.json +++ b/artix7/tile_type_MONITOR_MID.json @@ -1,2336 +1,2336 @@ { - "wires": [ - "MONITOR_EE4BEG2_8", - "MONITOR_LOGIC_OUTS_B22_3", - "MONITOR_IMUX9_7", - "MONITOR_EE4B1_3", - "MONITOR_WW4B2_5", - "MONITOR_EE4BEG0_2", - "MONITOR_FAN0_6", - "MONITOR_LOGIC_OUTS_B16_2", - "MONITOR_WW4C2_3", - "MONITOR_NW4A0_4", - "MONITOR_NW4A3_2", - "MONITOR_WW2END2_0", - "MONITOR_BLOCK_OUTS_B3_0", - "MONITOR_IMUX5_8", - "MONITOR_IMUX25_0", - "MONITOR_ER1BEG2_4", - "MONITOR_VERT_VAUXN14", - "MONITOR_NE2A1_8", - "MONITOR_SW4A3_6", - "MONITOR_IMUX38_5", - "MONITOR_LH3_5", - "MONITOR_LOGIC_OUTS_B17_6", - "MONITOR_SE4BEG0_5", - "MONITOR_WW4C0_1", - "MONITOR_CLK1_0", - "MONITOR_LH12_0", - "MONITOR_VERT_VAUXP9", - "MONITOR_WW2A1_3", - "MONITOR_IMUX46_9", - "MONITOR_SE4BEG2_1", - "MONITOR_LOGIC_OUTS_B4_7", - "MONITOR_IMUX43_6", - "MONITOR_IMUX23_0", - "MONITOR_SE2A2_9", - "MONITOR_LOGIC_OUTS_B0_8", - "MONITOR_EE4B0_4", - "MONITOR_LH4_5", - "MONITOR_HORIZ_VAUXN1", - "MONITOR_IMUX12_7", - "MONITOR_IMUX47_8", - "MONITOR_LH6_1", - "MONITOR_IMUX2_7", - "MONITOR_EE4B2_1", - "MONITOR_BYP5_4", - "MONITOR_SW4A2_8", - "MONITOR_NW4END1_9", - "MONITOR_LOGIC_OUTS_B12_8", - "MONITOR_EE4C3_6", - "MONITOR_LOGIC_OUTS_B5_1", - "MONITOR_NE4C0_8", - "MONITOR_IMUX18_0", - "MONITOR_IMUX3_2", - "MONITOR_NW4A1_2", - "MONITOR_WW2A2_5", - "MONITOR_LOGIC_OUTS_B11_9", - "MONITOR_HORIZ_VAUXP1", - "MONITOR_BLOCK_OUTS_B1_3", - "MONITOR_NW2A0_6", - "MONITOR_WR1END0_8", - "MONITOR_FAN0_7", - "MONITOR_EL1BEG0_1", - "MONITOR_LOGIC_OUTS_B16_0", - "MONITOR_EE4BEG2_5", - "MONITOR_LOGIC_OUTS_B3_0", - "MONITOR_LOGIC_OUTS_B11_6", - "MONITOR_IMUX8_8", - "MONITOR_IMUX19_6", - "MONITOR_LOGIC_OUTS_B16_4", - "MONITOR_EE4B1_2", - "MONITOR_WW4B2_2", - "MONITOR_SW4END3_6", - "MONITOR_EE4A3_7", - "MONITOR_SW4END1_2", - "MONITOR_WW4END3_8", - "MONITOR_IMUX10_8", - "MONITOR_IMUX30_0", - "MONITOR_EE2A1_5", - "MONITOR_NW4END0_9", - "MONITOR_NE4C2_1", - "MONITOR_SW4END2_5", - "MONITOR_IMUX0_4", - "MONITOR_WW4A1_6", - "MONITOR_EE4A3_3", - "MONITOR_WW4C0_6", - "MONITOR_ER1BEG2_5", - "MONITOR_LH11_9", - "MONITOR_BYP2_7", - "MONITOR_IMUX6_5", - "MONITOR_WW4END3_4", - "MONITOR_LOGIC_OUTS_B19_2", - "MONITOR_WL1END2_0", - "MONITOR_LOGIC_OUTS_B21_0", - "MONITOR_IMUX31_1", - "MONITOR_WR1END0_3", - "MONITOR_LH1_5", - "MONITOR_BYP0_3", - "MONITOR_IMUX24_2", - "MONITOR_LOGIC_OUTS_B20_2", - "MONITOR_ER1BEG1_4", - "MONITOR_LH1_9", - "MONITOR_BLOCK_OUTS_B1_7", - "MONITOR_WL1END1_6", - "MONITOR_EE4A0_0", - "MONITOR_FAN0_1", - "MONITOR_WL1END1_2", - "MONITOR_EE4C1_1", - "MONITOR_IMUX5_0", - "MONITOR_EE4BEG3_6", - "MONITOR_EL1BEG1_6", - "MONITOR_EE4B2_9", - "MONITOR_SE4C0_4", - "MONITOR_LOGIC_OUTS_B2_8", - "MONITOR_IMUX26_9", - "MONITOR_WW2A3_8", - "MONITOR_LOGIC_OUTS_B15_9", - "MONITOR_WL1END3_6", - "MONITOR_BYP3_6", - "MONITOR_SW4A0_4", - "MONITOR_IMUX28_3", - "MONITOR_FAN7_6", - "MONITOR_SW4END1_9", - "MONITOR_IMUX35_7", - "MONITOR_BLOCK_OUTS_B3_9", - "MONITOR_EE4BEG3_9", - "MONITOR_LH10_4", - "MONITOR_ER1BEG3_5", - "MONITOR_SE4C2_0", - "MONITOR_WW4END2_6", - "MONITOR_LH10_2", - "MONITOR_SW4END1_7", - "MONITOR_IMUX35_6", - "MONITOR_LOGIC_OUTS_B23_6", - "MONITOR_WR1END0_7", - "MONITOR_EE4B3_0", - "MONITOR_NW2A0_2", - "MONITOR_VERT_VAUXP13", - "MONITOR_EE2BEG3_0", - "MONITOR_FAN1_0", - "MONITOR_IMUX42_5", - "MONITOR_WW4END0_9", - "MONITOR_WW4END3_7", - "MONITOR_EE4BEG0_7", - "MONITOR_IMUX40_8", - "MONITOR_EE4C0_5", - "MONITOR_SW4A0_6", - "MONITOR_LOGIC_OUTS_B1_0", - "MONITOR_IMUX28_4", - "MONITOR_WW4B3_8", - "MONITOR_EE4C1_3", - "MONITOR_EE2A1_2", - "MONITOR_WW4B1_2", - "MONITOR_BYP0_6", - "MONITOR_WW2END2_3", - "MONITOR_WW4END1_5", - "MONITOR_BLOCK_OUTS_B2_5", - "MONITOR_BYP1_8", - "MONITOR_LOGIC_OUTS_B3_6", - "MONITOR_FAN6_2", - "MONITOR_EE4BEG1_9", - "MONITOR_LOGIC_OUTS_B10_2", - "MONITOR_WW4A3_4", - "MONITOR_LH2_9", - "MONITOR_HORIZ_VAUXP5", - "MONITOR_LH1_0", - "MONITOR_EE2A1_0", - "MONITOR_WW2END3_7", - "MONITOR_WW4A2_6", - "MONITOR_BLOCK_OUTS_B1_2", - "MONITOR_IMUX11_0", - "MONITOR_NW2A2_1", - "MONITOR_ER1BEG1_5", - "MONITOR_FAN1_4", - "MONITOR_CLK1_5", - "MONITOR_IMUX46_7", - "MONITOR_NE4BEG1_1", - "MONITOR_BLOCK_OUTS_B3_2", - "MONITOR_EL1BEG2_9", - "MONITOR_IMUX6_6", - "MONITOR_WW4END3_9", - "MONITOR_NW2A1_2", - "MONITOR_WW4END1_4", - "MONITOR_CTRL0_9", - "MONITOR_SW4END0_4", - "MONITOR_EE4B1_4", - "MONITOR_NW4A0_1", - "MONITOR_LH8_8", - "MONITOR_IMUX21_1", - "MONITOR_LOGIC_OUTS_B1_5", - "MONITOR_EE2BEG0_0", - "MONITOR_IMUX46_1", - "MONITOR_NE4BEG0_9", - "MONITOR_NW4END3_2", - "MONITOR_EL1BEG1_9", - "MONITOR_VERT_VAUXP11", - "MONITOR_WR1END1_8", - "MONITOR_SE2A0_8", - "MONITOR_WR1END3_4", - "MONITOR_IMUX27_7", - "MONITOR_SE4C0_3", - "MONITOR_BYP2_6", - "MONITOR_LOGIC_OUTS_B15_4", - "MONITOR_SE2A1_4", - "MONITOR_WW2END1_4", - "MONITOR_SW4A2_5", - "MONITOR_IMUX3_8", - "MONITOR_NE4BEG3_2", - "MONITOR_NW2A3_1", - "MONITOR_SW2A3_7", - "MONITOR_LOGIC_OUTS_B18_8", - "MONITOR_LH6_3", - "MONITOR_NW2A1_3", - "MONITOR_IMUX19_0", - "MONITOR_NE2A1_2", - "MONITOR_EE4B3_5", - "MONITOR_NW4END1_0", - "MONITOR_LOGIC_OUTS_B6_8", - "MONITOR_LOGIC_OUTS_B23_5", - "MONITOR_WW2END0_9", - "MONITOR_NE4C1_8", - "MONITOR_LOGIC_OUTS_B0_3", - "MONITOR_EE4B1_7", - "MONITOR_WW4C2_1", - "MONITOR_BYP3_7", - "MONITOR_IMUX30_2", - "MONITOR_NE4BEG2_1", - "MONITOR_WR1END0_1", - "MONITOR_EE2A3_5", - "MONITOR_SE4C2_9", - "MONITOR_IMUX24_0", - "MONITOR_LOGIC_OUTS_B2_5", - "MONITOR_WW4A3_0", - "MONITOR_EE2A2_8", - "MONITOR_IMUX46_5", - "MONITOR_LOGIC_OUTS_B6_5", - "MONITOR_EE2BEG0_5", - "MONITOR_LOGIC_OUTS_B6_2", - "MONITOR_LOGIC_OUTS_B2_6", - "MONITOR_IMUX40_3", - "MONITOR_ER1BEG0_3", - "MONITOR_NW2A0_1", - "MONITOR_VERT_VAUXP12", - "MONITOR_IMUX45_6", - "MONITOR_EE4B2_6", - "MONITOR_NW4END3_7", - "MONITOR_IMUX35_5", - "MONITOR_LOGIC_OUTS_B11_7", - "MONITOR_IMUX7_6", - "MONITOR_SW4A1_7", - "MONITOR_WW2A0_0", - "MONITOR_NW4END0_6", - "MONITOR_SW4END0_5", - "MONITOR_SW4A2_7", - "MONITOR_IMUX18_6", - "MONITOR_NE4BEG0_3", - "MONITOR_NW4A1_8", - "MONITOR_LOGIC_OUTS_B12_2", - "MONITOR_SE4BEG1_9", - "MONITOR_LOGIC_OUTS_B1_2", - "MONITOR_NW4END0_1", - "MONITOR_WW4A2_2", - "MONITOR_SW4END3_7", - "MONITOR_IMUX32_2", - "MONITOR_NE4BEG2_9", - "MONITOR_SW4A2_6", - "MONITOR_BYP1_3", - "MONITOR_EE2A3_2", - "MONITOR_IMUX12_4", - "MONITOR_SE2A0_4", - "MONITOR_EE4A2_1", - "MONITOR_NW2A2_5", - "MONITOR_IMUX30_9", - "MONITOR_WL1END2_5", - "MONITOR_IMUX7_3", - "MONITOR_IMUX29_3", - "MONITOR_NW2A2_9", - "MONITOR_SE4C2_6", - "MONITOR_FAN4_9", - "MONITOR_IMUX27_4", - "MONITOR_IMUX10_1", - "MONITOR_IMUX36_2", - "MONITOR_WR1END2_2", - "MONITOR_IMUX10_2", - "MONITOR_WW2A0_7", - "MONITOR_IMUX18_2", - "MONITOR_WW2A2_9", - "MONITOR_CTRL1_6", - "MONITOR_LOGIC_OUTS_B11_8", - "MONITOR_BLOCK_OUTS_B2_3", - "MONITOR_CLK1_2", - "MONITOR_EE4A2_9", - "MONITOR_NE4C2_3", - "MONITOR_SW4A1_6", - "MONITOR_WW2A2_0", - "MONITOR_EL1BEG3_1", - "MONITOR_IMUX43_1", - "MONITOR_LH7_6", - "MONITOR_SE4C0_6", - "MONITOR_WW4B3_3", - "MONITOR_CLK0_1", - "MONITOR_IMUX31_8", - "MONITOR_SE4C2_5", - "MONITOR_SE2A0_0", - "MONITOR_IMUX3_3", - "MONITOR_VERT_VAUXN8", - "MONITOR_SE4BEG1_3", - "MONITOR_SE4C1_6", - "MONITOR_VERT_VAUXN5", - "MONITOR_SW2A1_8", - "MONITOR_IMUX8_7", - "MONITOR_LOGIC_OUTS_B9_5", - "MONITOR_IMUX41_7", - "MONITOR_VERT_VAUXN12", - "MONITOR_NE4BEG0_5", - "MONITOR_WW4B0_4", - "MONITOR_EE4BEG2_3", - "MONITOR_EE4C3_7", - "MONITOR_SE4C3_0", - "MONITOR_IMUX32_1", - "MONITOR_WR1END3_1", - "MONITOR_WW2END2_8", - "MONITOR_IMUX21_7", - "MONITOR_WW4B3_6", - "MONITOR_LOGIC_OUTS_B12_1", - "MONITOR_WW2END3_3", - "MONITOR_WW4A0_1", - "MONITOR_FAN6_6", - "MONITOR_VERT_VAUXP4", - "MONITOR_SE2A1_8", - "MONITOR_IMUX23_9", - "MONITOR_ER1BEG3_3", - "MONITOR_IMUX3_6", - "MONITOR_EE4BEG1_8", - "MONITOR_WR1END1_2", - "MONITOR_SE4C1_7", - "MONITOR_FAN4_2", - "MONITOR_WW4B2_7", - "MONITOR_EE4A0_1", - "MONITOR_EE2A3_7", - "MONITOR_LOGIC_OUTS_B7_2", - "MONITOR_EE2A3_9", - "MONITOR_LOGIC_OUTS_B18_5", - "MONITOR_IMUX36_4", - "MONITOR_VERT_VAUXP7", - "MONITOR_SW2A1_6", - "MONITOR_EE2BEG1_6", - "MONITOR_LOGIC_OUTS_B4_5", - "MONITOR_LOGIC_OUTS_B8_4", - "MONITOR_IMUX47_2", - "MONITOR_LH7_3", - "MONITOR_EE4A2_8", - "MONITOR_IMUX36_6", - "MONITOR_NW4A3_1", - "MONITOR_IMUX37_9", - "MONITOR_NE2A0_9", - "MONITOR_NW4END0_8", - "MONITOR_IMUX40_2", - "MONITOR_WR1END0_9", - "MONITOR_IMUX25_8", - "MONITOR_LOGIC_OUTS_B15_6", - "MONITOR_WL1END0_9", - "MONITOR_FAN1_9", - "MONITOR_LOGIC_OUTS_B2_1", - "MONITOR_IMUX4_2", - "MONITOR_LH5_3", - "MONITOR_IMUX7_8", - "MONITOR_LOGIC_OUTS_B1_8", - "MONITOR_LOGIC_OUTS_B10_5", - "MONITOR_IMUX27_5", - "MONITOR_IMUX42_2", - "MONITOR_WW4C3_7", - "MONITOR_IMUX4_7", - "MONITOR_LOGIC_OUTS_B5_2", - "MONITOR_WW2A1_9", - "MONITOR_IMUX14_6", - "MONITOR_WW4A3_6", - "MONITOR_SE4C3_9", - "MONITOR_WW2END3_4", - "MONITOR_IMUX27_2", - "MONITOR_NE2A1_3", - "MONITOR_IMUX43_8", - "MONITOR_IMUX11_1", - "MONITOR_IMUX1_8", - "MONITOR_IMUX12_0", - "MONITOR_FAN7_7", - "MONITOR_BYP6_0", - "MONITOR_IMUX13_1", - "MONITOR_LOGIC_OUTS_B11_4", - "MONITOR_LOGIC_OUTS_B11_0", - "MONITOR_LOGIC_OUTS_B9_3", - "MONITOR_FAN2_3", - "MONITOR_NW4END1_6", - "MONITOR_WL1END3_9", - "MONITOR_BYP2_9", - "MONITOR_IMUX17_6", - "MONITOR_FAN5_7", - "MONITOR_WW4B1_4", - "MONITOR_LH6_9", - "MONITOR_SE4C1_1", - "MONITOR_ER1BEG1_6", - "MONITOR_IMUX27_3", - "MONITOR_WL1END1_0", - "MONITOR_WL1END3_7", - "MONITOR_IMUX24_4", - "MONITOR_SW2A0_2", - "MONITOR_EE4A0_5", - "MONITOR_EE4C2_7", - "MONITOR_IMUX2_5", - "MONITOR_BLOCK_OUTS_B2_4", - "MONITOR_LH9_5", - "MONITOR_SE4C2_3", - "MONITOR_EE4C1_9", - "MONITOR_SW4END3_2", - "MONITOR_BYP1_6", - "MONITOR_IMUX17_0", - "MONITOR_LOGIC_OUTS_B16_1", - "MONITOR_LOGIC_OUTS_B23_4", - "MONITOR_LOGIC_OUTS_B6_6", - "MONITOR_IMUX43_0", - "MONITOR_IMUX6_9", - "MONITOR_NW2A2_3", - "MONITOR_LOGIC_OUTS_B19_6", - "MONITOR_IMUX8_0", - "MONITOR_LOGIC_OUTS_B3_2", - "MONITOR_SW2A2_5", - "MONITOR_IMUX9_6", - "MONITOR_LOGIC_OUTS_B5_3", - "MONITOR_LOGIC_OUTS_B15_2", - "MONITOR_WR1END0_2", - "MONITOR_IMUX23_2", - "MONITOR_SE4C0_7", - "MONITOR_WW4END0_4", - "MONITOR_WW2END1_2", - "MONITOR_IMUX45_2", - "MONITOR_IMUX30_3", - "MONITOR_NE4C3_2", - "MONITOR_LH7_1", - "MONITOR_WW4A1_8", - "MONITOR_BLOCK_OUTS_B0_5", - "MONITOR_NE4C2_7", - "MONITOR_EE2A1_8", - "MONITOR_LOGIC_OUTS_B20_9", - "MONITOR_SE2A3_4", - "MONITOR_CTRL1_1", - "MONITOR_EE4A2_7", - "MONITOR_EE2A2_2", - "MONITOR_WR1END1_0", - "MONITOR_IMUX6_8", - "MONITOR_IMUX28_9", - "MONITOR_WW4C3_4", - "MONITOR_NE4BEG1_6", - "MONITOR_EE4A1_0", - "MONITOR_BYP6_9", - "MONITOR_LOGIC_OUTS_B17_7", - "MONITOR_IMUX23_1", - "MONITOR_NW4END0_3", - "MONITOR_NE4BEG0_1", - "MONITOR_LOGIC_OUTS_B7_5", - "MONITOR_WR1END3_0", - "MONITOR_SE2A1_6", - "MONITOR_NE2A1_0", - "MONITOR_FAN7_8", - "MONITOR_NW2A3_0", - "MONITOR_NE2A1_6", - "MONITOR_SE2A1_1", - "MONITOR_NW4END3_9", - "MONITOR_WW4B0_1", - "MONITOR_SE2A2_2", - "MONITOR_IMUX47_0", - "MONITOR_ER1BEG1_3", - "MONITOR_WR1END2_3", - "MONITOR_IMUX29_7", - "MONITOR_EE4BEG0_8", - "MONITOR_IMUX9_4", - "MONITOR_SW4END1_8", - "MONITOR_LH2_8", - "MONITOR_SE4BEG3_5", - "MONITOR_IMUX4_1", - "MONITOR_WW2A0_1", - "MONITOR_WW4C1_2", - "MONITOR_CLK1_3", - "MONITOR_IMUX19_8", - "MONITOR_NE4BEG2_5", - "MONITOR_LH2_0", - "MONITOR_WW4B0_8", - "MONITOR_IMUX47_5", - "MONITOR_EE2BEG1_3", - "MONITOR_IMUX40_6", - "MONITOR_IMUX15_4", - "MONITOR_NE4BEG1_0", - "MONITOR_LH10_7", - "MONITOR_SE4C3_2", - "MONITOR_CTRL0_6", - "MONITOR_LOGIC_OUTS_B15_0", - "MONITOR_FAN7_4", - "MONITOR_NE4C0_0", - "MONITOR_CLK0_3", - "MONITOR_IMUX13_7", - "MONITOR_LH4_4", - "MONITOR_NE4C1_1", - "MONITOR_WW4C3_0", - "MONITOR_SE4BEG3_7", - "MONITOR_WW4B1_3", - "MONITOR_SW2A1_5", - "MONITOR_IMUX6_4", - "MONITOR_NE2A0_4", - "MONITOR_LOGIC_OUTS_B10_4", - "MONITOR_LOGIC_OUTS_B21_9", - "MONITOR_CTRL0_1", - "MONITOR_IMUX16_5", - "MONITOR_WL1END1_5", - "MONITOR_EE2A2_7", - "MONITOR_IMUX25_2", - "MONITOR_WW2A3_9", - "MONITOR_SW2A3_9", - "MONITOR_IMUX19_4", - "MONITOR_CLK0_5", - "MONITOR_LOGIC_OUTS_B4_6", - "MONITOR_IMUX21_3", - "MONITOR_IMUX14_1", - "MONITOR_EE2BEG3_5", - "MONITOR_BYP5_6", - "MONITOR_LOGIC_OUTS_B20_8", - "MONITOR_EE4BEG1_0", - "MONITOR_IMUX30_6", - "MONITOR_FAN3_9", - "MONITOR_FAN0_9", - "MONITOR_NW4END1_3", - "MONITOR_LOGIC_OUTS_B23_7", - "MONITOR_BYP2_0", - "MONITOR_SW4END2_8", - "MONITOR_WW4B0_2", - "MONITOR_SW2A0_9", - "MONITOR_BYP7_2", - "MONITOR_SE4BEG1_8", - "MONITOR_EE2BEG1_8", - "MONITOR_EE2A1_1", - "MONITOR_LH12_7", - "MONITOR_IMUX41_9", - "MONITOR_WW4B2_9", - "MONITOR_LOGIC_OUTS_B19_0", - "MONITOR_VERT_VAUXP8", - "MONITOR_IMUX8_4", - "MONITOR_SW4A3_3", - "MONITOR_LOGIC_OUTS_B9_0", - "MONITOR_LH6_6", - "MONITOR_SW4A0_7", - "MONITOR_LOGIC_OUTS_B21_6", - "MONITOR_EE4C2_8", - "MONITOR_CTRL0_3", - "MONITOR_LH9_2", - "MONITOR_LOGIC_OUTS_B19_7", - "MONITOR_WL1END2_8", - "MONITOR_BYP7_3", - "MONITOR_EL1BEG0_7", - "MONITOR_LOGIC_OUTS_B7_8", - "MONITOR_EE2A0_1", - "MONITOR_ER1BEG2_3", - "MONITOR_EE4C1_6", - "MONITOR_SW4END0_7", - "MONITOR_NE4C0_4", - "MONITOR_WW4A3_5", - "MONITOR_SE4C2_7", - "MONITOR_BYP4_8", - "MONITOR_IMUX15_3", - "MONITOR_NE4BEG3_0", - "MONITOR_EE4A0_2", - "MONITOR_LOGIC_OUTS_B13_9", - "MONITOR_CLK0_7", - "MONITOR_NE4C2_9", - "MONITOR_SW4END3_1", - "MONITOR_SE4C3_7", - "MONITOR_IMUX14_4", - "MONITOR_FAN4_7", - "MONITOR_LH11_8", - "MONITOR_EE4C0_8", - "MONITOR_ER1BEG2_2", - "MONITOR_IMUX45_5", - "MONITOR_NW2A3_4", - "MONITOR_NW4A0_8", - "MONITOR_WW4C1_7", - "MONITOR_SW2A2_9", - "MONITOR_IMUX31_3", - "MONITOR_WR1END2_9", - "MONITOR_EL1BEG0_9", - "MONITOR_NW4A2_8", - "MONITOR_NE4BEG1_8", - "MONITOR_SW4END3_3", - "MONITOR_LOGIC_OUTS_B8_6", - "MONITOR_BYP7_1", - "MONITOR_LOGIC_OUTS_B14_5", - "MONITOR_WW2A1_7", - "MONITOR_FAN3_2", - "MONITOR_EE4C2_9", - "MONITOR_ER1BEG3_7", - "MONITOR_FAN2_4", - "MONITOR_LOGIC_OUTS_B13_5", - "MONITOR_IMUX4_4", - "MONITOR_FAN1_8", - "MONITOR_LH5_4", - "MONITOR_IMUX33_1", - "MONITOR_NW4A3_0", - "MONITOR_LH5_7", - "MONITOR_IMUX24_9", - "MONITOR_IMUX32_8", - "MONITOR_NW4END0_2", - "MONITOR_WW4B1_6", - "MONITOR_IMUX17_2", - "MONITOR_IMUX42_8", - "MONITOR_SW2A2_6", - "MONITOR_IMUX17_9", - "MONITOR_WR1END1_1", - "MONITOR_IMUX2_0", - "MONITOR_EE2A0_7", - "MONITOR_LH11_1", - "MONITOR_WR1END1_5", - "MONITOR_SE2A1_3", - "MONITOR_CTRL1_3", - "MONITOR_EE4B3_8", - "MONITOR_NW4END3_4", - "MONITOR_SE4BEG0_6", - "MONITOR_SW2A1_9", - "MONITOR_LOGIC_OUTS_B22_0", - "MONITOR_ER1BEG0_6", - "MONITOR_IMUX46_3", - "MONITOR_WL1END3_4", - "MONITOR_IMUX18_5", - "MONITOR_WW4END3_0", - "MONITOR_LOGIC_OUTS_B12_3", - "MONITOR_LH11_6", - "MONITOR_EE4C1_0", - "MONITOR_EE4B3_1", - "MONITOR_LH6_4", - "MONITOR_LH2_6", - "MONITOR_WW4C3_8", - "MONITOR_EE2A0_2", - "MONITOR_FAN6_5", - "MONITOR_VERT_VAUXN7", - "MONITOR_IMUX3_0", - "MONITOR_IMUX47_3", - "MONITOR_VERT_VAUXN4", - "MONITOR_WR1END2_4", - "MONITOR_SW4A1_9", - "MONITOR_IMUX6_1", - "MONITOR_IMUX33_7", - "MONITOR_IMUX31_7", - "MONITOR_WL1END0_7", - "MONITOR_IMUX23_6", - "MONITOR_WW4END2_2", - "MONITOR_ER1BEG1_2", - "MONITOR_NW2A0_8", - "MONITOR_LH8_2", - "MONITOR_WW4END0_1", - "MONITOR_SE2A0_1", - "MONITOR_LOGIC_OUTS_B17_8", - "MONITOR_VERT_VAUXN11", - "MONITOR_NW2A1_1", - "MONITOR_WW4C2_5", - "MONITOR_EL1BEG1_5", - "MONITOR_EE4C2_1", - "MONITOR_LOGIC_OUTS_B1_7", - "MONITOR_WW4B0_5", - "MONITOR_EE4B2_7", - "MONITOR_EE4C1_5", - "MONITOR_EE2A0_8", - "MONITOR_BLOCK_OUTS_B0_9", - "MONITOR_IMUX12_5", - "MONITOR_IMUX18_4", - "MONITOR_FAN2_0", - "MONITOR_EE4A2_6", - "MONITOR_FAN5_9", - "MONITOR_WW2END0_5", - "MONITOR_SE2A0_9", - "MONITOR_BYP5_8", - "MONITOR_WW2END1_8", - "MONITOR_EE4A3_4", - "MONITOR_FAN3_3", - "MONITOR_SE2A3_5", - "MONITOR_LOGIC_OUTS_B22_2", - "MONITOR_ER1BEG0_8", - "MONITOR_FAN4_3", - "MONITOR_IMUX20_6", - "MONITOR_IMUX15_0", - "MONITOR_WW4END2_7", - "MONITOR_EE2BEG3_6", - "MONITOR_IMUX35_2", - "MONITOR_IMUX39_4", - "MONITOR_BYP1_1", - "MONITOR_SE4BEG3_4", - "MONITOR_IMUX18_7", - "MONITOR_LOGIC_OUTS_B4_2", - "MONITOR_SE4C0_1", - "MONITOR_EE4B1_0", - "MONITOR_NE4C3_4", - "MONITOR_WL1END1_3", - "MONITOR_ER1BEG1_1", - "MONITOR_BLOCK_OUTS_B0_4", - "MONITOR_SW2A1_2", - "MONITOR_LOGIC_OUTS_B7_9", - "MONITOR_IMUX1_9", - "MONITOR_EE2BEG3_2", - "MONITOR_NW4A3_3", - "MONITOR_LH9_6", - "MONITOR_LH5_6", - "MONITOR_LOGIC_OUTS_B19_5", - "MONITOR_BLOCK_OUTS_B3_1", - "MONITOR_BYP3_2", - "MONITOR_CTRL0_0", - "MONITOR_LOGIC_OUTS_B8_2", - "MONITOR_WW2A2_2", - "MONITOR_WW2END3_9", - "MONITOR_IMUX40_5", - "MONITOR_BLOCK_OUTS_B3_7", - "MONITOR_EE4A3_5", - "MONITOR_WR1END0_4", - "MONITOR_EL1BEG0_5", - "MONITOR_SW4A1_4", - "MONITOR_ER1BEG2_7", - "MONITOR_NE4BEG2_3", - "MONITOR_EE4A1_7", - "MONITOR_IMUX27_8", - "MONITOR_EE4A2_3", - "MONITOR_LOGIC_OUTS_B19_1", - "MONITOR_EE2BEG0_8", - "MONITOR_SW4END0_2", - "MONITOR_NE4BEG0_6", - "MONITOR_HORIZ_VAUXN13", - "MONITOR_WL1END0_6", - "MONITOR_SE2A0_3", - "MONITOR_LOGIC_OUTS_B3_5", - "MONITOR_IMUX16_3", - "MONITOR_WW2END3_2", - "MONITOR_WR1END2_8", - "MONITOR_IMUX20_3", - "MONITOR_IMUX32_3", - "MONITOR_IMUX4_6", - "MONITOR_SE4C2_4", - "MONITOR_BYP2_1", - "MONITOR_LH11_2", - "MONITOR_LOGIC_OUTS_B14_9", - "MONITOR_IMUX20_7", - "MONITOR_BYP0_7", - "MONITOR_BYP4_7", - "MONITOR_LOGIC_OUTS_B17_3", - "MONITOR_IMUX34_9", - "MONITOR_SE2A3_7", - "MONITOR_IMUX3_5", - "MONITOR_LH1_6", - "MONITOR_IMUX41_0", - "MONITOR_NE2A2_5", - "MONITOR_IMUX42_0", - "MONITOR_BYP4_2", - "MONITOR_WW4A3_7", - "MONITOR_FAN2_2", - "MONITOR_NW4A0_3", - "MONITOR_FAN7_3", - "MONITOR_SW2A3_5", - "MONITOR_WL1END1_8", - "MONITOR_LOGIC_OUTS_B21_2", - "MONITOR_LOGIC_OUTS_B6_0", - "MONITOR_BYP3_0", - "MONITOR_IMUX5_7", - "MONITOR_IMUX33_4", - "MONITOR_WW2A3_7", - "MONITOR_EE4BEG3_8", - "MONITOR_NE4C2_2", - "MONITOR_WW4A3_1", - "MONITOR_IMUX24_7", - "MONITOR_BYP2_4", - "MONITOR_IMUX21_5", - "MONITOR_NE4C3_9", - "MONITOR_IMUX10_6", - "MONITOR_LOGIC_OUTS_B16_6", - "MONITOR_NE2A2_6", - "MONITOR_IMUX45_3", - "MONITOR_IMUX11_3", - "MONITOR_IMUX14_3", - "MONITOR_SW4A2_0", - "MONITOR_IMUX35_4", - "MONITOR_WW4END2_0", - "MONITOR_CLK0_9", - "MONITOR_SE4BEG0_0", - "MONITOR_NE4C1_7", - "MONITOR_IMUX42_3", - "MONITOR_EE4A2_5", - "MONITOR_SW2A3_4", - "MONITOR_NW2A3_6", - "MONITOR_WL1END2_4", - "MONITOR_EE4BEG1_3", - "MONITOR_IMUX37_8", - "MONITOR_SE4BEG1_0", - "MONITOR_WL1END2_7", - "MONITOR_WW2END3_8", - "MONITOR_EE4B3_7", - "MONITOR_IMUX42_1", - "MONITOR_WW4C0_7", - "MONITOR_IMUX9_9", - "MONITOR_BLOCK_OUTS_B1_1", - "MONITOR_NW4A2_6", - "MONITOR_LOGIC_OUTS_B7_4", - "MONITOR_CTRL1_9", - "MONITOR_FAN6_3", - "MONITOR_BLOCK_OUTS_B1_4", - "MONITOR_IMUX38_0", - "MONITOR_NW2A1_6", - "MONITOR_HORIZ_VAUXP6", - "MONITOR_EE4A1_9", - "MONITOR_SW4A2_1", - "MONITOR_EE2A3_8", - "MONITOR_WL1END3_2", - "MONITOR_NW4END2_1", - "MONITOR_LH10_6", - "MONITOR_WL1END0_3", - "MONITOR_BYP0_5", - "MONITOR_LOGIC_OUTS_B0_6", - "MONITOR_ER1BEG1_8", - "MONITOR_SE4C0_2", - "MONITOR_IMUX1_0", - "MONITOR_LH4_3", - "MONITOR_SW2A3_3", - "MONITOR_IMUX4_8", - "MONITOR_IMUX12_2", - "MONITOR_NW4A3_6", - "MONITOR_SW2A0_3", - "MONITOR_EE4A1_8", - "MONITOR_IMUX39_2", - "MONITOR_LH3_9", - "MONITOR_IMUX12_6", - "MONITOR_IMUX7_7", - "MONITOR_LOGIC_OUTS_B16_8", - "MONITOR_FAN0_5", - "MONITOR_SW4END0_1", - "MONITOR_LH6_8", - "MONITOR_BYP1_7", - "MONITOR_EL1BEG3_9", - "MONITOR_IMUX15_6", - "MONITOR_IMUX10_4", - "MONITOR_LOGIC_OUTS_B6_1", - "MONITOR_WW2A1_6", - "MONITOR_EE4A0_9", - "MONITOR_LH2_3", - "MONITOR_LOGIC_OUTS_B18_7", - "MONITOR_NE2A3_1", - "MONITOR_IMUX47_7", - "MONITOR_NW4END2_5", - "MONITOR_WW4B0_0", - "MONITOR_WW2A3_6", - "MONITOR_WW2END1_3", - "MONITOR_EE4A2_2", - "MONITOR_BYP3_9", - "MONITOR_LH9_9", - "MONITOR_LH6_2", - "MONITOR_EE4C1_4", - "MONITOR_IMUX38_1", - "MONITOR_NE4BEG3_8", - "MONITOR_SE2A0_5", - "MONITOR_EE4B0_2", - "MONITOR_WW4A1_7", - "MONITOR_BLOCK_OUTS_B0_2", - "MONITOR_FAN1_5", - "MONITOR_LOGIC_OUTS_B23_3", - "MONITOR_LH5_5", - "MONITOR_IMUX44_5", - "MONITOR_WW4C0_4", - "MONITOR_SW2A0_0", - "MONITOR_SW2A2_4", - "MONITOR_BLOCK_OUTS_B2_1", - "MONITOR_WW2A2_4", - "MONITOR_WW4C1_0", - "MONITOR_LH11_3", - "MONITOR_IMUX8_6", - "MONITOR_NW4A1_9", - "MONITOR_LOGIC_OUTS_B18_2", - "MONITOR_WW2A0_8", - "MONITOR_LOGIC_OUTS_B8_1", - "MONITOR_FAN4_6", - "MONITOR_IMUX24_3", - "MONITOR_SW4A2_3", - "MONITOR_IMUX42_6", - "MONITOR_IMUX14_8", - "MONITOR_WW4C1_1", - "MONITOR_VERT_VAUXN0", - "MONITOR_LOGIC_OUTS_B9_4", - "MONITOR_IMUX34_7", - "MONITOR_NE4C0_6", - "MONITOR_EL1BEG3_0", - "MONITOR_WW4B0_7", - "MONITOR_LH10_0", - "MONITOR_BLOCK_OUTS_B0_8", - "MONITOR_NW2A3_2", - "MONITOR_EE2A0_0", - "MONITOR_NW4A1_7", - "MONITOR_IMUX46_6", - "MONITOR_BLOCK_OUTS_B1_5", - "MONITOR_EL1BEG3_3", - "MONITOR_WW4A1_0", - "MONITOR_CLK1_6", - "MONITOR_IMUX24_5", - "MONITOR_IMUX8_2", - "MONITOR_LH5_9", - "MONITOR_WR1END3_2", - "MONITOR_IMUX8_3", - "MONITOR_LOGIC_OUTS_B8_5", - "MONITOR_LH4_0", - "MONITOR_WR1END1_3", - "MONITOR_SW4A0_0", - "MONITOR_WR1END1_6", - "MONITOR_NW4END1_8", - "MONITOR_VERT_VAUXN3", - "MONITOR_WL1END0_4", - "MONITOR_SW4A3_1", - "MONITOR_EL1BEG2_4", - "MONITOR_EE4BEG0_3", - "MONITOR_NW4A3_8", - "MONITOR_LOGIC_OUTS_B10_1", - "MONITOR_HORIZ_VAUXN2", - "MONITOR_WW2A3_1", - "MONITOR_EE2BEG1_7", - "MONITOR_BLOCK_OUTS_B2_2", - "MONITOR_ER1BEG3_8", - "MONITOR_SW4END1_0", - "MONITOR_WW4A1_1", - "MONITOR_LH8_9", - "MONITOR_LOGIC_OUTS_B14_2", - "MONITOR_SW2A1_7", - "MONITOR_IMUX2_9", - "MONITOR_WL1END0_5", - "MONITOR_VERT_VAUXP2", - "MONITOR_EL1BEG0_4", - "MONITOR_LOGIC_OUTS_B8_0", - "MONITOR_IMUX37_7", - "MONITOR_IMUX30_8", - "MONITOR_IMUX18_3", - "MONITOR_IMUX34_4", - "MONITOR_IMUX33_6", - "MONITOR_WW4END2_8", - "MONITOR_NE4C1_9", - "MONITOR_IMUX13_5", - "MONITOR_NW4END2_3", - "MONITOR_IMUX35_9", - "MONITOR_EL1BEG2_0", - "MONITOR_IMUX29_8", - "MONITOR_ER1BEG2_8", - "MONITOR_IMUX6_2", - "MONITOR_IMUX38_2", - "MONITOR_SW2A3_8", - "MONITOR_EL1BEG2_6", - "MONITOR_IMUX47_9", - "MONITOR_BLOCK_OUTS_B3_8", - "MONITOR_EE4A3_1", - "MONITOR_BYP0_4", - "MONITOR_IMUX36_5", - "MONITOR_LOGIC_OUTS_B7_7", - "MONITOR_NW2A0_5", - "MONITOR_EE4A2_4", - "MONITOR_LOGIC_OUTS_B9_9", - "MONITOR_IMUX35_8", - "MONITOR_LOGIC_OUTS_B5_5", - "MONITOR_IMUX42_4", - "MONITOR_IMUX47_4", - "MONITOR_EE4B0_8", - "MONITOR_NE2A0_8", - "MONITOR_EE4C1_8", - "MONITOR_SE4C1_3", - "MONITOR_FAN6_7", - "MONITOR_BYP6_8", - "MONITOR_WW4END1_3", - "MONITOR_EE4BEG2_6", - "MONITOR_IMUX14_0", - "MONITOR_WR1END0_0", - "MONITOR_CLK1_8", - "MONITOR_IMUX0_9", - "MONITOR_SW4A2_4", - "MONITOR_LOGIC_OUTS_B19_3", - "MONITOR_LOGIC_OUTS_B18_9", - "MONITOR_IMUX36_1", - "MONITOR_WW2END2_9", - "MONITOR_SW4A0_1", - "MONITOR_NE4BEG3_1", - "MONITOR_SW2A0_8", - "MONITOR_SE2A1_9", - "MONITOR_LOGIC_OUTS_B6_3", - "MONITOR_WW4A2_1", - "MONITOR_SW2A1_3", - "MONITOR_SW4END2_1", - "MONITOR_FAN3_7", - "MONITOR_SE4BEG2_6", - "MONITOR_SE4BEG1_5", - "MONITOR_IMUX33_5", - "MONITOR_WW2END1_5", - "MONITOR_IMUX34_1", - "MONITOR_IMUX9_0", - "MONITOR_EE4A3_8", - "MONITOR_EE4B0_6", - "MONITOR_NW4END1_5", - "MONITOR_LOGIC_OUTS_B10_7", - "MONITOR_IMUX31_9", - "MONITOR_WW4C2_9", - "MONITOR_BLOCK_OUTS_B0_7", - "MONITOR_EL1BEG1_1", - "MONITOR_LOGIC_OUTS_B16_3", - "MONITOR_EE4C2_5", - "MONITOR_LH11_0", - "MONITOR_IMUX39_9", - "MONITOR_WL1END2_2", - "MONITOR_WR1END1_9", - "MONITOR_IMUX22_7", - "MONITOR_NE4C3_8", - "MONITOR_NE4C2_6", - "MONITOR_ER1BEG1_0", - "MONITOR_IMUX42_7", - "MONITOR_IMUX3_9", - "MONITOR_IMUX35_3", - "MONITOR_WW2END0_4", - "MONITOR_BYP6_3", - "MONITOR_IMUX26_8", - "MONITOR_SE4BEG1_7", - "MONITOR_EE4BEG2_2", - "MONITOR_EE2A3_6", - "MONITOR_EE2BEG3_9", - "MONITOR_LOGIC_OUTS_B4_4", - "MONITOR_WW4C3_6", - "MONITOR_ER1BEG2_6", - "MONITOR_IMUX12_9", - "MONITOR_BLOCK_OUTS_B1_0", - "MONITOR_IMUX9_2", - "MONITOR_IMUX33_2", - "MONITOR_CTRL0_4", - "MONITOR_EE4C0_4", - "MONITOR_IMUX26_2", - "MONITOR_LH9_1", - "MONITOR_WW4A3_8", - "MONITOR_IMUX40_0", - "MONITOR_SE2A1_2", - "MONITOR_LOGIC_OUTS_B0_5", - "MONITOR_EE4C3_0", - "MONITOR_FAN3_1", - "MONITOR_IMUX46_2", - "MONITOR_EE2A3_0", - "MONITOR_EE4B0_5", - "MONITOR_WW2A1_8", - "MONITOR_EE4B2_4", - "MONITOR_WW4B0_9", - "MONITOR_VERT_VAUXP14", - "MONITOR_BYP5_3", - "MONITOR_BYP7_4", - "MONITOR_EL1BEG2_2", - "MONITOR_IMUX39_8", - "MONITOR_NE4C1_5", - "MONITOR_NW4END1_2", - "MONITOR_IMUX10_7", - "MONITOR_IMUX0_7", - "MONITOR_IMUX16_6", - "MONITOR_IMUX28_8", - "MONITOR_EE4A0_4", - "MONITOR_WL1END2_6", - "MONITOR_IMUX28_7", - "MONITOR_LH9_7", - "MONITOR_WW4B1_0", - "MONITOR_NW4A0_7", - "MONITOR_LOGIC_OUTS_B22_1", - "MONITOR_NE4BEG1_9", - "MONITOR_IMUX22_2", - "MONITOR_IMUX6_0", - "MONITOR_LOGIC_OUTS_B22_8", - "MONITOR_LH3_2", - "MONITOR_LH7_9", - "MONITOR_FAN6_8", - "MONITOR_LH3_6", - "MONITOR_WW4C0_8", - "MONITOR_BYP4_6", - "MONITOR_EE2BEG2_8", - "MONITOR_NE4C0_9", - "MONITOR_IMUX28_6", - "MONITOR_IMUX1_5", - "MONITOR_WW2A1_4", - "MONITOR_IMUX7_5", - "MONITOR_IMUX22_9", - "MONITOR_IMUX0_3", - "MONITOR_IMUX39_0", - "MONITOR_LOGIC_OUTS_B11_1", - "MONITOR_EE2A2_3", - "MONITOR_IMUX5_2", - "MONITOR_IMUX31_5", - "MONITOR_EE2A2_4", - "MONITOR_IMUX37_0", - "MONITOR_EE2BEG1_9", - "MONITOR_LOGIC_OUTS_B15_7", - "MONITOR_NE4C2_4", - "MONITOR_NE4C0_2", - "MONITOR_SW4A3_7", - "MONITOR_IMUX24_6", - "MONITOR_NW2A2_2", - "MONITOR_FAN2_7", - "MONITOR_EE4A1_5", - "MONITOR_IMUX18_9", - "MONITOR_IMUX2_4", - "MONITOR_IMUX43_5", - "MONITOR_SE4BEG2_7", - "MONITOR_SW4A0_3", - "MONITOR_NW4A1_6", - "MONITOR_LOGIC_OUTS_B4_8", - "MONITOR_EE4A3_9", - "MONITOR_NW4END3_1", - "MONITOR_EE2A1_7", - "MONITOR_SE2A2_7", - "MONITOR_LOGIC_OUTS_B2_2", - "MONITOR_LOGIC_OUTS_B8_3", - "MONITOR_IMUX0_0", - "MONITOR_IMUX20_1", - "MONITOR_LOGIC_OUTS_B19_9", - "MONITOR_SW2A2_3", - "MONITOR_NW2A2_7", - "MONITOR_WW4A1_9", - "MONITOR_IMUX38_9", - "MONITOR_BYP5_5", - "MONITOR_EE4BEG0_6", - "MONITOR_BYP6_4", - "MONITOR_WW4C3_9", - "MONITOR_SW2A1_1", - "MONITOR_SW4END1_6", - "MONITOR_FAN1_2", - "MONITOR_BYP4_0", - "MONITOR_BYP6_6", - "MONITOR_IMUX25_5", - "MONITOR_IMUX11_9", - "MONITOR_LOGIC_OUTS_B0_0", - "MONITOR_WL1END0_0", - "MONITOR_WW2A0_2", - "MONITOR_IMUX0_2", - "MONITOR_EE4B2_8", - "MONITOR_LH9_3", - "MONITOR_LOGIC_OUTS_B1_9", - "MONITOR_FAN6_0", - "MONITOR_FAN3_4", - "MONITOR_EE4BEG3_5", - "MONITOR_LH7_7", - "MONITOR_IMUX38_3", - "MONITOR_NW2A0_0", - "MONITOR_IMUX25_3", - "MONITOR_LOGIC_OUTS_B1_4", - "MONITOR_BLOCK_OUTS_B0_1", - "MONITOR_IMUX46_4", - "MONITOR_NW4A2_3", - "MONITOR_WL1END3_3", - "MONITOR_NW4A1_1", - "MONITOR_IMUX2_3", - "MONITOR_SE2A3_2", - "MONITOR_IMUX29_0", - "MONITOR_BYP3_3", - "MONITOR_EE4A1_1", - "MONITOR_NE2A3_5", - "MONITOR_SW4END2_3", - "MONITOR_LOGIC_OUTS_B3_1", - "MONITOR_ER1BEG3_1", - "MONITOR_IMUX36_7", - "MONITOR_WW2END0_0", - "MONITOR_LH3_7", - "MONITOR_WL1END3_0", - "MONITOR_IMUX36_8", - "MONITOR_WW4END1_8", - "MONITOR_IMUX13_9", - "MONITOR_EE4B1_6", - "MONITOR_IMUX44_3", - "MONITOR_EE4BEG0_9", - "MONITOR_WW4A1_3", - "MONITOR_FAN2_6", - "MONITOR_IMUX22_0", - "MONITOR_NE4BEG3_4", - "MONITOR_IMUX10_5", - "MONITOR_WR1END1_7", - "MONITOR_WW4A3_2", - "MONITOR_NW4END2_7", - "MONITOR_EE4B0_7", - "MONITOR_IMUX41_8", - "MONITOR_LOGIC_OUTS_B6_9", - "MONITOR_IMUX32_5", - "MONITOR_IMUX7_4", - "MONITOR_NE4BEG2_2", - "MONITOR_VERT_VAUXN9", - "MONITOR_EE2BEG0_4", - "MONITOR_IMUX28_2", - "MONITOR_IMUX29_5", - "MONITOR_IMUX31_0", - "MONITOR_NE2A3_9", - "MONITOR_IMUX38_6", - "MONITOR_IMUX20_0", - "MONITOR_LOGIC_OUTS_B5_8", - "MONITOR_BLOCK_OUTS_B3_4", - "MONITOR_SE4BEG0_2", - "MONITOR_NW4A2_7", - "MONITOR_CLK1_9", - "MONITOR_NW4A3_9", - "MONITOR_WR1END3_8", - "MONITOR_VERT_VAUXP6", - "MONITOR_SE2A3_6", - "MONITOR_NE2A2_9", - "MONITOR_VERT_VAUXN1", - "MONITOR_ER1BEG0_4", - "MONITOR_NE4C1_3", - "MONITOR_WW4C1_5", - "MONITOR_SW4END3_0", - "MONITOR_NW2A3_7", - "MONITOR_LOGIC_OUTS_B9_7", - "MONITOR_ER1BEG1_9", - "MONITOR_IMUX27_9", - "MONITOR_IMUX33_8", - "MONITOR_FAN0_4", - "MONITOR_IMUX9_1", - "MONITOR_LOGIC_OUTS_B0_2", - "MONITOR_SE4BEG2_2", - "MONITOR_EE2A0_6", - "MONITOR_IMUX26_0", - "MONITOR_WW2A1_0", - "MONITOR_WW4B3_9", - "MONITOR_LOGIC_OUTS_B18_0", - "MONITOR_EE4BEG1_1", - "MONITOR_NW4END2_0", - "MONITOR_WW4A2_8", - "MONITOR_LH9_4", - "MONITOR_EE2BEG2_4", - "MONITOR_NW2A2_6", - "MONITOR_NE2A2_4", - "MONITOR_LH6_7", - "MONITOR_BLOCK_OUTS_B3_5", - "MONITOR_IMUX19_2", - "MONITOR_IMUX13_0", - "MONITOR_LOGIC_OUTS_B2_0", - "MONITOR_SW4END0_6", - "MONITOR_LOGIC_OUTS_B20_1", - "MONITOR_SW4A2_2", - "MONITOR_SE2A2_8", - "MONITOR_BYP0_0", - "MONITOR_LOGIC_OUTS_B17_1", - "MONITOR_NE4BEG3_6", - "MONITOR_IMUX4_3", - "MONITOR_EE4C0_3", - "MONITOR_EE2BEG3_1", - "MONITOR_EE4BEG1_7", - "MONITOR_IMUX37_1", - "MONITOR_EE2BEG1_1", - "MONITOR_IMUX34_0", - "MONITOR_WW4A0_3", - "MONITOR_IMUX9_3", - "MONITOR_IMUX46_8", - "MONITOR_NW4A3_4", - "MONITOR_SW4END1_3", - "MONITOR_SE2A3_0", - "MONITOR_IMUX10_3", - "MONITOR_WW4A3_3", - "MONITOR_IMUX22_1", - "MONITOR_HORIZ_VAUXP2", - "MONITOR_WW4END2_9", - "MONITOR_SE4C0_9", - "MONITOR_EL1BEG3_7", - "MONITOR_SE2A3_8", - "MONITOR_SW2A3_0", - "MONITOR_WW2END1_6", - "MONITOR_EE4B1_5", - "MONITOR_IMUX43_4", - "MONITOR_IMUX25_6", - "MONITOR_IMUX36_0", - "MONITOR_IMUX28_0", - "MONITOR_WR1END3_6", - "MONITOR_WW4C1_4", - "MONITOR_EE4C3_2", - "MONITOR_NW4END1_1", - "MONITOR_LH7_4", - "MONITOR_WW4B2_8", - "MONITOR_SW4A1_2", - "MONITOR_IMUX7_0", - "MONITOR_SE4C0_5", - "MONITOR_SE2A3_1", - "MONITOR_WW2END3_6", - "MONITOR_IMUX20_2", - "MONITOR_CLK0_4", - "MONITOR_LH12_4", - "MONITOR_IMUX36_9", - "MONITOR_LH12_9", - "MONITOR_IMUX45_0", - "MONITOR_EE4BEG3_2", - "MONITOR_LH4_6", - "MONITOR_IMUX43_3", - "MONITOR_WW2A3_0", - "MONITOR_WL1END3_8", - "MONITOR_IMUX5_1", - "MONITOR_BYP1_2", - "MONITOR_EE4BEG3_3", - "MONITOR_FAN1_7", - "MONITOR_IMUX21_9", - "MONITOR_FAN7_5", - "MONITOR_SW4END0_9", - "MONITOR_EE4C2_4", - "MONITOR_WW4C0_3", - "MONITOR_FAN5_1", - "MONITOR_EE2BEG0_6", - "MONITOR_IMUX35_0", - "MONITOR_IMUX7_1", - "MONITOR_IMUX19_7", - "MONITOR_LOGIC_OUTS_B12_7", - "MONITOR_NW4END1_4", - "MONITOR_WW4B3_7", - "MONITOR_EE4C3_8", - "MONITOR_NW2A0_3", - "MONITOR_NW2A1_8", - "MONITOR_SW4END3_8", - "MONITOR_EE2A1_3", - "MONITOR_LOGIC_OUTS_B13_0", - "MONITOR_IMUX14_9", - "MONITOR_LH6_5", - "MONITOR_SW2A0_1", - "MONITOR_LOGIC_OUTS_B14_6", - "MONITOR_BLOCK_OUTS_B3_3", - "MONITOR_EE2BEG1_2", - "MONITOR_IMUX41_1", - "MONITOR_NW4END0_4", - "MONITOR_IMUX9_8", - "MONITOR_EE2BEG0_7", - "MONITOR_IMUX17_1", - "MONITOR_NE2A1_4", - "MONITOR_IMUX44_1", - "MONITOR_IMUX45_9", - "MONITOR_NW4END1_7", - "MONITOR_IMUX44_0", - "MONITOR_IMUX19_9", - "MONITOR_NW4END3_6", - "MONITOR_LH12_2", - "MONITOR_LOGIC_OUTS_B3_9", - "MONITOR_LOGIC_OUTS_B9_6", - "MONITOR_LOGIC_OUTS_B13_7", - "MONITOR_IMUX47_6", - "MONITOR_EE2BEG0_3", - "MONITOR_WW2END3_1", - "MONITOR_LOGIC_OUTS_B18_4", - "MONITOR_EE4B2_5", - "MONITOR_SE4C3_3", - "MONITOR_WW2A3_4", - "MONITOR_LOGIC_OUTS_B9_2", - "MONITOR_LOGIC_OUTS_B10_3", - "MONITOR_WR1END3_9", - "MONITOR_IMUX39_5", - "MONITOR_BYP6_1", - "MONITOR_LH2_7", - "MONITOR_SW4A1_3", - "MONITOR_IMUX4_9", - "MONITOR_IMUX8_9", - "MONITOR_LOGIC_OUTS_B18_1", - "MONITOR_LOGIC_OUTS_B22_9", - "MONITOR_WW4C3_5", - "MONITOR_LH8_5", - "MONITOR_BYP2_5", - "MONITOR_NW2A2_4", - "MONITOR_IMUX11_8", - "MONITOR_IMUX30_5", - "MONITOR_CLK0_8", - "MONITOR_WW2END0_6", - "MONITOR_WR1END2_0", - "MONITOR_IMUX20_5", - "MONITOR_WW4B3_4", - "MONITOR_SW4END2_2", - "MONITOR_LH10_8", - "MONITOR_EL1BEG0_0", - "MONITOR_WW4A1_2", - "MONITOR_LOGIC_OUTS_B14_8", - "MONITOR_LOGIC_OUTS_B8_9", - "MONITOR_BYP0_2", - "MONITOR_NE4BEG0_0", - "MONITOR_LH8_0", - "MONITOR_EE4BEG1_2", - "MONITOR_LOGIC_OUTS_B18_6", - "MONITOR_WW4C2_8", - "MONITOR_IMUX6_7", - "MONITOR_CTRL0_8", - "MONITOR_IMUX41_5", - "MONITOR_FAN4_8", - "MONITOR_NE4BEG2_8", - "MONITOR_SE4C2_1", - "MONITOR_IMUX10_0", - "MONITOR_LOGIC_OUTS_B22_5", - "MONITOR_FAN2_1", - "MONITOR_WW4B2_1", - "MONITOR_SW4END1_5", - "MONITOR_FAN1_1", - "MONITOR_BYP1_9", - "MONITOR_LOGIC_OUTS_B15_3", - "MONITOR_NE4BEG1_2", - "MONITOR_NW4A1_0", - "MONITOR_LH10_3", - "MONITOR_IMUX43_9", - "MONITOR_BYP4_1", - "MONITOR_NE2A2_7", - "MONITOR_EE2A3_1", - "MONITOR_SE4C2_8", - "MONITOR_BYP1_4", - "MONITOR_CLK0_2", - "MONITOR_EE2A2_6", - "MONITOR_SE4BEG2_4", - "MONITOR_SE4C2_2", - "MONITOR_ER1BEG0_5", - "MONITOR_IMUX7_2", - "MONITOR_IMUX16_4", - "MONITOR_EE4B3_6", - "MONITOR_WW4END1_6", - "MONITOR_EE4C0_2", - "MONITOR_LOGIC_OUTS_B20_6", - "MONITOR_EE2A3_3", - "MONITOR_IMUX25_7", - "MONITOR_NW4A2_0", - "MONITOR_NW4A0_2", - "MONITOR_SE4BEG1_2", - "MONITOR_WL1END0_2", - "MONITOR_FAN0_2", - "MONITOR_EE4BEG3_1", - "MONITOR_WW4C2_7", - "MONITOR_LOGIC_OUTS_B7_6", - "MONITOR_LOGIC_OUTS_B1_3", - "MONITOR_IMUX5_9", - "MONITOR_ER1BEG1_7", - "MONITOR_IMUX19_3", - "MONITOR_BYP5_2", - "MONITOR_NW4END3_5", - "MONITOR_NE2A1_5", - "MONITOR_WW2A0_4", - "MONITOR_WL1END2_9", - "MONITOR_NW4END2_6", - "MONITOR_IMUX25_9", - "MONITOR_WL1END3_1", - "MONITOR_EE4BEG2_0", - "MONITOR_IMUX40_1", - "MONITOR_IMUX32_6", - "MONITOR_WW2A0_3", - "MONITOR_LOGIC_OUTS_B14_4", - "MONITOR_NE4BEG3_3", - "MONITOR_LH10_1", - "MONITOR_FAN7_2", - "MONITOR_EL1BEG0_3", - "MONITOR_LH8_6", - "MONITOR_CTRL0_2", - "MONITOR_SE2A2_0", - "MONITOR_BYP3_1", - "MONITOR_NE2A3_8", - "MONITOR_LOGIC_OUTS_B5_0", - "MONITOR_SW4A1_0", - "MONITOR_LH9_8", - "MONITOR_IMUX37_4", - "MONITOR_NE2A3_0", - "MONITOR_WW2END2_2", - "MONITOR_WW4C3_3", - "MONITOR_IMUX38_7", - "MONITOR_IMUX16_1", - "MONITOR_NE2A0_5", - "MONITOR_SW4END1_4", - "MONITOR_NW2A0_4", - "MONITOR_EE4A3_0", - "MONITOR_NE4C1_6", - "MONITOR_EE4C0_9", - "MONITOR_LH12_6", - "MONITOR_SW2A3_1", - "MONITOR_ER1BEG3_4", - "MONITOR_EE2A1_4", - "MONITOR_LOGIC_OUTS_B15_5", - "MONITOR_LOGIC_OUTS_B8_8", - "MONITOR_WR1END3_3", - "MONITOR_LH3_1", - "MONITOR_NE4C3_1", - "MONITOR_WW2A2_7", - "MONITOR_LOGIC_OUTS_B22_6", - "MONITOR_FAN5_6", - "MONITOR_SW4END2_7", - "MONITOR_FAN5_5", - "MONITOR_FAN6_1", - "MONITOR_IMUX22_3", - "MONITOR_BYP4_5", - "MONITOR_EL1BEG1_8", - "MONITOR_ER1BEG0_2", - "MONITOR_EE4A2_0", - "MONITOR_CTRL1_4", - "MONITOR_LOGIC_OUTS_B15_8", - "MONITOR_IMUX12_8", - "MONITOR_WW4B2_6", - "MONITOR_FAN4_5", - "MONITOR_WW4C2_6", - "MONITOR_IMUX14_7", - "MONITOR_IMUX29_2", - "MONITOR_SE4BEG3_6", - "MONITOR_WW4END1_9", - "MONITOR_LOGIC_OUTS_B11_2", - "MONITOR_LH1_8", - "MONITOR_IMUX39_1", - "MONITOR_EE2BEG2_6", - "MONITOR_LH11_7", - "MONITOR_NE4C2_0", - "MONITOR_WW4A0_9", - "MONITOR_SW4END2_0", - "MONITOR_SE2A0_7", - "MONITOR_EL1BEG1_0", - "MONITOR_EE2BEG2_1", - "MONITOR_IMUX24_8", - "MONITOR_FAN5_0", - "MONITOR_IMUX22_8", - "MONITOR_NW2A1_5", - "MONITOR_EE4BEG1_6", - "MONITOR_BYP0_8", - "MONITOR_LOGIC_OUTS_B9_1", - "MONITOR_NE4C2_5", - "MONITOR_WW4END3_3", - "MONITOR_IMUX22_5", - "MONITOR_IMUX26_4", - "MONITOR_IMUX5_5", - "MONITOR_IMUX3_1", - "MONITOR_EE4BEG1_4", - "MONITOR_VERT_VAUXN13", - "MONITOR_IMUX40_7", - "MONITOR_EE4B0_1", - "MONITOR_EE4C1_7", - "MONITOR_LOGIC_OUTS_B3_4", - "MONITOR_HORIZ_VAUXN5", - "MONITOR_LOGIC_OUTS_B20_4", - "MONITOR_HORIZ_VAUXN9", - "MONITOR_WL1END0_8", - "MONITOR_FAN5_8", - "MONITOR_IMUX36_3", - "MONITOR_LOGIC_OUTS_B4_3", - "MONITOR_LOGIC_OUTS_B6_7", - "MONITOR_EE2A1_9", - "MONITOR_IMUX17_3", - "MONITOR_BYP6_2", - "MONITOR_NW2A1_7", - "MONITOR_BYP7_7", - "MONITOR_BYP3_4", - "MONITOR_WW2END2_4", - "MONITOR_LH1_7", - "MONITOR_IMUX20_4", - "MONITOR_IMUX1_6", - "MONITOR_WR1END2_6", - "MONITOR_LH10_9", - "MONITOR_WW2END0_8", - "MONITOR_IMUX29_9", - "MONITOR_LH12_3", - "MONITOR_NW4A1_5", - "MONITOR_WR1END0_5", - "MONITOR_WR1END2_5", - "MONITOR_IMUX21_4", - "MONITOR_SE2A1_0", - "MONITOR_EL1BEG1_7", - "MONITOR_FAN2_5", - "MONITOR_NW4END2_4", - "MONITOR_WR1END2_1", - "MONITOR_NW2A1_9", - "MONITOR_IMUX0_1", - "MONITOR_ER1BEG0_9", - "MONITOR_FAN0_8", - "MONITOR_LOGIC_OUTS_B23_9", - "MONITOR_SE4BEG3_8", - "MONITOR_NW4END2_2", - "MONITOR_WW2END1_7", - "MONITOR_SE4C1_2", - "MONITOR_BLOCK_OUTS_B1_6", - "MONITOR_NE4C3_0", - "MONITOR_LH6_0", - "MONITOR_SE4BEG1_6", - "MONITOR_IMUX41_4", - "MONITOR_EE2A0_5", - "MONITOR_IMUX6_3", - "MONITOR_SW4END3_5", - "MONITOR_LOGIC_OUTS_B20_3", - "MONITOR_LOGIC_OUTS_B13_6", - "MONITOR_BLOCK_OUTS_B3_6", - "MONITOR_BYP1_0", - "MONITOR_LOGIC_OUTS_B13_4", - "MONITOR_SE4C1_8", - "MONITOR_NW4A3_7", - "MONITOR_IMUX18_8", - "MONITOR_LOGIC_OUTS_B14_3", - "MONITOR_SW2A3_6", - "MONITOR_NE4C3_7", - "MONITOR_IMUX16_7", - "MONITOR_IMUX38_8", - "MONITOR_SW4A3_2", - "MONITOR_FAN2_9", - "MONITOR_NE4BEG1_5", - "MONITOR_LOGIC_OUTS_B14_1", - "MONITOR_FAN3_5", - "MONITOR_LOGIC_OUTS_B12_5", - "MONITOR_BLOCK_OUTS_B2_8", - "MONITOR_NE4BEG1_4", - "MONITOR_IMUX13_6", - "MONITOR_WW2END1_0", - "MONITOR_WW2A0_6", - "MONITOR_IMUX26_1", - "MONITOR_IMUX0_5", - "MONITOR_NE4C0_7", - "MONITOR_WW2A2_3", - "MONITOR_EE4C3_9", - "MONITOR_IMUX45_8", - "MONITOR_EE4B3_2", - "MONITOR_NE4C1_4", - "MONITOR_EE4C3_5", - "MONITOR_SE2A2_5", - "MONITOR_EE4A3_6", - "MONITOR_NW4A1_4", - "MONITOR_ER1BEG0_0", - "MONITOR_EL1BEG3_2", - "MONITOR_LOGIC_OUTS_B22_4", - "MONITOR_ER1BEG2_9", - "MONITOR_WW4B3_0", - "MONITOR_NE4BEG1_7", - "MONITOR_WW2END3_0", - "MONITOR_FAN3_0", - "MONITOR_SE4BEG0_7", - "MONITOR_IMUX24_1", - "MONITOR_SE4BEG3_3", - "MONITOR_NW4END2_8", - "MONITOR_IMUX14_5", - "MONITOR_IMUX2_2", - "MONITOR_IMUX41_2", - "MONITOR_IMUX16_8", - "MONITOR_EE2A0_9", - "MONITOR_IMUX8_5", - "MONITOR_IMUX20_8", - "MONITOR_WW4B1_7", - "MONITOR_EL1BEG2_3", - "MONITOR_LH3_0", - "MONITOR_SW4END0_8", - "MONITOR_NE4C0_1", - "MONITOR_LOGIC_OUTS_B5_9", - "MONITOR_IMUX27_0", - "MONITOR_NW4A2_9", - "MONITOR_NE2A0_0", - "MONITOR_EE2BEG2_0", - "MONITOR_SW2A0_5", - "MONITOR_NE4C0_3", - "MONITOR_SE4BEG0_4", - "MONITOR_LOGIC_OUTS_B4_0", - "MONITOR_LOGIC_OUTS_B0_9", - "MONITOR_EE2BEG2_5", - "MONITOR_IMUX37_5", - "MONITOR_LH4_9", - "MONITOR_IMUX0_8", - "MONITOR_EE4BEG0_4", - "MONITOR_CTRL1_2", - "MONITOR_EE2A3_4", - "MONITOR_SE4BEG2_3", - "MONITOR_CLK1_1", - "MONITOR_EE4A1_4", - "MONITOR_NW2A1_0", - "MONITOR_WW4END2_4", - "MONITOR_IMUX15_2", - "MONITOR_LOGIC_OUTS_B11_5", - "MONITOR_BYP5_7", - "MONITOR_NE2A3_6", - "MONITOR_EE4BEG0_0", - "MONITOR_ER1BEG2_0", - "MONITOR_WW4C0_9", - "MONITOR_IMUX5_3", - "MONITOR_LOGIC_OUTS_B21_1", - "MONITOR_IMUX30_4", - "MONITOR_IMUX26_6", - "MONITOR_IMUX31_4", - "MONITOR_NE4BEG0_8", - "MONITOR_WW2A0_9", - "MONITOR_EE2A2_5", - "MONITOR_BLOCK_OUTS_B0_0", - "MONITOR_WW4C1_3", - "MONITOR_WW4A3_9", - "MONITOR_WW4A2_3", - "MONITOR_NW2A2_0", - "MONITOR_LH2_2", - "MONITOR_IMUX2_1", - "MONITOR_IMUX17_7", - "MONITOR_FAN0_0", - "MONITOR_IMUX21_2", - "MONITOR_LOGIC_OUTS_B21_8", - "MONITOR_IMUX34_2", - "MONITOR_WW4A2_4", - "MONITOR_IMUX37_3", - "MONITOR_NE2A3_2", - "MONITOR_FAN7_9", - "MONITOR_LOGIC_OUTS_B2_3", - "MONITOR_IMUX12_3", - "MONITOR_NE2A2_1", - "MONITOR_LH12_1", - "MONITOR_NE2A0_6", - "MONITOR_NE2A2_8", - "MONITOR_NE2A3_7", - "MONITOR_WW4END0_2", - "MONITOR_IMUX0_6", - "MONITOR_IMUX15_1", - "MONITOR_LOGIC_OUTS_B23_2", - "MONITOR_LOGIC_OUTS_B13_1", - "MONITOR_LOGIC_OUTS_B5_4", - "MONITOR_LOGIC_OUTS_B17_9", - "MONITOR_LH11_5", - "MONITOR_IMUX35_1", - "MONITOR_IMUX40_9", - "MONITOR_IMUX15_5", - "MONITOR_NW2A1_4", - "MONITOR_SE4BEG2_0", - "MONITOR_IMUX32_4", - "MONITOR_LOGIC_OUTS_B15_1", - "MONITOR_WW4B1_8", - "MONITOR_NE4BEG3_7", - "MONITOR_FAN5_4", - "MONITOR_SW2A2_2", - "MONITOR_EE2A1_6", - "MONITOR_VERT_VAUXP3", - "MONITOR_WW4A0_2", - "MONITOR_LH12_5", - "MONITOR_LH1_3", - "MONITOR_WW4B3_2", - "MONITOR_SW2A2_1", - "MONITOR_SE2A0_6", - "MONITOR_LH8_4", - "MONITOR_EE4C0_1", - "MONITOR_VERT_VAUXP10", - "MONITOR_SW4A3_5", - "MONITOR_IMUX11_5", - "MONITOR_EE4BEG0_5", - "MONITOR_NE4BEG2_4", - "MONITOR_IMUX21_6", - "MONITOR_VERT_VAUXP1", - "MONITOR_NE4BEG3_9", - "MONITOR_LH2_1", - "MONITOR_IMUX23_5", - "MONITOR_IMUX29_1", - "MONITOR_NW4A0_0", - "MONITOR_LOGIC_OUTS_B16_7", - "MONITOR_WW2END0_1", - "MONITOR_SW4END2_9", - "MONITOR_LOGIC_OUTS_B17_4", - "MONITOR_IMUX17_8", - "MONITOR_WW4B2_0", - "MONITOR_WW4C0_2", - "MONITOR_EE2BEG2_3", - "MONITOR_IMUX16_9", - "MONITOR_NE4C3_5", - "MONITOR_WR1END1_4", - "MONITOR_BYP2_2", - "MONITOR_IMUX37_2", - "MONITOR_FAN5_3", - "MONITOR_WW4B2_4", - "MONITOR_LOGIC_OUTS_B12_9", - "MONITOR_SW2A1_4", - "MONITOR_IMUX11_6", - "MONITOR_LOGIC_OUTS_B12_0", - "MONITOR_LH7_2", - "MONITOR_LOGIC_OUTS_B19_8", - "MONITOR_IMUX5_6", - "MONITOR_WW4A2_0", - "MONITOR_IMUX26_7", - "MONITOR_LOGIC_OUTS_B3_8", - "MONITOR_SW4A3_8", - "MONITOR_WW4C2_4", - "MONITOR_WW4B3_1", - "MONITOR_IMUX41_3", - "MONITOR_IMUX30_7", - "MONITOR_NW2A3_3", - "MONITOR_EE4B1_8", - "MONITOR_NW4END3_3", - "MONITOR_BLOCK_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B21_5", - "MONITOR_LOGIC_OUTS_B10_0", - "MONITOR_NW4A0_5", - "MONITOR_IMUX33_3", - "MONITOR_LH5_8", - "MONITOR_WW4END1_1", - "MONITOR_IMUX13_8", - "MONITOR_CTRL0_5", - "MONITOR_WR1END3_7", - "MONITOR_NW4A2_5", - "MONITOR_SW4A2_9", - "MONITOR_BYP7_9", - "MONITOR_IMUX34_8", - "MONITOR_LOGIC_OUTS_B2_4", - "MONITOR_LOGIC_OUTS_B0_7", - "MONITOR_BLOCK_OUTS_B0_6", - "MONITOR_IMUX33_0", - "MONITOR_NW4A2_1", - "MONITOR_VERT_VAUXP5", - "MONITOR_NW2A3_5", - "MONITOR_SW4A3_0", - "MONITOR_FAN5_2", - "MONITOR_WW4B2_3", - "MONITOR_SE4BEG0_1", - "MONITOR_WW2A1_1", - "MONITOR_WW4B0_3", - "MONITOR_WL1END2_1", - "MONITOR_NE4C1_0", - "MONITOR_LOGIC_OUTS_B0_4", - "MONITOR_WW2A3_5", - "MONITOR_FAN4_1", - "MONITOR_NE2A3_3", - "MONITOR_FAN6_4", - "MONITOR_LH2_4", - "MONITOR_IMUX44_7", - "MONITOR_IMUX13_4", - "MONITOR_BYP5_0", - "MONITOR_IMUX39_7", - "MONITOR_HORIZ_VAUXN6", - "MONITOR_EE4C0_7", - "MONITOR_WW2END0_7", - "MONITOR_IMUX26_3", - "MONITOR_WL1END1_7", - "MONITOR_LOGIC_OUTS_B5_7", - "MONITOR_BYP7_5", - "MONITOR_WW4END3_1", - "MONITOR_FAN3_8", - "MONITOR_LH5_1", - "MONITOR_IMUX26_5", - "MONITOR_IMUX3_4", - "MONITOR_IMUX41_6", - "MONITOR_NW4END3_8", - "MONITOR_NE4BEG0_4", - "MONITOR_WW4END2_5", - "MONITOR_LOGIC_OUTS_B17_5", - "MONITOR_LOGIC_OUTS_B16_5", - "MONITOR_WW2END1_1", - "MONITOR_ER1BEG2_1", - "MONITOR_BYP3_5", - "MONITOR_EE4B2_3", - "MONITOR_EL1BEG1_3", - "MONITOR_WW2END2_6", - "MONITOR_FAN4_4", - "MONITOR_EE2BEG3_3", - "MONITOR_ER1BEG0_1", - "MONITOR_NE2A2_0", - "MONITOR_WW2END3_5", - "MONITOR_EE2BEG1_5", - "MONITOR_IMUX23_7", - "MONITOR_SW2A0_7", - "MONITOR_EE2BEG0_2", - "MONITOR_WW2END2_1", - "MONITOR_EE4BEG3_4", - "MONITOR_HORIZ_VAUXP9", - "MONITOR_SE2A3_3", - "MONITOR_SE4C1_9", - "MONITOR_SW4A0_5", - "MONITOR_IMUX18_1", - "MONITOR_LOGIC_OUTS_B10_8", - "MONITOR_IMUX27_1", - "MONITOR_IMUX8_1", - "MONITOR_BLOCK_OUTS_B2_0", - "MONITOR_LOGIC_OUTS_B21_3", - "MONITOR_EE4BEG2_9", - "MONITOR_SW2A0_4", - "MONITOR_SW4A1_5", - "MONITOR_FAN1_6", - "MONITOR_WW4B1_5", - "MONITOR_IMUX39_6", - "MONITOR_IMUX15_8", - "MONITOR_BLOCK_OUTS_B2_6", - "MONITOR_SE4BEG2_9", - "MONITOR_NW4A0_9", - "MONITOR_NE2A0_7", - "MONITOR_LOGIC_OUTS_B12_4", - "MONITOR_EE4A0_3", - "MONITOR_LOGIC_OUTS_B12_6", - "MONITOR_EE4B1_1", - "MONITOR_WW2END0_3", - "MONITOR_NW4END2_9", - "MONITOR_BYP5_9", - "MONITOR_NW2A2_8", - "MONITOR_IMUX39_3", - "MONITOR_IMUX16_2", - "MONITOR_LOGIC_OUTS_B3_3", - "MONITOR_SE4BEG1_1", - "MONITOR_IMUX23_3", - "MONITOR_SE4BEG0_3", - "MONITOR_IMUX42_9", - "MONITOR_EE4B0_3", - "MONITOR_WW2END2_5", - "MONITOR_WL1END1_1", - "MONITOR_WW4A0_0", - "MONITOR_NW4A0_6", - "MONITOR_WW4A2_9", - "MONITOR_NW2A0_7", - "MONITOR_NW4A2_2", - "MONITOR_SE4C1_4", - "MONITOR_BYP3_8", - "MONITOR_WW4END0_7", - "MONITOR_SE4C3_8", - "MONITOR_EE4BEG2_1", - "MONITOR_LH4_8", - "MONITOR_CTRL1_5", - "MONITOR_NE4C2_8", - "MONITOR_NW4A2_4", - "MONITOR_EL1BEG0_8", - "MONITOR_LH8_1", - "MONITOR_WW4C2_0", - "MONITOR_LOGIC_OUTS_B6_4", - "MONITOR_SE4C3_1", - "MONITOR_IMUX1_7", - "MONITOR_SW4END1_1", - "MONITOR_EE4C3_4", - "MONITOR_IMUX29_4", - "MONITOR_IMUX44_4", - "MONITOR_SE4C1_5", - "MONITOR_NW2A3_8", - "MONITOR_SE4C0_0", - "MONITOR_SW4END2_4", - "MONITOR_LOGIC_OUTS_B7_1", - "MONITOR_EE4A1_3", - "MONITOR_BLOCK_OUTS_B1_9", - "MONITOR_IMUX45_1", - "MONITOR_IMUX38_4", - "MONITOR_WR1END2_7", - "MONITOR_LOGIC_OUTS_B10_9", - "MONITOR_VERT_VAUXP15", - "MONITOR_EE4C2_2", - "MONITOR_EE2BEG3_7", - "MONITOR_IMUX32_7", - "MONITOR_EL1BEG2_5", - "MONITOR_LOGIC_OUTS_B17_0", - "MONITOR_WW2A1_2", - "MONITOR_EE4A0_7", - "MONITOR_IMUX19_5", - "MONITOR_EE4C0_0", - "MONITOR_IMUX12_1", - "MONITOR_CLK0_6", - "MONITOR_IMUX21_8", - "MONITOR_EL1BEG2_1", - "MONITOR_BYP0_1", - "MONITOR_SE4C3_5", - "MONITOR_VERT_VAUXN6", - "MONITOR_EE2BEG2_7", - "MONITOR_LOGIC_OUTS_B11_3", - "MONITOR_LH7_8", - "MONITOR_WW4C3_1", - "MONITOR_EE4C3_1", - "MONITOR_IMUX44_8", - "MONITOR_IMUX22_6", - "MONITOR_WW4C0_5", - "MONITOR_IMUX40_4", - "MONITOR_WW2A2_8", - "MONITOR_IMUX44_9", - "MONITOR_LH9_0", - "MONITOR_CLK0_0", - "MONITOR_NW2A3_9", - "MONITOR_IMUX21_0", - "MONITOR_NE4BEG2_0", - "MONITOR_BYP7_6", - "MONITOR_CTRL1_8", - "MONITOR_LH4_1", - "MONITOR_LH7_0", - "MONITOR_LH11_4", - "MONITOR_WW2END1_9", - "MONITOR_IMUX27_6", - "MONITOR_LOGIC_OUTS_B13_2", - "MONITOR_WR1END0_6", - "MONITOR_NE2A2_3", - "MONITOR_WW4END2_1", - "MONITOR_IMUX44_6", - "MONITOR_EE4B2_2", - "MONITOR_LOGIC_OUTS_B19_4", - "MONITOR_WW4END1_7", - "MONITOR_WW2END0_2", - "MONITOR_EL1BEG2_7", - "MONITOR_ER1BEG3_2", - "MONITOR_FAN2_8", - "MONITOR_IMUX31_2", - "MONITOR_LOGIC_OUTS_B21_7", - "MONITOR_IMUX1_2", - "MONITOR_LH1_2", - "MONITOR_NE4BEG2_7", - "MONITOR_EE2BEG0_9", - "MONITOR_IMUX32_9", - "MONITOR_LOGIC_OUTS_B1_1", - "MONITOR_IMUX16_0", - "MONITOR_WW4END2_3", - "MONITOR_WW2A3_3", - "MONITOR_EL1BEG1_2", - "MONITOR_BLOCK_OUTS_B2_9", - "MONITOR_NE2A0_1", - "MONITOR_BYP7_0", - "MONITOR_SW2A2_8", - "MONITOR_NE4BEG2_6", - "MONITOR_EE2A0_3", - "MONITOR_EE4B0_0", - "MONITOR_WW4A0_7", - "MONITOR_BYP0_9", - "MONITOR_IMUX15_7", - "MONITOR_LOGIC_OUTS_B5_6", - "MONITOR_WL1END1_4", - "MONITOR_EL1BEG2_8", - "MONITOR_FAN1_3", - "MONITOR_EE4C0_6", - "MONITOR_IMUX23_8", - "MONITOR_WW4END0_0", - "MONITOR_NE4BEG1_3", - "MONITOR_LOGIC_OUTS_B2_7", - "MONITOR_EE4B3_9", - "MONITOR_EE4A1_6", - "MONITOR_EL1BEG3_8", - "MONITOR_WW4A0_8", - "MONITOR_LOGIC_OUTS_B17_2", - "MONITOR_CLK1_7", - "MONITOR_WW2A2_1", - "MONITOR_WW4C2_2", - "MONITOR_EE2BEG1_4", - "MONITOR_IMUX34_6", - "MONITOR_SE2A0_2", - "MONITOR_LOGIC_OUTS_B20_7", - "MONITOR_BYP6_5", - "MONITOR_NE2A1_7", - "MONITOR_WW4B0_6", - "MONITOR_LH4_2", - "MONITOR_WW2A1_5", - "MONITOR_EE4BEG0_1", - "MONITOR_SE4BEG0_8", - "MONITOR_BYP4_9", - "MONITOR_IMUX1_1", - "MONITOR_EE2A2_9", - "MONITOR_WW4A0_4", - "MONITOR_WW4A1_5", - "MONITOR_SE2A2_4", - "MONITOR_NW2A0_9", - "MONITOR_SW2A3_2", - "MONITOR_LOGIC_OUTS_B21_4", - "MONITOR_EE4A0_8", - "MONITOR_SE4C3_4", - "MONITOR_EE4B3_4", - "MONITOR_EE2BEG2_9", - "MONITOR_WW4END0_3", - "MONITOR_LOGIC_OUTS_B23_0", - "MONITOR_EL1BEG3_4", - "MONITOR_SW4A3_9", - "MONITOR_CTRL1_7", - "MONITOR_IMUX17_4", - "MONITOR_LOGIC_OUTS_B2_9", - "MONITOR_EE4C3_3", - "MONITOR_BYP4_4", - "MONITOR_IMUX13_3", - "MONITOR_IMUX4_0", - "MONITOR_NE4C0_5", - "MONITOR_IMUX14_2", - "MONITOR_SW4END3_4", - "MONITOR_NE2A1_9", - "MONITOR_LOGIC_OUTS_B7_3", - "MONITOR_EE4A1_2", - "MONITOR_LOGIC_OUTS_B18_3", - "MONITOR_EL1BEG3_6", - "MONITOR_SE4BEG2_8", - "MONITOR_ER1BEG3_6", - "MONITOR_SE4BEG3_1", - "MONITOR_IMUX43_2", - "MONITOR_SW4A0_2", - "MONITOR_SE2A1_5", - "MONITOR_NE2A3_4", - "MONITOR_LH3_3", - "MONITOR_IMUX47_1", - "MONITOR_IMUX22_4", - "MONITOR_LOGIC_OUTS_B13_8", - "MONITOR_WW4A0_6", - "MONITOR_WW4C0_0", - "MONITOR_IMUX13_2", - "MONITOR_IMUX33_9", - "MONITOR_NE4C1_2", - "MONITOR_IMUX32_0", - "MONITOR_NE2A0_3", - "MONITOR_HORIZ_VAUXP13", - "MONITOR_BYP5_1", - "MONITOR_IMUX25_4", - "MONITOR_EE4C2_6", - "MONITOR_BYP7_8", - "MONITOR_WW4A2_5", - "MONITOR_NE4BEG0_2", - "MONITOR_SW2A2_7", - "MONITOR_EE4BEG3_0", - "MONITOR_WW4B1_9", - "MONITOR_WW2END2_7", - "MONITOR_EE4C2_3", - "MONITOR_IMUX15_9", - "MONITOR_IMUX1_3", - "MONITOR_SE2A2_6", - "MONITOR_IMUX1_4", - "MONITOR_WW4END3_2", - "MONITOR_WL1END1_9", - "MONITOR_LH12_8", - "MONITOR_SE4BEG3_9", - "MONITOR_WW4C1_8", - "MONITOR_WW2A2_6", - "MONITOR_IMUX37_6", - "MONITOR_LH8_7", - "MONITOR_SW4A1_8", - "MONITOR_NE2A2_2", - "MONITOR_LOGIC_OUTS_B22_7", - "MONITOR_SW4A0_9", - "MONITOR_IMUX29_6", - "MONITOR_NE4BEG3_5", - "MONITOR_WW4A0_5", - "MONITOR_WW4B3_5", - "MONITOR_LH3_8", - "MONITOR_IMUX23_4", - "MONITOR_EE4C2_0", - "MONITOR_LOGIC_OUTS_B3_7", - "MONITOR_BLOCK_OUTS_B1_8", - "MONITOR_EE4BEG2_4", - "MONITOR_IMUX44_2", - "MONITOR_NE4C3_3", - "MONITOR_WW4END1_0", - "MONITOR_LOGIC_OUTS_B13_3", - "MONITOR_WW4END3_5", - "MONITOR_IMUX2_8", - "MONITOR_LOGIC_OUTS_B0_1", - "MONITOR_LOGIC_OUTS_B14_7", - "MONITOR_SW2A0_6", - "MONITOR_BYP2_8", - "MONITOR_NW4END0_7", - "MONITOR_WR1END3_5", - "MONITOR_EE2BEG3_4", - "MONITOR_SW4A0_8", - "MONITOR_WL1END3_5", - "MONITOR_SW4END0_0", - "MONITOR_LH5_2", - "MONITOR_EE4BEG2_7", - "MONITOR_LH8_3", - "MONITOR_NW4A1_3", - "MONITOR_EE4B3_3", - "MONITOR_EE4BEG1_5", - "MONITOR_NW4END0_0", - "MONITOR_EE2BEG1_0", - "MONITOR_IMUX11_2", - "MONITOR_WW4END0_8", - "MONITOR_NW4A3_5", - "MONITOR_EE4BEG3_7", - "MONITOR_FAN7_0", - "MONITOR_BYP2_3", - "MONITOR_EE4A0_6", - "MONITOR_BYP4_3", - "MONITOR_SE4BEG3_2", - "MONITOR_WW4A2_7", - "MONITOR_IMUX20_9", - "MONITOR_FAN0_3", - "MONITOR_IMUX7_9", - "MONITOR_VERT_VAUXN15", - "MONITOR_LOGIC_OUTS_B16_9", - "MONITOR_LOGIC_OUTS_B4_1", - "MONITOR_VERT_VAUXP0", - "MONITOR_IMUX9_5", - "MONITOR_EE2A2_0", - "MONITOR_NW4END3_0", - "MONITOR_CTRL1_0", - "MONITOR_IMUX5_4", - "MONITOR_IMUX11_4", - "MONITOR_IMUX2_6", - "MONITOR_EE2BEG3_8", - "MONITOR_EL1BEG3_5", - "MONITOR_ER1BEG3_0", - "MONITOR_EE2A2_1", - "MONITOR_IMUX43_7", - "MONITOR_WW4C1_9", - "MONITOR_IMUX45_4", - "MONITOR_LH3_4", - "MONITOR_NE2A0_2", - "MONITOR_EE4B2_0", - "MONITOR_SE4C3_6", - "MONITOR_WW4END1_2", - "MONITOR_SE4C1_0", - "MONITOR_IMUX25_1", - "MONITOR_VERT_VAUXN10", - "MONITOR_NE2A1_1", - "MONITOR_SE2A2_1", - "MONITOR_SW2A1_0", - "MONITOR_SW4A1_1", - "MONITOR_LOGIC_OUTS_B9_8", - "MONITOR_LOGIC_OUTS_B8_7", - "MONITOR_SW4END3_9", - "MONITOR_SW4END0_3", - "MONITOR_EE4C1_2", - "MONITOR_EL1BEG0_6", - "MONITOR_EE4A3_2", - "MONITOR_LH5_0", - "MONITOR_SW4A3_4", - "MONITOR_IMUX31_6", - "MONITOR_IMUX17_5", - "MONITOR_SE4BEG3_0", - "MONITOR_FAN7_1", - "MONITOR_LH10_5", - "MONITOR_IMUX34_3", - "MONITOR_LH7_5", - "MONITOR_LOGIC_OUTS_B1_6", - "MONITOR_IMUX3_7", - "MONITOR_WW4END3_6", - "MONITOR_SW4END2_6", - "MONITOR_LOGIC_OUTS_B14_0", - "MONITOR_WW2A0_5", - "MONITOR_LH2_5", - "MONITOR_SW2A2_0", - "MONITOR_VERT_VAUXN2", - "MONITOR_SE2A2_3", - "MONITOR_IMUX30_1", - "MONITOR_IMUX28_5", - "MONITOR_SE2A3_9", - "MONITOR_EE2A0_4", - "MONITOR_EE2BEG2_2", - "MONITOR_WW4B1_1", - "MONITOR_EL1BEG0_2", - "MONITOR_ER1BEG0_7", - "MONITOR_LOGIC_OUTS_B23_1", - "MONITOR_NW4END0_5", - "MONITOR_WL1END2_3", - "MONITOR_WW4END0_5", - "MONITOR_WW2A3_2", - "MONITOR_BYP1_5", - "MONITOR_WW4C1_6", - "MONITOR_LH4_7", - "MONITOR_LOGIC_OUTS_B23_8", - "MONITOR_WL1END0_1", - "MONITOR_IMUX45_7", - "MONITOR_FAN6_9", - "MONITOR_EE2BEG0_1", - "MONITOR_SE4BEG2_5", - "MONITOR_LOGIC_OUTS_B20_5", - "MONITOR_WW4A1_4", - "MONITOR_ER1BEG3_9", - "MONITOR_CTRL0_7", - "MONITOR_WW4C3_2", - "MONITOR_SE4BEG0_9", - "MONITOR_EE4B1_9", - "MONITOR_LH1_4", - "MONITOR_EE4B0_9", - "MONITOR_LOGIC_OUTS_B10_6", - "MONITOR_LH1_1", - "MONITOR_SE2A1_7", - "MONITOR_IMUX46_0", - "MONITOR_FAN4_0", - "MONITOR_LOGIC_OUTS_B7_0", - "MONITOR_EL1BEG1_4", - "MONITOR_CLK1_4", - "MONITOR_BLOCK_OUTS_B2_7", - "MONITOR_IMUX28_1", - "MONITOR_LOGIC_OUTS_B20_0", - "MONITOR_IMUX10_9", - "MONITOR_NE4C3_6", - "MONITOR_NE4BEG0_7", - "MONITOR_IMUX11_7", - "MONITOR_LOGIC_OUTS_B4_9", - "MONITOR_IMUX34_5", - "MONITOR_WW4END0_6", - "MONITOR_IMUX4_5", - "MONITOR_IMUX19_1", - "MONITOR_BYP6_7", - "MONITOR_FAN3_6", - "MONITOR_SE4BEG1_4", - "MONITOR_SE4C0_8" - ], - "sites": [], "pips": { "MONITOR_MID.MONITOR_HORIZ_VAUXN6->MONITOR_VERT_VAUXN6": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN6", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXN6", - "is_pseudo": "0" - }, - "MONITOR_MID.MONITOR_HORIZ_VAUXP5->MONITOR_VERT_VAUXP5": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP5", "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN6" }, "MONITOR_MID.MONITOR_HORIZ_VAUXN9->MONITOR_VERT_VAUXN9": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN9", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXN9", - "is_pseudo": "0" - }, - "MONITOR_MID.MONITOR_HORIZ_VAUXP1->MONITOR_VERT_VAUXP1": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP1", "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN9" }, "MONITOR_MID.MONITOR_HORIZ_VAUXN2->MONITOR_VERT_VAUXN2": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN2", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXN2", - "is_pseudo": "0" - }, - "MONITOR_MID.MONITOR_HORIZ_VAUXP9->MONITOR_VERT_VAUXP9": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP9", "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP9", - "is_pseudo": "0" - }, - "MONITOR_MID.MONITOR_HORIZ_VAUXN5->MONITOR_VERT_VAUXN5": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN5", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN5", - "is_pseudo": "0" - }, - "MONITOR_MID.MONITOR_HORIZ_VAUXP6->MONITOR_VERT_VAUXP6": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP6", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP6", - "is_pseudo": "0" - }, - "MONITOR_MID.MONITOR_HORIZ_VAUXP13->MONITOR_VERT_VAUXP13": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP13", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP13", - "is_pseudo": "0" - }, - "MONITOR_MID.MONITOR_HORIZ_VAUXN1->MONITOR_VERT_VAUXN1": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN1", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN2" }, "MONITOR_MID.MONITOR_HORIZ_VAUXP2->MONITOR_VERT_VAUXP2": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXP2", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXP2", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP2" + }, + "MONITOR_MID.MONITOR_HORIZ_VAUXP1->MONITOR_VERT_VAUXP1": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP1" + }, + "MONITOR_MID.MONITOR_HORIZ_VAUXP5->MONITOR_VERT_VAUXP5": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP5" + }, + "MONITOR_MID.MONITOR_HORIZ_VAUXP13->MONITOR_VERT_VAUXP13": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP13" + }, + "MONITOR_MID.MONITOR_HORIZ_VAUXP6->MONITOR_VERT_VAUXP6": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP6" + }, + "MONITOR_MID.MONITOR_HORIZ_VAUXN5->MONITOR_VERT_VAUXN5": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN5" + }, + "MONITOR_MID.MONITOR_HORIZ_VAUXP9->MONITOR_VERT_VAUXP9": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXP9" }, "MONITOR_MID.MONITOR_HORIZ_VAUXN13->MONITOR_VERT_VAUXN13": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_VAUXN13", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXN13", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN13" + }, + "MONITOR_MID.MONITOR_HORIZ_VAUXN1->MONITOR_VERT_VAUXN1": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_VAUXN1" } }, - "tile_type": "MONITOR_MID" + "wires": [ + "MONITOR_SW4END3_2", + "MONITOR_WW4B1_3", + "MONITOR_IMUX4_1", + "MONITOR_NW4END2_9", + "MONITOR_FAN0_2", + "MONITOR_WW4END3_0", + "MONITOR_EE2A2_7", + "MONITOR_NE4C3_1", + "MONITOR_LH2_3", + "MONITOR_IMUX23_6", + "MONITOR_LOGIC_OUTS_B19_7", + "MONITOR_CLK0_0", + "MONITOR_IMUX42_3", + "MONITOR_NW2A1_0", + "MONITOR_NW4END1_9", + "MONITOR_SE4BEG3_2", + "MONITOR_IMUX24_0", + "MONITOR_IMUX4_2", + "MONITOR_EE2A0_6", + "MONITOR_IMUX37_3", + "MONITOR_LH6_2", + "MONITOR_WW2END3_8", + "MONITOR_LOGIC_OUTS_B0_3", + "MONITOR_WW4C1_3", + "MONITOR_IMUX3_9", + "MONITOR_LOGIC_OUTS_B14_6", + "MONITOR_LH4_6", + "MONITOR_LH6_9", + "MONITOR_LOGIC_OUTS_B23_4", + "MONITOR_LOGIC_OUTS_B4_2", + "MONITOR_SW4A2_3", + "MONITOR_NW4A2_1", + "MONITOR_LOGIC_OUTS_B9_6", + "MONITOR_EE4C0_7", + "MONITOR_IMUX6_0", + "MONITOR_CLK1_5", + "MONITOR_SW4A2_2", + "MONITOR_LH6_1", + "MONITOR_EE4C2_0", + "MONITOR_IMUX35_5", + "MONITOR_BYP7_8", + "MONITOR_WR1END1_2", + "MONITOR_IMUX32_6", + "MONITOR_BYP6_3", + "MONITOR_LH4_5", + "MONITOR_WW4C2_3", + "MONITOR_FAN3_9", + "MONITOR_LOGIC_OUTS_B16_0", + "MONITOR_IMUX4_0", + "MONITOR_SE4BEG3_6", + "MONITOR_IMUX1_3", + "MONITOR_WW4A0_6", + "MONITOR_LOGIC_OUTS_B6_6", + "MONITOR_VERT_VAUXP7", + "MONITOR_NW2A1_6", + "MONITOR_IMUX14_3", + "MONITOR_WW4C0_8", + "MONITOR_IMUX41_2", + "MONITOR_IMUX27_0", + "MONITOR_LH10_2", + "MONITOR_IMUX12_3", + "MONITOR_SE4C1_3", + "MONITOR_EE4B2_5", + "MONITOR_SE4BEG0_5", + "MONITOR_WW4B3_4", + "MONITOR_BYP5_6", + "MONITOR_BYP7_6", + "MONITOR_WW4END1_7", + "MONITOR_WR1END1_1", + "MONITOR_EE4BEG1_8", + "MONITOR_NE2A3_8", + "MONITOR_IMUX31_6", + "MONITOR_LOGIC_OUTS_B4_9", + "MONITOR_BLOCK_OUTS_B1_0", + "MONITOR_IMUX41_4", + "MONITOR_NE4BEG2_2", + "MONITOR_BYP5_4", + "MONITOR_NW4A3_6", + "MONITOR_IMUX11_3", + "MONITOR_IMUX20_1", + "MONITOR_NW2A3_7", + "MONITOR_CLK0_5", + "MONITOR_WW4C3_6", + "MONITOR_CTRL1_6", + "MONITOR_EE2BEG0_3", + "MONITOR_IMUX19_3", + "MONITOR_WW2A0_3", + "MONITOR_IMUX5_6", + "MONITOR_BYP0_5", + "MONITOR_WW2A1_4", + "MONITOR_BYP4_4", + "MONITOR_SW2A2_2", + "MONITOR_NW4A2_9", + "MONITOR_SE2A0_2", + "MONITOR_SW4END1_7", + "MONITOR_EE4A0_4", + "MONITOR_SE2A3_4", + "MONITOR_WR1END0_4", + "MONITOR_SE4C0_9", + "MONITOR_SE4BEG1_8", + "MONITOR_LOGIC_OUTS_B20_2", + "MONITOR_SE4C2_0", + "MONITOR_EE4B0_4", + "MONITOR_BYP7_9", + "MONITOR_EE4BEG3_9", + "MONITOR_WW4C1_8", + "MONITOR_EE2A1_2", + "MONITOR_IMUX27_1", + "MONITOR_EE2BEG3_6", + "MONITOR_EE4C3_0", + "MONITOR_IMUX18_4", + "MONITOR_EE2BEG2_7", + "MONITOR_EE4A1_7", + "MONITOR_WW2A3_1", + "MONITOR_FAN7_5", + "MONITOR_EE2A0_2", + "MONITOR_EE4BEG1_4", + "MONITOR_VERT_VAUXN1", + "MONITOR_SW4A3_6", + "MONITOR_NE4C2_2", + "MONITOR_SW4A1_7", + "MONITOR_FAN1_2", + "MONITOR_BLOCK_OUTS_B0_2", + "MONITOR_IMUX29_1", + "MONITOR_LH4_7", + "MONITOR_IMUX24_8", + "MONITOR_FAN1_0", + "MONITOR_IMUX38_7", + "MONITOR_NE4C1_8", + "MONITOR_SW2A1_2", + "MONITOR_LOGIC_OUTS_B1_2", + "MONITOR_IMUX3_8", + "MONITOR_WW4B1_2", + "MONITOR_EE4A3_2", + "MONITOR_IMUX31_1", + "MONITOR_FAN6_9", + "MONITOR_IMUX34_2", + "MONITOR_NE2A3_6", + "MONITOR_SW4A1_9", + "MONITOR_NE2A1_7", + "MONITOR_SE4BEG3_4", + "MONITOR_IMUX20_3", + "MONITOR_FAN5_9", + "MONITOR_BYP4_8", + "MONITOR_LOGIC_OUTS_B7_5", + "MONITOR_IMUX25_2", + "MONITOR_LH11_8", + "MONITOR_EE4A3_4", + "MONITOR_SE4C0_5", + "MONITOR_NW4END2_2", + "MONITOR_WL1END2_9", + "MONITOR_WR1END1_8", + "MONITOR_LOGIC_OUTS_B7_2", + "MONITOR_IMUX21_1", + "MONITOR_SE4BEG1_4", + "MONITOR_EL1BEG0_2", + "MONITOR_BLOCK_OUTS_B3_4", + "MONITOR_LOGIC_OUTS_B21_6", + "MONITOR_NW4A2_4", + "MONITOR_LOGIC_OUTS_B18_3", + "MONITOR_IMUX23_4", + "MONITOR_LOGIC_OUTS_B5_5", + "MONITOR_SE2A2_4", + "MONITOR_EE4C3_3", + "MONITOR_EE4C2_6", + "MONITOR_IMUX26_9", + "MONITOR_EL1BEG3_8", + "MONITOR_LOGIC_OUTS_B5_4", + "MONITOR_IMUX40_1", + "MONITOR_SW4END3_1", + "MONITOR_SE4C3_3", + "MONITOR_LOGIC_OUTS_B15_4", + "MONITOR_IMUX40_7", + "MONITOR_EE4BEG0_3", + "MONITOR_EE4B1_6", + "MONITOR_LH11_1", + "MONITOR_WW2A0_6", + "MONITOR_LOGIC_OUTS_B16_1", + "MONITOR_LH1_3", + "MONITOR_IMUX1_5", + "MONITOR_FAN5_4", + "MONITOR_FAN3_3", + "MONITOR_LOGIC_OUTS_B16_2", + "MONITOR_WW4A0_5", + "MONITOR_EE4BEG0_4", + "MONITOR_SE2A1_9", + "MONITOR_NW2A3_6", + "MONITOR_LH8_6", + "MONITOR_IMUX45_9", + "MONITOR_LH2_0", + "MONITOR_LH1_2", + "MONITOR_IMUX31_4", + "MONITOR_FAN0_0", + "MONITOR_BLOCK_OUTS_B3_8", + "MONITOR_IMUX13_6", + "MONITOR_NE4C2_5", + "MONITOR_SW4A2_0", + "MONITOR_LOGIC_OUTS_B11_8", + "MONITOR_NE4C3_4", + "MONITOR_IMUX32_9", + "MONITOR_NE4C3_6", + "MONITOR_LH12_4", + "MONITOR_BYP7_4", + "MONITOR_WW2END0_1", + "MONITOR_EE2A1_7", + "MONITOR_NW2A2_1", + "MONITOR_SE2A3_2", + "MONITOR_VERT_VAUXP6", + "MONITOR_WW2A0_8", + "MONITOR_WW4C3_0", + "MONITOR_NE4BEG2_0", + "MONITOR_WW4END1_3", + "MONITOR_WW4C0_4", + "MONITOR_IMUX4_8", + "MONITOR_EE4BEG1_5", + "MONITOR_HORIZ_VAUXN5", + "MONITOR_EE4B0_8", + "MONITOR_IMUX19_4", + "MONITOR_NE4BEG2_4", + "MONITOR_IMUX0_6", + "MONITOR_IMUX23_5", + "MONITOR_CLK1_9", + "MONITOR_BLOCK_OUTS_B2_9", + "MONITOR_NW4END3_6", + "MONITOR_BLOCK_OUTS_B1_3", + "MONITOR_IMUX30_8", + "MONITOR_NE4C3_7", + "MONITOR_IMUX3_4", + "MONITOR_SE4C3_7", + "MONITOR_FAN7_0", + "MONITOR_EE4B0_1", + "MONITOR_NE4C0_3", + "MONITOR_LOGIC_OUTS_B5_0", + "MONITOR_LOGIC_OUTS_B21_2", + "MONITOR_SW4A1_0", + "MONITOR_IMUX38_0", + "MONITOR_CTRL0_3", + "MONITOR_FAN5_6", + "MONITOR_EE4BEG1_2", + "MONITOR_EE4B0_7", + "MONITOR_IMUX4_7", + "MONITOR_NE4BEG2_3", + "MONITOR_NE4BEG3_5", + "MONITOR_NE2A0_7", + "MONITOR_IMUX43_3", + "MONITOR_EL1BEG3_2", + "MONITOR_NW4A0_3", + "MONITOR_LH7_2", + "MONITOR_WW4A2_2", + "MONITOR_IMUX36_3", + "MONITOR_FAN7_4", + "MONITOR_LOGIC_OUTS_B3_2", + "MONITOR_LH4_2", + "MONITOR_WW4END3_6", + "MONITOR_NE4C2_7", + "MONITOR_ER1BEG2_2", + "MONITOR_SW4A2_7", + "MONITOR_IMUX5_0", + "MONITOR_NW4A1_2", + "MONITOR_SW2A3_7", + "MONITOR_CTRL1_7", + "MONITOR_IMUX34_4", + "MONITOR_LOGIC_OUTS_B5_2", + "MONITOR_LH5_9", + "MONITOR_SE4C0_3", + "MONITOR_EE4A1_1", + "MONITOR_IMUX34_3", + "MONITOR_NE4BEG3_7", + "MONITOR_NW4A3_0", + "MONITOR_LOGIC_OUTS_B10_4", + "MONITOR_IMUX21_2", + "MONITOR_IMUX2_2", + "MONITOR_EE2A0_9", + "MONITOR_IMUX36_0", + "MONITOR_IMUX40_2", + "MONITOR_NE2A1_8", + "MONITOR_WW2END3_2", + "MONITOR_IMUX36_6", + "MONITOR_LH5_1", + "MONITOR_SE4BEG3_8", + "MONITOR_IMUX39_9", + "MONITOR_WL1END3_3", + "MONITOR_LOGIC_OUTS_B1_9", + "MONITOR_HORIZ_VAUXP6", + "MONITOR_BYP5_7", + "MONITOR_WW4A0_3", + "MONITOR_EE4B0_5", + "MONITOR_EL1BEG1_2", + "MONITOR_EL1BEG1_0", + "MONITOR_IMUX46_9", + "MONITOR_SE4C2_1", + "MONITOR_EE4BEG2_0", + "MONITOR_BYP1_6", + "MONITOR_NE4C3_3", + "MONITOR_IMUX31_3", + "MONITOR_LOGIC_OUTS_B10_0", + "MONITOR_LOGIC_OUTS_B7_6", + "MONITOR_EE4BEG3_3", + "MONITOR_WW4END0_1", + "MONITOR_SW4END3_9", + "MONITOR_IMUX12_6", + "MONITOR_NE4BEG0_2", + "MONITOR_WL1END3_9", + "MONITOR_EE2BEG3_4", + "MONITOR_IMUX34_7", + "MONITOR_LH2_4", + "MONITOR_EL1BEG3_0", + "MONITOR_IMUX14_5", + "MONITOR_IMUX35_4", + "MONITOR_NW4END3_0", + "MONITOR_IMUX45_4", + "MONITOR_IMUX27_4", + "MONITOR_IMUX19_9", + "MONITOR_LOGIC_OUTS_B17_7", + "MONITOR_EE4A3_9", + "MONITOR_WW4B3_5", + "MONITOR_WW4A2_1", + "MONITOR_LH11_0", + "MONITOR_SE2A0_0", + "MONITOR_WW4A1_8", + "MONITOR_EE2A2_8", + "MONITOR_SW4A3_9", + "MONITOR_SW4END3_0", + "MONITOR_EE4A2_3", + "MONITOR_BYP0_2", + "MONITOR_IMUX29_4", + "MONITOR_NE4BEG0_7", + "MONITOR_NW4END1_2", + "MONITOR_VERT_VAUXN10", + "MONITOR_WW4END2_0", + "MONITOR_WW4A3_6", + "MONITOR_NW2A1_2", + "MONITOR_BYP3_0", + "MONITOR_NE4C0_8", + "MONITOR_NE4BEG2_8", + "MONITOR_LOGIC_OUTS_B23_2", + "MONITOR_WL1END2_7", + "MONITOR_LH4_9", + "MONITOR_SE2A3_0", + "MONITOR_WR1END2_1", + "MONITOR_WW4A3_2", + "MONITOR_LH11_3", + "MONITOR_IMUX30_0", + "MONITOR_EE4B1_2", + "MONITOR_LOGIC_OUTS_B16_3", + "MONITOR_LOGIC_OUTS_B3_6", + "MONITOR_NE4BEG0_8", + "MONITOR_LH11_4", + "MONITOR_WW4C1_6", + "MONITOR_EE2BEG3_2", + "MONITOR_NW4A3_4", + "MONITOR_LOGIC_OUTS_B6_5", + "MONITOR_WW4B2_1", + "MONITOR_ER1BEG1_7", + "MONITOR_WW2END1_8", + "MONITOR_IMUX1_0", + "MONITOR_ER1BEG2_5", + "MONITOR_IMUX16_5", + "MONITOR_IMUX46_6", + "MONITOR_IMUX17_2", + "MONITOR_IMUX11_2", + "MONITOR_BYP5_8", + "MONITOR_IMUX21_8", + "MONITOR_LOGIC_OUTS_B14_5", + "MONITOR_WR1END3_2", + "MONITOR_SE4BEG1_1", + "MONITOR_IMUX32_4", + "MONITOR_LOGIC_OUTS_B1_3", + "MONITOR_IMUX33_2", + "MONITOR_FAN6_1", + "MONITOR_LOGIC_OUTS_B17_4", + "MONITOR_NW2A2_7", + "MONITOR_IMUX27_2", + "MONITOR_WR1END3_5", + "MONITOR_SW4A1_2", + "MONITOR_WW4END2_8", + "MONITOR_SW4END0_2", + "MONITOR_LOGIC_OUTS_B4_7", + "MONITOR_EE4B3_5", + "MONITOR_FAN2_4", + "MONITOR_LH1_1", + "MONITOR_SE2A2_6", + "MONITOR_SW4A2_5", + "MONITOR_IMUX30_1", + "MONITOR_ER1BEG2_8", + "MONITOR_LH9_5", + "MONITOR_NW2A2_3", + "MONITOR_LH1_0", + "MONITOR_LOGIC_OUTS_B2_3", + "MONITOR_LOGIC_OUTS_B7_3", + "MONITOR_EE4C0_9", + "MONITOR_SW2A2_9", + "MONITOR_SW4END3_7", + "MONITOR_WW2END2_3", + "MONITOR_SW4END1_2", + "MONITOR_LOGIC_OUTS_B8_6", + "MONITOR_LOGIC_OUTS_B18_1", + "MONITOR_LOGIC_OUTS_B3_0", + "MONITOR_IMUX33_5", + "MONITOR_BYP6_0", + "MONITOR_IMUX32_8", + "MONITOR_WL1END1_3", + "MONITOR_WW4END1_4", + "MONITOR_IMUX21_5", + "MONITOR_BYP0_0", + "MONITOR_BYP7_0", + "MONITOR_FAN1_6", + "MONITOR_SW4A2_4", + "MONITOR_CTRL1_4", + "MONITOR_LOGIC_OUTS_B14_0", + "MONITOR_WW2END3_5", + "MONITOR_IMUX20_2", + "MONITOR_WR1END2_8", + "MONITOR_SE4C1_2", + "MONITOR_IMUX39_4", + "MONITOR_SW2A3_0", + "MONITOR_BLOCK_OUTS_B2_4", + "MONITOR_IMUX40_8", + "MONITOR_ER1BEG3_1", + "MONITOR_EE4A1_3", + "MONITOR_IMUX44_2", + "MONITOR_SE2A2_8", + "MONITOR_EE2BEG1_6", + "MONITOR_IMUX43_5", + "MONITOR_IMUX40_5", + "MONITOR_IMUX4_9", + "MONITOR_LOGIC_OUTS_B11_5", + "MONITOR_IMUX35_6", + "MONITOR_EE4C1_5", + "MONITOR_FAN3_6", + "MONITOR_SE4C2_6", + "MONITOR_EE4C3_7", + "MONITOR_IMUX1_7", + "MONITOR_BYP3_4", + "MONITOR_LOGIC_OUTS_B22_6", + "MONITOR_FAN3_7", + "MONITOR_CLK0_2", + "MONITOR_NE4BEG0_1", + "MONITOR_IMUX0_0", + "MONITOR_EE4C1_2", + "MONITOR_SW2A0_7", + "MONITOR_EE2BEG2_2", + "MONITOR_FAN2_5", + "MONITOR_IMUX28_1", + "MONITOR_NE2A3_5", + "MONITOR_WW4B0_4", + "MONITOR_LOGIC_OUTS_B2_2", + "MONITOR_IMUX22_5", + "MONITOR_IMUX35_3", + "MONITOR_NE2A0_9", + "MONITOR_WR1END0_3", + "MONITOR_IMUX10_9", + "MONITOR_CLK1_7", + "MONITOR_SE2A3_8", + "MONITOR_EE2A3_9", + "MONITOR_EE4A1_4", + "MONITOR_WW4C1_0", + "MONITOR_NE4BEG1_3", + "MONITOR_EL1BEG1_6", + "MONITOR_EL1BEG1_8", + "MONITOR_EE2A3_0", + "MONITOR_IMUX28_8", + "MONITOR_LOGIC_OUTS_B8_5", + "MONITOR_IMUX33_7", + "MONITOR_WW2A2_6", + "MONITOR_WW2A3_5", + "MONITOR_WL1END3_6", + "MONITOR_LH1_4", + "MONITOR_BLOCK_OUTS_B0_5", + "MONITOR_CLK1_6", + "MONITOR_SW4END3_4", + "MONITOR_WW2A1_3", + "MONITOR_SE4C1_5", + "MONITOR_EE2A1_6", + "MONITOR_NW4A2_5", + "MONITOR_EE4B3_4", + "MONITOR_IMUX17_7", + "MONITOR_LOGIC_OUTS_B13_6", + "MONITOR_IMUX28_4", + "MONITOR_EE4B3_3", + "MONITOR_SW2A3_6", + "MONITOR_CTRL0_6", + "MONITOR_IMUX46_4", + "MONITOR_EE2BEG0_0", + "MONITOR_NW2A1_9", + "MONITOR_SW4END1_0", + "MONITOR_EE2A3_4", + "MONITOR_WW2A2_1", + "MONITOR_LOGIC_OUTS_B18_7", + "MONITOR_ER1BEG2_4", + "MONITOR_WW2END1_7", + "MONITOR_SE4BEG2_6", + "MONITOR_IMUX0_3", + "MONITOR_WR1END3_3", + "MONITOR_IMUX16_8", + "MONITOR_LH3_8", + "MONITOR_WW4B2_2", + "MONITOR_SE4C0_0", + "MONITOR_IMUX38_4", + "MONITOR_EE4A0_6", + "MONITOR_IMUX5_5", + "MONITOR_WL1END3_8", + "MONITOR_NW4A1_0", + "MONITOR_LOGIC_OUTS_B9_0", + "MONITOR_ER1BEG1_0", + "MONITOR_SE2A1_2", + "MONITOR_IMUX46_3", + "MONITOR_IMUX46_8", + "MONITOR_WW4END1_5", + "MONITOR_EE4BEG3_5", + "MONITOR_NE4BEG3_0", + "MONITOR_LH12_5", + "MONITOR_IMUX21_0", + "MONITOR_IMUX13_4", + "MONITOR_SE2A1_1", + "MONITOR_NE4C3_8", + "MONITOR_WW2A3_9", + "MONITOR_BLOCK_OUTS_B3_6", + "MONITOR_SE2A0_3", + "MONITOR_NW2A2_8", + "MONITOR_BLOCK_OUTS_B2_3", + "MONITOR_LH9_8", + "MONITOR_BYP4_0", + "MONITOR_LOGIC_OUTS_B17_8", + "MONITOR_WW2END3_9", + "MONITOR_IMUX23_8", + "MONITOR_WL1END2_2", + "MONITOR_IMUX8_3", + "MONITOR_LOGIC_OUTS_B2_0", + "MONITOR_WR1END1_3", + "MONITOR_IMUX47_5", + "MONITOR_NW4A0_8", + "MONITOR_IMUX20_0", + "MONITOR_WW2END1_9", + "MONITOR_WW4A2_9", + "MONITOR_LH12_1", + "MONITOR_WW4C2_7", + "MONITOR_EE2A2_5", + "MONITOR_BYP2_2", + "MONITOR_IMUX42_4", + "MONITOR_IMUX43_1", + "MONITOR_WL1END1_2", + "MONITOR_NW4A3_2", + "MONITOR_BYP3_7", + "MONITOR_CTRL0_5", + "MONITOR_IMUX23_9", + "MONITOR_FAN2_2", + "MONITOR_IMUX15_9", + "MONITOR_WR1END3_4", + "MONITOR_SE4BEG2_3", + "MONITOR_EE4B1_8", + "MONITOR_FAN5_5", + "MONITOR_SE4C2_4", + "MONITOR_WW2END2_2", + "MONITOR_WW2A0_7", + "MONITOR_SW4A1_1", + "MONITOR_LOGIC_OUTS_B1_5", + "MONITOR_LOGIC_OUTS_B12_1", + "MONITOR_EL1BEG2_3", + "MONITOR_LOGIC_OUTS_B16_6", + "MONITOR_NE2A0_0", + "MONITOR_FAN3_4", + "MONITOR_IMUX23_7", + "MONITOR_EE4B2_1", + "MONITOR_SW2A1_9", + "MONITOR_BYP5_2", + "MONITOR_LH5_5", + "MONITOR_LOGIC_OUTS_B21_7", + "MONITOR_WW4B3_9", + "MONITOR_LOGIC_OUTS_B21_0", + "MONITOR_EE4B3_8", + "MONITOR_FAN2_0", + "MONITOR_NW2A3_2", + "MONITOR_IMUX22_1", + "MONITOR_VERT_VAUXP4", + "MONITOR_NW2A0_7", + "MONITOR_WW4END3_7", + "MONITOR_IMUX9_0", + "MONITOR_EE4BEG0_7", + "MONITOR_CLK0_3", + "MONITOR_WW4C1_4", + "MONITOR_SW4END2_0", + "MONITOR_WR1END1_9", + "MONITOR_SW2A1_4", + "MONITOR_BLOCK_OUTS_B1_6", + "MONITOR_IMUX17_3", + "MONITOR_LOGIC_OUTS_B18_6", + "MONITOR_LOGIC_OUTS_B2_9", + "MONITOR_WW4C3_7", + "MONITOR_BLOCK_OUTS_B3_5", + "MONITOR_LH10_4", + "MONITOR_LOGIC_OUTS_B4_4", + "MONITOR_VERT_VAUXP15", + "MONITOR_LOGIC_OUTS_B16_4", + "MONITOR_SE2A1_5", + "MONITOR_WW4B1_6", + "MONITOR_FAN2_3", + "MONITOR_EE4C1_9", + "MONITOR_SE2A0_8", + "MONITOR_IMUX21_3", + "MONITOR_ER1BEG2_7", + "MONITOR_IMUX14_9", + "MONITOR_EE2A0_8", + "MONITOR_IMUX39_7", + "MONITOR_NW2A2_4", + "MONITOR_NW4A2_0", + "MONITOR_IMUX25_7", + "MONITOR_EE4B2_7", + "MONITOR_NW4A0_6", + "MONITOR_EE4BEG1_9", + "MONITOR_WW2A3_3", + "MONITOR_EE4B3_2", + "MONITOR_VERT_VAUXN4", + "MONITOR_IMUX27_5", + "MONITOR_SW2A2_0", + "MONITOR_WL1END2_6", + "MONITOR_IMUX29_7", + "MONITOR_EE4A2_0", + "MONITOR_FAN1_1", + "MONITOR_FAN4_5", + "MONITOR_WW4B2_4", + "MONITOR_SE2A0_9", + "MONITOR_IMUX34_6", + "MONITOR_WW2END2_6", + "MONITOR_LOGIC_OUTS_B2_6", + "MONITOR_CTRL0_9", + "MONITOR_WW2A2_7", + "MONITOR_HORIZ_VAUXN9", + "MONITOR_HORIZ_VAUXP2", + "MONITOR_FAN6_5", + "MONITOR_IMUX9_9", + "MONITOR_FAN7_3", + "MONITOR_IMUX47_4", + "MONITOR_IMUX46_0", + "MONITOR_NW4A2_6", + "MONITOR_EE4C1_0", + "MONITOR_NW4A0_1", + "MONITOR_LOGIC_OUTS_B16_5", + "MONITOR_IMUX10_4", + "MONITOR_LOGIC_OUTS_B3_3", + "MONITOR_SE4BEG3_0", + "MONITOR_EE4BEG2_7", + "MONITOR_IMUX44_7", + "MONITOR_WL1END3_7", + "MONITOR_IMUX13_2", + "MONITOR_IMUX19_1", + "MONITOR_IMUX40_6", + "MONITOR_IMUX30_7", + "MONITOR_IMUX8_8", + "MONITOR_SW2A2_3", + "MONITOR_IMUX28_2", + "MONITOR_IMUX26_1", + "MONITOR_NW4END0_6", + "MONITOR_IMUX25_9", + "MONITOR_SW2A1_6", + "MONITOR_ER1BEG0_0", + "MONITOR_WW2END1_5", + "MONITOR_SE2A0_6", + "MONITOR_WR1END3_1", + "MONITOR_NW4END0_1", + "MONITOR_LOGIC_OUTS_B18_4", + "MONITOR_NE4C0_4", + "MONITOR_SE4C2_3", + "MONITOR_BYP0_1", + "MONITOR_LH12_6", + "MONITOR_ER1BEG3_5", + "MONITOR_IMUX16_9", + "MONITOR_SW2A0_8", + "MONITOR_LH2_1", + "MONITOR_LOGIC_OUTS_B23_7", + "MONITOR_NW2A2_2", + "MONITOR_BYP6_4", + "MONITOR_IMUX19_2", + "MONITOR_WR1END0_2", + "MONITOR_IMUX45_3", + "MONITOR_LOGIC_OUTS_B12_3", + "MONITOR_SW4A0_3", + "MONITOR_WL1END1_9", + "MONITOR_CLK0_8", + "MONITOR_LH6_4", + "MONITOR_SW4A0_4", + "MONITOR_SW4END3_8", + "MONITOR_LH3_2", + "MONITOR_NW4A1_4", + "MONITOR_IMUX31_9", + "MONITOR_NW4END0_4", + "MONITOR_NE2A3_7", + "MONITOR_EE4BEG2_9", + "MONITOR_WW2END3_7", + "MONITOR_NE4BEG2_1", + "MONITOR_LOGIC_OUTS_B15_8", + "MONITOR_LH8_5", + "MONITOR_SE4BEG3_9", + "MONITOR_IMUX10_1", + "MONITOR_WW2A2_3", + "MONITOR_IMUX30_2", + "MONITOR_LOGIC_OUTS_B12_7", + "MONITOR_WW4END3_5", + "MONITOR_FAN1_5", + "MONITOR_EE2BEG0_9", + "MONITOR_IMUX12_8", + "MONITOR_FAN0_5", + "MONITOR_IMUX12_5", + "MONITOR_BLOCK_OUTS_B2_2", + "MONITOR_WW4C2_6", + "MONITOR_SE4C2_2", + "MONITOR_LOGIC_OUTS_B21_3", + "MONITOR_WW4B3_3", + "MONITOR_WW4END0_0", + "MONITOR_NE2A2_5", + "MONITOR_LOGIC_OUTS_B12_4", + "MONITOR_SW4END3_6", + "MONITOR_IMUX9_3", + "MONITOR_SW2A2_5", + "MONITOR_WW4B1_8", + "MONITOR_CLK0_1", + "MONITOR_FAN2_8", + "MONITOR_LOGIC_OUTS_B4_1", + "MONITOR_LOGIC_OUTS_B11_1", + "MONITOR_BYP6_6", + "MONITOR_LOGIC_OUTS_B6_1", + "MONITOR_IMUX26_8", + "MONITOR_WL1END2_4", + "MONITOR_SE2A1_6", + "MONITOR_WW2END2_8", + "MONITOR_BYP1_5", + "MONITOR_FAN3_1", + "MONITOR_IMUX45_5", + "MONITOR_WW4END3_2", + "MONITOR_EE2A2_1", + "MONITOR_CTRL0_4", + "MONITOR_LOGIC_OUTS_B3_8", + "MONITOR_IMUX22_7", + "MONITOR_LOGIC_OUTS_B4_8", + "MONITOR_NE4BEG1_9", + "MONITOR_WW4C3_5", + "MONITOR_IMUX14_8", + "MONITOR_EE4BEG3_0", + "MONITOR_IMUX36_4", + "MONITOR_IMUX12_0", + "MONITOR_IMUX22_9", + "MONITOR_SE4C3_5", + "MONITOR_WW4B0_8", + "MONITOR_IMUX23_3", + "MONITOR_EE4B0_9", + "MONITOR_EL1BEG3_5", + "MONITOR_IMUX44_4", + "MONITOR_LOGIC_OUTS_B20_3", + "MONITOR_EE2A1_4", + "MONITOR_IMUX10_8", + "MONITOR_NW4END0_3", + "MONITOR_NW4A1_3", + "MONITOR_LOGIC_OUTS_B0_8", + "MONITOR_IMUX15_0", + "MONITOR_EL1BEG2_7", + "MONITOR_IMUX44_0", + "MONITOR_SW4END1_5", + "MONITOR_SE4C0_2", + "MONITOR_IMUX27_3", + "MONITOR_LOGIC_OUTS_B2_4", + "MONITOR_WW4END3_4", + "MONITOR_NW2A3_9", + "MONITOR_WL1END3_5", + "MONITOR_LH3_1", + "MONITOR_LOGIC_OUTS_B15_0", + "MONITOR_SW4A1_6", + "MONITOR_EE2BEG2_3", + "MONITOR_IMUX14_4", + "MONITOR_SE4C1_4", + "MONITOR_LOGIC_OUTS_B7_1", + "MONITOR_IMUX0_1", + "MONITOR_IMUX7_4", + "MONITOR_LOGIC_OUTS_B5_7", + "MONITOR_SW4END1_6", + "MONITOR_IMUX6_4", + "MONITOR_IMUX32_5", + "MONITOR_LH4_8", + "MONITOR_IMUX38_9", + "MONITOR_IMUX11_8", + "MONITOR_EE2BEG1_1", + "MONITOR_WW2A2_5", + "MONITOR_EE2BEG2_0", + "MONITOR_NE4C0_9", + "MONITOR_VERT_VAUXN12", + "MONITOR_CTRL0_0", + "MONITOR_EE4C0_1", + "MONITOR_LOGIC_OUTS_B12_8", + "MONITOR_EL1BEG0_7", + "MONITOR_FAN4_4", + "MONITOR_IMUX29_3", + "MONITOR_WW4C2_1", + "MONITOR_IMUX11_9", + "MONITOR_SE4C2_7", + "MONITOR_VERT_VAUXP9", + "MONITOR_LOGIC_OUTS_B11_3", + "MONITOR_LOGIC_OUTS_B15_7", + "MONITOR_NE4C3_2", + "MONITOR_LH7_1", + "MONITOR_IMUX18_9", + "MONITOR_FAN6_8", + "MONITOR_VERT_VAUXP5", + "MONITOR_WR1END2_6", + "MONITOR_LOGIC_OUTS_B18_5", + "MONITOR_IMUX4_6", + "MONITOR_IMUX31_8", + "MONITOR_WW4B2_0", + "MONITOR_ER1BEG0_1", + "MONITOR_IMUX18_5", + "MONITOR_LH7_9", + "MONITOR_IMUX27_8", + "MONITOR_ER1BEG2_1", + "MONITOR_LOGIC_OUTS_B1_4", + "MONITOR_IMUX19_0", + "MONITOR_EE4A0_8", + "MONITOR_LH12_2", + "MONITOR_NW4A1_9", + "MONITOR_WW2END0_3", + "MONITOR_EE4B1_7", + "MONITOR_SW4A3_2", + "MONITOR_NW4A3_1", + "MONITOR_IMUX42_8", + "MONITOR_WW4B3_6", + "MONITOR_NE4C3_9", + "MONITOR_SW4A2_1", + "MONITOR_IMUX6_5", + "MONITOR_NE4C0_0", + "MONITOR_WW4END3_9", + "MONITOR_EL1BEG2_6", + "MONITOR_BYP1_4", + "MONITOR_SE4C2_9", + "MONITOR_EE4C0_6", + "MONITOR_BYP0_7", + "MONITOR_WW4B2_8", + "MONITOR_IMUX9_2", + "MONITOR_SE2A0_5", + "MONITOR_NW4A0_7", + "MONITOR_BYP1_9", + "MONITOR_SW4END0_4", + "MONITOR_LH12_3", + "MONITOR_IMUX19_6", + "MONITOR_EE4C2_7", + "MONITOR_EE2A1_3", + "MONITOR_IMUX28_0", + "MONITOR_EE2BEG0_2", + "MONITOR_NE4C2_6", + "MONITOR_LOGIC_OUTS_B6_0", + "MONITOR_IMUX6_8", + "MONITOR_LH9_6", + "MONITOR_LOGIC_OUTS_B23_5", + "MONITOR_EE2A2_0", + "MONITOR_EL1BEG1_7", + "MONITOR_IMUX16_2", + "MONITOR_IMUX18_6", + "MONITOR_LOGIC_OUTS_B8_4", + "MONITOR_WW4C0_0", + "MONITOR_BYP6_2", + "MONITOR_LOGIC_OUTS_B12_0", + "MONITOR_EE4BEG0_2", + "MONITOR_EE2BEG2_1", + "MONITOR_IMUX6_1", + "MONITOR_IMUX1_6", + "MONITOR_EL1BEG3_1", + "MONITOR_NW4END0_7", + "MONITOR_IMUX11_7", + "MONITOR_NW4END3_2", + "MONITOR_NW4END2_4", + "MONITOR_IMUX20_8", + "MONITOR_EE4B2_2", + "MONITOR_WW4C0_9", + "MONITOR_IMUX37_6", + "MONITOR_BYP0_6", + "MONITOR_SW4END0_8", + "MONITOR_WL1END0_7", + "MONITOR_LH4_4", + "MONITOR_SE2A3_1", + "MONITOR_NE2A3_2", + "MONITOR_LH10_8", + "MONITOR_BYP5_5", + "MONITOR_IMUX38_5", + "MONITOR_EE2BEG1_9", + "MONITOR_EE4C2_3", + "MONITOR_LOGIC_OUTS_B0_0", + "MONITOR_IMUX31_7", + "MONITOR_EE4BEG2_6", + "MONITOR_WW2A0_0", + "MONITOR_WL1END1_8", + "MONITOR_WW4END1_8", + "MONITOR_BYP0_9", + "MONITOR_EE2BEG1_0", + "MONITOR_EE4A3_5", + "MONITOR_LOGIC_OUTS_B18_0", + "MONITOR_HORIZ_VAUXP5", + "MONITOR_WW4END0_3", + "MONITOR_WR1END1_5", + "MONITOR_SE2A3_6", + "MONITOR_IMUX4_4", + "MONITOR_LH5_3", + "MONITOR_IMUX44_9", + "MONITOR_BYP4_1", + "MONITOR_SW4END2_8", + "MONITOR_WR1END1_7", + "MONITOR_IMUX5_8", + "MONITOR_EE2BEG3_8", + "MONITOR_LOGIC_OUTS_B10_1", + "MONITOR_LOGIC_OUTS_B5_8", + "MONITOR_NW4A3_9", + "MONITOR_IMUX40_3", + "MONITOR_WW4B0_9", + "MONITOR_NE4C2_3", + "MONITOR_NE2A2_0", + "MONITOR_EE2BEG3_3", + "MONITOR_EE2BEG3_5", + "MONITOR_EE4A1_2", + "MONITOR_LOGIC_OUTS_B13_0", + "MONITOR_SE2A2_3", + "MONITOR_IMUX20_5", + "MONITOR_NW4END3_8", + "MONITOR_WW2END0_5", + "MONITOR_SE2A2_0", + "MONITOR_BYP2_5", + "MONITOR_IMUX3_5", + "MONITOR_IMUX31_2", + "MONITOR_LOGIC_OUTS_B20_4", + "MONITOR_LOGIC_OUTS_B23_9", + "MONITOR_EE2A3_2", + "MONITOR_WW4A0_8", + "MONITOR_LH11_7", + "MONITOR_LOGIC_OUTS_B23_6", + "MONITOR_CTRL1_9", + "MONITOR_LOGIC_OUTS_B22_4", + "MONITOR_LOGIC_OUTS_B12_9", + "MONITOR_NW2A3_0", + "MONITOR_ER1BEG3_4", + "MONITOR_NE4BEG0_0", + "MONITOR_BYP2_4", + "MONITOR_EE2BEG3_7", + "MONITOR_NE2A1_3", + "MONITOR_SE4C3_6", + "MONITOR_IMUX45_1", + "MONITOR_IMUX2_9", + "MONITOR_SE4C0_7", + "MONITOR_IMUX10_2", + "MONITOR_FAN4_0", + "MONITOR_ER1BEG1_8", + "MONITOR_EL1BEG0_1", + "MONITOR_NE2A0_6", + "MONITOR_IMUX13_7", + "MONITOR_EE4A0_3", + "MONITOR_NW4END1_5", + "MONITOR_WW4A0_7", + "MONITOR_LOGIC_OUTS_B21_4", + "MONITOR_FAN3_0", + "MONITOR_LOGIC_OUTS_B6_7", + "MONITOR_WW4C0_2", + "MONITOR_WW2A1_6", + "MONITOR_EE4A1_8", + "MONITOR_IMUX29_6", + "MONITOR_WR1END2_9", + "MONITOR_LH7_4", + "MONITOR_LH10_6", + "MONITOR_BLOCK_OUTS_B2_7", + "MONITOR_IMUX15_1", + "MONITOR_EE4BEG3_1", + "MONITOR_WW4A2_4", + "MONITOR_EE4B2_6", + "MONITOR_LH11_9", + "MONITOR_LH3_5", + "MONITOR_EL1BEG0_5", + "MONITOR_NE2A0_3", + "MONITOR_LOGIC_OUTS_B21_1", + "MONITOR_EE4C1_3", + "MONITOR_FAN4_8", + "MONITOR_VERT_VAUXN9", + "MONITOR_IMUX47_2", + "MONITOR_EE2BEG3_9", + "MONITOR_IMUX0_8", + "MONITOR_LH5_2", + "MONITOR_NW2A3_4", + "MONITOR_WR1END0_6", + "MONITOR_BLOCK_OUTS_B1_8", + "MONITOR_EE4C2_5", + "MONITOR_LOGIC_OUTS_B17_0", + "MONITOR_IMUX36_8", + "MONITOR_BLOCK_OUTS_B1_7", + "MONITOR_IMUX24_2", + "MONITOR_NE4BEG3_1", + "MONITOR_BLOCK_OUTS_B3_3", + "MONITOR_WR1END3_6", + "MONITOR_SW4A3_0", + "MONITOR_BYP3_5", + "MONITOR_WR1END1_6", + "MONITOR_ER1BEG1_4", + "MONITOR_IMUX47_0", + "MONITOR_EE4C2_9", + "MONITOR_WW2A1_7", + "MONITOR_SW2A0_9", + "MONITOR_NW2A0_9", + "MONITOR_WW4C3_2", + "MONITOR_IMUX29_8", + "MONITOR_WW2A2_2", + "MONITOR_EE2A1_8", + "MONITOR_IMUX24_6", + "MONITOR_IMUX43_4", + "MONITOR_IMUX45_2", + "MONITOR_IMUX17_4", + "MONITOR_EL1BEG1_9", + "MONITOR_FAN1_9", + "MONITOR_EE4BEG3_7", + "MONITOR_EE4A2_6", + "MONITOR_LOGIC_OUTS_B22_5", + "MONITOR_SE4C1_6", + "MONITOR_WW2END2_0", + "MONITOR_EE2A2_3", + "MONITOR_EE2BEG0_1", + "MONITOR_IMUX40_4", + "MONITOR_LH6_6", + "MONITOR_EE4BEG0_0", + "MONITOR_FAN2_1", + "MONITOR_SE2A2_1", + "MONITOR_WW4C1_9", + "MONITOR_IMUX16_3", + "MONITOR_EE4C3_5", + "MONITOR_LOGIC_OUTS_B7_7", + "MONITOR_IMUX42_9", + "MONITOR_IMUX13_5", + "MONITOR_LH3_3", + "MONITOR_WW2END0_2", + "MONITOR_IMUX19_8", + "MONITOR_WR1END1_0", + "MONITOR_IMUX1_8", + "MONITOR_SW2A0_6", + "MONITOR_LOGIC_OUTS_B2_5", + "MONITOR_LOGIC_OUTS_B11_7", + "MONITOR_LOGIC_OUTS_B19_4", + "MONITOR_SW2A0_4", + "MONITOR_EE2BEG3_0", + "MONITOR_LH1_6", + "MONITOR_SW2A1_1", + "MONITOR_EE4C1_4", + "MONITOR_LOGIC_OUTS_B1_0", + "MONITOR_SE4BEG2_1", + "MONITOR_VERT_VAUXN6", + "MONITOR_LH9_4", + "MONITOR_LH9_3", + "MONITOR_WW2A3_8", + "MONITOR_WW4A2_7", + "MONITOR_EE4C3_2", + "MONITOR_EE4B2_4", + "MONITOR_LH7_5", + "MONITOR_WL1END1_0", + "MONITOR_IMUX16_4", + "MONITOR_IMUX35_2", + "MONITOR_EL1BEG3_6", + "MONITOR_NE4C0_1", + "MONITOR_LH1_7", + "MONITOR_FAN1_7", + "MONITOR_BYP6_9", + "MONITOR_WW4END3_8", + "MONITOR_NW4END2_5", + "MONITOR_WR1END0_7", + "MONITOR_NE4C1_3", + "MONITOR_LOGIC_OUTS_B0_1", + "MONITOR_NW4END2_0", + "MONITOR_LOGIC_OUTS_B8_9", + "MONITOR_IMUX17_8", + "MONITOR_SW4A2_9", + "MONITOR_LOGIC_OUTS_B14_9", + "MONITOR_NW4A3_3", + "MONITOR_LOGIC_OUTS_B0_5", + "MONITOR_EE4A2_9", + "MONITOR_WW2A2_8", + "MONITOR_LOGIC_OUTS_B13_9", + "MONITOR_SE4BEG1_5", + "MONITOR_SE4BEG2_4", + "MONITOR_EE4A1_5", + "MONITOR_WW4END1_1", + "MONITOR_IMUX37_4", + "MONITOR_NE4BEG2_7", + "MONITOR_IMUX14_0", + "MONITOR_NW2A0_8", + "MONITOR_ER1BEG1_1", + "MONITOR_IMUX2_8", + "MONITOR_SW2A2_4", + "MONITOR_IMUX17_5", + "MONITOR_IMUX13_3", + "MONITOR_LOGIC_OUTS_B12_5", + "MONITOR_LOGIC_OUTS_B19_5", + "MONITOR_WW4B0_2", + "MONITOR_WW4B1_1", + "MONITOR_IMUX45_0", + "MONITOR_IMUX24_5", + "MONITOR_IMUX12_7", + "MONITOR_IMUX25_4", + "MONITOR_WW4B2_7", + "MONITOR_LOGIC_OUTS_B17_3", + "MONITOR_IMUX7_3", + "MONITOR_SE2A2_9", + "MONITOR_EE4C3_4", + "MONITOR_WW4END1_9", + "MONITOR_NW2A0_4", + "MONITOR_IMUX33_9", + "MONITOR_CTRL0_1", + "MONITOR_WW4A0_0", + "MONITOR_BLOCK_OUTS_B0_7", + "MONITOR_CTRL0_8", + "MONITOR_WW4B1_4", + "MONITOR_BYP3_9", + "MONITOR_VERT_VAUXN5", + "MONITOR_EE4BEG1_0", + "MONITOR_IMUX12_2", + "MONITOR_LOGIC_OUTS_B22_1", + "MONITOR_IMUX45_6", + "MONITOR_FAN0_4", + "MONITOR_WL1END0_4", + "MONITOR_EE4C2_2", + "MONITOR_FAN4_9", + "MONITOR_LOGIC_OUTS_B4_3", + "MONITOR_NW4END0_9", + "MONITOR_LH7_6", + "MONITOR_SE4C1_9", + "MONITOR_IMUX41_1", + "MONITOR_WW2END0_7", + "MONITOR_LH4_3", + "MONITOR_VERT_VAUXN2", + "MONITOR_IMUX37_0", + "MONITOR_WW4C1_5", + "MONITOR_WW4C3_1", + "MONITOR_IMUX9_1", + "MONITOR_SE4BEG0_4", + "MONITOR_IMUX14_7", + "MONITOR_VERT_VAUXN13", + "MONITOR_IMUX8_1", + "MONITOR_SW2A3_2", + "MONITOR_LOGIC_OUTS_B15_3", + "MONITOR_LH6_5", + "MONITOR_EE4B1_4", + "MONITOR_IMUX32_1", + "MONITOR_LH2_5", + "MONITOR_EE4B1_0", + "MONITOR_WW4END0_6", + "MONITOR_SW4A1_4", + "MONITOR_NE2A3_4", + "MONITOR_WW4C2_8", + "MONITOR_WW4END1_6", + "MONITOR_EE4C3_9", + "MONITOR_LH8_8", + "MONITOR_WW4A2_5", + "MONITOR_EL1BEG2_1", + "MONITOR_NW2A0_1", + "MONITOR_CTRL1_8", + "MONITOR_IMUX34_9", + "MONITOR_EL1BEG2_9", + "MONITOR_WW4A2_6", + "MONITOR_NE4BEG3_3", + "MONITOR_ER1BEG0_3", + "MONITOR_IMUX42_1", + "MONITOR_SW4A0_5", + "MONITOR_WW4END2_4", + "MONITOR_IMUX13_0", + "MONITOR_BYP6_5", + "MONITOR_SW4END0_3", + "MONITOR_EE4B3_9", + "MONITOR_EL1BEG1_5", + "MONITOR_WW4C3_3", + "MONITOR_WW4C2_2", + "MONITOR_LOGIC_OUTS_B9_7", + "MONITOR_WW4END2_2", + "MONITOR_WL1END3_0", + "MONITOR_IMUX44_8", + "MONITOR_IMUX2_7", + "MONITOR_NW2A2_0", + "MONITOR_LH7_3", + "MONITOR_EE2A0_7", + "MONITOR_LH10_0", + "MONITOR_WW4B3_2", + "MONITOR_IMUX43_0", + "MONITOR_IMUX39_3", + "MONITOR_SW4END0_6", + "MONITOR_EL1BEG2_0", + "MONITOR_IMUX3_0", + "MONITOR_IMUX1_2", + "MONITOR_WW4C2_9", + "MONITOR_LH5_7", + "MONITOR_EE4A2_5", + "MONITOR_IMUX0_9", + "MONITOR_FAN7_7", + "MONITOR_IMUX36_9", + "MONITOR_WW2END3_6", + "MONITOR_FAN0_3", + "MONITOR_LOGIC_OUTS_B23_1", + "MONITOR_LOGIC_OUTS_B20_0", + "MONITOR_WW2END3_4", + "MONITOR_FAN2_6", + "MONITOR_WR1END1_4", + "MONITOR_LOGIC_OUTS_B22_2", + "MONITOR_IMUX17_0", + "MONITOR_FAN7_6", + "MONITOR_EE2A0_5", + "MONITOR_WW2A2_0", + "MONITOR_IMUX18_8", + "MONITOR_NW4END3_3", + "MONITOR_SE4BEG2_7", + "MONITOR_BLOCK_OUTS_B3_0", + "MONITOR_BLOCK_OUTS_B3_7", + "MONITOR_WW4C0_1", + "MONITOR_SW4END2_2", + "MONITOR_LH3_9", + "MONITOR_LOGIC_OUTS_B9_4", + "MONITOR_SW4END1_8", + "MONITOR_EL1BEG0_0", + "MONITOR_WW2END3_0", + "MONITOR_FAN5_7", + "MONITOR_WW4B1_5", + "MONITOR_EE4C0_2", + "MONITOR_WW2A3_0", + "MONITOR_WR1END3_9", + "MONITOR_SW2A3_5", + "MONITOR_EE4B0_6", + "MONITOR_BYP7_5", + "MONITOR_IMUX12_4", + "MONITOR_LOGIC_OUTS_B2_8", + "MONITOR_EE4B0_2", + "MONITOR_FAN1_4", + "MONITOR_FAN0_1", + "MONITOR_WW4B0_5", + "MONITOR_NE2A2_8", + "MONITOR_EE4A0_1", + "MONITOR_BYP2_8", + "MONITOR_LOGIC_OUTS_B4_5", + "MONITOR_WW4END0_8", + "MONITOR_LH6_7", + "MONITOR_IMUX44_3", + "MONITOR_LH7_7", + "MONITOR_EE4B3_7", + "MONITOR_ER1BEG0_4", + "MONITOR_SW2A1_8", + "MONITOR_SE2A1_8", + "MONITOR_SE4BEG0_1", + "MONITOR_WW4A3_3", + "MONITOR_WW4END1_0", + "MONITOR_NE4BEG3_8", + "MONITOR_EE4BEG0_6", + "MONITOR_IMUX25_1", + "MONITOR_LOGIC_OUTS_B15_1", + "MONITOR_NE2A2_2", + "MONITOR_NE4C2_4", + "MONITOR_FAN7_8", + "MONITOR_VERT_VAUXP2", + "MONITOR_IMUX42_7", + "MONITOR_WW2END2_9", + "MONITOR_LOGIC_OUTS_B21_8", + "MONITOR_BYP4_9", + "MONITOR_IMUX34_5", + "MONITOR_IMUX47_8", + "MONITOR_EE4A2_2", + "MONITOR_WW4A3_4", + "MONITOR_NW4A2_2", + "MONITOR_EE2BEG2_8", + "MONITOR_IMUX1_9", + "MONITOR_ER1BEG2_6", + "MONITOR_FAN5_3", + "MONITOR_HORIZ_VAUXN1", + "MONITOR_BYP4_3", + "MONITOR_NW2A1_1", + "MONITOR_NE2A3_1", + "MONITOR_NW4END3_7", + "MONITOR_IMUX46_5", + "MONITOR_SE2A3_9", + "MONITOR_EE4B1_5", + "MONITOR_SE4BEG3_1", + "MONITOR_NW4END2_6", + "MONITOR_LH6_0", + "MONITOR_NW2A3_5", + "MONITOR_SE4C3_8", + "MONITOR_VERT_VAUXP13", + "MONITOR_EE2BEG2_4", + "MONITOR_IMUX20_6", + "MONITOR_EE4B2_9", + "MONITOR_LOGIC_OUTS_B6_8", + "MONITOR_WW4END0_2", + "MONITOR_LOGIC_OUTS_B0_4", + "MONITOR_BLOCK_OUTS_B0_1", + "MONITOR_WW4B3_7", + "MONITOR_IMUX14_6", + "MONITOR_LOGIC_OUTS_B2_7", + "MONITOR_EE4A3_7", + "MONITOR_NW4A3_5", + "MONITOR_EE4BEG1_7", + "MONITOR_CTRL1_2", + "MONITOR_EL1BEG1_4", + "MONITOR_LOGIC_OUTS_B13_1", + "MONITOR_IMUX7_5", + "MONITOR_SW4A2_8", + "MONITOR_EE4BEG1_1", + "MONITOR_WW2A1_2", + "MONITOR_CLK1_1", + "MONITOR_IMUX36_7", + "MONITOR_NW4END0_5", + "MONITOR_LOGIC_OUTS_B10_5", + "MONITOR_FAN6_7", + "MONITOR_BYP4_6", + "MONITOR_SE4C3_0", + "MONITOR_WW4B1_9", + "MONITOR_NE2A1_2", + "MONITOR_IMUX45_7", + "MONITOR_NE4C0_5", + "MONITOR_EE4C2_8", + "MONITOR_EE4BEG0_8", + "MONITOR_EE4BEG0_5", + "MONITOR_IMUX43_6", + "MONITOR_LOGIC_OUTS_B10_2", + "MONITOR_NW4END1_3", + "MONITOR_SE4C0_8", + "MONITOR_LH4_1", + "MONITOR_IMUX5_3", + "MONITOR_LOGIC_OUTS_B22_9", + "MONITOR_SW2A3_4", + "MONITOR_EE4C0_0", + "MONITOR_LOGIC_OUTS_B11_2", + "MONITOR_SE2A3_7", + "MONITOR_ER1BEG1_5", + "MONITOR_ER1BEG0_6", + "MONITOR_IMUX20_4", + "MONITOR_LH10_1", + "MONITOR_WL1END2_8", + "MONITOR_FAN5_2", + "MONITOR_IMUX18_0", + "MONITOR_EE4B1_3", + "MONITOR_NW2A0_6", + "MONITOR_NW2A1_4", + "MONITOR_CLK1_2", + "MONITOR_WL1END3_4", + "MONITOR_EE2A3_3", + "MONITOR_BYP7_7", + "MONITOR_SE4BEG2_2", + "MONITOR_BYP7_2", + "MONITOR_IMUX29_0", + "MONITOR_CLK1_0", + "MONITOR_LOGIC_OUTS_B3_9", + "MONITOR_BLOCK_OUTS_B1_4", + "MONITOR_SW4END3_5", + "MONITOR_WL1END0_3", + "MONITOR_NE2A1_4", + "MONITOR_IMUX22_2", + "MONITOR_NW4END2_1", + "MONITOR_LOGIC_OUTS_B0_9", + "MONITOR_IMUX24_9", + "MONITOR_LOGIC_OUTS_B7_9", + "MONITOR_SE2A1_7", + "MONITOR_WW2A1_0", + "MONITOR_BLOCK_OUTS_B0_4", + "MONITOR_LOGIC_OUTS_B5_3", + "MONITOR_SW4A3_1", + "MONITOR_LH1_8", + "MONITOR_IMUX11_5", + "MONITOR_LOGIC_OUTS_B9_5", + "MONITOR_IMUX3_1", + "MONITOR_IMUX24_3", + "MONITOR_IMUX43_2", + "MONITOR_IMUX0_4", + "MONITOR_WW2A1_5", + "MONITOR_LOGIC_OUTS_B9_2", + "MONITOR_WR1END2_5", + "MONITOR_IMUX35_0", + "MONITOR_LOGIC_OUTS_B9_3", + "MONITOR_EL1BEG0_4", + "MONITOR_SE2A0_1", + "MONITOR_LOGIC_OUTS_B15_6", + "MONITOR_IMUX44_5", + "MONITOR_NE4BEG1_6", + "MONITOR_WW4A3_8", + "MONITOR_WW2END0_9", + "MONITOR_HORIZ_VAUXP1", + "MONITOR_NE2A0_1", + "MONITOR_CLK0_4", + "MONITOR_LOGIC_OUTS_B8_7", + "MONITOR_EE4C1_6", + "MONITOR_WW4END0_5", + "MONITOR_LOGIC_OUTS_B13_8", + "MONITOR_IMUX30_5", + "MONITOR_LOGIC_OUTS_B6_3", + "MONITOR_ER1BEG0_2", + "MONITOR_SW4A0_2", + "MONITOR_SW4END1_4", + "MONITOR_IMUX43_9", + "MONITOR_SW4END2_3", + "MONITOR_IMUX13_1", + "MONITOR_LOGIC_OUTS_B20_6", + "MONITOR_WW4A2_3", + "MONITOR_IMUX6_9", + "MONITOR_SE4C2_5", + "MONITOR_LOGIC_OUTS_B14_3", + "MONITOR_LOGIC_OUTS_B10_6", + "MONITOR_LOGIC_OUTS_B23_0", + "MONITOR_IMUX10_7", + "MONITOR_LH1_9", + "MONITOR_BYP7_1", + "MONITOR_WW4A1_0", + "MONITOR_FAN0_6", + "MONITOR_NE4BEG1_1", + "MONITOR_SW4END2_1", + "MONITOR_LOGIC_OUTS_B16_7", + "MONITOR_NE4C1_1", + "MONITOR_WW4A2_0", + "MONITOR_SW2A0_3", + "MONITOR_IMUX27_6", + "MONITOR_EL1BEG3_3", + "MONITOR_WW4END2_3", + "MONITOR_WL1END1_7", + "MONITOR_WW4C1_7", + "MONITOR_IMUX38_1", + "MONITOR_LH11_5", + "MONITOR_FAN7_1", + "MONITOR_SE4BEG2_8", + "MONITOR_SW4A3_8", + "MONITOR_EE4B3_6", + "MONITOR_EE2A1_9", + "MONITOR_LOGIC_OUTS_B1_8", + "MONITOR_IMUX33_1", + "MONITOR_NW4A0_9", + "MONITOR_CLK0_6", + "MONITOR_FAN6_0", + "MONITOR_BLOCK_OUTS_B1_9", + "MONITOR_BYP6_7", + "MONITOR_WL1END0_5", + "MONITOR_EE4BEG3_6", + "MONITOR_EE2A3_8", + "MONITOR_LOGIC_OUTS_B5_1", + "MONITOR_NW4A1_6", + "MONITOR_IMUX37_7", + "MONITOR_IMUX8_4", + "MONITOR_BYP0_4", + "MONITOR_BYP0_3", + "MONITOR_IMUX22_6", + "MONITOR_LOGIC_OUTS_B14_8", + "MONITOR_IMUX16_0", + "MONITOR_LOGIC_OUTS_B3_4", + "MONITOR_LH8_2", + "MONITOR_IMUX26_2", + "MONITOR_SE4BEG1_7", + "MONITOR_IMUX2_6", + "MONITOR_WW2A3_6", + "MONITOR_IMUX9_5", + "MONITOR_SE4BEG3_7", + "MONITOR_IMUX14_1", + "MONITOR_LOGIC_OUTS_B19_2", + "MONITOR_NE4BEG0_4", + "MONITOR_EE4A0_5", + "MONITOR_NW4END0_8", + "MONITOR_VERT_VAUXP10", + "MONITOR_NE2A3_9", + "MONITOR_LOGIC_OUTS_B5_9", + "MONITOR_WL1END0_2", + "MONITOR_ER1BEG1_6", + "MONITOR_LOGIC_OUTS_B13_4", + "MONITOR_EE4B1_9", + "MONITOR_IMUX42_5", + "MONITOR_LOGIC_OUTS_B22_3", + "MONITOR_WW4END3_3", + "MONITOR_NW4A1_8", + "MONITOR_FAN7_2", + "MONITOR_IMUX18_7", + "MONITOR_EE4A0_9", + "MONITOR_SW2A2_7", + "MONITOR_BYP4_7", + "MONITOR_EE4C2_1", + "MONITOR_SE4C1_1", + "MONITOR_WW4A1_9", + "MONITOR_IMUX46_2", + "MONITOR_SW2A1_3", + "MONITOR_IMUX17_1", + "MONITOR_LOGIC_OUTS_B12_2", + "MONITOR_LH3_4", + "MONITOR_IMUX33_4", + "MONITOR_IMUX15_3", + "MONITOR_BLOCK_OUTS_B2_1", + "MONITOR_WR1END0_5", + "MONITOR_VERT_VAUXN14", + "MONITOR_SE4BEG3_3", + "MONITOR_FAN4_3", + "MONITOR_LOGIC_OUTS_B15_5", + "MONITOR_IMUX17_6", + "MONITOR_LOGIC_OUTS_B10_8", + "MONITOR_WW4A1_4", + "MONITOR_WW4A0_9", + "MONITOR_BYP5_9", + "MONITOR_LOGIC_OUTS_B22_8", + "MONITOR_SW4END1_1", + "MONITOR_WR1END3_7", + "MONITOR_NW4A2_8", + "MONITOR_IMUX32_2", + "MONITOR_LH9_2", + "MONITOR_IMUX37_1", + "MONITOR_LOGIC_OUTS_B8_8", + "MONITOR_SE2A1_0", + "MONITOR_WW2A3_4", + "MONITOR_IMUX11_1", + "MONITOR_SW4A0_6", + "MONITOR_EL1BEG0_6", + "MONITOR_NW4END3_4", + "MONITOR_ER1BEG0_8", + "MONITOR_LH3_0", + "MONITOR_SW2A1_7", + "MONITOR_LOGIC_OUTS_B17_2", + "MONITOR_LOGIC_OUTS_B23_3", + "MONITOR_BYP6_8", + "MONITOR_EE4BEG1_3", + "MONITOR_LOGIC_OUTS_B10_3", + "MONITOR_WR1END3_8", + "MONITOR_EE4C2_4", + "MONITOR_IMUX3_3", + "MONITOR_IMUX4_5", + "MONITOR_WL1END0_8", + "MONITOR_FAN5_8", + "MONITOR_NW2A1_8", + "MONITOR_SE4BEG0_0", + "MONITOR_NW2A2_9", + "MONITOR_ER1BEG1_9", + "MONITOR_WW4A0_1", + "MONITOR_IMUX2_3", + "MONITOR_LOGIC_OUTS_B8_0", + "MONITOR_EE4A3_1", + "MONITOR_WW4B0_0", + "MONITOR_SE4BEG2_0", + "MONITOR_IMUX45_8", + "MONITOR_LOGIC_OUTS_B6_4", + "MONITOR_CTRL0_7", + "MONITOR_IMUX6_2", + "MONITOR_IMUX43_8", + "MONITOR_EE2A2_4", + "MONITOR_LH12_9", + "MONITOR_SE4BEG0_9", + "MONITOR_EE4C3_1", + "MONITOR_WR1END0_0", + "MONITOR_WR1END2_7", + "MONITOR_SE4C2_8", + "MONITOR_SW4END2_9", + "MONITOR_EE4B0_0", + "MONITOR_LOGIC_OUTS_B8_3", + "MONITOR_LOGIC_OUTS_B19_8", + "MONITOR_ER1BEG2_3", + "MONITOR_NW2A2_5", + "MONITOR_EE2BEG1_8", + "MONITOR_LH2_7", + "MONITOR_LOGIC_OUTS_B19_0", + "MONITOR_EE4BEG3_4", + "MONITOR_IMUX10_0", + "MONITOR_IMUX17_9", + "MONITOR_IMUX32_0", + "MONITOR_FAN6_3", + "MONITOR_IMUX15_6", + "MONITOR_LH10_7", + "MONITOR_VERT_VAUXP1", + "MONITOR_ER1BEG3_0", + "MONITOR_CLK1_4", + "MONITOR_IMUX9_8", + "MONITOR_EE2A0_1", + "MONITOR_IMUX40_9", + "MONITOR_NW2A3_1", + "MONITOR_BLOCK_OUTS_B3_1", + "MONITOR_WW4B0_3", + "MONITOR_LH8_7", + "MONITOR_NW4END2_3", + "MONITOR_SW4A1_5", + "MONITOR_EL1BEG0_3", + "MONITOR_BLOCK_OUTS_B0_0", + "MONITOR_IMUX38_8", + "MONITOR_NE4C1_4", + "MONITOR_WW4C0_3", + "MONITOR_ER1BEG2_0", + "MONITOR_BYP1_0", + "MONITOR_EE4A2_1", + "MONITOR_SE4C3_1", + "MONITOR_NE4BEG2_6", + "MONITOR_IMUX21_7", + "MONITOR_NE2A2_7", + "MONITOR_IMUX41_8", + "MONITOR_SE4C0_6", + "MONITOR_WL1END1_6", + "MONITOR_EL1BEG0_9", + "MONITOR_IMUX8_7", + "MONITOR_EE4A2_8", + "MONITOR_IMUX30_3", + "MONITOR_IMUX8_0", + "MONITOR_LOGIC_OUTS_B11_9", + "MONITOR_IMUX7_0", + "MONITOR_IMUX28_5", + "MONITOR_SW4A2_6", + "MONITOR_NW2A3_8", + "MONITOR_LOGIC_OUTS_B18_9", + "MONITOR_ER1BEG0_5", + "MONITOR_LH8_9", + "MONITOR_IMUX46_1", + "MONITOR_EE4BEG2_8", + "MONITOR_IMUX30_9", + "MONITOR_FAN2_9", + "MONITOR_ER1BEG1_3", + "MONITOR_WW4A3_9", + "MONITOR_BYP3_6", + "MONITOR_LOGIC_OUTS_B5_6", + "MONITOR_IMUX28_6", + "MONITOR_WW4C2_4", + "MONITOR_LH7_8", + "MONITOR_IMUX47_9", + "MONITOR_EE2A1_1", + "MONITOR_LOGIC_OUTS_B17_5", + "MONITOR_ER1BEG3_7", + "MONITOR_IMUX41_0", + "MONITOR_WW4END3_1", + "MONITOR_WW2END1_2", + "MONITOR_EE4A3_8", + "MONITOR_WW2END1_3", + "MONITOR_WW2END2_1", + "MONITOR_WW2A0_5", + "MONITOR_NW2A3_3", + "MONITOR_IMUX10_5", + "MONITOR_BYP2_3", + "MONITOR_WW4END0_9", + "MONITOR_NW4A3_8", + "MONITOR_LH8_3", + "MONITOR_EE4A2_4", + "MONITOR_WL1END0_6", + "MONITOR_IMUX26_5", + "MONITOR_EE4C1_1", + "MONITOR_NE4C3_5", + "MONITOR_SW2A3_8", + "MONITOR_IMUX2_5", + "MONITOR_LOGIC_OUTS_B3_7", + "MONITOR_WW4END2_6", + "MONITOR_EL1BEG1_3", + "MONITOR_IMUX41_7", + "MONITOR_LOGIC_OUTS_B15_9", + "MONITOR_HORIZ_VAUXN13", + "MONITOR_SW2A2_8", + "MONITOR_EE4BEG1_6", + "MONITOR_EE2A3_1", + "MONITOR_IMUX7_9", + "MONITOR_IMUX19_5", + "MONITOR_SW4END1_3", + "MONITOR_LOGIC_OUTS_B0_6", + "MONITOR_LOGIC_OUTS_B19_9", + "MONITOR_WL1END1_5", + "MONITOR_BYP2_0", + "MONITOR_IMUX5_7", + "MONITOR_IMUX23_2", + "MONITOR_LOGIC_OUTS_B14_2", + "MONITOR_WW2END1_0", + "MONITOR_IMUX36_1", + "MONITOR_SE4C3_4", + "MONITOR_CTRL1_1", + "MONITOR_EE4B0_3", + "MONITOR_WW4A1_1", + "MONITOR_WW2END1_4", + "MONITOR_SE4BEG1_6", + "MONITOR_WL1END2_0", + "MONITOR_IMUX32_3", + "MONITOR_WW4B2_9", + "MONITOR_IMUX40_0", + "MONITOR_LH12_7", + "MONITOR_IMUX41_5", + "MONITOR_LH10_3", + "MONITOR_HORIZ_VAUXN6", + "MONITOR_BYP1_1", + "MONITOR_LOGIC_OUTS_B22_0", + "MONITOR_EL1BEG2_4", + "MONITOR_IMUX6_7", + "MONITOR_NW2A0_5", + "MONITOR_NE4BEG1_5", + "MONITOR_NW4END1_8", + "MONITOR_NW4A0_2", + "MONITOR_WW4B2_3", + "MONITOR_NE2A1_9", + "MONITOR_IMUX41_6", + "MONITOR_NE4BEG3_6", + "MONITOR_BLOCK_OUTS_B0_6", + "MONITOR_SE4C1_7", + "MONITOR_SW4END2_4", + "MONITOR_IMUX35_1", + "MONITOR_LOGIC_OUTS_B14_7", + "MONITOR_WW4A1_6", + "MONITOR_LOGIC_OUTS_B19_3", + "MONITOR_LH4_0", + "MONITOR_LOGIC_OUTS_B15_2", + "MONITOR_IMUX39_0", + "MONITOR_WL1END0_9", + "MONITOR_LOGIC_OUTS_B16_9", + "MONITOR_WW4B3_1", + "MONITOR_NE4C1_5", + "MONITOR_BYP0_8", + "MONITOR_IMUX33_0", + "MONITOR_EE4A0_0", + "MONITOR_SE2A0_7", + "MONITOR_IMUX34_1", + "MONITOR_LH9_9", + "MONITOR_CLK1_3", + "MONITOR_WW2END2_4", + "MONITOR_NE4C3_0", + "MONITOR_NW4END1_4", + "MONITOR_FAN0_7", + "MONITOR_IMUX5_4", + "MONITOR_WW4END2_1", + "MONITOR_IMUX34_8", + "MONITOR_VERT_VAUXP3", + "MONITOR_SE4BEG1_9", + "MONITOR_IMUX35_7", + "MONITOR_NW4END1_6", + "MONITOR_SE4BEG2_9", + "MONITOR_WW4END1_2", + "MONITOR_FAN4_7", + "MONITOR_LH6_3", + "MONITOR_EE4A2_7", + "MONITOR_NE4BEG0_9", + "MONITOR_LOGIC_OUTS_B18_2", + "MONITOR_ER1BEG3_6", + "MONITOR_EE4A0_2", + "MONITOR_LOGIC_OUTS_B20_8", + "MONITOR_WR1END0_1", + "MONITOR_SW4A3_7", + "MONITOR_BLOCK_OUTS_B3_2", + "MONITOR_EE2BEG1_4", + "MONITOR_SW4END0_0", + "MONITOR_BLOCK_OUTS_B2_8", + "MONITOR_NE2A0_2", + "MONITOR_SE4BEG1_2", + "MONITOR_EE4C0_3", + "MONITOR_IMUX2_0", + "MONITOR_LOGIC_OUTS_B3_5", + "MONITOR_IMUX20_9", + "MONITOR_SW4END0_7", + "MONITOR_EE2BEG2_5", + "MONITOR_FAN6_4", + "MONITOR_LOGIC_OUTS_B2_1", + "MONITOR_LH7_0", + "MONITOR_EE2A1_5", + "MONITOR_NE4C1_2", + "MONITOR_EE4C0_4", + "MONITOR_WL1END2_1", + "MONITOR_IMUX28_7", + "MONITOR_IMUX7_8", + "MONITOR_LH11_6", + "MONITOR_WR1END3_0", + "MONITOR_SW4A0_8", + "MONITOR_IMUX15_8", + "MONITOR_WW2A1_8", + "MONITOR_WW2A3_2", + "MONITOR_IMUX47_3", + "MONITOR_IMUX30_6", + "MONITOR_IMUX5_2", + "MONITOR_IMUX29_9", + "MONITOR_WL1END3_2", + "MONITOR_BYP3_2", + "MONITOR_LOGIC_OUTS_B6_2", + "MONITOR_CTRL1_5", + "MONITOR_NE4BEG3_4", + "MONITOR_SE4BEG0_8", + "MONITOR_LOGIC_OUTS_B10_9", + "MONITOR_EE4BEG2_3", + "MONITOR_IMUX18_1", + "MONITOR_EE4C1_7", + "MONITOR_WW2END2_7", + "MONITOR_LH9_0", + "MONITOR_SE4C0_4", + "MONITOR_BYP2_7", + "MONITOR_EL1BEG2_5", + "MONITOR_EE4BEG0_1", + "MONITOR_LH8_1", + "MONITOR_SW4A1_8", + "MONITOR_HORIZ_VAUXN2", + "MONITOR_IMUX29_2", + "MONITOR_LH1_5", + "MONITOR_LOGIC_OUTS_B11_6", + "MONITOR_WW4A1_2", + "MONITOR_EE2A0_3", + "MONITOR_IMUX35_9", + "MONITOR_IMUX44_6", + "MONITOR_IMUX8_2", + "MONITOR_WW4A1_3", + "MONITOR_LH5_8", + "MONITOR_CTRL1_3", + "MONITOR_WW4C2_5", + "MONITOR_WW4B0_6", + "MONITOR_SW4END2_5", + "MONITOR_IMUX5_1", + "MONITOR_NE2A2_3", + "MONITOR_IMUX26_4", + "MONITOR_LH12_0", + "MONITOR_EE2A1_0", + "MONITOR_IMUX25_3", + "MONITOR_NE4C2_8", + "MONITOR_IMUX2_1", + "MONITOR_IMUX22_0", + "MONITOR_WW4END2_9", + "MONITOR_EE2A2_6", + "MONITOR_EL1BEG3_7", + "MONITOR_IMUX39_2", + "MONITOR_BLOCK_OUTS_B3_9", + "MONITOR_LOGIC_OUTS_B4_6", + "MONITOR_EE2A0_4", + "MONITOR_EE4C0_5", + "MONITOR_NW4END1_1", + "MONITOR_SW2A0_1", + "MONITOR_EE4B1_1", + "MONITOR_NE2A0_4", + "MONITOR_LOGIC_OUTS_B1_1", + "MONITOR_IMUX2_4", + "MONITOR_EE2BEG0_5", + "MONITOR_WW4A3_0", + "MONITOR_IMUX28_3", + "MONITOR_WW4A1_7", + "MONITOR_SW2A3_9", + "MONITOR_NE4C2_1", + "MONITOR_EE2BEG0_7", + "MONITOR_BYP1_8", + "MONITOR_IMUX25_0", + "MONITOR_SE4C3_9", + "MONITOR_IMUX35_8", + "MONITOR_IMUX8_9", + "MONITOR_NE4C0_7", + "MONITOR_NE2A2_9", + "MONITOR_SW4END3_3", + "MONITOR_IMUX25_5", + "MONITOR_WW4END2_7", + "MONITOR_EE4A3_3", + "MONITOR_ER1BEG2_9", + "MONITOR_NE2A1_0", + "MONITOR_WW4B1_0", + "MONITOR_EE2BEG0_4", + "MONITOR_BYP1_3", + "MONITOR_SW4A1_3", + "MONITOR_NE4BEG1_4", + "MONITOR_IMUX37_2", + "MONITOR_LOGIC_OUTS_B1_6", + "MONITOR_EE2BEG0_6", + "MONITOR_IMUX36_2", + "MONITOR_BYP2_6", + "MONITOR_NW4END3_1", + "MONITOR_WW2A0_1", + "MONITOR_IMUX42_0", + "MONITOR_IMUX25_8", + "MONITOR_WW4C3_4", + "MONITOR_NE4BEG1_8", + "MONITOR_SW2A0_0", + "MONITOR_WW2A1_1", + "MONITOR_IMUX7_1", + "MONITOR_EL1BEG3_9", + "MONITOR_NE4C1_6", + "MONITOR_IMUX1_1", + "MONITOR_SW4A3_4", + "MONITOR_WR1END2_2", + "MONITOR_NE2A1_1", + "MONITOR_WW4B0_7", + "MONITOR_WW4B2_5", + "MONITOR_IMUX42_6", + "MONITOR_LOGIC_OUTS_B10_7", + "MONITOR_EE4BEG3_8", + "MONITOR_NW4A1_7", + "MONITOR_EE2BEG1_2", + "MONITOR_EE2BEG1_7", + "MONITOR_NW4END2_8", + "MONITOR_ER1BEG1_2", + "MONITOR_WW4C3_8", + "MONITOR_SW2A2_1", + "MONITOR_LOGIC_OUTS_B20_7", + "MONITOR_EE4BEG2_1", + "MONITOR_EE4C3_6", + "MONITOR_WR1END0_8", + "MONITOR_EE2A2_2", + "MONITOR_WW2END0_0", + "MONITOR_WW4C0_6", + "MONITOR_NE4BEG0_5", + "MONITOR_SW2A0_5", + "MONITOR_IMUX36_5", + "MONITOR_IMUX10_6", + "MONITOR_IMUX12_1", + "MONITOR_LOGIC_OUTS_B11_0", + "MONITOR_IMUX24_7", + "MONITOR_WR1END2_3", + "MONITOR_BYP5_0", + "MONITOR_IMUX16_6", + "MONITOR_IMUX18_2", + "MONITOR_BYP7_3", + "MONITOR_NE4BEG0_6", + "MONITOR_IMUX42_2", + "MONITOR_LH3_7", + "MONITOR_FAN1_8", + "MONITOR_LOGIC_OUTS_B3_1", + "MONITOR_EE4BEG0_9", + "MONITOR_WW4B1_7", + "MONITOR_IMUX11_0", + "MONITOR_LOGIC_OUTS_B23_8", + "MONITOR_LH2_6", + "MONITOR_SE4C1_0", + "MONITOR_BLOCK_OUTS_B2_5", + "MONITOR_IMUX12_9", + "MONITOR_LH10_9", + "MONITOR_LH3_6", + "MONITOR_NE4BEG3_9", + "MONITOR_SW4END0_9", + "MONITOR_LOGIC_OUTS_B1_7", + "MONITOR_SW4A0_7", + "MONITOR_BLOCK_OUTS_B0_9", + "MONITOR_IMUX33_8", + "MONITOR_SE4BEG3_5", + "MONITOR_CLK0_7", + "MONITOR_LH5_6", + "MONITOR_LOGIC_OUTS_B9_9", + "MONITOR_IMUX16_7", + "MONITOR_WW4B3_8", + "MONITOR_WR1END2_4", + "MONITOR_IMUX20_7", + "MONITOR_SE4C0_1", + "MONITOR_FAN0_9", + "MONITOR_FAN3_8", + "MONITOR_NE4BEG1_2", + "MONITOR_EE2BEG1_5", + "MONITOR_NW4END1_7", + "MONITOR_IMUX26_3", + "MONITOR_IMUX23_0", + "MONITOR_IMUX41_9", + "MONITOR_SE4C1_8", + "MONITOR_SW4END2_7", + "MONITOR_FAN3_5", + "MONITOR_IMUX1_4", + "MONITOR_WW4A2_8", + "MONITOR_SE4BEG0_3", + "MONITOR_IMUX5_9", + "MONITOR_SE2A2_7", + "MONITOR_IMUX8_5", + "MONITOR_LOGIC_OUTS_B14_1", + "MONITOR_EE4A1_6", + "MONITOR_EE4A0_7", + "MONITOR_LOGIC_OUTS_B11_4", + "MONITOR_IMUX13_9", + "MONITOR_EE4B2_0", + "MONITOR_LH2_8", + "MONITOR_IMUX0_7", + "MONITOR_WL1END0_0", + "MONITOR_SE4BEG1_3", + "MONITOR_NW4A3_7", + "MONITOR_WW2A0_4", + "MONITOR_IMUX24_4", + "MONITOR_SW4A3_3", + "MONITOR_SW2A1_5", + "MONITOR_EL1BEG2_2", + "MONITOR_WW4C1_2", + "MONITOR_LOGIC_OUTS_B16_8", + "MONITOR_FAN4_2", + "MONITOR_IMUX7_7", + "MONITOR_IMUX0_5", + "MONITOR_WW4B3_0", + "MONITOR_IMUX26_7", + "MONITOR_WW2A0_9", + "MONITOR_SW4A3_5", + "MONITOR_IMUX22_4", + "MONITOR_WW2END2_5", + "MONITOR_NW4A0_0", + "MONITOR_IMUX37_5", + "MONITOR_SE2A1_3", + "MONITOR_BYP4_2", + "MONITOR_WW4C3_9", + "MONITOR_EE4A1_9", + "MONITOR_IMUX23_1", + "MONITOR_IMUX47_6", + "MONITOR_LH8_4", + "MONITOR_NW4A1_5", + "MONITOR_ER1BEG0_7", + "MONITOR_SW4END2_6", + "MONITOR_IMUX31_5", + "MONITOR_LOGIC_OUTS_B17_9", + "MONITOR_WL1END1_4", + "MONITOR_IMUX15_4", + "MONITOR_NE2A2_1", + "MONITOR_NE4BEG0_3", + "MONITOR_WW2END1_6", + "MONITOR_LOGIC_OUTS_B8_2", + "MONITOR_EE4A1_0", + "MONITOR_IMUX47_1", + "MONITOR_WW2A3_7", + "MONITOR_NE4C1_0", + "MONITOR_IMUX15_5", + "MONITOR_EE4B3_0", + "MONITOR_IMUX9_6", + "MONITOR_LH5_0", + "MONITOR_WW4A0_4", + "MONITOR_IMUX7_6", + "MONITOR_NE4BEG2_9", + "MONITOR_WW4A0_2", + "MONITOR_LH12_8", + "MONITOR_SE2A2_2", + "MONITOR_IMUX4_3", + "MONITOR_EE2BEG2_6", + "MONITOR_LH9_7", + "MONITOR_WL1END1_1", + "MONITOR_IMUX9_4", + "MONITOR_EE2BEG1_3", + "MONITOR_IMUX9_7", + "MONITOR_IMUX18_3", + "MONITOR_IMUX15_2", + "MONITOR_WW2END3_1", + "MONITOR_LOGIC_OUTS_B19_6", + "MONITOR_FAN5_0", + "MONITOR_LOGIC_OUTS_B7_4", + "MONITOR_IMUX0_2", + "MONITOR_WW4END0_7", + "MONITOR_SW4A0_1", + "MONITOR_IMUX15_7", + "MONITOR_BYP1_2", + "MONITOR_SW2A2_6", + "MONITOR_NE2A2_6", + "MONITOR_LOGIC_OUTS_B6_9", + "MONITOR_SE2A3_5", + "MONITOR_CTRL0_2", + "MONITOR_WW2A2_4", + "MONITOR_LH5_4", + "MONITOR_EE4BEG2_2", + "MONITOR_LOGIC_OUTS_B0_2", + "MONITOR_NW2A0_2", + "MONITOR_EE4BEG2_4", + "MONITOR_EE4B2_3", + "MONITOR_IMUX14_2", + "MONITOR_LOGIC_OUTS_B8_1", + "MONITOR_SE2A2_5", + "MONITOR_SE2A3_3", + "MONITOR_EE2A3_5", + "MONITOR_WW4C0_7", + "MONITOR_FAN7_9", + "MONITOR_LOGIC_OUTS_B13_7", + "MONITOR_EL1BEG3_4", + "MONITOR_IMUX24_1", + "MONITOR_WW4C1_1", + "MONITOR_LOGIC_OUTS_B17_6", + "MONITOR_BYP2_1", + "MONITOR_IMUX11_6", + "MONITOR_LOGIC_OUTS_B7_0", + "MONITOR_EE2BEG0_8", + "MONITOR_NE4BEG1_0", + "MONITOR_NE2A2_4", + "MONITOR_IMUX3_6", + "MONITOR_NE4C2_0", + "MONITOR_IMUX39_6", + "MONITOR_NE4BEG2_5", + "MONITOR_FAN3_2", + "MONITOR_WW2END1_1", + "MONITOR_BLOCK_OUTS_B0_3", + "MONITOR_NW2A1_5", + "MONITOR_SW4END1_9", + "MONITOR_IMUX25_6", + "MONITOR_IMUX26_0", + "MONITOR_WW2END3_3", + "MONITOR_FAN4_6", + "MONITOR_SW4A0_9", + "MONITOR_NW4END3_9", + "MONITOR_WW2END0_4", + "MONITOR_EE2A3_6", + "MONITOR_BYP3_3", + "MONITOR_EE4C1_8", + "MONITOR_EE2BEG3_1", + "MONITOR_IMUX3_2", + "MONITOR_CLK0_9", + "MONITOR_IMUX22_3", + "MONITOR_WW4A3_5", + "MONITOR_SW4A0_0", + "MONITOR_BLOCK_OUTS_B2_6", + "MONITOR_WL1END2_5", + "MONITOR_EE2A2_9", + "MONITOR_IMUX8_6", + "MONITOR_SW4END0_1", + "MONITOR_NW4END2_7", + "MONITOR_LOGIC_OUTS_B20_5", + "MONITOR_ER1BEG3_9", + "MONITOR_FAN2_7", + "MONITOR_EL1BEG2_8", + "MONITOR_CTRL1_0", + "MONITOR_LH8_0", + "MONITOR_LOGIC_OUTS_B9_1", + "MONITOR_FAN0_8", + "MONITOR_EE4BEG3_2", + "MONITOR_IMUX21_9", + "MONITOR_WW4A1_5", + "MONITOR_NW2A0_3", + "MONITOR_EE4C0_8", + "MONITOR_FAN6_2", + "MONITOR_NW4A2_7", + "MONITOR_IMUX26_6", + "MONITOR_NE2A0_8", + "MONITOR_NE2A0_5", + "MONITOR_WW2A0_2", + "MONITOR_WW2END0_6", + "MONITOR_IMUX39_1", + "MONITOR_BYP5_3", + "MONITOR_IMUX11_4", + "MONITOR_IMUX39_8", + "MONITOR_NW4A1_1", + "MONITOR_NW4END0_2", + "MONITOR_VERT_VAUXP8", + "MONITOR_SW2A0_2", + "MONITOR_VERT_VAUXP11", + "MONITOR_VERT_VAUXN8", + "MONITOR_LOGIC_OUTS_B22_7", + "MONITOR_IMUX27_7", + "MONITOR_VERT_VAUXN3", + "MONITOR_LOGIC_OUTS_B19_1", + "MONITOR_BYP4_5", + "MONITOR_IMUX16_1", + "MONITOR_EE4A3_6", + "MONITOR_NE2A3_0", + "MONITOR_WW4C0_5", + "MONITOR_WW4END0_4", + "MONITOR_IMUX6_3", + "MONITOR_WW4C2_0", + "MONITOR_SE2A0_4", + "MONITOR_LOGIC_OUTS_B20_1", + "MONITOR_WW4A3_7", + "MONITOR_EE2BEG2_9", + "MONITOR_SE4BEG1_0", + "MONITOR_ER1BEG3_3", + "MONITOR_IMUX37_9", + "MONITOR_WW2A2_9", + "MONITOR_IMUX29_5", + "MONITOR_EE2A0_0", + "MONITOR_BLOCK_OUTS_B1_2", + "MONITOR_LOGIC_OUTS_B0_7", + "MONITOR_NW2A0_0", + "MONITOR_IMUX13_8", + "MONITOR_NW2A1_7", + "MONITOR_EL1BEG1_1", + "MONITOR_IMUX39_5", + "MONITOR_FAN5_1", + "MONITOR_EL1BEG0_8", + "MONITOR_LH6_8", + "MONITOR_IMUX38_3", + "MONITOR_BYP3_1", + "MONITOR_LH9_1", + "MONITOR_IMUX6_6", + "MONITOR_FAN6_6", + "MONITOR_LOGIC_OUTS_B20_9", + "MONITOR_SW2A1_0", + "MONITOR_WL1END3_1", + "MONITOR_IMUX38_6", + "MONITOR_IMUX47_7", + "MONITOR_IMUX32_7", + "MONITOR_IMUX22_8", + "MONITOR_IMUX7_2", + "MONITOR_ER1BEG3_2", + "MONITOR_FAN1_3", + "MONITOR_LH2_9", + "MONITOR_BYP1_7", + "MONITOR_HORIZ_VAUXP13", + "MONITOR_LOGIC_OUTS_B4_0", + "MONITOR_SE4BEG0_7", + "MONITOR_EE4C3_8", + "MONITOR_LH11_2", + "MONITOR_BLOCK_OUTS_B1_1", + "MONITOR_IMUX19_7", + "MONITOR_SE4BEG0_6", + "MONITOR_IMUX34_0", + "MONITOR_IMUX27_9", + "MONITOR_NE2A1_5", + "MONITOR_NE4C1_7", + "MONITOR_SE2A1_4", + "MONITOR_NE4C1_9", + "MONITOR_LH10_5", + "MONITOR_NW4A0_5", + "MONITOR_NE4BEG1_7", + "MONITOR_WW2END0_8", + "MONITOR_IMUX10_3", + "MONITOR_WW4A3_1", + "MONITOR_SE4BEG2_5", + "MONITOR_HORIZ_VAUXP9", + "MONITOR_WL1END2_3", + "MONITOR_NW4A0_4", + "MONITOR_NW4END1_0", + "MONITOR_IMUX28_9", + "MONITOR_LOGIC_OUTS_B21_5", + "MONITOR_LOGIC_OUTS_B18_8", + "MONITOR_ER1BEG3_8", + "MONITOR_FAN4_1", + "MONITOR_LOGIC_OUTS_B12_6", + "MONITOR_WW2A1_9", + "MONITOR_LOGIC_OUTS_B21_9", + "MONITOR_VERT_VAUXP0", + "MONITOR_VERT_VAUXN7", + "MONITOR_BYP2_9", + "MONITOR_BYP3_8", + "MONITOR_WW4END2_5", + "MONITOR_NW2A2_6", + "MONITOR_CLK1_8", + "MONITOR_NE2A1_6", + "MONITOR_EE4A3_0", + "MONITOR_NE4C2_9", + "MONITOR_IMUX33_6", + "MONITOR_SW2A3_1", + "MONITOR_SW2A3_3", + "MONITOR_NW2A1_3", + "MONITOR_EE4BEG2_5", + "MONITOR_EE4B2_8", + "MONITOR_NW4END0_0", + "MONITOR_LOGIC_OUTS_B9_8", + "MONITOR_ER1BEG0_9", + "MONITOR_LOGIC_OUTS_B7_8", + "MONITOR_WL1END0_1", + "MONITOR_WR1END0_9", + "MONITOR_VERT_VAUXN15", + "MONITOR_WR1END2_0", + "MONITOR_IMUX21_6", + "MONITOR_SE4BEG0_2", + "MONITOR_SE4C3_2", + "MONITOR_NE2A3_3", + "MONITOR_VERT_VAUXN0", + "MONITOR_IMUX31_0", + "MONITOR_LH2_2", + "MONITOR_IMUX41_3", + "MONITOR_NE4C0_6", + "MONITOR_LOGIC_OUTS_B13_5", + "MONITOR_VERT_VAUXN11", + "MONITOR_IMUX46_7", + "MONITOR_BLOCK_OUTS_B2_0", + "MONITOR_NW4A2_3", + "MONITOR_IMUX21_4", + "MONITOR_NE4C0_2", + "MONITOR_BYP5_1", + "MONITOR_EE4B3_1", + "MONITOR_LOGIC_OUTS_B17_1", + "MONITOR_VERT_VAUXP14", + "MONITOR_IMUX44_1", + "MONITOR_IMUX3_7", + "MONITOR_IMUX37_8", + "MONITOR_IMUX30_4", + "MONITOR_EE2A3_7", + "MONITOR_SW4END0_5", + "MONITOR_BLOCK_OUTS_B0_8", + "MONITOR_LOGIC_OUTS_B14_4", + "MONITOR_WW4B0_1", + "MONITOR_IMUX43_7", + "MONITOR_NW4END3_5", + "MONITOR_IMUX38_2", + "MONITOR_NE4BEG3_2", + "MONITOR_WW4B2_6", + "MONITOR_LOGIC_OUTS_B13_3", + "MONITOR_VERT_VAUXP12", + "MONITOR_BYP6_1", + "MONITOR_BLOCK_OUTS_B1_5", + "MONITOR_LOGIC_OUTS_B13_2", + "MONITOR_IMUX33_3" + ], + "tile_type": "MONITOR_MID", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_MONITOR_TOP.json b/artix7/tile_type_MONITOR_TOP.json index 5c08d18..8df3cba 100644 --- a/artix7/tile_type_MONITOR_TOP.json +++ b/artix7/tile_type_MONITOR_TOP.json @@ -1,1204 +1,1204 @@ { - "wires": [ - "MONITOR_LOGIC_OUTS_B22_3", - "MONITOR_NW4A2_3", - "MONITOR_EE4B1_3", - "MONITOR_EE4BEG0_2", - "MONITOR_WL1END3_3", - "MONITOR_NW4A1_1", - "MONITOR_IMUX2_3", - "MONITOR_SE2A3_2", - "MONITOR_LOGIC_OUTS_B16_2", - "MONITOR_WW4C2_3", - "MONITOR_NW4A0_4", - "MONITOR_IMUX29_0", - "MONITOR_BYP3_3", - "MONITOR_EE4A1_1", - "MONITOR_NW4A3_2", - "MONITOR_WW2END2_0", - "MONITOR_SW4END2_3", - "MONITOR_BLOCK_OUTS_B3_0", - "MONITOR_IMUX25_0", - "MONITOR_LOGIC_OUTS_B3_1", - "MONITOR_ER1BEG3_1", - "MONITOR_ER1BEG2_4", - "MONITOR_WW2END0_0", - "MONITOR_WL1END3_0", - "MONITOR_IMUX44_3", - "MONITOR_WW4C0_1", - "MONITOR_CLK1_0", - "MONITOR_LH12_0", - "MONITOR_WW4A1_3", - "MONITOR_WW2A1_3", - "MONITOR_IMUX22_0", - "MONITOR_VERT_SHORT_VAUXP6", - "MONITOR_SE4BEG2_1", - "MONITOR_NE4BEG3_4", - "MONITOR_IMUX23_0", - "MONITOR_WW4A3_2", - "MONITOR_EE4B0_4", - "MONITOR_IMUX7_4", - "MONITOR_NE4BEG2_2", - "MONITOR_LH6_1", - "MONITOR_EE2BEG0_4", - "MONITOR_EE4B2_1", - "MONITOR_BYP5_4", - "MONITOR_IMUX28_2", - "MONITOR_IMUX31_0", - "MONITOR_IMUX20_0", - "MONITOR_BLOCK_OUTS_B3_4", - "MONITOR_SE4BEG0_2", - "MONITOR_LOGIC_OUTS_B5_1", - "MONITOR_ER1BEG0_4", - "MONITOR_IMUX18_0", - "MONITOR_NE4C1_3", - "MONITOR_IMUX3_2", - "MONITOR_NW4A1_2", - "MONITOR_SW4END3_0", - "MONITOR_BLOCK_OUTS_B1_3", - "MONITOR_FAN0_4", - "MONITOR_IMUX9_1", - "MONITOR_LOGIC_OUTS_B0_2", - "MONITOR_VERT_SHORT_VAUXN5", - "MONITOR_EL1BEG0_1", - "MONITOR_SE4BEG2_2", - "MONITOR_LOGIC_OUTS_B16_0", - "MONITOR_LOGIC_OUTS_B3_0", - "MONITOR_LOGIC_OUTS_B16_4", - "MONITOR_EE4B1_2", - "MONITOR_WW4B2_2", - "MONITOR_IMUX26_0", - "MONITOR_WW2A1_0", - "MONITOR_LOGIC_OUTS_B18_0", - "MONITOR_SW4END1_2", - "MONITOR_EE4BEG1_1", - "MONITOR_IMUX30_0", - "MONITOR_NW4END2_0", - "MONITOR_LH9_4", - "MONITOR_NE4C2_1", - "MONITOR_EE2BEG2_4", - "MONITOR_IMUX0_4", - "MONITOR_EE4A3_3", - "MONITOR_NE2A2_4", - "MONITOR_VERT_SHORT_VAUXN6", - "MONITOR_VERT_SHORT_VAUXN10", - "MONITOR_WW4END3_4", - "MONITOR_IMUX19_2", - "MONITOR_IMUX13_0", - "MONITOR_LOGIC_OUTS_B19_2", - "MONITOR_WL1END2_0", - "MONITOR_LOGIC_OUTS_B2_0", - "MONITOR_LOGIC_OUTS_B20_1", - "MONITOR_LOGIC_OUTS_B21_0", - "MONITOR_SW4A2_2", - "MONITOR_BYP0_0", - "MONITOR_IMUX31_1", - "MONITOR_WR1END0_3", - "MONITOR_BYP0_3", - "MONITOR_IMUX24_2", - "MONITOR_LOGIC_OUTS_B20_2", - "MONITOR_ER1BEG1_4", - "MONITOR_LOGIC_OUTS_B17_1", - "MONITOR_EE4A0_0", - "MONITOR_FAN0_1", - "MONITOR_WL1END1_2", - "MONITOR_EE4C1_1", - "MONITOR_IMUX5_0", - "MONITOR_IMUX4_3", - "MONITOR_EE4C0_3", - "MONITOR_EE2BEG3_1", - "MONITOR_SE4C0_4", - "MONITOR_IMUX37_1", - "MONITOR_EE2BEG1_1", - "MONITOR_IMUX34_0", - "MONITOR_WW4A0_3", - "MONITOR_IMUX9_3", - "MONITOR_NW4A3_4", - "MONITOR_SW4END1_3", - "MONITOR_SW4A0_4", - "MONITOR_SE2A3_0", - "MONITOR_IMUX10_3", - "MONITOR_WW4A3_3", - "MONITOR_IMUX28_3", - "MONITOR_IMUX22_1", - "MONITOR_IMUX43_4", - "MONITOR_SW2A3_0", - "MONITOR_LH10_4", - "MONITOR_IMUX36_0", - "MONITOR_SE4C2_0", - "MONITOR_VERT_SHORT_VAUXN11", - "MONITOR_LH10_2", - "MONITOR_IMUX28_0", - "MONITOR_WW4C1_4", - "MONITOR_EE4C3_2", - "MONITOR_NW4END1_1", - "MONITOR_LH7_4", - "MONITOR_SW4A1_2", - "MONITOR_IMUX7_0", - "MONITOR_VERT_SHORT_VAUXP5", - "MONITOR_VERT_SHORT_VAUXN15", - "MONITOR_SE2A3_1", - "MONITOR_EE4B3_0", - "MONITOR_NW2A0_2", - "MONITOR_IMUX20_2", - "MONITOR_CLK0_4", - "MONITOR_EE2BEG3_0", - "MONITOR_FAN1_0", - "MONITOR_LH12_4", - "MONITOR_IMUX45_0", - "MONITOR_LOGIC_OUTS_B1_0", - "MONITOR_EE4BEG3_2", - "MONITOR_IMUX43_3", - "MONITOR_IMUX28_4", - "MONITOR_WW2A3_0", - "MONITOR_IMUX5_1", - "MONITOR_EE4C1_3", - "MONITOR_BYP1_2", - "MONITOR_EE4BEG3_3", - "MONITOR_EE2A1_2", - "MONITOR_WW4B1_2", - "MONITOR_WW2END2_3", - "MONITOR_EE4C2_4", - "MONITOR_HORIZ_VAUXN12", - "MONITOR_WW4C0_3", - "MONITOR_FAN6_2", - "MONITOR_FAN5_1", - "MONITOR_LOGIC_OUTS_B10_2", - "MONITOR_WW4A3_4", - "MONITOR_IMUX7_1", - "MONITOR_IMUX35_0", - "MONITOR_NW4END1_4", - "MONITOR_LH1_0", - "MONITOR_EE2A1_0", - "MONITOR_NW2A0_3", - "MONITOR_BLOCK_OUTS_B1_2", - "MONITOR_IMUX11_0", - "MONITOR_NW2A2_1", - "MONITOR_EE2A1_3", - "MONITOR_FAN1_4", - "MONITOR_LOGIC_OUTS_B13_0", - "MONITOR_NE4BEG1_1", - "MONITOR_BLOCK_OUTS_B3_2", - "MONITOR_SW2A0_1", - "MONITOR_NW2A1_2", - "MONITOR_WW4END1_4", - "MONITOR_BLOCK_OUTS_B3_3", - "MONITOR_EE2BEG1_2", - "MONITOR_SW4END0_4", - "MONITOR_EE4B1_4", - "MONITOR_IMUX41_1", - "MONITOR_NW4END0_4", - "MONITOR_NW4A0_1", - "MONITOR_IMUX17_1", - "MONITOR_IMUX21_1", - "MONITOR_NE2A1_4", - "MONITOR_EE2BEG0_0", - "MONITOR_IMUX44_1", - "MONITOR_IMUX46_1", - "MONITOR_NW4END3_2", - "MONITOR_IMUX44_0", - "MONITOR_WR1END3_4", - "MONITOR_LH12_2", - "MONITOR_SE4C0_3", - "MONITOR_LOGIC_OUTS_B15_4", - "MONITOR_SE2A1_4", - "MONITOR_EE2BEG0_3", - "MONITOR_WW2END3_1", - "MONITOR_LOGIC_OUTS_B18_4", - "MONITOR_WW2END1_4", - "MONITOR_SE4C3_3", - "MONITOR_WW2A3_4", - "MONITOR_NE4BEG3_2", - "MONITOR_NW2A3_1", - "MONITOR_LOGIC_OUTS_B9_2", - "MONITOR_LOGIC_OUTS_B10_3", - "MONITOR_BYP6_1", - "MONITOR_LH6_3", - "MONITOR_NW2A1_3", - "MONITOR_SW4A1_3", - "MONITOR_IMUX19_0", - "MONITOR_NE2A1_2", - "MONITOR_VERT_SHORT_VAUXP2", - "MONITOR_NW4END1_0", - "MONITOR_LOGIC_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B18_1", - "MONITOR_WW4C2_1", - "MONITOR_IMUX30_2", - "MONITOR_NE4BEG2_1", - "MONITOR_WR1END0_1", - "MONITOR_NW2A2_4", - "MONITOR_IMUX24_0", - "MONITOR_WW4A3_0", - "MONITOR_WR1END2_0", - "MONITOR_LOGIC_OUTS_B6_2", - "MONITOR_WW4B3_4", - "MONITOR_SW4END2_2", - "MONITOR_NW2A0_1", - "MONITOR_ER1BEG0_3", - "MONITOR_IMUX40_3", - "MONITOR_EL1BEG0_0", - "MONITOR_WW4A1_2", - "MONITOR_BYP0_2", - "MONITOR_NE4BEG0_0", - "MONITOR_LH8_0", - "MONITOR_EE4BEG1_2", - "MONITOR_WW2A0_0", - "MONITOR_NE4BEG0_3", - "MONITOR_LOGIC_OUTS_B12_2", - "MONITOR_LOGIC_OUTS_B1_2", - "MONITOR_NW4END0_1", - "MONITOR_WW4A2_2", - "MONITOR_IMUX32_2", - "MONITOR_BYP1_3", - "MONITOR_EE2A3_2", - "MONITOR_IMUX12_4", - "MONITOR_SE2A0_4", - "MONITOR_IMUX10_0", - "MONITOR_SE4C2_1", - "MONITOR_VERT_SHORT_VAUXN4", - "MONITOR_FAN2_1", - "MONITOR_EE4A2_1", - "MONITOR_WW4B2_1", - "MONITOR_FAN1_1", - "MONITOR_IMUX7_3", - "MONITOR_IMUX29_3", - "MONITOR_LOGIC_OUTS_B15_3", - "MONITOR_NE4BEG1_2", - "MONITOR_IMUX27_4", - "MONITOR_NW4A1_0", - "MONITOR_IMUX10_1", - "MONITOR_IMUX36_2", - "MONITOR_WR1END2_2", - "MONITOR_LH10_3", - "MONITOR_IMUX10_2", - "MONITOR_BYP4_1", - "MONITOR_IMUX18_2", - "MONITOR_EE2A3_1", - "MONITOR_BYP1_4", - "MONITOR_CLK0_2", - "MONITOR_SE4BEG2_4", - "MONITOR_SE4C2_2", - "MONITOR_IMUX7_2", - "MONITOR_IMUX16_4", - "MONITOR_BLOCK_OUTS_B2_3", - "MONITOR_CLK1_2", - "MONITOR_NE4C2_3", - "MONITOR_VERT_SHORT_VAUXP9", - "MONITOR_EE4C0_2", - "MONITOR_WW2A2_0", - "MONITOR_EL1BEG3_1", - "MONITOR_EE2A3_3", - "MONITOR_NW4A2_0", - "MONITOR_NW4A0_2", - "MONITOR_SE4BEG1_2", - "MONITOR_IMUX43_1", - "MONITOR_WW4B3_3", - "MONITOR_CLK0_1", - "MONITOR_WL1END0_2", - "MONITOR_FAN0_2", - "MONITOR_SE2A0_0", - "MONITOR_EE4BEG3_1", - "MONITOR_IMUX3_3", - "MONITOR_LOGIC_OUTS_B1_3", - "MONITOR_SE4BEG1_3", - "MONITOR_IMUX19_3", - "MONITOR_BYP5_2", - "MONITOR_WW2A0_4", - "MONITOR_WL1END3_1", - "MONITOR_VERT_SHORT_VAUXP1", - "MONITOR_EE4BEG2_0", - "MONITOR_IMUX40_1", - "MONITOR_WW2A0_3", - "MONITOR_WW4B0_4", - "MONITOR_EE4BEG2_3", - "MONITOR_LOGIC_OUTS_B14_4", - "MONITOR_NE4BEG3_3", - "MONITOR_SE4C3_0", - "MONITOR_LH10_1", - "MONITOR_VERT_SHORT_VAUXP15", - "MONITOR_WR1END3_1", - "MONITOR_VERT_SHORT_VAUXN7", - "MONITOR_EL1BEG0_3", - "MONITOR_FAN7_2", - "MONITOR_IMUX32_1", - "MONITOR_CTRL0_2", - "MONITOR_SE2A2_0", - "MONITOR_BYP3_1", - "MONITOR_LOGIC_OUTS_B12_1", - "MONITOR_WW2END3_3", - "MONITOR_LOGIC_OUTS_B5_0", - "MONITOR_SW4A1_0", - "MONITOR_WW4A0_1", - "MONITOR_IMUX37_4", - "MONITOR_NE2A3_0", - "MONITOR_WW2END2_2", - "MONITOR_WW4C3_3", - "MONITOR_ER1BEG3_3", - "MONITOR_IMUX16_1", - "MONITOR_SW4END1_4", - "MONITOR_NW2A0_4", - "MONITOR_EE4A3_0", - "MONITOR_WR1END1_2", - "MONITOR_SW2A3_1", - "MONITOR_FAN4_2", - "MONITOR_ER1BEG3_4", - "MONITOR_EE2A1_4", - "MONITOR_WR1END3_3", - "MONITOR_EE4A0_1", - "MONITOR_LOGIC_OUTS_B7_2", - "MONITOR_LH3_1", - "MONITOR_NE4C3_1", - "MONITOR_IMUX36_4", - "MONITOR_LOGIC_OUTS_B8_4", - "MONITOR_FAN6_1", - "MONITOR_IMUX47_2", - "MONITOR_LH7_3", - "MONITOR_IMUX22_3", - "MONITOR_ER1BEG0_2", - "MONITOR_EE4A2_0", - "MONITOR_VERT_SHORT_VAUXN0", - "MONITOR_NW4A3_1", - "MONITOR_IMUX40_2", - "MONITOR_VERT_SHORT_VAUXP3", - "MONITOR_CTRL1_4", - "MONITOR_LOGIC_OUTS_B2_1", - "MONITOR_IMUX4_2", - "MONITOR_LH5_3", - "MONITOR_IMUX29_2", - "MONITOR_LOGIC_OUTS_B11_2", - "MONITOR_IMUX42_2", - "MONITOR_IMUX39_1", - "MONITOR_NE4C2_0", - "MONITOR_LOGIC_OUTS_B5_2", - "MONITOR_WW2END3_4", - "MONITOR_IMUX27_2", - "MONITOR_SW4END2_0", - "MONITOR_EL1BEG1_0", - "MONITOR_EE2BEG2_1", - "MONITOR_FAN5_0", - "MONITOR_NE2A1_3", - "MONITOR_IMUX11_1", - "MONITOR_IMUX12_0", - "MONITOR_LOGIC_OUTS_B9_1", - "MONITOR_WW4END3_3", - "MONITOR_IMUX26_4", - "MONITOR_BYP6_0", - "MONITOR_IMUX3_1", - "MONITOR_EE4BEG1_4", - "MONITOR_IMUX13_1", - "MONITOR_LOGIC_OUTS_B11_4", - "MONITOR_LOGIC_OUTS_B11_0", - "MONITOR_EE4B0_1", - "MONITOR_LOGIC_OUTS_B9_3", - "MONITOR_FAN2_3", - "MONITOR_VERT_SHORT_VAUXP4", - "MONITOR_LOGIC_OUTS_B3_4", - "MONITOR_WW4B1_4", - "MONITOR_SE4C1_1", - "MONITOR_LOGIC_OUTS_B20_4", - "MONITOR_IMUX27_3", - "MONITOR_IMUX36_3", - "MONITOR_WL1END1_0", - "MONITOR_LOGIC_OUTS_B4_3", - "MONITOR_IMUX17_3", - "MONITOR_BYP6_2", - "MONITOR_IMUX24_4", - "MONITOR_SW2A0_2", - "MONITOR_BLOCK_OUTS_B2_4", - "MONITOR_BYP3_4", - "MONITOR_WW2END2_4", - "MONITOR_SE4C2_3", - "MONITOR_IMUX20_4", - "MONITOR_SW4END3_2", - "MONITOR_IMUX17_0", - "MONITOR_LOGIC_OUTS_B16_1", - "MONITOR_LOGIC_OUTS_B23_4", - "MONITOR_IMUX43_0", - "MONITOR_NW2A2_3", - "MONITOR_IMUX8_0", - "MONITOR_LOGIC_OUTS_B3_2", - "MONITOR_LH12_3", - "MONITOR_LOGIC_OUTS_B5_3", - "MONITOR_LOGIC_OUTS_B15_2", - "MONITOR_WR1END0_2", - "MONITOR_IMUX21_4", - "MONITOR_SE2A1_0", - "MONITOR_IMUX23_2", - "MONITOR_WW4END0_4", - "MONITOR_NW4END2_4", - "MONITOR_WW2END1_2", - "MONITOR_WR1END2_1", - "MONITOR_IMUX45_2", - "MONITOR_IMUX30_3", - "MONITOR_NE4C3_2", - "MONITOR_IMUX0_1", - "MONITOR_LH7_1", - "MONITOR_NW4END2_2", - "MONITOR_SE2A3_4", - "MONITOR_SE4C1_2", - "MONITOR_CTRL1_1", - "MONITOR_NE4C3_0", - "MONITOR_LH6_0", - "MONITOR_IMUX41_4", - "MONITOR_VERT_SHORT_VAUXN12", - "MONITOR_IMUX6_3", - "MONITOR_LOGIC_OUTS_B20_3", - "MONITOR_VERT_SHORT_VAUXN3", - "MONITOR_BYP1_0", - "MONITOR_LOGIC_OUTS_B13_4", - "MONITOR_EE2A2_2", - "MONITOR_WR1END1_0", - "MONITOR_LOGIC_OUTS_B14_3", - "MONITOR_WW4C3_4", - "MONITOR_EE4A1_0", - "MONITOR_IMUX23_1", - "MONITOR_NW4END0_3", - "MONITOR_NE4BEG0_1", - "MONITOR_SW4A3_2", - "MONITOR_WR1END3_0", - "MONITOR_LOGIC_OUTS_B14_1", - "MONITOR_NE2A1_0", - "MONITOR_NW2A3_0", - "MONITOR_SE2A1_1", - "MONITOR_WW4B0_1", - "MONITOR_SE2A2_2", - "MONITOR_IMUX47_0", - "MONITOR_ER1BEG1_3", - "MONITOR_WR1END2_3", - "MONITOR_NE4BEG1_4", - "MONITOR_WW2END1_0", - "MONITOR_IMUX9_4", - "MONITOR_IMUX26_1", - "MONITOR_WW2A2_3", - "MONITOR_EE4B3_2", - "MONITOR_IMUX4_1", - "MONITOR_NE4C1_4", - "MONITOR_WW2A0_1", - "MONITOR_NW4A1_4", - "MONITOR_WW4C1_2", - "MONITOR_ER1BEG0_0", - "MONITOR_LOGIC_OUTS_B22_4", - "MONITOR_EL1BEG3_2", - "MONITOR_CLK1_3", - "MONITOR_WW4B3_0", - "MONITOR_WW2END3_0", - "MONITOR_FAN3_0", - "MONITOR_LH2_0", - "MONITOR_IMUX24_1", - "MONITOR_EE2BEG1_3", - "MONITOR_IMUX15_4", - "MONITOR_NE4BEG1_0", - "MONITOR_SE4BEG3_3", - "MONITOR_SE4C3_2", - "MONITOR_LOGIC_OUTS_B15_0", - "MONITOR_FAN7_4", - "MONITOR_NE4C0_0", - "MONITOR_CLK0_3", - "MONITOR_IMUX2_2", - "MONITOR_IMUX41_2", - "MONITOR_LH4_4", - "MONITOR_NE4C1_1", - "MONITOR_WW4C3_0", - "MONITOR_WW4B1_3", - "MONITOR_EL1BEG2_3", - "MONITOR_IMUX6_4", - "MONITOR_LH3_0", - "MONITOR_NE2A0_4", - "MONITOR_LOGIC_OUTS_B10_4", - "MONITOR_NE4C0_1", - "MONITOR_CTRL0_1", - "MONITOR_IMUX27_0", - "MONITOR_IMUX25_2", - "MONITOR_NE2A0_0", - "MONITOR_EE2BEG2_0", - "MONITOR_IMUX19_4", - "MONITOR_NE4C0_3", - "MONITOR_SE4BEG0_4", - "MONITOR_IMUX21_3", - "MONITOR_LOGIC_OUTS_B4_0", - "MONITOR_IMUX14_1", - "MONITOR_EE4BEG0_4", - "MONITOR_CTRL1_2", - "MONITOR_EE2A3_4", - "MONITOR_EE4BEG1_0", - "MONITOR_SE4BEG2_3", - "MONITOR_HORIZ_VAUXN0", - "MONITOR_CLK1_1", - "MONITOR_EE4A1_4", - "MONITOR_NW4END1_3", - "MONITOR_BYP2_0", - "MONITOR_NW2A1_0", - "MONITOR_WW4END2_4", - "MONITOR_IMUX15_2", - "MONITOR_WW4B0_2", - "MONITOR_HORIZ_VAUXP12", - "MONITOR_EE4BEG0_0", - "MONITOR_ER1BEG2_0", - "MONITOR_BYP7_2", - "MONITOR_IMUX5_3", - "MONITOR_LOGIC_OUTS_B21_1", - "MONITOR_EE2A1_1", - "MONITOR_IMUX30_4", - "MONITOR_LOGIC_OUTS_B19_0", - "MONITOR_IMUX8_4", - "MONITOR_IMUX31_4", - "MONITOR_SW4A3_3", - "MONITOR_LOGIC_OUTS_B9_0", - "MONITOR_HORIZ_VAUXP4", - "MONITOR_CTRL0_3", - "MONITOR_BLOCK_OUTS_B0_0", - "MONITOR_LH9_2", - "MONITOR_WW4C1_3", - "MONITOR_WW4A2_3", - "MONITOR_NW2A2_0", - "MONITOR_BYP7_3", - "MONITOR_LH2_2", - "MONITOR_IMUX2_1", - "MONITOR_FAN0_0", - "MONITOR_EE2A0_1", - "MONITOR_IMUX21_2", - "MONITOR_ER1BEG2_3", - "MONITOR_IMUX34_2", - "MONITOR_WW4A2_4", - "MONITOR_IMUX37_3", - "MONITOR_NE2A3_2", - "MONITOR_NE4C0_4", - "MONITOR_VERT_SHORT_VAUXN1", - "MONITOR_LOGIC_OUTS_B2_3", - "MONITOR_IMUX15_3", - "MONITOR_IMUX12_3", - "MONITOR_NE4BEG3_0", - "MONITOR_EE4A0_2", - "MONITOR_NE2A2_1", - "MONITOR_LH12_1", - "MONITOR_SW4END3_1", - "MONITOR_WW4END0_2", - "MONITOR_HORIZ_VAUXN4", - "MONITOR_IMUX14_4", - "MONITOR_IMUX15_1", - "MONITOR_LOGIC_OUTS_B23_2", - "MONITOR_LOGIC_OUTS_B13_1", - "MONITOR_ER1BEG2_2", - "MONITOR_LOGIC_OUTS_B5_4", - "MONITOR_IMUX35_1", - "MONITOR_NW2A3_4", - "MONITOR_NW2A1_4", - "MONITOR_IMUX31_3", - "MONITOR_SE4BEG2_0", - "MONITOR_IMUX32_4", - "MONITOR_LOGIC_OUTS_B15_1", - "MONITOR_SW4END3_3", - "MONITOR_FAN5_4", - "MONITOR_SW2A2_2", - "MONITOR_BYP7_1", - "MONITOR_WW4A0_2", - "MONITOR_LH1_3", - "MONITOR_FAN3_2", - "MONITOR_WW4B3_2", - "MONITOR_SW2A2_1", - "MONITOR_FAN2_4", - "MONITOR_IMUX4_4", - "MONITOR_LH8_4", - "MONITOR_LH5_4", - "MONITOR_EE4C0_1", - "MONITOR_IMUX33_1", - "MONITOR_NW4A3_0", - "MONITOR_NW4END0_2", - "MONITOR_IMUX17_2", - "MONITOR_WR1END1_1", - "MONITOR_VERT_SHORT_VAUXN2", - "MONITOR_NE4BEG2_4", - "MONITOR_IMUX2_0", - "MONITOR_LH11_1", - "MONITOR_LH2_1", - "MONITOR_SE2A1_3", - "MONITOR_CTRL1_3", - "MONITOR_VERT_SHORT_VAUXN8", - "MONITOR_IMUX29_1", - "MONITOR_NW4END3_4", - "MONITOR_NW4A0_0", - "MONITOR_WW2END0_1", - "MONITOR_LOGIC_OUTS_B17_4", - "MONITOR_WW4B2_0", - "MONITOR_LOGIC_OUTS_B22_0", - "MONITOR_WW4C0_2", - "MONITOR_EE2BEG2_3", - "MONITOR_WL1END3_4", - "MONITOR_IMUX46_3", - "MONITOR_WW4END3_0", - "MONITOR_WR1END1_4", - "MONITOR_BYP2_2", - "MONITOR_IMUX37_2", - "MONITOR_FAN5_3", - "MONITOR_WW4B2_4", - "MONITOR_SW2A1_4", - "MONITOR_LOGIC_OUTS_B12_3", - "MONITOR_EE4C1_0", - "MONITOR_LOGIC_OUTS_B12_0", - "MONITOR_LH7_2", - "MONITOR_EE4B3_1", - "MONITOR_LH6_4", - "MONITOR_EE2A0_2", - "MONITOR_IMUX3_0", - "MONITOR_WW4A2_0", - "MONITOR_VERT_SHORT_VAUXP11", - "MONITOR_IMUX47_3", - "MONITOR_WR1END2_4", - "MONITOR_IMUX6_1", - "MONITOR_WW4END2_2", - "MONITOR_WW4C2_4", - "MONITOR_ER1BEG1_2", - "MONITOR_WW4B3_1", - "MONITOR_IMUX41_3", - "MONITOR_LH8_2", - "MONITOR_WW4END0_1", - "MONITOR_SE2A0_1", - "MONITOR_NW2A3_3", - "MONITOR_NW4END3_3", - "MONITOR_NW2A1_1", - "MONITOR_EE4C2_1", - "MONITOR_BLOCK_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B10_0", - "MONITOR_HORIZ_VAUXP0", - "MONITOR_IMUX33_3", - "MONITOR_IMUX18_4", - "MONITOR_WW4END1_1", - "MONITOR_FAN2_0", - "MONITOR_LOGIC_OUTS_B2_4", - "MONITOR_IMUX33_0", - "MONITOR_EE4A3_4", - "MONITOR_FAN3_3", - "MONITOR_LOGIC_OUTS_B22_2", - "MONITOR_NW4A2_1", - "MONITOR_FAN4_3", - "MONITOR_SW4A3_0", - "MONITOR_FAN5_2", - "MONITOR_SE4BEG0_1", - "MONITOR_WW4B2_3", - "MONITOR_IMUX15_0", - "MONITOR_WW2A1_1", - "MONITOR_WW4B0_3", - "MONITOR_IMUX35_2", - "MONITOR_WL1END2_1", - "MONITOR_IMUX39_4", - "MONITOR_NE4C1_0", - "MONITOR_LOGIC_OUTS_B0_4", - "MONITOR_BYP1_1", - "MONITOR_SE4BEG3_4", - "MONITOR_FAN4_1", - "MONITOR_LOGIC_OUTS_B4_2", - "MONITOR_SE4C0_1", - "MONITOR_NE2A3_3", - "MONITOR_FAN6_4", - "MONITOR_LH2_4", - "MONITOR_EE4B1_0", - "MONITOR_NE4C3_4", - "MONITOR_WL1END1_3", - "MONITOR_IMUX13_4", - "MONITOR_BYP5_0", - "MONITOR_VERT_SHORT_VAUXN14", - "MONITOR_ER1BEG1_1", - "MONITOR_IMUX26_3", - "MONITOR_BLOCK_OUTS_B0_4", - "MONITOR_WW4END3_1", - "MONITOR_SW2A1_2", - "MONITOR_LH5_1", - "MONITOR_IMUX3_4", - "MONITOR_EE2BEG3_2", - "MONITOR_NW4A3_3", - "MONITOR_NE4BEG0_4", - "MONITOR_WW2END1_1", - "MONITOR_BLOCK_OUTS_B3_1", - "MONITOR_ER1BEG2_1", - "MONITOR_BYP3_2", - "MONITOR_CTRL0_0", - "MONITOR_LOGIC_OUTS_B8_2", - "MONITOR_WW2A2_2", - "MONITOR_EE4B2_3", - "MONITOR_EL1BEG1_3", - "MONITOR_FAN4_4", - "MONITOR_EE2BEG3_3", - "MONITOR_WR1END0_4", - "MONITOR_ER1BEG0_1", - "MONITOR_NE2A2_0", - "MONITOR_SW4A1_4", - "MONITOR_NE4BEG2_3", - "MONITOR_EE4A2_3", - "MONITOR_LOGIC_OUTS_B19_1", - "MONITOR_SW4END0_2", - "MONITOR_EE2BEG0_2", - "MONITOR_WW2END2_1", - "MONITOR_EE4BEG3_4", - "MONITOR_SE2A3_3", - "MONITOR_IMUX18_1", - "MONITOR_SE2A0_3", - "MONITOR_IMUX27_1", - "MONITOR_IMUX8_1", - "MONITOR_BLOCK_OUTS_B2_0", - "MONITOR_IMUX16_3", - "MONITOR_WW2END3_2", - "MONITOR_LOGIC_OUTS_B21_3", - "MONITOR_SW2A0_4", - "MONITOR_VERT_SHORT_VAUXP13", - "MONITOR_IMUX20_3", - "MONITOR_IMUX32_3", - "MONITOR_SE4C2_4", - "MONITOR_BYP2_1", - "MONITOR_LH11_2", - "MONITOR_VERT_SHORT_VAUXN9", - "MONITOR_EE4A0_3", - "MONITOR_LOGIC_OUTS_B12_4", - "MONITOR_EE4B1_1", - "MONITOR_WW2END0_3", - "MONITOR_IMUX39_3", - "MONITOR_IMUX16_2", - "MONITOR_LOGIC_OUTS_B17_3", - "MONITOR_LOGIC_OUTS_B3_3", - "MONITOR_SE4BEG1_1", - "MONITOR_IMUX23_3", - "MONITOR_SE4BEG0_3", - "MONITOR_IMUX41_0", - "MONITOR_IMUX42_0", - "MONITOR_EE4B0_3", - "MONITOR_WL1END1_1", - "MONITOR_WW4A0_0", - "MONITOR_BYP4_2", - "MONITOR_FAN2_2", - "MONITOR_NW4A0_3", - "MONITOR_NW4A2_2", - "MONITOR_SE4C1_4", - "MONITOR_FAN7_3", - "MONITOR_LOGIC_OUTS_B21_2", - "MONITOR_EE4BEG2_1", - "MONITOR_LOGIC_OUTS_B6_0", - "MONITOR_BYP3_0", - "MONITOR_IMUX33_4", - "MONITOR_NE4C2_2", - "MONITOR_WW4A3_1", - "MONITOR_NW4A2_4", - "MONITOR_BYP2_4", - "MONITOR_LH8_1", - "MONITOR_HORIZ_VAUXP8", - "MONITOR_WW4C2_0", - "MONITOR_LOGIC_OUTS_B6_4", - "MONITOR_SE4C3_1", - "MONITOR_IMUX45_3", - "MONITOR_SW4END1_1", - "MONITOR_IMUX11_3", - "MONITOR_EE4C3_4", - "MONITOR_IMUX14_3", - "MONITOR_IMUX29_4", - "MONITOR_SW4A2_0", - "MONITOR_IMUX44_4", - "MONITOR_IMUX35_4", - "MONITOR_WW4END2_0", - "MONITOR_SE4BEG0_0", - "MONITOR_IMUX42_3", - "MONITOR_SE4C0_0", - "MONITOR_SW2A3_4", - "MONITOR_SW4END2_4", - "MONITOR_LOGIC_OUTS_B7_1", - "MONITOR_WL1END2_4", - "MONITOR_EE4BEG1_3", - "MONITOR_EE4A1_3", - "MONITOR_IMUX45_1", - "MONITOR_IMUX38_4", - "MONITOR_SE4BEG1_0", - "MONITOR_IMUX42_1", - "MONITOR_EE4C2_2", - "MONITOR_BLOCK_OUTS_B1_1", - "MONITOR_LOGIC_OUTS_B17_0", - "MONITOR_LOGIC_OUTS_B7_4", - "MONITOR_WW2A1_2", - "MONITOR_FAN6_3", - "MONITOR_BLOCK_OUTS_B1_4", - "MONITOR_IMUX38_0", - "MONITOR_EE4C0_0", - "MONITOR_SW4A2_1", - "MONITOR_IMUX12_1", - "MONITOR_WL1END3_2", - "MONITOR_NW4END2_1", - "MONITOR_WL1END0_3", - "MONITOR_EL1BEG2_1", - "MONITOR_BYP0_1", - "MONITOR_IMUX1_0", - "MONITOR_SE4C0_2", - "MONITOR_LOGIC_OUTS_B11_3", - "MONITOR_WW4C3_1", - "MONITOR_LH4_3", - "MONITOR_EE4C3_1", - "MONITOR_SW2A3_3", - "MONITOR_IMUX12_2", - "MONITOR_IMUX40_4", - "MONITOR_SW2A0_3", - "MONITOR_IMUX39_2", - "MONITOR_LH9_0", - "MONITOR_CLK0_0", - "MONITOR_IMUX21_0", - "MONITOR_SW4END0_1", - "MONITOR_NE4BEG2_0", - "MONITOR_LH4_1", - "MONITOR_LH7_0", - "MONITOR_LH11_4", - "MONITOR_LOGIC_OUTS_B13_2", - "MONITOR_IMUX10_4", - "MONITOR_LOGIC_OUTS_B6_1", - "MONITOR_LH2_3", - "MONITOR_NE2A2_3", - "MONITOR_WW4END2_1", - "MONITOR_EE4B2_2", - "MONITOR_LOGIC_OUTS_B19_4", - "MONITOR_WW2END0_2", - "MONITOR_ER1BEG3_2", - "MONITOR_NE2A3_1", - "MONITOR_WW4B0_0", - "MONITOR_IMUX31_2", - "MONITOR_WW2END1_3", - "MONITOR_EE4A2_2", - "MONITOR_IMUX1_2", - "MONITOR_LH1_2", - "MONITOR_LH6_2", - "MONITOR_EE4C1_4", - "MONITOR_IMUX38_1", - "MONITOR_EE4B0_2", - "MONITOR_LOGIC_OUTS_B1_1", - "MONITOR_BLOCK_OUTS_B0_2", - "MONITOR_IMUX16_0", - "MONITOR_WW4END2_3", - "MONITOR_LOGIC_OUTS_B23_3", - "MONITOR_WW2A3_3", - "MONITOR_EL1BEG1_2", - "MONITOR_NE2A0_1", - "MONITOR_WW4C0_4", - "MONITOR_BYP7_0", - "MONITOR_SW2A0_0", - "MONITOR_SW2A2_4", - "MONITOR_BLOCK_OUTS_B2_1", - "MONITOR_WW2A2_4", - "MONITOR_WW4C1_0", - "MONITOR_LH11_3", - "MONITOR_LOGIC_OUTS_B18_2", - "MONITOR_EE2A0_3", - "MONITOR_LOGIC_OUTS_B8_1", - "MONITOR_EE4B0_0", - "MONITOR_IMUX24_3", - "MONITOR_SW4A2_3", - "MONITOR_WL1END1_4", - "MONITOR_FAN1_3", - "MONITOR_WW4C1_1", - "MONITOR_LOGIC_OUTS_B9_4", - "MONITOR_WW4END0_0", - "MONITOR_EL1BEG3_0", - "MONITOR_NE4BEG1_3", - "MONITOR_LH10_0", - "MONITOR_NW2A3_2", - "MONITOR_EE2A0_0", - "MONITOR_EL1BEG3_3", - "MONITOR_LOGIC_OUTS_B17_2", - "MONITOR_WW4A1_0", - "MONITOR_WW2A2_1", - "MONITOR_WW4C2_2", - "MONITOR_IMUX8_2", - "MONITOR_EE2BEG1_4", - "MONITOR_WR1END3_2", - "MONITOR_IMUX8_3", - "MONITOR_SE2A0_2", - "MONITOR_LH4_0", - "MONITOR_WR1END1_3", - "MONITOR_LH4_2", - "MONITOR_SW4A0_0", - "MONITOR_EE4BEG0_1", - "MONITOR_WL1END0_4", - "MONITOR_SW4A3_1", - "MONITOR_EL1BEG2_4", - "MONITOR_IMUX1_1", - "MONITOR_EE4BEG0_3", - "MONITOR_LOGIC_OUTS_B10_1", - "MONITOR_WW4A0_4", - "MONITOR_WW2A3_1", - "MONITOR_SE2A2_4", - "MONITOR_BLOCK_OUTS_B2_2", - "MONITOR_VERT_SHORT_VAUXP0", - "MONITOR_WW4A1_1", - "MONITOR_SW2A3_2", - "MONITOR_LOGIC_OUTS_B21_4", - "MONITOR_SW4END1_0", - "MONITOR_SE4C3_4", - "MONITOR_LOGIC_OUTS_B14_2", - "MONITOR_EE4B3_4", - "MONITOR_WW4END0_3", - "MONITOR_EL1BEG0_4", - "MONITOR_LOGIC_OUTS_B8_0", - "MONITOR_LOGIC_OUTS_B23_0", - "MONITOR_EL1BEG3_4", - "MONITOR_IMUX18_3", - "MONITOR_IMUX34_4", - "MONITOR_IMUX17_4", - "MONITOR_NW4END2_3", - "MONITOR_EE4C3_3", - "MONITOR_EL1BEG2_0", - "MONITOR_BYP4_4", - "MONITOR_IMUX13_3", - "MONITOR_IMUX4_0", - "MONITOR_IMUX14_2", - "MONITOR_SW4END3_4", - "MONITOR_IMUX6_2", - "MONITOR_IMUX38_2", - "MONITOR_LOGIC_OUTS_B7_3", - "MONITOR_EE4A1_2", - "MONITOR_LOGIC_OUTS_B18_3", - "MONITOR_SE4BEG3_1", - "MONITOR_IMUX43_2", - "MONITOR_SW4A0_2", - "MONITOR_EE4A3_1", - "MONITOR_BYP0_4", - "MONITOR_VERT_SHORT_VAUXP10", - "MONITOR_NE2A3_4", - "MONITOR_LH3_3", - "MONITOR_IMUX47_1", - "MONITOR_IMUX22_4", - "MONITOR_EE4A2_4", - "MONITOR_WW4C0_0", - "MONITOR_IMUX42_4", - "MONITOR_IMUX47_4", - "MONITOR_IMUX13_2", - "MONITOR_NE4C1_2", - "MONITOR_IMUX32_0", - "MONITOR_NE2A0_3", - "MONITOR_BYP5_1", - "MONITOR_IMUX25_4", - "MONITOR_VERT_SHORT_VAUXP12", - "MONITOR_SE4C1_3", - "MONITOR_NE4BEG0_2", - "MONITOR_WW4END1_3", - "MONITOR_EE4BEG3_0", - "MONITOR_IMUX14_0", - "MONITOR_EE4C2_3", - "MONITOR_IMUX1_3", - "MONITOR_IMUX1_4", - "MONITOR_WR1END0_0", - "MONITOR_WW4END3_2", - "MONITOR_SW4A2_4", - "MONITOR_LOGIC_OUTS_B19_3", - "MONITOR_IMUX36_1", - "MONITOR_VERT_SHORT_VAUXP7", - "MONITOR_NE2A2_2", - "MONITOR_SW4A0_1", - "MONITOR_NE4BEG3_1", - "MONITOR_IMUX23_4", - "MONITOR_LOGIC_OUTS_B6_3", - "MONITOR_WW4A2_1", - "MONITOR_SW2A1_3", - "MONITOR_SW4END2_1", - "MONITOR_EE4C2_0", - "MONITOR_EE4BEG2_4", - "MONITOR_IMUX44_2", - "MONITOR_NE4C3_3", - "MONITOR_WW4END1_0", - "MONITOR_LOGIC_OUTS_B13_3", - "MONITOR_IMUX34_1", - "MONITOR_LOGIC_OUTS_B0_1", - "MONITOR_IMUX9_0", - "MONITOR_EE2BEG3_4", - "MONITOR_LH5_2", - "MONITOR_SW4END0_0", - "MONITOR_EL1BEG1_1", - "MONITOR_LOGIC_OUTS_B16_3", - "MONITOR_LH8_3", - "MONITOR_LH11_0", - "MONITOR_NW4A1_3", - "MONITOR_EE4B3_3", - "MONITOR_WL1END2_2", - "MONITOR_NW4END0_0", - "MONITOR_EE2BEG1_0", - "MONITOR_IMUX11_2", - "MONITOR_ER1BEG1_0", - "MONITOR_BYP2_3", - "MONITOR_FAN7_0", - "MONITOR_IMUX35_3", - "MONITOR_WW2END0_4", - "MONITOR_BYP6_3", - "MONITOR_EE4BEG2_2", - "MONITOR_LOGIC_OUTS_B4_4", - "MONITOR_BYP4_3", - "MONITOR_SE4BEG3_2", - "MONITOR_FAN0_3", - "MONITOR_LOGIC_OUTS_B4_1", - "MONITOR_BLOCK_OUTS_B1_0", - "MONITOR_EE2A2_0", - "MONITOR_IMUX9_2", - "MONITOR_IMUX33_2", - "MONITOR_NW4END3_0", - "MONITOR_CTRL0_4", - "MONITOR_EE4C0_4", - "MONITOR_CTRL1_0", - "MONITOR_IMUX5_4", - "MONITOR_IMUX26_2", - "MONITOR_LH9_1", - "MONITOR_IMUX40_0", - "MONITOR_IMUX11_4", - "MONITOR_SE2A1_2", - "MONITOR_ER1BEG3_0", - "MONITOR_EE2A2_1", - "MONITOR_IMUX46_2", - "MONITOR_EE4C3_0", - "MONITOR_FAN3_1", - "MONITOR_EE2A3_0", - "MONITOR_IMUX45_4", - "MONITOR_LH3_4", - "MONITOR_NE2A0_2", - "MONITOR_EE4B2_4", - "MONITOR_HORIZ_VAUXN8", - "MONITOR_EE4B2_0", - "MONITOR_BYP5_3", - "MONITOR_BYP7_4", - "MONITOR_EL1BEG2_2", - "MONITOR_WW4END1_2", - "MONITOR_SE4C1_0", - "MONITOR_IMUX25_1", - "MONITOR_NE2A1_1", - "MONITOR_NW4END1_2", - "MONITOR_SE2A2_1", - "MONITOR_SW2A1_0", - "MONITOR_SW4A1_1", - "MONITOR_SW4END0_3", - "MONITOR_EE4C1_2", - "MONITOR_EE4A3_2", - "MONITOR_EE4A0_4", - "MONITOR_LH5_0", - "MONITOR_SW4A3_4", - "MONITOR_SE4BEG3_0", - "MONITOR_FAN7_1", - "MONITOR_IMUX34_3", - "MONITOR_WW4B1_0", - "MONITOR_LOGIC_OUTS_B22_1", - "MONITOR_IMUX22_2", - "MONITOR_IMUX6_0", - "MONITOR_LOGIC_OUTS_B14_0", - "MONITOR_LH3_2", - "MONITOR_SW2A2_0", - "MONITOR_SE2A2_3", - "MONITOR_IMUX30_1", - "MONITOR_EE2A0_4", - "MONITOR_WW2A1_4", - "MONITOR_IMUX0_3", - "MONITOR_IMUX39_0", - "MONITOR_LOGIC_OUTS_B11_1", - "MONITOR_EE2A2_3", - "MONITOR_IMUX5_2", - "MONITOR_EE2BEG2_2", - "MONITOR_WW4B1_1", - "MONITOR_EE2A2_4", - "MONITOR_EL1BEG0_2", - "MONITOR_IMUX37_0", - "MONITOR_LOGIC_OUTS_B23_1", - "MONITOR_NE4C2_4", - "MONITOR_WL1END2_3", - "MONITOR_NE4C0_2", - "MONITOR_NW2A2_2", - "MONITOR_WW2A3_2", - "MONITOR_IMUX2_4", - "MONITOR_VERT_SHORT_VAUXN13", - "MONITOR_WL1END0_1", - "MONITOR_SW4A0_3", - "MONITOR_NW4END3_1", - "MONITOR_LOGIC_OUTS_B2_2", - "MONITOR_LOGIC_OUTS_B8_3", - "MONITOR_EE2BEG0_1", - "MONITOR_IMUX0_0", - "MONITOR_WW4A1_4", - "MONITOR_IMUX20_1", - "MONITOR_WW4C3_2", - "MONITOR_SW2A2_3", - "MONITOR_LH1_4", - "MONITOR_LH1_1", - "MONITOR_VERT_SHORT_VAUXP8", - "MONITOR_BYP6_4", - "MONITOR_IMUX46_0", - "MONITOR_FAN4_0", - "MONITOR_LOGIC_OUTS_B7_0", - "MONITOR_SW2A1_1", - "MONITOR_EL1BEG1_4", - "MONITOR_CLK1_4", - "MONITOR_FAN1_2", - "MONITOR_IMUX28_1", - "MONITOR_BYP4_0", - "MONITOR_LOGIC_OUTS_B20_0", - "MONITOR_LOGIC_OUTS_B0_0", - "MONITOR_WL1END0_0", - "MONITOR_WW2A0_2", - "MONITOR_IMUX0_2", - "MONITOR_VERT_SHORT_VAUXP14", - "MONITOR_LH9_3", - "MONITOR_IMUX19_1", - "MONITOR_FAN6_0", - "MONITOR_FAN3_4", - "MONITOR_IMUX38_3", - "MONITOR_NW2A0_0", - "MONITOR_IMUX25_3", - "MONITOR_LOGIC_OUTS_B1_4", - "MONITOR_BLOCK_OUTS_B0_1", - "MONITOR_SE4BEG1_4", - "MONITOR_IMUX46_4" - ], - "sites": [], "pips": { - "MONITOR_TOP.MONITOR_HORIZ_VAUXP0->MONITOR_VERT_SHORT_VAUXP0": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_SHORT_VAUXP0", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP0", - "is_pseudo": "0" - }, - "MONITOR_TOP.MONITOR_HORIZ_VAUXP12->MONITOR_VERT_SHORT_VAUXP12": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_SHORT_VAUXP12", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXP12", - "is_pseudo": "0" - }, - "MONITOR_TOP.MONITOR_HORIZ_VAUXN4->MONITOR_VERT_SHORT_VAUXN4": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_SHORT_VAUXN4", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN4", - "is_pseudo": "0" - }, "MONITOR_TOP.MONITOR_HORIZ_VAUXN12->MONITOR_VERT_SHORT_VAUXN12": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_SHORT_VAUXN12", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXN12", - "is_pseudo": "0" - }, - "MONITOR_TOP.MONITOR_HORIZ_VAUXN0->MONITOR_VERT_SHORT_VAUXN0": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_SHORT_VAUXN0", "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN0", - "is_pseudo": "0" - }, - "MONITOR_TOP.MONITOR_HORIZ_VAUXN8->MONITOR_VERT_SHORT_VAUXN8": { - "can_invert": "0", - "dst_wire": "MONITOR_VERT_SHORT_VAUXN8", - "is_directional": "1", - "src_wire": "MONITOR_HORIZ_VAUXN8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXN12" }, "MONITOR_TOP.MONITOR_HORIZ_VAUXP8->MONITOR_VERT_SHORT_VAUXP8": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_SHORT_VAUXP8", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXP8", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXP8" + }, + "MONITOR_TOP.MONITOR_HORIZ_VAUXP12->MONITOR_VERT_SHORT_VAUXP12": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXP12" + }, + "MONITOR_TOP.MONITOR_HORIZ_VAUXN4->MONITOR_VERT_SHORT_VAUXN4": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXN4" + }, + "MONITOR_TOP.MONITOR_HORIZ_VAUXN0->MONITOR_VERT_SHORT_VAUXN0": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXN0" + }, + "MONITOR_TOP.MONITOR_HORIZ_VAUXP0->MONITOR_VERT_SHORT_VAUXP0": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXP0" + }, + "MONITOR_TOP.MONITOR_HORIZ_VAUXN8->MONITOR_VERT_SHORT_VAUXN8": { + "can_invert": "0", + "src_wire": "MONITOR_HORIZ_VAUXN8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXN8" }, "MONITOR_TOP.MONITOR_HORIZ_VAUXP4->MONITOR_VERT_SHORT_VAUXP4": { "can_invert": "0", - "dst_wire": "MONITOR_VERT_SHORT_VAUXP4", - "is_directional": "1", "src_wire": "MONITOR_HORIZ_VAUXP4", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "MONITOR_VERT_SHORT_VAUXP4" } }, - "tile_type": "MONITOR_TOP" + "wires": [ + "MONITOR_SW4END3_2", + "MONITOR_WW4B1_3", + "MONITOR_IMUX4_1", + "MONITOR_EE4C3_2", + "MONITOR_FAN0_2", + "MONITOR_WW4END3_0", + "MONITOR_LH2_3", + "MONITOR_NE4C3_1", + "MONITOR_EE4B2_4", + "MONITOR_WL1END1_0", + "MONITOR_IMUX16_4", + "MONITOR_IMUX35_2", + "MONITOR_NE4C0_1", + "MONITOR_CLK0_0", + "MONITOR_IMUX42_3", + "MONITOR_NW2A1_0", + "MONITOR_NE4C1_3", + "MONITOR_SE4BEG3_2", + "MONITOR_IMUX24_0", + "MONITOR_IMUX4_2", + "MONITOR_LOGIC_OUTS_B0_1", + "MONITOR_NW4END2_0", + "MONITOR_IMUX37_3", + "MONITOR_LH6_2", + "MONITOR_LOGIC_OUTS_B0_3", + "MONITOR_WW4C1_3", + "MONITOR_NW4A3_3", + "MONITOR_HORIZ_VAUXP4", + "MONITOR_LOGIC_OUTS_B23_4", + "MONITOR_LOGIC_OUTS_B4_2", + "MONITOR_SW4A2_3", + "MONITOR_NW4A2_1", + "MONITOR_SE4BEG2_4", + "MONITOR_IMUX6_0", + "MONITOR_IMUX37_4", + "MONITOR_WW4END1_1", + "MONITOR_IMUX14_0", + "MONITOR_ER1BEG1_1", + "MONITOR_SW2A2_4", + "MONITOR_SW4A2_2", + "MONITOR_EE4C2_0", + "MONITOR_LH6_1", + "MONITOR_IMUX13_3", + "MONITOR_WR1END1_2", + "MONITOR_WW4B0_2", + "MONITOR_WW4B1_1", + "MONITOR_IMUX45_0", + "MONITOR_BYP6_3", + "MONITOR_IMUX25_4", + "MONITOR_WW4C2_3", + "MONITOR_LOGIC_OUTS_B17_3", + "MONITOR_IMUX7_3", + "MONITOR_LOGIC_OUTS_B16_0", + "MONITOR_EE4C3_4", + "MONITOR_IMUX4_0", + "MONITOR_NW2A0_4", + "MONITOR_CTRL0_1", + "MONITOR_IMUX1_3", + "MONITOR_WW4A0_0", + "MONITOR_WW4B1_4", + "MONITOR_IMUX14_3", + "MONITOR_EE4BEG1_0", + "MONITOR_IMUX41_2", + "MONITOR_IMUX27_0", + "MONITOR_LH10_2", + "MONITOR_IMUX12_3", + "MONITOR_SE4C1_3", + "MONITOR_IMUX12_2", + "MONITOR_LOGIC_OUTS_B22_1", + "MONITOR_FAN0_4", + "MONITOR_WL1END0_4", + "MONITOR_EE4C2_2", + "MONITOR_WW4B3_4", + "MONITOR_LOGIC_OUTS_B4_3", + "MONITOR_IMUX41_1", + "MONITOR_WR1END1_1", + "MONITOR_LH4_3", + "MONITOR_BLOCK_OUTS_B1_0", + "MONITOR_IMUX37_0", + "MONITOR_IMUX41_4", + "MONITOR_NE4BEG2_2", + "MONITOR_BYP5_4", + "MONITOR_WW4C3_1", + "MONITOR_IMUX11_3", + "MONITOR_IMUX9_1", + "MONITOR_SE4BEG0_4", + "MONITOR_IMUX20_1", + "MONITOR_EE2BEG0_3", + "MONITOR_IMUX19_3", + "MONITOR_IMUX8_1", + "MONITOR_SW2A3_2", + "MONITOR_LOGIC_OUTS_B15_3", + "MONITOR_EE4B1_4", + "MONITOR_WW2A0_3", + "MONITOR_IMUX32_1", + "MONITOR_EE4B1_0", + "MONITOR_WW2A1_4", + "MONITOR_BYP4_4", + "MONITOR_SW2A2_2", + "MONITOR_SE2A0_2", + "MONITOR_NE2A3_4", + "MONITOR_SW4A1_4", + "MONITOR_EE4A0_4", + "MONITOR_SE2A3_4", + "MONITOR_WR1END0_4", + "MONITOR_EL1BEG2_1", + "MONITOR_LOGIC_OUTS_B20_2", + "MONITOR_SE4C2_0", + "MONITOR_NW2A0_1", + "MONITOR_EE4B0_4", + "MONITOR_NE4BEG3_3", + "MONITOR_EE2A1_2", + "MONITOR_ER1BEG0_3", + "MONITOR_IMUX27_1", + "MONITOR_IMUX42_1", + "MONITOR_HORIZ_VAUXN12", + "MONITOR_WW4END2_4", + "MONITOR_IMUX13_0", + "MONITOR_EE4C3_0", + "MONITOR_IMUX18_4", + "MONITOR_SW4END0_3", + "MONITOR_WW4C3_3", + "MONITOR_WW4C2_2", + "MONITOR_WW4END2_2", + "MONITOR_WL1END3_0", + "MONITOR_WW2A3_1", + "MONITOR_NW2A2_0", + "MONITOR_LH7_3", + "MONITOR_EE2A0_2", + "MONITOR_WW4B3_2", + "MONITOR_LH10_0", + "MONITOR_EE4BEG1_4", + "MONITOR_IMUX43_0", + "MONITOR_IMUX39_3", + "MONITOR_EL1BEG2_0", + "MONITOR_IMUX3_0", + "MONITOR_HORIZ_VAUXP8", + "MONITOR_IMUX1_2", + "MONITOR_NE4C2_2", + "MONITOR_FAN1_2", + "MONITOR_BLOCK_OUTS_B0_2", + "MONITOR_IMUX29_1", + "MONITOR_FAN0_3", + "MONITOR_LOGIC_OUTS_B23_1", + "MONITOR_FAN1_0", + "MONITOR_LOGIC_OUTS_B20_0", + "MONITOR_SW2A1_2", + "MONITOR_WW2END3_4", + "MONITOR_LOGIC_OUTS_B1_2", + "MONITOR_WR1END1_4", + "MONITOR_WW4B1_2", + "MONITOR_LOGIC_OUTS_B22_2", + "MONITOR_IMUX17_0", + "MONITOR_WW2A2_0", + "MONITOR_EE4A3_2", + "MONITOR_IMUX31_1", + "MONITOR_NW4END3_3", + "MONITOR_IMUX34_2", + "MONITOR_BLOCK_OUTS_B3_0", + "MONITOR_WW4C0_1", + "MONITOR_SW4END2_2", + "MONITOR_VERT_SHORT_VAUXN2", + "MONITOR_LOGIC_OUTS_B9_4", + "MONITOR_EL1BEG0_0", + "MONITOR_WW2END3_0", + "MONITOR_SE4BEG3_4", + "MONITOR_IMUX20_3", + "MONITOR_EE4C0_2", + "MONITOR_WW2A3_0", + "MONITOR_IMUX12_4", + "MONITOR_IMUX25_2", + "MONITOR_EE4B0_2", + "MONITOR_EE4A3_4", + "MONITOR_FAN1_4", + "MONITOR_FAN0_1", + "MONITOR_NW4END2_2", + "MONITOR_EE4A0_1", + "MONITOR_LOGIC_OUTS_B7_2", + "MONITOR_IMUX21_1", + "MONITOR_SE4BEG1_4", + "MONITOR_EL1BEG0_2", + "MONITOR_BLOCK_OUTS_B3_4", + "MONITOR_NW4A2_4", + "MONITOR_LOGIC_OUTS_B18_3", + "MONITOR_IMUX23_4", + "MONITOR_SE2A2_4", + "MONITOR_EE4C3_3", + "MONITOR_HORIZ_VAUXN8", + "MONITOR_IMUX44_3", + "MONITOR_LOGIC_OUTS_B5_4", + "MONITOR_ER1BEG0_4", + "MONITOR_IMUX40_1", + "MONITOR_SE4BEG0_1", + "MONITOR_WW4A3_3", + "MONITOR_WW4END1_0", + "MONITOR_SE4C3_3", + "MONITOR_SW4END3_1", + "MONITOR_LOGIC_OUTS_B15_4", + "MONITOR_IMUX25_1", + "MONITOR_LOGIC_OUTS_B15_1", + "MONITOR_NE2A2_2", + "MONITOR_NE4C2_4", + "MONITOR_VERT_SHORT_VAUXP14", + "MONITOR_EE4BEG0_3", + "MONITOR_LH11_1", + "MONITOR_LH1_3", + "MONITOR_LOGIC_OUTS_B16_1", + "MONITOR_EE4A2_2", + "MONITOR_WW4A3_4", + "MONITOR_FAN5_4", + "MONITOR_FAN3_3", + "MONITOR_NW4A2_2", + "MONITOR_LOGIC_OUTS_B16_2", + "MONITOR_FAN5_3", + "MONITOR_EE4BEG0_4", + "MONITOR_BYP4_3", + "MONITOR_NW2A1_1", + "MONITOR_NE2A3_1", + "MONITOR_LH2_0", + "MONITOR_LH1_2", + "MONITOR_SE4BEG3_1", + "MONITOR_IMUX31_4", + "MONITOR_LH6_0", + "MONITOR_FAN0_0", + "MONITOR_EE2BEG2_4", + "MONITOR_WW4END0_2", + "MONITOR_LOGIC_OUTS_B0_4", + "MONITOR_BLOCK_OUTS_B0_1", + "MONITOR_SW4A2_0", + "MONITOR_NE4C3_4", + "MONITOR_LH12_4", + "MONITOR_CTRL1_2", + "MONITOR_EL1BEG1_4", + "MONITOR_LOGIC_OUTS_B13_1", + "MONITOR_BYP7_4", + "MONITOR_WW2END0_1", + "MONITOR_EE4BEG1_1", + "MONITOR_VERT_SHORT_VAUXN8", + "MONITOR_WW2A1_2", + "MONITOR_CLK1_1", + "MONITOR_NW2A2_1", + "MONITOR_SE2A3_2", + "MONITOR_SE4C3_0", + "MONITOR_NE2A1_2", + "MONITOR_WW4C3_0", + "MONITOR_NE4BEG2_0", + "MONITOR_LOGIC_OUTS_B10_2", + "MONITOR_NW4END1_3", + "MONITOR_WW4END1_3", + "MONITOR_WW4C0_4", + "MONITOR_LH4_1", + "MONITOR_IMUX5_3", + "MONITOR_SW2A3_4", + "MONITOR_EE4C0_0", + "MONITOR_LOGIC_OUTS_B11_2", + "MONITOR_IMUX19_4", + "MONITOR_NE4BEG2_4", + "MONITOR_IMUX20_4", + "MONITOR_BLOCK_OUTS_B1_3", + "MONITOR_LH10_1", + "MONITOR_IMUX3_4", + "MONITOR_FAN7_0", + "MONITOR_FAN5_2", + "MONITOR_IMUX18_0", + "MONITOR_EE4B1_3", + "MONITOR_EE4B0_1", + "MONITOR_LOGIC_OUTS_B5_0", + "MONITOR_NW2A1_4", + "MONITOR_NE4C0_3", + "MONITOR_LOGIC_OUTS_B21_2", + "MONITOR_SW4A1_0", + "MONITOR_WL1END3_4", + "MONITOR_CLK1_2", + "MONITOR_IMUX38_0", + "MONITOR_CTRL0_3", + "MONITOR_EE2A3_3", + "MONITOR_EE4BEG1_2", + "MONITOR_SE4BEG2_2", + "MONITOR_BYP7_2", + "MONITOR_IMUX29_0", + "MONITOR_CLK1_0", + "MONITOR_NE4BEG2_3", + "MONITOR_BLOCK_OUTS_B1_4", + "MONITOR_WL1END0_3", + "MONITOR_NE2A1_4", + "MONITOR_IMUX43_3", + "MONITOR_IMUX22_2", + "MONITOR_NW4END2_1", + "MONITOR_EL1BEG3_2", + "MONITOR_NW4A0_3", + "MONITOR_LH7_2", + "MONITOR_WW4A2_2", + "MONITOR_IMUX36_3", + "MONITOR_FAN7_4", + "MONITOR_LOGIC_OUTS_B3_2", + "MONITOR_WW2A1_0", + "MONITOR_LH4_2", + "MONITOR_BLOCK_OUTS_B0_4", + "MONITOR_LOGIC_OUTS_B5_3", + "MONITOR_SW4A3_1", + "MONITOR_IMUX24_3", + "MONITOR_IMUX3_1", + "MONITOR_ER1BEG2_2", + "MONITOR_IMUX5_0", + "MONITOR_NW4A1_2", + "MONITOR_IMUX43_2", + "MONITOR_IMUX34_4", + "MONITOR_IMUX0_4", + "MONITOR_LOGIC_OUTS_B5_2", + "MONITOR_SE4C0_3", + "MONITOR_EE4A1_1", + "MONITOR_IMUX34_3", + "MONITOR_LOGIC_OUTS_B9_2", + "MONITOR_NW4A3_0", + "MONITOR_LOGIC_OUTS_B10_4", + "MONITOR_IMUX21_2", + "MONITOR_IMUX2_2", + "MONITOR_IMUX36_0", + "MONITOR_IMUX40_2", + "MONITOR_IMUX35_0", + "MONITOR_LOGIC_OUTS_B9_3", + "MONITOR_EL1BEG0_4", + "MONITOR_VERT_SHORT_VAUXP15", + "MONITOR_SE2A0_1", + "MONITOR_WW2END3_2", + "MONITOR_VERT_SHORT_VAUXN13", + "MONITOR_CLK0_4", + "MONITOR_NE2A0_1", + "MONITOR_LH5_1", + "MONITOR_LH9_3", + "MONITOR_WL1END3_3", + "MONITOR_WW4A0_3", + "MONITOR_LOGIC_OUTS_B6_3", + "MONITOR_ER1BEG0_2", + "MONITOR_SW4A0_2", + "MONITOR_EL1BEG1_2", + "MONITOR_SW4END1_4", + "MONITOR_EL1BEG1_0", + "MONITOR_SW4END2_3", + "MONITOR_VERT_SHORT_VAUXP10", + "MONITOR_VERT_SHORT_VAUXP6", + "MONITOR_SE4C2_1", + "MONITOR_IMUX13_1", + "MONITOR_EE4BEG2_0", + "MONITOR_WW4A2_3", + "MONITOR_NE4C3_3", + "MONITOR_HORIZ_VAUXP0", + "MONITOR_IMUX31_3", + "MONITOR_LOGIC_OUTS_B10_0", + "MONITOR_EE4BEG3_3", + "MONITOR_WW4END0_1", + "MONITOR_LOGIC_OUTS_B14_3", + "MONITOR_LOGIC_OUTS_B23_0", + "MONITOR_NE4BEG0_2", + "MONITOR_EE2BEG3_4", + "MONITOR_BYP7_1", + "MONITOR_WW4A1_0", + "MONITOR_LH2_4", + "MONITOR_NE4BEG1_1", + "MONITOR_SW4END2_1", + "MONITOR_EL1BEG3_0", + "MONITOR_NE4C1_1", + "MONITOR_WW4A2_0", + "MONITOR_SW2A0_3", + "MONITOR_IMUX35_4", + "MONITOR_EL1BEG3_3", + "MONITOR_WW4END2_3", + "MONITOR_NW4END3_0", + "MONITOR_IMUX45_4", + "MONITOR_IMUX27_4", + "MONITOR_WW4A2_1", + "MONITOR_IMUX38_1", + "MONITOR_LH11_0", + "MONITOR_SE2A0_0", + "MONITOR_FAN7_1", + "MONITOR_SW4END3_0", + "MONITOR_EE4A2_3", + "MONITOR_BYP0_2", + "MONITOR_IMUX29_4", + "MONITOR_IMUX33_1", + "MONITOR_NW4END1_2", + "MONITOR_FAN6_0", + "MONITOR_LOGIC_OUTS_B5_1", + "MONITOR_WW4END2_0", + "MONITOR_NW2A1_2", + "MONITOR_BYP3_0", + "MONITOR_IMUX8_4", + "MONITOR_BYP0_4", + "MONITOR_BYP0_3", + "MONITOR_IMUX16_0", + "MONITOR_LOGIC_OUTS_B23_2", + "MONITOR_LOGIC_OUTS_B3_4", + "MONITOR_SE2A3_0", + "MONITOR_LH8_2", + "MONITOR_IMUX26_2", + "MONITOR_WR1END2_1", + "MONITOR_WW4A3_2", + "MONITOR_LH11_3", + "MONITOR_IMUX30_0", + "MONITOR_EE4B1_2", + "MONITOR_IMUX14_1", + "MONITOR_LOGIC_OUTS_B16_3", + "MONITOR_LOGIC_OUTS_B19_2", + "MONITOR_NE4BEG0_4", + "MONITOR_LH11_4", + "MONITOR_EE2BEG3_2", + "MONITOR_NW4A3_4", + "MONITOR_WW4B2_1", + "MONITOR_WL1END0_2", + "MONITOR_IMUX1_0", + "MONITOR_LOGIC_OUTS_B13_4", + "MONITOR_LOGIC_OUTS_B22_3", + "MONITOR_WW4END3_3", + "MONITOR_FAN7_2", + "MONITOR_IMUX17_2", + "MONITOR_IMUX11_2", + "MONITOR_WR1END3_2", + "MONITOR_SE4BEG1_1", + "MONITOR_IMUX32_4", + "MONITOR_EE4C2_1", + "MONITOR_SE4C1_1", + "MONITOR_LOGIC_OUTS_B1_3", + "MONITOR_IMUX33_2", + "MONITOR_IMUX46_2", + "MONITOR_FAN6_1", + "MONITOR_LOGIC_OUTS_B17_4", + "MONITOR_IMUX27_2", + "MONITOR_SW4A1_2", + "MONITOR_SW2A1_3", + "MONITOR_IMUX17_1", + "MONITOR_LOGIC_OUTS_B12_2", + "MONITOR_LH3_4", + "MONITOR_IMUX33_4", + "MONITOR_IMUX15_3", + "MONITOR_SW4END0_2", + "MONITOR_BLOCK_OUTS_B2_1", + "MONITOR_FAN2_4", + "MONITOR_LH1_1", + "MONITOR_SE4BEG3_3", + "MONITOR_FAN4_3", + "MONITOR_WW4A1_4", + "MONITOR_IMUX30_1", + "MONITOR_SW4END1_1", + "MONITOR_NW2A2_3", + "MONITOR_IMUX32_2", + "MONITOR_LH9_2", + "MONITOR_LH1_0", + "MONITOR_LOGIC_OUTS_B2_3", + "MONITOR_IMUX37_1", + "MONITOR_LOGIC_OUTS_B7_3", + "MONITOR_SE2A1_0", + "MONITOR_WW2END2_3", + "MONITOR_SW4END1_2", + "MONITOR_WW2A3_4", + "MONITOR_LOGIC_OUTS_B18_1", + "MONITOR_LOGIC_OUTS_B3_0", + "MONITOR_IMUX11_1", + "MONITOR_BYP6_0", + "MONITOR_NW4END3_4", + "MONITOR_WL1END1_3", + "MONITOR_LH3_0", + "MONITOR_WW4END1_4", + "MONITOR_LOGIC_OUTS_B17_2", + "MONITOR_LOGIC_OUTS_B23_3", + "MONITOR_BYP0_0", + "MONITOR_EE4BEG1_3", + "MONITOR_BYP7_0", + "MONITOR_LOGIC_OUTS_B10_3", + "MONITOR_SW4A2_4", + "MONITOR_CTRL1_4", + "MONITOR_EE4C2_4", + "MONITOR_LOGIC_OUTS_B14_0", + "MONITOR_IMUX3_3", + "MONITOR_IMUX20_2", + "MONITOR_SE4C1_2", + "MONITOR_IMUX39_4", + "MONITOR_SW2A3_0", + "MONITOR_BLOCK_OUTS_B2_4", + "MONITOR_SE4BEG0_0", + "MONITOR_WW4A0_1", + "MONITOR_IMUX2_3", + "MONITOR_LOGIC_OUTS_B8_0", + "MONITOR_ER1BEG3_1", + "MONITOR_WW4B0_0", + "MONITOR_EE4A3_1", + "MONITOR_EE4A1_3", + "MONITOR_SE4BEG2_0", + "MONITOR_IMUX44_2", + "MONITOR_LOGIC_OUTS_B6_4", + "MONITOR_IMUX6_2", + "MONITOR_EE2A2_4", + "MONITOR_EE4C3_1", + "MONITOR_WR1END0_0", + "MONITOR_EE4B0_0", + "MONITOR_BYP3_4", + "MONITOR_LOGIC_OUTS_B8_3", + "MONITOR_ER1BEG2_3", + "MONITOR_VERT_SHORT_VAUXN11", + "MONITOR_CLK0_2", + "MONITOR_NE4BEG0_1", + "MONITOR_LOGIC_OUTS_B19_0", + "MONITOR_EE4BEG3_4", + "MONITOR_IMUX10_0", + "MONITOR_IMUX32_0", + "MONITOR_FAN6_3", + "MONITOR_IMUX0_0", + "MONITOR_ER1BEG3_0", + "MONITOR_EE4C1_2", + "MONITOR_CLK1_4", + "MONITOR_EE2A0_1", + "MONITOR_EE2BEG2_2", + "MONITOR_NW2A3_1", + "MONITOR_BLOCK_OUTS_B3_1", + "MONITOR_WW4B0_3", + "MONITOR_IMUX28_1", + "MONITOR_NW4END2_3", + "MONITOR_WW4B0_4", + "MONITOR_EL1BEG0_3", + "MONITOR_LOGIC_OUTS_B2_2", + "MONITOR_IMUX35_3", + "MONITOR_WR1END0_3", + "MONITOR_BLOCK_OUTS_B0_0", + "MONITOR_NE4C1_4", + "MONITOR_WW4C0_3", + "MONITOR_ER1BEG2_0", + "MONITOR_BYP1_0", + "MONITOR_EE4A2_1", + "MONITOR_SE4C3_1", + "MONITOR_EE4A1_4", + "MONITOR_WW4C1_0", + "MONITOR_NE4BEG1_3", + "MONITOR_EE2A3_0", + "MONITOR_IMUX30_3", + "MONITOR_LH1_4", + "MONITOR_IMUX8_0", + "MONITOR_IMUX7_0", + "MONITOR_SW4END3_4", + "MONITOR_WW2A1_3", + "MONITOR_IMUX46_1", + "MONITOR_EE4B3_4", + "MONITOR_IMUX28_4", + "MONITOR_EE4B3_3", + "MONITOR_IMUX46_4", + "MONITOR_EE2BEG0_0", + "MONITOR_ER1BEG1_3", + "MONITOR_SW4END1_0", + "MONITOR_EE2A3_4", + "MONITOR_WW2A2_1", + "MONITOR_VERT_SHORT_VAUXP5", + "MONITOR_ER1BEG2_4", + "MONITOR_VERT_SHORT_VAUXP13", + "MONITOR_WW4C2_4", + "MONITOR_IMUX0_3", + "MONITOR_WR1END3_3", + "MONITOR_EE2A1_1", + "MONITOR_IMUX41_0", + "MONITOR_WW4B2_2", + "MONITOR_SE4C0_0", + "MONITOR_WW4END3_1", + "MONITOR_WW2END1_2", + "MONITOR_WW2END1_3", + "MONITOR_WW2END2_1", + "MONITOR_NW2A3_3", + "MONITOR_IMUX38_4", + "MONITOR_BYP2_3", + "MONITOR_NW4A1_0", + "MONITOR_LOGIC_OUTS_B9_0", + "MONITOR_LH8_3", + "MONITOR_SE2A1_2", + "MONITOR_ER1BEG1_0", + "MONITOR_EE4A2_4", + "MONITOR_IMUX46_3", + "MONITOR_NE4BEG3_0", + "MONITOR_IMUX21_0", + "MONITOR_IMUX13_4", + "MONITOR_SE2A1_1", + "MONITOR_EE4C1_1", + "MONITOR_SE2A0_3", + "MONITOR_BLOCK_OUTS_B2_3", + "MONITOR_BYP4_0", + "MONITOR_EL1BEG1_3", + "MONITOR_WL1END2_2", + "MONITOR_VERT_SHORT_VAUXP2", + "MONITOR_IMUX8_3", + "MONITOR_LOGIC_OUTS_B2_0", + "MONITOR_WR1END1_3", + "MONITOR_EE2A3_1", + "MONITOR_SW4END1_3", + "MONITOR_IMUX20_0", + "MONITOR_LH12_1", + "MONITOR_BYP2_0", + "MONITOR_IMUX23_2", + "MONITOR_LOGIC_OUTS_B14_2", + "MONITOR_WW2END1_0", + "MONITOR_IMUX36_1", + "MONITOR_BYP2_2", + "MONITOR_SE4C3_4", + "MONITOR_IMUX42_4", + "MONITOR_IMUX43_1", + "MONITOR_WL1END1_2", + "MONITOR_NW4A3_2", + "MONITOR_CTRL1_1", + "MONITOR_EE4B0_3", + "MONITOR_WW4A1_1", + "MONITOR_WW2END1_4", + "MONITOR_FAN2_2", + "MONITOR_IMUX32_3", + "MONITOR_WR1END3_4", + "MONITOR_WL1END2_0", + "MONITOR_IMUX40_0", + "MONITOR_SE4BEG2_3", + "MONITOR_LH10_3", + "MONITOR_BYP1_1", + "MONITOR_LOGIC_OUTS_B22_0", + "MONITOR_EL1BEG2_4", + "MONITOR_SE4C2_4", + "MONITOR_WW2END2_2", + "MONITOR_SW4A1_1", + "MONITOR_NW4A0_2", + "MONITOR_WW4B2_3", + "MONITOR_LOGIC_OUTS_B12_1", + "MONITOR_EL1BEG2_3", + "MONITOR_SW4END2_4", + "MONITOR_IMUX35_1", + "MONITOR_NE2A0_0", + "MONITOR_FAN3_4", + "MONITOR_EE4B2_1", + "MONITOR_LOGIC_OUTS_B19_3", + "MONITOR_BYP5_2", + "MONITOR_LH4_0", + "MONITOR_LOGIC_OUTS_B15_2", + "MONITOR_IMUX39_0", + "MONITOR_LOGIC_OUTS_B21_0", + "MONITOR_WW4B3_1", + "MONITOR_FAN2_0", + "MONITOR_IMUX33_0", + "MONITOR_EE4A0_0", + "MONITOR_NW2A3_2", + "MONITOR_IMUX34_1", + "MONITOR_CLK1_3", + "MONITOR_IMUX22_1", + "MONITOR_WW2END2_4", + "MONITOR_NE4C3_0", + "MONITOR_NW4END1_4", + "MONITOR_IMUX5_4", + "MONITOR_IMUX9_0", + "MONITOR_WW4END2_1", + "MONITOR_CLK0_3", + "MONITOR_VERT_SHORT_VAUXN1", + "MONITOR_WW4C1_4", + "MONITOR_SW4END2_0", + "MONITOR_VERT_SHORT_VAUXN7", + "MONITOR_WW4END1_2", + "MONITOR_SW2A1_4", + "MONITOR_LH6_3", + "MONITOR_LOGIC_OUTS_B18_2", + "MONITOR_IMUX17_3", + "MONITOR_EE4A0_2", + "MONITOR_LH10_4", + "MONITOR_LOGIC_OUTS_B4_4", + "MONITOR_WR1END0_1", + "MONITOR_BLOCK_OUTS_B3_2", + "MONITOR_EE2BEG1_4", + "MONITOR_SW4END0_0", + "MONITOR_LOGIC_OUTS_B16_4", + "MONITOR_FAN2_3", + "MONITOR_NE2A0_2", + "MONITOR_SE4BEG1_2", + "MONITOR_EE4C0_3", + "MONITOR_IMUX2_0", + "MONITOR_IMUX21_3", + "MONITOR_FAN6_4", + "MONITOR_LOGIC_OUTS_B2_1", + "MONITOR_LH7_0", + "MONITOR_NE4C1_2", + "MONITOR_EE4C0_4", + "MONITOR_WL1END2_1", + "MONITOR_NW2A2_4", + "MONITOR_NW4A2_0", + "MONITOR_WR1END3_0", + "MONITOR_WW2A3_2", + "MONITOR_IMUX47_3", + "MONITOR_IMUX5_2", + "MONITOR_VERT_SHORT_VAUXN3", + "MONITOR_WW2A3_3", + "MONITOR_WL1END3_2", + "MONITOR_EE4B3_2", + "MONITOR_BYP3_2", + "MONITOR_VERT_SHORT_VAUXP3", + "MONITOR_SW2A2_0", + "MONITOR_EE4A2_0", + "MONITOR_FAN1_1", + "MONITOR_WW4B2_4", + "MONITOR_LOGIC_OUTS_B6_2", + "MONITOR_NE4BEG3_4", + "MONITOR_EE4BEG2_3", + "MONITOR_IMUX18_1", + "MONITOR_LH9_0", + "MONITOR_FAN7_3", + "MONITOR_IMUX47_4", + "MONITOR_SE4C0_4", + "MONITOR_IMUX46_0", + "MONITOR_EE4BEG0_1", + "MONITOR_LH8_1", + "MONITOR_EE4C1_0", + "MONITOR_IMUX29_2", + "MONITOR_NW4A0_1", + "MONITOR_WW4A1_2", + "MONITOR_IMUX10_4", + "MONITOR_EE2A0_3", + "MONITOR_LOGIC_OUTS_B3_3", + "MONITOR_IMUX8_2", + "MONITOR_SE4BEG3_0", + "MONITOR_WW4A1_3", + "MONITOR_HORIZ_VAUXN0", + "MONITOR_CTRL1_3", + "MONITOR_IMUX5_1", + "MONITOR_IMUX13_2", + "MONITOR_NE2A2_3", + "MONITOR_IMUX26_4", + "MONITOR_IMUX19_1", + "MONITOR_LH12_0", + "MONITOR_EE2A1_0", + "MONITOR_SW2A2_3", + "MONITOR_IMUX25_3", + "MONITOR_IMUX26_1", + "MONITOR_IMUX28_2", + "MONITOR_IMUX2_1", + "MONITOR_IMUX22_0", + "MONITOR_IMUX39_2", + "MONITOR_ER1BEG0_0", + "MONITOR_EE2A0_4", + "MONITOR_NW4END1_1", + "MONITOR_WR1END3_1", + "MONITOR_NW4END0_1", + "MONITOR_LOGIC_OUTS_B18_4", + "MONITOR_NE4C0_4", + "MONITOR_LOGIC_OUTS_B1_1", + "MONITOR_NE2A0_4", + "MONITOR_SW2A0_1", + "MONITOR_SE4C2_3", + "MONITOR_EE4B1_1", + "MONITOR_IMUX2_4", + "MONITOR_WW4A3_0", + "MONITOR_BYP0_1", + "MONITOR_VERT_SHORT_VAUXP7", + "MONITOR_IMUX28_3", + "MONITOR_NE4C2_1", + "MONITOR_LH2_1", + "MONITOR_IMUX25_0", + "MONITOR_NW2A2_2", + "MONITOR_BYP6_4", + "MONITOR_IMUX19_2", + "MONITOR_WR1END0_2", + "MONITOR_IMUX45_3", + "MONITOR_LOGIC_OUTS_B12_3", + "MONITOR_SW4END3_3", + "MONITOR_SW4A0_3", + "MONITOR_LH6_4", + "MONITOR_SW4A0_4", + "MONITOR_EE4A3_3", + "MONITOR_NE2A1_0", + "MONITOR_WW4B1_0", + "MONITOR_EE2BEG0_4", + "MONITOR_BYP1_3", + "MONITOR_SW4A1_3", + "MONITOR_NE4BEG1_4", + "MONITOR_IMUX37_2", + "MONITOR_LH3_2", + "MONITOR_IMUX36_2", + "MONITOR_NW4END3_1", + "MONITOR_WW2A0_1", + "MONITOR_NW4A1_4", + "MONITOR_IMUX42_0", + "MONITOR_WW4C3_4", + "MONITOR_NW4END0_4", + "MONITOR_SW2A0_0", + "MONITOR_WW2A1_1", + "MONITOR_IMUX7_1", + "MONITOR_NE4BEG2_1", + "MONITOR_IMUX1_1", + "MONITOR_IMUX10_1", + "MONITOR_WW2A2_3", + "MONITOR_SW4A3_4", + "MONITOR_WR1END2_2", + "MONITOR_NE2A1_1", + "MONITOR_IMUX30_2", + "MONITOR_EE2BEG1_2", + "MONITOR_ER1BEG1_2", + "MONITOR_SW2A2_1", + "MONITOR_EE4BEG2_1", + "MONITOR_EE2A2_2", + "MONITOR_WW2END0_0", + "MONITOR_BLOCK_OUTS_B2_2", + "MONITOR_SE4C2_2", + "MONITOR_LOGIC_OUTS_B21_3", + "MONITOR_IMUX12_1", + "MONITOR_WW4B3_3", + "MONITOR_LOGIC_OUTS_B11_0", + "MONITOR_WW4END0_0", + "MONITOR_LOGIC_OUTS_B12_4", + "MONITOR_WR1END2_3", + "MONITOR_BYP5_0", + "MONITOR_IMUX18_2", + "MONITOR_IMUX9_3", + "MONITOR_BYP7_3", + "MONITOR_IMUX42_2", + "MONITOR_VERT_SHORT_VAUXP4", + "MONITOR_VERT_SHORT_VAUXP9", + "MONITOR_LOGIC_OUTS_B3_1", + "MONITOR_CLK0_1", + "MONITOR_LOGIC_OUTS_B4_1", + "MONITOR_LOGIC_OUTS_B11_1", + "MONITOR_LOGIC_OUTS_B6_1", + "MONITOR_IMUX11_0", + "MONITOR_WL1END2_4", + "MONITOR_SE4C1_0", + "MONITOR_FAN3_1", + "MONITOR_WW4END3_2", + "MONITOR_VERT_SHORT_VAUXN14", + "MONITOR_EE2A2_1", + "MONITOR_CTRL0_4", + "MONITOR_VERT_SHORT_VAUXN4", + "MONITOR_VERT_SHORT_VAUXP0", + "MONITOR_EE4BEG3_0", + "MONITOR_IMUX36_4", + "MONITOR_IMUX12_0", + "MONITOR_WR1END2_4", + "MONITOR_SE4C0_1", + "MONITOR_NE4BEG1_2", + "MONITOR_IMUX23_3", + "MONITOR_IMUX44_4", + "MONITOR_IMUX26_3", + "MONITOR_LOGIC_OUTS_B20_3", + "MONITOR_IMUX23_0", + "MONITOR_EE2A1_4", + "MONITOR_NW4A1_3", + "MONITOR_NW4END0_3", + "MONITOR_IMUX1_4", + "MONITOR_SE4BEG0_3", + "MONITOR_IMUX15_0", + "MONITOR_IMUX44_0", + "MONITOR_SE4C0_2", + "MONITOR_LOGIC_OUTS_B14_1", + "MONITOR_IMUX27_3", + "MONITOR_LOGIC_OUTS_B2_4", + "MONITOR_LOGIC_OUTS_B11_4", + "MONITOR_WW4END3_4", + "MONITOR_LH3_1", + "MONITOR_LOGIC_OUTS_B15_0", + "MONITOR_EE2BEG2_3", + "MONITOR_IMUX14_4", + "MONITOR_SE4C1_4", + "MONITOR_EE4B2_0", + "MONITOR_WL1END0_0", + "MONITOR_LOGIC_OUTS_B7_1", + "MONITOR_SE4BEG1_3", + "MONITOR_IMUX0_1", + "MONITOR_IMUX7_4", + "MONITOR_WW2A0_4", + "MONITOR_IMUX24_4", + "MONITOR_SW4A3_3", + "MONITOR_IMUX6_4", + "MONITOR_EL1BEG2_2", + "MONITOR_WW4C1_2", + "MONITOR_EE2BEG1_1", + "MONITOR_EE2BEG2_0", + "MONITOR_FAN4_2", + "MONITOR_CTRL0_0", + "MONITOR_WW4B3_0", + "MONITOR_EE4C0_1", + "MONITOR_IMUX22_4", + "MONITOR_FAN4_4", + "MONITOR_VERT_SHORT_VAUXN12", + "MONITOR_NW4A0_0", + "MONITOR_WW4C2_1", + "MONITOR_IMUX29_3", + "MONITOR_SE2A1_3", + "MONITOR_BYP4_2", + "MONITOR_IMUX23_1", + "MONITOR_LOGIC_OUTS_B11_3", + "MONITOR_LH8_4", + "MONITOR_NE4C3_2", + "MONITOR_LH7_1", + "MONITOR_VERT_SHORT_VAUXN9", + "MONITOR_IMUX15_4", + "MONITOR_WL1END1_4", + "MONITOR_NE2A2_1", + "MONITOR_NE4BEG0_3", + "MONITOR_LOGIC_OUTS_B8_2", + "MONITOR_EE4A1_0", + "MONITOR_IMUX47_1", + "MONITOR_NE4C1_0", + "MONITOR_EE4B3_0", + "MONITOR_WW4B2_0", + "MONITOR_ER1BEG0_1", + "MONITOR_LH5_0", + "MONITOR_ER1BEG2_1", + "MONITOR_LOGIC_OUTS_B1_4", + "MONITOR_WW4A0_4", + "MONITOR_IMUX19_0", + "MONITOR_LH12_2", + "MONITOR_WW2END0_3", + "MONITOR_WW4A0_2", + "MONITOR_SE2A2_2", + "MONITOR_IMUX4_3", + "MONITOR_SW4A3_2", + "MONITOR_NW4A3_1", + "MONITOR_SW4A2_1", + "MONITOR_NE4C0_0", + "MONITOR_BYP1_4", + "MONITOR_WL1END1_1", + "MONITOR_IMUX9_4", + "MONITOR_EE2BEG1_3", + "MONITOR_IMUX18_3", + "MONITOR_IMUX15_2", + "MONITOR_WW2END3_1", + "MONITOR_FAN5_0", + "MONITOR_IMUX9_2", + "MONITOR_LOGIC_OUTS_B7_4", + "MONITOR_IMUX0_2", + "MONITOR_SW4A0_1", + "MONITOR_SW4END0_4", + "MONITOR_BYP1_2", + "MONITOR_LH12_3", + "MONITOR_EE2A1_3", + "MONITOR_IMUX28_0", + "MONITOR_CTRL0_2", + "MONITOR_EE2BEG0_2", + "MONITOR_WW2A2_4", + "MONITOR_LH5_4", + "MONITOR_EE4BEG2_2", + "MONITOR_LOGIC_OUTS_B6_0", + "MONITOR_LOGIC_OUTS_B0_2", + "MONITOR_NW2A0_2", + "MONITOR_EE4BEG2_4", + "MONITOR_EE4B2_3", + "MONITOR_IMUX14_2", + "MONITOR_SE2A3_3", + "MONITOR_LOGIC_OUTS_B8_1", + "MONITOR_EE2A2_0", + "MONITOR_IMUX16_2", + "MONITOR_EL1BEG3_4", + "MONITOR_IMUX24_1", + "MONITOR_LOGIC_OUTS_B8_4", + "MONITOR_WW4C1_1", + "MONITOR_WW4C0_0", + "MONITOR_BYP2_1", + "MONITOR_LOGIC_OUTS_B7_0", + "MONITOR_VERT_SHORT_VAUXN6", + "MONITOR_BYP6_2", + "MONITOR_LOGIC_OUTS_B12_0", + "MONITOR_NE4BEG1_0", + "MONITOR_EE4BEG0_2", + "MONITOR_EE2BEG2_1", + "MONITOR_IMUX6_1", + "MONITOR_EL1BEG3_1", + "MONITOR_NE2A2_4", + "MONITOR_NE4C2_0", + "MONITOR_FAN3_2", + "MONITOR_WW2END1_1", + "MONITOR_BLOCK_OUTS_B0_3", + "MONITOR_NW4END3_2", + "MONITOR_IMUX26_0", + "MONITOR_WW2END3_3", + "MONITOR_NW4END2_4", + "MONITOR_EE4B2_2", + "MONITOR_WW2END0_4", + "MONITOR_BYP3_3", + "MONITOR_EE2BEG3_1", + "MONITOR_LH4_4", + "MONITOR_SE2A3_1", + "MONITOR_NE2A3_2", + "MONITOR_IMUX3_2", + "MONITOR_EE4C2_3", + "MONITOR_LOGIC_OUTS_B0_0", + "MONITOR_IMUX22_3", + "MONITOR_SW4A0_0", + "MONITOR_WW2A0_0", + "MONITOR_SW4END0_1", + "MONITOR_EE2BEG1_0", + "MONITOR_CTRL1_0", + "MONITOR_LH8_0", + "MONITOR_LOGIC_OUTS_B9_1", + "MONITOR_EE4BEG3_2", + "MONITOR_LOGIC_OUTS_B18_0", + "MONITOR_VERT_SHORT_VAUXP8", + "MONITOR_WW4END0_3", + "MONITOR_NW2A0_3", + "MONITOR_FAN6_2", + "MONITOR_IMUX4_4", + "MONITOR_LH5_3", + "MONITOR_VERT_SHORT_VAUXN15", + "MONITOR_BYP4_1", + "MONITOR_VERT_SHORT_VAUXP1", + "MONITOR_WW2A0_2", + "MONITOR_LOGIC_OUTS_B10_1", + "MONITOR_IMUX40_3", + "MONITOR_IMUX39_1", + "MONITOR_BYP5_3", + "MONITOR_IMUX11_4", + "MONITOR_NE4C2_3", + "MONITOR_NW4A1_1", + "MONITOR_NW4END0_2", + "MONITOR_SW2A0_2", + "MONITOR_NE2A2_0", + "MONITOR_EE2BEG3_3", + "MONITOR_LOGIC_OUTS_B19_1", + "MONITOR_HORIZ_VAUXN4", + "MONITOR_EE4A1_2", + "MONITOR_IMUX16_1", + "MONITOR_LOGIC_OUTS_B13_0", + "MONITOR_SE2A2_3", + "MONITOR_NE2A3_0", + "MONITOR_WW4END0_4", + "MONITOR_SE2A2_0", + "MONITOR_IMUX6_3", + "MONITOR_WW4C2_0", + "MONITOR_SE2A0_4", + "MONITOR_LOGIC_OUTS_B20_1", + "MONITOR_IMUX31_2", + "MONITOR_LOGIC_OUTS_B20_4", + "MONITOR_EE2A3_2", + "MONITOR_SE4BEG1_0", + "MONITOR_ER1BEG3_3", + "MONITOR_EE2A0_0", + "MONITOR_BLOCK_OUTS_B1_2", + "MONITOR_LOGIC_OUTS_B22_4", + "MONITOR_NW2A0_0", + "MONITOR_ER1BEG3_4", + "MONITOR_NW2A3_0", + "MONITOR_NE4BEG0_0", + "MONITOR_EL1BEG1_1", + "MONITOR_FAN5_1", + "MONITOR_BYP2_4", + "MONITOR_NE2A1_3", + "MONITOR_IMUX45_1", + "MONITOR_IMUX38_3", + "MONITOR_BYP3_1", + "MONITOR_IMUX10_2", + "MONITOR_FAN4_0", + "MONITOR_LH9_1", + "MONITOR_EL1BEG0_1", + "MONITOR_SW2A1_0", + "MONITOR_WL1END3_1", + "MONITOR_EE4A0_3", + "MONITOR_LOGIC_OUTS_B21_4", + "MONITOR_FAN3_0", + "MONITOR_IMUX7_2", + "MONITOR_WW4C0_2", + "MONITOR_ER1BEG3_2", + "MONITOR_FAN1_3", + "MONITOR_LH7_4", + "MONITOR_LOGIC_OUTS_B4_0", + "MONITOR_LH11_2", + "MONITOR_BLOCK_OUTS_B1_1", + "MONITOR_IMUX34_0", + "MONITOR_IMUX15_1", + "MONITOR_EE4BEG3_1", + "MONITOR_WW4A2_4", + "MONITOR_VERT_SHORT_VAUXN5", + "MONITOR_SE2A1_4", + "MONITOR_VERT_SHORT_VAUXP11", + "MONITOR_NE2A0_3", + "MONITOR_LOGIC_OUTS_B21_1", + "MONITOR_EE4C1_3", + "MONITOR_IMUX47_2", + "MONITOR_IMUX10_3", + "MONITOR_WW4A3_1", + "MONITOR_WL1END2_3", + "MONITOR_NW4A0_4", + "MONITOR_LH5_2", + "MONITOR_NW2A3_4", + "MONITOR_NW4END1_0", + "MONITOR_LOGIC_OUTS_B17_0", + "MONITOR_VERT_SHORT_VAUXN10", + "MONITOR_IMUX24_2", + "MONITOR_NE4BEG3_1", + "MONITOR_FAN4_1", + "MONITOR_BLOCK_OUTS_B3_3", + "MONITOR_VERT_SHORT_VAUXP12", + "MONITOR_SW4A3_0", + "MONITOR_HORIZ_VAUXP12", + "MONITOR_ER1BEG1_4", + "MONITOR_IMUX47_0", + "MONITOR_EE4A3_0", + "MONITOR_WW4C3_2", + "MONITOR_SW2A3_1", + "MONITOR_SW2A3_3", + "MONITOR_NW2A1_3", + "MONITOR_WW2A2_2", + "MONITOR_IMUX43_4", + "MONITOR_IMUX45_2", + "MONITOR_IMUX17_4", + "MONITOR_NW4END0_0", + "MONITOR_WL1END0_1", + "MONITOR_WR1END2_0", + "MONITOR_SE4BEG0_2", + "MONITOR_SE4C3_2", + "MONITOR_WW2END2_0", + "MONITOR_NE2A3_3", + "MONITOR_EE2A2_3", + "MONITOR_EE2BEG0_1", + "MONITOR_IMUX40_4", + "MONITOR_IMUX31_0", + "MONITOR_EE4BEG0_0", + "MONITOR_FAN2_1", + "MONITOR_SE2A2_1", + "MONITOR_LH2_2", + "MONITOR_IMUX41_3", + "MONITOR_IMUX16_3", + "MONITOR_BLOCK_OUTS_B2_0", + "MONITOR_LH3_3", + "MONITOR_WW2END0_2", + "MONITOR_NW4A2_3", + "MONITOR_IMUX21_4", + "MONITOR_WR1END1_0", + "MONITOR_NE4C0_2", + "MONITOR_SW2A0_4", + "MONITOR_EE4B3_1", + "MONITOR_LOGIC_OUTS_B19_4", + "MONITOR_BYP5_1", + "MONITOR_LOGIC_OUTS_B17_1", + "MONITOR_EE2BEG3_0", + "MONITOR_IMUX44_1", + "MONITOR_IMUX30_4", + "MONITOR_SW2A1_1", + "MONITOR_EE4C1_4", + "MONITOR_LOGIC_OUTS_B14_4", + "MONITOR_LOGIC_OUTS_B1_0", + "MONITOR_WW4B0_1", + "MONITOR_SE4BEG2_1", + "MONITOR_IMUX38_2", + "MONITOR_NE4BEG3_2", + "MONITOR_LOGIC_OUTS_B13_3", + "MONITOR_BYP6_1", + "MONITOR_VERT_SHORT_VAUXN0", + "MONITOR_LOGIC_OUTS_B13_2", + "MONITOR_IMUX33_3", + "MONITOR_LH9_4" + ], + "tile_type": "MONITOR_TOP", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_NULL.json b/artix7/tile_type_NULL.json index 3f30fd0..e9356f2 100644 --- a/artix7/tile_type_NULL.json +++ b/artix7/tile_type_NULL.json @@ -1,8 +1,8 @@ { + "pips": {}, "wires": [ "DUMMYFOO" ], - "sites": [], - "pips": {}, - "tile_type": "NULL" + "tile_type": "NULL", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_PCIE_BOT.json b/artix7/tile_type_PCIE_BOT.json index 52e1f6b..47fd667 100644 --- a/artix7/tile_type_PCIE_BOT.json +++ b/artix7/tile_type_PCIE_BOT.json @@ -1,23028 +1,23028 @@ { - "wires": [ - "PCIE_BLOCK_OUTS_B2_R_8", - "PCIE_TRNRDLLPDATA57", - "PCIE_PIPETX3CHARISK1", - "PCIE_EE4C1_4", - "PCIE_FAN4_R_9", - "PCIE_LOGIC_OUTS_B7_L_6", - "PCIE_EE2BEG3_3", - "PCIE_TRNRBARHIT5", - "PCIE_TRNTD95", - "PCIE_CFGERRAERHEADERLOG14", - "PCIE_TRNTD106", - "PCIE_CFGVCTCVCMAP3", - "PCIE_IMUX9_R_1", - "PCIE_IMUX17_R_3", - "PCIE_TRNTEOF", - "PCIE_EE2BEG3_6", - "PCIE_LOGIC_OUTS_B0_R_1", - "PCIE_CFGMSGDATA6", - "PCIE_SW2A3_11", - "PCIE_IMUX37_L_9", - "PCIE_CFGERRAERHEADERLOG63", - "PCIE_IMUX38_R_11", - "PCIE_IMUX32_R_0", - "PCIE_MIMRXRDATA54", - "PCIE_IMUX30_R_4", - "PCIE_CFGPMFORCESTATEENN", - "PCIE_WW4A3_14", - "PCIE_PIPETX5DATA14", - "PCIE_CFGMSGDATA15", - "PCIE_WL1END0_5", - "PCIE_IMUX21_R_3", - "PCIE_LH4_6", - "PCIE_LOGIC_OUTS_B20_R_16", - "PCIE_LOGIC_OUTS_B0_L_18", - "PCIE_SW2A3_13", - "PCIE_DBGVECB6", - "PCIE_LOGIC_OUTS_B13_R_17", - "PCIE_MIMTXWDATA57", - "PCIE_IMUX26_R_2", - "PCIE_EE4BEG1_9", - "PCIE_WW4A1_0", - "PCIE_PL2RECOVERY", - "PCIE_PIPETX1CHARISK0", - "PCIE_IMUX31_R_15", - "PCIE_EE4C0_13", - "PCIE_IMUX29_L_10", - "PCIE_CFGDEVCONTROL2ARIFORWARDEN", - "PCIE_IMUX42_L_13", - "PCIE_EE2A1_17", - "PCIE_IMUX14_R_16", - "PCIE_TRNRD58", - "PCIE_SW4A1_11", - "PCIE_BLOCK_OUTS_B0_L_8", - "PCIE_IMUX39_L_8", - "PCIE_WR1END0_8", - "PCIE_MIMRXRADDR6", - "PCIE_WW4C1_2", - "PCIE_LOGIC_OUTS_B6_L_12", - "PCIE_CFGSUBSYSVENDID15", - "PCIE_IMUX42_R_16", - "PCIE_DBGVECA27", - "PCIE_IMUX42_L_9", - "PCIE_MIMTXWDATA45", - "PCIE_LOGIC_OUTS_B16_L_0", - "PCIE_TRNTDLLPDATA12", - "PCIE_LOGIC_OUTS_B4_R_6", - "PCIE_MIMTXWDATA36", - "PCIE_CFGINTERRUPTDO3", - "PCIE_DBGVECB23", - "PCIE_WL1END2_13", - "PCIE_BLOCK_OUTS_B1_R_17", - "PCIE_LH8_15", - "PCIE_SE4C1_13", - "PCIE_EE4A0_14", - "PCIE_WW4A1_18", - "PCIE_NE4BEG1_9", - "PCIE_EE4A0_15", - "PCIE_NW2A2_14", - "PCIE_CFGERRAERHEADERLOG106", - "PCIE_NE2A1_3", - "PCIE_LOGIC_OUTS_B11_R_8", - "PCIE_LOGIC_OUTS_B7_R_1", - "PCIE_TRNTD89", - "PCIE_LOGIC_OUTS_B16_R_3", - "PCIE_BLOCK_OUTS_B3_R_13", - "PCIE_CFGERRPOISONEDN", - "PCIE_TL2ERRHDR56", - "PCIE_PIPETX7ELECIDLE", - "PCIE_IMUX46_L_8", - "PCIE_NW4END1_16", - "PCIE_NW4END0_15", - "PCIE_IMUX37_R_14", - "PCIE_IMUX39_L_6", - "PCIE_NE4BEG2_4", - "PCIE_EE2BEG0_10", - "PCIE_LOGIC_OUTS_B0_L_11", - "PCIE_BYP5_R_18", - "PCIE_NW4END1_17", - "PCIE_CFGMGMTDO11", - "PCIE_LH2_12", - "PCIE_BYP4_R_5", - "PCIE_MIMTXWDATA8", - "PCIE_WW4A0_4", - "PCIE_IMUX4_L_0", - "PCIE_IMUX36_R_10", - "PCIE_IMUX9_L_15", - "PCIE_IMUX37_R_8", - "PCIE_LOGIC_OUTS_B10_L_10", - "PCIE_LOGIC_OUTS_B12_L_14", - "PCIE_IMUX3_L_11", - "PCIE_CFGSUBSYSID12", - "PCIE_TRNFCSEL1", - "PCIE_CFGDSN35", - "PCIE_IMUX47_R_16", - "PCIE_MIMTXWDATA14", - "PCIE_WR1END2_15", - "PCIE_IMUX31_L_9", - "PCIE_CFGMSGDATA11", - "PCIE_BYP1_R_0", - "PCIE_TRNRD48", - "PCIE_LH6_2", - "PCIE_CFGCOMMANDINTERRUPTDISABLE", - "PCIE_IMUX21_L_16", - "PCIE_NW2A0_1", - "PCIE_FAN6_R_11", - "PCIE_PIPERX3DATA12", - "PCIE_IMUX15_R_15", - "PCIE_NE4C1_5", - "PCIE_CFGMGMTDO13", - "PCIE_IMUX27_L_0", - "PCIE_IMUX41_R_1", - "PCIE_NW4END2_7", - "PCIE_IMUX20_R_12", - "PCIE_CFGMGMTDO25", - "PCIE_WL1END2_5", - "PCIE_CFGPORTNUMBER2", - "PCIE_FAN2_L_6", - "PCIE_EE4B1_5", - "PCIE_PIPERX6DATA1", - "PCIE_LOGIC_OUTS_B4_L_10", - "PCIE_FAN0_L_15", - "PCIE_CFGMGMTDO16", - "PCIE_FAN2_L_15", - "PCIE_BLOCK_OUTS_B1_L_7", - "PCIE_NW4END1_14", - "PCIE_CFGMGMTDO17", - "PCIE_FAN0_L_11", - "PCIE_LOGIC_OUTS_B1_R_10", - "PCIE_CFGPMTURNOFFOKN", - "PCIE_TRNTD22", - "PCIE_PIPERX5DATA12", - "PCIE_IMUX23_L_6", - "PCIE_PIPERX1STATUS1", - "PCIE_IMUX39_L_0", - "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", - "PCIE_CFGERRAERHEADERLOG16", - "PCIE_NE4BEG2_12", - "PCIE_IMUX35_L_6", - "PCIE_DBGSCLRD", - "PCIE_SW2A3_1", - "PCIE_EE2A1_10", - "PCIE_IMUX23_L_15", - "PCIE_CFGSUBSYSVENDID8", - "PCIE_SE4C2_4", - "PCIE_LOGIC_OUTS_B1_R_17", - "PCIE_LOGIC_OUTS_B22_L_17", - "PCIE_TRNFCCPLD0", - "PCIE_PIPERX3DATA5", - "PCIE_IMUX8_L_4", - "PCIE_IMUX15_R_0", - "PCIE_LOGIC_OUTS_B17_L_3", - "PCIE_EE4A3_12", - "PCIE_TRNTD122", - "PCIE_TRNRD94", - "PCIE_WL1END0_7", - "PCIE_CFGMSGDATA14", - "PCIE_LH9_12", - "PCIE_NE4BEG2_8", - "PCIE_LOGIC_OUTS_B4_L_2", - "PCIE_PIPETX4DATA12", - "PCIE_LOGIC_OUTS_B14_L_12", - "PCIE_LOGIC_OUTS_B12_R_2", - "PCIE_IMUX33_R_16", - "PCIE_LOGIC_OUTS_B15_R_2", - "PCIE_LOGIC_OUTS_B0_R_7", - "PCIE_PLDIRECTEDLINKSPEED", - "PCIE_CFGMGMTDI7", - "PCIE_IMUX40_R_6", - "PCIE_NE4C3_13", - "PCIE_IMUX12_R_19", - "PCIE_EL1BEG0_4", - "PCIE_CFGINTERRUPTDI3", - "PCIE_MIMRXWDATA1", - "PCIE_BYP5_R_14", - "PCIE_IMUX13_R_18", - "PCIE_EE4BEG1_4", - "PCIE_CFGDEVID13", - "PCIE_NE2A0_13", - "PCIE_CFGERRAERHEADERLOG6", - "PCIE_TRNRD83", - "PCIE_ER1BEG1_4", - "PCIE_LOGIC_OUTS_B6_R_0", - "PCIE_DRPCLK", - "PCIE_CTRL1_L_18", - "PCIE_IMUX12_R_12", - "PCIE_IMUX25_L_8", - "PCIE_LH11_15", - "PCIE_IMUX7_R_17", - "PCIE_LOGIC_OUTS_B3_L_4", - "PCIE_SE2A0_17", - "PCIE_TRNFCCPLD4", - "PCIE_LOGIC_OUTS_B13_L_12", - "PCIE_BYP4_L_12", - "PCIE_SW4END3_16", - "PCIE_TRNRDLLPDATA62", - "PCIE_WW4B0_14", - "PCIE_EL1BEG2_7", - "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", - "PCIE_MONITOR_P_3", - "PCIE_LOGIC_OUTS_B0_L_6", - "PCIE_TRNFCCPLD10", - "PCIE_LH7_13", - "PCIE_WW2END1_13", - "PCIE_IMUX35_R_1", - "PCIE_LOGIC_OUTS_B8_L_10", - "PCIE_LOGIC_OUTS_B2_L_7", - "PCIE_EE4BEG0_12", - "PCIE_IMUX20_R_9", - "PCIE_IMUX12_R_16", - "PCIE_SW4A2_9", - "PCIE_IMUX3_L_10", - "PCIE_BYP6_L_17", - "PCIE_IMUX44_R_16", - "PCIE_LH8_19", - "PCIE_PIPERX4ELECIDLE", - "PCIE_EE4BEG1_0", - "PCIE_IMUX32_L_13", - "PCIE_SW2A0_3", - "PCIE_IMUX22_L_5", - "PCIE_TRNTD79", - "PCIE_CLK1_R_1", - "PCIE_SW4END1_10", - "PCIE_BLOCK_OUTS_B0_L_2", - "PCIE_IMUX44_R_14", - "PCIE_LOGIC_OUTS_B15_R_11", - "PCIE_LOGIC_OUTS_B11_R_3", - "PCIE_IMUX45_R_13", - "PCIE_IMUX30_L_9", - "PCIE_IMUX44_L_7", - "PCIE_TRNRD67", - "PCIE_IMUX32_R_10", - "PCIE_LOGIC_OUTS_B16_L_16", - "PCIE_IMUX29_L_13", - "PCIE_NE2A2_10", - "PCIE_IMUX42_L_12", - "PCIE_SE4BEG3_2", - "PCIE_EE2BEG1_3", - "PCIE_MIMRXWADDR5", - "PCIE_ER1BEG1_13", - "PCIE_NW2A3_18", - "PCIE_TRNTD54", - "PCIE_EE4B1_15", - "PCIE_BYP7_R_15", - "PCIE_SW2A0_0", - "PCIE_PIPETX7POWERDOWN1", - "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", - "PCIE_FAN4_R_18", - "PCIE_IMUX15_R_6", - "PCIE_EL1BEG0_12", - "PCIE_CTRL1_L_2", - "PCIE_IMUX26_R_0", - "PCIE_SE4C3_11", - "PCIE_IMUX18_L_11", - "PCIE_IMUX19_R_7", - "PCIE_DBGVECA25", - "PCIE_SE2A1_19", - "PCIE_NE4C1_6", - "PCIE_MIMRXWDATA57", - "PCIE_NE4BEG2_11", - "PCIE_LOGIC_OUTS_B16_L_18", - "PCIE_IMUX27_L_2", - "PCIE_LOGIC_OUTS_B11_L_19", - "PCIE_MONITOR_N_18", - "PCIE_EE4A0_17", - "PCIE_CTRL0_L_15", - "PCIE_BYP5_L_10", - "PCIE_WW4B3_18", - "PCIE_IMUX19_L_4", - "PCIE_EE2A3_10", - "PCIE_WW4B2_12", - "PCIE_IMUX24_R_17", - "PCIE_PIPERX4STATUS2", - "PCIE_IMUX27_R_5", - "PCIE_MIMTXRDATA52", - "PCIE_CFGERRURN", - "PCIE_WW4A0_19", - "PCIE_CTRL0_R_7", - "PCIE_SE4BEG1_14", - "PCIE_LL2TLPRCV", - "PCIE_CFGERRAERHEADERLOG42", - "PCIE_EDTCHANNELSIN5", - "PCIE_MIMRXWDATA16", - "PCIE_WW4END0_15", - "PCIE_MIMRXRDATA10", - "PCIE_TRNTD82", - "PCIE_WW4A1_5", - "PCIE_IMUX0_R_19", - "PCIE_IMUX41_R_5", - "PCIE_TRNRD87", - "PCIE_XILUNCONNOUT31", - "PCIE_IMUX17_L_4", - "PCIE_TRNTD113", - "PCIE_NW4END3_19", - "PCIE_LH7_17", - "PCIE_MIMTXWDATA16", - "PCIE_LOGIC_OUTS_B5_R_16", - "PCIE_SW4A1_12", - "PCIE_LOGIC_OUTS_B7_L_19", - "PCIE_IMUX35_R_12", - "PCIE_SW4END2_8", - "PCIE_IMUX16_R_16", - "PCIE_MIMTXWADDR5", - "PCIE_LOGIC_OUTS_B18_R_5", - "PCIE_MIMTXWADDR9", - "PCIE_CFGDEVID15", - "PCIE_TL2ERRHDR36", - "PCIE_MONITOR_N_15", - "PCIE_LH9_5", - "PCIE_WW4END3_13", - "PCIE_IMUX29_R_0", - "PCIE_SW4A3_2", - "PCIE_TRNRD41", - "PCIE_EE4B2_15", - "PCIE_LOGIC_OUTS_B16_R_8", - "PCIE_LOGIC_OUTS_B16_L_5", - "PCIE_IMUX29_R_9", - "PCIE_SE4BEG3_8", - "PCIE_IMUX41_L_5", - "PCIE_BYP4_L_0", - "PCIE_LL2SENDASREQL1", - "PCIE_WW4END2_14", - "PCIE_EE4C3_0", - "PCIE_SE4BEG2_3", - "PCIE_IMUX4_R_9", - "PCIE_MIMTXRDATA47", - "PCIE_BYP1_R_15", - "PCIE_PLDBGVEC1", - "PCIE_BYP7_L_5", - "PCIE_NW2A2_15", - "PCIE_IMUX20_R_15", - "PCIE_CFGMGMTDI12", - "PCIE_SW2A3_18", - "PCIE_SE2A3_9", - "PCIE_SW4A1_15", - "PCIE_IMUX0_R_4", - "PCIE_CLK1_L_6", - "PCIE_LOGIC_OUTS_B11_R_4", - "PCIE_LOGIC_OUTS_B16_R_10", - "PCIE_CFGMGMTDWADDR4", - "PCIE_CFGERRTLPCPLHEADER38", - "PCIE_BYP2_R_3", - "PCIE_IMUX5_R_17", - "PCIE_LOGIC_OUTS_B1_L_5", - "PCIE_WW4A3_7", - "PCIE_LH8_11", - "PCIE_SW2A0_14", - "PCIE_NE2A1_10", - "PCIE_IMUX15_L_6", - "PCIE_FAN7_R_4", - "PCIE_PIPETX0DATA10", - "PCIE_NW4A3_10", - "PCIE_CTRL1_L_0", - "PCIE_TRNRD13", - "PCIE_DRPADDR8", - "PCIE_LOGIC_OUTS_B1_R_2", - "PCIE_IMUX32_L_0", - "PCIE_CFGDSN10", - "PCIE_NW4A0_9", - "PCIE_IMUX45_L_2", - "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", - "PCIE_WW4END1_17", - "PCIE_MIMTXRDATA54", - "PCIE_WL1END2_15", - "PCIE_BYP5_L_9", - "PCIE_BLOCK_OUTS_B3_R_2", - "PCIE_FAN7_L_17", - "PCIE_CFGERRTLPCPLHEADER10", - "PCIE_IMUX12_R_15", - "PCIE_WW4C1_5", - "PCIE_NE4C2_16", - "PCIE_IMUX41_L_3", - "PCIE_EE2A0_4", - "PCIE_LOGIC_OUTS_B10_L_17", - "PCIE_WL1END2_17", - "PCIE_ER1BEG2_14", - "PCIE_IMUX15_R_4", - "PCIE_NW2A0_11", - "PCIE_CFGERRTLPCPLHEADER21", - "PCIE_SE4C2_17", - "PCIE_BYP5_L_1", - "PCIE_LOGIC_OUTS_B12_R_8", - "PCIE_ER1BEG0_15", - "PCIE_IMUX19_L_14", - "PCIE_ER1BEG3_3", - "PCIE_IMUX31_R_16", - "PCIE_PIPERX4DATA11", - "PCIE_BYP5_R_6", - "PCIE_DBGVECB59", - "PCIE_DRPADDR1", - "PCIE_MIMTXRDATA5", - "PCIE_CLK0_R_18", - "PCIE_PIPERX6DATA7", - "PCIE_BYP1_L_4", - "PCIE_PMVENABLEN", - "PCIE_CFGINTERRUPTMMENABLE0", - "PCIE_SW4END0_15", - "PCIE_EE4C0_8", - "PCIE_WW2A3_10", - "PCIE_BLOCK_OUTS_B2_L_11", - "PCIE_IMUX7_L_5", - "PCIE_WW2END0_5", - "PCIE_IMUX38_R_6", - "PCIE_MIMRXWDATA26", - "PCIE_WW4C2_10", - "PCIE_LOGIC_OUTS_B21_L_15", - "PCIE_IMUX29_R_18", - "PCIE_LOGIC_OUTS_B1_L_12", - "PCIE_IMUX17_L_3", - "PCIE_IMUX7_L_12", - "PCIE_IMUX36_L_9", - "PCIE_WW4END1_7", - "PCIE_LOGIC_OUTS_B11_R_0", - "PCIE_EE4A1_1", - "PCIE_BYP5_R_7", - "PCIE_IMUX39_R_8", - "PCIE_CFGMGMTDO20", - "PCIE_PIPERX4DATA6", - "PCIE_IMUX2_R_14", - "PCIE_DBGVECA51", - "PCIE_MIMRXRDATA13", - "PCIE_LOGIC_OUTS_B21_R_4", - "PCIE_WL1END3_13", - "PCIE_NW4A1_6", - "PCIE_EE4C3_11", - "PCIE_LH6_8", - "PCIE_EL1BEG3_17", - "PCIE_IMUX45_R_7", - "PCIE_LOGIC_OUTS_B7_R_14", - "PCIE_IMUX25_R_4", - "PCIE_PIPETX4DATA10", - "PCIE_NE4BEG2_2", - "PCIE_FAN2_R_5", - "PCIE_WW2A3_8", - "PCIE_MONITOR_P_11", - "PCIE_BYP4_R_14", - "PCIE_NW4END1_2", - "PCIE_LOGIC_OUTS_B1_L_8", - "PCIE_TRNRD72", - "PCIE_LOGIC_OUTS_B8_L_6", - "PCIE_WW2END2_14", - "PCIE_IMUX35_L_10", - "PCIE_NW2A3_7", - "PCIE_SE2A2_18", - "PCIE_ER1BEG2_19", - "PCIE_LOGIC_OUTS_B4_R_17", - "PCIE_NE4C2_2", - "PCIE_IMUX44_L_11", - "PCIE_SW4A3_19", - "PCIE_IMUX24_L_2", - "PCIE_PIPETX7CHARISK1", - "PCIE_WW4C3_14", - "PCIE_WR1END3_7", - "PCIE_ER1BEG0_18", - "PCIE_SW4A0_3", - "PCIE_EE4A2_14", - "PCIE_LOGIC_OUTS_B7_L_15", - "PCIE_IMUX45_L_0", - "PCIE_NE2A1_13", - "PCIE_LOGIC_OUTS_B19_R_2", - "PCIE_IMUX17_L_7", - "PCIE_IMUX47_R_19", - "PCIE_CFGERRAERHEADERLOG35", - "PCIE_CFGERRAERHEADERLOG27", - "PCIE_IMUX44_R_13", - "PCIE_IMUX21_L_7", - "PCIE_NW4A3_8", - "PCIE_TRNTDLLPDATA0", - "PCIE_NW4A2_10", - "PCIE_SE4BEG3_12", - "PCIE_IMUX20_L_4", - "PCIE_SE2A3_4", - "PCIE_LOGIC_OUTS_B19_R_19", - "PCIE_WW4C1_4", - "PCIE_DBGVECA14", - "PCIE_TRNTD66", - "PCIE_PIPERX6VALID", - "PCIE_BYP0_L_0", - "PCIE_PIPETX3DATA5", - "PCIE_WW2END2_5", - "PCIE_LOGIC_OUTS_B22_L_12", - "PCIE_SW4A1_0", - "PCIE_LOGIC_OUTS_B18_L_5", - "PCIE_LH6_5", - "PCIE_IMUX18_R_4", - "PCIE_LOGIC_OUTS_B13_R_1", - "PCIE_WW4C1_11", - "PCIE_PIPERX5CHARISK1", - "PCIE_PIPERX3CHARISK1", - "PCIE_CFGDSDEVICENUMBER3", - "PCIE_MIMRXWDATA11", - "PCIE_LH12_7", - "PCIE_WW4C2_14", - "PCIE_PIPETX1DATA10", - "PCIE_DBGVECB40", - "PCIE_LOGIC_OUTS_B16_R_7", - "PCIE_LOGIC_OUTS_B12_L_1", - "PCIE_CFGFORCECOMMONCLOCKOFF", - "PCIE_TRNFCPD1", - "PCIE_IMUX11_R_6", - "PCIE_BYP1_R_7", - "PCIE_IMUX45_L_7", - "PCIE_LH11_3", - "PCIE_MIMTXRADDR10", - "PCIE_IMUX47_R_1", - "PCIE_PIPETX7DATA6", - "PCIE_WL1END0_11", - "PCIE_LH8_10", - "PCIE_CFGSUBSYSVENDID1", - "PCIE_IMUX24_R_16", - "PCIE_IMUX45_L_3", - "PCIE_MIMRXRDATA0", - "PCIE_IMUX9_R_18", - "PCIE_PIPETX6ELECIDLE", - "PCIE_WW4A0_7", - "PCIE_PIPETX1DATA9", - "PCIE_NW2A2_6", - "PCIE_SE4C3_3", - "PCIE_FAN3_R_9", - "PCIE_LH12_18", - "PCIE_SW4END1_16", - "PCIE_MIMRXWDATA42", - "PCIE_LOGIC_OUTS_B20_R_9", - "PCIE_WW4A2_13", - "PCIE_PIPETX4DATA1", - "PCIE_PIPERX5DATA4", - "PCIE_EE2BEG2_16", - "PCIE_CLK0_R_1", - "PCIE_IMUX5_L_10", - "PCIE_DBGVECA36", - "PCIE_IMUX44_R_2", - "PCIE_LOGIC_OUTS_B13_L_7", - "PCIE_FAN4_R_14", - "PCIE_LOGIC_OUTS_B8_R_18", - "PCIE_LOGIC_OUTS_B12_L_5", - "PCIE_PL2DIRECTEDLSTATE3", - "PCIE_LOGIC_OUTS_B4_L_17", - "PCIE_LH9_16", - "PCIE_IMUX25_R_17", - "PCIE_EE4BEG0_3", - "PCIE_LOGIC_OUTS_B13_R_13", - "PCIE_IMUX22_R_13", - "PCIE_WW4C0_4", - "PCIE_WW4B2_7", - "PCIE_MIMRXRDATA45", - "PCIE_IMUX33_L_4", - "PCIE_TRNRD84", - "PCIE_LH7_15", - "PCIE_LOGIC_OUTS_B6_R_18", - "PCIE_IMUX11_L_4", - "PCIE_FAN3_R_5", - "PCIE_NW2A3_9", - "PCIE_PIPETX3DATA2", - "PCIE_TRNRDLLPDATA24", - "PCIE_CFGERRAERHEADERLOG28", - "PCIE_LH1_17", - "PCIE_PIPETX1DATA1", - "PCIE_SE4BEG1_19", - "PCIE_IMUX6_R_12", - "PCIE_LOGIC_OUTS_B6_R_13", - "PCIE_IMUX40_L_13", - "PCIE_CTRL0_L_13", - "PCIE_NE2A3_10", - "PCIE_IMUX41_L_10", - "PCIE_IMUX5_L_12", - "PCIE_MIMTXWDATA63", - "PCIE_TRNRD64", - "PCIE_BLOCK_OUTS_B3_L_11", - "PCIE_IMUX12_R_1", - "PCIE_CLK0_R_15", - "PCIE_IMUX37_L_19", - "PCIE_MIMRXRDATA33", - "PCIE_BYP6_L_9", - "PCIE_NW4END1_3", - "PCIE_TL2ERRHDR61", - "PCIE_IMUX22_L_14", - "PCIE_LOGIC_OUTS_B1_L_19", - "PCIE_MIMRXWDATA14", - "PCIE_IMUX27_L_1", - "PCIE_WW2A3_17", - "PCIE_IMUX19_R_19", - "PCIE_BYP7_R_5", - "PCIE_NE4BEG0_9", - "PCIE_FAN4_R_17", - "PCIE_MIMRXRDATA35", - "PCIE_EE2A1_5", - "PCIE_CLK0_L_9", - "PCIE_BLOCK_OUTS_B2_L_7", - "PCIE_WW4C2_19", - "PCIE_LOGIC_OUTS_B14_R_0", - "PCIE_DBGVECA39", - "PCIE_FAN7_R_13", - "PCIE_PIPETX3DATA0", - "PCIE_IMUX22_R_12", - "PCIE_EE4B0_0", - "PCIE_IMUX22_R_0", - "PCIE_IMUX11_L_15", - "PCIE_IMUX13_L_5", - "PCIE_FAN4_R_2", - "PCIE_IMUX5_L_7", - "PCIE_BYP7_L_19", - "PCIE_NE4C2_11", - "PCIE_FAN1_L_5", - "PCIE_CFGERRAERHEADERLOG103", - "PCIE_LOGIC_OUTS_B2_L_6", - "PCIE_SE4BEG0_4", - "PCIE_IMUX44_L_16", - "PCIE_XILUNCONNOUT29", - "PCIE_DBGVECB32", - "PCIE_IMUX34_L_3", - "PCIE_LOGIC_OUTS_B9_R_10", - "PCIE_MIMRXREN", - "PCIE_TRNTD58", - "PCIE_IMUX2_R_4", - "PCIE_NW4END0_12", - "PCIE_MIMRXRDATA5", - "PCIE_IMUX0_R_6", - "PCIE_IMUX34_L_9", - "PCIE_NE4C0_16", - "PCIE_IMUX43_R_9", - "PCIE_CFGINTERRUPTDO1", - "PCIE_TRNTD91", - "PCIE_LOGIC_OUTS_B21_L_16", - "PCIE_LOGIC_OUTS_B10_R_1", - "PCIE_IMUX35_R_2", - "PCIE_PIPETX2ELECIDLE", - "PCIE_IMUX9_L_0", - "PCIE_IMUX26_L_17", - "PCIE_IMUX38_L_13", - "PCIE_DBGVECB8", - "PCIE_EE2BEG1_8", - "PCIE_SE4BEG1_6", - "PCIE_LOGIC_OUTS_B17_L_6", - "PCIE_EE2BEG3_14", - "PCIE_WW2A2_6", - "PCIE_IMUX17_R_13", - "PCIE_LOGIC_OUTS_B10_R_18", - "PCIE_CFGMGMTDI14", - "PCIE_PIPERX6DATA15", - "PCIE_EE4BEG3_14", - "PCIE_EE2BEG1_0", - "PCIE_EE2A2_13", - "PCIE_LOGIC_OUTS_B9_R_18", - "PCIE_CLK1_L_9", - "PCIE_WW4A3_10", - "PCIE_IMUX21_L_10", - "PCIE_SW2A0_7", - "PCIE_SW4END3_17", - "PCIE_LOGIC_OUTS_B7_R_19", - "PCIE_BYP6_R_14", - "PCIE_TRNFCPH0", - "PCIE_MIMTXRDATA15", - "PCIE_IMUX43_R_11", - "PCIE_TL2ERRHDR20", - "PCIE_IMUX5_R_15", - "PCIE_IMUX27_R_2", - "PCIE_IMUX19_L_12", - "PCIE_NW2A0_6", - "PCIE_WW2END1_5", - "PCIE_CFGDEVID1", - "PCIE_BYP3_R_6", - "PCIE_LOGIC_OUTS_B8_R_10", - "PCIE_LOGIC_OUTS_B11_L_14", - "PCIE_PIPERX2PHYSTATUS", - "PCIE_TRNRD98", - "PCIE_CFGERRTLPCPLHEADER41", - "PCIE_EE4A0_0", - "PCIE_LOGIC_OUTS_B21_L_7", - "PCIE_IMUX10_L_4", - "PCIE_FAN0_L_9", - "PCIE_TRNTDSTRDY1", - "PCIE_PIPERX7ELECIDLE", - "PCIE_DBGVECB34", - "PCIE_CFGREVID1", - "PCIE_IMUX24_L_0", - "PCIE_TRNRD26", - "PCIE_CFGDSN33", - "PCIE_LOGIC_OUTS_B18_R_9", - "PCIE_LOGIC_OUTS_B4_R_13", - "PCIE_LOGIC_OUTS_B0_R_3", - "PCIE_NE4C3_10", - "PCIE_PIPETX2DATA12", - "PCIE_PIPERX1DATA9", - "PCIE_MIMTXRDATA23", - "PCIE_NE4BEG1_5", - "PCIE_TRNFCCPLD3", - "PCIE_IMUX29_R_15", - "PCIE_MIMRXRDATA66", - "PCIE_LOGIC_OUTS_B16_R_15", - "PCIE_FAN1_L_12", - "PCIE_NW4END3_9", - "PCIE_WW2A0_19", - "PCIE_CFGERRAERHEADERLOG56", - "PCIE_ER1BEG3_0", - "PCIE_IMUX30_R_7", - "PCIE_PIPERX0CHARISK0", - "PCIE_CFGTRANSACTIONADDR0", - "PCIE_SE2A0_11", - "PCIE_ER1BEG0_13", - "PCIE_WW4A3_15", - "PCIE_EE2BEG2_4", - "PCIE_PIPERX7DATA3", - "PCIE_IMUX12_R_6", - "PCIE_CLK1_R_19", - "PCIE_LOGIC_OUTS_B19_L_15", - "PCIE_TRNTD26", - "PCIE_LOGIC_OUTS_B16_L_14", - "PCIE_BYP4_L_6", - "PCIE_FAN3_L_12", - "PCIE_IMUX36_L_3", - "PCIE_MONITOR_P_8", - "PCIE_SW2A0_13", - "PCIE_LOGIC_OUTS_B15_R_3", - "PCIE_PIPERX4DATA5", - "PCIE_NE4C2_15", - "PCIE_TRNFCNPH7", - "PCIE_NE4BEG0_0", - "PCIE_TL2ERRHDR59", - "PCIE_NW4A3_2", - "PCIE_IMUX17_L_2", - "PCIE_IMUX28_R_11", - "PCIE_IMUX12_L_10", - "PCIE_EE4A0_13", - "PCIE_CFGPMCSRPMEEN", - "PCIE_EE4BEG1_10", - "PCIE_WR1END2_8", - "PCIE_SE4BEG1_18", - "PCIE_CTRL1_L_7", - "PCIE_FUNCLVLRSTN", - "PCIE_LOGIC_OUTS_B22_L_13", - "PCIE_EE2A1_7", - "PCIE_PIPERX7DATA5", - "PCIE_IMUX19_R_1", - "PCIE_MIMTXRDATA59", - "PCIE_IMUX18_R_16", - "PCIE_SE4BEG1_8", - "PCIE_WW4C3_3", - "PCIE_FAN2_R_14", - "PCIE_SE4C0_8", - "PCIE_LOGIC_OUTS_B11_R_18", - "PCIE_LOGIC_OUTS_B16_L_19", - "PCIE_SE2A1_1", - "PCIE_DBGVECB3", - "PCIE_EE2A3_7", - "PCIE_SE4C1_18", - "PCIE_LOGIC_OUTS_B19_R_6", - "PCIE_IMUX18_L_0", - "PCIE_NE4C2_19", - "PCIE_IMUX41_L_4", - "PCIE_IMUX11_L_13", - "PCIE_SE4BEG3_18", - "PCIE_LOGIC_OUTS_B18_L_18", - "PCIE_PIPERX1CHARISK0", - "PCIE_IMUX14_L_1", - "PCIE_DBGVECB21", - "PCIE_BYP0_L_11", - "PCIE_EE2BEG1_16", - "PCIE_TRNRDLLPDATA53", - "PCIE_CFGVCTCVCMAP5", - "PCIE_LH11_13", - "PCIE_EE4BEG1_19", - "PCIE_LOGIC_OUTS_B9_R_16", - "PCIE_MIMTXRDATA58", - "PCIE_IMUX35_R_8", - "PCIE_BYP3_R_5", - "PCIE_CLK1_L_0", - "PCIE_WW4C3_8", - "PCIE_IMUX7_R_10", - "PCIE_IMUX0_R_5", - "PCIE_EE4B1_12", - "PCIE_DBGVECB49", - "PCIE_DRPDI5", - "PCIE_LOGIC_OUTS_B23_R_3", - "PCIE_TRNTD14", - "PCIE_BLOCK_OUTS_B0_L_6", - "PCIE_PLDIRECTEDLTSSMNEW0", - "PCIE_PIPERX0CHANISALIGNED", - "PCIE_BYP7_L_17", - "PCIE_LH3_18", - "PCIE_WW4END2_7", - "PCIE_IMUX26_R_4", - "PCIE_CLK0_R_13", - "PCIE_PIPERX0DATA14", - "PCIE_BYP3_L_12", - "PCIE_IMUX29_L_14", - "PCIE_IMUX7_L_1", - "PCIE_NE2A2_7", - "PCIE_TRNFCNPD8", - "PCIE_LOGIC_OUTS_B15_R_13", - "PCIE_EE2BEG1_7", - "PCIE_LH11_19", - "PCIE_LOGIC_OUTS_B3_L_17", - "PCIE_TRNRD78", - "PCIE_BLOCK_OUTS_B1_L_6", - "PCIE_PIPETX0POWERDOWN0", - "PCIE_IMUX40_R_9", - "PCIE_PIPETX0DATA12", - "PCIE_CFGERRTLPCPLHEADER46", - "PCIE_EE2BEG3_10", - "PCIE_CFGDSN34", - "PCIE_IMUX44_L_0", - "PCIE_IMUX27_R_18", - "PCIE_LOGIC_OUTS_B11_R_13", - "PCIE_TRNTD52", - "PCIE_IMUX15_R_11", - "PCIE_IMUX29_R_10", - "PCIE_FAN7_R_0", - "PCIE_EE4BEG0_18", - "PCIE_SE4C1_17", - "PCIE_MIMRXRDATA56", - "PCIE_LOGIC_OUTS_B3_L_9", - "PCIE_LOGIC_OUTS_B1_L_10", - "PCIE_SW4A3_3", - "PCIE_IMUX26_R_7", - "PCIE_WW2A1_3", - "PCIE_TRNFCNPD5", - "PCIE_SW4END3_12", - "PCIE_IMUX0_L_16", - "PCIE_EE2BEG1_18", - "PCIE_TRNRD6", - "PCIE_IMUX9_L_7", - "PCIE_IMUX27_R_19", - "PCIE_FAN3_R_19", - "PCIE_LOGIC_OUTS_B11_L_17", - "PCIE_WW4C1_13", - "PCIE_BYP7_L_11", - "PCIE_LOGIC_OUTS_B5_R_7", - "PCIE_NW4END1_5", - "PCIE_BYP2_R_7", - "PCIE_MIMTXRDATA61", - "PCIE_BYP0_L_18", - "PCIE_IMUX45_R_14", - "PCIE_PIPETX6DATA14", - "PCIE_LOGIC_OUTS_B12_R_12", - "PCIE_IMUX18_R_18", - "PCIE_LOGIC_OUTS_B17_L_15", - "PCIE_LOGIC_OUTS_B7_L_16", - "PCIE_PIPETX0DATA3", - "PCIE_BLOCK_OUTS_B1_R_8", - "PCIE_MIMRXWDATA41", - "PCIE_IMUX0_R_12", - "PCIE_EL1BEG2_5", - "PCIE_PIPETX4DATA9", - "PCIE_DBGVECB30", - "PCIE_CFGERRAERHEADERLOG102", - "PCIE_PIPETX5DATA7", - "PCIE_WW4C2_3", - "PCIE_FAN1_L_16", - "PCIE_IMUX3_L_1", - "PCIE_CFGTRANSACTIONADDR2", - "PCIE_IMUX10_R_5", - "PCIE_PIPETX7COMPLIANCE", - "PCIE_NE4BEG1_10", - "PCIE_LOGIC_OUTS_B20_L_9", - "PCIE_IMUX17_L_16", - "PCIE_EE2BEG3_2", - "PCIE_IMUX2_R_19", - "PCIE_EE4C3_17", - "PCIE_CFGMGMTDI1", - "PCIE_CTRL0_L_19", - "PCIE_NW4A2_15", - "PCIE_WL1END1_6", - "PCIE_SE4C0_4", - "PCIE_BYP3_R_18", - "PCIE_FAN7_R_16", - "PCIE_EE4BEG3_13", - "PCIE_PIPETX7DATA10", - "PCIE_NW2A1_4", - "PCIE_IMUX32_R_12", - "PCIE_CFGMGMTDI5", - "PCIE_TRNTD31", - "PCIE_EE4A3_7", - "PCIE_NE2A3_3", - "PCIE_IMUX29_L_4", - "PCIE_LOGIC_OUTS_B3_R_12", - "PCIE_EE4A3_18", - "PCIE_LOGIC_OUTS_B11_L_0", - "PCIE_IMUX15_L_2", - "PCIE_LH5_19", - "PCIE_LH10_9", - "PCIE_EE2A0_11", - "PCIE_IMUX17_R_16", - "PCIE_CFGDEVCONTROLMAXPAYLOAD0", - "PCIE_LOGIC_OUTS_B5_L_6", - "PCIE_CFGMGMTDO1", - "PCIE_LH12_1", - "PCIE_NW4A1_9", - "PCIE_CFGMGMTDO27", - "PCIE_IMUX13_R_2", - "PCIE_WW4C0_11", - "PCIE_TRNRD111", - "PCIE_TRNFCNPD4", - "PCIE_LOGIC_OUTS_B9_L_11", - "PCIE_PLINITIALLINKWIDTH0", - "PCIE_IMUX34_L_15", - "PCIE_WW4END1_10", - "PCIE_IMUX35_R_3", - "PCIE_PIPERX5DATA8", - "PCIE_EE4B1_1", - "PCIE_TRNRD112", - "PCIE_NE4C2_13", - "PCIE_FAN5_R_16", - "PCIE_SW4END0_16", - "PCIE_BLOCK_OUTS_B0_L_5", - "PCIE_TRNRD88", - "PCIE_TRNRD55", - "PCIE_MIMTXWDATA33", - "PCIE_CFGERRACSN", - "PCIE_EE2BEG0_3", - "PCIE_LOGIC_OUTS_B13_L_19", - "PCIE_NW4A0_18", - "PCIE_EE2BEG2_2", - "PCIE_IMUX44_R_15", - "PCIE_PIPERX4STATUS0", - "PCIE_SW4A1_3", - "PCIE_TRNRD11", - "PCIE_PLDIRECTEDCHANGEDONE", - "PCIE_NE4BEG0_18", - "PCIE_EE4B0_11", - "PCIE_LOGIC_OUTS_B10_L_9", - "PCIE_LH1_13", - "PCIE_XILUNCONNOUT37", - "PCIE_PIPERX4DATA1", - "PCIE_LH12_17", - "PCIE_LH6_17", - "PCIE_CFGMGMTRDWRDONEN", - "PCIE_MIMTXRDATA24", - "PCIE_EDTCHANNELSOUT2", - "PCIE_EE4C1_11", - "PCIE_DBGVECB28", - "PCIE_TL2ERRHDR40", - "PCIE_CFGDSDEVICENUMBER0", - "PCIE_NW4A3_5", - "PCIE_IMUX25_L_16", - "PCIE_XILUNCONNOUT25", - "PCIE_WW4A1_3", - "PCIE_LOGIC_OUTS_B16_L_13", - "PCIE_SE4C3_13", - "PCIE_CTRL0_L_2", - "PCIE_FAN0_R_13", - "PCIE_BLOCK_OUTS_B0_R_16", - "PCIE_NE2A0_10", - "PCIE_LOGIC_OUTS_B15_L_18", - "PCIE_LOGIC_OUTS_B4_L_0", - "PCIE_IMUX3_R_13", - "PCIE_CFGMGMTDWADDR2", - "PCIE_IMUX28_L_18", - "PCIE_MIMRXRDATA59", - "PCIE_LOGIC_OUTS_B9_L_18", - "PCIE_ER1BEG2_11", - "PCIE_DBGVECA34", - "PCIE_CFGDSN14", - "PCIE_FAN0_R_0", - "PCIE_SE4C0_12", - "PCIE_NW2A1_15", - "PCIE_TRNRDLLPDATA34", - "PCIE_IMUX16_R_9", - "PCIE_MIMTXWDATA46", - "PCIE_IMUX3_L_2", - "PCIE_IMUX14_L_18", - "PCIE_CFGMGMTWRREADONLYN", - "PCIE_SW4END1_19", - "PCIE_PIPETX7DATA0", - "PCIE_IMUX33_L_8", - "PCIE_EE2A1_18", - "PCIE_IMUX40_L_16", - "PCIE_IMUX36_R_7", - "PCIE_LH2_15", - "PCIE_IMUX28_L_10", - "PCIE_LOGIC_OUTS_B1_L_17", - "PCIE_IMUX19_R_10", - "PCIE_DRPDI8", - "PCIE_IMUX6_R_18", - "PCIE_EE2A1_6", - "PCIE_LH11_2", - "PCIE_IMUX11_L_0", - "PCIE_WL1END0_15", - "PCIE_SW4A3_6", - "PCIE_CFGERRAERHEADERLOG109", - "PCIE_EL1BEG3_4", - "PCIE_IMUX12_L_19", - "PCIE_IMUX6_R_13", - "PCIE_IMUX20_R_8", - "PCIE_CLK0_L_6", - "PCIE_BYP5_L_5", - "PCIE_LOGIC_OUTS_B0_L_2", - "PCIE_IMUX3_L_12", - "PCIE_TRNRDLLPDATA27", - "PCIE_CTRL1_L_6", - "PCIE_NW4END0_6", - "PCIE_IMUX35_L_18", - "PCIE_IMUX19_L_17", - "PCIE_PIPETX5DATA4", - "PCIE_CFGERRTLPCPLHEADER4", - "PCIE_IMUX4_L_4", - "PCIE_IMUX1_L_2", - "PCIE_WW4A1_4", - "PCIE_PIPETX5COMPLIANCE", - "PCIE_MIMTXWADDR2", - "PCIE_IMUX21_L_12", - "PCIE_IMUX30_L_12", - "PCIE_MIMRXRDATA19", - "PCIE_IMUX41_R_17", - "PCIE_CFGSUBSYSID11", - "PCIE_EE4C3_7", - "PCIE_EL1BEG1_8", - "PCIE_FAN4_R_11", - "PCIE_LH8_6", - "PCIE_ER1BEG2_2", - "PCIE_TRNRD37", - "PCIE_IMUX46_R_6", - "PCIE_IMUX9_L_19", - "PCIE_CFGERRTLPCPLHEADER0", - "PCIE_PIPERX6PHYSTATUS", - "PCIE_EE2A1_1", - "PCIE_WR1END2_4", - "PCIE_WW4END1_16", - "PCIE_IMUX5_R_14", - "PCIE_CTRL1_L_9", - "PCIE_EL1BEG0_15", - "PCIE_LOGIC_OUTS_B12_R_15", - "PCIE_CFGMGMTDI8", - "PCIE_IMUX40_R_11", - "PCIE_CFGERRAERHEADERLOG9", - "PCIE_TRNTDLLPDATA17", - "PCIE_DBGVECA33", - "PCIE_EE2BEG3_4", - "PCIE_SE4BEG2_8", - "PCIE_IMUX32_L_17", - "PCIE_IMUX30_L_14", - "PCIE_TRNTD11", - "PCIE_IMUX1_R_3", - "PCIE_NE4C1_9", - "PCIE_MIMTXRADDR3", - "PCIE_WL1END3_16", - "PCIE_LOGIC_OUTS_B16_R_9", - "PCIE_MONITOR_P_17", - "PCIE_MIMRXWDATA45", - "PCIE_IMUX35_L_16", - "PCIE_LOGIC_OUTS_B16_L_8", - "PCIE_EE2BEG3_15", - "PCIE_TRNFCCPLH6", - "PCIE_IMUX35_R_9", - "PCIE_IMUX19_R_6", - "PCIE_IMUX20_R_16", - "PCIE_IMUX27_L_6", - "PCIE_CLK1_R_4", - "PCIE_SE2A0_8", - "PCIE_IMUX23_R_9", - "PCIE_SE2A3_2", - "PCIE_IMUX23_L_16", - "PCIE_NE4C1_11", - "PCIE_MIMTXRADDR7", - "PCIE_TL2ERRHDR16", - "PCIE_TRNRDLLPDATA6", - "PCIE_CTRL1_L_10", - "PCIE_EE4BEG0_10", - "PCIE_EE2A2_6", - "PCIE_LOGIC_OUTS_B21_R_12", - "PCIE_LH1_8", - "PCIE_LOGIC_OUTS_B2_L_16", - "PCIE_BYP0_R_19", - "PCIE_SW2A3_3", - "PCIE_LOGIC_OUTS_B9_R_17", - "PCIE_IMUX24_R_0", - "PCIE_CFGERRAERHEADERLOG93", - "PCIE_TRNRD0", - "PCIE_BYP6_L_10", - "PCIE_EL1BEG1_13", - "PCIE_LOGIC_OUTS_B19_R_16", - "PCIE_CFGINTERRUPTDI0", - "PCIE_EL1BEG2_11", - "PCIE_XILUNCONNOUT1", - "PCIE_IMUX22_R_8", - "PCIE_LH4_10", - "PCIE_NE4C2_18", - "PCIE_IMUX9_R_15", - "PCIE_LOGIC_OUTS_B19_R_7", - "PCIE_EE4B3_5", - "PCIE_IMUX18_R_3", - "PCIE_IMUX22_L_12", - "PCIE_PLLTSSMSTATE2", - "PCIE_SE4C2_8", - "PCIE_IMUX3_R_12", - "PCIE_EE2A3_19", - "PCIE_TRNTD55", - "PCIE_LOGIC_OUTS_B8_L_12", - "PCIE_IMUX10_L_1", - "PCIE_LOGIC_OUTS_B16_R_12", - "PCIE_WL1END3_15", - "PCIE_TRNRDLLPSRCRDY1", - "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", - "PCIE_IMUX22_R_7", - "PCIE_WL1END0_16", - "PCIE_BLOCK_OUTS_B3_R_4", - "PCIE_WW2A1_11", - "PCIE_IMUX20_R_17", - "PCIE_EE2BEG0_4", - "PCIE_LOGIC_OUTS_B2_R_1", - "PCIE_TRNRD2", - "PCIE_LOGIC_OUTS_B2_R_16", - "PCIE_WR1END3_8", - "PCIE_LOGIC_OUTS_B20_R_19", - "PCIE_WW2END0_12", - "PCIE_CFGERRAERHEADERLOG40", - "PCIE_FAN0_R_2", - "PCIE_LH2_13", - "PCIE_XILUNCONNOUT18", - "PCIE_IMUX12_R_13", - "PCIE_TRNRD101", - "PCIE_NE2A1_19", - "PCIE_WW4B3_3", - "PCIE_PIPETX4DATA15", - "PCIE_TL2ERRHDR11", - "PCIE_CFGVENDID14", - "PCIE_IMUX34_L_0", - "PCIE_CFGDSN31", - "PCIE_BYP3_R_1", - "PCIE_FAN4_L_1", - "PCIE_MIMRXRADDR10", - "PCIE_EE4C3_12", - "PCIE_IMUX9_R_13", - "PCIE_IMUX33_R_17", - "PCIE_CFGDSFUNCTIONNUMBER0", - "PCIE_LH6_9", - "PCIE_EE4B1_19", - "PCIE_IMUX17_R_11", - "PCIE_LOGIC_OUTS_B23_L_0", - "PCIE_FAN1_L_18", - "PCIE_BYP1_L_6", - "PCIE_IMUX14_R_8", - "PCIE_PLLTSSMSTATE4", - "PCIE_SE4C1_12", - "PCIE_IMUX29_L_3", - "PCIE_WW4A1_13", - "PCIE_IMUX42_L_2", - "PCIE_CFGLINKCONTROLASPMCONTROL0", - "PCIE_WW4END3_15", - "PCIE_MIMRXRDATA64", - "PCIE_LOGIC_OUTS_B23_R_9", - "PCIE_MIMTXWDATA38", - "PCIE_PIPERX4DATA15", - "PCIE_IMUX4_L_15", - "PCIE_XILUNCONNOUT9", - "PCIE_MIMTXWEN", - "PCIE_TRNRD99", - "PCIE_LH3_15", - "PCIE_SE4BEG0_6", - "PCIE_WW2A1_2", - "PCIE_PLDBGVEC4", - "PCIE_IMUX16_L_9", - "PCIE_CFGTRANSACTIONADDR6", - "PCIE_PIPETX3COMPLIANCE", - "PCIE_MIMRXWDATA38", - "PCIE_LOGIC_OUTS_B15_L_9", - "PCIE_EE2BEG1_13", - "PCIE_EE4B1_2", - "PCIE_MIMRXWDATA58", - "PCIE_WW2A2_11", - "PCIE_FAN5_L_2", - "PCIE_EE4A0_8", - "PCIE_BYP4_R_8", - "PCIE_CFGERRTLPCPLHEADER1", - "PCIE_MIMTXRDATA37", - "PCIE_PIPETX1DATA0", - "PCIE_IMUX7_R_5", - "PCIE_WW4B1_8", - "PCIE_WW4END1_2", - "PCIE_MIMRXWDATA5", - "PCIE_TRNTDLLPDATA27", - "PCIE_FAN1_L_3", - "PCIE_LH7_11", - "PCIE_LOGIC_OUTS_B5_R_5", - "PCIE_CFGMSGDATA10", - "PCIE_LOGIC_OUTS_B9_R_9", - "PCIE_NW4END0_3", - "PCIE_LOGIC_OUTS_B6_R_9", - "PCIE_WW4C2_1", - "PCIE_LOGIC_OUTS_B4_L_6", - "PCIE_EL1BEG2_16", - "PCIE_FAN1_R_5", - "PCIE_SE2A0_19", - "PCIE_LOGIC_OUTS_B19_R_5", - "PCIE_NW2A1_18", - "PCIE_IMUX30_L_18", - "PCIE_CLK1_L_2", - "PCIE_CFGDEVCONTROL2LTREN", - "PCIE_IMUX8_L_12", - "PCIE_IMUX13_R_9", - "PCIE_WW4A3_13", - "PCIE_EE2BEG2_6", - "PCIE_WW4C2_6", - "PCIE_LOGIC_OUTS_B3_L_11", - "PCIE_WW4END0_6", - "PCIE_MIMRXWDATA51", - "PCIE_CFGVENDID13", - "PCIE_IMUX17_R_14", - "PCIE_CTRL0_L_1", - "PCIE_IMUX22_R_19", - "PCIE_PIPERX1DATA5", - "PCIE_SW4A0_15", - "PCIE_IMUX31_R_18", - "PCIE_IMUX12_L_4", - "PCIE_IMUX15_R_8", - "PCIE_BYP0_L_17", - "PCIE_CLK1_L_18", - "PCIE_IMUX17_R_1", - "PCIE_IMUX34_L_10", - "PCIE_DRPDI2", - "PCIE_IMUX0_R_13", - "PCIE_WW2END0_19", - "PCIE_FAN3_R_12", - "PCIE_IMUX19_L_19", - "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", - "PCIE_CTRL0_R_17", - "PCIE_IMUX32_L_14", - "PCIE_IMUX37_L_10", - "PCIE_MIMRXRDATA55", - "PCIE_IMUX13_R_10", - "PCIE_CFGERRTLPCPLHEADER22", - "PCIE_SE4C3_4", - "PCIE_IMUX47_L_16", - "PCIE_DBGSCLRA", - "PCIE_NE4BEG2_1", - "PCIE_TRNFCPD8", - "PCIE_IMUX16_L_10", - "PCIE_WW4B1_15", - "PCIE_CFGERRAERHEADERLOG59", - "PCIE_TRNRDLLPDATA50", - "PCIE_FAN5_R_14", - "PCIE_IMUX17_L_18", - "PCIE_CFGERRAERHEADERLOG85", - "PCIE_IMUX36_R_4", - "PCIE_SW4END2_16", - "PCIE_IMUX35_R_11", - "PCIE_FAN6_L_12", - "PCIE_IMUX25_R_11", - "PCIE_IMUX14_R_4", - "PCIE_WR1END3_15", - "PCIE_NW2A3_8", - "PCIE_EE4A3_2", - "PCIE_EE4C2_0", - "PCIE_IMUX36_L_6", - "PCIE_XILUNCONNOUT30", - "PCIE_EE4B0_19", - "PCIE_NE4BEG3_0", - "PCIE_LOGIC_OUTS_B22_L_4", - "PCIE_IMUX14_R_11", - "PCIE_PIPETX2DATA2", - "PCIE_EE2A1_0", - "PCIE_CFGDSBUSNUMBER0", - "PCIE_BLOCK_OUTS_B3_R_6", - "PCIE_EE2BEG2_3", - "PCIE_MONITOR_P_16", - "PCIE_FAN0_L_19", - "PCIE_NW4END3_12", - "PCIE_BLOCK_OUTS_B3_L_12", - "PCIE_CFGAERINTERRUPTMSGNUM2", - "PCIE_EE4B2_0", - "PCIE_NW4END3_1", - "PCIE_BLOCK_OUTS_B2_R_18", - "PCIE_IMUX27_L_19", - "PCIE_IMUX40_L_0", - "PCIE_IMUX25_R_0", - "PCIE_TL2ERRHDR12", - "PCIE_TRNRDLLPSRCRDY0", - "PCIE_SE4C3_15", - "PCIE_BYP0_R_6", - "PCIE_BLOCK_OUTS_B2_L_18", - "PCIE_IMUX23_L_1", - "PCIE_IMUX28_R_18", - "PCIE_LOGIC_OUTS_B10_R_15", - "PCIE_IMUX18_L_19", - "PCIE_WW4END0_13", - "PCIE_IMUX40_R_5", - "PCIE_LOGIC_OUTS_B0_L_8", - "PCIE_IMUX18_R_0", - "PCIE_SW2A1_7", - "PCIE_WR1END0_9", - "PCIE_LOGIC_OUTS_B13_R_7", - "PCIE_PIPERX5DATA15", - "PCIE_TRNTDLLPDATA11", - "PCIE_IMUX20_R_10", - "PCIE_CFGERRTLPCPLHEADER25", - "PCIE_WL1END1_16", - "PCIE_WW4A2_0", - "PCIE_CFGERRAERHEADERLOG70", - "PCIE_PIPETX7DATA7", - "PCIE_FAN6_L_3", - "PCIE_FAN1_R_17", - "PCIE_IMUX37_R_16", - "PCIE_CFGDSN48", - "PCIE_PIPERX3STATUS0", - "PCIE_IMUX31_L_7", - "PCIE_IMUX1_L_15", - "PCIE_PIPERX1DATA8", - "PCIE_CFGAERECRCGENEN", - "PCIE_EE2A2_18", - "PCIE_IMUX17_L_14", - "PCIE_IMUX29_R_17", - "PCIE_WW2A0_12", - "PCIE_TRNFCCPLH5", - "PCIE_SE2A1_16", - "PCIE_WW4B0_7", - "PCIE_LOGIC_OUTS_B23_R_10", - "PCIE_IMUX36_L_1", - "PCIE_LOGIC_OUTS_B22_R_2", - "PCIE_IMUX26_L_14", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", - "PCIE_IMUX30_L_4", - "PCIE_LOGIC_OUTS_B23_L_2", - "PCIE_CFGMSGRECEIVEDERRFATAL", - "PCIE_WW4END1_6", - "PCIE_WR1END0_17", - "PCIE_EE2A0_15", - "PCIE_IMUX35_L_9", - "PCIE_CTRL0_R_9", - "PCIE_LOGIC_OUTS_B15_L_7", - "PCIE_EE4C2_19", - "PCIE_IMUX33_L_11", - "PCIE_WL1END1_15", - "PCIE_IMUX18_L_13", - "PCIE_LH8_17", - "PCIE_LOGIC_OUTS_B1_R_11", - "PCIE_WW4C3_16", - "PCIE_NE2A3_16", - "PCIE_FAN1_L_6", - "PCIE_IMUX16_R_11", - "PCIE_CFGERRAERHEADERLOG44", - "PCIE_IMUX1_R_11", - "PCIE_NW4A3_9", - "PCIE_NW4A1_12", - "PCIE_SW2A1_13", - "PCIE_LL2SUSPENDNOW", - "PCIE_PIPERX5STATUS2", - "PCIE_PLLTSSMSTATE5", - "PCIE_PIPERX7DATA8", - "PCIE_IMUX6_L_12", - "PCIE_LH2_6", - "PCIE_CLK0_L_2", - "PCIE_TRNRD46", - "PCIE_EE4B3_14", - "PCIE_IMUX47_R_12", - "PCIE_EE2A3_1", - "PCIE_PIPETX2POWERDOWN0", - "PCIE_LOGIC_OUTS_B19_L_5", - "PCIE_TL2ERRHDR60", - "PCIE_NE4C3_1", - "PCIE_SE4BEG2_10", - "PCIE_PIPERX0STATUS0", - "PCIE_PIPETX5POWERDOWN0", - "PCIE_NW2A2_3", - "PCIE_FAN5_L_9", - "PCIE_TRNTD118", - "PCIE_LOGIC_OUTS_B9_R_1", - "PCIE_NW2A0_10", - "PCIE_NW4END2_3", - "PCIE_IMUX39_R_2", - "PCIE_PIPETX4DATA6", - "PCIE_CFGINTERRUPTDO2", - "PCIE_FAN6_L_8", - "PCIE_LOGIC_OUTS_B10_L_7", - "PCIE_TRNRD121", - "PCIE_IMUX14_R_0", - "PCIE_IMUX47_R_17", - "PCIE_PIPERX3CHANISALIGNED", - "PCIE_CFGERRAERHEADERLOG84", - "PCIE_IMUX28_L_14", - "PCIE_IMUX30_L_7", - "PCIE_BYP3_R_15", - "PCIE_LL2LINKSTATUS1", - "PCIE_FAN1_R_4", - "PCIE_FAN4_L_2", - "PCIE_TRNRD124", - "PCIE_IMUX11_L_2", - "PCIE_SW4A2_3", - "PCIE_DBGVECA11", - "PCIE_IMUX9_L_10", - "PCIE_BLOCK_OUTS_B3_L_18", - "PCIE_TRNFCCPLH4", - "PCIE_IMUX25_L_13", - "PCIE_PIPETX3DATA11", - "PCIE_LOGIC_OUTS_B8_R_2", - "PCIE_BYP6_R_9", - "PCIE_IMUX25_L_4", - "PCIE_FAN3_L_3", - "PCIE_LOGIC_OUTS_B21_R_3", - "PCIE_IMUX11_R_5", - "PCIE_BLOCK_OUTS_B1_R_11", - "PCIE_PIPETX4DATA0", - "PCIE_CTRL0_L_18", - "PCIE_BYP0_L_13", - "PCIE_TL2ERRHDR41", - "PCIE_CFGDSN63", - "PCIE_IMUX7_R_3", - "PCIE_IMUX5_R_18", - "PCIE_SW2A1_18", - "PCIE_SW2A2_18", - "PCIE_IMUX31_L_15", - "PCIE_CTRL1_L_12", - "PCIE_PL2DIRECTEDLSTATE1", - "PCIE_PIPETX5DATA9", - "PCIE_NW4A3_1", - "PCIE_LOGIC_OUTS_B22_L_9", - "PCIE_FAN2_R_18", - "PCIE_CLK0_L_19", - "PCIE_IMUX3_R_5", - "PCIE_LOGIC_OUTS_B10_R_6", - "PCIE_LOGIC_OUTS_B18_R_2", - "PCIE_BYP1_R_10", - "PCIE_EE4BEG3_10", - "PCIE_BLOCK_OUTS_B1_R_0", - "PCIE_IMUX22_R_16", - "PCIE_IMUX15_R_16", - "PCIE_WW4A1_9", - "PCIE_IMUX24_L_9", - "PCIE_TRNTD72", - "PCIE_BYP5_L_0", - "PCIE_FAN0_R_5", - "PCIE_SW4A1_18", - "PCIE_CTRL0_L_8", - "PCIE_LOGIC_OUTS_B17_R_11", - "PCIE_PIPETX7DATA4", - "PCIE_LOGIC_OUTS_B8_R_6", - "PCIE_LOGIC_OUTS_B16_L_12", - "PCIE_LOGIC_OUTS_B6_L_3", - "PCIE_WR1END3_19", - "PCIE_WL1END0_9", - "PCIE_EE4A0_3", - "PCIE_CFGMSGDATA12", - "PCIE_SE2A1_17", - "PCIE_EE2A3_3", - "PCIE_IMUX42_R_14", - "PCIE_IMUX21_L_9", - "PCIE_IMUX18_L_1", - "PCIE_SE4BEG3_10", - "PCIE_BYP2_R_14", - "PCIE_IMUX28_L_2", - "PCIE_SW4A0_4", - "PCIE_IMUX41_R_19", - "PCIE_CLK0_R_14", - "PCIE_NW4A3_19", - "PCIE_IMUX37_L_7", - "PCIE_IMUX10_L_10", - "PCIE_EE4BEG0_8", - "PCIE_IMUX44_L_5", - "PCIE_WW4END2_19", - "PCIE_IMUX18_R_17", - "PCIE_IMUX28_L_6", - "PCIE_SE4C1_6", - "PCIE_WW4B1_10", - "PCIE_IMUX12_L_6", - "PCIE_DBGVECB31", - "PCIE_SE2A0_0", - "PCIE_NW4A0_5", - "PCIE_NW4END0_4", - "PCIE_LH8_2", - "PCIE_NW4A2_0", - "PCIE_DBGVECC1", - "PCIE_IMUX2_L_3", - "PCIE_IMUX1_R_4", - "PCIE_EE2BEG1_2", - "PCIE_LOGIC_OUTS_B20_R_7", - "PCIE_LOGIC_OUTS_B20_L_17", - "PCIE_LOGIC_OUTS_B12_L_12", - "PCIE_LOGIC_OUTS_B19_L_9", - "PCIE_TRNTD19", - "PCIE_DRPDO14", - "PCIE_CFGFORCEMPS1", - "PCIE_SE4C0_15", - "PCIE_FAN7_L_16", - "PCIE_IMUX19_R_8", - "PCIE_EE4B2_17", - "PCIE_IMUX43_L_4", - "PCIE_BLOCK_OUTS_B0_L_7", - "PCIE_IMUX41_L_13", - "PCIE_LOGIC_OUTS_B6_R_11", - "PCIE_FAN3_L_17", - "PCIE_IMUX29_L_15", - "PCIE_LH6_15", - "PCIE_BLOCK_OUTS_B0_R_18", - "PCIE_LOGIC_OUTS_B7_L_17", - "PCIE_EE2BEG1_4", - "PCIE_CLK1_L_16", - "PCIE_PLLTSSMSTATE0", - "PCIE_CLK0_R_0", - "PCIE_LOGIC_OUTS_B2_R_3", - "PCIE_SE4BEG3_4", - "PCIE_LOGIC_OUTS_B5_R_6", - "PCIE_IMUX4_R_6", - "PCIE_TRNRDLLPDATA42", - "PCIE_IMUX32_L_5", - "PCIE_TRNTD108", - "PCIE_IMUX46_L_13", - "PCIE_NW4END3_10", - "PCIE_TRNRDLLPDATA18", - "PCIE_LOGIC_OUTS_B3_R_14", - "PCIE_WW4C0_8", - "PCIE_IMUX35_R_15", - "PCIE_EE2A1_15", - "PCIE_NW4A0_16", - "PCIE_WW4END0_12", - "PCIE_BYP5_R_9", - "PCIE_EL1BEG1_15", - "PCIE_IMUX12_R_17", - "PCIE_LOGIC_OUTS_B14_L_8", - "PCIE_IMUX3_R_0", - "PCIE_DRPDO0", - "PCIE_EE2BEG2_17", - "PCIE_IMUX5_R_16", - "PCIE_EE2BEG3_17", - "PCIE_LH4_1", - "PCIE_WW2A2_17", - "PCIE_LOGIC_OUTS_B7_R_10", - "PCIE_WR1END2_7", - "PCIE_PIPETX7DATA1", - "PCIE_CFGERRATOMICEGRESSBLOCKEDN", - "PCIE_TRNFCPH4", - "PCIE_EL1BEG2_2", - "PCIE_IMUX42_L_7", - "PCIE_CFGDSDEVICENUMBER2", - "PCIE_PIPETX0DATA4", - "PCIE_TRNRD120", - "PCIE_IMUX35_L_7", - "PCIE_CFGDEVID8", - "PCIE_MIMRXWDATA25", - "PCIE_EE4BEG1_1", - "PCIE_LOGIC_OUTS_B1_L_14", - "PCIE_NE2A3_15", - "PCIE_PIPERX5DATA1", - "PCIE_WW4C0_19", - "PCIE_NE2A1_8", - "PCIE_CFGAERINTERRUPTMSGNUM0", - "PCIE_IMUX2_L_18", - "PCIE_LH6_19", - "PCIE_WL1END2_1", - "PCIE_LOGIC_OUTS_B15_R_8", - "PCIE_IMUX11_R_14", - "PCIE_IMUX18_L_8", - "PCIE_TRNTD97", - "PCIE_LOGIC_OUTS_B18_R_14", - "PCIE_PIPERX4STATUS1", - "PCIE_BLOCK_OUTS_B2_R_3", - "PCIE_WW2A3_11", - "PCIE_PLDOWNSTREAMDEEMPHSOURCE", - "PCIE_CFGERRAERHEADERLOG126", - "PCIE_PIPERX6DATA14", - "PCIE_IMUX16_R_2", - "PCIE_PIPETX2DATA9", - "PCIE_IMUX20_L_0", - "PCIE_CFGDSN41", - "PCIE_NE4BEG1_3", - "PCIE_LOGIC_OUTS_B17_R_14", - "PCIE_CFGFORCEMPS2", - "PCIE_SW4END1_4", - "PCIE_LOGIC_OUTS_B10_L_1", - "PCIE_WW4A3_18", - "PCIE_FAN5_L_6", - "PCIE_LOGIC_OUTS_B7_R_16", - "PCIE_TRNRD97", - "PCIE_WW4C0_18", - "PCIE_IMUX37_L_6", - "PCIE_IMUX30_R_1", - "PCIE_MIMRXWDATA49", - "PCIE_WW2END1_9", - "PCIE_EE4B3_16", - "PCIE_TRNFCNPD11", - "PCIE_TRNRD9", - "PCIE_EL1BEG1_14", - "PCIE_LOGIC_OUTS_B22_R_0", - "PCIE_BYP0_R_2", - "PCIE_FAN3_L_18", - "PCIE_LOGIC_OUTS_B6_L_10", - "PCIE_EE4B3_12", - "PCIE_MIMTXRDATA10", - "PCIE_IMUX1_L_8", - "PCIE_DBGVECA38", - "PCIE_PIPERX2DATA6", - "PCIE_MIMTXRADDR2", - "PCIE_CTRL0_R_19", - "PCIE_IMUX44_R_4", - "PCIE_MIMRXRDATA32", - "PCIE_BYP0_R_11", - "PCIE_CTRL0_R_10", - "PCIE_LOGIC_OUTS_B5_L_12", - "PCIE_LH12_10", - "PCIE_IMUX37_R_11", - "PCIE_FAN3_L_7", - "PCIE_EE2BEG2_0", - "PCIE_SE4BEG2_11", - "PCIE_LH5_8", - "PCIE_IMUX12_R_7", - "PCIE_PIPERX1DATA6", - "PCIE_IMUX47_R_2", - "PCIE_BYP6_L_3", - "PCIE_IMUX24_R_5", - "PCIE_DBGVECB5", - "PCIE_SE4BEG1_0", - "PCIE_CFGLINKCONTROLEXTENDEDSYNC", - "PCIE_IMUX16_L_0", - "PCIE_FAN0_R_19", - "PCIE_IMUX44_R_12", - "PCIE_DBGVECA13", - "PCIE_WW2A3_9", - "PCIE_DBGVECA47", - "PCIE_CFGSUBSYSID13", - "PCIE_ER1BEG3_13", - "PCIE_PIPETX3DATA13", - "PCIE_SW2A3_8", - "PCIE_PIPERX3DATA13", - "PCIE_WW4END1_18", - "PCIE_NE2A2_5", - "PCIE_NW4A1_8", - "PCIE_LH2_18", - "PCIE_TRNTD107", - "PCIE_IMUX20_R_0", - "PCIE_IMUX26_L_4", - "PCIE_BYP1_L_8", - "PCIE_IMUX43_L_11", - "PCIE_LOGIC_OUTS_B1_L_13", - "PCIE_CFGERRAERHEADERLOG96", - "PCIE_LOGIC_OUTS_B11_R_5", - "PCIE_IMUX39_R_12", - "PCIE_PIPERX4VALID", - "PCIE_FAN5_L_17", - "PCIE_IMUX27_L_10", - "PCIE_LOGIC_OUTS_B23_R_7", - "PCIE_LOGIC_OUTS_B20_L_1", - "PCIE_FAN2_L_12", - "PCIE_IMUX4_L_10", - "PCIE_EE4A1_19", - "PCIE_BLOCK_OUTS_B2_L_13", - "PCIE_MIMRXWDATA22", - "PCIE_IMUX5_L_6", - "PCIE_LH10_1", - "PCIE_XILUNCONNOUT39", - "PCIE_EE4B3_0", - "PCIE_IMUX27_R_0", - "PCIE_TL2ERRMALFORMED", - "PCIE_NW4END3_14", - "PCIE_PLUPSTREAMPREFERDEEMPH", - "PCIE_WL1END2_10", - "PCIE_LH6_3", - "PCIE_ER1BEG2_9", - "PCIE_TRNTD74", - "PCIE_LL2REPLAYROERR", - "PCIE_XILUNCONNOUT24", - "PCIE_IMUX7_L_15", - "PCIE_IMUX24_L_16", - "PCIE_CTRL0_L_9", - "PCIE_LH10_17", - "PCIE_WW2A2_5", - "PCIE_BLOCK_OUTS_B2_R_17", - "PCIE_CFGMGMTDI2", - "PCIE_IMUX31_L_0", - "PCIE_MIMTXWDATA6", - "PCIE_TRNFCNPD1", - "PCIE_IMUX28_L_1", - "PCIE_TRNTD121", - "PCIE_IMUX36_L_14", - "PCIE_NW4END3_5", - "PCIE_LOGIC_OUTS_B20_R_15", - "PCIE_SW4END0_1", - "PCIE_DBGVECA6", - "PCIE_CFGPCIELINKSTATE2", - "PCIE_SE4C2_14", - "PCIE_EE4A2_2", - "PCIE_PIPERX1STATUS2", - "PCIE_EE4C1_9", - "PCIE_MIMRXRDATA1", - "PCIE_TRNRD39", - "PCIE_FAN1_L_13", - "PCIE_CFGDSN52", - "PCIE_IMUX44_L_8", - "PCIE_CFGDSN29", - "PCIE_FAN2_R_11", - "PCIE_CFGMGMTDO30", - "PCIE_NE4BEG0_1", - "PCIE_IMUX7_L_16", - "PCIE_PIPERX6CHANISALIGNED", - "PCIE_WW4END1_3", - "PCIE_NE2A3_8", - "PCIE_TL2ERRHDR31", - "PCIE_CFGPMWAKEN", - "PCIE_IMUX25_L_5", - "PCIE_NE2A1_14", - "PCIE_MONITOR_N_17", - "PCIE_BYP5_L_13", - "PCIE_WW2END1_3", - "PCIE_DBGVECB39", - "PCIE_WL1END1_18", - "PCIE_SW2A0_18", - "PCIE_BYP7_R_13", - "PCIE_MIMRXWADDR4", - "PCIE_EE4C3_14", - "PCIE_MIMTXWDATA47", - "PCIE_SE4C1_0", - "PCIE_LOGIC_OUTS_B7_R_12", - "PCIE_EE4B2_2", - "PCIE_IMUX43_L_13", - "PCIE_WW2END3_0", - "PCIE_PIPETX2POWERDOWN1", - "PCIE_WW2END0_18", - "PCIE_NE4C3_6", - "PCIE_BYP4_L_17", - "PCIE_TL2ERRHDR23", - "PCIE_NW2A1_12", - "PCIE_LOGIC_OUTS_B21_R_5", - "PCIE_LOGIC_OUTS_B18_R_13", - "PCIE_FAN0_L_18", - "PCIE_IMUX35_L_17", - "PCIE_IMUX11_L_17", - "PCIE_IMUX12_R_5", - "PCIE_CFGVENDID10", - "PCIE_MONITOR_P_6", - "PCIE_DBGVECA37", - "PCIE_EE4C0_4", - "PCIE_IMUX36_R_3", - "PCIE_SW2A1_15", - "PCIE_LOGIC_OUTS_B22_L_2", - "PCIE_LH4_9", - "PCIE_IMUX26_L_15", - "PCIE_IMUX0_R_0", - "PCIE_LOGIC_OUTS_B1_R_5", - "PCIE_IMUX45_R_2", - "PCIE_CLK0_L_5", - "PCIE_LOGIC_OUTS_B14_L_19", - "PCIE_LOGIC_OUTS_B21_L_17", - "PCIE_IMUX8_L_5", - "PCIE_DRPDI7", - "PCIE_LH3_10", - "PCIE_IMUX17_L_17", - "PCIE_IMUX10_R_1", - "PCIE_IMUX44_L_10", - "PCIE_LH9_2", - "PCIE_LOGIC_OUTS_B16_R_2", - "PCIE_ER1BEG0_4", - "PCIE_BLOCK_OUTS_B1_R_9", - "PCIE_IMUX43_R_19", - "PCIE_LOGIC_OUTS_B4_L_5", - "PCIE_CFGDSN42", - "PCIE_IMUX8_R_19", - "PCIE_TL2ERRHDR57", - "PCIE_DBGVECA2", - "PCIE_PL2L0REQ", - "PCIE_IMUX2_R_18", - "PCIE_SW4END0_5", - "PCIE_IMUX4_R_7", - "PCIE_TRNTD18", - "PCIE_EE4B3_15", - "PCIE_WW4B2_3", - "PCIE_CFGPMHALTASPML0SN", - "PCIE_IMUX38_R_4", - "PCIE_CFGMSGDATA9", - "PCIE_CFGVENDID3", - "PCIE_CFGERRAERHEADERLOG104", - "PCIE_LOGIC_OUTS_B14_R_7", - "PCIE_CFGERRAERHEADERLOG18", - "PCIE_BYP7_R_17", - "PCIE_PIPERX6STATUS1", - "PCIE_CTRL0_R_18", - "PCIE_EL1BEG0_10", - "PCIE_PIPERX2DATA1", - "PCIE_BYP3_L_15", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", - "PCIE_WW4A0_14", - "PCIE_IMUX20_R_2", - "PCIE_WW4A0_10", - "PCIE_LOGIC_OUTS_B17_R_6", - "PCIE_IMUX32_L_1", - "PCIE_CFGERRAERHEADERLOG94", - "PCIE_IMUX36_L_12", - "PCIE_LOGIC_OUTS_B3_R_16", - "PCIE_IMUX13_L_2", - "PCIE_FAN5_R_15", - "PCIE_NW2A0_19", - "PCIE_WW2END1_11", - "PCIE_WW2END3_7", - "PCIE_CTRL1_R_13", - "PCIE_SE4C3_2", - "PCIE_IMUX0_L_4", - "PCIE_MIMTXWDATA4", - "PCIE_IMUX42_L_16", - "PCIE_BYP1_R_11", - "PCIE_TRNRD110", - "PCIE_IMUX3_R_4", - "PCIE_WW4C0_16", - "PCIE_MIMTXWDATA15", - "PCIE_BLOCK_OUTS_B1_L_5", - "PCIE_FAN6_R_8", - "PCIE_NW4A3_4", - "PCIE_IMUX37_R_0", - "PCIE_TRNRDLLPDATA63", - "PCIE_IMUX3_R_8", - "PCIE_PIPETX0DATA8", - "PCIE_IMUX7_L_6", - "PCIE_CLK1_L_19", - "PCIE_SW4END0_7", - "PCIE_TRNTD5", - "PCIE_LOGIC_OUTS_B4_L_3", - "PCIE_LOGIC_OUTS_B10_R_19", - "PCIE_CLK1_L_3", - "PCIE_LOGIC_OUTS_B5_R_3", - "PCIE_NW4A0_14", - "PCIE_LOGIC_OUTS_B15_R_9", - "PCIE_IMUX42_R_7", - "PCIE_BYP5_R_2", - "PCIE_LOGIC_OUTS_B3_R_17", - "PCIE_IMUX44_R_8", - "PCIE_FAN5_R_6", - "PCIE_FAN0_L_0", - "PCIE_TRNTD37", - "PCIE_IMUX38_L_4", - "PCIE_LOGIC_OUTS_B2_L_17", - "PCIE_PIPETX7DATA14", - "PCIE_BYP2_R_11", - "PCIE_SE4BEG3_16", - "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", - "PCIE_CLK0_R_4", - "PCIE_WW2A0_11", - "PCIE_CTRL1_L_5", - "PCIE_WW2A1_13", - "PCIE_NE2A3_2", - "PCIE_WW4B1_13", - "PCIE_EE2BEG3_16", - "PCIE_IMUX39_R_6", - "PCIE_SE4BEG2_4", - "PCIE_NE2A2_4", - "PCIE_DBGVECB7", - "PCIE_EE2BEG0_19", - "PCIE_BLOCK_OUTS_B2_R_19", - "PCIE_DBGVECB11", - "PCIE_WW4B3_1", - "PCIE_IMUX17_R_6", - "PCIE_IMUX43_R_12", - "PCIE_CLK0_R_8", - "PCIE_IMUX13_L_12", - "PCIE_WW4C0_1", - "PCIE_IMUX31_R_4", - "PCIE_TRNRDLLPDATA23", - "PCIE_XILUNCONNOUT28", - "PCIE_IMUX25_L_6", - "PCIE_IMUX42_R_8", - "PCIE_LOGIC_OUTS_B1_L_18", - "PCIE_IMUX22_L_15", - "PCIE_FAN3_L_13", - "PCIE_LH12_15", - "PCIE_LOGIC_OUTS_B4_L_1", - "PCIE_CTRL1_L_8", - "PCIE_DBGSCLRE", - "PCIE_TRNRFCPRET", - "PCIE_IMUX22_R_5", - "PCIE_MIMRXRDATA41", - "PCIE_IMUX14_L_15", - "PCIE_DBGVECB10", - "PCIE_CFGMSGRECEIVEDDEASSERTINTB", - "PCIE_TRNFCNPH1", - "PCIE_IMUX40_R_2", - "PCIE_CFGDSN54", - "PCIE_SW2A1_0", - "PCIE_NE2A2_9", - "PCIE_SW4END1_3", - "PCIE_PIPERX3DATA3", - "PCIE_CFGPORTNUMBER3", - "PCIE_WW4A2_19", - "PCIE_SW4END0_18", - "PCIE_CFGMSGDATA3", - "PCIE_IMUX16_L_16", - "PCIE_TL2ERRHDR3", - "PCIE_IMUX2_L_9", - "PCIE_LH11_0", - "PCIE_WR1END1_2", - "PCIE_CFGFORCEMPS0", - "PCIE_EE4A3_16", - "PCIE_LOGIC_OUTS_B2_R_8", - "PCIE_LOGIC_OUTS_B0_R_16", - "PCIE_TRNFCCPLH1", - "PCIE_IMUX4_L_1", - "PCIE_EE4A3_15", - "PCIE_IMUX45_R_10", - "PCIE_FAN5_L_12", - "PCIE_NE2A1_6", - "PCIE_SE4BEG1_11", - "PCIE_WW4END0_16", - "PCIE_CFGERRAERHEADERLOG0", - "PCIE_LOGIC_OUTS_B20_R_13", - "PCIE_IMUX34_R_4", - "PCIE_WW4END0_5", - "PCIE_FAN0_R_17", - "PCIE_IMUX14_L_11", - "PCIE_NE4C0_4", - "PCIE_SW2A2_0", - "PCIE_LH6_7", - "PCIE_IMUX21_R_5", - "PCIE_IMUX33_R_1", - "PCIE_LOGIC_OUTS_B9_L_7", - "PCIE_IMUX31_R_12", - "PCIE_NE2A3_14", - "PCIE_DBGVECB18", - "PCIE_IMUX20_L_18", - "PCIE_IMUX20_L_2", - "PCIE_IMUX16_L_4", - "PCIE_BYP4_R_12", - "PCIE_WW4B3_0", - "PCIE_TRNRDLLPDATA37", - "PCIE_WW4B0_16", - "PCIE_LL2RECEIVERERR", - "PCIE_CFGDSN5", - "PCIE_LOGIC_OUTS_B14_L_13", - "PCIE_LOGIC_OUTS_B17_R_19", - "PCIE_LOGIC_OUTS_B4_R_3", - "PCIE_LOGIC_OUTS_B15_R_6", - "PCIE_IMUX20_L_7", - "PCIE_LOGIC_OUTS_B19_R_4", - "PCIE_WW4C1_3", - "PCIE_DBGVECA43", - "PCIE_WW4END1_1", - "PCIE_FAN6_L_4", - "PCIE_EE4A1_9", - "PCIE_CFGMGMTDO18", - "PCIE_BYP4_L_5", - "PCIE_IMUX18_R_13", - "PCIE_BLOCK_OUTS_B0_R_2", - "PCIE_CFGMGMTDI4", - "PCIE_IMUX3_L_6", - "PCIE_NE2A0_12", - "PCIE_EE2A1_3", - "PCIE_CFGDSN51", - "PCIE_TRNRDLLPDATA11", - "PCIE_LH6_6", - "PCIE_IMUX37_L_14", - "PCIE_DRPWE", - "PCIE_LOGIC_OUTS_B17_L_14", - "PCIE_LOGIC_OUTS_B12_R_14", - "PCIE_DRPDI6", - "PCIE_LH3_11", - "PCIE_IMUX4_R_16", - "PCIE_SE4C0_3", - "PCIE_PIPETX3DATA14", - "PCIE_IMUX1_R_6", - "PCIE_BLOCK_OUTS_B1_L_19", - "PCIE_WW4C2_17", - "PCIE_EL1BEG1_2", - "PCIE_WW4C1_18", - "PCIE_TRNRD118", - "PCIE_CFGTRANSACTIONADDR1", - "PCIE_TRNTD87", - "PCIE_IMUX28_R_14", - "PCIE_TRNRDLLPDATA3", - "PCIE_IMUX45_L_11", - "PCIE_NE4BEG0_17", - "PCIE_TRNRD107", - "PCIE_IMUX2_L_0", - "PCIE_LOGIC_OUTS_B22_L_15", - "PCIE_IMUX4_R_1", - "PCIE_IMUX1_L_7", - "PCIE_EE4BEG3_15", - "PCIE_CFGERRTLPCPLHEADER19", - "PCIE_IMUX39_R_15", - "PCIE_LOGIC_OUTS_B18_L_4", - "PCIE_IMUX36_R_15", - "PCIE_WW4B0_2", - "PCIE_IMUX39_L_12", - "PCIE_FAN5_R_9", - "PCIE_TRNRD53", - "PCIE_WW4B3_12", - "PCIE_IMUX40_R_10", - "PCIE_PIPERX7CHARISK0", - "PCIE_CFGVENDID7", - "PCIE_SE4C2_11", - "PCIE_IMUX16_R_6", - "PCIE_TRNFCNPH0", - "PCIE_FAN0_L_1", - "PCIE_IMUX33_L_0", - "PCIE_TRNRDLLPDATA29", - "PCIE_LH4_5", - "PCIE_XILUNCONNOUT33", - "PCIE_SW2A0_2", - "PCIE_CFGERRTLPCPLHEADER26", - "PCIE_BYP7_R_0", - "PCIE_IMUX30_R_3", - "PCIE_IMUX47_L_7", - "PCIE_TRNRD10", - "PCIE_EE2BEG1_11", - "PCIE_CFGDSN58", - "PCIE_MIMRXWDATA66", - "PCIE_SE4C2_9", - "PCIE_SW4A3_5", - "PCIE_IMUX1_R_16", - "PCIE_LH1_11", - "PCIE_XILUNCONNOUT38", - "PCIE_IMUX27_L_12", - "PCIE_SW2A3_0", - "PCIE_CFGPMRCVENTERL1N", - "PCIE_MIMRXRDATA40", - "PCIE_TRNRD40", - "PCIE_PIPETXRESET", - "PCIE_TRNFCNPH3", - "PCIE_IMUX12_L_7", - "PCIE_EL1BEG1_1", - "PCIE_IMUX14_R_10", - "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", - "PCIE_IMUX24_R_12", - "PCIE_SW2A1_10", - "PCIE_IMUX46_L_12", - "PCIE_BLOCK_OUTS_B2_L_14", - "PCIE_MIMRXWDATA63", - "PCIE_IMUX47_L_17", - "PCIE_PIPETX2DATA6", - "PCIE_TRNRD92", - "PCIE_PIPETX1DATA12", - "PCIE_WR1END0_16", - "PCIE_CFGMGMTDI17", - "PCIE_FAN0_L_4", - "PCIE_BYP3_L_2", - "PCIE_SE4BEG1_4", - "PCIE_EL1BEG3_18", - "PCIE_PIPETX1DATA11", - "PCIE_SE4BEG0_16", - "PCIE_BYP6_R_13", - "PCIE_SW4END3_14", - "PCIE_DBGVECC8", - "PCIE_WL1END0_3", - "PCIE_IMUX31_R_19", - "PCIE_IMUX41_L_12", - "PCIE_IMUX47_L_3", - "PCIE_IMUX28_L_11", - "PCIE_LOGIC_OUTS_B7_L_7", - "PCIE_IMUX26_R_6", - "PCIE_BYP7_L_10", - "PCIE_IMUX43_L_1", - "PCIE_EE4BEG0_16", - "PCIE_WW4A2_11", - "PCIE_BYP5_R_16", - "PCIE_SW4END2_11", - "PCIE_PLDIRECTEDLTSSMNEW4", - "PCIE_EE4A0_2", - "PCIE_LOGIC_OUTS_B5_R_4", - "PCIE_FAN0_L_13", - "PCIE_NE2A0_3", - "PCIE_MIMTXWADDR8", - "PCIE_IMUX41_L_2", - "PCIE_BYP6_R_11", - "PCIE_FAN1_R_1", - "PCIE_TRNTBUFAV1", - "PCIE_DBGVECC7", - "PCIE_IMUX37_L_5", - "PCIE_IMUX1_R_10", - "PCIE_NW2A3_19", - "PCIE_CFGDSN4", - "PCIE_EE4C0_5", - "PCIE_IMUX2_R_16", - "PCIE_FAN5_L_8", - "PCIE_PIPETX6POWERDOWN1", - "PCIE_NW4END1_8", - "PCIE_MIMRXRDATA49", - "PCIE_LOGIC_OUTS_B17_R_17", - "PCIE_WW4C0_7", - "PCIE_IMUX26_R_18", - "PCIE_EL1BEG1_10", - "PCIE_LOGIC_OUTS_B17_R_8", - "PCIE_WR1END0_19", - "PCIE_LOGIC_OUTS_B19_L_17", - "PCIE_PLDBGVEC3", - "PCIE_LOGIC_OUTS_B20_R_3", - "PCIE_PIPERX3STATUS2", - "PCIE_NW4END2_8", - "PCIE_CFGDSN26", - "PCIE_NW4A3_13", - "PCIE_TLRSTN", - "PCIE_WW4END2_1", - "PCIE_LOGIC_OUTS_B14_L_18", - "PCIE_BYP0_L_7", - "PCIE_LOGIC_OUTS_B23_R_1", - "PCIE_CLK1_R_10", - "PCIE_TRNRD24", - "PCIE_LOGIC_OUTS_B18_L_13", - "PCIE_IMUX2_R_7", - "PCIE_IMUX5_R_12", - "PCIE_TRNRDLLPDATA44", - "PCIE_IMUX45_R_8", - "PCIE_LOGIC_OUTS_B7_R_6", - "PCIE_LOGIC_OUTS_B21_R_0", - "PCIE_IMUX25_R_2", - "PCIE_MIMRXRDATA25", - "PCIE_TL2ERRFCPE", - "PCIE_LH8_18", - "PCIE_IMUX25_L_18", - "PCIE_LOGIC_OUTS_B16_L_10", - "PCIE_IMUX14_R_17", - "PCIE_SW4END3_8", - "PCIE_BYP1_R_8", - "PCIE_PIPETX5DATA0", - "PCIE_SW4END3_6", - "PCIE_BLOCK_OUTS_B3_L_16", - "PCIE_IMUX18_L_17", - "PCIE_IMUX1_R_0", - "PCIE_CFGDEVCONTROLPHANTOMEN", - "PCIE_WR1END2_16", - "PCIE_PIPETX0DATA14", - "PCIE_IMUX31_L_6", - "PCIE_IMUX13_L_8", - "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", - "PCIE_LOGIC_OUTS_B13_L_2", - "PCIE_IMUX11_R_19", - "PCIE_FAN2_R_17", - "PCIE_MONITOR_P_4", - "PCIE_IMUX15_R_2", - "PCIE_LOGIC_OUTS_B3_L_18", - "PCIE_BYP6_L_11", - "PCIE_CFGERRAERHEADERLOG72", - "PCIE_BLOCK_OUTS_B3_R_1", - "PCIE_IMUX4_L_13", - "PCIE_CFGERRAERHEADERLOG10", - "PCIE_PIPETX3ELECIDLE", - "PCIE_IMUX40_L_14", - "PCIE_IMUX23_R_15", - "PCIE_IMUX43_R_2", - "PCIE_LH1_5", - "PCIE_WW4A0_17", - "PCIE_NE2A0_0", - "PCIE_BLOCK_OUTS_B2_L_0", - "PCIE_BYP0_L_8", - "PCIE_CFGLINKCONTROLASPMCONTROL1", - "PCIE_IMUX3_L_14", - "PCIE_CLK0_L_3", - "PCIE_MIMRXRDATA60", - "PCIE_SE4C2_15", - "PCIE_BYP3_L_4", - "PCIE_MIMRXRDATA21", - "PCIE_PIPETX3DATA10", - "PCIE_BYP2_L_19", - "PCIE_LH11_5", - "PCIE_CFGTRANSACTION", - "PCIE_IMUX41_R_16", - "PCIE_TRNFCPH3", - "PCIE_EL1BEG1_9", - "PCIE_NE4C0_11", - "PCIE_IMUX13_R_4", - "PCIE_LOGIC_OUTS_B15_R_12", - "PCIE_NW4END0_10", - "PCIE_MIMRXRDATA65", - "PCIE_CTRL0_L_5", - "PCIE_WW4A1_14", - "PCIE_WW4A0_16", - "PCIE_IMUX2_L_16", - "PCIE_IMUX26_L_0", - "PCIE_CFGMSGRECEIVEDASSERTINTC", - "PCIE_DBGVECA1", - "PCIE_NW4A2_3", - "PCIE_IMUX16_L_7", - "PCIE_FAN6_L_17", - "PCIE_EE2BEG1_12", - "PCIE_BYP4_L_8", - "PCIE_SE2A2_19", - "PCIE_LOGIC_OUTS_B2_L_15", - "PCIE_LH9_18", - "PCIE_CFGERRAERHEADERLOG54", - "PCIE_CFGMSGRECEIVEDDEASSERTINTA", - "PCIE_IMUX15_L_1", - "PCIE_LOGIC_OUTS_B14_R_17", - "PCIE_LH12_14", - "PCIE_IMUX33_R_2", - "PCIE_TRNRD95", - "PCIE_SW2A3_17", - "PCIE_IMUX23_R_1", - "PCIE_IMUX43_L_16", - "PCIE_FAN4_R_3", - "PCIE_LOGIC_OUTS_B13_R_5", - "PCIE_WW4A3_5", - "PCIE_DBGVECC4", - "PCIE_IMUX4_L_12", - "PCIE_LOGIC_OUTS_B22_L_14", - "PCIE_TRNRD70", - "PCIE_PIPERX5STATUS0", - "PCIE_IMUX31_L_4", - "PCIE_SE4C2_18", - "PCIE_MIMTXWADDR11", - "PCIE_CFGERRAERHEADERLOG45", - "PCIE_IMUX46_R_2", - "PCIE_LOGIC_OUTS_B6_R_19", - "PCIE_IMUX15_R_12", - "PCIE_EE4B2_12", - "PCIE_MIMTXWDATA53", - "PCIE_LOGIC_OUTS_B4_R_9", - "PCIE_CFGMSGDATA4", - "PCIE_DBGSUBMODE", - "PCIE_IMUX39_L_1", - "PCIE_LOGIC_OUTS_B12_L_13", - "PCIE_TRNTD114", - "PCIE_LOGIC_OUTS_B15_L_16", - "PCIE_PLINITIALLINKWIDTH1", - "PCIE_LH5_3", - "PCIE_LOGIC_OUTS_B17_L_11", - "PCIE_IMUX45_R_5", - "PCIE_IMUX6_L_10", - "PCIE_IMUX22_L_19", - "PCIE_IMUX38_L_10", - "PCIE_CFGTRANSACTIONADDR4", - "PCIE_TRNTSRCDSC", - "PCIE_IMUX15_R_17", - "PCIE_NE4C1_18", - "PCIE_LOGIC_OUTS_B11_L_13", - "PCIE_LH10_7", - "PCIE_IMUX3_R_7", - "PCIE_XILUNCONNOUT27", - "PCIE_SE2A1_7", - "PCIE_IMUX38_R_7", - "PCIE_IMUX37_R_13", - "PCIE_MIMRXWDATA54", - "PCIE_EE4B0_13", - "PCIE_CFGERRTLPCPLHEADER11", - "PCIE_CFGSUBSYSVENDID10", - "PCIE_PIPETX1DATA5", - "PCIE_IMUX42_R_12", - "PCIE_LOGIC_OUTS_B14_R_6", - "PCIE_MONITOR_P_9", - "PCIE_IMUX46_R_14", - "PCIE_TL2ERRHDR63", - "PCIE_IMUX42_R_18", - "PCIE_WL1END0_8", - "PCIE_WW4B1_4", - "PCIE_IMUX44_R_10", - "PCIE_IMUX39_L_14", - "PCIE_MIMTXWDATA5", - "PCIE_CFGERRAERHEADERLOG97", - "PCIE_LOGIC_OUTS_B9_L_13", - "PCIE_IMUX33_L_14", - "PCIE_WW2END1_4", - "PCIE_IMUX14_L_8", - "PCIE_CFGLINKCONTROLCLOCKPMEN", - "PCIE_CFGDSN7", - "PCIE_IMUX22_L_7", - "PCIE_LOGIC_OUTS_B1_L_16", - "PCIE_LOGIC_OUTS_B5_R_15", - "PCIE_EE4C0_17", - "PCIE_IMUX29_L_19", - "PCIE_IMUX17_R_9", - "PCIE_IMUX11_L_8", - "PCIE_CFGPCIELINKSTATE1", - "PCIE_LOGIC_OUTS_B13_L_17", - "PCIE_WW2END0_0", - "PCIE_WL1END1_8", - "PCIE_WW2A3_0", - "PCIE_BYP2_L_18", - "PCIE_IMUX13_R_11", - "PCIE_CFGMSGDATA0", - "PCIE_BYP7_R_2", - "PCIE_IMUX23_L_13", - "PCIE_SW4A0_5", - "PCIE_MIMTXWADDR1", - "PCIE_MIMTXRDATA29", - "PCIE_CFGERRAERHEADERLOG73", - "PCIE_MIMRXWDATA3", - "PCIE_LH10_16", - "PCIE_BYP7_L_12", - "PCIE_FAN6_R_18", - "PCIE_LOGIC_OUTS_B21_L_6", - "PCIE_ER1BEG0_6", - "PCIE_LOGIC_OUTS_B3_R_4", - "PCIE_IMUX33_R_3", - "PCIE_CFGERRAERHEADERLOG76", - "PCIE_LOGIC_OUTS_B17_R_2", - "PCIE_LOGIC_OUTS_B13_R_6", - "PCIE_PIPETX2DATA14", - "PCIE_TRNRD23", - "PCIE_WW4END1_8", - "PCIE_BLOCK_OUTS_B1_R_15", - "PCIE_TRNRDLLPDATA7", - "PCIE_IMUX6_L_11", - "PCIE_IMUX8_L_9", - "PCIE_IMUX22_L_2", - "PCIE_WW4END2_17", - "PCIE_IMUX7_L_2", - "PCIE_EDTCHANNELSIN2", - "PCIE_TRNRDSTRDY", - "PCIE_IMUX46_L_19", - "PCIE_WW2END3_17", - "PCIE_TRNTSTR", - "PCIE_IMUX43_L_18", - "PCIE_LOGIC_OUTS_B20_L_2", - "PCIE_IMUX26_L_5", - "PCIE_TL2ERRHDR18", - "PCIE_CLK0_L_18", - "PCIE_NE2A3_5", - "PCIE_FAN0_R_16", - "PCIE_DRPDO9", - "PCIE_WW4B0_3", - "PCIE_LH6_14", - "PCIE_FAN2_L_0", - "PCIE_LOGIC_OUTS_B13_R_4", - "PCIE_IMUX38_R_5", - "PCIE_WW4END3_14", - "PCIE_ER1BEG0_17", - "PCIE_LH5_1", - "PCIE_TRNRD108", - "PCIE_BYP7_L_0", - "PCIE_NW4A2_14", - "PCIE_IMUX46_L_2", - "PCIE_EL1BEG0_6", - "PCIE_LOGIC_OUTS_B3_R_3", - "PCIE_EE2A3_0", - "PCIE_BYP2_R_2", - "PCIE_BLOCK_OUTS_B2_R_12", - "PCIE_WW2END3_5", - "PCIE_BYP1_L_12", - "PCIE_LOGIC_OUTS_B18_L_7", - "PCIE_CFGERRAERHEADERLOG51", - "PCIE_MIMRXWDATA43", - "PCIE_TRNTD3", - "PCIE_FAN2_R_15", - "PCIE_CFGMSGRECEIVEDPMETO", - "PCIE_SE4C1_19", - "PCIE_CFGDEVID5", - "PCIE_SE2A1_4", - "PCIE_IMUX32_R_15", - "PCIE_LH5_10", - "PCIE_SW2A3_4", - "PCIE_CFGMGMTDI13", - "PCIE_WW4C3_17", - "PCIE_ER1BEG2_12", - "PCIE_TRNTD86", - "PCIE_NE4BEG2_14", - "PCIE_EE4B2_19", - "PCIE_MIMRXRADDR8", - "PCIE_SE4C3_8", - "PCIE_IMUX8_R_12", - "PCIE_PLDIRECTEDLTSSMNEWVLD", - "PCIE_IMUX8_L_0", - "PCIE_IMUX40_L_1", - "PCIE_LOGIC_OUTS_B3_L_0", - "PCIE_LOGIC_OUTS_B8_R_15", - "PCIE_LOGIC_OUTS_B13_L_18", - "PCIE_BYP7_L_2", - "PCIE_IMUX6_R_2", - "PCIE_BLOCK_OUTS_B3_L_14", - "PCIE_IMUX41_R_9", - "PCIE_IMUX23_L_14", - "PCIE_LH2_2", - "PCIE_IMUX13_R_12", - "PCIE_LL2BADTLPERR", - "PCIE_LOGIC_OUTS_B15_R_14", - "PCIE_CFGERRTLPCPLHEADER23", - "PCIE_TRNFCCPLD1", - "PCIE_IMUX27_L_17", - "PCIE_BYP4_R_4", - "PCIE_SW4END1_7", - "PCIE_CFGDEVID2", - "PCIE_NW4A3_6", - "PCIE_LOGIC_OUTS_B15_L_4", - "PCIE_WR1END0_2", - "PCIE_LH3_14", - "PCIE_WR1END2_0", - "PCIE_NW2A2_18", - "PCIE_CFGDSN55", - "PCIE_LH4_2", - "PCIE_IMUX27_L_18", - "PCIE_FAN6_R_10", - "PCIE_CFGDSBUSNUMBER7", - "PCIE_LH12_16", - "PCIE_PIPERX4DATA12", - "PCIE_CTRL0_R_3", - "PCIE_LH4_7", - "PCIE_EE2A0_13", - "PCIE_WW4A2_12", - "PCIE_EL1BEG2_4", - "PCIE_WW4C1_17", - "PCIE_LH7_5", - "PCIE_WL1END0_18", - "PCIE_EE4C3_10", - "PCIE_MIMTXRDATA18", - "PCIE_WW4B1_12", - "PCIE_IMUX37_L_13", - "PCIE_NE4C1_2", - "PCIE_IMUX7_L_4", - "PCIE_MIMTXWADDR10", - "PCIE_FAN1_L_19", - "PCIE_TRNTD57", - "PCIE_SW4A2_18", - "PCIE_IMUX31_L_16", - "PCIE_IMUX31_L_19", - "PCIE_PIPETX4COMPLIANCE", - "PCIE_IMUX45_R_0", - "PCIE_CFGDEVCONTROLMAXPAYLOAD2", - "PCIE_SE2A3_1", - "PCIE_CLK0_L_14", - "PCIE_LOGIC_OUTS_B21_R_19", - "PCIE_LOGIC_OUTS_B20_R_5", - "PCIE_IMUX5_L_17", - "PCIE_IMUX18_L_16", - "PCIE_NE4BEG2_3", - "PCIE_BYP2_R_9", - "PCIE_LOGIC_OUTS_B3_L_16", - "PCIE_TRNTD46", - "PCIE_IMUX41_R_3", - "PCIE_NW4END3_4", - "PCIE_WW2A2_19", - "PCIE_BLOCK_OUTS_B2_L_3", - "PCIE_WW2A3_16", - "PCIE_EE4C0_1", - "PCIE_IMUX20_L_5", - "PCIE_TRNTD62", - "PCIE_CLK1_R_17", - "PCIE_SE4C2_16", - "PCIE_CFGERRAERHEADERLOG53", - "PCIE_NW4A2_19", - "PCIE_LOGIC_OUTS_B3_L_10", - "PCIE_EE4BEG1_12", - "PCIE_BYP7_L_8", - "PCIE_MIMTXWDATA3", - "PCIE_SE4BEG0_0", - "PCIE_IMUX27_R_6", - "PCIE_WW4C1_9", - "PCIE_PIPERX2DATA4", - "PCIE_CLK0_L_13", - "PCIE_PLRXPMSTATE1", - "PCIE_MIMRXWDATA0", - "PCIE_PIPERX7DATA15", - "PCIE_LOGIC_OUTS_B3_L_1", - "PCIE_NW4END1_10", - "PCIE_LOGIC_OUTS_B15_R_17", - "PCIE_LOGIC_OUTS_B1_L_3", - "PCIE_IMUX46_R_3", - "PCIE_CFGMGMTDO9", - "PCIE_EE2A3_13", - "PCIE_LL2TXIDLE", - "PCIE_LOGIC_OUTS_B17_R_0", - "PCIE_IMUX19_L_8", - "PCIE_BYP2_R_18", - "PCIE_CFGDSN25", - "PCIE_CTRL1_L_13", - "PCIE_NW4END1_0", - "PCIE_PIPERX7STATUS2", - "PCIE_IMUX7_L_8", - "PCIE_BYP1_L_15", - "PCIE_IMUX22_L_3", - "PCIE_LOGIC_OUTS_B14_R_13", - "PCIE_EE4A1_4", - "PCIE_WW4END0_10", - "PCIE_ER1BEG2_13", - "PCIE_IMUX41_R_18", - "PCIE_IMUX42_L_0", - "PCIE_DBGVECB55", - "PCIE_SW4A0_2", - "PCIE_WW2A0_9", - "PCIE_NE2A2_3", - "PCIE_NE4C1_13", - "PCIE_FAN2_R_19", - "PCIE_TRNRD43", - "PCIE_DBGVECA10", - "PCIE_EE2BEG0_16", - "PCIE_BYP2_L_16", - "PCIE_IMUX41_L_6", - "PCIE_TRNFCPH7", - "PCIE_FAN6_L_6", - "PCIE_CFGERRCPLRDYN", - "PCIE_IMUX30_L_10", - "PCIE_NW4A2_16", - "PCIE_EE4BEG2_15", - "PCIE_IMUX10_R_8", - "PCIE_EE2BEG2_9", - "PCIE_LOGIC_OUTS_B4_L_8", - "PCIE_PIPERX6STATUS0", - "PCIE_IMUX25_R_10", - "PCIE_IMUX43_R_13", - "PCIE_EE4BEG2_12", - "PCIE_IMUX28_L_19", - "PCIE_WW4END3_19", - "PCIE_CFGDSFUNCTIONNUMBER2", - "PCIE_IMUX27_R_15", - "PCIE_FAN6_R_3", - "PCIE_SE4BEG0_12", - "PCIE_LOGIC_OUTS_B14_R_12", - "PCIE_BYP6_R_18", - "PCIE_SW4END1_13", - "PCIE_PIPETX2CHARISK0", - "PCIE_MIMRXWADDR1", - "PCIE_FAN6_L_7", - "PCIE_PIPERX6DATA5", - "PCIE_IMUX22_L_10", - "PCIE_CMSTICKYRSTN", - "PCIE_SW2A0_4", - "PCIE_DRPDO1", - "PCIE_TRNFCPD0", - "PCIE_IMUX19_L_9", - "PCIE_TRNRD25", - "PCIE_IMUX39_R_3", - "PCIE_BYP1_R_5", - "PCIE_IMUX42_R_15", - "PCIE_BYP4_L_19", - "PCIE_MIMRXWADDR9", - "PCIE_LOGIC_OUTS_B14_R_18", - "PCIE_ER1BEG3_17", - "PCIE_WW4A1_10", - "PCIE_SE4BEG0_5", - "PCIE_PIPETX1ELECIDLE", - "PCIE_IMUX3_L_7", - "PCIE_FAN5_R_0", - "PCIE_WW2END3_9", - "PCIE_TRNRBARHIT0", - "PCIE_TRNTDLLPDATA18", - "PCIE_SE2A0_18", - "PCIE_NE4C0_14", - "PCIE_IMUX6_L_0", - "PCIE_EE4C3_16", - "PCIE_TRNTBUFAV0", - "PCIE_PIPETX0DATA6", - "PCIE_IMUX37_L_18", - "PCIE_LOGIC_OUTS_B9_L_16", - "PCIE_WW4END3_17", - "PCIE_IMUX28_L_13", - "PCIE_LOGIC_OUTS_B3_R_10", - "PCIE_IMUX15_L_12", - "PCIE_LH10_2", - "PCIE_IMUX2_L_10", - "PCIE_LOGIC_OUTS_B15_L_17", - "PCIE_BLOCK_OUTS_B2_L_2", - "PCIE_LOGIC_OUTS_B5_L_19", - "PCIE_IMUX9_R_0", - "PCIE_WL1END2_9", - "PCIE_WW4END1_12", - "PCIE_BYP6_L_16", - "PCIE_LOGIC_OUTS_B6_L_14", - "PCIE_NW4A1_14", - "PCIE_FAN3_R_1", - "PCIE_TRNTDLLPDATA14", - "PCIE_NE4BEG2_6", - "PCIE_NW4A1_5", - "PCIE_PLLINKGEN2CAP", - "PCIE_LH12_12", - "PCIE_SW4END1_2", - "PCIE_IMUX38_L_1", - "PCIE_LOGIC_OUTS_B15_R_7", - "PCIE_SE2A3_5", - "PCIE_IMUX6_R_6", - "PCIE_LOGIC_OUTS_B15_R_19", - "PCIE_EE4A1_5", - "PCIE_NW2A3_2", - "PCIE_CLK1_L_8", - "PCIE_LOGIC_OUTS_B8_R_8", - "PCIE_WR1END2_18", - "PCIE_EE4A2_19", - "PCIE_IMUX8_L_6", - "PCIE_LH2_4", - "PCIE_IMUX3_L_15", - "PCIE_SE2A2_7", - "PCIE_IMUX44_R_3", - "PCIE_DLRSTN", - "PCIE_WW2A1_9", - "PCIE_ER1BEG1_3", - "PCIE_NW2A3_3", - "PCIE_IMUX34_L_7", - "PCIE_BYP7_L_14", - "PCIE_IMUX42_L_18", - "PCIE_IMUX33_R_0", - "PCIE_CFGMGMTDI30", - "PCIE_MIMTXRADDR4", - "PCIE_EE4A3_4", - "PCIE_NW4A0_7", - "PCIE_SW4END2_9", - "PCIE_IMUX33_R_18", - "PCIE_LOGIC_OUTS_B16_R_1", - "PCIE_IMUX19_L_7", - "PCIE_IMUX9_R_12", - "PCIE_MIMRXRDATA22", - "PCIE_FAN4_R_7", - "PCIE_DBGVECB44", - "PCIE_IMUX3_L_13", - "PCIE_IMUX36_R_9", - "PCIE_BYP6_R_15", - "PCIE_BYP2_R_8", - "PCIE_BYP3_L_1", - "PCIE_PIPETX1POWERDOWN1", - "PCIE_IMUX6_L_16", - "PCIE_BLOCK_OUTS_B3_L_0", - "PCIE_CFGPMSENDPMETON", - "PCIE_TRNRD73", - "PCIE_LOGIC_OUTS_B2_R_0", - "PCIE_MIMTXRDATA35", - "PCIE_DRPDI0", - "PCIE_IMUX5_L_11", - "PCIE_WW4END3_11", - "PCIE_IMUX7_R_15", - "PCIE_LOGIC_OUTS_B19_R_0", - "PCIE_LOGIC_OUTS_B6_L_13", - "PCIE_IMUX34_L_4", - "PCIE_LOGIC_OUTS_B19_R_12", - "PCIE_WR1END3_2", - "PCIE_SE4C2_10", - "PCIE_IMUX8_R_4", - "PCIE_BYP4_R_3", - "PCIE_IMUX20_L_9", - "PCIE_IMUX1_R_8", - "PCIE_CTRL1_L_15", - "PCIE_LOGIC_OUTS_B22_R_8", - "PCIE_WW4B0_10", - "PCIE_BYP5_L_11", - "PCIE_LOGIC_OUTS_B23_L_7", - "PCIE_LOGIC_OUTS_B18_L_6", - "PCIE_EE4A1_2", - "PCIE_WW4END0_3", - "PCIE_BYP5_R_1", - "PCIE_PIPERX7PHYSTATUS", - "PCIE_WL1END1_3", - "PCIE_TRNTD32", - "PCIE_PIPERX7DATA13", - "PCIE_WW4B2_16", - "PCIE_SW2A2_7", - "PCIE_ER1BEG3_12", - "PCIE_PIPETX1COMPLIANCE", - "PCIE_LOGIC_OUTS_B19_R_14", - "PCIE_WW4C1_0", - "PCIE_LOGIC_OUTS_B16_L_11", - "PCIE_TRNREOF", - "PCIE_IMUX5_R_1", - "PCIE_LOGIC_OUTS_B7_L_12", - "PCIE_IMUX17_R_15", - "PCIE_IMUX22_R_1", - "PCIE_LH11_4", - "PCIE_DBGMODE0", - "PCIE_BYP7_R_12", - "PCIE_XILUNCONNOUT21", - "PCIE_PIPETX3DATA7", - "PCIE_DBGVECA59", - "PCIE_NE4BEG1_12", - "PCIE_LL2SENDENTERL1", - "PCIE_WR1END2_11", - "PCIE_IMUX5_L_3", - "PCIE_IMUX8_R_1", - "PCIE_IMUX2_L_19", - "PCIE_CFGLINKSTATUSDLLACTIVE", - "PCIE_MIMTXRDATA65", - "PCIE_MIMRXWDATA18", - "PCIE_EE4A2_6", - "PCIE_IMUX29_R_2", - "PCIE_PIPETX1DATA3", - "PCIE_IMUX44_L_9", - "PCIE_TL2ERRHDR50", - "PCIE_IMUX2_L_5", - "PCIE_FAN4_R_1", - "PCIE_SW2A2_1", - "PCIE_EE4BEG1_2", - "PCIE_TRNFCPD6", - "PCIE_IMUX42_L_10", - "PCIE_IMUX8_R_10", - "PCIE_BLOCK_OUTS_B0_R_7", - "PCIE_WR1END3_16", - "PCIE_CFGERRAERHEADERLOG4", - "PCIE_DBGSCLRI", - "PCIE_WW4A1_11", - "PCIE_IMUX4_R_19", - "PCIE_IMUX35_R_4", - "PCIE_IMUX14_L_9", - "PCIE_IMUX34_L_11", - "PCIE_IMUX27_L_9", - "PCIE_NW4A2_17", - "PCIE_BYP3_L_9", - "PCIE_MIMRXWDATA7", - "PCIE_TRNTDLLPDATA16", - "PCIE_BLOCK_OUTS_B3_L_2", - "PCIE_LOGIC_OUTS_B9_L_17", - "PCIE_FAN6_R_5", - "PCIE_NE4C3_3", - "PCIE_IMUX16_L_17", - "PCIE_FAN1_L_9", - "PCIE_BYP4_R_6", - "PCIE_LOGIC_OUTS_B5_R_12", - "PCIE_PIPERX2STATUS0", - "PCIE_PIPERX2DATA3", - "PCIE_SW4A0_10", - "PCIE_DBGVECA50", - "PCIE_IMUX9_R_10", - "PCIE_NW2A2_1", - "PCIE_MIMRXWDATA64", - "PCIE_IMUX15_L_0", - "PCIE_IMUX27_R_14", - "PCIE_NW4END2_19", - "PCIE_LOGIC_OUTS_B18_R_7", - "PCIE_IMUX44_L_13", - "PCIE_CFGMGMTDI6", - "PCIE_PIPETX2DATA13", - "PCIE_DBGVECA35", - "PCIE_PLLTSSMSTATE1", - "PCIE_SW4END0_10", - "PCIE_WW2END1_16", - "PCIE_TRNRD20", - "PCIE_CFGMGMTDI21", - "PCIE_IMUX21_R_9", - "PCIE_CFGDSN36", - "PCIE_NE4C2_3", - "PCIE_IMUX37_L_2", - "PCIE_EE2BEG0_18", - "PCIE_EE4C1_2", - "PCIE_IMUX21_L_19", - "PCIE_EE4C0_11", - "PCIE_LOGIC_OUTS_B6_L_11", - "PCIE_LOGIC_OUTS_B12_L_3", - "PCIE_WL1END0_0", - "PCIE_IMUX29_L_7", - "PCIE_IMUX16_R_18", - "PCIE_BLOCK_OUTS_B0_L_10", - "PCIE_LOGIC_OUTS_B17_R_10", - "PCIE_IMUX32_R_2", - "PCIE_WW4A3_3", - "PCIE_SW2A0_10", - "PCIE_MIMTXWDATA48", - "PCIE_MONITOR_N_8", - "PCIE_CFGMGMTDWADDR9", - "PCIE_CFGMSGDATA7", - "PCIE_LOGIC_OUTS_B15_R_0", - "PCIE_EE2A3_17", - "PCIE_DBGVECA7", - "PCIE_EL1BEG3_1", - "PCIE_WL1END0_19", - "PCIE_CFGERRTLPCPLHEADER7", - "PCIE_TRNTD7", - "PCIE_NE4C3_2", - "PCIE_WW4B2_15", - "PCIE_LH2_1", - "PCIE_LOGIC_OUTS_B11_R_1", - "PCIE_CFGERRAERHEADERLOG108", - "PCIE_LOGIC_OUTS_B18_L_16", - "PCIE_WW4C0_15", - "PCIE_IMUX3_L_3", - "PCIE_SW2A3_9", - "PCIE_WR1END0_12", - "PCIE_MIMRXRDATA14", - "PCIE_EL1BEG0_0", - "PCIE_FAN2_R_0", - "PCIE_CFGERRAERHEADERLOG86", - "PCIE_BLOCK_OUTS_B0_R_5", - "PCIE_DBGVECA44", - "PCIE_TL2ERRHDR47", - "PCIE_ER1BEG3_6", - "PCIE_EE4BEG0_2", - "PCIE_IMUX24_L_15", - "PCIE_IMUX26_L_6", - "PCIE_LH11_6", - "PCIE_WW4A3_11", - "PCIE_CFGMGMTDO15", - "PCIE_NW2A1_1", - "PCIE_WW4END0_11", - "PCIE_EE2A0_12", - "PCIE_BLOCK_OUTS_B2_R_1", - "PCIE_WW4B2_11", - "PCIE_LOGIC_OUTS_B18_L_19", - "PCIE_WW2A1_6", - "PCIE_IMUX35_L_12", - "PCIE_NE4BEG2_16", - "PCIE_IMUX37_L_0", - "PCIE_LOGIC_OUTS_B11_L_9", - "PCIE_LOGIC_OUTS_B15_R_15", - "PCIE_CFGMSGDATA13", - "PCIE_WR1END2_13", - "PCIE_SW4A1_10", - "PCIE_WW4C2_5", - "PCIE_IMUX30_L_8", - "PCIE_LOGIC_OUTS_B10_R_5", - "PCIE_IMUX23_L_10", - "PCIE_NW4A2_4", - "PCIE_CFGINTERRUPTMMENABLE2", - "PCIE_IMUX31_R_17", - "PCIE_WW4B1_2", - "PCIE_BYP2_L_4", - "PCIE_IMUX18_R_8", - "PCIE_TRNTD127", - "PCIE_TRNFCPD9", - "PCIE_IMUX40_L_7", - "PCIE_IMUX42_R_6", - "PCIE_NE2A1_18", - "PCIE_NE4BEG3_18", - "PCIE_LL2LINKSTATUS4", - "PCIE_TRNTDLLPDATA28", - "PCIE_WW2A3_14", - "PCIE_TRNRD60", - "PCIE_IMUX15_L_19", - "PCIE_LOGIC_OUTS_B9_R_15", - "PCIE_IMUX18_R_2", - "PCIE_LOGIC_OUTS_B7_L_1", - "PCIE_TRNTD12", - "PCIE_LH5_5", - "PCIE_IMUX0_R_10", - "PCIE_FAN5_R_17", - "PCIE_SE4C3_6", - "PCIE_SE4BEG1_15", - "PCIE_BYP6_L_19", - "PCIE_NE2A3_12", - "PCIE_WW4A0_0", - "PCIE_WR1END3_4", - "PCIE_IMUX4_L_6", - "PCIE_IMUX8_R_2", - "PCIE_IMUX4_L_17", - "PCIE_FAN0_L_3", - "PCIE_BYP0_L_9", - "PCIE_IMUX11_R_16", - "PCIE_IMUX39_R_18", - "PCIE_CFGVENDID0", - "PCIE_LOGIC_OUTS_B1_R_3", - "PCIE_PL2DIRECTEDLSTATE2", - "PCIE_WW2END1_17", - "PCIE_ER1BEG2_10", - "PCIE_LH8_9", - "PCIE_MIMTXWDATA27", - "PCIE_IMUX39_L_13", - "PCIE_IMUX25_R_1", - "PCIE_SE4BEG2_6", - "PCIE_WW4C1_10", - "PCIE_BYP0_R_14", - "PCIE_DBGVECA63", - "PCIE_IMUX44_L_19", - "PCIE_BYP3_L_13", - "PCIE_WW4B3_9", - "PCIE_WW2A1_4", - "PCIE_IMUX17_L_6", - "PCIE_IMUX24_L_12", - "PCIE_IMUX0_L_18", - "PCIE_EE4BEG0_4", - "PCIE_PIPERX2DATA0", - "PCIE_NE4BEG1_14", - "PCIE_CFGDSN32", - "PCIE_EDTBYPASS", - "PCIE_PIPETX1CHARISK1", - "PCIE_IMUX9_R_11", - "PCIE_EE4B1_9", - "PCIE_IMUX45_R_18", - "PCIE_IMUX35_R_19", - "PCIE_WL1END2_4", - "PCIE_IMUX19_R_5", - "PCIE_ER1BEG3_8", - "PCIE_WW4A1_15", - "PCIE_CFGPMFORCESTATE0", - "PCIE_IMUX37_L_8", - "PCIE_CFGMGMTDO7", - "PCIE_CFGERRTLPCPLHEADER16", - "PCIE_IMUX40_L_5", - "PCIE_NE2A2_19", - "PCIE_PIPERX2DATA12", - "PCIE_NE2A1_0", - "PCIE_IMUX45_R_9", - "PCIE_BYP1_R_2", - "PCIE_NW4END1_1", - "PCIE_MIMRXRDATA6", - "PCIE_TRNRD47", - "PCIE_PLDIRECTEDLINKAUTON", - "PCIE_PLLTSSMSTATE3", - "PCIE_WW4B1_7", - "PCIE_IMUX19_R_0", - "PCIE_TRNRD122", - "PCIE_WW4B2_0", - "PCIE_TRNTCFGGNT", - "PCIE_IMUX37_L_15", - "PCIE_LOGIC_OUTS_B20_L_14", - "PCIE_BYP2_R_19", - "PCIE_MIMRXWDATA10", - "PCIE_EE4A0_19", - "PCIE_TRNFCPH1", - "PCIE_PIPETXRCVRDET", - "PCIE_TRNRDLLPDATA21", - "PCIE_WW4A2_17", - "PCIE_EL1BEG0_8", - "PCIE_SW2A3_2", - "PCIE_TRNTD90", - "PCIE_LOGIC_OUTS_B21_R_14", - "PCIE_CFGMGMTDI23", - "PCIE_CFGSUBSYSID3", - "PCIE_TRNTD6", - "PCIE_LOGIC_OUTS_B0_R_14", - "PCIE_IMUX7_L_3", - "PCIE_CFGDSN37", - "PCIE_ER1BEG1_0", - "PCIE_XILUNCONNOUT20", - "PCIE_IMUX38_L_11", - "PCIE_FAN1_R_8", - "PCIE_IMUX13_R_7", - "PCIE_PIPERX4DATA3", - "PCIE_NW4END1_11", - "PCIE_LOGIC_OUTS_B7_L_3", - "PCIE_EE4B0_14", - "PCIE_BLOCK_OUTS_B2_L_5", - "PCIE_MIMTXRDATA14", - "PCIE_MIMRXRDATA61", - "PCIE_TRNRD62", - "PCIE_IMUX20_L_10", - "PCIE_SE4C0_13", - "PCIE_LOGIC_OUTS_B13_L_0", - "PCIE_IMUX32_L_2", - "PCIE_TRNTD119", - "PCIE_CTRL1_R_0", - "PCIE_IMUX40_L_18", - "PCIE_WW4C3_12", - "PCIE_MONITOR_N_10", - "PCIE_EE4B2_14", - "PCIE_IMUX22_L_11", - "PCIE_NE4BEG0_8", - "PCIE_IMUX15_R_9", - "PCIE_TRNTREM1", - "PCIE_EE2A2_12", - "PCIE_NE4C3_14", - "PCIE_SCANENABLEN", - "PCIE_LOGIC_OUTS_B10_L_3", - "PCIE_LH3_5", - "PCIE_IMUX36_L_16", - "PCIE_LOGIC_OUTS_B4_R_11", - "PCIE_IMUX19_R_2", - "PCIE_BYP6_L_5", - "PCIE_LH11_9", - "PCIE_EL1BEG3_9", - "PCIE_XILUNCONNOUT22", - "PCIE_IMUX41_L_18", - "PCIE_CFGERRAERHEADERLOG19", - "PCIE_MIMTXRDATA63", - "PCIE_NW2A1_14", - "PCIE_WL1END2_0", - "PCIE_WL1END1_9", - "PCIE_CTRL0_R_5", - "PCIE_WL1END1_0", - "PCIE_EE4BEG0_5", - "PCIE_WL1END0_6", - "PCIE_CFGDSN28", - "PCIE_IMUX30_L_13", - "PCIE_CFGDSN22", - "PCIE_LH1_14", - "PCIE_MIMTXRADDR6", - "PCIE_CFGERRAERHEADERLOG15", - "PCIE_EE2A0_6", - "PCIE_EE4B0_16", - "PCIE_FAN4_L_13", - "PCIE_EDTCHANNELSOUT6", - "PCIE_PIPERX2DATA14", - "PCIE_BLOCK_OUTS_B1_L_16", - "PCIE_NE4C1_7", - "PCIE_TRNTD84", - "PCIE_CFGERRAERHEADERLOGSETN", - "PCIE_NE2A0_2", - "PCIE_TL2ERRHDR39", - "PCIE_LOGIC_OUTS_B4_L_4", - "PCIE_LOGIC_OUTS_B18_L_9", - "PCIE_NE4C3_17", - "PCIE_ER1BEG3_10", - "PCIE_BYP0_R_16", - "PCIE_BYP2_L_14", - "PCIE_CFGLINKCONTROLCOMMONCLOCK", - "PCIE_IMUX1_R_1", - "PCIE_PLDBGVEC11", - "PCIE_BYP4_R_15", - "PCIE_IMUX8_L_18", - "PCIE_TRNFCNPH5", - "PCIE_LOGIC_OUTS_B6_L_9", - "PCIE_TRNTD28", - "PCIE_TRNTD16", - "PCIE_NW4END3_17", - "PCIE_BLOCK_OUTS_B3_L_9", - "PCIE_NE4C2_6", - "PCIE_FAN2_R_2", - "PCIE_MIMTXRDATA8", - "PCIE_NE2A3_4", - "PCIE_BLOCK_OUTS_B0_R_15", - "PCIE_WW4B3_10", - "PCIE_IMUX37_L_3", - "PCIE_BYP3_R_7", - "PCIE_IMUX28_R_7", - "PCIE_DBGVECA20", - "PCIE_LOGIC_OUTS_B20_L_19", - "PCIE_IMUX38_L_12", - "PCIE_SW4A2_11", - "PCIE_IMUX24_R_14", - "PCIE_SW4END1_1", - "PCIE_WW4C2_18", - "PCIE_TRNRDLLPDATA17", - "PCIE_SE4C1_10", - "PCIE_SE2A0_2", - "PCIE_IMUX46_R_13", - "PCIE_FAN0_L_8", - "PCIE_LOGIC_OUTS_B12_L_7", - "PCIE_IMUX6_R_0", - "PCIE_SE4C3_14", - "PCIE_IMUX44_R_19", - "PCIE_LOGIC_OUTS_B19_L_6", - "PCIE_SE4BEG3_11", - "PCIE_EDTSINGLEBYPASSCHAIN", - "PCIE_IMUX21_R_0", - "PCIE_EE4B3_9", - "PCIE_CFGERRAERHEADERLOG41", - "PCIE_SE2A2_17", - "PCIE_NW4A3_18", - "PCIE_DBGSCLRJ", - "PCIE_EE2BEG2_5", - "PCIE_SW4END3_0", - "PCIE_DRPDI15", - "PCIE_IMUX3_L_9", - "PCIE_EE4A1_3", - "PCIE_IMUX15_L_18", - "PCIE_MIMTXWDATA17", - "PCIE_IMUX24_L_13", - "PCIE_CLK1_R_0", - "PCIE_CFGMSGRECEIVEDUNLOCK", - "PCIE_IMUX35_L_0", - "PCIE_BYP3_R_16", - "PCIE_CFGERRAERHEADERLOG13", - "PCIE_EE2A1_11", - "PCIE_NE4C1_15", - "PCIE_IMUX4_R_11", - "PCIE_IMUX13_L_17", - "PCIE_BYP1_R_9", - "PCIE_FAN6_L_0", - "PCIE_LOGIC_OUTS_B18_R_19", - "PCIE_CFGMGMTDI0", - "PCIE_IMUX0_L_1", - "PCIE_BLOCK_OUTS_B2_R_5", - "PCIE_NE4BEG2_7", - "PCIE_FAN4_L_14", - "PCIE_IMUX34_R_10", - "PCIE_LH1_4", - "PCIE_IMUX42_L_14", - "PCIE_TRNRD3", - "PCIE_EE4BEG2_13", - "PCIE_LOGIC_OUTS_B13_R_11", - "PCIE_BYP2_L_13", - "PCIE_SW4END0_2", - "PCIE_NW4END2_13", - "PCIE_WW2END3_18", - "PCIE_FAN1_L_11", - "PCIE_TRNRD38", - "PCIE_IMUX19_L_6", - "PCIE_LOGIC_OUTS_B9_R_7", - "PCIE_CFGSUBSYSID5", - "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", - "PCIE_LOGIC_OUTS_B23_R_18", - "PCIE_PIPETX4DATA14", - "PCIE_CFGMGMTDO23", - "PCIE_TRNRD103", - "PCIE_EL1BEG3_14", - "PCIE_LOGIC_OUTS_B1_R_14", - "PCIE_MIMRXRDATA57", - "PCIE_CFGERRAERHEADERLOG33", - "PCIE_SE4C3_9", - "PCIE_WW4END2_2", - "PCIE_FAN7_R_7", - "PCIE_FAN4_L_8", - "PCIE_CLK1_L_7", - "PCIE_IMUX31_R_8", - "PCIE_IMUX25_R_13", - "PCIE_IMUX25_L_3", - "PCIE_TRNTD34", - "PCIE_WR1END2_3", - "PCIE_TRNTD125", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", - "PCIE_CFGPMCSRPOWERSTATE1", - "PCIE_IMUX1_L_12", - "PCIE_BYP4_R_2", - "PCIE_BLOCK_OUTS_B3_R_3", - "PCIE_LOGIC_OUTS_B14_L_4", - "PCIE_EL1BEG1_19", - "PCIE_BYP7_L_4", - "PCIE_WW4B3_7", - "PCIE_FAN4_L_5", - "PCIE_IMUX14_R_12", - "PCIE_SW4A0_8", - "PCIE_TRNRD81", - "PCIE_DRPADDR0", - "PCIE_SW4A1_8", - "PCIE_IMUX1_R_9", - "PCIE_MONITOR_P_0", - "PCIE_PIPERX1POLARITY", - "PCIE_IMUX38_R_12", - "PCIE_EE4BEG3_11", - "PCIE_IMUX46_L_3", - "PCIE_CFGERRTLPCPLHEADER33", - "PCIE_IMUX2_L_2", - "PCIE_EE4A0_10", - "PCIE_PIPETX7CHARISK0", - "PCIE_PL2RXPMSTATE0", - "PCIE_XILUNCONNOUT17", - "PCIE_IMUX26_R_9", - "PCIE_LOGIC_OUTS_B12_R_16", - "PCIE_LOGIC_OUTS_B14_L_3", - "PCIE_IMUX21_R_12", - "PCIE_ER1BEG3_9", - "PCIE_FAN4_L_4", - "PCIE_CFGPMRCVASREQL1N", - "PCIE_IMUX6_R_16", - "PCIE_BYP0_L_10", - "PCIE_LH3_17", - "PCIE_SW2A1_6", - "PCIE_FAN7_L_18", - "PCIE_MIMTXWDATA42", - "PCIE_IMUX30_R_11", - "PCIE_SE2A1_8", - "PCIE_NW4END0_16", - "PCIE_NE4BEG1_15", - "PCIE_LH2_8", - "PCIE_CFGERRAERHEADERLOG100", - "PCIE_IMUX23_R_16", - "PCIE_CLK0_L_0", - "PCIE_EE4A0_5", - "PCIE_IMUX34_R_2", - "PCIE_BYP1_L_7", - "PCIE_CFGVENDID6", - "PCIE_WW4A2_14", - "PCIE_DBGVECB35", - "PCIE_CFGMSGRECEIVEDASSERTINTA", - "PCIE_CFGMSGRECEIVEDASSERTINTD", - "PCIE_CFGMGMTDO2", - "PCIE_WW2A1_18", - "PCIE_IMUX4_L_3", - "PCIE_IMUX23_R_6", - "PCIE_WW4END2_3", - "PCIE_WW4END1_15", - "PCIE_CFGERRTLPCPLHEADER36", - "PCIE_SE2A1_5", - "PCIE_IMUX45_L_9", - "PCIE_NW4END0_18", - "PCIE_NE2A2_13", - "PCIE_ER1BEG0_10", - "PCIE_LOGIC_OUTS_B16_L_3", - "PCIE_SW4A0_0", - "PCIE_NE4C1_14", - "PCIE_BYP3_R_13", - "PCIE_DBGVECB45", - "PCIE_MIMRXWDATA31", - "PCIE_LOGIC_OUTS_B3_L_3", - "PCIE_IMUX28_R_9", - "PCIE_IMUX34_R_19", - "PCIE_LOGIC_OUTS_B9_L_15", - "PCIE_LOGIC_OUTS_B17_R_5", - "PCIE_EE4BEG0_7", - "PCIE_FAN0_L_2", - "PCIE_EDTCHANNELSIN3", - "PCIE_CLK1_R_3", - "PCIE_IMUX17_L_8", - "PCIE_IMUX3_L_17", - "PCIE_LOGIC_OUTS_B17_L_4", - "PCIE_WW4C2_0", - "PCIE_TRNTDLLPDATA7", - "PCIE_PIPERX2DATA11", - "PCIE_IMUX41_R_13", - "PCIE_IMUX38_L_6", - "PCIE_LOGIC_OUTS_B22_L_18", - "PCIE_WR1END0_0", - "PCIE_WW4B3_8", - "PCIE_IMUX30_R_0", - "PCIE_IMUX15_L_9", - "PCIE_IMUX7_L_13", - "PCIE_SE4BEG2_14", - "PCIE_PIPERX4PHYSTATUS", - "PCIE_IMUX46_L_5", - "PCIE_NE4BEG3_6", - "PCIE_TRNRD119", - "PCIE_TRNRD91", - "PCIE_EE2BEG3_1", - "PCIE_IMUX15_R_19", - "PCIE_LOGIC_OUTS_B6_R_1", - "PCIE_MIMTXWDATA19", - "PCIE_PIPETX6DATA11", - "PCIE_PIPERX1DATA2", - "PCIE_CFGERRAERHEADERLOG47", - "PCIE_FAN6_R_9", - "PCIE_DBGVECB33", - "PCIE_IMUX19_L_18", - "PCIE_IMUX29_R_6", - "PCIE_NE4C2_10", - "PCIE_CFGINTERRUPTDO0", - "PCIE_LOGIC_OUTS_B5_L_13", - "PCIE_WW4B0_6", - "PCIE_LOGIC_OUTS_B18_L_14", - "PCIE_CFGERRTLPCPLHEADER32", - "PCIE_TRNRDLLPDATA52", - "PCIE_IMUX3_R_1", - "PCIE_EE4BEG2_16", - "PCIE_IMUX1_R_18", - "PCIE_IMUX18_R_9", - "PCIE_NW4A1_16", - "PCIE_CFGDSN38", - "PCIE_BYP3_R_17", - "PCIE_IMUX14_R_14", - "PCIE_EE2A2_0", - "PCIE_EE4C1_7", - "PCIE_WW4C3_15", - "PCIE_WW2END2_2", - "PCIE_BYP4_L_14", - "PCIE_IMUX46_L_6", - "PCIE_LH1_12", - "PCIE_WR1END1_9", - "PCIE_EE4B1_13", - "PCIE_FAN3_R_13", - "PCIE_WW4END1_4", - "PCIE_IMUX39_R_9", - "PCIE_BLOCK_OUTS_B1_L_0", - "PCIE_WW2A3_13", - "PCIE_LOGIC_OUTS_B7_R_17", - "PCIE_NW2A2_9", - "PCIE_DBGVECB19", - "PCIE_IMUX5_L_14", - "PCIE_EE4C0_6", - "PCIE_MIMTXRADDR9", - "PCIE_PIPERX0DATA9", - "PCIE_PIPETX1DATA4", - "PCIE_FAN0_R_6", - "PCIE_IMUX3_L_0", - "PCIE_CTRL0_R_2", - "PCIE_NW4END3_15", - "PCIE_BLOCK_OUTS_B0_L_3", - "PCIE_LOGIC_OUTS_B14_L_17", - "PCIE_EE2BEG3_19", - "PCIE_NW4A3_16", - "PCIE_IMUX7_R_7", - "PCIE_SE2A2_11", - "PCIE_WW4C3_19", - "PCIE_CFGERRAERHEADERLOG122", - "PCIE_CLK1_R_12", - "PCIE_IMUX43_L_5", - "PCIE_TRNTD47", - "PCIE_IMUX11_L_11", - "PCIE_WW4A3_6", - "PCIE_FAN4_L_12", - "PCIE_DBGVECB26", - "PCIE_DBGVECB61", - "PCIE_MIMRXWDATA35", - "PCIE_CTRL1_L_17", - "PCIE_MIMRXRADDR1", - "PCIE_TRNTD99", - "PCIE_PIPETX5DATA3", - "PCIE_IMUX23_R_19", - "PCIE_LOGIC_OUTS_B0_L_16", - "PCIE_CFGDSN8", - "PCIE_SW4END3_4", - "PCIE_WW2END0_7", - "PCIE_IMUX19_R_13", - "PCIE_TRNRDLLPDATA40", - "PCIE_ER1BEG2_8", - "PCIE_WW4END3_9", - "PCIE_DBGVECA0", - "PCIE_TL2ERRHDR6", - "PCIE_LOGIC_OUTS_B6_R_7", - "PCIE_TRNRDLLPDATA47", - "PCIE_IMUX14_L_4", - "PCIE_FAN2_L_19", - "PCIE_LOGIC_OUTS_B15_R_16", - "PCIE_PIPETX1POWERDOWN0", - "PCIE_IMUX28_R_5", - "PCIE_MIMRXRDATA16", - "PCIE_LOGIC_OUTS_B15_L_19", - "PCIE_EE2A0_10", - "PCIE_NW4END2_15", - "PCIE_WW4C0_2", - "PCIE_PIPETX6DATA7", - "PCIE_PIPERX7VALID", - "PCIE_PLRECEIVEDHOTRST", - "PCIE_TRNRBARHIT1", - "PCIE_BYP5_R_5", - "PCIE_BYP6_R_10", - "PCIE_NE4C3_19", - "PCIE_CTRL1_R_14", - "PCIE_CFGERRAERHEADERLOG55", - "PCIE_IMUX11_L_14", - "PCIE_PIPERX2DATA13", - "PCIE_BLOCK_OUTS_B1_R_18", - "PCIE_TRNFCNPD9", - "PCIE_LOGIC_OUTS_B5_R_13", - "PCIE_SE4C3_10", - "PCIE_LOGIC_OUTS_B1_R_4", - "PCIE_LOGIC_OUTS_B17_L_1", - "PCIE_CFGERRAERHEADERLOG80", - "PCIE_CFGPMFORCESTATE1", - "PCIE_WR1END3_17", - "PCIE_EL1BEG3_0", - "PCIE_EE4BEG2_6", - "PCIE_PIPETXMARGIN1", - "PCIE_MIMRXRDATA44", - "PCIE_EE2A0_16", - "PCIE_IMUX41_L_17", - "PCIE_LOGIC_OUTS_B16_L_1", - "PCIE_LOGIC_OUTS_B7_R_11", - "PCIE_CFGPMCSRPOWERSTATE0", - "PCIE_MIMTXWDATA62", - "PCIE_CTRL1_R_4", - "PCIE_IMUX46_R_0", - "PCIE_IMUX45_L_17", - "PCIE_LH10_19", - "PCIE_LOGIC_OUTS_B11_R_11", - "PCIE_SW4A2_10", - "PCIE_MIMRXWADDR8", - "PCIE_TRNFCPD4", - "PCIE_LOGIC_OUTS_B12_R_18", - "PCIE_NW4A2_13", - "PCIE_MIMTXRDATA26", - "PCIE_IMUX5_R_9", - "PCIE_LOGIC_OUTS_B4_L_15", - "PCIE_IMUX19_L_3", - "PCIE_IMUX44_L_18", - "PCIE_CFGINTERRUPTASSERTN", - "PCIE_NE4C2_4", - "PCIE_TRNTDLLPDATA31", - "PCIE_EE4A3_0", - "PCIE_IMUX10_L_7", - "PCIE_CFGDSN20", - "PCIE_CFGDEVID10", - "PCIE_LOGIC_OUTS_B20_R_4", - "PCIE_PIPERX7DATA2", - "PCIE_EE4B1_4", - "PCIE_IMUX42_L_17", - "PCIE_CFGERRAERHEADERLOG101", - "PCIE_BYP5_L_19", - "PCIE_WR1END0_10", - "PCIE_LOGIC_OUTS_B23_R_13", - "PCIE_WW4A3_17", - "PCIE_TRNRDLLPDATA28", - "PCIE_BYP7_L_6", - "PCIE_BYP6_L_15", - "PCIE_CFGDSN57", - "PCIE_CFGERRTLPCPLHEADER45", - "PCIE_BYP7_R_18", - "PCIE_IMUX20_R_7", - "PCIE_PL2RXPMSTATE1", - "PCIE_LOGIC_OUTS_B13_L_14", - "PCIE_FAN1_R_7", - "PCIE_IMUX10_R_19", - "PCIE_IMUX0_L_15", - "PCIE_FAN7_R_9", - "PCIE_SW2A3_6", - "PCIE_SE4BEG1_2", - "PCIE_CFGDSN2", - "PCIE_CFGERRTLPCPLHEADER5", - "PCIE_WW2A0_3", - "PCIE_BLOCK_OUTS_B1_R_6", - "PCIE_WW4END3_3", - "PCIE_IMUX2_L_15", - "PCIE_IMUX35_R_0", - "PCIE_EE2BEG0_14", - "PCIE_LOGIC_OUTS_B8_R_16", - "PCIE_LOGIC_OUTS_B8_R_11", - "PCIE_SE4C2_5", - "PCIE_CFGSUBSYSVENDID4", - "PCIE_PIPERX0DATA11", - "PCIE_DBGVECA16", - "PCIE_IMUX43_L_2", - "PCIE_LH7_12", - "PCIE_LOGIC_OUTS_B7_R_2", - "PCIE_LH11_12", - "PCIE_WW4END3_2", - "PCIE_IMUX9_R_7", - "PCIE_IMUX1_R_14", - "PCIE_EE4A2_12", - "PCIE_TRNFCSEL2", - "PCIE_IMUX12_R_18", - "PCIE_WW2A0_0", - "PCIE_WW2A2_15", - "PCIE_PIPERX5STATUS1", - "PCIE_CFGROOTCONTROLSYSERRFATALERREN", - "PCIE_IMUX37_L_17", - "PCIE_LOGIC_OUTS_B10_L_0", - "PCIE_NE4C3_0", - "PCIE_IMUX18_L_5", - "PCIE_IMUX47_R_14", - "PCIE_XILUNCONNOUT14", - "PCIE_SW2A2_13", - "PCIE_SW4A2_0", - "PCIE_LOGIC_OUTS_B8_L_5", - "PCIE_BYP1_L_10", - "PCIE_CFGERRAERHEADERLOG60", - "PCIE_IMUX7_R_13", - "PCIE_LOGIC_OUTS_B19_L_0", - "PCIE_IMUX39_L_17", - "PCIE_IMUX21_L_8", - "PCIE_IMUX20_R_19", - "PCIE_CFGERRAERHEADERLOG20", - "PCIE_LOGIC_OUTS_B21_L_3", - "PCIE_MONITOR_N_0", - "PCIE_IMUX14_L_6", - "PCIE_CFGREVID6", - "PCIE_IMUX33_L_13", - "PCIE_WW4END2_8", - "PCIE_EE2A2_11", - "PCIE_FAN1_L_2", - "PCIE_WW4END3_7", - "PCIE_ER1BEG1_17", - "PCIE_TL2ERRHDR37", - "PCIE_CFGSUBSYSVENDID11", - "PCIE_MIMRXWADDR10", - "PCIE_NW4A1_11", - "PCIE_LOGIC_OUTS_B18_R_11", - "PCIE_LOGIC_OUTS_B2_R_6", - "PCIE_IMUX20_L_8", - "PCIE_EE2BEG0_11", - "PCIE_BYP2_R_13", - "PCIE_IMUX47_L_6", - "PCIE_FAN7_R_3", - "PCIE_IMUX2_R_1", - "PCIE_TRNTDLLPDATA1", - "PCIE_DRPDI13", - "PCIE_WW4C3_1", - "PCIE_LH5_17", - "PCIE_EE2BEG3_8", - "PCIE_LOGIC_OUTS_B11_L_11", - "PCIE_NW4END3_3", - "PCIE_IMUX9_L_17", - "PCIE_SYSRSTN", - "PCIE_LOGIC_OUTS_B20_R_18", - "PCIE_BYP5_L_3", - "PCIE_NW2A2_11", - "PCIE_EE2BEG0_12", - "PCIE_EL1BEG2_3", - "PCIE_LOGIC_OUTS_B8_L_19", - "PCIE_NW4A0_17", - "PCIE_WW2A0_1", - "PCIE_WL1END1_14", - "PCIE_MIMRXWDATA9", - "PCIE_IMUX41_R_2", - "PCIE_LOGIC_OUTS_B6_L_15", - "PCIE_WW2END0_8", - "PCIE_FAN6_L_5", - "PCIE_BYP7_R_7", - "PCIE_LOGIC_OUTS_B19_L_12", - "PCIE_CFGMSGRECEIVEDERRCOR", - "PCIE_PIPERX4CHARISK0", - "PCIE_CFGERRAERHEADERLOG32", - "PCIE_IMUX29_R_11", - "PCIE_DBGVECB9", - "PCIE_CFGDSN0", - "PCIE_LOGIC_OUTS_B17_R_13", - "PCIE_IMUX40_R_8", - "PCIE_SE4C0_11", - "PCIE_PL2SUSPENDOK", - "PCIE_LOGIC_OUTS_B10_R_0", - "PCIE_NW2A3_12", - "PCIE_WR1END2_19", - "PCIE_IMUX4_L_11", - "PCIE_EL1BEG0_1", - "PCIE_MIMRXRDATA29", - "PCIE_IMUX37_L_1", - "PCIE_PIPETX6CHARISK1", - "PCIE_IMUX45_R_12", - "PCIE_IMUX32_L_15", - "PCIE_WW2A3_7", - "PCIE_TRNFCPD7", - "PCIE_EE2A0_3", - "PCIE_BLOCK_OUTS_B0_L_13", - "PCIE_LH7_19", - "PCIE_LOGIC_OUTS_B2_R_12", - "PCIE_LH5_4", - "PCIE_LOGIC_OUTS_B2_R_18", - "PCIE_SE2A3_17", - "PCIE_IMUX35_L_1", - "PCIE_BLOCK_OUTS_B0_L_18", - "PCIE_TRNTERRDROP", - "PCIE_LOGIC_OUTS_B8_R_0", - "PCIE_IMUX39_L_9", - "PCIE_EE4C2_13", - "PCIE_PIPERX6STATUS2", - "PCIE_EE4C3_18", - "PCIE_IMUX30_R_14", - "PCIE_IMUX10_R_15", - "PCIE_LOGIC_OUTS_B16_R_18", - "PCIE_EE4C2_1", - "PCIE_CFGERRAERHEADERLOG90", - "PCIE_TRNTDLLPDATA20", - "PCIE_TRNFCCPLH0", - "PCIE_NE4C1_0", - "PCIE_IMUX45_R_16", - "PCIE_TRNFCCPLD6", - "PCIE_DBGVECA57", - "PCIE_IMUX13_L_6", - "PCIE_TRNTD35", - "PCIE_FAN4_L_6", - "PCIE_LOGIC_OUTS_B2_L_12", - "PCIE_LOGIC_OUTS_B5_R_11", - "PCIE_WR1END2_1", - "PCIE_TRNFCCPLD9", - "PCIE_CLK0_L_8", - "PCIE_TRNTD51", - "PCIE_LOGIC_OUTS_B1_R_8", - "PCIE_BLOCK_OUTS_B1_R_14", - "PCIE_SW4A1_19", - "PCIE_IMUX46_L_17", - "PCIE_EL1BEG2_13", - "PCIE_BYP1_R_1", - "PCIE_FAN5_L_18", - "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", - "PCIE_NW2A2_16", - "PCIE_FAN1_R_2", - "PCIE_LOGIC_OUTS_B20_L_15", - "PCIE_CTRL1_L_4", - "PCIE_IMUX9_L_12", - "PCIE_EE4BEG2_11", - "PCIE_LOGIC_OUTS_B6_R_6", - "PCIE_PIPERX7DATA7", - "PCIE_EE2A2_4", - "PCIE_EE4C3_13", - "PCIE_SE4BEG0_8", - "PCIE_FAN4_L_3", - "PCIE_EE2A3_4", - "PCIE_LOGIC_OUTS_B3_R_15", - "PCIE_IMUX37_R_18", - "PCIE_MIMRXWDATA53", - "PCIE_CFGDEVID4", - "PCIE_SW2A1_17", - "PCIE_ER1BEG1_15", - "PCIE_LOGIC_OUTS_B19_L_16", - "PCIE_SW4A2_4", - "PCIE_CFGINTERRUPTSTATN", - "PCIE_EE2A1_13", - "PCIE_FAN0_L_14", - "PCIE_SW4END2_7", - "PCIE_CFGPMCSRPMESTATUS", - "PCIE_CFGERRTLPCPLHEADER42", - "PCIE_LOGIC_OUTS_B3_R_9", - "PCIE_FAN5_L_7", - "PCIE_LOGIC_OUTS_B13_R_18", - "PCIE_LOGIC_OUTS_B0_L_10", - "PCIE_BLOCK_OUTS_B1_L_18", - "PCIE_CFGMGMTDWADDR0", - "PCIE_DBGVECB24", - "PCIE_SE2A2_0", - "PCIE_IMUX2_R_15", - "PCIE_EL1BEG3_10", - "PCIE_PIPERX0DATA13", - "PCIE_IMUX41_L_9", - "PCIE_EE2BEG0_8", - "PCIE_LOGIC_OUTS_B5_L_10", - "PCIE_IMUX40_R_7", - "PCIE_PIPETX6DATA15", - "PCIE_IMUX12_L_16", - "PCIE_WL1END0_2", - "PCIE_BLOCK_OUTS_B0_R_8", - "PCIE_SE4BEG2_5", - "PCIE_BYP0_R_8", - "PCIE_IMUX0_L_14", - "PCIE_DBGVECB29", - "PCIE_NW2A3_16", - "PCIE_IMUX2_L_7", - "PCIE_LOGIC_OUTS_B7_L_18", - "PCIE_FAN5_R_2", - "PCIE_EE4A0_18", - "PCIE_IMUX43_R_5", - "PCIE_NW4END2_18", - "PCIE_CTRL0_L_17", - "PCIE_TRNRDLLPDATA35", - "PCIE_CFGMGMTDWADDR1", - "PCIE_BYP3_L_0", - "PCIE_IMUX30_L_15", - "PCIE_EE4B0_6", - "PCIE_LOGIC_OUTS_B3_R_2", - "PCIE_IMUX10_R_7", - "PCIE_IMUX46_L_0", - "PCIE_LOGIC_OUTS_B23_L_9", - "PCIE_IMUX7_L_7", - "PCIE_FAN5_R_13", - "PCIE_IMUX13_L_9", - "PCIE_BYP2_R_4", - "PCIE_EE4BEG3_6", - "PCIE_IMUX4_R_8", - "PCIE_IMUX31_R_14", - "PCIE_EL1BEG0_18", - "PCIE_SE4C2_2", - "PCIE_TRNRD68", - "PCIE_LOGIC_OUTS_B8_R_3", - "PCIE_EE4BEG2_3", - "PCIE_LOGIC_OUTS_B5_L_11", - "PCIE_LOGIC_OUTS_B12_L_11", - "PCIE_TRNRDLLPDATA31", - "PCIE_LOGIC_OUTS_B19_R_10", - "PCIE_IMUX44_L_15", - "PCIE_LOGIC_OUTS_B11_L_15", - "PCIE_LOGIC_OUTS_B6_L_5", - "PCIE_WW4C2_15", - "PCIE_IMUX8_L_8", - "PCIE_WR1END1_14", - "PCIE_WW2A1_14", - "PCIE_IMUX34_L_17", - "PCIE_EE2BEG2_18", - "PCIE_SE4C1_14", - "PCIE_CFGPORTNUMBER1", - "PCIE_EE4C3_8", - "PCIE_IMUX25_R_3", - "PCIE_TRNTD21", - "PCIE_IMUX20_R_4", - "PCIE_PIPERX4POLARITY", - "PCIE_TL2ERRHDR38", - "PCIE_LOGIC_OUTS_B19_R_1", - "PCIE_LH6_16", - "PCIE_LH12_2", - "PCIE_TRNTD42", - "PCIE_TL2PPMSUSPENDREQ", - "PCIE_IMUX32_R_14", - "PCIE_LOGIC_OUTS_B11_L_2", - "PCIE_IMUX12_L_5", - "PCIE_PIPERX3DATA14", - "PCIE_TRNRD59", - "PCIE_PIPETX1DATA8", - "PCIE_IMUX26_L_3", - "PCIE_TRNTDLLPDATA21", - "PCIE_EE4B1_8", - "PCIE_IMUX7_L_0", - "PCIE_CFGSUBSYSVENDID7", - "PCIE_CFGSUBSYSVENDID14", - "PCIE_TRNTD48", - "PCIE_MIMTXWDATA44", - "PCIE_IMUX8_R_8", - "PCIE_BLOCK_OUTS_B2_L_16", - "PCIE_BYP4_L_13", - "PCIE_IMUX47_R_8", - "PCIE_MIMTXRDATA46", - "PCIE_PIPETX3DATA1", - "PCIE_IMUX46_R_17", - "PCIE_IMUX38_R_13", - "PCIE_IMUX10_L_5", - "PCIE_SW4A2_5", - "PCIE_EE4B3_17", - "PCIE_LOGIC_OUTS_B8_L_1", - "PCIE_FAN7_L_9", - "PCIE_IMUX26_L_7", - "PCIE_EE4BEG2_19", - "PCIE_XILUNCONNOUT13", - "PCIE_NE4C1_12", - "PCIE_WW4A0_12", - "PCIE_LH9_8", - "PCIE_TRNTD112", - "PCIE_PIPERX6CHARISK0", - "PCIE_BYP7_L_7", - "PCIE_IMUX28_R_4", - "PCIE_WW4B0_8", - "PCIE_EE4A1_10", - "PCIE_TRNRD30", - "PCIE_TL2ERRHDR13", - "PCIE_TRNTD100", - "PCIE_LOGIC_OUTS_B10_L_6", - "PCIE_CTRL0_L_16", - "PCIE_TRNTD67", - "PCIE_BYP6_R_5", - "PCIE_TL2ERRHDR53", - "PCIE_NE4C0_10", - "PCIE_CFGSUBSYSVENDID2", - "PCIE_IMUX7_L_9", - "PCIE_NW4A1_0", - "PCIE_FAN3_R_0", - "PCIE_SW2A3_14", - "PCIE_NE4C2_17", - "PCIE_IMUX35_R_10", - "PCIE_CFGBRIDGESERREN", - "PCIE_NE4C3_11", - "PCIE_IMUX18_R_15", - "PCIE_WL1END3_19", - "PCIE_EE4B2_18", - "PCIE_DBGVECC10", - "PCIE_LOGIC_OUTS_B12_L_16", - "PCIE_EE2BEG0_5", - "PCIE_EE4A2_10", - "PCIE_EE2A2_2", - "PCIE_LL2LINKSTATUS0", - "PCIE_LOGIC_OUTS_B13_L_4", - "PCIE_EE4B0_8", - "PCIE_EE4BEG3_16", - "PCIE_TRNRDLLPDATA13", - "PCIE_TRNRD16", - "PCIE_SE4BEG3_7", - "PCIE_DBGVECA24", - "PCIE_LOGIC_OUTS_B15_L_6", - "PCIE_WL1END1_5", - "PCIE_IMUX27_L_4", - "PCIE_LOGIC_OUTS_B8_R_9", - "PCIE_EE4C1_6", - "PCIE_IMUX12_R_3", - "PCIE_IMUX16_R_1", - "PCIE_SE2A2_6", - "PCIE_EE2BEG2_14", - "PCIE_CLK0_L_12", - "PCIE_TRNRD102", - "PCIE_NE4BEG3_9", - "PCIE_FAN1_R_11", - "PCIE_LOGIC_OUTS_B8_L_2", - "PCIE_MIMTXWDATA59", - "PCIE_CTRL1_R_3", - "PCIE_WR1END3_11", - "PCIE_SW4END2_4", - "PCIE_IMUX1_L_6", - "PCIE_IMUX13_R_6", - "PCIE_PIPETX0CHARISK1", - "PCIE_IMUX29_L_9", - "PCIE_PIPERX7DATA10", - "PCIE_LOGIC_OUTS_B14_L_9", - "PCIE_LH3_1", - "PCIE_EE2A1_16", - "PCIE_IMUX7_R_9", - "PCIE_WW4C3_11", - "PCIE_DBGVECA4", - "PCIE_NW2A2_7", - "PCIE_IMUX15_L_15", - "PCIE_CFGERRTLPCPLHEADER12", - "PCIE_IMUX1_L_0", - "PCIE_MIMTXRDATA42", - "PCIE_NW4END1_18", - "PCIE_CFGVENDID12", - "PCIE_EE4A2_5", - "PCIE_SW4END1_6", - "PCIE_IMUX18_L_2", - "PCIE_XILUNCONNOUT32", - "PCIE_CFGERRCORN", - "PCIE_SE4C2_13", - "PCIE_IMUX8_L_7", - "PCIE_BYP1_L_19", - "PCIE_DBGVECA61", - "PCIE_LH4_17", - "PCIE_BYP7_L_18", - "PCIE_BYP2_L_8", - "PCIE_SE4BEG1_12", - "PCIE_CFGVCTCVCMAP6", - "PCIE_IMUX28_R_16", - "PCIE_FAN5_R_11", - "PCIE_XILUNCONNOUT11", - "PCIE_FAN2_L_5", - "PCIE_IMUX36_R_1", - "PCIE_IMUX26_L_2", - "PCIE_IMUX26_R_13", - "PCIE_SE4C1_5", - "PCIE_SW2A0_19", - "PCIE_IMUX44_L_14", - "PCIE_NW2A1_6", - "PCIE_CFGSUBSYSVENDID5", - "PCIE_CFGDSBUSNUMBER5", - "PCIE_LOGIC_OUTS_B12_R_4", - "PCIE_LOGIC_OUTS_B11_L_4", - "PCIE_LOGIC_OUTS_B10_L_5", - "PCIE_NW2A1_8", - "PCIE_BYP7_R_11", - "PCIE_IMUX32_L_19", - "PCIE_IMUX28_R_2", - "PCIE_SW2A3_19", - "PCIE_IMUX19_L_1", - "PCIE_WR1END2_10", - "PCIE_BYP7_R_10", - "PCIE_BYP4_R_16", - "PCIE_SE4BEG0_2", - "PCIE_LOGIC_OUTS_B11_L_3", - "PCIE_LOGIC_OUTS_B7_L_11", - "PCIE_CLK0_R_2", - "PCIE_CFGERRTLPCPLHEADER47", - "PCIE_WW2END2_18", - "PCIE_IMUX45_L_12", - "PCIE_LOGIC_OUTS_B21_L_10", - "PCIE_BLOCK_OUTS_B1_R_5", - "PCIE_LOGIC_OUTS_B23_L_1", - "PCIE_LOGIC_OUTS_B1_L_7", - "PCIE_MIMRXRDATA4", - "PCIE_CFGSUBSYSVENDID6", - "PCIE_IMUX37_R_7", - "PCIE_IMUX10_L_13", - "PCIE_WW2END1_7", - "PCIE_BYP3_R_14", - "PCIE_CFGMGMTDI10", - "PCIE_BYP6_R_4", - "PCIE_IMUX33_L_1", - "PCIE_PIPETX7DATA5", - "PCIE_SE4BEG0_18", - "PCIE_PIPETX0DATA0", - "PCIE_SW2A1_5", - "PCIE_LOGIC_OUTS_B20_R_17", - "PCIE_BLOCK_OUTS_B2_R_2", - "PCIE_TRNRD100", - "PCIE_IMUX19_L_16", - "PCIE_IMUX29_L_1", - "PCIE_TRNRDLLPDATA22", - "PCIE_DBGVECA41", - "PCIE_IMUX5_L_13", - "PCIE_IMUX11_R_3", - "PCIE_FAN2_R_8", - "PCIE_USERRSTN", - "PCIE_IMUX8_R_16", - "PCIE_NE4BEG3_7", - "PCIE_EE4BEG1_16", - "PCIE_IMUX42_R_9", - "PCIE_NE4BEG1_7", - "PCIE_LOGIC_OUTS_B22_L_10", - "PCIE_SE4BEG1_5", - "PCIE_PIPERX5PHYSTATUS", - "PCIE_IMUX27_R_12", - "PCIE_EE2A2_8", - "PCIE_LOGIC_OUTS_B22_R_5", - "PCIE_LOGIC_OUTS_B3_R_8", - "PCIE_CFGDEVID12", - "PCIE_LOGIC_OUTS_B12_R_10", - "PCIE_IMUX38_R_2", - "PCIE_LOGIC_OUTS_B19_L_8", - "PCIE_PIPETX6DATA2", - "PCIE_WW2END1_12", - "PCIE_IMUX0_R_11", - "PCIE_SW4END3_15", - "PCIE_LH11_8", - "PCIE_IMUX12_L_1", - "PCIE_BLOCK_OUTS_B1_L_4", - "PCIE_DBGVECB56", - "PCIE_SE2A3_6", - "PCIE_WW4END2_9", - "PCIE_IMUX24_R_15", - "PCIE_EL1BEG3_12", - "PCIE_IMUX0_R_18", - "PCIE_CFGDSN43", - "PCIE_IMUX1_R_12", - "PCIE_LOGIC_OUTS_B9_R_2", - "PCIE_CFGINTERRUPTMMENABLE1", - "PCIE_IMUX31_L_5", - "PCIE_CLK0_L_7", - "PCIE_BLOCK_OUTS_B2_R_16", - "PCIE_SW2A3_16", - "PCIE_LOGIC_OUTS_B17_L_5", - "PCIE_LOGIC_OUTS_B18_R_12", - "PCIE_LOGIC_OUTS_B18_L_8", - "PCIE_LOGIC_OUTS_B10_R_3", - "PCIE_IMUX3_R_18", - "PCIE_EDTCONFIGURATION", - "PCIE_LOGIC_OUTS_B17_L_13", - "PCIE_BLOCK_OUTS_B0_R_17", - "PCIE_LOGIC_OUTS_B22_R_7", - "PCIE_DRPEN", - "PCIE_IMUX6_L_13", - "PCIE_IMUX17_R_7", - "PCIE_SE2A2_3", - "PCIE_IMUX36_R_0", - "PCIE_IMUX32_L_8", - "PCIE_EE2BEG1_1", - "PCIE_IMUX35_L_14", - "PCIE_TRNTD77", - "PCIE_IMUX47_L_19", - "PCIE_CFGERRTLPCPLHEADER40", - "PCIE_CFGERRMCBLOCKEDN", - "PCIE_LOGIC_OUTS_B13_L_1", - "PCIE_CFGTRNPENDINGN", - "PCIE_PIPETX3POWERDOWN1", - "PCIE_IMUX43_L_7", - "PCIE_IMUX6_L_14", - "PCIE_LOGIC_OUTS_B2_L_11", - "PCIE_PIPETX3DATA3", - "PCIE_NE2A0_8", - "PCIE_TRNRD17", - "PCIE_PIPERX5DATA2", - "PCIE_IMUX1_R_7", - "PCIE_CFGREVID3", - "PCIE_IMUX7_L_11", - "PCIE_LH7_9", - "PCIE_WL1END3_17", - "PCIE_DBGVECA29", - "PCIE_WW2A1_0", - "PCIE_NE2A0_6", - "PCIE_TRNTD27", - "PCIE_TRNRD65", - "PCIE_WW2A2_9", - "PCIE_LOGIC_OUTS_B4_R_19", - "PCIE_IMUX17_L_9", - "PCIE_BYP1_L_5", - "PCIE_IMUX15_L_11", - "PCIE_DBGVECC9", - "PCIE_IMUX16_L_2", - "PCIE_ER1BEG0_16", - "PCIE_IMUX36_L_18", - "PCIE_SE2A2_1", - "PCIE_PIPERX1DATA11", - "PCIE_FAN2_L_1", - "PCIE_LOGIC_OUTS_B23_L_14", - "PCIE_NW2A0_9", - "PCIE_NW4END1_19", - "PCIE_IMUX8_R_9", - "PCIE_IMUX28_L_4", - "PCIE_MIMTXRDATA27", - "PCIE_BLOCK_OUTS_B3_R_10", - "PCIE_NE4BEG2_17", - "PCIE_LOGIC_OUTS_B10_L_11", - "PCIE_MIMTXRDATA6", - "PCIE_EE4C1_0", - "PCIE_IMUX5_R_8", - "PCIE_LOGIC_OUTS_B7_L_0", - "PCIE_IMUX27_R_16", - "PCIE_LOGIC_OUTS_B13_L_6", - "PCIE_CTRL1_R_9", - "PCIE_IMUX43_L_19", - "PCIE_PIPETX2DATA0", - "PCIE_LH2_17", - "PCIE_BYP0_R_5", - "PCIE_IMUX33_L_16", - "PCIE_DBGVECB1", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", - "PCIE_IMUX5_L_19", - "PCIE_IMUX5_R_2", - "PCIE_PIPERX4DATA9", - "PCIE_LOGIC_OUTS_B23_L_11", - "PCIE_SE4BEG1_13", - "PCIE_SE4BEG2_13", - "PCIE_SW2A1_12", - "PCIE_IMUX23_R_12", - "PCIE_PIPERX3DATA0", - "PCIE_PIPERX1STATUS0", - "PCIE_MIMRXRADDR11", - "PCIE_IMUX18_R_19", - "PCIE_MIMTXRDATA4", - "PCIE_LOGIC_OUTS_B9_R_13", - "PCIE_IMUX3_R_6", - "PCIE_NE4C3_15", - "PCIE_TRNRD54", - "PCIE_IMUX33_R_14", - "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", - "PCIE_IMUX14_L_16", - "PCIE_WL1END2_16", - "PCIE_SW4END0_4", - "PCIE_LOGIC_OUTS_B13_R_9", - "PCIE_CFGMGMTDI22", - "PCIE_IMUX23_R_11", - "PCIE_FAN2_L_16", - "PCIE_IMUX16_L_3", - "PCIE_MIMRXRADDR12", - "PCIE_BYP0_L_3", - "PCIE_IMUX24_L_11", - "PCIE_NE4C1_8", - "PCIE_WW4END1_13", - "PCIE_ER1BEG0_11", - "PCIE_ER1BEG0_8", - "PCIE_LOGIC_OUTS_B21_L_11", - "PCIE_PIPETX4POWERDOWN1", - "PCIE_IMUX33_L_10", - "PCIE_IMUX36_R_11", - "PCIE_LOGIC_OUTS_B15_L_8", - "PCIE_CFGINTERRUPTDO7", - "PCIE_SE4BEG2_7", - "PCIE_DBGVECB13", - "PCIE_EE4C3_4", - "PCIE_LOGIC_OUTS_B23_R_14", - "PCIE_LOGIC_OUTS_B7_L_4", - "PCIE_TL2ERRHDR51", - "PCIE_IMUX25_R_14", - "PCIE_ER1BEG1_8", - "PCIE_TRNTERRFWD", - "PCIE_IMUX43_R_6", - "PCIE_IMUX37_R_19", - "PCIE_CFGMGMTDO4", - "PCIE_WW4A2_16", - "PCIE_LH12_6", - "PCIE_IMUX26_R_3", - "PCIE_WW4A1_2", - "PCIE_IMUX12_R_9", - "PCIE_LH6_0", - "PCIE_WW2A1_12", - "PCIE_IMUX24_R_9", - "PCIE_CFGERRAERHEADERLOG62", - "PCIE_FAN7_R_1", - "PCIE_LOGIC_OUTS_B14_L_6", - "PCIE_LOGIC_OUTS_B3_L_8", - "PCIE_FAN6_L_10", - "PCIE_LOGIC_OUTS_B7_R_3", - "PCIE_CFGAERINTERRUPTMSGNUM4", - "PCIE_MIMTXWDATA2", - "PCIE_IMUX0_R_1", - "PCIE_PLDIRECTEDLTSSMSTALL", - "PCIE_CFGDSN24", - "PCIE_SE4C2_12", - "PCIE_PIPERX3DATA10", - "PCIE_LOGIC_OUTS_B20_L_12", - "PCIE_TRNRD34", - "PCIE_FAN1_L_15", - "PCIE_TRNTECRCGEN", - "PCIE_BLOCK_OUTS_B3_L_17", - "PCIE_BYP4_L_15", - "PCIE_LOGIC_OUTS_B3_L_13", - "PCIE_NE4BEG0_7", - "PCIE_TRNRREM1", - "PCIE_PIPETX4CHARISK0", - "PCIE_IMUX31_R_2", - "PCIE_PIPERX1DATA1", - "PCIE_TRNTD53", - "PCIE_CFGERRTLPCPLHEADER9", - "PCIE_WL1END3_7", - "PCIE_BLOCK_OUTS_B2_R_6", - "PCIE_TRNRREM0", - "PCIE_ER1BEG1_9", - "PCIE_FAN4_L_7", - "PCIE_CFGINTERRUPTMSIENABLE", - "PCIE_TRNRDLLPDATA20", - "PCIE_PIPETX7DATA2", - "PCIE_XILUNCONNOUT34", - "PCIE_IMUX39_R_7", - "PCIE_SW4A3_9", - "PCIE_BYP0_R_17", - "PCIE_BYP7_R_3", - "PCIE_CFGDEVID0", - "PCIE_ER1BEG2_18", - "PCIE_LOGIC_OUTS_B17_L_12", - "PCIE_SE2A0_9", - "PCIE_IMUX40_R_1", - "PCIE_NE4C3_9", - "PCIE_LOGIC_OUTS_B3_L_15", - "PCIE_NW4A0_1", - "PCIE_IMUX14_L_5", - "PCIE_MIMRXRDATA27", - "PCIE_BYP0_R_18", - "PCIE_IMUX16_R_13", - "PCIE_LOGIC_OUTS_B15_R_18", - "PCIE_SW4A2_2", - "PCIE_MIMTXRDATA53", - "PCIE_TRNRD29", - "PCIE_CTRL1_R_19", - "PCIE_PIPERX0DATA15", - "PCIE_LOGIC_OUTS_B8_R_19", - "PCIE_NW2A1_2", - "PCIE_IMUX41_R_7", - "PCIE_EE4C2_7", - "PCIE_PIPERX3DATA15", - "PCIE_PIPERX7CHARISK1", - "PCIE_IMUX22_R_18", - "PCIE_FAN0_L_16", - "PCIE_CFGERRAERHEADERLOG95", - "PCIE_FAN1_R_18", - "PCIE_CFGMGMTDI3", - "PCIE_IMUX13_L_7", - "PCIE_NE4BEG2_15", - "PCIE_IMUX41_L_7", - "PCIE_LH5_0", - "PCIE_MIMRXWDATA34", - "PCIE_TRNTD94", - "PCIE_ER1BEG1_10", - "PCIE_PIPETX1DATA6", - "PCIE_DBGVECA21", - "PCIE_TRNRD36", - "PCIE_LH10_13", - "PCIE_PIPETX0DATA15", - "PCIE_IMUX21_L_18", - "PCIE_LOGIC_OUTS_B12_L_0", - "PCIE_CFGERRAERHEADERLOG116", - "PCIE_BYP7_R_14", - "PCIE_IMUX29_L_0", - "PCIE_EE4C1_19", - "PCIE_PIPETX7POWERDOWN0", - "PCIE_PLDBGVEC9", - "PCIE_PIPERX2CHARISK0", - "PCIE_MIMTXWDATA41", - "PCIE_LOGIC_OUTS_B8_L_8", - "PCIE_IMUX12_L_11", - "PCIE_IMUX23_R_0", - "PCIE_LOGIC_OUTS_B20_L_16", - "PCIE_TRNRD113", - "PCIE_EE2BEG2_1", - "PCIE_IMUX22_L_18", - "PCIE_IMUX41_R_8", - "PCIE_WW2END2_3", - "PCIE_DBGVECB54", - "PCIE_LH7_18", - "PCIE_LOGIC_OUTS_B10_R_11", - "PCIE_MIMTXREN", - "PCIE_LOGIC_OUTS_B5_R_19", - "PCIE_EE2A2_1", - "PCIE_LOGIC_OUTS_B3_L_2", - "PCIE_CFGERRCPLABORTN", - "PCIE_NW4END0_13", - "PCIE_IMUX22_R_10", - "PCIE_EE4B3_19", - "PCIE_SW4END2_5", - "PCIE_TRNTD40", - "PCIE_LOGIC_OUTS_B5_R_8", - "PCIE_EDTUPDATE", - "PCIE_MIMRXRDATA15", - "PCIE_NW4A3_11", - "PCIE_BLOCK_OUTS_B1_L_14", - "PCIE_CFGERRAERHEADERLOG2", - "PCIE_LH5_16", - "PCIE_TRNTD116", - "PCIE_IMUX0_R_2", - "PCIE_IMUX13_R_1", - "PCIE_LL2REPLAYTOERR", - "PCIE_SE4C0_19", - "PCIE_MIMRXWADDR0", - "PCIE_LOGIC_OUTS_B12_R_13", - "PCIE_NE4BEG0_12", - "PCIE_IMUX2_R_9", - "PCIE_LOGIC_OUTS_B22_R_19", - "PCIE_IMUX29_R_5", - "PCIE_TRNRD82", - "PCIE_DBGVECC11", - "PCIE_IMUX44_L_2", - "PCIE_WW2A1_19", - "PCIE_TRNRDLLPDATA15", - "PCIE_PIPETX6COMPLIANCE", - "PCIE_TRNTD78", - "PCIE_WW4END1_11", - "PCIE_SE4BEG2_2", - "PCIE_IMUX34_R_8", - "PCIE_SW4A2_14", - "PCIE_IMUX25_L_2", - "PCIE_IMUX17_R_2", - "PCIE_BLOCK_OUTS_B2_L_19", - "PCIE_IMUX24_L_18", - "PCIE_FAN1_L_10", - "PCIE_CFGPMHALTASPML1N", - "PCIE_LL2SUSPENDOK", - "PCIE_IMUX9_R_3", - "PCIE_IMUX7_R_2", - "PCIE_IMUX1_R_2", - "PCIE_NW2A1_5", - "PCIE_SE2A1_6", - "PCIE_WW4END0_19", - "PCIE_IMUX44_L_4", - "PCIE_IMUX10_R_4", - "PCIE_NW2A2_8", - "PCIE_LH3_2", - "PCIE_LOGIC_OUTS_B15_L_5", - "PCIE_TL2ERRHDR22", - "PCIE_IMUX12_L_15", - "PCIE_LOGIC_OUTS_B23_R_6", - "PCIE_EE4A3_5", - "PCIE_TRNFCCPLH7", - "PCIE_BLOCK_OUTS_B3_R_0", - "PCIE_IMUX24_R_7", - "PCIE_EE2BEG1_6", - "PCIE_NE2A0_16", - "PCIE_LOGIC_OUTS_B11_R_17", - "PCIE_LOGIC_OUTS_B12_L_19", - "PCIE_SW4A3_18", - "PCIE_EE4B1_10", - "PCIE_LH4_3", - "PCIE_XILUNCONNOUT15", - "PCIE_NE4BEG2_10", - "PCIE_IMUX45_R_17", - "PCIE_IMUX1_L_9", - "PCIE_IMUX9_R_8", - "PCIE_TRNRD14", - "PCIE_DBGVECA53", - "PCIE_SE2A0_3", - "PCIE_LOGIC_OUTS_B21_R_1", - "PCIE_IMUX10_L_3", - "PCIE_NE4BEG0_13", - "PCIE_LOGIC_OUTS_B0_L_3", - "PCIE_BYP5_R_11", - "PCIE_CFGERRAERHEADERLOG127", - "PCIE_IMUX37_L_11", - "PCIE_SE2A3_16", - "PCIE_NW4A1_1", - "PCIE_WW4C0_9", - "PCIE_CFGMGMTDWADDR6", - "PCIE_IMUX6_L_1", - "PCIE_IMUX13_L_19", - "PCIE_LOGIC_OUTS_B13_R_8", - "PCIE_BYP5_L_12", - "PCIE_TRNFCNPD0", - "PCIE_IMUX33_R_15", - "PCIE_WW2END0_3", - "PCIE_LOGIC_OUTS_B5_L_16", - "PCIE_TRNRD42", - "PCIE_IMUX3_L_4", - "PCIE_LOGIC_OUTS_B5_L_2", - "PCIE_MIMRXRDATA63", - "PCIE_NW4END3_11", - "PCIE_LOGIC_OUTS_B21_L_12", - "PCIE_IMUX15_L_14", - "PCIE_SW4END3_3", - "PCIE_PLDIRECTEDLTSSMNEW3", - "PCIE_SW2A0_17", - "PCIE_WW4A0_15", - "PCIE_WW4C3_13", - "PCIE_MONITOR_P_13", - "PCIE_TL2ERRHDR8", - "PCIE_DBGVECA32", - "PCIE_PIPERX0DATA5", - "PCIE_BYP1_L_2", - "PCIE_IMUX38_L_2", - "PCIE_BYP1_R_19", - "PCIE_TRNRDLLPDATA46", - "PCIE_FAN3_L_10", - "PCIE_LOGIC_OUTS_B0_R_10", - "PCIE_IMUX11_R_12", - "PCIE_SE4C2_1", - "PCIE_TRNRDLLPDATA43", - "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", - "PCIE_CFGERRTLPCPLHEADER15", - "PCIE_EE2BEG0_15", - "PCIE_LOGIC_OUTS_B1_L_2", - "PCIE_NE2A0_4", - "PCIE_PIPETX0COMPLIANCE", - "PCIE_BLOCK_OUTS_B3_L_15", - "PCIE_WL1END3_14", - "PCIE_IMUX26_R_10", - "PCIE_IMUX31_R_7", - "PCIE_CFGERRAERHEADERLOG83", - "PCIE_SE2A3_18", - "PCIE_WR1END3_3", - "PCIE_EE4BEG2_9", - "PCIE_EE2A2_16", - "PCIE_PIPERX1DATA15", - "PCIE_CTRL1_R_11", - "PCIE_LOGIC_OUTS_B9_R_4", - "PCIE_LOGIC_OUTS_B13_R_12", - "PCIE_EL1BEG2_12", - "PCIE_LOGIC_OUTS_B11_R_9", - "PCIE_CFGMSGRECEIVEDDEASSERTINTC", - "PCIE_EE2A0_7", - "PCIE_WW4A3_8", - "PCIE_XILUNCONNOUT35", - "PCIE_LOGIC_OUTS_B9_L_19", - "PCIE_LOGIC_OUTS_B6_R_12", - "PCIE_CFGMSGRECEIVEDERRNONFATAL", - "PCIE_TRNRD28", - "PCIE_IMUX1_L_1", - "PCIE_EE4C1_15", - "PCIE_EE4C3_19", - "PCIE_NW4A2_2", - "PCIE_MIMTXWDATA64", - "PCIE_TRNRD89", - "PCIE_IMUX5_L_4", - "PCIE_TL2ERRHDR7", - "PCIE_IMUX25_L_12", - "PCIE_CTRL0_R_6", - "PCIE_LH1_9", - "PCIE_WR1END1_13", - "PCIE_BYP0_R_13", - "PCIE_SE4C1_1", - "PCIE_NE4C3_12", - "PCIE_BYP0_L_19", - "PCIE_CFGCOMMANDMEMENABLE", - "PCIE_CFGMGMTDI9", - "PCIE_IMUX47_R_9", - "PCIE_FAN7_R_12", - "PCIE_BLOCK_OUTS_B2_L_6", - "PCIE_NE4C1_4", - "PCIE_WW4END3_18", - "PCIE_FAN6_R_13", - "PCIE_WW4A3_2", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", - "PCIE_TRNTD56", - "PCIE_NE2A0_17", - "PCIE_IMUX19_R_15", - "PCIE_IMUX21_R_17", - "PCIE_FAN3_L_6", - "PCIE_SE2A2_2", - "PCIE_IMUX16_R_0", - "PCIE_PIPERX3DATA6", - "PCIE_MIMTXWADDR6", - "PCIE_LOGIC_OUTS_B20_R_14", - "PCIE_CFGINTERRUPTDI2", - "PCIE_IMUX13_L_13", - "PCIE_SE4BEG0_9", - "PCIE_BLOCK_OUTS_B3_L_8", - "PCIE_TRNTDLLPDATA24", - "PCIE_CFGLINKCONTROLRCB", - "PCIE_BLOCK_OUTS_B1_R_19", - "PCIE_MIMRXWADDR3", - "PCIE_WR1END1_5", - "PCIE_IMUX32_L_18", - "PCIE_BLOCK_OUTS_B0_L_14", - "PCIE_SW4END3_7", - "PCIE_TRNTD9", - "PCIE_PIPETX2DATA7", - "PCIE_BYP0_R_3", - "PCIE_EE2BEG0_0", - "PCIE_TRNTD38", - "PCIE_IMUX10_R_17", - "PCIE_IMUX5_L_18", - "PCIE_BYP3_R_12", - "PCIE_PIPERX6DATA9", - "PCIE_WW4B3_14", - "PCIE_CFGDEVID9", - "PCIE_CFGMGMTDO19", - "PCIE_WR1END0_14", - "PCIE_IMUX13_R_5", - "PCIE_TRNRSRCDSC", - "PCIE_WW4END0_9", - "PCIE_DBGSCLRG", - "PCIE_LH3_7", - "PCIE_EE4BEG2_8", - "PCIE_BYP5_R_4", - "PCIE_SW4END2_0", - "PCIE_TRNRD123", - "PCIE_LOGIC_OUTS_B18_L_1", - "PCIE_IMUX43_L_15", - "PCIE_LOGIC_OUTS_B10_R_14", - "PCIE_CFGERRAERHEADERLOG5", - "PCIE_WW4A0_9", - "PCIE_BYP3_R_10", - "PCIE_IMUX6_L_2", - "PCIE_IMUX0_R_9", - "PCIE_WW4END0_1", - "PCIE_LOGIC_OUTS_B10_R_8", - "PCIE_LOGIC_OUTS_B7_R_8", - "PCIE_EE4B0_17", - "PCIE_IMUX38_R_17", - "PCIE_TL2ERRHDR49", - "PCIE_IMUX13_L_15", - "PCIE_CFGERRLOCKEDN", - "PCIE_NW2A0_17", - "PCIE_LOGIC_OUTS_B14_R_11", - "PCIE_SW4A3_17", - "PCIE_TRNTD13", - "PCIE_LH12_8", - "PCIE_CFGERRAERHEADERLOG78", - "PCIE_WW4A0_8", - "PCIE_ER1BEG2_5", - "PCIE_ER1BEG0_19", - "PCIE_TRNRDLLPDATA1", - "PCIE_LOGIC_OUTS_B20_R_0", - "PCIE_SW4END1_0", - "PCIE_WW4B0_9", - "PCIE_TL2ERRHDR25", - "PCIE_LOGIC_OUTS_B23_R_5", - "PCIE_IMUX21_R_2", - "PCIE_CFGMGMTDI24", - "PCIE_WW4END3_8", - "PCIE_LOGIC_OUTS_B22_R_12", - "PCIE_WL1END1_2", - "PCIE_TRNTBUFAV4", - "PCIE_WR1END3_0", - "PCIE_LOGIC_OUTS_B0_L_19", - "PCIE_NE4BEG1_19", - "PCIE_BYP1_R_3", - "PCIE_LOGIC_OUTS_B1_L_0", - "PCIE_CFGINTERRUPTRDYN", - "PCIE_IMUX30_R_19", - "PCIE_EE2A3_14", - "PCIE_BYP6_R_6", - "PCIE_WW2A0_17", - "PCIE_IMUX42_R_1", - "PCIE_LOGIC_OUTS_B9_R_19", - "PCIE_PIPERX0PHYSTATUS", - "PCIE_EL1BEG3_3", - "PCIE_MIMTXRADDR8", - "PCIE_IMUX24_R_2", - "PCIE_BLOCK_OUTS_B0_R_14", - "PCIE_CTRL1_R_5", - "PCIE_PIPETX0POWERDOWN1", - "PCIE_IMUX11_R_11", - "PCIE_LOGIC_OUTS_B19_L_10", - "PCIE_BYP6_R_16", - "PCIE_IMUX38_R_8", - "PCIE_LOGIC_OUTS_B4_R_18", - "PCIE_TL2ERRHDR30", - "PCIE_EE2BEG1_10", - "PCIE_NW2A1_17", - "PCIE_WW4A3_4", - "PCIE_IMUX5_L_0", - "PCIE_LOGIC_OUTS_B12_L_15", - "PCIE_WR1END0_15", - "PCIE_IMUX35_L_8", - "PCIE_TRNFCPD10", - "PCIE_IMUX36_L_4", - "PCIE_SE4C3_17", - "PCIE_PIPERX1CHARISK1", - "PCIE_TRNFCPD2", - "PCIE_PIPETX1DATA14", - "PCIE_WW4C0_3", - "PCIE_TRNRD57", - "PCIE_CFGERRAERHEADERLOG64", - "PCIE_IMUX8_R_17", - "PCIE_TRNTD98", - "PCIE_TRNTBUFAV3", - "PCIE_CFGERRTLPCPLHEADER27", - "PCIE_PIPETX0DATA1", - "PCIE_NW4END0_17", - "PCIE_NE4C3_8", - "PCIE_WW4A1_12", - "PCIE_LOGIC_OUTS_B16_R_5", - "PCIE_BYP0_L_5", - "PCIE_FAN3_R_2", - "PCIE_EE4C0_3", - "PCIE_XILUNCONNOUT19", - "PCIE_IMUX2_L_11", - "PCIE_NE4C0_15", - "PCIE_CFGDSBUSNUMBER2", - "PCIE_MIMRXWDATA2", - "PCIE_DBGVECA26", - "PCIE_CFGMSGDATA8", - "PCIE_LH1_2", - "PCIE_LOGIC_OUTS_B2_L_19", - "PCIE_IMUX25_L_7", - "PCIE_EDTCHANNELSOUT4", - "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", - "PCIE_PLRXPMSTATE0", - "PCIE_TRNRD116", - "PCIE_LOGIC_OUTS_B13_L_5", - "PCIE_SE4BEG3_5", - "PCIE_IMUX19_R_17", - "PCIE_WW4B3_13", - "PCIE_IMUX26_L_1", - "PCIE_DBGVECA48", - "PCIE_NW2A1_0", - "PCIE_BYP3_R_11", - "PCIE_BYP5_R_3", - "PCIE_EE4A1_14", - "PCIE_FAN2_L_13", - "PCIE_IMUX38_L_0", - "PCIE_PIPERX5DATA9", - "PCIE_IMUX0_L_13", - "PCIE_CFGERRAERHEADERLOG124", - "PCIE_BYP2_R_5", - "PCIE_LOGIC_OUTS_B15_R_4", - "PCIE_NW2A3_15", - "PCIE_PIPERX0DATA4", - "PCIE_WR1END3_1", - "PCIE_EE4B3_13", - "PCIE_LOGIC_OUTS_B4_R_1", - "PCIE_LOGIC_OUTS_B0_R_17", - "PCIE_BYP2_R_12", - "PCIE_MIMRXWDATA32", - "PCIE_IMUX46_R_15", - "PCIE_PLTXPMSTATE1", - "PCIE_TRNRSOF", - "PCIE_FAN0_R_18", - "PCIE_MIMTXWDATA39", - "PCIE_NW4A1_17", - "PCIE_BLOCK_OUTS_B3_R_5", - "PCIE_TRNFCNPH4", - "PCIE_EL1BEG0_11", - "PCIE_TRNTBUFAV5", - "PCIE_IMUX21_L_17", - "PCIE_WW2END0_4", - "PCIE_EE4BEG3_12", - "PCIE_MONITOR_N_1", - "PCIE_WW4B3_6", - "PCIE_LH9_9", - "PCIE_MONITOR_N_7", - "PCIE_CFGDEVCONTROLMAXREADREQ2", - "PCIE_CFGERRAERHEADERLOG34", - "PCIE_IMUX1_L_3", - "PCIE_LOGIC_OUTS_B11_R_19", - "PCIE_WW2A0_8", - "PCIE_IMUX45_R_4", - "PCIE_PLRSTN", - "PCIE_PLDIRECTEDLINKCHANGE0", - "PCIE_TRNRD31", - "PCIE_IMUX4_L_19", - "PCIE_BYP3_R_0", - "PCIE_ER1BEG2_16", - "PCIE_MIMTXRDATA20", - "PCIE_IMUX2_L_12", - "PCIE_FAN5_L_13", - "PCIE_LOGIC_OUTS_B21_L_4", - "PCIE_TL2ERRHDR54", - "PCIE_EE4B0_18", - "PCIE_EE4BEG2_4", - "PCIE_FAN3_L_16", - "PCIE_WW2END3_10", - "PCIE_BYP2_R_15", - "PCIE_PIPETX2CHARISK1", - "PCIE_WW4B2_14", - "PCIE_EE4BEG0_1", - "PCIE_NW4A0_3", - "PCIE_LOGIC_OUTS_B14_L_0", - "PCIE_SW4END0_9", - "PCIE_EE4BEG3_7", - "PCIE_IMUX6_R_4", - "PCIE_DBGVECB14", - "PCIE_EE4B1_17", - "PCIE_IMUX25_R_5", - "PCIE_CFGERRAERHEADERLOG118", - "PCIE_EE4A2_18", - "PCIE_SW2A1_19", - "PCIE_TRNRERRFWD", - "PCIE_FAN3_R_6", - "PCIE_EE4C1_5", - "PCIE_IMUX34_L_1", - "PCIE_EE4C1_10", - "PCIE_CFGSUBSYSVENDID3", - "PCIE_PIPETX5DATA15", - "PCIE_CLK1_L_14", - "PCIE_FAN2_R_9", - "PCIE_IMUX16_L_1", - "PCIE_PIPETX1DATA2", - "PCIE_IMUX22_R_2", - "PCIE_TRNRDLLPDATA58", - "PCIE_EE4C2_6", - "PCIE_MIMTXRDATA38", - "PCIE_SE2A0_13", - "PCIE_ER1BEG3_5", - "PCIE_SE2A1_10", - "PCIE_LH4_18", - "PCIE_IMUX23_R_13", - "PCIE_BLOCK_OUTS_B2_R_11", - "PCIE_CFGERRCPLUNEXPECTN", - "PCIE_EE2A0_18", - "PCIE_CFGERRAERHEADERLOG107", - "PCIE_IMUX14_R_9", - "PCIE_CFGDEVCONTROLENABLERO", - "PCIE_ER1BEG2_4", - "PCIE_LH9_17", - "PCIE_IMUX29_R_13", - "PCIE_EE2BEG1_5", - "PCIE_WW2A3_1", - "PCIE_FAN6_L_19", - "PCIE_BYP4_L_16", - "PCIE_IMUX33_R_4", - "PCIE_SW4A1_17", - "PCIE_IMUX27_L_11", - "PCIE_MIMTXRDATA0", - "PCIE_NW2A0_18", - "PCIE_CFGERRAERHEADERLOG82", - "PCIE_IMUX32_R_19", - "PCIE_NE4BEG0_2", - "PCIE_LOGIC_OUTS_B17_L_7", - "PCIE_EE4C1_1", - "PCIE_TRNRDLLPDATA10", - "PCIE_LOGIC_OUTS_B23_R_19", - "PCIE_PIPERX1DATA10", - "PCIE_WW2END2_1", - "PCIE_IMUX35_R_14", - "PCIE_WR1END1_18", - "PCIE_TRNFCNPD7", - "PCIE_LH6_18", - "PCIE_FAN2_R_7", - "PCIE_IMUX42_L_4", - "PCIE_SE4BEG3_13", - "PCIE_SE4BEG3_3", - "PCIE_LOGIC_OUTS_B19_L_14", - "PCIE_WW2END2_19", - "PCIE_CLK1_R_11", - "PCIE_IMUX26_L_13", - "PCIE_CFGINTERRUPTDO6", - "PCIE_NW4A0_12", - "PCIE_IMUX36_R_2", - "PCIE_IMUX45_L_14", - "PCIE_LOGIC_OUTS_B5_L_3", - "PCIE_IMUX35_R_13", - "PCIE_WL1END3_9", - "PCIE_PIPERX1ELECIDLE", - "PCIE_TRNRD126", - "PCIE_EE2A3_18", - "PCIE_LH1_10", - "PCIE_IMUX29_L_5", - "PCIE_IMUX38_L_8", - "PCIE_IMUX18_R_10", - "PCIE_IMUX3_L_5", - "PCIE_ER1BEG1_6", - "PCIE_IMUX42_L_15", - "PCIE_IMUX16_R_12", - "PCIE_IMUX23_R_2", - "PCIE_BLOCK_OUTS_B1_R_10", - "PCIE_LH1_3", - "PCIE_LOGIC_OUTS_B22_L_3", - "PCIE_IMUX47_L_0", - "PCIE_IMUX37_R_4", - "PCIE_EE4A3_9", - "PCIE_EE4A3_1", - "PCIE_IMUX27_L_14", - "PCIE_LOGIC_OUTS_B17_L_10", - "PCIE_BLOCK_OUTS_B2_L_12", - "PCIE_LOGIC_OUTS_B5_L_7", - "PCIE_WW4END2_11", - "PCIE_LOGIC_OUTS_B2_L_10", - "PCIE_MIMTXRDATA1", - "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", - "PCIE_IMUX12_L_3", - "PCIE_NW2A1_7", - "PCIE_FAN1_R_12", - "PCIE_TRNTDLLPDATA26", - "PCIE_IMUX43_R_16", - "PCIE_CFGDEVID11", - "PCIE_WW4C0_12", - "PCIE_IMUX1_L_14", - "PCIE_NE4BEG2_5", - "PCIE_WL1END3_12", - "PCIE_MIMTXWDATA21", - "PCIE_NE4BEG1_18", - "PCIE_MIMTXRDATA11", - "PCIE_IMUX44_R_5", - "PCIE_IMUX29_R_16", - "PCIE_CFGLINKSTATUSLINKTRAINING", - "PCIE_EE2A2_17", - "PCIE_NW4A2_1", - "PCIE_LH8_14", - "PCIE_TRNRDLLPDATA61", - "PCIE_NE2A3_17", - "PCIE_NW2A3_5", - "PCIE_BLOCK_OUTS_B0_L_1", - "PCIE_PIPERX2DATA9", - "PCIE_MIMRXRDATA12", - "PCIE_SE2A3_7", - "PCIE_LH1_16", - "PCIE_TL2ERRHDR32", - "PCIE_TRNRD7", - "PCIE_NW4END0_5", - "PCIE_IMUX3_R_19", - "PCIE_CFGDSN56", - "PCIE_EE4BEG2_7", - "PCIE_LL2LINKSTATUS2", - "PCIE_WW4END2_18", - "PCIE_BYP0_R_12", - "PCIE_DBGVECB58", - "PCIE_IMUX11_R_13", - "PCIE_IMUX14_R_15", - "PCIE_LOGIC_OUTS_B13_R_16", - "PCIE_WW4B0_0", - "PCIE_LOGIC_OUTS_B17_L_19", - "PCIE_NW2A1_19", - "PCIE_NW4A1_4", - "PCIE_NE4C2_8", - "PCIE_IMUX9_L_6", - "PCIE_IMUX2_R_11", - "PCIE_BLOCK_OUTS_B0_R_19", - "PCIE_IMUX46_L_15", - "PCIE_MONITOR_P_18", - "PCIE_EE4C3_6", - "PCIE_WR1END1_8", - "PCIE_PLDIRECTEDLTSSMNEW2", - "PCIE_CFGDSN16", - "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", - "PCIE_XILUNCONNOUT10", - "PCIE_CFGERRTLPCPLHEADER39", - "PCIE_LOGIC_OUTS_B4_L_12", - "PCIE_MIMTXRDATA68", - "PCIE_WW2END2_17", - "PCIE_FAN4_L_17", - "PCIE_CFGERRAERHEADERLOG81", - "PCIE_IMUX45_L_8", - "PCIE_SW4A3_1", - "PCIE_IMUX45_R_3", - "PCIE_FAN2_L_9", - "PCIE_LOGIC_OUTS_B7_L_8", - "PCIE_TRNTD1", - "PCIE_WR1END1_7", - "PCIE_LOGIC_OUTS_B13_L_15", - "PCIE_TRNTD61", - "PCIE_IMUX36_L_11", - "PCIE_IMUX8_L_17", - "PCIE_FAN7_R_11", - "PCIE_LNKCLKEN", - "PCIE_LOGIC_OUTS_B20_L_11", - "PCIE_DBGVECC0", - "PCIE_SE4BEG2_0", - "PCIE_IMUX17_L_12", - "PCIE_WL1END3_10", - "PCIE_IMUX9_L_5", - "PCIE_MIMRXRDATA26", - "PCIE_CFGERRAERHEADERLOG61", - "PCIE_WW4A2_8", - "PCIE_WW2END2_10", - "PCIE_CFGMGMTRDENN", - "PCIE_LH8_0", - "PCIE_LH4_8", - "PCIE_MIMRXWADDR7", - "PCIE_FAN7_L_19", - "PCIE_IMUX45_R_15", - "PCIE_IMUX44_R_11", - "PCIE_CFGPCIELINKSTATE0", - "PCIE_TRNTDLLPDATA6", - "PCIE_IMUX23_R_18", - "PCIE_LOGIC_OUTS_B15_R_1", - "PCIE_IMUX31_R_10", - "PCIE_NE2A3_11", - "PCIE_MIMTXWDATA10", - "PCIE_CFGDEVCONTROLMAXPAYLOAD1", - "PCIE_IMUX0_L_19", - "PCIE_IMUX34_R_11", - "PCIE_EE4B1_0", - "PCIE_WW4C1_16", - "PCIE_CFGERRAERHEADERLOG17", - "PCIE_MIMRXRDATA46", - "PCIE_IMUX17_L_0", - "PCIE_EE4B2_9", - "PCIE_PIPETX1DATA13", - "PCIE_WW4B3_17", - "PCIE_TRNTDLLPDATA25", - "PCIE_IMUX27_R_3", - "PCIE_LOGIC_OUTS_B3_R_6", - "PCIE_PIPERX6DATA2", - "PCIE_WW4A2_4", - "PCIE_SW4A2_19", - "PCIE_CFGERRTLPCPLHEADER6", - "PCIE_FAN4_R_15", - "PCIE_IMUX31_R_9", - "PCIE_IMUX31_R_6", - "PCIE_MONITOR_P_15", - "PCIE_IMUX29_R_7", - "PCIE_PIPETX3DATA6", - "PCIE_SE2A2_8", - "PCIE_TRNTDLLPDATA9", - "PCIE_IMUX4_L_5", - "PCIE_BYP4_L_18", - "PCIE_TRNRDLLPDATA56", - "PCIE_EE4A3_19", - "PCIE_SW4END1_8", - "PCIE_MIMTXWDATA40", - "PCIE_IMUX10_L_18", - "PCIE_EE4BEG0_17", - "PCIE_FAN0_R_1", - "PCIE_PIPETX3DATA12", - "PCIE_PIPETX4DATA7", - "PCIE_SW4A2_6", - "PCIE_NE4C0_2", - "PCIE_IMUX28_R_15", - "PCIE_IMUX45_R_1", - "PCIE_TRNRDLLPDATA59", - "PCIE_PIPERX4CHARISK1", - "PCIE_IMUX23_L_17", - "PCIE_PL2LINKUP", - "PCIE_NE4BEG3_2", - "PCIE_CFGDSN53", - "PCIE_IMUX46_L_11", - "PCIE_IMUX40_R_4", - "PCIE_CFGMGMTDI28", - "PCIE_WW4C2_8", - "PCIE_PIPERX5POLARITY", - "PCIE_NE4BEG2_19", - "PCIE_IMUX45_L_18", - "PCIE_EDTCHANNELSIN1", - "PCIE_ER1BEG2_17", - "PCIE_LOGIC_OUTS_B9_L_8", - "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", - "PCIE_IMUX11_L_16", - "PCIE_DBGVECB2", - "PCIE_WW4C1_7", - "PCIE_IMUX24_R_18", - "PCIE_EE4B3_18", - "PCIE_LOGIC_OUTS_B23_R_12", - "PCIE_BYP0_L_16", - "PCIE_PIPETX3POWERDOWN0", - "PCIE_LOGIC_OUTS_B21_L_8", - "PCIE_TRNRD12", - "PCIE_PIPETX2DATA1", - "PCIE_IMUX11_R_4", - "PCIE_MONITOR_N_4", - "PCIE_LOGIC_OUTS_B4_R_10", - "PCIE_MIMRXWDATA33", - "PCIE_TRNFCNPD10", - "PCIE_NE4BEG3_10", - "PCIE_WW2A0_14", - "PCIE_IMUX7_R_19", - "PCIE_LOGIC_OUTS_B19_L_18", - "PCIE_TRNRBARHIT3", - "PCIE_BYP3_L_14", - "PCIE_PIPETX7DATA15", - "PCIE_WW4C2_12", - "PCIE_FAN7_L_2", - "PCIE_TRNRBARHIT6", - "PCIE_EL1BEG1_11", - "PCIE_IMUX20_R_6", - "PCIE_IMUX21_R_19", - "PCIE_LOGIC_OUTS_B10_L_12", - "PCIE_IMUX15_R_7", - "PCIE_IMUX34_R_6", - "PCIE_SE2A1_2", - "PCIE_CFGERRTLPCPLHEADER2", - "PCIE_CFGDSN1", - "PCIE_IMUX13_L_16", - "PCIE_IMUX5_L_16", - "PCIE_IMUX29_R_12", - "PCIE_WL1END3_18", - "PCIE_IMUX5_L_2", - "PCIE_WW4END2_13", - "PCIE_MIMTXRDATA49", - "PCIE_CFGERRTLPCPLHEADER14", - "PCIE_IMUX6_R_7", - "PCIE_IMUX32_R_6", - "PCIE_MIMTXRDATA45", - "PCIE_IMUX41_R_14", - "PCIE_LOGIC_OUTS_B22_R_10", - "PCIE_LOGIC_OUTS_B7_L_9", - "PCIE_IMUX43_R_7", - "PCIE_PLDIRECTEDLINKWIDTH0", - "PCIE_WW2END0_2", - "PCIE_IMUX9_R_14", - "PCIE_CFGSUBSYSID0", - "PCIE_PIPERX4CHANISALIGNED", - "PCIE_EE4A1_12", - "PCIE_CFGERRINTERNALCORN", - "PCIE_LOGIC_OUTS_B9_L_4", - "PCIE_EE4BEG0_11", - "PCIE_FAN3_R_15", - "PCIE_WW4B2_13", - "PCIE_CLK1_L_5", - "PCIE_LH3_13", - "PCIE_PIPETX4DATA3", - "PCIE_LOGIC_OUTS_B4_R_16", - "PCIE_BLOCK_OUTS_B3_L_1", - "PCIE_IMUX5_L_8", - "PCIE_TRNRD5", - "PCIE_DBGVECB48", - "PCIE_IMUX26_R_1", - "PCIE_IMUX23_L_18", - "PCIE_CFGDEVCONTROLAUXPOWEREN", - "PCIE_TRNTD69", - "PCIE_LOGIC_OUTS_B21_L_0", - "PCIE_IMUX6_L_3", - "PCIE_DBGVECA31", - "PCIE_TRNTD85", - "PCIE_FAN3_L_1", - "PCIE_BLOCK_OUTS_B0_R_11", - "PCIE_SE4BEG1_3", - "PCIE_IMUX12_L_17", - "PCIE_IMUX10_R_14", - "PCIE_CFGDEVCONTROL2IDOREQEN", - "PCIE_EE4C2_16", - "PCIE_PIPETXMARGIN0", - "PCIE_MONITOR_N_5", - "PCIE_LOGIC_OUTS_B13_L_8", - "PCIE_WW2A3_18", - "PCIE_LOGIC_OUTS_B15_L_14", - "PCIE_IMUX47_R_3", - "PCIE_IMUX37_R_10", - "PCIE_IMUX33_L_15", - "PCIE_IMUX7_R_4", - "PCIE_EE2A0_9", - "PCIE_LOGIC_OUTS_B23_R_17", - "PCIE_LOGIC_OUTS_B17_L_8", - "PCIE_NW4END0_11", - "PCIE_NW4A0_11", - "PCIE_EE4A2_3", - "PCIE_WW4B1_6", - "PCIE_LOGIC_OUTS_B7_L_13", - "PCIE_WW4END2_5", - "PCIE_BLOCK_OUTS_B1_L_17", - "PCIE_LH11_17", - "PCIE_IMUX47_L_10", - "PCIE_DBGVECB15", - "PCIE_NE2A1_9", - "PCIE_LH10_4", - "PCIE_EE4BEG3_4", - "PCIE_SW4A2_16", - "PCIE_IMUX17_L_5", - "PCIE_MIMRXRDATA8", - "PCIE_EL1BEG1_4", - "PCIE_NE2A1_4", - "PCIE_NE4BEG0_11", - "PCIE_CFGDEVID3", - "PCIE_IMUX8_R_3", - "PCIE_IMUX17_R_19", - "PCIE_NE4BEG3_12", - "PCIE_IMUX25_L_11", - "PCIE_IMUX39_L_18", - "PCIE_IMUX12_L_8", - "PCIE_BYP6_L_4", - "PCIE_CTRL1_L_19", - "PCIE_LOGIC_OUTS_B8_L_11", - "PCIE_EE4A3_17", - "PCIE_IMUX31_L_1", - "PCIE_BLOCK_OUTS_B2_R_9", - "PCIE_SE4BEG3_17", - "PCIE_ER1BEG1_11", - "PCIE_PIPERX2CHARISK1", - "PCIE_SE2A1_18", - "PCIE_TRNRD49", - "PCIE_PL2DIRECTEDLSTATE4", - "PCIE_IMUX9_L_18", - "PCIE_FAN0_R_8", - "PCIE_TRNTD8", - "PCIE_BLOCK_OUTS_B1_L_12", - "PCIE_LOGIC_OUTS_B5_L_15", - "PCIE_IMUX8_L_14", - "PCIE_XILUNCONNOUT12", - "PCIE_IMUX33_L_5", - "PCIE_CTRL1_R_7", - "PCIE_NE2A1_16", - "PCIE_MIMTXRDATA60", - "PCIE_IMUX8_L_13", - "PCIE_LOGIC_OUTS_B10_L_18", - "PCIE_CFGAERINTERRUPTMSGNUM1", - "PCIE_LOGIC_OUTS_B21_R_11", - "PCIE_IMUX11_L_7", - "PCIE_MIMTXRADDR11", - "PCIE_IMUX4_R_15", - "PCIE_WR1END1_10", - "PCIE_LOGIC_OUTS_B3_R_13", - "PCIE_BLOCK_OUTS_B3_L_19", - "PCIE_IMUX12_R_2", - "PCIE_IMUX35_L_5", - "PCIE_CFGROOTCONTROLPMEINTEN", - "PCIE_IMUX18_R_6", - "PCIE_TRNRNPREQ", - "PCIE_EE4C0_9", - "PCIE_NE4BEG3_14", - "PCIE_BLOCK_OUTS_B1_L_9", - "PCIE_IMUX2_R_6", - "PCIE_IMUX2_L_4", - "PCIE_IMUX3_L_16", - "PCIE_PIPERX7DATA1", - "PCIE_IMUX26_L_12", - "PCIE_NW2A1_3", - "PCIE_BYP3_L_19", - "PCIE_EE4C3_9", - "PCIE_CFGMGMTDI26", - "PCIE_FAN2_R_6", - "PCIE_SE2A3_0", - "PCIE_XILUNCONNOUT3", - "PCIE_CFGMSGDATA2", - "PCIE_EL1BEG1_16", - "PCIE_ER1BEG0_1", - "PCIE_BYP2_L_5", - "PCIE_NW4A1_10", - "PCIE_EL1BEG3_15", - "PCIE_USERCLK", - "PCIE_LOGIC_OUTS_B10_L_13", - "PCIE_IMUX20_R_5", - "PCIE_WL1END0_14", - "PCIE_IMUX44_R_17", - "PCIE_LH7_1", - "PCIE_LOGIC_OUTS_B18_R_15", - "PCIE_CFGMGMTDI27", - "PCIE_PIPETX5DATA6", - "PCIE_EL1BEG2_0", - "PCIE_TRNRD76", - "PCIE_IMUX43_R_3", - "PCIE_NW2A2_19", - "PCIE_PLDIRECTEDLINKCHANGE1", - "PCIE_IMUX10_L_17", - "PCIE_IMUX45_L_15", - "PCIE_IMUX14_L_10", - "PCIE_IMUX32_R_5", - "PCIE_IMUX18_L_4", - "PCIE_NE2A0_7", - "PCIE_PIPERX7STATUS0", - "PCIE_LOGIC_OUTS_B2_L_18", - "PCIE_IMUX38_R_9", - "PCIE_CFGINTERRUPTDI7", - "PCIE_IMUX3_R_3", - "PCIE_MIMTXRADDR1", - "PCIE_IMUX41_R_15", - "PCIE_BYP7_L_1", - "PCIE_EE4B0_5", - "PCIE_PLSELLNKRATE", - "PCIE_EE4BEG0_0", - "PCIE_IMUX26_L_10", - "PCIE_FAN4_L_10", - "PCIE_FAN0_L_17", - "PCIE_TRNTDLLPDATA10", - "PCIE_CLK0_L_11", - "PCIE_IMUX9_L_16", - "PCIE_PIPETX5DATA8", - "PCIE_CFGINTERRUPTN", - "PCIE_TRNRDLLPDATA45", - "PCIE_IMUX41_R_6", - "PCIE_TRNRD75", - "PCIE_LOGIC_OUTS_B10_R_10", - "PCIE_LOGIC_OUTS_B14_L_10", - "PCIE_NE4BEG3_11", - "PCIE_MIMTXRDATA25", - "PCIE_LH1_18", - "PCIE_MIMTXRDATA31", - "PCIE_LOGIC_OUTS_B8_R_13", - "PCIE_NW4END1_15", - "PCIE_IMUX43_R_4", - "PCIE_IMUX39_L_19", - "PCIE_BYP5_L_6", - "PCIE_CTRL1_R_1", - "PCIE_FAN4_L_19", - "PCIE_IMUX36_L_10", - "PCIE_IMUX1_L_5", - "PCIE_CTRL1_R_15", - "PCIE_NW2A0_14", - "PCIE_BYP6_L_12", - "PCIE_WW4A0_11", - "PCIE_CFGERRINTERNALUNCORN", - "PCIE_IMUX0_L_9", - "PCIE_SW2A1_4", - "PCIE_LOGIC_OUTS_B2_R_13", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", - "PCIE_PLDBGMODE1", - "PCIE_IMUX36_R_13", - "PCIE_CTRL1_R_17", - "PCIE_IMUX11_R_1", - "PCIE_TRNRBARHIT2", - "PCIE_LOGIC_OUTS_B6_R_10", - "PCIE_BYP0_L_14", - "PCIE_EE2BEG0_6", - "PCIE_LOGIC_OUTS_B19_R_13", - "PCIE_DBGVECB17", - "PCIE_IMUX34_R_13", - "PCIE_IMUX28_L_17", - "PCIE_IMUX29_L_17", - "PCIE_EE4BEG2_10", - "PCIE_LOGIC_OUTS_B8_L_9", - "PCIE_NE2A0_11", - "PCIE_FAN7_L_5", - "PCIE_WL1END3_3", - "PCIE_IMUX16_R_10", - "PCIE_EE4C0_14", - "PCIE_TRNRD21", - "PCIE_CFGERRTLPCPLHEADER30", - "PCIE_SW4A3_11", - "PCIE_IMUX38_R_15", - "PCIE_FAN0_R_15", - "PCIE_BLOCK_OUTS_B3_R_15", - "PCIE_IMUX6_R_17", - "PCIE_PIPETX5DATA10", - "PCIE_IMUX13_R_0", - "PCIE_CFGMGMTDO28", - "PCIE_LH3_0", - "PCIE_PIPETX0DATA13", - "PCIE_TRNRD19", - "PCIE_SE2A2_15", - "PCIE_SW4A2_13", - "PCIE_EE2A3_16", - "PCIE_IMUX11_L_5", - "PCIE_LOGIC_OUTS_B17_L_9", - "PCIE_EE2A1_4", - "PCIE_FAN4_R_6", - "PCIE_CFGMGMTDO12", - "PCIE_TRNTDLLPDATA13", - "PCIE_PIPETX6DATA5", - "PCIE_IMUX18_R_7", - "PCIE_LOGIC_OUTS_B16_L_9", - "PCIE_LOGIC_OUTS_B14_R_5", - "PCIE_IMUX16_R_5", - "PCIE_IMUX16_L_6", - "PCIE_ER1BEG1_7", - "PCIE_IMUX14_L_13", - "PCIE_LH5_14", - "PCIE_IMUX25_L_0", - "PCIE_IMUX15_L_3", - "PCIE_LOGIC_OUTS_B22_L_19", - "PCIE_IMUX29_L_8", - "PCIE_MIMTXRDATA30", - "PCIE_IMUX47_R_0", - "PCIE_WW2END3_1", - "PCIE_CFGSUBSYSVENDID13", - "PCIE_PMVSELECT1", - "PCIE_DRPADDR6", - "PCIE_FAN4_R_16", - "PCIE_MIMRXRDATA36", - "PCIE_IMUX18_R_1", - "PCIE_IMUX38_L_18", - "PCIE_BLOCK_OUTS_B2_R_14", - "PCIE_IMUX19_L_15", - "PCIE_DBGVECB41", - "PCIE_IMUX9_R_17", - "PCIE_WW2A3_3", - "PCIE_LOGIC_OUTS_B8_L_3", - "PCIE_IMUX23_L_19", - "PCIE_LOGIC_OUTS_B22_R_1", - "PCIE_IMUX46_R_5", - "PCIE_PIPERX5CHANISALIGNED", - "PCIE_TL2ERRRXOVERFLOW", - "PCIE_IMUX3_R_2", - "PCIE_LOGIC_OUTS_B3_L_19", - "PCIE_IMUX32_L_4", - "PCIE_IMUX2_R_3", - "PCIE_WL1END1_10", - "PCIE_FAN1_R_15", - "PCIE_SW4END2_19", - "PCIE_IMUX18_R_12", - "PCIE_WL1END0_4", - "PCIE_SCANMODEN", - "PCIE_FAN7_R_10", - "PCIE_IMUX17_L_10", - "PCIE_PIPERX2DATA10", - "PCIE_IMUX10_L_6", - "PCIE_LH7_14", - "PCIE_NW4END3_6", - "PCIE_SW4END2_15", - "PCIE_IMUX10_R_6", - "PCIE_IMUX28_R_3", - "PCIE_LOGIC_OUTS_B20_R_10", - "PCIE_EE4A2_0", - "PCIE_CFGSUBSYSID4", - "PCIE_IMUX16_L_15", - "PCIE_NE4C0_8", - "PCIE_NW2A0_0", - "PCIE_NW2A3_4", - "PCIE_EE4C0_0", - "PCIE_EE2BEG2_10", - "PCIE_CLK1_R_13", - "PCIE_TRNTDLLPDATA22", - "PCIE_PIPERX5DATA11", - "PCIE_IMUX46_L_18", - "PCIE_FAN1_R_10", - "PCIE_PIPERX5DATA0", - "PCIE_TRNRSRCRDY", - "PCIE_CTRL1_R_6", - "PCIE_SW4END1_11", - "PCIE_MIMTXWDATA37", - "PCIE_MIMTXWDATA0", - "PCIE_BYP1_R_17", - "PCIE_FAN3_R_4", - "PCIE_MIMTXRDATA21", - "PCIE_WR1END0_13", - "PCIE_IMUX43_R_17", - "PCIE_IMUX19_R_12", - "PCIE_IMUX39_L_2", - "PCIE_LH7_2", - "PCIE_CFGMSGRECEIVEDPMASNAK", - "PCIE_IMUX19_R_14", - "PCIE_WW4B0_5", - "PCIE_TRNFCCPLH3", - "PCIE_WW2END3_8", - "PCIE_LH4_14", - "PCIE_SW4END0_0", - "PCIE_EE2BEG2_19", - "PCIE_NW4A1_15", - "PCIE_WL1END2_11", - "PCIE_IMUX30_L_17", - "PCIE_TRNRD45", - "PCIE_IMUX0_R_8", - "PCIE_LOGIC_OUTS_B6_L_6", - "PCIE_DRPADDR5", - "PCIE_LOGIC_OUTS_B7_L_10", - "PCIE_FAN3_L_0", - "PCIE_LOGIC_OUTS_B10_R_4", - "PCIE_ER1BEG1_2", - "PCIE_CFGMGMTDI19", - "PCIE_SW4A2_8", - "PCIE_EE4C3_15", - "PCIE_LOGIC_OUTS_B2_L_9", - "PCIE_EE4B2_4", - "PCIE_MIMRXRDATA47", - "PCIE_IMUX34_R_9", - "PCIE_CFGDSN44", - "PCIE_IMUX0_R_17", - "PCIE_IMUX21_L_0", - "PCIE_CLK1_R_7", - "PCIE_LOGIC_OUTS_B18_L_2", - "PCIE_NW4A2_9", - "PCIE_SE2A0_14", - "PCIE_FAN2_L_8", - "PCIE_EL1BEG1_3", - "PCIE_BYP7_R_4", - "PCIE_LOGIC_OUTS_B6_L_0", - "PCIE_IMUX23_L_9", - "PCIE_PIPERX3POLARITY", - "PCIE_WW2A2_2", - "PCIE_NW2A3_0", - "PCIE_IMUX34_L_16", - "PCIE_WW4END2_0", - "PCIE_WW4B0_19", - "PCIE_FAN7_R_19", - "PCIE_LH3_19", - "PCIE_NE2A2_15", - "PCIE_IMUX14_L_0", - "PCIE_PIPERX5ELECIDLE", - "PCIE_IMUX41_L_15", - "PCIE_WL1END0_13", - "PCIE_EL1BEG2_17", - "PCIE_IMUX12_R_0", - "PCIE_LH1_19", - "PCIE_IMUX23_R_17", - "PCIE_NE2A1_12", - "PCIE_LOGIC_OUTS_B22_R_13", - "PCIE_IMUX9_L_9", - "PCIE_LOGIC_OUTS_B18_R_3", - "PCIE_TRNTD76", - "PCIE_SW4A0_13", - "PCIE_NE4C0_9", - "PCIE_IMUX1_L_13", - "PCIE_IMUX15_L_10", - "PCIE_EE4B0_3", - "PCIE_LOGIC_OUTS_B9_R_5", - "PCIE_IMUX44_R_0", - "PCIE_IMUX1_R_13", - "PCIE_SE4C1_11", - "PCIE_IMUX40_R_12", - "PCIE_IMUX40_L_10", - "PCIE_IMUX11_L_6", - "PCIE_PIPETX5DATA5", - "PCIE_MIMTXRDATA67", - "PCIE_LOGIC_OUTS_B0_R_0", - "PCIE_IMUX10_R_11", - "PCIE_SE4BEG2_17", - "PCIE_SW2A3_12", - "PCIE_NW4END0_19", - "PCIE_CTRL0_R_8", - "PCIE_LOGIC_OUTS_B5_R_2", - "PCIE_EE4A1_8", - "PCIE_SE4C0_7", - "PCIE_SE2A2_13", - "PCIE_SW4A1_2", - "PCIE_EE4B3_3", - "PCIE_IMUX40_R_0", - "PCIE_SE4C3_0", - "PCIE_IMUX33_R_11", - "PCIE_CFGMGMTDWADDR3", - "PCIE_BYP5_R_13", - "PCIE_IMUX38_L_16", - "PCIE_SE4C1_4", - "PCIE_IMUX33_L_18", - "PCIE_FAN7_R_14", - "PCIE_IMUX11_R_0", - "PCIE_LOGIC_OUTS_B8_R_17", - "PCIE_MIMTXWADDR4", - "PCIE_EE2BEG0_2", - "PCIE_IMUX27_R_11", - "PCIE_IMUX24_R_4", - "PCIE_IMUX22_L_16", - "PCIE_LOGIC_OUTS_B22_L_8", - "PCIE_LOGIC_OUTS_B9_L_5", - "PCIE_DBGSCLRB", - "PCIE_EDTCHANNELSIN7", - "PCIE_IMUX41_L_11", - "PCIE_MIMTXRDATA36", - "PCIE_CFGVCTCVCMAP4", - "PCIE_IMUX14_L_3", - "PCIE_NE2A0_14", - "PCIE_BLOCK_OUTS_B0_R_0", - "PCIE_WW2A1_10", - "PCIE_IMUX46_R_7", - "PCIE_MIMRXWDATA59", - "PCIE_IMUX22_R_17", - "PCIE_SE4BEG3_9", - "PCIE_CFGINTERRUPTDI4", - "PCIE_CFGERRTLPCPLHEADER8", - "PCIE_LOGIC_OUTS_B23_L_6", - "PCIE_LOGIC_OUTS_B4_L_11", - "PCIE_IMUX22_R_11", - "PCIE_LOGIC_OUTS_B19_L_13", - "PCIE_WR1END2_9", - "PCIE_EE4BEG1_8", - "PCIE_LOGIC_OUTS_B18_R_1", - "PCIE_LH3_12", - "PCIE_IMUX3_R_17", - "PCIE_SE4C1_7", - "PCIE_IMUX8_R_15", - "PCIE_PIPERX2DATA2", - "PCIE_LOGIC_OUTS_B12_L_18", - "PCIE_IMUX45_L_6", - "PCIE_LOGIC_OUTS_B22_R_16", - "PCIE_MONITOR_P_7", - "PCIE_EL1BEG2_6", - "PCIE_LOGIC_OUTS_B20_L_6", - "PCIE_LOGIC_OUTS_B1_R_7", - "PCIE_LOGIC_OUTS_B21_R_2", - "PCIE_MIMTXWDATA58", - "PCIE_LOGIC_OUTS_B15_L_15", - "PCIE_LH2_5", - "PCIE_WW2END3_12", - "PCIE_TRNTD70", - "PCIE_BYP3_L_3", - "PCIE_LOGIC_OUTS_B4_L_18", - "PCIE_IMUX40_L_15", - "PCIE_CFGVCTCVCMAP2", - "PCIE_IMUX32_L_16", - "PCIE_SE4C1_9", - "PCIE_TRNTD120", - "PCIE_SW2A2_19", - "PCIE_IMUX22_R_4", - "PCIE_LOGIC_OUTS_B21_R_17", - "PCIE_PIPERX1VALID", - "PCIE_WW4END1_5", - "PCIE_ER1BEG1_5", - "PCIE_WR1END1_11", - "PCIE_BLOCK_OUTS_B0_L_9", - "PCIE_LOGIC_OUTS_B0_L_17", - "PCIE_IMUX8_L_2", - "PCIE_LOGIC_OUTS_B0_R_12", - "PCIE_PIPERX5DATA13", - "PCIE_CTRL0_L_3", - "PCIE_IMUX43_L_3", - "PCIE_IMUX10_R_2", - "PCIE_LOGIC_OUTS_B22_R_6", - "PCIE_MIMRXRDATA39", - "PCIE_LOGIC_OUTS_B20_R_8", - "PCIE_ER1BEG1_19", - "PCIE_SE4BEG0_17", - "PCIE_LOGIC_OUTS_B11_L_12", - "PCIE_FAN6_L_15", - "PCIE_LOGIC_OUTS_B15_L_10", - "PCIE_FAN3_L_11", - "PCIE_BYP5_L_16", - "PCIE_NE4C2_5", - "PCIE_LOGIC_OUTS_B19_R_9", - "PCIE_SW4END0_11", - "PCIE_LOGIC_OUTS_B17_L_16", - "PCIE_LOGIC_OUTS_B2_R_9", - "PCIE_NW4END2_4", - "PCIE_SE2A1_15", - "PCIE_FAN5_L_11", - "PCIE_LOGIC_OUTS_B7_L_5", - "PCIE_IMUX9_L_3", - "PCIE_EE2BEG2_12", - "PCIE_BLOCK_OUTS_B1_L_13", - "PCIE_IMUX5_L_9", - "PCIE_FAN1_L_1", - "PCIE_WR1END1_0", - "PCIE_IMUX13_L_0", - "PCIE_LOGIC_OUTS_B23_R_2", - "PCIE_WL1END2_2", - "PCIE_PIPERX3DATA2", - "PCIE_IMUX15_L_13", - "PCIE_EE4B3_8", - "PCIE_DBGVECA58", - "PCIE_TL2ERRHDR26", - "PCIE_IMUX14_R_7", - "PCIE_LH9_1", - "PCIE_IMUX40_L_8", - "PCIE_IMUX46_R_4", - "PCIE_IMUX32_L_3", - "PCIE_DBGVECA54", - "PCIE_CFGERRAERHEADERLOG30", - "PCIE_SE4C3_18", - "PCIE_WR1END0_6", - "PCIE_PIPETX4DATA13", - "PCIE_NW4A2_12", - "PCIE_WL1END0_10", - "PCIE_FAN6_L_13", - "PCIE_LOGIC_OUTS_B6_R_3", - "PCIE_WW2A0_16", - "PCIE_MIMRXWDATA61", - "PCIE_CFGREVID2", - "PCIE_IMUX40_R_3", - "PCIE_LOGIC_OUTS_B6_R_15", - "PCIE_IMUX3_L_18", - "PCIE_BLOCK_OUTS_B3_L_7", - "PCIE_NW4A3_7", - "PCIE_PIPETX2DATA5", - "PCIE_EE4A1_7", - "PCIE_LOGIC_OUTS_B20_R_11", - "PCIE_EL1BEG3_11", - "PCIE_DBGVECA56", - "PCIE_FAN4_L_9", - "PCIE_FAN0_L_10", - "PCIE_LOGIC_OUTS_B17_R_1", - "PCIE_FAN1_R_9", - "PCIE_CFGERRAERHEADERLOG50", - "PCIE_CFGDSN13", - "PCIE_WW2END3_11", - "PCIE_IMUX2_R_12", - "PCIE_FAN5_L_15", - "PCIE_EE2A0_0", - "PCIE_CFGMGMTDO22", - "PCIE_WW2END1_0", - "PCIE_TRNRD109", - "PCIE_LH9_19", - "PCIE_EE2A0_8", - "PCIE_PIPETX6CHARISK0", - "PCIE_IMUX22_L_4", - "PCIE_IMUX18_L_18", - "PCIE_IMUX15_L_5", - "PCIE_EE2A0_19", - "PCIE_IMUX40_L_12", - "PCIE_TL2ASPMSUSPENDREQ", - "PCIE_MIMTXWDATA12", - "PCIE_FAN2_L_14", - "PCIE_MIMTXWADDR3", - "PCIE_FAN3_R_17", - "PCIE_CLK1_L_15", - "PCIE_LOGIC_OUTS_B22_R_4", - "PCIE_PIPETX5CHARISK0", - "PCIE_IMUX28_R_0", - "PCIE_TRNFCNPH2", - "PCIE_LOGIC_OUTS_B12_L_4", - "PCIE_NE4BEG1_17", - "PCIE_CFGMGMTBYTEENN0", - "PCIE_LOGIC_OUTS_B14_L_7", - "PCIE_NE2A3_18", - "PCIE_NW4END2_2", - "PCIE_SE4BEG0_10", - "PCIE_IMUX12_L_2", - "PCIE_LOGIC_OUTS_B11_R_7", - "PCIE_LOGIC_OUTS_B6_R_16", - "PCIE_WW2A2_4", - "PCIE_CFGMGMTDO26", - "PCIE_CFGAERECRCCHECKEN", - "PCIE_BLOCK_OUTS_B1_L_8", - "PCIE_CFGSUBSYSID7", - "PCIE_NE4BEG2_9", - "PCIE_CFGERRAERHEADERLOG57", - "PCIE_IMUX38_L_7", - "PCIE_IMUX33_L_9", - "PCIE_IMUX34_L_19", - "PCIE_LOGIC_OUTS_B3_L_14", - "PCIE_PIPERX6DATA0", - "PCIE_FAN5_L_0", - "PCIE_IMUX43_L_6", - "PCIE_IMUX37_R_3", - "PCIE_CFGMGMTDO5", - "PCIE_WW2END3_16", - "PCIE_LOGIC_OUTS_B0_L_14", - "PCIE_IMUX16_L_18", - "PCIE_DBGVECA22", - "PCIE_LOGIC_OUTS_B14_R_9", - "PCIE_IMUX42_R_19", - "PCIE_MIMRXRDATA20", - "PCIE_WW4B1_9", - "PCIE_TRNRBARHIT7", - "PCIE_FAN7_L_4", - "PCIE_SW4A3_4", - "PCIE_FAN0_R_9", - "PCIE_WW4END2_10", - "PCIE_IMUX45_L_1", - "PCIE_EE4A0_7", - "PCIE_IMUX17_R_10", - "PCIE_MIMTXRDATA17", - "PCIE_CFGMGMTDO31", - "PCIE_IMUX23_L_7", - "PCIE_LH5_13", - "PCIE_WW4B3_15", - "PCIE_TRNTD20", - "PCIE_IMUX16_L_8", - "PCIE_IMUX40_L_11", - "PCIE_IMUX42_R_0", - "PCIE_BLOCK_OUTS_B0_L_12", - "PCIE_EE4C3_1", - "PCIE_IMUX42_L_19", - "PCIE_WW4END1_19", - "PCIE_WW4B2_5", - "PCIE_BYP4_R_18", - "PCIE_SE4C0_1", - "PCIE_TRNTD49", - "PCIE_MIMRXWEN", - "PCIE_FAN3_R_7", - "PCIE_LOGIC_OUTS_B13_R_14", - "PCIE_XILUNCONNOUT5", - "PCIE_MONITOR_P_19", - "PCIE_SW4A0_14", - "PCIE_DBGSCLRK", - "PCIE_WW4C1_6", - "PCIE_IMUX23_L_5", - "PCIE_LOGIC_OUTS_B0_L_13", - "PCIE_CLK1_R_16", - "PCIE_SE4BEG2_16", - "PCIE_NW2A2_4", - "PCIE_IMUX37_L_16", - "PCIE_IMUX27_R_9", - "PCIE_CFGDSN3", - "PCIE_NW2A2_10", - "PCIE_LOGIC_OUTS_B13_R_2", - "PCIE_EE2BEG0_1", - "PCIE_LOGIC_OUTS_B9_R_8", - "PCIE_NE4BEG2_0", - "PCIE_WW4END0_18", - "PCIE_EDTCHANNELSOUT8", - "PCIE_MIMRXRADDR3", - "PCIE_IMUX0_L_10", - "PCIE_NE2A2_16", - "PCIE_TRNFCPD3", - "PCIE_IMUX2_R_17", - "PCIE_TRNTDLLPDATA23", - "PCIE_TRNFCCPLD8", - "PCIE_WL1END2_14", - "PCIE_CFGSUBSYSID1", - "PCIE_LOGIC_OUTS_B23_R_4", - "PCIE_IMUX6_R_5", - "PCIE_LL2PROTOCOLERR", - "PCIE_IMUX36_R_8", - "PCIE_BYP1_L_11", - "PCIE_TRNRDLLPDATA19", - "PCIE_IMUX38_L_3", - "PCIE_IMUX36_L_5", - "PCIE_ER1BEG2_3", - "PCIE_DBGVECB16", - "PCIE_CFGMGMTDI16", - "PCIE_LOGIC_OUTS_B18_R_4", - "PCIE_XILUNCONNOUT7", - "PCIE_EE4C0_10", - "PCIE_IMUX34_L_13", - "PCIE_SW4END0_12", - "PCIE_CFGERRAERHEADERLOG113", - "PCIE_IMUX35_R_17", - "PCIE_IMUX42_L_8", - "PCIE_FAN5_L_19", - "PCIE_TRNTDLLPDATA30", - "PCIE_SE4BEG3_6", - "PCIE_WR1END1_12", - "PCIE_CFGDEVCONTROL2IDOCPLEN", - "PCIE_TL2ERRHDR43", - "PCIE_LH10_11", - "PCIE_LOGIC_OUTS_B16_R_0", - "PCIE_IMUX44_L_3", - "PCIE_TRNRD63", - "PCIE_MIMRXWDATA46", - "PCIE_DBGVECB42", - "PCIE_BLOCK_OUTS_B2_L_1", - "PCIE_PIPERX5DATA14", - "PCIE_IMUX29_L_12", - "PCIE_TRNTD80", - "PCIE_FAN4_R_19", - "PCIE_PIPETX2DATA4", - "PCIE_SW2A3_15", - "PCIE_IMUX34_L_8", - "PCIE_CFGERRAERHEADERLOG92", - "PCIE_SW4END2_1", - "PCIE_IMUX9_L_4", - "PCIE_LOGIC_OUTS_B1_R_19", - "PCIE_MIMTXRADDR12", - "PCIE_CFGERRAERHEADERLOG65", - "PCIE_IMUX21_R_1", - "PCIE_LOGIC_OUTS_B0_R_11", - "PCIE_IMUX1_R_15", - "PCIE_NE2A1_7", - "PCIE_PIPETX5DATA13", - "PCIE_PIPERX1PHYSTATUS", - "PCIE_LL2BADDLLPERR", - "PCIE_CFGDEVSTATUSFATALERRDETECTED", - "PCIE_WW4C3_18", - "PCIE_CFGSUBSYSID8", - "PCIE_IMUX41_R_12", - "PCIE_LOGIC_OUTS_B22_R_3", - "PCIE_IMUX34_R_15", - "PCIE_BYP7_R_9", - "PCIE_IMUX21_R_7", - "PCIE_EL1BEG1_6", - "PCIE_TRNRDLLPDATA14", - "PCIE_SW2A0_9", - "PCIE_TRNTD81", - "PCIE_TL2ERRHDR58", - "PCIE_CLK0_L_1", - "PCIE_MONITOR_P_1", - "PCIE_EE4B2_13", - "PCIE_IMUX24_R_10", - "PCIE_IMUX28_L_7", - "PCIE_TRNTD63", - "PCIE_SE4C0_9", - "PCIE_CFGMGMTDO3", - "PCIE_LH8_12", - "PCIE_CTRL0_L_14", - "PCIE_MIMTXRADDR5", - "PCIE_CFGERRAERHEADERLOG75", - "PCIE_FAN3_L_8", - "PCIE_BYP7_L_3", - "PCIE_IMUX37_R_17", - "PCIE_IMUX41_L_19", - "PCIE_LOGIC_OUTS_B14_R_2", - "PCIE_BYP2_L_6", - "PCIE_IMUX31_L_12", - "PCIE_ER1BEG2_1", - "PCIE_WR1END1_4", - "PCIE_PIPETX4DATA5", - "PCIE_LOGIC_OUTS_B18_R_8", - "PCIE_CFGERRAERHEADERLOG58", - "PCIE_LOGIC_OUTS_B16_L_4", - "PCIE_PIPERX7DATA12", - "PCIE_NE4BEG3_15", - "PCIE_PIPETX5DATA2", - "PCIE_LOGIC_OUTS_B22_L_16", - "PCIE_ER1BEG2_0", - "PCIE_IMUX4_L_8", - "PCIE_SE4C0_10", - "PCIE_ER1BEG1_12", - "PCIE_IMUX3_L_8", - "PCIE_LOGIC_OUTS_B22_R_18", - "PCIE_SE4C0_16", - "PCIE_SW4A2_1", - "PCIE_EE4B0_2", - "PCIE_LOGIC_OUTS_B23_L_13", - "PCIE_WW2END2_15", - "PCIE_LOGIC_OUTS_B2_R_17", - "PCIE_LOGIC_OUTS_B2_R_5", - "PCIE_IMUX13_R_3", - "PCIE_IMUX47_R_6", - "PCIE_TL2ERRHDR15", - "PCIE_EL1BEG2_15", - "PCIE_MIMRXRDATA37", - "PCIE_BYP0_L_6", - "PCIE_FAN3_R_3", - "PCIE_SE2A3_8", - "PCIE_IMUX24_L_3", - "PCIE_WW4B2_9", - "PCIE_WW4B2_17", - "PCIE_PLDBGVEC2", - "PCIE_CFGERRTLPCPLHEADER13", - "PCIE_WW4A3_12", - "PCIE_LOGIC_OUTS_B23_L_4", - "PCIE_IMUX14_R_6", - "PCIE_CTRL0_L_10", - "PCIE_IMUX47_R_4", - "PCIE_DRPDO6", - "PCIE_NW2A3_11", - "PCIE_MONITOR_N_3", - "PCIE_MONITOR_N_6", - "PCIE_NW4END3_7", - "PCIE_LH1_15", - "PCIE_IMUX0_R_15", - "PCIE_PIPERX4DATA13", - "PCIE_WR1END1_16", - "PCIE_LH1_0", - "PCIE_EE4B0_9", - "PCIE_EE4BEG1_6", - "PCIE_WW4C3_5", - "PCIE_LOGIC_OUTS_B8_R_1", - "PCIE_MIMRXWDATA37", - "PCIE_IMUX47_R_13", - "PCIE_NW4A1_18", - "PCIE_NE4BEG0_10", - "PCIE_NE4BEG3_4", - "PCIE_NE4C0_13", - "PCIE_CLK0_R_3", - "PCIE_LOGIC_OUTS_B19_R_17", - "PCIE_CFGERRAERHEADERLOG49", - "PCIE_LOGIC_OUTS_B11_R_14", - "PCIE_TRNTSOF", - "PCIE_BLOCK_OUTS_B3_L_6", - "PCIE_PIPERX2ELECIDLE", - "PCIE_NW2A3_6", - "PCIE_LOGIC_OUTS_B12_R_19", - "PCIE_IMUX0_L_6", - "PCIE_EE4A0_6", - "PCIE_EE4BEG0_15", - "PCIE_MIMTXWDATA20", - "PCIE_LOGIC_OUTS_B2_L_5", - "PCIE_CTRL0_R_0", - "PCIE_LOGIC_OUTS_B1_L_15", - "PCIE_CFGERRNORECOVERYN", - "PCIE_IMUX32_R_11", - "PCIE_NW4A1_3", - "PCIE_WW2END1_19", - "PCIE_WW4END3_0", - "PCIE_PLDBGVEC6", - "PCIE_NE4C1_19", - "PCIE_BYP6_L_8", - "PCIE_WL1END0_1", - "PCIE_IMUX26_R_8", - "PCIE_LOGIC_OUTS_B14_R_15", - "PCIE_WW4C3_6", - "PCIE_PIPETXRATE", - "PCIE_PIPETX6DATA8", - "PCIE_NE4BEG0_6", - "PCIE_WW4B2_18", - "PCIE_IMUX29_L_16", - "PCIE_BYP0_R_10", - "PCIE_BYP6_R_8", - "PCIE_IMUX16_R_4", - "PCIE_WW4B3_16", - "PCIE_NE2A1_15", - "PCIE_PIPERX7DATA9", - "PCIE_MIMTXWADDR12", - "PCIE_LOGIC_OUTS_B6_R_5", - "PCIE_IMUX44_R_1", - "PCIE_IMUX16_L_11", - "PCIE_LOGIC_OUTS_B4_R_5", - "PCIE_LOGIC_OUTS_B12_R_3", - "PCIE_IMUX1_L_10", - "PCIE_IMUX36_R_5", - "PCIE_IMUX3_R_9", - "PCIE_CFGINTERRUPTDI5", - "PCIE_LH11_18", - "PCIE_IMUX44_L_6", - "PCIE_NW4A2_6", - "PCIE_IMUX27_L_7", - "PCIE_CTRL0_R_1", - "PCIE_FAN2_L_7", - "PCIE_SW4END2_18", - "PCIE_IMUX10_L_19", - "PCIE_IMUX6_L_7", - "PCIE_WW4A2_3", - "PCIE_BLOCK_OUTS_B1_L_15", - "PCIE_LOGIC_OUTS_B21_R_9", - "PCIE_BLOCK_OUTS_B1_R_3", - "PCIE_MIMRXRDATA58", - "PCIE_BYP6_L_13", - "PCIE_EE4C3_3", - "PCIE_NW2A1_16", - "PCIE_MIMRXWDATA17", - "PCIE_CFGMGMTDO6", - "PCIE_IMUX44_L_12", - "PCIE_IMUX18_L_3", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", - "PCIE_EE4BEG3_2", - "PCIE_EE4C3_2", - "PCIE_WW4A0_5", - "PCIE_SW2A2_10", - "PCIE_NW4END1_6", - "PCIE_LOGIC_OUTS_B8_R_7", - "PCIE_PIPERX6DATA12", - "PCIE_SE4C1_16", - "PCIE_LOGIC_OUTS_B1_R_0", - "PCIE_LOGIC_OUTS_B7_R_7", - "PCIE_WW4END0_17", - "PCIE_EE4A2_1", - "PCIE_NW4A0_8", - "PCIE_CFGMSGRECEIVEDPMPME", - "PCIE_NW4END2_6", - "PCIE_EE2BEG1_19", - "PCIE_DBGVECA5", - "PCIE_BYP2_L_11", - "PCIE_IMUX42_L_1", - "PCIE_TRNRD79", - "PCIE_PIPETX0DATA11", - "PCIE_MIMTXRDATA16", - "PCIE_CFGSUBSYSID14", - "PCIE_FAN7_L_3", - "PCIE_EL1BEG0_3", - "PCIE_TL2ERRHDR27", - "PCIE_CFGERRAERHEADERLOG98", - "PCIE_IMUX39_L_16", - "PCIE_LOGIC_OUTS_B5_L_8", - "PCIE_SE4C2_6", - "PCIE_EE4B0_10", - "PCIE_BLOCK_OUTS_B3_R_11", - "PCIE_IMUX42_R_2", - "PCIE_EE4C0_19", - "PCIE_LOGIC_OUTS_B0_R_9", - "PCIE_CFGTRANSACTIONADDR5", - "PCIE_LOGIC_OUTS_B18_R_10", - "PCIE_IMUX0_L_0", - "PCIE_EE4BEG3_0", - "PCIE_LOGIC_OUTS_B6_L_7", - "PCIE_LOGIC_OUTS_B7_L_14", - "PCIE_LOGIC_OUTS_B18_L_11", - "PCIE_NW4END3_13", - "PCIE_IMUX20_R_11", - "PCIE_PLINITIALLINKWIDTH2", - "PCIE_SE4C1_8", - "PCIE_EE4B2_3", - "PCIE_IMUX11_L_9", - "PCIE_WW4B1_16", - "PCIE_IMUX26_R_14", - "PCIE_IMUX33_R_19", - "PCIE_IMUX24_L_4", - "PCIE_EE2A1_14", - "PCIE_LH1_6", - "PCIE_BLOCK_OUTS_B2_L_17", - "PCIE_BYP6_R_1", - "PCIE_DRPDO4", - "PCIE_WW4B0_1", - "PCIE_BYP6_R_12", - "PCIE_WW2A2_12", - "PCIE_IMUX9_R_2", - "PCIE_LOGIC_OUTS_B4_R_2", - "PCIE_LOGIC_OUTS_B14_L_14", - "PCIE_ER1BEG0_3", - "PCIE_EE4B3_2", - "PCIE_MIMRXWDATA48", - "PCIE_LOGIC_OUTS_B8_L_16", - "PCIE_FAN5_L_5", - "PCIE_CFGDSN27", - "PCIE_NE4BEG0_5", - "PCIE_NE4C0_3", - "PCIE_IMUX28_L_3", - "PCIE_SW4A0_1", - "PCIE_BLOCK_OUTS_B1_L_3", - "PCIE_PIPERX6CHARISK1", - "PCIE_IMUX35_R_5", - "PCIE_LOGIC_OUTS_B5_L_17", - "PCIE_CFGERRAERHEADERLOG123", - "PCIE_WW4END0_7", - "PCIE_PIPERX2DATA5", - "PCIE_LH4_11", - "PCIE_IMUX39_L_11", - "PCIE_PIPETX6POWERDOWN0", - "PCIE_FAN0_R_11", - "PCIE_EE2BEG3_18", - "PCIE_CFGERRAERHEADERLOG26", - "PCIE_EE4A1_18", - "PCIE_SE2A1_14", - "PCIE_IMUX9_R_9", - "PCIE_NE4C2_12", - "PCIE_DBGVECB62", - "PCIE_EE4C2_9", - "PCIE_IMUX23_R_5", - "PCIE_WL1END1_11", - "PCIE_WW4A1_6", - "PCIE_BYP3_L_17", - "PCIE_CFGDSN50", - "PCIE_IMUX37_R_1", - "PCIE_LOGIC_OUTS_B13_L_3", - "PCIE_TRNTD96", - "PCIE_LH6_1", - "PCIE_TRNRD1", - "PCIE_CFGMGMTDI29", - "PCIE_LH10_8", - "PCIE_CFGERRTLPCPLHEADER20", - "PCIE_IMUX20_L_14", - "PCIE_PL2DIRECTEDLSTATE0", - "PCIE_CTRL0_L_6", - "PCIE_LOGIC_OUTS_B22_L_7", - "PCIE_FAN1_L_8", - "PCIE_TRNTD39", - "PCIE_CFGERRAERHEADERLOG87", - "PCIE_IMUX30_R_8", - "PCIE_IMUX33_R_8", - "PCIE_NW2A3_1", - "PCIE_IMUX2_L_8", - "PCIE_DRPDI1", - "PCIE_IMUX27_R_7", - "PCIE_MONITOR_P_12", - "PCIE_IMUX18_R_5", - "PCIE_TRNRDLLPDATA32", - "PCIE_ER1BEG3_16", - "PCIE_IMUX26_R_16", - "PCIE_PIPERX0STATUS1", - "PCIE_CLK0_R_6", - "PCIE_LOGIC_OUTS_B5_L_18", - "PCIE_WW4A0_2", - "PCIE_PIPETXMARGIN2", - "PCIE_IMUX21_L_6", - "PCIE_SW4A3_12", - "PCIE_NW4A0_0", - "PCIE_BLOCK_OUTS_B2_R_10", - "PCIE_PIPERX6ELECIDLE", - "PCIE_WW4B2_1", - "PCIE_WW2END0_10", - "PCIE_PIPERX3DATA4", - "PCIE_IMUX17_R_4", - "PCIE_CFGDEVCONTROLURERRREPORTINGEN", - "PCIE_CFGVCTCVCMAP1", - "PCIE_FAN5_L_3", - "PCIE_CFGERRTLPCPLHEADER31", - "PCIE_IMUX5_R_7", - "PCIE_IMUX21_R_6", - "PCIE_LOGIC_OUTS_B21_R_18", - "PCIE_BYP3_R_2", - "PCIE_LOGIC_OUTS_B6_L_2", - "PCIE_LOGIC_OUTS_B19_L_11", - "PCIE_TRNTDLLPDATA2", - "PCIE_IMUX30_L_5", - "PCIE_EE2A0_14", - "PCIE_TRNTDSTRDY0", - "PCIE_FAN7_L_7", - "PCIE_IMUX32_R_13", - "PCIE_LOGIC_OUTS_B11_R_2", - "PCIE_IMUX24_L_19", - "PCIE_MIMRXWDATA55", - "PCIE_NW4A3_12", - "PCIE_PIPERX6POLARITY", - "PCIE_CFGREVID0", - "PCIE_LOGIC_OUTS_B14_L_5", - "PCIE_MONITOR_N_2", - "PCIE_BLOCK_OUTS_B1_R_7", - "PCIE_PIPERX4DATA14", - "PCIE_FAN6_L_9", - "PCIE_IMUX30_R_16", - "PCIE_PIPERX6DATA8", - "PCIE_BYP2_L_0", - "PCIE_MIMRXWDATA21", - "PCIE_DRPDI3", - "PCIE_IMUX23_R_10", - "PCIE_EE4C0_18", - "PCIE_TRNRDLLPDATA8", - "PCIE_WW4B1_0", - "PCIE_BYP7_R_8", - "PCIE_TRNRD104", - "PCIE_CFGERRPOSTEDN", - "PCIE_WW4END0_14", - "PCIE_BYP6_R_19", - "PCIE_IMUX38_R_0", - "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", - "PCIE_PLPHYLNKUPN", - "PCIE_XILUNCONNOUT16", - "PCIE_BYP4_L_11", - "PCIE_IMUX28_R_6", - "PCIE_LOGIC_OUTS_B3_L_12", - "PCIE_PIPETX4POWERDOWN0", - "PCIE_WR1END3_18", - "PCIE_IMUX41_L_0", - "PCIE_IMUX15_R_10", - "PCIE_IMUX21_R_8", - "PCIE_IMUX3_R_15", - "PCIE_IMUX30_L_2", - "PCIE_SW4END0_19", - "PCIE_SW4END1_14", - "PCIE_NE4C1_17", - "PCIE_EDTCHANNELSIN6", - "PCIE_IMUX10_L_2", - "PCIE_WW4A2_18", - "PCIE_IMUX44_R_7", - "PCIE_NW4END2_0", - "PCIE_CFGERRTLPCPLHEADER35", - "PCIE_CTRL1_L_14", - "PCIE_WW2END2_12", - "PCIE_IMUX1_R_17", - "PCIE_EE2BEG1_17", - "PCIE_LOGIC_OUTS_B12_R_9", - "PCIE_PIPETX3DATA8", - "PCIE_BYP4_L_10", - "PCIE_EE4BEG0_9", - "PCIE_CLK0_L_17", - "PCIE_LOGIC_OUTS_B3_R_5", - "PCIE_IMUX32_L_11", - "PCIE_DBGVECA45", - "PCIE_IMUX21_L_15", - "PCIE_IMUX47_R_10", - "PCIE_CFGVENDID11", - "PCIE_LOGIC_OUTS_B2_R_15", - "PCIE_BYP1_L_13", - "PCIE_SW4A3_13", - "PCIE_FAN5_R_7", - "PCIE_IMUX23_L_8", - "PCIE_DBGVECC6", - "PCIE_PLDIRECTEDLINKWIDTH1", - "PCIE_WW2A0_10", - "PCIE_LOGIC_OUTS_B1_R_12", - "PCIE_LOGIC_OUTS_B21_R_16", - "PCIE_TL2ERRHDR33", - "PCIE_NW2A2_0", - "PCIE_IMUX23_R_7", - "PCIE_LOGIC_OUTS_B20_L_18", - "PCIE_WW2END0_9", - "PCIE_NE4BEG0_16", - "PCIE_SE4BEG2_1", - "PCIE_IMUX34_L_14", - "PCIE_CFGDSDEVICENUMBER1", - "PCIE_IMUX31_R_5", - "PCIE_LOGIC_OUTS_B14_R_19", - "PCIE_IMUX41_L_1", - "PCIE_WW4A2_15", - "PCIE_SW2A3_5", - "PCIE_IMUX17_L_11", - "PCIE_IMUX7_L_10", - "PCIE_WW4C3_9", - "PCIE_IMUX12_R_4", - "PCIE_BYP1_L_9", - "PCIE_DBGVECA3", - "PCIE_IMUX26_R_17", - "PCIE_CFGDEVID7", - "PCIE_PIPETX2DATA11", - "PCIE_LH4_4", - "PCIE_IMUX47_L_13", - "PCIE_TRNRDLLPDATA33", - "PCIE_MIMRXWDATA15", - "PCIE_NW2A0_13", - "PCIE_NE4BEG1_13", - "PCIE_FAN5_R_5", - "PCIE_BYP6_L_18", - "PCIE_IMUX40_L_19", - "PCIE_EE4A3_10", - "PCIE_BYP2_L_3", - "PCIE_SE2A0_4", - "PCIE_LOGIC_OUTS_B10_R_13", - "PCIE_LOGIC_OUTS_B20_R_12", - "PCIE_WL1END1_7", - "PCIE_MIMTXWDATA51", - "PCIE_MIMRXWDATA65", - "PCIE_IMUX35_L_15", - "PCIE_PIPETX5ELECIDLE", - "PCIE_IMUX40_L_9", - "PCIE_IMUX6_R_1", - "PCIE_IMUX43_L_0", - "PCIE_IMUX19_R_4", - "PCIE_IMUX47_L_8", - "PCIE_USERCLKPREBUFEN", - "PCIE_LOGIC_OUTS_B6_L_17", - "PCIE_IMUX34_R_5", - "PCIE_WW4A0_6", - "PCIE_LH2_9", - "PCIE_WW2A0_7", - "PCIE_WW4A0_13", - "PCIE_IMUX28_L_5", - "PCIE_CFGFORCEEXTENDEDSYNCON", - "PCIE_IMUX1_R_5", - "PCIE_WW2END1_10", - "PCIE_WW4C2_2", - "PCIE_DBGVECA49", - "PCIE_CFGDSN49", - "PCIE_IMUX37_R_9", - "PCIE_SE2A2_5", - "PCIE_LOGIC_OUTS_B15_L_11", - "PCIE_LOGIC_OUTS_B13_R_10", - "PCIE_IMUX14_L_12", - "PCIE_LOGIC_OUTS_B12_L_10", - "PCIE_MIMRXRDATA7", - "PCIE_EE2A2_10", - "PCIE_IMUX15_R_14", - "PCIE_ER1BEG3_4", - "PCIE_IMUX26_L_9", - "PCIE_EE2A1_9", - "PCIE_LOGIC_OUTS_B2_R_4", - "PCIE_BLOCK_OUTS_B2_L_15", - "PCIE_ER1BEG0_14", - "PCIE_CFGERRAERHEADERLOG23", - "PCIE_WW4B0_18", - "PCIE_EE4C2_11", - "PCIE_EL1BEG3_7", - "PCIE_TRNRD85", - "PCIE_CLK1_L_17", - "PCIE_IMUX4_L_14", - "PCIE_EE4BEG1_13", - "PCIE_IMUX23_R_4", - "PCIE_IMUX1_L_17", - "PCIE_EE4A2_9", - "PCIE_FAN7_R_8", - "PCIE_BYP6_L_6", - "PCIE_WW4B3_5", - "PCIE_TRNTD15", - "PCIE_PIPERX1DATA0", - "PCIE_MONITOR_N_9", - "PCIE_MIMRXWDATA67", - "PCIE_EL1BEG3_16", - "PCIE_IMUX6_L_4", - "PCIE_IMUX27_L_13", - "PCIE_CFGDEVCONTROLNOSNOOPEN", - "PCIE_ER1BEG3_7", - "PCIE_PLSELLNKWIDTH0", - "PCIE_IMUX23_L_12", - "PCIE_NW4A1_13", - "PCIE_WW4END0_4", - "PCIE_CTRL1_R_16", - "PCIE_IMUX28_R_17", - "PCIE_SE4BEG0_19", - "PCIE_PLLINKPARTNERGEN2SUPPORTED", - "PCIE_CFGMGMTBYTEENN2", - "PCIE_CFGERRAERHEADERLOG1", - "PCIE_EE2A2_15", - "PCIE_WW2A2_10", - "PCIE_LOGIC_OUTS_B15_L_13", - "PCIE_DBGVECA19", - "PCIE_SW4END2_12", - "PCIE_WR1END1_19", - "PCIE_NW4A0_4", - "PCIE_MIMTXWDATA67", - "PCIE_TRNTD93", - "PCIE_FAN5_L_10", - "PCIE_FAN2_R_1", - "PCIE_WW4C3_10", - "PCIE_IMUX3_R_11", - "PCIE_IMUX37_R_12", - "PCIE_IMUX15_L_7", - "PCIE_EE2A3_2", - "PCIE_CTRL1_L_11", - "PCIE_WW4B0_4", - "PCIE_WW4C2_13", - "PCIE_SW4A3_10", - "PCIE_MIMRXWDATA23", - "PCIE_EL1BEG0_2", - "PCIE_IMUX5_R_13", - "PCIE_LH3_8", - "PCIE_EE4C2_17", - "PCIE_DBGVECB60", - "PCIE_EL1BEG1_0", - "PCIE_CFGERRAERHEADERLOG46", - "PCIE_TRNRDLLPDATA49", - "PCIE_MIMTXWDATA56", - "PCIE_TRNFCPD5", - "PCIE_IMUX29_L_18", - "PCIE_IMUX33_L_7", - "PCIE_MIMTXWDATA25", - "PCIE_WW2A3_2", - "PCIE_SE4BEG0_7", - "PCIE_LOGIC_OUTS_B13_R_0", - "PCIE_EE2A0_1", - "PCIE_IMUX45_R_19", - "PCIE_IMUX28_L_15", - "PCIE_BLOCK_OUTS_B1_L_10", - "PCIE_WW2END0_1", - "PCIE_WL1END1_13", - "PCIE_WW4A2_2", - "PCIE_IMUX39_R_16", - "PCIE_EE2BEG3_0", - "PCIE_FAN7_L_15", - "PCIE_MIMRXWDATA24", - "PCIE_DBGVECB43", - "PCIE_EE4A3_3", - "PCIE_IMUX37_R_6", - "PCIE_SE2A0_10", - "PCIE_CFGINTERRUPTDI1", - "PCIE_IMUX11_L_10", - "PCIE_TRNRD71", - "PCIE_DRPDI10", - "PCIE_EE2BEG2_13", - "PCIE_WW2A2_18", - "PCIE_WW4A3_1", - "PCIE_FAN4_R_13", - "PCIE_WL1END2_12", - "PCIE_WW4A0_18", - "PCIE_EE4A1_0", - "PCIE_WR1END2_5", - "PCIE_IMUX13_L_11", - "PCIE_IMUX36_R_16", - "PCIE_PIPERX7CHANISALIGNED", - "PCIE_SW4END3_13", - "PCIE_FAN4_R_12", - "PCIE_BYP1_L_17", - "PCIE_IMUX25_L_1", - "PCIE_NW4END1_7", - "PCIE_FAN2_L_11", - "PCIE_DBGVECB22", - "PCIE_CTRL0_L_11", - "PCIE_LOGIC_OUTS_B20_L_3", - "PCIE_PIPERX0ELECIDLE", - "PCIE_IMUX42_R_10", - "PCIE_IMUX5_R_19", - "PCIE_WW2A2_0", - "PCIE_NE2A2_1", - "PCIE_DRPADDR7", - "PCIE_IMUX12_L_9", - "PCIE_SE4C0_2", - "PCIE_LH11_14", - "PCIE_WW4A1_7", - "PCIE_PIPERX5CHARISK0", - "PCIE_EE4C1_8", - "PCIE_CFGINTERRUPTDO5", - "PCIE_TRNRD86", - "PCIE_CFGMSGRECEIVEDPMETOACK", - "PCIE_IMUX18_L_7", - "PCIE_IMUX29_L_2", - "PCIE_MIMTXWDATA54", - "PCIE_LOGIC_OUTS_B13_L_9", - "PCIE_TRNRDLLPDATA54", - "PCIE_FAN3_R_18", - "PCIE_CTRL1_R_12", - "PCIE_SE4C1_3", - "PCIE_TL2ERRHDR1", - "PCIE_IMUX36_L_2", - "PCIE_EE2A3_8", - "PCIE_IMUX11_R_9", - "PCIE_SW4END0_13", - "PCIE_NE2A3_19", - "PCIE_SW2A2_17", - "PCIE_NW4A0_15", - "PCIE_IMUX30_L_0", - "PCIE_IMUX36_L_13", - "PCIE_USERCLKPREBUF", - "PCIE_IMUX7_R_14", - "PCIE_SW4A0_7", - "PCIE_SE4BEG0_3", - "PCIE_PIPETX3DATA9", - "PCIE_IMUX27_L_16", - "PCIE_NW2A2_5", - "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", - "PCIE_SW2A1_14", - "PCIE_IMUX20_L_3", - "PCIE_CFGERRAERHEADERLOG120", - "PCIE_IMUX42_L_11", - "PCIE_EDTCHANNELSOUT1", - "PCIE_LL2TFCINIT1SEQ", - "PCIE_SW2A0_1", - "PCIE_IMUX45_R_11", - "PCIE_IMUX4_L_7", - "PCIE_FAN6_R_7", - "PCIE_LH5_18", - "PCIE_SW4A1_5", - "PCIE_IMUX39_R_1", - "PCIE_TRNTREM0", - "PCIE_EE4A2_15", - "PCIE_IMUX18_R_11", - "PCIE_LOGIC_OUTS_B9_L_2", - "PCIE_TRNTDSTRDY2", - "PCIE_IMUX30_L_16", - "PCIE_WW4B0_15", - "PCIE_TL2ERRHDR46", - "PCIE_WW2END1_15", - "PCIE_IMUX43_L_12", - "PCIE_SE4BEG1_9", - "PCIE_PIPERX6DATA13", - "PCIE_TRNTD45", - "PCIE_PIPETX2DATA10", - "PCIE_MIMRXWDATA4", - "PCIE_LH3_3", - "PCIE_WR1END2_12", - "PCIE_EDTCHANNELSOUT5", - "PCIE_LOGIC_OUTS_B17_R_15", - "PCIE_SE2A3_19", - "PCIE_WW2END2_7", - "PCIE_SW4END1_18", - "PCIE_LOGIC_OUTS_B1_L_4", - "PCIE_SW2A1_16", - "PCIE_IMUX27_L_5", - "PCIE_LOGIC_OUTS_B0_L_5", - "PCIE_MIMRXWADDR6", - "PCIE_TRNTD43", - "PCIE_IMUX25_R_16", - "PCIE_CFGMGMTDO8", - "PCIE_CFGMGMTDWADDR8", - "PCIE_LOGIC_OUTS_B23_R_11", - "PCIE_LOGIC_OUTS_B12_L_9", - "PCIE_IMUX10_L_0", - "PCIE_TRNTD30", - "PCIE_EL1BEG0_14", - "PCIE_EE4A3_8", - "PCIE_CTRL0_R_12", - "PCIE_CTRL0_L_0", - "PCIE_BLOCK_OUTS_B0_R_3", - "PCIE_BYP4_R_7", - "PCIE_IMUX35_L_2", - "PCIE_IMUX19_L_5", - "PCIE_IMUX9_R_19", - "PCIE_IMUX31_L_17", - "PCIE_CLK1_R_18", - "PCIE_IMUX29_L_11", - "PCIE_NW4A3_0", - "PCIE_TRNRD44", - "PCIE_IMUX11_R_8", - "PCIE_LOGIC_OUTS_B18_R_6", - "PCIE_LL2TFCINIT2SEQ", - "PCIE_IMUX6_R_10", - "PCIE_IMUX23_R_8", - "PCIE_IMUX11_R_7", - "PCIE_CFGDEVCONTROLEXTTAGEN", - "PCIE_IMUX12_R_10", - "PCIE_PIPETX6DATA4", - "PCIE_IMUX45_L_10", - "PCIE_DBGVECB51", - "PCIE_NW4END2_12", - "PCIE_LOGIC_OUTS_B1_L_6", - "PCIE_EE2A2_9", - "PCIE_IMUX32_L_9", - "PCIE_CFGSUBSYSID15", - "PCIE_IMUX27_L_8", - "PCIE_BLOCK_OUTS_B1_R_12", - "PCIE_PIPERX0DATA0", - "PCIE_IMUX6_R_9", - "PCIE_LH2_7", - "PCIE_NE4BEG0_3", - "PCIE_SW4END3_18", - "PCIE_TRNTDLLPDATA5", - "PCIE_LOGIC_OUTS_B14_R_16", - "PCIE_CLK0_R_19", - "PCIE_TRNFCCPLD11", - "PCIE_PIPERX5DATA5", - "PCIE_SW2A2_12", - "PCIE_IMUX21_L_5", - "PCIE_IMUX4_R_4", - "PCIE_TL2ERRHDR44", - "PCIE_IMUX9_L_13", - "PCIE_LH12_11", - "PCIE_EE4C0_15", - "PCIE_EE2BEG3_11", - "PCIE_IMUX32_R_4", - "PCIE_LOGIC_OUTS_B19_L_1", - "PCIE_IMUX5_R_11", - "PCIE_LOGIC_OUTS_B0_R_2", - "PCIE_BYP4_L_7", - "PCIE_IMUX46_L_10", - "PCIE_BYP1_L_16", - "PCIE_PMVSELECT2", - "PCIE_IMUX28_L_16", - "PCIE_IMUX8_R_7", - "PCIE_TL2ERRHDR19", - "PCIE_WW2A1_8", - "PCIE_IMUX19_R_16", - "PCIE_IMUX38_L_15", - "PCIE_LH5_15", - "PCIE_IMUX25_L_15", - "PCIE_FAN5_R_10", - "PCIE_IMUX26_L_19", - "PCIE_WW2A0_18", - "PCIE_IMUX35_L_3", - "PCIE_IMUX2_R_0", - "PCIE_IMUX1_L_11", - "PCIE_SE4C3_7", - "PCIE_SE4BEG3_15", - "PCIE_NE4BEG1_4", - "PCIE_LOGIC_OUTS_B17_R_7", - "PCIE_LH10_18", - "PCIE_IMUX14_R_19", - "PCIE_CFGDSN46", - "PCIE_PIPETX1DATA7", - "PCIE_LH6_10", - "PCIE_TRNRDLLPDATA41", - "PCIE_WW4C0_6", - "PCIE_LOGIC_OUTS_B10_R_12", - "PCIE_IMUX6_R_11", - "PCIE_WW4END3_5", - "PCIE_IMUX31_L_18", - "PCIE_IMUX17_R_12", - "PCIE_IMUX8_R_18", - "PCIE_MIMRXRDATA34", - "PCIE_LOGIC_OUTS_B7_R_0", - "PCIE_EE4A2_8", - "PCIE_NW2A0_5", - "PCIE_CFGMGMTDI25", - "PCIE_CFGERRAERHEADERLOG71", - "PCIE_NW4A2_5", - "PCIE_CFGERRAERHEADERLOG66", - "PCIE_FAN2_L_18", - "PCIE_CFGDSN12", - "PCIE_DBGVECA17", - "PCIE_MIMTXRADDR0", - "PCIE_PIPERX4DATA2", - "PCIE_LOGIC_OUTS_B17_R_4", - "PCIE_SE4C0_17", - "PCIE_LH9_14", - "PCIE_PIPERX1DATA13", - "PCIE_SE2A3_13", - "PCIE_IMUX2_R_8", - "PCIE_IMUX38_L_14", - "PCIE_SE4BEG3_14", - "PCIE_DRPDO10", - "PCIE_IMUX20_R_14", - "PCIE_LOGIC_OUTS_B17_R_3", - "PCIE_NE2A1_2", - "PCIE_MONITOR_N_19", - "PCIE_FAN4_R_4", - "PCIE_BYP6_R_2", - "PCIE_SW4A0_19", - "PCIE_LOGIC_OUTS_B20_L_7", - "PCIE_WR1END0_1", - "PCIE_CFGMGMTDI20", - "PCIE_CLK1_R_15", - "PCIE_CFGSUBSYSID6", - "PCIE_WW4B1_19", - "PCIE_BYP5_L_18", - "PCIE_IMUX26_L_8", - "PCIE_MIMRXRDATA67", - "PCIE_FAN7_L_13", - "PCIE_SE2A2_14", - "PCIE_DRPDI4", - "PCIE_IMUX0_L_17", - "PCIE_DRPDO15", - "PCIE_IMUX12_R_8", - "PCIE_MIMTXWDATA30", - "PCIE_SE4C2_7", - "PCIE_IMUX33_R_6", - "PCIE_IMUX14_L_17", - "PCIE_DBGSCLRF", - "PCIE_BLOCK_OUTS_B0_L_15", - "PCIE_EL1BEG3_8", - "PCIE_IMUX15_L_4", - "PCIE_IMUX47_R_18", - "PCIE_RECEIVEDFUNCLVLRSTN", - "PCIE_LOGIC_OUTS_B5_L_5", - "PCIE_CFGDSN40", - "PCIE_BYP2_L_9", - "PCIE_MIMTXWDATA34", - "PCIE_NE4BEG3_19", - "PCIE_IMUX16_L_5", - "PCIE_CFGMGMTDO21", - "PCIE_CFGDSN21", - "PCIE_FAN0_L_7", - "PCIE_IMUX18_L_14", - "PCIE_IMUX21_L_2", - "PCIE_NW4A3_3", - "PCIE_IMUX19_L_2", - "PCIE_DBGVECB36", - "PCIE_CLK1_L_1", - "PCIE_TRNRD56", - "PCIE_MIMTXRDATA9", - "PCIE_NE4C0_18", - "PCIE_LOGIC_OUTS_B10_R_7", - "PCIE_CFGINTERRUPTDO4", - "PCIE_TL2ERRHDR34", - "PCIE_ER1BEG2_7", - "PCIE_IMUX18_L_6", - "PCIE_LOGIC_OUTS_B22_R_11", - "PCIE_LOGIC_OUTS_B5_R_17", - "PCIE_LH12_9", - "PCIE_LH1_7", - "PCIE_BLOCK_OUTS_B1_R_2", - "PCIE_EE4B1_3", - "PCIE_BLOCK_OUTS_B2_L_8", - "PCIE_DBGVECC5", - "PCIE_EE2A3_12", - "PCIE_IMUX24_R_6", - "PCIE_TRNTD126", - "PCIE_WW2A3_6", - "PCIE_IMUX47_L_9", - "PCIE_NE4BEG0_4", - "PCIE_LH3_6", - "PCIE_NE2A3_7", - "PCIE_MIMRXWADDR11", - "PCIE_TL2ERRHDR17", - "PCIE_MIMRXWDATA52", - "PCIE_TRNRD61", - "PCIE_WW4A2_5", - "PCIE_EE4BEG3_8", - "PCIE_LH12_3", - "PCIE_IMUX35_R_18", - "PCIE_CFGERRTLPCPLHEADER18", - "PCIE_NW4END2_16", - "PCIE_PLDIRECTEDLTSSMNEW5", - "PCIE_WW2A2_8", - "PCIE_CTRL1_R_8", - "PCIE_TRNRD51", - "PCIE_IMUX4_L_18", - "PCIE_NW4END0_0", - "PCIE_TRNRD106", - "PCIE_PIPERX0DATA7", - "PCIE_WW2A2_16", - "PCIE_IMUX25_L_19", - "PCIE_SW2A1_11", - "PCIE_IMUX43_L_9", - "PCIE_PIPERX0CHARISK1", - "PCIE_IMUX39_R_17", - "PCIE_MIMRXWDATA20", - "PCIE_IMUX33_L_3", - "PCIE_BLOCK_OUTS_B3_R_9", - "PCIE_BLOCK_OUTS_B0_L_11", - "PCIE_TRNRDLLPDATA39", - "PCIE_NW4END3_18", - "PCIE_IMUX27_R_17", - "PCIE_IMUX23_L_2", - "PCIE_IMUX46_R_18", - "PCIE_EL1BEG3_2", - "PCIE_IMUX7_R_8", - "PCIE_WW4END2_6", - "PCIE_TRNRNPOK", - "PCIE_CFGDSN30", - "PCIE_NE2A2_2", - "PCIE_IMUX43_R_8", - "PCIE_LOGIC_OUTS_B11_L_5", - "PCIE_DBGVECC2", - "PCIE_TRNTD104", - "PCIE_WW4A2_7", - "PCIE_CFGERRAERHEADERLOG91", - "PCIE_BLOCK_OUTS_B3_L_4", - "PCIE_NE4C0_12", - "PCIE_WW4A2_9", - "PCIE_IMUX46_R_19", - "PCIE_BYP1_L_18", - "PCIE_SE2A0_5", - "PCIE_BYP0_L_4", - "PCIE_LH10_15", - "PCIE_IMUX45_R_6", - "PCIE_IMUX33_R_5", - "PCIE_IMUX30_R_12", - "PCIE_LOGIC_OUTS_B6_L_8", - "PCIE_CFGROOTCONTROLSYSERRCORRERREN", - "PCIE_CFGCOMMANDSERREN", - "PCIE_MIMTXWDATA31", - "PCIE_BYP4_L_9", - "PCIE_LOGIC_OUTS_B14_L_2", - "PCIE_MIMRXRDATA23", - "PCIE_BYP2_L_17", - "PCIE_LOGIC_OUTS_B6_L_16", - "PCIE_CFGERRAERHEADERLOG114", - "PCIE_NW4A1_2", - "PCIE_PIPETX5DATA12", - "PCIE_IMUX34_R_0", - "PCIE_IMUX25_R_8", - "PCIE_LOGIC_OUTS_B5_R_18", - "PCIE_SW2A3_10", - "PCIE_FAN3_R_10", - "PCIE_NE4C3_7", - "PCIE_MIMTXRDATA40", - "PCIE_CFGERRAERHEADERLOG119", - "PCIE_IMUX6_L_6", - "PCIE_USERCLK2", - "PCIE_IMUX34_R_16", - "PCIE_CFGTRANSACTIONADDR3", - "PCIE_IMUX8_R_5", - "PCIE_NW4END0_7", - "PCIE_FAN6_R_19", - "PCIE_NE4C1_3", - "PCIE_TRNTD110", - "PCIE_SE4BEG0_15", - "PCIE_WW4C2_4", - "PCIE_WW2END1_2", - "PCIE_LOGIC_OUTS_B3_R_7", - "PCIE_CFGERRAERHEADERLOG12", - "PCIE_DRPRDY", - "PCIE_IMUX27_R_1", - "PCIE_FAN7_R_6", - "PCIE_NE2A3_1", - "PCIE_IMUX26_R_5", - "PCIE_EE4B0_1", - "PCIE_LOGIC_OUTS_B0_R_19", - "PCIE_DBGVECB50", - "PCIE_NE4BEG3_1", - "PCIE_DBGVECB63", - "PCIE_SW4A0_16", - "PCIE_IMUX19_L_10", - "PCIE_IMUX42_L_6", - "PCIE_IMUX39_R_0", - "PCIE_IMUX34_L_6", - "PCIE_PIPERX0STATUS2", - "PCIE_IMUX30_R_2", - "PCIE_TRNFCNPD6", - "PCIE_SW2A1_9", - "PCIE_BYP5_L_14", - "PCIE_EE4A2_7", - "PCIE_MIMTXWDATA24", - "PCIE_IMUX34_R_18", - "PCIE_MIMTXRDATA7", - "PCIE_MIMTXWDATA1", - "PCIE_SW4A0_12", - "PCIE_WL1END1_17", - "PCIE_FAN7_L_12", - "PCIE_CLK1_L_10", - "PCIE_BYP2_R_6", - "PCIE_PIPETXDEEMPH", - "PCIE_IMUX5_R_5", - "PCIE_WL1END1_1", - "PCIE_WW4END3_1", - "PCIE_IMUX28_L_12", - "PCIE_SW2A2_4", - "PCIE_SE2A1_11", - "PCIE_WW2END0_11", - "PCIE_BYP2_L_1", - "PCIE_LOGIC_OUTS_B6_L_1", - "PCIE_SW4END3_2", - "PCIE_EE2A2_7", - "PCIE_SW4END1_17", - "PCIE_IMUX47_L_14", - "PCIE_EE4BEG2_14", - "PCIE_TL2ERRHDR45", - "PCIE_IMUX10_R_9", - "PCIE_TRNRD105", - "PCIE_EE4B3_4", - "PCIE_MONITOR_P_2", - "PCIE_IMUX5_R_3", - "PCIE_SE2A2_16", - "PCIE_BLOCK_OUTS_B0_L_4", - "PCIE_BYP3_R_8", - "PCIE_IMUX25_L_10", - "PCIE_TRNRD8", - "PCIE_SE4C2_3", - "PCIE_IMUX6_R_19", - "PCIE_FAN5_R_4", - "PCIE_IMUX17_L_15", - "PCIE_CFGERRAERHEADERLOG105", - "PCIE_EE2BEG3_5", - "PCIE_DBGVECA23", - "PCIE_IMUX36_R_6", - "PCIE_TRNTD59", - "PCIE_SW4END0_17", - "PCIE_PIPERX3DATA9", - "PCIE_WW2END0_6", - "PCIE_SW2A2_2", - "PCIE_LOGIC_OUTS_B12_R_17", - "PCIE_MIMTXRDATA62", - "PCIE_NE4C2_1", - "PCIE_IMUX31_R_1", - "PCIE_MIMRXWDATA28", - "PCIE_CFGERRAERHEADERLOG110", - "PCIE_MIMTXRDATA28", - "PCIE_IMUX46_L_7", - "PCIE_WW4C0_14", - "PCIE_EE4C1_3", - "PCIE_NE4BEG0_19", - "PCIE_FAN7_L_8", - "PCIE_IMUX47_L_2", - "PCIE_TL2ERRHDR10", - "PCIE_PIPERX2POLARITY", - "PCIE_PLDBGVEC7", - "PCIE_WW4B2_10", - "PCIE_LOGIC_OUTS_B2_L_0", - "PCIE_NE2A2_0", - "PCIE_MONITOR_N_11", - "PCIE_MIMTXWDATA43", - "PCIE_TRNTD73", - "PCIE_ER1BEG3_18", - "PCIE_IMUX25_R_19", - "PCIE_PIPERX2STATUS1", - "PCIE_EL1BEG0_13", - "PCIE_IMUX45_L_5", - "PCIE_CFGMGMTDI31", - "PCIE_IMUX6_R_14", - "PCIE_EL1BEG1_17", - "PCIE_CFGERRTLPCPLHEADER17", - "PCIE_LOGIC_OUTS_B21_R_10", - "PCIE_IMUX0_L_3", - "PCIE_MONITOR_N_12", - "PCIE_TRNRD66", - "PCIE_NW4END3_2", - "PCIE_LOGIC_OUTS_B6_R_14", - "PCIE_LOGIC_OUTS_B17_L_18", - "PCIE_IMUX4_R_18", - "PCIE_SW2A0_15", - "PCIE_IMUX41_R_11", - "PCIE_CFGDSN45", - "PCIE_IMUX17_L_1", - "PCIE_IMUX28_R_19", - "PCIE_LOGIC_OUTS_B23_R_8", - "PCIE_EE4C1_18", - "PCIE_NE4BEG0_15", - "PCIE_SE4BEG1_17", - "PCIE_IMUX43_R_0", - "PCIE_IMUX14_L_14", - "PCIE_LOGIC_OUTS_B10_L_4", - "PCIE_PIPETX5CHARISK1", - "PCIE_CFGDSN60", - "PCIE_DRPDO3", - "PCIE_LOGIC_OUTS_B23_L_16", - "PCIE_IMUX19_R_3", - "PCIE_IMUX17_R_18", - "PCIE_CFGERRECRCN", - "PCIE_IMUX20_L_17", - "PCIE_CFGERRAERHEADERLOG38", - "PCIE_FAN7_L_10", - "PCIE_IMUX13_R_8", - "PCIE_IMUX11_L_19", - "PCIE_MIMTXWDATA60", - "PCIE_LOGIC_OUTS_B19_L_7", - "PCIE_LH10_6", - "PCIE_IMUX7_L_19", - "PCIE_LOGIC_OUTS_B0_R_18", - "PCIE_IMUX17_L_13", - "PCIE_NE2A0_18", - "PCIE_IMUX47_L_18", - "PCIE_LOGIC_OUTS_B20_R_1", - "PCIE_IMUX47_L_15", - "PCIE_WR1END2_14", - "PCIE_CLK0_R_10", - "PCIE_EDTCHANNELSIN8", - "PCIE_TRNFCPH2", - "PCIE_EL1BEG2_10", - "PCIE_SW4A0_6", - "PCIE_FAN5_R_19", - "PCIE_BLOCK_OUTS_B3_L_3", - "PCIE_LOGIC_OUTS_B18_L_12", - "PCIE_IMUX15_R_1", - "PCIE_DBGVECB57", - "PCIE_LH5_7", - "PCIE_NW4A0_19", - "PCIE_BYP7_L_9", - "PCIE_SE4BEG2_19", - "PCIE_SW4END0_14", - "PCIE_LH10_14", - "PCIE_LOGIC_OUTS_B23_L_3", - "PCIE_EE2A1_8", - "PCIE_CFGVENDID4", - "PCIE_EE4C3_5", - "PCIE_LOGIC_OUTS_B16_L_17", - "PCIE_IMUX12_L_14", - "PCIE_ER1BEG2_6", - "PCIE_IMUX8_L_16", - "PCIE_IMUX28_R_8", - "PCIE_ER1BEG1_18", - "PCIE_TRNRBARHIT4", - "PCIE_MIMRXRDATA51", - "PCIE_IMUX21_R_13", - "PCIE_SE4C1_2", - "PCIE_IMUX20_L_13", - "PCIE_IMUX11_L_1", - "PCIE_IMUX3_R_16", - "PCIE_BLOCK_OUTS_B3_R_19", - "PCIE_LH6_12", - "PCIE_SW4END3_9", - "PCIE_TRNTD124", - "PCIE_DBGVECB20", - "PCIE_CFGDSBUSNUMBER4", - "PCIE_CFGCOMMANDBUSMASTERENABLE", - "PCIE_BLOCK_OUTS_B3_L_10", - "PCIE_WW2END3_6", - "PCIE_DBGVECB52", - "PCIE_IMUX6_R_15", - "PCIE_LOGIC_OUTS_B0_L_4", - "PCIE_BLOCK_OUTS_B0_R_4", - "PCIE_BLOCK_OUTS_B0_L_19", - "PCIE_LOGIC_OUTS_B3_R_11", - "PCIE_EE2BEG2_15", - "PCIE_BYP1_R_12", - "PCIE_EE2A3_5", - "PCIE_SE2A2_4", - "PCIE_IMUX24_L_6", - "PCIE_IMUX41_L_8", - "PCIE_WW4A3_0", - "PCIE_DBGMODE1", - "PCIE_EL1BEG2_18", - "PCIE_EE4A2_4", - "PCIE_IMUX38_R_18", - "PCIE_EE2A3_9", - "PCIE_IMUX24_R_11", - "PCIE_FAN7_L_6", - "PCIE_BYP1_L_1", - "PCIE_PLTXPMSTATE0", - "PCIE_BYP1_R_4", - "PCIE_CFGERRAERHEADERLOG24", - "PCIE_WW4C1_1", - "PCIE_PIPETX7DATA13", - "PCIE_PMVDIVIDE0", - "PCIE_LOGIC_OUTS_B5_L_9", - "PCIE_LOGIC_OUTS_B17_L_0", - "PCIE_IMUX9_L_1", - "PCIE_LOGIC_OUTS_B19_R_15", - "PCIE_IMUX11_L_18", - "PCIE_TRNTD25", - "PCIE_LH1_1", - "PCIE_BLOCK_OUTS_B1_R_4", - "PCIE_IMUX14_R_18", - "PCIE_IMUX23_L_4", - "PCIE_NE2A2_14", - "PCIE_LOGIC_OUTS_B1_R_9", - "PCIE_MIMRXWDATA47", - "PCIE_FAN6_R_16", - "PCIE_LH7_16", - "PCIE_DBGVECB46", - "PCIE_WW4END2_15", - "PCIE_LH3_9", - "PCIE_PIPETX0CHARISK0", - "PCIE_IMUX8_L_3", - "PCIE_WL1END3_4", - "PCIE_IMUX47_L_4", - "PCIE_SW4END1_15", - "PCIE_EDTCHANNELSIN4", - "PCIE_LOGIC_OUTS_B10_R_9", - "PCIE_IMUX35_L_19", - "PCIE_WW4END3_12", - "PCIE_BLOCK_OUTS_B1_R_13", - "PCIE_NE4C3_18", - "PCIE_LOGIC_OUTS_B12_R_0", - "PCIE_WW2END2_6", - "PCIE_IMUX27_R_13", - "PCIE_IMUX6_L_19", - "PCIE_BLOCK_OUTS_B0_R_10", - "PCIE_ER1BEG1_14", - "PCIE_LOGIC_OUTS_B12_R_7", - "PCIE_WW2A2_14", - "PCIE_LOGIC_OUTS_B13_R_15", - "PCIE_SW2A3_7", - "PCIE_CFGINTERRUPTMSIXENABLE", - "PCIE_WW2END3_2", - "PCIE_SE2A0_15", - "PCIE_WW2END0_13", - "PCIE_CFGAERROOTERRFATALERRRECEIVED", - "PCIE_IMUX20_R_1", - "PCIE_WW2A1_15", - "PCIE_PIPERX3PHYSTATUS", - "PCIE_DBGVECB4", - "PCIE_IMUX40_R_13", - "PCIE_LOGIC_OUTS_B21_L_19", - "PCIE_LOGIC_OUTS_B4_L_16", - "PCIE_EE2BEG2_7", - "PCIE_IMUX8_R_13", - "PCIE_SW2A2_11", - "PCIE_WW4END0_2", - "PCIE_IMUX26_L_11", - "PCIE_IMUX32_L_7", - "PCIE_IMUX16_L_14", - "PCIE_TRNTD23", - "PCIE_SE4BEG0_13", - "PCIE_CFGVENDID9", - "PCIE_EE4C0_12", - "PCIE_IMUX13_L_10", - "PCIE_EE4BEG2_2", - "PCIE_WW4C1_14", - "PCIE_EDTCLK", - "PCIE_PIPERX0DATA2", - "PCIE_WW2END3_4", - "PCIE_BYP1_L_3", - "PCIE_NE4C2_7", - "PCIE_EE4B3_10", - "PCIE_CLK1_R_14", - "PCIE_LOGIC_OUTS_B5_L_0", - "PCIE_TRNTD75", - "PCIE_LOGIC_OUTS_B16_R_14", - "PCIE_MIMRXRADDR7", - "PCIE_WW4B1_3", - "PCIE_SE4C0_18", - "PCIE_FAN2_L_3", - "PCIE_IMUX10_L_8", - "PCIE_LOGIC_OUTS_B21_R_15", - "PCIE_TRNRDLLPDATA4", - "PCIE_BLOCK_OUTS_B1_R_1", - "PCIE_NW4A1_19", - "PCIE_NW2A0_15", - "PCIE_CFGREVID4", - "PCIE_NW2A1_13", - "PCIE_EE4A1_17", - "PCIE_IMUX28_L_9", - "PCIE_IMUX21_R_4", - "PCIE_PLDIRECTEDLTSSMNEW1", - "PCIE_BLOCK_OUTS_B0_L_16", - "PCIE_CTRL1_R_2", - "PCIE_SE4BEG2_12", - "PCIE_IMUX42_R_13", - "PCIE_SW4END1_9", - "PCIE_CFGMSGRECEIVEDASSERTINTB", - "PCIE_NE2A2_12", - "PCIE_PIPERX1DATA14", - "PCIE_IMUX8_R_0", - "PCIE_LOGIC_OUTS_B0_L_12", - "PCIE_NE2A2_18", - "PCIE_IMUX26_R_11", - "PCIE_EE4B1_6", - "PCIE_WR1END0_3", - "PCIE_MIMRXRDATA11", - "PCIE_ER1BEG0_9", - "PCIE_SE4BEG1_7", - "PCIE_NW4END1_12", - "PCIE_IMUX32_L_10", - "PCIE_FAN6_R_6", - "PCIE_DRPDO7", - "PCIE_WW4B1_5", - "PCIE_BYP7_R_1", - "PCIE_WW4C1_19", - "PCIE_FAN5_R_8", - "PCIE_IMUX23_R_14", - "PCIE_BYP3_R_4", - "PCIE_LOGIC_OUTS_B18_L_15", - "PCIE_LOGIC_OUTS_B10_L_19", - "PCIE_IMUX8_L_19", - "PCIE_EE4C0_16", - "PCIE_EL1BEG3_19", - "PCIE_BYP7_L_16", - "PCIE_IMUX19_R_18", - "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", - "PCIE_SW2A1_8", - "PCIE_EE4B2_1", - "PCIE_IMUX24_L_1", - "PCIE_IMUX39_L_7", - "PCIE_IMUX16_R_19", - "PCIE_PIPERX5DATA6", - "PCIE_WW2END3_13", - "PCIE_LOGIC_OUTS_B2_L_8", - "PCIE_DBGVECA28", - "PCIE_TL2ERRHDR62", - "PCIE_IMUX2_R_5", - "PCIE_MIMRXWDATA40", - "PCIE_LOGIC_OUTS_B4_L_9", - "PCIE_IMUX11_R_17", - "PCIE_BLOCK_OUTS_B0_L_0", - "PCIE_FAN3_L_2", - "PCIE_LOGIC_OUTS_B11_L_8", - "PCIE_DBGVECA9", - "PCIE_CLK0_R_17", - "PCIE_EE4C1_12", - "PCIE_BLOCK_OUTS_B2_R_0", - "PCIE_IMUX30_R_13", - "PCIE_WW4A0_3", - "PCIE_BYP5_L_17", - "PCIE_IMUX4_R_13", - "PCIE_TRNRDLLPDATA0", - "PCIE_WR1END2_17", - "PCIE_LOGIC_OUTS_B4_L_14", - "PCIE_CFGMSGRECEIVEDDEASSERTINTD", - "PCIE_IMUX39_R_19", - "PCIE_NE4C3_4", - "PCIE_CLK1_R_5", - "PCIE_BYP4_R_10", - "PCIE_FAN6_L_14", - "PCIE_LOGIC_OUTS_B22_L_1", - "PCIE_SE4C3_1", - "PCIE_CTRL0_R_13", - "PCIE_LOGIC_OUTS_B17_R_18", - "PCIE_XILUNCONNOUT0", - "PCIE_CFGREVID7", - "PCIE_CMRSTN", - "PCIE_NW2A2_12", - "PCIE_EE4C2_5", - "PCIE_FAN5_R_18", - "PCIE_EE4C2_15", - "PCIE_IMUX40_L_17", - "PCIE_SE2A1_13", - "PCIE_WW2END2_11", - "PCIE_LH9_13", - "PCIE_DRPDO8", - "PCIE_LOGIC_OUTS_B3_L_6", - "PCIE_IMUX20_L_16", - "PCIE_BYP0_L_1", - "PCIE_TRNFCPH6", - "PCIE_DBGVECA8", - "PCIE_MIMRXWDATA8", - "PCIE_MIMRXWADDR12", - "PCIE_MIMTXWDATA7", - "PCIE_LH9_10", - "PCIE_WL1END2_6", - "PCIE_FAN5_R_12", - "PCIE_WW4B1_1", - "PCIE_IMUX16_R_15", - "PCIE_IMUX22_L_17", - "PCIE_IMUX1_L_16", - "PCIE_SE4BEG3_1", - "PCIE_WW2A1_17", - "PCIE_IMUX25_R_18", - "PCIE_IMUX2_R_10", - "PCIE_MIMRXRDATA18", - "PCIE_LH7_10", - "PCIE_IMUX41_R_0", - "PCIE_TRNTDLLPSRCRDY", - "PCIE_IMUX14_R_13", - "PCIE_NW4END3_16", - "PCIE_SE2A1_0", - "PCIE_CFGERRAERHEADERLOG125", - "PCIE_IMUX36_R_18", - "PCIE_LOGIC_OUTS_B3_R_19", - "PCIE_IMUX35_L_11", - "PCIE_LH8_3", - "PCIE_IMUX5_R_4", - "PCIE_EE4BEG3_5", - "PCIE_LOGIC_OUTS_B19_R_18", - "PCIE_IMUX39_L_10", - "PCIE_IMUX44_L_1", - "PCIE_LOGIC_OUTS_B6_L_19", - "PCIE_LOGIC_OUTS_B7_R_15", - "PCIE_CLK0_L_10", - "PCIE_IMUX21_R_16", - "PCIE_WL1END3_1", - "PCIE_CFGVENDID8", - "PCIE_IMUX40_R_18", - "PCIE_EE4BEG3_17", - "PCIE_EE4A0_11", - "PCIE_PLDBGVEC8", - "PCIE_IMUX11_R_2", - "PCIE_NE4BEG3_3", - "PCIE_PIPETX7DATA8", - "PCIE_PIPERX3ELECIDLE", - "PCIE_PMVSELECT0", - "PCIE_IMUX6_L_17", - "PCIE_SE4C2_0", - "PCIE_MONITOR_N_13", - "PCIE_EL1BEG2_14", - "PCIE_LOGIC_OUTS_B23_L_17", - "PCIE_IMUX13_L_14", - "PCIE_TRNFCSEL0", - "PCIE_ER1BEG3_19", - "PCIE_CFGPORTNUMBER7", - "PCIE_IMUX36_R_17", - "PCIE_IMUX47_L_1", - "PCIE_EE4A1_11", - "PCIE_IMUX38_L_17", - "PCIE_IMUX7_L_17", - "PCIE_IMUX10_L_11", - "PCIE_IMUX24_L_17", - "PCIE_TRNFCCPLD7", - "PCIE_IMUX15_R_13", - "PCIE_MIMRXWDATA6", - "PCIE_BLOCK_OUTS_B3_L_5", - "PCIE_IMUX30_L_3", - "PCIE_TL2ERRHDR14", - "PCIE_LOGIC_OUTS_B11_R_12", - "PCIE_LOGIC_OUTS_B1_R_1", - "PCIE_FAN6_R_17", - "PCIE_TRNFCNPD2", - "PCIE_BLOCK_OUTS_B3_L_13", - "PCIE_BYP4_R_13", - "PCIE_CFGERRAERHEADERLOG11", - "PCIE_CFGTRANSACTIONTYPE", - "PCIE_BLOCK_OUTS_B1_L_1", - "PCIE_IMUX15_R_5", - "PCIE_CLK1_L_11", - "PCIE_DRPDO12", - "PCIE_FAN0_L_6", - "PCIE_LOGIC_OUTS_B10_R_16", - "PCIE_EE4B3_7", - "PCIE_IMUX15_L_17", - "PCIE_WW4C0_5", - "PCIE_PIPERX0VALID", - "PCIE_TRNLNKUP", - "PCIE_PIPERX6DATA10", - "PCIE_FAN7_L_1", - "PCIE_LOGIC_OUTS_B17_R_12", - "PCIE_LOGIC_OUTS_B8_L_14", - "PCIE_EL1BEG2_9", - "PCIE_NE4C0_1", - "PCIE_NE4C3_16", - "PCIE_FAN7_R_2", - "PCIE_SE4BEG2_18", - "PCIE_TL2ERRHDR4", - "PCIE_IMUX13_L_1", - "PCIE_BYP3_L_18", - "PCIE_MIMRXWDATA44", - "PCIE_NE4BEG2_13", - "PCIE_CFGDSN18", - "PCIE_PIPETX0ELECIDLE", - "PCIE_CFGERRAERHEADERLOG48", - "PCIE_PIPERX4DATA4", - "PCIE_BYP5_L_2", - "PCIE_IMUX32_R_3", - "PCIE_EE4BEG2_1", - "PCIE_IMUX25_R_6", - "PCIE_LH4_13", - "PCIE_CFGPMRCVENTERL23N", - "PCIE_DRPDI11", - "PCIE_TRNFCNPH6", - "PCIE_IMUX4_R_5", - "PCIE_WW4C2_7", - "PCIE_NW2A0_3", - "PCIE_FAN6_R_15", - "PCIE_IMUX20_R_3", - "PCIE_FAN1_L_17", - "PCIE_IMUX40_R_16", - "PCIE_IMUX7_L_14", - "PCIE_IMUX21_R_14", - "PCIE_LOGIC_OUTS_B19_R_3", - "PCIE_NW2A3_17", - "PCIE_IMUX43_L_8", - "PCIE_TRNRD125", - "PCIE_FAN0_L_12", - "PCIE_LH8_1", - "PCIE_IMUX21_L_11", - "PCIE_IMUX25_R_7", - "PCIE_NE4C2_9", - "PCIE_IMUX7_R_6", - "PCIE_LOGIC_OUTS_B7_R_9", - "PCIE_EE4A3_13", - "PCIE_LOGIC_OUTS_B16_L_7", - "PCIE_CTRL0_R_16", - "PCIE_LH9_11", - "PCIE_IMUX46_L_14", - "PCIE_BYP0_R_15", - "PCIE_XILUNCONNOUT2", - "PCIE_SW2A2_5", - "PCIE_IMUX8_R_11", - "PCIE_NW4A2_7", - "PCIE_TRNTDLLPDATA3", - "PCIE_NW4END0_1", - "PCIE_LOGIC_OUTS_B2_L_13", - "PCIE_LOGIC_OUTS_B11_L_7", - "PCIE_LOGIC_OUTS_B9_R_14", - "PCIE_FAN2_R_16", - "PCIE_IMUX30_R_6", - "PCIE_TRNRDLLPDATA38", - "PCIE_SE2A2_12", - "PCIE_TL2ERRHDR55", - "PCIE_EE4C1_16", - "PCIE_IMUX36_L_15", - "PCIE_LOGIC_OUTS_B9_R_12", - "PCIE_WW2END2_16", - "PCIE_LOGIC_OUTS_B1_R_18", - "PCIE_IMUX4_R_10", - "PCIE_WW2A1_5", - "PCIE_LH10_10", - "PCIE_ER1BEG3_1", - "PCIE_CFGDEVCONTROLMAXREADREQ1", - "PCIE_TRNTD68", - "PCIE_NW4END3_0", - "PCIE_FAN6_R_4", - "PCIE_TRNRDLLPDATA36", - "PCIE_PLLANEREVERSALMODE1", - "PCIE_FAN4_L_18", - "PCIE_CTRL0_R_14", - "PCIE_LOGIC_OUTS_B6_L_4", - "PCIE_SE4C3_5", - "PCIE_CTRL0_R_4", - "PCIE_CLK0_R_16", - "PCIE_DBGVECA52", - "PCIE_WR1END0_5", - "PCIE_MIMRXWDATA39", - "PCIE_EL1BEG1_12", - "PCIE_IMUX18_L_12", - "PCIE_ER1BEG0_5", - "PCIE_IMUX8_L_1", - "PCIE_LOGIC_OUTS_B12_L_2", - "PCIE_EE4A2_17", - "PCIE_TRNFCCPLD2", - "PCIE_CFGERRAERHEADERLOG99", - "PCIE_TRNRD22", - "PCIE_BYP5_L_8", - "PCIE_EE4B1_7", - "PCIE_LOGIC_OUTS_B23_L_8", - "PCIE_LOGIC_OUTS_B15_L_0", - "PCIE_WL1END3_2", - "PCIE_FAN3_R_8", - "PCIE_TRNTD36", - "PCIE_IMUX47_L_11", - "PCIE_IMUX15_R_18", - "PCIE_BYP4_L_2", - "PCIE_BYP6_R_17", - "PCIE_WL1END2_18", - "PCIE_SW4A2_15", - "PCIE_LOGIC_OUTS_B10_R_2", - "PCIE_NE4BEG0_14", - "PCIE_TRNFCNPD3", - "PCIE_EE4C2_10", - "PCIE_EL1BEG2_1", - "PCIE_NW2A0_8", - "PCIE_WW2END2_8", - "PCIE_WW4C3_0", - "PCIE_CFGERRTLPCPLHEADER44", - "PCIE_MIMRXRDATA31", - "PCIE_IMUX44_R_9", - "PCIE_IMUX43_L_10", - "PCIE_IMUX14_R_3", - "PCIE_IMUX13_L_3", - "PCIE_LOGIC_OUTS_B10_L_8", - "PCIE_EE2A2_3", - "PCIE_PIPETX3DATA4", - "PCIE_IMUX18_L_10", - "PCIE_PIPERX7POLARITY", - "PCIE_SE2A2_10", - "PCIE_EE4A0_1", - "PCIE_LOGIC_OUTS_B20_R_6", - "PCIE_WR1END2_2", - "PCIE_LOGIC_OUTS_B19_L_3", - "PCIE_EL1BEG3_6", - "PCIE_LOGIC_OUTS_B9_L_3", - "PCIE_WW2END0_17", - "PCIE_FAN0_R_12", - "PCIE_LOGIC_OUTS_B10_L_2", - "PCIE_LOGIC_OUTS_B12_R_6", - "PCIE_WR1END3_6", - "PCIE_IMUX40_L_6", - "PCIE_PIPETX6DATA3", - "PCIE_IMUX10_R_0", - "PCIE_LH9_15", - "PCIE_NW4A0_6", - "PCIE_BYP0_R_4", - "PCIE_IMUX30_L_1", - "PCIE_IMUX46_R_12", - "PCIE_IMUX10_R_16", - "PCIE_ER1BEG0_12", - "PCIE_EE4A1_15", - "PCIE_LOGIC_OUTS_B0_R_15", - "PCIE_LOGIC_OUTS_B19_R_11", - "PCIE_MIMTXWDATA32", - "PCIE_IMUX42_L_5", - "PCIE_SW4END2_10", - "PCIE_FAN0_R_7", - "PCIE_LH8_4", - "PCIE_NE4BEG1_2", - "PCIE_IMUX39_L_15", - "PCIE_IMUX35_L_4", - "PCIE_EE4BEG0_6", - "PCIE_EL1BEG0_17", - "PCIE_IMUX20_L_11", - "PCIE_DBGVECA15", - "PCIE_WL1END3_0", - "PCIE_IMUX25_L_17", - "PCIE_LOGIC_OUTS_B13_L_11", - "PCIE_LOGIC_OUTS_B2_L_4", - "PCIE_CLK0_L_15", - "PCIE_LOGIC_OUTS_B16_R_13", - "PCIE_TRNRD80", - "PCIE_MIMTXRDATA57", - "PCIE_TRNRD114", - "PCIE_TRNRD35", - "PCIE_CFGERRAERHEADERLOG3", - "PCIE_FAN3_L_5", - "PCIE_LOGIC_OUTS_B13_L_10", - "PCIE_LOGIC_OUTS_B1_L_9", - "PCIE_EE4A0_4", - "PCIE_NW4END0_2", - "PCIE_EE4BEG3_9", - "PCIE_IMUX17_R_17", - "PCIE_LOGIC_OUTS_B6_L_18", - "PCIE_WR1END1_17", - "PCIE_LOGIC_OUTS_B8_L_18", - "PCIE_TRNRDLLPDATA25", - "PCIE_PIPERX1DATA4", - "PCIE_CFGERRTLPCPLHEADER28", - "PCIE_WW4B2_19", - "PCIE_IMUX47_R_15", - "PCIE_SW4A1_7", - "PCIE_LOGIC_OUTS_B14_L_11", - "PCIE_EE4A3_6", - "PCIE_NW4A2_8", - "PCIE_CFGDSBUSNUMBER3", - "PCIE_LOGIC_OUTS_B2_L_2", - "PCIE_IMUX19_R_11", - "PCIE_WW4C2_9", - "PCIE_IMUX36_L_17", - "PCIE_CFGMSGDATA5", - "PCIE_IMUX32_R_9", - "PCIE_MONITOR_P_14", - "PCIE_NW2A0_4", - "PCIE_BYP3_L_6", - "PCIE_IMUX2_L_13", - "PCIE_EE4BEG2_5", - "PCIE_LOGIC_OUTS_B4_L_7", - "PCIE_NE4BEG3_5", - "PCIE_CFGDSN39", - "PCIE_CFGERRAERHEADERLOG77", - "PCIE_IMUX10_L_15", - "PCIE_SE4BEG2_9", - "PCIE_IMUX33_R_9", - "PCIE_MIMTXRDATA51", - "PCIE_DBGVECB25", - "PCIE_DBGVECA60", - "PCIE_CFGERRAERHEADERLOG29", - "PCIE_CFGERRAERHEADERLOG67", - "PCIE_BYP2_R_16", - "PCIE_IMUX21_R_15", - "PCIE_TRNRD127", - "PCIE_CFGMGMTDWADDR5", - "PCIE_TRNFCCPLD5", - "PCIE_EE4BEG0_13", - "PCIE_WR1END0_4", - "PCIE_DBGVECB47", - "PCIE_IMUX35_L_13", - "PCIE_MIMTXRDATA44", - "PCIE_LOGIC_OUTS_B14_R_8", - "PCIE_IMUX43_R_15", - "PCIE_DBGVECB27", - "PCIE_PLTRANSMITHOTRST", - "PCIE_IMUX22_L_0", - "PCIE_MIMTXWDATA29", - "PCIE_BYP7_L_15", - "PCIE_IMUX34_L_2", - "PCIE_PIPERX0DATA12", - "PCIE_IMUX46_R_8", - "PCIE_LOGIC_OUTS_B2_R_19", - "PCIE_TRNTD109", - "PCIE_LOGIC_OUTS_B22_L_6", - "PCIE_IMUX19_L_0", - "PCIE_LOGIC_OUTS_B6_R_2", - "PCIE_EE2A3_6", - "PCIE_MIMTXRDATA66", - "PCIE_IMUX34_L_12", - "PCIE_EE4B1_14", - "PCIE_BLOCK_OUTS_B3_R_12", - "PCIE_CTRL1_R_18", - "PCIE_CFGDSN47", - "PCIE_IMUX14_R_2", - "PCIE_MIMRXRDATA50", - "PCIE_LH3_16", - "PCIE_LH5_2", - "PCIE_NE2A0_9", - "PCIE_LOGIC_OUTS_B19_L_19", - "PCIE_WW4A0_1", - "PCIE_PIPERX3DATA1", - "PCIE_LOGIC_OUTS_B16_R_4", - "PCIE_MIMTXWDATA13", - "PCIE_IMUX0_R_7", - "PCIE_LOGIC_OUTS_B5_R_1", - "PCIE_MIMTXRDATA34", - "PCIE_NW2A3_10", - "PCIE_LH11_16", - "PCIE_MIMRXRDATA52", - "PCIE_IMUX6_L_5", - "PCIE_MIMTXWDATA52", - "PCIE_MIMRXRDATA9", - "PCIE_IMUX36_L_19", - "PCIE_SE2A3_14", - "PCIE_EE2A1_12", - "PCIE_WW4C0_17", - "PCIE_NE4C0_19", - "PCIE_CFGERRAERHEADERLOG111", - "PCIE_EE2BEG1_15", - "PCIE_LH12_4", - "PCIE_WW4B3_4", - "PCIE_LOGIC_OUTS_B0_R_6", - "PCIE_PIPETX4DATA11", - "PCIE_IMUX24_R_19", - "PCIE_WW4B0_12", - "PCIE_MIMTXWDATA18", - "PCIE_BLOCK_OUTS_B0_R_13", - "PCIE_TRNRDLLPDATA5", - "PCIE_LOGIC_OUTS_B0_R_13", - "PCIE_LH10_12", - "PCIE_CFGERRAERHEADERLOG112", - "PCIE_WW4B1_11", - "PCIE_CFGAERROOTERRCORRERRRECEIVED", - "PCIE_ER1BEG1_1", - "PCIE_WW4END2_4", - "PCIE_IMUX21_L_4", - "PCIE_BYP4_R_1", - "PCIE_DBGVECA42", - "PCIE_CFGERRAERHEADERLOG8", - "PCIE_FAN0_R_14", - "PCIE_BLOCK_OUTS_B3_R_7", - "PCIE_LOGIC_OUTS_B15_R_5", - "PCIE_TRNTDLLPDATA8", - "PCIE_LOGIC_OUTS_B10_L_14", - "PCIE_IMUX24_L_14", - "PCIE_IMUX35_R_6", - "PCIE_DRPADDR3", - "PCIE_FAN7_R_5", - "PCIE_TRNRD90", - "PCIE_PIPETX6DATA13", - "PCIE_BYP1_L_14", - "PCIE_BLOCK_OUTS_B2_R_13", - "PCIE_IMUX10_L_16", - "PCIE_WR1END1_15", - "PCIE_SW2A2_15", - "PCIE_IMUX34_R_14", - "PCIE_EE4C2_8", - "PCIE_MIMRXRDATA3", - "PCIE_SE2A3_15", - "PCIE_EE2BEG0_13", - "PCIE_WW4A1_1", - "PCIE_IMUX44_L_17", - "PCIE_WW2A0_13", - "PCIE_LOGIC_OUTS_B23_L_19", - "PCIE_LOGIC_OUTS_B15_L_12", - "PCIE_IMUX40_L_4", - "PCIE_IMUX27_R_8", - "PCIE_WR1END0_7", - "PCIE_FAN6_L_11", - "PCIE_IMUX38_R_1", - "PCIE_LH2_14", - "PCIE_LOGIC_OUTS_B9_R_3", - "PCIE_CFGMGMTDI15", - "PCIE_LOGIC_OUTS_B6_R_17", - "PCIE_SE2A3_3", - "PCIE_NW2A2_13", - "PCIE_IMUX10_L_9", - "PCIE_IMUX10_R_3", - "PCIE_WW4C0_0", - "PCIE_PIPETX2COMPLIANCE", - "PCIE_BYP3_L_5", - "PCIE_BYP4_R_9", - "PCIE_WL1END3_8", - "PCIE_MIMTXRDATA39", - "PCIE_EE4BEG2_18", - "PCIE_LH4_12", - "PCIE_EE4C0_2", - "PCIE_IMUX7_R_18", - "PCIE_CFGMGMTDI11", - "PCIE_LOGIC_OUTS_B9_R_6", - "PCIE_WW4B3_19", - "PCIE_SW4A1_13", - "PCIE_TRNTD71", - "PCIE_CFGERRAERHEADERLOG31", - "PCIE_PIPERX0DATA3", - "PCIE_SE2A1_3", - "PCIE_ER1BEG2_15", - "PCIE_NW2A0_7", - "PCIE_LOGIC_OUTS_B8_L_7", - "PCIE_BYP0_L_12", - "PCIE_IMUX39_L_4", - "PCIE_IMUX25_R_9", - "PCIE_PIPERX5DATA3", - "PCIE_LH2_19", - "PCIE_MIMRXRADDR5", - "PCIE_IMUX38_L_19", - "PCIE_BYP6_R_3", - "PCIE_CLK1_R_9", - "PCIE_IMUX32_R_16", - "PCIE_IMUX38_R_10", - "PCIE_TRNTD65", - "PCIE_EE2BEG1_9", - "PCIE_LOGIC_OUTS_B1_L_11", - "PCIE_PIPECLK", - "PCIE_PIPERX1DATA7", - "PCIE_EE4B0_7", - "PCIE_IMUX26_R_15", - "PCIE_SE4C0_6", - "PCIE_IMUX44_R_18", - "PCIE_IMUX22_R_9", - "PCIE_NE4C0_6", - "PCIE_CTRL0_R_11", - "PCIE_IMUX23_L_0", - "PCIE_FAN1_R_6", - "PCIE_FAN1_R_19", - "PCIE_LH9_0", - "PCIE_BYP5_R_12", - "PCIE_BYP4_L_4", - "PCIE_FAN5_R_1", - "PCIE_LOGIC_OUTS_B18_L_10", - "PCIE_TRNTD92", - "PCIE_IMUX19_R_9", - "PCIE_LH12_13", - "PCIE_PIPETX0DATA2", - "PCIE_IMUX7_R_12", - "PCIE_PIPETX0DATA5", - "PCIE_WW4A2_10", - "PCIE_IMUX42_R_5", - "PCIE_WW2END2_4", - "PCIE_SW4A1_4", - "PCIE_PIPERX2VALID", - "PCIE_CFGERRMALFORMEDN", - "PCIE_IMUX13_R_16", - "PCIE_WW2A2_13", - "PCIE_WW2A0_6", - "PCIE_IMUX9_L_2", - "PCIE_CFGDEVSTATUSCORRERRDETECTED", - "PCIE_IMUX2_R_2", - "PCIE_CFGMGMTDO10", - "PCIE_CFGERRAERHEADERLOG22", - "PCIE_IMUX11_R_10", - "PCIE_NE2A2_17", - "PCIE_BYP2_L_12", - "PCIE_ER1BEG3_2", - "PCIE_FAN0_R_3", - "PCIE_IMUX44_R_6", - "PCIE_PIPERX2DATA8", - "PCIE_TRNRD96", - "PCIE_WW2END3_15", - "PCIE_SW4A1_1", - "PCIE_IMUX41_R_10", - "PCIE_IMUX0_L_7", - "PCIE_WW2A0_5", - "PCIE_IMUX46_L_9", - "PCIE_LOGIC_OUTS_B19_L_4", - "PCIE_TRNTD44", - "PCIE_FAN7_L_0", - "PCIE_SE2A0_7", - "PCIE_WW4A1_8", - "PCIE_IMUX2_L_17", - "PCIE_LOGIC_OUTS_B8_L_15", - "PCIE_CFGDSN9", - "PCIE_XILUNCONNOUT8", - "PCIE_IMUX31_L_11", - "PCIE_PIPERX3CHARISK0", - "PCIE_CFGDSN15", - "PCIE_IMUX41_L_16", - "PCIE_CFGVENDID2", - "PCIE_CFGMGMTWRENN", - "PCIE_PIPETX5DATA1", - "PCIE_MIMTXRDATA56", - "PCIE_MIMRXRDATA28", - "PCIE_SW2A0_12", - "PCIE_PIPERX6DATA6", - "PCIE_IMUX0_R_16", - "PCIE_EE4C2_2", - "PCIE_LOGIC_OUTS_B12_R_1", - "PCIE_BLOCK_OUTS_B2_R_15", - "PCIE_WW4C3_2", - "PCIE_FAN6_R_12", - "PCIE_EE4C2_3", - "PCIE_PIPERX2DATA15", - "PCIE_TRNRDLLPDATA48", - "PCIE_LOGIC_OUTS_B7_R_5", - "PCIE_CFGDSN59", - "PCIE_IMUX5_R_0", - "PCIE_IMUX45_L_4", - "PCIE_SW2A1_1", - "PCIE_FAN3_L_9", - "PCIE_LOGIC_OUTS_B12_L_8", - "PCIE_LOGIC_OUTS_B21_R_6", - "PCIE_XILUNCONNOUT4", - "PCIE_BLOCK_OUTS_B3_R_17", - "PCIE_LOGIC_OUTS_B11_L_18", - "PCIE_FAN6_R_2", - "PCIE_PIPETX7DATA9", - "PCIE_NE4C1_10", - "PCIE_CFGAERINTERRUPTMSGNUM3", - "PCIE_NE2A3_0", - "PCIE_LH3_4", - "PCIE_WW2END0_14", - "PCIE_LOGIC_OUTS_B19_R_8", - "PCIE_TRNTD88", - "PCIE_IMUX19_L_13", - "PCIE_NW4END3_8", - "PCIE_LOGIC_OUTS_B20_L_5", - "PCIE_LOGIC_OUTS_B22_R_15", - "PCIE_EE4C1_14", - "PCIE_CLK1_L_12", - "PCIE_NW2A1_11", - "PCIE_TRNRECRCERR", - "PCIE_EE4BEG2_0", - "PCIE_IMUX47_R_5", - "PCIE_IMUX14_L_19", - "PCIE_SW4A3_16", - "PCIE_SW4END3_5", - "PCIE_FAN5_L_4", - "PCIE_TL2ERRHDR35", - "PCIE_IMUX13_R_17", - "PCIE_WW2A0_15", - "PCIE_EE2BEG2_8", - "PCIE_IMUX35_R_16", - "PCIE_DBGVECB38", - "PCIE_CFGDSN6", - "PCIE_NW4END1_13", - "PCIE_SE4BEG1_16", - "PCIE_MIMRXWADDR2", - "PCIE_MIMTXRDATA64", - "PCIE_CLK0_R_5", - "PCIE_CFGSUBSYSVENDID0", - "PCIE_BLOCK_OUTS_B2_L_4", - "PCIE_IMUX41_L_14", - "PCIE_NE2A0_19", - "PCIE_FAN3_R_11", - "PCIE_BLOCK_OUTS_B0_R_9", - "PCIE_NW2A0_16", - "PCIE_IMUX6_L_18", - "PCIE_IMUX38_R_3", - "PCIE_IMUX42_R_4", - "PCIE_LOGIC_OUTS_B14_R_10", - "PCIE_IMUX17_L_19", - "PCIE_IMUX6_R_3", - "PCIE_CFGMSGDATA1", - "PCIE_SW4A2_17", - "PCIE_IMUX45_L_13", - "PCIE_PIPERX5VALID", - "PCIE_IMUX32_R_7", - "PCIE_LOGIC_OUTS_B18_R_16", - "PCIE_TL2ERRHDR2", - "PCIE_BYP3_L_16", - "PCIE_WW4C2_16", - "PCIE_IMUX24_R_3", - "PCIE_IMUX7_R_0", - "PCIE_IMUX31_R_13", - "PCIE_LH12_5", - "PCIE_LOGIC_OUTS_B12_L_6", - "PCIE_PIPERX2STATUS2", - "PCIE_IMUX35_R_7", - "PCIE_BYP4_L_1", - "PCIE_CFGINTERRUPTMSIXFM", - "PCIE_EE4BEG1_17", - "PCIE_IMUX32_R_18", - "PCIE_WR1END0_11", - "PCIE_PIPERX7DATA4", - "PCIE_LOGIC_OUTS_B21_L_9", - "PCIE_SW4A2_12", - "PCIE_LH8_5", - "PCIE_TRNTD29", - "PCIE_SE2A3_11", - "PCIE_LOGIC_OUTS_B11_R_10", - "PCIE_WW4A2_6", - "PCIE_WR1END3_14", - "PCIE_LOGIC_OUTS_B8_R_14", - "PCIE_PIPERX0DATA1", - "PCIE_IMUX43_L_17", - "PCIE_MIMTXRDATA32", - "PCIE_SW4A3_15", - "PCIE_LOGIC_OUTS_B18_R_0", - "PCIE_IMUX47_R_7", - "PCIE_EE4BEG1_7", - "PCIE_FAN2_L_10", - "PCIE_PLLANEREVERSALMODE0", - "PCIE_LOGIC_OUTS_B18_R_17", - "PCIE_BYP0_L_15", - "PCIE_LOGIC_OUTS_B5_R_10", - "PCIE_PIPERX3STATUS1", - "PCIE_LH9_3", - "PCIE_WW2END3_19", - "PCIE_IMUX0_L_11", - "PCIE_LOGIC_OUTS_B13_R_19", - "PCIE_NW4A0_10", - "PCIE_LH11_11", - "PCIE_NE4BEG3_16", - "PCIE_IMUX18_R_14", - "PCIE_CFGVCTCVCMAP0", - "PCIE_TRNRD74", - "PCIE_PL2RECEIVERERR", - "PCIE_IMUX43_R_1", - "PCIE_TRNTCFGREQ", - "PCIE_LL2SENDENTERL23", - "PCIE_SE2A0_16", - "PCIE_PIPERX3VALID", - "PCIE_PIPETX6DATA12", - "PCIE_LOGIC_OUTS_B23_R_16", - "PCIE_PIPETX6DATA1", - "PCIE_IMUX12_R_14", - "PCIE_WW4B1_17", - "PCIE_IMUX28_L_0", - "PCIE_DBGVECB53", - "PCIE_IMUX34_R_1", - "PCIE_IMUX8_R_6", - "PCIE_WW2A2_3", - "PCIE_CLK1_L_4", - "PCIE_NE2A0_5", - "PCIE_IMUX36_L_0", - "PCIE_CFGCOMMANDIOENABLE", - "PCIE_IMUX25_R_15", - "PCIE_IMUX10_R_13", - "PCIE_WW2A2_7", - "PCIE_FAN2_R_3", - "PCIE_SW4END2_13", - "PCIE_FAN4_L_0", - "PCIE_IMUX21_L_1", - "PCIE_LOGIC_OUTS_B16_R_17", - "PCIE_EE4A3_14", - "PCIE_BLOCK_OUTS_B1_L_11", - "PCIE_IMUX30_R_10", - "PCIE_IMUX22_R_6", - "PCIE_BYP6_L_2", - "PCIE_IMUX11_R_18", - "PCIE_LOGIC_OUTS_B2_L_1", - "PCIE_LOGIC_OUTS_B21_L_1", - "PCIE_MIMTXWDATA61", - "PCIE_NW4END2_5", - "PCIE_IMUX41_R_4", - "PCIE_IMUX34_R_17", - "PCIE_IMUX4_R_12", - "PCIE_BYP6_L_1", - "PCIE_CFGLINKSTATUSCURRENTSPEED1", - "PCIE_TRNTDLLPDATA29", - "PCIE_IMUX7_R_16", - "PCIE_BYP2_L_7", - "PCIE_DRPADDR4", - "PCIE_WW4END1_9", - "PCIE_SE4C1_15", - "PCIE_EE4BEG2_17", - "PCIE_EE4A2_16", - "PCIE_CFGERRAERHEADERLOG37", - "PCIE_LOGIC_OUTS_B7_R_4", - "PCIE_EE4C1_17", - "PCIE_BYP0_R_7", - "PCIE_EE4A1_6", - "PCIE_TRNRD52", - "PCIE_BYP7_R_16", - "PCIE_CFGDSDEVICENUMBER4", - "PCIE_LOGIC_OUTS_B17_L_2", - "PCIE_CTRL0_R_15", - "PCIE_SW4END3_11", - "PCIE_WL1END2_7", - "PCIE_EE4B2_5", - "PCIE_CFGPMRCVREQACKN", - "PCIE_CFGDSN17", - "PCIE_SE4BEG0_14", - "PCIE_FAN1_R_0", - "PCIE_FAN1_L_14", - "PCIE_IMUX29_R_4", - "PCIE_LOGIC_OUTS_B4_R_4", - "PCIE_IMUX20_L_12", - "PCIE_BYP2_R_0", - "PCIE_IMUX10_R_18", - "PCIE_IMUX45_L_16", - "PCIE_PIPERX0DATA10", - "PCIE_MIMRXRDATA43", - "PCIE_LL2LINKSTATUS3", - "PCIE_CFGERRAERHEADERLOG7", - "PCIE_IMUX16_R_7", - "PCIE_LOGIC_OUTS_B14_L_15", - "PCIE_MIMRXRADDR4", - "PCIE_WR1END3_13", - "PCIE_EL1BEG0_9", - "PCIE_MIMRXWDATA30", - "PCIE_MIMRXWDATA27", - "PCIE_IMUX23_R_3", - "PCIE_BLOCK_OUTS_B3_R_14", - "PCIE_EL1BEG2_8", - "PCIE_TRNTD123", - "PCIE_LH10_5", - "PCIE_EE4BEG1_15", - "PCIE_NE4BEG2_18", - "PCIE_CFGERRAERHEADERLOG25", - "PCIE_LOGIC_OUTS_B20_R_2", - "PCIE_BYP0_R_9", - "PCIE_IMUX30_R_18", - "PCIE_WL1END1_12", - "PCIE_NE4C2_14", - "PCIE_IMUX21_R_11", - "PCIE_PLLINKUPCFGCAP", - "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", - "PCIE_ER1BEG3_14", - "PCIE_EE4BEG1_11", - "PCIE_IMUX29_R_3", - "PCIE_MIMRXWDATA29", - "PCIE_SE2A2_9", - "PCIE_LOGIC_OUTS_B18_L_3", - "PCIE_SW4END1_5", - "PCIE_LH5_6", - "PCIE_LOGIC_OUTS_B22_R_14", - "PCIE_NW4END2_1", - "PCIE_EE2BEG3_13", - "PCIE_IMUX47_R_11", - "PCIE_NE4BEG1_1", - "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", - "PCIE_WL1END1_19", - "PCIE_IMUX7_R_11", - "PCIE_PLDBGVEC5", - "PCIE_CFGERRAERHEADERLOG36", - "PCIE_CFGERRAERHEADERLOG52", - "PCIE_TL2ERRHDR48", - "PCIE_FAN5_L_14", - "PCIE_IMUX31_R_11", - "PCIE_IMUX22_L_13", - "PCIE_IMUX39_L_5", - "PCIE_DBGVECB0", - "PCIE_IMUX21_R_10", - "PCIE_IMUX23_L_3", - "PCIE_FAN6_L_1", - "PCIE_WW4C1_15", - "PCIE_LOGIC_OUTS_B14_R_3", - "PCIE_IMUX33_L_12", - "PCIE_CFGERRAERHEADERLOG88", - "PCIE_DBGVECA30", - "PCIE_BLOCK_OUTS_B0_R_12", - "PCIE_IMUX30_L_6", - "PCIE_TRNTD105", - "PCIE_IMUX38_L_5", - "PCIE_WW2A3_5", - "PCIE_ER1BEG3_11", - "PCIE_EE4A2_11", - "PCIE_MIMRXWDATA13", - "PCIE_BYP2_L_2", - "PCIE_CFGERRAERHEADERLOG39", - "PCIE_SW4END0_6", - "PCIE_SE2A1_9", - "PCIE_LH7_0", - "PCIE_WW2END1_14", - "PCIE_PIPETX4ELECIDLE", - "PCIE_LOGIC_OUTS_B18_L_17", - "PCIE_IMUX16_L_19", - "PCIE_WW2A0_4", - "PCIE_BYP4_R_0", - "PCIE_PIPETX5POWERDOWN1", - "PCIE_MIMRXWDATA19", - "PCIE_IMUX9_R_16", - "PCIE_BYP7_R_19", - "PCIE_IMUX8_R_14", - "PCIE_LOGIC_OUTS_B0_L_7", - "PCIE_LOGIC_OUTS_B9_L_10", - "PCIE_DBGVECA18", - "PCIE_IMUX12_L_0", - "PCIE_IMUX42_L_3", - "PCIE_IMUX11_L_3", - "PCIE_PIPERX4DATA10", - "PCIE_CFGSUBSYSID9", - "PCIE_SE2A1_12", - "PCIE_DBGVECA40", - "PCIE_TRNRDLLPDATA9", - "PCIE_NE2A3_9", - "PCIE_LOGIC_OUTS_B0_R_4", - "PCIE_CLK1_R_6", - "PCIE_IMUX37_R_5", - "PCIE_NW4END0_9", - "PCIE_EE2A1_2", - "PCIE_WW4END1_0", - "PCIE_XILUNCONNOUT26", - "PCIE_TRNTDLLPDSTRDY", - "PCIE_SW4END0_3", - "PCIE_TRNRDLLPDATA60", - "PCIE_EE4B2_8", - "PCIE_NE4C1_1", - "PCIE_EE4B3_11", - "PCIE_FAN1_L_4", - "PCIE_EE4A3_11", - "PCIE_WL1END2_19", - "PCIE_CLK1_R_2", - "PCIE_FAN2_R_12", - "PCIE_TRNRDLLPDATA51", - "PCIE_BYP2_L_10", - "PCIE_IMUX46_R_10", - "PCIE_FAN2_R_4", - "PCIE_CFGDSN19", - "PCIE_CLK0_L_4", - "PCIE_IMUX46_R_1", - "PCIE_LOGIC_OUTS_B0_R_5", - "PCIE_NW2A1_9", - "PCIE_MIMTXRDATA41", - "PCIE_IMUX25_L_9", - "PCIE_BYP1_R_18", - "PCIE_ER1BEG0_2", - "PCIE_NE4BEG3_8", - "PCIE_NE2A0_15", - "PCIE_LOGIC_OUTS_B17_R_9", - "PCIE_IMUX16_L_12", - "PCIE_WW4END0_8", - "PCIE_LOGIC_OUTS_B9_R_11", - "PCIE_TRNRD115", - "PCIE_FAN7_L_14", - "PCIE_DBGSCLRH", - "PCIE_IMUX10_L_14", - "PCIE_WW4A3_9", - "PCIE_TRNRD27", - "PCIE_BYP2_R_17", - "PCIE_IMUX27_R_10", - "PCIE_LOGIC_OUTS_B8_R_12", - "PCIE_EE2BEG0_7", - "PCIE_LH6_13", - "PCIE_EE4B1_11", - "PCIE_WW4C0_13", - "PCIE_MIMRXRDATA42", - "PCIE_IMUX2_R_13", - "PCIE_PIPETX2DATA15", - "PCIE_LH5_12", - "PCIE_CFGMGMTDI18", - "PCIE_NE2A1_17", - "PCIE_IMUX46_L_16", - "PCIE_LOGIC_OUTS_B9_R_0", - "PCIE_IMUX13_L_4", - "PCIE_LOGIC_OUTS_B23_L_5", - "PCIE_BYP3_L_7", - "PCIE_LOGIC_OUTS_B11_L_16", - "PCIE_IMUX33_L_2", - "PCIE_BYP3_R_9", - "PCIE_LOGIC_OUTS_B21_R_8", - "PCIE_EE2A1_19", - "PCIE_LOGIC_OUTS_B4_R_15", - "PCIE_IMUX9_L_11", - "PCIE_TL2PPMSUSPENDOK", - "PCIE_PIPERX2DATA7", - "PCIE_WW4A1_17", - "PCIE_BYP6_R_0", - "PCIE_BYP3_R_19", - "PCIE_CFGERRAERHEADERLOG121", - "PCIE_TL2ERRHDR52", - "PCIE_IMUX22_L_8", - "PCIE_EE4A0_9", - "PCIE_DRPDO11", - "PCIE_IMUX21_L_3", - "PCIE_NE2A2_8", - "PCIE_NW4A2_18", - "PCIE_CTRL0_L_7", - "PCIE_EE2BEG2_11", - "PCIE_BYP5_R_17", - "PCIE_SW4END1_12", - "PCIE_NW4A3_15", - "PCIE_TL2ERRHDR28", - "PCIE_IMUX40_L_2", - "PCIE_PIPETX2DATA3", - "PCIE_IMUX4_L_2", - "PCIE_EE4BEG1_3", - "PCIE_IMUX16_R_14", - "PCIE_EE4BEG0_19", - "PCIE_IMUX43_L_14", - "PCIE_LOGIC_OUTS_B13_L_13", - "PCIE_LOGIC_OUTS_B0_L_1", - "PCIE_LOGIC_OUTS_B17_L_17", - "PCIE_ER1BEG3_15", - "PCIE_EE4BEG3_19", - "PCIE_LOGIC_OUTS_B9_L_14", - "PCIE_PMVDIVIDE1", - "PCIE_CFGDEVID14", - "PCIE_SW4END2_2", - "PCIE_IMUX21_R_18", - "PCIE_BYP4_L_3", - "PCIE_BLOCK_OUTS_B2_L_10", - "PCIE_LOGIC_OUTS_B5_R_14", - "PCIE_WW2END1_1", - "PCIE_CFGLINKCONTROLRETRAINLINK", - "PCIE_IMUX19_L_11", - "PCIE_LOGIC_OUTS_B15_L_2", - "PCIE_CFGMGMTWRRW1CASRWN", - "PCIE_CFGSUBSYSVENDID9", - "PCIE_IMUX6_L_8", - "PCIE_MIMTXWDATA55", - "PCIE_PIPETX2DATA8", - "PCIE_IMUX38_R_14", - "PCIE_SW2A1_2", - "PCIE_SW4END2_17", - "PCIE_FAN1_L_7", - "PCIE_MIMRXRDATA30", - "PCIE_LOGIC_OUTS_B2_R_14", - "PCIE_MIMTXWDATA68", - "PCIE_SW4END0_8", - "PCIE_EE4B1_16", - "PCIE_EL1BEG0_5", - "PCIE_EE4B2_6", - "PCIE_TRNTD83", - "PCIE_NW2A3_14", - "PCIE_LOGIC_OUTS_B11_L_6", - "PCIE_DBGVECA62", - "PCIE_WW4B1_14", - "PCIE_MIMRXWDATA36", - "PCIE_IMUX30_L_19", - "PCIE_IMUX15_L_8", - "PCIE_BYP0_L_2", - "PCIE_SW4A1_16", - "PCIE_DBGVECA12", - "PCIE_IMUX27_L_3", - "PCIE_FAN3_R_14", - "PCIE_SW4A0_18", - "PCIE_EE4BEG3_3", - "PCIE_SE2A3_12", - "PCIE_IMUX39_L_3", - "PCIE_LOGIC_OUTS_B16_L_2", - "PCIE_PLDBGMODE2", - "PCIE_IMUX17_R_5", - "PCIE_IMUX14_R_5", - "PCIE_TRNRD32", - "PCIE_SW4A2_7", - "PCIE_BYP1_R_13", - "PCIE_LOGIC_OUTS_B20_L_10", - "PCIE_CFGERRAERHEADERLOG68", - "PCIE_CLK0_R_12", - "PCIE_TRNTD2", - "PCIE_NW4A0_13", - "PCIE_TRNTDLLPDATA4", - "PCIE_LOGIC_OUTS_B11_L_1", - "PCIE_PIPETX0DATA7", - "PCIE_IMUX20_R_13", - "PCIE_EE2A0_5", - "PCIE_LOGIC_OUTS_B22_R_17", - "PCIE_IMUX40_L_3", - "PCIE_LOGIC_OUTS_B3_R_0", - "PCIE_PIPERX6DATA11", - "PCIE_FAN1_R_14", - "PCIE_CLK0_R_11", - "PCIE_IMUX39_R_11", - "PCIE_IMUX20_L_6", - "PCIE_IMUX2_L_14", - "PCIE_LH10_3", - "PCIE_TRNTD10", - "PCIE_CFGERRAERHEADERLOG115", - "PCIE_LOGIC_OUTS_B22_L_5", - "PCIE_CFGERRAERHEADERLOG89", - "PCIE_MIMTXWDATA50", - "PCIE_IMUX10_R_12", - "PCIE_WW2A0_2", - "PCIE_TRNTD102", - "PCIE_CFGSUBSYSID10", - "PCIE_SE2A0_1", - "PCIE_PIPERX4DATA7", - "PCIE_NW4A3_14", - "PCIE_DBGSCLRC", - "PCIE_LL2SENDPMACK", - "PCIE_CFGLINKSTATUSCURRENTSPEED0", - "PCIE_LOGIC_OUTS_B18_R_18", - "PCIE_LOGIC_OUTS_B19_L_2", - "PCIE_PLDBGVEC0", - "PCIE_DBGVECA46", - "PCIE_TRNTD24", - "PCIE_IMUX37_R_15", - "PCIE_WL1END0_17", - "PCIE_IMUX11_L_12", - "PCIE_IMUX24_R_13", - "PCIE_NE2A3_13", - "PCIE_IMUX31_L_10", - "PCIE_MIMRXWDATA56", - "PCIE_IMUX23_L_11", - "PCIE_LOGIC_OUTS_B23_L_18", - "PCIE_LOGIC_OUTS_B5_L_1", - "PCIE_IMUX30_R_9", - "PCIE_IMUX8_L_15", - "PCIE_EL1BEG0_19", - "PCIE_EE2A0_17", - "PCIE_IMUX3_R_10", - "PCIE_LOGIC_OUTS_B10_L_15", - "PCIE_BYP5_L_4", - "PCIE_PLDBGVEC10", - "PCIE_FAN1_R_16", - "PCIE_IMUX7_L_18", - "PCIE_LH12_19", - "PCIE_CLK0_R_7", - "PCIE_WW2END1_8", - "PCIE_CTRL1_L_1", - "PCIE_LOGIC_OUTS_B14_R_14", - "PCIE_NW2A0_2", - "PCIE_PIPETX3CHARISK0", - "PCIE_IMUX46_L_4", - "PCIE_CFGERRTLPCPLHEADER43", - "PCIE_WW4B2_4", - "PCIE_IMUX31_L_3", - "PCIE_MIMTXWDATA28", - "PCIE_XILUNCONNOUT36", - "PCIE_PIPETX7DATA3", - "PCIE_LOGIC_OUTS_B2_L_14", - "PCIE_NW4A2_11", - "PCIE_EE2A2_5", - "PCIE_IMUX34_R_3", - "PCIE_NE4C3_5", - "PCIE_TRNRD50", - "PCIE_IMUX12_L_12", - "PCIE_WW4B0_13", - "PCIE_EE4A0_12", - "PCIE_IMUX33_R_10", - "PCIE_PIPERX4DATA0", - "PCIE_TRNRD93", - "PCIE_BYP7_L_13", - "PCIE_LH11_7", - "PCIE_IMUX34_R_7", - "PCIE_MIMTXWADDR0", - "PCIE_BLOCK_OUTS_B0_R_6", - "PCIE_MIMRXWDATA62", - "PCIE_WW4B0_17", - "PCIE_TRNTD50", - "PCIE_LH6_4", - "PCIE_IMUX2_L_6", - "PCIE_BYP5_L_15", - "PCIE_LOGIC_OUTS_B10_R_17", - "PCIE_IMUX43_R_10", - "PCIE_IMUX22_R_14", - "PCIE_SW4A1_9", - "PCIE_WW4END1_14", - "PCIE_IMUX30_L_11", - "PCIE_LOGIC_OUTS_B7_L_2", - "PCIE_NW4END2_14", - "PCIE_PIPERX3DATA11", - "PCIE_WL1END3_5", - "PCIE_LOGIC_OUTS_B3_L_7", - "PCIE_PLDBGMODE0", - "PCIE_FAN4_L_11", - "PCIE_IMUX29_R_14", - "PCIE_WW2A3_12", - "PCIE_PIPETX0DATA9", - "PCIE_SW4A0_9", - "PCIE_SE4BEG0_1", - "PCIE_LOGIC_OUTS_B1_R_13", - "PCIE_CFGERRTLPCPLHEADER3", - "PCIE_BLOCK_OUTS_B2_R_4", - "PCIE_WR1END3_5", - "PCIE_SW4END3_19", - "PCIE_TRNFCPD11", - "PCIE_PIPERX6DATA4", - "PCIE_TRNRDLLPDATA16", - "PCIE_LOGIC_OUTS_B8_L_0", - "PCIE_IMUX31_L_13", - "PCIE_DBGVECC3", - "PCIE_TRNRDLLPDATA2", - "PCIE_SE4BEG1_10", - "PCIE_IMUX24_R_1", - "PCIE_TRNRD18", - "PCIE_IMUX5_L_5", - "PCIE_LOGIC_OUTS_B9_L_12", - "PCIE_SW4A3_0", - "PCIE_BYP0_R_0", - "PCIE_CFGMGMTBYTEENN1", - "PCIE_IMUX10_R_10", - "PCIE_LH4_15", - "PCIE_SW2A2_8", - "PCIE_IMUX22_R_3", - "PCIE_LOGIC_OUTS_B8_L_4", - "PCIE_LH2_3", - "PCIE_LOGIC_OUTS_B6_R_8", - "PCIE_SW2A0_6", - "PCIE_IMUX38_R_16", - "PCIE_CFGERRAERHEADERLOG79", - "PCIE_EE4BEG3_18", - "PCIE_DBGVECB12", - "PCIE_EE4C2_14", - "PCIE_BLOCK_OUTS_B3_R_8", - "PCIE_EE2A2_14", - "PCIE_PIPERX2CHANISALIGNED", - "PCIE_LOGIC_OUTS_B20_L_8", - "PCIE_WL1END3_6", - "PCIE_EL1BEG2_19", - "PCIE_IMUX4_R_2", - "PCIE_BYP4_R_17", - "PCIE_CFGMGMTBYTEENN3", - "PCIE_FAN3_L_4", - "PCIE_WW2END2_9", - "PCIE_WW4A1_16", - "PCIE_TRNRD4", - "PCIE_BLOCK_OUTS_B3_R_18", - "PCIE_IMUX26_L_18", - "PCIE_EE4C2_12", - "PCIE_IMUX28_R_13", - "PCIE_WW2A1_16", - "PCIE_LOGIC_OUTS_B9_L_9", - "PCIE_SE4BEG2_15", - "PCIE_BLOCK_OUTS_B2_L_9", - "PCIE_IMUX21_L_13", - "PCIE_MIMTXRDATA3", - "PCIE_CLK0_R_9", - "PCIE_SW4A1_6", - "PCIE_MIMTXWDATA49", - "PCIE_LOGIC_OUTS_B23_R_0", - "PCIE_CFGERRAERHEADERLOG21", - "PCIE_LOGIC_OUTS_B5_L_4", - "PCIE_LOGIC_OUTS_B14_L_16", - "PCIE_EE4B2_7", - "PCIE_LH12_0", - "PCIE_LH6_11", - "PCIE_PIPERX4DATA8", - "PCIE_MIMTXRDATA19", - "PCIE_CFGDEVSTATUSURDETECTED", - "PCIE_TL2ASPMSUSPENDCREDITCHECK", - "PCIE_FAN4_R_0", - "PCIE_NW2A3_13", - "PCIE_IMUX22_L_9", - "PCIE_PIPERX7DATA6", - "PCIE_WW2END1_6", - "PCIE_EE4C0_7", - "PCIE_LOGIC_OUTS_B1_R_16", - "PCIE_BYP6_L_0", - "PCIE_WL1END0_12", - "PCIE_IMUX34_L_18", - "PCIE_FAN5_L_1", - "PCIE_PIPETX6DATA10", - "PCIE_IMUX36_R_14", - "PCIE_NW2A1_10", - "PCIE_IMUX30_R_17", - "PCIE_IMUX32_L_6", - "PCIE_LOGIC_OUTS_B4_R_14", - "PCIE_IMUX33_L_6", - "PCIE_DRPDI9", - "PCIE_EE4BEG1_5", - "PCIE_MIMTXWDATA65", - "PCIE_LOGIC_OUTS_B1_R_15", - "PCIE_IMUX13_L_18", - "PCIE_MIMRXRDATA38", - "PCIE_IMUX27_R_4", - "PCIE_TL2ERRHDR9", - "PCIE_IMUX30_R_5", - "PCIE_LH2_11", - "PCIE_WW4END3_6", - "PCIE_BLOCK_OUTS_B1_R_16", - "PCIE_NE4C0_17", - "PCIE_IMUX29_L_6", - "PCIE_FAN7_R_18", - "PCIE_IMUX30_R_15", - "PCIE_SW2A0_8", - "PCIE_LH4_19", - "PCIE_LOGIC_OUTS_B16_L_15", - "PCIE_IMUX34_R_12", - "PCIE_FAN6_R_0", - "PCIE_PIPERX7DATA14", - "PCIE_IMUX7_R_1", - "PCIE_PIPERX5DATA10", - "PCIE_WR1END0_18", - "PCIE_IMUX6_L_15", - "PCIE_PLTXPMSTATE2", - "PCIE_CFGPORTNUMBER4", - "PCIE_LOGIC_OUTS_B21_L_13", - "PCIE_IMUX42_R_3", - "PCIE_LOGIC_OUTS_B20_L_13", - "PCIE_NE4BEG1_11", - "PCIE_LOGIC_OUTS_B2_R_7", - "PCIE_BYP4_R_11", - "PCIE_SE4C0_14", - "PCIE_WW4C3_7", - "PCIE_IMUX4_L_16", - "PCIE_WR1END3_12", - "PCIE_NE2A1_5", - "PCIE_IMUX37_R_2", - "PCIE_WW2A3_19", - "PCIE_IMUX43_R_14", - "PCIE_LH8_7", - "PCIE_NE2A1_1", - "PCIE_WW4C3_4", - "PCIE_PIPETX7DATA12", - "PCIE_MIMRXRADDR0", - "PCIE_WW2END2_0", - "PCIE_TRNRD15", - "PCIE_ER1BEG1_16", - "PCIE_IMUX5_L_15", - "PCIE_SW4A0_11", - "PCIE_TL2ERRHDR21", - "PCIE_EE2BEG3_12", - "PCIE_MIMTXRDATA55", - "PCIE_MONITOR_P_5", - "PCIE_WW4END2_12", - "PCIE_CFGERRTLPCPLHEADER29", - "PCIE_SE2A0_6", - "PCIE_EE4C1_13", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", - "PCIE_FAN4_L_16", - "PCIE_LOGIC_OUTS_B4_L_19", - "PCIE_IMUX47_L_12", - "PCIE_BYP6_L_7", - "PCIE_IMUX0_L_2", - "PCIE_LOGIC_OUTS_B12_L_17", - "PCIE_IMUX38_L_9", - "PCIE_IMUX3_R_14", - "PCIE_WW4B2_2", - "PCIE_IMUX13_R_15", - "PCIE_WW4B1_18", - "PCIE_LH10_0", - "PCIE_TRNTDLLPDATA15", - "PCIE_BYP3_R_3", - "PCIE_LH4_16", - "PCIE_TRNTD0", - "PCIE_FAN0_R_4", - "PCIE_CFGPORTNUMBER6", - "PCIE_LOGIC_OUTS_B21_L_18", - "PCIE_IMUX27_L_15", - "PCIE_IMUX4_L_9", - "PCIE_NE4C0_7", - "PCIE_PIPETX5DATA11", - "PCIE_NE2A2_11", - "PCIE_TRNRDLLPDATA55", - "PCIE_FAN5_R_3", - "PCIE_NE4C0_0", - "PCIE_ER1BEG0_0", - "PCIE_BYP3_L_8", - "PCIE_BLOCK_OUTS_B0_L_17", - "PCIE_LOGIC_OUTS_B16_R_19", - "PCIE_BYP2_R_10", - "PCIE_WR1END1_6", - "PCIE_IMUX4_R_3", - "PCIE_EE2A3_15", - "PCIE_BYP1_R_14", - "PCIE_IMUX28_R_12", - "PCIE_IMUX22_L_6", - "PCIE_IMUX31_L_14", - "PCIE_PIPERX1DATA12", - "PCIE_LOGIC_OUTS_B20_L_4", - "PCIE_IMUX13_R_19", - "PCIE_WW2END0_15", - "PCIE_EE4B0_15", - "PCIE_IMUX1_R_19", - "PCIE_EL1BEG1_18", - "PCIE_PIPERX0DATA8", - "PCIE_LOGIC_OUTS_B14_L_1", - "PCIE_PIPERX7STATUS1", - "PCIE_MIMTXWDATA9", - "PCIE_IMUX0_L_12", - "PCIE_IMUX29_R_19", - "PCIE_LOGIC_OUTS_B23_R_15", - "PCIE_MIMTXWDATA35", - "PCIE_MIMTXRDATA48", - "PCIE_IMUX15_L_16", - "PCIE_LH2_0", - "PCIE_SE4C3_19", - "PCIE_PIPERX1DATA3", - "PCIE_IMUX6_R_8", - "PCIE_LOGIC_OUTS_B3_R_18", - "PCIE_LOGIC_OUTS_B5_R_0", - "PCIE_LH2_16", - "PCIE_LH7_7", - "PCIE_LH9_4", - "PCIE_BYP1_R_6", - "PCIE_CTRL0_L_4", - "PCIE_IMUX16_L_13", - "PCIE_IMUX39_R_5", - "PCIE_TRNFCPH5", - "PCIE_WR1END1_3", - "PCIE_WW4END3_4", - "PCIE_IMUX14_L_7", - "PCIE_CFGMSGRECEIVED", - "PCIE_WW2A1_7", - "PCIE_FAN4_R_10", - "PCIE_LOGIC_OUTS_B2_R_11", - "PCIE_EE4B3_1", - "PCIE_EE2BEG1_14", - "PCIE_IMUX24_L_5", - "PCIE_TRNRD69", - "PCIE_IMUX3_L_19", - "PCIE_CFGERRTLPCPLHEADER34", - "PCIE_SE4BEG3_0", - "PCIE_IMUX39_R_14", - "PCIE_WW2A3_4", - "PCIE_LOGIC_OUTS_B22_R_9", - "PCIE_IMUX39_R_4", - "PCIE_BYP1_L_0", - "PCIE_BYP6_R_7", - "PCIE_IMUX4_R_14", - "PCIE_PIPETX6DATA9", - "PCIE_IMUX31_L_2", - "PCIE_PIPERX3DATA8", - "PCIE_EE4B2_11", - "PCIE_IMUX46_L_1", - "PCIE_NW4A1_7", - "PCIE_WW2END1_18", - "PCIE_MIMRXRDATA2", - "PCIE_TRNRDLLPDATA12", - "PCIE_LOGIC_OUTS_B1_L_1", - "PCIE_WW4B0_11", - "PCIE_IMUX47_L_5", - "PCIE_WW2A3_15", - "PCIE_PIPERX3DATA7", - "PCIE_IMUX31_R_3", - "PCIE_LOGIC_OUTS_B7_R_18", - "PCIE_WW4A3_19", - "PCIE_BLOCK_OUTS_B0_R_1", - "PCIE_WW4B2_8", - "PCIE_LOGIC_OUTS_B9_L_1", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", - "PCIE_IMUX25_L_14", - "PCIE_MIMTXWADDR7", - "PCIE_WW4C0_10", - "PCIE_PLSELLNKWIDTH1", - "PCIE_NW4END0_8", - "PCIE_BYP2_L_15", - "PCIE_NE2A2_6", - "PCIE_IMUX36_R_19", - "PCIE_IMUX37_L_12", - "PCIE_SE4BEG0_11", - "PCIE_LOGIC_OUTS_B22_L_0", - "PCIE_MIMRXRDATA48", - "PCIE_IMUX20_L_15", - "PCIE_SW4A3_14", - "PCIE_FAN6_R_14", - "PCIE_IMUX22_R_15", - "PCIE_IMUX9_L_14", - "PCIE_PIPETX4CHARISK1", - "PCIE_LOGIC_OUTS_B0_R_8", - "PCIE_IMUX9_R_4", - "PCIE_NE4BEG1_16", - "PCIE_NE4C0_5", - "PCIE_CLK1_R_8", - "PCIE_LH9_6", - "PCIE_LOGIC_OUTS_B12_R_11", - "PCIE_TRNTD64", - "PCIE_TL2ERRHDR0", - "PCIE_DRPDO2", - "PCIE_FAN4_R_5", - "PCIE_PIPETX7DATA11", - "PCIE_LOGIC_OUTS_B9_L_6", - "PCIE_IMUX18_L_15", - "PCIE_WW2END3_3", - "PCIE_IMUX0_L_5", - "PCIE_CFGDEVCONTROLMAXREADREQ0", - "PCIE_IMUX46_R_11", - "PCIE_EE4B3_6", - "PCIE_LOGIC_OUTS_B3_L_5", - "PCIE_EE4B0_12", - "PCIE_TRNTSRCRDY", - "PCIE_BYP5_R_0", - "PCIE_MONITOR_P_10", - "PCIE_CFGDSN62", - "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", - "PCIE_IMUX17_R_8", - "PCIE_MIMTXWDATA22", - "PCIE_BLOCK_OUTS_B3_R_16", - "PCIE_IMUX5_R_10", - "PCIE_PL2RXELECIDLE", - "PCIE_IMUX32_R_8", - "PCIE_IMUX46_R_9", - "PCIE_IMUX5_R_6", - "PCIE_IMUX26_L_16", - "PCIE_LOGIC_OUTS_B4_R_0", - "PCIE_CTRL1_R_10", - "PCIE_EL1BEG0_7", - "PCIE_DBGVECB37", - "PCIE_PIPETX1DATA15", - "PCIE_DRPDO5", - "PCIE_WW2END0_16", - "PCIE_LOGIC_OUTS_B21_R_13", - "PCIE_NE2A3_6", - "PCIE_TRNRD33", - "PCIE_PIPERX7DATA0", - "PCIE_NW4END2_17", - "PCIE_IMUX9_R_6", - "PCIE_IMUX11_R_15", - "PCIE_LOGIC_OUTS_B6_R_4", - "PCIE_IMUX24_L_7", - "PCIE_CFGERRAERHEADERLOG69", - "PCIE_SE2A3_10", - "PCIE_SW2A0_11", - "PCIE_IMUX15_R_3", - "PCIE_LOGIC_OUTS_B21_L_5", - "PCIE_XILUNCONNOUT23", - "PCIE_EDTCHANNELSOUT7", - "PCIE_PIPETX4DATA2", - "PCIE_FAN6_L_2", - "PCIE_MIMRXWDATA50", - "PCIE_IMUX16_R_17", - "PCIE_IMUX39_R_10", - "PCIE_EE4BEG3_1", - "PCIE_TRNRDLLPDATA30", - "PCIE_LOGIC_OUTS_B23_L_12", - "PCIE_IMUX16_R_3", - "PCIE_LH8_13", - "PCIE_LOGIC_OUTS_B14_R_4", - "PCIE_NE4BEG3_13", - "PCIE_LH5_9", - "PCIE_SE4C2_19", - "PCIE_NW2A2_2", - "PCIE_IMUX33_L_19", - "PCIE_DBGVECA55", - "PCIE_IMUX37_L_4", - "PCIE_PIPERX1CHANISALIGNED", - "PCIE_DRPDI12", - "PCIE_IMUX8_L_10", - "PCIE_EE4A0_16", - "PCIE_TRNTDSTRDY3", - "PCIE_BYP2_R_1", - "PCIE_LOGIC_OUTS_B21_L_2", - "PCIE_LOGIC_OUTS_B0_L_9", - "PCIE_FAN4_L_15", - "PCIE_CFGDSBUSNUMBER1", - "PCIE_CFGVENDID15", - "PCIE_SW4A3_7", - "PCIE_LH7_4", - "PCIE_WW2END3_14", - "PCIE_NE4BEG3_17", - "PCIE_PIPETX6DATA6", - "PCIE_LOGIC_OUTS_B2_L_3", - "PCIE_IMUX40_R_17", - "PCIE_TL2ERRHDR5", - "PCIE_MIMTXWDATA66", - "PCIE_MIMTXRDATA33", - "PCIE_NW4A3_17", - "PCIE_EE4C2_4", - "PCIE_MIMRXWDATA12", - "PCIE_NW4END2_10", - "PCIE_IMUX40_R_14", - "PCIE_SW4END3_10", - "PCIE_IMUX0_R_3", - "PCIE_WL1END2_3", - "PCIE_IMUX40_R_19", - "PCIE_LH4_0", - "PCIE_IMUX42_R_11", - "PCIE_LOGIC_OUTS_B15_R_10", - "PCIE_TRNTD111", - "PCIE_BYP5_R_15", - "PCIE_TRNFCCPLH2", - "PCIE_IMUX32_R_1", - "PCIE_IMUX33_R_13", - "PCIE_CFGERRAERHEADERLOG117", - "PCIE_SW4A3_8", - "PCIE_WW4END2_16", - "PCIE_IMUX34_L_5", - "PCIE_LOGIC_OUTS_B3_R_1", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", - "PCIE_LOGIC_OUTS_B0_L_0", - "PCIE_PIPETX6DATA0", - "PCIE_IMUX36_L_8", - "PCIE_NW2A2_17", - "PCIE_LH5_11", - "PCIE_NE2A0_1", - "PCIE_SW2A2_3", - "PCIE_IMUX45_L_19", - "PCIE_TRNTD33", - "PCIE_LOGIC_OUTS_B23_L_10", - "PCIE_IMUX9_R_5", - "PCIE_MIMTXWDATA11", - "PCIE_IMUX1_L_19", - "PCIE_TRNTD17", - "PCIE_LOGIC_OUTS_B2_R_2", - "PCIE_SE2A0_12", - "PCIE_FAN0_L_5", - "PCIE_IMUX17_R_0", - "PCIE_PIPERX6DATA3", - "PCIE_LOGIC_OUTS_B5_L_14", - "PCIE_SW2A2_6", - "PCIE_LOGIC_OUTS_B11_R_6", - "PCIE_FAN6_R_1", - "PCIE_FAN0_R_10", - "PCIE_IMUX20_R_18", - "PCIE_CFGERRTLPCPLHEADER24", - "PCIE_FAN3_L_15", - "PCIE_IMUX13_R_14", - "PCIE_FAN1_R_13", - "PCIE_CFGLINKCONTROLLINKDISABLE", - "PCIE_SW4A0_17", - "PCIE_PIPETX4DATA8", - "PCIE_SW4END2_3", - "PCIE_IMUX42_R_17", - "PCIE_SW2A2_9", - "PCIE_FAN5_L_16", - "PCIE_LOGIC_OUTS_B15_L_3", - "PCIE_WW4C1_12", - "PCIE_CFGERRAERHEADERLOG43", - "PCIE_WW4A2_1", - "PCIE_WW4END3_10", - "PCIE_IMUX2_L_1", - "PCIE_WW4C2_11", - "PCIE_LOGIC_OUTS_B7_R_13", - "PCIE_IMUX36_R_12", - "PCIE_WR1END1_1", - "PCIE_NE2A1_11", - "PCIE_WW4END3_16", - "PCIE_MIMTXRDATA2", - "PCIE_WL1END3_11", - "PCIE_LOGIC_OUTS_B5_R_9", - "PCIE_IMUX20_L_1", - "PCIE_MONITOR_N_16", - "PCIE_EE4BEG1_14", - "PCIE_IMUX21_L_14", - "PCIE_MIMRXWDATA60", - "PCIE_IMUX5_L_1", - "PCIE_MIMTXWDATA26", - "PCIE_MIMTXRDATA43", - "PCIE_LOGIC_OUTS_B4_R_8", - "PCIE_TRNTD117", - "PCIE_IMUX46_R_16", - "PCIE_IMUX12_R_11", - "PCIE_DRPADDR2", - "PCIE_LOGIC_OUTS_B23_L_15", - "PCIE_FAN3_R_16", - "PCIE_SE4C0_0", - "PCIE_IMUX0_R_14", - "PCIE_IMUX33_R_12", - "PCIE_IMUX6_L_9", - "PCIE_EL1BEG1_7", - "PCIE_IMUX22_L_1", - "PCIE_LH8_16", - "PCIE_CFGDSBUSNUMBER6", - "PCIE_SW2A2_16", - "PCIE_BLOCK_OUTS_B1_L_2", - "PCIE_CFGDSN23", - "PCIE_CFGREVID5", - "PCIE_LOGIC_OUTS_B13_R_3", - "PCIE_IMUX12_L_13", - "PCIE_IMUX26_R_12", - "PCIE_PIPETX3DATA15", - "PCIE_TRNTD41", - "PCIE_EE4B2_16", - "PCIE_TRNRD117", - "PCIE_WW4C1_8", - "PCIE_LOGIC_OUTS_B16_R_16", - "PCIE_CFGDSN61", - "PCIE_WL1END2_8", - "PCIE_FAN3_L_14", - "PCIE_CFGERRAERHEADERLOG74", - "PCIE_EL1BEG0_16", - "PCIE_EE4BEG0_14", - "PCIE_FAN2_L_17", - "PCIE_LOGIC_OUTS_B8_L_13", - "PCIE_CTRL1_L_3", - "PCIE_NW4END1_4", - "PCIE_WW4B3_11", - "PCIE_CFGINTERRUPTDI6", - "PCIE_IMUX14_R_1", - "PCIE_EE2A3_11", - "PCIE_IMUX16_R_8", - "PCIE_CFGVENDID1", - "PCIE_CFGDEVID6", - "PCIE_EE4A1_13", - "PCIE_IMUX18_L_9", - "PCIE_SE4C3_16", - "PCIE_LH11_1", - "PCIE_BYP5_L_7", - "PCIE_SW4END3_1", - "PCIE_WW4A1_19", - "PCIE_LOGIC_OUTS_B0_L_15", - "PCIE_FAN2_R_10", - "PCIE_WW4A3_16", - "PCIE_WW2A1_1", - "PCIE_SE4BEG3_19", - "PCIE_PIPERX7DATA11", - "PCIE_LOGIC_OUTS_B8_R_4", - "PCIE_FAN2_L_4", - "PCIE_NW4A0_2", - "PCIE_EE2BEG0_17", - "PCIE_FAN6_L_18", - "PCIE_IMUX1_L_18", - "PCIE_CFGDSFUNCTIONNUMBER1", - "PCIE_LOGIC_OUTS_B17_R_16", - "PCIE_EE2BEG3_9", - "PCIE_WR1END3_9", - "PCIE_SW4END2_6", - "PCIE_FAN3_L_19", - "PCIE_MIMRXRDATA53", - "PCIE_CFGDSN11", - "PCIE_EDTCHANNELSOUT3", - "PCIE_IMUX29_R_1", - "PCIE_BYP7_R_6", - "PCIE_MIMRXRDATA17", - "PCIE_BYP1_R_16", - "PCIE_MIMTXRDATA13", - "PCIE_LOGIC_OUTS_B1_R_6", - "PCIE_IMUX1_L_4", - "PCIE_DRPDI14", - "PCIE_SW2A2_14", - "PCIE_MIMTXWDATA23", - "PCIE_TRNTD101", - "PCIE_FAN7_L_11", - "PCIE_EL1BEG3_13", - "PCIE_CTRL1_L_16", - "PCIE_LOGIC_OUTS_B15_L_1", - "PCIE_MIMTXRDATA22", - "PCIE_CFGMGMTDO14", - "PCIE_CTRL0_L_12", - "PCIE_BYP3_L_11", - "PCIE_LOGIC_OUTS_B11_R_15", - "PCIE_LOGIC_OUTS_B11_L_10", - "PCIE_MIMTXRDATA12", - "PCIE_TRNTD60", - "PCIE_EL1BEG3_5", - "PCIE_IMUX43_R_18", - "PCIE_CFGPORTNUMBER5", - "PCIE_BYP5_R_19", - "PCIE_IMUX12_L_18", - "PCIE_MIMRXRADDR9", - "PCIE_CLK0_L_16", - "PCIE_MIMRXRDATA24", - "PCIE_TRNTD115", - "PCIE_SW2A0_5", - "PCIE_TRNTD103", - "PCIE_IMUX28_L_8", - "PCIE_TL2ERRHDR29", - "PCIE_NE4C2_0", - "PCIE_PIPETX4DATA4", - "PCIE_CFGPORTNUMBER0", - "PCIE_CFGVENDID5", - "PCIE_BYP4_R_19", - "PCIE_IMUX38_R_19", - "PCIE_TRNTD4", - "PCIE_IMUX29_R_8", - "PCIE_LOGIC_OUTS_B21_R_7", - "PCIE_EL1BEG1_5", - "PCIE_LOGIC_OUTS_B10_L_16", - "PCIE_IMUX25_R_12", - "PCIE_LOGIC_OUTS_B4_R_7", - "PCIE_IMUX20_L_19", - "PCIE_LOGIC_OUTS_B12_R_5", - "PCIE_SW4END2_14", - "PCIE_EE2BEG0_9", - "PCIE_IMUX36_L_7", - "PCIE_MIMTXRDATA50", - "PCIE_BYP6_L_14", - "PCIE_BYP5_R_8", - "PCIE_EE4C2_18", - "PCIE_LH11_10", - "PCIE_PIPERX5DATA7", - "PCIE_EE4BEG1_18", - "PCIE_IMUX31_L_8", - "PCIE_IMUX9_L_8", - "PCIE_SE4BEG1_1", - "PCIE_IMUX28_R_10", - "PCIE_WW2A2_1", - "PCIE_SE4C0_5", - "PCIE_LH7_6", - "PCIE_NW4END2_11", - "PCIE_LH7_8", - "PCIE_IMUX4_R_17", - "PCIE_WW4END0_0", - "PCIE_CLK1_L_13", - "PCIE_EE4A1_16", - "PCIE_DRPDO13", - "PCIE_IMUX39_R_13", - "PCIE_LOGIC_OUTS_B2_R_10", - "PCIE_IMUX24_R_8", - "PCIE_WW4B3_2", - "PCIE_LH8_8", - "PCIE_CFGMGMTDO29", - "PCIE_CFGERRCPLTIMEOUTN", - "PCIE_CFGSUBSYSID2", - "PCIE_EE4A2_13", - "PCIE_CFGERRTLPCPLHEADER37", - "PCIE_WW2END2_13", - "PCIE_CFGMGMTDO0", - "PCIE_EE2A2_19", - "PCIE_IMUX24_L_10", - "PCIE_IMUX10_L_12", - "PCIE_NW4END1_9", - "PCIE_TRNRD77", - "PCIE_LOGIC_OUTS_B9_L_0", - "PCIE_PIPERX0POLARITY", - "PCIE_IMUX8_L_11", - "PCIE_BYP5_R_10", - "PCIE_BYP0_R_1", - "PCIE_IMUX32_L_12", - "PCIE_IMUX32_R_17", - "PCIE_IMUX26_R_19", - "PCIE_SW2A1_3", - "PCIE_LOGIC_OUTS_B16_R_11", - "PCIE_MIMRXRADDR2", - "PCIE_CFGMGMTDO24", - "PCIE_SE4C3_12", - "PCIE_IMUX14_L_2", - "PCIE_NW4END2_9", - "PCIE_IMUX28_R_1", - "PCIE_IMUX13_R_13", - "PCIE_WW4B2_6", - "PCIE_WL1END1_4", - "PCIE_LOGIC_OUTS_B11_R_16", - "PCIE_FAN2_R_13", - "PCIE_NE4BEG1_6", - "PCIE_LOGIC_OUTS_B21_L_14", - "PCIE_NW2A0_12", - "PCIE_FAN1_R_3", - "PCIE_LOGIC_OUTS_B4_L_13", - "PCIE_TL2ERRHDR42", - "PCIE_FAN6_L_16", - "PCIE_TRNTDLLPDATA19", - "PCIE_MIMRXRDATA62", - "PCIE_NE4BEG1_8", - "PCIE_LOGIC_OUTS_B8_R_5", - "PCIE_LOGIC_OUTS_B4_R_12", - "PCIE_CFGSUBSYSVENDID12", - "PCIE_FAN7_R_17", - "PCIE_LOGIC_OUTS_B13_L_16", - "PCIE_LOGIC_OUTS_B22_L_11", - "PCIE_SW4A1_14", - "PCIE_NE4C1_16", - "PCIE_WR1END3_10", - "PCIE_FAN2_L_2", - "PCIE_WR1END2_6", - "PCIE_LOGIC_OUTS_B14_R_1", - "PCIE_LOGIC_OUTS_B18_L_0", - "PCIE_EE4B2_10", - "PCIE_IMUX24_L_8", - "PCIE_TRNTBUFAV2", - "PCIE_LOGIC_OUTS_B16_R_6", - "PCIE_BYP3_L_10", - "PCIE_LH7_3", - "PCIE_IMUX4_R_0", - "PCIE_LH9_7", - "PCIE_FAN1_L_0", - "PCIE_NW4END0_14", - "PCIE_IMUX31_R_0", - "PCIE_IMUX0_L_8", - "PCIE_IMUX33_R_7", - "PCIE_SW2A0_16", - "PCIE_EE2BEG3_7", - "PCIE_BLOCK_OUTS_B2_R_7", - "PCIE_LOGIC_OUTS_B16_L_6", - "PCIE_IMUX40_R_15", - "PCIE_EE4B1_18", - "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", - "PCIE_LOGIC_OUTS_B8_L_17", - "PCIE_ER1BEG0_7", - "PCIE_LOGIC_OUTS_B20_L_0", - "PCIE_MONITOR_N_14", - "PCIE_LH2_10", - "PCIE_FAN7_R_15", - "PCIE_PIPERX0DATA6", - "PCIE_TL2ERRHDR24", - "PCIE_XILUNCONNOUT6", - "PCIE_NE4BEG1_0", - "PCIE_EE2A0_2", - "PCIE_CFGMGMTDWADDR7", - "PCIE_PMVOUT", - "PCIE_TRNRDLLPDATA26", - "PCIE_EE4B0_4", - "PCIE_FAN4_R_8", - "PCIE_IMUX33_L_17" - ], - "sites": [ - { - "prefix": "PCIE", - "y_coord": 0, - "type": "PCIE_2_1", - "site_pins": { - "CFGERRAERHEADERLOG38": "PCIE_CFGERRAERHEADERLOG38", - "TLRSTN": "PCIE_TLRSTN", - "CFGERRTLPCPLHEADER45": "PCIE_CFGERRTLPCPLHEADER45", - "CFGDEVCONTROL2ARIFORWARDEN": "PCIE_CFGDEVCONTROL2ARIFORWARDEN", - "MIMTXWDATA34": "PCIE_MIMTXWDATA34", - "PIPERX7DATA4": "PCIE_PIPERX7DATA4", - "DBGVECA52": "PCIE_DBGVECA52", - "PIPETX1DATA4": "PCIE_PIPETX1DATA4", - "MIMRXRDATA41": "PCIE_MIMRXRDATA41", - "MIMTXRDATA21": "PCIE_MIMTXRDATA21", - "TRNRD48": "PCIE_TRNRD48", - "CFGMSGRECEIVEDDEASSERTINTC": "PCIE_CFGMSGRECEIVEDDEASSERTINTC", - "EDTCHANNELSIN6": "PCIE_EDTCHANNELSIN6", - "XILUNCONNOUT25": "PCIE_XILUNCONNOUT25", - "CFGERRAERHEADERLOG69": "PCIE_CFGERRAERHEADERLOG69", - "DBGMODE1": "PCIE_DBGMODE1", - "CFGERRAERHEADERLOG97": "PCIE_CFGERRAERHEADERLOG97", - "TRNTD17": "PCIE_TRNTD17", - "XILUNCONNOUT39": "PCIE_XILUNCONNOUT39", - "PMVDIVIDE1": "PCIE_PMVDIVIDE1", - "PL2L0REQ": "PCIE_PL2L0REQ", - "TRNFCNPD4": "PCIE_TRNFCNPD4", - "EDTCHANNELSOUT6": "PCIE_EDTCHANNELSOUT6", - "TL2ERRHDR14": "PCIE_TL2ERRHDR14", - "MIMRXWDATA31": "PCIE_MIMRXWDATA31", - "CFGSUBSYSVENDID5": "PCIE_CFGSUBSYSVENDID5", - "CFGERRAERHEADERLOG41": "PCIE_CFGERRAERHEADERLOG41", - "CFGDEVCONTROLEXTTAGEN": "PCIE_CFGDEVCONTROLEXTTAGEN", - "PIPERX4CHANISALIGNED": "PCIE_PIPERX4CHANISALIGNED", - "CFGMSGDATA15": "PCIE_CFGMSGDATA15", - "PIPERX3CHARISK1": "PCIE_PIPERX3CHARISK1", - "CFGMGMTDWADDR2": "PCIE_CFGMGMTDWADDR2", - "TRNTD117": "PCIE_TRNTD117", - "MIMTXWADDR11": "PCIE_MIMTXWADDR11", - "TRNTD87": "PCIE_TRNTD87", - "CFGDSN0": "PCIE_CFGDSN0", - "TRNRD117": "PCIE_TRNRD117", - "PIPERX6STATUS2": "PCIE_PIPERX6STATUS2", - "TRNTERRFWD": "PCIE_TRNTERRFWD", - "CFGMSGRECEIVEDSETSLOTPOWERLIMIT": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", - "DBGVECA7": "PCIE_DBGVECA7", - "CFGVENDID3": "PCIE_CFGVENDID3", - "CFGERRTLPCPLHEADER29": "PCIE_CFGERRTLPCPLHEADER29", - "PIPERX1ELECIDLE": "PCIE_PIPERX1ELECIDLE", - "PIPETX3DATA1": "PCIE_PIPETX3DATA1", - "TRNTD83": "PCIE_TRNTD83", - "XILUNCONNOUT37": "PCIE_XILUNCONNOUT37", - "TRNTDLLPDATA12": "PCIE_TRNTDLLPDATA12", - "CFGLINKCONTROLASPMCONTROL0": "PCIE_CFGLINKCONTROLASPMCONTROL0", - "CFGERRAERHEADERLOG98": "PCIE_CFGERRAERHEADERLOG98", - "CFGERRTLPCPLHEADER41": "PCIE_CFGERRTLPCPLHEADER41", - "MIMRXRDATA9": "PCIE_MIMRXRDATA9", - "CFGMSGRECEIVEDASSERTINTC": "PCIE_CFGMSGRECEIVEDASSERTINTC", - "DRPADDR1": "PCIE_DRPADDR1", - "TRNFCPH5": "PCIE_TRNFCPH5", - "CFGAERECRCGENEN": "PCIE_CFGAERECRCGENEN", - "PIPERX2PHYSTATUS": "PCIE_PIPERX2PHYSTATUS", - "CFGSUBSYSVENDID11": "PCIE_CFGSUBSYSVENDID11", - "CFGERRAERHEADERLOG40": "PCIE_CFGERRAERHEADERLOG40", - "PL2RECEIVERERR": "PCIE_PL2RECEIVERERR", - "PIPERX5CHANISALIGNED": "PCIE_PIPERX5CHANISALIGNED", - "TRNTREM0": "PCIE_TRNTREM0", - "TRNRD22": "PCIE_TRNRD22", - "EDTCHANNELSOUT4": "PCIE_EDTCHANNELSOUT4", - "CFGCOMMANDINTERRUPTDISABLE": "PCIE_CFGCOMMANDINTERRUPTDISABLE", - "CFGERRTLPCPLHEADER17": "PCIE_CFGERRTLPCPLHEADER17", - "PIPERX3DATA0": "PCIE_PIPERX3DATA0", - "MIMTXRDATA17": "PCIE_MIMTXRDATA17", - "PIPERX0PHYSTATUS": "PCIE_PIPERX0PHYSTATUS", - "CFGERRAERHEADERLOG42": "PCIE_CFGERRAERHEADERLOG42", - "PIPETX4DATA0": "PCIE_PIPETX4DATA0", - "PIPERX1PHYSTATUS": "PCIE_PIPERX1PHYSTATUS", - "DRPADDR5": "PCIE_DRPADDR5", - "MIMRXWDATA23": "PCIE_MIMRXWDATA23", - "CFGDSBUSNUMBER1": "PCIE_CFGDSBUSNUMBER1", - "CFGERRAERHEADERLOG12": "PCIE_CFGERRAERHEADERLOG12", - "MIMRXRDATA35": "PCIE_MIMRXRDATA35", - "DBGVECB2": "PCIE_DBGVECB2", - "TRNRD81": "PCIE_TRNRD81", - "MIMTXRDATA7": "PCIE_MIMTXRDATA7", - "CFGSUBSYSVENDID15": "PCIE_CFGSUBSYSVENDID15", - "CFGERRINTERNALUNCORN": "PCIE_CFGERRINTERNALUNCORN", - "PIPETX7DATA15": "PCIE_PIPETX7DATA15", - "MIMRXRDATA57": "PCIE_MIMRXRDATA57", - "CFGMGMTDWADDR5": "PCIE_CFGMGMTDWADDR5", - "CFGERRAERHEADERLOG5": "PCIE_CFGERRAERHEADERLOG5", - "MIMRXWDATA40": "PCIE_MIMRXWDATA40", - "MIMTXWDATA30": "PCIE_MIMTXWDATA30", - "MIMTXWDATA61": "PCIE_MIMTXWDATA61", - "CFGPMCSRPOWERSTATE0": "PCIE_CFGPMCSRPOWERSTATE0", - "CFGERRAERHEADERLOG106": "PCIE_CFGERRAERHEADERLOG106", - "TL2ERRHDR26": "PCIE_TL2ERRHDR26", - "CFGERRATOMICEGRESSBLOCKEDN": "PCIE_CFGERRATOMICEGRESSBLOCKEDN", - "PIPERX1STATUS1": "PCIE_PIPERX1STATUS1", - "CFGDEVCONTROLFATALERRREPORTINGEN": "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", - "MIMRXWDATA0": "PCIE_MIMRXWDATA0", - "MIMTXWDATA24": "PCIE_MIMTXWDATA24", - "CFGERRAERHEADERLOG31": "PCIE_CFGERRAERHEADERLOG31", - "CFGERRTLPCPLHEADER32": "PCIE_CFGERRTLPCPLHEADER32", - "CFGDSN52": "PCIE_CFGDSN52", - "XILUNCONNOUT9": "PCIE_XILUNCONNOUT9", - "CFGINTERRUPTDI1": "PCIE_CFGINTERRUPTDI1", - "PIPERX4ELECIDLE": "PCIE_PIPERX4ELECIDLE", - "DRPDO4": "PCIE_DRPDO4", - "TRNRDLLPDATA7": "PCIE_TRNRDLLPDATA7", - "TRNTD76": "PCIE_TRNTD76", - "MIMTXRDATA45": "PCIE_MIMTXRDATA45", - "TL2ERRHDR34": "PCIE_TL2ERRHDR34", - "PMVSELECT1": "PCIE_PMVSELECT1", - "MIMRXRDATA7": "PCIE_MIMRXRDATA7", - "CFGDSN34": "PCIE_CFGDSN34", - "PIPETX2DATA14": "PCIE_PIPETX2DATA14", - "CFGDSN49": "PCIE_CFGDSN49", - "CFGMGMTDI13": "PCIE_CFGMGMTDI13", - "TRNRD112": "PCIE_TRNRD112", - "PIPETX7DATA9": "PCIE_PIPETX7DATA9", - "PIPERX1CHARISK1": "PCIE_PIPERX1CHARISK1", - "DRPDO0": "PCIE_DRPDO0", - "TRNTD21": "PCIE_TRNTD21", - "CFGERRTLPCPLHEADER1": "PCIE_CFGERRTLPCPLHEADER1", - "PLSELLNKRATE": "PCIE_PLSELLNKRATE", - "CFGDEVCONTROL2TLPPREFIXBLOCK": "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", - "PIPERX3DATA12": "PCIE_PIPERX3DATA12", - "DRPDO1": "PCIE_DRPDO1", - "MIMTXWDATA62": "PCIE_MIMTXWDATA62", - "TRNTD82": "PCIE_TRNTD82", - "TRNTDLLPDATA18": "PCIE_TRNTDLLPDATA18", - "CFGDEVCONTROL2CPLTIMEOUTVAL3": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", - "TRNFCNPH2": "PCIE_TRNFCNPH2", - "CFGPMFORCESTATEENN": "PCIE_CFGPMFORCESTATEENN", - "MIMRXWADDR5": "PCIE_MIMRXWADDR5", - "MIMTXRDATA41": "PCIE_MIMTXRDATA41", - "CFGDSN26": "PCIE_CFGDSN26", - "MIMTXWDATA28": "PCIE_MIMTXWDATA28", - "CFGDEVSTATUSNONFATALERRDETECTED": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", - "CFGMGMTDI16": "PCIE_CFGMGMTDI16", - "PIPERX5CHARISK0": "PCIE_PIPERX5CHARISK0", - "DBGVECC11": "PCIE_DBGVECC11", - "CFGERRTLPCPLHEADER37": "PCIE_CFGERRTLPCPLHEADER37", - "CFGREVID4": "PCIE_CFGREVID4", - "TRNRDLLPDATA34": "PCIE_TRNRDLLPDATA34", - "MIMRXWDATA62": "PCIE_MIMRXWDATA62", - "MIMRXWADDR1": "PCIE_MIMRXWADDR1", - "MIMTXWDATA20": "PCIE_MIMTXWDATA20", - "DRPDI8": "PCIE_DRPDI8", - "MIMRXRDATA4": "PCIE_MIMRXRDATA4", - "PIPERX7DATA0": "PCIE_PIPERX7DATA0", - "PIPETX0DATA15": "PCIE_PIPETX0DATA15", - "DBGSCLRA": "PCIE_DBGSCLRA", - "CFGMSGDATA7": "PCIE_CFGMSGDATA7", - "CFGREVID2": "PCIE_CFGREVID2", - "DBGVECA57": "PCIE_DBGVECA57", - "CFGVENDID10": "PCIE_CFGVENDID10", - "PIPERX7STATUS2": "PCIE_PIPERX7STATUS2", - "CFGMGMTDO10": "PCIE_CFGMGMTDO10", - "PIPERX6DATA9": "PCIE_PIPERX6DATA9", - "MIMTXRDATA65": "PCIE_MIMTXRDATA65", - "MIMRXWDATA59": "PCIE_MIMRXWDATA59", - "CFGREVID0": "PCIE_CFGREVID0", - "TRNRD47": "PCIE_TRNRD47", - "TRNTSRCDSC": "PCIE_TRNTSRCDSC", - "PIPERX3DATA10": "PCIE_PIPERX3DATA10", - "CFGVENDID8": "PCIE_CFGVENDID8", - "TRNRDLLPDATA11": "PCIE_TRNRDLLPDATA11", - "MIMRXRDATA6": "PCIE_MIMRXRDATA6", - "CFGINTERRUPTDI6": "PCIE_CFGINTERRUPTDI6", - "PLDBGVEC0": "PCIE_PLDBGVEC0", - "MIMRXWDATA19": "PCIE_MIMRXWDATA19", - "TRNTD6": "PCIE_TRNTD6", - "PLLTSSMSTATE3": "PCIE_PLLTSSMSTATE3", - "TRNRD94": "PCIE_TRNRD94", - "DBGVECA43": "PCIE_DBGVECA43", - "TRNRDLLPSRCRDY1": "PCIE_TRNRDLLPSRCRDY1", - "CFGERRAERHEADERLOG88": "PCIE_CFGERRAERHEADERLOG88", - "CFGSUBSYSID1": "PCIE_CFGSUBSYSID1", - "XILUNCONNOUT3": "PCIE_XILUNCONNOUT3", - "PIPETX3COMPLIANCE": "PCIE_PIPETX3COMPLIANCE", - "TL2ERRHDR57": "PCIE_TL2ERRHDR57", - "PIPETX0POWERDOWN1": "PCIE_PIPETX0POWERDOWN1", - "TRNTD102": "PCIE_TRNTD102", - "MIMRXWDATA61": "PCIE_MIMRXWDATA61", - "TRNTBUFAV0": "PCIE_TRNTBUFAV0", - "PIPETX1DATA5": "PCIE_PIPETX1DATA5", - "TRNTD23": "PCIE_TRNTD23", - "CFGMSGDATA12": "PCIE_CFGMSGDATA12", - "TRNTD125": "PCIE_TRNTD125", - "TRNFCCPLH2": "PCIE_TRNFCCPLH2", - "MIMTXWDATA57": "PCIE_MIMTXWDATA57", - "XILUNCONNOUT15": "PCIE_XILUNCONNOUT15", - "TRNTCFGREQ": "PCIE_TRNTCFGREQ", - "PIPETX0DATA11": "PCIE_PIPETX0DATA11", - "DBGVECA5": "PCIE_DBGVECA5", - "PL2RXELECIDLE": "PCIE_PL2RXELECIDLE", - "CFGERRAERHEADERLOG74": "PCIE_CFGERRAERHEADERLOG74", - "CFGAERINTERRUPTMSGNUM3": "PCIE_CFGAERINTERRUPTMSGNUM3", - "CFGMGMTDO28": "PCIE_CFGMGMTDO28", - "DRPADDR6": "PCIE_DRPADDR6", - "TRNRD27": "PCIE_TRNRD27", - "CFGERRAERHEADERLOG83": "PCIE_CFGERRAERHEADERLOG83", - "CFGSUBSYSVENDID1": "PCIE_CFGSUBSYSVENDID1", - "MIMRXRDATA44": "PCIE_MIMRXRDATA44", - "MIMRXRDATA67": "PCIE_MIMRXRDATA67", - "MIMRXRDATA62": "PCIE_MIMRXRDATA62", - "PIPETX4DATA9": "PCIE_PIPETX4DATA9", - "MIMTXRDATA1": "PCIE_MIMTXRDATA1", - "MIMRXWDATA45": "PCIE_MIMRXWDATA45", - "TRNRD115": "PCIE_TRNRD115", - "CFGPMCSRPMESTATUS": "PCIE_CFGPMCSRPMESTATUS", - "CFGDSN43": "PCIE_CFGDSN43", - "CFGDSN42": "PCIE_CFGDSN42", - "PIPERX5VALID": "PCIE_PIPERX5VALID", - "TL2ERRHDR13": "PCIE_TL2ERRHDR13", - "PIPETX0DATA1": "PCIE_PIPETX0DATA1", - "MIMRXRDATA22": "PCIE_MIMRXRDATA22", - "MIMRXWDATA56": "PCIE_MIMRXWDATA56", - "CFGMGMTDI22": "PCIE_CFGMGMTDI22", - "PIPERX4STATUS0": "PCIE_PIPERX4STATUS0", - "DBGVECB52": "PCIE_DBGVECB52", - "CFGERRAERHEADERLOG66": "PCIE_CFGERRAERHEADERLOG66", - "DLRSTN": "PCIE_DLRSTN", - "CFGERRAERHEADERLOG102": "PCIE_CFGERRAERHEADERLOG102", - "TRNRD68": "PCIE_TRNRD68", - "CFGERRAERHEADERLOG57": "PCIE_CFGERRAERHEADERLOG57", - "PIPERX0DATA5": "PCIE_PIPERX0DATA5", - "MIMRXWDATA37": "PCIE_MIMRXWDATA37", - "CFGERRTLPCPLHEADER6": "PCIE_CFGERRTLPCPLHEADER6", - "CFGERRTLPCPLHEADER39": "PCIE_CFGERRTLPCPLHEADER39", - "CFGMGMTWRRW1CASRWN": "PCIE_CFGMGMTWRRW1CASRWN", - "TL2ERRHDR18": "PCIE_TL2ERRHDR18", - "PIPERX4DATA15": "PCIE_PIPERX4DATA15", - "PIPETX3CHARISK0": "PCIE_PIPETX3CHARISK0", - "CFGERRAERHEADERLOG94": "PCIE_CFGERRAERHEADERLOG94", - "CFGERRTLPCPLHEADER13": "PCIE_CFGERRTLPCPLHEADER13", - "CFGERRAERHEADERLOG121": "PCIE_CFGERRAERHEADERLOG121", - "PIPETX3DATA5": "PCIE_PIPETX3DATA5", - "CFGERRTLPCPLHEADER40": "PCIE_CFGERRTLPCPLHEADER40", - "CFGINTERRUPTDO3": "PCIE_CFGINTERRUPTDO3", - "PIPERX4DATA13": "PCIE_PIPERX4DATA13", - "TRNRDLLPDATA28": "PCIE_TRNRDLLPDATA28", - "PIPERX1VALID": "PCIE_PIPERX1VALID", - "DBGSCLRB": "PCIE_DBGSCLRB", - "CFGMSGRECEIVEDERRFATAL": "PCIE_CFGMSGRECEIVEDERRFATAL", - "PIPERX1DATA15": "PCIE_PIPERX1DATA15", - "TRNFCNPD0": "PCIE_TRNFCNPD0", - "PIPECLK": "PCIE_PIPECLK", - "PIPETX1DATA6": "PCIE_PIPETX1DATA6", - "CFGERRTLPCPLHEADER27": "PCIE_CFGERRTLPCPLHEADER27", - "MIMRXRDATA59": "PCIE_MIMRXRDATA59", - "DBGVECA56": "PCIE_DBGVECA56", - "TRNRD86": "PCIE_TRNRD86", - "PLDIRECTEDCHANGEDONE": "PCIE_PLDIRECTEDCHANGEDONE", - "PIPERX6DATA8": "PCIE_PIPERX6DATA8", - "CFGMGMTDO8": "PCIE_CFGMGMTDO8", - "CFGPCIELINKSTATE2": "PCIE_CFGPCIELINKSTATE2", - "SCANENABLEN": "PCIE_SCANENABLEN", - "MIMRXRDATA8": "PCIE_MIMRXRDATA8", - "DBGSCLRH": "PCIE_DBGSCLRH", - "MIMTXWDATA4": "PCIE_MIMTXWDATA4", - "XILUNCONNOUT28": "PCIE_XILUNCONNOUT28", - "CFGMGMTDO16": "PCIE_CFGMGMTDO16", - "MIMTXRDATA54": "PCIE_MIMTXRDATA54", - "MIMRXWDATA11": "PCIE_MIMRXWDATA11", - "TRNRD89": "PCIE_TRNRD89", - "CFGDEVID3": "PCIE_CFGDEVID3", - "TL2ERRHDR58": "PCIE_TL2ERRHDR58", - "PIPETX0DATA5": "PCIE_PIPETX0DATA5", - "DBGVECB14": "PCIE_DBGVECB14", - "TRNFCPD7": "PCIE_TRNFCPD7", - "TRNFCCPLD10": "PCIE_TRNFCCPLD10", - "DBGSCLRK": "PCIE_DBGSCLRK", - "DBGSCLRC": "PCIE_DBGSCLRC", - "CFGERRTLPCPLHEADER43": "PCIE_CFGERRTLPCPLHEADER43", - "TRNTD78": "PCIE_TRNTD78", - "TRNTDLLPDATA8": "PCIE_TRNTDLLPDATA8", - "TRNTD69": "PCIE_TRNTD69", - "CFGDEVCONTROLENABLERO": "PCIE_CFGDEVCONTROLENABLERO", - "PLTXPMSTATE2": "PCIE_PLTXPMSTATE2", - "CFGDEVCONTROLAUXPOWEREN": "PCIE_CFGDEVCONTROLAUXPOWEREN", - "DRPDI5": "PCIE_DRPDI5", - "MIMTXWDATA31": "PCIE_MIMTXWDATA31", - "CFGMGMTDO4": "PCIE_CFGMGMTDO4", - "PIPERX2DATA12": "PCIE_PIPERX2DATA12", - "TRNRD52": "PCIE_TRNRD52", - "CFGDEVID15": "PCIE_CFGDEVID15", - "XILUNCONNOUT7": "PCIE_XILUNCONNOUT7", - "CFGSUBSYSID5": "PCIE_CFGSUBSYSID5", - "CFGAERROOTERRFATALERRRECEIVED": "PCIE_CFGAERROOTERRFATALERRRECEIVED", - "CFGSUBSYSID9": "PCIE_CFGSUBSYSID9", - "USERRSTN": "PCIE_USERRSTN", - "CFGERRAERHEADERLOG105": "PCIE_CFGERRAERHEADERLOG105", - "LL2SENDENTERL1": "PCIE_LL2SENDENTERL1", - "TRNTD29": "PCIE_TRNTD29", - "PIPETX1DATA12": "PCIE_PIPETX1DATA12", - "TL2ERRHDR6": "PCIE_TL2ERRHDR6", - "TRNRD88": "PCIE_TRNRD88", - "DRPDI11": "PCIE_DRPDI11", - "TRNTD33": "PCIE_TRNTD33", - "TL2ERRHDR37": "PCIE_TL2ERRHDR37", - "MIMTXWADDR1": "PCIE_MIMTXWADDR1", - "CFGERRAERHEADERLOG39": "PCIE_CFGERRAERHEADERLOG39", - "TRNTD26": "PCIE_TRNTD26", - "CFGDSDEVICENUMBER0": "PCIE_CFGDSDEVICENUMBER0", - "DBGMODE0": "PCIE_DBGMODE0", - "MIMTXRDATA30": "PCIE_MIMTXRDATA30", - "TL2ERRHDR32": "PCIE_TL2ERRHDR32", - "TL2ERRHDR0": "PCIE_TL2ERRHDR0", - "DBGVECB25": "PCIE_DBGVECB25", - "TRNTD109": "PCIE_TRNTD109", - "TRNRD67": "PCIE_TRNRD67", - "CFGLINKCONTROLASPMCONTROL1": "PCIE_CFGLINKCONTROLASPMCONTROL1", - "PIPERX2DATA13": "PCIE_PIPERX2DATA13", - "TRNTSRCRDY": "PCIE_TRNTSRCRDY", - "XILUNCONNOUT2": "PCIE_XILUNCONNOUT2", - "DBGVECB11": "PCIE_DBGVECB11", - "MIMRXRDATA10": "PCIE_MIMRXRDATA10", - "CFGERRAERHEADERLOG71": "PCIE_CFGERRAERHEADERLOG71", - "MIMRXRDATA56": "PCIE_MIMRXRDATA56", - "CFGMGMTDI21": "PCIE_CFGMGMTDI21", - "CFGINTERRUPTSTATN": "PCIE_CFGINTERRUPTSTATN", - "TRNRD23": "PCIE_TRNRD23", - "CFGREVID1": "PCIE_CFGREVID1", - "DRPADDR7": "PCIE_DRPADDR7", - "TRNRDLLPDATA32": "PCIE_TRNRDLLPDATA32", - "CFGVENDID7": "PCIE_CFGVENDID7", - "PIPERX4DATA9": "PCIE_PIPERX4DATA9", - "TRNTBUFAV3": "PCIE_TRNTBUFAV3", - "PIPETX0DATA13": "PCIE_PIPETX0DATA13", - "TL2ERRHDR15": "PCIE_TL2ERRHDR15", - "XILUNCONNOUT26": "PCIE_XILUNCONNOUT26", - "DBGVECB10": "PCIE_DBGVECB10", - "CFGDSN47": "PCIE_CFGDSN47", - "CFGMGMTBYTEENN2": "PCIE_CFGMGMTBYTEENN2", - "TL2ERRFCPE": "PCIE_TL2ERRFCPE", - "MIMTXWDATA40": "PCIE_MIMTXWDATA40", - "MIMTXRDATA13": "PCIE_MIMTXRDATA13", - "CFGINTERRUPTDO6": "PCIE_CFGINTERRUPTDO6", - "CFGINTERRUPTDO5": "PCIE_CFGINTERRUPTDO5", - "CFGERRAERHEADERLOG82": "PCIE_CFGERRAERHEADERLOG82", - "TRNRBARHIT4": "PCIE_TRNRBARHIT4", - "PIPERX3DATA6": "PCIE_PIPERX3DATA6", - "TRNRD42": "PCIE_TRNRD42", - "PIPETX4DATA10": "PCIE_PIPETX4DATA10", - "PIPETX0DATA12": "PCIE_PIPETX0DATA12", - "TRNFCCPLD9": "PCIE_TRNFCCPLD9", - "DBGVECB45": "PCIE_DBGVECB45", - "MIMTXWDATA25": "PCIE_MIMTXWDATA25", - "PIPERX1DATA2": "PCIE_PIPERX1DATA2", - "TRNTD32": "PCIE_TRNTD32", - "CFGERRAERHEADERLOG124": "PCIE_CFGERRAERHEADERLOG124", - "TRNTDLLPDATA31": "PCIE_TRNTDLLPDATA31", - "TRNFCPH0": "PCIE_TRNFCPH0", - "CFGSUBSYSID8": "PCIE_CFGSUBSYSID8", - "CFGSUBSYSID15": "PCIE_CFGSUBSYSID15", - "PMVSELECT0": "PCIE_PMVSELECT0", - "CFGDSN35": "PCIE_CFGDSN35", - "CFGPORTNUMBER6": "PCIE_CFGPORTNUMBER6", - "PIPERX7DATA7": "PCIE_PIPERX7DATA7", - "CFGDEVCONTROLMAXPAYLOAD1": "PCIE_CFGDEVCONTROLMAXPAYLOAD1", - "TRNTD14": "PCIE_TRNTD14", - "TRNTD39": "PCIE_TRNTD39", - "PIPERX5DATA9": "PCIE_PIPERX5DATA9", - "DBGVECB16": "PCIE_DBGVECB16", - "PIPERX3DATA15": "PCIE_PIPERX3DATA15", - "CFGERRAERHEADERLOG95": "PCIE_CFGERRAERHEADERLOG95", - "TRNRD53": "PCIE_TRNRD53", - "DBGVECB56": "PCIE_DBGVECB56", - "PIPETX4POWERDOWN0": "PCIE_PIPETX4POWERDOWN0", - "CFGDSN24": "PCIE_CFGDSN24", - "PIPERX1CHANISALIGNED": "PCIE_PIPERX1CHANISALIGNED", - "CFGPORTNUMBER0": "PCIE_CFGPORTNUMBER0", - "TRNTD96": "PCIE_TRNTD96", - "CFGINTERRUPTDO7": "PCIE_CFGINTERRUPTDO7", - "LL2TFCINIT2SEQ": "PCIE_LL2TFCINIT2SEQ", - "MIMTXRDATA18": "PCIE_MIMTXRDATA18", - "TRNTD100": "PCIE_TRNTD100", - "CFGMGMTWRREADONLYN": "PCIE_CFGMGMTWRREADONLYN", - "MIMRXRDATA13": "PCIE_MIMRXRDATA13", - "CFGFORCEMPS2": "PCIE_CFGFORCEMPS2", - "CFGDSN57": "PCIE_CFGDSN57", - "TRNRDLLPDATA48": "PCIE_TRNRDLLPDATA48", - "CFGERRTLPCPLHEADER4": "PCIE_CFGERRTLPCPLHEADER4", - "CFGMGMTDI6": "PCIE_CFGMGMTDI6", - "PLSELLNKWIDTH1": "PCIE_PLSELLNKWIDTH1", - "TRNTDLLPDATA28": "PCIE_TRNTDLLPDATA28", - "TL2ERRHDR10": "PCIE_TL2ERRHDR10", - "TRNFCCPLH0": "PCIE_TRNFCCPLH0", - "CFGDSBUSNUMBER4": "PCIE_CFGDSBUSNUMBER4", - "PIPERX7PHYSTATUS": "PCIE_PIPERX7PHYSTATUS", - "TRNTD49": "PCIE_TRNTD49", - "TRNFCCPLD4": "PCIE_TRNFCCPLD4", - "TRNTD126": "PCIE_TRNTD126", - "PIPETX3DATA7": "PCIE_PIPETX3DATA7", - "CFGERRAERHEADERLOG37": "PCIE_CFGERRAERHEADERLOG37", - "PIPETX6ELECIDLE": "PCIE_PIPETX6ELECIDLE", - "PIPERX7DATA11": "PCIE_PIPERX7DATA11", - "CFGERRAERHEADERLOG118": "PCIE_CFGERRAERHEADERLOG118", - "MIMTXWDATA0": "PCIE_MIMTXWDATA0", - "CFGMGMTDI28": "PCIE_CFGMGMTDI28", - "TRNTDLLPDATA22": "PCIE_TRNTDLLPDATA22", - "MIMRXWDATA53": "PCIE_MIMRXWDATA53", - "DBGVECB61": "PCIE_DBGVECB61", - "TRNFCPD9": "PCIE_TRNFCPD9", - "PIPETX5DATA7": "PCIE_PIPETX5DATA7", - "CFGERRTLPCPLHEADER16": "PCIE_CFGERRTLPCPLHEADER16", - "TRNRD9": "PCIE_TRNRD9", - "MIMTXRADDR1": "PCIE_MIMTXRADDR1", - "CFGMGMTDI11": "PCIE_CFGMGMTDI11", - "CFGPCIECAPINTERRUPTMSGNUM3": "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", - "PIPERX2DATA1": "PCIE_PIPERX2DATA1", - "MIMRXRDATA24": "PCIE_MIMRXRDATA24", - "TRNRDLLPDATA35": "PCIE_TRNRDLLPDATA35", - "CFGERRAERHEADERLOG61": "PCIE_CFGERRAERHEADERLOG61", - "PIPETX3DATA14": "PCIE_PIPETX3DATA14", - "DRPDI10": "PCIE_DRPDI10", - "TL2ASPMSUSPENDCREDITCHECK": "PCIE_TL2ASPMSUSPENDCREDITCHECK", - "CFGDSN8": "PCIE_CFGDSN8", - "PLRXPMSTATE0": "PCIE_PLRXPMSTATE0", - "DBGVECA33": "PCIE_DBGVECA33", - "PIPERX4DATA11": "PCIE_PIPERX4DATA11", - "CFGMGMTDI4": "PCIE_CFGMGMTDI4", - "PIPETX3DATA12": "PCIE_PIPETX3DATA12", - "CFGDEVCONTROL2IDOREQEN": "PCIE_CFGDEVCONTROL2IDOREQEN", - "PIPETX1COMPLIANCE": "PCIE_PIPETX1COMPLIANCE", - "CFGDEVCONTROLMAXREADREQ1": "PCIE_CFGDEVCONTROLMAXREADREQ1", - "TRNRDLLPDATA57": "PCIE_TRNRDLLPDATA57", - "CFGMSGDATA6": "PCIE_CFGMSGDATA6", - "DBGVECC3": "PCIE_DBGVECC3", - "MIMRXWDATA17": "PCIE_MIMRXWDATA17", - "DBGVECA34": "PCIE_DBGVECA34", - "DBGVECA32": "PCIE_DBGVECA32", - "TRNRD50": "PCIE_TRNRD50", - "XILUNCONNOUT31": "PCIE_XILUNCONNOUT31", - "PIPETX4DATA11": "PCIE_PIPETX4DATA11", - "DBGVECB38": "PCIE_DBGVECB38", - "CFGERRAERHEADERLOG27": "PCIE_CFGERRAERHEADERLOG27", - "MIMRXWADDR0": "PCIE_MIMRXWADDR0", - "CFGDSN25": "PCIE_CFGDSN25", - "MIMRXWDATA22": "PCIE_MIMRXWDATA22", - "TL2ERRHDR40": "PCIE_TL2ERRHDR40", - "CFGERRAERHEADERLOG32": "PCIE_CFGERRAERHEADERLOG32", - "DBGVECA58": "PCIE_DBGVECA58", - "MIMTXWDATA29": "PCIE_MIMTXWDATA29", - "TRNRBARHIT2": "PCIE_TRNRBARHIT2", - "PIPERX6DATA12": "PCIE_PIPERX6DATA12", - "PIPETX0ELECIDLE": "PCIE_PIPETX0ELECIDLE", - "PIPERX0VALID": "PCIE_PIPERX0VALID", - "PLDBGMODE2": "PCIE_PLDBGMODE2", - "PL2LINKUP": "PCIE_PL2LINKUP", - "DBGVECB15": "PCIE_DBGVECB15", - "DBGVECB44": "PCIE_DBGVECB44", - "TRNTD115": "PCIE_TRNTD115", - "MIMTXRDATA49": "PCIE_MIMTXRDATA49", - "TRNFCNPH5": "PCIE_TRNFCNPH5", - "SYSRSTN": "PCIE_SYSRSTN", - "CFGERRAERHEADERLOG53": "PCIE_CFGERRAERHEADERLOG53", - "CFGPMHALTASPML0SN": "PCIE_CFGPMHALTASPML0SN", - "DBGVECB22": "PCIE_DBGVECB22", - "MIMTXWDATA43": "PCIE_MIMTXWDATA43", - "PIPETX3DATA10": "PCIE_PIPETX3DATA10", - "PIPERX7DATA8": "PCIE_PIPERX7DATA8", - "MIMTXWDATA60": "PCIE_MIMTXWDATA60", - "MIMTXWDATA54": "PCIE_MIMTXWDATA54", - "CFGERRAERHEADERLOG10": "PCIE_CFGERRAERHEADERLOG10", - "CFGMGMTDO30": "PCIE_CFGMGMTDO30", - "PIPERX5DATA13": "PCIE_PIPERX5DATA13", - "PIPETX3DATA3": "PCIE_PIPETX3DATA3", - "PLDIRECTEDLINKAUTON": "PCIE_PLDIRECTEDLINKAUTON", - "CFGVCTCVCMAP0": "PCIE_CFGVCTCVCMAP0", - "TRNRDLLPDATA22": "PCIE_TRNRDLLPDATA22", - "TRNTD18": "PCIE_TRNTD18", - "PIPERX3DATA14": "PCIE_PIPERX3DATA14", - "PIPERX6VALID": "PCIE_PIPERX6VALID", - "MIMTXRDATA63": "PCIE_MIMTXRDATA63", - "CFGMSGDATA14": "PCIE_CFGMSGDATA14", - "PIPERX3CHANISALIGNED": "PCIE_PIPERX3CHANISALIGNED", - "TRNRD40": "PCIE_TRNRD40", - "CFGERRAERHEADERLOG114": "PCIE_CFGERRAERHEADERLOG114", - "DRPDO10": "PCIE_DRPDO10", - "TRNTD74": "PCIE_TRNTD74", - "TRNTD88": "PCIE_TRNTD88", - "CFGTRANSACTIONADDR3": "PCIE_CFGTRANSACTIONADDR3", - "DBGVECB55": "PCIE_DBGVECB55", - "PIPETX0DATA7": "PCIE_PIPETX0DATA7", - "PIPETX7DATA14": "PCIE_PIPETX7DATA14", - "DBGSCLRD": "PCIE_DBGSCLRD", - "MIMTXRDATA14": "PCIE_MIMTXRDATA14", - "TRNRDLLPDATA54": "PCIE_TRNRDLLPDATA54", - "MIMTXRDATA6": "PCIE_MIMTXRDATA6", - "MIMTXWDATA1": "PCIE_MIMTXWDATA1", - "TRNRDLLPDATA26": "PCIE_TRNRDLLPDATA26", - "PIPERX1DATA0": "PCIE_PIPERX1DATA0", - "PL2SUSPENDOK": "PCIE_PL2SUSPENDOK", - "DBGVECB40": "PCIE_DBGVECB40", - "MIMRXRDATA12": "PCIE_MIMRXRDATA12", - "TRNRDLLPDATA37": "PCIE_TRNRDLLPDATA37", - "CFGVENDID1": "PCIE_CFGVENDID1", - "MIMRXRADDR8": "PCIE_MIMRXRADDR8", - "EDTCHANNELSOUT7": "PCIE_EDTCHANNELSOUT7", - "PIPETX2DATA10": "PCIE_PIPETX2DATA10", - "PIPETX4DATA12": "PCIE_PIPETX4DATA12", - "TRNTD25": "PCIE_TRNTD25", - "MIMTXRDATA46": "PCIE_MIMTXRDATA46", - "DBGVECA40": "PCIE_DBGVECA40", - "CFGMGMTDI5": "PCIE_CFGMGMTDI5", - "PL2RXPMSTATE0": "PCIE_PL2RXPMSTATE0", - "TRNFCCPLH4": "PCIE_TRNFCCPLH4", - "TRNTD114": "PCIE_TRNTD114", - "CFGSUBSYSID7": "PCIE_CFGSUBSYSID7", - "TRNTDLLPDATA23": "PCIE_TRNTDLLPDATA23", - "XILUNCONNOUT21": "PCIE_XILUNCONNOUT21", - "DBGVECA38": "PCIE_DBGVECA38", - "DBGVECA50": "PCIE_DBGVECA50", - "MIMRXRDATA5": "PCIE_MIMRXRDATA5", - "TRNRD75": "PCIE_TRNRD75", - "CFGERRTLPCPLHEADER5": "PCIE_CFGERRTLPCPLHEADER5", - "PIPETX6DATA1": "PCIE_PIPETX6DATA1", - "CFGERRTLPCPLHEADER26": "PCIE_CFGERRTLPCPLHEADER26", - "DBGVECB62": "PCIE_DBGVECB62", - "CFGMGMTDO24": "PCIE_CFGMGMTDO24", - "PIPERX3DATA2": "PCIE_PIPERX3DATA2", - "DBGVECC6": "PCIE_DBGVECC6", - "TL2ERRHDR1": "PCIE_TL2ERRHDR1", - "CFGERRAERHEADERLOG85": "PCIE_CFGERRAERHEADERLOG85", - "MIMRXRDATA50": "PCIE_MIMRXRDATA50", - "PIPETX1DATA9": "PCIE_PIPETX1DATA9", - "CFGMSGRECEIVEDASSERTINTA": "PCIE_CFGMSGRECEIVEDASSERTINTA", - "DRPDO13": "PCIE_DRPDO13", - "TRNRD100": "PCIE_TRNRD100", - "PIPETX5DATA1": "PCIE_PIPETX5DATA1", - "TRNRBARHIT7": "PCIE_TRNRBARHIT7", - "FUNCLVLRSTN": "PCIE_FUNCLVLRSTN", - "TL2ERRHDR46": "PCIE_TL2ERRHDR46", - "CFGERRTLPCPLHEADER11": "PCIE_CFGERRTLPCPLHEADER11", - "PIPERX1DATA4": "PCIE_PIPERX1DATA4", - "CFGMGMTDO7": "PCIE_CFGMGMTDO7", - "PIPERX1DATA1": "PCIE_PIPERX1DATA1", - "CFGERRAERHEADERLOG113": "PCIE_CFGERRAERHEADERLOG113", - "CFGERRAERHEADERLOG110": "PCIE_CFGERRAERHEADERLOG110", - "XILUNCONNOUT6": "PCIE_XILUNCONNOUT6", - "TRNTD106": "PCIE_TRNTD106", - "TL2ERRHDR45": "PCIE_TL2ERRHDR45", - "PLDIRECTEDLINKWIDTH0": "PCIE_PLDIRECTEDLINKWIDTH0", - "DBGVECA6": "PCIE_DBGVECA6", - "PIPETX0COMPLIANCE": "PCIE_PIPETX0COMPLIANCE", - "MIMTXRDATA37": "PCIE_MIMTXRDATA37", - "TRNTD119": "PCIE_TRNTD119", - "TRNRDLLPDATA17": "PCIE_TRNRDLLPDATA17", - "DBGVECA10": "PCIE_DBGVECA10", - "CFGVCTCVCMAP4": "PCIE_CFGVCTCVCMAP4", - "LL2BADTLPERR": "PCIE_LL2BADTLPERR", - "XILUNCONNOUT29": "PCIE_XILUNCONNOUT29", - "MIMRXRDATA64": "PCIE_MIMRXRDATA64", - "DBGVECA24": "PCIE_DBGVECA24", - "PIPETX6CHARISK0": "PCIE_PIPETX6CHARISK0", - "PIPERX6CHARISK0": "PCIE_PIPERX6CHARISK0", - "TL2ERRHDR36": "PCIE_TL2ERRHDR36", - "PIPERX6STATUS0": "PCIE_PIPERX6STATUS0", - "MIMTXWDATA17": "PCIE_MIMTXWDATA17", - "TRNTDLLPSRCRDY": "PCIE_TRNTDLLPSRCRDY", - "PIPERX5CHARISK1": "PCIE_PIPERX5CHARISK1", - "PLDBGMODE0": "PCIE_PLDBGMODE0", - "DBGVECB43": "PCIE_DBGVECB43", - "PIPETXRCVRDET": "PCIE_PIPETXRCVRDET", - "PMVOUT": "PCIE_PMVOUT", - "MIMRXRDATA52": "PCIE_MIMRXRDATA52", - "MIMRXWDATA49": "PCIE_MIMRXWDATA49", - "CFGVENDID13": "PCIE_CFGVENDID13", - "PIPETX2DATA9": "PCIE_PIPETX2DATA9", - "TRNFCPD1": "PCIE_TRNFCPD1", - "TRNTD62": "PCIE_TRNTD62", - "PIPETX2DATA0": "PCIE_PIPETX2DATA0", - "PIPERX2POLARITY": "PCIE_PIPERX2POLARITY", - "TRNFCCPLD3": "PCIE_TRNFCCPLD3", - "TRNRD114": "PCIE_TRNRD114", - "CFGMGMTDO21": "PCIE_CFGMGMTDO21", - "CFGDSN33": "PCIE_CFGDSN33", - "TRNFCNPH3": "PCIE_TRNFCNPH3", - "RECEIVEDFUNCLVLRSTN": "PCIE_RECEIVEDFUNCLVLRSTN", - "PIPERX0DATA0": "PCIE_PIPERX0DATA0", - "MIMRXWDATA20": "PCIE_MIMRXWDATA20", - "PIPERX5DATA2": "PCIE_PIPERX5DATA2", - "MIMRXWDATA60": "PCIE_MIMRXWDATA60", - "MIMTXRDATA51": "PCIE_MIMTXRDATA51", - "TRNRDLLPDATA14": "PCIE_TRNRDLLPDATA14", - "MIMRXWDATA10": "PCIE_MIMRXWDATA10", - "PIPETX1POWERDOWN1": "PCIE_PIPETX1POWERDOWN1", - "MIMTXRDATA20": "PCIE_MIMTXRDATA20", - "PIPETX4POWERDOWN1": "PCIE_PIPETX4POWERDOWN1", - "TRNTD10": "PCIE_TRNTD10", - "DBGVECA30": "PCIE_DBGVECA30", - "DRPDI12": "PCIE_DRPDI12", - "SCANMODEN": "PCIE_SCANMODEN", - "TRNRD36": "PCIE_TRNRD36", - "MIMRXWDATA29": "PCIE_MIMRXWDATA29", - "TRNRDLLPDATA21": "PCIE_TRNRDLLPDATA21", - "MIMRXRDATA11": "PCIE_MIMRXRDATA11", - "TRNFCPD5": "PCIE_TRNFCPD5", - "DBGVECA27": "PCIE_DBGVECA27", - "CFGERRAERHEADERLOG63": "PCIE_CFGERRAERHEADERLOG63", - "LL2SENDENTERL23": "PCIE_LL2SENDENTERL23", - "PIPETX1CHARISK1": "PCIE_PIPETX1CHARISK1", - "DBGVECA36": "PCIE_DBGVECA36", - "PIPETX2CHARISK1": "PCIE_PIPETX2CHARISK1", - "MIMTXRADDR2": "PCIE_MIMTXRADDR2", - "MIMTXWDATA41": "PCIE_MIMTXWDATA41", - "CFGVCTCVCMAP5": "PCIE_CFGVCTCVCMAP5", - "CFGERRAERHEADERLOG68": "PCIE_CFGERRAERHEADERLOG68", - "PIPETX7DATA0": "PCIE_PIPETX7DATA0", - "TL2ERRHDR53": "PCIE_TL2ERRHDR53", - "PIPERX5DATA4": "PCIE_PIPERX5DATA4", - "USERCLK2": "PCIE_USERCLK2", - "PIPETX2ELECIDLE": "PCIE_PIPETX2ELECIDLE", - "DRPDO6": "PCIE_DRPDO6", - "DBGVECA16": "PCIE_DBGVECA16", - "PIPERX7DATA5": "PCIE_PIPERX7DATA5", - "CFGSUBSYSVENDID2": "PCIE_CFGSUBSYSVENDID2", - "PIPERX2DATA0": "PCIE_PIPERX2DATA0", - "TRNTD45": "PCIE_TRNTD45", - "CFGMGMTDO31": "PCIE_CFGMGMTDO31", - "MIMRXRDATA29": "PCIE_MIMRXRDATA29", - "PIPERX6STATUS1": "PCIE_PIPERX6STATUS1", - "TRNTDLLPDATA14": "PCIE_TRNTDLLPDATA14", - "MIMRXWEN": "PCIE_MIMRXWEN", - "PIPETX6DATA12": "PCIE_PIPETX6DATA12", - "TRNTBUFAV4": "PCIE_TRNTBUFAV4", - "MIMRXWDATA43": "PCIE_MIMRXWDATA43", - "PIPERX1STATUS2": "PCIE_PIPERX1STATUS2", - "CFGDSN2": "PCIE_CFGDSN2", - "CFGMGMTDI27": "PCIE_CFGMGMTDI27", - "PIPETX5DATA12": "PCIE_PIPETX5DATA12", - "TRNRDLLPDATA55": "PCIE_TRNRDLLPDATA55", - "EDTCHANNELSOUT8": "PCIE_EDTCHANNELSOUT8", - "PIPETX0DATA10": "PCIE_PIPETX0DATA10", - "PL2DIRECTEDLSTATE3": "PCIE_PL2DIRECTEDLSTATE3", - "CFGDSN62": "PCIE_CFGDSN62", - "MIMTXWADDR0": "PCIE_MIMTXWADDR0", - "PIPETX7DATA3": "PCIE_PIPETX7DATA3", - "PIPETX7POWERDOWN0": "PCIE_PIPETX7POWERDOWN0", - "DBGVECB13": "PCIE_DBGVECB13", - "CFGERRMALFORMEDN": "PCIE_CFGERRMALFORMEDN", - "DBGVECA12": "PCIE_DBGVECA12", - "PLDIRECTEDLTSSMNEW4": "PCIE_PLDIRECTEDLTSSMNEW4", - "XILUNCONNOUT14": "PCIE_XILUNCONNOUT14", - "TRNRDLLPDATA30": "PCIE_TRNRDLLPDATA30", - "CFGDEVCONTROL2ATOMICREQUESTEREN": "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", - "TRNRDLLPDATA16": "PCIE_TRNRDLLPDATA16", - "DBGVECB26": "PCIE_DBGVECB26", - "DBGVECC5": "PCIE_DBGVECC5", - "PLUPSTREAMPREFERDEEMPH": "PCIE_PLUPSTREAMPREFERDEEMPH", - "TRNTD79": "PCIE_TRNTD79", - "PIPERX4DATA1": "PCIE_PIPERX4DATA1", - "CFGERRTLPCPLHEADER23": "PCIE_CFGERRTLPCPLHEADER23", - "CFGMGMTBYTEENN1": "PCIE_CFGMGMTBYTEENN1", - "DBGVECB51": "PCIE_DBGVECB51", - "DBGVECA28": "PCIE_DBGVECA28", - "CFGMGMTDO5": "PCIE_CFGMGMTDO5", - "PIPERX0DATA2": "PCIE_PIPERX0DATA2", - "TRNTD37": "PCIE_TRNTD37", - "TRNRDLLPDATA24": "PCIE_TRNRDLLPDATA24", - "PIPERX2DATA7": "PCIE_PIPERX2DATA7", - "CFGMGMTDO23": "PCIE_CFGMGMTDO23", - "CFGDSN29": "PCIE_CFGDSN29", - "MIMRXWDATA55": "PCIE_MIMRXWDATA55", - "MIMTXRDATA34": "PCIE_MIMTXRDATA34", - "MIMTXRDATA25": "PCIE_MIMTXRDATA25", - "MIMTXRDATA15": "PCIE_MIMTXRDATA15", - "XILUNCONNOUT1": "PCIE_XILUNCONNOUT1", - "TRNRD124": "PCIE_TRNRD124", - "DBGVECA41": "PCIE_DBGVECA41", - "TRNTDLLPDATA1": "PCIE_TRNTDLLPDATA1", - "TRNFCNPH7": "PCIE_TRNFCNPH7", - "TRNRDSTRDY": "PCIE_TRNRDSTRDY", - "CFGERRPOISONEDN": "PCIE_CFGERRPOISONEDN", - "PLDIRECTEDLTSSMNEW2": "PCIE_PLDIRECTEDLTSSMNEW2", - "PIPETX3DATA13": "PCIE_PIPETX3DATA13", - "TRNRD49": "PCIE_TRNRD49", - "TRNTDLLPDATA6": "PCIE_TRNTDLLPDATA6", - "DBGVECB21": "PCIE_DBGVECB21", - "TRNTDLLPDATA25": "PCIE_TRNTDLLPDATA25", - "PLDBGVEC9": "PCIE_PLDBGVEC9", - "XILUNCONNOUT22": "PCIE_XILUNCONNOUT22", - "PLRSTN": "PCIE_PLRSTN", - "MIMRXWDATA50": "PCIE_MIMRXWDATA50", - "TRNTD110": "PCIE_TRNTD110", - "DBGSCLRJ": "PCIE_DBGSCLRJ", - "TRNTDLLPDATA27": "PCIE_TRNTDLLPDATA27", - "TRNTD51": "PCIE_TRNTD51", - "CFGERRAERHEADERLOG1": "PCIE_CFGERRAERHEADERLOG1", - "PIPETX7DATA8": "PCIE_PIPETX7DATA8", - "TRNTD91": "PCIE_TRNTD91", - "CFGMGMTDWADDR0": "PCIE_CFGMGMTDWADDR0", - "MIMRXWDATA30": "PCIE_MIMRXWDATA30", - "CFGAERINTERRUPTMSGNUM0": "PCIE_CFGAERINTERRUPTMSGNUM0", - "PIPERX5DATA10": "PCIE_PIPERX5DATA10", - "PIPERX4VALID": "PCIE_PIPERX4VALID", - "TRNRD61": "PCIE_TRNRD61", - "TL2ERRHDR29": "PCIE_TL2ERRHDR29", - "DRPDI13": "PCIE_DRPDI13", - "CFGLINKCONTROLRETRAINLINK": "PCIE_CFGLINKCONTROLRETRAINLINK", - "TL2ERRHDR2": "PCIE_TL2ERRHDR2", - "CFGPMRCVENTERL23N": "PCIE_CFGPMRCVENTERL23N", - "CFGERRAERHEADERLOG7": "PCIE_CFGERRAERHEADERLOG7", - "PIPERX4CHARISK0": "PCIE_PIPERX4CHARISK0", - "TRNRDLLPDATA50": "PCIE_TRNRDLLPDATA50", - "CFGMSGDATA2": "PCIE_CFGMSGDATA2", - "CFGDEVCONTROL2CPLTIMEOUTVAL0": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", - "MIMRXWDATA32": "PCIE_MIMRXWDATA32", - "CFGERRAERHEADERLOG59": "PCIE_CFGERRAERHEADERLOG59", - "MIMTXRDATA33": "PCIE_MIMTXRDATA33", - "PIPERX4DATA3": "PCIE_PIPERX4DATA3", - "PIPERX3STATUS1": "PCIE_PIPERX3STATUS1", - "DBGVECB4": "PCIE_DBGVECB4", - "MIMRXRDATA39": "PCIE_MIMRXRDATA39", - "MIMTXWDATA59": "PCIE_MIMTXWDATA59", - "DBGVECB6": "PCIE_DBGVECB6", - "PIPERX0DATA8": "PCIE_PIPERX0DATA8", - "TRNTD9": "PCIE_TRNTD9", - "DBGVECB3": "PCIE_DBGVECB3", - "TL2ERRHDR42": "PCIE_TL2ERRHDR42", - "PLLANEREVERSALMODE1": "PCIE_PLLANEREVERSALMODE1", - "TRNRD21": "PCIE_TRNRD21", - "TRNRDLLPDATA46": "PCIE_TRNRDLLPDATA46", - "CFGLINKSTATUSAUTOBANDWIDTHSTATUS": "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", - "CFGMGMTDO0": "PCIE_CFGMGMTDO0", - "MIMTXWDATA66": "PCIE_MIMTXWDATA66", - "PLLTSSMSTATE4": "PCIE_PLLTSSMSTATE4", - "TRNRD65": "PCIE_TRNRD65", - "CFGAERINTERRUPTMSGNUM2": "PCIE_CFGAERINTERRUPTMSGNUM2", - "MIMTXRDATA29": "PCIE_MIMTXRDATA29", - "TRNFCPD4": "PCIE_TRNFCPD4", - "TRNRD1": "PCIE_TRNRD1", - "TRNRD85": "PCIE_TRNRD85", - "DBGVECA20": "PCIE_DBGVECA20", - "DBGVECB31": "PCIE_DBGVECB31", - "MIMTXWDATA6": "PCIE_MIMTXWDATA6", - "CFGERRAERHEADERLOG43": "PCIE_CFGERRAERHEADERLOG43", - "CFGERRAERHEADERLOG126": "PCIE_CFGERRAERHEADERLOG126", - "CFGMSGRECEIVED": "PCIE_CFGMSGRECEIVED", - "PIPETX7DATA6": "PCIE_PIPETX7DATA6", - "PIPETX1DATA7": "PCIE_PIPETX1DATA7", - "MIMRXRDATA51": "PCIE_MIMRXRDATA51", - "PIPETX7COMPLIANCE": "PCIE_PIPETX7COMPLIANCE", - "CFGERRAERHEADERLOG79": "PCIE_CFGERRAERHEADERLOG79", - "CFGMSGDATA10": "PCIE_CFGMSGDATA10", - "PIPERX2VALID": "PCIE_PIPERX2VALID", - "PIPERX7DATA1": "PCIE_PIPERX7DATA1", - "PIPERX6DATA10": "PCIE_PIPERX6DATA10", - "CFGMGMTDI25": "PCIE_CFGMGMTDI25", - "PIPETX5DATA6": "PCIE_PIPETX5DATA6", - "CFGSLOTCONTROLELECTROMECHILCTLPULSE": "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", - "DRPADDR3": "PCIE_DRPADDR3", - "TRNFCSEL2": "PCIE_TRNFCSEL2", - "CFGMGMTDI12": "PCIE_CFGMGMTDI12", - "MIMTXRDATA57": "PCIE_MIMTXRDATA57", - "CFGERRAERHEADERLOG123": "PCIE_CFGERRAERHEADERLOG123", - "TL2ERRHDR38": "PCIE_TL2ERRHDR38", - "MIMRXWADDR2": "PCIE_MIMRXWADDR2", - "CFGDSN27": "PCIE_CFGDSN27", - "PIPERX0STATUS1": "PCIE_PIPERX0STATUS1", - "MIMTXWADDR4": "PCIE_MIMTXWADDR4", - "TRNFCNPD9": "PCIE_TRNFCNPD9", - "PIPETX4COMPLIANCE": "PCIE_PIPETX4COMPLIANCE", - "TRNTD86": "PCIE_TRNTD86", - "MIMTXWDATA67": "PCIE_MIMTXWDATA67", - "CFGDEVCONTROL2CPLTIMEOUTVAL1": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", - "TRNFCNPD2": "PCIE_TRNFCNPD2", - "PIPETX1DATA11": "PCIE_PIPETX1DATA11", - "TRNRD96": "PCIE_TRNRD96", - "PIPERX7CHANISALIGNED": "PCIE_PIPERX7CHANISALIGNED", - "XILUNCONNOUT19": "PCIE_XILUNCONNOUT19", - "MIMTXWDATA19": "PCIE_MIMTXWDATA19", - "TRNRDLLPDATA33": "PCIE_TRNRDLLPDATA33", - "TRNTD43": "PCIE_TRNTD43", - "TRNTD108": "PCIE_TRNTD108", - "DBGVECB59": "PCIE_DBGVECB59", - "PIPETXMARGIN2": "PCIE_PIPETXMARGIN2", - "MIMRXWDATA2": "PCIE_MIMRXWDATA2", - "TL2ERRHDR35": "PCIE_TL2ERRHDR35", - "LL2SENDPMACK": "PCIE_LL2SENDPMACK", - "CFGDEVCONTROL2IDOCPLEN": "PCIE_CFGDEVCONTROL2IDOCPLEN", - "CFGERRAERHEADERLOG33": "PCIE_CFGERRAERHEADERLOG33", - "CFGERRAERHEADERLOG22": "PCIE_CFGERRAERHEADERLOG22", - "DBGVECB50": "PCIE_DBGVECB50", - "TRNTDLLPDATA30": "PCIE_TRNTDLLPDATA30", - "PL2DIRECTEDLSTATE0": "PCIE_PL2DIRECTEDLSTATE0", - "TL2ERRHDR23": "PCIE_TL2ERRHDR23", - "CFGAERROOTERRCORRERRRECEIVED": "PCIE_CFGAERROOTERRCORRERRRECEIVED", - "PLDIRECTEDLTSSMSTALL": "PCIE_PLDIRECTEDLTSSMSTALL", - "TRNRDLLPDATA0": "PCIE_TRNRDLLPDATA0", - "MIMTXRDATA22": "PCIE_MIMTXRDATA22", - "DBGVECB30": "PCIE_DBGVECB30", - "TRNTD122": "PCIE_TRNTD122", - "TRNTDLLPDATA19": "PCIE_TRNTDLLPDATA19", - "TRNRDLLPDATA19": "PCIE_TRNRDLLPDATA19", - "PLDBGVEC11": "PCIE_PLDBGVEC11", - "DBGSCLRI": "PCIE_DBGSCLRI", - "CFGERRECRCN": "PCIE_CFGERRECRCN", - "CFGDSN16": "PCIE_CFGDSN16", - "CFGMSGRECEIVEDDEASSERTINTD": "PCIE_CFGMSGRECEIVEDDEASSERTINTD", - "CFGERRTLPCPLHEADER46": "PCIE_CFGERRTLPCPLHEADER46", - "PIPETX2DATA2": "PCIE_PIPETX2DATA2", - "MIMTXWDATA39": "PCIE_MIMTXWDATA39", - "DBGVECA31": "PCIE_DBGVECA31", - "CFGERRTLPCPLHEADER35": "PCIE_CFGERRTLPCPLHEADER35", - "MIMTXWADDR3": "PCIE_MIMTXWADDR3", - "TRNFCPH2": "PCIE_TRNFCPH2", - "MIMRXWDATA12": "PCIE_MIMRXWDATA12", - "CFGBRIDGESERREN": "PCIE_CFGBRIDGESERREN", - "USERCLKPREBUFEN": "PCIE_USERCLKPREBUFEN", - "CFGDSN44": "PCIE_CFGDSN44", - "PIPETXMARGIN0": "PCIE_PIPETXMARGIN0", - "DRPDI1": "PCIE_DRPDI1", - "CFGMSGRECEIVEDPMETOACK": "PCIE_CFGMSGRECEIVEDPMETOACK", - "TL2ERRHDR30": "PCIE_TL2ERRHDR30", - "CFGERRAERHEADERLOG26": "PCIE_CFGERRAERHEADERLOG26", - "CFGERRCORN": "PCIE_CFGERRCORN", - "PIPERX5ELECIDLE": "PCIE_PIPERX5ELECIDLE", - "PIPERX2CHARISK1": "PCIE_PIPERX2CHARISK1", - "PIPERX3DATA3": "PCIE_PIPERX3DATA3", - "CFGREVID3": "PCIE_CFGREVID3", - "MIMTXWDATA36": "PCIE_MIMTXWDATA36", - "PIPERX2STATUS0": "PCIE_PIPERX2STATUS0", - "PIPETX0CHARISK0": "PCIE_PIPETX0CHARISK0", - "PIPERX1DATA9": "PCIE_PIPERX1DATA9", - "MIMRXWDATA57": "PCIE_MIMRXWDATA57", - "CFGDSBUSNUMBER3": "PCIE_CFGDSBUSNUMBER3", - "PIPERX3VALID": "PCIE_PIPERX3VALID", - "XILUNCONNOUT0": "PCIE_XILUNCONNOUT0", - "CFGERRAERHEADERLOG16": "PCIE_CFGERRAERHEADERLOG16", - "CFGLINKCONTROLAUTOBANDWIDTHINTEN": "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", - "MIMTXWDATA51": "PCIE_MIMTXWDATA51", - "MIMTXRDATA27": "PCIE_MIMTXRDATA27", - "PIPETX2POWERDOWN0": "PCIE_PIPETX2POWERDOWN0", - "TRNFCPD11": "PCIE_TRNFCPD11", - "MIMTXWADDR2": "PCIE_MIMTXWADDR2", - "CFGERRCPLTIMEOUTN": "PCIE_CFGERRCPLTIMEOUTN", - "MIMRXRDATA48": "PCIE_MIMRXRDATA48", - "CFGLINKCONTROLCLOCKPMEN": "PCIE_CFGLINKCONTROLCLOCKPMEN", - "TRNTD52": "PCIE_TRNTD52", - "EDTUPDATE": "PCIE_EDTUPDATE", - "TRNRECRCERR": "PCIE_TRNRECRCERR", - "PIPERX7ELECIDLE": "PCIE_PIPERX7ELECIDLE", - "PIPERX4DATA7": "PCIE_PIPERX4DATA7", - "TRNFCCPLH3": "PCIE_TRNFCCPLH3", - "TRNRDLLPDATA29": "PCIE_TRNRDLLPDATA29", - "CFGERRAERHEADERLOG100": "PCIE_CFGERRAERHEADERLOG100", - "PLLINKUPCFGCAP": "PCIE_PLLINKUPCFGCAP", - "CFGERRAERHEADERLOG47": "PCIE_CFGERRAERHEADERLOG47", - "MIMTXWDATA64": "PCIE_MIMTXWDATA64", - "TRNRD120": "PCIE_TRNRD120", - "TRNRD72": "PCIE_TRNRD72", - "TRNRD64": "PCIE_TRNRD64", - "MIMTXWDATA42": "PCIE_MIMTXWDATA42", - "DRPDO8": "PCIE_DRPDO8", - "TRNTD16": "PCIE_TRNTD16", - "MIMTXRDATA2": "PCIE_MIMTXRDATA2", - "MIMTXRDATA3": "PCIE_MIMTXRDATA3", - "TRNRD122": "PCIE_TRNRD122", - "MIMTXWDATA35": "PCIE_MIMTXWDATA35", - "CFGDEVCONTROLURERRREPORTINGEN": "PCIE_CFGDEVCONTROLURERRREPORTINGEN", - "CFGDSN36": "PCIE_CFGDSN36", - "PLPHYLNKUPN": "PCIE_PLPHYLNKUPN", - "PIPERX7DATA12": "PCIE_PIPERX7DATA12", - "CFGERRCPLABORTN": "PCIE_CFGERRCPLABORTN", - "CFGREVID5": "PCIE_CFGREVID5", - "CFGDSN53": "PCIE_CFGDSN53", - "TL2PPMSUSPENDOK": "PCIE_TL2PPMSUSPENDOK", - "LL2SENDASREQL1": "PCIE_LL2SENDASREQL1", - "TRNRD56": "PCIE_TRNRD56", - "TRNFCPD6": "PCIE_TRNFCPD6", - "TRNTDLLPDATA16": "PCIE_TRNTDLLPDATA16", - "CFGFORCEMPS1": "PCIE_CFGFORCEMPS1", - "TRNFCNPD10": "PCIE_TRNFCNPD10", - "PIPERX2DATA2": "PCIE_PIPERX2DATA2", - "CFGDSN58": "PCIE_CFGDSN58", - "CFGVENDID6": "PCIE_CFGVENDID6", - "PLDIRECTEDLTSSMNEW0": "PCIE_PLDIRECTEDLTSSMNEW0", - "PIPERX3STATUS0": "PCIE_PIPERX3STATUS0", - "DBGVECB17": "PCIE_DBGVECB17", - "PIPERX1DATA5": "PCIE_PIPERX1DATA5", - "TRNTDLLPDATA13": "PCIE_TRNTDLLPDATA13", - "DBGVECC10": "PCIE_DBGVECC10", - "CFGMGMTBYTEENN0": "PCIE_CFGMGMTBYTEENN0", - "CFGERRAERHEADERLOG17": "PCIE_CFGERRAERHEADERLOG17", - "PLDBGVEC8": "PCIE_PLDBGVEC8", - "MIMRXWDATA14": "PCIE_MIMRXWDATA14", - "TRNFCNPH0": "PCIE_TRNFCNPH0", - "PLRECEIVEDHOTRST": "PCIE_PLRECEIVEDHOTRST", - "TRNRDLLPDATA18": "PCIE_TRNRDLLPDATA18", - "PIPERX2CHANISALIGNED": "PCIE_PIPERX2CHANISALIGNED", - "CFGSUBSYSVENDID10": "PCIE_CFGSUBSYSVENDID10", - "MIMRXRDATA43": "PCIE_MIMRXRDATA43", - "TRNTD34": "PCIE_TRNTD34", - "PIPERX2STATUS1": "PCIE_PIPERX2STATUS1", - "CFGERRTLPCPLHEADER10": "PCIE_CFGERRTLPCPLHEADER10", - "MIMTXRDATA44": "PCIE_MIMTXRDATA44", - "TRNTD93": "PCIE_TRNTD93", - "DBGVECB12": "PCIE_DBGVECB12", - "TRNRD84": "PCIE_TRNRD84", - "CFGERRAERHEADERLOG90": "PCIE_CFGERRAERHEADERLOG90", - "TRNRDLLPDATA36": "PCIE_TRNRDLLPDATA36", - "CFGROOTCONTROLSYSERRNONFATALERREN": "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", - "TRNFCCPLH1": "PCIE_TRNFCCPLH1", - "CFGMGMTDI10": "PCIE_CFGMGMTDI10", - "DBGVECB48": "PCIE_DBGVECB48", - "DBGVECB8": "PCIE_DBGVECB8", - "PIPETX5DATA10": "PCIE_PIPETX5DATA10", - "CFGDSN12": "PCIE_CFGDSN12", - "MIMTXRDATA68": "PCIE_MIMTXRDATA68", - "CFGERRTLPCPLHEADER47": "PCIE_CFGERRTLPCPLHEADER47", - "MIMTXWDATA45": "PCIE_MIMTXWDATA45", - "CFGCOMMANDIOENABLE": "PCIE_CFGCOMMANDIOENABLE", - "TRNRDLLPDATA6": "PCIE_TRNRDLLPDATA6", - "TRNRDLLPDATA3": "PCIE_TRNRDLLPDATA3", - "CFGINTERRUPTMMENABLE0": "PCIE_CFGINTERRUPTMMENABLE0", - "PIPETX5COMPLIANCE": "PCIE_PIPETX5COMPLIANCE", - "TRNRD34": "PCIE_TRNRD34", - "TRNTD38": "PCIE_TRNTD38", - "TRNRDLLPDATA23": "PCIE_TRNRDLLPDATA23", - "CFGMGMTDO11": "PCIE_CFGMGMTDO11", - "CFGERRAERHEADERLOG44": "PCIE_CFGERRAERHEADERLOG44", - "MIMRXWDATA21": "PCIE_MIMRXWDATA21", - "CFGERRTLPCPLHEADER14": "PCIE_CFGERRTLPCPLHEADER14", - "TRNRSOF": "PCIE_TRNRSOF", - "DRPDO15": "PCIE_DRPDO15", - "CFGFORCEMPS0": "PCIE_CFGFORCEMPS0", - "TRNRD76": "PCIE_TRNRD76", - "PIPETX5CHARISK0": "PCIE_PIPETX5CHARISK0", - "PIPETX7DATA11": "PCIE_PIPETX7DATA11", - "CFGERRAERHEADERLOG46": "PCIE_CFGERRAERHEADERLOG46", - "DBGVECA53": "PCIE_DBGVECA53", - "TRNRD4": "PCIE_TRNRD4", - "CFGMGMTDWADDR3": "PCIE_CFGMGMTDWADDR3", - "TRNFCNPD3": "PCIE_TRNFCNPD3", - "CFGPMCSRPOWERSTATE1": "PCIE_CFGPMCSRPOWERSTATE1", - "DRPEN": "PCIE_DRPEN", - "MIMTXRDATA28": "PCIE_MIMTXRDATA28", - "TRNTDLLPDATA0": "PCIE_TRNTDLLPDATA0", - "CFGLINKCONTROLEXTENDEDSYNC": "PCIE_CFGLINKCONTROLEXTENDEDSYNC", - "PIPETX5POWERDOWN1": "PCIE_PIPETX5POWERDOWN1", - "DRPDI14": "PCIE_DRPDI14", - "TRNRD79": "PCIE_TRNRD79", - "CFGDEVID2": "PCIE_CFGDEVID2", - "TRNRREM1": "PCIE_TRNRREM1", - "CFGMGMTDI1": "PCIE_CFGMGMTDI1", - "CFGSUBSYSID13": "PCIE_CFGSUBSYSID13", - "CFGCOMMANDSERREN": "PCIE_CFGCOMMANDSERREN", - "MIMRXWDATA26": "PCIE_MIMRXWDATA26", - "CFGDSN23": "PCIE_CFGDSN23", - "CFGSUBSYSVENDID12": "PCIE_CFGSUBSYSVENDID12", - "MIMRXRDATA19": "PCIE_MIMRXRDATA19", - "MIMRXWDATA33": "PCIE_MIMRXWDATA33", - "CFGTRANSACTIONADDR4": "PCIE_CFGTRANSACTIONADDR4", - "TRNTD67": "PCIE_TRNTD67", - "TRNTBUFAV2": "PCIE_TRNTBUFAV2", - "MIMRXWDATA38": "PCIE_MIMRXWDATA38", - "CFGDSN21": "PCIE_CFGDSN21", - "DRPDI3": "PCIE_DRPDI3", - "EDTCLK": "PCIE_EDTCLK", - "TRNRD38": "PCIE_TRNRD38", - "CFGERRTLPCPLHEADER38": "PCIE_CFGERRTLPCPLHEADER38", - "CFGVCTCVCMAP3": "PCIE_CFGVCTCVCMAP3", - "CFGERRAERHEADERLOG91": "PCIE_CFGERRAERHEADERLOG91", - "DRPRDY": "PCIE_DRPRDY", - "TRNTD92": "PCIE_TRNTD92", - "CFGDSN14": "PCIE_CFGDSN14", - "MIMRXRDATA15": "PCIE_MIMRXRDATA15", - "MIMTXWDATA55": "PCIE_MIMTXWDATA55", - "MIMRXRADDR5": "PCIE_MIMRXRADDR5", - "MIMRXWDATA9": "PCIE_MIMRXWDATA9", - "MIMRXRADDR11": "PCIE_MIMRXRADDR11", - "TRNRDLLPDATA47": "PCIE_TRNRDLLPDATA47", - "PIPETX6DATA13": "PCIE_PIPETX6DATA13", - "MIMTXWDATA9": "PCIE_MIMTXWDATA9", - "CFGERRTLPCPLHEADER12": "PCIE_CFGERRTLPCPLHEADER12", - "CFGLINKSTATUSNEGOTIATEDWIDTH0": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", - "MIMRXRDATA61": "PCIE_MIMRXRDATA61", - "PIPETX1POWERDOWN0": "PCIE_PIPETX1POWERDOWN0", - "TRNRD13": "PCIE_TRNRD13", - "XILUNCONNOUT18": "PCIE_XILUNCONNOUT18", - "PIPETX5DATA5": "PCIE_PIPETX5DATA5", - "TL2ERRHDR12": "PCIE_TL2ERRHDR12", - "MIMRXRDATA27": "PCIE_MIMRXRDATA27", - "PIPERX0DATA11": "PCIE_PIPERX0DATA11", - "CFGDEVCONTROLMAXPAYLOAD2": "PCIE_CFGDEVCONTROLMAXPAYLOAD2", - "MIMRXWDATA52": "PCIE_MIMRXWDATA52", - "MIMTXRADDR7": "PCIE_MIMTXRADDR7", - "CFGMGMTDI29": "PCIE_CFGMGMTDI29", - "CFGERRAERHEADERLOG72": "PCIE_CFGERRAERHEADERLOG72", - "TRNRD17": "PCIE_TRNRD17", - "CFGDEVCONTROLMAXREADREQ2": "PCIE_CFGDEVCONTROLMAXREADREQ2", - "DBGVECA42": "PCIE_DBGVECA42", - "PIPETX3DATA11": "PCIE_PIPETX3DATA11", - "TRNRD119": "PCIE_TRNRD119", - "DBGVECB41": "PCIE_DBGVECB41", - "LL2SUSPENDOK": "PCIE_LL2SUSPENDOK", - "PIPETX6DATA6": "PCIE_PIPETX6DATA6", - "CFGDEVSTATUSCORRERRDETECTED": "PCIE_CFGDEVSTATUSCORRERRDETECTED", - "MIMTXRDATA19": "PCIE_MIMTXRDATA19", - "CFGMSGRECEIVEDDEASSERTINTA": "PCIE_CFGMSGRECEIVEDDEASSERTINTA", - "MIMRXWDATA36": "PCIE_MIMRXWDATA36", - "CFGLINKSTATUSNEGOTIATEDWIDTH1": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", - "DRPDO14": "PCIE_DRPDO14", - "CFGERRAERHEADERLOG87": "PCIE_CFGERRAERHEADERLOG87", - "USERCLKPREBUF": "PCIE_USERCLKPREBUF", - "MIMRXWADDR10": "PCIE_MIMRXWADDR10", - "CFGMSGDATA11": "PCIE_CFGMSGDATA11", - "TRNTD20": "PCIE_TRNTD20", - "MIMTXWADDR5": "PCIE_MIMTXWADDR5", - "PIPERX5DATA15": "PCIE_PIPERX5DATA15", - "CFGTRANSACTIONADDR5": "PCIE_CFGTRANSACTIONADDR5", - "PIPERX7DATA2": "PCIE_PIPERX7DATA2", - "PIPETX5DATA4": "PCIE_PIPETX5DATA4", - "PIPETXRATE": "PCIE_PIPETXRATE", - "CFGERRAERHEADERLOG65": "PCIE_CFGERRAERHEADERLOG65", - "CFGERRAERHEADERLOG36": "PCIE_CFGERRAERHEADERLOG36", - "CFGDSN55": "PCIE_CFGDSN55", - "TRNFCCPLH5": "PCIE_TRNFCCPLH5", - "TRNRDLLPDATA43": "PCIE_TRNRDLLPDATA43", - "DRPADDR0": "PCIE_DRPADDR0", - "MIMRXWDATA6": "PCIE_MIMRXWDATA6", - "TRNTBUFAV1": "PCIE_TRNTBUFAV1", - "MIMTXWDATA46": "PCIE_MIMTXWDATA46", - "DBGSUBMODE": "PCIE_DBGSUBMODE", - "CFGDSN5": "PCIE_CFGDSN5", - "PIPETX2DATA11": "PCIE_PIPETX2DATA11", - "PIPERX5DATA8": "PCIE_PIPERX5DATA8", - "PIPERX5DATA14": "PCIE_PIPERX5DATA14", - "TRNTD0": "PCIE_TRNTD0", - "PIPETX6POWERDOWN0": "PCIE_PIPETX6POWERDOWN0", - "PIPERX6DATA14": "PCIE_PIPERX6DATA14", - "PIPETX5DATA14": "PCIE_PIPETX5DATA14", - "PIPERX7DATA10": "PCIE_PIPERX7DATA10", - "TRNRD12": "PCIE_TRNRD12", - "CFGDEVCONTROLCORRERRREPORTINGEN": "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", - "CFGSUBSYSID12": "PCIE_CFGSUBSYSID12", - "PIPETX4CHARISK1": "PCIE_PIPETX4CHARISK1", - "CFGMGMTDO2": "PCIE_CFGMGMTDO2", - "MIMTXWDATA5": "PCIE_MIMTXWDATA5", - "TRNTD113": "PCIE_TRNTD113", - "TRNTDLLPDATA17": "PCIE_TRNTDLLPDATA17", - "CFGDSN40": "PCIE_CFGDSN40", - "CFGERRAERHEADERLOG99": "PCIE_CFGERRAERHEADERLOG99", - "TRNRD123": "PCIE_TRNRD123", - "TRNTD90": "PCIE_TRNTD90", - "LL2LINKSTATUS1": "PCIE_LL2LINKSTATUS1", - "MIMRXRDATA31": "PCIE_MIMRXRDATA31", - "CFGPMWAKEN": "PCIE_CFGPMWAKEN", - "CFGDSBUSNUMBER6": "PCIE_CFGDSBUSNUMBER6", - "PLDBGVEC2": "PCIE_PLDBGVEC2", - "PIPERX0POLARITY": "PCIE_PIPERX0POLARITY", - "CFGERRTLPCPLHEADER30": "PCIE_CFGERRTLPCPLHEADER30", - "TRNTD41": "PCIE_TRNTD41", - "TRNRD105": "PCIE_TRNRD105", - "CFGERRAERHEADERLOG52": "PCIE_CFGERRAERHEADERLOG52", - "MIMRXWDATA48": "PCIE_MIMRXWDATA48", - "TRNRDLLPDATA44": "PCIE_TRNRDLLPDATA44", - "TL2ERRHDR17": "PCIE_TL2ERRHDR17", - "TL2ERRHDR20": "PCIE_TL2ERRHDR20", - "TRNRD92": "PCIE_TRNRD92", - "XILUNCONNOUT34": "PCIE_XILUNCONNOUT34", - "TL2ERRHDR43": "PCIE_TL2ERRHDR43", - "TRNRDLLPDATA58": "PCIE_TRNRDLLPDATA58", - "CFGLINKSTATUSLINKTRAINING": "PCIE_CFGLINKSTATUSLINKTRAINING", - "DBGVECB63": "PCIE_DBGVECB63", - "TRNFCCPLD1": "PCIE_TRNFCCPLD1", - "CFGAERECRCCHECKEN": "PCIE_CFGAERECRCCHECKEN", - "CFGREVID6": "PCIE_CFGREVID6", - "PLDBGVEC3": "PCIE_PLDBGVEC3", - "CFGMGMTRDENN": "PCIE_CFGMGMTRDENN", - "PIPETX7DATA12": "PCIE_PIPETX7DATA12", - "XILUNCONNOUT10": "PCIE_XILUNCONNOUT10", - "MIMRXWDATA25": "PCIE_MIMRXWDATA25", - "PIPETX4ELECIDLE": "PCIE_PIPETX4ELECIDLE", - "EDTBYPASS": "PCIE_EDTBYPASS", - "CFGVENDID0": "PCIE_CFGVENDID0", - "CFGPCIECAPINTERRUPTMSGNUM0": "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", - "TRNRNPOK": "PCIE_TRNRNPOK", - "CFGVENDID11": "PCIE_CFGVENDID11", - "LL2LINKSTATUS4": "PCIE_LL2LINKSTATUS4", - "CFGMGMTDO22": "PCIE_CFGMGMTDO22", - "CFGERRAERHEADERLOG73": "PCIE_CFGERRAERHEADERLOG73", - "CFGDSBUSNUMBER0": "PCIE_CFGDSBUSNUMBER0", - "CFGLINKSTATUSNEGOTIATEDWIDTH3": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", - "CFGERRTLPCPLHEADER0": "PCIE_CFGERRTLPCPLHEADER0", - "MIMRXWDATA64": "PCIE_MIMRXWDATA64", - "PIPETX0DATA9": "PCIE_PIPETX0DATA9", - "DRPDI9": "PCIE_DRPDI9", - "CFGDEVID9": "PCIE_CFGDEVID9", - "PIPERX0DATA9": "PCIE_PIPERX0DATA9", - "MIMTXWDATA33": "PCIE_MIMTXWDATA33", - "LL2REPLAYTOERR": "PCIE_LL2REPLAYTOERR", - "CFGMGMTDO3": "PCIE_CFGMGMTDO3", - "MIMRXWADDR6": "PCIE_MIMRXWADDR6", - "TRNTD61": "PCIE_TRNTD61", - "TRNRD46": "PCIE_TRNRD46", - "CFGDEVID8": "PCIE_CFGDEVID8", - "DRPDI2": "PCIE_DRPDI2", - "TRNTDLLPDATA2": "PCIE_TRNTDLLPDATA2", - "MIMTXRDATA24": "PCIE_MIMTXRDATA24", - "PIPETX0DATA2": "PCIE_PIPETX0DATA2", - "MIMRXWDATA65": "PCIE_MIMRXWDATA65", - "TRNRD90": "PCIE_TRNRD90", - "TRNRDLLPDATA40": "PCIE_TRNRDLLPDATA40", - "PIPERX6CHARISK1": "PCIE_PIPERX6CHARISK1", - "PIPERX2DATA5": "PCIE_PIPERX2DATA5", - "PIPERX7DATA3": "PCIE_PIPERX7DATA3", - "XILUNCONNOUT35": "PCIE_XILUNCONNOUT35", - "TRNRDLLPDATA12": "PCIE_TRNRDLLPDATA12", - "CFGERRTLPCPLHEADER36": "PCIE_CFGERRTLPCPLHEADER36", - "TRNTD66": "PCIE_TRNTD66", - "TRNFCPD8": "PCIE_TRNFCPD8", - "MIMTXWDATA58": "PCIE_MIMTXWDATA58", - "CFGROOTCONTROLPMEINTEN": "PCIE_CFGROOTCONTROLPMEINTEN", - "TRNTD85": "PCIE_TRNTD85", - "MIMTXRDATA47": "PCIE_MIMTXRDATA47", - "DBGVECA54": "PCIE_DBGVECA54", - "PIPERX7CHARISK0": "PCIE_PIPERX7CHARISK0", - "TRNFCPH7": "PCIE_TRNFCPH7", - "CFGDSN38": "PCIE_CFGDSN38", - "TRNRD3": "PCIE_TRNRD3", - "PL2DIRECTEDLSTATE2": "PCIE_PL2DIRECTEDLSTATE2", - "EDTCHANNELSIN3": "PCIE_EDTCHANNELSIN3", - "TRNTD4": "PCIE_TRNTD4", - "TL2PPMSUSPENDREQ": "PCIE_TL2PPMSUSPENDREQ", - "CFGDSN31": "PCIE_CFGDSN31", - "MIMTXRDATA8": "PCIE_MIMTXRDATA8", - "TRNTDSTRDY0": "PCIE_TRNTDSTRDY0", - "CFGSUBSYSVENDID4": "PCIE_CFGSUBSYSVENDID4", - "TRNRD8": "PCIE_TRNRD8", - "CFGDEVID4": "PCIE_CFGDEVID4", - "TRNTD2": "PCIE_TRNTD2", - "CFGROOTCONTROLSYSERRFATALERREN": "PCIE_CFGROOTCONTROLSYSERRFATALERREN", - "DBGVECA45": "PCIE_DBGVECA45", - "CFGERRAERHEADERLOG18": "PCIE_CFGERRAERHEADERLOG18", - "TRNRD95": "PCIE_TRNRD95", - "TRNTDLLPDATA9": "PCIE_TRNTDLLPDATA9", - "MIMTXRDATA35": "PCIE_MIMTXRDATA35", - "TRNTD72": "PCIE_TRNTD72", - "MIMTXWDATA32": "PCIE_MIMTXWDATA32", - "TRNTDSTRDY1": "PCIE_TRNTDSTRDY1", - "TRNTREM1": "PCIE_TRNTREM1", - "CFGINTERRUPTDO4": "PCIE_CFGINTERRUPTDO4", - "MIMRXRDATA60": "PCIE_MIMRXRDATA60", - "CFGDSBUSNUMBER2": "PCIE_CFGDSBUSNUMBER2", - "PL2RXPMSTATE1": "PCIE_PL2RXPMSTATE1", - "PLINITIALLINKWIDTH2": "PCIE_PLINITIALLINKWIDTH2", - "XILUNCONNOUT32": "PCIE_XILUNCONNOUT32", - "MIMTXWADDR9": "PCIE_MIMTXWADDR9", - "PIPERX6DATA7": "PCIE_PIPERX6DATA7", - "TRNFCNPD5": "PCIE_TRNFCNPD5", - "PIPERX4DATA0": "PCIE_PIPERX4DATA0", - "MIMRXWDATA46": "PCIE_MIMRXWDATA46", - "LNKCLKEN": "PCIE_LNKCLKEN", - "TRNTD127": "PCIE_TRNTD127", - "DBGVECA29": "PCIE_DBGVECA29", - "DBGVECA1": "PCIE_DBGVECA1", - "PIPETX2DATA8": "PCIE_PIPETX2DATA8", - "DBGVECB32": "PCIE_DBGVECB32", - "PIPERX2CHARISK0": "PCIE_PIPERX2CHARISK0", - "DBGVECB33": "PCIE_DBGVECB33", - "DBGVECB9": "PCIE_DBGVECB9", - "MIMRXRDATA14": "PCIE_MIMRXRDATA14", - "CFGERRAERHEADERLOG54": "PCIE_CFGERRAERHEADERLOG54", - "TL2ERRHDR63": "PCIE_TL2ERRHDR63", - "TRNRDLLPDATA2": "PCIE_TRNRDLLPDATA2", - "TRNRD41": "PCIE_TRNRD41", - "TRNTD27": "PCIE_TRNTD27", - "PLDIRECTEDLTSSMNEWVLD": "PCIE_PLDIRECTEDLTSSMNEWVLD", - "TRNTD107": "PCIE_TRNTD107", - "CFGINTERRUPTN": "PCIE_CFGINTERRUPTN", - "TRNRD118": "PCIE_TRNRD118", - "TRNRD7": "PCIE_TRNRD7", - "PIPETX5DATA13": "PCIE_PIPETX5DATA13", - "PIPERX6DATA11": "PCIE_PIPERX6DATA11", - "DBGVECA14": "PCIE_DBGVECA14", - "MIMTXWADDR10": "PCIE_MIMTXWADDR10", - "LL2LINKSTATUS2": "PCIE_LL2LINKSTATUS2", - "DBGVECA0": "PCIE_DBGVECA0", - "CFGMSGDATA13": "PCIE_CFGMSGDATA13", - "MIMRXRDATA40": "PCIE_MIMRXRDATA40", - "CFGINTERRUPTMSIXFM": "PCIE_CFGINTERRUPTMSIXFM", - "MIMRXWDATA27": "PCIE_MIMRXWDATA27", - "DBGVECA13": "PCIE_DBGVECA13", - "PIPETX6COMPLIANCE": "PCIE_PIPETX6COMPLIANCE", - "LL2TLPRCV": "PCIE_LL2TLPRCV", - "PIPETX0CHARISK1": "PCIE_PIPETX0CHARISK1", - "MIMRXRDATA34": "PCIE_MIMRXRDATA34", - "MIMTXRDATA9": "PCIE_MIMTXRDATA9", - "PIPETX0DATA4": "PCIE_PIPETX0DATA4", - "CFGDSN60": "PCIE_CFGDSN60", - "CFGDEVCONTROL2CPLTIMEOUTDIS": "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", - "PIPERX5DATA1": "PCIE_PIPERX5DATA1", - "MIMTXWDATA13": "PCIE_MIMTXWDATA13", - "MIMTXRDATA36": "PCIE_MIMTXRDATA36", - "PIPERX1DATA10": "PCIE_PIPERX1DATA10", - "TRNRD29": "PCIE_TRNRD29", - "CFGSUBSYSID2": "PCIE_CFGSUBSYSID2", - "CFGDEVSTATUSFATALERRDETECTED": "PCIE_CFGDEVSTATUSFATALERRDETECTED", - "MIMTXWDATA23": "PCIE_MIMTXWDATA23", - "TRNRD109": "PCIE_TRNRD109", - "CFGMGMTBYTEENN3": "PCIE_CFGMGMTBYTEENN3", - "CFGDSDEVICENUMBER3": "PCIE_CFGDSDEVICENUMBER3", - "PLDBGVEC6": "PCIE_PLDBGVEC6", - "CFGDSN19": "PCIE_CFGDSN19", - "MIMTXWDATA12": "PCIE_MIMTXWDATA12", - "EDTSINGLEBYPASSCHAIN": "PCIE_EDTSINGLEBYPASSCHAIN", - "CFGERRCPLRDYN": "PCIE_CFGERRCPLRDYN", - "PIPETX6DATA3": "PCIE_PIPETX6DATA3", - "MIMTXWDATA37": "PCIE_MIMTXWDATA37", - "TRNTD118": "PCIE_TRNTD118", - "TRNRBARHIT0": "PCIE_TRNRBARHIT0", - "DBGVECA49": "PCIE_DBGVECA49", - "PIPERX4STATUS1": "PCIE_PIPERX4STATUS1", - "CFGDSN32": "PCIE_CFGDSN32", - "CFGLINKSTATUSCURRENTSPEED1": "PCIE_CFGLINKSTATUSCURRENTSPEED1", - "MIMTXRDATA12": "PCIE_MIMTXRDATA12", - "CFGDSN9": "PCIE_CFGDSN9", - "MIMTXWDATA18": "PCIE_MIMTXWDATA18", - "CMRSTN": "PCIE_CMRSTN", - "DBGVECA8": "PCIE_DBGVECA8", - "CFGMGMTDWADDR8": "PCIE_CFGMGMTDWADDR8", - "CFGERRTLPCPLHEADER7": "PCIE_CFGERRTLPCPLHEADER7", - "PIPETX5DATA9": "PCIE_PIPETX5DATA9", - "CFGERRAERHEADERLOG64": "PCIE_CFGERRAERHEADERLOG64", - "CFGPCIECAPINTERRUPTMSGNUM2": "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", - "CFGVENDID9": "PCIE_CFGVENDID9", - "CFGSUBSYSID6": "PCIE_CFGSUBSYSID6", - "PIPERX1DATA7": "PCIE_PIPERX1DATA7", - "CFGTRANSACTIONTYPE": "PCIE_CFGTRANSACTIONTYPE", - "TL2ERRHDR27": "PCIE_TL2ERRHDR27", - "PIPETX6DATA9": "PCIE_PIPETX6DATA9", - "PIPERX3POLARITY": "PCIE_PIPERX3POLARITY", - "CFGMGMTWRENN": "PCIE_CFGMGMTWRENN", - "CFGDSN41": "PCIE_CFGDSN41", - "TRNRD31": "PCIE_TRNRD31", - "TRNTDLLPDATA21": "PCIE_TRNTDLLPDATA21", - "MIMRXWDATA28": "PCIE_MIMRXWDATA28", - "TRNRFCPRET": "PCIE_TRNRFCPRET", - "TRNRD63": "PCIE_TRNRD63", - "TRNTD97": "PCIE_TRNTD97", - "TL2ERRHDR51": "PCIE_TL2ERRHDR51", - "CFGDSN6": "PCIE_CFGDSN6", - "MIMRXWDATA7": "PCIE_MIMRXWDATA7", - "CFGERRTLPCPLHEADER21": "PCIE_CFGERRTLPCPLHEADER21", - "CFGPMHALTASPML1N": "PCIE_CFGPMHALTASPML1N", - "CFGERRAERHEADERLOG112": "PCIE_CFGERRAERHEADERLOG112", - "DBGVECB19": "PCIE_DBGVECB19", - "CFGDEVID10": "PCIE_CFGDEVID10", - "CFGINTERRUPTDI2": "PCIE_CFGINTERRUPTDI2", - "DBGVECB23": "PCIE_DBGVECB23", - "MIMTXRADDR0": "PCIE_MIMTXRADDR0", - "TRNFCSEL1": "PCIE_TRNFCSEL1", - "PIPETX1DATA0": "PCIE_PIPETX1DATA0", - "TRNRDLLPDATA5": "PCIE_TRNRDLLPDATA5", - "CFGERRCPLUNEXPECTN": "PCIE_CFGERRCPLUNEXPECTN", - "CFGERRURN": "PCIE_CFGERRURN", - "MIMTXRDATA10": "PCIE_MIMTXRDATA10", - "XILUNCONNOUT24": "PCIE_XILUNCONNOUT24", - "PIPETX2DATA5": "PCIE_PIPETX2DATA5", - "MIMTXRADDR3": "PCIE_MIMTXRADDR3", - "DBGVECA18": "PCIE_DBGVECA18", - "CFGSUBSYSID11": "PCIE_CFGSUBSYSID11", - "PIPERX2ELECIDLE": "PCIE_PIPERX2ELECIDLE", - "TRNFCCPLD7": "PCIE_TRNFCCPLD7", - "MIMRXRADDR1": "PCIE_MIMRXRADDR1", - "XILUNCONNOUT38": "PCIE_XILUNCONNOUT38", - "CFGPCIECAPINTERRUPTMSGNUM4": "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", - "CFGAERINTERRUPTMSGNUM4": "PCIE_CFGAERINTERRUPTMSGNUM4", - "XILUNCONNOUT23": "PCIE_XILUNCONNOUT23", - "PIPETX7DATA4": "PCIE_PIPETX7DATA4", - "PIPERX0CHANISALIGNED": "PCIE_PIPERX0CHANISALIGNED", - "TL2ERRRXOVERFLOW": "PCIE_TL2ERRRXOVERFLOW", - "CFGDSN56": "PCIE_CFGDSN56", - "DBGVECC1": "PCIE_DBGVECC1", - "CFGDEVID14": "PCIE_CFGDEVID14", - "TRNRD33": "PCIE_TRNRD33", - "TL2ERRHDR22": "PCIE_TL2ERRHDR22", - "MIMRXRDATA1": "PCIE_MIMRXRDATA1", - "XILUNCONNOUT5": "PCIE_XILUNCONNOUT5", - "PLDBGMODE1": "PCIE_PLDBGMODE1", - "CFGERRAERHEADERLOG13": "PCIE_CFGERRAERHEADERLOG13", - "CFGLINKCONTROLLINKDISABLE": "PCIE_CFGLINKCONTROLLINKDISABLE", - "CFGERRAERHEADERLOG24": "PCIE_CFGERRAERHEADERLOG24", - "TRNTSTR": "PCIE_TRNTSTR", - "MIMTXRDATA62": "PCIE_MIMTXRDATA62", - "TRNTD104": "PCIE_TRNTD104", - "CFGERRAERHEADERLOG62": "PCIE_CFGERRAERHEADERLOG62", - "TRNRD80": "PCIE_TRNRD80", - "CFGERRAERHEADERLOG103": "PCIE_CFGERRAERHEADERLOG103", - "CFGPMCSRPMEEN": "PCIE_CFGPMCSRPMEEN", - "PLLINKGEN2CAP": "PCIE_PLLINKGEN2CAP", - "MIMRXRADDR2": "PCIE_MIMRXRADDR2", - "DBGSCLRF": "PCIE_DBGSCLRF", - "TRNRDLLPDATA42": "PCIE_TRNRDLLPDATA42", - "MIMRXRADDR0": "PCIE_MIMRXRADDR0", - "CFGDEVID11": "PCIE_CFGDEVID11", - "TRNRD70": "PCIE_TRNRD70", - "TRNRSRCRDY": "PCIE_TRNRSRCRDY", - "DBGVECA55": "PCIE_DBGVECA55", - "CFGERRTLPCPLHEADER19": "PCIE_CFGERRTLPCPLHEADER19", - "PIPETX2DATA6": "PCIE_PIPETX2DATA6", - "TRNTD11": "PCIE_TRNTD11", - "TRNTD47": "PCIE_TRNTD47", - "MIMTXRADDR4": "PCIE_MIMTXRADDR4", - "PLDIRECTEDLTSSMNEW5": "PCIE_PLDIRECTEDLTSSMNEW5", - "MIMRXWADDR11": "PCIE_MIMRXWADDR11", - "TRNRDLLPDATA25": "PCIE_TRNRDLLPDATA25", - "CFGDSFUNCTIONNUMBER2": "PCIE_CFGDSFUNCTIONNUMBER2", - "TRNRDLLPDATA39": "PCIE_TRNRDLLPDATA39", - "PIPETX7DATA5": "PCIE_PIPETX7DATA5", - "CFGINTERRUPTDO1": "PCIE_CFGINTERRUPTDO1", - "DBGVECA51": "PCIE_DBGVECA51", - "TRNTDLLPDATA7": "PCIE_TRNTDLLPDATA7", - "CFGMGMTDI17": "PCIE_CFGMGMTDI17", - "CFGERRINTERNALCORN": "PCIE_CFGERRINTERNALCORN", - "PIPERX3STATUS2": "PCIE_PIPERX3STATUS2", - "CFGERRAERHEADERLOG0": "PCIE_CFGERRAERHEADERLOG0", - "EDTCHANNELSOUT1": "PCIE_EDTCHANNELSOUT1", - "TRNRD59": "PCIE_TRNRD59", - "PLDIRECTEDLINKCHANGE1": "PCIE_PLDIRECTEDLINKCHANGE1", - "CFGMSGDATA9": "PCIE_CFGMSGDATA9", - "PIPERX1DATA14": "PCIE_PIPERX1DATA14", - "DBGVECB7": "PCIE_DBGVECB7", - "TL2ERRHDR19": "PCIE_TL2ERRHDR19", - "CFGMSGRECEIVEDPMETO": "PCIE_CFGMSGRECEIVEDPMETO", - "TRNTD64": "PCIE_TRNTD64", - "CFGERRTLPCPLHEADER20": "PCIE_CFGERRTLPCPLHEADER20", - "MIMRXWADDR8": "PCIE_MIMRXWADDR8", - "MIMTXRADDR9": "PCIE_MIMTXRADDR9", - "TRNTD15": "PCIE_TRNTD15", - "TRNRBARHIT6": "PCIE_TRNRBARHIT6", - "PIPETX1DATA15": "PCIE_PIPETX1DATA15", - "PIPETX5DATA11": "PCIE_PIPETX5DATA11", - "DBGVECC8": "PCIE_DBGVECC8", - "CFGDSN22": "PCIE_CFGDSN22", - "PIPETXRESET": "PCIE_PIPETXRESET", - "TRNTD120": "PCIE_TRNTD120", - "MIMTXRDATA50": "PCIE_MIMTXRDATA50", - "CFGDSN7": "PCIE_CFGDSN7", - "TL2ERRHDR59": "PCIE_TL2ERRHDR59", - "TRNRD24": "PCIE_TRNRD24", - "PIPERX6DATA2": "PCIE_PIPERX6DATA2", - "PIPERX2DATA3": "PCIE_PIPERX2DATA3", - "MIMTXWDATA56": "PCIE_MIMTXWDATA56", - "CFGMGMTDI14": "PCIE_CFGMGMTDI14", - "CFGERRAERHEADERLOG67": "PCIE_CFGERRAERHEADERLOG67", - "TRNTD121": "PCIE_TRNTD121", - "EDTCHANNELSIN1": "PCIE_EDTCHANNELSIN1", - "CFGPMSENDPMETON": "PCIE_CFGPMSENDPMETON", - "CFGVENDID4": "PCIE_CFGVENDID4", - "PIPETX3POWERDOWN0": "PCIE_PIPETX3POWERDOWN0", - "PLDBGVEC7": "PCIE_PLDBGVEC7", - "PLLTSSMSTATE5": "PCIE_PLLTSSMSTATE5", - "MIMTXRDATA23": "PCIE_MIMTXRDATA23", - "TL2ERRHDR25": "PCIE_TL2ERRHDR25", - "CFGMGMTDO20": "PCIE_CFGMGMTDO20", - "MIMRXRDATA37": "PCIE_MIMRXRDATA37", - "PIPERX5DATA5": "PCIE_PIPERX5DATA5", - "PIPETX1DATA8": "PCIE_PIPETX1DATA8", - "DBGVECA26": "PCIE_DBGVECA26", - "CFGDEVID6": "PCIE_CFGDEVID6", - "CFGMGMTDWADDR9": "PCIE_CFGMGMTDWADDR9", - "CFGMGMTDI30": "PCIE_CFGMGMTDI30", - "CFGSUBSYSID0": "PCIE_CFGSUBSYSID0", - "TRNTD124": "PCIE_TRNTD124", - "PIPERX0ELECIDLE": "PCIE_PIPERX0ELECIDLE", - "PIPERX5STATUS0": "PCIE_PIPERX5STATUS0", - "CFGPMFORCESTATE0": "PCIE_CFGPMFORCESTATE0", - "TRNRD14": "PCIE_TRNRD14", - "CFGERRAERHEADERLOG15": "PCIE_CFGERRAERHEADERLOG15", - "PIPETX2DATA3": "PCIE_PIPETX2DATA3", - "PIPERX6DATA6": "PCIE_PIPERX6DATA6", - "CFGMGMTDI19": "PCIE_CFGMGMTDI19", - "PIPERX4DATA10": "PCIE_PIPERX4DATA10", - "XILUNCONNOUT17": "PCIE_XILUNCONNOUT17", - "MIMTXRADDR11": "PCIE_MIMTXRADDR11", - "DBGVECC9": "PCIE_DBGVECC9", - "MIMTXWDATA16": "PCIE_MIMTXWDATA16", - "CFGINTERRUPTDI7": "PCIE_CFGINTERRUPTDI7", - "TL2ERRHDR44": "PCIE_TL2ERRHDR44", - "CFGERRAERHEADERLOG119": "PCIE_CFGERRAERHEADERLOG119", - "MIMTXRDATA53": "PCIE_MIMTXRDATA53", - "TRNRD57": "PCIE_TRNRD57", - "PLLTSSMSTATE1": "PCIE_PLLTSSMSTATE1", - "PIPETX2DATA4": "PCIE_PIPETX2DATA4", - "TRNRDLLPDATA59": "PCIE_TRNRDLLPDATA59", - "MIMTXWDATA3": "PCIE_MIMTXWDATA3", - "MIMTXWDATA10": "PCIE_MIMTXWDATA10", - "CFGMGMTDI20": "PCIE_CFGMGMTDI20", - "CFGINTERRUPTDI4": "PCIE_CFGINTERRUPTDI4", - "CFGSUBSYSVENDID14": "PCIE_CFGSUBSYSVENDID14", - "PIPERX5STATUS1": "PCIE_PIPERX5STATUS1", - "CFGAERROOTERRNONFATALERRREPORTINGEN": "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", - "PIPETX2DATA13": "PCIE_PIPETX2DATA13", - "CFGLINKSTATUSCURRENTSPEED0": "PCIE_CFGLINKSTATUSCURRENTSPEED0", - "DRPDI15": "PCIE_DRPDI15", - "MIMRXWDATA18": "PCIE_MIMRXWDATA18", - "MIMTXRDATA43": "PCIE_MIMTXRDATA43", - "TRNRD110": "PCIE_TRNRD110", - "CFGERRTLPCPLHEADER44": "PCIE_CFGERRTLPCPLHEADER44", - "DBGVECA48": "PCIE_DBGVECA48", - "CFGMGMTDO27": "PCIE_CFGMGMTDO27", - "CFGERRAERHEADERLOG101": "PCIE_CFGERRAERHEADERLOG101", - "CFGVENDID5": "PCIE_CFGVENDID5", - "MIMTXWDATA48": "PCIE_MIMTXWDATA48", - "DBGVECA25": "PCIE_DBGVECA25", - "CFGMGMTDO1": "PCIE_CFGMGMTDO1", - "DBGVECB60": "PCIE_DBGVECB60", - "DBGVECB42": "PCIE_DBGVECB42", - "MIMTXRDATA55": "PCIE_MIMTXRDATA55", - "PIPETX0DATA0": "PCIE_PIPETX0DATA0", - "CFGINTERRUPTDO0": "PCIE_CFGINTERRUPTDO0", - "TRNRD78": "PCIE_TRNRD78", - "CFGINTERRUPTDI5": "PCIE_CFGINTERRUPTDI5", - "DRPDO3": "PCIE_DRPDO3", - "XILUNCONNOUT13": "PCIE_XILUNCONNOUT13", - "TRNTD3": "PCIE_TRNTD3", - "DBGVECA62": "PCIE_DBGVECA62", - "CFGMGMTDI26": "PCIE_CFGMGMTDI26", - "PIPETX5DATA0": "PCIE_PIPETX5DATA0", - "CFGERRAERHEADERLOG25": "PCIE_CFGERRAERHEADERLOG25", - "EDTCONFIGURATION": "PCIE_EDTCONFIGURATION", - "MIMRXRDATA33": "PCIE_MIMRXRDATA33", - "MIMRXWDATA42": "PCIE_MIMRXWDATA42", - "MIMTXWDATA50": "PCIE_MIMTXWDATA50", - "TRNRD121": "PCIE_TRNRD121", - "PLTRANSMITHOTRST": "PCIE_PLTRANSMITHOTRST", - "TRNRD20": "PCIE_TRNRD20", - "CFGLINKCONTROLRCB": "PCIE_CFGLINKCONTROLRCB", - "TRNRDLLPDATA27": "PCIE_TRNRDLLPDATA27", - "TRNTD54": "PCIE_TRNTD54", - "TRNTD1": "PCIE_TRNTD1", - "DBGVECA9": "PCIE_DBGVECA9", - "LL2LINKSTATUS3": "PCIE_LL2LINKSTATUS3", - "DBGVECA35": "PCIE_DBGVECA35", - "PIPETX6CHARISK1": "PCIE_PIPETX6CHARISK1", - "TRNTD94": "PCIE_TRNTD94", - "DBGVECA59": "PCIE_DBGVECA59", - "PIPERX3DATA8": "PCIE_PIPERX3DATA8", - "CFGLINKCONTROLCOMMONCLOCK": "PCIE_CFGLINKCONTROLCOMMONCLOCK", - "CFGPMRCVASREQL1N": "PCIE_CFGPMRCVASREQL1N", - "DRPDO7": "PCIE_DRPDO7", - "PIPETX3ELECIDLE": "PCIE_PIPETX3ELECIDLE", - "CFGERRTLPCPLHEADER2": "PCIE_CFGERRTLPCPLHEADER2", - "PIPERX7DATA9": "PCIE_PIPERX7DATA9", - "PIPERX5DATA11": "PCIE_PIPERX5DATA11", - "PIPETX7CHARISK0": "PCIE_PIPETX7CHARISK0", - "MIMRXRDATA17": "PCIE_MIMRXRDATA17", - "PIPERX6ELECIDLE": "PCIE_PIPERX6ELECIDLE", - "DBGVECB28": "PCIE_DBGVECB28", - "PLDBGVEC10": "PCIE_PLDBGVEC10", - "DBGVECA44": "PCIE_DBGVECA44", - "TRNTD103": "PCIE_TRNTD103", - "TRNRD51": "PCIE_TRNRD51", - "MIMTXRDATA16": "PCIE_MIMTXRDATA16", - "PLLTSSMSTATE0": "PCIE_PLLTSSMSTATE0", - "MIMRXRADDR3": "PCIE_MIMRXRADDR3", - "XILUNCONNOUT8": "PCIE_XILUNCONNOUT8", - "TL2ERRHDR48": "PCIE_TL2ERRHDR48", - "CFGERRAERHEADERLOG2": "PCIE_CFGERRAERHEADERLOG2", - "TL2ERRHDR3": "PCIE_TL2ERRHDR3", - "MIMTXWDATA26": "PCIE_MIMTXWDATA26", - "TRNRDLLPSRCRDY0": "PCIE_TRNRDLLPSRCRDY0", - "TRNRNPREQ": "PCIE_TRNRNPREQ", - "CFGDSN11": "PCIE_CFGDSN11", - "CFGMGMTDWADDR6": "PCIE_CFGMGMTDWADDR6", - "CFGERRTLPCPLHEADER22": "PCIE_CFGERRTLPCPLHEADER22", - "MIMTXRDATA59": "PCIE_MIMTXRDATA59", - "PMVENABLEN": "PCIE_PMVENABLEN", - "PIPERX4POLARITY": "PCIE_PIPERX4POLARITY", - "PIPERX2DATA8": "PCIE_PIPERX2DATA8", - "CFGERRNORECOVERYN": "PCIE_CFGERRNORECOVERYN", - "CFGINTERRUPTDI0": "PCIE_CFGINTERRUPTDI0", - "PIPERX1DATA12": "PCIE_PIPERX1DATA12", - "MIMRXRDATA23": "PCIE_MIMRXRDATA23", - "PIPERX4CHARISK1": "PCIE_PIPERX4CHARISK1", - "CFGERRAERHEADERLOG84": "PCIE_CFGERRAERHEADERLOG84", - "CFGMSGRECEIVEDERRNONFATAL": "PCIE_CFGMSGRECEIVEDERRNONFATAL", - "PIPETX3DATA8": "PCIE_PIPETX3DATA8", - "CFGFORCECOMMONCLOCKOFF": "PCIE_CFGFORCECOMMONCLOCKOFF", - "PIPERX5POLARITY": "PCIE_PIPERX5POLARITY", - "CMSTICKYRSTN": "PCIE_CMSTICKYRSTN", - "TRNTD101": "PCIE_TRNTD101", - "PIPETX5ELECIDLE": "PCIE_PIPETX5ELECIDLE", - "DBGVECA19": "PCIE_DBGVECA19", - "MIMRXWDATA5": "PCIE_MIMRXWDATA5", - "CFGMGMTDO13": "PCIE_CFGMGMTDO13", - "MIMTXWDATA52": "PCIE_MIMTXWDATA52", - "PLDIRECTEDLTSSMNEW3": "PCIE_PLDIRECTEDLTSSMNEW3", - "MIMRXWDATA67": "PCIE_MIMRXWDATA67", - "PIPETX4DATA2": "PCIE_PIPETX4DATA2", - "DBGVECA39": "PCIE_DBGVECA39", - "MIMRXRDATA26": "PCIE_MIMRXRDATA26", - "PLSELLNKWIDTH0": "PCIE_PLSELLNKWIDTH0", - "DBGVECB34": "PCIE_DBGVECB34", - "PIPERX2DATA11": "PCIE_PIPERX2DATA11", - "MIMRXWDATA16": "PCIE_MIMRXWDATA16", - "CFGPCIELINKSTATE0": "PCIE_CFGPCIELINKSTATE0", - "DRPWE": "PCIE_DRPWE", - "CFGMSGRECEIVEDASSERTINTB": "PCIE_CFGMSGRECEIVEDASSERTINTB", - "TRNTD55": "PCIE_TRNTD55", - "CFGAERROOTERRCORRERRREPORTINGEN": "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", - "TRNTD42": "PCIE_TRNTD42", - "MIMRXRDATA0": "PCIE_MIMRXRDATA0", - "PLDBGVEC5": "PCIE_PLDBGVEC5", - "CFGPCIECAPINTERRUPTMSGNUM1": "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", - "LL2LINKSTATUS0": "PCIE_LL2LINKSTATUS0", - "TL2ERRHDR11": "PCIE_TL2ERRHDR11", - "TRNTD13": "PCIE_TRNTD13", - "MIMTXRADDR5": "PCIE_MIMTXRADDR5", - "CFGMGMTDO19": "PCIE_CFGMGMTDO19", - "CFGTRANSACTIONADDR6": "PCIE_CFGTRANSACTIONADDR6", - "TRNTD70": "PCIE_TRNTD70", - "TRNTD48": "PCIE_TRNTD48", - "CFGMGMTDO15": "PCIE_CFGMGMTDO15", - "MIMTXWADDR7": "PCIE_MIMTXWADDR7", - "PIPERX7DATA14": "PCIE_PIPERX7DATA14", - "TRNRBARHIT1": "PCIE_TRNRBARHIT1", - "CFGERRTLPCPLHEADER18": "PCIE_CFGERRTLPCPLHEADER18", - "XILUNCONNOUT20": "PCIE_XILUNCONNOUT20", - "DBGVECB47": "PCIE_DBGVECB47", - "TRNTD44": "PCIE_TRNTD44", - "PIPERX6DATA4": "PCIE_PIPERX6DATA4", - "TRNTD98": "PCIE_TRNTD98", - "CFGERRAERHEADERLOG11": "PCIE_CFGERRAERHEADERLOG11", - "MIMRXWDATA3": "PCIE_MIMRXWDATA3", - "PIPERX7STATUS1": "PCIE_PIPERX7STATUS1", - "TRNTD123": "PCIE_TRNTD123", - "TRNFCPH3": "PCIE_TRNFCPH3", - "TRNRD25": "PCIE_TRNRD25", - "DBGVECA17": "PCIE_DBGVECA17", - "DBGVECA4": "PCIE_DBGVECA4", - "CFGINTERRUPTDO2": "PCIE_CFGINTERRUPTDO2", - "TRNRD74": "PCIE_TRNRD74", - "MIMTXRADDR12": "PCIE_MIMTXRADDR12", - "PIPERX4PHYSTATUS": "PCIE_PIPERX4PHYSTATUS", - "MIMTXRDATA4": "PCIE_MIMTXRDATA4", - "PIPERX2DATA9": "PCIE_PIPERX2DATA9", - "PIPETX6DATA8": "PCIE_PIPETX6DATA8", - "CFGERRMCBLOCKEDN": "PCIE_CFGERRMCBLOCKEDN", - "MIMTXWDATA22": "PCIE_MIMTXWDATA22", - "CFGAERROOTERRNONFATALERRRECEIVED": "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", - "MIMRXRDATA18": "PCIE_MIMRXRDATA18", - "MIMRXWADDR3": "PCIE_MIMRXWADDR3", - "TRNTD50": "PCIE_TRNTD50", - "PIPETX0DATA3": "PCIE_PIPETX0DATA3", - "TRNRD99": "PCIE_TRNRD99", - "CFGMGMTDO14": "PCIE_CFGMGMTDO14", - "TRNRD11": "PCIE_TRNRD11", - "PIPETX6DATA4": "PCIE_PIPETX6DATA4", - "PIPERX7POLARITY": "PCIE_PIPERX7POLARITY", - "PLDIRECTEDLINKCHANGE0": "PCIE_PLDIRECTEDLINKCHANGE0", - "TL2ERRHDR24": "PCIE_TL2ERRHDR24", - "MIMRXWDATA24": "PCIE_MIMRXWDATA24", - "PLINITIALLINKWIDTH1": "PCIE_PLINITIALLINKWIDTH1", - "DBGVECB5": "PCIE_DBGVECB5", - "CFGERRAERHEADERLOG89": "PCIE_CFGERRAERHEADERLOG89", - "CFGPMRCVREQACKN": "PCIE_CFGPMRCVREQACKN", - "DBGVECB18": "PCIE_DBGVECB18", - "CFGMGMTDI2": "PCIE_CFGMGMTDI2", - "EDTCHANNELSIN5": "PCIE_EDTCHANNELSIN5", - "TRNTSOF": "PCIE_TRNTSOF", - "PMVSELECT2": "PCIE_PMVSELECT2", - "PIPETX6DATA2": "PCIE_PIPETX6DATA2", - "PIPERX7STATUS0": "PCIE_PIPERX7STATUS0", - "CFGDSBUSNUMBER7": "PCIE_CFGDSBUSNUMBER7", - "TRNRD125": "PCIE_TRNRD125", - "TRNTDLLPDSTRDY": "PCIE_TRNTDLLPDSTRDY", - "TRNRD127": "PCIE_TRNRD127", - "TRNTDLLPDATA10": "PCIE_TRNTDLLPDATA10", - "TRNFCNPH1": "PCIE_TRNFCNPH1", - "CFGMGMTDO25": "PCIE_CFGMGMTDO25", - "MIMRXRDATA16": "PCIE_MIMRXRDATA16", - "PIPERX6CHANISALIGNED": "PCIE_PIPERX6CHANISALIGNED", - "PIPETX5DATA8": "PCIE_PIPETX5DATA8", - "LL2PROTOCOLERR": "PCIE_LL2PROTOCOLERR", - "CFGVENDID2": "PCIE_CFGVENDID2", - "TRNRD116": "PCIE_TRNRD116", - "TRNRD30": "PCIE_TRNRD30", - "CFGSUBSYSID14": "PCIE_CFGSUBSYSID14", - "PIPETX3CHARISK1": "PCIE_PIPETX3CHARISK1", - "CFGERRAERHEADERLOG127": "PCIE_CFGERRAERHEADERLOG127", - "CFGDSN13": "PCIE_CFGDSN13", - "MIMRXWDATA35": "PCIE_MIMRXWDATA35", - "CFGINTERRUPTMSIXENABLE": "PCIE_CFGINTERRUPTMSIXENABLE", - "CFGERRTLPCPLHEADER25": "PCIE_CFGERRTLPCPLHEADER25", - "CFGDEVID12": "PCIE_CFGDEVID12", - "PIPERX4DATA2": "PCIE_PIPERX4DATA2", - "TRNRD82": "PCIE_TRNRD82", - "CFGERRAERHEADERLOG107": "PCIE_CFGERRAERHEADERLOG107", - "MIMTXRADDR8": "PCIE_MIMTXRADDR8", - "TRNTD75": "PCIE_TRNTD75", - "EDTCHANNELSIN8": "PCIE_EDTCHANNELSIN8", - "MIMTXRDATA58": "PCIE_MIMTXRDATA58", - "PIPERX3DATA1": "PCIE_PIPERX3DATA1", - "TRNTD116": "PCIE_TRNTD116", - "USERCLK": "PCIE_USERCLK", - "PIPETX0DATA14": "PCIE_PIPETX0DATA14", - "PIPERX6DATA15": "PCIE_PIPERX6DATA15", - "TRNTECRCGEN": "PCIE_TRNTECRCGEN", - "CFGERRTLPCPLHEADER24": "PCIE_CFGERRTLPCPLHEADER24", - "TRNRDLLPDATA63": "PCIE_TRNRDLLPDATA63", - "TL2ERRHDR39": "PCIE_TL2ERRHDR39", - "TRNTD99": "PCIE_TRNTD99", - "CFGTRANSACTIONADDR0": "PCIE_CFGTRANSACTIONADDR0", - "MIMRXWDATA4": "PCIE_MIMRXWDATA4", - "DBGVECC2": "PCIE_DBGVECC2", - "LL2BADDLLPERR": "PCIE_LL2BADDLLPERR", - "TRNFCCPLD0": "PCIE_TRNFCCPLD0", - "DBGVECA47": "PCIE_DBGVECA47", - "DBGVECB29": "PCIE_DBGVECB29", - "TRNTD31": "PCIE_TRNTD31", - "PIPERX2DATA4": "PCIE_PIPERX2DATA4", - "MIMRXRDATA63": "PCIE_MIMRXRDATA63", - "PL2DIRECTEDLSTATE4": "PCIE_PL2DIRECTEDLSTATE4", - "CFGSUBSYSID10": "PCIE_CFGSUBSYSID10", - "PIPETX3DATA4": "PCIE_PIPETX3DATA4", - "MIMRXRDATA55": "PCIE_MIMRXRDATA55", - "PIPETX2CHARISK0": "PCIE_PIPETX2CHARISK0", - "DBGVECA61": "PCIE_DBGVECA61", - "PIPETX4DATA5": "PCIE_PIPETX4DATA5", - "TRNFCNPD6": "PCIE_TRNFCNPD6", - "PIPERX3DATA7": "PCIE_PIPERX3DATA7", - "TRNRD54": "PCIE_TRNRD54", - "MIMRXRDATA2": "PCIE_MIMRXRDATA2", - "CFGERRAERHEADERLOG111": "PCIE_CFGERRAERHEADERLOG111", - "TRNLNKUP": "PCIE_TRNLNKUP", - "TRNTD77": "PCIE_TRNTD77", - "DBGVECA63": "PCIE_DBGVECA63", - "PIPERX5STATUS2": "PCIE_PIPERX5STATUS2", - "PIPETX6DATA5": "PCIE_PIPETX6DATA5", - "MIMTXRADDR10": "PCIE_MIMTXRADDR10", - "TL2ERRHDR61": "PCIE_TL2ERRHDR61", - "DBGVECB54": "PCIE_DBGVECB54", - "TRNFCNPH6": "PCIE_TRNFCNPH6", - "TL2ERRHDR31": "PCIE_TL2ERRHDR31", - "PIPERX5PHYSTATUS": "PCIE_PIPERX5PHYSTATUS", - "DBGVECC4": "PCIE_DBGVECC4", - "PIPETXMARGIN1": "PCIE_PIPETXMARGIN1", - "CFGERRAERHEADERLOG30": "PCIE_CFGERRAERHEADERLOG30", - "PIPERX6DATA0": "PCIE_PIPERX6DATA0", - "XILUNCONNOUT33": "PCIE_XILUNCONNOUT33", - "TRNFCCPLD6": "PCIE_TRNFCCPLD6", - "PIPERX1DATA8": "PCIE_PIPERX1DATA8", - "TRNRD35": "PCIE_TRNRD35", - "XILUNCONNOUT36": "PCIE_XILUNCONNOUT36", - "CFGERRAERHEADERLOG60": "PCIE_CFGERRAERHEADERLOG60", - "PIPERX0DATA4": "PCIE_PIPERX0DATA4", - "CFGERRTLPCPLHEADER34": "PCIE_CFGERRTLPCPLHEADER34", - "TRNRD37": "PCIE_TRNRD37", - "PIPETX5DATA2": "PCIE_PIPETX5DATA2", - "TRNRD19": "PCIE_TRNRD19", - "MIMRXWDATA34": "PCIE_MIMRXWDATA34", - "CFGDSFUNCTIONNUMBER1": "PCIE_CFGDSFUNCTIONNUMBER1", - "TRNRD0": "PCIE_TRNRD0", - "CFGDSN48": "PCIE_CFGDSN48", - "TL2ASPMSUSPENDCREDITCHECKOK": "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", - "TRNTD12": "PCIE_TRNTD12", - "CFGDSDEVICENUMBER2": "PCIE_CFGDSDEVICENUMBER2", - "PIPERX0DATA10": "PCIE_PIPERX0DATA10", - "CFGERRAERHEADERLOG28": "PCIE_CFGERRAERHEADERLOG28", - "TRNTD30": "PCIE_TRNTD30", - "PIPETX2DATA7": "PCIE_PIPETX2DATA7", - "DBGVECA60": "PCIE_DBGVECA60", - "CFGMGMTDO26": "PCIE_CFGMGMTDO26", - "CFGROOTCONTROLSYSERRCORRERREN": "PCIE_CFGROOTCONTROLSYSERRCORRERREN", - "PLDBGVEC1": "PCIE_PLDBGVEC1", - "TRNTDLLPDATA26": "PCIE_TRNTDLLPDATA26", - "MIMRXRADDR9": "PCIE_MIMRXRADDR9", - "PIPERX3DATA11": "PCIE_PIPERX3DATA11", - "DBGVECA21": "PCIE_DBGVECA21", - "DRPCLK": "PCIE_DRPCLK", - "MIMRXWADDR12": "PCIE_MIMRXWADDR12", - "TRNFCPD2": "PCIE_TRNFCPD2", - "PIPERX6DATA3": "PCIE_PIPERX6DATA3", - "TRNRD108": "PCIE_TRNRD108", - "MIMRXRDATA58": "PCIE_MIMRXRDATA58", - "TRNTD73": "PCIE_TRNTD73", - "TRNRD104": "PCIE_TRNRD104", - "CFGPORTNUMBER5": "PCIE_CFGPORTNUMBER5", - "CFGVENDID12": "PCIE_CFGVENDID12", - "CFGMSGDATA0": "PCIE_CFGMSGDATA0", - "CFGSUBSYSVENDID0": "PCIE_CFGSUBSYSVENDID0", - "CFGERRAERHEADERLOG86": "PCIE_CFGERRAERHEADERLOG86", - "CFGDSN30": "PCIE_CFGDSN30", - "PIPERX5DATA3": "PCIE_PIPERX5DATA3", - "PIPERX0CHARISK1": "PCIE_PIPERX0CHARISK1", - "TRNRD58": "PCIE_TRNRD58", - "TRNRDLLPDATA61": "PCIE_TRNRDLLPDATA61", - "CFGMSGDATA3": "PCIE_CFGMSGDATA3", - "TRNTD111": "PCIE_TRNTD111", - "MIMRXWADDR9": "PCIE_MIMRXWADDR9", - "TRNTD24": "PCIE_TRNTD24", - "CFGERRAERHEADERLOG55": "PCIE_CFGERRAERHEADERLOG55", - "PIPETXDEEMPH": "PCIE_PIPETXDEEMPH", - "MIMRXWDATA15": "PCIE_MIMRXWDATA15", - "MIMTXRDATA32": "PCIE_MIMTXRDATA32", - "CFGMGMTDI3": "PCIE_CFGMGMTDI3", - "CFGSUBSYSVENDID6": "PCIE_CFGSUBSYSVENDID6", - "CFGINTERRUPTMSIENABLE": "PCIE_CFGINTERRUPTMSIENABLE", - "PIPETX7POWERDOWN1": "PCIE_PIPETX7POWERDOWN1", - "PIPETX4DATA8": "PCIE_PIPETX4DATA8", - "MIMRXWADDR4": "PCIE_MIMRXWADDR4", - "CFGMGMTDWADDR7": "PCIE_CFGMGMTDWADDR7", - "CFGDEVCONTROL2ATOMICEGRESSBLOCK": "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", - "DBGVECB37": "PCIE_DBGVECB37", - "PIPERX1DATA6": "PCIE_PIPERX1DATA6", - "CFGCOMMANDMEMENABLE": "PCIE_CFGCOMMANDMEMENABLE", - "MIMRXWDATA39": "PCIE_MIMRXWDATA39", - "EDTCHANNELSOUT2": "PCIE_EDTCHANNELSOUT2", - "PIPERX0DATA3": "PCIE_PIPERX0DATA3", - "PIPERX4DATA6": "PCIE_PIPERX4DATA6", - "MIMRXRDATA54": "PCIE_MIMRXRDATA54", - "CFGERRAERHEADERLOG115": "PCIE_CFGERRAERHEADERLOG115", - "MIMRXRDATA30": "PCIE_MIMRXRDATA30", - "MIMTXWDATA15": "PCIE_MIMTXWDATA15", - "PIPERX0DATA7": "PCIE_PIPERX0DATA7", - "TRNFCPD0": "PCIE_TRNFCPD0", - "PIPETX3DATA15": "PCIE_PIPETX3DATA15", - "MIMRXWDATA47": "PCIE_MIMRXWDATA47", - "MIMRXRDATA21": "PCIE_MIMRXRDATA21", - "PMVDIVIDE0": "PCIE_PMVDIVIDE0", - "CFGERRAERHEADERLOG50": "PCIE_CFGERRAERHEADERLOG50", - "PIPERX6PHYSTATUS": "PCIE_PIPERX6PHYSTATUS", - "PIPERX7VALID": "PCIE_PIPERX7VALID", - "CFGMGMTDO9": "PCIE_CFGMGMTDO9", - "TRNTDLLPDATA4": "PCIE_TRNTDLLPDATA4", - "PIPERX2DATA15": "PCIE_PIPERX2DATA15", - "CFGTRANSACTIONADDR2": "PCIE_CFGTRANSACTIONADDR2", - "MIMTXRDATA66": "PCIE_MIMTXRDATA66", - "CFGFORCEEXTENDEDSYNCON": "PCIE_CFGFORCEEXTENDEDSYNCON", - "PIPETX3DATA2": "PCIE_PIPETX3DATA2", - "PIPETX6DATA7": "PCIE_PIPETX6DATA7", - "CFGVCTCVCMAP2": "PCIE_CFGVCTCVCMAP2", - "CFGERRAERHEADERLOG81": "PCIE_CFGERRAERHEADERLOG81", - "CFGERRAERHEADERLOG14": "PCIE_CFGERRAERHEADERLOG14", - "CFGSUBSYSVENDID3": "PCIE_CFGSUBSYSVENDID3", - "PIPETX1DATA3": "PCIE_PIPETX1DATA3", - "TRNTBUFAV5": "PCIE_TRNTBUFAV5", - "TL2ERRHDR4": "PCIE_TL2ERRHDR4", - "TRNRD103": "PCIE_TRNRD103", - "CFGREVID7": "PCIE_CFGREVID7", - "CFGDSN63": "PCIE_CFGDSN63", - "TRNRDLLPDATA10": "PCIE_TRNRDLLPDATA10", - "MIMTXRDATA38": "PCIE_MIMTXRDATA38", - "CFGDSN18": "PCIE_CFGDSN18", - "CFGERRAERHEADERLOG20": "PCIE_CFGERRAERHEADERLOG20", - "CFGMGMTDI0": "PCIE_CFGMGMTDI0", - "MIMRXRDATA66": "PCIE_MIMRXRDATA66", - "MIMRXRDATA47": "PCIE_MIMRXRDATA47", - "LL2RECEIVERERR": "PCIE_LL2RECEIVERERR", - "DRPDI6": "PCIE_DRPDI6", - "CFGDSN45": "PCIE_CFGDSN45", - "CFGMGMTDI24": "PCIE_CFGMGMTDI24", - "CFGLINKSTATUSDLLACTIVE": "PCIE_CFGLINKSTATUSDLLACTIVE", - "DBGVECB1": "PCIE_DBGVECB1", - "CFGMSGDATA1": "PCIE_CFGMSGDATA1", - "TRNTD28": "PCIE_TRNTD28", - "TRNRD10": "PCIE_TRNRD10", - "TL2ERRHDR9": "PCIE_TL2ERRHDR9", - "MIMTXWDATA47": "PCIE_MIMTXWDATA47", - "TRNRBARHIT5": "PCIE_TRNRBARHIT5", - "PIPETX3DATA0": "PCIE_PIPETX3DATA0", - "TRNRDLLPDATA52": "PCIE_TRNRDLLPDATA52", - "TRNTEOF": "PCIE_TRNTEOF", - "TRNRREM0": "PCIE_TRNRREM0", - "MIMTXRDATA61": "PCIE_MIMTXRDATA61", - "CFGLINKSTATUSBANDWIDTHSTATUS": "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", - "TRNRD107": "PCIE_TRNRD107", - "CFGERRTLPCPLHEADER28": "PCIE_CFGERRTLPCPLHEADER28", - "PIPERX0DATA1": "PCIE_PIPERX0DATA1", - "MIMTXWDATA53": "PCIE_MIMTXWDATA53", - "TRNRD87": "PCIE_TRNRD87", - "PLDIRECTEDLTSSMNEW1": "PCIE_PLDIRECTEDLTSSMNEW1", - "PIPETX6DATA11": "PCIE_PIPETX6DATA11", - "TRNTD81": "PCIE_TRNTD81", - "TRNFCPD10": "PCIE_TRNFCPD10", - "TRNTD71": "PCIE_TRNTD71", - "CFGERRAERHEADERLOG96": "PCIE_CFGERRAERHEADERLOG96", - "CFGDSDEVICENUMBER1": "PCIE_CFGDSDEVICENUMBER1", - "PIPERX7DATA13": "PCIE_PIPERX7DATA13", - "TL2ERRHDR47": "PCIE_TL2ERRHDR47", - "EDTCHANNELSOUT5": "PCIE_EDTCHANNELSOUT5", - "PIPETX0DATA6": "PCIE_PIPETX0DATA6", - "CFGDSN1": "PCIE_CFGDSN1", - "CFGERRAERHEADERLOG108": "PCIE_CFGERRAERHEADERLOG108", - "EDTCHANNELSIN7": "PCIE_EDTCHANNELSIN7", - "CFGPORTNUMBER1": "PCIE_CFGPORTNUMBER1", - "TRNFCSEL0": "PCIE_TRNFCSEL0", - "CFGMGMTDO6": "PCIE_CFGMGMTDO6", - "PIPETX1DATA14": "PCIE_PIPETX1DATA14", - "PIPETX4DATA14": "PCIE_PIPETX4DATA14", - "TRNRDLLPDATA31": "PCIE_TRNRDLLPDATA31", - "DBGVECA22": "PCIE_DBGVECA22", - "CFGDSN51": "PCIE_CFGDSN51", - "TRNTDLLPDATA15": "PCIE_TRNTDLLPDATA15", - "TRNTD35": "PCIE_TRNTD35", - "TL2ERRHDR52": "PCIE_TL2ERRHDR52", - "DBGVECC0": "PCIE_DBGVECC0", - "CFGDEVCONTROLMAXPAYLOAD0": "PCIE_CFGDEVCONTROLMAXPAYLOAD0", - "TRNTD8": "PCIE_TRNTD8", - "LL2TFCINIT1SEQ": "PCIE_LL2TFCINIT1SEQ", - "XILUNCONNOUT4": "PCIE_XILUNCONNOUT4", - "MIMRXRADDR12": "PCIE_MIMRXRADDR12", - "MIMRXWDATA51": "PCIE_MIMRXWDATA51", - "CFGERRAERHEADERLOG48": "PCIE_CFGERRAERHEADERLOG48", - "PIPERX5DATA7": "PCIE_PIPERX5DATA7", - "PIPERX5DATA0": "PCIE_PIPERX5DATA0", - "CFGINTERRUPTASSERTN": "PCIE_CFGINTERRUPTASSERTN", - "TRNRBARHIT3": "PCIE_TRNRBARHIT3", - "TRNRD2": "PCIE_TRNRD2", - "TRNTDLLPDATA3": "PCIE_TRNTDLLPDATA3", - "TL2ERRHDR56": "PCIE_TL2ERRHDR56", - "CFGERRAERHEADERLOG4": "PCIE_CFGERRAERHEADERLOG4", - "MIMRXRDATA28": "PCIE_MIMRXRDATA28", - "MIMTXRDATA60": "PCIE_MIMTXRDATA60", - "PIPERX4DATA5": "PCIE_PIPERX4DATA5", - "PIPERX7DATA6": "PCIE_PIPERX7DATA6", - "TRNRD126": "PCIE_TRNRD126", - "PIPETX6DATA0": "PCIE_PIPETX6DATA0", - "DRPDI0": "PCIE_DRPDI0", - "CFGERRAERHEADERLOG6": "PCIE_CFGERRAERHEADERLOG6", - "CFGVCTCVCMAP6": "PCIE_CFGVCTCVCMAP6", - "TRNFCCPLD11": "PCIE_TRNFCCPLD11", - "CFGDEVCONTROLPHANTOMEN": "PCIE_CFGDEVCONTROLPHANTOMEN", - "CFGERRAERHEADERLOG109": "PCIE_CFGERRAERHEADERLOG109", - "MIMTXWDATA63": "PCIE_MIMTXWDATA63", - "MIMRXRDATA53": "PCIE_MIMRXRDATA53", - "CFGDSN20": "PCIE_CFGDSN20", - "PIPERX3ELECIDLE": "PCIE_PIPERX3ELECIDLE", - "CFGDSN4": "PCIE_CFGDSN4", - "CFGMSGRECEIVEDERRCOR": "PCIE_CFGMSGRECEIVEDERRCOR", - "DBGVECB27": "PCIE_DBGVECB27", - "CFGERRTLPCPLHEADER31": "PCIE_CFGERRTLPCPLHEADER31", - "CFGERRAERHEADERLOG8": "PCIE_CFGERRAERHEADERLOG8", - "TL2ERRHDR7": "PCIE_TL2ERRHDR7", - "MIMTXWDATA65": "PCIE_MIMTXWDATA65", - "DBGVECB57": "PCIE_DBGVECB57", - "PIPETX2POWERDOWN1": "PCIE_PIPETX2POWERDOWN1", - "MIMTXRDATA64": "PCIE_MIMTXRDATA64", - "TRNTD46": "PCIE_TRNTD46", - "PIPERX3DATA9": "PCIE_PIPERX3DATA9", - "PL2DIRECTEDLSTATE1": "PCIE_PL2DIRECTEDLSTATE1", - "CFGPMTURNOFFOKN": "PCIE_CFGPMTURNOFFOKN", - "MIMRXWDATA58": "PCIE_MIMRXWDATA58", - "PIPERX2DATA14": "PCIE_PIPERX2DATA14", - "DRPADDR4": "PCIE_DRPADDR4", - "TRNTDSTRDY3": "PCIE_TRNTDSTRDY3", - "MIMTXWDATA38": "PCIE_MIMTXWDATA38", - "MIMRXREN": "PCIE_MIMRXREN", - "MIMTXRDATA11": "PCIE_MIMTXRDATA11", - "MIMTXWADDR6": "PCIE_MIMTXWADDR6", - "CFGMGMTDO29": "PCIE_CFGMGMTDO29", - "TRNRD113": "PCIE_TRNRD113", - "MIMRXWDATA41": "PCIE_MIMRXWDATA41", - "TRNTERRDROP": "PCIE_TRNTERRDROP", - "TRNRDLLPDATA49": "PCIE_TRNRDLLPDATA49", - "CFGSUBSYSVENDID9": "PCIE_CFGSUBSYSVENDID9", - "XILUNCONNOUT30": "PCIE_XILUNCONNOUT30", - "TRNRSRCDSC": "PCIE_TRNRSRCDSC", - "TRNRD71": "PCIE_TRNRD71", - "PIPETX1DATA13": "PCIE_PIPETX1DATA13", - "TRNRD62": "PCIE_TRNRD62", - "CFGDSN28": "PCIE_CFGDSN28", - "CFGSUBSYSVENDID13": "PCIE_CFGSUBSYSVENDID13", - "CFGMSGRECEIVEDPMASNAK": "PCIE_CFGMSGRECEIVEDPMASNAK", - "CFGDSN39": "PCIE_CFGDSN39", - "CFGERRTLPCPLHEADER33": "PCIE_CFGERRTLPCPLHEADER33", - "CFGDSN3": "PCIE_CFGDSN3", - "DRPDO9": "PCIE_DRPDO9", - "DBGVECA37": "PCIE_DBGVECA37", - "PIPETX0DATA8": "PCIE_PIPETX0DATA8", - "CFGINTERRUPTMMENABLE2": "PCIE_CFGINTERRUPTMMENABLE2", - "PIPERX6DATA1": "PCIE_PIPERX6DATA1", - "TRNRDLLPDATA1": "PCIE_TRNRDLLPDATA1", - "TL2ASPMSUSPENDREQ": "PCIE_TL2ASPMSUSPENDREQ", - "PIPETX1DATA10": "PCIE_PIPETX1DATA10", - "PIPETX7ELECIDLE": "PCIE_PIPETX7ELECIDLE", - "EDTCHANNELSIN2": "PCIE_EDTCHANNELSIN2", - "CFGERRAERHEADERLOG58": "PCIE_CFGERRAERHEADERLOG58", - "TRNRDLLPDATA60": "PCIE_TRNRDLLPDATA60", - "TRNRERRFWD": "PCIE_TRNRERRFWD", - "CFGERRAERHEADERLOG117": "PCIE_CFGERRAERHEADERLOG117", - "DBGVECA2": "PCIE_DBGVECA2", - "DBGVECB39": "PCIE_DBGVECB39", - "PIPETX3POWERDOWN1": "PCIE_PIPETX3POWERDOWN1", - "MIMTXRDATA56": "PCIE_MIMTXRDATA56", - "TRNRD39": "PCIE_TRNRD39", - "MIMRXWADDR7": "PCIE_MIMRXWADDR7", - "EDTCHANNELSOUT3": "PCIE_EDTCHANNELSOUT3", - "PIPETX4DATA1": "PCIE_PIPETX4DATA1", - "PIPERX4DATA8": "PCIE_PIPERX4DATA8", - "PIPETX7DATA2": "PCIE_PIPETX7DATA2", - "TRNFCPD3": "PCIE_TRNFCPD3", - "PIPETX1ELECIDLE": "PCIE_PIPETX1ELECIDLE", - "PIPERX7CHARISK1": "PCIE_PIPERX7CHARISK1", - "PIPERX1STATUS0": "PCIE_PIPERX1STATUS0", - "TL2ERRHDR33": "PCIE_TL2ERRHDR33", - "CFGMGMTDI23": "PCIE_CFGMGMTDI23", - "CFGERRAERHEADERLOG122": "PCIE_CFGERRAERHEADERLOG122", - "CFGTRANSACTIONADDR1": "PCIE_CFGTRANSACTIONADDR1", - "PIPERX0DATA12": "PCIE_PIPERX0DATA12", - "TRNRD106": "PCIE_TRNRD106", - "TRNFCCPLH6": "PCIE_TRNFCCPLH6", - "CFGPORTNUMBER2": "PCIE_CFGPORTNUMBER2", - "CFGSUBSYSVENDID8": "PCIE_CFGSUBSYSVENDID8", - "CFGPMRCVENTERL1N": "PCIE_CFGPMRCVENTERL1N", - "TRNRDLLPDATA56": "PCIE_TRNRDLLPDATA56", - "MIMTXWDATA8": "PCIE_MIMTXWDATA8", - "PLLANEREVERSALMODE0": "PCIE_PLLANEREVERSALMODE0", - "CFGINTERRUPTDI3": "PCIE_CFGINTERRUPTDI3", - "MIMTXWDATA68": "PCIE_MIMTXWDATA68", - "CFGMGMTDO17": "PCIE_CFGMGMTDO17", - "MIMRXRADDR7": "PCIE_MIMRXRADDR7", - "CFGERRAERHEADERLOG70": "PCIE_CFGERRAERHEADERLOG70", - "XILUNCONNOUT27": "PCIE_XILUNCONNOUT27", - "PIPERX0STATUS0": "PCIE_PIPERX0STATUS0", - "CFGTRNPENDINGN": "PCIE_CFGTRNPENDINGN", - "TRNTDSTRDY2": "PCIE_TRNTDSTRDY2", - "DBGVECA46": "PCIE_DBGVECA46", - "PIPERX3DATA4": "PCIE_PIPERX3DATA4", - "PLTXPMSTATE1": "PCIE_PLTXPMSTATE1", - "TRNRDLLPDATA53": "PCIE_TRNRDLLPDATA53", - "MIMRXWDATA54": "PCIE_MIMRXWDATA54", - "CFGAERINTERRUPTMSGNUM1": "PCIE_CFGAERINTERRUPTMSGNUM1", - "PIPETX2DATA12": "PCIE_PIPETX2DATA12", - "DBGVECB24": "PCIE_DBGVECB24", - "PIPERX2DATA6": "PCIE_PIPERX2DATA6", - "TRNRD26": "PCIE_TRNRD26", - "DRPDO12": "PCIE_DRPDO12", - "CFGMGMTDI18": "PCIE_CFGMGMTDI18", - "CFGPORTNUMBER3": "PCIE_CFGPORTNUMBER3", - "CFGERRACSN": "PCIE_CFGERRACSN", - "CFGMSGRECEIVEDPMPME": "PCIE_CFGMSGRECEIVEDPMPME", - "PIPERX2DATA10": "PCIE_PIPERX2DATA10", - "CFGMGMTDI7": "PCIE_CFGMGMTDI7", - "PLTXPMSTATE0": "PCIE_PLTXPMSTATE0", - "TRNFCCPLD8": "PCIE_TRNFCCPLD8", - "DBGVECB49": "PCIE_DBGVECB49", - "CFGDSN50": "PCIE_CFGDSN50", - "TRNRD44": "PCIE_TRNRD44", - "MIMTXRADDR6": "PCIE_MIMTXRADDR6", - "PLDIRECTEDLINKWIDTH1": "PCIE_PLDIRECTEDLINKWIDTH1", - "CFGMSGDATA4": "PCIE_CFGMSGDATA4", - "CFGERRPOSTEDN": "PCIE_CFGERRPOSTEDN", - "TRNREOF": "PCIE_TRNREOF", - "TRNRD45": "PCIE_TRNRD45", - "MIMTXRDATA31": "PCIE_MIMTXRDATA31", - "CFGDSN61": "PCIE_CFGDSN61", - "PIPETX1DATA2": "PCIE_PIPETX1DATA2", - "DRPDO2": "PCIE_DRPDO2", - "CFGDEVCONTROLNOSNOOPEN": "PCIE_CFGDEVCONTROLNOSNOOPEN", - "TRNRDLLPDATA15": "PCIE_TRNRDLLPDATA15", - "PIPERX5DATA12": "PCIE_PIPERX5DATA12", - "MIMTXRDATA26": "PCIE_MIMTXRDATA26", - "CFGERRAERHEADERLOG3": "PCIE_CFGERRAERHEADERLOG3", - "PIPETX7CHARISK1": "PCIE_PIPETX7CHARISK1", - "TRNRDLLPDATA4": "PCIE_TRNRDLLPDATA4", - "CFGERRAERHEADERLOGSETN": "PCIE_CFGERRAERHEADERLOGSETN", - "TRNTD60": "PCIE_TRNTD60", - "TRNFCPH6": "PCIE_TRNFCPH6", - "MIMTXRDATA48": "PCIE_MIMTXRDATA48", - "CFGMSGDATA8": "PCIE_CFGMSGDATA8", - "TRNTD58": "PCIE_TRNTD58", - "DBGVECA23": "PCIE_DBGVECA23", - "TRNRD102": "PCIE_TRNRD102", - "PIPETX4CHARISK0": "PCIE_PIPETX4CHARISK0", - "TL2ERRHDR49": "PCIE_TL2ERRHDR49", - "PIPERX1POLARITY": "PCIE_PIPERX1POLARITY", - "TRNFCCPLD2": "PCIE_TRNFCCPLD2", - "MIMRXRADDR4": "PCIE_MIMRXRADDR4", - "TRNRD6": "PCIE_TRNRD6", - "PIPERX1DATA13": "PCIE_PIPERX1DATA13", - "CFGMSGRECEIVEDUNLOCK": "PCIE_CFGMSGRECEIVEDUNLOCK", - "DBGVECB36": "PCIE_DBGVECB36", - "TRNTDLLPDATA24": "PCIE_TRNTDLLPDATA24", - "MIMTXWDATA44": "PCIE_MIMTXWDATA44", - "CFGERRAERHEADERLOG19": "PCIE_CFGERRAERHEADERLOG19", - "DBGVECA11": "PCIE_DBGVECA11", - "PIPETX7DATA7": "PCIE_PIPETX7DATA7", - "PIPERX3PHYSTATUS": "PCIE_PIPERX3PHYSTATUS", - "XILUNCONNOUT11": "PCIE_XILUNCONNOUT11", - "TRNRD83": "PCIE_TRNRD83", - "CFGAERROOTERRFATALERRREPORTINGEN": "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", - "TRNRD101": "PCIE_TRNRD101", - "CFGDEVID0": "PCIE_CFGDEVID0", - "TRNRD73": "PCIE_TRNRD73", - "PIPETX6DATA14": "PCIE_PIPETX6DATA14", - "CFGDEVID1": "PCIE_CFGDEVID1", - "CFGERRAERHEADERLOG78": "PCIE_CFGERRAERHEADERLOG78", - "PIPETX5CHARISK1": "PCIE_PIPETX5CHARISK1", - "CFGERRTLPCPLHEADER9": "PCIE_CFGERRTLPCPLHEADER9", - "TL2ERRHDR16": "PCIE_TL2ERRHDR16", - "TL2ERRHDR8": "PCIE_TL2ERRHDR8", - "PIPETX5DATA15": "PCIE_PIPETX5DATA15", - "CFGERRAERHEADERLOG29": "PCIE_CFGERRAERHEADERLOG29", - "PIPETX4DATA4": "PCIE_PIPETX4DATA4", - "PIPERX4STATUS2": "PCIE_PIPERX4STATUS2", - "CFGERRTLPCPLHEADER42": "PCIE_CFGERRTLPCPLHEADER42", - "PIPETX4DATA3": "PCIE_PIPETX4DATA3", - "TRNTD56": "PCIE_TRNTD56", - "PIPERX3DATA13": "PCIE_PIPERX3DATA13", - "MIMTXRDATA39": "PCIE_MIMTXRDATA39", - "CFGERRAERHEADERLOG125": "PCIE_CFGERRAERHEADERLOG125", - "CFGERRAERHEADERLOG77": "PCIE_CFGERRAERHEADERLOG77", - "TRNFCCPLH7": "PCIE_TRNFCCPLH7", - "TRNRD93": "PCIE_TRNRD93", - "TRNTD59": "PCIE_TRNTD59", - "PIPETX2DATA1": "PCIE_PIPETX2DATA1", - "PIPERX7DATA15": "PCIE_PIPERX7DATA15", - "CFGLINKSTATUSNEGOTIATEDWIDTH2": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", - "PIPERX1DATA11": "PCIE_PIPERX1DATA11", - "MIMRXRDATA65": "PCIE_MIMRXRDATA65", - "CFGERRAERHEADERLOG51": "PCIE_CFGERRAERHEADERLOG51", - "PIPETX6DATA15": "PCIE_PIPETX6DATA15", - "TRNRDLLPDATA51": "PCIE_TRNRDLLPDATA51", - "MIMRXWDATA8": "PCIE_MIMRXWDATA8", - "XILUNCONNOUT12": "PCIE_XILUNCONNOUT12", - "CFGERRAERHEADERLOG49": "PCIE_CFGERRAERHEADERLOG49", - "CFGDEVID7": "PCIE_CFGDEVID7", - "TRNTD36": "PCIE_TRNTD36", - "PLLTSSMSTATE2": "PCIE_PLLTSSMSTATE2", - "PIPETX2COMPLIANCE": "PCIE_PIPETX2COMPLIANCE", - "TRNRD111": "PCIE_TRNRD111", - "DBGSCLRG": "PCIE_DBGSCLRG", - "TL2ERRHDR28": "PCIE_TL2ERRHDR28", - "TRNRDLLPDATA8": "PCIE_TRNRDLLPDATA8", - "TRNTD68": "PCIE_TRNTD68", - "PIPERX3DATA5": "PCIE_PIPERX3DATA5", - "MIMRXRDATA42": "PCIE_MIMRXRDATA42", - "MIMRXRADDR10": "PCIE_MIMRXRADDR10", - "CFGMSGRECEIVEDASSERTINTD": "PCIE_CFGMSGRECEIVEDASSERTINTD", - "TRNRD16": "PCIE_TRNRD16", - "MIMRXRDATA25": "PCIE_MIMRXRDATA25", - "CFGPORTNUMBER4": "PCIE_CFGPORTNUMBER4", - "CFGMSGRECEIVEDDEASSERTINTB": "PCIE_CFGMSGRECEIVEDDEASSERTINTB", - "DBGVECB46": "PCIE_DBGVECB46", - "PIPERX6DATA13": "PCIE_PIPERX6DATA13", - "PIPETX3DATA6": "PCIE_PIPETX3DATA6", - "PLLINKPARTNERGEN2SUPPORTED": "PCIE_PLLINKPARTNERGEN2SUPPORTED", - "CFGLINKCONTROLHWAUTOWIDTHDIS": "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", - "TRNTCFGGNT": "PCIE_TRNTCFGGNT", - "PIPERX0DATA15": "PCIE_PIPERX0DATA15", - "TRNTD22": "PCIE_TRNTD22", - "MIMTXWADDR8": "PCIE_MIMTXWADDR8", - "CFGDEVCONTROLMAXREADREQ0": "PCIE_CFGDEVCONTROLMAXREADREQ0", - "CFGDEVID13": "PCIE_CFGDEVID13", - "CFGERRTLPCPLHEADER8": "PCIE_CFGERRTLPCPLHEADER8", - "PIPETX4DATA15": "PCIE_PIPETX4DATA15", - "PIPERX1CHARISK0": "PCIE_PIPERX1CHARISK0", - "TRNRD97": "PCIE_TRNRD97", - "TRNRDLLPDATA13": "PCIE_TRNRDLLPDATA13", - "CFGERRLOCKEDN": "PCIE_CFGERRLOCKEDN", - "TRNRDLLPDATA62": "PCIE_TRNRDLLPDATA62", - "CFGERRAERHEADERLOG76": "PCIE_CFGERRAERHEADERLOG76", - "CFGERRAERHEADERLOG93": "PCIE_CFGERRAERHEADERLOG93", - "TL2ERRHDR54": "PCIE_TL2ERRHDR54", - "CFGDSN15": "PCIE_CFGDSN15", - "CFGDSN17": "PCIE_CFGDSN17", - "TRNTDLLPDATA11": "PCIE_TRNTDLLPDATA11", - "TRNTD19": "PCIE_TRNTD19", - "PLDOWNSTREAMDEEMPHSOURCE": "PCIE_PLDOWNSTREAMDEEMPHSOURCE", - "CFGERRTLPCPLHEADER3": "PCIE_CFGERRTLPCPLHEADER3", - "CFGERRAERHEADERLOG120": "PCIE_CFGERRAERHEADERLOG120", - "TL2ERRHDR50": "PCIE_TL2ERRHDR50", - "CFGDSN54": "PCIE_CFGDSN54", - "CFGSUBSYSID3": "PCIE_CFGSUBSYSID3", - "PLDBGVEC4": "PCIE_PLDBGVEC4", - "CFGLINKCONTROLBANDWIDTHINTEN": "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", - "CFGDEVCONTROL2LTREN": "PCIE_CFGDEVCONTROL2LTREN", - "TRNRD91": "PCIE_TRNRD91", - "TRNFCNPD8": "PCIE_TRNFCNPD8", - "TRNFCNPH4": "PCIE_TRNFCNPH4", - "CFGMGMTDWADDR1": "PCIE_CFGMGMTDWADDR1", - "MIMRXWDATA63": "PCIE_MIMRXWDATA63", - "PIPETX7DATA1": "PCIE_PIPETX7DATA1", - "CFGSUBSYSVENDID7": "PCIE_CFGSUBSYSVENDID7", - "PIPERX0DATA13": "PCIE_PIPERX0DATA13", - "CFGERRAERHEADERLOG34": "PCIE_CFGERRAERHEADERLOG34", - "TRNRDLLPDATA9": "PCIE_TRNRDLLPDATA9", - "TRNRDLLPDATA41": "PCIE_TRNRDLLPDATA41", - "CFGMGMTDO18": "PCIE_CFGMGMTDO18", - "MIMTXRDATA52": "PCIE_MIMTXRDATA52", - "CFGERRAERHEADERLOG21": "PCIE_CFGERRAERHEADERLOG21", - "CFGERRAERHEADERLOG23": "PCIE_CFGERRAERHEADERLOG23", - "DBGVECC7": "PCIE_DBGVECC7", - "LL2TXIDLE": "PCIE_LL2TXIDLE", - "TRNTD40": "PCIE_TRNTD40", - "PIPETX5DATA3": "PCIE_PIPETX5DATA3", - "TRNFCPH1": "PCIE_TRNFCPH1", - "CFGDEVSTATUSURDETECTED": "PCIE_CFGDEVSTATUSURDETECTED", - "MIMTXRDATA67": "PCIE_MIMTXRDATA67", - "MIMRXRADDR6": "PCIE_MIMRXRADDR6", - "CFGDSFUNCTIONNUMBER0": "PCIE_CFGDSFUNCTIONNUMBER0", - "CFGERRAERHEADERLOG104": "PCIE_CFGERRAERHEADERLOG104", - "TL2ERRHDR55": "PCIE_TL2ERRHDR55", - "DBGVECA15": "PCIE_DBGVECA15", - "TRNTDLLPDATA5": "PCIE_TRNTDLLPDATA5", - "CFGSUBSYSID4": "PCIE_CFGSUBSYSID4", - "MIMRXRDATA45": "PCIE_MIMRXRDATA45", - "PIPERX6DATA5": "PCIE_PIPERX6DATA5", - "TRNTD84": "PCIE_TRNTD84", - "MIMTXWDATA27": "PCIE_MIMTXWDATA27", - "CFGERRAERHEADERLOG80": "PCIE_CFGERRAERHEADERLOG80", - "MIMRXRDATA32": "PCIE_MIMRXRDATA32", - "DBGVECA3": "PCIE_DBGVECA3", - "CFGPORTNUMBER7": "PCIE_CFGPORTNUMBER7", - "PIPERX0DATA14": "PCIE_PIPERX0DATA14", - "MIMTXWEN": "PCIE_MIMTXWEN", - "CFGMGMTDI8": "PCIE_CFGMGMTDI8", - "DRPDO5": "PCIE_DRPDO5", - "MIMRXRDATA3": "PCIE_MIMRXRDATA3", - "CFGMGMTDI31": "PCIE_CFGMGMTDI31", - "TL2ERRHDR21": "PCIE_TL2ERRHDR21", - "TRNRD60": "PCIE_TRNRD60", - "PIPETX0POWERDOWN0": "PCIE_PIPETX0POWERDOWN0", - "DBGVECB35": "PCIE_DBGVECB35", - "CFGERRAERHEADERLOG9": "PCIE_CFGERRAERHEADERLOG9", - "CFGERRAERHEADERLOG45": "PCIE_CFGERRAERHEADERLOG45", - "PIPETX7DATA10": "PCIE_PIPETX7DATA10", - "MIMRXRDATA49": "PCIE_MIMRXRDATA49", - "DRPDI7": "PCIE_DRPDI7", - "DRPADDR8": "PCIE_DRPADDR8", - "TRNTD89": "PCIE_TRNTD89", - "TRNRD15": "PCIE_TRNRD15", - "TRNFCPH4": "PCIE_TRNFCPH4", - "CFGDSDEVICENUMBER4": "PCIE_CFGDSDEVICENUMBER4", - "TRNTD95": "PCIE_TRNTD95", - "TL2ERRHDR62": "PCIE_TL2ERRHDR62", - "MIMTXREN": "PCIE_MIMTXREN", - "TRNRD77": "PCIE_TRNRD77", - "TL2ERRHDR5": "PCIE_TL2ERRHDR5", - "TRNTD105": "PCIE_TRNTD105", - "TRNRDLLPDATA45": "PCIE_TRNRDLLPDATA45", - "CFGVENDID15": "PCIE_CFGVENDID15", - "CFGDEVCONTROLNONFATALREPORTINGEN": "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", - "DBGVECB53": "PCIE_DBGVECB53", - "CFGMGMTDI15": "PCIE_CFGMGMTDI15", - "TRNTD65": "PCIE_TRNTD65", - "MIMRXRDATA36": "PCIE_MIMRXRDATA36", - "MIMTXRDATA42": "PCIE_MIMTXRDATA42", - "CFGINTERRUPTRDYN": "PCIE_CFGINTERRUPTRDYN", - "TRNTDLLPDATA29": "PCIE_TRNTDLLPDATA29", - "PIPETX6DATA10": "PCIE_PIPETX6DATA10", - "DRPDI4": "PCIE_DRPDI4", - "DBGSCLRE": "PCIE_DBGSCLRE", - "CFGERRTLPCPLHEADER15": "PCIE_CFGERRTLPCPLHEADER15", - "DRPADDR2": "PCIE_DRPADDR2", - "TRNTD5": "PCIE_TRNTD5", - "TL2ERRMALFORMED": "PCIE_TL2ERRMALFORMED", - "CFGMGMTDWADDR4": "PCIE_CFGMGMTDWADDR4", - "PIPETX4DATA13": "PCIE_PIPETX4DATA13", - "TRNFCNPD7": "PCIE_TRNFCNPD7", - "TRNRD43": "PCIE_TRNRD43", - "PLDIRECTEDLINKSPEED": "PCIE_PLDIRECTEDLINKSPEED", - "PIPERX5DATA6": "PCIE_PIPERX5DATA6", - "TRNRDLLPDATA38": "PCIE_TRNRDLLPDATA38", - "PLRXPMSTATE1": "PCIE_PLRXPMSTATE1", - "MIMRXRDATA38": "PCIE_MIMRXRDATA38", - "PIPERX0DATA6": "PCIE_PIPERX0DATA6", - "MIMRXWDATA1": "PCIE_MIMRXWDATA1", - "MIMRXWDATA44": "PCIE_MIMRXWDATA44", - "CFGMSGDATA5": "PCIE_CFGMSGDATA5", - "CFGERRAERHEADERLOG35": "PCIE_CFGERRAERHEADERLOG35", - "CFGTRANSACTION": "PCIE_CFGTRANSACTION", - "PIPETX2DATA15": "PCIE_PIPETX2DATA15", - "PIPETX5POWERDOWN0": "PCIE_PIPETX5POWERDOWN0", - "MIMTXWDATA21": "PCIE_MIMTXWDATA21", - "PIPERX3CHARISK0": "PCIE_PIPERX3CHARISK0", - "MIMTXRDATA0": "PCIE_MIMTXRDATA0", - "CFGMGMTDO12": "PCIE_CFGMGMTDO12", - "PIPERX4DATA4": "PCIE_PIPERX4DATA4", - "TRNRD32": "PCIE_TRNRD32", - "TRNRD55": "PCIE_TRNRD55", - "CFGCOMMANDBUSMASTERENABLE": "PCIE_CFGCOMMANDBUSMASTERENABLE", - "TRNRD5": "PCIE_TRNRD5", - "TRNRD28": "PCIE_TRNRD28", - "MIMTXWDATA11": "PCIE_MIMTXWDATA11", - "PIPERX1DATA3": "PCIE_PIPERX1DATA3", - "CFGDSN10": "PCIE_CFGDSN10", - "EDTCHANNELSIN4": "PCIE_EDTCHANNELSIN4", - "PIPETX1DATA1": "PCIE_PIPETX1DATA1", - "PIPETX4DATA6": "PCIE_PIPETX4DATA6", - "PLINITIALLINKWIDTH0": "PCIE_PLINITIALLINKWIDTH0", - "CFGPMFORCESTATE1": "PCIE_CFGPMFORCESTATE1", - "TRNRDLLPDATA20": "PCIE_TRNRDLLPDATA20", - "PIPERX6POLARITY": "PCIE_PIPERX6POLARITY", - "TRNRD69": "PCIE_TRNRD69", - "TRNFCCPLD5": "PCIE_TRNFCCPLD5", - "CFGMGMTDI9": "PCIE_CFGMGMTDI9", - "CFGERRAERHEADERLOG92": "PCIE_CFGERRAERHEADERLOG92", - "DBGVECB58": "PCIE_DBGVECB58", - "PIPERX4DATA14": "PCIE_PIPERX4DATA14", - "CFGDSN46": "PCIE_CFGDSN46", - "PIPERX2STATUS2": "PCIE_PIPERX2STATUS2", - "MIMTXRDATA5": "PCIE_MIMTXRDATA5", - "DRPDO11": "PCIE_DRPDO11", - "TRNTD80": "PCIE_TRNTD80", - "MIMTXWDATA14": "PCIE_MIMTXWDATA14", - "MIMTXWDATA49": "PCIE_MIMTXWDATA49", - "DBGVECB20": "PCIE_DBGVECB20", - "MIMTXRDATA40": "PCIE_MIMTXRDATA40", - "PIPETX7DATA13": "PCIE_PIPETX7DATA13", - "CFGDSN59": "PCIE_CFGDSN59", - "MIMRXRDATA46": "PCIE_MIMRXRDATA46", - "MIMTXWADDR12": "PCIE_MIMTXWADDR12", - "TL2ERRHDR60": "PCIE_TL2ERRHDR60", - "DBGVECB0": "PCIE_DBGVECB0", - "CFGERRAERHEADERLOG116": "PCIE_CFGERRAERHEADERLOG116", - "PIPETX1CHARISK0": "PCIE_PIPETX1CHARISK0", - "PIPETX4DATA7": "PCIE_PIPETX4DATA7", - "PIPETX6POWERDOWN1": "PCIE_PIPETX6POWERDOWN1", - "MIMRXWDATA13": "PCIE_MIMRXWDATA13", - "PIPETX3DATA9": "PCIE_PIPETX3DATA9", - "TRNRD18": "PCIE_TRNRD18", - "CFGDSBUSNUMBER5": "PCIE_CFGDSBUSNUMBER5", - "PIPERX4DATA12": "PCIE_PIPERX4DATA12", - "XILUNCONNOUT16": "PCIE_XILUNCONNOUT16", - "MIMRXRDATA20": "PCIE_MIMRXRDATA20", - "CFGDSN37": "PCIE_CFGDSN37", - "PIPERX0CHARISK0": "PCIE_PIPERX0CHARISK0", - "PIPERX0STATUS2": "PCIE_PIPERX0STATUS2", - "TL2ERRHDR41": "PCIE_TL2ERRHDR41", - "TRNTD63": "PCIE_TRNTD63", - "CFGMGMTRDWRDONEN": "PCIE_CFGMGMTRDWRDONEN", - "TRNTD112": "PCIE_TRNTD112", - "TRNFCNPD11": "PCIE_TRNFCNPD11", - "TRNTD53": "PCIE_TRNTD53", - "CFGDEVCONTROL2CPLTIMEOUTVAL2": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", - "MIMTXWDATA2": "PCIE_MIMTXWDATA2", - "CFGVENDID14": "PCIE_CFGVENDID14", - "MIMTXWDATA7": "PCIE_MIMTXWDATA7", - "TRNTD7": "PCIE_TRNTD7", - "TRNTD57": "PCIE_TRNTD57", - "LL2REPLAYROERR": "PCIE_LL2REPLAYROERR", - "CFGERRAERHEADERLOG75": "PCIE_CFGERRAERHEADERLOG75", - "TRNRD98": "PCIE_TRNRD98", - "TRNRD66": "PCIE_TRNRD66", - "TRNTDLLPDATA20": "PCIE_TRNTDLLPDATA20", - "PL2RECOVERY": "PCIE_PL2RECOVERY", - "LL2SUSPENDNOW": "PCIE_LL2SUSPENDNOW", - "TRNFCNPD1": "PCIE_TRNFCNPD1", - "CFGERRAERHEADERLOG56": "PCIE_CFGERRAERHEADERLOG56", - "CFGPCIELINKSTATE1": "PCIE_CFGPCIELINKSTATE1", - "CFGVCTCVCMAP1": "PCIE_CFGVCTCVCMAP1", - "CFGDEVID5": "PCIE_CFGDEVID5", - "CFGINTERRUPTMMENABLE1": "PCIE_CFGINTERRUPTMMENABLE1", - "MIMRXWDATA66": "PCIE_MIMRXWDATA66" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "PCIE_BOT.PCIE_PLDBGVEC1->PCIE_LOGIC_OUTS_B23_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_14", - "is_directional": "1", - "src_wire": "PCIE_PLDBGVEC1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC4->PCIE_LOGIC_OUTS_B19_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_8", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLDBGVEC11->PCIE_LOGIC_OUTS_B22_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_4", - "is_directional": "1", - "src_wire": "PCIE_PLDBGVEC11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA14->PCIE_LOGIC_OUTS_B2_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CTRL0_R_1->PCIE_CMSTICKYRSTN": { - "can_invert": "0", - "dst_wire": "PCIE_CMSTICKYRSTN", - "is_directional": "1", - "src_wire": "PCIE_CTRL0_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_2->PCIE_PLTRANSMITHOTRST": { - "can_invert": "0", - "dst_wire": "PCIE_PLTRANSMITHOTRST", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTDSTRDY1->PCIE_LOGIC_OUTS_B1_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_15", - "is_directional": "1", - "src_wire": "PCIE_TRNTDSTRDY1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7POWERDOWN0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_2->PCIE_TRNTD82": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD82", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA12->PCIE_LOGIC_OUTS_B0_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_0->PCIE_CFGERRAERHEADERLOG74": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG74", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_14->PCIE_PIPERX2DATA15": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_7->PCIE_PIPERX1DATA15": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_1->PCIE_CFGERRAERHEADERLOG79": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG79", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_10->PCIE_CFGERRAERHEADERLOG117": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG117", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR9->PCIE_LOGIC_OUTS_B9_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_10", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD6->PCIE_LOGIC_OUTS_B5_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_10", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_4->PCIE_PIPERX7DATA10": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_10->PCIE_CFGDSDEVICENUMBER0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSDEVICENUMBER0", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR11->PCIE_LOGIC_OUTS_B8_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA9->PCIE_LOGIC_OUTS_B13_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_5", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD19->PCIE_LOGIC_OUTS_B0_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_10", - "is_directional": "1", - "src_wire": "PCIE_TRNRD19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA30->PCIE_LOGIC_OUTS_B6_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA30", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD126->PCIE_LOGIC_OUTS_B2_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRD126", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_1->PCIE_CFGERRAERHEADERLOG68": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG68", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA4->PCIE_LOGIC_OUTS_B0_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR10->PCIE_LOGIC_OUTS_B6_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_9", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_14->PCIE_CFGAERINTERRUPTMSGNUM0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM0", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_7->PCIE_CFGSUBSYSID11": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID11", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR51->PCIE_LOGIC_OUTS_B8_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_10", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR51", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRBARHIT5->PCIE_LOGIC_OUTS_B2_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_8", - "is_directional": "1", - "src_wire": "PCIE_TRNRBARHIT5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_11->PCIE_TRNTEOF": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTEOF", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_11->PCIE_CFGDSBUSNUMBER5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSBUSNUMBER5", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD10->PCIE_LOGIC_OUTS_B9_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_11", - "is_directional": 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"PCIE_LOGIC_OUTS_B17_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTDO3->PCIE_LOGIC_OUTS_B14_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_8", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTDO3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_16->PCIE_CFGERRAERHEADERLOG13": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG13", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_10->PCIE_CFGDSBUSNUMBER7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSBUSNUMBER7", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRMALFORMED->PCIE_LOGIC_OUTS_B17_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_13", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRMALFORMED", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_3->PCIE_CFGERRAERHEADERLOG59": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG59", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_3", - "is_pseudo": "0" - }, "PCIE_BOT.PCIE_TL2PPMSUSPENDOK->PCIE_LOGIC_OUTS_B21_R_16": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_16", - "is_directional": "1", "src_wire": "PCIE_TL2PPMSUSPENDOK", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_L_5->PCIE_PIPERX3PHYSTATUS": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3PHYSTATUS", "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLENABLERO->PCIE_LOGIC_OUTS_B18_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_14", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLENABLERO", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA51->PCIE_LOGIC_OUTS_B18_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_11", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA51", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA15->PCIE_LOGIC_OUTS_B13_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_15", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_11->PCIE_CFGDSBUSNUMBER3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSBUSNUMBER3", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA18->PCIE_LOGIC_OUTS_B1_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_2->PCIE_MIMTXRDATA8": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA8", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC7->PCIE_LOGIC_OUTS_B18_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_9", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA6->PCIE_LOGIC_OUTS_B20_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_5->PCIE_CFGFORCECOMMONCLOCKOFF": { - "can_invert": "0", - "dst_wire": "PCIE_CFGFORCECOMMONCLOCKOFF", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_5->PCIE_PIPERX3DATA4": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_6->PCIE_CFGERRAERHEADERLOG100": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG100", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA6->PCIE_LOGIC_OUTS_B2_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB33->PCIE_LOGIC_OUTS_B22_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_2", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB33", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_2->PCIE_CFGERRAERHEADERLOG82": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG82", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2->PCIE_LOGIC_OUTS_B19_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_18", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_4->PCIE_MIMTXRDATA18": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA18", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA15->PCIE_LOGIC_OUTS_B6_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX18_L_0->PCIE_CFGPORTNUMBER5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPORTNUMBER5", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWADDR7->PCIE_LOGIC_OUTS_B11_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWADDR7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_4->PCIE_PIPERX7STATUS1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7STATUS1", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO15->PCIE_LOGIC_OUTS_B17_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_14", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2REPLAYROERR->PCIE_LOGIC_OUTS_B4_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_12", - "is_directional": "1", - "src_wire": "PCIE_LL2REPLAYROERR", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA10->PCIE_LOGIC_OUTS_B11_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_1", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_18->PCIE_TRNTD45": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD45", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3ELECIDLE->PCIE_LOGIC_OUTS_B3_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3ELECIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_18->PCIE_DRPADDR4": { - "can_invert": "0", - "dst_wire": "PCIE_DRPADDR4", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_13->PCIE_CFGERRAERHEADERLOG127": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG127", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_16->PCIE_PIPERX6DATA7": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA10->PCIE_LOGIC_OUTS_B11_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_1", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA11->PCIE_LOGIC_OUTS_B18_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_9", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA35->PCIE_LOGIC_OUTS_B11_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_15", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA35", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA7->PCIE_LOGIC_OUTS_B6_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD105->PCIE_LOGIC_OUTS_B5_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRD105", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_6->PCIE_CFGERRAERHEADERLOG47": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG47", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CTRL0_R_3->PCIE_PLRSTN": { - "can_invert": "0", - "dst_wire": "PCIE_PLRSTN", - "is_directional": "1", - "src_wire": "PCIE_CTRL0_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD13->PCIE_LOGIC_OUTS_B2_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_8", - "is_directional": "1", - "src_wire": "PCIE_TRNRD13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_16->PCIE_PIPERX2DATA5": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_17->PCIE_CFGERRATOMICEGRESSBLOCKEDN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRATOMICEGRESSBLOCKEDN", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA28->PCIE_LOGIC_OUTS_B16_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_7", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA28", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_L_19->PCIE_PIPERX0CHARISK1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0CHARISK1", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB35->PCIE_LOGIC_OUTS_B22_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_0", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB35", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLANEREVERSALMODE0->PCIE_LOGIC_OUTS_B13_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLLANEREVERSALMODE0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_4->PCIE_PIPERX3STATUS2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3STATUS2", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD112->PCIE_LOGIC_OUTS_B3_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRD112", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR22->PCIE_LOGIC_OUTS_B14_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_1", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR22", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_1->PCIE_TRNTD84": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD84", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_L_10->PCIE_PIPERX1DATA0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_17->PCIE_TRNTD46": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD46", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA10->PCIE_LOGIC_OUTS_B8_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA67->PCIE_LOGIC_OUTS_B14_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_2", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA67", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_13->PCIE_TRNTD64": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD64", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD6->PCIE_LOGIC_OUTS_B5_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_0", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_10->PCIE_TRNTD77": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD77", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_0->PCIE_MIMTXRDATA62": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA62", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGPCIELINKSTATE0->PCIE_LOGIC_OUTS_B11_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGPCIELINKSTATE0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA0->PCIE_LOGIC_OUTS_B9_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_14", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA5->PCIE_LOGIC_OUTS_B12_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR6->PCIE_LOGIC_OUTS_B17_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_2", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXRADDR3->PCIE_LOGIC_OUTS_B16_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_18", - "is_directional": "1", - "src_wire": "PCIE_MIMRXRADDR3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_7->PCIE_CFGMGMTDI20": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI20", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_18->PCIE_DRPADDR3": { - "can_invert": "0", - "dst_wire": "PCIE_DRPADDR3", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_14->PCIE_TRNTD61": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD61", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR45->PCIE_LOGIC_OUTS_B10_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_8", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR45", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_3->PCIE_CFGSUBSYSID1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID1", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA16->PCIE_LOGIC_OUTS_B4_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_USERRSTN->PCIE_LOGIC_OUTS_B12_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_8", - "is_directional": "1", - "src_wire": "PCIE_USERRSTN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB61->PCIE_LOGIC_OUTS_B20_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_6", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB61", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_2->PCIE_CFGERRAERHEADERLOG84": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG84", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPH3->PCIE_LOGIC_OUTS_B13_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_2", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPH3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1POWERDOWN1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_16->PCIE_DRPEN": { - "can_invert": "0", - "dst_wire": "PCIE_DRPEN", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_8->PCIE_CFGERRAERHEADERLOG40": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG40", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLEXTTAGEN->PCIE_LOGIC_OUTS_B17_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_15", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLEXTTAGEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA14->PCIE_LOGIC_OUTS_B12_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_15", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_19->PCIE_PIPERX0STATUS1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0STATUS1", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLH4->PCIE_LOGIC_OUTS_B10_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_7", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLH4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB57->PCIE_LOGIC_OUTS_B20_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_5", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB57", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_2->PCIE_CFGERRAERHEADERLOG83": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG83", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_1->PCIE_CFGREVID3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGREVID3", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB48->PCIE_LOGIC_OUTS_B19_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_3", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB48", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_17->PCIE_CFGDSN45": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN45", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_16->PCIE_TRNTDLLPDATA4": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_14->PCIE_CFGDSN34": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN34", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA28->PCIE_LOGIC_OUTS_B21_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_18", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA28", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_5->PCIE_PIPERX7DATA4": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_14->PCIE_TRNRFCPRET": { - "can_invert": "0", - "dst_wire": "PCIE_TRNRFCPRET", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_0->PCIE_PLDIRECTEDLTSSMNEWVLD": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLTSSMNEWVLD", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_19->PCIE_CFGDSN53": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN53", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_4->PCIE_PIPERX7STATUS2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7STATUS2", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_0->PCIE_MIMTXRDATA2": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA13->PCIE_LOGIC_OUTS_B4_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLTXPMSTATE0->PCIE_LOGIC_OUTS_B17_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLTXPMSTATE0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_7->PCIE_PIPERX1DATA12": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA12", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_6->PCIE_CFGSUBSYSID6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID6", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLRECEIVEDHOTRST->PCIE_LOGIC_OUTS_B13_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_8", - "is_directional": "1", - "src_wire": "PCIE_PLRECEIVEDHOTRST", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_4->PCIE_PIPERX3STATUS1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3STATUS1", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3POWERDOWN1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_19->PCIE_MIMRXRDATA59": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA59", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTMSIXENABLE->PCIE_LOGIC_OUTS_B17_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_4", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTMSIXENABLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTDLLPDSTRDY->PCIE_LOGIC_OUTS_B11_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_11", - "is_directional": "1", - "src_wire": "PCIE_TRNTDLLPDSTRDY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR10->PCIE_LOGIC_OUTS_B8_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_9", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_0->PCIE_CFGERRAERHEADERLOG76": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG76", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PL2RXELECIDLE->PCIE_LOGIC_OUTS_B7_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_19", - "is_directional": "1", - "src_wire": "PCIE_PL2RXELECIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA50->PCIE_LOGIC_OUTS_B17_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA50", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD121->PCIE_LOGIC_OUTS_B8_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRD121", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX19_R_12->PCIE_CFGVENDID8": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID8", - "is_directional": "1", - "src_wire": "PCIE_IMUX19_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR52->PCIE_LOGIC_OUTS_B9_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_10", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR52", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_15->PCIE_PIPERX6STATUS1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6STATUS1", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_7->PCIE_CFGERRAERHEADERLOG103": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG103", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWADDR11->PCIE_LOGIC_OUTS_B14_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWADDR11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD49->PCIE_LOGIC_OUTS_B9_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRD49", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNREOF->PCIE_LOGIC_OUTS_B7_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_11", - "is_directional": "1", - "src_wire": "PCIE_TRNREOF", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR12->PCIE_LOGIC_OUTS_B10_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_9", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_11->PCIE_TRNTSOF": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTSOF", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_8->PCIE_PIPERX1STATUS0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1STATUS0", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE1->PCIE_LOGIC_OUTS_B17_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_10", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTMMENABLE1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA13->PCIE_LOGIC_OUTS_B5_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_9", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA2->PCIE_LOGIC_OUTS_B11_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_7", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_13->PCIE_CFGVENDID2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID2", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_18->PCIE_PIPERX4DATA15": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4DATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA21->PCIE_LOGIC_OUTS_B5_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_8", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA21", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_18->PCIE_MIMRXRDATA63": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA63", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PL2LINKUP->PCIE_LOGIC_OUTS_B8_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_14", - "is_directional": "1", - "src_wire": "PCIE_PL2LINKUP", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR5->PCIE_LOGIC_OUTS_B12_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_11", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4COMPLIANCE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTDO7->PCIE_LOGIC_OUTS_B14_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_9", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTDO7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_8->PCIE_CFGMGMTDI23": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI23", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_13->PCIE_CFGDSN30": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN30", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA66->PCIE_LOGIC_OUTS_B18_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_17", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA66", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR9->PCIE_LOGIC_OUTS_B21_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CTRL0_R_0->PCIE_SYSRSTN": { - "can_invert": "0", - "dst_wire": "PCIE_SYSRSTN", - "is_directional": "1", - "src_wire": "PCIE_CTRL0_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_0->PCIE_PLDIRECTEDLTSSMNEW2": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW2", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB12->PCIE_LOGIC_OUTS_B10_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_7", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_11->PCIE_TRNTD71": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD71", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_R_10->PCIE_PIPERX5DATA3": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_3->PCIE_MIMTXRDATA51": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA51", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_9->PCIE_PIPERX5VALID": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5VALID", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLTXPMSTATE2->PCIE_LOGIC_OUTS_B19_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLTXPMSTATE2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD23->PCIE_LOGIC_OUTS_B1_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_11", - "is_directional": "1", - "src_wire": "PCIE_TRNRD23", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGBRIDGESERREN->PCIE_LOGIC_OUTS_B17_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_8", - "is_directional": "1", - "src_wire": "PCIE_CFGBRIDGESERREN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_9->PCIE_CFGERRAERHEADERLOG110": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG110", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA11->PCIE_LOGIC_OUTS_B15_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_1", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_8->PCIE_CFGMGMTDI24": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI24", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_17->PCIE_TRNTDLLPDATA9": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA9", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_2->PCIE_TRNTD79": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD79", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC1->PCIE_LOGIC_OUTS_B20_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_7", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_7->PCIE_CFGERRAERHEADERLOG104": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG104", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_10->PCIE_CFGMGMTDI31": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI31", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_5->PCIE_CFGERRAERHEADERLOG95": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG95", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_13->PCIE_TRNTCFGGNT": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTCFGGNT", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLH6->PCIE_LOGIC_OUTS_B5_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_8", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLH6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE->PCIE_LOGIC_OUTS_B22_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_15", - "is_directional": "1", - "src_wire": "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_L_17->PCIE_PIPERX2DATA1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_8->PCIE_MIMTXRDATA32": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA32", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA33->PCIE_LOGIC_OUTS_B22_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_16", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA33", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA3->PCIE_LOGIC_OUTS_B15_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_7->PCIE_TRNTD114": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD114", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_14->PCIE_PIPERX2DATA13": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_9->PCIE_TRNTD123": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD123", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR34->PCIE_LOGIC_OUTS_B10_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_5", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR34", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_5->PCIE_CFGSUBSYSID5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID5", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_16->PCIE_CFGAERINTERRUPTMSGNUM4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM4", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5ELECIDLE->PCIE_LOGIC_OUTS_B3_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5ELECIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_19->PCIE_MIMRXRDATA19": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA19", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_4->PCIE_CFGMGMTDI9": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI9", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_8->PCIE_PIPERX1ELECIDLE": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1ELECIDLE", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_7->PCIE_MIMTXRDATA42": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA42", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7CHARISK0->PCIE_LOGIC_OUTS_B16_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7CHARISK0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_6->PCIE_CFGERRAERHEADERLOG46": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG46", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_16" }, "PCIE_BOT.PCIE_DBGVECA52->PCIE_LOGIC_OUTS_B20_R_11": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_11", - "is_directional": "1", "src_wire": "PCIE_DBGVECA52", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_6", "is_directional": "1", - "src_wire": "PCIE_PIPETX5POWERDOWN1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD0->PCIE_LOGIC_OUTS_B7_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_8", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_9->PCIE_MIMTXRDATA38": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA38", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS->PCIE_LOGIC_OUTS_B14_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_16->PCIE_CFGDSN41": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN41", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX18_R_11->PCIE_CFGVENDID11": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID11", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA5->PCIE_LOGIC_OUTS_B18_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_11", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1ELECIDLE->PCIE_LOGIC_OUTS_B3_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1ELECIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_1->PCIE_MIMTXRDATA5": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD2->PCIE_LOGIC_OUTS_B5_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_9", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_15->PCIE_PIPERX6DATA9": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA9", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_13->PCIE_TRNTSTR": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTSTR", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_1->PCIE_PLDIRECTEDLTSSMNEW5": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW5", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_L_17->PCIE_PIPERX2DATA3": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_7->PCIE_CFGSUBSYSID12": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID12", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_1->PCIE_CFGERRAERHEADERLOG69": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG69", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_17->PCIE_TRNTDLLPDATA8": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA8", - "is_directional": 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"is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA44", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_17->PCIE_PIPERX6DATA1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_19->PCIE_CFGDSN56": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN56", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_6->PCIE_CFGSUBSYSID9": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID9", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_4->PCIE_MIMTXRDATA19": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA19", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB13->PCIE_LOGIC_OUTS_B14_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_7", - "is_directional": "1", - "src_wire": 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"PCIE_BOT.PCIE_IMUX12_R_10->PCIE_CFGERRAERHEADERLOG33": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG33", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_7", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5COMPLIANCE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA6->PCIE_LOGIC_OUTS_B2_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA5->PCIE_LOGIC_OUTS_B4_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLNONFATALREPORTINGEN->PCIE_LOGIC_OUTS_B21_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_12", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_2->PCIE_MIMTXRDATA10": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR14->PCIE_LOGIC_OUTS_B7_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_8", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA11->PCIE_LOGIC_OUTS_B15_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_12", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_3->PCIE_CFGSUBSYSID0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID0", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA0->PCIE_LOGIC_OUTS_B4_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_8->PCIE_CFGERRAERHEADERLOG38": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG38", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETXRCVRDET->PCIE_LOGIC_OUTS_B15_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_9", - "is_directional": "1", - "src_wire": "PCIE_PIPETXRCVRDET", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR15->PCIE_LOGIC_OUTS_B8_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_8", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLH5->PCIE_LOGIC_OUTS_B4_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_8", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLH5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_5->PCIE_TRNTD106": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD106", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_19->PCIE_PIPERX4DATA10": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4DATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD39->PCIE_LOGIC_OUTS_B1_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRD39", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD107->PCIE_LOGIC_OUTS_B8_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRD107", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_1->PCIE_MIMTXRDATA61": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA61", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR48->PCIE_LOGIC_OUTS_B9_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_9", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR48", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_16->PCIE_TRNTDLLPDATA3": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA13->PCIE_LOGIC_OUTS_B4_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRH->PCIE_LOGIC_OUTS_B22_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_12", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRH", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA2->PCIE_LOGIC_OUTS_B11_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_14", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_8->PCIE_PIPERX5STATUS0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5STATUS0", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_6->PCIE_TRNTD109": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD109", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA62->PCIE_LOGIC_OUTS_B19_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA62", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_15->PCIE_CFGERRTLPCPLHEADER6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER6", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA65->PCIE_LOGIC_OUTS_B10_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA65", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_16->PCIE_CFGERRTLPCPLHEADER10": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER10", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_2->PCIE_CFGREVID6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGREVID6", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPERX4POLARITY->PCIE_LOGIC_OUTS_B1_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_18", - "is_directional": "1", - "src_wire": "PCIE_PIPERX4POLARITY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO12->PCIE_LOGIC_OUTS_B12_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_14", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_0->PCIE_PLDIRECTEDLINKWIDTH0": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLINKWIDTH0", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CLK1_R_11->PCIE_DRPCLK": { - "can_invert": "0", - "dst_wire": "PCIE_DRPCLK", - "is_directional": "1", - "src_wire": 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"PCIE_LOGIC_OUTS_B10_L_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_3->PCIE_CFGERRAERHEADERLOG60": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG60", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_6->PCIE_CFGMGMTDI18": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI18", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_0->PCIE_PLDIRECTEDLINKAUTON": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLINKAUTON", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA8->PCIE_LOGIC_OUTS_B22_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX19_R_1->PCIE_CFGDSFUNCTIONNUMBER2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSFUNCTIONNUMBER2", - "is_directional": "1", - "src_wire": "PCIE_IMUX19_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_19->PCIE_PIPERX0ELECIDLE": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0ELECIDLE", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA2->PCIE_LOGIC_OUTS_B11_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_7", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX18_R_13->PCIE_CFGVENDID3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID3", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_10->PCIE_CFGSUBSYSVENDID0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID0", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD114->PCIE_LOGIC_OUTS_B7_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRD114", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_L_5->PCIE_PIPERX3VALID": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3VALID", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA30->PCIE_LOGIC_OUTS_B21_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_17", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA30", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR3->PCIE_LOGIC_OUTS_B10_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_2", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_6->PCIE_PIPERX7DATA0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_13->PCIE_CFGMGMTDWADDR7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR7", 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"PCIE_IMUX0_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA19->PCIE_LOGIC_OUTS_B4_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_8", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_3->PCIE_CFGERRAERHEADERLOG86": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG86", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_4->PCIE_PIPERX7DATA9": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA9", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB18->PCIE_LOGIC_OUTS_B6_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_5", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_17->PCIE_CFGERRTLPCPLHEADER16": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER16", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA0->PCIE_LOGIC_OUTS_B12_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_10", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD5->PCIE_LOGIC_OUTS_B9_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_6", - "is_directional": "1", - "src_wire": "PCIE_TRNRD5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_14->PCIE_CFGAERINTERRUPTMSGNUM1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM1", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_17->PCIE_MIMRXRDATA67": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA67", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB28->PCIE_LOGIC_OUTS_B16_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_3", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB28", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA15->PCIE_LOGIC_OUTS_B16_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_9", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_5->PCIE_CFGMGMTDI13": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI13", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_2->PCIE_CFGREVID7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGREVID7", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_L_15->PCIE_PIPERX2DATA11": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA8->PCIE_LOGIC_OUTS_B9_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_12", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_3->PCIE_TRNTD97": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD97", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_19->PCIE_PIPERX0STATUS2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0STATUS2", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_6->PCIE_CFGMGMTDI16": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI16", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA9->PCIE_LOGIC_OUTS_B13_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_1", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_2->PCIE_CFGERRAERHEADERLOG62": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG62", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1CHARISK1->PCIE_LOGIC_OUTS_B16_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_4", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1CHARISK1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR55->PCIE_LOGIC_OUTS_B12_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_11", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR55", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA12->PCIE_LOGIC_OUTS_B0_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_9->PCIE_CFGERRAERHEADERLOG37": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG37", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR3->PCIE_LOGIC_OUTS_B10_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_11", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_12->PCIE_CFGINTERRUPTSTATN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGINTERRUPTSTATN", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD127->PCIE_LOGIC_OUTS_B3_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRD127", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_1->PCIE_PLDIRECTEDLTSSMSTALL": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLTSSMSTALL", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA30->PCIE_LOGIC_OUTS_B20_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA30", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLH3->PCIE_LOGIC_OUTS_B8_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_7", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLH3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRERRFWD->PCIE_LOGIC_OUTS_B5_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_10", - "is_directional": "1", - "src_wire": "PCIE_TRNRERRFWD", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPH5->PCIE_LOGIC_OUTS_B5_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_4", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPH5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB46->PCIE_LOGIC_OUTS_B21_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_2", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB46", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5CHARISK1->PCIE_LOGIC_OUTS_B16_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_4", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5CHARISK1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD33->PCIE_LOGIC_OUTS_B9_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRD33", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_1->PCIE_CFGDSFUNCTIONNUMBER0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSFUNCTIONNUMBER0", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPH1->PCIE_LOGIC_OUTS_B11_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_2", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPH1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_16->PCIE_TRNTD51": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD51", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPD1->PCIE_LOGIC_OUTS_B8_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_4", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA0->PCIE_LOGIC_OUTS_B9_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_7", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_1->PCIE_CFGPMFORCESTATE0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPMFORCESTATE0", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_3->PCIE_MIMTXRDATA53": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA53", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_0->PCIE_PLDOWNSTREAMDEEMPHSOURCE": { - "can_invert": "0", - "dst_wire": "PCIE_PLDOWNSTREAMDEEMPHSOURCE", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD32->PCIE_LOGIC_OUTS_B8_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRD32", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR12->PCIE_LOGIC_OUTS_B10_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_1", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_10->PCIE_CFGERRAERHEADERLOG114": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG114", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_14->PCIE_PIPERX6DATA15": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_19->PCIE_CFGERRTLPCPLHEADER23": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER23", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6CHARISK0->PCIE_LOGIC_OUTS_B16_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6CHARISK0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2PROTOCOLERR->PCIE_LOGIC_OUTS_B12_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_13", - "is_directional": "1", - "src_wire": "PCIE_LL2PROTOCOLERR", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR29->PCIE_LOGIC_OUTS_B12_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_4", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR29", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_19->PCIE_PIPERX4DATA8": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4DATA8", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPERX7POLARITY->PCIE_LOGIC_OUTS_B1_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_3", - "is_directional": "1", - "src_wire": "PCIE_PIPERX7POLARITY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA6->PCIE_LOGIC_OUTS_B13_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ2->PCIE_LOGIC_OUTS_B18_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_5->PCIE_CFGERRAERHEADERLOG97": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG97", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_5->PCIE_CFGMGMTDI11": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI11", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB54->PCIE_LOGIC_OUTS_B21_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_4", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB54", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CLK0_R_12->PCIE_USERCLK": { - "can_invert": "0", - "dst_wire": "PCIE_USERCLK", - "is_directional": "1", - "src_wire": "PCIE_CLK0_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR7->PCIE_LOGIC_OUTS_B15_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_2->PCIE_CFGMGMTDI2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI2", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR1->PCIE_LOGIC_OUTS_B7_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_12", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_15->PCIE_CFGERRTLPCPLHEADER8": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER8", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_L_16->PCIE_PIPERX2PHYSTATUS": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2PHYSTATUS", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_10->PCIE_TRNTD75": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD75", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_16->PCIE_CFGERRCPLABORTN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRCPLABORTN", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_10->PCIE_TRNTD124": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD124", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLH2->PCIE_LOGIC_OUTS_B7_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_7", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLH2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO14->PCIE_LOGIC_OUTS_B16_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_14", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRFCPE->PCIE_LOGIC_OUTS_B19_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_13", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRFCPE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD99->PCIE_LOGIC_OUTS_B1_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRD99", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR33->PCIE_LOGIC_OUTS_B8_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_5", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR33", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_12->PCIE_CFGMGMTDWADDR5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR5", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD45->PCIE_LOGIC_OUTS_B2_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRD45", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD103->PCIE_LOGIC_OUTS_B0_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRD103", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_8->PCIE_CFGERRAERHEADERLOG109": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG109", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_19->PCIE_MIMRXRDATA56": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA56", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_17->PCIE_DRPADDR2": { - "can_invert": "0", - "dst_wire": "PCIE_DRPADDR2", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA25->PCIE_LOGIC_OUTS_B7_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA25", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR25->PCIE_LOGIC_OUTS_B12_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_3", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR25", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_18->PCIE_CFGDSN49": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN49", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_9->PCIE_PIPERX1DATA7": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_5->PCIE_PIPERX7DATA7": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPD4->PCIE_LOGIC_OUTS_B11_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_4", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRBARHIT1->PCIE_LOGIC_OUTS_B1_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_9", - "is_directional": "1", - "src_wire": "PCIE_TRNRBARHIT1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_7", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1COMPLIANCE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA2->PCIE_LOGIC_OUTS_B14_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_10", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_4->PCIE_MIMTXRDATA17": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA17", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR38->PCIE_LOGIC_OUTS_B17_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_6", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR38", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA38->PCIE_LOGIC_OUTS_B18_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_0", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA38", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB26->PCIE_LOGIC_OUTS_B7_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_3", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB26", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA36->PCIE_LOGIC_OUTS_B19_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_15", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA36", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA24->PCIE_LOGIC_OUTS_B18_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA24", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD124->PCIE_LOGIC_OUTS_B0_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRD124", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA5->PCIE_LOGIC_OUTS_B4_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD118->PCIE_LOGIC_OUTS_B4_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRD118", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRCORRERREN->PCIE_LOGIC_OUTS_B20_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGROOTCONTROLSYSERRCORRERREN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA46->PCIE_LOGIC_OUTS_B18_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_12", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA46", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_17->PCIE_CFGERRTLPCPLHEADER15": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER15", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA2->PCIE_LOGIC_OUTS_B11_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_0->PCIE_PLDIRECTEDLINKCHANGE1": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLINKCHANGE1", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD34->PCIE_LOGIC_OUTS_B10_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRD34", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA14->PCIE_LOGIC_OUTS_B2_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_4", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRNONFATALERREN->PCIE_LOGIC_OUTS_B21_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_6->PCIE_MIMTXRDATA25": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA25", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_L_1->PCIE_PLDBGMODE1": { - "can_invert": "0", - "dst_wire": "PCIE_PLDBGMODE1", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_13->PCIE_CFGSUBSYSVENDID12": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID12", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_1->PCIE_TRNTD91": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD91", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_10->PCIE_TRNTD74": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD74", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_18->PCIE_MIMRXRDATA62": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA62", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_RECEIVEDFUNCLVLRSTN->PCIE_LOGIC_OUTS_B12_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_9", - "is_directional": "1", - "src_wire": "PCIE_RECEIVEDFUNCLVLRSTN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD8->PCIE_LOGIC_OUTS_B8_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_0", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA57->PCIE_LOGIC_OUTS_B5_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA57", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4POWERDOWN1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRF->PCIE_LOGIC_OUTS_B21_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_11", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRF", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_9->PCIE_CFGMGMTDI29": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI29", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_12->PCIE_CFGVENDID6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID6", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_5->PCIE_PIPERX3DATA5": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_L_4->PCIE_PIPERX3CHARISK1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3CHARISK1", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD5->PCIE_LOGIC_OUTS_B4_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_10", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD44->PCIE_LOGIC_OUTS_B1_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRD44", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_2->PCIE_MIMTXRDATA56": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA56", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_8->PCIE_MIMTXRDATA35": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA35", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_9->PCIE_CFGERRAERHEADERLOG35": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG35", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_16->PCIE_MIMRXRDATA4": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRD->PCIE_LOGIC_OUTS_B19_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_11", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRD", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR46->PCIE_LOGIC_OUTS_B11_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_8", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR46", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_0->PCIE_CFGERRAERHEADERLOG71": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG71", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_1->PCIE_MIMTXRDATA4": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_L_10->PCIE_PIPERX1DATA3": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DRPDO7->PCIE_LOGIC_OUTS_B20_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_19", - "is_directional": "1", - "src_wire": "PCIE_DRPDO7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_7->PCIE_TRNTD113": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD113", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_8->PCIE_CFGERRAERHEADERLOG39": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG39", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_14->PCIE_PIPERX6DATA14": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD21->PCIE_LOGIC_OUTS_B2_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_10", - "is_directional": "1", - "src_wire": "PCIE_TRNRD21", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA11->PCIE_LOGIC_OUTS_B15_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_5", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_2->PCIE_MIMTXRDATA54": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA54", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_13->PCIE_CFGINTERRUPTASSERTN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGINTERRUPTASSERTN", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_19->PCIE_PIPERX0DATA10": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0DATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA8->PCIE_LOGIC_OUTS_B9_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_16", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_19->PCIE_CFGERRTLPCPLHEADER22": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER22", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_8->PCIE_CFGERRAERHEADERLOG108": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG108", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_4->PCIE_TRNTD102": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD102", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTD->PCIE_LOGIC_OUTS_B12_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_18", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTD", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_19->PCIE_TRNTDLLPDATA15": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_5->PCIE_CFGERRAERHEADERLOG50": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG50", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_18->PCIE_CFGDSN50": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN50", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD26->PCIE_LOGIC_OUTS_B7_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_11", - "is_directional": "1", - "src_wire": "PCIE_TRNRD26", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_16->PCIE_CFGDSN44": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN44", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA6->PCIE_LOGIC_OUTS_B2_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_8->PCIE_CFGDSN12": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN12", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR7->PCIE_LOGIC_OUTS_B17_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO8->PCIE_LOGIC_OUTS_B12_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_12", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA56->PCIE_LOGIC_OUTS_B10_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_0", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA56", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_16->PCIE_PIPERX6DATA4": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_3->PCIE_MIMTXRDATA50": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA50", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_8->PCIE_CFGERRAERHEADERLOG106": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG106", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_19->PCIE_CFGDSN54": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN54", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX21_R_13->PCIE_DBGMODE1": { - "can_invert": "0", - "dst_wire": "PCIE_DBGMODE1", - "is_directional": "1", - "src_wire": "PCIE_IMUX21_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_1->PCIE_CFGPMHALTASPML1N": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPMHALTASPML1N", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_9->PCIE_CFGERRAERHEADERLOG36": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG36", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA26->PCIE_LOGIC_OUTS_B8_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA26", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX20_R_12->PCIE_CFGVENDID9": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID9", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_2->PCIE_MIMTXRDATA57": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA57", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA60->PCIE_LOGIC_OUTS_B12_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_1", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA60", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA0->PCIE_LOGIC_OUTS_B9_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_11->PCIE_CFGERRAERHEADERLOG27": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG27", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD8->PCIE_LOGIC_OUTS_B7_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_10", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_9->PCIE_PIPERX5PHYSTATUS": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5PHYSTATUS", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA10->PCIE_LOGIC_OUTS_B11_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_5", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO3->PCIE_LOGIC_OUTS_B13_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_11", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC11->PCIE_LOGIC_OUTS_B18_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_10", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1CHARISK0->PCIE_LOGIC_OUTS_B16_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1CHARISK0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD5->PCIE_LOGIC_OUTS_B3_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_1", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX20_R_2->PCIE_CFGDSDEVICENUMBER3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSDEVICENUMBER3", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA9->PCIE_LOGIC_OUTS_B7_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA9->PCIE_LOGIC_OUTS_B13_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_1", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_9->PCIE_TRNTD121": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD121", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPH2->PCIE_LOGIC_OUTS_B12_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_2", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPH2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_5->PCIE_CFGERRAERHEADERLOG96": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG96", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA28->PCIE_LOGIC_OUTS_B4_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA28", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_6->PCIE_CFGERRAERHEADERLOG48": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG48", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA60->PCIE_LOGIC_OUTS_B20_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_9", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA60", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO6->PCIE_LOGIC_OUTS_B8_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_12", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRSRCDSC->PCIE_LOGIC_OUTS_B3_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_10", - "is_directional": "1", - "src_wire": "PCIE_TRNRSRCDSC", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_12->PCIE_TRNTECRCGEN": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTECRCGEN", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_L_10->PCIE_PIPERX1DATA1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_18->PCIE_TRNTD42": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD42", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD0->PCIE_LOGIC_OUTS_B19_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_14", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_17->PCIE_DRPADDR1": { - "can_invert": "0", - "dst_wire": "PCIE_DRPADDR1", - "is_directional": "1", - "src_wire": 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"is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR49->PCIE_LOGIC_OUTS_B10_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_9", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR49", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_0->PCIE_TRNTD89": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD89", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD106->PCIE_LOGIC_OUTS_B5_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRD106", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA7->PCIE_LOGIC_OUTS_B6_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA6->PCIE_LOGIC_OUTS_B2_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA0->PCIE_LOGIC_OUTS_B9_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA58->PCIE_LOGIC_OUTS_B14_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_9", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA58", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR30->PCIE_LOGIC_OUTS_B13_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_4", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR30", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA44->PCIE_LOGIC_OUTS_B18_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA44", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA49->PCIE_LOGIC_OUTS_B21_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_12", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA49", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA42->PCIE_LOGIC_OUTS_B14_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_15", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA42", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA45->PCIE_LOGIC_OUTS_B17_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_3", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA45", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA52->PCIE_LOGIC_OUTS_B12_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_0", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA52", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA2->PCIE_LOGIC_OUTS_B11_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_15->PCIE_MIMRXRDATA0": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_12->PCIE_CFGSUBSYSVENDID8": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID8", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_9->PCIE_CFGERRAERHEADERLOG112": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG112", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_9->PCIE_MIMTXRDATA66": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA66", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLAUXPOWEREN->PCIE_LOGIC_OUTS_B19_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_15", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLAUXPOWEREN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA12->PCIE_LOGIC_OUTS_B0_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_R_4->PCIE_PIPERX7DATA11": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPERX1POLARITY->PCIE_LOGIC_OUTS_B1_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_7", - "is_directional": "1", - "src_wire": "PCIE_PIPERX1POLARITY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR28->PCIE_LOGIC_OUTS_B17_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_3", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR28", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_15->PCIE_TRNTD57": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD57", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA22->PCIE_LOGIC_OUTS_B21_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_19", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA22", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA3->PCIE_LOGIC_OUTS_B7_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_7", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_13->PCIE_CFGINTERRUPTDI5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGINTERRUPTDI5", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX19_L_0->PCIE_CFGPORTNUMBER6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPORTNUMBER6", - "is_directional": "1", - "src_wire": "PCIE_IMUX19_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_14->PCIE_CFGDSN36": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN36", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_8->PCIE_PIPERX5STATUS2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5STATUS2", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_17->PCIE_DRPADDR0": { - "can_invert": "0", - "dst_wire": "PCIE_DRPADDR0", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA8->PCIE_LOGIC_OUTS_B9_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_1", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB59->PCIE_LOGIC_OUTS_B18_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_6", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB59", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB40->PCIE_LOGIC_OUTS_B19_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_1", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB40", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB36->PCIE_LOGIC_OUTS_B20_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_0", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB36", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA27->PCIE_LOGIC_OUTS_B10_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA27", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD53->PCIE_LOGIC_OUTS_B4_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRD53", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA8->PCIE_LOGIC_OUTS_B6_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_12->PCIE_CFGERRAERHEADERLOG22": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG22", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR18->PCIE_LOGIC_OUTS_B4_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_1", - "is_directional": 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"PCIE_IMUX12_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_15->PCIE_PIPERX2DATA10": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_12->PCIE_CFGERRAERHEADERLOG24": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG24", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_3->PCIE_MIMTXRDATA13": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB58->PCIE_LOGIC_OUTS_B21_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_5", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB58", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB22->PCIE_LOGIC_OUTS_B7_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_4", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB22", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_17->PCIE_CFGERRINTERNALCORN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRINTERNALCORN", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD22->PCIE_LOGIC_OUTS_B3_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_10", - "is_directional": "1", - "src_wire": "PCIE_TRNRD22", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_13->PCIE_CFGMGMTDWADDR9": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR9", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_R_17->PCIE_PIPERX6DATA3": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2CHARISK0->PCIE_LOGIC_OUTS_B16_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2CHARISK0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_13->PCIE_CFGERRTLPCPLHEADER0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER0", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_16->PCIE_CFGERRACSN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRACSN", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA8->PCIE_LOGIC_OUTS_B9_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_5", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA60->PCIE_LOGIC_OUTS_B6_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_18", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA60", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX20_L_0->PCIE_CFGPORTNUMBER7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPORTNUMBER7", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_7->PCIE_CFGERRAERHEADERLOG44": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG44", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_17->PCIE_CFGDSN48": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN48", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_4->PCIE_PIPERX7STATUS0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7STATUS0", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA18->PCIE_LOGIC_OUTS_B6_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_12->PCIE_CFGDSBUSNUMBER1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSBUSNUMBER1", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_9->PCIE_PIPERX5DATA5": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD38->PCIE_LOGIC_OUTS_B5_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRD38", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA23->PCIE_LOGIC_OUTS_B22_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_19", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA23", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_L_6->PCIE_PIPERX3DATA0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR19->PCIE_LOGIC_OUTS_B8_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_1", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_0->PCIE_PLDIRECTEDLINKWIDTH1": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLINKWIDTH1", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_12->PCIE_CFGDSN25": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN25", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA63->PCIE_LOGIC_OUTS_B15_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_8", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA63", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_2->PCIE_TRNTD92": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD92", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_18->PCIE_CFGDSN52": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN52", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_15->PCIE_PIPERX2STATUS2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2STATUS2", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_19->PCIE_TRNTD7": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD7", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_0->PCIE_MIMTXRDATA64": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA64", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA1->PCIE_LOGIC_OUTS_B13_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_L_4->PCIE_PIPERX3DATA11": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_6->PCIE_CFGERRAERHEADERLOG99": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG99", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_12->PCIE_CFGERRAERHEADERLOG23": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG23", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX19_R_2->PCIE_CFGERRAERHEADERLOG65": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG65", - "is_directional": "1", - "src_wire": "PCIE_IMUX19_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR1->PCIE_LOGIC_OUTS_B6_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_1", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_5->PCIE_MIMTXRDATA21": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA21", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD102->PCIE_LOGIC_OUTS_B6_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRD102", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR11->PCIE_LOGIC_OUTS_B9_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_9", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLDBGVEC4->PCIE_LOGIC_OUTS_B23_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_16", - "is_directional": "1", - "src_wire": "PCIE_PLDBGVEC4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_17->PCIE_TRNTDLLPDATA7": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC2->PCIE_LOGIC_OUTS_B21_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_7", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTRDWRDONEN->PCIE_LOGIC_OUTS_B16_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_12", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTRDWRDONEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_9->PCIE_CFGDSN15": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN15", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_18->PCIE_MIMRXRDATA12": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA12", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA15->PCIE_LOGIC_OUTS_B6_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_11->PCIE_CFGDSBUSNUMBER4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSBUSNUMBER4", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_6->PCIE_CFGSUBSYSID8": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID8", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_14->PCIE_CFGMGMTWRREADONLYN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTWRREADONLYN", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_10->PCIE_CFGSUBSYSVENDID1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID1", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_1->PCIE_CFGREVID1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGREVID1", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD43->PCIE_LOGIC_OUTS_B0_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRD43", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_8->PCIE_PIPERX5DATA10": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD3->PCIE_LOGIC_OUTS_B6_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_9", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6CHARISK1->PCIE_LOGIC_OUTS_B16_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6CHARISK1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_14->PCIE_CFGERRMALFORMEDN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRMALFORMEDN", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD0->PCIE_LOGIC_OUTS_B5_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_3", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRE->PCIE_LOGIC_OUTS_B20_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_11", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR21->PCIE_LOGIC_OUTS_B12_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_1", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR21", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPERX5POLARITY->PCIE_LOGIC_OUTS_B1_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_7", - "is_directional": "1", - "src_wire": "PCIE_PIPERX5POLARITY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_11->PCIE_CFGERRAERHEADERLOG118": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG118", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRBARHIT0->PCIE_LOGIC_OUTS_B0_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_9", - "is_directional": "1", - "src_wire": "PCIE_TRNRBARHIT0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_1->PCIE_CFGERRAERHEADERLOG81": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG81", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPH4->PCIE_LOGIC_OUTS_B14_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_2", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPH4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRSOF->PCIE_LOGIC_OUTS_B5_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_11", - "is_directional": "1", - "src_wire": "PCIE_TRNRSOF", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD1->PCIE_LOGIC_OUTS_B2_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_5", - "is_directional": "1", - "src_wire": "PCIE_TRNRD1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETXRATE->PCIE_LOGIC_OUTS_B19_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETXRATE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRCOR->PCIE_LOGIC_OUTS_B14_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_15", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDERRCOR", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_9->PCIE_PIPERX1CHANISALIGNED": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1CHANISALIGNED", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB50->PCIE_LOGIC_OUTS_B21_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_3", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB50", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR8->PCIE_LOGIC_OUTS_B22_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_3", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_15->PCIE_CFGERRECRCN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRECRCN", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTA->PCIE_LOGIC_OUTS_B12_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTA", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_14->PCIE_CFGERRTLPCPLHEADER3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER3", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_1->PCIE_CFGERRAERHEADERLOG66": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG66", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3COMPLIANCE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA13->PCIE_LOGIC_OUTS_B17_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_14", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB24->PCIE_LOGIC_OUTS_B12_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_4", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB24", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD2->PCIE_LOGIC_OUTS_B0_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_1", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_1->PCIE_TRNTD83": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD83", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO4->PCIE_LOGIC_OUTS_B14_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_11", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_5->PCIE_MIMTXRDATA20": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA20", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_15->PCIE_CFGERRURN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRURN", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_9->PCIE_PIPERX1DATA5": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX18_R_2->PCIE_CFGERRAERHEADERLOG64": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG64", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4ELECIDLE->PCIE_LOGIC_OUTS_B3_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4ELECIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA11->PCIE_LOGIC_OUTS_B14_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_14", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_R_6->PCIE_PIPERX7DATA3": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_2->PCIE_CFGMGMTDI0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI0", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2BADDLLPERR->PCIE_LOGIC_OUTS_B14_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_13", - "is_directional": "1", - "src_wire": "PCIE_LL2BADDLLPERR", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD4->PCIE_LOGIC_OUTS_B7_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_9", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_10->PCIE_CFGDSN20": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN20", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_14->PCIE_CFGINTERRUPTDI4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGINTERRUPTDI4", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB56->PCIE_LOGIC_OUTS_B19_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_5", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB56", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPH1->PCIE_LOGIC_OUTS_B6_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_7", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPH1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_8->PCIE_CFGMGMTDI25": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI25", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_15->PCIE_TRNFCSEL2": { - "can_invert": "0", - "dst_wire": "PCIE_TRNFCSEL2", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_15->PCIE_CFGDSN38": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN38", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA1->PCIE_LOGIC_OUTS_B19_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR9->PCIE_LOGIC_OUTS_B3_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTDO2->PCIE_LOGIC_OUTS_B13_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_8", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTDO2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_4->PCIE_PIPERX3ELECIDLE": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3ELECIDLE", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA10->PCIE_LOGIC_OUTS_B23_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_6->PCIE_CFGDSN3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN3", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLH1->PCIE_LOGIC_OUTS_B6_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_7", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLH1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB0->PCIE_LOGIC_OUTS_B16_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_8", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWADDR10->PCIE_LOGIC_OUTS_B12_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWADDR10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_15->PCIE_PIPERX6STATUS0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6STATUS0", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_5->PCIE_TRNTD107": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD107", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA68->PCIE_LOGIC_OUTS_B5_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_2", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA68", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA14->PCIE_LOGIC_OUTS_B2_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRG->PCIE_LOGIC_OUTS_B22_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_11", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRG", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_12->PCIE_TRNTSRCRDY": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTSRCRDY", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA2->PCIE_LOGIC_OUTS_B11_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR37->PCIE_LOGIC_OUTS_B15_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_6", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR37", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXRADDR12->PCIE_LOGIC_OUTS_B21_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_15", - "is_directional": "1", - "src_wire": "PCIE_MIMRXRADDR12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD50->PCIE_LOGIC_OUTS_B10_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRD50", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR32->PCIE_LOGIC_OUTS_B15_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_4", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR32", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD110->PCIE_LOGIC_OUTS_B0_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRD110", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_15->PCIE_PIPERX6DATA8": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA8", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_14->PCIE_PIPERX6DATA12": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA12", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA59->PCIE_LOGIC_OUTS_B19_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_9", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA59", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_14->PCIE_CFGDSN33": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN33", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_6->PCIE_CFGDSN4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN4", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR31->PCIE_LOGIC_OUTS_B14_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_4", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR31", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO2->PCIE_LOGIC_OUTS_B13_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_10", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGROOTCONTROLPMEINTEN->PCIE_LOGIC_OUTS_B16_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGROOTCONTROLPMEINTEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_10->PCIE_CFGDSN19": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN19", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_4->PCIE_PIPERX7DATA8": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA8", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA39->PCIE_LOGIC_OUTS_B21_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_2", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA39", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_5->PCIE_TRNTD105": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD105", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD42->PCIE_LOGIC_OUTS_B7_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRD42", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_1->PCIE_CFGREVID0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGREVID0", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE2->PCIE_LOGIC_OUTS_B16_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_1", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTMMENABLE2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_10->PCIE_TRNTD125": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD125", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_3->PCIE_MIMTXRDATA14": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_13->PCIE_TRNTD65": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD65", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_19->PCIE_PIPERX4ELECIDLE": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4ELECIDLE", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_7->PCIE_CFGERRAERHEADERLOG45": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG45", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_5->PCIE_CFGFORCEEXTENDEDSYNCON": { - "can_invert": "0", - "dst_wire": "PCIE_CFGFORCEEXTENDEDSYNCON", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTDO5->PCIE_LOGIC_OUTS_B12_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_9", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTDO5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_7->PCIE_CFGMGMTDI21": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI21", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPERX3POLARITY->PCIE_LOGIC_OUTS_B1_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_3", - "is_directional": "1", - "src_wire": "PCIE_PIPERX3POLARITY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA10->PCIE_LOGIC_OUTS_B11_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_12", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_L_6->PCIE_PIPERX3DATA3": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTBUFAV1->PCIE_LOGIC_OUTS_B5_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_3", - "is_directional": "1", - "src_wire": "PCIE_TRNTBUFAV1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB29->PCIE_LOGIC_OUTS_B20_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_3", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB29", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7COMPLIANCE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_10->PCIE_PIPERX5DATA0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_10->PCIE_CFGSUBSYSVENDID2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID2", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA33->PCIE_LOGIC_OUTS_B4_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_7", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA33", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR27->PCIE_LOGIC_OUTS_B16_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_3", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR27", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_9->PCIE_CFGERRAERHEADERLOG113": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG113", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD27->PCIE_LOGIC_OUTS_B0_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRD27", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA11->PCIE_LOGIC_OUTS_B15_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_16", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_8->PCIE_TRNTD119": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD119", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTDO6->PCIE_LOGIC_OUTS_B13_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_9", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTDO6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRB->PCIE_LOGIC_OUTS_B20_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_10", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRB", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_8->PCIE_PIPERX5DATA9": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA9", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_3->PCIE_TRNTD98": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD98", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_19->PCIE_MIMRXRDATA58": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA58", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_18->PCIE_CFGERRTLPCPLHEADER19": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER19", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_6->PCIE_MIMTXRDATA44": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA44", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR12->PCIE_LOGIC_OUTS_B8_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_7", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_19->PCIE_MIMRXRDATA16": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA16", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_13->PCIE_CFGDSN29": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN29", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_6->PCIE_MIMTXRDATA26": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA26", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_18->PCIE_MIMRXRDATA60": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA60", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3CHARISK0->PCIE_LOGIC_OUTS_B16_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3CHARISK0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_R_19->PCIE_PIPERX4DATA11": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4DATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_16->PCIE_MIMRXRDATA6": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2REPLAYTOERR->PCIE_LOGIC_OUTS_B5_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_12", - "is_directional": "1", - "src_wire": "PCIE_LL2REPLAYTOERR", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB21->PCIE_LOGIC_OUTS_B18_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_5", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB21", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD37->PCIE_LOGIC_OUTS_B4_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRD37", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7POWERDOWN1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_14->PCIE_TRNRNPOK": { - "can_invert": "0", - "dst_wire": "PCIE_TRNRNPOK", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2ELECIDLE->PCIE_LOGIC_OUTS_B3_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2ELECIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETOACK->PCIE_LOGIC_OUTS_B16_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_18", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDPMETOACK", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA3->PCIE_LOGIC_OUTS_B7_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR58->PCIE_LOGIC_OUTS_B15_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_11", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR58", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD9->PCIE_LOGIC_OUTS_B4_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_7", - "is_directional": "1", - "src_wire": "PCIE_TRNRD9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA15->PCIE_LOGIC_OUTS_B6_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_4", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_0->PCIE_TRNTD88": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD88", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_3->PCIE_PIPERX3DATA15": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB45->PCIE_LOGIC_OUTS_B20_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_2", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB45", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPERX2POLARITY->PCIE_LOGIC_OUTS_B1_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_14", - "is_directional": "1", - "src_wire": "PCIE_PIPERX2POLARITY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_6->PCIE_CFGMGMTDI17": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI17", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD48->PCIE_LOGIC_OUTS_B8_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRD48", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA24->PCIE_LOGIC_OUTS_B6_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA24", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2RECEIVERERR->PCIE_LOGIC_OUTS_B11_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_13", - "is_directional": "1", - "src_wire": "PCIE_LL2RECEIVERERR", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR62->PCIE_LOGIC_OUTS_B14_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_12", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR62", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_9->PCIE_CFGERRAERHEADERLOG111": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG111", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DRPDO8->PCIE_LOGIC_OUTS_B21_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_19", - "is_directional": "1", - "src_wire": "PCIE_DRPDO8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR59->PCIE_LOGIC_OUTS_B8_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_12", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR59", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTCFGREQ->PCIE_LOGIC_OUTS_B0_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_5", - "is_directional": "1", - "src_wire": "PCIE_TRNTCFGREQ", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PL2L0REQ->PCIE_LOGIC_OUTS_B20_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_19", - "is_directional": "1", - "src_wire": "PCIE_PL2L0REQ", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_5->PCIE_MIMTXRDATA49": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA49", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA7->PCIE_LOGIC_OUTS_B6_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB31->PCIE_LOGIC_OUTS_B13_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_2", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB31", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_12->PCIE_TRNTD68": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD68", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD15->PCIE_LOGIC_OUTS_B0_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_9", - "is_directional": "1", - "src_wire": "PCIE_TRNRD15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_13->PCIE_CFGERRTLPCPLHEADER1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER1", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_17->PCIE_CFGERRTLPCPLHEADER17": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER17", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_9->PCIE_CFGDSN14": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN14", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_1->PCIE_CFGPMHALTASPML0SN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPMHALTASPML0SN", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD28->PCIE_LOGIC_OUTS_B1_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRD28", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR2->PCIE_LOGIC_OUTS_B12_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_7", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_11->PCIE_CFGMGMTBYTEENN3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTBYTEENN3", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_19->PCIE_MIMRXRDATA18": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA18", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_14->PCIE_CFGAERINTERRUPTMSGNUM2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM2", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA12->PCIE_LOGIC_OUTS_B10_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA5->PCIE_LOGIC_OUTS_B4_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2BADTLPERR->PCIE_LOGIC_OUTS_B13_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_13", - "is_directional": "1", - "src_wire": "PCIE_LL2BADTLPERR", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKCONTROLASPMCONTROL0->PCIE_LOGIC_OUTS_B15_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKCONTROLASPMCONTROL0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_6->PCIE_PIPERX7DATA1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVSTATUSCORRERRDETECTED->PCIE_LOGIC_OUTS_B16_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_9", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVSTATUSCORRERRDETECTED", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_16->PCIE_TRNTD53": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD53", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_0->PCIE_PLDIRECTEDLINKCHANGE0": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLINKCHANGE0", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB30->PCIE_LOGIC_OUTS_B12_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_2", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB30", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_10->PCIE_CFGERRAERHEADERLOG115": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG115", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_12->PCIE_TRNTD69": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD69", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_6->PCIE_MIMTXRDATA47": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA47", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2LINKSTATUS2->PCIE_LOGIC_OUTS_B3_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_16", - "is_directional": "1", - "src_wire": "PCIE_LL2LINKSTATUS2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB3->PCIE_LOGIC_OUTS_B22_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_10", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA0->PCIE_LOGIC_OUTS_B17_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB38->PCIE_LOGIC_OUTS_B22_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_0", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB38", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD104->PCIE_LOGIC_OUTS_B2_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRD104", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPH5->PCIE_LOGIC_OUTS_B6_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_3", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPH5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_5->PCIE_PIPERX3DATA7": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_7->PCIE_PIPERX1DATA13": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD12->PCIE_LOGIC_OUTS_B1_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_8", - "is_directional": "1", - "src_wire": "PCIE_TRNRD12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_1->PCIE_PLDIRECTEDLTSSMNEW4": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW4", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLTSSMSTATE5->PCIE_LOGIC_OUTS_B12_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLLTSSMSTATE5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD3->PCIE_LOGIC_OUTS_B5_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_6", - "is_directional": "1", - "src_wire": "PCIE_TRNRD3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_9->PCIE_CFGSUBSYSID14": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID14", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_13->PCIE_CFGERRAERHEADERLOG20": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG20", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLINKPARTNERGEN2SUPPORTED->PCIE_LOGIC_OUTS_B5_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_2", - "is_directional": "1", - "src_wire": "PCIE_PLLINKPARTNERGEN2SUPPORTED", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLINKUPCFGCAP->PCIE_LOGIC_OUTS_B2_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_1", - "is_directional": "1", - "src_wire": "PCIE_PLLINKUPCFGCAP", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_4->PCIE_PIPERX7CHARISK1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7CHARISK1", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA4->PCIE_LOGIC_OUTS_B0_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA13->PCIE_LOGIC_OUTS_B4_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_1->PCIE_MIMTXRDATA58": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA58", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_16->PCIE_PIPERX2DATA4": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB8->PCIE_LOGIC_OUTS_B22_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_15", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB60->PCIE_LOGIC_OUTS_B19_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_6", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB60", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_7->PCIE_CFGDSN5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN5", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_12->PCIE_CFGERRAERHEADERLOG123": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG123", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_18->PCIE_PIPERX4DATA12": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4DATA12", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA8->PCIE_LOGIC_OUTS_B9_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_1", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2SUSPENDOK->PCIE_LOGIC_OUTS_B12_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_17", - "is_directional": "1", - "src_wire": "PCIE_LL2SUSPENDOK", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA61->PCIE_LOGIC_OUTS_B12_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA61", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2CHARISK1->PCIE_LOGIC_OUTS_B16_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2CHARISK1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_8->PCIE_TRNTD116": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD116", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD7->PCIE_LOGIC_OUTS_B0_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_7", - "is_directional": "1", - "src_wire": "PCIE_TRNRD7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_4->PCIE_CFGMGMTDI7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI7", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_5->PCIE_PIPERX7PHYSTATUS": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7PHYSTATUS", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_3->PCIE_PIPERX7DATA15": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA40->PCIE_LOGIC_OUTS_B1_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_0", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA40", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_11->PCIE_CFGMGMTDWADDR0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR0", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_L_16->PCIE_PIPERX2VALID": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2VALID", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX21_R_12->PCIE_DBGSUBMODE": { - "can_invert": "0", - "dst_wire": "PCIE_DBGSUBMODE", - "is_directional": "1", - "src_wire": "PCIE_IMUX21_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_16->PCIE_TRNTDLLPDATA6": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA7->PCIE_LOGIC_OUTS_B19_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_8", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD10->PCIE_LOGIC_OUTS_B5_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_7", - "is_directional": "1", - "src_wire": "PCIE_TRNRD10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA17->PCIE_LOGIC_OUTS_B5_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_7", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_5->PCIE_MIMTXRDATA48": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA48", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA13->PCIE_LOGIC_OUTS_B4_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_4", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPD11->PCIE_LOGIC_OUTS_B13_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_6", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX19_R_13->PCIE_CFGVENDID4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID4", - "is_directional": "1", - "src_wire": "PCIE_IMUX19_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA54->PCIE_LOGIC_OUTS_B18_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_10", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA54", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_14->PCIE_CFGERRAERHEADERLOG14": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG14", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_L_9->PCIE_PIPERX1PHYSTATUS": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1PHYSTATUS", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD16->PCIE_LOGIC_OUTS_B1_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_9", - "is_directional": "1", - "src_wire": "PCIE_TRNRD16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR8->PCIE_LOGIC_OUTS_B8_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_10", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_8->PCIE_PIPERX1STATUS2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1STATUS2", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_4->PCIE_CFGFORCEMPS1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGFORCEMPS1", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD125->PCIE_LOGIC_OUTS_B1_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRD125", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA58->PCIE_LOGIC_OUTS_B15_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_15", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA58", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_1->PCIE_CFGREVID2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGREVID2", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVSTATUSNONFATALERRDETECTED->PCIE_LOGIC_OUTS_B17_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_9", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA47->PCIE_LOGIC_OUTS_B18_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA47", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO1->PCIE_LOGIC_OUTS_B12_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_10", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_2->PCIE_TRNTD94": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD94", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA5->PCIE_LOGIC_OUTS_B4_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_18->PCIE_CFGDSN51": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN51", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_15->PCIE_PIPERX6CHARISK1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6CHARISK1", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0CHARISK0->PCIE_LOGIC_OUTS_B16_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0CHARISK0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_5->PCIE_PIPERX3DATA6": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLDBGVEC6->PCIE_LOGIC_OUTS_B23_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_17", - "is_directional": "1", - "src_wire": "PCIE_PLDBGVEC6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_0->PCIE_PLDIRECTEDLTSSMNEW3": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW3", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA1->PCIE_LOGIC_OUTS_B13_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_7", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_15->PCIE_TRNTDLLPDATA1": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_5->PCIE_PIPERX7VALID": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7VALID", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_15->PCIE_CFGERRTLPCPLHEADER9": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER9", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA0->PCIE_LOGIC_OUTS_B9_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_14", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0CHARISK1->PCIE_LOGIC_OUTS_B16_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0CHARISK1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_5->PCIE_CFGSUBSYSID4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID4", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_12->PCIE_CFGMGMTDWADDR3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR3", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA7->PCIE_LOGIC_OUTS_B17_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_12", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_10->PCIE_PIPERX5DATA1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_15->PCIE_MIMRXRDATA3": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA31->PCIE_LOGIC_OUTS_B22_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_17", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA31", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_3->PCIE_MIMTXRDATA52": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA52", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_13->PCIE_CFGDSN32": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN32", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA15->PCIE_LOGIC_OUTS_B6_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLINITIALLINKWIDTH1->PCIE_LOGIC_OUTS_B9_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_2", - "is_directional": "1", - "src_wire": "PCIE_PLINITIALLINKWIDTH1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA38->PCIE_LOGIC_OUTS_B19_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_14", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA38", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_15->PCIE_CFGERRCORN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRCORN", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_9->PCIE_CFGERRAERHEADERLOG34": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG34", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_9->PCIE_PIPERX1DATA6": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR6->PCIE_LOGIC_OUTS_B6_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_10", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_13->PCIE_CFGINTERRUPTDI6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGINTERRUPTDI6", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR8->PCIE_LOGIC_OUTS_B12_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_3", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA2->PCIE_LOGIC_OUTS_B11_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA40->PCIE_LOGIC_OUTS_B13_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_15", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA40", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA34->PCIE_LOGIC_OUTS_B15_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA34", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR42->PCIE_LOGIC_OUTS_B17_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_7", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR42", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_2->PCIE_MIMTXRDATA55": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA55", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA1->PCIE_LOGIC_OUTS_B13_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLDBGVEC3->PCIE_LOGIC_OUTS_B22_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_16", - "is_directional": "1", - "src_wire": "PCIE_PLDBGVEC3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR56->PCIE_LOGIC_OUTS_B13_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_11", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR56", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_11->PCIE_CFGERRAERHEADERLOG121": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG121", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR4->PCIE_LOGIC_OUTS_B11_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_11", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_11->PCIE_CFGMGMTDWADDR1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR1", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD56->PCIE_LOGIC_OUTS_B1_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRD56", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_1->PCIE_MIMTXRDATA59": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA59", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_16->PCIE_PIPERX2DATA7": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_11->PCIE_CFGDSN21": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN21", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_17->PCIE_CFGDSN47": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN47", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_18->PCIE_CFGERRTLPCPLHEADER20": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER20", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_L_0->PCIE_CFGERRAERHEADERLOG77": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG77", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLDBGVEC7->PCIE_LOGIC_OUTS_B23_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_18", - "is_directional": "1", - "src_wire": "PCIE_PLDBGVEC7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB9->PCIE_LOGIC_OUTS_B22_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_18", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA2->PCIE_LOGIC_OUTS_B11_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_14", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_10->PCIE_CFGERRAERHEADERLOG32": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG32", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_18->PCIE_TRNTD43": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD43", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR26->PCIE_LOGIC_OUTS_B14_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_3", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR26", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_14->PCIE_CFGERRTLPCPLHEADER2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER2", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR53->PCIE_LOGIC_OUTS_B10_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_10", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR53", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_2->PCIE_MIMTXRDATA9": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA9", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_6->PCIE_MIMTXRDATA45": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA45", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA5->PCIE_LOGIC_OUTS_B4_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_9", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA23->PCIE_LOGIC_OUTS_B20_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_8", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA23", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_19->PCIE_PIPERX4DATA9": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4DATA9", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA54->PCIE_LOGIC_OUTS_B13_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_0", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA54", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_6->PCIE_TRNTD108": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD108", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD1->PCIE_LOGIC_OUTS_B20_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_14", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA12->PCIE_LOGIC_OUTS_B0_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLSELLNKWIDTH1->PCIE_LOGIC_OUTS_B5_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLSELLNKWIDTH1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_14->PCIE_CFGDSN35": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN35", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD29->PCIE_LOGIC_OUTS_B2_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRD29", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPD5->PCIE_LOGIC_OUTS_B4_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_5", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_L_10->PCIE_PIPERX1CHARISK0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1CHARISK0", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB7->PCIE_LOGIC_OUTS_B23_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_14", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR11->PCIE_LOGIC_OUTS_B2_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_3", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_18->PCIE_CFGERRTLPCPLHEADER21": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER21", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_13->PCIE_TRNRDSTRDY": { - "can_invert": "0", - "dst_wire": "PCIE_TRNRDSTRDY", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD108->PCIE_LOGIC_OUTS_B9_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRD108", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA32->PCIE_LOGIC_OUTS_B19_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_7", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA32", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_5->PCIE_CFGERRAERHEADERLOG53": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG53", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX20_R_11->PCIE_CFGVENDID13": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID13", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_4->PCIE_CFGMGMTDI8": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI8", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA31->PCIE_LOGIC_OUTS_B7_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA31", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_11->PCIE_CFGERRAERHEADERLOG26": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG26", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_11->PCIE_TRNTD73": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD73", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA6->PCIE_LOGIC_OUTS_B2_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_12->PCIE_TRNTD66": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD66", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_19->PCIE_TRNTD4": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD4", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_6->PCIE_CFGSUBSYSID7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID7", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD47->PCIE_LOGIC_OUTS_B5_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRD47", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3->PCIE_LOGIC_OUTS_B20_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_18", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_7->PCIE_TRNTD112": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD112", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_0->PCIE_PLDIRECTEDLTSSMNEW1": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW1", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_10->PCIE_CFGERRAERHEADERLOG31": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG31", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB39->PCIE_LOGIC_OUTS_B18_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_1", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB39", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_6->PCIE_CFGERRAERHEADERLOG101": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG101", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK->PCIE_LOGIC_OUTS_B21_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_15", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_16->PCIE_CFGDSN42": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN42", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2LINKSTATUS0->PCIE_LOGIC_OUTS_B15_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_17", - "is_directional": "1", - "src_wire": "PCIE_LL2LINKSTATUS0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_0->PCIE_MIMTXRDATA65": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA65", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWADDR3->PCIE_LOGIC_OUTS_B7_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWADDR3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_10->PCIE_CFGMGMTBYTEENN0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTBYTEENN0", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA67->PCIE_LOGIC_OUTS_B14_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_17", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA67", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_3->PCIE_CFGMGMTDI4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI4", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVED->PCIE_LOGIC_OUTS_B15_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_9", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVED", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CLK0_R_11->PCIE_PIPECLK": { - "can_invert": "0", - "dst_wire": "PCIE_PIPECLK", - "is_directional": "1", - "src_wire": "PCIE_CLK0_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO0->PCIE_LOGIC_OUTS_B11_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_10", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_12->PCIE_CFGDSN28": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN28", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_15->PCIE_PIPERX2STATUS0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2STATUS0", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA13->PCIE_LOGIC_OUTS_B4_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_16->PCIE_PIPERX6DATA6": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5POWERDOWN0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_8->PCIE_MIMTXRDATA34": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA34", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_15->PCIE_PIPERX6STATUS2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6STATUS2", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_8->PCIE_CFGDSN10": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN10", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPH0->PCIE_LOGIC_OUTS_B7_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_1", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPH0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_13->PCIE_CFGERRAERHEADERLOG21": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG21", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_15->PCIE_TRNTDLLPDATA0": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_4->PCIE_TRNTD103": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD103", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_2->PCIE_CFGPMTURNOFFOKN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPMTURNOFFOKN", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_0->PCIE_CFGPORTNUMBER0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPORTNUMBER0", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA5->PCIE_LOGIC_OUTS_B4_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLH7->PCIE_LOGIC_OUTS_B6_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_8", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLH7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6ELECIDLE->PCIE_LOGIC_OUTS_B3_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6ELECIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_1->PCIE_CFGERRAERHEADERLOG67": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG67", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0POWERDOWN1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA47->PCIE_LOGIC_OUTS_B19_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_12", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA47", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_7->PCIE_MIMTXRDATA40": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA40", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA56->PCIE_LOGIC_OUTS_B6_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA56", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_12->PCIE_TRNTSRCDSC": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTSRCDSC", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_0->PCIE_MIMTXRDATA0": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_18->PCIE_TRNTDLLPDATA12": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA12", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB27->PCIE_LOGIC_OUTS_B8_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_3", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB27", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_L_17->PCIE_PIPERX2CHARISK0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2CHARISK0", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA48->PCIE_LOGIC_OUTS_B20_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_12", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA48", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_4->PCIE_CFGMGMTDI10": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI10", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_14->PCIE_CFGMGMTRDENN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTRDENN", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA16->PCIE_LOGIC_OUTS_B1_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRECRCERR->PCIE_LOGIC_OUTS_B4_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_10", - "is_directional": "1", - "src_wire": "PCIE_TRNRECRCERR", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_9->PCIE_PIPERX5CHANISALIGNED": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5CHANISALIGNED", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_8->PCIE_PIPERX1DATA10": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA0->PCIE_LOGIC_OUTS_B9_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_7", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_16->PCIE_CFGERRCPLUNEXPECTN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRCPLUNEXPECTN", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA9->PCIE_LOGIC_OUTS_B13_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_12", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_17->PCIE_PIPERX2DATA2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_8->PCIE_PIPERX1STATUS1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1STATUS1", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_10->PCIE_CFGDSDEVICENUMBER2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSDEVICENUMBER2", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRSRCRDY->PCIE_LOGIC_OUTS_B0_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_10", - "is_directional": "1", - "src_wire": "PCIE_TRNRSRCRDY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX20_R_0->PCIE_CFGVENDID15": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID15", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR20->PCIE_LOGIC_OUTS_B10_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_1", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR20", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_7->PCIE_CFGSUBSYSID13": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID13", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXREN->PCIE_LOGIC_OUTS_B8_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXREN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC3->PCIE_LOGIC_OUTS_B18_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_8", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA31->PCIE_LOGIC_OUTS_B7_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_9", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA31", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX20_R_1->PCIE_CFGVENDID14": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID14", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA1->PCIE_LOGIC_OUTS_B13_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTDO0->PCIE_LOGIC_OUTS_B17_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_5", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTDO0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA3->PCIE_LOGIC_OUTS_B15_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_10", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_19->PCIE_MIMRXRDATA17": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA17", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA4->PCIE_LOGIC_OUTS_B11_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXRADDR5->PCIE_LOGIC_OUTS_B8_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXRADDR5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR63->PCIE_LOGIC_OUTS_B15_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_13", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR63", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWADDR6->PCIE_LOGIC_OUTS_B17_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_17", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWADDR6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_17->PCIE_CFGERRMCBLOCKEDN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRMCBLOCKEDN", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_3->PCIE_CFGSUBSYSID3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID3", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DRPDO10->PCIE_LOGIC_OUTS_B23_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_19", - "is_directional": "1", - "src_wire": "PCIE_DRPDO10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_3->PCIE_CFGERRAERHEADERLOG89": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG89", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_18->PCIE_PIPERX0DATA14": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0DATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_5->PCIE_PIPERX7DATA6": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_3->PCIE_CFGERRAERHEADERLOG87": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG87", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC0->PCIE_LOGIC_OUTS_B19_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_7", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWADDR0->PCIE_LOGIC_OUTS_B14_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWADDR0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_16->PCIE_CFGERRTLPCPLHEADER13": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER13", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_8->PCIE_CFGDSN11": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN11", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR1->PCIE_LOGIC_OUTS_B11_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_5->PCIE_CFGDSN0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN0", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_12->PCIE_CFGDSN27": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN27", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO5->PCIE_LOGIC_OUTS_B15_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_11", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD120->PCIE_LOGIC_OUTS_B5_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRD120", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB62->PCIE_LOGIC_OUTS_B21_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_6", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB62", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR57->PCIE_LOGIC_OUTS_B14_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_11", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR57", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_2->PCIE_TRNTD93": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD93", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA23->PCIE_LOGIC_OUTS_B14_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA23", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_6->PCIE_TRNTD110": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD110", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_11->PCIE_CFGVENDID10": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID10", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_17->PCIE_CFGDSN46": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN46", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA17->PCIE_LOGIC_OUTS_B5_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO9->PCIE_LOGIC_OUTS_B14_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_12", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_15->PCIE_PIPERX2STATUS1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2STATUS1", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRC->PCIE_LOGIC_OUTS_B21_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_10", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRC", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTB->PCIE_LOGIC_OUTS_B14_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTB", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD111->PCIE_LOGIC_OUTS_B1_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRD111", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_3->PCIE_PIPERX3DATA14": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA50->PCIE_LOGIC_OUTS_B17_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_11", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA50", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGAERECRCCHECKEN->PCIE_LOGIC_OUTS_B17_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGAERECRCCHECKEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB34->PCIE_LOGIC_OUTS_B22_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_1", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB34", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_9->PCIE_CFGSUBSYSID15": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID15", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_11->PCIE_CFGERRAERHEADERLOG119": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG119", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTA->PCIE_LOGIC_OUTS_B10_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTA", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_3->PCIE_PIPERX7DATA13": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA50->PCIE_LOGIC_OUTS_B7_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_1", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA50", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB15->PCIE_LOGIC_OUTS_B18_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_7", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_8->PCIE_CFGERRAERHEADERLOG41": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG41", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_4->PCIE_CFGERRAERHEADERLOG90": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG90", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA56->PCIE_LOGIC_OUTS_B20_R_10": { - "can_invert": "0", - "dst_wire": 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"is_directional": "1", - "src_wire": "PCIE_IMUX37_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA9->PCIE_LOGIC_OUTS_B13_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_16", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_10->PCIE_PIPERX1DATA2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA46->PCIE_LOGIC_OUTS_B19_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_1", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA46", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA15->PCIE_LOGIC_OUTS_B6_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_1->PCIE_CFGPMFORCESTATEENN": { - "can_invert": "0", - "dst_wire": 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"PCIE_LOGIC_OUTS_B14_R_3", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_13->PCIE_TRNTD63": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD63", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_9->PCIE_MIMTXRDATA39": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA39", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA7->PCIE_LOGIC_OUTS_B6_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_0->PCIE_CFGERRAERHEADERLOG75": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG75", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_L_4->PCIE_PIPERX3DATA8": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA8", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_7->PCIE_PIPERX5DATA13": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0COMPLIANCE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_18->PCIE_TRNTDLLPDATA14": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTC->PCIE_LOGIC_OUTS_B18_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_17", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTC", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLTSSMSTATE3->PCIE_LOGIC_OUTS_B10_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLLTSSMSTATE3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLINKGEN2CAP->PCIE_LOGIC_OUTS_B3_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_1", - "is_directional": "1", - "src_wire": "PCIE_PLLINKGEN2CAP", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD100->PCIE_LOGIC_OUTS_B3_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRD100", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTBUFAV0->PCIE_LOGIC_OUTS_B4_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_3", - "is_directional": "1", - "src_wire": "PCIE_TRNTBUFAV0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA39->PCIE_LOGIC_OUTS_B23_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_17", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA39", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTBUFAV5->PCIE_LOGIC_OUTS_B7_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_4", - "is_directional": "1", - "src_wire": "PCIE_TRNTBUFAV5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD52->PCIE_LOGIC_OUTS_B2_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRD52", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_16->PCIE_CFGERRAERHEADERLOG12": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG12", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ0->PCIE_LOGIC_OUTS_B16_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_10->PCIE_CFGDSN17": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN17", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD57->PCIE_LOGIC_OUTS_B2_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRD57", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_3->PCIE_PIPERX7DATA12": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA12", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_2->PCIE_TRNTD95": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD95", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD9->PCIE_LOGIC_OUTS_B4_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_1", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA53->PCIE_LOGIC_OUTS_B11_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_17", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA53", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CTRL1_R_0->PCIE_CMRSTN": { - "can_invert": "0", - "dst_wire": "PCIE_CMRSTN", - "is_directional": "1", - "src_wire": "PCIE_CTRL1_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_7->PCIE_CFGDSN7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN7", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_19->PCIE_CFGDSN55": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN55", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_4->PCIE_MIMTXRDATA16": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA16", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD11->PCIE_LOGIC_OUTS_B0_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_8", - "is_directional": "1", - "src_wire": "PCIE_TRNRD11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_15->PCIE_CFGDSN39": { - "can_invert": "0", - "dst_wire": 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"PCIE_BOT.PCIE_PIPETX6DATA15->PCIE_LOGIC_OUTS_B6_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_13->PCIE_CFGERRAERHEADERLOG126": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG126", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPERX0POLARITY->PCIE_LOGIC_OUTS_B1_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_18", - "is_directional": "1", - "src_wire": "PCIE_PIPERX0POLARITY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_19->PCIE_PIPERX4CHARISK1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4CHARISK1", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA14->PCIE_LOGIC_OUTS_B10_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA0->PCIE_LOGIC_OUTS_B9_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_L_8->PCIE_PIPERX1DATA8": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA8", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_9->PCIE_CFGMGMTDI30": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI30", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_19->PCIE_PIPERX4STATUS2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4STATUS2", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_14->PCIE_CFGERRTLPCPLHEADER5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER5", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_10->PCIE_CFGERRAERHEADERLOG116": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG116", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRK->PCIE_LOGIC_OUTS_B23_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_13", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRK", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4POWERDOWN0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_L_9->PCIE_PIPERX1VALID": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1VALID", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA25->PCIE_LOGIC_OUTS_B7_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_18", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA25", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC8->PCIE_LOGIC_OUTS_B19_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_9", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD119->PCIE_LOGIC_OUTS_B5_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRD119", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB51->PCIE_LOGIC_OUTS_B18_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_4", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB51", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7ELECIDLE->PCIE_LOGIC_OUTS_B3_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7ELECIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA3->PCIE_LOGIC_OUTS_B15_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_7", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVSTATUSFATALERRDETECTED->PCIE_LOGIC_OUTS_B16_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_10", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVSTATUSFATALERRDETECTED", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_9->PCIE_TRNTD120": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD120", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_8->PCIE_TRNTD118": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD118", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD46->PCIE_LOGIC_OUTS_B3_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRD46", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_3->PCIE_PIPERX3DATA12": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA12", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA13->PCIE_LOGIC_OUTS_B9_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_16->PCIE_PIPERX6DATA5": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB19->PCIE_LOGIC_OUTS_B7_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_5", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR61->PCIE_LOGIC_OUTS_B12_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_12", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR61", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_18->PCIE_TRNTDLLPDATA11": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLTSSMSTATE1->PCIE_LOGIC_OUTS_B8_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLLTSSMSTATE1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR13->PCIE_LOGIC_OUTS_B11_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_9", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_12->PCIE_CFGDSBUSNUMBER0": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSBUSNUMBER0", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD116->PCIE_LOGIC_OUTS_B0_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRD116", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_12->PCIE_CFGERRAERHEADERLOG124": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG124", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLRXPMSTATE0->PCIE_LOGIC_OUTS_B0_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_1", - "is_directional": "1", - "src_wire": "PCIE_PLRXPMSTATE0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_14", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6COMPLIANCE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_12->PCIE_CFGDSBUSNUMBER2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSBUSNUMBER2", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CLK1_R_12->PCIE_USERCLK2": { - "can_invert": "0", - "dst_wire": "PCIE_USERCLK2", - "is_directional": "1", - "src_wire": "PCIE_CLK1_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_11->PCIE_CFGDSBUSNUMBER6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSBUSNUMBER6", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_17->PCIE_MIMRXRDATA65": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA65", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX18_R_0->PCIE_CFGPORTNUMBER2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPORTNUMBER2", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_15->PCIE_TRNTD55": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD55", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD6->PCIE_LOGIC_OUTS_B10_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_6", - "is_directional": "1", - "src_wire": "PCIE_TRNRD6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_7->PCIE_PIPERX5DATA14": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC9->PCIE_LOGIC_OUTS_B20_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_9", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_16->PCIE_TRNTD52": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD52", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRFATALERREN->PCIE_LOGIC_OUTS_B22_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_18", - "is_directional": "1", - "src_wire": "PCIE_CFGROOTCONTROLSYSERRFATALERREN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA59->PCIE_LOGIC_OUTS_B14_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_18", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA59", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTC->PCIE_LOGIC_OUTS_B17_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_17", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTC", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_14->PCIE_CFGERRAERHEADERLOG17": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG17", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR44->PCIE_LOGIC_OUTS_B9_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_8", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR44", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_13->PCIE_CFGERRAERHEADERLOG19": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG19", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_12->PCIE_CFGMGMTDWADDR4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR4", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE0->PCIE_LOGIC_OUTS_B16_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_10", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTMMENABLE0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_9->PCIE_MIMTXRDATA37": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA37", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_15->PCIE_CFGERRCPLTIMEOUTN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRCPLTIMEOUTN", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA41->PCIE_LOGIC_OUTS_B22_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_14", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA41", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA12->PCIE_LOGIC_OUTS_B0_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_4", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_16->PCIE_MIMRXRDATA5": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_7->PCIE_CFGDSN8": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN8", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PL2RXPMSTATE1->PCIE_LOGIC_OUTS_B19_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_19", - "is_directional": "1", - "src_wire": "PCIE_PL2RXPMSTATE1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_12->PCIE_CFGMGMTDWADDR6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR6", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMASNAK->PCIE_LOGIC_OUTS_B10_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDPMASNAK", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_16->PCIE_CFGERRPOISONEDN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRPOISONEDN", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTMSIENABLE->PCIE_LOGIC_OUTS_B17_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_1", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTMSIENABLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_11->PCIE_TRNTREM0": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTREM0", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_18->PCIE_TRNTD0": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD0", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_9->PCIE_CFGMGMTDI27": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI27", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_12->PCIE_TRNTERRFWD": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTERRFWD", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_2->PCIE_CFGREVID4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGREVID4", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_3->PCIE_TRNTD99": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD99", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA15->PCIE_LOGIC_OUTS_B6_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX19_R_0->PCIE_CFGPORTNUMBER3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPORTNUMBER3", - "is_directional": "1", - "src_wire": "PCIE_IMUX19_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD123->PCIE_LOGIC_OUTS_B10_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRD123", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_10->PCIE_CFGDSN18": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN18", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPH7->PCIE_LOGIC_OUTS_B8_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_3", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPH7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_11->PCIE_CFGERRAERHEADERLOG120": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG120", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_5->PCIE_CFGERRAERHEADERLOG52": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG52", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_6->PCIE_CFGDSN2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN2", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA3->PCIE_LOGIC_OUTS_B15_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_14", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_10->PCIE_TRNTD76": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD76", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LNKCLKEN->PCIE_LOGIC_OUTS_B10_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_10", - "is_directional": "1", - "src_wire": "PCIE_LNKCLKEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_2->PCIE_CFGMGMTDI1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI1", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_3->PCIE_CFGERRAERHEADERLOG58": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG58", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA54->PCIE_LOGIC_OUTS_B5_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA54", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_16->PCIE_TRNTDLLPDATA5": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_1->PCIE_MIMTXRDATA6": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_4->PCIE_PIPERX3DATA10": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA18->PCIE_LOGIC_OUTS_B2_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA26->PCIE_LOGIC_OUTS_B5_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA26", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_6->PCIE_CFGERRAERHEADERLOG49": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG49", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0->PCIE_LOGIC_OUTS_B21_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_17", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_19->PCIE_CFGERRTLPCPLHEADER24": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER24", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA9->PCIE_LOGIC_OUTS_B21_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_8", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_9->PCIE_CFGMGMTDI28": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI28", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD58->PCIE_LOGIC_OUTS_B3_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRD58", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA10->PCIE_LOGIC_OUTS_B11_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_5", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB6->PCIE_LOGIC_OUTS_B22_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_13", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR0->PCIE_LOGIC_OUTS_B6_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_12", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA11->PCIE_LOGIC_OUTS_B15_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_5", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA4->PCIE_LOGIC_OUTS_B0_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_5->PCIE_PIPERX7CHANISALIGNED": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7CHANISALIGNED", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_1->PCIE_CFGDSDEVICENUMBER4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSDEVICENUMBER4", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETO->PCIE_LOGIC_OUTS_B17_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_18", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDPMETO", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA48->PCIE_LOGIC_OUTS_B16_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA48", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA29->PCIE_LOGIC_OUTS_B5_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA29", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_15->PCIE_TRNTD56": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD56", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_19->PCIE_TRNTD6": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD6", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA37->PCIE_LOGIC_OUTS_B9_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_0", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA37", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA14->PCIE_LOGIC_OUTS_B2_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA49->PCIE_LOGIC_OUTS_B13_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA49", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_11->PCIE_CFGERRAERHEADERLOG28": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG28", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSDLLACTIVE->PCIE_LOGIC_OUTS_B12_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSDLLACTIVE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA63->PCIE_LOGIC_OUTS_B10_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_3", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA63", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD8->PCIE_LOGIC_OUTS_B2_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_7", - "is_directional": "1", - "src_wire": "PCIE_TRNRD8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_17->PCIE_CFGERRINTERNALUNCORN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRINTERNALUNCORN", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA40->PCIE_LOGIC_OUTS_B21_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_14", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA40", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_1->PCIE_TRNTD85": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD85", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_11->PCIE_CFGDSN22": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN22", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_0->PCIE_MIMTXRDATA3": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA41->PCIE_LOGIC_OUTS_B18_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_3", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA41", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRI->PCIE_LOGIC_OUTS_B23_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_12", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRI", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_2->PCIE_CFGERRAERHEADERLOG63": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG63", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA3->PCIE_LOGIC_OUTS_B15_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_3->PCIE_CFGMGMTDI6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI6", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR0->PCIE_LOGIC_OUTS_B20_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA46->PCIE_LOGIC_OUTS_B23_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA46", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA57->PCIE_LOGIC_OUTS_B21_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_10", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA57", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_15->PCIE_TRNTDLLPDATA2": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSCURRENTSPEED0->PCIE_LOGIC_OUTS_B19_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSCURRENTSPEED0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_12->PCIE_CFGERRAERHEADERLOG25": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG25", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2POWERDOWN0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA15->PCIE_LOGIC_OUTS_B11_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD17->PCIE_LOGIC_OUTS_B2_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_9", - "is_directional": "1", - "src_wire": "PCIE_TRNRD17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA64->PCIE_LOGIC_OUTS_B16_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_1", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA64", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_3->PCIE_MIMTXRDATA15": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX21_R_11->PCIE_PLDBGMODE0": { - "can_invert": "0", - "dst_wire": "PCIE_PLDBGMODE0", - "is_directional": "1", - "src_wire": "PCIE_IMUX21_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD30->PCIE_LOGIC_OUTS_B3_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRD30", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA36->PCIE_LOGIC_OUTS_B17_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_15", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA36", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_10->PCIE_CFGSUBSYSVENDID3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID3", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_10->PCIE_CFGMGMTBYTEENN1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTBYTEENN1", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_2->PCIE_MIMTXRDATA11": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR10->PCIE_LOGIC_OUTS_B23_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_8", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_0->PCIE_CFGERRAERHEADERLOG72": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG72", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA14->PCIE_LOGIC_OUTS_B2_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA43->PCIE_LOGIC_OUTS_B19_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_18", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA43", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA35->PCIE_LOGIC_OUTS_B17_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_9", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA35", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_R_16->PCIE_PIPERX6VALID": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6VALID", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB20->PCIE_LOGIC_OUTS_B16_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_5", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB20", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_7->PCIE_MIMTXRDATA28": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA28", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC10->PCIE_LOGIC_OUTS_B21_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_9", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA12->PCIE_LOGIC_OUTS_B8_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPH7->PCIE_LOGIC_OUTS_B4_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_3", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPH7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_17->PCIE_TRNTDLLPDATA10": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR16->PCIE_LOGIC_OUTS_B9_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_8", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTBUFAV2->PCIE_LOGIC_OUTS_B1_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_4", - "is_directional": "1", - "src_wire": "PCIE_TRNTBUFAV2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_6->PCIE_PIPERX3DATA2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_7->PCIE_TRNTD115": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD115", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLINITIALLINKWIDTH0->PCIE_LOGIC_OUTS_B8_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_2", - "is_directional": "1", - "src_wire": "PCIE_PLINITIALLINKWIDTH0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_13->PCIE_TRNTD62": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD62", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_11" }, "PCIE_BOT.PCIE_IMUX14_R_7->PCIE_CFGERRAERHEADERLOG42": { "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG42", - "is_directional": "1", "src_wire": "PCIE_IMUX14_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTERRDROP->PCIE_LOGIC_OUTS_B2_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3", "is_directional": "1", - "src_wire": "PCIE_TRNTERRDROP", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG42" }, - "PCIE_BOT.PCIE_IMUX1_R_17->PCIE_MIMRXRDATA9": { + "PCIE_BOT.PCIE_MIMTXRADDR7->PCIE_LOGIC_OUTS_B17_R_4": { "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA9", + "src_wire": "PCIE_MIMTXRADDR7", "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_17", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_4" }, - "PCIE_BOT.PCIE_IMUX13_L_13->PCIE_CFGSUBSYSVENDID13": { + "PCIE_BOT.PCIE_IMUX38_L_19->PCIE_PIPERX0STATUS1": { "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID13", + "src_wire": "PCIE_IMUX38_L_19", "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0STATUS1" }, - "PCIE_BOT.PCIE_TRNFCNPD9->PCIE_LOGIC_OUTS_B11_L_6": { + "PCIE_BOT.PCIE_IMUX1_L_10->PCIE_TRNTD125": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_6", + "src_wire": "PCIE_IMUX1_L_10", "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD125" }, - "PCIE_BOT.PCIE_IMUX3_R_5->PCIE_MIMTXRDATA23": { + "PCIE_BOT.PCIE_IMUX8_R_2->PCIE_TRNTD79": { "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA23", + "src_wire": "PCIE_IMUX8_R_2", "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD79" }, - "PCIE_BOT.PCIE_IMUX15_L_14->PCIE_CFGAERINTERRUPTMSGNUM3": { + "PCIE_BOT.PCIE_IMUX3_L_2->PCIE_TRNTD95": { "can_invert": "0", - "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM3", + "src_wire": "PCIE_IMUX3_L_2", "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD95" }, - "PCIE_BOT.PCIE_IMUX16_R_17->PCIE_PIPERX6CHARISK0": { + "PCIE_BOT.PCIE_IMUX3_L_4->PCIE_TRNTD103": { "can_invert": "0", - "dst_wire": "PCIE_PIPERX6CHARISK0", + "src_wire": "PCIE_IMUX3_L_4", "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_17", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD103" }, - "PCIE_BOT.PCIE_CFGDEVCONTROLCORRERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_12": { + "PCIE_BOT.PCIE_IMUX7_L_13->PCIE_CFGERRTLPCPLHEADER1": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_12", + "src_wire": "PCIE_IMUX7_L_13", "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_19->PCIE_TRNTD5": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD5", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA12->PCIE_LOGIC_OUTS_B0_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_7->PCIE_MIMTXRDATA29": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA29", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO13->PCIE_LOGIC_OUTS_B14_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_14", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_4->PCIE_CFGERRAERHEADERLOG57": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG57", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA1->PCIE_LOGIC_OUTS_B13_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA13->PCIE_LOGIC_OUTS_B4_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_17->PCIE_TRNTD49": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD49", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1->PCIE_LOGIC_OUTS_B18_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_18", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_13->PCIE_TRNRNPREQ": { - "can_invert": "0", - "dst_wire": "PCIE_TRNRNPREQ", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA37->PCIE_LOGIC_OUTS_B9_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_15", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA37", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX19_R_11->PCIE_CFGVENDID12": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID12", - "is_directional": "1", - "src_wire": "PCIE_IMUX19_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRBARHIT4->PCIE_LOGIC_OUTS_B1_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_8", - "is_directional": "1", - "src_wire": "PCIE_TRNRBARHIT4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA21->PCIE_LOGIC_OUTS_B12_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA21", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_L_8->PCIE_PIPERX1DATA9": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA9", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO31->PCIE_LOGIC_OUTS_B18_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_14", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO31", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA10->PCIE_LOGIC_OUTS_B11_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_12", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPH6->PCIE_LOGIC_OUTS_B0_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_3", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPH6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_10->PCIE_TRNTD126": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD126", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_8->PCIE_PIPERX5STATUS1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5STATUS1", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_15->PCIE_PIPERX2ELECIDLE": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2ELECIDLE", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_2->PCIE_TRNTD81": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD81", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRBARHIT2->PCIE_LOGIC_OUTS_B2_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_9", - "is_directional": "1", - "src_wire": "PCIE_TRNRBARHIT2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_18->PCIE_DRPADDR6": { - "can_invert": "0", - "dst_wire": "PCIE_DRPADDR6", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB47->PCIE_LOGIC_OUTS_B18_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_3", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB47", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTBUFAV3->PCIE_LOGIC_OUTS_B3_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4", - "is_directional": "1", - "src_wire": "PCIE_TRNTBUFAV3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_9->PCIE_PIPERX1DATA4": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA4->PCIE_LOGIC_OUTS_B5_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA1->PCIE_LOGIC_OUTS_B13_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_14", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGAERROOTERRCORRERRREPORTINGEN->PCIE_LOGIC_OUTS_B19_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_13->PCIE_CFGMGMTDWADDR8": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR8", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLDIRECTEDCHANGEDONE->PCIE_LOGIC_OUTS_B0_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_3", - "is_directional": "1", - "src_wire": "PCIE_PLDIRECTEDCHANGEDONE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_4->PCIE_PIPERX3STATUS0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3STATUS0", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_6->PCIE_PIPERX7DATA2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA4->PCIE_LOGIC_OUTS_B0_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_19->PCIE_TRNTDLLPDATA16": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA16", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB53->PCIE_LOGIC_OUTS_B20_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_4", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB53", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_6->PCIE_PIPERX7CHARISK0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7CHARISK0", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_8->PCIE_PIPERX5DATA8": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA8", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGERRCPLRDYN->PCIE_LOGIC_OUTS_B14_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_10", - "is_directional": "1", - "src_wire": "PCIE_CFGERRCPLRDYN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTD->PCIE_LOGIC_OUTS_B19_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_17", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTD", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_L_4->PCIE_PIPERX3DATA9": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA9", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA19->PCIE_LOGIC_OUTS_B7_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_16", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_19->PCIE_PIPERX4STATUS0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4STATUS0", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD0->PCIE_LOGIC_OUTS_B1_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_5", - "is_directional": "1", - "src_wire": "PCIE_TRNRD0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTDO4->PCIE_LOGIC_OUTS_B15_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_8", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTDO4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_15->PCIE_CFGERRTLPCPLHEADER7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER7", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_15", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER1" }, "PCIE_BOT.PCIE_TRNFCNPH6->PCIE_LOGIC_OUTS_B7_L_3": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_3", - "is_directional": "1", "src_wire": "PCIE_TRNFCNPH6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD11->PCIE_LOGIC_OUTS_B10_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_11", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_17->PCIE_MIMRXRDATA64": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA64", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_10->PCIE_PIPERX5DATA2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR4->PCIE_LOGIC_OUTS_B10_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_14->PCIE_PIPERX2DATA12": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA12", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_7->PCIE_PIPERX1DATA14": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGERRAERHEADERLOGSETN->PCIE_LOGIC_OUTS_B17_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_12", - "is_directional": "1", - "src_wire": "PCIE_CFGERRAERHEADERLOGSETN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR23->PCIE_LOGIC_OUTS_B15_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_2", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR23", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA44->PCIE_LOGIC_OUTS_B20_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_13", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA44", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR36->PCIE_LOGIC_OUTS_B14_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_5", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR36", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD9->PCIE_LOGIC_OUTS_B8_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_11", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_L_6->PCIE_TRNTD111": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD111", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD31->PCIE_LOGIC_OUTS_B5_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRD31", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_18->PCIE_CFGERRPOSTEDN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRPOSTEDN", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_18->PCIE_TRNTD44": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD44", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_R_7->PCIE_CFGMGMTDI22": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI22", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSLINKTRAINING->PCIE_LOGIC_OUTS_B21_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_18", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSLINKTRAINING", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA27->PCIE_LOGIC_OUTS_B13_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_9", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA27", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR6->PCIE_LOGIC_OUTS_B11_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_2", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR24->PCIE_LOGIC_OUTS_B17_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_2", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR24", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR2->PCIE_LOGIC_OUTS_B8_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_11", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_18->PCIE_PIPERX4DATA14": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4DATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_18->PCIE_PIPERX4DATA13": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4DATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_2->PCIE_CFGERRAERHEADERLOG85": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG85", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD55->PCIE_LOGIC_OUTS_B0_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRD55", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_18->PCIE_MIMRXRDATA15": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_8->PCIE_TRNTD117": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD117", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMPME->PCIE_LOGIC_OUTS_B14_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_18", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDPMPME", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_10->PCIE_PIPERX5CHARISK0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5CHARISK0", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB42->PCIE_LOGIC_OUTS_B21_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_1", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB42", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD4->PCIE_LOGIC_OUTS_B2_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_1", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_3->PCIE_PIPERX3DATA13": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGAERECRCGENEN->PCIE_LOGIC_OUTS_B18_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGAERECRCGENEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA43->PCIE_LOGIC_OUTS_B19_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_3", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA43", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLD7->PCIE_LOGIC_OUTS_B6_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_10", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLD7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA64->PCIE_LOGIC_OUTS_B10_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA64", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD41->PCIE_LOGIC_OUTS_B5_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRD41", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_3->PCIE_TRNTD96": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD96", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5CHARISK0->PCIE_LOGIC_OUTS_B16_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5CHARISK0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_19->PCIE_CFGERRTLPCPLHEADER25": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER25", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTMSIXFM->PCIE_LOGIC_OUTS_B16_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_5", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTMSIXFM", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_12->PCIE_CFGSUBSYSVENDID9": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID9", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSBANDWIDTHSTATUS->PCIE_LOGIC_OUTS_B13_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_R_14->PCIE_CFGINTERRUPTDI2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGINTERRUPTDI2", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR2->PCIE_LOGIC_OUTS_B22_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_7", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA13->PCIE_LOGIC_OUTS_B4_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_4", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_L_18->PCIE_PIPERX0DATA15": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0DATA15", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR4->PCIE_LOGIC_OUTS_B14_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_11->PCIE_CFGDSN24": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN24", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLINITIALLINKWIDTH2->PCIE_LOGIC_OUTS_B10_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_2", - "is_directional": "1", - "src_wire": "PCIE_PLINITIALLINKWIDTH2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA5->PCIE_LOGIC_OUTS_B4_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPD6->PCIE_LOGIC_OUTS_B5_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_5", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_0->PCIE_PLUPSTREAMPREFERDEEMPH": { - "can_invert": "0", - "dst_wire": "PCIE_PLUPSTREAMPREFERDEEMPH", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_11->PCIE_CFGSUBSYSVENDID4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID4", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_8->PCIE_CFGERRAERHEADERLOG107": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG107", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA9->PCIE_LOGIC_OUTS_B13_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_5", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_18->PCIE_CFGERRTLPCPLHEADER18": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER18", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA8->PCIE_LOGIC_OUTS_B9_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_12", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_3->PCIE_CFGMGMTDI3": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI3", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_9->PCIE_MIMTXRDATA36": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA36", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_7->PCIE_MIMTXRDATA68": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA68", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRA->PCIE_LOGIC_OUTS_B19_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_10", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRA", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_R_15->PCIE_PIPERX6DATA11": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_16->PCIE_PIPERX2CHANISALIGNED": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2CHANISALIGNED", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPERX6POLARITY->PCIE_LOGIC_OUTS_B1_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_14", - "is_directional": "1", - "src_wire": "PCIE_PIPERX6POLARITY", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_1->PCIE_MIMTXRDATA7": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_4->PCIE_CFGERRAERHEADERLOG54": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG54", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CTRL1_R_1->PCIE_FUNCLVLRSTN": { - "can_invert": "0", - "dst_wire": "PCIE_FUNCLVLRSTN", - "is_directional": "1", - "src_wire": "PCIE_CTRL1_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_L_19->PCIE_PIPERX0DATA9": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0DATA9", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTRDYN->PCIE_LOGIC_OUTS_B15_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_10", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTRDYN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_8->PCIE_MIMTXRDATA33": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA33", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA29->PCIE_LOGIC_OUTS_B20_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_17", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA29", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_L_17->PCIE_DRPWE": { - "can_invert": "0", - "dst_wire": "PCIE_DRPWE", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA36->PCIE_LOGIC_OUTS_B11_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_0", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA36", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA16->PCIE_LOGIC_OUTS_B0_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVSTATUSURDETECTED->PCIE_LOGIC_OUTS_B17_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_10", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVSTATUSURDETECTED", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPH3->PCIE_LOGIC_OUTS_B3_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_5", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPH3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3CHARISK1->PCIE_LOGIC_OUTS_B16_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3CHARISK1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLURERRREPORTINGEN->PCIE_LOGIC_OUTS_B21_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_13", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLURERRREPORTINGEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_0->PCIE_MIMTXRDATA1": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1POWERDOWN0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA42->PCIE_LOGIC_OUTS_B18_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_13", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA42", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA26->PCIE_LOGIC_OUTS_B8_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_18", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA26", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4CHARISK1->PCIE_LOGIC_OUTS_B16_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4CHARISK1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT->PCIE_LOGIC_OUTS_B8_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA10->PCIE_LOGIC_OUTS_B12_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_14", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB43->PCIE_LOGIC_OUTS_B18_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_2", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB43", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_19->PCIE_TRNTDLLPDATA17": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA17", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR50->PCIE_LOGIC_OUTS_B11_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_9", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR50", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA38->PCIE_LOGIC_OUTS_B12_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_15", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA38", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_15->PCIE_PIPERX6DATA10": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA10", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_5->PCIE_TRNTD104": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD104", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_17->PCIE_MIMRXRDATA8": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA8", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_7->PCIE_CFGMGMTDI19": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI19", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_4->PCIE_CFGTRNPENDINGN": { - "can_invert": "0", - "dst_wire": "PCIE_CFGTRNPENDINGN", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_0->PCIE_TRNTD87": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD87", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_6->PCIE_CFGMGMTDI15": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI15", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_17->PCIE_MIMRXRDATA11": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6POWERDOWN1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_16->PCIE_PIPERX6CHANISALIGNED": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6CHANISALIGNED", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_R_7->PCIE_MIMTXRDATA43": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA43", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA32->PCIE_LOGIC_OUTS_B2_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_16", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA32", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_8->PCIE_PIPERX5CHARISK1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5CHARISK1", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD25->PCIE_LOGIC_OUTS_B5_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_11", - "is_directional": "1", - "src_wire": "PCIE_TRNRD25", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA4->PCIE_LOGIC_OUTS_B0_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLTSSMSTATE2->PCIE_LOGIC_OUTS_B9_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLLTSSMSTATE2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX18_R_1->PCIE_CFGDSFUNCTIONNUMBER1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSFUNCTIONNUMBER1", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD122->PCIE_LOGIC_OUTS_B9_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRD122", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPH0->PCIE_LOGIC_OUTS_B2_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_7", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPH0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGLINKSTATUSCURRENTSPEED1->PCIE_LOGIC_OUTS_B20_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_17", - "is_directional": "1", - "src_wire": "PCIE_CFGLINKSTATUSCURRENTSPEED1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3POWERDOWN0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_9->PCIE_TRNTD122": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD122", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDUNLOCK->PCIE_LOGIC_OUTS_B9_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_19", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDUNLOCK", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_7->PCIE_CFGDSN6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN6", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_L_5->PCIE_PIPERX3CHANISALIGNED": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3CHANISALIGNED", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_11->PCIE_TRNTREM1": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTREM1", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB55->PCIE_LOGIC_OUTS_B18_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_5", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB55", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_19->PCIE_PIPERX0STATUS0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0STATUS0", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD115->PCIE_LOGIC_OUTS_B8_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRD115", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2DATA1->PCIE_LOGIC_OUTS_B13_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_14", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETXDEEMPH->PCIE_LOGIC_OUTS_B0_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_8", - "is_directional": "1", - "src_wire": "PCIE_PIPETXDEEMPH", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_13->PCIE_CFGDSN31": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN31", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWADDR3->PCIE_LOGIC_OUTS_B23_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWADDR3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_17->PCIE_PIPERX6DATA0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_4->PCIE_CFGERRAERHEADERLOG91": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG91", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_1->PCIE_TRNTD86": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD86", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_11->PCIE_CFGMGMTDWADDR2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDWADDR2", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_17->PCIE_TRNTD48": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD48", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_5->PCIE_CFGERRAERHEADERLOG94": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG94", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA34->PCIE_LOGIC_OUTS_B10_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_15", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA34", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA9->PCIE_LOGIC_OUTS_B13_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_12", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTB->PCIE_LOGIC_OUTS_B15_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_17", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTB", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2LINKSTATUS3->PCIE_LOGIC_OUTS_B4_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_16", - "is_directional": "1", - "src_wire": "PCIE_LL2LINKSTATUS3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_L_16->PCIE_CFGERRTLPCPLHEADER11": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER11", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_L_4->PCIE_TRNTD100": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD100", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2LINKSTATUS4->PCIE_LOGIC_OUTS_B20_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_16", - "is_directional": "1", - "src_wire": "PCIE_LL2LINKSTATUS4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA61->PCIE_LOGIC_OUTS_B6_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_3", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA61", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_5->PCIE_MIMTXRDATA22": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA22", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD101->PCIE_LOGIC_OUTS_B4_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_19", - "is_directional": "1", - "src_wire": "PCIE_TRNRD101", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_4->PCIE_CFGERRAERHEADERLOG93": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG93", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DRPDO9->PCIE_LOGIC_OUTS_B22_L_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_19", - "is_directional": "1", - "src_wire": "PCIE_DRPDO9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_L_0->PCIE_PLDIRECTEDLTSSMNEW0": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW0", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_11->PCIE_CFGSUBSYSVENDID6": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID6", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB32->PCIE_LOGIC_OUTS_B15_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_2", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB32", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_16->PCIE_MIMRXRDATA7": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPH2->PCIE_LOGIC_OUTS_B2_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_5", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPH2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_10->PCIE_CFGERRAERHEADERLOG30": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG30", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWADDR4->PCIE_LOGIC_OUTS_B16_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWADDR4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_9->PCIE_PIPERX5DATA7": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLTSSMSTATE4->PCIE_LOGIC_OUTS_B11_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLLTSSMSTATE4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_R_10->PCIE_CFGMGMTBYTEENN2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTBYTEENN2", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD4->PCIE_LOGIC_OUTS_B8_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_6", - "is_directional": "1", - "src_wire": "PCIE_TRNRD4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_18->PCIE_TRNTD2": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD2", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_12->PCIE_CFGSUBSYSVENDID10": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID10", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_R_15->PCIE_TRNTD54": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD54", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_1->PCIE_CFGERRAERHEADERLOG80": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG80", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2LINKSTATUS1->PCIE_LOGIC_OUTS_B19_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_17", - "is_directional": "1", - "src_wire": "PCIE_LL2LINKSTATUS1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA52->PCIE_LOGIC_OUTS_B18_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_15", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA52", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA61->PCIE_LOGIC_OUTS_B21_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_9", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA61", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_19->PCIE_PIPERX4STATUS1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX4STATUS1", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCCPLH0->PCIE_LOGIC_OUTS_B14_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_6", - "is_directional": "1", - "src_wire": "PCIE_TRNFCCPLH0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWADDR8->PCIE_LOGIC_OUTS_B8_R_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_16", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWADDR8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_L_14->PCIE_TRNFCSEL0": { - "can_invert": "0", - "dst_wire": "PCIE_TRNFCSEL0", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_11->PCIE_TRNTD72": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD72", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLDBGVEC10->PCIE_LOGIC_OUTS_B21_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_5", - "is_directional": "1", - "src_wire": "PCIE_PLDBGVEC10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_9->PCIE_CFGDSN16": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN16", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD1->PCIE_LOGIC_OUTS_B8_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_2", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_7->PCIE_MIMTXRDATA30": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA30", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_12->PCIE_CFGERRAERHEADERLOG122": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG122", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_7->PCIE_MIMTXRDATA41": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA41", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPD3->PCIE_LOGIC_OUTS_B10_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_4", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB37->PCIE_LOGIC_OUTS_B21_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_0", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB37", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_5->PCIE_CFGMGMTDI14": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI14", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA24->PCIE_LOGIC_OUTS_B23_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_19", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA24", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_0->PCIE_CFGPORTNUMBER1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPORTNUMBER1", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_11->PCIE_CFGERRAERHEADERLOG29": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG29", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLTXPMSTATE1->PCIE_LOGIC_OUTS_B18_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLTXPMSTATE1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_14->PCIE_PIPERX6DATA13": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_13", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA4->PCIE_LOGIC_OUTS_B0_L_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX20_R_13->PCIE_CFGVENDID5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID5", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRRXOVERFLOW->PCIE_LOGIC_OUTS_B18_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_13", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRRXOVERFLOW", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD24->PCIE_LOGIC_OUTS_B3_L_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_11", - "is_directional": "1", - "src_wire": "PCIE_TRNRD24", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA14->PCIE_LOGIC_OUTS_B2_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_4", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECC5->PCIE_LOGIC_OUTS_B20_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_8", - "is_directional": "1", - "src_wire": "PCIE_DBGVECC5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX3_R_7->PCIE_MIMTXRDATA31": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA31", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_13->PCIE_CFGINTERRUPTDI7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGINTERRUPTDI7", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA55->PCIE_LOGIC_OUTS_B20_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_2", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA55", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_R_16->PCIE_PIPERX6PHYSTATUS": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6PHYSTATUS", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_14->PCIE_CFGERRAERHEADERLOG16": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG16", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA37->PCIE_LOGIC_OUTS_B20_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_15", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA37", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB16->PCIE_LOGIC_OUTS_B9_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_6", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA58->PCIE_LOGIC_OUTS_B17_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_0", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA58", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX1DATA15->PCIE_LOGIC_OUTS_B6_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_4", - "is_directional": "1", - "src_wire": "PCIE_PIPETX1DATA15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_12->PCIE_TRNTD67": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD67", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLSELLNKWIDTH0->PCIE_LOGIC_OUTS_B3_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLSELLNKWIDTH0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRFATAL->PCIE_LOGIC_OUTS_B8_L_16": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_16", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDERRFATAL", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_4->PCIE_CFGPCIECAPINTERRUPTMSGNUM4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB14->PCIE_LOGIC_OUTS_B17_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_7", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_5->PCIE_CFGFORCEMPS2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGFORCEMPS2", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD113->PCIE_LOGIC_OUTS_B5_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRD113", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_L_17->PCIE_PIPERX2DATA0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_L_16->PCIE_CFGDSN43": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN43", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA11->PCIE_LOGIC_OUTS_B15_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_1", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_8->PCIE_PIPERX5ELECIDLE": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5ELECIDLE", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_L_4->PCIE_TRNTD101": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD101", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB23->PCIE_LOGIC_OUTS_B8_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_4", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB23", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD3->PCIE_LOGIC_OUTS_B1_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_1", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0POWERDOWN0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA51->PCIE_LOGIC_OUTS_B14_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA51", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_2->PCIE_TRNTD80": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD80", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_18->PCIE_MIMRXRDATA13": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6POWERDOWN0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_2->PCIE_CFGPMFORCESTATE1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPMFORCESTATE1", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX36_L_6->PCIE_PIPERX3DATA1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3DATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_R_5->PCIE_PIPERX7DATA5": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_15->PCIE_MIMRXRDATA1": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_LL2TXIDLE->PCIE_LOGIC_OUTS_B13_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_17", - "is_directional": "1", - "src_wire": "PCIE_LL2TXIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNLNKUP->PCIE_LOGIC_OUTS_B0_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_7", - "is_directional": "1", - "src_wire": "PCIE_TRNLNKUP", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_L_0->PCIE_CFGPORTNUMBER4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPORTNUMBER4", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX3DATA6->PCIE_LOGIC_OUTS_B2_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_2", - "is_directional": "1", - "src_wire": "PCIE_PIPETX3DATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD54->PCIE_LOGIC_OUTS_B5_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_18", - "is_directional": "1", - "src_wire": "PCIE_TRNRD54", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD10->PCIE_LOGIC_OUTS_B5_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_1", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD10", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ASPMSUSPENDREQ->PCIE_LOGIC_OUTS_B6_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_14", - "is_directional": "1", - "src_wire": "PCIE_TL2ASPMSUSPENDREQ", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA39->PCIE_LOGIC_OUTS_B20_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_14", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA39", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_17->PCIE_MIMRXRDATA66": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA66", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXRADDR6->PCIE_LOGIC_OUTS_B9_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXRADDR6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA45->PCIE_LOGIC_OUTS_B17_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_18", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA45", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_6->PCIE_CFGERRAERHEADERLOG98": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG98", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_4->PCIE_PIPERX7ELECIDLE": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7ELECIDLE", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA3->PCIE_LOGIC_OUTS_B15_R_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_7", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGSCLRJ->PCIE_LOGIC_OUTS_B22_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_13", - "is_directional": "1", - "src_wire": "PCIE_DBGSCLRJ", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX37_L_19->PCIE_PIPERX0DATA8": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0DATA8", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA14->PCIE_LOGIC_OUTS_B4_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_18", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA12->PCIE_LOGIC_OUTS_B0_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA27->PCIE_LOGIC_OUTS_B20_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_18", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA27", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PL2RECEIVERERR->PCIE_LOGIC_OUTS_B10_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_14", - "is_directional": "1", - "src_wire": "PCIE_PL2RECEIVERERR", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX12_R_0->PCIE_CFGERRAERHEADERLOG70": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG70", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA13->PCIE_LOGIC_OUTS_B4_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_13->PCIE_CFGERRAERHEADERLOG18": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG18", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD109->PCIE_LOGIC_OUTS_B10_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_17", - "is_directional": "1", - "src_wire": "PCIE_TRNRD109", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLANEREVERSALMODE1->PCIE_LOGIC_OUTS_B14_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLLANEREVERSALMODE1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_16->PCIE_PIPERX2DATA6": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_16", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA20->PCIE_LOGIC_OUTS_B0_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA20", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGINTERRUPTDO1->PCIE_LOGIC_OUTS_B12_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_8", - "is_directional": "1", - "src_wire": "PCIE_CFGINTERRUPTDO1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA7->PCIE_LOGIC_OUTS_B14_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_13", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA6->PCIE_LOGIC_OUTS_B2_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0ELECIDLE->PCIE_LOGIC_OUTS_B3_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0ELECIDLE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_L_8->PCIE_PIPERX1DATA11": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1DATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA12->PCIE_LOGIC_OUTS_B16_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_14", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA43->PCIE_LOGIC_OUTS_B19_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_13", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA43", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA3->PCIE_LOGIC_OUTS_B15_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_11->PCIE_CFGSUBSYSVENDID7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID7", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB52->PCIE_LOGIC_OUTS_B19_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_4", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB52", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_13->PCIE_CFGSUBSYSVENDID14": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID14", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_13", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CTRL0_R_2->PCIE_TLRSTN": { - "can_invert": "0", - "dst_wire": "PCIE_TLRSTN", - "is_directional": "1", - "src_wire": "PCIE_CTRL0_R_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7CHARISK1->PCIE_LOGIC_OUTS_B16_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_0", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7CHARISK1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXRADDR5->PCIE_LOGIC_OUTS_B19_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXRADDR5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPD7->PCIE_LOGIC_OUTS_B7_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_0", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPD7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB2->PCIE_LOGIC_OUTS_B22_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_9", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA14->PCIE_LOGIC_OUTS_B21_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_L_8->PCIE_PIPERX1CHARISK1": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX1CHARISK1", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR54->PCIE_LOGIC_OUTS_B11_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_10", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR54", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD117->PCIE_LOGIC_OUTS_B2_R_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRD117", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD2->PCIE_LOGIC_OUTS_B3_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_5", - "is_directional": "1", - "src_wire": "PCIE_TRNRD2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRBARHIT7->PCIE_LOGIC_OUTS_B6_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_8", - "is_directional": "1", - "src_wire": "PCIE_TRNRBARHIT7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_L_14->PCIE_PIPERX2DATA14": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD40->PCIE_LOGIC_OUTS_B3_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_15", - "is_directional": "1", - "src_wire": "PCIE_TRNRD40", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_18->PCIE_DRPADDR5": { - "can_invert": "0", - "dst_wire": "PCIE_DRPADDR5", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR60->PCIE_LOGIC_OUTS_B10_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_12", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR60", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX5DATA7->PCIE_LOGIC_OUTS_B6_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_6", - "is_directional": "1", - "src_wire": "PCIE_PIPETX5DATA7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_4->PCIE_CFGERRAERHEADERLOG55": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG55", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA6->PCIE_LOGIC_OUTS_B16_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_12", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA62->PCIE_LOGIC_OUTS_B5_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_1", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA62", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_13", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2POWERDOWN1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR17->PCIE_LOGIC_OUTS_B11_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_8", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA55->PCIE_LOGIC_OUTS_B19_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_10", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA55", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCPH4->PCIE_LOGIC_OUTS_B4_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_5", - "is_directional": "1", - "src_wire": "PCIE_TRNFCPH4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_9->PCIE_CFGDSN13": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN13", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLDBGVEC5->PCIE_LOGIC_OUTS_B22_L_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_17", - "is_directional": "1", - "src_wire": "PCIE_PLDBGVEC5", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB63->PCIE_LOGIC_OUTS_B18_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_7", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB63", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR47->PCIE_LOGIC_OUTS_B8_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_9", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR47", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_17->PCIE_CFGERRTLPCPLHEADER14": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER14", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXRADDR7->PCIE_LOGIC_OUTS_B15_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXRADDR7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPD0->PCIE_LOGIC_OUTS_B10_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_3", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA66->PCIE_LOGIC_OUTS_B18_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_2", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA66", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRBARHIT3->PCIE_LOGIC_OUTS_B3_R_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_9", "is_directional": "1", - "src_wire": "PCIE_TRNRBARHIT3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_3" }, - "PCIE_BOT.PCIE_PIPETX0DATA8->PCIE_LOGIC_OUTS_B9_L_16": { + "PCIE_BOT.PCIE_PIPETX6CHARISK0->PCIE_LOGIC_OUTS_B16_R_13": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_16", + "src_wire": "PCIE_PIPETX6CHARISK0", "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_13" }, - "PCIE_BOT.PCIE_DBGVECB49->PCIE_LOGIC_OUTS_B20_L_3": { + "PCIE_BOT.PCIE_CTRL0_R_0->PCIE_SYSRSTN": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_3", + "src_wire": "PCIE_CTRL0_R_0", "is_directional": "1", - "src_wire": "PCIE_DBGVECB49", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_SYSRSTN" }, - "PCIE_BOT.PCIE_TRNRD51->PCIE_LOGIC_OUTS_B0_L_18": { + "PCIE_BOT.PCIE_CFGINTERRUPTDO3->PCIE_LOGIC_OUTS_B14_L_8": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_18", + "src_wire": "PCIE_CFGINTERRUPTDO3", "is_directional": "1", - "src_wire": "PCIE_TRNRD51", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_8" }, - "PCIE_BOT.PCIE_DBGVECB4->PCIE_LOGIC_OUTS_B22_R_11": { + "PCIE_BOT.PCIE_PIPETX7DATA12->PCIE_LOGIC_OUTS_B0_R_0": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_11", + "src_wire": "PCIE_PIPETX7DATA12", "is_directional": "1", - "src_wire": "PCIE_DBGVECB4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_0" }, - "PCIE_BOT.PCIE_IMUX0_R_3->PCIE_MIMTXRDATA12": { + "PCIE_BOT.PCIE_TRNRD11->PCIE_LOGIC_OUTS_B0_L_8": { "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA12", + "src_wire": "PCIE_TRNRD11", "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_8" }, "PCIE_BOT.PCIE_IMUX8_R_8->PCIE_CFGMGMTDI26": { "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI26", - "is_directional": "1", "src_wire": "PCIE_IMUX8_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_9->PCIE_MIMTXRDATA67": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA67", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWEN->PCIE_LOGIC_OUTS_B12_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWEN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR35->PCIE_LOGIC_OUTS_B12_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_5", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR35", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR41->PCIE_LOGIC_OUTS_B16_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_7", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR41", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA45->PCIE_LOGIC_OUTS_B21_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_13", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA45", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_14->PCIE_TRNTD58": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD58", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA55->PCIE_LOGIC_OUTS_B12_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_18", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA55", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB1->PCIE_LOGIC_OUTS_B17_R_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_8", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA14->PCIE_LOGIC_OUTS_B2_R_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_15", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX14_L_3->PCIE_CFGSUBSYSID2": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSID2", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRNONFATAL->PCIE_LOGIC_OUTS_B15_L_15": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_15", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGRECEIVEDERRNONFATAL", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR43->PCIE_LOGIC_OUTS_B8_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_8", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR43", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA4->PCIE_LOGIC_OUTS_B0_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_0->PCIE_PLDIRECTEDLINKSPEED": { - "can_invert": "0", - "dst_wire": "PCIE_PLDIRECTEDLINKSPEED", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX8_L_6->PCIE_CFGDSN1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGDSN1", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_1->PCIE_MIMTXRDATA60": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA60", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD35->PCIE_LOGIC_OUTS_B0_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_14", - "is_directional": "1", - "src_wire": "PCIE_TRNRD35", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_L_18->PCIE_PIPERX0DATA12": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0DATA12", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_L_6->PCIE_PIPERX3CHARISK0": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX3CHARISK0", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECB41->PCIE_LOGIC_OUTS_B20_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_1", - "is_directional": "1", - "src_wire": "PCIE_DBGVECB41", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA42->PCIE_LOGIC_OUTS_B14_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_0", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA42", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX2_R_15->PCIE_MIMRXRDATA2": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_9->PCIE_PIPERX5DATA6": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR40->PCIE_LOGIC_OUTS_B14_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_7", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR40", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD18->PCIE_LOGIC_OUTS_B3_L_9": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_9", - "is_directional": "1", - "src_wire": "PCIE_TRNRD18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX17_R_14->PCIE_CFGVENDID1": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID1", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_DBGVECA53->PCIE_LOGIC_OUTS_B21_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_11", - "is_directional": "1", - "src_wire": "PCIE_DBGVECA53", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLPHYLNKUPN->PCIE_LOGIC_OUTS_B15_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLPHYLNKUPN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD2->PCIE_LOGIC_OUTS_B21_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_14", - "is_directional": "1", - "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_R_7->PCIE_CFGERRAERHEADERLOG43": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG43", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_R_6->PCIE_MIMTXRDATA46": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA46", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PLLTSSMSTATE0->PCIE_LOGIC_OUTS_B7_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_0", - "is_directional": "1", - "src_wire": "PCIE_PLLTSSMSTATE0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX18_R_12->PCIE_CFGVENDID7": { - "can_invert": "0", - "dst_wire": "PCIE_CFGVENDID7", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_R_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX34_R_15->PCIE_PIPERX6ELECIDLE": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6ELECIDLE", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_15", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4CHARISK0->PCIE_LOGIC_OUTS_B16_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4CHARISK0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRREM0->PCIE_LOGIC_OUTS_B1_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_11", - "is_directional": "1", - "src_wire": "PCIE_TRNRREM0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX13_L_2->PCIE_CFGREVID5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGREVID5", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_1->PCIE_CFGERRAERHEADERLOG78": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG78", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX7DATA0->PCIE_LOGIC_OUTS_B9_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_3", - "is_directional": "1", - "src_wire": "PCIE_PIPETX7DATA0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA41->PCIE_LOGIC_OUTS_B18_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_18", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA41", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTBUFAV4->PCIE_LOGIC_OUTS_B5_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_4", - "is_directional": "1", - "src_wire": "PCIE_TRNTBUFAV4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX6DATA14->PCIE_LOGIC_OUTS_B2_R_11": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_11", - "is_directional": "1", - "src_wire": "PCIE_PIPETX6DATA14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_R_3->PCIE_CFGMGMTDI5": { - "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI5", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMSGDATA1->PCIE_LOGIC_OUTS_B13_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_10", - "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA1", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_14->PCIE_CFGERRTLPCPLHEADER4": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER4", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR39->PCIE_LOGIC_OUTS_B12_L_7": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_7", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR39", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA57->PCIE_LOGIC_OUTS_B9_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_4", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA57", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX6_L_4->PCIE_CFGERRAERHEADERLOG92": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG92", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_4", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGCOMMANDSERREN->PCIE_LOGIC_OUTS_B16_L_8": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_8", - "is_directional": "1", - "src_wire": "PCIE_CFGCOMMANDSERREN", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNTDSTRDY0->PCIE_LOGIC_OUTS_B1_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_10", - "is_directional": "1", - "src_wire": "PCIE_TRNTDSTRDY0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX7_L_12->PCIE_CFGERRAERHEADERLOG125": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG125", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX32_R_8->PCIE_PIPERX5DATA11": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA11", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_R_8", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX35_R_3->PCIE_PIPERX7DATA14": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX7DATA14", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX10_R_14->PCIE_CFGERRAERHEADERLOG15": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG15", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_14", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWDATA63->PCIE_LOGIC_OUTS_B10_R_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_18", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWDATA63", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRD20->PCIE_LOGIC_OUTS_B1_L_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_10", - "is_directional": "1", - "src_wire": "PCIE_TRNRD20", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA22->PCIE_LOGIC_OUTS_B17_R_6": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_6", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA22", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMRXWADDR9->PCIE_LOGIC_OUTS_B17_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_19", - "is_directional": "1", - "src_wire": "PCIE_MIMRXWADDR9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX4DATA7->PCIE_LOGIC_OUTS_B6_R_17": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_17", - "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX4_L_7->PCIE_CFGERRAERHEADERLOG102": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG102", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX2COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_14": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_14", - "is_directional": "1", - "src_wire": "PCIE_PIPETX2COMPLIANCE", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNRDLLPDATA2->PCIE_LOGIC_OUTS_B6_L_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_12", - "is_directional": "1", - "src_wire": "PCIE_TRNRDLLPDATA2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PL2RXPMSTATE0->PCIE_LOGIC_OUTS_B13_R_19": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_19", - "is_directional": "1", - "src_wire": "PCIE_PL2RXPMSTATE0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPD2->PCIE_LOGIC_OUTS_B9_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_4", - "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX16_R_3->PCIE_CFGERRAERHEADERLOG61": { - "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG61", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX39_R_9->PCIE_PIPERX5DATA4": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_9", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO11->PCIE_LOGIC_OUTS_B17_R_13": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_13", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO11", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX9_R_17->PCIE_TRNTD47": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD47", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_17", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX11_L_2->PCIE_CFGPMSENDPMETON": { - "can_invert": "0", - "dst_wire": "PCIE_CFGPMSENDPMETON", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_2", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_PIPETX0DATA3->PCIE_LOGIC_OUTS_B15_L_18": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_18", - "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA3", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_MIMTXWDATA65->PCIE_LOGIC_OUTS_B10_R_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_5", - "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA65", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_CFGMGMTDO7->PCIE_LOGIC_OUTS_B10_R_12": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_12", - "is_directional": "1", - "src_wire": "PCIE_CFGMGMTDO7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_0->PCIE_MIMTXRDATA63": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA63", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TL2ERRHDR7->PCIE_LOGIC_OUTS_B7_R_10": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_10", - "is_directional": "1", - "src_wire": "PCIE_TL2ERRHDR7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX0_R_6->PCIE_MIMTXRDATA24": { - "can_invert": "0", - "dst_wire": "PCIE_MIMTXRDATA24", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_6", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_19->PCIE_MIMRXRDATA57": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA57", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_19", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX38_L_18->PCIE_PIPERX0DATA13": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX0DATA13", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX5_R_18->PCIE_MIMRXRDATA61": { - "can_invert": "0", - "dst_wire": "PCIE_MIMRXRDATA61", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_18", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_12->PCIE_CFGSUBSYSVENDID11": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID11", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_12", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX33_R_17->PCIE_PIPERX6DATA2": { - "can_invert": "0", - "dst_wire": "PCIE_PIPERX6DATA2", "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_17", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI26" }, - "PCIE_BOT.PCIE_PIPETXRESET->PCIE_LOGIC_OUTS_B9_R_11": { + "PCIE_BOT.PCIE_IMUX32_L_15->PCIE_PIPERX2DATA11": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_11", + "src_wire": "PCIE_IMUX32_L_15", "is_directional": "1", - "src_wire": "PCIE_PIPETXRESET", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA11" }, - "PCIE_BOT.PCIE_PIPETX2DATA4->PCIE_LOGIC_OUTS_B0_L_13": { + "PCIE_BOT.PCIE_DBGVECB9->PCIE_LOGIC_OUTS_B22_R_18": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_13", + "src_wire": "PCIE_DBGVECB9", "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_18" }, - "PCIE_BOT.PCIE_IMUX8_R_3->PCIE_TRNTD78": { + "PCIE_BOT.PCIE_DBGVECB28->PCIE_LOGIC_OUTS_B16_R_3": { "can_invert": "0", - "dst_wire": "PCIE_TRNTD78", + "src_wire": "PCIE_DBGVECB28", "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_3" }, - "PCIE_BOT.PCIE_PIPETX2DATA3->PCIE_LOGIC_OUTS_B15_L_14": { + "PCIE_BOT.PCIE_PIPETX5DATA3->PCIE_LOGIC_OUTS_B15_R_7": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_14", + "src_wire": "PCIE_PIPETX5DATA3", "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_7" }, - "PCIE_BOT.PCIE_PIPETX0DATA7->PCIE_LOGIC_OUTS_B6_L_17": { + "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTC->PCIE_LOGIC_OUTS_B18_L_17": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_17", + "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTC", "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_17" }, - "PCIE_BOT.PCIE_IMUX39_R_7->PCIE_PIPERX5DATA12": { + "PCIE_BOT.PCIE_IMUX14_L_1->PCIE_CFGREVID2": { "can_invert": "0", - "dst_wire": "PCIE_PIPERX5DATA12", + "src_wire": "PCIE_IMUX14_L_1", "is_directional": "1", - "src_wire": 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"src_wire": "PCIE_PLDBGVEC0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG34" }, - "PCIE_BOT.PCIE_TRNRD36->PCIE_LOGIC_OUTS_B2_L_14": { + "PCIE_BOT.PCIE_IMUX7_R_18->PCIE_MIMRXRDATA63": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_14", + "src_wire": "PCIE_IMUX7_R_18", "is_directional": "1", - "src_wire": "PCIE_TRNRD36", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA63" }, - "PCIE_BOT.PCIE_MIMTXWDATA47->PCIE_LOGIC_OUTS_B18_R_4": { + "PCIE_BOT.PCIE_MIMRXWDATA45->PCIE_LOGIC_OUTS_B17_R_18": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_4", + "src_wire": "PCIE_MIMRXWDATA45", "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA47", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_18" }, - "PCIE_BOT.PCIE_MIMTXWDATA29->PCIE_LOGIC_OUTS_B2_R_10": { + "PCIE_BOT.PCIE_IMUX33_R_15->PCIE_PIPERX6DATA10": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_10", + "src_wire": "PCIE_IMUX33_R_15", "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA29", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA10" }, - "PCIE_BOT.PCIE_IMUX6_L_16->PCIE_CFGERRTLPCPLHEADER12": { + "PCIE_BOT.PCIE_IMUX18_R_13->PCIE_CFGVENDID3": { "can_invert": "0", - "dst_wire": "PCIE_CFGERRTLPCPLHEADER12", + "src_wire": "PCIE_IMUX18_R_13", "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_16", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID3" }, - "PCIE_BOT.PCIE_IMUX13_L_11->PCIE_CFGSUBSYSVENDID5": { + "PCIE_BOT.PCIE_IMUX11_L_7->PCIE_CFGDSN8": { "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID5", + "src_wire": "PCIE_IMUX11_L_7", "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN8" }, - "PCIE_BOT.PCIE_MIMTXWDATA53->PCIE_LOGIC_OUTS_B19_R_2": { + "PCIE_BOT.PCIE_DBGVECC2->PCIE_LOGIC_OUTS_B21_L_7": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_2", + "src_wire": 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"dst_wire": "PCIE_LOGIC_OUTS_B17_L_11", + "src_wire": "PCIE_PIPETX3DATA2", "is_directional": "1", - "src_wire": "PCIE_CFGMSGDATA4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_3" }, "PCIE_BOT.PCIE_IMUX15_R_0->PCIE_CFGERRAERHEADERLOG73": { "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG73", - "is_directional": "1", "src_wire": "PCIE_IMUX15_R_0", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX1_R_14->PCIE_TRNTD59": { - "can_invert": "0", - "dst_wire": "PCIE_TRNTD59", "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG73" }, - "PCIE_BOT.PCIE_IMUX13_R_14->PCIE_CFGINTERRUPTDI1": { + "PCIE_BOT.PCIE_PIPETX7DATA1->PCIE_LOGIC_OUTS_B13_R_3": { "can_invert": "0", - "dst_wire": "PCIE_CFGINTERRUPTDI1", + "src_wire": "PCIE_PIPETX7DATA1", "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_3" }, - "PCIE_BOT.PCIE_MIMTXWDATA48->PCIE_LOGIC_OUTS_B14_R_1": { + "PCIE_BOT.PCIE_DBGVECA46->PCIE_LOGIC_OUTS_B18_R_12": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_1", + "src_wire": "PCIE_DBGVECA46", "is_directional": "1", - "src_wire": "PCIE_MIMTXWDATA48", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_12" }, - "PCIE_BOT.PCIE_PIPETX4DATA10->PCIE_LOGIC_OUTS_B11_R_16": { + "PCIE_BOT.PCIE_TRNRD36->PCIE_LOGIC_OUTS_B2_L_14": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_16", + "src_wire": "PCIE_TRNRD36", "is_directional": "1", - "src_wire": "PCIE_PIPETX4DATA10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_14" }, - "PCIE_BOT.PCIE_IMUX2_L_18->PCIE_TRNTDLLPDATA13": { + "PCIE_BOT.PCIE_DBGVECB26->PCIE_LOGIC_OUTS_B7_R_3": { "can_invert": "0", - "dst_wire": "PCIE_TRNTDLLPDATA13", + "src_wire": "PCIE_DBGVECB26", "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_18", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_3" }, - "PCIE_BOT.PCIE_PIPETX0DATA11->PCIE_LOGIC_OUTS_B15_L_16": { + "PCIE_BOT.PCIE_TL2ERRHDR54->PCIE_LOGIC_OUTS_B11_L_10": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_16", + "src_wire": "PCIE_TL2ERRHDR54", "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_10" }, - "PCIE_BOT.PCIE_TRNFCNPD10->PCIE_LOGIC_OUTS_B12_L_6": { + "PCIE_BOT.PCIE_IMUX38_L_3->PCIE_PIPERX3DATA13": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_6", + "src_wire": "PCIE_IMUX38_L_3", "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA13" }, - "PCIE_BOT.PCIE_IMUX10_R_4->PCIE_CFGERRAERHEADERLOG56": { + "PCIE_BOT.PCIE_PIPETX1DATA15->PCIE_LOGIC_OUTS_B6_L_4": { "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG56", + "src_wire": "PCIE_PIPETX1DATA15", "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_4" }, - "PCIE_BOT.PCIE_PIPETX2DATA11->PCIE_LOGIC_OUTS_B15_L_12": { + "PCIE_BOT.PCIE_IMUX12_R_14->PCIE_CFGERRAERHEADERLOG17": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_12", + "src_wire": "PCIE_IMUX12_R_14", "is_directional": "1", - "src_wire": "PCIE_PIPETX2DATA11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG17" }, - "PCIE_BOT.PCIE_IMUX6_R_14->PCIE_CFGMGMTWRENN": { + "PCIE_BOT.PCIE_MIMTXWDATA31->PCIE_LOGIC_OUTS_B7_R_9": { "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTWRENN", + "src_wire": "PCIE_MIMTXWDATA31", "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_9" }, - "PCIE_BOT.PCIE_IMUX8_R_5->PCIE_CFGMGMTDI12": { + "PCIE_BOT.PCIE_DBGVECB7->PCIE_LOGIC_OUTS_B23_R_14": { "can_invert": "0", - "dst_wire": "PCIE_CFGMGMTDI12", + "src_wire": "PCIE_DBGVECB7", "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_14" }, - "PCIE_BOT.PCIE_IMUX36_L_15->PCIE_PIPERX2DATA9": { + "PCIE_BOT.PCIE_IMUX35_R_15->PCIE_PIPERX6STATUS2": { "can_invert": "0", - "dst_wire": "PCIE_PIPERX2DATA9", + "src_wire": "PCIE_IMUX35_R_15", "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_15", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6STATUS2" }, - "PCIE_BOT.PCIE_IMUX3_L_14->PCIE_TRNFCSEL1": { + "PCIE_BOT.PCIE_DBGVECB63->PCIE_LOGIC_OUTS_B18_L_7": { "can_invert": "0", - "dst_wire": "PCIE_TRNFCSEL1", + "src_wire": "PCIE_DBGVECB63", "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_14", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_7" }, - "PCIE_BOT.PCIE_PLDBGVEC2->PCIE_LOGIC_OUTS_B23_L_15": { + "PCIE_BOT.PCIE_PIPETX6DATA7->PCIE_LOGIC_OUTS_B6_R_13": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_15", + "src_wire": "PCIE_PIPETX6DATA7", "is_directional": "1", - "src_wire": "PCIE_PLDBGVEC2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_13" }, - "PCIE_BOT.PCIE_IMUX8_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM0": { + "PCIE_BOT.PCIE_TRNFCPD10->PCIE_LOGIC_OUTS_B5_L_1": { "can_invert": "0", - "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", + "src_wire": "PCIE_TRNFCPD10", "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_1" }, - "PCIE_BOT.PCIE_IMUX16_L_15->PCIE_PIPERX2CHARISK1": { + "PCIE_BOT.PCIE_IMUX16_L_1->PCIE_PLDBGMODE1": { "can_invert": "0", - "dst_wire": "PCIE_PIPERX2CHARISK1", + "src_wire": "PCIE_IMUX16_L_1", "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_15", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_PLDBGMODE1" }, - "PCIE_BOT.PCIE_TRNTDSTRDY2->PCIE_LOGIC_OUTS_B3_R_0": { + "PCIE_BOT.PCIE_DBGVECB54->PCIE_LOGIC_OUTS_B21_L_4": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0", + "src_wire": "PCIE_DBGVECB54", "is_directional": "1", - "src_wire": "PCIE_TRNTDSTRDY2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_4" }, - "PCIE_BOT.PCIE_DBGVECB5->PCIE_LOGIC_OUTS_B22_R_12": { + "PCIE_BOT.PCIE_DBGVECB42->PCIE_LOGIC_OUTS_B21_L_1": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_12", + "src_wire": "PCIE_DBGVECB42", "is_directional": "1", - "src_wire": "PCIE_DBGVECB5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_1" }, - "PCIE_BOT.PCIE_IMUX17_L_1->PCIE_PLDBGMODE2": { + "PCIE_BOT.PCIE_IMUX34_R_5->PCIE_PIPERX7DATA7": { "can_invert": "0", - "dst_wire": "PCIE_PLDBGMODE2", + "src_wire": "PCIE_IMUX34_R_5", "is_directional": "1", - "src_wire": "PCIE_IMUX17_L_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA7" }, - "PCIE_BOT.PCIE_TRNFCPD11->PCIE_LOGIC_OUTS_B6_L_1": { + "PCIE_BOT.PCIE_IMUX13_L_5->PCIE_CFGSUBSYSID5": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_1", + "src_wire": "PCIE_IMUX13_L_5", "is_directional": "1", - "src_wire": "PCIE_TRNFCPD11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID5" }, - "PCIE_BOT.PCIE_IMUX11_L_15->PCIE_CFGDSN40": { + "PCIE_BOT.PCIE_MIMRXWDATA54->PCIE_LOGIC_OUTS_B5_R_16": { "can_invert": "0", - "dst_wire": "PCIE_CFGDSN40", + "src_wire": "PCIE_MIMRXWDATA54", "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_15", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_16" + }, + "PCIE_BOT.PCIE_IMUX1_L_11->PCIE_TRNTREM1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTREM1" + }, + "PCIE_BOT.PCIE_IMUX2_L_7->PCIE_TRNTD114": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD114" + }, + "PCIE_BOT.PCIE_TRNRD31->PCIE_LOGIC_OUTS_B5_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_13" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA13->PCIE_LOGIC_OUTS_B9_L_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_15" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ2->PCIE_LOGIC_OUTS_B18_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_16" + }, + "PCIE_BOT.PCIE_IMUX2_L_16->PCIE_TRNTDLLPDATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA5" + }, + "PCIE_BOT.PCIE_IMUX9_L_7->PCIE_CFGDSN6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN6" + }, + "PCIE_BOT.PCIE_IMUX39_L_14->PCIE_PIPERX2DATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA12" + }, + "PCIE_BOT.PCIE_TRNRD54->PCIE_LOGIC_OUTS_B5_L_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD54", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_18" + }, + "PCIE_BOT.PCIE_IMUX16_R_19->PCIE_PIPERX4CHARISK1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4CHARISK1" + }, + "PCIE_BOT.PCIE_DBGVECA24->PCIE_LOGIC_OUTS_B23_R_19": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_19" + }, + "PCIE_BOT.PCIE_IMUX36_R_15->PCIE_PIPERX6DATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA9" + }, + "PCIE_BOT.PCIE_IMUX10_L_4->PCIE_CFGFORCEMPS0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCEMPS0" + }, + "PCIE_BOT.PCIE_IMUX7_L_2->PCIE_CFGERRAERHEADERLOG85": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG85" + }, + "PCIE_BOT.PCIE_IMUX33_R_10->PCIE_PIPERX5DATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA2" + }, + "PCIE_BOT.PCIE_IMUX14_R_2->PCIE_CFGMGMTDI1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI1" + }, + "PCIE_BOT.PCIE_PIPETX1DATA2->PCIE_LOGIC_OUTS_B11_L_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_7" + }, + "PCIE_BOT.PCIE_TRNFCCPLD0->PCIE_LOGIC_OUTS_B7_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_8" + }, + "PCIE_BOT.PCIE_IMUX0_L_12->PCIE_TRNTSRCRDY": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTSRCRDY" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA24->PCIE_LOGIC_OUTS_B6_L_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_18" + }, + "PCIE_BOT.PCIE_DBGVECB31->PCIE_LOGIC_OUTS_B13_R_2": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_2" + }, + "PCIE_BOT.PCIE_IMUX12_R_15->PCIE_CFGERRCPLTIMEOUTN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRCPLTIMEOUTN" + }, + "PCIE_BOT.PCIE_IMUX12_L_16->PCIE_CFGAERINTERRUPTMSGNUM4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM4" + }, + "PCIE_BOT.PCIE_IMUX10_R_0->PCIE_TRNTD89": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD89" + }, + "PCIE_BOT.PCIE_IMUX13_R_0->PCIE_CFGERRAERHEADERLOG71": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG71" + }, + "PCIE_BOT.PCIE_PIPETX7DATA2->PCIE_LOGIC_OUTS_B11_R_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_3" + }, + "PCIE_BOT.PCIE_IMUX8_L_17->PCIE_CFGDSN45": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN45" + }, + "PCIE_BOT.PCIE_PLTXPMSTATE1->PCIE_LOGIC_OUTS_B18_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLTXPMSTATE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA8->PCIE_LOGIC_OUTS_B9_L_12": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_12" + }, + "PCIE_BOT.PCIE_IMUX0_R_11->PCIE_TRNTD70": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD70" + }, + "PCIE_BOT.PCIE_PIPERX0POLARITY->PCIE_LOGIC_OUTS_B1_L_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPERX0POLARITY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_18" + }, + "PCIE_BOT.PCIE_MIMTXWDATA43->PCIE_LOGIC_OUTS_B19_R_3": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_3" + }, + "PCIE_BOT.PCIE_IMUX13_L_2->PCIE_CFGREVID5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID5" + }, + "PCIE_BOT.PCIE_IMUX15_R_1->PCIE_CFGERRAERHEADERLOG69": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG69" + }, + "PCIE_BOT.PCIE_IMUX9_L_11->PCIE_CFGDSN22": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN22" + }, + "PCIE_BOT.PCIE_IMUX17_R_1->PCIE_CFGDSFUNCTIONNUMBER0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSFUNCTIONNUMBER0" + }, + "PCIE_BOT.PCIE_IMUX0_R_2->PCIE_MIMTXRDATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA8" + }, + "PCIE_BOT.PCIE_IMUX18_R_12->PCIE_CFGVENDID7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX18_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID7" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_13": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_13" + }, + "PCIE_BOT.PCIE_MIMTXWDATA35->PCIE_LOGIC_OUTS_B17_R_9": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_9" + }, + "PCIE_BOT.PCIE_IMUX3_R_8->PCIE_MIMTXRDATA35": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA35" + }, + "PCIE_BOT.PCIE_IMUX5_L_8->PCIE_CFGERRAERHEADERLOG107": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG107" + }, + "PCIE_BOT.PCIE_IMUX34_L_14->PCIE_PIPERX2DATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA15" + }, + "PCIE_BOT.PCIE_PL2L0REQ->PCIE_LOGIC_OUTS_B20_R_19": { + "can_invert": "0", + "src_wire": "PCIE_PL2L0REQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_19" + }, + "PCIE_BOT.PCIE_TRNRD1->PCIE_LOGIC_OUTS_B2_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_5" + }, + "PCIE_BOT.PCIE_PIPETX4DATA15->PCIE_LOGIC_OUTS_B6_R_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_15" + }, + "PCIE_BOT.PCIE_MIMRXWDATA47->PCIE_LOGIC_OUTS_B18_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_19" + }, + "PCIE_BOT.PCIE_DRPDO8->PCIE_LOGIC_OUTS_B21_L_19": { + "can_invert": "0", + "src_wire": "PCIE_DRPDO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_19" + }, + "PCIE_BOT.PCIE_IMUX15_R_14->PCIE_CFGINTERRUPTDI3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI3" + }, + "PCIE_BOT.PCIE_MIMTXWADDR9->PCIE_LOGIC_OUTS_B21_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_4" + }, + "PCIE_BOT.PCIE_TL2ERRHDR7->PCIE_LOGIC_OUTS_B7_R_10": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_10" + }, + "PCIE_BOT.PCIE_CFGMGMTDO9->PCIE_LOGIC_OUTS_B14_R_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_12" + }, + "PCIE_BOT.PCIE_IMUX0_R_17->PCIE_MIMRXRDATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA8" + }, + "PCIE_BOT.PCIE_MIMRXWADDR7->PCIE_LOGIC_OUTS_B11_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWADDR7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_19" + }, + "PCIE_BOT.PCIE_IMUX14_L_12->PCIE_CFGSUBSYSVENDID10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID10" + }, + "PCIE_BOT.PCIE_IMUX14_L_3->PCIE_CFGSUBSYSID2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID2" + }, + "PCIE_BOT.PCIE_IMUX3_L_1->PCIE_TRNTD91": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD91" + }, + "PCIE_BOT.PCIE_IMUX12_L_1->PCIE_CFGREVID0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID0" + }, + "PCIE_BOT.PCIE_IMUX34_R_18->PCIE_PIPERX4DATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA15" + }, + "PCIE_BOT.PCIE_IMUX7_R_13->PCIE_CFGMGMTDWADDR9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR9" + }, + "PCIE_BOT.PCIE_IMUX12_L_9->PCIE_CFGSUBSYSID14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID14" + }, + "PCIE_BOT.PCIE_TRNFCPD4->PCIE_LOGIC_OUTS_B2_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_1" + }, + "PCIE_BOT.PCIE_DBGVECA30->PCIE_LOGIC_OUTS_B21_R_17": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_17" + }, + "PCIE_BOT.PCIE_PIPETX4DATA1->PCIE_LOGIC_OUTS_B13_R_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_18" + }, + "PCIE_BOT.PCIE_TRNRD4->PCIE_LOGIC_OUTS_B8_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_6" + }, + "PCIE_BOT.PCIE_MIMTXWDATA0->PCIE_LOGIC_OUTS_B17_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_5" + }, + "PCIE_BOT.PCIE_PIPETX3COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3COMPLIANCE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_3" + }, + "PCIE_BOT.PCIE_IMUX13_R_5->PCIE_CFGERRAERHEADERLOG52": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG52" + }, + "PCIE_BOT.PCIE_IMUX13_R_9->PCIE_CFGERRAERHEADERLOG36": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG36" + }, + "PCIE_BOT.PCIE_TRNRSRCDSC->PCIE_LOGIC_OUTS_B3_R_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNRSRCDSC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_10" + }, + "PCIE_BOT.PCIE_PIPETX7DATA0->PCIE_LOGIC_OUTS_B9_R_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_3" }, "PCIE_BOT.PCIE_IMUX7_L_7->PCIE_CFGERRAERHEADERLOG105": { "can_invert": "0", - "dst_wire": "PCIE_CFGERRAERHEADERLOG105", - "is_directional": "1", "src_wire": "PCIE_IMUX7_L_7", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_IMUX15_L_13->PCIE_CFGSUBSYSVENDID15": { - "can_invert": "0", - "dst_wire": "PCIE_CFGSUBSYSVENDID15", "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_13", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG105" }, - "PCIE_BOT.PCIE_PIPETX0DATA10->PCIE_LOGIC_OUTS_B11_L_16": { + "PCIE_BOT.PCIE_IMUX11_L_9->PCIE_CFGDSN16": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_16", + "src_wire": "PCIE_IMUX11_L_9", "is_directional": "1", - "src_wire": "PCIE_PIPETX0DATA10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN16" }, - "PCIE_BOT.PCIE_IMUX11_R_0->PCIE_TRNTD90": { + "PCIE_BOT.PCIE_IMUX17_R_18->PCIE_CFGERRPOSTEDN": { "can_invert": "0", - "dst_wire": "PCIE_TRNTD90", + "src_wire": "PCIE_IMUX17_R_18", "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRPOSTEDN" + }, + "PCIE_BOT.PCIE_IMUX11_L_12->PCIE_CFGDSN28": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN28" + }, + "PCIE_BOT.PCIE_MIMRXWDATA52->PCIE_LOGIC_OUTS_B18_R_15": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA52", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_15" + }, + "PCIE_BOT.PCIE_PIPETX2ELECIDLE->PCIE_LOGIC_OUTS_B3_L_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2ELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_13" + }, + "PCIE_BOT.PCIE_IMUX2_L_12->PCIE_TRNTERRFWD": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTERRFWD" + }, + "PCIE_BOT.PCIE_IMUX4_L_0->PCIE_PLDIRECTEDLINKSPEED": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKSPEED" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSCURRENTSPEED1->PCIE_LOGIC_OUTS_B20_L_17": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSCURRENTSPEED1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_17" + }, + "PCIE_BOT.PCIE_IMUX37_L_16->PCIE_PIPERX2PHYSTATUS": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2PHYSTATUS" + }, + "PCIE_BOT.PCIE_TRNRD12->PCIE_LOGIC_OUTS_B1_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_8" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA1->PCIE_LOGIC_OUTS_B5_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_12" + }, + "PCIE_BOT.PCIE_TRNRD20->PCIE_LOGIC_OUTS_B1_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_10" + }, + "PCIE_BOT.PCIE_IMUX0_R_18->PCIE_MIMRXRDATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA12" + }, + "PCIE_BOT.PCIE_CFGMSGDATA13->PCIE_LOGIC_OUTS_B17_L_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_14" + }, + "PCIE_BOT.PCIE_MIMTXWDATA1->PCIE_LOGIC_OUTS_B19_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_5" + }, + "PCIE_BOT.PCIE_IMUX2_R_11->PCIE_TRNTD72": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD72" + }, + "PCIE_BOT.PCIE_DBGVECB3->PCIE_LOGIC_OUTS_B22_R_10": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_10" + }, + "PCIE_BOT.PCIE_TRNFCCPLH6->PCIE_LOGIC_OUTS_B5_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLH6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_8" + }, + "PCIE_BOT.PCIE_CLK1_R_12->PCIE_USERCLK2": { + "can_invert": "0", + "src_wire": "PCIE_CLK1_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_USERCLK2" + }, + "PCIE_BOT.PCIE_TL2ERRHDR47->PCIE_LOGIC_OUTS_B8_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_9" + }, + "PCIE_BOT.PCIE_TRNRD120->PCIE_LOGIC_OUTS_B5_R_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD120", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_13" + }, + "PCIE_BOT.PCIE_DBGSCLRK->PCIE_LOGIC_OUTS_B23_L_13": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_13" + }, + "PCIE_BOT.PCIE_IMUX5_R_11->PCIE_CFGMGMTBYTEENN3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTBYTEENN3" + }, + "PCIE_BOT.PCIE_IMUX9_L_17->PCIE_CFGDSN46": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN46" + }, + "PCIE_BOT.PCIE_TRNRD44->PCIE_LOGIC_OUTS_B1_L_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_16" + }, + "PCIE_BOT.PCIE_IMUX35_L_18->PCIE_PIPERX0DATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA14" + }, + "PCIE_BOT.PCIE_IMUX15_L_7->PCIE_CFGSUBSYSID13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID13" + }, + "PCIE_BOT.PCIE_IMUX21_R_12->PCIE_DBGSUBMODE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX21_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DBGSUBMODE" + }, + "PCIE_BOT.PCIE_TRNRD105->PCIE_LOGIC_OUTS_B5_R_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD105", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_18" + }, + "PCIE_BOT.PCIE_DBGVECB20->PCIE_LOGIC_OUTS_B16_R_5": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_5" + }, + "PCIE_BOT.PCIE_IMUX6_L_13->PCIE_CFGERRTLPCPLHEADER0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER0" + }, + "PCIE_BOT.PCIE_IMUX7_R_0->PCIE_MIMTXRDATA65": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA65" + }, + "PCIE_BOT.PCIE_DBGSCLRG->PCIE_LOGIC_OUTS_B22_L_11": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRG", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_11" + }, + "PCIE_BOT.PCIE_IMUX9_R_9->PCIE_CFGMGMTDI29": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI29" + }, + "PCIE_BOT.PCIE_MIMRXWDATA63->PCIE_LOGIC_OUTS_B10_R_18": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_18" + }, + "PCIE_BOT.PCIE_MIMRXWDATA50->PCIE_LOGIC_OUTS_B17_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_16" + }, + "PCIE_BOT.PCIE_IMUX7_R_17->PCIE_MIMRXRDATA67": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA67" + }, + "PCIE_BOT.PCIE_IMUX7_L_9->PCIE_CFGERRAERHEADERLOG113": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG113" + }, + "PCIE_BOT.PCIE_IMUX14_L_13->PCIE_CFGSUBSYSVENDID14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID14" + }, + "PCIE_BOT.PCIE_IMUX1_R_19->PCIE_MIMRXRDATA17": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA17" + }, + "PCIE_BOT.PCIE_IMUX12_R_9->PCIE_CFGERRAERHEADERLOG35": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG35" + }, + "PCIE_BOT.PCIE_MIMTXWADDR0->PCIE_LOGIC_OUTS_B23_R_7": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_7" + }, + "PCIE_BOT.PCIE_DBGVECB48->PCIE_LOGIC_OUTS_B19_L_3": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB48", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_3" + }, + "PCIE_BOT.PCIE_IMUX8_R_7->PCIE_MIMTXRDATA68": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA68" + }, + "PCIE_BOT.PCIE_PLLINKPARTNERGEN2SUPPORTED->PCIE_LOGIC_OUTS_B5_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PLLINKPARTNERGEN2SUPPORTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_2" + }, + "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRFATALERREN->PCIE_LOGIC_OUTS_B22_L_18": { + "can_invert": "0", + "src_wire": "PCIE_CFGROOTCONTROLSYSERRFATALERREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_18" + }, + "PCIE_BOT.PCIE_IMUX1_L_2->PCIE_TRNTD93": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD93" + }, + "PCIE_BOT.PCIE_IMUX36_R_9->PCIE_PIPERX5VALID": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5VALID" + }, + "PCIE_BOT.PCIE_PIPETX6DATA5->PCIE_LOGIC_OUTS_B4_R_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_13" + }, + "PCIE_BOT.PCIE_IMUX14_L_0->PCIE_CFGERRAERHEADERLOG75": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG75" + }, + "PCIE_BOT.PCIE_TL2ERRHDR5->PCIE_LOGIC_OUTS_B12_R_11": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_11" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMSIENABLE->PCIE_LOGIC_OUTS_B17_L_1": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTMSIENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_1" + }, + "PCIE_BOT.PCIE_IMUX15_L_0->PCIE_CFGERRAERHEADERLOG76": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG76" + }, + "PCIE_BOT.PCIE_IMUX0_L_19->PCIE_TRNTDLLPDATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA15" + }, + "PCIE_BOT.PCIE_TRNRD111->PCIE_LOGIC_OUTS_B1_R_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD111", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_16" + }, + "PCIE_BOT.PCIE_IMUX2_L_17->PCIE_TRNTDLLPDATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA9" + }, + "PCIE_BOT.PCIE_DBGVECA50->PCIE_LOGIC_OUTS_B17_R_11": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_11" + }, + "PCIE_BOT.PCIE_DBGVECC0->PCIE_LOGIC_OUTS_B19_L_7": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_7" + }, + "PCIE_BOT.PCIE_DBGVECB34->PCIE_LOGIC_OUTS_B22_R_1": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_1" + }, + "PCIE_BOT.PCIE_DBGVECB27->PCIE_LOGIC_OUTS_B8_R_3": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_3" + }, + "PCIE_BOT.PCIE_DBGVECB18->PCIE_LOGIC_OUTS_B6_R_5": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_5" + }, + "PCIE_BOT.PCIE_IMUX36_R_6->PCIE_PIPERX7DATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA1" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDUNLOCK->PCIE_LOGIC_OUTS_B9_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDUNLOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_19" + }, + "PCIE_BOT.PCIE_IMUX3_R_4->PCIE_MIMTXRDATA19": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA19" + }, + "PCIE_BOT.PCIE_IMUX16_R_13->PCIE_CFGINTERRUPTASSERTN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTASSERTN" + }, + "PCIE_BOT.PCIE_DBGVECB22->PCIE_LOGIC_OUTS_B7_R_4": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_4" + }, + "PCIE_BOT.PCIE_PIPETX2DATA9->PCIE_LOGIC_OUTS_B13_L_12": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_12" + }, + "PCIE_BOT.PCIE_IMUX11_R_18->PCIE_TRNTD3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD3" + }, + "PCIE_BOT.PCIE_IMUX10_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM2" + }, + "PCIE_BOT.PCIE_DRPDO7->PCIE_LOGIC_OUTS_B20_L_19": { + "can_invert": "0", + "src_wire": "PCIE_DRPDO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_19" + }, + "PCIE_BOT.PCIE_MIMRXWDATA66->PCIE_LOGIC_OUTS_B18_R_17": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA66", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_17" + }, + "PCIE_BOT.PCIE_MIMTXWDATA14->PCIE_LOGIC_OUTS_B21_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_6" + }, + "PCIE_BOT.PCIE_IMUX12_L_12->PCIE_CFGSUBSYSVENDID8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID8" + }, + "PCIE_BOT.PCIE_IMUX9_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM1" + }, + "PCIE_BOT.PCIE_TRNRD107->PCIE_LOGIC_OUTS_B8_R_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD107", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_17" + }, + "PCIE_BOT.PCIE_IMUX5_R_4->PCIE_CFGMGMTDI8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI8" + }, + "PCIE_BOT.PCIE_DBGSCLRI->PCIE_LOGIC_OUTS_B23_L_12": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRI", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_12" + }, + "PCIE_BOT.PCIE_TRNFCNPD3->PCIE_LOGIC_OUTS_B10_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_4" + }, + "PCIE_BOT.PCIE_PIPETX3DATA11->PCIE_LOGIC_OUTS_B15_L_1": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_1" + }, + "PCIE_BOT.PCIE_IMUX12_L_2->PCIE_CFGREVID4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID4" + }, + "PCIE_BOT.PCIE_IMUX2_L_14->PCIE_TRNFCSEL0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNFCSEL0" + }, + "PCIE_BOT.PCIE_DBGVECB51->PCIE_LOGIC_OUTS_B18_L_4": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_4" + }, + "PCIE_BOT.PCIE_IMUX7_R_9->PCIE_CFGMGMTDI27": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI27" + }, + "PCIE_BOT.PCIE_MIMTXWDATA6->PCIE_LOGIC_OUTS_B20_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_5" + }, + "PCIE_BOT.PCIE_IMUX0_R_12->PCIE_TRNTD66": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD66" + }, + "PCIE_BOT.PCIE_PIPETX0POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0POWERDOWN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_17" + }, + "PCIE_BOT.PCIE_TRNRD30->PCIE_LOGIC_OUTS_B3_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_12" + }, + "PCIE_BOT.PCIE_IMUX0_R_13->PCIE_TRNTD62": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD62" + }, + "PCIE_BOT.PCIE_MIMRXWADDR11->PCIE_LOGIC_OUTS_B14_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWADDR11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_16" + }, + "PCIE_BOT.PCIE_PIPETX4DATA10->PCIE_LOGIC_OUTS_B11_R_16": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_16" + }, + "PCIE_BOT.PCIE_IMUX3_L_5->PCIE_TRNTD107": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD107" + }, + "PCIE_BOT.PCIE_PLDBGVEC2->PCIE_LOGIC_OUTS_B23_L_15": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_15" + }, + "PCIE_BOT.PCIE_IMUX37_R_8->PCIE_PIPERX5DATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA8" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD0->PCIE_LOGIC_OUTS_B19_L_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_14" + }, + "PCIE_BOT.PCIE_PLRECEIVEDHOTRST->PCIE_LOGIC_OUTS_B13_R_8": { + "can_invert": "0", + "src_wire": "PCIE_PLRECEIVEDHOTRST", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_8" + }, + "PCIE_BOT.PCIE_IMUX9_R_19->PCIE_TRNTD5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD5" + }, + "PCIE_BOT.PCIE_IMUX15_R_12->PCIE_CFGDSBUSNUMBER1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER1" + }, + "PCIE_BOT.PCIE_DBGSCLRE->PCIE_LOGIC_OUTS_B20_L_11": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_11" + }, + "PCIE_BOT.PCIE_IMUX33_R_9->PCIE_PIPERX5CHANISALIGNED": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5CHANISALIGNED" + }, + "PCIE_BOT.PCIE_TRNRD99->PCIE_LOGIC_OUTS_B1_R_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD99", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_19" + }, + "PCIE_BOT.PCIE_MIMTXRADDR12->PCIE_LOGIC_OUTS_B8_R_7": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_7" + }, + "PCIE_BOT.PCIE_DBGVECB53->PCIE_LOGIC_OUTS_B20_L_4": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_4" + }, + "PCIE_BOT.PCIE_TRNTDSTRDY2->PCIE_LOGIC_OUTS_B3_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TRNTDSTRDY2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0" + }, + "PCIE_BOT.PCIE_TRNRBARHIT7->PCIE_LOGIC_OUTS_B6_R_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNRBARHIT7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_8" + }, + "PCIE_BOT.PCIE_IMUX4_R_2->PCIE_MIMTXRDATA54": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA54" + }, + "PCIE_BOT.PCIE_TRNRD58->PCIE_LOGIC_OUTS_B3_L_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD58", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_19" + }, + "PCIE_BOT.PCIE_IMUX9_R_10->PCIE_CFGERRAERHEADERLOG30": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG30" + }, + "PCIE_BOT.PCIE_IMUX16_R_10->PCIE_PIPERX5CHARISK0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5CHARISK0" + }, + "PCIE_BOT.PCIE_IMUX0_R_1->PCIE_MIMTXRDATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA4" + }, + "PCIE_BOT.PCIE_IMUX10_L_13->PCIE_CFGDSN31": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN31" + }, + "PCIE_BOT.PCIE_IMUX4_L_5->PCIE_CFGERRAERHEADERLOG94": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG94" }, "PCIE_BOT.PCIE_MIMTXWDATA59->PCIE_LOGIC_OUTS_B11_R_4": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_4", - "is_directional": "1", "src_wire": "PCIE_MIMTXWDATA59", - "is_pseudo": "0" - }, - "PCIE_BOT.PCIE_TRNFCNPD8->PCIE_LOGIC_OUTS_B7_L_5": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_5", "is_directional": "1", - "src_wire": "PCIE_TRNFCNPD8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_4" + }, + "PCIE_BOT.PCIE_TRNFCPD6->PCIE_LOGIC_OUTS_B5_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_0" + }, + "PCIE_BOT.PCIE_PIPETX2DATA2->PCIE_LOGIC_OUTS_B11_L_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_14" + }, + "PCIE_BOT.PCIE_TL2ERRHDR34->PCIE_LOGIC_OUTS_B10_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_5" + }, + "PCIE_BOT.PCIE_IMUX14_R_1->PCIE_CFGERRAERHEADERLOG68": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG68" + }, + "PCIE_BOT.PCIE_PIPETX4ELECIDLE->PCIE_LOGIC_OUTS_B3_R_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4ELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_17" + }, + "PCIE_BOT.PCIE_IMUX1_R_9->PCIE_MIMTXRDATA37": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA37" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0->PCIE_LOGIC_OUTS_B21_L_17": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_17" + }, + "PCIE_BOT.PCIE_TL2ERRHDR40->PCIE_LOGIC_OUTS_B14_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_7" + }, + "PCIE_BOT.PCIE_PL2RXPMSTATE0->PCIE_LOGIC_OUTS_B13_R_19": { + "can_invert": "0", + "src_wire": "PCIE_PL2RXPMSTATE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_19" + }, + "PCIE_BOT.PCIE_MIMRXWDATA67->PCIE_LOGIC_OUTS_B14_R_17": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA67", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_17" + }, + "PCIE_BOT.PCIE_IMUX2_R_0->PCIE_MIMTXRDATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA2" + }, + "PCIE_BOT.PCIE_IMUX0_R_7->PCIE_MIMTXRDATA28": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA28" + }, + "PCIE_BOT.PCIE_IMUX14_R_17->PCIE_CFGERRMCBLOCKEDN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRMCBLOCKEDN" + }, + "PCIE_BOT.PCIE_TL2ERRHDR6->PCIE_LOGIC_OUTS_B6_R_10": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_10" + }, + "PCIE_BOT.PCIE_PLDBGVEC9->PCIE_LOGIC_OUTS_B20_R_7": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_7" + }, + "PCIE_BOT.PCIE_IMUX33_L_8->PCIE_PIPERX1DATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA10" + }, + "PCIE_BOT.PCIE_LL2PROTOCOLERR->PCIE_LOGIC_OUTS_B12_R_13": { + "can_invert": "0", + "src_wire": "PCIE_LL2PROTOCOLERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_13" + }, + "PCIE_BOT.PCIE_PIPETX3CHARISK0->PCIE_LOGIC_OUTS_B16_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3CHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_2" + }, + "PCIE_BOT.PCIE_IMUX5_R_7->PCIE_MIMTXRDATA41": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA41" + }, + "PCIE_BOT.PCIE_IMUX38_L_15->PCIE_PIPERX2STATUS1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2STATUS1" + }, + "PCIE_BOT.PCIE_PIPETX5COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5COMPLIANCE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_7" + }, + "PCIE_BOT.PCIE_TL2ERRHDR56->PCIE_LOGIC_OUTS_B13_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_11" + }, + "PCIE_BOT.PCIE_IMUX1_L_0->PCIE_PLDIRECTEDLINKCHANGE1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKCHANGE1" + }, + "PCIE_BOT.PCIE_PIPETX7ELECIDLE->PCIE_LOGIC_OUTS_B3_R_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7ELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_2" + }, + "PCIE_BOT.PCIE_TRNRD119->PCIE_LOGIC_OUTS_B5_R_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD119", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_14" + }, + "PCIE_BOT.PCIE_IMUX7_R_12->PCIE_CFGMGMTDWADDR5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR5" + }, + "PCIE_BOT.PCIE_TL2ERRHDR58->PCIE_LOGIC_OUTS_B15_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR58", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_11" + }, + "PCIE_BOT.PCIE_PIPETX0DATA6->PCIE_LOGIC_OUTS_B2_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_17" + }, + "PCIE_BOT.PCIE_IMUX2_R_7->PCIE_MIMTXRDATA30": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA30" + }, + "PCIE_BOT.PCIE_IMUX10_L_1->PCIE_CFGPMFORCESTATEENN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMFORCESTATEENN" + }, + "PCIE_BOT.PCIE_TRNRD47->PCIE_LOGIC_OUTS_B5_L_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_17" + }, + "PCIE_BOT.PCIE_IMUX38_R_16->PCIE_PIPERX6DATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA5" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD1->PCIE_LOGIC_OUTS_B20_L_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_14" + }, + "PCIE_BOT.PCIE_IMUX2_R_18->PCIE_MIMRXRDATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA14" + }, + "PCIE_BOT.PCIE_TRNRERRFWD->PCIE_LOGIC_OUTS_B5_R_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNRERRFWD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_10" + }, + "PCIE_BOT.PCIE_PIPETX2DATA15->PCIE_LOGIC_OUTS_B6_L_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_11" + }, + "PCIE_BOT.PCIE_TRNRD39->PCIE_LOGIC_OUTS_B1_L_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_15" + }, + "PCIE_BOT.PCIE_MIMTXWADDR10->PCIE_LOGIC_OUTS_B23_R_8": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_8" + }, + "PCIE_BOT.PCIE_IMUX4_L_10->PCIE_CFGERRAERHEADERLOG114": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG114" + }, + "PCIE_BOT.PCIE_TRNRD24->PCIE_LOGIC_OUTS_B3_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_11" + }, + "PCIE_BOT.PCIE_PIPETX3DATA7->PCIE_LOGIC_OUTS_B6_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_2" + }, + "PCIE_BOT.PCIE_IMUX39_L_16->PCIE_PIPERX2DATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA4" + }, + "PCIE_BOT.PCIE_IMUX10_L_2->PCIE_CFGPMTURNOFFOKN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMTURNOFFOKN" + }, + "PCIE_BOT.PCIE_PIPETX2COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2COMPLIANCE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_14" + }, + "PCIE_BOT.PCIE_TL2ERRHDR41->PCIE_LOGIC_OUTS_B16_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_7" + }, + "PCIE_BOT.PCIE_PLLANEREVERSALMODE1->PCIE_LOGIC_OUTS_B14_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLLANEREVERSALMODE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_0" + }, + "PCIE_BOT.PCIE_IMUX37_L_10->PCIE_PIPERX1DATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA0" + }, + "PCIE_BOT.PCIE_IMUX35_R_16->PCIE_PIPERX6DATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA6" + }, + "PCIE_BOT.PCIE_TRNRREM0->PCIE_LOGIC_OUTS_B1_R_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNRREM0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_11" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ1->PCIE_LOGIC_OUTS_B17_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_16" + }, + "PCIE_BOT.PCIE_TRNRD25->PCIE_LOGIC_OUTS_B5_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_11" + }, + "PCIE_BOT.PCIE_IMUX33_L_5->PCIE_PIPERX3CHANISALIGNED": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3CHANISALIGNED" + }, + "PCIE_BOT.PCIE_PIPETX2CHARISK0->PCIE_LOGIC_OUTS_B16_L_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2CHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_13" + }, + "PCIE_BOT.PCIE_IMUX13_L_16->PCIE_DRPEN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPEN" + }, + "PCIE_BOT.PCIE_PIPETX0COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0COMPLIANCE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_18" + }, + "PCIE_BOT.PCIE_TL2ERRHDR22->PCIE_LOGIC_OUTS_B14_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_1" + }, + "PCIE_BOT.PCIE_DBGVECA26->PCIE_LOGIC_OUTS_B8_R_18": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_18" + }, + "PCIE_BOT.PCIE_IMUX11_L_10->PCIE_CFGDSN20": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN20" + }, + "PCIE_BOT.PCIE_IMUX9_L_19->PCIE_CFGDSN54": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN54" + }, + "PCIE_BOT.PCIE_IMUX33_R_8->PCIE_PIPERX5DATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA10" + }, + "PCIE_BOT.PCIE_MIMTXWDATA7->PCIE_LOGIC_OUTS_B19_R_8": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_8" + }, + "PCIE_BOT.PCIE_IMUX3_R_12->PCIE_TRNTD69": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD69" + }, + "PCIE_BOT.PCIE_IMUX7_R_3->PCIE_MIMTXRDATA53": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA53" + }, + "PCIE_BOT.PCIE_IMUX6_R_10->PCIE_CFGMGMTBYTEENN0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTBYTEENN0" + }, + "PCIE_BOT.PCIE_MIMRXWDATA53->PCIE_LOGIC_OUTS_B11_R_17": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_17" + }, + "PCIE_BOT.PCIE_DBGVECA33->PCIE_LOGIC_OUTS_B22_R_16": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_16" + }, + "PCIE_BOT.PCIE_IMUX1_R_5->PCIE_MIMTXRDATA21": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA21" + }, + "PCIE_BOT.PCIE_IMUX2_L_0->PCIE_PLDIRECTEDLINKWIDTH0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKWIDTH0" + }, + "PCIE_BOT.PCIE_CFGAERECRCCHECKEN->PCIE_LOGIC_OUTS_B17_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGAERECRCCHECKEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_19" + }, + "PCIE_BOT.PCIE_DBGVECA56->PCIE_LOGIC_OUTS_B20_R_10": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_10" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLNOSNOOPEN->PCIE_LOGIC_OUTS_B20_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLNOSNOOPEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_15" + }, + "PCIE_BOT.PCIE_PIPETX5DATA11->PCIE_LOGIC_OUTS_B15_R_5": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_5" + }, + "PCIE_BOT.PCIE_PIPETX5DATA4->PCIE_LOGIC_OUTS_B0_R_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_6" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS->PCIE_LOGIC_OUTS_B14_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_19" + }, + "PCIE_BOT.PCIE_PLDBGVEC4->PCIE_LOGIC_OUTS_B23_L_16": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_16" + }, + "PCIE_BOT.PCIE_PIPETX4CHARISK1->PCIE_LOGIC_OUTS_B16_R_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4CHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_15" + }, + "PCIE_BOT.PCIE_TRNRD5->PCIE_LOGIC_OUTS_B9_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_6" + }, + "PCIE_BOT.PCIE_TRNRD40->PCIE_LOGIC_OUTS_B3_L_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_15" + }, + "PCIE_BOT.PCIE_IMUX37_R_17->PCIE_PIPERX6DATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA0" + }, + "PCIE_BOT.PCIE_IMUX15_R_10->PCIE_CFGDSDEVICENUMBER1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER1" + }, + "PCIE_BOT.PCIE_IMUX10_L_16->PCIE_CFGDSN43": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN43" + }, + "PCIE_BOT.PCIE_IMUX10_L_10->PCIE_CFGDSN19": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN19" + }, + "PCIE_BOT.PCIE_MIMRXWADDR3->PCIE_LOGIC_OUTS_B7_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWADDR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_16" + }, + "PCIE_BOT.PCIE_IMUX1_L_19->PCIE_TRNTDLLPDATA16": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA16" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLPHANTOMEN->PCIE_LOGIC_OUTS_B18_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLPHANTOMEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_15" + }, + "PCIE_BOT.PCIE_IMUX11_R_8->PCIE_CFGERRAERHEADERLOG40": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG40" + }, + "PCIE_BOT.PCIE_IMUX33_L_9->PCIE_PIPERX1CHANISALIGNED": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1CHANISALIGNED" + }, + "PCIE_BOT.PCIE_TL2ERRHDR57->PCIE_LOGIC_OUTS_B14_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_11" + }, + "PCIE_BOT.PCIE_IMUX2_R_5->PCIE_MIMTXRDATA22": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA22" + }, + "PCIE_BOT.PCIE_IMUX5_R_14->PCIE_CFGMGMTWRREADONLYN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTWRREADONLYN" + }, + "PCIE_BOT.PCIE_IMUX11_R_15->PCIE_CFGERRECRCN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRECRCN" + }, + "PCIE_BOT.PCIE_IMUX10_L_5->PCIE_CFGFORCEEXTENDEDSYNCON": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCEEXTENDEDSYNCON" + }, + "PCIE_BOT.PCIE_IMUX5_R_15->PCIE_TRNTD55": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD55" + }, + "PCIE_BOT.PCIE_TRNRD6->PCIE_LOGIC_OUTS_B10_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_6" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSBANDWIDTHSTATUS->PCIE_LOGIC_OUTS_B13_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_19" + }, + "PCIE_BOT.PCIE_PIPERX5POLARITY->PCIE_LOGIC_OUTS_B1_R_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPERX5POLARITY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_7" + }, + "PCIE_BOT.PCIE_IMUX36_L_19->PCIE_PIPERX0DATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA9" + }, + "PCIE_BOT.PCIE_IMUX2_L_9->PCIE_TRNTD122": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD122" + }, + "PCIE_BOT.PCIE_IMUX19_R_0->PCIE_CFGPORTNUMBER3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX19_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER3" + }, + "PCIE_BOT.PCIE_MIMTXWDATA19->PCIE_LOGIC_OUTS_B4_R_8": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_8" + }, + "PCIE_BOT.PCIE_CFGMGMTDO8->PCIE_LOGIC_OUTS_B12_R_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_12" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETO->PCIE_LOGIC_OUTS_B17_L_18": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDPMETO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_18" + }, + "PCIE_BOT.PCIE_CFGMSGDATA11->PCIE_LOGIC_OUTS_B14_L_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_14" + }, + "PCIE_BOT.PCIE_IMUX14_R_9->PCIE_CFGERRAERHEADERLOG37": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG37" + }, + "PCIE_BOT.PCIE_IMUX3_L_3->PCIE_TRNTD99": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD99" + }, + "PCIE_BOT.PCIE_IMUX9_R_5->PCIE_CFGMGMTDI13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI13" + }, + "PCIE_BOT.PCIE_MIMTXWDATA17->PCIE_LOGIC_OUTS_B5_R_7": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_7" + }, + "PCIE_BOT.PCIE_IMUX10_L_18->PCIE_CFGDSN51": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN51" + }, + "PCIE_BOT.PCIE_MIMRXWADDR9->PCIE_LOGIC_OUTS_B17_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWADDR9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_19" + }, + "PCIE_BOT.PCIE_IMUX33_R_19->PCIE_PIPERX4DATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA10" + }, + "PCIE_BOT.PCIE_DBGVECA62->PCIE_LOGIC_OUTS_B14_R_8": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_8" + }, + "PCIE_BOT.PCIE_TRNFCPD5->PCIE_LOGIC_OUTS_B3_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_1" + }, + "PCIE_BOT.PCIE_MIMTXWDATA13->PCIE_LOGIC_OUTS_B5_R_9": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_9" + }, + "PCIE_BOT.PCIE_IMUX7_R_7->PCIE_MIMTXRDATA43": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA43" + }, + "PCIE_BOT.PCIE_IMUX13_R_18->PCIE_TRNTD43": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD43" + }, + "PCIE_BOT.PCIE_TRNRD23->PCIE_LOGIC_OUTS_B1_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_11" + }, + "PCIE_BOT.PCIE_IMUX19_R_2->PCIE_CFGERRAERHEADERLOG65": { + "can_invert": "0", + "src_wire": "PCIE_IMUX19_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG65" + }, + "PCIE_BOT.PCIE_TL2ERRHDR45->PCIE_LOGIC_OUTS_B10_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_8" + }, + "PCIE_BOT.PCIE_PIPETX6DATA2->PCIE_LOGIC_OUTS_B11_R_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_14" + }, + "PCIE_BOT.PCIE_PIPETX7DATA3->PCIE_LOGIC_OUTS_B15_R_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_3" + }, + "PCIE_BOT.PCIE_PLDBGVEC11->PCIE_LOGIC_OUTS_B22_R_4": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_4" + }, + "PCIE_BOT.PCIE_IMUX16_R_0->PCIE_CFGPORTNUMBER0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER0" + }, + "PCIE_BOT.PCIE_DBGVECA59->PCIE_LOGIC_OUTS_B19_R_9": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA59", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_9" + }, + "PCIE_BOT.PCIE_IMUX20_R_2->PCIE_CFGDSDEVICENUMBER3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER3" + }, + "PCIE_BOT.PCIE_IMUX37_L_19->PCIE_PIPERX0DATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA8" + }, + "PCIE_BOT.PCIE_MIMTXWDATA38->PCIE_LOGIC_OUTS_B18_R_0": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_0" + }, + "PCIE_BOT.PCIE_IMUX39_L_3->PCIE_PIPERX3DATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA12" + }, + "PCIE_BOT.PCIE_IMUX0_R_3->PCIE_MIMTXRDATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA12" + }, + "PCIE_BOT.PCIE_MIMTXWDATA48->PCIE_LOGIC_OUTS_B14_R_1": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA48", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_1" + }, + "PCIE_BOT.PCIE_TRNRD8->PCIE_LOGIC_OUTS_B2_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_7" + }, + "PCIE_BOT.PCIE_IMUX16_R_7->PCIE_CFGERRAERHEADERLOG44": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG44" + }, + "PCIE_BOT.PCIE_IMUX15_R_17->PCIE_CFGERRINTERNALUNCORN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRINTERNALUNCORN" + }, + "PCIE_BOT.PCIE_PIPETX7DATA5->PCIE_LOGIC_OUTS_B4_R_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_2" + }, + "PCIE_BOT.PCIE_TRNFCPH0->PCIE_LOGIC_OUTS_B2_R_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPH0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_7" + }, + "PCIE_BOT.PCIE_PIPETX0ELECIDLE->PCIE_LOGIC_OUTS_B3_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0ELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_17" + }, + "PCIE_BOT.PCIE_PIPETX6DATA12->PCIE_LOGIC_OUTS_B0_R_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_11" + }, + "PCIE_BOT.PCIE_TL2ERRHDR16->PCIE_LOGIC_OUTS_B9_R_8": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_8" + }, + "PCIE_BOT.PCIE_IMUX17_R_7->PCIE_CFGERRAERHEADERLOG45": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG45" + }, + "PCIE_BOT.PCIE_PIPETX7POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7POWERDOWN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_2" + }, + "PCIE_BOT.PCIE_IMUX11_L_13->PCIE_CFGDSN32": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN32" + }, + "PCIE_BOT.PCIE_IMUX0_L_4->PCIE_TRNTD100": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD100" + }, + "PCIE_BOT.PCIE_PIPETX2DATA10->PCIE_LOGIC_OUTS_B11_L_12": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_12" + }, + "PCIE_BOT.PCIE_TRNRD38->PCIE_LOGIC_OUTS_B5_L_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_14" + }, + "PCIE_BOT.PCIE_IMUX10_L_0->PCIE_PLDIRECTEDLTSSMNEW1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW1" + }, + "PCIE_BOT.PCIE_MIMTXWDATA18->PCIE_LOGIC_OUTS_B1_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_5" + }, + "PCIE_BOT.PCIE_PIPETX5DATA14->PCIE_LOGIC_OUTS_B2_R_4": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_4" + }, + "PCIE_BOT.PCIE_IMUX37_R_9->PCIE_PIPERX5PHYSTATUS": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5PHYSTATUS" + }, + "PCIE_BOT.PCIE_IMUX35_L_7->PCIE_PIPERX1DATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA14" + }, + "PCIE_BOT.PCIE_TRNRD109->PCIE_LOGIC_OUTS_B10_R_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD109", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_17" + }, + "PCIE_BOT.PCIE_IMUX17_L_0->PCIE_CFGPORTNUMBER4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER4" + }, + "PCIE_BOT.PCIE_IMUX16_R_4->PCIE_PIPERX7CHARISK1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7CHARISK1" + }, + "PCIE_BOT.PCIE_IMUX9_R_8->PCIE_CFGERRAERHEADERLOG38": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG38" + }, + "PCIE_BOT.PCIE_PIPETX1DATA9->PCIE_LOGIC_OUTS_B13_L_5": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_5" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTD->PCIE_LOGIC_OUTS_B12_L_18": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_18" + }, + "PCIE_BOT.PCIE_PIPETX0DATA3->PCIE_LOGIC_OUTS_B15_L_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_18" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSDLLACTIVE->PCIE_LOGIC_OUTS_B12_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSDLLACTIVE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_19" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO4->PCIE_LOGIC_OUTS_B15_L_8": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_8" + }, + "PCIE_BOT.PCIE_MIMTXWDATA44->PCIE_LOGIC_OUTS_B8_R_1": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_1" + }, + "PCIE_BOT.PCIE_IMUX7_R_4->PCIE_CFGMGMTDI10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI10" + }, + "PCIE_BOT.PCIE_MIMTXRADDR0->PCIE_LOGIC_OUTS_B20_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_4" + }, + "PCIE_BOT.PCIE_TL2ERRHDR42->PCIE_LOGIC_OUTS_B17_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_7" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRNONFATAL->PCIE_LOGIC_OUTS_B15_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDERRNONFATAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_15" + }, + "PCIE_BOT.PCIE_IMUX36_R_19->PCIE_PIPERX4DATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA9" + }, + "PCIE_BOT.PCIE_TRNRD14->PCIE_LOGIC_OUTS_B3_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_8" + }, + "PCIE_BOT.PCIE_IMUX1_L_17->PCIE_TRNTDLLPDATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA8" + }, + "PCIE_BOT.PCIE_IMUX7_R_19->PCIE_MIMRXRDATA59": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA59" + }, + "PCIE_BOT.PCIE_IMUX10_R_18->PCIE_TRNTD2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD2" + }, + "PCIE_BOT.PCIE_PIPETX1CHARISK0->PCIE_LOGIC_OUTS_B16_L_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1CHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_6" + }, + "PCIE_BOT.PCIE_TL2ERRHDR60->PCIE_LOGIC_OUTS_B10_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_12" + }, + "PCIE_BOT.PCIE_IMUX8_R_3->PCIE_TRNTD78": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD78" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE5->PCIE_LOGIC_OUTS_B12_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLLTSSMSTATE5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_0" + }, + "PCIE_BOT.PCIE_IMUX6_L_19->PCIE_CFGERRTLPCPLHEADER24": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER24" + }, + "PCIE_BOT.PCIE_TRNFCNPD11->PCIE_LOGIC_OUTS_B13_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_6" + }, + "PCIE_BOT.PCIE_IMUX33_R_5->PCIE_PIPERX7CHANISALIGNED": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7CHANISALIGNED" + }, + "PCIE_BOT.PCIE_IMUX6_R_2->PCIE_MIMTXRDATA56": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA56" + }, + "PCIE_BOT.PCIE_MIMTXWADDR6->PCIE_LOGIC_OUTS_B11_R_2": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_2" + }, + "PCIE_BOT.PCIE_PLDIRECTEDCHANGEDONE->PCIE_LOGIC_OUTS_B0_L_3": { + "can_invert": "0", + "src_wire": "PCIE_PLDIRECTEDCHANGEDONE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_3" + }, + "PCIE_BOT.PCIE_IMUX33_L_4->PCIE_PIPERX3DATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA10" + }, + "PCIE_BOT.PCIE_CFGMSGDATA9->PCIE_LOGIC_OUTS_B19_L_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_12" + }, + "PCIE_BOT.PCIE_TRNRD26->PCIE_LOGIC_OUTS_B7_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_11" + }, + "PCIE_BOT.PCIE_PIPETX1DATA5->PCIE_LOGIC_OUTS_B4_L_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_6" + }, + "PCIE_BOT.PCIE_DBGVECB17->PCIE_LOGIC_OUTS_B13_R_6": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_6" + }, + "PCIE_BOT.PCIE_CFGLINKCONTROLASPMCONTROL0->PCIE_LOGIC_OUTS_B15_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKCONTROLASPMCONTROL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_19" + }, + "PCIE_BOT.PCIE_PL2RECEIVERERR->PCIE_LOGIC_OUTS_B10_R_14": { + "can_invert": "0", + "src_wire": "PCIE_PL2RECEIVERERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_14" + }, + "PCIE_BOT.PCIE_TL2ERRHDR12->PCIE_LOGIC_OUTS_B10_R_9": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_9" + }, + "PCIE_BOT.PCIE_IMUX15_R_6->PCIE_CFGERRAERHEADERLOG48": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG48" }, "PCIE_BOT.PCIE_IMUX8_L_15->PCIE_CFGDSN37": { "can_invert": "0", - "dst_wire": "PCIE_CFGDSN37", - "is_directional": "1", "src_wire": "PCIE_IMUX8_L_15", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN37" + }, + "PCIE_BOT.PCIE_TRNTDLLPDSTRDY->PCIE_LOGIC_OUTS_B11_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNTDLLPDSTRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_11" + }, + "PCIE_BOT.PCIE_TRNRD2->PCIE_LOGIC_OUTS_B3_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_5" + }, + "PCIE_BOT.PCIE_IMUX8_L_0->PCIE_PLDIRECTEDLTSSMNEWVLD": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEWVLD" + }, + "PCIE_BOT.PCIE_IMUX0_L_7->PCIE_TRNTD112": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD112" + }, + "PCIE_BOT.PCIE_TRNFCNPD2->PCIE_LOGIC_OUTS_B9_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_4" + }, + "PCIE_BOT.PCIE_IMUX4_R_18->PCIE_MIMRXRDATA60": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA60" + }, + "PCIE_BOT.PCIE_DBGVECB33->PCIE_LOGIC_OUTS_B22_R_2": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_2" + }, + "PCIE_BOT.PCIE_TRNFCNPD0->PCIE_LOGIC_OUTS_B10_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_3" + }, + "PCIE_BOT.PCIE_DBGVECB62->PCIE_LOGIC_OUTS_B21_L_6": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_6" + }, + "PCIE_BOT.PCIE_IMUX5_R_0->PCIE_MIMTXRDATA63": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA63" + }, + "PCIE_BOT.PCIE_MIMTXWDATA33->PCIE_LOGIC_OUTS_B4_R_7": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_7" + }, + "PCIE_BOT.PCIE_MIMTXWADDR8->PCIE_LOGIC_OUTS_B12_R_3": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_3" + }, + "PCIE_BOT.PCIE_MIMTXWDATA3->PCIE_LOGIC_OUTS_B7_R_7": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_7" + }, + "PCIE_BOT.PCIE_IMUX3_R_18->PCIE_MIMRXRDATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA15" + }, + "PCIE_BOT.PCIE_TRNRD32->PCIE_LOGIC_OUTS_B8_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_13" + }, + "PCIE_BOT.PCIE_IMUX0_L_15->PCIE_TRNFCSEL2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNFCSEL2" + }, + "PCIE_BOT.PCIE_CFGMSGDATA8->PCIE_LOGIC_OUTS_B18_L_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_12" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTA->PCIE_LOGIC_OUTS_B10_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTA", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_16" + }, + "PCIE_BOT.PCIE_DBGSCLRF->PCIE_LOGIC_OUTS_B21_L_11": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRF", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_11" + }, + "PCIE_BOT.PCIE_IMUX10_R_8->PCIE_CFGERRAERHEADERLOG39": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG39" + }, + "PCIE_BOT.PCIE_PIPETX1DATA13->PCIE_LOGIC_OUTS_B4_L_4": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_4" + }, + "PCIE_BOT.PCIE_TRNFCPD0->PCIE_LOGIC_OUTS_B5_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_3" + }, + "PCIE_BOT.PCIE_IMUX35_R_14->PCIE_PIPERX6DATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA14" + }, + "PCIE_BOT.PCIE_IMUX39_R_14->PCIE_PIPERX6DATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA12" + }, + "PCIE_BOT.PCIE_IMUX4_R_1->PCIE_MIMTXRDATA58": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA58" + }, + "PCIE_BOT.PCIE_IMUX5_L_2->PCIE_CFGERRAERHEADERLOG83": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG83" + }, + "PCIE_BOT.PCIE_DBGVECA45->PCIE_LOGIC_OUTS_B21_R_13": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_13" + }, + "PCIE_BOT.PCIE_IMUX32_L_4->PCIE_PIPERX3DATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA11" + }, + "PCIE_BOT.PCIE_IMUX34_R_14->PCIE_PIPERX6DATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA15" + }, + "PCIE_BOT.PCIE_IMUX36_L_9->PCIE_PIPERX1VALID": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1VALID" + }, + "PCIE_BOT.PCIE_IMUX6_L_14->PCIE_CFGERRTLPCPLHEADER4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER4" + }, + "PCIE_BOT.PCIE_IMUX1_R_1->PCIE_MIMTXRDATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA5" + }, + "PCIE_BOT.PCIE_MIMRXWDATA14->PCIE_LOGIC_OUTS_B4_R_18": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_18" + }, + "PCIE_BOT.PCIE_TL2ERRHDR24->PCIE_LOGIC_OUTS_B17_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_2" + }, + "PCIE_BOT.PCIE_IMUX6_L_7->PCIE_CFGERRAERHEADERLOG104": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG104" + }, + "PCIE_BOT.PCIE_CFGDEVSTATUSURDETECTED->PCIE_LOGIC_OUTS_B17_L_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVSTATUSURDETECTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_10" + }, + "PCIE_BOT.PCIE_IMUX4_L_12->PCIE_CFGERRAERHEADERLOG122": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG122" + }, + "PCIE_BOT.PCIE_IMUX36_R_8->PCIE_PIPERX5DATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA9" + }, + "PCIE_BOT.PCIE_IMUX9_R_3->PCIE_CFGMGMTDI3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI3" + }, + "PCIE_BOT.PCIE_PIPETX2POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2POWERDOWN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_13" + }, + "PCIE_BOT.PCIE_IMUX0_R_8->PCIE_MIMTXRDATA32": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA32" + }, + "PCIE_BOT.PCIE_TRNFCPH7->PCIE_LOGIC_OUTS_B4_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPH7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_3" + }, + "PCIE_BOT.PCIE_PIPETX3CHARISK1->PCIE_LOGIC_OUTS_B16_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3CHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_0" + }, + "PCIE_BOT.PCIE_IMUX12_L_5->PCIE_CFGSUBSYSID4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID4" + }, + "PCIE_BOT.PCIE_IMUX4_R_4->PCIE_CFGMGMTDI7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI7" + }, + "PCIE_BOT.PCIE_IMUX8_R_17->PCIE_TRNTD46": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD46" + }, + "PCIE_BOT.PCIE_IMUX20_R_0->PCIE_CFGVENDID15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID15" + }, + "PCIE_BOT.PCIE_DBGVECA48->PCIE_LOGIC_OUTS_B20_R_12": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA48", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_12" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE4->PCIE_LOGIC_OUTS_B11_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLLTSSMSTATE4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_0" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTC->PCIE_LOGIC_OUTS_B17_L_17": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_17" + }, + "PCIE_BOT.PCIE_PIPETXDEEMPH->PCIE_LOGIC_OUTS_B0_R_8": { + "can_invert": "0", + "src_wire": "PCIE_PIPETXDEEMPH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_8" + }, + "PCIE_BOT.PCIE_PLSELLNKWIDTH0->PCIE_LOGIC_OUTS_B3_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLSELLNKWIDTH0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA5->PCIE_LOGIC_OUTS_B4_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_17" + }, + "PCIE_BOT.PCIE_TL2ERRHDR15->PCIE_LOGIC_OUTS_B8_R_8": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_8" + }, + "PCIE_BOT.PCIE_IMUX38_L_4->PCIE_PIPERX3STATUS1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3STATUS1" + }, + "PCIE_BOT.PCIE_IMUX1_R_0->PCIE_MIMTXRDATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA1" + }, + "PCIE_BOT.PCIE_MIMTXWDATA23->PCIE_LOGIC_OUTS_B20_R_8": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_8" + }, + "PCIE_BOT.PCIE_IMUX7_L_14->PCIE_CFGERRTLPCPLHEADER5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER5" + }, + "PCIE_BOT.PCIE_TL2ERRHDR17->PCIE_LOGIC_OUTS_B11_R_8": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_8" + }, + "PCIE_BOT.PCIE_IMUX37_R_6->PCIE_PIPERX7DATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA0" + }, + "PCIE_BOT.PCIE_IMUX6_R_11->PCIE_CFGMGMTDWADDR0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR0" + }, + "PCIE_BOT.PCIE_IMUX3_L_6->PCIE_TRNTD111": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD111" + }, + "PCIE_BOT.PCIE_IMUX1_L_4->PCIE_TRNTD101": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD101" + }, + "PCIE_BOT.PCIE_IMUX13_R_13->PCIE_CFGINTERRUPTDI5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI5" + }, + "PCIE_BOT.PCIE_DBGVECB0->PCIE_LOGIC_OUTS_B16_R_8": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_8" + }, + "PCIE_BOT.PCIE_TRNRD27->PCIE_LOGIC_OUTS_B0_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_12" + }, + "PCIE_BOT.PCIE_IMUX5_L_14->PCIE_CFGERRTLPCPLHEADER3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER3" + }, + "PCIE_BOT.PCIE_IMUX15_L_14->PCIE_CFGAERINTERRUPTMSGNUM3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM3" + }, + "PCIE_BOT.PCIE_IMUX14_R_5->PCIE_CFGERRAERHEADERLOG53": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG53" + }, + "PCIE_BOT.PCIE_IMUX17_R_10->PCIE_CFGDSDEVICENUMBER2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER2" + }, + "PCIE_BOT.PCIE_LNKCLKEN->PCIE_LOGIC_OUTS_B10_R_10": { + "can_invert": "0", + "src_wire": "PCIE_LNKCLKEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_10" + }, + "PCIE_BOT.PCIE_TRNFCPD8->PCIE_LOGIC_OUTS_B8_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_0" + }, + "PCIE_BOT.PCIE_IMUX5_L_1->PCIE_CFGERRAERHEADERLOG79": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG79" + }, + "PCIE_BOT.PCIE_IMUX38_L_5->PCIE_PIPERX3DATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA5" + }, + "PCIE_BOT.PCIE_PIPETX6DATA11->PCIE_LOGIC_OUTS_B15_R_12": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_12" + }, + "PCIE_BOT.PCIE_MIMTXWDATA42->PCIE_LOGIC_OUTS_B14_R_0": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA8->PCIE_LOGIC_OUTS_B6_L_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_14" + }, + "PCIE_BOT.PCIE_IMUX39_L_7->PCIE_PIPERX1DATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA12" + }, + "PCIE_BOT.PCIE_PLRXPMSTATE1->PCIE_LOGIC_OUTS_B1_L_1": { + "can_invert": "0", + "src_wire": "PCIE_PLRXPMSTATE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_1" + }, + "PCIE_BOT.PCIE_PIPETXRESET->PCIE_LOGIC_OUTS_B9_R_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETXRESET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_11" + }, + "PCIE_BOT.PCIE_IMUX2_R_1->PCIE_MIMTXRDATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA6" + }, + "PCIE_BOT.PCIE_PIPETX0DATA8->PCIE_LOGIC_OUTS_B9_L_16": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_16" + }, + "PCIE_BOT.PCIE_TL2ERRHDR14->PCIE_LOGIC_OUTS_B7_R_8": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_8" + }, + "PCIE_BOT.PCIE_IMUX4_L_16->PCIE_CFGERRTLPCPLHEADER10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER10" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLNONFATALREPORTINGEN->PCIE_LOGIC_OUTS_B21_L_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_12" + }, + "PCIE_BOT.PCIE_PIPETX3DATA3->PCIE_LOGIC_OUTS_B15_L_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_3" + }, + "PCIE_BOT.PCIE_DBGVECB60->PCIE_LOGIC_OUTS_B19_L_6": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_6" + }, + "PCIE_BOT.PCIE_MIMTXRADDR1->PCIE_LOGIC_OUTS_B11_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_6" + }, + "PCIE_BOT.PCIE_IMUX37_L_8->PCIE_PIPERX1DATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA8" + }, + "PCIE_BOT.PCIE_MIMTXWDATA45->PCIE_LOGIC_OUTS_B17_R_3": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_3" + }, + "PCIE_BOT.PCIE_TRNRD17->PCIE_LOGIC_OUTS_B2_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_9" + }, + "PCIE_BOT.PCIE_IMUX4_R_15->PCIE_TRNTD54": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD54" + }, + "PCIE_BOT.PCIE_IMUX9_R_6->PCIE_CFGMGMTDI15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI15" + }, + "PCIE_BOT.PCIE_IMUX11_R_16->PCIE_CFGERRPOISONEDN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRPOISONEDN" + }, + "PCIE_BOT.PCIE_IMUX8_R_10->PCIE_CFGMGMTBYTEENN2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTBYTEENN2" + }, + "PCIE_BOT.PCIE_MIMRXWDATA41->PCIE_LOGIC_OUTS_B18_R_18": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_18" + }, + "PCIE_BOT.PCIE_IMUX12_L_3->PCIE_CFGSUBSYSID0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR30->PCIE_LOGIC_OUTS_B13_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_4" + }, + "PCIE_BOT.PCIE_IMUX38_R_5->PCIE_PIPERX7DATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA5" + }, + "PCIE_BOT.PCIE_PIPETX7DATA15->PCIE_LOGIC_OUTS_B6_R_0": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_0" + }, + "PCIE_BOT.PCIE_TRNRD0->PCIE_LOGIC_OUTS_B1_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_5" + }, + "PCIE_BOT.PCIE_IMUX11_L_18->PCIE_CFGDSN52": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN52" + }, + "PCIE_BOT.PCIE_IMUX35_L_15->PCIE_PIPERX2STATUS2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2STATUS2" + }, + "PCIE_BOT.PCIE_PIPERX6POLARITY->PCIE_LOGIC_OUTS_B1_R_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPERX6POLARITY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_14" + }, + "PCIE_BOT.PCIE_IMUX0_L_8->PCIE_TRNTD116": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD116" + }, + "PCIE_BOT.PCIE_CTRL1_R_2->PCIE_DLRSTN": { + "can_invert": "0", + "src_wire": "PCIE_CTRL1_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DLRSTN" + }, + "PCIE_BOT.PCIE_MIMTXWDATA12->PCIE_LOGIC_OUTS_B10_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_6" + }, + "PCIE_BOT.PCIE_IMUX12_R_1->PCIE_CFGERRAERHEADERLOG66": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG66" + }, + "PCIE_BOT.PCIE_PIPETX0DATA7->PCIE_LOGIC_OUTS_B6_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_17" + }, + "PCIE_BOT.PCIE_PLRXPMSTATE0->PCIE_LOGIC_OUTS_B0_L_1": { + "can_invert": "0", + "src_wire": "PCIE_PLRXPMSTATE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_1" + }, + "PCIE_BOT.PCIE_IMUX3_L_9->PCIE_TRNTD123": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD123" + }, + "PCIE_BOT.PCIE_IMUX16_R_6->PCIE_PIPERX7CHARISK0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7CHARISK0" + }, + "PCIE_BOT.PCIE_IMUX0_R_4->PCIE_MIMTXRDATA16": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA16" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE2->PCIE_LOGIC_OUTS_B9_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLLTSSMSTATE2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA17->PCIE_LOGIC_OUTS_B5_L_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_16" + }, + "PCIE_BOT.PCIE_TRNFCCPLD9->PCIE_LOGIC_OUTS_B8_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_11" + }, + "PCIE_BOT.PCIE_IMUX14_L_7->PCIE_CFGSUBSYSID12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID12" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTRDYN->PCIE_LOGIC_OUTS_B15_R_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTRDYN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_10" + }, + "PCIE_BOT.PCIE_PIPETX4DATA6->PCIE_LOGIC_OUTS_B2_R_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_17" + }, + "PCIE_BOT.PCIE_TRNRD42->PCIE_LOGIC_OUTS_B7_L_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_15" + }, + "PCIE_BOT.PCIE_IMUX3_R_1->PCIE_MIMTXRDATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA7" + }, + "PCIE_BOT.PCIE_IMUX2_R_4->PCIE_MIMTXRDATA18": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA18" + }, + "PCIE_BOT.PCIE_IMUX3_R_0->PCIE_MIMTXRDATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA3" + }, + "PCIE_BOT.PCIE_TL2ERRHDR39->PCIE_LOGIC_OUTS_B12_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_7" + }, + "PCIE_BOT.PCIE_PIPETX5DATA1->PCIE_LOGIC_OUTS_B13_R_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_7" + }, + "PCIE_BOT.PCIE_TRNTBUFAV4->PCIE_LOGIC_OUTS_B5_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TRNTBUFAV4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_4" + }, + "PCIE_BOT.PCIE_DBGVECA44->PCIE_LOGIC_OUTS_B20_R_13": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_13" + }, + "PCIE_BOT.PCIE_PIPERX1POLARITY->PCIE_LOGIC_OUTS_B1_L_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPERX1POLARITY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_7" + }, + "PCIE_BOT.PCIE_IMUX6_L_10->PCIE_CFGERRAERHEADERLOG116": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG116" + }, + "PCIE_BOT.PCIE_PIPETX0CHARISK0->PCIE_LOGIC_OUTS_B16_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0CHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_17" + }, + "PCIE_BOT.PCIE_IMUX7_R_16->PCIE_TRNTD53": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD53" + }, + "PCIE_BOT.PCIE_IMUX10_R_5->PCIE_CFGMGMTDI14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI14" + }, + "PCIE_BOT.PCIE_DBGVECB58->PCIE_LOGIC_OUTS_B21_L_5": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB58", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_5" + }, + "PCIE_BOT.PCIE_IMUX0_R_14->PCIE_TRNTD58": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD58" + }, + "PCIE_BOT.PCIE_IMUX7_R_2->PCIE_MIMTXRDATA57": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA57" + }, + "PCIE_BOT.PCIE_DBGVECB11->PCIE_LOGIC_OUTS_B18_R_8": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_8" + }, + "PCIE_BOT.PCIE_IMUX10_R_10->PCIE_CFGERRAERHEADERLOG31": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG31" + }, + "PCIE_BOT.PCIE_DBGVECB43->PCIE_LOGIC_OUTS_B18_L_2": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_2" + }, + "PCIE_BOT.PCIE_IMUX12_L_10->PCIE_CFGSUBSYSVENDID0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID0" + }, + "PCIE_BOT.PCIE_IMUX39_L_4->PCIE_PIPERX3STATUS0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3STATUS0" + }, + "PCIE_BOT.PCIE_IMUX1_L_7->PCIE_TRNTD113": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD113" + }, + "PCIE_BOT.PCIE_IMUX36_L_8->PCIE_PIPERX1DATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA9" + }, + "PCIE_BOT.PCIE_IMUX15_R_3->PCIE_CFGERRAERHEADERLOG60": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG60" + }, + "PCIE_BOT.PCIE_TRNRD50->PCIE_LOGIC_OUTS_B10_L_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_17" + }, + "PCIE_BOT.PCIE_IMUX1_L_5->PCIE_TRNTD105": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD105" + }, + "PCIE_BOT.PCIE_IMUX2_R_15->PCIE_MIMRXRDATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA2" + }, + "PCIE_BOT.PCIE_IMUX37_R_5->PCIE_PIPERX7PHYSTATUS": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7PHYSTATUS" + }, + "PCIE_BOT.PCIE_PIPETX5DATA7->PCIE_LOGIC_OUTS_B6_R_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_6" + }, + "PCIE_BOT.PCIE_IMUX9_L_14->PCIE_CFGDSN34": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN34" + }, + "PCIE_BOT.PCIE_IMUX1_R_3->PCIE_MIMTXRDATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA13" + }, + "PCIE_BOT.PCIE_PLPHYLNKUPN->PCIE_LOGIC_OUTS_B15_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLPHYLNKUPN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_0" + }, + "PCIE_BOT.PCIE_IMUX13_R_2->PCIE_CFGMGMTDI0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI0" + }, + "PCIE_BOT.PCIE_IMUX35_R_9->PCIE_PIPERX5DATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA6" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1->PCIE_LOGIC_OUTS_B18_L_18": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_18" + }, + "PCIE_BOT.PCIE_IMUX7_L_0->PCIE_PLDOWNSTREAMDEEMPHSOURCE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDOWNSTREAMDEEMPHSOURCE" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTD->PCIE_LOGIC_OUTS_B19_L_17": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_17" + }, + "PCIE_BOT.PCIE_IMUX6_R_13->PCIE_CFGMGMTDWADDR8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR8" + }, + "PCIE_BOT.PCIE_IMUX11_L_0->PCIE_PLDIRECTEDLTSSMNEW2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW2" + }, + "PCIE_BOT.PCIE_IMUX3_R_6->PCIE_MIMTXRDATA27": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA27" + }, + "PCIE_BOT.PCIE_TRNTCFGREQ->PCIE_LOGIC_OUTS_B0_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNTCFGREQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_5" + }, + "PCIE_BOT.PCIE_MIMRXRADDR6->PCIE_LOGIC_OUTS_B9_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXRADDR6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_19" + }, + "PCIE_BOT.PCIE_IMUX11_R_13->PCIE_CFGERRAERHEADERLOG20": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG20" + }, + "PCIE_BOT.PCIE_DBGVECB8->PCIE_LOGIC_OUTS_B22_R_15": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_15" + }, + "PCIE_BOT.PCIE_IMUX39_L_15->PCIE_PIPERX2STATUS0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2STATUS0" + }, + "PCIE_BOT.PCIE_IMUX1_L_9->PCIE_TRNTD121": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD121" + }, + "PCIE_BOT.PCIE_IMUX7_L_3->PCIE_CFGERRAERHEADERLOG89": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG89" + }, + "PCIE_BOT.PCIE_IMUX0_L_9->PCIE_TRNTD120": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD120" + }, + "PCIE_BOT.PCIE_IMUX9_R_12->PCIE_CFGERRAERHEADERLOG22": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG22" + }, + "PCIE_BOT.PCIE_PIPETX3DATA14->PCIE_LOGIC_OUTS_B2_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_0" + }, + "PCIE_BOT.PCIE_IMUX10_R_15->PCIE_CFGERRURN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRURN" + }, + "PCIE_BOT.PCIE_IMUX3_L_19->PCIE_TRNTDLLPDATA18": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA18" + }, + "PCIE_BOT.PCIE_IMUX13_R_16->PCIE_CFGERRAERHEADERLOG12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG12" + }, + "PCIE_BOT.PCIE_MIMRXWDATA61->PCIE_LOGIC_OUTS_B12_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_19" + }, + "PCIE_BOT.PCIE_DBGVECB61->PCIE_LOGIC_OUTS_B20_L_6": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_6" + }, + "PCIE_BOT.PCIE_IMUX4_R_0->PCIE_MIMTXRDATA62": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA62" + }, + "PCIE_BOT.PCIE_MIMTXWDATA21->PCIE_LOGIC_OUTS_B5_R_8": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_8" + }, + "PCIE_BOT.PCIE_IMUX3_L_18->PCIE_TRNTDLLPDATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA14" + }, + "PCIE_BOT.PCIE_MIMTXWDATA53->PCIE_LOGIC_OUTS_B19_R_2": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_2" + }, + "PCIE_BOT.PCIE_IMUX6_L_0->PCIE_PLUPSTREAMPREFERDEEMPH": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLUPSTREAMPREFERDEEMPH" + }, + "PCIE_BOT.PCIE_IMUX9_L_13->PCIE_CFGDSN30": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN30" + }, + "PCIE_BOT.PCIE_IMUX5_L_19->PCIE_CFGERRTLPCPLHEADER23": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER23" + }, + "PCIE_BOT.PCIE_MIMTXWDATA5->PCIE_LOGIC_OUTS_B4_R_9": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_9" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLENABLERO->PCIE_LOGIC_OUTS_B18_L_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLENABLERO", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_14" + }, + "PCIE_BOT.PCIE_DBGVECA22->PCIE_LOGIC_OUTS_B21_R_19": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_19" + }, + "PCIE_BOT.PCIE_IMUX32_R_17->PCIE_PIPERX6DATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA3" + }, + "PCIE_BOT.PCIE_IMUX0_R_5->PCIE_MIMTXRDATA20": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA20" + }, + "PCIE_BOT.PCIE_IMUX13_L_10->PCIE_CFGSUBSYSVENDID1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID1" + }, + "PCIE_BOT.PCIE_MIMRXWDATA48->PCIE_LOGIC_OUTS_B16_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA48", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_16" + }, + "PCIE_BOT.PCIE_IMUX7_L_18->PCIE_CFGERRTLPCPLHEADER21": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER21" + }, + "PCIE_BOT.PCIE_DBGVECB49->PCIE_LOGIC_OUTS_B20_L_3": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB49", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_3" + }, + "PCIE_BOT.PCIE_TL2ERRHDR55->PCIE_LOGIC_OUTS_B12_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_11" + }, + "PCIE_BOT.PCIE_IMUX36_R_5->PCIE_PIPERX7VALID": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7VALID" + }, + "PCIE_BOT.PCIE_PIPETX1DATA4->PCIE_LOGIC_OUTS_B0_L_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_6" + }, + "PCIE_BOT.PCIE_IMUX4_L_8->PCIE_CFGERRAERHEADERLOG106": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG106" + }, + "PCIE_BOT.PCIE_IMUX32_L_17->PCIE_PIPERX2DATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA3" + }, + "PCIE_BOT.PCIE_PIPETX7DATA13->PCIE_LOGIC_OUTS_B4_R_0": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_0" + }, + "PCIE_BOT.PCIE_IMUX13_L_7->PCIE_CFGSUBSYSID11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID11" + }, + "PCIE_BOT.PCIE_PIPETX4COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4COMPLIANCE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_18" + }, + "PCIE_BOT.PCIE_PL2RXPMSTATE1->PCIE_LOGIC_OUTS_B19_R_19": { + "can_invert": "0", + "src_wire": "PCIE_PL2RXPMSTATE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_19" + }, + "PCIE_BOT.PCIE_IMUX8_R_0->PCIE_TRNTD87": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD87" + }, + "PCIE_BOT.PCIE_CFGDEVSTATUSFATALERRDETECTED->PCIE_LOGIC_OUTS_B16_L_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVSTATUSFATALERRDETECTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_10" + }, + "PCIE_BOT.PCIE_IMUX36_L_5->PCIE_PIPERX3VALID": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3VALID" + }, + "PCIE_BOT.PCIE_CFGMSGDATA7->PCIE_LOGIC_OUTS_B17_L_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_12" + }, + "PCIE_BOT.PCIE_IMUX5_R_8->PCIE_CFGMGMTDI23": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI23" + }, + "PCIE_BOT.PCIE_IMUX15_R_11->PCIE_CFGDSBUSNUMBER5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER5" + }, + "PCIE_BOT.PCIE_PIPETX2DATA1->PCIE_LOGIC_OUTS_B13_L_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_14" + }, + "PCIE_BOT.PCIE_TRNFCNPH1->PCIE_LOGIC_OUTS_B11_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPH1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_2" + }, + "PCIE_BOT.PCIE_IMUX36_L_17->PCIE_PIPERX2DATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA1" + }, + "PCIE_BOT.PCIE_IMUX34_L_16->PCIE_PIPERX2DATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA7" + }, + "PCIE_BOT.PCIE_IMUX0_L_2->PCIE_TRNTD92": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD92" + }, + "PCIE_BOT.PCIE_TRNRD115->PCIE_LOGIC_OUTS_B8_R_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD115", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_15" + }, + "PCIE_BOT.PCIE_PIPETX4DATA13->PCIE_LOGIC_OUTS_B4_R_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_15" + }, + "PCIE_BOT.PCIE_IMUX10_L_9->PCIE_CFGDSN15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN15" + }, + "PCIE_BOT.PCIE_IMUX13_L_1->PCIE_CFGREVID1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID1" + }, + "PCIE_BOT.PCIE_LL2TXIDLE->PCIE_LOGIC_OUTS_B13_R_17": { + "can_invert": "0", + "src_wire": "PCIE_LL2TXIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_17" + }, + "PCIE_BOT.PCIE_PIPETX1DATA7->PCIE_LOGIC_OUTS_B6_L_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_6" + }, + "PCIE_BOT.PCIE_IMUX34_R_3->PCIE_PIPERX7DATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA15" + }, + "PCIE_BOT.PCIE_IMUX14_R_11->PCIE_CFGDSBUSNUMBER4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER4" + }, + "PCIE_BOT.PCIE_IMUX2_R_12->PCIE_TRNTD68": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD68" + }, + "PCIE_BOT.PCIE_IMUX12_R_16->PCIE_CFGERRACSN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRACSN" + }, + "PCIE_BOT.PCIE_IMUX5_R_5->PCIE_MIMTXRDATA49": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA49" + }, + "PCIE_BOT.PCIE_IMUX34_R_8->PCIE_PIPERX5ELECIDLE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5ELECIDLE" + }, + "PCIE_BOT.PCIE_MIMTXWDATA62->PCIE_LOGIC_OUTS_B5_R_1": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_1" + }, + "PCIE_BOT.PCIE_IMUX4_L_1->PCIE_CFGERRAERHEADERLOG78": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG78" + }, + "PCIE_BOT.PCIE_PIPETX2DATA3->PCIE_LOGIC_OUTS_B15_L_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_14" + }, + "PCIE_BOT.PCIE_MIMTXWDATA66->PCIE_LOGIC_OUTS_B18_R_2": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA66", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_2" + }, + "PCIE_BOT.PCIE_IMUX39_R_3->PCIE_PIPERX7DATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA12" + }, + "PCIE_BOT.PCIE_TRNRD126->PCIE_LOGIC_OUTS_B2_R_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD126", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_12" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETOACK->PCIE_LOGIC_OUTS_B16_L_18": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDPMETOACK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_18" + }, + "PCIE_BOT.PCIE_IMUX7_R_15->PCIE_TRNTD57": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD57" + }, + "PCIE_BOT.PCIE_IMUX16_R_15->PCIE_PIPERX6CHARISK1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6CHARISK1" + }, + "PCIE_BOT.PCIE_IMUX5_R_13->PCIE_CFGMGMTDWADDR7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR7" + }, + "PCIE_BOT.PCIE_IMUX1_L_8->PCIE_TRNTD117": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD117" + }, + "PCIE_BOT.PCIE_IMUX39_R_15->PCIE_PIPERX6STATUS0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6STATUS0" + }, + "PCIE_BOT.PCIE_IMUX18_R_0->PCIE_CFGPORTNUMBER2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX18_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER2" + }, + "PCIE_BOT.PCIE_IMUX36_R_4->PCIE_PIPERX7DATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA9" + }, + "PCIE_BOT.PCIE_IMUX3_L_15->PCIE_TRNTDLLPDATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA2" + }, + "PCIE_BOT.PCIE_DBGVECA31->PCIE_LOGIC_OUTS_B22_R_17": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_17" + }, + "PCIE_BOT.PCIE_DBGVECA32->PCIE_LOGIC_OUTS_B2_R_16": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_16" + }, + "PCIE_BOT.PCIE_PIPETX3DATA0->PCIE_LOGIC_OUTS_B9_L_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_3" + }, + "PCIE_BOT.PCIE_TRNFCCPLH2->PCIE_LOGIC_OUTS_B7_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLH2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_7" + }, + "PCIE_BOT.PCIE_IMUX3_L_16->PCIE_TRNTDLLPDATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA6" + }, + "PCIE_BOT.PCIE_TRNTBUFAV1->PCIE_LOGIC_OUTS_B5_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TRNTBUFAV1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_3" + }, + "PCIE_BOT.PCIE_DBGVECB44->PCIE_LOGIC_OUTS_B19_L_2": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_2" + }, + "PCIE_BOT.PCIE_CFGMGMTDO1->PCIE_LOGIC_OUTS_B12_R_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_10" + }, + "PCIE_BOT.PCIE_CTRL0_R_3->PCIE_PLRSTN": { + "can_invert": "0", + "src_wire": "PCIE_CTRL0_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLRSTN" + }, + "PCIE_BOT.PCIE_IMUX1_L_1->PCIE_PLDIRECTEDLTSSMNEW5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW5" + }, + "PCIE_BOT.PCIE_PLDBGVEC0->PCIE_LOGIC_OUTS_B22_L_14": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_14" + }, + "PCIE_BOT.PCIE_IMUX3_L_7->PCIE_TRNTD115": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD115" + }, + "PCIE_BOT.PCIE_PLINITIALLINKWIDTH1->PCIE_LOGIC_OUTS_B9_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PLINITIALLINKWIDTH1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_2" + }, + "PCIE_BOT.PCIE_PIPETX4DATA11->PCIE_LOGIC_OUTS_B15_R_16": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_16" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA0->PCIE_LOGIC_OUTS_B4_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_12" + }, + "PCIE_BOT.PCIE_DBGVECA61->PCIE_LOGIC_OUTS_B21_R_9": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_9" + }, + "PCIE_BOT.PCIE_TRNRD37->PCIE_LOGIC_OUTS_B4_L_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_14" + }, + "PCIE_BOT.PCIE_PIPETX1DATA11->PCIE_LOGIC_OUTS_B15_L_5": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_5" + }, + "PCIE_BOT.PCIE_IMUX34_L_3->PCIE_PIPERX3DATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA15" + }, + "PCIE_BOT.PCIE_DBGVECB12->PCIE_LOGIC_OUTS_B10_R_7": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_7" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO2->PCIE_LOGIC_OUTS_B13_L_8": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_8" + }, + "PCIE_BOT.PCIE_PIPETX4POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4POWERDOWN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_17" + }, + "PCIE_BOT.PCIE_IMUX2_L_19->PCIE_TRNTDLLPDATA17": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA17" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRCOR->PCIE_LOGIC_OUTS_B14_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDERRCOR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_15" + }, + "PCIE_BOT.PCIE_IMUX4_R_5->PCIE_MIMTXRDATA48": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA48" + }, + "PCIE_BOT.PCIE_IMUX9_L_15->PCIE_CFGDSN38": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN38" + }, + "PCIE_BOT.PCIE_IMUX11_R_3->PCIE_CFGMGMTDI5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI5" + }, + "PCIE_BOT.PCIE_PIPETX6POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6POWERDOWN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_13" + }, + "PCIE_BOT.PCIE_DBGVECA43->PCIE_LOGIC_OUTS_B19_R_13": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_13" + }, + "PCIE_BOT.PCIE_DBGVECB25->PCIE_LOGIC_OUTS_B19_R_4": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_4" + }, + "PCIE_BOT.PCIE_IMUX3_L_17->PCIE_TRNTDLLPDATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA10" + }, + "PCIE_BOT.PCIE_IMUX1_R_13->PCIE_TRNTD63": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD63" + }, + "PCIE_BOT.PCIE_DBGVECB14->PCIE_LOGIC_OUTS_B17_R_7": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_7" + }, + "PCIE_BOT.PCIE_CFGMSGDATA12->PCIE_LOGIC_OUTS_B16_L_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_14" + }, + "PCIE_BOT.PCIE_PIPETX3DATA8->PCIE_LOGIC_OUTS_B9_L_1": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_1" + }, + "PCIE_BOT.PCIE_IMUX16_L_10->PCIE_PIPERX1CHARISK0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1CHARISK0" + }, + "PCIE_BOT.PCIE_IMUX6_L_11->PCIE_CFGERRAERHEADERLOG120": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG120" + }, + "PCIE_BOT.PCIE_IMUX9_R_0->PCIE_TRNTD88": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD88" + }, + "PCIE_BOT.PCIE_IMUX0_L_0->PCIE_PLDIRECTEDLINKCHANGE0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKCHANGE0" + }, + "PCIE_BOT.PCIE_TRNRD102->PCIE_LOGIC_OUTS_B6_R_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD102", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_19" + }, + "PCIE_BOT.PCIE_IMUX5_R_1->PCIE_MIMTXRDATA59": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA59" + }, + "PCIE_BOT.PCIE_MIMTXRADDR11->PCIE_LOGIC_OUTS_B8_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_5" + }, + "PCIE_BOT.PCIE_IMUX33_R_4->PCIE_PIPERX7DATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA10" + }, + "PCIE_BOT.PCIE_IMUX34_L_8->PCIE_PIPERX1ELECIDLE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1ELECIDLE" + }, + "PCIE_BOT.PCIE_MIMTXWDATA67->PCIE_LOGIC_OUTS_B14_R_2": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA67", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_2" + }, + "PCIE_BOT.PCIE_MIMTXRADDR4->PCIE_LOGIC_OUTS_B14_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_4" + }, + "PCIE_BOT.PCIE_TRNFCPH5->PCIE_LOGIC_OUTS_B5_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPH5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_4" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA20->PCIE_LOGIC_OUTS_B11_L_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_17" + }, + "PCIE_BOT.PCIE_IMUX37_L_17->PCIE_PIPERX2DATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA0" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA31->PCIE_LOGIC_OUTS_B7_L_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_19" + }, + "PCIE_BOT.PCIE_IMUX35_L_4->PCIE_PIPERX3STATUS2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3STATUS2" + }, + "PCIE_BOT.PCIE_DBGVECB59->PCIE_LOGIC_OUTS_B18_L_6": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB59", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_6" + }, + "PCIE_BOT.PCIE_TL2ERRHDR35->PCIE_LOGIC_OUTS_B12_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_5" + }, + "PCIE_BOT.PCIE_IMUX32_L_8->PCIE_PIPERX1DATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA11" + }, + "PCIE_BOT.PCIE_IMUX7_R_5->PCIE_CFGMGMTDI11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI11" + }, + "PCIE_BOT.PCIE_TL2ERRHDR8->PCIE_LOGIC_OUTS_B8_R_10": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_10" + }, + "PCIE_BOT.PCIE_IMUX13_L_18->PCIE_DRPADDR4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR4" + }, + "PCIE_BOT.PCIE_IMUX32_R_6->PCIE_PIPERX7DATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA3" + }, + "PCIE_BOT.PCIE_MIMTXWDATA16->PCIE_LOGIC_OUTS_B1_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_4" + }, + "PCIE_BOT.PCIE_IMUX7_L_6->PCIE_CFGERRAERHEADERLOG101": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG101" + }, + "PCIE_BOT.PCIE_TL2ERRHDR26->PCIE_LOGIC_OUTS_B14_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_3" + }, + "PCIE_BOT.PCIE_IMUX37_R_10->PCIE_PIPERX5DATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA0" + }, + "PCIE_BOT.PCIE_TRNRD41->PCIE_LOGIC_OUTS_B5_L_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_15" + }, + "PCIE_BOT.PCIE_MIMTXWDATA63->PCIE_LOGIC_OUTS_B10_R_3": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_3" + }, + "PCIE_BOT.PCIE_TRNFCCPLH0->PCIE_LOGIC_OUTS_B14_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLH0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_6" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE3->PCIE_LOGIC_OUTS_B10_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLLTSSMSTATE3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_0" + }, + "PCIE_BOT.PCIE_PIPETX3DATA12->PCIE_LOGIC_OUTS_B0_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_0" + }, + "PCIE_BOT.PCIE_IMUX15_R_2->PCIE_CFGMGMTDI2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI2" + }, + "PCIE_BOT.PCIE_DBGVECA25->PCIE_LOGIC_OUTS_B7_R_18": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_18" + }, + "PCIE_BOT.PCIE_TL2ERRHDR36->PCIE_LOGIC_OUTS_B14_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_5" + }, + "PCIE_BOT.PCIE_MIMTXWDATA47->PCIE_LOGIC_OUTS_B18_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_4" + }, + "PCIE_BOT.PCIE_IMUX9_R_13->PCIE_CFGERRAERHEADERLOG18": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG18" + }, + "PCIE_BOT.PCIE_PIPETX5DATA13->PCIE_LOGIC_OUTS_B4_R_4": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_4" + }, + "PCIE_BOT.PCIE_IMUX39_R_5->PCIE_PIPERX7DATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA4" + }, + "PCIE_BOT.PCIE_IMUX11_L_16->PCIE_CFGDSN44": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN44" + }, + "PCIE_BOT.PCIE_PIPETX5DATA2->PCIE_LOGIC_OUTS_B11_R_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_7" + }, + "PCIE_BOT.PCIE_IMUX13_R_10->PCIE_CFGDSBUSNUMBER7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER7" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA14->PCIE_LOGIC_OUTS_B10_L_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_15" + }, + "PCIE_BOT.PCIE_CFGMSGDATA6->PCIE_LOGIC_OUTS_B16_L_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_12" + }, + "PCIE_BOT.PCIE_IMUX39_R_19->PCIE_PIPERX4STATUS0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4STATUS0" + }, + "PCIE_BOT.PCIE_IMUX3_R_17->PCIE_MIMRXRDATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA11" + }, + "PCIE_BOT.PCIE_IMUX11_L_1->PCIE_CFGPMFORCESTATE0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMFORCESTATE0" + }, + "PCIE_BOT.PCIE_TRNFCNPH5->PCIE_LOGIC_OUTS_B6_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPH5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_3" + }, + "PCIE_BOT.PCIE_IMUX3_R_19->PCIE_MIMRXRDATA19": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA19" + }, + "PCIE_BOT.PCIE_MIMRXWADDR6->PCIE_LOGIC_OUTS_B17_R_17": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWADDR6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_17" + }, + "PCIE_BOT.PCIE_MIMTXWADDR11->PCIE_LOGIC_OUTS_B2_R_3": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_3" + }, + "PCIE_BOT.PCIE_IMUX35_L_14->PCIE_PIPERX2DATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA14" + }, + "PCIE_BOT.PCIE_IMUX9_R_2->PCIE_TRNTD80": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD80" + }, + "PCIE_BOT.PCIE_IMUX35_L_16->PCIE_PIPERX2DATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA6" + }, + "PCIE_BOT.PCIE_PIPETX3DATA13->PCIE_LOGIC_OUTS_B4_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_0" + }, + "PCIE_BOT.PCIE_DBGVECB36->PCIE_LOGIC_OUTS_B20_L_0": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA4->PCIE_LOGIC_OUTS_B5_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_5" + }, + "PCIE_BOT.PCIE_IMUX8_L_19->PCIE_CFGDSN53": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN53" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRFATAL->PCIE_LOGIC_OUTS_B8_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDERRFATAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_16" + }, + "PCIE_BOT.PCIE_IMUX16_R_2->PCIE_CFGERRAERHEADERLOG62": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG62" + }, + "PCIE_BOT.PCIE_IMUX13_L_13->PCIE_CFGSUBSYSVENDID13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID13" + }, + "PCIE_BOT.PCIE_IMUX35_L_19->PCIE_PIPERX0STATUS2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0STATUS2" + }, + "PCIE_BOT.PCIE_IMUX16_R_11->PCIE_CFGDSBUSNUMBER6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER6" + }, + "PCIE_BOT.PCIE_IMUX11_R_19->PCIE_TRNTD7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD7" + }, + "PCIE_BOT.PCIE_IMUX1_L_3->PCIE_TRNTD97": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD97" + }, + "PCIE_BOT.PCIE_IMUX38_L_14->PCIE_PIPERX2DATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA13" + }, + "PCIE_BOT.PCIE_TRNRD127->PCIE_LOGIC_OUTS_B3_R_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD127", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_12" + }, + "PCIE_BOT.PCIE_IMUX14_R_0->PCIE_CFGERRAERHEADERLOG72": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG72" + }, + "PCIE_BOT.PCIE_IMUX1_L_6->PCIE_TRNTD109": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD109" + }, + "PCIE_BOT.PCIE_IMUX4_L_17->PCIE_CFGERRTLPCPLHEADER14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER14" + }, + "PCIE_BOT.PCIE_PIPETX0CHARISK1->PCIE_LOGIC_OUTS_B16_L_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0CHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_15" + }, + "PCIE_BOT.PCIE_DBGSCLRA->PCIE_LOGIC_OUTS_B19_L_10": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRA", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_10" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTB->PCIE_LOGIC_OUTS_B14_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_16" + }, + "PCIE_BOT.PCIE_IMUX34_R_19->PCIE_PIPERX4ELECIDLE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4ELECIDLE" + }, + "PCIE_BOT.PCIE_PLDBGVEC6->PCIE_LOGIC_OUTS_B23_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_17" + }, + "PCIE_BOT.PCIE_DBGVECA51->PCIE_LOGIC_OUTS_B18_R_11": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_11" + }, + "PCIE_BOT.PCIE_TRNRD53->PCIE_LOGIC_OUTS_B4_L_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_18" + }, + "PCIE_BOT.PCIE_IMUX8_R_1->PCIE_TRNTD83": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD83" + }, + "PCIE_BOT.PCIE_IMUX0_L_16->PCIE_TRNTDLLPDATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA3" + }, + "PCIE_BOT.PCIE_TL2ERRHDR62->PCIE_LOGIC_OUTS_B14_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_12" + }, + "PCIE_BOT.PCIE_PIPETX4DATA4->PCIE_LOGIC_OUTS_B0_R_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_17" + }, + "PCIE_BOT.PCIE_IMUX38_L_9->PCIE_PIPERX1DATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA5" + }, + "PCIE_BOT.PCIE_IMUX0_L_5->PCIE_TRNTD104": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD104" + }, + "PCIE_BOT.PCIE_IMUX19_R_1->PCIE_CFGDSFUNCTIONNUMBER2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX19_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSFUNCTIONNUMBER2" + }, + "PCIE_BOT.PCIE_IMUX0_R_10->PCIE_TRNTD74": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD74" + }, + "PCIE_BOT.PCIE_IMUX3_R_2->PCIE_MIMTXRDATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA11" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA19->PCIE_LOGIC_OUTS_B7_L_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_16" + }, + "PCIE_BOT.PCIE_TRNFCPH2->PCIE_LOGIC_OUTS_B2_R_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPH2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_5" + }, + "PCIE_BOT.PCIE_IMUX20_R_13->PCIE_CFGVENDID5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID5" + }, + "PCIE_BOT.PCIE_CFGMSGDATA10->PCIE_LOGIC_OUTS_B12_L_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_14" + }, + "PCIE_BOT.PCIE_MIMTXWDATA51->PCIE_LOGIC_OUTS_B14_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_5" + }, + "PCIE_BOT.PCIE_PIPETX0DATA1->PCIE_LOGIC_OUTS_B13_L_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_18" + }, + "PCIE_BOT.PCIE_TRNFCNPD8->PCIE_LOGIC_OUTS_B7_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_5" + }, + "PCIE_BOT.PCIE_IMUX10_L_17->PCIE_CFGDSN47": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN47" + }, + "PCIE_BOT.PCIE_DBGVECB39->PCIE_LOGIC_OUTS_B18_L_1": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_1" + }, + "PCIE_BOT.PCIE_IMUX6_L_17->PCIE_CFGERRTLPCPLHEADER16": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER16" + }, + "PCIE_BOT.PCIE_IMUX11_L_8->PCIE_CFGDSN12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN12" + }, + "PCIE_BOT.PCIE_IMUX4_R_3->PCIE_MIMTXRDATA50": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA50" + }, + "PCIE_BOT.PCIE_CFGAERECRCGENEN->PCIE_LOGIC_OUTS_B18_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGAERECRCGENEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_19" + }, + "PCIE_BOT.PCIE_CFGMGMTDO4->PCIE_LOGIC_OUTS_B14_R_11": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_11" + }, + "PCIE_BOT.PCIE_IMUX14_L_18->PCIE_DRPADDR5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR5" + }, + "PCIE_BOT.PCIE_TL2ERRHDR27->PCIE_LOGIC_OUTS_B16_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_3" + }, + "PCIE_BOT.PCIE_MIMTXWDATA46->PCIE_LOGIC_OUTS_B19_R_1": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_1" + }, + "PCIE_BOT.PCIE_LL2SUSPENDOK->PCIE_LOGIC_OUTS_B12_R_17": { + "can_invert": "0", + "src_wire": "PCIE_LL2SUSPENDOK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_17" + }, + "PCIE_BOT.PCIE_IMUX6_L_9->PCIE_CFGERRAERHEADERLOG112": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG112" + }, + "PCIE_BOT.PCIE_PIPETX7DATA4->PCIE_LOGIC_OUTS_B0_R_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_2" + }, + "PCIE_BOT.PCIE_IMUX10_R_1->PCIE_TRNTD85": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD85" + }, + "PCIE_BOT.PCIE_TRNRD117->PCIE_LOGIC_OUTS_B2_R_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD117", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_14" + }, + "PCIE_BOT.PCIE_TL2ERRHDR19->PCIE_LOGIC_OUTS_B8_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_1" + }, + "PCIE_BOT.PCIE_PIPETX6DATA9->PCIE_LOGIC_OUTS_B13_R_12": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_12" + }, + "PCIE_BOT.PCIE_IMUX3_L_14->PCIE_TRNFCSEL1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNFCSEL1" + }, + "PCIE_BOT.PCIE_TRNRD18->PCIE_LOGIC_OUTS_B3_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_9" + }, + "PCIE_BOT.PCIE_TRNRD22->PCIE_LOGIC_OUTS_B3_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_10" + }, + "PCIE_BOT.PCIE_IMUX9_R_11->PCIE_CFGERRAERHEADERLOG26": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG26" + }, + "PCIE_BOT.PCIE_MIMTXWDATA50->PCIE_LOGIC_OUTS_B7_R_1": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_1" + }, + "PCIE_BOT.PCIE_IMUX10_L_11->PCIE_CFGDSN23": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN23" + }, + "PCIE_BOT.PCIE_TRNFCCPLD3->PCIE_LOGIC_OUTS_B6_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_9" + }, + "PCIE_BOT.PCIE_TL2ERRHDR63->PCIE_LOGIC_OUTS_B15_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_13" + }, + "PCIE_BOT.PCIE_PIPETX2DATA5->PCIE_LOGIC_OUTS_B4_L_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_13" + }, + "PCIE_BOT.PCIE_PIPETX0DATA11->PCIE_LOGIC_OUTS_B15_L_16": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_16" + }, + "PCIE_BOT.PCIE_IMUX6_L_2->PCIE_CFGERRAERHEADERLOG84": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG84" + }, + "PCIE_BOT.PCIE_PIPETX6DATA10->PCIE_LOGIC_OUTS_B11_R_12": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_12" + }, + "PCIE_BOT.PCIE_IMUX37_R_4->PCIE_PIPERX7DATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA8" + }, + "PCIE_BOT.PCIE_PIPETX5DATA9->PCIE_LOGIC_OUTS_B13_R_5": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_5" + }, + "PCIE_BOT.PCIE_IMUX1_R_6->PCIE_MIMTXRDATA25": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA25" + }, + "PCIE_BOT.PCIE_TRNFCCPLD1->PCIE_LOGIC_OUTS_B4_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_9" + }, + "PCIE_BOT.PCIE_PIPETX0DATA2->PCIE_LOGIC_OUTS_B11_L_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_18" + }, + "PCIE_BOT.PCIE_DBGVECB5->PCIE_LOGIC_OUTS_B22_R_12": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_12" + }, + "PCIE_BOT.PCIE_IMUX17_R_13->PCIE_CFGVENDID2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID2" + }, + "PCIE_BOT.PCIE_PIPETX6COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6COMPLIANCE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_14" + }, + "PCIE_BOT.PCIE_TRNRD101->PCIE_LOGIC_OUTS_B4_R_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD101", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_19" + }, + "PCIE_BOT.PCIE_TL2ERRHDR9->PCIE_LOGIC_OUTS_B9_R_10": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_10" + }, + "PCIE_BOT.PCIE_PIPETX3DATA9->PCIE_LOGIC_OUTS_B13_L_1": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_1" + }, + "PCIE_BOT.PCIE_PIPETX5DATA5->PCIE_LOGIC_OUTS_B4_R_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_6" + }, + "PCIE_BOT.PCIE_DBGVECB30->PCIE_LOGIC_OUTS_B12_R_2": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_2" + }, + "PCIE_BOT.PCIE_CFGMGMTDO12->PCIE_LOGIC_OUTS_B12_R_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_14" + }, + "PCIE_BOT.PCIE_IMUX11_R_7->PCIE_CFGMGMTDI20": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI20" + }, + "PCIE_BOT.PCIE_IMUX37_L_15->PCIE_PIPERX2DATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA8" + }, + "PCIE_BOT.PCIE_IMUX4_L_3->PCIE_CFGERRAERHEADERLOG86": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG86" + }, + "PCIE_BOT.PCIE_IMUX4_L_2->PCIE_CFGERRAERHEADERLOG82": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG82" + }, + "PCIE_BOT.PCIE_TRNFCNPH2->PCIE_LOGIC_OUTS_B12_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPH2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_2" + }, + "PCIE_BOT.PCIE_IMUX11_R_6->PCIE_CFGMGMTDI17": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI17" + }, + "PCIE_BOT.PCIE_PIPETX2DATA14->PCIE_LOGIC_OUTS_B2_L_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_11" + }, + "PCIE_BOT.PCIE_DBGVECC10->PCIE_LOGIC_OUTS_B21_L_9": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_9" + }, + "PCIE_BOT.PCIE_CFGDEVSTATUSNONFATALERRDETECTED->PCIE_LOGIC_OUTS_B17_L_9": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_9" + }, + "PCIE_BOT.PCIE_IMUX4_R_19->PCIE_MIMRXRDATA56": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA56" + }, + "PCIE_BOT.PCIE_MIMRXWDATA60->PCIE_LOGIC_OUTS_B6_R_18": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_18" + }, + "PCIE_BOT.PCIE_TRNRD125->PCIE_LOGIC_OUTS_B1_R_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD125", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_12" + }, + "PCIE_BOT.PCIE_IMUX3_R_11->PCIE_TRNTD73": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD73" + }, + "PCIE_BOT.PCIE_DBGVECB24->PCIE_LOGIC_OUTS_B12_R_4": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_4" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO6->PCIE_LOGIC_OUTS_B13_L_9": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_9" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMPME->PCIE_LOGIC_OUTS_B14_L_18": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDPMPME", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_18" + }, + "PCIE_BOT.PCIE_IMUX11_R_12->PCIE_CFGERRAERHEADERLOG24": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG24" + }, + "PCIE_BOT.PCIE_TL2ERRFCPE->PCIE_LOGIC_OUTS_B19_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRFCPE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_13" + }, + "PCIE_BOT.PCIE_MIMRXWDATA42->PCIE_LOGIC_OUTS_B14_R_15": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_15" + }, + "PCIE_BOT.PCIE_CFGMSGDATA1->PCIE_LOGIC_OUTS_B13_L_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_10" + }, + "PCIE_BOT.PCIE_IMUX9_R_14->PCIE_CFGERRAERHEADERLOG14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG14" + }, + "PCIE_BOT.PCIE_IMUX9_R_4->PCIE_CFGERRAERHEADERLOG55": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG55" + }, + "PCIE_BOT.PCIE_MIMRXWDATA40->PCIE_LOGIC_OUTS_B13_R_15": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_15" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA18->PCIE_LOGIC_OUTS_B6_L_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_16" + }, + "PCIE_BOT.PCIE_TRNFCCPLH3->PCIE_LOGIC_OUTS_B8_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLH3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_7" + }, + "PCIE_BOT.PCIE_TL2ERRHDR20->PCIE_LOGIC_OUTS_B10_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_1" + }, + "PCIE_BOT.PCIE_PIPETX1DATA8->PCIE_LOGIC_OUTS_B9_L_5": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_5" + }, + "PCIE_BOT.PCIE_TRNFCNPH4->PCIE_LOGIC_OUTS_B14_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPH4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_2" + }, + "PCIE_BOT.PCIE_IMUX0_R_9->PCIE_MIMTXRDATA36": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA36" + }, + "PCIE_BOT.PCIE_PIPETX6POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6POWERDOWN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_13" + }, + "PCIE_BOT.PCIE_IMUX5_R_12->PCIE_CFGMGMTDWADDR3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR3" + }, + "PCIE_BOT.PCIE_PIPETX4DATA0->PCIE_LOGIC_OUTS_B9_R_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_18" + }, + "PCIE_BOT.PCIE_IMUX14_L_17->PCIE_DRPADDR1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR1" + }, + "PCIE_BOT.PCIE_IMUX37_L_6->PCIE_PIPERX3DATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA0" + }, + "PCIE_BOT.PCIE_IMUX4_R_7->PCIE_MIMTXRDATA40": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA40" + }, + "PCIE_BOT.PCIE_IMUX6_R_19->PCIE_MIMRXRDATA58": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA58" + }, + "PCIE_BOT.PCIE_IMUX12_L_6->PCIE_CFGSUBSYSID6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID6" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS1->PCIE_LOGIC_OUTS_B19_R_17": { + "can_invert": "0", + "src_wire": "PCIE_LL2LINKSTATUS1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_17" + }, + "PCIE_BOT.PCIE_DBGVECB21->PCIE_LOGIC_OUTS_B18_R_5": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_5" + }, + "PCIE_BOT.PCIE_MIMRXWDATA58->PCIE_LOGIC_OUTS_B15_R_15": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA58", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_15" + }, + "PCIE_BOT.PCIE_IMUX14_R_12->PCIE_CFGDSBUSNUMBER0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER0" + }, + "PCIE_BOT.PCIE_IMUX15_L_17->PCIE_DRPADDR2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR2" + }, + "PCIE_BOT.PCIE_IMUX6_R_0->PCIE_MIMTXRDATA64": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA64" + }, + "PCIE_BOT.PCIE_IMUX16_L_0->PCIE_CFGERRAERHEADERLOG77": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG77" + }, + "PCIE_BOT.PCIE_PIPETX7CHARISK0->PCIE_LOGIC_OUTS_B16_R_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7CHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_2" + }, + "PCIE_BOT.PCIE_IMUX1_R_11->PCIE_TRNTD71": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD71" + }, + "PCIE_BOT.PCIE_PIPETX3DATA10->PCIE_LOGIC_OUTS_B11_L_1": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_1" + }, + "PCIE_BOT.PCIE_MIMTXWADDR12->PCIE_LOGIC_OUTS_B10_R_1": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_1" + }, + "PCIE_BOT.PCIE_PIPETX3DATA15->PCIE_LOGIC_OUTS_B6_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_0" + }, + "PCIE_BOT.PCIE_TRNFCCPLH4->PCIE_LOGIC_OUTS_B10_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLH4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_7" + }, + "PCIE_BOT.PCIE_DBGVECA47->PCIE_LOGIC_OUTS_B19_R_12": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_12" + }, + "PCIE_BOT.PCIE_IMUX18_R_1->PCIE_CFGDSFUNCTIONNUMBER1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX18_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSFUNCTIONNUMBER1" + }, + "PCIE_BOT.PCIE_IMUX15_L_2->PCIE_CFGREVID7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID7" + }, + "PCIE_BOT.PCIE_IMUX35_R_8->PCIE_PIPERX5STATUS2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5STATUS2" + }, + "PCIE_BOT.PCIE_IMUX2_R_2->PCIE_MIMTXRDATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA10" + }, + "PCIE_BOT.PCIE_IMUX12_L_7->PCIE_CFGSUBSYSID10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID10" + }, + "PCIE_BOT.PCIE_IMUX11_R_14->PCIE_CFGERRAERHEADERLOG16": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG16" + }, + "PCIE_BOT.PCIE_TRNFCCPLD7->PCIE_LOGIC_OUTS_B6_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_10" + }, + "PCIE_BOT.PCIE_TRNRD35->PCIE_LOGIC_OUTS_B0_L_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_14" + }, + "PCIE_BOT.PCIE_MIMRXWDATA64->PCIE_LOGIC_OUTS_B10_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA64", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_16" + }, + "PCIE_BOT.PCIE_DBGVECB13->PCIE_LOGIC_OUTS_B14_R_7": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_7" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA25->PCIE_LOGIC_OUTS_B7_L_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_18" + }, + "PCIE_BOT.PCIE_IMUX7_L_5->PCIE_CFGERRAERHEADERLOG97": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG97" + }, + "PCIE_BOT.PCIE_TL2ERRHDR51->PCIE_LOGIC_OUTS_B8_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_10" + }, + "PCIE_BOT.PCIE_IMUX9_R_15->PCIE_CFGERRCORN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRCORN" + }, + "PCIE_BOT.PCIE_IMUX1_R_16->PCIE_MIMRXRDATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA5" + }, + "PCIE_BOT.PCIE_IMUX5_L_5->PCIE_CFGERRAERHEADERLOG95": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG95" + }, + "PCIE_BOT.PCIE_PIPETX5DATA0->PCIE_LOGIC_OUTS_B9_R_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_7" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTB->PCIE_LOGIC_OUTS_B15_L_17": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_17" + }, + "PCIE_BOT.PCIE_IMUX12_L_17->PCIE_DRPWE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPWE" + }, + "PCIE_BOT.PCIE_IMUX8_L_12->PCIE_CFGDSN25": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN25" + }, + "PCIE_BOT.PCIE_TL2ERRHDR43->PCIE_LOGIC_OUTS_B8_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_8" + }, + "PCIE_BOT.PCIE_IMUX0_L_3->PCIE_TRNTD96": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD96" + }, + "PCIE_BOT.PCIE_TRNTBUFAV5->PCIE_LOGIC_OUTS_B7_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TRNTBUFAV5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_4" + }, + "PCIE_BOT.PCIE_DBGVECC5->PCIE_LOGIC_OUTS_B20_L_8": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_8" + }, + "PCIE_BOT.PCIE_DBGVECB16->PCIE_LOGIC_OUTS_B9_R_6": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_6" + }, + "PCIE_BOT.PCIE_IMUX8_R_11->PCIE_CFGMGMTDWADDR2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR2" + }, + "PCIE_BOT.PCIE_IMUX9_R_17->PCIE_TRNTD47": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD47" + }, + "PCIE_BOT.PCIE_IMUX1_R_2->PCIE_MIMTXRDATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA9" + }, + "PCIE_BOT.PCIE_TL2ERRHDR25->PCIE_LOGIC_OUTS_B12_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_3" + }, + "PCIE_BOT.PCIE_IMUX13_R_14->PCIE_CFGINTERRUPTDI1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI1" + }, + "PCIE_BOT.PCIE_IMUX0_R_6->PCIE_MIMTXRDATA24": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA24" + }, + "PCIE_BOT.PCIE_MIMTXWDATA56->PCIE_LOGIC_OUTS_B10_R_0": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_0" + }, + "PCIE_BOT.PCIE_CFGMGMTDO10->PCIE_LOGIC_OUTS_B15_R_13": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_13" + }, + "PCIE_BOT.PCIE_TRNRD52->PCIE_LOGIC_OUTS_B2_L_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD52", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_18" + }, + "PCIE_BOT.PCIE_IMUX9_R_16->PCIE_CFGERRCPLABORTN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRCPLABORTN" + }, + "PCIE_BOT.PCIE_IMUX21_R_13->PCIE_DBGMODE1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX21_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DBGMODE1" + }, + "PCIE_BOT.PCIE_DBGVECA23->PCIE_LOGIC_OUTS_B22_R_19": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_19" + }, + "PCIE_BOT.PCIE_IMUX15_R_13->PCIE_CFGINTERRUPTDI7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI7" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK->PCIE_LOGIC_OUTS_B21_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_15" + }, + "PCIE_BOT.PCIE_IMUX7_L_1->PCIE_CFGERRAERHEADERLOG81": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG81" + }, + "PCIE_BOT.PCIE_PIPETX0DATA14->PCIE_LOGIC_OUTS_B2_L_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_15" + }, + "PCIE_BOT.PCIE_IMUX3_R_5->PCIE_MIMTXRDATA23": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA23" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA23->PCIE_LOGIC_OUTS_B14_L_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_17" + }, + "PCIE_BOT.PCIE_IMUX12_R_6->PCIE_CFGMGMTDI18": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI18" + }, + "PCIE_BOT.PCIE_IMUX1_R_17->PCIE_MIMRXRDATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA9" + }, + "PCIE_BOT.PCIE_CFGMGMTRDWRDONEN->PCIE_LOGIC_OUTS_B16_R_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTRDWRDONEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_12" + }, + "PCIE_BOT.PCIE_IMUX6_L_1->PCIE_CFGERRAERHEADERLOG80": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG80" + }, + "PCIE_BOT.PCIE_IMUX10_R_4->PCIE_CFGERRAERHEADERLOG56": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG56" + }, + "PCIE_BOT.PCIE_IMUX12_R_5->PCIE_CFGERRAERHEADERLOG51": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG51" + }, + "PCIE_BOT.PCIE_DBGVECB1->PCIE_LOGIC_OUTS_B17_R_8": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_8" + }, + "PCIE_BOT.PCIE_IMUX11_L_17->PCIE_CFGDSN48": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN48" + }, + "PCIE_BOT.PCIE_TL2ERRHDR33->PCIE_LOGIC_OUTS_B8_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_5" + }, + "PCIE_BOT.PCIE_TL2ERRHDR37->PCIE_LOGIC_OUTS_B15_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_6" + }, + "PCIE_BOT.PCIE_IMUX14_L_10->PCIE_CFGSUBSYSVENDID2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID2" + }, + "PCIE_BOT.PCIE_TL2ERRHDR48->PCIE_LOGIC_OUTS_B9_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR48", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_9" + }, + "PCIE_BOT.PCIE_IMUX2_R_17->PCIE_MIMRXRDATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA10" + }, + "PCIE_BOT.PCIE_IMUX1_L_14->PCIE_TRNRNPOK": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNRNPOK" + }, + "PCIE_BOT.PCIE_TRNRD10->PCIE_LOGIC_OUTS_B5_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_7" + }, + "PCIE_BOT.PCIE_DBGVECC4->PCIE_LOGIC_OUTS_B19_L_8": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_8" + }, + "PCIE_BOT.PCIE_IMUX1_L_12->PCIE_TRNTSRCDSC": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTSRCDSC" + }, + "PCIE_BOT.PCIE_IMUX21_R_11->PCIE_PLDBGMODE0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX21_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDBGMODE0" + }, + "PCIE_BOT.PCIE_DBGVECA36->PCIE_LOGIC_OUTS_B19_R_15": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_15" + }, + "PCIE_BOT.PCIE_IMUX10_L_12->PCIE_CFGDSN27": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN27" + }, + "PCIE_BOT.PCIE_IMUX2_L_3->PCIE_TRNTD98": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD98" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3->PCIE_LOGIC_OUTS_B20_L_18": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_18" + }, + "PCIE_BOT.PCIE_IMUX33_R_6->PCIE_PIPERX7DATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA2" + }, + "PCIE_BOT.PCIE_PIPETX6DATA1->PCIE_LOGIC_OUTS_B13_R_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_14" + }, + "PCIE_BOT.PCIE_IMUX38_L_16->PCIE_PIPERX2DATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA5" + }, + "PCIE_BOT.PCIE_IMUX17_R_11->PCIE_CFGVENDID10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID10" + }, + "PCIE_BOT.PCIE_PL2RXELECIDLE->PCIE_LOGIC_OUTS_B7_R_19": { + "can_invert": "0", + "src_wire": "PCIE_PL2RXELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_19" + }, + "PCIE_BOT.PCIE_IMUX5_L_7->PCIE_CFGERRAERHEADERLOG103": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG103" + }, + "PCIE_BOT.PCIE_IMUX12_R_18->PCIE_TRNTD42": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD42" + }, + "PCIE_BOT.PCIE_CFGMGMTDO2->PCIE_LOGIC_OUTS_B13_R_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_10" + }, + "PCIE_BOT.PCIE_IMUX34_L_9->PCIE_PIPERX1DATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA7" + }, + "PCIE_BOT.PCIE_IMUX10_R_16->PCIE_CFGERRCPLUNEXPECTN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRCPLUNEXPECTN" + }, + "PCIE_BOT.PCIE_PIPETX4DATA7->PCIE_LOGIC_OUTS_B6_R_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_17" + }, + "PCIE_BOT.PCIE_IMUX16_R_8->PCIE_PIPERX5CHARISK1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5CHARISK1" + }, + "PCIE_BOT.PCIE_IMUX6_R_7->PCIE_MIMTXRDATA42": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA42" + }, + "PCIE_BOT.PCIE_IMUX36_L_15->PCIE_PIPERX2DATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA9" + }, + "PCIE_BOT.PCIE_IMUX5_L_15->PCIE_CFGERRTLPCPLHEADER7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER7" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE1->PCIE_LOGIC_OUTS_B17_R_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTMMENABLE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_10" + }, + "PCIE_BOT.PCIE_CTRL0_R_1->PCIE_CMSTICKYRSTN": { + "can_invert": "0", + "src_wire": "PCIE_CTRL0_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CMSTICKYRSTN" + }, + "PCIE_BOT.PCIE_TL2ERRHDR1->PCIE_LOGIC_OUTS_B7_R_12": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_12" + }, + "PCIE_BOT.PCIE_IMUX17_L_1->PCIE_PLDBGMODE2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDBGMODE2" + }, + "PCIE_BOT.PCIE_PIPETX1POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1POWERDOWN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_6" + }, + "PCIE_BOT.PCIE_DBGVECA49->PCIE_LOGIC_OUTS_B21_R_12": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA49", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_12" + }, + "PCIE_BOT.PCIE_MIMRXWDATA44->PCIE_LOGIC_OUTS_B18_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_16" + }, + "PCIE_BOT.PCIE_IMUX4_L_6->PCIE_CFGERRAERHEADERLOG98": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG98" + }, + "PCIE_BOT.PCIE_PIPETX2DATA6->PCIE_LOGIC_OUTS_B2_L_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_13" + }, + "PCIE_BOT.PCIE_MIMTXWDATA55->PCIE_LOGIC_OUTS_B20_R_2": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_2" + }, + "PCIE_BOT.PCIE_MIMTXWADDR7->PCIE_LOGIC_OUTS_B15_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_4" + }, + "PCIE_BOT.PCIE_IMUX6_L_4->PCIE_CFGERRAERHEADERLOG92": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG92" + }, + "PCIE_BOT.PCIE_IMUX13_R_7->PCIE_CFGMGMTDI22": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI22" + }, + "PCIE_BOT.PCIE_DBGSCLRB->PCIE_LOGIC_OUTS_B20_L_10": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_10" + }, + "PCIE_BOT.PCIE_TRNFCNPD6->PCIE_LOGIC_OUTS_B5_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_5" + }, + "PCIE_BOT.PCIE_IMUX14_R_13->PCIE_CFGINTERRUPTDI6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI6" + }, + "PCIE_BOT.PCIE_IMUX20_L_0->PCIE_CFGPORTNUMBER7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER7" + }, + "PCIE_BOT.PCIE_PIPETX5DATA6->PCIE_LOGIC_OUTS_B2_R_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_6" + }, + "PCIE_BOT.PCIE_IMUX2_L_18->PCIE_TRNTDLLPDATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA13" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA3->PCIE_LOGIC_OUTS_B7_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_12" + }, + "PCIE_BOT.PCIE_TL2ERRHDR10->PCIE_LOGIC_OUTS_B6_R_9": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_9" + }, + "PCIE_BOT.PCIE_IMUX0_L_14->PCIE_TRNRFCPRET": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNRFCPRET" + }, + "PCIE_BOT.PCIE_TRNFCPD9->PCIE_LOGIC_OUTS_B4_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_1" + }, + "PCIE_BOT.PCIE_IMUX2_L_4->PCIE_TRNTD102": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD102" + }, + "PCIE_BOT.PCIE_IMUX39_L_19->PCIE_PIPERX0STATUS0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0STATUS0" + }, + "PCIE_BOT.PCIE_PIPETX1ELECIDLE->PCIE_LOGIC_OUTS_B3_L_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1ELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_6" + }, + "PCIE_BOT.PCIE_IMUX14_L_11->PCIE_CFGSUBSYSVENDID6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID6" + }, + "PCIE_BOT.PCIE_TL2ASPMSUSPENDREQ->PCIE_LOGIC_OUTS_B6_R_14": { + "can_invert": "0", + "src_wire": "PCIE_TL2ASPMSUSPENDREQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_14" + }, + "PCIE_BOT.PCIE_IMUX8_R_19->PCIE_TRNTD4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD4" + }, + "PCIE_BOT.PCIE_PIPETX5DATA12->PCIE_LOGIC_OUTS_B0_R_4": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_4" + }, + "PCIE_BOT.PCIE_IMUX0_R_16->PCIE_MIMRXRDATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA4" + }, + "PCIE_BOT.PCIE_MIMTXRADDR2->PCIE_LOGIC_OUTS_B22_R_7": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_7" + }, + "PCIE_BOT.PCIE_IMUX18_R_11->PCIE_CFGVENDID11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX18_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID11" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE1->PCIE_LOGIC_OUTS_B8_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLLTSSMSTATE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_0" + }, + "PCIE_BOT.PCIE_IMUX15_L_13->PCIE_CFGSUBSYSVENDID15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID15" + }, + "PCIE_BOT.PCIE_USERRSTN->PCIE_LOGIC_OUTS_B12_R_8": { + "can_invert": "0", + "src_wire": "PCIE_USERRSTN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_8" + }, + "PCIE_BOT.PCIE_MIMTXWADDR1->PCIE_LOGIC_OUTS_B6_R_1": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_1" + }, + "PCIE_BOT.PCIE_PIPETX5CHARISK1->PCIE_LOGIC_OUTS_B16_R_4": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5CHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_4" + }, + "PCIE_BOT.PCIE_IMUX2_R_19->PCIE_MIMRXRDATA18": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA18" + }, + "PCIE_BOT.PCIE_IMUX2_R_14->PCIE_TRNTD60": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD60" + }, + "PCIE_BOT.PCIE_MIMRXWDATA65->PCIE_LOGIC_OUTS_B10_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA65", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_19" + }, + "PCIE_BOT.PCIE_DBGVECB19->PCIE_LOGIC_OUTS_B7_R_5": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_5" + }, + "PCIE_BOT.PCIE_DBGVECA41->PCIE_LOGIC_OUTS_B22_R_14": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_14" + }, + "PCIE_BOT.PCIE_IMUX15_L_12->PCIE_CFGSUBSYSVENDID11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID11" + }, + "PCIE_BOT.PCIE_TRNRD121->PCIE_LOGIC_OUTS_B8_R_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD121", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_13" + }, + "PCIE_BOT.PCIE_MIMRXWDATA38->PCIE_LOGIC_OUTS_B12_R_15": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_15" + }, + "PCIE_BOT.PCIE_DBGVECB45->PCIE_LOGIC_OUTS_B20_L_2": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_2" + }, + "PCIE_BOT.PCIE_IMUX5_R_9->PCIE_MIMTXRDATA67": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA67" + }, + "PCIE_BOT.PCIE_DBGSCLRC->PCIE_LOGIC_OUTS_B21_L_10": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_10" + }, + "PCIE_BOT.PCIE_IMUX39_L_9->PCIE_PIPERX1DATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA4" + }, + "PCIE_BOT.PCIE_IMUX35_L_8->PCIE_PIPERX1STATUS2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1STATUS2" + }, + "PCIE_BOT.PCIE_MIMRXWDATA36->PCIE_LOGIC_OUTS_B17_R_15": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_15" + }, + "PCIE_BOT.PCIE_DBGVECC11->PCIE_LOGIC_OUTS_B18_L_10": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_10" + }, + "PCIE_BOT.PCIE_TRNRD104->PCIE_LOGIC_OUTS_B2_R_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD104", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_18" + }, + "PCIE_BOT.PCIE_PIPETX5DATA10->PCIE_LOGIC_OUTS_B11_R_5": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_5" + }, + "PCIE_BOT.PCIE_DBGVECA35->PCIE_LOGIC_OUTS_B11_R_15": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_15" + }, + "PCIE_BOT.PCIE_DBGVECB47->PCIE_LOGIC_OUTS_B18_L_3": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_3" + }, + "PCIE_BOT.PCIE_DBGVECC6->PCIE_LOGIC_OUTS_B21_L_8": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_8" + }, + "PCIE_BOT.PCIE_PIPETX6DATA14->PCIE_LOGIC_OUTS_B2_R_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_11" + }, + "PCIE_BOT.PCIE_PIPETX1DATA3->PCIE_LOGIC_OUTS_B15_L_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_7" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA12->PCIE_LOGIC_OUTS_B8_L_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_15" + }, + "PCIE_BOT.PCIE_CFGROOTCONTROLPMEINTEN->PCIE_LOGIC_OUTS_B16_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGROOTCONTROLPMEINTEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_19" + }, + "PCIE_BOT.PCIE_IMUX6_R_12->PCIE_CFGMGMTDWADDR4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR4" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO7->PCIE_LOGIC_OUTS_B14_L_9": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTDO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_9" + }, + "PCIE_BOT.PCIE_IMUX11_R_5->PCIE_CFGERRAERHEADERLOG50": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG50" + }, + "PCIE_BOT.PCIE_IMUX4_L_15->PCIE_CFGERRTLPCPLHEADER6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER6" + }, + "PCIE_BOT.PCIE_CFGDEVSTATUSCORRERRDETECTED->PCIE_LOGIC_OUTS_B16_L_9": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVSTATUSCORRERRDETECTED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_9" + }, + "PCIE_BOT.PCIE_IMUX9_L_0->PCIE_PLDIRECTEDLTSSMNEW0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW0" + }, + "PCIE_BOT.PCIE_IMUX0_L_6->PCIE_TRNTD108": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD108" + }, + "PCIE_BOT.PCIE_TRNFCCPLH7->PCIE_LOGIC_OUTS_B6_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLH7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_8" + }, + "PCIE_BOT.PCIE_TL2ERRHDR0->PCIE_LOGIC_OUTS_B6_R_12": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_12" + }, + "PCIE_BOT.PCIE_TRNFCNPD5->PCIE_LOGIC_OUTS_B4_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_5" + }, + "PCIE_BOT.PCIE_MIMRXWDATA62->PCIE_LOGIC_OUTS_B19_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_16" + }, + "PCIE_BOT.PCIE_PIPETX6DATA6->PCIE_LOGIC_OUTS_B2_R_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_13" + }, + "PCIE_BOT.PCIE_IMUX5_L_13->PCIE_CFGERRAERHEADERLOG127": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG127" + }, + "PCIE_BOT.PCIE_CFGMGMTDO31->PCIE_LOGIC_OUTS_B18_R_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_14" + }, + "PCIE_BOT.PCIE_MIMTXWDATA30->PCIE_LOGIC_OUTS_B20_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_6" + }, + "PCIE_BOT.PCIE_TL2ERRHDR59->PCIE_LOGIC_OUTS_B8_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR59", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_12" + }, + "PCIE_BOT.PCIE_PIPETX0DATA9->PCIE_LOGIC_OUTS_B13_L_16": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_16" + }, + "PCIE_BOT.PCIE_CFGMSGDATA0->PCIE_LOGIC_OUTS_B12_L_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_10" + }, + "PCIE_BOT.PCIE_TL2ERRHDR61->PCIE_LOGIC_OUTS_B12_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_12" + }, + "PCIE_BOT.PCIE_TRNFCCPLD11->PCIE_LOGIC_OUTS_B10_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_11" + }, + "PCIE_BOT.PCIE_IMUX16_L_8->PCIE_PIPERX1CHARISK1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1CHARISK1" + }, + "PCIE_BOT.PCIE_TRNFCNPD10->PCIE_LOGIC_OUTS_B12_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_6" + }, + "PCIE_BOT.PCIE_IMUX17_R_2->PCIE_CFGERRAERHEADERLOG63": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG63" + }, + "PCIE_BOT.PCIE_DBGVECB57->PCIE_LOGIC_OUTS_B20_L_5": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_5" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA6->PCIE_LOGIC_OUTS_B13_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_13" + }, + "PCIE_BOT.PCIE_IMUX10_L_6->PCIE_CFGDSN3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN3" + }, + "PCIE_BOT.PCIE_IMUX19_R_11->PCIE_CFGVENDID12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX19_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID12" + }, + "PCIE_BOT.PCIE_IMUX1_L_15->PCIE_TRNTDLLPDATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA0" + }, + "PCIE_BOT.PCIE_IMUX2_R_8->PCIE_MIMTXRDATA34": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA34" + }, + "PCIE_BOT.PCIE_LL2BADTLPERR->PCIE_LOGIC_OUTS_B13_R_13": { + "can_invert": "0", + "src_wire": "PCIE_LL2BADTLPERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_13" + }, + "PCIE_BOT.PCIE_IMUX12_L_0->PCIE_PLDIRECTEDLTSSMNEW3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW3" + }, + "PCIE_BOT.PCIE_PIPETX5POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5POWERDOWN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_6" + }, + "PCIE_BOT.PCIE_IMUX35_R_7->PCIE_PIPERX5DATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA14" + }, + "PCIE_BOT.PCIE_IMUX39_R_18->PCIE_PIPERX4DATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA12" + }, + "PCIE_BOT.PCIE_DBGVECC9->PCIE_LOGIC_OUTS_B20_L_9": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_9" + }, + "PCIE_BOT.PCIE_TRNFCNPD4->PCIE_LOGIC_OUTS_B11_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_4" + }, + "PCIE_BOT.PCIE_IMUX9_L_1->PCIE_CFGPMHALTASPML1N": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMHALTASPML1N" + }, + "PCIE_BOT.PCIE_MIMTXWDATA65->PCIE_LOGIC_OUTS_B10_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA65", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_5" + }, + "PCIE_BOT.PCIE_PIPETX3DATA6->PCIE_LOGIC_OUTS_B2_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_2" + }, + "PCIE_BOT.PCIE_PIPETX6CHARISK1->PCIE_LOGIC_OUTS_B16_R_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6CHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_11" + }, + "PCIE_BOT.PCIE_MIMTXRADDR8->PCIE_LOGIC_OUTS_B22_R_3": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_3" + }, + "PCIE_BOT.PCIE_IMUX3_R_13->PCIE_TRNTD65": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD65" + }, + "PCIE_BOT.PCIE_IMUX10_L_8->PCIE_CFGDSN11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN11" + }, + "PCIE_BOT.PCIE_PIPETX7DATA8->PCIE_LOGIC_OUTS_B9_R_1": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_1" + }, + "PCIE_BOT.PCIE_IMUX11_R_11->PCIE_CFGERRAERHEADERLOG28": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG28" + }, + "PCIE_BOT.PCIE_MIMTXWDATA64->PCIE_LOGIC_OUTS_B16_R_1": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA64", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_1" + }, + "PCIE_BOT.PCIE_PIPETX7POWERDOWN1->PCIE_LOGIC_OUTS_B7_R_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7POWERDOWN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_2" + }, + "PCIE_BOT.PCIE_IMUX10_R_2->PCIE_TRNTD81": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD81" + }, + "PCIE_BOT.PCIE_IMUX16_R_3->PCIE_CFGERRAERHEADERLOG61": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG61" + }, + "PCIE_BOT.PCIE_PIPETX6DATA15->PCIE_LOGIC_OUTS_B6_R_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_11" + }, + "PCIE_BOT.PCIE_PLLTSSMSTATE0->PCIE_LOGIC_OUTS_B7_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLLTSSMSTATE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA9->PCIE_LOGIC_OUTS_B13_R_1": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_1" + }, + "PCIE_BOT.PCIE_MIMTXWDATA36->PCIE_LOGIC_OUTS_B11_R_0": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_0" + }, + "PCIE_BOT.PCIE_IMUX19_L_0->PCIE_CFGPORTNUMBER6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX19_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER6" + }, + "PCIE_BOT.PCIE_TL2ERRHDR21->PCIE_LOGIC_OUTS_B12_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_1" + }, + "PCIE_BOT.PCIE_IMUX14_R_18->PCIE_TRNTD44": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD44" + }, + "PCIE_BOT.PCIE_IMUX5_L_6->PCIE_CFGERRAERHEADERLOG99": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG99" + }, + "PCIE_BOT.PCIE_TL2ERRHDR46->PCIE_LOGIC_OUTS_B11_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_8" + }, + "PCIE_BOT.PCIE_IMUX8_L_14->PCIE_CFGDSN33": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN33" + }, + "PCIE_BOT.PCIE_TRNRD43->PCIE_LOGIC_OUTS_B0_L_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_16" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE2->PCIE_LOGIC_OUTS_B16_L_1": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTMMENABLE2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_1" + }, + "PCIE_BOT.PCIE_IMUX6_L_5->PCIE_CFGERRAERHEADERLOG96": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG96" + }, + "PCIE_BOT.PCIE_IMUX6_R_16->PCIE_TRNTD52": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD52" + }, + "PCIE_BOT.PCIE_IMUX2_L_1->PCIE_PLDIRECTEDLTSSMSTALL": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMSTALL" + }, + "PCIE_BOT.PCIE_IMUX16_R_14->PCIE_CFGINTERRUPTDI4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI4" + }, + "PCIE_BOT.PCIE_TRNRD3->PCIE_LOGIC_OUTS_B5_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_6" + }, + "PCIE_BOT.PCIE_TRNRD108->PCIE_LOGIC_OUTS_B9_R_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD108", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_17" + }, + "PCIE_BOT.PCIE_PIPETX2DATA11->PCIE_LOGIC_OUTS_B15_L_12": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_12" + }, + "PCIE_BOT.PCIE_PIPETX7DATA6->PCIE_LOGIC_OUTS_B2_R_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_2" + }, + "PCIE_BOT.PCIE_TRNFCPD11->PCIE_LOGIC_OUTS_B6_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_1" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA30->PCIE_LOGIC_OUTS_B6_L_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_19" + }, + "PCIE_BOT.PCIE_TRNRD48->PCIE_LOGIC_OUTS_B8_L_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD48", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_17" + }, + "PCIE_BOT.PCIE_IMUX39_L_5->PCIE_PIPERX3DATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA4" + }, + "PCIE_BOT.PCIE_IMUX7_R_11->PCIE_CFGMGMTDWADDR1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR1" + }, + "PCIE_BOT.PCIE_IMUX11_R_4->PCIE_CFGERRAERHEADERLOG57": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG57" + }, + "PCIE_BOT.PCIE_IMUX12_R_3->PCIE_CFGMGMTDI6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI6" + }, + "PCIE_BOT.PCIE_IMUX10_L_14->PCIE_CFGDSN35": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN35" + }, + "PCIE_BOT.PCIE_IMUX9_L_9->PCIE_CFGDSN14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN14" + }, + "PCIE_BOT.PCIE_PIPETX0DATA10->PCIE_LOGIC_OUTS_B11_L_16": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_16" + }, + "PCIE_BOT.PCIE_IMUX13_R_11->PCIE_CFGDSBUSNUMBER3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER3" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO0->PCIE_LOGIC_OUTS_B17_L_5": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_5" + }, + "PCIE_BOT.PCIE_DBGVECA58->PCIE_LOGIC_OUTS_B14_R_9": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA58", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_9" + }, + "PCIE_BOT.PCIE_IMUX14_L_6->PCIE_CFGSUBSYSID8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID8" + }, + "PCIE_BOT.PCIE_IMUX9_L_2->PCIE_CFGPMWAKEN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMWAKEN" + }, + "PCIE_BOT.PCIE_PIPETX5DATA15->PCIE_LOGIC_OUTS_B6_R_4": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_4" + }, + "PCIE_BOT.PCIE_IMUX38_R_3->PCIE_PIPERX7DATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA13" + }, + "PCIE_BOT.PCIE_IMUX14_R_3->PCIE_CFGERRAERHEADERLOG59": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG59" + }, + "PCIE_BOT.PCIE_IMUX8_L_9->PCIE_CFGDSN13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN13" + }, + "PCIE_BOT.PCIE_IMUX6_R_15->PCIE_TRNTD56": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD56" + }, + "PCIE_BOT.PCIE_PIPETX2DATA0->PCIE_LOGIC_OUTS_B9_L_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_14" + }, + "PCIE_BOT.PCIE_IMUX39_R_4->PCIE_PIPERX7STATUS0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7STATUS0" + }, + "PCIE_BOT.PCIE_PIPETX1DATA10->PCIE_LOGIC_OUTS_B11_L_5": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_5" + }, + "PCIE_BOT.PCIE_PIPETX3DATA5->PCIE_LOGIC_OUTS_B4_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_2" + }, + "PCIE_BOT.PCIE_IMUX12_R_8->PCIE_CFGERRAERHEADERLOG41": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG41" + }, + "PCIE_BOT.PCIE_DBGVECA40->PCIE_LOGIC_OUTS_B21_R_14": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_14" + }, + "PCIE_BOT.PCIE_TRNRD118->PCIE_LOGIC_OUTS_B4_R_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD118", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_14" + }, + "PCIE_BOT.PCIE_PLSELLNKRATE->PCIE_LOGIC_OUTS_B1_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLSELLNKRATE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_0" + }, + "PCIE_BOT.PCIE_IMUX7_R_14->PCIE_CFGMGMTRDENN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTRDENN" + }, + "PCIE_BOT.PCIE_TRNRBARHIT2->PCIE_LOGIC_OUTS_B2_R_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNRBARHIT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_9" + }, + "PCIE_BOT.PCIE_DBGVECA55->PCIE_LOGIC_OUTS_B19_R_10": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_10" + }, + "PCIE_BOT.PCIE_MIMRXWDATA39->PCIE_LOGIC_OUTS_B23_R_17": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_17" + }, + "PCIE_BOT.PCIE_IMUX34_R_15->PCIE_PIPERX6ELECIDLE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6ELECIDLE" + }, + "PCIE_BOT.PCIE_IMUX6_R_17->PCIE_MIMRXRDATA66": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA66" + }, + "PCIE_BOT.PCIE_IMUX12_L_13->PCIE_CFGSUBSYSVENDID12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID12" + }, + "PCIE_BOT.PCIE_PLSELLNKWIDTH1->PCIE_LOGIC_OUTS_B5_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLSELLNKWIDTH1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_0" + }, + "PCIE_BOT.PCIE_IMUX10_R_7->PCIE_CFGMGMTDI19": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI19" + }, + "PCIE_BOT.PCIE_IMUX9_L_8->PCIE_CFGDSN10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN10" + }, + "PCIE_BOT.PCIE_TRNLNKUP->PCIE_LOGIC_OUTS_B0_R_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNLNKUP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_7" + }, + "PCIE_BOT.PCIE_IMUX8_L_8->PCIE_CFGDSN9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN9" + }, + "PCIE_BOT.PCIE_TRNRD103->PCIE_LOGIC_OUTS_B0_R_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD103", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_18" + }, + "PCIE_BOT.PCIE_IMUX2_L_2->PCIE_TRNTD94": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD94" + }, + "PCIE_BOT.PCIE_IMUX19_R_12->PCIE_CFGVENDID8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX19_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID8" + }, + "PCIE_BOT.PCIE_CFGPCIELINKSTATE0->PCIE_LOGIC_OUTS_B11_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGPCIELINKSTATE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_19" + }, + "PCIE_BOT.PCIE_PIPETX0DATA12->PCIE_LOGIC_OUTS_B0_L_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_15" + }, + "PCIE_BOT.PCIE_IMUX16_L_17->PCIE_PIPERX2CHARISK0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2CHARISK0" + }, + "PCIE_BOT.PCIE_DBGVECA60->PCIE_LOGIC_OUTS_B20_R_9": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_9" + }, + "PCIE_BOT.PCIE_DBGVECA57->PCIE_LOGIC_OUTS_B21_R_10": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_10" + }, + "PCIE_BOT.PCIE_IMUX32_R_15->PCIE_PIPERX6DATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA11" + }, + "PCIE_BOT.PCIE_MIMRXWDATA43->PCIE_LOGIC_OUTS_B19_R_18": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_18" + }, + "PCIE_BOT.PCIE_IMUX4_L_9->PCIE_CFGERRAERHEADERLOG110": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG110" + }, + "PCIE_BOT.PCIE_PIPETX1DATA1->PCIE_LOGIC_OUTS_B13_L_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_7" + }, + "PCIE_BOT.PCIE_TRNFCPH1->PCIE_LOGIC_OUTS_B6_R_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPH1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_7" + }, + "PCIE_BOT.PCIE_IMUX36_L_6->PCIE_PIPERX3DATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA1" + }, + "PCIE_BOT.PCIE_IMUX38_R_19->PCIE_PIPERX4STATUS1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4STATUS1" + }, + "PCIE_BOT.PCIE_IMUX8_L_18->PCIE_CFGDSN49": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN49" + }, + "PCIE_BOT.PCIE_MIMTXWDATA52->PCIE_LOGIC_OUTS_B12_R_0": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA52", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_0" + }, + "PCIE_BOT.PCIE_PIPETX0DATA15->PCIE_LOGIC_OUTS_B6_L_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_15" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD2->PCIE_LOGIC_OUTS_B21_L_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_14" + }, + "PCIE_BOT.PCIE_IMUX16_L_6->PCIE_PIPERX3CHARISK0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3CHARISK0" + }, + "PCIE_BOT.PCIE_IMUX18_R_2->PCIE_CFGERRAERHEADERLOG64": { + "can_invert": "0", + "src_wire": "PCIE_IMUX18_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG64" + }, + "PCIE_BOT.PCIE_PIPETX3DATA1->PCIE_LOGIC_OUTS_B13_L_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_3" + }, + "PCIE_BOT.PCIE_MIMTXWDATA25->PCIE_LOGIC_OUTS_B10_R_8": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_8" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLURERRREPORTINGEN->PCIE_LOGIC_OUTS_B21_L_13": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLURERRREPORTINGEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_13" + }, + "PCIE_BOT.PCIE_IMUX2_R_16->PCIE_MIMRXRDATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA6" + }, + "PCIE_BOT.PCIE_IMUX2_L_5->PCIE_TRNTD106": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD106" + }, + "PCIE_BOT.PCIE_IMUX20_R_12->PCIE_CFGVENDID9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID9" + }, + "PCIE_BOT.PCIE_IMUX13_R_1->PCIE_CFGERRAERHEADERLOG67": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG67" + }, + "PCIE_BOT.PCIE_IMUX38_R_8->PCIE_PIPERX5STATUS1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5STATUS1" + }, + "PCIE_BOT.PCIE_IMUX17_R_17->PCIE_CFGERRINTERNALCORN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRINTERNALCORN" + }, + "PCIE_BOT.PCIE_IMUX16_R_1->PCIE_CFGDSDEVICENUMBER4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER4" + }, + "PCIE_BOT.PCIE_IMUX0_L_18->PCIE_TRNTDLLPDATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA11" + }, + "PCIE_BOT.PCIE_IMUX1_R_18->PCIE_MIMRXRDATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA13" + }, + "PCIE_BOT.PCIE_IMUX7_R_8->PCIE_CFGMGMTDI25": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI25" + }, + "PCIE_BOT.PCIE_IMUX38_L_7->PCIE_PIPERX1DATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA13" + }, + "PCIE_BOT.PCIE_IMUX33_L_17->PCIE_PIPERX2DATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA2" + }, + "PCIE_BOT.PCIE_MIMTXWDATA27->PCIE_LOGIC_OUTS_B13_R_9": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_9" + }, + "PCIE_BOT.PCIE_IMUX5_R_2->PCIE_MIMTXRDATA55": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA55" + }, + "PCIE_BOT.PCIE_IMUX8_R_18->PCIE_TRNTD0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD0" + }, + "PCIE_BOT.PCIE_PIPETXRCVRDET->PCIE_LOGIC_OUTS_B15_R_9": { + "can_invert": "0", + "src_wire": "PCIE_PIPETXRCVRDET", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_9" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS2->PCIE_LOGIC_OUTS_B3_R_16": { + "can_invert": "0", + "src_wire": "PCIE_LL2LINKSTATUS2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_16" + }, + "PCIE_BOT.PCIE_PLINITIALLINKWIDTH0->PCIE_LOGIC_OUTS_B8_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PLINITIALLINKWIDTH0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_2" + }, + "PCIE_BOT.PCIE_TRNRD46->PCIE_LOGIC_OUTS_B3_L_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_16" + }, + "PCIE_BOT.PCIE_IMUX7_L_4->PCIE_CFGERRAERHEADERLOG93": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG93" + }, + "PCIE_BOT.PCIE_IMUX37_L_4->PCIE_PIPERX3DATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA8" + }, + "PCIE_BOT.PCIE_PIPETX1DATA14->PCIE_LOGIC_OUTS_B2_L_4": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_4" + }, + "PCIE_BOT.PCIE_IMUX33_L_16->PCIE_PIPERX2CHANISALIGNED": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2CHANISALIGNED" + }, + "PCIE_BOT.PCIE_IMUX4_L_19->PCIE_CFGERRTLPCPLHEADER22": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER22" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA22->PCIE_LOGIC_OUTS_B13_L_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_17" + }, + "PCIE_BOT.PCIE_DBGVECA29->PCIE_LOGIC_OUTS_B20_R_17": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_17" + }, + "PCIE_BOT.PCIE_IMUX39_R_9->PCIE_PIPERX5DATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA4" + }, + "PCIE_BOT.PCIE_TRNFCCPLD4->PCIE_LOGIC_OUTS_B7_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_9" + }, + "PCIE_BOT.PCIE_PL2LINKUP->PCIE_LOGIC_OUTS_B8_R_14": { + "can_invert": "0", + "src_wire": "PCIE_PL2LINKUP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_14" + }, + "PCIE_BOT.PCIE_IMUX2_L_15->PCIE_TRNTDLLPDATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA1" + }, + "PCIE_BOT.PCIE_IMUX15_R_7->PCIE_CFGERRAERHEADERLOG43": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG43" + }, + "PCIE_BOT.PCIE_IMUX10_L_15->PCIE_CFGDSN39": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN39" + }, + "PCIE_BOT.PCIE_IMUX5_L_9->PCIE_CFGERRAERHEADERLOG111": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG111" + }, + "PCIE_BOT.PCIE_PLTXPMSTATE2->PCIE_LOGIC_OUTS_B19_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLTXPMSTATE2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_0" + }, + "PCIE_BOT.PCIE_IMUX32_R_4->PCIE_PIPERX7DATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA11" + }, + "PCIE_BOT.PCIE_MIMTXWDATA39->PCIE_LOGIC_OUTS_B21_R_2": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_2" + }, + "PCIE_BOT.PCIE_MIMTXWDATA2->PCIE_LOGIC_OUTS_B12_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_5" + }, + "PCIE_BOT.PCIE_IMUX18_L_0->PCIE_CFGPORTNUMBER5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX18_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER5" + }, + "PCIE_BOT.PCIE_MIMRXWDATA46->PCIE_LOGIC_OUTS_B23_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_16" + }, + "PCIE_BOT.PCIE_IMUX35_L_9->PCIE_PIPERX1DATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA6" + }, + "PCIE_BOT.PCIE_IMUX12_R_12->PCIE_CFGERRAERHEADERLOG25": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG25" + }, + "PCIE_BOT.PCIE_IMUX16_L_15->PCIE_PIPERX2CHARISK1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2CHARISK1" + }, + "PCIE_BOT.PCIE_MIMTXWADDR3->PCIE_LOGIC_OUTS_B23_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_5" + }, + "PCIE_BOT.PCIE_TRNFCPH3->PCIE_LOGIC_OUTS_B3_R_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPH3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_5" + }, + "PCIE_BOT.PCIE_TRNFCCPLD5->PCIE_LOGIC_OUTS_B4_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_10" + }, + "PCIE_BOT.PCIE_IMUX34_L_5->PCIE_PIPERX3DATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA7" + }, + "PCIE_BOT.PCIE_MIMTXRADDR9->PCIE_LOGIC_OUTS_B3_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_4" + }, + "PCIE_BOT.PCIE_IMUX38_L_18->PCIE_PIPERX0DATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA13" + }, + "PCIE_BOT.PCIE_CFGMSGDATA5->PCIE_LOGIC_OUTS_B18_L_11": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_11" + }, + "PCIE_BOT.PCIE_PIPETX3ELECIDLE->PCIE_LOGIC_OUTS_B3_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3ELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_2" + }, + "PCIE_BOT.PCIE_MIMRXWADDR8->PCIE_LOGIC_OUTS_B8_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWADDR8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_16" + }, + "PCIE_BOT.PCIE_IMUX11_L_11->PCIE_CFGDSN24": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN24" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA2->PCIE_LOGIC_OUTS_B6_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_12" + }, + "PCIE_BOT.PCIE_IMUX14_R_6->PCIE_CFGERRAERHEADERLOG47": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG47" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLEXTTAGEN->PCIE_LOGIC_OUTS_B17_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLEXTTAGEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_15" + }, + "PCIE_BOT.PCIE_IMUX4_L_4->PCIE_CFGERRAERHEADERLOG90": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG90" + }, + "PCIE_BOT.PCIE_IMUX5_L_0->PCIE_PLDIRECTEDLINKAUTON": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKAUTON" + }, + "PCIE_BOT.PCIE_IMUX33_R_16->PCIE_PIPERX6CHANISALIGNED": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6CHANISALIGNED" + }, + "PCIE_BOT.PCIE_IMUX35_R_3->PCIE_PIPERX7DATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA14" + }, + "PCIE_BOT.PCIE_TRNRBARHIT1->PCIE_LOGIC_OUTS_B1_R_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNRBARHIT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_9" + }, + "PCIE_BOT.PCIE_CLK0_R_12->PCIE_USERCLK": { + "can_invert": "0", + "src_wire": "PCIE_CLK0_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_USERCLK" + }, + "PCIE_BOT.PCIE_DBGVECB50->PCIE_LOGIC_OUTS_B21_L_3": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_3" + }, + "PCIE_BOT.PCIE_TRNRD123->PCIE_LOGIC_OUTS_B10_R_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD123", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_13" + }, + "PCIE_BOT.PCIE_IMUX8_L_13->PCIE_CFGDSN29": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN29" + }, + "PCIE_BOT.PCIE_DRPDO9->PCIE_LOGIC_OUTS_B22_L_19": { + "can_invert": "0", + "src_wire": "PCIE_DRPDO9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_19" + }, + "PCIE_BOT.PCIE_MIMTXWDATA10->PCIE_LOGIC_OUTS_B23_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_6" + }, + "PCIE_BOT.PCIE_IMUX1_L_18->PCIE_TRNTDLLPDATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA12" + }, + "PCIE_BOT.PCIE_IMUX7_L_10->PCIE_CFGERRAERHEADERLOG117": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG117" + }, + "PCIE_BOT.PCIE_IMUX15_L_1->PCIE_CFGREVID3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID3" + }, + "PCIE_BOT.PCIE_IMUX9_L_6->PCIE_CFGDSN2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN2" + }, + "PCIE_BOT.PCIE_IMUX15_R_18->PCIE_TRNTD45": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD45" + }, + "PCIE_BOT.PCIE_IMUX0_L_13->PCIE_TRNTSTR": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTSTR" + }, + "PCIE_BOT.PCIE_CFGMSGDATA2->PCIE_LOGIC_OUTS_B14_L_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_10" + }, + "PCIE_BOT.PCIE_PLDBGVEC7->PCIE_LOGIC_OUTS_B23_L_18": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_18" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA9->PCIE_LOGIC_OUTS_B7_L_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_14" + }, + "PCIE_BOT.PCIE_IMUX34_L_7->PCIE_PIPERX1DATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA15" + }, + "PCIE_BOT.PCIE_DBGVECB2->PCIE_LOGIC_OUTS_B22_R_9": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_9" + }, + "PCIE_BOT.PCIE_PIPETX4DATA14->PCIE_LOGIC_OUTS_B2_R_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_15" + }, + "PCIE_BOT.PCIE_MIMRXWADDR10->PCIE_LOGIC_OUTS_B12_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWADDR10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_16" + }, + "PCIE_BOT.PCIE_DBGVECB52->PCIE_LOGIC_OUTS_B19_L_4": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB52", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_4" + }, + "PCIE_BOT.PCIE_IMUX5_L_16->PCIE_CFGERRTLPCPLHEADER11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER11" + }, + "PCIE_BOT.PCIE_IMUX34_R_9->PCIE_PIPERX5DATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA7" + }, + "PCIE_BOT.PCIE_IMUX36_R_10->PCIE_PIPERX5DATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA1" + }, + "PCIE_BOT.PCIE_PIPERX4POLARITY->PCIE_LOGIC_OUTS_B1_R_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPERX4POLARITY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_18" + }, + "PCIE_BOT.PCIE_CFGMGMTDO11->PCIE_LOGIC_OUTS_B17_R_13": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_13" + }, + "PCIE_BOT.PCIE_IMUX35_L_5->PCIE_PIPERX3DATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA6" + }, + "PCIE_BOT.PCIE_TRNFCCPLD6->PCIE_LOGIC_OUTS_B5_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_10" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA15->PCIE_LOGIC_OUTS_B11_L_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_15" + }, + "PCIE_BOT.PCIE_CTRL0_R_2->PCIE_TLRSTN": { + "can_invert": "0", + "src_wire": "PCIE_CTRL0_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TLRSTN" + }, + "PCIE_BOT.PCIE_IMUX39_R_7->PCIE_PIPERX5DATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA12" + }, + "PCIE_BOT.PCIE_CLK1_R_11->PCIE_DRPCLK": { + "can_invert": "0", + "src_wire": "PCIE_CLK1_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPCLK" + }, + "PCIE_BOT.PCIE_DBGVECC7->PCIE_LOGIC_OUTS_B18_L_9": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_9" + }, + "PCIE_BOT.PCIE_IMUX35_R_4->PCIE_PIPERX7STATUS2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7STATUS2" + }, + "PCIE_BOT.PCIE_DBGVECA34->PCIE_LOGIC_OUTS_B10_R_15": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_15" + }, + "PCIE_BOT.PCIE_TL2ERRHDR53->PCIE_LOGIC_OUTS_B10_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_10" + }, + "PCIE_BOT.PCIE_PIPETX1CHARISK1->PCIE_LOGIC_OUTS_B16_L_4": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1CHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_4" + }, + "PCIE_BOT.PCIE_MIMRXRADDR3->PCIE_LOGIC_OUTS_B16_R_18": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXRADDR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_18" + }, + "PCIE_BOT.PCIE_PIPETX5ELECIDLE->PCIE_LOGIC_OUTS_B3_R_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5ELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_6" + }, + "PCIE_BOT.PCIE_TRNRD112->PCIE_LOGIC_OUTS_B3_R_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD112", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_15" + }, + "PCIE_BOT.PCIE_DBGVECA53->PCIE_LOGIC_OUTS_B21_R_11": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_11" + }, + "PCIE_BOT.PCIE_IMUX20_R_11->PCIE_CFGVENDID13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID13" + }, + "PCIE_BOT.PCIE_TRNFCNPD7->PCIE_LOGIC_OUTS_B6_L_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_5" + }, + "PCIE_BOT.PCIE_MIMTXWDATA54->PCIE_LOGIC_OUTS_B13_R_0": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA54", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_0" + }, + "PCIE_BOT.PCIE_IMUX0_R_0->PCIE_MIMTXRDATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA0" + }, + "PCIE_BOT.PCIE_IMUX35_R_5->PCIE_PIPERX7DATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7DATA6" + }, + "PCIE_BOT.PCIE_IMUX1_R_7->PCIE_MIMTXRDATA29": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA29" + }, + "PCIE_BOT.PCIE_IMUX4_L_13->PCIE_CFGERRAERHEADERLOG126": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG126" + }, + "PCIE_BOT.PCIE_IMUX3_L_0->PCIE_PLDIRECTEDLINKWIDTH1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLINKWIDTH1" + }, + "PCIE_BOT.PCIE_IMUX13_L_17->PCIE_DRPADDR0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR0" + }, + "PCIE_BOT.PCIE_PIPETX5CHARISK0->PCIE_LOGIC_OUTS_B16_R_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5CHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_6" + }, + "PCIE_BOT.PCIE_IMUX3_R_14->PCIE_TRNTD61": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD61" + }, + "PCIE_BOT.PCIE_PLLINKGEN2CAP->PCIE_LOGIC_OUTS_B3_L_1": { + "can_invert": "0", + "src_wire": "PCIE_PLLINKGEN2CAP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_1" + }, + "PCIE_BOT.PCIE_PIPETX4DATA2->PCIE_LOGIC_OUTS_B11_R_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_18" + }, + "PCIE_BOT.PCIE_IMUX8_R_12->PCIE_CFGMGMTDWADDR6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDWADDR6" + }, + "PCIE_BOT.PCIE_TL2ERRHDR31->PCIE_LOGIC_OUTS_B14_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_4" + }, + "PCIE_BOT.PCIE_IMUX9_L_4->PCIE_CFGTRNPENDINGN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGTRNPENDINGN" + }, + "PCIE_BOT.PCIE_IMUX12_R_2->PCIE_PLTRANSMITHOTRST": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLTRANSMITHOTRST" + }, + "PCIE_BOT.PCIE_PIPETX3DATA4->PCIE_LOGIC_OUTS_B0_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_2" + }, + "PCIE_BOT.PCIE_TL2ERRHDR49->PCIE_LOGIC_OUTS_B10_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR49", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_9" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTA->PCIE_LOGIC_OUTS_B12_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTA", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_16" + }, + "PCIE_BOT.PCIE_TRNRD124->PCIE_LOGIC_OUTS_B0_R_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD124", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_12" + }, + "PCIE_BOT.PCIE_PIPETX4POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4POWERDOWN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_17" + }, + "PCIE_BOT.PCIE_IMUX9_L_18->PCIE_CFGDSN50": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN50" + }, + "PCIE_BOT.PCIE_IMUX8_R_5->PCIE_CFGMGMTDI12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI12" + }, + "PCIE_BOT.PCIE_IMUX10_R_11->PCIE_CFGERRAERHEADERLOG27": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG27" + }, + "PCIE_BOT.PCIE_IMUX17_R_12->PCIE_CFGVENDID6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID6" + }, + "PCIE_BOT.PCIE_PIPERX2POLARITY->PCIE_LOGIC_OUTS_B1_L_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPERX2POLARITY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_14" + }, + "PCIE_BOT.PCIE_IMUX5_R_6->PCIE_MIMTXRDATA45": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA45" + }, + "PCIE_BOT.PCIE_IMUX4_L_7->PCIE_CFGERRAERHEADERLOG102": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG102" + }, + "PCIE_BOT.PCIE_IMUX10_R_3->PCIE_CFGMGMTDI4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI4" + }, + "PCIE_BOT.PCIE_IMUX33_L_10->PCIE_PIPERX1DATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA2" + }, + "PCIE_BOT.PCIE_TRNFCCPLH5->PCIE_LOGIC_OUTS_B4_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLH5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_8" + }, + "PCIE_BOT.PCIE_IMUX35_L_3->PCIE_PIPERX3DATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA14" + }, + "PCIE_BOT.PCIE_IMUX2_R_13->PCIE_TRNTD64": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD64" + }, + "PCIE_BOT.PCIE_CFGMGMTDO5->PCIE_LOGIC_OUTS_B15_R_11": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_11" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS3->PCIE_LOGIC_OUTS_B4_R_16": { + "can_invert": "0", + "src_wire": "PCIE_LL2LINKSTATUS3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_16" + }, + "PCIE_BOT.PCIE_TRNRBARHIT4->PCIE_LOGIC_OUTS_B1_R_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNRBARHIT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_8" + }, + "PCIE_BOT.PCIE_IMUX2_L_13->PCIE_TRNRDSTRDY": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNRDSTRDY" + }, + "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRCORRERREN->PCIE_LOGIC_OUTS_B20_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGROOTCONTROLSYSERRCORRERREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_16" + }, + "PCIE_BOT.PCIE_TRNRD7->PCIE_LOGIC_OUTS_B0_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_7" + }, + "PCIE_BOT.PCIE_IMUX11_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM3" + }, + "PCIE_BOT.PCIE_TL2ERRHDR13->PCIE_LOGIC_OUTS_B11_R_9": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_9" + }, + "PCIE_BOT.PCIE_CFGMGMTDO7->PCIE_LOGIC_OUTS_B10_R_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_12" + }, + "PCIE_BOT.PCIE_IMUX36_L_10->PCIE_PIPERX1DATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA1" + }, + "PCIE_BOT.PCIE_IMUX5_R_17->PCIE_MIMRXRDATA65": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA65" + }, + "PCIE_BOT.PCIE_PIPETX7DATA11->PCIE_LOGIC_OUTS_B15_R_1": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_1" + }, + "PCIE_BOT.PCIE_MIMTXWDATA41->PCIE_LOGIC_OUTS_B18_R_3": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_3" + }, + "PCIE_BOT.PCIE_MIMTXRADDR3->PCIE_LOGIC_OUTS_B10_R_2": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_2" + }, + "PCIE_BOT.PCIE_IMUX37_R_16->PCIE_PIPERX6PHYSTATUS": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6PHYSTATUS" + }, + "PCIE_BOT.PCIE_IMUX20_R_1->PCIE_CFGVENDID14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID14" + }, + "PCIE_BOT.PCIE_CFGMGMTDO15->PCIE_LOGIC_OUTS_B17_R_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_14" + }, + "PCIE_BOT.PCIE_IMUX36_R_17->PCIE_PIPERX6DATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA1" + }, + "PCIE_BOT.PCIE_DBGSCLRD->PCIE_LOGIC_OUTS_B19_L_11": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRD", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_11" + }, + "PCIE_BOT.PCIE_IMUX8_L_2->PCIE_CFGPMFORCESTATE1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMFORCESTATE1" + }, + "PCIE_BOT.PCIE_PIPETX4DATA8->PCIE_LOGIC_OUTS_B9_R_16": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_16" + }, + "PCIE_BOT.PCIE_TRNTDSTRDY1->PCIE_LOGIC_OUTS_B1_R_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNTDSTRDY1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_15" + }, + "PCIE_BOT.PCIE_IMUX3_R_16->PCIE_MIMRXRDATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA7" + }, + "PCIE_BOT.PCIE_IMUX3_R_15->PCIE_MIMRXRDATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA3" + }, + "PCIE_BOT.PCIE_PIPETX1DATA12->PCIE_LOGIC_OUTS_B0_L_4": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_4" + }, + "PCIE_BOT.PCIE_IMUX33_L_6->PCIE_PIPERX3DATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA2" + }, + "PCIE_BOT.PCIE_IMUX14_R_16->PCIE_CFGERRAERHEADERLOG13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG13" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSCURRENTSPEED0->PCIE_LOGIC_OUTS_B19_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSCURRENTSPEED0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_16" + }, + "PCIE_BOT.PCIE_TL2ERRHDR52->PCIE_LOGIC_OUTS_B9_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR52", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_10" + }, + "PCIE_BOT.PCIE_IMUX6_R_3->PCIE_MIMTXRDATA52": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA52" + }, + "PCIE_BOT.PCIE_IMUX6_R_6->PCIE_MIMTXRDATA46": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA46" + }, + "PCIE_BOT.PCIE_CFGMGMTDO13->PCIE_LOGIC_OUTS_B14_R_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_14" + }, + "PCIE_BOT.PCIE_TL2ERRHDR29->PCIE_LOGIC_OUTS_B12_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_4" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE0->PCIE_LOGIC_OUTS_B16_R_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTMMENABLE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_10" + }, + "PCIE_BOT.PCIE_DBGSCLRH->PCIE_LOGIC_OUTS_B22_L_12": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_12" + }, + "PCIE_BOT.PCIE_TRNFCCPLD2->PCIE_LOGIC_OUTS_B5_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_9" + }, + "PCIE_BOT.PCIE_IMUX3_R_3->PCIE_MIMTXRDATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA15" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVED->PCIE_LOGIC_OUTS_B15_L_9": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_9" + }, + "PCIE_BOT.PCIE_IMUX5_L_18->PCIE_CFGERRTLPCPLHEADER19": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER19" + }, + "PCIE_BOT.PCIE_IMUX37_R_15->PCIE_PIPERX6DATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA8" + }, + "PCIE_BOT.PCIE_TRNRD110->PCIE_LOGIC_OUTS_B0_R_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD110", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_16" + }, + "PCIE_BOT.PCIE_IMUX1_L_16->PCIE_TRNTDLLPDATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA4" + }, + "PCIE_BOT.PCIE_CLK0_R_11->PCIE_PIPECLK": { + "can_invert": "0", + "src_wire": "PCIE_CLK0_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPECLK" + }, + "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRNONFATALERREN->PCIE_LOGIC_OUTS_B21_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_16" + }, + "PCIE_BOT.PCIE_IMUX16_L_4->PCIE_PIPERX3CHARISK1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3CHARISK1" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA28->PCIE_LOGIC_OUTS_B4_L_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_19" + }, + "PCIE_BOT.PCIE_MIMTXWADDR4->PCIE_LOGIC_OUTS_B10_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_4" + }, + "PCIE_BOT.PCIE_IMUX6_L_15->PCIE_CFGERRTLPCPLHEADER8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER8" + }, + "PCIE_BOT.PCIE_MIMRXWDATA18->PCIE_LOGIC_OUTS_B2_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_19" + }, + "PCIE_BOT.PCIE_MIMRXRADDR5->PCIE_LOGIC_OUTS_B8_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXRADDR5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_19" + }, + "PCIE_BOT.PCIE_TL2ERRHDR28->PCIE_LOGIC_OUTS_B17_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_3" + }, + "PCIE_BOT.PCIE_IMUX6_R_4->PCIE_CFGMGMTDI9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI9" + }, + "PCIE_BOT.PCIE_IMUX19_R_13->PCIE_CFGVENDID4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX19_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID4" + }, + "PCIE_BOT.PCIE_PIPETX5DATA8->PCIE_LOGIC_OUTS_B9_R_5": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_5" + }, + "PCIE_BOT.PCIE_IMUX14_L_2->PCIE_CFGREVID6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGREVID6" + }, + "PCIE_BOT.PCIE_TL2ERRHDR50->PCIE_LOGIC_OUTS_B11_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_9" + }, + "PCIE_BOT.PCIE_IMUX38_L_8->PCIE_PIPERX1STATUS1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1STATUS1" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA4->PCIE_LOGIC_OUTS_B11_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_13" + }, + "PCIE_BOT.PCIE_TRNRD55->PCIE_LOGIC_OUTS_B0_L_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_19" + }, + "PCIE_BOT.PCIE_IMUX12_R_0->PCIE_CFGERRAERHEADERLOG70": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG70" + }, + "PCIE_BOT.PCIE_CFGMSGDATA14->PCIE_LOGIC_OUTS_B12_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_15" + }, + "PCIE_BOT.PCIE_MIMTXWDATA60->PCIE_LOGIC_OUTS_B12_R_1": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_1" + }, + "PCIE_BOT.PCIE_IMUX8_R_13->PCIE_CFGMGMTWRRW1CASRWN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTWRRW1CASRWN" + }, + "PCIE_BOT.PCIE_PIPETX1DATA6->PCIE_LOGIC_OUTS_B2_L_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_6" + }, + "PCIE_BOT.PCIE_IMUX32_R_10->PCIE_PIPERX5DATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA3" + }, + "PCIE_BOT.PCIE_PIPETX6DATA13->PCIE_LOGIC_OUTS_B4_R_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_11" + }, + "PCIE_BOT.PCIE_IMUX37_R_19->PCIE_PIPERX4DATA8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA8" + }, + "PCIE_BOT.PCIE_CFGMGMTDO0->PCIE_LOGIC_OUTS_B11_R_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_10" + }, + "PCIE_BOT.PCIE_MIMTXWDATA8->PCIE_LOGIC_OUTS_B22_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_6" + }, + "PCIE_BOT.PCIE_TL2ERRRXOVERFLOW->PCIE_LOGIC_OUTS_B18_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRRXOVERFLOW", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_13" + }, + "PCIE_BOT.PCIE_TRNFCPH6->PCIE_LOGIC_OUTS_B0_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPH6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_3" + }, + "PCIE_BOT.PCIE_CFGERRCPLRDYN->PCIE_LOGIC_OUTS_B14_R_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGERRCPLRDYN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_10" + }, + "PCIE_BOT.PCIE_TRNFCCPLD8->PCIE_LOGIC_OUTS_B7_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_10" + }, + "PCIE_BOT.PCIE_IMUX9_R_1->PCIE_TRNTD84": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD84" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2->PCIE_LOGIC_OUTS_B19_L_18": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_18" + }, + "PCIE_BOT.PCIE_IMUX6_R_14->PCIE_CFGMGMTWRENN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTWRENN" + }, + "PCIE_BOT.PCIE_IMUX1_R_15->PCIE_MIMRXRDATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA1" + }, + "PCIE_BOT.PCIE_MIMTXWDATA9->PCIE_LOGIC_OUTS_B21_R_8": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_8" + }, + "PCIE_BOT.PCIE_PIPETX2POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2POWERDOWN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_13" + }, + "PCIE_BOT.PCIE_IMUX2_R_3->PCIE_MIMTXRDATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA14" + }, + "PCIE_BOT.PCIE_TRNTBUFAV2->PCIE_LOGIC_OUTS_B1_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TRNTBUFAV2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_4" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS0->PCIE_LOGIC_OUTS_B15_R_17": { + "can_invert": "0", + "src_wire": "PCIE_LL2LINKSTATUS0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_17" + }, + "PCIE_BOT.PCIE_IMUX6_R_1->PCIE_MIMTXRDATA60": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA60" + }, + "PCIE_BOT.PCIE_MIMTXWDATA57->PCIE_LOGIC_OUTS_B9_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_4" + }, + "PCIE_BOT.PCIE_TRNRBARHIT0->PCIE_LOGIC_OUTS_B0_R_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNRBARHIT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_9" + }, + "PCIE_BOT.PCIE_TRNREOF->PCIE_LOGIC_OUTS_B7_R_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNREOF", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_11" + }, + "PCIE_BOT.PCIE_IMUX3_L_12->PCIE_TRNTECRCGEN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTECRCGEN" + }, + "PCIE_BOT.PCIE_MIMTXWDATA34->PCIE_LOGIC_OUTS_B15_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_6" + }, + "PCIE_BOT.PCIE_IMUX11_L_4->PCIE_CFGFORCEMPS1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCEMPS1" + }, + "PCIE_BOT.PCIE_IMUX15_L_18->PCIE_DRPADDR6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR6" + }, + "PCIE_BOT.PCIE_PIPETX6DATA3->PCIE_LOGIC_OUTS_B15_R_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_14" + }, + "PCIE_BOT.PCIE_DBGVECA63->PCIE_LOGIC_OUTS_B15_R_8": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_8" + }, + "PCIE_BOT.PCIE_TL2ERRHDR11->PCIE_LOGIC_OUTS_B9_R_9": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_9" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA11->PCIE_LOGIC_OUTS_B10_L_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_14" + }, + "PCIE_BOT.PCIE_IMUX34_L_19->PCIE_PIPERX0ELECIDLE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0ELECIDLE" + }, + "PCIE_BOT.PCIE_MIMTXWDATA11->PCIE_LOGIC_OUTS_B18_R_9": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_9" + }, + "PCIE_BOT.PCIE_MIMTXWDATA22->PCIE_LOGIC_OUTS_B17_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_6" + }, + "PCIE_BOT.PCIE_TL2ERRHDR32->PCIE_LOGIC_OUTS_B15_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_4" + }, + "PCIE_BOT.PCIE_IMUX8_L_6->PCIE_CFGDSN1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN1" + }, + "PCIE_BOT.PCIE_PIPETX6DATA4->PCIE_LOGIC_OUTS_B0_R_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_13" + }, + "PCIE_BOT.PCIE_MIMRXWDATA55->PCIE_LOGIC_OUTS_B12_R_18": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_18" + }, + "PCIE_BOT.PCIE_IMUX33_L_15->PCIE_PIPERX2DATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2DATA10" + }, + "PCIE_BOT.PCIE_PIPETX6ELECIDLE->PCIE_LOGIC_OUTS_B3_R_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6ELECIDLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_13" + }, + "PCIE_BOT.PCIE_PLDBGVEC1->PCIE_LOGIC_OUTS_B23_L_14": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_14" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO1->PCIE_LOGIC_OUTS_B12_L_8": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_8" + }, + "PCIE_BOT.PCIE_MIMTXWDATA29->PCIE_LOGIC_OUTS_B2_R_10": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_10" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMSIXFM->PCIE_LOGIC_OUTS_B16_L_5": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTMSIXFM", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_5" + }, + "PCIE_BOT.PCIE_IMUX1_R_12->PCIE_TRNTD67": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD67" + }, + "PCIE_BOT.PCIE_MIMTXWDATA24->PCIE_LOGIC_OUTS_B18_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_6" + }, + "PCIE_BOT.PCIE_CTRL1_R_1->PCIE_FUNCLVLRSTN": { + "can_invert": "0", + "src_wire": "PCIE_CTRL1_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_FUNCLVLRSTN" + }, + "PCIE_BOT.PCIE_MIMTXWDATA58->PCIE_LOGIC_OUTS_B17_R_0": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA58", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_0" + }, + "PCIE_BOT.PCIE_CFGMSGDATA3->PCIE_LOGIC_OUTS_B15_L_10": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_10" + }, + "PCIE_BOT.PCIE_DBGVECA38->PCIE_LOGIC_OUTS_B19_R_14": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_14" + }, + "PCIE_BOT.PCIE_TRNRBARHIT3->PCIE_LOGIC_OUTS_B3_R_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNRBARHIT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_9" + }, + "PCIE_BOT.PCIE_IMUX1_R_4->PCIE_MIMTXRDATA17": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA17" + }, + "PCIE_BOT.PCIE_IMUX34_R_4->PCIE_PIPERX7ELECIDLE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7ELECIDLE" + }, + "PCIE_BOT.PCIE_PIPETXRATE->PCIE_LOGIC_OUTS_B19_R_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETXRATE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_11" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ0->PCIE_LOGIC_OUTS_B16_L_16": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_16" + }, + "PCIE_BOT.PCIE_PLDBGVEC5->PCIE_LOGIC_OUTS_B22_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_17" + }, + "PCIE_BOT.PCIE_MIMTXWADDR5->PCIE_LOGIC_OUTS_B14_R_3": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_3" + }, + "PCIE_BOT.PCIE_IMUX11_R_2->PCIE_TRNTD82": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD82" + }, + "PCIE_BOT.PCIE_IMUX6_L_6->PCIE_CFGERRAERHEADERLOG100": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG100" + }, + "PCIE_BOT.PCIE_IMUX11_L_6->PCIE_CFGDSN4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN4" + }, + "PCIE_BOT.PCIE_TRNTBUFAV3->PCIE_LOGIC_OUTS_B3_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TRNTBUFAV3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4" + }, + "PCIE_BOT.PCIE_IMUX12_R_7->PCIE_CFGMGMTDI21": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI21" + }, + "PCIE_BOT.PCIE_IMUX38_R_4->PCIE_PIPERX7STATUS1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX7STATUS1" + }, + "PCIE_BOT.PCIE_IMUX13_R_3->PCIE_CFGERRAERHEADERLOG58": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG58" + }, + "PCIE_BOT.PCIE_IMUX12_R_13->PCIE_CFGERRAERHEADERLOG21": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG21" + }, + "PCIE_BOT.PCIE_IMUX1_R_14->PCIE_TRNTD59": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD59" + }, + "PCIE_BOT.PCIE_IMUX34_L_18->PCIE_PIPERX0DATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA15" + }, + "PCIE_BOT.PCIE_LL2LINKSTATUS4->PCIE_LOGIC_OUTS_B20_R_16": { + "can_invert": "0", + "src_wire": "PCIE_LL2LINKSTATUS4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_16" + }, + "PCIE_BOT.PCIE_IMUX34_R_7->PCIE_PIPERX5DATA15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA15" + }, + "PCIE_BOT.PCIE_IMUX7_R_6->PCIE_MIMTXRDATA47": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA47" + }, + "PCIE_BOT.PCIE_IMUX32_R_19->PCIE_PIPERX4DATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA11" + }, + "PCIE_BOT.PCIE_TRNRD33->PCIE_LOGIC_OUTS_B9_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_13" + }, + "PCIE_BOT.PCIE_IMUX10_L_7->PCIE_CFGDSN7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN7" + }, + "PCIE_BOT.PCIE_TRNRD15->PCIE_LOGIC_OUTS_B0_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_9" + }, + "PCIE_BOT.PCIE_IMUX10_R_19->PCIE_TRNTD6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD6" + }, + "PCIE_BOT.PCIE_IMUX17_R_14->PCIE_CFGVENDID1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGVENDID1" + }, + "PCIE_BOT.PCIE_TRNRD100->PCIE_LOGIC_OUTS_B3_R_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD100", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_19" + }, + "PCIE_BOT.PCIE_PIPETX4DATA5->PCIE_LOGIC_OUTS_B4_R_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_17" + }, + "PCIE_BOT.PCIE_IMUX11_L_5->PCIE_CFGDSN0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN0" + }, + "PCIE_BOT.PCIE_TRNFCPD1->PCIE_LOGIC_OUTS_B8_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_2" + }, + "PCIE_BOT.PCIE_TRNRD57->PCIE_LOGIC_OUTS_B2_L_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_19" + }, + "PCIE_BOT.PCIE_IMUX7_L_15->PCIE_CFGERRTLPCPLHEADER9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER9" + }, + "PCIE_BOT.PCIE_TL2ERRMALFORMED->PCIE_LOGIC_OUTS_B17_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRMALFORMED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_13" + }, + "PCIE_BOT.PCIE_IMUX13_L_11->PCIE_CFGSUBSYSVENDID5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID5" + }, + "PCIE_BOT.PCIE_IMUX6_L_18->PCIE_CFGERRTLPCPLHEADER20": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER20" + }, + "PCIE_BOT.PCIE_IMUX5_L_10->PCIE_CFGERRAERHEADERLOG115": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG115" + }, + "PCIE_BOT.PCIE_IMUX5_R_19->PCIE_MIMRXRDATA57": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA57" + }, + "PCIE_BOT.PCIE_IMUX0_L_1->PCIE_PLDIRECTEDLTSSMNEW4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PLDIRECTEDLTSSMNEW4" + }, + "PCIE_BOT.PCIE_DBGVECB55->PCIE_LOGIC_OUTS_B18_L_5": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_5" + }, + "PCIE_BOT.PCIE_IMUX8_L_4->PCIE_CFGPCIECAPINTERRUPTMSGNUM4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM4" + }, + "PCIE_BOT.PCIE_IMUX8_R_14->PCIE_CFGERRMALFORMEDN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRMALFORMEDN" + }, + "PCIE_BOT.PCIE_IMUX0_L_17->PCIE_TRNTDLLPDATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTDLLPDATA7" + }, + "PCIE_BOT.PCIE_IMUX5_R_3->PCIE_MIMTXRDATA51": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA51" + }, + "PCIE_BOT.PCIE_MIMRXWDATA59->PCIE_LOGIC_OUTS_B14_R_18": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA59", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_18" + }, + "PCIE_BOT.PCIE_IMUX3_L_8->PCIE_TRNTD119": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD119" + }, + "PCIE_BOT.PCIE_TRNRD16->PCIE_LOGIC_OUTS_B1_L_9": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_9" + }, + "PCIE_BOT.PCIE_IMUX10_R_6->PCIE_CFGMGMTDI16": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI16" + }, + "PCIE_BOT.PCIE_IMUX3_L_13->PCIE_TRNRNPREQ": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNRNPREQ" + }, + "PCIE_BOT.PCIE_IMUX4_L_18->PCIE_CFGERRTLPCPLHEADER18": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER18" + }, + "PCIE_BOT.PCIE_IMUX15_L_6->PCIE_CFGSUBSYSID9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID9" + }, + "PCIE_BOT.PCIE_IMUX4_R_16->PCIE_TRNTD50": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD50" + }, + "PCIE_BOT.PCIE_IMUX9_L_16->PCIE_CFGDSN42": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN42" + }, + "PCIE_BOT.PCIE_MIMTXREN->PCIE_LOGIC_OUTS_B8_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_6" + }, + "PCIE_BOT.PCIE_IMUX32_L_10->PCIE_PIPERX1DATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1DATA3" + }, + "PCIE_BOT.PCIE_IMUX0_R_19->PCIE_MIMRXRDATA16": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA16" + }, + "PCIE_BOT.PCIE_DBGVECA54->PCIE_LOGIC_OUTS_B18_R_10": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA54", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_10" + }, + "PCIE_BOT.PCIE_PLDBGVEC3->PCIE_LOGIC_OUTS_B22_L_16": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_16" + }, + "PCIE_BOT.PCIE_MIMTXWDATA15->PCIE_LOGIC_OUTS_B16_R_9": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_9" + }, + "PCIE_BOT.PCIE_CFGERRAERHEADERLOGSETN->PCIE_LOGIC_OUTS_B17_R_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGERRAERHEADERLOGSETN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_12" + }, + "PCIE_BOT.PCIE_IMUX35_R_18->PCIE_PIPERX4DATA14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA14" + }, + "PCIE_BOT.PCIE_IMUX8_L_11->PCIE_CFGDSN21": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN21" + }, + "PCIE_BOT.PCIE_DBGVECC8->PCIE_LOGIC_OUTS_B19_L_9": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_9" + }, + "PCIE_BOT.PCIE_TRNRSRCRDY->PCIE_LOGIC_OUTS_B0_R_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNRSRCRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_10" + }, + "PCIE_BOT.PCIE_PIPETX6DATA8->PCIE_LOGIC_OUTS_B9_R_12": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_12" + }, + "PCIE_BOT.PCIE_IMUX8_L_7->PCIE_CFGDSN5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN5" + }, + "PCIE_BOT.PCIE_IMUX16_R_17->PCIE_PIPERX6CHARISK0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6CHARISK0" + }, + "PCIE_BOT.PCIE_IMUX5_L_4->PCIE_CFGERRAERHEADERLOG91": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG91" + }, + "PCIE_BOT.PCIE_TRNFCPD3->PCIE_LOGIC_OUTS_B1_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_1" + }, + "PCIE_BOT.PCIE_TRNRD29->PCIE_LOGIC_OUTS_B2_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_12" + }, + "PCIE_BOT.PCIE_TRNFCPD7->PCIE_LOGIC_OUTS_B7_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_0" + }, + "PCIE_BOT.PCIE_IMUX15_L_10->PCIE_CFGSUBSYSVENDID3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID3" + }, + "PCIE_BOT.PCIE_IMUX32_L_19->PCIE_PIPERX0DATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA11" + }, + "PCIE_BOT.PCIE_IMUX34_R_16->PCIE_PIPERX6DATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA7" + }, + "PCIE_BOT.PCIE_PIPETX3POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3POWERDOWN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_2" + }, + "PCIE_BOT.PCIE_IMUX7_R_1->PCIE_MIMTXRDATA61": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA61" + }, + "PCIE_BOT.PCIE_IMUX2_L_8->PCIE_TRNTD118": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD118" + }, + "PCIE_BOT.PCIE_IMUX11_L_15->PCIE_CFGDSN40": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN40" + }, + "PCIE_BOT.PCIE_IMUX1_R_8->PCIE_MIMTXRDATA33": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA33" + }, + "PCIE_BOT.PCIE_IMUX10_R_12->PCIE_CFGERRAERHEADERLOG23": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG23" + }, + "PCIE_BOT.PCIE_IMUX3_L_10->PCIE_TRNTD127": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD127" + }, + "PCIE_BOT.PCIE_IMUX4_R_17->PCIE_MIMRXRDATA64": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA64" + }, + "PCIE_BOT.PCIE_CFGMGMTDO3->PCIE_LOGIC_OUTS_B13_R_11": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_11" + }, + "PCIE_BOT.PCIE_PIPETX4DATA9->PCIE_LOGIC_OUTS_B13_R_16": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_16" + }, + "PCIE_BOT.PCIE_IMUX15_L_3->PCIE_CFGSUBSYSID3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID3" + }, + "PCIE_BOT.PCIE_IMUX5_R_10->PCIE_CFGMGMTDI31": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI31" + }, + "PCIE_BOT.PCIE_PLTXPMSTATE0->PCIE_LOGIC_OUTS_B17_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLTXPMSTATE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_0" + }, + "PCIE_BOT.PCIE_TRNRD122->PCIE_LOGIC_OUTS_B9_R_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD122", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_13" + }, + "PCIE_BOT.PCIE_TRNRD114->PCIE_LOGIC_OUTS_B7_R_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD114", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_15" + }, + "PCIE_BOT.PCIE_IMUX5_L_17->PCIE_CFGERRTLPCPLHEADER15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER15" + }, + "PCIE_BOT.PCIE_IMUX5_R_18->PCIE_MIMRXRDATA61": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA61" + }, + "PCIE_BOT.PCIE_PIPETX5POWERDOWN0->PCIE_LOGIC_OUTS_B1_R_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX5POWERDOWN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_6" + }, + "PCIE_BOT.PCIE_MIMTXWADDR2->PCIE_LOGIC_OUTS_B12_R_7": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWADDR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_7" + }, + "PCIE_BOT.PCIE_IMUX9_L_12->PCIE_CFGDSN26": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN26" + }, + "PCIE_BOT.PCIE_IMUX37_L_5->PCIE_PIPERX3PHYSTATUS": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3PHYSTATUS" + }, + "PCIE_BOT.PCIE_TRNTBUFAV0->PCIE_LOGIC_OUTS_B4_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TRNTBUFAV0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_3" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA29->PCIE_LOGIC_OUTS_B5_L_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_19" + }, + "PCIE_BOT.PCIE_DBGSCLRJ->PCIE_LOGIC_OUTS_B22_L_13": { + "can_invert": "0", + "src_wire": "PCIE_DBGSCLRJ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_13" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA7->PCIE_LOGIC_OUTS_B14_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_13" + }, + "PCIE_BOT.PCIE_PLLINKUPCFGCAP->PCIE_LOGIC_OUTS_B2_L_1": { + "can_invert": "0", + "src_wire": "PCIE_PLLINKUPCFGCAP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_1" + }, + "PCIE_BOT.PCIE_CFGLINKSTATUSLINKTRAINING->PCIE_LOGIC_OUTS_B21_L_18": { + "can_invert": "0", + "src_wire": "PCIE_CFGLINKSTATUSLINKTRAINING", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_18" + }, + "PCIE_BOT.PCIE_IMUX11_L_14->PCIE_CFGDSN36": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN36" + }, + "PCIE_BOT.PCIE_MIMTXWDATA61->PCIE_LOGIC_OUTS_B6_R_3": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_3" + }, + "PCIE_BOT.PCIE_DBGVECA37->PCIE_LOGIC_OUTS_B20_R_15": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_15" + }, + "PCIE_BOT.PCIE_TRNRBARHIT6->PCIE_LOGIC_OUTS_B3_R_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNRBARHIT6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_8" + }, + "PCIE_BOT.PCIE_TRNRD45->PCIE_LOGIC_OUTS_B2_L_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_16" + }, + "PCIE_BOT.PCIE_TRNFCPD2->PCIE_LOGIC_OUTS_B0_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPD2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_1" + }, + "PCIE_BOT.PCIE_IMUX6_L_12->PCIE_CFGERRAERHEADERLOG124": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG124" + }, + "PCIE_BOT.PCIE_TRNFCPH4->PCIE_LOGIC_OUTS_B4_R_5": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCPH4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_5" + }, + "PCIE_BOT.PCIE_IMUX5_L_11->PCIE_CFGERRAERHEADERLOG119": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG119" + }, + "PCIE_BOT.PCIE_IMUX12_L_11->PCIE_CFGSUBSYSVENDID4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID4" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLCORRERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_12" + }, + "PCIE_BOT.PCIE_IMUX2_R_6->PCIE_MIMTXRDATA26": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA26" + }, + "PCIE_BOT.PCIE_CFGMGMTDO6->PCIE_LOGIC_OUTS_B8_R_12": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_12" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA10->PCIE_LOGIC_OUTS_B8_L_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_14" + }, + "PCIE_BOT.PCIE_DRPDO10->PCIE_LOGIC_OUTS_B23_L_19": { + "can_invert": "0", + "src_wire": "PCIE_DRPDO10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_19" + }, + "PCIE_BOT.PCIE_IMUX8_L_5->PCIE_CFGFORCEMPS2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCEMPS2" + }, + "PCIE_BOT.PCIE_IMUX0_R_15->PCIE_MIMRXRDATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA0" + }, + "PCIE_BOT.PCIE_IMUX11_R_17->PCIE_TRNTD49": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD49" + }, + "PCIE_BOT.PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE->PCIE_LOGIC_OUTS_B22_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_15" + }, + "PCIE_BOT.PCIE_IMUX13_L_6->PCIE_CFGSUBSYSID7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID7" + }, + "PCIE_BOT.PCIE_IMUX13_R_12->PCIE_CFGINTERRUPTSTATN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTSTATN" + }, + "PCIE_BOT.PCIE_CFGMGMTDO14->PCIE_LOGIC_OUTS_B16_R_14": { + "can_invert": "0", + "src_wire": "PCIE_CFGMGMTDO14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_14" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTDO5->PCIE_LOGIC_OUTS_B12_L_9": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_9" + }, + "PCIE_BOT.PCIE_TRNRD49->PCIE_LOGIC_OUTS_B9_L_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD49", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_17" + }, + "PCIE_BOT.PCIE_TL2ERRHDR2->PCIE_LOGIC_OUTS_B8_R_11": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_11" + }, + "PCIE_BOT.PCIE_IMUX4_L_11->PCIE_CFGERRAERHEADERLOG118": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG118" + }, + "PCIE_BOT.PCIE_IMUX3_R_7->PCIE_MIMTXRDATA31": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA31" + }, + "PCIE_BOT.PCIE_PIPETX7DATA14->PCIE_LOGIC_OUTS_B2_R_0": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_0" + }, + "PCIE_BOT.PCIE_PLLANEREVERSALMODE0->PCIE_LOGIC_OUTS_B13_L_0": { + "can_invert": "0", + "src_wire": "PCIE_PLLANEREVERSALMODE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_0" + }, + "PCIE_BOT.PCIE_TRNRD19->PCIE_LOGIC_OUTS_B0_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_10" + }, + "PCIE_BOT.PCIE_IMUX32_L_6->PCIE_PIPERX3DATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA3" + }, + "PCIE_BOT.PCIE_MIMTXRADDR5->PCIE_LOGIC_OUTS_B19_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_6" + }, + "PCIE_BOT.PCIE_MIMTXWDATA32->PCIE_LOGIC_OUTS_B19_R_7": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_7" + }, + "PCIE_BOT.PCIE_IMUX34_L_4->PCIE_PIPERX3ELECIDLE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3ELECIDLE" + }, + "PCIE_BOT.PCIE_IMUX39_L_8->PCIE_PIPERX1STATUS0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1STATUS0" + }, + "PCIE_BOT.PCIE_IMUX10_R_17->PCIE_TRNTD48": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD48" + }, + "PCIE_BOT.PCIE_IMUX36_L_16->PCIE_PIPERX2VALID": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2VALID" + }, + "PCIE_BOT.PCIE_IMUX11_L_19->PCIE_CFGDSN56": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN56" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA21->PCIE_LOGIC_OUTS_B12_L_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_17" + }, + "PCIE_BOT.PCIE_IMUX2_L_6->PCIE_TRNTD110": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD110" + }, + "PCIE_BOT.PCIE_IMUX38_R_18->PCIE_PIPERX4DATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4DATA13" + }, + "PCIE_BOT.PCIE_IMUX16_L_19->PCIE_PIPERX0CHARISK1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0CHARISK1" + }, + "PCIE_BOT.PCIE_TRNFCNPH3->PCIE_LOGIC_OUTS_B13_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPH3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_2" + }, + "PCIE_BOT.PCIE_TRNRD9->PCIE_LOGIC_OUTS_B4_L_7": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_7" + }, + "PCIE_BOT.PCIE_IMUX16_R_12->PCIE_CFGDSBUSNUMBER2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSBUSNUMBER2" + }, + "PCIE_BOT.PCIE_IMUX13_L_14->PCIE_CFGAERINTERRUPTMSGNUM1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM1" + }, + "PCIE_BOT.PCIE_IMUX3_R_10->PCIE_TRNTD77": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD77" + }, + "PCIE_BOT.PCIE_DBGVECB35->PCIE_LOGIC_OUTS_B22_R_0": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_0" + }, + "PCIE_BOT.PCIE_TL2ERRHDR4->PCIE_LOGIC_OUTS_B11_R_11": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_11" + }, + "PCIE_BOT.PCIE_DBGVECC1->PCIE_LOGIC_OUTS_B20_L_7": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_7" + }, + "PCIE_BOT.PCIE_MIMRXRADDR7->PCIE_LOGIC_OUTS_B15_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXRADDR7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_19" + }, + "PCIE_BOT.PCIE_IMUX12_L_14->PCIE_CFGAERINTERRUPTMSGNUM0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM0" + }, + "PCIE_BOT.PCIE_PIPETX2CHARISK1->PCIE_LOGIC_OUTS_B16_L_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2CHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_11" + }, + "PCIE_BOT.PCIE_TRNFCNPD9->PCIE_LOGIC_OUTS_B11_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_6" + }, + "PCIE_BOT.PCIE_TRNRD21->PCIE_LOGIC_OUTS_B2_L_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_10" + }, + "PCIE_BOT.PCIE_IMUX11_R_0->PCIE_TRNTD90": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD90" + }, + "PCIE_BOT.PCIE_TRNRBARHIT5->PCIE_LOGIC_OUTS_B2_R_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNRBARHIT5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_8" + }, + "PCIE_BOT.PCIE_IMUX5_R_16->PCIE_TRNTD51": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD51" + }, + "PCIE_BOT.PCIE_PIPETX2DATA13->PCIE_LOGIC_OUTS_B4_L_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_11" + }, + "PCIE_BOT.PCIE_DBGVECB32->PCIE_LOGIC_OUTS_B15_R_2": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_2" + }, + "PCIE_BOT.PCIE_PIPETX7CHARISK1->PCIE_LOGIC_OUTS_B16_R_0": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7CHARISK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_0" + }, + "PCIE_BOT.PCIE_IMUX6_R_18->PCIE_MIMRXRDATA62": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMRXRDATA62" + }, + "PCIE_BOT.PCIE_DBGVECB46->PCIE_LOGIC_OUTS_B21_L_2": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_2" + }, + "PCIE_BOT.PCIE_TL2ERRHDR44->PCIE_LOGIC_OUTS_B9_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_8" + }, + "PCIE_BOT.PCIE_IMUX17_R_0->PCIE_CFGPORTNUMBER1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPORTNUMBER1" + }, + "PCIE_BOT.PCIE_IMUX13_R_17->PCIE_CFGERRATOMICEGRESSBLOCKEDN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRATOMICEGRESSBLOCKEDN" + }, + "PCIE_BOT.PCIE_DBGVECB4->PCIE_LOGIC_OUTS_B22_R_11": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_11" + }, + "PCIE_BOT.PCIE_DBGVECB29->PCIE_LOGIC_OUTS_B20_R_3": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_3" + }, + "PCIE_BOT.PCIE_MIMRXWDATA16->PCIE_LOGIC_OUTS_B0_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_19" + }, + "PCIE_BOT.PCIE_IMUX4_L_14->PCIE_CFGERRTLPCPLHEADER2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER2" + }, + "PCIE_BOT.PCIE_IMUX38_R_9->PCIE_PIPERX5DATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA5" + }, + "PCIE_BOT.PCIE_PLINITIALLINKWIDTH2->PCIE_LOGIC_OUTS_B10_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PLINITIALLINKWIDTH2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_2" + }, + "PCIE_BOT.PCIE_DBGVECB40->PCIE_LOGIC_OUTS_B19_L_1": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_1" + }, + "PCIE_BOT.PCIE_TRNRSOF->PCIE_LOGIC_OUTS_B5_R_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNRSOF", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_11" + }, + "PCIE_BOT.PCIE_CFGINTERRUPTMSIXENABLE->PCIE_LOGIC_OUTS_B17_L_4": { + "can_invert": "0", + "src_wire": "PCIE_CFGINTERRUPTMSIXENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_4" + }, + "PCIE_BOT.PCIE_TRNTERRDROP->PCIE_LOGIC_OUTS_B2_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TRNTERRDROP", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3" + }, + "PCIE_BOT.PCIE_MIMTXWDATA49->PCIE_LOGIC_OUTS_B13_R_4": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA49", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_4" + }, + "PCIE_BOT.PCIE_PIPETX4DATA12->PCIE_LOGIC_OUTS_B0_R_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_15" + }, + "PCIE_BOT.PCIE_IMUX6_R_8->PCIE_CFGMGMTDI24": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI24" + }, + "PCIE_BOT.PCIE_IMUX37_L_9->PCIE_PIPERX1PHYSTATUS": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX1PHYSTATUS" + }, + "PCIE_BOT.PCIE_PIPERX7POLARITY->PCIE_LOGIC_OUTS_B1_R_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPERX7POLARITY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_3" + }, + "PCIE_BOT.PCIE_IMUX8_R_9->PCIE_CFGMGMTDI28": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI28" + }, + "PCIE_BOT.PCIE_TL2ERRHDR23->PCIE_LOGIC_OUTS_B15_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_2" + }, + "PCIE_BOT.PCIE_DBGVECA27->PCIE_LOGIC_OUTS_B20_R_18": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_18" + }, + "PCIE_BOT.PCIE_IMUX3_L_11->PCIE_TRNTEOF": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTEOF" + }, + "PCIE_BOT.PCIE_CFGMSGDATA4->PCIE_LOGIC_OUTS_B17_L_11": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_11" + }, + "PCIE_BOT.PCIE_IMUX12_L_18->PCIE_DRPADDR3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_DRPADDR3" + }, + "PCIE_BOT.PCIE_CFGDEVCONTROLAUXPOWEREN->PCIE_LOGIC_OUTS_B19_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGDEVCONTROLAUXPOWEREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_15" + }, + "PCIE_BOT.PCIE_IMUX32_R_8->PCIE_PIPERX5DATA11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_R_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA11" + }, + "PCIE_BOT.PCIE_IMUX10_L_19->PCIE_CFGDSN55": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN55" + }, + "PCIE_BOT.PCIE_CFGBRIDGESERREN->PCIE_LOGIC_OUTS_B17_L_8": { + "can_invert": "0", + "src_wire": "PCIE_CFGBRIDGESERREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_8" + }, + "PCIE_BOT.PCIE_IMUX10_R_13->PCIE_CFGERRAERHEADERLOG19": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG19" + }, + "PCIE_BOT.PCIE_IMUX7_L_16->PCIE_CFGERRTLPCPLHEADER13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER13" + }, + "PCIE_BOT.PCIE_LL2RECEIVERERR->PCIE_LOGIC_OUTS_B11_R_13": { + "can_invert": "0", + "src_wire": "PCIE_LL2RECEIVERERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_13" + }, + "PCIE_BOT.PCIE_IMUX2_R_10->PCIE_TRNTD76": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD76" + }, + "PCIE_BOT.PCIE_IMUX34_L_15->PCIE_PIPERX2ELECIDLE": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX2ELECIDLE" + }, + "PCIE_BOT.PCIE_TRNRD28->PCIE_LOGIC_OUTS_B1_L_12": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_12" + }, + "PCIE_BOT.PCIE_IMUX10_R_9->PCIE_CFGMGMTDI30": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTDI30" + }, + "PCIE_BOT.PCIE_IMUX13_L_0->PCIE_CFGERRAERHEADERLOG74": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG74" + }, + "PCIE_BOT.PCIE_DBGVECA42->PCIE_LOGIC_OUTS_B18_R_13": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_13" + }, + "PCIE_BOT.PCIE_PIPETX0POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0POWERDOWN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_17" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA16->PCIE_LOGIC_OUTS_B4_L_16": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_16" + }, + "PCIE_BOT.PCIE_PIPETX4DATA3->PCIE_LOGIC_OUTS_B15_R_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4DATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_18" + }, + "PCIE_BOT.PCIE_IMUX36_R_16->PCIE_PIPERX6VALID": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6VALID" + }, + "PCIE_BOT.PCIE_TRNFCCPLD10->PCIE_LOGIC_OUTS_B9_L_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCCPLD10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_11" + }, + "PCIE_BOT.PCIE_MIMRXRADDR12->PCIE_LOGIC_OUTS_B21_R_15": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXRADDR12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_15" + }, + "PCIE_BOT.PCIE_TRNFCNPH7->PCIE_LOGIC_OUTS_B8_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPH7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_3" + }, + "PCIE_BOT.PCIE_DBGVECB38->PCIE_LOGIC_OUTS_B22_L_0": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_0" + }, + "PCIE_BOT.PCIE_MIMTXWDATA28->PCIE_LOGIC_OUTS_B16_R_7": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_7" + }, + "PCIE_BOT.PCIE_IMUX11_R_10->PCIE_CFGERRAERHEADERLOG32": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG32" + }, + "PCIE_BOT.PCIE_DBGVECB6->PCIE_LOGIC_OUTS_B22_R_13": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_13" + }, + "PCIE_BOT.PCIE_IMUX13_L_3->PCIE_CFGSUBSYSID1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID1" + }, + "PCIE_BOT.PCIE_IMUX11_R_1->PCIE_TRNTD86": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD86" + }, + "PCIE_BOT.PCIE_PIPETX0DATA4->PCIE_LOGIC_OUTS_B0_L_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_17" + }, + "PCIE_BOT.PCIE_PIPETX1POWERDOWN0->PCIE_LOGIC_OUTS_B1_L_6": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1POWERDOWN0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_6" + }, + "PCIE_BOT.PCIE_IMUX9_L_5->PCIE_CFGFORCECOMMONCLOCKOFF": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGFORCECOMMONCLOCKOFF" + }, + "PCIE_BOT.PCIE_DBGVECB15->PCIE_LOGIC_OUTS_B18_R_7": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_7" + }, + "PCIE_BOT.PCIE_IMUX39_L_18->PCIE_PIPERX0DATA12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA12" + }, + "PCIE_BOT.PCIE_IMUX2_L_10->PCIE_TRNTD126": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD126" + }, + "PCIE_BOT.PCIE_IMUX4_R_6->PCIE_MIMTXRDATA44": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA44" + }, + "PCIE_BOT.PCIE_IMUX4_R_9->PCIE_MIMTXRDATA66": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA66" + }, + "PCIE_BOT.PCIE_IMUX13_R_6->PCIE_CFGERRAERHEADERLOG46": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG46" + }, + "PCIE_BOT.PCIE_CTRL1_R_0->PCIE_CMRSTN": { + "can_invert": "0", + "src_wire": "PCIE_CTRL1_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CMRSTN" + }, + "PCIE_BOT.PCIE_DBGVECB37->PCIE_LOGIC_OUTS_B21_L_0": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_0" + }, + "PCIE_BOT.PCIE_IMUX33_L_19->PCIE_PIPERX0DATA10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX0DATA10" + }, + "PCIE_BOT.PCIE_LL2REPLAYTOERR->PCIE_LOGIC_OUTS_B5_R_12": { + "can_invert": "0", + "src_wire": "PCIE_LL2REPLAYTOERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_12" + }, + "PCIE_BOT.PCIE_IMUX3_R_9->PCIE_MIMTXRDATA39": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA39" + }, + "PCIE_BOT.PCIE_TRNRD13->PCIE_LOGIC_OUTS_B2_L_8": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_8" + }, + "PCIE_BOT.PCIE_IMUX13_L_12->PCIE_CFGSUBSYSVENDID9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID9" + }, + "PCIE_BOT.PCIE_IMUX12_R_10->PCIE_CFGERRAERHEADERLOG33": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG33" + }, + "PCIE_BOT.PCIE_IMUX8_L_16->PCIE_CFGDSN41": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN41" + }, + "PCIE_BOT.PCIE_TRNRECRCERR->PCIE_LOGIC_OUTS_B4_R_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNRECRCERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_10" + }, + "PCIE_BOT.PCIE_PIPETX2DATA7->PCIE_LOGIC_OUTS_B6_L_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_13" + }, + "PCIE_BOT.PCIE_IMUX8_L_3->PCIE_CFGPCIECAPINTERRUPTMSGNUM0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM0" + }, + "PCIE_BOT.PCIE_IMUX35_R_19->PCIE_PIPERX4STATUS2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_R_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX4STATUS2" + }, + "PCIE_BOT.PCIE_MIMRXWDATA37->PCIE_LOGIC_OUTS_B9_R_15": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_15" + }, + "PCIE_BOT.PCIE_MIMTXRADDR10->PCIE_LOGIC_OUTS_B8_R_9": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_9" + }, + "PCIE_BOT.PCIE_TL2ERRHDR3->PCIE_LOGIC_OUTS_B10_R_11": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_11" + }, + "PCIE_BOT.PCIE_TRNTDSTRDY0->PCIE_LOGIC_OUTS_B1_R_10": { + "can_invert": "0", + "src_wire": "PCIE_TRNTDSTRDY0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_10" + }, + "PCIE_BOT.PCIE_DBGVECB41->PCIE_LOGIC_OUTS_B20_L_1": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_1" + }, + "PCIE_BOT.PCIE_IMUX1_R_10->PCIE_TRNTD75": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD75" + }, + "PCIE_BOT.PCIE_TRNFCNPH0->PCIE_LOGIC_OUTS_B7_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPH0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_1" + }, + "PCIE_BOT.PCIE_DBGVECA28->PCIE_LOGIC_OUTS_B21_R_18": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_18" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT->PCIE_LOGIC_OUTS_B8_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_19" + }, + "PCIE_BOT.PCIE_IMUX17_R_6->PCIE_CFGERRAERHEADERLOG49": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG49" + }, + "PCIE_BOT.PCIE_LL2REPLAYROERR->PCIE_LOGIC_OUTS_B4_R_12": { + "can_invert": "0", + "src_wire": "PCIE_LL2REPLAYROERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_12" + }, + "PCIE_BOT.PCIE_PIPETX3POWERDOWN1->PCIE_LOGIC_OUTS_B7_L_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX3POWERDOWN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_2" + }, + "PCIE_BOT.PCIE_PIPETX7COMPLIANCE->PCIE_LOGIC_OUTS_B3_R_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7COMPLIANCE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_3" + }, + "PCIE_BOT.PCIE_MIMRXWDATA57->PCIE_LOGIC_OUTS_B5_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_19" + }, + "PCIE_BOT.PCIE_MIMTXWDATA68->PCIE_LOGIC_OUTS_B5_R_2": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA68", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_2" + }, + "PCIE_BOT.PCIE_IMUX14_R_10->PCIE_CFGDSDEVICENUMBER0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSDEVICENUMBER0" + }, + "PCIE_BOT.PCIE_PIPETX4CHARISK0->PCIE_LOGIC_OUTS_B16_R_17": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX4CHARISK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_17" + }, + "PCIE_BOT.PCIE_DBGVECA39->PCIE_LOGIC_OUTS_B20_R_14": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECA39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_14" + }, + "PCIE_BOT.PCIE_MIMRXWADDR4->PCIE_LOGIC_OUTS_B16_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWADDR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_19" + }, + "PCIE_BOT.PCIE_PIPETX0DATA13->PCIE_LOGIC_OUTS_B4_L_15": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_15" + }, + "PCIE_BOT.PCIE_IMUX5_L_3->PCIE_CFGERRAERHEADERLOG87": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG87" + }, + "PCIE_BOT.PCIE_MIMTXWEN->PCIE_LOGIC_OUTS_B12_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_6" + }, + "PCIE_BOT.PCIE_TL2ERRHDR38->PCIE_LOGIC_OUTS_B17_L_6": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_6" + }, + "PCIE_BOT.PCIE_TL2ASPMSUSPENDCREDITCHECKOK->PCIE_LOGIC_OUTS_B7_R_14": { + "can_invert": "0", + "src_wire": "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_14" + }, + "PCIE_BOT.PCIE_IMUX39_R_16->PCIE_PIPERX6DATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA4" + }, + "PCIE_BOT.PCIE_IMUX7_L_17->PCIE_CFGERRTLPCPLHEADER17": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER17" + }, + "PCIE_BOT.PCIE_IMUX38_R_7->PCIE_PIPERX5DATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX5DATA13" + }, + "PCIE_BOT.PCIE_PIPETX1DATA0->PCIE_LOGIC_OUTS_B9_L_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1DATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_7" + }, + "PCIE_BOT.PCIE_CFGMSGDATA15->PCIE_LOGIC_OUTS_B13_L_15": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGDATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_15" + }, + "PCIE_BOT.PCIE_TRNRD34->PCIE_LOGIC_OUTS_B10_L_13": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_13" + }, + "PCIE_BOT.PCIE_PIPETX2DATA4->PCIE_LOGIC_OUTS_B0_L_13": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_13" + }, + "PCIE_BOT.PCIE_MIMTXWDATA26->PCIE_LOGIC_OUTS_B5_R_6": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_6" + }, + "PCIE_BOT.PCIE_TRNRD116->PCIE_LOGIC_OUTS_B0_R_14": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD116", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_14" + }, + "PCIE_BOT.PCIE_DBGVECB56->PCIE_LOGIC_OUTS_B19_L_5": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_5" + }, + "PCIE_BOT.PCIE_MIMTXWDATA40->PCIE_LOGIC_OUTS_B1_R_0": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_0" + }, + "PCIE_BOT.PCIE_PIPETX7DATA10->PCIE_LOGIC_OUTS_B11_R_1": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_1" + }, + "PCIE_BOT.PCIE_PIPERX3POLARITY->PCIE_LOGIC_OUTS_B1_L_3": { + "can_invert": "0", + "src_wire": "PCIE_PIPERX3POLARITY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_3" + }, + "PCIE_BOT.PCIE_MIMRXWDATA56->PCIE_LOGIC_OUTS_B6_R_16": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWDATA56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_16" + }, + "PCIE_BOT.PCIE_TRNRD113->PCIE_LOGIC_OUTS_B5_R_15": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD113", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_15" + }, + "PCIE_BOT.PCIE_IMUX38_R_15->PCIE_PIPERX6STATUS1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6STATUS1" + }, + "PCIE_BOT.PCIE_IMUX0_L_10->PCIE_TRNTD124": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD124" + }, + "PCIE_BOT.PCIE_IMUX7_L_8->PCIE_CFGERRAERHEADERLOG109": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG109" + }, + "PCIE_BOT.PCIE_IMUX6_L_16->PCIE_CFGERRTLPCPLHEADER12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER12" + }, + "PCIE_BOT.PCIE_TRNRD106->PCIE_LOGIC_OUTS_B5_R_17": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD106", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_17" + }, + "PCIE_BOT.PCIE_IMUX2_R_9->PCIE_MIMTXRDATA38": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_MIMTXRDATA38" + }, + "PCIE_BOT.PCIE_MIMTXWDATA20->PCIE_LOGIC_OUTS_B0_R_5": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_5" + }, + "PCIE_BOT.PCIE_MIMRXWADDR0->PCIE_LOGIC_OUTS_B14_R_19": { + "can_invert": "0", + "src_wire": "PCIE_MIMRXWADDR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_19" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA26->PCIE_LOGIC_OUTS_B8_L_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_18" + }, + "PCIE_BOT.PCIE_MIMTXRADDR6->PCIE_LOGIC_OUTS_B17_R_2": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXRADDR6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_2" + }, + "PCIE_BOT.PCIE_IMUX33_R_17->PCIE_PIPERX6DATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA2" + }, + "PCIE_BOT.PCIE_TRNRD56->PCIE_LOGIC_OUTS_B1_L_19": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD56", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_19" + }, + "PCIE_BOT.PCIE_IMUX7_L_19->PCIE_CFGERRTLPCPLHEADER25": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRTLPCPLHEADER25" + }, + "PCIE_BOT.PCIE_IMUX5_L_12->PCIE_CFGERRAERHEADERLOG123": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG123" + }, + "PCIE_BOT.PCIE_IMUX15_L_11->PCIE_CFGSUBSYSVENDID7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSVENDID7" + }, + "PCIE_BOT.PCIE_PIPETX2DATA12->PCIE_LOGIC_OUTS_B0_L_11": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX2DATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_11" + }, + "PCIE_BOT.PCIE_TL2ERRHDR18->PCIE_LOGIC_OUTS_B4_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TL2ERRHDR18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_1" + }, + "PCIE_BOT.PCIE_PIPETX0DATA0->PCIE_LOGIC_OUTS_B9_L_18": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX0DATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_18" + }, + "PCIE_BOT.PCIE_IMUX13_L_9->PCIE_CFGSUBSYSID15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGSUBSYSID15" + }, + "PCIE_BOT.PCIE_IMUX6_L_3->PCIE_CFGERRAERHEADERLOG88": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG88" + }, + "PCIE_BOT.PCIE_DBGVECB23->PCIE_LOGIC_OUTS_B8_R_4": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECB23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_4" + }, + "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMASNAK->PCIE_LOGIC_OUTS_B10_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGMSGRECEIVEDPMASNAK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_19" + }, + "PCIE_BOT.PCIE_RECEIVEDFUNCLVLRSTN->PCIE_LOGIC_OUTS_B12_R_9": { + "can_invert": "0", + "src_wire": "PCIE_RECEIVEDFUNCLVLRSTN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_9" + }, + "PCIE_BOT.PCIE_LL2BADDLLPERR->PCIE_LOGIC_OUTS_B14_R_13": { + "can_invert": "0", + "src_wire": "PCIE_LL2BADDLLPERR", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_13" + }, + "PCIE_BOT.PCIE_TRNFCNPD1->PCIE_LOGIC_OUTS_B8_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TRNFCNPD1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_4" + }, + "PCIE_BOT.PCIE_IMUX10_R_14->PCIE_CFGERRAERHEADERLOG15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG15" + }, + "PCIE_BOT.PCIE_IMUX8_L_1->PCIE_CFGPMHALTASPML0SN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMHALTASPML0SN" + }, + "PCIE_BOT.PCIE_IMUX1_L_13->PCIE_TRNTCFGGNT": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTCFGGNT" + }, + "PCIE_BOT.PCIE_IMUX7_R_10->PCIE_CFGMGMTBYTEENN1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGMGMTBYTEENN1" + }, + "PCIE_BOT.PCIE_IMUX14_R_14->PCIE_CFGINTERRUPTDI2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGINTERRUPTDI2" + }, + "PCIE_BOT.PCIE_TRNRDLLPDATA27->PCIE_LOGIC_OUTS_B10_L_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRDLLPDATA27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_18" + }, + "PCIE_BOT.PCIE_PIPETX7DATA7->PCIE_LOGIC_OUTS_B6_R_2": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX7DATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_2" + }, + "PCIE_BOT.PCIE_IMUX9_R_18->PCIE_TRNTD1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTD1" + }, + "PCIE_BOT.PCIE_IMUX7_L_11->PCIE_CFGERRAERHEADERLOG121": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG121" + }, + "PCIE_BOT.PCIE_IMUX7_L_12->PCIE_CFGERRAERHEADERLOG125": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG125" + }, + "PCIE_BOT.PCIE_IMUX6_L_8->PCIE_CFGERRAERHEADERLOG108": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG108" + }, + "PCIE_BOT.PCIE_IMUX2_L_11->PCIE_TRNTSOF": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTSOF" + }, + "PCIE_BOT.PCIE_IMUX12_R_11->PCIE_CFGERRAERHEADERLOG29": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGERRAERHEADERLOG29" + }, + "PCIE_BOT.PCIE_IMUX8_L_10->PCIE_CFGDSN17": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN17" + }, + "PCIE_BOT.PCIE_CFGAERROOTERRCORRERRREPORTINGEN->PCIE_LOGIC_OUTS_B19_L_19": { + "can_invert": "0", + "src_wire": "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_19" + }, + "PCIE_BOT.PCIE_TRNRD51->PCIE_LOGIC_OUTS_B0_L_18": { + "can_invert": "0", + "src_wire": "PCIE_TRNRD51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_18" + }, + "PCIE_BOT.PCIE_PIPETX6DATA0->PCIE_LOGIC_OUTS_B9_R_14": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX6DATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_14" + }, + "PCIE_BOT.PCIE_PIPETX1COMPLIANCE->PCIE_LOGIC_OUTS_B3_L_7": { + "can_invert": "0", + "src_wire": "PCIE_PIPETX1COMPLIANCE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_7" + }, + "PCIE_BOT.PCIE_IMUX0_L_11->PCIE_TRNTREM0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TRNTREM0" + }, + "PCIE_BOT.PCIE_IMUX11_L_2->PCIE_CFGPMSENDPMETON": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGPMSENDPMETON" + }, + "PCIE_BOT.PCIE_IMUX14_L_14->PCIE_CFGAERINTERRUPTMSGNUM2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGAERINTERRUPTMSGNUM2" + }, + "PCIE_BOT.PCIE_IMUX9_L_10->PCIE_CFGDSN18": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_CFGDSN18" + }, + "PCIE_BOT.PCIE_MIMTXWDATA37->PCIE_LOGIC_OUTS_B9_R_0": { + "can_invert": "0", + "src_wire": "PCIE_MIMTXWDATA37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_0" + }, + "PCIE_BOT.PCIE_CFGCOMMANDSERREN->PCIE_LOGIC_OUTS_B16_L_8": { + "can_invert": "0", + "src_wire": "PCIE_CFGCOMMANDSERREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_8" + }, + "PCIE_BOT.PCIE_IMUX38_R_14->PCIE_PIPERX6DATA13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX6DATA13" + }, + "PCIE_BOT.PCIE_IMUX36_L_4->PCIE_PIPERX3DATA9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_PIPERX3DATA9" + }, + "PCIE_BOT.PCIE_TRNRREM1->PCIE_LOGIC_OUTS_B3_R_11": { + "can_invert": "0", + "src_wire": "PCIE_TRNRREM1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_11" + }, + "PCIE_BOT.PCIE_PLDBGVEC10->PCIE_LOGIC_OUTS_B21_R_5": { + "can_invert": "0", + "src_wire": "PCIE_PLDBGVEC10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_5" + }, + "PCIE_BOT.PCIE_DBGVECC3->PCIE_LOGIC_OUTS_B18_L_8": { + "can_invert": "0", + "src_wire": "PCIE_DBGVECC3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_8" } }, - "tile_type": "PCIE_BOT" + "wires": [ + "PCIE_MONITOR_N_8", + "PCIE_TL2ERRHDR47", + "PCIE_IMUX3_R_0", + "PCIE_LOGIC_OUTS_B7_R_6", + "PCIE_LOGIC_OUTS_B17_L_3", + "PCIE_NE2A0_15", + "PCIE_BLOCK_OUTS_B1_R_3", + "PCIE_NE2A1_6", + "PCIE_MONITOR_N_4", + "PCIE_CFGMGMTDO13", + "PCIE_LOGIC_OUTS_B16_L_2", + "PCIE_IMUX27_R_5", + "PCIE_BYP6_R_7", + "PCIE_FAN3_R_17", + "PCIE_CFGDSN4", + "PCIE_BYP4_L_4", + "PCIE_NE4C0_5", + "PCIE_IMUX45_R_12", + "PCIE_PIPERX2DATA0", + "PCIE_TRNRD3", + "PCIE_EDTCHANNELSIN8", + "PCIE_LOGIC_OUTS_B22_R_11", + "PCIE_CFGCOMMANDSERREN", + "PCIE_EE2A1_9", + "PCIE_EL1BEG0_3", + "PCIE_IMUX35_R_13", + "PCIE_TRNTDLLPDATA9", + "PCIE_IMUX12_L_5", + "PCIE_FAN1_L_1", + "PCIE_NE4C3_6", + "PCIE_TRNFCSEL1", + "PCIE_CFGERRTLPCPLHEADER13", + "PCIE_EE4A1_1", + "PCIE_WL1END3_18", + "PCIE_IMUX36_L_11", + "PCIE_DBGVECC4", + "PCIE_TRNTD4", + "PCIE_TRNRD45", + "PCIE_LOGIC_OUTS_B17_R_12", + "PCIE_LOGIC_OUTS_B14_R_0", + "PCIE_MIMRXWADDR5", + "PCIE_TRNRDLLPDATA61", + "PCIE_EE4C0_6", + "PCIE_EL1BEG2_3", + "PCIE_WW4C3_16", + "PCIE_EE4C1_10", + "PCIE_PIPERX6DATA12", + "PCIE_BLOCK_OUTS_B1_L_1", + "PCIE_BYP2_L_17", + "PCIE_IMUX31_R_2", + "PCIE_IMUX16_L_6", + "PCIE_EE2BEG3_17", + "PCIE_IMUX45_R_0", + "PCIE_TRNRD46", + "PCIE_LOGIC_OUTS_B20_R_6", + "PCIE_LOGIC_OUTS_B8_R_16", + "PCIE_LH8_3", + "PCIE_LOGIC_OUTS_B6_L_7", + "PCIE_WW4C2_2", + "PCIE_BYP7_L_15", + "PCIE_MONITOR_P_15", + "PCIE_FAN7_L_10", + "PCIE_TRNTD113", + "PCIE_WW4C0_4", + "PCIE_USERRSTN", + "PCIE_SW4END1_2", + "PCIE_IMUX9_L_6", + "PCIE_EE4BEG2_4", + "PCIE_LOGIC_OUTS_B8_L_3", + "PCIE_LOGIC_OUTS_B20_R_11", + "PCIE_CLK1_R_10", + "PCIE_EL1BEG3_9", + "PCIE_WW4END0_9", + "PCIE_WW4A0_15", + "PCIE_IMUX21_L_9", + "PCIE_EE4C1_0", + "PCIE_TRNRDLLPDATA8", + "PCIE_WW4C3_17", + "PCIE_BLOCK_OUTS_B2_L_17", + "PCIE_CLK0_R_1", + "PCIE_FAN1_R_7", + "PCIE_NW4END1_9", + "PCIE_IMUX13_R_14", + "PCIE_LOGIC_OUTS_B2_L_10", + "PCIE_SE4C2_7", + "PCIE_NW4A3_13", + "PCIE_LOGIC_OUTS_B1_L_1", + "PCIE_IMUX25_R_11", + "PCIE_PIPERX0DATA6", + "PCIE_EL1BEG0_0", + "PCIE_TRNRDLLPDATA41", + "PCIE_SE2A0_2", + "PCIE_PLSELLNKWIDTH0", + "PCIE_SW2A2_5", + "PCIE_NW4A3_2", + "PCIE_IMUX47_R_16", + "PCIE_BYP2_R_0", + "PCIE_LOGIC_OUTS_B19_R_1", + "PCIE_IMUX35_L_1", + "PCIE_IMUX38_L_10", + "PCIE_NE4BEG1_14", + "PCIE_BYP7_L_13", + "PCIE_LOGIC_OUTS_B4_R_9", + "PCIE_LOGIC_OUTS_B5_L_1", + "PCIE_MIMRXRDATA9", + "PCIE_BYP0_L_13", + "PCIE_SE2A1_18", + "PCIE_CFGDSFUNCTIONNUMBER2", + "PCIE_IMUX14_R_14", + "PCIE_FAN2_L_17", + "PCIE_PIPERX0DATA15", + "PCIE_PIPETX3POWERDOWN1", + "PCIE_IMUX45_L_18", + "PCIE_EE4C0_17", + "PCIE_IMUX46_L_8", + "PCIE_NW2A2_17", + "PCIE_BYP0_L_6", + "PCIE_NW4A1_13", + "PCIE_LOGIC_OUTS_B1_R_0", + "PCIE_MIMRXRDATA28", + "PCIE_IMUX13_R_0", + "PCIE_BYP3_R_17", + "PCIE_LH1_4", + "PCIE_FAN7_L_5", + "PCIE_DRPADDR4", + "PCIE_PLRXPMSTATE1", + "PCIE_TRNTDLLPDSTRDY", + "PCIE_PLRSTN", + "PCIE_IMUX1_R_3", + "PCIE_IMUX14_R_8", + "PCIE_MIMRXWDATA55", + "PCIE_LOGIC_OUTS_B3_R_7", + "PCIE_LOGIC_OUTS_B22_L_13", + "PCIE_NW2A1_1", + "PCIE_LOGIC_OUTS_B20_R_15", + "PCIE_BYP0_L_14", + "PCIE_IMUX11_L_8", + "PCIE_CFGTRANSACTIONADDR1", + "PCIE_WW4END3_9", + "PCIE_EE2BEG3_1", + "PCIE_FAN5_L_6", + "PCIE_EE2BEG2_4", + "PCIE_LOGIC_OUTS_B22_L_14", + "PCIE_CFGDSN10", + "PCIE_IMUX17_R_15", + "PCIE_IMUX18_R_18", + "PCIE_SW4A1_5", + "PCIE_LOGIC_OUTS_B7_L_6", + "PCIE_BLOCK_OUTS_B3_L_16", + "PCIE_LOGIC_OUTS_B15_L_15", + "PCIE_PIPERX2DATA9", + "PCIE_IMUX40_R_5", + "PCIE_IMUX44_L_1", + "PCIE_CFGERRAERHEADERLOG68", + "PCIE_PIPERX7STATUS0", + "PCIE_IMUX42_L_8", + "PCIE_MIMRXRDATA64", + "PCIE_LOGIC_OUTS_B15_R_11", + "PCIE_MIMRXWDATA19", + "PCIE_BYP4_L_7", + "PCIE_FAN0_L_15", + "PCIE_FAN7_R_13", + "PCIE_IMUX10_L_4", + "PCIE_WW2A0_15", + "PCIE_TRNTD84", + "PCIE_IMUX39_L_12", + "PCIE_LOGIC_OUTS_B17_R_5", + "PCIE_WW2A3_0", + "PCIE_FAN3_R_5", + "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", + "PCIE_IMUX10_R_10", + "PCIE_EE4B1_9", + "PCIE_PIPERX0DATA5", + "PCIE_LOGIC_OUTS_B17_L_14", + "PCIE_WL1END1_16", + "PCIE_PIPERX0STATUS2", + "PCIE_WW4END0_15", + "PCIE_LOGIC_OUTS_B6_L_19", + "PCIE_BLOCK_OUTS_B2_R_13", + "PCIE_BYP3_L_18", + "PCIE_MIMRXWDATA3", + "PCIE_TRNTD95", + "PCIE_LOGIC_OUTS_B20_L_3", + "PCIE_EE4B1_15", + "PCIE_MIMRXWDATA23", + "PCIE_TL2ERRHDR40", + "PCIE_NW4A2_12", + "PCIE_CFGERRAERHEADERLOG99", + "PCIE_BYP4_R_5", + "PCIE_LOGIC_OUTS_B7_L_17", + "PCIE_DRPDO10", + "PCIE_LL2BADDLLPERR", + "PCIE_IMUX5_L_13", + "PCIE_NE2A1_13", + "PCIE_BYP2_L_6", + "PCIE_BLOCK_OUTS_B2_R_5", + "PCIE_BYP0_R_6", + "PCIE_LH8_8", + "PCIE_TRNTD45", + "PCIE_FAN2_L_13", + "PCIE_LOGIC_OUTS_B5_R_15", + "PCIE_IMUX11_R_16", + "PCIE_IMUX13_L_7", + "PCIE_FAN1_L_10", + "PCIE_SW4A1_7", + "PCIE_FAN5_L_4", + "PCIE_PIPETX4CHARISK1", + "PCIE_NW2A2_3", + "PCIE_LOGIC_OUTS_B3_R_0", + "PCIE_FAN5_R_16", + "PCIE_PIPETX2POWERDOWN1", + "PCIE_EE4BEG0_8", + "PCIE_LOGIC_OUTS_B16_L_18", + "PCIE_WW4A0_16", + "PCIE_LOGIC_OUTS_B21_R_12", + "PCIE_MIMTXWDATA3", + "PCIE_CFGERRTLPCPLHEADER38", + "PCIE_LOGIC_OUTS_B12_L_15", + "PCIE_PIPETX4DATA4", + "PCIE_LOGIC_OUTS_B13_L_17", + "PCIE_MIMTXRDATA29", + "PCIE_IMUX9_L_16", + "PCIE_CFGERRTLPCPLHEADER45", + "PCIE_TRNRSOF", + "PCIE_CFGDSBUSNUMBER0", + "PCIE_WW4END2_7", + "PCIE_MIMRXRDATA55", + "PCIE_IMUX1_L_2", + "PCIE_IMUX9_L_8", + "PCIE_WR1END3_1", + "PCIE_NW4END1_0", + "PCIE_LOGIC_OUTS_B1_L_5", + "PCIE_LOGIC_OUTS_B0_R_13", + "PCIE_SW4A2_9", + "PCIE_IMUX6_R_15", + "PCIE_IMUX35_R_2", + "PCIE_IMUX6_L_10", + "PCIE_SE4C1_18", + "PCIE_WW4B0_18", + "PCIE_IMUX41_L_7", + "PCIE_EE4C2_14", + "PCIE_NE2A3_16", + "PCIE_LH10_8", + "PCIE_IMUX6_L_1", + "PCIE_BYP3_R_14", + "PCIE_TRNRD78", + "PCIE_NE2A3_10", + "PCIE_IMUX47_R_0", + "PCIE_IMUX14_L_8", + "PCIE_FAN7_L_4", + "PCIE_CFGDEVCONTROL2ARIFORWARDEN", + "PCIE_LH10_2", + "PCIE_TRNTD56", + "PCIE_TRNRD64", + "PCIE_IMUX9_L_2", + "PCIE_LOGIC_OUTS_B7_L_12", + "PCIE_FAN5_L_12", + "PCIE_SW4END0_17", + "PCIE_LH4_1", + "PCIE_IMUX45_L_15", + "PCIE_PIPETX4DATA11", + "PCIE_PIPERX4DATA10", + "PCIE_BLOCK_OUTS_B1_R_11", + "PCIE_MIMTXRDATA26", + "PCIE_IMUX13_R_3", + "PCIE_LOGIC_OUTS_B13_L_6", + "PCIE_SW2A2_12", + "PCIE_IMUX12_R_17", + "PCIE_LOGIC_OUTS_B7_R_17", + "PCIE_IMUX15_R_5", + "PCIE_TRNTSTR", + "PCIE_EE4C3_13", + "PCIE_MIMTXRDATA3", + "PCIE_SE4BEG1_12", + "PCIE_CFGLINKCONTROLASPMCONTROL1", + "PCIE_IMUX32_R_19", + "PCIE_PIPERX4DATA2", + "PCIE_NE2A3_15", + "PCIE_IMUX25_L_4", + "PCIE_IMUX39_R_6", + "PCIE_IMUX46_R_10", + "PCIE_EE4BEG0_9", + "PCIE_BLOCK_OUTS_B0_R_14", + "PCIE_CLK1_L_6", + "PCIE_WW4A2_16", + "PCIE_PLLTSSMSTATE5", + "PCIE_TRNTD73", + "PCIE_CTRL0_L_4", + "PCIE_IMUX28_L_5", + "PCIE_SE2A0_11", + "PCIE_WW4C0_5", + "PCIE_EL1BEG0_11", + "PCIE_PIPETX7DATA6", + "PCIE_IMUX27_L_15", + "PCIE_PIPETX7CHARISK0", + "PCIE_PIPERX1DATA3", + "PCIE_FAN1_L_4", + "PCIE_SW4END1_1", + "PCIE_PIPETX4DATA9", + "PCIE_IMUX22_L_14", + "PCIE_IMUX39_L_17", + "PCIE_LOGIC_OUTS_B3_L_17", + "PCIE_PIPERX5DATA1", + "PCIE_SW2A2_13", + "PCIE_NE4BEG0_5", + "PCIE_IMUX15_L_13", + "PCIE_IMUX3_R_3", + "PCIE_IMUX20_R_18", + "PCIE_DBGVECB18", + "PCIE_CFGMSGRECEIVEDPMETOACK", + "PCIE_EE4C0_10", + "PCIE_DRPDI12", + "PCIE_WW2A1_14", + "PCIE_FAN5_L_16", + "PCIE_LOGIC_OUTS_B13_L_12", + "PCIE_MIMTXRDATA62", + "PCIE_IMUX22_R_4", + "PCIE_WW4C2_11", + "PCIE_IMUX47_L_0", + "PCIE_LOGIC_OUTS_B22_R_10", + "PCIE_PIPETX5DATA12", + "PCIE_NW4A3_9", + "PCIE_IMUX8_R_13", + "PCIE_IMUX16_L_15", + "PCIE_IMUX47_R_7", + "PCIE_CFGERRINTERNALUNCORN", + "PCIE_FAN3_L_0", + "PCIE_EE2BEG1_18", + "PCIE_IMUX36_L_13", + "PCIE_WW4C1_5", + "PCIE_NE4BEG1_0", + "PCIE_DBGVECA16", + "PCIE_LOGIC_OUTS_B1_R_9", + "PCIE_CFGSUBSYSID15", + "PCIE_FAN6_L_1", + "PCIE_IMUX18_L_19", + "PCIE_CFGDSN2", + "PCIE_IMUX34_L_19", + "PCIE_TRNRD109", + "PCIE_TRNRD100", + "PCIE_NE4BEG2_10", + "PCIE_BYP6_R_11", + "PCIE_ER1BEG1_15", + "PCIE_IMUX33_L_7", + "PCIE_IMUX3_R_11", + "PCIE_IMUX10_L_19", + "PCIE_WL1END1_0", + "PCIE_BYP5_R_2", + "PCIE_LOGIC_OUTS_B19_L_18", + "PCIE_LOGIC_OUTS_B15_R_18", + "PCIE_EE2A3_13", + "PCIE_SW4END3_18", + "PCIE_IMUX46_L_17", + "PCIE_IMUX15_R_15", + "PCIE_CLK1_R_1", + "PCIE_LOGIC_OUTS_B8_R_10", + "PCIE_EE4A3_17", + "PCIE_NE2A2_12", + "PCIE_NE4C2_13", + "PCIE_PIPERX5CHARISK1", + "PCIE_TRNTDLLPDATA20", + "PCIE_IMUX43_L_7", + "PCIE_LOGIC_OUTS_B21_R_5", + "PCIE_CFGERRAERHEADERLOG123", + "PCIE_EE4A3_18", + "PCIE_IMUX45_L_17", + "PCIE_IMUX17_R_0", + "PCIE_SW2A3_3", + "PCIE_IMUX7_R_8", + "PCIE_ER1BEG1_17", + "PCIE_MIMRXWDATA59", + "PCIE_EE2A2_4", + "PCIE_IMUX45_R_1", + "PCIE_CFGERRAERHEADERLOG55", + "PCIE_NE2A3_0", + "PCIE_BYP4_L_10", + "PCIE_IMUX43_R_12", + "PCIE_XILUNCONNOUT6", + "PCIE_WW2A3_13", + "PCIE_WL1END0_2", + "PCIE_SE4BEG2_19", + "PCIE_NE2A2_10", + "PCIE_CFGMGMTDWADDR8", + "PCIE_WW2END2_5", + "PCIE_TRNRD9", + "PCIE_IMUX16_L_2", + "PCIE_NE4BEG3_14", + "PCIE_BLOCK_OUTS_B0_R_8", + "PCIE_EE4B1_5", + "PCIE_SW2A3_11", + "PCIE_NE4C2_14", + "PCIE_CFGERRAERHEADERLOG42", + "PCIE_BLOCK_OUTS_B0_R_6", + "PCIE_EE2BEG2_15", + "PCIE_IMUX2_R_6", + "PCIE_LOGIC_OUTS_B3_L_18", + "PCIE_WW4C2_10", + "PCIE_DBGVECB33", + "PCIE_LOGIC_OUTS_B10_L_14", + "PCIE_IMUX42_R_0", + "PCIE_ER1BEG0_8", + "PCIE_LH4_19", + "PCIE_CTRL1_L_16", + "PCIE_IMUX25_L_0", + "PCIE_IMUX7_L_2", + "PCIE_SE4BEG3_1", + "PCIE_SW2A0_6", + "PCIE_BYP4_L_19", + "PCIE_BLOCK_OUTS_B3_L_10", + "PCIE_PLDBGMODE1", + "PCIE_NW2A2_4", + "PCIE_CFGLINKSTATUSDLLACTIVE", + "PCIE_CFGSUBSYSID13", + "PCIE_PIPERX4DATA13", + "PCIE_CFGERRAERHEADERLOG27", + "PCIE_SE4BEG0_0", + "PCIE_IMUX8_L_2", + "PCIE_BLOCK_OUTS_B3_L_2", + "PCIE_LOGIC_OUTS_B0_R_5", + "PCIE_IMUX23_L_7", + "PCIE_IMUX4_R_15", + "PCIE_NE2A0_2", + "PCIE_IMUX41_L_11", + "PCIE_IMUX23_R_13", + "PCIE_SW4END3_15", + "PCIE_WW4B1_1", + "PCIE_DRPDO14", + "PCIE_DBGVECA40", + "PCIE_LOGIC_OUTS_B16_R_0", + "PCIE_DBGVECB30", + "PCIE_NE2A2_4", + "PCIE_LOGIC_OUTS_B22_R_14", + "PCIE_MIMTXRDATA65", + "PCIE_TL2ERRHDR19", + "PCIE_TRNTD94", + "PCIE_MIMTXRDATA32", + "PCIE_CLK0_R_19", + "PCIE_LOGIC_OUTS_B23_R_16", + "PCIE_DBGVECB20", + "PCIE_BYP5_R_13", + "PCIE_IMUX16_L_12", + "PCIE_EE4B2_1", + "PCIE_BYP3_R_19", + "PCIE_WR1END3_15", + "PCIE_LOGIC_OUTS_B2_R_19", + "PCIE_IMUX14_R_16", + "PCIE_IMUX43_R_4", + "PCIE_NE4C2_8", + "PCIE_WW4B2_10", + "PCIE_CFGERRAERHEADERLOG34", + "PCIE_BLOCK_OUTS_B2_R_2", + "PCIE_WW4A2_2", + "PCIE_TRNTDLLPDATA7", + "PCIE_TRNRD1", + "PCIE_IMUX8_R_19", + "PCIE_PIPERX7POLARITY", + "PCIE_CFGDSN57", + "PCIE_CFGDSN59", + "PCIE_IMUX23_L_1", + "PCIE_PIPERX4DATA8", + "PCIE_CFGMGMTDO22", + "PCIE_EE2A3_10", + "PCIE_LOGIC_OUTS_B19_R_2", + "PCIE_TRNRREM1", + "PCIE_TRNRD66", + "PCIE_WW4A2_3", + "PCIE_DBGVECB36", + "PCIE_EE2BEG3_19", + "PCIE_TRNTDLLPDATA16", + "PCIE_IMUX10_L_18", + "PCIE_IMUX11_L_11", + "PCIE_CLK0_R_16", + "PCIE_IMUX16_L_9", + "PCIE_WL1END0_19", + "PCIE_MIMRXWADDR12", + "PCIE_IMUX9_R_17", + "PCIE_TL2ERRHDR15", + "PCIE_IMUX7_R_12", + "PCIE_LOGIC_OUTS_B23_L_18", + "PCIE_PIPERX4DATA9", + "PCIE_TL2ERRHDR14", + "PCIE_PIPETX5DATA2", + "PCIE_EE4A2_0", + "PCIE_PLDIRECTEDLTSSMNEW2", + "PCIE_IMUX31_L_13", + "PCIE_LOGIC_OUTS_B1_L_0", + "PCIE_IMUX8_L_15", + "PCIE_IMUX32_L_16", + "PCIE_MONITOR_N_17", + "PCIE_DRPDO11", + "PCIE_CFGTRANSACTIONTYPE", + "PCIE_LOGIC_OUTS_B0_R_9", + "PCIE_LH10_9", + "PCIE_PIPETX3DATA4", + "PCIE_FAN6_L_6", + "PCIE_IMUX36_R_9", + "PCIE_CFGDSN11", + "PCIE_LOGIC_OUTS_B5_R_13", + "PCIE_IMUX6_R_18", + "PCIE_BYP5_R_3", + "PCIE_ER1BEG0_4", + "PCIE_LOGIC_OUTS_B15_L_14", + "PCIE_IMUX43_L_16", + "PCIE_EL1BEG1_12", + "PCIE_CLK0_L_19", + "PCIE_IMUX35_L_16", + "PCIE_NE4BEG0_10", + "PCIE_LOGIC_OUTS_B4_R_5", + "PCIE_IMUX2_L_14", + "PCIE_WW2END1_4", + "PCIE_SE4BEG1_3", + "PCIE_TRNRD6", + "PCIE_CFGDSDEVICENUMBER3", + "PCIE_DBGVECA58", + "PCIE_IMUX39_L_1", + "PCIE_IMUX37_R_10", + "PCIE_DRPDI2", + "PCIE_CFGDEVID2", + "PCIE_CFGSUBSYSVENDID12", + "PCIE_IMUX36_R_7", + "PCIE_LOGIC_OUTS_B5_R_6", + "PCIE_WW2END3_8", + "PCIE_IMUX47_R_12", + "PCIE_IMUX46_L_5", + "PCIE_PIPETX0DATA5", + "PCIE_TRNRD102", + "PCIE_IMUX41_R_12", + "PCIE_IMUX20_R_11", + "PCIE_NE4BEG2_19", + "PCIE_LOGIC_OUTS_B6_L_6", + "PCIE_IMUX30_R_13", + "PCIE_IMUX36_L_12", + "PCIE_LOGIC_OUTS_B15_R_6", + "PCIE_FAN5_R_1", + "PCIE_SE2A1_2", + "PCIE_MIMTXRDATA2", + "PCIE_IMUX43_L_4", + "PCIE_CFGINTERRUPTDO0", + "PCIE_PIPERX5PHYSTATUS", + "PCIE_IMUX37_R_2", + "PCIE_MIMTXRDATA44", + "PCIE_NW4END3_3", + "PCIE_CFGSUBSYSVENDID5", + "PCIE_BLOCK_OUTS_B3_R_13", + "PCIE_FAN5_R_8", + "PCIE_NW4A1_14", + "PCIE_WW4C2_15", + "PCIE_MIMRXRDATA42", + "PCIE_LOGIC_OUTS_B7_L_4", + "PCIE_IMUX30_L_2", + "PCIE_EE4BEG3_5", + "PCIE_WW4A2_6", + "PCIE_DBGVECB27", + "PCIE_PIPETX3POWERDOWN0", + "PCIE_IMUX41_L_19", + "PCIE_FAN6_R_8", + "PCIE_FAN2_L_16", + "PCIE_PIPETX1CHARISK0", + "PCIE_IMUX45_L_6", + "PCIE_LOGIC_OUTS_B5_R_10", + "PCIE_PIPERX4POLARITY", + "PCIE_CFGERRAERHEADERLOG71", + "PCIE_WL1END2_15", + "PCIE_LH2_9", + "PCIE_IMUX23_R_2", + "PCIE_IMUX13_R_17", + "PCIE_TRNRDLLPDATA50", + "PCIE_DBGVECB62", + "PCIE_CFGDSN25", + "PCIE_IMUX26_L_9", + "PCIE_CFGMGMTDO28", + "PCIE_IMUX18_L_12", + "PCIE_BYP5_R_7", + "PCIE_CFGMGMTBYTEENN0", + "PCIE_EE4B0_14", + "PCIE_CTRL1_R_13", + "PCIE_CFGDEVCONTROL2IDOREQEN", + "PCIE_LOGIC_OUTS_B21_L_6", + "PCIE_WW2END0_18", + "PCIE_NE4BEG0_18", + "PCIE_CFGDSN38", + "PCIE_LH5_6", + "PCIE_SE4BEG2_2", + "PCIE_IMUX1_R_4", + "PCIE_BLOCK_OUTS_B2_R_10", + "PCIE_IMUX19_R_9", + "PCIE_EE4A1_19", + "PCIE_BYP6_R_2", + "PCIE_EE2BEG1_8", + "PCIE_IMUX43_R_9", + "PCIE_IMUX29_L_1", + "PCIE_IMUX40_R_10", + "PCIE_CFGERRAERHEADERLOG25", + "PCIE_BYP0_L_18", + "PCIE_BYP1_R_13", + "PCIE_CFGERRAERHEADERLOG16", + "PCIE_IMUX8_R_8", + "PCIE_IMUX15_R_0", + "PCIE_IMUX7_L_15", + "PCIE_TRNRDLLPDATA49", + "PCIE_TL2ERRHDR50", + "PCIE_MIMTXRDATA54", + "PCIE_EE2A3_11", + "PCIE_LOGIC_OUTS_B3_L_10", + "PCIE_TRNTD26", + "PCIE_LOGIC_OUTS_B21_R_14", + "PCIE_CFGMGMTDO4", + "PCIE_LOGIC_OUTS_B6_L_15", + "PCIE_LOGIC_OUTS_B0_L_10", + "PCIE_FAN4_L_11", + "PCIE_EE2A2_5", + "PCIE_BYP6_R_13", + "PCIE_WW4END2_9", + "PCIE_LOGIC_OUTS_B11_L_15", + "PCIE_CFGERRTLPCPLHEADER4", + "PCIE_FAN7_R_5", + "PCIE_IMUX31_L_16", + "PCIE_IMUX45_L_7", + "PCIE_IMUX21_L_1", + "PCIE_MIMRXRDATA61", + "PCIE_NE4C1_7", + "PCIE_IMUX33_L_11", + "PCIE_IMUX9_R_14", + "PCIE_SE4BEG1_15", + "PCIE_BYP3_L_8", + "PCIE_EE4B3_15", + "PCIE_MONITOR_P_18", + "PCIE_LOGIC_OUTS_B23_L_11", + "PCIE_BYP7_L_12", + "PCIE_IMUX19_L_1", + "PCIE_CFGINTERRUPTMSIENABLE", + "PCIE_SW4END2_15", + "PCIE_CFGMGMTDO10", + "PCIE_SE4C3_0", + "PCIE_LH6_3", + "PCIE_WW2END2_2", + "PCIE_SW4END2_11", + "PCIE_IMUX1_R_11", + "PCIE_FAN5_L_13", + "PCIE_IMUX39_R_5", + "PCIE_SE4C1_13", + "PCIE_BLOCK_OUTS_B3_L_0", + "PCIE_LOGIC_OUTS_B10_L_13", + "PCIE_ER1BEG0_13", + "PCIE_CFGERRAERHEADERLOG81", + "PCIE_LOGIC_OUTS_B12_R_1", + "PCIE_WW4END3_8", + "PCIE_LOGIC_OUTS_B10_R_0", + "PCIE_FAN2_R_11", + "PCIE_SE4C2_9", + "PCIE_CLK1_L_17", + "PCIE_SW4A3_2", + "PCIE_NW2A0_5", + "PCIE_DBGVECB1", + "PCIE_LH11_15", + "PCIE_EE2BEG0_10", + "PCIE_LH2_1", + "PCIE_LOGIC_OUTS_B6_L_1", + "PCIE_LOGIC_OUTS_B11_L_8", + "PCIE_NW4END3_19", + "PCIE_FAN2_L_2", + "PCIE_SE4BEG3_16", + "PCIE_FAN4_R_7", + "PCIE_IMUX33_L_2", + "PCIE_LH7_15", + "PCIE_LOGIC_OUTS_B2_L_12", + "PCIE_IMUX29_R_8", + "PCIE_EDTCLK", + "PCIE_LH7_1", + "PCIE_WW4B2_12", + "PCIE_MIMTXWDATA33", + "PCIE_ER1BEG0_11", + "PCIE_NE4C0_1", + "PCIE_TL2ERRHDR21", + "PCIE_CFGMGMTDI17", + "PCIE_DBGVECB57", + "PCIE_PIPETX7DATA0", + "PCIE_MONITOR_N_0", + "PCIE_MIMTXWADDR5", + "PCIE_PIPERX0STATUS0", + "PCIE_WL1END1_10", + "PCIE_IMUX32_R_9", + "PCIE_BYP4_R_14", + "PCIE_LOGIC_OUTS_B20_L_7", + "PCIE_LOGIC_OUTS_B0_L_17", + "PCIE_LOGIC_OUTS_B19_L_6", + "PCIE_PIPERX2CHANISALIGNED", + "PCIE_IMUX36_R_11", + "PCIE_LOGIC_OUTS_B21_R_18", + "PCIE_LOGIC_OUTS_B16_L_1", + "PCIE_IMUX15_R_4", + "PCIE_IMUX33_L_4", + "PCIE_MIMTXWDATA54", + "PCIE_WW4A0_17", + "PCIE_LOGIC_OUTS_B14_R_10", + "PCIE_PIPETX6DATA3", + "PCIE_SW4A2_4", + "PCIE_CFGMGMTWRRW1CASRWN", + "PCIE_IMUX34_R_9", + "PCIE_PIPETX6COMPLIANCE", + "PCIE_MIMTXRDATA12", + "PCIE_BYP6_R_9", + "PCIE_CFGMSGRECEIVEDDEASSERTINTC", + "PCIE_IMUX6_R_8", + "PCIE_LOGIC_OUTS_B8_R_7", + "PCIE_LOGIC_OUTS_B10_L_19", + "PCIE_CFGMSGDATA11", + "PCIE_IMUX19_R_0", + "PCIE_SE2A2_19", + "PCIE_IMUX47_L_18", + "PCIE_CFGPMFORCESTATE1", + "PCIE_BYP6_R_16", + "PCIE_BLOCK_OUTS_B3_L_17", + "PCIE_WW2END2_17", + "PCIE_LOGIC_OUTS_B14_R_13", + "PCIE_LH11_7", + "PCIE_LH5_12", + "PCIE_SW4END3_16", + "PCIE_IMUX26_R_17", + "PCIE_LOGIC_OUTS_B12_L_6", + "PCIE_CFGMGMTDWADDR9", + "PCIE_IMUX2_R_1", + "PCIE_CFGDSN56", + "PCIE_LOGIC_OUTS_B17_R_4", + "PCIE_IMUX0_L_2", + "PCIE_NW4A2_17", + "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", + "PCIE_NW2A3_0", + "PCIE_WW4A3_16", + "PCIE_CTRL0_R_18", + "PCIE_SE4BEG1_11", + "PCIE_SE4BEG1_13", + "PCIE_TRNRDLLPDATA14", + "PCIE_LOGIC_OUTS_B20_L_12", + "PCIE_LOGIC_OUTS_B5_L_6", + "PCIE_SE4C2_1", + "PCIE_CLK0_L_2", + "PCIE_LOGIC_OUTS_B4_R_4", + "PCIE_EE4B3_4", + "PCIE_CFGDEVID4", + "PCIE_MIMRXRDATA31", + "PCIE_LOGIC_OUTS_B12_R_14", + "PCIE_SE4BEG2_4", + "PCIE_EE2BEG1_16", + "PCIE_LOGIC_OUTS_B11_L_3", + "PCIE_IMUX1_R_14", + "PCIE_MIMTXWDATA19", + "PCIE_LOGIC_OUTS_B8_R_14", + "PCIE_EE2A1_14", + "PCIE_LOGIC_OUTS_B13_R_17", + "PCIE_DBGVECB56", + "PCIE_IMUX27_L_9", + "PCIE_FAN5_R_14", + "PCIE_BLOCK_OUTS_B2_L_5", + "PCIE_IMUX13_R_4", + "PCIE_WW2A3_8", + "PCIE_WW4A1_9", + "PCIE_TL2ERRMALFORMED", + "PCIE_WR1END2_0", + "PCIE_EE4C2_10", + "PCIE_IMUX0_L_10", + "PCIE_TRNTD23", + "PCIE_SE4C0_5", + "PCIE_EE2BEG0_7", + "PCIE_PIPETX5CHARISK1", + "PCIE_LOGIC_OUTS_B18_R_11", + "PCIE_WW4B3_4", + "PCIE_WW4C1_0", + "PCIE_FAN6_L_16", + "PCIE_MIMRXRDATA36", + "PCIE_NW4END3_5", + "PCIE_IMUX24_R_2", + "PCIE_EE4A1_15", + "PCIE_FAN1_R_5", + "PCIE_LOGIC_OUTS_B14_L_6", + "PCIE_IMUX30_R_7", + "PCIE_LOGIC_OUTS_B5_L_3", + "PCIE_EE4A2_11", + "PCIE_PIPERX0CHANISALIGNED", + "PCIE_TRNRD55", + "PCIE_CFGERRAERHEADERLOG62", + "PCIE_WR1END1_0", + "PCIE_LOGIC_OUTS_B1_R_2", + "PCIE_DBGVECB40", + "PCIE_PLDBGVEC10", + "PCIE_BYP4_R_10", + "PCIE_BYP2_L_1", + "PCIE_NW4END1_3", + "PCIE_XILUNCONNOUT10", + "PCIE_FAN5_L_17", + "PCIE_WW2END0_1", + "PCIE_EE4C2_15", + "PCIE_LOGIC_OUTS_B21_R_19", + "PCIE_IMUX22_R_5", + "PCIE_IMUX18_L_0", + "PCIE_LOGIC_OUTS_B9_R_12", + "PCIE_TRNFCNPD8", + "PCIE_BYP4_R_16", + "PCIE_LH8_10", + "PCIE_CFGMGMTRDENN", + "PCIE_EE4A3_16", + "PCIE_LH4_8", + "PCIE_CFGERRAERHEADERLOG4", + "PCIE_CFGINTERRUPTDO1", + "PCIE_PIPERX2DATA12", + "PCIE_IMUX22_L_12", + "PCIE_WL1END1_9", + "PCIE_IMUX2_R_2", + "PCIE_IMUX20_L_3", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", + "PCIE_FAN2_R_17", + "PCIE_SW4A1_1", + "PCIE_CFGMGMTDO19", + "PCIE_SE4C1_6", + "PCIE_BYP4_L_3", + "PCIE_IMUX9_R_4", + "PCIE_BYP0_R_18", + "PCIE_CFGMGMTDI18", + "PCIE_TRNRD51", + "PCIE_CFGERRTLPCPLHEADER5", + "PCIE_WW4C1_17", + "PCIE_EE2A0_7", + "PCIE_WW2A1_4", + "PCIE_MIMTXRDATA39", + "PCIE_IMUX14_R_12", + "PCIE_IMUX30_L_7", + "PCIE_EL1BEG0_7", + "PCIE_WL1END1_7", + "PCIE_SW4A2_3", + "PCIE_WR1END1_14", + "PCIE_FAN6_L_19", + "PCIE_EE4C2_17", + "PCIE_FAN4_R_10", + "PCIE_LH6_13", + "PCIE_PIPERX7DATA9", + "PCIE_BYP2_R_10", + "PCIE_CFGERRAERHEADERLOG5", + "PCIE_BYP3_L_13", + "PCIE_FAN0_R_2", + "PCIE_PIPERX3DATA12", + "PCIE_EE2BEG0_12", + "PCIE_IMUX24_L_2", + "PCIE_IMUX18_R_14", + "PCIE_NE4BEG0_16", + "PCIE_EL1BEG3_12", + "PCIE_BLOCK_OUTS_B0_R_11", + "PCIE_IMUX4_L_5", + "PCIE_WW4A3_12", + "PCIE_IMUX34_L_11", + "PCIE_LOGIC_OUTS_B21_L_8", + "PCIE_MIMRXWDATA21", + "PCIE_LH8_9", + "PCIE_IMUX11_R_4", + "PCIE_IMUX23_R_10", + "PCIE_LOGIC_OUTS_B19_R_12", + "PCIE_PIPERX6STATUS1", + "PCIE_NW4A0_5", + "PCIE_LOGIC_OUTS_B0_L_12", + "PCIE_TRNTD5", + "PCIE_WW4END3_2", + "PCIE_PIPETX1DATA8", + "PCIE_FAN6_L_3", + "PCIE_PIPETX1DATA1", + "PCIE_FAN7_R_15", + "PCIE_CFGSUBSYSVENDID13", + "PCIE_CTRL0_R_16", + "PCIE_CTRL1_R_3", + "PCIE_BYP3_R_11", + "PCIE_SW4A0_19", + "PCIE_IMUX43_R_11", + "PCIE_WW4A1_0", + "PCIE_LOGIC_OUTS_B1_L_15", + "PCIE_LOGIC_OUTS_B23_L_16", + "PCIE_PIPERX2CHARISK1", + "PCIE_MIMTXWDATA61", + "PCIE_BLOCK_OUTS_B0_R_19", + "PCIE_WR1END3_18", + "PCIE_NE2A1_1", + "PCIE_EE4BEG1_6", + "PCIE_NW4A0_3", + "PCIE_WR1END2_13", + "PCIE_NE4C1_13", + "PCIE_SW2A2_9", + "PCIE_BYP0_R_5", + "PCIE_WW2END3_16", + "PCIE_IMUX25_R_17", + "PCIE_WW4A3_8", + "PCIE_IMUX39_R_17", + "PCIE_NE4BEG2_6", + "PCIE_PIPERX7DATA7", + "PCIE_CFGMSGDATA3", + "PCIE_LOGIC_OUTS_B13_R_3", + "PCIE_IMUX44_R_10", + "PCIE_CFGMSGDATA5", + "PCIE_DRPDI13", + "PCIE_LH6_7", + "PCIE_EL1BEG1_3", + "PCIE_DBGVECA23", + "PCIE_EE4BEG3_0", + "PCIE_SW2A3_7", + "PCIE_LH3_16", + "PCIE_LH4_11", + "PCIE_EE4A2_12", + "PCIE_MONITOR_P_7", + "PCIE_IMUX39_R_4", + "PCIE_LOGIC_OUTS_B1_R_16", + "PCIE_ER1BEG0_12", + "PCIE_IMUX5_L_3", + "PCIE_IMUX32_R_1", + "PCIE_TRNRDLLPDATA52", + "PCIE_LOGIC_OUTS_B19_R_4", + "PCIE_IMUX19_R_4", + "PCIE_IMUX30_R_19", + "PCIE_DRPDO12", + "PCIE_CFGTRANSACTIONADDR0", + "PCIE_CFGSUBSYSVENDID3", + "PCIE_TRNFCNPD3", + "PCIE_LOGIC_OUTS_B9_R_5", + "PCIE_DBGSCLRG", + "PCIE_FAN0_R_7", + "PCIE_IMUX31_L_14", + "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", + "PCIE_TRNFCNPH1", + "PCIE_PIPERX1STATUS0", + "PCIE_LOGIC_OUTS_B13_L_11", + "PCIE_IMUX5_R_8", + "PCIE_FAN6_L_14", + "PCIE_EE4B2_2", + "PCIE_TRNRD106", + "PCIE_IMUX15_L_11", + "PCIE_IMUX21_L_0", + "PCIE_PIPETX0DATA2", + "PCIE_MIMRXWDATA8", + "PCIE_IMUX3_L_15", + "PCIE_IMUX0_R_18", + "PCIE_LOGIC_OUTS_B14_R_7", + "PCIE_IMUX45_R_5", + "PCIE_CFGPMCSRPMEEN", + "PCIE_LOGIC_OUTS_B14_L_19", + "PCIE_IMUX10_L_8", + "PCIE_LOGIC_OUTS_B10_R_11", + "PCIE_IMUX37_L_9", + "PCIE_IMUX32_L_7", + "PCIE_SE4C0_4", + "PCIE_FAN3_R_19", + "PCIE_LOGIC_OUTS_B18_L_4", + "PCIE_CTRL0_R_10", + "PCIE_SE4C3_17", + "PCIE_CFGERRMCBLOCKEDN", + "PCIE_IMUX3_R_12", + "PCIE_MIMTXWADDR2", + "PCIE_IMUX12_L_2", + "PCIE_NW2A0_3", + "PCIE_ER1BEG3_2", + "PCIE_CFGERRTLPCPLHEADER40", + "PCIE_NW4A2_16", + "PCIE_SE2A0_13", + "PCIE_TRNRDLLPDATA33", + "PCIE_SE4C2_5", + "PCIE_LOGIC_OUTS_B22_L_15", + "PCIE_WW2A2_18", + "PCIE_IMUX39_L_13", + "PCIE_ER1BEG3_8", + "PCIE_SE2A2_2", + "PCIE_BYP6_R_3", + "PCIE_CFGPMCSRPOWERSTATE1", + "PCIE_LH12_1", + "PCIE_IMUX40_R_12", + "PCIE_IMUX18_R_1", + "PCIE_SE4BEG0_1", + "PCIE_MIMTXRDATA48", + "PCIE_DRPDO13", + "PCIE_TRNRDLLPDATA2", + "PCIE_WW4C3_13", + "PCIE_CLK0_R_3", + "PCIE_LOGIC_OUTS_B11_L_9", + "PCIE_PLLANEREVERSALMODE0", + "PCIE_SE4C2_11", + "PCIE_BLOCK_OUTS_B2_L_2", + "PCIE_IMUX37_R_11", + "PCIE_EE2BEG1_13", + "PCIE_LOGIC_OUTS_B2_R_4", + "PCIE_IMUX47_L_17", + "PCIE_IMUX31_R_5", + "PCIE_IMUX32_R_12", + "PCIE_IMUX45_L_19", + "PCIE_DBGVECA15", + "PCIE_PIPETX3DATA11", + "PCIE_EE4C1_16", + "PCIE_BYP4_R_2", + "PCIE_NW4A0_17", + "PCIE_NW2A0_10", + "PCIE_NW4END0_12", + "PCIE_IMUX17_R_1", + "PCIE_PIPETX7DATA5", + "PCIE_WW2END3_15", + "PCIE_DBGVECB16", + "PCIE_WW4END2_13", + "PCIE_FAN2_R_13", + "PCIE_TRNFCPD0", + "PCIE_LOGIC_OUTS_B12_L_12", + "PCIE_EE4BEG2_8", + "PCIE_LOGIC_OUTS_B23_R_11", + "PCIE_EE2BEG0_16", + "PCIE_PIPERX3STATUS0", + "PCIE_NW4END1_19", + "PCIE_NW4A3_15", + "PCIE_EE4B0_18", + "PCIE_LOGIC_OUTS_B2_R_0", + "PCIE_IMUX44_R_5", + "PCIE_FAN0_R_13", + "PCIE_IMUX27_R_19", + "PCIE_CFGMSGDATA9", + "PCIE_IMUX5_R_13", + "PCIE_IMUX37_R_19", + "PCIE_TRNRD22", + "PCIE_PIPETX4POWERDOWN1", + "PCIE_MIMTXWDATA47", + "PCIE_WW4B3_6", + "PCIE_FAN5_R_17", + "PCIE_TL2ERRHDR10", + "PCIE_IMUX38_R_8", + "PCIE_IMUX15_R_18", + "PCIE_TRNRD50", + "PCIE_SE2A1_3", + "PCIE_EE2BEG1_11", + "PCIE_IMUX15_L_8", + "PCIE_TRNRDLLPDATA1", + "PCIE_PIPERX6CHARISK0", + "PCIE_TRNTD108", + "PCIE_LOGIC_OUTS_B23_R_5", + "PCIE_IMUX26_R_8", + "PCIE_IMUX14_R_9", + "PCIE_NW4A0_2", + "PCIE_BYP5_R_1", + "PCIE_WW4A1_14", + "PCIE_PIPETX0DATA14", + "PCIE_DBGVECB31", + "PCIE_IMUX28_L_14", + "PCIE_IMUX21_R_12", + "PCIE_FAN2_R_8", + "PCIE_LOGIC_OUTS_B4_R_8", + "PCIE_EL1BEG1_8", + "PCIE_CFGERRAERHEADERLOG60", + "PCIE_CFGLINKCONTROLEXTENDEDSYNC", + "PCIE_IMUX6_L_2", + "PCIE_LOGIC_OUTS_B2_L_7", + "PCIE_PIPETX0DATA12", + "PCIE_IMUX22_R_8", + "PCIE_LOGIC_OUTS_B10_R_10", + "PCIE_WW2END3_11", + "PCIE_LOGIC_OUTS_B6_R_9", + "PCIE_LOGIC_OUTS_B11_L_12", + "PCIE_IMUX23_L_9", + "PCIE_NE4C1_12", + "PCIE_LOGIC_OUTS_B3_L_7", + "PCIE_TRNRDLLPDATA19", + "PCIE_IMUX12_R_10", + "PCIE_IMUX41_R_6", + "PCIE_LOGIC_OUTS_B20_R_10", + "PCIE_IMUX36_R_4", + "PCIE_SE2A3_9", + "PCIE_TRNTD120", + "PCIE_BYP7_L_17", + "PCIE_IMUX31_R_7", + "PCIE_DBGVECB48", + "PCIE_ER1BEG3_9", + "PCIE_IMUX1_R_9", + "PCIE_IMUX8_L_7", + "PCIE_NE4C3_14", + "PCIE_LOGIC_OUTS_B12_L_4", + "PCIE_BYP1_L_19", + "PCIE_FAN1_L_9", + "PCIE_CFGMGMTDI8", + "PCIE_LOGIC_OUTS_B12_R_7", + "PCIE_DBGVECB63", + "PCIE_CFGSUBSYSID9", + "PCIE_NE2A2_8", + "PCIE_IMUX8_R_12", + "PCIE_BLOCK_OUTS_B0_R_18", + "PCIE_LH7_18", + "PCIE_NW4A0_10", + "PCIE_IMUX32_R_16", + "PCIE_WW4C1_12", + "PCIE_FAN4_R_3", + "PCIE_CFGSUBSYSID11", + "PCIE_CFGDEVID11", + "PCIE_WW4A3_17", + "PCIE_EL1BEG3_11", + "PCIE_IMUX42_L_11", + "PCIE_LOGIC_OUTS_B10_L_8", + "PCIE_BLOCK_OUTS_B1_R_16", + "PCIE_WL1END3_15", + "PCIE_BYP0_L_1", + "PCIE_MIMTXRADDR9", + "PCIE_IMUX24_R_7", + "PCIE_IMUX14_L_10", + "PCIE_EE4BEG1_19", + "PCIE_LH9_6", + "PCIE_IMUX7_R_4", + "PCIE_WR1END0_12", + "PCIE_CFGREVID1", + "PCIE_LOGIC_OUTS_B0_R_16", + "PCIE_IMUX19_R_2", + "PCIE_IMUX9_R_9", + "PCIE_EE4C0_9", + "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", + "PCIE_LH9_3", + "PCIE_PIPERX6DATA4", + "PCIE_PIPERX4STATUS2", + "PCIE_IMUX42_L_17", + "PCIE_IMUX42_L_5", + "PCIE_CLK0_R_11", + "PCIE_DBGVECA20", + "PCIE_IMUX8_R_11", + "PCIE_LOGIC_OUTS_B14_R_1", + "PCIE_MIMRXWDATA10", + "PCIE_WW4A1_18", + "PCIE_IMUX46_L_12", + "PCIE_IMUX3_R_14", + "PCIE_IMUX40_L_2", + "PCIE_WL1END1_12", + "PCIE_IMUX41_L_14", + "PCIE_SW4A3_11", + "PCIE_ER1BEG3_15", + "PCIE_EL1BEG3_6", + "PCIE_IMUX19_R_17", + "PCIE_IMUX13_R_18", + "PCIE_TRNTD106", + "PCIE_CMRSTN", + "PCIE_IMUX16_R_17", + "PCIE_CFGSUBSYSID4", + "PCIE_FAN6_L_4", + "PCIE_DBGVECA33", + "PCIE_PIPETX5DATA8", + "PCIE_NW2A3_3", + "PCIE_LOGIC_OUTS_B16_L_7", + "PCIE_TRNFCCPLD11", + "PCIE_PIPERX0DATA3", + "PCIE_PIPERX7DATA2", + "PCIE_CFGERRPOISONEDN", + "PCIE_SE4C3_18", + "PCIE_IMUX4_R_0", + "PCIE_PIPETX6DATA14", + "PCIE_WW4B1_12", + "PCIE_BYP2_L_18", + "PCIE_TRNFCPH6", + "PCIE_WR1END2_11", + "PCIE_MIMTXRDATA43", + "PCIE_PL2DIRECTEDLSTATE1", + "PCIE_LOGIC_OUTS_B1_L_18", + "PCIE_LOGIC_OUTS_B3_L_12", + "PCIE_CTRL0_R_13", + "PCIE_NW4A2_18", + "PCIE_LOGIC_OUTS_B9_L_5", + "PCIE_WW2A2_19", + "PCIE_EE2BEG0_4", + "PCIE_WW4C1_6", + "PCIE_BLOCK_OUTS_B3_R_7", + "PCIE_WW4C0_2", + "PCIE_FAN3_L_10", + "PCIE_LOGIC_OUTS_B1_L_6", + "PCIE_NE4BEG2_18", + "PCIE_LOGIC_OUTS_B17_R_2", + "PCIE_FAN3_R_12", + "PCIE_TRNRD54", + "PCIE_WR1END1_10", + "PCIE_SW4END2_9", + "PCIE_CFGLINKSTATUSLINKTRAINING", + "PCIE_LOGIC_OUTS_B22_L_1", + "PCIE_TRNFCCPLD5", + "PCIE_IMUX45_L_4", + "PCIE_CFGPMRCVASREQL1N", + "PCIE_SE2A3_15", + "PCIE_BYP3_R_18", + "PCIE_IMUX2_L_10", + "PCIE_BYP4_R_18", + "PCIE_FAN2_R_7", + "PCIE_LOGIC_OUTS_B13_L_3", + "PCIE_IMUX1_R_8", + "PCIE_FAN3_R_8", + "PCIE_PIPETX2ELECIDLE", + "PCIE_IMUX5_L_19", + "PCIE_BYP4_R_7", + "PCIE_IMUX21_R_6", + "PCIE_FAN3_L_6", + "PCIE_TRNRNPOK", + "PCIE_DBGVECB37", + "PCIE_TRNFCPH4", + "PCIE_SE2A2_4", + "PCIE_MIMTXRDATA33", + "PCIE_IMUX5_L_2", + "PCIE_IMUX5_R_7", + "PCIE_LOGIC_OUTS_B3_L_19", + "PCIE_NE4C1_4", + "PCIE_EE4A0_4", + "PCIE_LOGIC_OUTS_B18_R_0", + "PCIE_LOGIC_OUTS_B4_L_16", + "PCIE_DBGVECB38", + "PCIE_PIPERX3DATA4", + "PCIE_LH5_2", + "PCIE_PIPETX5DATA3", + "PCIE_IMUX3_L_3", + "PCIE_IMUX14_R_11", + "PCIE_LOGIC_OUTS_B2_R_17", + "PCIE_LOGIC_OUTS_B13_R_14", + "PCIE_IMUX25_R_18", + "PCIE_IMUX46_R_5", + "PCIE_NE4C2_16", + "PCIE_MIMRXWDATA61", + "PCIE_TRNRD89", + "PCIE_SW2A0_7", + "PCIE_WW4A2_10", + "PCIE_CFGERRCORN", + "PCIE_CFGERRAERHEADERLOG70", + "PCIE_CFGTRANSACTIONADDR6", + "PCIE_IMUX7_L_4", + "PCIE_IMUX11_L_0", + "PCIE_IMUX23_R_11", + "PCIE_WW4C0_11", + "PCIE_BLOCK_OUTS_B0_L_3", + "PCIE_MIMRXWDATA40", + "PCIE_IMUX41_L_12", + "PCIE_MIMTXWDATA10", + "PCIE_MIMTXWADDR4", + "PCIE_IMUX8_R_17", + "PCIE_EE2BEG3_10", + "PCIE_SW2A0_14", + "PCIE_NE2A3_13", + "PCIE_TRNFCCPLD8", + "PCIE_XILUNCONNOUT30", + "PCIE_WW2END0_15", + "PCIE_EE4BEG2_18", + "PCIE_WW2A2_8", + "PCIE_TRNFCPH0", + "PCIE_CTRL0_L_17", + "PCIE_WW2A2_3", + "PCIE_TRNRFCPRET", + "PCIE_EE2A2_7", + "PCIE_BLOCK_OUTS_B1_L_10", + "PCIE_BLOCK_OUTS_B1_R_0", + "PCIE_WW4C0_9", + "PCIE_WW4END1_14", + "PCIE_CFGINTERRUPTDI5", + "PCIE_SW2A3_6", + "PCIE_BYP4_L_12", + "PCIE_TRNRDLLPDATA23", + "PCIE_CFGERRATOMICEGRESSBLOCKEDN", + "PCIE_DBGVECB26", + "PCIE_IMUX14_L_6", + "PCIE_CFGDEVSTATUSURDETECTED", + "PCIE_MIMTXWADDR8", + "PCIE_IMUX10_L_12", + "PCIE_MIMRXWDATA67", + "PCIE_IMUX44_R_9", + "PCIE_NE4BEG1_4", + "PCIE_LOGIC_OUTS_B12_R_11", + "PCIE_CFGMSGRECEIVEDASSERTINTA", + "PCIE_FAN6_L_18", + "PCIE_WW4A3_14", + "PCIE_EE4A1_9", + "PCIE_IMUX29_R_16", + "PCIE_IMUX12_R_19", + "PCIE_LOGIC_OUTS_B22_L_2", + "PCIE_IMUX24_R_5", + "PCIE_IMUX6_L_19", + "PCIE_CTRL0_L_14", + "PCIE_WL1END0_17", + "PCIE_NE2A0_12", + "PCIE_EE4B2_7", + "PCIE_EE4A0_16", + "PCIE_SE4C1_1", + "PCIE_WL1END1_19", + "PCIE_IMUX10_R_14", + "PCIE_LOGIC_OUTS_B22_L_8", + "PCIE_LH1_8", + "PCIE_NE4BEG2_5", + "PCIE_SE2A2_5", + "PCIE_PIPETX2DATA3", + "PCIE_WW4C3_9", + "PCIE_IMUX11_R_15", + "PCIE_WL1END2_4", + "PCIE_IMUX10_R_1", + "PCIE_DRPRDY", + "PCIE_NW2A3_4", + "PCIE_EE4B1_10", + "PCIE_IMUX40_R_6", + "PCIE_WW2A2_4", + "PCIE_DBGVECB29", + "PCIE_LOGIC_OUTS_B8_L_14", + "PCIE_TRNTD97", + "PCIE_CTRL1_R_1", + "PCIE_WL1END1_18", + "PCIE_IMUX30_R_18", + "PCIE_IMUX16_L_1", + "PCIE_DBGVECB41", + "PCIE_TRNTDLLPDATA26", + "PCIE_CFGMSGDATA1", + "PCIE_SW2A2_4", + "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", + "PCIE_EE4A0_7", + "PCIE_WW2A3_15", + "PCIE_DBGVECC3", + "PCIE_CFGMGMTDI14", + "PCIE_IMUX10_R_0", + "PCIE_IMUX40_L_8", + "PCIE_PL2DIRECTEDLSTATE2", + "PCIE_SW4A0_1", + "PCIE_LOGIC_OUTS_B23_R_1", + "PCIE_NE2A1_2", + "PCIE_LOGIC_OUTS_B22_L_11", + "PCIE_EE4B3_2", + "PCIE_LOGIC_OUTS_B8_L_9", + "PCIE_EDTCHANNELSIN2", + "PCIE_LOGIC_OUTS_B14_L_8", + "PCIE_USERCLKPREBUF", + "PCIE_CLK1_L_19", + "PCIE_WL1END2_14", + "PCIE_NW2A1_11", + "PCIE_EE2A0_3", + "PCIE_TRNRD87", + "PCIE_EE2BEG3_3", + "PCIE_WR1END3_14", + "PCIE_CLK1_R_15", + "PCIE_EE2BEG2_14", + "PCIE_SE4BEG0_7", + "PCIE_IMUX9_R_15", + "PCIE_FAN6_L_8", + "PCIE_BYP5_R_5", + "PCIE_DRPADDR7", + "PCIE_MONITOR_P_19", + "PCIE_WR1END3_16", + "PCIE_MIMRXRDATA16", + "PCIE_LOGIC_OUTS_B15_L_8", + "PCIE_MIMTXRDATA40", + "PCIE_FAN1_R_3", + "PCIE_IMUX27_R_15", + "PCIE_IMUX31_L_11", + "PCIE_LH4_18", + "PCIE_MIMRXWDATA38", + "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", + "PCIE_LH1_13", + "PCIE_EE4A1_4", + "PCIE_LOGIC_OUTS_B22_L_17", + "PCIE_WW4C1_11", + "PCIE_LOGIC_OUTS_B1_R_3", + "PCIE_NE4BEG3_2", + "PCIE_MIMTXWDATA45", + "PCIE_SW2A0_0", + "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", + "PCIE_CFGREVID0", + "PCIE_EE2A1_6", + "PCIE_WR1END0_13", + "PCIE_LOGIC_OUTS_B6_R_13", + "PCIE_FAN5_L_14", + "PCIE_FAN7_L_16", + "PCIE_XILUNCONNOUT14", + "PCIE_NE4C1_9", + "PCIE_MIMRXWDATA48", + "PCIE_BYP3_L_12", + "PCIE_CFGMSGRECEIVEDPMPME", + "PCIE_WW4C2_16", + "PCIE_LOGIC_OUTS_B20_L_14", + "PCIE_IMUX33_R_19", + "PCIE_EE4C3_15", + "PCIE_CFGERRAERHEADERLOG1", + "PCIE_IMUX10_R_13", + "PCIE_TRNRECRCERR", + "PCIE_BLOCK_OUTS_B2_R_3", + "PCIE_CFGERRAERHEADERLOG118", + "PCIE_IMUX29_R_9", + "PCIE_LOGIC_OUTS_B18_R_6", + "PCIE_BLOCK_OUTS_B1_R_8", + "PCIE_IMUX2_L_9", + "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", + "PCIE_LOGIC_OUTS_B0_L_14", + "PCIE_CTRL1_L_13", + "PCIE_CFGINTERRUPTMSIXFM", + "PCIE_IMUX36_R_0", + "PCIE_NW4A3_17", + "PCIE_LH9_14", + "PCIE_IMUX5_L_15", + "PCIE_BLOCK_OUTS_B0_L_8", + "PCIE_LOGIC_OUTS_B21_L_1", + "PCIE_IMUX45_L_0", + "PCIE_EE4C2_7", + "PCIE_TRNRD25", + "PCIE_IMUX15_L_7", + "PCIE_IMUX37_L_0", + "PCIE_BYP4_R_8", + "PCIE_DBGSCLRC", + "PCIE_IMUX5_L_16", + "PCIE_LOGIC_OUTS_B14_L_13", + "PCIE_EL1BEG1_9", + "PCIE_SW2A0_13", + "PCIE_SE4C1_9", + "PCIE_EE2A0_13", + "PCIE_TRNTCFGGNT", + "PCIE_LOGIC_OUTS_B12_L_17", + "PCIE_NE4BEG3_13", + "PCIE_PIPERX6DATA6", + "PCIE_IMUX19_L_7", + "PCIE_NW4A3_1", + "PCIE_IMUX36_L_15", + "PCIE_PIPETX5DATA5", + "PCIE_EE4B3_9", + "PCIE_NE4BEG3_12", + "PCIE_IMUX47_R_8", + "PCIE_EE4BEG2_3", + "PCIE_PIPERX2DATA7", + "PCIE_BLOCK_OUTS_B2_R_4", + "PCIE_WW4C2_9", + "PCIE_TRNRD112", + "PCIE_MIMTXRDATA13", + "PCIE_CFGVCTCVCMAP0", + "PCIE_CFGDEVID3", + "PCIE_CTRL0_L_0", + "PCIE_NE4BEG1_19", + "PCIE_IMUX19_L_16", + "PCIE_SW4END0_18", + "PCIE_DRPDI15", + "PCIE_FAN7_R_18", + "PCIE_IMUX23_R_4", + "PCIE_IMUX37_R_14", + "PCIE_LOGIC_OUTS_B9_L_1", + "PCIE_MIMRXWDATA50", + "PCIE_PIPERX1DATA7", + "PCIE_FAN2_R_18", + "PCIE_NW4END1_1", + "PCIE_WW4A3_0", + "PCIE_BLOCK_OUTS_B2_R_6", + "PCIE_ER1BEG2_18", + "PCIE_MIMRXWDATA30", + "PCIE_BLOCK_OUTS_B1_L_15", + "PCIE_NE4BEG1_7", + "PCIE_WW4C1_10", + "PCIE_IMUX22_R_15", + "PCIE_CFGERRTLPCPLHEADER36", + "PCIE_LH8_6", + "PCIE_IMUX38_L_0", + "PCIE_FAN5_R_11", + "PCIE_IMUX16_R_4", + "PCIE_LOGIC_OUTS_B4_L_6", + "PCIE_NE4BEG0_17", + "PCIE_EE4B3_14", + "PCIE_CFGSUBSYSID0", + "PCIE_TL2ERRHDR3", + "PCIE_FAN4_R_9", + "PCIE_SW2A3_17", + "PCIE_TRNRDLLPSRCRDY0", + "PCIE_LH5_13", + "PCIE_CFGERRAERHEADERLOG36", + "PCIE_NW2A2_19", + "PCIE_LOGIC_OUTS_B22_R_3", + "PCIE_CFGMGMTDI25", + "PCIE_NW4END0_15", + "PCIE_BYP2_R_1", + "PCIE_LOGIC_OUTS_B6_L_18", + "PCIE_NE4BEG2_0", + "PCIE_FAN7_L_11", + "PCIE_PIPECLK", + "PCIE_SE2A3_0", + "PCIE_MIMRXWDATA15", + "PCIE_IMUX36_L_2", + "PCIE_TRNTD91", + "PCIE_IMUX24_R_12", + "PCIE_LOGIC_OUTS_B8_L_8", + "PCIE_EE2A3_3", + "PCIE_TRNRBARHIT4", + "PCIE_LOGIC_OUTS_B20_L_18", + "PCIE_IMUX16_L_3", + "PCIE_TRNFCCPLD1", + "PCIE_IMUX24_R_3", + "PCIE_EE4A3_1", + "PCIE_LOGIC_OUTS_B7_R_12", + "PCIE_WW2A1_18", + "PCIE_IMUX29_R_6", + "PCIE_SE4C0_11", + "PCIE_IMUX19_L_13", + "PCIE_IMUX19_R_18", + "PCIE_WW2END2_1", + "PCIE_IMUX37_L_15", + "PCIE_NE4C0_10", + "PCIE_LOGIC_OUTS_B6_L_14", + "PCIE_BLOCK_OUTS_B2_L_12", + "PCIE_CLK1_R_18", + "PCIE_LOGIC_OUTS_B21_L_16", + "PCIE_CFGDSN29", + "PCIE_IMUX33_R_12", + "PCIE_PIPERX0CHARISK1", + "PCIE_WW4A0_10", + "PCIE_TRNTD77", + "PCIE_CFGMSGRECEIVEDDEASSERTINTD", + "PCIE_CFGMGMTDWADDR1", + "PCIE_SE4C2_17", + "PCIE_CFGPMSENDPMETON", + "PCIE_NE4C0_16", + "PCIE_LOGIC_OUTS_B7_L_0", + "PCIE_SE2A1_8", + "PCIE_PIPETX5DATA15", + "PCIE_TRNTD116", + "PCIE_CFGINTERRUPTMMENABLE0", + "PCIE_IMUX18_L_2", + "PCIE_TRNRDLLPDATA46", + "PCIE_PL2LINKUP", + "PCIE_CFGERRTLPCPLHEADER30", + "PCIE_FAN6_L_15", + "PCIE_IMUX31_L_12", + "PCIE_PIPERX4DATA12", + "PCIE_MIMRXWDATA16", + "PCIE_CFGDSN14", + "PCIE_TRNRD120", + "PCIE_BYP4_L_6", + "PCIE_EL1BEG2_7", + "PCIE_LOGIC_OUTS_B20_R_19", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "PCIE_TRNRD85", + "PCIE_LOGIC_OUTS_B7_R_19", + "PCIE_DBGVECB32", + "PCIE_WW2A0_5", + "PCIE_IMUX36_L_14", + "PCIE_BYP5_L_7", + "PCIE_MIMRXRADDR0", + "PCIE_LOGIC_OUTS_B16_R_17", + "PCIE_IMUX23_R_14", + "PCIE_WW4C0_7", + "PCIE_FAN2_R_9", + "PCIE_NE2A1_4", + "PCIE_FAN1_R_8", + "PCIE_CFGMGMTDI26", + "PCIE_SW2A3_0", + "PCIE_DBGVECA61", + "PCIE_IMUX43_R_13", + "PCIE_CFGMGMTBYTEENN3", + "PCIE_NW4A3_5", + "PCIE_WW4END2_11", + "PCIE_IMUX6_L_3", + "PCIE_IMUX47_L_11", + "PCIE_IMUX29_R_3", + "PCIE_BLOCK_OUTS_B1_R_12", + "PCIE_IMUX31_R_12", + "PCIE_NW4A3_19", + "PCIE_CFGERRTLPCPLHEADER3", + "PCIE_BLOCK_OUTS_B2_L_0", + "PCIE_WW2END2_15", + "PCIE_FAN5_L_9", + "PCIE_MIMRXWDATA46", + "PCIE_EE4BEG0_19", + "PCIE_LOGIC_OUTS_B18_L_15", + "PCIE_PIPERX7DATA5", + "PCIE_PIPERX7STATUS1", + "PCIE_IMUX31_R_9", + "PCIE_IMUX40_L_0", + "PCIE_IMUX14_L_2", + "PCIE_SW4END0_0", + "PCIE_DBGVECB23", + "PCIE_PIPETX7DATA1", + "PCIE_CFGINTERRUPTDI0", + "PCIE_SW4END1_11", + "PCIE_WW4END0_5", + "PCIE_IMUX31_L_10", + "PCIE_WW4C1_19", + "PCIE_CLK0_R_14", + "PCIE_PIPERX3DATA3", + "PCIE_CFGERRTLPCPLHEADER37", + "PCIE_LOGIC_OUTS_B15_L_5", + "PCIE_LOGIC_OUTS_B0_L_4", + "PCIE_IMUX23_R_1", + "PCIE_IMUX18_R_2", + "PCIE_PIPETX7DATA4", + "PCIE_BYP0_R_10", + "PCIE_EE2A0_8", + "PCIE_IMUX3_L_7", + "PCIE_WW4END1_9", + "PCIE_SW4END2_14", + "PCIE_IMUX12_L_15", + "PCIE_SW4A3_17", + "PCIE_TRNRD119", + "PCIE_PL2DIRECTEDLSTATE4", + "PCIE_IMUX18_L_15", + "PCIE_MIMRXRDATA25", + "PCIE_EE4BEG3_3", + "PCIE_WW4B0_2", + "PCIE_WW4C1_15", + "PCIE_EE4A0_2", + "PCIE_SW4A0_7", + "PCIE_MIMRXWDATA29", + "PCIE_LOGIC_OUTS_B18_R_15", + "PCIE_SW4END1_16", + "PCIE_IMUX28_R_6", + "PCIE_IMUX19_R_10", + "PCIE_NE4C1_5", + "PCIE_DBGVECA4", + "PCIE_EL1BEG1_1", + "PCIE_LOGIC_OUTS_B9_R_10", + "PCIE_NW4END2_6", + "PCIE_CFGDSN58", + "PCIE_DBGVECB25", + "PCIE_IMUX39_L_9", + "PCIE_IMUX46_R_6", + "PCIE_BYP0_L_4", + "PCIE_EE4BEG2_5", + "PCIE_SW4END3_5", + "PCIE_WW2END1_18", + "PCIE_IMUX29_L_14", + "PCIE_MIMTXWDATA40", + "PCIE_LOGIC_OUTS_B15_R_16", + "PCIE_IMUX0_R_0", + "PCIE_MONITOR_N_16", + "PCIE_IMUX17_L_7", + "PCIE_PIPERX6VALID", + "PCIE_IMUX11_R_0", + "PCIE_FAN4_L_9", + "PCIE_CFGERRAERHEADERLOG87", + "PCIE_LH6_8", + "PCIE_PIPETX0DATA9", + "PCIE_IMUX3_R_15", + "PCIE_WR1END3_0", + "PCIE_PIPETX2DATA8", + "PCIE_TRNRD103", + "PCIE_PIPETX7COMPLIANCE", + "PCIE_PIPERX7ELECIDLE", + "PCIE_LOGIC_OUTS_B1_R_14", + "PCIE_PIPERX2STATUS0", + "PCIE_FAN3_R_1", + "PCIE_PIPETX1DATA10", + "PCIE_IMUX12_R_3", + "PCIE_IMUX22_L_8", + "PCIE_IMUX20_L_19", + "PCIE_IMUX12_R_16", + "PCIE_IMUX28_R_5", + "PCIE_LOGIC_OUTS_B16_R_12", + "PCIE_TRNRD86", + "PCIE_CFGDEVCONTROL2IDOCPLEN", + "PCIE_PIPERX7PHYSTATUS", + "PCIE_IMUX25_R_5", + "PCIE_TRNTDLLPDATA4", + "PCIE_BYP3_R_10", + "PCIE_LOGIC_OUTS_B11_L_10", + "PCIE_CTRL0_L_2", + "PCIE_LOGIC_OUTS_B6_L_12", + "PCIE_WW4B0_11", + "PCIE_BYP2_R_16", + "PCIE_BYP6_L_1", + "PCIE_SE4C3_15", + "PCIE_LOGIC_OUTS_B8_R_1", + "PCIE_CTRL0_L_6", + "PCIE_IMUX8_R_10", + "PCIE_CFGERRTLPCPLHEADER21", + "PCIE_NE4BEG3_1", + "PCIE_IMUX19_L_0", + "PCIE_IMUX26_L_1", + "PCIE_SE4BEG3_9", + "PCIE_FAN5_L_19", + "PCIE_LL2LINKSTATUS0", + "PCIE_IMUX6_R_17", + "PCIE_WW4A0_9", + "PCIE_IMUX5_R_0", + "PCIE_MIMTXWDATA26", + "PCIE_MIMTXWDATA57", + "PCIE_EE2BEG2_5", + "PCIE_BYP1_L_4", + "PCIE_LH11_9", + "PCIE_EE4BEG2_9", + "PCIE_IMUX28_L_10", + "PCIE_CFGINTERRUPTDO5", + "PCIE_LH12_4", + "PCIE_IMUX41_L_9", + "PCIE_EE4A2_1", + "PCIE_NW4END2_13", + "PCIE_BLOCK_OUTS_B2_L_16", + "PCIE_EE4A0_15", + "PCIE_LH2_8", + "PCIE_EL1BEG0_2", + "PCIE_DBGVECA6", + "PCIE_MIMTXRDATA64", + "PCIE_CFGDSN49", + "PCIE_LH9_16", + "PCIE_PIPETX7DATA15", + "PCIE_WR1END3_11", + "PCIE_NE4C2_1", + "PCIE_ER1BEG3_0", + "PCIE_IMUX1_R_17", + "PCIE_LH4_6", + "PCIE_MIMRXWDATA14", + "PCIE_LOGIC_OUTS_B23_L_4", + "PCIE_LOGIC_OUTS_B16_R_4", + "PCIE_LOGIC_OUTS_B12_L_3", + "PCIE_IMUX9_R_7", + "PCIE_TRNRD37", + "PCIE_EL1BEG2_15", + "PCIE_NW4END3_6", + "PCIE_IMUX40_R_15", + "PCIE_CFGDSN54", + "PCIE_NE4C3_10", + "PCIE_CFGPMRCVENTERL23N", + "PCIE_EE4A1_13", + "PCIE_NW4END0_17", + "PCIE_SW4END0_15", + "PCIE_CFGERRTLPCPLHEADER0", + "PCIE_IMUX26_L_14", + "PCIE_LH12_7", + "PCIE_PLTXPMSTATE2", + "PCIE_WR1END2_16", + "PCIE_CFGVENDID14", + "PCIE_EE4BEG3_13", + "PCIE_NE2A2_17", + "PCIE_IMUX39_L_3", + "PCIE_EE4A3_5", + "PCIE_IMUX27_L_17", + "PCIE_IMUX4_R_11", + "PCIE_IMUX10_R_18", + "PCIE_FAN6_L_2", + "PCIE_IMUX21_R_11", + "PCIE_IMUX28_L_2", + "PCIE_IMUX23_L_6", + "PCIE_IMUX18_L_6", + "PCIE_LH9_0", + "PCIE_IMUX31_L_4", + "PCIE_CFGREVID4", + "PCIE_IMUX35_R_7", + "PCIE_BLOCK_OUTS_B1_R_7", + "PCIE_CTRL0_R_6", + "PCIE_CFGAERECRCCHECKEN", + "PCIE_WR1END3_13", + "PCIE_IMUX29_R_2", + "PCIE_IMUX38_R_1", + "PCIE_NW2A0_4", + "PCIE_MIMTXRDATA56", + "PCIE_IMUX41_L_13", + "PCIE_LOGIC_OUTS_B13_L_1", + "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", + "PCIE_CFGERRAERHEADERLOG100", + "PCIE_IMUX33_R_15", + "PCIE_ER1BEG0_17", + "PCIE_NE4C2_7", + "PCIE_IMUX3_L_19", + "PCIE_WW2A0_2", + "PCIE_IMUX35_R_1", + "PCIE_FAN3_R_16", + "PCIE_IMUX32_L_6", + "PCIE_TRNRD29", + "PCIE_PIPETX1DATA11", + "PCIE_IMUX29_L_2", + "PCIE_CFGERRAERHEADERLOG40", + "PCIE_IMUX46_R_15", + "PCIE_LOGIC_OUTS_B22_R_19", + "PCIE_SE4C1_12", + "PCIE_TRNTREM0", + "PCIE_IMUX30_R_17", + "PCIE_FAN1_R_9", + "PCIE_BYP3_R_5", + "PCIE_NW2A3_13", + "PCIE_WR1END2_3", + "PCIE_IMUX35_L_7", + "PCIE_DBGVECA42", + "PCIE_LOGIC_OUTS_B17_R_3", + "PCIE_WW4A0_8", + "PCIE_BLOCK_OUTS_B1_L_18", + "PCIE_FAN2_R_6", + "PCIE_SE4C2_12", + "PCIE_IMUX21_L_12", + "PCIE_LOGIC_OUTS_B1_R_8", + "PCIE_IMUX2_R_3", + "PCIE_TRNTD119", + "PCIE_EDTCHANNELSOUT7", + "PCIE_SW4END1_12", + "PCIE_IMUX27_L_6", + "PCIE_IMUX6_L_9", + "PCIE_BYP1_L_17", + "PCIE_WW2A2_7", + "PCIE_PIPERX3DATA7", + "PCIE_IMUX30_L_17", + "PCIE_LH2_3", + "PCIE_DBGVECA63", + "PCIE_IMUX15_R_9", + "PCIE_LOGIC_OUTS_B17_R_19", + "PCIE_TRNTDLLPDATA0", + "PCIE_IMUX16_R_12", + "PCIE_IMUX41_R_5", + "PCIE_CFGERRAERHEADERLOG49", + "PCIE_WL1END2_0", + "PCIE_IMUX37_R_13", + "PCIE_WW2END0_17", + "PCIE_NE4BEG3_17", + "PCIE_IMUX46_R_17", + "PCIE_MIMRXWDATA6", + "PCIE_CFGINTERRUPTDI6", + "PCIE_EE4BEG0_3", + "PCIE_EE4A2_18", + "PCIE_LOGIC_OUTS_B6_L_16", + "PCIE_NE4BEG0_4", + "PCIE_MIMRXRDATA50", + "PCIE_TRNTBUFAV2", + "PCIE_EE2A3_2", + "PCIE_LOGIC_OUTS_B14_R_8", + "PCIE_LOGIC_OUTS_B19_L_0", + "PCIE_PIPETX7POWERDOWN1", + "PCIE_BYP7_L_0", + "PCIE_LOGIC_OUTS_B4_R_13", + "PCIE_FAN6_R_2", + "PCIE_WW2A1_17", + "PCIE_WW4C2_13", + "PCIE_PIPERX3STATUS2", + "PCIE_SW4A1_4", + "PCIE_LOGIC_OUTS_B14_R_5", + "PCIE_NE4BEG3_9", + "PCIE_FAN7_L_2", + "PCIE_PIPERX7DATA4", + "PCIE_MIMTXWADDR10", + "PCIE_SE4BEG1_4", + "PCIE_IMUX6_R_5", + "PCIE_TRNTD126", + "PCIE_SE4C2_3", + "PCIE_FAN3_L_5", + "PCIE_CFGERRAERHEADERLOG18", + "PCIE_EE2A1_3", + "PCIE_IMUX18_L_18", + "PCIE_LOGIC_OUTS_B14_R_15", + "PCIE_IMUX29_R_5", + "PCIE_IMUX16_R_2", + "PCIE_IMUX17_L_9", + "PCIE_LOGIC_OUTS_B11_R_8", + "PCIE_LOGIC_OUTS_B18_R_3", + "PCIE_PLDIRECTEDLINKWIDTH0", + "PCIE_CFGTRANSACTIONADDR5", + "PCIE_ER1BEG1_16", + "PCIE_IMUX28_L_9", + "PCIE_LOGIC_OUTS_B12_R_17", + "PCIE_IMUX46_L_3", + "PCIE_EE2BEG1_7", + "PCIE_NW4A0_0", + "PCIE_IMUX2_R_8", + "PCIE_LH10_17", + "PCIE_IMUX16_R_16", + "PCIE_NE4BEG2_15", + "PCIE_FAN4_L_4", + "PCIE_CFGERRAERHEADERLOG107", + "PCIE_MIMRXWDATA66", + "PCIE_TRNRD58", + "PCIE_IMUX44_R_7", + "PCIE_CFGSUBSYSID14", + "PCIE_SE4BEG1_16", + "PCIE_IMUX21_R_2", + "PCIE_LH1_12", + "PCIE_IMUX37_R_3", + "PCIE_TRNTERRDROP", + "PCIE_LOGIC_OUTS_B1_L_12", + "PCIE_PIPETX5ELECIDLE", + "PCIE_DBGVECB60", + "PCIE_NW2A3_7", + "PCIE_LOGIC_OUTS_B18_L_5", + "PCIE_LOGIC_OUTS_B6_L_11", + "PCIE_LOGIC_OUTS_B13_R_4", + "PCIE_EE2A1_13", + "PCIE_CFGERRMALFORMEDN", + "PCIE_IMUX12_R_11", + "PCIE_IMUX2_R_7", + "PCIE_DBGVECA31", + "PCIE_NW4A0_4", + "PCIE_BLOCK_OUTS_B3_R_17", + "PCIE_NW4A1_1", + "PCIE_SE4BEG0_8", + "PCIE_BYP1_L_13", + "PCIE_FAN2_L_9", + "PCIE_IMUX1_L_16", + "PCIE_LOGIC_OUTS_B20_L_9", + "PCIE_IMUX27_L_10", + "PCIE_ER1BEG0_3", + "PCIE_IMUX14_L_19", + "PCIE_CLK1_L_3", + "PCIE_CLK1_L_10", + "PCIE_SW4END2_19", + "PCIE_MIMRXWDATA4", + "PCIE_SW2A1_3", + "PCIE_IMUX1_R_13", + "PCIE_EE4B1_12", + "PCIE_TL2ASPMSUSPENDREQ", + "PCIE_EL1BEG3_7", + "PCIE_WR1END3_19", + "PCIE_LOGIC_OUTS_B4_R_14", + "PCIE_IMUX2_L_8", + "PCIE_IMUX25_L_10", + "PCIE_IMUX17_R_6", + "PCIE_SE4BEG2_0", + "PCIE_TRNTD18", + "PCIE_PIPERX2DATA2", + "PCIE_NW4A3_14", + "PCIE_MIMRXWDATA33", + "PCIE_WR1END3_10", + "PCIE_SE4BEG3_3", + "PCIE_TRNRD68", + "PCIE_LOGIC_OUTS_B4_R_6", + "PCIE_IMUX41_L_10", + "PCIE_PLDIRECTEDLTSSMNEW5", + "PCIE_LOGIC_OUTS_B15_L_10", + "PCIE_EDTCHANNELSIN3", + "PCIE_WW4B1_15", + "PCIE_BLOCK_OUTS_B1_L_13", + "PCIE_TRNTD11", + "PCIE_LOGIC_OUTS_B9_L_19", + "PCIE_LOGIC_OUTS_B18_R_5", + "PCIE_IMUX2_R_15", + "PCIE_SE4BEG1_7", + "PCIE_LOGIC_OUTS_B7_R_2", + "PCIE_BYP6_L_7", + "PCIE_SE2A3_8", + "PCIE_IMUX44_L_18", + "PCIE_IMUX3_R_7", + "PCIE_LH6_11", + "PCIE_LOGIC_OUTS_B8_L_4", + "PCIE_IMUX47_L_10", + "PCIE_TL2ERRHDR41", + "PCIE_WW4C0_3", + "PCIE_IMUX18_L_7", + "PCIE_LOGIC_OUTS_B16_L_11", + "PCIE_IMUX26_R_9", + "PCIE_SW4END3_13", + "PCIE_IMUX6_L_15", + "PCIE_IMUX41_R_0", + "PCIE_SW4END2_13", + "PCIE_PIPERX0DATA7", + "PCIE_LOGIC_OUTS_B22_R_15", + "PCIE_FAN4_L_0", + "PCIE_NW4END0_3", + "PCIE_PLRECEIVEDHOTRST", + "PCIE_SE2A2_10", + "PCIE_BYP7_L_6", + "PCIE_FAN4_L_6", + "PCIE_CLK1_R_11", + "PCIE_LOGIC_OUTS_B12_L_0", + "PCIE_SE4C2_15", + "PCIE_IMUX44_R_6", + "PCIE_EL1BEG0_16", + "PCIE_EE2A0_10", + "PCIE_WL1END0_14", + "PCIE_SW4A0_8", + "PCIE_WR1END0_7", + "PCIE_EE4B2_11", + "PCIE_NW4END2_3", + "PCIE_IMUX16_R_1", + "PCIE_IMUX17_R_11", + "PCIE_MIMRXRDATA59", + "PCIE_IMUX16_L_11", + "PCIE_NW2A2_11", + "PCIE_LH2_4", + "PCIE_WL1END0_1", + "PCIE_IMUX23_L_3", + "PCIE_MIMRXRADDR10", + "PCIE_FAN5_R_4", + "PCIE_PIPETX1POWERDOWN0", + "PCIE_PIPERX6DATA15", + "PCIE_CFGSUBSYSVENDID2", + "PCIE_SE4C0_15", + "PCIE_SW2A0_4", + "PCIE_SW4A1_3", + "PCIE_IMUX19_L_15", + "PCIE_WW4C2_4", + "PCIE_EE4A0_18", + "PCIE_LOGIC_OUTS_B12_R_13", + "PCIE_EE2BEG1_3", + "PCIE_LOGIC_OUTS_B19_R_13", + "PCIE_LH9_5", + "PCIE_IMUX8_R_5", + "PCIE_TRNRDLLPDATA39", + "PCIE_TRNRD92", + "PCIE_IMUX44_R_11", + "PCIE_TRNFCPD9", + "PCIE_SW2A2_3", + "PCIE_LOGIC_OUTS_B7_R_4", + "PCIE_WW4A1_15", + "PCIE_IMUX8_L_12", + "PCIE_TRNTDLLPDATA27", + "PCIE_IMUX27_R_8", + "PCIE_IMUX12_R_13", + "PCIE_MIMRXRDATA52", + "PCIE_WW4B1_19", + "PCIE_IMUX44_L_5", + "PCIE_WW4C3_10", + "PCIE_SE2A3_2", + "PCIE_IMUX30_R_11", + "PCIE_EE4C2_4", + "PCIE_TRNTD96", + "PCIE_WW2END3_2", + "PCIE_BLOCK_OUTS_B1_L_8", + "PCIE_WR1END2_2", + "PCIE_TRNTDLLPDATA12", + "PCIE_EE4BEG2_0", + "PCIE_FAN2_L_14", + "PCIE_WL1END3_11", + "PCIE_IMUX44_L_10", + "PCIE_BYP2_R_7", + "PCIE_SE4BEG2_7", + "PCIE_NW4END0_9", + "PCIE_PIPERX3STATUS1", + "PCIE_CFGLINKSTATUSCURRENTSPEED1", + "PCIE_EE2A2_17", + "PCIE_MIMRXRDATA48", + "PCIE_NE2A0_4", + "PCIE_IMUX11_L_2", + "PCIE_IMUX43_L_14", + "PCIE_LOGIC_OUTS_B20_R_4", + "PCIE_LOGIC_OUTS_B2_R_1", + "PCIE_TRNRD104", + "PCIE_IMUX37_R_12", + "PCIE_LOGIC_OUTS_B1_L_3", + "PCIE_CFGDSN22", + "PCIE_BLOCK_OUTS_B1_R_14", + "PCIE_NE4C3_8", + "PCIE_CFGMGMTDWADDR0", + "PCIE_SE4BEG0_11", + "PCIE_BYP1_R_11", + "PCIE_CFGDSN48", + "PCIE_LOGIC_OUTS_B18_R_10", + "PCIE_ER1BEG2_11", + "PCIE_NW2A0_11", + "PCIE_SE4BEG1_2", + "PCIE_LH8_4", + "PCIE_CFGDSN42", + "PCIE_LOGIC_OUTS_B22_L_5", + "PCIE_IMUX35_R_12", + "PCIE_IMUX0_R_5", + "PCIE_NE2A1_5", + "PCIE_FAN7_L_1", + "PCIE_IMUX26_R_11", + "PCIE_MIMTXWDATA53", + "PCIE_SE4BEG3_12", + "PCIE_IMUX13_R_1", + "PCIE_WW4B0_13", + "PCIE_TRNFCNPD5", + "PCIE_TRNFCSEL2", + "PCIE_EE2A2_12", + "PCIE_CFGDSDEVICENUMBER4", + "PCIE_DRPDI10", + "PCIE_LOGIC_OUTS_B2_L_8", + "PCIE_LOGIC_OUTS_B23_L_0", + "PCIE_CFGINTERRUPTMMENABLE2", + "PCIE_EE4BEG1_12", + "PCIE_TRNTD10", + "PCIE_EL1BEG0_5", + "PCIE_EE2BEG1_10", + "PCIE_LOGIC_OUTS_B6_R_18", + "PCIE_CFGDSN32", + "PCIE_FAN7_R_14", + "PCIE_LOGIC_OUTS_B21_L_11", + "PCIE_PIPETX4DATA14", + "PCIE_EDTCHANNELSOUT8", + "PCIE_LOGIC_OUTS_B9_R_9", + "PCIE_SW2A0_19", + "PCIE_IMUX46_L_9", + "PCIE_FAN3_L_1", + "PCIE_LOGIC_OUTS_B18_L_7", + "PCIE_IMUX22_L_17", + "PCIE_SW4A2_6", + "PCIE_NE2A2_0", + "PCIE_MIMTXWDATA44", + "PCIE_PIPERX4CHARISK1", + "PCIE_IMUX20_L_16", + "PCIE_LOGIC_OUTS_B2_R_8", + "PCIE_IMUX21_R_5", + "PCIE_CFGINTERRUPTASSERTN", + "PCIE_LOGIC_OUTS_B16_R_13", + "PCIE_TRNRDLLPDATA59", + "PCIE_CFGERRAERHEADERLOG102", + "PCIE_IMUX9_R_16", + "PCIE_LOGIC_OUTS_B5_R_17", + "PCIE_LH4_2", + "PCIE_EL1BEG3_10", + "PCIE_IMUX41_R_1", + "PCIE_NW4A0_15", + "PCIE_TRNRDLLPDATA25", + "PCIE_IMUX30_L_5", + "PCIE_LOGIC_OUTS_B4_L_14", + "PCIE_IMUX36_R_16", + "PCIE_LOGIC_OUTS_B21_R_9", + "PCIE_SW2A1_6", + "PCIE_IMUX44_R_0", + "PCIE_IMUX45_R_16", + "PCIE_NE2A0_1", + "PCIE_SW4A0_12", + "PCIE_IMUX32_L_1", + "PCIE_LOGIC_OUTS_B17_R_14", + "PCIE_IMUX27_R_12", + "PCIE_IMUX5_L_17", + "PCIE_EE2A1_12", + "PCIE_NE4BEG0_6", + "PCIE_EDTCHANNELSOUT5", + "PCIE_CFGMSGDATA8", + "PCIE_IMUX10_R_6", + "PCIE_WL1END3_3", + "PCIE_FAN6_L_13", + "PCIE_IMUX1_L_18", + "PCIE_BLOCK_OUTS_B0_R_17", + "PCIE_IMUX46_L_2", + "PCIE_IMUX8_L_0", + "PCIE_IMUX34_L_7", + "PCIE_EE2BEG3_14", + "PCIE_LOGIC_OUTS_B19_R_17", + "PCIE_PIPERX7DATA11", + "PCIE_CTRL1_L_7", + "PCIE_PIPETX6DATA2", + "PCIE_BYP1_R_14", + "PCIE_CFGERRAERHEADERLOG82", + "PCIE_FAN4_L_16", + "PCIE_IMUX34_L_2", + "PCIE_IMUX13_R_10", + "PCIE_EE4BEG3_19", + "PCIE_BLOCK_OUTS_B2_L_1", + "PCIE_LOGIC_OUTS_B11_L_18", + "PCIE_NW2A1_15", + "PCIE_SE4C3_4", + "PCIE_SW4END3_8", + "PCIE_CFGERRAERHEADERLOG114", + "PCIE_IMUX45_R_8", + "PCIE_ER1BEG1_8", + "PCIE_BYP1_R_0", + "PCIE_SE4C2_19", + "PCIE_NE4BEG0_15", + "PCIE_CTRL1_L_11", + "PCIE_EE2A2_11", + "PCIE_IMUX33_R_6", + "PCIE_CFGERRAERHEADERLOG44", + "PCIE_MONITOR_P_10", + "PCIE_WL1END3_2", + "PCIE_TRNRD16", + "PCIE_SW4A3_4", + "PCIE_IMUX32_L_11", + "PCIE_ER1BEG2_16", + "PCIE_IMUX19_R_5", + "PCIE_IMUX14_L_17", + "PCIE_WW4A0_19", + "PCIE_BYP2_R_8", + "PCIE_CFGERRAERHEADERLOG116", + "PCIE_IMUX35_R_9", + "PCIE_IMUX45_R_3", + "PCIE_LOGIC_OUTS_B10_L_12", + "PCIE_MONITOR_N_12", + "PCIE_NE4BEG2_7", + "PCIE_MIMTXWDATA11", + "PCIE_IMUX1_L_6", + "PCIE_TRNRD52", + "PCIE_CTRL0_R_14", + "PCIE_MIMTXWDATA32", + "PCIE_CFGDSDEVICENUMBER2", + "PCIE_EE4BEG1_3", + "PCIE_BYP6_L_16", + "PCIE_IMUX27_L_8", + "PCIE_WW4B0_16", + "PCIE_IMUX15_L_12", + "PCIE_WW4C1_1", + "PCIE_WL1END0_12", + "PCIE_CFGERRAERHEADERLOG126", + "PCIE_DRPADDR8", + "PCIE_LOGIC_OUTS_B5_L_15", + "PCIE_BLOCK_OUTS_B1_L_5", + "PCIE_SW4END3_7", + "PCIE_IMUX22_L_16", + "PCIE_IMUX26_R_1", + "PCIE_LOGIC_OUTS_B7_L_9", + "PCIE_WW4END1_0", + "PCIE_EL1BEG3_18", + "PCIE_IMUX19_L_3", + "PCIE_WW4C0_19", + "PCIE_EE4A3_8", + "PCIE_IMUX4_R_5", + "PCIE_IMUX21_L_7", + "PCIE_SE4C1_10", + "PCIE_NE4C3_19", + "PCIE_MONITOR_P_17", + "PCIE_IMUX3_R_16", + "PCIE_IMUX11_R_2", + "PCIE_IMUX21_R_1", + "PCIE_DBGVECA13", + "PCIE_WR1END1_13", + "PCIE_IMUX13_L_2", + "PCIE_LOGIC_OUTS_B2_R_14", + "PCIE_NW4END1_18", + "PCIE_IMUX30_L_8", + "PCIE_TRNFCCPLD4", + "PCIE_NE4C3_4", + "PCIE_CLK1_L_1", + "PCIE_PIPETXRESET", + "PCIE_EE4BEG1_16", + "PCIE_FAN6_R_16", + "PCIE_NW4END3_2", + "PCIE_CFGMSGDATA14", + "PCIE_LOGIC_OUTS_B8_L_17", + "PCIE_IMUX25_L_13", + "PCIE_BYP5_L_17", + "PCIE_EE2BEG3_9", + "PCIE_EE4A0_0", + "PCIE_IMUX0_L_8", + "PCIE_NE4BEG3_3", + "PCIE_MIMTXWDATA50", + "PCIE_FAN1_L_7", + "PCIE_SE4BEG3_2", + "PCIE_SW2A2_15", + "PCIE_IMUX45_L_12", + "PCIE_LOGIC_OUTS_B16_L_16", + "PCIE_PIPERX2DATA4", + "PCIE_IMUX35_L_11", + "PCIE_MIMTXRADDR8", + "PCIE_ER1BEG0_15", + "PCIE_CFGERRAERHEADERLOG15", + "PCIE_EE4B0_15", + "PCIE_NW4A0_19", + "PCIE_NW4A3_11", + "PCIE_WW4C3_7", + "PCIE_EL1BEG0_8", + "PCIE_IMUX37_R_8", + "PCIE_LOGIC_OUTS_B5_L_11", + "PCIE_IMUX39_L_14", + "PCIE_IMUX46_R_7", + "PCIE_IMUX25_L_7", + "PCIE_IMUX45_R_15", + "PCIE_IMUX18_L_8", + "PCIE_IMUX4_R_1", + "PCIE_WL1END1_17", + "PCIE_WW4C1_14", + "PCIE_PIPERX0CHARISK0", + "PCIE_BYP7_L_14", + "PCIE_WW2END2_9", + "PCIE_SE2A0_19", + "PCIE_MIMRXWDATA28", + "PCIE_PIPERX6PHYSTATUS", + "PCIE_SW2A1_7", + "PCIE_LOGIC_OUTS_B8_L_1", + "PCIE_IMUX37_L_3", + "PCIE_FAN6_R_19", + "PCIE_IMUX33_R_1", + "PCIE_IMUX22_R_6", + "PCIE_IMUX26_L_16", + "PCIE_IMUX33_R_5", + "PCIE_NW4A1_7", + "PCIE_IMUX12_L_17", + "PCIE_XILUNCONNOUT32", + "PCIE_CLK1_R_2", + "PCIE_IMUX37_L_13", + "PCIE_IMUX9_R_2", + "PCIE_EE4BEG0_11", + "PCIE_EE4BEG3_10", + "PCIE_CFGERRTLPCPLHEADER25", + "PCIE_CFGMGMTDI4", + "PCIE_EL1BEG2_6", + "PCIE_LL2RECEIVERERR", + "PCIE_LOGIC_OUTS_B13_R_2", + "PCIE_WL1END3_17", + "PCIE_IMUX25_L_3", + "PCIE_TRNFCPD1", + "PCIE_IMUX36_L_5", + "PCIE_IMUX10_L_10", + "PCIE_IMUX21_L_6", + "PCIE_CFGDSN26", + "PCIE_PIPETX7DATA12", + "PCIE_FAN3_R_14", + "PCIE_MIMRXWDATA37", + "PCIE_CTRL1_R_4", + "PCIE_TRNRD40", + "PCIE_SE4BEG3_15", + "PCIE_IMUX0_R_12", + "PCIE_BYP4_L_16", + "PCIE_SE4C3_14", + "PCIE_EE4BEG1_0", + "PCIE_TRNRD107", + "PCIE_PIPERX7DATA8", + "PCIE_BLOCK_OUTS_B2_L_9", + "PCIE_EL1BEG0_10", + "PCIE_LH4_14", + "PCIE_IMUX16_R_18", + "PCIE_IMUX33_L_5", + "PCIE_IMUX41_L_4", + "PCIE_IMUX15_L_4", + "PCIE_BYP5_L_6", + "PCIE_LOGIC_OUTS_B3_L_15", + "PCIE_LOGIC_OUTS_B3_L_9", + "PCIE_LH4_17", + "PCIE_IMUX3_L_11", + "PCIE_IMUX1_L_3", + "PCIE_FAN3_R_7", + "PCIE_LOGIC_OUTS_B13_L_10", + "PCIE_DBGVECC11", + "PCIE_MIMRXRADDR11", + "PCIE_WW4B1_10", + "PCIE_LL2LINKSTATUS3", + "PCIE_SW4END0_5", + "PCIE_LOGIC_OUTS_B10_R_4", + "PCIE_LOGIC_OUTS_B13_L_14", + "PCIE_IMUX15_L_19", + "PCIE_FAN5_L_0", + "PCIE_LOGIC_OUTS_B8_R_9", + "PCIE_LOGIC_OUTS_B10_R_17", + "PCIE_FAN7_L_8", + "PCIE_SE2A2_11", + "PCIE_NW4A3_7", + "PCIE_LOGIC_OUTS_B17_L_19", + "PCIE_IMUX36_L_0", + "PCIE_IMUX23_R_12", + "PCIE_IMUX9_L_15", + "PCIE_SW2A2_19", + "PCIE_LH9_13", + "PCIE_EE2A0_14", + "PCIE_LH4_13", + "PCIE_TL2ERRHDR62", + "PCIE_BYP7_R_16", + "PCIE_EE4B0_2", + "PCIE_LOGIC_OUTS_B22_L_16", + "PCIE_SW4END3_19", + "PCIE_MIMRXRDATA43", + "PCIE_LOGIC_OUTS_B17_L_13", + "PCIE_IMUX36_L_10", + "PCIE_FAN0_R_3", + "PCIE_IMUX40_L_15", + "PCIE_XILUNCONNOUT36", + "PCIE_DBGVECA21", + "PCIE_IMUX5_L_8", + "PCIE_WR1END3_8", + "PCIE_IMUX36_R_10", + "PCIE_SE2A2_9", + "PCIE_ER1BEG2_2", + "PCIE_TRNRDLLPDATA17", + "PCIE_IMUX20_L_18", + "PCIE_LOGIC_OUTS_B9_R_11", + "PCIE_LOGIC_OUTS_B19_L_13", + "PCIE_PL2RXPMSTATE1", + "PCIE_XILUNCONNOUT2", + "PCIE_IMUX23_R_3", + "PCIE_WW4B2_5", + "PCIE_DBGSCLRB", + "PCIE_NE4C1_15", + "PCIE_CLK1_L_7", + "PCIE_LOGIC_OUTS_B4_R_10", + "PCIE_EDTCHANNELSOUT6", + "PCIE_LH7_11", + "PCIE_NE2A0_7", + "PCIE_NE4C0_17", + "PCIE_MIMRXWDATA25", + "PCIE_LH9_17", + "PCIE_LH8_1", + "PCIE_MIMTXRDATA35", + "PCIE_LOGIC_OUTS_B5_R_11", + "PCIE_SE2A1_16", + "PCIE_NW4END0_6", + "PCIE_FAN3_R_15", + "PCIE_SW2A1_18", + "PCIE_LOGIC_OUTS_B23_R_18", + "PCIE_MIMRXRDATA1", + "PCIE_TL2ERRHDR49", + "PCIE_PIPERX4DATA11", + "PCIE_WW2END1_11", + "PCIE_IMUX12_L_16", + "PCIE_NW4END0_18", + "PCIE_BLOCK_OUTS_B2_L_15", + "PCIE_WR1END2_15", + "PCIE_IMUX16_L_17", + "PCIE_CTRL0_L_11", + "PCIE_MIMTXWADDR3", + "PCIE_IMUX43_R_3", + "PCIE_LOGIC_OUTS_B7_R_1", + "PCIE_LOGIC_OUTS_B10_R_14", + "PCIE_DBGVECB47", + "PCIE_EE4A3_19", + "PCIE_CTRL1_R_16", + "PCIE_NW4A2_3", + "PCIE_NW2A2_6", + "PCIE_WW4END2_14", + "PCIE_EDTCHANNELSIN1", + "PCIE_CFGTRANSACTIONADDR4", + "PCIE_IMUX13_L_5", + "PCIE_LOGIC_OUTS_B2_L_2", + "PCIE_IMUX1_R_7", + "PCIE_NW4END1_10", + "PCIE_EL1BEG0_13", + "PCIE_NE4BEG3_5", + "PCIE_IMUX7_R_17", + "PCIE_CTRL1_R_15", + "PCIE_SW4END2_1", + "PCIE_EE4B1_6", + "PCIE_TRNRD110", + "PCIE_SW4END2_2", + "PCIE_PLDBGVEC6", + "PCIE_LOGIC_OUTS_B2_R_10", + "PCIE_EE4A0_14", + "PCIE_MIMRXRDATA32", + "PCIE_NW2A2_16", + "PCIE_LH12_8", + "PCIE_WW2A0_13", + "PCIE_EE4BEG0_6", + "PCIE_WW2A1_11", + "PCIE_WL1END2_11", + "PCIE_IMUX29_L_17", + "PCIE_WW2A0_9", + "PCIE_EL1BEG0_12", + "PCIE_WL1END2_1", + "PCIE_IMUX19_L_14", + "PCIE_FAN4_L_8", + "PCIE_EE4B1_11", + "PCIE_IMUX10_R_16", + "PCIE_EE4B0_19", + "PCIE_LOGIC_OUTS_B12_L_16", + "PCIE_IMUX31_R_4", + "PCIE_IMUX11_R_18", + "PCIE_MIMTXRADDR4", + "PCIE_NW2A2_15", + "PCIE_LOGIC_OUTS_B14_R_11", + "PCIE_SE4BEG1_17", + "PCIE_IMUX39_L_5", + "PCIE_TRNRD26", + "PCIE_IMUX10_L_2", + "PCIE_WW4END0_1", + "PCIE_IMUX9_L_4", + "PCIE_NE4BEG1_10", + "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", + "PCIE_CFGMSGDATA4", + "PCIE_CFGMSGRECEIVEDPMETO", + "PCIE_IMUX32_L_17", + "PCIE_SE2A3_1", + "PCIE_IMUX9_R_11", + "PCIE_IMUX5_R_3", + "PCIE_WW4B3_11", + "PCIE_NW4END0_2", + "PCIE_IMUX27_L_4", + "PCIE_SW2A1_10", + "PCIE_MIMTXWDATA43", + "PCIE_IMUX29_R_17", + "PCIE_IMUX10_L_7", + "PCIE_SE4BEG3_11", + "PCIE_BYP0_L_19", + "PCIE_LOGIC_OUTS_B23_L_13", + "PCIE_SE4BEG3_0", + "PCIE_TRNRD69", + "PCIE_SW4A2_12", + "PCIE_CFGPMFORCESTATEENN", + "PCIE_FAN4_L_19", + "PCIE_IMUX11_L_10", + "PCIE_BYP6_L_19", + "PCIE_MONITOR_N_14", + "PCIE_WW4END3_12", + "PCIE_FAN1_R_18", + "PCIE_WL1END2_19", + "PCIE_EL1BEG3_3", + "PCIE_PIPERX1DATA15", + "PCIE_WW2A3_2", + "PCIE_IMUX24_L_15", + "PCIE_IMUX2_R_19", + "PCIE_BLOCK_OUTS_B0_R_7", + "PCIE_CTRL1_R_17", + "PCIE_WW2END3_7", + "PCIE_WW2A0_18", + "PCIE_BYP0_L_17", + "PCIE_LOGIC_OUTS_B9_R_13", + "PCIE_SE4C1_8", + "PCIE_CFGSUBSYSVENDID4", + "PCIE_LH5_0", + "PCIE_CFGMGMTDO3", + "PCIE_CFGSUBSYSVENDID15", + "PCIE_XILUNCONNOUT26", + "PCIE_SE4BEG3_17", + "PCIE_MIMTXRDATA7", + "PCIE_LH1_10", + "PCIE_LH10_1", + "PCIE_SW4END0_8", + "PCIE_CFGERRAERHEADERLOG9", + "PCIE_CFGDSBUSNUMBER1", + "PCIE_IMUX36_L_19", + "PCIE_TRNTD125", + "PCIE_IMUX23_R_16", + "PCIE_MONITOR_N_3", + "PCIE_CFGMSGDATA13", + "PCIE_TRNRD41", + "PCIE_IMUX25_R_16", + "PCIE_NE4C2_19", + "PCIE_TRNFCCPLH0", + "PCIE_DBGVECA49", + "PCIE_LOGIC_OUTS_B9_L_9", + "PCIE_DRPDI1", + "PCIE_EE4B3_18", + "PCIE_EE4C1_2", + "PCIE_EE4B3_0", + "PCIE_LOGIC_OUTS_B1_R_11", + "PCIE_LOGIC_OUTS_B17_L_7", + "PCIE_CFGDSN9", + "PCIE_IMUX6_R_3", + "PCIE_BYP3_L_0", + "PCIE_EE4BEG1_13", + "PCIE_WW4A3_19", + "PCIE_CFGINTERRUPTRDYN", + "PCIE_CFGERRAERHEADERLOG117", + "PCIE_WW4C3_8", + "PCIE_CFGMGMTDI10", + "PCIE_BYP5_R_19", + "PCIE_TRNRDLLPDATA21", + "PCIE_TRNTDLLPDATA21", + "PCIE_LOGIC_OUTS_B19_L_1", + "PCIE_IMUX6_L_13", + "PCIE_IMUX1_L_10", + "PCIE_LOGIC_OUTS_B10_L_5", + "PCIE_IMUX28_R_3", + "PCIE_FAN2_L_1", + "PCIE_PIPETXRATE", + "PCIE_DBGSCLRI", + "PCIE_NW2A2_5", + "PCIE_CTRL1_R_19", + "PCIE_CFGVENDID15", + "PCIE_LOGIC_OUTS_B16_L_13", + "PCIE_SE2A0_6", + "PCIE_LOGIC_OUTS_B0_L_6", + "PCIE_NE4BEG1_16", + "PCIE_PLLTSSMSTATE0", + "PCIE_TRNRD98", + "PCIE_FAN5_R_7", + "PCIE_TRNTD25", + "PCIE_PIPERX1VALID", + "PCIE_SW2A0_1", + "PCIE_BLOCK_OUTS_B2_L_19", + "PCIE_CLK1_R_8", + "PCIE_MIMRXRDATA11", + "PCIE_PIPETX7DATA3", + "PCIE_PIPETX0DATA15", + "PCIE_IMUX17_L_1", + "PCIE_BLOCK_OUTS_B3_L_1", + "PCIE_EE2BEG3_11", + "PCIE_ER1BEG2_5", + "PCIE_EE4A2_5", + "PCIE_IMUX47_L_8", + "PCIE_IMUX23_L_14", + "PCIE_DBGVECA30", + "PCIE_IMUX38_R_19", + "PCIE_MIMRXRDATA17", + "PCIE_IMUX38_L_9", + "PCIE_WW4B0_15", + "PCIE_EE2A3_7", + "PCIE_TL2ERRHDR44", + "PCIE_IMUX26_R_16", + "PCIE_IMUX19_L_2", + "PCIE_EE4C0_12", + "PCIE_SE4C3_9", + "PCIE_LOGIC_OUTS_B10_R_13", + "PCIE_NW4END3_13", + "PCIE_LL2SENDASREQL1", + "PCIE_NW2A0_9", + "PCIE_NE2A1_9", + "PCIE_SW4END0_2", + "PCIE_BLOCK_OUTS_B0_L_18", + "PCIE_IMUX14_L_7", + "PCIE_EE2BEG2_2", + "PCIE_NW2A2_13", + "PCIE_CFGMGMTDI30", + "PCIE_TRNFCPH2", + "PCIE_BLOCK_OUTS_B2_R_11", + "PCIE_LOGIC_OUTS_B13_R_5", + "PCIE_CFGMGMTWRREADONLYN", + "PCIE_LOGIC_OUTS_B4_L_1", + "PCIE_IMUX10_R_17", + "PCIE_ER1BEG1_5", + "PCIE_ER1BEG1_19", + "PCIE_IMUX37_L_19", + "PCIE_DBGVECB5", + "PCIE_BYP6_L_18", + "PCIE_IMUX26_L_2", + "PCIE_WW4B3_18", + "PCIE_CTRL1_L_9", + "PCIE_WW2A3_4", + "PCIE_IMUX20_R_17", + "PCIE_LOGIC_OUTS_B23_L_1", + "PCIE_ER1BEG2_12", + "PCIE_IMUX38_L_8", + "PCIE_MIMRXRDATA15", + "PCIE_ER1BEG3_6", + "PCIE_BYP6_R_1", + "PCIE_TRNTD92", + "PCIE_WW2A0_17", + "PCIE_DBGVECA5", + "PCIE_IMUX6_L_0", + "PCIE_FAN0_L_7", + "PCIE_TRNRD47", + "PCIE_EE4B2_6", + "PCIE_IMUX28_R_8", + "PCIE_IMUX24_L_8", + "PCIE_LOGIC_OUTS_B15_R_8", + "PCIE_NW2A1_6", + "PCIE_BYP4_R_6", + "PCIE_LOGIC_OUTS_B7_R_8", + "PCIE_IMUX2_L_2", + "PCIE_MONITOR_N_19", + "PCIE_TRNTDLLPDATA8", + "PCIE_CFGDSN53", + "PCIE_LH5_14", + "PCIE_TRNTD101", + "PCIE_LH5_9", + "PCIE_SW2A2_17", + "PCIE_WW4END0_3", + "PCIE_PIPETX3DATA12", + "PCIE_IMUX14_L_12", + "PCIE_BYP1_R_5", + "PCIE_IMUX22_L_3", + "PCIE_EE2A0_19", + "PCIE_BYP6_R_19", + "PCIE_TRNTD36", + "PCIE_CFGERRAERHEADERLOG31", + "PCIE_FAN6_R_18", + "PCIE_TRNRDLLPDATA26", + "PCIE_EE4C1_12", + "PCIE_PIPETX4DATA1", + "PCIE_IMUX12_L_10", + "PCIE_TRNFCCPLD10", + "PCIE_IMUX18_R_16", + "PCIE_SE4BEG1_18", + "PCIE_WW4A2_5", + "PCIE_NE2A3_18", + "PCIE_IMUX45_R_13", + "PCIE_IMUX27_R_4", + "PCIE_LOGIC_OUTS_B2_L_9", + "PCIE_BYP2_R_19", + "PCIE_EE4A1_16", + "PCIE_EE2BEG1_2", + "PCIE_WW2END2_3", + "PCIE_IMUX42_R_2", + "PCIE_IMUX40_R_7", + "PCIE_DRPDO9", + "PCIE_NE4C1_18", + "PCIE_DBGVECB54", + "PCIE_LOGIC_OUTS_B11_R_16", + "PCIE_SW4A1_13", + "PCIE_IMUX11_R_8", + "PCIE_IMUX28_R_12", + "PCIE_EDTUPDATE", + "PCIE_IMUX4_R_4", + "PCIE_SW4A3_3", + "PCIE_IMUX37_L_18", + "PCIE_MIMRXRDATA51", + "PCIE_CTRL0_R_5", + "PCIE_MIMTXWDATA64", + "PCIE_SE4BEG1_8", + "PCIE_ER1BEG0_14", + "PCIE_IMUX41_R_3", + "PCIE_SE2A2_3", + "PCIE_CFGVENDID10", + "PCIE_CFGVENDID5", + "PCIE_LH6_5", + "PCIE_IMUX25_R_14", + "PCIE_LOGIC_OUTS_B1_R_12", + "PCIE_IMUX21_L_17", + "PCIE_LOGIC_OUTS_B6_L_3", + "PCIE_FAN7_L_19", + "PCIE_LOGIC_OUTS_B0_R_10", + "PCIE_MIMTXWDATA46", + "PCIE_TRNREOF", + "PCIE_CFGDSN6", + "PCIE_LOGIC_OUTS_B15_L_3", + "PCIE_CLK1_L_16", + "PCIE_MIMRXRADDR8", + "PCIE_IMUX44_R_17", + "PCIE_LOGIC_OUTS_B21_R_4", + "PCIE_IMUX6_R_10", + "PCIE_IMUX33_R_17", + "PCIE_LOGIC_OUTS_B16_L_4", + "PCIE_CFGERRAERHEADERLOG94", + "PCIE_IMUX16_L_10", + "PCIE_WL1END2_3", + "PCIE_NE4C0_18", + "PCIE_LOGIC_OUTS_B12_L_11", + "PCIE_IMUX5_L_11", + "PCIE_WR1END1_18", + "PCIE_FAN0_L_12", + "PCIE_CFGROOTCONTROLPMEINTEN", + "PCIE_CFGMGMTDI31", + "PCIE_CFGMGMTDO2", + "PCIE_WW4C1_7", + "PCIE_SE2A0_0", + "PCIE_IMUX3_R_4", + "PCIE_IMUX35_L_8", + "PCIE_MIMTXWEN", + "PCIE_IMUX21_L_10", + "PCIE_LOGIC_OUTS_B6_L_17", + "PCIE_WW2END3_0", + "PCIE_IMUX47_L_12", + "PCIE_WR1END1_16", + "PCIE_CTRL0_R_17", + "PCIE_WW2END1_19", + "PCIE_DBGVECA62", + "PCIE_IMUX11_L_5", + "PCIE_LOGIC_OUTS_B4_R_7", + "PCIE_DBGVECC7", + "PCIE_WR1END2_10", + "PCIE_PLINITIALLINKWIDTH2", + "PCIE_DBGVECB11", + "PCIE_TRNTDLLPDATA15", + "PCIE_NE4C0_6", + "PCIE_IMUX35_R_19", + "PCIE_SE4C1_7", + "PCIE_IMUX12_R_6", + "PCIE_WR1END2_14", + "PCIE_CFGVENDID13", + "PCIE_MIMRXRDATA34", + "PCIE_NW4END3_18", + "PCIE_CFGSUBSYSVENDID7", + "PCIE_WW2END0_4", + "PCIE_IMUX7_R_1", + "PCIE_LOGIC_OUTS_B3_R_8", + "PCIE_SW4END1_3", + "PCIE_XILUNCONNOUT17", + "PCIE_WL1END0_8", + "PCIE_IMUX24_R_16", + "PCIE_CFGERRAERHEADERLOG91", + "PCIE_WW2A0_7", + "PCIE_CFGMGMTDI9", + "PCIE_LOGIC_OUTS_B17_R_10", + "PCIE_TRNTD112", + "PCIE_IMUX42_R_13", + "PCIE_DBGVECA45", + "PCIE_IMUX39_L_18", + "PCIE_ER1BEG2_0", + "PCIE_WW2A3_12", + "PCIE_LOGIC_OUTS_B14_L_10", + "PCIE_WW4B2_13", + "PCIE_BYP2_R_5", + "PCIE_PIPETX4POWERDOWN0", + "PCIE_BLOCK_OUTS_B3_R_2", + "PCIE_IMUX17_R_8", + "PCIE_BYP0_L_9", + "PCIE_WW4B1_13", + "PCIE_WR1END0_14", + "PCIE_DBGVECA53", + "PCIE_CTRL1_L_1", + "PCIE_MIMRXWDATA57", + "PCIE_NW2A0_8", + "PCIE_MIMTXWDATA7", + "PCIE_SW2A3_12", + "PCIE_IMUX32_R_2", + "PCIE_PLDIRECTEDLTSSMNEW1", + "PCIE_MIMRXRDATA20", + "PCIE_IMUX30_L_19", + "PCIE_LOGIC_OUTS_B13_R_8", + "PCIE_WW2END0_16", + "PCIE_CTRL1_L_10", + "PCIE_IMUX12_R_18", + "PCIE_IMUX33_L_18", + "PCIE_BYP3_L_9", + "PCIE_BYP6_R_4", + "PCIE_WW4C0_17", + "PCIE_BYP3_L_5", + "PCIE_EL1BEG0_4", + "PCIE_LH5_16", + "PCIE_TRNTD78", + "PCIE_SE2A1_17", + "PCIE_IMUX29_R_15", + "PCIE_IMUX36_L_9", + "PCIE_SW4A3_18", + "PCIE_IMUX8_R_1", + "PCIE_BYP3_L_15", + "PCIE_LOGIC_OUTS_B0_R_6", + "PCIE_IMUX24_L_12", + "PCIE_IMUX5_R_18", + "PCIE_NE2A2_15", + "PCIE_XILUNCONNOUT1", + "PCIE_FAN1_R_14", + "PCIE_TRNTBUFAV0", + "PCIE_EE2A2_6", + "PCIE_FAN2_R_16", + "PCIE_IMUX29_L_4", + "PCIE_CFGERRAERHEADERLOG104", + "PCIE_CFGERRTLPCPLHEADER20", + "PCIE_NW4A0_16", + "PCIE_IMUX24_R_18", + "PCIE_MIMTXWDATA21", + "PCIE_BYP6_L_10", + "PCIE_MIMRXWDATA20", + "PCIE_WW4A0_18", + "PCIE_SW2A1_19", + "PCIE_CLK0_R_0", + "PCIE_WW2A2_1", + "PCIE_TRNTDLLPDATA25", + "PCIE_SE4BEG2_14", + "PCIE_IMUX4_L_3", + "PCIE_LOGIC_OUTS_B12_R_6", + "PCIE_CFGERRAERHEADERLOG43", + "PCIE_TRNTD59", + "PCIE_LOGIC_OUTS_B19_L_10", + "PCIE_PIPERX2PHYSTATUS", + "PCIE_SW4A0_6", + "PCIE_WW2END0_0", + "PCIE_LOGIC_OUTS_B1_R_18", + "PCIE_FAN3_L_16", + "PCIE_PIPETX7POWERDOWN0", + "PCIE_EE4C3_0", + "PCIE_LOGIC_OUTS_B10_R_19", + "PCIE_CTRL0_R_2", + "PCIE_SW4A1_8", + "PCIE_WL1END0_5", + "PCIE_CFGDSN1", + "PCIE_LOGIC_OUTS_B5_L_5", + "PCIE_LOGIC_OUTS_B4_L_7", + "PCIE_NE4BEG0_14", + "PCIE_LOGIC_OUTS_B8_L_15", + "PCIE_SW4A0_5", + "PCIE_TRNTD35", + "PCIE_LH8_5", + "PCIE_MONITOR_P_8", + "PCIE_EE2A2_16", + "PCIE_FAN1_R_19", + "PCIE_LOGIC_OUTS_B15_R_1", + "PCIE_SE2A1_9", + "PCIE_PLDIRECTEDLINKCHANGE0", + "PCIE_WW4C3_18", + "PCIE_BYP0_L_15", + "PCIE_WW2A3_3", + "PCIE_IMUX7_R_6", + "PCIE_IMUX16_R_11", + "PCIE_WW4END3_14", + "PCIE_SW4END0_1", + "PCIE_WL1END3_0", + "PCIE_LOGIC_OUTS_B5_R_0", + "PCIE_PIPERX0DATA14", + "PCIE_PIPERX1DATA2", + "PCIE_FAN3_L_4", + "PCIE_IMUX46_R_0", + "PCIE_IMUX38_R_16", + "PCIE_SE4BEG2_16", + "PCIE_WW4END0_19", + "PCIE_LH12_12", + "PCIE_NE4BEG2_16", + "PCIE_IMUX43_R_6", + "PCIE_TRNRBARHIT3", + "PCIE_IMUX29_L_7", + "PCIE_LOGIC_OUTS_B22_R_7", + "PCIE_EE4BEG1_5", + "PCIE_IMUX4_L_0", + "PCIE_LOGIC_OUTS_B13_L_7", + "PCIE_PLLINKGEN2CAP", + "PCIE_IMUX29_L_13", + "PCIE_MIMRXWADDR6", + "PCIE_MIMTXWDATA6", + "PCIE_SE4C2_13", + "PCIE_IMUX44_L_0", + "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "PCIE_IMUX41_L_15", + "PCIE_LOGIC_OUTS_B12_L_8", + "PCIE_EE2A3_16", + "PCIE_CFGDSN61", + "PCIE_WW2END2_16", + "PCIE_TRNRDSTRDY", + "PCIE_LOGIC_OUTS_B20_L_8", + "PCIE_BLOCK_OUTS_B3_L_5", + "PCIE_WW4B3_2", + "PCIE_FAN4_R_12", + "PCIE_IMUX42_L_6", + "PCIE_WW4C1_3", + "PCIE_IMUX15_L_5", + "PCIE_WW4C3_2", + "PCIE_FAN0_L_19", + "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", + "PCIE_MIMTXRDATA5", + "PCIE_BYP7_L_9", + "PCIE_FAN3_R_4", + "PCIE_LOGIC_OUTS_B5_R_14", + "PCIE_LH10_13", + "PCIE_NW2A2_14", + "PCIE_CFGINTERRUPTSTATN", + "PCIE_FAN3_L_14", + "PCIE_SE2A0_5", + "PCIE_EE4A0_12", + "PCIE_IMUX34_L_0", + "PCIE_WW4B3_5", + "PCIE_LOGIC_OUTS_B11_L_17", + "PCIE_LOGIC_OUTS_B16_L_12", + "PCIE_CFGLINKCONTROLLINKDISABLE", + "PCIE_LOGIC_OUTS_B1_L_11", + "PCIE_NW4END3_8", + "PCIE_NE4BEG1_8", + "PCIE_IMUX43_L_10", + "PCIE_IMUX11_L_12", + "PCIE_IMUX38_L_14", + "PCIE_BYP6_R_17", + "PCIE_NE4C0_7", + "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", + "PCIE_MIMTXRDATA60", + "PCIE_IMUX43_L_11", + "PCIE_ER1BEG1_10", + "PCIE_TRNRD73", + "PCIE_SE4BEG1_19", + "PCIE_SE4C2_0", + "PCIE_PIPETX1COMPLIANCE", + "PCIE_CTRL0_L_5", + "PCIE_WW4C1_4", + "PCIE_MIMTXRDATA21", + "PCIE_LOGIC_OUTS_B23_L_15", + "PCIE_LOGIC_OUTS_B17_R_15", + "PCIE_CFGMSGRECEIVEDASSERTINTB", + "PCIE_IMUX7_L_11", + "PCIE_LH3_12", + "PCIE_WW4A0_3", + "PCIE_WW4A0_14", + "PCIE_TRNTBUFAV4", + "PCIE_WW2END2_11", + "PCIE_FAN6_L_0", + "PCIE_IMUX39_L_8", + "PCIE_IMUX4_L_17", + "PCIE_IMUX15_R_7", + "PCIE_BYP0_R_14", + "PCIE_IMUX7_R_15", + "PCIE_WW4C2_19", + "PCIE_IMUX28_R_7", + "PCIE_TRNRDLLPDATA5", + "PCIE_IMUX43_L_19", + "PCIE_IMUX21_L_18", + "PCIE_PIPERX0DATA4", + "PCIE_LH7_5", + "PCIE_NE2A0_17", + "PCIE_LOGIC_OUTS_B8_R_17", + "PCIE_WW4C3_1", + "PCIE_TRNTD19", + "PCIE_IMUX28_R_4", + "PCIE_NE4BEG2_4", + "PCIE_LOGIC_OUTS_B17_L_8", + "PCIE_PLINITIALLINKWIDTH1", + "PCIE_WR1END1_4", + "PCIE_NW2A3_11", + "PCIE_SW2A3_4", + "PCIE_TL2ERRHDR45", + "PCIE_LOGIC_OUTS_B19_L_3", + "PCIE_FAN4_L_10", + "PCIE_IMUX19_L_18", + "PCIE_BYP0_R_17", + "PCIE_IMUX18_R_5", + "PCIE_LOGIC_OUTS_B4_L_9", + "PCIE_IMUX20_L_6", + "PCIE_PL2RXELECIDLE", + "PCIE_IMUX44_R_18", + "PCIE_WW4C0_16", + "PCIE_LOGIC_OUTS_B7_L_16", + "PCIE_BYP1_L_10", + "PCIE_CFGERRAERHEADERLOG109", + "PCIE_LOGIC_OUTS_B19_R_15", + "PCIE_DBGVECB10", + "PCIE_NE4BEG2_12", + "PCIE_EE4B2_5", + "PCIE_PIPERX1CHARISK1", + "PCIE_WR1END0_18", + "PCIE_IMUX19_R_19", + "PCIE_MIMTXRADDR1", + "PCIE_IMUX9_R_6", + "PCIE_IMUX11_R_5", + "PCIE_LOGIC_OUTS_B2_R_11", + "PCIE_NW4END2_18", + "PCIE_BYP3_R_3", + "PCIE_IMUX5_R_19", + "PCIE_MIMRXRDATA57", + "PCIE_LOGIC_OUTS_B12_R_8", + "PCIE_CFGPORTNUMBER1", + "PCIE_CFGERRAERHEADERLOG22", + "PCIE_EE4BEG0_0", + "PCIE_MIMTXRDATA59", + "PCIE_LOGIC_OUTS_B19_L_16", + "PCIE_SE4C1_14", + "PCIE_LOGIC_OUTS_B0_L_15", + "PCIE_LOGIC_OUTS_B0_R_0", + "PCIE_NE4BEG1_1", + "PCIE_NE4C1_17", + "PCIE_WR1END2_18", + "PCIE_CFGERRAERHEADERLOG61", + "PCIE_IMUX5_R_11", + "PCIE_LH8_18", + "PCIE_IMUX36_L_3", + "PCIE_IMUX14_L_16", + "PCIE_EE4BEG2_15", + "PCIE_TRNTDLLPDATA17", + "PCIE_EE2BEG0_8", + "PCIE_IMUX46_R_8", + "PCIE_WW4END1_5", + "PCIE_ER1BEG1_14", + "PCIE_ER1BEG2_13", + "PCIE_LOGIC_OUTS_B9_L_13", + "PCIE_LH4_3", + "PCIE_EE4BEG0_17", + "PCIE_IMUX41_R_11", + "PCIE_WW2A3_16", + "PCIE_FAN4_R_6", + "PCIE_IMUX22_R_13", + "PCIE_IMUX42_R_18", + "PCIE_IMUX35_L_0", + "PCIE_NW4END0_7", + "PCIE_LOGIC_OUTS_B7_R_7", + "PCIE_IMUX5_L_12", + "PCIE_CFGMGMTDI15", + "PCIE_BYP5_L_13", + "PCIE_EE4BEG1_4", + "PCIE_IMUX32_L_9", + "PCIE_CMSTICKYRSTN", + "PCIE_LOGIC_OUTS_B3_L_11", + "PCIE_EE4C1_5", + "PCIE_BLOCK_OUTS_B0_R_12", + "PCIE_TRNFCCPLH4", + "PCIE_IMUX25_R_19", + "PCIE_EE4C0_1", + "PCIE_NW4A0_11", + "PCIE_IMUX16_R_13", + "PCIE_FAN4_L_15", + "PCIE_WW2A2_9", + "PCIE_CFGMSGRECEIVEDUNLOCK", + "PCIE_EE2BEG0_1", + "PCIE_WR1END1_17", + "PCIE_CTRL1_L_5", + "PCIE_WW4B2_2", + "PCIE_IMUX30_L_10", + "PCIE_IMUX20_R_15", + "PCIE_CFGDEVCONTROLMAXPAYLOAD2", + "PCIE_FAN4_R_16", + "PCIE_LOGIC_OUTS_B3_L_6", + "PCIE_LH12_10", + "PCIE_CFGMGMTDI29", + "PCIE_LH6_6", + "PCIE_IMUX7_R_13", + "PCIE_EL1BEG3_19", + "PCIE_NW4END1_6", + "PCIE_LOGIC_OUTS_B0_R_12", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "PCIE_WW4B2_17", + "PCIE_CTRL0_L_10", + "PCIE_CFGERRAERHEADERLOG12", + "PCIE_CFGMGMTDWADDR2", + "PCIE_IMUX35_L_13", + "PCIE_LH3_10", + "PCIE_SW2A3_15", + "PCIE_IMUX43_R_17", + "PCIE_LOGIC_OUTS_B23_L_14", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "PCIE_LOGIC_OUTS_B5_L_16", + "PCIE_PLLTSSMSTATE1", + "PCIE_NW4END3_7", + "PCIE_WR1END0_5", + "PCIE_SW4END2_5", + "PCIE_LH4_9", + "PCIE_LOGIC_OUTS_B7_R_16", + "PCIE_LOGIC_OUTS_B19_L_17", + "PCIE_FAN4_R_8", + "PCIE_CFGLINKSTATUSCURRENTSPEED0", + "PCIE_EL1BEG0_14", + "PCIE_CFGMSGRECEIVEDASSERTINTD", + "PCIE_SE2A3_5", + "PCIE_IMUX37_R_5", + "PCIE_PIPERX0DATA8", + "PCIE_IMUX38_R_4", + "PCIE_NW2A0_15", + "PCIE_PIPERX4STATUS1", + "PCIE_PIPERX5DATA15", + "PCIE_IMUX4_R_10", + "PCIE_IMUX20_R_19", + "PCIE_EE2BEG0_5", + "PCIE_NW4A3_4", + "PCIE_WR1END1_2", + "PCIE_NW2A0_14", + "PCIE_IMUX5_R_15", + "PCIE_EE2A3_17", + "PCIE_LOGIC_OUTS_B7_L_15", + "PCIE_IMUX18_L_17", + "PCIE_FAN7_L_13", + "PCIE_IMUX0_L_12", + "PCIE_LH5_8", + "PCIE_CFGREVID2", + "PCIE_WW2END0_6", + "PCIE_BYP5_R_17", + "PCIE_IMUX29_L_10", + "PCIE_FAN0_R_11", + "PCIE_IMUX25_R_10", + "PCIE_PIPERX1DATA10", + "PCIE_LOGIC_OUTS_B19_L_14", + "PCIE_EE4C1_14", + "PCIE_CFGDSBUSNUMBER4", + "PCIE_SE4BEG0_19", + "PCIE_EE4BEG2_17", + "PCIE_PIPETX7DATA7", + "PCIE_FAN3_R_0", + "PCIE_IMUX38_R_7", + "PCIE_SW4A3_8", + "PCIE_PIPETX5DATA4", + "PCIE_IMUX5_L_6", + "PCIE_WL1END0_6", + "PCIE_TRNFCNPD4", + "PCIE_NE4BEG2_1", + "PCIE_BYP5_L_14", + "PCIE_IMUX35_L_5", + "PCIE_IMUX2_L_12", + "PCIE_SE2A2_7", + "PCIE_EE2BEG1_5", + "PCIE_BLOCK_OUTS_B3_R_5", + "PCIE_IMUX30_R_3", + "PCIE_DBGVECA47", + "PCIE_CFGMGMTDI24", + "PCIE_IMUX42_R_7", + "PCIE_LOGIC_OUTS_B16_R_16", + "PCIE_MIMRXWDATA63", + "PCIE_TRNRDLLPDATA32", + "PCIE_NW2A3_18", + "PCIE_BLOCK_OUTS_B3_L_18", + "PCIE_MIMRXWDATA41", + "PCIE_LOGIC_OUTS_B14_L_2", + "PCIE_IMUX41_R_16", + "PCIE_IMUX2_R_0", + "PCIE_IMUX45_R_2", + "PCIE_IMUX33_R_13", + "PCIE_SW4END0_13", + "PCIE_WW4A3_5", + "PCIE_EE4BEG0_7", + "PCIE_IMUX47_R_18", + "PCIE_NE2A1_19", + "PCIE_MONITOR_P_2", + "PCIE_EE4B1_19", + "PCIE_MIMRXWDATA36", + "PCIE_CFGMGMTDO5", + "PCIE_IMUX4_L_15", + "PCIE_WL1END3_6", + "PCIE_EE4C2_16", + "PCIE_CFGMGMTDWADDR3", + "PCIE_BYP2_R_18", + "PCIE_XILUNCONNOUT8", + "PCIE_WR1END2_4", + "PCIE_BYP0_R_8", + "PCIE_IMUX29_L_3", + "PCIE_MIMRXRDATA39", + "PCIE_NE4C1_8", + "PCIE_SW2A2_16", + "PCIE_BYP0_R_9", + "PCIE_IMUX18_R_12", + "PCIE_TRNTD34", + "PCIE_LOGIC_OUTS_B18_R_13", + "PCIE_NE4C3_13", + "PCIE_CFGDSN13", + "PCIE_LOGIC_OUTS_B18_R_7", + "PCIE_LOGIC_OUTS_B20_L_6", + "PCIE_LOGIC_OUTS_B1_L_2", + "PCIE_BLOCK_OUTS_B3_R_15", + "PCIE_DRPDO6", + "PCIE_MIMRXWDATA58", + "PCIE_LOGIC_OUTS_B11_R_2", + "PCIE_IMUX41_L_17", + "PCIE_IMUX32_L_12", + "PCIE_IMUX23_L_17", + "PCIE_LOGIC_OUTS_B2_R_9", + "PCIE_CFGERRAERHEADERLOG41", + "PCIE_CFGDEVID0", + "PCIE_IMUX38_R_6", + "PCIE_CLK0_R_2", + "PCIE_IMUX43_R_8", + "PCIE_NE4BEG0_1", + "PCIE_CFGINTERRUPTDI1", + "PCIE_DBGVECB13", + "PCIE_NW2A2_8", + "PCIE_NE4C0_2", + "PCIE_WW2END1_1", + "PCIE_IMUX30_R_9", + "PCIE_TRNTD122", + "PCIE_NW4A1_0", + "PCIE_LOGIC_OUTS_B13_R_7", + "PCIE_CFGERRAERHEADERLOG39", + "PCIE_CFGSUBSYSID6", + "PCIE_EL1BEG1_7", + "PCIE_LH3_6", + "PCIE_IMUX3_R_18", + "PCIE_FAN1_R_13", + "PCIE_DBGVECA22", + "PCIE_IMUX30_L_6", + "PCIE_EE4BEG3_8", + "PCIE_CTRL1_R_7", + "PCIE_IMUX23_R_6", + "PCIE_LH11_1", + "PCIE_LOGIC_OUTS_B5_L_13", + "PCIE_NW4A1_6", + "PCIE_BYP0_L_5", + "PCIE_PLDIRECTEDLINKSPEED", + "PCIE_DBGVECB22", + "PCIE_IMUX16_L_5", + "PCIE_BYP5_R_8", + "PCIE_MIMRXWDATA39", + "PCIE_LOGIC_OUTS_B0_R_14", + "PCIE_BYP3_L_4", + "PCIE_IMUX36_R_12", + "PCIE_TRNRD43", + "PCIE_LH4_16", + "PCIE_IMUX27_L_19", + "PCIE_IMUX1_L_15", + "PCIE_IMUX16_R_9", + "PCIE_WW2A1_1", + "PCIE_LOGIC_OUTS_B20_R_3", + "PCIE_EE4B0_6", + "PCIE_MIMTXWDATA17", + "PCIE_PIPETX6DATA12", + "PCIE_EE2A0_18", + "PCIE_BLOCK_OUTS_B0_L_4", + "PCIE_CLK0_R_18", + "PCIE_LOGIC_OUTS_B0_L_2", + "PCIE_IMUX22_L_10", + "PCIE_LOGIC_OUTS_B0_R_1", + "PCIE_PIPETX2COMPLIANCE", + "PCIE_IMUX40_L_4", + "PCIE_TRNRD35", + "PCIE_LOGIC_OUTS_B0_L_7", + "PCIE_IMUX26_L_19", + "PCIE_NW4A2_10", + "PCIE_BYP0_L_12", + "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "PCIE_MIMTXRDATA15", + "PCIE_IMUX0_L_11", + "PCIE_EL1BEG2_11", + "PCIE_IMUX24_L_9", + "PCIE_XILUNCONNOUT21", + "PCIE_FAN5_L_11", + "PCIE_ER1BEG3_1", + "PCIE_IMUX18_R_10", + "PCIE_LOGIC_OUTS_B4_R_15", + "PCIE_FAN2_L_6", + "PCIE_TRNTD29", + "PCIE_LL2SENDENTERL23", + "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", + "PCIE_LOGIC_OUTS_B10_L_6", + "PCIE_IMUX20_L_8", + "PCIE_EE4A2_7", + "PCIE_LOGIC_OUTS_B22_R_9", + "PCIE_PIPETX1DATA15", + "PCIE_LOGIC_OUTS_B23_R_14", + "PCIE_LOGIC_OUTS_B0_L_18", + "PCIE_LOGIC_OUTS_B17_L_15", + "PCIE_IMUX25_R_8", + "PCIE_WW2END1_10", + "PCIE_ER1BEG3_5", + "PCIE_BLOCK_OUTS_B0_R_15", + "PCIE_IMUX38_L_18", + "PCIE_IMUX21_L_13", + "PCIE_NW2A2_0", + "PCIE_NE4BEG2_13", + "PCIE_EE2BEG1_6", + "PCIE_DBGVECB59", + "PCIE_SE2A1_0", + "PCIE_TRNFCNPD10", + "PCIE_IMUX16_R_8", + "PCIE_EE4BEG2_7", + "PCIE_XILUNCONNOUT37", + "PCIE_SE4C1_16", + "PCIE_SW4END3_0", + "PCIE_IMUX30_R_12", + "PCIE_LOGIC_OUTS_B6_L_0", + "PCIE_CFGMGMTDI22", + "PCIE_PIPETX1DATA13", + "PCIE_IMUX4_R_3", + "PCIE_CFGERRAERHEADERLOG113", + "PCIE_NE4C3_7", + "PCIE_TRNRD67", + "PCIE_TRNTD107", + "PCIE_WW4B0_8", + "PCIE_LOGIC_OUTS_B7_R_3", + "PCIE_LH12_3", + "PCIE_IMUX33_L_14", + "PCIE_IMUX4_L_9", + "PCIE_IMUX14_R_10", + "PCIE_BYP1_R_3", + "PCIE_IMUX7_L_10", + "PCIE_IMUX34_L_12", + "PCIE_EE4B2_18", + "PCIE_DBGVECB53", + "PCIE_MIMRXRADDR9", + "PCIE_WW4C1_13", + "PCIE_IMUX32_L_18", + "PCIE_EE4BEG0_13", + "PCIE_EE2BEG2_18", + "PCIE_MIMTXRDATA10", + "PCIE_IMUX31_L_8", + "PCIE_IMUX14_R_5", + "PCIE_EE2BEG1_14", + "PCIE_DBGVECA57", + "PCIE_TRNRDLLPDATA57", + "PCIE_IMUX39_R_1", + "PCIE_EE4A1_6", + "PCIE_NW4A0_12", + "PCIE_IMUX7_R_5", + "PCIE_PIPETX5DATA6", + "PCIE_IMUX38_L_2", + "PCIE_LOGIC_OUTS_B1_L_14", + "PCIE_IMUX26_L_0", + "PCIE_NE4C2_11", + "PCIE_TRNTD110", + "PCIE_SE4BEG2_5", + "PCIE_TRNRD13", + "PCIE_IMUX24_L_0", + "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", + "PCIE_IMUX37_R_15", + "PCIE_IMUX3_R_1", + "PCIE_LH12_19", + "PCIE_NE4BEG3_8", + "PCIE_TRNTD99", + "PCIE_IMUX10_R_15", + "PCIE_BYP4_L_5", + "PCIE_CFGMGMTDI11", + "PCIE_CFGLINKCONTROLRETRAINLINK", + "PCIE_MIMRXRDATA40", + "PCIE_ER1BEG3_18", + "PCIE_MIMRXRDATA62", + "PCIE_LOGIC_OUTS_B12_R_12", + "PCIE_IMUX25_R_9", + "PCIE_WW4A2_18", + "PCIE_MIMTXWDATA30", + "PCIE_IMUX18_L_13", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", + "PCIE_WW4B0_4", + "PCIE_MIMTXRDATA45", + "PCIE_LOGIC_OUTS_B13_L_2", + "PCIE_WL1END3_7", + "PCIE_IMUX21_R_4", + "PCIE_IMUX41_L_18", + "PCIE_FAN7_L_18", + "PCIE_LH11_18", + "PCIE_NE2A0_5", + "PCIE_PLDOWNSTREAMDEEMPHSOURCE", + "PCIE_ER1BEG3_19", + "PCIE_IMUX33_L_1", + "PCIE_NW4END1_8", + "PCIE_IMUX37_L_17", + "PCIE_MIMTXRADDR5", + "PCIE_PMVENABLEN", + "PCIE_FAN3_L_7", + "PCIE_TRNTDLLPDATA10", + "PCIE_PIPERX5ELECIDLE", + "PCIE_IMUX12_R_2", + "PCIE_ER1BEG2_3", + "PCIE_WW2END1_8", + "PCIE_LOGIC_OUTS_B11_R_5", + "PCIE_CFGERRTLPCPLHEADER41", + "PCIE_WW4END1_18", + "PCIE_IMUX17_L_15", + "PCIE_IMUX47_L_16", + "PCIE_EE4C2_13", + "PCIE_DBGVECA36", + "PCIE_LH6_4", + "PCIE_EL1BEG3_14", + "PCIE_MIMRXWDATA22", + "PCIE_TLRSTN", + "PCIE_CFGDSN15", + "PCIE_CFGDSBUSNUMBER3", + "PCIE_NE2A2_9", + "PCIE_NW2A3_16", + "PCIE_SW2A1_13", + "PCIE_NW4END3_9", + "PCIE_BLOCK_OUTS_B0_L_9", + "PCIE_CFGERRAERHEADERLOG78", + "PCIE_CFGERRTLPCPLHEADER19", + "PCIE_WL1END1_11", + "PCIE_WW4B3_19", + "PCIE_WR1END0_0", + "PCIE_LH10_14", + "PCIE_IMUX20_R_9", + "PCIE_PIPERX1PHYSTATUS", + "PCIE_WL1END2_8", + "PCIE_IMUX11_R_1", + "PCIE_IMUX14_R_2", + "PCIE_LOGIC_OUTS_B7_L_2", + "PCIE_IMUX6_R_0", + "PCIE_PIPETX4DATA7", + "PCIE_PIPERX3DATA11", + "PCIE_IMUX36_R_14", + "PCIE_LOGIC_OUTS_B19_R_10", + "PCIE_MIMTXRADDR0", + "PCIE_IMUX14_L_13", + "PCIE_BYP3_L_14", + "PCIE_IMUX20_L_13", + "PCIE_LOGIC_OUTS_B7_R_10", + "PCIE_CLK0_L_11", + "PCIE_TRNTDLLPDATA24", + "PCIE_CFGERRAERHEADERLOG11", + "PCIE_EE4BEG1_1", + "PCIE_LH11_4", + "PCIE_IMUX0_R_14", + "PCIE_PIPERX5DATA12", + "PCIE_LOGIC_OUTS_B18_L_9", + "PCIE_MIMTXRDATA8", + "PCIE_CTRL1_R_5", + "PCIE_LOGIC_OUTS_B0_L_9", + "PCIE_EL1BEG3_1", + "PCIE_MIMRXRDATA30", + "PCIE_IMUX44_R_3", + "PCIE_SE4C1_17", + "PCIE_CLK1_R_13", + "PCIE_FAN2_R_5", + "PCIE_IMUX42_R_17", + "PCIE_EE2A2_10", + "PCIE_NW4END1_5", + "PCIE_LH9_4", + "PCIE_BLOCK_OUTS_B3_L_19", + "PCIE_NE4C3_17", + "PCIE_LOGIC_OUTS_B13_L_18", + "PCIE_BYP0_R_13", + "PCIE_TRNRDLLPDATA36", + "PCIE_LOGIC_OUTS_B3_R_10", + "PCIE_LOGIC_OUTS_B10_L_9", + "PCIE_LH5_17", + "PCIE_IMUX2_R_17", + "PCIE_BYP1_R_6", + "PCIE_FAN5_L_18", + "PCIE_MIMTXRDATA46", + "PCIE_MIMRXWADDR9", + "PCIE_IMUX33_L_16", + "PCIE_IMUX31_L_17", + "PCIE_LOGIC_OUTS_B4_L_4", + "PCIE_IMUX2_L_0", + "PCIE_SE4BEG3_14", + "PCIE_EE4BEG3_17", + "PCIE_IMUX9_R_18", + "PCIE_IMUX34_R_18", + "PCIE_SW4A0_15", + "PCIE_EL1BEG3_0", + "PCIE_SW4A2_11", + "PCIE_TRNTDLLPDATA18", + "PCIE_WW2A2_11", + "PCIE_EE2BEG3_12", + "PCIE_LL2REPLAYTOERR", + "PCIE_WW2A3_1", + "PCIE_LOGIC_OUTS_B2_L_13", + "PCIE_EE4BEG0_4", + "PCIE_IMUX45_R_6", + "PCIE_DBGMODE1", + "PCIE_CLK1_L_11", + "PCIE_SE4BEG2_3", + "PCIE_EE2BEG1_15", + "PCIE_IMUX1_R_5", + "PCIE_EE4A3_14", + "PCIE_PIPETX5CHARISK0", + "PCIE_PLTXPMSTATE0", + "PCIE_IMUX45_R_10", + "PCIE_IMUX30_R_8", + "PCIE_IMUX12_R_4", + "PCIE_BYP4_R_4", + "PCIE_SW2A3_10", + "PCIE_FAN6_R_12", + "PCIE_TRNFCNPH3", + "PCIE_CFGINTERRUPTDO6", + "PCIE_EE2BEG0_13", + "PCIE_CFGMGMTDO26", + "PCIE_NE2A1_14", + "PCIE_MIMRXRADDR4", + "PCIE_TRNFCSEL0", + "PCIE_LOGIC_OUTS_B1_L_16", + "PCIE_IMUX0_R_7", + "PCIE_LOGIC_OUTS_B6_R_5", + "PCIE_WW4B2_8", + "PCIE_TL2ERRHDR7", + "PCIE_BYP2_L_10", + "PCIE_PIPETX2DATA7", + "PCIE_PIPERX2VALID", + "PCIE_SW4END2_8", + "PCIE_LH3_9", + "PCIE_SW4A3_14", + "PCIE_IMUX13_R_12", + "PCIE_EE4A0_8", + "PCIE_IMUX15_L_9", + "PCIE_WR1END1_9", + "PCIE_LOGIC_OUTS_B17_R_18", + "PCIE_IMUX25_L_16", + "PCIE_LH12_11", + "PCIE_EE2BEG3_13", + "PCIE_LOGIC_OUTS_B18_R_18", + "PCIE_BYP7_R_8", + "PCIE_PIPERX6DATA3", + "PCIE_TL2ERRHDR25", + "PCIE_EE4B3_17", + "PCIE_TRNRDLLPDATA28", + "PCIE_IMUX9_L_18", + "PCIE_FAN7_L_3", + "PCIE_PIPERX4STATUS0", + "PCIE_IMUX41_R_7", + "PCIE_LOGIC_OUTS_B17_R_1", + "PCIE_PIPETX6DATA9", + "PCIE_LOGIC_OUTS_B12_L_13", + "PCIE_PIPETX3DATA1", + "PCIE_CLK0_R_8", + "PCIE_CFGMGMTDI13", + "PCIE_LH4_0", + "PCIE_CFGAERINTERRUPTMSGNUM2", + "PCIE_PIPETX4ELECIDLE", + "PCIE_IMUX45_L_5", + "PCIE_IMUX21_L_19", + "PCIE_IMUX44_L_13", + "PCIE_PIPETX2DATA4", + "PCIE_SE2A2_6", + "PCIE_WW2END3_10", + "PCIE_WW4END2_17", + "PCIE_LOGIC_OUTS_B7_L_3", + "PCIE_WR1END0_16", + "PCIE_EE4A3_4", + "PCIE_LOGIC_OUTS_B20_L_2", + "PCIE_WW2END0_10", + "PCIE_EE4A0_10", + "PCIE_LOGIC_OUTS_B9_L_11", + "PCIE_WL1END0_16", + "PCIE_EL1BEG2_9", + "PCIE_LOGIC_OUTS_B9_R_14", + "PCIE_LOGIC_OUTS_B10_L_2", + "PCIE_PIPERX1DATA14", + "PCIE_TRNRD59", + "PCIE_LOGIC_OUTS_B23_L_9", + "PCIE_IMUX31_L_5", + "PCIE_IMUX26_R_5", + "PCIE_IMUX8_R_15", + "PCIE_CFGAERECRCGENEN", + "PCIE_SE4C2_8", + "PCIE_NE4C0_13", + "PCIE_IMUX8_R_16", + "PCIE_LOGIC_OUTS_B17_L_17", + "PCIE_NE4C2_6", + "PCIE_TL2ERRHDR11", + "PCIE_BLOCK_OUTS_B0_L_14", + "PCIE_IMUX26_R_14", + "PCIE_MONITOR_P_5", + "PCIE_EE4C2_18", + "PCIE_BYP4_L_11", + "PCIE_PIPERX7DATA13", + "PCIE_IMUX22_R_10", + "PCIE_EE4A2_19", + "PCIE_IMUX36_R_3", + "PCIE_PIPERX0DATA9", + "PCIE_IMUX28_L_16", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", + "PCIE_TRNTDLLPDATA5", + "PCIE_LOGIC_OUTS_B19_R_11", + "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", + "PCIE_EE4C3_18", + "PCIE_IMUX17_L_3", + "PCIE_FAN4_L_1", + "PCIE_MIMRXRADDR7", + "PCIE_CFGSUBSYSVENDID9", + "PCIE_PL2L0REQ", + "PCIE_DBGVECC9", + "PCIE_NW2A0_0", + "PCIE_ER1BEG2_8", + "PCIE_FAN2_L_4", + "PCIE_IMUX43_L_5", + "PCIE_SE4BEG0_10", + "PCIE_IMUX22_R_9", + "PCIE_CFGERRTLPCPLHEADER43", + "PCIE_TRNTD1", + "PCIE_IMUX35_R_18", + "PCIE_WW4B0_17", + "PCIE_LOGIC_OUTS_B22_R_13", + "PCIE_MONITOR_N_9", + "PCIE_WW4B0_6", + "PCIE_LOGIC_OUTS_B16_L_5", + "PCIE_DBGVECB52", + "PCIE_BYP3_R_7", + "PCIE_CTRL0_R_7", + "PCIE_IMUX26_L_12", + "PCIE_IMUX2_L_6", + "PCIE_LOGIC_OUTS_B14_L_18", + "PCIE_CFGDEVCONTROLENABLERO", + "PCIE_DBGVECB24", + "PCIE_IMUX37_L_8", + "PCIE_CLK1_R_14", + "PCIE_PLRXPMSTATE0", + "PCIE_LOGIC_OUTS_B5_L_19", + "PCIE_EE4C2_5", + "PCIE_MIMTXWDATA52", + "PCIE_PIPERX2CHARISK0", + "PCIE_TRNFCNPD7", + "PCIE_EE2BEG3_18", + "PCIE_BYP6_L_4", + "PCIE_LOGIC_OUTS_B13_L_4", + "PCIE_PIPERX4CHARISK0", + "PCIE_CTRL1_R_14", + "PCIE_EE4A2_17", + "PCIE_WL1END2_9", + "PCIE_WL1END1_13", + "PCIE_LOGIC_OUTS_B20_R_0", + "PCIE_PIPERX5DATA8", + "PCIE_WW4B2_1", + "PCIE_CLK1_L_5", + "PCIE_MONITOR_N_10", + "PCIE_IMUX2_R_12", + "PCIE_EE2BEG2_0", + "PCIE_IMUX28_L_12", + "PCIE_LOGIC_OUTS_B10_L_17", + "PCIE_DBGVECA32", + "PCIE_MIMRXWDATA54", + "PCIE_IMUX41_L_2", + "PCIE_DBGVECB61", + "PCIE_PIPETX0POWERDOWN1", + "PCIE_CTRL0_L_3", + "PCIE_IMUX25_L_6", + "PCIE_NW4A0_1", + "PCIE_BYP7_R_3", + "PCIE_TRNFCNPH7", + "PCIE_PIPETX0DATA1", + "PCIE_BYP5_L_0", + "PCIE_LOGIC_OUTS_B16_R_11", + "PCIE_IMUX0_R_3", + "PCIE_NW2A1_4", + "PCIE_LOGIC_OUTS_B23_R_10", + "PCIE_LOGIC_OUTS_B20_R_9", + "PCIE_EE2BEG3_7", + "PCIE_IMUX46_L_15", + "PCIE_IMUX5_L_5", + "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", + "PCIE_CFGERRNORECOVERYN", + "PCIE_LOGIC_OUTS_B4_L_3", + "PCIE_IMUX46_L_0", + "PCIE_IMUX45_L_16", + "PCIE_IMUX14_R_0", + "PCIE_CFGINTERRUPTMSIXENABLE", + "PCIE_LOGIC_OUTS_B20_L_16", + "PCIE_LOGIC_OUTS_B1_R_4", + "PCIE_NE4C2_4", + "PCIE_IMUX10_L_14", + "PCIE_CFGERRTLPCPLHEADER28", + "PCIE_LOGIC_OUTS_B2_L_3", + "PCIE_WW4C2_7", + "PCIE_IMUX3_R_5", + "PCIE_LH10_19", + "PCIE_LOGIC_OUTS_B5_R_12", + "PCIE_IMUX26_R_12", + "PCIE_IMUX21_R_3", + "PCIE_IMUX5_R_4", + "PCIE_PIPETX3DATA7", + "PCIE_CFGERRAERHEADERLOG14", + "PCIE_FAN2_L_12", + "PCIE_CFGERRAERHEADERLOG32", + "PCIE_CFGMGMTDI12", + "PCIE_BYP7_L_1", + "PCIE_SW4END2_7", + "PCIE_FAN7_L_15", + "PCIE_WW4C3_3", + "PCIE_IMUX28_L_17", + "PCIE_EE2A1_4", + "PCIE_LH8_13", + "PCIE_IMUX40_R_4", + "PCIE_FAN0_R_4", + "PCIE_IMUX43_R_5", + "PCIE_FAN0_R_1", + "PCIE_SW2A1_0", + "PCIE_LOGIC_OUTS_B1_R_5", + "PCIE_EE2BEG3_15", + "PCIE_TRNTDLLPDATA31", + "PCIE_LH8_12", + "PCIE_CFGMGMTDI5", + "PCIE_IMUX0_L_1", + "PCIE_FAN2_L_15", + "PCIE_PIPETX3DATA8", + "PCIE_EE4C3_3", + "PCIE_NE2A0_9", + "PCIE_IMUX17_L_11", + "PCIE_IMUX10_R_5", + "PCIE_WW4A1_8", + "PCIE_FAN0_L_1", + "PCIE_WW2A3_19", + "PCIE_IMUX45_L_13", + "PCIE_PIPERX3CHARISK0", + "PCIE_IMUX26_L_7", + "PCIE_BLOCK_OUTS_B0_L_19", + "PCIE_FAN0_L_16", + "PCIE_LH3_19", + "PCIE_LOGIC_OUTS_B7_L_19", + "PCIE_PIPETX4DATA3", + "PCIE_BYP0_L_7", + "PCIE_PIPERX5POLARITY", + "PCIE_LH9_9", + "PCIE_NE4C0_12", + "PCIE_XILUNCONNOUT23", + "PCIE_IMUX31_R_6", + "PCIE_IMUX41_R_19", + "PCIE_LOGIC_OUTS_B8_R_19", + "PCIE_LOGIC_OUTS_B5_R_9", + "PCIE_SE2A0_7", + "PCIE_IMUX13_L_14", + "PCIE_LOGIC_OUTS_B4_R_19", + "PCIE_IMUX5_R_2", + "PCIE_WW4A1_5", + "PCIE_IMUX26_L_6", + "PCIE_IMUX21_L_2", + "PCIE_BYP1_L_2", + "PCIE_IMUX40_L_3", + "PCIE_NW4A1_2", + "PCIE_IMUX16_R_14", + "PCIE_IMUX40_R_17", + "PCIE_PIPERX2ELECIDLE", + "PCIE_IMUX3_R_2", + "PCIE_IMUX41_R_10", + "PCIE_PIPERX5STATUS1", + "PCIE_IMUX37_R_18", + "PCIE_PIPERX0DATA11", + "PCIE_WW4END2_0", + "PCIE_IMUX0_R_19", + "PCIE_BYP5_L_3", + "PCIE_LOGIC_OUTS_B6_L_4", + "PCIE_LOGIC_OUTS_B21_L_18", + "PCIE_PIPERX3CHANISALIGNED", + "PCIE_FAN3_R_9", + "PCIE_LOGIC_OUTS_B1_L_17", + "PCIE_LOGIC_OUTS_B5_R_3", + "PCIE_PIPETX6DATA1", + "PCIE_LOGIC_OUTS_B0_L_3", + "PCIE_IMUX28_L_1", + "PCIE_EL1BEG1_10", + "PCIE_MIMRXRDATA18", + "PCIE_BLOCK_OUTS_B0_R_5", + "PCIE_EE4C2_19", + "PCIE_LL2SENDENTERL1", + "PCIE_LOGIC_OUTS_B0_L_5", + "PCIE_ER1BEG1_13", + "PCIE_NW4A2_1", + "PCIE_WW4A3_2", + "PCIE_IMUX44_L_16", + "PCIE_IMUX0_R_11", + "PCIE_IMUX3_L_17", + "PCIE_IMUX40_R_18", + "PCIE_PIPETX5DATA14", + "PCIE_LH3_8", + "PCIE_IMUX45_R_17", + "PCIE_LOGIC_OUTS_B8_L_16", + "PCIE_PIPERX2DATA5", + "PCIE_MIMTXWDATA49", + "PCIE_IMUX34_L_4", + "PCIE_SW4END1_7", + "PCIE_LOGIC_OUTS_B8_R_8", + "PCIE_CFGDSN60", + "PCIE_NW2A2_7", + "PCIE_PIPETX4DATA6", + "PCIE_NW4A0_13", + "PCIE_EE2BEG0_19", + "PCIE_IMUX44_L_14", + "PCIE_LH8_7", + "PCIE_PIPETX7DATA10", + "PCIE_PIPETX0CHARISK0", + "PCIE_DBGVECB21", + "PCIE_LOGIC_OUTS_B22_L_7", + "PCIE_CFGFORCEMPS0", + "PCIE_TRNTCFGREQ", + "PCIE_TL2ERRRXOVERFLOW", + "PCIE_CFGMSGDATA12", + "PCIE_PIPETXDEEMPH", + "PCIE_IMUX31_L_0", + "PCIE_TRNRDLLPDATA7", + "PCIE_NE2A3_19", + "PCIE_FAN2_R_4", + "PCIE_IMUX32_L_3", + "PCIE_IMUX19_R_14", + "PCIE_CFGMSGDATA6", + "PCIE_LOGIC_OUTS_B10_L_1", + "PCIE_TRNRD99", + "PCIE_WR1END3_3", + "PCIE_IMUX21_L_11", + "PCIE_PIPERX4VALID", + "PCIE_MIMTXRDATA66", + "PCIE_TRNTDLLPDATA11", + "PCIE_CFGSUBSYSVENDID14", + "PCIE_IMUX37_L_10", + "PCIE_FAN1_R_11", + "PCIE_NW2A1_5", + "PCIE_FAN1_L_17", + "PCIE_NW4A1_16", + "PCIE_IMUX29_R_0", + "PCIE_SW4A2_1", + "PCIE_SW2A0_11", + "PCIE_IMUX31_L_18", + "PCIE_BYP5_R_9", + "PCIE_CFGPMTURNOFFOKN", + "PCIE_WW2A2_16", + "PCIE_MIMTXRDATA34", + "PCIE_CFGERRAERHEADERLOG35", + "PCIE_CTRL1_L_2", + "PCIE_IMUX25_L_17", + "PCIE_SE4BEG1_6", + "PCIE_WW4C3_11", + "PCIE_IMUX17_L_8", + "PCIE_CFGMGMTDI1", + "PCIE_BYP6_L_2", + "PCIE_CTRL0_R_0", + "PCIE_FAN3_R_2", + "PCIE_CLK1_L_12", + "PCIE_TRNRDLLPDATA45", + "PCIE_IMUX9_R_3", + "PCIE_WW4B2_6", + "PCIE_CFGERRTLPCPLHEADER23", + "PCIE_LH7_4", + "PCIE_FAN6_R_1", + "PCIE_CFGREVID3", + "PCIE_IMUX8_L_5", + "PCIE_ER1BEG3_13", + "PCIE_MIMTXWDATA4", + "PCIE_NW4A2_2", + "PCIE_CFGDSFUNCTIONNUMBER1", + "PCIE_NW4END0_14", + "PCIE_NE4C0_14", + "PCIE_CFGERRTLPCPLHEADER33", + "PCIE_IMUX20_R_10", + "PCIE_EE4A3_3", + "PCIE_WW2END1_6", + "PCIE_SE4BEG0_6", + "PCIE_EE2BEG0_9", + "PCIE_IMUX21_R_8", + "PCIE_ER1BEG1_3", + "PCIE_IMUX26_R_4", + "PCIE_TRNTD24", + "PCIE_MIMRXWDATA26", + "PCIE_BLOCK_OUTS_B2_R_19", + "PCIE_LOGIC_OUTS_B13_R_18", + "PCIE_SW2A2_0", + "PCIE_IMUX36_L_7", + "PCIE_LH6_2", + "PCIE_SW4A3_5", + "PCIE_IMUX47_L_6", + "PCIE_IMUX36_L_17", + "PCIE_NE2A2_5", + "PCIE_TRNTD30", + "PCIE_MIMTXWADDR6", + "PCIE_IMUX15_L_15", + "PCIE_PIPETX2CHARISK1", + "PCIE_TRNRD75", + "PCIE_TRNTD40", + "PCIE_DBGVECA19", + "PCIE_IMUX32_L_10", + "PCIE_BYP6_R_0", + "PCIE_FAN1_R_12", + "PCIE_SE2A2_15", + "PCIE_TRNRDLLPDATA22", + "PCIE_IMUX38_L_4", + "PCIE_LOGIC_OUTS_B5_L_8", + "PCIE_SE4BEG2_15", + "PCIE_NE4C1_2", + "PCIE_TL2ERRHDR24", + "PCIE_IMUX26_L_15", + "PCIE_PIPETX0ELECIDLE", + "PCIE_TRNRD2", + "PCIE_WW4A3_11", + "PCIE_FAN6_R_15", + "PCIE_IMUX17_R_9", + "PCIE_BYP2_R_15", + "PCIE_EE2A2_15", + "PCIE_CFGERRAERHEADERLOG111", + "PCIE_MIMTXRDATA30", + "PCIE_IMUX24_L_17", + "PCIE_PIPERX5DATA4", + "PCIE_TRNRD56", + "PCIE_TL2ERRHDR57", + "PCIE_ER1BEG0_2", + "PCIE_FAN2_L_0", + "PCIE_WW4END1_8", + "PCIE_EL1BEG1_19", + "PCIE_WW4END0_11", + "PCIE_SE4C0_1", + "PCIE_CTRL1_L_14", + "PCIE_BLOCK_OUTS_B2_R_1", + "PCIE_IMUX14_R_13", + "PCIE_IMUX26_R_7", + "PCIE_LOGIC_OUTS_B9_R_16", + "PCIE_EE4BEG3_12", + "PCIE_PIPERX2DATA10", + "PCIE_WW4END1_13", + "PCIE_LOGIC_OUTS_B16_L_9", + "PCIE_WW4A3_1", + "PCIE_CLK0_L_10", + "PCIE_MIMTXWDATA15", + "PCIE_EL1BEG1_2", + "PCIE_WL1END1_1", + "PCIE_IMUX19_L_11", + "PCIE_FAN3_R_11", + "PCIE_IMUX27_R_2", + "PCIE_WR1END2_5", + "PCIE_IMUX44_R_1", + "PCIE_IMUX21_L_3", + "PCIE_EE4A0_1", + "PCIE_PIPERX3DATA6", + "PCIE_CFGERRTLPCPLHEADER34", + "PCIE_IMUX15_R_19", + "PCIE_FAN0_R_9", + "PCIE_IMUX41_L_1", + "PCIE_IMUX27_L_5", + "PCIE_CFGMGMTDI27", + "PCIE_NE4BEG2_3", + "PCIE_IMUX13_L_17", + "PCIE_PIPETX3COMPLIANCE", + "PCIE_TRNRD42", + "PCIE_LH9_19", + "PCIE_WW2A0_6", + "PCIE_BYP2_R_14", + "PCIE_CFGCOMMANDINTERRUPTDISABLE", + "PCIE_IMUX9_R_5", + "PCIE_IMUX8_L_13", + "PCIE_TRNTD20", + "PCIE_EE2A2_8", + "PCIE_MIMRXWDATA44", + "PCIE_PIPERX4DATA5", + "PCIE_NW4A1_12", + "PCIE_SW4END2_12", + "PCIE_DBGVECC8", + "PCIE_SW4END3_1", + "PCIE_WR1END3_5", + "PCIE_CLK0_L_1", + "PCIE_LOGIC_OUTS_B18_L_8", + "PCIE_IMUX9_L_3", + "PCIE_TRNRD122", + "PCIE_CFGMGMTDI0", + "PCIE_FAN5_L_15", + "PCIE_BYP2_L_8", + "PCIE_TRNTD43", + "PCIE_SE4BEG2_8", + "PCIE_PIPETX4CHARISK0", + "PCIE_IMUX17_L_17", + "PCIE_IMUX27_R_10", + "PCIE_IMUX32_R_14", + "PCIE_PMVSELECT0", + "PCIE_IMUX32_R_3", + "PCIE_SE2A1_5", + "PCIE_EE4C3_12", + "PCIE_TRNFCCPLD7", + "PCIE_LOGIC_OUTS_B2_L_4", + "PCIE_IMUX29_L_6", + "PCIE_IMUX42_L_2", + "PCIE_WR1END1_6", + "PCIE_PIPETX1DATA0", + "PCIE_NW2A0_19", + "PCIE_CFGDEVCONTROLPHANTOMEN", + "PCIE_CFGDEVID10", + "PCIE_LOGIC_OUTS_B20_R_7", + "PCIE_NW2A3_8", + "PCIE_LOGIC_OUTS_B9_L_8", + "PCIE_NE4C2_0", + "PCIE_NW2A2_10", + "PCIE_IMUX34_R_6", + "PCIE_TRNTD14", + "PCIE_TRNRD101", + "PCIE_CFGMGMTDWADDR5", + "PCIE_LOGIC_OUTS_B6_R_6", + "PCIE_IMUX0_L_14", + "PCIE_EE4BEG0_10", + "PCIE_TRNTD22", + "PCIE_WW4B2_15", + "PCIE_IMUX32_R_0", + "PCIE_IMUX25_L_14", + "PCIE_IMUX14_R_6", + "PCIE_WW4C3_15", + "PCIE_FAN1_L_19", + "PCIE_IMUX44_R_16", + "PCIE_BYP7_L_7", + "PCIE_LOGIC_OUTS_B6_R_16", + "PCIE_PIPERX6DATA14", + "PCIE_SE4BEG3_4", + "PCIE_TRNFCCPLD9", + "PCIE_IMUX31_R_1", + "PCIE_LOGIC_OUTS_B5_R_19", + "PCIE_IMUX3_R_17", + "PCIE_MIMTXWDATA39", + "PCIE_EE2A0_11", + "PCIE_NW4A2_11", + "PCIE_SE4C0_18", + "PCIE_WW4A3_7", + "PCIE_EE4A0_11", + "PCIE_LH12_13", + "PCIE_WW4B1_17", + "PCIE_LOGIC_OUTS_B2_R_2", + "PCIE_PIPERX6CHARISK1", + "PCIE_IMUX24_R_1", + "PCIE_BYP4_L_17", + "PCIE_NE4BEG3_11", + "PCIE_WW4A1_6", + "PCIE_FAN0_L_14", + "PCIE_SW4A2_13", + "PCIE_TL2ERRHDR16", + "PCIE_CFGDSN30", + "PCIE_EE4B0_12", + "PCIE_SE2A1_10", + "PCIE_SE4BEG0_3", + "PCIE_SE4C1_5", + "PCIE_IMUX2_L_11", + "PCIE_IMUX37_R_17", + "PCIE_IMUX4_L_18", + "PCIE_PIPETX0DATA3", + "PCIE_MIMRXRADDR6", + "PCIE_WW4B2_0", + "PCIE_EE4B2_3", + "PCIE_WW4B3_8", + "PCIE_MIMRXRDATA10", + "PCIE_NW4END1_7", + "PCIE_TRNRD111", + "PCIE_WR1END0_9", + "PCIE_LOGIC_OUTS_B20_L_5", + "PCIE_LH3_4", + "PCIE_IMUX21_R_16", + "PCIE_EE2BEG1_19", + "PCIE_IMUX30_R_10", + "PCIE_TRNTD50", + "PCIE_IMUX0_R_6", + "PCIE_LOGIC_OUTS_B19_R_6", + "PCIE_NE2A1_11", + "PCIE_LOGIC_OUTS_B13_R_19", + "PCIE_NW2A1_3", + "PCIE_PIPERX7DATA14", + "PCIE_SE2A0_16", + "PCIE_CFGERRAERHEADERLOG85", + "PCIE_IMUX9_R_19", + "PCIE_SW4A0_11", + "PCIE_CFGDEVCONTROLMAXPAYLOAD1", + "PCIE_CFGLINKCONTROLASPMCONTROL0", + "PCIE_BYP6_R_18", + "PCIE_NE2A1_8", + "PCIE_CFGDSN39", + "PCIE_IMUX22_R_17", + "PCIE_CFGPORTNUMBER6", + "PCIE_EE4C3_6", + "PCIE_PIPETX1DATA14", + "PCIE_IMUX2_L_15", + "PCIE_IMUX20_R_7", + "PCIE_EE4C3_7", + "PCIE_TL2ASPMSUSPENDCREDITCHECK", + "PCIE_IMUX9_R_8", + "PCIE_BYP4_R_13", + "PCIE_CFGMGMTDO27", + "PCIE_IMUX24_R_15", + "PCIE_IMUX29_L_12", + "PCIE_LOGIC_OUTS_B12_L_2", + "PCIE_NE4C3_16", + "PCIE_IMUX1_L_14", + "PCIE_LH10_6", + "PCIE_ER1BEG3_7", + "PCIE_PIPERX3POLARITY", + "PCIE_PIPETX0DATA10", + "PCIE_IMUX43_L_17", + "PCIE_BYP4_R_12", + "PCIE_LOGIC_OUTS_B3_R_11", + "PCIE_TRNTD58", + "PCIE_MIMRXRDATA46", + "PCIE_CFGAERROOTERRCORRERRRECEIVED", + "PCIE_DRPADDR3", + "PCIE_IMUX40_L_17", + "PCIE_XILUNCONNOUT20", + "PCIE_TRNRD10", + "PCIE_CFGVENDID3", + "PCIE_CFGERRAERHEADERLOG2", + "PCIE_WL1END3_13", + "PCIE_CFGERRAERHEADERLOG103", + "PCIE_MIMTXRDATA0", + "PCIE_TRNTD13", + "PCIE_TRNTDLLPDATA19", + "PCIE_EE4C2_2", + "PCIE_NE4BEG1_13", + "PCIE_WW4A1_3", + "PCIE_ER1BEG0_10", + "PCIE_TRNRSRCDSC", + "PCIE_EE4B3_7", + "PCIE_IMUX47_L_2", + "PCIE_LOGIC_OUTS_B20_R_18", + "PCIE_NE2A1_15", + "PCIE_LH2_19", + "PCIE_FAN7_L_7", + "PCIE_LOGIC_OUTS_B23_R_8", + "PCIE_IMUX13_L_16", + "PCIE_IMUX25_R_6", + "PCIE_WR1END1_11", + "PCIE_IMUX1_R_16", + "PCIE_CFGSUBSYSVENDID10", + "PCIE_LH6_15", + "PCIE_IMUX20_R_5", + "PCIE_EE4B0_4", + "PCIE_MIMRXWADDR8", + "PCIE_EE4B0_9", + "PCIE_IMUX43_R_2", + "PCIE_PIPETX0DATA0", + "PCIE_IMUX18_R_3", + "PCIE_WW2A3_7", + "PCIE_IMUX3_L_10", + "PCIE_IMUX33_R_8", + "PCIE_WW4C2_18", + "PCIE_IMUX12_L_19", + "PCIE_LOGIC_OUTS_B3_L_13", + "PCIE_LOGIC_OUTS_B21_R_3", + "PCIE_CFGLINKCONTROLCOMMONCLOCK", + "PCIE_FAN0_R_19", + "PCIE_WR1END0_19", + "PCIE_IMUX33_L_9", + "PCIE_IMUX34_L_18", + "PCIE_LH10_12", + "PCIE_EE2BEG0_15", + "PCIE_IMUX44_L_8", + "PCIE_LOGIC_OUTS_B23_L_2", + "PCIE_NE2A2_18", + "PCIE_IMUX11_R_10", + "PCIE_TRNTD2", + "PCIE_BLOCK_OUTS_B1_R_15", + "PCIE_BYP1_L_16", + "PCIE_TRNRDLLPDATA3", + "PCIE_CFGMGMTDI19", + "PCIE_CLK0_L_18", + "PCIE_CLK0_R_17", + "PCIE_LOGIC_OUTS_B21_L_10", + "PCIE_LOGIC_OUTS_B6_R_12", + "PCIE_IMUX3_L_18", + "PCIE_EE4BEG1_17", + "PCIE_EE4B0_5", + "PCIE_IMUX37_L_14", + "PCIE_NE4C2_9", + "PCIE_NW4END2_8", + "PCIE_PIPETX4COMPLIANCE", + "PCIE_PLLTSSMSTATE3", + "PCIE_LH9_1", + "PCIE_TRNRREM0", + "PCIE_LOGIC_OUTS_B11_R_14", + "PCIE_SW4END2_4", + "PCIE_FAN3_L_3", + "PCIE_BYP1_R_12", + "PCIE_TRNRDLLPDATA24", + "PCIE_SE4C2_16", + "PCIE_CFGERRAERHEADERLOG64", + "PCIE_FAN7_R_17", + "PCIE_WL1END0_7", + "PCIE_TRNTD82", + "PCIE_BLOCK_OUTS_B2_R_18", + "PCIE_LOGIC_OUTS_B5_R_16", + "PCIE_EE2A3_14", + "PCIE_FAN7_R_0", + "PCIE_DBGVECA46", + "PCIE_ER1BEG2_1", + "PCIE_NE2A1_17", + "PCIE_PIPETX3DATA15", + "PCIE_IMUX33_L_12", + "PCIE_CFGDSBUSNUMBER5", + "PCIE_NE2A3_9", + "PCIE_EE2BEG2_8", + "PCIE_NW2A3_19", + "PCIE_IMUX46_L_19", + "PCIE_IMUX38_L_11", + "PCIE_TL2ERRHDR29", + "PCIE_PIPERX1STATUS1", + "PCIE_TRNFCPD11", + "PCIE_EE2A1_5", + "PCIE_DBGVECA54", + "PCIE_MIMTXRADDR10", + "PCIE_IMUX5_L_4", + "PCIE_TRNTD87", + "PCIE_TRNTD64", + "PCIE_PLDBGVEC4", + "PCIE_LOGIC_OUTS_B16_L_3", + "PCIE_WW4B3_3", + "PCIE_NW4A2_8", + "PCIE_IMUX5_L_9", + "PCIE_IMUX5_R_14", + "PCIE_DBGSCLRF", + "PCIE_WW2END0_14", + "PCIE_BLOCK_OUTS_B0_L_5", + "PCIE_IMUX14_R_7", + "PCIE_IMUX22_L_7", + "PCIE_EL1BEG1_16", + "PCIE_MIMRXRDATA13", + "PCIE_IMUX42_R_19", + "PCIE_FAN2_R_12", + "PCIE_NW4END2_1", + "PCIE_IMUX38_R_14", + "PCIE_DBGVECB49", + "PCIE_CFGVENDID7", + "PCIE_MIMTXRDATA22", + "PCIE_CFGDEVID15", + "PCIE_LOGIC_OUTS_B8_L_13", + "PCIE_TL2ERRHDR33", + "PCIE_LH10_5", + "PCIE_IMUX37_R_0", + "PCIE_WL1END1_5", + "PCIE_TRNFCPD7", + "PCIE_EL1BEG2_5", + "PCIE_MIMRXRDATA23", + "PCIE_SW2A3_13", + "PCIE_TRNRDLLPDATA55", + "PCIE_NW4END2_14", + "PCIE_MIMTXRDATA68", + "PCIE_CFGDEVID8", + "PCIE_MIMRXRDATA35", + "PCIE_IMUX16_L_8", + "PCIE_FAN1_L_16", + "PCIE_WR1END3_4", + "PCIE_PIPETX7DATA14", + "PCIE_IMUX36_R_17", + "PCIE_SW2A0_16", + "PCIE_BLOCK_OUTS_B2_R_14", + "PCIE_SE4BEG3_8", + "PCIE_MIMTXRDATA16", + "PCIE_LOGIC_OUTS_B22_R_5", + "PCIE_IMUX41_L_3", + "PCIE_PIPETX2DATA10", + "PCIE_EE4B2_19", + "PCIE_LH7_0", + "PCIE_IMUX39_R_16", + "PCIE_IMUX36_R_13", + "PCIE_IMUX24_R_19", + "PCIE_IMUX31_L_2", + "PCIE_DRPADDR6", + "PCIE_MIMRXWDATA17", + "PCIE_CFGERRAERHEADERLOG37", + "PCIE_IMUX46_R_11", + "PCIE_EE2BEG0_3", + "PCIE_LOGIC_OUTS_B0_R_19", + "PCIE_LH5_5", + "PCIE_IMUX44_L_15", + "PCIE_EE2BEG2_16", + "PCIE_MIMRXRDATA27", + "PCIE_CFGERRAERHEADERLOG69", + "PCIE_DRPDI7", + "PCIE_IMUX8_R_3", + "PCIE_TRNTBUFAV1", + "PCIE_DBGVECA10", + "PCIE_CFGMGMTDWADDR6", + "PCIE_IMUX41_L_5", + "PCIE_TRNFCPH5", + "PCIE_TRNRDLLPDATA62", + "PCIE_BYP2_R_11", + "PCIE_NW4END1_2", + "PCIE_WW4END0_16", + "PCIE_WW4A3_13", + "PCIE_LH7_10", + "PCIE_WW2END1_15", + "PCIE_IMUX42_R_10", + "PCIE_MIMTXRDATA52", + "PCIE_PIPETX4DATA8", + "PCIE_SE2A2_18", + "PCIE_SE4BEG0_17", + "PCIE_SW4END0_3", + "PCIE_BYP7_L_3", + "PCIE_MIMRXRDATA47", + "PCIE_BYP0_L_3", + "PCIE_IMUX42_R_12", + "PCIE_MIMTXWDATA28", + "PCIE_LH1_5", + "PCIE_LOGIC_OUTS_B16_L_14", + "PCIE_XILUNCONNOUT29", + "PCIE_IMUX27_L_13", + "PCIE_NE4BEG3_0", + "PCIE_BLOCK_OUTS_B3_L_12", + "PCIE_TRNRD57", + "PCIE_EE4C2_9", + "PCIE_NW2A3_5", + "PCIE_CFGVENDID4", + "PCIE_IMUX34_L_14", + "PCIE_LH6_12", + "PCIE_IMUX4_L_8", + "PCIE_LOGIC_OUTS_B21_L_0", + "PCIE_IMUX30_L_18", + "PCIE_LOGIC_OUTS_B11_L_16", + "PCIE_FAN0_L_0", + "PCIE_IMUX2_R_14", + "PCIE_IMUX33_L_19", + "PCIE_SW2A1_9", + "PCIE_TRNRDLLPDATA40", + "PCIE_TRNRDLLPDATA27", + "PCIE_IMUX4_R_12", + "PCIE_SE4BEG0_12", + "PCIE_BYP7_R_10", + "PCIE_IMUX20_R_2", + "PCIE_LOGIC_OUTS_B6_R_4", + "PCIE_EE2A3_12", + "PCIE_LOGIC_OUTS_B5_R_2", + "PCIE_WW4A2_4", + "PCIE_LOGIC_OUTS_B10_L_3", + "PCIE_LH1_16", + "PCIE_WW4B0_0", + "PCIE_IMUX21_L_16", + "PCIE_IMUX5_L_18", + "PCIE_WW4B1_16", + "PCIE_IMUX37_L_12", + "PCIE_IMUX36_L_16", + "PCIE_MIMTXWDATA63", + "PCIE_PIPETX6DATA5", + "PCIE_TL2ERRHDR58", + "PCIE_PIPERX4DATA0", + "PCIE_TL2ERRHDR30", + "PCIE_TRNFCCPLH3", + "PCIE_TRNRD8", + "PCIE_NE4C2_5", + "PCIE_CFGDEVID13", + "PCIE_SE2A0_18", + "PCIE_MONITOR_N_6", + "PCIE_EL1BEG0_6", + "PCIE_IMUX37_R_1", + "PCIE_TRNRD49", + "PCIE_IMUX38_R_17", + "PCIE_LOGIC_OUTS_B2_R_5", + "PCIE_IMUX39_R_11", + "PCIE_CLK1_R_0", + "PCIE_DBGVECA2", + "PCIE_SW4A2_8", + "PCIE_IMUX17_R_2", + "PCIE_PIPERX2DATA11", + "PCIE_IMUX13_L_6", + "PCIE_LOGIC_OUTS_B2_L_14", + "PCIE_FAN6_L_9", + "PCIE_FAN1_L_14", + "PCIE_TRNRD23", + "PCIE_XILUNCONNOUT12", + "PCIE_PIPERX2DATA13", + "PCIE_NE2A1_0", + "PCIE_IMUX7_L_0", + "PCIE_BLOCK_OUTS_B0_L_16", + "PCIE_MIMTXWADDR7", + "PCIE_LH10_16", + "PCIE_SE4BEG1_10", + "PCIE_ER1BEG3_10", + "PCIE_BLOCK_OUTS_B0_L_6", + "PCIE_BLOCK_OUTS_B0_L_7", + "PCIE_SE4C2_2", + "PCIE_MIMTXRDATA36", + "PCIE_IMUX22_R_19", + "PCIE_IMUX0_L_17", + "PCIE_LH3_18", + "PCIE_IMUX39_R_0", + "PCIE_TRNFCNPD9", + "PCIE_TRNRD124", + "PCIE_TRNRD97", + "PCIE_MONITOR_N_13", + "PCIE_CTRL0_R_1", + "PCIE_LOGIC_OUTS_B8_R_3", + "PCIE_MONITOR_P_1", + "PCIE_NE2A0_10", + "PCIE_SE4C0_9", + "PCIE_TL2ERRHDR37", + "PCIE_EL1BEG0_9", + "PCIE_WW2END2_10", + "PCIE_SW4A3_7", + "PCIE_LOGIC_OUTS_B2_R_7", + "PCIE_BYP4_R_3", + "PCIE_WW4END3_16", + "PCIE_EE2A3_6", + "PCIE_WW4C0_15", + "PCIE_NE2A3_1", + "PCIE_IMUX26_R_15", + "PCIE_IMUX46_L_18", + "PCIE_PIPERX7DATA3", + "PCIE_NE4BEG0_11", + "PCIE_IMUX44_L_4", + "PCIE_CFGVENDID6", + "PCIE_IMUX30_R_1", + "PCIE_EE4BEG1_11", + "PCIE_EE4B3_11", + "PCIE_EE4A1_0", + "PCIE_MIMTXWDATA55", + "PCIE_CFGREVID6", + "PCIE_FAN4_R_5", + "PCIE_WW4END0_7", + "PCIE_PIPETX6DATA13", + "PCIE_PIPERX7CHARISK0", + "PCIE_NW4END3_10", + "PCIE_CFGERRAERHEADERLOG30", + "PCIE_MIMTXWDATA59", + "PCIE_SW4A0_4", + "PCIE_WL1END3_1", + "PCIE_LOGIC_OUTS_B12_R_19", + "PCIE_CFGMGMTDI20", + "PCIE_MIMTXWADDR12", + "PCIE_IMUX17_R_10", + "PCIE_SCANENABLEN", + "PCIE_IMUX43_L_6", + "PCIE_MIMTXWDATA24", + "PCIE_LOGIC_OUTS_B20_R_1", + "PCIE_WW4END2_10", + "PCIE_CFGERRTLPCPLHEADER44", + "PCIE_WW4B1_5", + "PCIE_SE4C2_14", + "PCIE_LH11_19", + "PCIE_IMUX24_R_13", + "PCIE_CFGERRTLPCPLHEADER7", + "PCIE_IMUX31_R_0", + "PCIE_IMUX18_L_9", + "PCIE_WW4END2_12", + "PCIE_FAN7_L_17", + "PCIE_IMUX8_R_9", + "PCIE_EE2A3_5", + "PCIE_PIPETX2DATA11", + "PCIE_FAN2_L_18", + "PCIE_MIMTXWDATA27", + "PCIE_LOGIC_OUTS_B3_R_9", + "PCIE_BYP7_R_14", + "PCIE_TL2ERRHDR35", + "PCIE_MIMTXRDATA47", + "PCIE_PLDBGVEC2", + "PCIE_IMUX10_R_8", + "PCIE_LH3_5", + "PCIE_LOGIC_OUTS_B14_R_3", + "PCIE_WW4B3_17", + "PCIE_EE4BEG0_1", + "PCIE_IMUX5_R_16", + "PCIE_IMUX25_R_7", + "PCIE_IMUX14_L_1", + "PCIE_IMUX22_L_11", + "PCIE_WW4B0_19", + "PCIE_IMUX25_L_11", + "PCIE_TRNRD114", + "PCIE_LOGIC_OUTS_B21_R_1", + "PCIE_FAN6_L_17", + "PCIE_LOGIC_OUTS_B21_R_13", + "PCIE_PIPERX3DATA10", + "PCIE_LL2LINKSTATUS4", + "PCIE_IMUX31_L_1", + "PCIE_EE4BEG2_14", + "PCIE_NW2A0_12", + "PCIE_BYP1_R_17", + "PCIE_IMUX39_L_16", + "PCIE_MIMRXWADDR10", + "PCIE_TRNTD105", + "PCIE_IMUX3_L_8", + "PCIE_LOGIC_OUTS_B16_R_14", + "PCIE_IMUX17_R_7", + "PCIE_SW4A0_3", + "PCIE_NW2A2_9", + "PCIE_IMUX47_R_17", + "PCIE_CFGDSN35", + "PCIE_CFGSUBSYSVENDID11", + "PCIE_IMUX15_R_13", + "PCIE_TRNTD3", + "PCIE_TRNRD63", + "PCIE_IMUX0_R_1", + "PCIE_LH11_12", + "PCIE_BYP5_R_11", + "PCIE_DBGVECA0", + "PCIE_CFGMGMTDI7", + "PCIE_EE4C2_0", + "PCIE_NW4A1_5", + "PCIE_IMUX37_R_9", + "PCIE_SW2A2_18", + "PCIE_LH11_2", + "PCIE_IMUX3_R_10", + "PCIE_WL1END2_18", + "PCIE_NW2A0_13", + "PCIE_EDTCONFIGURATION", + "PCIE_DBGVECA14", + "PCIE_IMUX6_L_5", + "PCIE_LH9_15", + "PCIE_LOGIC_OUTS_B11_L_11", + "PCIE_IMUX19_L_8", + "PCIE_WW2END0_5", + "PCIE_DRPDO2", + "PCIE_FAN3_R_10", + "PCIE_WL1END2_6", + "PCIE_IMUX38_L_19", + "PCIE_IMUX6_R_2", + "PCIE_LOGIC_OUTS_B12_R_5", + "PCIE_MIMTXWDATA29", + "PCIE_BYP6_R_5", + "PCIE_NW2A2_12", + "PCIE_IMUX33_R_16", + "PCIE_CFGERRAERHEADERLOG0", + "PCIE_WW4A0_4", + "PCIE_BYP5_L_15", + "PCIE_BLOCK_OUTS_B1_R_19", + "PCIE_NE2A0_19", + "PCIE_TRNFCNPD6", + "PCIE_IMUX31_L_7", + "PCIE_IMUX17_L_19", + "PCIE_MIMTXRDATA55", + "PCIE_CFGERRTLPCPLHEADER46", + "PCIE_IMUX39_R_12", + "PCIE_PIPETX6DATA8", + "PCIE_IMUX11_L_1", + "PCIE_IMUX42_L_19", + "PCIE_BLOCK_OUTS_B3_R_8", + "PCIE_IMUX32_R_17", + "PCIE_LOGIC_OUTS_B18_L_10", + "PCIE_IMUX34_R_14", + "PCIE_SE2A1_1", + "PCIE_WR1END2_19", + "PCIE_TRNRDLLPDATA63", + "PCIE_BLOCK_OUTS_B0_L_0", + "PCIE_WR1END0_4", + "PCIE_IMUX26_L_18", + "PCIE_LOGIC_OUTS_B12_L_7", + "PCIE_DBGVECC6", + "PCIE_BYP1_L_18", + "PCIE_LOGIC_OUTS_B8_R_11", + "PCIE_WW4END2_5", + "PCIE_IMUX21_R_13", + "PCIE_EE4A1_17", + "PCIE_TRNFCNPD2", + "PCIE_PIPERX5DATA13", + "PCIE_WW4END2_6", + "PCIE_IMUX17_L_12", + "PCIE_SE4BEG2_17", + "PCIE_EDTCHANNELSIN5", + "PCIE_LOGIC_OUTS_B2_L_18", + "PCIE_BYP4_L_1", + "PCIE_CFGERRAERHEADERLOG73", + "PCIE_MIMRXWDATA53", + "PCIE_IMUX18_R_19", + "PCIE_IMUX10_L_15", + "PCIE_TRNRD118", + "PCIE_LOGIC_OUTS_B22_L_0", + "PCIE_LOGIC_OUTS_B13_L_9", + "PCIE_BLOCK_OUTS_B2_L_8", + "PCIE_PIPERX4DATA14", + "PCIE_WL1END0_15", + "PCIE_NE4C1_11", + "PCIE_WW4END1_11", + "PCIE_BYP3_L_19", + "PCIE_FAN3_R_13", + "PCIE_DBGSCLRE", + "PCIE_BLOCK_OUTS_B0_R_3", + "PCIE_NW2A1_14", + "PCIE_PIPETX6POWERDOWN0", + "PCIE_TRNRNPREQ", + "PCIE_TRNTD117", + "PCIE_CFGERRCPLABORTN", + "PCIE_PIPERX2DATA14", + "PCIE_DBGVECB46", + "PCIE_IMUX22_R_14", + "PCIE_IMUX41_R_2", + "PCIE_IMUX7_L_13", + "PCIE_IMUX1_L_19", + "PCIE_SW4A3_0", + "PCIE_TRNTSOF", + "PCIE_IMUX21_L_4", + "PCIE_LH10_0", + "PCIE_LOGIC_OUTS_B22_R_16", + "PCIE_EL1BEG1_17", + "PCIE_CFGFORCEMPS2", + "PCIE_IMUX6_R_4", + "PCIE_IMUX45_R_14", + "PCIE_WR1END0_11", + "PCIE_CFGDSN63", + "PCIE_LOGIC_OUTS_B7_L_13", + "PCIE_CFGDEVCONTROLEXTTAGEN", + "PCIE_EE4B1_1", + "PCIE_PIPERX3PHYSTATUS", + "PCIE_PIPETX7ELECIDLE", + "PCIE_WL1END1_2", + "PCIE_MIMRXRADDR2", + "PCIE_EE4A1_18", + "PCIE_CFGDSBUSNUMBER7", + "PCIE_IMUX34_R_19", + "PCIE_NW4END3_4", + "PCIE_IMUX43_R_10", + "PCIE_IMUX32_R_15", + "PCIE_IMUX25_R_12", + "PCIE_BYP0_R_0", + "PCIE_LOGIC_OUTS_B11_L_19", + "PCIE_EL1BEG3_17", + "PCIE_EE2A1_18", + "PCIE_DBGVECB19", + "PCIE_IMUX21_R_9", + "PCIE_TRNRD60", + "PCIE_IMUX42_R_4", + "PCIE_IMUX39_R_10", + "PCIE_LOGIC_OUTS_B1_L_13", + "PCIE_CFGDSN12", + "PCIE_WW4C0_14", + "PCIE_WW4C2_14", + "PCIE_FAN3_L_12", + "PCIE_CFGVCTCVCMAP5", + "PCIE_IMUX14_R_3", + "PCIE_BYP5_L_11", + "PCIE_LOGIC_OUTS_B7_L_1", + "PCIE_WW4C3_14", + "PCIE_LOGIC_OUTS_B13_R_9", + "PCIE_PIPETX6DATA15", + "PCIE_LOGIC_OUTS_B6_R_0", + "PCIE_LOGIC_OUTS_B2_L_5", + "PCIE_NE4BEG0_0", + "PCIE_LH9_10", + "PCIE_IMUX25_R_15", + "PCIE_IMUX27_L_7", + "PCIE_IMUX40_L_13", + "PCIE_DBGVECA41", + "PCIE_EE4B3_13", + "PCIE_IMUX28_L_13", + "PCIE_FAN5_R_0", + "PCIE_PIPERX3DATA14", + "PCIE_NW2A1_18", + "PCIE_SW4A2_17", + "PCIE_IMUX31_R_11", + "PCIE_WW4A2_8", + "PCIE_LOGIC_OUTS_B12_L_14", + "PCIE_IMUX38_L_17", + "PCIE_PIPERX6DATA7", + "PCIE_NW2A1_10", + "PCIE_IMUX42_L_7", + "PCIE_IMUX1_R_15", + "PCIE_CFGMGMTDO6", + "PCIE_SW2A2_14", + "PCIE_BYP2_L_16", + "PCIE_WW2A0_12", + "PCIE_MIMRXWDATA34", + "PCIE_NE2A3_4", + "PCIE_EE4A1_5", + "PCIE_MIMRXRDATA0", + "PCIE_EE2A2_13", + "PCIE_MIMTXRDATA51", + "PCIE_CFGERRAERHEADERLOG110", + "PCIE_CFGAERINTERRUPTMSGNUM3", + "PCIE_EL1BEG3_16", + "PCIE_NE4C0_11", + "PCIE_LOGIC_OUTS_B21_L_15", + "PCIE_IMUX18_R_4", + "PCIE_SW2A1_2", + "PCIE_SE4BEG1_14", + "PCIE_WW4A0_0", + "PCIE_WW2A2_6", + "PCIE_BYP6_L_3", + "PCIE_LOGIC_OUTS_B23_R_15", + "PCIE_LOGIC_OUTS_B16_R_9", + "PCIE_IMUX25_R_1", + "PCIE_CFGERRURN", + "PCIE_NW4A2_5", + "PCIE_LOGIC_OUTS_B14_L_11", + "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", + "PCIE_IMUX35_R_0", + "PCIE_LOGIC_OUTS_B15_L_6", + "PCIE_WW4C3_5", + "PCIE_PIPERX1DATA6", + "PCIE_FAN0_L_10", + "PCIE_IMUX31_R_10", + "PCIE_PIPERX7CHANISALIGNED", + "PCIE_IMUX32_L_14", + "PCIE_PIPETX6DATA6", + "PCIE_IMUX14_L_15", + "PCIE_LOGIC_OUTS_B12_R_10", + "PCIE_EE4BEG2_2", + "PCIE_LOGIC_OUTS_B22_L_9", + "PCIE_PLLTSSMSTATE2", + "PCIE_IMUX1_L_12", + "PCIE_LH7_6", + "PCIE_IMUX14_L_9", + "PCIE_FAN1_R_16", + "PCIE_CTRL0_R_8", + "PCIE_IMUX30_L_1", + "PCIE_PIPERX7DATA10", + "PCIE_IMUX21_R_18", + "PCIE_CTRL0_R_19", + "PCIE_SE4C1_4", + "PCIE_CLK0_L_6", + "PCIE_MIMRXRDATA8", + "PCIE_IMUX2_R_10", + "PCIE_NE4BEG3_10", + "PCIE_SW2A1_12", + "PCIE_IMUX8_L_17", + "PCIE_WL1END2_12", + "PCIE_IMUX15_R_17", + "PCIE_LOGIC_OUTS_B14_R_9", + "PCIE_LOGIC_OUTS_B10_R_12", + "PCIE_IMUX47_L_13", + "PCIE_MONITOR_N_2", + "PCIE_SE4BEG0_18", + "PCIE_LOGIC_OUTS_B21_L_19", + "PCIE_PIPERX1CHARISK0", + "PCIE_EE2BEG2_19", + "PCIE_LOGIC_OUTS_B19_R_9", + "PCIE_WW4B1_0", + "PCIE_PIPETX3DATA9", + "PCIE_IMUX44_L_7", + "PCIE_CFGERRAERHEADERLOG112", + "PCIE_IMUX42_R_1", + "PCIE_PLDBGVEC5", + "PCIE_LOGIC_OUTS_B2_R_16", + "PCIE_BYP2_R_2", + "PCIE_LOGIC_OUTS_B17_L_11", + "PCIE_LOGIC_OUTS_B19_L_15", + "PCIE_SE2A0_14", + "PCIE_TRNTDLLPDATA14", + "PCIE_PIPERX2DATA3", + "PCIE_WW4A2_9", + "PCIE_IMUX34_R_13", + "PCIE_LOGIC_OUTS_B19_R_8", + "PCIE_NW4A3_12", + "PCIE_PIPETX1POWERDOWN1", + "PCIE_BYP7_L_11", + "PCIE_EE2A0_5", + "PCIE_CFGERRAERHEADERLOG77", + "PCIE_IMUX16_R_7", + "PCIE_BLOCK_OUTS_B2_L_11", + "PCIE_IMUX17_L_10", + "PCIE_BYP5_L_16", + "PCIE_IMUX39_R_18", + "PCIE_EE4A2_16", + "PCIE_IMUX22_L_15", + "PCIE_IMUX23_L_11", + "PCIE_LH5_15", + "PCIE_IMUX34_R_11", + "PCIE_NW2A1_7", + "PCIE_TRNTD44", + "PCIE_WW4B3_9", + "PCIE_CFGPORTNUMBER2", + "PCIE_LOGIC_OUTS_B17_L_10", + "PCIE_WW4END1_2", + "PCIE_DBGVECB42", + "PCIE_TL2ERRHDR6", + "PCIE_FAN5_L_7", + "PCIE_IMUX2_R_4", + "PCIE_CFGDSN20", + "PCIE_IMUX47_R_6", + "PCIE_LH3_13", + "PCIE_LOGIC_OUTS_B16_L_8", + "PCIE_NE2A3_8", + "PCIE_CFGVENDID1", + "PCIE_BYP4_L_13", + "PCIE_LOGIC_OUTS_B22_L_12", + "PCIE_CFGREVID5", + "PCIE_FAN5_R_2", + "PCIE_IMUX46_R_16", + "PCIE_LH6_14", + "PCIE_BLOCK_OUTS_B3_L_14", + "PCIE_BYP2_L_11", + "PCIE_IMUX0_R_17", + "PCIE_PLLINKUPCFGCAP", + "PCIE_CFGERRAERHEADERLOG46", + "PCIE_NE2A2_16", + "PCIE_LH11_3", + "PCIE_LH10_3", + "PCIE_SW4A0_0", + "PCIE_CFGERRAERHEADERLOG86", + "PCIE_IMUX1_L_13", + "PCIE_IMUX1_L_7", + "PCIE_TRNTD111", + "PCIE_SW4END0_12", + "PCIE_IMUX28_R_19", + "PCIE_LOGIC_OUTS_B9_R_19", + "PCIE_EE4BEG3_11", + "PCIE_LOGIC_OUTS_B9_L_0", + "PCIE_LOGIC_OUTS_B15_R_14", + "PCIE_PLSELLNKWIDTH1", + "PCIE_WW4B1_9", + "PCIE_CFGMGMTDI16", + "PCIE_FAN2_L_10", + "PCIE_IMUX5_L_1", + "PCIE_WW2END1_14", + "PCIE_TRNRD33", + "PCIE_IMUX0_L_4", + "PCIE_LH1_7", + "PCIE_BLOCK_OUTS_B3_R_14", + "PCIE_IMUX41_R_8", + "PCIE_LH6_1", + "PCIE_EE4C2_8", + "PCIE_PIPETX6DATA11", + "PCIE_IMUX6_L_8", + "PCIE_FAN1_L_2", + "PCIE_EE2BEG1_9", + "PCIE_IMUX30_L_4", + "PCIE_SW4A2_10", + "PCIE_TRNFCCPLH1", + "PCIE_IMUX1_R_6", + "PCIE_WW2A0_8", + "PCIE_TRNRD65", + "PCIE_WW4END0_18", + "PCIE_IMUX23_R_9", + "PCIE_TRNFCPD2", + "PCIE_IMUX23_R_7", + "PCIE_PLINITIALLINKWIDTH0", + "PCIE_DBGVECA18", + "PCIE_BYP7_R_13", + "PCIE_EE4C1_15", + "PCIE_MIMRXWDATA49", + "PCIE_IMUX0_L_3", + "PCIE_CTRL0_R_4", + "PCIE_IMUX9_L_5", + "PCIE_SW4A3_1", + "PCIE_NE4C3_0", + "PCIE_WR1END1_7", + "PCIE_TRNTD52", + "PCIE_IMUX6_R_11", + "PCIE_IMUX10_R_12", + "PCIE_BLOCK_OUTS_B1_L_4", + "PCIE_SW4END3_10", + "PCIE_LOGIC_OUTS_B15_L_0", + "PCIE_IMUX40_L_19", + "PCIE_CFGSUBSYSVENDID0", + "PCIE_IMUX45_L_11", + "PCIE_TRNTD28", + "PCIE_FAN5_R_6", + "PCIE_BLOCK_OUTS_B1_R_4", + "PCIE_CTRL0_R_12", + "PCIE_EE4A2_8", + "PCIE_LOGIC_OUTS_B21_R_15", + "PCIE_IMUX16_R_5", + "PCIE_TRNRD113", + "PCIE_IMUX10_R_3", + "PCIE_IMUX17_R_19", + "PCIE_LOGIC_OUTS_B10_L_16", + "PCIE_SW4END0_4", + "PCIE_SE2A1_15", + "PCIE_LOGIC_OUTS_B20_L_17", + "PCIE_PMVDIVIDE0", + "PCIE_TRNFCNPD11", + "PCIE_LOGIC_OUTS_B11_L_13", + "PCIE_IMUX26_L_13", + "PCIE_TRNRSRCRDY", + "PCIE_IMUX16_L_14", + "PCIE_CFGMGMTDO7", + "PCIE_PMVDIVIDE1", + "PCIE_IMUX20_R_13", + "PCIE_BYP1_R_19", + "PCIE_LOGIC_OUTS_B11_R_10", + "PCIE_TRNRDLLPDATA37", + "PCIE_EE4BEG2_16", + "PCIE_CFGDSN37", + "PCIE_IMUX12_L_9", + "PCIE_IMUX42_L_18", + "PCIE_LOGIC_OUTS_B15_R_5", + "PCIE_EE4B1_8", + "PCIE_CFGMGMTDI21", + "PCIE_IMUX9_R_10", + "PCIE_SE2A1_11", + "PCIE_BYP4_R_1", + "PCIE_SE4C3_7", + "PCIE_BYP7_R_2", + "PCIE_EL1BEG2_13", + "PCIE_DRPDO4", + "PCIE_IMUX22_R_16", + "PCIE_CFGDSN33", + "PCIE_WL1END3_16", + "PCIE_IMUX39_L_0", + "PCIE_IMUX16_R_15", + "PCIE_SE2A3_11", + "PCIE_WW2A1_15", + "PCIE_SE4BEG2_10", + "PCIE_WW2END2_13", + "PCIE_IMUX43_R_14", + "PCIE_IMUX41_R_13", + "PCIE_CFGERRTLPCPLHEADER16", + "PCIE_IMUX10_L_17", + "PCIE_CFGDEVSTATUSFATALERRDETECTED", + "PCIE_IMUX36_R_8", + "PCIE_LH2_12", + "PCIE_CFGDSN55", + "PCIE_BLOCK_OUTS_B0_R_0", + "PCIE_CFGDSN40", + "PCIE_CFGINTERRUPTDO7", + "PCIE_LOGIC_OUTS_B17_R_11", + "PCIE_WW2END3_12", + "PCIE_CFGERRAERHEADERLOG76", + "PCIE_LOGIC_OUTS_B6_R_17", + "PCIE_WW4END2_19", + "PCIE_IMUX22_L_2", + "PCIE_DRPDI9", + "PCIE_NW2A1_13", + "PCIE_MIMTXWDATA31", + "PCIE_EL1BEG0_18", + "PCIE_FAN6_R_14", + "PCIE_IMUX24_L_5", + "PCIE_IMUX33_L_13", + "PCIE_LOGIC_OUTS_B23_R_3", + "PCIE_SE4BEG0_14", + "PCIE_CLK0_L_4", + "PCIE_IMUX22_R_18", + "PCIE_IMUX3_R_9", + "PCIE_IMUX17_R_16", + "PCIE_NE4C3_3", + "PCIE_BLOCK_OUTS_B1_R_6", + "PCIE_LL2TFCINIT2SEQ", + "PCIE_EE4A1_8", + "PCIE_LH5_18", + "PCIE_LOGIC_OUTS_B8_L_11", + "PCIE_IMUX30_L_3", + "PCIE_IMUX30_R_16", + "PCIE_BLOCK_OUTS_B0_R_10", + "PCIE_WW4C2_6", + "PCIE_EE4BEG1_15", + "PCIE_IMUX23_L_15", + "PCIE_MIMRXRDATA24", + "PCIE_IMUX47_R_3", + "PCIE_IMUX22_L_0", + "PCIE_DBGVECA8", + "PCIE_SW2A3_16", + "PCIE_LOGIC_OUTS_B14_L_0", + "PCIE_IMUX47_R_14", + "PCIE_PIPETX6DATA0", + "PCIE_CFGDSN46", + "PCIE_NE4C3_11", + "PCIE_IMUX20_L_11", + "PCIE_NE4C3_9", + "PCIE_LOGIC_OUTS_B19_L_7", + "PCIE_PLDBGVEC11", + "PCIE_PIPERX1DATA0", + "PCIE_CLK1_L_9", + "PCIE_WW2A1_9", + "PCIE_BYP1_L_1", + "PCIE_TRNFCPH1", + "PCIE_EE4B1_2", + "PCIE_BYP6_R_12", + "PCIE_PIPETX5DATA13", + "PCIE_TRNTD76", + "PCIE_FAN4_R_15", + "PCIE_IMUX10_L_0", + "PCIE_LOGIC_OUTS_B18_R_9", + "PCIE_LOGIC_OUTS_B15_L_2", + "PCIE_WW2A1_16", + "PCIE_WL1END1_15", + "PCIE_CFGDEVCONTROL2LTREN", + "PCIE_TRNTD123", + "PCIE_EE4B1_13", + "PCIE_SE4C2_10", + "PCIE_IMUX23_L_0", + "PCIE_EE4C3_2", + "PCIE_LOGIC_OUTS_B9_L_2", + "PCIE_MIMTXRDATA28", + "PCIE_MIMRXWDATA13", + "PCIE_NW4END2_17", + "PCIE_IMUX27_L_11", + "PCIE_IMUX47_L_1", + "PCIE_CTRL0_L_12", + "PCIE_MONITOR_P_3", + "PCIE_IMUX0_R_2", + "PCIE_IMUX6_L_7", + "PCIE_LOGIC_OUTS_B7_R_11", + "PCIE_IMUX35_R_14", + "PCIE_EE4B3_6", + "PCIE_SE4BEG3_6", + "PCIE_LOGIC_OUTS_B15_L_12", + "PCIE_IMUX23_L_18", + "PCIE_CFGROOTCONTROLSYSERRFATALERREN", + "PCIE_IMUX19_L_12", + "PCIE_WW4A3_6", + "PCIE_LOGIC_OUTS_B18_R_14", + "PCIE_ER1BEG1_7", + "PCIE_IMUX12_R_1", + "PCIE_IMUX3_L_0", + "PCIE_LOGIC_OUTS_B8_L_12", + "PCIE_NE4BEG2_8", + "PCIE_WW2END2_4", + "PCIE_IMUX46_L_13", + "PCIE_WL1END3_12", + "PCIE_LOGIC_OUTS_B13_L_0", + "PCIE_SE2A3_18", + "PCIE_BYP5_R_15", + "PCIE_TL2ERRHDR36", + "PCIE_DBGVECB45", + "PCIE_EE4C3_17", + "PCIE_MIMRXWDATA0", + "PCIE_EL1BEG2_16", + "PCIE_BYP5_L_5", + "PCIE_IMUX16_L_4", + "PCIE_TRNRERRFWD", + "PCIE_NE2A0_6", + "PCIE_EE4C1_17", + "PCIE_DBGVECB39", + "PCIE_EE2A0_16", + "PCIE_TRNTD71", + "PCIE_EE4BEG1_9", + "PCIE_PIPERX2DATA6", + "PCIE_MIMTXWDATA2", + "PCIE_LH5_1", + "PCIE_LOGIC_OUTS_B21_R_2", + "PCIE_LOGIC_OUTS_B14_R_14", + "PCIE_PIPERX7DATA0", + "PCIE_SW4A1_15", + "PCIE_TRNTDLLPDATA28", + "PCIE_BYP3_R_13", + "PCIE_IMUX11_L_7", + "PCIE_SW2A1_11", + "PCIE_LOGIC_OUTS_B10_L_11", + "PCIE_TRNTDLLPDATA29", + "PCIE_LOGIC_OUTS_B18_L_14", + "PCIE_NE4C1_19", + "PCIE_ER1BEG3_11", + "PCIE_CLK0_L_8", + "PCIE_WW4B1_14", + "PCIE_IMUX25_L_2", + "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", + "PCIE_SW4END2_0", + "PCIE_EE4C1_18", + "PCIE_BLOCK_OUTS_B3_L_9", + "PCIE_LOGIC_OUTS_B2_R_12", + "PCIE_IMUX13_R_19", + "PCIE_EE4BEG3_6", + "PCIE_FAN6_R_10", + "PCIE_CFGERRAERHEADERLOG120", + "PCIE_IMUX21_L_5", + "PCIE_LH3_17", + "PCIE_PIPERX5STATUS0", + "PCIE_IMUX29_R_12", + "PCIE_PIPERX6DATA10", + "PCIE_IMUX19_L_19", + "PCIE_BYP0_R_4", + "PCIE_LOGIC_OUTS_B9_R_4", + "PCIE_TRNTD16", + "PCIE_IMUX2_R_18", + "PCIE_IMUX34_R_7", + "PCIE_IMUX21_R_15", + "PCIE_BYP2_L_15", + "PCIE_LOGIC_OUTS_B15_R_2", + "PCIE_IMUX34_R_1", + "PCIE_PLDIRECTEDLTSSMNEW0", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", + "PCIE_IMUX37_L_7", + "PCIE_TRNRDLLPDATA56", + "PCIE_IMUX28_L_18", + "PCIE_MIMTXWDATA67", + "PCIE_EE4C3_14", + "PCIE_LOGIC_OUTS_B5_L_4", + "PCIE_LOGIC_OUTS_B16_L_10", + "PCIE_FAN0_L_17", + "PCIE_CLK0_L_14", + "PCIE_BYP7_L_18", + "PCIE_EE2A1_2", + "PCIE_SW4A1_19", + "PCIE_DBGVECB35", + "PCIE_IMUX35_L_3", + "PCIE_IMUX6_L_17", + "PCIE_BLOCK_OUTS_B2_L_14", + "PCIE_TRNRDLLPDATA0", + "PCIE_EE4B3_12", + "PCIE_BLOCK_OUTS_B3_R_0", + "PCIE_DBGVECA55", + "PCIE_WR1END3_9", + "PCIE_LH9_7", + "PCIE_IMUX34_R_5", + "PCIE_DRPDI8", + "PCIE_SW4END3_12", + "PCIE_EE4A3_12", + "PCIE_MIMRXWADDR4", + "PCIE_DBGVECA44", + "PCIE_EE2A3_4", + "PCIE_LOGIC_OUTS_B20_R_2", + "PCIE_LOGIC_OUTS_B18_L_12", + "PCIE_LOGIC_OUTS_B9_L_10", + "PCIE_IMUX34_L_3", + "PCIE_WW2A3_11", + "PCIE_FAN7_L_9", + "PCIE_BLOCK_OUTS_B3_L_4", + "PCIE_EE4C3_19", + "PCIE_SE2A3_4", + "PCIE_LOGIC_OUTS_B9_L_17", + "PCIE_SW4END1_0", + "PCIE_PIPERX0DATA0", + "PCIE_MIMTXRDATA41", + "PCIE_WW2A2_2", + "PCIE_BYP7_L_2", + "PCIE_IMUX45_R_7", + "PCIE_WW2A3_18", + "PCIE_CFGPORTNUMBER0", + "PCIE_TRNTD53", + "PCIE_TRNRD88", + "PCIE_EE4C0_7", + "PCIE_NE2A0_16", + "PCIE_EE4B3_1", + "PCIE_EE4B1_16", + "PCIE_SW4A0_16", + "PCIE_EE2A2_2", + "PCIE_IMUX23_R_19", + "PCIE_IMUX34_R_0", + "PCIE_IMUX42_R_14", + "PCIE_DRPDO1", + "PCIE_SE4C0_3", + "PCIE_MIMTXRADDR6", + "PCIE_CFGDEVID14", + "PCIE_IMUX15_L_6", + "PCIE_TRNRD82", + "PCIE_CFGERRAERHEADERLOG83", + "PCIE_LH6_0", + "PCIE_LOGIC_OUTS_B3_R_19", + "PCIE_IMUX8_R_4", + "PCIE_LOGIC_OUTS_B14_R_18", + "PCIE_WW4END0_6", + "PCIE_TRNTD57", + "PCIE_TRNFCPD10", + "PCIE_LOGIC_OUTS_B6_L_10", + "PCIE_TRNTD21", + "PCIE_WW2END1_13", + "PCIE_LOGIC_OUTS_B4_L_15", + "PCIE_FAN0_L_18", + "PCIE_WL1END2_10", + "PCIE_LOGIC_OUTS_B16_R_5", + "PCIE_CFGMSGDATA10", + "PCIE_LH11_5", + "PCIE_CFGVENDID9", + "PCIE_BYP2_R_3", + "PCIE_BYP0_L_16", + "PCIE_PIPETXMARGIN1", + "PCIE_SW4A3_19", + "PCIE_IMUX22_L_6", + "PCIE_MIMTXWDATA36", + "PCIE_NW4A2_15", + "PCIE_EE2BEG2_1", + "PCIE_EE4C2_12", + "PCIE_PIPERX7DATA15", + "PCIE_IMUX28_R_17", + "PCIE_LOGIC_OUTS_B4_L_10", + "PCIE_IMUX42_L_16", + "PCIE_IMUX15_L_17", + "PCIE_DBGVECA11", + "PCIE_CFGDSFUNCTIONNUMBER0", + "PCIE_BLOCK_OUTS_B1_L_0", + "PCIE_WW4A3_18", + "PCIE_LH12_2", + "PCIE_IMUX42_R_5", + "PCIE_BYP0_L_0", + "PCIE_WW2A0_16", + "PCIE_IMUX46_L_14", + "PCIE_LOGIC_OUTS_B2_R_6", + "PCIE_LOGIC_OUTS_B3_R_6", + "PCIE_IMUX4_L_10", + "PCIE_IMUX6_L_11", + "PCIE_WR1END2_9", + "PCIE_MIMRXWDATA12", + "PCIE_CFGVCTCVCMAP3", + "PCIE_IMUX42_L_13", + "PCIE_IMUX14_L_18", + "PCIE_EE2A0_0", + "PCIE_SW4A0_13", + "PCIE_BYP4_L_0", + "PCIE_NE4BEG1_3", + "PCIE_TRNRBARHIT6", + "PCIE_EE4BEG3_1", + "PCIE_BYP1_R_2", + "PCIE_IMUX35_R_17", + "PCIE_IMUX36_L_4", + "PCIE_WW4END2_16", + "PCIE_WW2A3_5", + "PCIE_EE4BEG1_14", + "PCIE_CFGERRTLPCPLHEADER31", + "PCIE_NW4END1_14", + "PCIE_BLOCK_OUTS_B2_R_8", + "PCIE_LOGIC_OUTS_B7_L_11", + "PCIE_IMUX15_R_1", + "PCIE_BYP1_L_5", + "PCIE_NW4END2_10", + "PCIE_IMUX17_L_0", + "PCIE_CFGDEVCONTROLMAXREADREQ2", + "PCIE_TRNTD60", + "PCIE_IMUX13_L_1", + "PCIE_IMUX37_R_16", + "PCIE_PIPERX7DATA12", + "PCIE_TRNTD55", + "PCIE_IMUX32_R_11", + "PCIE_IMUX26_R_6", + "PCIE_LOGIC_OUTS_B11_R_12", + "PCIE_IMUX14_R_18", + "PCIE_LOGIC_OUTS_B18_R_12", + "PCIE_LOGIC_OUTS_B17_L_9", + "PCIE_WW4B2_19", + "PCIE_IMUX25_L_1", + "PCIE_FAN2_R_2", + "PCIE_EL1BEG2_18", + "PCIE_TL2ERRHDR28", + "PCIE_NW4END2_15", + "PCIE_SE2A2_14", + "PCIE_WW2A3_14", + "PCIE_MIMTXRDATA27", + "PCIE_SW4END2_6", + "PCIE_FAN7_R_11", + "PCIE_TL2ERRHDR46", + "PCIE_MIMTXWDATA18", + "PCIE_SW4END2_16", + "PCIE_LOGIC_OUTS_B17_L_12", + "PCIE_IMUX7_R_7", + "PCIE_IMUX40_L_1", + "PCIE_IMUX33_L_15", + "PCIE_LOGIC_OUTS_B14_L_14", + "PCIE_NE2A3_11", + "PCIE_IMUX44_L_11", + "PCIE_EE4B0_13", + "PCIE_NE4BEG2_2", + "PCIE_LH12_6", + "PCIE_LOGIC_OUTS_B22_L_10", + "PCIE_XILUNCONNOUT15", + "PCIE_CFGMGMTDO15", + "PCIE_CFGERRAERHEADERLOG89", + "PCIE_IMUX22_L_9", + "PCIE_LOGIC_OUTS_B16_L_6", + "PCIE_IMUX5_L_14", + "PCIE_BYP5_L_18", + "PCIE_NE4C2_18", + "PCIE_SE4C0_13", + "PCIE_SE4BEG0_9", + "PCIE_TRNRD81", + "PCIE_FAN0_R_17", + "PCIE_EE2A0_2", + "PCIE_LH8_17", + "PCIE_WW4B1_4", + "PCIE_MIMRXRDATA37", + "PCIE_IMUX34_L_6", + "PCIE_FAN3_R_18", + "PCIE_PIPETX6DATA4", + "PCIE_EE2A1_7", + "PCIE_IMUX24_R_17", + "PCIE_CLK1_R_4", + "PCIE_CFGERRTLPCPLHEADER18", + "PCIE_SW4A1_18", + "PCIE_CFGERRTLPCPLHEADER47", + "PCIE_XILUNCONNOUT27", + "PCIE_CFGMGMTDWADDR7", + "PCIE_MIMTXRDATA25", + "PCIE_LOGIC_OUTS_B1_L_4", + "PCIE_WR1END3_7", + "PCIE_LOGIC_OUTS_B16_R_10", + "PCIE_LOGIC_OUTS_B21_L_4", + "PCIE_BYP1_R_7", + "PCIE_IMUX4_L_12", + "PCIE_CFGVCTCVCMAP2", + "PCIE_BYP1_L_12", + "PCIE_PIPETX1DATA4", + "PCIE_EE2A1_8", + "PCIE_WW2A2_0", + "PCIE_XILUNCONNOUT19", + "PCIE_CTRL0_L_8", + "PCIE_NE4BEG2_14", + "PCIE_WR1END3_12", + "PCIE_IMUX35_L_6", + "PCIE_IMUX9_L_13", + "PCIE_PIPERX4PHYSTATUS", + "PCIE_IMUX28_R_0", + "PCIE_TL2ERRHDR53", + "PCIE_TRNTD37", + "PCIE_LOGIC_OUTS_B9_L_15", + "PCIE_FAN4_L_13", + "PCIE_FUNCLVLRSTN", + "PCIE_PIPETX6CHARISK1", + "PCIE_MIMTXWDATA12", + "PCIE_EE2BEG3_2", + "PCIE_NE2A3_2", + "PCIE_IMUX23_L_4", + "PCIE_BYP2_R_13", + "PCIE_CTRL1_L_6", + "PCIE_IMUX41_R_9", + "PCIE_TRNRBARHIT0", + "PCIE_LOGIC_OUTS_B15_R_12", + "PCIE_MIMRXRDATA45", + "PCIE_IMUX14_R_17", + "PCIE_IMUX34_R_16", + "PCIE_IMUX15_L_10", + "PCIE_LOGIC_OUTS_B20_L_0", + "PCIE_BYP7_R_12", + "PCIE_FAN2_R_15", + "PCIE_DBGVECA17", + "PCIE_NW4END1_11", + "PCIE_BYP5_L_1", + "PCIE_MIMTXWDATA25", + "PCIE_BLOCK_OUTS_B0_R_16", + "PCIE_CFGVENDID11", + "PCIE_IMUX40_R_16", + "PCIE_IMUX1_R_2", + "PCIE_FAN1_L_8", + "PCIE_NW2A1_12", + "PCIE_MIMRXWADDR11", + "PCIE_BYP5_R_10", + "PCIE_DRPDO0", + "PCIE_WW4END3_0", + "PCIE_BYP4_L_15", + "PCIE_IMUX32_R_8", + "PCIE_BLOCK_OUTS_B0_L_15", + "PCIE_LOGIC_OUTS_B23_R_13", + "PCIE_TRNRD77", + "PCIE_LOGIC_OUTS_B14_L_9", + "PCIE_CFGERRAERHEADERLOG84", + "PCIE_XILUNCONNOUT35", + "PCIE_WW4B2_14", + "PCIE_DRPDI3", + "PCIE_WL1END3_10", + "PCIE_TRNFCNPH2", + "PCIE_LOGIC_OUTS_B23_L_10", + "PCIE_LOGIC_OUTS_B5_R_5", + "PCIE_CLK1_L_0", + "PCIE_EE4B2_14", + "PCIE_IMUX40_L_14", + "PCIE_EL1BEG3_4", + "PCIE_PIPERX3DATA13", + "PCIE_MIMTXRDATA6", + "PCIE_CLK0_L_15", + "PCIE_IMUX29_L_15", + "PCIE_CLK1_R_16", + "PCIE_MIMRXWDATA62", + "PCIE_PIPETX2CHARISK0", + "PCIE_PIPETX2DATA5", + "PCIE_LOGIC_OUTS_B11_L_14", + "PCIE_LOGIC_OUTS_B5_R_18", + "PCIE_IMUX41_L_16", + "PCIE_IMUX17_R_17", + "PCIE_IMUX24_R_14", + "PCIE_NW4END1_12", + "PCIE_EDTCHANNELSIN4", + "PCIE_TRNRD19", + "PCIE_MIMTXWADDR0", + "PCIE_SW4END0_14", + "PCIE_BYP2_R_17", + "PCIE_LH10_15", + "PCIE_TL2ERRHDR27", + "PCIE_CFGVENDID12", + "PCIE_LOGIC_OUTS_B3_R_2", + "PCIE_MIMTXRDATA4", + "PCIE_TL2ERRHDR0", + "PCIE_LOGIC_OUTS_B6_L_2", + "PCIE_MIMRXRDATA63", + "PCIE_TRNTD80", + "PCIE_IMUX11_L_16", + "PCIE_IMUX33_L_17", + "PCIE_PIPETX2DATA2", + "PCIE_CFGMGMTDO30", + "PCIE_WW4END1_19", + "PCIE_IMUX27_R_13", + "PCIE_IMUX44_L_12", + "PCIE_LOGIC_OUTS_B14_R_2", + "PCIE_SE4C0_7", + "PCIE_IMUX13_R_15", + "PCIE_BYP7_R_6", + "PCIE_BLOCK_OUTS_B2_R_15", + "PCIE_EE4C1_3", + "PCIE_NE2A3_3", + "PCIE_TRNRD115", + "PCIE_IMUX35_R_6", + "PCIE_IMUX25_L_8", + "PCIE_LOGIC_OUTS_B3_R_15", + "PCIE_IMUX45_L_2", + "PCIE_SE4BEG2_13", + "PCIE_LOGIC_OUTS_B0_R_2", + "PCIE_IMUX40_R_13", + "PCIE_WW4B0_14", + "PCIE_IMUX30_R_6", + "PCIE_IMUX33_R_11", + "PCIE_NW2A3_12", + "PCIE_CFGMGMTDO8", + "PCIE_SE4BEG3_10", + "PCIE_ER1BEG3_12", + "PCIE_CFGDSN19", + "PCIE_EE2A2_19", + "PCIE_LOGIC_OUTS_B18_L_6", + "PCIE_IMUX39_R_13", + "PCIE_IMUX30_R_4", + "PCIE_IMUX32_L_8", + "PCIE_FAN7_L_12", + "PCIE_EE4BEG1_10", + "PCIE_LOGIC_OUTS_B4_R_2", + "PCIE_WW2A1_6", + "PCIE_LOGIC_OUTS_B8_R_12", + "PCIE_LL2REPLAYROERR", + "PCIE_IMUX6_L_4", + "PCIE_LOGIC_OUTS_B21_R_11", + "PCIE_CFGAERINTERRUPTMSGNUM0", + "PCIE_PIPETX0DATA6", + "PCIE_MIMRXWADDR0", + "PCIE_BLOCK_OUTS_B3_R_11", + "PCIE_PIPERX1STATUS2", + "PCIE_PIPETX2DATA9", + "PCIE_LOGIC_OUTS_B9_R_0", + "PCIE_BLOCK_OUTS_B3_L_6", + "PCIE_IMUX21_L_15", + "PCIE_IMUX4_R_16", + "PCIE_IMUX0_L_16", + "PCIE_LOGIC_OUTS_B1_L_10", + "PCIE_IMUX36_L_18", + "PCIE_NW4A2_13", + "PCIE_LOGIC_OUTS_B19_L_12", + "PCIE_IMUX18_L_5", + "PCIE_NE2A0_8", + "PCIE_LOGIC_OUTS_B21_R_0", + "PCIE_EE4BEG3_16", + "PCIE_IMUX28_L_15", + "PCIE_PIPERX3VALID", + "PCIE_IMUX1_L_5", + "PCIE_IMUX6_R_13", + "PCIE_FAN6_R_3", + "PCIE_IMUX40_R_1", + "PCIE_LOGIC_OUTS_B14_R_17", + "PCIE_WW4C1_18", + "PCIE_DBGVECB4", + "PCIE_WL1END0_13", + "PCIE_LOGIC_OUTS_B17_R_16", + "PCIE_PIPETX0DATA13", + "PCIE_DBGVECB28", + "PCIE_IMUX39_L_19", + "PCIE_TRNTD17", + "PCIE_IMUX13_L_10", + "PCIE_CFGMSGRECEIVEDERRFATAL", + "PCIE_SW4END1_5", + "PCIE_CLK1_R_5", + "PCIE_DBGVECA26", + "PCIE_IMUX33_L_10", + "PCIE_LH2_15", + "PCIE_IMUX39_R_7", + "PCIE_IMUX0_R_16", + "PCIE_CTRL1_L_8", + "PCIE_LOGIC_OUTS_B15_L_4", + "PCIE_LOGIC_OUTS_B20_R_12", + "PCIE_FAN1_R_10", + "PCIE_NW2A2_18", + "PCIE_NE2A0_3", + "PCIE_LH2_17", + "PCIE_TRNRD116", + "PCIE_LH6_10", + "PCIE_LOGIC_OUTS_B13_L_15", + "PCIE_ER1BEG3_4", + "PCIE_EE4BEG0_16", + "PCIE_TRNRBARHIT7", + "PCIE_IMUX29_L_0", + "PCIE_LOGIC_OUTS_B20_R_8", + "PCIE_SW2A3_5", + "PCIE_CLK0_L_3", + "PCIE_BLOCK_OUTS_B2_L_18", + "PCIE_IMUX33_R_18", + "PCIE_PIPERX4DATA4", + "PCIE_IMUX18_L_11", + "PCIE_CFGMGMTDI28", + "PCIE_TL2ERRHDR55", + "PCIE_CFGSUBSYSID7", + "PCIE_MIMRXRADDR5", + "PCIE_IMUX13_L_4", + "PCIE_EE2A1_15", + "PCIE_CFGERRTLPCPLHEADER12", + "PCIE_IMUX47_L_19", + "PCIE_EE4BEG0_15", + "PCIE_IMUX1_R_1", + "PCIE_NW4A3_0", + "PCIE_IMUX30_R_15", + "PCIE_LOGIC_OUTS_B16_R_8", + "PCIE_BLOCK_OUTS_B1_R_5", + "PCIE_CFGSUBSYSVENDID1", + "PCIE_IMUX13_R_8", + "PCIE_BLOCK_OUTS_B3_R_18", + "PCIE_LH1_14", + "PCIE_WW4END3_4", + "PCIE_LH1_18", + "PCIE_LH5_7", + "PCIE_LOGIC_OUTS_B19_R_18", + "PCIE_NE4BEG1_17", + "PCIE_MIMRXRDATA33", + "PCIE_LOGIC_OUTS_B18_R_8", + "PCIE_IMUX40_L_7", + "PCIE_LOGIC_OUTS_B12_L_18", + "PCIE_MIMRXWDATA7", + "PCIE_CFGERRAERHEADERLOG52", + "PCIE_CTRL1_L_4", + "PCIE_TRNTD67", + "PCIE_IMUX40_L_16", + "PCIE_LOGIC_OUTS_B20_L_10", + "PCIE_SE2A1_13", + "PCIE_SW4A0_2", + "PCIE_CFGERRTLPCPLHEADER9", + "PCIE_ER1BEG1_6", + "PCIE_LOGIC_OUTS_B1_R_7", + "PCIE_CFGERRTLPCPLHEADER6", + "PCIE_FAN1_R_15", + "PCIE_FAN4_L_14", + "PCIE_FAN7_R_10", + "PCIE_IMUX14_L_4", + "PCIE_PIPERX0DATA13", + "PCIE_CTRL1_L_17", + "PCIE_FAN6_R_7", + "PCIE_LOGIC_OUTS_B2_R_18", + "PCIE_LOGIC_OUTS_B6_R_7", + "PCIE_NE2A0_18", + "PCIE_IMUX18_R_15", + "PCIE_DRPCLK", + "PCIE_IMUX13_L_3", + "PCIE_CFGMGMTDO12", + "PCIE_TRNRD7", + "PCIE_BYP3_R_8", + "PCIE_CFGDSN31", + "PCIE_IMUX2_L_7", + "PCIE_WW2A0_10", + "PCIE_TL2ERRHDR32", + "PCIE_SE4C2_4", + "PCIE_CFGERRAERHEADERLOG95", + "PCIE_IMUX23_R_0", + "PCIE_WW4B0_5", + "PCIE_LOGIC_OUTS_B6_R_3", + "PCIE_IMUX20_L_14", + "PCIE_IMUX16_R_3", + "PCIE_BYP5_L_19", + "PCIE_TRNRD80", + "PCIE_DRPDO7", + "PCIE_MIMRXWDATA60", + "PCIE_WW4END0_14", + "PCIE_BYP0_L_11", + "PCIE_FAN7_R_7", + "PCIE_TRNRD32", + "PCIE_IMUX6_R_19", + "PCIE_LOGIC_OUTS_B10_L_7", + "PCIE_IMUX23_R_18", + "PCIE_BYP6_R_14", + "PCIE_BLOCK_OUTS_B2_R_17", + "PCIE_IMUX33_R_2", + "PCIE_IMUX18_L_10", + "PCIE_USERCLK2", + "PCIE_EE2BEG3_16", + "PCIE_CFGPORTNUMBER5", + "PCIE_IMUX14_R_4", + "PCIE_PIPERX5CHARISK0", + "PCIE_BLOCK_OUTS_B2_R_7", + "PCIE_NE4BEG1_12", + "PCIE_DBGVECA50", + "PCIE_PIPERX3DATA8", + "PCIE_CFGDEVCONTROLNOSNOOPEN", + "PCIE_PIPERX5DATA3", + "PCIE_LOGIC_OUTS_B18_R_2", + "PCIE_LOGIC_OUTS_B9_L_7", + "PCIE_EE4B1_4", + "PCIE_LOGIC_OUTS_B6_R_1", + "PCIE_TL2ERRHDR34", + "PCIE_NW4A0_7", + "PCIE_BYP6_L_15", + "PCIE_IMUX43_R_15", + "PCIE_WL1END0_4", + "PCIE_IMUX12_L_4", + "PCIE_DBGVECB15", + "PCIE_CFGERRAERHEADERLOG121", + "PCIE_WW4END3_19", + "PCIE_IMUX19_L_4", + "PCIE_BYP0_R_11", + "PCIE_LOGIC_OUTS_B20_L_19", + "PCIE_NW4A2_7", + "PCIE_PIPETX4DATA10", + "PCIE_PLDBGVEC7", + "PCIE_TRNTD70", + "PCIE_IMUX0_L_7", + "PCIE_WW4B2_11", + "PCIE_LOGIC_OUTS_B17_L_1", + "PCIE_IMUX12_L_8", + "PCIE_LOGIC_OUTS_B10_L_0", + "PCIE_LOGIC_OUTS_B19_R_5", + "PCIE_LH3_3", + "PCIE_IMUX26_L_3", + "PCIE_ER1BEG3_16", + "PCIE_NE4BEG1_11", + "PCIE_IMUX12_L_3", + "PCIE_PL2SUSPENDOK", + "PCIE_PLUPSTREAMPREFERDEEMPH", + "PCIE_CTRL0_L_16", + "PCIE_WW4END3_5", + "PCIE_IMUX21_R_17", + "PCIE_SW4END3_11", + "PCIE_IMUX17_L_13", + "PCIE_LOGIC_OUTS_B6_L_13", + "PCIE_LOGIC_OUTS_B7_R_15", + "PCIE_BYP3_L_1", + "PCIE_IMUX22_L_4", + "PCIE_IMUX8_R_6", + "PCIE_BLOCK_OUTS_B2_L_4", + "PCIE_FAN3_L_19", + "PCIE_FAN1_L_15", + "PCIE_TRNTD68", + "PCIE_BYP5_R_14", + "PCIE_WR1END1_3", + "PCIE_IMUX14_L_5", + "PCIE_CFGDSN28", + "PCIE_TL2ERRHDR9", + "PCIE_SE4BEG0_13", + "PCIE_CTRL1_R_11", + "PCIE_LOGIC_OUTS_B12_R_0", + "PCIE_CLK0_R_13", + "PCIE_IMUX3_R_8", + "PCIE_CFGERRAERHEADERLOG58", + "PCIE_IMUX40_L_11", + "PCIE_LOGIC_OUTS_B10_L_18", + "PCIE_IMUX34_L_17", + "PCIE_IMUX27_L_12", + "PCIE_LOGIC_OUTS_B14_L_1", + "PCIE_IMUX26_L_17", + "PCIE_IMUX32_L_4", + "PCIE_CTRL1_R_2", + "PCIE_EE4B2_17", + "PCIE_FAN2_L_11", + "PCIE_IMUX3_L_6", + "PCIE_EE2BEG0_2", + "PCIE_IMUX23_L_16", + "PCIE_LH1_17", + "PCIE_PIPETX5POWERDOWN1", + "PCIE_LOGIC_OUTS_B7_L_14", + "PCIE_CFGERRAERHEADERLOG122", + "PCIE_IMUX36_L_6", + "PCIE_BYP1_R_18", + "PCIE_CTRL0_L_7", + "PCIE_FAN1_L_3", + "PCIE_IMUX7_L_9", + "PCIE_SE2A1_14", + "PCIE_SE4BEG3_7", + "PCIE_LH4_7", + "PCIE_BYP5_L_4", + "PCIE_BYP3_L_11", + "PCIE_IMUX44_R_4", + "PCIE_IMUX16_L_16", + "PCIE_PL2RECEIVERERR", + "PCIE_IMUX7_L_5", + "PCIE_IMUX39_R_3", + "PCIE_EE4B0_1", + "PCIE_PIPERX6STATUS2", + "PCIE_CFGMGMTDO18", + "PCIE_IMUX37_L_1", + "PCIE_FAN5_R_3", + "PCIE_CFGMGMTDO20", + "PCIE_MIMTXWDATA34", + "PCIE_LL2TLPRCV", + "PCIE_SW2A3_19", + "PCIE_SE4BEG3_18", + "PCIE_SW4END0_10", + "PCIE_ER1BEG0_6", + "PCIE_IMUX26_R_18", + "PCIE_EE4C0_14", + "PCIE_FAN3_L_8", + "PCIE_IMUX7_L_7", + "PCIE_PIPETX6DATA7", + "PCIE_LH11_10", + "PCIE_SE4BEG1_9", + "PCIE_IMUX12_R_12", + "PCIE_TL2ERRHDR51", + "PCIE_NE2A1_3", + "PCIE_EE4B2_4", + "PCIE_IMUX9_R_1", + "PCIE_IMUX22_L_5", + "PCIE_IMUX21_R_19", + "PCIE_PLDBGVEC1", + "PCIE_IMUX37_R_4", + "PCIE_IMUX35_L_18", + "PCIE_FAN6_L_12", + "PCIE_IMUX26_L_10", + "PCIE_CFGDSN45", + "PCIE_IMUX42_R_15", + "PCIE_EE4C0_2", + "PCIE_WW2A1_0", + "PCIE_WW4END0_10", + "PCIE_IMUX32_R_10", + "PCIE_IMUX2_R_9", + "PCIE_SW2A0_5", + "PCIE_CFGERRAERHEADERLOG51", + "PCIE_TRNRD94", + "PCIE_LOGIC_OUTS_B21_R_17", + "PCIE_NE2A3_6", + "PCIE_WL1END3_14", + "PCIE_TRNRDLLPDATA13", + "PCIE_LOGIC_OUTS_B23_R_9", + "PCIE_BYP3_R_1", + "PCIE_IMUX2_R_5", + "PCIE_IMUX17_L_16", + "PCIE_WW2END2_6", + "PCIE_IMUX31_R_19", + "PCIE_IMUX25_R_2", + "PCIE_MIMTXWDATA35", + "PCIE_EE4BEG2_12", + "PCIE_NW2A3_10", + "PCIE_LOGIC_OUTS_B5_L_9", + "PCIE_CFGVENDID2", + "PCIE_IMUX0_L_5", + "PCIE_NE4C3_2", + "PCIE_LOGIC_OUTS_B23_L_5", + "PCIE_FAN7_R_12", + "PCIE_LOGIC_OUTS_B1_L_7", + "PCIE_IMUX35_R_8", + "PCIE_EE4B1_7", + "PCIE_WW2A1_2", + "PCIE_BLOCK_OUTS_B2_L_13", + "PCIE_PIPETX2DATA14", + "PCIE_CTRL0_R_15", + "PCIE_SW2A1_14", + "PCIE_BYP4_L_8", + "PCIE_FAN0_L_2", + "PCIE_WW4C3_4", + "PCIE_SE4C1_0", + "PCIE_IMUX15_L_1", + "PCIE_IMUX33_R_7", + "PCIE_IMUX23_L_2", + "PCIE_WW4B1_2", + "PCIE_EE2BEG1_12", + "PCIE_PL2DIRECTEDLSTATE3", + "PCIE_CFGERRAERHEADERLOG125", + "PCIE_EE4BEG0_12", + "PCIE_EE4B0_17", + "PCIE_IMUX27_L_1", + "PCIE_IMUX7_R_3", + "PCIE_SW4A0_18", + "PCIE_FAN5_L_8", + "PCIE_PIPETX0CHARISK1", + "PCIE_CLK0_R_7", + "PCIE_IMUX29_L_16", + "PCIE_CFGDEVSTATUSCORRERRDETECTED", + "PCIE_IMUX46_L_4", + "PCIE_IMUX14_L_0", + "PCIE_WW4C2_5", + "PCIE_LH9_18", + "PCIE_IMUX43_L_8", + "PCIE_LH8_14", + "PCIE_CFGERRTLPCPLHEADER29", + "PCIE_SW4A2_14", + "PCIE_LH4_15", + "PCIE_LOGIC_OUTS_B11_L_6", + "PCIE_DRPDI0", + "PCIE_TRNTD83", + "PCIE_FAN5_R_9", + "PCIE_WW4END0_17", + "PCIE_CFGERRAERHEADERLOG57", + "PCIE_IMUX47_L_9", + "PCIE_IMUX38_L_7", + "PCIE_LOGIC_OUTS_B0_L_16", + "PCIE_CFGFORCEEXTENDEDSYNCON", + "PCIE_CTRL0_L_9", + "PCIE_WW4A2_13", + "PCIE_EE4A1_2", + "PCIE_PIPERX6DATA0", + "PCIE_WW4A2_11", + "PCIE_XILUNCONNOUT13", + "PCIE_IMUX43_L_1", + "PCIE_LH5_3", + "PCIE_WW2A1_8", + "PCIE_TRNTD62", + "PCIE_WW2END3_3", + "PCIE_WW4A2_19", + "PCIE_BYP2_R_9", + "PCIE_PIPERX5DATA5", + "PCIE_IMUX17_R_13", + "PCIE_XILUNCONNOUT31", + "PCIE_LOGIC_OUTS_B15_L_18", + "PCIE_MIMTXRADDR3", + "PCIE_TRNFCPD6", + "PCIE_LH12_15", + "PCIE_CFGERRAERHEADERLOG13", + "PCIE_BYP3_R_15", + "PCIE_SE4BEG0_5", + "PCIE_IMUX31_R_3", + "PCIE_LOGIC_OUTS_B20_L_11", + "PCIE_DRPDO15", + "PCIE_IMUX30_L_15", + "PCIE_SW2A3_18", + "PCIE_CFGCOMMANDIOENABLE", + "PCIE_TRNTD27", + "PCIE_WW4END1_10", + "PCIE_EL1BEG1_0", + "PCIE_EE2BEG1_17", + "PCIE_EE2BEG2_13", + "PCIE_IMUX23_L_19", + "PCIE_CFGSUBSYSID3", + "PCIE_LOGIC_OUTS_B21_L_2", + "PCIE_LOGIC_OUTS_B0_R_15", + "PCIE_LH6_9", + "PCIE_NW4A1_8", + "PCIE_PIPETX6ELECIDLE", + "PCIE_CLK0_L_0", + "PCIE_CLK0_R_12", + "PCIE_NE4BEG0_8", + "PCIE_LOGIC_OUTS_B6_R_14", + "PCIE_SE2A0_17", + "PCIE_TRNFCPD5", + "PCIE_IMUX15_R_2", + "PCIE_BYP0_L_8", + "PCIE_BYP7_L_10", + "PCIE_LOGIC_OUTS_B22_R_2", + "PCIE_TL2ERRHDR17", + "PCIE_WW2A1_19", + "PCIE_MIMRXWDATA42", + "PCIE_BYP7_R_7", + "PCIE_SE2A0_8", + "PCIE_LH3_0", + "PCIE_LNKCLKEN", + "PCIE_LOGIC_OUTS_B18_R_16", + "PCIE_WW2END0_8", + "PCIE_DRPDI11", + "PCIE_EE4B1_18", + "PCIE_WL1END2_16", + "PCIE_CFGERRTLPCPLHEADER42", + "PCIE_IMUX12_L_6", + "PCIE_IMUX12_L_0", + "PCIE_LH2_13", + "PCIE_IMUX20_L_2", + "PCIE_XILUNCONNOUT5", + "PCIE_EE4A0_6", + "PCIE_IMUX37_L_5", + "PCIE_EL1BEG1_18", + "PCIE_FAN4_L_18", + "PCIE_CTRL0_R_9", + "PCIE_CFGMGMTDO9", + "PCIE_BLOCK_OUTS_B1_L_6", + "PCIE_LOGIC_OUTS_B11_R_3", + "PCIE_NE2A1_10", + "PCIE_LH6_18", + "PCIE_CTRL1_L_3", + "PCIE_WW2END0_13", + "PCIE_IMUX13_R_6", + "PCIE_SE4C3_8", + "PCIE_SW4A3_15", + "PCIE_IMUX42_L_1", + "PCIE_NE2A3_12", + "PCIE_CFGERRAERHEADERLOG38", + "PCIE_PMVSELECT2", + "PCIE_LH11_6", + "PCIE_NE4BEG3_7", + "PCIE_LOGIC_OUTS_B16_R_18", + "PCIE_BYP5_R_0", + "PCIE_TRNTD75", + "PCIE_IMUX3_L_14", + "PCIE_SW4END3_3", + "PCIE_IMUX12_L_13", + "PCIE_CTRL1_L_18", + "PCIE_BLOCK_OUTS_B3_R_3", + "PCIE_LOGIC_OUTS_B17_L_5", + "PCIE_SW4END0_9", + "PCIE_IMUX7_L_8", + "PCIE_LOGIC_OUTS_B8_R_6", + "PCIE_CLK1_L_15", + "PCIE_NW2A1_19", + "PCIE_PIPETX7CHARISK1", + "PCIE_SE4BEG0_4", + "PCIE_LOGIC_OUTS_B0_R_17", + "PCIE_IMUX11_L_19", + "PCIE_IMUX28_L_8", + "PCIE_NW2A3_9", + "PCIE_FAN6_R_4", + "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", + "PCIE_TRNRD21", + "PCIE_NE2A3_17", + "PCIE_IMUX1_L_8", + "PCIE_IMUX38_R_10", + "PCIE_CTRL1_R_6", + "PCIE_IMUX43_R_1", + "PCIE_IMUX44_R_14", + "PCIE_NE4BEG0_9", + "PCIE_IMUX1_R_19", + "PCIE_NW4END0_16", + "PCIE_PIPERX2DATA15", + "PCIE_SW4END3_17", + "PCIE_SE2A3_12", + "PCIE_PIPERX0DATA1", + "PCIE_LOGIC_OUTS_B22_R_8", + "PCIE_LOGIC_OUTS_B19_L_19", + "PCIE_IMUX39_R_19", + "PCIE_CTRL0_L_18", + "PCIE_EE4C0_8", + "PCIE_EE2A2_9", + "PCIE_SE2A1_7", + "PCIE_LOGIC_OUTS_B7_L_18", + "PCIE_NE4C0_3", + "PCIE_PIPETX0DATA11", + "PCIE_PIPERX4DATA7", + "PCIE_WW2A3_9", + "PCIE_CFGERRAERHEADERLOG108", + "PCIE_IMUX37_L_16", + "PCIE_IMUX30_R_0", + "PCIE_EE2BEG3_5", + "PCIE_EE4A3_13", + "PCIE_IMUX6_R_12", + "PCIE_IMUX25_R_4", + "PCIE_FAN0_R_15", + "PCIE_EE2A2_1", + "PCIE_WL1END1_3", + "PCIE_WW2A3_10", + "PCIE_CFGERRTLPCPLHEADER11", + "PCIE_LOGIC_OUTS_B16_R_2", + "PCIE_SW4END1_17", + "PCIE_NW2A1_0", + "PCIE_IMUX19_L_17", + "PCIE_MIMRXWDATA31", + "PCIE_WW4A1_17", + "PCIE_MIMRXWDATA9", + "PCIE_LOGIC_OUTS_B5_R_7", + "PCIE_WW2END1_9", + "PCIE_BLOCK_OUTS_B0_R_9", + "PCIE_IMUX35_L_12", + "PCIE_LOGIC_OUTS_B9_L_16", + "PCIE_MIMTXRDATA63", + "PCIE_SW4A2_5", + "PCIE_LOGIC_OUTS_B16_R_1", + "PCIE_NE2A2_11", + "PCIE_IMUX35_R_15", + "PCIE_TRNFCNPH4", + "PCIE_IMUX30_L_12", + "PCIE_IMUX10_L_5", + "PCIE_SW4A3_9", + "PCIE_IMUX27_L_0", + "PCIE_MIMTXWADDR11", + "PCIE_IMUX31_L_15", + "PCIE_DBGVECA38", + "PCIE_CFGERRAERHEADERLOG124", + "PCIE_IMUX8_R_7", + "PCIE_IMUX26_R_19", + "PCIE_BYP6_L_12", + "PCIE_CFGDSN16", + "PCIE_SW2A0_9", + "PCIE_IMUX29_L_19", + "PCIE_IMUX8_L_3", + "PCIE_IMUX26_R_3", + "PCIE_EE2BEG2_7", + "PCIE_IMUX44_L_9", + "PCIE_EE2BEG2_17", + "PCIE_WL1END3_4", + "PCIE_NE4BEG0_7", + "PCIE_IMUX15_L_0", + "PCIE_IMUX31_R_8", + "PCIE_LOGIC_OUTS_B20_L_4", + "PCIE_IMUX9_L_17", + "PCIE_SE2A0_12", + "PCIE_LH3_7", + "PCIE_BLOCK_OUTS_B0_L_17", + "PCIE_TRNRD20", + "PCIE_TRNRD91", + "PCIE_FAN7_R_9", + "PCIE_LOGIC_OUTS_B22_L_4", + "PCIE_IMUX42_L_4", + "PCIE_IMUX7_L_6", + "PCIE_LOGIC_OUTS_B23_R_7", + "PCIE_IMUX36_R_15", + "PCIE_BLOCK_OUTS_B2_R_0", + "PCIE_PIPETX2DATA6", + "PCIE_MIMRXWDATA52", + "PCIE_PLDIRECTEDLTSSMSTALL", + "PCIE_SW4END1_19", + "PCIE_IMUX10_R_7", + "PCIE_CFGERRTLPCPLHEADER26", + "PCIE_DRPADDR2", + "PCIE_IMUX20_R_4", + "PCIE_LOGIC_OUTS_B9_R_17", + "PCIE_NE2A2_7", + "PCIE_EL1BEG1_14", + "PCIE_EE4C1_8", + "PCIE_LH5_19", + "PCIE_IMUX24_L_16", + "PCIE_TRNFCPD4", + "PCIE_CFGVCTCVCMAP1", + "PCIE_EE2A1_17", + "PCIE_IMUX29_R_1", + "PCIE_CFGMSGDATA7", + "PCIE_WW4C1_16", + "PCIE_IMUX33_R_3", + "PCIE_LOGIC_OUTS_B21_L_9", + "PCIE_CFGERRAERHEADERLOG66", + "PCIE_ER1BEG0_19", + "PCIE_TRNRD11", + "PCIE_IMUX24_R_10", + "PCIE_IMUX20_R_0", + "PCIE_TRNRD125", + "PCIE_SW4A2_19", + "PCIE_IMUX11_R_6", + "PCIE_CFGSUBSYSID2", + "PCIE_LH7_7", + "PCIE_EL1BEG2_8", + "PCIE_IMUX22_R_12", + "PCIE_LOGIC_OUTS_B21_L_13", + "PCIE_MONITOR_P_9", + "PCIE_CLK1_R_19", + "PCIE_BYP6_L_6", + "PCIE_MIMTXWDATA5", + "PCIE_ER1BEG1_11", + "PCIE_LOGIC_OUTS_B9_R_3", + "PCIE_SW4A1_17", + "PCIE_IMUX31_R_17", + "PCIE_LOGIC_OUTS_B12_R_3", + "PCIE_BYP1_R_16", + "PCIE_CFGERRTLPCPLHEADER32", + "PCIE_ER1BEG2_14", + "PCIE_EL1BEG1_11", + "PCIE_LH7_13", + "PCIE_IMUX27_L_18", + "PCIE_PIPERX5DATA11", + "PCIE_PIPERX6STATUS0", + "PCIE_PIPERX7DATA1", + "PCIE_IMUX5_R_6", + "PCIE_SW4A2_15", + "PCIE_DBGVECA39", + "PCIE_BYP3_R_12", + "PCIE_TRNTD48", + "PCIE_IMUX33_L_8", + "PCIE_WW4END0_13", + "PCIE_ER1BEG2_15", + "PCIE_IMUX12_L_7", + "PCIE_IMUX7_R_16", + "PCIE_WW4B1_18", + "PCIE_DBGVECA3", + "PCIE_WW2A1_3", + "PCIE_IMUX31_R_14", + "PCIE_PL2RECOVERY", + "PCIE_NE4C0_8", + "PCIE_SE4C0_14", + "PCIE_IMUX32_R_7", + "PCIE_IMUX1_L_1", + "PCIE_IMUX20_R_6", + "PCIE_SE2A0_15", + "PCIE_MIMTXWDATA38", + "PCIE_LOGIC_OUTS_B11_L_5", + "PCIE_WW4C2_12", + "PCIE_CFGDSBUSNUMBER2", + "PCIE_CFGDSN21", + "PCIE_WL1END0_3", + "PCIE_IMUX4_L_1", + "PCIE_BYP2_L_9", + "PCIE_NW2A1_9", + "PCIE_IMUX10_L_9", + "PCIE_IMUX42_L_15", + "PCIE_TRNTD38", + "PCIE_CTRL0_L_1", + "PCIE_EE2A3_19", + "PCIE_USERCLKPREBUFEN", + "PCIE_IMUX23_R_5", + "PCIE_MIMRXWADDR2", + "PCIE_IMUX45_R_18", + "PCIE_IMUX17_L_14", + "PCIE_NE2A0_13", + "PCIE_BYP4_L_14", + "PCIE_LOGIC_OUTS_B15_L_7", + "PCIE_BLOCK_OUTS_B3_R_19", + "PCIE_TRNRD44", + "PCIE_IMUX34_L_9", + "PCIE_MIMTXRDATA61", + "PCIE_CLK0_L_7", + "PCIE_CFGAERROOTERRFATALERRRECEIVED", + "PCIE_EE4BEG0_18", + "PCIE_PIPETX5DATA10", + "PCIE_LOGIC_OUTS_B0_L_1", + "PCIE_NE4C3_12", + "PCIE_CFGDSN17", + "PCIE_IMUX37_R_6", + "PCIE_IMUX26_R_0", + "PCIE_LOGIC_OUTS_B7_L_8", + "PCIE_FAN5_R_13", + "PCIE_IMUX2_L_13", + "PCIE_DRPDI5", + "PCIE_LOGIC_OUTS_B12_R_16", + "PCIE_IMUX44_L_6", + "PCIE_EL1BEG1_13", + "PCIE_SW2A0_2", + "PCIE_WW4A3_10", + "PCIE_IMUX4_R_13", + "PCIE_FAN4_R_17", + "PCIE_EDTCHANNELSOUT2", + "PCIE_WW4B0_9", + "PCIE_DBGSCLRK", + "PCIE_TRNRDLLPDATA44", + "PCIE_NW4END2_2", + "PCIE_PIPETX1ELECIDLE", + "PCIE_IMUX15_L_16", + "PCIE_LOGIC_OUTS_B22_R_17", + "PCIE_IMUX20_R_1", + "PCIE_CFGERRTLPCPLHEADER10", + "PCIE_LOGIC_OUTS_B23_L_3", + "PCIE_IMUX9_L_12", + "PCIE_NE2A2_3", + "PCIE_IMUX22_R_1", + "PCIE_NW4A1_18", + "PCIE_NE4BEG2_11", + "PCIE_SW2A3_2", + "PCIE_EE4A0_13", + "PCIE_IMUX12_L_11", + "PCIE_LOGIC_OUTS_B3_L_1", + "PCIE_PIPETX0DATA8", + "PCIE_EE2A1_1", + "PCIE_TRNRD123", + "PCIE_IMUX7_R_0", + "PCIE_WW4C0_13", + "PCIE_IMUX7_R_19", + "PCIE_BYP1_R_8", + "PCIE_PIPERX4ELECIDLE", + "PCIE_DBGVECB14", + "PCIE_IMUX38_R_2", + "PCIE_LH3_11", + "PCIE_SE4BEG2_6", + "PCIE_PLDBGVEC3", + "PCIE_PLDBGMODE0", + "PCIE_MIMTXWADDR9", + "PCIE_IMUX3_L_12", + "PCIE_EE2A1_16", + "PCIE_LOGIC_OUTS_B8_L_5", + "PCIE_NW2A0_17", + "PCIE_SW2A1_5", + "PCIE_DLRSTN", + "PCIE_CTRL0_R_11", + "PCIE_IMUX40_L_5", + "PCIE_DBGVECA29", + "PCIE_IMUX16_R_0", + "PCIE_NW4END2_11", + "PCIE_EE2A0_17", + "PCIE_IMUX13_L_15", + "PCIE_WW2A1_13", + "PCIE_SW4A3_10", + "PCIE_LL2LINKSTATUS1", + "PCIE_LOGIC_OUTS_B11_L_4", + "PCIE_TRNFCNPD0", + "PCIE_EE4C3_1", + "PCIE_FAN4_R_2", + "PCIE_PIPETX6CHARISK0", + "PCIE_CFGINTERRUPTMMENABLE1", + "PCIE_EE2BEG0_11", + "PCIE_WR1END0_3", + "PCIE_IMUX15_L_18", + "PCIE_IMUX45_L_10", + "PCIE_LOGIC_OUTS_B10_R_2", + "PCIE_EE4A0_5", + "PCIE_LOGIC_OUTS_B15_L_19", + "PCIE_NE2A3_7", + "PCIE_EE2BEG1_0", + "PCIE_LOGIC_OUTS_B13_L_5", + "PCIE_IMUX40_R_19", + "PCIE_CLK1_L_13", + "PCIE_LH3_2", + "PCIE_LH11_0", + "PCIE_EE2BEG1_4", + "PCIE_BYP4_R_0", + "PCIE_IMUX20_R_3", + "PCIE_IMUX18_L_14", + "PCIE_IMUX4_L_2", + "PCIE_IMUX10_R_4", + "PCIE_IMUX47_L_4", + "PCIE_SW4END3_14", + "PCIE_WW4A2_1", + "PCIE_DBGVECB8", + "PCIE_SW2A3_8", + "PCIE_EL1BEG1_15", + "PCIE_IMUX24_L_7", + "PCIE_LOGIC_OUTS_B11_R_17", + "PCIE_NE4C0_19", + "PCIE_LOGIC_OUTS_B22_R_0", + "PCIE_LH2_6", + "PCIE_CLK1_L_14", + "PCIE_EE4A3_6", + "PCIE_SE2A2_8", + "PCIE_IMUX34_R_3", + "PCIE_WR1END2_17", + "PCIE_CFGERRAERHEADERLOG80", + "PCIE_NE4BEG1_2", + "PCIE_EL1BEG0_1", + "PCIE_IMUX19_L_10", + "PCIE_IMUX20_R_12", + "PCIE_IMUX40_R_0", + "PCIE_NW4A1_3", + "PCIE_EL1BEG2_12", + "PCIE_IMUX19_R_12", + "PCIE_BYP1_R_4", + "PCIE_DBGSCLRA", + "PCIE_LH2_10", + "PCIE_IMUX11_R_19", + "PCIE_IMUX20_L_0", + "PCIE_WW4A1_19", + "PCIE_LOGIC_OUTS_B19_R_16", + "PCIE_DBGVECB2", + "PCIE_IMUX16_R_10", + "PCIE_BYP6_R_10", + "PCIE_EE4B3_16", + "PCIE_FAN7_R_6", + "PCIE_IMUX12_L_1", + "PCIE_NW4END1_13", + "PCIE_PIPETX0POWERDOWN0", + "PCIE_IMUX13_R_16", + "PCIE_IMUX3_L_1", + "PCIE_EE2A3_18", + "PCIE_MIMRXWDATA1", + "PCIE_PIPETX5DATA7", + "PCIE_LOGIC_OUTS_B18_L_1", + "PCIE_NE4C2_3", + "PCIE_NW4A1_10", + "PCIE_PIPERX0ELECIDLE", + "PCIE_TL2ERRHDR12", + "PCIE_TRNTD33", + "PCIE_EL1BEG1_6", + "PCIE_PIPETX3DATA13", + "PCIE_WW4END0_12", + "PCIE_CFGINTERRUPTDO3", + "PCIE_LOGIC_OUTS_B21_R_7", + "PCIE_NE2A3_14", + "PCIE_EL1BEG3_13", + "PCIE_BLOCK_OUTS_B0_L_12", + "PCIE_CFGDSN50", + "PCIE_WW2A2_5", + "PCIE_WW4A0_5", + "PCIE_SE4C3_6", + "PCIE_IMUX23_L_8", + "PCIE_TRNTD98", + "PCIE_SE4BEG1_5", + "PCIE_MIMTXRDATA9", + "PCIE_BLOCK_OUTS_B3_L_8", + "PCIE_IMUX35_L_4", + "PCIE_IMUX40_L_6", + "PCIE_SE2A3_3", + "PCIE_SW4A2_18", + "PCIE_WW2A0_4", + "PCIE_MIMTXWDATA56", + "PCIE_CFGMSGRECEIVEDASSERTINTC", + "PCIE_DRPADDR5", + "PCIE_EE4C1_4", + "PCIE_EE4A2_2", + "PCIE_EE4A0_19", + "PCIE_EE4A2_3", + "PCIE_MIMTXWDATA37", + "PCIE_MIMTXWDATA58", + "PCIE_IMUX7_R_2", + "PCIE_SW2A2_2", + "PCIE_NE4BEG0_19", + "PCIE_TRNTD72", + "PCIE_LH11_8", + "PCIE_IMUX40_L_10", + "PCIE_IMUX2_L_16", + "PCIE_IMUX30_R_14", + "PCIE_MIMTXRDATA58", + "PCIE_IMUX41_R_4", + "PCIE_CFGERRAERHEADERLOG72", + "PCIE_IMUX13_L_12", + "PCIE_IMUX24_R_0", + "PCIE_WW2END0_19", + "PCIE_LH4_5", + "PCIE_DBGVECB50", + "PCIE_SE2A2_0", + "PCIE_WW4B3_14", + "PCIE_IMUX24_L_19", + "PCIE_WW4END1_1", + "PCIE_LOGIC_OUTS_B19_R_0", + "PCIE_TRNRBARHIT5", + "PCIE_IMUX43_R_16", + "PCIE_IMUX18_R_6", + "PCIE_LH11_17", + "PCIE_FAN0_L_4", + "PCIE_MIMTXWDATA16", + "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", + "PCIE_BYP4_L_9", + "PCIE_IMUX14_L_11", + "PCIE_IMUX29_R_4", + "PCIE_IMUX39_L_10", + "PCIE_BLOCK_OUTS_B3_R_12", + "PCIE_PIPERX2DATA8", + "PCIE_NE4BEG3_19", + "PCIE_LOGIC_OUTS_B11_R_4", + "PCIE_BYP3_L_2", + "PCIE_WR1END0_6", + "PCIE_NE4C0_4", + "PCIE_LH7_16", + "PCIE_PLDBGVEC0", + "PCIE_LOGIC_OUTS_B22_R_4", + "PCIE_EE2BEG2_12", + "PCIE_BLOCK_OUTS_B2_R_9", + "PCIE_IMUX24_L_13", + "PCIE_NE4C3_5", + "PCIE_ER1BEG1_4", + "PCIE_CFGLINKCONTROLCLOCKPMEN", + "PCIE_LOGIC_OUTS_B5_L_14", + "PCIE_CFGDSN8", + "PCIE_BYP7_L_19", + "PCIE_DBGVECB12", + "PCIE_NE4C1_6", + "PCIE_NE4BEG1_5", + "PCIE_WW4A1_10", + "PCIE_PIPERX0VALID", + "PCIE_WW4END2_1", + "PCIE_IMUX29_R_7", + "PCIE_IMUX46_L_16", + "PCIE_IMUX15_R_3", + "PCIE_IMUX9_R_13", + "PCIE_TRNRD71", + "PCIE_EL1BEG1_4", + "PCIE_TRNTDLLPDATA13", + "PCIE_EE4B0_16", + "PCIE_IMUX36_R_18", + "PCIE_IMUX18_R_7", + "PCIE_DBGVECC2", + "PCIE_EE4B0_8", + "PCIE_EE4BEG3_14", + "PCIE_IMUX17_R_4", + "PCIE_TRNFCPH7", + "PCIE_DBGVECA35", + "PCIE_LOGIC_OUTS_B17_R_8", + "PCIE_CFGERRAERHEADERLOG53", + "PCIE_IMUX9_L_9", + "PCIE_CLK0_R_9", + "PCIE_TRNTDSTRDY2", + "PCIE_TRNFCCPLH7", + "PCIE_FAN2_R_0", + "PCIE_TRNFCNPH6", + "PCIE_LOGIC_OUTS_B12_R_2", + "PCIE_LH1_11", + "PCIE_NW4A3_16", + "PCIE_WW4END1_17", + "PCIE_SW2A1_4", + "PCIE_IMUX22_R_0", + "PCIE_BYP7_R_9", + "PCIE_NE2A2_13", + "PCIE_LOGIC_OUTS_B11_R_11", + "PCIE_NE4BEG1_9", + "PCIE_LOGIC_OUTS_B2_L_17", + "PCIE_LOGIC_OUTS_B9_R_6", + "PCIE_BYP3_R_16", + "PCIE_LH4_4", + "PCIE_BLOCK_OUTS_B3_R_4", + "PCIE_NW4END2_4", + "PCIE_IMUX40_R_8", + "PCIE_XILUNCONNOUT34", + "PCIE_LOGIC_OUTS_B19_R_7", + "PCIE_PLTXPMSTATE1", + "PCIE_FAN7_R_16", + "PCIE_BLOCK_OUTS_B2_L_6", + "PCIE_LH2_11", + "PCIE_WW4END2_2", + "PCIE_FAN0_L_9", + "PCIE_BYP5_L_9", + "PCIE_WL1END1_6", + "PCIE_EE4BEG1_8", + "PCIE_BYP4_L_2", + "PCIE_LOGIC_OUTS_B17_R_7", + "PCIE_NW2A1_2", + "PCIE_IMUX26_L_11", + "PCIE_CFGAERINTERRUPTMSGNUM1", + "PCIE_CFGERRAERHEADERLOG7", + "PCIE_NW2A3_17", + "PCIE_CFGSUBSYSVENDID6", + "PCIE_EE4C0_15", + "PCIE_TRNTD51", + "PCIE_BYP6_L_17", + "PCIE_LOGIC_OUTS_B14_L_17", + "PCIE_MIMRXWADDR3", + "PCIE_PIPERX1DATA5", + "PCIE_MIMRXRDATA6", + "PCIE_FAN2_R_14", + "PCIE_LOGIC_OUTS_B3_R_13", + "PCIE_LOGIC_OUTS_B10_L_4", + "PCIE_IMUX35_R_16", + "PCIE_PIPERX0DATA12", + "PCIE_BYP5_L_10", + "PCIE_MIMRXWADDR7", + "PCIE_CFGMSGRECEIVEDDEASSERTINTA", + "PCIE_LOGIC_OUTS_B9_R_8", + "PCIE_BYP6_L_11", + "PCIE_EE4C3_10", + "PCIE_SW4A1_9", + "PCIE_NW4END0_0", + "PCIE_CTRL0_L_15", + "PCIE_CLK0_L_17", + "PCIE_LOGIC_OUTS_B14_L_4", + "PCIE_EE4C0_11", + "PCIE_IMUX3_L_4", + "PCIE_WR1END2_7", + "PCIE_MIMTXRDATA42", + "PCIE_XILUNCONNOUT7", + "PCIE_NE4C2_12", + "PCIE_LOGIC_OUTS_B18_L_16", + "PCIE_IMUX35_L_17", + "PCIE_DBGVECA28", + "PCIE_EE2BEG3_0", + "PCIE_LOGIC_OUTS_B2_L_11", + "PCIE_IMUX4_R_2", + "PCIE_NW4A3_18", + "PCIE_MIMRXWEN", + "PCIE_MIMTXWDATA22", + "PCIE_MIMRXRDATA65", + "PCIE_IMUX41_R_15", + "PCIE_TL2ERRHDR54", + "PCIE_EE4BEG3_9", + "PCIE_IMUX34_L_10", + "PCIE_IMUX27_L_16", + "PCIE_IMUX11_R_13", + "PCIE_TRNFCCPLD6", + "PCIE_TRNTEOF", + "PCIE_FAN1_L_5", + "PCIE_MIMRXWDATA27", + "PCIE_CFGMGMTDO1", + "PCIE_EE4C1_7", + "PCIE_TRNRDLLPDATA6", + "PCIE_SW2A3_14", + "PCIE_EE4C1_1", + "PCIE_IMUX12_R_5", + "PCIE_MIMRXRADDR3", + "PCIE_WW4B2_9", + "PCIE_CFGDSN24", + "PCIE_IMUX22_L_18", + "PCIE_EE4B1_0", + "PCIE_TRNFCCPLD3", + "PCIE_PIPERX3DATA9", + "PCIE_IMUX38_R_15", + "PCIE_CTRL1_R_18", + "PCIE_DRPADDR0", + "PCIE_PIPERX3ELECIDLE", + "PCIE_DBGVECA56", + "PCIE_MONITOR_N_18", + "PCIE_IMUX9_L_11", + "PCIE_FAN1_R_4", + "PCIE_IMUX0_R_10", + "PCIE_LOGIC_OUTS_B9_L_18", + "PCIE_WW4C1_2", + "PCIE_PIPERX3DATA5", + "PCIE_LOGIC_OUTS_B1_R_6", + "PCIE_LOGIC_OUTS_B16_L_15", + "PCIE_IMUX27_R_7", + "PCIE_LOGIC_OUTS_B4_L_2", + "PCIE_IMUX0_L_18", + "PCIE_IMUX28_L_3", + "PCIE_NW4A3_10", + "PCIE_CFGINTERRUPTDI7", + "PCIE_NE4C1_10", + "PCIE_EE4C2_6", + "PCIE_IMUX13_L_11", + "PCIE_LOGIC_OUTS_B13_R_11", + "PCIE_LOGIC_OUTS_B15_L_13", + "PCIE_WW4C0_6", + "PCIE_LOGIC_OUTS_B7_L_7", + "PCIE_SE4BEG0_16", + "PCIE_NW4END0_8", + "PCIE_WW2END2_7", + "PCIE_CFGERRINTERNALCORN", + "PCIE_SE2A3_7", + "PCIE_PIPETXRCVRDET", + "PCIE_IMUX40_R_3", + "PCIE_LOGIC_OUTS_B20_R_5", + "PCIE_TRNRD93", + "PCIE_WW4END1_3", + "PCIE_PL2DIRECTEDLSTATE0", + "PCIE_TRNRD90", + "PCIE_IMUX15_L_2", + "PCIE_WW4A1_13", + "PCIE_MIMTXWDATA66", + "PCIE_MIMRXRDATA56", + "PCIE_SE2A1_19", + "PCIE_EL1BEG2_4", + "PCIE_LH10_18", + "PCIE_LOGIC_OUTS_B12_R_9", + "PCIE_PIPERX0DATA10", + "PCIE_IMUX36_L_1", + "PCIE_BYP3_L_16", + "PCIE_FAN4_R_18", + "PCIE_IMUX38_L_1", + "PCIE_MIMTXRDATA24", + "PCIE_PIPERX2DATA1", + "PCIE_IMUX32_R_6", + "PCIE_BYP4_R_11", + "PCIE_ER1BEG2_7", + "PCIE_WW4B3_16", + "PCIE_LOGIC_OUTS_B14_L_15", + "PCIE_TRNRDLLPDATA18", + "PCIE_TRNTBUFAV3", + "PCIE_EE4B0_11", + "PCIE_IMUX45_L_9", + "PCIE_TRNRDLLPDATA51", + "PCIE_NW4A1_4", + "PCIE_TRNTDLLPDATA3", + "PCIE_IMUX28_L_11", + "PCIE_CFGDSDEVICENUMBER1", + "PCIE_CFGMSGRECEIVED", + "PCIE_EE4BEG0_5", + "PCIE_LOGIC_OUTS_B15_R_13", + "PCIE_BYP6_R_6", + "PCIE_BLOCK_OUTS_B1_L_16", + "PCIE_CTRL1_R_10", + "PCIE_IMUX8_L_19", + "PCIE_TRNTD63", + "PCIE_IMUX42_R_8", + "PCIE_BLOCK_OUTS_B3_R_1", + "PCIE_WW2END1_2", + "PCIE_LOGIC_OUTS_B6_R_2", + "PCIE_CTRL0_L_13", + "PCIE_LOGIC_OUTS_B3_R_3", + "PCIE_WW4END3_13", + "PCIE_LOGIC_OUTS_B10_R_15", + "PCIE_IMUX1_R_0", + "PCIE_NE4C2_10", + "PCIE_SE2A1_6", + "PCIE_DBGVECB9", + "PCIE_SW4A1_14", + "PCIE_NW4END1_16", + "PCIE_WW4A1_4", + "PCIE_LOGIC_OUTS_B2_L_19", + "PCIE_IMUX10_L_1", + "PCIE_EL1BEG3_5", + "PCIE_IMUX17_L_5", + "PCIE_CFGPORTNUMBER3", + "PCIE_WL1END1_8", + "PCIE_LOGIC_OUTS_B8_R_5", + "PCIE_LOGIC_OUTS_B23_R_17", + "PCIE_IMUX40_R_11", + "PCIE_SE4BEG3_5", + "PCIE_SW4END0_11", + "PCIE_IMUX28_R_11", + "PCIE_LOGIC_OUTS_B16_L_19", + "PCIE_PIPERX1DATA8", + "PCIE_CFGDEVID7", + "PCIE_DBGVECA27", + "PCIE_IMUX32_L_0", + "PCIE_PIPETX1DATA9", + "PCIE_NW2A3_14", + "PCIE_EE4A0_9", + "PCIE_NW4END3_0", + "PCIE_IMUX46_L_1", + "PCIE_CFGMGMTWRENN", + "PCIE_IMUX32_L_5", + "PCIE_TL2ERRHDR43", + "PCIE_NE4BEG1_6", + "PCIE_WW4A0_7", + "PCIE_IMUX34_R_10", + "PCIE_MIMTXRDATA49", + "PCIE_BYP4_L_18", + "PCIE_IMUX31_L_19", + "PCIE_ER1BEG2_4", + "PCIE_EE4C0_4", + "PCIE_TRNTERRFWD", + "PCIE_WW4END0_4", + "PCIE_IMUX10_L_13", + "PCIE_CFGDEVID12", + "PCIE_PLDIRECTEDLTSSMNEW3", + "PCIE_FAN3_L_9", + "PCIE_SW4END1_9", + "PCIE_PIPERX1DATA4", + "PCIE_WW4END1_15", + "PCIE_CLK0_L_5", + "PCIE_IMUX21_R_14", + "PCIE_BYP0_L_2", + "PCIE_TRNRDLLPSRCRDY1", + "PCIE_LOGIC_OUTS_B21_L_5", + "PCIE_IMUX42_L_14", + "PCIE_WW4B0_3", + "PCIE_DRPWE", + "PCIE_EE2A3_15", + "PCIE_WW4END0_2", + "PCIE_IMUX19_R_8", + "PCIE_LOGIC_OUTS_B5_L_0", + "PCIE_TRNTREM1", + "PCIE_LOGIC_OUTS_B7_R_18", + "PCIE_EE4A2_13", + "PCIE_PIPERX1DATA12", + "PCIE_IMUX24_R_8", + "PCIE_LOGIC_OUTS_B17_R_9", + "PCIE_IMUX43_L_9", + "PCIE_WW4B1_7", + "PCIE_WW2END0_9", + "PCIE_WW2A1_5", + "PCIE_DRPADDR1", + "PCIE_CFGERRAERHEADERLOG74", + "PCIE_IMUX36_R_5", + "PCIE_IMUX0_L_19", + "PCIE_IMUX40_R_14", + "PCIE_LOGIC_OUTS_B12_R_4", + "PCIE_IMUX0_R_15", + "PCIE_ER1BEG1_1", + "PCIE_MIMRXRDATA5", + "PCIE_EE4C1_13", + "PCIE_IMUX11_L_4", + "PCIE_LOGIC_OUTS_B23_L_6", + "PCIE_CFGTRANSACTION", + "PCIE_TRNRD96", + "PCIE_IMUX6_R_1", + "PCIE_CTRL1_R_9", + "PCIE_SE2A3_6", + "PCIE_FAN5_L_1", + "PCIE_TL2ERRHDR38", + "PCIE_LOGIC_OUTS_B6_L_5", + "PCIE_IMUX6_L_12", + "PCIE_LOGIC_OUTS_B3_L_4", + "PCIE_SE4C2_6", + "PCIE_FAN0_L_3", + "PCIE_IMUX2_L_3", + "PCIE_LOGIC_OUTS_B7_R_5", + "PCIE_CFGERRTLPCPLHEADER35", + "PCIE_CFGDEVID1", + "PCIE_SE4C0_8", + "PCIE_TL2ERRHDR39", + "PCIE_NW2A2_1", + "PCIE_BYP3_R_4", + "PCIE_TRNTD32", + "PCIE_IMUX38_R_5", + "PCIE_MIMRXRDATA38", + "PCIE_TRNRDLLPDATA31", + "PCIE_IMUX17_R_3", + "PCIE_NE4BEG3_18", + "PCIE_LOGIC_OUTS_B14_R_19", + "PCIE_IMUX26_L_5", + "PCIE_EE4B0_0", + "PCIE_IMUX41_L_6", + "PCIE_FAN5_R_5", + "PCIE_CLK0_L_9", + "PCIE_IMUX27_R_17", + "PCIE_NE4BEG2_17", + "PCIE_FAN3_L_2", + "PCIE_CFGDSN3", + "PCIE_DRPDI4", + "PCIE_XILUNCONNOUT25", + "PCIE_LOGIC_OUTS_B12_R_15", + "PCIE_LOGIC_OUTS_B13_R_16", + "PCIE_LOGIC_OUTS_B2_R_15", + "PCIE_PIPERX1DATA1", + "PCIE_EE2A3_0", + "PCIE_TRNRD70", + "PCIE_IMUX34_L_5", + "PCIE_IMUX27_R_3", + "PCIE_CFGERRAERHEADERLOG6", + "PCIE_TRNRD53", + "PCIE_IMUX22_L_13", + "PCIE_CFGERRAERHEADERLOG101", + "PCIE_IMUX9_L_1", + "PCIE_IMUX27_R_9", + "PCIE_MIMRXRDATA3", + "PCIE_BLOCK_OUTS_B1_L_14", + "PCIE_BYP6_L_5", + "PCIE_EE2BEG2_6", + "PCIE_EE4C3_5", + "PCIE_SW4A0_10", + "PCIE_MIMTXWDATA51", + "PCIE_MIMTXWDATA60", + "PCIE_LH7_12", + "PCIE_EE4B2_10", + "PCIE_IMUX24_R_9", + "PCIE_TRNRD117", + "PCIE_IMUX35_R_10", + "PCIE_TRNRD95", + "PCIE_CFGERRAERHEADERLOG88", + "PCIE_BYP0_R_19", + "PCIE_WW2END0_12", + "PCIE_IMUX13_L_18", + "PCIE_ER1BEG3_3", + "PCIE_SW4END1_4", + "PCIE_CFGERRAERHEADERLOG3", + "PCIE_IMUX11_L_13", + "PCIE_ER1BEG2_9", + "PCIE_BYP5_L_2", + "PCIE_TL2ERRHDR20", + "PCIE_FAN0_L_11", + "PCIE_TRNTD8", + "PCIE_LH7_8", + "PCIE_IMUX24_L_11", + "PCIE_DBGVECB58", + "PCIE_IMUX34_R_17", + "PCIE_SW4END1_15", + "PCIE_TRNTD104", + "PCIE_EE2BEG2_3", + "PCIE_EE4A3_7", + "PCIE_SW2A1_1", + "PCIE_LOGIC_OUTS_B1_R_10", + "PCIE_IMUX40_L_9", + "PCIE_TRNRD74", + "PCIE_EE2A3_1", + "PCIE_EDTCHANNELSOUT4", + "PCIE_WW2END1_7", + "PCIE_TL2ERRHDR48", + "PCIE_IMUX30_L_16", + "PCIE_IMUX32_L_19", + "PCIE_FAN1_L_13", + "PCIE_NW4END0_13", + "PCIE_IMUX15_R_6", + "PCIE_ER1BEG3_17", + "PCIE_WW4END0_8", + "PCIE_IMUX29_L_9", + "PCIE_LOGIC_OUTS_B20_L_1", + "PCIE_PIPETX0COMPLIANCE", + "PCIE_NE4C3_18", + "PCIE_CFGERRAERHEADERLOG65", + "PCIE_TRNRDLLPDATA10", + "PCIE_PIPETX2DATA1", + "PCIE_CFGDEVCONTROLMAXREADREQ1", + "PCIE_LOGIC_OUTS_B6_L_9", + "PCIE_LOGIC_OUTS_B23_L_12", + "PCIE_TRNRDLLPDATA20", + "PCIE_IMUX12_L_14", + "PCIE_SW2A1_15", + "PCIE_PLTRANSMITHOTRST", + "PCIE_LH12_9", + "PCIE_IMUX18_R_11", + "PCIE_EE4A3_9", + "PCIE_EL1BEG0_17", + "PCIE_IMUX7_L_16", + "PCIE_LL2SENDPMACK", + "PCIE_TRNRD34", + "PCIE_IMUX37_R_7", + "PCIE_EE4B1_3", + "PCIE_IMUX11_L_15", + "PCIE_WW2A2_12", + "PCIE_WW2A1_10", + "PCIE_FAN3_L_17", + "PCIE_FAN6_L_7", + "PCIE_RECEIVEDFUNCLVLRSTN", + "PCIE_BYP2_L_7", + "PCIE_SE4C0_12", + "PCIE_PIPETX3DATA10", + "PCIE_LOGIC_OUTS_B11_R_15", + "PCIE_FAN5_R_15", + "PCIE_EE4C3_9", + "PCIE_BYP2_L_19", + "PCIE_TRNRDLLPDATA48", + "PCIE_LH9_11", + "PCIE_CFGERRAERHEADERLOG45", + "PCIE_TRNRDLLPDATA34", + "PCIE_EE2A0_15", + "PCIE_WW4C3_12", + "PCIE_SYSRSTN", + "PCIE_IMUX1_L_9", + "PCIE_FAN7_L_6", + "PCIE_IMUX38_R_18", + "PCIE_MIMTXWDATA9", + "PCIE_IMUX24_L_1", + "PCIE_TRNFCNPH0", + "PCIE_WW4C1_9", + "PCIE_LOGIC_OUTS_B20_R_14", + "PCIE_WW4A1_1", + "PCIE_BYP7_R_19", + "PCIE_EE2BEG0_17", + "PCIE_IMUX40_L_12", + "PCIE_BLOCK_OUTS_B0_R_1", + "PCIE_TL2ERRHDR22", + "PCIE_WW4END3_7", + "PCIE_LOGIC_OUTS_B14_L_5", + "PCIE_LOGIC_OUTS_B11_R_6", + "PCIE_FAN0_R_14", + "PCIE_LOGIC_OUTS_B6_R_8", + "PCIE_CFGERRAERHEADERLOG97", + "PCIE_PIPETXMARGIN2", + "PCIE_CFGERRAERHEADERLOG56", + "PCIE_SE4C3_13", + "PCIE_WW2END3_14", + "PCIE_IMUX30_R_2", + "PCIE_WW4A3_15", + "PCIE_MIMTXWDATA65", + "PCIE_IMUX42_L_0", + "PCIE_IMUX14_L_3", + "PCIE_WR1END1_1", + "PCIE_BLOCK_OUTS_B3_L_7", + "PCIE_TRNTDSTRDY0", + "PCIE_LOGIC_OUTS_B12_L_19", + "PCIE_LOGIC_OUTS_B15_L_16", + "PCIE_IMUX39_L_11", + "PCIE_WW2END2_8", + "PCIE_IMUX31_R_13", + "PCIE_LOGIC_OUTS_B19_R_14", + "PCIE_SW4A1_11", + "PCIE_IMUX39_R_2", + "PCIE_BYP6_R_15", + "PCIE_IMUX9_R_0", + "PCIE_TRNFCCPLH5", + "PCIE_IMUX32_R_4", + "PCIE_BLOCK_OUTS_B0_L_2", + "PCIE_FAN6_R_5", + "PCIE_BLOCK_OUTS_B0_R_4", + "PCIE_WW4A1_16", + "PCIE_TL2ERRHDR56", + "PCIE_LOGIC_OUTS_B15_R_17", + "PCIE_NE2A0_11", + "PCIE_IMUX25_L_15", + "PCIE_IMUX13_R_2", + "PCIE_LOGIC_OUTS_B15_R_10", + "PCIE_BLOCK_OUTS_B1_L_3", + "PCIE_WR1END0_1", + "PCIE_FAN3_R_3", + "PCIE_PIPETX2DATA12", + "PCIE_IMUX2_L_1", + "PCIE_CLK1_R_3", + "PCIE_CFGVCTCVCMAP6", + "PCIE_SW2A0_10", + "PCIE_BLOCK_OUTS_B1_R_18", + "PCIE_CFGMSGRECEIVEDDEASSERTINTB", + "PCIE_IMUX24_L_10", + "PCIE_ER1BEG0_0", + "PCIE_CFGDSN47", + "PCIE_NE2A0_0", + "PCIE_TL2ERRHDR61", + "PCIE_ER1BEG1_9", + "PCIE_IMUX34_L_16", + "PCIE_MIMRXRDATA21", + "PCIE_NW4A1_11", + "PCIE_LOGIC_OUTS_B4_L_0", + "PCIE_MIMRXWDATA35", + "PCIE_FAN6_R_6", + "PCIE_EE4C3_4", + "PCIE_EE2BEG0_0", + "PCIE_LOGIC_OUTS_B16_R_7", + "PCIE_IMUX34_R_4", + "PCIE_TRNFCNPD1", + "PCIE_NE2A1_16", + "PCIE_LH6_17", + "PCIE_CFGMSGRECEIVEDERRCOR", + "PCIE_FAN2_L_19", + "PCIE_LH3_15", + "PCIE_EE4BEG1_18", + "PCIE_WW4A1_2", + "PCIE_TL2ERRHDR60", + "PCIE_IMUX34_L_15", + "PCIE_CFGMGMTDI6", + "PCIE_NE4C2_2", + "PCIE_LH8_11", + "PCIE_IMUX16_R_19", + "PCIE_CFGINTERRUPTDO4", + "PCIE_NW4A1_9", + "PCIE_DRPDI6", + "PCIE_CFGPCIELINKSTATE1", + "PCIE_LOGIC_OUTS_B3_L_3", + "PCIE_DRPDO8", + "PCIE_PIPETX5DATA11", + "PCIE_CFGPCIELINKSTATE2", + "PCIE_LH4_12", + "PCIE_IMUX20_R_8", + "PCIE_LOGIC_OUTS_B9_L_6", + "PCIE_EDTCHANNELSOUT3", + "PCIE_EE4B0_7", + "PCIE_WW4C2_1", + "PCIE_IMUX45_R_4", + "PCIE_LOGIC_OUTS_B3_L_14", + "PCIE_IMUX24_R_11", + "PCIE_IMUX38_R_9", + "PCIE_IMUX22_R_3", + "PCIE_IMUX33_L_0", + "PCIE_PIPETX4DATA15", + "PCIE_FAN4_R_1", + "PCIE_PIPETX4DATA0", + "PCIE_CFGINTERRUPTN", + "PCIE_LOGIC_OUTS_B20_L_13", + "PCIE_FAN4_L_5", + "PCIE_CFGERRAERHEADERLOG105", + "PCIE_NW4A2_6", + "PCIE_BLOCK_OUTS_B3_R_6", + "PCIE_IMUX22_R_7", + "PCIE_LOGIC_OUTS_B6_R_19", + "PCIE_TRNTDLLPDATA1", + "PCIE_WW4B2_3", + "PCIE_EE4A2_14", + "PCIE_LOGIC_OUTS_B0_L_8", + "PCIE_TL2ERRHDR63", + "PCIE_PIPERX2STATUS2", + "PCIE_WW4END3_3", + "PCIE_EE4B2_13", + "PCIE_LOGIC_OUTS_B2_R_13", + "PCIE_PMVOUT", + "PCIE_NW4END2_7", + "PCIE_IMUX12_R_9", + "PCIE_MIMTXWDATA14", + "PCIE_TRNTD15", + "PCIE_CFGAERINTERRUPTMSGNUM4", + "PCIE_PIPERX6DATA1", + "PCIE_IMUX39_R_8", + "PCIE_PIPERX4DATA3", + "PCIE_PIPERX3DATA0", + "PCIE_IMUX23_L_12", + "PCIE_SE4C3_16", + "PCIE_CFGMGMTDO25", + "PCIE_WW2END3_5", + "PCIE_SE4C3_5", + "PCIE_EE4A0_17", + "PCIE_IMUX44_R_19", + "PCIE_PIPETX0DATA7", + "PCIE_NW4END2_12", + "PCIE_SE2A2_1", + "PCIE_FAN7_R_19", + "PCIE_MIMRXRDATA2", + "PCIE_LOGIC_OUTS_B23_R_0", + "PCIE_NW4A0_8", + "PCIE_WL1END0_10", + "PCIE_IMUX19_R_6", + "PCIE_IMUX19_L_5", + "PCIE_WW2END1_3", + "PCIE_IMUX10_L_6", + "PCIE_SE2A2_13", + "PCIE_WW4A2_17", + "PCIE_IMUX2_R_13", + "PCIE_LOGIC_OUTS_B5_L_17", + "PCIE_TRNTD66", + "PCIE_IMUX46_R_18", + "PCIE_IMUX17_L_4", + "PCIE_TRNTSRCRDY", + "PCIE_LOGIC_OUTS_B3_R_1", + "PCIE_LOGIC_OUTS_B11_R_18", + "PCIE_LOGIC_OUTS_B10_R_18", + "PCIE_IMUX13_L_19", + "PCIE_LH11_13", + "PCIE_LH10_10", + "PCIE_LOGIC_OUTS_B4_R_3", + "PCIE_TRNTD0", + "PCIE_SW2A2_6", + "PCIE_IMUX17_R_14", + "PCIE_WW4B3_1", + "PCIE_PIPERX6DATA2", + "PCIE_SW4A2_16", + "PCIE_LOGIC_OUTS_B22_L_18", + "PCIE_EE2BEG1_1", + "PCIE_IMUX0_L_6", + "PCIE_IMUX39_L_7", + "PCIE_IMUX30_L_9", + "PCIE_BYP2_R_6", + "PCIE_IMUX9_R_12", + "PCIE_IMUX20_L_9", + "PCIE_NW4A0_6", + "PCIE_TRNFCPH3", + "PCIE_IMUX36_R_6", + "PCIE_LOGIC_OUTS_B17_L_18", + "PCIE_IMUX6_L_14", + "PCIE_EE2A3_8", + "PCIE_LH8_19", + "PCIE_CFGMGMTDO11", + "PCIE_LOGIC_OUTS_B3_R_16", + "PCIE_PIPETX1DATA7", + "PCIE_WW4END2_8", + "PCIE_SW4A2_2", + "PCIE_IMUX8_L_16", + "PCIE_IMUX22_L_19", + "PCIE_BYP3_R_6", + "PCIE_IMUX23_L_5", + "PCIE_LOGIC_OUTS_B0_L_0", + "PCIE_XILUNCONNOUT16", + "PCIE_NW2A1_17", + "PCIE_TRNTD102", + "PCIE_BYP2_R_12", + "PCIE_ER1BEG1_12", + "PCIE_EE2BEG2_9", + "PCIE_LOGIC_OUTS_B19_L_8", + "PCIE_PIPERX4CHANISALIGNED", + "PCIE_DBGVECB44", + "PCIE_IMUX30_L_0", + "PCIE_WL1END0_9", + "PCIE_LOGIC_OUTS_B16_R_15", + "PCIE_EE4A1_11", + "PCIE_PLPHYLNKUPN", + "PCIE_DBGVECA24", + "PCIE_EE4C3_11", + "PCIE_EE4C3_8", + "PCIE_SW4END0_6", + "PCIE_LOGIC_OUTS_B17_R_13", + "PCIE_IMUX7_L_14", + "PCIE_SE4BEG2_9", + "PCIE_WW2A3_6", + "PCIE_IMUX27_R_18", + "PCIE_FAN2_L_8", + "PCIE_MIMRXWDATA32", + "PCIE_BYP7_L_4", + "PCIE_LOGIC_OUTS_B3_R_12", + "PCIE_SE4C0_16", + "PCIE_BLOCK_OUTS_B3_R_9", + "PCIE_IMUX27_R_11", + "PCIE_CFGMGMTDO24", + "PCIE_BYP3_R_9", + "PCIE_PIPERX5DATA2", + "PCIE_IMUX46_R_13", + "PCIE_CFGMGMTDO17", + "PCIE_WW4C0_10", + "PCIE_IMUX13_R_5", + "PCIE_IMUX12_R_15", + "PCIE_IMUX39_L_2", + "PCIE_SE2A3_19", + "PCIE_EE4C2_1", + "PCIE_WW4A2_15", + "PCIE_LH1_3", + "PCIE_SW4END1_6", + "PCIE_BYP1_L_3", + "PCIE_TRNFCPD3", + "PCIE_NE4BEG0_13", + "PCIE_IMUX0_R_9", + "PCIE_IMUX38_L_13", + "PCIE_WL1END0_0", + "PCIE_IMUX8_L_6", + "PCIE_WW2END1_16", + "PCIE_PIPERX6DATA5", + "PCIE_WW4A1_7", + "PCIE_SE2A3_13", + "PCIE_WW4END0_0", + "PCIE_MIMTXWDATA42", + "PCIE_FAN7_R_8", + "PCIE_LOGIC_OUTS_B10_R_5", + "PCIE_FAN7_R_1", + "PCIE_WR1END1_8", + "PCIE_WL1END3_8", + "PCIE_LOGIC_OUTS_B0_L_11", + "PCIE_LH5_11", + "PCIE_EE4BEG1_2", + "PCIE_IMUX6_L_16", + "PCIE_WR1END1_12", + "PCIE_BLOCK_OUTS_B3_R_10", + "PCIE_LOGIC_OUTS_B3_R_17", + "PCIE_WW4END2_18", + "PCIE_IMUX17_R_12", + "PCIE_LOGIC_OUTS_B7_R_0", + "PCIE_PIPERX3CHARISK1", + "PCIE_DBGVECC5", + "PCIE_XILUNCONNOUT22", + "PCIE_WW4A0_12", + "PCIE_LOGIC_OUTS_B8_L_19", + "PCIE_CFGDEVCONTROLURERRREPORTINGEN", + "PCIE_LOGIC_OUTS_B16_R_19", + "PCIE_MIMTXRDATA38", + "PCIE_LH2_14", + "PCIE_LOGIC_OUTS_B9_R_18", + "PCIE_NE4C2_17", + "PCIE_CFGBRIDGESERREN", + "PCIE_BYP1_L_6", + "PCIE_CFGPMFORCESTATE0", + "PCIE_IMUX29_L_8", + "PCIE_LOGIC_OUTS_B8_R_0", + "PCIE_IMUX11_R_3", + "PCIE_IMUX32_R_18", + "PCIE_LOGIC_OUTS_B13_R_0", + "PCIE_EE4A3_0", + "PCIE_IMUX42_L_12", + "PCIE_ER1BEG3_14", + "PCIE_CFGERRAERHEADERLOG92", + "PCIE_SW2A1_17", + "PCIE_CFGERRCPLUNEXPECTN", + "PCIE_LOGIC_OUTS_B5_L_10", + "PCIE_TRNFCCPLD0", + "PCIE_PLDIRECTEDLINKWIDTH1", + "PCIE_BLOCK_OUTS_B3_L_11", + "PCIE_MIMRXRDATA26", + "PCIE_SW4END0_16", + "PCIE_IMUX7_R_14", + "PCIE_NE4C2_15", + "PCIE_LOGIC_OUTS_B2_L_0", + "PCIE_IMUX8_R_0", + "PCIE_IMUX5_R_12", + "PCIE_IMUX20_L_15", + "PCIE_LOGIC_OUTS_B8_R_13", + "PCIE_IMUX43_L_12", + "PCIE_TRNRD24", + "PCIE_IMUX29_L_18", + "PCIE_IMUX20_L_5", + "PCIE_PIPETX7DATA8", + "PCIE_PLLINKPARTNERGEN2SUPPORTED", + "PCIE_LH10_11", + "PCIE_BYP3_R_0", + "PCIE_IMUX16_L_18", + "PCIE_IMUX4_L_13", + "PCIE_IMUX22_L_1", + "PCIE_IMUX5_R_17", + "PCIE_CFGTRNPENDINGN", + "PCIE_CFGERRAERHEADERLOG93", + "PCIE_WW4B2_16", + "PCIE_LOGIC_OUTS_B4_L_5", + "PCIE_LOGIC_OUTS_B0_L_19", + "PCIE_BYP1_R_1", + "PCIE_PIPERX5CHANISALIGNED", + "PCIE_PIPERX5VALID", + "PCIE_PIPERX0STATUS1", + "PCIE_LOGIC_OUTS_B7_R_14", + "PCIE_BYP2_L_5", + "PCIE_MIMTXRDATA19", + "PCIE_IMUX8_L_1", + "PCIE_CFGMGMTRDWRDONEN", + "PCIE_FAN1_L_6", + "PCIE_LL2LINKSTATUS2", + "PCIE_MIMRXWDATA2", + "PCIE_DBGVECA52", + "PCIE_CFGSUBSYSID8", + "PCIE_WW4C3_19", + "PCIE_TRNRD108", + "PCIE_MONITOR_N_11", + "PCIE_IMUX46_R_4", + "PCIE_LH8_16", + "PCIE_LOGIC_OUTS_B3_R_18", + "PCIE_CFGERRTLPCPLHEADER1", + "PCIE_IMUX1_R_10", + "PCIE_SW2A1_16", + "PCIE_PIPETX3CHARISK0", + "PCIE_WW4C0_8", + "PCIE_LOGIC_OUTS_B5_R_1", + "PCIE_BYP3_L_10", + "PCIE_TL2ERRHDR5", + "PCIE_TRNTDLLPDATA2", + "PCIE_TRNRD121", + "PCIE_MIMRXWDATA45", + "PCIE_NW4END3_17", + "PCIE_IMUX26_L_8", + "PCIE_PIPERX5DATA14", + "PCIE_FAN4_L_3", + "PCIE_IMUX1_L_0", + "PCIE_LOGIC_OUTS_B21_L_12", + "PCIE_BLOCK_OUTS_B2_R_16", + "PCIE_EE4A2_4", + "PCIE_FAN6_R_11", + "PCIE_ER1BEG2_10", + "PCIE_NW4END1_4", + "PCIE_IMUX32_L_15", + "PCIE_BLOCK_OUTS_B1_L_7", + "PCIE_TRNRD105", + "PCIE_IMUX28_R_16", + "PCIE_LOGIC_OUTS_B1_L_19", + "PCIE_WW4C0_0", + "PCIE_IMUX24_R_6", + "PCIE_CFGDEVID9", + "PCIE_WW4B1_3", + "PCIE_BLOCK_OUTS_B2_L_7", + "PCIE_LOGIC_OUTS_B19_L_5", + "PCIE_TRNRD39", + "PCIE_IMUX10_R_19", + "PCIE_WL1END2_7", + "PCIE_LOGIC_OUTS_B15_R_9", + "PCIE_IMUX3_R_13", + "PCIE_IMUX15_R_10", + "PCIE_EE2BEG3_4", + "PCIE_IMUX10_R_2", + "PCIE_IMUX44_R_2", + "PCIE_EE4BEG1_7", + "PCIE_NE2A1_18", + "PCIE_TRNRDLLPDATA9", + "PCIE_MIMTXWDATA13", + "PCIE_NE4BEG1_15", + "PCIE_MONITOR_N_1", + "PCIE_IMUX27_R_16", + "PCIE_BYP1_L_9", + "PCIE_IMUX1_L_17", + "PCIE_IMUX33_R_0", + "PCIE_LOGIC_OUTS_B4_R_11", + "PCIE_IMUX13_R_7", + "PCIE_SW4END2_17", + "PCIE_NE2A3_5", + "PCIE_LOGIC_OUTS_B10_R_16", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", + "PCIE_IMUX6_R_16", + "PCIE_LOGIC_OUTS_B16_L_0", + "PCIE_ER1BEG0_7", + "PCIE_PIPETX4DATA13", + "PCIE_LH8_15", + "PCIE_MIMTXRADDR12", + "PCIE_WW4B2_18", + "PCIE_IMUX0_L_0", + "PCIE_IMUX17_L_2", + "PCIE_PIPETX2DATA13", + "PCIE_IMUX8_L_14", + "PCIE_CLK1_R_17", + "PCIE_EE4C2_11", + "PCIE_IMUX42_L_10", + "PCIE_WW2A2_17", + "PCIE_NW2A3_6", + "PCIE_FAN5_L_5", + "PCIE_BYP2_R_4", + "PCIE_FAN4_R_4", + "PCIE_MIMRXWADDR1", + "PCIE_IMUX47_R_5", + "PCIE_FAN2_R_19", + "PCIE_EE2BEG3_6", + "PCIE_WR1END2_6", + "PCIE_MIMTXWDATA68", + "PCIE_IMUX40_R_2", + "PCIE_MONITOR_P_13", + "PCIE_EE2A0_9", + "PCIE_SW2A0_8", + "PCIE_LOGIC_OUTS_B19_L_9", + "PCIE_FAN1_L_11", + "PCIE_IMUX34_R_15", + "PCIE_PIPETX7DATA2", + "PCIE_MIMTXREN", + "PCIE_SW4END2_18", + "PCIE_EDTSINGLEBYPASSCHAIN", + "PCIE_IMUX23_R_15", + "PCIE_CFGMGMTBYTEENN2", + "PCIE_MONITOR_P_12", + "PCIE_EE2A2_3", + "PCIE_XILUNCONNOUT28", + "PCIE_IMUX20_L_12", + "PCIE_IMUX14_L_14", + "PCIE_IMUX18_R_9", + "PCIE_IMUX7_R_9", + "PCIE_SE2A1_12", + "PCIE_LOGIC_OUTS_B15_R_15", + "PCIE_DBGSCLRJ", + "PCIE_IMUX42_R_16", + "PCIE_LH1_6", + "PCIE_SW2A2_7", + "PCIE_WW4B3_0", + "PCIE_LOGIC_OUTS_B21_L_14", + "PCIE_WW4END3_11", + "PCIE_IMUX34_L_1", + "PCIE_MIMRXRDATA49", + "PCIE_IMUX14_R_19", + "PCIE_WW4A2_14", + "PCIE_FAN7_L_14", + "PCIE_IMUX47_L_14", + "PCIE_XILUNCONNOUT24", + "PCIE_MIMRXRDATA66", + "PCIE_SE2A3_17", + "PCIE_EE4A3_10", + "PCIE_WW2END3_13", + "PCIE_BYP7_R_5", + "PCIE_PLDBGMODE2", + "PCIE_IMUX6_L_6", + "PCIE_IMUX0_L_9", + "PCIE_NE2A2_19", + "PCIE_TRNRDLLPDATA16", + "PCIE_WW2END3_9", + "PCIE_SW4A2_0", + "PCIE_LOGIC_OUTS_B5_L_18", + "PCIE_XILUNCONNOUT33", + "PCIE_FAN0_R_6", + "PCIE_TRNRD79", + "PCIE_BYP3_L_3", + "PCIE_LOGIC_OUTS_B23_R_2", + "PCIE_MIMRXRADDR12", + "PCIE_IMUX11_L_9", + "PCIE_CFGERRAERHEADERLOG75", + "PCIE_IMUX22_R_11", + "PCIE_IMUX29_R_19", + "PCIE_LOGIC_OUTS_B11_R_1", + "PCIE_PIPERX6DATA11", + "PCIE_WW4END1_6", + "PCIE_WR1END3_17", + "PCIE_SE2A0_9", + "PCIE_IMUX11_L_14", + "PCIE_EDTCHANNELSIN7", + "PCIE_IMUX43_L_15", + "PCIE_CFGDSN62", + "PCIE_NW2A1_8", + "PCIE_LH12_5", + "PCIE_XILUNCONNOUT9", + "PCIE_LOGIC_OUTS_B1_L_9", + "PCIE_CFGERRTLPCPLHEADER8", + "PCIE_SE4C1_3", + "PCIE_DBGVECC0", + "PCIE_SW2A2_8", + "PCIE_NE4BEG0_12", + "PCIE_FAN6_L_5", + "PCIE_BYP3_R_2", + "PCIE_LOGIC_OUTS_B8_L_2", + "PCIE_IMUX5_L_7", + "PCIE_EL1BEG2_14", + "PCIE_IMUX12_R_0", + "PCIE_LOGIC_OUTS_B15_L_9", + "PCIE_WW2END2_19", + "PCIE_TRNRD30", + "PCIE_TRNRDLLPDATA4", + "PCIE_BLOCK_OUTS_B0_R_13", + "PCIE_PIPERX6ELECIDLE", + "PCIE_LOGIC_OUTS_B7_R_13", + "PCIE_TRNRD61", + "PCIE_IMUX38_R_3", + "PCIE_IMUX28_L_7", + "PCIE_WW2A0_3", + "PCIE_EE4A2_10", + "PCIE_PIPETX3DATA5", + "PCIE_CFGDSN52", + "PCIE_NW4END2_16", + "PCIE_CFGMGMTDO14", + "PCIE_WR1END3_2", + "PCIE_EL1BEG1_5", + "PCIE_DBGVECB51", + "PCIE_IMUX12_R_14", + "PCIE_SW2A2_10", + "PCIE_PIPERX7STATUS2", + "PCIE_NW4END1_17", + "PCIE_WW4B2_4", + "PCIE_FAN3_R_6", + "PCIE_IMUX47_R_15", + "PCIE_LH2_7", + "PCIE_IMUX46_L_11", + "PCIE_FAN4_R_13", + "PCIE_IMUX47_R_4", + "PCIE_IMUX31_R_15", + "PCIE_SCANMODEN", + "PCIE_WW4B3_7", + "PCIE_CFGSUBSYSID1", + "PCIE_IMUX11_R_17", + "PCIE_LOGIC_OUTS_B4_R_1", + "PCIE_TRNTDLLPDATA22", + "PCIE_NE4BEG3_6", + "PCIE_NW4END0_1", + "PCIE_WL1END0_18", + "PCIE_LOGIC_OUTS_B23_R_12", + "PCIE_PLDIRECTEDLTSSMNEW4", + "PCIE_SE4BEG3_19", + "PCIE_PIPETX2POWERDOWN0", + "PCIE_NE4C0_15", + "PCIE_FAN1_R_2", + "PCIE_NW4END3_15", + "PCIE_NW4END0_11", + "PCIE_FAN0_R_16", + "PCIE_WW4C2_3", + "PCIE_LOGIC_OUTS_B4_L_19", + "PCIE_TRNRDLLPDATA43", + "PCIE_LOGIC_OUTS_B17_L_0", + "PCIE_IMUX13_R_13", + "PCIE_FAN6_R_13", + "PCIE_CFGMGMTDO29", + "PCIE_TRNRDLLPDATA47", + "PCIE_CFGLINKCONTROLRCB", + "PCIE_LOGIC_OUTS_B11_L_0", + "PCIE_DBGVECB43", + "PCIE_LOGIC_OUTS_B9_R_2", + "PCIE_IMUX6_R_7", + "PCIE_EE4BEG2_13", + "PCIE_WR1END1_19", + "PCIE_LOGIC_OUTS_B17_R_17", + "PCIE_CFGMSGDATA2", + "PCIE_LOGIC_OUTS_B1_L_8", + "PCIE_NW4A1_15", + "PCIE_WR1END1_15", + "PCIE_FAN3_L_15", + "PCIE_LOGIC_OUTS_B2_L_15", + "PCIE_CFGPMRCVREQACKN", + "PCIE_TRNTD54", + "PCIE_LOGIC_OUTS_B0_R_18", + "PCIE_WW2END3_4", + "PCIE_LOGIC_OUTS_B12_R_18", + "PCIE_LOGIC_OUTS_B13_L_16", + "PCIE_IMUX42_R_6", + "PCIE_LOGIC_OUTS_B10_R_1", + "PCIE_EL1BEG2_10", + "PCIE_LOGIC_OUTS_B13_R_12", + "PCIE_IMUX12_L_12", + "PCIE_SE4C0_10", + "PCIE_FAN0_R_0", + "PCIE_EE4A0_3", + "PCIE_LOGIC_OUTS_B10_R_6", + "PCIE_IMUX4_R_17", + "PCIE_IMUX2_L_5", + "PCIE_FAN1_L_12", + "PCIE_IMUX28_L_6", + "PCIE_CFGMSGRECEIVEDPMASNAK", + "PCIE_IMUX8_R_18", + "PCIE_SE4BEG0_2", + "PCIE_IMUX41_R_17", + "PCIE_IMUX44_L_17", + "PCIE_IMUX29_R_10", + "PCIE_MONITOR_P_11", + "PCIE_IMUX13_L_13", + "PCIE_BYP0_R_7", + "PCIE_BLOCK_OUTS_B1_L_19", + "PCIE_CTRL1_L_0", + "PCIE_IMUX31_L_3", + "PCIE_MIMTXRDATA23", + "PCIE_WR1END3_6", + "PCIE_LOGIC_OUTS_B0_R_4", + "PCIE_IMUX34_R_8", + "PCIE_CFGERRAERHEADERLOG17", + "PCIE_CFGERRAERHEADERLOG115", + "PCIE_CFGERRAERHEADERLOG119", + "PCIE_PLLTSSMSTATE4", + "PCIE_DBGVECA48", + "PCIE_PIPERX4DATA6", + "PCIE_MIMRXWDATA65", + "PCIE_EE4A3_2", + "PCIE_NW4A3_3", + "PCIE_FAN1_R_6", + "PCIE_DBGVECA59", + "PCIE_LH7_9", + "PCIE_PIPETX7DATA13", + "PCIE_IMUX20_L_1", + "PCIE_IMUX27_L_2", + "PCIE_IMUX4_R_9", + "PCIE_CFGERRAERHEADERLOG127", + "PCIE_IMUX24_L_14", + "PCIE_LOGIC_OUTS_B18_R_17", + "PCIE_DBGVECB55", + "PCIE_BYP7_R_17", + "PCIE_SW4END3_2", + "PCIE_CFGMSGDATA0", + "PCIE_CFGERRAERHEADERLOGSETN", + "PCIE_TRNTDSTRDY3", + "PCIE_CFGMGMTDI3", + "PCIE_FAN0_R_8", + "PCIE_IMUX12_L_18", + "PCIE_IMUX2_L_17", + "PCIE_EE2A0_4", + "PCIE_PIPETX4DATA2", + "PCIE_IMUX0_R_13", + "PCIE_EE4C0_16", + "PCIE_MIMTXRDATA37", + "PCIE_LOGIC_OUTS_B16_L_17", + "PCIE_TRNLNKUP", + "PCIE_WW2END3_18", + "PCIE_WR1END2_8", + "PCIE_LH3_14", + "PCIE_LOGIC_OUTS_B3_R_4", + "PCIE_IMUX1_L_4", + "PCIE_TRNRD126", + "PCIE_CFGERRAERHEADERLOG20", + "PCIE_SW2A1_8", + "PCIE_TL2ERRHDR1", + "PCIE_LH7_2", + "PCIE_NW4END0_10", + "PCIE_BYP4_R_9", + "PCIE_BLOCK_OUTS_B0_L_13", + "PCIE_WW4END3_6", + "PCIE_IMUX20_R_16", + "PCIE_BYP0_L_10", + "PCIE_EE4BEG2_10", + "PCIE_MONITOR_N_7", + "PCIE_IMUX3_L_2", + "PCIE_LOGIC_OUTS_B21_L_17", + "PCIE_BYP7_R_1", + "PCIE_IMUX2_L_4", + "PCIE_MONITOR_N_15", + "PCIE_LL2SUSPENDOK", + "PCIE_LOGIC_OUTS_B15_R_19", + "PCIE_IMUX4_R_8", + "PCIE_IMUX43_R_19", + "PCIE_LOGIC_OUTS_B4_R_0", + "PCIE_IMUX15_L_14", + "PCIE_IMUX4_L_19", + "PCIE_CFGERRAERHEADERLOG67", + "PCIE_EE4B3_3", + "PCIE_BLOCK_OUTS_B1_L_2", + "PCIE_IMUX45_R_11", + "PCIE_PIPERX6DATA9", + "PCIE_CFGMGMTBYTEENN1", + "PCIE_MIMTXRDATA20", + "PCIE_TL2ERRHDR4", + "PCIE_SE4C1_19", + "PCIE_EE2A1_10", + "PCIE_SW2A0_3", + "PCIE_IMUX27_L_3", + "PCIE_IMUX8_L_10", + "PCIE_IMUX42_R_3", + "PCIE_SW2A0_18", + "PCIE_EL1BEG3_15", + "PCIE_FAN7_L_0", + "PCIE_NE2A1_7", + "PCIE_SW4A3_16", + "PCIE_LH1_0", + "PCIE_LOGIC_OUTS_B2_R_3", + "PCIE_TRNRD17", + "PCIE_LOGIC_OUTS_B12_L_1", + "PCIE_IMUX0_R_8", + "PCIE_CFGCOMMANDMEMENABLE", + "PCIE_SW4END1_18", + "PCIE_MIMRXRDATA7", + "PCIE_IMUX8_R_2", + "PCIE_FAN5_R_10", + "PCIE_LOGIC_OUTS_B10_R_8", + "PCIE_PIPETX5POWERDOWN0", + "PCIE_IMUX5_L_0", + "PCIE_EE4C3_16", + "PCIE_IMUX28_L_0", + "PCIE_LOGIC_OUTS_B6_R_15", + "PCIE_LOGIC_OUTS_B15_L_17", + "PCIE_CFGPMHALTASPML1N", + "PCIE_TRNTD61", + "PCIE_EE4B2_9", + "PCIE_LOGIC_OUTS_B14_L_16", + "PCIE_PIPERX4DATA15", + "PCIE_BLOCK_OUTS_B2_L_10", + "PCIE_IMUX40_R_9", + "PCIE_EL1BEG3_8", + "PCIE_LOGIC_OUTS_B20_R_17", + "PCIE_WW4A2_7", + "PCIE_LOGIC_OUTS_B9_R_1", + "PCIE_LH5_10", + "PCIE_PIPERX2POLARITY", + "PCIE_IMUX7_L_19", + "PCIE_LOGIC_OUTS_B4_L_11", + "PCIE_WR1END0_2", + "PCIE_BYP4_R_17", + "PCIE_BYP2_L_0", + "PCIE_CFGTRANSACTIONADDR2", + "PCIE_EE2A3_9", + "PCIE_LOGIC_OUTS_B8_L_7", + "PCIE_TRNTD46", + "PCIE_LOGIC_OUTS_B20_R_13", + "PCIE_IMUX3_R_6", + "PCIE_EE4B0_3", + "PCIE_DBGVECC1", + "PCIE_LOGIC_OUTS_B4_R_12", + "PCIE_BYP1_L_15", + "PCIE_LOGIC_OUTS_B3_R_14", + "PCIE_LOGIC_OUTS_B14_R_16", + "PCIE_IMUX47_R_13", + "PCIE_LOGIC_OUTS_B11_L_2", + "PCIE_IMUX37_L_6", + "PCIE_IMUX36_R_19", + "PCIE_IMUX31_L_9", + "PCIE_LOGIC_OUTS_B14_L_3", + "PCIE_TRNRD48", + "PCIE_IMUX7_R_11", + "PCIE_PIPERX1DATA11", + "PCIE_IMUX19_R_1", + "PCIE_NW4END3_14", + "PCIE_MIMTXWDATA8", + "PCIE_TRNTD39", + "PCIE_FAN5_R_19", + "PCIE_IMUX26_R_10", + "PCIE_PIPERX2STATUS1", + "PCIE_IMUX27_R_6", + "PCIE_IMUX7_L_1", + "PCIE_CFGDSBUSNUMBER6", + "PCIE_CFGERRAERHEADERLOG59", + "PCIE_IMUX19_R_13", + "PCIE_CFGMSGRECEIVEDERRNONFATAL", + "PCIE_MIMTXWDATA0", + "PCIE_LH12_16", + "PCIE_TRNRDLLPDATA11", + "PCIE_SE4BEG2_12", + "PCIE_SE2A2_17", + "PCIE_NW4END3_11", + "PCIE_EE4A2_15", + "PCIE_DBGSUBMODE", + "PCIE_PIPETX5DATA9", + "PCIE_CTRL1_L_19", + "PCIE_LH1_9", + "PCIE_LL2TXIDLE", + "PCIE_NE4BEG2_9", + "PCIE_LOGIC_OUTS_B5_L_7", + "PCIE_PIPETX6DATA10", + "PCIE_IMUX43_L_13", + "PCIE_BYP3_L_7", + "PCIE_NE4C1_16", + "PCIE_SE2A0_3", + "PCIE_LOGIC_OUTS_B3_L_0", + "PCIE_WW4B2_7", + "PCIE_BYP6_R_8", + "PCIE_BYP5_R_4", + "PCIE_CFGMGMTDO0", + "PCIE_TL2ERRHDR23", + "PCIE_BYP5_R_12", + "PCIE_BYP6_L_8", + "PCIE_LH3_1", + "PCIE_FAN4_R_11", + "PCIE_IMUX8_L_8", + "PCIE_LH4_10", + "PCIE_ER1BEG0_5", + "PCIE_WW4C2_0", + "PCIE_IMUX0_R_4", + "PCIE_CLK0_L_12", + "PCIE_LH12_18", + "PCIE_IMUX21_L_8", + "PCIE_EE4A1_7", + "PCIE_TRNTDLLPDATA30", + "PCIE_EE4C0_19", + "PCIE_TRNTD85", + "PCIE_CTRL1_L_12", + "PCIE_LOGIC_OUTS_B7_L_10", + "PCIE_PIPERX5DATA10", + "PCIE_NW4A1_19", + "PCIE_BYP1_L_7", + "PCIE_IMUX29_R_18", + "PCIE_TRNTD127", + "PCIE_LOGIC_OUTS_B19_L_2", + "PCIE_CFGERRAERHEADERLOG29", + "PCIE_NE2A2_1", + "PCIE_LOGIC_OUTS_B23_L_8", + "PCIE_IMUX11_L_17", + "PCIE_LH7_14", + "PCIE_DBGVECA7", + "PCIE_PLDBGVEC8", + "PCIE_TRNFCCPLD2", + "PCIE_LH9_12", + "PCIE_NE4C0_0", + "PCIE_IMUX3_R_19", + "PCIE_EDTCHANNELSIN6", + "PCIE_IMUX15_L_3", + "PCIE_WW2A0_14", + "PCIE_TRNTD81", + "PCIE_LOGIC_OUTS_B22_R_1", + "PCIE_DBGVECB6", + "PCIE_CFGVENDID0", + "PCIE_TRNRDLLPDATA38", + "PCIE_IMUX10_R_11", + "PCIE_IMUX23_L_10", + "PCIE_IMUX42_L_9", + "PCIE_DBGVECA51", + "PCIE_NE4C3_1", + "PCIE_TRNTD93", + "PCIE_LOGIC_OUTS_B15_R_0", + "PCIE_IMUX10_L_11", + "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", + "PCIE_IMUX4_L_11", + "PCIE_TRNRD0", + "PCIE_BYP2_L_13", + "PCIE_IMUX44_R_8", + "PCIE_DRPDO3", + "PCIE_XILUNCONNOUT18", + "PCIE_BYP5_L_8", + "PCIE_EE4BEG2_11", + "PCIE_IMUX26_R_13", + "PCIE_WW4B0_7", + "PCIE_CFGERRAERHEADERLOG48", + "PCIE_LL2SUSPENDNOW", + "PCIE_EL1BEG2_2", + "PCIE_LH2_0", + "PCIE_IMUX16_L_13", + "PCIE_WR1END0_15", + "PCIE_WW4B1_6", + "PCIE_EE4A3_15", + "PCIE_FAN5_L_2", + "PCIE_LH2_2", + "PCIE_BYP6_L_0", + "PCIE_EE4B2_16", + "PCIE_WW4END1_12", + "PCIE_LOGIC_OUTS_B13_R_10", + "PCIE_IMUX30_L_13", + "PCIE_NW4END2_5", + "PCIE_IMUX3_L_5", + "PCIE_FAN5_R_12", + "PCIE_MONITOR_P_14", + "PCIE_IMUX19_L_9", + "PCIE_IMUX44_L_2", + "PCIE_MONITOR_P_0", + "PCIE_IMUX35_L_10", + "PCIE_LOGIC_OUTS_B1_R_19", + "PCIE_TRNFCPD8", + "PCIE_PLDIRECTEDCHANGEDONE", + "PCIE_NE2A2_2", + "PCIE_IMUX47_L_7", + "PCIE_WW2END0_7", + "PCIE_SE4C3_10", + "PCIE_LOGIC_OUTS_B21_R_16", + "PCIE_CFGERRTLPCPLHEADER27", + "PCIE_WW4END3_15", + "PCIE_SW4END2_3", + "PCIE_IMUX32_R_13", + "PCIE_CFGERRCPLRDYN", + "PCIE_IMUX44_R_13", + "PCIE_WW2A2_15", + "PCIE_FAN4_L_7", + "PCIE_IMUX38_L_6", + "PCIE_LOGIC_OUTS_B2_L_1", + "PCIE_MIMTXWDATA1", + "PCIE_FAN3_L_18", + "PCIE_CFGPCIELINKSTATE0", + "PCIE_SE4C1_15", + "PCIE_IMUX19_R_3", + "PCIE_LOGIC_OUTS_B21_R_6", + "PCIE_NE4BEG3_15", + "PCIE_DBGVECB0", + "PCIE_LOGIC_OUTS_B8_L_0", + "PCIE_FAN0_L_6", + "PCIE_PIPETX1DATA3", + "PCIE_NW4A1_17", + "PCIE_IMUX27_L_14", + "PCIE_CTRL1_R_0", + "PCIE_IMUX28_R_14", + "PCIE_BLOCK_OUTS_B1_R_13", + "PCIE_IMUX25_L_5", + "PCIE_IMUX11_L_18", + "PCIE_CFGERRTLPCPLHEADER17", + "PCIE_LOGIC_OUTS_B4_R_17", + "PCIE_MIMTXRDATA14", + "PCIE_MIMTXRADDR2", + "PCIE_WW4A3_4", + "PCIE_WW4C0_1", + "PCIE_IMUX21_R_0", + "PCIE_IMUX1_R_12", + "PCIE_SE4C3_19", + "PCIE_PIPETX7DATA11", + "PCIE_WW4C0_18", + "PCIE_TRNTD79", + "PCIE_FAN3_L_13", + "PCIE_IMUX18_L_4", + "PCIE_LOGIC_OUTS_B11_R_13", + "PCIE_IMUX25_L_12", + "PCIE_FAN7_R_3", + "PCIE_TRNTD118", + "PCIE_NW2A0_1", + "PCIE_LOGIC_OUTS_B11_R_19", + "PCIE_IMUX29_L_11", + "PCIE_LOGIC_OUTS_B0_R_3", + "PCIE_IMUX11_L_6", + "PCIE_EE2BEG2_10", + "PCIE_CFGPMCSRPMESTATUS", + "PCIE_TRNTD90", + "PCIE_TL2PPMSUSPENDREQ", + "PCIE_BYP6_L_9", + "PCIE_IMUX27_R_0", + "PCIE_IMUX41_L_0", + "PCIE_TRNTD103", + "PCIE_IMUX38_R_0", + "PCIE_CFGERRAERHEADERLOG90", + "PCIE_TRNFCCPLH6", + "PCIE_SE2A3_16", + "PCIE_BYP1_R_9", + "PCIE_SW4END3_4", + "PCIE_BLOCK_OUTS_B1_R_2", + "PCIE_IMUX3_L_9", + "PCIE_IMUX46_R_3", + "PCIE_IMUX25_L_19", + "PCIE_PLSELLNKRATE", + "PCIE_TRNRDLLPDATA58", + "PCIE_LOGIC_OUTS_B4_R_18", + "PCIE_FAN2_R_1", + "PCIE_CFGDSN44", + "PCIE_FAN1_L_18", + "PCIE_SE4BEG3_13", + "PCIE_CFGTRANSACTIONADDR3", + "PCIE_NE4BEG0_3", + "PCIE_EE4A2_6", + "PCIE_IMUX46_R_12", + "PCIE_TRNFCNPH5", + "PCIE_IMUX4_L_6", + "PCIE_EE4C1_11", + "PCIE_PIPERX6POLARITY", + "PCIE_FAN3_L_11", + "PCIE_MIMTXRDATA18", + "PCIE_IMUX18_L_16", + "PCIE_WL1END2_17", + "PCIE_TRNTD47", + "PCIE_IMUX18_R_13", + "PCIE_IMUX11_L_3", + "PCIE_NE4BEG1_18", + "PCIE_MIMRXWDATA43", + "PCIE_WL1END0_11", + "PCIE_CFGPORTNUMBER4", + "PCIE_WW4B0_10", + "PCIE_IMUX24_L_6", + "PCIE_NW4END3_12", + "PCIE_LOGIC_OUTS_B21_L_7", + "PCIE_PIPETX3DATA0", + "PCIE_FAN0_R_10", + "PCIE_LOGIC_OUTS_B8_L_6", + "PCIE_TL2ERRHDR13", + "PCIE_IMUX2_R_16", + "PCIE_LOGIC_OUTS_B22_R_6", + "PCIE_IMUX45_L_1", + "PCIE_CFGERRAERHEADERLOG96", + "PCIE_LOGIC_OUTS_B4_R_16", + "PCIE_CFGPORTNUMBER7", + "PCIE_LOGIC_OUTS_B0_R_8", + "PCIE_LOGIC_OUTS_B18_L_17", + "PCIE_LOGIC_OUTS_B15_L_1", + "PCIE_WW4C2_17", + "PCIE_LOGIC_OUTS_B19_L_4", + "PCIE_WR1END0_10", + "PCIE_WL1END1_4", + "PCIE_DBGMODE0", + "PCIE_CFGFORCEMPS1", + "PCIE_FAN1_R_1", + "PCIE_PIPETX1CHARISK1", + "PCIE_CFGDEVCONTROLMAXPAYLOAD0", + "PCIE_TRNTBUFAV5", + "PCIE_LOGIC_OUTS_B4_L_13", + "PCIE_LOGIC_OUTS_B16_R_6", + "PCIE_LOGIC_OUTS_B1_R_17", + "PCIE_MIMTXRDATA17", + "PCIE_WW2END0_2", + "PCIE_MIMRXWDATA47", + "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", + "PCIE_IMUX9_L_0", + "PCIE_SW4A3_13", + "PCIE_EL1BEG0_15", + "PCIE_LH11_11", + "PCIE_BYP0_R_1", + "PCIE_SE4C0_6", + "PCIE_TRNTD74", + "PCIE_SE4BEG2_18", + "PCIE_LOGIC_OUTS_B0_L_13", + "PCIE_IMUX17_L_6", + "PCIE_WW2END2_18", + "PCIE_CFGERRTLPCPLHEADER22", + "PCIE_WW4END1_7", + "PCIE_WL1END3_19", + "PCIE_BLOCK_OUTS_B0_L_11", + "PCIE_CFGERRAERHEADERLOG24", + "PCIE_TRNTD12", + "PCIE_PIPERX5DATA0", + "PCIE_MIMRXRDATA58", + "PCIE_CFGDEVID6", + "PCIE_WW2A0_19", + "PCIE_TL2ERRHDR26", + "PCIE_WW4END3_18", + "PCIE_MIMRXRDATA4", + "PCIE_CFGDSN5", + "PCIE_CFGDSN18", + "PCIE_IMUX42_L_3", + "PCIE_WW2END2_12", + "PCIE_LOGIC_OUTS_B10_R_3", + "PCIE_IMUX14_R_1", + "PCIE_CFGDSN27", + "PCIE_DBGVECA34", + "PCIE_PIPERX5STATUS2", + "PCIE_IMUX29_R_11", + "PCIE_IMUX45_L_8", + "PCIE_FAN7_R_4", + "PCIE_SW4END1_14", + "PCIE_EL1BEG2_17", + "PCIE_IMUX28_R_10", + "PCIE_NW2A2_2", + "PCIE_IMUX28_R_18", + "PCIE_DBGVECA25", + "PCIE_BYP0_R_3", + "PCIE_WL1END3_9", + "PCIE_LH8_0", + "PCIE_IMUX7_L_17", + "PCIE_EE2BEG3_8", + "PCIE_SE4BEG2_11", + "PCIE_DBGSCLRD", + "PCIE_IMUX2_R_11", + "PCIE_IMUX38_R_12", + "PCIE_TL2ERRHDR8", + "PCIE_IMUX9_L_14", + "PCIE_IMUX7_L_18", + "PCIE_MIMRXRDATA29", + "PCIE_IMUX4_L_16", + "PCIE_EE4C2_3", + "PCIE_LOGIC_OUTS_B23_R_6", + "PCIE_MIMRXRDATA53", + "PCIE_TRNTDLLPSRCRDY", + "PCIE_IMUX35_L_19", + "PCIE_NE4BEG3_4", + "PCIE_LOGIC_OUTS_B13_R_15", + "PCIE_IMUX33_L_3", + "PCIE_IMUX25_R_3", + "PCIE_WW4A0_6", + "PCIE_BYP2_L_12", + "PCIE_LOGIC_OUTS_B5_L_12", + "PCIE_PIPERX0POLARITY", + "PCIE_LOGIC_OUTS_B8_R_2", + "PCIE_MIMTXRDATA50", + "PCIE_CFGERRTLPCPLHEADER15", + "PCIE_IMUX42_R_11", + "PCIE_TRNTD7", + "PCIE_MIMRXRDATA67", + "PCIE_PIPERX1DATA9", + "PCIE_CFGMGMTDI2", + "PCIE_IMUX15_R_12", + "PCIE_SW4A0_9", + "PCIE_EE4B2_8", + "PCIE_IMUX35_R_5", + "PCIE_LL2BADTLPERR", + "PCIE_MIMTXRDATA67", + "PCIE_LH2_5", + "PCIE_IMUX43_R_18", + "PCIE_SW2A3_1", + "PCIE_MIMTXRDATA53", + "PCIE_MIMRXRADDR1", + "PCIE_IMUX25_L_18", + "PCIE_SE4C3_1", + "PCIE_FAN4_L_2", + "PCIE_IMUX34_R_12", + "PCIE_IMUX15_R_11", + "PCIE_EE4B2_0", + "PCIE_LOGIC_OUTS_B10_L_15", + "PCIE_IMUX6_L_18", + "PCIE_CFGERRTLPCPLHEADER39", + "PCIE_EE4A1_14", + "PCIE_IMUX5_R_9", + "PCIE_TRNRBARHIT2", + "PCIE_EE4B3_8", + "PCIE_LOGIC_OUTS_B11_L_1", + "PCIE_TRNTD114", + "PCIE_SW2A0_15", + "PCIE_FAN4_R_14", + "PCIE_BYP1_L_8", + "PCIE_EE4BEG3_15", + "PCIE_FAN4_L_17", + "PCIE_IMUX7_L_3", + "PCIE_SE4C3_12", + "PCIE_IMUX17_R_5", + "PCIE_IMUX28_R_13", + "PCIE_IMUX38_L_12", + "PCIE_IMUX47_R_9", + "PCIE_IMUX44_R_12", + "PCIE_PLDIRECTEDLTSSMNEWVLD", + "PCIE_EE2BEG0_18", + "PCIE_MONITOR_P_4", + "PCIE_TRNTD31", + "PCIE_IMUX30_R_5", + "PCIE_XILUNCONNOUT4", + "PCIE_LOGIC_OUTS_B15_R_3", + "PCIE_IMUX23_R_17", + "PCIE_IMUX10_L_3", + "PCIE_CTRL0_L_19", + "PCIE_MIMRXWDATA56", + "PCIE_CFGROOTCONTROLSYSERRCORRERREN", + "PCIE_IMUX43_L_2", + "PCIE_TRNRBARHIT1", + "PCIE_IMUX6_R_14", + "PCIE_BYP6_L_13", + "PCIE_BYP2_L_3", + "PCIE_IMUX20_L_7", + "PCIE_FAN5_L_10", + "PCIE_IMUX1_R_18", + "PCIE_TRNTD115", + "PCIE_SE2A0_4", + "PCIE_TRNRD76", + "PCIE_TRNTDLLPDATA6", + "PCIE_IMUX12_R_7", + "PCIE_CFGDSN41", + "PCIE_LOGIC_OUTS_B17_R_0", + "PCIE_CFGMGMTDO16", + "PCIE_SE4BEG1_0", + "PCIE_SW4END1_10", + "PCIE_TRNRDLLPDATA15", + "PCIE_CLK0_L_16", + "PCIE_LH9_2", + "PCIE_MIMRXRDATA54", + "PCIE_IMUX19_L_6", + "PCIE_IMUX36_R_2", + "PCIE_LOGIC_OUTS_B23_L_17", + "PCIE_IMUX29_L_5", + "PCIE_BYP2_L_4", + "PCIE_LOGIC_OUTS_B5_R_8", + "PCIE_LOGIC_OUTS_B10_R_9", + "PCIE_WW4END2_4", + "PCIE_BYP4_R_15", + "PCIE_NW2A0_18", + "PCIE_NE4C1_14", + "PCIE_MIMRXRDATA41", + "PCIE_IMUX45_L_14", + "PCIE_EL1BEG2_0", + "PCIE_IMUX26_R_2", + "PCIE_CFGINTERRUPTDO2", + "PCIE_BYP5_R_6", + "PCIE_CLK0_R_15", + "PCIE_LOGIC_OUTS_B23_L_19", + "PCIE_LOGIC_OUTS_B15_R_7", + "PCIE_WW4END1_4", + "PCIE_NW4A2_9", + "PCIE_BYP6_L_14", + "PCIE_CFGERRAERHEADERLOG79", + "PCIE_IMUX24_L_18", + "PCIE_IMUX46_L_10", + "PCIE_CFGDSN23", + "PCIE_BYP2_L_2", + "PCIE_SE4C0_17", + "PCIE_SW2A3_9", + "PCIE_IMUX41_L_8", + "PCIE_PIPERX0DATA2", + "PCIE_IMUX31_R_16", + "PCIE_PIPERX5DATA6", + "PCIE_MIMTXWDATA20", + "PCIE_EE4C1_6", + "PCIE_EE4BEG0_14", + "PCIE_LOGIC_OUTS_B7_R_9", + "PCIE_BLOCK_OUTS_B3_L_13", + "PCIE_IMUX31_L_6", + "PCIE_BLOCK_OUTS_B2_L_3", + "PCIE_WW4A3_3", + "PCIE_SE2A2_12", + "PCIE_PIPETX0DATA4", + "PCIE_EL1BEG2_19", + "PCIE_CLK1_L_18", + "PCIE_MIMRXWDATA24", + "PCIE_IMUX46_R_19", + "PCIE_NE2A2_6", + "PCIE_BYP5_R_18", + "PCIE_SW4END3_9", + "PCIE_EL1BEG3_2", + "PCIE_WW4A0_1", + "PCIE_IMUX23_R_8", + "PCIE_MONITOR_P_6", + "PCIE_EE2A2_14", + "PCIE_EE2BEG2_11", + "PCIE_WL1END2_5", + "PCIE_LH12_14", + "PCIE_IMUX16_L_19", + "PCIE_SW4END3_6", + "PCIE_BYP1_L_11", + "PCIE_WW4A2_12", + "PCIE_NW4A0_18", + "PCIE_IMUX34_R_2", + "PCIE_LOGIC_OUTS_B4_L_12", + "PCIE_SW2A2_11", + "PCIE_WW4A0_2", + "PCIE_PIPETX1DATA6", + "PCIE_IMUX36_L_8", + "PCIE_FAN7_R_2", + "PCIE_WW2A3_17", + "PCIE_WW4END1_16", + "PCIE_NW2A3_1", + "PCIE_IMUX22_R_2", + "PCIE_BLOCK_OUTS_B1_R_17", + "PCIE_BYP1_L_14", + "PCIE_TRNTD88", + "PCIE_LOGIC_OUTS_B8_L_18", + "PCIE_WW2A0_1", + "PCIE_PIPERX3DATA2", + "PCIE_NE2A0_14", + "PCIE_NE2A2_14", + "PCIE_CFGERRAERHEADERLOG8", + "PCIE_EE2A0_1", + "PCIE_IMUX33_R_10", + "PCIE_DBGVECA43", + "PCIE_LOGIC_OUTS_B6_L_8", + "PCIE_TL2ERRFCPE", + "PCIE_IMUX28_R_1", + "PCIE_LOGIC_OUTS_B11_R_0", + "PCIE_WW4B3_13", + "PCIE_TRNTD100", + "PCIE_IMUX46_R_14", + "PCIE_WW4A1_12", + "PCIE_WR1END2_1", + "PCIE_WW4END2_15", + "PCIE_TRNRDLLPDATA30", + "PCIE_SW4A3_12", + "PCIE_EE2A1_0", + "PCIE_DRPDO5", + "PCIE_FAN2_L_7", + "PCIE_CFGPMHALTASPML0SN", + "PCIE_IMUX39_R_15", + "PCIE_SW4A3_6", + "PCIE_IMUX26_L_4", + "PCIE_EE4C1_19", + "PCIE_LOGIC_OUTS_B21_L_3", + "PCIE_WW2END3_6", + "PCIE_CFGERRAERHEADERLOG33", + "PCIE_CTRL1_R_12", + "PCIE_TRNTD9", + "PCIE_PIPETX3DATA2", + "PCIE_TRNTDLLPDATA23", + "PCIE_EE4BEG2_6", + "PCIE_NE4C1_0", + "PCIE_MIMRXWDATA18", + "PCIE_EE2BEG0_6", + "PCIE_TRNRD31", + "PCIE_CTRL1_R_8", + "PCIE_CFGERRAERHEADERLOG98", + "PCIE_LOGIC_OUTS_B19_L_11", + "PCIE_SE4C1_2", + "PCIE_EDTBYPASS", + "PCIE_TRNRD15", + "PCIE_IMUX43_L_0", + "PCIE_LH10_4", + "PCIE_IMUX24_L_3", + "PCIE_IMUX37_L_4", + "PCIE_IMUX25_R_0", + "PCIE_NW4A2_19", + "PCIE_LH6_16", + "PCIE_PIPETX6POWERDOWN1", + "PCIE_IMUX25_R_13", + "PCIE_TRNTD89", + "PCIE_LOGIC_OUTS_B3_L_5", + "PCIE_IMUX33_R_9", + "PCIE_WW2END3_19", + "PCIE_NW2A3_2", + "PCIE_CLK0_R_6", + "PCIE_BYP1_R_10", + "PCIE_IMUX18_L_1", + "PCIE_LOGIC_OUTS_B12_L_9", + "PCIE_LOGIC_OUTS_B18_L_2", + "PCIE_PLDBGVEC9", + "PCIE_WW4A1_11", + "PCIE_IMUX39_L_15", + "PCIE_LOGIC_OUTS_B4_L_18", + "PCIE_IMUX38_R_13", + "PCIE_IMUX16_L_0", + "PCIE_ER1BEG1_0", + "PCIE_LH11_14", + "PCIE_CFGREVID7", + "PCIE_LH2_16", + "PCIE_MIMTXRDATA1", + "PCIE_LOGIC_OUTS_B17_L_6", + "PCIE_WR1END2_12", + "PCIE_TRNRD4", + "PCIE_IMUX43_R_0", + "PCIE_IMUX20_L_4", + "PCIE_FAN0_R_12", + "PCIE_LH1_19", + "PCIE_LOGIC_OUTS_B23_L_7", + "PCIE_DBGVECB34", + "PCIE_CFGERRAERHEADERLOG21", + "PCIE_CFGERRAERHEADERLOG23", + "PCIE_LOGIC_OUTS_B17_R_6", + "PCIE_MIMRXWDATA51", + "PCIE_LOGIC_OUTS_B3_L_8", + "PCIE_IMUX42_R_9", + "PCIE_TRNRDLLPDATA35", + "PCIE_TRNRDLLPDATA12", + "PCIE_EE4B0_10", + "PCIE_IMUX8_L_11", + "PCIE_FAN2_L_3", + "PCIE_PIPETX2DATA15", + "PCIE_BLOCK_OUTS_B0_R_2", + "PCIE_MONITOR_N_5", + "PCIE_IMUX9_L_19", + "PCIE_LH12_17", + "PCIE_TRNFCCPLH2", + "PCIE_WW2A1_7", + "PCIE_CLK1_R_12", + "PCIE_WW4A3_9", + "PCIE_CFGINTERRUPTDI3", + "PCIE_IMUX34_L_13", + "PCIE_IMUX5_R_10", + "PCIE_PIPETX5DATA1", + "PCIE_SW4A1_12", + "PCIE_IMUX0_L_13", + "PCIE_BLOCK_OUTS_B3_R_16", + "PCIE_MIMRXREN", + "PCIE_IMUX38_L_16", + "PCIE_IMUX21_R_10", + "PCIE_MONITOR_P_16", + "PCIE_IMUX8_R_14", + "PCIE_LOGIC_OUTS_B10_R_7", + "PCIE_IMUX16_L_7", + "PCIE_TRNRD12", + "PCIE_LOGIC_OUTS_B14_R_6", + "PCIE_WW2A2_14", + "PCIE_EE4C1_9", + "PCIE_IMUX47_R_10", + "PCIE_PIPETXMARGIN0", + "PCIE_LOGIC_OUTS_B21_R_8", + "PCIE_LOGIC_OUTS_B13_L_8", + "PCIE_IMUX44_R_15", + "PCIE_TL2ERRHDR31", + "PCIE_CFGSUBSYSID12", + "PCIE_TL2PPMSUSPENDOK", + "PCIE_DBGVECC10", + "PCIE_CFGERRAERHEADERLOG10", + "PCIE_CFGPMWAKEN", + "PCIE_IMUX45_R_9", + "PCIE_LOGIC_OUTS_B5_L_2", + "PCIE_CLK1_L_2", + "PCIE_WW4B3_12", + "PCIE_BYP7_R_15", + "PCIE_CFGDEVCONTROLAUXPOWEREN", + "PCIE_TRNRD5", + "PCIE_WW4END2_3", + "PCIE_NW4A3_6", + "PCIE_USERCLK", + "PCIE_LOGIC_OUTS_B22_L_19", + "PCIE_LOGIC_OUTS_B18_R_19", + "PCIE_NW4A2_0", + "PCIE_WW2END2_14", + "PCIE_EE2A0_6", + "PCIE_IMUX4_R_7", + "PCIE_FAN5_R_18", + "PCIE_CFGERRTLPCPLHEADER24", + "PCIE_PIPETX5DATA0", + "PCIE_IMUX18_R_17", + "PCIE_LOGIC_OUTS_B23_R_4", + "PCIE_IMUX8_L_9", + "PCIE_EL1BEG0_19", + "PCIE_NW2A3_15", + "PCIE_CFGPMRCVENTERL1N", + "PCIE_IMUX47_R_11", + "PCIE_SE4BEG1_1", + "PCIE_IMUX18_R_8", + "PCIE_LH11_16", + "PCIE_CFGDSN51", + "PCIE_BLOCK_OUTS_B2_R_12", + "PCIE_BYP0_R_16", + "PCIE_LOGIC_OUTS_B2_L_6", + "PCIE_IMUX30_L_14", + "PCIE_CFGERRECRCN", + "PCIE_MIMTXRADDR11", + "PCIE_NE4C0_9", + "PCIE_ER1BEG1_18", + "PCIE_WR1END0_17", + "PCIE_WW4B1_11", + "PCIE_IMUX4_L_7", + "PCIE_WW4B3_10", + "PCIE_WW2A2_13", + "PCIE_SW2A0_12", + "PCIE_NW2A0_6", + "PCIE_FAN6_L_10", + "PCIE_EE4BEG3_18", + "PCIE_DBGVECB17", + "PCIE_LH9_8", + "PCIE_DBGVECA60", + "PCIE_LOGIC_OUTS_B15_L_11", + "PCIE_LOGIC_OUTS_B14_L_7", + "PCIE_CFGSUBSYSID5", + "PCIE_CFGMGMTDWADDR4", + "PCIE_CFGDSN7", + "PCIE_XILUNCONNOUT39", + "PCIE_XILUNCONNOUT38", + "PCIE_IMUX46_R_2", + "PCIE_EE4BEG3_7", + "PCIE_IMUX4_R_19", + "PCIE_IMUX18_L_3", + "PCIE_LOGIC_OUTS_B3_L_16", + "PCIE_LOGIC_OUTS_B13_R_1", + "PCIE_TRNRD36", + "PCIE_CFGDEVID5", + "PCIE_CTRL1_L_15", + "PCIE_WW2A0_0", + "PCIE_IMUX29_R_13", + "PCIE_PIPETX3DATA3", + "PCIE_IMUX15_R_8", + "PCIE_IMUX20_L_17", + "PCIE_TRNTD86", + "PCIE_IMUX2_L_19", + "PCIE_FAN2_L_5", + "PCIE_NW2A0_2", + "PCIE_SE2A0_10", + "PCIE_EL1BEG2_1", + "PCIE_SW4A1_10", + "PCIE_SE4C1_11", + "PCIE_SW2A2_1", + "PCIE_CFGERRAERHEADERLOG28", + "PCIE_SE2A0_1", + "PCIE_BYP7_L_16", + "PCIE_LOGIC_OUTS_B10_L_10", + "PCIE_NW4END1_15", + "PCIE_TRNRDLLPDATA29", + "PCIE_IMUX19_R_7", + "PCIE_LH1_15", + "PCIE_IMUX4_R_18", + "PCIE_LOGIC_OUTS_B19_R_19", + "PCIE_LH5_4", + "PCIE_NW4END2_0", + "PCIE_CFGSUBSYSID10", + "PCIE_LOGIC_OUTS_B6_R_11", + "PCIE_EE4BEG3_2", + "PCIE_LL2PROTOCOLERR", + "PCIE_LOGIC_OUTS_B12_L_10", + "PCIE_EE4B1_17", + "PCIE_TRNRD72", + "PCIE_LOGIC_OUTS_B18_L_3", + "PCIE_MIMTXWDATA62", + "PCIE_PIPERX6DATA13", + "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", + "PCIE_MIMTXWDATA23", + "PCIE_PIPERX3DATA15", + "PCIE_BLOCK_OUTS_B1_R_9", + "PCIE_MIMRXWDATA11", + "PCIE_IMUX4_L_14", + "PCIE_EE2A1_19", + "PCIE_IMUX37_L_11", + "PCIE_EE4A2_9", + "PCIE_IMUX9_L_10", + "PCIE_EE4B3_19", + "PCIE_IMUX8_L_18", + "PCIE_MIMRXRDATA12", + "PCIE_PIPETX3CHARISK1", + "PCIE_TRNRDLLPDATA53", + "PCIE_TL2ERRHDR18", + "PCIE_CLK1_R_7", + "PCIE_CLK1_R_9", + "PCIE_WW2END3_17", + "PCIE_TRNTD121", + "PCIE_EE2A2_18", + "PCIE_LOGIC_OUTS_B14_R_12", + "PCIE_TRNRD18", + "PCIE_IMUX11_R_9", + "PCIE_LOGIC_OUTS_B13_R_13", + "PCIE_LOGIC_OUTS_B22_L_3", + "PCIE_SE4BEG0_15", + "PCIE_EE4A1_10", + "PCIE_IMUX13_L_0", + "PCIE_DRPEN", + "PCIE_NW4A0_14", + "PCIE_LH7_17", + "PCIE_LOGIC_OUTS_B20_R_16", + "PCIE_WL1END2_13", + "PCIE_WW4B0_12", + "PCIE_PIPERX1DATA13", + "PCIE_MIMRXWDATA64", + "PCIE_MIMTXRDATA57", + "PCIE_PIPERX1POLARITY", + "PCIE_NW4A3_8", + "PCIE_EE4BEG2_1", + "PCIE_EE4BEG2_19", + "PCIE_IMUX4_R_14", + "PCIE_IMUX47_R_2", + "PCIE_PIPERX1ELECIDLE", + "PCIE_IMUX24_L_4", + "PCIE_LOGIC_OUTS_B15_R_4", + "PCIE_LH7_19", + "PCIE_CLK0_R_4", + "PCIE_CLK0_R_5", + "PCIE_LOGIC_OUTS_B21_R_10", + "PCIE_IMUX13_L_9", + "PCIE_IMUX6_R_9", + "PCIE_LOGIC_OUTS_B12_L_5", + "PCIE_LOGIC_OUTS_B9_R_15", + "PCIE_BLOCK_OUTS_B1_L_17", + "PCIE_BYP1_R_15", + "PCIE_PLLANEREVERSALMODE1", + "PCIE_EE2A2_0", + "PCIE_NW4END2_9", + "PCIE_IMUX37_L_2", + "PCIE_IMUX13_R_9", + "PCIE_EE4A1_3", + "PCIE_IMUX47_R_19", + "PCIE_SW4END1_13", + "PCIE_WW2A0_11", + "PCIE_LOGIC_OUTS_B13_L_19", + "PCIE_WW4B0_1", + "PCIE_IMUX36_R_1", + "PCIE_LOGIC_OUTS_B11_R_9", + "PCIE_BYP4_R_19", + "PCIE_TRNTD69", + "PCIE_NW4END3_1", + "PCIE_IMUX5_R_5", + "PCIE_CFGERRCPLTIMEOUTN", + "PCIE_BLOCK_OUTS_B0_L_1", + "PCIE_IMUX4_L_4", + "PCIE_LOGIC_OUTS_B13_R_6", + "PCIE_SE4C3_2", + "PCIE_SW4END0_19", + "PCIE_MIMRXRDATA22", + "PCIE_WW2END0_3", + "PCIE_BYP3_L_6", + "PCIE_ER1BEG0_1", + "PCIE_IMUX47_R_1", + "PCIE_SW4END2_10", + "PCIE_LH7_3", + "PCIE_IMUX14_R_15", + "PCIE_IMUX17_L_18", + "PCIE_IMUX27_R_1", + "PCIE_IMUX46_L_6", + "PCIE_IMUX19_R_16", + "PCIE_IMUX46_L_7", + "PCIE_PIPETX7DATA9", + "PCIE_CFGMGMTDO21", + "PCIE_IMUX39_R_14", + "PCIE_IMUX2_L_18", + "PCIE_PLDIRECTEDLINKAUTON", + "PCIE_BLOCK_OUTS_B1_R_1", + "PCIE_LH12_0", + "PCIE_SE4C3_3", + "PCIE_TRNTD109", + "PCIE_FAN0_L_13", + "PCIE_WW2END1_5", + "PCIE_IMUX20_L_10", + "PCIE_IMUX39_R_9", + "PCIE_CFGERRAERHEADERLOG106", + "PCIE_IMUX6_R_6", + "PCIE_IMUX24_R_4", + "PCIE_FAN0_L_8", + "PCIE_IMUX0_L_15", + "PCIE_PIPERX5DATA7", + "PCIE_XILUNCONNOUT11", + "PCIE_WW2END0_11", + "PCIE_LOGIC_OUTS_B23_R_19", + "PCIE_NW4END3_16", + "PCIE_ER1BEG2_19", + "PCIE_IMUX33_R_14", + "PCIE_WW2END1_12", + "PCIE_TRNTD41", + "PCIE_LH6_19", + "PCIE_EE4B3_5", + "PCIE_LH1_1", + "PCIE_SW4A2_7", + "PCIE_MIMTXRDATA11", + "PCIE_IMUX32_L_2", + "PCIE_CFGVENDID8", + "PCIE_IMUX11_R_12", + "PCIE_ER1BEG0_18", + "PCIE_CFGDSDEVICENUMBER0", + "PCIE_DBGSCLRH", + "PCIE_NW4END0_19", + "PCIE_CLK0_R_10", + "PCIE_NE4C1_3", + "PCIE_LOGIC_OUTS_B9_L_3", + "PCIE_SW2A0_17", + "PCIE_CFGDSN34", + "PCIE_SE4C3_11", + "PCIE_IMUX15_R_14", + "PCIE_EE4BEG3_4", + "PCIE_SE4C0_2", + "PCIE_EE4B2_15", + "PCIE_EE2BEG0_14", + "PCIE_IMUX43_R_7", + "PCIE_PIPERX3DATA1", + "PCIE_CFGDEVCONTROLMAXREADREQ0", + "PCIE_NW4END2_19", + "PCIE_NE4C1_1", + "PCIE_LOGIC_OUTS_B8_R_15", + "PCIE_EE4C0_18", + "PCIE_MIMRXRDATA19", + "PCIE_IMUX13_L_8", + "PCIE_IMUX46_R_1", + "PCIE_WW4C2_8", + "PCIE_ER1BEG2_17", + "PCIE_FAN4_R_19", + "PCIE_WR1END0_8", + "PCIE_IMUX47_L_15", + "PCIE_IMUX25_L_9", + "PCIE_WR1END1_5", + "PCIE_BYP7_R_18", + "PCIE_IMUX41_R_14", + "PCIE_LOGIC_OUTS_B5_R_4", + "PCIE_CFGPMCSRPOWERSTATE0", + "PCIE_BYP0_R_15", + "PCIE_ER1BEG2_6", + "PCIE_IMUX21_L_14", + "PCIE_MIMTXWDATA48", + "PCIE_LOGIC_OUTS_B8_L_10", + "PCIE_PIPETX1DATA2", + "PCIE_TL2ERRHDR52", + "PCIE_FAN1_L_0", + "PCIE_LOGIC_OUTS_B1_R_15", + "PCIE_WW4B3_15", + "PCIE_FAN4_L_12", + "PCIE_LOGIC_OUTS_B4_L_8", + "PCIE_MIMTXWADDR1", + "PCIE_PIPERX0PHYSTATUS", + "PCIE_CLK1_L_4", + "PCIE_BYP7_L_5", + "PCIE_IMUX44_L_3", + "PCIE_LOGIC_OUTS_B3_R_5", + "PCIE_NW2A1_16", + "PCIE_CTRL0_R_3", + "PCIE_IMUX21_R_7", + "PCIE_IMUX5_R_1", + "PCIE_DBGVECB7", + "PCIE_IMUX38_R_11", + "PCIE_IMUX32_R_5", + "PCIE_WW4END3_17", + "PCIE_TRNRDLLPDATA60", + "PCIE_EE4C0_5", + "PCIE_LOGIC_OUTS_B18_L_19", + "PCIE_LOGIC_OUTS_B9_L_12", + "PCIE_LOGIC_OUTS_B9_R_7", + "PCIE_LOGIC_OUTS_B18_R_4", + "PCIE_TRNTD124", + "PCIE_SE4C0_0", + "PCIE_LOGIC_OUTS_B18_L_0", + "PCIE_IMUX43_L_18", + "PCIE_CFGERRAERHEADERLOG26", + "PCIE_PMVSELECT1", + "PCIE_BYP2_L_14", + "PCIE_PIPETX5COMPLIANCE", + "PCIE_SW4A1_2", + "PCIE_WW4C1_8", + "PCIE_TRNRD127", + "PCIE_FAN4_R_0", + "PCIE_EE4BEG0_2", + "PCIE_TRNRD14", + "PCIE_IMUX13_R_11", + "PCIE_BYP7_R_0", + "PCIE_TRNTD49", + "PCIE_IMUX40_L_18", + "PCIE_IMUX17_R_18", + "PCIE_LL2TFCINIT1SEQ", + "PCIE_BLOCK_OUTS_B1_L_9", + "PCIE_EE2A0_12", + "PCIE_IMUX46_R_9", + "PCIE_LOGIC_OUTS_B9_L_14", + "PCIE_SE2A1_4", + "PCIE_PIPERX4DATA1", + "PCIE_MIMRXRDATA44", + "PCIE_FAN1_R_0", + "PCIE_LOGIC_OUTS_B3_L_2", + "PCIE_TL2ERRHDR59", + "PCIE_IMUX7_R_18", + "PCIE_IMUX39_L_6", + "PCIE_IMUX28_R_9", + "PCIE_BLOCK_OUTS_B3_L_15", + "PCIE_MIMTXRDATA31", + "PCIE_PIPERX7VALID", + "PCIE_IMUX39_L_4", + "PCIE_TRNRDLLPDATA42", + "PCIE_LOGIC_OUTS_B2_L_16", + "PCIE_BYP1_L_0", + "PCIE_NW2A0_16", + "PCIE_IMUX16_R_6", + "PCIE_WW4A2_0", + "PCIE_EE4A1_12", + "PCIE_TL2ERRHDR42", + "PCIE_CFGERRAERHEADERLOG54", + "PCIE_EE4B1_14", + "PCIE_FAN0_L_5", + "PCIE_CLK1_L_8", + "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "PCIE_FAN6_R_9", + "PCIE_TRNRD27", + "PCIE_IMUX3_L_16", + "PCIE_IMUX23_L_13", + "PCIE_NW4END0_4", + "PCIE_DBGVECA37", + "PCIE_IMUX43_L_3", + "PCIE_WW4END3_10", + "PCIE_LOGIC_OUTS_B17_L_2", + "PCIE_CFGVCTCVCMAP4", + "PCIE_CFGERRAERHEADERLOG50", + "PCIE_TRNRD62", + "PCIE_CLK1_R_6", + "PCIE_WW4C3_6", + "PCIE_SE4C0_19", + "PCIE_BYP0_R_2", + "PCIE_FAN0_R_5", + "PCIE_EDTCHANNELSOUT1", + "PCIE_BYP3_L_17", + "PCIE_TRNTD65", + "PCIE_TRNRD38", + "PCIE_LOGIC_OUTS_B7_L_5", + "PCIE_PIPERX6DATA8", + "PCIE_DBGVECA9", + "PCIE_CFGSUBSYSVENDID8", + "PCIE_SW4END0_7", + "PCIE_IMUX35_R_11", + "PCIE_IMUX10_R_9", + "PCIE_WW4B1_8", + "PCIE_PIPERX7DATA6", + "PCIE_CLK0_L_13", + "PCIE_CFGMGMTDO31", + "PCIE_LH8_2", + "PCIE_SW4A1_16", + "PCIE_SE2A2_16", + "PCIE_PIPERX1CHANISALIGNED", + "PCIE_TRNTD6", + "PCIE_LOGIC_OUTS_B17_L_16", + "PCIE_SE4C2_18", + "PCIE_IMUX4_R_6", + "PCIE_IMUX41_R_18", + "PCIE_EE4B2_12", + "PCIE_CFGERRTLPCPLHEADER2", + "PCIE_LOGIC_OUTS_B20_L_15", + "PCIE_ER1BEG1_2", + "PCIE_EE4C0_3", + "PCIE_PIPETX3DATA6", + "PCIE_TRNTD42", + "PCIE_LOGIC_OUTS_B0_R_11", + "PCIE_DBGVECB3", + "PCIE_DRPDI14", + "PCIE_CFGDSN36", + "PCIE_BLOCK_OUTS_B1_L_12", + "PCIE_ER1BEG0_16", + "PCIE_LOGIC_OUTS_B19_R_3", + "PCIE_WW4C3_0", + "PCIE_PIPETX4DATA12", + "PCIE_IMUX3_L_13", + "PCIE_NW4A2_4", + "PCIE_WW4END3_1", + "PCIE_EE4C0_0", + "PCIE_IMUX47_L_5", + "PCIE_CFGINTERRUPTDI2", + "PCIE_EE4A3_11", + "PCIE_TRNRD83", + "PCIE_LOGIC_OUTS_B1_R_13", + "PCIE_WL1END2_2", + "PCIE_FAN2_R_3", + "PCIE_CFGERRPOSTEDN", + "PCIE_PIPETX1DATA12", + "PCIE_SW4A0_17", + "PCIE_EE4B3_10", + "PCIE_LOGIC_OUTS_B22_L_6", + "PCIE_SE4BEG2_1", + "PCIE_NW4A2_14", + "PCIE_WW2END2_0", + "PCIE_IMUX12_R_8", + "PCIE_FAN0_R_18", + "PCIE_WW4A0_13", + "PCIE_MIMTXWDATA41", + "PCIE_CFGMGMTDO23", + "PCIE_WW2END3_1", + "PCIE_MIMRXRDATA14", + "PCIE_TRNRD28", + "PCIE_TRNTSRCDSC", + "PCIE_PIPETX3ELECIDLE", + "PCIE_NE2A1_12", + "PCIE_WW2END1_17", + "PCIE_SE2A3_10", + "PCIE_IMUX32_L_13", + "PCIE_WL1END3_5", + "PCIE_ER1BEG0_9", + "PCIE_NW4END0_5", + "PCIE_IMUX9_L_7", + "PCIE_NW2A0_7", + "PCIE_CFGERRAERHEADERLOG63", + "PCIE_NE4BEG3_16", + "PCIE_CFGMSGDATA15", + "PCIE_IMUX8_L_4", + "PCIE_PIPETX3DATA14", + "PCIE_LOGIC_OUTS_B4_L_17", + "PCIE_IMUX38_L_15", + "PCIE_BYP7_R_4", + "PCIE_CFGDSN0", + "PCIE_WW2A2_10", + "PCIE_PLDIRECTEDLINKCHANGE1", + "PCIE_LOGIC_OUTS_B18_R_1", + "PCIE_CFGERRTLPCPLHEADER14", + "PCIE_CFGDSN43", + "PCIE_BLOCK_OUTS_B1_R_10", + "PCIE_BYP7_R_11", + "PCIE_SW4A1_0", + "PCIE_IMUX38_L_5", + "PCIE_IMUX33_R_4", + "PCIE_CFGERRACSN", + "PCIE_MIMRXWDATA5", + "PCIE_BLOCK_OUTS_B3_L_3", + "PCIE_IMUX45_L_3", + "PCIE_TRNRD84", + "PCIE_SW4A0_14", + "PCIE_PIPETX2DATA0", + "PCIE_IMUX28_L_4", + "PCIE_LH10_7", + "PCIE_CFGCOMMANDBUSMASTERENABLE", + "PCIE_FAN5_L_3", + "PCIE_FAN6_R_17", + "PCIE_BYP5_L_12", + "PCIE_IMUX19_R_11", + "PCIE_LOGIC_OUTS_B9_L_4", + "PCIE_LH2_18", + "PCIE_LOGIC_OUTS_B18_L_13", + "PCIE_LOGIC_OUTS_B11_L_7", + "PCIE_WW2A1_12", + "PCIE_IMUX28_R_2", + "PCIE_IMUX11_R_7", + "PCIE_IMUX27_R_14", + "PCIE_WW2END1_0", + "PCIE_XILUNCONNOUT0", + "PCIE_IMUX38_L_3", + "PCIE_IMUX10_L_16", + "PCIE_FAN6_R_0", + "PCIE_IMUX44_L_19", + "PCIE_FAN2_R_10", + "PCIE_IMUX28_R_15", + "PCIE_IMUX35_L_14", + "PCIE_LOGIC_OUTS_B0_R_7", + "PCIE_LOGIC_OUTS_B13_L_13", + "PCIE_IMUX11_R_11", + "PCIE_IMUX28_L_19", + "PCIE_CFGMGMTDI23", + "PCIE_IMUX11_R_14", + "PCIE_LOGIC_OUTS_B16_R_3", + "PCIE_PIPERX7CHARISK1", + "PCIE_LH1_2", + "PCIE_LOGIC_OUTS_B6_R_10", + "PCIE_IMUX1_L_11", + "PCIE_SE2A3_14", + "PCIE_IMUX20_R_14", + "PCIE_XILUNCONNOUT3", + "PCIE_BYP5_R_16", + "PCIE_LOGIC_OUTS_B22_R_18", + "PCIE_LOGIC_OUTS_B22_R_12", + "PCIE_CFGINTERRUPTDI4", + "PCIE_IMUX35_L_2", + "PCIE_BLOCK_OUTS_B1_L_11", + "PCIE_MIMTXRADDR7", + "PCIE_EE4C0_13", + "PCIE_IMUX35_L_9", + "PCIE_PIPETX4DATA5", + "PCIE_LOGIC_OUTS_B18_L_11", + "PCIE_IMUX30_L_11", + "PCIE_DBGVECA12", + "PCIE_LOGIC_OUTS_B11_R_7", + "PCIE_FAN1_R_17", + "PCIE_PIPERX6CHANISALIGNED", + "PCIE_BYP0_R_12", + "PCIE_DBGVECA1", + "PCIE_EE2A1_11", + "PCIE_IMUX34_L_8", + "PCIE_PIPETX1DATA5", + "PCIE_IMUX15_R_16", + "PCIE_IMUX31_R_18", + "PCIE_IMUX35_L_15", + "PCIE_PIPERX5DATA9", + "PCIE_CFGFORCECOMMONCLOCKOFF", + "PCIE_IMUX5_L_10", + "PCIE_LOGIC_OUTS_B1_R_1", + "PCIE_TRNRDLLPDATA54", + "PCIE_LOGIC_OUTS_B14_R_4", + "PCIE_TRNTECRCGEN", + "PCIE_MIMRXRDATA60", + "PCIE_SW4A1_6", + "PCIE_IMUX33_L_6", + "PCIE_WL1END1_14", + "PCIE_CFGERRLOCKEDN", + "PCIE_TL2ERRHDR2", + "PCIE_NW4A0_9", + "PCIE_NE4C3_15", + "PCIE_LOGIC_OUTS_B17_L_4", + "PCIE_BYP7_L_8", + "PCIE_IMUX47_L_3", + "PCIE_IMUX45_R_19", + "PCIE_PL2RXPMSTATE0", + "PCIE_IMUX35_R_4", + "PCIE_LOGIC_OUTS_B18_L_18", + "PCIE_IMUX29_R_14", + "PCIE_TRNTDSTRDY1", + "PCIE_LOGIC_OUTS_B14_L_12", + "PCIE_LOGIC_OUTS_B8_R_18", + "PCIE_IMUX18_R_0", + "PCIE_FAN6_L_11", + "PCIE_LOGIC_OUTS_B8_R_4", + "PCIE_WW4A0_11", + "PCIE_BLOCK_OUTS_B0_L_10", + "PCIE_NE4BEG0_2", + "PCIE_IMUX7_R_10", + "PCIE_CFGERRAERHEADERLOG19", + "PCIE_IMUX7_L_12", + "PCIE_CFGERRAERHEADERLOG47", + "PCIE_IMUX35_R_3", + "PCIE_SW4END1_8", + "PCIE_IMUX19_R_15", + "PCIE_WW4C0_12" + ], + "tile_type": "PCIE_BOT", + "sites": [ + { + "site_pins": { + "CFGERRAERHEADERLOG77": "PCIE_CFGERRAERHEADERLOG77", + "CFGMSGRECEIVEDERRCOR": "PCIE_CFGMSGRECEIVEDERRCOR", + "PIPETX7DATA3": "PCIE_PIPETX7DATA3", + "PIPETX1DATA0": "PCIE_PIPETX1DATA0", + "TRNRDLLPDATA31": "PCIE_TRNRDLLPDATA31", + "DBGVECA51": "PCIE_DBGVECA51", + "TRNTECRCGEN": "PCIE_TRNTECRCGEN", + "CFGERRAERHEADERLOG90": "PCIE_CFGERRAERHEADERLOG90", + "MIMRXWDATA28": "PCIE_MIMRXWDATA28", + "CFGLINKSTATUSLINKTRAINING": "PCIE_CFGLINKSTATUSLINKTRAINING", + "TRNRD110": "PCIE_TRNRD110", + "TRNTD35": "PCIE_TRNTD35", + "CFGDSN46": "PCIE_CFGDSN46", + "TRNFCCPLH0": "PCIE_TRNFCCPLH0", + "TRNRBARHIT0": "PCIE_TRNRBARHIT0", + "TRNRD51": "PCIE_TRNRD51", + "PIPERX0DATA6": "PCIE_PIPERX0DATA6", + "TRNTD120": "PCIE_TRNTD120", + "PIPETX6COMPLIANCE": "PCIE_PIPETX6COMPLIANCE", + "CFGERRAERHEADERLOG9": "PCIE_CFGERRAERHEADERLOG9", + "PLINITIALLINKWIDTH2": "PCIE_PLINITIALLINKWIDTH2", + "TRNTD42": "PCIE_TRNTD42", + "CFGERRAERHEADERLOG78": "PCIE_CFGERRAERHEADERLOG78", + "CFGERRAERHEADERLOG23": "PCIE_CFGERRAERHEADERLOG23", + "CFGMGMTWRREADONLYN": "PCIE_CFGMGMTWRREADONLYN", + "TRNTD15": "PCIE_TRNTD15", + "CFGMGMTDO4": "PCIE_CFGMGMTDO4", + "DRPDO9": "PCIE_DRPDO9", + "CFGDSN42": "PCIE_CFGDSN42", + "CFGDSN28": "PCIE_CFGDSN28", + "CFGTRANSACTIONADDR4": "PCIE_CFGTRANSACTIONADDR4", + "MIMTXRDATA66": "PCIE_MIMTXRDATA66", + "MIMTXWADDR4": "PCIE_MIMTXWADDR4", + "PIPERX0POLARITY": "PCIE_PIPERX0POLARITY", + "TL2ERRHDR47": "PCIE_TL2ERRHDR47", + "CFGSUBSYSVENDID7": "PCIE_CFGSUBSYSVENDID7", + "TL2ERRHDR22": "PCIE_TL2ERRHDR22", + "TRNFCPD4": "PCIE_TRNFCPD4", + "PLLANEREVERSALMODE0": "PCIE_PLLANEREVERSALMODE0", + "MIMRXRDATA46": "PCIE_MIMRXRDATA46", + "TRNTD87": "PCIE_TRNTD87", + "CFGVCTCVCMAP5": "PCIE_CFGVCTCVCMAP5", + "CFGFORCEEXTENDEDSYNCON": "PCIE_CFGFORCEEXTENDEDSYNCON", + "XILUNCONNOUT15": "PCIE_XILUNCONNOUT15", + "TRNTD20": "PCIE_TRNTD20", + "PLDIRECTEDLINKCHANGE0": "PCIE_PLDIRECTEDLINKCHANGE0", + "SCANMODEN": "PCIE_SCANMODEN", + "TRNRD30": "PCIE_TRNRD30", + "PIPETX6DATA0": "PCIE_PIPETX6DATA0", + "MIMRXWDATA6": "PCIE_MIMRXWDATA6", + "CFGDSN23": "PCIE_CFGDSN23", + "MIMTXRDATA55": "PCIE_MIMTXRDATA55", + "PIPETX1ELECIDLE": "PCIE_PIPETX1ELECIDLE", + "CFGMGMTDI9": "PCIE_CFGMGMTDI9", + "TRNTD76": "PCIE_TRNTD76", + "MIMTXWDATA60": "PCIE_MIMTXWDATA60", + "CFGMGMTDI20": "PCIE_CFGMGMTDI20", + "MIMTXRDATA27": "PCIE_MIMTXRDATA27", + "TRNRSOF": "PCIE_TRNRSOF", + "CFGMGMTDI7": "PCIE_CFGMGMTDI7", + "CFGPMFORCESTATEENN": "PCIE_CFGPMFORCESTATEENN", + "DBGVECA2": "PCIE_DBGVECA2", + "XILUNCONNOUT20": "PCIE_XILUNCONNOUT20", + "TRNRD85": "PCIE_TRNRD85", + "CFGINTERRUPTDI0": "PCIE_CFGINTERRUPTDI0", + "PIPERX3DATA15": "PCIE_PIPERX3DATA15", + "LL2TXIDLE": "PCIE_LL2TXIDLE", + "CFGDSN30": "PCIE_CFGDSN30", + "PLLTSSMSTATE4": "PCIE_PLLTSSMSTATE4", + "CFGERRAERHEADERLOG83": "PCIE_CFGERRAERHEADERLOG83", + "TRNTD103": "PCIE_TRNTD103", + "MIMRXRDATA3": "PCIE_MIMRXRDATA3", + "PIPETX7DATA13": "PCIE_PIPETX7DATA13", + "CFGROOTCONTROLSYSERRFATALERREN": "PCIE_CFGROOTCONTROLSYSERRFATALERREN", + "MIMRXWDATA60": "PCIE_MIMRXWDATA60", + "TL2ERRHDR9": "PCIE_TL2ERRHDR9", + "CFGAERROOTERRCORRERRREPORTINGEN": "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", + "PIPERX2DATA14": "PCIE_PIPERX2DATA14", + "TRNTDLLPDATA4": "PCIE_TRNTDLLPDATA4", + "CFGFORCEMPS1": "PCIE_CFGFORCEMPS1", + "PIPETX4DATA14": "PCIE_PIPETX4DATA14", + "MIMTXRDATA59": "PCIE_MIMTXRDATA59", + "MIMRXRDATA0": "PCIE_MIMRXRDATA0", + "MIMTXRDATA52": "PCIE_MIMTXRDATA52", + "DRPDO4": "PCIE_DRPDO4", + "MIMTXRADDR3": "PCIE_MIMTXRADDR3", + "PIPETX1DATA11": "PCIE_PIPETX1DATA11", + "PL2DIRECTEDLSTATE4": "PCIE_PL2DIRECTEDLSTATE4", + "DBGVECA35": "PCIE_DBGVECA35", + "TL2ERRHDR20": "PCIE_TL2ERRHDR20", + "MIMRXRDATA40": "PCIE_MIMRXRDATA40", + "TL2ERRHDR4": "PCIE_TL2ERRHDR4", + "CFGLINKSTATUSNEGOTIATEDWIDTH3": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", + "TRNRD1": "PCIE_TRNRD1", + "CFGDSN7": "PCIE_CFGDSN7", + "PLDOWNSTREAMDEEMPHSOURCE": "PCIE_PLDOWNSTREAMDEEMPHSOURCE", + "MIMRXRDATA62": "PCIE_MIMRXRDATA62", + "EDTCHANNELSIN3": "PCIE_EDTCHANNELSIN3", + "TRNRD56": "PCIE_TRNRD56", + "DBGVECB39": "PCIE_DBGVECB39", + "DRPDI10": "PCIE_DRPDI10", + "PIPETX3DATA13": "PCIE_PIPETX3DATA13", + "PIPETX4DATA15": "PCIE_PIPETX4DATA15", + "DBGVECA10": "PCIE_DBGVECA10", + "CFGERRAERHEADERLOG64": "PCIE_CFGERRAERHEADERLOG64", + "MIMRXRDATA66": "PCIE_MIMRXRDATA66", + "PLDIRECTEDLTSSMNEW4": "PCIE_PLDIRECTEDLTSSMNEW4", + "XILUNCONNOUT4": "PCIE_XILUNCONNOUT4", + "PIPERX3DATA8": "PCIE_PIPERX3DATA8", + "PIPETX2DATA12": "PCIE_PIPETX2DATA12", + "PIPERX4CHARISK0": "PCIE_PIPERX4CHARISK0", + "CFGMGMTWRENN": "PCIE_CFGMGMTWRENN", + "PIPERX1DATA9": "PCIE_PIPERX1DATA9", + "MIMRXWDATA35": "PCIE_MIMRXWDATA35", + "PIPETX4CHARISK1": "PCIE_PIPETX4CHARISK1", + "CFGDSN6": "PCIE_CFGDSN6", + "TRNTSTR": "PCIE_TRNTSTR", + "PIPERX4DATA15": "PCIE_PIPERX4DATA15", + "PIPETX6DATA14": "PCIE_PIPETX6DATA14", + "CFGMGMTDO12": "PCIE_CFGMGMTDO12", + "CFGERRTLPCPLHEADER43": "PCIE_CFGERRTLPCPLHEADER43", + "DBGVECB40": "PCIE_DBGVECB40", + "TRNTD102": "PCIE_TRNTD102", + "TRNRD78": "PCIE_TRNRD78", + "CFGVENDID0": "PCIE_CFGVENDID0", + "MIMTXRDATA13": "PCIE_MIMTXRDATA13", + "CFGERRAERHEADERLOG7": "PCIE_CFGERRAERHEADERLOG7", + "CFGERRAERHEADERLOG98": "PCIE_CFGERRAERHEADERLOG98", + "CFGMGMTDO2": "PCIE_CFGMGMTDO2", + "CFGDSN11": "PCIE_CFGDSN11", + "TRNFCCPLH7": "PCIE_TRNFCCPLH7", + "PIPETX7DATA14": "PCIE_PIPETX7DATA14", + "PIPERX4DATA10": "PCIE_PIPERX4DATA10", + "CFGDSN17": "PCIE_CFGDSN17", + "CFGSUBSYSVENDID4": "PCIE_CFGSUBSYSVENDID4", + "MIMRXWDATA54": "PCIE_MIMRXWDATA54", + "PLDIRECTEDLTSSMNEW2": "PCIE_PLDIRECTEDLTSSMNEW2", + "CFGMGMTDO29": "PCIE_CFGMGMTDO29", + "CFGPMRCVENTERL23N": "PCIE_CFGPMRCVENTERL23N", + "DBGVECA34": "PCIE_DBGVECA34", + "CFGERRTLPCPLHEADER31": "PCIE_CFGERRTLPCPLHEADER31", + "PIPETX2DATA6": "PCIE_PIPETX2DATA6", + "DBGSCLRD": "PCIE_DBGSCLRD", + "TRNRD32": "PCIE_TRNRD32", + "MIMTXRDATA60": "PCIE_MIMTXRDATA60", + "CFGMGMTDO21": "PCIE_CFGMGMTDO21", + "DBGVECB21": "PCIE_DBGVECB21", + "CFGREVID3": "PCIE_CFGREVID3", + "PIPETX7POWERDOWN1": "PCIE_PIPETX7POWERDOWN1", + "PIPERX1CHARISK1": "PCIE_PIPERX1CHARISK1", + "DBGVECC8": "PCIE_DBGVECC8", + "PIPERX2DATA13": "PCIE_PIPERX2DATA13", + "DBGVECA38": "PCIE_DBGVECA38", + "MIMTXRDATA9": "PCIE_MIMTXRDATA9", + "PIPETX3DATA14": "PCIE_PIPETX3DATA14", + "XILUNCONNOUT14": "PCIE_XILUNCONNOUT14", + "CFGMGMTDI12": "PCIE_CFGMGMTDI12", + "CFGERRTLPCPLHEADER35": "PCIE_CFGERRTLPCPLHEADER35", + "CFGERRAERHEADERLOG60": "PCIE_CFGERRAERHEADERLOG60", + "TRNRD40": "PCIE_TRNRD40", + "DBGVECA27": "PCIE_DBGVECA27", + "DRPADDR4": "PCIE_DRPADDR4", + "PIPERX6DATA0": "PCIE_PIPERX6DATA0", + "CFGERRTLPCPLHEADER37": "PCIE_CFGERRTLPCPLHEADER37", + "MIMRXWDATA58": "PCIE_MIMRXWDATA58", + "CFGDSN49": "PCIE_CFGDSN49", + "MIMTXWDATA25": "PCIE_MIMTXWDATA25", + "DBGVECA36": "PCIE_DBGVECA36", + "CFGERRCPLTIMEOUTN": "PCIE_CFGERRCPLTIMEOUTN", + "CFGERRTLPCPLHEADER27": "PCIE_CFGERRTLPCPLHEADER27", + "PIPERX3STATUS0": "PCIE_PIPERX3STATUS0", + "CFGERRAERHEADERLOG109": "PCIE_CFGERRAERHEADERLOG109", + "CFGPMFORCESTATE0": "PCIE_CFGPMFORCESTATE0", + "CFGSUBSYSID0": "PCIE_CFGSUBSYSID0", + "TRNTDLLPDATA25": "PCIE_TRNTDLLPDATA25", + "TRNFCSEL0": "PCIE_TRNFCSEL0", + "CFGERRTLPCPLHEADER29": "PCIE_CFGERRTLPCPLHEADER29", + "EDTCHANNELSOUT7": "PCIE_EDTCHANNELSOUT7", + "MIMTXRDATA58": "PCIE_MIMTXRDATA58", + "MIMTXRDATA37": "PCIE_MIMTXRDATA37", + "PIPERX2POLARITY": "PCIE_PIPERX2POLARITY", + "CFGERRTLPCPLHEADER8": "PCIE_CFGERRTLPCPLHEADER8", + "PIPETX1DATA8": "PCIE_PIPETX1DATA8", + "CFGDEVSTATUSFATALERRDETECTED": "PCIE_CFGDEVSTATUSFATALERRDETECTED", + "TRNRD64": "PCIE_TRNRD64", + "PIPERX4POLARITY": "PCIE_PIPERX4POLARITY", + "MIMTXREN": "PCIE_MIMTXREN", + "DBGVECB55": "PCIE_DBGVECB55", + "XILUNCONNOUT36": "PCIE_XILUNCONNOUT36", + "EDTCLK": "PCIE_EDTCLK", + "DRPDO15": "PCIE_DRPDO15", + "XILUNCONNOUT9": "PCIE_XILUNCONNOUT9", + "TRNFCCPLH1": "PCIE_TRNFCCPLH1", + "TRNRD88": "PCIE_TRNRD88", + "TRNRDLLPDATA21": "PCIE_TRNRDLLPDATA21", + "CFGVCTCVCMAP0": "PCIE_CFGVCTCVCMAP0", + "TRNTD48": "PCIE_TRNTD48", + "DBGVECA1": "PCIE_DBGVECA1", + "DBGVECA53": "PCIE_DBGVECA53", + "TRNRD101": "PCIE_TRNRD101", + "TRNRD68": "PCIE_TRNRD68", + "PLTRANSMITHOTRST": "PCIE_PLTRANSMITHOTRST", + "TRNTD4": "PCIE_TRNTD4", + "TRNRBARHIT6": "PCIE_TRNRBARHIT6", + "TRNRD36": "PCIE_TRNRD36", + "PIPERX2DATA6": "PCIE_PIPERX2DATA6", + "CFGERRAERHEADERLOG72": "PCIE_CFGERRAERHEADERLOG72", + "TRNTDLLPDSTRDY": "PCIE_TRNTDLLPDSTRDY", + "DBGVECB11": "PCIE_DBGVECB11", + "PIPERX3VALID": "PCIE_PIPERX3VALID", + "TRNRD80": "PCIE_TRNRD80", + "LL2RECEIVERERR": "PCIE_LL2RECEIVERERR", + "PIPERX7ELECIDLE": "PCIE_PIPERX7ELECIDLE", + "DRPDO14": "PCIE_DRPDO14", + "TRNRDLLPDATA8": "PCIE_TRNRDLLPDATA8", + "CFGPMRCVENTERL1N": "PCIE_CFGPMRCVENTERL1N", + "CFGDSDEVICENUMBER1": "PCIE_CFGDSDEVICENUMBER1", + "TRNTD1": "PCIE_TRNTD1", + "CFGMSGDATA12": "PCIE_CFGMSGDATA12", + "MIMRXWADDR0": "PCIE_MIMRXWADDR0", + "CFGSUBSYSID10": "PCIE_CFGSUBSYSID10", + "TRNTD74": "PCIE_TRNTD74", + "MIMRXWADDR7": "PCIE_MIMRXWADDR7", + "PIPETX0DATA9": "PCIE_PIPETX0DATA9", + "PIPERX3DATA5": "PCIE_PIPERX3DATA5", + "DBGVECA52": "PCIE_DBGVECA52", + "TRNRD3": "PCIE_TRNRD3", + "PIPETXRESET": "PCIE_PIPETXRESET", + "PIPETX7DATA15": "PCIE_PIPETX7DATA15", + "TL2ERRFCPE": "PCIE_TL2ERRFCPE", + "CFGDSN15": "PCIE_CFGDSN15", + "PLDIRECTEDLINKWIDTH0": "PCIE_PLDIRECTEDLINKWIDTH0", + "CFGERRAERHEADERLOG18": "PCIE_CFGERRAERHEADERLOG18", + "TRNRD123": "PCIE_TRNRD123", + "PIPERX6DATA4": "PCIE_PIPERX6DATA4", + "TRNRD49": "PCIE_TRNRD49", + "CFGINTERRUPTDI3": "PCIE_CFGINTERRUPTDI3", + "TRNRD0": "PCIE_TRNRD0", + "TRNTDSTRDY1": "PCIE_TRNTDSTRDY1", + "MIMTXRADDR11": "PCIE_MIMTXRADDR11", + "DRPDI12": "PCIE_DRPDI12", + "TL2ERRHDR54": "PCIE_TL2ERRHDR54", + "CFGERRAERHEADERLOG86": "PCIE_CFGERRAERHEADERLOG86", + "CFGLINKSTATUSBANDWIDTHSTATUS": "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", + "CFGVENDID4": "PCIE_CFGVENDID4", + "PLDIRECTEDLTSSMSTALL": "PCIE_PLDIRECTEDLTSSMSTALL", + "DBGVECB7": "PCIE_DBGVECB7", + "EDTCHANNELSOUT6": "PCIE_EDTCHANNELSOUT6", + "DBGVECC6": "PCIE_DBGVECC6", + "TRNTDLLPDATA30": "PCIE_TRNTDLLPDATA30", + "XILUNCONNOUT23": "PCIE_XILUNCONNOUT23", + "CFGINTERRUPTDI7": "PCIE_CFGINTERRUPTDI7", + "TRNFCNPH5": "PCIE_TRNFCNPH5", + "CFGERRTLPCPLHEADER38": "PCIE_CFGERRTLPCPLHEADER38", + "MIMTXWDATA13": "PCIE_MIMTXWDATA13", + "TRNTD0": "PCIE_TRNTD0", + "DBGVECB16": "PCIE_DBGVECB16", + "DRPCLK": "PCIE_DRPCLK", + "DBGVECA14": "PCIE_DBGVECA14", + "PIPETX5COMPLIANCE": "PCIE_PIPETX5COMPLIANCE", + "TL2ERRHDR16": "PCIE_TL2ERRHDR16", + "PIPETX6DATA5": "PCIE_PIPETX6DATA5", + "CFGTRNPENDINGN": "PCIE_CFGTRNPENDINGN", + "PIPERX5DATA12": "PCIE_PIPERX5DATA12", + "MIMRXRDATA64": "PCIE_MIMRXRDATA64", + "CFGMSGDATA13": "PCIE_CFGMSGDATA13", + "PIPETX2DATA0": "PCIE_PIPETX2DATA0", + "CFGERRAERHEADERLOG35": "PCIE_CFGERRAERHEADERLOG35", + "MIMTXRADDR10": "PCIE_MIMTXRADDR10", + "CFGMGMTDI31": "PCIE_CFGMGMTDI31", + "CFGINTERRUPTDO4": "PCIE_CFGINTERRUPTDO4", + "CFGINTERRUPTMSIENABLE": "PCIE_CFGINTERRUPTMSIENABLE", + "CFGMSGRECEIVEDERRFATAL": "PCIE_CFGMSGRECEIVEDERRFATAL", + "CFGSUBSYSVENDID1": "PCIE_CFGSUBSYSVENDID1", + "PIPERX7DATA7": "PCIE_PIPERX7DATA7", + "PIPETX6DATA11": "PCIE_PIPETX6DATA11", + "TRNTD23": "PCIE_TRNTD23", + "PLDBGVEC2": "PCIE_PLDBGVEC2", + "CFGMGMTDO26": "PCIE_CFGMGMTDO26", + "MIMRXRDATA26": "PCIE_MIMRXRDATA26", + "CFGDEVID14": "PCIE_CFGDEVID14", + "MIMTXWDATA29": "PCIE_MIMTXWDATA29", + "CFGERRECRCN": "PCIE_CFGERRECRCN", + "PIPERX7CHARISK1": "PCIE_PIPERX7CHARISK1", + "DBGVECB45": "PCIE_DBGVECB45", + "CFGBRIDGESERREN": "PCIE_CFGBRIDGESERREN", + "TRNRD38": "PCIE_TRNRD38", + "TRNRDLLPDATA2": "PCIE_TRNRDLLPDATA2", + "PIPERX0DATA9": "PCIE_PIPERX0DATA9", + "CFGERRAERHEADERLOG66": "PCIE_CFGERRAERHEADERLOG66", + "CFGERRTLPCPLHEADER6": "PCIE_CFGERRTLPCPLHEADER6", + "PIPERX1DATA4": "PCIE_PIPERX1DATA4", + "LL2BADTLPERR": "PCIE_LL2BADTLPERR", + "DBGVECC1": "PCIE_DBGVECC1", + "TRNTD8": "PCIE_TRNTD8", + "CFGSUBSYSVENDID6": "PCIE_CFGSUBSYSVENDID6", + "DBGVECB10": "PCIE_DBGVECB10", + "TRNRBARHIT3": "PCIE_TRNRBARHIT3", + "CFGERRTLPCPLHEADER46": "PCIE_CFGERRTLPCPLHEADER46", + "PIPETXRATE": "PCIE_PIPETXRATE", + "CFGMGMTDO25": "PCIE_CFGMGMTDO25", + "MIMTXWDATA23": "PCIE_MIMTXWDATA23", + "CFGDSN44": "PCIE_CFGDSN44", + "TRNTBUFAV5": "PCIE_TRNTBUFAV5", + "CFGPMFORCESTATE1": "PCIE_CFGPMFORCESTATE1", + "PIPERX4ELECIDLE": "PCIE_PIPERX4ELECIDLE", + "PIPETX0CHARISK1": "PCIE_PIPETX0CHARISK1", + "CFGERRTLPCPLHEADER13": "PCIE_CFGERRTLPCPLHEADER13", + "MIMRXRDATA42": "PCIE_MIMRXRDATA42", + "PIPERX0DATA5": "PCIE_PIPERX0DATA5", + "PIPERX2STATUS2": "PCIE_PIPERX2STATUS2", + "CFGERRAERHEADERLOG81": "PCIE_CFGERRAERHEADERLOG81", + "MIMRXWDATA44": "PCIE_MIMRXWDATA44", + "PIPETX0DATA13": "PCIE_PIPETX0DATA13", + "TRNRFCPRET": "PCIE_TRNRFCPRET", + "TRNTD127": "PCIE_TRNTD127", + "MIMTXWADDR8": "PCIE_MIMTXWADDR8", + "TRNRD92": "PCIE_TRNRD92", + "MIMRXWDATA41": "PCIE_MIMRXWDATA41", + "TRNTD17": "PCIE_TRNTD17", + "TL2ERRMALFORMED": "PCIE_TL2ERRMALFORMED", + "XILUNCONNOUT6": "PCIE_XILUNCONNOUT6", + "TRNRDLLPDATA12": "PCIE_TRNRDLLPDATA12", + "PIPETX0POWERDOWN0": "PCIE_PIPETX0POWERDOWN0", + "TRNTERRFWD": "PCIE_TRNTERRFWD", + "TRNFCPH2": "PCIE_TRNFCPH2", + "CFGINTERRUPTDI1": "PCIE_CFGINTERRUPTDI1", + "CFGERRAERHEADERLOG71": "PCIE_CFGERRAERHEADERLOG71", + "DBGVECA62": "PCIE_DBGVECA62", + "PIPETX7ELECIDLE": "PCIE_PIPETX7ELECIDLE", + "CFGERRAERHEADERLOG42": "PCIE_CFGERRAERHEADERLOG42", + "CFGVENDID11": "PCIE_CFGVENDID11", + "XILUNCONNOUT29": "PCIE_XILUNCONNOUT29", + "MIMTXWDATA47": "PCIE_MIMTXWDATA47", + "CFGSUBSYSVENDID12": "PCIE_CFGSUBSYSVENDID12", + "CFGDSFUNCTIONNUMBER1": "PCIE_CFGDSFUNCTIONNUMBER1", + "TRNRD25": "PCIE_TRNRD25", + "CFGDSFUNCTIONNUMBER2": "PCIE_CFGDSFUNCTIONNUMBER2", + "PIPERX0STATUS0": "PCIE_PIPERX0STATUS0", + "CFGMGMTDI10": "PCIE_CFGMGMTDI10", + "TRNTSRCRDY": "PCIE_TRNTSRCRDY", + "DBGVECB47": "PCIE_DBGVECB47", + "DBGVECB1": "PCIE_DBGVECB1", + "PIPERX3CHARISK0": "PCIE_PIPERX3CHARISK0", + "CFGSUBSYSID5": "PCIE_CFGSUBSYSID5", + "TL2ERRHDR44": "PCIE_TL2ERRHDR44", + "CFGDSDEVICENUMBER3": "PCIE_CFGDSDEVICENUMBER3", + "DBGVECB62": "PCIE_DBGVECB62", + "CFGINTERRUPTMSIXENABLE": "PCIE_CFGINTERRUPTMSIXENABLE", + "TRNFCNPD2": "PCIE_TRNFCNPD2", + "RECEIVEDFUNCLVLRSTN": "PCIE_RECEIVEDFUNCLVLRSTN", + "TRNTDLLPDATA5": "PCIE_TRNTDLLPDATA5", + "CFGERRAERHEADERLOG21": "PCIE_CFGERRAERHEADERLOG21", + "CFGLINKCONTROLRCB": "PCIE_CFGLINKCONTROLRCB", + "CFGLINKCONTROLEXTENDEDSYNC": "PCIE_CFGLINKCONTROLEXTENDEDSYNC", + "CFGAERROOTERRCORRERRRECEIVED": "PCIE_CFGAERROOTERRCORRERRRECEIVED", + "PIPERX6CHARISK1": "PCIE_PIPERX6CHARISK1", + "CFGMGMTDWADDR9": "PCIE_CFGMGMTDWADDR9", + "MIMTXRDATA1": "PCIE_MIMTXRDATA1", + "DBGVECA31": "PCIE_DBGVECA31", + "PIPERX5VALID": "PCIE_PIPERX5VALID", + "TRNFCCPLH5": "PCIE_TRNFCCPLH5", + "TRNRDLLPDATA19": "PCIE_TRNRDLLPDATA19", + "CFGERRAERHEADERLOG102": "PCIE_CFGERRAERHEADERLOG102", + "CFGMGMTDO23": "PCIE_CFGMGMTDO23", + "MIMTXWDATA54": "PCIE_MIMTXWDATA54", + "PIPERX6ELECIDLE": "PCIE_PIPERX6ELECIDLE", + "TRNTDLLPDATA23": "PCIE_TRNTDLLPDATA23", + "CFGDEVCONTROL2CPLTIMEOUTVAL2": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "PIPETX4COMPLIANCE": "PCIE_PIPETX4COMPLIANCE", + "DBGVECB15": "PCIE_DBGVECB15", + "TRNRD100": "PCIE_TRNRD100", + "TRNRD22": "PCIE_TRNRD22", + "DBGMODE0": "PCIE_DBGMODE0", + "TL2ERRHDR17": "PCIE_TL2ERRHDR17", + "MIMTXWDATA0": "PCIE_MIMTXWDATA0", + "CFGLINKSTATUSCURRENTSPEED1": "PCIE_CFGLINKSTATUSCURRENTSPEED1", + "CFGDEVCONTROLPHANTOMEN": "PCIE_CFGDEVCONTROLPHANTOMEN", + "EDTCHANNELSIN7": "PCIE_EDTCHANNELSIN7", + "PIPERX7STATUS0": "PCIE_PIPERX7STATUS0", + "DBGVECA8": "PCIE_DBGVECA8", + "CFGVCTCVCMAP6": "PCIE_CFGVCTCVCMAP6", + "XILUNCONNOUT37": "PCIE_XILUNCONNOUT37", + "DBGVECA9": "PCIE_DBGVECA9", + "CFGERRTLPCPLHEADER45": "PCIE_CFGERRTLPCPLHEADER45", + "TRNRD8": "PCIE_TRNRD8", + "MIMRXRDATA5": "PCIE_MIMRXRDATA5", + "CFGERRAERHEADERLOG110": "PCIE_CFGERRAERHEADERLOG110", + "CFGDSN38": "PCIE_CFGDSN38", + "DBGVECB37": "PCIE_DBGVECB37", + "CFGPORTNUMBER1": "PCIE_CFGPORTNUMBER1", + "CFGDSN8": "PCIE_CFGDSN8", + "CFGMGMTDO0": "PCIE_CFGMGMTDO0", + "MIMTXRDATA19": "PCIE_MIMTXRDATA19", + "TL2ERRHDR24": "PCIE_TL2ERRHDR24", + "CFGVCTCVCMAP4": "PCIE_CFGVCTCVCMAP4", + "CFGINTERRUPTDI5": "PCIE_CFGINTERRUPTDI5", + "MIMRXWDATA33": "PCIE_MIMRXWDATA33", + "TRNRDLLPDATA62": "PCIE_TRNRDLLPDATA62", + "PIPERX5DATA4": "PCIE_PIPERX5DATA4", + "PIPERX4DATA2": "PCIE_PIPERX4DATA2", + "MIMRXWDATA23": "PCIE_MIMRXWDATA23", + "XILUNCONNOUT11": "PCIE_XILUNCONNOUT11", + "CFGMGMTDO15": "PCIE_CFGMGMTDO15", + "DBGVECB30": "PCIE_DBGVECB30", + "DBGVECA16": "PCIE_DBGVECA16", + "TRNTD27": "PCIE_TRNTD27", + "PL2RECEIVERERR": "PCIE_PL2RECEIVERERR", + "CFGERRAERHEADERLOG96": "PCIE_CFGERRAERHEADERLOG96", + "DBGVECB25": "PCIE_DBGVECB25", + "CFGERRAERHEADERLOG25": "PCIE_CFGERRAERHEADERLOG25", + "CFGERRTLPCPLHEADER0": "PCIE_CFGERRTLPCPLHEADER0", + "TRNRD42": "PCIE_TRNRD42", + "PLDBGVEC4": "PCIE_PLDBGVEC4", + "TRNTBUFAV3": "PCIE_TRNTBUFAV3", + "PIPETX5DATA10": "PCIE_PIPETX5DATA10", + "TRNTDLLPDATA9": "PCIE_TRNTDLLPDATA9", + "PIPETX5DATA14": "PCIE_PIPETX5DATA14", + "CFGDEVCONTROLMAXPAYLOAD2": "PCIE_CFGDEVCONTROLMAXPAYLOAD2", + "TRNRD81": "PCIE_TRNRD81", + "PMVSELECT1": "PCIE_PMVSELECT1", + "CFGREVID0": "PCIE_CFGREVID0", + "TRNREOF": "PCIE_TRNREOF", + "CFGERRAERHEADERLOG93": "PCIE_CFGERRAERHEADERLOG93", + "DBGVECB57": "PCIE_DBGVECB57", + "CFGSUBSYSID11": "PCIE_CFGSUBSYSID11", + "DBGVECA61": "PCIE_DBGVECA61", + "CFGSUBSYSID4": "PCIE_CFGSUBSYSID4", + "CFGMSGDATA9": "PCIE_CFGMSGDATA9", + "MIMRXRDATA1": "PCIE_MIMRXRDATA1", + "TRNRD79": "PCIE_TRNRD79", + "TRNFCCPLD4": "PCIE_TRNFCCPLD4", + "TRNRD89": "PCIE_TRNRD89", + "DBGVECA33": "PCIE_DBGVECA33", + "DBGVECA54": "PCIE_DBGVECA54", + "CFGERRAERHEADERLOG12": "PCIE_CFGERRAERHEADERLOG12", + "CFGVENDID12": "PCIE_CFGVENDID12", + "MIMTXWDATA35": "PCIE_MIMTXWDATA35", + "TRNRREM0": "PCIE_TRNRREM0", + "PIPERX6DATA8": "PCIE_PIPERX6DATA8", + "CFGPORTNUMBER5": "PCIE_CFGPORTNUMBER5", + "CFGLINKSTATUSDLLACTIVE": "PCIE_CFGLINKSTATUSDLLACTIVE", + "PIPERX5CHARISK0": "PCIE_PIPERX5CHARISK0", + "DBGVECA7": "PCIE_DBGVECA7", + "CFGVCTCVCMAP1": "PCIE_CFGVCTCVCMAP1", + "CFGMSGDATA4": "PCIE_CFGMSGDATA4", + "TRNTD81": "PCIE_TRNTD81", + "PIPERX5DATA15": "PCIE_PIPERX5DATA15", + "CFGDSN33": "PCIE_CFGDSN33", + "TRNRD13": "PCIE_TRNRD13", + "MIMRXRDATA20": "PCIE_MIMRXRDATA20", + "CFGERRAERHEADERLOG97": "PCIE_CFGERRAERHEADERLOG97", + "MIMTXWDATA11": "PCIE_MIMTXWDATA11", + "TRNFCCPLD7": "PCIE_TRNFCCPLD7", + "TRNRD60": "PCIE_TRNRD60", + "PIPERX6DATA5": "PCIE_PIPERX6DATA5", + "TRNFCPH5": "PCIE_TRNFCPH5", + "MIMTXWDATA31": "PCIE_MIMTXWDATA31", + "DBGVECA3": "PCIE_DBGVECA3", + "CFGERRAERHEADERLOG84": "PCIE_CFGERRAERHEADERLOG84", + "MIMTXWADDR6": "PCIE_MIMTXWADDR6", + "MIMRXWDATA11": "PCIE_MIMRXWDATA11", + "USERCLKPREBUFEN": "PCIE_USERCLKPREBUFEN", + "TL2ERRHDR49": "PCIE_TL2ERRHDR49", + "TRNRDLLPDATA41": "PCIE_TRNRDLLPDATA41", + "PIPETX5DATA5": "PCIE_PIPETX5DATA5", + "TL2ERRHDR6": "PCIE_TL2ERRHDR6", + "TRNFCPD2": "PCIE_TRNFCPD2", + "MIMTXWDATA58": "PCIE_MIMTXWDATA58", + "TRNTD68": "PCIE_TRNTD68", + "TRNFCCPLH2": "PCIE_TRNFCCPLH2", + "DBGVECA60": "PCIE_DBGVECA60", + "CFGPCIELINKSTATE2": "PCIE_CFGPCIELINKSTATE2", + "TL2ERRHDR21": "PCIE_TL2ERRHDR21", + "TRNRD16": "PCIE_TRNRD16", + "PIPERX2DATA9": "PCIE_PIPERX2DATA9", + "PIPERX1DATA8": "PCIE_PIPERX1DATA8", + "EDTCHANNELSIN8": "PCIE_EDTCHANNELSIN8", + "PIPERX2DATA7": "PCIE_PIPERX2DATA7", + "TRNTDLLPDATA26": "PCIE_TRNTDLLPDATA26", + "PLDIRECTEDLINKCHANGE1": "PCIE_PLDIRECTEDLINKCHANGE1", + "CFGERRAERHEADERLOG68": "PCIE_CFGERRAERHEADERLOG68", + "CFGDEVCONTROLMAXREADREQ2": "PCIE_CFGDEVCONTROLMAXREADREQ2", + "CFGDEVCONTROLMAXREADREQ1": "PCIE_CFGDEVCONTROLMAXREADREQ1", + "CFGROOTCONTROLSYSERRCORRERREN": "PCIE_CFGROOTCONTROLSYSERRCORRERREN", + "EDTCHANNELSOUT3": "PCIE_EDTCHANNELSOUT3", + "XILUNCONNOUT25": "PCIE_XILUNCONNOUT25", + "CFGDSN45": "PCIE_CFGDSN45", + "PLTXPMSTATE0": "PCIE_PLTXPMSTATE0", + "PIPERX3CHARISK1": "PCIE_PIPERX3CHARISK1", + "TRNTD119": "PCIE_TRNTD119", + "MIMTXWDATA65": "PCIE_MIMTXWDATA65", + "TRNRDLLPDATA63": "PCIE_TRNRDLLPDATA63", + "CFGPCIECAPINTERRUPTMSGNUM3": "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", + "PL2DIRECTEDLSTATE1": "PCIE_PL2DIRECTEDLSTATE1", + "MIMRXWDATA14": "PCIE_MIMRXWDATA14", + "TL2ERRHDR31": "PCIE_TL2ERRHDR31", + "TL2ERRHDR56": "PCIE_TL2ERRHDR56", + "MIMRXRADDR4": "PCIE_MIMRXRADDR4", + "DRPDO10": "PCIE_DRPDO10", + "TRNTREM1": "PCIE_TRNTREM1", + "TRNTDSTRDY0": "PCIE_TRNTDSTRDY0", + "DBGVECB27": "PCIE_DBGVECB27", + "TRNRD33": "PCIE_TRNRD33", + "CFGDSN57": "PCIE_CFGDSN57", + "TL2ERRHDR0": "PCIE_TL2ERRHDR0", + "TRNRD111": "PCIE_TRNRD111", + "MIMTXWDATA57": "PCIE_MIMTXWDATA57", + "MIMTXWDATA20": "PCIE_MIMTXWDATA20", + "MIMTXRDATA34": "PCIE_MIMTXRDATA34", + "CFGLINKCONTROLCLOCKPMEN": "PCIE_CFGLINKCONTROLCLOCKPMEN", + "MIMTXRDATA67": "PCIE_MIMTXRDATA67", + "CFGERRAERHEADERLOG114": "PCIE_CFGERRAERHEADERLOG114", + "TRNRD83": "PCIE_TRNRD83", + "TRNTD121": "PCIE_TRNTD121", + "CFGDSN34": "PCIE_CFGDSN34", + "CFGPMHALTASPML1N": "PCIE_CFGPMHALTASPML1N", + "PIPERX7DATA9": "PCIE_PIPERX7DATA9", + "TRNTD122": "PCIE_TRNTD122", + "MIMTXRDATA43": "PCIE_MIMTXRDATA43", + "PIPETX5DATA1": "PCIE_PIPETX5DATA1", + "TRNTD63": "PCIE_TRNTD63", + "CFGERRCPLABORTN": "PCIE_CFGERRCPLABORTN", + "CFGMGMTDO27": "PCIE_CFGMGMTDO27", + "CMSTICKYRSTN": "PCIE_CMSTICKYRSTN", + "CFGERRAERHEADERLOG47": "PCIE_CFGERRAERHEADERLOG47", + "TRNRD102": "PCIE_TRNRD102", + "PIPERX4CHANISALIGNED": "PCIE_PIPERX4CHANISALIGNED", + "CFGDSN24": "PCIE_CFGDSN24", + "TRNTD88": "PCIE_TRNTD88", + "DBGSCLRC": "PCIE_DBGSCLRC", + "TRNRD98": "PCIE_TRNRD98", + "PIPETX2DATA11": "PCIE_PIPETX2DATA11", + "TRNRD94": "PCIE_TRNRD94", + "CFGTRANSACTIONADDR5": "PCIE_CFGTRANSACTIONADDR5", + "PIPERX1ELECIDLE": "PCIE_PIPERX1ELECIDLE", + "CFGERRMCBLOCKEDN": "PCIE_CFGERRMCBLOCKEDN", + "MIMTXRADDR5": "PCIE_MIMTXRADDR5", + "CFGMSGRECEIVEDASSERTINTB": "PCIE_CFGMSGRECEIVEDASSERTINTB", + "LL2SUSPENDOK": "PCIE_LL2SUSPENDOK", + "DBGVECC2": "PCIE_DBGVECC2", + "CFGERRAERHEADERLOG19": "PCIE_CFGERRAERHEADERLOG19", + "CFGSUBSYSID2": "PCIE_CFGSUBSYSID2", + "TRNTD108": "PCIE_TRNTD108", + "DRPDI8": "PCIE_DRPDI8", + "CFGCOMMANDIOENABLE": "PCIE_CFGCOMMANDIOENABLE", + "PIPERX7VALID": "PCIE_PIPERX7VALID", + "PIPETX4DATA9": "PCIE_PIPETX4DATA9", + "MIMTXWDATA53": "PCIE_MIMTXWDATA53", + "XILUNCONNOUT17": "PCIE_XILUNCONNOUT17", + "DBGVECA37": "PCIE_DBGVECA37", + "PLUPSTREAMPREFERDEEMPH": "PCIE_PLUPSTREAMPREFERDEEMPH", + "CFGERRACSN": "PCIE_CFGERRACSN", + "DRPDO13": "PCIE_DRPDO13", + "PIPETX3DATA2": "PCIE_PIPETX3DATA2", + "TRNTD47": "PCIE_TRNTD47", + "TRNFCSEL1": "PCIE_TRNFCSEL1", + "DBGVECA5": "PCIE_DBGVECA5", + "PIPERX1DATA1": "PCIE_PIPERX1DATA1", + "MIMTXWDATA44": "PCIE_MIMTXWDATA44", + "TRNRERRFWD": "PCIE_TRNRERRFWD", + "TL2ERRHDR33": "PCIE_TL2ERRHDR33", + "PIPERX6VALID": "PCIE_PIPERX6VALID", + "TRNRD14": "PCIE_TRNRD14", + "TRNTD125": "PCIE_TRNTD125", + "PIPETX2DATA2": "PCIE_PIPETX2DATA2", + "PIPERX2DATA12": "PCIE_PIPERX2DATA12", + "MIMTXRDATA61": "PCIE_MIMTXRDATA61", + "TRNTDLLPDATA18": "PCIE_TRNTDLLPDATA18", + "PIPETX3COMPLIANCE": "PCIE_PIPETX3COMPLIANCE", + "TRNRD10": "PCIE_TRNRD10", + "CFGINTERRUPTMMENABLE0": "PCIE_CFGINTERRUPTMMENABLE0", + "LL2SENDENTERL23": "PCIE_LL2SENDENTERL23", + "CFGINTERRUPTMMENABLE2": "PCIE_CFGINTERRUPTMMENABLE2", + "TRNTD89": "PCIE_TRNTD89", + "CFGERRPOISONEDN": "PCIE_CFGERRPOISONEDN", + "PIPERX1DATA7": "PCIE_PIPERX1DATA7", + "MIMRXWDATA52": "PCIE_MIMRXWDATA52", + "PIPERX3DATA2": "PCIE_PIPERX3DATA2", + "TRNTD77": "PCIE_TRNTD77", + "PIPERX5DATA9": "PCIE_PIPERX5DATA9", + "DBGVECB63": "PCIE_DBGVECB63", + "MIMTXRADDR0": "PCIE_MIMTXRADDR0", + "CFGERRLOCKEDN": "PCIE_CFGERRLOCKEDN", + "MIMTXRADDR2": "PCIE_MIMTXRADDR2", + "TRNFCPD3": "PCIE_TRNFCPD3", + "MIMRXRADDR11": "PCIE_MIMRXRADDR11", + "CFGERRAERHEADERLOG0": "PCIE_CFGERRAERHEADERLOG0", + "MIMTXRDATA16": "PCIE_MIMTXRDATA16", + "PIPERX6DATA10": "PCIE_PIPERX6DATA10", + "DBGVECB29": "PCIE_DBGVECB29", + "TRNTD86": "PCIE_TRNTD86", + "TRNRD9": "PCIE_TRNRD9", + "PIPERX2DATA11": "PCIE_PIPERX2DATA11", + "TL2ERRHDR25": "PCIE_TL2ERRHDR25", + "DBGVECA40": "PCIE_DBGVECA40", + "MIMTXRDATA44": "PCIE_MIMTXRDATA44", + "PIPERX6DATA15": "PCIE_PIPERX6DATA15", + "TRNRD126": "PCIE_TRNRD126", + "PIPERX7CHARISK0": "PCIE_PIPERX7CHARISK0", + "PIPETX6DATA8": "PCIE_PIPETX6DATA8", + "PLDIRECTEDLTSSMNEW1": "PCIE_PLDIRECTEDLTSSMNEW1", + "MIMRXRDATA18": "PCIE_MIMRXRDATA18", + "TRNRD12": "PCIE_TRNRD12", + "CFGERRTLPCPLHEADER4": "PCIE_CFGERRTLPCPLHEADER4", + "PIPETX2POWERDOWN0": "PCIE_PIPETX2POWERDOWN0", + "MIMTXWDATA56": "PCIE_MIMTXWDATA56", + "TRNTD70": "PCIE_TRNTD70", + "TRNRD77": "PCIE_TRNRD77", + "TRNFCNPH2": "PCIE_TRNFCNPH2", + "CFGAERINTERRUPTMSGNUM0": "PCIE_CFGAERINTERRUPTMSGNUM0", + "TRNRDLLPDATA39": "PCIE_TRNRDLLPDATA39", + "TRNTDLLPDATA6": "PCIE_TRNTDLLPDATA6", + "PIPETX5DATA2": "PCIE_PIPETX5DATA2", + "TRNTD18": "PCIE_TRNTD18", + "TL2ERRHDR32": "PCIE_TL2ERRHDR32", + "CFGLINKCONTROLHWAUTOWIDTHDIS": "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", + "CFGMGMTDO18": "PCIE_CFGMGMTDO18", + "MIMTXWADDR0": "PCIE_MIMTXWADDR0", + "TRNTD56": "PCIE_TRNTD56", + "CFGERRAERHEADERLOG103": "PCIE_CFGERRAERHEADERLOG103", + "MIMRXRADDR1": "PCIE_MIMRXRADDR1", + "PLLINKGEN2CAP": "PCIE_PLLINKGEN2CAP", + "PIPERX2DATA0": "PCIE_PIPERX2DATA0", + "PL2L0REQ": "PCIE_PL2L0REQ", + "MIMRXRADDR12": "PCIE_MIMRXRADDR12", + "CFGMSGRECEIVEDDEASSERTINTD": "PCIE_CFGMSGRECEIVEDDEASSERTINTD", + "CFGERRTLPCPLHEADER32": "PCIE_CFGERRTLPCPLHEADER32", + "PIPERX0PHYSTATUS": "PCIE_PIPERX0PHYSTATUS", + "TRNFCPD0": "PCIE_TRNFCPD0", + "CFGDSN19": "PCIE_CFGDSN19", + "TRNTREM0": "PCIE_TRNTREM0", + "CFGMGMTDI25": "PCIE_CFGMGMTDI25", + "TRNTD46": "PCIE_TRNTD46", + "TRNTD54": "PCIE_TRNTD54", + "CFGERRAERHEADERLOG29": "PCIE_CFGERRAERHEADERLOG29", + "MIMTXWDATA18": "PCIE_MIMTXWDATA18", + "TRNTDLLPDATA29": "PCIE_TRNTDLLPDATA29", + "PIPERX4STATUS1": "PCIE_PIPERX4STATUS1", + "CFGPMWAKEN": "PCIE_CFGPMWAKEN", + "PIPETX2DATA10": "PCIE_PIPETX2DATA10", + "CFGPCIECAPINTERRUPTMSGNUM2": "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", + "CFGSUBSYSVENDID14": "PCIE_CFGSUBSYSVENDID14", + "CFGMGMTDO5": "PCIE_CFGMGMTDO5", + "CFGDSN31": "PCIE_CFGDSN31", + "CFGDSN39": "PCIE_CFGDSN39", + "PIPERX5POLARITY": "PCIE_PIPERX5POLARITY", + "PLDBGMODE0": "PCIE_PLDBGMODE0", + "TRNTD85": "PCIE_TRNTD85", + "TRNFCNPD3": "PCIE_TRNFCNPD3", + "DBGVECA41": "PCIE_DBGVECA41", + "CFGINTERRUPTMSIXFM": "PCIE_CFGINTERRUPTMSIXFM", + "TL2ERRHDR29": "PCIE_TL2ERRHDR29", + "TRNRDLLPDATA50": "PCIE_TRNRDLLPDATA50", + "MIMTXRADDR8": "PCIE_MIMTXRADDR8", + "CFGMGMTBYTEENN0": "PCIE_CFGMGMTBYTEENN0", + "TRNRD67": "PCIE_TRNRD67", + "MIMRXRDATA12": "PCIE_MIMRXRDATA12", + "TL2ERRHDR43": "PCIE_TL2ERRHDR43", + "TL2ERRHDR19": "PCIE_TL2ERRHDR19", + "TRNRDLLPDATA36": "PCIE_TRNRDLLPDATA36", + "PIPERX5DATA3": "PCIE_PIPERX5DATA3", + "PIPETX7DATA0": "PCIE_PIPETX7DATA0", + "MIMTXRDATA29": "PCIE_MIMTXRDATA29", + "CFGERRAERHEADERLOG126": "PCIE_CFGERRAERHEADERLOG126", + "CFGPMTURNOFFOKN": "PCIE_CFGPMTURNOFFOKN", + "DBGMODE1": "PCIE_DBGMODE1", + "MIMTXRDATA5": "PCIE_MIMTXRDATA5", + "XILUNCONNOUT19": "PCIE_XILUNCONNOUT19", + "LL2LINKSTATUS3": "PCIE_LL2LINKSTATUS3", + "MIMTXRADDR6": "PCIE_MIMTXRADDR6", + "TRNRD15": "PCIE_TRNRD15", + "MIMRXRADDR5": "PCIE_MIMRXRADDR5", + "PIPETX6DATA7": "PCIE_PIPETX6DATA7", + "PIPETXMARGIN1": "PCIE_PIPETXMARGIN1", + "DBGVECB8": "PCIE_DBGVECB8", + "MIMTXWDATA32": "PCIE_MIMTXWDATA32", + "CFGVENDID8": "PCIE_CFGVENDID8", + "CFGINTERRUPTDI6": "PCIE_CFGINTERRUPTDI6", + "CFGSUBSYSVENDID10": "PCIE_CFGSUBSYSVENDID10", + "CFGERRAERHEADERLOG40": "PCIE_CFGERRAERHEADERLOG40", + "MIMRXWDATA21": "PCIE_MIMRXWDATA21", + "CFGVENDID14": "PCIE_CFGVENDID14", + "PIPERX4DATA0": "PCIE_PIPERX4DATA0", + "MIMTXWDATA63": "PCIE_MIMTXWDATA63", + "TRNRDLLPDATA11": "PCIE_TRNRDLLPDATA11", + "TRNTCFGGNT": "PCIE_TRNTCFGGNT", + "MIMRXWDATA31": "PCIE_MIMRXWDATA31", + "TRNTD115": "PCIE_TRNTD115", + "DBGVECA50": "PCIE_DBGVECA50", + "CFGERRMALFORMEDN": "PCIE_CFGERRMALFORMEDN", + "MIMTXWDATA55": "PCIE_MIMTXWDATA55", + "TRNRD6": "PCIE_TRNRD6", + "PL2DIRECTEDLSTATE3": "PCIE_PL2DIRECTEDLSTATE3", + "TRNFCCPLD5": "PCIE_TRNFCCPLD5", + "EDTSINGLEBYPASSCHAIN": "PCIE_EDTSINGLEBYPASSCHAIN", + "CFGERRAERHEADERLOG119": "PCIE_CFGERRAERHEADERLOG119", + "DBGVECB54": "PCIE_DBGVECB54", + "TRNRD99": "PCIE_TRNRD99", + "MIMRXRADDR2": "PCIE_MIMRXRADDR2", + "TRNRD59": "PCIE_TRNRD59", + "CFGERRAERHEADERLOG107": "PCIE_CFGERRAERHEADERLOG107", + "PIPETX5DATA4": "PCIE_PIPETX5DATA4", + "TRNRDLLPDATA59": "PCIE_TRNRDLLPDATA59", + "PIPERX3DATA11": "PCIE_PIPERX3DATA11", + "MIMRXRDATA8": "PCIE_MIMRXRDATA8", + "PIPETX6DATA15": "PCIE_PIPETX6DATA15", + "TRNTD58": "PCIE_TRNTD58", + "PIPERX5DATA8": "PCIE_PIPERX5DATA8", + "CFGMGMTDI16": "PCIE_CFGMGMTDI16", + "CFGMSGRECEIVEDSETSLOTPOWERLIMIT": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", + "TRNRD87": "PCIE_TRNRD87", + "CFGERRTLPCPLHEADER10": "PCIE_CFGERRTLPCPLHEADER10", + "PIPETX6DATA9": "PCIE_PIPETX6DATA9", + "CFGCOMMANDBUSMASTERENABLE": "PCIE_CFGCOMMANDBUSMASTERENABLE", + "TRNTDLLPDATA22": "PCIE_TRNTDLLPDATA22", + "TRNTD53": "PCIE_TRNTD53", + "CFGSLOTCONTROLELECTROMECHILCTLPULSE": "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", + "PIPERX4DATA3": "PCIE_PIPERX4DATA3", + "CFGSUBSYSID1": "PCIE_CFGSUBSYSID1", + "DBGVECB6": "PCIE_DBGVECB6", + "TL2ERRHDR36": "PCIE_TL2ERRHDR36", + "TRNRDLLPDATA10": "PCIE_TRNRDLLPDATA10", + "XILUNCONNOUT24": "PCIE_XILUNCONNOUT24", + "CFGERRTLPCPLHEADER39": "PCIE_CFGERRTLPCPLHEADER39", + "TRNRD31": "PCIE_TRNRD31", + "PIPERX1DATA0": "PCIE_PIPERX1DATA0", + "CFGERRTLPCPLHEADER24": "PCIE_CFGERRTLPCPLHEADER24", + "TRNRBARHIT1": "PCIE_TRNRBARHIT1", + "PLDBGVEC1": "PCIE_PLDBGVEC1", + "DBGVECA57": "PCIE_DBGVECA57", + "MIMRXWDATA40": "PCIE_MIMRXWDATA40", + "PIPERX1STATUS1": "PCIE_PIPERX1STATUS1", + "CFGMGMTDI1": "PCIE_CFGMGMTDI1", + "PIPERX6PHYSTATUS": "PCIE_PIPERX6PHYSTATUS", + "PIPERX1STATUS2": "PCIE_PIPERX1STATUS2", + "PIPERX4DATA13": "PCIE_PIPERX4DATA13", + "MIMRXRDATA37": "PCIE_MIMRXRDATA37", + "CFGINTERRUPTMMENABLE1": "PCIE_CFGINTERRUPTMMENABLE1", + "PIPETX3DATA0": "PCIE_PIPETX3DATA0", + "TRNTD31": "PCIE_TRNTD31", + "TRNFCPH3": "PCIE_TRNFCPH3", + "PIPERX4DATA1": "PCIE_PIPERX4DATA1", + "TRNRD95": "PCIE_TRNRD95", + "CFGDSN27": "PCIE_CFGDSN27", + "MIMTXWDATA37": "PCIE_MIMTXWDATA37", + "MIMRXRDATA48": "PCIE_MIMRXRDATA48", + "CFGMGMTDWADDR7": "PCIE_CFGMGMTDWADDR7", + "TRNRD46": "PCIE_TRNRD46", + "DBGVECB33": "PCIE_DBGVECB33", + "MIMRXWDATA64": "PCIE_MIMRXWDATA64", + "TRNTD28": "PCIE_TRNTD28", + "CFGMGMTDI27": "PCIE_CFGMGMTDI27", + "DBGVECB43": "PCIE_DBGVECB43", + "TRNFCCPLD2": "PCIE_TRNFCCPLD2", + "MIMTXRDATA41": "PCIE_MIMTXRDATA41", + "MIMRXRADDR6": "PCIE_MIMRXRADDR6", + "PIPERX5PHYSTATUS": "PCIE_PIPERX5PHYSTATUS", + "MIMRXWDATA53": "PCIE_MIMRXWDATA53", + "CFGMGMTDI4": "PCIE_CFGMGMTDI4", + "CFGMGMTDO1": "PCIE_CFGMGMTDO1", + "PMVOUT": "PCIE_PMVOUT", + "PIPERX7DATA14": "PCIE_PIPERX7DATA14", + "TRNFCPD10": "PCIE_TRNFCPD10", + "MIMRXWADDR8": "PCIE_MIMRXWADDR8", + "CFGDEVID7": "PCIE_CFGDEVID7", + "MIMTXWDATA7": "PCIE_MIMTXWDATA7", + "LL2SUSPENDNOW": "PCIE_LL2SUSPENDNOW", + "TL2ERRHDR37": "PCIE_TL2ERRHDR37", + "XILUNCONNOUT3": "PCIE_XILUNCONNOUT3", + "CFGREVID4": "PCIE_CFGREVID4", + "PIPETX4DATA12": "PCIE_PIPETX4DATA12", + "TRNTD57": "PCIE_TRNTD57", + "PIPERX3PHYSTATUS": "PCIE_PIPERX3PHYSTATUS", + "TRNRDLLPDATA5": "PCIE_TRNRDLLPDATA5", + "DBGVECB0": "PCIE_DBGVECB0", + "PIPERX3DATA9": "PCIE_PIPERX3DATA9", + "PIPETX7CHARISK0": "PCIE_PIPETX7CHARISK0", + "PIPETX7DATA2": "PCIE_PIPETX7DATA2", + "CFGERRURN": "PCIE_CFGERRURN", + "CFGVENDID3": "PCIE_CFGVENDID3", + "PLDBGVEC7": "PCIE_PLDBGVEC7", + "CFGMSGRECEIVEDPMETO": "PCIE_CFGMSGRECEIVEDPMETO", + "DBGVECB4": "PCIE_DBGVECB4", + "TRNTD97": "PCIE_TRNTD97", + "DBGVECC0": "PCIE_DBGVECC0", + "TRNTD33": "PCIE_TRNTD33", + "CFGAERINTERRUPTMSGNUM4": "PCIE_CFGAERINTERRUPTMSGNUM4", + "CFGERRTLPCPLHEADER18": "PCIE_CFGERRTLPCPLHEADER18", + "PIPETX7DATA5": "PCIE_PIPETX7DATA5", + "TRNRDLLPSRCRDY0": "PCIE_TRNRDLLPSRCRDY0", + "TRNRD117": "PCIE_TRNRD117", + "TRNRDLLPDATA47": "PCIE_TRNRDLLPDATA47", + "TL2ERRHDR41": "PCIE_TL2ERRHDR41", + "PIPETX5DATA6": "PCIE_PIPETX5DATA6", + "MIMTXWDATA30": "PCIE_MIMTXWDATA30", + "DBGVECA4": "PCIE_DBGVECA4", + "CFGERRAERHEADERLOG11": "PCIE_CFGERRAERHEADERLOG11", + "CFGDSN41": "PCIE_CFGDSN41", + "MIMTXWDATA19": "PCIE_MIMTXWDATA19", + "TRNRDLLPDATA46": "PCIE_TRNRDLLPDATA46", + "TRNFCNPH3": "PCIE_TRNFCNPH3", + "XILUNCONNOUT27": "PCIE_XILUNCONNOUT27", + "XILUNCONNOUT7": "PCIE_XILUNCONNOUT7", + "PIPERX6DATA3": "PCIE_PIPERX6DATA3", + "MIMRXRDATA17": "PCIE_MIMRXRDATA17", + "TRNTD14": "PCIE_TRNTD14", + "TRNTD30": "PCIE_TRNTD30", + "PIPETX1DATA12": "PCIE_PIPETX1DATA12", + "TRNTD39": "PCIE_TRNTD39", + "DBGVECB23": "PCIE_DBGVECB23", + "PLDIRECTEDLTSSMNEW0": "PCIE_PLDIRECTEDLTSSMNEW0", + "PIPETX2DATA5": "PCIE_PIPETX2DATA5", + "PIPETX0DATA10": "PCIE_PIPETX0DATA10", + "MIMTXWDATA42": "PCIE_MIMTXWDATA42", + "CFGMSGRECEIVEDPMETOACK": "PCIE_CFGMSGRECEIVEDPMETOACK", + "PIPERX1DATA10": "PCIE_PIPERX1DATA10", + "MIMTXRDATA6": "PCIE_MIMTXRDATA6", + "CFGMGMTBYTEENN3": "PCIE_CFGMGMTBYTEENN3", + "PIPERX1DATA3": "PCIE_PIPERX1DATA3", + "PLSELLNKWIDTH1": "PCIE_PLSELLNKWIDTH1", + "PLINITIALLINKWIDTH0": "PCIE_PLINITIALLINKWIDTH0", + "TRNTD110": "PCIE_TRNTD110", + "TL2ERRHDR8": "PCIE_TL2ERRHDR8", + "CFGMGMTDI23": "PCIE_CFGMGMTDI23", + "PIPERX6POLARITY": "PCIE_PIPERX6POLARITY", + "MIMRXWDATA12": "PCIE_MIMRXWDATA12", + "MIMTXWDATA3": "PCIE_MIMTXWDATA3", + "USERCLK": "PCIE_USERCLK", + "CFGERRAERHEADERLOG69": "PCIE_CFGERRAERHEADERLOG69", + "EDTCHANNELSIN5": "PCIE_EDTCHANNELSIN5", + "CFGMGMTBYTEENN2": "PCIE_CFGMGMTBYTEENN2", + "DBGVECB56": "PCIE_DBGVECB56", + "CFGDEVCONTROLAUXPOWEREN": "PCIE_CFGDEVCONTROLAUXPOWEREN", + "MIMTXWDATA61": "PCIE_MIMTXWDATA61", + "TRNRDLLPDATA3": "PCIE_TRNRDLLPDATA3", + "TRNRD82": "PCIE_TRNRD82", + "CFGSUBSYSID7": "PCIE_CFGSUBSYSID7", + "DBGVECA17": "PCIE_DBGVECA17", + "TL2PPMSUSPENDOK": "PCIE_TL2PPMSUSPENDOK", + "MIMTXRDATA30": "PCIE_MIMTXRDATA30", + "CFGMGMTDI29": "PCIE_CFGMGMTDI29", + "CFGAERECRCCHECKEN": "PCIE_CFGAERECRCCHECKEN", + "TRNRD29": "PCIE_TRNRD29", + "DBGVECA22": "PCIE_DBGVECA22", + "CFGERRINTERNALUNCORN": "PCIE_CFGERRINTERNALUNCORN", + "CFGERRAERHEADERLOG32": "PCIE_CFGERRAERHEADERLOG32", + "TRNRD35": "PCIE_TRNRD35", + "MIMRXRDATA4": "PCIE_MIMRXRDATA4", + "MIMTXRDATA7": "PCIE_MIMTXRDATA7", + "PIPETXDEEMPH": "PCIE_PIPETXDEEMPH", + "TRNTD100": "PCIE_TRNTD100", + "MIMTXRDATA23": "PCIE_MIMTXRDATA23", + "MIMRXRDATA2": "PCIE_MIMRXRDATA2", + "XILUNCONNOUT8": "PCIE_XILUNCONNOUT8", + "TRNFCPD6": "PCIE_TRNFCPD6", + "PIPETX4ELECIDLE": "PCIE_PIPETX4ELECIDLE", + "TRNTBUFAV0": "PCIE_TRNTBUFAV0", + "FUNCLVLRSTN": "PCIE_FUNCLVLRSTN", + "PIPETX4DATA5": "PCIE_PIPETX4DATA5", + "MIMTXRDATA53": "PCIE_MIMTXRDATA53", + "MIMTXRDATA62": "PCIE_MIMTXRDATA62", + "PIPERX3STATUS1": "PCIE_PIPERX3STATUS1", + "MIMRXRADDR8": "PCIE_MIMRXRADDR8", + "DBGVECA0": "PCIE_DBGVECA0", + "MIMRXWDATA13": "PCIE_MIMRXWDATA13", + "PLLANEREVERSALMODE1": "PCIE_PLLANEREVERSALMODE1", + "PIPETX3ELECIDLE": "PCIE_PIPETX3ELECIDLE", + "LL2TFCINIT2SEQ": "PCIE_LL2TFCINIT2SEQ", + "CFGAERROOTERRFATALERRRECEIVED": "PCIE_CFGAERROOTERRFATALERRRECEIVED", + "MIMRXRDATA63": "PCIE_MIMRXRDATA63", + "PIPETX2DATA15": "PCIE_PIPETX2DATA15", + "MIMRXWDATA45": "PCIE_MIMRXWDATA45", + "PIPERX2STATUS0": "PCIE_PIPERX2STATUS0", + "TRNRD65": "PCIE_TRNRD65", + "TRNTD40": "PCIE_TRNTD40", + "DBGVECA55": "PCIE_DBGVECA55", + "DBGVECB46": "PCIE_DBGVECB46", + "CFGDEVCONTROLFATALERRREPORTINGEN": "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", + "MIMRXWDATA9": "PCIE_MIMRXWDATA9", + "CFGDSN58": "PCIE_CFGDSN58", + "TRNRD58": "PCIE_TRNRD58", + "PIPETX0POWERDOWN1": "PCIE_PIPETX0POWERDOWN1", + "TL2ERRHDR10": "PCIE_TL2ERRHDR10", + "MIMRXRDATA14": "PCIE_MIMRXRDATA14", + "MIMTXWDATA66": "PCIE_MIMTXWDATA66", + "CFGMGMTDI2": "PCIE_CFGMGMTDI2", + "TRNRD93": "PCIE_TRNRD93", + "CFGERRAERHEADERLOG39": "PCIE_CFGERRAERHEADERLOG39", + "CFGMSGDATA1": "PCIE_CFGMSGDATA1", + "PIPETX1DATA14": "PCIE_PIPETX1DATA14", + "TRNTDLLPDATA15": "PCIE_TRNTDLLPDATA15", + "DRPDI14": "PCIE_DRPDI14", + "PIPETX3DATA3": "PCIE_PIPETX3DATA3", + "CFGERRAERHEADERLOG4": "PCIE_CFGERRAERHEADERLOG4", + "CFGTRANSACTIONADDR6": "PCIE_CFGTRANSACTIONADDR6", + "TRNFCPH7": "PCIE_TRNFCPH7", + "TL2ERRHDR3": "PCIE_TL2ERRHDR3", + "CFGERRAERHEADERLOG127": "PCIE_CFGERRAERHEADERLOG127", + "MIMRXRDATA45": "PCIE_MIMRXRDATA45", + "MIMTXRDATA36": "PCIE_MIMTXRDATA36", + "PLDIRECTEDLINKWIDTH1": "PCIE_PLDIRECTEDLINKWIDTH1", + "CFGDSN16": "PCIE_CFGDSN16", + "PIPETX6POWERDOWN0": "PCIE_PIPETX6POWERDOWN0", + "CFGLINKCONTROLCOMMONCLOCK": "PCIE_CFGLINKCONTROLCOMMONCLOCK", + "MIMRXWDATA3": "PCIE_MIMRXWDATA3", + "MIMTXWDATA24": "PCIE_MIMTXWDATA24", + "TRNTD96": "PCIE_TRNTD96", + "TRNTD5": "PCIE_TRNTD5", + "DBGVECB49": "PCIE_DBGVECB49", + "TRNTD37": "PCIE_TRNTD37", + "PIPERX6DATA11": "PCIE_PIPERX6DATA11", + "PLDIRECTEDCHANGEDONE": "PCIE_PLDIRECTEDCHANGEDONE", + "MIMTXRDATA22": "PCIE_MIMTXRDATA22", + "CFGDSN14": "PCIE_CFGDSN14", + "DBGVECA59": "PCIE_DBGVECA59", + "PL2RXELECIDLE": "PCIE_PL2RXELECIDLE", + "TRNTDLLPDATA13": "PCIE_TRNTDLLPDATA13", + "MIMTXRDATA65": "PCIE_MIMTXRDATA65", + "MIMRXWDATA38": "PCIE_MIMRXWDATA38", + "TL2ERRHDR5": "PCIE_TL2ERRHDR5", + "CFGDSN26": "PCIE_CFGDSN26", + "TRNFCNPD9": "PCIE_TRNFCNPD9", + "PIPETX5POWERDOWN1": "PCIE_PIPETX5POWERDOWN1", + "PIPERX4CHARISK1": "PCIE_PIPERX4CHARISK1", + "DRPDO3": "PCIE_DRPDO3", + "CFGVENDID10": "PCIE_CFGVENDID10", + "CFGAERROOTERRNONFATALERRREPORTINGEN": "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", + "CFGDSN36": "PCIE_CFGDSN36", + "CFGERRAERHEADERLOG8": "PCIE_CFGERRAERHEADERLOG8", + "CFGERRAERHEADERLOG117": "PCIE_CFGERRAERHEADERLOG117", + "MIMTXRDATA33": "PCIE_MIMTXRDATA33", + "TRNRD26": "PCIE_TRNRD26", + "PIPERX0DATA8": "PCIE_PIPERX0DATA8", + "PIPETX0DATA1": "PCIE_PIPETX0DATA1", + "CFGDEVID8": "PCIE_CFGDEVID8", + "CFGPCIECAPINTERRUPTMSGNUM1": "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", + "EDTCHANNELSOUT1": "PCIE_EDTCHANNELSOUT1", + "CFGERRAERHEADERLOG50": "PCIE_CFGERRAERHEADERLOG50", + "TRNRD21": "PCIE_TRNRD21", + "CFGERRAERHEADERLOG122": "PCIE_CFGERRAERHEADERLOG122", + "DBGVECC4": "PCIE_DBGVECC4", + "TRNFCPH6": "PCIE_TRNFCPH6", + "TRNFCPD7": "PCIE_TRNFCPD7", + "PIPERX0CHANISALIGNED": "PCIE_PIPERX0CHANISALIGNED", + "PLDBGVEC0": "PCIE_PLDBGVEC0", + "CFGSUBSYSVENDID2": "PCIE_CFGSUBSYSVENDID2", + "CFGMGMTDO3": "PCIE_CFGMGMTDO3", + "DBGVECB19": "PCIE_DBGVECB19", + "TRNRD121": "PCIE_TRNRD121", + "DRPADDR8": "PCIE_DRPADDR8", + "CFGDEVID1": "PCIE_CFGDEVID1", + "MIMTXWDATA2": "PCIE_MIMTXWDATA2", + "MIMRXWDATA55": "PCIE_MIMRXWDATA55", + "PIPERX7CHANISALIGNED": "PCIE_PIPERX7CHANISALIGNED", + "PIPETX6DATA10": "PCIE_PIPETX6DATA10", + "CFGREVID6": "PCIE_CFGREVID6", + "CFGERRAERHEADERLOG89": "PCIE_CFGERRAERHEADERLOG89", + "PIPETX2COMPLIANCE": "PCIE_PIPETX2COMPLIANCE", + "MIMTXRDATA21": "PCIE_MIMTXRDATA21", + "TRNRD107": "PCIE_TRNRD107", + "MIMTXWADDR2": "PCIE_MIMTXWADDR2", + "DBGVECA58": "PCIE_DBGVECA58", + "CFGFORCECOMMONCLOCKOFF": "PCIE_CFGFORCECOMMONCLOCKOFF", + "TLRSTN": "PCIE_TLRSTN", + "PIPERX3DATA0": "PCIE_PIPERX3DATA0", + "CFGAERINTERRUPTMSGNUM2": "PCIE_CFGAERINTERRUPTMSGNUM2", + "CFGDSBUSNUMBER1": "PCIE_CFGDSBUSNUMBER1", + "MIMTXWDATA12": "PCIE_MIMTXWDATA12", + "MIMTXWDATA48": "PCIE_MIMTXWDATA48", + "PIPETX1DATA13": "PCIE_PIPETX1DATA13", + "EDTCHANNELSOUT8": "PCIE_EDTCHANNELSOUT8", + "TRNTD79": "PCIE_TRNTD79", + "PIPETX0DATA7": "PCIE_PIPETX0DATA7", + "DRPDI7": "PCIE_DRPDI7", + "DRPDI6": "PCIE_DRPDI6", + "DBGSCLRI": "PCIE_DBGSCLRI", + "TRNTD22": "PCIE_TRNTD22", + "CFGDEVCONTROL2CPLTIMEOUTVAL1": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "CFGPCIECAPINTERRUPTMSGNUM0": "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", + "TRNFCCPLD0": "PCIE_TRNFCCPLD0", + "PIPERX7DATA12": "PCIE_PIPERX7DATA12", + "TRNTDLLPDATA8": "PCIE_TRNTDLLPDATA8", + "CFGERRAERHEADERLOG62": "PCIE_CFGERRAERHEADERLOG62", + "XILUNCONNOUT2": "PCIE_XILUNCONNOUT2", + "DRPWE": "PCIE_DRPWE", + "CFGDEVCONTROLENABLERO": "PCIE_CFGDEVCONTROLENABLERO", + "MIMRXWDATA39": "PCIE_MIMRXWDATA39", + "CFGMSGDATA0": "PCIE_CFGMSGDATA0", + "TL2ERRHDR63": "PCIE_TL2ERRHDR63", + "MIMTXWDATA8": "PCIE_MIMTXWDATA8", + "TRNTDLLPDATA7": "PCIE_TRNTDLLPDATA7", + "CFGPCIELINKSTATE0": "PCIE_CFGPCIELINKSTATE0", + "MIMRXRDATA31": "PCIE_MIMRXRDATA31", + "XILUNCONNOUT31": "PCIE_XILUNCONNOUT31", + "DBGVECB59": "PCIE_DBGVECB59", + "TRNRD69": "PCIE_TRNRD69", + "CFGINTERRUPTASSERTN": "PCIE_CFGINTERRUPTASSERTN", + "CFGDEVCONTROL2CPLTIMEOUTDIS": "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", + "MIMRXRDATA15": "PCIE_MIMRXRDATA15", + "CFGFORCEMPS2": "PCIE_CFGFORCEMPS2", + "PIPERX4DATA11": "PCIE_PIPERX4DATA11", + "MIMRXRDATA25": "PCIE_MIMRXRDATA25", + "TRNTD45": "PCIE_TRNTD45", + "PIPERX1CHARISK0": "PCIE_PIPERX1CHARISK0", + "PIPERX0DATA3": "PCIE_PIPERX0DATA3", + "PIPERX6DATA7": "PCIE_PIPERX6DATA7", + "TRNRD54": "PCIE_TRNRD54", + "XILUNCONNOUT13": "PCIE_XILUNCONNOUT13", + "CFGPORTNUMBER4": "PCIE_CFGPORTNUMBER4", + "PIPETX7DATA4": "PCIE_PIPETX7DATA4", + "PIPETX4DATA13": "PCIE_PIPETX4DATA13", + "MIMTXWDATA1": "PCIE_MIMTXWDATA1", + "CFGMGMTDI15": "PCIE_CFGMGMTDI15", + "CFGERRAERHEADERLOG67": "PCIE_CFGERRAERHEADERLOG67", + "TRNRDLLPDATA26": "PCIE_TRNRDLLPDATA26", + "TRNRDLLPDATA16": "PCIE_TRNRDLLPDATA16", + "TL2ERRHDR2": "PCIE_TL2ERRHDR2", + "MIMTXWDATA17": "PCIE_MIMTXWDATA17", + "TRNRDLLPDATA6": "PCIE_TRNRDLLPDATA6", + "TRNRD90": "PCIE_TRNRD90", + "PIPERX4DATA4": "PCIE_PIPERX4DATA4", + "DRPDO11": "PCIE_DRPDO11", + "PIPERX5DATA11": "PCIE_PIPERX5DATA11", + "MIMTXWDATA49": "PCIE_MIMTXWDATA49", + "DRPDI3": "PCIE_DRPDI3", + "CFGSUBSYSID12": "PCIE_CFGSUBSYSID12", + "DBGVECA47": "PCIE_DBGVECA47", + "CFGMSGDATA2": "PCIE_CFGMSGDATA2", + "CFGSUBSYSVENDID0": "PCIE_CFGSUBSYSVENDID0", + "MIMRXWDATA47": "PCIE_MIMRXWDATA47", + "MIMRXWDATA4": "PCIE_MIMRXWDATA4", + "MIMTXWADDR7": "PCIE_MIMTXWADDR7", + "PIPETX7DATA11": "PCIE_PIPETX7DATA11", + "TRNFCNPD6": "PCIE_TRNFCNPD6", + "PIPERX2DATA3": "PCIE_PIPERX2DATA3", + "TRNRDLLPDATA25": "PCIE_TRNRDLLPDATA25", + "CFGERRTLPCPLHEADER28": "PCIE_CFGERRTLPCPLHEADER28", + "PIPETX0DATA5": "PCIE_PIPETX0DATA5", + "CFGERRAERHEADERLOG121": "PCIE_CFGERRAERHEADERLOG121", + "TL2ERRRXOVERFLOW": "PCIE_TL2ERRRXOVERFLOW", + "CFGDSN4": "PCIE_CFGDSN4", + "TRNTDLLPDATA21": "PCIE_TRNTDLLPDATA21", + "MIMTXRDATA17": "PCIE_MIMTXRDATA17", + "CFGFORCEMPS0": "PCIE_CFGFORCEMPS0", + "CFGTRANSACTIONADDR0": "PCIE_CFGTRANSACTIONADDR0", + "TRNRNPOK": "PCIE_TRNRNPOK", + "CFGERRTLPCPLHEADER21": "PCIE_CFGERRTLPCPLHEADER21", + "TRNFCNPD0": "PCIE_TRNFCNPD0", + "PIPETX5DATA7": "PCIE_PIPETX5DATA7", + "PIPERX5CHARISK1": "PCIE_PIPERX5CHARISK1", + "CFGSUBSYSID9": "PCIE_CFGSUBSYSID9", + "TRNTD72": "PCIE_TRNTD72", + "TRNRDLLPDATA38": "PCIE_TRNRDLLPDATA38", + "PIPERX0DATA7": "PCIE_PIPERX0DATA7", + "PIPETX0CHARISK0": "PCIE_PIPETX0CHARISK0", + "MIMRXWDATA67": "PCIE_MIMRXWDATA67", + "TRNTD118": "PCIE_TRNTD118", + "TRNTD51": "PCIE_TRNTD51", + "EDTCHANNELSIN2": "PCIE_EDTCHANNELSIN2", + "PIPERX3DATA7": "PCIE_PIPERX3DATA7", + "EDTCHANNELSIN1": "PCIE_EDTCHANNELSIN1", + "TRNRD115": "PCIE_TRNRD115", + "CFGERRAERHEADERLOG15": "PCIE_CFGERRAERHEADERLOG15", + "EDTCONFIGURATION": "PCIE_EDTCONFIGURATION", + "CFGMSGRECEIVED": "PCIE_CFGMSGRECEIVED", + "CFGERRTLPCPLHEADER26": "PCIE_CFGERRTLPCPLHEADER26", + "CFGERRAERHEADERLOG16": "PCIE_CFGERRAERHEADERLOG16", + "MIMTXWDATA43": "PCIE_MIMTXWDATA43", + "TRNTD34": "PCIE_TRNTD34", + "PLSELLNKWIDTH0": "PCIE_PLSELLNKWIDTH0", + "PIPERX3ELECIDLE": "PCIE_PIPERX3ELECIDLE", + "CFGDEVID10": "PCIE_CFGDEVID10", + "TRNTD80": "PCIE_TRNTD80", + "CFGDSN52": "PCIE_CFGDSN52", + "TRNRBARHIT4": "PCIE_TRNRBARHIT4", + "MIMRXRDATA49": "PCIE_MIMRXRDATA49", + "MIMRXWDATA24": "PCIE_MIMRXWDATA24", + "MIMTXWDATA33": "PCIE_MIMTXWDATA33", + "TL2ERRHDR53": "PCIE_TL2ERRHDR53", + "TRNRDLLPDATA18": "PCIE_TRNRDLLPDATA18", + "TRNTD71": "PCIE_TRNTD71", + "CFGERRAERHEADERLOG120": "PCIE_CFGERRAERHEADERLOG120", + "PIPERX1PHYSTATUS": "PCIE_PIPERX1PHYSTATUS", + "TRNRDLLPSRCRDY1": "PCIE_TRNRDLLPSRCRDY1", + "CFGDSN2": "PCIE_CFGDSN2", + "PIPERX1DATA14": "PCIE_PIPERX1DATA14", + "TRNRDLLPDATA1": "PCIE_TRNRDLLPDATA1", + "CFGERRAERHEADERLOG70": "PCIE_CFGERRAERHEADERLOG70", + "CFGSUBSYSVENDID9": "PCIE_CFGSUBSYSVENDID9", + "PIPERX0DATA13": "PCIE_PIPERX0DATA13", + "CFGSUBSYSID6": "PCIE_CFGSUBSYSID6", + "TRNRDLLPDATA20": "PCIE_TRNRDLLPDATA20", + "XILUNCONNOUT39": "PCIE_XILUNCONNOUT39", + "DBGVECC10": "PCIE_DBGVECC10", + "CFGERRAERHEADERLOG31": "PCIE_CFGERRAERHEADERLOG31", + "CFGERRTLPCPLHEADER36": "PCIE_CFGERRTLPCPLHEADER36", + "CFGMGMTDI8": "PCIE_CFGMGMTDI8", + "PIPETX2DATA4": "PCIE_PIPETX2DATA4", + "CFGDEVID11": "PCIE_CFGDEVID11", + "PIPERX7DATA5": "PCIE_PIPERX7DATA5", + "TRNTD2": "PCIE_TRNTD2", + "TRNRD43": "PCIE_TRNRD43", + "CFGERRAERHEADERLOG34": "PCIE_CFGERRAERHEADERLOG34", + "DBGVECA42": "PCIE_DBGVECA42", + "PLDIRECTEDLTSSMNEWVLD": "PCIE_PLDIRECTEDLTSSMNEWVLD", + "TRNTD75": "PCIE_TRNTD75", + "PIPERX3DATA14": "PCIE_PIPERX3DATA14", + "USERCLK2": "PCIE_USERCLK2", + "PIPERX7STATUS2": "PCIE_PIPERX7STATUS2", + "CFGLINKSTATUSNEGOTIATEDWIDTH1": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", + "CFGMGMTDO24": "PCIE_CFGMGMTDO24", + "CFGDSBUSNUMBER7": "PCIE_CFGDSBUSNUMBER7", + "MIMRXRDATA13": "PCIE_MIMRXRDATA13", + "TRNRD2": "PCIE_TRNRD2", + "PIPETX0DATA11": "PCIE_PIPETX0DATA11", + "PIPERX6DATA14": "PCIE_PIPERX6DATA14", + "CFGPCIECAPINTERRUPTMSGNUM4": "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", + "PIPERX0DATA1": "PCIE_PIPERX0DATA1", + "CFGDSN35": "PCIE_CFGDSN35", + "PIPETX3CHARISK0": "PCIE_PIPETX3CHARISK0", + "TRNFCPD8": "PCIE_TRNFCPD8", + "PIPERX3DATA6": "PCIE_PIPERX3DATA6", + "MIMRXRDATA53": "PCIE_MIMRXRDATA53", + "TRNTD94": "PCIE_TRNTD94", + "CFGERRAERHEADERLOG53": "PCIE_CFGERRAERHEADERLOG53", + "PIPERX5CHANISALIGNED": "PCIE_PIPERX5CHANISALIGNED", + "MIMRXREN": "PCIE_MIMRXREN", + "TRNRDLLPDATA42": "PCIE_TRNRDLLPDATA42", + "XILUNCONNOUT35": "PCIE_XILUNCONNOUT35", + "CFGMGMTDWADDR4": "PCIE_CFGMGMTDWADDR4", + "CFGREVID5": "PCIE_CFGREVID5", + "CFGERRAERHEADERLOG100": "PCIE_CFGERRAERHEADERLOG100", + "TRNRD20": "PCIE_TRNRD20", + "DBGSCLRA": "PCIE_DBGSCLRA", + "TRNRD86": "PCIE_TRNRD86", + "TRNTD106": "PCIE_TRNTD106", + "CFGERRTLPCPLHEADER1": "PCIE_CFGERRTLPCPLHEADER1", + "PIPETX0DATA8": "PCIE_PIPETX0DATA8", + "PMVSELECT2": "PCIE_PMVSELECT2", + "CFGSUBSYSVENDID3": "PCIE_CFGSUBSYSVENDID3", + "CFGDSN54": "PCIE_CFGDSN54", + "MIMRXRDATA41": "PCIE_MIMRXRDATA41", + "CFGROOTCONTROLSYSERRNONFATALERREN": "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", + "CFGERRAERHEADERLOG116": "PCIE_CFGERRAERHEADERLOG116", + "CFGERRTLPCPLHEADER19": "PCIE_CFGERRTLPCPLHEADER19", + "MIMTXWDATA9": "PCIE_MIMTXWDATA9", + "TRNRD73": "PCIE_TRNRD73", + "CFGERRAERHEADERLOG45": "PCIE_CFGERRAERHEADERLOG45", + "TRNTD59": "PCIE_TRNTD59", + "PLDIRECTEDLTSSMNEW5": "PCIE_PLDIRECTEDLTSSMNEW5", + "MIMRXRDATA52": "PCIE_MIMRXRDATA52", + "PIPERX7DATA0": "PCIE_PIPERX7DATA0", + "CFGMGMTDI28": "PCIE_CFGMGMTDI28", + "DBGSUBMODE": "PCIE_DBGSUBMODE", + "TRNRNPREQ": "PCIE_TRNRNPREQ", + "PIPERX3POLARITY": "PCIE_PIPERX3POLARITY", + "USERCLKPREBUF": "PCIE_USERCLKPREBUF", + "MIMTXRDATA56": "PCIE_MIMTXRDATA56", + "DBGSCLRE": "PCIE_DBGSCLRE", + "PIPECLK": "PCIE_PIPECLK", + "PLLTSSMSTATE0": "PCIE_PLLTSSMSTATE0", + "DBGVECA30": "PCIE_DBGVECA30", + "CFGTRANSACTIONADDR1": "PCIE_CFGTRANSACTIONADDR1", + "TRNRDLLPDATA27": "PCIE_TRNRDLLPDATA27", + "PIPERX5DATA14": "PCIE_PIPERX5DATA14", + "CFGERRAERHEADERLOG112": "PCIE_CFGERRAERHEADERLOG112", + "DBGVECB38": "PCIE_DBGVECB38", + "CFGMSGRECEIVEDERRNONFATAL": "PCIE_CFGMSGRECEIVEDERRNONFATAL", + "PIPERX2DATA8": "PCIE_PIPERX2DATA8", + "DBGVECA25": "PCIE_DBGVECA25", + "PLDBGVEC8": "PCIE_PLDBGVEC8", + "MIMRXRDATA56": "PCIE_MIMRXRDATA56", + "CFGERRAERHEADERLOG22": "PCIE_CFGERRAERHEADERLOG22", + "MIMRXWDATA18": "PCIE_MIMRXWDATA18", + "TRNTDSTRDY2": "PCIE_TRNTDSTRDY2", + "CFGDEVCONTROLEXTTAGEN": "PCIE_CFGDEVCONTROLEXTTAGEN", + "MIMRXWDATA65": "PCIE_MIMRXWDATA65", + "PIPETX5DATA15": "PCIE_PIPETX5DATA15", + "MIMRXWDATA27": "PCIE_MIMRXWDATA27", + "TRNTD9": "PCIE_TRNTD9", + "PIPETX1COMPLIANCE": "PCIE_PIPETX1COMPLIANCE", + "CFGERRAERHEADERLOGSETN": "PCIE_CFGERRAERHEADERLOGSETN", + "PIPETX4DATA4": "PCIE_PIPETX4DATA4", + "TRNFCNPH1": "PCIE_TRNFCNPH1", + "PLDIRECTEDLTSSMNEW3": "PCIE_PLDIRECTEDLTSSMNEW3", + "PIPERX7POLARITY": "PCIE_PIPERX7POLARITY", + "MIMTXRDATA42": "PCIE_MIMTXRDATA42", + "TRNRD120": "PCIE_TRNRD120", + "CFGERRAERHEADERLOG28": "PCIE_CFGERRAERHEADERLOG28", + "PIPETX3DATA1": "PCIE_PIPETX3DATA1", + "TRNTD61": "PCIE_TRNTD61", + "TRNRD41": "PCIE_TRNRD41", + "CFGSUBSYSVENDID5": "PCIE_CFGSUBSYSVENDID5", + "CFGDEVID9": "PCIE_CFGDEVID9", + "CFGPMCSRPMEEN": "PCIE_CFGPMCSRPMEEN", + "DBGVECB20": "PCIE_DBGVECB20", + "PIPERX6DATA12": "PCIE_PIPERX6DATA12", + "XILUNCONNOUT22": "PCIE_XILUNCONNOUT22", + "CFGMSGRECEIVEDASSERTINTC": "PCIE_CFGMSGRECEIVEDASSERTINTC", + "MIMTXRDATA15": "PCIE_MIMTXRDATA15", + "CFGERRAERHEADERLOG106": "PCIE_CFGERRAERHEADERLOG106", + "CFGERRAERHEADERLOG55": "PCIE_CFGERRAERHEADERLOG55", + "MIMRXRADDR3": "PCIE_MIMRXRADDR3", + "MIMRXWDATA42": "PCIE_MIMRXWDATA42", + "PIPERX5STATUS0": "PCIE_PIPERX5STATUS0", + "CFGPMSENDPMETON": "PCIE_CFGPMSENDPMETON", + "CFGMGMTDO7": "PCIE_CFGMGMTDO7", + "TRNTD41": "PCIE_TRNTD41", + "CFGERRAERHEADERLOG52": "PCIE_CFGERRAERHEADERLOG52", + "PIPETX3DATA8": "PCIE_PIPETX3DATA8", + "TRNRDLLPDATA60": "PCIE_TRNRDLLPDATA60", + "TRNRD34": "PCIE_TRNRD34", + "MIMTXWDATA5": "PCIE_MIMTXWDATA5", + "MIMTXRDATA25": "PCIE_MIMTXRDATA25", + "CFGDEVCONTROL2ATOMICREQUESTEREN": "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", + "MIMRXRDATA28": "PCIE_MIMRXRDATA28", + "CFGMSGDATA7": "PCIE_CFGMSGDATA7", + "CFGINTERRUPTSTATN": "PCIE_CFGINTERRUPTSTATN", + "MIMRXRADDR9": "PCIE_MIMRXRADDR9", + "CFGPORTNUMBER7": "PCIE_CFGPORTNUMBER7", + "CFGERRAERHEADERLOG113": "PCIE_CFGERRAERHEADERLOG113", + "CFGDEVCONTROLCORRERRREPORTINGEN": "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", + "TRNRD124": "PCIE_TRNRD124", + "PIPERX6CHANISALIGNED": "PCIE_PIPERX6CHANISALIGNED", + "CFGMGMTDWADDR2": "PCIE_CFGMGMTDWADDR2", + "CFGERRAERHEADERLOG94": "PCIE_CFGERRAERHEADERLOG94", + "PIPERX5DATA5": "PCIE_PIPERX5DATA5", + "CFGERRCPLRDYN": "PCIE_CFGERRCPLRDYN", + "TRNTDLLPSRCRDY": "PCIE_TRNTDLLPSRCRDY", + "CFGERRAERHEADERLOG2": "PCIE_CFGERRAERHEADERLOG2", + "PIPERX3CHANISALIGNED": "PCIE_PIPERX3CHANISALIGNED", + "PLLINKPARTNERGEN2SUPPORTED": "PCIE_PLLINKPARTNERGEN2SUPPORTED", + "TRNTDLLPDATA0": "PCIE_TRNTDLLPDATA0", + "TL2ERRHDR18": "PCIE_TL2ERRHDR18", + "XILUNCONNOUT10": "PCIE_XILUNCONNOUT10", + "XILUNCONNOUT0": "PCIE_XILUNCONNOUT0", + "TRNRD105": "PCIE_TRNRD105", + "TRNFCSEL2": "PCIE_TRNFCSEL2", + "MIMRXWADDR1": "PCIE_MIMRXWADDR1", + "CFGSUBSYSVENDID13": "PCIE_CFGSUBSYSVENDID13", + "CFGMSGDATA11": "PCIE_CFGMSGDATA11", + "MIMRXWDATA34": "PCIE_MIMRXWDATA34", + "TRNRD72": "PCIE_TRNRD72", + "MIMRXRDATA43": "PCIE_MIMRXRDATA43", + "PIPERX5DATA1": "PCIE_PIPERX5DATA1", + "PIPERX7DATA11": "PCIE_PIPERX7DATA11", + "TRNRDLLPDATA13": "PCIE_TRNRDLLPDATA13", + "CFGERRTLPCPLHEADER5": "PCIE_CFGERRTLPCPLHEADER5", + "DBGVECB36": "PCIE_DBGVECB36", + "PLLTSSMSTATE2": "PCIE_PLLTSSMSTATE2", + "DBGVECB41": "PCIE_DBGVECB41", + "TRNTDSTRDY3": "PCIE_TRNTDSTRDY3", + "CFGERRAERHEADERLOG118": "PCIE_CFGERRAERHEADERLOG118", + "TL2ERRHDR60": "PCIE_TL2ERRHDR60", + "TRNTBUFAV4": "PCIE_TRNTBUFAV4", + "CFGMSGDATA8": "PCIE_CFGMSGDATA8", + "PIPERX6DATA1": "PCIE_PIPERX6DATA1", + "TRNRDLLPDATA52": "PCIE_TRNRDLLPDATA52", + "MIMRXWDATA20": "PCIE_MIMRXWDATA20", + "PIPERX0STATUS1": "PCIE_PIPERX0STATUS1", + "MIMRXWDATA37": "PCIE_MIMRXWDATA37", + "MIMRXRDATA58": "PCIE_MIMRXRDATA58", + "TRNFCPH1": "PCIE_TRNFCPH1", + "TRNTDLLPDATA17": "PCIE_TRNTDLLPDATA17", + "MIMTXRDATA8": "PCIE_MIMTXRDATA8", + "XILUNCONNOUT28": "PCIE_XILUNCONNOUT28", + "LL2SENDPMACK": "PCIE_LL2SENDPMACK", + "CFGDSN29": "PCIE_CFGDSN29", + "MIMRXWADDR2": "PCIE_MIMRXWADDR2", + "SYSRSTN": "PCIE_SYSRSTN", + "PIPETX3DATA5": "PCIE_PIPETX3DATA5", + "PLINITIALLINKWIDTH1": "PCIE_PLINITIALLINKWIDTH1", + "MIMRXWDATA19": "PCIE_MIMRXWDATA19", + "CFGERRAERHEADERLOG104": "PCIE_CFGERRAERHEADERLOG104", + "TRNTD82": "PCIE_TRNTD82", + "CFGERRTLPCPLHEADER9": "PCIE_CFGERRTLPCPLHEADER9", + "TRNRD71": "PCIE_TRNRD71", + "CFGDSN3": "PCIE_CFGDSN3", + "TRNTDLLPDATA16": "PCIE_TRNTDLLPDATA16", + "TRNTD6": "PCIE_TRNTD6", + "TRNRSRCDSC": "PCIE_TRNRSRCDSC", + "PIPETX5DATA3": "PCIE_PIPETX5DATA3", + "PIPERX0STATUS2": "PCIE_PIPERX0STATUS2", + "DBGVECA15": "PCIE_DBGVECA15", + "CFGDEVCONTROLMAXREADREQ0": "PCIE_CFGDEVCONTROLMAXREADREQ0", + "CFGDSN21": "PCIE_CFGDSN21", + "CFGMSGDATA5": "PCIE_CFGMSGDATA5", + "CFGMSGRECEIVEDDEASSERTINTA": "PCIE_CFGMSGRECEIVEDDEASSERTINTA", + "TRNTD69": "PCIE_TRNTD69", + "TL2ERRHDR39": "PCIE_TL2ERRHDR39", + "CFGERRAERHEADERLOG74": "PCIE_CFGERRAERHEADERLOG74", + "XILUNCONNOUT1": "PCIE_XILUNCONNOUT1", + "MIMRXRDATA34": "PCIE_MIMRXRDATA34", + "MIMRXRDATA60": "PCIE_MIMRXRDATA60", + "TRNRD114": "PCIE_TRNRD114", + "CFGDSN51": "PCIE_CFGDSN51", + "DBGVECC5": "PCIE_DBGVECC5", + "CFGERRTLPCPLHEADER30": "PCIE_CFGERRTLPCPLHEADER30", + "LL2LINKSTATUS1": "PCIE_LL2LINKSTATUS1", + "TL2ERRHDR23": "PCIE_TL2ERRHDR23", + "CFGLINKCONTROLASPMCONTROL0": "PCIE_CFGLINKCONTROLASPMCONTROL0", + "PIPETX5ELECIDLE": "PCIE_PIPETX5ELECIDLE", + "MIMTXRDATA40": "PCIE_MIMTXRDATA40", + "DBGVECB44": "PCIE_DBGVECB44", + "TRNTDLLPDATA3": "PCIE_TRNTDLLPDATA3", + "MIMTXWDATA67": "PCIE_MIMTXWDATA67", + "TRNRDLLPDATA33": "PCIE_TRNRDLLPDATA33", + "CFGVENDID9": "PCIE_CFGVENDID9", + "XILUNCONNOUT33": "PCIE_XILUNCONNOUT33", + "CFGVCTCVCMAP2": "PCIE_CFGVCTCVCMAP2", + "MIMTXWDATA62": "PCIE_MIMTXWDATA62", + "CFGERRAERHEADERLOG26": "PCIE_CFGERRAERHEADERLOG26", + "TRNTD55": "PCIE_TRNTD55", + "TL2ERRHDR48": "PCIE_TL2ERRHDR48", + "PIPETXMARGIN0": "PCIE_PIPETXMARGIN0", + "DBGVECA46": "PCIE_DBGVECA46", + "MIMRXRDATA38": "PCIE_MIMRXRDATA38", + "TRNRD109": "PCIE_TRNRD109", + "CFGDEVID0": "PCIE_CFGDEVID0", + "CFGERRAERHEADERLOG87": "PCIE_CFGERRAERHEADERLOG87", + "CFGMGMTDWADDR0": "PCIE_CFGMGMTDWADDR0", + "PIPETX3DATA10": "PCIE_PIPETX3DATA10", + "MIMTXRDATA12": "PCIE_MIMTXRDATA12", + "TRNTD123": "PCIE_TRNTD123", + "CFGINTERRUPTDO3": "PCIE_CFGINTERRUPTDO3", + "TRNRD66": "PCIE_TRNRD66", + "PIPETX4DATA3": "PCIE_PIPETX4DATA3", + "DBGSCLRB": "PCIE_DBGSCLRB", + "CFGERRAERHEADERLOG59": "PCIE_CFGERRAERHEADERLOG59", + "PIPERX1STATUS0": "PCIE_PIPERX1STATUS0", + "CFGERRAERHEADERLOG123": "PCIE_CFGERRAERHEADERLOG123", + "DBGVECA18": "PCIE_DBGVECA18", + "MIMRXWDATA10": "PCIE_MIMRXWDATA10", + "TRNTD19": "PCIE_TRNTD19", + "PIPETX0DATA15": "PCIE_PIPETX0DATA15", + "PIPERX7DATA13": "PCIE_PIPERX7DATA13", + "CFGAERROOTERRNONFATALERRRECEIVED": "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", + "TRNTDLLPDATA28": "PCIE_TRNTDLLPDATA28", + "CFGDEVID15": "PCIE_CFGDEVID15", + "DRPDO6": "PCIE_DRPDO6", + "CFGMGMTDI13": "PCIE_CFGMGMTDI13", + "PLDBGVEC10": "PCIE_PLDBGVEC10", + "XILUNCONNOUT30": "PCIE_XILUNCONNOUT30", + "CFGMSGRECEIVEDASSERTINTD": "PCIE_CFGMSGRECEIVEDASSERTINTD", + "PIPERX2PHYSTATUS": "PCIE_PIPERX2PHYSTATUS", + "PIPERX2DATA10": "PCIE_PIPERX2DATA10", + "MIMRXWDATA1": "PCIE_MIMRXWDATA1", + "TL2ERRHDR55": "PCIE_TL2ERRHDR55", + "PIPERX7DATA4": "PCIE_PIPERX7DATA4", + "LL2LINKSTATUS0": "PCIE_LL2LINKSTATUS0", + "TRNFCNPH0": "PCIE_TRNFCNPH0", + "PIPETX7DATA6": "PCIE_PIPETX7DATA6", + "CFGMGMTDO22": "PCIE_CFGMGMTDO22", + "CFGERRAERHEADERLOG88": "PCIE_CFGERRAERHEADERLOG88", + "PIPETX7CHARISK1": "PCIE_PIPETX7CHARISK1", + "LL2REPLAYTOERR": "PCIE_LL2REPLAYTOERR", + "TRNTD93": "PCIE_TRNTD93", + "DBGVECA43": "PCIE_DBGVECA43", + "TRNRBARHIT7": "PCIE_TRNRBARHIT7", + "PIPERX4STATUS2": "PCIE_PIPERX4STATUS2", + "MIMRXRDATA36": "PCIE_MIMRXRDATA36", + "PMVDIVIDE1": "PCIE_PMVDIVIDE1", + "MIMRXRDATA50": "PCIE_MIMRXRDATA50", + "CFGMSGRECEIVEDASSERTINTA": "PCIE_CFGMSGRECEIVEDASSERTINTA", + "CFGDEVSTATUSCORRERRDETECTED": "PCIE_CFGDEVSTATUSCORRERRDETECTED", + "MIMRXWDATA25": "PCIE_MIMRXWDATA25", + "CFGERRTLPCPLHEADER15": "PCIE_CFGERRTLPCPLHEADER15", + "PIPERX1DATA11": "PCIE_PIPERX1DATA11", + "CFGMGMTDO28": "PCIE_CFGMGMTDO28", + "TRNTD52": "PCIE_TRNTD52", + "CFGMGMTDWADDR5": "PCIE_CFGMGMTDWADDR5", + "TRNTEOF": "PCIE_TRNTEOF", + "TRNTBUFAV2": "PCIE_TRNTBUFAV2", + "PIPERX1DATA12": "PCIE_PIPERX1DATA12", + "MIMTXRDATA63": "PCIE_MIMTXRDATA63", + "PIPETX4DATA0": "PCIE_PIPETX4DATA0", + "MIMTXWADDR3": "PCIE_MIMTXWADDR3", + "CFGMGMTDWADDR1": "PCIE_CFGMGMTDWADDR1", + "PIPERX4DATA8": "PCIE_PIPERX4DATA8", + "CFGERRAERHEADERLOG46": "PCIE_CFGERRAERHEADERLOG46", + "CFGERRAERHEADERLOG80": "PCIE_CFGERRAERHEADERLOG80", + "TRNFCPH4": "PCIE_TRNFCPH4", + "CFGERRAERHEADERLOG43": "PCIE_CFGERRAERHEADERLOG43", + "TRNTD83": "PCIE_TRNTD83", + "PIPETX6DATA6": "PCIE_PIPETX6DATA6", + "CFGDSN1": "PCIE_CFGDSN1", + "CFGERRAERHEADERLOG36": "PCIE_CFGERRAERHEADERLOG36", + "CFGVENDID7": "PCIE_CFGVENDID7", + "DBGVECC11": "PCIE_DBGVECC11", + "CFGERRTLPCPLHEADER20": "PCIE_CFGERRTLPCPLHEADER20", + "CFGMGMTDI19": "PCIE_CFGMGMTDI19", + "TRNRDLLPDATA22": "PCIE_TRNRDLLPDATA22", + "MIMTXRDATA46": "PCIE_MIMTXRDATA46", + "MIMTXRADDR4": "PCIE_MIMTXRADDR4", + "MIMTXWADDR12": "PCIE_MIMTXWADDR12", + "CFGERRCORN": "PCIE_CFGERRCORN", + "DRPADDR7": "PCIE_DRPADDR7", + "TRNTD10": "PCIE_TRNTD10", + "MIMTXWDATA27": "PCIE_MIMTXWDATA27", + "DBGVECB32": "PCIE_DBGVECB32", + "TL2ERRHDR57": "PCIE_TL2ERRHDR57", + "PIPERX5DATA6": "PCIE_PIPERX5DATA6", + "MIMRXWDATA32": "PCIE_MIMRXWDATA32", + "PIPERX1VALID": "PCIE_PIPERX1VALID", + "TRNTD114": "PCIE_TRNTD114", + "CFGLINKSTATUSNEGOTIATEDWIDTH0": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", + "PIPERX0CHARISK0": "PCIE_PIPERX0CHARISK0", + "CFGMGMTDO13": "PCIE_CFGMGMTDO13", + "PIPERX0VALID": "PCIE_PIPERX0VALID", + "CFGVENDID2": "PCIE_CFGVENDID2", + "TRNRDLLPDATA57": "PCIE_TRNRDLLPDATA57", + "CFGMGMTDO30": "PCIE_CFGMGMTDO30", + "CFGDEVCONTROLMAXPAYLOAD1": "PCIE_CFGDEVCONTROLMAXPAYLOAD1", + "CFGDSN20": "PCIE_CFGDSN20", + "PIPERX5DATA0": "PCIE_PIPERX5DATA0", + "CFGVENDID13": "PCIE_CFGVENDID13", + "DRPDI5": "PCIE_DRPDI5", + "DBGVECB53": "PCIE_DBGVECB53", + "DBGVECB2": "PCIE_DBGVECB2", + "TL2ERRHDR38": "PCIE_TL2ERRHDR38", + "CFGERRAERHEADERLOG3": "PCIE_CFGERRAERHEADERLOG3", + "CFGERRAERHEADERLOG24": "PCIE_CFGERRAERHEADERLOG24", + "CFGAERINTERRUPTMSGNUM1": "PCIE_CFGAERINTERRUPTMSGNUM1", + "TRNTDLLPDATA12": "PCIE_TRNTDLLPDATA12", + "MIMRXWADDR12": "PCIE_MIMRXWADDR12", + "CFGDEVCONTROL2ARIFORWARDEN": "PCIE_CFGDEVCONTROL2ARIFORWARDEN", + "TRNTDLLPDATA19": "PCIE_TRNTDLLPDATA19", + "MIMRXWDATA49": "PCIE_MIMRXWDATA49", + "MIMRXRDATA51": "PCIE_MIMRXRDATA51", + "CFGERRAERHEADERLOG49": "PCIE_CFGERRAERHEADERLOG49", + "DBGVECB28": "PCIE_DBGVECB28", + "CFGROOTCONTROLPMEINTEN": "PCIE_CFGROOTCONTROLPMEINTEN", + "PIPERX0CHARISK1": "PCIE_PIPERX0CHARISK1", + "TRNTD117": "PCIE_TRNTD117", + "CFGMGMTDI11": "PCIE_CFGMGMTDI11", + "MIMTXWDATA10": "PCIE_MIMTXWDATA10", + "TRNTDLLPDATA11": "PCIE_TRNTDLLPDATA11", + "MIMRXRDATA11": "PCIE_MIMRXRDATA11", + "PLDIRECTEDLINKAUTON": "PCIE_PLDIRECTEDLINKAUTON", + "PIPERX3DATA12": "PCIE_PIPERX3DATA12", + "CFGDEVSTATUSURDETECTED": "PCIE_CFGDEVSTATUSURDETECTED", + "MIMTXRDATA2": "PCIE_MIMTXRDATA2", + "PLTXPMSTATE2": "PCIE_PLTXPMSTATE2", + "CFGSUBSYSID13": "PCIE_CFGSUBSYSID13", + "CFGREVID2": "PCIE_CFGREVID2", + "DRPDI15": "PCIE_DRPDI15", + "TRNTD36": "PCIE_TRNTD36", + "PIPETX2CHARISK1": "PCIE_PIPETX2CHARISK1", + "PIPETX2DATA13": "PCIE_PIPETX2DATA13", + "DBGVECB48": "PCIE_DBGVECB48", + "DBGVECA45": "PCIE_DBGVECA45", + "CFGERRAERHEADERLOG41": "PCIE_CFGERRAERHEADERLOG41", + "TRNRDLLPDATA0": "PCIE_TRNRDLLPDATA0", + "TRNTD29": "PCIE_TRNTD29", + "PIPETX3DATA4": "PCIE_PIPETX3DATA4", + "MIMRXWDATA43": "PCIE_MIMRXWDATA43", + "PIPETX6DATA4": "PCIE_PIPETX6DATA4", + "DBGSCLRJ": "PCIE_DBGSCLRJ", + "TRNRD24": "PCIE_TRNRD24", + "CFGDSN25": "PCIE_CFGDSN25", + "CFGAERROOTERRFATALERRREPORTINGEN": "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", + "PIPERX3DATA1": "PCIE_PIPERX3DATA1", + "TRNRD104": "PCIE_TRNRD104", + "CFGDEVCONTROL2CPLTIMEOUTVAL3": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "PIPETX3DATA6": "PCIE_PIPETX3DATA6", + "PIPERX7DATA3": "PCIE_PIPERX7DATA3", + "TRNRD76": "PCIE_TRNRD76", + "PLLTSSMSTATE5": "PCIE_PLLTSSMSTATE5", + "MIMTXWDATA6": "PCIE_MIMTXWDATA6", + "TL2ERRHDR26": "PCIE_TL2ERRHDR26", + "CFGERRAERHEADERLOG101": "PCIE_CFGERRAERHEADERLOG101", + "CFGERRATOMICEGRESSBLOCKEDN": "PCIE_CFGERRATOMICEGRESSBLOCKEDN", + "TRNFCNPH7": "PCIE_TRNFCNPH7", + "DRPEN": "PCIE_DRPEN", + "MIMTXRADDR7": "PCIE_MIMTXRADDR7", + "TRNTD7": "PCIE_TRNTD7", + "PIPETX6CHARISK1": "PCIE_PIPETX6CHARISK1", + "CFGDSN10": "PCIE_CFGDSN10", + "PIPETXMARGIN2": "PCIE_PIPETXMARGIN2", + "TRNFCCPLD6": "PCIE_TRNFCCPLD6", + "CFGMGMTDI30": "PCIE_CFGMGMTDI30", + "TRNFCCPLD1": "PCIE_TRNFCCPLD1", + "CFGERRAERHEADERLOG33": "PCIE_CFGERRAERHEADERLOG33", + "PIPERX0DATA2": "PCIE_PIPERX0DATA2", + "TRNFCCPLH6": "PCIE_TRNFCCPLH6", + "CFGMGMTDI0": "PCIE_CFGMGMTDI0", + "LL2LINKSTATUS2": "PCIE_LL2LINKSTATUS2", + "TRNRD18": "PCIE_TRNRD18", + "MIMTXWDATA38": "PCIE_MIMTXWDATA38", + "PIPETX0DATA14": "PCIE_PIPETX0DATA14", + "MIMRXRDATA21": "PCIE_MIMRXRDATA21", + "TRNRD55": "PCIE_TRNRD55", + "TRNTDLLPDATA20": "PCIE_TRNTDLLPDATA20", + "PIPETX1DATA1": "PCIE_PIPETX1DATA1", + "CFGMGMTDI24": "PCIE_CFGMGMTDI24", + "CFGAERECRCGENEN": "PCIE_CFGAERECRCGENEN", + "CFGVENDID6": "PCIE_CFGVENDID6", + "TRNTD78": "PCIE_TRNTD78", + "CFGSUBSYSVENDID11": "PCIE_CFGSUBSYSVENDID11", + "CFGDSN55": "PCIE_CFGDSN55", + "DBGVECB52": "PCIE_DBGVECB52", + "TRNTD113": "PCIE_TRNTD113", + "TRNRDLLPDATA55": "PCIE_TRNRDLLPDATA55", + "PIPETX1DATA5": "PCIE_PIPETX1DATA5", + "DBGVECA26": "PCIE_DBGVECA26", + "PIPETX6DATA2": "PCIE_PIPETX6DATA2", + "PIPERX4STATUS0": "PCIE_PIPERX4STATUS0", + "TL2ERRHDR51": "PCIE_TL2ERRHDR51", + "CFGERRTLPCPLHEADER2": "PCIE_CFGERRTLPCPLHEADER2", + "CFGMGMTDO6": "PCIE_CFGMGMTDO6", + "MIMTXRDATA11": "PCIE_MIMTXRDATA11", + "DBGVECB42": "PCIE_DBGVECB42", + "PIPETX0COMPLIANCE": "PCIE_PIPETX0COMPLIANCE", + "CFGPORTNUMBER6": "PCIE_CFGPORTNUMBER6", + "DBGVECB22": "PCIE_DBGVECB22", + "CFGERRCPLUNEXPECTN": "PCIE_CFGERRCPLUNEXPECTN", + "DBGVECB13": "PCIE_DBGVECB13", + "DBGVECB50": "PCIE_DBGVECB50", + "CFGVENDID5": "PCIE_CFGVENDID5", + "DRPADDR3": "PCIE_DRPADDR3", + "XILUNCONNOUT16": "PCIE_XILUNCONNOUT16", + "CFGDEVID12": "PCIE_CFGDEVID12", + "TRNFCNPD10": "PCIE_TRNFCNPD10", + "MIMTXRDATA57": "PCIE_MIMTXRDATA57", + "TRNTDLLPDATA1": "PCIE_TRNTDLLPDATA1", + "PIPETX1DATA2": "PCIE_PIPETX1DATA2", + "DRPDO2": "PCIE_DRPDO2", + "CFGMGMTDO8": "PCIE_CFGMGMTDO8", + "CFGDEVCONTROLNOSNOOPEN": "PCIE_CFGDEVCONTROLNOSNOOPEN", + "TRNRD91": "PCIE_TRNRD91", + "TRNFCNPH6": "PCIE_TRNFCNPH6", + "PIPERX7DATA10": "PCIE_PIPERX7DATA10", + "PIPETX7DATA10": "PCIE_PIPETX7DATA10", + "TRNRD113": "PCIE_TRNRD113", + "MIMTXWADDR9": "PCIE_MIMTXWADDR9", + "CFGERRAERHEADERLOG14": "PCIE_CFGERRAERHEADERLOG14", + "PIPETX0DATA6": "PCIE_PIPETX0DATA6", + "PIPETX6DATA3": "PCIE_PIPETX6DATA3", + "TRNRD39": "PCIE_TRNRD39", + "PIPERX2CHARISK0": "PCIE_PIPERX2CHARISK0", + "CFGMGMTDO16": "PCIE_CFGMGMTDO16", + "CFGMSGDATA14": "PCIE_CFGMSGDATA14", + "MIMTXWEN": "PCIE_MIMTXWEN", + "MIMRXRDATA10": "PCIE_MIMRXRDATA10", + "MIMTXWDATA39": "PCIE_MIMTXWDATA39", + "PIPETX7DATA12": "PCIE_PIPETX7DATA12", + "PMVSELECT0": "PCIE_PMVSELECT0", + "CFGDSN32": "PCIE_CFGDSN32", + "DRPDO12": "PCIE_DRPDO12", + "PIPETX1DATA10": "PCIE_PIPETX1DATA10", + "PLSELLNKRATE": "PCIE_PLSELLNKRATE", + "PIPETX6DATA1": "PCIE_PIPETX6DATA1", + "PLDBGVEC9": "PCIE_PLDBGVEC9", + "DBGVECB26": "PCIE_DBGVECB26", + "TRNRD37": "PCIE_TRNRD37", + "EDTCHANNELSOUT2": "PCIE_EDTCHANNELSOUT2", + "DBGVECA56": "PCIE_DBGVECA56", + "TRNRD97": "PCIE_TRNRD97", + "PIPETX7DATA1": "PCIE_PIPETX7DATA1", + "MIMTXWDATA68": "PCIE_MIMTXWDATA68", + "CFGREVID1": "PCIE_CFGREVID1", + "CFGDEVID3": "PCIE_CFGDEVID3", + "MIMTXRDATA38": "PCIE_MIMTXRDATA38", + "CFGPMRCVREQACKN": "PCIE_CFGPMRCVREQACKN", + "PLDBGVEC6": "PCIE_PLDBGVEC6", + "DBGVECC7": "PCIE_DBGVECC7", + "CFGMGMTDI3": "PCIE_CFGMGMTDI3", + "DRPDO7": "PCIE_DRPDO7", + "PIPERX4VALID": "PCIE_PIPERX4VALID", + "XILUNCONNOUT12": "PCIE_XILUNCONNOUT12", + "CFGMGMTDI5": "PCIE_CFGMGMTDI5", + "DRPADDR5": "PCIE_DRPADDR5", + "TRNRDLLPDATA29": "PCIE_TRNRDLLPDATA29", + "CFGPMRCVASREQL1N": "PCIE_CFGPMRCVASREQL1N", + "MIMRXRDATA29": "PCIE_MIMRXRDATA29", + "CFGDEVCONTROL2IDOCPLEN": "PCIE_CFGDEVCONTROL2IDOCPLEN", + "TL2ERRHDR1": "PCIE_TL2ERRHDR1", + "TRNRD70": "PCIE_TRNRD70", + "MIMTXWADDR5": "PCIE_MIMTXWADDR5", + "CFGVENDID1": "PCIE_CFGVENDID1", + "MIMRXWDATA2": "PCIE_MIMRXWDATA2", + "CFGERRTLPCPLHEADER11": "PCIE_CFGERRTLPCPLHEADER11", + "PIPERX0DATA12": "PCIE_PIPERX0DATA12", + "CFGERRTLPCPLHEADER33": "PCIE_CFGERRTLPCPLHEADER33", + "CFGERRTLPCPLHEADER44": "PCIE_CFGERRTLPCPLHEADER44", + "DBGVECB58": "PCIE_DBGVECB58", + "CFGDSBUSNUMBER4": "PCIE_CFGDSBUSNUMBER4", + "PIPETX3DATA12": "PCIE_PIPETX3DATA12", + "TRNRDLLPDATA44": "PCIE_TRNRDLLPDATA44", + "CFGINTERRUPTDI4": "PCIE_CFGINTERRUPTDI4", + "CFGDSN40": "PCIE_CFGDSN40", + "PLDBGMODE1": "PCIE_PLDBGMODE1", + "TRNTDLLPDATA24": "PCIE_TRNTDLLPDATA24", + "MIMRXWDATA66": "PCIE_MIMRXWDATA66", + "CFGMGMTRDWRDONEN": "PCIE_CFGMGMTRDWRDONEN", + "DBGVECA11": "PCIE_DBGVECA11", + "TRNFCNPD7": "PCIE_TRNFCNPD7", + "MIMRXWADDR9": "PCIE_MIMRXWADDR9", + "CFGERRTLPCPLHEADER23": "PCIE_CFGERRTLPCPLHEADER23", + "TRNTD66": "PCIE_TRNTD66", + "MIMRXRDATA22": "PCIE_MIMRXRDATA22", + "CFGPORTNUMBER2": "PCIE_CFGPORTNUMBER2", + "CFGERRAERHEADERLOG95": "PCIE_CFGERRAERHEADERLOG95", + "PIPETX7DATA8": "PCIE_PIPETX7DATA8", + "TRNTD11": "PCIE_TRNTD11", + "CFGLINKCONTROLLINKDISABLE": "PCIE_CFGLINKCONTROLLINKDISABLE", + "MIMTXRDATA0": "PCIE_MIMTXRDATA0", + "TL2ASPMSUSPENDREQ": "PCIE_TL2ASPMSUSPENDREQ", + "TRNRDLLPDATA48": "PCIE_TRNRDLLPDATA48", + "TRNRD116": "PCIE_TRNRD116", + "MIMTXWDATA41": "PCIE_MIMTXWDATA41", + "TL2ERRHDR13": "PCIE_TL2ERRHDR13", + "TRNRD5": "PCIE_TRNRD5", + "TRNTD24": "PCIE_TRNTD24", + "MIMRXWDATA0": "PCIE_MIMRXWDATA0", + "PIPETX2DATA9": "PCIE_PIPETX2DATA9", + "MIMTXRDATA26": "PCIE_MIMTXRDATA26", + "PIPETX0DATA4": "PCIE_PIPETX0DATA4", + "PLDIRECTEDLINKSPEED": "PCIE_PLDIRECTEDLINKSPEED", + "CFGDSN37": "PCIE_CFGDSN37", + "TRNTD43": "PCIE_TRNTD43", + "CFGMGMTDO19": "PCIE_CFGMGMTDO19", + "CFGMGMTWRRW1CASRWN": "PCIE_CFGMGMTWRRW1CASRWN", + "MIMTXWDATA34": "PCIE_MIMTXWDATA34", + "TRNFCCPLH3": "PCIE_TRNFCCPLH3", + "TL2ERRHDR14": "PCIE_TL2ERRHDR14", + "CFGERRTLPCPLHEADER42": "PCIE_CFGERRTLPCPLHEADER42", + "DBGVECB5": "PCIE_DBGVECB5", + "PIPETX2CHARISK0": "PCIE_PIPETX2CHARISK0", + "PIPERX1POLARITY": "PCIE_PIPERX1POLARITY", + "PLRSTN": "PCIE_PLRSTN", + "CFGERRTLPCPLHEADER7": "PCIE_CFGERRTLPCPLHEADER7", + "PIPETX6DATA12": "PCIE_PIPETX6DATA12", + "MIMRXRDATA61": "PCIE_MIMRXRDATA61", + "CFGMGMTDO10": "PCIE_CFGMGMTDO10", + "MIMRXWDATA30": "PCIE_MIMRXWDATA30", + "TL2ERRHDR28": "PCIE_TL2ERRHDR28", + "MIMRXWDATA36": "PCIE_MIMRXWDATA36", + "MIMRXRDATA27": "PCIE_MIMRXRDATA27", + "DBGVECB35": "PCIE_DBGVECB35", + "CFGERRAERHEADERLOG65": "PCIE_CFGERRAERHEADERLOG65", + "CFGMGMTDO20": "PCIE_CFGMGMTDO20", + "PIPERX3DATA10": "PCIE_PIPERX3DATA10", + "MIMTXRDATA35": "PCIE_MIMTXRDATA35", + "MIMRXWDATA51": "PCIE_MIMRXWDATA51", + "DBGVECA28": "PCIE_DBGVECA28", + "PIPERX0DATA11": "PCIE_PIPERX0DATA11", + "TL2ERRHDR46": "PCIE_TL2ERRHDR46", + "TRNTBUFAV1": "PCIE_TRNTBUFAV1", + "TRNFCCPLD8": "PCIE_TRNFCCPLD8", + "CFGPMCSRPOWERSTATE0": "PCIE_CFGPMCSRPOWERSTATE0", + "MIMRXRDATA59": "PCIE_MIMRXRDATA59", + "MIMTXRDATA49": "PCIE_MIMTXRDATA49", + "PIPERX5DATA7": "PCIE_PIPERX5DATA7", + "CFGDSN50": "PCIE_CFGDSN50", + "CFGERRAERHEADERLOG85": "PCIE_CFGERRAERHEADERLOG85", + "MIMRXRDATA67": "PCIE_MIMRXRDATA67", + "TRNRDLLPDATA17": "PCIE_TRNRDLLPDATA17", + "PIPERX2DATA5": "PCIE_PIPERX2DATA5", + "MIMRXWADDR5": "PCIE_MIMRXWADDR5", + "CFGERRAERHEADERLOG10": "PCIE_CFGERRAERHEADERLOG10", + "PIPETX4POWERDOWN1": "PCIE_PIPETX4POWERDOWN1", + "CFGERRAERHEADERLOG38": "PCIE_CFGERRAERHEADERLOG38", + "LNKCLKEN": "PCIE_LNKCLKEN", + "MIMRXRDATA23": "PCIE_MIMRXRDATA23", + "TRNRDLLPDATA4": "PCIE_TRNRDLLPDATA4", + "PLPHYLNKUPN": "PCIE_PLPHYLNKUPN", + "MIMRXRDATA44": "PCIE_MIMRXRDATA44", + "TRNFCPH0": "PCIE_TRNFCPH0", + "PIPERX3DATA13": "PCIE_PIPERX3DATA13", + "PIPERX7DATA2": "PCIE_PIPERX7DATA2", + "CFGCOMMANDINTERRUPTDISABLE": "PCIE_CFGCOMMANDINTERRUPTDISABLE", + "TRNTD50": "PCIE_TRNTD50", + "CFGDEVID13": "PCIE_CFGDEVID13", + "DBGVECC9": "PCIE_DBGVECC9", + "CFGERRNORECOVERYN": "PCIE_CFGERRNORECOVERYN", + "PIPERX6STATUS2": "PCIE_PIPERX6STATUS2", + "MIMRXWEN": "PCIE_MIMRXWEN", + "CFGDSN0": "PCIE_CFGDSN0", + "PIPERX3DATA3": "PCIE_PIPERX3DATA3", + "MIMRXRDATA19": "PCIE_MIMRXRDATA19", + "DRPADDR0": "PCIE_DRPADDR0", + "XILUNCONNOUT32": "PCIE_XILUNCONNOUT32", + "DRPDI11": "PCIE_DRPDI11", + "XILUNCONNOUT26": "PCIE_XILUNCONNOUT26", + "CFGERRAERHEADERLOG56": "PCIE_CFGERRAERHEADERLOG56", + "MIMRXRADDR10": "PCIE_MIMRXRADDR10", + "TRNTD60": "PCIE_TRNTD60", + "CFGERRAERHEADERLOG111": "PCIE_CFGERRAERHEADERLOG111", + "CFGMSGDATA6": "PCIE_CFGMSGDATA6", + "CFGDSDEVICENUMBER4": "PCIE_CFGDSDEVICENUMBER4", + "MIMTXWDATA59": "PCIE_MIMTXWDATA59", + "TRNRDLLPDATA24": "PCIE_TRNRDLLPDATA24", + "CFGDSN60": "PCIE_CFGDSN60", + "PIPETX3DATA7": "PCIE_PIPETX3DATA7", + "TRNRD44": "PCIE_TRNRD44", + "CFGDSN22": "PCIE_CFGDSN22", + "PL2LINKUP": "PCIE_PL2LINKUP", + "PIPETX4DATA1": "PCIE_PIPETX4DATA1", + "PIPERX5STATUS1": "PCIE_PIPERX5STATUS1", + "PIPETXRCVRDET": "PCIE_PIPETXRCVRDET", + "CFGERRAERHEADERLOG54": "PCIE_CFGERRAERHEADERLOG54", + "CFGDSN56": "PCIE_CFGDSN56", + "PLLTSSMSTATE3": "PCIE_PLLTSSMSTATE3", + "DRPDI4": "PCIE_DRPDI4", + "CFGMGMTDO14": "PCIE_CFGMGMTDO14", + "PIPETX1CHARISK1": "PCIE_PIPETX1CHARISK1", + "DRPDO1": "PCIE_DRPDO1", + "TRNRDLLPDATA7": "PCIE_TRNRDLLPDATA7", + "TRNRBARHIT5": "PCIE_TRNRBARHIT5", + "PL2RXPMSTATE1": "PCIE_PL2RXPMSTATE1", + "DBGVECB61": "PCIE_DBGVECB61", + "TRNTSOF": "PCIE_TRNTSOF", + "CFGDSDEVICENUMBER2": "PCIE_CFGDSDEVICENUMBER2", + "CFGERRAERHEADERLOG75": "PCIE_CFGERRAERHEADERLOG75", + "MIMRXRDATA54": "PCIE_MIMRXRDATA54", + "DRPDI13": "PCIE_DRPDI13", + "CFGDSDEVICENUMBER0": "PCIE_CFGDSDEVICENUMBER0", + "CFGINTERRUPTDO5": "PCIE_CFGINTERRUPTDO5", + "TRNTDLLPDATA14": "PCIE_TRNTDLLPDATA14", + "MIMRXWDATA56": "PCIE_MIMRXWDATA56", + "CFGDEVCONTROL2LTREN": "PCIE_CFGDEVCONTROL2LTREN", + "DBGVECA23": "PCIE_DBGVECA23", + "PIPETX1POWERDOWN1": "PCIE_PIPETX1POWERDOWN1", + "DBGVECA44": "PCIE_DBGVECA44", + "MIMTXWDATA45": "PCIE_MIMTXWDATA45", + "TRNFCPD11": "PCIE_TRNFCPD11", + "CFGMGMTDWADDR3": "PCIE_CFGMGMTDWADDR3", + "CFGERRAERHEADERLOG6": "PCIE_CFGERRAERHEADERLOG6", + "PIPETX4CHARISK0": "PCIE_PIPETX4CHARISK0", + "MIMRXRDATA65": "PCIE_MIMRXRDATA65", + "EDTCHANNELSOUT5": "PCIE_EDTCHANNELSOUT5", + "MIMTXRDATA31": "PCIE_MIMTXRDATA31", + "PIPERX0DATA0": "PCIE_PIPERX0DATA0", + "CFGMSGDATA10": "PCIE_CFGMSGDATA10", + "CFGDSBUSNUMBER0": "PCIE_CFGDSBUSNUMBER0", + "CFGMGMTDO11": "PCIE_CFGMGMTDO11", + "CFGPORTNUMBER3": "PCIE_CFGPORTNUMBER3", + "CFGDSBUSNUMBER6": "PCIE_CFGDSBUSNUMBER6", + "MIMTXRDATA20": "PCIE_MIMTXRDATA20", + "MIMRXWDATA7": "PCIE_MIMRXWDATA7", + "LL2TLPRCV": "PCIE_LL2TLPRCV", + "PIPERX2DATA1": "PCIE_PIPERX2DATA1", + "CFGERRAERHEADERLOG17": "PCIE_CFGERRAERHEADERLOG17", + "TRNRDLLPDATA45": "PCIE_TRNRDLLPDATA45", + "CFGERRAERHEADERLOG91": "PCIE_CFGERRAERHEADERLOG91", + "EDTUPDATE": "PCIE_EDTUPDATE", + "CFGDSFUNCTIONNUMBER0": "PCIE_CFGDSFUNCTIONNUMBER0", + "MIMRXRADDR7": "PCIE_MIMRXRADDR7", + "MIMRXWDATA57": "PCIE_MIMRXWDATA57", + "CFGERRAERHEADERLOG48": "PCIE_CFGERRAERHEADERLOG48", + "PIPERX1DATA6": "PCIE_PIPERX1DATA6", + "CFGDSN61": "PCIE_CFGDSN61", + "CFGERRTLPCPLHEADER40": "PCIE_CFGERRTLPCPLHEADER40", + "CFGINTERRUPTN": "PCIE_CFGINTERRUPTN", + "TRNRD119": "PCIE_TRNRD119", + "PIPETX2DATA1": "PCIE_PIPETX2DATA1", + "TRNFCCPLH4": "PCIE_TRNFCCPLH4", + "CFGMSGRECEIVEDPMPME": "PCIE_CFGMSGRECEIVEDPMPME", + "PIPETX5DATA0": "PCIE_PIPETX5DATA0", + "DBGVECA24": "PCIE_DBGVECA24", + "DRPDO5": "PCIE_DRPDO5", + "CFGTRANSACTIONADDR3": "PCIE_CFGTRANSACTIONADDR3", + "TRNRDLLPDATA32": "PCIE_TRNRDLLPDATA32", + "TRNFCNPD4": "PCIE_TRNFCNPD4", + "PL2DIRECTEDLSTATE0": "PCIE_PL2DIRECTEDLSTATE0", + "PIPERX6DATA2": "PCIE_PIPERX6DATA2", + "TRNRD57": "PCIE_TRNRD57", + "PIPERX0DATA10": "PCIE_PIPERX0DATA10", + "TRNRD23": "PCIE_TRNRD23", + "CFGERRTLPCPLHEADER14": "PCIE_CFGERRTLPCPLHEADER14", + "MIMTXRDATA18": "PCIE_MIMTXRDATA18", + "DBGVECA21": "PCIE_DBGVECA21", + "MIMRXRDATA9": "PCIE_MIMRXRDATA9", + "CFGMGMTDO9": "PCIE_CFGMGMTDO9", + "CFGMGMTDI21": "PCIE_CFGMGMTDI21", + "CFGDEVCONTROL2TLPPREFIXBLOCK": "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", + "PIPETX0ELECIDLE": "PCIE_PIPETX0ELECIDLE", + "DRPDI9": "PCIE_DRPDI9", + "CFGERRAERHEADERLOG125": "PCIE_CFGERRAERHEADERLOG125", + "CFGVCTCVCMAP3": "PCIE_CFGVCTCVCMAP3", + "PIPERX5DATA13": "PCIE_PIPERX5DATA13", + "TRNRDLLPDATA37": "PCIE_TRNRDLLPDATA37", + "TRNFCNPD8": "PCIE_TRNFCNPD8", + "TRNTD109": "PCIE_TRNTD109", + "MIMTXWDATA28": "PCIE_MIMTXWDATA28", + "CFGMGMTDO17": "PCIE_CFGMGMTDO17", + "PIPETX5DATA12": "PCIE_PIPETX5DATA12", + "MIMTXWDATA40": "PCIE_MIMTXWDATA40", + "CFGDEVID5": "PCIE_CFGDEVID5", + "CFGLINKSTATUSNEGOTIATEDWIDTH2": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", + "CFGMGMTDO31": "PCIE_CFGMGMTDO31", + "PMVDIVIDE0": "PCIE_PMVDIVIDE0", + "XILUNCONNOUT34": "PCIE_XILUNCONNOUT34", + "CFGERRAERHEADERLOG30": "PCIE_CFGERRAERHEADERLOG30", + "PIPERX3STATUS2": "PCIE_PIPERX3STATUS2", + "CFGSUBSYSVENDID8": "PCIE_CFGSUBSYSVENDID8", + "TRNTD101": "PCIE_TRNTD101", + "MIMRXWDATA29": "PCIE_MIMRXWDATA29", + "CFGERRTLPCPLHEADER16": "PCIE_CFGERRTLPCPLHEADER16", + "MIMTXWDATA64": "PCIE_MIMTXWDATA64", + "TRNTD32": "PCIE_TRNTD32", + "CFGINTERRUPTDO7": "PCIE_CFGINTERRUPTDO7", + "TRNRECRCERR": "PCIE_TRNRECRCERR", + "MIMTXWDATA36": "PCIE_MIMTXWDATA36", + "PIPETX4DATA7": "PCIE_PIPETX4DATA7", + "CFGDSN62": "PCIE_CFGDSN62", + "MIMRXRDATA55": "PCIE_MIMRXRDATA55", + "CFGMGMTDI17": "PCIE_CFGMGMTDI17", + "MIMRXWDATA62": "PCIE_MIMRXWDATA62", + "PIPETX5CHARISK0": "PCIE_PIPETX5CHARISK0", + "MIMTXRDATA14": "PCIE_MIMTXRDATA14", + "TRNRD4": "PCIE_TRNRD4", + "DBGVECC3": "PCIE_DBGVECC3", + "CFGERRAERHEADERLOG82": "PCIE_CFGERRAERHEADERLOG82", + "TRNTD65": "PCIE_TRNTD65", + "TL2ERRHDR30": "PCIE_TL2ERRHDR30", + "MIMTXWDATA15": "PCIE_MIMTXWDATA15", + "TRNRD108": "PCIE_TRNRD108", + "CFGMSGRECEIVEDDEASSERTINTC": "PCIE_CFGMSGRECEIVEDDEASSERTINTC", + "TRNRD17": "PCIE_TRNRD17", + "DBGVECB60": "PCIE_DBGVECB60", + "PIPERX1DATA15": "PCIE_PIPERX1DATA15", + "TRNTD99": "PCIE_TRNTD99", + "TRNLNKUP": "PCIE_TRNLNKUP", + "PIPERX5ELECIDLE": "PCIE_PIPERX5ELECIDLE", + "TL2PPMSUSPENDREQ": "PCIE_TL2PPMSUSPENDREQ", + "CFGTRANSACTION": "PCIE_CFGTRANSACTION", + "PIPETX1CHARISK0": "PCIE_PIPETX1CHARISK0", + "CFGSUBSYSID8": "PCIE_CFGSUBSYSID8", + "DBGVECB17": "PCIE_DBGVECB17", + "TRNRD74": "PCIE_TRNRD74", + "MIMTXRDATA4": "PCIE_MIMTXRDATA4", + "CFGINTERRUPTRDYN": "PCIE_CFGINTERRUPTRDYN", + "DBGVECA63": "PCIE_DBGVECA63", + "CFGERRTLPCPLHEADER41": "PCIE_CFGERRTLPCPLHEADER41", + "CMRSTN": "PCIE_CMRSTN", + "TRNRDLLPDATA9": "PCIE_TRNRDLLPDATA9", + "PIPERX6STATUS0": "PCIE_PIPERX6STATUS0", + "TL2ERRHDR34": "PCIE_TL2ERRHDR34", + "TRNTD62": "PCIE_TRNTD62", + "MIMRXRDATA57": "PCIE_MIMRXRDATA57", + "TRNTD107": "PCIE_TRNTD107", + "CFGDSN47": "PCIE_CFGDSN47", + "TRNRDLLPDATA49": "PCIE_TRNRDLLPDATA49", + "PIPETX4DATA2": "PCIE_PIPETX4DATA2", + "PIPETX4DATA6": "PCIE_PIPETX4DATA6", + "EDTBYPASS": "PCIE_EDTBYPASS", + "CFGERRAERHEADERLOG63": "PCIE_CFGERRAERHEADERLOG63", + "PIPERX7STATUS1": "PCIE_PIPERX7STATUS1", + "TRNTD111": "PCIE_TRNTD111", + "MIMTXWDATA51": "PCIE_MIMTXWDATA51", + "TRNTD38": "PCIE_TRNTD38", + "TRNRD61": "PCIE_TRNRD61", + "TRNTD91": "PCIE_TRNTD91", + "TRNTD104": "PCIE_TRNTD104", + "TRNTD95": "PCIE_TRNTD95", + "PIPETX3POWERDOWN0": "PCIE_PIPETX3POWERDOWN0", + "DBGVECB18": "PCIE_DBGVECB18", + "MIMRXWADDR4": "PCIE_MIMRXWADDR4", + "CFGINTERRUPTDO0": "PCIE_CFGINTERRUPTDO0", + "CFGDEVCONTROL2CPLTIMEOUTVAL0": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "MIMTXWDATA4": "PCIE_MIMTXWDATA4", + "CFGTRANSACTIONTYPE": "PCIE_CFGTRANSACTIONTYPE", + "PLRXPMSTATE0": "PCIE_PLRXPMSTATE0", + "CFGDEVID6": "PCIE_CFGDEVID6", + "PLDBGMODE2": "PCIE_PLDBGMODE2", + "TRNRD106": "PCIE_TRNRD106", + "TRNRDLLPDATA35": "PCIE_TRNRDLLPDATA35", + "PLLINKUPCFGCAP": "PCIE_PLLINKUPCFGCAP", + "CFGERRAERHEADERLOG1": "PCIE_CFGERRAERHEADERLOG1", + "DBGVECA6": "PCIE_DBGVECA6", + "PLRXPMSTATE1": "PCIE_PLRXPMSTATE1", + "PIPERX2STATUS1": "PCIE_PIPERX2STATUS1", + "PIPERX2DATA15": "PCIE_PIPERX2DATA15", + "CFGERRAERHEADERLOG37": "PCIE_CFGERRAERHEADERLOG37", + "CFGMGMTDWADDR8": "PCIE_CFGMGMTDWADDR8", + "PIPETX0DATA0": "PCIE_PIPETX0DATA0", + "PL2SUSPENDOK": "PCIE_PL2SUSPENDOK", + "MIMTXWADDR1": "PCIE_MIMTXWADDR1", + "CFGINTERRUPTDO6": "PCIE_CFGINTERRUPTDO6", + "CFGERRAERHEADERLOG115": "PCIE_CFGERRAERHEADERLOG115", + "MIMTXRDATA48": "PCIE_MIMTXRDATA48", + "CFGMSGRECEIVEDDEASSERTINTB": "PCIE_CFGMSGRECEIVEDDEASSERTINTB", + "CFGDEVID2": "PCIE_CFGDEVID2", + "EDTCHANNELSOUT4": "PCIE_EDTCHANNELSOUT4", + "CFGDSN53": "PCIE_CFGDSN53", + "PIPETX3POWERDOWN1": "PCIE_PIPETX3POWERDOWN1", + "TL2ERRHDR59": "PCIE_TL2ERRHDR59", + "MIMTXRDATA64": "PCIE_MIMTXRDATA64", + "TRNTERRDROP": "PCIE_TRNTERRDROP", + "PL2DIRECTEDLSTATE2": "PCIE_PL2DIRECTEDLSTATE2", + "TRNTD98": "PCIE_TRNTD98", + "CFGAERINTERRUPTMSGNUM3": "PCIE_CFGAERINTERRUPTMSGNUM3", + "MIMRXRDATA32": "PCIE_MIMRXRDATA32", + "MIMTXWDATA50": "PCIE_MIMTXWDATA50", + "MIMTXRDATA68": "PCIE_MIMTXRDATA68", + "CFGSUBSYSID3": "PCIE_CFGSUBSYSID3", + "DBGVECB31": "PCIE_DBGVECB31", + "TRNTD3": "PCIE_TRNTD3", + "DBGVECB3": "PCIE_DBGVECB3", + "XILUNCONNOUT21": "PCIE_XILUNCONNOUT21", + "TRNRD75": "PCIE_TRNRD75", + "CFGERRAERHEADERLOG5": "PCIE_CFGERRAERHEADERLOG5", + "CFGDSN63": "PCIE_CFGDSN63", + "MIMRXWDATA22": "PCIE_MIMRXWDATA22", + "DBGVECA29": "PCIE_DBGVECA29", + "MIMRXWDATA59": "PCIE_MIMRXWDATA59", + "PMVENABLEN": "PCIE_PMVENABLEN", + "PIPETX7POWERDOWN0": "PCIE_PIPETX7POWERDOWN0", + "PIPERX4PHYSTATUS": "PCIE_PIPERX4PHYSTATUS", + "MIMTXWDATA26": "PCIE_MIMTXWDATA26", + "MIMTXWADDR10": "PCIE_MIMTXWADDR10", + "CFGDSN12": "PCIE_CFGDSN12", + "CFGMGMTDI26": "PCIE_CFGMGMTDI26", + "CFGERRAERHEADERLOG73": "PCIE_CFGERRAERHEADERLOG73", + "TRNTDLLPDATA27": "PCIE_TRNTDLLPDATA27", + "TL2ERRHDR50": "PCIE_TL2ERRHDR50", + "MIMTXRDATA10": "PCIE_MIMTXRDATA10", + "TRNTD25": "PCIE_TRNTD25", + "MIMRXWADDR10": "PCIE_MIMRXWADDR10", + "TRNRD122": "PCIE_TRNRD122", + "PIPETX6ELECIDLE": "PCIE_PIPETX6ELECIDLE", + "TL2ERRHDR40": "PCIE_TL2ERRHDR40", + "DBGVECB34": "PCIE_DBGVECB34", + "DRPADDR1": "PCIE_DRPADDR1", + "MIMRXWDATA61": "PCIE_MIMRXWDATA61", + "TRNRD96": "PCIE_TRNRD96", + "PIPETX5DATA11": "PCIE_PIPETX5DATA11", + "TRNRREM1": "PCIE_TRNRREM1", + "PIPERX6STATUS1": "PCIE_PIPERX6STATUS1", + "TRNTD12": "PCIE_TRNTD12", + "PIPERX4DATA5": "PCIE_PIPERX4DATA5", + "MIMRXWADDR11": "PCIE_MIMRXWADDR11", + "PIPETX4DATA8": "PCIE_PIPETX4DATA8", + "DBGVECB9": "PCIE_DBGVECB9", + "PIPERX3DATA4": "PCIE_PIPERX3DATA4", + "MIMTXWDATA21": "PCIE_MIMTXWDATA21", + "TRNRDLLPDATA15": "PCIE_TRNRDLLPDATA15", + "CFGDSN18": "PCIE_CFGDSN18", + "PIPETX4DATA10": "PCIE_PIPETX4DATA10", + "TRNRD50": "PCIE_TRNRD50", + "PIPETX7DATA7": "PCIE_PIPETX7DATA7", + "TRNTD126": "PCIE_TRNTD126", + "TRNRD63": "PCIE_TRNRD63", + "TRNRDLLPDATA61": "PCIE_TRNRDLLPDATA61", + "TRNTD92": "PCIE_TRNTD92", + "PIPERX2ELECIDLE": "PCIE_PIPERX2ELECIDLE", + "TRNRDLLPDATA51": "PCIE_TRNRDLLPDATA51", + "XILUNCONNOUT5": "PCIE_XILUNCONNOUT5", + "MIMRXRDATA24": "PCIE_MIMRXRDATA24", + "MIMTXRADDR12": "PCIE_MIMTXRADDR12", + "PIPETX4POWERDOWN0": "PCIE_PIPETX4POWERDOWN0", + "PIPETX1POWERDOWN0": "PCIE_PIPETX1POWERDOWN0", + "CFGDEVCONTROLMAXPAYLOAD0": "PCIE_CFGDEVCONTROLMAXPAYLOAD0", + "EDTCHANNELSIN6": "PCIE_EDTCHANNELSIN6", + "DRPDO0": "PCIE_DRPDO0", + "CFGERRTLPCPLHEADER12": "PCIE_CFGERRTLPCPLHEADER12", + "TRNTDLLPDATA2": "PCIE_TRNTDLLPDATA2", + "TRNTD21": "PCIE_TRNTD21", + "PIPETX3DATA9": "PCIE_PIPETX3DATA9", + "PIPETX2POWERDOWN1": "PCIE_PIPETX2POWERDOWN1", + "CFGREVID7": "PCIE_CFGREVID7", + "TL2ERRHDR27": "PCIE_TL2ERRHDR27", + "TRNRDLLPDATA58": "PCIE_TRNRDLLPDATA58", + "TL2ERRHDR45": "PCIE_TL2ERRHDR45", + "DRPRDY": "PCIE_DRPRDY", + "MIMRXRDATA47": "PCIE_MIMRXRDATA47", + "CFGERRTLPCPLHEADER47": "PCIE_CFGERRTLPCPLHEADER47", + "TL2ERRHDR35": "PCIE_TL2ERRHDR35", + "TL2ERRHDR7": "PCIE_TL2ERRHDR7", + "PIPETX2DATA8": "PCIE_PIPETX2DATA8", + "CFGERRAERHEADERLOG27": "PCIE_CFGERRAERHEADERLOG27", + "PIPERX6CHARISK0": "PCIE_PIPERX6CHARISK0", + "MIMRXWDATA46": "PCIE_MIMRXWDATA46", + "TRNTD64": "PCIE_TRNTD64", + "MIMRXRDATA33": "PCIE_MIMRXRDATA33", + "TRNTD84": "PCIE_TRNTD84", + "TRNRD53": "PCIE_TRNRD53", + "EDTCHANNELSIN4": "PCIE_EDTCHANNELSIN4", + "TRNRD52": "PCIE_TRNRD52", + "PIPERX0DATA14": "PCIE_PIPERX0DATA14", + "DBGSCLRG": "PCIE_DBGSCLRG", + "TL2ASPMSUSPENDCREDITCHECK": "PCIE_TL2ASPMSUSPENDCREDITCHECK", + "CFGPCIELINKSTATE1": "PCIE_CFGPCIELINKSTATE1", + "PIPETX7COMPLIANCE": "PCIE_PIPETX7COMPLIANCE", + "PIPETX3DATA15": "PCIE_PIPETX3DATA15", + "TRNRDLLPDATA53": "PCIE_TRNRDLLPDATA53", + "PIPETX2DATA14": "PCIE_PIPETX2DATA14", + "MIMRXRDATA6": "PCIE_MIMRXRDATA6", + "PIPERX4DATA9": "PCIE_PIPERX4DATA9", + "PIPETX3DATA11": "PCIE_PIPETX3DATA11", + "PL2RECOVERY": "PCIE_PL2RECOVERY", + "MIMTXWDATA52": "PCIE_MIMTXWDATA52", + "LL2SENDASREQL1": "PCIE_LL2SENDASREQL1", + "TRNRDLLPDATA54": "PCIE_TRNRDLLPDATA54", + "CFGERRAERHEADERLOG51": "PCIE_CFGERRAERHEADERLOG51", + "DBGVECA39": "PCIE_DBGVECA39", + "TRNRD19": "PCIE_TRNRD19", + "CFGDSN5": "PCIE_CFGDSN5", + "TL2ERRHDR12": "PCIE_TL2ERRHDR12", + "MIMTXRADDR9": "PCIE_MIMTXRADDR9", + "DRPADDR2": "PCIE_DRPADDR2", + "CFGERRTLPCPLHEADER17": "PCIE_CFGERRTLPCPLHEADER17", + "PIPERX1DATA2": "PCIE_PIPERX1DATA2", + "PIPERX1DATA5": "PCIE_PIPERX1DATA5", + "DBGVECB51": "PCIE_DBGVECB51", + "PIPETX5POWERDOWN0": "PCIE_PIPETX5POWERDOWN0", + "MIMRXWADDR6": "PCIE_MIMRXWADDR6", + "CFGERRTLPCPLHEADER22": "PCIE_CFGERRTLPCPLHEADER22", + "PIPERX7DATA6": "PCIE_PIPERX7DATA6", + "TRNTSRCDSC": "PCIE_TRNTSRCDSC", + "XILUNCONNOUT18": "PCIE_XILUNCONNOUT18", + "TRNRD125": "PCIE_TRNRD125", + "MIMRXWDATA15": "PCIE_MIMRXWDATA15", + "TRNTD44": "PCIE_TRNTD44", + "CFGINTERRUPTDI2": "PCIE_CFGINTERRUPTDI2", + "PIPERX5DATA10": "PCIE_PIPERX5DATA10", + "PIPERX2CHANISALIGNED": "PCIE_PIPERX2CHANISALIGNED", + "TRNRD62": "PCIE_TRNRD62", + "CFGLINKSTATUSAUTOBANDWIDTHSTATUS": "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", + "DBGVECB12": "PCIE_DBGVECB12", + "CFGERRPOSTEDN": "PCIE_CFGERRPOSTEDN", + "MIMRXWDATA17": "PCIE_MIMRXWDATA17", + "TRNFCPD9": "PCIE_TRNFCPD9", + "DRPDI1": "PCIE_DRPDI1", + "PIPETX1DATA6": "PCIE_PIPETX1DATA6", + "MIMTXRDATA32": "PCIE_MIMTXRDATA32", + "MIMTXRADDR1": "PCIE_MIMTXRADDR1", + "TRNRBARHIT2": "PCIE_TRNRBARHIT2", + "TRNTD49": "PCIE_TRNTD49", + "CFGMSGRECEIVEDPMASNAK": "PCIE_CFGMSGRECEIVEDPMASNAK", + "DBGSCLRH": "PCIE_DBGSCLRH", + "CFGMSGDATA3": "PCIE_CFGMSGDATA3", + "PL2RXPMSTATE0": "PCIE_PL2RXPMSTATE0", + "XILUNCONNOUT38": "PCIE_XILUNCONNOUT38", + "CFGERRAERHEADERLOG76": "PCIE_CFGERRAERHEADERLOG76", + "CFGDEVCONTROLNONFATALREPORTINGEN": "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", + "PIPERX4DATA6": "PCIE_PIPERX4DATA6", + "PIPETX2DATA7": "PCIE_PIPETX2DATA7", + "PIPETX0DATA2": "PCIE_PIPETX0DATA2", + "TRNTD67": "PCIE_TRNTD67", + "DBGSCLRF": "PCIE_DBGSCLRF", + "LL2PROTOCOLERR": "PCIE_LL2PROTOCOLERR", + "MIMRXRDATA35": "PCIE_MIMRXRDATA35", + "PIPETX0DATA12": "PCIE_PIPETX0DATA12", + "PIPETX4DATA11": "PCIE_PIPETX4DATA11", + "PIPERX5DATA2": "PCIE_PIPERX5DATA2", + "CFGERRAERHEADERLOG79": "PCIE_CFGERRAERHEADERLOG79", + "TRNFCNPD11": "PCIE_TRNFCNPD11", + "USERRSTN": "PCIE_USERRSTN", + "MIMRXWDATA16": "PCIE_MIMRXWDATA16", + "PIPERX6DATA13": "PCIE_PIPERX6DATA13", + "DRPDI0": "PCIE_DRPDI0", + "MIMRXWDATA8": "PCIE_MIMRXWDATA8", + "PLLTSSMSTATE1": "PCIE_PLLTSSMSTATE1", + "CFGSUBSYSID14": "PCIE_CFGSUBSYSID14", + "PIPERX7DATA8": "PCIE_PIPERX7DATA8", + "TRNFCCPLD9": "PCIE_TRNFCCPLD9", + "TL2ERRHDR58": "PCIE_TL2ERRHDR58", + "DBGVECA49": "PCIE_DBGVECA49", + "CFGINTERRUPTDO2": "PCIE_CFGINTERRUPTDO2", + "TRNTD26": "PCIE_TRNTD26", + "DLRSTN": "PCIE_DLRSTN", + "PIPETX5DATA8": "PCIE_PIPETX5DATA8", + "CFGDSBUSNUMBER3": "PCIE_CFGDSBUSNUMBER3", + "CFGERRTLPCPLHEADER34": "PCIE_CFGERRTLPCPLHEADER34", + "CFGSUBSYSID15": "PCIE_CFGSUBSYSID15", + "TRNRD7": "PCIE_TRNRD7", + "SCANENABLEN": "PCIE_SCANENABLEN", + "LL2TFCINIT1SEQ": "PCIE_LL2TFCINIT1SEQ", + "CFGMSGDATA15": "PCIE_CFGMSGDATA15", + "MIMRXWDATA5": "PCIE_MIMRXWDATA5", + "CFGLINKCONTROLRETRAINLINK": "PCIE_CFGLINKCONTROLRETRAINLINK", + "PIPETX2ELECIDLE": "PCIE_PIPETX2ELECIDLE", + "PIPERX1CHANISALIGNED": "PCIE_PIPERX1CHANISALIGNED", + "TRNTDLLPDATA10": "PCIE_TRNTDLLPDATA10", + "TRNFCNPD5": "PCIE_TRNFCNPD5", + "TRNRDLLPDATA40": "PCIE_TRNRDLLPDATA40", + "CFGLINKCONTROLAUTOBANDWIDTHINTEN": "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "CFGERRAERHEADERLOG108": "PCIE_CFGERRAERHEADERLOG108", + "CFGMGMTBYTEENN1": "PCIE_CFGMGMTBYTEENN1", + "PLDBGVEC3": "PCIE_PLDBGVEC3", + "TRNRD103": "PCIE_TRNRD103", + "DBGSCLRK": "PCIE_DBGSCLRK", + "LL2LINKSTATUS4": "PCIE_LL2LINKSTATUS4", + "CFGPMCSRPOWERSTATE1": "PCIE_CFGPMCSRPOWERSTATE1", + "CFGMSGRECEIVEDUNLOCK": "PCIE_CFGMSGRECEIVEDUNLOCK", + "PIPETX6CHARISK0": "PCIE_PIPETX6CHARISK0", + "CFGERRAERHEADERLOG57": "PCIE_CFGERRAERHEADERLOG57", + "CFGPORTNUMBER0": "PCIE_CFGPORTNUMBER0", + "LL2REPLAYROERR": "PCIE_LL2REPLAYROERR", + "DBGVECA20": "PCIE_DBGVECA20", + "CFGDSN59": "PCIE_CFGDSN59", + "CFGMGMTDWADDR6": "PCIE_CFGMGMTDWADDR6", + "CFGVENDID15": "PCIE_CFGVENDID15", + "MIMTXRDATA47": "PCIE_MIMTXRDATA47", + "CFGDSN43": "PCIE_CFGDSN43", + "MIMTXRDATA51": "PCIE_MIMTXRDATA51", + "TRNTD116": "PCIE_TRNTD116", + "TRNRD27": "PCIE_TRNRD27", + "PIPERX2CHARISK1": "PCIE_PIPERX2CHARISK1", + "CFGLINKCONTROLASPMCONTROL1": "PCIE_CFGLINKCONTROLASPMCONTROL1", + "TRNRDLLPDATA30": "PCIE_TRNRDLLPDATA30", + "MIMTXWDATA22": "PCIE_MIMTXWDATA22", + "CFGDEVCONTROL2IDOREQEN": "PCIE_CFGDEVCONTROL2IDOREQEN", + "PIPETX2DATA3": "PCIE_PIPETX2DATA3", + "CFGERRAERHEADERLOG105": "PCIE_CFGERRAERHEADERLOG105", + "TRNTD124": "PCIE_TRNTD124", + "MIMTXWDATA16": "PCIE_MIMTXWDATA16", + "PIPERX2DATA4": "PCIE_PIPERX2DATA4", + "CFGMGMTRDENN": "PCIE_CFGMGMTRDENN", + "MIMRXRDATA30": "PCIE_MIMRXRDATA30", + "PLDBGVEC11": "PCIE_PLDBGVEC11", + "PIPETX1DATA15": "PCIE_PIPETX1DATA15", + "TRNFCNPD1": "PCIE_TRNFCNPD1", + "CFGDEVCONTROLURERRREPORTINGEN": "PCIE_CFGDEVCONTROLURERRREPORTINGEN", + "TRNTDLLPDATA31": "PCIE_TRNTDLLPDATA31", + "TRNRDSTRDY": "PCIE_TRNRDSTRDY", + "DBGVECA12": "PCIE_DBGVECA12", + "LL2SENDENTERL1": "PCIE_LL2SENDENTERL1", + "DBGVECA32": "PCIE_DBGVECA32", + "TRNRD112": "PCIE_TRNRD112", + "TRNTD112": "PCIE_TRNTD112", + "MIMTXWADDR11": "PCIE_MIMTXWADDR11", + "TL2ERRHDR15": "PCIE_TL2ERRHDR15", + "TRNRD28": "PCIE_TRNRD28", + "DRPDO8": "PCIE_DRPDO8", + "PIPERX7PHYSTATUS": "PCIE_PIPERX7PHYSTATUS", + "PIPETX6POWERDOWN1": "PCIE_PIPETX6POWERDOWN1", + "MIMRXWDATA63": "PCIE_MIMRXWDATA63", + "TL2ERRHDR52": "PCIE_TL2ERRHDR52", + "CFGERRAERHEADERLOG20": "PCIE_CFGERRAERHEADERLOG20", + "LL2BADDLLPERR": "PCIE_LL2BADDLLPERR", + "TL2ERRHDR42": "PCIE_TL2ERRHDR42", + "TRNRD127": "PCIE_TRNRD127", + "CFGCOMMANDMEMENABLE": "PCIE_CFGCOMMANDMEMENABLE", + "TRNRSRCRDY": "PCIE_TRNRSRCRDY", + "DBGVECB24": "PCIE_DBGVECB24", + "CFGPMCSRPMESTATUS": "PCIE_CFGPMCSRPMESTATUS", + "PIPETX5CHARISK1": "PCIE_PIPETX5CHARISK1", + "CFGERRAERHEADERLOG99": "PCIE_CFGERRAERHEADERLOG99", + "MIMRXRDATA16": "PCIE_MIMRXRDATA16", + "PIPERX4DATA14": "PCIE_PIPERX4DATA14", + "TRNRD48": "PCIE_TRNRD48", + "PIPERX6DATA9": "PCIE_PIPERX6DATA9", + "CFGINTERRUPTDO1": "PCIE_CFGINTERRUPTDO1", + "TRNRD118": "PCIE_TRNRD118", + "PIPERX0ELECIDLE": "PCIE_PIPERX0ELECIDLE", + "CFGERRAERHEADERLOG61": "PCIE_CFGERRAERHEADERLOG61", + "CFGDSBUSNUMBER2": "PCIE_CFGDSBUSNUMBER2", + "CFGERRAERHEADERLOG13": "PCIE_CFGERRAERHEADERLOG13", + "TRNRDLLPDATA23": "PCIE_TRNRDLLPDATA23", + "MIMTXRDATA50": "PCIE_MIMTXRDATA50", + "PIPERX5STATUS2": "PCIE_PIPERX5STATUS2", + "CFGERRINTERNALCORN": "PCIE_CFGERRINTERNALCORN", + "TRNFCCPLD10": "PCIE_TRNFCCPLD10", + "CFGLINKSTATUSCURRENTSPEED0": "PCIE_CFGLINKSTATUSCURRENTSPEED0", + "TRNFCPD1": "PCIE_TRNFCPD1", + "CFGERRTLPCPLHEADER3": "PCIE_CFGERRTLPCPLHEADER3", + "MIMTXRDATA39": "PCIE_MIMTXRDATA39", + "PIPETX3CHARISK1": "PCIE_PIPETX3CHARISK1", + "TRNTCFGREQ": "PCIE_TRNTCFGREQ", + "CFGLINKCONTROLBANDWIDTHINTEN": "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", + "TL2ASPMSUSPENDCREDITCHECKOK": "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", + "TRNFCCPLD11": "PCIE_TRNFCCPLD11", + "CFGTRANSACTIONADDR2": "PCIE_CFGTRANSACTIONADDR2", + "MIMRXWDATA50": "PCIE_MIMRXWDATA50", + "CFGERRAERHEADERLOG124": "PCIE_CFGERRAERHEADERLOG124", + "CFGDSBUSNUMBER5": "PCIE_CFGDSBUSNUMBER5", + "TRNTD16": "PCIE_TRNTD16", + "PIPETX1DATA4": "PCIE_PIPETX1DATA4", + "MIMRXWDATA26": "PCIE_MIMRXWDATA26", + "CFGDSN48": "PCIE_CFGDSN48", + "PIPETX0DATA3": "PCIE_PIPETX0DATA3", + "MIMTXRDATA45": "PCIE_MIMTXRDATA45", + "TRNFCPD5": "PCIE_TRNFCPD5", + "CFGPMHALTASPML0SN": "PCIE_CFGPMHALTASPML0SN", + "PIPERX1DATA13": "PCIE_PIPERX1DATA13", + "DRPDI2": "PCIE_DRPDI2", + "PIPERX0DATA15": "PCIE_PIPERX0DATA15", + "MIMRXRDATA7": "PCIE_MIMRXRDATA7", + "PIPERX7DATA1": "PCIE_PIPERX7DATA1", + "DBGVECA13": "PCIE_DBGVECA13", + "MIMRXRDATA39": "PCIE_MIMRXRDATA39", + "CFGERRAERHEADERLOG58": "PCIE_CFGERRAERHEADERLOG58", + "PIPERX4DATA12": "PCIE_PIPERX4DATA12", + "MIMRXWDATA48": "PCIE_MIMRXWDATA48", + "TL2ERRHDR62": "PCIE_TL2ERRHDR62", + "PLDBGVEC5": "PCIE_PLDBGVEC5", + "PIPETX1DATA7": "PCIE_PIPETX1DATA7", + "TRNFCCPLD3": "PCIE_TRNFCCPLD3", + "CFGDSN9": "PCIE_CFGDSN9", + "PIPERX6DATA6": "PCIE_PIPERX6DATA6", + "TRNRD84": "PCIE_TRNRD84", + "CFGERRAERHEADERLOG92": "PCIE_CFGERRAERHEADERLOG92", + "TRNFCNPH4": "PCIE_TRNFCNPH4", + "MIMTXWDATA14": "PCIE_MIMTXWDATA14", + "PIPERX2VALID": "PCIE_PIPERX2VALID", + "CFGMGMTDI22": "PCIE_CFGMGMTDI22", + "TRNRDLLPDATA56": "PCIE_TRNRDLLPDATA56", + "MIMTXRDATA24": "PCIE_MIMTXRDATA24", + "DBGVECA48": "PCIE_DBGVECA48", + "PIPERX7DATA15": "PCIE_PIPERX7DATA15", + "TRNTD105": "PCIE_TRNTD105", + "CFGERRAERHEADERLOG44": "PCIE_CFGERRAERHEADERLOG44", + "TRNRDLLPDATA14": "PCIE_TRNRDLLPDATA14", + "CFGDEVCONTROL2ATOMICEGRESSBLOCK": "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "PIPETX5DATA9": "PCIE_PIPETX5DATA9", + "TL2ERRHDR61": "PCIE_TL2ERRHDR61", + "PLRECEIVEDHOTRST": "PCIE_PLRECEIVEDHOTRST", + "CFGDEVSTATUSNONFATALERRDETECTED": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", + "CFGMGMTDI14": "PCIE_CFGMGMTDI14", + "TRNTD90": "PCIE_TRNTD90", + "TRNRDLLPDATA34": "PCIE_TRNRDLLPDATA34", + "CFGCOMMANDSERREN": "PCIE_CFGCOMMANDSERREN", + "MIMTXRDATA54": "PCIE_MIMTXRDATA54", + "PIPETX6DATA13": "PCIE_PIPETX6DATA13", + "PIPETX1DATA9": "PCIE_PIPETX1DATA9", + "MIMRXWADDR3": "PCIE_MIMRXWADDR3", + "MIMRXRADDR0": "PCIE_MIMRXRADDR0", + "MIMTXRDATA28": "PCIE_MIMTXRDATA28", + "TRNRD45": "PCIE_TRNRD45", + "TRNRD11": "PCIE_TRNRD11", + "MIMTXWDATA46": "PCIE_MIMTXWDATA46", + "DRPADDR6": "PCIE_DRPADDR6", + "TRNRDLLPDATA43": "PCIE_TRNRDLLPDATA43", + "TRNRD47": "PCIE_TRNRD47", + "PLTXPMSTATE1": "PCIE_PLTXPMSTATE1", + "PIPETX1DATA3": "PCIE_PIPETX1DATA3", + "CFGERRTLPCPLHEADER25": "PCIE_CFGERRTLPCPLHEADER25", + "TRNRDLLPDATA28": "PCIE_TRNRDLLPDATA28", + "PIPERX0DATA4": "PCIE_PIPERX0DATA4", + "MIMTXRDATA3": "PCIE_MIMTXRDATA3", + "CFGDEVID4": "PCIE_CFGDEVID4", + "PIPETX5DATA13": "PCIE_PIPETX5DATA13", + "TRNTD73": "PCIE_TRNTD73", + "PIPETX7DATA9": "PCIE_PIPETX7DATA9", + "TL2ERRHDR11": "PCIE_TL2ERRHDR11", + "TRNTD13": "PCIE_TRNTD13", + "CFGMGMTDI18": "PCIE_CFGMGMTDI18", + "DBGVECA19": "PCIE_DBGVECA19", + "DBGVECB14": "PCIE_DBGVECB14", + "PIPERX2DATA2": "PCIE_PIPERX2DATA2", + "CFGSUBSYSVENDID15": "PCIE_CFGSUBSYSVENDID15", + "CFGDSN13": "PCIE_CFGDSN13", + "PIPERX4DATA7": "PCIE_PIPERX4DATA7", + "CFGMGMTDI6": "PCIE_CFGMGMTDI6" + }, + "type": "PCIE_2_1", + "prefix": "PCIE", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_PCIE_INT_INTERFACE_L.json b/artix7/tile_type_PCIE_INT_INTERFACE_L.json index ea7bf13..1759bb5 100644 --- a/artix7/tile_type_PCIE_INT_INTERFACE_L.json +++ b/artix7/tile_type_PCIE_INT_INTERFACE_L.json @@ -1,1526 +1,1526 @@ { - "wires": [ - "INT_INTERFACE_BYP5", - "PCIE_INT_INTERFACE_IMUX_L_DELAY34", - "PCIE_INT_INTERFACE_IMUX_L1", - "PCIE_INT_INTERFACE_IMUX_L31", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_BYP4", - "PCIE_INT_INTERFACE_IMUX_L15", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WL1END3", - "PCIE_INT_INTERFACE_IMUX_L_OUT36", - "INT_INTERFACE_LH10", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_NW4END1", - "PCIE_INT_INTERFACE_IMUX_L12", - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "INT_INTERFACE_LH1", - "PCIE_INT_INTERFACE_IMUX_L_DELAY32", - "PCIE_INT_INTERFACE_IMUX_L_DELAY33", - "PCIE_INT_INTERFACE_IMUX_L5", - "PCIE_INT_INTERFACE_IMUX_L18", - "PCIE_INT_INTERFACE_IMUX_L_OUT35", - "PCIE_INT_INTERFACE_IMUX_L41", - "INT_INTERFACE_BYP3", - "PCIE_INT_INTERFACE_IMUX_L_OUT33", - "PCIE_INT_INTERFACE_IMUX_L_DELAY3", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_LOGIC_OUTS_L4", - "INT_INTERFACE_LH6", - "PCIE_INT_INTERFACE_IMUX_L29", - "INT_INTERFACE_SW4A3", - "PCIE_INT_INTERFACE_IMUX_L_DELAY7", - "PCIE_INT_INTERFACE_IMUX_L_DELAY24", - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "PCIE_INT_INTERFACE_IMUX_L_OUT25", - "INT_INTERFACE_BLOCK_OUTS_L_B2", - "PCIE_INT_INTERFACE_IMUX_L17", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_WW4A2", - "PCIE_INT_INTERFACE_IMUX_L_DELAY35", - "PCIE_INT_INTERFACE_IMUX_L34", - "PCIE_INT_INTERFACE_IMUX_L_OUT46", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_ER1BEG2", - "PCIE_INT_INTERFACE_IMUX_L40", - "INT_INTERFACE_LOGIC_OUTS_L7", - "PCIE_INT_INTERFACE_IMUX_L_DELAY38", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_MONITOR_N", - "PCIE_INT_INTERFACE_IMUX_L13", - "PCIE_INT_INTERFACE_IMUX_L_DELAY42", - "PCIE_INT_INTERFACE_IMUX_L_OUT3", - "PCIE_INT_INTERFACE_IMUX_L38", - "PCIE_INT_INTERFACE_IMUX_L_DELAY1", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_SE4BEG2", - "PCIE_INT_INTERFACE_IMUX_L_DELAY11", - "INT_INTERFACE_LOGIC_OUTS_L18", - "INT_INTERFACE_LOGIC_OUTS_L14", - "PCIE_INT_INTERFACE_IMUX_L_OUT24", - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_SE4C3", - "PCIE_INT_INTERFACE_IMUX_L_OUT2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "INT_INTERFACE_LH8", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_FAN1", - "PCIE_INT_INTERFACE_IMUX_L_DELAY37", - "PCIE_INT_INTERFACE_IMUX_L_DELAY40", - "INT_INTERFACE_SE4BEG0", - "PCIE_INT_INTERFACE_IMUX_L_DELAY46", - "PCIE_INT_INTERFACE_IMUX_L20", - "INT_INTERFACE_LOGIC_OUTS_L8", - "INT_INTERFACE_NE4BEG3", - "PCIE_INT_INTERFACE_IMUX_L24", - "PCIE_INT_INTERFACE_IMUX_L19", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_SW2A3", - "PCIE_INT_INTERFACE_IMUX_L_DELAY31", - "INT_INTERFACE_SW2A2", - "PCIE_INT_INTERFACE_IMUX_L16", - "PCIE_INT_INTERFACE_IMUX_L6", - "INT_INTERFACE_LH5", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_FAN3", - "PCIE_INT_INTERFACE_IMUX_L2", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "INT_INTERFACE_WL1END1", - "PCIE_INT_INTERFACE_IMUX_L_DELAY25", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_WR1END1", - "PCIE_INT_INTERFACE_IMUX_L_OUT44", - "INT_INTERFACE_EE4B0", - "PCIE_INT_INTERFACE_IMUX_L_DELAY18", - "PCIE_INT_INTERFACE_IMUX_L_DELAY41", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_LOGIC_OUTS_L10", - "PCIE_INT_INTERFACE_IMUX_L_OUT10", - "INT_INTERFACE_NW2A3", - "PCIE_INT_INTERFACE_IMUX_L_OUT6", - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "PCIE_INT_INTERFACE_IMUX_L_DELAY17", - "INT_INTERFACE_LH2", - "PCIE_INT_INTERFACE_IMUX_L_DELAY19", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_EE4A2", - "PCIE_INT_INTERFACE_IMUX_L28", - "INT_INTERFACE_SE2A2", - "PCIE_INT_INTERFACE_IMUX_L_OUT31", - "INT_INTERFACE_EE4C1", - "PCIE_INT_INTERFACE_IMUX_L_OUT13", - "INT_INTERFACE_EL1BEG1", - "PCIE_INT_INTERFACE_IMUX_L_OUT40", - "INT_INTERFACE_LOGIC_OUTS_L6", - "PCIE_INT_INTERFACE_IMUX_L_DELAY6", - "PCIE_INT_INTERFACE_IMUX_L23", - "INT_INTERFACE_SW2A1", - "PCIE_INT_INTERFACE_IMUX_L39", - "PCIE_INT_INTERFACE_IMUX_L_OUT19", - "PCIE_INT_INTERFACE_IMUX_L8", - "INT_INTERFACE_NE4C1", - "PCIE_INT_INTERFACE_IMUX_L_DELAY14", - "PCIE_INT_INTERFACE_IMUX_L_OUT12", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_EE4B3", - "PCIE_INT_INTERFACE_IMUX_L44", - "PCIE_INT_INTERFACE_IMUX_L_DELAY16", - "INT_INTERFACE_LOGIC_OUTS_L15", - "INT_INTERFACE_BLOCK_OUTS_L_B1", - "PCIE_INT_INTERFACE_IMUX_L_OUT45", - "PCIE_INT_INTERFACE_IMUX_L_DELAY2", - "INT_INTERFACE_EE4BEG2", - "PCIE_INT_INTERFACE_IMUX_L7", - "INT_INTERFACE_WW4B2", - "PCIE_INT_INTERFACE_IMUX_L_DELAY43", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_EE4B1", - "PCIE_INT_INTERFACE_IMUX_L_OUT21", - "INT_INTERFACE_FAN4", - "PCIE_INT_INTERFACE_IMUX_L_OUT7", - "INT_INTERFACE_BLOCK_OUTS_L_B3", - "INT_INTERFACE_ER1BEG1", - "PCIE_INT_INTERFACE_IMUX_L_OUT26", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_SW4END1", - "PCIE_INT_INTERFACE_IMUX_L25", - "INT_INTERFACE_LH3", - "PCIE_INT_INTERFACE_IMUX_L_OUT16", - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "PCIE_INT_INTERFACE_IMUX_L10", - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "INT_INTERFACE_NW4A1", - "PCIE_INT_INTERFACE_IMUX_L_DELAY20", - "PCIE_INT_INTERFACE_IMUX_L_DELAY21", - "INT_INTERFACE_WW4B3", - "PCIE_INT_INTERFACE_IMUX_L_DELAY36", - "INT_INTERFACE_SE4C1", - "PCIE_INT_INTERFACE_IMUX_L37", - "INT_INTERFACE_SE4C2", - "PCIE_INT_INTERFACE_IMUX_L_DELAY0", - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_LOGIC_OUTS_L19", - "PCIE_INT_INTERFACE_IMUX_L_DELAY27", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_NE4BEG1", - "PCIE_INT_INTERFACE_IMUX_L_OUT11", - "INT_INTERFACE_FAN5", - "PCIE_INT_INTERFACE_IMUX_L_OUT38", - "PCIE_INT_INTERFACE_IMUX_L_DELAY39", - "PCIE_INT_INTERFACE_IMUX_L_OUT14", - "PCIE_INT_INTERFACE_IMUX_L_OUT43", - "INT_INTERFACE_CLK0", - "PCIE_INT_INTERFACE_IMUX_L_OUT9", - "INT_INTERFACE_LOGIC_OUTS_L22", - "PCIE_INT_INTERFACE_IMUX_L_DELAY30", - "PCIE_INT_INTERFACE_IMUX_L_OUT32", - "PCIE_INT_INTERFACE_IMUX_L_DELAY13", - "PCIE_INT_INTERFACE_IMUX_L_DELAY12", - "PCIE_INT_INTERFACE_IMUX_L_OUT30", - "PCIE_INT_INTERFACE_IMUX_L_OUT1", - "INT_INTERFACE_SE4BEG1", - "PCIE_INT_INTERFACE_IMUX_L_DELAY10", - "PCIE_INT_INTERFACE_IMUX_L30", - "INT_INTERFACE_LOGIC_OUTS_L13", - "INT_INTERFACE_NE4BEG2", - "PCIE_INT_INTERFACE_IMUX_L35", - "PCIE_INT_INTERFACE_IMUX_L_DELAY15", - "PCIE_INT_INTERFACE_IMUX_L_DELAY8", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_LOGIC_OUTS_L1", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_EE4A3", - "PCIE_INT_INTERFACE_IMUX_L_OUT42", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_LOGIC_OUTS_L5", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_LOGIC_OUTS_L3", - "PCIE_INT_INTERFACE_IMUX_L_OUT34", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_LOGIC_OUTS_L0", - "PCIE_INT_INTERFACE_IMUX_L9", - "PCIE_INT_INTERFACE_IMUX_L32", - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "INT_INTERFACE_EE2A0", - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "PCIE_INT_INTERFACE_IMUX_L47", - "INT_INTERFACE_WR1END2", - "PCIE_INT_INTERFACE_IMUX_L_OUT0", - "PCIE_INT_INTERFACE_IMUX_L_OUT28", - "PCIE_INT_INTERFACE_IMUX_L33", - "PCIE_INT_INTERFACE_IMUX_L0", - "INT_INTERFACE_LOGIC_OUTS_L21", - "INT_INTERFACE_NW4A0", - "PCIE_INT_INTERFACE_IMUX_L_OUT23", - "INT_INTERFACE_LOGIC_OUTS_L11", - "PCIE_INT_INTERFACE_IMUX_L_OUT29", - "PCIE_INT_INTERFACE_IMUX_L_OUT4", - "PCIE_INT_INTERFACE_IMUX_L_OUT39", - "INT_INTERFACE_SW4END3", - "PCIE_INT_INTERFACE_IMUX_L_DELAY5", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_BYP1", - "PCIE_INT_INTERFACE_IMUX_L_DELAY23", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_LOGIC_OUTS_L23", - "PCIE_INT_INTERFACE_IMUX_L_DELAY45", - "PCIE_INT_INTERFACE_IMUX_L26", - "PCIE_INT_INTERFACE_IMUX_L42", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_LOGIC_OUTS_L_B14", - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "PCIE_INT_INTERFACE_IMUX_L_OUT5", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_LH7", - "PCIE_INT_INTERFACE_IMUX_L43", - "INT_INTERFACE_LOGIC_OUTS_L20", - "PCIE_INT_INTERFACE_IMUX_L_DELAY28", - "PCIE_INT_INTERFACE_IMUX_L21", - "INT_INTERFACE_NW4A2", - "PCIE_INT_INTERFACE_IMUX_L_DELAY44", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_LOGIC_OUTS_L2", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_BYP2", - "PCIE_INT_INTERFACE_IMUX_L3", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_WR1END0", - "PCIE_INT_INTERFACE_IMUX_L_DELAY4", - "PCIE_INT_INTERFACE_IMUX_L27", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_EE2BEG3", - "PCIE_INT_INTERFACE_IMUX_L46", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_WW2END3", - "PCIE_INT_INTERFACE_IMUX_L_OUT18", - "INT_INTERFACE_WW4END0", - "PCIE_INT_INTERFACE_IMUX_L_OUT41", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH9", - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "INT_INTERFACE_BLOCK_OUTS_L_B0", - "INT_INTERFACE_NW4END3", - "PCIE_INT_INTERFACE_IMUX_L_OUT8", - "PCIE_INT_INTERFACE_IMUX_L22", - "PCIE_INT_INTERFACE_IMUX_L_DELAY22", - "PCIE_INT_INTERFACE_IMUX_L_DELAY47", - "INT_INTERFACE_WW4END1", - "PCIE_INT_INTERFACE_IMUX_L11", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_LOGIC_OUTS_L12", - "PCIE_INT_INTERFACE_IMUX_L_OUT17", - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW4END3", - "INT_INTERFACE_LH11", - "PCIE_INT_INTERFACE_IMUX_L_OUT47", - "PCIE_INT_INTERFACE_IMUX_L45", - "INT_INTERFACE_WW4C1", - "PCIE_INT_INTERFACE_IMUX_L_OUT27", - "INT_INTERFACE_EE2A3", - "PCIE_INT_INTERFACE_IMUX_L_DELAY29", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "PCIE_INT_INTERFACE_IMUX_L36", - "INT_INTERFACE_EE4A0", - "PCIE_INT_INTERFACE_IMUX_L14", - "PCIE_INT_INTERFACE_IMUX_L_OUT37", - "PCIE_INT_INTERFACE_IMUX_L_DELAY9", - "PCIE_INT_INTERFACE_IMUX_L_OUT22", - "INT_INTERFACE_FAN7", - "PCIE_INT_INTERFACE_IMUX_L_DELAY26", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_LOGIC_OUTS_L16", - "PCIE_INT_INTERFACE_IMUX_L4", - "PCIE_INT_INTERFACE_IMUX_L_OUT15", - "PCIE_INT_INTERFACE_IMUX_L_OUT20", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_LOGIC_OUTS_L17", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_LOGIC_OUTS_L9" - ], - "sites": [], "pips": { - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L29->>PCIE_INT_INTERFACE_IMUX_L_DELAY29": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY29", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L29", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY14->PCIE_INT_INTERFACE_IMUX_L_OUT14": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT14", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY14", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY25->PCIE_INT_INTERFACE_IMUX_L_OUT25": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT25", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY25", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L0->>PCIE_INT_INTERFACE_IMUX_L_OUT0": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT0", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L0", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY4->PCIE_INT_INTERFACE_IMUX_L_OUT4": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT4", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY4", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY7->PCIE_INT_INTERFACE_IMUX_L_OUT7": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT7", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY7", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L18->>PCIE_INT_INTERFACE_IMUX_L_DELAY18": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY18", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L18", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY11->PCIE_INT_INTERFACE_IMUX_L_OUT11": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT11", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY11", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L44->>PCIE_INT_INTERFACE_IMUX_L_DELAY44": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY44", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L44", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY29->PCIE_INT_INTERFACE_IMUX_L_OUT29": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT29", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY29", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY38->PCIE_INT_INTERFACE_IMUX_L_OUT38": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT38", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY38", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY40->PCIE_INT_INTERFACE_IMUX_L_OUT40": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT40", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY40", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY43->PCIE_INT_INTERFACE_IMUX_L_OUT43": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT43", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY43", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L15->>PCIE_INT_INTERFACE_IMUX_L_OUT15": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT15", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L15", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L9->>PCIE_INT_INTERFACE_IMUX_L_OUT9": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT9", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L9", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L42->>PCIE_INT_INTERFACE_IMUX_L_OUT42": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT42", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L42", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY10->PCIE_INT_INTERFACE_IMUX_L_OUT10": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT10", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY10", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L45->>PCIE_INT_INTERFACE_IMUX_L_OUT45": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT45", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L45", - "is_pseudo": "0" - }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY20->PCIE_INT_INTERFACE_IMUX_L_OUT20": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT20", - "is_directional": "1", "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY20", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15", "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L22->>PCIE_INT_INTERFACE_IMUX_L_DELAY22": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY22", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L22", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L41->>PCIE_INT_INTERFACE_IMUX_L_OUT41": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT41", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L41", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L33->>PCIE_INT_INTERFACE_IMUX_L_DELAY33": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY33", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L33", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY18->PCIE_INT_INTERFACE_IMUX_L_OUT18": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT18", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY18", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L11->>PCIE_INT_INTERFACE_IMUX_L_OUT11": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT11", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L11", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L8->>PCIE_INT_INTERFACE_IMUX_L_DELAY8": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY8", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L8", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY15->PCIE_INT_INTERFACE_IMUX_L_OUT15": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT15", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY15", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY17->PCIE_INT_INTERFACE_IMUX_L_OUT17": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT17", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY17", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L40->>PCIE_INT_INTERFACE_IMUX_L_OUT40": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT40", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L40", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L21->>PCIE_INT_INTERFACE_IMUX_L_OUT21": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT21", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L21", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L2->>PCIE_INT_INTERFACE_IMUX_L_DELAY2": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY2", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L2", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L43->>PCIE_INT_INTERFACE_IMUX_L_OUT43": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT43", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L43", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L41->>PCIE_INT_INTERFACE_IMUX_L_DELAY41": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY41", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L41", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L5->>PCIE_INT_INTERFACE_IMUX_L_DELAY5": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY5", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L5", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L13->>PCIE_INT_INTERFACE_IMUX_L_DELAY13": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY13", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L13", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L36->>PCIE_INT_INTERFACE_IMUX_L_DELAY36": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY36", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L36", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L25->>PCIE_INT_INTERFACE_IMUX_L_DELAY25": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY25", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L25", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY13->PCIE_INT_INTERFACE_IMUX_L_OUT13": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT13", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY13", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L17->>PCIE_INT_INTERFACE_IMUX_L_DELAY17": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY17", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L17", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L39->>PCIE_INT_INTERFACE_IMUX_L_OUT39": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT39", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L39", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY45->PCIE_INT_INTERFACE_IMUX_L_OUT45": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT45", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY45", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L15->>PCIE_INT_INTERFACE_IMUX_L_DELAY15": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY15", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L15", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L30->>PCIE_INT_INTERFACE_IMUX_L_DELAY30": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY30", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L30", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L26->>PCIE_INT_INTERFACE_IMUX_L_OUT26": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT26", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L26", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY22->PCIE_INT_INTERFACE_IMUX_L_OUT22": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT22", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY22", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L34->>PCIE_INT_INTERFACE_IMUX_L_DELAY34": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY34", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L34", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L2->>PCIE_INT_INTERFACE_IMUX_L_OUT2": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT2", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L2", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L1->>PCIE_INT_INTERFACE_IMUX_L_OUT1": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT1", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L1", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L31->>PCIE_INT_INTERFACE_IMUX_L_DELAY31": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY31", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L31", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY5->PCIE_INT_INTERFACE_IMUX_L_OUT5": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT5", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY5", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L38->>PCIE_INT_INTERFACE_IMUX_L_DELAY38": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY38", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L38", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L19->>PCIE_INT_INTERFACE_IMUX_L_DELAY19": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY19", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L19", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L46->>PCIE_INT_INTERFACE_IMUX_L_DELAY46": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY46", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L46", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT20" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L1->>PCIE_INT_INTERFACE_IMUX_L_DELAY1": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY1", - "is_directional": "1", "src_wire": "PCIE_INT_INTERFACE_IMUX_L1", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L35->>PCIE_INT_INTERFACE_IMUX_L_DELAY35": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY35", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L35", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY1" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY9->PCIE_INT_INTERFACE_IMUX_L_OUT9": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L0->>PCIE_INT_INTERFACE_IMUX_L_OUT0": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT9", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY9", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY30->PCIE_INT_INTERFACE_IMUX_L_OUT30": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT30", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY30", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L42->>PCIE_INT_INTERFACE_IMUX_L_DELAY42": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY42", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L42", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L32->>PCIE_INT_INTERFACE_IMUX_L_DELAY32": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY32", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L32", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L6->>PCIE_INT_INTERFACE_IMUX_L_OUT6": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT6", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L6", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L30->>PCIE_INT_INTERFACE_IMUX_L_OUT30": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT30", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L30", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY44->PCIE_INT_INTERFACE_IMUX_L_OUT44": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT44", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY44", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L28->>PCIE_INT_INTERFACE_IMUX_L_OUT28": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT28", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L28", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L12->>PCIE_INT_INTERFACE_IMUX_L_DELAY12": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY12", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L12", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L10->>PCIE_INT_INTERFACE_IMUX_L_OUT10": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT10", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L10", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY41->PCIE_INT_INTERFACE_IMUX_L_OUT41": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT41", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY41", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L37->>PCIE_INT_INTERFACE_IMUX_L_DELAY37": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY37", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L37", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L24->>PCIE_INT_INTERFACE_IMUX_L_DELAY24": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY24", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L24", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY32->PCIE_INT_INTERFACE_IMUX_L_OUT32": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT32", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY32", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L13->>PCIE_INT_INTERFACE_IMUX_L_OUT13": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT13", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L13", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L14->>PCIE_INT_INTERFACE_IMUX_L_DELAY14": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY14", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L14", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY31->PCIE_INT_INTERFACE_IMUX_L_OUT31": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT31", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY31", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY42->PCIE_INT_INTERFACE_IMUX_L_OUT42": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT42", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY42", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L14->>PCIE_INT_INTERFACE_IMUX_L_OUT14": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT14", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L14", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L46->>PCIE_INT_INTERFACE_IMUX_L_OUT46": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT46", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L46", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L7->>PCIE_INT_INTERFACE_IMUX_L_OUT7": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT7", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L7", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L9->>PCIE_INT_INTERFACE_IMUX_L_DELAY9": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY9", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L9", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY1->PCIE_INT_INTERFACE_IMUX_L_OUT1": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT1", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY1", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L8->>PCIE_INT_INTERFACE_IMUX_L_OUT8": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT8", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L8", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L20->>PCIE_INT_INTERFACE_IMUX_L_OUT20": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT20", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L20", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY21->PCIE_INT_INTERFACE_IMUX_L_OUT21": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT21", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY21", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY39->PCIE_INT_INTERFACE_IMUX_L_OUT39": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT39", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY39", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L0->>PCIE_INT_INTERFACE_IMUX_L_DELAY0": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY0", - "is_directional": "1", "src_wire": "PCIE_INT_INTERFACE_IMUX_L0", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L4->>PCIE_INT_INTERFACE_IMUX_L_DELAY4": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY4", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L4", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY24->PCIE_INT_INTERFACE_IMUX_L_OUT24": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT24", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY24", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L23->>PCIE_INT_INTERFACE_IMUX_L_OUT23": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT23", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L23", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY47->PCIE_INT_INTERFACE_IMUX_L_OUT47": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT47", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY47", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L28->>PCIE_INT_INTERFACE_IMUX_L_DELAY28": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY28", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L28", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY12->PCIE_INT_INTERFACE_IMUX_L_OUT12": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT12", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY12", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L17->>PCIE_INT_INTERFACE_IMUX_L_OUT17": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT17", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L17", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L31->>PCIE_INT_INTERFACE_IMUX_L_OUT31": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT31", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L31", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY2->PCIE_INT_INTERFACE_IMUX_L_OUT2": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT2", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY2", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L40->>PCIE_INT_INTERFACE_IMUX_L_DELAY40": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY40", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L40", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY6->PCIE_INT_INTERFACE_IMUX_L_OUT6": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT6", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY6", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L47->>PCIE_INT_INTERFACE_IMUX_L_OUT47": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT47", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L47", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L5->>PCIE_INT_INTERFACE_IMUX_L_OUT5": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT5", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L5", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L18->>PCIE_INT_INTERFACE_IMUX_L_OUT18": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT18", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L18", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L26->>PCIE_INT_INTERFACE_IMUX_L_DELAY26": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY26", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L26", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L29->>PCIE_INT_INTERFACE_IMUX_L_OUT29": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT29", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L29", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L34->>PCIE_INT_INTERFACE_IMUX_L_OUT34": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT34", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L34", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L10->>PCIE_INT_INTERFACE_IMUX_L_DELAY10": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY10", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L10", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L24->>PCIE_INT_INTERFACE_IMUX_L_OUT24": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT24", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L24", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L39->>PCIE_INT_INTERFACE_IMUX_L_DELAY39": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY39", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L39", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L7->>PCIE_INT_INTERFACE_IMUX_L_DELAY7": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY7", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L7", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L36->>PCIE_INT_INTERFACE_IMUX_L_OUT36": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT36", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L36", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L19->>PCIE_INT_INTERFACE_IMUX_L_OUT19": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT19", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L19", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY23->PCIE_INT_INTERFACE_IMUX_L_OUT23": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT23", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY23", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY27->PCIE_INT_INTERFACE_IMUX_L_OUT27": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT27", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY27", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L21->>PCIE_INT_INTERFACE_IMUX_L_DELAY21": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY21", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L21", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY33->PCIE_INT_INTERFACE_IMUX_L_OUT33": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT33", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY33", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY26->PCIE_INT_INTERFACE_IMUX_L_OUT26": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT26", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY26", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY35->PCIE_INT_INTERFACE_IMUX_L_OUT35": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT35", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY35", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY46->PCIE_INT_INTERFACE_IMUX_L_OUT46": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT46", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY46", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L47->>PCIE_INT_INTERFACE_IMUX_L_DELAY47": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY47", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L47", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L38->>PCIE_INT_INTERFACE_IMUX_L_OUT38": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT38", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L38", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L25->>PCIE_INT_INTERFACE_IMUX_L_OUT25": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT25", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L25", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L27->>PCIE_INT_INTERFACE_IMUX_L_OUT27": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT27", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L27", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L27->>PCIE_INT_INTERFACE_IMUX_L_DELAY27": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY27", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L27", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY16->PCIE_INT_INTERFACE_IMUX_L_OUT16": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT16", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY16", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY36->PCIE_INT_INTERFACE_IMUX_L_OUT36": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT36", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY36", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY34->PCIE_INT_INTERFACE_IMUX_L_OUT34": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT34", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY34", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L45->>PCIE_INT_INTERFACE_IMUX_L_DELAY45": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY45", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L45", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L3->>PCIE_INT_INTERFACE_IMUX_L_DELAY3": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY3", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L3", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY28->PCIE_INT_INTERFACE_IMUX_L_OUT28": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT28", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY28", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT0" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY3->PCIE_INT_INTERFACE_IMUX_L_OUT3": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT3", - "is_directional": "1", "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY3", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L35->>PCIE_INT_INTERFACE_IMUX_L_OUT35": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT35", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L35", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT3" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L11->>PCIE_INT_INTERFACE_IMUX_L_DELAY11": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L0->>PCIE_INT_INTERFACE_IMUX_L_DELAY0": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY11", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L0", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L11", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY0" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L16->>PCIE_INT_INTERFACE_IMUX_L_DELAY16": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L36->>PCIE_INT_INTERFACE_IMUX_L_OUT36": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY16", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L36", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L16", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT36" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY19->PCIE_INT_INTERFACE_IMUX_L_OUT19": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L20->>PCIE_INT_INTERFACE_IMUX_L_OUT20": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L20", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY19", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT20" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L6->>PCIE_INT_INTERFACE_IMUX_L_DELAY6": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L41->>PCIE_INT_INTERFACE_IMUX_L_OUT41": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY6", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L41", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT41" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L22->>PCIE_INT_INTERFACE_IMUX_L_OUT22": { + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L22", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L4->>PCIE_INT_INTERFACE_IMUX_L_OUT4": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY30->PCIE_INT_INTERFACE_IMUX_L_OUT30": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY30", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT30" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L3->>PCIE_INT_INTERFACE_IMUX_L_OUT3": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY22->PCIE_INT_INTERFACE_IMUX_L_OUT22": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY22", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT22" }, "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": { "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0", - "is_directional": "1", "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY8->PCIE_INT_INTERFACE_IMUX_L_OUT8": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT8", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L12->>PCIE_INT_INTERFACE_IMUX_L_OUT12": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY16->PCIE_INT_INTERFACE_IMUX_L_OUT16": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY16", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L12", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT16" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L33->>PCIE_INT_INTERFACE_IMUX_L_OUT33": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L23->>PCIE_INT_INTERFACE_IMUX_L_OUT23": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L23", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L33", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT23" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY37->PCIE_INT_INTERFACE_IMUX_L_OUT37": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY34->PCIE_INT_INTERFACE_IMUX_L_OUT34": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY34", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY37", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT34" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L43->>PCIE_INT_INTERFACE_IMUX_L_DELAY43": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY19->PCIE_INT_INTERFACE_IMUX_L_OUT19": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY43", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY19", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L43", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT19" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L20->>PCIE_INT_INTERFACE_IMUX_L_DELAY20": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY26->PCIE_INT_INTERFACE_IMUX_L_OUT26": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY20", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY26", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L20", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT26" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L44->>PCIE_INT_INTERFACE_IMUX_L_OUT44": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L35->>PCIE_INT_INTERFACE_IMUX_L_DELAY35": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L35", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L44", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY35" }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY9->PCIE_INT_INTERFACE_IMUX_L_OUT9": { "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY9", "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT9" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L32->>PCIE_INT_INTERFACE_IMUX_L_OUT32": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY46->PCIE_INT_INTERFACE_IMUX_L_OUT46": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY46", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT46" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L2->>PCIE_INT_INTERFACE_IMUX_L_DELAY2": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY2" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY13->PCIE_INT_INTERFACE_IMUX_L_OUT13": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT13" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L15->>PCIE_INT_INTERFACE_IMUX_L_DELAY15": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY15" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L24->>PCIE_INT_INTERFACE_IMUX_L_DELAY24": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY24" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY28->PCIE_INT_INTERFACE_IMUX_L_OUT28": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT28" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY38->PCIE_INT_INTERFACE_IMUX_L_OUT38": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT38" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L38->>PCIE_INT_INTERFACE_IMUX_L_DELAY38": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY38" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY10->PCIE_INT_INTERFACE_IMUX_L_OUT10": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT10" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L40->>PCIE_INT_INTERFACE_IMUX_L_DELAY40": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY40" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L25->>PCIE_INT_INTERFACE_IMUX_L_OUT25": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT25" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L39->>PCIE_INT_INTERFACE_IMUX_L_DELAY39": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY39" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L32->>PCIE_INT_INTERFACE_IMUX_L_DELAY32": { + "can_invert": "0", "src_wire": "PCIE_INT_INTERFACE_IMUX_L32", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7", "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY32" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L37->>PCIE_INT_INTERFACE_IMUX_L_OUT37": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L7->>PCIE_INT_INTERFACE_IMUX_L_DELAY7": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L7", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L37", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY7" }, - "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L16->>PCIE_INT_INTERFACE_IMUX_L_OUT16": { + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY2->PCIE_INT_INTERFACE_IMUX_L_OUT2": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY2", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_L16", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT2" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L2->>PCIE_INT_INTERFACE_IMUX_L_OUT2": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT2" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L7->>PCIE_INT_INTERFACE_IMUX_L_OUT7": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT7" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L5->>PCIE_INT_INTERFACE_IMUX_L_DELAY5": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY5" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L26->>PCIE_INT_INTERFACE_IMUX_L_OUT26": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT26" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY17->PCIE_INT_INTERFACE_IMUX_L_OUT17": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT17" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L21->>PCIE_INT_INTERFACE_IMUX_L_OUT21": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT21" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L12->>PCIE_INT_INTERFACE_IMUX_L_DELAY12": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY12" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY5->PCIE_INT_INTERFACE_IMUX_L_OUT5": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT5" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L22->>PCIE_INT_INTERFACE_IMUX_L_OUT22": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT22" }, "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": { "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10", - "is_directional": "1", "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY42->PCIE_INT_INTERFACE_IMUX_L_OUT42": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT42" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L34->>PCIE_INT_INTERFACE_IMUX_L_DELAY34": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY34" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L18->>PCIE_INT_INTERFACE_IMUX_L_OUT18": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT18" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L28->>PCIE_INT_INTERFACE_IMUX_L_OUT28": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT28" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L33->>PCIE_INT_INTERFACE_IMUX_L_OUT33": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT33" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L45->>PCIE_INT_INTERFACE_IMUX_L_OUT45": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT45" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L28->>PCIE_INT_INTERFACE_IMUX_L_DELAY28": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY28" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L11->>PCIE_INT_INTERFACE_IMUX_L_OUT11": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT11" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L44->>PCIE_INT_INTERFACE_IMUX_L_OUT44": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT44" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L44->>PCIE_INT_INTERFACE_IMUX_L_DELAY44": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY44" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L16->>PCIE_INT_INTERFACE_IMUX_L_DELAY16": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY16" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L21->>PCIE_INT_INTERFACE_IMUX_L_DELAY21": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY21" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY0->PCIE_INT_INTERFACE_IMUX_L_OUT0": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT0", - "is_directional": "1", "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY0", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19", "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT0" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L39->>PCIE_INT_INTERFACE_IMUX_L_OUT39": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT39" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY24->PCIE_INT_INTERFACE_IMUX_L_OUT24": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT24" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L19->>PCIE_INT_INTERFACE_IMUX_L_DELAY19": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY19" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY43->PCIE_INT_INTERFACE_IMUX_L_OUT43": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT43" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L32->>PCIE_INT_INTERFACE_IMUX_L_OUT32": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT32" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L17->>PCIE_INT_INTERFACE_IMUX_L_DELAY17": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY17" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L45->>PCIE_INT_INTERFACE_IMUX_L_DELAY45": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY45" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY18->PCIE_INT_INTERFACE_IMUX_L_OUT18": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT18" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY4->PCIE_INT_INTERFACE_IMUX_L_OUT4": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT4" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY40->PCIE_INT_INTERFACE_IMUX_L_OUT40": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT40" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L26->>PCIE_INT_INTERFACE_IMUX_L_DELAY26": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY26" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L37->>PCIE_INT_INTERFACE_IMUX_L_OUT37": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT37" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L18->>PCIE_INT_INTERFACE_IMUX_L_DELAY18": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY18" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L30->>PCIE_INT_INTERFACE_IMUX_L_OUT30": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT30" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L42->>PCIE_INT_INTERFACE_IMUX_L_DELAY42": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY42" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY12->PCIE_INT_INTERFACE_IMUX_L_OUT12": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT12" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L43->>PCIE_INT_INTERFACE_IMUX_L_DELAY43": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY43" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L42->>PCIE_INT_INTERFACE_IMUX_L_OUT42": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT42" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L23->>PCIE_INT_INTERFACE_IMUX_L_DELAY23": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY23", - "is_directional": "1", "src_wire": "PCIE_INT_INTERFACE_IMUX_L23", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY23" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L20->>PCIE_INT_INTERFACE_IMUX_L_DELAY20": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY20" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L43->>PCIE_INT_INTERFACE_IMUX_L_OUT43": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT43" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L22->>PCIE_INT_INTERFACE_IMUX_L_DELAY22": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY22" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY27->PCIE_INT_INTERFACE_IMUX_L_OUT27": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT27" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L11->>PCIE_INT_INTERFACE_IMUX_L_DELAY11": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY11" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY14->PCIE_INT_INTERFACE_IMUX_L_OUT14": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT14" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY7->PCIE_INT_INTERFACE_IMUX_L_OUT7": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT7" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY1->PCIE_INT_INTERFACE_IMUX_L_OUT1": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT1" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L16->>PCIE_INT_INTERFACE_IMUX_L_OUT16": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT16" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L5->>PCIE_INT_INTERFACE_IMUX_L_OUT5": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT5" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY45->PCIE_INT_INTERFACE_IMUX_L_OUT45": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT45" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY47->PCIE_INT_INTERFACE_IMUX_L_OUT47": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT47" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L3->>PCIE_INT_INTERFACE_IMUX_L_DELAY3": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY3" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY33->PCIE_INT_INTERFACE_IMUX_L_OUT33": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT33" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L25->>PCIE_INT_INTERFACE_IMUX_L_DELAY25": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY25" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L8->>PCIE_INT_INTERFACE_IMUX_L_DELAY8": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY8" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L10->>PCIE_INT_INTERFACE_IMUX_L_OUT10": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT10" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY21->PCIE_INT_INTERFACE_IMUX_L_OUT21": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT21" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY23->PCIE_INT_INTERFACE_IMUX_L_OUT23": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT23" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L37->>PCIE_INT_INTERFACE_IMUX_L_DELAY37": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY37" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L36->>PCIE_INT_INTERFACE_IMUX_L_DELAY36": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY36" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L3->>PCIE_INT_INTERFACE_IMUX_L_OUT3": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT3" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY25->PCIE_INT_INTERFACE_IMUX_L_OUT25": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT25" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY15->PCIE_INT_INTERFACE_IMUX_L_OUT15": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT15" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY6->PCIE_INT_INTERFACE_IMUX_L_OUT6": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT6" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L29->>PCIE_INT_INTERFACE_IMUX_L_DELAY29": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY29" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L19->>PCIE_INT_INTERFACE_IMUX_L_OUT19": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT19" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L17->>PCIE_INT_INTERFACE_IMUX_L_OUT17": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT17" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY11->PCIE_INT_INTERFACE_IMUX_L_OUT11": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT11" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L9->>PCIE_INT_INTERFACE_IMUX_L_OUT9": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT9" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY32->PCIE_INT_INTERFACE_IMUX_L_OUT32": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT32" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L15->>PCIE_INT_INTERFACE_IMUX_L_OUT15": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT15" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L31->>PCIE_INT_INTERFACE_IMUX_L_OUT31": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT31" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY37->PCIE_INT_INTERFACE_IMUX_L_OUT37": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT37" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY8->PCIE_INT_INTERFACE_IMUX_L_OUT8": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT8" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L1->>PCIE_INT_INTERFACE_IMUX_L_OUT1": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT1" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L35->>PCIE_INT_INTERFACE_IMUX_L_OUT35": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT35" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L14->>PCIE_INT_INTERFACE_IMUX_L_DELAY14": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY14" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L33->>PCIE_INT_INTERFACE_IMUX_L_DELAY33": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY33" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L27->>PCIE_INT_INTERFACE_IMUX_L_OUT27": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT27" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L6->>PCIE_INT_INTERFACE_IMUX_L_OUT6": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT6" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY31->PCIE_INT_INTERFACE_IMUX_L_OUT31": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT31" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L4->>PCIE_INT_INTERFACE_IMUX_L_DELAY4": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY4" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L27->>PCIE_INT_INTERFACE_IMUX_L_DELAY27": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY27" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L10->>PCIE_INT_INTERFACE_IMUX_L_DELAY10": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY10" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY44->PCIE_INT_INTERFACE_IMUX_L_OUT44": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT44" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L34->>PCIE_INT_INTERFACE_IMUX_L_OUT34": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT34" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY29->PCIE_INT_INTERFACE_IMUX_L_OUT29": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT29" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L8->>PCIE_INT_INTERFACE_IMUX_L_OUT8": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT8" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L40->>PCIE_INT_INTERFACE_IMUX_L_OUT40": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT40" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L41->>PCIE_INT_INTERFACE_IMUX_L_DELAY41": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY41" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L4->>PCIE_INT_INTERFACE_IMUX_L_OUT4": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT4" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY35->PCIE_INT_INTERFACE_IMUX_L_OUT35": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT35" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L47->>PCIE_INT_INTERFACE_IMUX_L_OUT47": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT47" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L12->>PCIE_INT_INTERFACE_IMUX_L_OUT12": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT12" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L29->>PCIE_INT_INTERFACE_IMUX_L_OUT29": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT29" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L13->>PCIE_INT_INTERFACE_IMUX_L_OUT13": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT13" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L38->>PCIE_INT_INTERFACE_IMUX_L_OUT38": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT38" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L47->>PCIE_INT_INTERFACE_IMUX_L_DELAY47": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY47" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L30->>PCIE_INT_INTERFACE_IMUX_L_DELAY30": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY30" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY36->PCIE_INT_INTERFACE_IMUX_L_OUT36": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT36" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L46->>PCIE_INT_INTERFACE_IMUX_L_DELAY46": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY46" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L6->>PCIE_INT_INTERFACE_IMUX_L_DELAY6": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY6" + }, + "PCIE_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L24->>PCIE_INT_INTERFACE_IMUX_L_OUT24": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT24" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY41->PCIE_INT_INTERFACE_IMUX_L_OUT41": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT41" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L31->>PCIE_INT_INTERFACE_IMUX_L_DELAY31": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY31" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L46->>PCIE_INT_INTERFACE_IMUX_L_OUT46": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT46" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY39->PCIE_INT_INTERFACE_IMUX_L_OUT39": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT39" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L9->>PCIE_INT_INTERFACE_IMUX_L_DELAY9": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY9" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L14->>PCIE_INT_INTERFACE_IMUX_L_OUT14": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT14" + }, + "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L13->>PCIE_INT_INTERFACE_IMUX_L_DELAY13": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_L13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY13" } }, - "tile_type": "PCIE_INT_INTERFACE_L" + "wires": [ + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_WL1END2", + "PCIE_INT_INTERFACE_IMUX_L_OUT28", + "PCIE_INT_INTERFACE_IMUX_L_OUT37", + "PCIE_INT_INTERFACE_IMUX_L38", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_LOGIC_OUTS_L_B3", + "INT_INTERFACE_LOGIC_OUTS_L19", + "PCIE_INT_INTERFACE_IMUX_L_OUT39", + "INT_INTERFACE_SW2A3", + "PCIE_INT_INTERFACE_IMUX_L24", + "INT_INTERFACE_BLOCK_OUTS_L_B0", + "PCIE_INT_INTERFACE_IMUX_L45", + "INT_INTERFACE_WW2A2", + "PCIE_INT_INTERFACE_IMUX_L_OUT47", + "INT_INTERFACE_WW2END0", + "PCIE_INT_INTERFACE_IMUX_L20", + "PCIE_INT_INTERFACE_IMUX_L_OUT19", + "INT_INTERFACE_EE4C1", + "PCIE_INT_INTERFACE_IMUX_L_OUT41", + "PCIE_INT_INTERFACE_IMUX_L_OUT6", + "INT_INTERFACE_SW4A3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY11", + "INT_INTERFACE_EE2BEG3", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_EE4BEG2", + "PCIE_INT_INTERFACE_IMUX_L33", + "PCIE_INT_INTERFACE_IMUX_L12", + "INT_INTERFACE_BYP7", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_SE4BEG0", + "PCIE_INT_INTERFACE_IMUX_L_OUT44", + "INT_INTERFACE_WL1END1", + "PCIE_INT_INTERFACE_IMUX_L_OUT0", + "INT_INTERFACE_NE2A0", + "INT_INTERFACE_LOGIC_OUTS_L_B14", + "PCIE_INT_INTERFACE_IMUX_L_DELAY39", + "INT_INTERFACE_LOGIC_OUTS_L_B5", + "PCIE_INT_INTERFACE_IMUX_L29", + "INT_INTERFACE_EL1BEG0", + "PCIE_INT_INTERFACE_IMUX_L_DELAY47", + "PCIE_INT_INTERFACE_IMUX_L22", + "INT_INTERFACE_CLK0", + "PCIE_INT_INTERFACE_IMUX_L_OUT21", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_EE4B0", + "PCIE_INT_INTERFACE_IMUX_L_OUT17", + "PCIE_INT_INTERFACE_IMUX_L_DELAY2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY27", + "INT_INTERFACE_SW4END0", + "INT_INTERFACE_WW4C2", + "INT_INTERFACE_EE4C2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY6", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_WW4C1", + "PCIE_INT_INTERFACE_IMUX_L_OUT24", + "INT_INTERFACE_LOGIC_OUTS_L23", + "INT_INTERFACE_LOGIC_OUTS_L11", + "PCIE_INT_INTERFACE_IMUX_L_OUT31", + "INT_INTERFACE_EL1BEG1", + "INT_INTERFACE_LH6", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_LOGIC_OUTS_L_B19", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_LOGIC_OUTS_L_B16", + "INT_INTERFACE_NE4BEG3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY38", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_NE2A2", + "PCIE_INT_INTERFACE_IMUX_L_OUT42", + "PCIE_INT_INTERFACE_IMUX_L_DELAY40", + "INT_INTERFACE_FAN7", + "PCIE_INT_INTERFACE_IMUX_L37", + "PCIE_INT_INTERFACE_IMUX_L_OUT20", + "INT_INTERFACE_LH4", + "INT_INTERFACE_LH12", + "PCIE_INT_INTERFACE_IMUX_L_DELAY10", + "INT_INTERFACE_LOGIC_OUTS_L16", + "PCIE_INT_INTERFACE_IMUX_L_DELAY16", + "PCIE_INT_INTERFACE_IMUX_L41", + "PCIE_INT_INTERFACE_IMUX_L_DELAY33", + "PCIE_INT_INTERFACE_IMUX_L_OUT3", + "PCIE_INT_INTERFACE_IMUX_L39", + "INT_INTERFACE_BLOCK_OUTS_L_B3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY42", + "INT_INTERFACE_LOGIC_OUTS_L_B17", + "PCIE_INT_INTERFACE_IMUX_L30", + "PCIE_INT_INTERFACE_IMUX_L6", + "INT_INTERFACE_LOGIC_OUTS_L_B2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY21", + "INT_INTERFACE_WW4END1", + "PCIE_INT_INTERFACE_IMUX_L_DELAY22", + "PCIE_INT_INTERFACE_IMUX_L_OUT5", + "PCIE_INT_INTERFACE_IMUX_L_OUT16", + "INT_INTERFACE_WW2A3", + "INT_INTERFACE_LOGIC_OUTS_L_B13", + "PCIE_INT_INTERFACE_IMUX_L_DELAY35", + "PCIE_INT_INTERFACE_IMUX_L_DELAY14", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_FAN4", + "PCIE_INT_INTERFACE_IMUX_L_OUT7", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_NW4A3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY9", + "INT_INTERFACE_BYP5", + "PCIE_INT_INTERFACE_IMUX_L_OUT45", + "INT_INTERFACE_LOGIC_OUTS_L9", + "PCIE_INT_INTERFACE_IMUX_L_DELAY1", + "PCIE_INT_INTERFACE_IMUX_L_OUT4", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_NE2A3", + "INT_INTERFACE_LOGIC_OUTS_L_B23", + "PCIE_INT_INTERFACE_IMUX_L_DELAY24", + "INT_INTERFACE_SE2A2", + "PCIE_INT_INTERFACE_IMUX_L_OUT22", + "INT_INTERFACE_LOGIC_OUTS_L15", + "PCIE_INT_INTERFACE_IMUX_L44", + "INT_INTERFACE_BYP4", + "PCIE_INT_INTERFACE_IMUX_L_OUT46", + "INT_INTERFACE_LOGIC_OUTS_L21", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_LOGIC_OUTS_L20", + "INT_INTERFACE_LOGIC_OUTS_L14", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_FAN5", + "PCIE_INT_INTERFACE_IMUX_L_DELAY18", + "INT_INTERFACE_EE4B1", + "PCIE_INT_INTERFACE_IMUX_L_OUT40", + "INT_INTERFACE_LOGIC_OUTS_L_B18", + "INT_INTERFACE_EE4BEG0", + "PCIE_INT_INTERFACE_IMUX_L7", + "PCIE_INT_INTERFACE_IMUX_L34", + "INT_INTERFACE_LH9", + "INT_INTERFACE_WW4C3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY28", + "INT_INTERFACE_LOGIC_OUTS_L0", + "PCIE_INT_INTERFACE_IMUX_L_OUT36", + "INT_INTERFACE_LH3", + "PCIE_INT_INTERFACE_IMUX_L_OUT43", + "INT_INTERFACE_NW4END1", + "PCIE_INT_INTERFACE_IMUX_L16", + "PCIE_INT_INTERFACE_IMUX_L_OUT25", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_NE4C3", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_LH10", + "PCIE_INT_INTERFACE_IMUX_L_DELAY29", + "INT_INTERFACE_LOGIC_OUTS_L7", + "PCIE_INT_INTERFACE_IMUX_L_OUT8", + "INT_INTERFACE_WR1END1", + "PCIE_INT_INTERFACE_IMUX_L_DELAY34", + "INT_INTERFACE_LOGIC_OUTS_L_B11", + "INT_INTERFACE_LOGIC_OUTS_L13", + "PCIE_INT_INTERFACE_IMUX_L36", + "INT_INTERFACE_WW4A1", + "PCIE_INT_INTERFACE_IMUX_L_DELAY36", + "PCIE_INT_INTERFACE_IMUX_L47", + "PCIE_INT_INTERFACE_IMUX_L25", + "INT_INTERFACE_LOGIC_OUTS_L_B6", + "INT_INTERFACE_SW2A2", + "PCIE_INT_INTERFACE_IMUX_L4", + "INT_INTERFACE_LOGIC_OUTS_L1", + "PCIE_INT_INTERFACE_IMUX_L_OUT10", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_WW4A3", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LH8", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_WW4B1", + "PCIE_INT_INTERFACE_IMUX_L14", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS_L_B1", + "PCIE_INT_INTERFACE_IMUX_L43", + "PCIE_INT_INTERFACE_IMUX_L_DELAY32", + "PCIE_INT_INTERFACE_IMUX_L_OUT1", + "PCIE_INT_INTERFACE_IMUX_L21", + "PCIE_INT_INTERFACE_IMUX_L18", + "PCIE_INT_INTERFACE_IMUX_L_OUT18", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS_L_B7", + "PCIE_INT_INTERFACE_IMUX_L28", + "PCIE_INT_INTERFACE_IMUX_L_DELAY26", + "INT_INTERFACE_LOGIC_OUTS_L8", + "PCIE_INT_INTERFACE_IMUX_L13", + "INT_INTERFACE_WW2END2", + "PCIE_INT_INTERFACE_IMUX_L_OUT14", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_LOGIC_OUTS_L_B4", + "INT_INTERFACE_LOGIC_OUTS_L_B10", + "INT_INTERFACE_LOGIC_OUTS_L5", + "INT_INTERFACE_EE2BEG1", + "PCIE_INT_INTERFACE_IMUX_L15", + "INT_INTERFACE_MONITOR_P", + "INT_INTERFACE_LOGIC_OUTS_L_B20", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_BLOCK_OUTS_L_B2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY5", + "PCIE_INT_INTERFACE_IMUX_L19", + "PCIE_INT_INTERFACE_IMUX_L_DELAY37", + "INT_INTERFACE_WR1END0", + "PCIE_INT_INTERFACE_IMUX_L9", + "INT_INTERFACE_NW4END0", + "PCIE_INT_INTERFACE_IMUX_L1", + "PCIE_INT_INTERFACE_IMUX_L_DELAY43", + "INT_INTERFACE_SW2A0", + "PCIE_INT_INTERFACE_IMUX_L2", + "INT_INTERFACE_NW4END3", + "PCIE_INT_INTERFACE_IMUX_L35", + "INT_INTERFACE_LOGIC_OUTS_L22", + "PCIE_INT_INTERFACE_IMUX_L10", + "PCIE_INT_INTERFACE_IMUX_L_DELAY3", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_LOGIC_OUTS_L3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY12", + "INT_INTERFACE_WW4B3", + "PCIE_INT_INTERFACE_IMUX_L_OUT13", + "PCIE_INT_INTERFACE_IMUX_L31", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_EE4C3", + "PCIE_INT_INTERFACE_IMUX_L_OUT12", + "INT_INTERFACE_BLOCK_OUTS_L_B1", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_ER1BEG3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY25", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_WL1END0", + "INT_INTERFACE_WW4B0", + "PCIE_INT_INTERFACE_IMUX_L0", + "PCIE_INT_INTERFACE_IMUX_L_DELAY13", + "INT_INTERFACE_SE2A0", + "INT_INTERFACE_LOGIC_OUTS_L_B9", + "INT_INTERFACE_NW2A1", + "PCIE_INT_INTERFACE_IMUX_L_OUT23", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LH1", + "PCIE_INT_INTERFACE_IMUX_L_DELAY46", + "INT_INTERFACE_LH5", + "PCIE_INT_INTERFACE_IMUX_L_DELAY45", + "PCIE_INT_INTERFACE_IMUX_L_OUT32", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_LOGIC_OUTS_L18", + "INT_INTERFACE_NW2A3", + "PCIE_INT_INTERFACE_IMUX_L_OUT30", + "INT_INTERFACE_LOGIC_OUTS_L_B8", + "INT_INTERFACE_LOGIC_OUTS_L2", + "INT_INTERFACE_LOGIC_OUTS_L_B12", + "PCIE_INT_INTERFACE_IMUX_L_DELAY30", + "INT_INTERFACE_EL1BEG3", + "INT_INTERFACE_LOGIC_OUTS_L_B15", + "PCIE_INT_INTERFACE_IMUX_L_OUT33", + "PCIE_INT_INTERFACE_IMUX_L_DELAY0", + "INT_INTERFACE_SE4BEG3", + "PCIE_INT_INTERFACE_IMUX_L27", + "INT_INTERFACE_LOGIC_OUTS_L_B22", + "INT_INTERFACE_LOGIC_OUTS_L_B0", + "PCIE_INT_INTERFACE_IMUX_L_OUT38", + "PCIE_INT_INTERFACE_IMUX_L_DELAY23", + "PCIE_INT_INTERFACE_IMUX_L32", + "PCIE_INT_INTERFACE_IMUX_L_DELAY20", + "PCIE_INT_INTERFACE_IMUX_L_DELAY19", + "PCIE_INT_INTERFACE_IMUX_L42", + "PCIE_INT_INTERFACE_IMUX_L_OUT35", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SE4C1", + "PCIE_INT_INTERFACE_IMUX_L_OUT11", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_EE2A3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY44", + "INT_INTERFACE_WW4A0", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_FAN3", + "PCIE_INT_INTERFACE_IMUX_L_OUT29", + "PCIE_INT_INTERFACE_IMUX_L40", + "PCIE_INT_INTERFACE_IMUX_L_OUT34", + "INT_INTERFACE_CTRL1", + "INT_INTERFACE_LOGIC_OUTS_L10", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_LH7", + "INT_INTERFACE_NW2A2", + "PCIE_INT_INTERFACE_IMUX_L8", + "PCIE_INT_INTERFACE_IMUX_L_DELAY7", + "INT_INTERFACE_SE2A1", + "INT_INTERFACE_WW2A1", + "PCIE_INT_INTERFACE_IMUX_L11", + "PCIE_INT_INTERFACE_IMUX_L3", + "PCIE_INT_INTERFACE_IMUX_L_DELAY15", + "INT_INTERFACE_BYP6", + "INT_INTERFACE_NW4END2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY41", + "PCIE_INT_INTERFACE_IMUX_L23", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_NW4A0", + "PCIE_INT_INTERFACE_IMUX_L_OUT27", + "INT_INTERFACE_WW4END3", + "INT_INTERFACE_WR1END2", + "PCIE_INT_INTERFACE_IMUX_L26", + "INT_INTERFACE_LH2", + "INT_INTERFACE_SW2A1", + "INT_INTERFACE_WW4B2", + "PCIE_INT_INTERFACE_IMUX_L_DELAY31", + "PCIE_INT_INTERFACE_IMUX_L_DELAY8", + "PCIE_INT_INTERFACE_IMUX_L_DELAY17", + "INT_INTERFACE_EE4C0", + "PCIE_INT_INTERFACE_IMUX_L_DELAY4", + "INT_INTERFACE_ER1BEG0", + "PCIE_INT_INTERFACE_IMUX_L_OUT15", + "PCIE_INT_INTERFACE_IMUX_L_OUT9", + "PCIE_INT_INTERFACE_IMUX_L46", + "INT_INTERFACE_WW4END0", + "PCIE_INT_INTERFACE_IMUX_L17", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS_L17", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_EE2A0", + "PCIE_INT_INTERFACE_IMUX_L5", + "INT_INTERFACE_SW4END1", + "INT_INTERFACE_LOGIC_OUTS_L12", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_LOGIC_OUTS_L6", + "INT_INTERFACE_EE2A1", + "PCIE_INT_INTERFACE_IMUX_L_OUT2", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_NE4BEG1", + "INT_INTERFACE_LOGIC_OUTS_L4", + "PCIE_INT_INTERFACE_IMUX_L_OUT26", + "INT_INTERFACE_LOGIC_OUTS_L_B21" + ], + "tile_type": "PCIE_INT_INTERFACE_L", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_PCIE_INT_INTERFACE_R.json b/artix7/tile_type_PCIE_INT_INTERFACE_R.json index e08c584..d63eb76 100644 --- a/artix7/tile_type_PCIE_INT_INTERFACE_R.json +++ b/artix7/tile_type_PCIE_INT_INTERFACE_R.json @@ -1,1526 +1,1526 @@ { - "wires": [ - "INT_INTERFACE_BYP5", - "PCIE_INT_INTERFACE_IMUX_OUT16", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_EE4B2", - "PCIE_INT_INTERFACE_IMUX_OUT19", - "PCIE_INT_INTERFACE_IMUX_DELAY23", - "PCIE_INT_INTERFACE_IMUX29", - "PCIE_INT_INTERFACE_IMUX22", - "INT_INTERFACE_WW2END2", - "PCIE_INT_INTERFACE_IMUX_DELAY40", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_LOGIC_OUTS17", - "PCIE_INT_INTERFACE_IMUX_DELAY8", - "PCIE_INT_INTERFACE_IMUX_OUT12", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_LH10", - "INT_INTERFACE_LOGIC_OUTS16", - "INT_INTERFACE_NW4END1", - "PCIE_INT_INTERFACE_IMUX_DELAY0", - "INT_INTERFACE_SW4A0", - "PCIE_INT_INTERFACE_IMUX_OUT34", - "PCIE_INT_INTERFACE_IMUX_OUT13", - "PCIE_INT_INTERFACE_IMUX_OUT36", - "INT_INTERFACE_BLOCK_OUTS_B0", - "INT_INTERFACE_LH1", - "PCIE_INT_INTERFACE_IMUX16", - "PCIE_INT_INTERFACE_IMUX_OUT14", - "PCIE_INT_INTERFACE_IMUX42", - "PCIE_INT_INTERFACE_IMUX32", - "INT_INTERFACE_LOGIC_OUTS7", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_NW2A1", - "PCIE_INT_INTERFACE_IMUX_DELAY19", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_LH6", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_BLOCK_OUTS_B2", - "PCIE_INT_INTERFACE_IMUX_OUT2", - "PCIE_INT_INTERFACE_IMUX_DELAY7", - "PCIE_INT_INTERFACE_IMUX_OUT39", - "PCIE_INT_INTERFACE_IMUX_OUT43", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_WW4A2", - "PCIE_INT_INTERFACE_IMUX_DELAY44", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_MONITOR_N", - "PCIE_INT_INTERFACE_IMUX_DELAY22", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_FAN2", - "PCIE_INT_INTERFACE_IMUX12", - "PCIE_INT_INTERFACE_IMUX_DELAY31", - "PCIE_INT_INTERFACE_IMUX9", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_LOGIC_OUTS_B23", - "INT_INTERFACE_SE4BEG2", - "PCIE_INT_INTERFACE_IMUX4", - "INT_INTERFACE_LOGIC_OUTS20", - "PCIE_INT_INTERFACE_IMUX_DELAY43", - "INT_INTERFACE_SW4END0", - "PCIE_INT_INTERFACE_IMUX_DELAY25", - "PCIE_INT_INTERFACE_IMUX2", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_SE4C3", - "PCIE_INT_INTERFACE_IMUX26", - "PCIE_INT_INTERFACE_IMUX_OUT38", - "PCIE_INT_INTERFACE_IMUX_OUT23", - "INT_INTERFACE_WR1END3", - "PCIE_INT_INTERFACE_IMUX0", - "INT_INTERFACE_LOGIC_OUTS4", - "PCIE_INT_INTERFACE_IMUX_OUT29", - "INT_INTERFACE_LH8", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_LOGIC_OUTS_B4", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS_B5", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW2A2", - "PCIE_INT_INTERFACE_IMUX_DELAY6", - "PCIE_INT_INTERFACE_IMUX_DELAY38", - "PCIE_INT_INTERFACE_IMUX18", - "INT_INTERFACE_LH5", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_FAN3", - "PCIE_INT_INTERFACE_IMUX_DELAY32", - "PCIE_INT_INTERFACE_IMUX_OUT37", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_LOGIC_OUTS22", - "PCIE_INT_INTERFACE_IMUX_DELAY39", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_EE4B0", - "PCIE_INT_INTERFACE_IMUX_OUT46", - "INT_INTERFACE_CTRL1", - "PCIE_INT_INTERFACE_IMUX_DELAY41", - "PCIE_INT_INTERFACE_IMUX_OUT22", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_LOGIC_OUTS_B6", - "PCIE_INT_INTERFACE_IMUX19", - "PCIE_INT_INTERFACE_IMUX_OUT20", - "INT_INTERFACE_LOGIC_OUTS0", - "PCIE_INT_INTERFACE_IMUX7", - "PCIE_INT_INTERFACE_IMUX27", - "INT_INTERFACE_LH2", - "PCIE_INT_INTERFACE_IMUX_OUT24", - "PCIE_INT_INTERFACE_IMUX_OUT28", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_SE2A2", - "PCIE_INT_INTERFACE_IMUX47", - "INT_INTERFACE_EE4C1", - "PCIE_INT_INTERFACE_IMUX_OUT25", - "PCIE_INT_INTERFACE_IMUX_DELAY27", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_LOGIC_OUTS9", - "PCIE_INT_INTERFACE_IMUX_OUT4", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_NE4C1", - "PCIE_INT_INTERFACE_IMUX_DELAY1", - "PCIE_INT_INTERFACE_IMUX_DELAY28", - "INT_INTERFACE_LOGIC_OUTS15", - "PCIE_INT_INTERFACE_IMUX_OUT18", - "INT_INTERFACE_SE2A3", - "PCIE_INT_INTERFACE_IMUX_OUT1", - "PCIE_INT_INTERFACE_IMUX_DELAY14", - "INT_INTERFACE_SE2A0", - "PCIE_INT_INTERFACE_IMUX23", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_EE4B3", - "PCIE_INT_INTERFACE_IMUX46", - "PCIE_INT_INTERFACE_IMUX_DELAY12", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_WW4B2", - "PCIE_INT_INTERFACE_IMUX_DELAY21", - "INT_INTERFACE_LOGIC_OUTS19", - "PCIE_INT_INTERFACE_IMUX_DELAY37", - "PCIE_INT_INTERFACE_IMUX_OUT6", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_LOGIC_OUTS_B14", - "PCIE_INT_INTERFACE_IMUX21", - "INT_INTERFACE_FAN4", - "PCIE_INT_INTERFACE_IMUX_OUT35", - "INT_INTERFACE_ER1BEG1", - "PCIE_INT_INTERFACE_IMUX_DELAY18", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_SW4END1", - "PCIE_INT_INTERFACE_IMUX1", - "INT_INTERFACE_LH3", - "PCIE_INT_INTERFACE_IMUX25", - "PCIE_INT_INTERFACE_IMUX5", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_NW4A1", - "PCIE_INT_INTERFACE_IMUX13", - "INT_INTERFACE_WW4B3", - "PCIE_INT_INTERFACE_IMUX39", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "PCIE_INT_INTERFACE_IMUX37", - "PCIE_INT_INTERFACE_IMUX33", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE2A1", - "PCIE_INT_INTERFACE_IMUX_DELAY47", - "INT_INTERFACE_BYP6", - "PCIE_INT_INTERFACE_IMUX3", - "INT_INTERFACE_NE4BEG1", - "PCIE_INT_INTERFACE_IMUX_OUT0", - "PCIE_INT_INTERFACE_IMUX_OUT17", - "INT_INTERFACE_FAN5", - "PCIE_INT_INTERFACE_IMUX_DELAY3", - "INT_INTERFACE_LOGIC_OUTS10", - "PCIE_INT_INTERFACE_IMUX_OUT8", - "INT_INTERFACE_CLK0", - "PCIE_INT_INTERFACE_IMUX_DELAY42", - "PCIE_INT_INTERFACE_IMUX_DELAY5", - "INT_INTERFACE_LOGIC_OUTS_B1", - "PCIE_INT_INTERFACE_IMUX_OUT9", - "INT_INTERFACE_LOGIC_OUTS5", - "PCIE_INT_INTERFACE_IMUX_DELAY11", - "PCIE_INT_INTERFACE_IMUX_DELAY35", - "PCIE_INT_INTERFACE_IMUX8", - "INT_INTERFACE_SE4BEG1", - "PCIE_INT_INTERFACE_IMUX_OUT21", - "INT_INTERFACE_LOGIC_OUTS_B9", - "INT_INTERFACE_NE4BEG2", - "PCIE_INT_INTERFACE_IMUX31", - "INT_INTERFACE_LOGIC_OUTS_B18", - "INT_INTERFACE_LOGIC_OUTS_B21", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS21", - "INT_INTERFACE_NE2A3", - "PCIE_INT_INTERFACE_IMUX36", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_NE2A0", - "PCIE_INT_INTERFACE_IMUX24", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_EE4C2", - "PCIE_INT_INTERFACE_IMUX30", - "INT_INTERFACE_SW2A0", - "PCIE_INT_INTERFACE_IMUX_OUT44", - "PCIE_INT_INTERFACE_IMUX14", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_EE2A0", - "PCIE_INT_INTERFACE_IMUX_DELAY29", - "INT_INTERFACE_LOGIC_OUTS1", - "PCIE_INT_INTERFACE_IMUX_OUT11", - "INT_INTERFACE_LOGIC_OUTS3", - "INT_INTERFACE_WR1END2", - "PCIE_INT_INTERFACE_IMUX_OUT47", - "PCIE_INT_INTERFACE_IMUX_DELAY20", - "PCIE_INT_INTERFACE_IMUX_DELAY46", - "PCIE_INT_INTERFACE_IMUX_DELAY4", - "PCIE_INT_INTERFACE_IMUX6", - "PCIE_INT_INTERFACE_IMUX_OUT15", - "PCIE_INT_INTERFACE_IMUX28", - "INT_INTERFACE_NW4A0", - "PCIE_INT_INTERFACE_IMUX44", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_BYP1", - "PCIE_INT_INTERFACE_IMUX15", - "INT_INTERFACE_WW4C3", - "PCIE_INT_INTERFACE_IMUX_DELAY2", - "PCIE_INT_INTERFACE_IMUX_OUT27", - "PCIE_INT_INTERFACE_IMUX20", - "INT_INTERFACE_LOGIC_OUTS12", - "PCIE_INT_INTERFACE_IMUX34", - "INT_INTERFACE_CLK1", - "PCIE_INT_INTERFACE_IMUX_DELAY10", - "PCIE_INT_INTERFACE_IMUX_OUT31", - "INT_INTERFACE_WW4END2", - "PCIE_INT_INTERFACE_IMUX_OUT32", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_LH7", - "INT_INTERFACE_LOGIC_OUTS11", - "PCIE_INT_INTERFACE_IMUX_DELAY45", - "INT_INTERFACE_BLOCK_OUTS_B3", - "PCIE_INT_INTERFACE_IMUX_OUT30", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_NW4A2", - "PCIE_INT_INTERFACE_IMUX17", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_LOGIC_OUTS18", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_BYP2", - "PCIE_INT_INTERFACE_IMUX11", - "INT_INTERFACE_LOGIC_OUTS_B12", - "PCIE_INT_INTERFACE_IMUX_OUT45", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_WW4A3", - "PCIE_INT_INTERFACE_IMUX_OUT33", - "PCIE_INT_INTERFACE_IMUX40", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_SE4BEG3", - "PCIE_INT_INTERFACE_IMUX45", - "PCIE_INT_INTERFACE_IMUX_OUT10", - "INT_INTERFACE_LOGIC_OUTS13", - "INT_INTERFACE_LOGIC_OUTS6", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_WW4C0", - "PCIE_INT_INTERFACE_IMUX_OUT26", - "INT_INTERFACE_NE4BEG0", - "PCIE_INT_INTERFACE_IMUX_OUT5", - "PCIE_INT_INTERFACE_IMUX38", - "PCIE_INT_INTERFACE_IMUX43", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_LH12", - "PCIE_INT_INTERFACE_IMUX_DELAY36", - "INT_INTERFACE_LH9", - "PCIE_INT_INTERFACE_IMUX35", - "INT_INTERFACE_NW4END3", - "PCIE_INT_INTERFACE_IMUX_DELAY15", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WL1END2", - "PCIE_INT_INTERFACE_IMUX_DELAY34", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_WW4C2", - "PCIE_INT_INTERFACE_IMUX_DELAY13", - "PCIE_INT_INTERFACE_IMUX41", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW4END3", - "INT_INTERFACE_LH11", - "INT_INTERFACE_WW4C1", - "PCIE_INT_INTERFACE_IMUX_DELAY16", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_LOGIC_OUTS2", - "INT_INTERFACE_SE4C0", - "PCIE_INT_INTERFACE_IMUX_DELAY17", - "INT_INTERFACE_LOGIC_OUTS23", - "INT_INTERFACE_EE2A2", - "PCIE_INT_INTERFACE_IMUX_DELAY9", - "INT_INTERFACE_EE4A0", - "PCIE_INT_INTERFACE_IMUX_OUT42", - "PCIE_INT_INTERFACE_IMUX_DELAY24", - "PCIE_INT_INTERFACE_IMUX_DELAY30", - "INT_INTERFACE_LOGIC_OUTS14", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_LOGIC_OUTS_B2", - "INT_INTERFACE_NE2A1", - "PCIE_INT_INTERFACE_IMUX_DELAY33", - "INT_INTERFACE_LOGIC_OUTS_B11", - "PCIE_INT_INTERFACE_IMUX_DELAY26", - "PCIE_INT_INTERFACE_IMUX_OUT40", - "PCIE_INT_INTERFACE_IMUX_OUT3", - "PCIE_INT_INTERFACE_IMUX_OUT7", - "INT_INTERFACE_FAN0", - "PCIE_INT_INTERFACE_IMUX10", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A0", - "PCIE_INT_INTERFACE_IMUX_OUT41", - "INT_INTERFACE_BLOCK_OUTS_B1" - ], - "sites": [], "pips": { - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX24->>PCIE_INT_INTERFACE_IMUX_OUT24": { + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT24", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B22", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX24", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX5->>PCIE_INT_INTERFACE_IMUX_OUT5": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT5", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX5", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX7->>PCIE_INT_INTERFACE_IMUX_DELAY7": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY7", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX7", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX22->>PCIE_INT_INTERFACE_IMUX_OUT22": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT22", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX22", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX10->>PCIE_INT_INTERFACE_IMUX_DELAY10": { - "can_invert": "0", - "dst_wire": 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"PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX11->>PCIE_INT_INTERFACE_IMUX_OUT11": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT11", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX11", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX37->>PCIE_INT_INTERFACE_IMUX_DELAY37": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY37", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX37", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS15", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX35->>PCIE_INT_INTERFACE_IMUX_DELAY35": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY35", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX35", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS20", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B20", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY47->PCIE_INT_INTERFACE_IMUX_OUT47": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT47", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY47", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS14", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY42->PCIE_INT_INTERFACE_IMUX_OUT42": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT42", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY42", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS10", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX15->>PCIE_INT_INTERFACE_IMUX_DELAY15": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY15", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX15", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX44->>PCIE_INT_INTERFACE_IMUX_DELAY44": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY44", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX44", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS2", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX40->>PCIE_INT_INTERFACE_IMUX_DELAY40": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY40", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX40", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY33->PCIE_INT_INTERFACE_IMUX_OUT33": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT33", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY33", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX31->>PCIE_INT_INTERFACE_IMUX_OUT31": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT31", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX31", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY6->PCIE_INT_INTERFACE_IMUX_OUT6": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT6", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY6", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY10->PCIE_INT_INTERFACE_IMUX_OUT10": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT10", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY10", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY28->PCIE_INT_INTERFACE_IMUX_OUT28": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT28", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY28", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX27->>PCIE_INT_INTERFACE_IMUX_OUT27": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT27", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX27", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX5->>PCIE_INT_INTERFACE_IMUX_DELAY5": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY5", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX5", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS23", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS18", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY7->PCIE_INT_INTERFACE_IMUX_OUT7": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT7", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY7", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX24->>PCIE_INT_INTERFACE_IMUX_DELAY24": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY24", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX24", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX32->>PCIE_INT_INTERFACE_IMUX_DELAY32": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY32", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX32", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX3->>PCIE_INT_INTERFACE_IMUX_DELAY3": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY3", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX3", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX28->>PCIE_INT_INTERFACE_IMUX_OUT28": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT28", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX28", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX32->>PCIE_INT_INTERFACE_IMUX_OUT32": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT32", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX32", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX7->>PCIE_INT_INTERFACE_IMUX_OUT7": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT7", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX7", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX4->>PCIE_INT_INTERFACE_IMUX_DELAY4": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY4", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX4", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX36->>PCIE_INT_INTERFACE_IMUX_OUT36": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT36", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX36", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX20->>PCIE_INT_INTERFACE_IMUX_OUT20": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT20", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX20", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX9->>PCIE_INT_INTERFACE_IMUX_OUT9": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT9", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX9", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY18->PCIE_INT_INTERFACE_IMUX_OUT18": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT18", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY18", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX47->>PCIE_INT_INTERFACE_IMUX_DELAY47": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY47", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX47", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY9->PCIE_INT_INTERFACE_IMUX_OUT9": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT9", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY9", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX17->>PCIE_INT_INTERFACE_IMUX_OUT17": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT17", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX17", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX35->>PCIE_INT_INTERFACE_IMUX_OUT35": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT35", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX35", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX14->>PCIE_INT_INTERFACE_IMUX_DELAY14": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY14", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX14", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX34->>PCIE_INT_INTERFACE_IMUX_DELAY34": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY34", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX34", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY0->PCIE_INT_INTERFACE_IMUX_OUT0": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT0", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY0", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX33->>PCIE_INT_INTERFACE_IMUX_OUT33": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT33", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX33", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY27->PCIE_INT_INTERFACE_IMUX_OUT27": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT27", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY27", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY15->PCIE_INT_INTERFACE_IMUX_OUT15": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT15", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY15", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX3->>PCIE_INT_INTERFACE_IMUX_OUT3": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT3", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX3", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY8->PCIE_INT_INTERFACE_IMUX_OUT8": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT8", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY8", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS21", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B21", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX37->>PCIE_INT_INTERFACE_IMUX_OUT37": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT37", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX37", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY22->PCIE_INT_INTERFACE_IMUX_OUT22": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT22", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY22", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY4->PCIE_INT_INTERFACE_IMUX_OUT4": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT4", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY4", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX36->>PCIE_INT_INTERFACE_IMUX_DELAY36": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY36", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX36", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX18->>PCIE_INT_INTERFACE_IMUX_DELAY18": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY18", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX18", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY37->PCIE_INT_INTERFACE_IMUX_OUT37": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT37", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY37", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY21->PCIE_INT_INTERFACE_IMUX_OUT21": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT21", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY21", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS22" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY25->PCIE_INT_INTERFACE_IMUX_OUT25": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT25", - "is_directional": "1", "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY25", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY26->PCIE_INT_INTERFACE_IMUX_OUT26": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT26", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY26", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT25" }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY20->PCIE_INT_INTERFACE_IMUX_OUT20": { + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY18->PCIE_INT_INTERFACE_IMUX_OUT18": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT20", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY18", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY20", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT18" }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX12->>PCIE_INT_INTERFACE_IMUX_DELAY12": { + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX22->>PCIE_INT_INTERFACE_IMUX_OUT22": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY12", + "src_wire": "PCIE_INT_INTERFACE_IMUX22", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX12", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT22" }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": { + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY39->PCIE_INT_INTERFACE_IMUX_OUT39": { "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS8", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY39", "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT39" }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY29->PCIE_INT_INTERFACE_IMUX_OUT29": { + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX5->>PCIE_INT_INTERFACE_IMUX_OUT5": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT29", + "src_wire": "PCIE_INT_INTERFACE_IMUX5", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY29", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX19->>PCIE_INT_INTERFACE_IMUX_OUT19": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT19", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX19", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS17", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX2->>PCIE_INT_INTERFACE_IMUX_DELAY2": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY2", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX2", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY11->PCIE_INT_INTERFACE_IMUX_OUT11": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT11", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY11", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX15->>PCIE_INT_INTERFACE_IMUX_OUT15": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT15", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX15", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY1->PCIE_INT_INTERFACE_IMUX_OUT1": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT1", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY1", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX21->>PCIE_INT_INTERFACE_IMUX_DELAY21": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY21", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX21", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS16", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX33->>PCIE_INT_INTERFACE_IMUX_DELAY33": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY33", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX33", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS12", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS11", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX46->>PCIE_INT_INTERFACE_IMUX_DELAY46": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY46", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX46", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX41->>PCIE_INT_INTERFACE_IMUX_OUT41": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT41", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX41", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX43->>PCIE_INT_INTERFACE_IMUX_DELAY43": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY43", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX43", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX16->>PCIE_INT_INTERFACE_IMUX_DELAY16": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY16", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX16", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY32->PCIE_INT_INTERFACE_IMUX_OUT32": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT32", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY32", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS22", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B22", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX6->>PCIE_INT_INTERFACE_IMUX_OUT6": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT6", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX6", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX40->>PCIE_INT_INTERFACE_IMUX_OUT40": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT40", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX40", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX45->>PCIE_INT_INTERFACE_IMUX_OUT45": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT45", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX45", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY5->PCIE_INT_INTERFACE_IMUX_OUT5": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT5", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY5", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX19->>PCIE_INT_INTERFACE_IMUX_DELAY19": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY19", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX19", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX25->>PCIE_INT_INTERFACE_IMUX_DELAY25": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY25", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX25", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX13->>PCIE_INT_INTERFACE_IMUX_OUT13": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT13", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX13", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY46->PCIE_INT_INTERFACE_IMUX_OUT46": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT46", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY46", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY40->PCIE_INT_INTERFACE_IMUX_OUT40": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT40", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY40", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX42->>PCIE_INT_INTERFACE_IMUX_OUT42": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT42", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX42", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX29->>PCIE_INT_INTERFACE_IMUX_DELAY29": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY29", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX29", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX23->>PCIE_INT_INTERFACE_IMUX_DELAY23": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY23", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX23", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX29->>PCIE_INT_INTERFACE_IMUX_OUT29": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT29", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX29", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX41->>PCIE_INT_INTERFACE_IMUX_DELAY41": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY41", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX41", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX12->>PCIE_INT_INTERFACE_IMUX_OUT12": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT12", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX12", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX47->>PCIE_INT_INTERFACE_IMUX_OUT47": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT47", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX47", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX27->>PCIE_INT_INTERFACE_IMUX_DELAY27": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY27", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX27", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX43->>PCIE_INT_INTERFACE_IMUX_OUT43": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT43", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX43", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY41->PCIE_INT_INTERFACE_IMUX_OUT41": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT41", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY41", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX6->>PCIE_INT_INTERFACE_IMUX_DELAY6": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY6", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX6", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY30->PCIE_INT_INTERFACE_IMUX_OUT30": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT30", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY30", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX0->>PCIE_INT_INTERFACE_IMUX_DELAY0": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY0", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX0", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS6", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B6", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX44->>PCIE_INT_INTERFACE_IMUX_OUT44": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT44", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX44", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY16->PCIE_INT_INTERFACE_IMUX_OUT16": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT16", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY16", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX1->>PCIE_INT_INTERFACE_IMUX_DELAY1": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY1", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX1", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": { - "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS7", - "is_directional": "1", - "src_wire": "INT_INTERFACE_LOGIC_OUTS_B7", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY24->PCIE_INT_INTERFACE_IMUX_OUT24": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT24", - "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY24", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT5" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY31->PCIE_INT_INTERFACE_IMUX_OUT31": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT31", - "is_directional": "1", "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY31", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX34->>PCIE_INT_INTERFACE_IMUX_OUT34": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT34", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT31" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX41->>PCIE_INT_INTERFACE_IMUX_DELAY41": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY41" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY10->PCIE_INT_INTERFACE_IMUX_OUT10": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT10" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY14->PCIE_INT_INTERFACE_IMUX_OUT14": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT14" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX34->>PCIE_INT_INTERFACE_IMUX_DELAY34": { + "can_invert": "0", "src_wire": "PCIE_INT_INTERFACE_IMUX34", - "is_pseudo": "0" - }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX8->>PCIE_INT_INTERFACE_IMUX_OUT8": { - "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT8", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX8", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY34" }, - "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX46->>PCIE_INT_INTERFACE_IMUX_OUT46": { + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX36->>PCIE_INT_INTERFACE_IMUX_OUT36": { "can_invert": "0", - "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT46", + "src_wire": "PCIE_INT_INTERFACE_IMUX36", "is_directional": "1", - "src_wire": "PCIE_INT_INTERFACE_IMUX46", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT36" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS2" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX42->>PCIE_INT_INTERFACE_IMUX_DELAY42": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY42" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX2->>PCIE_INT_INTERFACE_IMUX_OUT2": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT2" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS18" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX33->>PCIE_INT_INTERFACE_IMUX_OUT33": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT33" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX27->>PCIE_INT_INTERFACE_IMUX_DELAY27": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY27" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX23->>PCIE_INT_INTERFACE_IMUX_OUT23": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT23" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY34->PCIE_INT_INTERFACE_IMUX_OUT34": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT34" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX10->>PCIE_INT_INTERFACE_IMUX_DELAY10": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY10" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX42->>PCIE_INT_INTERFACE_IMUX_OUT42": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT42" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY47->PCIE_INT_INTERFACE_IMUX_OUT47": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT47" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX28->>PCIE_INT_INTERFACE_IMUX_DELAY28": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY28" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX38->>PCIE_INT_INTERFACE_IMUX_DELAY38": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY38" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY0->PCIE_INT_INTERFACE_IMUX_OUT0": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY33->PCIE_INT_INTERFACE_IMUX_OUT33": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT33" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX26->>PCIE_INT_INTERFACE_IMUX_DELAY26": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY26" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX28->>PCIE_INT_INTERFACE_IMUX_OUT28": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT28" }, "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", - "is_directional": "1", "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX40->>PCIE_INT_INTERFACE_IMUX_DELAY40": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY40" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX3->>PCIE_INT_INTERFACE_IMUX_OUT3": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT3" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX36->>PCIE_INT_INTERFACE_IMUX_DELAY36": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY36" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX19->>PCIE_INT_INTERFACE_IMUX_DELAY19": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY19" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX24->>PCIE_INT_INTERFACE_IMUX_OUT24": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT24" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS12" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX44->>PCIE_INT_INTERFACE_IMUX_OUT44": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT44" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY28->PCIE_INT_INTERFACE_IMUX_OUT28": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT28" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY9->PCIE_INT_INTERFACE_IMUX_OUT9": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT9" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX15->>PCIE_INT_INTERFACE_IMUX_DELAY15": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY15" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX11->>PCIE_INT_INTERFACE_IMUX_DELAY11": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY11" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX37->>PCIE_INT_INTERFACE_IMUX_OUT37": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT37" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX34->>PCIE_INT_INTERFACE_IMUX_OUT34": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT34" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY22->PCIE_INT_INTERFACE_IMUX_OUT22": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT22" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX45->>PCIE_INT_INTERFACE_IMUX_OUT45": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT45" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX37->>PCIE_INT_INTERFACE_IMUX_DELAY37": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY37" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX18->>PCIE_INT_INTERFACE_IMUX_DELAY18": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY18" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY42->PCIE_INT_INTERFACE_IMUX_OUT42": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY42", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT42" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY21->PCIE_INT_INTERFACE_IMUX_OUT21": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT21" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS6" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX31->>PCIE_INT_INTERFACE_IMUX_OUT31": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT31" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS7" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX32->>PCIE_INT_INTERFACE_IMUX_OUT32": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT32" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS10" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY24->PCIE_INT_INTERFACE_IMUX_OUT24": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT24" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY32->PCIE_INT_INTERFACE_IMUX_OUT32": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT32" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX14->>PCIE_INT_INTERFACE_IMUX_DELAY14": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY14" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS16" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX31->>PCIE_INT_INTERFACE_IMUX_DELAY31": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY31" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX4->>PCIE_INT_INTERFACE_IMUX_OUT4": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT4" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY46->PCIE_INT_INTERFACE_IMUX_OUT46": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT46" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX10->>PCIE_INT_INTERFACE_IMUX_OUT10": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT10" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX22->>PCIE_INT_INTERFACE_IMUX_DELAY22": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY22" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX13->>PCIE_INT_INTERFACE_IMUX_OUT13": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT13" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY23->PCIE_INT_INTERFACE_IMUX_OUT23": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT23" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY11->PCIE_INT_INTERFACE_IMUX_OUT11": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT11" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX12->>PCIE_INT_INTERFACE_IMUX_DELAY12": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY12" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX27->>PCIE_INT_INTERFACE_IMUX_OUT27": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT27" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX46->>PCIE_INT_INTERFACE_IMUX_DELAY46": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY46" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY8->PCIE_INT_INTERFACE_IMUX_OUT8": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT8" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX7->>PCIE_INT_INTERFACE_IMUX_OUT7": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT7" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY5->PCIE_INT_INTERFACE_IMUX_OUT5": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT5" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX39->>PCIE_INT_INTERFACE_IMUX_OUT39": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT39" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX21->>PCIE_INT_INTERFACE_IMUX_DELAY21": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY21" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX21->>PCIE_INT_INTERFACE_IMUX_OUT21": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT21" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY19->PCIE_INT_INTERFACE_IMUX_OUT19": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT19" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX24->>PCIE_INT_INTERFACE_IMUX_DELAY24": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY24" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX17->>PCIE_INT_INTERFACE_IMUX_OUT17": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT17" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY4->PCIE_INT_INTERFACE_IMUX_OUT4": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT4" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS9" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX15->>PCIE_INT_INTERFACE_IMUX_OUT15": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT15" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS11" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX9->>PCIE_INT_INTERFACE_IMUX_OUT9": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT9" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX4->>PCIE_INT_INTERFACE_IMUX_DELAY4": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY4" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX26->>PCIE_INT_INTERFACE_IMUX_OUT26": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT26" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY12->PCIE_INT_INTERFACE_IMUX_OUT12": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT12" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY35->PCIE_INT_INTERFACE_IMUX_OUT35": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT35" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS5" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS15" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY20->PCIE_INT_INTERFACE_IMUX_OUT20": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT20" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX2->>PCIE_INT_INTERFACE_IMUX_DELAY2": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY2" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX13->>PCIE_INT_INTERFACE_IMUX_DELAY13": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY13" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS1" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX1->>PCIE_INT_INTERFACE_IMUX_DELAY1": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY1" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX47->>PCIE_INT_INTERFACE_IMUX_DELAY47": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY47" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY30->PCIE_INT_INTERFACE_IMUX_OUT30": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT30" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY26->PCIE_INT_INTERFACE_IMUX_OUT26": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT26" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY36->PCIE_INT_INTERFACE_IMUX_OUT36": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT36" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY13->PCIE_INT_INTERFACE_IMUX_OUT13": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT13" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY1->PCIE_INT_INTERFACE_IMUX_OUT1": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT1" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS14" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY16->PCIE_INT_INTERFACE_IMUX_OUT16": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT16" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY3->PCIE_INT_INTERFACE_IMUX_OUT3": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT3" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX30->>PCIE_INT_INTERFACE_IMUX_OUT30": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT30" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY45->PCIE_INT_INTERFACE_IMUX_OUT45": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT45" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX16->>PCIE_INT_INTERFACE_IMUX_OUT16": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT16" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX1->>PCIE_INT_INTERFACE_IMUX_OUT1": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT1" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX23->>PCIE_INT_INTERFACE_IMUX_DELAY23": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY23" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX20->>PCIE_INT_INTERFACE_IMUX_OUT20": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT20" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX16->>PCIE_INT_INTERFACE_IMUX_DELAY16": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY16" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX0->>PCIE_INT_INTERFACE_IMUX_OUT0": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT0" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY6->PCIE_INT_INTERFACE_IMUX_OUT6": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT6" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX45->>PCIE_INT_INTERFACE_IMUX_DELAY45": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY45" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX6->>PCIE_INT_INTERFACE_IMUX_OUT6": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT6" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY43->PCIE_INT_INTERFACE_IMUX_OUT43": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT43" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX32->>PCIE_INT_INTERFACE_IMUX_DELAY32": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY32" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY2->PCIE_INT_INTERFACE_IMUX_OUT2": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT2" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX9->>PCIE_INT_INTERFACE_IMUX_DELAY9": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY9" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX29->>PCIE_INT_INTERFACE_IMUX_DELAY29": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY29" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY15->PCIE_INT_INTERFACE_IMUX_OUT15": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT15" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY17->PCIE_INT_INTERFACE_IMUX_OUT17": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT17" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY7->PCIE_INT_INTERFACE_IMUX_OUT7": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT7" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX29->>PCIE_INT_INTERFACE_IMUX_OUT29": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT29" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY40->PCIE_INT_INTERFACE_IMUX_OUT40": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT40" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY41->PCIE_INT_INTERFACE_IMUX_OUT41": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT41" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX8->>PCIE_INT_INTERFACE_IMUX_OUT8": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT8" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX19->>PCIE_INT_INTERFACE_IMUX_OUT19": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT19" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY37->PCIE_INT_INTERFACE_IMUX_OUT37": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT37" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX40->>PCIE_INT_INTERFACE_IMUX_OUT40": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT40" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX46->>PCIE_INT_INTERFACE_IMUX_OUT46": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT46" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS20" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX39->>PCIE_INT_INTERFACE_IMUX_DELAY39": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY39" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS13" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX6->>PCIE_INT_INTERFACE_IMUX_DELAY6": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY6" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX41->>PCIE_INT_INTERFACE_IMUX_OUT41": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT41" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX8->>PCIE_INT_INTERFACE_IMUX_DELAY8": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY8" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS4" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS23" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX43->>PCIE_INT_INTERFACE_IMUX_OUT43": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT43" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY29->PCIE_INT_INTERFACE_IMUX_OUT29": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT29" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX11->>PCIE_INT_INTERFACE_IMUX_OUT11": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT11" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX25->>PCIE_INT_INTERFACE_IMUX_OUT25": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT25" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX5->>PCIE_INT_INTERFACE_IMUX_DELAY5": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY5" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY27->PCIE_INT_INTERFACE_IMUX_OUT27": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT27" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX7->>PCIE_INT_INTERFACE_IMUX_DELAY7": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY7" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX17->>PCIE_INT_INTERFACE_IMUX_DELAY17": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY17" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX35->>PCIE_INT_INTERFACE_IMUX_OUT35": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT35" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX14->>PCIE_INT_INTERFACE_IMUX_OUT14": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT14" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX47->>PCIE_INT_INTERFACE_IMUX_OUT47": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT47" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX35->>PCIE_INT_INTERFACE_IMUX_DELAY35": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY35" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS17" }, "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": { "can_invert": "0", - "dst_wire": "INT_INTERFACE_LOGIC_OUTS3", - "is_directional": "1", "src_wire": "INT_INTERFACE_LOGIC_OUTS_B3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS3" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX18->>PCIE_INT_INTERFACE_IMUX_OUT18": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT18" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX12->>PCIE_INT_INTERFACE_IMUX_OUT12": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT12" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY38->PCIE_INT_INTERFACE_IMUX_OUT38": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT38" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX33->>PCIE_INT_INTERFACE_IMUX_DELAY33": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY33" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX3->>PCIE_INT_INTERFACE_IMUX_DELAY3": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY3" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS8" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX25->>PCIE_INT_INTERFACE_IMUX_DELAY25": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY25" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX0->>PCIE_INT_INTERFACE_IMUX_DELAY0": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY0" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS21" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY44->PCIE_INT_INTERFACE_IMUX_OUT44": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT44" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX43->>PCIE_INT_INTERFACE_IMUX_DELAY43": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY43" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX20->>PCIE_INT_INTERFACE_IMUX_DELAY20": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY20" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX38->>PCIE_INT_INTERFACE_IMUX_OUT38": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT38" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX44->>PCIE_INT_INTERFACE_IMUX_DELAY44": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX44", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY44" + }, + "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX30->>PCIE_INT_INTERFACE_IMUX_DELAY30": { + "can_invert": "0", + "src_wire": "PCIE_INT_INTERFACE_IMUX30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_INT_INTERFACE_IMUX_DELAY30" + }, + "PCIE_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": { + "can_invert": "0", + "src_wire": "INT_INTERFACE_LOGIC_OUTS_B19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "INT_INTERFACE_LOGIC_OUTS19" } }, - "tile_type": "PCIE_INT_INTERFACE_R" + "wires": [ + "INT_INTERFACE_SE4BEG1", + "INT_INTERFACE_WL1END2", + "INT_INTERFACE_LOGIC_OUTS_B12", + "INT_INTERFACE_EE4A1", + "INT_INTERFACE_LOGIC_OUTS_B10", + "INT_INTERFACE_SW2A3", + "PCIE_INT_INTERFACE_IMUX32", + "PCIE_INT_INTERFACE_IMUX_OUT47", + "PCIE_INT_INTERFACE_IMUX1", + "INT_INTERFACE_LOGIC_OUTS_B22", + "PCIE_INT_INTERFACE_IMUX_OUT24", + "PCIE_INT_INTERFACE_IMUX_DELAY37", + "INT_INTERFACE_LOGIC_OUTS4", + "PCIE_INT_INTERFACE_IMUX7", + "INT_INTERFACE_WW2A2", + "PCIE_INT_INTERFACE_IMUX_OUT40", + "INT_INTERFACE_LOGIC_OUTS_B11", + "INT_INTERFACE_WW2END0", + "INT_INTERFACE_EE4C1", + "PCIE_INT_INTERFACE_IMUX_DELAY3", + "INT_INTERFACE_LOGIC_OUTS18", + "INT_INTERFACE_SW4A3", + "INT_INTERFACE_EE2BEG3", + "PCIE_INT_INTERFACE_IMUX33", + "INT_INTERFACE_WW2END1", + "INT_INTERFACE_SE4C3", + "INT_INTERFACE_LH11", + "INT_INTERFACE_SE4C0", + "INT_INTERFACE_EE4BEG2", + "INT_INTERFACE_BYP7", + "PCIE_INT_INTERFACE_IMUX27", + "INT_INTERFACE_ER1BEG2", + "INT_INTERFACE_EE4BEG3", + "INT_INTERFACE_SE4BEG0", + "INT_INTERFACE_WL1END1", + "INT_INTERFACE_NE2A0", + "PCIE_INT_INTERFACE_IMUX_OUT34", + "PCIE_INT_INTERFACE_IMUX0", + "PCIE_INT_INTERFACE_IMUX_DELAY0", + "PCIE_INT_INTERFACE_IMUX_OUT30", + "INT_INTERFACE_LOGIC_OUTS_B7", + "PCIE_INT_INTERFACE_IMUX_DELAY29", + "PCIE_INT_INTERFACE_IMUX11", + "PCIE_INT_INTERFACE_IMUX24", + "INT_INTERFACE_EL1BEG0", + "INT_INTERFACE_CLK0", + "PCIE_INT_INTERFACE_IMUX15", + "PCIE_INT_INTERFACE_IMUX_DELAY9", + "INT_INTERFACE_EE2A2", + "INT_INTERFACE_BYP0", + "INT_INTERFACE_LOGIC_OUTS17", + "INT_INTERFACE_FAN6", + "INT_INTERFACE_EE4B0", + "INT_INTERFACE_SW4END0", + "PCIE_INT_INTERFACE_IMUX23", + "INT_INTERFACE_WW4C2", + "PCIE_INT_INTERFACE_IMUX20", + "INT_INTERFACE_EE4C2", + "PCIE_INT_INTERFACE_IMUX2", + "PCIE_INT_INTERFACE_IMUX_OUT11", + "INT_INTERFACE_SE4C2", + "INT_INTERFACE_WW4C1", + "PCIE_INT_INTERFACE_IMUX_DELAY10", + "PCIE_INT_INTERFACE_IMUX_DELAY13", + "PCIE_INT_INTERFACE_IMUX_DELAY18", + "INT_INTERFACE_EL1BEG1", + "PCIE_INT_INTERFACE_IMUX_OUT17", + "PCIE_INT_INTERFACE_IMUX3", + "INT_INTERFACE_LH6", + "PCIE_INT_INTERFACE_IMUX_DELAY5", + "INT_INTERFACE_SW4A0", + "INT_INTERFACE_CTRL0", + "INT_INTERFACE_WW2END3", + "INT_INTERFACE_LOGIC_OUTS14", + "PCIE_INT_INTERFACE_IMUX_OUT36", + "INT_INTERFACE_NE4BEG3", + "INT_INTERFACE_LOGIC_OUTS11", + "INT_INTERFACE_EE4B2", + "INT_INTERFACE_NE2A2", + "PCIE_INT_INTERFACE_IMUX13", + "INT_INTERFACE_LOGIC_OUTS5", + "INT_INTERFACE_LOGIC_OUTS10", + "PCIE_INT_INTERFACE_IMUX_DELAY11", + "INT_INTERFACE_FAN7", + "PCIE_INT_INTERFACE_IMUX_OUT39", + "INT_INTERFACE_LH4", + "INT_INTERFACE_LH12", + "PCIE_INT_INTERFACE_IMUX_OUT23", + "PCIE_INT_INTERFACE_IMUX_DELAY15", + "PCIE_INT_INTERFACE_IMUX_OUT27", + "PCIE_INT_INTERFACE_IMUX12", + "INT_INTERFACE_LOGIC_OUTS23", + "PCIE_INT_INTERFACE_IMUX_OUT41", + "PCIE_INT_INTERFACE_IMUX_DELAY8", + "PCIE_INT_INTERFACE_IMUX30", + "PCIE_INT_INTERFACE_IMUX16", + "PCIE_INT_INTERFACE_IMUX_DELAY30", + "INT_INTERFACE_WW4END1", + "PCIE_INT_INTERFACE_IMUX9", + "PCIE_INT_INTERFACE_IMUX36", + "PCIE_INT_INTERFACE_IMUX6", + "PCIE_INT_INTERFACE_IMUX_OUT35", + "INT_INTERFACE_WW2A3", + "PCIE_INT_INTERFACE_IMUX_DELAY39", + "PCIE_INT_INTERFACE_IMUX10", + "PCIE_INT_INTERFACE_IMUX_DELAY14", + "PCIE_INT_INTERFACE_IMUX17", + "INT_INTERFACE_EE4A0", + "INT_INTERFACE_FAN4", + "INT_INTERFACE_BYP3", + "INT_INTERFACE_NW4A3", + "PCIE_INT_INTERFACE_IMUX_OUT6", + "PCIE_INT_INTERFACE_IMUX22", + "PCIE_INT_INTERFACE_IMUX21", + "INT_INTERFACE_BYP5", + "PCIE_INT_INTERFACE_IMUX_DELAY47", + "PCIE_INT_INTERFACE_IMUX40", + "PCIE_INT_INTERFACE_IMUX26", + "INT_INTERFACE_NW2A0", + "INT_INTERFACE_NE2A3", + "PCIE_INT_INTERFACE_IMUX_OUT29", + "INT_INTERFACE_SE2A2", + "INT_INTERFACE_BYP4", + "PCIE_INT_INTERFACE_IMUX31", + "INT_INTERFACE_LOGIC_OUTS_B4", + "PCIE_INT_INTERFACE_IMUX_DELAY16", + "INT_INTERFACE_WW4A2", + "INT_INTERFACE_LOGIC_OUTS_B17", + "PCIE_INT_INTERFACE_IMUX_OUT20", + "INT_INTERFACE_SE2A3", + "INT_INTERFACE_LOGIC_OUTS7", + "INT_INTERFACE_EL1BEG2", + "INT_INTERFACE_FAN5", + "PCIE_INT_INTERFACE_IMUX38", + "PCIE_INT_INTERFACE_IMUX_DELAY6", + "PCIE_INT_INTERFACE_IMUX_OUT16", + "INT_INTERFACE_EE4B1", + "INT_INTERFACE_EE4BEG0", + "INT_INTERFACE_LH9", + "INT_INTERFACE_WW4C3", + "PCIE_INT_INTERFACE_IMUX_DELAY23", + "PCIE_INT_INTERFACE_IMUX_OUT37", + "INT_INTERFACE_LH3", + "INT_INTERFACE_NW4END1", + "INT_INTERFACE_WR1END3", + "INT_INTERFACE_LOGIC_OUTS22", + "INT_INTERFACE_WW2A0", + "INT_INTERFACE_NE4C3", + "PCIE_INT_INTERFACE_IMUX43", + "INT_INTERFACE_EE4BEG1", + "INT_INTERFACE_LH10", + "PCIE_INT_INTERFACE_IMUX_OUT43", + "INT_INTERFACE_LOGIC_OUTS_B15", + "PCIE_INT_INTERFACE_IMUX_DELAY38", + "INT_INTERFACE_LOGIC_OUTS13", + "INT_INTERFACE_WR1END1", + "PCIE_INT_INTERFACE_IMUX_OUT19", + "PCIE_INT_INTERFACE_IMUX_OUT21", + "INT_INTERFACE_LOGIC_OUTS_B9", + "PCIE_INT_INTERFACE_IMUX46", + "PCIE_INT_INTERFACE_IMUX_OUT3", + "INT_INTERFACE_BLOCK_OUTS_B3", + "INT_INTERFACE_WW4A1", + "PCIE_INT_INTERFACE_IMUX_OUT2", + "PCIE_INT_INTERFACE_IMUX_OUT7", + "INT_INTERFACE_SW2A2", + "PCIE_INT_INTERFACE_IMUX4", + "INT_INTERFACE_SE4BEG2", + "INT_INTERFACE_WW4A3", + "PCIE_INT_INTERFACE_IMUX_DELAY36", + "INT_INTERFACE_CLK1", + "INT_INTERFACE_LH8", + "PCIE_INT_INTERFACE_IMUX_DELAY17", + "PCIE_INT_INTERFACE_IMUX_DELAY43", + "INT_INTERFACE_WW4C0", + "INT_INTERFACE_WW4B1", + "PCIE_INT_INTERFACE_IMUX_DELAY28", + "INT_INTERFACE_LOGIC_OUTS1", + "INT_INTERFACE_LOGIC_OUTS0", + "INT_INTERFACE_EE4A2", + "INT_INTERFACE_LOGIC_OUTS20", + "PCIE_INT_INTERFACE_IMUX_OUT18", + "INT_INTERFACE_LOGIC_OUTS_B20", + "PCIE_INT_INTERFACE_IMUX_OUT13", + "INT_INTERFACE_NE4BEG2", + "INT_INTERFACE_LOGIC_OUTS3", + "PCIE_INT_INTERFACE_IMUX_DELAY19", + "INT_INTERFACE_LOGIC_OUTS_B14", + "INT_INTERFACE_BLOCK_OUTS_B2", + "INT_INTERFACE_LOGIC_OUTS_B1", + "INT_INTERFACE_WW2END2", + "PCIE_INT_INTERFACE_IMUX_DELAY26", + "PCIE_INT_INTERFACE_IMUX19", + "INT_INTERFACE_LOGIC_OUTS2", + "PCIE_INT_INTERFACE_IMUX_DELAY40", + "INT_INTERFACE_FAN0", + "INT_INTERFACE_EE2BEG1", + "PCIE_INT_INTERFACE_IMUX29", + "PCIE_INT_INTERFACE_IMUX_OUT28", + "INT_INTERFACE_MONITOR_P", + "PCIE_INT_INTERFACE_IMUX_OUT9", + "INT_INTERFACE_LOGIC_OUTS16", + "PCIE_INT_INTERFACE_IMUX_OUT12", + "INT_INTERFACE_NW4A1", + "INT_INTERFACE_WR1END0", + "INT_INTERFACE_NW4END0", + "PCIE_INT_INTERFACE_IMUX39", + "PCIE_INT_INTERFACE_IMUX_DELAY20", + "INT_INTERFACE_LOGIC_OUTS8", + "PCIE_INT_INTERFACE_IMUX_OUT31", + "INT_INTERFACE_LOGIC_OUTS9", + "PCIE_INT_INTERFACE_IMUX_OUT46", + "INT_INTERFACE_SW2A0", + "PCIE_INT_INTERFACE_IMUX_OUT44", + "PCIE_INT_INTERFACE_IMUX42", + "INT_INTERFACE_NW4END3", + "INT_INTERFACE_LOGIC_OUTS_B21", + "PCIE_INT_INTERFACE_IMUX_OUT1", + "PCIE_INT_INTERFACE_IMUX8", + "INT_INTERFACE_NE4C0", + "INT_INTERFACE_EE4A3", + "INT_INTERFACE_WW4B3", + "INT_INTERFACE_EE2BEG2", + "INT_INTERFACE_EE4C3", + "PCIE_INT_INTERFACE_IMUX_DELAY25", + "PCIE_INT_INTERFACE_IMUX_DELAY44", + "INT_INTERFACE_WL1END3", + "INT_INTERFACE_SW4A2", + "INT_INTERFACE_ER1BEG3", + "PCIE_INT_INTERFACE_IMUX_OUT33", + "PCIE_INT_INTERFACE_IMUX_DELAY27", + "INT_INTERFACE_SW4A1", + "INT_INTERFACE_BYP2", + "INT_INTERFACE_NE2A1", + "INT_INTERFACE_WL1END0", + "PCIE_INT_INTERFACE_IMUX_DELAY22", + "PCIE_INT_INTERFACE_IMUX41", + "PCIE_INT_INTERFACE_IMUX_OUT5", + "PCIE_INT_INTERFACE_IMUX25", + "INT_INTERFACE_WW4B0", + "PCIE_INT_INTERFACE_IMUX5", + "INT_INTERFACE_LOGIC_OUTS_B18", + "PCIE_INT_INTERFACE_IMUX_OUT8", + "INT_INTERFACE_SE2A0", + "PCIE_INT_INTERFACE_IMUX_OUT25", + "INT_INTERFACE_NW2A1", + "PCIE_INT_INTERFACE_IMUX_OUT14", + "PCIE_INT_INTERFACE_IMUX_DELAY21", + "INT_INTERFACE_EE2BEG0", + "INT_INTERFACE_LH1", + "PCIE_INT_INTERFACE_IMUX_DELAY2", + "INT_INTERFACE_LH5", + "INT_INTERFACE_LOGIC_OUTS_B0", + "INT_INTERFACE_LOGIC_OUTS_B3", + "PCIE_INT_INTERFACE_IMUX_OUT4", + "INT_INTERFACE_SW4END2", + "INT_INTERFACE_NW2A3", + "INT_INTERFACE_LOGIC_OUTS19", + "INT_INTERFACE_LOGIC_OUTS_B5", + "PCIE_INT_INTERFACE_IMUX28", + "PCIE_INT_INTERFACE_IMUX37", + "PCIE_INT_INTERFACE_IMUX_DELAY33", + "INT_INTERFACE_EL1BEG3", + "PCIE_INT_INTERFACE_IMUX45", + "INT_INTERFACE_LOGIC_OUTS_B8", + "INT_INTERFACE_LOGIC_OUTS_B6", + "INT_INTERFACE_LOGIC_OUTS_B2", + "INT_INTERFACE_LOGIC_OUTS_B19", + "INT_INTERFACE_SE4BEG3", + "PCIE_INT_INTERFACE_IMUX_DELAY24", + "INT_INTERFACE_NE4C2", + "INT_INTERFACE_SE4C1", + "INT_INTERFACE_LOGIC_OUTS_B13", + "INT_INTERFACE_WW4END2", + "INT_INTERFACE_EE2A3", + "PCIE_INT_INTERFACE_IMUX_DELAY7", + "INT_INTERFACE_WW4A0", + "PCIE_INT_INTERFACE_IMUX18", + "INT_INTERFACE_BYP1", + "INT_INTERFACE_FAN3", + "PCIE_INT_INTERFACE_IMUX_OUT26", + "INT_INTERFACE_CTRL1", + "PCIE_INT_INTERFACE_IMUX34", + "INT_INTERFACE_MONITOR_N", + "INT_INTERFACE_LH7", + "PCIE_INT_INTERFACE_IMUX_OUT42", + "INT_INTERFACE_LOGIC_OUTS_B23", + "INT_INTERFACE_NW2A2", + "INT_INTERFACE_SE2A1", + "PCIE_INT_INTERFACE_IMUX_DELAY35", + "INT_INTERFACE_WW2A1", + "PCIE_INT_INTERFACE_IMUX_OUT0", + "INT_INTERFACE_LOGIC_OUTS21", + "INT_INTERFACE_BYP6", + "PCIE_INT_INTERFACE_IMUX_OUT45", + "PCIE_INT_INTERFACE_IMUX_DELAY1", + "INT_INTERFACE_NW4END2", + "PCIE_INT_INTERFACE_IMUX_DELAY12", + "INT_INTERFACE_EE4B3", + "INT_INTERFACE_LOGIC_OUTS12", + "INT_INTERFACE_SW4END3", + "INT_INTERFACE_NE4C1", + "INT_INTERFACE_NW4A2", + "INT_INTERFACE_NW4A0", + "PCIE_INT_INTERFACE_IMUX_DELAY42", + "INT_INTERFACE_WW4END3", + "PCIE_INT_INTERFACE_IMUX_OUT10", + "INT_INTERFACE_WR1END2", + "PCIE_INT_INTERFACE_IMUX14", + "INT_INTERFACE_LH2", + "PCIE_INT_INTERFACE_IMUX_DELAY34", + "INT_INTERFACE_SW2A1", + "PCIE_INT_INTERFACE_IMUX_DELAY4", + "PCIE_INT_INTERFACE_IMUX44", + "PCIE_INT_INTERFACE_IMUX_OUT38", + "INT_INTERFACE_WW4B2", + "PCIE_INT_INTERFACE_IMUX_DELAY32", + "INT_INTERFACE_EE4C0", + "PCIE_INT_INTERFACE_IMUX35", + "INT_INTERFACE_ER1BEG0", + "INT_INTERFACE_WW4END0", + "INT_INTERFACE_FAN1", + "INT_INTERFACE_LOGIC_OUTS15", + "INT_INTERFACE_LOGIC_OUTS6", + "INT_INTERFACE_NE4BEG0", + "INT_INTERFACE_EE2A0", + "INT_INTERFACE_SW4END1", + "PCIE_INT_INTERFACE_IMUX_DELAY31", + "INT_INTERFACE_FAN2", + "INT_INTERFACE_LOGIC_OUTS_B16", + "PCIE_INT_INTERFACE_IMUX47", + "INT_INTERFACE_EE2A1", + "PCIE_INT_INTERFACE_IMUX_OUT32", + "INT_INTERFACE_BLOCK_OUTS_B0", + "PCIE_INT_INTERFACE_IMUX_OUT15", + "PCIE_INT_INTERFACE_IMUX_DELAY45", + "PCIE_INT_INTERFACE_IMUX_DELAY46", + "PCIE_INT_INTERFACE_IMUX_DELAY41", + "INT_INTERFACE_BLOCK_OUTS_B1", + "PCIE_INT_INTERFACE_IMUX_OUT22", + "INT_INTERFACE_ER1BEG1", + "INT_INTERFACE_NE4BEG1" + ], + "tile_type": "PCIE_INT_INTERFACE_R", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_PCIE_NULL.json b/artix7/tile_type_PCIE_NULL.json index c2331f0..51292f4 100644 --- a/artix7/tile_type_PCIE_NULL.json +++ b/artix7/tile_type_PCIE_NULL.json @@ -1,8 +1,8 @@ { + "pips": {}, "wires": [ "DUMMYFOO" ], - "sites": [], - "pips": {}, - "tile_type": "PCIE_NULL" + "tile_type": "PCIE_NULL", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_PCIE_TOP.json b/artix7/tile_type_PCIE_TOP.json index c007611..da92863 100644 --- a/artix7/tile_type_PCIE_TOP.json +++ b/artix7/tile_type_PCIE_TOP.json @@ -1,5132 +1,5132 @@ { - "wires": [ - "PCIE_IMUX21_L_1", - "PCIE_IMUX24_R_2", - "PCIE_TOP_TRNRD66", - "PCIE_IMUX18_R_3", - "PCIE_FAN5_L_0", - "PCIE_WL1END1_1", - "PCIE_EE4C1_4", - "PCIE_IMUX37_R_3", - "PCIE_TOP_PIPERX4PHYSTATUS", - "PCIE_TOP_CFGDEVID9", - "PCIE_WW4C0_2", - "PCIE_WW4END3_1", - "PCIE_EE2BEG3_3", - "PCIE_SW2A2_4", - "PCIE_TOP_CFGMGMTDO25", - "PCIE_BYP2_L_1", - "PCIE_BYP6_L_2", - "PCIE_LOGIC_OUTS_B21_L_1", - "PCIE_LOGIC_OUTS_B6_L_1", - "PCIE_TOP_TRNRD98", - "PCIE_LOGIC_OUTS_B2_L_1", - "PCIE_IMUX41_R_4", - "PCIE_BYP6_L_1", - "PCIE_IMUX9_R_1", - "PCIE_TOP_TRNRD60", - "PCIE_IMUX10_L_1", - "PCIE_TOP_CFGERRAERHEADERLOG8", - "PCIE_IMUX17_R_3", - "PCIE_TOP_TRNTDLLPDATA28", - "PCIE_SW4END3_2", - "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN", - "PCIE_TOP_TRNTD28", - "PCIE_TOP_CFGPMRCVENTERL1N", - "PCIE_WW4A3_4", - "PCIE_IMUX5_L_0", - "PCIE_TOP_TRNTD41", - "PCIE_TOP_TRNRD67", - "PCIE_TOP_MIMRXREN", - "PCIE_TOP_CFGDEVID1", - "PCIE_TOP_CFGDEVID2", - "PCIE_LOGIC_OUTS_B0_R_1", - "PCIE_LOGIC_OUTS_B7_R_4", - "PCIE_FAN7_L_4", - "PCIE_SW4A3_4", - "PCIE_BLOCK_OUTS_B3_R_4", - "PCIE_EE4B3_4", - "PCIE_MONITOR_P_2", - "PCIE_LOGIC_OUTS_B1_R_4", - "PCIE_LOGIC_OUTS_B2_R_1", - "PCIE_TOP_TRNTD21", - "PCIE_EE2BEG0_4", - "PCIE_IMUX5_R_3", - "PCIE_BLOCK_OUTS_B0_L_4", - "PCIE_IMUX45_L_1", - "PCIE_LOGIC_OUTS_B17_L_1", - "PCIE_LOGIC_OUTS_B17_L_2", - "PCIE_TOP_CFGINTERRUPTN", - "PCIE_SE4C2_3", - "PCIE_TOP_DRPDI2", - "PCIE_EL1BEG3_0", - "PCIE_IMUX36_L_4", - "PCIE_TOP_CFGDSN57", - "PCIE_IMUX32_R_0", - "PCIE_FAN1_R_0", - "PCIE_IMUX30_R_4", - "PCIE_TOP_CFGDEVCONTROL2IDOREQEN", - "PCIE_LOGIC_OUTS_B16_L_1", - "PCIE_WW4B1_4", - "PCIE_TOP_DRPDI7", - "PCIE_FAN5_R_4", - "PCIE_FAN0_R_2", - "PCIE_TOP_MIMRXWDATA11", - "PCIE_WW4C0_3", - "PCIE_IMUX29_R_4", - "PCIE_LOGIC_OUTS_B4_R_4", - "PCIE_TOP_MIMRXWDATA0", - "PCIE_BYP2_R_0", - "PCIE_CTRL1_R_4", - "PCIE_TOP_CFGTRANSACTIONADDR1", - "PCIE_WW4B3_3", - "PCIE_IMUX46_R_0", - "PCIE_IMUX42_R_0", - "PCIE_TOP_TRNTD27", - "PCIE_TOP_CFGDEVID4", - "PCIE_WW2END1_4", - "PCIE_TOP_MIMRXRDATA27", - "PCIE_TOP_CFGVCTCVCMAP5", - "PCIE_EE4C3_1", - "PCIE_IMUX34_L_0", - "PCIE_TOP_TRNRD74", - "PCIE_TOP_DBGVECA7", - "PCIE_SW2A2_2", - "PCIE_IMUX21_R_3", - "PCIE_BYP3_R_1", - "PCIE_NE4C2_1", - "PCIE_FAN4_L_1", - "PCIE_IMUX31_R_1", - "PCIE_SE4C0_1", - "PCIE_IMUX23_R_3", - "PCIE_IMUX19_L_3", - "PCIE_WW2END0_0", - "PCIE_TOP_CFGLINKCONTROLRETRAINLINK", - "PCIE_NE4C2_4", - "PCIE_TOP_CFGDEVID8", - "PCIE_TOP_DRPDI1", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1", - "PCIE_EE4A3_0", - "PCIE_FAN3_R_2", - "PCIE_IMUX26_R_2", - "PCIE_EE4C0_3", - "PCIE_TOP_DBGVECA6", - "PCIE_WW2A3_0", - "PCIE_EE4C1_3", - "PCIE_WW4A1_0", - "PCIE_LOGIC_OUTS_B23_L_0", - "PCIE_TOP_TRNRDLLPDATA47", - "PCIE_TOP_CFGDSN61", - "PCIE_IMUX29_L_3", - "PCIE_LOGIC_OUTS_B20_R_2", - "PCIE_IMUX47_L_2", - "PCIE_IMUX42_L_2", - "PCIE_LOGIC_OUTS_B20_R_4", - "PCIE_BYP7_R_2", - "PCIE_EE4B1_4", - "PCIE_TOP_MIMRXWDATA8", - "PCIE_LOGIC_OUTS_B2_L_0", - "PCIE_NE2A2_0", - "PCIE_LH1_2", - "PCIE_NW2A2_4", - "PCIE_WW2A1_2", - "PCIE_TOP_MIMRXRADDR9", - "PCIE_IMUX29_R_3", - "PCIE_LOGIC_OUTS_B18_L_3", - "PCIE_LOGIC_OUTS_B13_R_2", - "PCIE_EE2BEG0_1", - "PCIE_EE4B1_2", - "PCIE_NW4END2_1", - "PCIE_IMUX0_L_3", - "PCIE_TOP_CFGTRANSACTIONTYPE", - "PCIE_NE4BEG1_1", - "PCIE_NE4BEG2_0", - "PCIE_LOGIC_OUTS_B3_R_4", - "PCIE_IMUX33_R_3", - "PCIE_NW4END3_2", - "PCIE_IMUX26_L_1", - "PCIE_LOGIC_OUTS_B17_R_2", - "PCIE_WW4C1_2", - "PCIE_NW2A1_0", - "PCIE_FAN5_L_2", - "PCIE_IMUX17_L_1", - "PCIE_TOP_CFGERRAERHEADERLOG3", - "PCIE_TOP_TRNRD81", - "PCIE_BYP5_R_3", - "PCIE_IMUX22_L_2", - "PCIE_TOP_TRNRDLLPDATA41", - "PCIE_TOP_EDTUPDATE", - "PCIE_IMUX43_R_0", - "PCIE_WW4END1_2", - "PCIE_LOGIC_OUTS_B16_L_0", - "PCIE_IMUX7_L_2", - "PCIE_FAN1_L_3", - "PCIE_IMUX38_L_0", - "PCIE_TOP_TRNTD24", - "PCIE_SE4BEG1_2", - "PCIE_LOGIC_OUTS_B10_L_4", - "PCIE_LOGIC_OUTS_B23_R_4", - "PCIE_FAN6_L_1", - "PCIE_TOP_PIPERX0PHYSTATUS", - "PCIE_IMUX23_L_3", - "PCIE_WW2A0_3", - "PCIE_LOGIC_OUTS_B14_R_3", - "PCIE_LOGIC_OUTS_B20_L_2", - "PCIE_WW4END3_3", - "PCIE_IMUX19_R_3", - "PCIE_LOGIC_OUTS_B15_R_4", - "PCIE_NW4END0_3", - "PCIE_IMUX35_R_0", - "PCIE_WW4C2_1", - "PCIE_TOP_CFGTRANSACTIONADDR4", - "PCIE_WR1END3_1", - "PCIE_IMUX38_L_3", - "PCIE_NE2A1_3", - "PCIE_LOGIC_OUTS_B7_R_1", - "PCIE_TOP_TRNRDLLPSRCRDY0", - "PCIE_LOGIC_OUTS_B16_R_3", - "PCIE_WW4B0_3", - "PCIE_FAN2_L_0", - "PCIE_LOGIC_OUTS_B13_R_4", - "PCIE_ER1BEG2_3", - "PCIE_IMUX43_L_2", - "PCIE_TOP_MIMRXRDATA30", - "PCIE_LOGIC_OUTS_B4_R_1", - "PCIE_LH5_1", - "PCIE_CLK1_L_2", - "PCIE_BYP2_L_2", - "PCIE_LOGIC_OUTS_B18_R_4", - "PCIE_TOP_TRNRD72", - "PCIE_BYP7_L_0", - "PCIE_IMUX46_L_2", - "PCIE_LOGIC_OUTS_B3_R_3", - "PCIE_NE4BEG2_4", - "PCIE_LOGIC_OUTS_B7_R_2", - "PCIE_BYP2_R_2", - "PCIE_EE2A3_0", - "PCIE_TOP_CFGDEVID7", - "PCIE_LH7_0", - "PCIE_LOGIC_OUTS_B20_R_1", - "PCIE_TOP_PIPETXMARGIN0", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3", - "PCIE_WW2A0_4", - "PCIE_WW4END3_2", - "PCIE_TOP_DBGVECA16", - "PCIE_TOP_DRPDI4", - "PCIE_BYP4_R_0", - "PCIE_CTRL0_L_1", - "PCIE_TOP_TRNRD79", - "PCIE_TOP_TRNTD29", - "PCIE_WW4A0_4", - "PCIE_IMUX4_L_0", - "PCIE_TOP_DRPDI10", - "PCIE_WW2A0_0", - "PCIE_BLOCK_OUTS_B3_L_3", - "PCIE_IMUX12_L_4", - "PCIE_IMUX15_R_1", - "PCIE_TOP_LL2TFCINIT2SEQ", - "PCIE_IMUX12_L_0", - "PCIE_IMUX42_L_3", - "PCIE_TOP_MIMRXWDATA23", - "PCIE_LOGIC_OUTS_B10_L_0", - "PCIE_TOP_DRPDI13", - "PCIE_SE2A1_4", - "PCIE_LOGIC_OUTS_B16_R_0", - "PCIE_IMUX17_R_1", - "PCIE_NE4C3_0", - "PCIE_IMUX44_L_3", - "PCIE_TOP_PIPERX0DATA3", - "PCIE_WW2END0_4", - "PCIE_LOGIC_OUTS_B23_L_3", - "PCIE_TOP_TRNRD70", - "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN", - "PCIE_TOP_MIMRXRDATA29", - "PCIE_TOP_CFGVCTCVCMAP0", - "PCIE_SW2A3_4", - "PCIE_IMUX11_L_3", - "PCIE_SW4A2_0", - "PCIE_TOP_DBGVECA21", - "PCIE_MONITOR_N_1", - "PCIE_TOP_MIMRXWDATA13", - "PCIE_TOP_DBGVECA11", - "PCIE_BLOCK_OUTS_B2_L_1", - "PCIE_LOGIC_OUTS_B19_L_0", - "PCIE_LOGIC_OUTS_B0_R_4", - "PCIE_TOP_DBGVECA4", - "PCIE_BYP1_R_0", - "PCIE_LH6_2", - "PCIE_TOP_DRPADDR7", - "PCIE_NW2A0_1", - "PCIE_IMUX1_L_3", - "PCIE_IMUX45_R_4", - "PCIE_WW4END1_0", - "PCIE_EE2A1_2", - "PCIE_BYP3_R_0", - "PCIE_LOGIC_OUTS_B21_L_3", - "PCIE_MONITOR_N_0", - "PCIE_IMUX8_L_0", - "PCIE_IMUX40_L_1", - "PCIE_IMUX27_L_0", - "PCIE_LOGIC_OUTS_B3_L_0", - "PCIE_BYP7_L_2", - "PCIE_SW4END0_3", - "PCIE_SW4END2_1", - "PCIE_IMUX6_R_2", - "PCIE_IMUX41_R_1", - "PCIE_LOGIC_OUTS_B21_L_4", - "PCIE_IMUX9_L_4", - "PCIE_NE4C1_1", - "PCIE_FAN1_L_2", - "PCIE_SE4C3_4", - "PCIE_EE4BEG2_4", - "PCIE_LH2_2", - "PCIE_SE4C1_2", - "PCIE_FAN1_L_4", - "PCIE_NE4BEG2_1", - "PCIE_IMUX11_L_1", - "PCIE_IMUX21_R_1", - "PCIE_EE4BEG0_1", - "PCIE_TOP_PIPERX4VALID", - "PCIE_LOGIC_OUTS_B14_L_0", - "PCIE_NW4A0_3", - "PCIE_CLK1_R_2", - "PCIE_IMUX6_R_4", - "PCIE_IMUX36_R_4", - "PCIE_FAN2_R_4", - "PCIE_FAN7_R_3", - "PCIE_IMUX2_R_1", - "PCIE_TOP_MIMRXWDATA24", - "PCIE_BYP4_R_4", - "PCIE_WW4C3_1", - "PCIE_CLK0_L_4", - "PCIE_LOGIC_OUTS_B0_L_4", - "PCIE_IMUX46_R_1", - "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC", - "PCIE_BLOCK_OUTS_B0_R_4", - "PCIE_IMUX14_R_4", - "PCIE_WR1END0_2", - "PCIE_LOGIC_OUTS_B15_L_4", - "PCIE_IMUX34_L_1", - "PCIE_TOP_TRNRDLLPDATA49", - "PCIE_WR1END2_0", - "PCIE_LOGIC_OUTS_B22_R_3", - "PCIE_ER1BEG0_2", - "PCIE_EE4A3_2", - "PCIE_TOP_MIMRXWDATA51", - "PCIE_LH4_2", - "PCIE_NW4END3_3", - "PCIE_TOP_CFGERRTLPCPLHEADER34", - "PCIE_EE4C2_0", - "PCIE_SE2A2_4", - "PCIE_IMUX16_L_1", - "PCIE_NE4BEG3_0", - "PCIE_LOGIC_OUTS_B22_L_4", - "PCIE_CTRL0_R_3", - "PCIE_IMUX22_R_2", - "PCIE_CLK0_L_1", - "PCIE_MONITOR_P_1", - "PCIE_TOP_PLDBGVEC8", - "PCIE_BYP5_L_3", - "PCIE_WW4A3_0", - "PCIE_EL1BEG2_4", - "PCIE_EL1BEG2_3", - "PCIE_IMUX39_L_0", - "PCIE_TOP_MIMRXWDATA21", - "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED", - "PCIE_EE4A2_4", - "PCIE_EE2A1_0", - "PCIE_TOP_PIPERX4DATA3", - "PCIE_EE2BEG2_3", - "PCIE_WW2A0_1", - "PCIE_TOP_MIMRXWADDR2", - "PCIE_BYP7_L_3", - "PCIE_NE4C1_2", - "PCIE_TOP_PIPERX0CHANISALIGNED", - "PCIE_IMUX7_L_4", - "PCIE_IMUX41_R_2", - "PCIE_TOP_CFGERRTLPCPLHEADER39", - "PCIE_LOGIC_OUTS_B14_R_2", - "PCIE_LOGIC_OUTS_B9_R_0", - "PCIE_EE4B2_0", - "PCIE_IMUX13_L_4", - "PCIE_NW4END3_1", - "PCIE_SW2A3_1", - "PCIE_TOP_MIMRXRDATA28", - "PCIE_BYP1_L_1", - "PCIE_IMUX40_L_0", - "PCIE_IMUX33_L_2", - "PCIE_TOP_CFGTRANSACTIONADDR6", - "PCIE_ER1BEG2_1", - "PCIE_SE4C2_4", - "PCIE_TOP_CFGERRTLPCPLHEADER47", - "PCIE_TOP_DBGVECB10", - "PCIE_WR1END1_4", - "PCIE_TOP_CFGTRANSACTION", - "PCIE_IMUX25_R_0", - "PCIE_IMUX8_L_4", - "PCIE_LOGIC_OUTS_B16_L_4", - "PCIE_IMUX15_R_0", - "PCIE_BYP1_R_4", - "PCIE_TOP_CFGERRTLPCPLHEADER43", - "PCIE_WW4C1_1", - "PCIE_LOGIC_OUTS_B17_L_3", - "PCIE_ER1BEG2_4", - "PCIE_IMUX45_R_0", - "PCIE_IMUX23_L_1", - "PCIE_TOP_PIPERX0CHARISK0", - "PCIE_SE2A3_1", - "PCIE_BYP6_R_0", - "PCIE_LOGIC_OUTS_B10_R_0", - "PCIE_IMUX21_L_3", - "PCIE_TOP_TRNTDLLPDATA24", - "PCIE_WW2A3_1", - "PCIE_ER1BEG2_0", - "PCIE_LOGIC_OUTS_B4_L_2", - "PCIE_EL1BEG0_1", - "PCIE_LOGIC_OUTS_B17_L_0", - "PCIE_IMUX33_R_4", - "PCIE_IMUX18_R_0", - "PCIE_NE4BEG2_3", - "PCIE_IMUX9_L_1", - "PCIE_IMUX37_L_1", - "PCIE_LOGIC_OUTS_B12_R_2", - "PCIE_TOP_CFGVCTCVCMAP4", - "PCIE_IMUX41_R_3", - "PCIE_LOGIC_OUTS_B15_R_2", - "PCIE_SW4A2_1", - "PCIE_TOP_PIPERX4CHANISALIGNED", - "PCIE_TOP_TRNRDLLPDATA62", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2", - "PCIE_EE4B0_2", - "PCIE_NW4END3_4", - "PCIE_LH1_1", - "PCIE_BLOCK_OUTS_B1_R_4", - "PCIE_TOP_CFGDSN62", - "PCIE_TOP_MIMRXRDATA42", - "PCIE_TOP_EDTCONFIGURATION", - "PCIE_EE2A0_3", - "PCIE_TOP_DRPDO6", - "PCIE_NE4BEG0_2", - "PCIE_IMUX23_L_4", - "PCIE_EL1BEG0_4", - "PCIE_BLOCK_OUTS_B2_L_3", - "PCIE_IMUX40_L_2", - "PCIE_IMUX13_R_3", - "PCIE_IMUX4_L_2", - "PCIE_EE4C1_1", - "PCIE_EE4BEG1_3", - "PCIE_EE4BEG1_4", - "PCIE_WW4A2_0", - "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1", - "PCIE_FAN6_L_3", - "PCIE_WW2END2_1", - "PCIE_EE4C0_1", - "PCIE_TOP_TRNRDLLPDATA48", - "PCIE_LH5_4", - "PCIE_ER1BEG1_4", - "PCIE_IMUX35_L_1", - "PCIE_TOP_TRNRD59", - "PCIE_IMUX42_L_4", - "PCIE_FAN3_R_3", - "PCIE_LOGIC_OUTS_B6_R_0", - "PCIE_LOGIC_OUTS_B0_L_1", - "PCIE_IMUX24_L_3", - "PCIE_LOGIC_OUTS_B8_R_0", - "PCIE_SE4BEG3_3", - "PCIE_SW4END2_2", - "PCIE_TOP_TRNRD69", - "PCIE_TOP_SCANMODEN", - "PCIE_IMUX8_L_3", - "PCIE_BYP4_L_3", - "PCIE_WL1END3_4", - "PCIE_IMUX47_L_4", - "PCIE_TOP_DBGMODE0", - "PCIE_SE4BEG0_0", - "PCIE_TOP_MIMRXWDATA3", - "PCIE_WW2END1_1", - "PCIE_LOGIC_OUTS_B23_L_4", - "PCIE_IMUX47_R_4", - "PCIE_LOGIC_OUTS_B3_L_4", - "PCIE_LOGIC_OUTS_B15_L_2", - "PCIE_MONITOR_N_3", - "PCIE_IMUX36_R_2", - "PCIE_IMUX36_L_1", - "PCIE_LOGIC_OUTS_B22_R_2", - "PCIE_EE4C2_1", - "PCIE_SW2A1_2", - "PCIE_TOP_MIMRXRDATA24", - "PCIE_LOGIC_OUTS_B5_L_3", - "PCIE_LOGIC_OUTS_B12_R_0", - "PCIE_TOP_EDTBYPASS", - "PCIE_LOGIC_OUTS_B3_L_1", - "PCIE_IMUX30_L_4", - "PCIE_LOGIC_OUTS_B23_L_2", - "PCIE_NE4C1_0", - "PCIE_LOGIC_OUTS_B1_L_3", - "PCIE_IMUX46_R_3", - "PCIE_TOP_TRNRDLLPDATA35", - "PCIE_TOP_DRPDO15", - "PCIE_LH1_0", - "PCIE_MONITOR_P_3", - "PCIE_LOGIC_OUTS_B17_R_0", - "PCIE_LOGIC_OUTS_B8_R_1", - "PCIE_WW2END3_2", - "PCIE_TOP_TRNRDLLPDATA32", - "PCIE_TOP_CFGDSN59", - "PCIE_WR1END2_1", - "PCIE_NE4BEG3_4", - "PCIE_IMUX23_R_2", - "PCIE_TOP_CFGERRTLPCPLHEADER29", - "PCIE_IMUX20_R_1", - "PCIE_IMUX35_R_1", - "PCIE_LH1_3", - "PCIE_LOGIC_OUTS_B22_L_3", - "PCIE_IMUX47_L_0", - "PCIE_CLK0_R_3", - "PCIE_BYP0_L_2", - "PCIE_BYP1_R_1", - "PCIE_NW4END1_0", - "PCIE_IMUX27_L_3", - "PCIE_IMUX37_R_4", - "PCIE_WW4END0_2", - "PCIE_EE4A3_1", - "PCIE_EE4BEG3_3", - "PCIE_FAN1_R_2", - "PCIE_IMUX39_L_3", - "PCIE_LOGIC_OUTS_B16_L_2", - "PCIE_CTRL1_L_4", - "PCIE_TOP_PIPERX0DATA4", - "PCIE_IMUX22_L_3", - "PCIE_EE2A2_4", - "PCIE_TOP_CFGMGMTDO30", - "PCIE_CLK0_L_2", - "PCIE_EE4BEG1_0", - "PCIE_IMUX12_L_3", - "PCIE_EE4BEG2_2", - "PCIE_TOP_CFGDEVID14", - "PCIE_TOP_CFGERRTLPCPLHEADER42", - "PCIE_EE4A1_4", - "PCIE_FAN4_L_3", - "PCIE_EE2A3_1", - "PCIE_TOP_TRNRDLLPDATA40", - "PCIE_EE2A3_4", - "PCIE_WW2END3_4", - "PCIE_BYP1_L_3", - "PCIE_CTRL0_R_0", - "PCIE_NE4C3_1", - "PCIE_NW4A1_3", - "PCIE_SW2A0_3", - "PCIE_TOP_MIMRXWDATA15", - "PCIE_NW2A2_3", - "PCIE_IMUX42_L_0", - "PCIE_SW4A0_2", - "PCIE_LOGIC_OUTS_B5_L_0", - "PCIE_NE2A2_3", - "PCIE_WW4END3_0", - "PCIE_LOGIC_OUTS_B9_R_1", - "PCIE_TOP_PIPERX4DATA7", - "PCIE_CLK1_R_1", - "PCIE_TOP_MIMRXRADDR4", - "PCIE_BLOCK_OUTS_B0_L_2", - "PCIE_SW4A2_4", - "PCIE_WW4B1_3", - "PCIE_LOGIC_OUTS_B11_R_3", - "PCIE_FAN2_L_3", - "PCIE_NW4END2_3", - "PCIE_BLOCK_OUTS_B1_R_1", - "PCIE_WL1END0_1", - "PCIE_NW4A2_1", - "PCIE_IMUX39_R_2", - "PCIE_LOGIC_OUTS_B11_L_1", - "PCIE_TOP_CFGDEVID13", - "PCIE_IMUX14_R_0", - "PCIE_TOP_CFGDEVID10", - "PCIE_TOP_MIMRXRDATA26", - "PCIE_TOP_CFGMGMTDO20", - "PCIE_TOP_MIMRXRDATA48", - "PCIE_BLOCK_OUTS_B0_L_1", - "PCIE_IMUX16_R_4", - "PCIE_TOP_LL2SENDASREQL1", - "PCIE_SE4BEG3_2", - "PCIE_IMUX40_L_3", - "PCIE_IMUX21_R_4", - "PCIE_SE2A2_0", - "PCIE_TOP_MIMRXWADDR12", - "PCIE_LOGIC_OUTS_B3_R_0", - "PCIE_CTRL1_R_2", - "PCIE_EE2BEG1_3", - "PCIE_FAN1_R_4", - "PCIE_FAN4_L_2", - "PCIE_TOP_MIMRXWDATA12", - "PCIE_TOP_MIMRXRDATA33", - "PCIE_IMUX8_R_0", - "PCIE_SW4A2_3", - "PCIE_IMUX11_L_2", - "PCIE_LH10_3", - "PCIE_TOP_CFGERRTLPCPLHEADER40", - "PCIE_SW2A0_0", - "PCIE_IMUX44_R_1", - "PCIE_TOP_TRNTD39", - "PCIE_TOP_XILUNCONNOUT28", - "PCIE_LOGIC_OUTS_B12_R_3", - "PCIE_TOP_MIMRXRDATA38", - "PCIE_WR1END0_3", - "PCIE_LOGIC_OUTS_B8_R_2", - "PCIE_IMUX25_L_4", - "PCIE_FAN3_L_3", - "PCIE_WL1END0_2", - "PCIE_TOP_CFGCOMMANDIOENABLE", - "PCIE_LOGIC_OUTS_B21_R_3", - "PCIE_TOP_TRNRD85", - "PCIE_WW2A0_2", - "PCIE_TOP_CFGCOMMANDMEMENABLE", - "PCIE_TOP_TRNTD20", - "PCIE_WW4B0_0", - "PCIE_CTRL1_L_2", - "PCIE_NW4A1_4", - "PCIE_IMUX26_R_0", - "PCIE_IMUX7_R_3", - "PCIE_FAN6_R_3", - "PCIE_SE2A0_1", - "PCIE_BYP7_R_1", - "PCIE_CTRL0_R_1", - "PCIE_FAN5_R_2", - "PCIE_BYP3_R_4", - "PCIE_WW4A2_3", - "PCIE_LOGIC_OUTS_B19_L_2", - "PCIE_TOP_TRNRDLLPDATA45", - "PCIE_TOP_MIMRXRDATA40", - "PCIE_NW4A3_1", - "PCIE_BYP3_L_0", - "PCIE_SW2A0_4", - "PCIE_TOP_TRNTD13", - "PCIE_TOP_PIPERX4CHARISK0", - "PCIE_IMUX27_L_2", - "PCIE_EE4B2_1", - "PCIE_LOGIC_OUTS_B5_L_1", - "PCIE_BLOCK_OUTS_B1_R_3", - "PCIE_TOP_MIMRXWADDR5", - "PCIE_IMUX24_L_1", - "PCIE_IMUX39_R_3", - "PCIE_LOGIC_OUTS_B3_R_2", - "PCIE_TOP_CFGDSN60", - "PCIE_TOP_TRNRD61", - "PCIE_BYP5_L_4", - "PCIE_SW4A3_1", - "PCIE_TOP_CFGERRAERHEADERLOG10", - "PCIE_IMUX45_R_3", - "PCIE_IMUX46_L_0", - "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN", - "PCIE_LOGIC_OUTS_B18_R_2", - "PCIE_IMUX19_L_4", - "PCIE_EE4C3_3", - "PCIE_TOP_TRNRDLLPDATA42", - "PCIE_BLOCK_OUTS_B1_R_0", - "PCIE_IMUX18_L_3", - "PCIE_TOP_CFGVCTCVCMAP1", - "PCIE_TOP_CFGERRTLPCPLHEADER31", - "PCIE_BYP2_R_4", - "PCIE_TOP_CFGMGMTDO29", - "PCIE_EE4BEG3_2", - "PCIE_TOP_DRPDI0", - "PCIE_CTRL1_L_1", - "PCIE_EE4C3_2", - "PCIE_FAN5_R_0", - "PCIE_NW2A0_2", - "PCIE_LOGIC_OUTS_B1_R_0", - "PCIE_TOP_TRNRDLLPDATA33", - "PCIE_TOP_TRNRDLLPDATA50", - "PCIE_SE4C2_2", - "PCIE_BYP5_L_0", - "PCIE_EE4A2_1", - "PCIE_LOGIC_OUTS_B8_R_3", - "PCIE_BLOCK_OUTS_B0_L_0", - "PCIE_FAN3_L_2", - "PCIE_IMUX46_L_4", - "PCIE_EE4BEG2_3", - "PCIE_IMUX6_L_0", - "PCIE_WW4B2_4", - "PCIE_IMUX31_L_3", - "PCIE_SE4BEG2_0", - "PCIE_IMUX17_L_4", - "PCIE_TOP_CFGMGMTDO28", - "PCIE_IMUX42_L_1", - "PCIE_BLOCK_OUTS_B2_R_0", - "PCIE_LOGIC_OUTS_B6_L_3", - "PCIE_TOP_TRNTD19", - "PCIE_WW4A0_3", - "PCIE_TOP_TRNRD73", - "PCIE_EE4A0_3", - "PCIE_FAN7_L_3", - "PCIE_EL1BEG0_3", - "PCIE_LH10_2", - "PCIE_LH8_0", - "PCIE_EE2A3_3", - "PCIE_BLOCK_OUTS_B2_L_2", - "PCIE_IMUX25_R_3", - "PCIE_NE4C3_4", - "PCIE_IMUX20_R_4", - "PCIE_IMUX34_R_3", - "PCIE_IMUX42_R_2", - "PCIE_IMUX18_L_1", - "PCIE_LOGIC_OUTS_B19_R_1", - "PCIE_LOGIC_OUTS_B22_L_1", - "PCIE_IMUX9_R_0", - "PCIE_IMUX0_L_0", - "PCIE_SE4C3_1", - "PCIE_EE4BEG3_0", - "PCIE_IMUX28_L_2", - "PCIE_SW4A0_4", - "PCIE_TOP_MIMRXRADDR1", - "PCIE_IMUX29_R_0", - "PCIE_LOGIC_OUTS_B15_R_1", - "PCIE_TOP_CFGDSN63", - "PCIE_SW4A3_2", - "PCIE_FAN3_R_1", - "PCIE_LH12_2", - "PCIE_TOP_TRNRD93", - "PCIE_TOP_CFGMGMTDO17", - "PCIE_TOP_TRNRDLLPDATA57", - "PCIE_SW4END1_2", - "PCIE_LOGIC_OUTS_B11_L_2", - "PCIE_IMUX38_L_1", - "PCIE_LH6_4", - "PCIE_TOP_DBGVECA19", - "PCIE_TOP_MIMRXRADDR0", - "PCIE_EE4B1_0", - "PCIE_IMUX26_L_3", - "PCIE_BYP4_L_0", - "PCIE_IMUX7_L_0", - "PCIE_EE4C3_0", - "PCIE_IMUX17_L_0", - "PCIE_SE4BEG2_3", - "PCIE_TOP_DRPRDY", - "PCIE_BYP0_L_1", - "PCIE_EE4B2_3", - "PCIE_SE2A0_0", - "PCIE_TOP_TRNTD12", - "PCIE_NW4END0_4", - "PCIE_TOP_CFGPCIELINKSTATE2", - "PCIE_NW2A3_2", - "PCIE_IMUX27_R_3", - "PCIE_LOGIC_OUTS_B7_L_2", - "PCIE_LH8_2", - "PCIE_TOP_DRPDO4", - "PCIE_WW4A2_4", - "PCIE_IMUX24_L_4", - "PCIE_NW4A2_0", - "PCIE_IMUX2_L_3", - "PCIE_TOP_CFGERRAERHEADERLOG9", - "PCIE_IMUX1_R_4", - "PCIE_LH2_4", - "PCIE_TOP_DBGVECA1", - "PCIE_IMUX44_R_3", - "PCIE_EE2BEG1_2", - "PCIE_WW4B1_1", - "PCIE_TOP_TRNTD23", - "PCIE_BYP6_R_1", - "PCIE_WW4B0_1", - "PCIE_SE4BEG3_1", - "PCIE_NW2A3_3", - "PCIE_ER1BEG1_3", - "PCIE_IMUX9_R_2", - "PCIE_TOP_CFGDEVID11", - "PCIE_LOGIC_OUTS_B4_R_2", - "PCIE_FAN0_R_1", - "PCIE_IMUX0_R_4", - "PCIE_SE4BEG0_1", - "PCIE_LOGIC_OUTS_B8_L_1", - "PCIE_IMUX41_R_0", - "PCIE_IMUX43_L_4", - "PCIE_LOGIC_OUTS_B11_R_4", - "PCIE_ER1BEG0_3", - "PCIE_EE4B3_2", - "PCIE_SE2A1_0", - "PCIE_NE4C0_2", - "PCIE_TOP_DBGVECA14", - "PCIE_IMUX45_R_1", - "PCIE_BLOCK_OUTS_B2_R_4", - "PCIE_IMUX33_R_0", - "PCIE_NE4C0_3", - "PCIE_EE4A3_4", - "PCIE_BYP2_R_3", - "PCIE_IMUX28_L_3", - "PCIE_LH8_3", - "PCIE_SW4A0_1", - "PCIE_IMUX5_R_4", - "PCIE_TOP_TRNTD30", - "PCIE_LOGIC_OUTS_B16_R_1", - "PCIE_EE2BEG1_4", - "PCIE_BLOCK_OUTS_B1_L_3", - "PCIE_TOP_CFGPCIELINKSTATE1", - "PCIE_NE4BEG3_2", - "PCIE_LOGIC_OUTS_B2_R_3", - "PCIE_FAN7_R_4", - "PCIE_LOGIC_OUTS_B8_L_0", - "PCIE_SE4BEG3_4", - "PCIE_CLK0_R_0", - "PCIE_IMUX28_R_4", - "PCIE_IMUX44_L_1", - "PCIE_IMUX40_R_4", - "PCIE_TOP_MIMRXRDATA20", - "PCIE_CTRL1_L_0", - "PCIE_WL1END3_1", - "PCIE_TOP_DRPDO1", - "PCIE_BYP3_L_1", - "PCIE_IMUX24_R_1", - "PCIE_LOGIC_OUTS_B1_R_2", - "PCIE_IMUX32_L_0", - "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE", - "PCIE_BLOCK_OUTS_B3_L_0", - "PCIE_SW4A3_0", - "PCIE_TOP_DRPADDR8", - "PCIE_IMUX45_L_2", - "PCIE_BYP0_R_0", - "PCIE_LOGIC_OUTS_B2_R_0", - "PCIE_IMUX11_R_2", - "PCIE_NE4BEG3_3", - "PCIE_TOP_TRNRD63", - "PCIE_IMUX22_R_3", - "PCIE_LOGIC_OUTS_B8_L_4", - "PCIE_LH2_3", - "PCIE_IMUX37_R_1", - "PCIE_BLOCK_OUTS_B3_R_2", - "PCIE_NW4A1_0", - "PCIE_LOGIC_OUTS_B19_R_0", - "PCIE_SE4C2_0", - "PCIE_FAN3_R_0", - "PCIE_LOGIC_OUTS_B13_L_3", - "PCIE_LH6_1", - "PCIE_IMUX34_L_4", - "PCIE_WR1END3_2", - "PCIE_IMUX8_R_4", - "PCIE_IMUX11_R_4", - "PCIE_BYP4_R_3", - "PCIE_MONITOR_N_4", - "PCIE_IMUX3_R_0", - "PCIE_TOP_MIMRXWDATA28", - "PCIE_TOP_TRNTDLLPDATA31", - "PCIE_IMUX47_L_1", - "PCIE_IMUX41_L_3", - "PCIE_EE2A2_2", - "PCIE_LH4_1", - "PCIE_LOGIC_OUTS_B13_L_4", - "PCIE_EE2A0_4", - "PCIE_NW2A3_1", - "PCIE_IMUX15_R_4", - "PCIE_IMUX30_L_3", - "PCIE_EL1BEG2_2", - "PCIE_WW4END0_3", - "PCIE_EE4A1_2", - "PCIE_IMUX4_R_2", - "PCIE_BYP5_R_1", - "PCIE_TOP_CFGERRTLPCPLHEADER45", - "PCIE_TOP_MIMRXWDATA2", - "PCIE_LOGIC_OUTS_B1_R_1", - "PCIE_BYP5_L_1", - "PCIE_FAN7_L_2", - "PCIE_FAN3_L_4", - "PCIE_EE4BEG1_1", - "PCIE_TOP_CFGTRANSACTIONADDR0", - "PCIE_WL1END1_3", - "PCIE_ER1BEG3_3", - "PCIE_IMUX27_L_4", - "PCIE_WW4A0_2", - "PCIE_IMUX12_R_3", - "PCIE_IMUX16_R_1", - "PCIE_WW4C1_0", - "PCIE_WL1END2_1", - "PCIE_BLOCK_OUTS_B1_L_1", - "PCIE_TOP_DRPDI14", - "PCIE_BYP1_L_4", - "PCIE_IMUX5_R_1", - "PCIE_LOGIC_OUTS_B23_R_0", - "PCIE_IMUX22_R_1", - "PCIE_NW4A0_0", - "PCIE_TOP_MIMRXRDATA39", - "PCIE_BLOCK_OUTS_B2_R_3", - "PCIE_LH11_4", - "PCIE_LOGIC_OUTS_B5_L_4", - "PCIE_TOP_PIPERX4DATA2", - "PCIE_LH12_0", - "PCIE_WW4B2_1", - "PCIE_SE2A1_2", - "PCIE_LOGIC_OUTS_B8_L_2", - "PCIE_CTRL1_R_3", - "PCIE_SW4END2_4", - "PCIE_FAN7_L_1", - "PCIE_IMUX17_R_4", - "PCIE_NE4C0_1", - "PCIE_FAN4_R_0", - "PCIE_TOP_TRNTD32", - "PCIE_IMUX16_R_2", - "PCIE_FAN7_R_2", - "PCIE_FAN5_L_3", - "PCIE_TOP_PL2RECOVERY", - "PCIE_IMUX5_L_3", - "PCIE_IMUX8_R_1", - "PCIE_IMUX13_L_1", - "PCIE_IMUX5_L_2", - "PCIE_IMUX20_L_0", - "PCIE_TOP_TRNRD80", - "PCIE_TOP_CFGERRTLPCPLHEADER37", - "PCIE_BYP3_R_2", - "PCIE_IMUX17_L_3", - "PCIE_LOGIC_OUTS_B6_L_2", - "PCIE_LH3_1", - "PCIE_NE4BEG1_3", - "PCIE_IMUX29_R_2", - "PCIE_TOP_CFGDEVID15", - "PCIE_LOGIC_OUTS_B11_R_2", - "PCIE_SW4END1_4", - "PCIE_LOGIC_OUTS_B11_R_0", - "PCIE_EE4A1_1", - "PCIE_BYP5_L_2", - "PCIE_LOGIC_OUTS_B10_L_1", - "PCIE_BYP6_L_0", - "PCIE_TOP_TRNRDLLPDATA60", - "PCIE_TOP_TRNTD11", - "PCIE_IMUX32_R_3", - "PCIE_WW2END0_2", - "PCIE_FAN5_L_1", - "PCIE_IMUX1_L_0", - "PCIE_IMUX30_R_1", - "PCIE_EE4BEG2_1", - "PCIE_FAN4_R_1", - "PCIE_SW2A2_1", - "PCIE_EE4BEG1_2", - "PCIE_TOP_TRNRD64", - "PCIE_LOGIC_OUTS_B22_R_0", - "PCIE_BYP0_R_2", - "PCIE_LOGIC_OUTS_B21_R_4", - "PCIE_LOGIC_OUTS_B9_L_4", - "PCIE_TOP_TRNRDLLPDATA61", - "PCIE_TOP_TL2PPMSUSPENDREQ", - "PCIE_MONITOR_N_2", - "PCIE_IMUX18_L_2", - "PCIE_IMUX25_R_4", - "PCIE_NE4BEG2_2", - "PCIE_NW2A0_3", - "PCIE_BLOCK_OUTS_B3_L_1", - "PCIE_BYP2_L_0", - "PCIE_IMUX20_R_3", - "PCIE_IMUX26_R_1", - "PCIE_IMUX35_R_4", - "PCIE_WW4B1_0", - "PCIE_LOGIC_OUTS_B19_R_3", - "PCIE_IMUX38_R_0", - "PCIE_IMUX27_R_4", - "PCIE_TOP_TRNRD86", - "PCIE_BLOCK_OUTS_B3_L_2", - "PCIE_LOGIC_OUTS_B21_L_0", - "PCIE_IMUX6_L_3", - "PCIE_NE4C3_3", - "PCIE_NW4END1_2", - "PCIE_IMUX44_R_4", - "PCIE_IMUX41_L_0", - "PCIE_LH8_1", - "PCIE_FAN3_L_1", - "PCIE_IMUX36_R_1", - "PCIE_EE2BEG2_0", - "PCIE_TOP_CFGERRAERHEADERLOG0", - "PCIE_IMUX26_L_2", - "PCIE_TOP_TRNRD62", - "PCIE_NW2A2_1", - "PCIE_SE4BEG1_3", - "PCIE_IMUX30_L_2", - "PCIE_FAN6_R_0", - "PCIE_TOP_CFGERRAERHEADERLOG4", - "PCIE_IMUX15_L_0", - "PCIE_IMUX47_R_2", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0", - "PCIE_NE4C2_2", - "PCIE_TOP_MIMRXWDATA4", - "PCIE_IMUX7_R_1", - "PCIE_IMUX10_L_2", - "PCIE_BYP6_L_3", - "PCIE_LOGIC_OUTS_B11_L_4", - "PCIE_LOGIC_OUTS_B12_R_4", - "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK", - "PCIE_NW4END2_0", - "PCIE_TOP_MIMRXWDATA9", - "PCIE_IMUX24_L_2", - "PCIE_TOP_TRNRD90", - "PCIE_IMUX28_R_2", - "PCIE_SW4A0_3", - "PCIE_IMUX45_L_0", - "PCIE_TOP_TRNTD10", - "PCIE_IMUX19_L_1", - "PCIE_IMUX47_R_3", - "PCIE_TOP_DBGVECA2", - "PCIE_TOP_TRNRDLLPDATA51", - "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN", - "PCIE_LOGIC_OUTS_B19_R_2", - "PCIE_NW4END0_1", - "PCIE_NE4C2_3", - "PCIE_IMUX7_R_4", - "PCIE_IMUX37_L_2", - "PCIE_IMUX42_R_3", - "PCIE_SE4BEG1_0", - "PCIE_TOP_TRNRDLLPDATA34", - "PCIE_EE4C1_2", - "PCIE_SE4BEG0_2", - "PCIE_EE4A2_3", - "PCIE_IMUX16_L_0", - "PCIE_LOGIC_OUTS_B11_L_3", - "PCIE_LOGIC_OUTS_B12_L_3", - "PCIE_TOP_DRPDO5", - "PCIE_WL1END0_0", - "PCIE_CLK0_R_2", - "PCIE_IMUX20_L_4", - "PCIE_SE2A3_4", - "PCIE_TOP_TRNTD36", - "PCIE_TOP_MIMRXWDATA49", - "PCIE_LH10_4", - "PCIE_EE4BEG3_4", - "PCIE_IMUX37_R_2", - "PCIE_TOP_TRNRDLLPDATA52", - "PCIE_WW4C1_4", - "PCIE_WW4A3_3", - "PCIE_EL1BEG1_4", - "PCIE_NE2A1_4", - "PCIE_IMUX32_R_2", - "PCIE_TOP_TRNRDLLPDATA63", - "PCIE_IMUX8_R_3", - "PCIE_LOGIC_OUTS_B23_L_1", - "PCIE_TOP_PIPERX0DATA1", - "PCIE_BYP0_L_0", - "PCIE_IMUX20_R_0", - "PCIE_TOP_MIMRXRDATA46", - "PCIE_NE2A1_1", - "PCIE_TOP_CFGERRTLPCPLHEADER44", - "PCIE_IMUX26_L_4", - "PCIE_WW4C3_4", - "PCIE_NW2A2_0", - "PCIE_SW4A1_0", - "PCIE_BYP6_L_4", - "PCIE_BYP6_R_4", - "PCIE_IMUX18_R_4", - "PCIE_IMUX33_L_1", - "PCIE_ER1BEG3_1", - "PCIE_IMUX31_L_1", - "PCIE_LOGIC_OUTS_B20_L_1", - "PCIE_LOGIC_OUTS_B15_R_0", - "PCIE_NW4END3_0", - "PCIE_EL1BEG3_1", - "PCIE_LOGIC_OUTS_B13_R_1", - "PCIE_TOP_MIMRXWDATA6", - "PCIE_FAN6_R_4", - "PCIE_WW2END2_0", - "PCIE_SE4BEG2_1", - "PCIE_TOP_CFGMGMTDO16", - "PCIE_TOP_TRNTD38", - "PCIE_BLOCK_OUTS_B2_R_2", - "PCIE_LH10_1", - "PCIE_IMUX41_L_1", - "PCIE_IMUX29_L_1", - "PCIE_LOGIC_OUTS_B6_L_4", - "PCIE_EE4B3_0", - "PCIE_IMUX27_R_0", - "PCIE_TOP_PIPERX4DATA1", - "PCIE_NE4C3_2", - "PCIE_CTRL0_R_4", - "PCIE_IMUX0_L_2", - "PCIE_LH2_1", - "PCIE_TOP_MIMRXWDATA34", - "PCIE_IMUX11_R_3", - "PCIE_LOGIC_OUTS_B12_L_1", - "PCIE_LOGIC_OUTS_B11_R_1", - "PCIE_WW4B2_2", - "PCIE_IMUX8_L_1", - "PCIE_TOP_DBGVECA5", - "PCIE_LH6_3", - "PCIE_LH11_3", - "PCIE_LH10_0", - "PCIE_LOGIC_OUTS_B12_L_2", - "PCIE_IMUX47_R_1", - "PCIE_TOP_CFGMGMTDO24", - "PCIE_IMUX12_R_4", - "PCIE_BYP3_R_3", - "PCIE_TOP_MIMRXRDATA23", - "PCIE_IMUX3_L_3", - "PCIE_IMUX45_L_3", - "PCIE_FAN0_R_4", - "PCIE_LH4_4", - "PCIE_TOP_TRNRDLLPDATA44", - "PCIE_IMUX31_L_0", - "PCIE_SE4C3_3", - "PCIE_IMUX28_L_1", - "PCIE_EL1BEG0_0", - "PCIE_FAN2_R_0", - "PCIE_FAN5_R_3", - "PCIE_NE4C0_0", - "PCIE_IMUX38_R_2", - "PCIE_SW4END0_1", - "PCIE_CLK0_R_1", - "PCIE_TOP_TRNRDLLPDATA53", - "PCIE_TOP_DRPDI8", - "PCIE_IMUX44_R_2", - "PCIE_LOGIC_OUTS_B15_L_0", - "PCIE_ER1BEG0_0", - "PCIE_WL1END3_2", - "PCIE_EE4BEG0_2", - "PCIE_BYP2_L_3", - "PCIE_IMUX12_L_1", - "PCIE_SE2A0_4", - "PCIE_EE4A2_2", - "PCIE_BYP4_L_2", - "PCIE_BLOCK_OUTS_B1_L_4", - "PCIE_TOP_LL2TLPRCV", - "PCIE_TOP_TRNRDLLPDATA58", - "PCIE_IMUX4_R_3", - "PCIE_IMUX12_R_2", - "PCIE_TOP_TRNTD8", - "PCIE_EE4BEG0_3", - "PCIE_TOP_TRNTD17", - "PCIE_TOP_MIMRXWDATA27", - "PCIE_LOGIC_OUTS_B10_R_2", - "PCIE_NE4BEG0_1", - "PCIE_LOGIC_OUTS_B20_L_4", - "PCIE_TOP_TRNTDLLPDATA25", - "PCIE_WW4C0_4", - "PCIE_EL1BEG2_1", - "PCIE_NW2A1_1", - "PCIE_TOP_DBGVECA17", - "PCIE_IMUX33_L_4", - "PCIE_IMUX11_L_4", - "PCIE_LOGIC_OUTS_B9_R_2", - "PCIE_WW4END1_3", - "PCIE_LOGIC_OUTS_B14_L_1", - "PCIE_WW4C3_0", - "PCIE_BLOCK_OUTS_B2_R_1", - "PCIE_LH2_0", - "PCIE_IMUX2_L_4", - "PCIE_WW2END1_3", - "PCIE_NW2A1_3", - "PCIE_IMUX14_R_3", - "PCIE_TOP_PIPERX4DATA4", - "PCIE_IMUX6_R_1", - "PCIE_IMUX13_L_3", - "PCIE_IMUX43_L_0", - "PCIE_TOP_PL2SUSPENDOK", - "PCIE_LOGIC_OUTS_B10_R_3", - "PCIE_IMUX37_L_0", - "PCIE_EE2A2_3", - "PCIE_IMUX19_R_4", - "PCIE_LOGIC_OUTS_B5_R_0", - "PCIE_TOP_CFGPMCSRPOWERSTATE0", - "PCIE_LH9_4", - "PCIE_CTRL0_L_4", - "PCIE_EE4A0_1", - "PCIE_TOP_MIMRXRDATA55", - "PCIE_SE2A2_3", - "PCIE_TOP_MIMRXRADDR11", - "PCIE_IMUX12_R_1", - "PCIE_WR1END2_2", - "PCIE_SE2A3_0", - "PCIE_TOP_CFGERRAERHEADERLOG5", - "PCIE_IMUX36_R_0", - "PCIE_LOGIC_OUTS_B19_L_3", - "PCIE_SE4C1_0", - "PCIE_ER1BEG0_1", - "PCIE_WR1END1_3", - "PCIE_EE4B2_2", - "PCIE_LOGIC_OUTS_B9_L_3", - "PCIE_WW4END3_4", - "PCIE_EE2BEG1_1", - "PCIE_LOGIC_OUTS_B10_L_2", - "PCIE_WW4C2_2", - "PCIE_NW4END1_3", - "PCIE_WW2END3_0", - "PCIE_TOP_DRPDI15", - "PCIE_TOP_CFGPMCSRPMESTATUS", - "PCIE_IMUX10_R_0", - "PCIE_NW4A2_4", - "PCIE_IMUX27_L_1", - "PCIE_EE4B3_1", - "PCIE_BYP0_R_4", - "PCIE_TOP_TRNRD92", - "PCIE_TOP_CFGERRTLPCPLHEADER28", - "PCIE_IMUX30_L_1", - "PCIE_WW4B1_2", - "PCIE_TOP_PIPERX0DATA0", - "PCIE_LOGIC_OUTS_B13_L_1", - "PCIE_BYP2_L_4", - "PCIE_LH7_1", - "PCIE_TOP_DRPDO14", - "PCIE_TOP_PL2DIRECTEDLSTATE2", - "PCIE_ER1BEG3_4", - "PCIE_SE4BEG3_0", - "PCIE_EL1BEG2_0", - "PCIE_TOP_TRNTD40", - "PCIE_LOGIC_OUTS_B14_R_0", - "PCIE_WW2A3_4", - "PCIE_LOGIC_OUTS_B2_R_4", - "PCIE_BYP1_L_0", - "PCIE_IMUX39_R_4", - "PCIE_TOP_TRNTD26", - "PCIE_IMUX43_R_3", - "PCIE_IMUX36_R_3", - "PCIE_EE4C0_4", - "PCIE_TOP_CFGTRANSACTIONADDR2", - "PCIE_NE4BEG1_2", - "PCIE_LH8_4", - "PCIE_EE4B0_0", - "PCIE_IMUX22_R_0", - "PCIE_TOP_MIMRXWDATA35", - "PCIE_WW2A1_0", - "PCIE_TOP_MIMRXWADDR1", - "PCIE_LOGIC_OUTS_B22_L_2", - "PCIE_IMUX31_L_2", - "PCIE_IMUX35_L_4", - "PCIE_FAN4_R_2", - "PCIE_IMUX23_R_4", - "PCIE_IMUX0_R_0", - "PCIE_IMUX45_R_2", - "PCIE_IMUX46_L_1", - "PCIE_IMUX18_R_2", - "PCIE_WL1END3_0", - "PCIE_TOP_TRNTD18", - "PCIE_LOGIC_OUTS_B7_L_1", - "PCIE_SE4BEG0_4", - "PCIE_IMUX18_L_4", - "PCIE_TOP_TRNTDLLPDATA27", - "PCIE_LOGIC_OUTS_B2_L_4", - "PCIE_LOGIC_OUTS_B1_L_1", - "PCIE_TOP_TRNRDLLPDATA46", - "PCIE_IMUX16_L_2", - "PCIE_IMUX10_R_1", - "PCIE_TOP_CFGPMRCVREQACKN", - "PCIE_SE2A2_1", - "PCIE_LH9_2", - "PCIE_IMUX3_R_3", - "PCIE_LOGIC_OUTS_B16_R_2", - "PCIE_ER1BEG0_4", - "PCIE_WW4A0_0", - "PCIE_WR1END3_4", - "PCIE_TOP_TRNTD16", - "PCIE_IMUX31_R_3", - "PCIE_TOP_MIMRXRDATA52", - "PCIE_FAN2_L_1", - "PCIE_BYP7_L_1", - "PCIE_IMUX8_R_2", - "PCIE_TOP_CFGVENDID0", - "PCIE_IMUX6_L_4", - "PCIE_FAN0_L_3", - "PCIE_BLOCK_OUTS_B0_R_1", - "PCIE_IMUX34_L_3", - "PCIE_EE4BEG0_0", - "PCIE_IMUX2_R_4", - "PCIE_LOGIC_OUTS_B9_L_1", - "PCIE_TOP_LL2SENDPMACK", - "PCIE_TOP_TRNRD75", - "PCIE_EE4A0_4", - "PCIE_WW4END0_4", - "PCIE_IMUX28_L_4", - "PCIE_LOGIC_OUTS_B1_R_3", - "PCIE_NW4END0_2", - "PCIE_WW4B2_3", - "PCIE_EE4C1_0", - "PCIE_IMUX38_R_4", - "PCIE_LOGIC_OUTS_B22_L_0", - "PCIE_LOGIC_OUTS_B7_L_0", - "PCIE_IMUX25_R_1", - "PCIE_TOP_CFGERRNORECOVERYN", - "PCIE_TOP_PIPERX4DATA0", - "PCIE_LOGIC_OUTS_B10_R_1", - "PCIE_IMUX35_R_2", - "PCIE_TOP_TRNRDLLPDATA56", - "PCIE_LOGIC_OUTS_B2_L_2", - "PCIE_IMUX9_L_0", - "PCIE_NW4A0_4", - "PCIE_TOP_MIMRXRDATA25", - "PCIE_IMUX9_R_4", - "PCIE_WW2A1_4", - "PCIE_NW2A0_4", - "PCIE_IMUX43_R_4", - "PCIE_IMUX20_R_2", - "PCIE_TOP_TRNTDLLPSRCRDY", - "PCIE_FAN2_R_1", - "PCIE_TOP_TRNTD34", - "PCIE_CTRL1_R_1", - "PCIE_IMUX32_L_1", - "PCIE_TOP_TRNTD35", - "PCIE_IMUX5_R_2", - "PCIE_EE4BEG0_4", - "PCIE_EE2A3_2", - "PCIE_WW4B0_4", - "PCIE_EE2BEG1_0", - "PCIE_TOP_TRNRDLLPSRCRDY1", - "PCIE_TOP_MIMRXRDATA53", - "PCIE_IMUX13_L_2", - "PCIE_EL1BEG0_2", - "PCIE_WW2END3_3", - "PCIE_WL1END2_4", - "PCIE_TOP_CFGPMCSRPOWERSTATE1", - "PCIE_SE4C3_2", - "PCIE_TOP_DRPDI3", - "PCIE_TOP_CFGVCTCVCMAP2", - "PCIE_SW2A1_4", - "PCIE_IMUX0_L_4", - "PCIE_EL1BEG1_0", - "PCIE_TOP_DRPDO3", - "PCIE_TOP_TRNRD96", - "PCIE_WW2A3_2", - "PCIE_TOP_TRNRD87", - "PCIE_IMUX11_R_1", - "PCIE_LOGIC_OUTS_B13_R_0", - "PCIE_IMUX3_R_4", - "PCIE_EE2A0_1", - "PCIE_BYP5_R_0", - "PCIE_NE2A1_0", - "PCIE_BYP1_R_2", - "PCIE_NW4END1_1", - "PCIE_WR1END0_4", - "PCIE_WW2END0_1", - "PCIE_WW4A2_2", - "PCIE_EE2BEG3_0", - "PCIE_IMUX37_R_0", - "PCIE_NW4A3_4", - "PCIE_SW4END0_4", - "PCIE_IMUX27_R_2", - "PCIE_EE4A3_3", - "PCIE_TOP_DBGVECA18", - "PCIE_IMUX16_L_3", - "PCIE_TOP_TRNRD88", - "PCIE_IMUX19_R_0", - "PCIE_BYP0_L_3", - "PCIE_LOGIC_OUTS_B4_L_3", - "PCIE_TOP_TRNRD84", - "PCIE_TOP_PIPERX0DATA5", - "PCIE_TOP_MIMRXRDATA35", - "PCIE_WW4B2_0", - "PCIE_WW4A3_1", - "PCIE_LOGIC_OUTS_B5_R_3", - "PCIE_CLK1_L_3", - "PCIE_IMUX22_L_0", - "PCIE_TOP_TRNTDLLPDATA30", - "PCIE_EE4A0_0", - "PCIE_EE4A1_0", - "PCIE_WL1END3_3", - "PCIE_IMUX10_L_4", - "PCIE_TOP_MIMRXRDATA45", - "PCIE_LOGIC_OUTS_B4_R_0", - "PCIE_BYP5_R_2", - "PCIE_IMUX34_L_2", - "PCIE_FAN0_L_0", - "PCIE_EE4C3_4", - "PCIE_TOP_PL2DIRECTEDLSTATE0", - "PCIE_LOGIC_OUTS_B7_L_4", - "PCIE_IMUX38_L_4", - "PCIE_IMUX25_L_1", - "PCIE_TOP_TRNRD65", - "PCIE_TOP_MIMRXRADDR2", - "PCIE_IMUX19_L_0", - "PCIE_IMUX24_L_0", - "PCIE_LOGIC_OUTS_B6_R_2", - "PCIE_TOP_CFGERRAERHEADERLOG7", - "PCIE_TOP_MIMRXWDATA19", - "PCIE_TOP_MIMRXRDATA43", - "PCIE_TOP_MIMRXWDATA25", - "PCIE_IMUX26_R_3", - "PCIE_TOP_MIMRXWDATA33", - "PCIE_LOGIC_OUTS_B20_L_3", - "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK", - "PCIE_WW4A1_2", - "PCIE_LH6_0", - "PCIE_CLK0_R_4", - "PCIE_TOP_TRNRDLLPDATA55", - "PCIE_LOGIC_OUTS_B0_R_3", - "PCIE_TOP_CFGERRTLPCPLHEADER41", - "PCIE_SW2A3_2", - "PCIE_TOP_DBGVECA0", - "PCIE_IMUX13_R_0", - "PCIE_WW2A2_0", - "PCIE_NE2A3_2", - "PCIE_IMUX14_R_2", - "PCIE_FAN7_R_1", - "PCIE_NE2A2_1", - "PCIE_LOGIC_OUTS_B6_R_4", - "PCIE_TOP_MIMRXWDATA29", - "PCIE_SE4C0_2", - "PCIE_SE4BEG2_4", - "PCIE_LH3_0", - "PCIE_IMUX15_R_3", - "PCIE_NE2A2_4", - "PCIE_LOGIC_OUTS_B7_R_3", - "PCIE_TOP_DBGVECA12", - "PCIE_TOP_CFGERRAERHEADERLOG11", - "PCIE_LH5_2", - "PCIE_IMUX7_L_3", - "PCIE_ER1BEG1_0", - "PCIE_IMUX0_R_1", - "PCIE_IMUX29_L_2", - "PCIE_TOP_TRNRDLLPDATA38", - "PCIE_FAN6_L_2", - "PCIE_TOP_MIMRXWEN", - "PCIE_LOGIC_OUTS_B7_L_3", - "PCIE_ER1BEG3_0", - "PCIE_WW4B3_1", - "PCIE_WW4A0_1", - "PCIE_LOGIC_OUTS_B16_R_4", - "PCIE_EE2A1_4", - "PCIE_SE4C1_3", - "PCIE_EE4BEG3_1", - "PCIE_IMUX36_L_2", - "PCIE_LOGIC_OUTS_B5_R_1", - "PCIE_TOP_TRNRD76", - "PCIE_TOP_CFGERRTLPCPLHEADER33", - "PCIE_LOGIC_OUTS_B13_L_0", - "PCIE_IMUX16_R_3", - "PCIE_IMUX32_L_2", - "PCIE_CTRL1_R_0", - "PCIE_EE2BEG2_4", - "PCIE_WW4C0_1", - "PCIE_TOP_TRNRDLLPDATA37", - "PCIE_LOGIC_OUTS_B14_R_4", - "PCIE_IMUX31_R_4", - "PCIE_TOP_CFGERRTLPCPLHEADER36", - "PCIE_NW2A2_2", - "PCIE_TOP_TRNRDLLPDATA39", - "PCIE_IMUX36_L_3", - "PCIE_TOP_DRPDO12", - "PCIE_IMUX25_L_0", - "PCIE_IMUX37_L_4", - "PCIE_IMUX30_L_0", - "PCIE_IMUX15_L_3", - "PCIE_LOGIC_OUTS_B15_R_3", - "PCIE_IMUX31_R_2", - "PCIE_LOGIC_OUTS_B4_L_1", - "PCIE_BYP2_R_1", - "PCIE_LOGIC_OUTS_B21_L_2", - "PCIE_IMUX47_R_0", - "PCIE_WW2END3_1", - "PCIE_LH12_4", - "PCIE_NE4BEG0_0", - "PCIE_WW4B3_4", - "PCIE_LH7_4", - "PCIE_SE4BEG0_3", - "PCIE_NW4A3_2", - "PCIE_IMUX17_L_2", - "PCIE_IMUX18_R_1", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS", - "PCIE_LOGIC_OUTS_B2_L_3", - "PCIE_LOGIC_OUTS_B10_L_3", - "PCIE_IMUX20_L_3", - "PCIE_IMUX40_R_2", - "PCIE_IMUX19_R_2", - "PCIE_SW2A1_0", - "PCIE_TOP_TRNTD14", - "PCIE_TOP_MIMRXRDATA50", - "PCIE_TOP_TRNRD78", - "PCIE_SW4END1_3", - "PCIE_WW2A3_3", - "PCIE_LOGIC_OUTS_B8_L_3", - "PCIE_EE4C2_4", - "PCIE_BYP7_R_3", - "PCIE_IMUX19_R_1", - "PCIE_WW4C3_3", - "PCIE_LOGIC_OUTS_B22_R_1", - "PCIE_SW2A0_1", - "PCIE_SE2A1_1", - "PCIE_WL1END2_0", - "PCIE_IMUX40_R_1", - "PCIE_NW4A0_1", - "PCIE_WL1END1_0", - "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN", - "PCIE_TOP_TRNTD22", - "PCIE_TOP_CFGERRTLPCPLHEADER30", - "PCIE_TOP_CFGLINKCONTROLRCB", - "PCIE_IMUX39_R_1", - "PCIE_IMUX3_R_2", - "PCIE_IMUX18_L_0", - "PCIE_SW4A2_2", - "PCIE_TOP_LL2SUSPENDNOW", - "PCIE_ER1BEG1_1", - "PCIE_WW4END2_4", - "PCIE_LH11_0", - "PCIE_IMUX0_R_3", - "PCIE_IMUX21_L_4", - "PCIE_WR1END1_2", - "PCIE_BYP4_R_1", - "PCIE_TOP_CFGTRANSACTIONADDR5", - "PCIE_IMUX41_L_4", - "PCIE_LOGIC_OUTS_B9_L_2", - "PCIE_TOP_DRPDO2", - "PCIE_IMUX32_L_4", - "PCIE_TOP_MIMRXWDATA32", - "PCIE_WL1END2_3", - "PCIE_IMUX2_R_3", - "PCIE_LH4_0", - "PCIE_TOP_TRNRD94", - "PCIE_IMUX14_L_1", - "PCIE_TOP_MIMRXWDATA7", - "PCIE_TOP_TRNRD77", - "PCIE_TOP_TRNRDLLPDATA54", - "PCIE_NW2A1_2", - "PCIE_WL1END0_4", - "PCIE_TOP_TRNRDLLPDATA43", - "PCIE_IMUX32_R_1", - "PCIE_TOP_PIPERX0VALID", - "PCIE_IMUX4_L_1", - "PCIE_TOP_CFGMGMTDO21", - "PCIE_TOP_PL2DIRECTEDLSTATE1", - "PCIE_LH3_3", - "PCIE_LOGIC_OUTS_B3_R_1", - "PCIE_LOGIC_OUTS_B0_L_0", - "PCIE_NE2A0_2", - "PCIE_TOP_DRPDI12", - "PCIE_TOP_CFGINTERRUPTDI0", - "PCIE_IMUX28_R_3", - "PCIE_LOGIC_OUTS_B1_L_4", - "PCIE_LOGIC_OUTS_B4_L_4", - "PCIE_TOP_DRPDO0", - "PCIE_CLK1_L_0", - "PCIE_EE4A2_0", - "PCIE_NE2A0_1", - "PCIE_IMUX34_R_4", - "PCIE_SW2A2_3", - "PCIE_NW2A0_0", - "PCIE_LH5_0", - "PCIE_NW2A3_4", - "PCIE_EE4C0_0", - "PCIE_TOP_DRPDI11", - "PCIE_TOP_TRNTD37", - "PCIE_IMUX1_R_1", - "PCIE_LOGIC_OUTS_B12_L_0", - "PCIE_NE4C0_4", - "PCIE_LOGIC_OUTS_B23_R_3", - "PCIE_IMUX10_L_0", - "PCIE_IMUX29_L_0", - "PCIE_IMUX33_R_1", - "PCIE_SW2A2_0", - "PCIE_TOP_PIPETXMARGIN2", - "PCIE_WW4A1_1", - "PCIE_IMUX26_R_4", - "PCIE_FAN2_R_2", - "PCIE_LOGIC_OUTS_B2_R_2", - "PCIE_CTRL0_L_0", - "PCIE_NE2A3_4", - "PCIE_FAN3_R_4", - "PCIE_TOP_CFGERRTLPCPLHEADER32", - "PCIE_BLOCK_OUTS_B0_R_3", - "PCIE_IMUX17_R_0", - "PCIE_TOP_TRNRDLLPDATA36", - "PCIE_TOP_CFGERRAERHEADERLOG6", - "PCIE_IMUX35_L_2", - "PCIE_IMUX23_R_0", - "PCIE_FAN6_R_1", - "PCIE_IMUX37_L_3", - "PCIE_IMUX20_L_2", - "PCIE_EE2BEG2_1", - "PCIE_IMUX40_L_4", - "PCIE_TOP_TRNRD95", - "PCIE_IMUX16_L_4", - "PCIE_IMUX39_L_2", - "PCIE_NW4A3_0", - "PCIE_WW2END2_3", - "PCIE_SW4END2_3", - "PCIE_IMUX7_L_1", - "PCIE_SW4END1_1", - "PCIE_IMUX38_R_1", - "PCIE_WW4B3_0", - "PCIE_SE2A0_2", - "PCIE_LOGIC_OUTS_B9_R_3", - "PCIE_LH7_2", - "PCIE_SE2A3_3", - "PCIE_LOGIC_OUTS_B15_L_3", - "PCIE_IMUX6_R_0", - "PCIE_IMUX10_R_3", - "PCIE_TOP_MIMRXRDATA21", - "PCIE_WW4A2_1", - "PCIE_WW4C0_0", - "PCIE_IMUX21_R_0", - "PCIE_IMUX2_L_1", - "PCIE_SW4END0_0", - "PCIE_LOGIC_OUTS_B4_R_3", - "PCIE_WR1END1_1", - "PCIE_EE2A2_1", - "PCIE_LOGIC_OUTS_B3_L_2", - "PCIE_TOP_TRNTD33", - "PCIE_LOGIC_OUTS_B19_R_4", - "PCIE_WW4C1_3", - "PCIE_SW4END3_0", - "PCIE_IMUX20_L_1", - "PCIE_TOP_DBGVECA13", - "PCIE_IMUX44_L_0", - "PCIE_TOP_LL2SENDENTERL1", - "PCIE_WW4END1_1", - "PCIE_EE4C0_2", - "PCIE_EE4A1_3", - "PCIE_LOGIC_OUTS_B10_R_4", - "PCIE_FAN3_L_0", - "PCIE_FAN7_R_0", - "PCIE_ER1BEG1_2", - "PCIE_FAN6_L_4", - "PCIE_TOP_DRPDI9", - "PCIE_TOP_PL2DIRECTEDLSTATE3", - "PCIE_CLK1_R_0", - "PCIE_IMUX5_L_1", - "PCIE_SW4A3_3", - "PCIE_IMUX35_L_0", - "PCIE_WW2A1_3", - "PCIE_TOP_CFGERRTLPCPLHEADER35", - "PCIE_EE4B2_4", - "PCIE_TOP_CFGDEVID12", - "PCIE_IMUX0_R_2", - "PCIE_NE4BEG0_3", - "PCIE_TOP_MIMRXWDATA10", - "PCIE_IMUX13_R_1", - "PCIE_BLOCK_OUTS_B0_R_2", - "PCIE_EE2A1_3", - "PCIE_FAN6_L_0", - "PCIE_IMUX4_R_4", - "PCIE_IMUX0_L_1", - "PCIE_TOP_CFGERRTLPCPLHEADER38", - "PCIE_IMUX21_L_0", - "PCIE_LOGIC_OUTS_B18_L_2", - "PCIE_SE4C0_0", - "PCIE_LH1_4", - "PCIE_IMUX32_R_4", - "PCIE_LOGIC_OUTS_B19_L_1", - "PCIE_TOP_TRNRDLLPDATA59", - "PCIE_SE2A1_3", - "PCIE_LOGIC_OUTS_B0_R_2", - "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS", - "PCIE_IMUX44_L_2", - "PCIE_EL1BEG1_3", - "PCIE_BYP7_R_4", - "PCIE_IMUX22_L_1", - "PCIE_LOGIC_OUTS_B6_L_0", - "PCIE_SE4C0_3", - "PCIE_WW2A2_2", - "PCIE_NW2A3_0", - "PCIE_SW4END0_2", - "PCIE_WW4END2_0", - "PCIE_IMUX39_L_4", - "PCIE_SE4BEG2_2", - "PCIE_TOP_MIMRXWDATA30", - "PCIE_BLOCK_OUTS_B1_L_2", - "PCIE_EL1BEG1_2", - "PCIE_IMUX25_L_2", - "PCIE_IMUX17_R_2", - "PCIE_TOP_PIPERX4DATA6", - "PCIE_BYP6_R_3", - "PCIE_TOP_TRNTDSTRDY3", - "PCIE_IMUX14_L_0", - "PCIE_LOGIC_OUTS_B13_R_3", - "PCIE_TOP_CFGMGMTDO23", - "PCIE_IMUX9_R_3", - "PCIE_IMUX7_R_2", - "PCIE_IMUX1_R_2", - "PCIE_TOP_MIMRXRDATA34", - "PCIE_TOP_MIMRXRADDR8", - "PCIE_IMUX2_L_0", - "PCIE_IMUX4_R_1", - "PCIE_TOP_MIMRXRADDR10", - "PCIE_TOP_CFGDEVID5", - "PCIE_IMUX35_L_3", - "PCIE_IMUX2_R_0", - "PCIE_IMUX44_L_4", - "PCIE_WW4C2_3", - "PCIE_IMUX10_R_4", - "PCIE_IMUX3_L_1", - "PCIE_IMUX23_L_0", - "PCIE_LOGIC_OUTS_B18_L_4", - "PCIE_LH3_2", - "PCIE_NE4BEG1_4", - "PCIE_WW4B0_2", - "PCIE_LH9_0", - "PCIE_IMUX12_R_0", - "PCIE_TOP_CFGDEVID0", - "PCIE_TOP_CFGDEVID6", - "PCIE_BYP4_L_4", - "PCIE_FAN5_R_1", - "PCIE_BLOCK_OUTS_B3_R_0", - "PCIE_WW4END2_2", - "PCIE_CTRL1_L_3", - "PCIE_LOGIC_OUTS_B18_R_3", - "PCIE_TOP_MIMRXRDATA51", - "PCIE_NW4END1_4", - "PCIE_EE2BEG3_2", - "PCIE_IMUX14_R_1", - "PCIE_TOP_TRNTDLLPDATA26", - "PCIE_TOP_DRPDO11", - "PCIE_IMUX25_L_3", - "PCIE_WR1END2_3", - "PCIE_TOP_CFGDSN58", - "PCIE_WW2END2_4", - "PCIE_LH4_3", - "PCIE_EE4B0_3", - "PCIE_TOP_CFGPMRCVENTERL23N", - "PCIE_TOP_TRNRD71", - "PCIE_SW4A1_4", - "PCIE_TOP_MIMRXRDATA37", - "PCIE_FAN0_L_1", - "PCIE_BLOCK_OUTS_B3_R_3", - "PCIE_TOP_TRNRD83", - "PCIE_SE4C0_4", - "PCIE_BYP4_R_2", - "PCIE_LOGIC_OUTS_B14_L_4", - "PCIE_IMUX44_R_0", - "PCIE_LH11_1", - "PCIE_TOP_CFGPMRCVASREQL1N", - "PCIE_BYP7_L_4", - "PCIE_IMUX33_L_0", - "PCIE_TOP_MIMRXWDATA31", - "PCIE_SW4END3_1", - "PCIE_SE2A0_3", - "PCIE_LOGIC_OUTS_B7_R_0", - "PCIE_TOP_CFGDEVCONTROL2LTREN", - "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED", - "PCIE_LOGIC_OUTS_B21_R_1", - "PCIE_IMUX9_L_2", - "PCIE_NW2A1_4", - "PCIE_SW2A0_2", - "PCIE_IMUX2_R_2", - "PCIE_TOP_TRNTD25", - "PCIE_BYP7_R_0", - "PCIE_WW2A1_1", - "PCIE_IMUX10_L_3", - "PCIE_IMUX30_R_3", - "PCIE_ER1BEG3_2", - "PCIE_LOGIC_OUTS_B0_L_3", - "PCIE_TOP_DRPDO13", - "PCIE_FAN0_R_3", - "PCIE_LOGIC_OUTS_B8_R_4", - "PCIE_FAN2_L_4", - "PCIE_NE2A3_3", - "PCIE_NW4A0_2", - "PCIE_IMUX29_L_4", - "PCIE_TOP_PIPERX0DATA6", - "PCIE_LOGIC_OUTS_B0_R_0", - "PCIE_MONITOR_P_0", - "PCIE_TOP_CFGDEVID3", - "PCIE_LOGIC_OUTS_B11_L_0", - "PCIE_IMUX15_L_2", - "PCIE_NW4A1_1", - "PCIE_LOGIC_OUTS_B5_R_2", - "PCIE_IMUX6_L_1", - "PCIE_IMUX40_R_0", - "PCIE_TOP_MIMRXRDATA47", - "PCIE_EE4B3_3", - "PCIE_SW4A1_2", - "PCIE_TOP_CFGTRANSACTIONADDR3", - "PCIE_SE4C3_0", - "PCIE_LOGIC_OUTS_B17_R_4", - "PCIE_SW2A3_0", - "PCIE_TOP_TRNTDLLPDATA22", - "PCIE_TOP_MIMRXWDATA17", - "PCIE_SW4A1_1", - "PCIE_IMUX46_L_3", - "PCIE_LH12_1", - "PCIE_SE4C1_4", - "PCIE_IMUX29_R_1", - "PCIE_IMUX2_L_2", - "PCIE_IMUX13_R_2", - "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN", - "PCIE_WW2END0_3", - "PCIE_IMUX11_R_0", - "PCIE_LOGIC_OUTS_B17_R_3", - "PCIE_IMUX35_R_3", - "PCIE_NE2A1_2", - "PCIE_EE2BEG0_2", - "PCIE_TOP_CFGLINKCONTROLLINKDISABLE", - "PCIE_LOGIC_OUTS_B19_L_4", - "PCIE_IMUX24_R_4", - "PCIE_EE4B1_1", - "PCIE_FAN4_R_4", - "PCIE_IMUX3_L_4", - "PCIE_LOGIC_OUTS_B5_L_2", - "PCIE_IMUX1_L_4", - "PCIE_EL1BEG1_1", - "PCIE_FAN7_L_0", - "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED", - "PCIE_BYP6_R_2", - "PCIE_SW4END3_3", - "PCIE_LOGIC_OUTS_B14_L_3", - "PCIE_FAN4_L_4", - "PCIE_WR1END0_1", - "PCIE_LOGIC_OUTS_B15_L_1", - "PCIE_TOP_DBGVECA3", - "PCIE_TOP_DRPDI5", - "PCIE_IMUX38_L_2", - "PCIE_BYP1_L_2", - "PCIE_TOP_MIMRXRDATA32", - "PCIE_TOP_MIMRXRDATA22", - "PCIE_TOP_DBGVECA15", - "PCIE_SE4C2_1", - "PCIE_TOP_CFGERRLOCKEDN", - "PCIE_IMUX14_L_3", - "PCIE_FAN0_L_4", - "PCIE_BYP3_L_2", - "PCIE_EE2BEG0_3", - "PCIE_EE2BEG2_2", - "PCIE_BLOCK_OUTS_B0_R_0", - "PCIE_SW4A1_3", - "PCIE_SE4BEG1_4", - "PCIE_TOP_LL2SENDENTERL23", - "PCIE_LOGIC_OUTS_B1_L_2", - "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK", - "PCIE_NE2A0_4", - "PCIE_WL1END0_3", - "PCIE_IMUX47_L_3", - "PCIE_IMUX15_L_4", - "PCIE_LOGIC_OUTS_B18_R_1", - "PCIE_TOP_MIMRXWDATA26", - "PCIE_IMUX43_L_1", - "PCIE_CLK0_L_0", - "PCIE_WR1END3_3", - "PCIE_EE4C2_2", - "PCIE_LOGIC_OUTS_B12_R_1", - "PCIE_IMUX34_R_2", - "PCIE_WW4A1_3", - "PCIE_WW4C3_2", - "PCIE_EE4C2_3", - "PCIE_LOGIC_OUTS_B9_R_4", - "PCIE_EE4A0_2", - "PCIE_NE4C2_0", - "PCIE_IMUX21_L_2", - "PCIE_NW4A3_3", - "PCIE_LOGIC_OUTS_B5_R_4", - "PCIE_NE2A0_3", - "PCIE_IMUX19_L_2", - "PCIE_IMUX45_L_4", - "PCIE_IMUX5_R_0", - "PCIE_SW2A1_1", - "PCIE_CTRL0_L_2", - "PCIE_IMUX41_L_2", - "PCIE_LOGIC_OUTS_B21_R_2", - "PCIE_CLK1_L_1", - "PCIE_IMUX4_L_3", - "PCIE_FAN1_R_1", - "PCIE_LOGIC_OUTS_B4_L_0", - "PCIE_WW4END2_3", - "PCIE_FAN6_R_2", - "PCIE_TOP_MIMRXWDATA1", - "PCIE_IMUX1_L_1", - "PCIE_BYP3_L_3", - "PCIE_TOP_CFGERRTLPCPLHEADER27", - "PCIE_TOP_PIPERX0DATA7", - "PCIE_NE2A3_0", - "PCIE_LH3_4", - "PCIE_TOP_TRNRD82", - "PCIE_BLOCK_OUTS_B1_R_2", - "PCIE_FAN0_R_0", - "PCIE_NW4A2_2", - "PCIE_EE4B1_3", - "PCIE_IMUX22_R_4", - "PCIE_IMUX5_L_4", - "PCIE_LOGIC_OUTS_B16_L_3", - "PCIE_SW4A0_0", - "PCIE_IMUX3_L_2", - "PCIE_TOP_DBGVECA9", - "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN", - "PCIE_LOGIC_OUTS_B3_L_3", - "PCIE_TOP_DRPDI6", - "PCIE_SE4C1_1", - "PCIE_FAN0_L_2", - "PCIE_NE4BEG0_4", - "PCIE_IMUX8_L_2", - "PCIE_TOP_TRNTDLLPDATA23", - "PCIE_LOGIC_OUTS_B20_R_3", - "PCIE_CLK1_R_3", - "PCIE_SE4BEG1_1", - "PCIE_EE4BEG2_0", - "PCIE_CTRL0_L_3", - "PCIE_IMUX43_L_3", - "PCIE_IMUX10_R_2", - "PCIE_WW2A2_1", - "PCIE_WW4END2_1", - "PCIE_LOGIC_OUTS_B17_L_4", - "PCIE_LOGIC_OUTS_B23_R_1", - "PCIE_TOP_TRNRD89", - "PCIE_WW4C2_0", - "PCIE_FAN5_L_4", - "PCIE_NE4C1_4", - "PCIE_WW4A3_2", - "PCIE_TOP_CFGERRTLPCPLHEADER26", - "PCIE_LH12_3", - "PCIE_WW4END0_0", - "PCIE_LH11_2", - "PCIE_IMUX11_L_0", - "PCIE_WR1END0_0", - "PCIE_TOP_PIPERX4DATA5", - "PCIE_LOGIC_OUTS_B21_R_0", - "PCIE_IMUX30_R_0", - "PCIE_SE2A2_2", - "PCIE_NW4END0_0", - "PCIE_IMUX25_R_2", - "PCIE_TOP_CFGERRAERHEADERLOG2", - "PCIE_WW4B3_2", - "PCIE_IMUX16_R_0", - "PCIE_TOP_MIMRXRDATA41", - "PCIE_EL1BEG3_4", - "PCIE_EE2BEG3_1", - "PCIE_TOP_CFGERRAERHEADERLOG1", - "PCIE_IMUX33_L_3", - "PCIE_NW4END2_4", - "PCIE_IMUX1_R_0", - "PCIE_LOGIC_OUTS_B6_R_1", - "PCIE_BLOCK_OUTS_B2_L_4", - "PCIE_IMUX23_L_2", - "PCIE_LOGIC_OUTS_B0_L_2", - "PCIE_IMUX9_L_3", - "PCIE_TOP_TRNTD15", - "PCIE_EL1BEG3_2", - "PCIE_FAN1_L_1", - "PCIE_LOGIC_OUTS_B9_L_0", - "PCIE_LOGIC_OUTS_B13_L_2", - "PCIE_BYP0_R_1", - "PCIE_TOP_MIMRXWDATA5", - "PCIE_WR1END1_0", - "PCIE_TOP_TRNRD97", - "PCIE_IMUX13_L_0", - "PCIE_IMUX42_R_4", - "PCIE_IMUX38_R_3", - "PCIE_NE2A2_2", - "PCIE_MONITOR_P_4", - "PCIE_BYP0_R_3", - "PCIE_IMUX15_R_2", - "PCIE_IMUX4_L_4", - "PCIE_LOGIC_OUTS_B23_R_2", - "PCIE_SW2A1_3", - "PCIE_WL1END2_2", - "PCIE_EE2BEG0_0", - "PCIE_IMUX6_R_3", - "PCIE_BLOCK_OUTS_B3_R_1", - "PCIE_IMUX1_L_2", - "PCIE_WW4A1_4", - "PCIE_IMUX3_R_1", - "PCIE_TOP_TRNTDLLPDATA20", - "PCIE_IMUX43_R_2", - "PCIE_NE2A0_0", - "PCIE_BLOCK_OUTS_B2_L_0", - "PCIE_EE2A2_0", - "PCIE_IMUX14_L_2", - "PCIE_BLOCK_OUTS_B3_L_4", - "PCIE_TOP_SCANENABLEN", - "PCIE_LH9_1", - "PCIE_IMUX28_R_1", - "PCIE_WL1END1_4", - "PCIE_CLK0_L_3", - "PCIE_TOP_MIMRXRDATA54", - "PCIE_WW2END2_2", - "PCIE_IMUX24_R_3", - "PCIE_IMUX46_R_4", - "PCIE_IMUX7_R_0", - "PCIE_IMUX32_L_3", - "PCIE_TOP_CFGVCTCVCMAP3", - "PCIE_BYP3_L_4", - "PCIE_BYP0_L_4", - "PCIE_TOP_TRNTD31", - "PCIE_WW4END1_4", - "PCIE_BYP4_L_1", - "PCIE_LOGIC_OUTS_B6_R_3", - "PCIE_TOP_CFGPMCSRPMEEN", - "PCIE_FAN1_R_3", - "PCIE_TOP_TRNTDLLPDATA29", - "PCIE_ER1BEG2_2", - "PCIE_BLOCK_OUTS_B1_L_0", - "PCIE_BYP5_R_4", - "PCIE_SW4END2_0", - "PCIE_TOP_TRNRD91", - "PCIE_IMUX13_R_4", - "PCIE_TOP_PIPETXMARGIN1", - "PCIE_IMUX40_R_3", - "PCIE_TOP_LL2TFCINIT1SEQ", - "PCIE_EE2A1_1", - "PCIE_LOGIC_OUTS_B18_L_1", - "PCIE_IMUX26_L_0", - "PCIE_WR1END2_4", - "PCIE_LOGIC_OUTS_B14_L_2", - "PCIE_NW4A2_3", - "PCIE_TOP_CFGMGMTDO22", - "PCIE_NW4A1_2", - "PCIE_TOP_CFGVCTCVCMAP6", - "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE", - "PCIE_IMUX34_R_0", - "PCIE_TOP_MIMRXWDATA22", - "PCIE_TOP_CFGMGMTDO26", - "PCIE_IMUX6_L_2", - "PCIE_TOP_MIMRXWDATA20", - "PCIE_LOGIC_OUTS_B18_R_0", - "PCIE_LOGIC_OUTS_B17_R_1", - "PCIE_FAN2_L_2", - "PCIE_IMUX3_L_0", - "PCIE_LOGIC_OUTS_B14_R_1", - "PCIE_LOGIC_OUTS_B18_L_0", - "PCIE_EE2BEG3_4", - "PCIE_WW4END0_1", - "PCIE_EE2A0_0", - "PCIE_CTRL0_R_2", - "PCIE_IMUX15_L_1", - "PCIE_TOP_MIMRXRDATA31", - "PCIE_BLOCK_OUTS_B0_L_3", - "PCIE_TOP_MIMRXRDATA36", - "PCIE_TOP_TRNTDLLPDATA21", - "PCIE_WW2END1_0", - "PCIE_NE4C1_3", - "PCIE_IMUX33_R_2", - "PCIE_WW4C2_4", - "PCIE_TOP_PIPERX0DATA2", - "PCIE_IMUX23_R_1", - "PCIE_LH9_3", - "PCIE_WW2END1_2", - "PCIE_TOP_CFGMGMTDO18", - "PCIE_IMUX1_R_3", - "PCIE_FAN4_R_3", - "PCIE_TOP_TRNTD9", - "PCIE_IMUX22_L_4", - "PCIE_TOP_CFGMGMTDO27", - "PCIE_IMUX27_R_1", - "PCIE_NE2A3_1", - "PCIE_TOP_DBGVECA8", - "PCIE_EE4B0_1", - "PCIE_LH7_3", - "PCIE_LOGIC_OUTS_B20_R_0", - "PCIE_IMUX4_R_0", - "PCIE_FAN1_L_0", - "PCIE_SW4END1_0", - "PCIE_TOP_DBGVECA10", - "PCIE_IMUX21_R_2", - "PCIE_TOP_TRNRD68", - "PCIE_IMUX31_L_4", - "PCIE_CLK1_R_4", - "PCIE_IMUX31_R_0", - "PCIE_IMUX43_R_1", - "PCIE_LOGIC_OUTS_B22_R_4", - "PCIE_IMUX46_R_2", - "PCIE_IMUX28_R_0", - "PCIE_NE4BEG3_1", - "PCIE_LOGIC_OUTS_B12_L_4", - "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN", - "PCIE_SE2A3_2", - "PCIE_WL1END1_2", - "PCIE_IMUX39_R_0", - "PCIE_WR1END3_0", - "PCIE_SW4END3_4", - "PCIE_LOGIC_OUTS_B20_L_0", - "PCIE_IMUX28_L_0", - "PCIE_BYP1_R_3", - "PCIE_NW4END2_2", - "PCIE_IMUX34_R_1", - "PCIE_IMUX12_L_2", - "PCIE_IMUX30_R_2", - "PCIE_LOGIC_OUTS_B1_L_0", - "PCIE_WW2A2_4", - "PCIE_SW2A3_3", - "PCIE_NE4BEG1_0", - "PCIE_IMUX39_L_1", - "PCIE_WW2A2_3", - "PCIE_EE2A0_2", - "PCIE_CLK1_L_4", - "PCIE_IMUX24_R_0", - "PCIE_TOP_MIMRXRDATA49", - "PCIE_TOP_MIMRXRDATA44", - "PCIE_IMUX14_L_4", - "PCIE_TOP_CFGERRTLPCPLHEADER46", - "PCIE_IMUX36_L_0", - "PCIE_TOP_TRNTDLLPDATA19", - "PCIE_IMUX42_R_1", - "PCIE_LH5_3", - "PCIE_TOP_CFGMGMTDO19", - "PCIE_EE4B0_4", - "PCIE_TOP_DBGVECA20", - "PCIE_FAN2_R_3", - "PCIE_EL1BEG3_3", - "PCIE_TOP_PL2DIRECTEDLSTATE4", - "PCIE_FAN4_L_0" - ], - "sites": [], "pips": { - "PCIE_TOP.PCIE_IMUX13_L_0->PCIE_TOP_DRPADDR8": { + "PCIE_TOP.PCIE_TOP_CFGTRANSACTION->PCIE_LOGIC_OUTS_B10_L_2": { "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPADDR8", + "src_wire": "PCIE_TOP_CFGTRANSACTION", "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA8->PCIE_LOGIC_OUTS_B21_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA8", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_L_1->PCIE_TOP_TRNTDLLPDATA26": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA26", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA27->PCIE_LOGIC_OUTS_B19_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA27", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC->PCIE_LOGIC_OUTS_B13_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP4->PCIE_LOGIC_OUTS_B17_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGVCTCVCMAP4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLLINKDISABLE->PCIE_LOGIC_OUTS_B15_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGLINKCONTROLLINKDISABLE", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX13_R_0->PCIE_TOP_TRNTD41": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD41", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA11->PCIE_LOGIC_OUTS_B22_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA11", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA13->PCIE_LOGIC_OUTS_B21_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA13", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX14_R_1->PCIE_TOP_TRNTD38": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD38", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA13->PCIE_LOGIC_OUTS_B9_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA13", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECB10->PCIE_LOGIC_OUTS_B22_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECB10", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_R_0->PCIE_TOP_MIMRXRDATA52": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA52", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO16->PCIE_LOGIC_OUTS_B21_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO16", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO30->PCIE_LOGIC_OUTS_B18_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO30", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_2" }, "PCIE_TOP.PCIE_IMUX11_L_1->PCIE_TOP_CFGDEVID0": { "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID0", - "is_directional": "1", "src_wire": "PCIE_IMUX11_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_0", "is_directional": "1", - "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_R_3->PCIE_TOP_MIMRXRDATA32": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA32", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR0->PCIE_LOGIC_OUTS_B8_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_L_1->PCIE_TOP_TRNTDLLPDATA23": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA23", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD74->PCIE_LOGIC_OUTS_B3_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD74", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO4->PCIE_LOGIC_OUTS_B17_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX24_R_4->PCIE_TOP_CFGVENDID0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGVENDID0", - "is_directional": "1", - "src_wire": "PCIE_IMUX24_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXRADDR1->PCIE_LOGIC_OUTS_B11_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXRADDR1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA50->PCIE_LOGIC_OUTS_B6_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA50", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX11_L_0->PCIE_TOP_CFGDSN60": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDSN60", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX12_R_3->PCIE_TOP_TRNTD28": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD28", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA45->PCIE_LOGIC_OUTS_B5_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA45", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX2_L_1->PCIE_TOP_TRNTDLLPDATA25": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA25", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXRADDR2->PCIE_LOGIC_OUTS_B12_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXRADDR2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_R_2->PCIE_TOP_MIMRXRDATA31": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA31", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA63->PCIE_LOGIC_OUTS_B11_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA63", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA9->PCIE_LOGIC_OUTS_B3_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA9", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD86->PCIE_LOGIC_OUTS_B4_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD86", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA1->PCIE_LOGIC_OUTS_B13_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED->PCIE_LOGIC_OUTS_B16_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_L_4->PCIE_TOP_LL2SENDASREQL1": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_LL2SENDASREQL1", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX12_L_0->PCIE_TOP_DRPADDR7": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPADDR7", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL23N->PCIE_LOGIC_OUTS_B8_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPMRCVENTERL23N", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_R_3->PCIE_TOP_TRNTD21": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD21", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA4->PCIE_LOGIC_OUTS_B9_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN->PCIE_LOGIC_OUTS_B15_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA22->PCIE_LOGIC_OUTS_B15_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA22", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_L_0->PCIE_TOP_CFGERRTLPCPLHEADER26": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER26", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD87->PCIE_LOGIC_OUTS_B2_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD87", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA15->PCIE_LOGIC_OUTS_B10_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA15", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA31->PCIE_LOGIC_OUTS_B21_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA31", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA54->PCIE_LOGIC_OUTS_B7_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA54", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX8_R_4->PCIE_TOP_PL2DIRECTEDLSTATE1": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE1", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK->PCIE_LOGIC_OUTS_B12_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX11_R_0->PCIE_TOP_TRNTD11": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD11", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD75->PCIE_LOGIC_OUTS_B0_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD75", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_L_3->PCIE_TOP_TRNTDLLPSRCRDY": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPSRCRDY", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA57->PCIE_LOGIC_OUTS_B6_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA57", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX6_R_4->PCIE_TOP_TRNTD26": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD26", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK->PCIE_LOGIC_OUTS_B13_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX11_L_4->PCIE_TOP_CFGDEVID12": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID12", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPMRCVREQACKN->PCIE_LOGIC_OUTS_B9_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPMRCVREQACKN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA38->PCIE_LOGIC_OUTS_B6_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA38", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX8_L_1->PCIE_TOP_CFGDSN61": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDSN61", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA2->PCIE_LOGIC_OUTS_B18_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD64->PCIE_LOGIC_OUTS_B1_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD64", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_R_2->PCIE_TOP_MIMRXRDATA44": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA44", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX14_L_1->PCIE_TOP_DRPDI2": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI2", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD83->PCIE_LOGIC_OUTS_B0_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD83", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX33_L_1->PCIE_TOP_PIPERX0DATA2": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0DATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO2->PCIE_LOGIC_OUTS_B19_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED->PCIE_LOGIC_OUTS_B21_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX5_L_4->PCIE_TOP_CFGERRTLPCPLHEADER43": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER43", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX17_R_3->PCIE_TOP_TL2PPMSUSPENDREQ": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TL2PPMSUSPENDREQ", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX2_L_3->PCIE_TOP_LL2TLPRCV": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_LL2TLPRCV", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA12->PCIE_LOGIC_OUTS_B2_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA12", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_R_1->PCIE_TOP_TRNTD13": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD13", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL1N->PCIE_LOGIC_OUTS_B12_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPMRCVENTERL1N", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD93->PCIE_LOGIC_OUTS_B4_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD93", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPSRCRDY1->PCIE_LOGIC_OUTS_B14_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPSRCRDY1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX11_R_1->PCIE_TOP_TRNTD15": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD15", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX37_R_0->PCIE_TOP_PIPERX4PHYSTATUS": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4PHYSTATUS", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA3->PCIE_LOGIC_OUTS_B15_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX16_R_3->PCIE_TOP_LL2SUSPENDNOW": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_LL2SUSPENDNOW", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA12->PCIE_LOGIC_OUTS_B20_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA12", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE0->PCIE_LOGIC_OUTS_B10_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR3->PCIE_LOGIC_OUTS_B11_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA32->PCIE_LOGIC_OUTS_B4_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA32", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX5_R_3->PCIE_TOP_MIMRXRDATA41": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA41", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX15_R_2->PCIE_TOP_TRNTD35": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD35", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3->PCIE_LOGIC_OUTS_B13_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_R_4->PCIE_TOP_PL2DIRECTEDLSTATE2": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE2", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD89->PCIE_LOGIC_OUTS_B4_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD89", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD79->PCIE_LOGIC_OUTS_B0_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD79", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA21->PCIE_LOGIC_OUTS_B21_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA21", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX17_R_2->PCIE_TOP_CFGERRLOCKEDN": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRLOCKEDN", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO23->PCIE_LOGIC_OUTS_B15_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO23", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD63->PCIE_LOGIC_OUTS_B0_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD63", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX10_L_1->PCIE_TOP_CFGDSN63": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDSN63", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX14_L_4->PCIE_TOP_DRPDI14": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI14", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX12_L_1->PCIE_TOP_DRPDI0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI0", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA35->PCIE_LOGIC_OUTS_B11_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA35", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA60->PCIE_LOGIC_OUTS_B7_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA60", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_L_3->PCIE_TOP_CFGERRTLPCPLHEADER38": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER38", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA46->PCIE_LOGIC_OUTS_B6_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA46", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWADDR2->PCIE_LOGIC_OUTS_B0_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWADDR2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX12_L_2->PCIE_TOP_DRPDI4": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI4", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX14_L_3->PCIE_TOP_DRPDI10": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI10", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX2_R_0->PCIE_TOP_MIMRXRDATA22": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA22", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP6->PCIE_LOGIC_OUTS_B19_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGVCTCVCMAP6", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN->PCIE_LOGIC_OUTS_B12_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO25->PCIE_LOGIC_OUTS_B14_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO25", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX21_R_4->PCIE_TOP_CFGDEVID13": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID13", - "is_directional": "1", - "src_wire": "PCIE_IMUX21_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD96->PCIE_LOGIC_OUTS_B4_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD96", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX12_L_4->PCIE_TOP_DRPDI12": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI12", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA24->PCIE_LOGIC_OUTS_B0_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA24", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX6_L_0->PCIE_TOP_CFGERRTLPCPLHEADER28": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER28", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA49->PCIE_LOGIC_OUTS_B5_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA49", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA48->PCIE_LOGIC_OUTS_B4_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA48", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD77->PCIE_LOGIC_OUTS_B2_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD77", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX7_L_1->PCIE_TOP_CFGERRTLPCPLHEADER33": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER33", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX8_L_3->PCIE_TOP_CFGDEVID5": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID5", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGCOMMANDBUSMASTERENABLE->PCIE_LOGIC_OUTS_B20_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD82->PCIE_LOGIC_OUTS_B4_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD82", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_L_0->PCIE_TOP_TRNTDLLPDATA20": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA20", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXRADDR10->PCIE_LOGIC_OUTS_B3_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXRADDR10", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX34_R_0->PCIE_TOP_PIPERX4DATA7": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4DATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX2_L_2->PCIE_TOP_TRNTDLLPDATA29": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA29", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO17->PCIE_LOGIC_OUTS_B16_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO17", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO0->PCIE_LOGIC_OUTS_B17_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE1->PCIE_LOGIC_OUTS_B11_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX13_L_4->PCIE_TOP_DRPDI13": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI13", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA35->PCIE_LOGIC_OUTS_B8_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA35", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_L_4->PCIE_TOP_CFGERRTLPCPLHEADER42": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER42", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR5->PCIE_LOGIC_OUTS_B9_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR5", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWEN->PCIE_LOGIC_OUTS_B18_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX2_R_2->PCIE_TOP_MIMRXRDATA30": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA30", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP2->PCIE_LOGIC_OUTS_B19_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGVCTCVCMAP2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD95->PCIE_LOGIC_OUTS_B2_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD95", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX10_R_1->PCIE_TOP_TRNTD14": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD14", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_R_0->PCIE_TOP_TRNTD9": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD9", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPMCSRPMEEN->PCIE_LOGIC_OUTS_B8_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPMCSRPMEEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_R_2->PCIE_TOP_TRNTD17": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD17", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP3->PCIE_LOGIC_OUTS_B16_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGVCTCVCMAP3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX35_L_0->PCIE_TOP_PIPERX0DATA6": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0DATA6", - "is_directional": "1", - "src_wire": "PCIE_IMUX35_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX8_L_4->PCIE_TOP_CFGDEVID9": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID9", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO21->PCIE_LOGIC_OUTS_B12_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO21", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR2->PCIE_LOGIC_OUTS_B10_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_R_1->PCIE_TOP_MIMRXRDATA48": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA48", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX18_R_4->PCIE_TOP_CFGERRTLPCPLHEADER47": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER47", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_L_2->PCIE_TOP_TRNTDLLPDATA27": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA27", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA11->PCIE_LOGIC_OUTS_B18_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA11", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX38_R_0->PCIE_TOP_PIPERX4DATA5": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4DATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_L_2->PCIE_TOP_TRNTDLLPDATA28": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA28", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXREN->PCIE_LOGIC_OUTS_B12_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXREN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO14->PCIE_LOGIC_OUTS_B23_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO14", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO6->PCIE_LOGIC_OUTS_B19_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO6", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO1->PCIE_LOGIC_OUTS_B18_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B19_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA2->PCIE_LOGIC_OUTS_B23_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP1->PCIE_LOGIC_OUTS_B18_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGVCTCVCMAP1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA49->PCIE_LOGIC_OUTS_B5_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA49", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_L_3->PCIE_TOP_CFGDEVID6": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID6", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD94->PCIE_LOGIC_OUTS_B6_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD94", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO11->PCIE_LOGIC_OUTS_B20_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO11", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX11_L_3->PCIE_TOP_CFGDEVID8": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID8", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B13_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA51->PCIE_LOGIC_OUTS_B7_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA51", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX11_R_2->PCIE_TOP_TRNTD19": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD19", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR1->PCIE_LOGIC_OUTS_B9_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX32_R_1->PCIE_TOP_PIPERX4DATA3": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4DATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA0->PCIE_LOGIC_OUTS_B21_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA36->PCIE_LOGIC_OUTS_B4_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA36", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD60->PCIE_LOGIC_OUTS_B1_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD60", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA53->PCIE_LOGIC_OUTS_B6_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA53", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX14_R_2->PCIE_TOP_TRNTD34": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD34", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA52->PCIE_LOGIC_OUTS_B5_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA52", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX20_R_3->PCIE_TOP_CFGERRAERHEADERLOG2": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG2", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA39->PCIE_LOGIC_OUTS_B7_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA39", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX8_L_0->PCIE_TOP_CFGDSN57": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDSN57", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX10_L_3->PCIE_TOP_CFGDEVID7": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID7", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE1->PCIE_LOGIC_OUTS_B9_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPCIELINKSTATE1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_PIPETXMARGIN1->PCIE_LOGIC_OUTS_B16_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_PIPETXMARGIN1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA59->PCIE_LOGIC_OUTS_B9_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA59", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX7_L_4->PCIE_TOP_CFGERRTLPCPLHEADER45": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER45", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_L_4->PCIE_TOP_LL2SENDENTERL23": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_LL2SENDENTERL23", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONTYPE->PCIE_LOGIC_OUTS_B11_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGTRANSACTIONTYPE", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_L_2->PCIE_TOP_TRNTDLLPDATA30": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA30", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA21->PCIE_LOGIC_OUTS_B19_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA21", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX38_L_0->PCIE_TOP_PIPERX0DATA5": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0DATA5", - "is_directional": "1", - "src_wire": "PCIE_IMUX38_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD92->PCIE_LOGIC_OUTS_B3_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD92", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX13_L_2->PCIE_TOP_DRPDI5": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI5", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP5->PCIE_LOGIC_OUTS_B18_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGVCTCVCMAP5", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX14_L_2->PCIE_TOP_DRPDI6": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI6", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA25->PCIE_LOGIC_OUTS_B10_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA25", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX23_R_4->PCIE_TOP_CFGDEVID15": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID15", - "is_directional": "1", - "src_wire": "PCIE_IMUX23_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX13_L_3->PCIE_TOP_DRPDI9": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI9", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_L_1->PCIE_TOP_CFGERRTLPCPLHEADER30": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER30", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA44->PCIE_LOGIC_OUTS_B4_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA44", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPSRCRDY0->PCIE_LOGIC_OUTS_B10_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPSRCRDY0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_R_3->PCIE_TOP_MIMRXRDATA33": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA33", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX17_R_4->PCIE_TOP_CFGERRTLPCPLHEADER46": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER46", - "is_directional": "1", - "src_wire": "PCIE_IMUX17_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA41->PCIE_LOGIC_OUTS_B5_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA41", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO15->PCIE_LOGIC_OUTS_B20_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO15", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA32->PCIE_LOGIC_OUTS_B1_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA32", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX15_R_4->PCIE_TOP_CFGERRAERHEADERLOG8": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG8", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD84->PCIE_LOGIC_OUTS_B1_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD84", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2->PCIE_LOGIC_OUTS_B12_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO27->PCIE_LOGIC_OUTS_B16_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO27", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO5->PCIE_LOGIC_OUTS_B18_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO5", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA47->PCIE_LOGIC_OUTS_B7_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA47", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD97->PCIE_LOGIC_OUTS_B5_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD97", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX15_L_4->PCIE_TOP_DRPDI15": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI15", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXRADDR8->PCIE_LOGIC_OUTS_B17_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXRADDR8", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD62->PCIE_LOGIC_OUTS_B3_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD62", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA19->PCIE_LOGIC_OUTS_B8_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA19", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX33_L_0->PCIE_TOP_PIPERX0CHANISALIGNED": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0CHANISALIGNED", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA8->PCIE_LOGIC_OUTS_B8_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA8", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX12_R_2->PCIE_TOP_TRNTD32": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD32", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX21_R_3->PCIE_TOP_CFGERRAERHEADERLOG3": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG3", - "is_directional": "1", - "src_wire": "PCIE_IMUX21_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX20_R_4->PCIE_TOP_CFGINTERRUPTDI0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGINTERRUPTDI0", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX6_L_1->PCIE_TOP_CFGERRTLPCPLHEADER32": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER32", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOREQEN->PCIE_LOGIC_OUTS_B14_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOREQEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX10_R_4->PCIE_TOP_PL2DIRECTEDLSTATE3": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE3", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO22->PCIE_LOGIC_OUTS_B13_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO22", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX13_R_2->PCIE_TOP_TRNTD33": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD33", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPMCSRPMESTATUS->PCIE_LOGIC_OUTS_B9_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPMCSRPMESTATUS", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPMRCVASREQL1N->PCIE_LOGIC_OUTS_B11_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPMRCVASREQL1N", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGTRANSACTION->PCIE_LOGIC_OUTS_B10_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGTRANSACTION", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD69->PCIE_LOGIC_OUTS_B2_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD69", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX10_R_3->PCIE_TOP_TRNTD22": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD22", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD90->PCIE_LOGIC_OUTS_B6_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD90", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX5_L_2->PCIE_TOP_CFGERRTLPCPLHEADER35": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER35", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX23_R_3->PCIE_TOP_CFGERRAERHEADERLOG5": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG5", - "is_directional": "1", - "src_wire": "PCIE_IMUX23_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD66->PCIE_LOGIC_OUTS_B3_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD66", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA34->PCIE_LOGIC_OUTS_B7_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA34", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_PIPETXMARGIN0->PCIE_LOGIC_OUTS_B18_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_PIPETXMARGIN0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX37_L_0->PCIE_TOP_PIPERX0PHYSTATUS": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0PHYSTATUS", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD78->PCIE_LOGIC_OUTS_B3_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD78", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLRCB->PCIE_LOGIC_OUTS_B14_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGLINKCONTROLRCB", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA17->PCIE_LOGIC_OUTS_B23_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA17", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD71->PCIE_LOGIC_OUTS_B0_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD71", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_R_1->PCIE_TOP_MIMRXRDATA27": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA27", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO18->PCIE_LOGIC_OUTS_B17_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO18", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA51->PCIE_LOGIC_OUTS_B7_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA51", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX12_R_0->PCIE_TOP_TRNTD40": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD40", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_R_4->PCIE_TOP_MIMRXRDATA36": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA36", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX5_R_2->PCIE_TOP_MIMRXRDATA45": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA45", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX20_R_2->PCIE_TOP_CFGERRAERHEADERLOG1": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG1", - "is_directional": "1", - "src_wire": "PCIE_IMUX20_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGCOMMANDIOENABLE->PCIE_LOGIC_OUTS_B11_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGCOMMANDIOENABLE", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO26->PCIE_LOGIC_OUTS_B15_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO26", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA3->PCIE_LOGIC_OUTS_B20_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO12->PCIE_LOGIC_OUTS_B21_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO12", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO3->PCIE_LOGIC_OUTS_B16_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX14_R_3->PCIE_TOP_TRNTD30": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD30", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA20->PCIE_LOGIC_OUTS_B20_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA20", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_R_1->PCIE_TOP_MIMRXRDATA24": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA24", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_L_0->PCIE_TOP_TRNTDLLPDATA22": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA22", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_L_3->PCIE_TOP_TRNTDLLPDATA31": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA31", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA17->PCIE_LOGIC_OUTS_B9_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA17", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX12_R_1->PCIE_TOP_TRNTD36": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD36", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX33_R_1->PCIE_TOP_PIPERX4DATA2": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4DATA2", - "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX6_R_0->PCIE_TOP_MIMRXRDATA54": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA54", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA58->PCIE_LOGIC_OUTS_B7_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA58", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS->PCIE_LOGIC_OUTS_B14_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXRADDR4->PCIE_LOGIC_OUTS_B5_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXRADDR4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX13_R_3->PCIE_TOP_TRNTD29": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD29", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD81->PCIE_LOGIC_OUTS_B3_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD81", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_R_0->PCIE_TOP_MIMRXRDATA20": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA20", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP0->PCIE_LOGIC_OUTS_B17_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGVCTCVCMAP0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA6->PCIE_LOGIC_OUTS_B23_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA6", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX10_R_2->PCIE_TOP_TRNTD18": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD18", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX18_R_3->PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX24_R_3->PCIE_TOP_CFGERRAERHEADERLOG10": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG10", - "is_directional": "1", - "src_wire": "PCIE_IMUX24_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_R_0->PCIE_TOP_MIMRXRDATA21": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA21", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX12_L_3->PCIE_TOP_DRPDI8": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI8", - "is_directional": "1", - "src_wire": "PCIE_IMUX12_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD73->PCIE_LOGIC_OUTS_B2_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD73", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX7_R_0->PCIE_TOP_MIMRXRDATA55": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA55", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_PIPETXMARGIN2->PCIE_LOGIC_OUTS_B6_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_PIPETXMARGIN2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_L_3->PCIE_TOP_LL2SENDENTERL1": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_LL2SENDENTERL1", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE2->PCIE_LOGIC_OUTS_B10_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGPCIELINKSTATE2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX25_R_4->PCIE_TOP_DBGMODE0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DBGMODE0", - "is_directional": "1", - "src_wire": "PCIE_IMUX25_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX5_L_1->PCIE_TOP_CFGERRTLPCPLHEADER31": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER31", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX11_R_4->PCIE_TOP_PL2DIRECTEDLSTATE4": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE4", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_L_1->PCIE_TOP_TRNTDLLPDATA24": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA24", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX7_R_2->PCIE_TOP_MIMRXRDATA47": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA47", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX11_R_3->PCIE_TOP_TRNTD23": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD23", - "is_directional": "1", - "src_wire": "PCIE_IMUX11_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA18->PCIE_LOGIC_OUTS_B14_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA18", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD59->PCIE_LOGIC_OUTS_B0_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD59", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_L_4->PCIE_TOP_CFGDEVID10": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID10", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR4->PCIE_LOGIC_OUTS_B8_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX8_R_1->PCIE_TOP_TRNTD12": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD12", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX18_R_2->PCIE_TOP_CFGERRNORECOVERYN": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRNORECOVERYN", - "is_directional": "1", - "src_wire": "PCIE_IMUX18_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXRADDR11->PCIE_LOGIC_OUTS_B10_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXRADDR11", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA29->PCIE_LOGIC_OUTS_B8_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA29", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_R_2->PCIE_TOP_MIMRXRDATA28": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA28", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX8_L_2->PCIE_TOP_CFGDEVID1": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID1", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX10_R_0->PCIE_TOP_TRNTD10": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD10", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA56->PCIE_LOGIC_OUTS_B5_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA56", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX32_L_1->PCIE_TOP_PIPERX0DATA3": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0DATA3", - "is_directional": "1", - "src_wire": "PCIE_IMUX32_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD61->PCIE_LOGIC_OUTS_B2_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD61", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B12_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX6_L_3->PCIE_TOP_CFGERRTLPCPLHEADER40": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER40", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA20->PCIE_LOGIC_OUTS_B0_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA20", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_L_1->PCIE_TOP_CFGDSN62": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDSN62", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD85->PCIE_LOGIC_OUTS_B2_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD85", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX0_L_0->PCIE_TOP_TRNTDLLPDATA19": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA19", - "is_directional": "1", - "src_wire": "PCIE_IMUX0_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX15_R_3->PCIE_TOP_TRNTD31": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD31", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX15_L_2->PCIE_TOP_DRPDI7": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI7", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_R_2->PCIE_TOP_MIMRXRDATA29": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA29", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS->PCIE_LOGIC_OUTS_B15_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX13_R_4->PCIE_TOP_CFGERRAERHEADERLOG6": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG6", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_R_0->PCIE_TOP_MIMRXRDATA23": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA23", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX7_L_2->PCIE_TOP_CFGERRTLPCPLHEADER37": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER37", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD72->PCIE_LOGIC_OUTS_B1_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD72", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX2_R_3->PCIE_TOP_MIMRXRDATA34": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA34", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD98->PCIE_LOGIC_OUTS_B6_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD98", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX34_L_0->PCIE_TOP_PIPERX0DATA7": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0DATA7", - "is_directional": "1", - "src_wire": "PCIE_IMUX34_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOCPLEN->PCIE_LOGIC_OUTS_B15_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA19->PCIE_LOGIC_OUTS_B19_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA19", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX2_R_1->PCIE_TOP_MIMRXRDATA26": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA26", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLASPMCONTROL1->PCIE_LOGIC_OUTS_B13_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPDO13->PCIE_LOGIC_OUTS_B22_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPDO13", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX15_L_3->PCIE_TOP_DRPDI11": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI11", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_L_2->PCIE_TOP_CFGDEVID2": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID2", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD91->PCIE_LOGIC_OUTS_B1_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD91", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX36_R_0->PCIE_TOP_PIPERX4VALID": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4VALID", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX13_L_1->PCIE_TOP_DRPDI1": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI1", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR6->PCIE_LOGIC_OUTS_B10_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR6", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX10_L_0->PCIE_TOP_CFGDSN59": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDSN59", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE->PCIE_LOGIC_OUTS_B21_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DRPRDY->PCIE_LOGIC_OUTS_B16_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_DRPRDY", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX39_R_0->PCIE_TOP_PIPERX4DATA4": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4DATA4", - "is_directional": "1", - "src_wire": "PCIE_IMUX39_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA28->PCIE_LOGIC_OUTS_B14_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA28", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD80->PCIE_LOGIC_OUTS_B2_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD80", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX5_L_3->PCIE_TOP_CFGERRTLPCPLHEADER39": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER39", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD88->PCIE_LOGIC_OUTS_B3_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD88", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX5_L_0->PCIE_TOP_CFGERRTLPCPLHEADER27": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER27", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA1->PCIE_LOGIC_OUTS_B22_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA14->PCIE_LOGIC_OUTS_B20_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA14", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO24->PCIE_LOGIC_OUTS_B13_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO24", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX36_L_1->PCIE_TOP_PIPERX0DATA1": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0DATA1", - "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA10->PCIE_LOGIC_OUTS_B23_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA10", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA5->PCIE_LOGIC_OUTS_B22_L_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA5", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA16->PCIE_LOGIC_OUTS_B22_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA16", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX19_R_2->PCIE_TOP_CFGERRAERHEADERLOG0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG0", - "is_directional": "1", - "src_wire": "PCIE_IMUX19_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_R_3->PCIE_TOP_MIMRXRDATA40": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA40", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA34->PCIE_LOGIC_OUTS_B17_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA34", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX14_R_4->PCIE_TOP_CFGERRAERHEADERLOG7": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG7", - "is_directional": "1", - "src_wire": "PCIE_IMUX14_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA30->PCIE_LOGIC_OUTS_B18_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B18_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA30", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_PL2RECOVERY->PCIE_LOGIC_OUTS_B12_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_PL2RECOVERY", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNTDSTRDY3->PCIE_LOGIC_OUTS_B1_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNTDSTRDY3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA43->PCIE_LOGIC_OUTS_B7_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA43", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX6_R_3->PCIE_TOP_MIMRXRDATA42": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA42", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_L_2->PCIE_TOP_CFGERRTLPCPLHEADER34": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER34", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX5_R_4->PCIE_TOP_TRNTD25": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD25", - "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_R_1->PCIE_TOP_MIMRXRDATA25": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA25", - "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX4_R_4->PCIE_TOP_TRNTD24": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD24", - "is_directional": "1", - "src_wire": "PCIE_IMUX4_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXRADDR0->PCIE_LOGIC_OUTS_B13_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXRADDR0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD67->PCIE_LOGIC_OUTS_B0_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B0_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD67", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD70->PCIE_LOGIC_OUTS_B3_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B3_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD70", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1->PCIE_LOGIC_OUTS_B15_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX22_R_4->PCIE_TOP_CFGDEVID14": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID14", - "is_directional": "1", - "src_wire": "PCIE_IMUX22_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED->PCIE_LOGIC_OUTS_B22_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX8_R_3->PCIE_TOP_TRNTD20": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD20", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA40->PCIE_LOGIC_OUTS_B4_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B4_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA40", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCLOCKPMEN->PCIE_LOGIC_OUTS_B14_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA37->PCIE_LOGIC_OUTS_B5_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA37", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0->PCIE_LOGIC_OUTS_B14_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_L_4->PCIE_TOP_PL2DIRECTEDLSTATE0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE0", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX15_R_1->PCIE_TOP_TRNTD39": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD39", - "is_directional": "1", - "src_wire": "PCIE_IMUX15_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA6->PCIE_LOGIC_OUTS_B16_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA6", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA23->PCIE_LOGIC_OUTS_B14_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B14_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA23", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO29->PCIE_LOGIC_OUTS_B17_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO29", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO28->PCIE_LOGIC_OUTS_B16_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO28", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWADDR1->PCIE_LOGIC_OUTS_B15_R_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B15_R_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWADDR1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX6_R_1->PCIE_TOP_MIMRXRDATA50": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA50", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX7_L_0->PCIE_TOP_CFGERRTLPCPLHEADER29": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER29", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX21_R_2->PCIE_TOP_CFGERRAERHEADERLOG11": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG11", - "is_directional": "1", - "src_wire": "PCIE_IMUX21_R_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID0" }, "PCIE_TOP.PCIE_TOP_CFGCOMMANDMEMENABLE->PCIE_LOGIC_OUTS_B17_R_4": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_R_4", - "is_directional": "1", "src_wire": "PCIE_TOP_CFGCOMMANDMEMENABLE", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX39_L_0->PCIE_TOP_PIPERX0DATA4": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0DATA4", "is_directional": "1", - "src_wire": "PCIE_IMUX39_L_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_4" }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA7->PCIE_LOGIC_OUTS_B23_R_3": { + "PCIE_TOP.PCIE_IMUX3_R_0->PCIE_TOP_MIMRXRDATA23": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_3", + "src_wire": "PCIE_IMUX3_R_0", "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA7", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA23" }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA62->PCIE_LOGIC_OUTS_B10_R_2": { + "PCIE_TOP.PCIE_TOP_DBGVECA2->PCIE_LOGIC_OUTS_B23_L_2": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B10_R_2", + "src_wire": "PCIE_TOP_DBGVECA2", "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA62", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_2" }, - "PCIE_TOP.PCIE_IMUX6_L_4->PCIE_TOP_CFGERRTLPCPLHEADER44": { + "PCIE_TOP.PCIE_IMUX1_L_0->PCIE_TOP_TRNTDLLPDATA20": { "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER44", + "src_wire": "PCIE_IMUX1_L_0", "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA20" }, - "PCIE_TOP.PCIE_TOP_MIMRXWADDR5->PCIE_LOGIC_OUTS_B9_R_1": { + "PCIE_TOP.PCIE_TOP_CFGCOMMANDIOENABLE->PCIE_LOGIC_OUTS_B11_L_4": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B9_R_1", + "src_wire": "PCIE_TOP_CFGCOMMANDIOENABLE", "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWADDR5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_4" }, - "PCIE_TOP.PCIE_TOP_DBGVECA9->PCIE_LOGIC_OUTS_B22_L_4": { + "PCIE_TOP.PCIE_IMUX18_R_4->PCIE_TOP_CFGERRTLPCPLHEADER47": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_L_4", + "src_wire": "PCIE_IMUX18_R_4", "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER47" }, - "PCIE_TOP.PCIE_TOP_MIMRXRADDR9->PCIE_LOGIC_OUTS_B8_R_0": { + "PCIE_TOP.PCIE_IMUX2_R_1->PCIE_TOP_MIMRXRDATA26": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_0", + "src_wire": "PCIE_IMUX2_R_1", "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXRADDR9", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA26" }, - "PCIE_TOP.PCIE_IMUX36_R_1->PCIE_TOP_PIPERX4DATA1": { + "PCIE_TOP.PCIE_IMUX11_L_0->PCIE_TOP_CFGDSN60": { "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4DATA1", + "src_wire": "PCIE_IMUX11_L_0", "is_directional": "1", - "src_wire": "PCIE_IMUX36_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD68->PCIE_LOGIC_OUTS_B1_L_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD68", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX2_L_4->PCIE_TOP_LL2SENDPMACK": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_LL2SENDPMACK", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX37_R_1->PCIE_TOP_PIPERX4DATA0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4DATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX10_L_2->PCIE_TOP_CFGDEVID3": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID3", - "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA7->PCIE_LOGIC_OUTS_B20_L_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_L_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA7", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA33->PCIE_LOGIC_OUTS_B5_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B5_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA33", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO20->PCIE_LOGIC_OUTS_B11_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO20", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA55->PCIE_LOGIC_OUTS_B12_R_4": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B12_R_4", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA55", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_R_3->PCIE_TOP_MIMRXRDATA35": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA35", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX6_R_2->PCIE_TOP_MIMRXRDATA46": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA46", - "is_directional": "1", - "src_wire": "PCIE_IMUX6_R_2", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX16_R_4->PCIE_TOP_CFGERRAERHEADERLOG9": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG9", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX16_L_1->PCIE_TOP_PIPERX0CHARISK0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0CHARISK0", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA33->PCIE_LOGIC_OUTS_B22_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA33", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX7_R_4->PCIE_TOP_TRNTD27": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD27", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX9_L_0->PCIE_TOP_CFGDSN58": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDSN58", - "is_directional": "1", - "src_wire": "PCIE_IMUX9_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX13_R_1->PCIE_TOP_TRNTD37": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD37", - "is_directional": "1", - "src_wire": "PCIE_IMUX13_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX19_R_4->PCIE_TOP_CFGINTERRUPTN": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGINTERRUPTN", - "is_directional": "1", - "src_wire": "PCIE_IMUX19_R_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN60" }, "PCIE_TOP.PCIE_IMUX8_R_0->PCIE_TOP_TRNTD8": { "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD8", - "is_directional": "1", "src_wire": "PCIE_IMUX8_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_DBGVECA15->PCIE_LOGIC_OUTS_B23_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_2", "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA15", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD8" }, - "PCIE_TOP.PCIE_IMUX7_R_1->PCIE_TOP_MIMRXRDATA51": { + "PCIE_TOP.PCIE_IMUX6_L_3->PCIE_TOP_CFGERRTLPCPLHEADER40": { "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA51", + "src_wire": "PCIE_IMUX6_L_3", "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER40" }, - "PCIE_TOP.PCIE_IMUX5_R_0->PCIE_TOP_MIMRXRDATA53": { + "PCIE_TOP.PCIE_IMUX32_R_1->PCIE_TOP_PIPERX4DATA3": { "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA53", + "src_wire": "PCIE_IMUX32_R_1", "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA3" }, - "PCIE_TOP.PCIE_IMUX7_R_3->PCIE_TOP_MIMRXRDATA43": { + "PCIE_TOP.PCIE_TOP_MIMRXRADDR11->PCIE_LOGIC_OUTS_B10_R_0": { "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA43", + "src_wire": "PCIE_TOP_MIMRXRADDR11", "is_directional": "1", - "src_wire": "PCIE_IMUX7_R_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX37_L_1->PCIE_TOP_PIPERX0DATA0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0DATA0", - "is_directional": "1", - "src_wire": "PCIE_IMUX37_L_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX8_R_2->PCIE_TOP_TRNTD16": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTD16", - "is_directional": "1", - "src_wire": "PCIE_IMUX8_R_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_0" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA42->PCIE_LOGIC_OUTS_B6_L_2": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B6_L_2", - "is_directional": "1", "src_wire": "PCIE_TOP_TRNRDLLPDATA42", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX33_R_0->PCIE_TOP_PIPERX4CHANISALIGNED": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4CHANISALIGNED", "is_directional": "1", - "src_wire": "PCIE_IMUX33_R_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_2" }, - "PCIE_TOP.PCIE_TOP_DBGVECA4->PCIE_LOGIC_OUTS_B21_L_3": { + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA56->PCIE_LOGIC_OUTS_B5_R_3": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B21_L_3", + "src_wire": "PCIE_TOP_TRNRDLLPDATA56", "is_directional": "1", - "src_wire": "PCIE_TOP_DBGVECA4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_3" }, - "PCIE_TOP.PCIE_TOP_TRNRD76->PCIE_LOGIC_OUTS_B1_L_4": { + "PCIE_TOP.PCIE_IMUX6_R_0->PCIE_TOP_MIMRXRDATA54": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_L_4", + "src_wire": "PCIE_IMUX6_R_0", "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD76", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA54" }, - "PCIE_TOP.PCIE_IMUX22_R_3->PCIE_TOP_CFGERRAERHEADERLOG4": { + "PCIE_TOP.PCIE_TOP_TRNRD96->PCIE_LOGIC_OUTS_B4_R_0": { "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG4", + "src_wire": "PCIE_TOP_TRNRD96", "is_directional": "1", - "src_wire": "PCIE_IMUX22_R_3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_0" }, - "PCIE_TOP.PCIE_IMUX10_L_4->PCIE_TOP_CFGDEVID11": { + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA44->PCIE_LOGIC_OUTS_B4_L_3": { "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID11", + "src_wire": "PCIE_TOP_TRNRDLLPDATA44", "is_directional": "1", - "src_wire": "PCIE_IMUX10_L_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_3" }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA0->PCIE_LOGIC_OUTS_B11_R_0": { + "PCIE_TOP.PCIE_IMUX0_L_4->PCIE_TOP_LL2SENDENTERL23": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B11_R_0", + "src_wire": "PCIE_IMUX0_L_4", "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SENDENTERL23" }, - "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2LTREN->PCIE_LOGIC_OUTS_B23_R_4": { + "PCIE_TOP.PCIE_IMUX1_R_2->PCIE_TOP_MIMRXRDATA29": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_R_4", + "src_wire": "PCIE_IMUX1_R_2", "is_directional": "1", - "src_wire": "PCIE_TOP_CFGDEVCONTROL2LTREN", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA29" }, - "PCIE_TOP.PCIE_TOP_PL2SUSPENDOK->PCIE_LOGIC_OUTS_B7_R_0": { + "PCIE_TOP.PCIE_IMUX10_L_3->PCIE_TOP_CFGDEVID7": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B7_R_0", + "src_wire": "PCIE_IMUX10_L_3", "is_directional": "1", - "src_wire": "PCIE_TOP_PL2SUSPENDOK", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID7" }, - "PCIE_TOP.PCIE_IMUX11_L_2->PCIE_TOP_CFGDEVID4": { + "PCIE_TOP.PCIE_TOP_PIPETXMARGIN0->PCIE_LOGIC_OUTS_B18_L_0": { "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGDEVID4", + "src_wire": "PCIE_TOP_PIPETXMARGIN0", "is_directional": "1", - "src_wire": "PCIE_IMUX11_L_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_0" }, - "PCIE_TOP.PCIE_IMUX5_R_1->PCIE_TOP_MIMRXRDATA49": { + "PCIE_TOP.PCIE_TOP_DRPDO14->PCIE_LOGIC_OUTS_B23_L_1": { "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA49", + "src_wire": "PCIE_TOP_DRPDO14", "is_directional": "1", - "src_wire": "PCIE_IMUX5_R_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_1" }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA10->PCIE_LOGIC_OUTS_B19_R_1": { + "PCIE_TOP.PCIE_IMUX19_R_4->PCIE_TOP_CFGINTERRUPTN": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_1", + "src_wire": "PCIE_IMUX19_R_4", "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA10", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGINTERRUPTN" }, - "PCIE_TOP.PCIE_IMUX2_L_0->PCIE_TOP_TRNTDLLPDATA21": { + "PCIE_TOP.PCIE_IMUX14_L_2->PCIE_TOP_DRPDI6": { "can_invert": "0", - "dst_wire": "PCIE_TOP_TRNTDLLPDATA21", + "src_wire": "PCIE_IMUX14_L_2", "is_directional": "1", - "src_wire": "PCIE_IMUX2_L_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA5->PCIE_LOGIC_OUTS_B22_R_3": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B22_R_3", - "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA5", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA61->PCIE_LOGIC_OUTS_B8_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B8_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRDLLPDATA61", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX7_L_3->PCIE_TOP_CFGERRTLPCPLHEADER41": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER41", - "is_directional": "1", - "src_wire": "PCIE_IMUX7_L_3", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX16_R_1->PCIE_TOP_PIPERX4CHARISK0": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4CHARISK0", - "is_directional": "1", - "src_wire": "PCIE_IMUX16_R_1", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_TRNRD65->PCIE_LOGIC_OUTS_B2_L_1": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B2_L_1", - "is_directional": "1", - "src_wire": "PCIE_TOP_TRNRD65", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_CFGMGMTDO19->PCIE_LOGIC_OUTS_B19_R_2": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B19_R_2", - "is_directional": "1", - "src_wire": "PCIE_TOP_CFGMGMTDO19", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_PLDBGVEC8->PCIE_LOGIC_OUTS_B23_L_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B23_L_0", - "is_directional": "1", - "src_wire": "PCIE_TOP_PLDBGVEC8", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX2_R_4->PCIE_TOP_MIMRXRDATA38": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA38", - "is_directional": "1", - "src_wire": "PCIE_IMUX2_R_4", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX3_R_4->PCIE_TOP_MIMRXRDATA39": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA39", - "is_directional": "1", - "src_wire": "PCIE_IMUX3_R_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI6" }, "PCIE_TOP.PCIE_TOP_LL2TFCINIT1SEQ->PCIE_LOGIC_OUTS_B16_R_1": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B16_R_1", - "is_directional": "1", "src_wire": "PCIE_TOP_LL2TFCINIT1SEQ", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_IMUX1_R_4->PCIE_TOP_MIMRXRDATA37": { - "can_invert": "0", - "dst_wire": "PCIE_TOP_MIMRXRDATA37", "is_directional": "1", - "src_wire": "PCIE_IMUX1_R_4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_1" }, - "PCIE_TOP.PCIE_IMUX36_L_0->PCIE_TOP_PIPERX0VALID": { + "PCIE_TOP.PCIE_IMUX14_L_1->PCIE_TOP_DRPDI2": { "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX0VALID", + "src_wire": "PCIE_IMUX14_L_1", "is_directional": "1", - "src_wire": "PCIE_IMUX36_L_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI2" }, - "PCIE_TOP.PCIE_TOP_MIMRXWDATA26->PCIE_LOGIC_OUTS_B13_R_1": { + "PCIE_TOP.PCIE_IMUX14_R_1->PCIE_TOP_TRNTD38": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B13_R_1", + "src_wire": "PCIE_IMUX14_R_1", "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWDATA26", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD38" }, - "PCIE_TOP.PCIE_IMUX6_L_2->PCIE_TOP_CFGERRTLPCPLHEADER36": { + "PCIE_TOP.PCIE_IMUX0_R_1->PCIE_TOP_MIMRXRDATA24": { "can_invert": "0", - "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER36", + "src_wire": "PCIE_IMUX0_R_1", "is_directional": "1", - "src_wire": "PCIE_IMUX6_L_2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA24" }, - "PCIE_TOP.PCIE_TOP_LL2TFCINIT2SEQ->PCIE_LOGIC_OUTS_B20_R_1": { + "PCIE_TOP.PCIE_IMUX0_R_3->PCIE_TOP_MIMRXRDATA32": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B20_R_1", + "src_wire": "PCIE_IMUX0_R_3", "is_directional": "1", - "src_wire": "PCIE_TOP_LL2TFCINIT2SEQ", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA32" + }, + "PCIE_TOP.PCIE_IMUX12_L_4->PCIE_TOP_DRPDI12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI12" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO16->PCIE_LOGIC_OUTS_B21_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_1" + }, + "PCIE_TOP.PCIE_IMUX13_L_1->PCIE_TOP_DRPDI1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI1" + }, + "PCIE_TOP.PCIE_TOP_TRNRD92->PCIE_LOGIC_OUTS_B3_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD92", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_1" + }, + "PCIE_TOP.PCIE_TOP_MIMRXREN->PCIE_LOGIC_OUTS_B12_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_1" + }, + "PCIE_TOP.PCIE_IMUX16_R_3->PCIE_TOP_LL2SUSPENDNOW": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SUSPENDNOW" + }, + "PCIE_TOP.PCIE_TOP_TRNRD61->PCIE_LOGIC_OUTS_B2_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA7->PCIE_LOGIC_OUTS_B20_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_4" + }, + "PCIE_TOP.PCIE_IMUX37_R_0->PCIE_TOP_PIPERX4PHYSTATUS": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4PHYSTATUS" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA3->PCIE_LOGIC_OUTS_B15_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_2" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA55->PCIE_LOGIC_OUTS_B12_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA55", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_4" + }, + "PCIE_TOP.PCIE_IMUX1_R_0->PCIE_TOP_MIMRXRDATA21": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA21" + }, + "PCIE_TOP.PCIE_IMUX20_R_3->PCIE_TOP_CFGERRAERHEADERLOG2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG2" + }, + "PCIE_TOP.PCIE_TOP_TRNRD88->PCIE_LOGIC_OUTS_B3_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD88", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_2" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA12->PCIE_LOGIC_OUTS_B2_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_1" + }, + "PCIE_TOP.PCIE_IMUX4_L_0->PCIE_TOP_CFGERRTLPCPLHEADER26": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER26" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA15->PCIE_LOGIC_OUTS_B23_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_2" + }, + "PCIE_TOP.PCIE_IMUX13_L_0->PCIE_TOP_DRPADDR8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPADDR8" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWADDR2->PCIE_LOGIC_OUTS_B0_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWADDR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_2" + }, + "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE1->PCIE_LOGIC_OUTS_B9_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPCIELINKSTATE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_0" + }, + "PCIE_TOP.PCIE_IMUX2_R_2->PCIE_TOP_MIMRXRDATA30": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA30" + }, + "PCIE_TOP.PCIE_IMUX3_L_0->PCIE_TOP_TRNTDLLPDATA22": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA22" + }, + "PCIE_TOP.PCIE_IMUX13_R_1->PCIE_TOP_TRNTD37": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD37" + }, + "PCIE_TOP.PCIE_IMUX17_R_4->PCIE_TOP_CFGERRTLPCPLHEADER46": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER46" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED->PCIE_LOGIC_OUTS_B21_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_0" + }, + "PCIE_TOP.PCIE_TOP_PIPETXMARGIN2->PCIE_LOGIC_OUTS_B6_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_PIPETXMARGIN2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA33->PCIE_LOGIC_OUTS_B22_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_2" + }, + "PCIE_TOP.PCIE_IMUX3_R_1->PCIE_TOP_MIMRXRDATA27": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA27" + }, + "PCIE_TOP.PCIE_TOP_DRPDO15->PCIE_LOGIC_OUTS_B20_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_2" + }, + "PCIE_TOP.PCIE_IMUX3_R_3->PCIE_TOP_MIMRXRDATA35": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA35" + }, + "PCIE_TOP.PCIE_TOP_DRPDO6->PCIE_LOGIC_OUTS_B19_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_4" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA9->PCIE_LOGIC_OUTS_B22_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_4" + }, + "PCIE_TOP.PCIE_IMUX5_R_2->PCIE_TOP_MIMRXRDATA45": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA45" + }, + "PCIE_TOP.PCIE_TOP_TRNRD65->PCIE_LOGIC_OUTS_B2_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD65", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_1" + }, + "PCIE_TOP.PCIE_IMUX0_L_2->PCIE_TOP_TRNTDLLPDATA27": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA27" + }, + "PCIE_TOP.PCIE_IMUX0_L_0->PCIE_TOP_TRNTDLLPDATA19": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA19" + }, + "PCIE_TOP.PCIE_IMUX10_R_2->PCIE_TOP_TRNTD18": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD18" }, "PCIE_TOP.PCIE_IMUX15_L_1->PCIE_TOP_DRPDI3": { "can_invert": "0", - "dst_wire": "PCIE_TOP_DRPDI3", - "is_directional": "1", "src_wire": "PCIE_IMUX15_L_1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI3" + }, + "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL1N->PCIE_LOGIC_OUTS_B12_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPMRCVENTERL1N", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA48->PCIE_LOGIC_OUTS_B4_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA48", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_4" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWADDR1->PCIE_LOGIC_OUTS_B15_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWADDR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_1" + }, + "PCIE_TOP.PCIE_IMUX1_L_4->PCIE_TOP_LL2SENDASREQL1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SENDASREQL1" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA14->PCIE_LOGIC_OUTS_B20_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA14", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_2" + }, + "PCIE_TOP.PCIE_TOP_TRNRD72->PCIE_LOGIC_OUTS_B1_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD72", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_3" + }, + "PCIE_TOP.PCIE_IMUX12_R_1->PCIE_TOP_TRNTD36": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD36" + }, + "PCIE_TOP.PCIE_TOP_CFGPMRCVREQACKN->PCIE_LOGIC_OUTS_B9_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPMRCVREQACKN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_1" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA20->PCIE_LOGIC_OUTS_B20_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_0" + }, + "PCIE_TOP.PCIE_IMUX8_L_4->PCIE_TOP_CFGDEVID9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID9" + }, + "PCIE_TOP.PCIE_IMUX15_L_3->PCIE_TOP_DRPDI11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI11" + }, + "PCIE_TOP.PCIE_IMUX11_R_4->PCIE_TOP_PL2DIRECTEDLSTATE4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE4" + }, + "PCIE_TOP.PCIE_IMUX2_R_0->PCIE_TOP_MIMRXRDATA22": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA22" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR10->PCIE_LOGIC_OUTS_B3_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXRADDR10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA51->PCIE_LOGIC_OUTS_B7_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_4" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO24->PCIE_LOGIC_OUTS_B13_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_4" + }, + "PCIE_TOP.PCIE_TOP_TRNRD94->PCIE_LOGIC_OUTS_B6_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD94", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_1" + }, + "PCIE_TOP.PCIE_IMUX9_R_0->PCIE_TOP_TRNTD9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD9" + }, + "PCIE_TOP.PCIE_TOP_TRNRD74->PCIE_LOGIC_OUTS_B3_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD74", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_3" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA4->PCIE_LOGIC_OUTS_B21_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_3" + }, + "PCIE_TOP.PCIE_IMUX13_R_4->PCIE_TOP_CFGERRAERHEADERLOG6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG6" + }, + "PCIE_TOP.PCIE_TOP_TRNRD71->PCIE_LOGIC_OUTS_B0_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD71", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_3" + }, + "PCIE_TOP.PCIE_TOP_TRNRD73->PCIE_LOGIC_OUTS_B2_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD73", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO17->PCIE_LOGIC_OUTS_B16_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_2" + }, + "PCIE_TOP.PCIE_IMUX13_L_4->PCIE_TOP_DRPDI13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI13" + }, + "PCIE_TOP.PCIE_TOP_TRNRD85->PCIE_LOGIC_OUTS_B2_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD85", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_3" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA58->PCIE_LOGIC_OUTS_B7_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA58", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_3" + }, + "PCIE_TOP.PCIE_IMUX10_L_0->PCIE_TOP_CFGDSN59": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN59" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA21->PCIE_LOGIC_OUTS_B21_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA11->PCIE_LOGIC_OUTS_B18_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_4" + }, + "PCIE_TOP.PCIE_IMUX3_R_4->PCIE_TOP_MIMRXRDATA39": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA39" + }, + "PCIE_TOP.PCIE_IMUX1_L_1->PCIE_TOP_TRNTDLLPDATA24": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA24" + }, + "PCIE_TOP.PCIE_IMUX5_R_1->PCIE_TOP_MIMRXRDATA49": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA49" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA41->PCIE_LOGIC_OUTS_B5_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA41", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_2" + }, + "PCIE_TOP.PCIE_TOP_PL2RECOVERY->PCIE_LOGIC_OUTS_B12_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_PL2RECOVERY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_0" + }, + "PCIE_TOP.PCIE_IMUX2_R_3->PCIE_TOP_MIMRXRDATA34": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA34" + }, + "PCIE_TOP.PCIE_IMUX8_L_1->PCIE_TOP_CFGDSN61": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN61" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO25->PCIE_LOGIC_OUTS_B14_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_4" + }, + "PCIE_TOP.PCIE_IMUX5_L_4->PCIE_TOP_CFGERRTLPCPLHEADER43": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER43" + }, + "PCIE_TOP.PCIE_IMUX17_R_2->PCIE_TOP_CFGERRLOCKEDN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRLOCKEDN" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLASPMCONTROL1->PCIE_LOGIC_OUTS_B13_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_0" + }, + "PCIE_TOP.PCIE_IMUX11_R_2->PCIE_TOP_TRNTD19": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD19" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA20->PCIE_LOGIC_OUTS_B0_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR0->PCIE_LOGIC_OUTS_B13_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXRADDR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_2" + }, + "PCIE_TOP.PCIE_IMUX32_L_1->PCIE_TOP_PIPERX0DATA3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX32_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA3" + }, + "PCIE_TOP.PCIE_IMUX14_R_4->PCIE_TOP_CFGERRAERHEADERLOG7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG7" + }, + "PCIE_TOP.PCIE_IMUX11_L_3->PCIE_TOP_CFGDEVID8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID8" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA0->PCIE_LOGIC_OUTS_B21_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_2" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP3->PCIE_LOGIC_OUTS_B16_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGVCTCVCMAP3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_2" + }, + "PCIE_TOP.PCIE_TOP_TRNRD59->PCIE_LOGIC_OUTS_B0_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD59", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_0" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR5->PCIE_LOGIC_OUTS_B9_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_4" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC->PCIE_LOGIC_OUTS_B13_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_1" + }, + "PCIE_TOP.PCIE_IMUX3_L_3->PCIE_TOP_LL2SENDENTERL1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SENDENTERL1" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA17->PCIE_LOGIC_OUTS_B9_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_2" + }, + "PCIE_TOP.PCIE_IMUX9_R_3->PCIE_TOP_TRNTD21": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD21" + }, + "PCIE_TOP.PCIE_TOP_TRNRD79->PCIE_LOGIC_OUTS_B0_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD79", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_4" + }, + "PCIE_TOP.PCIE_IMUX5_L_0->PCIE_TOP_CFGERRTLPCPLHEADER27": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER27" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR1->PCIE_LOGIC_OUTS_B11_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXRADDR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_1" + }, + "PCIE_TOP.PCIE_IMUX10_R_3->PCIE_TOP_TRNTD22": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD22" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2->PCIE_LOGIC_OUTS_B12_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_3" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO29->PCIE_LOGIC_OUTS_B17_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_3" + }, + "PCIE_TOP.PCIE_IMUX11_R_0->PCIE_TOP_TRNTD11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD11" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA5->PCIE_LOGIC_OUTS_B22_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_3" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO19->PCIE_LOGIC_OUTS_B19_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_2" + }, + "PCIE_TOP.PCIE_TOP_TRNRD95->PCIE_LOGIC_OUTS_B2_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD95", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_0" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP0->PCIE_LOGIC_OUTS_B17_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGVCTCVCMAP0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_1" + }, + "PCIE_TOP.PCIE_IMUX12_L_2->PCIE_TOP_DRPDI4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI4" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA17->PCIE_LOGIC_OUTS_B23_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA17", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_1" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B13_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_2" + }, + "PCIE_TOP.PCIE_IMUX33_R_0->PCIE_TOP_PIPERX4CHANISALIGNED": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4CHANISALIGNED" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA61->PCIE_LOGIC_OUTS_B8_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA61", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_2" + }, + "PCIE_TOP.PCIE_IMUX2_L_1->PCIE_TOP_TRNTDLLPDATA25": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA25" + }, + "PCIE_TOP.PCIE_TOP_CFGCOMMANDBUSMASTERENABLE->PCIE_LOGIC_OUTS_B20_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_4" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA47->PCIE_LOGIC_OUTS_B7_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA47", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_3" + }, + "PCIE_TOP.PCIE_TOP_DRPDO12->PCIE_LOGIC_OUTS_B21_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_1" + }, + "PCIE_TOP.PCIE_TOP_TRNRD80->PCIE_LOGIC_OUTS_B2_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD80", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_4" + }, + "PCIE_TOP.PCIE_IMUX5_R_0->PCIE_TOP_MIMRXRDATA53": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA53" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1->PCIE_LOGIC_OUTS_B15_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_2" + }, + "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE1->PCIE_LOGIC_OUTS_B11_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_1" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA9->PCIE_LOGIC_OUTS_B3_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_3" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA62->PCIE_LOGIC_OUTS_B10_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_2" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA6->PCIE_LOGIC_OUTS_B16_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_0" + }, + "PCIE_TOP.PCIE_IMUX12_R_0->PCIE_TOP_TRNTD40": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD40" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA1->PCIE_LOGIC_OUTS_B22_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_2" + }, + "PCIE_TOP.PCIE_TOP_DRPDO2->PCIE_LOGIC_OUTS_B19_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_3" + }, + "PCIE_TOP.PCIE_TOP_TRNRD60->PCIE_LOGIC_OUTS_B1_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_0" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3->PCIE_LOGIC_OUTS_B13_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_3" + }, + "PCIE_TOP.PCIE_TOP_TRNRD81->PCIE_LOGIC_OUTS_B3_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD81", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_R_4" + }, + "PCIE_TOP.PCIE_IMUX12_L_0->PCIE_TOP_DRPADDR7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPADDR7" + }, + "PCIE_TOP.PCIE_TOP_TRNRD68->PCIE_LOGIC_OUTS_B1_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD68", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_2" + }, + "PCIE_TOP.PCIE_TOP_TRNRD89->PCIE_LOGIC_OUTS_B4_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD89", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_2" + }, + "PCIE_TOP.PCIE_TOP_DRPDO0->PCIE_LOGIC_OUTS_B17_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_3" + }, + "PCIE_TOP.PCIE_IMUX12_R_3->PCIE_TOP_TRNTD28": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD28" + }, + "PCIE_TOP.PCIE_IMUX21_R_4->PCIE_TOP_CFGDEVID13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX21_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID13" + }, + "PCIE_TOP.PCIE_IMUX34_R_0->PCIE_TOP_PIPERX4DATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA7" + }, + "PCIE_TOP.PCIE_IMUX22_R_3->PCIE_TOP_CFGERRAERHEADERLOG4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX22_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG4" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR4->PCIE_LOGIC_OUTS_B5_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXRADDR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_2" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR0->PCIE_LOGIC_OUTS_B8_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_3" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA21->PCIE_LOGIC_OUTS_B19_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_3" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA26->PCIE_LOGIC_OUTS_B13_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_1" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN->PCIE_LOGIC_OUTS_B12_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_4" + }, + "PCIE_TOP.PCIE_IMUX13_R_3->PCIE_TOP_TRNTD29": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD29" + }, + "PCIE_TOP.PCIE_IMUX10_L_1->PCIE_TOP_CFGDSN63": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN63" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA13->PCIE_LOGIC_OUTS_B21_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_3" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA2->PCIE_LOGIC_OUTS_B18_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_0" + }, + "PCIE_TOP.PCIE_IMUX8_L_3->PCIE_TOP_CFGDEVID5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID5" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR4->PCIE_LOGIC_OUTS_B8_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_4" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK->PCIE_LOGIC_OUTS_B13_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_L_4" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK->PCIE_LOGIC_OUTS_B12_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_1" + }, + "PCIE_TOP.PCIE_IMUX5_R_4->PCIE_TOP_TRNTD25": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD25" + }, + "PCIE_TOP.PCIE_IMUX15_L_4->PCIE_TOP_DRPDI15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI15" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA40->PCIE_LOGIC_OUTS_B4_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA40", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_2" + }, + "PCIE_TOP.PCIE_IMUX6_L_2->PCIE_TOP_CFGERRTLPCPLHEADER36": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER36" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP1->PCIE_LOGIC_OUTS_B18_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGVCTCVCMAP1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_1" + }, + "PCIE_TOP.PCIE_IMUX36_L_1->PCIE_TOP_PIPERX0DATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA1" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS->PCIE_LOGIC_OUTS_B14_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_3" + }, + "PCIE_TOP.PCIE_TOP_TRNRD82->PCIE_LOGIC_OUTS_B4_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD82", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_4" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP5->PCIE_LOGIC_OUTS_B18_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGVCTCVCMAP5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_2" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLLINKDISABLE->PCIE_LOGIC_OUTS_B15_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGLINKCONTROLLINKDISABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_0" + }, + "PCIE_TOP.PCIE_IMUX6_R_1->PCIE_TOP_MIMRXRDATA50": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA50" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA29->PCIE_LOGIC_OUTS_B8_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA29", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_4" + }, + "PCIE_TOP.PCIE_IMUX18_R_3->PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK": { + "can_invert": "0", + "src_wire": "PCIE_IMUX18_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK" + }, + "PCIE_TOP.PCIE_TOP_DRPDO1->PCIE_LOGIC_OUTS_B18_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_3" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA5->PCIE_LOGIC_OUTS_B22_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_3" + }, + "PCIE_TOP.PCIE_IMUX9_L_1->PCIE_TOP_CFGDSN62": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN62" + }, + "PCIE_TOP.PCIE_TOP_TRNRD90->PCIE_LOGIC_OUTS_B6_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_2" + }, + "PCIE_TOP.PCIE_IMUX36_R_1->PCIE_TOP_PIPERX4DATA1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA1" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA15->PCIE_LOGIC_OUTS_B10_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA15", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_4" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA23->PCIE_LOGIC_OUTS_B14_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_3" + }, + "PCIE_TOP.PCIE_IMUX0_R_0->PCIE_TOP_MIMRXRDATA20": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA20" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA38->PCIE_LOGIC_OUTS_B6_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA38", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_1" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0->PCIE_LOGIC_OUTS_B14_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_2" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO21->PCIE_LOGIC_OUTS_B12_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_3" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO28->PCIE_LOGIC_OUTS_B16_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_3" + }, + "PCIE_TOP.PCIE_IMUX13_R_2->PCIE_TOP_TRNTD33": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD33" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B19_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD76->PCIE_LOGIC_OUTS_B1_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD76", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_4" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA30->PCIE_LOGIC_OUTS_B18_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_2" + }, + "PCIE_TOP.PCIE_TOP_TRNRD84->PCIE_LOGIC_OUTS_B1_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD84", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_3" + }, + "PCIE_TOP.PCIE_IMUX2_R_4->PCIE_TOP_MIMRXRDATA38": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA38" + }, + "PCIE_TOP.PCIE_TOP_DRPDO3->PCIE_LOGIC_OUTS_B16_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_4" + }, + "PCIE_TOP.PCIE_IMUX3_L_4->PCIE_TOP_PL2DIRECTEDLSTATE0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE0" + }, + "PCIE_TOP.PCIE_IMUX7_L_3->PCIE_TOP_CFGERRTLPCPLHEADER41": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER41" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA27->PCIE_LOGIC_OUTS_B19_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_4" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA6->PCIE_LOGIC_OUTS_B23_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_3" + }, + "PCIE_TOP.PCIE_IMUX8_R_2->PCIE_TOP_TRNTD16": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD16" + }, + "PCIE_TOP.PCIE_IMUX23_R_3->PCIE_TOP_CFGERRAERHEADERLOG5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX23_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG5" + }, + "PCIE_TOP.PCIE_IMUX36_L_0->PCIE_TOP_PIPERX0VALID": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0VALID" + }, + "PCIE_TOP.PCIE_IMUX2_L_0->PCIE_TOP_TRNTDLLPDATA21": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA21" + }, + "PCIE_TOP.PCIE_IMUX9_L_3->PCIE_TOP_CFGDEVID6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID6" + }, + "PCIE_TOP.PCIE_IMUX37_L_1->PCIE_TOP_PIPERX0DATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA0" + }, + "PCIE_TOP.PCIE_IMUX11_R_3->PCIE_TOP_TRNTD23": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD23" + }, + "PCIE_TOP.PCIE_IMUX5_L_3->PCIE_TOP_CFGERRTLPCPLHEADER39": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER39" + }, + "PCIE_TOP.PCIE_IMUX10_R_4->PCIE_TOP_PL2DIRECTEDLSTATE3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE3" + }, + "PCIE_TOP.PCIE_IMUX12_L_3->PCIE_TOP_DRPDI8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI8" + }, + "PCIE_TOP.PCIE_IMUX12_L_1->PCIE_TOP_DRPDI0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI0" + }, + "PCIE_TOP.PCIE_IMUX1_R_4->PCIE_TOP_MIMRXRDATA37": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA37" + }, + "PCIE_TOP.PCIE_IMUX3_L_1->PCIE_TOP_TRNTDLLPDATA26": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA26" + }, + "PCIE_TOP.PCIE_IMUX15_R_3->PCIE_TOP_TRNTD31": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD31" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR6->PCIE_LOGIC_OUTS_B10_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_4" + }, + "PCIE_TOP.PCIE_IMUX7_R_2->PCIE_TOP_MIMRXRDATA47": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA47" + }, + "PCIE_TOP.PCIE_IMUX6_R_2->PCIE_TOP_MIMRXRDATA46": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA46" + }, + "PCIE_TOP.PCIE_TOP_DRPDO4->PCIE_LOGIC_OUTS_B17_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_4" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA22->PCIE_LOGIC_OUTS_B15_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_0" + }, + "PCIE_TOP.PCIE_IMUX17_R_3->PCIE_TOP_TL2PPMSUSPENDREQ": { + "can_invert": "0", + "src_wire": "PCIE_IMUX17_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TL2PPMSUSPENDREQ" + }, + "PCIE_TOP.PCIE_IMUX2_L_3->PCIE_TOP_LL2TLPRCV": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2TLPRCV" + }, + "PCIE_TOP.PCIE_IMUX16_R_1->PCIE_TOP_PIPERX4CHARISK0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4CHARISK0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA13->PCIE_LOGIC_OUTS_B9_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_4" + }, + "PCIE_TOP.PCIE_TOP_CFGPMCSRPMESTATUS->PCIE_LOGIC_OUTS_B9_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPMCSRPMESTATUS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_2" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR2->PCIE_LOGIC_OUTS_B10_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_3" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLRCB->PCIE_LOGIC_OUTS_B14_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGLINKCONTROLRCB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_0" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP2->PCIE_LOGIC_OUTS_B19_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGVCTCVCMAP2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_1" + }, + "PCIE_TOP.PCIE_IMUX5_R_3->PCIE_TOP_MIMRXRDATA41": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA41" + }, + "PCIE_TOP.PCIE_IMUX1_R_3->PCIE_TOP_MIMRXRDATA33": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA33" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO22->PCIE_LOGIC_OUTS_B13_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO22", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_3" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPSRCRDY1->PCIE_LOGIC_OUTS_B14_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPSRCRDY1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_1" + }, + "PCIE_TOP.PCIE_IMUX13_R_0->PCIE_TOP_TRNTD41": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD41" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO23->PCIE_LOGIC_OUTS_B15_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO23", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_3" + }, + "PCIE_TOP.PCIE_IMUX34_L_0->PCIE_TOP_PIPERX0DATA7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX34_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA7" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOREQEN->PCIE_LOGIC_OUTS_B14_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOREQEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_4" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA31->PCIE_LOGIC_OUTS_B21_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA31", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_2" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR3->PCIE_LOGIC_OUTS_B11_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_3" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA34->PCIE_LOGIC_OUTS_B7_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA12->PCIE_LOGIC_OUTS_B20_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_3" + }, + "PCIE_TOP.PCIE_IMUX35_L_0->PCIE_TOP_PIPERX0DATA6": { + "can_invert": "0", + "src_wire": "PCIE_IMUX35_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA6" + }, + "PCIE_TOP.PCIE_IMUX8_R_4->PCIE_TOP_PL2DIRECTEDLSTATE1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE1" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA11->PCIE_LOGIC_OUTS_B22_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_4" + }, + "PCIE_TOP.PCIE_TOP_TRNRD75->PCIE_LOGIC_OUTS_B0_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD75", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_4" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA1->PCIE_LOGIC_OUTS_B13_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B13_R_0" + }, + "PCIE_TOP.PCIE_IMUX37_R_1->PCIE_TOP_PIPERX4DATA0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA0" + }, + "PCIE_TOP.PCIE_IMUX13_L_2->PCIE_TOP_DRPDI5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI5" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWADDR5->PCIE_LOGIC_OUTS_B9_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWADDR5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_1" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA57->PCIE_LOGIC_OUTS_B6_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA57", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_3" + }, + "PCIE_TOP.PCIE_IMUX39_L_0->PCIE_TOP_PIPERX0DATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA4" + }, + "PCIE_TOP.PCIE_IMUX8_R_1->PCIE_TOP_TRNTD12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD12" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA32->PCIE_LOGIC_OUTS_B1_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_2" + }, + "PCIE_TOP.PCIE_TOP_PIPETXMARGIN1->PCIE_LOGIC_OUTS_B16_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_PIPETXMARGIN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_0" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA18->PCIE_LOGIC_OUTS_B14_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_0" + }, + "PCIE_TOP.PCIE_IMUX9_L_0->PCIE_TOP_CFGDSN58": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN58" + }, + "PCIE_TOP.PCIE_IMUX25_R_4->PCIE_TOP_DBGMODE0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX25_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DBGMODE0" + }, + "PCIE_TOP.PCIE_IMUX13_L_3->PCIE_TOP_DRPDI9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX13_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI9" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA8->PCIE_LOGIC_OUTS_B8_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_1" + }, + "PCIE_TOP.PCIE_TOP_DRPDO5->PCIE_LOGIC_OUTS_B18_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_L_4" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA50->PCIE_LOGIC_OUTS_B6_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA50", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_4" + }, + "PCIE_TOP.PCIE_TOP_TRNRD97->PCIE_LOGIC_OUTS_B5_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD97", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA7->PCIE_LOGIC_OUTS_B23_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_3" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA49->PCIE_LOGIC_OUTS_B5_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA49", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_1" + }, + "PCIE_TOP.PCIE_IMUX14_R_2->PCIE_TOP_TRNTD34": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD34" + }, + "PCIE_TOP.PCIE_IMUX16_R_4->PCIE_TOP_CFGERRAERHEADERLOG9": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG9" + }, + "PCIE_TOP.PCIE_IMUX11_L_4->PCIE_TOP_CFGDEVID12": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID12" }, "PCIE_TOP.PCIE_IMUX35_R_0->PCIE_TOP_PIPERX4DATA6": { "can_invert": "0", - "dst_wire": "PCIE_TOP_PIPERX4DATA6", - "is_directional": "1", "src_wire": "PCIE_IMUX35_R_0", - "is_pseudo": "0" - }, - "PCIE_TOP.PCIE_TOP_MIMRXWADDR12->PCIE_LOGIC_OUTS_B1_R_0": { - "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B1_R_0", "is_directional": "1", - "src_wire": "PCIE_TOP_MIMRXWADDR12", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA6" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO26->PCIE_LOGIC_OUTS_B15_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO26", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_R_4" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA54->PCIE_LOGIC_OUTS_B7_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA54", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_4" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA36->PCIE_LOGIC_OUTS_B4_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA36", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_1" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA53->PCIE_LOGIC_OUTS_B6_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA53", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_4" + }, + "PCIE_TOP.PCIE_IMUX21_R_2->PCIE_TOP_CFGERRAERHEADERLOG11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX21_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG11" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED->PCIE_LOGIC_OUTS_B16_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_1" + }, + "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL23N->PCIE_LOGIC_OUTS_B8_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPMRCVENTERL23N", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_1" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOCPLEN->PCIE_LOGIC_OUTS_B15_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_4" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA3->PCIE_LOGIC_OUTS_B20_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_3" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA10->PCIE_LOGIC_OUTS_B19_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_1" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_0" + }, + "PCIE_TOP.PCIE_IMUX3_L_2->PCIE_TOP_TRNTDLLPDATA30": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA30" + }, + "PCIE_TOP.PCIE_IMUX38_R_0->PCIE_TOP_PIPERX4DATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA5" + }, + "PCIE_TOP.PCIE_IMUX8_R_3->PCIE_TOP_TRNTD20": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD20" + }, + "PCIE_TOP.PCIE_IMUX23_R_4->PCIE_TOP_CFGDEVID15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX23_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID15" + }, + "PCIE_TOP.PCIE_IMUX6_L_0->PCIE_TOP_CFGERRTLPCPLHEADER28": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER28" + }, + "PCIE_TOP.PCIE_IMUX10_L_2->PCIE_TOP_CFGDEVID3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID3" + }, + "PCIE_TOP.PCIE_TOP_TRNRD77->PCIE_LOGIC_OUTS_B2_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD77", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_4" + }, + "PCIE_TOP.PCIE_IMUX9_R_1->PCIE_TOP_TRNTD13": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD13" + }, + "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED->PCIE_LOGIC_OUTS_B22_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_0" + }, + "PCIE_TOP.PCIE_IMUX15_R_2->PCIE_TOP_TRNTD35": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD35" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR1->PCIE_LOGIC_OUTS_B9_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_L_3" + }, + "PCIE_TOP.PCIE_IMUX2_L_2->PCIE_TOP_TRNTDLLPDATA29": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA29" + }, + "PCIE_TOP.PCIE_IMUX7_L_1->PCIE_TOP_CFGERRTLPCPLHEADER33": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER33" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP4->PCIE_LOGIC_OUTS_B17_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGVCTCVCMAP4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_2" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA25->PCIE_LOGIC_OUTS_B10_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA25", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_3" + }, + "PCIE_TOP.PCIE_IMUX7_R_3->PCIE_TOP_MIMRXRDATA43": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA43" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS->PCIE_LOGIC_OUTS_B15_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_1" + }, + "PCIE_TOP.PCIE_TOP_TRNRD67->PCIE_LOGIC_OUTS_B0_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD67", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_2" + }, + "PCIE_TOP.PCIE_IMUX10_R_0->PCIE_TOP_TRNTD10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD10" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA19->PCIE_LOGIC_OUTS_B8_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_3" + }, + "PCIE_TOP.PCIE_IMUX4_L_2->PCIE_TOP_CFGERRTLPCPLHEADER34": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER34" + }, + "PCIE_TOP.PCIE_IMUX4_R_4->PCIE_TOP_TRNTD24": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD24" + }, + "PCIE_TOP.PCIE_TOP_DRPDO11->PCIE_LOGIC_OUTS_B20_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_L_1" + }, + "PCIE_TOP.PCIE_IMUX1_R_1->PCIE_TOP_MIMRXRDATA25": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA25" + }, + "PCIE_TOP.PCIE_IMUX14_R_3->PCIE_TOP_TRNTD30": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD30" + }, + "PCIE_TOP.PCIE_IMUX1_L_3->PCIE_TOP_TRNTDLLPSRCRDY": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPSRCRDY" + }, + "PCIE_TOP.PCIE_IMUX8_L_0->PCIE_TOP_CFGDSN57": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDSN57" + }, + "PCIE_TOP.PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE->PCIE_LOGIC_OUTS_B21_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_R_4" + }, + "PCIE_TOP.PCIE_IMUX16_L_1->PCIE_TOP_PIPERX0CHARISK0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX16_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0CHARISK0" + }, + "PCIE_TOP.PCIE_TOP_PL2SUSPENDOK->PCIE_LOGIC_OUTS_B7_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_PL2SUSPENDOK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_0" + }, + "PCIE_TOP.PCIE_IMUX37_L_0->PCIE_TOP_PIPERX0PHYSTATUS": { + "can_invert": "0", + "src_wire": "PCIE_IMUX37_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0PHYSTATUS" + }, + "PCIE_TOP.PCIE_TOP_TRNRD69->PCIE_LOGIC_OUTS_B2_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD69", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_L_2" + }, + "PCIE_TOP.PCIE_IMUX18_R_2->PCIE_TOP_CFGERRNORECOVERYN": { + "can_invert": "0", + "src_wire": "PCIE_IMUX18_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRNORECOVERYN" + }, + "PCIE_TOP.PCIE_IMUX24_R_3->PCIE_TOP_CFGERRAERHEADERLOG10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX24_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG10" + }, + "PCIE_TOP.PCIE_TOP_TRNRD98->PCIE_LOGIC_OUTS_B6_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD98", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_R_0" + }, + "PCIE_TOP.PCIE_TOP_TRNRD87->PCIE_LOGIC_OUTS_B2_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD87", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B2_R_2" + }, + "PCIE_TOP.PCIE_IMUX39_R_0->PCIE_TOP_PIPERX4DATA4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX39_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA4" + }, + "PCIE_TOP.PCIE_IMUX7_L_2->PCIE_TOP_CFGERRTLPCPLHEADER37": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER37" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR2->PCIE_LOGIC_OUTS_B12_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXRADDR2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_R_2" + }, + "PCIE_TOP.PCIE_IMUX7_R_1->PCIE_TOP_MIMRXRDATA51": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA51" + }, + "PCIE_TOP.PCIE_IMUX9_R_4->PCIE_TOP_PL2DIRECTEDLSTATE2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE2" + }, + "PCIE_TOP.PCIE_TOP_TRNRD70->PCIE_LOGIC_OUTS_B3_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD70", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_2" + }, + "PCIE_TOP.PCIE_IMUX4_L_3->PCIE_TOP_CFGERRTLPCPLHEADER38": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER38" + }, + "PCIE_TOP.PCIE_IMUX4_R_1->PCIE_TOP_MIMRXRDATA48": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA48" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO20->PCIE_LOGIC_OUTS_B11_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_3" + }, + "PCIE_TOP.PCIE_IMUX4_L_4->PCIE_TOP_CFGERRTLPCPLHEADER42": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER42" + }, + "PCIE_TOP.PCIE_IMUX19_R_2->PCIE_TOP_CFGERRAERHEADERLOG0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX19_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG0" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO18->PCIE_LOGIC_OUTS_B17_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO18", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_2" + }, + "PCIE_TOP.PCIE_IMUX6_R_4->PCIE_TOP_TRNTD26": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD26" + }, + "PCIE_TOP.PCIE_IMUX9_L_2->PCIE_TOP_CFGDEVID2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID2" + }, + "PCIE_TOP.PCIE_IMUX22_R_4->PCIE_TOP_CFGDEVID14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX22_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID14" + }, + "PCIE_TOP.PCIE_TOP_TRNRD78->PCIE_LOGIC_OUTS_B3_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD78", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4" + }, + "PCIE_TOP.PCIE_IMUX4_R_2->PCIE_TOP_MIMRXRDATA44": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA44" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA59->PCIE_LOGIC_OUTS_B9_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA59", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_3" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO27->PCIE_LOGIC_OUTS_B16_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO27", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_R_4" + }, + "PCIE_TOP.PCIE_TOP_DRPRDY->PCIE_LOGIC_OUTS_B16_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPRDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B16_L_3" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLRETRAINLINK->PCIE_LOGIC_OUTS_B17_L_0": { "can_invert": "0", - "dst_wire": "PCIE_LOGIC_OUTS_B17_L_0", - "is_directional": "1", "src_wire": "PCIE_TOP_CFGLINKCONTROLRETRAINLINK", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_L_0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA52->PCIE_LOGIC_OUTS_B5_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA52", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_R_4" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA37->PCIE_LOGIC_OUTS_B5_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA37", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_1" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWEN->PCIE_LOGIC_OUTS_B18_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_1" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA16->PCIE_LOGIC_OUTS_B22_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA16", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_1" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2LTREN->PCIE_LOGIC_OUTS_B23_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2LTREN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_R_4" + }, + "PCIE_TOP.PCIE_IMUX5_L_2->PCIE_TOP_CFGERRTLPCPLHEADER35": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER35" + }, + "PCIE_TOP.PCIE_IMUX10_R_1->PCIE_TOP_TRNTD14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD14" + }, + "PCIE_TOP.PCIE_TOP_TRNRD86->PCIE_LOGIC_OUTS_B4_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD86", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_3" + }, + "PCIE_TOP.PCIE_TOP_DRPDO13->PCIE_LOGIC_OUTS_B22_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DRPDO13", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_L_1" + }, + "PCIE_TOP.PCIE_TOP_TRNRD91->PCIE_LOGIC_OUTS_B1_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD91", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_1" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B12_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B12_L_2" + }, + "PCIE_TOP.PCIE_TOP_TRNRD64->PCIE_LOGIC_OUTS_B1_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD64", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_L_1" + }, + "PCIE_TOP.PCIE_IMUX4_R_3->PCIE_TOP_MIMRXRDATA40": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA40" + }, + "PCIE_TOP.PCIE_TOP_PLDBGVEC8->PCIE_LOGIC_OUTS_B23_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_PLDBGVEC8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_0" + }, + "PCIE_TOP.PCIE_IMUX12_R_2->PCIE_TOP_TRNTD32": { + "can_invert": "0", + "src_wire": "PCIE_IMUX12_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD32" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA19->PCIE_LOGIC_OUTS_B19_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA19", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_R_0" + }, + "PCIE_TOP.PCIE_IMUX15_R_1->PCIE_TOP_TRNTD39": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD39" + }, + "PCIE_TOP.PCIE_IMUX2_L_4->PCIE_TOP_LL2SENDPMACK": { + "can_invert": "0", + "src_wire": "PCIE_IMUX2_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_LL2SENDPMACK" + }, + "PCIE_TOP.PCIE_IMUX5_L_1->PCIE_TOP_CFGERRTLPCPLHEADER31": { + "can_invert": "0", + "src_wire": "PCIE_IMUX5_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER31" + }, + "PCIE_TOP.PCIE_IMUX9_L_4->PCIE_TOP_CFGDEVID10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID10" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA32->PCIE_LOGIC_OUTS_B4_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA32", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_L_0" + }, + "PCIE_TOP.PCIE_IMUX20_R_2->PCIE_TOP_CFGERRAERHEADERLOG1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG1" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA4->PCIE_LOGIC_OUTS_B9_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B9_R_0" + }, + "PCIE_TOP.PCIE_IMUX1_L_2->PCIE_TOP_TRNTDLLPDATA28": { + "can_invert": "0", + "src_wire": "PCIE_IMUX1_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA28" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA28->PCIE_LOGIC_OUTS_B14_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA28", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_R_2" + }, + "PCIE_TOP.PCIE_TOP_CFGPMRCVASREQL1N->PCIE_LOGIC_OUTS_B11_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPMRCVASREQL1N", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_0" + }, + "PCIE_TOP.PCIE_IMUX3_R_2->PCIE_TOP_MIMRXRDATA31": { + "can_invert": "0", + "src_wire": "PCIE_IMUX3_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA31" + }, + "PCIE_TOP.PCIE_IMUX11_L_2->PCIE_TOP_CFGDEVID4": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID4" + }, + "PCIE_TOP.PCIE_TOP_TRNTDSTRDY3->PCIE_LOGIC_OUTS_B1_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNTDSTRDY3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_4" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA51->PCIE_LOGIC_OUTS_B7_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA51", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_1" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA10->PCIE_LOGIC_OUTS_B23_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B23_L_4" + }, + "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP6->PCIE_LOGIC_OUTS_B19_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGVCTCVCMAP6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B19_L_2" + }, + "PCIE_TOP.PCIE_IMUX9_R_2->PCIE_TOP_TRNTD17": { + "can_invert": "0", + "src_wire": "PCIE_IMUX9_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD17" + }, + "PCIE_TOP.PCIE_TOP_DBGVECB10->PCIE_LOGIC_OUTS_B22_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECB10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B22_R_0" + }, + "PCIE_TOP.PCIE_IMUX10_L_4->PCIE_TOP_CFGDEVID11": { + "can_invert": "0", + "src_wire": "PCIE_IMUX10_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID11" + }, + "PCIE_TOP.PCIE_IMUX14_L_4->PCIE_TOP_DRPDI14": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI14" + }, + "PCIE_TOP.PCIE_IMUX7_L_0->PCIE_TOP_CFGERRTLPCPLHEADER29": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER29" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA35->PCIE_LOGIC_OUTS_B11_R_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_4" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR8->PCIE_LOGIC_OUTS_B17_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXRADDR8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_0" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA24->PCIE_LOGIC_OUTS_B0_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA24", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_1" + }, + "PCIE_TOP.PCIE_TOP_CFGPMCSRPMEEN->PCIE_LOGIC_OUTS_B8_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPMCSRPMEEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_2" + }, + "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN->PCIE_LOGIC_OUTS_B15_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B15_L_3" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA60->PCIE_LOGIC_OUTS_B7_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA60", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_R_2" + }, + "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONTYPE->PCIE_LOGIC_OUTS_B11_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGTRANSACTIONTYPE", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_L_2" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA0->PCIE_LOGIC_OUTS_B11_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_0" + }, + "PCIE_TOP.PCIE_IMUX7_R_0->PCIE_TOP_MIMRXRDATA55": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA55" + }, + "PCIE_TOP.PCIE_TOP_LL2TFCINIT2SEQ->PCIE_LOGIC_OUTS_B20_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_LL2TFCINIT2SEQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B20_R_1" + }, + "PCIE_TOP.PCIE_IMUX33_L_1->PCIE_TOP_PIPERX0DATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA2" + }, + "PCIE_TOP.PCIE_TOP_CFGMGMTDO30->PCIE_LOGIC_OUTS_B18_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGMGMTDO30", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B18_R_3" + }, + "PCIE_TOP.PCIE_TOP_DBGVECA8->PCIE_LOGIC_OUTS_B21_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_DBGVECA8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B21_L_4" + }, + "PCIE_TOP.PCIE_IMUX24_R_4->PCIE_TOP_CFGVENDID0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX24_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGVENDID0" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA63->PCIE_LOGIC_OUTS_B11_R_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B11_R_2" + }, + "PCIE_TOP.PCIE_IMUX33_R_1->PCIE_TOP_PIPERX4DATA2": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4DATA2" + }, + "PCIE_TOP.PCIE_IMUX6_L_4->PCIE_TOP_CFGERRTLPCPLHEADER44": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER44" + }, + "PCIE_TOP.PCIE_IMUX14_L_3->PCIE_TOP_DRPDI10": { + "can_invert": "0", + "src_wire": "PCIE_IMUX14_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI10" + }, + "PCIE_TOP.PCIE_IMUX6_R_3->PCIE_TOP_MIMRXRDATA42": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA42" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA43->PCIE_LOGIC_OUTS_B7_L_2": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA43", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_2" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA33->PCIE_LOGIC_OUTS_B5_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA33", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_0" + }, + "PCIE_TOP.PCIE_IMUX36_R_0->PCIE_TOP_PIPERX4VALID": { + "can_invert": "0", + "src_wire": "PCIE_IMUX36_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX4VALID" + }, + "PCIE_TOP.PCIE_IMUX4_R_0->PCIE_TOP_MIMRXRDATA52": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_R_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA52" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA45->PCIE_LOGIC_OUTS_B5_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA45", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_3" + }, + "PCIE_TOP.PCIE_IMUX4_L_1->PCIE_TOP_CFGERRTLPCPLHEADER30": { + "can_invert": "0", + "src_wire": "PCIE_IMUX4_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER30" + }, + "PCIE_TOP.PCIE_IMUX7_L_4->PCIE_TOP_CFGERRTLPCPLHEADER45": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_L_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER45" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA39->PCIE_LOGIC_OUTS_B7_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA39", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B7_L_1" + }, + "PCIE_TOP.PCIE_IMUX6_L_1->PCIE_TOP_CFGERRTLPCPLHEADER32": { + "can_invert": "0", + "src_wire": "PCIE_IMUX6_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER32" + }, + "PCIE_TOP.PCIE_IMUX8_L_2->PCIE_TOP_CFGDEVID1": { + "can_invert": "0", + "src_wire": "PCIE_IMUX8_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGDEVID1" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA49->PCIE_LOGIC_OUTS_B5_L_4": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA49", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B5_L_4" + }, + "PCIE_TOP.PCIE_TOP_TRNRD63->PCIE_LOGIC_OUTS_B0_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD63", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_L_1" + }, + "PCIE_TOP.PCIE_IMUX21_R_3->PCIE_TOP_CFGERRAERHEADERLOG3": { + "can_invert": "0", + "src_wire": "PCIE_IMUX21_R_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG3" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPSRCRDY0->PCIE_LOGIC_OUTS_B10_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPSRCRDY0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_R_1" + }, + "PCIE_TOP.PCIE_TOP_TRNRD83->PCIE_LOGIC_OUTS_B0_R_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD83", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B0_R_3" + }, + "PCIE_TOP.PCIE_IMUX15_R_4->PCIE_TOP_CFGERRAERHEADERLOG8": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG8" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWADDR12->PCIE_LOGIC_OUTS_B1_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWADDR12", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B1_R_0" + }, + "PCIE_TOP.PCIE_IMUX0_L_1->PCIE_TOP_TRNTDLLPDATA23": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA23" + }, + "PCIE_TOP.PCIE_IMUX20_R_4->PCIE_TOP_CFGINTERRUPTDI0": { + "can_invert": "0", + "src_wire": "PCIE_IMUX20_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_CFGINTERRUPTDI0" + }, + "PCIE_TOP.PCIE_IMUX33_L_0->PCIE_TOP_PIPERX0CHANISALIGNED": { + "can_invert": "0", + "src_wire": "PCIE_IMUX33_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0CHANISALIGNED" + }, + "PCIE_TOP.PCIE_IMUX15_L_2->PCIE_TOP_DRPDI7": { + "can_invert": "0", + "src_wire": "PCIE_IMUX15_L_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_DRPDI7" + }, + "PCIE_TOP.PCIE_TOP_TRNRD62->PCIE_LOGIC_OUTS_B3_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD62", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_0" + }, + "PCIE_TOP.PCIE_IMUX11_R_1->PCIE_TOP_TRNTD15": { + "can_invert": "0", + "src_wire": "PCIE_IMUX11_R_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD15" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA46->PCIE_LOGIC_OUTS_B6_L_3": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA46", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B6_L_3" + }, + "PCIE_TOP.PCIE_IMUX38_L_0->PCIE_TOP_PIPERX0DATA5": { + "can_invert": "0", + "src_wire": "PCIE_IMUX38_L_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_PIPERX0DATA5" + }, + "PCIE_TOP.PCIE_IMUX7_R_4->PCIE_TOP_TRNTD27": { + "can_invert": "0", + "src_wire": "PCIE_IMUX7_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTD27" + }, + "PCIE_TOP.PCIE_TOP_MIMRXRADDR9->PCIE_LOGIC_OUTS_B8_R_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXRADDR9", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_R_0" + }, + "PCIE_TOP.PCIE_IMUX0_R_4->PCIE_TOP_MIMRXRDATA36": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA36" + }, + "PCIE_TOP.PCIE_IMUX0_L_3->PCIE_TOP_TRNTDLLPDATA31": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_L_3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_TRNTDLLPDATA31" + }, + "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA35->PCIE_LOGIC_OUTS_B8_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRDLLPDATA35", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B8_L_0" + }, + "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE2->PCIE_LOGIC_OUTS_B10_L_0": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPCIELINKSTATE2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_0" + }, + "PCIE_TOP.PCIE_IMUX0_R_2->PCIE_TOP_MIMRXRDATA28": { + "can_invert": "0", + "src_wire": "PCIE_IMUX0_R_2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_TOP_MIMRXRDATA28" + }, + "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE0->PCIE_LOGIC_OUTS_B10_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B10_L_1" + }, + "PCIE_TOP.PCIE_TOP_MIMRXWDATA34->PCIE_LOGIC_OUTS_B17_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_MIMRXWDATA34", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B17_R_1" + }, + "PCIE_TOP.PCIE_TOP_TRNRD66->PCIE_LOGIC_OUTS_B3_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD66", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B3_L_1" + }, + "PCIE_TOP.PCIE_TOP_TRNRD93->PCIE_LOGIC_OUTS_B4_R_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_TRNRD93", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B4_R_1" + }, + "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCLOCKPMEN->PCIE_LOGIC_OUTS_B14_L_1": { + "can_invert": "0", + "src_wire": "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "PCIE_LOGIC_OUTS_B14_L_1" } }, - "tile_type": "PCIE_TOP" + "wires": [ + "PCIE_FAN5_L_2", + "PCIE_EE4A1_0", + "PCIE_LH2_2", + "PCIE_IMUX3_R_0", + "PCIE_LOGIC_OUTS_B3_L_4", + "PCIE_LOGIC_OUTS_B17_L_3", + "PCIE_BYP6_L_0", + "PCIE_FAN4_R_3", + "PCIE_BLOCK_OUTS_B1_R_3", + "PCIE_IMUX26_R_1", + "PCIE_FAN0_L_3", + "PCIE_IMUX2_L_3", + "PCIE_MONITOR_N_4", + "PCIE_WL1END3_1", + "PCIE_SW4A0_4", + "PCIE_IMUX1_R_1", + "PCIE_NW4A3_0", + "PCIE_TOP_PIPERX4VALID", + "PCIE_WW4END1_0", + "PCIE_TOP_TRNRD68", + "PCIE_LOGIC_OUTS_B16_L_2", + "PCIE_IMUX19_L_3", + "PCIE_TOP_CFGDEVID4", + "PCIE_NW2A2_1", + "PCIE_IMUX39_R_1", + "PCIE_LOGIC_OUTS_B20_R_1", + "PCIE_BYP4_L_4", + "PCIE_BYP3_R_4", + "PCIE_IMUX44_L_2", + "PCIE_WW4END3_4", + "PCIE_MONITOR_P_0", + "PCIE_BYP0_L_1", + "PCIE_TOP_TRNTD24", + "PCIE_IMUX7_R_4", + "PCIE_IMUX17_R_3", + "PCIE_IMUX38_L_2", + "PCIE_TOP_DBGVECA15", + "PCIE_IMUX31_R_0", + "PCIE_IMUX11_R_2", + "PCIE_IMUX21_R_1", + "PCIE_IMUX26_L_0", + "PCIE_NE2A2_2", + "PCIE_IMUX19_R_2", + "PCIE_IMUX13_L_2", + "PCIE_EL1BEG0_3", + "PCIE_EE4B0_0", + "PCIE_TOP_TRNRD66", + "PCIE_TOP_DBGVECA5", + "PCIE_SW4END2_3", + "PCIE_CTRL1_L_4", + "PCIE_TOP_TRNRD80", + "PCIE_NE4C3_4", + "PCIE_TOP_TRNRD61", + "PCIE_FAN1_L_1", + "PCIE_TOP_PIPETXMARGIN2", + "PCIE_LOGIC_OUTS_B2_L_1", + "PCIE_LH9_3", + "PCIE_CLK1_L_1", + "PCIE_SW4A0_2", + "PCIE_TOP_TRNTD15", + "PCIE_EE4A1_1", + "PCIE_IMUX24_L_0", + "PCIE_IMUX3_R_1", + "PCIE_FAN3_L_2", + "PCIE_NW4END3_2", + "PCIE_IMUX19_R_3", + "PCIE_LOGIC_OUTS_B14_R_3", + "PCIE_LOGIC_OUTS_B14_R_1", + "PCIE_EE4BEG0_1", + "PCIE_TOP_TRNTD21", + "PCIE_LOGIC_OUTS_B8_L_0", + "PCIE_EE4A0_0", + "PCIE_TOP_DRPDI13", + "PCIE_LOGIC_OUTS_B14_R_0", + "PCIE_EE2A3_0", + "PCIE_NE4BEG3_3", + "PCIE_TOP_TRNRD98", + "PCIE_EL1BEG2_3", + "PCIE_TOP_PIPETXMARGIN1", + "PCIE_IMUX40_L_2", + "PCIE_TOP_CFGDEVID8", + "PCIE_SE4BEG3_2", + "PCIE_CTRL1_R_0", + "PCIE_IMUX14_L_4", + "PCIE_IMUX27_R_3", + "PCIE_IMUX14_L_1", + "PCIE_TOP_DRPDO4", + "PCIE_WW4B0_4", + "PCIE_TOP_TRNTD18", + "PCIE_IMUX9_L_1", + "PCIE_LOGIC_OUTS_B21_R_1", + "PCIE_WW4A3_4", + "PCIE_LOGIC_OUTS_B13_L_2", + "PCIE_WW4C0_1", + "PCIE_BLOCK_OUTS_B1_L_1", + "PCIE_IMUX31_R_2", + "PCIE_IMUX13_L_3", + "PCIE_IMUX21_R_0", + "PCIE_TOP_MIMRXWADDR5", + "PCIE_IMUX21_R_4", + "PCIE_TOP_SCANMODEN", + "PCIE_FAN6_L_4", + "PCIE_TOP_TRNRD78", + "PCIE_IMUX31_L_1", + "PCIE_IMUX45_R_0", + "PCIE_TOP_CFGERRTLPCPLHEADER47", + "PCIE_IMUX18_L_4", + "PCIE_SE4C2_4", + "PCIE_NW2A3_3", + "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED", + "PCIE_IMUX23_R_0", + "PCIE_LH8_3", + "PCIE_FAN7_R_3", + "PCIE_WW4C2_2", + "PCIE_NW2A0_1", + "PCIE_IMUX33_L_1", + "PCIE_SW4A0_3", + "PCIE_LOGIC_OUTS_B6_R_3", + "PCIE_TOP_DBGVECA16", + "PCIE_LOGIC_OUTS_B0_R_3", + "PCIE_WW4C0_4", + "PCIE_IMUX27_R_0", + "PCIE_IMUX4_R_0", + "PCIE_TOP_CFGLINKCONTROLRCB", + "PCIE_IMUX16_R_3", + "PCIE_SW4END1_2", + "PCIE_EE4BEG2_4", + "PCIE_IMUX38_R_0", + "PCIE_IMUX41_L_0", + "PCIE_TOP_MIMRXRDATA50", + "PCIE_IMUX4_R_1", + "PCIE_IMUX12_R_2", + "PCIE_IMUX0_R_1", + "PCIE_LOGIC_OUTS_B8_L_3", + "PCIE_TOP_MIMRXWDATA25", + "PCIE_TOP_CFGTRANSACTIONADDR5", + "PCIE_ER1BEG3_3", + "PCIE_ER1BEG2_3", + "PCIE_SW4END3_4", + "PCIE_SW4END1_4", + "PCIE_BLOCK_OUTS_B1_R_2", + "PCIE_TOP_DRPDI11", + "PCIE_EE4C1_0", + "PCIE_BYP5_L_2", + "PCIE_TOP_TRNTD12", + "PCIE_EE4C2_0", + "PCIE_IMUX46_R_3", + "PCIE_CLK0_R_1", + "PCIE_EE2BEG0_4", + "PCIE_LOGIC_OUTS_B8_L_1", + "PCIE_FAN2_R_1", + "PCIE_IMUX33_R_2", + "PCIE_WW4C0_2", + "PCIE_TOP_TRNTD8", + "PCIE_LH11_2", + "PCIE_IMUX37_L_3", + "PCIE_TOP_CFGERRTLPCPLHEADER42", + "PCIE_IMUX33_R_1", + "PCIE_EE2BEG2_3", + "PCIE_LOGIC_OUTS_B1_L_1", + "PCIE_SW2A1_1", + "PCIE_EL1BEG0_0", + "PCIE_LOGIC_OUTS_B17_R_2", + "PCIE_NE4BEG0_3", + "PCIE_SE2A0_2", + "PCIE_IMUX14_R_4", + "PCIE_NW4A3_2", + "PCIE_LH6_4", + "PCIE_LOGIC_OUTS_B22_L_1", + "PCIE_IMUX45_L_4", + "PCIE_EE2A3_1", + "PCIE_TOP_TRNRD92", + "PCIE_BYP2_R_0", + "PCIE_LOGIC_OUTS_B19_R_1", + "PCIE_CLK1_R_2", + "PCIE_IMUX35_L_1", + "PCIE_LOGIC_OUTS_B18_R_2", + "PCIE_LOGIC_OUTS_B13_L_3", + "PCIE_IMUX9_R_2", + "PCIE_EE4B1_4", + "PCIE_TOP_CFGERRTLPCPLHEADER28", + "PCIE_LOGIC_OUTS_B6_R_1", + "PCIE_TOP_TRNTD41", + "PCIE_LOGIC_OUTS_B5_L_1", + "PCIE_LOGIC_OUTS_B13_R_2", + "PCIE_TOP_CFGLINKCONTROLRETRAINLINK", + "PCIE_IMUX25_L_3", + "PCIE_TOP_TRNTD11", + "PCIE_LOGIC_OUTS_B20_L_1", + "PCIE_IMUX12_L_4", + "PCIE_WL1END0_4", + "PCIE_WR1END0_0", + "PCIE_IMUX19_L_4", + "PCIE_TOP_TRNRD63", + "PCIE_IMUX11_L_3", + "PCIE_SE2A2_4", + "PCIE_IMUX6_R_2", + "PCIE_CTRL1_R_4", + "PCIE_IMUX5_L_2", + "PCIE_IMUX14_R_2", + "PCIE_LOGIC_OUTS_B7_L_2", + "PCIE_IMUX6_R_0", + "PCIE_WW4A0_4", + "PCIE_IMUX11_R_1", + "PCIE_TOP_TRNRD84", + "PCIE_EE4BEG1_0", + "PCIE_TOP_CFGMGMTDO18", + "PCIE_TOP_MIMRXRDATA22", + "PCIE_NE4C1_4", + "PCIE_LOGIC_OUTS_B17_L_1", + "PCIE_EE4A0_4", + "PCIE_LOGIC_OUTS_B18_R_0", + "PCIE_LH5_2", + "PCIE_TOP_MIMRXRDATA41", + "PCIE_TOP_EDTCONFIGURATION", + "PCIE_IMUX3_L_3", + "PCIE_LOGIC_OUTS_B10_L_0", + "PCIE_LH3_3", + "PCIE_IMUX26_L_3", + "PCIE_TOP_MIMRXRDATA20", + "PCIE_LOGIC_OUTS_B1_R_0", + "PCIE_IMUX13_R_0", + "PCIE_TOP_CFGERRTLPCPLHEADER27", + "PCIE_IMUX11_L_1", + "PCIE_IMUX12_L_3", + "PCIE_LH1_4", + "PCIE_IMUX45_L_1", + "PCIE_EE4BEG1_1", + "PCIE_TOP_TRNTD34", + "PCIE_TOP_TRNRD86", + "PCIE_EE4B1_3", + "PCIE_TOP_PIPERX4CHANISALIGNED", + "PCIE_LH11_4", + "PCIE_IMUX41_L_4", + "PCIE_LOGIC_OUTS_B15_L_1", + "PCIE_SE2A1_1", + "PCIE_TOP_CFGDEVID9", + "PCIE_BLOCK_OUTS_B0_L_0", + "PCIE_IMUX15_L_4", + "PCIE_WR1END0_4", + "PCIE_LOGIC_OUTS_B19_L_4", + "PCIE_IMUX7_L_4", + "PCIE_IMUX11_L_0", + "PCIE_TOP_TRNRDLLPDATA54", + "PCIE_TOP_CFGPMCSRPMESTATUS", + "PCIE_TOP_CFGPCIELINKSTATE2", + "PCIE_BYP3_L_1", + "PCIE_WL1END1_4", + "PCIE_TOP_TRNRDLLPDATA34", + "PCIE_BLOCK_OUTS_B0_L_3", + "PCIE_IMUX22_L_4", + "PCIE_FAN1_R_1", + "PCIE_IMUX1_L_3", + "PCIE_EL1BEG3_1", + "PCIE_BLOCK_OUTS_B2_L_4", + "PCIE_IMUX1_R_3", + "PCIE_TOP_DBGVECA19", + "PCIE_IMUX44_R_3", + "PCIE_TOP_TRNTDLLPDATA24", + "PCIE_TOP_TRNRDLLPDATA62", + "PCIE_LOGIC_OUTS_B10_R_4", + "PCIE_FAN5_L_0", + "PCIE_LH9_4", + "PCIE_WR1END1_3", + "PCIE_TOP_PIPERX0DATA6", + "PCIE_TOP_MIMRXRADDR4", + "PCIE_TOP_PIPERX0VALID", + "PCIE_TOP_CFGMGMTDO19", + "PCIE_NW2A1_1", + "PCIE_WW2END0_2", + "PCIE_TOP_LL2SUSPENDNOW", + "PCIE_BYP4_L_1", + "PCIE_LOGIC_OUTS_B12_R_0", + "PCIE_TOP_TRNTD23", + "PCIE_IMUX24_L_1", + "PCIE_IMUX36_L_0", + "PCIE_IMUX9_L_0", + "PCIE_TOP_CFGDSN63", + "PCIE_TOP_TRNRDLLPDATA46", + "PCIE_BYP0_R_1", + "PCIE_TOP_PIPERX0DATA3", + "PCIE_LOGIC_OUTS_B22_L_0", + "PCIE_WW4A1_1", + "PCIE_EE2BEG3_1", + "PCIE_TOP_MIMRXRDATA28", + "PCIE_TOP_CFGVCTCVCMAP4", + "PCIE_LOGIC_OUTS_B14_L_1", + "PCIE_EE2BEG2_4", + "PCIE_IMUX32_L_4", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2", + "PCIE_CTRL1_R_2", + "PCIE_BLOCK_OUTS_B0_R_1", + "PCIE_EE4B0_2", + "PCIE_TOP_PIPERX0CHARISK0", + "PCIE_LOGIC_OUTS_B4_L_4", + "PCIE_TOP_CFGERRTLPCPLHEADER37", + "PCIE_WW2A2_3", + "PCIE_IMUX2_L_0", + "PCIE_EE2BEG0_2", + "PCIE_TOP_DRPDO13", + "PCIE_IMUX44_L_1", + "PCIE_BLOCK_OUTS_B0_R_3", + "PCIE_BLOCK_OUTS_B1_R_0", + "PCIE_FAN0_R_3", + "PCIE_EL1BEG3_0", + "PCIE_TOP_MIMRXWDATA10", + "PCIE_IMUX30_R_2", + "PCIE_IMUX42_L_0", + "PCIE_IMUX14_L_3", + "PCIE_WW2A3_1", + "PCIE_TOP_TRNRDLLPDATA50", + "PCIE_IMUX42_L_3", + "PCIE_WR1END1_1", + "PCIE_FAN1_L_3", + "PCIE_EE4BEG0_4", + "PCIE_LOGIC_OUTS_B10_R_3", + "PCIE_ER1BEG2_2", + "PCIE_IMUX41_R_2", + "PCIE_IMUX10_L_4", + "PCIE_IMUX14_R_1", + "PCIE_SE4BEG2_3", + "PCIE_BYP5_L_4", + "PCIE_SW4A3_0", + "PCIE_TOP_PIPERX4DATA0", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS", + "PCIE_TOP_MIMRXRDATA44", + "PCIE_WW2A3_0", + "PCIE_FAN7_R_4", + "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED", + "PCIE_IMUX44_R_4", + "PCIE_TOP_CFGERRLOCKEDN", + "PCIE_IMUX23_R_3", + "PCIE_NW2A2_2", + "PCIE_IMUX21_L_4", + "PCIE_IMUX12_R_4", + "PCIE_LH10_0", + "PCIE_TOP_CFGDEVID13", + "PCIE_IMUX39_R_2", + "PCIE_NE4BEG1_4", + "PCIE_BYP4_R_4", + "PCIE_IMUX39_R_3", + "PCIE_EE4B0_1", + "PCIE_IMUX9_R_0", + "PCIE_IMUX37_L_1", + "PCIE_FAN5_R_3", + "PCIE_IMUX6_R_4", + "PCIE_IMUX32_R_4", + "PCIE_BLOCK_OUTS_B0_L_2", + "PCIE_LH8_1", + "PCIE_BYP0_R_3", + "PCIE_BLOCK_OUTS_B0_R_4", + "PCIE_LOGIC_OUTS_B20_L_3", + "PCIE_LH8_0", + "PCIE_LOGIC_OUTS_B22_L_2", + "PCIE_TOP_MIMRXWDATA20", + "PCIE_IMUX13_R_2", + "PCIE_BLOCK_OUTS_B1_L_3", + "PCIE_EE4B1_1", + "PCIE_TOP_MIMRXWDATA6", + "PCIE_WR1END0_1", + "PCIE_WL1END1_2", + "PCIE_EE4C2_3", + "PCIE_FAN3_R_3", + "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN", + "PCIE_NE4BEG3_4", + "PCIE_SE4C1_1", + "PCIE_IMUX2_L_1", + "PCIE_TOP_MIMRXWDATA34", + "PCIE_NW4END3_4", + "PCIE_CLK1_R_3", + "PCIE_NE2A1_3", + "PCIE_IMUX33_L_3", + "PCIE_IMUX25_R_3", + "PCIE_BYP0_R_0", + "PCIE_TOP_CFGPMRCVENTERL1N", + "PCIE_IMUX43_R_3", + "PCIE_LOGIC_OUTS_B7_R_1", + "PCIE_TOP_MIMRXWDATA11", + "PCIE_EE4B2_4", + "PCIE_IMUX9_R_1", + "PCIE_FAN5_L_4", + "PCIE_ER1BEG0_0", + "PCIE_NE2A0_0", + "PCIE_LOGIC_OUTS_B8_R_2", + "PCIE_TOP_MIMRXRDATA40", + "PCIE_NW2A2_3", + "PCIE_IMUX42_R_4", + "PCIE_WL1END2_4", + "PCIE_IMUX10_R_1", + "PCIE_LOGIC_OUTS_B3_R_0", + "PCIE_TOP_MIMRXRDATA38", + "PCIE_IMUX37_R_4", + "PCIE_NW4A2_3", + "PCIE_TOP_TRNRDLLPDATA60", + "PCIE_LOGIC_OUTS_B4_L_0", + "PCIE_NW2A3_4", + "PCIE_LOGIC_OUTS_B2_L_2", + "PCIE_EE4C3_4", + "PCIE_IMUX14_R_3", + "PCIE_FAN7_L_3", + "PCIE_TOP_CFGERRTLPCPLHEADER33", + "PCIE_EE2BEG0_0", + "PCIE_EE4C0_2", + "PCIE_LOGIC_OUTS_B7_L_1", + "PCIE_WW2A1_0", + "PCIE_WW2A2_4", + "PCIE_LOGIC_OUTS_B17_R_1", + "PCIE_IMUX34_R_4", + "PCIE_SW2A3_1", + "PCIE_CTRL1_R_1", + "PCIE_LOGIC_OUTS_B6_R_0", + "PCIE_IMUX16_L_1", + "PCIE_SW4END2_1", + "PCIE_NE4BEG0_0", + "PCIE_TOP_DRPDO11", + "PCIE_SW4END2_2", + "PCIE_LH4_0", + "PCIE_SE4C3_1", + "PCIE_SW2A2_4", + "PCIE_TOP_CFGDSN58", + "PCIE_FAN4_L_2", + "PCIE_WW4A1_2", + "PCIE_FAN5_R_0", + "PCIE_TOP_TRNTD32", + "PCIE_BYP3_R_1", + "PCIE_IMUX10_R_0", + "PCIE_SW4A0_1", + "PCIE_LOGIC_OUTS_B23_R_1", + "PCIE_IMUX1_L_2", + "PCIE_NE4C2_2", + "PCIE_TOP_MIMRXWDATA22", + "PCIE_EE4B2_0", + "PCIE_TOP_CFGTRANSACTIONADDR0", + "PCIE_WR1END3_1", + "PCIE_NW4END1_0", + "PCIE_IMUX25_R_2", + "PCIE_NE2A1_2", + "PCIE_TOP_TRNRD87", + "PCIE_EE4B3_2", + "PCIE_IMUX35_R_2", + "PCIE_TOP_TRNRDLLPDATA37", + "PCIE_TOP_TRNRD81", + "PCIE_NE4C3_2", + "PCIE_LOGIC_OUTS_B3_L_3", + "PCIE_LOGIC_OUTS_B7_L_3", + "PCIE_WL1END2_1", + "PCIE_LOGIC_OUTS_B11_L_1", + "PCIE_EE4A3_4", + "PCIE_LOGIC_OUTS_B20_L_2", + "PCIE_TOP_PIPETXMARGIN0", + "PCIE_TOP_PIPERX0PHYSTATUS", + "PCIE_WW2A1_2", + "PCIE_TOP_MIMRXWDATA23", + "PCIE_EE2A0_3", + "PCIE_TOP_MIMRXWDATA0", + "PCIE_FAN0_L_2", + "PCIE_WW4C3_4", + "PCIE_WW4C2_1", + "PCIE_IMUX45_R_4", + "PCIE_IMUX31_R_4", + "PCIE_SE4C1_0", + "PCIE_IMUX7_L_3", + "PCIE_IMUX15_L_1", + "PCIE_EE2BEG3_3", + "PCIE_LOGIC_OUTS_B10_L_2", + "PCIE_IMUX6_L_1", + "PCIE_IMUX47_R_0", + "PCIE_IMUX22_R_3", + "PCIE_TOP_MIMRXWDATA29", + "PCIE_IMUX33_L_0", + "PCIE_IMUX23_L_2", + "PCIE_WW4B1_2", + "PCIE_FAN7_L_4", + "PCIE_LH10_2", + "PCIE_IMUX10_L_2", + "PCIE_FAN4_R_1", + "PCIE_NE2A3_4", + "PCIE_WW4END0_1", + "PCIE_IMUX9_L_4", + "PCIE_TOP_MIMRXWEN", + "PCIE_IMUX9_L_2", + "PCIE_TOP_CFGERRAERHEADERLOG0", + "PCIE_MONITOR_P_4", + "PCIE_IMUX27_L_1", + "PCIE_SE2A3_1", + "PCIE_TOP_PL2DIRECTEDLSTATE2", + "PCIE_IMUX7_R_3", + "PCIE_TOP_TRNRDLLPDATA39", + "PCIE_IMUX5_R_3", + "PCIE_LH4_1", + "PCIE_NW4END0_2", + "PCIE_IMUX27_L_4", + "PCIE_FAN1_R_3", + "PCIE_TOP_DRPDI5", + "PCIE_TOP_TRNTD35", + "PCIE_IMUX46_L_4", + "PCIE_IMUX14_L_0", + "PCIE_TOP_TRNTD27", + "PCIE_LOGIC_OUTS_B15_R_3", + "PCIE_IMUX13_R_3", + "PCIE_IMUX18_R_4", + "PCIE_IMUX36_R_3", + "PCIE_IMUX10_L_3", + "PCIE_SW2A1_2", + "PCIE_WW4B2_3", + "PCIE_WW4A0_0", + "PCIE_WW4END3_3", + "PCIE_BYP6_L_3", + "PCIE_SE4BEG3_0", + "PCIE_TOP_CFGDEVID15", + "PCIE_IMUX43_L_2", + "PCIE_EE4A1_4", + "PCIE_TOP_PIPERX4DATA4", + "PCIE_NE4BEG3_2", + "PCIE_LOGIC_OUTS_B1_R_3", + "PCIE_IMUX25_R_1", + "PCIE_FAN4_L_1", + "PCIE_IMUX17_L_3", + "PCIE_TOP_CFGPMRCVREQACKN", + "PCIE_BYP2_L_3", + "PCIE_TOP_PIPERX0DATA5", + "PCIE_IMUX35_R_0", + "PCIE_TOP_TRNTDLLPDATA22", + "PCIE_TOP_TRNRD91", + "PCIE_TOP_CFGMGMTDO30", + "PCIE_NW2A0_0", + "PCIE_SW2A0_0", + "PCIE_FAN2_L_4", + "PCIE_TOP_MIMRXRADDR8", + "PCIE_TOP_CFGLINKCONTROLLINKDISABLE", + "PCIE_IMUX25_L_4", + "PCIE_TOP_MIMRXRDATA24", + "PCIE_SE2A0_4", + "PCIE_EE4BEG2_2", + "PCIE_EE4A1_2", + "PCIE_IMUX43_L_1", + "PCIE_LH5_3", + "PCIE_WW2END3_3", + "PCIE_TOP_MIMRXRDATA30", + "PCIE_TOP_MIMRXRDATA49", + "PCIE_CTRL0_L_4", + "PCIE_LOGIC_OUTS_B17_R_0", + "PCIE_TOP_TRNRD65", + "PCIE_SE4BEG1_0", + "PCIE_EL1BEG3_3", + "PCIE_IMUX30_L_1", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3", + "PCIE_WW2A3_2", + "PCIE_SE4C1_4", + "PCIE_LH9_2", + "PCIE_SE2A2_1", + "PCIE_BLOCK_OUTS_B2_R_3", + "PCIE_TOP_DRPDI1", + "PCIE_LOGIC_OUTS_B23_R_0", + "PCIE_IMUX31_R_3", + "PCIE_TOP_DRPDO0", + "PCIE_TOP_LL2SENDENTERL1", + "PCIE_IMUX36_R_2", + "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK", + "PCIE_TOP_MIMRXRDATA36", + "PCIE_EL1BEG1_0", + "PCIE_TOP_SCANENABLEN", + "PCIE_BYP6_L_4", + "PCIE_WW2END1_3", + "PCIE_FAN1_L_4", + "PCIE_BYP2_L_4", + "PCIE_SW4END1_1", + "PCIE_LH5_0", + "PCIE_TOP_TRNRDLLPDATA47", + "PCIE_LOGIC_OUTS_B13_L_4", + "PCIE_LOGIC_OUTS_B21_L_2", + "PCIE_IMUX36_R_0", + "PCIE_TOP_CFGVCTCVCMAP0", + "PCIE_TOP_CFGDEVID12", + "PCIE_WW4END2_4", + "PCIE_LOGIC_OUTS_B20_R_0", + "PCIE_TOP_TRNRD90", + "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK", + "PCIE_WW4B2_1", + "PCIE_TOP_CFGERRTLPCPLHEADER32", + "PCIE_TOP_CFGERRAERHEADERLOG6", + "PCIE_IMUX17_L_4", + "PCIE_EL1BEG2_0", + "PCIE_TOP_TRNRDLLPDATA63", + "PCIE_TOP_DBGVECA1", + "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN", + "PCIE_LH10_1", + "PCIE_TOP_PL2RECOVERY", + "PCIE_IMUX26_R_2", + "PCIE_LOGIC_OUTS_B3_R_1", + "PCIE_MONITOR_N_2", + "PCIE_IMUX3_R_3", + "PCIE_LOGIC_OUTS_B21_L_1", + "PCIE_EE2BEG2_0", + "PCIE_CLK0_L_0", + "PCIE_IMUX45_L_0", + "PCIE_IMUX37_L_0", + "PCIE_MONITOR_N_3", + "PCIE_WW4END1_4", + "PCIE_LOGIC_OUTS_B4_R_3", + "PCIE_IMUX41_L_2", + "PCIE_TOP_MIMRXWDATA12", + "PCIE_NW4A0_1", + "PCIE_WW4B1_0", + "PCIE_IMUX15_R_2", + "PCIE_CTRL0_L_3", + "PCIE_LOGIC_OUTS_B22_R_2", + "PCIE_WW4B3_1", + "PCIE_IMUX42_R_1", + "PCIE_BYP2_R_2", + "PCIE_TOP_TRNRD94", + "PCIE_BYP2_L_2", + "PCIE_BYP7_R_3", + "PCIE_TOP_CFGINTERRUPTN", + "PCIE_IMUX22_R_4", + "PCIE_BYP5_L_0", + "PCIE_TOP_TRNRD64", + "PCIE_EE2BEG1_1", + "PCIE_LH3_0", + "PCIE_IMUX0_R_3", + "PCIE_IMUX47_L_0", + "PCIE_NW2A1_4", + "PCIE_EE4C1_2", + "PCIE_EE4B3_0", + "PCIE_TOP_TRNRDLLPSRCRDY1", + "PCIE_NW4A3_1", + "PCIE_TOP_CFGERRTLPCPLHEADER46", + "PCIE_LOGIC_OUTS_B4_L_3", + "PCIE_TOP_TRNRDLLPDATA41", + "PCIE_IMUX12_L_0", + "PCIE_TOP_TRNRDLLPDATA49", + "PCIE_WW4A3_3", + "PCIE_BLOCK_OUTS_B2_L_3", + "PCIE_IMUX14_R_0", + "PCIE_IMUX46_L_0", + "PCIE_TOP_MIMRXWDATA8", + "PCIE_TOP_TRNRD60", + "PCIE_TOP_MIMRXRDATA31", + "PCIE_TOP_DRPDI14", + "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN", + "PCIE_IMUX6_R_3", + "PCIE_BYP3_L_0", + "PCIE_FAN3_L_0", + "PCIE_EE4BEG2_3", + "PCIE_TOP_TRNTD38", + "PCIE_TOP_MIMRXWDATA3", + "PCIE_LOGIC_OUTS_B11_R_3", + "PCIE_LOGIC_OUTS_B1_R_4", + "PCIE_NE4C2_4", + "PCIE_NE4BEG1_0", + "PCIE_EL1BEG3_2", + "PCIE_BLOCK_OUTS_B2_R_4", + "PCIE_WW4A0_1", + "PCIE_CTRL1_L_3", + "PCIE_SW4A2_2", + "PCIE_LOGIC_OUTS_B19_L_1", + "PCIE_LOGIC_OUTS_B2_L_3", + "PCIE_FAN6_L_1", + "PCIE_TOP_MIMRXRDATA42", + "PCIE_CTRL0_L_0", + "PCIE_IMUX42_L_1", + "PCIE_IMUX28_R_3", + "PCIE_FAN2_L_1", + "PCIE_IMUX23_R_4", + "PCIE_IMUX34_R_2", + "PCIE_LOGIC_OUTS_B0_L_0", + "PCIE_IMUX21_R_3", + "PCIE_IMUX5_R_4", + "PCIE_LOGIC_OUTS_B9_L_1", + "PCIE_TOP_TRNRDLLPDATA55", + "PCIE_NW4END1_1", + "PCIE_WW4A0_2", + "PCIE_WL1END1_0", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0", + "PCIE_WW4A3_0", + "PCIE_FAN7_R_2", + "PCIE_BYP5_R_2", + "PCIE_SW4END3_3", + "PCIE_BYP5_R_0", + "PCIE_BYP7_L_1", + "PCIE_IMUX30_L_0", + "PCIE_TOP_TRNTDLLPDATA19", + "PCIE_NW2A3_1", + "PCIE_WW4END1_2", + "PCIE_TOP_MIMRXRADDR10", + "PCIE_IMUX22_R_2", + "PCIE_TOP_TRNRD72", + "PCIE_BLOCK_OUTS_B3_R_3", + "PCIE_IMUX2_R_4", + "PCIE_CLK1_R_1", + "PCIE_WW4C3_3", + "PCIE_EE2A1_4", + "PCIE_TOP_PIPERX0DATA2", + "PCIE_TOP_TRNRDLLPDATA58", + "PCIE_TOP_TRNTDLLPDATA25", + "PCIE_IMUX40_R_4", + "PCIE_WW2A0_1", + "PCIE_TOP_CFGPMCSRPMEEN", + "PCIE_IMUX38_L_0", + "PCIE_TOP_TRNRD77", + "PCIE_FAN0_R_4", + "PCIE_IMUX16_R_4", + "PCIE_SE4BEG0_4", + "PCIE_SW2A0_1", + "PCIE_TOP_CFGTRANSACTIONADDR3", + "PCIE_SW2A1_0", + "PCIE_FAN0_R_1", + "PCIE_TOP_MIMRXRDATA34", + "PCIE_IMUX0_L_1", + "PCIE_TOP_CFGERRTLPCPLHEADER45", + "PCIE_FAN5_R_2", + "PCIE_EE2A0_1", + "PCIE_FAN6_R_4", + "PCIE_TOP_MIMRXWDATA30", + "PCIE_IMUX17_R_0", + "PCIE_SW2A3_3", + "PCIE_TOP_MIMRXWADDR12", + "PCIE_BLOCK_OUTS_B3_L_1", + "PCIE_IMUX17_L_1", + "PCIE_EE4C3_3", + "PCIE_IMUX28_R_1", + "PCIE_IMUX43_R_1", + "PCIE_TOP_TRNTDLLPDATA26", + "PCIE_FAN0_L_1", + "PCIE_EE2A2_4", + "PCIE_LOGIC_OUTS_B11_R_0", + "PCIE_IMUX45_R_1", + "PCIE_LOGIC_OUTS_B22_R_3", + "PCIE_TOP_MIMRXRDATA37", + "PCIE_TOP_CFGMGMTDO17", + "PCIE_BYP7_L_4", + "PCIE_NE2A3_0", + "PCIE_BYP2_R_1", + "PCIE_TOP_TRNRDLLPDATA59", + "PCIE_NE4BEG2_0", + "PCIE_WL1END0_2", + "PCIE_WR1END2_1", + "PCIE_TOP_DRPDI3", + "PCIE_TOP_DRPDI2", + "PCIE_LH11_3", + "PCIE_EE2A1_0", + "PCIE_SE2A3_0", + "PCIE_IMUX36_L_2", + "PCIE_LH10_3", + "PCIE_SW4A0_0", + "PCIE_TOP_CFGPMCSRPOWERSTATE1", + "PCIE_IMUX16_L_2", + "PCIE_NE4C0_3", + "PCIE_IMUX19_L_2", + "PCIE_TOP_TRNRD59", + "PCIE_TOP_CFGPMRCVASREQL1N", + "PCIE_IMUX39_L_2", + "PCIE_IMUX26_L_4", + "PCIE_LOGIC_OUTS_B21_L_3", + "PCIE_IMUX30_R_0", + "PCIE_EE2A3_3", + "PCIE_IMUX16_L_3", + "PCIE_EE4C2_1", + "PCIE_IMUX24_R_3", + "PCIE_IMUX25_R_4", + "PCIE_SW4END0_2", + "PCIE_NE4C1_0", + "PCIE_EE2A2_1", + "PCIE_WL1END1_3", + "PCIE_EE4A3_1", + "PCIE_IMUX42_R_0", + "PCIE_IMUX5_R_2", + "PCIE_LOGIC_OUTS_B9_L_0", + "PCIE_TOP_TRNRDLLPDATA42", + "PCIE_LH1_3", + "PCIE_TOP_CFGMGMTDO24", + "PCIE_IMUX21_L_2", + "PCIE_BYP1_L_3", + "PCIE_EE2BEG2_2", + "PCIE_TOP_MIMRXWADDR2", + "PCIE_NW4A1_2", + "PCIE_BYP1_L_2", + "PCIE_LOGIC_OUTS_B16_R_2", + "PCIE_IMUX40_L_3", + "PCIE_NW2A1_0", + "PCIE_IMUX5_L_1", + "PCIE_WW2END2_1", + "PCIE_WL1END0_0", + "PCIE_IMUX25_L_0", + "PCIE_IMUX7_L_2", + "PCIE_IMUX3_R_2", + "PCIE_SE4BEG3_1", + "PCIE_IMUX0_L_4", + "PCIE_TOP_DRPDI10", + "PCIE_WW4END0_0", + "PCIE_LOGIC_OUTS_B4_L_1", + "PCIE_LH6_1", + "PCIE_NW2A2_4", + "PCIE_LOGIC_OUTS_B16_R_1", + "PCIE_WW4END2_0", + "PCIE_FAN7_R_1", + "PCIE_SE4C1_2", + "PCIE_BYP5_L_3", + "PCIE_FAN1_L_2", + "PCIE_LOGIC_OUTS_B6_L_4", + "PCIE_IMUX43_L_0", + "PCIE_LH10_4", + "PCIE_TOP_DRPRDY", + "PCIE_IMUX26_L_2", + "PCIE_SE4BEG0_0", + "PCIE_IMUX30_L_4", + "PCIE_IMUX24_L_3", + "PCIE_TOP_PIPERX4CHARISK0", + "PCIE_IMUX8_L_2", + "PCIE_WW2A3_4", + "PCIE_IMUX37_L_4", + "PCIE_LOGIC_OUTS_B23_L_1", + "PCIE_EE4BEG1_2", + "PCIE_BLOCK_OUTS_B3_L_2", + "PCIE_IMUX25_R_0", + "PCIE_TOP_TRNTD16", + "PCIE_IMUX27_L_0", + "PCIE_TOP_DBGMODE0", + "PCIE_LOGIC_OUTS_B5_R_3", + "PCIE_NE2A0_2", + "PCIE_LOGIC_OUTS_B7_R_0", + "PCIE_BYP6_R_1", + "PCIE_TOP_MIMRXWDATA28", + "PCIE_TOP_DBGVECA20", + "PCIE_LOGIC_OUTS_B0_L_3", + "PCIE_WW4B1_1", + "PCIE_IMUX28_L_1", + "PCIE_TOP_TRNTD28", + "PCIE_TOP_TRNTDLLPDATA23", + "PCIE_TOP_LL2TLPRCV", + "PCIE_LOGIC_OUTS_B7_L_0", + "PCIE_IMUX6_L_0", + "PCIE_IMUX0_L_3", + "PCIE_CTRL0_R_4", + "PCIE_LOGIC_OUTS_B16_R_0", + "PCIE_NE2A2_4", + "PCIE_NW2A3_2", + "PCIE_IMUX18_L_1", + "PCIE_IMUX18_L_2", + "PCIE_NW4A2_1", + "PCIE_NE4C3_0", + "PCIE_SW4A3_1", + "PCIE_LOGIC_OUTS_B18_L_2", + "PCIE_IMUX8_L_3", + "PCIE_IMUX26_R_3", + "PCIE_WW4A3_2", + "PCIE_WL1END3_4", + "PCIE_IMUX2_L_2", + "PCIE_BLOCK_OUTS_B1_L_4", + "PCIE_LOGIC_OUTS_B15_L_0", + "PCIE_IMUX15_L_0", + "PCIE_LOGIC_OUTS_B8_R_0", + "PCIE_IMUX11_R_3", + "PCIE_EE4B2_1", + "PCIE_IMUX16_L_0", + "PCIE_BLOCK_OUTS_B1_R_4", + "PCIE_TOP_MIMRXRADDR1", + "PCIE_LOGIC_OUTS_B20_L_4", + "PCIE_WW4END0_3", + "PCIE_ER1BEG1_0", + "PCIE_LOGIC_OUTS_B13_R_0", + "PCIE_TOP_CFGDSN60", + "PCIE_IMUX43_R_4", + "PCIE_EE4A3_0", + "PCIE_IMUX22_L_3", + "PCIE_LOGIC_OUTS_B22_L_4", + "PCIE_IMUX42_L_4", + "PCIE_TOP_CFGERRTLPCPLHEADER29", + "PCIE_IMUX34_L_4", + "PCIE_IMUX10_R_3", + "PCIE_TOP_DRPDI15", + "PCIE_BLOCK_OUTS_B2_R_0", + "PCIE_BLOCK_OUTS_B2_R_2", + "PCIE_WW4A2_2", + "PCIE_NE2A1_4", + "PCIE_TOP_TRNTD33", + "PCIE_SW2A3_0", + "PCIE_IMUX43_R_0", + "PCIE_SW4END0_4", + "PCIE_TOP_MIMRXRADDR9", + "PCIE_IMUX20_L_4", + "PCIE_IMUX27_R_4", + "PCIE_IMUX20_R_4", + "PCIE_TOP_DBGVECA3", + "PCIE_EE2BEG1_2", + "PCIE_WW2END2_3", + "PCIE_IMUX42_R_2", + "PCIE_LOGIC_OUTS_B2_L_0", + "PCIE_TOP_MIMRXWDATA9", + "PCIE_IMUX8_R_0", + "PCIE_TOP_TRNRDLLPDATA56", + "PCIE_IMUX23_L_1", + "PCIE_IMUX20_L_2", + "PCIE_IMUX6_L_3", + "PCIE_FAN2_L_3", + "PCIE_TOP_CFGERRTLPCPLHEADER40", + "PCIE_IMUX29_R_1", + "PCIE_IMUX29_R_3", + "PCIE_TOP_PIPERX4DATA6", + "PCIE_BLOCK_OUTS_B0_R_2", + "PCIE_TOP_PL2SUSPENDOK", + "PCIE_LOGIC_OUTS_B19_R_2", + "PCIE_IMUX4_R_4", + "PCIE_SW4A3_3", + "PCIE_WW4A2_3", + "PCIE_TOP_CFGDEVID2", + "PCIE_BLOCK_OUTS_B2_L_0", + "PCIE_BYP3_R_0", + "PCIE_IMUX31_L_0", + "PCIE_FAN2_R_4", + "PCIE_TOP_DRPDI4", + "PCIE_IMUX22_L_1", + "PCIE_IMUX33_R_3", + "PCIE_IMUX32_L_3", + "PCIE_TOP_XILUNCONNOUT28", + "PCIE_TOP_MIMRXWDATA49", + "PCIE_BYP4_R_1", + "PCIE_LOGIC_OUTS_B10_L_1", + "PCIE_TOP_TRNTD39", + "PCIE_IMUX20_R_0", + "PCIE_WR1END3_3", + "PCIE_BYP7_R_2", + "PCIE_IMUX41_R_3", + "PCIE_EE4A2_0", + "PCIE_TOP_PIPERX0CHANISALIGNED", + "PCIE_IMUX40_L_0", + "PCIE_SE2A2_3", + "PCIE_IMUX14_L_2", + "PCIE_SW4END0_0", + "PCIE_BYP1_R_1", + "PCIE_TOP_CFGVCTCVCMAP3", + "PCIE_TOP_TRNRD93", + "PCIE_TOP_PIPERX4DATA7", + "PCIE_LOGIC_OUTS_B1_L_0", + "PCIE_IMUX39_L_0", + "PCIE_IMUX29_R_0", + "PCIE_LOGIC_OUTS_B6_L_3", + "PCIE_SW4A2_1", + "PCIE_TOP_CFGTRANSACTION", + "PCIE_IMUX8_L_1", + "PCIE_TOP_TRNTD31", + "PCIE_LOGIC_OUTS_B9_R_3", + "PCIE_BLOCK_OUTS_B0_R_0", + "PCIE_ER1BEG0_4", + "PCIE_LOGIC_OUTS_B15_L_3", + "PCIE_BYP5_R_3", + "PCIE_IMUX46_R_4", + "PCIE_LOGIC_OUTS_B12_R_3", + "PCIE_LOGIC_OUTS_B0_L_4", + "PCIE_CTRL1_L_2", + "PCIE_IMUX23_R_1", + "PCIE_IMUX18_R_2", + "PCIE_LOGIC_OUTS_B21_R_4", + "PCIE_WL1END2_3", + "PCIE_LOGIC_OUTS_B16_L_4", + "PCIE_LOGIC_OUTS_B5_R_1", + "PCIE_IMUX22_L_2", + "PCIE_WW2END1_4", + "PCIE_BYP6_L_2", + "PCIE_SE4BEG1_3", + "PCIE_CTRL0_R_0", + "PCIE_FAN3_R_2", + "PCIE_TOP_TRNTDLLPDATA29", + "PCIE_TOP_DRPDI7", + "PCIE_SE2A0_0", + "PCIE_TOP_DRPDO2", + "PCIE_TOP_PIPERX0DATA0", + "PCIE_LOGIC_OUTS_B5_L_2", + "PCIE_IMUX9_R_3", + "PCIE_IMUX39_L_1", + "PCIE_CLK1_L_2", + "PCIE_LH7_4", + "PCIE_IMUX3_R_4", + "PCIE_TOP_PL2DIRECTEDLSTATE3", + "PCIE_EE4BEG3_3", + "PCIE_FAN4_L_3", + "PCIE_FAN6_R_1", + "PCIE_TOP_CFGERRAERHEADERLOG5", + "PCIE_TOP_CFGMGMTDO23", + "PCIE_WW4END2_3", + "PCIE_WW4B0_2", + "PCIE_EE4A0_2", + "PCIE_IMUX1_L_0", + "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN", + "PCIE_LOGIC_OUTS_B23_R_3", + "PCIE_WW2END3_0", + "PCIE_WW2A1_3", + "PCIE_TOP_DBGVECA18", + "PCIE_EE4A2_4", + "PCIE_NW4A2_2", + "PCIE_CLK0_L_4", + "PCIE_TOP_CFGERRAERHEADERLOG3", + "PCIE_NW4A2_0", + "PCIE_IMUX1_L_1", + "PCIE_TOP_PL2DIRECTEDLSTATE1", + "PCIE_TOP_MIMRXRDATA52", + "PCIE_NW4END1_4", + "PCIE_NE4C3_3", + "PCIE_TOP_MIMRXRDATA48", + "PCIE_TOP_TRNRDLLPDATA44", + "PCIE_FAN5_R_1", + "PCIE_EE4A3_3", + "PCIE_TOP_LL2SENDASREQL1", + "PCIE_TOP_CFGDEVID3", + "PCIE_SE2A1_2", + "PCIE_TOP_DRPDI12", + "PCIE_LOGIC_OUTS_B23_R_4", + "PCIE_EL1BEG1_1", + "PCIE_ER1BEG1_3", + "PCIE_WL1END0_3", + "PCIE_IMUX43_L_4", + "PCIE_WW4C0_0", + "PCIE_IMUX4_L_1", + "PCIE_IMUX26_R_4", + "PCIE_TOP_MIMRXWDATA2", + "PCIE_WW4B1_3", + "PCIE_CTRL0_L_1", + "PCIE_IMUX37_R_2", + "PCIE_NW4END3_3", + "PCIE_WW2END0_4", + "PCIE_IMUX30_L_3", + "PCIE_TOP_CFGDEVID7", + "PCIE_IMUX7_R_1", + "PCIE_SW4END1_3", + "PCIE_SE4BEG1_1", + "PCIE_SW2A2_0", + "PCIE_TOP_TRNTD17", + "PCIE_BYP0_L_4", + "PCIE_LH6_2", + "PCIE_LOGIC_OUTS_B7_L_4", + "PCIE_IMUX30_L_2", + "PCIE_IMUX47_R_3", + "PCIE_IMUX22_L_0", + "PCIE_TOP_TRNTD40", + "PCIE_TOP_TRNTDLLPDATA30", + "PCIE_TOP_TRNRDLLPDATA40", + "PCIE_IMUX0_R_0", + "PCIE_EE2BEG3_4", + "PCIE_BYP6_R_0", + "PCIE_ER1BEG2_0", + "PCIE_LOGIC_OUTS_B14_L_0", + "PCIE_IMUX10_R_2", + "PCIE_IMUX44_R_2", + "PCIE_LOGIC_OUTS_B0_L_1", + "PCIE_TOP_TRNRDLLPDATA32", + "PCIE_IMUX11_R_0", + "PCIE_IMUX38_L_4", + "PCIE_WR1END3_0", + "PCIE_IMUX26_R_0", + "PCIE_IMUX23_R_2", + "PCIE_BLOCK_OUTS_B3_R_2", + "PCIE_TOP_PIPERX0DATA1", + "PCIE_NE4C1_2", + "PCIE_TOP_MIMRXRDATA35", + "PCIE_FAN3_R_1", + "PCIE_BYP1_L_1", + "PCIE_MONITOR_N_1", + "PCIE_TOP_DBGVECA9", + "PCIE_EE4B1_2", + "PCIE_CTRL1_L_1", + "PCIE_IMUX12_R_3", + "PCIE_SW2A0_2", + "PCIE_IMUX33_R_0", + "PCIE_TOP_CFGCOMMANDIOENABLE", + "PCIE_TOP_TRNRDLLPDATA61", + "PCIE_LOGIC_OUTS_B16_L_0", + "PCIE_IMUX10_L_0", + "PCIE_IMUX32_R_2", + "PCIE_LOGIC_OUTS_B15_L_2", + "PCIE_NW4END2_2", + "PCIE_TOP_CFGERRAERHEADERLOG1", + "PCIE_IMUX0_L_0", + "PCIE_IMUX46_R_2", + "PCIE_TOP_PIPERX4DATA2", + "PCIE_IMUX17_L_2", + "PCIE_IMUX23_L_0", + "PCIE_IMUX20_R_1", + "PCIE_EE4C3_2", + "PCIE_LOGIC_OUTS_B9_L_2", + "PCIE_LOGIC_OUTS_B23_L_3", + "PCIE_IMUX18_L_3", + "PCIE_CTRL0_L_2", + "PCIE_BYP6_R_4", + "PCIE_LOGIC_OUTS_B13_R_1", + "PCIE_WW2A0_0", + "PCIE_BYP6_L_1", + "PCIE_ER1BEG0_2", + "PCIE_NE2A2_3", + "PCIE_TOP_DRPDO1", + "PCIE_EL1BEG0_4", + "PCIE_FAN4_R_4", + "PCIE_SE4BEG2_2", + "PCIE_BYP2_R_4", + "PCIE_IMUX47_L_1", + "PCIE_LOGIC_OUTS_B8_R_1", + "PCIE_FAN2_L_0", + "PCIE_MONITOR_P_3", + "PCIE_IMUX22_R_1", + "PCIE_IMUX1_R_4", + "PCIE_SW2A3_2", + "PCIE_TOP_LL2TFCINIT1SEQ", + "PCIE_NE4BEG3_1", + "PCIE_IMUX19_L_0", + "PCIE_LOGIC_OUTS_B3_L_1", + "PCIE_IMUX8_R_1", + "PCIE_IMUX0_R_2", + "PCIE_IMUX40_R_2", + "PCIE_NW2A0_2", + "PCIE_EE2A1_1", + "PCIE_IMUX26_L_1", + "PCIE_BYP6_R_2", + "PCIE_TOP_PIPERX0DATA7", + "PCIE_SE4C0_1", + "PCIE_EL1BEG2_1", + "PCIE_IMUX7_R_0", + "PCIE_SW2A2_1", + "PCIE_IMUX29_L_1", + "PCIE_BLOCK_OUTS_B2_R_1", + "PCIE_IMUX38_R_2", + "PCIE_SE2A0_1", + "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1", + "PCIE_IMUX12_R_1", + "PCIE_TOP_TRNRDLLPDATA33", + "PCIE_IMUX3_L_0", + "PCIE_IMUX15_R_0", + "PCIE_IMUX5_R_0", + "PCIE_TOP_MIMRXWDATA27", + "PCIE_WW2END2_4", + "PCIE_IMUX16_R_0", + "PCIE_IMUX29_L_4", + "PCIE_BYP1_L_4", + "PCIE_TOP_CFGCOMMANDMEMENABLE", + "PCIE_WW4A3_1", + "PCIE_TOP_CFGERRTLPCPLHEADER35", + "PCIE_LH5_4", + "PCIE_LOGIC_OUTS_B13_L_0", + "PCIE_NW4END2_0", + "PCIE_EL1BEG1_2", + "PCIE_WL1END1_1", + "PCIE_IMUX27_R_2", + "PCIE_TOP_MIMRXRDATA46", + "PCIE_EE4BEG3_2", + "PCIE_LOGIC_OUTS_B11_L_4", + "PCIE_EE4C3_1", + "PCIE_TOP_TRNTD30", + "PCIE_FAN4_R_2", + "PCIE_EE4A0_1", + "PCIE_LH12_4", + "PCIE_TOP_MIMRXRADDR11", + "PCIE_IMUX44_R_1", + "PCIE_TOP_DBGVECA0", + "PCIE_IMUX21_L_3", + "PCIE_WW4C1_1", + "PCIE_LOGIC_OUTS_B18_L_3", + "PCIE_EE2A2_3", + "PCIE_IMUX16_L_4", + "PCIE_EE4A2_1", + "PCIE_IMUX41_L_1", + "PCIE_WW2A2_1", + "PCIE_CLK0_R_0", + "PCIE_WR1END0_3", + "PCIE_TOP_CFGMGMTDO25", + "PCIE_TOP_TRNRD79", + "PCIE_IMUX21_L_1", + "PCIE_TOP_TRNRD71", + "PCIE_LOGIC_OUTS_B10_R_2", + "PCIE_IMUX4_L_3", + "PCIE_TOP_MIMRXWDATA13", + "PCIE_TOP_TRNRD62", + "PCIE_WW4B3_0", + "PCIE_TOP_CFGDEVID14", + "PCIE_TOP_TRNRD82", + "PCIE_LH5_1", + "PCIE_EE2BEG1_0", + "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1", + "PCIE_NE4BEG2_3", + "PCIE_EL1BEG0_2", + "PCIE_IMUX34_L_1", + "PCIE_IMUX19_L_1", + "PCIE_LOGIC_OUTS_B21_R_2", + "PCIE_LH3_2", + "PCIE_TOP_CFGTRANSACTIONADDR2", + "PCIE_LH11_0", + "PCIE_EE2BEG1_4", + "PCIE_TOP_PIPERX4DATA5", + "PCIE_SE4C3_0", + "PCIE_BYP4_R_0", + "PCIE_ER1BEG3_0", + "PCIE_IMUX20_R_3", + "PCIE_NE4C2_1", + "PCIE_LH6_3", + "PCIE_IMUX4_L_2", + "PCIE_IMUX10_R_4", + "PCIE_TOP_TRNTDLLPDATA31", + "PCIE_TOP_TL2PPMSUSPENDREQ", + "PCIE_IMUX47_L_4", + "PCIE_WW2END0_0", + "PCIE_WW2END2_2", + "PCIE_WW4A2_1", + "PCIE_LOGIC_OUTS_B23_L_4", + "PCIE_EE4C3_0", + "PCIE_CTRL0_R_2", + "PCIE_TOP_MIMRXRDATA55", + "PCIE_BLOCK_OUTS_B3_L_0", + "PCIE_LOGIC_OUTS_B16_R_4", + "PCIE_IMUX25_L_2", + "PCIE_LOGIC_OUTS_B12_L_3", + "PCIE_SW4END3_1", + "PCIE_SW4END2_0", + "PCIE_LOGIC_OUTS_B12_R_1", + "PCIE_TOP_MIMRXRDATA51", + "PCIE_LOGIC_OUTS_B22_L_3", + "PCIE_LOGIC_OUTS_B10_R_0", + "PCIE_LOGIC_OUTS_B22_R_0", + "PCIE_CLK0_L_1", + "PCIE_IMUX9_L_3", + "PCIE_LOGIC_OUTS_B15_R_1", + "PCIE_SW4A3_2", + "PCIE_SW4A2_0", + "PCIE_TOP_TRNRDLLPDATA38", + "PCIE_TOP_DBGVECA12", + "PCIE_IMUX34_R_3", + "PCIE_IMUX13_L_0", + "PCIE_TOP_DRPADDR8", + "PCIE_TOP_MIMRXWDATA32", + "PCIE_BYP0_R_4", + "PCIE_BYP3_L_3", + "PCIE_LOGIC_OUTS_B23_R_2", + "PCIE_LOGIC_OUTS_B9_R_4", + "PCIE_NE4BEG1_2", + "PCIE_TOP_TRNTD13", + "PCIE_EL1BEG0_1", + "PCIE_IMUX40_R_0", + "PCIE_IMUX39_L_3", + "PCIE_NW4A1_3", + "PCIE_WW2A3_3", + "PCIE_IMUX32_R_3", + "PCIE_LOGIC_OUTS_B15_R_2", + "PCIE_LH2_1", + "PCIE_FAN6_L_2", + "PCIE_TOP_CFGDSN59", + "PCIE_BYP1_R_4", + "PCIE_LOGIC_OUTS_B6_L_1", + "PCIE_FAN2_L_2", + "PCIE_IMUX34_R_1", + "PCIE_EE4BEG2_1", + "PCIE_SW4END0_1", + "PCIE_IMUX28_L_2", + "PCIE_TOP_CFGINTERRUPTDI0", + "PCIE_WL1END3_0", + "PCIE_IMUX47_R_2", + "PCIE_LH9_0", + "PCIE_TOP_MIMRXRDATA26", + "PCIE_LOGIC_OUTS_B11_R_1", + "PCIE_TOP_TRNTDLLPDATA20", + "PCIE_IMUX33_L_2", + "PCIE_IMUX24_L_4", + "PCIE_IMUX20_L_0", + "PCIE_LOGIC_OUTS_B15_R_4", + "PCIE_IMUX31_L_4", + "PCIE_CLK0_R_4", + "PCIE_LOGIC_OUTS_B5_R_0", + "PCIE_LH7_1", + "PCIE_LOGIC_OUTS_B2_L_4", + "PCIE_LOGIC_OUTS_B5_L_4", + "PCIE_IMUX42_L_2", + "PCIE_TOP_TRNRDLLPDATA52", + "PCIE_FAN3_L_4", + "PCIE_EE2A2_0", + "PCIE_IMUX46_R_0", + "PCIE_TOP_TRNRDLLPSRCRDY0", + "PCIE_IMUX29_R_2", + "PCIE_IMUX37_L_2", + "PCIE_NE4C0_1", + "PCIE_EE4A1_3", + "PCIE_EE2A1_2", + "PCIE_IMUX12_L_1", + "PCIE_NW2A0_4", + "PCIE_TOP_CFGTRANSACTIONADDR6", + "PCIE_IMUX38_R_1", + "PCIE_MONITOR_N_0", + "PCIE_TOP_DBGVECA7", + "PCIE_NE4C2_0", + "PCIE_LOGIC_OUTS_B13_L_1", + "PCIE_WW4B0_1", + "PCIE_IMUX36_R_1", + "PCIE_IMUX35_L_3", + "PCIE_TOP_PL2DIRECTEDLSTATE0", + "PCIE_SE4C1_3", + "PCIE_IMUX3_L_1", + "PCIE_IMUX4_L_0", + "PCIE_BLOCK_OUTS_B3_R_0", + "PCIE_BYP3_R_2", + "PCIE_TOP_CFGERRTLPCPLHEADER34", + "PCIE_TOP_MIMRXWADDR1", + "PCIE_TOP_CFGERRTLPCPLHEADER39", + "PCIE_IMUX32_R_0", + "PCIE_LOGIC_OUTS_B16_L_1", + "PCIE_TOP_CFGERRAERHEADERLOG4", + "PCIE_WW2A0_2", + "PCIE_LOGIC_OUTS_B8_L_2", + "PCIE_NW4END3_1", + "PCIE_IMUX35_R_1", + "PCIE_LOGIC_OUTS_B18_L_1", + "PCIE_IMUX15_R_4", + "PCIE_NE4C2_3", + "PCIE_EE2A3_4", + "PCIE_BLOCK_OUTS_B0_L_1", + "PCIE_IMUX44_L_0", + "PCIE_LOGIC_OUTS_B20_R_2", + "PCIE_IMUX12_R_0", + "PCIE_IMUX33_L_4", + "PCIE_IMUX29_L_2", + "PCIE_IMUX4_L_4", + "PCIE_SE4BEG3_4", + "PCIE_SW4A2_4", + "PCIE_SE4C3_2", + "PCIE_IMUX31_R_1", + "PCIE_WW4B3_2", + "PCIE_WW2END0_3", + "PCIE_WW4C1_3", + "PCIE_TOP_TRNTD19", + "PCIE_WW4C3_2", + "PCIE_TOP_CFGDEVCONTROL2IDOREQEN", + "PCIE_IMUX34_L_3", + "PCIE_BLOCK_OUTS_B3_L_4", + "PCIE_TOP_DRPDI6", + "PCIE_WR1END2_3", + "PCIE_TOP_TRNTD37", + "PCIE_FAN3_R_4", + "PCIE_ER1BEG0_1", + "PCIE_LOGIC_OUTS_B17_R_3", + "PCIE_SE2A3_4", + "PCIE_LOGIC_OUTS_B2_R_2", + "PCIE_SW4END1_0", + "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN", + "PCIE_IMUX19_R_0", + "PCIE_IMUX38_R_3", + "PCIE_IMUX24_R_1", + "PCIE_TOP_CFGMGMTDO27", + "PCIE_IMUX47_R_1", + "PCIE_IMUX35_L_4", + "PCIE_WW2A0_3", + "PCIE_LH7_3", + "PCIE_IMUX34_L_0", + "PCIE_TOP_TRNTDSTRDY3", + "PCIE_WW2A2_2", + "PCIE_BYP7_L_2", + "PCIE_IMUX2_R_3", + "PCIE_SE2A3_3", + "PCIE_IMUX27_R_1", + "PCIE_TOP_TRNTD36", + "PCIE_WW2A0_4", + "PCIE_TOP_TRNTD22", + "PCIE_WR1END3_2", + "PCIE_SE4BEG0_3", + "PCIE_IMUX2_R_1", + "PCIE_BLOCK_OUTS_B1_R_1", + "PCIE_LH12_0", + "PCIE_LOGIC_OUTS_B17_R_4", + "PCIE_EE4B3_1", + "PCIE_EE4C1_4", + "PCIE_EE4A2_2", + "PCIE_EE2A2_2", + "PCIE_SE4C3_3", + "PCIE_TOP_MIMRXWDATA1", + "PCIE_IMUX0_L_2", + "PCIE_NW2A3_0", + "PCIE_WW4B2_0", + "PCIE_LH2_3", + "PCIE_EE4A2_3", + "PCIE_EE4B2_3", + "PCIE_SE4C2_0", + "PCIE_TOP_LL2SENDPMACK", + "PCIE_IMUX34_R_0", + "PCIE_IMUX7_R_2", + "PCIE_WW4B2_4", + "PCIE_SW2A2_2", + "PCIE_TOP_MIMRXWDATA33", + "PCIE_WW4C1_4", + "PCIE_LH3_4", + "PCIE_WL1END2_0", + "PCIE_SE4C0_3", + "PCIE_WW4A0_3", + "PCIE_TOP_CFGERRTLPCPLHEADER41", + "PCIE_IMUX47_R_4", + "PCIE_IMUX24_R_4", + "PCIE_IMUX41_R_4", + "PCIE_EE4BEG0_3", + "PCIE_LH6_0", + "PCIE_NW2A1_3", + "PCIE_TOP_MIMRXWDATA51", + "PCIE_LOGIC_OUTS_B4_R_1", + "PCIE_IMUX8_R_4", + "PCIE_SE4C2_1", + "PCIE_FAN6_L_0", + "PCIE_NW4END0_1", + "PCIE_CLK0_L_2", + "PCIE_NE4BEG0_4", + "PCIE_LOGIC_OUTS_B4_R_4", + "PCIE_IMUX24_R_0", + "PCIE_EE4B3_4", + "PCIE_EE2A3_2", + "PCIE_LOGIC_OUTS_B19_L_0", + "PCIE_BYP7_L_0", + "PCIE_SE4BEG2_4", + "PCIE_SE2A2_0", + "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN", + "PCIE_LOGIC_OUTS_B11_L_3", + "PCIE_FAN1_R_2", + "PCIE_LH1_1", + "PCIE_WW4END1_1", + "PCIE_WW4C3_1", + "PCIE_LOGIC_OUTS_B19_R_0", + "PCIE_FAN6_R_2", + "PCIE_NE4BEG2_4", + "PCIE_IMUX28_R_4", + "PCIE_IMUX32_L_2", + "PCIE_WW4C2_3", + "PCIE_BYP2_R_3", + "PCIE_TOP_MIMRXWDATA4", + "PCIE_TOP_TRNRD73", + "PCIE_SW4A1_4", + "PCIE_LOGIC_OUTS_B17_L_0", + "PCIE_WR1END1_4", + "PCIE_FAN0_L_4", + "PCIE_NE4C1_3", + "PCIE_LOGIC_OUTS_B9_L_3", + "PCIE_EE2BEG2_1", + "PCIE_IMUX13_R_4", + "PCIE_IMUX29_R_4", + "PCIE_LOGIC_OUTS_B11_L_0", + "PCIE_EE4BEG3_4", + "PCIE_TOP_DRPDO6", + "PCIE_LOGIC_OUTS_B9_R_2", + "PCIE_SW2A3_4", + "PCIE_SE4C0_2", + "PCIE_LOGIC_OUTS_B19_L_3", + "PCIE_FAN7_L_2", + "PCIE_WR1END2_0", + "PCIE_TOP_CFGERRAERHEADERLOG9", + "PCIE_SE4BEG1_4", + "PCIE_TOP_TRNRDLLPDATA43", + "PCIE_BLOCK_OUTS_B1_L_0", + "PCIE_TOP_MIMRXWDATA35", + "PCIE_LH12_2", + "PCIE_TOP_CFGDEVID6", + "PCIE_BYP0_L_0", + "PCIE_SE4C2_3", + "PCIE_NE4C1_1", + "PCIE_LOGIC_OUTS_B12_L_2", + "PCIE_LOGIC_OUTS_B11_R_4", + "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN", + "PCIE_BYP3_L_2", + "PCIE_EE2A1_3", + "PCIE_IMUX46_R_1", + "PCIE_WW4B3_4", + "PCIE_IMUX16_R_2", + "PCIE_WW4C1_0", + "PCIE_WW2END3_4", + "PCIE_LOGIC_OUTS_B18_R_3", + "PCIE_NE4C0_4", + "PCIE_IMUX24_R_2", + "PCIE_TOP_DBGVECA14", + "PCIE_LOGIC_OUTS_B22_R_4", + "PCIE_TOP_CFGDEVCONTROL2LTREN", + "PCIE_TOP_PLDBGVEC8", + "PCIE_EE2A0_0", + "PCIE_NW4A0_0", + "PCIE_LOGIC_OUTS_B10_R_1", + "PCIE_BYP3_R_3", + "PCIE_IMUX46_L_3", + "PCIE_LOGIC_OUTS_B5_L_3", + "PCIE_TOP_TRNRD95", + "PCIE_BYP4_L_0", + "PCIE_TOP_MIMRXRDATA47", + "PCIE_NE4BEG1_3", + "PCIE_WR1END1_0", + "PCIE_EE4BEG0_0", + "PCIE_TOP_DRPDI8", + "PCIE_TOP_CFGVCTCVCMAP6", + "PCIE_TOP_DBGVECA13", + "PCIE_LOGIC_OUTS_B1_R_2", + "PCIE_EE4BEG3_1", + "PCIE_FAN0_R_0", + "PCIE_LOGIC_OUTS_B5_R_4", + "PCIE_EE4A0_3", + "PCIE_BYP1_R_2", + "PCIE_BYP2_L_1", + "PCIE_NW4END1_3", + "PCIE_IMUX36_L_4", + "PCIE_TOP_MIMRXRDATA45", + "PCIE_FAN4_L_4", + "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS", + "PCIE_ER1BEG1_4", + "PCIE_WW2END0_1", + "PCIE_TOP_EDTUPDATE", + "PCIE_LOGIC_OUTS_B0_R_0", + "PCIE_NE4BEG1_1", + "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC", + "PCIE_FAN1_L_0", + "PCIE_IMUX36_L_3", + "PCIE_IMUX18_L_0", + "PCIE_TOP_CFGVCTCVCMAP1", + "PCIE_TOP_CFGPMCSRPOWERSTATE0", + "PCIE_IMUX21_R_2", + "PCIE_WW4END2_1", + "PCIE_CLK1_L_4", + "PCIE_TOP_TRNRDLLPDATA36", + "PCIE_SE4BEG0_2", + "PCIE_TOP_TRNRD83", + "PCIE_IMUX37_R_3", + "PCIE_IMUX44_L_3", + "PCIE_IMUX15_R_3", + "PCIE_EE4C2_2", + "PCIE_TOP_MIMRXWDATA26", + "PCIE_IMUX15_R_1", + "PCIE_TOP_TRNTD25", + "PCIE_CTRL0_R_3", + "PCIE_WW4A1_3", + "PCIE_EL1BEG1_4", + "PCIE_IMUX5_R_1", + "PCIE_CTRL1_L_0", + "PCIE_IMUX17_L_0", + "PCIE_IMUX31_L_3", + "PCIE_IMUX2_R_2", + "PCIE_IMUX13_L_1", + "PCIE_IMUX20_L_3", + "PCIE_LH4_3", + "PCIE_IMUX47_L_2", + "PCIE_TOP_CFGVENDID0", + "PCIE_LOGIC_OUTS_B0_R_4", + "PCIE_LOGIC_OUTS_B13_R_4", + "PCIE_IMUX17_R_4", + "PCIE_SW4A1_1", + "PCIE_BYP4_L_3", + "PCIE_TOP_CFGDSN57", + "PCIE_NW4A0_4", + "PCIE_IMUX9_R_4", + "PCIE_IMUX25_L_1", + "PCIE_IMUX35_L_0", + "PCIE_FAN2_R_2", + "PCIE_NW4A1_1", + "PCIE_LOGIC_OUTS_B18_R_4", + "PCIE_TOP_MIMRXWDATA15", + "PCIE_TOP_TRNRD89", + "PCIE_FAN2_R_0", + "PCIE_EE4BEG1_4", + "PCIE_EE4A3_2", + "PCIE_TOP_PL2DIRECTEDLSTATE4", + "PCIE_WW2A1_4", + "PCIE_NW4A3_3", + "PCIE_SE4C0_0", + "PCIE_LOGIC_OUTS_B18_L_0", + "PCIE_TOP_DBGVECA21", + "PCIE_LOGIC_OUTS_B12_R_2", + "PCIE_TOP_MIMRXRDATA25", + "PCIE_TOP_CFGERRTLPCPLHEADER38", + "PCIE_IMUX20_L_1", + "PCIE_EE4B0_4", + "PCIE_IMUX27_L_2", + "PCIE_ER1BEG0_3", + "PCIE_SW2A1_4", + "PCIE_SW4A1_2", + "PCIE_SW4A2_3", + "PCIE_IMUX22_R_0", + "PCIE_IMUX18_R_3", + "PCIE_IMUX43_R_2", + "PCIE_EE4C0_1", + "PCIE_IMUX40_L_1", + "PCIE_TOP_LL2SENDENTERL23", + "PCIE_EE4BEG0_2", + "PCIE_TOP_CFGMGMTDO29", + "PCIE_FAN4_R_0", + "PCIE_CLK1_L_3", + "PCIE_BYP7_R_0", + "PCIE_EE2BEG0_1", + "PCIE_LOGIC_OUTS_B21_R_3", + "PCIE_SW2A1_3", + "PCIE_WW4B2_2", + "PCIE_FAN0_R_2", + "PCIE_IMUX24_L_2", + "PCIE_TOP_TRNTDLLPDATA27", + "PCIE_NE4BEG2_2", + "PCIE_LOGIC_OUTS_B23_L_2", + "PCIE_SW4END3_2", + "PCIE_LH4_4", + "PCIE_BLOCK_OUTS_B3_R_4", + "PCIE_NW4END2_4", + "PCIE_EE2A0_4", + "PCIE_TOP_MIMRXRDATA32", + "PCIE_SE2A1_4", + "PCIE_TOP_CFGMGMTDO20", + "PCIE_FAN1_R_0", + "PCIE_LOGIC_OUTS_B3_L_2", + "PCIE_LOGIC_OUTS_B3_R_4", + "PCIE_SE4BEG2_0", + "PCIE_TOP_TRNRDLLPDATA53", + "PCIE_IMUX1_L_4", + "PCIE_TOP_CFGPCIELINKSTATE1", + "PCIE_TOP_PIPERX4DATA3", + "PCIE_SE4BEG3_3", + "PCIE_EE2A0_2", + "PCIE_IMUX11_R_4", + "PCIE_TOP_CFGERRTLPCPLHEADER26", + "PCIE_WW4B1_4", + "PCIE_IMUX39_L_4", + "PCIE_WW4END2_2", + "PCIE_LH7_2", + "PCIE_TOP_DBGVECA11", + "PCIE_TOP_TRNRDLLPDATA48", + "PCIE_BYP1_L_0", + "PCIE_TOP_MIMRXRDATA21", + "PCIE_LH9_1", + "PCIE_WW4A2_0", + "PCIE_TOP_PIPERX4PHYSTATUS", + "PCIE_BYP4_L_2", + "PCIE_NW2A1_2", + "PCIE_TOP_CFGERRAERHEADERLOG7", + "PCIE_IMUX3_L_2", + "PCIE_SW4END2_4", + "PCIE_FAN3_L_3", + "PCIE_LOGIC_OUTS_B7_R_2", + "PCIE_TOP_MIMRXRADDR0", + "PCIE_CLK1_R_4", + "PCIE_BYP7_R_1", + "PCIE_TOP_TRNTD20", + "PCIE_IMUX2_L_4", + "PCIE_WW4END3_2", + "PCIE_NW4END0_4", + "PCIE_TOP_CFGDSN61", + "PCIE_FAN6_L_3", + "PCIE_TOP_CFGERRTLPCPLHEADER44", + "PCIE_IMUX43_L_3", + "PCIE_TOP_CFGDEVID1", + "PCIE_LOGIC_OUTS_B17_L_2", + "PCIE_LOGIC_OUTS_B8_L_4", + "PCIE_TOP_TRNRDLLPDATA35", + "PCIE_LOGIC_OUTS_B1_L_4", + "PCIE_CTRL1_R_3", + "PCIE_LOGIC_OUTS_B4_R_0", + "PCIE_WW4C0_3", + "PCIE_TOP_TRNRD67", + "PCIE_BYP0_R_2", + "PCIE_EE4B3_3", + "PCIE_LOGIC_OUTS_B21_L_4", + "PCIE_WW4A1_0", + "PCIE_BLOCK_OUTS_B1_L_2", + "PCIE_LOGIC_OUTS_B10_L_4", + "PCIE_FAN7_R_0", + "PCIE_TOP_MIMRXRDATA33", + "PCIE_ER1BEG2_1", + "PCIE_IMUX41_R_0", + "PCIE_IMUX38_R_4", + "PCIE_WW2A2_0", + "PCIE_FAN4_L_0", + "PCIE_NW4END0_3", + "PCIE_NW4END0_0", + "PCIE_TOP_PIPERX4DATA1", + "PCIE_TOP_DBGVECA10", + "PCIE_LOGIC_OUTS_B12_L_0", + "PCIE_LH8_2", + "PCIE_SW2A0_3", + "PCIE_NE2A1_1", + "PCIE_NW4A0_3", + "PCIE_NW4A3_4", + "PCIE_IMUX27_L_3", + "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED", + "PCIE_WR1END1_2", + "PCIE_LOGIC_OUTS_B14_L_4", + "PCIE_NW4END2_3", + "PCIE_IMUX3_L_4", + "PCIE_IMUX16_R_1", + "PCIE_IMUX42_R_3", + "PCIE_IMUX28_R_0", + "PCIE_IMUX5_L_4", + "PCIE_ER1BEG1_2", + "PCIE_FAN7_L_0", + "PCIE_EE4C0_3", + "PCIE_TOP_MIMRXRDATA54", + "PCIE_LH2_4", + "PCIE_LH1_0", + "PCIE_WL1END0_1", + "PCIE_EE2BEG3_0", + "PCIE_LOGIC_OUTS_B2_R_3", + "PCIE_TOP_TRNRDLLPDATA51", + "PCIE_IMUX23_L_3", + "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK", + "PCIE_LOGIC_OUTS_B16_L_3", + "PCIE_IMUX4_R_2", + "PCIE_FAN5_R_4", + "PCIE_LOGIC_OUTS_B13_R_3", + "PCIE_TOP_MIMRXRDATA23", + "PCIE_TOP_EDTBYPASS", + "PCIE_TOP_CFGDSN62", + "PCIE_LOGIC_OUTS_B19_R_3", + "PCIE_LOGIC_OUTS_B12_L_1", + "PCIE_EE2BEG3_2", + "PCIE_WW4C3_0", + "PCIE_TOP_CFGERRNORECOVERYN", + "PCIE_WW4B3_3", + "PCIE_NE2A3_2", + "PCIE_TOP_TRNTDLLPDATA21", + "PCIE_SW2A0_4", + "PCIE_SW4A1_3", + "PCIE_FAN3_R_0", + "PCIE_TOP_DRPDO15", + "PCIE_IMUX23_L_4", + "PCIE_NW4A2_4", + "PCIE_TOP_TRNRD97", + "PCIE_WW4C2_4", + "PCIE_TOP_CFGDEVID11", + "PCIE_WW4END3_1", + "PCIE_EE4C0_0", + "PCIE_IMUX8_R_2", + "PCIE_EE2BEG1_3", + "PCIE_TOP_CFGDEVID5", + "PCIE_EL1BEG1_3", + "PCIE_TOP_MIMRXWDATA21", + "PCIE_NE4BEG2_1", + "PCIE_TOP_TRNTDLLPDATA28", + "PCIE_EE4BEG3_0", + "PCIE_SW2A2_3", + "PCIE_LOGIC_OUTS_B7_R_4", + "PCIE_LOGIC_OUTS_B20_L_0", + "PCIE_TOP_MIMRXRDATA43", + "PCIE_IMUX5_L_0", + "PCIE_NW4END2_1", + "PCIE_EE4C1_1", + "PCIE_IMUX28_L_0", + "PCIE_TOP_DRPDO3", + "PCIE_IMUX39_R_4", + "PCIE_WL1END2_2", + "PCIE_IMUX30_R_3", + "PCIE_IMUX5_L_3", + "PCIE_TOP_DBGVECA17", + "PCIE_IMUX32_R_1", + "PCIE_FAN2_R_3", + "PCIE_EE4B1_0", + "PCIE_LOGIC_OUTS_B19_R_4", + "PCIE_BYP5_L_1", + "PCIE_IMUX19_R_4", + "PCIE_SE2A3_2", + "PCIE_TOP_TRNRD85", + "PCIE_EE4C2_4", + "PCIE_IMUX37_R_0", + "PCIE_TOP_CFGMGMTDO21", + "PCIE_TOP_CFGPMRCVENTERL23N", + "PCIE_TOP_MIMRXRDATA39", + "PCIE_SE4BEG2_1", + "PCIE_WW2END3_2", + "PCIE_TOP_TRNTD10", + "PCIE_WW2END2_0", + "PCIE_TOP_CFGERRAERHEADERLOG2", + "PCIE_LOGIC_OUTS_B9_R_1", + "PCIE_LOGIC_OUTS_B14_L_2", + "PCIE_IMUX1_R_2", + "PCIE_TOP_MIMRXRDATA27", + "PCIE_WR1END2_2", + "PCIE_EE4BEG2_0", + "PCIE_TOP_DRPDI9", + "PCIE_WW2END3_1", + "PCIE_IMUX2_R_0", + "PCIE_WR1END0_2", + "PCIE_BYP2_L_0", + "PCIE_IMUX45_R_2", + "PCIE_TOP_TRNTD26", + "PCIE_WR1END3_4", + "PCIE_FAN1_R_4", + "PCIE_TOP_CFGMGMTDO26", + "PCIE_TOP_CFGERRTLPCPLHEADER31", + "PCIE_WW4END3_0", + "PCIE_TOP_CFGERRTLPCPLHEADER36", + "PCIE_WW4C1_2", + "PCIE_TOP_LL2TFCINIT2SEQ", + "PCIE_MONITOR_P_2", + "PCIE_TOP_TRNRDLLPDATA45", + "PCIE_EE4B0_3", + "PCIE_TOP_MIMRXRDATA53", + "PCIE_NE2A0_4", + "PCIE_IMUX11_L_2", + "PCIE_IMUX41_L_3", + "PCIE_LOGIC_OUTS_B4_L_2", + "PCIE_LH7_0", + "PCIE_EE4B2_2", + "PCIE_IMUX8_L_4", + "PCIE_CLK1_L_0", + "PCIE_LOGIC_OUTS_B20_R_4", + "PCIE_IMUX21_L_0", + "PCIE_LOGIC_OUTS_B2_R_1", + "PCIE_IMUX31_L_2", + "PCIE_TOP_CFGMGMTDO22", + "PCIE_WR1END2_4", + "PCIE_EL1BEG3_4", + "PCIE_LOGIC_OUTS_B1_L_3", + "PCIE_BYP7_R_4", + "PCIE_LOGIC_OUTS_B11_L_2", + "PCIE_EE2BEG0_3", + "PCIE_IMUX28_L_3", + "PCIE_IMUX29_L_3", + "PCIE_TOP_TRNRD74", + "PCIE_LOGIC_OUTS_B18_R_1", + "PCIE_LOGIC_OUTS_B14_L_3", + "PCIE_TOP_TRNTDLLPSRCRDY", + "PCIE_SE4C0_4", + "PCIE_SE4BEG1_2", + "PCIE_LOGIC_OUTS_B18_L_4", + "PCIE_LH8_4", + "PCIE_IMUX8_R_3", + "PCIE_LOGIC_OUTS_B1_L_2", + "PCIE_SW4A1_0", + "PCIE_IMUX33_R_4", + "PCIE_IMUX19_R_1", + "PCIE_TOP_DRPADDR7", + "PCIE_BLOCK_OUTS_B3_L_3", + "PCIE_LOGIC_OUTS_B11_R_2", + "PCIE_IMUX12_L_2", + "PCIE_NW2A0_3", + "PCIE_ER1BEG3_2", + "PCIE_TOP_CFGVCTCVCMAP2", + "PCIE_IMUX45_L_3", + "PCIE_FAN7_L_1", + "PCIE_TOP_MIMRXRADDR2", + "PCIE_CLK0_R_2", + "PCIE_TOP_CFGERRAERHEADERLOG10", + "PCIE_IMUX28_L_4", + "PCIE_IMUX7_L_1", + "PCIE_IMUX40_R_3", + "PCIE_TOP_CFGERRAERHEADERLOG11", + "PCIE_NW4END1_2", + "PCIE_NE4BEG0_1", + "PCIE_WW4END1_3", + "PCIE_SE2A2_2", + "PCIE_IMUX13_R_1", + "PCIE_IMUX15_L_2", + "PCIE_BYP6_R_3", + "PCIE_TOP_MIMRXWDATA19", + "PCIE_LH12_1", + "PCIE_TOP_DBGVECA8", + "PCIE_NE4C0_2", + "PCIE_WW2END1_1", + "PCIE_FAN5_L_3", + "PCIE_LOGIC_OUTS_B3_R_2", + "PCIE_TOP_DRPDO14", + "PCIE_SW4END0_3", + "PCIE_SE4BEG0_1", + "PCIE_IMUX18_R_1", + "PCIE_BYP7_L_3", + "PCIE_LOGIC_OUTS_B9_L_4", + "PCIE_LOGIC_OUTS_B6_L_2", + "PCIE_CLK0_R_3", + "PCIE_TOP_DBGVECA4", + "PCIE_EL1BEG2_4", + "PCIE_NW4A1_0", + "PCIE_BYP0_L_3", + "PCIE_TOP_TRNTD29", + "PCIE_LOGIC_OUTS_B23_L_0", + "PCIE_BLOCK_OUTS_B2_L_2", + "PCIE_IMUX36_L_1", + "PCIE_IMUX28_R_2", + "PCIE_TOP_TRNTD9", + "PCIE_WW2END1_0", + "PCIE_IMUX38_L_1", + "PCIE_LOGIC_OUTS_B2_R_4", + "PCIE_LOGIC_OUTS_B14_R_2", + "PCIE_NE4BEG3_0", + "PCIE_IMUX38_L_3", + "PCIE_FAN6_R_0", + "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE", + "PCIE_EE4C1_3", + "PCIE_TOP_CFGTRANSACTIONTYPE", + "PCIE_NE2A3_3", + "PCIE_TOP_CFGMGMTDO28", + "PCIE_TOP_CFGDEVID0", + "PCIE_BYP4_R_2", + "PCIE_LOGIC_OUTS_B21_L_0", + "PCIE_NW4A1_4", + "PCIE_FAN0_L_0", + "PCIE_IMUX17_R_1", + "PCIE_IMUX45_L_2", + "PCIE_LOGIC_OUTS_B0_R_2", + "PCIE_FAN3_L_1", + "PCIE_TOP_TRNRD76", + "PCIE_TOP_CFGDEVID10", + "PCIE_TOP_MIMRXREN", + "PCIE_NE2A2_0", + "PCIE_SE2A0_3", + "PCIE_IMUX20_R_2", + "PCIE_LOGIC_OUTS_B3_L_0", + "PCIE_LOGIC_OUTS_B6_R_4", + "PCIE_LH11_1", + "PCIE_TOP_PIPERX0DATA4", + "PCIE_LOGIC_OUTS_B5_R_2", + "PCIE_LOGIC_OUTS_B16_R_3", + "PCIE_LOGIC_OUTS_B10_L_3", + "PCIE_WW2END1_2", + "PCIE_LOGIC_OUTS_B6_R_2", + "PCIE_WW4B0_0", + "PCIE_WW4A2_4", + "PCIE_BLOCK_OUTS_B3_R_1", + "PCIE_TOP_DRPDO12", + "PCIE_LOGIC_OUTS_B2_R_0", + "PCIE_LOGIC_OUTS_B3_R_3", + "PCIE_IMUX30_R_4", + "PCIE_LH1_2", + "PCIE_BYP5_R_4", + "PCIE_IMUX1_R_0", + "PCIE_LOGIC_OUTS_B4_R_2", + "PCIE_BYP3_L_4", + "PCIE_LH4_2", + "PCIE_IMUX41_R_1", + "PCIE_WW4A1_4", + "PCIE_LH3_1", + "PCIE_IMUX10_L_1", + "PCIE_IMUX6_L_4", + "PCIE_TOP_CFGTRANSACTIONADDR1", + "PCIE_TOP_CFGMGMTDO16", + "PCIE_WW2A1_1", + "PCIE_LOGIC_OUTS_B20_R_3", + "PCIE_WW4C2_0", + "PCIE_IMUX37_R_1", + "PCIE_IMUX0_R_4", + "PCIE_IMUX44_R_0", + "PCIE_TOP_CFGERRTLPCPLHEADER43", + "PCIE_CLK1_R_0", + "PCIE_NE2A0_1", + "PCIE_SE2A1_3", + "PCIE_IMUX17_R_2", + "PCIE_IMUX32_L_1", + "PCIE_LOGIC_OUTS_B9_R_0", + "PCIE_WL1END3_3", + "PCIE_BLOCK_OUTS_B0_L_4", + "PCIE_IMUX35_L_2", + "PCIE_LOGIC_OUTS_B0_L_2", + "PCIE_TOP_TRNRD70", + "PCIE_TOP_DBGVECA2", + "PCIE_TOP_CFGTRANSACTIONADDR4", + "PCIE_IMUX32_L_0", + "PCIE_LOGIC_OUTS_B0_R_1", + "PCIE_IMUX40_L_4", + "PCIE_NE2A1_0", + "PCIE_IMUX46_L_2", + "PCIE_TOP_TRNRD96", + "PCIE_NW4A0_2", + "PCIE_IMUX46_L_1", + "PCIE_NW4END3_0", + "PCIE_IMUX8_L_0", + "PCIE_IMUX7_L_0", + "PCIE_TOP_CFGERRAERHEADERLOG8", + "PCIE_LOGIC_OUTS_B21_R_0", + "PCIE_TOP_CFGVCTCVCMAP5", + "PCIE_TOP_MIMRXRDATA29", + "PCIE_TOP_TRNRD69", + "PCIE_ER1BEG2_4", + "PCIE_LOGIC_OUTS_B19_L_2", + "PCIE_TOP_DBGVECA6", + "PCIE_BYP5_R_1", + "PCIE_EE4C0_4", + "PCIE_NE2A2_1", + "PCIE_WW4END0_4", + "PCIE_IMUX34_L_2", + "PCIE_TOP_TRNRDLLPDATA57", + "PCIE_SE4C2_2", + "PCIE_TOP_MIMRXWDATA24", + "PCIE_ER1BEG3_1", + "PCIE_BLOCK_OUTS_B2_L_1", + "PCIE_FAN6_R_3", + "PCIE_TOP_TRNTD14", + "PCIE_NE4C0_0", + "PCIE_IMUX40_R_1", + "PCIE_LOGIC_OUTS_B1_R_1", + "PCIE_TOP_DRPDI0", + "PCIE_LOGIC_OUTS_B14_R_4", + "PCIE_IMUX15_L_3", + "PCIE_SE4C3_4", + "PCIE_TOP_DRPDO5", + "PCIE_IMUX6_L_2", + "PCIE_BYP0_L_2", + "PCIE_WW4B0_3", + "PCIE_LOGIC_OUTS_B22_R_1", + "PCIE_IMUX39_R_0", + "PCIE_BYP1_R_0", + "PCIE_TOP_TRNRD88", + "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN", + "PCIE_WW4END0_2", + "PCIE_LOGIC_OUTS_B17_L_4", + "PCIE_LOGIC_OUTS_B5_L_0", + "PCIE_IMUX47_L_3", + "PCIE_CTRL0_R_1", + "PCIE_NE4C3_1", + "PCIE_WL1END3_2", + "PCIE_LOGIC_OUTS_B15_R_0", + "PCIE_LOGIC_OUTS_B8_R_3", + "PCIE_MONITOR_P_1", + "PCIE_IMUX35_R_4", + "PCIE_TOP_MIMRXWDATA17", + "PCIE_SW4A3_4", + "PCIE_TOP_TRNRD75", + "PCIE_NW2A2_0", + "PCIE_LOGIC_OUTS_B15_L_4", + "PCIE_TOP_MIMRXWDATA31", + "PCIE_LOGIC_OUTS_B12_R_4", + "PCIE_SE2A1_0", + "PCIE_NE2A0_3", + "PCIE_ER1BEG1_1", + "PCIE_BYP4_R_3", + "PCIE_IMUX18_R_0", + "PCIE_IMUX11_L_4", + "PCIE_IMUX36_R_4", + "PCIE_IMUX45_R_3", + "PCIE_LOGIC_OUTS_B8_R_4", + "PCIE_ER1BEG3_4", + "PCIE_TOP_MIMRXWDATA7", + "PCIE_SW4END3_0", + "PCIE_NE4BEG0_2", + "PCIE_LOGIC_OUTS_B6_L_0", + "PCIE_IMUX29_L_0", + "PCIE_NE2A3_1", + "PCIE_CLK0_L_3", + "PCIE_IMUX6_R_1", + "PCIE_IMUX4_R_3", + "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE", + "PCIE_LOGIC_OUTS_B12_L_4", + "PCIE_EE4BEG1_3", + "PCIE_IMUX35_R_3", + "PCIE_EL1BEG2_2", + "PCIE_TOP_DBGVECB10", + "PCIE_LH2_0", + "PCIE_FAN5_L_1", + "PCIE_LH12_3", + "PCIE_LOGIC_OUTS_B7_R_3", + "PCIE_TOP_MIMRXWDATA5", + "PCIE_IMUX44_L_4", + "PCIE_TOP_CFGERRTLPCPLHEADER30", + "PCIE_IMUX30_R_1", + "PCIE_IMUX13_L_4", + "PCIE_BYP1_R_3" + ], + "tile_type": "PCIE_TOP", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_RIOB33.json b/artix7/tile_type_RIOB33.json index 276fcb6..c862f7e 100644 --- a/artix7/tile_type_RIOB33.json +++ b/artix7/tile_type_RIOB33.json @@ -1,408 +1,408 @@ { - "wires": [ - "RIOB_WR1END3_0", - "RIOB_SW2A3_0", - "RIOB_LH6_0", - "RIOB_WL1END0_1", - "RIOB_EE4C2_1", - "RIOB_WW4END2_0", - "RIOB_NE4BEG2_1", - "RIOB_SW4A3_0", - "RIOB_NE4C2_0", - "RIOB_WW4A1_1", - "IOB_PADOUT1", - "RIOB_NE2A1_1", - "RIOB_SW4A1_1", - "IOB_IBUF_DISABLE1", - "RIOB_EE4BEG0_0", - "RIOB_NE4BEG3_1", - "RIOB_WW4B3_0", - "RIOB_EE2BEG0_1", - "RIOB_WL1END3_1", - "IOB_KEEPER_INT_EN_1", - "RIOB_EE4A3_0", - "RIOB_WW4END0_0", - "RIOB_WL1END2_0", - "RIOB_WW4B2_1", - "RIOB_WW2A0_1", - "RIOB_SW4END2_0", - "RIOB_SE4BEG0_1", - "RIOB_SW4A0_1", - "RIOB_WW2A1_1", - "RIOB_WL1END0_0", - "IOB_DIFFI_IN1", - "RIOB_WW4C0_0", - "RIOB_LH1_0", - "RIOB_LH8_1", - "RIOB_NE2A0_0", - "RIOB_NE4BEG2_0", - "RIOB_EE2BEG1_1", - "RIOB_LH12_1", - "RIOB_EE2BEG2_1", - "RIOB_EL1BEG3_0", - "IOB_DIFF_TERM_INT_EN_STUB", - "RIOB_NW4END2_1", - "RIOB_WW2A2_0", - "RIOB_EE2BEG3_1", - "RIOB_EE2A3_0", - "RIOB_NE4BEG0_0", - "RIOB_WW2END1_1", - "RIOB_EE4A1_0", - "IOB_T_OUT0", - "RIOB_SW4END1_0", - "RIOB_WW4END1_1", - "RIOB_WW2END0_0", - "RIOB_LH5_1", - "RIOB_NE4C0_1", - "IOB_O1", - "RIOB_SE4C0_0", - "RIOB_LH3_1", - "RIOB_EE2A0_1", - "IOB_IBUF0", - "RIOB_WW4B0_1", - "RIOB_SE4BEG3_1", - "RIOB_EE4C3_0", - "IOB_DIFFO_OUT1", - "RIOB_LH11_1", - "RIOB_ER1BEG2_0", - "RIOB_EE4B1_1", - "RIOB_WW4B1_1", - "RIOB_EE4BEG2_0", - "RIOB_NW4A1_1", - "RIOB_WW2A3_1", - "RIOB_EL1BEG1_1", - "RIOB_SW4END3_1", - "RIOB_ER1BEG1_1", - "RIOB_LH3_0", - "RIOB_SE2A2_1", - "RIOB_WW2END1_0", - "RIOB_WW4C2_1", - "RIOB_WW4END3_0", - "IOB_KEEPER_INT_EN_0", - "RIOB_EE4A1_1", - "RIOB_LH9_1", - "IOB_T_IN1", - "RIOB_NE2A2_0", - "RIOB_SE4C2_1", - "RIOB_EE4A3_1", - "RIOB_SW4A2_0", - "RIOB_WR1END1_0", - "RIOB_NW2A3_0", - "RIOB_WW2END2_1", - "RIOB_EL1BEG2_0", - "RIOB_SW4A2_1", - "LIOB_IN_TERM0", - "RIOB_NE4BEG1_0", - "RIOB_SW2A0_1", - "RIOB_NE4C1_1", - "RIOB_WW2A1_0", - "RIOB_EL1BEG0_1", - "RIOB_SW2A1_1", - "IOB_IBUF1", - "RIOB_EE2BEG3_0", - "RIOB_WW4END2_1", - "RIOB_ER1BEG0_0", - "RIOB_SE4C1_0", - "RIOB_SE4C3_0", - "RIOB_SE2A0_1", - "RIOB_EE4B2_0", - "LIOB_IN_TERM1", - "RIOB_NW4A0_0", - "RIOB_LH5_0", - "RIOB_NW4END1_0", - "RIOB_NW2A2_0", - "RIOB_EL1BEG3_1", - "RIOB_EE2BEG1_0", - "RIOB_ER1BEG3_1", - "RIOB_EL1BEG1_0", - "RIOB_SW2A0_0", - "RIOB_NW2A0_0", - "RIOB_NW4A2_0", - "RIOB_LH9_0", - "RIOB_WW4A1_0", - "RIOB_SW4A0_0", - "RIOB_NE4BEG1_1", - "RIOB_WW4C2_0", - "RIOB_WW4A0_0", - "RIOB_EE4B0_0", - "IOB_O_OUT1", - "IOB_O0", - "RIOB_SE4BEG2_1", - "RIOB_EE4C3_1", - "RIOB_EE4B0_1", - "RIOB_NW2A3_1", - "RIOB_EE4C0_1", - "RIOB_ER1BEG3_0", - "RIOB_WW2END2_0", - "RIOB_SW4END2_1", - "RIOB_NW4END3_1", - "RIOB_EL1BEG2_1", - "RIOB_LH2_1", - "IOB_DIFFO_OUT0", - "RIOB_LH11_0", - "RIOB_MONITOR_N", - "RIOB_WW4B3_1", - "RIOB_ER1BEG1_0", - "RIOB_SE2A0_0", - "RIOB_SE2A2_0", - "RIOB_SW2A2_1", - "RIOB_SE4BEG1_0", - "RIOB_NW4A3_1", - "RIOB_WR1END0_0", - "IOB_T0", - "RIOB_EE4BEG3_1", - "RIOB_EE4C0_0", - "RIOB_SE4BEG3_0", - "RIOB_LH10_1", - "IOB_PADOUT0", - "RIOB_SE4BEG1_1", - "RIOB_EL1BEG0_0", - "RIOB_EE2BEG2_0", - "IOB_O_IN0", - "RIOB_SW4END0_0", - "RIOB_LH7_0", - "RIOB_WW2END3_1", - "RIOB_SW4A1_0", - "RIOB_NE4C3_1", - "IOB_T1", - "RIOB_WW4A0_1", - "RIOB_SW4END0_1", - "RIOB_WW4C1_1", - "RIOB_MONITOR_P", - "RIOB_SE4BEG0_0", - "RIOB_WW4A2_1", - "RIOB_EE2A3_1", - "IOB_DIFFO_IN0", - "RIOB_NW4A1_0", - "RIOB_LH10_0", - "RIOB_LH8_0", - "RIOB_NW4END0_1", - "RIOB_NW4A2_1", - "RIOB_SE4C2_0", - "IOB_T_IN0", - "RIOB_SE4C3_1", - "RIOB_EE4BEG3_0", - "RIOB_NW2A1_0", - "RIOB_EE2A1_1", - "RIOB_EE4C1_1", - "RIOB_EE4BEG0_1", - "RIOB_WW4A3_0", - "RIOB_WR1END1_1", - "RIOB_NW4END0_0", - "RIOB_EE4A2_1", - "RIOB_LH1_1", - "RIOB_EE4BEG1_1", - "IOB_DIFFO_IN1", - "RIOB_WW4A2_0", - "RIOB_EE4A0_1", - "IOB_DIFFI_IN0", - "RIOB_WR1END2_1", - "RIOB_EE2BEG0_0", - "RIOB_NE4C0_0", - "RIOB_LH4_0", - "RIOB_NE4C3_0", - "RIOB_EE2A0_0", - "RIOB_ER1BEG2_1", - "RIOB_ER1BEG0_1", - "IOB_O_OUT0", - "RIOB_WW4B0_0", - "RIOB_EE4BEG1_0", - "IOB_PU_INT_EN_0", - "RIOB_NE2A3_1", - "IOB_PD_INT_EN_1", - "RIOB_SE4C1_1", - "RIOB_NW4END3_0", - "RIOB_SW4A3_1", - "RIOB_WL1END3_0", - "RIOB_SW2A1_0", - "RIOB_NW4A3_0", - "RIOB_EE2A2_1", - "RIOB_LH6_1", - "RIOB_WR1END0_1", - "RIOB_NE4C2_1", - "RIOB_EE4B1_0", - "RIOB_LH12_0", - "RIOB_SE4BEG2_0", - "RIOB_WR1END2_0", - "RIOB_EE4BEG2_1", - "RIOB_EE4B2_1", - "RIOB_WW2END0_1", - "RIOB_SE2A1_1", - "IOB_O_IN1", - "IOB_T_OUT1", - "RIOB_SE2A1_0", - "RIOB_WL1END2_1", - "RIOB_EE4C1_0", - "RIOB_WW4A3_1", - "RIOB_EE4A0_0", - "RIOB_NE2A3_0", - "RIOB_WW4C3_1", - "RIOB_EE4C2_0", - "RIOB_NW2A1_1", - "IOB_DIFF_TERM_INT_EN", - "RIOB_SW4END1_1", - "RIOB_NW4END1_1", - "RIOB_WL1END1_0", - "RIOB_NW4A0_1", - "RIOB_NE4C1_0", - "RIOB_WW2A2_1", - "IOB_PU_INT_EN_1", - "RIOB_WW2END3_0", - "RIOB_SE2A3_0", - "RIOB_WW4C1_0", - "RIOB_EE2A2_0", - "RIOB_WW4END1_0", - "RIOB_NE2A1_0", - "RIOB_LH2_0", - "RIOB_SE2A3_1", - "RIOB_SE4C0_1", - "RIOB_LH7_1", - "RIOB_EE4B3_0", - "RIOB_WW4END0_1", - "RIOB_LH4_1", - "RIOB_NE4BEG0_1", - "IOB_PD_INT_EN_0", - "RIOB_SW2A2_0", - "RIOB_WW4B2_0", - "RIOB_WR1END3_1", - "RIOB_NE2A0_1", - "RIOB_SW4END3_0", - "IOB_IBUF_DISABLE0", - "RIOB_NW2A0_1", - "RIOB_WW2A0_0", - "RIOB_WL1END1_1", - "RIOB_NE2A2_1", - "RIOB_WW4C0_1", - "RIOB_EE4A2_0", - "RIOB_NE4BEG3_0", - "RIOB_SW2A3_1", - "RIOB_WW4B1_0", - "RIOB_NW4END2_0", - "RIOB_WW2A3_0", - "RIOB_EE2A1_0", - "RIOB_EE4B3_1", - "RIOB_NW2A2_1", - "RIOB_WW4END3_1", - "RIOB_WW4C3_0" - ], - "sites": [ - { - "prefix": "IOB", - "y_coord": 0, - "type": "IOB33S", - "site_pins": { - "O": "IOB_O1", - "O_IN": "IOB_O_IN1", - "O_OUT": "IOB_O_OUT1", - "DIFFI_IN": "IOB_DIFFI_IN1", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_0", - "PADOUT": "IOB_PADOUT1", - "T_IN": "IOB_T_IN1", - "PU_INT_EN": "IOB_PU_INT_EN_0", - "IBUFDISABLE": "IOB_IBUF_DISABLE1", - "I": "IOB_IBUF1", - "DIFFO_OUT": "IOB_DIFFO_OUT1", - "T": "IOB_T1", - "T_OUT": "IOB_T_OUT1", - "INTERMDISABLE": "LIOB_IN_TERM1", - "PD_INT_EN": "IOB_PD_INT_EN_0", - "DIFFO_IN": "IOB_DIFFO_IN1", - "DIFF_TERM_INT_EN": "IOB_DIFF_TERM_INT_EN" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IOB", - "y_coord": 1, - "type": "IOB33M", - "site_pins": { - "O": "IOB_O0", - "O_IN": null, - "O_OUT": "IOB_O_OUT0", - "DIFFI_IN": "IOB_DIFFI_IN0", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "PADOUT": "IOB_PADOUT0", - "T_IN": null, - "PU_INT_EN": "IOB_PU_INT_EN_1", - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "I": "IOB_IBUF0", - "DIFFO_OUT": "IOB_DIFFO_OUT0", - "T": "IOB_T0", - "T_OUT": "IOB_T_OUT0", - "INTERMDISABLE": "LIOB_IN_TERM0", - "PD_INT_EN": "IOB_PD_INT_EN_1", - "DIFFO_IN": null, - "DIFF_TERM_INT_EN": null - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "RIOB33.IOB_PADOUT1->IOB_DIFFI_IN0": { - "can_invert": "0", - "dst_wire": "IOB_DIFFI_IN0", - "is_directional": "1", - "src_wire": "IOB_PADOUT1", - "is_pseudo": "0" - }, - "RIOB33.IOB_O0->>IOB_O_OUT0": { - "can_invert": "0", - "dst_wire": "IOB_O_OUT0", - "is_directional": "1", - "src_wire": "IOB_O0", - "is_pseudo": "1" - }, - "RIOB33.IOB_T0->>IOB_T_OUT0": { - "can_invert": "0", - "dst_wire": "IOB_T_OUT0", - "is_directional": "1", - "src_wire": "IOB_T0", - "is_pseudo": "1" - }, - "RIOB33.IOB_PADOUT0->IOB_DIFFI_IN1": { - "can_invert": "0", - "dst_wire": "IOB_DIFFI_IN1", - "is_directional": "1", - "src_wire": "IOB_PADOUT0", - "is_pseudo": "0" - }, "RIOB33.IOB_PADOUT0->RIOB_MONITOR_P": { - "can_invert": "0", - "dst_wire": "RIOB_MONITOR_P", - "is_directional": "1", "src_wire": "IOB_PADOUT0", - "is_pseudo": "0" - }, - "RIOB33.IOB_O_OUT0->IOB_O_IN1": { "can_invert": "0", - "dst_wire": "IOB_O_IN1", "is_directional": "1", - "src_wire": "IOB_O_OUT0", - "is_pseudo": "0" - }, - "RIOB33.IOB_T_OUT0->IOB_T_IN1": { - "can_invert": "0", - "dst_wire": "IOB_T_IN1", - "is_directional": "1", - "src_wire": "IOB_T_OUT0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "RIOB_MONITOR_P" }, "RIOB33.IOB_PADOUT1->RIOB_MONITOR_N": { - "can_invert": "0", - "dst_wire": "RIOB_MONITOR_N", - "is_directional": "1", "src_wire": "IOB_PADOUT1", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOB_MONITOR_N" + }, + "RIOB33.IOB_O_OUT0->IOB_O_IN1": { + "src_wire": "IOB_O_OUT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOB_O_IN1" + }, + "RIOB33.IOB_PADOUT0->IOB_DIFFI_IN1": { + "src_wire": "IOB_PADOUT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFI_IN1" + }, + "RIOB33.IOB_T_OUT0->IOB_T_IN1": { + "src_wire": "IOB_T_OUT0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOB_T_IN1" }, "RIOB33.IOB_DIFFO_OUT0->IOB_DIFFO_IN1": { - "can_invert": "0", - "dst_wire": "IOB_DIFFO_IN1", - "is_directional": "1", "src_wire": "IOB_DIFFO_OUT0", - "is_pseudo": "0" + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFO_IN1" + }, + "RIOB33.IOB_T0->>IOB_T_OUT0": { + "src_wire": "IOB_T0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOB_T_OUT0" + }, + "RIOB33.IOB_O0->>IOB_O_OUT0": { + "src_wire": "IOB_O0", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOB_O_OUT0" + }, + "RIOB33.IOB_PADOUT1->IOB_DIFFI_IN0": { + "src_wire": "IOB_PADOUT1", + "can_invert": "0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOB_DIFFI_IN0" } }, - "tile_type": "RIOB33" + "wires": [ + "RIOB_WW2END3_1", + "IOB_DIFFO_OUT0", + "RIOB_SE4C3_1", + "RIOB_WR1END1_1", + "RIOB_EE4B1_1", + "RIOB_EL1BEG3_1", + "IOB_DIFFI_IN1", + "RIOB_NE2A3_0", + "RIOB_EE4A2_1", + "RIOB_WR1END2_0", + "RIOB_SW2A2_0", + "RIOB_NW4A1_1", + "RIOB_WR1END3_1", + "RIOB_EL1BEG1_1", + "RIOB_WL1END3_0", + "RIOB_WW4A2_1", + "IOB_DIFFO_IN1", + "RIOB_NE4C2_1", + "RIOB_NW2A3_1", + "RIOB_WW4C0_1", + "RIOB_WW4C3_1", + "IOB_O_IN1", + "RIOB_WW4B1_1", + "RIOB_WW2A3_1", + "RIOB_NE4C1_0", + "RIOB_SW4END0_1", + "RIOB_EE2BEG3_0", + "RIOB_NE4C0_0", + "RIOB_EE4C3_0", + "RIOB_SE4C1_1", + "RIOB_SW4END3_1", + "RIOB_EE4C2_1", + "RIOB_NW4END3_0", + "IOB_IBUF0", + "RIOB_EE4BEG0_0", + "RIOB_WL1END0_1", + "RIOB_NE2A3_1", + "RIOB_SE4C0_1", + "RIOB_SE4BEG0_1", + "RIOB_ER1BEG2_0", + "IOB_IBUF_DISABLE0", + "RIOB_SE2A0_1", + "RIOB_WW4END0_1", + "RIOB_SW4END1_0", + "RIOB_SE2A0_0", + "RIOB_SW2A1_1", + "RIOB_WW4B1_0", + "RIOB_EE2BEG3_1", + "RIOB_SE4C0_0", + "RIOB_NW4END1_0", + "RIOB_NE4BEG1_1", + "RIOB_LH1_0", + "RIOB_SW2A2_1", + "RIOB_WW4A1_0", + "RIOB_SE4BEG2_0", + "RIOB_EE4A0_1", + "RIOB_NE2A1_0", + "RIOB_LH6_1", + "RIOB_NE2A1_1", + "RIOB_WR1END2_1", + "RIOB_EE4B2_1", + "RIOB_EE4A3_1", + "RIOB_EE2A1_1", + "RIOB_NE4BEG3_1", + "RIOB_NE4C2_0", + "RIOB_NE2A0_0", + "RIOB_WW4C1_0", + "RIOB_NW4A2_0", + "RIOB_WW2A3_0", + "RIOB_SW4A3_0", + "RIOB_EE4BEG3_0", + "RIOB_WW4B0_1", + "RIOB_EE4C1_0", + "RIOB_ER1BEG3_0", + "IOB_O_OUT0", + "RIOB_NW4END2_0", + "RIOB_WL1END3_1", + "RIOB_SE4BEG0_0", + "RIOB_WW4B0_0", + "IOB_DIFFO_OUT1", + "IOB_DIFF_TERM_INT_EN_STUB", + "RIOB_SW4A1_0", + "RIOB_WW4A2_0", + "RIOB_EL1BEG0_0", + "RIOB_EE2BEG0_1", + "RIOB_SE4BEG1_1", + "RIOB_NE2A2_1", + "IOB_IBUF1", + "RIOB_SW4A2_0", + "RIOB_ER1BEG1_0", + "RIOB_SW2A0_0", + "RIOB_EE2A2_0", + "RIOB_NE4C3_0", + "RIOB_EE2A2_1", + "RIOB_ER1BEG2_1", + "RIOB_WW4END2_0", + "RIOB_LH4_0", + "RIOB_SW4END2_1", + "RIOB_EE4A1_0", + "RIOB_SE4BEG3_0", + "RIOB_SW2A0_1", + "RIOB_LH8_0", + "RIOB_EE4BEG1_0", + "IOB_DIFF_TERM_INT_EN", + "RIOB_WW2A1_0", + "RIOB_NE4BEG0_0", + "RIOB_SE4C2_1", + "RIOB_WW4C1_1", + "RIOB_NE4C0_1", + "RIOB_WW2END0_0", + "RIOB_ER1BEG3_1", + "RIOB_NW4END3_1", + "RIOB_NE4C1_1", + "RIOB_SE4C1_0", + "RIOB_EE4A3_0", + "RIOB_SW4END1_1", + "RIOB_WW4B3_0", + "RIOB_SE2A3_1", + "RIOB_WW2A1_1", + "RIOB_NW2A2_0", + "RIOB_EE4C3_1", + "IOB_PD_INT_EN_0", + "RIOB_SE2A3_0", + "RIOB_WW2A0_1", + "RIOB_NW2A2_1", + "RIOB_SE2A2_0", + "RIOB_NE4BEG1_0", + "IOB_KEEPER_INT_EN_0", + "RIOB_EL1BEG2_0", + "RIOB_NW2A0_1", + "LIOB_IN_TERM0", + "RIOB_EE4B3_1", + "RIOB_EE2BEG0_0", + "RIOB_NW4A0_0", + "RIOB_EE2A0_0", + "RIOB_EE2A3_1", + "RIOB_WW2END3_0", + "RIOB_NE4BEG0_1", + "RIOB_NW2A1_0", + "RIOB_ER1BEG1_1", + "RIOB_NW2A0_0", + "RIOB_SE4BEG2_1", + "RIOB_SW2A3_1", + "RIOB_EE4A1_1", + "RIOB_LH2_0", + "RIOB_EE2BEG1_0", + "RIOB_LH10_0", + "RIOB_NE4C3_1", + "RIOB_WR1END3_0", + "RIOB_SW4END0_0", + "RIOB_SE2A1_0", + "IOB_T_IN1", + "RIOB_LH8_1", + "IOB_KEEPER_INT_EN_1", + "RIOB_SE4C3_0", + "RIOB_NE2A0_1", + "RIOB_LH10_1", + "RIOB_SE4BEG3_1", + "RIOB_MONITOR_N", + "RIOB_WR1END0_1", + "RIOB_NW2A1_1", + "RIOB_WW4C0_0", + "RIOB_WW2A0_0", + "RIOB_NE4BEG2_1", + "RIOB_WW4A1_1", + "RIOB_EE4B0_0", + "IOB_T_OUT0", + "RIOB_WW4A0_0", + "RIOB_LH3_0", + "IOB_DIFFI_IN0", + "RIOB_SW4A3_1", + "RIOB_WW4C2_0", + "RIOB_WW2A2_0", + "RIOB_WW4END0_0", + "RIOB_WL1END1_1", + "RIOB_EE2BEG2_1", + "RIOB_EE4C0_1", + "RIOB_EE4B2_0", + "RIOB_WL1END2_0", + "RIOB_WL1END2_1", + "RIOB_WW2END2_0", + "RIOB_WW4END3_0", + "RIOB_WW4B2_1", + "IOB_PU_INT_EN_0", + "RIOB_MONITOR_P", + "IOB_T1", + "RIOB_WW4C2_1", + "RIOB_WW4B2_0", + "RIOB_LH7_1", + "RIOB_WW4A0_1", + "RIOB_EE2A3_0", + "RIOB_SE4BEG1_0", + "RIOB_EE2BEG2_0", + "RIOB_WW4A3_1", + "RIOB_SW4A2_1", + "RIOB_EE4BEG1_1", + "RIOB_NW4END0_1", + "RIOB_SW4END3_0", + "RIOB_LH5_1", + "RIOB_NW4END0_0", + "RIOB_EE2BEG1_1", + "IOB_IBUF_DISABLE1", + "RIOB_NW4A3_0", + "RIOB_EL1BEG0_1", + "RIOB_WW4END3_1", + "RIOB_NW4A1_0", + "IOB_O_OUT1", + "RIOB_NW4A0_1", + "RIOB_LH9_0", + "RIOB_EE4C2_0", + "RIOB_EE4BEG3_1", + "RIOB_NE4BEG2_0", + "RIOB_WW4END1_1", + "RIOB_EE4C1_1", + "RIOB_SE4C2_0", + "RIOB_NW4END2_1", + "IOB_O0", + "RIOB_EL1BEG2_1", + "IOB_T0", + "RIOB_EE4BEG2_1", + "RIOB_LH6_0", + "RIOB_WW2END2_1", + "RIOB_EE4B0_1", + "RIOB_LH9_1", + "RIOB_WW4A3_0", + "RIOB_ER1BEG0_0", + "RIOB_EE2A1_0", + "RIOB_NW4END1_1", + "IOB_PD_INT_EN_1", + "RIOB_SE2A1_1", + "LIOB_IN_TERM1", + "IOB_T_IN0", + "RIOB_NE4BEG3_0", + "RIOB_EL1BEG1_0", + "RIOB_WW2END1_0", + "RIOB_EE4BEG2_0", + "RIOB_SW4END2_0", + "RIOB_LH12_1", + "IOB_DIFFO_IN0", + "RIOB_WR1END1_0", + "IOB_PU_INT_EN_1", + "RIOB_NE2A2_0", + "RIOB_EL1BEG3_0", + "RIOB_EE4A2_0", + "IOB_O_IN0", + "RIOB_SW2A1_0", + "RIOB_WW4C3_0", + "RIOB_LH1_1", + "RIOB_ER1BEG0_1", + "IOB_PADOUT0", + "RIOB_WL1END0_0", + "RIOB_WW2A2_1", + "RIOB_WW4END1_0", + "RIOB_SW4A0_0", + "RIOB_LH5_0", + "RIOB_SE2A2_1", + "RIOB_EE4B3_0", + "RIOB_SW2A3_0", + "RIOB_SW4A1_1", + "RIOB_LH12_0", + "RIOB_WW4END2_1", + "IOB_O1", + "RIOB_EE2A0_1", + "RIOB_LH4_1", + "RIOB_WW2END1_1", + "RIOB_WL1END1_0", + "RIOB_LH3_1", + "RIOB_NW4A3_1", + "RIOB_LH11_1", + "RIOB_WW2END0_1", + "RIOB_EE4C0_0", + "RIOB_WR1END0_0", + "RIOB_LH11_0", + "RIOB_EE4BEG0_1", + "RIOB_NW4A2_1", + "RIOB_SW4A0_1", + "RIOB_LH7_0", + "RIOB_EE4B1_0", + "RIOB_WW4B3_1", + "RIOB_EE4A0_0", + "RIOB_NW2A3_0", + "RIOB_LH2_1", + "IOB_PADOUT1", + "IOB_T_OUT1" + ], + "tile_type": "RIOB33", + "sites": [ + { + "site_pins": { + "I": "IOB_IBUF1", + "DIFFO_OUT": "IOB_DIFFO_OUT1", + "INTERMDISABLE": "LIOB_IN_TERM1", + "DIFF_TERM_INT_EN": "IOB_DIFF_TERM_INT_EN", + "T": "IOB_T1", + "O_IN": "IOB_O_IN1", + "DIFFO_IN": "IOB_DIFFO_IN1", + "DIFFI_IN": "IOB_DIFFI_IN1", + "PD_INT_EN": "IOB_PD_INT_EN_0", + "IBUFDISABLE": "IOB_IBUF_DISABLE1", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_0", + "T_OUT": "IOB_T_OUT1", + "PADOUT": "IOB_PADOUT1", + "PU_INT_EN": "IOB_PU_INT_EN_0", + "O_OUT": "IOB_O_OUT1", + "O": "IOB_O1", + "T_IN": "IOB_T_IN1" + }, + "type": "IOB33S", + "prefix": "IOB", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "I": "IOB_IBUF0", + "DIFFO_OUT": "IOB_DIFFO_OUT0", + "INTERMDISABLE": "LIOB_IN_TERM0", + "DIFF_TERM_INT_EN": null, + "T": "IOB_T0", + "O_IN": null, + "DIFFO_IN": null, + "DIFFI_IN": "IOB_DIFFI_IN0", + "PD_INT_EN": "IOB_PD_INT_EN_1", + "IBUFDISABLE": "IOB_IBUF_DISABLE0", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", + "T_OUT": "IOB_T_OUT0", + "PADOUT": "IOB_PADOUT0", + "PU_INT_EN": "IOB_PU_INT_EN_1", + "O_OUT": "IOB_O_OUT0", + "O": "IOB_O0", + "T_IN": null + }, + "type": "IOB33M", + "prefix": "IOB", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_RIOB33_SING.json b/artix7/tile_type_RIOB33_SING.json index e4b6b00..5172239 100644 --- a/artix7/tile_type_RIOB33_SING.json +++ b/artix7/tile_type_RIOB33_SING.json @@ -1,175 +1,175 @@ { + "pips": {}, "wires": [ - "RIOB_WR1END0_0", - "RIOB_WR1END3_0", - "IOB_T0", - "RIOB_SW2A3_0", - "RIOB_LH6_0", - "RIOB_EE4C0_0", - "RIOB_SE4BEG3_0", - "RIOB_WW4END2_0", - "IOB_PADOUT0", - "RIOB_EL1BEG0_0", - "RIOB_SW4A3_0", - "RIOB_EE2BEG2_0", - "RIOB_NE4C2_0", - "IOB_O_IN0", - "RIOB_SW4END0_0", - "RIOB_LH7_0", - "RIOB_SW4A1_0", - "RIOB_EE4BEG0_0", - "RIOB_WW4B3_0", - "RIOB_SE4BEG0_0", - "IOB_DIFFO_IN0", - "RIOB_NW4A1_0", - "RIOB_LH10_0", - "RIOB_LH8_0", - "IOB_KEEPER_INT_EN_1", - "RIOB_EE4A3_0", - "RIOB_SE4C2_0", - "IOB_T_IN0", - "RIOB_EE4BEG3_0", - "RIOB_WW4END0_0", - "RIOB_WL1END2_0", - "RIOB_NW2A1_0", - "RIOB_SW4END2_0", - "RIOB_WL1END0_0", - "RIOB_WW4A3_0", - "RIOB_WW4C0_0", - "RIOB_NW4END0_0", - "RIOB_LH1_0", - "RIOB_NE2A0_0", - "RIOB_NE4BEG2_0", - "RIOB_WW4A2_0", - "RIOB_EL1BEG3_0", - "IOB_DIFF_TERM_INT_EN_STUB", - "IOB_DIFFI_IN0", - "RIOB_EE2BEG0_0", - "RIOB_WW2A2_0", - "RIOB_NE4C0_0", - "RIOB_NE4C3_0", - "RIOB_LH4_0", - "RIOB_EE2A3_0", - "RIOB_NE4BEG0_0", - "RIOB_EE4A1_0", - "IOB_T_OUT0", - "RIOB_SW4END1_0", "RIOB_EE2A0_0", - "RIOB_WW2END0_0", - "RIOB_SE4C0_0", - "IOB_O_OUT0", - "IOB_IBUF0", - "RIOB_WW4B0_0", - "RIOB_EE4C3_0", - "RIOB_EE4BEG1_0", - "RIOB_ER1BEG2_0", - "RIOB_EE4BEG2_0", - "IOB_PD_INT_EN_1", - "RIOB_NW4END3_0", - "RIOB_WL1END3_0", - "RIOB_SW2A1_0", - "RIOB_NW4A3_0", - "RIOB_LH3_0", - "RIOB_WW2END1_0", - "RIOB_EE4B1_0", - "RIOB_WW4END3_0", - "RIOB_LH12_0", - "RIOB_SE4BEG2_0", - "RIOB_NE2A2_0", - "RIOB_WR1END2_0", - "RIOB_SW4A2_0", - "RIOB_WR1END1_0", - "RIOB_NW2A3_0", - "RIOB_EL1BEG2_0", - "LIOB_IN_TERM0", - "RIOB_NE4BEG1_0", - "RIOB_SE2A1_0", - "RIOB_EE4C1_0", - "RIOB_WW2A1_0", - "RIOB_EE4A0_0", - "RIOB_EE2BEG3_0", - "RIOB_NE2A3_0", - "RIOB_ER1BEG0_0", - "RIOB_EE4C2_0", - "RIOB_SE4C1_0", - "RIOB_SE4C3_0", - "RIOB_WL1END1_0", - "RIOB_EE4B2_0", - "RIOB_NE4C1_0", - "IOB_PU_INT_EN_1", - "RIOB_NW4A0_0", + "IOB_DIFFO_OUT0", "RIOB_WW2END3_0", - "RIOB_SE2A3_0", - "RIOB_LH5_0", - "RIOB_NW4END1_0", - "RIOB_WW4C1_0", - "RIOB_EE2A2_0", - "RIOB_WW4END1_0", - "RIOB_NE2A1_0", - "RIOB_NW2A2_0", + "RIOB_NW2A1_0", + "RIOB_NW2A0_0", "RIOB_LH2_0", "RIOB_EE2BEG1_0", - "RIOB_EE4B3_0", - "RIOB_EL1BEG1_0", - "RIOB_SW2A0_0", - "RIOB_NW2A0_0", - "RIOB_NW4A2_0", - "RIOB_LH9_0", - "RIOB_WW4A1_0", - "RIOB_SW4A0_0", - "RIOB_WW4C2_0", - "RIOB_WW4A0_0", - "RIOB_EE4B0_0", + "RIOB_LH10_0", + "RIOB_NE2A3_0", + "RIOB_WR1END3_0", "RIOB_SW2A2_0", - "RIOB_WW4B2_0", - "IOB_O0", - "RIOB_SW4END3_0", - "IOB_IBUF_DISABLE0", - "RIOB_ER1BEG3_0", - "RIOB_WW2END2_0", + "RIOB_WR1END2_0", + "RIOB_SW4END0_0", + "RIOB_SE2A1_0", + "IOB_KEEPER_INT_EN_1", + "RIOB_SE4C3_0", + "RIOB_WL1END3_0", + "RIOB_WW4C0_0", "RIOB_WW2A0_0", - "IOB_DIFFO_OUT0", - "RIOB_EE4A2_0", - "RIOB_NE4BEG3_0", - "RIOB_WW4B1_0", - "RIOB_LH11_0", - "RIOB_NW4END2_0", - "RIOB_WW2A3_0", - "RIOB_EE2A1_0", - "RIOB_ER1BEG1_0", - "RIOB_SE2A0_0", - "RIOB_SE2A2_0", + "RIOB_EE4B0_0", + "IOB_T_OUT0", + "RIOB_WW4A0_0", + "RIOB_LH3_0", + "IOB_DIFFI_IN0", + "RIOB_NE4C1_0", + "RIOB_WW4C2_0", + "RIOB_WW2A2_0", + "RIOB_WW4END0_0", + "RIOB_EE2BEG3_0", + "RIOB_NE4C0_0", + "RIOB_EE4C3_0", + "RIOB_NW4END3_0", + "RIOB_EE4B2_0", + "RIOB_WL1END2_0", + "IOB_IBUF0", + "RIOB_EE4BEG0_0", + "RIOB_WW2END2_0", + "RIOB_WW4END3_0", + "RIOB_ER1BEG2_0", + "IOB_IBUF_DISABLE0", + "RIOB_WW4B2_0", + "RIOB_EE2A3_0", "RIOB_SE4BEG1_0", - "RIOB_WW4C3_0" + "RIOB_EE2BEG2_0", + "RIOB_SW4END1_0", + "RIOB_SE2A0_0", + "RIOB_WW4B1_0", + "RIOB_SW4END3_0", + "RIOB_SE4C0_0", + "RIOB_NW4END0_0", + "RIOB_NW4END1_0", + "RIOB_LH1_0", + "RIOB_WW4A1_0", + "RIOB_SE4BEG2_0", + "RIOB_NE2A1_0", + "RIOB_NW4A3_0", + "RIOB_NW4A1_0", + "RIOB_LH9_0", + "RIOB_EE4C2_0", + "RIOB_NE4BEG2_0", + "RIOB_NE4C2_0", + "RIOB_SE4C2_0", + "RIOB_NE2A0_0", + "IOB_O0", + "RIOB_LH6_0", + "IOB_T0", + "RIOB_WW4C1_0", + "RIOB_NW4A2_0", + "RIOB_WW2A3_0", + "RIOB_SW4A3_0", + "RIOB_EE4BEG3_0", + "RIOB_EE4C1_0", + "RIOB_ER1BEG3_0", + "IOB_O_OUT0", + "RIOB_NW4END2_0", + "RIOB_WW4A3_0", + "RIOB_ER1BEG0_0", + "RIOB_SE4BEG0_0", + "RIOB_EE2A1_0", + "IOB_PD_INT_EN_1", + "RIOB_WW4B0_0", + "IOB_DIFF_TERM_INT_EN_STUB", + "RIOB_SW4A1_0", + "RIOB_WW4A2_0", + "RIOB_EL1BEG0_0", + "IOB_T_IN0", + "RIOB_NE4BEG3_0", + "RIOB_EL1BEG1_0", + "RIOB_WW2END1_0", + "RIOB_EE4BEG2_0", + "RIOB_SW4END2_0", + "RIOB_SW4A2_0", + "RIOB_ER1BEG1_0", + "RIOB_SW2A0_0", + "IOB_DIFFO_IN0", + "RIOB_EE2A2_0", + "RIOB_NE4C3_0", + "RIOB_WR1END1_0", + "IOB_PU_INT_EN_1", + "RIOB_NE2A2_0", + "RIOB_EL1BEG3_0", + "RIOB_EE4A2_0", + "IOB_O_IN0", + "RIOB_WW4END2_0", + "RIOB_SW2A1_0", + "RIOB_LH4_0", + "RIOB_WW4C3_0", + "RIOB_EE4A1_0", + "IOB_PADOUT0", + "RIOB_SE4BEG3_0", + "RIOB_WL1END0_0", + "RIOB_LH8_0", + "RIOB_EE4BEG1_0", + "RIOB_WW2A1_0", + "RIOB_WW4END1_0", + "RIOB_SW4A0_0", + "RIOB_NE4BEG0_0", + "RIOB_LH5_0", + "RIOB_EE4B3_0", + "RIOB_SW2A3_0", + "RIOB_WW2END0_0", + "RIOB_LH12_0", + "RIOB_SE4C1_0", + "RIOB_EE4A3_0", + "RIOB_WL1END1_0", + "RIOB_WW4B3_0", + "RIOB_NW2A2_0", + "RIOB_EE4C0_0", + "RIOB_WR1END0_0", + "RIOB_SE2A3_0", + "RIOB_LH11_0", + "RIOB_SE2A2_0", + "RIOB_LH7_0", + "RIOB_NE4BEG1_0", + "RIOB_EE4B1_0", + "RIOB_EL1BEG2_0", + "RIOB_EE4A0_0", + "LIOB_IN_TERM0", + "RIOB_NW2A3_0", + "RIOB_EE2BEG0_0", + "RIOB_NW4A0_0" ], + "tile_type": "RIOB33_SING", "sites": [ { - "prefix": "IOB", - "y_coord": 0, - "type": "IOB33", "site_pins": { - "DIFFI_IN": null, - "DIFFO_OUT": "IOB_DIFFO_OUT0", - "PADOUT": "IOB_PADOUT0", - "T_IN": null, - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "O_OUT": "IOB_O_OUT0", - "T": "IOB_T0", - "O": "IOB_O0", - "O_IN": null, - "DIFFO_IN": null, - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "T_OUT": "IOB_T_OUT0", - "PU_INT_EN": "IOB_PU_INT_EN_1", "I": "IOB_IBUF0", "DIFF_TERM_INT_EN": null, + "T": "IOB_T0", + "O_IN": null, + "PU_INT_EN": "IOB_PU_INT_EN_1", + "DIFFI_IN": null, "PD_INT_EN": "IOB_PD_INT_EN_1", - "INTERMDISABLE": "LIOB_IN_TERM0" + "PADOUT": "IOB_PADOUT0", + "DIFFO_IN": null, + "O": "IOB_O0", + "INTERMDISABLE": "LIOB_IN_TERM0", + "O_OUT": "IOB_O_OUT0", + "T_IN": null, + "IBUFDISABLE": "IOB_IBUF_DISABLE0", + "T_OUT": "IOB_T_OUT0", + "DIFFO_OUT": "IOB_DIFFO_OUT0", + "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1" }, + "type": "IOB33", + "prefix": "IOB", + "name": "X0Y0", "x_coord": 0, - "name": "X0Y0" + "y_coord": 0 } - ], - "pips": {}, - "tile_type": "RIOB33_SING" + ] } \ No newline at end of file diff --git a/artix7/tile_type_RIOI3.json b/artix7/tile_type_RIOI3.json index a01d78e..dbf18ec 100644 --- a/artix7/tile_type_RIOI3.json +++ b/artix7/tile_type_RIOI3.json @@ -1,3928 +1,3928 @@ { - "wires": [ - "IOI_LOGIC_OUTS17_1", - "IOI_WW2END3_1", - "IOI_SE4BEG2_0", - "RIOI3_IDELAY0_IFDLY1", - "RIOI_OLOGIC0_TFB_LOCAL", - "IOI_NW4A2_0", - "IOI_NW4END1_0", - "IOI_IMUX21_1", - "IOI_WR1END3_0", - "IOI_NE2A2_0", - "IOI_IMUX20_0", - "IOI_EE2BEG2_0", - "IOI_BYP3_1", - "IOI_OLOGIC1_D8", - "IOI_CLK1_1", - "IOI_ODELAY0_C", - "IOI_IMUX3_1", - "IOI_WR1END3_1", - "IOI_NW4END1_1", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_WW4END0_1", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_EE2A3_1", - "IOI_OLOGIC1_D6", - "IOI_IMUX9_1", - "IOI_IMUX35_0", - "IOI_BLOCK_OUTS3_1", - "RIOI3_IDELAY1_IFDLY1", - "IOI_OLOGIC0_D2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_OLOGIC0_CLKDIV", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_RCLK_DIV_CE2", - "IOI_SW2A2_1", - "IOI_WW4END1_1", - "IOI_ODELAY0_CE", - "IOI_NE2A1_0", - "RIOI_OLOGIC0_TQ", - "IOI_IMUX0_0", - "RIOI_ISOUT10", - "IOI_ER1BEG0_0", - "IOI_IMUX10_1", - "IOI_ILOGIC0_BITSLIP", - "IOI_NE4C3_0", - "IOI_IMUX10_0", - "IOI_EE4B3_0", - "IOI_IMUX45_1", - "IOI_LH4_0", - "IOI_NW4END2_0", - "IOI_OLOGIC0_SR", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_LH1_0", - "IOI_EE4A1_1", - "IOI_LOGIC_OUTS2_1", - "IOI_BLOCK_OUTS1_0", - "IOI_WW4B1_0", - "IOI_IDELAYCTRL_OUTN1", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_LH2_0", - "IOI_FAN4_1", - "IOI_IMUX12_1", - "RIOI_T1", - "IOI_OLOGIC1_TBYTEIN", - "IOI_IMUX1_1", - "IOI_IMUX8_0", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_CTRL0_0", - "IOI_IDELAY1_INC", - "IOI_IMUX24_1", - "IOI_SW2A2_0", - "IOI_NW4A2_1", - "IOI_LOGIC_OUTS12_1", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_INC", - "IOI_OLOGIC0_T4", - "IOI_ER1BEG1_0", - "RIOI_ODELAY1_OFDLY1", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_IMUX14_1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_ILOGIC1_Q1", - "IOI_EL1BEG2_0", - "IOI_ILOGIC1_SR", - "RIOI_KEEPER_INT_EN_0", - "RIOI_OLOGIC1_TFB", - "IOI_NE4BEG2_0", - "IOI_EL1BEG3_1", - "IOI_SW2A0_0", - "IOI_IMUX36_1", - "IOI_IMUX24_0", - "IOI_NW4END3_1", - "IOI_OLOGIC1_D2", - "IOI_EE4C1_1", - "IOI_LOGIC_OUTS21_0", - "IOI_IMUX4_1", - "IOI_WW4C3_0", - "IOI_OLOGIC0_D7", - "IOI_EE2A1_1", - "IOI_IMUX37_0", - "IOI_IDELAY1_CE", - "IOI_ODELAY1_CNTVALUEIN1", - "RIOI3_IDELAY0_IFDLY2", - "IOI_WW2A2_0", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_BYP4_1", - "IOI_IMUX42_1", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_IMUX35_1", - "IOI_IMUX30_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LH8_1", - "IOI_IMUX33_0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_EE4BEG3_1", - "IOI_NE2A2_1", - "IOI_ILOGIC0_Q2", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_BYP7_0", - "IOI_TBYTEIN", - "IOI_IMUX42_0", - "IOI_SW4A2_0", - "IOI_WR1END0_1", - "IOI_WW2A2_1", - "IOI_MONITOR_P", - "RIOI_OSIN20", - "IOI_NE4C1_0", - "IOI_IMUX29_0", - "IOI_OCLKM_1", - "RIOI_ODELAY0_ODATAIN", - "IOI_WW4B2_1", - "IOI_OLOGIC0_REV", - "IOI_WW4END3_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LH7_1", - "IOI_NW2A3_1", - "IOI_LH12_1", - "IOI_EE4BEG2_0", - "IOI_LH7_0", - "RIOI_ILOGIC0_D", - "IOI_ER1BEG3_0", - "IOI_IMUX0_1", - "IOI_LOGIC_OUTS7_1", - "IOI_ILOGIC0_Q3", - "IOI_IDELAY0_LDPIPEEN", - "IOI_WW2END2_0", - "RIOI_PD_INT_EN_0", - "IOI_LH11_1", - "IOI_IDELAY1_CINVCTRL", - "IOI_NW4A3_1", - "RIOI_OLOGIC0_OQ", - "IOI_IMUX23_0", - "IOI_IMUX37_1", - "IOI_LOGIC_OUTS3_0", - "IOI_WW4A0_0", - "IOI_IOCLK0", - "RIOI_I2GCLK_BOT1", - "IOI_WW2END3_0", - "RIOI_ISOUT11", - "IOI_NE4BEG3_0", - "IOI_SE2A2_1", - "IOI_LEAF_GCLK0", - "IOI_IDELAY0_CNTVALUEIN1", - "RIOI_ODELAY1_OFDLY2", - "IOI_IMUX18_1", - "IOI_IDELAY0_CE", - "RIOI_ISIN21", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_NW4END3_0", - "IOI_WW4C0_1", - "IOI_SE4C3_0", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IMUX39_1", - "IOI_NW4A1_0", - "IOI_NE4BEG2_1", - "IOI_SE4BEG0_0", - "IOI_IMUX22_1", - "IOI_IMUX14_0", - "IOI_CLK1_0", - "IOI_SE4BEG3_0", - "IOI_OLOGIC0_D6", - "IOI_WW2A1_1", - "IOI_EE2A3_0", - "IOI_IMUX28_0", - "IOI_OCLK_0", - "IOI_IMUX18_0", - "IOI_NW2A1_1", - "RIOI_ILOGIC1_D", - "RIOI_OLOGIC0_TFB", - "IOI_IDELAY1_C", - "IOI_WW4A2_0", - "IOI_NE4C0_0", - "IOI_NW2A1_0", - "IOI_IMUX2_1", - "IOI_LOGIC_OUTS9_0", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_IMUX16_0", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_BLOCK_OUTS2_1", - "IOI_WL1END3_0", - "IOI_LOGIC_OUTS7_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_IDELAYCTRL_RDY", - "IOI_RCLK_DIV_CLR2", - "IOI_IMUX11_0", - "IOI_LOGIC_OUTS16_1", - "IOI_RCLK_DIV_CE3", - "IOI_WR1END2_0", - "IOI_LOGIC_OUTS18_1", - "IOI_SW4A0_0", - "IOI_NE4BEG1_1", - "IOI_WR1END1_0", - "IOI_OLOGIC1_CLK", - "IOI_EE4B0_0", - "IOI_WW4A3_1", - "RIOI_PU_INT_EN_0", - "IOI_RCLK_DIV_CLR1", - "IOI_LOGIC_OUTS15_0", - "RIOI_I2GCLK_TOP1", - "RIOI_I0", - "IOI_WW4B0_0", - "IOI_OLOGIC1_D3", - "IOI_ODELAY1_LD", - "RIOI_ILOGIC1_OFB", - "IOI_NW4END2_1", - "IOI_LOGIC_OUTS10_1", - "IOI_NE2A3_1", - "IOI_NW2A0_0", - "IOI_WW4END3_0", - "IOI_IOCLK3", - "IOI_SE2A3_0", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_WW2A3_0", - "IOI_ILOGIC0_CE1", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_BYP1_1", - "RIOI_OSOUT20", - "IOI_SE4C1_1", - "IOI_SW4A3_1", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IMUX38_1", - "IOI_ER1BEG2_0", - "IOI_WW4C0_0", - "RIOI_DCI_T_TERM0", - "IOI_IMUX25_0", - "IOI_NE4BEG0_0", - "IOI_IMUX7_1", - "IOI_FAN3_1", - "IOI_OLOGIC1_SR", - "IOI_SW4END1_0", - "IOI_ILOGIC1_CE2", - "RIOI_DIFF_TERM_INT_EN", - "IOI_WW4END0_0", - "IOI_FAN7_0", - "IOI_LOGIC_OUTS1_0", - "IOI_EE2BEG0_0", - "IOI_SE4C0_1", - "IOI_OLOGIC1_T3", - "IOI_IMUX43_1", - "IOI_EE2BEG3_1", - "IOI_NE4C3_1", - "IOI_IMUX34_1", - "IOI_IMUX46_0", - "IOI_IMUX27_0", - "RIOI_IBUF_DISABLE0", - "IOI_DCI_TSTCLK", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_D8", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_EE4C2_0", - "IOI_IMUX11_1", - "IOI_CTRL1_0", - "IOI_DCI_TSTHLP", - "IOI_EE4A3_0", - "IOI_OLOGIC0_CLKB", - "IOI_WW4C3_1", - "IOI_IMUX40_0", - "RIOI_O0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_IMUX47_0", - "RIOI_OSIN10", - "IOI_OLOGIC1_CLKDIV", - "IOI_LOGIC_OUTS5_1", - "RIOI_OLOGIC1_TFB_LOCAL", - "IOI_BYP7_1", - "IOI_LOGIC_OUTS12_0", - "RIOI_OSOUT21", - "IOI_SE4BEG0_1", - "IOI_OLOGIC0_IOCLKGLITCH", - "RIOI_IBUF1", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_LOGIC_OUTS5_0", - "IOI_FAN4_0", - "IOI_WW4B0_1", - "IOI_WL1END0_1", - "IOI_IMUX2_0", - "IOI_WW2END0_0", - "IOI_LH2_1", - "IOI_WW4A1_1", - "IOI_WW4C1_1", - "RIOI_OSIN11", - "IOI_ER1BEG2_1", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_OLOGIC0_T1", - "IOI_IMUX3_0", - "IOI_EE2BEG1_0", - "IOI_IMUX29_1", - "IOI_WW2END0_1", - "IOI_OCLK_1", - "IOI_WW2A0_0", - "IOI_ER1BEG1_1", - "RIOI_ILOGIC1_DDLY", - "IOI_RCLK_FORIO2", - "IOI_PHASER_TO_IO_ICLK", - "IOI_NE4C2_0", - "IOI_BYP2_1", - "IOI_WR1END1_1", - "IOI_FAN3_0", - "IOI_ILOGIC1_BITSLIP", - "IOI_ODELAY0_LDPIPEEN", - "IOI_IMUX44_1", - "IOI_NE2A1_1", - "IOI_LOGIC_OUTS1_1", - "IOI_EE4B0_1", - "IOI_OLOGIC1_CLKB", - "IOI_RCLK_DIV_CLR0", - "IOI_ILOGIC1_CLKDIV", - "IOI_DCI_TSTHLN", - "IOI_OLOGIC1_D5", - "IOI_SW2A3_0", - "IOI_IDELAY1_REGRST", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_LOGIC_OUTS19_0", - "IOI_IMUX32_1", - "IOI_SE2A1_1", - "IOI_LOGIC_OUTS21_1", - "IOI_EE2A2_0", - "IOI_ODELAY1_REGRST", - "RIOI_OLOGIC1_OFB", - "IOI_LH9_0", - "IOI_FAN5_1", - "IOI_LH6_0", - "RIOI_ODELAY0_DATAOUT", - "IOI_ODELAY1_C", - "IOI_IMUX19_0", - "IOI_OLOGIC1_D4", - "IOI_LOGIC_OUTS10_0", - "IOI_ILOGIC0_OCLK", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_INT_DCI_EN", - "IOI_EL1BEG0_1", - "IOI_SW2A1_0", - "IOI_OLOGIC1_D1", - "RIOI_OLOGIC0_CLKDIVF", - "IOI_DCI_TSTRST0", - "IOI_OLOGIC0_T2", - "IOI_BLOCK_OUTS0_0", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_EE4BEG2_1", - "IOI_SE4BEG3_1", - "IOI_OLOGIC1_T2", - "IOI_WW4A0_1", - "IOI_IMUX26_0", - "IOI_IMUX45_0", - "IOI_MONITOR_N", - "IOI_IMUX8_1", - "IOI_RCLK_DIV_CLR3", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY1_CE", - "IOI_LH6_1", - "RIOI_OLOGIC1_CLKDIVF", - "RIOI_OLOGIC1_OQ", - "IOI_IOCLK1", - "IOI_FAN7_1", - "IOI_RCLK_DIV_CLR0_1", - "IOI_LOGIC_OUTS2_0", - "IOI_WW4A1_0", - "IOI_IMUX7_0", - "IOI_ODELAY1_INC", - "IOI_ILOGIC0_CLK", - "IOI_IMUX20_1", - "IOI_WW2END1_1", - "RIOI_IDELAY1_DATAOUT", - "IOI_LOGIC_OUTS11_0", - "IOI_SE4C0_0", - "IOI_LOGIC_OUTS17_0", - "IOI_ER1BEG3_1", - "IOI_ILOGIC0_CLKDIV", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_REV", - "IOI_FAN1_1", - "IOI_LH10_0", - "RIOI_ISOUT20", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC0_CE2", - "IOI_FAN6_1", - "IOI_IDELAY1_CNTVALUEOUT0", - "RIOI_ODELAY0_OFDLY0", - "IOI_IMUX5_0", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_SW4END0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_ILOGIC1_Q5", - "IOI_NE4BEG0_1", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_WW4B3_0", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_EE4BEG0_1", - "IOI_EE2BEG2_1", - "IOI_OLOGIC1_T1", - "IOI_IMUX6_1", - "IOI_EL1BEG2_1", - "IOI_SE4C1_0", - "IOI_NW4END0_1", - "RIOI_ODELAY1_OFDLY0", - "IOI_IMUX1_0", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_REV", - "IOI_SE4C2_1", - "IOI_SE4BEG2_1", - "IOI_EE4A0_1", - "IOI_IMUX36_0", - "IOI_EE2BEG0_1", - "RIOI_OSIN21", - "RIOI_ILOGIC0_DDLY", - "IOI_NW4A0_1", - "IOI_WW4END2_1", - "IOI_IMUX46_1", - "IOI_EE4A3_1", - "IOI_LOGIC_OUTS20_0", - "IOI_WL1END1_1", - "RIOI_OLOGIC1_TQ", - "IOI_SW4END1_1", - "IOI_IMUX13_1", - "IOI_ODELAY0_LD", - "IOI_ILOGIC1_Q8", - "IOI_IMUX23_1", - "IOI_IMUX_RC3", - "IOI_IMUX31_1", - "IOI_WW4A3_0", - "IOI_OLOGIC0_OCE", - "IOI_LOGIC_OUTS3_1", - "RIOI_O1", - "IOI_EE2A2_1", - "IOI_LOGIC_OUTS8_0", - "IOI_ILOGIC0_CLKB", - "IOI_IMUX27_1", - "IOI_NE2A0_1", - "IOI_RCLK_DIV_CE1", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_NE2A0_0", - "IOI_IDELAY0_REGRST", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_SE4BEG1_1", - "IOI_IMUX_RC2", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_ILOGIC0_O", - "IOI_EE4A1_0", - "IOI_IDELAYCTRL_RST", - "IOI_SW4A1_0", - "RIOI3_IDELAY1_IFDLY2", - "IOI_EE4A2_1", - "IOI_LOGIC_OUTS9_1", - "RIOI_ISIN20", - "IOI_WW4A2_1", - "IOI_FAN2_1", - "IOI_FAN5_0", - "RIOI_ODELAY0_OFDLY2", - "IOI_IMUX16_1", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_IOCLK2", - "IOI_OLOGIC1_D7", - "RIOI_PU_INT_EN_1", - "IOI_IMUX6_0", - "RIOI_IBUF0", - "IOI_LOGIC_OUTS4_0", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC1_Q4", - "IOI_NW4END0_0", - "RIOI_OLOGIC0_OFB", - "IOI_FAN0_1", - "IOI_BLOCK_OUTS3_0", - "IOI_IMUX38_0", - "IOI_IDELAY0_CINVCTRL", - "IOI_OLOGIC1_OCE", - "IOI_EE4A2_0", - "IOI_BLOCK_OUTS0_1", - "IOI_IMUX4_0", - "IOI_OLOGIC1_CLKDIVB", - "IOI_SW4END2_0", - "IOI_BYP0_1", - "IOI_IMUX_RC0", - "IOI_IMUX31_0", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IMUX15_0", - "IOI_EE4C3_0", - "IOI_LOGIC_OUTS11_1", - "IOI_NE4BEG1_0", - "IOI_SW4END2_1", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS4_1", - "IOI_WR1END0_0", - "IOI_IDELAY0_C", - "IOI_SE2A2_0", - "IOI_LOGIC_OUTS13_0", - "IOI_ILOGIC1_OCLK", - "IOI_BYP4_0", - "IOI_WW2A1_0", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_IDELAY0_DATAIN", - "IOI_EE4B2_1", - "IOI_IMUX28_1", - "IOI_LEAF_GCLK5", - "IOI_SW4A3_0", - "IOI_BLOCK_OUTS1_1", - "IOI_WW4C1_0", - "IOI_IMUX9_0", - "IOI_BYP5_0", - "IOI_LOGIC_OUTS18_0", - "IOI_NW4A0_0", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_LH10_1", - "IOI_IMUX12_0", - "RIOI_PD_INT_EN_1", - "RIOI_ISIN11", - "IOI_LOGIC_OUTS23_0", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_DCI_DCIDONE", - "IOI_SE2A0_0", - "IOI_IMUX21_0", - "IOI_EE4B1_1", - "IOI_RCLK_DIV_CE3_1", - "IOI_EE4BEG0_0", - "RIOI_I1", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ILOGIC1_CLK", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_LOGIC_OUTS14_1", - "IOI_BYP3_0", - "IOI_EE2A0_1", - "IOI_LEAF_GCLK4", - "IOI_SW4A2_1", - "IOI_OLOGIC1_T4", - "IOI_LOGIC_OUTS0_0", - "IOI_WW2END1_0", - "IOI_BYP5_1", - "IOI_ER1BEG0_1", - "IOI_LOGIC_OUTS16_0", - "IOI_IMUX5_1", - "IOI_NW4A3_0", - "IOI_EE4BEG1_1", - "RIOI3_IDELAY0_IFDLY0", - "IOI_SW2A1_1", - "RIOI_ILOGIC0_TFB", - "IOI_IDELAY0_LD", - "IOI_EE2A0_0", - "IOI_ODELAY1_CNTVALUEOUT0", - "RIOI_ILOGIC0_OFB", - "IOI_CLK0_1", - "IOI_RCLK_FORIO3", - "IOI_IMUX44_0", - "IOI_PHASER_TO_IO_OCLK_0", - "RIOI_I2GCLK_TOP0", - "IOI_ILOGIC1_O", - "IOI_SE2A3_1", - "IOI_ILOGIC1_REV", - "IOI_ODELAY0_CNTVALUEIN0", - "RIOI_T0", - "IOI_EE2A1_0", - "IOI_IMUX17_1", - "IOI_FAN1_0", - "IOI_EE4A0_0", - "IOI_LOGIC_OUTS22_0", - "RIOI_ISOUT21", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_RCLK_DIV_CE0", - "RIOI_ODELAY1_ODATAIN", - "IOI_WW4C2_0", - "IOI_NW2A3_0", - "IOI_IMUX34_0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_NE4C2_1", - "IOI_IMUX22_0", - "IOI_OLOGIC0_T3", - "IOI_ODELAY1_CINVCTRL", - "IOI_IMUX17_0", - "RIOI_ODELAY0_OFDLY1", - "IOI_WW4B2_0", - "IOI_FAN6_0", - "IOI_IDELAY1_LDPIPEEN", - "IOI_WL1END0_0", - "IOI_OCLKM_0", - "IOI_IMUX15_1", - "IOI_CLK0_0", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IMUX25_1", - "RIOI_IDELAY1_IDATAIN", - "IOI_EL1BEG0_0", - "IOI_OLOGIC0_CLK", - "IOI_IMUX39_0", - "IOI_WL1END1_0", - "IOI_WL1END2_0", - "IOI_IMUX41_0", - "IOI_CTRL0_1", - "IOI_EE4C0_0", - "IOI_ILOGIC1_Q6", - "IOI_NW2A0_1", - "IOI_EE2BEG1_1", - "RIOI_ODELAY1_DATAOUT", - "IOI_ILOGIC1_Q2", - "IOI_CTRL1_1", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_OLOGIC0_D4", - "IOI_SE4BEG1_0", - "IOI_EE2BEG3_0", - "IOI_LOGIC_OUTS15_1", - "IOI_SW4A1_1", - "IOI_EL1BEG1_0", - "IOI_DCI_TSTRST", - "IOI_SW2A3_1", - "IOI_NE4C0_1", - "IOI_ILOGIC1_CLKDIVP", - "IOI_IMUX30_1", - "IOI_ILOGIC0_Q5", - "IOI_IDELAYCTRL_OUTN65", - "IOI_WR1END2_1", - "IOI_WW4B1_1", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_EE4BEG3_0", - "IOI_SE2A0_1", - "IOI_FAN0_0", - "RIOI_DCI_T_TERM1", - "RIOI_ILOGIC1_TFB", - "IOI_EE4BEG1_0", - "IOI_IMUX47_1", - "IOI_LH1_1", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC0_OCLKB", - "IOI_RCLK_DIV_CE2_1", - "IOI_BYP2_0", - "IOI_EE4C1_0", - "IOI_WW2END2_1", - "IOI_IMUX43_0", - "IOI_BYP6_1", - "IOI_RCLK_FORIO1", - "IOI_ILOGIC1_OCLKB", - "IOI_LEAF_GCLK1", - "IOI_NW2A2_0", - "RIOI_KEEPER_INT_EN_1", - "IOI_IMUX33_1", - "IOI_LH11_0", - "IOI_ILOGIC0_Q6", - "IOI_SW4END3_1", - "IOI_ODELAY1_CLKIN", - "IOI_NW2A2_1", - "IOI_LH9_1", - "RIOI_OSOUT11", - "IOI_PHASER_TO_IO_OCLK", - "RIOI3_IDELAY1_IFDLY0", - "IOI_EE4B3_1", - "IOI_WW4B3_1", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "RIOI_IDELAY0_IDATAIN", - "IOI_ILOGIC1_Q3", - "IOI_FAN2_0", - "IOI_WW4C2_1", - "IOI_WL1END2_1", - "IOI_RCLK_FORIO0", - "IOI_SW4A0_1", - "IOI_NW4A1_1", - "RIOI_IBUF_DISABLE1", - "IOI_IMUX41_1", - "IOI_LOGIC_OUTS13_1", - "IOI_BLOCK_OUTS2_0", - "IOI_WW4END1_0", - "IOI_IMUX40_1", - "IOI_IMUX19_1", - "IOI_EE4B1_0", - "IOI_WL1END3_1", - "IOI_LEAF_GCLK2", - "IOI_ODELAY0_CLKIN", - "IOI_EE4B2_0", - "IOI_SE2A1_0", - "IOI_BYP6_0", - "IOI_IMUX32_0", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_DATAIN", - "IOI_EE4C2_1", - "IOI_LH5_1", - "IOI_ILOGIC0_Q7", - "IOI_IMUX_RC1", - "IOI_EL1BEG3_0", - "IOI_WW2A3_1", - "IOI_NE4C1_1", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_SW4END3_0", - "IOI_WW2A0_1", - "IOI_NE4BEG3_1", - "IOI_SE4C2_0", - "RIOI_OSOUT10", - "IOI_ODELAY0_INC", - "IOI_LOGIC_OUTS6_1", - "IOI_BYP1_0", - "IOI_NE2A3_0", - "IOI_ILOGIC1_Q7", - "IOI_ODELAY0_REGRST", - "IOI_ILOGIC0_CLKDIVP", - "IOI_EE4C3_1", - "IOI_SE4C3_1", - "IOI_ILOGIC1_CLKB", - "IOI_LOGIC_OUTS23_1", - "IOI_OLOGIC0_D1", - "IOI_EE4C0_1", - "IOI_LOGIC_OUTS22_1", - "IOI_OLOGIC1_TCE", - "IOI_LH8_0", - "RIOI_IDELAY0_DATAOUT", - "IOI_SW2A0_1", - "IOI_SW4END0_1", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_LOGIC_OUTS14_0", - "IOI_ODELAY1_LDPIPEEN", - "IOI_LH12_0", - "IOI_IMUX13_0", - "IOI_LEAF_GCLK3", - "IOI_BYP0_0", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ILOGIC0_Q4", - "IOI_EL1BEG1_1", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_WW4END2_0", - "IOI_IMUX26_1", - "RIOI_ISIN10", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_TBYTEIN", - "IOI_LOGIC_OUTS20_1" - ], - "sites": [ - { - "prefix": "OLOGIC", - "y_coord": 0, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC1_D1", - "D3": "IOI_OLOGIC1_D3", - "SR": "IOI_OLOGIC1_SR", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "TFB": "RIOI_OLOGIC1_TFB", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLK": "IOI_OLOGIC1_CLK", - "T4": "IOI_OLOGIC1_T4", - "OQ": "RIOI_OLOGIC1_OQ", - "D8": "IOI_OLOGIC1_D8", - "T1": "IOI_OLOGIC1_T1", - "D5": "IOI_OLOGIC1_D5", - "SHIFTOUT1": "RIOI_OSOUT11", - "T2": "IOI_OLOGIC1_T2", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "D4": "IOI_OLOGIC1_D4", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D2": "IOI_OLOGIC1_D2", - "TQ": "RIOI_OLOGIC1_TQ", - "T3": "IOI_OLOGIC1_T3", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "OCE": "IOI_OLOGIC1_OCE", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "SHIFTIN1": null, - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "TCE": "IOI_OLOGIC1_TCE", - "OFB": "RIOI_OLOGIC1_OFB", - "SHIFTIN2": null, - "SHIFTOUT2": "RIOI_OSOUT21", - "REV": null, - "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "ILOGIC", - "y_coord": 0, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q1": "IOI_ILOGIC1_Q1", - "SR": "IOI_ILOGIC1_SR", - "D": "RIOI_ILOGIC1_D", - "DDLY": "RIOI_ILOGIC1_DDLY", - "SHIFTIN2": "RIOI_ISIN21", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "Q3": "IOI_ILOGIC1_Q3", - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "Q8": "IOI_ILOGIC1_Q8", - "TFB": "RIOI_ILOGIC1_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC1_CE1", - "Q2": "IOI_ILOGIC1_Q2", - "Q6": "IOI_ILOGIC1_Q6", - "CLKB": "IOI_ILOGIC1_CLKB", - "Q7": "IOI_ILOGIC1_Q7", - "O": "IOI_ILOGIC1_O", - "CLK": "IOI_ILOGIC1_CLK", - "CE2": "IOI_ILOGIC1_CE2", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "SHIFTIN1": "RIOI_ISIN11", - "OCLK": "IOI_ILOGIC1_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "OFB": "RIOI_ILOGIC1_OFB", - "SHIFTOUT1": "RIOI_ISOUT11", - "SHIFTOUT2": "RIOI_ISOUT21", - "REV": null, - "CLKDIV": "IOI_ILOGIC1_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "OLOGIC", - "y_coord": 1, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC0_D1", - "D3": "IOI_OLOGIC0_D3", - "SR": "IOI_OLOGIC0_SR", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "TFB": "RIOI_OLOGIC0_TFB", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLK": "IOI_OLOGIC0_CLK", - "T4": "IOI_OLOGIC0_T4", - "OQ": "RIOI_OLOGIC0_OQ", - "D8": "IOI_OLOGIC0_D8", - "T1": "IOI_OLOGIC0_T1", - "D5": "IOI_OLOGIC0_D5", - "SHIFTOUT1": "RIOI_OSOUT10", - "T2": "IOI_OLOGIC0_T2", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "D4": "IOI_OLOGIC0_D4", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D2": "IOI_OLOGIC0_D2", - "TQ": "RIOI_OLOGIC0_TQ", - "T3": "IOI_OLOGIC0_T3", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "OCE": "IOI_OLOGIC0_OCE", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "SHIFTIN1": "RIOI_OSIN10", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "TCE": "IOI_OLOGIC0_TCE", - "OFB": "RIOI_OLOGIC0_OFB", - "SHIFTIN2": "RIOI_OSIN20", - "SHIFTOUT2": "RIOI_OSOUT20", - "REV": null, - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "ILOGIC", - "y_coord": 1, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q1": "IOI_ILOGIC0_Q1", - "SR": "IOI_ILOGIC0_SR", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "SHIFTIN2": null, - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "Q3": "IOI_ILOGIC0_Q3", - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "Q8": "IOI_ILOGIC0_Q8", - "TFB": "RIOI_ILOGIC0_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC0_CE1", - "Q2": "IOI_ILOGIC0_Q2", - "Q6": "IOI_ILOGIC0_Q6", - "CLKB": "IOI_ILOGIC0_CLKB", - "Q7": "IOI_ILOGIC0_Q7", - "O": "IOI_ILOGIC0_O", - "CLK": "IOI_ILOGIC0_CLK", - "CE2": "IOI_ILOGIC0_CE2", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "SHIFTIN1": null, - "OCLK": "IOI_ILOGIC0_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "OFB": "RIOI_ILOGIC0_OFB", - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "REV": null, - "CLKDIV": "IOI_ILOGIC0_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "IDELAY", - "y_coord": 0, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CE": "IOI_IDELAY1_CE", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "IFDLY2": "RIOI3_IDELAY1_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "LD": "IOI_IDELAY1_LD", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "IFDLY0": "RIOI3_IDELAY1_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "INC": "IOI_IDELAY1_INC", - "DATAOUT": "RIOI_IDELAY1_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY1_DATAIN", - "C": "IOI_IDELAY1_C", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "IDATAIN": "RIOI_IDELAY1_IDATAIN", - "REGRST": "IOI_IDELAY1_REGRST", - "IFDLY1": "RIOI3_IDELAY1_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IDELAY", - "y_coord": 1, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CE": "IOI_IDELAY0_CE", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "IFDLY2": "RIOI3_IDELAY0_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "LD": "IOI_IDELAY0_LD", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "IFDLY0": "RIOI3_IDELAY0_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "INC": "IOI_IDELAY0_INC", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY0_DATAIN", - "C": "IOI_IDELAY0_C", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "REGRST": "IOI_IDELAY0_REGRST", - "IFDLY1": "RIOI3_IDELAY0_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "RIOI3.IOI_RCLK_FORIO0->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC0_OQ->>RIOI_O0": { - "can_invert": "0", - "dst_wire": "RIOI_O0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OQ", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX15_1->IOI_OLOGIC0_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX43_0->IOI_OLOGIC1_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX42_0->IOI_OLOGIC1_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX40_0->IOI_OLOGIC1_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP3_0->IOI_IMUX_RC0": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC0", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX15_0->IOI_OLOGIC1_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX26_0->IOI_IDELAY1_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q4", - "is_pseudo": "0" - }, - "RIOI3.IOI_CTRL1_1->IOI_ILOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX30_0->IOI_IDELAY1_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX47_1->IOI_OLOGIC0_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_CLK1_1->IOI_IDELAY0_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { - "can_invert": "0", - "dst_wire": "RIOI_DCI_T_TERM1", - "is_directional": "1", - "src_wire": "IOI_IMUX6_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, "RIOI3.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_1", - "is_directional": "1", "src_wire": "IOI_ILOGIC0_Q2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q8", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TQ", - "is_pseudo": "1" - }, - "RIOI3.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { - "can_invert": "0", - "dst_wire": "RIOI_IBUF_DISABLE0", - "is_directional": "1", - "src_wire": "IOI_IMUX9_1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_ISOUT20->RIOI_ISIN21": { - "can_invert": "0", - "dst_wire": "RIOI_ISIN21", - "is_directional": "1", - "src_wire": "RIOI_ISOUT20", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAYCTRL_RST", - "is_directional": "1", - "src_wire": "IOI_IMUX24_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC1_DDLY", - "is_pseudo": "1" - }, - "RIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY1_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX43_1->IOI_OLOGIC0_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX34_1->IOI_OLOGIC0_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX40_1->IOI_OLOGIC0_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX44_0->IOI_OLOGIC1_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q6", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX45_0->IOI_OLOGIC1_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q7", - "is_pseudo": "0" - }, - "RIOI3.IOI_CTRL0_0->IOI_OLOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX13_1->IOI_OLOGIC0_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q8", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "RIOI3.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3.RIOI_IBUF1->RIOI_I1": { - "can_invert": "0", - "dst_wire": "RIOI_I1", - "is_directional": "1", - "src_wire": "RIOI_IBUF1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q3", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC0_TQ->>RIOI_T0": { - "can_invert": "0", - "dst_wire": "RIOI_T0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TQ", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OQ", - "is_pseudo": "1" - }, - "RIOI3.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_DDLY", - "is_directional": "1", - "src_wire": "RIOI_IDELAY1_DATAOUT", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE2_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_CTRL1_0->IOI_ILOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_1", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS13_1", - "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_OUTN1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_O", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.RIOI_I1->RIOI_IDELAY1_IDATAIN": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY1_IDATAIN", - "is_directional": "1", - "src_wire": "RIOI_I1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX31_0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE0", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TFB", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "RIOI3.IOI_IMUX21_1->IOI_OLOGIC0_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_CLK1_0->IOI_IDELAY1_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "RIOI3.IOI_IMUX21_0->IOI_OLOGIC1_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "RIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX31_1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX47_0->IOI_OLOGIC1_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR0_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX46_0->IOI_OLOGIC1_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS16_0", - "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX42_1->IOI_OLOGIC0_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_OQ", - "is_pseudo": "1" - }, - "RIOI3.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX30_1->IOI_IDELAY0_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC0_DDLY", - "is_pseudo": "1" - }, - "RIOI3.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "RIOI3.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q7", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC1_OQ->>RIOI_O1": { - "can_invert": "0", - "dst_wire": "RIOI_O1", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_OQ", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY1_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { - "can_invert": "0", - "dst_wire": "RIOI_DCI_T_TERM0", - "is_directional": "1", - "src_wire": "IOI_IMUX6_1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OSOUT11->RIOI_OSIN10": { - "can_invert": "0", - "dst_wire": "RIOI_OSIN10", - "is_directional": "1", - "src_wire": "RIOI_OSOUT11", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX26_1->IOI_IDELAY0_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q5", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_CTRL0_1->IOI_OLOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q2", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TQ", - "is_pseudo": "1" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP4_0->IOI_IMUX_RC1": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "RIOI3.RIOI_I0->RIOI_IDELAY0_IDATAIN": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY0_IDATAIN", - "is_directional": "1", - "src_wire": "RIOI_I0", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "RIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR3", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", - "is_pseudo": "0" - }, - "RIOI3.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC1_D", - "is_pseudo": "1" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX32_0->IOI_IDELAY1_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1" }, "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "RIOI_I2GCLK_TOP0", "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q5", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX44_1->IOI_OLOGIC0_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.RIOI_I0->RIOI_ILOGIC0_D": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_D", - "is_directional": "1", - "src_wire": "RIOI_I0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX45_1->IOI_OLOGIC0_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX7_0->IOI_OLOGIC1_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" }, "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" }, - "RIOI3.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { + "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TFB", + "src_wire": "IOI_RCLK_FORIO0", "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "RIOI3.IOI_IOCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_1", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE3_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" }, "RIOI3.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_1", - "is_directional": "1", "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1" }, - "RIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "RIOI3.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", + "src_wire": "IOI_ILOGIC1_O", "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0" }, - "RIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OSOUT21->RIOI_OSIN20": { - "can_invert": "0", - "dst_wire": "RIOI_OSIN20", - "is_directional": "1", - "src_wire": "RIOI_OSOUT21", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.RIOI_I1->RIOI_ILOGIC1_D": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_D", "is_directional": "1", - "src_wire": "RIOI_I1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY0_DATAOUT", - "is_directional": "1", - "src_wire": "RIOI_IDELAY0_IDATAIN", - "is_pseudo": "1" - }, - "RIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR1_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX31_1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OFB", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY1_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX46_1->IOI_OLOGIC0_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP4_1->IOI_IMUX_RC2": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC2", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC0_D", - "is_pseudo": "1" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_OFB", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { - "can_invert": "0", - "dst_wire": "RIOI_IBUF_DISABLE1", - "is_directional": "1", - "src_wire": "IOI_IMUX9_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.RIOI_ISOUT10->RIOI_ISIN11": { - "can_invert": "0", - "dst_wire": "RIOI_ISIN11", - "is_directional": "1", - "src_wire": "RIOI_ISOUT10", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX31_0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS16_1", - "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_OUTN65", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "RIOI3.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_DDLY", - "is_directional": "1", - "src_wire": "RIOI_IDELAY0_DATAOUT", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q4", - "is_pseudo": "0" - }, - "RIOI3.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "RIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY1_DATAOUT", - "is_directional": "1", - "src_wire": "RIOI_IDELAY1_IDATAIN", - "is_pseudo": "1" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX32_1->IOI_IDELAY0_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS13_0", - "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT", - "is_pseudo": "0" - }, - "RIOI3.IOI_BYP3_1->IOI_IMUX_RC3": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC3", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IMUX7_1->IOI_OLOGIC0_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_1", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" }, "RIOI3.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D1", - "is_directional": "1", "src_wire": "IOI_IMUX34_0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1" }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "RIOI3.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { "can_invert": "0", - "dst_wire": "IOI_OCLK_0", + "src_wire": "RIOI_ILOGIC0_D", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3.RIOI_IBUF0->RIOI_I0": { - "can_invert": "0", - "dst_wire": "RIOI_I0", - "is_directional": "1", - "src_wire": "RIOI_IBUF0", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" }, "RIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_RCLK_FORIO2->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" }, - "RIOI3.RIOI_OLOGIC1_TQ->>RIOI_T1": { + "RIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", - "dst_wire": "RIOI_T1", + "src_wire": "IOI_IOCLK1", "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TQ", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" }, - "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "RIOI3.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", + "src_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_OFB" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL" + }, + "RIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.RIOI_IBUF0->RIOI_I0": { + "can_invert": "0", + "src_wire": "RIOI_IBUF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_I0" + }, + "RIOI3.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS22_1", "is_directional": "1", - "src_wire": "IOI_IDELAYCTRL_RDY", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" }, - "RIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "RIOI3.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", + "src_wire": "RIOI_IDELAY1_DATAOUT", "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_DDLY" }, - "RIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", + "src_wire": "IOI_LEAF_GCLK5", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" }, - "RIOI3.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "RIOI3.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T3", + "src_wire": "IOI_IMUX43_1", "is_directional": "1", - "src_wire": "IOI_IMUX13_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5" }, - "RIOI3.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "RIOI3.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", + "src_wire": "IOI_IMUX0_0", "is_directional": "1", - "src_wire": "IOI_IMUX35_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP" }, - "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "RIOI3.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", + "src_wire": "IOI_IMUX47_1", "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8" }, "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY1_IFDLY2" + }, + "RIOI3.IOI_IOCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6" + }, + "RIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0" + }, + "RIOI3.IOI_IOCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_IMUX31_0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "RIOI3.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "RIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TQ" + }, + "RIOI3.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD" + }, + "RIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1" + }, + "RIOI3.IOI_RCLK_FORIO0->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OQ" + }, + "RIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAYCTRL_OUTN65", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS16_1" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "can_invert": "0", + "src_wire": "IOI_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE1" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR" + }, + "RIOI3.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "RIOI3.IOI_IOCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_RCLK_FORIO1->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE0" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_TFB" + }, + "RIOI3.IOI_IOCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_IOCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1" + }, + "RIOI3.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN" + }, + "RIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV" + }, + "RIOI3.RIOI_OSOUT21->RIOI_OSIN20": { + "can_invert": "0", + "src_wire": "RIOI_OSOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN20" + }, + "RIOI3.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB" + }, + "RIOI3.IOI_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "can_invert": "0", + "src_wire": "IOI_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "RIOI3.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8" + }, + "RIOI3.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0" + }, + "RIOI3.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1" + }, + "RIOI3.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3" + }, + "RIOI3.RIOI_ISOUT10->RIOI_ISIN11": { + "can_invert": "0", + "src_wire": "RIOI_ISOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN11" + }, + "RIOI3.IOI_IMUX31_1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY1_IFDLY0" + }, + "RIOI3.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1" + }, + "RIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_IOCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.RIOI_ISOUT20->RIOI_ISIN21": { + "can_invert": "0", + "src_wire": "RIOI_ISOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN21" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.IOI_IMUX31_1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3" + }, + "RIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1" + }, + "RIOI3.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB" + }, + "RIOI3.RIOI_I0->RIOI_ILOGIC0_D": { + "can_invert": "0", + "src_wire": "RIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_D" + }, + "RIOI3.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_TFB" + }, + "RIOI3.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_BYP4_0->IOI_IMUX_RC1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1" + }, + "RIOI3.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1" + }, + "RIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC1_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "RIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1" + }, + "RIOI3.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4" + }, + "RIOI3.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB" + }, + "RIOI3.IOI_IOCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3" + }, + "RIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY1" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.RIOI_OLOGIC1_TQ->>RIOI_T1": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_T1" + }, + "RIOI3.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0" + }, + "RIOI3.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0" + }, + "RIOI3.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2" + }, + "RIOI3.IOI_IOCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_BYP3_1->IOI_IMUX_RC3": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB" + }, + "RIOI3.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.RIOI_I1->RIOI_ILOGIC1_D": { + "can_invert": "0", + "src_wire": "RIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_D" + }, + "RIOI3.IOI_IOCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TQ" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY1_DATAOUT" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY0" + }, + "RIOI3.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0" + }, + "RIOI3.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { + "can_invert": "0", + "src_wire": "IOI_IMUX24_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAYCTRL_RST" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0" + }, + "RIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0" + }, + "RIOI3.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY1_IFDLY1" + }, + "RIOI3.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAYCTRL_RDY", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS22_1" + }, + "RIOI3.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "RIOI3.RIOI_I0->RIOI_IDELAY0_IDATAIN": { + "can_invert": "0", + "src_wire": "RIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IDATAIN" + }, + "RIOI3.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_IOCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_DDLY" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_CLK1_1->IOI_IDELAY0_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C" + }, + "RIOI3.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_I2GCLK_TOP0" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "RIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST" + }, + "RIOI3.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY0_DATAOUT" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS13_0" + }, + "RIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM0" + }, + "RIOI3.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "RIOI3.IOI_CLK1_0->IOI_IDELAY1_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C" + }, + "RIOI3.RIOI_OSOUT11->RIOI_OSIN10": { + "can_invert": "0", + "src_wire": "RIOI_OSOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN10" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE" + }, + "RIOI3.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1" + }, + "RIOI3.IOI_IOCLK0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "RIOI3.RIOI_OLOGIC1_OQ->>RIOI_O1": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_O1" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6" + }, + "RIOI3.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL" + }, + "RIOI3.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "RIOI3.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OQ" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_IOCLK3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_IOCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN" + }, + "RIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK" + }, + "RIOI3.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC" + }, + "RIOI3.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM1" + }, + "RIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1" + }, + "RIOI3.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN" + }, + "RIOI3.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.RIOI_IBUF1->RIOI_I1": { + "can_invert": "0", + "src_wire": "RIOI_IBUF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_I1" + }, + "RIOI3.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS16_0" + }, + "RIOI3.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_IMUX31_0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_IOCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1" + }, + "RIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK" + }, + "RIOI3.IOI_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC" + }, + "RIOI3.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "RIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1" + }, + "RIOI3.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB" + }, + "RIOI3.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0" + }, + "RIOI3.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR" + }, + "RIOI3.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB" + }, + "RIOI3.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN" + }, + "RIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB" + }, + "RIOI3.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST" + }, + "RIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN" + }, + "RIOI3.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN" + }, + "RIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV" + }, + "RIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE" + }, + "RIOI3.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_OFB" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "RIOI3.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY2" + }, + "RIOI3.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.RIOI_I1->RIOI_IDELAY1_IDATAIN": { + "can_invert": "0", + "src_wire": "RIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IDATAIN" + }, + "RIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2" + }, + "RIOI3.IOI_BYP3_0->IOI_IMUX_RC0": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0" + }, + "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3.RIOI_OLOGIC0_TQ->>RIOI_T0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_T0" + }, + "RIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0" + }, + "RIOI3.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4" + }, + "RIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3.IOI_LEAF_GCLK0->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "RIOI3.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC0_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "RIOI3.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAYCTRL_OUTN1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS13_1" + }, + "RIOI3.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2" + }, + "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3.RIOI_OLOGIC0_OQ->>RIOI_O0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_O0" + }, + "RIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "RIOI3.IOI_IOCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3.IOI_BYP4_1->IOI_IMUX_RC2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2" + }, + "RIOI3.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4" + }, + "RIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC1_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "RIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK" + }, + "RIOI3.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3.IOI_IOCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1" + }, + "RIOI3.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0" + }, + "RIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7" + }, + "RIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" } }, - "tile_type": "RIOI3" + "wires": [ + "IOI_BYP5_1", + "IOI_IMUX26_1", + "IOI_NW4END3_1", + "IOI_ILOGIC1_REV", + "IOI_IMUX42_0", + "RIOI_I1", + "IOI_EE4A1_1", + "IOI_IMUX22_1", + "IOI_ILOGIC0_CE2", + "RIOI_ILOGIC1_D", + "IOI_IMUX5_0", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "IOI_OLOGIC1_CLKB", + "IOI_WW4C1_1", + "IOI_ER1BEG0_1", + "IOI_IMUX23_0", + "IOI_RCLK_DIV_CLR0_1", + "IOI_OLOGIC1_T1", + "IOI_IOCLK3", + "RIOI_OLOGIC0_TFB", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_RCLK_DIV_CE2_1", + "IOI_DCI_TSTRST", + "IOI_OLOGIC1_REV", + "IOI_WW4END1_0", + "IOI_CTRL0_1", + "IOI_MONITOR_N", + "IOI_ILOGIC1_Q7", + "IOI_IMUX38_0", + "IOI_WW4B1_1", + "IOI_EE4C1_1", + "IOI_IOCLK2", + "IOI_OLOGIC1_D8", + "IOI_LEAF_GCLK4", + "IOI_WW2END2_1", + "IOI_BYP2_0", + "IOI_ILOGIC1_Q1", + "IOI_IMUX36_1", + "IOI_LEAF_GCLK3", + "IOI_SW2A0_1", + "IOI_IMUX16_1", + "IOI_FAN2_1", + "IOI_IMUX27_0", + "IOI_IMUX22_0", + "IOI_EL1BEG2_1", + "IOI_NW4A1_0", + "IOI_BLOCK_OUTS0_1", + "IOI_SE2A1_0", + "IOI_IMUX4_1", + "IOI_EL1BEG2_0", + "IOI_WW4B0_1", + "IOI_NE4BEG3_1", + "IOI_SW4A3_1", + "IOI_SW4A1_0", + "IOI_ODELAY0_LDPIPEEN", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_EE4B3_1", + "IOI_NE4C0_1", + "IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_BYP4_1", + "IOI_EE2BEG1_0", + "IOI_LOGIC_OUTS20_0", + "IOI_SE4C3_1", + "IOI_WL1END2_0", + "IOI_CTRL1_1", + "RIOI_ISOUT21", + "IOI_FAN5_0", + "IOI_EE2A2_0", + "IOI_WW4END2_1", + "IOI_WW4C0_0", + "IOI_IDELAY1_REGRST", + "IOI_PHASER_TO_IO_OCLK", + "IOI_SW4A0_1", + "IOI_IDELAY1_CNTVALUEIN0", + "RIOI_OLOGIC1_OFB", + "IOI_OLOGIC0_CLKDIV", + "IOI_IMUX17_0", + "IOI_WW2END2_0", + "IOI_FAN3_0", + "IOI_LOGIC_OUTS14_0", + "IOI_DCI_TSTCLK", + "IOI_FAN0_0", + "IOI_ODELAY1_CINVCTRL", + "IOI_SE4BEG0_0", + "IOI_IMUX20_1", + "IOI_EE2BEG3_0", + "IOI_LH7_0", + "IOI_IMUX15_1", + "IOI_ILOGIC0_Q3", + "IOI_EE4A1_0", + "IOI_ILOGIC1_Q8", + "IOI_IDELAY1_C", + "IOI_BYP7_0", + "IOI_IMUX25_0", + "IOI_IDELAY0_REGRST", + "IOI_BYP3_1", + "IOI_NE2A0_1", + "IOI_IMUX11_1", + "IOI_SE4BEG0_1", + "IOI_ILOGIC0_OCLKB", + "RIOI_OLOGIC1_TFB_LOCAL", + "IOI_IMUX47_0", + "IOI_OLOGIC0_D4", + "IOI_SE2A0_0", + "IOI_SE4BEG1_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_SW4END3_0", + "IOI_EE4BEG3_0", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLKB", + "IOI_LOGIC_OUTS19_1", + "IOI_EL1BEG1_1", + "IOI_OLOGIC0_D3", + "IOI_EE4C0_0", + "RIOI_KEEPER_INT_EN_1", + "IOI_OLOGIC0_TCE", + "IOI_WW2A0_0", + "IOI_ODELAY0_CLKIN", + "IOI_DCI_TSTHLN", + "IOI_IMUX15_0", + "IOI_WW2END1_1", + "IOI_NE4C3_1", + "IOI_ILOGIC0_O", + "IOI_RCLK_DIV_CE3", + "IOI_BLOCK_OUTS0_0", + "IOI_SE4C3_0", + "IOI_ILOGIC1_CLKDIV", + "IOI_BYP0_1", + "IOI_IMUX32_0", + "IOI_OLOGIC1_D5", + "IOI_LH4_0", + "IOI_RCLK_DIV_CLR1", + "IOI_IMUX10_0", + "IOI_NW2A0_1", + "IOI_ILOGIC0_REV", + "RIOI_ISIN20", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_LOGIC_OUTS1_1", + "IOI_OLOGIC0_T1", + "IOI_EE4BEG1_0", + "RIOI_ISIN11", + "RIOI_OLOGIC0_TFB_LOCAL", + "IOI_IMUX41_0", + "IOI_WW4C3_0", + "IOI_LOGIC_OUTS23_0", + "IOI_RCLK_DIV_CE0", + "RIOI_ODELAY1_OFDLY2", + "IOI_SW2A3_1", + "IOI_EE4B3_0", + "IOI_IOCLK0", + "IOI_EE4BEG0_0", + "IOI_ODELAY0_INC", + "IOI_IMUX6_0", + "IOI_IMUX40_0", + "IOI_IMUX10_1", + "IOI_WR1END3_0", + "RIOI_ILOGIC0_DDLY", + "IOI_IMUX37_1", + "IOI_OLOGIC0_REV", + "IOI_OLOGIC0_D1", + "IOI_IOCLK1", + "IOI_RCLK_FORIO1", + "IOI_ODELAY1_LD", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_WW4A1_1", + "IOI_NE4C0_0", + "IOI_NW4A2_1", + "IOI_LOGIC_OUTS6_1", + "IOI_LH3_1", + "IOI_IMUX33_0", + "IOI_IMUX13_0", + "IOI_IMUX9_0", + "IOI_EE4BEG0_1", + "IOI_WW2A2_1", + "IOI_WR1END0_1", + "IOI_OLOGIC0_T3", + "IOI_EE4A2_0", + "IOI_IMUX26_0", + "IOI_IMUX0_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX3_0", + "IOI_EE4B2_0", + "RIOI_IBUF_DISABLE0", + "IOI_SW2A2_1", + "IOI_OLOGIC0_OCE", + "IOI_ILOGIC0_CE1", + "IOI_LOGIC_OUTS8_0", + "IOI_SE2A2_1", + "IOI_WW2END0_0", + "IOI_SW2A1_0", + "RIOI_OSOUT10", + "IOI_RCLK_FORIO2", + "RIOI_OLOGIC1_TQ", + "IOI_LH3_0", + "IOI_EE4B1_0", + "IOI_SW4END1_0", + "IOI_WW4A2_0", + "IOI_ER1BEG3_0", + "IOI_LH6_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_IMUX40_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IMUX2_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_BYP1_1", + "IOI_SW4END1_1", + "RIOI_I2GCLK_BOT1", + "RIOI3_IDELAY0_IFDLY2", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_IDELAYCTRL_RDY", + "IOI_ODELAY1_CNTVALUEOUT0", + "IOI_IMUX44_0", + "IOI_NW2A2_0", + "IOI_OLOGIC1_D4", + "IOI_SW4A1_1", + "IOI_LOGIC_OUTS22_1", + "IOI_RCLK_DIV_CE3_1", + "IOI_OLOGIC0_D6", + "IOI_IDELAY0_CINVCTRL", + "IOI_IMUX25_1", + "IOI_WW4END1_1", + "IOI_WW4END0_1", + "IOI_SE4BEG2_0", + "IOI_LOGIC_OUTS16_0", + "IOI_NW4END3_0", + "IOI_NE4BEG2_0", + "IOI_DCI_DCIDONE", + "IOI_OLOGIC1_TBYTEIN", + "IOI_ILOGIC0_CLKDIVP", + "IOI_IMUX13_1", + "IOI_LOGIC_OUTS7_0", + "IOI_IMUX_RC1", + "IOI_CLK0_1", + "IOI_NE2A3_1", + "IOI_DCI_TSTRST0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS13_0", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_IDELAY1_INC", + "IOI_OLOGIC1_OCE", + "IOI_LEAF_GCLK2", + "IOI_CLK1_1", + "RIOI_T1", + "RIOI_ISOUT11", + "IOI_NE4C2_1", + "IOI_WW4B0_0", + "IOI_ODELAY1_CNTVALUEIN0", + "IOI_WL1END3_1", + "IOI_IMUX28_0", + "IOI_NW4END1_0", + "IOI_OLOGIC1_D7", + "IOI_LOGIC_OUTS11_0", + "IOI_IDELAY0_CNTVALUEIN0", + "RIOI_IDELAY1_IDATAIN", + "IOI_IMUX18_1", + "IOI_WW4A0_1", + "RIOI_I0", + "IOI_OLOGIC0_D8", + "IOI_IMUX38_1", + "IOI_IMUX21_0", + "IOI_EE2BEG1_1", + "IOI_EE4B0_0", + "IOI_FAN4_0", + "IOI_IDELAYCTRL_RST", + "IOI_SW4A2_0", + "IOI_NW2A0_0", + "IOI_OCLKM_0", + "IOI_EE2BEG0_1", + "IOI_LOGIC_OUTS14_1", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS21_0", + "IOI_ODELAY1_CNTVALUEIN1", + "IOI_ILOGIC1_OCLK", + "RIOI_DIFF_TERM_INT_EN", + "IOI_IMUX17_1", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_SW4END3_1", + "IOI_ODELAY1_CLKIN", + "IOI_NE2A1_0", + "IOI_EE4A2_1", + "IOI_OCLKM_1", + "RIOI_OLOGIC1_CLKDIVF", + "IOI_IMUX43_0", + "IOI_LH8_1", + "IOI_RCLK_DIV_CE1", + "IOI_LOGIC_OUTS17_0", + "IOI_SE2A3_0", + "IOI_ILOGIC1_Q6", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LH9_0", + "IOI_OLOGIC0_D2", + "IOI_OLOGIC0_CLKDIVB", + "RIOI_ILOGIC0_D", + "IOI_IMUX30_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_LOGIC_OUTS0_0", + "IOI_WW2A1_0", + "IOI_BYP7_1", + "RIOI_ODELAY0_DATAOUT", + "RIOI_ODELAY0_ODATAIN", + "IOI_SE4C1_0", + "IOI_IMUX39_1", + "IOI_OCLK_1", + "IOI_EL1BEG0_1", + "IOI_ILOGIC0_Q4", + "IOI_IMUX45_1", + "IOI_IMUX20_0", + "RIOI_ODELAY0_OFDLY0", + "IOI_ODELAY1_REGRST", + "IOI_OLOGIC0_D5", + "IOI_ODELAY1_INC", + "IOI_ODELAY1_CNTVALUEIN3", + "RIOI_OLOGIC0_CLKDIVF", + "IOI_WW2A0_1", + "IOI_NW2A1_0", + "IOI_WW2A2_0", + "IOI_EE2BEG3_1", + "IOI_ILOGIC0_Q8", + "IOI_IMUX24_0", + "IOI_OLOGIC0_T2", + "IOI_IDELAY0_LD", + "IOI_FAN5_1", + "IOI_OLOGIC1_T2", + "IOI_LOGIC_OUTS3_1", + "RIOI_ISOUT20", + "IOI_FAN3_1", + "IOI_BYP0_0", + "IOI_IMUX35_1", + "IOI_ILOGIC1_OCLKB", + "IOI_IMUX27_1", + "IOI_WW4END3_1", + "IOI_BLOCK_OUTS2_1", + "RIOI_O1", + "IOI_EE2BEG2_0", + "IOI_NE2A3_0", + "IOI_SE2A1_1", + "IOI_NE4BEG3_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_LH12_0", + "RIOI3_IDELAY0_IFDLY1", + "IOI_LH2_1", + "IOI_ER1BEG3_1", + "IOI_LH1_1", + "IOI_ILOGIC1_CE2", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_FAN4_1", + "IOI_IDELAY0_CE", + "IOI_EE4C2_1", + "IOI_OLOGIC0_CLK", + "IOI_LOGIC_OUTS12_1", + "RIOI_ISIN21", + "IOI_SW2A3_0", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_ODELAY1_CNTVALUEIN2", + "RIOI_ILOGIC1_TFB", + "IOI_SW2A1_1", + "IOI_LH1_0", + "IOI_FAN1_1", + "IOI_LOGIC_OUTS10_1", + "RIOI_OSIN21", + "IOI_LOGIC_OUTS22_0", + "IOI_IMUX34_1", + "IOI_WW4A1_0", + "IOI_FAN7_0", + "IOI_IDELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OCLK_0", + "IOI_ODELAY0_REGRST", + "IOI_LOGIC_OUTS15_0", + "IOI_LEAF_GCLK0", + "IOI_EE2A0_1", + "IOI_IMUX12_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_IMUX23_1", + "IOI_ODELAY0_CNTVALUEIN2", + "RIOI_ODELAY1_OFDLY1", + "IOI_LOGIC_OUTS15_1", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_EL1BEG3_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IMUX39_0", + "IOI_WR1END0_0", + "IOI_ODELAY1_CNTVALUEIN4", + "IOI_IMUX19_0", + "IOI_RCLK_FORIO3", + "IOI_BYP1_0", + "IOI_ILOGIC0_Q2", + "RIOI_KEEPER_INT_EN_0", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_NW2A3_1", + "IOI_IDELAY0_C", + "RIOI_IDELAY1_DATAOUT", + "IOI_NW2A2_1", + "IOI_SW4END2_0", + "IOI_SW4END0_0", + "IOI_IMUX32_1", + "RIOI_IDELAY0_DATAOUT", + "IOI_IMUX19_1", + "RIOI_OLOGIC0_OFB", + "IOI_SW2A0_0", + "IOI_IMUX46_0", + "IOI_WR1END1_0", + "RIOI3_IDELAY0_IFDLY0", + "IOI_LOGIC_OUTS19_0", + "IOI_LOGIC_OUTS1_0", + "IOI_IMUX8_0", + "IOI_WW4C2_1", + "IOI_WW4C3_1", + "IOI_WW2END3_1", + "RIOI_DCI_T_TERM1", + "IOI_LH5_1", + "IOI_ODELAY1_CE", + "IOI_ILOGIC1_CLKDIVP", + "IOI_OLOGIC0_T4", + "IOI_NE4C2_0", + "IOI_IMUX31_1", + "IOI_NE4C3_0", + "IOI_NW4END2_1", + "IOI_IMUX7_1", + "IOI_IDELAY1_LD", + "IOI_LOGIC_OUTS23_1", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_LOGIC_OUTS9_0", + "IOI_EE2A0_0", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_WW4A3_1", + "IOI_IMUX9_1", + "IOI_NW2A1_1", + "IOI_IMUX1_0", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS9_1", + "IOI_IMUX42_1", + "IOI_RCLK_DIV_CLR3", + "IOI_IMUX21_1", + "IOI_EE2BEG0_0", + "IOI_IMUX1_1", + "RIOI_PU_INT_EN_1", + "IOI_OLOGIC1_T4", + "IOI_LH7_1", + "IOI_LOGIC_OUTS0_1", + "IOI_ILOGIC1_O", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_LOGIC_OUTS2_0", + "IOI_FAN0_1", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_ILOGIC0_OCLK", + "IOI_IMUX30_0", + "IOI_SE4C1_1", + "IOI_NE4BEG0_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LOGIC_OUTS4_1", + "IOI_WL1END2_1", + "IOI_LEAF_GCLK5", + "RIOI3_IDELAY1_IFDLY0", + "IOI_IMUX43_1", + "IOI_EE2BEG2_1", + "RIOI_ILOGIC0_OFB", + "IOI_NW4A2_0", + "IOI_ER1BEG1_1", + "IOI_NW4END0_0", + "IOI_BYP5_0", + "RIOI_OLOGIC1_OQ", + "IOI_ILOGIC1_Q3", + "IOI_LH4_1", + "IOI_IMUX37_0", + "RIOI_DCI_T_TERM0", + "IOI_IDELAY1_DATAIN", + "IOI_IMUX_RC3", + "IOI_ILOGIC0_CLKB", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IDELAY1_CNTVALUEIN3", + "RIOI_OSIN10", + "IOI_IDELAY1_CNTVALUEIN2", + "IOI_IMUX16_0", + "IOI_SW4A2_1", + "RIOI_OSOUT11", + "RIOI_T0", + "IOI_WW4END0_0", + "IOI_BLOCK_OUTS2_0", + "IOI_EE4BEG2_1", + "IOI_NW2A3_0", + "IOI_IMUX_RC0", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WR1END3_1", + "IOI_NW4END1_1", + "IOI_SE2A2_0", + "IOI_ILOGIC0_Q6", + "IOI_NW4A3_1", + "IOI_EE4B2_1", + "IOI_SE4BEG3_0", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_IMUX36_0", + "IOI_LOGIC_OUTS5_0", + "IOI_LH8_0", + "IOI_IMUX12_0", + "IOI_EE4C3_0", + "IOI_ODELAY1_CNTVALUEOUT2", + "IOI_SW4END0_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_OLOGIC1_CLKDIVFB", + "RIOI_I2GCLK_TOP0", + "IOI_IMUX0_1", + "RIOI_OSIN11", + "IOI_CLK1_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_OLOGIC0_D7", + "IOI_BLOCK_OUTS3_1", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_WW4END3_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_OLOGIC1_D6", + "IOI_IMUX29_0", + "IOI_LOGIC_OUTS18_0", + "IOI_WL1END1_0", + "IOI_LH6_1", + "IOI_EL1BEG0_0", + "IOI_ILOGIC1_Q2", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_LEAF_GCLK1", + "IOI_EE2A1_0", + "IOI_WW4B1_0", + "IOI_DCI_TSTHLP", + "IOI_EE4A0_0", + "IOI_BYP3_0", + "IOI_FAN6_0", + "IOI_LOGIC_OUTS10_0", + "IOI_SE4BEG2_1", + "RIOI_OLOGIC1_TFB", + "IOI_IMUX29_1", + "RIOI_OSIN20", + "IOI_IDELAY0_LDPIPEEN", + "IOI_ILOGIC0_SR", + "IOI_WW4A0_0", + "IOI_NE4BEG2_1", + "IOI_IDELAY1_CE", + "IOI_WL1END0_0", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IDELAY0_INC", + "IOI_SE4C0_1", + "IOI_OLOGIC1_T3", + "IOI_LH10_0", + "RIOI_ODELAY1_DATAOUT", + "IOI_EE4A3_0", + "IOI_ILOGIC1_CE1", + "IOI_FAN7_1", + "IOI_WW4B3_0", + "IOI_WL1END0_1", + "IOI_IMUX45_0", + "IOI_ODELAY1_C", + "IOI_LH12_1", + "IOI_WW2END3_0", + "IOI_WR1END2_0", + "IOI_IMUX11_0", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_NE2A0_0", + "RIOI_ODELAY0_OFDLY2", + "IOI_NW4END0_1", + "IOI_WW4A2_1", + "IOI_EL1BEG3_1", + "RIOI_ISOUT10", + "IOI_EE2A3_1", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_WR1END2_1", + "RIOI_ILOGIC0_TFB", + "IOI_ODELAY0_LD", + "RIOI_ODELAY1_ODATAIN", + "IOI_MONITOR_P", + "IOI_EE4BEG3_1", + "IOI_WW2END0_1", + "IOI_OLOGIC0_CLKB", + "IOI_RCLK_DIV_CE2", + "IOI_OLOGIC1_D2", + "IOI_LH11_1", + "IOI_IMUX34_0", + "RIOI_IBUF0", + "IOI_LH9_1", + "IOI_BYP6_0", + "IOI_ILOGIC1_BITSLIP", + "RIOI_OSOUT21", + "IOI_SE4BEG3_1", + "IOI_TBYTEIN", + "IOI_WW4B2_1", + "IOI_ODELAY1_CNTVALUEOUT4", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS12_0", + "IOI_NW4A3_0", + "IOI_SE4C0_0", + "IOI_NE2A1_1", + "IOI_LOGIC_OUTS20_1", + "IOI_SW4A3_0", + "IOI_SE4C2_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_BLOCK_OUTS1_1", + "IOI_EE4A0_1", + "IOI_WL1END3_0", + "IOI_WW2A3_0", + "IOI_CLK0_0", + "IOI_NE4BEG1_0", + "IOI_OLOGIC1_TCE", + "IOI_OLOGIC1_D3", + "IOI_LOGIC_OUTS6_0", + "IOI_IMUX2_1", + "IOI_ODELAY1_CNTVALUEOUT1", + "RIOI_O0", + "IOI_IMUX44_1", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE4A3_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX5_1", + "IOI_EE2A1_1", + "IOI_WW4B3_1", + "IOI_ILOGIC1_Q4", + "IOI_WW2A1_1", + "IOI_INT_DCI_EN", + "IOI_IMUX47_1", + "IOI_IMUX3_1", + "IOI_IMUX6_1", + "RIOI_PD_INT_EN_0", + "IOI_NE2A2_0", + "IOI_WW4B2_0", + "IOI_FAN6_1", + "IOI_BLOCK_OUTS3_0", + "IOI_IDELAY0_DATAIN", + "IOI_EE4B0_1", + "IOI_LOGIC_OUTS13_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_LH11_0", + "IOI_LH10_1", + "IOI_NW4A0_0", + "RIOI_ODELAY0_OFDLY1", + "IOI_BYP2_1", + "IOI_LOGIC_OUTS5_1", + "IOI_NW4END2_0", + "IOI_WW4C1_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WR1END1_1", + "RIOI3_IDELAY1_IFDLY2", + "RIOI_OLOGIC0_TQ", + "IOI_LOGIC_OUTS16_1", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC1_CLK", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_IMUX7_0", + "IOI_FAN1_0", + "IOI_IMUX41_1", + "IOI_WW2A3_1", + "IOI_SE2A3_1", + "RIOI_PU_INT_EN_0", + "IOI_LOGIC_OUTS2_1", + "IOI_CTRL1_0", + "IOI_RCLK_FORIO0", + "IOI_IMUX8_1", + "IOI_SW4A0_0", + "IOI_BLOCK_OUTS1_0", + "RIOI_IBUF_DISABLE1", + "IOI_WW4A3_0", + "IOI_ER1BEG0_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_RCLK_DIV_CLR1_1", + "IOI_RCLK_DIV_CLR2", + "IOI_NW4A1_1", + "IOI_EL1BEG1_0", + "IOI_FAN2_0", + "IOI_CTRL0_0", + "IOI_ILOGIC1_Q5", + "IOI_SE4BEG1_0", + "IOI_OLOGIC0_SR", + "RIOI_PD_INT_EN_1", + "IOI_ODELAY1_LDPIPEEN", + "IOI_LH2_0", + "IOI_EE4C3_1", + "IOI_ODELAY0_CE", + "IOI_EE2A3_0", + "IOI_OLOGIC1_D1", + "IOI_NW4A0_1", + "IOI_LOGIC_OUTS3_0", + "IOI_EE4C0_1", + "IOI_ILOGIC1_CLK", + "RIOI_OSOUT20", + "IOI_WW4C2_0", + "IOI_SW4END2_1", + "RIOI_ILOGIC1_DDLY", + "IOI_IMUX33_1", + "IOI_WW2END1_0", + "IOI_SE2A0_1", + "IOI_LOGIC_OUTS8_1", + "RIOI_IDELAY0_IDATAIN", + "IOI_LH5_0", + "RIOI3_IDELAY1_IFDLY1", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_ILOGIC0_Q1", + "IOI_OLOGIC1_CLKDIVB", + "IOI_NE4C1_1", + "IOI_NE4BEG0_1", + "IOI_OLOGIC1_SR", + "IOI_EE4B1_1", + "RIOI_ODELAY1_OFDLY0", + "IOI_IMUX14_1", + "IOI_ODELAY0_C", + "IOI_IMUX35_0", + "IOI_RCLK_DIV_CLR0", + "IOI_ILOGIC1_SR", + "IOI_NE4BEG1_1", + "IOI_BYP6_1", + "RIOI_OLOGIC0_OQ", + "IOI_ER1BEG2_1", + "IOI_IMUX4_0", + "IOI_EE4BEG2_0", + "IOI_LOGIC_OUTS4_0", + "IOI_NE2A2_1", + "RIOI_ILOGIC1_OFB", + "IOI_LOGIC_OUTS7_1", + "IOI_IMUX24_1", + "IOI_IMUX18_0", + "IOI_NE4C1_0", + "IOI_EE4BEG1_1", + "RIOI_IBUF1", + "RIOI_I2GCLK_TOP1", + "IOI_BYP4_0", + "RIOI_ISIN10", + "IOI_EE2A2_1", + "IOI_ER1BEG1_0", + "IOI_WL1END1_1", + "IOI_IMUX31_0", + "IOI_ER1BEG2_0", + "IOI_IMUX28_1", + "IOI_WW4C0_1", + "IOI_SE4C2_0", + "IOI_LOGIC_OUTS17_1", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_IMUX_RC2", + "IOI_WW4END2_0" + ], + "tile_type": "RIOI3", + "sites": [ + { + "site_pins": { + "T2": "IOI_OLOGIC1_T2", + "D5": "IOI_OLOGIC1_D5", + "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", + "D8": "IOI_OLOGIC1_D8", + "SR": "IOI_OLOGIC1_SR", + "SHIFTOUT1": "RIOI_OSOUT11", + "T4": "IOI_OLOGIC1_T4", + "SHIFTIN1": null, + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "OCE": "IOI_OLOGIC1_OCE", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "CLKB": "IOI_OLOGIC1_CLKB", + "OQ": "RIOI_OLOGIC1_OQ", + "D3": "IOI_OLOGIC1_D3", + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "SHIFTIN2": null, + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "D1": "IOI_OLOGIC1_D1", + "CLK": "IOI_OLOGIC1_CLK", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "T1": "IOI_OLOGIC1_T1", + "D4": "IOI_OLOGIC1_D4", + "TCE": "IOI_OLOGIC1_TCE", + "D2": "IOI_OLOGIC1_D2", + "SHIFTOUT2": "RIOI_OSOUT21", + "OFB": "RIOI_OLOGIC1_OFB", + "TFB": "RIOI_OLOGIC1_TFB", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "T3": "IOI_OLOGIC1_T3", + "D6": "IOI_OLOGIC1_D6", + "TQ": "RIOI_OLOGIC1_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "CLK": "IOI_ILOGIC1_CLK", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "Q3": "IOI_ILOGIC1_Q3", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "D": "RIOI_ILOGIC1_D", + "SR": "IOI_ILOGIC1_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC1_CE1", + "Q8": "IOI_ILOGIC1_Q8", + "SHIFTIN2": "RIOI_ISIN21", + "Q2": "IOI_ILOGIC1_Q2", + "CE2": "IOI_ILOGIC1_CE2", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "SHIFTOUT2": "RIOI_ISOUT21", + "O": "IOI_ILOGIC1_O", + "OFB": "RIOI_ILOGIC1_OFB", + "TFB": "RIOI_ILOGIC1_TFB", + "Q4": "IOI_ILOGIC1_Q4", + "CLKB": "IOI_ILOGIC1_CLKB", + "Q1": "IOI_ILOGIC1_Q1", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN1": "RIOI_ISIN11", + "Q6": "IOI_ILOGIC1_Q6", + "DDLY": "RIOI_ILOGIC1_DDLY", + "SHIFTOUT1": "RIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC1_Q7", + "OCLKB": "IOI_ILOGIC1_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "T2": "IOI_OLOGIC0_T2", + "D5": "IOI_OLOGIC0_D5", + "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", + "D8": "IOI_OLOGIC0_D8", + "SR": "IOI_OLOGIC0_SR", + "SHIFTOUT1": "RIOI_OSOUT10", + "T4": "IOI_OLOGIC0_T4", + "SHIFTIN1": "RIOI_OSIN10", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "OCE": "IOI_OLOGIC0_OCE", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "CLKB": "IOI_OLOGIC0_CLKB", + "OQ": "RIOI_OLOGIC0_OQ", + "D3": "IOI_OLOGIC0_D3", + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "SHIFTIN2": "RIOI_OSIN20", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "D1": "IOI_OLOGIC0_D1", + "CLK": "IOI_OLOGIC0_CLK", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "T1": "IOI_OLOGIC0_T1", + "D4": "IOI_OLOGIC0_D4", + "TCE": "IOI_OLOGIC0_TCE", + "D2": "IOI_OLOGIC0_D2", + "SHIFTOUT2": "RIOI_OSOUT20", + "OFB": "RIOI_OLOGIC0_OFB", + "TFB": "RIOI_OLOGIC0_TFB", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "T3": "IOI_OLOGIC0_T3", + "D6": "IOI_OLOGIC0_D6", + "TQ": "RIOI_OLOGIC0_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "CLK": "IOI_ILOGIC0_CLK", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "Q3": "IOI_ILOGIC0_Q3", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "D": "RIOI_ILOGIC0_D", + "SR": "IOI_ILOGIC0_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC0_CE1", + "Q8": "IOI_ILOGIC0_Q8", + "SHIFTIN2": null, + "Q2": "IOI_ILOGIC0_Q2", + "CE2": "IOI_ILOGIC0_CE2", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "SHIFTOUT2": "RIOI_ISOUT20", + "O": "IOI_ILOGIC0_O", + "OFB": "RIOI_ILOGIC0_OFB", + "TFB": "RIOI_ILOGIC0_TFB", + "Q4": "IOI_ILOGIC0_Q4", + "CLKB": "IOI_ILOGIC0_CLKB", + "Q1": "IOI_ILOGIC0_Q1", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN1": null, + "Q6": "IOI_ILOGIC0_Q6", + "DDLY": "RIOI_ILOGIC0_DDLY", + "SHIFTOUT1": "RIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC0_Q7", + "OCLKB": "IOI_ILOGIC0_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "IFDLY0": "RIOI3_IDELAY1_IFDLY0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", + "LD": "IOI_IDELAY1_LD", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "IDATAIN": "RIOI_IDELAY1_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "IFDLY2": "RIOI3_IDELAY1_IFDLY2", + "C": "IOI_IDELAY1_C", + "IFDLY1": "RIOI3_IDELAY1_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "DATAOUT": "RIOI_IDELAY1_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "IFDLY0": "RIOI3_IDELAY0_IFDLY0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", + "LD": "IOI_IDELAY0_LD", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "IDATAIN": "RIOI_IDELAY0_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "IFDLY2": "RIOI3_IDELAY0_IFDLY2", + "C": "IOI_IDELAY0_C", + "IFDLY1": "RIOI3_IDELAY0_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "DATAOUT": "RIOI_IDELAY0_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_RIOI3_SING.json b/artix7/tile_type_RIOI3_SING.json index 0386bf1..edccdbb 100644 --- a/artix7/tile_type_RIOI3_SING.json +++ b/artix7/tile_type_RIOI3_SING.json @@ -1,1878 +1,1878 @@ { - "wires": [ - "IOI_LOGIC_OUTS2_0", - "IOI_WW4A1_0", - "IOI_IMUX7_0", - "IOI_SE4BEG2_0", - "RIOI3_IDELAY0_IFDLY1", - "RIOI_OLOGIC0_TFB_LOCAL", - "IOI_ILOGIC0_CLK", - "IOI_SING_RCLK_FORIO3", - "IOI_NW4A2_0", - "IOI_NW4END1_0", - "IOI_LOGIC_OUTS11_0", - "IOI_SE4C0_0", - "IOI_LOGIC_OUTS17_0", - "IOI_WR1END3_0", - "IOI_NE2A2_0", - "IOI_ILOGIC0_CLKDIV", - "IOI_IMUX20_0", - "IOI_OLOGIC0_TCE", - "IOI_EE2BEG2_0", - "IOI_LH10_0", - "RIOI_ISOUT20", - "IOI_ILOGIC0_CE2", - "IOI_ODELAY0_C", - "RIOI_ODELAY0_OFDLY0", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_SING_LEAF_GCLK4", - "IOI_IMUX5_0", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_SW4END0_0", - "IOI_IMUX35_0", - "IOI_WW4B3_0", - "IOI_OLOGIC0_D2", - "IOI_SING_TBYTEIN", - "IOI_OLOGIC0_CLKDIV", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_SE4C1_0", - "IOI_ODELAY0_CE", - "IOI_NE2A1_0", - "IOI_IMUX1_0", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_REV", - "RIOI_OLOGIC0_TQ", - "IOI_IMUX0_0", - "RIOI_ISOUT10", - "IOI_ER1BEG0_0", - "IOI_IMUX36_0", - "IOI_ILOGIC0_BITSLIP", - "RIOI_ILOGIC0_DDLY", - "IOI_NE4C3_0", - "IOI_IMUX10_0", - "IOI_EE4B3_0", - "IOI_LH4_0", - "IOI_LOGIC_OUTS20_0", - "IOI_NW4END2_0", - "IOI_OLOGIC0_SR", - "IOI_LH1_0", - "IOI_BLOCK_OUTS1_0", - "IOI_WW4B1_0", - "IOI_LH2_0", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ODELAY0_LD", - "IOI_WW4A3_0", - "IOI_OLOGIC0_OCE", - "IOI_IMUX8_0", - "IOI_CTRL0_0", - "IOI_LOGIC_OUTS8_0", - "IOI_ILOGIC0_CLKB", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_SW2A2_0", - "IOI_NE2A0_0", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_INC", - "IOI_OLOGIC0_T4", - "IOI_ER1BEG1_0", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ILOGIC0_O", - "IOI_EL1BEG2_0", - "IOI_EE4A1_0", - "IOI_SW4A1_0", - "IOI_NE4BEG2_0", - "IOI_SW2A0_0", - "IOI_IMUX24_0", - "RIOI_ISIN20", - "IOI_FAN5_0", - "RIOI_ODELAY0_OFDLY2", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_LOGIC_OUTS21_0", - "IOI_WW4C3_0", - "RIOI_PU_INT_EN_1", - "IOI_OLOGIC0_D7", - "IOI_IMUX37_0", - "IOI_IMUX6_0", - "RIOI_IBUF0", - "IOI_LOGIC_OUTS4_0", - "IOI_ILOGIC0_Q8", - "RIOI3_IDELAY0_IFDLY2", - "IOI_WW2A2_0", - "IOI_NW4END0_0", - "RIOI_OLOGIC0_OFB", - "IOI_BLOCK_OUTS3_0", - "IOI_IMUX38_0", - "IOI_IDELAY0_CINVCTRL", - "IOI_IMUX30_0", - "IOI_IMUX33_0", - "IOI_EE4A2_0", - "IOI_IMUX4_0", - "IOI_SW4END2_0", - "IOI_IMUX31_0", - "IOI_IMUX15_0", - "IOI_ILOGIC0_Q2", - "IOI_EE4C3_0", - "IOI_NE4BEG1_0", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_BYP7_0", - "IOI_SW4A2_0", - "IOI_IMUX42_0", - "IOI_SING_LEAF_GCLK5", - "IOI_WR1END0_0", - "RIOI_OSIN20", - "IOI_NE4C1_0", - "IOI_IDELAY0_C", - "IOI_IMUX29_0", - "RIOI_ODELAY0_ODATAIN", - "IOI_SE2A2_0", - "IOI_LOGIC_OUTS13_0", - "IOI_BYP4_0", - "IOI_OLOGIC0_REV", - "IOI_LOGIC_OUTS6_0", - "IOI_WW2A1_0", - "IOI_SING_IOCLK1", - "IOI_IDELAY0_DATAIN", - "IOI_SW4A3_0", - "IOI_EE4BEG2_0", - "IOI_LH7_0", - "RIOI_ILOGIC0_D", - "IOI_WW4C1_0", - "IOI_IMUX9_0", - "IOI_BYP5_0", - "IOI_ER1BEG3_0", - "IOI_LOGIC_OUTS18_0", - "IOI_NW4A0_0", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ILOGIC0_Q3", - "IOI_IDELAY0_LDPIPEEN", - "IOI_WW2END2_0", - "IOI_IMUX12_0", - "RIOI_OLOGIC0_OQ", - "RIOI_PD_INT_EN_1", - "IOI_IMUX23_0", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS23_0", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_WW4A0_0", - "IOI_SE2A0_0", - "IOI_WW2END3_0", - "IOI_IMUX21_0", - "IOI_SING_IOCLK2", - "IOI_NE4BEG3_0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_EE4BEG0_0", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CE", - "IOI_NW4END3_0", - "IOI_SE4C3_0", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_BYP3_0", - "IOI_NW4A1_0", - "IOI_SE4BEG0_0", - "IOI_IMUX14_0", - "IOI_CLK1_0", - "IOI_SE4BEG3_0", - "IOI_LOGIC_OUTS0_0", - "IOI_WW2END1_0", - "IOI_OLOGIC0_D6", - "IOI_EE2A3_0", - "IOI_IMUX28_0", - "IOI_OCLK_0", - "IOI_LOGIC_OUTS16_0", - "IOI_IMUX18_0", - "IOI_NW4A3_0", - "RIOI_OLOGIC0_TFB", - "RIOI3_IDELAY0_IFDLY0", - "IOI_WW4A2_0", - "RIOI_ILOGIC0_TFB", - "IOI_NE4C0_0", - "IOI_IDELAY0_LD", - "IOI_EE2A0_0", - "IOI_NW2A1_0", - "RIOI_ILOGIC0_OFB", - "IOI_IMUX44_0", - "IOI_LOGIC_OUTS9_0", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_IMUX16_0", - "RIOI_T0", - "IOI_WL1END3_0", - "IOI_EE2A1_0", - "IOI_FAN1_0", - "IOI_LOGIC_OUTS7_0", - "IOI_EE4A0_0", - "IOI_LOGIC_OUTS22_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_SING_LEAF_GCLK2", - "IOI_IMUX11_0", - "IOI_WW4C2_0", - "IOI_NW2A3_0", - "IOI_IMUX34_0", - "IOI_WR1END2_0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_SW4A0_0", - "IOI_IMUX22_0", - "IOI_WR1END1_0", - "IOI_OLOGIC0_T3", - "IOI_IMUX17_0", - "IOI_EE4B0_0", - "RIOI_ODELAY0_OFDLY1", - "IOI_WW4B2_0", - "IOI_FAN6_0", - "IOI_WL1END0_0", - "IOI_OCLKM_0", - "IOI_SING_LEAF_GCLK1", - "IOI_CLK0_0", - "IOI_EL1BEG0_0", - "IOI_LOGIC_OUTS15_0", - "IOI_OLOGIC0_CLK", - "IOI_IMUX39_0", - "IOI_WL1END1_0", - "RIOI_I0", - "IOI_WW4B0_0", - "IOI_WL1END2_0", - "IOI_IMUX41_0", - "IOI_EE4C0_0", - "IOI_SING_RCLK_FORIO0", - "IOI_NW2A0_0", - "IOI_WW4END3_0", - "IOI_SE2A3_0", - "IOI_WW2A3_0", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_OLOGIC0_D4", - "IOI_ILOGIC0_CE1", - "IOI_SE4BEG1_0", - "IOI_EE2BEG3_0", - "IOI_ODELAY0_CNTVALUEIN1", - "RIOI_OSOUT20", - "IOI_EL1BEG1_0", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_ER1BEG2_0", - "IOI_WW4C0_0", - "IOI_ILOGIC0_Q5", - "RIOI_DCI_T_TERM0", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_EE4BEG3_0", - "IOI_IMUX25_0", - "IOI_NE4BEG0_0", - "IOI_SW4END1_0", - "IOI_FAN0_0", - "IOI_WW4END0_0", - "IOI_EE4BEG1_0", - "IOI_FAN7_0", - "IOI_LOGIC_OUTS1_0", - "IOI_EE2BEG0_0", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC0_OCLKB", - "IOI_EE4C1_0", - "IOI_BYP2_0", - "IOI_SING_LEAF_GCLK0", - "IOI_IMUX43_0", - "IOI_IMUX46_0", - "IOI_IMUX27_0", - "RIOI_IBUF_DISABLE0", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_D8", - "IOI_NW2A2_0", - "RIOI_KEEPER_INT_EN_1", - "IOI_EE4C2_0", - "IOI_LH11_0", - "IOI_ILOGIC0_Q6", - "IOI_CTRL1_0", - "IOI_SING_IOCLK3", - "IOI_EE4A3_0", - "IOI_OLOGIC0_CLKB", - "IOI_IMUX40_0", - "RIOI_O0", - "IOI_LH5_0", - "IOI_IMUX47_0", - "IOI_PHASER_TO_IO_OCLK", - "RIOI_OSIN10", - "RIOI_IDELAY0_IDATAIN", - "IOI_LOGIC_OUTS12_0", - "IOI_FAN2_0", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_LOGIC_OUTS5_0", - "IOI_SING_LEAF_GCLK3", - "IOI_FAN4_0", - "IOI_IMUX2_0", - "IOI_WW2END0_0", - "IOI_BLOCK_OUTS2_0", - "IOI_WW4END1_0", - "IOI_EE4B1_0", - "IOI_OLOGIC0_T1", - "IOI_IMUX3_0", - "IOI_ODELAY0_CLKIN", - "IOI_EE4B2_0", - "IOI_SE2A1_0", - "IOI_SING_RCLK_FORIO1", - "IOI_BYP6_0", - "IOI_EE2BEG1_0", - "IOI_IMUX32_0", - "IOI_WW2A0_0", - "IOI_ILOGIC0_Q7", - "IOI_PHASER_TO_IO_ICLK", - "IOI_NE4C2_0", - "IOI_EL1BEG3_0", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_FAN3_0", - "IOI_SW4END3_0", - "IOI_ODELAY0_LDPIPEEN", - "IOI_SE4C2_0", - "RIOI_OSOUT10", - "IOI_ODELAY0_INC", - "IOI_BYP1_0", - "IOI_NE2A3_0", - "IOI_ODELAY0_REGRST", - "IOI_SING_RCLK_FORIO2", - "IOI_SW2A3_0", - "IOI_ILOGIC0_CLKDIVP", - "IOI_LOGIC_OUTS19_0", - "IOI_EE2A2_0", - "IOI_OLOGIC0_D1", - "IOI_LH9_0", - "IOI_LH6_0", - "RIOI_ODELAY0_DATAOUT", - "IOI_IMUX19_0", - "IOI_LH8_0", - "IOI_LOGIC_OUTS10_0", - "RIOI_IDELAY0_DATAOUT", - "IOI_ILOGIC0_OCLK", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_SW2A1_0", - "RIOI_OLOGIC0_CLKDIVF", - "IOI_LOGIC_OUTS14_0", - "IOI_OLOGIC0_T2", - "IOI_BLOCK_OUTS0_0", - "IOI_LH3_0", - "IOI_LH12_0", - "IOI_SING_IOCLK0", - "IOI_IMUX26_0", - "IOI_IMUX45_0", - "IOI_IMUX13_0", - "IOI_ODELAY0_CINVCTRL", - "IOI_BYP0_0", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ILOGIC0_Q4", - "IOI_WW4END2_0", - "RIOI_ISIN10", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_TBYTEIN" - ], - "sites": [ - { - "prefix": "OLOGIC", - "y_coord": 0, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC0_D1", - "D3": "IOI_OLOGIC0_D3", - "SR": "IOI_OLOGIC0_SR", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "TFB": "RIOI_OLOGIC0_TFB", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLK": "IOI_OLOGIC0_CLK", - "T4": "IOI_OLOGIC0_T4", - "OQ": "RIOI_OLOGIC0_OQ", - "D8": "IOI_OLOGIC0_D8", - "T1": "IOI_OLOGIC0_T1", - "D5": "IOI_OLOGIC0_D5", - "SHIFTOUT1": "RIOI_OSOUT10", - "T2": "IOI_OLOGIC0_T2", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "D4": "IOI_OLOGIC0_D4", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D2": "IOI_OLOGIC0_D2", - "TQ": "RIOI_OLOGIC0_TQ", - "T3": "IOI_OLOGIC0_T3", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "OCE": "IOI_OLOGIC0_OCE", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "SHIFTIN1": null, - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "TCE": "IOI_OLOGIC0_TCE", - "OFB": "RIOI_OLOGIC0_OFB", - "SHIFTIN2": null, - "SHIFTOUT2": "RIOI_OSOUT20", - "REV": null, - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "ILOGIC", - "y_coord": 0, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q1": "IOI_ILOGIC0_Q1", - "SR": "IOI_ILOGIC0_SR", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "SHIFTIN2": null, - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "Q3": "IOI_ILOGIC0_Q3", - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "Q8": "IOI_ILOGIC0_Q8", - "TFB": "RIOI_ILOGIC0_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC0_CE1", - "Q2": "IOI_ILOGIC0_Q2", - "Q6": "IOI_ILOGIC0_Q6", - "CLKB": "IOI_ILOGIC0_CLKB", - "Q7": "IOI_ILOGIC0_Q7", - "O": "IOI_ILOGIC0_O", - "CLK": "IOI_ILOGIC0_CLK", - "CE2": "IOI_ILOGIC0_CE2", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "SHIFTIN1": null, - "OCLK": "IOI_ILOGIC0_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "OFB": "RIOI_ILOGIC0_OFB", - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "REV": null, - "CLKDIV": "IOI_ILOGIC0_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IDELAY", - "y_coord": 0, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CE": "IOI_IDELAY0_CE", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "IFDLY2": "RIOI3_IDELAY0_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "LD": "IOI_IDELAY0_LD", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "IFDLY0": "RIOI3_IDELAY0_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "INC": "IOI_IDELAY0_INC", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY0_DATAIN", - "C": "IOI_IDELAY0_C", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "REGRST": "IOI_IDELAY0_REGRST", - "IFDLY1": "RIOI3_IDELAY0_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y0" - } - ], "pips": { - "RIOI3_SING.RIOI_I0->RIOI_ILOGIC0_D": { + "RIOI3_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_D", + "src_wire": "IOI_IMUX34_0", "is_directional": "1", - "src_wire": "RIOI_I0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_BYP7_0->RIOI3_IDELAY0_IFDLY2": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_0", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_CLK1_0->IOI_IDELAY0_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_0", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_DDLY", - "is_directional": "1", - "src_wire": "RIOI_IDELAY0_DATAOUT", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_SING_TBYTEIN", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "RIOI3_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX31_0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "RIOI3_SING.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC0_D", - "is_pseudo": "1" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_I0->RIOI_IDELAY0_IDATAIN": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY0_IDATAIN", - "is_directional": "1", - "src_wire": "RIOI_I0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OQ", - "is_pseudo": "1" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q5", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC0_DDLY", - "is_pseudo": "1" - }, - "RIOI3_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q7", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "RIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX26_0->IOI_IDELAY0_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1" }, "RIOI3_SING.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX8_0->RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_IBUF0->RIOI_I0": { - "can_invert": "0", - "dst_wire": "RIOI_I0", - "is_directional": "1", - "src_wire": "RIOI_IBUF0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q6", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX31_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" }, "RIOI3_SING.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_OFB", - "is_directional": "1", "src_wire": "RIOI_OLOGIC0_OFB", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_OLOGIC0_TQ->>RIOI_T0": { - "can_invert": "0", - "dst_wire": "RIOI_T0", "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TQ", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_OFB" }, - "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "RIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", + "src_wire": "IOI_IMUX22_0", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TQ" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" }, - "RIOI3_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { + "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_BITSLIP", + "src_wire": "IOI_SING_LEAF_GCLK5", "is_directional": "1", - "src_wire": "IOI_IMUX0_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" }, - "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_0", + "src_wire": "IOI_SING_LEAF_GCLK4", "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" }, - "RIOI3_SING.IOI_SING_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { + "RIOI3_SING.RIOI_I0->RIOI_ILOGIC0_D": { "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", + "src_wire": "RIOI_I0", "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX9_0->RIOI_IBUF_DISABLE0": { - "can_invert": "0", - "dst_wire": "RIOI_IBUF_DISABLE0", - "is_directional": "1", - "src_wire": "IOI_IMUX9_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_D" }, "RIOI3_SING.IOI_IMUX35_0->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", - "is_directional": "1", "src_wire": "IOI_IMUX35_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_0", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_OLOGIC0_OQ->>RIOI_O0": { - "can_invert": "0", - "dst_wire": "RIOI_O0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OQ", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q8", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TQ", - "is_pseudo": "1" - }, - "RIOI3_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_FAN4_0->RIOI3_IDELAY0_IFDLY0": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_FAN5_0->RIOI3_IDELAY0_IFDLY1": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_SING.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY0_DATAOUT", - "is_directional": "1", - "src_wire": "RIOI_IDELAY0_IDATAIN", - "is_pseudo": "1" - }, - "RIOI3_SING.IOI_IMUX6_0->RIOI_DCI_T_TERM0": { - "can_invert": "0", - "dst_wire": "RIOI_DCI_T_TERM0", - "is_directional": "1", - "src_wire": "IOI_IMUX6_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_SING_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_SING_IOCLK0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2" }, "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLKM_0": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.RIOI_OLOGIC0_OQ->>RIOI_O0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_O0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.IOI_IMUX31_0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK" + }, + "RIOI3_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { + "can_invert": "0", + "src_wire": "IOI_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "RIOI3_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_IMUX8_0->RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP" + }, + "RIOI3_SING.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY0_DATAOUT" + }, + "RIOI3_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0" + }, + "RIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5" + }, + "RIOI3_SING.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_DDLY" + }, + "RIOI3_SING.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB" + }, + "RIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK" + }, + "RIOI3_SING.RIOI_I0->RIOI_IDELAY0_IDATAIN": { + "can_invert": "0", + "src_wire": "RIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IDATAIN" + }, + "RIOI3_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0" + }, + "RIOI3_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_CLK1_0->IOI_IDELAY0_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C" + }, + "RIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.RIOI_OLOGIC0_TQ->>RIOI_T0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_T0" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", "src_wire": "IOI_SING_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" }, - "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "RIOI3_SING.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", + "src_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL" + }, + "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", "src_wire": "IOI_SING_LEAF_GCLK3", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_IMUX26_0->IOI_IDELAY0_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC" }, "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", "src_wire": "IOI_SING_LEAF_GCLK2", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0" + }, + "RIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" }, "RIOI3_SING.IOI_SING_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", "src_wire": "IOI_SING_RCLK_FORIO2", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR" + }, + "RIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "RIOI3_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OQ" + }, + "RIOI3_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN" + }, + "RIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR" + }, + "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0" + }, + "RIOI3_SING.IOI_FAN5_0->RIOI3_IDELAY0_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY1" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_IMUX31_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_SING_TBYTEIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN" + }, + "RIOI3_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "RIOI3_SING.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0" + }, + "RIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0" + }, + "RIOI3_SING.IOI_FAN4_0->RIOI3_IDELAY0_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY0" + }, + "RIOI3_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2" + }, + "RIOI3_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB" + }, + "RIOI3_SING.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC0_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST" + }, + "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0" + }, + "RIOI3_SING.RIOI_IBUF0->RIOI_I0": { + "can_invert": "0", + "src_wire": "RIOI_IBUF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_I0" + }, + "RIOI3_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "RIOI3_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_SING.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC0_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "RIOI3_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_BYP7_0->RIOI3_IDELAY0_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY2" + }, + "RIOI3_SING.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_TFB" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "RIOI3_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7" + }, + "RIOI3_SING.IOI_IMUX6_0->RIOI_DCI_T_TERM0": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3" + }, + "RIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_SING.IOI_IMUX9_0->RIOI_IBUF_DISABLE0": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE0" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_SING_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_SING_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0" + }, + "RIOI3_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "RIOI3_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4" } }, - "tile_type": "RIOI3_SING" + "wires": [ + "IOI_IMUX42_0", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_EL1BEG3_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_ILOGIC0_CE2", + "IOI_IMUX39_0", + "IOI_SING_IOCLK2", + "IOI_WR1END0_0", + "IOI_IMUX5_0", + "IOI_IMUX19_0", + "IOI_BYP1_0", + "IOI_ILOGIC0_Q2", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_IMUX23_0", + "IOI_SING_LEAF_GCLK4", + "IOI_IDELAY0_C", + "RIOI_OLOGIC0_TFB", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_SW4END2_0", + "IOI_SW4END0_0", + "IOI_WW4END1_0", + "RIOI_IDELAY0_DATAOUT", + "RIOI_OLOGIC0_OFB", + "IOI_IMUX38_0", + "IOI_SW2A0_0", + "IOI_IMUX46_0", + "IOI_WR1END1_0", + "RIOI3_IDELAY0_IFDLY0", + "IOI_LOGIC_OUTS19_0", + "IOI_LOGIC_OUTS1_0", + "IOI_IMUX8_0", + "IOI_BYP2_0", + "IOI_OLOGIC0_T4", + "IOI_NE4C2_0", + "IOI_NE4C3_0", + "IOI_IMUX27_0", + "IOI_IMUX22_0", + "IOI_NW4A1_0", + "IOI_SE2A1_0", + "IOI_EL1BEG2_0", + "IOI_SW4A1_0", + "IOI_LOGIC_OUTS9_0", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_ODELAY0_LDPIPEEN", + "IOI_EE2A0_0", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_IMUX1_0", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_EE4C2_0", + "IOI_EE2BEG1_0", + "IOI_LOGIC_OUTS20_0", + "IOI_WL1END2_0", + "IOI_EE2BEG0_0", + "IOI_FAN5_0", + "RIOI_PU_INT_EN_1", + "IOI_EE2A2_0", + "IOI_WW4C0_0", + "IOI_PHASER_TO_IO_OCLK", + "IOI_OLOGIC0_CLKDIV", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_LOGIC_OUTS2_0", + "IOI_IMUX17_0", + "IOI_WW2END2_0", + "IOI_FAN3_0", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_LOGIC_OUTS14_0", + "IOI_ILOGIC0_OCLK", + "IOI_IMUX30_0", + "IOI_NE4BEG0_0", + "IOI_FAN0_0", + "IOI_SE4BEG0_0", + "IOI_EE2BEG3_0", + "IOI_LH7_0", + "IOI_ILOGIC0_Q3", + "IOI_EE4A1_0", + "IOI_BYP7_0", + "IOI_IMUX25_0", + "RIOI_ILOGIC0_OFB", + "IOI_IDELAY0_REGRST", + "IOI_NW4A2_0", + "IOI_NW4END0_0", + "IOI_BYP5_0", + "IOI_ILOGIC0_OCLKB", + "IOI_IMUX37_0", + "IOI_IMUX47_0", + "RIOI_DCI_T_TERM0", + "IOI_OLOGIC0_D4", + "IOI_SE2A0_0", + "IOI_ILOGIC0_CLKB", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_SW4END3_0", + "IOI_EE4BEG3_0", + "IOI_ILOGIC0_Q7", + "RIOI_OSIN10", + "IOI_IMUX16_0", + "RIOI_T0", + "IOI_WW4END0_0", + "IOI_BLOCK_OUTS2_0", + "IOI_NW2A3_0", + "IOI_SING_LEAF_GCLK1", + "IOI_SING_RCLK_FORIO3", + "IOI_OLOGIC0_D3", + "IOI_EE4C0_0", + "IOI_ODELAY0_CNTVALUEOUT2", + "RIOI_KEEPER_INT_EN_1", + "IOI_SE2A2_0", + "IOI_ILOGIC0_Q6", + "IOI_OLOGIC0_TCE", + "IOI_WW2A0_0", + "IOI_SE4BEG3_0", + "IOI_EE4C1_0", + "IOI_ODELAY0_CLKIN", + "IOI_IMUX36_0", + "IOI_LOGIC_OUTS5_0", + "IOI_LH8_0", + "IOI_IMUX15_0", + "IOI_IMUX12_0", + "IOI_EE4C3_0", + "IOI_ILOGIC0_O", + "IOI_BLOCK_OUTS0_0", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_SE4C3_0", + "IOI_IMUX32_0", + "IOI_CLK1_0", + "IOI_LH4_0", + "IOI_OLOGIC0_D7", + "IOI_IMUX10_0", + "IOI_WW4END3_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_ILOGIC0_REV", + "IOI_SING_LEAF_GCLK0", + "RIOI_ISIN20", + "IOI_IMUX29_0", + "IOI_LOGIC_OUTS18_0", + "IOI_WL1END1_0", + "IOI_EL1BEG0_0", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_OLOGIC0_T1", + "IOI_EE4BEG1_0", + "IOI_EE2A1_0", + "RIOI_OLOGIC0_TFB_LOCAL", + "IOI_IMUX41_0", + "IOI_WW4C3_0", + "IOI_LOGIC_OUTS23_0", + "IOI_WW4B1_0", + "IOI_EE4A0_0", + "IOI_BYP3_0", + "IOI_FAN6_0", + "IOI_LOGIC_OUTS10_0", + "IOI_SING_IOCLK1", + "IOI_EE4B3_0", + "IOI_EE4BEG0_0", + "IOI_ODELAY0_INC", + "IOI_IMUX6_0", + "RIOI_OSIN20", + "IOI_IDELAY0_LDPIPEEN", + "IOI_ILOGIC0_SR", + "IOI_IMUX40_0", + "IOI_WW4A0_0", + "IOI_WR1END3_0", + "IOI_WL1END0_0", + "RIOI_ILOGIC0_DDLY", + "IOI_OLOGIC0_REV", + "IOI_IDELAY0_INC", + "IOI_OLOGIC0_D1", + "IOI_LH10_0", + "IOI_EE4A3_0", + "IOI_WW4B3_0", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_NE4C0_0", + "IOI_SING_LEAF_GCLK3", + "IOI_IMUX45_0", + "IOI_IMUX33_0", + "IOI_IMUX13_0", + "IOI_IMUX9_0", + "IOI_OLOGIC0_T3", + "IOI_WW2END3_0", + "IOI_EE4A2_0", + "IOI_WR1END2_0", + "IOI_IMUX26_0", + "IOI_IMUX11_0", + "IOI_IMUX0_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX3_0", + "IOI_EE4B2_0", + "RIOI_IBUF_DISABLE0", + "IOI_NE2A0_0", + "RIOI_ODELAY0_OFDLY2", + "IOI_OLOGIC0_OCE", + "IOI_ILOGIC0_CE1", + "RIOI_ISOUT10", + "IOI_LOGIC_OUTS8_0", + "IOI_WW2END0_0", + "IOI_SW2A1_0", + "RIOI_ILOGIC0_TFB", + "RIOI_OSOUT10", + "IOI_SING_RCLK_FORIO0", + "IOI_ODELAY0_LD", + "IOI_LH3_0", + "IOI_OLOGIC0_CLKB", + "IOI_EE4B1_0", + "IOI_SW4END1_0", + "IOI_WW4A2_0", + "IOI_ER1BEG3_0", + "IOI_LH6_0", + "IOI_IMUX34_0", + "IOI_ILOGIC0_CLK", + "RIOI_IBUF0", + "IOI_SW2A2_0", + "IOI_BYP6_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_IMUX2_0", + "IOI_SING_LEAF_GCLK5", + "RIOI3_IDELAY0_IFDLY2", + "IOI_IMUX14_0", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_IMUX44_0", + "IOI_NW2A2_0", + "IOI_LOGIC_OUTS12_0", + "IOI_NW4A3_0", + "IOI_SE4C0_0", + "IOI_SING_IOCLK3", + "IOI_OLOGIC0_D6", + "IOI_IDELAY0_CINVCTRL", + "IOI_SW4A3_0", + "IOI_ODELAY0_CINVCTRL", + "IOI_WL1END3_0", + "IOI_WW2A3_0", + "IOI_SE4BEG2_0", + "IOI_LOGIC_OUTS16_0", + "IOI_NW4END3_0", + "IOI_CLK0_0", + "IOI_NE4BEG1_0", + "IOI_NE4BEG2_0", + "IOI_ILOGIC0_CLKDIVP", + "IOI_LOGIC_OUTS7_0", + "IOI_LOGIC_OUTS6_0", + "RIOI_O0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS13_0", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_SING_RCLK_FORIO1", + "IOI_WW4B0_0", + "IOI_IMUX28_0", + "IOI_NW4END1_0", + "IOI_LOGIC_OUTS11_0", + "IOI_IDELAY0_CNTVALUEIN0", + "RIOI_I0", + "IOI_OLOGIC0_D8", + "IOI_NE2A2_0", + "IOI_WW4B2_0", + "IOI_BLOCK_OUTS3_0", + "IOI_IMUX21_0", + "IOI_IDELAY0_DATAIN", + "IOI_EE4B0_0", + "IOI_FAN4_0", + "IOI_OLOGIC0_TBYTEIN", + "IOI_LH11_0", + "IOI_NW4A0_0", + "RIOI_ODELAY0_OFDLY1", + "IOI_SW4A2_0", + "IOI_NW2A0_0", + "IOI_OCLKM_0", + "IOI_NW4END2_0", + "IOI_WW4C1_0", + "IOI_ILOGIC0_DYNCLKSEL", + "RIOI_OLOGIC0_TQ", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_LOGIC_OUTS21_0", + "IOI_IMUX7_0", + "IOI_FAN1_0", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_NE2A1_0", + "IOI_IMUX43_0", + "IOI_CTRL1_0", + "IOI_LOGIC_OUTS17_0", + "IOI_SE2A3_0", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LH9_0", + "IOI_OLOGIC0_D2", + "IOI_OLOGIC0_CLKDIVB", + "RIOI_ILOGIC0_D", + "IOI_SW4A0_0", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_BLOCK_OUTS1_0", + "IOI_LOGIC_OUTS0_0", + "IOI_WW2A1_0", + "RIOI_ODELAY0_DATAOUT", + "IOI_WW4A3_0", + "RIOI_ODELAY0_ODATAIN", + "IOI_SE4C1_0", + "IOI_ER1BEG0_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_ILOGIC0_Q4", + "IOI_IMUX20_0", + "RIOI_ODELAY0_OFDLY0", + "IOI_OLOGIC0_D5", + "IOI_EL1BEG1_0", + "IOI_FAN2_0", + "RIOI_OLOGIC0_CLKDIVF", + "IOI_NW2A1_0", + "IOI_CTRL0_0", + "IOI_SE4BEG1_0", + "IOI_OLOGIC0_SR", + "RIOI_PD_INT_EN_1", + "IOI_LH2_0", + "IOI_WW2A2_0", + "IOI_ODELAY0_CE", + "IOI_EE2A3_0", + "IOI_ILOGIC0_Q8", + "IOI_IMUX24_0", + "IOI_OLOGIC0_T2", + "IOI_IDELAY0_LD", + "IOI_LOGIC_OUTS3_0", + "RIOI_ISOUT20", + "IOI_BYP0_0", + "RIOI_OSOUT20", + "IOI_WW4C2_0", + "IOI_WW2END1_0", + "IOI_EE2BEG2_0", + "IOI_NE2A3_0", + "RIOI_IDELAY0_IDATAIN", + "IOI_NE4BEG3_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_LH5_0", + "IOI_LH12_0", + "RIOI3_IDELAY0_IFDLY1", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_ILOGIC0_Q1", + "IOI_IDELAY0_CE", + "IOI_SING_LEAF_GCLK2", + "IOI_OLOGIC0_CLK", + "IOI_SW2A3_0", + "IOI_ODELAY0_C", + "IOI_IMUX35_0", + "IOI_SING_IOCLK0", + "IOI_LH1_0", + "RIOI_OLOGIC0_OQ", + "IOI_IMUX4_0", + "IOI_EE4BEG2_0", + "IOI_LOGIC_OUTS4_0", + "IOI_SING_TBYTEIN", + "IOI_LOGIC_OUTS22_0", + "IOI_IMUX18_0", + "IOI_NE4C1_0", + "IOI_WW4A1_0", + "IOI_FAN7_0", + "IOI_BYP4_0", + "RIOI_ISIN10", + "IOI_SING_RCLK_FORIO2", + "IOI_ER1BEG1_0", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OCLK_0", + "IOI_ODELAY0_REGRST", + "IOI_IMUX31_0", + "IOI_ER1BEG2_0", + "IOI_LOGIC_OUTS15_0", + "IOI_SE4C2_0", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_WW4END2_0", + "IOI_ODELAY0_CNTVALUEIN2" + ], + "tile_type": "RIOI3_SING", + "sites": [ + { + "site_pins": { + "T2": "IOI_OLOGIC0_T2", + "D5": "IOI_OLOGIC0_D5", + "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", + "D8": "IOI_OLOGIC0_D8", + "SR": "IOI_OLOGIC0_SR", + "SHIFTOUT1": "RIOI_OSOUT10", + "T4": "IOI_OLOGIC0_T4", + "SHIFTIN1": null, + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "OCE": "IOI_OLOGIC0_OCE", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "CLKB": "IOI_OLOGIC0_CLKB", + "OQ": "RIOI_OLOGIC0_OQ", + "D3": "IOI_OLOGIC0_D3", + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "SHIFTIN2": null, + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "D1": "IOI_OLOGIC0_D1", + "CLK": "IOI_OLOGIC0_CLK", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "T1": "IOI_OLOGIC0_T1", + "D4": "IOI_OLOGIC0_D4", + "TCE": "IOI_OLOGIC0_TCE", + "D2": "IOI_OLOGIC0_D2", + "SHIFTOUT2": "RIOI_OSOUT20", + "OFB": "RIOI_OLOGIC0_OFB", + "TFB": "RIOI_OLOGIC0_TFB", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "T3": "IOI_OLOGIC0_T3", + "D6": "IOI_OLOGIC0_D6", + "TQ": "RIOI_OLOGIC0_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "CLK": "IOI_ILOGIC0_CLK", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "Q3": "IOI_ILOGIC0_Q3", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "D": "RIOI_ILOGIC0_D", + "SR": "IOI_ILOGIC0_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC0_CE1", + "Q8": "IOI_ILOGIC0_Q8", + "SHIFTIN2": null, + "Q2": "IOI_ILOGIC0_Q2", + "CE2": "IOI_ILOGIC0_CE2", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "SHIFTOUT2": "RIOI_ISOUT20", + "O": "IOI_ILOGIC0_O", + "OFB": "RIOI_ILOGIC0_OFB", + "TFB": "RIOI_ILOGIC0_TFB", + "Q4": "IOI_ILOGIC0_Q4", + "CLKB": "IOI_ILOGIC0_CLKB", + "Q1": "IOI_ILOGIC0_Q1", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN1": null, + "Q6": "IOI_ILOGIC0_Q6", + "DDLY": "RIOI_ILOGIC0_DDLY", + "SHIFTOUT1": "RIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC0_Q7", + "OCLKB": "IOI_ILOGIC0_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "IFDLY0": "RIOI3_IDELAY0_IFDLY0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", + "LD": "IOI_IDELAY0_LD", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "IDATAIN": "RIOI_IDELAY0_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "IFDLY2": "RIOI3_IDELAY0_IFDLY2", + "C": "IOI_IDELAY0_C", + "IFDLY1": "RIOI3_IDELAY0_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "DATAOUT": "RIOI_IDELAY0_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_RIOI3_TBYTESRC.json b/artix7/tile_type_RIOI3_TBYTESRC.json index 2611aef..5f90ec0 100644 --- a/artix7/tile_type_RIOI3_TBYTESRC.json +++ b/artix7/tile_type_RIOI3_TBYTESRC.json @@ -1,3893 +1,3893 @@ { - "wires": [ - "IOI_LOGIC_OUTS17_1", - "IOI_WW2END3_1", - "IOI_SE4BEG2_0", - "RIOI3_IDELAY0_IFDLY1", - "RIOI_OLOGIC0_TFB_LOCAL", - "IOI_NW4A2_0", - "IOI_NW4END1_0", - "IOI_IMUX21_1", - "IOI_WR1END3_0", - "IOI_NE2A2_0", - "IOI_IMUX20_0", - "IOI_EE2BEG2_0", - "IOI_BYP3_1", - "IOI_OLOGIC1_D8", - "IOI_CLK1_1", - "IOI_ODELAY0_C", - "IOI_IMUX3_1", - "IOI_WR1END3_1", - "IOI_NW4END1_1", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_WW4END0_1", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_EE2A3_1", - "IOI_OLOGIC1_D6", - "IOI_IMUX9_1", - "IOI_IMUX35_0", - "IOI_BLOCK_OUTS3_1", - "RIOI3_IDELAY1_IFDLY1", - "IOI_OLOGIC0_D2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_OLOGIC0_CLKDIV", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_RCLK_DIV_CE2", - "IOI_SW2A2_1", - "IOI_WW4END1_1", - "IOI_ODELAY0_CE", - "IOI_NE2A1_0", - "RIOI_OLOGIC0_TQ", - "IOI_IMUX0_0", - "RIOI_ISOUT10", - "IOI_ER1BEG0_0", - "IOI_IMUX10_1", - "IOI_ILOGIC0_BITSLIP", - "IOI_NE4C3_0", - "IOI_IMUX10_0", - "IOI_EE4B3_0", - "IOI_IMUX45_1", - "IOI_LH4_0", - "IOI_NW4END2_0", - "IOI_OLOGIC0_SR", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_LH1_0", - "IOI_EE4A1_1", - "IOI_LOGIC_OUTS2_1", - "IOI_BLOCK_OUTS1_0", - "IOI_WW4B1_0", - "IOI_LH2_0", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_IDELAYCTRL_OUTN1", - "IOI_FAN4_1", - "IOI_IMUX12_1", - "RIOI_T1", - "IOI_OLOGIC1_TBYTEIN", - "IOI_IMUX1_1", - "IOI_IMUX8_0", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_CTRL0_0", - "IOI_IDELAY1_INC", - "IOI_IMUX24_1", - "IOI_SW2A2_0", - "IOI_NW4A2_1", - "IOI_LOGIC_OUTS12_1", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_INC", - "IOI_OLOGIC0_T4", - "IOI_ER1BEG1_0", - "RIOI_ODELAY1_OFDLY1", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_IMUX14_1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_ILOGIC1_Q1", - "IOI_EL1BEG2_0", - "IOI_ILOGIC1_SR", - "RIOI_KEEPER_INT_EN_0", - "RIOI_OLOGIC1_TFB", - "IOI_NE4BEG2_0", - "IOI_EL1BEG3_1", - "IOI_SW2A0_0", - "IOI_IMUX36_1", - "IOI_IMUX24_0", - "IOI_NW4END3_1", - "IOI_OLOGIC1_D2", - "IOI_EE4C1_1", - "IOI_LOGIC_OUTS21_0", - "IOI_IMUX4_1", - "IOI_WW4C3_0", - "IOI_OLOGIC0_D7", - "IOI_EE2A1_1", - "IOI_IMUX37_0", - "IOI_IDELAY1_CE", - "IOI_ODELAY1_CNTVALUEIN1", - "RIOI3_IDELAY0_IFDLY2", - "IOI_WW2A2_0", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_BYP4_1", - "IOI_IMUX42_1", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_IMUX30_0", - "IOI_IMUX35_1", - "IOI_LOGIC_OUTS19_1", - "IOI_LH8_1", - "IOI_IMUX33_0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_EE4BEG3_1", - "IOI_NE2A2_1", - "IOI_ILOGIC0_Q2", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_BYP7_0", - "IOI_TBYTEIN", - "IOI_IMUX42_0", - "IOI_SW4A2_0", - "IOI_WR1END0_1", - "IOI_WW2A2_1", - "IOI_MONITOR_P", - "RIOI_OSIN20", - "IOI_NE4C1_0", - "IOI_IMUX29_0", - "IOI_OCLKM_1", - "RIOI_ODELAY0_ODATAIN", - "IOI_WW4B2_1", - "IOI_OLOGIC0_REV", - "IOI_WW4END3_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LH7_1", - "IOI_NW2A3_1", - "IOI_LH12_1", - "IOI_EE4BEG2_0", - "IOI_LH7_0", - "RIOI_ILOGIC0_D", - "IOI_ER1BEG3_0", - "IOI_IMUX0_1", - "IOI_LOGIC_OUTS7_1", - "IOI_ILOGIC0_Q3", - "IOI_IDELAY0_LDPIPEEN", - "IOI_WW2END2_0", - "RIOI_PD_INT_EN_0", - "IOI_LH11_1", - "IOI_IDELAY1_CINVCTRL", - "IOI_NW4A3_1", - "RIOI_OLOGIC0_OQ", - "IOI_IMUX23_0", - "IOI_IMUX37_1", - "IOI_LOGIC_OUTS3_0", - "IOI_WW4A0_0", - "IOI_IOCLK0", - "RIOI_I2GCLK_BOT1", - "IOI_WW2END3_0", - "RIOI_ISOUT11", - "IOI_NE4BEG3_0", - "IOI_SE2A2_1", - "IOI_LEAF_GCLK0", - "IOI_IDELAY0_CNTVALUEIN1", - "RIOI_ODELAY1_OFDLY2", - "IOI_IMUX18_1", - "IOI_IDELAY0_CE", - "RIOI_ISIN21", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_NW4END3_0", - "IOI_WW4C0_1", - "IOI_SE4C3_0", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IMUX39_1", - "IOI_NW4A1_0", - "IOI_NE4BEG2_1", - "IOI_SE4BEG0_0", - "IOI_IMUX22_1", - "IOI_IMUX14_0", - "IOI_CLK1_0", - "IOI_SE4BEG3_0", - "IOI_OLOGIC0_D6", - "IOI_WW2A1_1", - "IOI_EE2A3_0", - "IOI_IMUX28_0", - "IOI_OCLK_0", - "IOI_IMUX18_0", - "IOI_NW2A1_1", - "RIOI_ILOGIC1_D", - "RIOI_OLOGIC0_TFB", - "IOI_IDELAY1_C", - "IOI_WW4A2_0", - "IOI_NE4C0_0", - "IOI_NW2A1_0", - "IOI_IMUX2_1", - "IOI_LOGIC_OUTS9_0", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_IMUX16_0", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_BLOCK_OUTS2_1", - "IOI_WL1END3_0", - "IOI_LOGIC_OUTS7_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_IDELAYCTRL_RDY", - "IOI_RCLK_DIV_CLR2", - "IOI_IMUX11_0", - "IOI_LOGIC_OUTS16_1", - "IOI_RCLK_DIV_CE3", - "IOI_WR1END2_0", - "IOI_LOGIC_OUTS18_1", - "IOI_SW4A0_0", - "IOI_NE4BEG1_1", - "IOI_WR1END1_0", - "IOI_OLOGIC1_CLK", - "IOI_EE4B0_0", - "IOI_WW4A3_1", - "RIOI_PU_INT_EN_0", - "IOI_RCLK_DIV_CLR1", - "IOI_LOGIC_OUTS15_0", - "RIOI_I2GCLK_TOP1", - "RIOI_I0", - "IOI_WW4B0_0", - "IOI_OLOGIC1_D3", - "IOI_ODELAY1_LD", - "RIOI_ILOGIC1_OFB", - "IOI_NW4END2_1", - "IOI_LOGIC_OUTS10_1", - "IOI_NE2A3_1", - "IOI_NW2A0_0", - "IOI_WW4END3_0", - "IOI_IOCLK3", - "IOI_SE2A3_0", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_WW2A3_0", - "IOI_ILOGIC0_CE1", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_BYP1_1", - "RIOI_OSOUT20", - "IOI_SE4C1_1", - "IOI_SW4A3_1", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IMUX38_1", - "IOI_ER1BEG2_0", - "IOI_WW4C0_0", - "RIOI_DCI_T_TERM0", - "IOI_IMUX25_0", - "IOI_NE4BEG0_0", - "IOI_IMUX7_1", - "IOI_FAN3_1", - "IOI_OLOGIC1_SR", - "IOI_SW4END1_0", - "IOI_ILOGIC1_CE2", - "RIOI_DIFF_TERM_INT_EN", - "IOI_WW4END0_0", - "IOI_FAN7_0", - "IOI_LOGIC_OUTS1_0", - "IOI_EE2BEG0_0", - "IOI_SE4C0_1", - "IOI_OLOGIC1_T3", - "IOI_IMUX43_1", - "IOI_EE2BEG3_1", - "IOI_NE4C3_1", - "IOI_IMUX34_1", - "IOI_IMUX46_0", - "IOI_IMUX27_0", - "RIOI_IBUF_DISABLE0", - "IOI_DCI_TSTCLK", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_D8", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_EE4C2_0", - "IOI_IMUX11_1", - "IOI_CTRL1_0", - "IOI_DCI_TSTHLP", - "IOI_EE4A3_0", - "IOI_OLOGIC0_CLKB", - "IOI_WW4C3_1", - "IOI_IMUX40_0", - "RIOI_O0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_IMUX47_0", - "RIOI_OSIN10", - "IOI_OLOGIC1_CLKDIV", - "IOI_LOGIC_OUTS5_1", - "RIOI_OLOGIC1_TFB_LOCAL", - "IOI_BYP7_1", - "IOI_LOGIC_OUTS12_0", - "RIOI_OSOUT21", - "IOI_SE4BEG0_1", - "IOI_OLOGIC0_IOCLKGLITCH", - "RIOI_IBUF1", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_LOGIC_OUTS5_0", - "IOI_FAN4_0", - "IOI_WW4B0_1", - "IOI_WL1END0_1", - "IOI_IMUX2_0", - "IOI_WW2END0_0", - "IOI_LH2_1", - "IOI_WW4A1_1", - "IOI_WW4C1_1", - "RIOI_OSIN11", - "IOI_ER1BEG2_1", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_OLOGIC0_T1", - "IOI_IMUX3_0", - "IOI_EE2BEG1_0", - "IOI_IMUX29_1", - "IOI_WW2END0_1", - "IOI_OCLK_1", - "IOI_WW2A0_0", - "IOI_ER1BEG1_1", - "RIOI_ILOGIC1_DDLY", - "IOI_RCLK_FORIO2", - "IOI_PHASER_TO_IO_ICLK", - "IOI_NE4C2_0", - "IOI_BYP2_1", - "IOI_WR1END1_1", - "IOI_FAN3_0", - "IOI_ILOGIC1_BITSLIP", - "IOI_ODELAY0_LDPIPEEN", - "IOI_IMUX44_1", - "IOI_NE2A1_1", - "IOI_LOGIC_OUTS1_1", - "IOI_EE4B0_1", - "IOI_OLOGIC1_CLKB", - "IOI_RCLK_DIV_CLR0", - "IOI_ILOGIC1_CLKDIV", - "IOI_DCI_TSTHLN", - "IOI_OLOGIC1_D5", - "IOI_SW2A3_0", - "IOI_IDELAY1_REGRST", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_LOGIC_OUTS19_0", - "IOI_IMUX32_1", - "IOI_SE2A1_1", - "IOI_LOGIC_OUTS21_1", - "IOI_EE2A2_0", - "IOI_ODELAY1_REGRST", - "RIOI_OLOGIC1_OFB", - "IOI_LH9_0", - "IOI_FAN5_1", - "IOI_LH6_0", - "RIOI_ODELAY0_DATAOUT", - "IOI_ODELAY1_C", - "IOI_IMUX19_0", - "IOI_OLOGIC1_D4", - "IOI_LOGIC_OUTS10_0", - "IOI_ILOGIC0_OCLK", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_INT_DCI_EN", - "IOI_EL1BEG0_1", - "IOI_SW2A1_0", - "RIOI_OLOGIC0_CLKDIVF", - "IOI_OLOGIC1_D1", - "IOI_DCI_TSTRST0", - "IOI_OLOGIC0_T2", - "IOI_BLOCK_OUTS0_0", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_EE4BEG2_1", - "IOI_SE4BEG3_1", - "IOI_OLOGIC1_T2", - "IOI_WW4A0_1", - "IOI_IMUX26_0", - "IOI_IMUX45_0", - "IOI_MONITOR_N", - "IOI_IMUX8_1", - "IOI_RCLK_DIV_CLR3", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY1_CE", - "IOI_LH6_1", - "RIOI_OLOGIC1_CLKDIVF", - "RIOI_OLOGIC1_OQ", - "IOI_IOCLK1", - "IOI_FAN7_1", - "IOI_RCLK_DIV_CLR0_1", - "IOI_LOGIC_OUTS2_0", - "IOI_WW4A1_0", - "IOI_IMUX7_0", - "IOI_ODELAY1_INC", - "IOI_ILOGIC0_CLK", - "IOI_IMUX20_1", - "IOI_WW2END1_1", - "RIOI_IDELAY1_DATAOUT", - "IOI_LOGIC_OUTS11_0", - "IOI_SE4C0_0", - "IOI_LOGIC_OUTS17_0", - "IOI_ER1BEG3_1", - "IOI_ILOGIC0_CLKDIV", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_REV", - "IOI_FAN1_1", - "IOI_LH10_0", - "RIOI_ISOUT20", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC0_CE2", - "IOI_FAN6_1", - "IOI_IDELAY1_CNTVALUEOUT0", - "RIOI_ODELAY0_OFDLY0", - "IOI_IMUX5_0", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_SW4END0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_ILOGIC1_Q5", - "IOI_NE4BEG0_1", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_WW4B3_0", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_EE4BEG0_1", - "IOI_EE2BEG2_1", - "IOI_OLOGIC1_T1", - "IOI_IMUX6_1", - "IOI_EL1BEG2_1", - "IOI_SE4C1_0", - "IOI_NW4END0_1", - "RIOI_ODELAY1_OFDLY0", - "IOI_IMUX1_0", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_REV", - "IOI_SE4C2_1", - "IOI_SE4BEG2_1", - "IOI_EE4A0_1", - "IOI_IMUX36_0", - "IOI_EE2BEG0_1", - "RIOI_OSIN21", - "RIOI_ILOGIC0_DDLY", - "IOI_NW4A0_1", - "IOI_WW4END2_1", - "IOI_IMUX46_1", - "IOI_EE4A3_1", - "IOI_LOGIC_OUTS20_0", - "IOI_WL1END1_1", - "RIOI_OLOGIC1_TQ", - "IOI_SW4END1_1", - "IOI_IMUX13_1", - "IOI_ODELAY0_LD", - "IOI_ILOGIC1_Q8", - "IOI_IMUX23_1", - "IOI_IMUX_RC3", - "IOI_IMUX31_1", - "IOI_WW4A3_0", - "IOI_OLOGIC0_OCE", - "IOI_LOGIC_OUTS3_1", - "RIOI_O1", - "IOI_EE2A2_1", - "IOI_LOGIC_OUTS8_0", - "IOI_ILOGIC0_CLKB", - "IOI_IMUX27_1", - "IOI_NE2A0_1", - "IOI_RCLK_DIV_CE1", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_NE2A0_0", - "IOI_IDELAY0_REGRST", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_SE4BEG1_1", - "IOI_IMUX_RC2", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_ILOGIC0_O", - "IOI_EE4A1_0", - "IOI_IDELAYCTRL_RST", - "IOI_SW4A1_0", - "RIOI3_IDELAY1_IFDLY2", - "IOI_EE4A2_1", - "IOI_LOGIC_OUTS9_1", - "RIOI_ISIN20", - "IOI_WW4A2_1", - "IOI_FAN2_1", - "IOI_FAN5_0", - "RIOI_ODELAY0_OFDLY2", - "IOI_IMUX16_1", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_IOCLK2", - "IOI_OLOGIC1_D7", - "RIOI_PU_INT_EN_1", - "IOI_IMUX6_0", - "RIOI_IBUF0", - "IOI_LOGIC_OUTS4_0", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC1_Q4", - "IOI_NW4END0_0", - "RIOI_OLOGIC0_OFB", - "IOI_FAN0_1", - "IOI_BLOCK_OUTS3_0", - "IOI_IMUX38_0", - "IOI_IDELAY0_CINVCTRL", - "IOI_OLOGIC1_OCE", - "IOI_EE4A2_0", - "IOI_BLOCK_OUTS0_1", - "IOI_IMUX4_0", - "IOI_OLOGIC1_CLKDIVB", - "IOI_SW4END2_0", - "IOI_BYP0_1", - "IOI_IMUX_RC0", - "IOI_IMUX31_0", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IMUX15_0", - "IOI_EE4C3_0", - "IOI_LOGIC_OUTS11_1", - "IOI_NE4BEG1_0", - "IOI_SW4END2_1", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS4_1", - "IOI_WR1END0_0", - "IOI_IDELAY0_C", - "IOI_SE2A2_0", - "IOI_LOGIC_OUTS13_0", - "IOI_ILOGIC1_OCLK", - "IOI_BYP4_0", - "IOI_WW2A1_0", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_IDELAY0_DATAIN", - "IOI_EE4B2_1", - "IOI_IMUX28_1", - "IOI_LEAF_GCLK5", - "IOI_SW4A3_0", - "IOI_BLOCK_OUTS1_1", - "IOI_WW4C1_0", - "IOI_IMUX9_0", - "IOI_BYP5_0", - "IOI_LOGIC_OUTS18_0", - "IOI_NW4A0_0", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_LH10_1", - "IOI_IMUX12_0", - "RIOI_PD_INT_EN_1", - "RIOI_ISIN11", - "IOI_LOGIC_OUTS23_0", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_DCI_DCIDONE", - "IOI_SE2A0_0", - "IOI_IMUX21_0", - "IOI_EE4B1_1", - "IOI_RCLK_DIV_CE3_1", - "IOI_EE4BEG0_0", - "RIOI_I1", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ILOGIC1_CLK", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_LOGIC_OUTS14_1", - "IOI_BYP3_0", - "IOI_EE2A0_1", - "IOI_LEAF_GCLK4", - "IOI_SW4A2_1", - "IOI_OLOGIC1_T4", - "IOI_LOGIC_OUTS0_0", - "IOI_WW2END1_0", - "IOI_BYP5_1", - "IOI_ER1BEG0_1", - "IOI_LOGIC_OUTS16_0", - "IOI_IMUX5_1", - "IOI_NW4A3_0", - "IOI_EE4BEG1_1", - "RIOI3_IDELAY0_IFDLY0", - "IOI_SW2A1_1", - "RIOI_ILOGIC0_TFB", - "IOI_IDELAY0_LD", - "IOI_EE2A0_0", - "IOI_ODELAY1_CNTVALUEOUT0", - "RIOI_ILOGIC0_OFB", - "IOI_CLK0_1", - "IOI_RCLK_FORIO3", - "IOI_IMUX44_0", - "IOI_PHASER_TO_IO_OCLK_0", - "RIOI_I2GCLK_TOP0", - "IOI_ILOGIC1_O", - "IOI_SE2A3_1", - "IOI_ILOGIC1_REV", - "IOI_ODELAY0_CNTVALUEIN0", - "RIOI_T0", - "IOI_EE2A1_0", - "IOI_IMUX17_1", - "IOI_FAN1_0", - "IOI_EE4A0_0", - "IOI_LOGIC_OUTS22_0", - "RIOI_ISOUT21", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_RCLK_DIV_CE0", - "RIOI_ODELAY1_ODATAIN", - "IOI_WW4C2_0", - "IOI_NW2A3_0", - "IOI_IMUX34_0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_NE4C2_1", - "IOI_IMUX22_0", - "IOI_OLOGIC0_T3", - "IOI_ODELAY1_CINVCTRL", - "IOI_IMUX17_0", - "RIOI_ODELAY0_OFDLY1", - "IOI_WW4B2_0", - "IOI_FAN6_0", - "IOI_IDELAY1_LDPIPEEN", - "IOI_WL1END0_0", - "IOI_OCLKM_0", - "IOI_IMUX15_1", - "IOI_CLK0_0", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IMUX25_1", - "RIOI_IDELAY1_IDATAIN", - "IOI_EL1BEG0_0", - "IOI_OLOGIC0_CLK", - "IOI_IMUX39_0", - "IOI_WL1END1_0", - "IOI_WL1END2_0", - "IOI_IMUX41_0", - "IOI_CTRL0_1", - "IOI_EE4C0_0", - "IOI_ILOGIC1_Q6", - "IOI_NW2A0_1", - "IOI_EE2BEG1_1", - "RIOI_ODELAY1_DATAOUT", - "IOI_ILOGIC1_Q2", - "IOI_CTRL1_1", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_OLOGIC0_D4", - "IOI_SE4BEG1_0", - "IOI_EE2BEG3_0", - "IOI_LOGIC_OUTS15_1", - "IOI_SW4A1_1", - "IOI_EL1BEG1_0", - "IOI_DCI_TSTRST", - "IOI_SW2A3_1", - "IOI_NE4C0_1", - "IOI_ILOGIC1_CLKDIVP", - "IOI_IMUX30_1", - "IOI_ILOGIC0_Q5", - "IOI_IDELAYCTRL_OUTN65", - "IOI_WR1END2_1", - "IOI_WW4B1_1", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_EE4BEG3_0", - "IOI_SE2A0_1", - "IOI_FAN0_0", - "RIOI_DCI_T_TERM1", - "RIOI_ILOGIC1_TFB", - "IOI_EE4BEG1_0", - "IOI_IMUX47_1", - "IOI_LH1_1", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC0_OCLKB", - "IOI_RCLK_DIV_CE2_1", - "IOI_BYP2_0", - "IOI_EE4C1_0", - "IOI_WW2END2_1", - "IOI_IMUX43_0", - "IOI_BYP6_1", - "IOI_RCLK_FORIO1", - "IOI_ILOGIC1_OCLKB", - "IOI_LEAF_GCLK1", - "IOI_NW2A2_0", - "RIOI_KEEPER_INT_EN_1", - "IOI_IMUX33_1", - "IOI_LH11_0", - "IOI_ILOGIC0_Q6", - "IOI_SW4END3_1", - "IOI_ODELAY1_CLKIN", - "IOI_NW2A2_1", - "IOI_LH9_1", - "RIOI_OSOUT11", - "IOI_PHASER_TO_IO_OCLK", - "RIOI3_IDELAY1_IFDLY0", - "IOI_EE4B3_1", - "IOI_WW4B3_1", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "RIOI_IDELAY0_IDATAIN", - "IOI_ILOGIC1_Q3", - "IOI_FAN2_0", - "IOI_WW4C2_1", - "IOI_WL1END2_1", - "IOI_RCLK_FORIO0", - "IOI_SW4A0_1", - "IOI_NW4A1_1", - "RIOI_IBUF_DISABLE1", - "IOI_IMUX41_1", - "IOI_LOGIC_OUTS13_1", - "IOI_BLOCK_OUTS2_0", - "IOI_WW4END1_0", - "IOI_IMUX40_1", - "IOI_IMUX19_1", - "IOI_EE4B1_0", - "IOI_WL1END3_1", - "IOI_LEAF_GCLK2", - "IOI_ODELAY0_CLKIN", - "IOI_EE4B2_0", - "IOI_SE2A1_0", - "IOI_BYP6_0", - "IOI_IMUX32_0", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_DATAIN", - "IOI_EE4C2_1", - "IOI_LH5_1", - "IOI_ILOGIC0_Q7", - "IOI_IMUX_RC1", - "IOI_EL1BEG3_0", - "IOI_WW2A3_1", - "IOI_NE4C1_1", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_SW4END3_0", - "IOI_WW2A0_1", - "IOI_NE4BEG3_1", - "IOI_SE4C2_0", - "RIOI_OSOUT10", - "IOI_ODELAY0_INC", - "IOI_LOGIC_OUTS6_1", - "IOI_BYP1_0", - "IOI_NE2A3_0", - "IOI_ILOGIC1_Q7", - "IOI_ODELAY0_REGRST", - "IOI_ILOGIC0_CLKDIVP", - "IOI_EE4C3_1", - "IOI_SE4C3_1", - "IOI_ILOGIC1_CLKB", - "IOI_LOGIC_OUTS23_1", - "IOI_OLOGIC0_D1", - "IOI_EE4C0_1", - "IOI_LOGIC_OUTS22_1", - "IOI_OLOGIC1_TCE", - "IOI_LH8_0", - "RIOI_IDELAY0_DATAOUT", - "IOI_SW2A0_1", - "IOI_SW4END0_1", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_LOGIC_OUTS14_0", - "IOI_ODELAY1_LDPIPEEN", - "IOI_LH12_0", - "IOI_IMUX13_0", - "IOI_LEAF_GCLK3", - "IOI_BYP0_0", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ILOGIC0_Q4", - "IOI_EL1BEG1_1", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_WW4END2_0", - "IOI_IMUX26_1", - "RIOI_ISIN10", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_TBYTEIN", - "IOI_LOGIC_OUTS20_1" - ], - "sites": [ - { - "prefix": "OLOGIC", - "y_coord": 0, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC1_D1", - "D3": "IOI_OLOGIC1_D3", - "SR": "IOI_OLOGIC1_SR", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "TFB": "RIOI_OLOGIC1_TFB", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLK": "IOI_OLOGIC1_CLK", - "T4": "IOI_OLOGIC1_T4", - "OQ": "RIOI_OLOGIC1_OQ", - "D8": "IOI_OLOGIC1_D8", - "T1": "IOI_OLOGIC1_T1", - "D5": "IOI_OLOGIC1_D5", - "SHIFTOUT1": "RIOI_OSOUT11", - "T2": "IOI_OLOGIC1_T2", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "D4": "IOI_OLOGIC1_D4", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D2": "IOI_OLOGIC1_D2", - "TQ": "RIOI_OLOGIC1_TQ", - "T3": "IOI_OLOGIC1_T3", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "OCE": "IOI_OLOGIC1_OCE", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "SHIFTIN1": null, - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "TCE": "IOI_OLOGIC1_TCE", - "OFB": "RIOI_OLOGIC1_OFB", - "SHIFTIN2": null, - "SHIFTOUT2": "RIOI_OSOUT21", - "REV": null, - "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "ILOGIC", - "y_coord": 0, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q1": "IOI_ILOGIC1_Q1", - "SR": "IOI_ILOGIC1_SR", - "D": "RIOI_ILOGIC1_D", - "DDLY": "RIOI_ILOGIC1_DDLY", - "SHIFTIN2": "RIOI_ISIN21", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "Q3": "IOI_ILOGIC1_Q3", - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "Q8": "IOI_ILOGIC1_Q8", - "TFB": "RIOI_ILOGIC1_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC1_CE1", - "Q2": "IOI_ILOGIC1_Q2", - "Q6": "IOI_ILOGIC1_Q6", - "CLKB": "IOI_ILOGIC1_CLKB", - "Q7": "IOI_ILOGIC1_Q7", - "O": "IOI_ILOGIC1_O", - "CLK": "IOI_ILOGIC1_CLK", - "CE2": "IOI_ILOGIC1_CE2", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "SHIFTIN1": "RIOI_ISIN11", - "OCLK": "IOI_ILOGIC1_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "OFB": "RIOI_ILOGIC1_OFB", - "SHIFTOUT1": "RIOI_ISOUT11", - "SHIFTOUT2": "RIOI_ISOUT21", - "REV": null, - "CLKDIV": "IOI_ILOGIC1_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "OLOGIC", - "y_coord": 1, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC0_D1", - "D3": "IOI_OLOGIC0_D3", - "SR": "IOI_OLOGIC0_SR", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "TFB": "RIOI_OLOGIC0_TFB", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLK": "IOI_OLOGIC0_CLK", - "T4": "IOI_OLOGIC0_T4", - "OQ": "RIOI_OLOGIC0_OQ", - "D8": "IOI_OLOGIC0_D8", - "T1": "IOI_OLOGIC0_T1", - "D5": "IOI_OLOGIC0_D5", - "SHIFTOUT1": "RIOI_OSOUT10", - "T2": "IOI_OLOGIC0_T2", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "D4": "IOI_OLOGIC0_D4", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D2": "IOI_OLOGIC0_D2", - "TQ": "RIOI_OLOGIC0_TQ", - "T3": "IOI_OLOGIC0_T3", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "OCE": "IOI_OLOGIC0_OCE", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "SHIFTIN1": "RIOI_OSIN10", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "TCE": "IOI_OLOGIC0_TCE", - "OFB": "RIOI_OLOGIC0_OFB", - "SHIFTIN2": "RIOI_OSIN20", - "SHIFTOUT2": "RIOI_OSOUT20", - "REV": null, - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "ILOGIC", - "y_coord": 1, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q1": "IOI_ILOGIC0_Q1", - "SR": "IOI_ILOGIC0_SR", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "SHIFTIN2": null, - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "Q3": "IOI_ILOGIC0_Q3", - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "Q8": "IOI_ILOGIC0_Q8", - "TFB": "RIOI_ILOGIC0_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC0_CE1", - "Q2": "IOI_ILOGIC0_Q2", - "Q6": "IOI_ILOGIC0_Q6", - "CLKB": "IOI_ILOGIC0_CLKB", - "Q7": "IOI_ILOGIC0_Q7", - "O": "IOI_ILOGIC0_O", - "CLK": "IOI_ILOGIC0_CLK", - "CE2": "IOI_ILOGIC0_CE2", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "SHIFTIN1": null, - "OCLK": "IOI_ILOGIC0_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "OFB": "RIOI_ILOGIC0_OFB", - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "REV": null, - "CLKDIV": "IOI_ILOGIC0_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "IDELAY", - "y_coord": 0, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CE": "IOI_IDELAY1_CE", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "IFDLY2": "RIOI3_IDELAY1_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "LD": "IOI_IDELAY1_LD", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "IFDLY0": "RIOI3_IDELAY1_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "INC": "IOI_IDELAY1_INC", - "DATAOUT": "RIOI_IDELAY1_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY1_DATAIN", - "C": "IOI_IDELAY1_C", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "IDATAIN": "RIOI_IDELAY1_IDATAIN", - "REGRST": "IOI_IDELAY1_REGRST", - "IFDLY1": "RIOI3_IDELAY1_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IDELAY", - "y_coord": 1, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CE": "IOI_IDELAY0_CE", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "IFDLY2": "RIOI3_IDELAY0_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "LD": "IOI_IDELAY0_LD", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "IFDLY0": "RIOI3_IDELAY0_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "INC": "IOI_IDELAY0_INC", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY0_DATAIN", - "C": "IOI_IDELAY0_C", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "REGRST": "IOI_IDELAY0_REGRST", - "IFDLY1": "RIOI3_IDELAY0_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "RIOI3_TBYTESRC.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": { + "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", - "dst_wire": "RIOI3_IDELAY1_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q7", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE2_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { - "can_invert": "0", - "dst_wire": "RIOI_IBUF_DISABLE0", - "is_directional": "1", - "src_wire": "IOI_IMUX9_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OSOUT11->RIOI_OSIN10": { - "can_invert": "0", - "dst_wire": "RIOI_OSIN10", - "is_directional": "1", - "src_wire": "RIOI_OSOUT11", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_1", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR3", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX47_0->IOI_OLOGIC1_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q8", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX43_0->IOI_OLOGIC1_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q8", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC1_D", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OSOUT21->RIOI_OSIN20": { - "can_invert": "0", - "dst_wire": "RIOI_OSIN20", - "is_directional": "1", - "src_wire": "RIOI_OSOUT21", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC0_DDLY", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TFB", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX44_1->IOI_OLOGIC0_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY0_DATAOUT", - "is_directional": "1", - "src_wire": "RIOI_IDELAY0_IDATAIN", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC3", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR0_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEOUT->>IOI_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_TBYTEOUT", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC2", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX46_1->IOI_OLOGIC0_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR1_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX42_0->IOI_OLOGIC1_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY1_DATAOUT", - "is_directional": "1", - "src_wire": "RIOI_IDELAY1_IDATAIN", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q6", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_1", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_O0": { - "can_invert": "0", - "dst_wire": "RIOI_O0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OQ", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY1_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX40_0->IOI_OLOGIC1_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OQ", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX21_0->IOI_OLOGIC1_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OFB", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_DDLY", - "is_directional": "1", - "src_wire": "RIOI_IDELAY1_DATAOUT", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" }, "RIOI3_TBYTESRC.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", - "is_directional": "1", "src_wire": "IOI_IMUX37_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX40_1->IOI_OLOGIC0_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX45_1->IOI_OLOGIC0_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { - "can_invert": "0", - "dst_wire": "RIOI_I2GCLK_TOP0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { - "can_invert": "0", - "dst_wire": "RIOI_DCI_T_TERM0", - "is_directional": "1", - "src_wire": "IOI_IMUX6_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_I1->RIOI_ILOGIC1_D": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_D", - "is_directional": "1", - "src_wire": "RIOI_I1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC0", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX45_0->IOI_OLOGIC1_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY1_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC0_D", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_OQ", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_I0->RIOI_IDELAY0_IDATAIN": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY0_IDATAIN", - "is_directional": "1", - "src_wire": "RIOI_I0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_DDLY", - "is_directional": "1", - "src_wire": "RIOI_IDELAY0_DATAOUT", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_IBUF1->RIOI_I1": { - "can_invert": "0", - "dst_wire": "RIOI_I1", - "is_directional": "1", - "src_wire": "RIOI_IBUF1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX46_0->IOI_OLOGIC1_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE3_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_ISOUT20->RIOI_ISIN21": { - "can_invert": "0", - "dst_wire": "RIOI_ISIN21", - "is_directional": "1", - "src_wire": "RIOI_ISOUT20", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX44_0->IOI_OLOGIC1_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { - "can_invert": "0", - "dst_wire": "RIOI_IBUF_DISABLE1", - "is_directional": "1", - "src_wire": "IOI_IMUX9_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TQ", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_ISOUT10->RIOI_ISIN11": { - "can_invert": "0", - "dst_wire": "RIOI_ISIN11", - "is_directional": "1", - "src_wire": "RIOI_ISOUT10", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX43_1->IOI_OLOGIC0_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_OFB", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q7", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_I1->RIOI_IDELAY1_IDATAIN": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY1_IDATAIN", - "is_directional": "1", - "src_wire": "RIOI_I1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC1_DDLY", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "RIOI3_TBYTESRC.RIOI_I0->RIOI_ILOGIC0_D": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_D", - "is_directional": "1", - "src_wire": "RIOI_I0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_IBUF0->RIOI_I0": { - "can_invert": "0", - "dst_wire": "RIOI_I0", - "is_directional": "1", - "src_wire": "RIOI_IBUF0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { - "can_invert": "0", - "dst_wire": "RIOI_DCI_T_TERM1", - "is_directional": "1", - "src_wire": "IOI_IMUX6_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" }, - "RIOI3_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE2", + "src_wire": "IOI_LEAF_GCLK2", "is_directional": "1", - "src_wire": "IOI_IMUX14_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" }, - "RIOI3_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_0", + "src_wire": "IOI_RCLK_FORIO2", "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q6", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" }, - "RIOI3_TBYTESRC.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D4", + "src_wire": "IOI_LEAF_GCLK2", "is_directional": "1", - "src_wire": "IOI_IMUX42_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.RIOI_I1->RIOI_IDELAY1_IDATAIN": { + "can_invert": "0", + "src_wire": "RIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IDATAIN" + }, + "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK" + }, + "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "RIOI3_TBYTESRC.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0" + }, + "RIOI3_TBYTESRC.RIOI_IBUF1->RIOI_I1": { + "can_invert": "0", + "src_wire": "RIOI_IBUF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_I1" + }, + "RIOI3_TBYTESRC.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC0_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1" + }, + "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OQ" + }, + "RIOI3_TBYTESRC.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY1" + }, + "RIOI3_TBYTESRC.RIOI_ISOUT10->RIOI_ISIN11": { + "can_invert": "0", + "src_wire": "RIOI_ISOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN11" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TBYTEIN", "is_directional": "1", - "src_wire": "IOI_TBYTEIN", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" }, - "RIOI3_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "RIOI3_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", + "src_wire": "IOI_CTRL1_0", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR" }, - "RIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR2", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0" }, - "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "RIOI3_TBYTESRC.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_1", + "src_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_OFB" }, "RIOI3_TBYTESRC.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", - "is_directional": "1", "src_wire": "IOI_IMUX36_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", - "src_wire": "IOI_IMUX4_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1" }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "RIOI3_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", + "src_wire": "IOI_BYP4_0", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1" }, - "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_0", + "src_wire": "IOI_RCLK_FORIO1", "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", + "src_wire": "IOI_LEAF_GCLK3", "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" }, - "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", + "src_wire": "IOI_LEAF_GCLK5", "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_T1": { - "can_invert": "0", - "dst_wire": "RIOI_T1", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TQ", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_O1": { - "can_invert": "0", - "dst_wire": "RIOI_O1", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_OQ", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_T0": { - "can_invert": "0", - "dst_wire": "RIOI_T0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TQ", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_O", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TQ", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" }, - "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_0": { + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", - "dst_wire": "IOI_OCLK_0", + "src_wire": "IOI_LEAF_GCLK0", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST" + }, + "RIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1" + }, + "RIOI3_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0" + }, + "RIOI3_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C" + }, + "RIOI3_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL" + }, + "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" }, - "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "RIOI3_TBYTESRC.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", + "src_wire": "IOI_IMUX40_1", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2" + }, + "RIOI3_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE" + }, + "RIOI3_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.RIOI_ISOUT20->RIOI_ISIN21": { + "can_invert": "0", + "src_wire": "RIOI_ISOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN21" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB" + }, + "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_I2GCLK_TOP0" + }, + "RIOI3_TBYTESRC.RIOI_I1->RIOI_ILOGIC1_D": { + "can_invert": "0", + "src_wire": "RIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_D" + }, + "RIOI3_TBYTESRC.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "RIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_T0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_T0" + }, + "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL" + }, + "RIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" }, - "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "RIOI3_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", + "src_wire": "IOI_IMUX38_1", "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD" + }, + "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" }, "RIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE0", - "is_directional": "1", "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0" + }, + "RIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.RIOI_I0->RIOI_ILOGIC0_D": { + "can_invert": "0", + "src_wire": "RIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_D" + }, + "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY0_DATAOUT" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN" + }, + "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY1_IFDLY0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "RIOI3_TBYTESRC.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC1_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_O1": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_O1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB" + }, + "RIOI3_TBYTESRC.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE0" + }, + "RIOI3_TBYTESRC.RIOI_I0->RIOI_IDELAY0_IDATAIN": { + "can_invert": "0", + "src_wire": "RIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IDATAIN" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.RIOI_IBUF0->RIOI_I0": { + "can_invert": "0", + "src_wire": "RIOI_IBUF0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_I0" + }, + "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN" + }, + "RIOI3_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2" + }, + "RIOI3_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_OFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_OFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEOUT->>IOI_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_TBYTEOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_TBYTEIN" + }, + "RIOI3_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR" + }, + "RIOI3_TBYTESRC.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY1_DATAOUT" + }, + "RIOI3_TBYTESRC.RIOI_OSOUT21->RIOI_OSIN20": { + "can_invert": "0", + "src_wire": "RIOI_OSOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN20" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY0" + }, + "RIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.RIOI_OSOUT11->RIOI_OSIN10": { + "can_invert": "0", + "src_wire": "RIOI_OSOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN10" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4" + }, + "RIOI3_TBYTESRC.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6" + }, + "RIOI3_TBYTESRC.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_T1": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_T1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TQ" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_TFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "RIOI3_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" }, "RIOI3_TBYTESRC.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_OCE", - "is_directional": "1", "src_wire": "IOI_IMUX29_1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE" + }, + "RIOI3_TBYTESRC.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_DDLY" + }, + "RIOI3_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4" + }, + "RIOI3_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY1_IFDLY1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" }, "RIOI3_TBYTESRC.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CE", - "is_directional": "1", "src_wire": "IOI_IMUX32_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", - "src_wire": "IOI_IMUX30_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE" + }, + "RIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN" + }, + "RIOI3_TBYTESRC.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2" + }, + "RIOI3_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "RIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OQ" + }, + "RIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4" + }, + "RIOI3_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "can_invert": "0", + "src_wire": "IOI_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" }, "RIOI3_TBYTESRC.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D8", - "is_directional": "1", "src_wire": "IOI_IMUX47_1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0" + }, + "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC0_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_DDLY" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD" + }, + "RIOI3_TBYTESRC.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY2" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1" + }, + "RIOI3_TBYTESRC.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC1_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TQ" + }, + "RIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3" + }, + "RIOI3_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_TFB" + }, + "RIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0" + }, + "RIOI3_TBYTESRC.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7" + }, + "RIOI3_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0" + }, + "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1" + }, + "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0" + }, + "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "RIOI3_TBYTESRC.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY1_IFDLY2" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_O0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_O0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST" + }, + "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "RIOI3_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C" + }, + "RIOI3_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE" + }, + "RIOI3_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC" + }, + "RIOI3_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1" + }, + "RIOI3_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTESRC.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE1" + }, + "RIOI3_TBYTESRC.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2" + }, + "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR" + }, + "RIOI3_TBYTESRC.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0" + }, + "RIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1" + }, + "RIOI3_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB" + }, + "RIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3" + }, + "RIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR" + }, + "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK" } }, - "tile_type": "RIOI3_TBYTESRC" + "wires": [ + "IOI_BYP5_1", + "IOI_IMUX26_1", + "IOI_NW4END3_1", + "IOI_ILOGIC1_REV", + "IOI_IMUX42_0", + "RIOI_I1", + "IOI_EE4A1_1", + "IOI_IMUX22_1", + "IOI_ILOGIC0_CE2", + "RIOI_ILOGIC1_D", + "IOI_IMUX5_0", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "IOI_OLOGIC1_CLKB", + "IOI_WW4C1_1", + "IOI_ER1BEG0_1", + "IOI_IMUX23_0", + "IOI_RCLK_DIV_CLR0_1", + "IOI_OLOGIC1_T1", + "IOI_IOCLK3", + "RIOI_OLOGIC0_TFB", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_RCLK_DIV_CE2_1", + "IOI_DCI_TSTRST", + "IOI_OLOGIC1_REV", + "IOI_WW4END1_0", + "IOI_CTRL0_1", + "IOI_MONITOR_N", + "IOI_ILOGIC1_Q7", + "IOI_IMUX38_0", + "IOI_WW4B1_1", + "IOI_EE4C1_1", + "IOI_IOCLK2", + "IOI_OLOGIC1_D8", + "IOI_LEAF_GCLK4", + "IOI_WW2END2_1", + "IOI_BYP2_0", + "IOI_ILOGIC1_Q1", + "IOI_IMUX36_1", + "IOI_LEAF_GCLK3", + "IOI_SW2A0_1", + "IOI_IMUX16_1", + "IOI_FAN2_1", + "IOI_IMUX27_0", + "IOI_IMUX22_0", + "IOI_EL1BEG2_1", + "IOI_NW4A1_0", + "IOI_BLOCK_OUTS0_1", + "IOI_SE2A1_0", + "IOI_IMUX4_1", + "IOI_EL1BEG2_0", + "IOI_WW4B0_1", + "IOI_NE4BEG3_1", + "IOI_SW4A3_1", + "IOI_SW4A1_0", + "IOI_ODELAY0_LDPIPEEN", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_EE4B3_1", + "IOI_NE4C0_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_IDELAYCTRL_OUTN65", + "IOI_BYP4_1", + "IOI_EE2BEG1_0", + "IOI_LOGIC_OUTS20_0", + "IOI_SE4C3_1", + "IOI_WL1END2_0", + "IOI_CTRL1_1", + "RIOI_ISOUT21", + "IOI_FAN5_0", + "IOI_EE2A2_0", + "IOI_WW4END2_1", + "IOI_WW4C0_0", + "IOI_IDELAY1_REGRST", + "IOI_PHASER_TO_IO_OCLK", + "IOI_SW4A0_1", + "IOI_IDELAY1_CNTVALUEIN0", + "RIOI_OLOGIC1_OFB", + "IOI_OLOGIC0_CLKDIV", + "IOI_IMUX17_0", + "IOI_WW2END2_0", + "IOI_FAN3_0", + "IOI_LOGIC_OUTS14_0", + "IOI_DCI_TSTCLK", + "IOI_FAN0_0", + "IOI_ODELAY1_CINVCTRL", + "IOI_SE4BEG0_0", + "IOI_IMUX20_1", + "IOI_EE2BEG3_0", + "IOI_LH7_0", + "IOI_IMUX15_1", + "IOI_ILOGIC0_Q3", + "IOI_EE4A1_0", + "IOI_ILOGIC1_Q8", + "IOI_IDELAY1_C", + "IOI_BYP7_0", + "IOI_IMUX25_0", + "IOI_IDELAY0_REGRST", + "IOI_BYP3_1", + "IOI_NE2A0_1", + "IOI_IMUX11_1", + "IOI_SE4BEG0_1", + "IOI_ILOGIC0_OCLKB", + "RIOI_OLOGIC1_TFB_LOCAL", + "IOI_IMUX47_0", + "IOI_OLOGIC0_D4", + "IOI_SE2A0_0", + "IOI_SE4BEG1_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_SW4END3_0", + "IOI_EE4BEG3_0", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLKB", + "IOI_LOGIC_OUTS19_1", + "IOI_EL1BEG1_1", + "IOI_OLOGIC0_D3", + "IOI_EE4C0_0", + "RIOI_KEEPER_INT_EN_1", + "IOI_OLOGIC0_TCE", + "IOI_WW2A0_0", + "IOI_ODELAY0_CLKIN", + "IOI_DCI_TSTHLN", + "IOI_IMUX15_0", + "IOI_WW2END1_1", + "IOI_NE4C3_1", + "IOI_ILOGIC0_O", + "IOI_RCLK_DIV_CE3", + "IOI_BLOCK_OUTS0_0", + "IOI_SE4C3_0", + "IOI_ILOGIC1_CLKDIV", + "IOI_BYP0_1", + "IOI_IMUX32_0", + "IOI_OLOGIC1_D5", + "IOI_LH4_0", + "IOI_RCLK_DIV_CLR1", + "IOI_IMUX10_0", + "IOI_NW2A0_1", + "IOI_ILOGIC0_REV", + "RIOI_ISIN20", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_LOGIC_OUTS1_1", + "IOI_OLOGIC0_T1", + "IOI_EE4BEG1_0", + "RIOI_ISIN11", + "RIOI_OLOGIC0_TFB_LOCAL", + "IOI_IMUX41_0", + "IOI_WW4C3_0", + "IOI_LOGIC_OUTS23_0", + "IOI_RCLK_DIV_CE0", + "RIOI_ODELAY1_OFDLY2", + "IOI_SW2A3_1", + "IOI_EE4B3_0", + "IOI_IOCLK0", + "IOI_EE4BEG0_0", + "IOI_ODELAY0_INC", + "IOI_IMUX6_0", + "IOI_IMUX40_0", + "IOI_IMUX10_1", + "IOI_WR1END3_0", + "RIOI_ILOGIC0_DDLY", + "IOI_IMUX37_1", + "IOI_OLOGIC0_REV", + "IOI_OLOGIC0_D1", + "IOI_IOCLK1", + "IOI_RCLK_FORIO1", + "IOI_ODELAY1_LD", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_WW4A1_1", + "IOI_NE4C0_0", + "IOI_NW4A2_1", + "IOI_LOGIC_OUTS6_1", + "IOI_LH3_1", + "IOI_IMUX33_0", + "IOI_IMUX13_0", + "IOI_IMUX9_0", + "IOI_EE4BEG0_1", + "IOI_WW2A2_1", + "IOI_WR1END0_1", + "IOI_OLOGIC0_T3", + "IOI_EE4A2_0", + "IOI_IMUX26_0", + "IOI_IMUX0_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX3_0", + "IOI_EE4B2_0", + "RIOI_IBUF_DISABLE0", + "IOI_SW2A2_1", + "IOI_OLOGIC0_OCE", + "IOI_ILOGIC0_CE1", + "IOI_LOGIC_OUTS8_0", + "IOI_SE2A2_1", + "IOI_WW2END0_0", + "IOI_SW2A1_0", + "RIOI_OSOUT10", + "IOI_RCLK_FORIO2", + "RIOI_OLOGIC1_TQ", + "IOI_LH3_0", + "IOI_EE4B1_0", + "IOI_SW4END1_0", + "IOI_WW4A2_0", + "IOI_ER1BEG3_0", + "IOI_LH6_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_IMUX40_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IMUX2_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_BYP1_1", + "IOI_SW4END1_1", + "RIOI_I2GCLK_BOT1", + "RIOI3_IDELAY0_IFDLY2", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_IDELAYCTRL_RDY", + "IOI_ODELAY1_CNTVALUEOUT0", + "IOI_IMUX44_0", + "IOI_NW2A2_0", + "IOI_OLOGIC1_D4", + "IOI_SW4A1_1", + "IOI_LOGIC_OUTS22_1", + "IOI_RCLK_DIV_CE3_1", + "IOI_OLOGIC0_D6", + "IOI_IDELAY0_CINVCTRL", + "IOI_IMUX25_1", + "IOI_WW4END1_1", + "IOI_WW4END0_1", + "IOI_SE4BEG2_0", + "IOI_LOGIC_OUTS16_0", + "IOI_NW4END3_0", + "IOI_NE4BEG2_0", + "IOI_DCI_DCIDONE", + "IOI_OLOGIC1_TBYTEIN", + "IOI_ILOGIC0_CLKDIVP", + "IOI_IMUX13_1", + "IOI_LOGIC_OUTS7_0", + "IOI_IMUX_RC1", + "IOI_CLK0_1", + "IOI_NE2A3_1", + "IOI_DCI_TSTRST0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_LEAF_GCLK2", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_IDELAY1_INC", + "IOI_OLOGIC1_OCE", + "IOI_LOGIC_OUTS13_0", + "IOI_CLK1_1", + "RIOI_T1", + "RIOI_ISOUT11", + "IOI_NE4C2_1", + "IOI_WW4B0_0", + "IOI_ODELAY1_CNTVALUEIN0", + "IOI_WL1END3_1", + "IOI_IMUX28_0", + "IOI_NW4END1_0", + "IOI_OLOGIC1_D7", + "IOI_LOGIC_OUTS11_0", + "IOI_IDELAY0_CNTVALUEIN0", + "RIOI_IDELAY1_IDATAIN", + "IOI_IMUX18_1", + "IOI_WW4A0_1", + "RIOI_I0", + "IOI_OLOGIC0_D8", + "IOI_IMUX38_1", + "IOI_IMUX21_0", + "IOI_EE2BEG1_1", + "IOI_EE4B0_0", + "IOI_FAN4_0", + "IOI_IDELAYCTRL_RST", + "IOI_SW4A2_0", + "IOI_NW2A0_0", + "IOI_OCLKM_0", + "IOI_EE2BEG0_1", + "IOI_LOGIC_OUTS14_1", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_ODELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_0", + "IOI_ILOGIC1_OCLK", + "RIOI_DIFF_TERM_INT_EN", + "IOI_IMUX17_1", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_SW4END3_1", + "IOI_ODELAY1_CLKIN", + "IOI_NE2A1_0", + "IOI_EE4A2_1", + "IOI_OCLKM_1", + "RIOI_OLOGIC1_CLKDIVF", + "IOI_IMUX43_0", + "IOI_LH8_1", + "IOI_RCLK_DIV_CE1", + "IOI_LOGIC_OUTS17_0", + "IOI_SE2A3_0", + "IOI_ILOGIC1_Q6", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LH9_0", + "IOI_OLOGIC0_D2", + "IOI_OLOGIC0_CLKDIVB", + "RIOI_ILOGIC0_D", + "IOI_IMUX30_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_LOGIC_OUTS0_0", + "IOI_WW2A1_0", + "IOI_BYP7_1", + "RIOI_ODELAY0_DATAOUT", + "RIOI_ODELAY0_ODATAIN", + "IOI_SE4C1_0", + "IOI_IMUX39_1", + "IOI_OCLK_1", + "IOI_EL1BEG0_1", + "IOI_ILOGIC0_Q4", + "IOI_IMUX45_1", + "IOI_IMUX20_0", + "RIOI_ODELAY0_OFDLY0", + "IOI_ODELAY1_REGRST", + "IOI_OLOGIC0_D5", + "IOI_ODELAY1_INC", + "IOI_ODELAY1_CNTVALUEIN3", + "RIOI_OLOGIC0_CLKDIVF", + "IOI_WW2A0_1", + "IOI_NW2A1_0", + "IOI_WW2A2_0", + "IOI_EE2BEG3_1", + "IOI_ILOGIC0_Q8", + "IOI_IMUX24_0", + "IOI_OLOGIC0_T2", + "IOI_IDELAY0_LD", + "IOI_FAN5_1", + "IOI_OLOGIC1_T2", + "IOI_LOGIC_OUTS3_1", + "RIOI_ISOUT20", + "IOI_FAN3_1", + "IOI_BYP0_0", + "IOI_IMUX35_1", + "IOI_ILOGIC1_OCLKB", + "IOI_IMUX27_1", + "IOI_WW4END3_1", + "IOI_BLOCK_OUTS2_1", + "RIOI_O1", + "IOI_EE2BEG2_0", + "IOI_NE2A3_0", + "IOI_SE2A1_1", + "IOI_NE4BEG3_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_LH12_0", + "RIOI3_IDELAY0_IFDLY1", + "IOI_LH2_1", + "IOI_ER1BEG3_1", + "IOI_LH1_1", + "IOI_ILOGIC1_CE2", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_FAN4_1", + "IOI_IDELAY0_CE", + "IOI_EE4C2_1", + "IOI_OLOGIC0_CLK", + "IOI_LOGIC_OUTS12_1", + "RIOI_ISIN21", + "IOI_SW2A3_0", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_ODELAY1_CNTVALUEIN2", + "RIOI_ILOGIC1_TFB", + "IOI_SW2A1_1", + "IOI_LH1_0", + "IOI_FAN1_1", + "IOI_LOGIC_OUTS10_1", + "RIOI_OSIN21", + "IOI_LOGIC_OUTS22_0", + "IOI_IMUX34_1", + "IOI_WW4A1_0", + "IOI_FAN7_0", + "IOI_IDELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OCLK_0", + "IOI_ODELAY0_REGRST", + "IOI_LOGIC_OUTS15_0", + "IOI_LEAF_GCLK0", + "IOI_EE2A0_1", + "IOI_IMUX12_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_IMUX23_1", + "IOI_ODELAY0_CNTVALUEIN2", + "RIOI_ODELAY1_OFDLY1", + "IOI_LOGIC_OUTS15_1", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_EL1BEG3_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IMUX39_0", + "IOI_WR1END0_0", + "IOI_ODELAY1_CNTVALUEIN4", + "IOI_IMUX19_0", + "IOI_RCLK_FORIO3", + "IOI_BYP1_0", + "IOI_ILOGIC0_Q2", + "RIOI_KEEPER_INT_EN_0", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_NW2A3_1", + "IOI_IDELAY0_C", + "RIOI_IDELAY1_DATAOUT", + "IOI_NW2A2_1", + "IOI_SW4END2_0", + "IOI_SW4END0_0", + "IOI_IMUX32_1", + "RIOI_IDELAY0_DATAOUT", + "IOI_IMUX19_1", + "RIOI_OLOGIC0_OFB", + "IOI_SW2A0_0", + "IOI_IMUX46_0", + "IOI_WR1END1_0", + "RIOI3_IDELAY0_IFDLY0", + "IOI_LOGIC_OUTS19_0", + "IOI_LOGIC_OUTS1_0", + "IOI_IMUX8_0", + "IOI_WW4C2_1", + "IOI_WW4C3_1", + "IOI_WW2END3_1", + "RIOI_DCI_T_TERM1", + "IOI_LH5_1", + "IOI_ODELAY1_CE", + "IOI_ILOGIC1_CLKDIVP", + "IOI_OLOGIC0_T4", + "IOI_NE4C2_0", + "IOI_IMUX31_1", + "IOI_NE4C3_0", + "IOI_NW4END2_1", + "IOI_IMUX7_1", + "IOI_IDELAY1_LD", + "IOI_LOGIC_OUTS23_1", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_LOGIC_OUTS9_0", + "IOI_EE2A0_0", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_WW4A3_1", + "IOI_IMUX9_1", + "IOI_NW2A1_1", + "IOI_IMUX1_0", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS9_1", + "IOI_IMUX42_1", + "IOI_RCLK_DIV_CLR3", + "IOI_IMUX21_1", + "IOI_EE2BEG0_0", + "IOI_IMUX1_1", + "RIOI_PU_INT_EN_1", + "IOI_OLOGIC1_T4", + "IOI_LH7_1", + "IOI_LOGIC_OUTS0_1", + "IOI_ILOGIC1_O", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_LOGIC_OUTS2_0", + "IOI_FAN0_1", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_ILOGIC0_OCLK", + "IOI_IMUX30_0", + "IOI_SE4C1_1", + "IOI_NE4BEG0_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LOGIC_OUTS4_1", + "IOI_WL1END2_1", + "IOI_LEAF_GCLK5", + "RIOI3_IDELAY1_IFDLY0", + "IOI_IMUX43_1", + "IOI_EE2BEG2_1", + "RIOI_ILOGIC0_OFB", + "IOI_NW4A2_0", + "IOI_ER1BEG1_1", + "IOI_NW4END0_0", + "IOI_BYP5_0", + "RIOI_OLOGIC1_OQ", + "IOI_ILOGIC1_Q3", + "IOI_LH4_1", + "IOI_IMUX37_0", + "RIOI_DCI_T_TERM0", + "IOI_IDELAY1_DATAIN", + "IOI_IMUX_RC3", + "IOI_ILOGIC0_CLKB", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IDELAY1_CNTVALUEIN3", + "RIOI_OSIN10", + "IOI_IDELAY1_CNTVALUEIN2", + "IOI_IMUX16_0", + "IOI_SW4A2_1", + "RIOI_OSOUT11", + "RIOI_T0", + "IOI_WW4END0_0", + "IOI_BLOCK_OUTS2_0", + "IOI_EE4BEG2_1", + "IOI_NW2A3_0", + "IOI_IMUX_RC0", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WR1END3_1", + "IOI_NW4END1_1", + "IOI_SE2A2_0", + "IOI_ILOGIC0_Q6", + "IOI_NW4A3_1", + "IOI_EE4B2_1", + "IOI_SE4BEG3_0", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_IMUX36_0", + "IOI_LOGIC_OUTS5_0", + "IOI_LH8_0", + "IOI_IMUX12_0", + "IOI_EE4C3_0", + "IOI_ODELAY1_CNTVALUEOUT2", + "IOI_SW4END0_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_OLOGIC1_CLKDIVFB", + "RIOI_I2GCLK_TOP0", + "IOI_IMUX0_1", + "RIOI_OSIN11", + "IOI_CLK1_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_OLOGIC0_D7", + "IOI_BLOCK_OUTS3_1", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_WW4END3_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_OLOGIC1_D6", + "IOI_IMUX29_0", + "IOI_LOGIC_OUTS18_0", + "IOI_WL1END1_0", + "IOI_LH6_1", + "IOI_EL1BEG0_0", + "IOI_ILOGIC1_Q2", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_LEAF_GCLK1", + "IOI_EE2A1_0", + "IOI_WW4B1_0", + "IOI_DCI_TSTHLP", + "IOI_EE4A0_0", + "IOI_BYP3_0", + "IOI_FAN6_0", + "IOI_LOGIC_OUTS10_0", + "IOI_SE4BEG2_1", + "RIOI_OLOGIC1_TFB", + "IOI_IMUX29_1", + "RIOI_OSIN20", + "IOI_IDELAY0_LDPIPEEN", + "IOI_ILOGIC0_SR", + "IOI_WW4A0_0", + "IOI_NE4BEG2_1", + "IOI_IDELAY1_CE", + "IOI_WL1END0_0", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IDELAY0_INC", + "IOI_SE4C0_1", + "IOI_OLOGIC1_T3", + "IOI_LH10_0", + "RIOI_ODELAY1_DATAOUT", + "IOI_EE4A3_0", + "IOI_ILOGIC1_CE1", + "IOI_FAN7_1", + "IOI_WW4B3_0", + "IOI_WL1END0_1", + "IOI_IMUX45_0", + "IOI_ODELAY1_C", + "IOI_LH12_1", + "IOI_WW2END3_0", + "IOI_WR1END2_0", + "IOI_IMUX11_0", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_NE2A0_0", + "RIOI_ODELAY0_OFDLY2", + "IOI_NW4END0_1", + "IOI_WW4A2_1", + "IOI_EL1BEG3_1", + "RIOI_ISOUT10", + "IOI_EE2A3_1", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_WR1END2_1", + "RIOI_ILOGIC0_TFB", + "IOI_ODELAY0_LD", + "RIOI_ODELAY1_ODATAIN", + "IOI_MONITOR_P", + "IOI_EE4BEG3_1", + "IOI_WW2END0_1", + "IOI_OLOGIC0_CLKB", + "IOI_RCLK_DIV_CE2", + "IOI_OLOGIC1_D2", + "IOI_LH11_1", + "IOI_IMUX34_0", + "RIOI_IBUF0", + "IOI_LH9_1", + "IOI_BYP6_0", + "IOI_ILOGIC1_BITSLIP", + "RIOI_OSOUT21", + "IOI_SE4BEG3_1", + "IOI_TBYTEIN", + "IOI_WW4B2_1", + "IOI_ODELAY1_CNTVALUEOUT4", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS12_0", + "IOI_NW4A3_0", + "IOI_SE4C0_0", + "IOI_NE2A1_1", + "IOI_LOGIC_OUTS20_1", + "IOI_SW4A3_0", + "IOI_SE4C2_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_BLOCK_OUTS1_1", + "IOI_EE4A0_1", + "IOI_WL1END3_0", + "IOI_WW2A3_0", + "IOI_CLK0_0", + "IOI_NE4BEG1_0", + "IOI_OLOGIC1_TCE", + "IOI_OLOGIC1_D3", + "IOI_LOGIC_OUTS6_0", + "IOI_IMUX2_1", + "IOI_ODELAY1_CNTVALUEOUT1", + "RIOI_O0", + "IOI_IMUX44_1", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE4A3_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX5_1", + "IOI_EE2A1_1", + "IOI_WW4B3_1", + "IOI_ILOGIC1_Q4", + "IOI_WW2A1_1", + "IOI_INT_DCI_EN", + "IOI_IMUX47_1", + "IOI_IMUX3_1", + "IOI_IMUX6_1", + "RIOI_PD_INT_EN_0", + "IOI_NE2A2_0", + "IOI_WW4B2_0", + "IOI_FAN6_1", + "IOI_BLOCK_OUTS3_0", + "IOI_IDELAY0_DATAIN", + "IOI_EE4B0_1", + "IOI_LOGIC_OUTS13_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_LH11_0", + "IOI_LH10_1", + "IOI_NW4A0_0", + "RIOI_ODELAY0_OFDLY1", + "IOI_BYP2_1", + "IOI_LOGIC_OUTS5_1", + "IOI_NW4END2_0", + "IOI_WW4C1_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WR1END1_1", + "RIOI3_IDELAY1_IFDLY2", + "RIOI_OLOGIC0_TQ", + "IOI_LOGIC_OUTS16_1", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC1_CLK", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_IMUX7_0", + "IOI_FAN1_0", + "IOI_IMUX41_1", + "IOI_WW2A3_1", + "IOI_SE2A3_1", + "RIOI_PU_INT_EN_0", + "IOI_LOGIC_OUTS2_1", + "IOI_CTRL1_0", + "IOI_RCLK_FORIO0", + "IOI_IMUX8_1", + "IOI_SW4A0_0", + "IOI_BLOCK_OUTS1_0", + "RIOI_IBUF_DISABLE1", + "IOI_WW4A3_0", + "IOI_ER1BEG0_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_RCLK_DIV_CLR1_1", + "IOI_RCLK_DIV_CLR2", + "IOI_NW4A1_1", + "IOI_EL1BEG1_0", + "IOI_FAN2_0", + "IOI_CTRL0_0", + "IOI_ILOGIC1_Q5", + "IOI_SE4BEG1_0", + "IOI_OLOGIC0_SR", + "RIOI_PD_INT_EN_1", + "IOI_ODELAY1_LDPIPEEN", + "IOI_LH2_0", + "IOI_EE4C3_1", + "IOI_ODELAY0_CE", + "IOI_EE2A3_0", + "IOI_OLOGIC1_D1", + "IOI_NW4A0_1", + "IOI_LOGIC_OUTS3_0", + "IOI_EE4C0_1", + "IOI_ILOGIC1_CLK", + "RIOI_OSOUT20", + "IOI_WW4C2_0", + "IOI_SW4END2_1", + "RIOI_ILOGIC1_DDLY", + "IOI_IMUX33_1", + "IOI_WW2END1_0", + "IOI_SE2A0_1", + "IOI_LOGIC_OUTS8_1", + "RIOI_IDELAY0_IDATAIN", + "IOI_LH5_0", + "RIOI3_IDELAY1_IFDLY1", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_ILOGIC0_Q1", + "IOI_OLOGIC1_CLKDIVB", + "IOI_NE4C1_1", + "IOI_NE4BEG0_1", + "IOI_OLOGIC1_SR", + "IOI_EE4B1_1", + "RIOI_ODELAY1_OFDLY0", + "IOI_IMUX14_1", + "IOI_ODELAY0_C", + "IOI_IMUX35_0", + "IOI_RCLK_DIV_CLR0", + "IOI_ILOGIC1_SR", + "IOI_NE4BEG1_1", + "IOI_BYP6_1", + "RIOI_OLOGIC0_OQ", + "IOI_ER1BEG2_1", + "IOI_IMUX4_0", + "IOI_EE4BEG2_0", + "IOI_LOGIC_OUTS4_0", + "IOI_NE2A2_1", + "RIOI_ILOGIC1_OFB", + "IOI_LOGIC_OUTS7_1", + "IOI_IMUX24_1", + "IOI_IMUX18_0", + "IOI_NE4C1_0", + "IOI_EE4BEG1_1", + "RIOI_IBUF1", + "RIOI_I2GCLK_TOP1", + "IOI_BYP4_0", + "RIOI_ISIN10", + "IOI_EE2A2_1", + "IOI_ER1BEG1_0", + "IOI_WL1END1_1", + "IOI_IMUX31_0", + "IOI_ER1BEG2_0", + "IOI_IMUX28_1", + "IOI_WW4C0_1", + "IOI_SE4C2_0", + "IOI_LOGIC_OUTS17_1", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_IMUX_RC2", + "IOI_WW4END2_0" + ], + "tile_type": "RIOI3_TBYTESRC", + "sites": [ + { + "site_pins": { + "T2": "IOI_OLOGIC1_T2", + "D5": "IOI_OLOGIC1_D5", + "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", + "D8": "IOI_OLOGIC1_D8", + "SR": "IOI_OLOGIC1_SR", + "SHIFTOUT1": "RIOI_OSOUT11", + "T4": "IOI_OLOGIC1_T4", + "SHIFTIN1": null, + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "OCE": "IOI_OLOGIC1_OCE", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "CLKB": "IOI_OLOGIC1_CLKB", + "OQ": "RIOI_OLOGIC1_OQ", + "D3": "IOI_OLOGIC1_D3", + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "SHIFTIN2": null, + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "D1": "IOI_OLOGIC1_D1", + "CLK": "IOI_OLOGIC1_CLK", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "T1": "IOI_OLOGIC1_T1", + "D4": "IOI_OLOGIC1_D4", + "TCE": "IOI_OLOGIC1_TCE", + "D2": "IOI_OLOGIC1_D2", + "SHIFTOUT2": "RIOI_OSOUT21", + "OFB": "RIOI_OLOGIC1_OFB", + "TFB": "RIOI_OLOGIC1_TFB", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "T3": "IOI_OLOGIC1_T3", + "D6": "IOI_OLOGIC1_D6", + "TQ": "RIOI_OLOGIC1_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "CLK": "IOI_ILOGIC1_CLK", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "Q3": "IOI_ILOGIC1_Q3", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "D": "RIOI_ILOGIC1_D", + "SR": "IOI_ILOGIC1_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC1_CE1", + "Q8": "IOI_ILOGIC1_Q8", + "SHIFTIN2": "RIOI_ISIN21", + "Q2": "IOI_ILOGIC1_Q2", + "CE2": "IOI_ILOGIC1_CE2", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "SHIFTOUT2": "RIOI_ISOUT21", + "O": "IOI_ILOGIC1_O", + "OFB": "RIOI_ILOGIC1_OFB", + "TFB": "RIOI_ILOGIC1_TFB", + "Q4": "IOI_ILOGIC1_Q4", + "CLKB": "IOI_ILOGIC1_CLKB", + "Q1": "IOI_ILOGIC1_Q1", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN1": "RIOI_ISIN11", + "Q6": "IOI_ILOGIC1_Q6", + "DDLY": "RIOI_ILOGIC1_DDLY", + "SHIFTOUT1": "RIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC1_Q7", + "OCLKB": "IOI_ILOGIC1_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "T2": "IOI_OLOGIC0_T2", + "D5": "IOI_OLOGIC0_D5", + "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", + "D8": "IOI_OLOGIC0_D8", + "SR": "IOI_OLOGIC0_SR", + "SHIFTOUT1": "RIOI_OSOUT10", + "T4": "IOI_OLOGIC0_T4", + "SHIFTIN1": "RIOI_OSIN10", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "OCE": "IOI_OLOGIC0_OCE", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "CLKB": "IOI_OLOGIC0_CLKB", + "OQ": "RIOI_OLOGIC0_OQ", + "D3": "IOI_OLOGIC0_D3", + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "SHIFTIN2": "RIOI_OSIN20", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "D1": "IOI_OLOGIC0_D1", + "CLK": "IOI_OLOGIC0_CLK", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "T1": "IOI_OLOGIC0_T1", + "D4": "IOI_OLOGIC0_D4", + "TCE": "IOI_OLOGIC0_TCE", + "D2": "IOI_OLOGIC0_D2", + "SHIFTOUT2": "RIOI_OSOUT20", + "OFB": "RIOI_OLOGIC0_OFB", + "TFB": "RIOI_OLOGIC0_TFB", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "T3": "IOI_OLOGIC0_T3", + "D6": "IOI_OLOGIC0_D6", + "TQ": "RIOI_OLOGIC0_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "CLK": "IOI_ILOGIC0_CLK", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "Q3": "IOI_ILOGIC0_Q3", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "D": "RIOI_ILOGIC0_D", + "SR": "IOI_ILOGIC0_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC0_CE1", + "Q8": "IOI_ILOGIC0_Q8", + "SHIFTIN2": null, + "Q2": "IOI_ILOGIC0_Q2", + "CE2": "IOI_ILOGIC0_CE2", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "SHIFTOUT2": "RIOI_ISOUT20", + "O": "IOI_ILOGIC0_O", + "OFB": "RIOI_ILOGIC0_OFB", + "TFB": "RIOI_ILOGIC0_TFB", + "Q4": "IOI_ILOGIC0_Q4", + "CLKB": "IOI_ILOGIC0_CLKB", + "Q1": "IOI_ILOGIC0_Q1", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN1": null, + "Q6": "IOI_ILOGIC0_Q6", + "DDLY": "RIOI_ILOGIC0_DDLY", + "SHIFTOUT1": "RIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC0_Q7", + "OCLKB": "IOI_ILOGIC0_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "IFDLY0": "RIOI3_IDELAY1_IFDLY0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", + "LD": "IOI_IDELAY1_LD", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "IDATAIN": "RIOI_IDELAY1_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "IFDLY2": "RIOI3_IDELAY1_IFDLY2", + "C": "IOI_IDELAY1_C", + "IFDLY1": "RIOI3_IDELAY1_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "DATAOUT": "RIOI_IDELAY1_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "IFDLY0": "RIOI3_IDELAY0_IFDLY0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", + "LD": "IOI_IDELAY0_LD", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "IDATAIN": "RIOI_IDELAY0_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "IFDLY2": "RIOI3_IDELAY0_IFDLY2", + "C": "IOI_IDELAY0_C", + "IFDLY1": "RIOI3_IDELAY0_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "DATAOUT": "RIOI_IDELAY0_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_RIOI3_TBYTETERM.json b/artix7/tile_type_RIOI3_TBYTETERM.json index 7d0bc97..5b1fbf0 100644 --- a/artix7/tile_type_RIOI3_TBYTETERM.json +++ b/artix7/tile_type_RIOI3_TBYTETERM.json @@ -1,3879 +1,3879 @@ { - "wires": [ - "IOI_LOGIC_OUTS17_1", - "IOI_WW2END3_1", - "IOI_SE4BEG2_0", - "RIOI3_IDELAY0_IFDLY1", - "RIOI_OLOGIC0_TFB_LOCAL", - "IOI_NW4A2_0", - "IOI_NW4END1_0", - "IOI_IMUX21_1", - "IOI_WR1END3_0", - "IOI_NE2A2_0", - "IOI_IMUX20_0", - "IOI_EE2BEG2_0", - "IOI_BYP3_1", - "IOI_OLOGIC1_D8", - "IOI_CLK1_1", - "IOI_ODELAY0_C", - "IOI_IMUX3_1", - "IOI_WR1END3_1", - "IOI_NW4END1_1", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_WW4END0_1", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_EE2A3_1", - "IOI_OLOGIC1_D6", - "IOI_IMUX9_1", - "IOI_IMUX35_0", - "IOI_BLOCK_OUTS3_1", - "RIOI3_IDELAY1_IFDLY1", - "IOI_OLOGIC0_D2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_OLOGIC0_CLKDIV", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_RCLK_DIV_CE2", - "IOI_SW2A2_1", - "IOI_WW4END1_1", - "IOI_ODELAY0_CE", - "IOI_NE2A1_0", - "RIOI_OLOGIC0_TQ", - "IOI_IMUX0_0", - "RIOI_ISOUT10", - "IOI_ER1BEG0_0", - "IOI_IMUX10_1", - "IOI_ILOGIC0_BITSLIP", - "IOI_NE4C3_0", - "IOI_IMUX10_0", - "IOI_EE4B3_0", - "IOI_IMUX45_1", - "IOI_LH4_0", - "IOI_NW4END2_0", - "IOI_OLOGIC0_SR", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_LH1_0", - "IOI_EE4A1_1", - "IOI_LOGIC_OUTS2_1", - "IOI_BLOCK_OUTS1_0", - "IOI_WW4B1_0", - "IOI_LH2_0", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_IDELAYCTRL_OUTN1", - "IOI_FAN4_1", - "IOI_IMUX12_1", - "RIOI_T1", - "IOI_OLOGIC1_TBYTEIN", - "IOI_IMUX1_1", - "IOI_IMUX8_0", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_CTRL0_0", - "IOI_IDELAY1_INC", - "IOI_IMUX24_1", - "IOI_SW2A2_0", - "IOI_NW4A2_1", - "IOI_LOGIC_OUTS12_1", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_INC", - "IOI_OLOGIC0_T4", - "IOI_ER1BEG1_0", - "RIOI_ODELAY1_OFDLY1", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_IMUX14_1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_ILOGIC1_Q1", - "IOI_EL1BEG2_0", - "IOI_ILOGIC1_SR", - "RIOI_KEEPER_INT_EN_0", - "RIOI_OLOGIC1_TFB", - "IOI_NE4BEG2_0", - "IOI_EL1BEG3_1", - "IOI_TBYTEIN_TERM", - "IOI_SW2A0_0", - "IOI_IMUX36_1", - "IOI_IMUX24_0", - "IOI_NW4END3_1", - "IOI_OLOGIC1_D2", - "IOI_EE4C1_1", - "IOI_LOGIC_OUTS21_0", - "IOI_IMUX4_1", - "IOI_WW4C3_0", - "IOI_OLOGIC0_D7", - "IOI_EE2A1_1", - "IOI_IMUX37_0", - "IOI_IDELAY1_CE", - "IOI_ODELAY1_CNTVALUEIN1", - "RIOI3_IDELAY0_IFDLY2", - "IOI_WW2A2_0", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_BYP4_1", - "IOI_IMUX42_1", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_IMUX30_0", - "IOI_IMUX35_1", - "IOI_LOGIC_OUTS19_1", - "IOI_LH8_1", - "IOI_IMUX33_0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_EE4BEG3_1", - "IOI_NE2A2_1", - "IOI_ILOGIC0_Q2", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_BYP7_0", - "IOI_SW4A2_0", - "IOI_IMUX42_0", - "IOI_WR1END0_1", - "IOI_WW2A2_1", - "IOI_MONITOR_P", - "RIOI_OSIN20", - "IOI_NE4C1_0", - "IOI_IMUX29_0", - "IOI_OCLKM_1", - "RIOI_ODELAY0_ODATAIN", - "IOI_WW4B2_1", - "IOI_OLOGIC0_REV", - "IOI_WW4END3_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LH7_1", - "IOI_NW2A3_1", - "IOI_LH12_1", - "IOI_EE4BEG2_0", - "IOI_LH7_0", - "RIOI_ILOGIC0_D", - "IOI_ER1BEG3_0", - "IOI_IMUX0_1", - "IOI_LOGIC_OUTS7_1", - "IOI_ILOGIC0_Q3", - "IOI_IDELAY0_LDPIPEEN", - "IOI_WW2END2_0", - "RIOI_PD_INT_EN_0", - "IOI_LH11_1", - "IOI_IDELAY1_CINVCTRL", - "IOI_NW4A3_1", - "RIOI_OLOGIC0_OQ", - "IOI_IMUX23_0", - "IOI_IMUX37_1", - "IOI_LOGIC_OUTS3_0", - "IOI_WW4A0_0", - "IOI_IOCLK0", - "RIOI_I2GCLK_BOT1", - "IOI_WW2END3_0", - "RIOI_ISOUT11", - "IOI_NE4BEG3_0", - "IOI_SE2A2_1", - "IOI_LEAF_GCLK0", - "IOI_IDELAY0_CNTVALUEIN1", - "RIOI_ODELAY1_OFDLY2", - "IOI_IMUX18_1", - "IOI_IDELAY0_CE", - "RIOI_ISIN21", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_NW4END3_0", - "IOI_WW4C0_1", - "IOI_SE4C3_0", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IMUX39_1", - "IOI_NW4A1_0", - "IOI_NE4BEG2_1", - "IOI_SE4BEG0_0", - "IOI_IMUX22_1", - "IOI_IMUX14_0", - "IOI_CLK1_0", - "IOI_SE4BEG3_0", - "IOI_OLOGIC0_D6", - "IOI_WW2A1_1", - "IOI_EE2A3_0", - "IOI_IMUX28_0", - "IOI_OCLK_0", - "IOI_IMUX18_0", - "IOI_NW2A1_1", - "RIOI_ILOGIC1_D", - "RIOI_OLOGIC0_TFB", - "IOI_IDELAY1_C", - "IOI_WW4A2_0", - "IOI_NE4C0_0", - "IOI_NW2A1_0", - "IOI_IMUX2_1", - "IOI_LOGIC_OUTS9_0", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_IMUX16_0", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_BLOCK_OUTS2_1", - "IOI_WL1END3_0", - "IOI_LOGIC_OUTS7_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_IDELAYCTRL_RDY", - "IOI_RCLK_DIV_CLR2", - "IOI_IMUX11_0", - "IOI_LOGIC_OUTS16_1", - "IOI_RCLK_DIV_CE3", - "IOI_WR1END2_0", - "IOI_LOGIC_OUTS18_1", - "IOI_SW4A0_0", - "IOI_NE4BEG1_1", - "IOI_WR1END1_0", - "IOI_OLOGIC1_CLK", - "IOI_EE4B0_0", - "IOI_WW4A3_1", - "RIOI_PU_INT_EN_0", - "IOI_RCLK_DIV_CLR1", - "IOI_LOGIC_OUTS15_0", - "RIOI_I2GCLK_TOP1", - "RIOI_I0", - "IOI_WW4B0_0", - "IOI_OLOGIC1_D3", - "IOI_ODELAY1_LD", - "RIOI_ILOGIC1_OFB", - "IOI_NW4END2_1", - "IOI_LOGIC_OUTS10_1", - "IOI_NE2A3_1", - "IOI_NW2A0_0", - "IOI_WW4END3_0", - "IOI_IOCLK3", - "IOI_SE2A3_0", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_WW2A3_0", - "IOI_ILOGIC0_CE1", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_BYP1_1", - "RIOI_OSOUT20", - "IOI_SE4C1_1", - "IOI_SW4A3_1", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IMUX38_1", - "IOI_ER1BEG2_0", - "IOI_WW4C0_0", - "RIOI_DCI_T_TERM0", - "IOI_IMUX25_0", - "IOI_NE4BEG0_0", - "IOI_IMUX7_1", - "IOI_FAN3_1", - "IOI_OLOGIC1_SR", - "IOI_SW4END1_0", - "IOI_ILOGIC1_CE2", - "RIOI_DIFF_TERM_INT_EN", - "IOI_WW4END0_0", - "IOI_FAN7_0", - "IOI_LOGIC_OUTS1_0", - "IOI_EE2BEG0_0", - "IOI_SE4C0_1", - "IOI_OLOGIC1_T3", - "IOI_IMUX43_1", - "IOI_EE2BEG3_1", - "IOI_NE4C3_1", - "IOI_IMUX46_0", - "IOI_IMUX34_1", - "IOI_IMUX27_0", - "RIOI_IBUF_DISABLE0", - "IOI_DCI_TSTCLK", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_D8", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_EE4C2_0", - "IOI_IMUX11_1", - "IOI_CTRL1_0", - "IOI_DCI_TSTHLP", - "IOI_EE4A3_0", - "IOI_OLOGIC0_CLKB", - "IOI_WW4C3_1", - "IOI_IMUX40_0", - "RIOI_O0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_IMUX47_0", - "RIOI_OSIN10", - "IOI_OLOGIC1_CLKDIV", - "IOI_LOGIC_OUTS5_1", - "RIOI_OLOGIC1_TFB_LOCAL", - "IOI_BYP7_1", - "IOI_LOGIC_OUTS12_0", - "RIOI_OSOUT21", - "IOI_SE4BEG0_1", - "IOI_OLOGIC0_IOCLKGLITCH", - "RIOI_IBUF1", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_LOGIC_OUTS5_0", - "IOI_FAN4_0", - "IOI_WW4B0_1", - "IOI_WL1END0_1", - "IOI_IMUX2_0", - "IOI_WW2END0_0", - "IOI_LH2_1", - "IOI_WW4A1_1", - "IOI_WW4C1_1", - "RIOI_OSIN11", - "IOI_ER1BEG2_1", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_OLOGIC0_T1", - "IOI_IMUX3_0", - "IOI_EE2BEG1_0", - "IOI_IMUX29_1", - "IOI_WW2END0_1", - "IOI_OCLK_1", - "IOI_WW2A0_0", - "IOI_ER1BEG1_1", - "RIOI_ILOGIC1_DDLY", - "IOI_RCLK_FORIO2", - "IOI_PHASER_TO_IO_ICLK", - "IOI_NE4C2_0", - "IOI_BYP2_1", - "IOI_WR1END1_1", - "IOI_FAN3_0", - "IOI_ILOGIC1_BITSLIP", - "IOI_ODELAY0_LDPIPEEN", - "IOI_IMUX44_1", - "IOI_NE2A1_1", - "IOI_LOGIC_OUTS1_1", - "IOI_EE4B0_1", - "IOI_OLOGIC1_CLKB", - "IOI_RCLK_DIV_CLR0", - "IOI_ILOGIC1_CLKDIV", - "IOI_DCI_TSTHLN", - "IOI_OLOGIC1_D5", - "IOI_SW2A3_0", - "IOI_IDELAY1_REGRST", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_LOGIC_OUTS19_0", - "IOI_IMUX32_1", - "IOI_SE2A1_1", - "IOI_LOGIC_OUTS21_1", - "IOI_EE2A2_0", - "IOI_ODELAY1_REGRST", - "RIOI_OLOGIC1_OFB", - "IOI_LH9_0", - "IOI_FAN5_1", - "IOI_LH6_0", - "RIOI_ODELAY0_DATAOUT", - "IOI_ODELAY1_C", - "IOI_IMUX19_0", - "IOI_OLOGIC1_D4", - "IOI_LOGIC_OUTS10_0", - "IOI_ILOGIC0_OCLK", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_INT_DCI_EN", - "IOI_EL1BEG0_1", - "IOI_SW2A1_0", - "RIOI_OLOGIC0_CLKDIVF", - "IOI_OLOGIC1_D1", - "IOI_DCI_TSTRST0", - "IOI_OLOGIC0_T2", - "IOI_BLOCK_OUTS0_0", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_EE4BEG2_1", - "IOI_SE4BEG3_1", - "IOI_OLOGIC1_T2", - "IOI_WW4A0_1", - "IOI_IMUX26_0", - "IOI_IMUX45_0", - "IOI_MONITOR_N", - "IOI_IMUX8_1", - "IOI_RCLK_DIV_CLR3", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY1_CE", - "IOI_LH6_1", - "RIOI_OLOGIC1_CLKDIVF", - "RIOI_OLOGIC1_OQ", - "IOI_IOCLK1", - "IOI_FAN7_1", - "IOI_RCLK_DIV_CLR0_1", - "IOI_LOGIC_OUTS2_0", - "IOI_WW4A1_0", - "IOI_IMUX7_0", - "IOI_ODELAY1_INC", - "IOI_ILOGIC0_CLK", - "IOI_IMUX20_1", - "IOI_WW2END1_1", - "RIOI_IDELAY1_DATAOUT", - "IOI_LOGIC_OUTS11_0", - "IOI_SE4C0_0", - "IOI_LOGIC_OUTS17_0", - "IOI_ER1BEG3_1", - "IOI_ILOGIC0_CLKDIV", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_REV", - "IOI_FAN1_1", - "IOI_LH10_0", - "RIOI_ISOUT20", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC0_CE2", - "IOI_FAN6_1", - "IOI_IDELAY1_CNTVALUEOUT0", - "RIOI_ODELAY0_OFDLY0", - "IOI_IMUX5_0", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_SW4END0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_ILOGIC1_Q5", - "IOI_NE4BEG0_1", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_WW4B3_0", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_EE4BEG0_1", - "IOI_EE2BEG2_1", - "IOI_OLOGIC1_T1", - "IOI_IMUX6_1", - "IOI_EL1BEG2_1", - "IOI_SE4C1_0", - "IOI_NW4END0_1", - "RIOI_ODELAY1_OFDLY0", - "IOI_IMUX1_0", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_REV", - "IOI_SE4C2_1", - "IOI_SE4BEG2_1", - "IOI_EE4A0_1", - "IOI_IMUX36_0", - "IOI_EE2BEG0_1", - "RIOI_OSIN21", - "RIOI_ILOGIC0_DDLY", - "IOI_NW4A0_1", - "IOI_WW4END2_1", - "IOI_IMUX46_1", - "IOI_EE4A3_1", - "IOI_LOGIC_OUTS20_0", - "IOI_WL1END1_1", - "RIOI_OLOGIC1_TQ", - "IOI_SW4END1_1", - "IOI_IMUX13_1", - "IOI_ODELAY0_LD", - "IOI_ILOGIC1_Q8", - "IOI_IMUX23_1", - "IOI_IMUX_RC3", - "IOI_IMUX31_1", - "IOI_WW4A3_0", - "IOI_OLOGIC0_OCE", - "IOI_LOGIC_OUTS3_1", - "RIOI_O1", - "IOI_EE2A2_1", - "IOI_LOGIC_OUTS8_0", - "IOI_ILOGIC0_CLKB", - "IOI_IMUX27_1", - "IOI_NE2A0_1", - "IOI_RCLK_DIV_CE1", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_NE2A0_0", - "IOI_IDELAY0_REGRST", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_SE4BEG1_1", - "IOI_IMUX_RC2", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_ILOGIC0_O", - "IOI_EE4A1_0", - "IOI_IDELAYCTRL_RST", - "IOI_SW4A1_0", - "RIOI3_IDELAY1_IFDLY2", - "IOI_EE4A2_1", - "IOI_LOGIC_OUTS9_1", - "RIOI_ISIN20", - "IOI_WW4A2_1", - "IOI_FAN2_1", - "IOI_FAN5_0", - "RIOI_ODELAY0_OFDLY2", - "IOI_IMUX16_1", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_IOCLK2", - "IOI_OLOGIC1_D7", - "RIOI_PU_INT_EN_1", - "IOI_IMUX6_0", - "RIOI_IBUF0", - "IOI_LOGIC_OUTS4_0", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC1_Q4", - "IOI_NW4END0_0", - "RIOI_OLOGIC0_OFB", - "IOI_FAN0_1", - "IOI_BLOCK_OUTS3_0", - "IOI_IMUX38_0", - "IOI_IDELAY0_CINVCTRL", - "IOI_OLOGIC1_OCE", - "IOI_EE4A2_0", - "IOI_BLOCK_OUTS0_1", - "IOI_IMUX4_0", - "IOI_OLOGIC1_CLKDIVB", - "IOI_SW4END2_0", - "IOI_BYP0_1", - "IOI_IMUX_RC0", - "IOI_IMUX31_0", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IMUX15_0", - "IOI_EE4C3_0", - "IOI_LOGIC_OUTS11_1", - "IOI_NE4BEG1_0", - "IOI_SW4END2_1", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS4_1", - "IOI_WR1END0_0", - "IOI_IDELAY0_C", - "IOI_SE2A2_0", - "IOI_LOGIC_OUTS13_0", - "IOI_ILOGIC1_OCLK", - "IOI_BYP4_0", - "IOI_WW2A1_0", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_IDELAY0_DATAIN", - "IOI_EE4B2_1", - "IOI_IMUX28_1", - "IOI_LEAF_GCLK5", - "IOI_SW4A3_0", - "IOI_BLOCK_OUTS1_1", - "IOI_WW4C1_0", - "IOI_IMUX9_0", - "IOI_BYP5_0", - "IOI_LOGIC_OUTS18_0", - "IOI_NW4A0_0", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_LH10_1", - "IOI_IMUX12_0", - "RIOI_PD_INT_EN_1", - "RIOI_ISIN11", - "IOI_LOGIC_OUTS23_0", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_DCI_DCIDONE", - "IOI_SE2A0_0", - "IOI_IMUX21_0", - "IOI_EE4B1_1", - "IOI_RCLK_DIV_CE3_1", - "IOI_EE4BEG0_0", - "RIOI_I1", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ILOGIC1_CLK", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_LOGIC_OUTS14_1", - "IOI_BYP3_0", - "IOI_EE2A0_1", - "IOI_LEAF_GCLK4", - "IOI_SW4A2_1", - "IOI_OLOGIC1_T4", - "IOI_LOGIC_OUTS0_0", - "IOI_WW2END1_0", - "IOI_BYP5_1", - "IOI_ER1BEG0_1", - "IOI_LOGIC_OUTS16_0", - "IOI_IMUX5_1", - "IOI_NW4A3_0", - "IOI_EE4BEG1_1", - "RIOI3_IDELAY0_IFDLY0", - "IOI_SW2A1_1", - "RIOI_ILOGIC0_TFB", - "IOI_IDELAY0_LD", - "IOI_EE2A0_0", - "IOI_ODELAY1_CNTVALUEOUT0", - "RIOI_ILOGIC0_OFB", - "IOI_CLK0_1", - "IOI_RCLK_FORIO3", - "IOI_IMUX44_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_ILOGIC1_O", - "IOI_SE2A3_1", - "RIOI_I2GCLK_TOP0", - "IOI_ILOGIC1_REV", - "IOI_ODELAY0_CNTVALUEIN0", - "RIOI_T0", - "IOI_EE2A1_0", - "IOI_IMUX17_1", - "IOI_FAN1_0", - "IOI_EE4A0_0", - "IOI_LOGIC_OUTS22_0", - "RIOI_ISOUT21", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_RCLK_DIV_CE0", - "RIOI_ODELAY1_ODATAIN", - "IOI_WW4C2_0", - "IOI_NW2A3_0", - "IOI_IMUX34_0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_NE4C2_1", - "IOI_IMUX22_0", - "IOI_OLOGIC0_T3", - "IOI_ODELAY1_CINVCTRL", - "IOI_IMUX17_0", - "RIOI_ODELAY0_OFDLY1", - "IOI_WW4B2_0", - "IOI_FAN6_0", - "IOI_IDELAY1_LDPIPEEN", - "IOI_WL1END0_0", - "IOI_OCLKM_0", - "IOI_IMUX15_1", - "IOI_CLK0_0", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IMUX25_1", - "RIOI_IDELAY1_IDATAIN", - "IOI_EL1BEG0_0", - "IOI_OLOGIC0_CLK", - "IOI_IMUX39_0", - "IOI_WL1END1_0", - "IOI_WL1END2_0", - "IOI_IMUX41_0", - "IOI_CTRL0_1", - "IOI_EE4C0_0", - "IOI_ILOGIC1_Q6", - "IOI_NW2A0_1", - "IOI_EE2BEG1_1", - "RIOI_ODELAY1_DATAOUT", - "IOI_ILOGIC1_Q2", - "IOI_CTRL1_1", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_OLOGIC0_D4", - "IOI_SE4BEG1_0", - "IOI_EE2BEG3_0", - "IOI_LOGIC_OUTS15_1", - "IOI_SW4A1_1", - "IOI_EL1BEG1_0", - "IOI_DCI_TSTRST", - "IOI_SW2A3_1", - "IOI_NE4C0_1", - "IOI_ILOGIC1_CLKDIVP", - "IOI_IMUX30_1", - "IOI_ILOGIC0_Q5", - "IOI_IDELAYCTRL_OUTN65", - "IOI_WR1END2_1", - "IOI_WW4B1_1", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_EE4BEG3_0", - "IOI_SE2A0_1", - "IOI_FAN0_0", - "RIOI_DCI_T_TERM1", - "RIOI_ILOGIC1_TFB", - "IOI_EE4BEG1_0", - "IOI_IMUX47_1", - "IOI_LH1_1", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC0_OCLKB", - "IOI_RCLK_DIV_CE2_1", - "IOI_BYP2_0", - "IOI_EE4C1_0", - "IOI_WW2END2_1", - "IOI_IMUX43_0", - "IOI_BYP6_1", - "IOI_RCLK_FORIO1", - "IOI_ILOGIC1_OCLKB", - "IOI_LEAF_GCLK1", - "IOI_NW2A2_0", - "RIOI_KEEPER_INT_EN_1", - "IOI_IMUX33_1", - "IOI_LH11_0", - "IOI_ILOGIC0_Q6", - "IOI_SW4END3_1", - "IOI_ODELAY1_CLKIN", - "IOI_NW2A2_1", - "IOI_LH9_1", - "RIOI_OSOUT11", - "IOI_PHASER_TO_IO_OCLK", - "RIOI3_IDELAY1_IFDLY0", - "IOI_EE4B3_1", - "IOI_WW4B3_1", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "RIOI_IDELAY0_IDATAIN", - "IOI_ILOGIC1_Q3", - "IOI_FAN2_0", - "IOI_WW4C2_1", - "IOI_WL1END2_1", - "IOI_RCLK_FORIO0", - "IOI_SW4A0_1", - "IOI_NW4A1_1", - "RIOI_IBUF_DISABLE1", - "IOI_IMUX41_1", - "IOI_LOGIC_OUTS13_1", - "IOI_BLOCK_OUTS2_0", - "IOI_WW4END1_0", - "IOI_IMUX40_1", - "IOI_IMUX19_1", - "IOI_EE4B1_0", - "IOI_WL1END3_1", - "IOI_LEAF_GCLK2", - "IOI_ODELAY0_CLKIN", - "IOI_EE4B2_0", - "IOI_SE2A1_0", - "IOI_BYP6_0", - "IOI_IMUX32_0", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_DATAIN", - "IOI_EE4C2_1", - "IOI_LH5_1", - "IOI_ILOGIC0_Q7", - "IOI_IMUX_RC1", - "IOI_EL1BEG3_0", - "IOI_WW2A3_1", - "IOI_NE4C1_1", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_SW4END3_0", - "IOI_WW2A0_1", - "IOI_NE4BEG3_1", - "IOI_SE4C2_0", - "RIOI_OSOUT10", - "IOI_ODELAY0_INC", - "IOI_LOGIC_OUTS6_1", - "IOI_BYP1_0", - "IOI_NE2A3_0", - "IOI_ILOGIC1_Q7", - "IOI_ODELAY0_REGRST", - "IOI_ILOGIC0_CLKDIVP", - "IOI_EE4C3_1", - "IOI_SE4C3_1", - "IOI_ILOGIC1_CLKB", - "IOI_LOGIC_OUTS23_1", - "IOI_OLOGIC0_D1", - "IOI_EE4C0_1", - "IOI_LOGIC_OUTS22_1", - "IOI_OLOGIC1_TCE", - "IOI_LH8_0", - "RIOI_IDELAY0_DATAOUT", - "IOI_SW2A0_1", - "IOI_SW4END0_1", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_LOGIC_OUTS14_0", - "IOI_ODELAY1_LDPIPEEN", - "IOI_LH12_0", - "IOI_IMUX13_0", - "IOI_LEAF_GCLK3", - "IOI_BYP0_0", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ILOGIC0_Q4", - "IOI_EL1BEG1_1", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_WW4END2_0", - "IOI_IMUX26_1", - "RIOI_ISIN10", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_TBYTEIN", - "IOI_LOGIC_OUTS20_1" - ], - "sites": [ - { - "prefix": "OLOGIC", - "y_coord": 0, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC1_D1", - "D3": "IOI_OLOGIC1_D3", - "SR": "IOI_OLOGIC1_SR", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "TFB": "RIOI_OLOGIC1_TFB", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLK": "IOI_OLOGIC1_CLK", - "T4": "IOI_OLOGIC1_T4", - "OQ": "RIOI_OLOGIC1_OQ", - "D8": "IOI_OLOGIC1_D8", - "T1": "IOI_OLOGIC1_T1", - "D5": "IOI_OLOGIC1_D5", - "SHIFTOUT1": "RIOI_OSOUT11", - "T2": "IOI_OLOGIC1_T2", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "D4": "IOI_OLOGIC1_D4", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D2": "IOI_OLOGIC1_D2", - "TQ": "RIOI_OLOGIC1_TQ", - "T3": "IOI_OLOGIC1_T3", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "OCE": "IOI_OLOGIC1_OCE", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "SHIFTIN1": null, - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "TCE": "IOI_OLOGIC1_TCE", - "OFB": "RIOI_OLOGIC1_OFB", - "SHIFTIN2": null, - "SHIFTOUT2": "RIOI_OSOUT21", - "REV": null, - "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "ILOGIC", - "y_coord": 0, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q1": "IOI_ILOGIC1_Q1", - "SR": "IOI_ILOGIC1_SR", - "D": "RIOI_ILOGIC1_D", - "DDLY": "RIOI_ILOGIC1_DDLY", - "SHIFTIN2": "RIOI_ISIN21", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "Q3": "IOI_ILOGIC1_Q3", - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "Q8": "IOI_ILOGIC1_Q8", - "TFB": "RIOI_ILOGIC1_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC1_CE1", - "Q2": "IOI_ILOGIC1_Q2", - "Q6": "IOI_ILOGIC1_Q6", - "CLKB": "IOI_ILOGIC1_CLKB", - "Q7": "IOI_ILOGIC1_Q7", - "O": "IOI_ILOGIC1_O", - "CLK": "IOI_ILOGIC1_CLK", - "CE2": "IOI_ILOGIC1_CE2", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "SHIFTIN1": "RIOI_ISIN11", - "OCLK": "IOI_ILOGIC1_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "OFB": "RIOI_ILOGIC1_OFB", - "SHIFTOUT1": "RIOI_ISOUT11", - "SHIFTOUT2": "RIOI_ISOUT21", - "REV": null, - "CLKDIV": "IOI_ILOGIC1_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "OLOGIC", - "y_coord": 1, - "type": "OLOGICE3", - "site_pins": { - "D1": "IOI_OLOGIC0_D1", - "D3": "IOI_OLOGIC0_D3", - "SR": "IOI_OLOGIC0_SR", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "TFB": "RIOI_OLOGIC0_TFB", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLK": "IOI_OLOGIC0_CLK", - "T4": "IOI_OLOGIC0_T4", - "OQ": "RIOI_OLOGIC0_OQ", - "D8": "IOI_OLOGIC0_D8", - "T1": "IOI_OLOGIC0_T1", - "D5": "IOI_OLOGIC0_D5", - "SHIFTOUT1": "RIOI_OSOUT10", - "T2": "IOI_OLOGIC0_T2", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "D4": "IOI_OLOGIC0_D4", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D2": "IOI_OLOGIC0_D2", - "TQ": "RIOI_OLOGIC0_TQ", - "T3": "IOI_OLOGIC0_T3", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "OCE": "IOI_OLOGIC0_OCE", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "SHIFTIN1": "RIOI_OSIN10", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "TCE": "IOI_OLOGIC0_TCE", - "OFB": "RIOI_OLOGIC0_OFB", - "SHIFTIN2": "RIOI_OSIN20", - "SHIFTOUT2": "RIOI_OSOUT20", - "REV": null, - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "ILOGIC", - "y_coord": 1, - "type": "ILOGICE3", - "site_pins": { - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q1": "IOI_ILOGIC0_Q1", - "SR": "IOI_ILOGIC0_SR", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "SHIFTIN2": null, - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "Q3": "IOI_ILOGIC0_Q3", - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "Q8": "IOI_ILOGIC0_Q8", - "TFB": "RIOI_ILOGIC0_TFB", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "CE1": "IOI_ILOGIC0_CE1", - "Q2": "IOI_ILOGIC0_Q2", - "Q6": "IOI_ILOGIC0_Q6", - "CLKB": "IOI_ILOGIC0_CLKB", - "Q7": "IOI_ILOGIC0_Q7", - "O": "IOI_ILOGIC0_O", - "CLK": "IOI_ILOGIC0_CLK", - "CE2": "IOI_ILOGIC0_CE2", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "SHIFTIN1": null, - "OCLK": "IOI_ILOGIC0_OCLK", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "OFB": "RIOI_ILOGIC0_OFB", - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "REV": null, - "CLKDIV": "IOI_ILOGIC0_CLKDIV" - }, - "x_coord": 0, - "name": "X0Y1" - }, - { - "prefix": "IDELAY", - "y_coord": 0, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CE": "IOI_IDELAY1_CE", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "IFDLY2": "RIOI3_IDELAY1_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "LD": "IOI_IDELAY1_LD", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "IFDLY0": "RIOI3_IDELAY1_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "INC": "IOI_IDELAY1_INC", - "DATAOUT": "RIOI_IDELAY1_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY1_DATAIN", - "C": "IOI_IDELAY1_C", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "IDATAIN": "RIOI_IDELAY1_IDATAIN", - "REGRST": "IOI_IDELAY1_REGRST", - "IFDLY1": "RIOI3_IDELAY1_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y0" - }, - { - "prefix": "IDELAY", - "y_coord": 1, - "type": "IDELAYE2", - "site_pins": { - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CE": "IOI_IDELAY0_CE", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "IFDLY2": "RIOI3_IDELAY0_IFDLY2", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "LD": "IOI_IDELAY0_LD", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "IFDLY0": "RIOI3_IDELAY0_IFDLY0", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "INC": "IOI_IDELAY0_INC", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "DATAIN": "IOI_IDELAY0_DATAIN", - "C": "IOI_IDELAY0_C", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "REGRST": "IOI_IDELAY0_REGRST", - "IFDLY1": "RIOI3_IDELAY0_IFDLY1" - }, - "x_coord": 0, - "name": "X0Y1" - } - ], "pips": { - "RIOI3_TBYTETERM.IOI_IMUX42_0->IOI_OLOGIC1_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_OQ", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY1_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_I1->RIOI_ILOGIC1_D": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_D", - "is_directional": "1", - "src_wire": "RIOI_I1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC0_D", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX13_0->IOI_OLOGIC1_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY1_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC0_DDLY", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CTRL0_0->IOI_OLOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE2_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR1_1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX7_0->IOI_OLOGIC1_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q8", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { - "can_invert": "0", - "dst_wire": "RIOI_DCI_T_TERM1", - "is_directional": "1", - "src_wire": "IOI_IMUX6_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_ISOUT20->RIOI_ISIN21": { - "can_invert": "0", - "dst_wire": "RIOI_ISIN21", - "is_directional": "1", - "src_wire": "RIOI_ISOUT20", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_O1": { - "can_invert": "0", - "dst_wire": "RIOI_O1", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_OQ", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX40_0->IOI_OLOGIC1_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY1", - "is_directional": "1", - "src_wire": "IOI_FAN5_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX15_0->IOI_OLOGIC1_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_DDLY", - "is_directional": "1", - "src_wire": "RIOI_IDELAY0_DATAOUT", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX46_0->IOI_OLOGIC1_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OFB", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_OFB", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_0", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_IBUF0->RIOI_I0": { - "can_invert": "0", - "dst_wire": "RIOI_I0", - "is_directional": "1", - "src_wire": "RIOI_IBUF0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TQ", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_IMUX30_0->IOI_IDELAY1_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { - "can_invert": "0", - "dst_wire": "RIOI_IBUF_DISABLE1", - "is_directional": "1", - "src_wire": "IOI_IMUX9_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { - "can_invert": "0", - "dst_wire": "RIOI_DCI_T_TERM0", - "is_directional": "1", - "src_wire": "IOI_IMUX6_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX26_0->IOI_IDELAY1_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX46_1->IOI_OLOGIC0_D7": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D7", - "is_directional": "1", - "src_wire": "IOI_IMUX46_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_T1": { - "can_invert": "0", - "dst_wire": "RIOI_T1", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TQ", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX20_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_ISOUT10->RIOI_ISIN11": { - "can_invert": "0", - "dst_wire": "RIOI_ISIN11", - "is_directional": "1", - "src_wire": "RIOI_ISOUT10", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX45_0->IOI_OLOGIC1_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX21_0->IOI_OLOGIC1_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX43_1->IOI_OLOGIC0_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OSOUT11->RIOI_OSIN10": { - "can_invert": "0", - "dst_wire": "RIOI_OSIN10", - "is_directional": "1", - "src_wire": "RIOI_OSOUT11", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX47_1->IOI_OLOGIC0_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE1", - "is_directional": "1", - "src_wire": "IOI_IMUX5_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX45_1->IOI_OLOGIC0_D6": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D6", - "is_directional": "1", - "src_wire": "IOI_IMUX45_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_OCE", - "is_directional": "1", - "src_wire": "IOI_IMUX29_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP4_0->IOI_IMUX_RC1": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC1", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIVP", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC0_OQ->>RIOI_O0": { - "can_invert": "0", - "dst_wire": "RIOI_O0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OQ", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_I0->RIOI_IDELAY0_IDATAIN": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY0_IDATAIN", - "is_directional": "1", - "src_wire": "RIOI_I0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX15_1->IOI_OLOGIC0_T1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T1", - "is_directional": "1", - "src_wire": "IOI_IMUX15_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX7_1->IOI_OLOGIC0_T2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T2", - "is_directional": "1", - "src_wire": "IOI_IMUX7_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CLK1_0->IOI_IDELAY1_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX37_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_IBUF1->RIOI_I1": { - "can_invert": "0", - "dst_wire": "RIOI_I1", - "is_directional": "1", - "src_wire": "RIOI_IBUF1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR2", - "is_directional": "1", - "src_wire": "IOI_BYP4_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CTRL1_0->IOI_ILOGIC1_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q7", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP3_1->IOI_IMUX_RC3": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC3", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_1", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX26_1->IOI_IDELAY0_INC": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_INC", - "is_directional": "1", - "src_wire": "IOI_IMUX26_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC1_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN_TERM", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS1_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC1_D", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY0_DATAOUT", - "is_directional": "1", - "src_wire": "RIOI_IDELAY0_IDATAIN", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR0_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX40_1->IOI_OLOGIC0_D2": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D2", - "is_directional": "1", - "src_wire": "IOI_IMUX40_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC1_DDLY", - "is_directional": "1", - "src_wire": "RIOI_IDELAY1_DATAOUT", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC0_TQ->>RIOI_T0": { - "can_invert": "0", - "dst_wire": "RIOI_T0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TQ", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX44_1->IOI_OLOGIC0_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX34_1->IOI_OLOGIC0_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS23_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_LDPIPEEN", - "is_directional": "1", - "src_wire": "IOI_IMUX33_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", - "is_directional": "1", - "src_wire": "IOI_IMUX41_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE3_1", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_BITSLIP", - "is_directional": "1", - "src_wire": "IOI_IMUX0_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX13_1->IOI_OLOGIC0_T3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T3", - "is_directional": "1", - "src_wire": "IOI_IMUX13_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TQ", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_IMUX44_0->IOI_OLOGIC1_D3": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D3", - "is_directional": "1", - "src_wire": "IOI_IMUX44_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX21_1->IOI_OLOGIC0_T4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_T4", - "is_directional": "1", - "src_wire": "IOI_IMUX21_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CINVCTRL", - "is_directional": "1", - "src_wire": "IOI_BYP6_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CE2", - "is_directional": "1", - "src_wire": "IOI_IMUX14_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { - "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CE0", - "is_directional": "1", - "src_wire": "IOI_BYP3_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC0_TBYTEIN": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TBYTEIN", - "is_directional": "1", - "src_wire": "IOI_TBYTEIN_TERM", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS0_1", - "is_directional": "1", "src_wire": "IOI_ILOGIC0_Q1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_O", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY1_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", - "is_directional": "1", - "src_wire": "IOI_IMUX38_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP4_1->IOI_IMUX_RC2": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC2", - "is_directional": "1", - "src_wire": "IOI_BYP4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS19_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS8_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q8", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IMUX31_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CTRL0_1->IOI_OLOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL0_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX47_0->IOI_OLOGIC1_D8": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D8", - "is_directional": "1", - "src_wire": "IOI_IMUX47_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX30_1->IOI_IDELAY0_LD": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_LD", - "is_directional": "1", - "src_wire": "IOI_IMUX30_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CTRL1_1->IOI_ILOGIC0_SR": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_SR", - "is_directional": "1", - "src_wire": "IOI_CTRL1_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q6", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS11_1", - "is_directional": "1", - "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_OQ", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX42_1->IOI_OLOGIC0_D4": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_D4", - "is_directional": "1", - "src_wire": "IOI_IMUX42_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY2", - "is_directional": "1", - "src_wire": "IOI_BYP7_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_ICLK", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX34_0->IOI_OLOGIC1_D1": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D1", - "is_directional": "1", - "src_wire": "IOI_IMUX34_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX32_0->IOI_IDELAY1_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CE", - "is_directional": "1", - "src_wire": "IOI_IMUX32_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_OQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_D1", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", - "is_directional": "1", - "src_wire": "IOI_IMUX36_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC1_T1", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_CLK0_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CLK1_1->IOI_IDELAY0_C": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_C", - "is_directional": "1", - "src_wire": "IOI_CLK1_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX43_0->IOI_OLOGIC1_D5": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_D5", - "is_directional": "1", - "src_wire": "IOI_IMUX43_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IMUX22_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_IMUX8_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS18_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_O", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS10_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC0_TFB", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS14_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q5", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS5_1", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OSOUT21->RIOI_OSIN20": { - "can_invert": "0", - "dst_wire": "RIOI_OSIN20", "is_directional": "1", - "src_wire": "RIOI_OSOUT21", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_1" }, - "RIOI3_TBYTETERM.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "RIOI3_TBYTETERM.RIOI_IBUF0->RIOI_I0": { "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS9_0", + "src_wire": "RIOI_IBUF0", "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q3", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "RIOI_I0" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX32_1->IOI_IDELAY0_CE": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", - "src_wire": "IOI_IMUX32_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", + "src_wire": "IOI_IOCLK0", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK5", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "RIOI3_TBYTETERM.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", + "src_wire": "IOI_ILOGIC0_Q8", "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { - "can_invert": "0", - "dst_wire": "RIOI_IBUF_DISABLE0", - "is_directional": "1", - "src_wire": "IOI_IMUX9_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_TCE", - "is_directional": "1", - "src_wire": "IOI_IMUX1_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS2_0", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "is_directional": "1", - "src_wire": "IOI_IMUX10_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", - "is_directional": "1", - "src_wire": "IOI_IMUX35_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS3_0", - "is_directional": "1", - "src_wire": "IOI_ILOGIC1_Q6", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS7_1", - "is_directional": "1", - "src_wire": "IOI_ILOGIC0_Q7", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_PHASER_TO_IO_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": { - "can_invert": "0", - "dst_wire": "RIOI3_IDELAY0_IFDLY0", - "is_directional": "1", - "src_wire": "IOI_FAN4_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_TQ", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_T1", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC0_OFB", - "is_directional": "1", - "src_wire": "IOI_OLOGIC0_D1", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLK", - "is_directional": "1", - "src_wire": "IOI_IOCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_I1->RIOI_IDELAY1_IDATAIN": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY1_IDATAIN", - "is_directional": "1", - "src_wire": "RIOI_I1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_OCLKB", - "is_directional": "1", - "src_wire": "IOI_OCLKM_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_DATAIN", - "is_directional": "1", - "src_wire": "IOI_IMUX25_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS20_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_REGRST", - "is_directional": "1", - "src_wire": "IOI_IMUX12_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { - "can_invert": "0", - "dst_wire": "IOI_LOGIC_OUTS15_0", - "is_directional": "1", - "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", - "is_directional": "1", - "src_wire": "RIOI_OLOGIC1_TFB", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_O", - "is_directional": "1", - "src_wire": "RIOI_ILOGIC1_DDLY", - "is_pseudo": "1" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLK_0", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { - "can_invert": "0", - "dst_wire": "RIOI_OLOGIC1_CLKDIVF", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIVFB", - "is_directional": "1", - "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_1": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_1", - "is_directional": "1", - "src_wire": "IOI_IOCLK1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLK": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLK", - "is_directional": "1", - "src_wire": "IOI_OCLK_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLKM_0": { - "can_invert": "0", - "dst_wire": "IOI_OCLKM_0", - "is_directional": "1", - "src_wire": "IOI_IMUX31_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { - "can_invert": "0", - "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", - "is_directional": "1", - "src_wire": "IOI_IMUX39_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { - "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", - "src_wire": "IOI_RCLK_FORIO3", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_BYP3_0->IOI_IMUX_RC0": { - "can_invert": "0", - "dst_wire": "IOI_IMUX_RC0", - "is_directional": "1", - "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_1" }, "RIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLK", - "is_directional": "1", "src_wire": "IOI_IMUX20_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { - "can_invert": "0", - "dst_wire": "RIOI_IDELAY1_DATAOUT", "is_directional": "1", - "src_wire": "RIOI_IDELAY1_IDATAIN", - "is_pseudo": "1" + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_IMUX7_0->IOI_OLOGIC1_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T2" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS0_0" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_0" + }, + "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX7_1->IOI_OLOGIC0_T2": { + "can_invert": "0", + "src_wire": "IOI_IMUX7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T2" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX21_1->IOI_OLOGIC0_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T4" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CINVCTRL" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.RIOI_I0->RIOI_IDELAY0_IDATAIN": { + "can_invert": "0", + "src_wire": "RIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY0_IDATAIN" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS2_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX44_1->IOI_OLOGIC0_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D3" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL" + }, + "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM0" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC0_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "RIOI3_TBYTETERM.IOI_IMUX13_0->IOI_OLOGIC1_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T3" + }, + "RIOI3_TBYTETERM.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { + "can_invert": "0", + "src_wire": "IOI_IMUX6_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_DCI_T_TERM1" + }, + "RIOI3_TBYTETERM.IOI_IMUX32_0->IOI_IDELAY1_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CE" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_BYP3_0->IOI_IMUX_RC0": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" }, "RIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC0_CLKDIV", - "is_directional": "1", "src_wire": "IOI_IMUX8_1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.RIOI_I0->RIOI_ILOGIC0_D": { - "can_invert": "0", - "dst_wire": "RIOI_ILOGIC0_D", "is_directional": "1", - "src_wire": "RIOI_I0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE1" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_CLK1_0->IOI_IDELAY1_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_C" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX47_0->IOI_OLOGIC1_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D8" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_IMUX46_0->IOI_OLOGIC1_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D7" + }, + "RIOI3_TBYTETERM.IOI_CLK1_1->IOI_IDELAY0_C": { + "can_invert": "0", + "src_wire": "IOI_CLK1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_C" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR0_1" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_OFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_OFB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { + "can_invert": "0", + "src_wire": "IOI_BYP6_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CINVCTRL" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { + "can_invert": "0", + "src_wire": "IOI_IMUX9_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IBUF_DISABLE0" + }, + "RIOI3_TBYTETERM.IOI_IMUX40_0->IOI_OLOGIC1_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D2" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB" }, "RIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", - "dst_wire": "IOI_RCLK_DIV_CLR3", - "is_directional": "1", "src_wire": "IOI_BYP3_0", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", - "src_wire": "IOI_CLK0_0", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR3" }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "RIOI3_TBYTETERM.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", - "dst_wire": "IOI_OCLK_0", + "src_wire": "IOI_OLOGIC1_IOCLKGLITCH", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_0" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX47_1->IOI_OLOGIC0_D8": { + "can_invert": "0", + "src_wire": "IOI_IMUX47_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D8" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", "src_wire": "IOI_LEAF_GCLK4", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_IMUX26_1->IOI_IDELAY0_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_INC" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "RIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE3_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_0" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TCE" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { + "can_invert": "0", + "src_wire": "IOI_IMUX38_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "RIOI3_TBYTETERM.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "RIOI3_TBYTETERM.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", "src_wire": "IOI_LEAF_GCLK2", - "is_pseudo": "0" - }, - "RIOI3_TBYTETERM.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { - "can_invert": "0", - "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", - "src_wire": "IOI_IMUX37_1", - "is_pseudo": "0" + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY0_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY0_DATAOUT" + }, + "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_BITSLIP" + }, + "RIOI3_TBYTETERM.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "RIOI3_TBYTETERM.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY1_IDATAIN", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_IDELAY1_DATAOUT" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_IMUX30_1->IOI_IDELAY0_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LD" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS10_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_OFB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE2" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OQ" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_0" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB" + }, + "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE0" + }, + "RIOI3_TBYTETERM.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TCE" + }, + "RIOI3_TBYTETERM.IOI_CTRL1_1->IOI_ILOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_SR" + }, + "RIOI3_TBYTETERM.IOI_IMUX32_1->IOI_IDELAY0_CE": { + "can_invert": "0", + "src_wire": "IOI_IMUX32_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CE" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OQ" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_TFB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_CTRL0_1->IOI_OLOGIC0_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_SR" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_REGRST" + }, + "RIOI3_TBYTETERM.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { + "can_invert": "0", + "src_wire": "IOI_IMUX39_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "RIOI3_TBYTETERM.RIOI_IBUF1->RIOI_I1": { + "can_invert": "0", + "src_wire": "RIOI_IBUF1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_I1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS19_0" + }, + "RIOI3_TBYTETERM.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY1_IFDLY2" + }, + "RIOI3_TBYTETERM.IOI_IMUX21_0->IOI_OLOGIC1_T4": { + "can_invert": "0", + "src_wire": "IOI_IMUX21_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T4" + }, + "RIOI3_TBYTETERM.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "RIOI3_TBYTETERM.RIOI_I0->RIOI_ILOGIC0_D": { + "can_invert": "0", + "src_wire": "RIOI_I0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_D" + }, + "RIOI3_TBYTETERM.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB" + }, + "RIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_CTRL0_0->IOI_OLOGIC1_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_SR" + }, + "RIOI3_TBYTETERM.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TFB" + }, + "RIOI3_TBYTETERM.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_OCE" + }, + "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.RIOI_I1->RIOI_ILOGIC1_D": { + "can_invert": "0", + "src_wire": "RIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_D" + }, + "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLK" + }, + "RIOI3_TBYTETERM.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { + "can_invert": "0", + "src_wire": "IOI_IMUX41_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIVP" + }, + "RIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LDPIPEEN" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TFB", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL" + }, + "RIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR1_1" + }, + "RIOI3_TBYTETERM.IOI_BYP4_1->IOI_IMUX_RC2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC2" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": { + "can_invert": "0", + "src_wire": "IOI_BYP7_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY2" + }, + "RIOI3_TBYTETERM.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { + "can_invert": "0", + "src_wire": "IOI_IMUX38_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS11_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_OFB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX42_1->IOI_OLOGIC0_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D4" + }, + "RIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CLR2" }, "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", - "dst_wire": "IOI_OLOGIC1_CLKDIVFB", - "is_directional": "1", "src_wire": "IOI_RCLK_FORIO1", - "is_pseudo": "0" + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { + "can_invert": "0", + "src_wire": "IOI_IMUX29_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_OCE" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX45_0->IOI_OLOGIC1_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D6" + }, + "RIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q8", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS8_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { + "can_invert": "0", + "src_wire": "IOI_IMUX36_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY1_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_DDLY" + }, + "RIOI3_TBYTETERM.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC1_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC1_TQ" + }, + "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { + "can_invert": "0", + "src_wire": "IOI_IDELAY1_CNTVALUEOUT1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS1_0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TFB_LOCAL", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC1_TFB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB" + }, + "RIOI3_TBYTETERM.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_DATAIN" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_O1": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_O1" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_CLK0_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC0_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN_TERM", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_TBYTEIN" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { + "can_invert": "0", + "src_wire": "IOI_IMUX35_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CE1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE2_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX43_0->IOI_OLOGIC1_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D5" + }, + "RIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_IMUX42_0->IOI_OLOGIC1_D4": { + "can_invert": "0", + "src_wire": "IOI_IMUX42_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D4" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { + "can_invert": "0", + "src_wire": "IOI_IMUX5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE1" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_1" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX45_1->IOI_OLOGIC0_D6": { + "can_invert": "0", + "src_wire": "IOI_IMUX45_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D6" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { + "can_invert": "0", + "src_wire": "IOI_IMUX25_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_DATAIN" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q7", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS7_0" + }, + "RIOI3_TBYTETERM.IOI_BYP3_1->IOI_IMUX_RC3": { + "can_invert": "0", + "src_wire": "IOI_BYP3_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC3" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.RIOI_ISOUT10->RIOI_ISIN11": { + "can_invert": "0", + "src_wire": "RIOI_ISOUT10", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN11" + }, + "RIOI3_TBYTETERM.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX10_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.RIOI_I1->RIOI_IDELAY1_IDATAIN": { + "can_invert": "0", + "src_wire": "RIOI_I1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_IDELAY1_IDATAIN" + }, + "RIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_BYP4_0->IOI_IMUX_RC1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IMUX_RC1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_IMUX31_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS23_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX37_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q6", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS3_0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_TBYTEIN_TERM->>IOI_OLOGIC1_TBYTEIN": { + "can_invert": "0", + "src_wire": "IOI_TBYTEIN_TERM", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_TBYTEIN" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.RIOI_OSOUT11->RIOI_OSIN10": { + "can_invert": "0", + "src_wire": "RIOI_OSOUT11", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN10" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS20_1" + }, + "RIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_IMUX44_0->IOI_OLOGIC1_D3": { + "can_invert": "0", + "src_wire": "IOI_IMUX44_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D3" + }, + "RIOI3_TBYTETERM.RIOI_ISOUT20->RIOI_ISIN21": { + "can_invert": "0", + "src_wire": "RIOI_ISOUT20", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ISIN21" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC0_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC0_O" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_ICLKDIV", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC0_OQ->>RIOI_O0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_OQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_O0" + }, + "RIOI3_TBYTETERM.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_OCLKB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { + "can_invert": "0", + "src_wire": "IOI_IMUX14_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CE2" + }, + "RIOI3_TBYTETERM.IOI_IMUX34_0->IOI_OLOGIC1_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_D1" + }, + "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX40_1->IOI_OLOGIC0_D2": { + "can_invert": "0", + "src_wire": "IOI_IMUX40_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D2" + }, + "RIOI3_TBYTETERM.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": { + "can_invert": "0", + "src_wire": "IOI_FAN4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY1_IFDLY0" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX15_1->IOI_OLOGIC0_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T1" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC0_TQ->>RIOI_T0": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_T0" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_IMUX46_1->IOI_OLOGIC0_D7": { + "can_invert": "0", + "src_wire": "IOI_IMUX46_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D7" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY0_IFDLY1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { + "can_invert": "0", + "src_wire": "IOI_IMUX33_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_LDPIPEEN" + }, + "RIOI3_TBYTETERM.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLKM_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_OCLKB" + }, + "RIOI3_TBYTETERM.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC1_DDLY", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVB" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_T1": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC1_TQ", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_T1" + }, + "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX20_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { + "can_invert": "0", + "src_wire": "IOI_OCLK_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKB" + }, + "RIOI3_TBYTETERM.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": { + "can_invert": "0", + "src_wire": "IOI_FAN5_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI3_IDELAY1_IFDLY1" + }, + "RIOI3_TBYTETERM.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { + "can_invert": "0", + "src_wire": "IOI_IMUX4_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLK" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_IMUX34_1->IOI_OLOGIC0_D1": { + "can_invert": "0", + "src_wire": "IOI_IMUX34_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D1" + }, + "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { + "can_invert": "0", + "src_wire": "IOI_IDELAY0_CNTVALUEOUT3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS15_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { + "can_invert": "0", + "src_wire": "IOI_BYP4_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_RCLK_DIV_CE1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { + "can_invert": "0", + "src_wire": "IOI_CLK0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKDIVP" + }, + "RIOI3_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_D1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_OFB" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { + "can_invert": "0", + "src_wire": "RIOI_OLOGIC0_TQ", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TFB" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_Q5", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS14_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK4", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK2", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { + "can_invert": "0", + "src_wire": "RIOI_IDELAY0_DATAOUT", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_ILOGIC0_DDLY" + }, + "RIOI3_TBYTETERM.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { + "can_invert": "0", + "src_wire": "IOI_IMUX0_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_BITSLIP" + }, + "RIOI3_TBYTETERM.IOI_CTRL1_0->IOI_ILOGIC1_SR": { + "can_invert": "0", + "src_wire": "IOI_CTRL1_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_SR" + }, + "RIOI3_TBYTETERM.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { + "can_invert": "0", + "src_wire": "IOI_IMUX12_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY0_REGRST" + }, + "RIOI3_TBYTETERM.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_T1", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "RIOI_OLOGIC0_TQ" + }, + "RIOI3_TBYTETERM.IOI_IMUX26_0->IOI_IDELAY1_INC": { + "can_invert": "0", + "src_wire": "IOI_IMUX26_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_INC" + }, + "RIOI3_TBYTETERM.IOI_IMUX43_1->IOI_OLOGIC0_D5": { + "can_invert": "0", + "src_wire": "IOI_IMUX43_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_D5" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_CLKDIVB" + }, + "RIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_IMUX22_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { + "can_invert": "0", + "src_wire": "IOI_OLOGIC0_IOCLKGLITCH", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS5_1" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_0" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC1_Q3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS9_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX13_1->IOI_OLOGIC0_T3": { + "can_invert": "0", + "src_wire": "IOI_IMUX13_1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC0_T3" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC1_CLKB" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>RIOI_OLOGIC1_CLKDIVF": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "RIOI3_TBYTETERM.IOI_IMUX30_0->IOI_IDELAY1_LD": { + "can_invert": "0", + "src_wire": "IOI_IMUX30_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_IDELAY1_LD" + }, + "RIOI3_TBYTETERM.IOI_IMUX15_0->IOI_OLOGIC1_T1": { + "can_invert": "0", + "src_wire": "IOI_IMUX15_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_T1" + }, + "RIOI3_TBYTETERM.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { + "can_invert": "0", + "src_wire": "RIOI_ILOGIC1_D", + "is_directional": "1", + "is_pseudo": "1", + "dst_wire": "IOI_ILOGIC1_O" + }, + "RIOI3_TBYTETERM.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { + "can_invert": "0", + "src_wire": "IOI_RCLK_FORIO1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIV" + }, + "RIOI3_TBYTETERM.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { + "can_invert": "0", + "src_wire": "IOI_ILOGIC0_O", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_LOGIC_OUTS18_1" + }, + "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_ILOGIC0_CLK" + }, + "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_0": { + "can_invert": "0", + "src_wire": "IOI_IOCLK1", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_0" + }, + "RIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { + "can_invert": "0", + "src_wire": "IOI_IMUX8_0", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_1": { + "can_invert": "0", + "src_wire": "IOI_IOCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLK_1" + }, + "RIOI3_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { + "can_invert": "0", + "src_wire": "IOI_LEAF_GCLK3", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "IOI_OCLKM_1" + }, + "RIOI3_TBYTETERM.RIOI_OSOUT21->RIOI_OSIN20": { + "can_invert": "0", + "src_wire": "RIOI_OSOUT21", + "is_directional": "1", + "is_pseudo": "0", + "dst_wire": "RIOI_OSIN20" } }, - "tile_type": "RIOI3_TBYTETERM" + "wires": [ + "IOI_BYP5_1", + "IOI_IMUX26_1", + "IOI_NW4END3_1", + "IOI_ILOGIC1_REV", + "IOI_IMUX42_0", + "RIOI_I1", + "IOI_EE4A1_1", + "IOI_IMUX22_1", + "IOI_ILOGIC0_CE2", + "RIOI_ILOGIC1_D", + "IOI_IMUX5_0", + "IOI_PHASER_TO_IO_OCLK1X_90_0", + "IOI_OLOGIC1_CLKB", + "IOI_WW4C1_1", + "IOI_ER1BEG0_1", + "IOI_IMUX23_0", + "IOI_RCLK_DIV_CLR0_1", + "IOI_OLOGIC1_T1", + "IOI_IOCLK3", + "RIOI_OLOGIC0_TFB", + "IOI_ODELAY0_CNTVALUEOUT0", + "IOI_RCLK_DIV_CE2_1", + "IOI_DCI_TSTRST", + "IOI_OLOGIC1_REV", + "IOI_WW4END1_0", + "IOI_CTRL0_1", + "IOI_MONITOR_N", + "IOI_ILOGIC1_Q7", + "IOI_IMUX38_0", + "IOI_WW4B1_1", + "IOI_EE4C1_1", + "IOI_IOCLK2", + "IOI_OLOGIC1_D8", + "IOI_LEAF_GCLK4", + "IOI_WW2END2_1", + "IOI_BYP2_0", + "IOI_ILOGIC1_Q1", + "IOI_IMUX36_1", + "IOI_LEAF_GCLK3", + "IOI_SW2A0_1", + "IOI_IMUX16_1", + "IOI_FAN2_1", + "IOI_IMUX27_0", + "IOI_IMUX22_0", + "IOI_EL1BEG2_1", + "IOI_NW4A1_0", + "IOI_BLOCK_OUTS0_1", + "IOI_SE2A1_0", + "IOI_IMUX4_1", + "IOI_EL1BEG2_0", + "IOI_WW4B0_1", + "IOI_NE4BEG3_1", + "IOI_SW4A3_1", + "IOI_SW4A1_0", + "IOI_ODELAY0_LDPIPEEN", + "IOI_IDELAY0_CNTVALUEIN3", + "IOI_EE4B3_1", + "IOI_NE4C0_1", + "IOI_IDELAY0_CNTVALUEOUT1", + "IOI_IDELAYCTRL_OUTN65", + "IOI_BYP4_1", + "IOI_EE2BEG1_0", + "IOI_LOGIC_OUTS20_0", + "IOI_SE4C3_1", + "IOI_WL1END2_0", + "IOI_CTRL1_1", + "RIOI_ISOUT21", + "IOI_FAN5_0", + "IOI_EE2A2_0", + "IOI_WW4END2_1", + "IOI_WW4C0_0", + "IOI_IDELAY1_REGRST", + "IOI_PHASER_TO_IO_OCLK", + "IOI_SW4A0_1", + "IOI_IDELAY1_CNTVALUEIN0", + "RIOI_OLOGIC1_OFB", + "IOI_OLOGIC0_CLKDIV", + "IOI_IMUX17_0", + "IOI_WW2END2_0", + "IOI_FAN3_0", + "IOI_LOGIC_OUTS14_0", + "IOI_DCI_TSTCLK", + "IOI_FAN0_0", + "IOI_ODELAY1_CINVCTRL", + "IOI_SE4BEG0_0", + "IOI_IMUX20_1", + "IOI_EE2BEG3_0", + "IOI_LH7_0", + "IOI_IMUX15_1", + "IOI_ILOGIC0_Q3", + "IOI_EE4A1_0", + "IOI_ILOGIC1_Q8", + "IOI_IDELAY1_C", + "IOI_BYP7_0", + "IOI_IMUX25_0", + "IOI_IDELAY0_REGRST", + "IOI_BYP3_1", + "IOI_NE2A0_1", + "IOI_IMUX11_1", + "IOI_SE4BEG0_1", + "IOI_ILOGIC0_OCLKB", + "RIOI_OLOGIC1_TFB_LOCAL", + "IOI_IMUX47_0", + "IOI_OLOGIC0_D4", + "IOI_SE2A0_0", + "IOI_SE4BEG1_1", + "IOI_IDELAY1_CINVCTRL", + "IOI_IDELAY0_CNTVALUEIN4", + "IOI_SW4END3_0", + "IOI_EE4BEG3_0", + "IOI_ILOGIC0_Q7", + "IOI_ILOGIC1_CLKB", + "IOI_LOGIC_OUTS19_1", + "IOI_EL1BEG1_1", + "IOI_OLOGIC0_D3", + "IOI_EE4C0_0", + "IOI_TBYTEIN_TERM", + "RIOI_KEEPER_INT_EN_1", + "IOI_OLOGIC0_TCE", + "IOI_WW2A0_0", + "IOI_ODELAY0_CLKIN", + "IOI_DCI_TSTHLN", + "IOI_IMUX15_0", + "IOI_WW2END1_1", + "IOI_NE4C3_1", + "IOI_ILOGIC0_O", + "IOI_RCLK_DIV_CE3", + "IOI_BLOCK_OUTS0_0", + "IOI_SE4C3_0", + "IOI_ILOGIC1_CLKDIV", + "IOI_BYP0_1", + "IOI_IMUX32_0", + "IOI_OLOGIC1_D5", + "IOI_LH4_0", + "IOI_RCLK_DIV_CLR1", + "IOI_IMUX10_0", + "IOI_NW2A0_1", + "IOI_ILOGIC0_REV", + "RIOI_ISIN20", + "IOI_ODELAY0_CNTVALUEIN4", + "IOI_LOGIC_OUTS1_1", + "IOI_OLOGIC0_T1", + "IOI_EE4BEG1_0", + "RIOI_ISIN11", + "RIOI_OLOGIC0_TFB_LOCAL", + "IOI_IMUX41_0", + "IOI_WW4C3_0", + "IOI_LOGIC_OUTS23_0", + "IOI_RCLK_DIV_CE0", + "RIOI_ODELAY1_OFDLY2", + "IOI_SW2A3_1", + "IOI_EE4B3_0", + "IOI_IOCLK0", + "IOI_EE4BEG0_0", + "IOI_ODELAY0_INC", + "IOI_IMUX6_0", + "IOI_IMUX40_0", + "IOI_IMUX10_1", + "IOI_WR1END3_0", + "RIOI_ILOGIC0_DDLY", + "IOI_IMUX37_1", + "IOI_OLOGIC0_REV", + "IOI_OLOGIC0_D1", + "IOI_IOCLK1", + "IOI_RCLK_FORIO1", + "IOI_ODELAY1_LD", + "IOI_PHASER_TO_IO_OCLK1X_90", + "IOI_WW4A1_1", + "IOI_NE4C0_0", + "IOI_NW4A2_1", + "IOI_LOGIC_OUTS6_1", + "IOI_LH3_1", + "IOI_IMUX33_0", + "IOI_IMUX13_0", + "IOI_IMUX9_0", + "IOI_EE4BEG0_1", + "IOI_WW2A2_1", + "IOI_WR1END0_1", + "IOI_OLOGIC0_T3", + "IOI_EE4A2_0", + "IOI_IMUX26_0", + "IOI_IMUX0_0", + "IOI_ILOGIC0_Q5", + "IOI_IMUX3_0", + "IOI_EE4B2_0", + "RIOI_IBUF_DISABLE0", + "IOI_SW2A2_1", + "IOI_OLOGIC0_OCE", + "IOI_ILOGIC0_CE1", + "IOI_LOGIC_OUTS8_0", + "IOI_SE2A2_1", + "IOI_WW2END0_0", + "IOI_SW2A1_0", + "RIOI_OSOUT10", + "IOI_RCLK_FORIO2", + "RIOI_OLOGIC1_TQ", + "IOI_LH3_0", + "IOI_EE4B1_0", + "IOI_SW4END1_0", + "IOI_WW4A2_0", + "IOI_ER1BEG3_0", + "IOI_LH6_0", + "IOI_IMUX46_1", + "IOI_ILOGIC0_CLK", + "IOI_SW2A2_0", + "IOI_IMUX40_1", + "IOI_LOGIC_OUTS11_1", + "IOI_IMUX2_0", + "IOI_ODELAY0_CNTVALUEIN1", + "IOI_IDELAY1_CNTVALUEIN4", + "IOI_BYP1_1", + "IOI_SW4END1_1", + "RIOI_I2GCLK_BOT1", + "RIOI3_IDELAY0_IFDLY2", + "IOI_IDELAY0_CNTVALUEIN2", + "IOI_IDELAYCTRL_RDY", + "IOI_ODELAY1_CNTVALUEOUT0", + "IOI_IMUX44_0", + "IOI_NW2A2_0", + "IOI_OLOGIC1_D4", + "IOI_SW4A1_1", + "IOI_LOGIC_OUTS22_1", + "IOI_RCLK_DIV_CE3_1", + "IOI_OLOGIC0_D6", + "IOI_IDELAY0_CINVCTRL", + "IOI_IMUX25_1", + "IOI_WW4END1_1", + "IOI_WW4END0_1", + "IOI_SE4BEG2_0", + "IOI_LOGIC_OUTS16_0", + "IOI_NW4END3_0", + "IOI_NE4BEG2_0", + "IOI_DCI_DCIDONE", + "IOI_OLOGIC1_TBYTEIN", + "IOI_ILOGIC0_CLKDIVP", + "IOI_IMUX13_1", + "IOI_LOGIC_OUTS7_0", + "IOI_IMUX_RC1", + "IOI_CLK0_1", + "IOI_NE2A3_1", + "IOI_DCI_TSTRST0", + "IOI_IDELAY0_CNTVALUEOUT4", + "IOI_LEAF_GCLK2", + "IOI_IDELAY0_CNTVALUEOUT2", + "IOI_IDELAY1_INC", + "IOI_OLOGIC1_OCE", + "IOI_LOGIC_OUTS13_0", + "IOI_CLK1_1", + "RIOI_T1", + "RIOI_ISOUT11", + "IOI_NE4C2_1", + "IOI_WW4B0_0", + "IOI_ODELAY1_CNTVALUEIN0", + "IOI_WL1END3_1", + "IOI_IMUX28_0", + "IOI_NW4END1_0", + "IOI_OLOGIC1_D7", + "IOI_LOGIC_OUTS11_0", + "IOI_IDELAY0_CNTVALUEIN0", + "RIOI_IDELAY1_IDATAIN", + "IOI_IMUX18_1", + "IOI_WW4A0_1", + "RIOI_I0", + "IOI_OLOGIC0_D8", + "IOI_IMUX38_1", + "IOI_IMUX21_0", + "IOI_EE2BEG1_1", + "IOI_EE4B0_0", + "IOI_FAN4_0", + "IOI_IDELAYCTRL_RST", + "IOI_SW4A2_0", + "IOI_NW2A0_0", + "IOI_OCLKM_0", + "IOI_EE2BEG0_1", + "IOI_LOGIC_OUTS14_1", + "IOI_ODELAY0_CNTVALUEOUT4", + "IOI_ODELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_0", + "IOI_ILOGIC1_OCLK", + "RIOI_DIFF_TERM_INT_EN", + "IOI_IMUX17_1", + "IOI_ILOGIC0_DYNCLKDIVPSEL", + "IOI_ODELAY1_CNTVALUEOUT3", + "IOI_SW4END3_1", + "IOI_ODELAY1_CLKIN", + "IOI_NE2A1_0", + "IOI_EE4A2_1", + "IOI_OCLKM_1", + "RIOI_OLOGIC1_CLKDIVF", + "IOI_IMUX43_0", + "IOI_LH8_1", + "IOI_RCLK_DIV_CE1", + "IOI_LOGIC_OUTS17_0", + "IOI_SE2A3_0", + "IOI_ILOGIC1_Q6", + "IOI_PHASER_TO_IO_ICLKDIV", + "IOI_LH9_0", + "IOI_OLOGIC0_D2", + "IOI_OLOGIC0_CLKDIVB", + "RIOI_ILOGIC0_D", + "IOI_IMUX30_1", + "IOI_ODELAY0_CNTVALUEOUT1", + "IOI_LOGIC_OUTS0_0", + "IOI_WW2A1_0", + "IOI_BYP7_1", + "RIOI_ODELAY0_DATAOUT", + "RIOI_ODELAY0_ODATAIN", + "IOI_SE4C1_0", + "IOI_IMUX39_1", + "IOI_OCLK_1", + "IOI_EL1BEG0_1", + "IOI_ILOGIC0_Q4", + "IOI_IMUX45_1", + "IOI_IMUX20_0", + "RIOI_ODELAY0_OFDLY0", + "IOI_ODELAY1_REGRST", + "IOI_OLOGIC0_D5", + "IOI_ODELAY1_INC", + "IOI_ODELAY1_CNTVALUEIN3", + "RIOI_OLOGIC0_CLKDIVF", + "IOI_WW2A0_1", + "IOI_NW2A1_0", + "IOI_WW2A2_0", + "IOI_EE2BEG3_1", + "IOI_ILOGIC0_Q8", + "IOI_IMUX24_0", + "IOI_OLOGIC0_T2", + "IOI_IDELAY0_LD", + "IOI_FAN5_1", + "IOI_OLOGIC1_T2", + "IOI_LOGIC_OUTS3_1", + "RIOI_ISOUT20", + "IOI_FAN3_1", + "IOI_BYP0_0", + "IOI_IMUX35_1", + "IOI_ILOGIC1_OCLKB", + "IOI_IMUX27_1", + "IOI_WW4END3_1", + "IOI_BLOCK_OUTS2_1", + "RIOI_O1", + "IOI_EE2BEG2_0", + "IOI_NE2A3_0", + "IOI_SE2A1_1", + "IOI_NE4BEG3_0", + "IOI_PHASER_TO_IO_OCLKDIV", + "IOI_LH12_0", + "RIOI3_IDELAY0_IFDLY1", + "IOI_LH2_1", + "IOI_ER1BEG3_1", + "IOI_LH1_1", + "IOI_ILOGIC1_CE2", + "IOI_IDELAYCTRL_UPPULSEOUT", + "IOI_FAN4_1", + "IOI_IDELAY0_CE", + "IOI_EE4C2_1", + "IOI_OLOGIC0_CLK", + "IOI_LOGIC_OUTS12_1", + "RIOI_ISIN21", + "IOI_SW2A3_0", + "IOI_ILOGIC1_DYNCLKSEL", + "IOI_ODELAY1_CNTVALUEIN2", + "RIOI_ILOGIC1_TFB", + "IOI_SW2A1_1", + "IOI_LH1_0", + "IOI_FAN1_1", + "IOI_LOGIC_OUTS10_1", + "RIOI_OSIN21", + "IOI_LOGIC_OUTS22_0", + "IOI_IMUX34_1", + "IOI_WW4A1_0", + "IOI_FAN7_0", + "IOI_IDELAY1_CNTVALUEIN1", + "IOI_LOGIC_OUTS21_1", + "IOI_ODELAY0_CNTVALUEOUT3", + "IOI_OCLK_0", + "IOI_ODELAY0_REGRST", + "IOI_LOGIC_OUTS15_0", + "IOI_LEAF_GCLK0", + "IOI_EE2A0_1", + "IOI_IMUX12_1", + "IOI_ILOGIC1_DYNCLKDIVSEL", + "IOI_IMUX23_1", + "IOI_ODELAY0_CNTVALUEIN2", + "RIOI_ODELAY1_OFDLY1", + "IOI_LOGIC_OUTS15_1", + "IOI_ILOGIC0_DYNCLKDIVSEL", + "IOI_EL1BEG3_0", + "IOI_ILOGIC0_BITSLIP", + "IOI_IDELAYCTRL_DNPULSEOUT", + "IOI_IMUX39_0", + "IOI_WR1END0_0", + "IOI_ODELAY1_CNTVALUEIN4", + "IOI_IMUX19_0", + "IOI_RCLK_FORIO3", + "IOI_BYP1_0", + "IOI_ILOGIC0_Q2", + "RIOI_KEEPER_INT_EN_0", + "IOI_OLOGIC0_IOCLKGLITCH", + "IOI_NW2A3_1", + "IOI_IDELAY0_C", + "RIOI_IDELAY1_DATAOUT", + "IOI_NW2A2_1", + "IOI_SW4END2_0", + "IOI_SW4END0_0", + "IOI_IMUX32_1", + "RIOI_IDELAY0_DATAOUT", + "IOI_IMUX19_1", + "RIOI_OLOGIC0_OFB", + "IOI_SW2A0_0", + "IOI_IMUX46_0", + "IOI_WR1END1_0", + "RIOI3_IDELAY0_IFDLY0", + "IOI_LOGIC_OUTS19_0", + "IOI_LOGIC_OUTS1_0", + "IOI_IMUX8_0", + "IOI_WW4C2_1", + "IOI_WW4C3_1", + "IOI_WW2END3_1", + "RIOI_DCI_T_TERM1", + "IOI_LH5_1", + "IOI_ODELAY1_CE", + "IOI_ILOGIC1_CLKDIVP", + "IOI_OLOGIC0_T4", + "IOI_NE4C2_0", + "IOI_IMUX31_1", + "IOI_NE4C3_0", + "IOI_NW4END2_1", + "IOI_IMUX7_1", + "IOI_IDELAY1_LD", + "IOI_LOGIC_OUTS23_1", + "IOI_ODELAY0_CNTVALUEIN3", + "IOI_LOGIC_OUTS9_0", + "IOI_EE2A0_0", + "IOI_OLOGIC1_TBYTEOUT", + "IOI_WW4A3_1", + "IOI_IMUX9_1", + "IOI_NW2A1_1", + "IOI_IMUX1_0", + "IOI_EE4C2_0", + "IOI_LOGIC_OUTS9_1", + "IOI_IMUX42_1", + "IOI_RCLK_DIV_CLR3", + "IOI_IMUX21_1", + "IOI_EE2BEG0_0", + "IOI_IMUX1_1", + "RIOI_PU_INT_EN_1", + "IOI_OLOGIC1_T4", + "IOI_LH7_1", + "IOI_LOGIC_OUTS0_1", + "IOI_ILOGIC1_O", + "IOI_OLOGIC0_TBYTEOUT", + "IOI_LOGIC_OUTS2_0", + "IOI_FAN0_1", + "IOI_IDELAY0_CNTVALUEOUT3", + "IOI_ILOGIC0_OCLK", + "IOI_IMUX30_0", + "IOI_SE4C1_1", + "IOI_NE4BEG0_0", + "IOI_OLOGIC1_CLKDIV", + "IOI_LOGIC_OUTS4_1", + "IOI_WL1END2_1", + "IOI_LEAF_GCLK5", + "RIOI3_IDELAY1_IFDLY0", + "IOI_IMUX43_1", + "IOI_EE2BEG2_1", + "RIOI_ILOGIC0_OFB", + "IOI_NW4A2_0", + "IOI_ER1BEG1_1", + "IOI_NW4END0_0", + "IOI_BYP5_0", + "RIOI_OLOGIC1_OQ", + "IOI_ILOGIC1_Q3", + "IOI_LH4_1", + "IOI_IMUX37_0", + "RIOI_DCI_T_TERM0", + "IOI_IDELAY1_DATAIN", + "IOI_IMUX_RC3", + "IOI_ILOGIC0_CLKB", + "IOI_OLOGIC0_CLKDIVFB", + "IOI_IDELAY1_CNTVALUEIN3", + "RIOI_OSIN10", + "IOI_IDELAY1_CNTVALUEIN2", + "IOI_IMUX16_0", + "IOI_SW4A2_1", + "RIOI_OSOUT11", + "RIOI_T0", + "IOI_WW4END0_0", + "IOI_BLOCK_OUTS2_0", + "IOI_EE4BEG2_1", + "IOI_NW2A3_0", + "IOI_IMUX_RC0", + "IOI_ODELAY0_CNTVALUEOUT2", + "IOI_WR1END3_1", + "IOI_NW4END1_1", + "IOI_SE2A2_0", + "IOI_ILOGIC0_Q6", + "IOI_NW4A3_1", + "IOI_EE4B2_1", + "IOI_SE4BEG3_0", + "IOI_EE4C1_0", + "IOI_IDELAY1_CNTVALUEOUT0", + "IOI_IMUX36_0", + "IOI_LOGIC_OUTS5_0", + "IOI_LH8_0", + "IOI_IMUX12_0", + "IOI_EE4C3_0", + "IOI_ODELAY1_CNTVALUEOUT2", + "IOI_SW4END0_1", + "IOI_IDELAY0_CNTVALUEIN1", + "IOI_OLOGIC1_CLKDIVFB", + "RIOI_I2GCLK_TOP0", + "IOI_IMUX0_1", + "RIOI_OSIN11", + "IOI_CLK1_0", + "IOI_IDELAY1_CNTVALUEOUT1", + "IOI_OLOGIC0_D7", + "IOI_BLOCK_OUTS3_1", + "IOI_IDELAY1_CNTVALUEOUT3", + "IOI_WW4END3_0", + "IOI_ILOGIC0_CLKDIV", + "IOI_OLOGIC1_D6", + "IOI_IMUX29_0", + "IOI_LOGIC_OUTS18_0", + "IOI_WL1END1_0", + "IOI_LH6_1", + "IOI_EL1BEG0_0", + "IOI_ILOGIC1_Q2", + "IOI_PHASER_TO_IO_OCLK_0", + "IOI_PHASER_TO_IO_ICLK_0", + "IOI_LEAF_GCLK1", + "IOI_EE2A1_0", + "IOI_WW4B1_0", + "IOI_DCI_TSTHLP", + "IOI_EE4A0_0", + "IOI_BYP3_0", + "IOI_FAN6_0", + "IOI_LOGIC_OUTS10_0", + "IOI_SE4BEG2_1", + "RIOI_OLOGIC1_TFB", + "IOI_IMUX29_1", + "RIOI_OSIN20", + "IOI_IDELAY0_LDPIPEEN", + "IOI_ILOGIC0_SR", + "IOI_WW4A0_0", + "IOI_NE4BEG2_1", + "IOI_IDELAY1_CE", + "IOI_WL1END0_0", + "IOI_IDELAY1_LDPIPEEN", + "IOI_IDELAY0_INC", + "IOI_SE4C0_1", + "IOI_OLOGIC1_T3", + "IOI_LH10_0", + "RIOI_ODELAY1_DATAOUT", + "IOI_EE4A3_0", + "IOI_ILOGIC1_CE1", + "IOI_FAN7_1", + "IOI_WW4B3_0", + "IOI_WL1END0_1", + "IOI_IMUX45_0", + "IOI_ODELAY1_C", + "IOI_LH12_1", + "IOI_WW2END3_0", + "IOI_WR1END2_0", + "IOI_IMUX11_0", + "IOI_IDELAY1_CNTVALUEOUT2", + "IOI_ILOGIC1_DYNCLKDIVPSEL", + "IOI_NE2A0_0", + "RIOI_ODELAY0_OFDLY2", + "IOI_NW4END0_1", + "IOI_WW4A2_1", + "IOI_EL1BEG3_1", + "RIOI_ISOUT10", + "IOI_EE2A3_1", + "IOI_IDELAY1_CNTVALUEOUT4", + "IOI_WR1END2_1", + "RIOI_ILOGIC0_TFB", + "IOI_ODELAY0_LD", + "RIOI_ODELAY1_ODATAIN", + "IOI_MONITOR_P", + "IOI_EE4BEG3_1", + "IOI_WW2END0_1", + "IOI_OLOGIC0_CLKB", + "IOI_RCLK_DIV_CE2", + "IOI_OLOGIC1_D2", + "IOI_LH11_1", + "IOI_IMUX34_0", + "RIOI_IBUF0", + "IOI_LH9_1", + "IOI_BYP6_0", + "IOI_ILOGIC1_BITSLIP", + "RIOI_OSOUT21", + "IOI_SE4BEG3_1", + "IOI_WW4B2_1", + "IOI_ODELAY1_CNTVALUEOUT4", + "IOI_IMUX14_0", + "IOI_LOGIC_OUTS12_0", + "IOI_NW4A3_0", + "IOI_SE4C0_0", + "IOI_NE2A1_1", + "IOI_LOGIC_OUTS20_1", + "IOI_SW4A3_0", + "IOI_SE4C2_1", + "IOI_ODELAY0_CINVCTRL", + "IOI_BLOCK_OUTS1_1", + "IOI_EE4A0_1", + "IOI_WL1END3_0", + "IOI_WW2A3_0", + "IOI_CLK0_0", + "IOI_NE4BEG1_0", + "IOI_OLOGIC1_TCE", + "IOI_OLOGIC1_D3", + "IOI_LOGIC_OUTS6_0", + "IOI_IMUX2_1", + "IOI_ODELAY1_CNTVALUEOUT1", + "RIOI_O0", + "IOI_IMUX44_1", + "IOI_IDELAYCTRL_OUTN1", + "IOI_EE4A3_1", + "IOI_PHASER_TO_IO_ICLKDIV_0", + "IOI_IMUX5_1", + "IOI_EE2A1_1", + "IOI_WW4B3_1", + "IOI_ILOGIC1_Q4", + "IOI_WW2A1_1", + "IOI_INT_DCI_EN", + "IOI_IMUX47_1", + "IOI_IMUX3_1", + "IOI_IMUX6_1", + "RIOI_PD_INT_EN_0", + "IOI_NE2A2_0", + "IOI_WW4B2_0", + "IOI_FAN6_1", + "IOI_BLOCK_OUTS3_0", + "IOI_IDELAY0_DATAIN", + "IOI_EE4B0_1", + "IOI_LOGIC_OUTS13_1", + "IOI_OLOGIC0_TBYTEIN", + "IOI_LH11_0", + "IOI_LH10_1", + "IOI_NW4A0_0", + "RIOI_ODELAY0_OFDLY1", + "IOI_BYP2_1", + "IOI_LOGIC_OUTS5_1", + "IOI_NW4END2_0", + "IOI_WW4C1_0", + "IOI_ILOGIC0_DYNCLKSEL", + "IOI_WR1END1_1", + "RIOI3_IDELAY1_IFDLY2", + "RIOI_OLOGIC0_TQ", + "IOI_LOGIC_OUTS16_1", + "IOI_LOGIC_OUTS18_1", + "IOI_OLOGIC1_CLK", + "IOI_OLOGIC1_IOCLKGLITCH", + "IOI_IMUX7_0", + "IOI_FAN1_0", + "IOI_IMUX41_1", + "IOI_WW2A3_1", + "IOI_SE2A3_1", + "RIOI_PU_INT_EN_0", + "IOI_LOGIC_OUTS2_1", + "IOI_CTRL1_0", + "IOI_RCLK_FORIO0", + "IOI_IMUX8_1", + "IOI_SW4A0_0", + "IOI_BLOCK_OUTS1_0", + "RIOI_IBUF_DISABLE1", + "IOI_WW4A3_0", + "IOI_ER1BEG0_0", + "IOI_PHASER_TO_IO_ICLK", + "IOI_RCLK_DIV_CLR1_1", + "IOI_RCLK_DIV_CLR2", + "IOI_NW4A1_1", + "IOI_EL1BEG1_0", + "IOI_FAN2_0", + "IOI_CTRL0_0", + "IOI_ILOGIC1_Q5", + "IOI_SE4BEG1_0", + "IOI_OLOGIC0_SR", + "RIOI_PD_INT_EN_1", + "IOI_ODELAY1_LDPIPEEN", + "IOI_LH2_0", + "IOI_EE4C3_1", + "IOI_ODELAY0_CE", + "IOI_EE2A3_0", + "IOI_OLOGIC1_D1", + "IOI_NW4A0_1", + "IOI_LOGIC_OUTS3_0", + "IOI_EE4C0_1", + "IOI_ILOGIC1_CLK", + "RIOI_OSOUT20", + "IOI_WW4C2_0", + "IOI_SW4END2_1", + "RIOI_ILOGIC1_DDLY", + "IOI_IMUX33_1", + "IOI_WW2END1_0", + "IOI_SE2A0_1", + "IOI_LOGIC_OUTS8_1", + "RIOI_IDELAY0_IDATAIN", + "IOI_LH5_0", + "RIOI3_IDELAY1_IFDLY1", + "IOI_IDELAY0_CNTVALUEOUT0", + "IOI_PHASER_TO_IO_OCLKDIV_0", + "IOI_ILOGIC0_Q1", + "IOI_OLOGIC1_CLKDIVB", + "IOI_NE4C1_1", + "IOI_NE4BEG0_1", + "IOI_OLOGIC1_SR", + "IOI_EE4B1_1", + "RIOI_ODELAY1_OFDLY0", + "IOI_IMUX14_1", + "IOI_ODELAY0_C", + "IOI_IMUX35_0", + "IOI_RCLK_DIV_CLR0", + "IOI_ILOGIC1_SR", + "IOI_NE4BEG1_1", + "IOI_BYP6_1", + "RIOI_OLOGIC0_OQ", + "IOI_ER1BEG2_1", + "IOI_IMUX4_0", + "IOI_EE4BEG2_0", + "IOI_LOGIC_OUTS4_0", + "IOI_NE2A2_1", + "RIOI_ILOGIC1_OFB", + "IOI_LOGIC_OUTS7_1", + "IOI_IMUX24_1", + "IOI_IMUX18_0", + "IOI_NE4C1_0", + "IOI_EE4BEG1_1", + "RIOI_IBUF1", + "RIOI_I2GCLK_TOP1", + "IOI_BYP4_0", + "RIOI_ISIN10", + "IOI_EE2A2_1", + "IOI_ER1BEG1_0", + "IOI_WL1END1_1", + "IOI_IMUX31_0", + "IOI_ER1BEG2_0", + "IOI_IMUX28_1", + "IOI_WW4C0_1", + "IOI_SE4C2_0", + "IOI_LOGIC_OUTS17_1", + "IOI_ODELAY0_CNTVALUEIN0", + "IOI_IMUX_RC2", + "IOI_WW4END2_0" + ], + "tile_type": "RIOI3_TBYTETERM", + "sites": [ + { + "site_pins": { + "T2": "IOI_OLOGIC1_T2", + "D5": "IOI_OLOGIC1_D5", + "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", + "D8": "IOI_OLOGIC1_D8", + "SR": "IOI_OLOGIC1_SR", + "SHIFTOUT1": "RIOI_OSOUT11", + "T4": "IOI_OLOGIC1_T4", + "SHIFTIN1": null, + "CLKDIV": "IOI_OLOGIC1_CLKDIV", + "OCE": "IOI_OLOGIC1_OCE", + "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", + "CLKB": "IOI_OLOGIC1_CLKB", + "OQ": "RIOI_OLOGIC1_OQ", + "D3": "IOI_OLOGIC1_D3", + "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", + "SHIFTIN2": null, + "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", + "D1": "IOI_OLOGIC1_D1", + "CLK": "IOI_OLOGIC1_CLK", + "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", + "T1": "IOI_OLOGIC1_T1", + "D4": "IOI_OLOGIC1_D4", + "TCE": "IOI_OLOGIC1_TCE", + "D2": "IOI_OLOGIC1_D2", + "SHIFTOUT2": "RIOI_OSOUT21", + "OFB": "RIOI_OLOGIC1_OFB", + "TFB": "RIOI_OLOGIC1_TFB", + "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", + "D7": "IOI_OLOGIC1_D7", + "T3": "IOI_OLOGIC1_T3", + "D6": "IOI_OLOGIC1_D6", + "TQ": "RIOI_OLOGIC1_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC1_BITSLIP", + "CLK": "IOI_ILOGIC1_CLK", + "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", + "Q3": "IOI_ILOGIC1_Q3", + "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", + "D": "RIOI_ILOGIC1_D", + "SR": "IOI_ILOGIC1_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC1_CE1", + "Q8": "IOI_ILOGIC1_Q8", + "SHIFTIN2": "RIOI_ISIN21", + "Q2": "IOI_ILOGIC1_Q2", + "CE2": "IOI_ILOGIC1_CE2", + "CLKDIV": "IOI_ILOGIC1_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", + "SHIFTOUT2": "RIOI_ISOUT21", + "O": "IOI_ILOGIC1_O", + "OFB": "RIOI_ILOGIC1_OFB", + "TFB": "RIOI_ILOGIC1_TFB", + "Q4": "IOI_ILOGIC1_Q4", + "CLKB": "IOI_ILOGIC1_CLKB", + "Q1": "IOI_ILOGIC1_Q1", + "Q5": "IOI_ILOGIC1_Q5", + "SHIFTIN1": "RIOI_ISIN11", + "Q6": "IOI_ILOGIC1_Q6", + "DDLY": "RIOI_ILOGIC1_DDLY", + "SHIFTOUT1": "RIOI_ISOUT11", + "OCLK": "IOI_ILOGIC1_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC1_Q7", + "OCLKB": "IOI_ILOGIC1_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "T2": "IOI_OLOGIC0_T2", + "D5": "IOI_OLOGIC0_D5", + "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", + "D8": "IOI_OLOGIC0_D8", + "SR": "IOI_OLOGIC0_SR", + "SHIFTOUT1": "RIOI_OSOUT10", + "T4": "IOI_OLOGIC0_T4", + "SHIFTIN1": "RIOI_OSIN10", + "CLKDIV": "IOI_OLOGIC0_CLKDIV", + "OCE": "IOI_OLOGIC0_OCE", + "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", + "CLKB": "IOI_OLOGIC0_CLKB", + "OQ": "RIOI_OLOGIC0_OQ", + "D3": "IOI_OLOGIC0_D3", + "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", + "SHIFTIN2": "RIOI_OSIN20", + "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", + "D1": "IOI_OLOGIC0_D1", + "CLK": "IOI_OLOGIC0_CLK", + "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", + "T1": "IOI_OLOGIC0_T1", + "D4": "IOI_OLOGIC0_D4", + "TCE": "IOI_OLOGIC0_TCE", + "D2": "IOI_OLOGIC0_D2", + "SHIFTOUT2": "RIOI_OSOUT20", + "OFB": "RIOI_OLOGIC0_OFB", + "TFB": "RIOI_OLOGIC0_TFB", + "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", + "D7": "IOI_OLOGIC0_D7", + "T3": "IOI_OLOGIC0_T3", + "D6": "IOI_OLOGIC0_D6", + "TQ": "RIOI_OLOGIC0_TQ", + "REV": null + }, + "type": "OLOGICE3", + "prefix": "OLOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "BITSLIP": "IOI_ILOGIC0_BITSLIP", + "CLK": "IOI_ILOGIC0_CLK", + "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", + "Q3": "IOI_ILOGIC0_Q3", + "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", + "D": "RIOI_ILOGIC0_D", + "SR": "IOI_ILOGIC0_SR", + "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", + "CE1": "IOI_ILOGIC0_CE1", + "Q8": "IOI_ILOGIC0_Q8", + "SHIFTIN2": null, + "Q2": "IOI_ILOGIC0_Q2", + "CE2": "IOI_ILOGIC0_CE2", + "CLKDIV": "IOI_ILOGIC0_CLKDIV", + "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", + "SHIFTOUT2": "RIOI_ISOUT20", + "O": "IOI_ILOGIC0_O", + "OFB": "RIOI_ILOGIC0_OFB", + "TFB": "RIOI_ILOGIC0_TFB", + "Q4": "IOI_ILOGIC0_Q4", + "CLKB": "IOI_ILOGIC0_CLKB", + "Q1": "IOI_ILOGIC0_Q1", + "Q5": "IOI_ILOGIC0_Q5", + "SHIFTIN1": null, + "Q6": "IOI_ILOGIC0_Q6", + "DDLY": "RIOI_ILOGIC0_DDLY", + "SHIFTOUT1": "RIOI_ISOUT10", + "OCLK": "IOI_ILOGIC0_OCLK", + "REV": null, + "Q7": "IOI_ILOGIC0_Q7", + "OCLKB": "IOI_ILOGIC0_OCLKB" + }, + "type": "ILOGICE3", + "prefix": "ILOGIC", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY1_CINVCTRL", + "IFDLY0": "RIOI3_IDELAY1_IFDLY0", + "INC": "IOI_IDELAY1_INC", + "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", + "LD": "IOI_IDELAY1_LD", + "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY1_REGRST", + "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", + "IDATAIN": "RIOI_IDELAY1_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY1_DATAIN", + "CE": "IOI_IDELAY1_CE", + "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", + "IFDLY2": "RIOI3_IDELAY1_IFDLY2", + "C": "IOI_IDELAY1_C", + "IFDLY1": "RIOI3_IDELAY1_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", + "DATAOUT": "RIOI_IDELAY1_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y0", + "x_coord": 0, + "y_coord": 0 + }, + { + "site_pins": { + "CINVCTRL": "IOI_IDELAY0_CINVCTRL", + "IFDLY0": "RIOI3_IDELAY0_IFDLY0", + "INC": "IOI_IDELAY0_INC", + "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", + "LD": "IOI_IDELAY0_LD", + "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", + "REGRST": "IOI_IDELAY0_REGRST", + "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", + "IDATAIN": "RIOI_IDELAY0_IDATAIN", + "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", + "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", + "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", + "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", + "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", + "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", + "DATAIN": "IOI_IDELAY0_DATAIN", + "CE": "IOI_IDELAY0_CE", + "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", + "IFDLY2": "RIOI3_IDELAY0_IFDLY2", + "C": "IOI_IDELAY0_C", + "IFDLY1": "RIOI3_IDELAY0_IFDLY1", + "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", + "DATAOUT": "RIOI_IDELAY0_DATAOUT" + }, + "type": "IDELAYE2", + "prefix": "IDELAY", + "name": "X0Y1", + "x_coord": 0, + "y_coord": 1 + } + ] } \ No newline at end of file diff --git a/artix7/tile_type_R_TERM_INT.json b/artix7/tile_type_R_TERM_INT.json index c71ccc8..6d5e1ce 100644 --- a/artix7/tile_type_R_TERM_INT.json +++ b/artix7/tile_type_R_TERM_INT.json @@ -1,173 +1,173 @@ { + "pips": {}, "wires": [ - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "R_TERM_INT_NW4END0", - "R_TERM_INT_NW2A3", - "TERM_INT_IMUX5", - "TERM_INT_IMUX46", - "TERM_INT_IMUX28", - "TERM_INT_LOGIC_OUTS_L_B6", - "R_TERM_INT_WW4A2", - "R_TERM_INT_NW4A1", - "TERM_INT_FAN1", - "R_TERM_INT_WW2A2", - "R_TERM_INT_SW4END3", - "TERM_INT_IMUX6", - "TERM_INT_IMUX19", - "R_TERM_INT_SW4A3", - "R_TERM_INT_WW2A0", - "TERM_INT_LOGIC_OUTS_L_B9", - "R_TERM_INT_NW4A0", - "R_TERM_INT_WW2END3", - "TERM_INT_BYP4", - "TERM_INT_MONITOR_P", - "TERM_INT_IMUX26", - "TERM_INT_BYP2", - "TERM_INT_FAN0", - "R_TERM_INT_LH0", - "TERM_INT_LOGIC_OUTS_L_B15", - "TERM_INT_BLOCK_OUTS_L_B2", - "TERM_INT_IMUX17", - "TERM_INT_IMUX45", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "TERM_INT_CTRL0", - "TERM_INT_IMUX39", - "TERM_INT_IMUX0", - "TERM_INT_IMUX31", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "TERM_INT_BYP0", + "R_TERM_INT_WR1END2", + "TERM_INT_IMUX8", + "R_TERM_INT_LH3", + "R_TERM_INT_WW2END1", "R_TERM_INT_WL1END2", - "TERM_INT_IMUX35", - "TERM_INT_IMUX43", - "R_TERM_INT_WW4C3", - "TERM_INT_IMUX10", - "TERM_INT_FAN6", - "TERM_INT_LOGIC_OUTS_L_B22", - "R_TERM_INT_WW4C0", - "TERM_INT_BYP6", - "TERM_INT_LOGIC_OUTS_L_B11", - "TERM_INT_LOGIC_OUTS_L_B12", - "TERM_INT_CLK0", - "R_TERM_INT_LH5", - "TERM_INT_MONITOR_N", - "R_TERM_INT_LH2", - "R_TERM_INT_NW4END3", - "TERM_INT_LOGIC_OUTS_L_B3", - "TERM_INT_IMUX20", - "TERM_INT_IMUX33", - "TERM_INT_IMUX40", - "R_TERM_INT_WR1END0", - "TERM_INT_LOGIC_OUTS_L_B0", - "TERM_INT_LOGIC_OUTS_L_B1", - "R_TERM_INT_WR1END1", - "TERM_INT_FAN5", - "R_TERM_INT_SW4A0", - "R_TERM_INT_WW4B0", - "TERM_INT_LOGIC_OUTS_L_B16", - "R_TERM_INT_NW4A3", - "TERM_INT_IMUX22", - "TERM_INT_BYP5", - "R_TERM_INT_WW4A0", - "R_TERM_INT_WW2END2", - "TERM_INT_IMUX30", - "TERM_INT_IMUX11", - "R_TERM_INT_WW4END1", - "TERM_INT_IMUX2", - "R_TERM_INT_WW4A3", - "R_TERM_INT_WW4END3", - "R_TERM_INT_WR1END3", - "R_TERM_INT_SW4END2", - "TERM_INT_LOGIC_OUTS_L_B14", - "R_TERM_INT_LH1", - "R_TERM_INT_SW2A3", - "TERM_INT_BLOCK_OUTS_L_B3", - "TERM_INT_IMUX42", - "TERM_INT_IMUX15", - "R_TERM_INT_NW4END2", "TERM_INT_IMUX27", - "R_TERM_INT_WW2A1", + "TERM_INT_LOGIC_OUTS_L_B14", + "TERM_INT_IMUX17", + "R_TERM_INT_NW4A2", + "TERM_INT_LOGIC_OUTS_L_B9", + "R_TERM_INT_WW4A2", + "L_TERM_INT_PHASER_TO_IO_ICLKDIV", + "R_TERM_INT_NW4A0", + "R_TERM_INT_WW2A3", "R_TERM_INT_WW4B1", + "TERM_INT_CLK0", + "R_TERM_INT_WR1END1", + "TERM_INT_IMUX30", + "R_TERM_INT_WW4C1", + "TERM_INT_IMUX35", + "TERM_INT_LOGIC_OUTS_L_B15", + "TERM_INT_LOGIC_OUTS_L_B16", + "TERM_INT_IMUX38", + "TERM_INT_IMUX6", + "TERM_INT_IMUX36", + "TERM_INT_CTRL1", + "TERM_INT_FAN5", + "R_TERM_INT_SW2A0", + "R_TERM_INT_NW2A3", + "R_TERM_INT_WW2END2", + "R_TERM_INT_NW4END3", + "R_TERM_INT_WW4A1", + "R_TERM_INT_WW2END0", + "R_TERM_INT_WW4B3", + "TERM_INT_IMUX26", + "TERM_INT_LOGIC_OUTS_L_B20", + "TERM_INT_LOGIC_OUTS_L_B1", + "R_TERM_INT_SW4A1", + "TERM_INT_IMUX13", + "TERM_INT_BYP5", + "TERM_INT_BLOCK_OUTS_L_B2", + "R_TERM_INT_WW4END0", + "TERM_INT_IMUX42", + "TERM_INT_IMUX19", + "R_TERM_INT_SW4END1", + "R_TERM_INT_SW2A2", + "R_TERM_INT_NW2A0", + "TERM_INT_IMUX3", + "R_TERM_INT_WW4C0", + "TERM_INT_BYP3", + "R_TERM_INT_WW2END3", + "TERM_INT_IMUX2", "R_TERM_INT_WW4B2", + "TERM_INT_FAN6", + "TERM_INT_FAN3", + "TERM_INT_LOGIC_OUTS_L_B12", + "TERM_INT_LOGIC_OUTS_L_B11", + "TERM_INT_LOGIC_OUTS_L_B3", + "R_TERM_INT_LH4", + "TERM_INT_BLOCK_OUTS_L_B3", + "TERM_INT_BYP6", + "TERM_INT_IMUX1", + "R_TERM_INT_NW2A1", + "TERM_INT_IMUX12", + "R_TERM_INT_WR1END0", + "TERM_INT_IMUX10", + "TERM_INT_BLOCK_OUTS_L_B1", + "R_TERM_INT_WW4C2", + "R_TERM_INT_LH1", + "R_TERM_INT_NW4A1", + "TERM_INT_IMUX23", + "R_TERM_INT_WW2A1", + "R_TERM_INT_SW4END2", + "TERM_INT_IMUX14", + "TERM_INT_CLK1", + "TERM_INT_IMUX25", + "R_TERM_INT_SW4A0", + "TERM_INT_LOGIC_OUTS_L_B0", + "TERM_INT_BYP1", + "L_TERM_INT_PHASER_TO_IO_OCLKDIV", + "TERM_INT_IMUX22", + "TERM_INT_FAN7", + "TERM_INT_MONITOR_N", + "R_TERM_INT_NW2A2", + "TERM_INT_IMUX4", + "R_TERM_INT_LH2", + "TERM_INT_LOGIC_OUTS_L_B10", + "TERM_INT_IMUX45", + "R_TERM_INT_NW4END0", + "TERM_INT_FAN1", + "TERM_INT_FAN0", + "R_TERM_INT_WW2A2", + "R_TERM_INT_WL1END1", + "TERM_INT_IMUX29", + "TERM_INT_IMUX5", + "R_TERM_INT_SW4END3", + "TERM_INT_IMUX41", + "L_TERM_INT_PHASER_TO_IO_OCLK", + "R_TERM_INT_WW4A0", + "TERM_INT_BLOCK_OUTS_L_B0", + "TERM_INT_IMUX46", + "R_TERM_INT_SW2A3", + "TERM_INT_LOGIC_OUTS_L_B21", + "R_TERM_INT_WL1END3", + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", + "TERM_INT_IMUX16", + "TERM_INT_BYP4", + "TERM_INT_IMUX37", + "TERM_INT_IMUX32", + "R_TERM_INT_WW4B0", + "R_TERM_INT_WW4A3", + "TERM_INT_IMUX28", + "TERM_INT_IMUX15", + "TERM_INT_FAN4", "TERM_INT_IMUX44", "R_TERM_INT_WL1END0", - "TERM_INT_IMUX23", - "TERM_INT_LOGIC_OUTS_L_B13", - "TERM_INT_LOGIC_OUTS_L_B21", - "R_TERM_INT_NW4A2", - "R_TERM_INT_SW4A1", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "TERM_INT_CLK1", - "TERM_INT_IMUX24", - "TERM_INT_IMUX14", - "R_TERM_INT_SW4END0", - "R_TERM_INT_NW2A2", - "TERM_INT_LOGIC_OUTS_L_B4", - "TERM_INT_IMUX1", - "TERM_INT_LOGIC_OUTS_L_B19", - "TERM_INT_LOGIC_OUTS_L_B23", - "R_TERM_INT_NW4END1", - "R_TERM_INT_WL1END1", - "TERM_INT_IMUX3", - "TERM_INT_FAN7", - "TERM_INT_BYP7", - "TERM_INT_FAN4", - "R_TERM_INT_LH3", - "TERM_INT_IMUX38", - "L_TERM_INT_DQS_IOTOPHASER", - "R_TERM_INT_WR1END2", - "TERM_INT_LOGIC_OUTS_L_B17", - "TERM_INT_LOGIC_OUTS_L_B5", - "R_TERM_INT_WW4C2", - "R_TERM_INT_SW2A1", - "R_TERM_INT_WW4END0", - "R_TERM_INT_WW2END1", - "R_TERM_INT_WW2END0", - "TERM_INT_BYP1", - "TERM_INT_IMUX13", - "TERM_INT_IMUX7", - "TERM_INT_LOGIC_OUTS_L_B10", - "R_TERM_INT_SW2A0", - "R_TERM_INT_NW2A0", - "TERM_INT_BYP3", - "TERM_INT_IMUX12", - "TERM_INT_BYP0", - "TERM_INT_LOGIC_OUTS_L_B8", - "R_TERM_INT_WL1END3", - "TERM_INT_BLOCK_OUTS_L_B1", - "R_TERM_INT_SW4END1", - "TERM_INT_LOGIC_OUTS_L_B2", + "R_TERM_INT_LH5", "TERM_INT_IMUX47", - "R_TERM_INT_WW4END2", - "R_TERM_INT_WW4C1", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", + "R_TERM_INT_SW4A3", + "TERM_INT_LOGIC_OUTS_L_B6", + "TERM_INT_IMUX20", + "TERM_INT_IMUX40", + "R_TERM_INT_SW2A1", + "L_TERM_INT_DQS_IOTOPHASER", + "TERM_INT_IMUX43", + "TERM_INT_LOGIC_OUTS_L_B19", + "TERM_INT_IMUX39", + "R_TERM_INT_WW4END1", + "TERM_INT_IMUX33", + "R_TERM_INT_NW4END1", + "TERM_INT_LOGIC_OUTS_L_B8", "TERM_INT_IMUX18", - "TERM_INT_IMUX32", - "TERM_INT_CTRL1", - "TERM_INT_BLOCK_OUTS_L_B0", - "TERM_INT_LOGIC_OUTS_L_B20", - "TERM_INT_IMUX37", - "TERM_INT_IMUX36", - "TERM_INT_IMUX4", - "TERM_INT_FAN3", + "R_TERM_INT_WW4END3", + "TERM_INT_MONITOR_P", + "TERM_INT_IMUX24", "TERM_INT_IMUX9", - "R_TERM_INT_NW2A1", - "R_TERM_INT_LH4", - "TERM_INT_IMUX41", - "TERM_INT_IMUX8", - "R_TERM_INT_SW4A2", - "TERM_INT_IMUX21", - "TERM_INT_LOGIC_OUTS_L_B18", - "TERM_INT_IMUX34", - "TERM_INT_IMUX25", - "R_TERM_INT_WW2A3", - "TERM_INT_IMUX16", - "R_TERM_INT_SW2A2", - "TERM_INT_IMUX29", - "R_TERM_INT_WW4B3", - "TERM_INT_FAN2", + "R_TERM_INT_WW4END2", + "TERM_INT_BYP2", + "TERM_INT_IMUX0", "TERM_INT_LOGIC_OUTS_L_B7", - "R_TERM_INT_WW4A1" + "TERM_INT_LOGIC_OUTS_L_B17", + "TERM_INT_LOGIC_OUTS_L_B23", + "R_TERM_INT_NW4END2", + "TERM_INT_CTRL0", + "TERM_INT_LOGIC_OUTS_L_B13", + "TERM_INT_LOGIC_OUTS_L_B5", + "R_TERM_INT_WR1END3", + "R_TERM_INT_LH0", + "TERM_INT_IMUX21", + "R_TERM_INT_SW4A2", + "TERM_INT_BYP7", + "R_TERM_INT_NW4A3", + "TERM_INT_IMUX11", + "TERM_INT_IMUX34", + "TERM_INT_FAN2", + "TERM_INT_IMUX7", + "TERM_INT_LOGIC_OUTS_L_B18", + "TERM_INT_LOGIC_OUTS_L_B4", + "TERM_INT_LOGIC_OUTS_L_B22", + "R_TERM_INT_WW2A0", + "TERM_INT_LOGIC_OUTS_L_B2", + "TERM_INT_IMUX31", + "L_TERM_INT_PHASER_TO_IO_ICLK", + "R_TERM_INT_WW4C3", + "R_TERM_INT_SW4END0" ], - "sites": [], - "pips": {}, - "tile_type": "R_TERM_INT" + "tile_type": "R_TERM_INT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_R_TERM_INT_GTX.json b/artix7/tile_type_R_TERM_INT_GTX.json index 23b026c..1265d82 100644 --- a/artix7/tile_type_R_TERM_INT_GTX.json +++ b/artix7/tile_type_R_TERM_INT_GTX.json @@ -1,161 +1,161 @@ { - "wires": [ - "R_TERM_INT_GTX_LOGIC_OUTS_B12", - "R_TERM_INT_NW4END0", - "R_TERM_INT_NW2A3", - "R_TERM_INT_GTX_IMUX23", - "R_TERM_INT_GTX_CTRL0", - "R_TERM_INT_GTX_BYP1", - "R_TERM_INT_GTX_IMUX34", - "R_TERM_INT_GTX_LOGIC_OUTS_B8", - "R_TERM_INT_WW4A2", - "R_TERM_INT_NW4A1", - "R_TERM_INT_GTX_LOGIC_OUTS_B1", - "R_TERM_INT_GTX_IMUX26", - "R_TERM_INT_WW2A2", - "R_TERM_INT_SW4END3", - "R_TERM_INT_GTX_IMUX24", - "R_TERM_INT_SW4A3", - "R_TERM_INT_GTX_IMUX0", - "R_TERM_INT_GTX_IMUX17", - "R_TERM_INT_WW2A0", - "R_TERM_INT_GTX_FAN2", - "R_TERM_INT_GTX_IMUX11", - "R_TERM_INT_NW4A0", - "R_TERM_INT_WW2END3", - "R_TERM_INT_GTX_IMUX9", - "R_TERM_INT_GTX_IMUX30", - "R_TERM_INT_LH0", - "R_TERM_INT_GTX_LOGIC_OUTS_B5", - "R_TERM_INT_GTX_IMUX4", - "R_TERM_INT_GTX_IMUX19", - "R_TERM_INT_GTX_FAN4", - "R_TERM_INT_GTX_LOGIC_OUTS_B22", - "R_TERM_INT_GTX_LOGIC_OUTS_B4", - "R_TERM_INT_GTX_LOGIC_OUTS_B21", - "R_TERM_INT_GTX_IMUX47", - "R_TERM_INT_GTX_FAN5", - "R_TERM_INT_GTX_LOGIC_OUTS_B0", - "R_TERM_INT_GTX_IMUX21", - "R_TERM_INT_WL1END2", - "R_TERM_INT_GTX_IMUX27", - "R_TERM_INT_GTX_IMUX7", - "R_TERM_INT_GTX_IMUX13", - "R_TERM_INT_GTX_LOGIC_OUTS_B7", - "R_TERM_INT_WW4C3", - "R_TERM_INT_WW4C0", - "R_TERM_INT_GTX_IMUX40", - "R_TERM_INT_GTX_IMUX5", - "R_TERM_INT_GTX_LOGIC_OUTS_B3", - "R_TERM_INT_GTX_IMUX36", - "R_TERM_INT_LH5", - "R_TERM_INT_LH2", - "R_TERM_INT_GTX_LOGIC_OUTS_B6", - "R_TERM_INT_NW4END3", - "R_TERM_INT_GTX_LOGIC_OUTS_B13", - "R_TERM_INT_WR1END0", - "R_TERM_INT_GTX_FAN3", - "R_TERM_INT_WR1END1", - "R_TERM_INT_SW4A0", - "R_TERM_INT_WW4B0", - "R_TERM_INT_GTX_BYP7", - "R_TERM_INT_NW4A3", - "R_TERM_INT_WW4A0", - "R_TERM_INT_WW2END2", - "R_TERM_INT_WW4END1", - "R_TERM_INT_WW4A3", - "R_TERM_INT_GTX_IMUX41", - "R_TERM_INT_WW4END3", - "R_TERM_INT_WR1END3", - "R_TERM_INT_GTX_IMUX42", - "R_TERM_INT_SW4END2", - "R_TERM_INT_LH1", - "R_TERM_INT_SW2A3", - "R_TERM_INT_WW2A1", - "R_TERM_INT_NW4END2", - "R_TERM_INT_WW4B1", - "R_TERM_INT_GTX_FAN7", - "R_TERM_INT_GTX_IMUX28", - "R_TERM_INT_WW4B2", - "R_TERM_INT_GTX_IMUX3", - "R_TERM_INT_GTX_IMUX20", - "R_TERM_INT_GTX_LOGIC_OUTS_B19", - "R_TERM_INT_WL1END0", - "R_TERM_INT_GTX_BYP5", - "R_TERM_INT_GTX_IMUX29", - "R_TERM_INT_GTX_IMUX37", - "R_TERM_INT_GTX_IMUX15", - "R_TERM_INT_GTX_BYP2", - "R_TERM_INT_GTX_LOGIC_OUTS_B11", - "R_TERM_INT_GTX_IMUX10", - "R_TERM_INT_GTX_IMUX6", - "R_TERM_INT_NW4A2", - "R_TERM_INT_GTX_LOGIC_OUTS_B9", - "R_TERM_INT_SW4A1", - "R_TERM_INT_NW2A2", - "R_TERM_INT_SW4END0", - "R_TERM_INT_GTX_CLK0", - "R_TERM_INT_GTX_IMUX33", - "R_TERM_INT_GTX_IMUX46", - "R_TERM_INT_GTX_FAN1", - "R_TERM_INT_NW4END1", - "R_TERM_INT_WL1END1", - "R_TERM_INT_GTX_IMUX14", - "R_TERM_INT_GTX_IMUX39", - "R_TERM_INT_GTX_LOGIC_OUTS_B15", - "R_TERM_INT_GTX_IMUX43", - "R_TERM_INT_LH3", - "R_TERM_INT_GTX_CTRL1", - "R_TERM_INT_GTX_IMUX2", - "R_TERM_INT_WR1END2", - "R_TERM_INT_WW4C2", - "R_TERM_INT_GTX_LOGIC_OUTS_B2", - "R_TERM_INT_GTX_IMUX12", - "R_TERM_INT_SW2A1", - "R_TERM_INT_WW2END1", - "R_TERM_INT_WW4END0", - "R_TERM_INT_WW2END0", - "R_TERM_INT_GTX_IMUX8", - "R_TERM_INT_NW2A0", - "R_TERM_INT_SW2A0", - "R_TERM_INT_GTX_IMUX35", - "R_TERM_INT_GTX_FAN0", - "R_TERM_INT_GTX_LOGIC_OUTS_B17", - "R_TERM_INT_WL1END3", - "R_TERM_INT_SW4END1", - "R_TERM_INT_GTX_IMUX25", - "R_TERM_INT_GTX_LOGIC_OUTS_B18", - "R_TERM_INT_WW4END2", - "R_TERM_INT_WW4C1", - "R_TERM_INT_GTX_IMUX44", - "R_TERM_INT_GTX_IMUX32", - "R_TERM_INT_GTX_LOGIC_OUTS_B14", - "R_TERM_INT_GTX_BYP4", - "R_TERM_INT_GTX_IMUX38", - "R_TERM_INT_GTX_LOGIC_OUTS_B23", - "R_TERM_INT_GTX_CLK1", - "R_TERM_INT_NW2A1", - "R_TERM_INT_GTX_IMUX45", - "R_TERM_INT_LH4", - "R_TERM_INT_GTX_BYP3", - "R_TERM_INT_GTX_IMUX16", - "R_TERM_INT_SW4A2", - "R_TERM_INT_GTX_LOGIC_OUTS_B20", - "R_TERM_INT_GTX_LOGIC_OUTS_B16", - "R_TERM_INT_GTX_IMUX22", - "R_TERM_INT_GTX_IMUX1", - "R_TERM_INT_WW2A3", - "R_TERM_INT_GTX_IMUX18", - "R_TERM_INT_GTX_LOGIC_OUTS_B10", - "R_TERM_INT_GTX_FAN6", - "R_TERM_INT_SW2A2", - "R_TERM_INT_WW4B3", - "R_TERM_INT_GTX_IMUX31", - "R_TERM_INT_GTX_BYP0", - "R_TERM_INT_WW4A1", - "R_TERM_INT_GTX_BYP6" - ], - "sites": [], "pips": {}, - "tile_type": "R_TERM_INT_GTX" + "wires": [ + "R_TERM_INT_WR1END2", + "R_TERM_INT_GTX_IMUX44", + "R_TERM_INT_GTX_LOGIC_OUTS_B6", + "R_TERM_INT_GTX_IMUX11", + "R_TERM_INT_LH3", + "R_TERM_INT_GTX_LOGIC_OUTS_B22", + "R_TERM_INT_WW2END1", + "R_TERM_INT_WL1END2", + "R_TERM_INT_NW4A2", + "R_TERM_INT_WW4A2", + "R_TERM_INT_NW4A0", + "R_TERM_INT_WW2A3", + "R_TERM_INT_WW4B1", + "R_TERM_INT_WR1END1", + "R_TERM_INT_WW4C1", + "R_TERM_INT_GTX_IMUX28", + "R_TERM_INT_SW2A0", + "R_TERM_INT_NW2A3", + "R_TERM_INT_WW2END2", + "R_TERM_INT_NW4END3", + "R_TERM_INT_GTX_FAN0", + "R_TERM_INT_WW4A1", + "R_TERM_INT_WW2END0", + "R_TERM_INT_WW4B3", + "R_TERM_INT_GTX_BYP3", + "R_TERM_INT_GTX_IMUX6", + "R_TERM_INT_SW4A1", + "R_TERM_INT_GTX_IMUX4", + "R_TERM_INT_GTX_IMUX8", + "R_TERM_INT_GTX_IMUX29", + "R_TERM_INT_GTX_LOGIC_OUTS_B17", + "R_TERM_INT_WW4END0", + "R_TERM_INT_SW4END1", + "R_TERM_INT_GTX_IMUX32", + "R_TERM_INT_NW2A0", + "R_TERM_INT_SW2A2", + "R_TERM_INT_WW4C0", + "R_TERM_INT_WW2END3", + "R_TERM_INT_GTX_IMUX34", + "R_TERM_INT_WW4B2", + "R_TERM_INT_GTX_LOGIC_OUTS_B2", + "R_TERM_INT_GTX_IMUX3", + "R_TERM_INT_GTX_IMUX40", + "R_TERM_INT_LH4", + "R_TERM_INT_GTX_LOGIC_OUTS_B0", + "R_TERM_INT_GTX_IMUX31", + "R_TERM_INT_GTX_IMUX22", + "R_TERM_INT_GTX_LOGIC_OUTS_B5", + "R_TERM_INT_GTX_LOGIC_OUTS_B10", + "R_TERM_INT_GTX_FAN4", + "R_TERM_INT_GTX_IMUX35", + "R_TERM_INT_GTX_IMUX9", + "R_TERM_INT_GTX_IMUX37", + "R_TERM_INT_GTX_LOGIC_OUTS_B16", + "R_TERM_INT_GTX_IMUX26", + "R_TERM_INT_NW2A1", + "R_TERM_INT_GTX_IMUX43", + "R_TERM_INT_GTX_IMUX17", + "R_TERM_INT_GTX_CTRL1", + "R_TERM_INT_WR1END0", + "R_TERM_INT_GTX_IMUX39", + "R_TERM_INT_GTX_LOGIC_OUTS_B3", + "R_TERM_INT_WW4C2", + "R_TERM_INT_LH1", + "R_TERM_INT_NW4A1", + "R_TERM_INT_GTX_BYP1", + "R_TERM_INT_GTX_IMUX36", + "R_TERM_INT_WW2A1", + "R_TERM_INT_GTX_BYP0", + "R_TERM_INT_SW4END2", + "R_TERM_INT_GTX_IMUX38", + "R_TERM_INT_GTX_FAN2", + "R_TERM_INT_GTX_IMUX47", + "R_TERM_INT_SW4A0", + "R_TERM_INT_GTX_IMUX25", + "R_TERM_INT_NW2A2", + "R_TERM_INT_GTX_IMUX45", + "R_TERM_INT_GTX_LOGIC_OUTS_B7", + "R_TERM_INT_LH2", + "R_TERM_INT_GTX_IMUX27", + "R_TERM_INT_NW4END0", + "R_TERM_INT_GTX_LOGIC_OUTS_B4", + "R_TERM_INT_GTX_IMUX18", + "R_TERM_INT_GTX_LOGIC_OUTS_B20", + "R_TERM_INT_GTX_LOGIC_OUTS_B18", + "R_TERM_INT_WW2A2", + "R_TERM_INT_GTX_IMUX30", + "R_TERM_INT_GTX_LOGIC_OUTS_B9", + "R_TERM_INT_GTX_LOGIC_OUTS_B15", + "R_TERM_INT_GTX_FAN3", + "R_TERM_INT_WL1END1", + "R_TERM_INT_GTX_IMUX41", + "R_TERM_INT_SW4END3", + "R_TERM_INT_GTX_IMUX13", + "R_TERM_INT_GTX_IMUX14", + "R_TERM_INT_GTX_CLK1", + "R_TERM_INT_WW4A0", + "R_TERM_INT_GTX_BYP2", + "R_TERM_INT_GTX_LOGIC_OUTS_B23", + "R_TERM_INT_SW2A3", + "R_TERM_INT_GTX_CLK0", + "R_TERM_INT_WL1END3", + "R_TERM_INT_GTX_LOGIC_OUTS_B19", + "R_TERM_INT_GTX_IMUX15", + "R_TERM_INT_GTX_FAN6", + "R_TERM_INT_GTX_IMUX7", + "R_TERM_INT_GTX_IMUX20", + "R_TERM_INT_WW4B0", + "R_TERM_INT_GTX_LOGIC_OUTS_B12", + "R_TERM_INT_WW4A3", + "R_TERM_INT_GTX_LOGIC_OUTS_B14", + "R_TERM_INT_GTX_CTRL0", + "R_TERM_INT_GTX_LOGIC_OUTS_B21", + "R_TERM_INT_WL1END0", + "R_TERM_INT_LH5", + "R_TERM_INT_SW4A3", + "R_TERM_INT_GTX_LOGIC_OUTS_B1", + "R_TERM_INT_SW2A1", + "R_TERM_INT_WW4END1", + "R_TERM_INT_GTX_LOGIC_OUTS_B13", + "R_TERM_INT_NW4END1", + "R_TERM_INT_GTX_IMUX23", + "R_TERM_INT_WW4END3", + "R_TERM_INT_GTX_BYP7", + "R_TERM_INT_GTX_FAN5", + "R_TERM_INT_GTX_LOGIC_OUTS_B8", + "R_TERM_INT_GTX_IMUX12", + "R_TERM_INT_GTX_IMUX5", + "R_TERM_INT_GTX_BYP4", + "R_TERM_INT_GTX_IMUX42", + "R_TERM_INT_GTX_BYP6", + "R_TERM_INT_GTX_IMUX21", + "R_TERM_INT_WW4END2", + "R_TERM_INT_NW4END2", + "R_TERM_INT_WR1END3", + "R_TERM_INT_GTX_BYP5", + "R_TERM_INT_GTX_IMUX46", + "R_TERM_INT_GTX_IMUX2", + "R_TERM_INT_LH0", + "R_TERM_INT_GTX_IMUX16", + "R_TERM_INT_GTX_FAN1", + "R_TERM_INT_GTX_LOGIC_OUTS_B11", + "R_TERM_INT_SW4A2", + "R_TERM_INT_GTX_IMUX10", + "R_TERM_INT_NW4A3", + "R_TERM_INT_GTX_IMUX0", + "R_TERM_INT_GTX_IMUX1", + "R_TERM_INT_GTX_IMUX33", + "R_TERM_INT_WW2A0", + "R_TERM_INT_GTX_IMUX19", + "R_TERM_INT_GTX_FAN7", + "R_TERM_INT_GTX_IMUX24", + "R_TERM_INT_WW4C3", + "R_TERM_INT_SW4END0" + ], + "tile_type": "R_TERM_INT_GTX", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_TERM_CMT.json b/artix7/tile_type_TERM_CMT.json index 9dbc798..f76a87e 100644 --- a/artix7/tile_type_TERM_CMT.json +++ b/artix7/tile_type_TERM_CMT.json @@ -1,11 +1,11 @@ { - "wires": [ - "TERM_CMT_FREQ_REF_NS3", - "TERM_CMT_FREQ_REF_NS0", - "TERM_CMT_FREQ_REF_NS1", - "TERM_CMT_FREQ_REF_NS2" - ], - "sites": [], "pips": {}, - "tile_type": "TERM_CMT" + "wires": [ + "TERM_CMT_FREQ_REF_NS1", + "TERM_CMT_FREQ_REF_NS2", + "TERM_CMT_FREQ_REF_NS0", + "TERM_CMT_FREQ_REF_NS3" + ], + "tile_type": "TERM_CMT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_T_TERM_INT.json b/artix7/tile_type_T_TERM_INT.json index 84e599c..1b14c7a 100644 --- a/artix7/tile_type_T_TERM_INT.json +++ b/artix7/tile_type_T_TERM_INT.json @@ -1,124 +1,124 @@ { + "pips": {}, "wires": [ - "T_TERM_UTURN_INT_LVB5", - "T_TERM_UTURN_INT_SE6C3", - "T_TERM_UTURN_INT_SW6D3", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", - "T_TERM_UTURN_INT_SE6E3", - "T_TERM_UTURN_INT_SS2A1", - "T_TERM_UTURN_INT_SW6C3", - "T_TERM_UTURN_INT_LV_L16", - "T_TERM_UTURN_INT_SS6B0", - "T_TERM_INT_UTURN_LV_R2", - "T_TERM_UTURN_INT_SS2A2", - "T_TERM_UTURN_INT_SW2A3", - "T_TERM_UTURN_INT_SS6END3", - "T_TERM_UTURN_INT_LVB1", - "T_TERM_INT_UTURN_LV_R5", - "T_TERM_UTURN_INT_SL1END0", - "T_TERM_UTURN_INT_SE6E1", - "T_TERM_INT_UTURN_LV_R17", - "T_TERM_UTURN_INT_SE6D3", - "T_TERM_UTURN_INT_SW6D1", - "T_TERM_UTURN_INT_SW2A1", - "T_TERM_UTURN_INT_SS6B2", - "T_TERM_UTURN_INT_LV_L4", - "T_TERM_UTURN_INT_SW6E3", - "T_TERM_UTURN_INT_SS6A3", - "T_TERM_UTURN_INT_LV_L17", - "T_TERM_UTURN_INT_SW2A0", - "T_TERM_UTURN_INT_LV_L6", - "T_TERM_INT_UTURN_LV_R9", - "T_TERM_UTURN_INT_SE2A3", - "T_TERM_UTURN_INT_SS6C0", - "T_TERM_UTURN_INT_SE6D0", - "T_TERM_UTURN_INT_SW6E1", - "T_TERM_UTURN_INT_LV_L2", - "T_TERM_UTURN_INT_SE2A0", - "T_TERM_UTURN_INT_SW6D0", - "T_TERM_UTURN_INT_LVB0", - "T_TERM_UTURN_INT_SS6END1", - "T_TERM_UTURN_INT_SR1END1", - "T_TERM_UTURN_INT_SL1END2", - "T_TERM_UTURN_INT_SW6C1", - "T_TERM_UTURN_INT_SS6E1", - "T_TERM_UTURN_INT_SW6B0", - "T_TERM_UTURN_INT_LVB2", - "T_TERM_UTURN_INT_SS2END0", - "T_TERM_UTURN_INT_SS6D3", - "T_TERM_UTURN_INT_SS6E2", - "T_TERM_INT_UTURN_LV_R4", - "T_TERM_INT_UTURN_LV_R6", - "T_TERM_UTURN_INT_SS6D1", - "T_TERM_UTURN_INT_SS6A0", - "T_TERM_UTURN_INT_SS2END1", "T_TERM_UTURN_INT_SE6D1", - "T_TERM_UTURN_INT_SS6A1", - "T_TERM_UTURN_INT_LVB_L5", - "T_TERM_UTURN_INT_SW2A2", - "T_TERM_UTURN_INT_LVB_L2", - "T_TERM_UTURN_INT_LVB_L3", - "T_TERM_UTURN_INT_SS6C2", - "T_TERM_UTURN_INT_SS6D0", - "T_TERM_UTURN_INT_SS2A0", - "T_TERM_UTURN_INT_SL1END3", - "T_TERM_UTURN_INT_LV_L9", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", - "T_TERM_UTURN_INT_SS6B1", - "T_TERM_UTURN_INT_SW6E2", - "T_TERM_UTURN_INT_SW6B2", - "T_TERM_UTURN_INT_SE2A1", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "T_TERM_UTURN_INT_SE6B2", - "T_TERM_UTURN_INT_SE6D2", - "T_TERM_UTURN_INT_SE6B3", - "T_TERM_UTURN_INT_LVB3", - "T_TERM_UTURN_INT_WR1BEG_S0", + "T_TERM_UTURN_INT_LVB1", + "T_TERM_UTURN_INT_SE6B0", + "T_TERM_UTURN_INT_SR1END1", + "T_TERM_UTURN_INT_WR1END_S1_0", "T_TERM_UTURN_INT_SW6B1", - "T_TERM_UTURN_INT_SR1END3", + "T_TERM_INT_UTURN_LV_R6", + "T_TERM_UTURN_INT_SS2A3", + "T_TERM_UTURN_INT_SS6E3", + "T_TERM_UTURN_INT_SW6B0", + "T_TERM_UTURN_INT_SW6B3", + "T_TERM_INT_UTURN_LV_R16", + "T_TERM_INT_UTURN_LV_R2", + "T_TERM_UTURN_INT_SE6D2", + "T_TERM_UTURN_INT_LV_L16", + "T_TERM_UTURN_INT_SE6C3", + "T_TERM_UTURN_INT_SE6B1", + "T_TERM_UTURN_INT_SE2A0", + "T_TERM_UTURN_INT_LV_L17", + "T_TERM_UTURN_INT_SS6END2", + "T_TERM_UTURN_INT_SW6D0", + "T_TERM_UTURN_INT_SS2END2", + "T_TERM_UTURN_INT_SW6E1", + "T_TERM_UTURN_INT_SS6D2", + "T_TERM_UTURN_INT_SW6D2", + "T_TERM_UTURN_INT_SE6E2", + "T_TERM_UTURN_INT_LVB2", + "T_TERM_UTURN_INT_SE6C1", + "T_TERM_UTURN_INT_LVB_L0", + "T_TERM_UTURN_INT_SW6D3", "T_TERM_UTURN_INT_LV_L7", "T_TERM_UTURN_INT_LV_L3", - "T_TERM_UTURN_INT_SS6END2", + "T_TERM_UTURN_INT_SS6C2", + "T_TERM_UTURN_INT_SW2A2", "T_TERM_UTURN_INT_LVB_L4", - "T_TERM_UTURN_INT_SE6C1", - "T_TERM_UTURN_INT_SS6C1", - "T_TERM_UTURN_INT_SW6E0", - "T_TERM_UTURN_INT_SE6B1", "T_TERM_UTURN_INT_SS6END0", - "T_TERM_UTURN_INT_SS6E0", - "T_TERM_UTURN_INT_LVB_L1", - "T_TERM_UTURN_INT_SS2END3", - "T_TERM_UTURN_INT_SS2END2", - "T_TERM_UTURN_INT_SS6A2", - "T_TERM_UTURN_INT_LVB_L0", - "T_TERM_UTURN_INT_ER1END3", - "T_TERM_INT_UTURN_LV_R16", - "T_TERM_UTURN_INT_SE6C2", - "T_TERM_UTURN_INT_SE2A2", - "T_TERM_UTURN_INT_SS6C3", - "T_TERM_INT_UTURN_LV_R7", - "T_TERM_UTURN_INT_SE6E0", - "T_TERM_UTURN_INT_SE6E2", - "T_TERM_UTURN_INT_SW6B3", - "T_TERM_UTURN_INT_LVB4", - "T_TERM_UTURN_INT_SS6D2", + "T_TERM_INT_UTURN_LV_R9", "T_TERM_UTURN_INT_SW6C2", - "T_TERM_UTURN_INT_SS6E3", - "T_TERM_UTURN_INT_WR1END_S1_0", - "T_TERM_UTURN_INT_SE6B0", - "T_TERM_UTURN_INT_SS6B3", - "T_TERM_UTURN_INT_SW6C0", - "T_TERM_UTURN_INT_SL1END1", - "T_TERM_UTURN_INT_LV_L5", - "T_TERM_UTURN_INT_SR1END2", - "T_TERM_UTURN_INT_SS2A3", - "T_TERM_UTURN_INT_SW6D2", - "T_TERM_UTURN_INT_SE6C0", + "T_TERM_UTURN_INT_WR1BEG_S0", + "T_TERM_UTURN_INT_SS6C0", + "T_TERM_UTURN_INT_SS6D1", + "T_TERM_UTURN_INT_SE6D0", + "T_TERM_UTURN_INT_SS2A0", "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", + "T_TERM_UTURN_INT_SS6E1", + "T_TERM_UTURN_INT_SS6A2", + "T_TERM_UTURN_INT_SW6E3", + "T_TERM_UTURN_INT_SE6C2", + "T_TERM_UTURN_INT_SW6B2", + "T_TERM_UTURN_INT_SS6B0", + "T_TERM_UTURN_INT_SR1END3", + "T_TERM_UTURN_INT_SS6C1", + "T_TERM_UTURN_INT_SS6A0", + "T_TERM_UTURN_INT_LVB_L2", + "T_TERM_INT_UTURN_LV_R5", + "T_TERM_UTURN_INT_SE6E3", + "T_TERM_UTURN_INT_SE2A2", + "T_TERM_UTURN_INT_SL1END1", + "T_TERM_UTURN_INT_SL1END3", + "T_TERM_UTURN_INT_LV_L6", + "T_TERM_UTURN_INT_SS2A1", + "T_TERM_UTURN_INT_LVB_L5", + "T_TERM_UTURN_INT_SE2A3", + "T_TERM_UTURN_INT_ER1END3", + "T_TERM_UTURN_INT_SS2END0", + "T_TERM_UTURN_INT_SS2A2", + "T_TERM_UTURN_INT_LV_L4", + "T_TERM_UTURN_INT_SW6C1", + "T_TERM_INT_UTURN_LV_R7", + "T_TERM_UTURN_INT_SW6C3", + "T_TERM_UTURN_INT_SW2A1", + "T_TERM_UTURN_INT_SS2END3", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", + "T_TERM_UTURN_INT_SS6C3", + "T_TERM_UTURN_INT_LVB_L3", + "T_TERM_UTURN_INT_SL1END2", + "T_TERM_UTURN_INT_SW6E0", + "T_TERM_UTURN_INT_SW2A0", "T_TERM_INT_UTURN_LV_R3", + "T_TERM_UTURN_INT_SE6C0", + "T_TERM_UTURN_INT_SR1END2", + "T_TERM_UTURN_INT_SS2END1", + "T_TERM_INT_UTURN_LV_R4", + "T_TERM_UTURN_INT_SE6B2", + "T_TERM_UTURN_INT_LVB4", + "T_TERM_UTURN_INT_LV_L2", + "T_TERM_UTURN_INT_SW6C0", + "T_TERM_UTURN_INT_LVB_L1", + "T_TERM_UTURN_INT_SS6E2", + "T_TERM_UTURN_INT_SS6B2", + "T_TERM_UTURN_INT_SW2A3", + "T_TERM_UTURN_INT_SE6D3", + "T_TERM_UTURN_INT_SS6D3", + "T_TERM_UTURN_INT_LVB3", + "T_TERM_UTURN_INT_SE6E0", + "T_TERM_UTURN_INT_SS6A3", + "T_TERM_UTURN_INT_LVB5", + "T_TERM_UTURN_INT_LV_L9", + "T_TERM_UTURN_INT_SS6B1", + "T_TERM_UTURN_INT_SS6E0", + "T_TERM_UTURN_INT_SS6D0", + "T_TERM_UTURN_INT_SW6D1", + "T_TERM_UTURN_INT_SE6B3", + "T_TERM_UTURN_INT_SS6END1", + "T_TERM_UTURN_INT_LV_L5", + "T_TERM_UTURN_INT_LVB0", + "T_TERM_UTURN_INT_SE6E1", + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", + "T_TERM_UTURN_INT_SE2A1", + "T_TERM_UTURN_INT_SS6B3", + "T_TERM_INT_UTURN_LV_R17", + "T_TERM_UTURN_INT_SS6END3", + "T_TERM_UTURN_INT_SS6A1", + "T_TERM_UTURN_INT_SW6E2", + "T_TERM_UTURN_INT_SL1END0", "T_TERM_UTURN_INT_ER1BEG_S0" ], - "sites": [], - "pips": {}, - "tile_type": "T_TERM_INT" + "tile_type": "T_TERM_INT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_VBRK.json b/artix7/tile_type_VBRK.json index c36d95b..1b76a90 100644 --- a/artix7/tile_type_VBRK.json +++ b/artix7/tile_type_VBRK.json @@ -1,133 +1,133 @@ { + "pips": {}, "wires": [ - "VBRK_WL1END1", - "VBRK_WW2A0", - "VBRK_NW2A1", - "VBRK_WW2END0", - "VBRK_NW2A0", - "VBRK_SE4C2", - "VBRK_SE4C1", - "VBRK_MONITOR_P", - "VBRK_NW4A0", - "VBRK_NE4BEG1", - "VBRK_SE4C3", - "VBRK_LH4", - "VBRK_SW2A2", - "VBRK_WW4B1", - "VBRK_SE4BEG3", - "VBRK_NW4END3", - "VBRK_EL1BEG2", - "VBRK_SE2A1", - "VBRK_NW2A2", - "VBRK_WW4C0", - "VBRK_EE2A3", - "VBRK_SW4A0", - "VBRK_SW4A1", - "VBRK_EE4A2", - "VBRK_WW4C1", - "VBRK_SW4A2", - "VBRK_EE4A1", - "VBRK_WW2END3", - "VBRK_SW4END1", - "VBRK_SE4C0", - "VBRK_WR1END1", - "VBRK_WL1END2", - "VBRK_WR1END3", - "VBRK_NE4BEG2", + "VBRK_EE4B2", + "VBRK_EE2BEG2", "VBRK_SW4A3", + "VBRK_SW2A0", + "VBRK_EL1BEG3", + "VBRK_LH1", + "VBRK_EE4B1", + "VBRK_NW4A3", + "VBRK_LH4", + "VBRK_WW2A3", + "VBRK_WW4B3", + "VBRK_SW2A1", + "VBRK_NW2A0", + "VBRK_WW2A2", + "VBRK_NE2A0", + "VBRK_EE4C1", + "VBRK_ER1BEG0", + "VBRK_SW4END2", + "VBRK_WW4C3", "VBRK_SE2A0", + "VBRK_NE4C0", + "VBRK_EE4A0", + "VBRK_WW2END1", + "VBRK_LH11", + "VBRK_NW4END3", + "VBRK_WW4C0", + "VBRK_SE4C3", + "VBRK_SW4A1", + "VBRK_WW4A2", + "VBRK_WW4A3", + "VBRK_LH8", + "VBRK_EE4BEG2", + "VBRK_NW2A1", + "VBRK_NE4BEG0", + "VBRK_WL1END3", + "VBRK_LH5", + "VBRK_WW2END0", + "VBRK_NE2A3", + "VBRK_EE2BEG1", + "VBRK_EE2A1", + "VBRK_LH10", + "VBRK_NW4END0", + "VBRK_WW2A1", + "VBRK_SW4END0", + "VBRK_NE4BEG3", + "VBRK_LH12", + "VBRK_SW4A2", + "VBRK_EE4BEG1", + "VBRK_WW4C1", + "VBRK_SW4END1", + "VBRK_EE4B0", + "VBRK_SW4END3", + "VBRK_WW4END1", + "VBRK_EE4BEG3", + "VBRK_NE4BEG2", + "VBRK_WW4A0", + "VBRK_EE2A0", + "VBRK_SW2A3", + "VBRK_SE4BEG0", + "VBRK_SE4BEG1", + "VBRK_WL1END2", + "VBRK_LH9", + "VBRK_EE4A1", "VBRK_MONITOR_N", - "VBRK_LH6", + "VBRK_NE4BEG1", + "VBRK_WW4B1", + "VBRK_WR1END3", + "VBRK_EE4B3", + "VBRK_EE4C3", + "VBRK_WW4A1", + "VBRK_NE2A2", + "VBRK_WW2END3", + "VBRK_NW4A2", + "VBRK_SE2A1", + "VBRK_EE4A2", + "VBRK_EE4C0", + "VBRK_NW2A3", + "VBRK_SE4C2", + "VBRK_WW4END2", "VBRK_EE2A2", "VBRK_EE4C2", - "VBRK_EE4A0", - "VBRK_ER1BEG3", - "VBRK_EE2BEG0", - "VBRK_EE4B1", - "VBRK_WL1END3", - "VBRK_EE4C1", - "VBRK_SE2A3", - "VBRK_EE4B2", - "VBRK_LH9", + "VBRK_EE2A3", + "VBRK_NE4C3", + "VBRK_MONITOR_P", + "VBRK_WL1END0", "VBRK_NE4C1", - "VBRK_NW4A1", - "VBRK_EE4BEG1", - "VBRK_EL1BEG3", - "VBRK_NW4END0", - "VBRK_SW4END0", - "VBRK_LH11", - "VBRK_LH2", - "VBRK_LH10", - "VBRK_WW4A0", - "VBRK_SW2A0", - "VBRK_SE4BEG1", - "VBRK_WW2A3", - "VBRK_NE4BEG3", - "VBRK_NE4BEG0", + "VBRK_LH3", + "VBRK_SE2A3", + "VBRK_EL1BEG1", + "VBRK_WW4C2", + "VBRK_NW2A2", "VBRK_EL1BEG0", - "VBRK_LH1", - "VBRK_EE2BEG2", - "VBRK_NW4END2", - "VBRK_WW2A2", - "VBRK_LH12", - "VBRK_WW4B2", - "VBRK_WW4B3", - "VBRK_WW2A1", - "VBRK_NW2A3", - "VBRK_EE4C3", - "VBRK_EE2BEG1", - "VBRK_LH8", + "VBRK_ER1BEG2", + "VBRK_LH6", + "VBRK_NW4A0", + "VBRK_LH2", "VBRK_ER1BEG1", "VBRK_EE4BEG0", - "VBRK_WW4A3", - "VBRK_EE4C0", - "VBRK_WW4END2", - "VBRK_ER1BEG0", - "VBRK_EE2A1", - "VBRK_ER1BEG2", - "VBRK_NW4A2", - "VBRK_EL1BEG1", - "VBRK_SW4END3", - "VBRK_LH3", - "VBRK_EE2A0", - "VBRK_NE2A3", - "VBRK_SE4BEG0", + "VBRK_EE2BEG0", "VBRK_EE2BEG3", - "VBRK_SW4END2", - "VBRK_SW2A3", - "VBRK_LH7", - "VBRK_WR1END2", - "VBRK_WW4C2", - "VBRK_NE4C3", - "VBRK_NE4C2", - "VBRK_LH5", - "VBRK_NE2A2", - "VBRK_WW4END1", - "VBRK_NE2A1", - "VBRK_SW2A1", - "VBRK_EE4B0", - "VBRK_NW4A3", - "VBRK_WR1END0", - "VBRK_NE2A0", - "VBRK_WW2END1", + "VBRK_WW4B2", "VBRK_NW4END1", - "VBRK_WL1END0", - "VBRK_EE4BEG2", - "VBRK_WW4END0", - "VBRK_WW4B0", - "VBRK_SE4BEG2", - "VBRK_EE4BEG3", - "VBRK_EE4A3", - "VBRK_WW4A1", - "VBRK_NE4C0", - "VBRK_WW4C3", - "VBRK_WW2END2", - "VBRK_WW4A2", - "VBRK_EE4B3", + "VBRK_SE4C0", + "VBRK_SE4C1", + "VBRK_WL1END1", + "VBRK_NW4A1", + "VBRK_EL1BEG2", "VBRK_SE2A2", - "VBRK_WW4END3" + "VBRK_SW2A2", + "VBRK_WW4B0", + "VBRK_NW4END2", + "VBRK_WW4END3", + "VBRK_WR1END1", + "VBRK_ER1BEG3", + "VBRK_WW2END2", + "VBRK_WR1END2", + "VBRK_EE4A3", + "VBRK_SE4BEG2", + "VBRK_WW4END0", + "VBRK_WW2A0", + "VBRK_NE2A1", + "VBRK_NE4C2", + "VBRK_SW4A0", + "VBRK_LH7", + "VBRK_SE4BEG3", + "VBRK_WR1END0" ], - "sites": [], - "pips": {}, - "tile_type": "VBRK" + "tile_type": "VBRK", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_VBRK_EXT.json b/artix7/tile_type_VBRK_EXT.json index f22f1f9..5ad85cc 100644 --- a/artix7/tile_type_VBRK_EXT.json +++ b/artix7/tile_type_VBRK_EXT.json @@ -1,99 +1,99 @@ { + "pips": {}, "wires": [ - "VBRK_EXT_FAN3", - "VBRK_EXT_LOGIC_OUTS_B11", - "VBRK_EXT_CTRL1", - "VBRK_EXT_IMUX4", - "VBRK_EXT_CTRL0", - "VBRK_EXT_IMUX2", - "VBRK_EXT_BYP2", - "VBRK_EXT_LOGIC_OUTS_B2", - "VBRK_EXT_IMUX33", - "VBRK_EXT_IMUX0", - "VBRK_EXT_LOGIC_OUTS_B6", - "VBRK_EXT_IMUX31", - "VBRK_EXT_IMUX10", "VBRK_EXT_LOGIC_OUTS_B9", - "VBRK_EXT_CLK0", + "VBRK_EXT_IMUX27", + "VBRK_EXT_CTRL1", + "VBRK_EXT_LOGIC_OUTS_B3", + "VBRK_EXT_LOGIC_OUTS_B10", + "VBRK_EXT_LOGIC_OUTS_B23", + "VBRK_EXT_IMUX3", + "VBRK_EXT_BYP2", + "VBRK_EXT_LOGIC_OUTS_B12", + "VBRK_EXT_IMUX21", + "VBRK_EXT_IMUX15", + "VBRK_EXT_IMUX25", + "VBRK_EXT_IMUX17", "VBRK_EXT_LOGIC_OUTS_B21", - "VBRK_EXT_LOGIC_OUTS_B16", - "VBRK_EXT_LOGIC_OUTS_B0", - "VBRK_EXT_IMUX20", - "VBRK_EXT_FAN4", + "VBRK_EXT_LOGIC_OUTS_B20", "VBRK_EXT_IMUX44", - "VBRK_EXT_LOGIC_OUTS_B7", + "VBRK_EXT_FAN7", + "VBRK_EXT_IMUX32", + "VBRK_EXT_IMUX6", + "VBRK_EXT_LOGIC_OUTS_B4", + "VBRK_EXT_LOGIC_OUTS_B2", + "VBRK_EXT_IMUX30", + "VBRK_EXT_IMUX23", + "VBRK_EXT_LOGIC_OUTS_B18", + "VBRK_EXT_IMUX43", + "VBRK_EXT_LOGIC_OUTS_B1", + "VBRK_EXT_IMUX12", + "VBRK_EXT_FAN4", + "VBRK_EXT_IMUX26", + "VBRK_EXT_IMUX4", + "VBRK_EXT_IMUX37", + "VBRK_EXT_FAN3", + "VBRK_EXT_IMUX41", + "VBRK_EXT_LOGIC_OUTS_B5", + "VBRK_EXT_LOGIC_OUTS_B17", "VBRK_EXT_IMUX46", "VBRK_EXT_IMUX7", - "VBRK_EXT_LOGIC_OUTS_B1", - "VBRK_EXT_LOGIC_OUTS_B19", - "VBRK_EXT_LOGIC_OUTS_B12", - "VBRK_EXT_IMUX35", - "VBRK_EXT_IMUX42", - "VBRK_EXT_LOGIC_OUTS_B8", - "VBRK_EXT_LOGIC_OUTS_B18", - "VBRK_EXT_LOGIC_OUTS_B13", - "VBRK_EXT_IMUX29", - "VBRK_EXT_IMUX18", - "VBRK_EXT_IMUX41", - "VBRK_EXT_IMUX8", - "VBRK_EXT_BYP5", - "VBRK_EXT_BYP0", - "VBRK_EXT_IMUX39", - "VBRK_EXT_IMUX45", - "VBRK_EXT_BYP6", - "VBRK_EXT_IMUX15", - "VBRK_EXT_IMUX30", - "VBRK_EXT_IMUX25", - "VBRK_EXT_BYP1", - "VBRK_EXT_BYP3", - "VBRK_EXT_IMUX32", + "VBRK_EXT_IMUX10", "VBRK_EXT_IMUX5", - "VBRK_EXT_FAN0", - "VBRK_EXT_IMUX40", - "VBRK_EXT_LOGIC_OUTS_B20", - "VBRK_EXT_BYP4", - "VBRK_EXT_IMUX47", - "VBRK_EXT_FAN6", - "VBRK_EXT_IMUX21", - "VBRK_EXT_LOGIC_OUTS_B23", - "VBRK_EXT_FAN2", - "VBRK_EXT_IMUX28", - "VBRK_EXT_LOGIC_OUTS_B17", - "VBRK_EXT_IMUX11", - "VBRK_EXT_IMUX26", - "VBRK_EXT_LOGIC_OUTS_B4", - "VBRK_EXT_IMUX24", - "VBRK_EXT_IMUX12", - "VBRK_EXT_IMUX19", - "VBRK_EXT_IMUX43", - "VBRK_EXT_LOGIC_OUTS_B5", - "VBRK_EXT_IMUX1", - "VBRK_EXT_LOGIC_OUTS_B3", - "VBRK_EXT_IMUX38", - "VBRK_EXT_IMUX13", - "VBRK_EXT_IMUX16", - "VBRK_EXT_LOGIC_OUTS_B14", - "VBRK_EXT_IMUX23", + "VBRK_EXT_CLK0", + "VBRK_EXT_BYP5", "VBRK_EXT_IMUX14", + "VBRK_EXT_IMUX8", + "VBRK_EXT_IMUX31", + "VBRK_EXT_IMUX35", + "VBRK_EXT_LOGIC_OUTS_B0", + "VBRK_EXT_FAN0", + "VBRK_EXT_IMUX1", + "VBRK_EXT_LOGIC_OUTS_B7", + "VBRK_EXT_BYP1", "VBRK_EXT_IMUX36", - "VBRK_EXT_LOGIC_OUTS_B10", - "VBRK_EXT_CLK1", - "VBRK_EXT_BYP7", - "VBRK_EXT_IMUX37", - "VBRK_EXT_IMUX34", - "VBRK_EXT_IMUX6", + "VBRK_EXT_LOGIC_OUTS_B22", + "VBRK_EXT_BYP6", + "VBRK_EXT_IMUX47", + "VBRK_EXT_IMUX16", + "VBRK_EXT_BYP3", + "VBRK_EXT_IMUX20", + "VBRK_EXT_BYP0", "VBRK_EXT_IMUX22", - "VBRK_EXT_FAN5", - "VBRK_EXT_IMUX27", - "VBRK_EXT_IMUX3", - "VBRK_EXT_FAN1", + "VBRK_EXT_IMUX42", + "VBRK_EXT_BYP7", + "VBRK_EXT_LOGIC_OUTS_B19", + "VBRK_EXT_IMUX29", + "VBRK_EXT_IMUX13", + "VBRK_EXT_IMUX40", + "VBRK_EXT_IMUX34", + "VBRK_EXT_IMUX0", + "VBRK_EXT_LOGIC_OUTS_B8", + "VBRK_EXT_CTRL0", + "VBRK_EXT_LOGIC_OUTS_B13", + "VBRK_EXT_IMUX39", + "VBRK_EXT_LOGIC_OUTS_B6", + "VBRK_EXT_IMUX18", + "VBRK_EXT_LOGIC_OUTS_B11", "VBRK_EXT_LOGIC_OUTS_B15", + "VBRK_EXT_LOGIC_OUTS_B16", "VBRK_EXT_IMUX9", - "VBRK_EXT_IMUX17", - "VBRK_EXT_FAN7", - "VBRK_EXT_LOGIC_OUTS_B22" + "VBRK_EXT_IMUX2", + "VBRK_EXT_CLK1", + "VBRK_EXT_FAN1", + "VBRK_EXT_BYP4", + "VBRK_EXT_FAN5", + "VBRK_EXT_IMUX38", + "VBRK_EXT_IMUX33", + "VBRK_EXT_LOGIC_OUTS_B14", + "VBRK_EXT_IMUX28", + "VBRK_EXT_IMUX45", + "VBRK_EXT_IMUX19", + "VBRK_EXT_IMUX24", + "VBRK_EXT_FAN6", + "VBRK_EXT_IMUX11", + "VBRK_EXT_FAN2" ], - "sites": [], - "pips": {}, - "tile_type": "VBRK_EXT" + "tile_type": "VBRK_EXT", + "sites": [] } \ No newline at end of file diff --git a/artix7/tile_type_VFRAME.json b/artix7/tile_type_VFRAME.json index 1896ce5..1e9a48b 100644 --- a/artix7/tile_type_VFRAME.json +++ b/artix7/tile_type_VFRAME.json @@ -1,229 +1,229 @@ { + "pips": {}, "wires": [ - "VFRAME_LOGIC_OUTS_B0", - "VFRAME_IMUX5", - "VFRAME_SW4A3", - "VFRAME_WW2A2", - "VFRAME_LOGIC_OUTS_B7", - "VFRAME_ER1BEG2", - "VFRAME_IMUX35", - "VFRAME_IMUX39", - "VFRAME_CLK0", - "VFRAME_WW4A0", - "VFRAME_FAN5", - "VFRAME_IMUX12", - "VFRAME_WR1END1", - "VFRAME_EE4B2", - "VFRAME_IMUX3", - "VFRAME_NW4END2", - "VFRAME_SE4BEG1", - "VFRAME_IMUX1", - "VFRAME_IMUX38", - "VFRAME_EE4C3", - "VFRAME_EE4BEG3", - "VFRAME_WW4B3", - "VFRAME_LOGIC_OUTS_B2", - "VFRAME_SE4C3", - "VFRAME_ER1BEG1", - "VFRAME_IMUX27", - "VFRAME_IMUX32", - "VFRAME_MONITOR_P", - "VFRAME_LOGIC_OUTS_B5", - "VFRAME_IMUX22", - "VFRAME_BYP7", - "VFRAME_IMUX29", - "VFRAME_IMUX34", - "VFRAME_BYP2", - "VFRAME_IMUX40", - "VFRAME_WW2A1", - "VFRAME_IMUX45", - "VFRAME_NW2A3", - "VFRAME_WR1END3", - "VFRAME_WW4C1", - "VFRAME_LH12", - "VFRAME_IMUX17", - "VFRAME_WW4B2", - "VFRAME_NE2A2", - "VFRAME_IMUX33", - "VFRAME_WW4END1", - "VFRAME_BYP3", - "VFRAME_LOGIC_OUTS_B18", - "VFRAME_EE4A2", - "VFRAME_LOGIC_OUTS_B23", - "VFRAME_SW4END2", - "VFRAME_EE2A1", - "VFRAME_IMUX15", - "VFRAME_NE4BEG1", - "VFRAME_IMUX20", - "VFRAME_IMUX6", - "VFRAME_LOGIC_OUTS_B16", - "VFRAME_IMUX25", - "VFRAME_WW4C3", - "VFRAME_IMUX13", - "VFRAME_SE2A0", - "VFRAME_SE2A3", - "VFRAME_NE2A1", - "VFRAME_LH11", - "VFRAME_SE4BEG3", - "VFRAME_IMUX8", - "VFRAME_EE4B3", - "VFRAME_NW4A3", - "VFRAME_EL1BEG0", - "VFRAME_LH4", - "VFRAME_IMUX11", - "VFRAME_LOGIC_OUTS_B1", - "VFRAME_IMUX24", - "VFRAME_NE2A3", - "VFRAME_LOGIC_OUTS_B9", - "VFRAME_IMUX7", - "VFRAME_EE4B1", - "VFRAME_EE2A0", - "VFRAME_IMUX9", - "VFRAME_NW2A2", - "VFRAME_LH5", - "VFRAME_LOGIC_OUTS_B8", - "VFRAME_SW4END1", - "VFRAME_IMUX26", - "VFRAME_NW4END3", - "VFRAME_WW4END2", - "VFRAME_SE2A1", - "VFRAME_IMUX2", - "VFRAME_BYP5", - "VFRAME_LOGIC_OUTS_B22", - "VFRAME_WL1END0", - "VFRAME_SW4END3", - "VFRAME_WW2END2", - "VFRAME_EE2A2", - "VFRAME_FAN3", - "VFRAME_SW2A3", - "VFRAME_LOGIC_OUTS_B13", - "VFRAME_ER1BEG0", - "VFRAME_IMUX44", - "VFRAME_LOGIC_OUTS_B6", - "VFRAME_IMUX42", - "VFRAME_FAN6", - "VFRAME_LH7", "VFRAME_EE4C0", - "VFRAME_IMUX21", - "VFRAME_EE2BEG3", + "VFRAME_FAN4", "VFRAME_LOGIC_OUTS_B17", - "VFRAME_CLK1", - "VFRAME_IMUX18", - "VFRAME_SE4C2", - "VFRAME_NE4BEG2", - "VFRAME_SW4A1", - "VFRAME_EE4BEG0", - "VFRAME_EL1BEG3", - "VFRAME_SE4BEG0", - "VFRAME_EE4A3", - "VFRAME_WR1END0", - "VFRAME_IMUX16", - "VFRAME_EE4BEG1", + "VFRAME_NE4C2", + "VFRAME_SE4C1", + "VFRAME_IMUX29", + "VFRAME_WW4C1", + "VFRAME_ER1BEG0", + "VFRAME_SW4END0", + "VFRAME_EL1BEG0", + "VFRAME_IMUX21", + "VFRAME_SW4END1", + "VFRAME_LH7", + "VFRAME_LH9", + "VFRAME_LOGIC_OUTS_B2", + "VFRAME_EE4C3", "VFRAME_IMUX19", - "VFRAME_EE4A1", - "VFRAME_BLOCK_OUTS_B3", - "VFRAME_LOGIC_OUTS_B15", - "VFRAME_MONITOR_N", - "VFRAME_CTRL1", "VFRAME_BLOCK_OUTS_B1", + "VFRAME_SW2A1", + "VFRAME_SE4BEG2", + "VFRAME_IMUX31", + "VFRAME_NE4BEG3", + "VFRAME_BLOCK_OUTS_B0", + "VFRAME_WL1END1", + "VFRAME_EE4B3", + "VFRAME_LOGIC_OUTS_B12", + "VFRAME_WW4C2", + "VFRAME_FAN7", + "VFRAME_EE4BEG1", + "VFRAME_IMUX8", + "VFRAME_ER1BEG1", + "VFRAME_IMUX5", + "VFRAME_MONITOR_P", + "VFRAME_WW2A0", + "VFRAME_LH6", + "VFRAME_SW4END2", + "VFRAME_EE2BEG0", + "VFRAME_IMUX44", + "VFRAME_WW4A3", + "VFRAME_EE4B0", + "VFRAME_FAN0", + "VFRAME_LOGIC_OUTS_B16", + "VFRAME_IMUX32", + "VFRAME_WL1END0", + "VFRAME_EE4B2", + "VFRAME_IMUX14", + "VFRAME_IMUX23", + "VFRAME_EE2A0", + "VFRAME_LOGIC_OUTS_B8", + "VFRAME_EE4A3", + "VFRAME_NW4END3", + "VFRAME_IMUX22", + "VFRAME_WL1END3", + "VFRAME_IMUX43", + "VFRAME_WW4END1", + "VFRAME_WR1END2", + "VFRAME_SE4C0", + "VFRAME_IMUX1", + "VFRAME_IMUX27", + "VFRAME_WW4A1", + "VFRAME_LH11", + "VFRAME_NE4C3", + "VFRAME_IMUX34", + "VFRAME_WW2A3", + "VFRAME_FAN2", + "VFRAME_LOGIC_OUTS_B11", + "VFRAME_WW4B3", + "VFRAME_LH10", + "VFRAME_IMUX46", + "VFRAME_SW4A2", + "VFRAME_ER1BEG2", + "VFRAME_LH2", + "VFRAME_SE2A3", "VFRAME_LOGIC_OUTS_B10", "VFRAME_WW4END3", - "VFRAME_EE4B0", - "VFRAME_EE2BEG2", - "VFRAME_LH10", - "VFRAME_LOGIC_OUTS_B14", - "VFRAME_NE4C2", - "VFRAME_IMUX23", - "VFRAME_LOGIC_OUTS_B3", - "VFRAME_FAN2", - "VFRAME_ER1BEG3", - "VFRAME_NW2A1", - "VFRAME_EE2BEG1", - "VFRAME_BLOCK_OUTS_B2", - "VFRAME_LOGIC_OUTS_B19", - "VFRAME_WL1END2", - "VFRAME_IMUX46", + "VFRAME_FAN3", + "VFRAME_SE2A1", "VFRAME_BYP4", - "VFRAME_IMUX36", - "VFRAME_SW4A2", - "VFRAME_FAN0", - "VFRAME_SE4C1", - "VFRAME_WW4C2", - "VFRAME_NE4BEG0", - "VFRAME_NW4END1", - "VFRAME_IMUX30", - "VFRAME_WW2A3", - "VFRAME_BYP1", - "VFRAME_IMUX28", - "VFRAME_WW4C0", - "VFRAME_IMUX37", - "VFRAME_SW4END0", - "VFRAME_EE4C2", - "VFRAME_SW2A0", - "VFRAME_SW4A0", - "VFRAME_NE4BEG3", - "VFRAME_LH9", - "VFRAME_WW2END0", - "VFRAME_NW4A0", - "VFRAME_EL1BEG1", - "VFRAME_NW4A2", - "VFRAME_LOGIC_OUTS_B4", - "VFRAME_IMUX0", - "VFRAME_WW4B0", - "VFRAME_WL1END3", + "VFRAME_SE2A0", "VFRAME_IMUX4", - "VFRAME_IMUX31", - "VFRAME_IMUX14", - "VFRAME_LOGIC_OUTS_B11", - "VFRAME_EE4C1", - "VFRAME_LH2", - "VFRAME_WR1END2", - "VFRAME_LH6", - "VFRAME_SW2A2", - "VFRAME_IMUX41", - "VFRAME_IMUX47", - "VFRAME_NW4END0", - "VFRAME_BLOCK_OUTS_B0", - "VFRAME_IMUX43", + "VFRAME_BLOCK_OUTS_B3", + "VFRAME_IMUX33", + "VFRAME_IMUX26", "VFRAME_NE4C1", - "VFRAME_SW2A1", - "VFRAME_NW2A0", - "VFRAME_NE4C0", - "VFRAME_SE2A2", - "VFRAME_EE2A3", - "VFRAME_WW4END0", - "VFRAME_NE2A0", - "VFRAME_EL1BEG2", - "VFRAME_FAN1", - "VFRAME_WW4A1", - "VFRAME_LH3", - "VFRAME_NW4A1", - "VFRAME_WW2END1", - "VFRAME_LH1", - "VFRAME_EE4BEG2", - "VFRAME_SE4C0", - "VFRAME_WW4B1", - "VFRAME_LOGIC_OUTS_B20", - "VFRAME_NE4C3", - "VFRAME_BYP0", "VFRAME_WW2END3", - "VFRAME_WW4A3", - "VFRAME_SE4BEG2", - "VFRAME_LH8", - "VFRAME_LOGIC_OUTS_B12", - "VFRAME_IMUX10", - "VFRAME_CTRL0", - "VFRAME_EE2BEG0", - "VFRAME_WL1END1", + "VFRAME_WW4C0", "VFRAME_LOGIC_OUTS_B21", + "VFRAME_SW2A3", + "VFRAME_EE2A3", + "VFRAME_BYP3", + "VFRAME_NW4END0", + "VFRAME_EE4C1", + "VFRAME_LOGIC_OUTS_B19", + "VFRAME_LH3", + "VFRAME_WW2A1", + "VFRAME_LH1", + "VFRAME_SE4BEG1", + "VFRAME_WW2END2", + "VFRAME_NW4A1", + "VFRAME_EE4A1", + "VFRAME_NW2A3", + "VFRAME_LH12", + "VFRAME_SE4C3", + "VFRAME_NE4BEG2", + "VFRAME_IMUX15", + "VFRAME_IMUX25", + "VFRAME_WW4B2", + "VFRAME_NE2A2", + "VFRAME_CLK1", + "VFRAME_NE2A0", + "VFRAME_IMUX38", + "VFRAME_WW4END0", + "VFRAME_SW2A2", + "VFRAME_EE2BEG2", + "VFRAME_FAN5", + "VFRAME_BYP2", + "VFRAME_NW4A0", + "VFRAME_LOGIC_OUTS_B15", + "VFRAME_IMUX41", + "VFRAME_NE4BEG0", + "VFRAME_BLOCK_OUTS_B2", + "VFRAME_EL1BEG1", + "VFRAME_NW4END1", + "VFRAME_NW2A2", + "VFRAME_IMUX17", "VFRAME_BYP6", - "VFRAME_WW2A0", + "VFRAME_EE2A2", + "VFRAME_WR1END3", + "VFRAME_SW4END3", + "VFRAME_LOGIC_OUTS_B20", + "VFRAME_FAN1", + "VFRAME_IMUX10", + "VFRAME_NW4END2", + "VFRAME_SE4BEG3", + "VFRAME_IMUX0", + "VFRAME_LOGIC_OUTS_B3", + "VFRAME_LOGIC_OUTS_B13", + "VFRAME_IMUX40", + "VFRAME_LOGIC_OUTS_B6", + "VFRAME_SE4BEG0", + "VFRAME_IMUX20", + "VFRAME_LOGIC_OUTS_B0", + "VFRAME_NE4BEG1", + "VFRAME_BYP1", + "VFRAME_BYP5", + "VFRAME_WW4B0", + "VFRAME_IMUX39", + "VFRAME_IMUX47", + "VFRAME_ER1BEG3", + "VFRAME_LOGIC_OUTS_B5", + "VFRAME_IMUX13", + "VFRAME_WW4C3", + "VFRAME_LOGIC_OUTS_B4", + "VFRAME_LOGIC_OUTS_B23", + "VFRAME_NE2A1", + "VFRAME_IMUX37", + "VFRAME_EE4BEG2", + "VFRAME_EE4BEG3", + "VFRAME_BYP0", + "VFRAME_WR1END0", + "VFRAME_EE2BEG3", + "VFRAME_LOGIC_OUTS_B7", + "VFRAME_LOGIC_OUTS_B18", + "VFRAME_CTRL0", + "VFRAME_SW4A0", + "VFRAME_EE4B1", + "VFRAME_SE4C2", + "VFRAME_WW2END0", + "VFRAME_EE4BEG0", + "VFRAME_EE2A1", + "VFRAME_IMUX36", + "VFRAME_WL1END2", + "VFRAME_SW4A1", + "VFRAME_IMUX2", + "VFRAME_CTRL1", + "VFRAME_NW2A0", + "VFRAME_BYP7", + "VFRAME_NW4A2", + "VFRAME_EE2BEG1", + "VFRAME_WW4A2", + "VFRAME_EL1BEG2", + "VFRAME_WW4A0", + "VFRAME_WW2END1", + "VFRAME_IMUX35", "VFRAME_EE4A0", - "VFRAME_FAN4", - "VFRAME_FAN7", - "VFRAME_WW4A2" + "VFRAME_WW2A2", + "VFRAME_WW4B1", + "VFRAME_LH4", + "VFRAME_IMUX42", + "VFRAME_NE4C0", + "VFRAME_MONITOR_N", + "VFRAME_SW2A0", + "VFRAME_IMUX45", + "VFRAME_FAN6", + "VFRAME_LOGIC_OUTS_B1", + "VFRAME_EE4A2", + "VFRAME_IMUX3", + "VFRAME_LOGIC_OUTS_B22", + "VFRAME_CLK0", + "VFRAME_LOGIC_OUTS_B9", + "VFRAME_NW4A3", + "VFRAME_EE4C2", + "VFRAME_IMUX30", + "VFRAME_LOGIC_OUTS_B14", + "VFRAME_IMUX12", + "VFRAME_IMUX16", + "VFRAME_IMUX28", + "VFRAME_NW2A1", + "VFRAME_WW4END2", + "VFRAME_IMUX11", + "VFRAME_IMUX9", + "VFRAME_IMUX24", + "VFRAME_WR1END1", + "VFRAME_EL1BEG3", + "VFRAME_IMUX7", + "VFRAME_IMUX18", + "VFRAME_SW4A3", + "VFRAME_LH5", + "VFRAME_NE2A3", + "VFRAME_SE2A2", + "VFRAME_IMUX6", + "VFRAME_LH8" ], - "sites": [], - "pips": {}, - "tile_type": "VFRAME" + "tile_type": "VFRAME", + "sites": [] } \ No newline at end of file diff --git a/artix7/tileconn.json b/artix7/tileconn.json index 82ed013..6728fc9 100644 --- a/artix7/tileconn.json +++ b/artix7/tileconn.json @@ -1,72070 +1,4210 @@ [ { - "wire_pairs": [ - [ - "BRKH_DSP_BCIN8", - "DSP_0_BCIN8" - ], - [ - "BRKH_DSP_ACIN4", - "DSP_0_ACIN4" - ], - [ - "BRKH_DSP_BCIN12", - "DSP_0_BCIN12" - ], - [ - "BRKH_DSP_ACIN24", - "DSP_0_ACIN24" - ], - [ - "BRKH_DSP_ACIN11", - "DSP_0_ACIN11" - ], - [ - "BRKH_DSP_ACIN17", - "DSP_0_ACIN17" - ], - [ - "BRKH_DSP_PCIN47", - "DSP_0_PCIN47" - ], - [ - "BRKH_DSP_BCIN4", - "DSP_0_BCIN4" - ], - [ - "BRKH_DSP_ACIN21", - "DSP_0_ACIN21" - ], - [ - "BRKH_DSP_ACIN6", - "DSP_0_ACIN6" - ], - [ - "BRKH_DSP_PCIN4", - "DSP_0_PCIN4" - ], - [ - "BRKH_DSP_PCIN35", - "DSP_0_PCIN35" - ], - [ - "BRKH_DSP_PCIN16", - "DSP_0_PCIN16" - ], - [ - "BRKH_DSP_PCIN1", - "DSP_0_PCIN1" - ], - [ - "BRKH_DSP_BCIN9", - "DSP_0_BCIN9" - ], - [ - "BRKH_DSP_PCIN44", - "DSP_0_PCIN44" - ], - [ - "BRKH_DSP_PCIN31", - "DSP_0_PCIN31" - ], - [ - "BRKH_DSP_ACIN22", - "DSP_0_ACIN22" - ], - [ - "BRKH_DSP_ACIN3", - "DSP_0_ACIN3" - ], - [ - "BRKH_DSP_PCIN19", - "DSP_0_PCIN19" - ], - [ - "BRKH_DSP_ACIN5", - "DSP_0_ACIN5" - ], - [ - "BRKH_DSP_PCIN6", - "DSP_0_PCIN6" - ], - [ - "BRKH_DSP_ACIN13", - "DSP_0_ACIN13" - ], - [ - "BRKH_DSP_PCIN21", - "DSP_0_PCIN21" - ], - [ - "BRKH_DSP_MULTSIGNIN", - "DSP_0_MULTSIGNIN" - ], - [ - "BRKH_DSP_ACIN19", - "DSP_0_ACIN19" - ], - [ - "BRKH_DSP_PCIN7", - "DSP_0_PCIN7" - ], - [ - "BRKH_DSP_ACIN26", - "DSP_0_ACIN26" - ], - [ - "BRKH_DSP_BCIN15", - "DSP_0_BCIN15" - ], - [ - "BRKH_DSP_BCIN2", - "DSP_0_BCIN2" - ], - [ - "BRKH_DSP_PCIN24", - "DSP_0_PCIN24" - ], - [ - "BRKH_DSP_PCIN28", - "DSP_0_PCIN28" - ], - [ - "BRKH_DSP_PCIN11", - "DSP_0_PCIN11" - ], - [ - "BRKH_DSP_ACIN1", - "DSP_0_ACIN1" - ], - [ - "BRKH_DSP_BCIN16", - "DSP_0_BCIN16" - ], - [ - "BRKH_DSP_PCIN32", - "DSP_0_PCIN32" - ], - [ - "BRKH_DSP_ACIN8", - "DSP_0_ACIN8" - ], - [ - "BRKH_DSP_PCIN22", - "DSP_0_PCIN22" - ], - [ - "BRKH_DSP_PCIN12", - "DSP_0_PCIN12" - ], - [ - "BRKH_DSP_BCIN1", - "DSP_0_BCIN1" - ], - [ - "BRKH_DSP_BCIN13", - "DSP_0_BCIN13" - ], - [ - "BRKH_DSP_PCIN34", - "DSP_0_PCIN34" - ], - [ - "BRKH_DSP_PCIN37", - "DSP_0_PCIN37" - ], - [ - "BRKH_DSP_BCIN17", - "DSP_0_BCIN17" - ], - [ - "BRKH_DSP_ACIN28", - "DSP_0_ACIN28" - ], - [ - "BRKH_DSP_ACIN16", - "DSP_0_ACIN16" - ], - [ - "BRKH_DSP_BCIN7", - "DSP_0_BCIN7" - ], - [ - "BRKH_DSP_PCIN13", - "DSP_0_PCIN13" - ], - [ - "BRKH_DSP_PCIN9", - "DSP_0_PCIN9" - ], - [ - "BRKH_DSP_PCIN15", - "DSP_0_PCIN15" - ], - [ - "BRKH_DSP_PCIN40", - "DSP_0_PCIN40" - ], - [ - "BRKH_DSP_PCIN25", - "DSP_0_PCIN25" - ], - [ - "BRKH_DSP_PCIN33", - "DSP_0_PCIN33" - ], - [ - "BRKH_DSP_ACIN9", - "DSP_0_ACIN9" - ], - [ - "BRKH_DSP_ACIN27", - "DSP_0_ACIN27" - ], - [ - "BRKH_DSP_PCIN45", - "DSP_0_PCIN45" - ], - [ - "BRKH_DSP_ACIN15", - "DSP_0_ACIN15" - ], - [ - "BRKH_DSP_ACIN20", - "DSP_0_ACIN20" - ], - [ - "BRKH_DSP_PCIN5", - "DSP_0_PCIN5" - ], - [ - "BRKH_DSP_ACIN23", - "DSP_0_ACIN23" - ], - [ - "BRKH_DSP_BCIN6", - "DSP_0_BCIN6" - ], - [ - "BRKH_DSP_PCIN27", - "DSP_0_PCIN27" - ], - [ - "BRKH_DSP_PCIN10", - "DSP_0_PCIN10" - ], - [ - "BRKH_DSP_PCIN0", - "DSP_0_PCIN0" - ], - [ - "BRKH_DSP_BCIN5", - "DSP_0_BCIN5" - ], - [ - "BRKH_DSP_PCIN17", - "DSP_0_PCIN17" - ], - [ - "BRKH_DSP_PCIN36", - "DSP_0_PCIN36" - ], - [ - "BRKH_DSP_ACIN14", - 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"CLK_HROW_WR1END1_5", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4A3_5", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_IMUX32_5", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NE2A2_5", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_NW4END1_5", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_IMUX27_5", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_IMUX25_5", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_IMUX28_5", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX46_5", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_ER1BEG2_5", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_LH2_5", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EE4BEG3_5", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_EE4BEG2_5", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW4C1_5", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_SW4A3_5", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_SW4END1_5", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EL1BEG0_5", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_IMUX31_5", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_FAN2_5", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_SE4C1_5", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX2_5", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WW4END1_5", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_NE2A1_5", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_WW4END3_5", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_IMUX36_5", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_FAN1_5", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_EE4C0_5", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_LH3_5", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_WW4A1_5", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_BYP4_5", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_IMUX41_5", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_IMUX10_5", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_EE4BEG1_5", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_SE2A2_5", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2A1_5", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX21_5", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_SW4END3_5", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EE4B2_5", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_SW2A0_5", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH6_5", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_WW2A2_5", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_EE4BEG0_5", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_EE2A3_5", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_WW4B3_5", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_LH9_5", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NE2A0_5", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_WR1END2_5", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_IMUX23_5", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_WW4END0_5", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_SE2A0_5", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_SE4BEG2_5", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_EL1BEG2_5", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_EE2A1_5", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_CTRL1_5", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW2END0_5", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH4_5", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_IMUX47_5", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_IMUX16_5", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX4_5", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX8_5", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_CLK0_5", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_IMUX26_5", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_IMUX15_5", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_EE2A2_5", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_IMUX5_5", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX22_5", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_SW4A1_5", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_EE4C3_5", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_FAN3_5", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_ER1BEG1_5", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WR1END3_5", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_WW4A2_5", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NW4A2_5", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_SW4END0_5", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EE4C1_5", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX9_5", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_NE4C0_5", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX3_5", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_SW4A0_5", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_LH5_5", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_LH12_5", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WL1END0_5", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_NE4BEG0_5", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_WL1END3_5", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_EE2BEG1_5", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_LH10_5", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_IMUX38_5", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX39_5", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_NE2A3_5", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_IMUX7_5", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE2BEG0_5", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_IMUX1_5", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_NE4C3_5", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_SE4BEG0_5", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_ER1BEG0_5", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SE4BEG3_5", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_SW4A2_5", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX6_5", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_LH11_5", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_BYP0_5", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_FAN5_5", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_NE4C1_5", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW4B1_5", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_NW4A3_5", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_EL1BEG1_5", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_NE4BEG2_5", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_EE4B1_5", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX20_5", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_NW4END3_5", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_IMUX12_5", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_EE2BEG3_5", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_EE4C2_5", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_BYP7_5", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WW2END2_5", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_IMUX11_5", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SE2A3_5", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_SW4END2_5", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_IMUX24_5", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_SE2A1_5", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_LH1_5", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_NW4END2_5", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_IMUX29_5", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX37_5", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_WW2A0_5", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW4C0_5", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_WW4A0_5", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_SW2A1_5", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_SE4C3_5", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE4B0_5", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_IMUX44_5", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_SW2A2_5", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW4B0_5", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW4C2_5", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_EE4A0_5", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_FAN4_5", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_EE4A1_5", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_FAN0_5", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_LH8_5", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_IMUX13_5", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_IMUX17_5", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_IMUX43_5", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_WL1END2_5", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_NE4BEG3_5", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_NW4A0_5", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX42_5", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_IMUX0_5", - "INT_INTERFACE_IMUX0" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -2 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_LH1_2", - "VBRK_LH1" - ], - [ - "CMT_TOP_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_LH3_2", - "VBRK_LH3" - ], - [ - "CMT_TOP_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_SE4BEG3_2", - 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"CLK_BUFG_REBUF_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_BUFG_REBUF_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_BUFG_REBUF_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_BUFG_REBUF_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_BUFG_REBUF_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_BUFG_REBUF_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_BUFG_REBUF_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_BUFG_REBUF_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_BUFG_REBUF_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_BUFG_REBUF_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_BUFG_REBUF_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_BUFG_REBUF_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_BUFG_REBUF_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_BUFG_REBUF_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_BUFG_REBUF_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_REBUF_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - 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"INT_INTERFACE_EE4A3" - ], - [ - "CLK_BUFG_REBUF_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_BUFG_REBUF_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_BUFG_REBUF_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_BUFG_REBUF_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_BUFG_REBUF_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_BUFG_REBUF_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_BUFG_REBUF_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_BUFG_REBUF_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_BUFG_REBUF_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_BUFG_REBUF_WW2END2_1", - "INT_INTERFACE_WW2END2" - ] - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_LH10_4", - "VBRK_LH10" - ], - [ - "CLK_HROW_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_LH5_4", - "VBRK_LH5" - ], - [ - "CLK_HROW_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_LH2_4", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SE2A1_4", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH9_4", - "VBRK_LH9" - ], - [ - "CLK_HROW_LH6_4", - "VBRK_LH6" - ], - [ - "CLK_HROW_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_LH7_4", - "VBRK_LH7" - ], - [ - "CLK_HROW_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH1_4", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH4_4", - "VBRK_LH4" - ], - [ - "CLK_HROW_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_LH3_4", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4A0_4", - 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"VBRK_LH8" - ], - [ - "CLK_HROW_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_EE4C0_4", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE2A0_4", - "VBRK_NE2A0" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CLBLL_WW4B3", - "WW4B3" - ], - [ - "CLBLL_NW4END3", - "NW6END3" - ], - [ - "CLBLL_WL1END3", - "WL1END3" - ], - [ - "CLBLL_EE4B3", - "EE4B3" - ], - [ - "CLBLL_LOGIC_OUTS18", - "LOGIC_OUTS18" - ], - [ - "CLBLL_WL1END2", - "WL1END2" - ], - [ - "CLBLL_SE4C3", - "SE6E3" - ], - [ - "CLBLL_SW4A3", - "SW6A3" - ], - [ - "CLBLL_IMUX46", - "IMUX46" - ], - [ - "CLBLL_BYP5", - "BYP5" - ], - [ - "CLBLL_EE4B2", - "EE4B2" - ], - [ - "CLBLL_WW4B1", - "WW4B1" - ], - [ - "CLBLL_LH7", - "LH7" - ], - [ - "CLBLL_IMUX11", - "IMUX11" - ], - [ - "CLBLL_NE4C1", - "NE6E1" - ], - [ - "CLBLL_IMUX13", - "IMUX13" - ], - [ - "CLBLL_LH12", - "LH12" - ], - [ - "CLBLL_IMUX8", - "IMUX8" - ], - [ - "CLBLL_IMUX0", - "IMUX0" - ], - [ - "CLBLL_IMUX32", - "IMUX32" - ], - [ - "CLBLL_IMUX10", - "IMUX10" - ], - [ - "CLBLL_IMUX9", - "IMUX9" - ], - [ - "CLBLL_SW2A3", - "SW2END3" - ], - [ - "CLBLL_WW4END0", - "WW4END0" - ], - [ - "CLBLL_BYP0", - "BYP0" - ], - [ - "CLBLL_LH11", - "LH11" - ], - [ - "CLBLL_IMUX39", - "IMUX39" - ], - [ - "CLBLL_EE4C2", - "EE4C2" - ], - [ - "CLBLL_ER1BEG3", - "ER1BEG3" - ], - [ - "CLBLL_CLK0", - "CLK0" - ], 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- ], - [ - "CLBLL_SE4C1", - "SE6E1" - ], - [ - "CLBLL_IMUX42", - "IMUX42" - ], - [ - "CLBLL_SE4C2", - "SE6E2" - ], - [ - "CLBLL_WR1END0", - "WR1END0" - ], - [ - "CLBLL_IMUX4", - "IMUX4" - ], - [ - "CLBLL_FAN2", - "FAN2" - ], - [ - "CLBLL_SE2A2", - "SE2A2" - ], - [ - "CLBLL_LOGIC_OUTS14", - "LOGIC_OUTS14" - ], - [ - "CLBLL_IMUX26", - "IMUX26" - ], - [ - "CLBLL_WW4END2", - "WW4END2" - ], - [ - "CLBLL_NE4BEG1", - "NE6BEG1" - ], - [ - "CLBLL_IMUX12", - "IMUX12" - ], - [ - "CLBLL_SE2A0", - "SE2A0" - ], - [ - "CLBLL_EE4B1", - "EE4B1" - ], - [ - "CLBLL_IMUX21", - "IMUX21" - ], - [ - "CLBLL_LOGIC_OUTS23", - "LOGIC_OUTS23" - ], - [ - "CLBLL_LOGIC_OUTS17", - "LOGIC_OUTS17" - ], - [ - "CLBLL_IMUX22", - "IMUX22" - ], - [ - "CLBLL_LOGIC_OUTS3", - "LOGIC_OUTS3" - ], - [ - "CLBLL_LH10", - "LH10" - ], - [ - "CLBLL_EE4C3", - "EE4C3" - ], - [ - "CLBLL_EE2BEG2", - "EE2BEG2" - ], - [ - "CLBLL_SW4END1", - "SW6END1" - ], - [ - "CLBLL_NW2A2", - "NW2END2" - ], - [ - "CLBLL_LH9", - "LH9" - ], - [ - "CLBLL_SE2A3", - "SE2A3" - ], - [ - "CLBLL_EL1BEG2", - "EL1BEG2" - ], - [ - "CLBLL_SW2A2", - "SW2END2" - ], - [ - "CLBLL_WW4END1", - "WW4END1" - ], - [ - "CLBLL_NE4C3", - "NE6E3" - ], - [ - "CLBLL_NW4END0", - "NW6END0" - ], - [ - "CLBLL_CTRL1", - "CTRL1" - ], - [ - "CLBLL_CTRL0", - "CTRL0" - ], - [ - "CLBLL_FAN7", - "FAN7" - ], - [ - "CLBLL_EE4A2", - "EE4A2" - ], - [ - "CLBLL_ER1BEG1", - "ER1BEG1" - ], - [ - "CLBLL_IMUX27", - "IMUX27" - ], - [ - "CLBLL_LOGIC_OUTS6", - "LOGIC_OUTS6" - ], - [ - "CLBLL_FAN4", - "FAN4" - ], - [ - "CLBLL_IMUX18", - "IMUX18" - ], - [ - "CLBLL_IMUX3", - "IMUX3" - ], - [ - "CLBLL_BYP3", - "BYP3" - ], - [ - "CLBLL_WW4B0", - "WW4B0" - ], - [ - "CLBLL_WL1END1", - "WL1END1" - ], - [ - "CLBLL_EE2BEG1", - "EE2BEG1" - ], - [ - "CLBLL_LOGIC_OUTS13", - "LOGIC_OUTS13" - ], - [ - "CLBLL_LOGIC_OUTS9", - "LOGIC_OUTS9" - ], - [ - "CLBLL_EE2A0", - "EE2A0" - ], - [ - "CLBLL_LH4", - "LH4" - ], - [ - "CLBLL_BYP1", - "BYP1" - ], - [ - "CLBLL_WW4C3", - "WW4C3" - ], - [ - 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- ], - [ - "CLBLL_MONITOR_P", - "MONITOR_P" - ], - [ - "CLBLL_NE2A3", - "NE2A3" - ], - [ - "CLBLL_IMUX29", - "IMUX29" - ], - [ - "CLBLL_IMUX41", - "IMUX41" - ], - [ - "CLBLL_LOGIC_OUTS11", - "LOGIC_OUTS11" - ], - [ - "CLBLL_WW2END1", - "WW2END1" - ], - [ - "CLBLL_IMUX7", - "IMUX7" - ], - [ - "CLBLL_SE4BEG3", - "SE6BEG3" - ], - [ - "CLBLL_BYP7", - "BYP7" - ], - [ - "CLBLL_WW4A1", - "WW4A1" - ], - [ - "CLBLL_LOGIC_OUTS16", - "LOGIC_OUTS16" - ], - [ - "CLBLL_WW4C2", - "WW4C2" - ], - [ - "CLBLL_IMUX43", - "IMUX43" - ], - [ - "CLBLL_LH1", - "LH1" - ], - [ - "CLBLL_WW4A3", - "WW4A3" - ], - [ - "CLBLL_NW4END2", - "NW6END2" - ], - [ - "CLBLL_NE4BEG0", - "NE6BEG0" - ], - [ - "CLBLL_IMUX44", - "IMUX44" - ], - [ - "CLBLL_EE2BEG0", - "EE2BEG0" - ], - [ - "CLBLL_NW2A0", - "NW2END0" - ], - [ - "CLBLL_NE4BEG2", - "NE6BEG2" - ], - [ - "CLBLL_BYP2", - "BYP2" - ], - [ - "CLBLL_BYP4", - "BYP4" - ], - [ - "CLBLL_IMUX31", - "IMUX31" - ], - [ - "CLBLL_IMUX30", - "IMUX30" - ], - [ - "CLBLL_LOGIC_OUTS19", - "LOGIC_OUTS19" - ], - [ - "CLBLL_EE4B0", - "EE4B0" - ], - [ - "CLBLL_IMUX28", - "IMUX28" - ], - [ - "CLBLL_CLK1", - "CLK1" - ], - [ - "CLBLL_WL1END0", - "WL1END0" - ], - [ - "CLBLL_WR1END1", - "WR1END1" - ], - [ - "CLBLL_NE4C2", - "NE6E2" - ], - [ - "CLBLL_EE2BEG3", - "EE2BEG3" - ], - [ - "CLBLL_LOGIC_OUTS15", - "LOGIC_OUTS15" - ], - [ - "CLBLL_EE4BEG0", - "EE4BEG0" - ], - [ - "CLBLL_FAN6", - "FAN6" - ], - [ - "CLBLL_FAN1", - "FAN1" - ], - [ - "CLBLL_SW4END0", - "SW6END0" - ], - [ - "CLBLL_LH8", - "LH8" - ], - [ - "CLBLL_IMUX17", - "IMUX17" - ], - [ - "CLBLL_NW4A1", - "NW6A1" - ], - [ - "CLBLL_SE4C0", - "SE6E0" - ], - [ - "CLBLL_WR1END2", - "WR1END2" - ], - [ - "CLBLL_NW4A0", - "NW6A0" - ], - [ - "CLBLL_IMUX20", - "IMUX20" - ], - [ - "CLBLL_EL1BEG1", - "EL1BEG1" - ], - [ - "CLBLL_IMUX5", - "IMUX5" - ], - [ - "CLBLL_IMUX14", - "IMUX14" - ], - [ - "CLBLL_NE2A2", - "NE2A2" - ], - [ - "CLBLL_EE2A2", - "EE2A2" - ], - [ - "CLBLL_SW4A2", - "SW6A2" - ], - [ - "CLBLL_WW4C1", - "WW4C1" - ], - [ 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"CMT_FIFO_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CMT_FIFO_L_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CMT_FIFO_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CMT_FIFO_L_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CMT_FIFO_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CMT_FIFO_L_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CMT_FIFO_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "CMT_FIFO_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS1_0", - "INT_INTERFACE_LOGIC_OUTS_L_B1" - ], - [ - "CMT_FIFO_L_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CMT_FIFO_L_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CMT_FIFO_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CMT_FIFO_L_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CMT_FIFO_L_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CMT_FIFO_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CMT_FIFO_L_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CMT_FIFO_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - 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], - [ - "CLBLL_LH5", - "VBRK_LH5" - ], - [ - "CLBLL_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLBLL_LH10", - "VBRK_LH10" - ], - [ - "CLBLL_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLBLL_WW2END1", - "VBRK_WW2END1" - ] - ], - "tile_types": [ - "CLBLL_R", - "VBRK" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_LH7_0", - "VBRK_LH7" - ], - [ - "CLK_HROW_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_LH12_0", - "VBRK_LH12" - ], - [ - "CLK_HROW_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_LH9_0", - "VBRK_LH9" - ], - [ - "CLK_HROW_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_LH6_0", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_LH2_0", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_NW4A1_0", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH10_0", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_HROW_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH5_0", - "VBRK_LH5" - ], - [ - "CLK_HROW_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_LH1_0", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_LH11_0", - "VBRK_LH11" - ], - [ - "CLK_HROW_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_LH8_0", - "VBRK_LH8" - ], - [ - "CLK_HROW_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4A2_0", - "VBRK_EE4A2" - ] - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "VBRK" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "PCIE_IMUX35_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT35" - ], - [ - "PCIE_IMUX25_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT25" - ], - [ - "PCIE_FAN5_L_15", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_LH8_15", - "INT_INTERFACE_LH8" - ], - [ - "PCIE_ER1BEG2_15", - "INT_INTERFACE_ER1BEG2" - ], - [ - "PCIE_WW2END2_15", - "INT_INTERFACE_WW2END2" - ], - [ - "PCIE_IMUX4_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT4" - ], - [ - "PCIE_IMUX8_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT8" - ], - [ - "PCIE_FAN2_L_15", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_EE4A0_15", - "INT_INTERFACE_EE4A0" - ], - [ - "PCIE_WW4B1_15", - "INT_INTERFACE_WW4B1" - ], - [ - "PCIE_SW4A2_15", - "INT_INTERFACE_SW4A2" - ], - [ - "PCIE_NW2A1_15", - "INT_INTERFACE_NW2A1" - ], - [ - "PCIE_WW2END1_15", - "INT_INTERFACE_WW2END1" - ], - [ - "PCIE_NW4A1_15", - "INT_INTERFACE_NW4A1" - ], - [ - "PCIE_SW4A1_15", - "INT_INTERFACE_SW4A1" - ], - [ - "PCIE_BYP1_L_15", - "INT_INTERFACE_BYP1" - ], - [ - "PCIE_SW2A3_15", - "INT_INTERFACE_SW2A3" - ], - [ - "PCIE_IMUX10_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT10" - ], - [ - "PCIE_NE4BEG3_15", - "INT_INTERFACE_NE4BEG3" - ], - [ - "PCIE_LOGIC_OUTS_B11_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "PCIE_LOGIC_OUTS_B1_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B1" - ], - [ - "PCIE_MONITOR_P_15", - "INT_INTERFACE_MONITOR_P" - ], - [ - "PCIE_WR1END2_15", - "INT_INTERFACE_WR1END2" - ], - [ - "PCIE_LOGIC_OUTS_B16_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B16" - ], - [ - "PCIE_LOGIC_OUTS_B19_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B19" - ], - [ - "PCIE_EL1BEG2_15", - "INT_INTERFACE_EL1BEG2" - ], - [ - "PCIE_IMUX43_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT43" - ], - [ - "PCIE_EE2A0_15", - "INT_INTERFACE_EE2A0" - ], - [ - "PCIE_SW4END3_15", - "INT_INTERFACE_SW4END3" - ], - [ - "PCIE_LOGIC_OUTS_B8_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B8" - ], - [ - "PCIE_LH3_15", - "INT_INTERFACE_LH3" - ], - [ - "PCIE_EE4A3_15", - "INT_INTERFACE_EE4A3" - ], - [ - "PCIE_NE4BEG1_15", - "INT_INTERFACE_NE4BEG1" - ], - [ - "PCIE_EE4A2_15", - "INT_INTERFACE_EE4A2" - ], - [ - "PCIE_SW4A0_15", - "INT_INTERFACE_SW4A0" - ], - [ - "PCIE_NE2A1_15", - "INT_INTERFACE_NE2A1" - ], - [ - "PCIE_BYP6_L_15", - "INT_INTERFACE_BYP6" - ], - [ - "PCIE_NW4END2_15", - "INT_INTERFACE_NW4END2" - ], - [ - "PCIE_LH4_15", - "INT_INTERFACE_LH4" - ], - [ - "PCIE_EE4C1_15", - "INT_INTERFACE_EE4C1" - ], - [ - "PCIE_IMUX37_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT37" - ], - [ - "PCIE_WR1END1_15", - "INT_INTERFACE_WR1END1" - ], - [ - "PCIE_BYP7_L_15", - "INT_INTERFACE_BYP7" - ], - [ - "PCIE_WW4A2_15", - "INT_INTERFACE_WW4A2" - ], - [ - "PCIE_IMUX30_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT30" - ], - [ - "PCIE_NE2A2_15", - "INT_INTERFACE_NE2A2" - ], - [ - "PCIE_IMUX9_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT9" - ], - [ - "PCIE_NE2A3_15", - "INT_INTERFACE_NE2A3" - ], - [ - "PCIE_IMUX28_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT28" - ], - [ - "PCIE_WL1END3_15", - "INT_INTERFACE_WL1END3" - ], - [ - "PCIE_LOGIC_OUTS_B7_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B7" - ], - [ - "PCIE_LOGIC_OUTS_B10_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B10" - ], - [ - "PCIE_NE4C2_15", - "INT_INTERFACE_NE4C2" - ], - [ - "PCIE_SW4END1_15", - "INT_INTERFACE_SW4END1" - ], - [ - "PCIE_IMUX12_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT12" - ], - [ - "PCIE_LOGIC_OUTS_B17_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B17" - ], - [ - "PCIE_NW2A2_15", - "INT_INTERFACE_NW2A2" - ], - [ - "PCIE_LOGIC_OUTS_B22_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B22" - ], - [ - "PCIE_WW2A3_15", - "INT_INTERFACE_WW2A3" - ], - [ - "PCIE_LOGIC_OUTS_B12_L_15", - "INT_INTERFACE_LOGIC_OUTS_L_B12" - ], - [ - "PCIE_IMUX6_L_15", - "PCIE_INT_INTERFACE_IMUX_L_OUT6" - ], - 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"CFG_CENTER_SE2A3_0", - "VFRAME_SE2A3" - ], - [ - "CFG_CENTER_IMUX7_0", - "VFRAME_IMUX7" - ], - [ - "CFG_CENTER_SE4BEG1_0", - "VFRAME_SE4BEG1" - ], - [ - "CFG_CENTER_BYP3_0", - "VFRAME_BYP3" - ], - [ - "CFG_CENTER_NW2A3_0", - "VFRAME_NW2A3" - ], - [ - "CFG_CENTER_SE2A0_0", - "VFRAME_SE2A0" - ], - [ - "CFG_CENTER_NW2A2_0", - "VFRAME_NW2A2" - ], - [ - "CFG_CENTER_CLK0_0", - "VFRAME_CLK0" - ], - [ - "CFG_CENTER_NE2A3_0", - "VFRAME_NE2A3" - ], - [ - "CFG_CENTER_WW4A2_0", - "VFRAME_WW4A2" - ], - [ - "CFG_CENTER_NE4BEG1_0", - "VFRAME_NE4BEG1" - ], - [ - "CFG_CENTER_LH10_0", - "VFRAME_LH10" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B20_0", - "VFRAME_LOGIC_OUTS_B20" - ], - [ - "CFG_CENTER_EE4BEG0_0", - "VFRAME_EE4BEG0" - ], - [ - "CFG_CENTER_LH2_0", - "VFRAME_LH2" - ], - [ - "CFG_CENTER_BYP2_0", - "VFRAME_BYP2" - ], - [ - "CFG_CENTER_IMUX29_0", - "VFRAME_IMUX29" - ], - [ - "CFG_CENTER_WL1END1_0", - "VFRAME_WL1END1" - ] - ], - "tile_types": [ - "CFG_CENTER_MID", - "VFRAME" - ], - "grid_deltas": [ - 1, - 11 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_NW2A0_3", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW4B2_3", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_IMUX19_3", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_EE2A0_3", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_WW2END0_3", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SW2A2_3", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_BYP3_3", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_WL1END0_3", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_SW4A0_3", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_IMUX43_3", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_CLK0_3", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW4C3_3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX22_3", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WW4END2_3", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_FAN6_3", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_EE4C0_3", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_FAN7_3", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_BYP7_3", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_SE2A3_3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_IMUX7_3", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WW2A3_3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NW2A2_3", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_EE4BEG0_3", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_NE4C2_3", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_IMUX0_3", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_NW2A1_3", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX8_3", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_SE2A1_3", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX14_3", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW2END3_3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX47_3", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_NE4C1_3", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW4A1_3", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EE4B0_3", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_EE4A1_3", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_IMUX4_3", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WW4C2_3", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SE4BEG1_3", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_WW4A2_3", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_IMUX38_3", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_EE4B2_3", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_WW2A2_3", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_IMUX39_3", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SE4C1_3", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX9_3", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_SW4END2_3", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_WL1END1_3", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_IMUX6_3", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_IMUX33_3", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX1_3", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_WW4END0_3", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_SE4BEG2_3", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_IMUX30_3", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SW4A3_3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_WR1END0_3", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_IMUX27_3", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_IMUX44_3", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_IMUX37_3", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW2A1_3", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_NW4END0_3", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_NE2A1_3", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_NE2A0_3", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_IMUX40_3", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_NW4A2_3", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WR1END1_3", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4B0_3", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_FAN3_3", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_FAN5_3", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_LH11_3", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX45_3", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NE4C0_3", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_BYP1_3", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_EE2A1_3", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_IMUX21_3", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_EE2A3_3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_BYP5_3", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_IMUX26_3", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX10_3", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_IMUX20_3", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_IMUX36_3", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_SW4END1_3", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_WW2END2_3", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_CLK1_3", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_IMUX41_3", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_NW2A3_3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_NE2A3_3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_SE4C3_3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_SE4C0_3", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_EE4C3_3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_SW2A1_3", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_LH1_3", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_WW4C1_3", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_NE2A2_3", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_SE2A2_3", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_IMUX18_3", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX5_3", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX3_3", + "DSP_IMUX3_3", "INT_INTERFACE_IMUX3" ], - [ - "CLK_HROW_NW4END3_3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SW4END0_3", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WW4C0_3", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_EE4B1_3", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX35_3", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX11_3", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_LH8_3", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_WW4B3_3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE4B3_3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_EE4A0_3", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_IMUX42_3", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_FAN0_3", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_NE4BEG3_3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE4C1_3", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX25_3", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_BYP0_3", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_WW2A0_3", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SE4C2_3", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_WW2END1_3", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX24_3", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WR1END2_3", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_LH7_3", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_NE4C3_3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_WL1END3_3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX17_3", - "INT_INTERFACE_IMUX17" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLBLM_M_COUT_N", - "HCLK_CLB_COUT0_L" - ], - [ - "CLBLM_L_COUT_N", - "HCLK_CLB_COUT1_L" - ] - ], - "tile_types": [ - "CLBLM_L", - "HCLK_CLB" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_DSP_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN5" - ], - [ - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "HCLK_DSP_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN8" - ], - [ - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_DSP_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN9" - ], - [ - "HCLK_DSP_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN11" - ], - [ - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "HCLK_DSP_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN6" - ], - [ - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "HCLK_DSP_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN4" - ], - [ - "HCLK_DSP_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN10" - ], - [ - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], - [ - "HCLK_DSP_CK_IN3", - "HCLK_INT_INTERFACE_CK_IN3" - ], - [ - "HCLK_DSP_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "HCLK_DSP_CK_IN1", - "HCLK_INT_INTERFACE_CK_IN1" - ], - [ - "HCLK_DSP_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN0" - ], - [ - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "HCLK_DSP_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "HCLK_DSP_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN7" - ], - [ - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "HCLK_DSP_CK_IN2", - "HCLK_INT_INTERFACE_CK_IN2" - ], - [ - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ] - ], - "tile_types": [ - "HCLK_DSP_L", - "HCLK_INT_INTERFACE" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_EL1BEG1_13", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_EE4BEG2_13", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_SW4A0_13", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_NW2A3_13", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_SW4END1_13", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE2A2_13", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_NE2A0_13", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_SE4BEG1_13", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_WW2A0_13", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_NE2A2_13", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_EE4A0_13", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_SW2A1_13", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_SE2A2_13", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_SW4END2_13", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_EE4BEG1_13", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_EE4BEG0_13", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW2A3_13", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_SW2A0_13", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_SE4C1_13", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_WL1END0_13", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_LH12_13", - "VBRK_LH12" - ], - [ - "CMT_TOP_WW4C0_13", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_WW4B0_13", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_LH11_13", - "VBRK_LH11" - ], - [ - "CMT_TOP_LH7_13", - "VBRK_LH7" - ], - [ - "CMT_TOP_NE2A1_13", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_NW4A1_13", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WL1END1_13", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_LH3_13", - "VBRK_LH3" - ], - [ - "CMT_TOP_MONITOR_N_13", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_EE2BEG3_13", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_NW4END1_13", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_WW4A3_13", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_NE4BEG1_13", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_SW4END0_13", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_EE2BEG2_13", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_NW4A2_13", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_LH5_13", - "VBRK_LH5" - ], - [ - "CMT_TOP_SE4C3_13", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WW4END3_13", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_NE4BEG3_13", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_LH2_13", - "VBRK_LH2" - ], - [ - "CMT_TOP_EL1BEG2_13", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_LH4_13", - "VBRK_LH4" - ], - [ - "CMT_TOP_WW2A2_13", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_EE2A3_13", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_SE2A0_13", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_EE4A3_13", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_SE4BEG0_13", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_WW4B1_13", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_EE2A1_13", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_WR1END2_13", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW4A2_13", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_SW4END3_13", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_NW4END0_13", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_NE4C2_13", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_SW2A3_13", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_WR1END1_13", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_EE4A2_13", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_WW2A1_13", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_NE4BEG0_13", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_NE4BEG2_13", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_LH8_13", - "VBRK_LH8" - ], - [ - "CMT_TOP_EE4C1_13", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_WR1END3_13", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_SW4A2_13", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_EE2BEG0_13", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_NW2A2_13", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_EE4C2_13", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_LH10_13", - "VBRK_LH10" - ], - [ - "CMT_TOP_EE4B1_13", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_SW2A2_13", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_NE4C1_13", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_EE4B2_13", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_WW4C2_13", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_WW4A1_13", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_WW4END2_13", - "VBRK_WW4END2" - ], - [ - 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"CMT_TOP_ER1BEG3_13", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_SE4BEG3_13", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW4B3_13", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_EE4A1_13", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_MONITOR_P_13", - "VBRK_MONITOR_P" - ], - [ - "CMT_TOP_WL1END2_13", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_SW4A3_13", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_NW2A1_13", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_LH1_13", - "VBRK_LH1" - ], - [ - "CMT_TOP_WW4END1_13", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_WW2END2_13", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_WW4B2_13", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_SE2A1_13", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_LH9_13", - "VBRK_LH9" - ], - [ - "CMT_TOP_WL1END3_13", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_NE4C0_13", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_EE4C0_13", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_SE4BEG2_13", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_EE4B0_13", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_SW4A1_13", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_EE2A0_13", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_EE2BEG1_13", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_EE4BEG3_13", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_WR1END0_13", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_WW4A0_13", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_EE4B3_13", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_ER1BEG1_13", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EL1BEG3_13", - "VBRK_EL1BEG3" - ] - ], - "tile_types": [ - "CMT_TOP_R_LOWER_B", - "VBRK" - ], - "grid_deltas": [ - 1, - -5 - ] - }, - { - "wire_pairs": [ - [ - "BRKH_INT_NN6END_S1_0", - "NN6END0" - ], - [ - "BRKH_INT_SS2A2", - "SS2BEG2" - ], - [ - "BRKH_INT_NN6C0", - "NN6D0" - ], - [ - "BRKH_INT_ER1END3", - "ER1END_N3_3" - ], - [ - "BRKH_INT_NN6E0", - "NN6END0" - ], - [ - "BRKH_INT_SS6C3", - "SS6B3" - ], - [ - "BRKH_INT_SE6C0", - "SE6B0" - ], - [ - "BRKH_INT_NN6B2", - "NN6C2" - ], - [ - "BRKH_INT_LVB_L4", - "LVB_L4" - ], - [ - "BRKH_INT_L_LV3", - "LV_L4" - ], - [ - "BRKH_INT_BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" - ], - [ - "BRKH_INT_NE6C2", - "NE6D2" - ], - [ - "BRKH_INT_SW2A1", - "SW2BEG1" - ], - [ - "BRKH_INT_BYP_BOUNCE7", - "BYP_BOUNCE_N3_7" - ], - [ - "BRKH_INT_NW6B1", - "NW6C1" - ], - [ - "BRKH_INT_NN6D1", - "NN6E1" - ], - [ - "BRKH_INT_NN2BEG3", - "NN2A3" - ], - [ - "BRKH_INT_WW4END_S0_0", - "WW4END0" - ], - [ - "BRKH_INT_NE6A0", - "NE6B0" - ], - [ - "BRKH_INT_SS6E1", - "SS6D1" - ], - [ - "BRKH_INT_SE6E2", - "SE6D2" - ], - [ - "BRKH_INT_SL1END3_SLOW", - "SL1BEG3" - ], - [ - "BRKH_INT_SS2END2", - "SS2A2" - ], - [ - "BRKH_INT_NN6D3", - "NN6E3" - ], - [ - "BRKH_INT_L_LV14", - "LV_L15" - ], - [ - "BRKH_INT_SS6B0", - "SS6A0" - ], - [ - "BRKH_INT_SS6END1", - "SS6E1" - ], - [ - "BRKH_INT_LVB_L9", - "LVB_L9" - ], - [ - "BRKH_INT_SE6B1", - "SE6A1" - ], - [ - "BRKH_INT_NN6BEG0", - "NN6A0" - ], - [ - "BRKH_INT_NN6BEG2", - "NN6A2" - ], - [ - "BRKH_INT_NN2A3", - "NN2END3" - ], - [ - "BRKH_INT_LVB_L7", - "LVB_L7" - ], - [ - "BRKH_INT_ER1BEG_S0", - "ER1BEG0" - ], - [ - "BRKH_INT_NN6A2", - "NN6B2" - ], - [ - "BRKH_INT_NN2BEG1", - "NN2A1" - ], - [ - "BRKH_INT_SS6B2", - "SS6A2" - ], - [ - "BRKH_INT_NW6C2", - "NW6D2" - ], - [ - "BRKH_INT_EL1BEG3", - "EL1BEG_N3" - ], - [ - "BRKH_INT_LVB_L8", - "LVB_L8" - ], - [ - "BRKH_INT_NE6C3", - "NE6D3" - ], - [ - "BRKH_INT_NW6B3", - "NW6C3" - ], - [ - "BRKH_INT_NR1BEG3_SLOW", - "NR1END3" - ], - [ - "BRKH_INT_SS6B1", - "SS6A1" - ], - [ - "BRKH_INT_NE6D2", - "NE6E2" - ], - [ - "BRKH_INT_NW6A1", - "NW6B1" - ], - [ - "BRKH_INT_L_LV8", - "LV_L9" - ], - [ - "BRKH_INT_SW6D2", - "SW6C2" - ], - [ - "BRKH_INT_SS6D3", - "SS6C3" - ], - [ - "BRKH_INT_SW2A0", - "SW2BEG0" - ], - [ - "BRKH_INT_NN6C3", - "NN6D3" - ], - [ - "BRKH_INT_NW6C1", - "NW6D1" - ], - [ - "BRKH_INT_SE6D2", - "SE6C2" - ], - [ - "BRKH_INT_NW2BEG2", - "NW2A2" - ], - [ - "BRKH_INT_SR1END_N3_3", - "SR1END_N3_3" - ], - [ - "BRKH_INT_NN6E3", - "NN6END3" - ], - [ - "BRKH_INT_SS6B3", - "SS6A3" - ], - [ - "BRKH_INT_WL1BEG3", - "WL1BEG_N3" - ], - [ - "BRKH_INT_NR1BEG0_SLOW", - "NR1END0" - ], - [ - "BRKH_INT_SW6B2", - "SW6A2" - ], - [ - "BRKH_INT_NN6D2", - "NN6E2" - ], - [ - "BRKH_INT_SS2END1", - "SS2A1" - ], - [ - "BRKH_INT_L_LV7", - "LV_L8" - ], - [ - "BRKH_INT_SE2A1", - "SE2BEG1" - ], - [ - "BRKH_INT_NE6C1", - "NE6D1" - ], - [ - "BRKH_INT_NW2BEG3", - "NW2A3" - ], - [ - "BRKH_INT_SS2END_N0_3", - "SS2END_N0_3" - ], - [ - "BRKH_INT_NN6A0", - "NN6B0" - ], - [ - "BRKH_INT_L_LV10", - "LV_L11" - ], - [ - "BRKH_INT_NW2BEG0", - "NW2A0" - ], - [ - "BRKH_INT_SE2A0", - "SE2BEG0" - ], - [ - "BRKH_INT_SS6D1", - "SS6C1" - ], - [ - "BRKH_INT_SS2A1", - "SS2BEG1" - ], - [ - "BRKH_INT_NE6D1", - "NE6E1" - ], - [ - "BRKH_INT_L_LV2", - "LV_L3" - ], - [ - "BRKH_INT_SE6E0", - "SE6D0" - ], - [ - "BRKH_INT_NN2A0", - "NN2END0" - ], - [ - "BRKH_INT_NE2BEG0", - "NE2A0" - ], - [ - "BRKH_INT_SE6B2", - "SE6A2" - ], - [ - "BRKH_INT_L_LV11", - "LV_L12" - ], - [ - "BRKH_INT_SE6D3", - "SE6C3" - ], - [ - "BRKH_INT_NL1END_S3_0", - "NL1END0" - ], - [ - "BRKH_INT_SS6E3", - "SS6D3" - ], - [ - "BRKH_INT_LVB_L11", - "LVB_L11" - ], - [ - "BRKH_INT_LVB_L5", - "LVB_L5" - ], - [ - "BRKH_INT_SS6END3", - "SS6E3" - ], - [ - "BRKH_INT_SS6E0", - "SS6D0" - ], - [ - "BRKH_INT_NE6A3", - "NE6B3" - ], - [ - "BRKH_INT_SW6B3", - "SW6A3" - ], - [ - "BRKH_INT_NW6C0", - "NW6D0" - ], - [ - "BRKH_INT_SR1END1_SLOW", - "SR1BEG1" - ], - [ - "BRKH_INT_NN6D0", - "NN6E0" - ], - [ - "BRKH_INT_SW6B0", - "SW6A0" - ], - [ - "BRKH_INT_NL1BEG1_SLOW", - "NL1END1" - ], - [ - "BRKH_INT_SS2A3", - "SS2BEG3" - ], - [ - "BRKH_INT_NN6BEG3", - "NN6A3" - ], - [ - "BRKH_INT_LVB_L10", - "LVB_L10" - ], - [ - "BRKH_INT_SS6END_N0_3", - "SS6END_N0_3" - ], - [ - "BRKH_INT_NE2BEG2", - "NE2A2" - ], - [ - "BRKH_INT_SS6A3", - "SS6BEG3" - ], - [ - "BRKH_INT_NW6D0", - "NW6E0" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_6", - "FAN_BOUNCE6" - ], - [ - "BRKH_INT_NR1BEG2_SLOW", - "NR1END2" - ], - [ - "BRKH_INT_L_LV9", - "LV_L10" - ], - [ - "BRKH_INT_NN6B3", - "NN6C3" - ], - [ - "BRKH_INT_SW2END3", - "SW2END_N0_3" - ], - [ - "BRKH_INT_NN6BEG1", - "NN6A1" - ], - [ - "BRKH_INT_NE6B3", - "NE6C3" - ], - [ - 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"BRKH_INT_L_LV17", - "LV_L18" - ], - [ - "BRKH_INT_SS6D0", - "SS6C0" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_4", - "FAN_BOUNCE4" - ], - [ - "BRKH_INT_NE6D3", - "NE6E3" - ], - [ - "BRKH_INT_NE6D0", - "NE6E0" - ], - [ - "BRKH_INT_SW6C0", - "SW6B0" - ], - [ - "BRKH_INT_L_LV4", - "LV_L5" - ], - [ - "BRKH_INT_NN2BEG0", - "NN2A0" - ], - [ - "BRKH_INT_NN2END_S2_0", - "NN2END0" - ], - [ - "BRKH_INT_L_LV15", - "LV_L16" - ], - [ - "BRKH_INT_LVB_L6", - "LVB_L6" - ], - [ - "BRKH_INT_SS2END0", - "SS2A0" - ], - [ - "BRKH_INT_L_LV0", - "LV_L1" - ], - [ - "BRKH_INT_SS2A0", - "SS2BEG0" - ], - [ - "BRKH_INT_SE2A3", - "SE2BEG3" - ], - [ - "BRKH_INT_NE2BEG3", - "NE2A3" - ], - [ - "BRKH_INT_SE6E3", - "SE6D3" - ], - [ - "BRKH_INT_SW6E1", - "SW6D1" - ], - [ - "BRKH_INT_LVB_L2", - "LVB_L2" - ], - [ - "BRKH_INT_WL1END3", - "WL1END_N1_3" - ], - [ - "BRKH_INT_SE6E1", - "SE6D1" - ], - [ - "BRKH_INT_LVB_L12", - "LVB_L12" - ], - [ - "BRKH_INT_SS6C1", - "SS6B1" - ], - [ - "BRKH_INT_SS2END3", - "SS2A3" - ], - [ - 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"BRKH_INT_NN6A3", - "NN6B3" - ], - [ - "BRKH_INT_NW2BEG1", - "NW2A1" - ], - [ - "BRKH_INT_SE6D1", - "SE6C1" - ], - [ - "BRKH_INT_NW6A0", - "NW6B0" - ], - [ - "BRKH_INT_SL1END1_SLOW", - "SL1BEG1" - ], - [ - "BRKH_INT_SW6D0", - "SW6C0" - ], - [ - "BRKH_INT_SE6B0", - "SE6A0" - ], - [ - "BRKH_INT_NE2END_S3_0", - "NE2END0" - ], - [ - "BRKH_INT_NR1BEG1_SLOW", - "NR1END1" - ], - [ - "BRKH_INT_LVB_L1", - "LVB_L1" - ], - [ - "BRKH_INT_SL1END2_SLOW", - "SL1BEG2" - ], - [ - "BRKH_INT_NE6C0", - "NE6D0" - ], - [ - "BRKH_INT_SE2A2", - "SE2BEG2" - ], - [ - "BRKH_INT_SR1END3_SLOW", - "SR1BEG3" - ], - [ - "BRKH_INT_NN2A1", - "NN2END1" - ], - [ - "BRKH_INT_SE6C1", - "SE6B1" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_2", - "FAN_BOUNCE2" - ], - [ - "BRKH_INT_NE6A1", - "NE6B1" - ], - [ - "BRKH_INT_SE6C3", - "SE6B3" - ], - [ - "BRKH_INT_BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "BRKH_INT_NW6B0", - "NW6C0" - ], - [ - "BRKH_INT_NW6END_S0_0", - "NW6END0" - ], - [ - "BRKH_INT_SS6C0", - "SS6B0" - ], - [ - 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"DSP_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "DSP_LH5_3", - "VBRK_LH5" - ], - [ - "DSP_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "DSP_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "DSP_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "DSP_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "DSP_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "DSP_MONITOR_N_3", - "VBRK_MONITOR_N" - ], - [ - "DSP_WW4C1_3", - "VBRK_WW4C1" - ], - [ - "DSP_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "DSP_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "DSP_LH1_3", - "VBRK_LH1" - ], - [ - "DSP_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "DSP_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "DSP_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "DSP_LH8_3", - "VBRK_LH8" - ], - [ - "DSP_NW4A2_3", - "VBRK_NW4A2" - ], - [ - "DSP_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "DSP_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "DSP_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "DSP_WW4A3_3", - "VBRK_WW4A3" - ], - [ - "DSP_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "DSP_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "DSP_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "DSP_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "DSP_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "DSP_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "DSP_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "DSP_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "DSP_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "DSP_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "DSP_WL1END2_3", - "VBRK_WL1END2" - ], - [ - "DSP_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "DSP_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "DSP_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "DSP_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "DSP_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "DSP_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "DSP_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "DSP_SW2A0_3", - "VBRK_SW2A0" - ], - [ - "DSP_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "DSP_LH6_3", - "VBRK_LH6" - ], - [ - "DSP_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "DSP_SE2A2_3", - "VBRK_SE2A2" - ], - [ - "DSP_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "DSP_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "DSP_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "DSP_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "DSP_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "DSP_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "DSP_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "DSP_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "DSP_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "DSP_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "DSP_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "DSP_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "DSP_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "DSP_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "DSP_LH7_3", - "VBRK_LH7" - ], - [ - "DSP_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "DSP_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "DSP_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "DSP_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "DSP_MONITOR_P_3", - "VBRK_MONITOR_P" - ], - [ - "DSP_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "DSP_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "DSP_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "DSP_LH4_3", - "VBRK_LH4" - ], - [ - "DSP_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "DSP_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "DSP_LH11_3", - "VBRK_LH11" - ], - [ - "DSP_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "DSP_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "DSP_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "DSP_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "DSP_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "DSP_LH12_3", - "VBRK_LH12" - ], - [ - "DSP_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "DSP_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "DSP_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "DSP_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "DSP_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "DSP_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "DSP_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "DSP_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "DSP_LH2_3", - "VBRK_LH2" - ], - [ - "DSP_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "DSP_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "DSP_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "DSP_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "DSP_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "DSP_LH3_3", - "VBRK_LH3" - ], - [ - "DSP_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "DSP_WW2A1_3", - "VBRK_WW2A1" - ], - [ - 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"INT_INTERFACE_LOGIC_OUTS_L_B22" + ], + [ + "DSP_NW2A2_3", + "INT_INTERFACE_NW2A2" + ], + [ + "DSP_IMUX37_3", + "INT_INTERFACE_IMUX37" + ], + [ + "DSP_SE4BEG0_3", + "INT_INTERFACE_SE4BEG0" + ], + [ + "DSP_LOGIC_OUTS_B0_3", + "INT_INTERFACE_LOGIC_OUTS_L_B0" + ], + [ + "DSP_EE4A1_3", + "INT_INTERFACE_EE4A1" + ], + [ + "DSP_LH4_3", + "INT_INTERFACE_LH4" + ], + [ + "DSP_EE2A1_3", + "INT_INTERFACE_EE2A1" + ], + [ + "DSP_BYP1_3", + "INT_INTERFACE_BYP1" + ], + [ + "DSP_SE2A3_3", + "INT_INTERFACE_SE2A3" ], [ "DSP_ER1BEG0_3", - "VBRK_ER1BEG0" - ] - ], - "tile_types": [ - "DSP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -3 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_BUFG_IMUX5_3", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NW2A0_3", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_3", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW4B2_3", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_MONITOR_P_3", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_EE2A0_3", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_WW2END0_3", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_SW2A2_3", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_BUFG_IMUX8_3", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_BYP3_3", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_BUFG_IMUX19_3", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_WL1END0_3", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_SW4A0_3", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_CLK0_3", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_BUFG_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_WW4C3_3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_BUFG_IMUX20_3", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_BUFG_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX41_3", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_BUFG_IMUX17_3", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_FAN6_3", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4END2_3", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE4C0_3", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_FAN7_3", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_BYP7_3", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_SE2A3_3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_BUFG_IMUX3_3", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_WW2A3_3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_3", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NW2A2_3", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_EE4BEG0_3", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_NE4C2_3", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_BUFG_IMUX43_3", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_3", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_HROW_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_ER1BEG0_3", "INT_INTERFACE_ER1BEG0" ], [ - "CLK_HROW_NW2A1_3", - "INT_INTERFACE_NW2A1" + "DSP_EE4C1_3", + "INT_INTERFACE_EE4C1" ], [ - "CLK_BUFG_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_BUFG_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_SE2A1_3", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW2END3_3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_NE4C1_3", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW4A1_3", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EE4B0_3", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_EE4A1_3", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_BUFG_IMUX6_3", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_WW4C2_3", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SE4BEG1_3", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_WW4A2_3", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_EE4B2_3", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_WW2A2_3", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_SE4C1_3", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_BUFG_IMUX30_3", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SW4END2_3", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_BUFG_IMUX24_3", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_WL1END1_3", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_WW4END0_3", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_BUFG_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_SE4BEG2_3", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_SW4A3_3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_WR1END0_3", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_BUFG_IMUX18_3", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_BUFG_IMUX26_3", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_BUFG_IMUX33_3", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW2A1_3", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_NW4END0_3", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_NE2A1_3", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_NE2A0_3", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_NW4A2_3", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WR1END1_3", + "DSP_WR1END1_3", "INT_INTERFACE_WR1END1" ], [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4B0_3", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_FAN3_3", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_FAN5_3", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_BUFG_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_BUFG_IMUX42_3", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_LH11_3", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NE4C0_3", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_BUFG_IMUX47_3", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_BYP1_3", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_EE2A1_3", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_IMUX10_3", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_BUFG_IMUX0_3", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_BUFG_IMUX39_3", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_EE2A3_3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_BUFG_IMUX25_3", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_BYP5_3", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "CLK_BUFG_IMUX44_3", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_BUFG_IMUX7_3", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_BUFG_IMUX38_3", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_SW4END1_3", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_WW2END2_3", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_CLK1_3", + "DSP_CLK1_3", "INT_INTERFACE_CLK1" ], [ - "CLK_HROW_NW2A3_3", - "INT_INTERFACE_NW2A3" + "DSP_MONITOR_N_3", + "INT_INTERFACE_MONITOR_N" ], [ - "CLK_BUFG_IMUX21_3", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_BUFG_IMUX11_3", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_NE2A3_3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_3", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_BUFG_IMUX35_3", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_BUFG_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_BUFG_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_SE4C3_3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_SE4C0_3", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_3", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_HROW_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_EE4C3_3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_SW2A1_3", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_LH1_3", - "INT_INTERFACE_LH1" - ], - [ - "CLK_BUFG_IMUX37_3", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_3", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_BUFG_IMUX22_3", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_WW4C1_3", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_NE2A2_3", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_SE2A2_3", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_3", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_3", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_BUFG_IMUX4_3", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_NW4END3_3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SW4END0_3", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_BUFG_IMUX9_3", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_BUFG_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WW4C0_3", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_BUFG_IMUX40_3", + "DSP_IMUX40_3", "INT_INTERFACE_IMUX40" ], [ - "CLK_BUFG_IMUX27_3", - "INT_INTERFACE_IMUX27" + "DSP_SE4BEG3_3", + "INT_INTERFACE_SE4BEG3" ], [ - "CLK_HROW_EE4B1_3", - "INT_INTERFACE_EE4B1" + "DSP_NW4END2_3", + "INT_INTERFACE_NW4END2" ], [ - "CLK_BUFG_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_LH8_3", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_WW4B3_3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE4B3_3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_EE4A0_3", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_FAN0_3", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_BUFG_IMUX36_3", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_BUFG_IMUX1_3", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_NE4BEG3_3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_MONITOR_N_3", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_EE4C1_3", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_BYP0_3", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_WW2A0_3", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SE4C2_3", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_BUFG_IMUX14_3", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WW2END1_3", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WR1END2_3", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_LH7_3", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_NE4C3_3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_WL1END3_3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_BUFG_IMUX45_3", - "INT_INTERFACE_IMUX45" - ] - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -3 - ] - }, - { - "wire_pairs": [ - [ - "GTPE2_IMUX17_5", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_CTRL0_5", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_IMUX5_5", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX41_5", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX19_5", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX36_5", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_FAN1_5", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX35_5", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX14_5", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_BYP6_5", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX18_5", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX30_5", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX27_5", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX32_5", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B5_5", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_LOGIC_OUTS_B15_5", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_CLK1_5", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX23_5", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_FAN6_5", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_BYP0_5", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_LOGIC_OUTS_B0_5", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_BYP3_5", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX2_5", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX46_5", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX6_5", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_LOGIC_OUTS_B6_5", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX43_5", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX44_5", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_LOGIC_OUTS_B13_5", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX25_5", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_LOGIC_OUTS_B2_5", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_BYP2_5", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX24_5", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_IMUX9_5", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX37_5", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_FAN5_5", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_IMUX3_5", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_CLK0_5", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_LOGIC_OUTS_B17_5", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX28_5", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX34_5", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX15_5", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_FAN4_5", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX26_5", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_FAN2_5", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX12_5", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX38_5", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX13_5", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_LOGIC_OUTS_B21_5", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_IMUX16_5", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_LOGIC_OUTS_B14_5", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_LOGIC_OUTS_B12_5", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_IMUX7_5", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_LOGIC_OUTS_B22_5", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX22_5", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX29_5", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX42_5", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_LOGIC_OUTS_B23_5", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_BYP1_5", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX33_5", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_BYP7_5", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_LOGIC_OUTS_B7_5", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX10_5", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_LOGIC_OUTS_B10_5", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_LOGIC_OUTS_B4_5", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_LOGIC_OUTS_B1_5", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX39_5", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX11_5", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_BYP4_5", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX21_5", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX4_5", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX20_5", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX8_5", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX1_5", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_FAN0_5", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX31_5", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX45_5", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX40_5", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_LOGIC_OUTS_B3_5", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_BYP5_5", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_LOGIC_OUTS_B9_5", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX47_5", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_CTRL1_5", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_FAN7_5", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX0_5", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_FAN3_5", - "VBRK_EXT_FAN3" - ] - ], - "tile_types": [ - "GTP_CHANNEL_2", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "INT_INTERFACE_BRAM_IMUX33", - "IMUX_L33" - ], - [ - "INT_INTERFACE_EE2A1", - "EE2END1" - ], - [ - "INT_INTERFACE_EE4A0", - "EE4B0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L10", - "LOGIC_OUTS_L10" - ], - [ - "INT_INTERFACE_EE2A2", - "EE2END2" - ], - [ - "INT_INTERFACE_SW4A2", - "SW6BEG2" - ], - [ - "INT_INTERFACE_NE4C0", - "NE6END0" - ], - [ - "INT_INTERFACE_SE2A1", - "SE2END1" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "IMUX_L41" - ], - [ - "INT_INTERFACE_SE2A2", - "SE2END2" - ], - [ - "INT_INTERFACE_NE4BEG2", - "NE6A2" - ], - [ - "INT_INTERFACE_EE4A1", - "EE4B1" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "IMUX_L5" - ], - [ - "INT_INTERFACE_CTRL1", - "CTRL_L1" - ], - [ - "INT_INTERFACE_LH4", - "LH3" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "IMUX_L6" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "IMUX_L8" - ], - [ - "INT_INTERFACE_EE4BEG1", - "EE4A1" - ], - [ - "INT_INTERFACE_BYP7", - "BYP_L7" - ], - [ - "INT_INTERFACE_SW4END0", - "SW6E0" - ], - [ - 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"CFG_CENTER_SW4END1_13", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_EE4B3_13", + "VFRAME_EE4B3" + ], + [ + "CFG_CENTER_IMUX1_13", + "VFRAME_IMUX1" + ], + [ + "CFG_CENTER_SE2A1_13", + "VFRAME_SE2A1" + ], + [ + "CFG_CENTER_EE2A1_13", + "VFRAME_EE2A1" + ], + [ + "CFG_CENTER_NE4BEG3_13", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_NW4A1_13", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_EE4A3_13", + "VFRAME_EE4A3" + ], + [ + "CFG_CENTER_NE4BEG2_13", + "VFRAME_NE4BEG2" + ], + [ + "CFG_CENTER_NE4C0_13", + "VFRAME_NE4C0" + ], + [ + "CFG_CENTER_EE4BEG2_13", + "VFRAME_EE4BEG2" + ] ] }, { - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN21" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN16" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN12" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN23" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_HROW_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN0" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN30" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN19" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN11" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN6" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN4" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN15" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN29" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN27" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN7" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN3" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN20" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN31" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN5" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK25" - ] - ], "tile_types": [ - "CLK_FEED", - "CLK_HROW_TOP_R" - ], - "grid_deltas": [ - 0, - 5 - ] - }, - { - "wire_pairs": [ - [ - "GTPE2_FAN0_3", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_CTRL1_3", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_LOGIC_OUTS_B9_3", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_LOGIC_OUTS_B18_3", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_CLK1_3", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX29_3", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX18_3", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX44_3", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_FAN3_3", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX46_3", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_CLK0_3", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_FAN4_3", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX11_3", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_BYP4_3", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_LOGIC_OUTS_B10_3", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_IMUX37_3", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_LOGIC_OUTS_B15_3", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_IMUX41_3", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX38_3", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_LOGIC_OUTS_B1_3", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX14_3", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX45_3", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_BYP3_3", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX27_3", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX19_3", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX1_3", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_LOGIC_OUTS_B12_3", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_LOGIC_OUTS_B13_3", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX10_3", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX24_3", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_LOGIC_OUTS_B14_3", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_LOGIC_OUTS_B5_3", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_IMUX16_3", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX15_3", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX5_3", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX2_3", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_CTRL0_3", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_LOGIC_OUTS_B17_3", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX42_3", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX30_3", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX39_3", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX8_3", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX9_3", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_LOGIC_OUTS_B22_3", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX36_3", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_BYP5_3", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX40_3", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX47_3", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_LOGIC_OUTS_B0_3", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_BYP7_3", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_FAN5_3", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_FAN7_3", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX33_3", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX6_3", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX7_3", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX3_3", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX12_3", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX25_3", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX43_3", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX35_3", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX4_3", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_FAN2_3", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_LOGIC_OUTS_B16_3", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_IMUX17_3", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_LOGIC_OUTS_B19_3", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_IMUX0_3", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_BYP2_3", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX31_3", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX13_3", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX34_3", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX28_3", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_BYP6_3", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_BYP0_3", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX20_3", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX32_3", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX23_3", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX26_3", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_FAN1_3", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_BYP1_3", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_FAN6_3", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX22_3", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_LOGIC_OUTS_B4_3", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_LOGIC_OUTS_B3_3", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_LOGIC_OUTS_B7_3", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX21_3", - "VBRK_EXT_IMUX21" - ] - ], - "tile_types": [ - "GTP_CHANNEL_2", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - 2 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU13", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU7", - 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"VBRK_EE4C2" - ], - [ - "CLK_HROW_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_LH6_1", - "VBRK_LH6" - ], - [ - "CLK_HROW_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_HROW_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_HROW_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_HROW_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_HROW_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_HROW_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_HROW_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW4A3_1", - "VBRK_WW4A3" - ] - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CFG_CENTER_CK_IN13", - "HCLK_VFRAME_CK_IN13" - ], - [ - "CFG_CENTER_CK_BUFHCLK1", - "HCLK_VFRAME_CK_BUFHCLK1" - ], - [ - "CFG_CENTER_CK_IN5", - "HCLK_VFRAME_CK_IN5" - ], - [ - "CFG_CENTER_CK_IN3", - "HCLK_VFRAME_CK_IN3" - ], - [ - "CFG_CENTER_CK_BUFHCLK0", - "HCLK_VFRAME_CK_BUFHCLK0" - ], - [ - "CFG_CENTER_CK_IN8", - "HCLK_VFRAME_CK_IN8" - ], - [ - "CFG_CENTER_CK_BUFRCLK3", - "HCLK_VFRAME_CK_BUFRCLK3" - ], - [ - "CFG_CENTER_CK_IN10", - "HCLK_VFRAME_CK_IN10" - ], - [ - "CFG_CENTER_CK_IN12", - "HCLK_VFRAME_CK_IN12" - ], - [ - "CFG_CENTER_CK_BUFHCLK6", - "HCLK_VFRAME_CK_BUFHCLK6" - ], - [ - "CFG_CENTER_CK_BUFHCLK3", - "HCLK_VFRAME_CK_BUFHCLK3" - ], - [ - "CFG_CENTER_CK_BUFHCLK9", - "HCLK_VFRAME_CK_BUFHCLK9" - ], - [ - "CFG_CENTER_CK_BUFRCLK0", - "HCLK_VFRAME_CK_BUFRCLK0" - ], - [ - "CFG_CENTER_CK_IN0", - "HCLK_VFRAME_CK_IN0" - ], - [ - "CFG_CENTER_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK4" - ], - [ - "CFG_CENTER_CK_IN2", - "HCLK_VFRAME_CK_IN2" - ], - [ - "CFG_CENTER_CK_IN1", - "HCLK_VFRAME_CK_IN1" - ], - [ - "CFG_CENTER_CK_IN11", - "HCLK_VFRAME_CK_IN11" - ], - [ - "CFG_CENTER_CK_BUFHCLK5", - "HCLK_VFRAME_CK_BUFHCLK5" - ], - [ - "CFG_CENTER_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK8" - ], - [ - "CFG_CENTER_CK_BUFHCLK2", - "HCLK_VFRAME_CK_BUFHCLK2" - ], - [ - "CFG_CENTER_CK_BUFRCLK2", - "HCLK_VFRAME_CK_BUFRCLK2" - ], - [ - "CFG_CENTER_CK_BUFHCLK11", - "HCLK_VFRAME_CK_BUFHCLK11" - ], - [ - "CFG_CENTER_CK_IN6", - "HCLK_VFRAME_CK_IN6" - ], - [ - "CFG_CENTER_CK_BUFHCLK10", - "HCLK_VFRAME_CK_BUFHCLK10" - ], - [ - "CFG_CENTER_CK_BUFHCLK7", - "HCLK_VFRAME_CK_BUFHCLK7" - ], - [ - "CFG_CENTER_CK_IN7", - "HCLK_VFRAME_CK_IN7" - ], - [ - "CFG_CENTER_CK_IN9", - "HCLK_VFRAME_CK_IN9" - ], - [ - "CFG_CENTER_CK_IN4", - "HCLK_VFRAME_CK_IN4" - ], - [ - "CFG_CENTER_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFRCLK1" - ] - ], - "tile_types": [ - "CFG_CENTER_MID", - "HCLK_VFRAME" - ], - "grid_deltas": [ - 1, - 6 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU13", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU0", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" - ], - [ - "BRAM_FIFO36_CASCADEOUTB_1", - "BRKH_BRAM_CASCADEB_L" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU0", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU13", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" - ], - [ - "BRAM_FIFO36_CASCADEOUTA_1", - "BRKH_BRAM_CASCADEA_L" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" - ] - ], - "tile_types": [ - "BRAM_L", - "BRKH_BRAM" - ], - "grid_deltas": [ - 0, - -5 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_FEEDTHRU_1_CK_IN9", - "HCLK_FEEDTHRU_2_CK_IN9" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_FEEDTHRU_2_CK_BUFHCLK9" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_FEEDTHRU_2_CK_BUFHCLK5" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_FEEDTHRU_2_CK_BUFHCLK6" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_FEEDTHRU_2_CK_BUFHCLK8" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_FEEDTHRU_2_CK_IN10" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_FEEDTHRU_2_CK_BUFHCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_FEEDTHRU_2_CK_IN4" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_FEEDTHRU_2_CK_BUFRCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_FEEDTHRU_2_CK_BUFRCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_FEEDTHRU_2_CK_BUFHCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_FEEDTHRU_2_CK_IN13" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_FEEDTHRU_2_CK_BUFHCLK11" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_FEEDTHRU_2_CK_IN8" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_FEEDTHRU_2_CK_BUFHCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_FEEDTHRU_2_CK_BUFHCLK10" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_FEEDTHRU_2_CK_IN5" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_FEEDTHRU_2_CK_BUFHCLK4" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN0", - 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"CLK_BUFG_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_ER1BEG0_1", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_MONITOR_N_1", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_BUFG_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_BUFG_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_BUFG_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_BUFG_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_BUFG_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_BUFG_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_BUFG_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX39_1", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_BUFG_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_BUFG_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_BUFG_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_1", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW2A3_1", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_BUFG_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_1", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_BUFG_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_BUFG_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_BUFG_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_BUFG_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_BUFG_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_1", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_HROW_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_1", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_BYP4_1", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_NW4END3_1", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_1", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_BUFG_IMUX10_1", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_BUFG_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_BUFG_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_BUFG_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_BUFG_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_BUFG_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_BUFG_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_EE4C2_1", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_BUFG_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_1", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_BUFG_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_BUFG_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_BUFG_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_BUFG_IMUX3_1", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_BUFG_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_BUFG_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_BUFG_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_1", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_1", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_HROW_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_WW4END2_1", - "INT_INTERFACE_WW4END2" - ] - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_NW2A0_2", - "CLBLM_NW2A0" - ], - [ - "BRAM_SW4END3_2", - "CLBLM_SW4END3" - ], - [ - "BRAM_EE4A2_2", - "CLBLM_EE4A2" - ], - [ - "BRAM_WW4B1_2", - "CLBLM_WW4B1" - ], - [ - "BRAM_WW4C0_2", - "CLBLM_WW4C0" - ], - [ - "BRAM_WW2A0_2", - "CLBLM_WW2A0" - ], - [ - "BRAM_SE4C3_2", - "CLBLM_SE4C3" - ], - [ - "BRAM_WR1END1_2", - "CLBLM_WR1END1" - ], - [ - "BRAM_NW4A3_2", - "CLBLM_NW4A3" - ], - [ - "BRAM_WW4A1_2", - "CLBLM_WW4A1" - ], - [ - "BRAM_WW4A3_2", - "CLBLM_WW4A3" - ], - [ - "BRAM_LH5_2", - "CLBLM_LH5" - ], - [ - "BRAM_NE4BEG2_2", - "CLBLM_NE4BEG2" - ], - [ - "BRAM_WR1END3_2", - "CLBLM_WR1END3" - ], - [ - "BRAM_WW4C1_2", - "CLBLM_WW4C1" - ], - [ - "BRAM_EL1BEG0_2", - "CLBLM_EL1BEG0" - ], - [ - "BRAM_NE4BEG0_2", - "CLBLM_NE4BEG0" - ], - [ - "BRAM_EE2BEG2_2", - "CLBLM_EE2BEG2" - ], - [ - "BRAM_SE4BEG3_2", - "CLBLM_SE4BEG3" - ], - [ - "BRAM_SE4BEG2_2", - "CLBLM_SE4BEG2" - ], - [ - "BRAM_NE4BEG3_2", - "CLBLM_NE4BEG3" - ], - [ - "BRAM_SE4BEG0_2", - "CLBLM_SE4BEG0" - ], - [ - "BRAM_ER1BEG1_2", - "CLBLM_ER1BEG1" - ], - [ - "BRAM_SE4C1_2", - "CLBLM_SE4C1" - ], - [ - "BRAM_ER1BEG2_2", - "CLBLM_ER1BEG2" - ], - [ - "BRAM_EE2BEG0_2", - "CLBLM_EE2BEG0" - ], - [ - "BRAM_WR1END0_2", - "CLBLM_WR1END0" - ], - [ - "BRAM_LH6_2", - "CLBLM_LH6" - ], - [ - "BRAM_EE4A1_2", - "CLBLM_EE4A1" - ], - [ - "BRAM_NE2A2_2", - "CLBLM_NE2A2" - ], - [ - "BRAM_WW2END0_2", - "CLBLM_WW2END0" - ], - [ - "BRAM_EE4C3_2", - "CLBLM_EE4C3" - ], - [ - "BRAM_NE2A1_2", - "CLBLM_NE2A1" - ], - [ - "BRAM_WW4C3_2", - "CLBLM_WW4C3" - ], - [ - "BRAM_SW4END1_2", - "CLBLM_SW4END1" - ], - [ - "BRAM_WW4B2_2", - "CLBLM_WW4B2" - ], - [ - "BRAM_SE4C2_2", - "CLBLM_SE4C2" - ], - [ - "BRAM_EE2A1_2", - "CLBLM_EE2A1" - ], - [ - "BRAM_EE4BEG2_2", - "CLBLM_EE4BEG2" - ], - [ - "BRAM_NE4C3_2", - "CLBLM_NE4C3" - ], - [ - "BRAM_NW4A1_2", - "CLBLM_NW4A1" - ], - [ - "BRAM_LH4_2", - "CLBLM_LH4" - ], - [ - "BRAM_WW4A2_2", - "CLBLM_WW4A2" - ], - [ - "BRAM_WW2END2_2", - "CLBLM_WW2END2" - ], - [ - "BRAM_ER1BEG0_2", - "CLBLM_ER1BEG0" - ], - [ - "BRAM_SW4END2_2", - "CLBLM_SW4END2" - ], - [ - "BRAM_LH10_2", - "CLBLM_LH10" - ], - [ - "BRAM_NW4END0_2", - "CLBLM_NW4END0" - ], - [ - "BRAM_WW4END3_2", - "CLBLM_WW4END3" - ], - [ - "BRAM_SW4A0_2", - "CLBLM_SW4A0" - ], - [ - "BRAM_EE2A0_2", - "CLBLM_EE2A0" - ], - [ - "BRAM_EE2A2_2", - "CLBLM_EE2A2" - ], - [ - "BRAM_SE2A0_2", - "CLBLM_SE2A0" - ], - [ - "BRAM_NE4C2_2", - "CLBLM_NE4C2" - ], - [ - "BRAM_NW4END2_2", - "CLBLM_NW4END2" - ], - [ - "BRAM_EE4A3_2", - "CLBLM_EE4A3" - ], - [ - "BRAM_NE4C1_2", - "CLBLM_NE4C1" - ], - [ - "BRAM_WW4END2_2", - "CLBLM_WW4END2" - ], - [ - "BRAM_WW2END1_2", - "CLBLM_WW2END1" - ], - [ - "BRAM_WR1END2_2", - "CLBLM_WR1END2" - ], - [ - "BRAM_SE2A3_2", - "CLBLM_SE2A3" - ], - [ - "BRAM_NE4C0_2", - "CLBLM_NE4C0" - ], - [ - "BRAM_LH8_2", - "CLBLM_LH8" - ], - [ - "BRAM_SE4C0_2", - "CLBLM_SE4C0" - ], - [ - "BRAM_LH7_2", - "CLBLM_LH7" - ], - [ - "BRAM_SW4A2_2", - "CLBLM_SW4A2" - ], - [ - "BRAM_EE4BEG3_2", - "CLBLM_EE4BEG3" - ], - [ - "BRAM_WW4C2_2", - "CLBLM_WW4C2" - ], - [ - "BRAM_EE2BEG1_2", - "CLBLM_EE2BEG1" - ], - [ - "BRAM_NE2A0_2", - "CLBLM_NE2A0" - ], - [ - "BRAM_NW2A1_2", - "CLBLM_NW2A1" - ], - [ - "BRAM_SE2A2_2", - "CLBLM_SE2A2" - ], - [ - "BRAM_EE4B3_2", - "CLBLM_EE4B3" - ], - [ - "BRAM_EE4B2_2", - "CLBLM_EE4B2" - ], - [ - "BRAM_ER1BEG3_2", - "CLBLM_ER1BEG3" - ], - [ - "BRAM_EE4C2_2", - "CLBLM_EE4C2" - ], - [ - "BRAM_NE4BEG1_2", - "CLBLM_NE4BEG1" - ], - [ - "BRAM_EE4B0_2", - "CLBLM_EE4B0" - ], - [ - "BRAM_WW4A0_2", - "CLBLM_WW4A0" - ], - [ - "BRAM_SW2A0_2", - "CLBLM_SW2A0" - ], - [ - "BRAM_NW4A0_2", - "CLBLM_NW4A0" - ], - [ - "BRAM_WW4B3_2", - "CLBLM_WW4B3" - ], - [ - "BRAM_EL1BEG1_2", - "CLBLM_EL1BEG1" - ], - [ - "BRAM_EE4A0_2", - "CLBLM_EE4A0" - ], - [ - "BRAM_WL1END1_2", - "CLBLM_WL1END1" - ], - [ - "BRAM_WW4B0_2", - "CLBLM_WW4B0" - ], - [ - "BRAM_SE4BEG1_2", - "CLBLM_SE4BEG1" - ], - [ - "BRAM_WL1END3_2", - "CLBLM_WL1END3" - ], - [ - "BRAM_NW2A3_2", - "CLBLM_NW2A3" - ], - [ - "BRAM_MONITOR_P_2", - "CLBLM_MONITOR_P" - ], - [ - "BRAM_SW2A1_2", - "CLBLM_SW2A1" - ], - [ - "BRAM_NW4END1_2", - "CLBLM_NW4END1" - ], - [ - "BRAM_EL1BEG3_2", - "CLBLM_EL1BEG3" - ], - [ - "BRAM_SW2A2_2", - "CLBLM_SW2A2" - ], - [ - "BRAM_EE2A3_2", - "CLBLM_EE2A3" - ], - [ - "BRAM_WW4END0_2", - "CLBLM_WW4END0" - ], - [ - "BRAM_NW4END3_2", - "CLBLM_NW4END3" - ], - [ - "BRAM_EE4C1_2", - "CLBLM_EE4C1" - ], - [ - "BRAM_EE4B1_2", - "CLBLM_EE4B1" - ], - [ - "BRAM_NW4A2_2", - "CLBLM_NW4A2" - ], - [ - "BRAM_SW2A3_2", - "CLBLM_SW2A3" - ], - [ - "BRAM_NE2A3_2", - "CLBLM_NE2A3" - ], - [ - "BRAM_LH3_2", - "CLBLM_LH3" - ], - [ - "BRAM_LH12_2", - "CLBLM_LH12" - ], - [ - "BRAM_WW2A2_2", - "CLBLM_WW2A2" - ], - [ - "BRAM_EE4BEG0_2", - "CLBLM_EE4BEG0" - ], - [ - "BRAM_EE4BEG1_2", - "CLBLM_EE4BEG1" - ], - [ - "BRAM_SW4A3_2", - "CLBLM_SW4A3" - ], - [ - "BRAM_WW2A1_2", - "CLBLM_WW2A1" - ], - [ - "BRAM_SW4END0_2", - "CLBLM_SW4END0" - ], - [ - "BRAM_WL1END2_2", - "CLBLM_WL1END2" - ], - [ - "BRAM_EL1BEG2_2", - "CLBLM_EL1BEG2" - ], - [ - "BRAM_SE2A1_2", - "CLBLM_SE2A1" - ], - [ - "BRAM_LH1_2", - "CLBLM_LH1" - ], - [ - "BRAM_SW4A1_2", - "CLBLM_SW4A1" - ], - [ - "BRAM_LH9_2", - "CLBLM_LH9" - ], - [ - "BRAM_WW2A3_2", - "CLBLM_WW2A3" - ], - [ - "BRAM_WL1END0_2", - "CLBLM_WL1END0" - ], - [ - "BRAM_LH11_2", - "CLBLM_LH11" - ], - [ - "BRAM_MONITOR_N_2", - "CLBLM_MONITOR_N" - ], - [ - "BRAM_EE2BEG3_2", - "CLBLM_EE2BEG3" - ], - [ - "BRAM_WW4END1_2", - "CLBLM_WW4END1" - ], - [ - "BRAM_EE4C0_2", - "CLBLM_EE4C0" - ], - [ - "BRAM_NW2A2_2", - "CLBLM_NW2A2" - ], - [ - "BRAM_WW2END3_2", - "CLBLM_WW2END3" - ], - [ - "BRAM_LH2_2", - "CLBLM_LH2" - ] - ], "tile_types": [ "BRAM_L", "CLBLM_R" ], "grid_deltas": [ -1, - -2 + -4 + ], + "wire_pairs": [ + [ + "BRAM_WW4B0_4", + "CLBLM_WW4B0" + ], + [ + "BRAM_SE4C1_4", + "CLBLM_SE4C1" + ], + [ + "BRAM_NE4BEG1_4", + "CLBLM_NE4BEG1" + ], + [ + "BRAM_LH10_4", + "CLBLM_LH10" + ], + [ + "BRAM_SE4C3_4", + "CLBLM_SE4C3" + ], + [ + "BRAM_NE2A0_4", + "CLBLM_NE2A0" + ], + [ + "BRAM_NW2A3_4", + "CLBLM_NW2A3" + ], + [ + "BRAM_SW4A3_4", + "CLBLM_SW4A3" + ], + [ + "BRAM_EE4B3_4", + "CLBLM_EE4B3" + ], + [ + "BRAM_EE2A3_4", + "CLBLM_EE2A3" + ], + [ + "BRAM_SE4BEG2_4", + "CLBLM_SE4BEG2" + ], + [ + "BRAM_SE2A2_4", + "CLBLM_SE2A2" + ], + [ + "BRAM_WW4END2_4", + "CLBLM_WW4END2" + ], + [ + "BRAM_EL1BEG1_4", + "CLBLM_EL1BEG1" + ], + [ + "BRAM_EE4A1_4", + "CLBLM_EE4A1" + ], + [ + "BRAM_WL1END1_4", + "CLBLM_WL1END1" + ], + [ + "BRAM_EE2BEG0_4", + "CLBLM_EE2BEG0" + ], + [ + "BRAM_LH2_4", + "CLBLM_LH2" + ], + [ + "BRAM_NW2A2_4", + "CLBLM_NW2A2" + ], + [ + "BRAM_SW2A2_4", + "CLBLM_SW2A2" + ], + [ + "BRAM_NE4C3_4", + "CLBLM_NE4C3" + ], + [ + "BRAM_SE2A1_4", + "CLBLM_SE2A1" + ], + [ + "BRAM_WW4END0_4", + "CLBLM_WW4END0" + ], + [ + "BRAM_SW2A0_4", + "CLBLM_SW2A0" + ], + [ + "BRAM_WW2A0_4", + "CLBLM_WW2A0" + ], + [ + "BRAM_EE2BEG1_4", + "CLBLM_EE2BEG1" + ], + [ + "BRAM_SW4END0_4", + "CLBLM_SW4END0" + ], + [ + "BRAM_SE4C0_4", + "CLBLM_SE4C0" + ], + [ + "BRAM_EE4A3_4", + "CLBLM_EE4A3" + ], + [ + "BRAM_SE4BEG3_4", + "CLBLM_SE4BEG3" + ], + [ + "BRAM_NW4A1_4", + "CLBLM_NW4A1" + ], + [ + "BRAM_EE2A1_4", + "CLBLM_EE2A1" + ], + [ + "BRAM_LH4_4", + "CLBLM_LH4" + ], + [ + "BRAM_WW4END1_4", + "CLBLM_WW4END1" + ], + [ + "BRAM_WL1END3_4", + "CLBLM_WL1END3" + ], + [ + "BRAM_WR1END0_4", + "CLBLM_WR1END0" + ], + [ + "BRAM_WW2A2_4", + "CLBLM_WW2A2" + ], + [ + "BRAM_SW4END3_4", + "CLBLM_SW4END3" + ], + [ + "BRAM_EE4C3_4", + "CLBLM_EE4C3" + ], + [ + "BRAM_LH12_4", + "CLBLM_LH12" + ], + [ + "BRAM_NE4C0_4", + "CLBLM_NE4C0" + ], + [ + "BRAM_LH7_4", + "CLBLM_LH7" + ], + [ + "BRAM_ER1BEG1_4", + "CLBLM_ER1BEG1" + ], + [ + "BRAM_SE2A0_4", + "CLBLM_SE2A0" + ], + [ + "BRAM_SE4BEG0_4", + "CLBLM_SE4BEG0" + ], + [ + "BRAM_NE4C1_4", + "CLBLM_NE4C1" + ], + [ + "BRAM_WW2END2_4", + "CLBLM_WW2END2" + ], + [ + "BRAM_SW2A3_4", + "CLBLM_SW2A3" + ], + [ + "BRAM_SW4A0_4", + "CLBLM_SW4A0" + ], + [ + "BRAM_LH9_4", + "CLBLM_LH9" + ], + [ + "BRAM_WW2END0_4", + "CLBLM_WW2END0" + ], + [ + "BRAM_EE4C1_4", + "CLBLM_EE4C1" + ], + [ + "BRAM_WW2A3_4", + "CLBLM_WW2A3" + ], + [ + "BRAM_NE2A2_4", + "CLBLM_NE2A2" + ], + [ + "BRAM_MONITOR_N_4", + "CLBLM_MONITOR_N" + ], + [ + "BRAM_WW4C0_4", + "CLBLM_WW4C0" + ], + [ + "BRAM_SW2A1_4", + "CLBLM_SW2A1" + ], + [ + "BRAM_EE4BEG0_4", + "CLBLM_EE4BEG0" + ], + [ + "BRAM_SE4C2_4", + "CLBLM_SE4C2" + ], + [ + "BRAM_LH3_4", + "CLBLM_LH3" + ], + [ + "BRAM_EL1BEG0_4", + "CLBLM_EL1BEG0" + ], + [ + "BRAM_NW2A0_4", + "CLBLM_NW2A0" + ], + [ + "BRAM_NE4BEG2_4", + "CLBLM_NE4BEG2" + ], + [ + "BRAM_SE4BEG1_4", + "CLBLM_SE4BEG1" + ], + [ + "BRAM_WW4B3_4", + "CLBLM_WW4B3" + ], + [ + "BRAM_SW4A2_4", + "CLBLM_SW4A2" + ], + [ + "BRAM_WW4A0_4", + "CLBLM_WW4A0" + ], + [ + "BRAM_NW4END1_4", + "CLBLM_NW4END1" + ], + [ + "BRAM_WW4C1_4", + "CLBLM_WW4C1" + ], + [ + "BRAM_EL1BEG3_4", + "CLBLM_EL1BEG3" + ], + [ + "BRAM_WR1END2_4", + "CLBLM_WR1END2" + ], + [ + "BRAM_SW4END2_4", + "CLBLM_SW4END2" + ], + [ + "BRAM_WW4C2_4", + "CLBLM_WW4C2" + ], + [ + "BRAM_WR1END3_4", + "CLBLM_WR1END3" + ], + [ + "BRAM_EE4B2_4", + "CLBLM_EE4B2" + ], + [ + "BRAM_WW4B1_4", + "CLBLM_WW4B1" + ], + [ + "BRAM_LH1_4", + "CLBLM_LH1" + ], + [ + "BRAM_SE2A3_4", + "CLBLM_SE2A3" + ], + [ + "BRAM_NW4END0_4", + "CLBLM_NW4END0" + ], + [ + "BRAM_WR1END1_4", + "CLBLM_WR1END1" + ], + [ + "BRAM_EE2BEG3_4", + "CLBLM_EE2BEG3" + ], + [ + "BRAM_NE4C2_4", + "CLBLM_NE4C2" + ], + [ + "BRAM_EE2A2_4", + "CLBLM_EE2A2" + ], + [ + "BRAM_EE4B0_4", + "CLBLM_EE4B0" + ], + [ + "BRAM_SW4A1_4", + "CLBLM_SW4A1" + ], + [ + "BRAM_ER1BEG2_4", + "CLBLM_ER1BEG2" + ], + [ + "BRAM_WL1END2_4", + "CLBLM_WL1END2" + ], + [ + "BRAM_EE4A2_4", + "CLBLM_EE4A2" + ], + [ + "BRAM_EE4C0_4", + "CLBLM_EE4C0" + ], + [ + "BRAM_EE4A0_4", + "CLBLM_EE4A0" + ], + [ + "BRAM_LH6_4", + "CLBLM_LH6" + ], + [ + "BRAM_WW4C3_4", + "CLBLM_WW4C3" + ], + [ + "BRAM_EE2A0_4", + "CLBLM_EE2A0" + ], + [ + "BRAM_SW4END1_4", + "CLBLM_SW4END1" + ], + [ + "BRAM_LH8_4", + "CLBLM_LH8" + ], + [ + "BRAM_NW4END2_4", + "CLBLM_NW4END2" + ], + [ + "BRAM_NW2A1_4", + "CLBLM_NW2A1" + ], + [ + "BRAM_ER1BEG0_4", + "CLBLM_ER1BEG0" + ], + [ + "BRAM_EE2BEG2_4", + "CLBLM_EE2BEG2" + ], + [ + "BRAM_ER1BEG3_4", + "CLBLM_ER1BEG3" + ], + [ + "BRAM_EE4B1_4", + "CLBLM_EE4B1" + ], + [ + "BRAM_WW4A2_4", + "CLBLM_WW4A2" + ], + [ + "BRAM_NW4A3_4", + "CLBLM_NW4A3" + ], + [ + "BRAM_WW4B2_4", + "CLBLM_WW4B2" + ], + [ + "BRAM_LH11_4", + "CLBLM_LH11" + ], + [ + "BRAM_WL1END0_4", + "CLBLM_WL1END0" + ], + [ + "BRAM_MONITOR_P_4", + "CLBLM_MONITOR_P" + ], + [ + "BRAM_NW4A2_4", + "CLBLM_NW4A2" + ], + [ + "BRAM_WW4A1_4", + "CLBLM_WW4A1" + ], + [ + "BRAM_WW2END3_4", + "CLBLM_WW2END3" + ], + [ + "BRAM_NE2A3_4", + "CLBLM_NE2A3" + ], + [ + "BRAM_LH5_4", + "CLBLM_LH5" + ], + [ + "BRAM_NE4BEG0_4", + "CLBLM_NE4BEG0" + ], + [ + "BRAM_WW2END1_4", + "CLBLM_WW2END1" + ], + [ + "BRAM_WW4A3_4", + "CLBLM_WW4A3" + ], + [ + "BRAM_NW4A0_4", + "CLBLM_NW4A0" + ], + [ + "BRAM_EE4C2_4", + "CLBLM_EE4C2" + ], + [ + "BRAM_EE4BEG1_4", + "CLBLM_EE4BEG1" + ], + [ + "BRAM_NE4BEG3_4", + "CLBLM_NE4BEG3" + ], + [ + "BRAM_EL1BEG2_4", + "CLBLM_EL1BEG2" + ], + [ + "BRAM_WW4END3_4", + "CLBLM_WW4END3" + ], + [ + "BRAM_NE2A1_4", + "CLBLM_NE2A1" + ], + [ + "BRAM_EE4BEG3_4", + "CLBLM_EE4BEG3" + ], + [ + "BRAM_NW4END3_4", + "CLBLM_NW4END3" + ], + [ + "BRAM_EE4BEG2_4", + "CLBLM_EE4BEG2" + ], + [ + "BRAM_WW2A1_4", + "CLBLM_WW2A1" + ] ] }, { - "wire_pairs": [ - [ - "HCLK_CK_INOUT_L2", - "HCLK_CK_OUTIN_R6" - ], - [ - "HCLK_CK_IN0", - "HCLK_CK_IN0" - ], - [ - "HCLK_CK_IN3", - "HCLK_CK_IN3" - ], - [ - "HCLK_INT_PERFCLK3", - "HCLK_INT_PERFCLK3" - ], - [ - "HCLK_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CK_INOUT_L5", - "HCLK_CK_OUTIN_R1" - ], - [ - "HCLK_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CK_INOUT_L0", - "HCLK_CK_OUTIN_R4" - ], - [ - "HCLK_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_CK_OUTIN_L5", - "HCLK_CK_INOUT_R5" - ], - [ - "HCLK_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_CK_INOUT_L6", - "HCLK_CK_OUTIN_R2" - ], - [ - "HCLK_CK_INOUT_L4", - "HCLK_CK_OUTIN_R0" - ], - [ - "HCLK_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CK_OUTIN_L4", - "HCLK_CK_INOUT_R4" - ], - [ - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_CK_OUTIN_L2", - "HCLK_CK_INOUT_R2" - ], - [ - "HCLK_CCIO3", - "HCLK_CCIO3" - ], - [ - "HCLK_CK_INOUT_L3", - "HCLK_CK_OUTIN_R7" - ], - [ - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK2" - ], - [ - "HCLK_CK_OUTIN_L0", - "HCLK_CK_INOUT_R0" - ], - [ - "HCLK_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_CK_IN1", - "HCLK_CK_IN1" - ], - [ - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_CK_BUFRCLK3", - "HCLK_CK_BUFRCLK3" - ], - [ - "HCLK_CCIO1", - "HCLK_CCIO1" - ], - [ - "HCLK_CK_OUTIN_L7", - "HCLK_CK_INOUT_R7" - ], - [ - "HCLK_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CCIO2", - "HCLK_CCIO2" - ], - [ - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CK_OUTIN_L3", - "HCLK_CK_INOUT_R3" - ], - [ - "HCLK_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK0" - ], - [ - "HCLK_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ], - [ - "HCLK_INT_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - "HCLK_INT_PERFCLK1", - "HCLK_INT_PERFCLK1" - ], - [ - "HCLK_INT_PERFCLK2", - "HCLK_INT_PERFCLK2" - ], - [ - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_CK_OUTIN_L6", - "HCLK_CK_INOUT_R6" - ], - [ - "HCLK_CK_OUTIN_L1", - "HCLK_CK_INOUT_R1" - ], - [ - "HCLK_CK_INOUT_L7", - "HCLK_CK_OUTIN_R3" - ], - [ - "HCLK_CK_INOUT_L1", - "HCLK_CK_OUTIN_R5" - ], - [ - "HCLK_CCIO0", - "HCLK_CCIO0" - ], - [ - "HCLK_CK_IN2", - "HCLK_CK_IN2" - ] - ], - "tile_types": [ - "HCLK_L", - "HCLK_R" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "INT_INTERFACE_WW2A2", - "PCIE_WW2A2_3" - ], - [ - "INT_INTERFACE_EE4C2", - "PCIE_EE4C2_3" - ], - [ - "INT_INTERFACE_LH7", - "PCIE_LH7_3" - ], - [ - "INT_INTERFACE_EE4BEG3", - "PCIE_EE4BEG3_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT34", - "PCIE_IMUX34_R_3" - ], - [ - "INT_INTERFACE_WW4A2", - "PCIE_WW4A2_3" - ], - [ - "INT_INTERFACE_NW2A2", - "PCIE_NW2A2_3" - ], - [ - "INT_INTERFACE_NW4END2", - "PCIE_NW4END2_3" - ], - [ - "INT_INTERFACE_WW2A0", - "PCIE_WW2A0_3" - ], - [ - "INT_INTERFACE_SW4END1", - "PCIE_SW4END1_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT39", - "PCIE_IMUX39_R_3" - ], - [ - "INT_INTERFACE_NE2A0", - "PCIE_NE2A0_3" - ], - [ - "INT_INTERFACE_EE4BEG1", - "PCIE_EE4BEG1_3" - ], - [ - "INT_INTERFACE_SE4C0", - "PCIE_SE4C0_3" - ], - [ - "INT_INTERFACE_ER1BEG2", - "PCIE_ER1BEG2_3" - ], - [ - "INT_INTERFACE_EE2A3", - "PCIE_EE2A3_3" - ], - [ - "INT_INTERFACE_EE4C3", - "PCIE_EE4C3_3" - ], - [ - "INT_INTERFACE_CLK0", - "PCIE_CLK0_R_3" - ], - [ - "INT_INTERFACE_FAN1", - "PCIE_FAN1_R_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_OUT24", - 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"CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ] - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMVIOB" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ] - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMV2_SVT" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ] - ], - "tile_types": [ - "CLK_FEED", - "CLK_MTBF2" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "NN2BEG3", - "T_TERM_UTURN_INT_SS2A0" - ], - [ - "ER1BEG_S0", - "T_TERM_UTURN_INT_ER1BEG_S0" - ], - [ - "NL1BEG0", - "T_TERM_UTURN_INT_SR1END3" - ], - [ - "LVB1", - "T_TERM_UTURN_INT_LVB1" - ], - [ - "SW6B2", - "T_TERM_UTURN_INT_SW6B2" - ], - [ - "NE6A2", - "T_TERM_UTURN_INT_SE6B1" - ], - [ - "WR1BEG_S0", - "T_TERM_UTURN_INT_WR1BEG_S0" - ], - [ - "NN2A0", - "T_TERM_UTURN_INT_SS2END3" - ], - [ - "SS6E0", - "T_TERM_UTURN_INT_SS6E0" - ], - [ - "ER1END3", - "T_TERM_UTURN_INT_ER1END3" - ], - [ - "SL1END2", - "T_TERM_UTURN_INT_SL1END2" - ], - [ - "SS2A1", - "T_TERM_UTURN_INT_SS2A1" - ], - [ - "SW2A1", - "T_TERM_UTURN_INT_SW2A1" - ], - [ - "NN6D1", - "T_TERM_UTURN_INT_SS6E2" - ], - [ - "LV12", - "T_TERM_INT_UTURN_LV_R5" - ], - [ - "SL1END0", - "T_TERM_UTURN_INT_SL1END0" - ], - [ - "NN6A2", - "T_TERM_UTURN_INT_SS6B1" - ], - [ - "NE6D1", - "T_TERM_UTURN_INT_SE6E2" - ], - [ - "SS6A0", - "T_TERM_UTURN_INT_SS6A0" - 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"GTPE2_IMUX42_1", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX22_1", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_CTRL1_1", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX9_1", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_LOGIC_OUTS_B23_1", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_IMUX12_1", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX21_1", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_LOGIC_OUTS_B18_1", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_IMUX20_1", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX46_1", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_CLK0_1", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_LOGIC_OUTS_B16_1", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_IMUX41_1", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX37_1", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX32_1", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B15_1", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_IMUX24_1", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_CLK1_1", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX19_1", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_FAN4_1", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX4_1", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX2_1", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_CTRL0_1", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_FAN1_1", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX0_1", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX28_1", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX47_1", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX25_1", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX26_1", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_BYP4_1", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX35_1", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX1_1", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_LOGIC_OUTS_B17_1", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX8_1", - "VBRK_EXT_IMUX8" - ] - ], - "tile_types": [ - "GTP_CHANNEL_2", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - 4 - ] - }, - { - "wire_pairs": [ - [ - "WW4B0", - "INT_INTERFACE_WW4C0" - ], - [ - "SW6E2", - "INT_INTERFACE_SW4END2" - ], - [ - "WR1BEG3", - "INT_INTERFACE_WR1END3" - ], - [ - "WR1BEG2", - "INT_INTERFACE_WR1END2" - ], - [ - "IMUX_L32", - "PCIE_INT_INTERFACE_IMUX_L32" - ], - [ - "LOGIC_OUTS_L12", - "INT_INTERFACE_LOGIC_OUTS_L12" - ], - [ - "IMUX_L10", - "PCIE_INT_INTERFACE_IMUX_L10" - ], - [ - "NW6E3", - "INT_INTERFACE_NW4END3" - ], - [ - "FAN_L6", - "INT_INTERFACE_FAN6" - ], - [ - "WW4B2", - "INT_INTERFACE_WW4C2" - ], - [ - "SE6A0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "IMUX_L39", - "PCIE_INT_INTERFACE_IMUX_L39" - ], - [ - "IMUX_L13", - "PCIE_INT_INTERFACE_IMUX_L13" - ], - [ - "EL1END3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "LOGIC_OUTS_L10", - "INT_INTERFACE_LOGIC_OUTS_L10" - ], - [ - "CTRL_L0", - "INT_INTERFACE_CTRL0" - ], - [ - "WW2BEG2", - "INT_INTERFACE_WW2A2" - ], - [ - "EE4END1", - "INT_INTERFACE_EE4C1" - ], - [ - "WW2BEG3", - "INT_INTERFACE_WW2A3" - ], - [ - "WW4BEG2", - "INT_INTERFACE_WW4A2" - ], - [ - "EE4A0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "NE6A0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "WW4B1", - "INT_INTERFACE_WW4C1" - ], - [ - "BYP_L4", - "INT_INTERFACE_BYP4" - ], - [ - "NW6BEG2", - "INT_INTERFACE_NW4A2" - ], - [ - "LOGIC_OUTS_L8", - "INT_INTERFACE_LOGIC_OUTS_L8" - ], - [ - "IMUX_L19", - "PCIE_INT_INTERFACE_IMUX_L19" - ], - [ - "IMUX_L22", - "PCIE_INT_INTERFACE_IMUX_L22" - ], - [ - "FAN_L7", - "INT_INTERFACE_FAN7" - ], - [ - "EE2A3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "IMUX_L8", - "PCIE_INT_INTERFACE_IMUX_L8" - ], - [ - "LOGIC_OUTS_L19", - "INT_INTERFACE_LOGIC_OUTS_L19" - ], - [ - "LH3", - "INT_INTERFACE_LH4" - ], - [ - "IMUX_L17", - "PCIE_INT_INTERFACE_IMUX_L17" - ], - [ - "WR1BEG0", - "INT_INTERFACE_WR1END0" - ], - [ - "BYP_L2", - "INT_INTERFACE_BYP2" - ], - [ - "ER1END2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "BYP_L3", - "INT_INTERFACE_BYP3" - ], - [ - "ER1END1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "IMUX_L23", - "PCIE_INT_INTERFACE_IMUX_L23" - ], - [ - "WL1BEG1", - "INT_INTERFACE_WL1END1" - ], - [ - "NW6E1", - "INT_INTERFACE_NW4END1" - ], - [ - "LH11", - "INT_INTERFACE_LH12" - ], - [ - "LOGIC_OUTS_L9", - "INT_INTERFACE_LOGIC_OUTS_L9" - ], - [ - "BYP_L0", - "INT_INTERFACE_BYP0" - ], - [ - "WW4A3", - "INT_INTERFACE_WW4B3" - ], - [ - "FAN_L4", - "INT_INTERFACE_FAN4" - ], - [ - "LH9", - "INT_INTERFACE_LH10" - ], - [ - "LOGIC_OUTS_L11", - "INT_INTERFACE_LOGIC_OUTS_L11" - ], - [ - "EE2END1", - "INT_INTERFACE_EE2A1" - ], - [ - "SW6E3", - "INT_INTERFACE_SW4END3" - ], - [ - "SE6A3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "IMUX_L41", - "PCIE_INT_INTERFACE_IMUX_L41" - ], - [ - "LOGIC_OUTS_L6", - "INT_INTERFACE_LOGIC_OUTS_L6" - ], - [ - "EE4A1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "LOGIC_OUTS_L7", - "INT_INTERFACE_LOGIC_OUTS_L7" - ], - [ - "CLK_L0", - "INT_INTERFACE_CLK0" - ], - [ - "NE6END0", - "INT_INTERFACE_NE4C0" - ], - [ - "SE2END1", - "INT_INTERFACE_SE2A1" - ], - [ - "SE2END0", - "INT_INTERFACE_SE2A0" - ], - [ - "WL1BEG2", - "INT_INTERFACE_WL1END2" - ], - [ - "LOGIC_OUTS_L21", - "INT_INTERFACE_LOGIC_OUTS_L21" - ], - [ - "EE2END2", - "INT_INTERFACE_EE2A2" - ], - [ - "LH1", - "INT_INTERFACE_LH2" - ], - [ - "LH7", - "INT_INTERFACE_LH8" - ], - [ - "SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "IMUX_L14", - "PCIE_INT_INTERFACE_IMUX_L14" - ], - [ - "WL1BEG3", - "INT_INTERFACE_WL1END3" - ], - [ - "SE6A1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "BYP_L6", - "INT_INTERFACE_BYP6" - ], - [ - "FAN_L5", - "INT_INTERFACE_FAN5" - ], - [ - "EE4A2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "IMUX_L33", - "PCIE_INT_INTERFACE_IMUX_L33" - ], - [ - "NE2END1", - "INT_INTERFACE_NE2A1" - ], - [ - "SE6END2", - "INT_INTERFACE_SE4C2" - ], - [ - "IMUX_L40", - "PCIE_INT_INTERFACE_IMUX_L40" - ], - [ - "NE6END3", - "INT_INTERFACE_NE4C3" - ], - [ - "EE4C2", - "INT_INTERFACE_EE4B2" - ], - [ - "EE4END2", - "INT_INTERFACE_EE4C2" - ], - [ - "IMUX_L26", - "PCIE_INT_INTERFACE_IMUX_L26" - ], - [ - "SW6E0", - "INT_INTERFACE_SW4END0" - ], - [ - "IMUX_L11", - "PCIE_INT_INTERFACE_IMUX_L11" - ], - [ - "WR1BEG1", - "INT_INTERFACE_WR1END1" - ], - [ - "NE6A1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "SW6BEG2", - "INT_INTERFACE_SW4A2" - ], - [ - "NW6BEG1", - "INT_INTERFACE_NW4A1" - ], - [ - "BYP_L1", - "INT_INTERFACE_BYP1" - ], - [ - "IMUX_L9", - "PCIE_INT_INTERFACE_IMUX_L9" - ], - [ - "WW2A3", - "INT_INTERFACE_WW2END3" - ], - [ - "IMUX_L29", - "PCIE_INT_INTERFACE_IMUX_L29" - ], - [ - "LOGIC_OUTS_L22", - "INT_INTERFACE_LOGIC_OUTS_L22" - ], - [ - "SW6BEG0", - "INT_INTERFACE_SW4A0" - ], - [ - "IMUX_L7", - "PCIE_INT_INTERFACE_IMUX_L7" - ], - [ - "WW4BEG0", - "INT_INTERFACE_WW4A0" - ], - [ - "WW2A1", - "INT_INTERFACE_WW2END1" - ], - [ - "WW4BEG1", - "INT_INTERFACE_WW4A1" - ], - [ - "WW2BEG1", - "INT_INTERFACE_WW2A1" - ], - [ - "IMUX_L28", - "PCIE_INT_INTERFACE_IMUX_L28" - ], - [ - "IMUX_L5", - "PCIE_INT_INTERFACE_IMUX_L5" - ], - [ - "SW6BEG3", - "INT_INTERFACE_SW4A3" - ], - [ - "NE6END1", - "INT_INTERFACE_NE4C1" - ], - [ - "IMUX_L25", - "PCIE_INT_INTERFACE_IMUX_L25" - ], - [ - "LH5", - "INT_INTERFACE_LH6" - ], - [ - "IMUX_L35", - "PCIE_INT_INTERFACE_IMUX_L35" - ], - [ - "FAN_L2", - "INT_INTERFACE_FAN2" - ], - [ - "WW4C1", - "INT_INTERFACE_WW4END1" - ], - [ - "LOGIC_OUTS_L14", - "INT_INTERFACE_LOGIC_OUTS_L14" - ], - [ - "IMUX_L6", - "PCIE_INT_INTERFACE_IMUX_L6" - ], - [ - "SE6A2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "IMUX_L15", - "PCIE_INT_INTERFACE_IMUX_L15" - ], - [ - "EE4END0", - "INT_INTERFACE_EE4C0" - ], - [ - "EE4B0", - "INT_INTERFACE_EE4A0" - ], - [ - "LOGIC_OUTS_L17", - "INT_INTERFACE_LOGIC_OUTS_L17" - ], - [ - "EL1END1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "LOGIC_OUTS_L13", - "INT_INTERFACE_LOGIC_OUTS_L13" - ], - [ - "IMUX_L30", - "PCIE_INT_INTERFACE_IMUX_L30" - ], - [ - "IMUX_L43", - "PCIE_INT_INTERFACE_IMUX_L43" - ], - [ - "BYP_L5", - "INT_INTERFACE_BYP5" - ], - [ - "LOGIC_OUTS_L23", - "INT_INTERFACE_LOGIC_OUTS_L23" - ], - [ - "LH4", - "INT_INTERFACE_LH5" - ], - [ - "IMUX_L4", - "PCIE_INT_INTERFACE_IMUX_L4" - ], - [ - "LOGIC_OUTS_L0", - "INT_INTERFACE_LOGIC_OUTS_L0" - ], - [ - "FAN_L3", - "INT_INTERFACE_FAN3" - ], - [ - "LH10", - "INT_INTERFACE_LH11" - ], - [ - "SE6END0", - "INT_INTERFACE_SE4C0" - ], - [ - "EE4C0", - "INT_INTERFACE_EE4B0" - ], - [ - "LOGIC_OUTS_L4", - "INT_INTERFACE_LOGIC_OUTS_L4" - ], - [ - "IMUX_L47", - "PCIE_INT_INTERFACE_IMUX_L47" - ], - [ - "IMUX_L27", - "PCIE_INT_INTERFACE_IMUX_L27" - ], - [ - "SW6BEG1", - "INT_INTERFACE_SW4A1" - ], [ "LOGIC_OUTS_L15", "INT_INTERFACE_LOGIC_OUTS_L15" @@ -72074,42204 +4214,1852 @@ "INT_INTERFACE_EE4B3" ], [ - "EE4B3", - "INT_INTERFACE_EE4A3" - ], - [ - "WW4BEG3", - "INT_INTERFACE_WW4A3" - ], - [ - "IMUX_L42", - "PCIE_INT_INTERFACE_IMUX_L42" - ], - [ - "WW4C3", - "INT_INTERFACE_WW4END3" - ], - [ - "LH8", - "INT_INTERFACE_LH9" - ], - [ - "NE2END0", - "INT_INTERFACE_NE2A0" - ], - [ - "NE2END3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_L1", - "INT_INTERFACE_CLK1" - ], - [ - "EE2A2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "NW2A1", - "INT_INTERFACE_NW2A1" - ], - [ - "NW6E0", - "INT_INTERFACE_NW4END0" - ], - [ - "IMUX_L3", - "PCIE_INT_INTERFACE_IMUX_L3" - ], - [ - "ER1END0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CTRL_L1", - "INT_INTERFACE_CTRL1" - ], - [ - "NW2A3", - "INT_INTERFACE_NW2A3" - ], - [ - "SW2A1", - "INT_INTERFACE_SW2A1" - ], - [ - "EE2END0", - "INT_INTERFACE_EE2A0" - ], - [ - "LOGIC_OUTS_L16", - "INT_INTERFACE_LOGIC_OUTS_L16" - ], - [ - "WW4A1", - "INT_INTERFACE_WW4B1" - ], - [ - "IMUX_L18", - "PCIE_INT_INTERFACE_IMUX_L18" - ], - [ - "MONITOR_N", - "INT_INTERFACE_MONITOR_N" - ], - [ - "IMUX_L21", - "PCIE_INT_INTERFACE_IMUX_L21" - ], - [ - "WW4A2", - "INT_INTERFACE_WW4B2" - ], - [ - "NW6BEG0", - "INT_INTERFACE_NW4A0" - ], - [ - "IMUX_L46", - "PCIE_INT_INTERFACE_IMUX_L46" - ], - [ - "SW2A2", - "INT_INTERFACE_SW2A2" - ], - [ - "EE2A0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "WW4C2", - "INT_INTERFACE_WW4END2" - ], - [ - "IMUX_L37", - "PCIE_INT_INTERFACE_IMUX_L37" - ], - [ - "NW2A0", - "INT_INTERFACE_NW2A0" + "SE2END3", + "INT_INTERFACE_SE2A3" ], [ "LOGIC_OUTS_L3", "INT_INTERFACE_LOGIC_OUTS_L3" ], [ - "IMUX_L1", - "PCIE_INT_INTERFACE_IMUX_L1" - ], - [ - "IMUX_L12", - "PCIE_INT_INTERFACE_IMUX_L12" - ], - [ - "SW6E1", - "INT_INTERFACE_SW4END1" - ], - [ - "IMUX_L2", - "PCIE_INT_INTERFACE_IMUX_L2" - ], - [ - "NW6E2", - "INT_INTERFACE_NW4END2" - ], - [ - "EE4C1", - "INT_INTERFACE_EE4B1" - ], - [ - "EL1END2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "EL1END0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "IMUX_L45", - "PCIE_INT_INTERFACE_IMUX_L45" - ], - [ - "IMUX_L38", - "PCIE_INT_INTERFACE_IMUX_L38" - ], - [ - "WW4A0", - "INT_INTERFACE_WW4B0" - ], - [ - "LOGIC_OUTS_L2", - "INT_INTERFACE_LOGIC_OUTS_L2" - ], - [ - "IMUX_L0", - "PCIE_INT_INTERFACE_IMUX_L0" - ], - [ - "EE2A1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "WW4C0", - "INT_INTERFACE_WW4END0" - ], - [ - "IMUX_L34", - "PCIE_INT_INTERFACE_IMUX_L34" - ], - [ - "FAN_L1", - "INT_INTERFACE_FAN1" - ], - [ - "LOGIC_OUTS_L20", - "INT_INTERFACE_LOGIC_OUTS_L20" - ], - [ - "IMUX_L44", - "PCIE_INT_INTERFACE_IMUX_L44" - ], - [ - "EE4B1", - "INT_INTERFACE_EE4A1" - ], - [ - "ER1END3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "IMUX_L20", - "PCIE_INT_INTERFACE_IMUX_L20" + "IMUX_L4", + "INT_INTERFACE_IMUX4" ], [ "IMUX_L16", - "PCIE_INT_INTERFACE_IMUX_L16" - ], - [ - "WW2A2", - "INT_INTERFACE_WW2END2" - ], - [ - "EE2END3", - "INT_INTERFACE_EE2A3" - ], - [ - "MONITOR_P", - "INT_INTERFACE_MONITOR_P" - ], - [ - "NE2END2", - "INT_INTERFACE_NE2A2" - ], - [ - "LOGIC_OUTS_L5", - "INT_INTERFACE_LOGIC_OUTS_L5" - ], - [ - "FAN_L0", - "INT_INTERFACE_FAN0" - ], - [ - "WW4B3", - "INT_INTERFACE_WW4C3" - ], - [ - "NE6A2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "EE4END3", - "INT_INTERFACE_EE4C3" - ], - [ - "SE6END1", - "INT_INTERFACE_SE4C1" - ], - [ - "LOGIC_OUTS_L1", - "INT_INTERFACE_LOGIC_OUTS_L1" - ], - [ - "EE4A3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "LH6", - "INT_INTERFACE_LH7" - ], - [ - "WW2A0", - "INT_INTERFACE_WW2END0" - ], - [ - "IMUX_L36", - "PCIE_INT_INTERFACE_IMUX_L36" - ], - [ - "BYP_L7", - "INT_INTERFACE_BYP7" - ], - [ - "WW2BEG0", - "INT_INTERFACE_WW2A0" - ], - [ - "LH0", - "INT_INTERFACE_LH1" - ], - [ - "SE2END2", - "INT_INTERFACE_SE2A2" - ], - [ - "SW2A0", - "INT_INTERFACE_SW2A0" - ], - [ - "LH2", - "INT_INTERFACE_LH3" - ], - [ - "LOGIC_OUTS_L18", - "INT_INTERFACE_LOGIC_OUTS_L18" - ], - [ - "IMUX_L31", - "PCIE_INT_INTERFACE_IMUX_L31" - ], - [ - "SE6END3", - "INT_INTERFACE_SE4C3" - ], - [ - "NE6A3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "NW6BEG3", - "INT_INTERFACE_NW4A3" - ], - [ - "IMUX_L24", - "PCIE_INT_INTERFACE_IMUX_L24" - ], - [ - "WL1BEG0", - "INT_INTERFACE_WL1END0" - ], - [ - "NW2A2", - "INT_INTERFACE_NW2A2" - ], - [ - "SE2END3", - "INT_INTERFACE_SE2A3" + "INT_INTERFACE_IMUX16" ], [ "EE4B2", "INT_INTERFACE_EE4A2" ], [ - "NE6END2", - "INT_INTERFACE_NE4C2" - ] - ], - "tile_types": [ - "INT_L", - "PCIE_INT_INTERFACE_L" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_NW4END2_0", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_0", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_HROW_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_SE2A0_0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_BUFG_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_BUFG_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_LH1_0", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_BUFG_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_BUFG_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WR1END3_0", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_BUFG_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_0", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_BUFG_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_BUFG_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_BUFG_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_BUFG_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_SW4END2_0", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_BUFG_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_0", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_BUFG_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_BUFG_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_BUFG_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_BUFG_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_BUFG_IMUX45_0", - "INT_INTERFACE_IMUX45" + "WW4B2", + "INT_INTERFACE_WW4C2" ], [ - "CLK_BUFG_IMUX22_0", + "IMUX_L22", "INT_INTERFACE_IMUX22" ], [ - "CLK_HROW_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_SE4C0_0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_SW4END0_0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_BUFG_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_BUFG_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_BUFG_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_0", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_BUFG_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_BUFG_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_BUFG_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_BUFG_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_BUFG_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_LH9_0", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_WL1END2_0", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_0", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_BUFG_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_BUFG_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_BUFG_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_BUFG_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_BUFG_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_BUFG_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_BUFG_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_BUFG_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_BUFG_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_BUFG_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_BUFG_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_BUFG_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_BUFG_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_BUFG_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_0", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_LH5_0", + "LH4", "INT_INTERFACE_LH5" ], [ - "CLK_BUFG_LOGIC_OUTS_B5_0", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_BUFG_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_BUFG_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_BUFG_IMUX16_0", - "INT_INTERFACE_IMUX16" - ] - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_CTRL0_5", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_EE4A2_5", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_NE4BEG1_5", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_NE4C2_5", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_EE4A3_5", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_WW2A3_5", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_WW4B2_5", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_WR1END0_5", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EL1BEG3_5", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_NW4END0_5", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_NW2A0_5", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE4B3_5", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_FAN6_5", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_CLK1_5", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_IMUX45_5", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_WL1END1_5", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_FAN7_5", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_SE4BEG1_5", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_IMUX18_5", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX34_5", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_WW2END1_5", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW4C3_5", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW2END3_5", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE2A0_5", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_IMUX33_5", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_LH7_5", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_BYP2_5", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_ER1BEG3_5", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_IMUX19_5", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_EE2BEG2_5", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_NW4A1_5", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_BYP5_5", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_SW2A3_5", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_WW4END2_5", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_IMUX14_5", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_BYP1_5", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SE4C2_5", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_NW2A3_5", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_BYP3_5", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NW2A2_5", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_BYP6_5", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX40_5", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_IMUX30_5", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX35_5", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_SE4C0_5", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_NW2A1_5", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_WR1END1_5", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4A3_5", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_IMUX32_5", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_NE2A2_5", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_NW4END1_5", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_IMUX27_5", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_IMUX25_5", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_IMUX28_5", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX46_5", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_ER1BEG2_5", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_LH2_5", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EE4BEG3_5", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_EE4BEG2_5", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW4C1_5", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_SW4A3_5", + "SW6BEG3", "INT_INTERFACE_SW4A3" ], [ - "CLK_HROW_SW4END1_5", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EL1BEG0_5", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_IMUX31_5", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_FAN2_5", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_SE4C1_5", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX2_5", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WW4END1_5", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_NE2A1_5", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_WW4END3_5", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_IMUX36_5", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_FAN1_5", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_EE4C0_5", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_LH3_5", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_WW4A1_5", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_BYP4_5", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_IMUX41_5", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_IMUX10_5", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_EE4BEG1_5", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_SE2A2_5", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2A1_5", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX21_5", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_SW4END3_5", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EE4B2_5", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_SW2A0_5", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH6_5", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_WW2A2_5", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_EE4BEG0_5", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_EE2A3_5", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_WW4B3_5", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_LH9_5", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NE2A0_5", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_WR1END2_5", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_IMUX23_5", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_WW4END0_5", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_SE2A0_5", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_SE4BEG2_5", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_EL1BEG2_5", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_EE2A1_5", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_CTRL1_5", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_WW2END0_5", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_LH4_5", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_IMUX47_5", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_IMUX16_5", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX4_5", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX8_5", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_CLK0_5", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_IMUX26_5", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_IMUX15_5", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_EE2A2_5", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_IMUX5_5", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX22_5", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_SW4A1_5", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_EE4C3_5", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_FAN3_5", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_ER1BEG1_5", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WR1END3_5", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_WW4A2_5", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NW4A2_5", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_SW4END0_5", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_EE4C1_5", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX9_5", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_NE4C0_5", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX3_5", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_SW4A0_5", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_LH5_5", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_LH12_5", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WL1END0_5", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_NE4BEG0_5", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_WL1END3_5", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_EE2BEG1_5", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_LH10_5", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_IMUX38_5", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX39_5", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_NE2A3_5", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_IMUX7_5", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE2BEG0_5", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_IMUX1_5", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_NE4C3_5", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_SE4BEG0_5", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_ER1BEG0_5", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SE4BEG3_5", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_SW4A2_5", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX6_5", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_LH11_5", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_BYP0_5", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_FAN5_5", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_NE4C1_5", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW4B1_5", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_NW4A3_5", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_EL1BEG1_5", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_NE4BEG2_5", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_EE4B1_5", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX20_5", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_NW4END3_5", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_IMUX12_5", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_EE2BEG3_5", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_EE4C2_5", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_BYP7_5", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WW2END2_5", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_IMUX11_5", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SE2A3_5", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_SW4END2_5", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_IMUX24_5", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_SE2A1_5", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_LH1_5", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_NW4END2_5", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_IMUX29_5", + "IMUX_L29", "INT_INTERFACE_IMUX29" ], [ - "CLK_HROW_IMUX37_5", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_WW2A0_5", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW4C0_5", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_WW4A0_5", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_SW2A1_5", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_SE4C3_5", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_EE4B0_5", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_IMUX44_5", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_SW2A2_5", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW4B0_5", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_WW4C2_5", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_EE4A0_5", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_FAN0_5", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_EE4A1_5", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_FAN4_5", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_LH8_5", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_IMUX13_5", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_IMUX17_5", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_IMUX43_5", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_WL1END2_5", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_NE4BEG3_5", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_NW4A0_5", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX42_5", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_IMUX0_5", - "INT_INTERFACE_IMUX0" - ] - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -2 - ] - }, - { - "wire_pairs": [ - [ - "CMT_FIFO_L_IMUX30_11", - "INT_INTERFACE_IMUX30" - ], - [ - "CMT_FIFO_LH1_11", - "INT_INTERFACE_LH1" - ], - [ - "CMT_FIFO_EE4A1_11", - "INT_INTERFACE_EE4A1" - ], - [ - "CMT_FIFO_L_IMUX8_11", - "INT_INTERFACE_IMUX8" - ], - [ - "CMT_FIFO_L_IMUX10_11", - "INT_INTERFACE_IMUX10" - ], - [ - "CMT_FIFO_WW4C2_11", - "INT_INTERFACE_WW4C2" - ], - [ - "CMT_FIFO_NE2A2_11", - "INT_INTERFACE_NE2A2" - ], - [ - "CMT_FIFO_NE2A1_11", - "INT_INTERFACE_NE2A1" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS6_11", - "INT_INTERFACE_LOGIC_OUTS_L_B6" - ], - [ - "CMT_FIFO_WW4A2_11", - "INT_INTERFACE_WW4A2" - ], - [ - "CMT_FIFO_NE4C2_11", - "INT_INTERFACE_NE4C2" - ], - [ - "CMT_FIFO_L_IMUX18_11", - "INT_INTERFACE_IMUX18" - ], - [ - "CMT_FIFO_L_BYP6_11", - "INT_INTERFACE_BYP6" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS19_11", - "INT_INTERFACE_LOGIC_OUTS_L_B19" - ], - [ - "CMT_FIFO_EE4B1_11", - "INT_INTERFACE_EE4B1" - ], - [ - "CMT_FIFO_L_FAN3_11", - "INT_INTERFACE_FAN3" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS8_11", - "INT_INTERFACE_LOGIC_OUTS_L_B8" - ], - [ - "CMT_FIFO_LH2_11", - "INT_INTERFACE_LH2" - ], - [ - "CMT_FIFO_WW4A3_11", - "INT_INTERFACE_WW4A3" - ], - [ - "CMT_FIFO_NE4C3_11", - "INT_INTERFACE_NE4C3" - ], - [ - "CMT_FIFO_LH11_11", - "INT_INTERFACE_LH11" - ], - [ - "CMT_FIFO_EE4B2_11", - "INT_INTERFACE_EE4B2" - ], - [ - "CMT_FIFO_L_BYP0_11", - "INT_INTERFACE_BYP0" - ], - [ - "CMT_FIFO_LH8_11", - "INT_INTERFACE_LH8" - ], - [ - "CMT_FIFO_EE2BEG2_11", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CMT_FIFO_SE4BEG0_11", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CMT_FIFO_WW4END3_11", - "INT_INTERFACE_WW4END3" - ], - [ - "CMT_FIFO_EE2A3_11", - "INT_INTERFACE_EE2A3" - ], - [ - "CMT_FIFO_L_BYP4_11", - "INT_INTERFACE_BYP4" - ], - [ - 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"tile_types": [ - "GTP_CHANNEL_2", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - 3 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_WW4END0_7", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_WW4C2_7", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_WW4C1_7", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_EE4B0_7", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_WR1END0_7", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_EE4C2_7", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_EE4BEG1_7", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_EE4A1_7", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_SE4C2_7", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_SW2A1_7", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_WR1END2_7", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW2A2_7", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_NW4END3_7", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_NW4END0_7", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_WW4C0_7", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_WW4END2_7", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_SE2A3_7", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_EL1BEG1_7", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_WW4B2_7", - "VBRK_WW4B2" - ], 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"CLK_HROW_CLK0_4", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_EE4B1_4", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SE4BEG2_4", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_SW2A3_4", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_IMUX5_4", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX8_4", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_IMUX41_4", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SW2A2_4", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_LH10_4", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_NE4BEG0_4", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_SE4BEG0_4", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_SE4C1_4", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_WR1END0_4", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_WW4C2_4", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_IMUX1_4", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_WW4A0_4", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NW2A0_4", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_IMUX29_4", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_NW4END2_4", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EE4C0_4", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE4BEG2_4", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_BYP2_4", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_WW4C0_4", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_IMUX6_4", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_SW2A1_4", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE4A2_4", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EL1BEG2_4", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_SE2A3_4", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_WW2END3_4", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE2BEG3_4", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_FAN4_4", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_IMUX14_4", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_EL1BEG1_4", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WW2END1_4", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WL1END3_4", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_BYP3_4", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NW2A1_4", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_NW4A2_4", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WR1END1_4", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_EE2BEG0_4", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_SW4END1_4", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_IMUX30_4", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX27_4", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_SW4A1_4", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_IMUX10_4", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_NW2A3_4", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_NE4C2_4", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_EE4BEG3_4", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_EE4A0_4", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_NW4A0_4", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WW2END2_4", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_IMUX47_4", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_EE4C3_4", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_IMUX24_4", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX35_4", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX20_4", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_SE4C0_4", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_LH7_4", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NE2A2_4", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_IMUX19_4", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX15_4", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_LH1_4", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX16_4", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4C1_4", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_SE4BEG1_4", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_EE4A1_4", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_NE4C1_4", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_MONITOR_P_4", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_IMUX12_4", + "IMUX_L12", "INT_INTERFACE_IMUX12" ], [ - "CLK_HROW_IMUX40_4", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_ER1BEG3_4", - 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- ], - [ - "PCIE_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "PCIE_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "PCIE_EE4C0_2", - "INT_INTERFACE_EE4C0" - ], - [ - "PCIE_CTRL1_R_2", - "INT_INTERFACE_CTRL1" - ], - [ - "PCIE_WR1END1_2", - "INT_INTERFACE_WR1END1" - ], - [ - "PCIE_EL1BEG0_2", - "INT_INTERFACE_EL1BEG0" - ], - [ - "PCIE_IMUX26_R_2", - "PCIE_INT_INTERFACE_IMUX_OUT26" - ], - [ - "PCIE_LOGIC_OUTS_B11_R_2", - "INT_INTERFACE_LOGIC_OUTS_B11" - ], - [ - "PCIE_FAN1_R_2", - "INT_INTERFACE_FAN1" - ], - [ - "PCIE_WW4C0_2", - "INT_INTERFACE_WW4C0" - ], - [ - "PCIE_LOGIC_OUTS_B21_R_2", - "INT_INTERFACE_LOGIC_OUTS_B21" - ], - [ - "PCIE_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "PCIE_IMUX18_R_2", - "PCIE_INT_INTERFACE_IMUX_OUT18" - ], - [ - "PCIE_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "PCIE_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "PCIE_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "PCIE_IMUX41_R_2", - "PCIE_INT_INTERFACE_IMUX_OUT41" - ], - [ - "PCIE_WR1END0_2", - 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], + [ + "WL1BEG1", "INT_INTERFACE_WL1END1" ], [ - "PCIE_IMUX2_L_10", - "PCIE_INT_INTERFACE_IMUX_L_OUT2" + "LOGIC_OUTS_L4", + "INT_INTERFACE_LOGIC_OUTS_L4" + ], + [ + "WW2BEG0", + "INT_INTERFACE_WW2A0" + ], + [ + "WL1BEG3", + "INT_INTERFACE_WL1END3" + ], + [ + "NE2END0", + "INT_INTERFACE_NE2A0" + ], + [ + "IMUX_L1", + "INT_INTERFACE_IMUX1" + ], + [ + "WW4BEG3", + "INT_INTERFACE_WW4A3" + ], + [ + "EE4A3", + "INT_INTERFACE_EE4BEG3" + ], + [ + "LH2", + "INT_INTERFACE_LH3" + ], + [ + "EE4END1", + "INT_INTERFACE_EE4C1" + ], + [ + "FAN_L7", + "INT_INTERFACE_FAN7" + ], + [ + "WW4A1", + "INT_INTERFACE_WW4B1" + ], + [ + "WR1BEG1", + "INT_INTERFACE_WR1END1" + ], + [ + "IMUX_L5", + "INT_INTERFACE_IMUX5" + ], + [ + "BYP_L0", + "INT_INTERFACE_BYP0" + ], + [ + "IMUX_L14", + "INT_INTERFACE_IMUX14" + ], + [ + "FAN_L2", + "INT_INTERFACE_FAN2" + ], + [ + "LOGIC_OUTS_L14", + "INT_INTERFACE_LOGIC_OUTS_L14" + ], + [ + "EE4END0", + "INT_INTERFACE_EE4C0" + ], + [ + "IMUX_L6", + "INT_INTERFACE_IMUX6" + ], + [ + "CTRL_L0", + "INT_INTERFACE_CTRL0" + ], + [ + "SW6BEG0", + "INT_INTERFACE_SW4A0" + ], + [ + "EE4B1", + "INT_INTERFACE_EE4A1" + ], + [ + "WW4A0", + "INT_INTERFACE_WW4B0" + ], + [ + "IMUX_L19", + "INT_INTERFACE_IMUX19" + ], + [ + "IMUX_L26", + "INT_INTERFACE_IMUX26" + ], + [ + "IMUX_L34", + "INT_INTERFACE_IMUX34" + ], + [ + "ER1END3", + "INT_INTERFACE_ER1BEG3" + ], + [ + "NE6END3", + "INT_INTERFACE_NE4C3" + ], + [ + "SW2A0", + "INT_INTERFACE_SW2A0" + ], + [ + "IMUX_L39", + "INT_INTERFACE_IMUX39" + ], + [ + "IMUX_L43", + "INT_INTERFACE_IMUX43" + ], + [ + "NW6BEG1", + "INT_INTERFACE_NW4A1" + ], + [ + "IMUX_L2", + "INT_INTERFACE_IMUX2" + ], + [ + "EE4A0", + "INT_INTERFACE_EE4BEG0" + ], + [ + "BYP_L6", + "INT_INTERFACE_BYP6" + ], + [ + "SE2END1", + "INT_INTERFACE_SE2A1" + ], + [ + "EE4C1", + "INT_INTERFACE_EE4B1" + ], + [ + "EE4A1", + "INT_INTERFACE_EE4BEG1" + ], + [ + "SE6END2", + "INT_INTERFACE_SE4C2" + ], + [ + "LOGIC_OUTS_L19", + "INT_INTERFACE_LOGIC_OUTS_L19" + ], + [ + "IMUX_L21", + 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"EE4A2", + "INT_INTERFACE_EE4BEG2" + ], + [ + "LOGIC_OUTS_L16", + "INT_INTERFACE_LOGIC_OUTS_L16" + ], + [ + "WW2BEG2", + "INT_INTERFACE_WW2A2" + ], + [ + "NW2A3", + "INT_INTERFACE_NW2A3" + ], + [ + "LH7", + "INT_INTERFACE_LH8" + ], + [ + "EE2A2", + "INT_INTERFACE_EE2BEG2" + ], + [ + "IMUX_L9", + "INT_INTERFACE_IMUX9" + ], + [ + "INT_PHASER_TO_IO_ICLKDIV", + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" + ], + [ + "MONITOR_P", + "INT_INTERFACE_MONITOR_P" + ], + [ + "IMUX_L28", + "INT_INTERFACE_IMUX28" + ], + [ + "WW2A0", + "INT_INTERFACE_WW2END0" + ], + [ + "INT_PHASER_TO_IO_OCLK1X_90", + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90" + ], + [ + "LOGIC_OUTS_L6", + "INT_INTERFACE_LOGIC_OUTS_L6" + ], + [ + "IMUX_L36", + "INT_INTERFACE_IMUX36" + ], + [ + "LOGIC_OUTS_L7", + "INT_INTERFACE_LOGIC_OUTS_L7" ] - ], + ] + }, + { "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_L" + "HCLK_CLB", + "HCLK_R" ], "grid_deltas": [ - 5, + -1, 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_IN13", + 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"T_TERM_UTURN_INT_SW6C0", - "NW6B3" - ], - [ - "T_TERM_UTURN_INT_SW2A3", - "NW2BEG0" - ], - [ - "T_TERM_UTURN_INT_SE6B3", - "NE6A0" - ], - [ - "T_TERM_UTURN_INT_SE2A0", - "SE2A0" - ], - [ - "T_TERM_UTURN_INT_SS2A0", - "SS2A0" - ], - [ - "T_TERM_UTURN_INT_SL1END1_SLOW", - "SL1END1" - ], - [ - "T_TERM_UTURN_INT_LV_L16", - "LV_L16" - ], - [ - "T_TERM_UTURN_INT_WR1BEG_S0", - "WL1BEG3" - ], - [ - "T_TERM_UTURN_INT_SS6A1", - "NN6BEG2" - ], - [ - "T_TERM_UTURN_INT_LVB_L3", - "LVB_L3" - ], - [ - "T_TERM_UTURN_INT_SS6D1", - "SS6D1" - ], - [ - "T_TERM_UTURN_INT_SE6E0", - "NE6D3" - ], - [ - "T_TERM_UTURN_INT_SE6D3", - "SE6D3" - ], - [ - "T_TERM_UTURN_INT_SS2A1", - "SS2A1" - ], - [ - "T_TERM_UTURN_INT_SE6B1", - "NE6A2" - ], - [ - "T_TERM_UTURN_INT_SL1END2_SLOW", - "NR1BEG1" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", - "BYP_BOUNCE3" - ], - [ - "T_TERM_UTURN_INT_SS6D0", - "SS6D0" - ], - [ - "T_TERM_UTURN_INT_SS6E1", - "SS6E1" - ], - [ - "T_TERM_UTURN_INT_LV_L9", - "LV_L8" - ], - [ - "T_TERM_UTURN_INT_SR1END3_SLOW", - "NL1BEG0" - ], - [ - "T_TERM_UTURN_INT_SL1END1_SLOW", - "NR1BEG2" - ], - [ - "T_TERM_UTURN_INT_SR1END2_SLOW", - "NL1BEG1" - ], - [ - "T_TERM_UTURN_INT_SW6C1", - "SW6C1" - ], - [ - "T_TERM_UTURN_INT_SS2END1", - "NN2A2" - ], - [ - "T_TERM_UTURN_INT_SE6C0", - "NE6B3" - ], - [ - "T_TERM_UTURN_INT_SS6A0", - "NN6BEG3" - ], - [ - "T_TERM_UTURN_INT_LV_L17", - "LV_L0" - ], - [ - "T_TERM_UTURN_INT_SE2A3", - "NE2BEG0" - ], - [ - "T_TERM_UTURN_INT_SS2END3", - "SS2END3" - ], - [ - "T_TERM_UTURN_INT_SS6D2", - "NN6C1" - ], - [ - "T_TERM_UTURN_INT_SR1END2_SLOW", - "SR1END2" - ], - [ - "T_TERM_UTURN_INT_SS6B3", - "NN6A0" - ], - [ - "T_TERM_UTURN_INT_SL1END3_SLOW", - "SL1END3" - ], - [ - "T_TERM_UTURN_INT_SS6B1", - "SS6B1" - ], - [ - "T_TERM_UTURN_INT_LV_L3", - "LV_L3" - ], - [ - "T_TERM_UTURN_INT_SS6D1", - "NN6C2" - ], - [ - "T_TERM_UTURN_INT_SS6END3", - "SS6END3" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_4" - ], - [ - "T_TERM_UTURN_INT_SE2A3", - "SE2A3" - ], - [ - "T_TERM_UTURN_INT_LV_L5", - "LV_L5" - ], - [ - "T_TERM_UTURN_INT_SS6C1", - "NN6B2" - ], - [ - "T_TERM_UTURN_INT_LV_L7", - "LV_L7" - ], - [ - "T_TERM_UTURN_INT_LV_L9", - "LV_L9" - ], - [ - "T_TERM_UTURN_INT_SS6A3", - "SS6A3" - ], - [ - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "BYP_BOUNCE2" - ], - [ - "T_TERM_UTURN_INT_SW6D3", - "SW6D3" - ], - [ - "T_TERM_UTURN_INT_LV_L4", - "LV_L13" - ], - [ - "T_TERM_UTURN_INT_SW6E3", - "NW6D0" - ], - [ - "T_TERM_UTURN_INT_SW6B0", - "NW6A3" - ], - [ - "T_TERM_UTURN_INT_SS6C0", - "SS6C0" - ], - [ - "T_TERM_UTURN_INT_WR1BEG_S0", - "WR1BEG_S0" - ], - [ - "T_TERM_UTURN_INT_SE6B1", - "SE6B1" - ], - [ - "T_TERM_UTURN_INT_SS2A0", - "NN2BEG3" - ], - [ - "T_TERM_UTURN_INT_SS2A1", - "NN2BEG2" - ] - ], - "tile_types": [ - "BRKH_TERM_INT", - "INT_L" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EL1BEG3_7", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_NE2A1_7", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_EE4BEG1_7", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_NW4END3_7", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW2A1_7", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_EL1BEG2_7", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW2END1_7", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WR1END3_7", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE2A2_7", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE4BEG0_7", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_WW4END0_7", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_EE2BEG0_7", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NE4BEG1_7", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_LH1_7", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW2A2_7", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_SE2A1_7", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE4B2_7", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_NE4C0_7", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_SE4BEG1_7", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_NW2A1_7", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SE2A2_7", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EL1BEG1_7", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_WW4A2_7", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_LH10_7", - "VBRK_LH10" - ], - [ - "CLK_HROW_NW4A0_7", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EE4C2_7", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NW4END2_7", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_WW2END2_7", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_WR1END2_7", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_ER1BEG0_7", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW2A3_7", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SE2A3_7", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_EE4A0_7", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_SW4END3_7", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_NE2A0_7", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_SW4A1_7", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG3_7", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WL1END3_7", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE2BEG2_7", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_ER1BEG1_7", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WR1END1_7", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW2A1_7", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW4A1_7", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NW2A2_7", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4A2_7", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW4C1_7", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_WW4A0_7", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_NW2A3_7", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE2A1_7", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_SE4C3_7", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WW4C2_7", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_LH12_7", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE4C0_7", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE4BEG2_7", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_LH9_7", - "VBRK_LH9" - ], - [ - "CLK_HROW_EE4A1_7", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_EE4C0_7", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_LH8_7", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE2BEG3_7", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_SW2A3_7", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_NE4BEG0_7", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SW4END0_7", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_LH4_7", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE2A2_7", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW4C0_7", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_SE4C2_7", - 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"MONITOR_IMUX5_6", + "VFRAME_IMUX5" + ], + [ + "MONITOR_WW2A0_6", + "VFRAME_WW2A0" + ], + [ + "MONITOR_EE4BEG1_6", + "VFRAME_EE4BEG1" + ], + [ + "MONITOR_IMUX23_6", "VFRAME_IMUX23" ], [ - "CFG_CENTER_EE4C0_9", - "VFRAME_EE4C0" + "MONITOR_IMUX7_6", + "VFRAME_IMUX7" ], [ - "CFG_CENTER_WL1END0_9", - "VFRAME_WL1END0" + "MONITOR_ER1BEG3_6", + "VFRAME_ER1BEG3" ], [ - "CFG_CENTER_CLK1_9", - "VFRAME_CLK1" + "MONITOR_FAN4_6", + "VFRAME_FAN4" ], [ - "CFG_CENTER_EE4BEG0_9", - "VFRAME_EE4BEG0" + "MONITOR_IMUX4_6", + "VFRAME_IMUX4" ], [ - "CFG_CENTER_WW4END1_9", - "VFRAME_WW4END1" + "MONITOR_WW4END2_6", + "VFRAME_WW4END2" + ], + [ + "MONITOR_IMUX38_6", + "VFRAME_IMUX38" + ], + [ + "MONITOR_NE2A3_6", + "VFRAME_NE2A3" + ], + [ + "MONITOR_SE4BEG2_6", + "VFRAME_SE4BEG2" + ], + [ + "MONITOR_IMUX21_6", + "VFRAME_IMUX21" + ], + [ + "MONITOR_WW4C1_6", + "VFRAME_WW4C1" + ], + [ + "MONITOR_LH3_6", + "VFRAME_LH3" + ], + [ + "MONITOR_LH11_6", + "VFRAME_LH11" + ], + [ + "MONITOR_NE4C0_6", + "VFRAME_NE4C0" + ], + [ + "MONITOR_LH1_6", + "VFRAME_LH1" + ], + [ + "MONITOR_WW2A1_6", + "VFRAME_WW2A1" + ], + [ + "MONITOR_SW4END3_6", + "VFRAME_SW4END3" + ], + [ + "MONITOR_SE4C0_6", + "VFRAME_SE4C0" + ], + [ + "MONITOR_IMUX37_6", + "VFRAME_IMUX37" + ], + [ + "MONITOR_IMUX31_6", + "VFRAME_IMUX31" + ], + [ + "MONITOR_WW4C0_6", + "VFRAME_WW4C0" + ], + [ + "MONITOR_NW4END2_6", + "VFRAME_NW4END2" + ], + [ + "MONITOR_EE4A1_6", + "VFRAME_EE4A1" + ], + [ + "MONITOR_WW4B3_6", + "VFRAME_WW4B3" + ], + [ + "MONITOR_WW2END0_6", + "VFRAME_WW2END0" ] - ], - "tile_types": [ - "CFG_CENTER_MID", - "VFRAME" - ], - "grid_deltas": [ - 1, - 1 ] }, { - "wire_pairs": [ - [ - "IOI_RCLK_FORIO0", - "IOI_SING_RCLK_FORIO0" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_SING_LEAF_GCLK4" - ], - [ - "IOI_IOCLK3", - "IOI_SING_IOCLK3" - ], - [ - "IOI_IOCLK0", - "IOI_SING_IOCLK0" - ], - [ - "IOI_IOCLK2", - "IOI_SING_IOCLK2" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_SING_RCLK_FORIO2" - ], - [ - "IOI_LEAF_GCLK0", - "IOI_SING_LEAF_GCLK0" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_SING_LEAF_GCLK5" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_SING_LEAF_GCLK1" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_SING_RCLK_FORIO1" - ], - [ - "IOI_IOCLK1", - "IOI_SING_IOCLK1" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_SING_LEAF_GCLK2" - ], - [ - "IOI_TBYTEIN", - "IOI_SING_TBYTEIN" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_SING_RCLK_FORIO3" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_SING_LEAF_GCLK3" - ] - ], "tile_types": [ - "LIOI3", - "LIOI3_SING" + "CLK_BUFG_REBUF", + "CLK_FEED" ], "grid_deltas": [ 0, - 1 + -2 + ], + "wire_pairs": [ + [ + "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", + "CLK_FEED_R_CK_GCLK18" + ] ] }, { - "wire_pairs": [ - [ - "CLK_HROW_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH8_2", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_LH11_2", - "VBRK_LH11" - ], - [ - "CLK_HROW_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_LH3_2", - "VBRK_LH3" - ], - [ - "CLK_HROW_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_LH1_2", - "VBRK_LH1" - ], - [ - "CLK_HROW_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH9_2", - "VBRK_LH9" - ], - [ - "CLK_HROW_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_LH4_2", - "VBRK_LH4" - ], - [ - "CLK_HROW_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_LH5_2", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH7_2", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_LH10_2", - "VBRK_LH10" - ], - [ - "CLK_HROW_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_LH12_2", - "VBRK_LH12" - ], - [ - "CLK_HROW_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_LH2_2", - "VBRK_LH2" - ], - [ - "CLK_HROW_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_LH6_2", - "VBRK_LH6" - ] - ], "tile_types": [ - "CLK_BUFG_BOT_R", + "CLBLM_R", "VBRK" ], "grid_deltas": [ 1, - -2 - ] - }, - { - "wire_pairs": [ - [ - "DSP_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "DSP_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "DSP_LOGIC_OUTS_B13_0", - "INT_INTERFACE_LOGIC_OUTS_B13" - ], - [ - "DSP_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "DSP_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "DSP_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "DSP_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "DSP_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "DSP_LOGIC_OUTS_B14_0", - "INT_INTERFACE_LOGIC_OUTS_B14" - ], - [ - "DSP_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "DSP_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "DSP_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "DSP_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "DSP_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "DSP_LOGIC_OUTS_B22_0", - "INT_INTERFACE_LOGIC_OUTS_B22" - ], - [ - "DSP_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "DSP_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "DSP_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "DSP_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "DSP_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "DSP_LOGIC_OUTS_B19_0", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "DSP_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "DSP_LH1_0", - "INT_INTERFACE_LH1" - ], - [ - "DSP_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "DSP_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "DSP_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "DSP_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "DSP_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "DSP_LOGIC_OUTS_B8_0", - "INT_INTERFACE_LOGIC_OUTS_B8" - ], - [ - "DSP_LOGIC_OUTS_B20_0", - "INT_INTERFACE_LOGIC_OUTS_B20" - ], - [ - "DSP_LOGIC_OUTS_B5_0", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "DSP_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "DSP_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "DSP_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "DSP_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "DSP_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "DSP_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "DSP_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "DSP_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "DSP_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "DSP_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "DSP_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "DSP_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "DSP_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "DSP_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "DSP_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "DSP_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "DSP_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "DSP_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "DSP_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "DSP_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "DSP_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "DSP_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "DSP_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "DSP_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "DSP_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "DSP_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "DSP_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "DSP_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "DSP_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "DSP_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "DSP_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "DSP_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "DSP_LOGIC_OUTS_B1_0", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "DSP_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "DSP_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "DSP_NW4END2_0", - "INT_INTERFACE_NW4END2" - ], - [ - "DSP_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "DSP_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "DSP_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "DSP_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "DSP_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "DSP_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "DSP_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "DSP_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "DSP_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "DSP_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "DSP_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "DSP_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "DSP_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "DSP_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "DSP_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "DSP_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "DSP_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "DSP_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "DSP_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "DSP_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "DSP_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "DSP_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "DSP_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "DSP_SW4END2_0", - "INT_INTERFACE_SW4END2" - ], - [ - "DSP_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "DSP_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "DSP_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "DSP_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "DSP_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "DSP_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "DSP_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "DSP_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "DSP_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "DSP_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "DSP_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" - ], - [ - "DSP_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "DSP_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "DSP_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "DSP_SE2A0_0", - "INT_INTERFACE_SE2A0" - ], - [ - "DSP_LOGIC_OUTS_B17_0", - "INT_INTERFACE_LOGIC_OUTS_B17" - ], - [ - "DSP_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "DSP_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "DSP_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "DSP_LOGIC_OUTS_B23_0", - "INT_INTERFACE_LOGIC_OUTS_B23" - ], - [ - "DSP_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "DSP_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "DSP_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "DSP_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "DSP_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "DSP_LOGIC_OUTS_B7_0", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "DSP_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "DSP_LOGIC_OUTS_B11_0", - "INT_INTERFACE_LOGIC_OUTS_B11" - ], - [ - "DSP_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "DSP_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "DSP_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "DSP_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "DSP_LOGIC_OUTS_B6_0", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "DSP_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "DSP_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "DSP_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "DSP_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "DSP_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "DSP_LOGIC_OUTS_B15_0", - "INT_INTERFACE_LOGIC_OUTS_B15" - ], - [ - "DSP_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "DSP_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "DSP_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "DSP_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "DSP_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "DSP_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "DSP_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "DSP_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "DSP_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "DSP_LH9_0", - "INT_INTERFACE_LH9" - ], - [ - "DSP_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "DSP_MONITOR_P_0", - "INT_INTERFACE_MONITOR_P" - ], - [ - "DSP_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "DSP_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "DSP_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "DSP_LOGIC_OUTS_B21_0", - "INT_INTERFACE_LOGIC_OUTS_B21" - ], - [ - "DSP_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "DSP_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "DSP_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "DSP_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "DSP_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "DSP_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "DSP_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "DSP_MONITOR_N_0", - "INT_INTERFACE_MONITOR_N" - ], - [ - "DSP_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "DSP_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "DSP_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "DSP_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "DSP_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "DSP_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "DSP_LOGIC_OUTS_B2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "DSP_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "DSP_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "DSP_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "DSP_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "DSP_IMUX8_0", - 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"PCIE_INT_INTERFACE_IMUX_L_OUT23" - ], - [ - "PCIE_SE4C2_11", - "INT_INTERFACE_SE4C2" - ], - [ - "PCIE_FAN1_L_11", - "INT_INTERFACE_FAN1" - ], - [ - "PCIE_IMUX33_L_11", - "PCIE_INT_INTERFACE_IMUX_L_OUT33" - ], - [ - "PCIE_EE4B1_11", - "INT_INTERFACE_EE4B1" - ], - [ - "PCIE_LOGIC_OUTS_B6_L_11", - "INT_INTERFACE_LOGIC_OUTS_L_B6" - ], - [ - "PCIE_LOGIC_OUTS_B12_L_11", - "INT_INTERFACE_LOGIC_OUTS_L_B12" - ], - [ - "PCIE_LOGIC_OUTS_B3_L_11", - "INT_INTERFACE_LOGIC_OUTS_L_B3" - ], - [ - "PCIE_NE4C0_11", - "INT_INTERFACE_NE4C0" - ], - [ - "PCIE_NE4C1_11", - "INT_INTERFACE_NE4C1" - ], - [ - "PCIE_IMUX19_L_11", - "PCIE_INT_INTERFACE_IMUX_L_OUT19" - ], - [ - "PCIE_EE2BEG3_11", - "INT_INTERFACE_EE2BEG3" - ], - [ - "PCIE_BYP1_L_11", - "INT_INTERFACE_BYP1" - ] - ], - "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_L" - ], - "grid_deltas": [ - 5, - -1 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "BRAM_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "BRAM_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "BRAM_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "BRAM_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "BRAM_LH12_2", - "VBRK_LH12" - ], - [ - "BRAM_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "BRAM_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "BRAM_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "BRAM_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "BRAM_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "BRAM_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "BRAM_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "BRAM_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "BRAM_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "BRAM_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "BRAM_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "BRAM_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "BRAM_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "BRAM_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "BRAM_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "BRAM_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "BRAM_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "BRAM_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "BRAM_LH7_2", - "VBRK_LH7" - ], - [ - "BRAM_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "BRAM_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "BRAM_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "BRAM_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "BRAM_NW4A1_2", + "CLBLM_NW4A1", "VBRK_NW4A1" ], [ - "BRAM_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "BRAM_LH11_2", - "VBRK_LH11" - ], - [ - "BRAM_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "BRAM_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "BRAM_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "BRAM_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "BRAM_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "BRAM_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "BRAM_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "BRAM_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "BRAM_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "BRAM_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "BRAM_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "BRAM_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "BRAM_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "BRAM_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "BRAM_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "BRAM_EE4C0_2", + "CLBLM_EE4C0", "VBRK_EE4C0" ], [ - "BRAM_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "BRAM_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "BRAM_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "BRAM_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "BRAM_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "BRAM_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "BRAM_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "BRAM_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "BRAM_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "BRAM_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "BRAM_LH6_2", - "VBRK_LH6" - ], - [ - "BRAM_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "BRAM_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "BRAM_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "BRAM_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "BRAM_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "BRAM_LH2_2", - "VBRK_LH2" - ], - [ - "BRAM_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "BRAM_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "BRAM_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "BRAM_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "BRAM_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "BRAM_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "BRAM_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "BRAM_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "BRAM_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "BRAM_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "BRAM_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "BRAM_EE2BEG0_2", + "CLBLM_EE2BEG0", "VBRK_EE2BEG0" ], [ - "BRAM_EE4A0_2", - "VBRK_EE4A0" + "CLBLM_NW4A3", + "VBRK_NW4A3" ], [ - "BRAM_MONITOR_N_2", - "VBRK_MONITOR_N" + "CLBLM_WR1END1", + "VBRK_WR1END1" ], [ - "BRAM_LH1_2", - "VBRK_LH1" + "CLBLM_WW4A2", + "VBRK_WW4A2" ], [ - "BRAM_SE4BEG0_2", - "VBRK_SE4BEG0" + "CLBLM_WW4B3", + "VBRK_WW4B3" ], [ - "BRAM_EE4B0_2", - "VBRK_EE4B0" + "CLBLM_SE4C2", + "VBRK_SE4C2" ], [ - "BRAM_EE2BEG1_2", - "VBRK_EE2BEG1" + "CLBLM_EE4B2", + "VBRK_EE4B2" ], [ - "BRAM_SW4A2_2", - "VBRK_SW4A2" + "CLBLM_EE4C2", + "VBRK_EE4C2" ], [ - "BRAM_NE2A3_2", - "VBRK_NE2A3" + "CLBLM_SE4C3", + "VBRK_SE4C3" ], [ - "BRAM_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "BRAM_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "BRAM_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "BRAM_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "BRAM_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "BRAM_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "BRAM_SE4C0_2", + "CLBLM_SE4C0", "VBRK_SE4C0" ], [ - "BRAM_SE4C1_2", - "VBRK_SE4C1" + "CLBLM_SW4A0", + "VBRK_SW4A0" ], [ - "BRAM_SW2A1_2", - "VBRK_SW2A1" + "CLBLM_NE4C0", + "VBRK_NE4C0" ], [ - "BRAM_LH5_2", - "VBRK_LH5" - ], - [ - "BRAM_SE2A1_2", + "CLBLM_SE2A1", "VBRK_SE2A1" ], [ - "BRAM_LH8_2", - "VBRK_LH8" + "CLBLM_WW4END3", + "VBRK_WW4END3" ], [ - "BRAM_SE2A0_2", - "VBRK_SE2A0" + "CLBLM_EE4B3", + "VBRK_EE4B3" ], [ - "BRAM_WR1END0_2", - "VBRK_WR1END0" + "CLBLM_LH1", + "VBRK_LH1" ], [ - "BRAM_NW4END0_2", - "VBRK_NW4END0" + "CLBLM_LH2", + "VBRK_LH2" ], [ - "BRAM_MONITOR_P_2", + "CLBLM_ER1BEG1", + "VBRK_ER1BEG1" + ], + [ + "CLBLM_EE4BEG3", + "VBRK_EE4BEG3" + ], + [ + "CLBLM_WL1END0", + "VBRK_WL1END0" + ], + [ + "CLBLM_NE2A2", + "VBRK_NE2A2" + ], + [ + "CLBLM_EE4A1", + "VBRK_EE4A1" + ], + [ + "CLBLM_EE4BEG1", + "VBRK_EE4BEG1" + ], + [ + "CLBLM_WL1END1", + "VBRK_WL1END1" + ], + [ + "CLBLM_LH9", + "VBRK_LH9" + ], + [ + "CLBLM_NW4END2", + "VBRK_NW4END2" + ], + [ + "CLBLM_EL1BEG3", + "VBRK_EL1BEG3" + ], + [ + "CLBLM_WW2END1", + "VBRK_WW2END1" + ], + [ + "CLBLM_WW4C0", + "VBRK_WW4C0" + ], + [ + "CLBLM_WR1END2", + "VBRK_WR1END2" + ], + [ + "CLBLM_WL1END3", + "VBRK_WL1END3" + ], + [ + "CLBLM_LH11", + "VBRK_LH11" + ], + [ + "CLBLM_WR1END3", + "VBRK_WR1END3" + ], + [ + "CLBLM_WW4B1", + "VBRK_WW4B1" + ], + [ + "CLBLM_SW4END2", + "VBRK_SW4END2" + ], + [ + "CLBLM_NE2A1", + "VBRK_NE2A1" + ], + [ + "CLBLM_MONITOR_P", "VBRK_MONITOR_P" ], [ - "BRAM_SE4C2_2", - "VBRK_SE4C2" + "CLBLM_SE4BEG1", + "VBRK_SE4BEG1" ], [ - "BRAM_NW4END3_2", - "VBRK_NW4END3" + "CLBLM_SE4BEG2", + "VBRK_SE4BEG2" ], [ - "BRAM_SE4C3_2", - "VBRK_SE4C3" + "CLBLM_WW4A3", + "VBRK_WW4A3" ], [ - "BRAM_SW4END2_2", - "VBRK_SW4END2" + "CLBLM_EE4A0", + "VBRK_EE4A0" ], [ - "BRAM_EE2BEG3_2", - "VBRK_EE2BEG3" + "CLBLM_SE4BEG0", + "VBRK_SE4BEG0" ], [ - "BRAM_SW2A3_2", - "VBRK_SW2A3" + "CLBLM_NW2A3", + "VBRK_NW2A3" ], [ - "BRAM_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "BRAM_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "BRAM_EE4A2_2", + "CLBLM_EE4A2", "VBRK_EE4A2" ], [ - "BRAM_EE2A3_2", + "CLBLM_EE2BEG3", + "VBRK_EE2BEG3" + ], + [ + "CLBLM_WW4END0", + "VBRK_WW4END0" + ], + [ + "CLBLM_NE4BEG3", + "VBRK_NE4BEG3" + ], + [ + "CLBLM_SE2A2", + "VBRK_SE2A2" + ], + [ + "CLBLM_ER1BEG2", + "VBRK_ER1BEG2" + ], + [ + "CLBLM_LH10", + "VBRK_LH10" + ], + [ + "CLBLM_SW4A2", + "VBRK_SW4A2" + ], + [ + "CLBLM_NE4BEG2", + "VBRK_NE4BEG2" + ], + [ + "CLBLM_SW2A0", + "VBRK_SW2A0" + ], + [ + "CLBLM_NW2A0", + "VBRK_NW2A0" + ], + [ + "CLBLM_EE2A3", "VBRK_EE2A3" ], [ - "BRAM_WW4A1_2", - "VBRK_WW4A1" + "CLBLM_EE4BEG2", + "VBRK_EE4BEG2" ], [ - "BRAM_WL1END0_2", - "VBRK_WL1END0" + "CLBLM_EE4C1", + "VBRK_EE4C1" ], [ - "BRAM_LH3_2", - "VBRK_LH3" + "CLBLM_WW2A3", + "VBRK_WW2A3" ], [ - "BRAM_WW2END3_2", - "VBRK_WW2END3" + "CLBLM_SW4END0", + "VBRK_SW4END0" ], [ - "BRAM_EL1BEG3_2", - "VBRK_EL1BEG3" + "CLBLM_NE4C2", + "VBRK_NE4C2" ], [ - "BRAM_WW4B2_2", - "VBRK_WW4B2" + "CLBLM_SW2A2", + "VBRK_SW2A2" ], [ - "BRAM_LH4_2", - "VBRK_LH4" + "CLBLM_SE2A3", + "VBRK_SE2A3" ], [ - "BRAM_EE4B1_2", - "VBRK_EE4B1" + "CLBLM_WW4END2", + "VBRK_WW4END2" ], [ - "BRAM_LH9_2", - "VBRK_LH9" - ], - [ - "BRAM_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "BRAM_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "BRAM_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "BRAM_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "BRAM_WW2A1_2", + "CLBLM_WW2A1", "VBRK_WW2A1" ], [ - "BRAM_LH10_2", - "VBRK_LH10" + "CLBLM_LH4", + "VBRK_LH4" + ], + [ + "CLBLM_EE4BEG0", + "VBRK_EE4BEG0" + ], + [ + "CLBLM_ER1BEG0", + "VBRK_ER1BEG0" + ], + [ + "CLBLM_LH7", + "VBRK_LH7" + ], + [ + "CLBLM_WW2END0", + "VBRK_WW2END0" + ], + [ + "CLBLM_LH3", + "VBRK_LH3" + ], + [ + "CLBLM_LH6", + "VBRK_LH6" + ], + [ + "CLBLM_NW4A0", + "VBRK_NW4A0" + ], + [ + "CLBLM_WW2A2", + "VBRK_WW2A2" + ], + [ + "CLBLM_WW4B0", + "VBRK_WW4B0" + ], + [ + "CLBLM_NE2A3", + "VBRK_NE2A3" + ], + [ + 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"GTPE2_BYP3_8", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX10_8", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_FAN3_8", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_FAN0_8", - "VBRK_EXT_FAN0" + "GTPE2_LOGIC_OUTS_B14_8", + "VBRK_EXT_LOGIC_OUTS_B14" ], [ "GTPE2_IMUX46_8", "VBRK_EXT_IMUX46" ], - [ - "GTPE2_IMUX38_8", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX45_8", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX4_8", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX19_8", - "VBRK_EXT_IMUX19" - ], [ "GTPE2_IMUX21_8", "VBRK_EXT_IMUX21" ], [ - "GTPE2_BYP7_8", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_BYP6_8", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX1_8", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_LOGIC_OUTS_B22_8", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX32_8", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX22_8", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX26_8", - "VBRK_EXT_IMUX26" + "GTPE2_IMUX17_8", + "VBRK_EXT_IMUX17" ], [ "GTPE2_LOGIC_OUTS_B18_8", @@ -122844,15546 +9944,12070 @@ [ "GTPE2_IMUX27_8", "VBRK_EXT_IMUX27" + ], + [ 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"VBRK_EXT_IMUX23" + ], + [ + "GTPE2_FAN2_8", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_LOGIC_OUTS_B16_8", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTPE2_IMUX6_8", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX8_8", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_BYP2_8", + "VBRK_EXT_BYP2" + ], + [ + "GTPE2_BYP4_8", + "VBRK_EXT_BYP4" + ], + [ + "GTPE2_IMUX22_8", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_LOGIC_OUTS_B17_8", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTPE2_IMUX40_8", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_IMUX15_8", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_BYP6_8", + "VBRK_EXT_BYP6" + ], + [ + "GTPE2_IMUX31_8", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_LOGIC_OUTS_B2_8", + "VBRK_EXT_LOGIC_OUTS_B2" ] - ], + ] + }, + { "tile_types": [ - "GTP_CHANNEL_3", + "GTP_COMMON", "VBRK_EXT" ], "grid_deltas": [ -1, - -3 - ] - }, - { + -6 + ], "wire_pairs": [ [ - "CMT_TOP_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE2A0_2", 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"VBRK_WW4END2" - ], - [ - "CMT_TOP_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_LH9_4", - "VBRK_LH9" - ], - [ - "CMT_TOP_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_LH6_4", - "VBRK_LH6" - ], - [ - "CMT_TOP_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_LH3_4", - "VBRK_LH3" - ], - [ - "CMT_TOP_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4B0_4", - "VBRK_WW4B0" - ] - ], "tile_types": [ - "CMT_TOP_R_LOWER_B", - "VBRK" - ], - "grid_deltas": [ - 1, - 4 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH7_3", - "VBRK_LH7" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_LH6_3", - "VBRK_LH6" - ], - [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_LH4_3", - "VBRK_LH4" - ], - [ - "CLK_HROW_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH5_3", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE2A3_3", - "VBRK_EE2A3" - ], - [ - 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], - [ - "CLK_HROW_LH8_3", - "VBRK_LH8" - ], - [ - "CLK_HROW_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_EE2BEG3_3", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_LH2_3", - "VBRK_LH2" - ], - [ - "CLK_HROW_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_NE4BEG2_3", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW4C2_3", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WW4A0_3", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_NE4C3_3", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_NW4A2_3", - "VBRK_NW4A2" - ] - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -3 - ] - }, - { - "wire_pairs": [ - [ - "BRKH_CLB_COUT1_R", - "CLBLM_M_COUT_N" - ], - [ - "BRKH_CLB_COUT0_R", - "CLBLM_L_COUT_N" - ] - ], - "tile_types": [ - "BRKH_CLB", - "CLBLM_R" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_EL1BEG1_13", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_EE4BEG2_13", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_SW4A0_13", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_NW2A3_13", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_SW4END1_13", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE2A2_13", - "VBRK_EE2A2" - ], - [ - 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+ ], + [ + "GTPE2_IMUX36_10", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX38_10", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX15_10", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_CLK0_10", + "VBRK_EXT_CLK0" + ], + [ + "GTPE2_LOGIC_OUTS_B17_10", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTPE2_IMUX27_10", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_LOGIC_OUTS_B12_10", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTPE2_IMUX40_10", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_LOGIC_OUTS_B3_10", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTPE2_LOGIC_OUTS_B1_10", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTPE2_LOGIC_OUTS_B11_10", + "VBRK_EXT_LOGIC_OUTS_B11" + ], + [ + "GTPE2_IMUX3_10", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_LOGIC_OUTS_B13_10", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTPE2_BYP5_10", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_IMUX22_10", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX42_10", + "VBRK_EXT_IMUX42" + ], + [ + "GTPE2_BYP7_10", + "VBRK_EXT_BYP7" + ], + [ + "GTPE2_IMUX45_10", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_IMUX34_10", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_LOGIC_OUTS_B19_10", + "VBRK_EXT_LOGIC_OUTS_B19" + ], + [ + "GTPE2_IMUX1_10", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_CLK1_10", + "VBRK_EXT_CLK1" + ], + [ + "GTPE2_LOGIC_OUTS_B16_10", + "VBRK_EXT_LOGIC_OUTS_B16" + ] ] }, { + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ], + "grid_deltas": [ + -1, + -3 + ], "wire_pairs": [ [ - "CMT_TOP_WW4B1_10", - "VBRK_WW4B1" + "CLK_HROW_WW4B0_6", + "INT_INTERFACE_WW4B0" ], [ - "CMT_TOP_EE2A0_10", - "VBRK_EE2A0" + "CLK_HROW_LH10_6", + "INT_INTERFACE_LH10" ], [ - "CMT_TOP_WR1END2_10", - "VBRK_WR1END2" + "CLK_HROW_BYP6_6", + "INT_INTERFACE_BYP6" ], [ - "CMT_TOP_WW4C0_10", - "VBRK_WW4C0" + "CLK_HROW_WW4B3_6", + "INT_INTERFACE_WW4B3" ], [ - "CMT_TOP_EE4C2_10", - "VBRK_EE4C2" + "CLK_HROW_WW2A1_6", + "INT_INTERFACE_WW2A1" ], [ - "CMT_TOP_NW2A3_10", - "VBRK_NW2A3" + "CLK_HROW_IMUX6_6", + "INT_INTERFACE_IMUX6" ], [ - "CMT_TOP_SE4C3_10", - "VBRK_SE4C3" + "CLK_HROW_WW4C2_6", + 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"INT_INTERFACE_IMUX47" ], [ - "CMT_TOP_LH8_10", - "VBRK_LH8" + "CLK_HROW_EE2A2_6", + "INT_INTERFACE_EE2A2" ], [ - "CMT_TOP_EE4A1_10", - "VBRK_EE4A1" + "CLK_HROW_SW2A2_6", + "INT_INTERFACE_SW2A2" ], [ - "CMT_TOP_SW4A2_10", - "VBRK_SW4A2" + "CLK_HROW_NW4A0_6", + "INT_INTERFACE_NW4A0" ], [ - "CMT_TOP_ER1BEG0_10", - "VBRK_ER1BEG0" + "CLK_HROW_BYP1_6", + "INT_INTERFACE_BYP1" ], [ - "CMT_TOP_WW4B2_10", - "VBRK_WW4B2" + "CLK_HROW_FAN7_6", + "INT_INTERFACE_FAN7" ], [ - "CMT_TOP_WW2END1_10", - "VBRK_WW2END1" + "CLK_HROW_IMUX41_6", + "INT_INTERFACE_IMUX41" ], [ - "CMT_TOP_WW2END0_10", - "VBRK_WW2END0" + "CLK_HROW_FAN1_6", + "INT_INTERFACE_FAN1" ], [ - "CMT_TOP_EE4BEG2_10", - "VBRK_EE4BEG2" + "CLK_HROW_NE2A2_6", + "INT_INTERFACE_NE2A2" ], [ - "CMT_TOP_WW4C3_10", - "VBRK_WW4C3" + "CLK_HROW_MONITOR_P_6", + "INT_INTERFACE_MONITOR_P" ], [ - "CMT_TOP_LH6_10", - "VBRK_LH6" + "CLK_HROW_IMUX18_6", + "INT_INTERFACE_IMUX18" ], [ - "CMT_TOP_ER1BEG2_10", - "VBRK_ER1BEG2" + "CLK_HROW_EE2BEG0_6", + "INT_INTERFACE_EE2BEG0" ], [ - "CMT_TOP_SW4END0_10", - "VBRK_SW4END0" + "CLK_HROW_CLK1_6", + "INT_INTERFACE_CLK1" ], [ - "CMT_TOP_LH10_10", - "VBRK_LH10" + "CLK_HROW_WW2END1_6", + "INT_INTERFACE_WW2END1" ], [ - "CMT_TOP_ER1BEG3_10", - "VBRK_ER1BEG3" + "CLK_HROW_EE4B1_6", + "INT_INTERFACE_EE4B1" ], [ - "CMT_TOP_SE2A2_10", - "VBRK_SE2A2" + "CLK_HROW_WW4END3_6", + "INT_INTERFACE_WW4END3" ], [ - "CMT_TOP_SE4BEG0_10", - "VBRK_SE4BEG0" + "CLK_HROW_EL1BEG0_6", + "INT_INTERFACE_EL1BEG0" ], [ - "CMT_TOP_WW4C2_10", - "VBRK_WW4C2" + "CLK_HROW_NW4END0_6", + "INT_INTERFACE_NW4END0" ], [ - "CMT_TOP_SW4END1_10", - "VBRK_SW4END1" + "CLK_HROW_BYP2_6", + "INT_INTERFACE_BYP2" ], [ - "CMT_TOP_LH5_10", - "VBRK_LH5" + "CLK_HROW_NW2A1_6", + "INT_INTERFACE_NW2A1" ], [ - "CMT_TOP_WW4END1_10", + "CLK_HROW_SW4A1_6", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_NW4A1_6", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_WW4A2_6", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_FAN5_6", + "INT_INTERFACE_FAN5" + ], + [ + "CLK_HROW_EE2BEG3_6", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_LH5_6", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_EE4BEG2_6", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_SE4C3_6", + "INT_INTERFACE_SE4C3" + ], + [ + "CLK_HROW_IMUX23_6", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_NE4BEG1_6", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_SE2A0_6", + "INT_INTERFACE_SE2A0" + ], + [ + "CLK_HROW_IMUX2_6", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_EE4BEG0_6", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_EE2BEG1_6", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_BYP4_6", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_WL1END3_6", + "INT_INTERFACE_WL1END3" + ], + [ + "CLK_HROW_WW4C0_6", + "INT_INTERFACE_WW4C0" + ], + [ + "CLK_HROW_WW2A3_6", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_NW2A3_6", + "INT_INTERFACE_NW2A3" + ], + [ + "CLK_HROW_NW4END2_6", + "INT_INTERFACE_NW4END2" + ], + [ + "CLK_HROW_NW4END3_6", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_WL1END0_6", + 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"VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTPE2_IMUX33_0", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX7_0", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_CTRL0_0", + "VBRK_EXT_CTRL0" + ], + [ + "GTPE2_IMUX45_0", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_IMUX15_0", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX4_0", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_CTRL1_0", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_IMUX41_0", + "VBRK_EXT_IMUX41" + ], + [ + "GTPE2_BYP2_0", + "VBRK_EXT_BYP2" + ], + [ + "GTPE2_FAN0_0", + "VBRK_EXT_FAN0" + ], + [ + "GTPE2_LOGIC_OUTS_B10_0", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTPE2_BYP5_0", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_IMUX36_0", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_LOGIC_OUTS_B15_0", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTPE2_IMUX34_0", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_LOGIC_OUTS_B18_0", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTPE2_LOGIC_OUTS_B9_0", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTPE2_IMUX38_0", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX39_0", + "VBRK_EXT_IMUX39" + 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"tile_types": [ + "CMT_TOP_R_LOWER_B", + "CMT_TOP_R_LOWER_T" + ], + "grid_deltas": [ + 0, + -9 + ], "wire_pairs": [ [ - "CMT_MMCM_PHASERREF_BELOW0", - "CMT_PHASER_DOWN_PHASERREF_BELOW0" + "CMT_R_LOWER_B_CLK_PERF1", + "CMT_LR_LOWER_T_CLK_PERF1" ], [ - "CMT_MMCM_PHASERA_CTSBUS1", - "CMT_PHASERA_CTSBUS1" - ], - [ - "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", - "CMT_PHASER_OUT_A_OCLK1X_90" - ], - [ - "MMCM_CLK_FREQ_BB_NS0", - "MMCM_CLK_FREQBB_REBUFOUT0" - ], - [ - "CMT_MMCM_PHASERA_DTSBUS1", - "CMT_PHASERA_DTSBUS1" - ], - [ - "CMT_MMCM_PHASERREF0", - "CMT_PHASER_DOWN_PHASERREF0" - ], - [ - "CMT_MMCM_A_WRCLK_TOFIFO", - "CMT_PHASER_IN_A_WRCLK_TOFIFO" - ], - [ - "CMT_MMCM_A_RDEN_TOFIFO", - "CMT_PHASER_OUT_A_RDEN_TOFIFO" - ], - [ - "CMT_MMCM_A_WREN_TOFIFO", - "CMT_PHASER_IN_A_WREN_TOFIFO" - ], - [ - "CMT_MMCM_PHASER_IN_B_ICLK", - "CMT_PHASER_B_TOMMCM_ICLK" - ], - [ - "MMCM_CLK_FREQ_BB_NS1", - "MMCM_CLK_FREQBB_REBUFOUT1" - ], - [ - "CMT_L_LOWER_B_CLK_MMCM3", - "CMT_LR_LOWER_T_CLK_MMCM3" - ], - [ - "CMT_L_LOWER_B_CLK_MMCM13", - "CMT_LR_LOWER_T_CLK_MMCM13" - ], - [ - "CMT_L_LOWER_B_CLK_MMCM1", - "CMT_LR_LOWER_T_CLK_MMCM1" - ], - [ - "CMT_MMCM_PHASERA_CTSBUS0", - "CMT_PHASERA_CTSBUS0" - ], - [ - "CMT_L_LOWER_B_CLK_IN2_HCLK", - "CMT_LR_LOWER_T_CLK_IN2_HCLK" - ], - [ - "MMCMOUT_CLK_FREQ_BB_3", - "MMCMOUT_CLK_FREQ_BB_REBUFIN3" - ], - [ - "CMT_L_LOWER_B_CLK_MMCM9", - "CMT_LR_LOWER_T_CLK_MMCM9" + "CMT_R_LOWER_B_CLK_MMCM4", + "CMT_LR_LOWER_T_CLK_MMCM4" ], [ "MMCM_CLK_FREQ_BB_NS3", "MMCM_CLK_FREQBB_REBUFOUT3" ], [ - "CMT_L_LOWER_B_CLK_PERF3", - "CMT_LR_LOWER_T_CLK_PERF3" + "MMCMOUT_CLK_FREQ_BB_2", + "MMCMOUT_CLK_FREQ_BB_REBUFIN2" ], [ - "CMT_L_LOWER_B_CLK_MMCM7", - "CMT_LR_LOWER_T_CLK_MMCM7" + "CMT_MMCM_PHASERREF_ABOVE0", + "CMT_PHASER_DOWN_PHASERREF_ABOVE0" ], [ - "CMT_MMCM_PHASER_OUT_A_OCLK", - "CMT_PHASER_OUT_A_OCLK" + "CMT_MMCM_PHASER_OUT_B_OCLKDIV", + "CMT_PHASER_B_TOMMCM_OCLKDIV" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM0", + "CMT_LR_LOWER_T_CLK_MMCM0" ], [ "CMT_MMCM_PHASER_IN_A_ICLK", "CMT_PHASER_IN_A_ICLK" ], [ - "MMCMOUT_CLK_FREQ_BB_1", - "MMCMOUT_CLK_FREQ_BB_REBUFIN1" + "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", + "CMT_PHASER_OUT_A_OCLK1X_90" ], [ - "CMT_L_LOWER_B_CLK_MMCM0", - "CMT_LR_LOWER_T_CLK_MMCM0" + "CMT_MMCM_PHASER_IN_B_ICLKDIV", + "CMT_PHASER_B_TOMMCM_ICLKDIV" ], [ - "CMT_L_LOWER_B_CLK_MMCM2", - "CMT_LR_LOWER_T_CLK_MMCM2" + "CMT_R_LOWER_B_CLK_IN3_HCLK", + "CMT_LR_LOWER_T_CLK_IN3_HCLK" + ], + [ + "CMT_MMCM_PHASERA_CTSBUS1", + "CMT_PHASERA_CTSBUS1" ], [ "CMT_MMCM_PHASER_OUT_A_OCLKDIV", "CMT_PHASER_OUT_A_OCLKDIV" ], [ - "MMCM_CLK_FREQ_BB_NS2", - "MMCM_CLK_FREQBB_REBUFOUT2" + "CMT_MMCM_PHASERA_DQSBUS0", + "CMT_PHASERA_DQSBUS0" + ], + [ + "CMT_MMCM_PHASER_OUT_B_OCLK", + "CMT_PHASER_B_TOMMCM_OCLK" + ], + [ + "CMT_MMCM_A_WRCLK_TOFIFO", + "CMT_PHASER_IN_A_WRCLK_TOFIFO" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM1", + "CMT_LR_LOWER_T_CLK_MMCM1" + ], + [ + "CMT_MMCM_PHASERREF_BELOW1", + "CMT_PHASER_DOWN_PHASERREF_BELOW1" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM13", + "CMT_LR_LOWER_T_CLK_MMCM13" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM3", + "CMT_LR_LOWER_T_CLK_MMCM3" + ], + [ + "CMT_MMCM_A_WREN_TOFIFO", + "CMT_PHASER_IN_A_WREN_TOFIFO" + ], + [ + "CMT_MMCM_PHASERREF0", + "CMT_PHASER_DOWN_PHASERREF0" + ], + [ + "CMT_MMCM_PHASER_IN_A_ICLKDIV", + "CMT_PHASER_IN_A_ICLKDIV" + ], + [ + "CMT_R_LOWER_B_CLK_IN2_HCLK", + "CMT_LR_LOWER_T_CLK_IN2_HCLK" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM9", + "CMT_LR_LOWER_T_CLK_MMCM9" + ], + [ + "CMT_MMCM_PHASERREF1", + "CMT_PHASER_DOWN_PHASERREF1" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM10", + "CMT_LR_LOWER_T_CLK_MMCM10" ], [ "CMT_MMCM_A_RDCLK_TOFIFO", "CMT_PHASER_OUT_A_RDCLK_TOFIFO" ], + [ + "CMT_MMCM_PHASER_OUT_A_OCLK", + "CMT_PHASER_OUT_A_OCLK" + ], + [ + "CMT_MMCM_A_RDEN_TOFIFO", + "CMT_PHASER_OUT_A_RDEN_TOFIFO" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM6", + "CMT_LR_LOWER_T_CLK_MMCM6" + ], + [ + "MMCM_CLK_FREQ_BB_NS2", + "MMCM_CLK_FREQBB_REBUFOUT2" + ], [ "CMT_MMCM_PHYCTRL_SYNC_BB_UP", "CMT_PHASER_BOT_SYNC_BB" @@ -138726,2733 +22682,2233 @@ "CMT_PHASER_DOWN_PHASERREF_ABOVE1" ], [ - "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "CMT_PHASER_B_TOMMCM_ICLKDIV" + "CMT_MMCM_PHASERREF_BELOW0", + "CMT_PHASER_DOWN_PHASERREF_BELOW0" ], [ - "CMT_L_LOWER_B_CLK_PERF0", - "CMT_LR_LOWER_T_CLK_PERF0" + "CMT_MMCM_PHASERA_DTSBUS1", + "CMT_PHASERA_DTSBUS1" ], [ - "CMT_MMCM_PHASER_OUT_B_OCLK", - "CMT_PHASER_B_TOMMCM_OCLK" + "CMT_R_LOWER_B_CLK_IN1_HCLK", + "CMT_LR_LOWER_T_CLK_IN1_HCLK" ], [ - "CMT_L_LOWER_B_CLK_MMCM6", - "CMT_LR_LOWER_T_CLK_MMCM6" + "CMT_R_LOWER_B_CLK_PERF3", + "CMT_LR_LOWER_T_CLK_PERF3" ], [ - "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "CMT_PHASER_B_TOMMCM_OCLKDIV" + "CMT_R_LOWER_B_CLK_MMCM5", + "CMT_LR_LOWER_T_CLK_MMCM5" ], [ - "CMT_MMCM_PHASERA_DTSBUS0", - "CMT_PHASERA_DTSBUS0" + "MMCMOUT_CLK_FREQ_BB_3", + "MMCMOUT_CLK_FREQ_BB_REBUFIN3" ], [ - "CMT_L_LOWER_B_CLK_MMCM12", - "CMT_LR_LOWER_T_CLK_MMCM12" + "CMT_MMCM_PHASERA_CTSBUS0", + "CMT_PHASERA_CTSBUS0" ], [ - "CMT_L_LOWER_B_CLK_PERF1", - "CMT_LR_LOWER_T_CLK_PERF1" + "CMT_R_LOWER_B_CLK_MMCM8", + "CMT_LR_LOWER_T_CLK_MMCM8" + ], + [ + "CMT_R_LOWER_B_CLK_MMCM2", + "CMT_LR_LOWER_T_CLK_MMCM2" + ], + [ + "MMCMOUT_CLK_FREQ_BB_1", + "MMCMOUT_CLK_FREQ_BB_REBUFIN1" ], [ "CMT_MMCM_PHASERA_DQSBUS1", "CMT_PHASERA_DQSBUS1" ], [ - "CMT_MMCM_PHASER_IN_A_ICLKDIV", - "CMT_PHASER_IN_A_ICLKDIV" + "CMT_R_LOWER_B_CLK_PERF2", + "CMT_LR_LOWER_T_CLK_PERF2" ], [ - "CMT_L_LOWER_B_CLK_MMCM11", + "CMT_R_LOWER_B_CLK_MMCM11", "CMT_LR_LOWER_T_CLK_MMCM11" ], - [ - "CMT_L_LOWER_B_CLK_IN3_HCLK", - "CMT_LR_LOWER_T_CLK_IN3_HCLK" - ], - [ - "MMCMOUT_CLK_FREQ_BB_2", - "MMCMOUT_CLK_FREQ_BB_REBUFIN2" - ], - [ - "CMT_L_LOWER_B_CLK_MMCM5", - "CMT_LR_LOWER_T_CLK_MMCM5" - ], - [ - "CMT_MMCM_PHASERA_DQSBUS0", - "CMT_PHASERA_DQSBUS0" - ], - [ - "CMT_MMCM_PHASERREF1", - "CMT_PHASER_DOWN_PHASERREF1" - ], - [ - "CMT_L_LOWER_B_CLK_MMCM8", - "CMT_LR_LOWER_T_CLK_MMCM8" - ], - [ - "CMT_L_LOWER_B_CLK_IN1_HCLK", - "CMT_LR_LOWER_T_CLK_IN1_HCLK" - ], - [ - "CMT_MMCM_PHASERREF_BELOW1", - "CMT_PHASER_DOWN_PHASERREF_BELOW1" - ], [ "MMCMOUT_CLK_FREQ_BB_0", "MMCMOUT_CLK_FREQ_BB_REBUFIN0" ], [ - "CMT_L_LOWER_B_CLK_MMCM10", - "CMT_LR_LOWER_T_CLK_MMCM10" + "CMT_R_LOWER_B_CLK_PERF0", + "CMT_LR_LOWER_T_CLK_PERF0" ], [ - "CMT_MMCM_PHASERREF_ABOVE0", - "CMT_PHASER_DOWN_PHASERREF_ABOVE0" + "CMT_R_LOWER_B_CLK_MMCM7", + "CMT_LR_LOWER_T_CLK_MMCM7" ], [ - "CMT_L_LOWER_B_CLK_PERF2", - "CMT_LR_LOWER_T_CLK_PERF2" + "CMT_R_LOWER_B_CLK_MMCM12", + "CMT_LR_LOWER_T_CLK_MMCM12" ], [ - "CMT_L_LOWER_B_CLK_MMCM4", - "CMT_LR_LOWER_T_CLK_MMCM4" + "MMCM_CLK_FREQ_BB_NS1", + "MMCM_CLK_FREQBB_REBUFOUT1" + ], + [ + "CMT_MMCM_PHASER_IN_B_ICLK", + "CMT_PHASER_B_TOMMCM_ICLK" + ], + [ + "MMCM_CLK_FREQ_BB_NS0", + "MMCM_CLK_FREQBB_REBUFOUT0" + ], + [ + "CMT_MMCM_PHASERA_DTSBUS0", + "CMT_PHASERA_DTSBUS0" ] - ], - "tile_types": [ - "CMT_TOP_L_LOWER_B", - "CMT_TOP_L_LOWER_T" - ], - "grid_deltas": [ - 0, - -9 ] }, { - "wire_pairs": [ - [ - "CLBLM_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLBLM_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLBLM_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLBLM_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLBLM_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLBLM_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLBLM_LH12", - "VBRK_LH12" - ], - [ - "CLBLM_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLBLM_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLBLM_LH8", - "VBRK_LH8" - ], - [ - "CLBLM_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLBLM_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLBLM_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLBLM_LH10", - "VBRK_LH10" - ], - [ - "CLBLM_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLBLM_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLBLM_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLBLM_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLBLM_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLBLM_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLBLM_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLBLM_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLBLM_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLBLM_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLBLM_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLBLM_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLBLM_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLBLM_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLBLM_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLBLM_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLBLM_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLBLM_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLBLM_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLBLM_LH2", - "VBRK_LH2" - ], - [ - "CLBLM_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLBLM_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLBLM_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLBLM_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLBLM_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLBLM_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLBLM_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLBLM_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLBLM_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLBLM_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLBLM_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLBLM_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLBLM_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLBLM_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLBLM_LH11", - "VBRK_LH11" - ], - [ - "CLBLM_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLBLM_LH3", - "VBRK_LH3" - ], - [ - "CLBLM_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLBLM_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLBLM_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLBLM_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLBLM_LH4", - "VBRK_LH4" - ], - [ - "CLBLM_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLBLM_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLBLM_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLBLM_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLBLM_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLBLM_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLBLM_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLBLM_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLBLM_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLBLM_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLBLM_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLBLM_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLBLM_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLBLM_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLBLM_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLBLM_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLBLM_EE2A2", - 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"IOI_RCLK_FORIO0", + "IOI_SING_RCLK_FORIO0" + ], + [ + "IOI_RCLK_FORIO1", + "IOI_SING_RCLK_FORIO1" + ], + [ + "IOI_IOCLK1", + "IOI_SING_IOCLK1" + ], + [ + "IOI_IOCLK3", + "IOI_SING_IOCLK3" + ], + [ + "IOI_TBYTEIN", + "IOI_SING_TBYTEIN" + ], + [ + "IOI_LEAF_GCLK5", + "IOI_SING_LEAF_GCLK5" + ], + [ + "IOI_LEAF_GCLK2", + "IOI_SING_LEAF_GCLK2" + ], + [ + "IOI_RCLK_FORIO2", + "IOI_SING_RCLK_FORIO2" + ] + ] + }, + { "tile_types": [ "CFG_CENTER_BOT", "VFRAME" ], "grid_deltas": [ 1, - 10 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_VFRAME_CK_BUFHCLK6" - ], - [ - "HCLK_INT_INTERFACE_CK_IN7", - "HCLK_VFRAME_CK_IN7" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_VFRAME_CK_BUFHCLK5" - ], - [ - "HCLK_INT_INTERFACE_CK_IN5", - "HCLK_VFRAME_CK_IN5" - ], - [ - "HCLK_INT_INTERFACE_CK_IN6", - "HCLK_VFRAME_CK_IN6" - ], - [ - "HCLK_INT_INTERFACE_CK_IN12", - "HCLK_VFRAME_CK_IN12" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_CK_IN8", - "HCLK_VFRAME_CK_IN8" - ], - [ - "HCLK_INT_INTERFACE_CK_IN13", - "HCLK_VFRAME_CK_IN13" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_VFRAME_CK_BUFHCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_VFRAME_CK_BUFRCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_VFRAME_CK_BUFHCLK10" - ], - [ - "HCLK_INT_INTERFACE_CK_IN3", - "HCLK_VFRAME_CK_IN3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_VFRAME_CK_BUFHCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_IN11", - "HCLK_VFRAME_CK_IN11" - ], - [ - "HCLK_INT_INTERFACE_CK_IN0", - "HCLK_VFRAME_CK_IN0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_VFRAME_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_VFRAME_CK_BUFHCLK9" - ], - [ - "HCLK_INT_INTERFACE_CK_IN1", - "HCLK_VFRAME_CK_IN1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_VFRAME_CK_BUFHCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_VFRAME_CK_BUFRCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN10", - "HCLK_VFRAME_CK_IN10" - ], - [ - "HCLK_INT_INTERFACE_CK_IN9", - "HCLK_VFRAME_CK_IN9" - ], - [ - "HCLK_INT_INTERFACE_CK_IN2", - "HCLK_VFRAME_CK_IN2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_VFRAME_CK_BUFRCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_VFRAME_CK_BUFHCLK11" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_VFRAME_CK_BUFHCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN4", - "HCLK_VFRAME_CK_IN4" - ] - ], - "tile_types": [ - "HCLK_INT_INTERFACE", - "HCLK_VFRAME" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT26", - "PCIE_IMUX26_L_0" - ], - [ - "INT_INTERFACE_NE4C1", - "PCIE_NE4C1_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "PCIE_LOGIC_OUTS_B22_L_0" - ], - [ - "INT_INTERFACE_SW2A1", - "PCIE_SW2A1_0" - ], - [ - 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"PCIE_INT_INTERFACE_IMUX_L_OUT45", - "PCIE_IMUX45_L_0" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT0", - "PCIE_IMUX0_L_0" - ], - [ - "INT_INTERFACE_WW4B3", - "PCIE_WW4B3_0" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT8", - "PCIE_IMUX8_L_0" - ], - [ - "INT_INTERFACE_WL1END1", - "PCIE_WL1END1_0" - ], - [ - "INT_INTERFACE_ER1BEG0", - "PCIE_ER1BEG0_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "PCIE_LOGIC_OUTS_B6_L_0" - ], - [ - "INT_INTERFACE_BYP6", - "PCIE_BYP6_L_0" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT9", - "PCIE_IMUX9_L_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "PCIE_LOGIC_OUTS_B10_L_0" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT6", - "PCIE_IMUX6_L_0" - ], - [ - "INT_INTERFACE_EE4B3", - "PCIE_EE4B3_0" - ], - [ - "INT_INTERFACE_NE4BEG1", - "PCIE_NE4BEG1_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "PCIE_LOGIC_OUTS_B4_L_0" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT46", - "PCIE_IMUX46_L_0" - ], - [ - "INT_INTERFACE_SE4C1", - "PCIE_SE4C1_0" - ], - [ - "INT_INTERFACE_SW4END3", - "PCIE_SW4END3_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "PCIE_LOGIC_OUTS_B18_L_0" - ], - [ - "INT_INTERFACE_LH6", - "PCIE_LH6_0" - ], - [ - "INT_INTERFACE_WW4C2", - "PCIE_WW4C2_0" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT16", - "PCIE_IMUX16_L_0" - ] - ], - "tile_types": [ - "PCIE_INT_INTERFACE_L", - "PCIE_TOP" - ], - "grid_deltas": [ - -5, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_WW2A1_2", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_BUFG_IMUX17_2", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_FAN3_2", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_2", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_BUFG_IMUX23_2", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_BUFG_IMUX3_2", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_EE4BEG1_2", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_NE4BEG0_2", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_FAN0_2", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_BUFG_IMUX7_2", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_EE4BEG3_2", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_IMUX14_2", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE4A3_2", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WR1END3_2", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_BUFG_IMUX39_2", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_BYP7_2", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WW2A3_2", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_WW4C3_2", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_NE4C1_2", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_ER1BEG0_2", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SE2A0_2", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_BUFG_IMUX22_2", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_SW4A3_2", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NE4C3_2", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_FAN7_2", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_BUFG_IMUX16_2", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_SE4BEG3_2", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NE4BEG2_2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NW4A0_2", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WL1END2_2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WW4C2_2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW4END0_2", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WW4A2_2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_SE4C1_2", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_CTRL0_2", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EL1BEG2_2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_BUFG_IMUX47_2", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_BUFG_IMUX30_2", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_WW2END3_2", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_BUFG_IMUX44_2", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_BUFG_IMUX21_2", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_CTRL1_2", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_NW4END1_2", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_EL1BEG3_2", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_LH2_2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_BUFG_IMUX26_2", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_SW4END3_2", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_BUFG_IMUX45_2", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_EE4BEG0_2", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_2", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_BUFG_IMUX40_2", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_2", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_BUFG_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_SW2A3_2", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_NW4END0_2", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_BUFG_IMUX13_2", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_BUFG_IMUX31_2", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX35_2", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_WW4END3_2", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_BUFG_IMUX8_2", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_SE4BEG1_2", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_FAN2_2", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WR1END0_2", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE2BEG1_2", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_BUFG_IMUX37_2", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_FAN6_2", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_SE2A3_2", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_LH12_2", - "INT_INTERFACE_LH12" - ], - [ - "CLK_BUFG_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_BUFG_IMUX18_2", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_IMUX43_2", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_BYP3_2", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_2", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_NE2A3_2", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_IMUX11_2", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SW4A2_2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_SW2A0_2", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_BUFG_IMUX27_2", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_BUFG_IMUX20_2", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_BUFG_IMUX29_2", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_BUFG_IMUX42_2", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_BUFG_IMUX36_2", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_WR1END1_2", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4A0_2", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_LH6_2", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH9_2", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_WW4END2_2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE2BEG0_2", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_SE2A1_2", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE2A0_2", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_SE4BEG2_2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_WW4END1_2", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_NE2A1_2", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_EE4C2_2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WW2END2_2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_NW4END3_2", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_NW4END2_2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_WR1END2_2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW4C0_2", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_EE4B3_2", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_BUFG_IMUX0_2", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_LH1_2", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_FAN1_2", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_BUFG_IMUX12_2", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_NW4A1_2", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_SE4C2_2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_EE4B0_2", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_WW4B3_2", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE2A1_2", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_EE4A1_2", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_SE4BEG0_2", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_EE4BEG2_2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_BYP0_2", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE2A2_2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_BUFG_IMUX19_2", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_BUFG_IMUX33_2", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_BYP4_2", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_NE2A2_2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_2", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_HROW_EE4B2_2", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_BYP5_2", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_BYP1_2", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_2", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_HROW_NE4BEG3_2", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_WW2A0_2", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW2END0_2", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_BUFG_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_EE2BEG3_2", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW4B0_2", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_LH10_2", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_FAN5_2", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_WW4A3_2", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_LH4_2", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_NW2A0_2", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_WL1END0_2", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_FAN4_2", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_BUFG_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_BUFG_IMUX2_2", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_BUFG_IMUX15_2", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_NW4A3_2", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_BUFG_IMUX4_2", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_2", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_NW2A2_2", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_NW2A3_2", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_LH3_2", - "INT_INTERFACE_LH3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_2", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_HROW_LH11_2", - "INT_INTERFACE_LH11" - ], - [ - "CLK_BUFG_IMUX24_2", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_NE2A0_2", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_SE4C0_2", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_EE4A0_2", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_WW4B2_2", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_WW4C1_2", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_BUFG_IMUX5_2", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_BUFG_IMUX46_2", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_WW2A2_2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_LH5_2", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_SW4A1_2", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_CLK0_2", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_BUFG_IMUX32_2", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_BUFG_IMUX9_2", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_ER1BEG2_2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_SE2A2_2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2END1_2", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_EE4C0_2", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE4B1_2", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_BUFG_IMUX6_2", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_EE4A2_2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_SW2A1_2", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_BUFG_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_BYP6_2", - "INT_INTERFACE_BYP6" - ] - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, -2 - ] - }, - { + ], "wire_pairs": [ [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_VFRAME_CK_BUFHCLK6" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_VFRAME_CK_IN7" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_VFRAME_CK_BUFRCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_VFRAME_CK_IN1" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_VFRAME_CK_BUFHCLK3" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_VFRAME_CK_BUFHCLK5" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFRCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_VFRAME_CK_BUFHCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_VFRAME_CK_IN5" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_VFRAME_CK_BUFHCLK11" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_VFRAME_CK_IN6" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_VFRAME_CK_BUFHCLK9" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_VFRAME_CK_IN8" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_VFRAME_CK_IN3" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN9", - "HCLK_VFRAME_CK_IN9" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_VFRAME_CK_BUFHCLK10" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_VFRAME_CK_IN10" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_VFRAME_CK_IN13" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_VFRAME_CK_BUFHCLK7" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK4" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_VFRAME_CK_BUFRCLK0" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_VFRAME_CK_IN0" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_VFRAME_CK_BUFHCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_VFRAME_CK_IN4" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK8" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_VFRAME_CK_IN11" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_VFRAME_CK_BUFRCLK2" - ], - [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_VFRAME_CK_BUFHCLK1" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_VFRAME_CK_IN2" - ], - [ - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_VFRAME_CK_IN12" - ] - ], - "tile_types": [ - "HCLK_FEEDTHRU_1", - "HCLK_VFRAME" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "DSP_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "DSP_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "DSP_EE4B2_3", - "INT_INTERFACE_EE4B2" - ], - [ - "DSP_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "DSP_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "DSP_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "DSP_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "DSP_LOGIC_OUTS_B8_3", - "INT_INTERFACE_LOGIC_OUTS_B8" - ], - [ - "DSP_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" - ], - [ - "DSP_NE4C3_3", - "INT_INTERFACE_NE4C3" - ], - [ - "DSP_IMUX39_3", - "INT_INTERFACE_IMUX39" - ], - [ - "DSP_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "DSP_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "DSP_LOGIC_OUTS_B16_3", - "INT_INTERFACE_LOGIC_OUTS_B16" - ], - [ - "DSP_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "DSP_LOGIC_OUTS_B1_3", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "DSP_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "DSP_FAN7_3", - "INT_INTERFACE_FAN7" - ], - [ - "DSP_WW4C2_3", - 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"DSP_IMUX24_3", - "INT_INTERFACE_IMUX24" - ], - [ - "DSP_BYP0_3", - "INT_INTERFACE_BYP0" - ], - [ - "DSP_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" - ], - [ - "DSP_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "DSP_WL1END1_3", - "INT_INTERFACE_WL1END1" - ], - [ - "DSP_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "DSP_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "DSP_NW2A2_3", - "INT_INTERFACE_NW2A2" - ], - [ - "DSP_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "DSP_LOGIC_OUTS_B6_3", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "DSP_EE4C3_3", - "INT_INTERFACE_EE4C3" - ], - [ - "DSP_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "DSP_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "DSP_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "DSP_SW4A0_3", - "INT_INTERFACE_SW4A0" - ], - [ - "DSP_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "DSP_CLK1_3", - "INT_INTERFACE_CLK1" - ], - [ - "DSP_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" - ], - [ - "DSP_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - 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[ + "CFG_CENTER_WR1END0_12", + "VFRAME_WR1END0" + ], + [ + "CFG_CENTER_IMUX29_12", + "VFRAME_IMUX29" + ], + [ + "CFG_CENTER_NE4BEG3_12", + "VFRAME_NE4BEG3" + ], + [ + "CFG_CENTER_IMUX38_12", + "VFRAME_IMUX38" + ], + [ + "CFG_CENTER_SE4C2_12", + "VFRAME_SE4C2" + ], + [ + "CFG_CENTER_SW4A1_12", + "VFRAME_SW4A1" + ], + [ + "CFG_CENTER_NW4A1_12", + "VFRAME_NW4A1" + ], + [ + "CFG_CENTER_FAN0_12", + "VFRAME_FAN0" + ], + [ + "CFG_CENTER_IMUX34_12", + "VFRAME_IMUX34" + ], + [ + "CFG_CENTER_NE4C2_12", + "VFRAME_NE4C2" + ], + [ + "CFG_CENTER_EE4A1_12", + "VFRAME_EE4A1" + ], + [ + "CFG_CENTER_WW2A2_12", + "VFRAME_WW2A2" + ], + [ + "CFG_CENTER_LH10_12", + "VFRAME_LH10" + ], + [ + "CFG_CENTER_SW4END1_12", + "VFRAME_SW4END1" + ], + [ + "CFG_CENTER_WW4B1_12", + "VFRAME_WW4B1" + ], + [ + "CFG_CENTER_WW4B0_12", + "VFRAME_WW4B0" + ], + [ + "CFG_CENTER_LH11_12", + "VFRAME_LH11" + ], + [ + "CFG_CENTER_NE2A3_12", + "VFRAME_NE2A3" + ], + [ + "CFG_CENTER_EE4A2_12", + "VFRAME_EE4A2" + ], + [ + "CFG_CENTER_CLK1_12", + "VFRAME_CLK1" + ], + [ + "CFG_CENTER_IMUX32_12", + "VFRAME_IMUX32" + ], + [ + "CFG_CENTER_LH3_12", + "VFRAME_LH3" + ], + [ + "CFG_CENTER_IMUX12_12", + "VFRAME_IMUX12" + ], + [ + "CFG_CENTER_NE2A1_12", + "VFRAME_NE2A1" + ], + [ + "CFG_CENTER_IMUX11_12", + "VFRAME_IMUX11" + ], + [ + "CFG_CENTER_CTRL1_12", + "VFRAME_CTRL1" + ], + [ + "CFG_CENTER_ER1BEG1_12", + "VFRAME_ER1BEG1" + ], + [ + "CFG_CENTER_EL1BEG2_12", + "VFRAME_EL1BEG2" + ], + [ + "CFG_CENTER_LH8_12", + "VFRAME_LH8" + ], [ "CFG_CENTER_EL1BEG3_12", "VFRAME_EL1BEG3" @@ -151785,393 +52957,73 @@ "CFG_CENTER_SE2A1_12", "VFRAME_SE2A1" ], - [ - "CFG_CENTER_NE4BEG1_12", - "VFRAME_NE4BEG1" - ], - [ - "CFG_CENTER_SE4BEG1_12", - "VFRAME_SE4BEG1" - ], - [ - "CFG_CENTER_WW4B1_12", - "VFRAME_WW4B1" - ], - [ - "CFG_CENTER_SW4A2_12", - "VFRAME_SW4A2" - ], - [ - "CFG_CENTER_IMUX43_12", - "VFRAME_IMUX43" - ], - [ - "CFG_CENTER_NE2A0_12", - "VFRAME_NE2A0" - ], - [ - "CFG_CENTER_EE4C3_12", - "VFRAME_EE4C3" - ], - [ - "CFG_CENTER_IMUX23_12", - "VFRAME_IMUX23" - ], - [ - "CFG_CENTER_ER1BEG3_12", - "VFRAME_ER1BEG3" - ], - [ - "CFG_CENTER_IMUX31_12", - "VFRAME_IMUX31" - ], - [ - "CFG_CENTER_NW2A2_12", - "VFRAME_NW2A2" - ], - [ - "CFG_CENTER_IMUX24_12", - "VFRAME_IMUX24" - ], - [ - "CFG_CENTER_FAN5_12", - "VFRAME_FAN5" - ], - [ - "CFG_CENTER_FAN1_12", - "VFRAME_FAN1" - ], - [ - "CFG_CENTER_IMUX39_12", - "VFRAME_IMUX39" - ], - [ - "CFG_CENTER_FAN3_12", - "VFRAME_FAN3" - ], - [ - "CFG_CENTER_EL1BEG2_12", - "VFRAME_EL1BEG2" - ], - [ - "CFG_CENTER_EE2BEG1_12", - "VFRAME_EE2BEG1" - ], - [ - "CFG_CENTER_NE4BEG3_12", - "VFRAME_NE4BEG3" - ], - [ - "CFG_CENTER_WW4A2_12", - "VFRAME_WW4A2" - ], - [ - "CFG_CENTER_EE4BEG3_12", - "VFRAME_EE4BEG3" - ], - [ - "CFG_CENTER_BYP3_12", - "VFRAME_BYP3" - ], - [ - "CFG_CENTER_IMUX29_12", - "VFRAME_IMUX29" - ], - [ - "CFG_CENTER_IMUX45_12", - "VFRAME_IMUX45" - ], - [ - "CFG_CENTER_IMUX18_12", - "VFRAME_IMUX18" - ], - [ - "CFG_CENTER_SE4BEG3_12", - "VFRAME_SE4BEG3" - ], - [ - "CFG_CENTER_WW4END3_12", - "VFRAME_WW4END3" - ], - [ - "CFG_CENTER_WW2END3_12", - "VFRAME_WW2END3" - ], - [ - "CFG_CENTER_IMUX26_12", - "VFRAME_IMUX26" - ], - [ - "CFG_CENTER_NW4A0_12", - "VFRAME_NW4A0" - ], - [ - "CFG_CENTER_EE4B0_12", - "VFRAME_EE4B0" - ], - [ - "CFG_CENTER_IMUX10_12", - "VFRAME_IMUX10" - ], - [ - "CFG_CENTER_IMUX30_12", - "VFRAME_IMUX30" - ], - [ - "CFG_CENTER_SE4C2_12", - "VFRAME_SE4C2" - ], - [ - "CFG_CENTER_FAN0_12", - "VFRAME_FAN0" - ], - [ - "CFG_CENTER_FAN2_12", - "VFRAME_FAN2" - ], - [ - "CFG_CENTER_NW4END0_12", - "VFRAME_NW4END0" - ], - [ - "CFG_CENTER_NW4A3_12", - "VFRAME_NW4A3" - ], - [ - "CFG_CENTER_EE4B2_12", - "VFRAME_EE4B2" - ], - [ - "CFG_CENTER_LH11_12", - "VFRAME_LH11" - ], - [ - "CFG_CENTER_EE2BEG0_12", - "VFRAME_EE2BEG0" - ], - [ - "CFG_CENTER_IMUX44_12", - "VFRAME_IMUX44" - ], - [ - "CFG_CENTER_SW4END0_12", - "VFRAME_SW4END0" - ], - [ - "CFG_CENTER_IMUX7_12", - "VFRAME_IMUX7" - ], - [ - "CFG_CENTER_BYP2_12", - "VFRAME_BYP2" - ], - [ - "CFG_CENTER_EE2A2_12", - "VFRAME_EE2A2" - ], - [ - "CFG_CENTER_IMUX34_12", - "VFRAME_IMUX34" - ], - [ - "CFG_CENTER_NW4END2_12", - "VFRAME_NW4END2" - ], - [ - "CFG_CENTER_LH9_12", - "VFRAME_LH9" - ], - [ - "CFG_CENTER_NE4C1_12", - "VFRAME_NE4C1" - ], - [ - "CFG_CENTER_SW2A1_12", - "VFRAME_SW2A1" - ], - [ - "CFG_CENTER_WW4C0_12", - "VFRAME_WW4C0" - ], - [ - "CFG_CENTER_EE4C2_12", - "VFRAME_EE4C2" - ], - [ - "CFG_CENTER_EE4A0_12", - "VFRAME_EE4A0" - ], - [ - "CFG_CENTER_IMUX16_12", - "VFRAME_IMUX16" - ], - [ - "CFG_CENTER_LH10_12", - "VFRAME_LH10" - ], - [ - "CFG_CENTER_IMUX46_12", - "VFRAME_IMUX46" - ], - [ - "CFG_CENTER_IMUX13_12", - "VFRAME_IMUX13" - ], - [ - "CFG_CENTER_LH5_12", - "VFRAME_LH5" - ], - [ - "CFG_CENTER_WW4B2_12", - "VFRAME_WW4B2" - ], - [ - "CFG_CENTER_NW4A1_12", - "VFRAME_NW4A1" - ], - [ - "CFG_CENTER_WW4C1_12", - "VFRAME_WW4C1" - ], - [ - "CFG_CENTER_WL1END0_12", - "VFRAME_WL1END0" - ], - [ - "CFG_CENTER_EE4B1_12", - "VFRAME_EE4B1" - ], - [ - "CFG_CENTER_IMUX27_12", - "VFRAME_IMUX27" - ], - [ - "CFG_CENTER_IMUX2_12", - "VFRAME_IMUX2" - ], - [ - "CFG_CENTER_WR1END3_12", - "VFRAME_WR1END3" - ], - [ - "CFG_CENTER_EE2BEG2_12", - "VFRAME_EE2BEG2" - ], - [ - "CFG_CENTER_LH6_12", - "VFRAME_LH6" - ], - [ - "CFG_CENTER_WW4A1_12", - "VFRAME_WW4A1" - ], - [ - "CFG_CENTER_EE2A3_12", - "VFRAME_EE2A3" - ], - [ - "CFG_CENTER_WW2A0_12", - "VFRAME_WW2A0" - ], - [ - "CFG_CENTER_NW2A1_12", - "VFRAME_NW2A1" - ], - [ - "CFG_CENTER_IMUX1_12", - "VFRAME_IMUX1" - ], - [ - "CFG_CENTER_IMUX17_12", - "VFRAME_IMUX17" - ], - [ - "CFG_CENTER_WR1END1_12", - "VFRAME_WR1END1" - ], - [ - "CFG_CENTER_WW4C3_12", - "VFRAME_WW4C3" - ], - [ - "CFG_CENTER_WW2END2_12", - "VFRAME_WW2END2" - ], [ "CFG_CENTER_IMUX36_12", "VFRAME_IMUX36" ], [ - "CFG_CENTER_EE4B3_12", - "VFRAME_EE4B3" + "CFG_CENTER_IMUX21_12", + "VFRAME_IMUX21" ], [ - "CFG_CENTER_WL1END1_12", - "VFRAME_WL1END1" + "CFG_CENTER_SE4BEG0_12", + "VFRAME_SE4BEG0" ], [ - "CFG_CENTER_EE4C1_12", - "VFRAME_EE4C1" + "CFG_CENTER_SE4C0_12", + "VFRAME_SE4C0" ], [ - "CFG_CENTER_WW4A0_12", - "VFRAME_WW4A0" + "CFG_CENTER_NW2A0_12", + "VFRAME_NW2A0" ], [ - "CFG_CENTER_WW4B3_12", - "VFRAME_WW4B3" + "CFG_CENTER_LH4_12", + "VFRAME_LH4" ], [ - "CFG_CENTER_WW4C2_12", - "VFRAME_WW4C2" - ], - [ - "CFG_CENTER_ER1BEG2_12", - "VFRAME_ER1BEG2" - ], - [ - "CFG_CENTER_BYP6_12", - "VFRAME_BYP6" - ], - [ - "CFG_CENTER_WW4END1_12", - "VFRAME_WW4END1" - ], - [ - "CFG_CENTER_WR1END2_12", - "VFRAME_WR1END2" - ], - [ - "CFG_CENTER_SW2A3_12", - "VFRAME_SW2A3" - ], - [ - "CFG_CENTER_IMUX12_12", - "VFRAME_IMUX12" + "CFG_CENTER_IMUX4_12", + "VFRAME_IMUX4" ], [ "CFG_CENTER_WW2END0_12", "VFRAME_WW2END0" ], [ - "CFG_CENTER_NW2A3_12", - "VFRAME_NW2A3" + "CFG_CENTER_EE2A3_12", + "VFRAME_EE2A3" ], [ - "CFG_CENTER_LH12_12", - "VFRAME_LH12" + "CFG_CENTER_IMUX25_12", + "VFRAME_IMUX25" ], [ - "CFG_CENTER_EE2A1_12", - "VFRAME_EE2A1" + "CFG_CENTER_WW4A3_12", + "VFRAME_WW4A3" ], [ - "CFG_CENTER_IMUX14_12", - "VFRAME_IMUX14" + "CFG_CENTER_BYP3_12", + "VFRAME_BYP3" ], [ - "CFG_CENTER_EE4C0_12", - "VFRAME_EE4C0" + "CFG_CENTER_FAN5_12", + "VFRAME_FAN5" + ], + [ + "CFG_CENTER_SW4END2_12", + "VFRAME_SW4END2" + ], + [ + "CFG_CENTER_EE4B1_12", + "VFRAME_EE4B1" + ], + [ + "CFG_CENTER_WW2END3_12", + "VFRAME_WW2END3" + ], + [ + "CFG_CENTER_NW2A2_12", + "VFRAME_NW2A2" ], [ "CFG_CENTER_EE2A0_12", @@ -152182,18352 +53034,2452 @@ "VFRAME_EE2BEG3" ], [ - "CFG_CENTER_NE2A2_12", - "VFRAME_NE2A2" - ], - [ - "CFG_CENTER_SE2A0_12", - "VFRAME_SE2A0" - ], - [ - "CFG_CENTER_FAN6_12", - "VFRAME_FAN6" - ], - [ - "CFG_CENTER_NE4C3_12", - "VFRAME_NE4C3" - ], - [ - "CFG_CENTER_WW4B0_12", - "VFRAME_WW4B0" - ], - [ - "CFG_CENTER_NW4END1_12", - "VFRAME_NW4END1" - ], - [ - "CFG_CENTER_BYP4_12", - "VFRAME_BYP4" - ], - [ - "CFG_CENTER_LH2_12", - "VFRAME_LH2" - ], - [ - "CFG_CENTER_FAN7_12", - "VFRAME_FAN7" - ], - [ - "CFG_CENTER_IMUX4_12", - "VFRAME_IMUX4" - ], - [ - "CFG_CENTER_SE4C0_12", - "VFRAME_SE4C0" - ], - [ - "CFG_CENTER_SW4END1_12", - "VFRAME_SW4END1" - ], - [ - "CFG_CENTER_ER1BEG1_12", - "VFRAME_ER1BEG1" - ], - [ - "CFG_CENTER_BYP7_12", - "VFRAME_BYP7" - ], - [ - "CFG_CENTER_EE4A1_12", - "VFRAME_EE4A1" - ], - [ - "CFG_CENTER_IMUX20_12", - "VFRAME_IMUX20" - ], - [ - "CFG_CENTER_LH7_12", - "VFRAME_LH7" - ], - [ - "CFG_CENTER_IMUX37_12", - "VFRAME_IMUX37" - ], - [ - "CFG_CENTER_CLK1_12", - "VFRAME_CLK1" - ], - [ - "CFG_CENTER_WR1END0_12", - "VFRAME_WR1END0" - ], - [ - "CFG_CENTER_NE4C2_12", - "VFRAME_NE4C2" - ], - [ - "CFG_CENTER_WW2A3_12", - "VFRAME_WW2A3" - ], - [ - "CFG_CENTER_IMUX15_12", - "VFRAME_IMUX15" - ], - [ - "CFG_CENTER_IMUX8_12", - "VFRAME_IMUX8" - ], - [ - "CFG_CENTER_BYP5_12", - "VFRAME_BYP5" - ], - [ - "CFG_CENTER_EL1BEG1_12", - "VFRAME_EL1BEG1" - ], - [ - "CFG_CENTER_IMUX28_12", - "VFRAME_IMUX28" - ], - [ - "CFG_CENTER_IMUX0_12", - "VFRAME_IMUX0" - ], - [ - "CFG_CENTER_WW4END2_12", - "VFRAME_WW4END2" - ], - [ - "CFG_CENTER_NW4A2_12", - "VFRAME_NW4A2" - ], - [ - "CFG_CENTER_CLK0_12", - "VFRAME_CLK0" - ], - [ - "CFG_CENTER_WL1END2_12", - "VFRAME_WL1END2" - ], - [ - "CFG_CENTER_CTRL1_12", - "VFRAME_CTRL1" - ], - [ - "CFG_CENTER_SE4C1_12", - "VFRAME_SE4C1" - ], - [ - "CFG_CENTER_SW4END2_12", - "VFRAME_SW4END2" - ], - [ - "CFG_CENTER_SE4BEG0_12", - "VFRAME_SE4BEG0" - ], - [ - "CFG_CENTER_WW2A2_12", - "VFRAME_WW2A2" - ], - [ - "CFG_CENTER_BYP0_12", - "VFRAME_BYP0" - ], - [ - "CFG_CENTER_SW2A2_12", - "VFRAME_SW2A2" - ], - [ - "CFG_CENTER_EE4BEG0_12", - "VFRAME_EE4BEG0" - ], - [ - "CFG_CENTER_NE4BEG0_12", - "VFRAME_NE4BEG0" - ], - [ - "CFG_CENTER_NE2A1_12", - "VFRAME_NE2A1" - ], - [ - "CFG_CENTER_EE4BEG1_12", - "VFRAME_EE4BEG1" - ], - [ - "CFG_CENTER_IMUX21_12", - "VFRAME_IMUX21" - ], - [ - "CFG_CENTER_IMUX3_12", - "VFRAME_IMUX3" - ], - [ - "CFG_CENTER_SE2A2_12", - "VFRAME_SE2A2" - ], - [ - "CFG_CENTER_NE4BEG2_12", - "VFRAME_NE4BEG2" - ], - [ - "CFG_CENTER_IMUX9_12", - "VFRAME_IMUX9" - ], - [ - "CFG_CENTER_SW4A1_12", - "VFRAME_SW4A1" - ], - [ - "CFG_CENTER_FAN4_12", - "VFRAME_FAN4" - ], - [ - "CFG_CENTER_EE4A2_12", - "VFRAME_EE4A2" - ], - [ - "CFG_CENTER_LH3_12", - "VFRAME_LH3" - ], - [ - "CFG_CENTER_NW4END3_12", - "VFRAME_NW4END3" - ], - [ - "CFG_CENTER_WW2END1_12", - "VFRAME_WW2END1" - ], - [ - "CFG_CENTER_LH1_12", - "VFRAME_LH1" - ], - [ - "CFG_CENTER_EL1BEG0_12", - "VFRAME_EL1BEG0" + "CFG_CENTER_IMUX39_12", + "VFRAME_IMUX39" ], [ "CFG_CENTER_CTRL0_12", "VFRAME_CTRL0" ], [ - "CFG_CENTER_IMUX35_12", - "VFRAME_IMUX35" - ], - [ - "CFG_CENTER_NE4C0_12", - "VFRAME_NE4C0" - ], - [ - "CFG_CENTER_BYP1_12", - "VFRAME_BYP1" - ], - [ - "CFG_CENTER_IMUX22_12", - "VFRAME_IMUX22" - ], - [ - "CFG_CENTER_IMUX33_12", - "VFRAME_IMUX33" - ], - [ - "CFG_CENTER_IMUX6_12", - "VFRAME_IMUX6" - ], - [ - "CFG_CENTER_LH4_12", - "VFRAME_LH4" - ], - [ - "CFG_CENTER_SE4BEG2_12", - "VFRAME_SE4BEG2" - ], - [ - "CFG_CENTER_WW4A3_12", - "VFRAME_WW4A3" - ], - [ - "CFG_CENTER_SW4END3_12", - "VFRAME_SW4END3" - ], - [ - "CFG_CENTER_IMUX42_12", - "VFRAME_IMUX42" - ], - [ - "CFG_CENTER_IMUX38_12", - "VFRAME_IMUX38" - ], - [ - "CFG_CENTER_EE4A3_12", - "VFRAME_EE4A3" - ], - [ - "CFG_CENTER_WW2A1_12", - "VFRAME_WW2A1" - ], - [ - "CFG_CENTER_IMUX32_12", - "VFRAME_IMUX32" - ], - [ - "CFG_CENTER_NE2A3_12", - "VFRAME_NE2A3" - ], - [ - "CFG_CENTER_SE4C3_12", - "VFRAME_SE4C3" - ], - [ - "CFG_CENTER_IMUX19_12", - "VFRAME_IMUX19" - ], - [ - "CFG_CENTER_LH8_12", - "VFRAME_LH8" - ], - [ - "CFG_CENTER_SW2A0_12", - "VFRAME_SW2A0" - ], - [ - "CFG_CENTER_IMUX47_12", - "VFRAME_IMUX47" - ], - [ - "CFG_CENTER_SE2A3_12", - "VFRAME_SE2A3" - ], - [ - "CFG_CENTER_NW2A0_12", - "VFRAME_NW2A0" - ], - [ - "CFG_CENTER_IMUX11_12", - "VFRAME_IMUX11" - ], - [ - "CFG_CENTER_SW4A0_12", - "VFRAME_SW4A0" - ], - [ - "CFG_CENTER_ER1BEG0_12", - "VFRAME_ER1BEG0" - ], - [ - "CFG_CENTER_IMUX41_12", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_WW4END0_12", - "VFRAME_WW4END0" - ], - [ - "CFG_CENTER_IMUX5_12", - "VFRAME_IMUX5" - ], - [ - "CFG_CENTER_WL1END3_12", - "VFRAME_WL1END3" - ], - [ - "CFG_CENTER_SW4A3_12", - "VFRAME_SW4A3" - ], - [ - "CFG_CENTER_IMUX40_12", - "VFRAME_IMUX40" - ], - [ - "CFG_CENTER_EE4BEG2_12", - "VFRAME_EE4BEG2" - ], - [ - "CFG_CENTER_IMUX25_12", - "VFRAME_IMUX25" - ] - ], - "tile_types": [ - "CFG_CENTER_BOT", - "VFRAME" - ], - "grid_deltas": [ - 1, - -2 - ] - }, - { - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], 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"DSP_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "DSP_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "DSP_LH7_3", - "VBRK_LH7" - ], - [ - "DSP_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "DSP_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "DSP_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "DSP_NE2A3_3", - "VBRK_NE2A3" - ], - [ - "DSP_MONITOR_P_3", - "VBRK_MONITOR_P" - ], - [ - "DSP_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "DSP_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "DSP_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "DSP_LH4_3", - "VBRK_LH4" - ], - [ - "DSP_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "DSP_EE4C0_3", - "VBRK_EE4C0" - ], - [ - "DSP_LH11_3", - "VBRK_LH11" - ], - [ - "DSP_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "DSP_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "DSP_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "DSP_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "DSP_LH12_3", - "VBRK_LH12" - ], - [ - "DSP_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "DSP_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "DSP_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "DSP_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "DSP_SW4A1_3", - "VBRK_SW4A1" - ], - [ - "DSP_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "DSP_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "DSP_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "DSP_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "DSP_LH2_3", - "VBRK_LH2" - ], - [ - "DSP_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "DSP_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "DSP_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "DSP_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "DSP_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "DSP_LH3_3", - "VBRK_LH3" - ], - [ - "DSP_SE4C3_3", - "VBRK_SE4C3" - ], - [ - "DSP_WW2A1_3", - "VBRK_WW2A1" - ], - [ - "DSP_WW4C2_3", - "VBRK_WW4C2" - ], - [ - "DSP_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "DSP_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "DSP_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "DSP_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "DSP_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "DSP_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "DSP_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "DSP_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "DSP_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "DSP_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "DSP_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "DSP_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "DSP_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "DSP_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "DSP_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "DSP_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "DSP_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "DSP_LH9_3", - "VBRK_LH9" - ], - [ - "DSP_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "DSP_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "DSP_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "DSP_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "DSP_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "DSP_ER1BEG0_3", - "VBRK_ER1BEG0" - ] - ], - "tile_types": [ - "DSP_L", - "VBRK" - ], - "grid_deltas": [ - -1, - -3 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_EL1BEG1_5", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_WW4C1_5", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_WW2END2_5", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_NW2A1_5", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_EE4B0_5", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_EE4A1_5", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_SE4C0_5", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_SW4A0_5", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_EL1BEG2_5", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_SE2A2_5", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_LH11_5", - "VBRK_LH11" - ], - [ - "CMT_TOP_ER1BEG0_5", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_EE4BEG1_5", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_NW2A0_5", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_NW4END2_5", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_WW4B2_5", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_EE2BEG0_5", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_EE4C1_5", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_ER1BEG2_5", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_EE2A1_5", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_SW4A2_5", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_WW4END3_5", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_LH5_5", - "VBRK_LH5" - ], - [ - "CMT_TOP_NW2A3_5", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_EE4B1_5", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_WW2A2_5", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_SW4END3_5", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SW2A0_5", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_EE2A0_5", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_WW4A0_5", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_SW2A1_5", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_EL1BEG0_5", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WL1END0_5", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_SE4C3_5", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_EE4C2_5", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_WL1END2_5", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_WR1END1_5", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_SE2A3_5", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_NE4C1_5", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_SW2A3_5", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_LH4_5", - "VBRK_LH4" - ], - [ - "CMT_TOP_EE4B3_5", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_ER1BEG3_5", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_NE2A1_5", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_SE4C2_5", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_SW4END2_5", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_LH10_5", - "VBRK_LH10" - ], - [ - "CMT_TOP_WR1END2_5", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_EE4A0_5", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_WR1END3_5", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW4B1_5", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WW4END0_5", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_WW2END1_5", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_LH7_5", - "VBRK_LH7" - ], - [ - "CMT_TOP_SE4BEG1_5", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_SW4A3_5", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_NE2A3_5", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_EL1BEG3_5", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_ER1BEG1_5", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EE4BEG3_5", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_NE4BEG2_5", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_EE2A3_5", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_WW2END0_5", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_NE2A2_5", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_NE4C2_5", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_WW4END1_5", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_NE4BEG1_5", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_WW2A1_5", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WL1END3_5", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_WW4B0_5", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_WW4A2_5", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_LH9_5", - "VBRK_LH9" - ], - [ - "CMT_TOP_SE4BEG0_5", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_EE2BEG3_5", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_NW4A0_5", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_WW2END3_5", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_NW4END1_5", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_NW4A1_5", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_NW4A2_5", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_EE4BEG0_5", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW4A1_5", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_WL1END1_5", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_SW4END0_5", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_WW4A3_5", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_EE4B2_5", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_SE4BEG2_5", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_SE4C1_5", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_SW4A1_5", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_NW4END3_5", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_SE4BEG3_5", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW4C0_5", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_LH12_5", - "VBRK_LH12" - ], - [ - "CMT_TOP_WW4C3_5", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_NE4BEG0_5", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_SW2A2_5", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_EE2A2_5", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_NE4BEG3_5", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_WW4B3_5", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_WW2A3_5", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_NE4C0_5", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_SE2A1_5", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_EE4A3_5", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_WW2A0_5", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_WW4C2_5", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_LH8_5", - "VBRK_LH8" - ], - [ - "CMT_TOP_EE4C3_5", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NW4A3_5", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_NW2A2_5", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WR1END0_5", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_EE2BEG2_5", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_EE4BEG2_5", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_LH3_5", - "VBRK_LH3" - ], - [ - "CMT_TOP_EE4C0_5", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_EE2BEG1_5", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_EE4A2_5", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_LH6_5", - "VBRK_LH6" - ], - [ - "CMT_TOP_NE4C3_5", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_NW4END0_5", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_NE2A0_5", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_SE2A0_5", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_LH1_5", - "VBRK_LH1" - ], - [ - "CMT_TOP_SW4END1_5", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_LH2_5", - "VBRK_LH2" - ], - [ - "CMT_TOP_WW4END2_5", - "VBRK_WW4END2" - ] - ], - "tile_types": [ - "CMT_TOP_L_UPPER_B", - "VBRK" - ], - "grid_deltas": [ - -1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" - ], - [ - "BRAM_FIFO36_CASCADEOUTA_1", - "HCLK_BRAM_CASCADEA_L" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" - ], - [ - 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"HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" - ], - [ - "BRAM_FIFO36_CASCADEOUTB_1", - "HCLK_BRAM_CASCADEB_L" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" - ] - ], - "tile_types": [ - "BRAM_L", - "HCLK_BRAM" - ], - "grid_deltas": [ - 0, - -5 - ] - }, - { - "wire_pairs": [ - [ - "CMT_FIFO_L_IMUX45_2", - "CMT_TOP_IMUX45_15" - ], - [ - "CMT_FIFO_L_IMUX44_1", - "CMT_TOP_IMUX44_14" - ], - [ - "CMT_FIFO_EE4B0_0", - "CMT_TOP_EE4B0_13" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_14" - ], - [ - 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"BRAM_WW4C2_4" - ], - [ - "INT_INTERFACE_NW2A3", - "BRAM_NW2A3_4" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_4" - ], - [ - "INT_INTERFACE_SE2A2", - "BRAM_SE2A2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX36", - "BRAM_IMUX36_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX12", - "BRAM_IMUX12_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX26", - "BRAM_IMUX26_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "BRAM_IMUX3_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B6", - "BRAM_LOGIC_OUTS_B6_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX42", - "BRAM_IMUX42_UTURN_4" - ], - [ - "INT_INTERFACE_WR1END1", - "BRAM_WR1END1_4" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX32", - "BRAM_IMUX32_UTURN_4" - ], - [ - "INT_INTERFACE_LH2", - "BRAM_LH2_4" - ], - [ - "INT_INTERFACE_WR1END3", - "BRAM_WR1END3_4" - ], - [ - "INT_INTERFACE_WW4B0", - "BRAM_WW4B0_4" - ], - [ - "INT_INTERFACE_WW4C1", - "BRAM_WW4C1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX26", - "BRAM_IMUX26_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX37", - "BRAM_IMUX37_UTURN_4" - ], - [ - "INT_INTERFACE_EE2BEG2", - "BRAM_EE2BEG2_4" - ], - [ - "INT_INTERFACE_WL1END1", - "BRAM_WL1END1_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "BRAM_IMUX31_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX22", - "BRAM_IMUX22_4" - ], - [ - "INT_INTERFACE_NE4BEG1", - "BRAM_NE4BEG1_4" - ], - [ - "INT_INTERFACE_EE4A1", - "BRAM_EE4A1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX15", - "BRAM_IMUX15_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX44", - "BRAM_IMUX44_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "BRAM_IMUX5_4" - ], - [ - "INT_INTERFACE_EE4A0", - "BRAM_EE4A0_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX46", - "BRAM_IMUX46_UTURN_4" - ], - [ - "INT_INTERFACE_BYP0", - "BRAM_BYP0_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "BRAM_IMUX8_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B5", - "BRAM_LOGIC_OUTS_B5_4" - ], - [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX17", - "BRAM_IMUX17_UTURN_4" - ], - [ - "INT_INTERFACE_WW4A1", - "BRAM_WW4A1_4" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_4" - ], - [ - "INT_INTERFACE_EE4A3", - "BRAM_EE4A3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX18", - "BRAM_IMUX18_4" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_4" - ], - [ - "INT_INTERFACE_WW2END2", - "BRAM_WW2END2_4" - ], - [ - "INT_INTERFACE_EE4A2", - "BRAM_EE4A2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_4" - ], - [ - "INT_INTERFACE_EE2BEG1", - "BRAM_EE2BEG1_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_4" - ], - [ - "INT_INTERFACE_NE4BEG0", - "BRAM_NE4BEG0_4" - ], - [ - "INT_INTERFACE_CTRL0", - "BRAM_CTRL0_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B16", - "BRAM_LOGIC_OUTS_B16_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B2", - "BRAM_LOGIC_OUTS_B2_4" - ], - [ - "INT_INTERFACE_BYP4", - "BRAM_BYP4_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - "BRAM_IMUX47_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX0", - "BRAM_IMUX0_4" - ], - [ - "INT_INTERFACE_WW2A2", - "BRAM_WW2A2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX5", - "BRAM_IMUX5_UTURN_4" - ], - [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_4" - ], - [ - "INT_INTERFACE_WL1END3", - "BRAM_WL1END3_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX30", - "BRAM_IMUX30_4" - ], - [ - "INT_INTERFACE_NW4A2", - "BRAM_NW4A2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX40", - "BRAM_IMUX40_UTURN_4" - ], - [ - "INT_INTERFACE_LH9", - "BRAM_LH9_4" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B10", - "BRAM_LOGIC_OUTS_B10_4" - ], - [ - "INT_INTERFACE_FAN0", - "BRAM_FAN0_4" - ], - [ - "INT_INTERFACE_SE4C1", - "BRAM_SE4C1_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX23", - "BRAM_IMUX23_UTURN_4" - ], - [ - "INT_INTERFACE_WL1END2", - "BRAM_WL1END2_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX29", - "BRAM_IMUX29_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX8", - "BRAM_IMUX8_UTURN_4" - ], - [ - "INT_INTERFACE_WW2END3", - "BRAM_WW2END3_4" - ], - [ - "INT_INTERFACE_LH12", - "BRAM_LH12_4" - ], - [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_4" - ], - [ - "INT_INTERFACE_EE4C1", - "BRAM_EE4C1_4" - ], - [ - "INT_INTERFACE_NE2A3", - "BRAM_NE2A3_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX9", - "BRAM_IMUX9_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX25", - "BRAM_IMUX25_UTURN_4" - ], - [ - "INT_INTERFACE_EL1BEG0", - "BRAM_EL1BEG0_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "BRAM_IMUX38_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX13", - "BRAM_IMUX13_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX7", - "BRAM_IMUX7_4" - ], - [ - "INT_INTERFACE_NE2A2", - "BRAM_NE2A2_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "BRAM_IMUX25_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_4" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX47", - "BRAM_IMUX47_UTURN_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "BRAM_IMUX6_4" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_4" - ], - [ - "INT_INTERFACE_WW2A1", - "BRAM_WW2A1_4" - ], - [ - "INT_INTERFACE_BRAM_IMUX43", - "BRAM_IMUX43_4" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX7", - "BRAM_IMUX7_UTURN_4" - ], - [ - "INT_INTERFACE_MONITOR_N", - "BRAM_MONITOR_N_4" - ] - ], - "tile_types": [ - "BRAM_INT_INTERFACE_R", - "BRAM_R" - ], - "grid_deltas": [ - 1, - 4 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_GTX_CK_IN10", - "HCLK_TERM_GTX_CK_IN10" - ], - [ - "HCLK_GTX_CK_IN11", - "HCLK_TERM_GTX_CK_IN11" - ], - [ - "HCLK_GTX_CK_IN7", - "HCLK_TERM_GTX_CK_IN7" - ], - [ - "HCLK_GTX_CK_IN4", - "HCLK_TERM_GTX_CK_IN4" - ], - [ - "HCLK_GTX_CK_IN5", - "HCLK_TERM_GTX_CK_IN5" - ], - [ - "HCLK_GTX_CK_IN8", - "HCLK_TERM_GTX_CK_IN8" - ], - [ - "HCLK_GTX_CK_IN6", - "HCLK_TERM_GTX_CK_IN6" - ], - [ - "HCLK_GTX_CK_IN13", - "HCLK_TERM_GTX_CK_IN13" - ], - [ - "HCLK_GTX_CK_IN9", - "HCLK_TERM_GTX_CK_IN9" - ], - [ - "HCLK_GTX_CK_IN12", - "HCLK_TERM_GTX_CK_IN12" - ] - ], - "tile_types": [ - "HCLK_GTX", - "HCLK_TERM_GTX" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "BRKH_CLB_COUT1_L", - "CLBLM_L_CIN" - ], - [ - "BRKH_CLB_COUT0_L", - "CLBLM_M_CIN" - ] - ], - "tile_types": [ - "BRKH_CLB", - "CLBLM_L" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "BRKH_CLB_COUT0_L", - "CLBLM_M_COUT_N" - ], - [ - "BRKH_CLB_COUT1_L", - "CLBLM_L_COUT_N" - ] - ], - "tile_types": [ - "BRKH_CLB", - "CLBLM_L" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_SW4END1_7", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_IMUX7_7", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_SE2A0_7", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_EE4C1_7", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_NE2A1_7", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_IMUX2_7", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WR1END2_7", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_IMUX47_7", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_BYP2_7", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_EE4C0_7", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE4BEG0_7", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_SW4A0_7", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_IMUX9_7", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_WW4B2_7", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_BYP7_7", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_CTRL0_7", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_SW4A2_7", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_SW4END0_7", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WW2END2_7", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_WR1END3_7", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_EE4B0_7", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_WW2A2_7", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_FAN5_7", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_NE4C3_7", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_LH7_7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NE2A0_7", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_WW4B1_7", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_NE4BEG2_7", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SE4C2_7", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_FAN0_7", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_EL1BEG3_7", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_IMUX22_7", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_SE4C3_7", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_LH4_7", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WW4END2_7", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE2A2_7", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_IMUX33_7", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX35_7", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_NW4END3_7", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SE4BEG0_7", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_CLK1_7", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_NW4END1_7", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_LH1_7", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX43_7", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_EE4B2_7", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_ER1BEG1_7", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_BYP1_7", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SE2A2_7", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_SE4BEG3_7", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_SW2A1_7", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_NW4A0_7", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_SE2A3_7", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_SW4END3_7", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EE2BEG1_7", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_IMUX27_7", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_CTRL1_7", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX38_7", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_IMUX1_7", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_SE4BEG1_7", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_WL1END3_7", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_WW2END0_7", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_NE4BEG3_7", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_WW2A3_7", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_LH6_7", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_IMUX16_7", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_SW4A3_7", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX39_7", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_IMUX6_7", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_SE4C0_7", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_IMUX19_7", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_NW2A1_7", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_NW2A3_7", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_BYP0_7", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_BYP3_7", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX23_7", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_NW4END0_7", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_LH2_7", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_BYP6_7", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX31_7", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_LH8_7", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_EL1BEG2_7", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_EE4A0_7", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_EE4BEG1_7", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_IMUX37_7", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_WW4A3_7", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_WW2END1_7", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW4END1_7", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_WR1END0_7", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_IMUX18_7", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_ER1BEG3_7", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_IMUX21_7", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_WW4C1_7", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_SW4END2_7", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE4A3_7", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_IMUX36_7", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_IMUX4_7", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX40_7", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_IMUX32_7", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_LH12_7", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WW4A0_7", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_BYP5_7", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_FAN6_7", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_EL1BEG1_7", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX26_7", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_IMUX13_7", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_IMUX44_7", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_NW2A2_7", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_IMUX24_7", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX15_7", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_IMUX20_7", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_IMUX3_7", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_EE4A2_7", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_IMUX45_7", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_WW2A1_7", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_SW2A0_7", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_WW4END3_7", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_NE2A2_7", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_IMUX8_7", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_IMUX17_7", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_SW2A2_7", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_LH3_7", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_NE4BEG1_7", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE4B1_7", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX28_7", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX12_7", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_IMUX14_7", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_SE4C1_7", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX5_7", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX42_7", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_NW4A1_7", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NE4C1_7", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_EE4B3_7", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_EE2A1_7", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_EE4C3_7", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE2A0_7", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_FAN1_7", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_WW4END0_7", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_EE2BEG2_7", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_WW4B3_7", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_LH11_7", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE4BEG2_7", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_NW2A0_7", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EE4BEG3_7", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_NE4C2_7", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX25_7", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_IMUX29_7", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_IMUX0_7", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_WW4C3_7", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_CLK0_7", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_FAN7_7", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW4A2_7", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_WW4C2_7", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_WW4A1_7", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_IMUX46_7", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_NE4BEG0_7", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_IMUX10_7", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_SW2A3_7", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_WW4B0_7", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_EE2A3_7", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_SE4BEG2_7", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_IMUX41_7", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_WL1END1_7", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_EE4A1_7", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_EE2BEG3_7", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WL1END0_7", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_IMUX34_7", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_ER1BEG2_7", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_NW4A2_7", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_EE4C2_7", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_IMUX11_7", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_BYP4_7", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_WR1END1_7", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_ER1BEG0_7", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_NE4C0_7", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_EE2BEG0_7", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_FAN4_7", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_WW2END3_7", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_LH5_7", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NW4A3_7", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_NE2A3_7", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_WL1END2_7", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_FAN3_7", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_LH9_7", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_WW2A0_7", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_FAN2_7", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_NW4END2_7", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EL1BEG0_7", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_LH10_7", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WW4C0_7", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_IMUX30_7", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SW4A1_7", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_SE2A1_7", - "INT_INTERFACE_SE2A1" - ] - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -4 - ] - }, - { - "wire_pairs": [ - [ - "MMCM_CLK_FREQ_BB_REBUF1_NS", - "TERM_CMT_FREQ_REF_NS1" - ], - [ - "MMCM_CLK_FREQ_BB_REBUF0_NS", - "TERM_CMT_FREQ_REF_NS0" - ], - [ - "MMCM_CLK_FREQ_BB_REBUF3_NS", - "TERM_CMT_FREQ_REF_NS3" - ], - [ - "MMCM_CLK_FREQ_BB_REBUF2_NS", - "TERM_CMT_FREQ_REF_NS2" - ] - ], - "tile_types": [ - "CMT_TOP_L_LOWER_B", - "TERM_CMT" - ], - "grid_deltas": [ - 0, - 9 - ] - }, - { - "wire_pairs": [ - [ - "GTPE2_BYP2_7", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX11_7", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX23_7", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX28_7", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_CTRL1_7", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX1_7", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_IMUX15_7", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX38_7", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_BYP5_7", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX14_7", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX27_7", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_FAN3_7", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_LOGIC_OUTS_B19_7", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_IMUX35_7", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX22_7", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_LOGIC_OUTS_B6_7", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_CLK0_7", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX47_7", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_LOGIC_OUTS_B5_7", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_IMUX30_7", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_BYP1_7", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_BYP0_7", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX10_7", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX8_7", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX44_7", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX43_7", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX21_7", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX9_7", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX42_7", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_FAN2_7", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX17_7", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX3_7", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX4_7", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_LOGIC_OUTS_B1_7", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX12_7", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX0_7", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_LOGIC_OUTS_B12_7", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_LOGIC_OUTS_B18_7", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_IMUX46_7", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX5_7", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_FAN6_7", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX6_7", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX32_7", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX31_7", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX45_7", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX13_7", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_FAN5_7", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_IMUX41_7", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX19_7", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_BYP6_7", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_LOGIC_OUTS_B4_7", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_IMUX20_7", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_LOGIC_OUTS_B0_7", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_LOGIC_OUTS_B9_7", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_FAN0_7", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_FAN7_7", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_LOGIC_OUTS_B15_7", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_IMUX16_7", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX37_7", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_LOGIC_OUTS_B16_7", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_CTRL0_7", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_LOGIC_OUTS_B21_7", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_LOGIC_OUTS_B2_7", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_IMUX36_7", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_IMUX33_7", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX25_7", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_BYP7_7", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX2_7", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX34_7", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX26_7", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_FAN1_7", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_LOGIC_OUTS_B7_7", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX29_7", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B14_7", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_BYP3_7", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX18_7", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_LOGIC_OUTS_B13_7", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_FAN4_7", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX39_7", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX24_7", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_LOGIC_OUTS_B3_7", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_BYP4_7", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX7_7", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX40_7", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_CLK1_7", - "VBRK_EXT_CLK1" - ] - ], - "tile_types": [ - "GTP_CHANNEL_2", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - -2 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - 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], + [ + "CMT_TOP_NW2A1_1", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_EE2A3_1", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_WW2END1_1", + "VBRK_WW2END1" + ], + [ + "CMT_TOP_SE4BEG0_1", + "VBRK_SE4BEG0" + ], + [ + "CMT_TOP_NE4BEG1_1", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4END0_1", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_WW2A2_1", + "VBRK_WW2A2" + ], [ "CMT_TOP_LH5_1", "VBRK_LH5" @@ -170546,15077 +55558,13641 @@ "VBRK_NW4END1" ], [ - "CMT_TOP_EE4B2_1", - "VBRK_EE4B2" + "CMT_TOP_WW4A3_1", + "VBRK_WW4A3" ], [ - "CMT_TOP_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_LH7_1", - "VBRK_LH7" - ], - [ - "CMT_TOP_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_LH6_1", - "VBRK_LH6" - ], - [ - "CMT_TOP_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_LH10_1", - "VBRK_LH10" - ], - [ - "CMT_TOP_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_LH4_1", - "VBRK_LH4" - ], - [ - "CMT_TOP_LH12_1", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CMT_TOP_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_LH11_1", - "VBRK_LH11" - ], - [ - "CMT_TOP_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_SE2A2_1", - "VBRK_SE2A2" + "CMT_TOP_LH1_1", + "VBRK_LH1" ], [ "CMT_TOP_WL1END2_1", "VBRK_WL1END2" ], - [ - "CMT_TOP_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_NE2A0_1", - "VBRK_NE2A0" - ], [ "CMT_TOP_WL1END3_1", "VBRK_WL1END3" ], [ - "CMT_TOP_EE2BEG1_1", - "VBRK_EE2BEG1" + "CMT_TOP_NW4A1_1", + "VBRK_NW4A1" + ], + [ + "CMT_TOP_NE4BEG3_1", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_WW4END2_1", + "VBRK_WW4END2" ], [ "CMT_TOP_LH3_1", "VBRK_LH3" ], [ - "CMT_TOP_LH2_1", - "VBRK_LH2" + "CMT_TOP_SE4C3_1", + "VBRK_SE4C3" ], [ - "CMT_TOP_WW4END0_1", - "VBRK_WW4END0" + "CMT_TOP_LH11_1", + "VBRK_LH11" ], [ - "CMT_TOP_WW2END2_1", - "VBRK_WW2END2" + "CMT_TOP_EE4BEG1_1", + "VBRK_EE4BEG1" ], [ - "CMT_TOP_SW4END1_1", - "VBRK_SW4END1" + "CMT_TOP_ER1BEG3_1", + "VBRK_ER1BEG3" ], [ - "CMT_TOP_EE4A1_1", - "VBRK_EE4A1" + "CMT_TOP_WR1END0_1", + "VBRK_WR1END0" ], [ - "CMT_TOP_WW4B0_1", - "VBRK_WW4B0" + "CMT_TOP_WW2END0_1", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_NE4C0_1", + "VBRK_NE4C0" + ], + [ + "CMT_TOP_NW4END3_1", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SE2A2_1", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_WL1END0_1", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_SW2A2_1", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SW4END3_1", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_EE4BEG0_1", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SE2A1_1", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_SW2A1_1", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE4BEG2_1", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_EE4A2_1", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_LH9_1", + "VBRK_LH9" + ], + [ + "CMT_TOP_WW4A1_1", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_ER1BEG2_1", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_LH7_1", + "VBRK_LH7" + ], + [ + "CMT_TOP_NE4BEG0_1", + "VBRK_NE4BEG0" ], [ "CMT_TOP_EL1BEG1_1", "VBRK_EL1BEG1" ], [ - "CMT_TOP_EE4C2_1", - "VBRK_EE4C2" + "CMT_TOP_WW2A3_1", + "VBRK_WW2A3" + ], + [ + "CMT_TOP_NW2A2_1", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_WW2END2_1", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_ER1BEG0_1", + "VBRK_ER1BEG0" + ], + [ + "CMT_TOP_EE2BEG3_1", + "VBRK_EE2BEG3" + ], + [ + "CMT_TOP_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_WW2A1_1", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4END0_1", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_WW4END1_1", + "VBRK_WW4END1" ], [ "CMT_TOP_WW4A0_1", "VBRK_WW4A0" ], [ - "CMT_TOP_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_NE4C2_1", - "VBRK_NE4C2" - ] - ], - "tile_types": [ - "CMT_TOP_L_LOWER_T", - "VBRK" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "MONITOR_IMUX26_0", - "VFRAME_IMUX26" - ], - [ - "MONITOR_BYP0_0", - "VFRAME_BYP0" - ], - [ - "MONITOR_IMUX25_0", - "VFRAME_IMUX25" - ], - [ - "MONITOR_SE2A3_0", - "VFRAME_SE2A3" - ], - [ - "MONITOR_IMUX23_0", - "VFRAME_IMUX23" - ], - [ - "MONITOR_NE4BEG2_0", - "VFRAME_NE4BEG2" - ], - [ - "MONITOR_IMUX10_0", - "VFRAME_IMUX10" - ], - [ - "MONITOR_LH11_0", - "VFRAME_LH11" - ], - [ - "MONITOR_LH7_0", - "VFRAME_LH7" - ], - [ - "MONITOR_SE4C2_0", - "VFRAME_SE4C2" - ], - [ - "MONITOR_EE2BEG3_0", - "VFRAME_EE2BEG3" - ], - [ - "MONITOR_WW4B2_0", - "VFRAME_WW4B2" - ], - [ - "MONITOR_WW2A2_0", - "VFRAME_WW2A2" - ], - [ - "MONITOR_LH9_0", - "VFRAME_LH9" - ], - [ - "MONITOR_IMUX1_0", - "VFRAME_IMUX1" - ], - [ - "MONITOR_IMUX11_0", - "VFRAME_IMUX11" - ], - [ - "MONITOR_WL1END3_0", - "VFRAME_WL1END3" - ], - [ - "MONITOR_EE4C2_0", - "VFRAME_EE4C2" - ], - [ - "MONITOR_WW4END2_0", - "VFRAME_WW4END2" - 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], - [ - "MONITOR_CLK0_0", - "VFRAME_CLK0" - ], - [ - "MONITOR_EE2BEG0_0", - "VFRAME_EE2BEG0" - ], - [ - "MONITOR_SE4C3_0", - "VFRAME_SE4C3" - ], - [ - "MONITOR_WW2END0_0", - "VFRAME_WW2END0" - ], - [ - "MONITOR_WW2END1_0", - "VFRAME_WW2END1" - ], - [ - "MONITOR_IMUX32_0", - "VFRAME_IMUX32" - ], - [ - "MONITOR_IMUX16_0", - "VFRAME_IMUX16" - ], - [ - "MONITOR_EE4A2_0", - "VFRAME_EE4A2" - ], - [ - "MONITOR_LH1_0", - "VFRAME_LH1" - ], - [ - "MONITOR_NE4BEG3_0", - "VFRAME_NE4BEG3" - ], - [ - "MONITOR_NE4C3_0", - "VFRAME_NE4C3" - ], - [ - "MONITOR_CTRL0_0", - "VFRAME_CTRL0" - ], - [ - "MONITOR_IMUX18_0", - "VFRAME_IMUX18" - ], - [ - "MONITOR_NW2A2_0", - "VFRAME_NW2A2" - ], - [ - "MONITOR_LH2_0", - "VFRAME_LH2" - ], - [ - "MONITOR_EE2A2_0", - "VFRAME_EE2A2" - ], - [ - "MONITOR_IMUX3_0", - "VFRAME_IMUX3" - ], - [ - "MONITOR_IMUX44_0", - "VFRAME_IMUX44" - ], - [ - "MONITOR_IMUX4_0", - "VFRAME_IMUX4" - ], - [ - "MONITOR_NW4END1_0", - "VFRAME_NW4END1" - ], - [ - "MONITOR_WW4B3_0", - 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"VBRK_EL1BEG0" - ], - [ - "BRAM_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "BRAM_SW4A2_3", - "VBRK_SW4A2" - ], - [ - "BRAM_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "BRAM_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "BRAM_EE4B3_3", - "VBRK_EE4B3" - ], - [ - "BRAM_EE2BEG1_3", - "VBRK_EE2BEG1" - ], - [ - "BRAM_LH4_3", - "VBRK_LH4" - ], - [ - "BRAM_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "BRAM_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "BRAM_EE4A0_3", - "VBRK_EE4A0" - ], - [ - "BRAM_NW4END0_3", - "VBRK_NW4END0" - ], - [ - "BRAM_WW2END2_3", - "VBRK_WW2END2" - ], - [ - "BRAM_EE4A1_3", - "VBRK_EE4A1" - ], - [ - "BRAM_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "BRAM_NW4A1_3", - "VBRK_NW4A1" - ], - [ - "BRAM_SE4BEG3_3", - "VBRK_SE4BEG3" - ], - [ - "BRAM_MONITOR_N_3", - "VBRK_MONITOR_N" - ], - [ - "BRAM_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "BRAM_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "BRAM_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "BRAM_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "BRAM_WW2END1_3", - "VBRK_WW2END1" - ], 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"VBRK_EE2BEG3" - ], - [ - "BRAM_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "BRAM_WW2END0_3", - "VBRK_WW2END0" - ], - [ - "BRAM_SW2A0_3", + "CMT_TOP_SW2A0_1", "VBRK_SW2A0" ], [ - "BRAM_WL1END2_3", - "VBRK_WL1END2" - ], - [ - "BRAM_NW4END3_3", - "VBRK_NW4END3" - ], - [ - "BRAM_LH8_3", - "VBRK_LH8" - ], - [ - "BRAM_NW4END2_3", - "VBRK_NW4END2" - ], - [ - "BRAM_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "BRAM_NE4C2_3", - "VBRK_NE4C2" - ], - [ - "BRAM_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "BRAM_SE4C2_3", - "VBRK_SE4C2" - ], - [ - "BRAM_WW4B1_3", - "VBRK_WW4B1" - ], - [ - "BRAM_WW4END0_3", - "VBRK_WW4END0" - ], - [ - "BRAM_SE2A0_3", - "VBRK_SE2A0" - ], - [ - "BRAM_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "BRAM_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "BRAM_NE4BEG0_3", - "VBRK_NE4BEG0" - ], - [ - "BRAM_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "BRAM_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "BRAM_EE4B0_3", - "VBRK_EE4B0" - ], - [ - "BRAM_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "BRAM_SE4BEG2_3", - "VBRK_SE4BEG2" - ], - [ - "BRAM_MONITOR_P_3", - "VBRK_MONITOR_P" - ], - [ - "BRAM_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "BRAM_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "BRAM_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - "BRAM_LH7_3", - "VBRK_LH7" - ], - [ - "BRAM_WW4B2_3", - "VBRK_WW4B2" - ], - [ - "BRAM_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "BRAM_NW2A3_3", - "VBRK_NW2A3" - ], - [ - "BRAM_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "BRAM_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "BRAM_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "BRAM_NE4C0_3", - "VBRK_NE4C0" - ], - [ - "BRAM_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "BRAM_NE2A1_3", - "VBRK_NE2A1" - ], - [ - "BRAM_EE4C2_3", - "VBRK_EE4C2" - ], - [ - "BRAM_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "BRAM_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "BRAM_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "BRAM_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "BRAM_WW4A2_3", - "VBRK_WW4A2" - ], - [ - "BRAM_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "BRAM_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "BRAM_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "BRAM_LH6_3", - "VBRK_LH6" - ], - [ - "BRAM_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "BRAM_EE2A0_3", - "VBRK_EE2A0" - ], - [ - "BRAM_SW2A3_3", - "VBRK_SW2A3" - ], - [ - "BRAM_SE4BEG1_3", - "VBRK_SE4BEG1" - ], - [ - "BRAM_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "BRAM_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "BRAM_NW4A3_3", - "VBRK_NW4A3" - ], - [ - "BRAM_NW2A1_3", - "VBRK_NW2A1" - ], - [ - "BRAM_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "BRAM_WR1END2_3", - "VBRK_WR1END2" - ], - [ - "BRAM_EE4A2_3", - "VBRK_EE4A2" - ], - [ - "BRAM_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "BRAM_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "BRAM_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "BRAM_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "BRAM_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "BRAM_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "BRAM_WW2A0_3", - "VBRK_WW2A0" - ], - [ - "BRAM_SE2A3_3", + "CMT_TOP_SE2A3_1", "VBRK_SE2A3" ], [ - "BRAM_LH11_3", - "VBRK_LH11" + "CMT_TOP_WW4B3_1", + "VBRK_WW4B3" ], [ - "BRAM_EL1BEG3_3", - "VBRK_EL1BEG3" + "CMT_TOP_LH12_1", + "VBRK_LH12" ], [ - "BRAM_NE2A3_3", - "VBRK_NE2A3" + "CMT_TOP_NW4END2_1", + "VBRK_NW4END2" ], [ - "BRAM_LH9_3", - "VBRK_LH9" + "CMT_TOP_WR1END2_1", + "VBRK_WR1END2" ], [ - "BRAM_LH3_3", - "VBRK_LH3" + "CMT_TOP_NE2A0_1", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_SE4C0_1", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_SW4A1_1", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_EL1BEG2_1", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_WW4END3_1", + "VBRK_WW4END3" ] - ], - "tile_types": [ - "BRAM_L", - "VBRK" - ], - "grid_deltas": [ - -1, - -3 ] }, { - "wire_pairs": [ - [ - "CLBLL_L_COUT_N", - "HCLK_CLB_COUT1_L" - ], - [ - "CLBLL_LL_COUT_N", - "HCLK_CLB_COUT0_L" - ] - ], - "tile_types": [ - "CLBLL_L", - "HCLK_CLB" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_CK_IN8" - ], - [ - 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- [ - "CMT_PMV_NW4END3", - "INT_INTERFACE_NW4END3" - ], - [ - "CMT_PMV_SE4C2", - "INT_INTERFACE_SE4C2" - ], - [ - "CMT_PMV_ER1BEG0", - "INT_INTERFACE_ER1BEG0" - ] - ], - "tile_types": [ - "CMT_PMV", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "BRAM_CASCOUT_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "BRAM_CASCOUT_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU10", - "BRAM_CASCOUT_ADDRARDADDRU10" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "BRAM_CASCOUT_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU11" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU3", - "BRAM_CASCOUT_ADDRARDADDRU3" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU13", - "BRAM_CASCOUT_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU0", - "BRAM_CASCOUT_ADDRARDADDRU0" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "BRAM_CASCOUT_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU2", - "BRAM_CASCOUT_ADDRARDADDRU2" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU1", - "BRAM_CASCOUT_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "BRAM_CASCOUT_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "BRAM_CASCOUT_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU14", - "BRAM_CASCOUT_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU10", - "BRAM_CASCOUT_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU8", - "BRAM_CASCOUT_ADDRARDADDRU8" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU12", - "BRAM_CASCOUT_ADDRARDADDRU12" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "BRAM_CASCOUT_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU6", - "BRAM_CASCOUT_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "BRAM_CASCOUT_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRARDADDRU7" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "BRAM_CASCOUT_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU5", - "BRAM_CASCOUT_ADDRARDADDRU5" - ], - [ - "BRAM_FIFO36_CASCADEINB", - "BRAM_FIFO36_CASCADEOUTB_1" - ], - [ - "BRAM_FIFO36_CASCADEINA", - "BRAM_FIFO36_CASCADEOUTA_1" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU4", - "BRAM_CASCOUT_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "BRAM_CASCOUT_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "BRAM_CASCOUT_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRARDADDRU9" - ] - ], "tile_types": [ "BRAM_L", "BRAM_L" ], "grid_deltas": [ 0, - 5 + -5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRARDADDRU0", + "BRAM_CASCOUT_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU7", + "BRAM_CASCOUT_ADDRARDADDRU7" + ], + [ + "BRAM_PMVBRAM_O", + "BRAM_PMVBRAM_O_1" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU11", + "BRAM_CASCOUT_ADDRARDADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "BRAM_CASCOUT_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU8", + "BRAM_CASCOUT_ADDRBWRADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "BRAM_CASCOUT_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU10", + "BRAM_CASCOUT_ADDRARDADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU13", + "BRAM_CASCOUT_ADDRARDADDRU13" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU3", + "BRAM_CASCOUT_ADDRBWRADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "BRAM_CASCOUT_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "BRAM_CASCOUT_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU10", + "BRAM_CASCOUT_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "BRAM_CASCOUT_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU9", + "BRAM_CASCOUT_ADDRARDADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU4", + "BRAM_CASCOUT_ADDRARDADDRU4" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU11", + "BRAM_CASCOUT_ADDRBWRADDRU11" + ], + [ + "BRAM_PMVBRAM_ODIV2", + "BRAM_PMVBRAM_ODIV2_1" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU12", + "BRAM_CASCOUT_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "BRAM_CASCOUT_ADDRBWRADDRU1" + ], + [ + "BRAM_PMVBRAM_O_1", + "BRAM_PMVBRAM_O_2" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU0", + "BRAM_CASCOUT_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU5", + "BRAM_CASCOUT_ADDRARDADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "BRAM_CASCOUT_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU1", + "BRAM_CASCOUT_ADDRARDADDRU1" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU3", + "BRAM_CASCOUT_ADDRARDADDRU3" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU12", + "BRAM_CASCOUT_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU2", + "BRAM_CASCOUT_ADDRARDADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU6", + "BRAM_CASCOUT_ADDRARDADDRU6" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU14", + "BRAM_CASCOUT_ADDRARDADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU14", + "BRAM_CASCOUT_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU8", + "BRAM_CASCOUT_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "BRAM_CASCOUT_ADDRBWRADDRU9" + ] ] }, { + "tile_types": [ + "GTP_CHANNEL_3", + "VBRK_EXT" + ], + "grid_deltas": [ + -1, + 2 + ], "wire_pairs": [ [ - "HCLK_IOI_LEAF_GCLK_BOT4", - "IOI_LEAF_GCLK4" + "GTPE2_IMUX13_3", + "VBRK_EXT_IMUX13" ], [ - "HCLK_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3" + "GTPE2_FAN1_3", + "VBRK_EXT_FAN1" ], [ - "HCLK_IOI_RCLK2IO0", - "IOI_RCLK_FORIO0" + "GTPE2_LOGIC_OUTS_B17_3", + "VBRK_EXT_LOGIC_OUTS_B17" ], [ - "HCLK_IOI_I2IOCLK_BOT1", - "RIOI_I2GCLK_TOP0" + "GTPE2_IMUX9_3", + "VBRK_EXT_IMUX9" ], [ - "HCLK_IOI_I2IOCLK_BOT0", - "RIOI_I2GCLK_BOT1" + "GTPE2_IMUX7_3", + "VBRK_EXT_IMUX7" ], [ - "HCLK_IOI_LEAF_GCLK_BOT0", - "IOI_LEAF_GCLK0" + "GTPE2_CLK1_3", + "VBRK_EXT_CLK1" ], [ - "HCLK_IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RDY" + "GTPE2_IMUX30_3", + "VBRK_EXT_IMUX30" ], [ - "HCLK_IOI_IOCLK1", - "IOI_IOCLK1" + "GTPE2_BYP3_3", + "VBRK_EXT_BYP3" ], [ - "HCLK_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2" + "GTPE2_LOGIC_OUTS_B22_3", + "VBRK_EXT_LOGIC_OUTS_B22" ], [ - "HCLK_IOI_RCLK_IMUX2", - "IOI_IMUX_RC2" + "GTPE2_IMUX5_3", + "VBRK_EXT_IMUX5" ], [ - "HCLK_IOI_RCLK2IO3", - "IOI_RCLK_FORIO3" + "GTPE2_BYP6_3", + "VBRK_EXT_BYP6" ], [ - "HCLK_IOI_LEAF_GCLK_BOT5", - "IOI_LEAF_GCLK5" + "GTPE2_LOGIC_OUTS_B5_3", + "VBRK_EXT_LOGIC_OUTS_B5" ], [ - "HCLK_IOI_IOCLK0", - "IOI_IOCLK0" + "GTPE2_FAN0_3", + "VBRK_EXT_FAN0" ], [ - "HCLK_IOI_RCLK2IO2", - "IOI_RCLK_FORIO2" + "GTPE2_IMUX37_3", + "VBRK_EXT_IMUX37" ], [ - "HCLK_IOI_LEAF_GCLK_BOT2", - "IOI_LEAF_GCLK2" + "GTPE2_IMUX39_3", + "VBRK_EXT_IMUX39" ], [ - "HCLK_IOI_IOCLK2", - "IOI_IOCLK2" + "GTPE2_BYP1_3", + "VBRK_EXT_BYP1" ], [ - "HCLK_RCLK_DIV_CLR3", - "IOI_RCLK_DIV_CLR3" + "GTPE2_IMUX6_3", + "VBRK_EXT_IMUX6" ], [ - "HCLK_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR2" + "GTPE2_LOGIC_OUTS_B4_3", + "VBRK_EXT_LOGIC_OUTS_B4" ], [ - "HCLK_IOI_LEAF_GCLK_BOT1", - "IOI_LEAF_GCLK1" + "GTPE2_LOGIC_OUTS_B7_3", + "VBRK_EXT_LOGIC_OUTS_B7" ], [ - "HCLK_IOI_IOCLK3", - "IOI_IOCLK3" + "GTPE2_IMUX35_3", + "VBRK_EXT_IMUX35" ], [ - "HCLK_IOI_LEAF_GCLK_BOT3", - "IOI_LEAF_GCLK3" + "GTPE2_LOGIC_OUTS_B13_3", + "VBRK_EXT_LOGIC_OUTS_B13" ], [ - "HCLK_IOI_RCLK_IMUX3", - "IOI_IMUX_RC3" + "GTPE2_FAN7_3", + "VBRK_EXT_FAN7" ], [ - "HCLK_IOI_RCLK2IO1", - "IOI_RCLK_FORIO1" + "GTPE2_IMUX19_3", + "VBRK_EXT_IMUX19" ], [ - "HCLK_IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN1" + "GTPE2_IMUX29_3", + "VBRK_EXT_IMUX29" ], [ - "HCLK_IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_OUTN65" + "GTPE2_IMUX41_3", + "VBRK_EXT_IMUX41" + ], + [ + "GTPE2_IMUX31_3", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_IMUX27_3", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_CLK0_3", + "VBRK_EXT_CLK0" + ], + [ + "GTPE2_IMUX26_3", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX18_3", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX32_3", + "VBRK_EXT_IMUX32" + ], + [ + "GTPE2_FAN5_3", + "VBRK_EXT_FAN5" + ], + [ + "GTPE2_IMUX16_3", + "VBRK_EXT_IMUX16" + ], + [ + "GTPE2_FAN4_3", + "VBRK_EXT_FAN4" + ], + [ + "GTPE2_LOGIC_OUTS_B14_3", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTPE2_CTRL0_3", + "VBRK_EXT_CTRL0" + ], + [ + "GTPE2_BYP7_3", + "VBRK_EXT_BYP7" + ], + [ + "GTPE2_IMUX15_3", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX10_3", + "VBRK_EXT_IMUX10" + ], + [ + "GTPE2_IMUX0_3", + "VBRK_EXT_IMUX0" + ], + [ + "GTPE2_IMUX45_3", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_FAN2_3", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_IMUX47_3", + "VBRK_EXT_IMUX47" + ], + [ + "GTPE2_LOGIC_OUTS_B9_3", + "VBRK_EXT_LOGIC_OUTS_B9" + ], + [ + "GTPE2_IMUX17_3", + "VBRK_EXT_IMUX17" + ], + [ + "GTPE2_IMUX4_3", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_LOGIC_OUTS_B12_3", + "VBRK_EXT_LOGIC_OUTS_B12" + ], + [ + "GTPE2_IMUX20_3", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_IMUX1_3", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX33_3", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_LOGIC_OUTS_B18_3", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTPE2_IMUX14_3", + "VBRK_EXT_IMUX14" + ], + [ + "GTPE2_LOGIC_OUTS_B1_3", + "VBRK_EXT_LOGIC_OUTS_B1" + ], + [ + "GTPE2_IMUX36_3", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_IMUX46_3", + "VBRK_EXT_IMUX46" + ], + [ + "GTPE2_IMUX44_3", + "VBRK_EXT_IMUX44" + ], + [ + "GTPE2_IMUX24_3", + "VBRK_EXT_IMUX24" + ], + [ + "GTPE2_IMUX8_3", + "VBRK_EXT_IMUX8" + ], + [ + "GTPE2_IMUX2_3", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_BYP0_3", + "VBRK_EXT_BYP0" + ], + [ + "GTPE2_BYP2_3", + "VBRK_EXT_BYP2" + ], + [ + "GTPE2_IMUX12_3", + "VBRK_EXT_IMUX12" + ], + [ + "GTPE2_IMUX38_3", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX34_3", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_IMUX25_3", + "VBRK_EXT_IMUX25" + ], + [ + "GTPE2_IMUX28_3", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_LOGIC_OUTS_B0_3", + "VBRK_EXT_LOGIC_OUTS_B0" + ], + [ + "GTPE2_FAN3_3", + "VBRK_EXT_FAN3" + ], + [ + "GTPE2_BYP4_3", + "VBRK_EXT_BYP4" + ], + [ + "GTPE2_IMUX3_3", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_LOGIC_OUTS_B3_3", + "VBRK_EXT_LOGIC_OUTS_B3" + ], + [ + "GTPE2_CTRL1_3", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_LOGIC_OUTS_B10_3", + "VBRK_EXT_LOGIC_OUTS_B10" + ], + [ + "GTPE2_BYP5_3", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_LOGIC_OUTS_B15_3", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTPE2_FAN6_3", + "VBRK_EXT_FAN6" + ], + [ + "GTPE2_IMUX21_3", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX22_3", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX23_3", + "VBRK_EXT_IMUX23" + ], + [ + "GTPE2_IMUX43_3", + "VBRK_EXT_IMUX43" + ], + [ + "GTPE2_LOGIC_OUTS_B16_3", + "VBRK_EXT_LOGIC_OUTS_B16" + ], + [ + "GTPE2_IMUX40_3", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_IMUX11_3", + "VBRK_EXT_IMUX11" + ], + [ + "GTPE2_IMUX42_3", + "VBRK_EXT_IMUX42" + ], + [ + "GTPE2_LOGIC_OUTS_B19_3", + "VBRK_EXT_LOGIC_OUTS_B19" ] - ], + ] + }, + { "tile_types": [ - "HCLK_IOI3", - "RIOI3" + "HCLK_L", + "INT_L" ], "grid_deltas": [ 0, - 2 + -1 + ], + "wire_pairs": [ + [ + "HCLK_BYP_BOUNCE7", + "BYP_BOUNCE_N3_7" + ], + [ + "HCLK_SW6D3", + "SW6C3" + ], + [ + "HCLK_NN6C1", + "NN6D1" + ], + [ + "HCLK_LEAF_CLK_B_TOPL3", + "GCLK_L_B9" + ], + [ + "HCLK_LV8", + "LV_L9" + ], + [ + "HCLK_NN6E0", + "NN6END0" + ], + [ + "HCLK_SS2A3", + "SS2A3" + ], + [ + "HCLK_NN6A3", + "NN6B3" + ], + [ + "HCLK_FAN_BOUNCE_S3_2", + "FAN_BOUNCE2" + ], + [ + "HCLK_EL1BEG3", + "EL1BEG_N3" + ], + [ + "HCLK_NN6D3", + "NN6E3" + ], + [ + "HCLK_WL1BEG3", + "WL1BEG_N3" + ], + [ + "HCLK_LV5", + "LV_L6" + ], + [ + "HCLK_SS6A1", + "SS6BEG1" + ], + [ + "HCLK_NE6D0", + "NE6E0" + ], + [ + "HCLK_LVB5", + "LVB_L5" + ], + [ + "HCLK_SS2END2", + "SS2A2" + ], + [ + "HCLK_EL1END_S3_0", + "EL1END0" + ], + [ + "HCLK_SR1END_N3_3", + "SR1END_N3_3" + ], + [ + "HCLK_LVB8", + "LVB_L8" + ], + [ + "HCLK_SS6B0", + "SS6A0" + ], + [ + "HCLK_NN2A0", + "NN2END0" + ], + [ + "HCLK_LVB7", + "LVB_L7" + ], + [ + "HCLK_NN6BEG2", + "NN6A2" + ], + [ + "HCLK_NR1BEG0", + "NR1END0" + ], + [ + "HCLK_NE2BEG1", + "NE2A1" + ], + [ + "HCLK_WR1BEG_S0", + "WR1BEG0" + ], + [ + "HCLK_NN6B0", + "NN6C0" + ], + [ + "HCLK_NE6C3", + "NE6D3" + ], + [ + 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-3 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLK_FEED_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLK_FEED_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLK_FEED_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLK_FEED_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLK_FEED_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_LH3", - "VBRK_LH3" - ], - [ - "CLK_FEED_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_SW2A2", - "VBRK_SW2A2" - ], - [ - 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- "VBRK_WL1END1" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLK_FEED_LH12", - "VBRK_LH12" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_NE2A2", - "VBRK_NE2A2" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_WW4C2", - "VBRK_WW4C2" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLK_FEED_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLK_FEED_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLK_FEED_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLK_FEED_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLK_FEED_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLK_FEED_LH2", - "VBRK_LH2" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLK_FEED_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_EE4B1", - "VBRK_EE4B1" - ], - [ - "CLK_FEED_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLK_FEED_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLK_FEED_LH7", - "VBRK_LH7" - ], - [ - "CLK_FEED_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLK_FEED_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLK_FEED_EE4BEG2", - "VBRK_EE4BEG2" - ] - ], - "tile_types": [ - "CLK_PMV2_SVT", - "VBRK" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "GTPE2_IMUX17_5", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_CTRL0_5", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_IMUX5_5", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX41_5", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX19_5", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX36_5", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_FAN1_5", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX35_5", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX14_5", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_BYP6_5", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX18_5", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX30_5", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX27_5", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX32_5", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_LOGIC_OUTS_B5_5", - "VBRK_EXT_LOGIC_OUTS_B5" - ], - [ - "GTPE2_LOGIC_OUTS_B15_5", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_CLK1_5", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX23_5", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_FAN6_5", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_BYP0_5", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_LOGIC_OUTS_B0_5", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_BYP3_5", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX2_5", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX46_5", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX6_5", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_LOGIC_OUTS_B6_5", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX43_5", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX44_5", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_LOGIC_OUTS_B13_5", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX25_5", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_LOGIC_OUTS_B2_5", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_BYP2_5", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX24_5", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_IMUX9_5", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX37_5", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_FAN5_5", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_IMUX3_5", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_CLK0_5", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_LOGIC_OUTS_B17_5", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX28_5", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX34_5", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX15_5", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_FAN4_5", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX26_5", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_FAN2_5", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX12_5", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX38_5", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX13_5", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_LOGIC_OUTS_B21_5", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_IMUX16_5", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_LOGIC_OUTS_B14_5", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_LOGIC_OUTS_B12_5", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_IMUX7_5", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_LOGIC_OUTS_B22_5", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX22_5", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX29_5", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX42_5", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_LOGIC_OUTS_B23_5", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_BYP1_5", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX33_5", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_BYP7_5", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_LOGIC_OUTS_B7_5", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX10_5", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_LOGIC_OUTS_B10_5", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_LOGIC_OUTS_B4_5", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_LOGIC_OUTS_B1_5", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX39_5", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX11_5", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_BYP4_5", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX21_5", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX4_5", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX20_5", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX8_5", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX1_5", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_FAN0_5", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX31_5", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX45_5", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX40_5", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_LOGIC_OUTS_B3_5", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_BYP5_5", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_LOGIC_OUTS_B9_5", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX47_5", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_CTRL1_5", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_FAN7_5", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX0_5", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_FAN3_5", - "VBRK_EXT_FAN3" - ] - ], - "tile_types": [ - "GTP_CHANNEL_1", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_LH1_1", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_LH6_1", - "VBRK_LH6" - ], - [ - "CLK_HROW_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_LH10_1", - "VBRK_LH10" - ], - [ - "CLK_HROW_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_LH4_1", - "VBRK_LH4" - ], - [ - "CLK_HROW_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_LH9_1", - "VBRK_LH9" - ], - [ - "CLK_HROW_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_HROW_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_HROW_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_HROW_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW4A3_1", - "VBRK_WW4A3" - ] - ], - "tile_types": [ - "CLK_BUFG_BOT_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "DSP_0_ACIN0", - "HCLK_DSP_ACIN0" - ], - [ - "DSP_0_ACIN14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_0_ACIN17", - "HCLK_DSP_ACIN17" - ], - [ - "DSP_0_PCIN19", - "HCLK_DSP_PCIN19" - ], - [ - "DSP_0_PCIN31", - "HCLK_DSP_PCIN31" - ], - [ - "DSP_0_BCIN1", - "HCLK_DSP_BCIN1" - ], - [ - "DSP_0_ACIN23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_0_PCIN44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_0_BCIN13", - "HCLK_DSP_BCIN13" - ], - [ - "DSP_0_ACIN13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_0_PCIN30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_0_PCIN0", - "HCLK_DSP_PCIN0" - ], - [ - "DSP_0_PCIN38", - "HCLK_DSP_PCIN38" - ], - [ - "DSP_0_BCIN5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_0_PCIN33", - "HCLK_DSP_PCIN33" - ], - [ - "DSP_0_PCIN17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_0_BCIN7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_0_PCIN10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_0_BCIN9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_0_ACIN21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_0_BCIN6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_0_BCIN8", - "HCLK_DSP_BCIN8" - ], - [ - "DSP_0_PCIN36", - "HCLK_DSP_PCIN36" - ], - [ - "DSP_0_PCIN37", - "HCLK_DSP_PCIN37" - ], - [ - "DSP_0_ACIN4", - "HCLK_DSP_ACIN4" - ], - [ - "DSP_0_PCIN16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_0_ACIN18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_0_ACIN12", - "HCLK_DSP_ACIN12" - ], - [ - "DSP_0_PCIN8", - "HCLK_DSP_PCIN8" - ], - [ - "DSP_0_ACIN27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_0_PCIN21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_0_ACIN25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_0_BCIN4", - "HCLK_DSP_BCIN4" - ], - [ - "DSP_0_ACIN5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_0_PCIN42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_0_ACIN3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_0_ACIN8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_0_ACIN26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_0_BCIN15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_0_PCIN15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_0_PCIN7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_0_BCIN17", - "HCLK_DSP_BCIN17" - ], - [ - "DSP_0_PCIN39", - "HCLK_DSP_PCIN39" - ], - [ - "DSP_0_ACIN10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_0_ACIN6", - "HCLK_DSP_ACIN6" - ], - [ - "DSP_0_BCIN10", - "HCLK_DSP_BCIN10" - ], - [ - "DSP_0_PCIN27", - "HCLK_DSP_PCIN27" - ], - [ - "DSP_0_PCIN22", - "HCLK_DSP_PCIN22" - ], - [ - "DSP_0_ACIN9", - "HCLK_DSP_ACIN9" - ], - [ - "DSP_0_PCIN18", - "HCLK_DSP_PCIN18" - ], - [ - "DSP_0_PCIN24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_0_PCIN13", - "HCLK_DSP_PCIN13" - ], - [ - "DSP_0_PCIN41", - "HCLK_DSP_PCIN41" - ], - [ - "DSP_0_PCIN2", - "HCLK_DSP_PCIN2" - ], - [ - "DSP_0_PCIN12", - "HCLK_DSP_PCIN12" - ], - [ - "DSP_0_ACIN24", - "HCLK_DSP_ACIN24" - ], - [ - "DSP_0_ACIN29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_0_ACIN20", - "HCLK_DSP_ACIN20" - ], - [ - "DSP_0_CARRYCASCIN", - "HCLK_DSP_CARRYCASCIN" - ], - [ - "DSP_0_ACIN1", - "HCLK_DSP_ACIN1" - ], - [ - "DSP_0_PCIN35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_0_PCIN20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_0_PCIN32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_0_PCIN40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_0_ACIN2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_0_ACIN22", - "HCLK_DSP_ACIN22" - ], - [ - "DSP_0_MULTSIGNIN", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_0_PCIN23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_0_BCIN2", - "HCLK_DSP_BCIN2" - ], - [ - "DSP_0_PCIN28", - "HCLK_DSP_PCIN28" - ], - [ - "DSP_0_PCIN11", - "HCLK_DSP_PCIN11" - ], - [ - "DSP_0_BCIN11", - "HCLK_DSP_BCIN11" - ], - [ - "DSP_0_ACIN28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_0_BCIN14", - "HCLK_DSP_BCIN14" - ], - [ - "DSP_0_ACIN16", - "HCLK_DSP_ACIN16" - ], - [ - "DSP_0_PCIN43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_0_PCIN34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_0_PCIN47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_0_PCIN25", - "HCLK_DSP_PCIN25" - ], - [ - "DSP_0_PCIN9", - "HCLK_DSP_PCIN9" - ], - [ - "DSP_0_BCIN12", - "HCLK_DSP_BCIN12" - ], - [ - "DSP_0_BCIN3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_0_ACIN7", - "HCLK_DSP_ACIN7" - ], - [ - "DSP_0_PCIN29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_0_BCIN16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_0_PCIN5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_0_BCIN0", - "HCLK_DSP_BCIN0" - ], - [ - "DSP_0_PCIN45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_0_PCIN1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_0_PCIN4", - "HCLK_DSP_PCIN4" - ], - [ - "DSP_0_ACIN19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_0_ACIN11", - "HCLK_DSP_ACIN11" - ], - [ - "DSP_0_PCIN6", - "HCLK_DSP_PCIN6" - ], - [ - "DSP_0_ACIN15", - "HCLK_DSP_ACIN15" - ], - [ - "DSP_0_PCIN26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_0_PCIN3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_0_PCIN46", - "HCLK_DSP_PCIN46" - ], - [ - "DSP_0_PCIN14", - "HCLK_DSP_PCIN14" - ] - ], - "tile_types": [ - "DSP_L", - "HCLK_DSP_L" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH7_3", - "VBRK_LH7" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_LH6_3", - "VBRK_LH6" - ], - [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_MONITOR_N_3", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_LH4_3", - "VBRK_LH4" - ], - [ - "CLK_HROW_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH5_3", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_NE4C1_3", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW2A2_3", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW4B0_3", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SW2A3_3", - "VBRK_SW2A3" - ], - [ - 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"GTPE2_IMUX39_0", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX32_0", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX18_0", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_BYP2_0", - "VBRK_EXT_BYP2" - ] - ], - "tile_types": [ - "GTP_COMMON", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "BRKH_CLK_R_CK_GCLK8", - "CLK_BUFG_CK_GCLK8" - ], - [ - "BRKH_CLK_R_CK_GCLK27", - "CLK_BUFG_CK_GCLK27" - ], - [ - "BRKH_CLK_R_CK_GCLK29", - "CLK_BUFG_CK_GCLK29" - ], - [ - "BRKH_CLK_R_CK_GCLK2", - "CLK_BUFG_CK_GCLK2" - ], - [ - "BRKH_CLK_R_CK_GCLK21", - "CLK_BUFG_CK_GCLK21" - ], - [ - "BRKH_CLK_R_CK_GCLK20", - "CLK_BUFG_CK_GCLK20" - ], - [ - "BRKH_CLK_R_CK_GCLK18", - "CLK_BUFG_CK_GCLK18" - ], - [ - "BRKH_CLK_R_CK_GCLK25", - "CLK_BUFG_CK_GCLK25" - ], - [ - "BRKH_CLK_R_CK_GCLK24", - "CLK_BUFG_CK_GCLK24" - ], - [ - "BRKH_CLK_R_CK_GCLK16", - "CLK_BUFG_CK_GCLK16" - ], - [ - "BRKH_CLK_R_CK_GCLK13", - "CLK_BUFG_CK_GCLK13" - ], - [ - "BRKH_CLK_R_CK_GCLK31", - "CLK_BUFG_CK_GCLK31" - ], - [ - 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"CLK_BUFG_CK_GCLK15" - ], - [ - "BRKH_CLK_R_CK_GCLK6", - "CLK_BUFG_CK_GCLK6" - ], - [ - "BRKH_CLK_R_CK_GCLK7", - "CLK_BUFG_CK_GCLK7" - ] - ], - "tile_types": [ - "BRKH_CLK", - "CLK_BUFG_BOT_R" - ], - "grid_deltas": [ - 0, - 4 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_WW2A3_6", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_NE2A1_6", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_WW4C0_6", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_LH4_6", - "VBRK_LH4" - ], - [ - "CMT_TOP_WW4B0_6", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_NW4END0_6", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_SE2A3_6", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_NW4A3_6", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_NE2A0_6", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_NE4C2_6", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_SE2A0_6", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_EE4A2_6", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_EE4B2_6", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_WL1END1_6", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_WW2A0_6", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_EE2A2_6", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_ER1BEG1_6", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EE4C0_6", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_NE2A2_6", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_WW4END0_6", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_NW2A3_6", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_SW2A1_6", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_WW4C3_6", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_SE4BEG1_6", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_NW4A2_6", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_SW4END3_6", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SE4C0_6", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_WL1END2_6", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_SE4C3_6", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WR1END1_6", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_EL1BEG0_6", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_NE4C0_6", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_NE4BEG0_6", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_WW4C1_6", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_SE4C1_6", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_EE4B1_6", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_LH11_6", - "VBRK_LH11" - ], - [ - "CMT_TOP_SW4END1_6", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_NE4C3_6", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_WR1END2_6", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_EE2A1_6", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_EL1BEG2_6", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_NW4A0_6", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_WW4END3_6", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_NW4END3_6", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_NW2A2_6", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_EL1BEG1_6", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_EL1BEG3_6", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_EE2BEG1_6", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_EE4BEG0_6", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW4B3_6", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_EE4B0_6", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_WW4A0_6", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WW4A1_6", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_EE4BEG2_6", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_WW4B2_6", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_NW2A1_6", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_WW2A2_6", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_WW2END3_6", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_NE4BEG2_6", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_NE4C1_6", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_NE4BEG1_6", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_WW4END1_6", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_NE4BEG3_6", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_EE4C2_6", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_WR1END0_6", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_EE2BEG3_6", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_EE4B3_6", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_WW2A1_6", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_EE4BEG1_6", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_LH6_6", - "VBRK_LH6" - ], - [ - "CMT_TOP_WW4C2_6", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_WL1END0_6", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_WW4A3_6", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_SE4BEG2_6", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_EE4C1_6", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_SW4END2_6", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WW2END0_6", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_NW4A1_6", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_LH7_6", - "VBRK_LH7" - ], - [ - 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"VBRK_SE4C2" - ] - ], - "tile_types": [ - "CMT_TOP_R_LOWER_T", - "VBRK" - ], - "grid_deltas": [ - 1, - -5 - ] - }, - { - "wire_pairs": [ - [ - "PCIE_NE2A0_12", - "INT_INTERFACE_NE2A0" - ], - [ - "PCIE_IMUX0_L_12", - "PCIE_INT_INTERFACE_IMUX_L_OUT0" - ], - [ - "PCIE_IMUX27_L_12", - "PCIE_INT_INTERFACE_IMUX_L_OUT27" - ], - [ - "PCIE_NW4A2_12", - "INT_INTERFACE_NW4A2" - ], - [ - "PCIE_LOGIC_OUTS_B0_L_12", - "INT_INTERFACE_LOGIC_OUTS_L_B0" - ], - [ - "PCIE_WL1END0_12", - "INT_INTERFACE_WL1END0" - ], - [ - "PCIE_LOGIC_OUTS_B8_L_12", - "INT_INTERFACE_LOGIC_OUTS_L_B8" - ], - [ - "PCIE_SE4C3_12", - "INT_INTERFACE_SE4C3" - ], - [ - "PCIE_FAN2_L_12", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_SE4BEG0_12", - "INT_INTERFACE_SE4BEG0" - ], - [ - "PCIE_IMUX5_L_12", - "PCIE_INT_INTERFACE_IMUX_L_OUT5" - ], - [ - "PCIE_IMUX24_L_12", - "PCIE_INT_INTERFACE_IMUX_L_OUT24" - ], - [ - "PCIE_CLK0_L_12", - "INT_INTERFACE_CLK0" - ], - [ - "PCIE_IMUX44_L_12", - "PCIE_INT_INTERFACE_IMUX_L_OUT44" - ], - [ - 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"VBRK_SE4BEG0" - ], - [ - "CMT_TOP_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_LH9_4", - "VBRK_LH9" - ], - [ - "CMT_TOP_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_LH6_4", - "VBRK_LH6" - ], - [ - "CMT_TOP_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_LH3_4", - "VBRK_LH3" - ], - [ - "CMT_TOP_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4B0_4", - "VBRK_WW4B0" - ] - ], - "tile_types": [ - "CMT_TOP_L_LOWER_T", - "VBRK" - ], - "grid_deltas": [ - -1, - -3 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_TERM_R_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_TERM_R_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_TERM_R_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_TERM_R_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_TERM_R_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_TERM_R_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_TERM_R_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_TERM_R_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_TERM_R_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_TERM_R_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_TERM_R_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_TERM_R_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_TERM_R_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_TERM_R_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_TERM_R_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_TERM_R_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_TERM_R_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_TERM_R_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_TERM_R_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_TERM_R_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_TERM_R_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_TERM_R_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_TERM_R_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_TERM_R_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_TERM_R_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_TERM_R_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_TERM_R_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_TERM_R_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_TERM_R_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_TERM_R_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_TERM_R_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_TERM_R_GCLK20" - ] - ], - "tile_types": [ - "CLK_FEED", - "CLK_TERM" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLBLL_WW2END3", - "CLBLM_WW2END3" - ], - [ - "CLBLL_NW2A2", - "CLBLM_NW2A2" - ], - [ - "CLBLL_NW2A1", - "CLBLM_NW2A1" - ], - [ - "CLBLL_EE4C1", - "CLBLM_EE4C1" - ], - [ - "CLBLL_WL1END3", - "CLBLM_WL1END3" - ], - [ - "CLBLL_LH4", - "CLBLM_LH4" - ], - [ - "CLBLL_WW2A0", - "CLBLM_WW2A0" - ], - [ - "CLBLL_WW4A0", - "CLBLM_WW4A0" - ], - [ - "CLBLL_LH6", - "CLBLM_LH6" - ], - [ - "CLBLL_WW2A2", - "CLBLM_WW2A2" - ], - [ - "CLBLL_NW4END1", - "CLBLM_NW4END1" - ], - [ - "CLBLL_MONITOR_P", - "CLBLM_MONITOR_P" - ], - [ - "CLBLL_NW4A1", - "CLBLM_NW4A1" - ], - [ - "CLBLL_SE4BEG0", - "CLBLM_SE4BEG0" - ], - [ - "CLBLL_EL1BEG3", - "CLBLM_EL1BEG3" - ], - [ - "CLBLL_WL1END1", - "CLBLM_WL1END1" - ], - [ - "CLBLL_EL1BEG0", - "CLBLM_EL1BEG0" - ], - [ - "CLBLL_LH1", - "CLBLM_LH1" - ], - [ - "CLBLL_EE4A0", - "CLBLM_EE4A0" - ], - [ - "CLBLL_SW2A2", - "CLBLM_SW2A2" - ], - [ - "CLBLL_SE2A3", - "CLBLM_SE2A3" - ], - [ - "CLBLL_WW2END1", - "CLBLM_WW2END1" - ], - [ - "CLBLL_EE2BEG3", - "CLBLM_EE2BEG3" - ], - [ - "CLBLL_SW4A2", - "CLBLM_SW4A2" - ], - [ - "CLBLL_WW4END2", - "CLBLM_WW4END2" - ], - [ - "CLBLL_NE4C0", - "CLBLM_NE4C0" - ], - [ - "CLBLL_WW4A1", - "CLBLM_WW4A1" - ], - [ - "CLBLL_SE4BEG1", - "CLBLM_SE4BEG1" - ], - [ - "CLBLL_EL1BEG1", - "CLBLM_EL1BEG1" - ], - [ - "CLBLL_WR1END1", - "CLBLM_WR1END1" - ], - [ - "CLBLL_EE2A3", - "CLBLM_EE2A3" - ], - [ - "CLBLL_SE4C3", - "CLBLM_SE4C3" - ], - [ - "CLBLL_LH7", - "CLBLM_LH7" - ], - [ - "CLBLL_EE4B1", - "CLBLM_EE4B1" - ], - [ - "CLBLL_WR1END2", - "CLBLM_WR1END2" - ], - [ - "CLBLL_ER1BEG1", - "CLBLM_ER1BEG1" - ], - [ - "CLBLL_NW4END3", - "CLBLM_NW4END3" - ], - [ - "CLBLL_SW2A3", - "CLBLM_SW2A3" - ], - [ - "CLBLL_EE4A1", - "CLBLM_EE4A1" - ], - [ - "CLBLL_WW4B2", - "CLBLM_WW4B2" - ], - [ - "CLBLL_NE2A1", - "CLBLM_NE2A1" - ], - [ - "CLBLL_WW2A1", - "CLBLM_WW2A1" - ], - [ - "CLBLL_WW2END0", - "CLBLM_WW2END0" - ], - [ - "CLBLL_SE4C2", - "CLBLM_SE4C2" - ], - [ - "CLBLL_EE2BEG1", - "CLBLM_EE2BEG1" - ], - [ - "CLBLL_SW4A3", - "CLBLM_SW4A3" - ], - [ - "CLBLL_WW4B3", - "CLBLM_WW4B3" - ], - [ - "CLBLL_SW4END3", - "CLBLM_SW4END3" - ], - [ - "CLBLL_NE2A2", - "CLBLM_NE2A2" - ], - [ - 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"CLBLM_WR1END0" - ], - [ - "CLBLL_NE4BEG0", - "CLBLM_NE4BEG0" - ], - [ - "CLBLL_LH10", - "CLBLM_LH10" - ], - [ - "CLBLL_EE4B2", - "CLBLM_EE4B2" - ], - [ - "CLBLL_SE2A0", - "CLBLM_SE2A0" - ], - [ - "CLBLL_EE2A1", - "CLBLM_EE2A1" - ], - [ - "CLBLL_NW4END2", - "CLBLM_NW4END2" - ], - [ - "CLBLL_EE4BEG2", - "CLBLM_EE4BEG2" - ], - [ - "CLBLL_WW4C3", - "CLBLM_WW4C3" - ], - [ - "CLBLL_WW4C1", - "CLBLM_WW4C1" - ], - [ - "CLBLL_WW4C2", - "CLBLM_WW4C2" - ], - [ - "CLBLL_EE4B0", - "CLBLM_EE4B0" - ], - [ - "CLBLL_NE2A3", - "CLBLM_NE2A3" - ], - [ - "CLBLL_LH12", - "CLBLM_LH12" - ], - [ - "CLBLL_SW4A1", - "CLBLM_SW4A1" - ], - [ - "CLBLL_WW4A2", - "CLBLM_WW4A2" - ], - [ - "CLBLL_EE2BEG2", - "CLBLM_EE2BEG2" - ], - [ - "CLBLL_NW2A3", - "CLBLM_NW2A3" - ], - [ - "CLBLL_SE4C0", - "CLBLM_SE4C0" - ], - [ - "CLBLL_NE4C3", - "CLBLM_NE4C3" - ], - [ - "CLBLL_EE4BEG3", - "CLBLM_EE4BEG3" - ], - [ - "CLBLL_EE2A0", - "CLBLM_EE2A0" - ], - [ - "CLBLL_LH2", - "CLBLM_LH2" - ], - [ - "CLBLL_NE4BEG1", - "CLBLM_NE4BEG1" - ], - [ - "CLBLL_SW4END2", - "CLBLM_SW4END2" - ], - [ - "CLBLL_WW4END3", - "CLBLM_WW4END3" - ], - [ - "CLBLL_WW4B1", - "CLBLM_WW4B1" - ], - [ - "CLBLL_NE4BEG2", - "CLBLM_NE4BEG2" - ], - [ - "CLBLL_SE2A2", - "CLBLM_SE2A2" - ], - [ - "CLBLL_NE4C2", - "CLBLM_NE4C2" - ], - [ - "CLBLL_EE2A2", - "CLBLM_EE2A2" - ], - [ - "CLBLL_EL1BEG2", - "CLBLM_EL1BEG2" - ], - [ - "CLBLL_WW4A3", - "CLBLM_WW4A3" - ], - [ - "CLBLL_EE4C2", - "CLBLM_EE4C2" - ], - [ - "CLBLL_SE4BEG2", - "CLBLM_SE4BEG2" - ], - [ - "CLBLL_NE4BEG3", - "CLBLM_NE4BEG3" - ], - [ - "CLBLL_EE4BEG0", - "CLBLM_EE4BEG0" - ], - [ - "CLBLL_NW4END0", - "CLBLM_NW4END0" - ], - [ - "CLBLL_ER1BEG3", - "CLBLM_ER1BEG3" - ], - [ - "CLBLL_LH11", - "CLBLM_LH11" - ], - [ - "CLBLL_NW4A2", - "CLBLM_NW4A2" - ], - [ - "CLBLL_SW4END0", - "CLBLM_SW4END0" - ], - [ - "CLBLL_MONITOR_N", - "CLBLM_MONITOR_N" - ], - [ - "CLBLL_WL1END0", - "CLBLM_WL1END0" - ], - [ - "CLBLL_WL1END2", - "CLBLM_WL1END2" - ], - [ - "CLBLL_NW2A0", - "CLBLM_NW2A0" - ], - [ - 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"CLK_HROW_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_HROW_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_HROW_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_LH3_1", - "VBRK_LH3" - ], - [ - "CLK_HROW_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_LH2_1", - "VBRK_LH2" - ], - [ - "CLK_HROW_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_HROW_LH7_1", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_WW4A3_1", - "VBRK_WW4A3" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - 3 - ] - }, - { - "wire_pairs": [ - [ - "CMT_MMCM_PHASERREF_BELOW0", - "CMT_PHASER_DOWN_PHASERREF_BELOW0" - ], - [ - "CMT_MMCM_PHASERA_CTSBUS1", - "CMT_PHASERA_CTSBUS1" - ], - [ - "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", - "CMT_PHASER_OUT_A_OCLK1X_90" - ], - [ - "MMCM_CLK_FREQ_BB_NS0", - "MMCM_CLK_FREQBB_REBUFOUT0" - ], - [ - "CMT_MMCM_PHASERA_DTSBUS1", - "CMT_PHASERA_DTSBUS1" - ], - [ - "CMT_MMCM_PHASERREF0", - "CMT_PHASER_DOWN_PHASERREF0" - ], - [ - "CMT_MMCM_A_WRCLK_TOFIFO", - "CMT_PHASER_IN_A_WRCLK_TOFIFO" - ], - [ - "CMT_MMCM_A_RDEN_TOFIFO", - "CMT_PHASER_OUT_A_RDEN_TOFIFO" - ], - [ - "CMT_MMCM_A_WREN_TOFIFO", - "CMT_PHASER_IN_A_WREN_TOFIFO" - ], - [ - "CMT_MMCM_PHASER_IN_B_ICLK", - "CMT_PHASER_B_TOMMCM_ICLK" - ], - [ - "MMCM_CLK_FREQ_BB_NS1", - "MMCM_CLK_FREQBB_REBUFOUT1" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM2", - "CMT_LR_LOWER_T_CLK_MMCM2" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM0", - "CMT_LR_LOWER_T_CLK_MMCM0" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM5", - "CMT_LR_LOWER_T_CLK_MMCM5" - ], - [ - "CMT_MMCM_PHASERA_CTSBUS0", - "CMT_PHASERA_CTSBUS0" - ], - [ - "MMCMOUT_CLK_FREQ_BB_3", - "MMCMOUT_CLK_FREQ_BB_REBUFIN3" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM3", - "CMT_LR_LOWER_T_CLK_MMCM3" - ], - [ - "MMCM_CLK_FREQ_BB_NS3", - "MMCM_CLK_FREQBB_REBUFOUT3" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM10", - "CMT_LR_LOWER_T_CLK_MMCM10" - ], - [ - "CMT_R_LOWER_B_CLK_PERF3", - "CMT_LR_LOWER_T_CLK_PERF3" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM11", - "CMT_LR_LOWER_T_CLK_MMCM11" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM4", - "CMT_LR_LOWER_T_CLK_MMCM4" - ], - [ - "CMT_MMCM_PHASER_OUT_A_OCLK", - "CMT_PHASER_OUT_A_OCLK" - ], - [ - "CMT_MMCM_PHASER_IN_A_ICLK", - "CMT_PHASER_IN_A_ICLK" - ], - [ - "MMCMOUT_CLK_FREQ_BB_1", - "MMCMOUT_CLK_FREQ_BB_REBUFIN1" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM9", - "CMT_LR_LOWER_T_CLK_MMCM9" - ], - [ - "CMT_R_LOWER_B_CLK_IN3_HCLK", - "CMT_LR_LOWER_T_CLK_IN3_HCLK" - ], - [ - "MMCM_CLK_FREQ_BB_NS2", - "MMCM_CLK_FREQBB_REBUFOUT2" - ], - [ - "CMT_MMCM_A_RDCLK_TOFIFO", - "CMT_PHASER_OUT_A_RDCLK_TOFIFO" - ], - [ - "CMT_MMCM_PHASER_OUT_A_OCLKDIV", - "CMT_PHASER_OUT_A_OCLKDIV" - ], - [ - "CMT_R_LOWER_B_CLK_PERF2", - "CMT_LR_LOWER_T_CLK_PERF2" - ], - [ - "CMT_MMCM_PHYCTRL_SYNC_BB_UP", - "CMT_PHASER_BOT_SYNC_BB" - ], - [ - "CMT_MMCM_PHASERREF_ABOVE1", - "CMT_PHASER_DOWN_PHASERREF_ABOVE1" - ], - [ - "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "CMT_PHASER_B_TOMMCM_ICLKDIV" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM13", - "CMT_LR_LOWER_T_CLK_MMCM13" - ], - [ - "CMT_MMCM_PHASER_OUT_B_OCLK", - "CMT_PHASER_B_TOMMCM_OCLK" - ], - [ - "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "CMT_PHASER_B_TOMMCM_OCLKDIV" - ], - [ - "CMT_MMCM_PHASERA_DTSBUS0", - "CMT_PHASERA_DTSBUS0" - ], - [ - "CMT_MMCM_PHASERA_DQSBUS1", - "CMT_PHASERA_DQSBUS1" - ], - [ - "CMT_MMCM_PHASER_IN_A_ICLKDIV", - "CMT_PHASER_IN_A_ICLKDIV" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM7", - "CMT_LR_LOWER_T_CLK_MMCM7" - ], - [ - "MMCMOUT_CLK_FREQ_BB_2", - "MMCMOUT_CLK_FREQ_BB_REBUFIN2" - ], - [ - "CMT_R_LOWER_B_CLK_PERF0", - "CMT_LR_LOWER_T_CLK_PERF0" - ], - [ - "CMT_R_LOWER_B_CLK_IN2_HCLK", - "CMT_LR_LOWER_T_CLK_IN2_HCLK" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM1", - "CMT_LR_LOWER_T_CLK_MMCM1" - ], - [ - "CMT_MMCM_PHASERA_DQSBUS0", - "CMT_PHASERA_DQSBUS0" - ], - [ - "CMT_MMCM_PHASERREF1", - "CMT_PHASER_DOWN_PHASERREF1" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM6", - "CMT_LR_LOWER_T_CLK_MMCM6" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM12", - "CMT_LR_LOWER_T_CLK_MMCM12" - ], - [ - "CMT_R_LOWER_B_CLK_PERF1", - "CMT_LR_LOWER_T_CLK_PERF1" - ], - [ - "CMT_R_LOWER_B_CLK_MMCM8", - "CMT_LR_LOWER_T_CLK_MMCM8" - ], - [ - "CMT_MMCM_PHASERREF_BELOW1", - "CMT_PHASER_DOWN_PHASERREF_BELOW1" - ], - [ - "CMT_R_LOWER_B_CLK_IN1_HCLK", - "CMT_LR_LOWER_T_CLK_IN1_HCLK" - ], - [ - "MMCMOUT_CLK_FREQ_BB_0", - "MMCMOUT_CLK_FREQ_BB_REBUFIN0" - ], - [ - "CMT_MMCM_PHASERREF_ABOVE0", - "CMT_PHASER_DOWN_PHASERREF_ABOVE0" - ] - ], - "tile_types": [ - "CMT_TOP_R_LOWER_B", - "CMT_TOP_R_LOWER_T" - ], - "grid_deltas": [ - 0, - -9 - ] - }, - { - "wire_pairs": [ - [ - "CLBLL_LL_CIN", - "HCLK_CLB_COUT1_R" - ], - [ - "CLBLL_L_CIN", - "HCLK_CLB_COUT0_R" - ] - ], - "tile_types": [ - "CLBLL_R", - "HCLK_CLB" - ], - "grid_deltas": [ - 0, - 1 - ] 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"BRAM_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "BRAM_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "BRAM_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "BRAM_LH12_4", - "VBRK_LH12" - ], - [ - "BRAM_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "BRAM_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "BRAM_LH6_4", - "VBRK_LH6" - ], - [ - "BRAM_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "BRAM_LH10_4", - "VBRK_LH10" - ], - [ - "BRAM_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "BRAM_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "BRAM_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "BRAM_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "BRAM_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "BRAM_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "BRAM_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "BRAM_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "BRAM_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "BRAM_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "BRAM_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "BRAM_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "BRAM_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "BRAM_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "BRAM_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "BRAM_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "BRAM_LH2_4", - "VBRK_LH2" - ], - [ - "BRAM_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "BRAM_LH4_4", - "VBRK_LH4" - ], - [ - "BRAM_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "BRAM_LH7_4", - "VBRK_LH7" - ], - [ - "BRAM_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "BRAM_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "BRAM_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "BRAM_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "BRAM_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "BRAM_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "BRAM_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "BRAM_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "BRAM_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "BRAM_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "BRAM_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "BRAM_LH8_4", - "VBRK_LH8" - ], - [ - "BRAM_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "BRAM_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "BRAM_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "BRAM_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "BRAM_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "BRAM_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "BRAM_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "BRAM_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "BRAM_LH5_4", - "VBRK_LH5" - ], - [ - "BRAM_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "BRAM_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "BRAM_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "BRAM_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "BRAM_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "BRAM_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "BRAM_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "BRAM_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "BRAM_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "BRAM_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "BRAM_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "BRAM_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "BRAM_LH3_4", - "VBRK_LH3" - ], - [ - "BRAM_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "BRAM_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "BRAM_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "BRAM_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "BRAM_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "BRAM_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "BRAM_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "BRAM_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "BRAM_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "BRAM_LH11_4", - "VBRK_LH11" - ], - [ - "BRAM_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "BRAM_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "BRAM_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "BRAM_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "BRAM_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "BRAM_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "BRAM_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "BRAM_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "BRAM_SE2A1_4", - "VBRK_SE2A1" - ], - [ - "BRAM_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "BRAM_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "BRAM_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "BRAM_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "BRAM_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "BRAM_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "BRAM_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "BRAM_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "BRAM_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "BRAM_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "BRAM_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "BRAM_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "BRAM_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "BRAM_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "BRAM_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "BRAM_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "BRAM_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "BRAM_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "BRAM_MONITOR_P_4", - "VBRK_MONITOR_P" - ] - ], - "tile_types": [ - "BRAM_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -4 - ] - }, - { - "wire_pairs": [ - [ - "CLK_PMV_NE2A0_3", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_PMV_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_PMV_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_PMV_WL1END3_3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_PMV_WW2A3_3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_PMV_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_PMV_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_PMV_IMUX17_3", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_WW4C1_3", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_PMV_SW2A2_3", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_PMV_WW4C2_3", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_PMV_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_FAN6_3", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_PMV_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_IMUX20_3", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_PMV_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_EE4C0_3", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_PMV_IMUX25_3", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_PMV_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_PMV_IMUX47_3", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_PMV_WL1END0_3", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_PMV_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_PMV_WW4C3_3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_IMUX39_3", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_PMV_EE2A0_3", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_PMV_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_PMV_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_PMV_WL1END1_3", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_PMV_EE2A1_3", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_PMV_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_PMV_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_PMV_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_LH1_3", - "INT_INTERFACE_LH1" - ], - [ - "CLK_PMV_IMUX3_3", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_PMV_NE4C1_3", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_PMV_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "CLK_PMV_CLK1_3", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_FAN0_3", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_SE4C3_3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_PMV_WW2A2_3", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_PMV_SE2A1_3", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_IMUX41_3", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_PMV_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_IMUX44_3", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_PMV_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_PMV_EE4B0_3", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_PMV_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_PMV_LH8_3", - "INT_INTERFACE_LH8" - ], - [ - "CLK_PMV_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_PMV_BYP5_3", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_WW2A1_3", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_PMV_SE4C1_3", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_PMV_CLK0_3", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_PMV_IMUX21_3", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_IMUX19_3", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_PMV_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_PMV_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_PMV_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_PMV_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_PMV_BYP7_3", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_IMUX6_3", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_PMV_IMUX7_3", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_EE4A0_3", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_PMV_EE4BEG0_3", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_PMV_BYP0_3", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_PMV_WW4END3_3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_PMV_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_IMUX0_3", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_PMV_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_PMV_IMUX26_3", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_PMV_SE4C2_3", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_PMV_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_PMV_IMUX10_3", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_PMV_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_PMV_SW2A1_3", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_PMV_WW4END0_3", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_PMV_SE4BEG1_3", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_PMV_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_PMV_FAN5_3", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_SE2A2_3", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_PMV_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_PMV_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_IMUX37_3", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_PMV_IMUX40_3", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_PMV_IMUX27_3", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_PMV_EE4B1_3", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_PMV_SW4A3_3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_PMV_WW2A0_3", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_IMUX43_3", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_PMV_WW4B3_3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_IMUX33_3", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_WW2END3_3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_NW4END0_3", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_PMV_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_PMV_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_PMV_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_PMV_WW4C0_3", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_PMV_SW4END0_3", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_PMV_LOGIC_OUTS9_3", - "INT_INTERFACE_LOGIC_OUTS_B9" - ], - [ - "CLK_PMV_EE4B3_3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_SE4BEG2_3", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_PMV_IMUX45_3", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_IMUX30_3", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_PMV_WR1END0_3", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_PMV_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_PMV_SW4END1_3", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_PMV_IMUX1_3", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_PMV_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_PMV_IMUX38_3", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_PMV_IMUX5_3", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_WR1END1_3", - "INT_INTERFACE_WR1END1" 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- [ - "CMT_TOP_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_LH4_1", - "VBRK_LH4" - ], - [ - "CMT_TOP_LH12_1", - "VBRK_LH12" - ], - [ - "CMT_TOP_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_LH11_1", - "VBRK_LH11" - ], - [ - "CMT_TOP_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_LH3_1", - "VBRK_LH3" - ], - [ - "CMT_TOP_LH2_1", - "VBRK_LH2" - ], - [ - "CMT_TOP_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_NE4C2_1", - "VBRK_NE4C2" - ] - ], - "tile_types": [ - "CMT_TOP_L_UPPER_B", - "VBRK" - ], - "grid_deltas": [ - -1, - 3 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_WW2A1_2", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_FAN3_2", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX30_2", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX23_2", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX6_2", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_IMUX11_2", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_EE4BEG1_2", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_NE4BEG0_2", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_FAN0_2", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX26_2", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_EE4BEG3_2", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE4A3_2", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WR1END3_2", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_IMUX19_2", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_BYP7_2", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WW2A3_2", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_NE4C1_2", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_IMUX7_2", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_ER1BEG0_2", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SE2A0_2", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_IMUX14_2", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_IMUX45_2", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SW4A3_2", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NE4C3_2", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX44_2", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_FAN7_2", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_IMUX39_2", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SE4BEG3_2", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NE4BEG2_2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NW4A0_2", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WL1END2_2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WW4C2_2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW4END0_2", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WW4A2_2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_SE4C1_2", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_IMUX33_2", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_CTRL0_2", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EL1BEG2_2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX16_2", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW2END3_2", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_IMUX8_2", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_CTRL1_2", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_NW4END1_2", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_EL1BEG3_2", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_LH2_2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_SW4END3_2", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EE4BEG0_2", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_IMUX21_2", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX46_2", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SW2A3_2", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_IMUX27_2", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX31_2", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_IMUX43_2", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_IMUX17_2", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_NW4END0_2", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX0_2", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX12_2", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SE4BEG1_2", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_FAN2_2", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_IMUX18_2", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_WR1END0_2", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE2BEG1_2", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_FAN6_2", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4C3_2", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_SE2A3_2", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_LH12_2", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_BYP3_2", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX2_2", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_NE2A3_2", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_SW4A2_2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_SW2A0_2", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_WR1END1_2", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4END3_2", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_WW4A0_2", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_LH6_2", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH9_2", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_WW4END2_2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE2BEG0_2", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_SE2A1_2", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_EE2A0_2", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_IMUX37_2", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_SE4BEG2_2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_WW4END1_2", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_EE4C2_2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_WW2END2_2", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_NE2A1_2", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_NW4END3_2", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_IMUX36_2", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_NW4END2_2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_WR1END2_2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW4C0_2", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_ER1BEG1_2", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_EE4B3_2", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_LH1_2", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX13_2", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_FAN1_2", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW4A1_2", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_SE4C2_2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_EE4B0_2", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_WW4B3_2", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE2A1_2", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_IMUX22_2", - "INT_INTERFACE_IMUX22" - ], - [ - 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"VBRK_WW4C0" - ], - [ - "CLBLL_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLBLL_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLBLL_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLBLL_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLBLL_LH9", - "VBRK_LH9" - ], - [ - "CLBLL_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLBLL_LH2", - "VBRK_LH2" - ], - [ - "CLBLL_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLBLL_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLBLL_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLBLL_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLBLL_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLBLL_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLBLL_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLBLL_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLBLL_LH4", - "VBRK_LH4" - ], - [ - "CLBLL_LH6", - "VBRK_LH6" - ], - [ - "CLBLL_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLBLL_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLBLL_LH1", - "VBRK_LH1" - ], - [ - "CLBLL_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLBLL_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLBLL_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLBLL_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLBLL_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLBLL_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLBLL_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLBLL_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLBLL_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLBLL_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLBLL_LH12", - "VBRK_LH12" - ], - [ - "CLBLL_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLBLL_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLBLL_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLBLL_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLBLL_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLBLL_LH7", - "VBRK_LH7" - ], - [ - "CLBLL_LH5", - "VBRK_LH5" - ], - [ - "CLBLL_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLBLL_LH10", - "VBRK_LH10" - ], - [ - "CLBLL_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLBLL_WW2END1", - "VBRK_WW2END1" - ] - ], - "tile_types": [ - "CLBLL_L", - "VBRK" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_FIFO_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "HCLK_FIFO_PERFCLK2", - "HCLK_INT_INTERFACE_PERFCLK2" - ], - [ - "HCLK_FIFO_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "HCLK_FIFO_CCIO1", - "HCLK_INT_INTERFACE_CCIO1" - ], - [ - "HCLK_FIFO_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "HCLK_FIFO_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "HCLK_FIFO_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "HCLK_FIFO_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "HCLK_FIFO_CCIO3", - "HCLK_INT_INTERFACE_CCIO3" - ], - [ - "HCLK_FIFO_CCIO0", - "HCLK_INT_INTERFACE_CCIO0" - ], - [ - "HCLK_FIFO_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "HCLK_FIFO_PERFCLK0", - "HCLK_INT_INTERFACE_PERFCLK0" - ], - [ - "HCLK_FIFO_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "HCLK_FIFO_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ], - [ - "HCLK_FIFO_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "HCLK_FIFO_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "HCLK_FIFO_PERFCLK3", - "HCLK_INT_INTERFACE_PERFCLK3" - ], - [ - "HCLK_FIFO_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "HCLK_FIFO_CCIO2", - "HCLK_INT_INTERFACE_CCIO2" - ], - [ - "HCLK_FIFO_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "HCLK_FIFO_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "HCLK_FIFO_PERFCLK1", - "HCLK_INT_INTERFACE_PERFCLK1" - ], - [ - "HCLK_FIFO_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_FIFO_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ] - ], - "tile_types": [ - "HCLK_FIFO_L", - "HCLK_INT_INTERFACE" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1" - ], - [ - "IOI_IOCLK3", - "IOI_IOCLK3" - ], - [ - "IOI_IOCLK2", - "IOI_IOCLK2" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK3" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK4" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK1" - ], - [ - "IOI_IOCLK0", - "IOI_IOCLK0" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_RCLK_FORIO3" - ], - [ - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CE3" - ], - [ - "IOI_IMUX_RC3", - "IOI_IMUX_RC1" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO2" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_LEAF_GCLK5" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO1" - ], - [ - "IOI_IMUX_RC2", - "IOI_IMUX_RC0" - ], - [ - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO0" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK2" - ], - [ - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK0" - ], - [ - "IOI_IOCLK1", - "IOI_IOCLK1" - ], - [ - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1" - ], - [ - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE2" - ] - ], - "tile_types": [ - "RIOI3", - "RIOI3_TBYTETERM" - ], - "grid_deltas": [ - 0, - -2 - ] - }, - { - "wire_pairs": [ - [ - "DSP_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - "DSP_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "DSP_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "DSP_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "DSP_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "DSP_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "DSP_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "DSP_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "DSP_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "DSP_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "DSP_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "DSP_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "DSP_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "DSP_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "DSP_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "DSP_LOGIC_OUTS_B23_1", - "INT_INTERFACE_LOGIC_OUTS_L_B23" - ], - [ - "DSP_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "DSP_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "DSP_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "DSP_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "DSP_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "DSP_LOGIC_OUTS_B21_1", - "INT_INTERFACE_LOGIC_OUTS_L_B21" - ], - [ - "DSP_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "DSP_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "DSP_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "DSP_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "DSP_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "DSP_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "DSP_LOGIC_OUTS_B0_1", - "INT_INTERFACE_LOGIC_OUTS_L_B0" - ], - [ - "DSP_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "DSP_LOGIC_OUTS_B11_1", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "DSP_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "DSP_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "DSP_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "DSP_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "DSP_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "DSP_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "DSP_LOGIC_OUTS_B20_1", - "INT_INTERFACE_LOGIC_OUTS_L_B20" - ], - [ - "DSP_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "DSP_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "DSP_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "DSP_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "DSP_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "DSP_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "DSP_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "DSP_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "DSP_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "DSP_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "DSP_NW4END3_1", - "INT_INTERFACE_NW4END3" - ], - [ - "DSP_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "DSP_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "DSP_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "DSP_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "DSP_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "DSP_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "DSP_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "DSP_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "DSP_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "DSP_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "DSP_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "DSP_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "DSP_LOGIC_OUTS_B6_1", - "INT_INTERFACE_LOGIC_OUTS_L_B6" - ], - [ - "DSP_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "DSP_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "DSP_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "DSP_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "DSP_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "DSP_LOGIC_OUTS_B7_1", - "INT_INTERFACE_LOGIC_OUTS_L_B7" - ], - [ - "DSP_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "DSP_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "DSP_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "DSP_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "DSP_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "DSP_IMUX10_1", - "INT_INTERFACE_IMUX10" - ], - [ - "DSP_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "DSP_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "DSP_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "DSP_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "DSP_EE4C2_1", - "INT_INTERFACE_EE4C2" - ], - [ - "DSP_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "DSP_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "DSP_LOGIC_OUTS_B17_1", - "INT_INTERFACE_LOGIC_OUTS_L_B17" - ], - [ - "DSP_BYP4_1", - "INT_INTERFACE_BYP4" - ], - [ - "DSP_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "DSP_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "DSP_LOGIC_OUTS_B22_1", - "INT_INTERFACE_LOGIC_OUTS_L_B22" - ], - [ - "DSP_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "DSP_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "DSP_LOGIC_OUTS_B1_1", - "INT_INTERFACE_LOGIC_OUTS_L_B1" - ], - [ - "DSP_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "DSP_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "DSP_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "DSP_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "DSP_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "DSP_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "DSP_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "DSP_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "DSP_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "DSP_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "DSP_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "DSP_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "DSP_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "DSP_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "DSP_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "DSP_LOGIC_OUTS_B3_1", - "INT_INTERFACE_LOGIC_OUTS_L_B3" - ], - [ - "DSP_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "DSP_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "DSP_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "DSP_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "DSP_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "DSP_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "DSP_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "DSP_SW2A0_1", - "INT_INTERFACE_SW2A0" - ], - [ - "DSP_LOGIC_OUTS_B19_1", - "INT_INTERFACE_LOGIC_OUTS_L_B19" - ], - [ - "DSP_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "DSP_LOGIC_OUTS_B18_1", - "INT_INTERFACE_LOGIC_OUTS_L_B18" - ], - [ - "DSP_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "DSP_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "DSP_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "DSP_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "DSP_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "DSP_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "DSP_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "DSP_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "DSP_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "DSP_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "DSP_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "DSP_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "DSP_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "DSP_LOGIC_OUTS_B12_1", - "INT_INTERFACE_LOGIC_OUTS_L_B12" - ], - [ - "DSP_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "DSP_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "DSP_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "DSP_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "DSP_MONITOR_N_1", - "INT_INTERFACE_MONITOR_N" - ], - [ - "DSP_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "DSP_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "DSP_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "DSP_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "DSP_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "DSP_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "DSP_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "DSP_ER1BEG1_1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "DSP_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "DSP_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "DSP_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "DSP_MONITOR_P_1", - "INT_INTERFACE_MONITOR_P" - ], - [ - "DSP_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "DSP_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "DSP_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "DSP_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "DSP_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "DSP_LOGIC_OUTS_B5_1", - "INT_INTERFACE_LOGIC_OUTS_L_B5" - ], - [ - "DSP_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "DSP_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "DSP_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "DSP_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "DSP_LOGIC_OUTS_B4_1", - "INT_INTERFACE_LOGIC_OUTS_L_B4" - ], - [ - "DSP_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "DSP_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "DSP_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "DSP_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "DSP_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "DSP_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "DSP_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "DSP_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "DSP_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "DSP_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "DSP_IMUX39_1", - "INT_INTERFACE_IMUX39" - ], - [ - "DSP_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "DSP_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "DSP_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "DSP_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "DSP_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "DSP_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "DSP_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "DSP_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "DSP_LOGIC_OUTS_B10_1", - "INT_INTERFACE_LOGIC_OUTS_L_B10" - ], - [ - "DSP_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "DSP_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "DSP_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "DSP_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "DSP_LOGIC_OUTS_B16_1", - "INT_INTERFACE_LOGIC_OUTS_L_B16" - ], - [ - "DSP_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "DSP_WW2A3_1", - "INT_INTERFACE_WW2A3" - ], - [ - "DSP_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "DSP_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "DSP_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "DSP_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "DSP_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "DSP_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "DSP_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "DSP_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "DSP_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "DSP_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "DSP_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "DSP_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "DSP_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "DSP_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "DSP_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "DSP_LOGIC_OUTS_B2_1", - "INT_INTERFACE_LOGIC_OUTS_L_B2" - ], - [ - "DSP_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "DSP_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "DSP_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "DSP_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "DSP_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "DSP_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "DSP_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "DSP_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "DSP_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "DSP_LOGIC_OUTS_B13_1", - "INT_INTERFACE_LOGIC_OUTS_L_B13" - ], - [ - "DSP_ER1BEG0_1", - "INT_INTERFACE_ER1BEG0" - ], - [ - "DSP_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "DSP_IMUX3_1", - "INT_INTERFACE_IMUX3" - ] - ], - "tile_types": [ - "DSP_L", - "INT_INTERFACE_L" - ], - "grid_deltas": [ - 1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "IOI_IOCLK3", - "IOI_IOCLK3" - ], - [ - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK3" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK4" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK1" - ], - [ - "IOI_IOCLK0", - "IOI_IOCLK0" - ], - [ - "IOI_IOCLK2", - "IOI_IOCLK2" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_RCLK_FORIO3" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO2" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO1" - ], - [ - "IOI_TBYTEIN", - "IOI_TBYTEIN" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_LEAF_GCLK5" - ], - [ - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO0" - ], - [ - "IOI_IMUX_RC1", - "IOI_IMUX_RC3" - ], - [ - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR0" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK2" - ], - [ - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK0" - ], - [ - "IOI_IOCLK1", - "IOI_IOCLK1" - ], - [ - "IOI_IMUX_RC0", - "IOI_IMUX_RC2" - ], - [ - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1" - ], - [ - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR1" - ] - ], - "tile_types": [ - "LIOI3", - "LIOI3_TBYTESRC" - ], - "grid_deltas": [ - 0, - 2 - ] - }, - { - "wire_pairs": [ - [ - "GTPE2_IMUX35_4", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_BYP0_4", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_CLK0_4", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_FAN0_4", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_LOGIC_OUTS_B16_4", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_IMUX20_4", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_LOGIC_OUTS_B14_4", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX5_4", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX47_4", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_FAN7_4", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX23_4", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_LOGIC_OUTS_B2_4", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_IMUX45_4", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_LOGIC_OUTS_B9_4", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX22_4", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_LOGIC_OUTS_B1_4", - "VBRK_EXT_LOGIC_OUTS_B1" - ], - [ - "GTPE2_IMUX24_4", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_IMUX32_4", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX27_4", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX44_4", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX41_4", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_LOGIC_OUTS_B18_4", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_IMUX42_4", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX33_4", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_LOGIC_OUTS_B19_4", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_FAN2_4", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX30_4", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_FAN4_4", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_LOGIC_OUTS_B4_4", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_IMUX28_4", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_LOGIC_OUTS_B12_4", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_LOGIC_OUTS_B15_4", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_IMUX39_4", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_BYP3_4", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_CLK1_4", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX10_4", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX9_4", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_BYP2_4", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_LOGIC_OUTS_B13_4", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_CTRL0_4", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_IMUX17_4", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_FAN1_4", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX36_4", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_FAN5_4", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_IMUX13_4", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_BYP1_4", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_FAN3_4", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_LOGIC_OUTS_B0_4", - "VBRK_EXT_LOGIC_OUTS_B0" - ], - [ - "GTPE2_IMUX29_4", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B23_4", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_LOGIC_OUTS_B20_4", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_IMUX40_4", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_BYP4_4", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX25_4", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX38_4", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_FAN6_4", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_LOGIC_OUTS_B7_4", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX31_4", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_LOGIC_OUTS_B22_4", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX7_4", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX46_4", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX6_4", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_BYP5_4", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX43_4", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX21_4", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_BYP6_4", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX4_4", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_LOGIC_OUTS_B17_4", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX37_4", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_IMUX14_4", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX26_4", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX8_4", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX12_4", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_LOGIC_OUTS_B6_4", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_IMUX2_4", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX19_4", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX15_4", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX1_4", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_IMUX16_4", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_LOGIC_OUTS_B21_4", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_CTRL1_4", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX0_4", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_BYP7_4", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX11_4", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX3_4", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX18_4", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX34_4", - "VBRK_EXT_IMUX34" - ] - ], - "tile_types": [ - "GTP_CHANNEL_0", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - 1 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_LV14", - "LV_L14" - ], - [ - "HCLK_SS6A2", - "SS6A2" - ], - [ - "HCLK_SE6B3", - "SE6B3" - ], - [ - "HCLK_NW6A2", - "NW6A2" - ], - [ - "HCLK_SR1BEG3", - "SR1END3" - ], - [ - "HCLK_NE2BEG2", - "NE2BEG2" - ], - [ - "HCLK_WR1BEG_S0", - "WR1BEG_S0" - ], - [ - "HCLK_NE6C2", - "NE6C2" - ], - [ - "HCLK_SR1END1", - "SR1END1" - ], - [ - "HCLK_NE6A0", - "NE6A0" - ], - [ - "HCLK_SS6E1", - "SS6E1" - ], - [ - "HCLK_NW2A1", - "NW2BEG1" - ], - [ - "HCLK_NE2BEG1", - "NE2BEG1" - ], - [ - "HCLK_NR1BEG3", - "NR1BEG3" - ], - [ - "HCLK_NE6A1", - "NE6A1" - ], - [ - "HCLK_SE6C2", - "SE6C2" - ], - [ - "HCLK_LV0", - "LV_L0" - ], - [ - "HCLK_FAN_BOUNCE_S3_6", - "FAN_BOUNCE_S3_6" - ], - [ - "HCLK_NL1END_S3_0", - "NL1END_S3_0" - ], - [ - "HCLK_NR1BEG1", - "NR1BEG1" - ], - [ - "HCLK_NN2A2", - "NN2A2" - ], - [ - "HCLK_SS2END2", - "SS2END2" - ], - [ - "HCLK_LV6", - "LV_L6" - ], - [ - "HCLK_SE6C3", - "SE6C3" - ], - [ - "HCLK_SE6D0", - "SE6D0" - ], - [ - "HCLK_NN6C3", - "NN6C3" - ], - [ - "HCLK_LEAF_CLK_B_BOTL0", - "GCLK_L_B6" - ], - [ - "HCLK_SS6END_N0_3", - "SS6END3" - ], - [ - "HCLK_LVB12", - "LVB_L11" - ], - [ - "HCLK_SW6E0", - "SW6E0" - ], - [ - "HCLK_LVB2", - "LVB_L1" - ], - [ - "HCLK_NE6D3", - "NE6D3" - ], - [ - "HCLK_SE2A1", - "SE2A1" - ], - [ - "HCLK_SW2END1", - "SW2A1" - ], - [ - "HCLK_NE6C3", - "NE6C3" - ], - [ - "HCLK_ER1END3", - "ER1END3" - ], - [ - "HCLK_NW6D2", - "NW6D2" - ], - [ - "HCLK_SE6C1", - "SE6C1" - ], - [ - "HCLK_NN6B1", - "NN6B1" - ], - [ - "HCLK_NW6B0", - "NW6B0" - ], - [ - "HCLK_EL1BEG3", - "EL1BEG3" - ], - [ - "HCLK_SE6E1", - "SE6E1" - ], - [ - "HCLK_SS2A0", - "SS2A0" - ], - [ - "HCLK_NN6C1", - "NN6C1" - ], - [ - "HCLK_NN2A3", - "NN2A3" - ], - [ - "HCLK_SS2BEG3", - "SS2A3" - ], - [ - "HCLK_LV16", - "LV_L16" - ], - [ - "HCLK_NE6B3", - "NE6B3" - ], - [ - "HCLK_NN6B3", - "NN6B3" - ], - [ - "HCLK_SE6D1", - "SE6D1" - ], - [ - "HCLK_SS6C2", - "SS6C2" - ], - [ - "HCLK_SW6C3", - "SW6C3" - ], - [ - "HCLK_NN2BEG1", - "NN2BEG1" - ], - [ - "HCLK_ER1BEG_S0", - "ER1BEG_S0" - ], - [ - "HCLK_LVB8", - "LVB_L7" - ], - [ - "HCLK_NN2BEG2", - "NN2BEG2" - ], - [ - "HCLK_NN2BEG0", - "NN2BEG0" - ], - [ - "HCLK_SS2A1", - "SS2A1" - ], - [ - "HCLK_SS6END1", - "SS6END1" - ], - [ - "HCLK_NE2END_S3_0", - "NE2END_S3_0" - ], - [ - "HCLK_NE2BEG0", - "NE2BEG0" - ], - [ - "HCLK_NL1BEG1", - "NL1BEG1" - ], - [ - "HCLK_NN6C0", - "NN6C0" - ], - [ - "HCLK_NW6B1", - "NW6B1" - ], - [ - "HCLK_SE2A0", - "SE2A0" - ], - [ - "HCLK_LEAF_CLK_B_BOTL3", - "GCLK_L_B9" - ], - [ - "HCLK_SE6B0", - "SE6B0" - ], - [ - "HCLK_NN2A0", - "NN2A0" - ], - [ - "HCLK_NL1BEG0", - "NL1BEG0" - ], - [ - "HCLK_LEAF_CLK_B_BOTL5", - "GCLK_L_B11" - ], - [ - "HCLK_SW6C1", - "SW6C1" - ], - [ - "HCLK_LV13", - "LV_L13" - ], - [ - "HCLK_NN2BEG3", - "NN2BEG3" - ], - [ - "HCLK_BYP_BOUNCE7", - "BYP_BOUNCE7" - ], - [ - "HCLK_LVB11", - "LVB_L10" - ], - [ - "HCLK_BYP_BOUNCE3", - "BYP_BOUNCE3" - ], - [ - "HCLK_NN6END_S1_0", - "NN6END_S1_0" - ], - [ - "HCLK_LV4", - "LV_L4" - ], - [ - "HCLK_NE2BEG3", - "NE2BEG3" - ], - [ - "HCLK_SW6C2", - "SW6C2" - ], - [ - "HCLK_SS6END3", - "SS6END3" - ], - [ - "HCLK_NW6B3", - "NW6B3" - ], - [ - "HCLK_NE6B0", - "NE6B0" - ], - [ - "HCLK_SS2A2", - "SS2A2" - ], - [ - "HCLK_SE6B1", - "SE6B1" - ], - [ - "HCLK_SS2END0", - "SS2END0" - ], - [ - "HCLK_NE6D0", - "NE6D0" - ], - [ - "HCLK_NN6BEG1", - "NN6BEG1" - ], - [ - "HCLK_NW2A0", - "NW2BEG0" - ], - [ - "HCLK_NW6C0", - "NW6C0" - ], - [ - "HCLK_NE6B1", - "NE6B1" - ], - [ - "HCLK_SL1END3", - "SL1END3" - ], - [ - "HCLK_SE6E3", - "SE6E3" - ], - [ - "HCLK_NE6B2", - "NE6B2" - ], - [ - "HCLK_LVB3", - "LVB_L2" - ], - [ - "HCLK_NW6C3", - "NW6C3" - ], - [ - "HCLK_LV17", - "LV_L17" - ], - [ - "HCLK_SW6B3", - "SW6B3" - ], - [ - "HCLK_NN6BEG0", - "NN6BEG0" - ], - [ - "HCLK_NN6D0", - "NN6D0" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE2" - ], - [ - "HCLK_SW6D0", - "SW6D0" - ], - [ - "HCLK_LVB6", - "LVB_L5" - ], - [ - "HCLK_NN6D1", - "NN6D1" - ], - [ - "HCLK_LEAF_CLK_B_BOTL2", - "GCLK_L_B8" - ], - [ - "HCLK_SS6D2", - "SS6D2" - ], - [ - "HCLK_SW6D2", - "SW6D2" - ], - [ - "HCLK_SW6E2", - "SW6E2" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END_S1_0" - ], - [ - "HCLK_WW4END_S0_0", - "WW4END_S0_0" - ], - [ - "HCLK_NN2END_S2_0", - "NN2END_S2_0" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END3" - ], - [ - "HCLK_SS2A3", - "SS2END3" - ], - [ - "HCLK_SE6D2", - "SE6D2" - ], - [ - "HCLK_SS6A1", - "SS6A1" - ], - [ - "HCLK_FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_4" - ], - [ - "HCLK_SE2A2", - "SE2A2" - ], - [ - "HCLK_SE6C0", - "SE6C0" - ], - [ - "HCLK_LVB7", - "LVB_L6" - ], - [ - "HCLK_SW2A3", - "SW2A3" - ], - [ - "HCLK_NN6A1", - "NN6A1" - ], - [ - "HCLK_NE6C1", - "NE6C1" - ], - [ - "HCLK_SS2END1", - "SS2END1" - ], - [ - "HCLK_WL1END3", - "WL1END3" - ], - [ - "HCLK_LV3", - "LV_L3" - ], - [ - "HCLK_NW6END_S0_0", - "NW6END_S0_0" - ], - [ - "HCLK_NN6D2", - "NN6D2" - ], - [ - "HCLK_LVB1", - "LVB_L0" - ], - [ - "HCLK_LEAF_CLK_B_BOTL4", - "GCLK_L_B10" - ], - [ - "HCLK_SS6D0", - "SS6D0" - ], - [ - "HCLK_SS6E3", - "SS6E3" - ], - [ - "HCLK_NW2A3", - "NW2BEG3" - ], - [ - "HCLK_NE6C0", - "NE6C0" - ], - [ - "HCLK_NW6C1", - "NW6C1" - ], - [ - "HCLK_NN6A0", - "NN6A0" - ], - [ - "HCLK_SW2END2", - "SW2A2" - ], - [ - "HCLK_NW2A2", - "NW2BEG2" - ], - [ - "HCLK_NW6A0", - "NW6A0" - ], - [ - "HCLK_SL1END0", - "SL1END0" - ], - [ - "HCLK_NN6B0", - "NN6B0" - ], - [ - "HCLK_SR1END_N3_3", - "SR1END3" - ], - [ - "HCLK_LV11", - "LV_L11" - ], - [ - "HCLK_LV8", - "LV_L8" - ], - [ - "HCLK_LVB9", - "LVB_L8" - ], - [ - "HCLK_SS6C1", - "SS6C1" - ], - [ - "HCLK_SL1END2", - "SL1END2" - ], - [ - "HCLK_LEAF_CLK_B_BOTL1", - "GCLK_L_B7" - ], - [ - "HCLK_NW6A3", - "NW6A3" - ], - [ - "HCLK_WW2END3", - "WW2END3" - ], - [ - "HCLK_NN6B2", - "NN6B2" - ], - [ - "HCLK_NN6E0", - "NN6E0" - ], - [ - "HCLK_NL1BEG2", - "NL1BEG2" - ], - [ - "HCLK_SS6C0", - "SS6C0" - ], - [ - "HCLK_NN6E2", - "NN6E2" - ], - [ - "HCLK_NE6A2", - "NE6A2" - ], - [ - "HCLK_NW6D0", - "NW6D0" - ], - [ - "HCLK_SL1END1", - "SL1END1" - ], - [ - "HCLK_SS6B0", - "SS6B0" - ], - [ - "HCLK_SS6E2", - "SS6E2" - ], - [ - "HCLK_SE6B2", - "SE6B2" - ], - [ - "HCLK_SE2A3", - "SE2A3" - ], - [ - "HCLK_SW6B0", - "SW6B0" - ], - [ - "HCLK_LV1", - "LV_L1" - ], - [ - "HCLK_NN6C2", - "NN6C2" - ], - [ - "HCLK_NW2END_S0_0", - "NW2END_S0_0" - ], - [ - "HCLK_SS6END2", - "SS6END2" - ], - [ - "HCLK_NW6C2", - "NW6C2" - ], - [ - "HCLK_SE6D3", - "SE6D3" - ], - [ - "HCLK_NW6A1", - "NW6A1" - ], - [ - "HCLK_SE6E0", - "SE6E0" - ], - [ - "HCLK_EL1END_S3_0", - "EL1END_S3_0" - ], - [ - "HCLK_SS6A3", - "SS6A3" - ], - [ - "HCLK_SW6E1", - "SW6E1" - ], - [ - "HCLK_SE6E2", - "SE6E2" - ], - [ - "HCLK_WL1BEG3", - "WL1BEG3" - ], - [ - "HCLK_NN6A3", - "NN6A3" - ], - [ - "HCLK_LV2", - "LV_L2" - ], - [ - "HCLK_NN2A1", - "NN2A1" - ], - [ - "HCLK_SS6B1", - "SS6B1" - ], - [ - "HCLK_SS6C3", - "SS6C3" - ], - [ - "HCLK_NR1BEG2", - "NR1BEG2" - ], - [ - "HCLK_SW6END3", - "SW6END3" - ], - [ - "HCLK_NE6D2", - "NE6D2" - ], - [ - "HCLK_NN6BEG3", - "NN6BEG3" - ], - [ - "HCLK_FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_2" - ], - [ - "HCLK_NN6E3", - "NN6E3" - ], - [ - "HCLK_NW6B2", - "NW6B2" - ], - [ - "HCLK_SS6A0", - "SS6A0" - ], - [ - "HCLK_SS6B2", - "SS6B2" - ], - [ - "HCLK_LVB4", - "LVB_L3" - ], - [ - "HCLK_SS6D3", - "SS6D3" - ], - [ - "HCLK_LVB5", - "LVB_L4" - ], - [ - "HCLK_SR1END2", - "SR1END2" - ], - [ - "HCLK_NR1BEG0", - "NR1BEG0" - ], - [ - "HCLK_LV5", - "LV_L5" - ], - [ - "HCLK_LVB10", - "LVB_L9" - ], - [ - "HCLK_BYP_BOUNCE6", - "BYP_BOUNCE6" - ], - [ - "HCLK_NW6D3", - "NW6D3" - ], - [ - "HCLK_LV15", - "LV_L15" - ], - [ - "HCLK_SS2END_N0_3", - "SS2END3" - ], - [ - "HCLK_NN6E1", - "NN6E1" - ], - [ - "HCLK_NE6A3", - "NE6A3" - ], - [ - "HCLK_SW6B1", - "SW6B1" - ], - [ - "HCLK_FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_0" - ], - [ - "HCLK_SW6D3", - "SW6D3" - ], - [ - "HCLK_NW6D1", - "NW6D1" - ], - [ - "HCLK_LV10", - "LV_L10" - ], - [ - "HCLK_SW2END0", - "SW2A0" - ], - [ - "HCLK_NN6A2", - "NN6A2" - ], - [ - "HCLK_NN6D3", - "NN6D3" - ], - [ - "HCLK_LV9", - "LV_L9" - ], - [ - "HCLK_SS6E0", - "SS6E0" - ], - [ - "HCLK_SW6D1", - "SW6D1" - ], - [ - "HCLK_NN6BEG2", - "NN6BEG2" - ], - [ - "HCLK_SW6B2", - "SW6B2" - ], - [ - "HCLK_NE6D1", - "NE6D1" - ], - [ - "HCLK_SS6B3", - "SS6B3" - ], - [ - "HCLK_SS6D1", - "SS6D1" - ], - [ - "HCLK_LV12", - "LV_L12" - ], - [ - "HCLK_LV7", - "LV_L7" - ], - [ - "HCLK_SW6C0", - "SW6C0" - ], - [ - "HCLK_SS6END0", - "SS6END0" - ], - [ - "HCLK_SW6E3", - "SW6E3" - ] - ], - "tile_types": [ - "HCLK_L", - "INT_L" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLBLM_L_CIN", - "CLBLM_L_COUT_N" - ], - [ - "CLBLM_M_CIN", - "CLBLM_M_COUT_N" - ] - ], - "tile_types": [ - "CLBLM_L", - "CLBLM_L" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "EL1BEG3", - "EL1BEG_N3" - ], - [ - "NN6B1", - "NN6C1" - ], - [ - "NN2A0", - "NN2END0" - ], - [ - "SE2A2", - "SE2BEG2" - ], - [ - "LVB_L2", - "LVB_L3" - ], - [ - "LV_L5", - "LV_L6" - ], - [ - "NE6D2", - "NE6E2" - ], - [ - "NW6B2", - "NW6C2" - ], - [ - "LV_L1", - "LV_L2" - ], - [ - "SW2A3", - "SW2BEG3" - ], - [ - "NE6A1", - "NE6B1" - ], - [ - "LVB_L6", - "LVB_L7" - ], - [ - "SS2A2", - "SS2BEG2" - ], - [ - "NW6A0", - "NW6B0" - ], - [ - "NN6A2", - "NN6B2" - ], - [ - "LV_L12", - "LV_L13" - ], - [ - "NW6C2", - "NW6D2" - ], - [ - "NN6E1", - "NN6END1" - ], - [ - "NE6A0", - "NE6B0" - ], - [ - "NN6C0", - "NN6D0" - ], - [ - "SS2END3", - "SS2END_N0_3" - ], - [ - "NL1BEG0", - "NL1END0" - ], - [ - "NE6C3", - "NE6D3" - ], - [ - "LVB_L0", - "LVB_L1" - ], - [ - "LVB_L8", - "LVB_L9" - ], - [ - "NN6C2", - "NN6D2" - ], - [ - "LVB_L11", - "LVB_L12" - ], - [ - "LVB_L1", - "LVB_L2" - ], - [ - "LV_L7", - "LV_L8" - ], - [ - "NL1BEG2", - "NL1END2" - ], - [ - "NE6B1", - "NE6C1" - ], - [ - "NN2A1", - "NN2END1" - ], - [ - "NN6A1", - "NN6B1" - ], - [ - "SS2A1", - "SS2BEG1" - ], - [ - "NW6D1", - "NW6E1" - ], - [ - "NW6D3", - "NW6E3" - ], - [ - "NN6D3", - "NN6E3" - ], - [ - "LV_L14", - "LV_L15" - ], - [ - "BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" - ], - [ - "SS6A1", - "SS6BEG1" - ], - [ - "NE6C1", - "NE6D1" - ], - [ - "LV_L17", - "LV_L18" - ], - [ - "LV_L4", - "LV_L5" - ], - [ - "NW6C0", - "NW6D0" - ], - [ - "SW2A2", - "SW2BEG2" - ], - [ - "LV_L16", - "LV_L17" - ], - [ - "LV_L10", - "LV_L11" - ], - [ - "NW6B1", - "NW6C1" - ], - [ - "LV_L8", - "LV_L9" - ], - [ - "NR1BEG2", - "NR1END2" - ], - [ - "NE6A3", - "NE6B3" - ], - [ - "NN6A0", - "NN6B0" - ], - [ - "NN6D2", - "NN6E2" - ], - [ - "NN6B2", - "NN6C2" - ], - [ - "LVB_L5", - "LVB_L6" - ], - [ - "NW6B3", - "NW6C3" - ], - [ - "LV_L2", - "LV_L3" - ], - [ - "NE6D3", - "NE6E3" - ], - [ - "NN2A3", - "NN2END3" - ], - [ - "SW6END3", - "SW6END_N0_3" - ], - [ - "SS6END3", - "SS6END_N0_3" - ], - [ - "NN6C1", - "NN6D1" - ], - [ - "NW6C3", - "NW6D3" - ], - [ - "SR1END3", - "SR1END_N3_3" - ], - [ - "SS2A3", - "SS2BEG3" - ], - [ - "LV_L0", - "LV_L1" - ], - [ - "WL1BEG3", - "WL1BEG_N3" - ], - [ - "NE6C2", - "NE6D2" - ], - [ - "BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "ER1END3", - "ER1END_N3_3" - ], - [ - "NN6E0", - "NN6END0" - ], - [ - "NN2A2", - "NN2END2" - ], - [ - "LV_L6", - "LV_L7" - ], - [ - "NE6B3", - "NE6C3" - ], - [ - "NW6D2", - "NW6E2" - ], - [ - "LV_L3", - "LV_L4" - ], - [ - "LVB_L4", - "LVB_L5" - ], - [ - "NE6B0", - "NE6C0" - ], - [ - "LV_L15", - "LV_L16" - ], - [ - "NW6A2", - "NW6B2" - ], - [ - "BYP_BOUNCE3", - "BYP_BOUNCE_N3_3" - ], - [ - "LV_L11", - "LV_L12" - ], - [ - "NR1BEG1", - "NR1END1" - ], - [ - "SW2A0", - "SW2BEG0" - ], - [ - "SS6A0", - "SS6BEG0" - ], - [ - "SW2END3", - "SW2END_N0_3" - ], - [ - "NN6D0", - "NN6E0" - ], - [ - "NN6E2", - "NN6END2" - ], - [ - "NE6D1", - "NE6E1" - ], - [ - "NN6E3", - "NN6END3" - ], - [ - "NN6B3", - "NN6C3" - ], - [ - "LVB_L10", - "LVB_L11" - ], - [ - "SE2A0", - "SE2BEG0" - ], - [ - "SS2A0", - "SS2BEG0" - ], - [ - "LV_L13", - "LV_L14" - ], - [ - "LVB_L3", - "LVB_L4" - ], - [ - "NW6A3", - "NW6B3" - ], - [ - "NW6D0", - "NW6E0" - ], - [ - "NE6A2", - "NE6B2" - ], - [ - "SS6A3", - "SS6BEG3" - ], - [ - "BYP_BOUNCE7", - "BYP_BOUNCE_N3_7" - ], - [ - "NN6C3", - "NN6D3" - ], - [ - "NW6B0", - "NW6C0" - ], - [ - "NE6B2", - "NE6C2" - ], - [ - "NN6A3", - "NN6B3" - ], - [ - "SE2A3", - "SE2BEG3" - ], - [ - "NN6D1", - "NN6E1" - ], - [ - "WL1END3", - "WL1END_N1_3" - ], - [ - "NW6A1", - "NW6B1" - ], - [ - "NE6D0", - "NE6E0" - ], - [ - "NN6B0", - "NN6C0" - ], - [ - "NR1BEG3", - "NR1END3" - ], - [ - "LVB_L7", - "LVB_L8" - ], - [ - "WW2END3", - "WW2END_N0_3" - ], - [ - "SS6A2", - "SS6BEG2" - ], - [ - "SW2A1", - "SW2BEG1" - ], - [ - "SE2A1", - "SE2BEG1" - ], - [ - "NL1BEG1", - "NL1END1" - ], - [ - "NR1BEG0", - "NR1END0" - ], - [ - "NE6C0", - "NE6D0" - ], - [ - "NW6C1", - "NW6D1" - ] - ], - "tile_types": [ - "INT_L", - "INT_L" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_SW2A0_1", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_ER1BEG1_1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_ER1BEG0_1", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_IMUX3_1", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_WW4END2_1", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_WW2A3_1", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_BYP4_1", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_NW4END3_1", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_IMUX10_1", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_EE4C2_1", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX39_1", - "INT_INTERFACE_IMUX39" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - 3 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_LH1_2", - "VBRK_LH1" - ], - [ - "CMT_TOP_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_EE4C0_2", - "VBRK_EE4C0" - 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"INT_INTERFACE_BRAM_IMUX1", - "BRAM_IMUX1_3" - ], - [ - "INT_INTERFACE_SE4BEG0", - "BRAM_SE4BEG0_3" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX0", - "BRAM_IMUX0_UTURN_3" - ], - [ - "INT_INTERFACE_NE4BEG2", - "BRAM_NE4BEG2_3" - ], - [ - "INT_INTERFACE_EE4BEG3", - "BRAM_EE4BEG3_3" - ], - [ - "INT_INTERFACE_SW2A2", - "BRAM_SW2A2_3" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_3" - ], - [ - "INT_INTERFACE_WL1END1", - "BRAM_WL1END1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "BRAM_LOGIC_OUTS_B9_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX35", - "BRAM_IMUX35_UTURN_3" - ], - [ - "INT_INTERFACE_BYP2", - "BRAM_BYP2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX42", - "BRAM_IMUX42_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "BRAM_LOGIC_OUTS_B11_3" - ], - [ - "INT_INTERFACE_NW4END0", - "BRAM_NW4END0_3" - ], - [ - "INT_INTERFACE_BYP1", - "BRAM_BYP1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX7", - "BRAM_IMUX7_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX23", - "BRAM_IMUX23_3" - ], - [ - "INT_INTERFACE_WW4END1", - "BRAM_WW4END1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "BRAM_LOGIC_OUTS_B19_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "BRAM_LOGIC_OUTS_B15_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX15", - "BRAM_IMUX15_UTURN_3" - ], - [ - "INT_INTERFACE_NE4C1", - "BRAM_NE4C1_3" - ], - [ - "INT_INTERFACE_NE4BEG1", - "BRAM_NE4BEG1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX34", - "BRAM_IMUX34_3" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "BRAM_IMUX31_3" - ], - [ - "INT_INTERFACE_LH11", - "BRAM_LH11_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX26", - "BRAM_IMUX26_3" - ], - [ - "INT_INTERFACE_NE4BEG3", - "BRAM_NE4BEG3_3" - ], - [ - "INT_INTERFACE_NE2A1", - "BRAM_NE2A1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX16", - "BRAM_IMUX16_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX24", - "BRAM_IMUX24_UTURN_3" - ], - [ - "INT_INTERFACE_SE4C1", - "BRAM_SE4C1_3" - ], - [ - "INT_INTERFACE_WL1END0", - "BRAM_WL1END0_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - "BRAM_IMUX47_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX12", - "BRAM_IMUX12_UTURN_3" - ], - [ - "INT_INTERFACE_SE2A2", - "BRAM_SE2A2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX14", - "BRAM_IMUX14_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "BRAM_LOGIC_OUTS_B8_3" - ], - [ - "INT_INTERFACE_SW4A2", - "BRAM_SW4A2_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX11", - "BRAM_IMUX11_3" - ], - [ - "INT_INTERFACE_NW4END2", - "BRAM_NW4END2_3" - ], - [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_3" - ], - [ - "INT_INTERFACE_NW4END3", - "BRAM_NW4END3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX45", - "BRAM_IMUX45_UTURN_3" - ], - [ - "INT_INTERFACE_FAN5", - "BRAM_FAN5_3" - ], - [ - "INT_INTERFACE_EE4B1", - "BRAM_EE4B1_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX27", - "BRAM_IMUX27_UTURN_3" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_3" - ], - [ - "INT_INTERFACE_FAN2", - "BRAM_FAN2_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "BRAM_LOGIC_OUTS_B0_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_3" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_3" - ], - [ - "INT_INTERFACE_EL1BEG1", - "BRAM_EL1BEG1_3" - ], - [ - "INT_INTERFACE_WW2A0", - "BRAM_WW2A0_3" - ], - [ - "INT_INTERFACE_CTRL0", - "BRAM_CTRL0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX18", - "BRAM_IMUX18_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX7", - "BRAM_IMUX7_UTURN_3" - ], - [ - "INT_INTERFACE_NW4A1", - "BRAM_NW4A1_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX43", - "BRAM_IMUX43_UTURN_3" - ], - [ - "INT_INTERFACE_SE4BEG1", - "BRAM_SE4BEG1_3" - ], - [ - "INT_INTERFACE_EE4C2", - "BRAM_EE4C2_3" - ], - [ - "INT_INTERFACE_CLK0", - "BRAM_CLK0_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "BRAM_LOGIC_OUTS_B5_3" - ], - [ - "INT_INTERFACE_FAN3", - "BRAM_FAN3_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX42", - "BRAM_IMUX42_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX19", - "BRAM_IMUX19_UTURN_3" - ], - [ - "INT_INTERFACE_WW2A1", - "BRAM_WW2A1_3" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_3" - ], - [ - "INT_INTERFACE_WW4B0", - "BRAM_WW4B0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX30", - "BRAM_IMUX30_UTURN_3" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_3" - ], - [ - "INT_INTERFACE_EE2A0", - "BRAM_EE2A0_3" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "BRAM_IMUX17_3" - ], - [ - "INT_INTERFACE_WW2A2", - "BRAM_WW2A2_3" - ], - [ - "INT_INTERFACE_EE2BEG1", - "BRAM_EE2BEG1_3" - ], - [ - "INT_INTERFACE_MONITOR_P", - "BRAM_MONITOR_P_3" - ], - [ - "INT_INTERFACE_NE4BEG0", - "BRAM_NE4BEG0_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX40", - "BRAM_IMUX40_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX43", - "BRAM_IMUX43_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX16", - "BRAM_IMUX16_UTURN_3" - ], - [ - "INT_INTERFACE_EE4BEG0", - "BRAM_EE4BEG0_3" - ], - [ - "INT_INTERFACE_BYP4", - "BRAM_BYP4_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "BRAM_IMUX44_3" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_3" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_3" - ], - [ - "INT_INTERFACE_EE4A0", - "BRAM_EE4A0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX5", - "BRAM_IMUX5_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B14", - "BRAM_LOGIC_OUTS_B14_3" - ], - [ - "INT_INTERFACE_WW4A3", - "BRAM_WW4A3_3" - ], - [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_3" - ], - [ - "INT_INTERFACE_EE4A2", - "BRAM_EE4A2_3" - ], - [ - "INT_INTERFACE_WW4END3", - "BRAM_WW4END3_3" - ], - [ - "INT_INTERFACE_FAN7", - "BRAM_FAN7_3" - ], - [ - "INT_INTERFACE_NW2A1", - "BRAM_NW2A1_3" - ], - [ - "INT_INTERFACE_LH4", - "BRAM_LH4_3" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "BRAM_IMUX38_3" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "BRAM_LOGIC_OUTS_B3_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "BRAM_LOGIC_OUTS_B16_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX40", - "BRAM_IMUX40_UTURN_3" - ], - [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX39", - "BRAM_IMUX39_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX47", - "BRAM_IMUX47_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX8", - "BRAM_IMUX8_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "BRAM_LOGIC_OUTS_B17_3" - ], - [ - "INT_INTERFACE_BYP5", - "BRAM_BYP5_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX25", - "BRAM_IMUX25_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_3" - ], - [ - "INT_INTERFACE_ER1BEG3", - "BRAM_ER1BEG3_3" - ], - [ - "INT_INTERFACE_SE4C3", - "BRAM_SE4C3_3" - ], - [ - "INT_INTERFACE_EE4B2", - "BRAM_EE4B2_3" - ], - [ - "INT_INTERFACE_EE4B3", - "BRAM_EE4B3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX34", - "BRAM_IMUX34_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "BRAM_LOGIC_OUTS_B7_3" - ], - [ - "INT_INTERFACE_NW4A2", - "BRAM_NW4A2_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX30", - "BRAM_IMUX30_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX20", - "BRAM_IMUX20_UTURN_3" - ], - [ - "INT_INTERFACE_LH5", - "BRAM_LH5_3" - ], - [ - "INT_INTERFACE_EE4A3", - "BRAM_EE4A3_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "BRAM_IMUX3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX46", - "BRAM_IMUX46_UTURN_3" - ], - [ - "INT_INTERFACE_SW4END0", - "BRAM_SW4END0_3" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "BRAM_LOGIC_OUTS_B2_3" - ], - [ - "INT_INTERFACE_EE2BEG2", - "BRAM_EE2BEG2_3" - ], - [ - "INT_INTERFACE_WR1END3", - "BRAM_WR1END3_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "BRAM_LOGIC_OUTS_B20_3" - ], - [ - "INT_INTERFACE_NE4C2", - "BRAM_NE4C2_3" - ], - [ - "INT_INTERFACE_LH12", - "BRAM_LH12_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "BRAM_IMUX32_3" - ], - [ - "INT_INTERFACE_SW2A3", - "BRAM_SW2A3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX36", - "BRAM_IMUX36_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX38", - "BRAM_IMUX38_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "BRAM_IMUX8_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX45", - "BRAM_IMUX45_3" - ], - [ - "INT_INTERFACE_NE4C0", - "BRAM_NE4C0_3" - ], - [ - "INT_INTERFACE_WW2END3", - "BRAM_WW2END3_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX20", - "BRAM_IMUX20_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX44", - "BRAM_IMUX44_UTURN_3" - ], - [ - "INT_INTERFACE_WL1END3", - "BRAM_WL1END3_3" - ], - [ - "INT_INTERFACE_LH6", - "BRAM_LH6_3" - ], - [ - "INT_INTERFACE_EE2A1", - "BRAM_EE2A1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "BRAM_LOGIC_OUTS_B1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX0", - "BRAM_IMUX0_3" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_3" - ], - [ - "INT_INTERFACE_EE4BEG2", - "BRAM_EE4BEG2_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX19", - "BRAM_IMUX19_3" - ], - [ - "INT_INTERFACE_FAN0", - "BRAM_FAN0_3" - ], - [ - "INT_INTERFACE_WW4END2", - "BRAM_WW4END2_3" - ], - [ - "INT_INTERFACE_NW2A3", - "BRAM_NW2A3_3" - ], - [ - "INT_INTERFACE_SW4END2", - "BRAM_SW4END2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX31", - "BRAM_IMUX31_UTURN_3" - ], - [ - "INT_INTERFACE_WW4C0", - "BRAM_WW4C0_3" - ], - [ - "INT_INTERFACE_EE4A1", - "BRAM_EE4A1_3" - ], - [ - "INT_INTERFACE_WW4A1", - "BRAM_WW4A1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "BRAM_LOGIC_OUTS_B4_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "BRAM_LOGIC_OUTS_B18_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX41", - "BRAM_IMUX41_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX6", - "BRAM_IMUX6_UTURN_3" - ], - [ - "INT_INTERFACE_NE2A2", - "BRAM_NE2A2_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "BRAM_LOGIC_OUTS_B13_3" - ], - [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_3" - ], - [ - "INT_INTERFACE_SE4C0", - "BRAM_SE4C0_3" - ], - [ - "INT_INTERFACE_EL1BEG0", - "BRAM_EL1BEG0_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "BRAM_LOGIC_OUTS_B22_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "BRAM_IMUX10_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX22", - "BRAM_IMUX22_UTURN_3" - ], - [ - "INT_INTERFACE_MONITOR_N", - "BRAM_MONITOR_N_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX27", - "BRAM_IMUX27_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "BRAM_IMUX6_3" - ], - [ - "INT_INTERFACE_FAN4", - "BRAM_FAN4_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX13", - "BRAM_IMUX13_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX29", - "BRAM_IMUX29_3" - ], - [ - "INT_INTERFACE_ER1BEG2", - "BRAM_ER1BEG2_3" - ], - [ - "INT_INTERFACE_EE4C3", - "BRAM_EE4C3_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "BRAM_IMUX25_3" - ], - [ - "INT_INTERFACE_CTRL1", - "BRAM_CTRL1_3" - ], - [ - "INT_INTERFACE_SW4A3", - "BRAM_SW4A3_3" - ], - [ - "INT_INTERFACE_FAN6", - "BRAM_FAN6_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_3" - ], - [ - "INT_INTERFACE_SE4BEG3", - "BRAM_SE4BEG3_3" - ], - [ - "INT_INTERFACE_SW4A0", - "BRAM_SW4A0_3" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "BRAM_LOGIC_OUTS_B23_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX4", - "BRAM_IMUX4_UTURN_3" - ], - [ - "INT_INTERFACE_NW4A0", - "BRAM_NW4A0_3" - ], - [ - "INT_INTERFACE_ER1BEG1", - "BRAM_ER1BEG1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX9", - "BRAM_IMUX9_UTURN_3" - ], - [ - "INT_INTERFACE_WW2A3", - "BRAM_WW2A3_3" - ], - [ - "INT_INTERFACE_WL1END2", - "BRAM_WL1END2_3" - ], - [ - "INT_INTERFACE_LH3", - "BRAM_LH3_3" - ] - ], - "tile_types": [ - "BRAM_INT_INTERFACE_L", - "BRAM_L" - ], - "grid_deltas": [ - -1, - 3 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "HCLK_CLB_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_CLB_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_CLB_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_CLB_PERFCLK3", - "HCLK_VBRK_PHSR_PERFCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_CLB_PERFCLK2", - "HCLK_VBRK_PHSR_PERFCLK2" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - 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"grid_deltas": [ - 1, - 7 - ] - }, - { - "wire_pairs": [ - [ - "CLK_BUFG_REBUF_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CLK_BUFG_REBUF_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "CLK_BUFG_REBUF_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_BUFG_REBUF_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CLK_BUFG_REBUF_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CLK_BUFG_REBUF_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CLK_BUFG_REBUF_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "CLK_BUFG_REBUF_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_BUFG_REBUF_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CLK_BUFG_REBUF_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CLK_BUFG_REBUF_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CLK_BUFG_REBUF_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CLK_BUFG_REBUF_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CLK_BUFG_REBUF_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CLK_BUFG_REBUF_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_BUFG_REBUF_LH10_0", - "VBRK_LH10" - ], - [ - "CLK_BUFG_REBUF_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CLK_BUFG_REBUF_WW2END2_0", - "VBRK_WW2END2" - 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"INT_INTERFACE_FAN6" - ], - [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_FEED_SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_FEED_WW4B1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_EL1BEG3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_FEED_LH7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_FEED_EE4A0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_FEED_EE4A1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_FEED_NE4C2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_FEED_SE4BEG1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_FEED_LH8", - "INT_INTERFACE_LH8" - ], - [ - "CLK_FEED_EL1BEG0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_FEED_SW4END0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_LOGIC_OUTS14_0", - "INT_INTERFACE_LOGIC_OUTS_B14" - ], - [ - "CLK_FEED_EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_FEED_NW4A1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_PMV_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_FEED_LH11", - "INT_INTERFACE_LH11" - ], - [ - "CLK_FEED_LH9", - "INT_INTERFACE_LH9" - ], - [ - "CLK_FEED_EE4C0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_FEED_SW4A2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_FEED_EE2BEG2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_FEED_EE4BEG2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_FEED_SE2A3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_FEED_WW4B3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_PMV_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_FEED_NW2A1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_FEED_SE4BEG3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_FEED_EE4BEG3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_FEED_ER1BEG1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_PMV_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_FEED_WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_FEED_WW2A1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_FEED_EE2A3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_FEED_NW4A2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_FEED_EE2BEG3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_FEED_WR1END0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_PMV_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_FEED_SE4BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_NE4C1", - "INT_INTERFACE_NE4C1" - ] - ], - "tile_types": [ - "CLK_MTBF2", - "INT_INTERFACE_R" ], - "grid_deltas": [ - -1, - 0 - ] - }, - { "wire_pairs": [ - [ - "BRKH_CLK_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "BRKH_CLK_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "BRKH_CLK_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "BRKH_CLK_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "BRKH_CLK_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "BRKH_CLK_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "BRKH_CLK_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "BRKH_CLK_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "BRKH_CLK_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "BRKH_CLK_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "BRKH_CLK_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "BRKH_CLK_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "BRKH_CLK_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "BRKH_CLK_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "BRKH_CLK_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "BRKH_CLK_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], [ "BRKH_CLK_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "BRKH_CLK_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "BRKH_CLK_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "BRKH_CLK_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "BRKH_CLK_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "BRKH_CLK_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "BRKH_CLK_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "BRKH_CLK_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "BRKH_CLK_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "BRKH_CLK_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC10" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "BRKH_CLK_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" + "CLK_BUFG_CK_GCLK21" ], [ "BRKH_CLK_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "BRKH_CLK_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC19" - ], - [ - "BRKH_CLK_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "BRKH_CLK_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "BRKH_CLK_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "BRKH_CLK_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ] - ], - "tile_types": [ - "BRKH_CLK", - "CLK_FEED" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_NW2A1_2", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_WW2A1_2", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_FAN3_2", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX30_2", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX28_2", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_IMUX23_2", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_IMUX38_2", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_NE4C0_2", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_IMUX6_2", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_IMUX11_2", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_EL1BEG1_2", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_EE4BEG1_2", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_NE4BEG0_2", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_FAN0_2", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_WW4B1_2", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WL1END1_2", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_IMUX26_2", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_EE4BEG3_2", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_ER1BEG3_2", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_EE4C3_2", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_EE4A3_2", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SW4END1_2", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_CLK1_2", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WR1END3_2", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_IMUX19_2", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX34_2", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_BYP7_2", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_WW2A3_2", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_NE4C1_2", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_SW4A0_2", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_NE4BEG1_2", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_IMUX7_2", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_ER1BEG0_2", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_SE2A0_2", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_IMUX41_2", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_IMUX14_2", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_LH8_2", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_IMUX45_2", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SW4A3_2", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NE4C3_2", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX44_2", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_FAN7_2", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_IMUX39_2", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SE4BEG3_2", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NE4BEG2_2", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW4END2_2", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_SE4C3_2", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_BYP2_2", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NW4A0_2", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WL1END2_2", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_WW4C2_2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SW4END0_2", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WW4A2_2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_SE4C1_2", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX10_2", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_IMUX33_2", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_CTRL0_2", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX1_2", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_WW4A1_2", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EL1BEG2_2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX16_2", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW2END3_2", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_IMUX8_2", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_EE2A3_2", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX25_2", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_WW4END0_2", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_CTRL1_2", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_NW4END1_2", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_EL1BEG3_2", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_LH2_2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_EE4C1_2", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_LH7_2", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_SW4END3_2", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_EE4BEG0_2", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_IMUX21_2", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX46_2", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SW2A3_2", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SW2A2_2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_IMUX27_2", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_WL1END3_2", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX31_2", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_IMUX43_2", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_IMUX17_2", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_NW4END0_2", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_NE4C2_2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX0_2", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_IMUX12_2", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SE4BEG1_2", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_FAN2_2", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_NW4A2_2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_IMUX18_2", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_WR1END0_2", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_EE2BEG1_2", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_FAN6_2", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_WW4C3_2", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_SE2A3_2", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_LH12_2", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_BYP3_2", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX2_2", - "INT_INTERFACE_IMUX2" - ], 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"INT_INTERFACE_LH9" - ], - [ - "PCIE_IMUX42_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT42" - ], - [ - "PCIE_LOGIC_OUTS_B2_L_14", - "INT_INTERFACE_LOGIC_OUTS_L_B2" - ], - [ - "PCIE_IMUX36_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT36" - ], - [ - "PCIE_LOGIC_OUTS_B23_L_14", - "INT_INTERFACE_LOGIC_OUTS_L_B23" - ], - [ - "PCIE_LOGIC_OUTS_B12_L_14", - "INT_INTERFACE_LOGIC_OUTS_L_B12" - ], - [ - "PCIE_SE4BEG2_14", - "INT_INTERFACE_SE4BEG2" - ], - [ - "PCIE_EE4A1_14", - "INT_INTERFACE_EE4A1" - ], - [ - "PCIE_EE4C0_14", - "INT_INTERFACE_EE4C0" - ], - [ - "PCIE_LOGIC_OUTS_B21_L_14", - "INT_INTERFACE_LOGIC_OUTS_L_B21" - ], - [ - "PCIE_IMUX41_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT41" - ], - [ - "PCIE_NW2A0_14", - "INT_INTERFACE_NW2A0" - ], - [ - "PCIE_IMUX12_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT12" - ], - [ - "PCIE_EE4B0_14", - "INT_INTERFACE_EE4B0" - ], - [ - "PCIE_SE4BEG1_14", - "INT_INTERFACE_SE4BEG1" - ], - [ - "PCIE_EL1BEG2_14", - "INT_INTERFACE_EL1BEG2" - ], - [ - "PCIE_IMUX19_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT19" - ], - [ - "PCIE_IMUX43_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT43" - ], - [ - "PCIE_SW4A2_14", - "INT_INTERFACE_SW4A2" - ], - [ - "PCIE_LH2_14", - "INT_INTERFACE_LH2" - ], - [ - "PCIE_SW4A0_14", - "INT_INTERFACE_SW4A0" - ], - [ - "PCIE_IMUX1_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT1" - ], - [ - "PCIE_CTRL1_L_14", - "INT_INTERFACE_CTRL1" - ], - [ - "PCIE_LOGIC_OUTS_B11_L_14", - "INT_INTERFACE_LOGIC_OUTS_L_B11" - ], - [ - "PCIE_LOGIC_OUTS_B19_L_14", - "INT_INTERFACE_LOGIC_OUTS_L_B19" - ], - [ - "PCIE_LOGIC_OUTS_B3_L_14", - "INT_INTERFACE_LOGIC_OUTS_L_B3" - ], - [ - "PCIE_IMUX20_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT20" - ], - [ - "PCIE_IMUX26_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT26" - ], - [ - "PCIE_SE4C3_14", - "INT_INTERFACE_SE4C3" - ], - [ - "PCIE_SE4C2_14", - "INT_INTERFACE_SE4C2" - ], - [ - "PCIE_FAN6_L_14", - "INT_INTERFACE_FAN6" - ], - [ - "PCIE_SE2A2_14", - "INT_INTERFACE_SE2A2" - ], - [ - "PCIE_IMUX7_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT7" - ], - [ - "PCIE_WL1END1_14", - "INT_INTERFACE_WL1END1" - ], - [ - "PCIE_IMUX34_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT34" - ], - [ - "PCIE_NE4C2_14", - "INT_INTERFACE_NE4C2" - ], - [ - "PCIE_BYP1_L_14", - "INT_INTERFACE_BYP1" - ], - [ - "PCIE_IMUX44_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT44" - ], - [ - "PCIE_EL1BEG1_14", - "INT_INTERFACE_EL1BEG1" - ], - [ - "PCIE_EE4BEG1_14", - "INT_INTERFACE_EE4BEG1" - ], - [ - "PCIE_IMUX38_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT38" - ], - [ - "PCIE_WL1END2_14", - "INT_INTERFACE_WL1END2" - ], - [ - "PCIE_WW4A2_14", - "INT_INTERFACE_WW4A2" - ], - [ - "PCIE_WW4END0_14", - "INT_INTERFACE_WW4END0" - ], - [ - "PCIE_WW2END1_14", - "INT_INTERFACE_WW2END1" - ], - [ - "PCIE_EE2A1_14", - "INT_INTERFACE_EE2A1" - ], - [ - "PCIE_WW4END1_14", - "INT_INTERFACE_WW4END1" - ], - [ - "PCIE_NE2A2_14", - "INT_INTERFACE_NE2A2" - ], - [ - "PCIE_WW4END2_14", - "INT_INTERFACE_WW4END2" - ], - [ - "PCIE_EE4B1_14", - "INT_INTERFACE_EE4B1" - ], - [ - "PCIE_IMUX9_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT9" - ], - [ - "PCIE_WL1END3_14", - "INT_INTERFACE_WL1END3" - ], - [ - "PCIE_IMUX10_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT10" - ], - [ - "PCIE_IMUX23_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT23" - ], - [ - "PCIE_NE2A1_14", - "INT_INTERFACE_NE2A1" - ], - [ - "PCIE_SW2A0_14", - "INT_INTERFACE_SW2A0" - ], - [ - "PCIE_LH5_14", - "INT_INTERFACE_LH5" - ], - [ - "PCIE_NE4BEG2_14", - "INT_INTERFACE_NE4BEG2" - ], - [ - "PCIE_FAN7_L_14", - "INT_INTERFACE_FAN7" - ], - [ - "PCIE_NW2A1_14", - "INT_INTERFACE_NW2A1" - ], - [ - "PCIE_SW2A3_14", - "INT_INTERFACE_SW2A3" - ], - [ - "PCIE_LOGIC_OUTS_B17_L_14", - "INT_INTERFACE_LOGIC_OUTS_L_B17" - ], - [ - "PCIE_FAN4_L_14", - "INT_INTERFACE_FAN4" - ], - [ - "PCIE_CTRL0_L_14", - "INT_INTERFACE_CTRL0" - ], - [ - "PCIE_NW4END3_14", - "INT_INTERFACE_NW4END3" - ], - [ - "PCIE_IMUX16_L_14", - "PCIE_INT_INTERFACE_IMUX_L_OUT16" - ] - ], - "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_L" - ], - "grid_deltas": [ - 5, - -4 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" - ], - [ - "BRAM_FIFO36_CASCADEOUTA_1", - "HCLK_BRAM_CASCADEA_R" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" - ], - [ - "BRAM_FIFO36_CASCADEOUTB_1", - "HCLK_BRAM_CASCADEB_R" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU13", - 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- ], - [ - "GTPE2_IMUX17_0", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX4_0", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX12_0", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX35_0", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_CTRL0_0", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_BYP7_0", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_FAN1_0", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_CTRL1_0", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX26_0", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B12_0", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_BYP4_0", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_FAN3_0", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX22_0", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX11_0", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_FAN6_0", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_FAN4_0", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX0_0", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX47_0", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX9_0", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_LOGIC_OUTS_B14_0", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX23_0", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX16_0", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX14_0", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX20_0", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX41_0", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX5_0", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX7_0", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX2_0", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX1_0", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_BYP0_0", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX37_0", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_LOGIC_OUTS_B20_0", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_IMUX21_0", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_LOGIC_OUTS_B9_0", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_BYP5_0", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX6_0", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_LOGIC_OUTS_B15_0", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_LOGIC_OUTS_B16_0", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_IMUX32_0", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX18_0", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_BYP2_0", - "VBRK_EXT_BYP2" - ] - ], - "tile_types": [ - "GTP_CHANNEL_1", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - 5 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRAM_CASCOUT_ADDRARDADDRU6" - ], - [ - "BRAM_PMVBRAM_ODIV2", - "BRAM_PMVBRAM_ODIV2_1" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRAM_CASCOUT_ADDRBWRADDRU10" - ], - [ - "BRAM_PMVBRAM_O", - "BRAM_PMVBRAM_O_1" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRAM_CASCOUT_ADDRARDADDRU12" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRAM_CASCOUT_ADDRBWRADDRU11" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRAM_CASCOUT_ADDRARDADDRU8" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRAM_CASCOUT_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRAM_CASCOUT_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRAM_CASCOUT_ADDRARDADDRU2" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRAM_CASCOUT_ADDRARDADDRU0" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU11" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRAM_CASCOUT_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRAM_CASCOUT_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRAM_CASCOUT_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRAM_CASCOUT_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRAM_CASCOUT_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRAM_CASCOUT_ADDRBWRADDRU8" - ], - [ - "BRAM_PMVBRAM_O_1", - "BRAM_PMVBRAM_O_2" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRARDADDRU7" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRAM_CASCOUT_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRAM_CASCOUT_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRAM_CASCOUT_ADDRARDADDRU3" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRAM_CASCOUT_ADDRARDADDRU10" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRAM_CASCOUT_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRAM_CASCOUT_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRAM_CASCOUT_ADDRARDADDRU5" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRAM_CASCOUT_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRAM_CASCOUT_ADDRBWRADDRU4" - ] - ], - "tile_types": [ - "BRAM_L", - "BRAM_L" - ], - "grid_deltas": [ - 0, - -5 - ] - }, - { - "wire_pairs": [ - [ - "CLBLM_SE2A0", - "SE2END0" - ], - [ - "CLBLM_IMUX16", - "IMUX_L16" - ], - [ - "CLBLM_EE2A2", - "EE2END2" - ], - [ - "CLBLM_IMUX9", - "IMUX_L9" - ], - [ - "CLBLM_EE2BEG2", - "EE2A2" - ], - [ - "CLBLM_NE4C3", - "NE6END3" - ], - [ - "CLBLM_IMUX41", - "IMUX_L41" - ], - [ - "CLBLM_NW4END2", - "NW6E2" - ], - [ - "CLBLM_IMUX21", - "IMUX_L21" - ], - [ - "CLBLM_WR1END2", - "WR1BEG2" - ], - [ - "CLBLM_IMUX10", - "IMUX_L10" - ], - [ - "CLBLM_ER1BEG2", - "ER1END2" - ], - [ - "CLBLM_WW2A0", - "WW2BEG0" - ], - [ - "CLBLM_NE4BEG0", - "NE6A0" - ], - [ - "CLBLM_IMUX15", - "IMUX_L15" - ], - [ - "CLBLM_BYP6", - "BYP_L6" - ], - [ - "CLBLM_IMUX40", - "IMUX_L40" - ], - [ - "CLBLM_SE4C1", - "SE6END1" - ], - [ - "CLBLM_NE4BEG3", - "NE6A3" - ], - [ - "CLBLM_SW4A0", - "SW6BEG0" - ], - [ - "CLBLM_CLK0", - "CLK_L0" - ], - [ - "CLBLM_NE2A1", - "NE2END1" - ], - [ - "CLBLM_SE4BEG0", - "SE6A0" - ], - [ - "CLBLM_EE2BEG0", - "EE2A0" - ], - [ - "CLBLM_SW4A2", - "SW6BEG2" - ], - [ - "CLBLM_IMUX8", - "IMUX_L8" - ], - [ - "CLBLM_IMUX4", - "IMUX_L4" - ], - [ - "CLBLM_WW2A3", - "WW2BEG3" - ], - [ - "CLBLM_WW2END1", - "WW2A1" - ], - [ - "CLBLM_IMUX43", - "IMUX_L43" - ], - [ - "CLBLM_WW4A2", - "WW4BEG2" - ], - [ - "CLBLM_IMUX6", - "IMUX_L6" - ], - [ - "CLBLM_WW4A1", - "WW4BEG1" - ], - [ - "CLBLM_IMUX32", - "IMUX_L32" - ], - [ - "CLBLM_BYP3", - "BYP_L3" - ], - [ - "CLBLM_ER1BEG0", - "ER1END0" - ], - [ - "CLBLM_IMUX30", - "IMUX_L30" - ], - [ - "CLBLM_WW4END0", - "WW4C0" - ], - [ - "CLBLM_NE4BEG1", - "NE6A1" - ], - [ - "CLBLM_SE2A3", - "SE2END3" - ], - [ - "CLBLM_LOGIC_OUTS3", - "LOGIC_OUTS_L3" - ], - [ - "CLBLM_IMUX26", - "IMUX_L26" - ], - [ - "CLBLM_LOGIC_OUTS9", - "LOGIC_OUTS_L9" - ], - [ - "CLBLM_IMUX18", - "IMUX_L18" - ], - [ - "CLBLM_IMUX23", - "IMUX_L23" - ], - [ - "CLBLM_IMUX35", - "IMUX_L35" - ], - [ - "CLBLM_IMUX19", - "IMUX_L19" - ], - [ - "CLBLM_IMUX13", - "IMUX_L13" - ], - [ - "CLBLM_CTRL1", - "CTRL_L1" - ], - [ - "CLBLM_EL1BEG3", - "EL1END3" - ], - [ - "CLBLM_LOGIC_OUTS22", - "LOGIC_OUTS_L22" - ], - [ - "CLBLM_WR1END0", - "WR1BEG0" - ], - [ - "CLBLM_IMUX2", - "IMUX_L2" - ], - [ - "CLBLM_WL1END3", - "WL1BEG3" - ], - [ - "CLBLM_SW2A3", - "SW2A3" - ], - [ - "CLBLM_LH2", - "LH1" - ], - [ - "CLBLM_EE4A2", - "EE4B2" - ], - [ - "CLBLM_IMUX33", - "IMUX_L33" - ], - [ - "CLBLM_IMUX20", - "IMUX_L20" - ], - [ - "CLBLM_FAN5", - "FAN_L5" - ], - [ - "CLBLM_CTRL0", - "CTRL_L0" - ], - [ - "CLBLM_WW2END3", - "WW2A3" - ], - [ - "CLBLM_LH7", - "LH6" - ], - [ - "CLBLM_EL1BEG0", - "EL1END0" - ], - [ - "CLBLM_LOGIC_OUTS5", - "LOGIC_OUTS_L5" - ], - [ - "CLBLM_LOGIC_OUTS6", - "LOGIC_OUTS_L6" - ], - [ - "CLBLM_IMUX14", - "IMUX_L14" - ], - [ - "CLBLM_NW4A1", - "NW6BEG1" - ], - [ - "CLBLM_WW2END2", - "WW2A2" - ], - [ - "CLBLM_IMUX11", - "IMUX_L11" - ], - [ - "CLBLM_IMUX38", - "IMUX_L38" - ], - [ - "CLBLM_IMUX5", - "IMUX_L5" - ], - [ - "CLBLM_IMUX39", - "IMUX_L39" - ], - [ - "CLBLM_LOGIC_OUTS20", - "LOGIC_OUTS_L20" - ], - [ - "CLBLM_EE4B3", - "EE4C3" - ], - [ - "CLBLM_EE4A1", - "EE4B1" - ], - [ - "CLBLM_NW2A1", - "NW2A1" - ], - [ - "CLBLM_NE2A0", - "NE2END0" - ], - [ - "CLBLM_SE4C2", - "SE6END2" - ], - [ - "CLBLM_LOGIC_OUTS8", - "LOGIC_OUTS_L8" - ], - [ - "CLBLM_IMUX17", - "IMUX_L17" - ], - [ - "CLBLM_LH10", - "LH9" - ], - [ - "CLBLM_EE2A0", - "EE2END0" - ], - [ - "CLBLM_WW4C0", - "WW4B0" - ], - [ - "CLBLM_IMUX28", - "IMUX_L28" - ], - [ - "CLBLM_WR1END3", - "WR1BEG3" - ], - [ - "CLBLM_IMUX12", - "IMUX_L12" - ], - [ - "CLBLM_SW4END0", - "SW6E0" - ], - [ - "CLBLM_WW4END3", - "WW4C3" - ], - [ - "CLBLM_LH1", - "LH0" - ], - [ - "CLBLM_IMUX29", - "IMUX_L29" - ], - [ - "CLBLM_WW4A0", - "WW4BEG0" - ], - [ - "CLBLM_NE2A2", - "NE2END2" - ], - [ - "CLBLM_SW2A0", - "SW2A0" - ], - [ - "CLBLM_SW2A1", - "SW2A1" - ], - [ - "CLBLM_FAN1", - "FAN_L1" - ], - [ - "CLBLM_EE4B2", - "EE4C2" - ], - [ - "CLBLM_IMUX24", - "IMUX_L24" - ], - [ - "CLBLM_IMUX34", - "IMUX_L34" - ], - [ - "CLBLM_LOGIC_OUTS0", - "LOGIC_OUTS_L0" - ], - [ - "CLBLM_WW4C2", - "WW4B2" - ], - [ - "CLBLM_FAN6", - "FAN_L6" - ], - [ - "CLBLM_WW4C3", - "WW4B3" - ], - [ - "CLBLM_LOGIC_OUTS15", - "LOGIC_OUTS_L15" - ], - [ - "CLBLM_MONITOR_N", - "MONITOR_N" - ], - [ - "CLBLM_SE2A2", - "SE2END2" - ], - [ - "CLBLM_MONITOR_P", - "MONITOR_P" - ], - [ - "CLBLM_NW4A0", - "NW6BEG0" - ], - [ - "CLBLM_NW4A2", - "NW6BEG2" - ], - [ - "CLBLM_WW4B1", - "WW4A1" - ], - [ - "CLBLM_CLK1", - "CLK_L1" - ], - [ - "CLBLM_BYP1", - "BYP_L1" - ], - [ - "CLBLM_NE4BEG2", - "NE6A2" - ], - [ - "CLBLM_SW4END2", - "SW6E2" - ], - [ - "CLBLM_EE4C3", - "EE4END3" - ], - [ - "CLBLM_EE2A1", - "EE2END1" - ], - [ - "CLBLM_IMUX44", - "IMUX_L44" - ], - [ - "CLBLM_FAN2", - "FAN_L2" - ], - [ - "CLBLM_SW4END3", - "SW6E3" - ], - [ - "CLBLM_NW2A2", - "NW2A2" - ], - [ - "CLBLM_BYP2", - "BYP_L2" - ], - [ - "CLBLM_SE2A1", - "SE2END1" - ], - [ - "CLBLM_LH3", - "LH2" - ], - [ - "CLBLM_LH9", - "LH8" - ], - [ - "CLBLM_LOGIC_OUTS13", - "LOGIC_OUTS_L13" - ], - [ - "CLBLM_WW4A3", - "WW4BEG3" - ], - [ - "CLBLM_IMUX1", - "IMUX_L1" - ], - [ - "CLBLM_WW2A2", - "WW2BEG2" - ], - [ - "CLBLM_FAN4", - "FAN_L4" - ], - [ - "CLBLM_NW2A0", - "NW2A0" - ], - [ - "CLBLM_LH8", - "LH7" - ], - [ - "CLBLM_WL1END2", - "WL1BEG2" - ], - [ - "CLBLM_EE2BEG3", - "EE2A3" - ], - [ - "CLBLM_SW4A1", - "SW6BEG1" - ], - [ - "CLBLM_NE2A3", - "NE2END3" - ], - [ - "CLBLM_LOGIC_OUTS2", - "LOGIC_OUTS_L2" - ], - [ - "CLBLM_IMUX27", - "IMUX_L27" - ], - [ - "CLBLM_IMUX47", - "IMUX_L47" - ], - [ - "CLBLM_LOGIC_OUTS1", - "LOGIC_OUTS_L1" - ], - [ - "CLBLM_ER1BEG1", - "ER1END1" - ], - [ - "CLBLM_LOGIC_OUTS7", - "LOGIC_OUTS_L7" - ], - [ - "CLBLM_LH5", - "LH4" - ], - [ - "CLBLM_LOGIC_OUTS10", - "LOGIC_OUTS_L10" - ], - [ - "CLBLM_EL1BEG1", - "EL1END1" - ], - [ - "CLBLM_IMUX46", - "IMUX_L46" - ], - [ - "CLBLM_EE4C2", - "EE4END2" - ], - [ - "CLBLM_EE4BEG3", - "EE4A3" - ], - [ - "CLBLM_EE4A3", - "EE4B3" - ], - [ - "CLBLM_FAN0", - "FAN_L0" - ], - [ - "CLBLM_SE4BEG3", - "SE6A3" - ], - [ - "CLBLM_NW4END0", - "NW6E0" - ], - [ - "CLBLM_LH12", - "LH11" - ], - [ - "CLBLM_WL1END0", - "WL1BEG0" - ], - [ - "CLBLM_SE4C0", - "SE6END0" - ], - [ - "CLBLM_LOGIC_OUTS4", - "LOGIC_OUTS_L4" - ], - [ - "CLBLM_IMUX36", - "IMUX_L36" - ], - [ - "CLBLM_EE4C0", - "EE4END0" - ], - [ - "CLBLM_LOGIC_OUTS17", - "LOGIC_OUTS_L17" - ], - [ - "CLBLM_NW4END3", - "NW6E3" - ], - [ - "CLBLM_LOGIC_OUTS19", - "LOGIC_OUTS_L19" - ], - [ - "CLBLM_SE4BEG2", - "SE6A2" - ], - [ - "CLBLM_LOGIC_OUTS18", - "LOGIC_OUTS_L18" - ], - [ - "CLBLM_BYP4", - "BYP_L4" - ], - [ - "CLBLM_WW4END2", - "WW4C2" - ], - [ - "CLBLM_FAN7", - "FAN_L7" - ], - [ - "CLBLM_EE4A0", - "EE4B0" - ], - [ - "CLBLM_LH6", - "LH5" - ], - [ - "CLBLM_NW4A3", - "NW6BEG3" - ], - [ - "CLBLM_EE4B1", - "EE4C1" - ], - [ - "CLBLM_SW4END1", - "SW6E1" - ], - [ - "CLBLM_LH4", - "LH3" - ], - [ - "CLBLM_LOGIC_OUTS16", - "LOGIC_OUTS_L16" - ], - [ - "CLBLM_WW4B3", - "WW4A3" - ], - [ - "CLBLM_LOGIC_OUTS11", - "LOGIC_OUTS_L11" - ], - [ - "CLBLM_IMUX45", - "IMUX_L45" - ], - [ - "CLBLM_IMUX22", - "IMUX_L22" - ], - [ - "CLBLM_WW4END1", - "WW4C1" - ], - [ - "CLBLM_NE4C2", - "NE6END2" - ], - [ - "CLBLM_LOGIC_OUTS21", - "LOGIC_OUTS_L21" - ], - [ - "CLBLM_WW4C1", - "WW4B1" - ], - [ - "CLBLM_IMUX0", - "IMUX_L0" - ], - [ - "CLBLM_LOGIC_OUTS23", - "LOGIC_OUTS_L23" - ], - [ - "CLBLM_EE4BEG2", - "EE4A2" - ], - [ - "CLBLM_EE4BEG1", - "EE4A1" - ], - [ - "CLBLM_IMUX3", - "IMUX_L3" - ], - [ - "CLBLM_SE4BEG1", - "SE6A1" - ], - [ - "CLBLM_EE4B0", - "EE4C0" - ], - [ - "CLBLM_EL1BEG2", - "EL1END2" - ], - [ - "CLBLM_NW4END1", - "NW6E1" - ], - [ - "CLBLM_IMUX31", - "IMUX_L31" - ], - [ - "CLBLM_IMUX37", - "IMUX_L37" - ], - [ - "CLBLM_WW4B0", - "WW4A0" - ], - [ - "CLBLM_NW2A3", - "NW2A3" - ], - [ - "CLBLM_BYP5", - "BYP_L5" - ], - [ - "CLBLM_IMUX42", - "IMUX_L42" - ], - [ - "CLBLM_EE4C1", - "EE4END1" - ], - [ - "CLBLM_NE4C0", - "NE6END0" - ], - [ - "CLBLM_FAN3", - "FAN_L3" - ], - [ - "CLBLM_BYP7", - "BYP_L7" - ], - [ - "CLBLM_EE2A3", - "EE2END3" - ], - [ - "CLBLM_SW2A2", - "SW2A2" - ], - [ - "CLBLM_WW4B2", - "WW4A2" - ], - [ - "CLBLM_EE4BEG0", - "EE4A0" - ], - [ - "CLBLM_IMUX25", - "IMUX_L25" - ], - [ - "CLBLM_NE4C1", - "NE6END1" - ], - [ - "CLBLM_EE2BEG1", - "EE2A1" - ], - [ - "CLBLM_ER1BEG3", - "ER1END3" - ], - [ - "CLBLM_LOGIC_OUTS14", - "LOGIC_OUTS_L14" - ], - [ - "CLBLM_SE4C3", - "SE6END3" - ], - [ - "CLBLM_LOGIC_OUTS12", - "LOGIC_OUTS_L12" - ], - [ - "CLBLM_WL1END1", - "WL1BEG1" - ], - [ - "CLBLM_WW2END0", - "WW2A0" - ], - [ - "CLBLM_LH11", - "LH10" - ], - [ - "CLBLM_SW4A3", - "SW6BEG3" - ], - [ - "CLBLM_WR1END1", - "WR1BEG1" - ], - [ - "CLBLM_IMUX7", - "IMUX_L7" - ], - [ - "CLBLM_BYP0", - "BYP_L0" - ], - [ - "CLBLM_WW2A1", - "WW2BEG1" - ] - ], - "tile_types": [ - "CLBLM_L", - "INT_L" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "IOI_IMUX29_1", - "TERM_INT_IMUX29" - ], - [ - "IOI_FAN3_1", - "TERM_INT_FAN3" - ], - [ - "IOI_BYP0_1", - "TERM_INT_BYP0" - ], - [ - "IOI_FAN0_1", - "TERM_INT_FAN0" - ], - [ - "IOI_LOGIC_OUTS18_1", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "IOI_IMUX23_1", - "TERM_INT_IMUX23" - ], - [ - "IOI_IMUX17_1", - "TERM_INT_IMUX17" - ], - [ - "IOI_IMUX20_1", - "TERM_INT_IMUX20" - ], - [ - "IOI_LOGIC_OUTS0_1", - "TERM_INT_LOGIC_OUTS_L_B0" - ], - [ - "IOI_IMUX36_1", - "TERM_INT_IMUX36" - ], - [ - "IOI_PHASER_TO_IO_ICLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" - ], - [ - "IOI_IMUX1_1", - "TERM_INT_IMUX1" - ], - [ - "IOI_IMUX24_1", - "TERM_INT_IMUX24" - ], - [ - "IOI_FAN1_1", - "TERM_INT_FAN1" - ], - [ - "IOI_PHASER_TO_IO_OCLK_0", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_LOGIC_OUTS15_1", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_IMUX40_1", - "TERM_INT_IMUX40" - ], - [ - "IOI_IMUX27_1", - "TERM_INT_IMUX27" - ], - [ - "IOI_IMUX8_1", - "TERM_INT_IMUX8" - ], - [ - "IOI_LOGIC_OUTS11_1", - "TERM_INT_LOGIC_OUTS_L_B11" - ], - [ - "IOI_IMUX11_1", - "TERM_INT_IMUX11" - ], - [ - "IOI_IMUX31_1", - "TERM_INT_IMUX31" - ], - [ - "IOI_BYP1_1", - "TERM_INT_BYP1" - ], - [ - "IOI_PHASER_TO_IO_ICLK_0", - "L_TERM_INT_PHASER_TO_IO_ICLK" - ], - [ - "IOI_IMUX45_1", - "TERM_INT_IMUX45" - ], - [ - "IOI_IMUX15_1", - "TERM_INT_IMUX15" - ], - [ - "IOI_CLK0_1", - "TERM_INT_CLK0" - ], - [ - "IOI_BYP3_1", - "TERM_INT_BYP3" - ], - [ - "IOI_FAN2_1", - "TERM_INT_FAN2" - ], - [ - "IOI_LOGIC_OUTS14_1", - "TERM_INT_LOGIC_OUTS_L_B14" - ], - [ - "IOI_LOGIC_OUTS22_1", - "TERM_INT_LOGIC_OUTS_L_B22" - ], - [ - "IOI_LOGIC_OUTS19_1", - "TERM_INT_LOGIC_OUTS_L_B19" - ], - [ - "IOI_IMUX37_1", - "TERM_INT_IMUX37" - ], - [ - "IOI_IMUX35_1", - "TERM_INT_IMUX35" - ], - [ - "IOI_IMUX33_1", - "TERM_INT_IMUX33" - ], - [ - "IOI_LOGIC_OUTS9_1", - "TERM_INT_LOGIC_OUTS_L_B9" - ], - [ - "IOI_BYP5_1", - "TERM_INT_BYP5" - ], - [ - "IOI_BYP6_1", - "TERM_INT_BYP6" - ], - [ - "IOI_IMUX38_1", - "TERM_INT_IMUX38" - ], - [ - "IOI_CLK1_1", - "TERM_INT_CLK1" - ], - [ - "IOI_IMUX16_1", - "TERM_INT_IMUX16" - ], - [ - "IOI_IMUX0_1", - "TERM_INT_IMUX0" - ], - [ - "IOI_IMUX5_1", - "TERM_INT_IMUX5" - ], - [ - "IOI_IMUX43_1", - "TERM_INT_IMUX43" - ], - [ - "IOI_IMUX2_1", - "TERM_INT_IMUX2" - ], - [ - "IOI_LOGIC_OUTS10_1", - "TERM_INT_LOGIC_OUTS_L_B10" - ], - [ - "IOI_LOGIC_OUTS13_1", - "TERM_INT_LOGIC_OUTS_L_B13" - ], - [ - "IOI_IMUX21_1", - "TERM_INT_IMUX21" - ], - [ - "IOI_IMUX39_1", - "TERM_INT_IMUX39" - ], - [ - "IOI_BYP7_1", - "TERM_INT_BYP7" - ], - [ - "IOI_LOGIC_OUTS3_1", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_IMUX41_1", - "TERM_INT_IMUX41" - ], - [ - "IOI_LOGIC_OUTS7_1", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_IMUX14_1", - "TERM_INT_IMUX14" - ], - [ - "IOI_CTRL0_1", - "TERM_INT_CTRL0" - ], - [ - "IOI_IMUX6_1", - "TERM_INT_IMUX6" - ], - [ - "IOI_IMUX44_1", - "TERM_INT_IMUX44" - ], - [ - "IOI_LOGIC_OUTS20_1", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_IMUX12_1", - "TERM_INT_IMUX12" - ], - [ - "IOI_LOGIC_OUTS16_1", - "TERM_INT_LOGIC_OUTS_L_B16" - ], - [ - "IOI_BYP4_1", - "TERM_INT_BYP4" - ], - [ - "IOI_IMUX47_1", - "TERM_INT_IMUX47" - ], - [ - "IOI_BLOCK_OUTS2_1", - "TERM_INT_BLOCK_OUTS_L_B2" - ], - [ - "IOI_LOGIC_OUTS1_1", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_CTRL1_1", - "TERM_INT_CTRL1" - ], - [ - "IOI_IMUX13_1", - "TERM_INT_IMUX13" - ], - [ - "IOI_IMUX42_1", - "TERM_INT_IMUX42" - ], - [ - "IOI_IMUX4_1", - "TERM_INT_IMUX4" - ], - [ - "IOI_IMUX30_1", - "TERM_INT_IMUX30" - ], - [ - "IOI_IMUX10_1", - "TERM_INT_IMUX10" - ], - [ - "IOI_IMUX3_1", - "TERM_INT_IMUX3" - ], - [ - "IOI_IMUX34_1", - "TERM_INT_IMUX34" - ], - [ - "IOI_IMUX18_1", - "TERM_INT_IMUX18" - ], - [ - "IOI_IMUX19_1", - "TERM_INT_IMUX19" - ], - [ - "IOI_IMUX22_1", - "TERM_INT_IMUX22" - ], - [ - "IOI_IMUX7_1", - "TERM_INT_IMUX7" - ], - [ - "IOI_BYP2_1", - "TERM_INT_BYP2" - ], - [ - "IOI_FAN4_1", - "TERM_INT_FAN4" - ], - [ - "IOI_IMUX25_1", - "TERM_INT_IMUX25" - ], - [ - "IOI_LOGIC_OUTS2_1", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "IOI_FAN7_1", - "TERM_INT_FAN7" - ], - [ - "IOI_LOGIC_OUTS8_1", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_IMUX9_1", - "TERM_INT_IMUX9" - ], - [ - "IOI_IMUX46_1", - "TERM_INT_IMUX46" - ], - [ - "IOI_FAN6_1", - "TERM_INT_FAN6" - ], - [ - "IOI_FAN5_1", - "TERM_INT_FAN5" - ], - [ - "IOI_IMUX26_1", - "TERM_INT_IMUX26" - ], - [ - "IOI_LOGIC_OUTS5_1", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_IMUX32_1", - "TERM_INT_IMUX32" - ], - [ - "IOI_PHASER_TO_IO_OCLKDIV_0", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ], - [ - "IOI_IMUX28_1", - "TERM_INT_IMUX28" - ], - [ - "IOI_LOGIC_OUTS23_1", - "TERM_INT_LOGIC_OUTS_L_B23" - ], - [ - "IOI_BLOCK_OUTS0_1", - "TERM_INT_BLOCK_OUTS_L_B0" - ] - ], - "tile_types": [ - "RIOI3", - "R_TERM_INT" - ], - "grid_deltas": [ - -1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO0" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_HROW_TOP_R_CK_BUFG_CASCO19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_HROW_TOP_R_CK_BUFG_CASCO14" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_HROW_TOP_R_CK_BUFG_CASCO17" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_HROW_TOP_R_CK_BUFG_CASCO26" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_HROW_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_HROW_TOP_R_CK_BUFG_CASCO16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_HROW_TOP_R_CK_BUFG_CASCO20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_HROW_TOP_R_CK_BUFG_CASCO24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_HROW_TOP_R_CK_BUFG_CASCO29" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_HROW_TOP_R_CK_BUFG_CASCO18" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_HROW_TOP_R_CK_BUFG_CASCO8" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_HROW_TOP_R_CK_BUFG_CASCO10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_HROW_TOP_R_CK_BUFG_CASCO4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_HROW_TOP_R_CK_BUFG_CASCO15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_HROW_TOP_R_CK_BUFG_CASCO2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_HROW_TOP_R_CK_BUFG_CASCO25" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_HROW_TOP_R_CK_BUFG_CASCO28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_HROW_TOP_R_CK_BUFG_CASCO31" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_HROW_TOP_R_CK_BUFG_CASCO13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_HROW_TOP_R_CK_BUFG_CASCO11" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_HROW_TOP_R_CK_BUFG_CASCO3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_HROW_TOP_R_CK_BUFG_CASCO6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_HROW_TOP_R_CK_BUFG_CASCO22" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_HROW_TOP_R_CK_BUFG_CASCO23" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_HROW_TOP_R_CK_BUFG_CASCO12" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - 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"CLK_BUFG_REBUF_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "CLK_BUFG_REBUF_LH12_1", - "VBRK_LH12" - ], - [ - "CLK_BUFG_REBUF_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "CLK_BUFG_REBUF_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "CLK_BUFG_REBUF_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "CLK_BUFG_REBUF_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "CLK_BUFG_REBUF_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "CLK_BUFG_REBUF_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "CLK_BUFG_REBUF_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "CLK_BUFG_REBUF_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "CLK_BUFG_REBUF_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "CLK_BUFG_REBUF_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "CLK_BUFG_REBUF_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "CLK_BUFG_REBUF_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "CLK_BUFG_REBUF_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "CLK_BUFG_REBUF_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "CLK_BUFG_REBUF_LH11_1", - "VBRK_LH11" - ], - [ - "CLK_BUFG_REBUF_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "CLK_BUFG_REBUF_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "CLK_BUFG_REBUF_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "CLK_BUFG_REBUF_LH8_1", - "VBRK_LH8" - ], - [ - "CLK_BUFG_REBUF_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "CLK_BUFG_REBUF_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "CLK_BUFG_REBUF_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "CLK_BUFG_REBUF_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "CLK_BUFG_REBUF_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "CLK_BUFG_REBUF_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "CLK_BUFG_REBUF_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "CLK_BUFG_REBUF_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "CLK_BUFG_REBUF_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "CLK_BUFG_REBUF_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "CLK_BUFG_REBUF_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "CLK_BUFG_REBUF_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "CLK_BUFG_REBUF_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "CLK_BUFG_REBUF_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "CLK_BUFG_REBUF_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "CLK_BUFG_REBUF_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "CLK_BUFG_REBUF_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "CLK_BUFG_REBUF_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "CLK_BUFG_REBUF_LH5_1", - "VBRK_LH5" - ], - [ - "CLK_BUFG_REBUF_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "CLK_BUFG_REBUF_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "CLK_BUFG_REBUF_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "CLK_BUFG_REBUF_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "CLK_BUFG_REBUF_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "CLK_BUFG_REBUF_WW4A2_1", - "VBRK_WW4A2" - ] - ], - "tile_types": [ - "CLK_BUFG_REBUF", - "VBRK" - ], - "grid_deltas": [ - 1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_NE4BEG0_1", - "CLBLM_NE4BEG0" - ], - [ - "BRAM_SE4C0_1", - "CLBLM_SE4C0" - ], - [ - "BRAM_SW4END3_1", - "CLBLM_SW4END3" - ], - [ - "BRAM_EL1BEG2_1", - "CLBLM_EL1BEG2" - ], - [ - "BRAM_WL1END1_1", - "CLBLM_WL1END1" - ], - [ - "BRAM_NW4END1_1", - "CLBLM_NW4END1" - ], - [ - "BRAM_SW2A3_1", - "CLBLM_SW2A3" - ], - [ - "BRAM_SW4A1_1", - "CLBLM_SW4A1" - ], - [ - "BRAM_SE4BEG1_1", - "CLBLM_SE4BEG1" - ], - [ - "BRAM_LH11_1", - "CLBLM_LH11" - ], - [ - "BRAM_WW4C3_1", - "CLBLM_WW4C3" - ], - [ - "BRAM_WW4C2_1", - "CLBLM_WW4C2" - ], - [ - "BRAM_SW4END0_1", - "CLBLM_SW4END0" - ], - [ - "BRAM_EE4C3_1", - "CLBLM_EE4C3" - ], - [ - "BRAM_WW4A3_1", - "CLBLM_WW4A3" - ], - [ - "BRAM_EE2BEG3_1", - "CLBLM_EE2BEG3" - ], - [ - "BRAM_SE4C3_1", - "CLBLM_SE4C3" - ], - [ - "BRAM_WW4END1_1", - "CLBLM_WW4END1" - ], - [ - "BRAM_WW4B2_1", - "CLBLM_WW4B2" - ], - [ - "BRAM_WR1END2_1", - "CLBLM_WR1END2" - ], - [ - "BRAM_LH9_1", - "CLBLM_LH9" - ], - [ - "BRAM_WW4END0_1", - "CLBLM_WW4END0" - ], - [ - "BRAM_WW2END0_1", - "CLBLM_WW2END0" - ], - [ - "BRAM_EE4B0_1", - "CLBLM_EE4B0" - ], - [ - "BRAM_NE4BEG1_1", - "CLBLM_NE4BEG1" - ], - [ - "BRAM_SW4A2_1", - "CLBLM_SW4A2" - ], - [ - "BRAM_NW4A3_1", - "CLBLM_NW4A3" - ], - [ - "BRAM_EE4B1_1", - "CLBLM_EE4B1" - ], - [ - "BRAM_NW2A3_1", - "CLBLM_NW2A3" - ], - [ - "BRAM_ER1BEG1_1", - "CLBLM_ER1BEG1" - ], - [ - "BRAM_SE4BEG3_1", - "CLBLM_SE4BEG3" - ], - [ - "BRAM_SW4A0_1", - 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"INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_SE4C0_0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_SW4END0_0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_LH9_0", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_WL1END2_0", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_MONITOR_P_0", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_MONITOR_N_0", - "INT_INTERFACE_MONITOR_N" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - 4 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "BRAM_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "BRAM_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "BRAM_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "BRAM_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "BRAM_LH12_2", - "VBRK_LH12" - ], - [ - "BRAM_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "BRAM_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "BRAM_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "BRAM_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "BRAM_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "BRAM_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "BRAM_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "BRAM_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "BRAM_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "BRAM_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "BRAM_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "BRAM_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "BRAM_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "BRAM_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "BRAM_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "BRAM_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "BRAM_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "BRAM_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "BRAM_LH7_2", - "VBRK_LH7" - ], - [ - "BRAM_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "BRAM_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "BRAM_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "BRAM_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "BRAM_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "BRAM_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "BRAM_LH11_2", - "VBRK_LH11" - ], - [ - "BRAM_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "BRAM_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "BRAM_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "BRAM_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "BRAM_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "BRAM_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "BRAM_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "BRAM_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "BRAM_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "BRAM_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "BRAM_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "BRAM_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "BRAM_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "BRAM_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "BRAM_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "BRAM_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "BRAM_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "BRAM_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "BRAM_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "BRAM_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "BRAM_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "BRAM_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "BRAM_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "BRAM_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "BRAM_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "BRAM_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "BRAM_LH6_2", - "VBRK_LH6" - ], - [ - "BRAM_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "BRAM_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "BRAM_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "BRAM_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "BRAM_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "BRAM_LH2_2", - "VBRK_LH2" - ], - [ - "BRAM_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "BRAM_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "BRAM_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "BRAM_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "BRAM_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "BRAM_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "BRAM_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "BRAM_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "BRAM_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "BRAM_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "BRAM_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "BRAM_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "BRAM_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "BRAM_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "BRAM_LH1_2", - "VBRK_LH1" - ], - [ - "BRAM_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "BRAM_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "BRAM_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "BRAM_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "BRAM_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "BRAM_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "BRAM_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "BRAM_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "BRAM_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "BRAM_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "BRAM_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "BRAM_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "BRAM_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "BRAM_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "BRAM_LH5_2", - "VBRK_LH5" - ], - [ - "BRAM_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "BRAM_LH8_2", - "VBRK_LH8" - ], - [ - "BRAM_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "BRAM_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "BRAM_NW4END0_2", - "VBRK_NW4END0" - ], - [ - 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"INT_INTERFACE_WR1END1" - ], - [ - "CLK_FEED_SE2A2", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_FEED_SW4A1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_FEED_WW4END0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_FEED_SW4A0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_FEED_WW2END3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_PMV_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_FEED_EE4BEG0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_PMV_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_FEED_NE4C0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_PMV_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_FEED_NW4END0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_FEED_WL1END3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_FEED_LH2", - "INT_INTERFACE_LH2" - ], - [ - "CLK_FEED_SE4C3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_PMV_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_PMV_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_PMV_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_FEED_NE2A0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_FEED_WW4C3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_LOGIC_OUTS2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_FEED_NE2A2", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_FEED_ER1BEG0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_FEED_SE2A1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_FEED_WW4END1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_FEED_SW2A2", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_FEED_NE4BEG0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_FEED_WW4B0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_FEED_EE2BEG0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_PMV_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - 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"CLK_FEED_EE4B1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_FEED_SE2A0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_FEED_WW4C0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_PMV_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_PMV_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_FEED_EL1BEG2", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_PMV_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_FEED_SE4BEG2", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_PMV_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_FEED_NE4C3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_FEED_SW4A3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_FEED_WW4A2", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_PMV_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_PMV_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - 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"CLK_PMV_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_PMV_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_FEED_WL1END1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_FEED_EL1BEG1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_FEED_WW4A0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_PMV_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_PMV_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_FEED_MONITOR_P", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_FEED_SW4END3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_FEED_ER1BEG2", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_FEED_NW2A3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_FEED_SE4C2", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_FEED_NW4A0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_FEED_LH10", - "INT_INTERFACE_LH10" - ], - [ - "CLK_FEED_NW2A0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_FEED_EE2A0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_FEED_EE2A2", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_PMV_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_FEED_WW4C2", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_FEED_NW4END2", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_FEED_WW2A3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_FEED_SW2A1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_FEED_SW2A0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_PMV_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_FEED_WW2A2", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_FEED_LH1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_PMV_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_FEED_WR1END2", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_PMV_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_FEED_LH4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_PMV_LOGIC_OUTS0_0", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_FEED_WW4C1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_FEED_WW4A1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_PMV_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_PMV_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_FEED_NW4END3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_FEED_NE4BEG3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_PMV_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_FEED_EE2A1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_FEED_EE4A2", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_FEED_NE4BEG1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_PMV_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_FEED_WW4END2", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_FEED_SW2A3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_FEED_WW4B1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_FEED_EE4C3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_FEED_EL1BEG3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_FEED_LH7", - "INT_INTERFACE_LH7" - ], - [ - "CLK_FEED_WW2A0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_FEED_EE4A0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_FEED_EE4A1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_FEED_NE4C2", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_FEED_SE4BEG1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_FEED_LH8", - "INT_INTERFACE_LH8" - ], - [ - "CLK_FEED_EL1BEG0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_FEED_SW4END0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_FEED_NW4A1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_FEED_EE4C1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_FEED_WL1END0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_PMV_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_FEED_LH11", - "INT_INTERFACE_LH11" - ], - [ - "CLK_PMV_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_FEED_LH9", - "INT_INTERFACE_LH9" - ], - [ - "CLK_FEED_EE4C0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_FEED_SW4A2", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_FEED_EE2BEG2", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_FEED_EE4BEG2", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_FEED_SE2A3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_FEED_WW4B3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_PMV_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_FEED_NE2A1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_FEED_NW2A1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_FEED_SE4BEG3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_FEED_ER1BEG3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_FEED_EE4BEG3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_FEED_ER1BEG1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_PMV_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_FEED_WW2END0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_FEED_WW2A1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_FEED_EE2A3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_FEED_NW4A2", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_FEED_EE2BEG3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_FEED_WR1END0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_PMV_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_FEED_SE4BEG0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_FEED_EE4C2", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_FEED_NE4C1", - "INT_INTERFACE_NE4C1" - ] - ], - "tile_types": [ - "CLK_PMVIOB", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "BRAM_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "BRAM_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "BRAM_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "BRAM_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "BRAM_LH9_4", - "VBRK_LH9" - ], - [ - "BRAM_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "BRAM_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "BRAM_EE4C0_4", - "VBRK_EE4C0" - ], - [ - "BRAM_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "BRAM_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "BRAM_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "BRAM_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "BRAM_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "BRAM_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "BRAM_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "BRAM_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "BRAM_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "BRAM_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "BRAM_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "BRAM_LH1_4", - "VBRK_LH1" - ], - [ - "BRAM_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "BRAM_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "BRAM_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "BRAM_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "BRAM_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "BRAM_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "BRAM_LH12_4", - "VBRK_LH12" - ], - [ - "BRAM_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "BRAM_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "BRAM_LH6_4", - "VBRK_LH6" - ], - [ - "BRAM_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "BRAM_LH10_4", - "VBRK_LH10" - ], - [ - "BRAM_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "BRAM_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "BRAM_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "BRAM_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "BRAM_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "BRAM_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "BRAM_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "BRAM_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "BRAM_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "BRAM_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "BRAM_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "BRAM_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "BRAM_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "BRAM_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "BRAM_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "BRAM_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "BRAM_LH2_4", - "VBRK_LH2" - ], - [ - "BRAM_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "BRAM_LH4_4", - "VBRK_LH4" - ], - [ - "BRAM_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "BRAM_LH7_4", - "VBRK_LH7" - ], - [ - "BRAM_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "BRAM_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "BRAM_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "BRAM_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "BRAM_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "BRAM_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "BRAM_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "BRAM_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "BRAM_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "BRAM_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "BRAM_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "BRAM_LH8_4", - "VBRK_LH8" - ], - [ - "BRAM_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "BRAM_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "BRAM_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "BRAM_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "BRAM_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "BRAM_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "BRAM_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "BRAM_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "BRAM_LH5_4", - "VBRK_LH5" - ], - [ - "BRAM_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "BRAM_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "BRAM_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "BRAM_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "BRAM_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "BRAM_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "BRAM_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "BRAM_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "BRAM_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "BRAM_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "BRAM_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "BRAM_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "BRAM_LH3_4", - "VBRK_LH3" - ], - [ - "BRAM_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "BRAM_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "BRAM_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "BRAM_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "BRAM_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "BRAM_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "BRAM_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "BRAM_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "BRAM_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "BRAM_LH11_4", - "VBRK_LH11" - ], - [ - "BRAM_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "BRAM_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "BRAM_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "BRAM_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "BRAM_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "BRAM_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "BRAM_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "BRAM_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "BRAM_SE2A1_4", - "VBRK_SE2A1" - ], - [ - "BRAM_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "BRAM_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "BRAM_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "BRAM_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "BRAM_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "BRAM_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "BRAM_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "BRAM_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "BRAM_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "BRAM_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "BRAM_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "BRAM_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "BRAM_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "BRAM_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "BRAM_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "BRAM_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "BRAM_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "BRAM_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "BRAM_MONITOR_P_4", - "VBRK_MONITOR_P" - ] - ], - "tile_types": [ - "BRAM_L", - "VBRK" - ], - "grid_deltas": [ - -1, - -4 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_DSP_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_DSP_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_DSP_CK_IN9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_DSP_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_DSP_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_DSP_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_DSP_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_DSP_CK_IN3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_DSP_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_DSP_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_DSP_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_DSP_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_DSP_CK_IN0", - "HCLK_VBRK_MUX_CLK0" - ], - [ - "HCLK_DSP_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ] - ], - "tile_types": [ - "HCLK_DSP_R", - "HCLK_VBRK" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "PCIE_CLK0_R_12", - "INT_INTERFACE_CLK0" - ], - [ - "PCIE_NE2A0_12", - "INT_INTERFACE_NE2A0" - ], - [ - "PCIE_LOGIC_OUTS_B12_R_12", - "INT_INTERFACE_LOGIC_OUTS_B12" - ], - [ - "PCIE_IMUX32_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT32" - ], - [ - "PCIE_NW4A2_12", - "INT_INTERFACE_NW4A2" - ], - [ - "PCIE_IMUX41_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT41" - ], - [ - "PCIE_WL1END0_12", - "INT_INTERFACE_WL1END0" - ], - [ - "PCIE_SE4C3_12", - "INT_INTERFACE_SE4C3" - ], - [ - "PCIE_CLK1_R_12", - "INT_INTERFACE_CLK1" - ], - [ - "PCIE_SE4BEG0_12", - "INT_INTERFACE_SE4BEG0" - ], - [ - "PCIE_LOGIC_OUTS_B13_R_12", - "INT_INTERFACE_LOGIC_OUTS_B13" - ], - [ - "PCIE_CTRL0_R_12", - "INT_INTERFACE_CTRL0" - ], - [ - "PCIE_FAN5_R_12", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_LOGIC_OUTS_B10_R_12", - "INT_INTERFACE_LOGIC_OUTS_B10" - ], - [ - "PCIE_LH12_12", - "INT_INTERFACE_LH12" - ], - [ - "PCIE_WW4END3_12", - "INT_INTERFACE_WW4END3" - ], - [ - "PCIE_EE4A0_12", - "INT_INTERFACE_EE4A0" - ], - [ - "PCIE_IMUX29_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT29" - ], - [ - "PCIE_IMUX13_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT13" - ], - [ - "PCIE_EL1BEG0_12", - "INT_INTERFACE_EL1BEG0" - ], - [ - "PCIE_NE4C2_12", - "INT_INTERFACE_NE4C2" - ], - [ - "PCIE_WL1END3_12", - "INT_INTERFACE_WL1END3" - ], - [ - "PCIE_EE4BEG3_12", - "INT_INTERFACE_EE4BEG3" - ], - [ - "PCIE_IMUX47_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT47" - ], - [ - "PCIE_NW4END1_12", - "INT_INTERFACE_NW4END1" - ], - [ - "PCIE_FAN3_R_12", - "INT_INTERFACE_FAN3" - ], - [ - "PCIE_WR1END0_12", - "INT_INTERFACE_WR1END0" - ], - [ - "PCIE_EE2A1_12", - "INT_INTERFACE_EE2A1" - ], - [ - "PCIE_EE4C2_12", - "INT_INTERFACE_EE4C2" - ], - [ - "PCIE_LH1_12", - "INT_INTERFACE_LH1" - ], - [ - "PCIE_SE2A2_12", - "INT_INTERFACE_SE2A2" - ], - [ - "PCIE_EE4B2_12", - "INT_INTERFACE_EE4B2" - ], - [ - "PCIE_IMUX21_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT21" - ], - [ - "PCIE_NW4A0_12", - "INT_INTERFACE_NW4A0" - ], - [ - "PCIE_EE2A2_12", - "INT_INTERFACE_EE2A2" - ], - [ - "PCIE_WW2A2_12", - "INT_INTERFACE_WW2A2" - ], - [ - "PCIE_NW4END3_12", - "INT_INTERFACE_NW4END3" - ], - [ - "PCIE_LH4_12", - "INT_INTERFACE_LH4" - ], - [ - "PCIE_LOGIC_OUTS_B21_R_12", - "INT_INTERFACE_LOGIC_OUTS_B21" - ], - [ - "PCIE_NW2A2_12", - "INT_INTERFACE_NW2A2" - ], - [ - "PCIE_IMUX36_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT36" - ], - [ - "PCIE_LOGIC_OUTS_B0_R_12", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "PCIE_WW4C3_12", - "INT_INTERFACE_WW4C3" - ], - [ - "PCIE_WW2END3_12", - "INT_INTERFACE_WW2END3" - ], - [ - "PCIE_WR1END3_12", - "INT_INTERFACE_WR1END3" - ], - [ - "PCIE_IMUX12_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT12" - ], - [ - "PCIE_LOGIC_OUTS_B23_R_12", - "INT_INTERFACE_LOGIC_OUTS_B23" - ], - [ - "PCIE_LH9_12", - "INT_INTERFACE_LH9" - ], - [ - "PCIE_IMUX5_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT5" - ], - [ - "PCIE_SW4A0_12", - "INT_INTERFACE_SW4A0" - ], - [ - "PCIE_FAN4_R_12", - "INT_INTERFACE_FAN4" - ], - [ - "PCIE_FAN0_R_12", - "INT_INTERFACE_FAN0" - ], - [ - "PCIE_IMUX45_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT45" - ], - [ - "PCIE_WW2A0_12", - "INT_INTERFACE_WW2A0" - ], - [ - "PCIE_ER1BEG0_12", - "INT_INTERFACE_ER1BEG0" - ], - [ - "PCIE_NE4BEG0_12", - "INT_INTERFACE_NE4BEG0" - ], - [ - "PCIE_FAN1_R_12", - "INT_INTERFACE_FAN1" - ], - [ - "PCIE_IMUX27_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT27" - ], - [ - "PCIE_IMUX42_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT42" - ], - [ - "PCIE_IMUX16_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT16" - ], - [ - "PCIE_EE2BEG3_12", - "INT_INTERFACE_EE2BEG3" - ], - [ - "PCIE_LH3_12", - "INT_INTERFACE_LH3" - ], - [ - "PCIE_LOGIC_OUTS_B18_R_12", - "INT_INTERFACE_LOGIC_OUTS_B18" - ], - [ - "PCIE_IMUX25_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT25" - ], - [ - "PCIE_WW2A3_12", - "INT_INTERFACE_WW2A3" - ], - [ - "PCIE_EL1BEG3_12", - "INT_INTERFACE_EL1BEG3" - ], - [ - "PCIE_SE2A1_12", - "INT_INTERFACE_SE2A1" - ], - [ - "PCIE_EE4B3_12", - "INT_INTERFACE_EE4B3" - ], - [ - "PCIE_EE2A0_12", - "INT_INTERFACE_EE2A0" - ], - [ - "PCIE_EE2A3_12", - "INT_INTERFACE_EE2A3" - ], - [ - "PCIE_EE4BEG1_12", - "INT_INTERFACE_EE4BEG1" - ], - [ - "PCIE_SW4A1_12", - "INT_INTERFACE_SW4A1" - ], - [ - "PCIE_LOGIC_OUTS_B1_R_12", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "PCIE_FAN2_R_12", - "INT_INTERFACE_FAN2" - ], - [ - "PCIE_LOGIC_OUTS_B5_R_12", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "PCIE_EE4B0_12", - "INT_INTERFACE_EE4B0" - ], - [ - "PCIE_IMUX10_R_12", - "PCIE_INT_INTERFACE_IMUX_OUT10" - ], - [ - "PCIE_FAN7_R_12", - "INT_INTERFACE_FAN7" - ], - [ - "PCIE_FAN6_R_12", - "INT_INTERFACE_FAN6" - ], - [ - "PCIE_SE4C1_12", - "INT_INTERFACE_SE4C1" - ], - [ - "PCIE_LOGIC_OUTS_B3_R_12", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "PCIE_LOGIC_OUTS_B14_R_12", - "INT_INTERFACE_LOGIC_OUTS_B14" - ], - [ - "PCIE_LOGIC_OUTS_B19_R_12", - "INT_INTERFACE_LOGIC_OUTS_B19" - ], - [ - "PCIE_EE4A3_12", - "INT_INTERFACE_EE4A3" - ], - [ - "PCIE_IMUX23_R_12", - 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"INT_INTERFACE_SE4C1", - "BRAM_SE4C1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B20", - "BRAM_LOGIC_OUTS_B20_3" - ], - [ - "INT_INTERFACE_WL1END0", - "BRAM_WL1END0_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - "BRAM_IMUX47_3" - ], - [ - "INT_INTERFACE_SE2A2", - "BRAM_SE2A2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX11", - "BRAM_IMUX11_UTURN_3" - ], - [ - "INT_INTERFACE_NW4END2", - "BRAM_NW4END2_3" - ], - [ - "INT_INTERFACE_SW4A2", - "BRAM_SW4A2_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX11", - "BRAM_IMUX11_3" - ], - [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_3" - ], - [ - "INT_INTERFACE_NW4END3", - "BRAM_NW4END3_3" - ], - [ - "INT_INTERFACE_FAN5", - "BRAM_FAN5_3" - ], - [ - "INT_INTERFACE_EE4B1", - "BRAM_EE4B1_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX8", - "BRAM_IMUX8_UTURN_3" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_3" - ], - [ - "INT_INTERFACE_FAN2", - "BRAM_FAN2_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_3" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_3" - ], - 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"INT_INTERFACE_LOGIC_OUTS_B12", - "BRAM_LOGIC_OUTS_B12_3" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B3", - "BRAM_LOGIC_OUTS_B3_3" - ], - [ - "INT_INTERFACE_EE2A0", - "BRAM_EE2A0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX1", - "BRAM_IMUX1_UTURN_3" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX17", - "BRAM_IMUX17_3" - ], - [ - "INT_INTERFACE_WW2A2", - "BRAM_WW2A2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX17", - "BRAM_IMUX17_UTURN_3" - ], - [ - "INT_INTERFACE_EE2BEG1", - "BRAM_EE2BEG1_3" - ], - [ - "INT_INTERFACE_MONITOR_P", - "BRAM_MONITOR_P_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX40", - "BRAM_IMUX40_3" - ], - [ - "INT_INTERFACE_NE4BEG0", - "BRAM_NE4BEG0_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX43", - "BRAM_IMUX43_3" - ], - [ - "INT_INTERFACE_EE4BEG0", - "BRAM_EE4BEG0_3" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "BRAM_IMUX44_3" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_3" - ], - [ - "INT_INTERFACE_BYP4", - "BRAM_BYP4_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B7", - "BRAM_LOGIC_OUTS_B7_3" - ], - [ - "INT_INTERFACE_EE4A0", - "BRAM_EE4A0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX44", - "BRAM_IMUX44_UTURN_3" - ], - [ - "INT_INTERFACE_WW4A3", - "BRAM_WW4A3_3" - ], - [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_3" - ], - [ - "INT_INTERFACE_EE4A2", - "BRAM_EE4A2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX38", - "BRAM_IMUX38_UTURN_3" - ], - [ - "INT_INTERFACE_WW4END3", - "BRAM_WW4END3_3" - ], - [ - "INT_INTERFACE_FAN7", - "BRAM_FAN7_3" - ], - [ - "INT_INTERFACE_NW2A1", - "BRAM_NW2A1_3" - ], - [ - "INT_INTERFACE_LH4", - "BRAM_LH4_3" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "BRAM_IMUX38_3" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B23", - "BRAM_LOGIC_OUTS_B23_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX45", - "BRAM_IMUX45_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B18", - "BRAM_LOGIC_OUTS_B18_3" - ], - [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_3" - ], - [ - "INT_INTERFACE_BYP5", - "BRAM_BYP5_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX33", - "BRAM_IMUX33_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_3" - ], - [ - "INT_INTERFACE_SE4C3", - "BRAM_SE4C3_3" - ], - [ - "INT_INTERFACE_ER1BEG3", - "BRAM_ER1BEG3_3" - ], - [ - "INT_INTERFACE_EE4B2", - "BRAM_EE4B2_3" - ], - [ - "INT_INTERFACE_EE4B3", - "BRAM_EE4B3_3" - ], - [ - "INT_INTERFACE_NW4A2", - "BRAM_NW4A2_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX30", - "BRAM_IMUX30_3" - ], - [ - "INT_INTERFACE_LH5", - "BRAM_LH5_3" - ], - [ - "INT_INTERFACE_EE4A3", - "BRAM_EE4A3_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "BRAM_IMUX3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX2", - "BRAM_IMUX2_UTURN_3" - ], - [ - "INT_INTERFACE_SW4END0", - "BRAM_SW4END0_3" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_3" - ], - [ - "INT_INTERFACE_EE2BEG2", - "BRAM_EE2BEG2_3" - ], - [ - "INT_INTERFACE_WR1END3", - "BRAM_WR1END3_3" - ], - [ - "INT_INTERFACE_NE4C2", - "BRAM_NE4C2_3" - ], - [ - "INT_INTERFACE_LH12", - "BRAM_LH12_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "BRAM_IMUX32_3" - ], - [ - "INT_INTERFACE_SW2A3", - "BRAM_SW2A3_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B11", - "BRAM_LOGIC_OUTS_B11_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "BRAM_IMUX8_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX45", - "BRAM_IMUX45_3" - ], - [ - "INT_INTERFACE_NE4C0", - "BRAM_NE4C0_3" - ], - [ - "INT_INTERFACE_WW2END3", - "BRAM_WW2END3_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX20", - "BRAM_IMUX20_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B1", - "BRAM_LOGIC_OUTS_B1_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX37", - "BRAM_IMUX37_UTURN_3" - ], - [ - "INT_INTERFACE_WL1END3", - "BRAM_WL1END3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX19", - "BRAM_IMUX19_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B13", - "BRAM_LOGIC_OUTS_B13_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX14", - "BRAM_IMUX14_UTURN_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B4", - "BRAM_LOGIC_OUTS_B4_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX27", - "BRAM_IMUX27_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX26", - "BRAM_IMUX26_UTURN_3" - ], - [ - "INT_INTERFACE_LH6", - "BRAM_LH6_3" - ], - [ - "INT_INTERFACE_EE2A1", - "BRAM_EE2A1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX0", - "BRAM_IMUX0_3" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX19", - "BRAM_IMUX19_3" - ], - [ - "INT_INTERFACE_EE4BEG2", - "BRAM_EE4BEG2_3" - ], - [ - "INT_INTERFACE_FAN0", - "BRAM_FAN0_3" - ], - [ - "INT_INTERFACE_WW4END2", - "BRAM_WW4END2_3" - ], - [ - "INT_INTERFACE_NW2A3", - "BRAM_NW2A3_3" - ], - [ - "INT_INTERFACE_SW4END2", - "BRAM_SW4END2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX15", - "BRAM_IMUX15_UTURN_3" - ], - [ - "INT_INTERFACE_WW4C0", - "BRAM_WW4C0_3" - ], - [ - "INT_INTERFACE_EE4A1", - "BRAM_EE4A1_3" - ], - [ - "INT_INTERFACE_WW4A1", - "BRAM_WW4A1_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX39", - "BRAM_IMUX39_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX29", - "BRAM_IMUX29_UTURN_3" - ], - [ - "INT_INTERFACE_NE2A2", - "BRAM_NE2A2_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B9", - "BRAM_LOGIC_OUTS_B9_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX35", - "BRAM_IMUX35_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX41", - "BRAM_IMUX41_UTURN_3" - ], - [ - "INT_INTERFACE_SE4C0", - "BRAM_SE4C0_3" - ], - [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_3" - ], - [ - "INT_INTERFACE_EL1BEG0", - "BRAM_EL1BEG0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX28", - "BRAM_IMUX28_UTURN_3" - ], - [ - "INT_INTERFACE_MONITOR_N", - "BRAM_MONITOR_N_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX27", - "BRAM_IMUX27_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "BRAM_IMUX6_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX43", - "BRAM_IMUX43_UTURN_3" - ], - [ - "INT_INTERFACE_FAN4", - "BRAM_FAN4_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B19", - "BRAM_LOGIC_OUTS_B19_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX29", - "BRAM_IMUX29_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "BRAM_IMUX25_3" - ], - [ - "INT_INTERFACE_EE4C3", - "BRAM_EE4C3_3" - ], - [ - "INT_INTERFACE_ER1BEG2", - "BRAM_ER1BEG2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX16", - "BRAM_IMUX16_UTURN_3" - ], - [ - "INT_INTERFACE_CTRL1", - "BRAM_CTRL1_3" - ], - [ - "INT_INTERFACE_SW4A3", - "BRAM_SW4A3_3" - ], - [ - "INT_INTERFACE_FAN6", - "BRAM_FAN6_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B2", - "BRAM_LOGIC_OUTS_B2_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX4", - "BRAM_IMUX4_UTURN_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_3" - ], - [ - "INT_INTERFACE_SE4BEG3", - "BRAM_SE4BEG3_3" - ], - [ - "INT_INTERFACE_SW4A0", - "BRAM_SW4A0_3" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX34", - "BRAM_IMUX34_UTURN_3" - ], - [ - "INT_INTERFACE_NW4A0", - "BRAM_NW4A0_3" - ], - [ - "INT_INTERFACE_ER1BEG1", - "BRAM_ER1BEG1_3" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_3" - ], - [ - "INT_INTERFACE_WW2A3", - "BRAM_WW2A3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX36", - "BRAM_IMUX36_UTURN_3" - ], - [ - "INT_INTERFACE_WL1END2", - "BRAM_WL1END2_3" - ], - [ - "INT_INTERFACE_LH3", - "BRAM_LH3_3" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX25", - "BRAM_IMUX25_UTURN_3" - ] - ], - "tile_types": [ - "BRAM_INT_INTERFACE_R", - "BRAM_R" - ], - "grid_deltas": [ - 1, - 3 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EE2A2_0", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_SE4BEG0_0", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_BYP6_0", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_NW4END2_0", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_SE2A2_0", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_WW2A2_0", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_WW4C3_0", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_WW4END3_0", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_FAN6_0", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_SE2A0_0", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_NE2A3_0", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_IMUX20_0", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_LH1_0", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_EE4A3_0", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX0_0", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_WR1END3_0", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_FAN4_0", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_SE4BEG2_0", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_SW4END2_0", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_NE4BEG0_0", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_FAN1_0", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_NW4A3_0", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_CTRL0_0", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_ER1BEG2_0", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_WW4END1_0", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_WW4C0_0", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_LH6_0", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_EE2A1_0", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_WW2A1_0", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_EE4B0_0", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_SE4C0_0", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_WL1END3_0", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_EE2BEG1_0", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_EE4B1_0", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_NW2A0_0", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_SW4END0_0", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_IMUX4_0", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_WR1END2_0", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_EL1BEG2_0", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_FAN3_0", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_IMUX38_0", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_IMUX5_0", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_IMUX15_0", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_IMUX22_0", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_NE4C1_0", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_EE4BEG2_0", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_LH9_0", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_IMUX32_0", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_WL1END2_0", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_EE4BEG0_0", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_LH7_0", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NW2A1_0", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_BYP7_0", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_NE4C3_0", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_EE4BEG1_0", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE4B3_0", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_LH3_0", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_IMUX39_0", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_EE4A0_0", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_WW2END0_0", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_NW4A0_0", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_MONITOR_P_0", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_IMUX10_0", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_ER1BEG0_0", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_WR1END0_0", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX45_0", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_IMUX3_0", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_IMUX47_0", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_IMUX16_0", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_MONITOR_N_0", - "INT_INTERFACE_MONITOR_N" - ] - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - 4 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EE2BEG0_3", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_NW2A0_3", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW4B2_3", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_IMUX19_3", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_NE4BEG1_3", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_SW4A1_3", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_EE2A0_3", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_SE2A0_3", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_WW2END0_3", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_IMUX12_3", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SW2A2_3", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_BYP3_3", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_IMUX34_3", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_WL1END0_3", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_SW4A0_3", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_IMUX43_3", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_CLK0_3", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_WW4C3_3", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX22_3", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_IMUX2_3", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WW4END2_3", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_FAN6_3", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_EE4C0_3", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_FAN7_3", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_BYP7_3", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_FAN2_3", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_SE2A3_3", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_IMUX7_3", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_WW2A3_3", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_LH9_3", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NW2A2_3", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_EE4C2_3", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_EE4BEG0_3", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_NE4C2_3", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_IMUX13_3", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_ER1BEG2_3", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_IMUX0_3", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_ER1BEG0_3", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_NW2A1_3", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_CTRL1_3", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_IMUX8_3", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_SE2A1_3", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX16_3", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_IMUX14_3", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_WW2END3_3", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE2BEG2_3", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX47_3", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_NE4C1_3", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW4A1_3", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EE4B0_3", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_NE4BEG0_3", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_EE4A1_3", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_IMUX4_3", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_WW4C2_3", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_SE4BEG1_3", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_WW4A2_3", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_IMUX38_3", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_EE4B2_3", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_WW2A2_3", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_IMUX39_3", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_SE4C1_3", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_EL1BEG1_3", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_IMUX9_3", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_SW4END2_3", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EL1BEG0_3", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_WL1END1_3", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_SW2A0_3", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_IMUX6_3", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_IMUX33_3", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_IMUX1_3", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_LH2_3", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_NE4BEG2_3", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_WW4END0_3", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_SE4BEG2_3", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_IMUX30_3", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SW4A3_3", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_WR1END0_3", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_FAN1_3", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_FAN4_3", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_WW4A0_3", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_BYP6_3", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_NW4END1_3", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_IMUX27_3", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_IMUX44_3", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_EE2BEG1_3", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_IMUX37_3", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_IMUX31_3", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_EL1BEG2_3", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_WW2A1_3", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_NW4END0_3", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_NE2A1_3", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_NE2A0_3", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_WW4B1_3", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_EE2A2_3", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_LH3_3", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_IMUX40_3", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_NW4A2_3", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WR1END1_3", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_WW4B0_3", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_NW4A3_3", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_FAN3_3", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_FAN5_3", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_IMUX23_3", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_LH11_3", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_SE4BEG0_3", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_IMUX45_3", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_SE4BEG3_3", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_NW4A1_3", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NE4C0_3", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_BYP1_3", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_EE2A1_3", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_WW4END3_3", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_IMUX21_3", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_EE2A3_3", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_WL1END2_3", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_BYP5_3", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_LH4_3", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_SW4END3_3", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_IMUX26_3", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_IMUX32_3", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_IMUX10_3", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_IMUX20_3", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_IMUX36_3", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_SW4END1_3", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_WW2END2_3", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_CLK1_3", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_IMUX41_3", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_NW2A3_3", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_NW4END2_3", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EE4BEG3_3", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_NE2A3_3", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_SE4C3_3", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_SE4C0_3", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_EL1BEG3_3", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_EE4C3_3", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_SW2A1_3", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_LH1_3", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX28_3", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EE2BEG3_3", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW4END1_3", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_WW4C1_3", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_NE2A2_3", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_SE2A2_3", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_IMUX46_3", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_IMUX18_3", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_IMUX5_3", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX3_3", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_NW4END3_3", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_SW4END0_3", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_LH6_3", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_LH12_3", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WW4C0_3", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_EE4BEG1_3", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE4A3_3", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_IMUX29_3", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_EE4B1_3", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_IMUX35_3", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX11_3", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_LH8_3", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_WW4B3_3", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE4B3_3", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_BYP2_3", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_EE4A0_3", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_SW2A3_3", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_IMUX42_3", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_FAN0_3", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_NE4BEG3_3", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE4C1_3", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_IMUX25_3", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_BYP0_3", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_WW2A0_3", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SE4C2_3", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_WW2END1_3", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_NW4A0_3", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_IMUX24_3", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WR1END2_3", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_EE4A2_3", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_LH7_3", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_LH10_3", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WR1END3_3", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_NE4C3_3", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_WL1END3_3", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_IMUX17_3", - "INT_INTERFACE_IMUX17" - ] - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - 1 - ] - }, - { - "wire_pairs": [ - [ - "INT_INTERFACE_SW4A1", - "BRAM_SW4A1_2" - ], - [ - "INT_INTERFACE_ER1BEG2", - "BRAM_ER1BEG2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX16", - "BRAM_IMUX16_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "BRAM_LOGIC_OUTS_B12_2" - ], - [ - "INT_INTERFACE_BYP6", - "BRAM_BYP6_2" - ], - [ - "INT_INTERFACE_NE4BEG3", - "BRAM_NE4BEG3_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "BRAM_LOGIC_OUTS_B13_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "BRAM_LOGIC_OUTS_B4_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX14", - "BRAM_IMUX14_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "BRAM_IMUX32_2" - ], - [ - "INT_INTERFACE_SE2A2", - "BRAM_SE2A2_2" - ], - [ - "INT_INTERFACE_NW4A1", - "BRAM_NW4A1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "BRAM_IMUX1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX9", - "BRAM_IMUX9_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX27", - "BRAM_IMUX27_UTURN_2" - ], - [ - "INT_INTERFACE_WW2A1", - "BRAM_WW2A1_2" - ], - [ - "INT_INTERFACE_BYP1", - "BRAM_BYP1_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "BRAM_IMUX8_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX36", - "BRAM_IMUX36_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "BRAM_LOGIC_OUTS_B7_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX27", - "BRAM_IMUX27_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX41", - "BRAM_IMUX41_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "BRAM_IMUX10_UTURN_2" - ], - [ - "INT_INTERFACE_EL1BEG1", - "BRAM_EL1BEG1_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX22", - "BRAM_IMUX22_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "BRAM_IMUX37_2" - ], - [ - "INT_INTERFACE_SW4A2", - "BRAM_SW4A2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX6", - "BRAM_IMUX6_2" - ], - [ - "INT_INTERFACE_WW4A1", - "BRAM_WW4A1_2" - ], - [ - "INT_INTERFACE_SE4C3", - "BRAM_SE4C3_2" - ], - [ - "INT_INTERFACE_SE4C0", - "BRAM_SE4C0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX9", - "BRAM_IMUX9_2" - ], - [ - "INT_INTERFACE_LH1", - "BRAM_LH1_2" - ], - [ - "INT_INTERFACE_SE4BEG0", - "BRAM_SE4BEG0_2" - ], - [ - "INT_INTERFACE_LH12", - "BRAM_LH12_2" - ], - [ - "INT_INTERFACE_WW4END1", - "BRAM_WW4END1_2" - ], - [ - "INT_INTERFACE_ER1BEG0", - "BRAM_ER1BEG0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "BRAM_LOGIC_OUTS_B5_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_2" - ], - [ - "INT_INTERFACE_SW2A2", - "BRAM_SW2A2_2" - ], - [ - "INT_INTERFACE_CLK0", - "BRAM_CLK0_2" - ], - [ - "INT_INTERFACE_LH2", - "BRAM_LH2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX24", - "BRAM_IMUX24_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX1", - "BRAM_IMUX1_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX46", - "BRAM_IMUX46_UTURN_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "BRAM_LOGIC_OUTS_B11_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX28", - "BRAM_IMUX28_UTURN_2" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_2" - ], - [ - "INT_INTERFACE_EE4A3", - "BRAM_EE4A3_2" - ], - [ - "INT_INTERFACE_WL1END0", - "BRAM_WL1END0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "BRAM_LOGIC_OUTS_B17_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX3", - "BRAM_IMUX3_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX26", - "BRAM_IMUX26_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX4", - "BRAM_IMUX4_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX5", - "BRAM_IMUX5_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX25", - "BRAM_IMUX25_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX7", - "BRAM_IMUX7_UTURN_2" - ], - [ - "INT_INTERFACE_BYP0", - "BRAM_BYP0_2" - ], - [ - "INT_INTERFACE_WW4B2", - "BRAM_WW4B2_2" - ], - [ - "INT_INTERFACE_WW2END2", - "BRAM_WW2END2_2" - ], - [ - "INT_INTERFACE_WW4A3", - "BRAM_WW4A3_2" - ], - [ - "INT_INTERFACE_NW2A1", - "BRAM_NW2A1_2" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_2" - ], - [ - "INT_INTERFACE_WW4B1", - "BRAM_WW4B1_2" - ], - [ - "INT_INTERFACE_NE4BEG0", - "BRAM_NE4BEG0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - "BRAM_IMUX47_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX39", - "BRAM_IMUX39_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX19", - "BRAM_IMUX19_UTURN_2" - ], - [ - "INT_INTERFACE_EE4B1", - "BRAM_EE4B1_2" - ], - [ - "INT_INTERFACE_EE4BEG1", - "BRAM_EE4BEG1_2" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_2" - ], - [ - "INT_INTERFACE_EE4BEG3", - "BRAM_EE4BEG3_2" - ], - [ - "INT_INTERFACE_WR1END3", - "BRAM_WR1END3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX29", - "BRAM_IMUX29_UTURN_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "BRAM_LOGIC_OUTS_B18_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "BRAM_LOGIC_OUTS_B9_2" - ], - [ - "INT_INTERFACE_WW4C1", - "BRAM_WW4C1_2" - ], - [ - "INT_INTERFACE_EE4B2", - "BRAM_EE4B2_2" - ], - [ - "INT_INTERFACE_EE2A3", - "BRAM_EE2A3_2" - ], - [ - "INT_INTERFACE_SW4A3", - "BRAM_SW4A3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX40", - "BRAM_IMUX40_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX19", - "BRAM_IMUX19_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX42", - "BRAM_IMUX42_2" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_2" - ], - [ - "INT_INTERFACE_NE2A2", - "BRAM_NE2A2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "BRAM_IMUX4_2" - ], - [ - "INT_INTERFACE_NW2A3", - "BRAM_NW2A3_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "BRAM_LOGIC_OUTS_B6_2" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_2" - ], - [ - "INT_INTERFACE_EL1BEG0", - "BRAM_EL1BEG0_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX31", - "BRAM_IMUX31_UTURN_2" - ], - [ - "INT_INTERFACE_LH5", - "BRAM_LH5_2" - ], - [ - "INT_INTERFACE_EL1BEG2", - "BRAM_EL1BEG2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX15", - "BRAM_IMUX15_UTURN_2" - ], - [ - "INT_INTERFACE_NW2A0", - "BRAM_NW2A0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "BRAM_LOGIC_OUTS_B16_2" - ], - [ - "INT_INTERFACE_WW2END1", - "BRAM_WW2END1_2" - ], - [ - "INT_INTERFACE_WW4C2", - "BRAM_WW4C2_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "BRAM_LOGIC_OUTS_B23_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "BRAM_LOGIC_OUTS_B2_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX45", - "BRAM_IMUX45_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX34", - "BRAM_IMUX34_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "BRAM_IMUX5_2" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_2" - ], - [ - "INT_INTERFACE_FAN5", - "BRAM_FAN5_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX35", - "BRAM_IMUX35_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "BRAM_IMUX3_2" - ], - [ - "INT_INTERFACE_EE2A2", - "BRAM_EE2A2_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_2" - ], - [ - "INT_INTERFACE_CTRL1", - "BRAM_CTRL1_2" - ], - [ - "INT_INTERFACE_FAN3", - "BRAM_FAN3_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX21", - "BRAM_IMUX21_UTURN_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX23", - "BRAM_IMUX23_2" - ], - [ - "INT_INTERFACE_SW4END0", - "BRAM_SW4END0_2" - ], - [ - "INT_INTERFACE_BRAM_IMUX26", - "BRAM_IMUX26_2" - ], - [ - "INT_INTERFACE_ER1BEG3", - "BRAM_ER1BEG3_2" - ], - [ - "INT_INTERFACE_EE4A0", - "BRAM_EE4A0_2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "BRAM_LOGIC_OUTS_B20_2" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX2", - "BRAM_IMUX2_UTURN_2" - ], - [ - "INT_INTERFACE_EE4BEG0", - "BRAM_EE4BEG0_2" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_2" - ], - [ - "INT_INTERFACE_NW4A0", - "BRAM_NW4A0_2" - ], - [ - "INT_INTERFACE_NW4END2", - "BRAM_NW4END2_2" - ], - [ - "INT_INTERFACE_WW4END2", - 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- [ - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC11" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_BUFG_CASC9" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC7" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC3" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC31" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC28" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC24" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC12" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC6" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC27" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC20" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC4" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC0" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC1" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC29" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC25" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC13" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC14" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC26" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC5" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK25" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC16" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC2" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC18" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC17" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC21" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC23" - ], - [ - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC22" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ] - ], - "tile_types": [ - "CLK_FEED", - "CLK_PMV2" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CMT_FIFO_L_LOGIC_OUTS22_0", - "INT_INTERFACE_LOGIC_OUTS_B22" - ], - [ - "CMT_FIFO_NE2A2_0", - "INT_INTERFACE_NE2A2" - ], - [ - "CMT_FIFO_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CMT_FIFO_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CMT_FIFO_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CMT_FIFO_L_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CMT_FIFO_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS2_0", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS8_0", - "INT_INTERFACE_LOGIC_OUTS_B8" - ], - [ - "CMT_FIFO_SE2A3_0", - "INT_INTERFACE_SE2A3" - ], - [ - "CMT_FIFO_EL1BEG1_0", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CMT_FIFO_L_IMUX43_0", - "INT_INTERFACE_IMUX43" - ], - [ - "CMT_FIFO_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CMT_FIFO_L_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CMT_FIFO_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CMT_FIFO_L_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CMT_FIFO_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CMT_FIFO_L_IMUX31_0", - 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- "VBRK_NE2A1" - ], - [ - "CMT_TOP_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4B0_4", - "VBRK_WW4B0" - ] - ], - "tile_types": [ - "CMT_TOP_R_UPPER_T", - "VBRK" - ], - "grid_deltas": [ - 1, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_SW4END3_5", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_ER1BEG3_5", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WL1END3_5", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_WW2END3_5", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NW2A1_5", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_NW4A0_5", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_SE2A3_5", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_NW2A0_5", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_SE4BEG0_5", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH5_5", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4A0_5", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_WR1END0_5", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_WW4C1_5", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_EE4C1_5", - "VBRK_EE4C1" - ], - [ - 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"CLK_HROW_SW4A1_5", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_NE4C2_5", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW4END1_5", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SE4BEG2_5", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_LH2_5", - "VBRK_LH2" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -2 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_DSP_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN5" - ], - [ - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "HCLK_DSP_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN8" - ], - [ - "HCLK_DSP_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN9" - ], - [ - "HCLK_DSP_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN11" - ], - [ - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "HCLK_DSP_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN6" - ], - [ - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "HCLK_DSP_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN4" - ], - [ - "HCLK_DSP_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN10" - ], - [ - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], - [ - "HCLK_DSP_CK_IN3", - "HCLK_INT_INTERFACE_CK_IN3" - ], - [ - "HCLK_DSP_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "HCLK_DSP_CK_IN1", - "HCLK_INT_INTERFACE_CK_IN1" - ], - [ - "HCLK_DSP_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN0" - ], - [ - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "HCLK_DSP_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "HCLK_DSP_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN7" - ], - [ - "HCLK_DSP_CK_IN2", - "HCLK_INT_INTERFACE_CK_IN2" - ], - [ - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ] - ], - "tile_types": [ - "HCLK_DSP_R", - "HCLK_INT_INTERFACE" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CMT_FIFO_L_IMUX5_3", - "INT_INTERFACE_IMUX5" - ], - [ - "CMT_FIFO_ER1BEG1_3", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CMT_FIFO_L_IMUX15_3", - "INT_INTERFACE_IMUX15" - ], - [ - "CMT_FIFO_EE4BEG2_3", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CMT_FIFO_ER1BEG3_3", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CMT_FIFO_L_CTRL0_3", - "INT_INTERFACE_CTRL0" - ], - [ - "CMT_FIFO_SE2A2_3", - "INT_INTERFACE_SE2A2" - ], - [ - "CMT_FIFO_EE2A3_3", - "INT_INTERFACE_EE2A3" - ], - [ - "CMT_FIFO_WW4A3_3", - "INT_INTERFACE_WW4A3" - ], - [ - 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"VBRK_EXT_IMUX30" - ], - [ - "GTPE2_FAN3_9", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX37_9", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_BYP6_9", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX33_9", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX31_9", - "VBRK_EXT_IMUX31" - ] - ], - "tile_types": [ - "GTP_CHANNEL_1", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - -4 - ] - }, - { - "wire_pairs": [ - [ - "GTPE2_IMUX18_2", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX2_2", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX40_2", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX12_2", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_LOGIC_OUTS_B17_2", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX24_2", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_LOGIC_OUTS_B20_2", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_IMUX6_2", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_BYP6_2", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX29_2", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B13_2", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX3_2", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_FAN0_2", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX22_2", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_CLK0_2", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_IMUX47_2", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX33_2", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX31_2", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX46_2", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX19_2", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX1_2", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_IMUX21_2", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX0_2", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX35_2", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_FAN7_2", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_FAN5_2", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_IMUX41_2", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_FAN4_2", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_BYP5_2", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX11_2", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_IMUX32_2", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX25_2", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_BYP1_2", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_FAN1_2", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX14_2", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX36_2", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_IMUX27_2", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_LOGIC_OUTS_B19_2", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_IMUX7_2", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX44_2", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_FAN6_2", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_IMUX5_2", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX4_2", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_LOGIC_OUTS_B18_2", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_IMUX8_2", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX30_2", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_IMUX20_2", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX23_2", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_FAN3_2", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_IMUX9_2", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX16_2", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX39_2", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_BYP4_2", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX34_2", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_CLK1_2", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX15_2", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_IMUX26_2", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B10_2", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_IMUX28_2", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_BYP3_2", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_BYP0_2", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_BYP7_2", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_LOGIC_OUTS_B16_2", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_LOGIC_OUTS_B9_2", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX42_2", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_FAN2_2", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX43_2", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_LOGIC_OUTS_B8_2", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTPE2_LOGIC_OUTS_B23_2", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_IMUX17_2", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX45_2", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX13_2", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX38_2", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_CTRL1_2", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX10_2", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX37_2", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_BYP2_2", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_CTRL0_2", - "VBRK_EXT_CTRL0" - ] - ], - "tile_types": [ - "GTP_COMMON", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - -2 - ] - }, - { - "wire_pairs": [ - [ - "GTPE2_BYP3_5", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX17_5", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX33_5", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_LOGIC_OUTS_B18_5", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_IMUX2_5", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_CTRL0_5", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_IMUX15_5", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_FAN4_5", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX5_5", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX46_5", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_BYP7_5", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX6_5", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX41_5", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX10_5", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_LOGIC_OUTS_B10_5", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_IMUX19_5", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_LOGIC_OUTS_B19_5", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_IMUX36_5", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_FAN1_5", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX26_5", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_IMUX43_5", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_IMUX35_5", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_IMUX44_5", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX39_5", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_FAN2_5", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_IMUX12_5", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX11_5", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_BYP4_5", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX21_5", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_IMUX14_5", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX38_5", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX4_5", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX20_5", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX13_5", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_LOGIC_OUTS_B13_5", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_IMUX8_5", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX25_5", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX1_5", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_FAN0_5", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX31_5", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX16_5", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_BYP6_5", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX18_5", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_IMUX45_5", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX40_5", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_BYP2_5", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX24_5", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_IMUX9_5", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_IMUX30_5", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_BYP5_5", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX37_5", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_LOGIC_OUTS_B16_5", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_LOGIC_OUTS_B9_5", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_IMUX27_5", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_LOGIC_OUTS_B14_5", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX47_5", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_FAN5_5", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_CTRL1_5", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_LOGIC_OUTS_B8_5", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTPE2_FAN7_5", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX7_5", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX32_5", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX22_5", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX0_5", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX29_5", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_IMUX3_5", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX42_5", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_CLK0_5", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_CLK1_5", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_FAN3_5", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_LOGIC_OUTS_B17_5", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX23_5", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_LOGIC_OUTS_B23_5", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_FAN6_5", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_BYP0_5", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX28_5", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_BYP1_5", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_IMUX34_5", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_LOGIC_OUTS_B11_5", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTPE2_LOGIC_OUTS_B20_5", - "VBRK_EXT_LOGIC_OUTS_B20" - ] - ], - "tile_types": [ - "GTP_COMMON", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - -6 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_BRAM_CK_IN1", - "HCLK_INT_INTERFACE_CK_IN1" - ], - [ - "HCLK_BRAM_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN11" - ], - [ - "HCLK_BRAM_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "HCLK_BRAM_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "HCLK_BRAM_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "HCLK_BRAM_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], - [ - "HCLK_BRAM_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN5" - ], - [ - "HCLK_BRAM_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "HCLK_BRAM_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "HCLK_BRAM_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_BRAM_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "HCLK_BRAM_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "HCLK_BRAM_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN9" - ], - [ - "HCLK_BRAM_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN0" - ], - [ - "HCLK_BRAM_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "HCLK_BRAM_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN6" - ], - [ - "HCLK_BRAM_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "HCLK_BRAM_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ], - [ - "HCLK_BRAM_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN7" - ], - [ - "HCLK_BRAM_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN8" - ], - [ - "HCLK_BRAM_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN10" - ], - [ - "HCLK_BRAM_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "HCLK_BRAM_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN4" - ], - [ - "HCLK_BRAM_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "HCLK_BRAM_CK_IN2", - "HCLK_INT_INTERFACE_CK_IN2" - ], - [ - "HCLK_BRAM_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "HCLK_BRAM_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "HCLK_BRAM_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "HCLK_BRAM_CK_IN3", - "HCLK_INT_INTERFACE_CK_IN3" - ], - [ - "HCLK_BRAM_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ] - ], - "tile_types": [ - "HCLK_BRAM", - "HCLK_INT_INTERFACE" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1" - ], - [ - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1" - ] - ], - "tile_types": [ - "LIOI3", - "LIOI3" - ], - "grid_deltas": [ - 0, - -2 - ] - }, - { - "wire_pairs": [ - [ - "CLK_BUFG_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_SE4C1_1", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_BUFG_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_BUFG_IMUX30_1", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_FAN2_1", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_BUFG_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_MONITOR_P_1", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_SE4C3_1", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_BUFG_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_NW2A2_1", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_BUFG_IMUX6_1", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_NE2A1_1", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_WW4B1_1", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WW4B0_1", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_SW2A0_1", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_BUFG_IMUX34_1", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_ER1BEG1_1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_BUFG_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_SE4C0_1", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_ER1BEG0_1", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_MONITOR_N_1", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_SW2A3_1", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_BUFG_IMUX27_1", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_WW4A3_1", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_FAN4_1", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_NE4C3_1", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_WR1END3_1", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_BUFG_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_BUFG_IMUX9_1", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_BUFG_IMUX15_1", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_NE2A3_1", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_BUFG_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_LH12_1", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_SE4BEG0_1", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_SE2A3_1", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_BUFG_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_WW4C2_1", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_EE4BEG1_1", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_EE2BEG3_1", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_WW4C0_1", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_BUFG_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_BUFG_IMUX7_1", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_BUFG_IMUX31_1", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_BUFG_IMUX39_1", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_NW4A3_1", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_BUFG_IMUX25_1", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_BUFG_IMUX1_1", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_BUFG_IMUX11_1", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_WL1END3_1", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_LH3_1", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_BUFG_IMUX18_1", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_BUFG_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_LH10_1", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_WW4C1_1", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_1", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_WW4A1_1", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WW2A3_1", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_BUFG_IMUX44_1", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_1", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_HROW_EE2A0_1", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_BUFG_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_BUFG_IMUX23_1", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_BYP3_1", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_EE4C3_1", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_SE4BEG1_1", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_NE4BEG1_1", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_WW2END3_1", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_BUFG_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_BUFG_IMUX16_1", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_SW4END3_1", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WL1END1_1", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_EE4BEG0_1", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_WL1END0_1", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_LH11_1", - "INT_INTERFACE_LH11" - ], - [ - "CLK_BUFG_IMUX28_1", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B6_1", - "INT_INTERFACE_LOGIC_OUTS_B6" - ], - [ - "CLK_HROW_NE4C1_1", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_1", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_BYP4_1", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_NW4END3_1", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B0_1", - "INT_INTERFACE_LOGIC_OUTS_B0" - ], - [ - "CLK_BUFG_IMUX10_1", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_EE4C1_1", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_CTRL1_1", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_BUFG_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NW4A2_1", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WR1END0_1", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_NE4C2_1", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_SW4END0_1", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_BUFG_IMUX14_1", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_WR1END2_1", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_BUFG_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_BUFG_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_BUFG_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_LH1_1", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_WW2END0_1", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_BUFG_IMUX29_1", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_EE4A0_1", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_SW4END1_1", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_EL1BEG2_1", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_ER1BEG3_1", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_BUFG_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_EE4C2_1", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_FAN6_1", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_BUFG_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B1_1", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CLK_HROW_NW2A1_1", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_BUFG_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_WW4B3_1", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_BUFG_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_NE4C0_1", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_BUFG_IMUX22_1", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_WW2A1_1", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_BUFG_IMUX3_1", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_BUFG_IMUX21_1", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_NE4BEG0_1", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_EE4BEG2_1", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_BUFG_IMUX43_1", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_BUFG_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B2_1", - "INT_INTERFACE_LOGIC_OUTS_B2" - ], - [ - "CLK_HROW_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_1", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_HROW_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_WW4END2_1", - "INT_INTERFACE_WW4END2" - ] - ], - "tile_types": [ - "CLK_BUFG_TOP_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CMT_FIFO_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CMT_FIFO_LH5_1", - "INT_INTERFACE_LH5" - ], - [ - "CMT_FIFO_WW2A2_1", - "INT_INTERFACE_WW2A2" - ], - [ - "CMT_FIFO_L_IMUX36_1", - "INT_INTERFACE_IMUX36" - ], - [ - "CMT_FIFO_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CMT_FIFO_L_IMUX38_1", - "INT_INTERFACE_IMUX38" - ], - [ - "CMT_FIFO_L_IMUX24_1", - "INT_INTERFACE_IMUX24" - ], - [ - "CMT_FIFO_L_IMUX23_1", - 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"IOI_IMUX26_0", - "TERM_INT_IMUX26" - ], - [ - "IOI_BYP0_0", - "TERM_INT_BYP0" - ], - [ - "IOI_BYP2_0", - "TERM_INT_BYP2" - ], - [ - "IOI_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK" - ], - [ - "IOI_IMUX23_0", - "TERM_INT_IMUX23" - ], - [ - "IOI_IMUX42_0", - "TERM_INT_IMUX42" - ], - [ - "IOI_IMUX17_0", - "TERM_INT_IMUX17" - ], - [ - "IOI_LOGIC_OUTS10_0", - "TERM_INT_LOGIC_OUTS_L_B10" - ], - [ - "IOI_FAN2_0", - "TERM_INT_FAN2" - ], - [ - "IOI_BYP1_0", - "TERM_INT_BYP1" - ], - [ - "IOI_IMUX14_0", - "TERM_INT_IMUX14" - ], - [ - "IOI_LOGIC_OUTS7_0", - "TERM_INT_LOGIC_OUTS_L_B7" - ], - [ - "IOI_IMUX40_0", - "TERM_INT_IMUX40" - ], - [ - "IOI_LOGIC_OUTS18_0", - "TERM_INT_LOGIC_OUTS_L_B18" - ], - [ - "IOI_IMUX30_0", - "TERM_INT_IMUX30" - ], - [ - "IOI_BYP6_0", - "TERM_INT_BYP6" - ], - [ - "IOI_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV" - ], - [ - "IOI_LOGIC_OUTS20_0", - "TERM_INT_LOGIC_OUTS_L_B20" - ], - [ - "IOI_LOGIC_OUTS8_0", - "TERM_INT_LOGIC_OUTS_L_B8" - ], - [ - "IOI_IMUX10_0", - "TERM_INT_IMUX10" - ], - [ - "IOI_IMUX32_0", - "TERM_INT_IMUX32" - ], - [ - "IOI_IMUX37_0", - "TERM_INT_IMUX37" - ], - [ - "IOI_IMUX18_0", - "TERM_INT_IMUX18" - ], - [ - "IOI_BLOCK_OUTS0_0", - "TERM_INT_BLOCK_OUTS_L_B0" - ], - [ - "IOI_IMUX36_0", - "TERM_INT_IMUX36" - ], - [ - "IOI_IMUX33_0", - "TERM_INT_IMUX33" - ], - [ - "IOI_LOGIC_OUTS2_0", - "TERM_INT_LOGIC_OUTS_L_B2" - ], - [ - "IOI_IMUX3_0", - "TERM_INT_IMUX3" - ], - [ - "IOI_LOGIC_OUTS5_0", - "TERM_INT_LOGIC_OUTS_L_B5" - ], - [ - "IOI_IMUX5_0", - "TERM_INT_IMUX5" - ], - [ - "IOI_BYP3_0", - "TERM_INT_BYP3" - ], - [ - "IOI_LOGIC_OUTS15_0", - "TERM_INT_LOGIC_OUTS_L_B15" - ], - [ - "IOI_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLK" - ], - [ - "IOI_IMUX11_0", - "TERM_INT_IMUX11" - ], - [ - "IOI_FAN1_0", - "TERM_INT_FAN1" - ], - [ - "IOI_IMUX47_0", - "TERM_INT_IMUX47" - ], - [ - "IOI_FAN5_0", - "TERM_INT_FAN5" - ], - [ - "IOI_FAN7_0", - "TERM_INT_FAN7" - ], - [ - "IOI_IMUX46_0", - "TERM_INT_IMUX46" - ], - [ - "IOI_IMUX0_0", - "TERM_INT_IMUX0" - ], - [ - "IOI_CTRL0_0", - "TERM_INT_CTRL0" - ], - [ - "IOI_IMUX45_0", - "TERM_INT_IMUX45" - ], - [ - "IOI_IMUX27_0", - "TERM_INT_IMUX27" - ], - [ - "IOI_IMUX1_0", - "TERM_INT_IMUX1" - ], - [ - "IOI_IMUX4_0", - "TERM_INT_IMUX4" - ], - [ - "IOI_IMUX25_0", - "TERM_INT_IMUX25" - ], - [ - "IOI_LOGIC_OUTS1_0", - "TERM_INT_LOGIC_OUTS_L_B1" - ], - [ - "IOI_BLOCK_OUTS2_0", - "TERM_INT_BLOCK_OUTS_L_B2" - ], - [ - "IOI_IMUX20_0", - "TERM_INT_IMUX20" - ], - [ - "IOI_BYP4_0", - "TERM_INT_BYP4" - ], - [ - "IOI_CLK1_0", - "TERM_INT_CLK1" - ], - [ - "IOI_LOGIC_OUTS19_0", - "TERM_INT_LOGIC_OUTS_L_B19" - ], - [ - "IOI_IMUX38_0", - "TERM_INT_IMUX38" - ], - [ - "IOI_IMUX8_0", - "TERM_INT_IMUX8" - ], - [ - "IOI_IMUX41_0", - "TERM_INT_IMUX41" - ], - [ - "IOI_IMUX43_0", - "TERM_INT_IMUX43" - ], - [ - "IOI_IMUX2_0", - "TERM_INT_IMUX2" - ], - [ - "IOI_IMUX12_0", - "TERM_INT_IMUX12" - ], - [ - "IOI_IMUX29_0", - "TERM_INT_IMUX29" - ], - [ - "IOI_CTRL1_0", - "TERM_INT_CTRL1" - ], - [ - "IOI_IMUX21_0", - "TERM_INT_IMUX21" - ], - [ - "IOI_LOGIC_OUTS3_0", - "TERM_INT_LOGIC_OUTS_L_B3" - ], - [ - "IOI_IMUX44_0", - "TERM_INT_IMUX44" - ], - [ - "IOI_CLK0_0", - "TERM_INT_CLK0" - ], - [ - "IOI_IMUX6_0", - "TERM_INT_IMUX6" - ] - ], - "tile_types": [ - "RIOI3_SING", - "R_TERM_INT" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_CK_IN_L5", - "HCLK_INT_INTERFACE_CK_IN5" - ], - [ - "CLK_HROW_CK_BUFHCLK_L9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "CLK_HROW_CK_BUFHCLK_L10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "CLK_HROW_CK_IN_L7", - "HCLK_INT_INTERFACE_CK_IN7" - ], - [ - "CLK_HROW_CK_IN_L13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "CLK_HROW_CK_IN_L10", - "HCLK_INT_INTERFACE_CK_IN10" - ], - [ - "CLK_HROW_CK_BUFRCLK_L0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "CLK_HROW_CK_IN_L4", - "HCLK_INT_INTERFACE_CK_IN4" - ], - [ - "CLK_HROW_CK_IN_L6", - "HCLK_INT_INTERFACE_CK_IN6" - ], - [ - "CLK_HROW_CK_IN_L12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "CLK_HROW_CK_BUFHCLK_L4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "CLK_HROW_CK_IN_L1", - "HCLK_INT_INTERFACE_CK_IN1" - ], - [ - "CLK_HROW_CK_BUFHCLK_L11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "CLK_HROW_CK_BUFHCLK_L8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "CLK_HROW_CK_BUFRCLK_L2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "CLK_HROW_CK_IN_L8", - "HCLK_INT_INTERFACE_CK_IN8" - ], - [ - "CLK_HROW_CK_BUFRCLK_L3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "CLK_HROW_CK_BUFHCLK_L7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ], - [ - "CLK_HROW_CK_BUFHCLK_L1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "CLK_HROW_CK_IN_L0", - "HCLK_INT_INTERFACE_CK_IN0" - ], - [ - "CLK_HROW_CK_BUFHCLK_L0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "CLK_HROW_CK_BUFHCLK_L6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ], - [ - "CLK_HROW_CK_BUFRCLK_L1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "CLK_HROW_CK_BUFHCLK_L2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "CLK_HROW_CK_BUFHCLK_L5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "CLK_HROW_CK_IN_L9", - "HCLK_INT_INTERFACE_CK_IN9" - ], - [ - "CLK_HROW_CK_IN_L2", - "HCLK_INT_INTERFACE_CK_IN2" - ], - [ - "CLK_HROW_CK_IN_L11", - "HCLK_INT_INTERFACE_CK_IN11" - ], - [ - "CLK_HROW_CK_IN_L3", - "HCLK_INT_INTERFACE_CK_IN3" - ], - [ - "CLK_HROW_CK_BUFHCLK_L3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "HCLK_INT_INTERFACE" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_WL1END0_6", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4B0_6", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4B1_6", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_SW4A0_6", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_SE4BEG2_6", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_WW2A0_6", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_NE4C3_6", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_NE4BEG3_6", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WW4END1_6", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WL1END3_6", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE4A0_6", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW4A0_6", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_SW2A3_6", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_SE4BEG1_6", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_SW2A1_6", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_SE4BEG0_6", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_EL1BEG1_6", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE4C0_6", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_NW4END0_6", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_LH4_6", - "VBRK_LH4" - ], - [ - "CLK_HROW_SW4A3_6", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_LH3_6", - "VBRK_LH3" - ], - [ - "CLK_HROW_SW4A2_6", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW4A2_6", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_SW4A1_6", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_NW4END2_6", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE2A1_6", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW4A2_6", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_SE4C3_6", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_SW4END2_6", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_LH7_6", - "VBRK_LH7" - ], - [ - "CLK_HROW_SW2A2_6", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_WW4B2_6", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_WW4C2_6", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_EL1BEG0_6", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW4C0_6", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4END0_6", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WW4END3_6", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_WW4END2_6", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_LH9_6", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW2END1_6", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_NE4BEG0_6", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WW4B3_6", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WR1END1_6", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW4END3_6", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WL1END2_6", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_NE4BEG1_6", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_NE4C1_6", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NE2A2_6", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE2A1_6", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE4B1_6", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE4C1_6", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW4C3_6", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4C2_6", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_SE4C2_6", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_EE4B3_6", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_EE4A3_6", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE2A3_6", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_SE4C1_6", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_EE2BEG0_6", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_EE4BEG2_6", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4A3_6", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_SW2A0_6", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SW4END1_6", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WL1END1_6", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NW4END1_6", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_WW2END3_6", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NW4A1_6", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE4A2_6", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_LH5_6", - "VBRK_LH5" - ], - [ - "CLK_HROW_NW4A0_6", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_WW2A2_6", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4BEG0_6", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4BEG1_6", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SE2A0_6", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_ER1BEG1_6", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_LH10_6", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE2BEG1_6", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_LH2_6", - "VBRK_LH2" - ], - [ - "CLK_HROW_NE4C2_6", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW4C1_6", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_EE4B0_6", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_NW4A3_6", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_EL1BEG2_6", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_MONITOR_N_6", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_EE2A3_6", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_EE2BEG3_6", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_ER1BEG0_6", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_NE4BEG2_6", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_EE2A2_6", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NW2A0_6", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE4C3_6", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_NE4C0_6", - "VBRK_NE4C0" - ], - [ - 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"CLK_HROW_EE4A1_6", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_EE2BEG2_6", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_EE4B2_6", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH8_6", - "VBRK_LH8" - ], - [ - "CLK_HROW_ER1BEG3_6", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE2A0_6", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NW2A3_6", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SE4C0_6", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW2END0_6", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SE2A2_6", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NW2A2_6", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4END3_6", - "VBRK_SW4END3" - ] - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -3 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_WW2A3_6", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_NE2A1_6", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_WW4C0_6", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_LH4_6", - "VBRK_LH4" - ], - [ - "CMT_TOP_WW4B0_6", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_NW4END0_6", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_NW4A3_6", - "VBRK_NW4A3" - ], - [ - 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- }, - { - "wire_pairs": [ - [ - "MONITOR_VERT_VAUXN6", - "MONITOR_VERT_VAUXN6" - ], - [ - "MONITOR_VERT_VAUXN3", - "MONITOR_VERT_VAUXN3" - ], - [ - "MONITOR_VERT_VAUXP14", - "MONITOR_VERT_VAUXP14" - ], - [ - "MONITOR_VERT_VAUXP3", - "MONITOR_VERT_VAUXP3" - ], - [ - "MONITOR_VERT_VAUXN14", - "MONITOR_VERT_VAUXN14" - ], - [ - "MONITOR_VERT_VAUXP9", - "MONITOR_VERT_VAUXP9" - ], - [ - "MONITOR_VERT_VAUXP6", - "MONITOR_VERT_VAUXP6" - ], - [ - "MONITOR_VERT_VAUXP7", - "MONITOR_VERT_VAUXP7" - ], - [ - "MONITOR_VERT_VAUXN13", - "MONITOR_VERT_VAUXN13" - ], - [ - "MONITOR_VERT_VAUXP12", - "MONITOR_VERT_VAUXP12" - ], - [ - "MONITOR_VERT_VAUXP0", - "MONITOR_VERT_VAUXP0" - ], - [ - "MONITOR_VERT_VAUXP13", - "MONITOR_VERT_VAUXP13" - ], - [ - "MONITOR_VERT_VAUXP5", - "MONITOR_VERT_VAUXP5" - ], - [ - "MONITOR_VERT_VAUXN0", - "MONITOR_VERT_VAUXN0" - ], - [ - "MONITOR_VERT_VAUXN15", - "MONITOR_VERT_VAUXN15" - ], - [ - "MONITOR_VERT_VAUXN12", - "MONITOR_VERT_VAUXN12" - ], - [ - "MONITOR_VERT_VAUXN7", - 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"BRAM_WW2A0_1" - ], - [ - "INT_INTERFACE_SW4END2", - "BRAM_SW4END2_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B11", - "BRAM_LOGIC_OUTS_B11_1" - ], - [ - "INT_INTERFACE_WW4A2", - "BRAM_WW4A2_1" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_1" - ], - [ - "INT_INTERFACE_NE4BEG1", - "BRAM_NE4BEG1_1" - ], - [ - "INT_INTERFACE_WW4C2", - "BRAM_WW4C2_1" - ], - [ - "INT_INTERFACE_WW4B1", - "BRAM_WW4B1_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B1", - "BRAM_LOGIC_OUTS_B1_1" - ], - [ - "INT_INTERFACE_NW2A1", - "BRAM_NW2A1_1" - ], - [ - "INT_INTERFACE_EE4BEG3", - "BRAM_EE4BEG3_1" - ], - [ - "INT_INTERFACE_SW2A3", - "BRAM_SW2A3_1" - ], - [ - "INT_INTERFACE_WW4A3", - "BRAM_WW4A3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - "BRAM_IMUX47_1" - ], - [ - "INT_INTERFACE_WW2END1", - "BRAM_WW2END1_1" - ], - [ - "INT_INTERFACE_WW2A3", - "BRAM_WW2A3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX12", - "BRAM_IMUX12_UTURN_1" - ], - [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_1" - ], - [ - "INT_INTERFACE_EE2BEG1", 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[ - "INT_INTERFACE_SE4BEG1", - "BRAM_SE4BEG1_1" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B22", - "BRAM_LOGIC_OUTS_B22_1" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX40", - "BRAM_IMUX40_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX11", - "BRAM_IMUX11_UTURN_1" - ], - [ - "INT_INTERFACE_SE2A1", - "BRAM_SE2A1_1" - ], - [ - "INT_INTERFACE_CLK0", - "BRAM_CLK0_1" - ], - [ - "INT_INTERFACE_WW2A1", - "BRAM_WW2A1_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B15", - "BRAM_LOGIC_OUTS_B15_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX8", - "BRAM_IMUX8_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "BRAM_IMUX25_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX32", - "BRAM_IMUX32_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX25", - "BRAM_IMUX25_UTURN_1" - ], - [ - "INT_INTERFACE_SW4END1", - "BRAM_SW4END1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX14", - "BRAM_IMUX14_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX0", - "BRAM_IMUX0_UTURN_1" - ], - [ - "INT_INTERFACE_FAN7", - "BRAM_FAN7_1" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_1" - ], - [ - "INT_INTERFACE_EE4B3", - "BRAM_EE4B3_1" - ], - [ - "INT_INTERFACE_EE4C2", - "BRAM_EE4C2_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX45", - "BRAM_IMUX45_1" - ], - [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX22", - "BRAM_IMUX22_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX29", - "BRAM_IMUX29_1" - ], - [ - "INT_INTERFACE_NW4A1", - "BRAM_NW4A1_1" - ], - [ - "INT_INTERFACE_ER1BEG2", - "BRAM_ER1BEG2_1" - ], - [ - "INT_INTERFACE_EL1BEG2", - "BRAM_EL1BEG2_1" - ], - [ - "INT_INTERFACE_FAN5", - "BRAM_FAN5_1" - ], - [ - "INT_INTERFACE_SE2A0", - "BRAM_SE2A0_1" - ], - [ - "INT_INTERFACE_WW4END3", - "BRAM_WW4END3_1" - ], - [ - "INT_INTERFACE_BYP0", - "BRAM_BYP0_1" - ], - [ - "INT_INTERFACE_NW2A3", - "BRAM_NW2A3_1" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX28", - "BRAM_IMUX28_UTURN_1" - ], - [ - "INT_INTERFACE_EE4B2", - "BRAM_EE4B2_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B9", - "BRAM_LOGIC_OUTS_B9_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX37", - "BRAM_IMUX37_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX6", - "BRAM_IMUX6_UTURN_1" - ], - [ - "INT_INTERFACE_NW4END3", - "BRAM_NW4END3_1" - ], - [ - "INT_INTERFACE_EE4BEG0", - "BRAM_EE4BEG0_1" - ], - [ - "INT_INTERFACE_EE4B1", - "BRAM_EE4B1_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "BRAM_IMUX4_1" - ], - [ - "INT_INTERFACE_EE4A3", - "BRAM_EE4A3_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B2", - "BRAM_LOGIC_OUTS_B2_1" - ], - [ - "INT_INTERFACE_WR1END0", - "BRAM_WR1END0_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX34", - "BRAM_IMUX34_1" - ], - [ - "INT_INTERFACE_WW4END2", - "BRAM_WW4END2_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX33", - "BRAM_IMUX33_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "BRAM_IMUX31_1" - ], - [ - "INT_INTERFACE_NE4C3", - "BRAM_NE4C3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_1" - ], - [ - "INT_INTERFACE_CTRL1", - "BRAM_CTRL1_1" - ], - [ - "INT_INTERFACE_SW4A1", - "BRAM_SW4A1_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "BRAM_IMUX37_1" - ], - [ - "INT_INTERFACE_NW2A2", - "BRAM_NW2A2_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B17", - "BRAM_LOGIC_OUTS_B17_1" - ], - [ - "INT_INTERFACE_BYP5", - "BRAM_BYP5_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX43", - "BRAM_IMUX43_UTURN_1" - ], - [ - "INT_INTERFACE_WR1END1", - "BRAM_WR1END1_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX9", - "BRAM_IMUX9_1" - ], - [ - "INT_INTERFACE_WL1END0", - "BRAM_WL1END0_1" - ], - [ - "INT_INTERFACE_EE4A0", - "BRAM_EE4A0_1" - ], - [ - "INT_INTERFACE_SE4C2", - "BRAM_SE4C2_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX5", - "BRAM_IMUX5_UTURN_1" - ], - [ - "INT_INTERFACE_ER1BEG3", - "BRAM_ER1BEG3_1" - ], - [ - "INT_INTERFACE_NW4A0", - "BRAM_NW4A0_1" - ], - [ - "INT_INTERFACE_LH8", - "BRAM_LH8_1" - ], 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"BRAM_EL1BEG0_1" - ], - [ - "INT_INTERFACE_ER1BEG0", - "BRAM_ER1BEG0_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B0", - "BRAM_LOGIC_OUTS_B0_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B8", - "BRAM_LOGIC_OUTS_B8_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B5", - "BRAM_LOGIC_OUTS_B5_1" - ], - [ - "INT_INTERFACE_SW4END0", - "BRAM_SW4END0_1" - ], - [ - "INT_INTERFACE_SE4C0", - "BRAM_SE4C0_1" - ], - [ - "INT_INTERFACE_LH2", - "BRAM_LH2_1" - ], - [ - "INT_INTERFACE_EE2BEG2", - "BRAM_EE2BEG2_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX41", - "BRAM_IMUX41_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX33", - "BRAM_IMUX33_UTURN_1" - ], - [ - "INT_INTERFACE_EE4BEG2", - "BRAM_EE4BEG2_1" - ], - [ - "INT_INTERFACE_WW4END0", - "BRAM_WW4END0_1" - ], - [ - "INT_INTERFACE_EE2A1", - "BRAM_EE2A1_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "BRAM_IMUX5_1" - ], - [ - "INT_INTERFACE_EE2A0", - "BRAM_EE2A0_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX20", - "BRAM_IMUX20_1" - ], - [ - "INT_INTERFACE_CTRL0", - "BRAM_CTRL0_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX30", - "BRAM_IMUX30_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B20", - "BRAM_LOGIC_OUTS_B20_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX23", - "BRAM_IMUX23_UTURN_1" - ], - [ - "INT_INTERFACE_WW4C1", - "BRAM_WW4C1_1" - ], - [ - "INT_INTERFACE_LH12", - "BRAM_LH12_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX11", - "BRAM_IMUX11_1" - ], - [ - "INT_INTERFACE_MONITOR_N", - "BRAM_MONITOR_N_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX7", - "BRAM_IMUX7_1" - ], - [ - "INT_INTERFACE_BYP1", - "BRAM_BYP1_1" - ], - [ - "INT_INTERFACE_SW4A2", - "BRAM_SW4A2_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX19", - "BRAM_IMUX19_1" - ], - [ - "INT_INTERFACE_LH3", - "BRAM_LH3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX10", - "BRAM_IMUX10_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_1" - ], - [ - "INT_INTERFACE_LH7", - "BRAM_LH7_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX26", - "BRAM_IMUX26_UTURN_1" - ], - [ - "INT_INTERFACE_NE4C2", - "BRAM_NE4C2_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "BRAM_IMUX44_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX4", - "BRAM_IMUX4_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX29", - "BRAM_IMUX29_UTURN_1" - ], - [ - "INT_INTERFACE_NW2A0", - "BRAM_NW2A0_1" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_1" - ], - [ - "INT_INTERFACE_FAN2", - "BRAM_FAN2_1" - ], - [ - "INT_INTERFACE_WW4C0", - "BRAM_WW4C0_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B19", - "BRAM_LOGIC_OUTS_B19_1" - ], - [ - "INT_INTERFACE_BYP6", - "BRAM_BYP6_1" - ], - [ - "INT_INTERFACE_EE4C0", - "BRAM_EE4C0_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX19", - "BRAM_IMUX19_UTURN_1" - ], - [ - "INT_INTERFACE_BYP3", - "BRAM_BYP3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX42", - "BRAM_IMUX42_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX47", - "BRAM_IMUX47_UTURN_1" - ], - [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_1" - ], - [ - "INT_INTERFACE_ER1BEG1", - "BRAM_ER1BEG1_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "BRAM_IMUX1_1" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_1" - ], - [ - "INT_INTERFACE_LH9", - "BRAM_LH9_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_1" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_1" - ], - [ - "INT_INTERFACE_FAN3", - "BRAM_FAN3_1" - ], - [ - "INT_INTERFACE_SW2A2", - "BRAM_SW2A2_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX21", - "BRAM_IMUX21_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "BRAM_IMUX38_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX13", - "BRAM_IMUX13_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_1" - ], - [ - "INT_INTERFACE_EE4C3", - "BRAM_EE4C3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX3", - "BRAM_IMUX3_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX15", - "BRAM_IMUX15_UTURN_1" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX24", - "BRAM_IMUX24_UTURN_1" - ], - [ - "INT_INTERFACE_EE2BEG0", - "BRAM_EE2BEG0_1" - ], - [ - "INT_INTERFACE_MONITOR_P", - "BRAM_MONITOR_P_1" - ], - [ - "INT_INTERFACE_LH4", - "BRAM_LH4_1" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX24", - "BRAM_IMUX24_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "BRAM_IMUX3_1" - ], - [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B12", - "BRAM_LOGIC_OUTS_B12_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX9", - "BRAM_IMUX9_UTURN_1" - ], - [ - "INT_INTERFACE_NE2A3", - "BRAM_NE2A3_1" - ], - [ - "INT_INTERFACE_SE4C1", - "BRAM_SE4C1_1" - ], - [ - "INT_INTERFACE_WL1END3", - "BRAM_WL1END3_1" - ], - [ - "INT_INTERFACE_SE4BEG0", - "BRAM_SE4BEG0_1" - ], - [ - "INT_INTERFACE_NE4BEG3", - "BRAM_NE4BEG3_1" - ], - [ - "INT_INTERFACE_NE4C1", - "BRAM_NE4C1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX18", - "BRAM_IMUX18_UTURN_1" - ], - [ - "INT_INTERFACE_FAN4", - "BRAM_FAN4_1" - ], - [ - "INT_INTERFACE_SW4A3", - "BRAM_SW4A3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX16", - "BRAM_IMUX16_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX44", - "BRAM_IMUX44_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX35", - "BRAM_IMUX35_UTURN_1" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_1" - ], - [ - "INT_INTERFACE_LH6", - "BRAM_LH6_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B13", - "BRAM_LOGIC_OUTS_B13_1" - ], - [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_1" - ] - ], - "tile_types": [ - "BRAM_INT_INTERFACE_R", - "BRAM_R" - ], - "grid_deltas": [ - 1, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_WW4A2_4", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_LH10_4", - "VBRK_LH10" - ], - [ - "CLK_HROW_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW4A2_4", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_NW4A2_4", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_SE2A0_4", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_SW4END1_4", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_EL1BEG3_4", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_SE4BEG1_4", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_EE4B0_4", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW2END2_4", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WR1END3_4", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_NE4C1_4", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_EE2A2_4", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_SE4C3_4", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE2BEG3_4", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_WW4END3_4", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NW4A0_4", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NE4C0_4", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_EE4C1_4", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_LH5_4", - "VBRK_LH5" - ], - [ - "CLK_HROW_NE2A2_4", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_NE4C2_4", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_EE4BEG0_4", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_MONITOR_P_4", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_ER1BEG3_4", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_LH2_4", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW2A1_4", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SE2A1_4", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_SW2A0_4", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SE2A3_4", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH9_4", - "VBRK_LH9" - ], - [ - "CLK_HROW_LH6_4", - "VBRK_LH6" - ], - [ - "CLK_HROW_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_LH7_4", - "VBRK_LH7" - ], - [ - "CLK_HROW_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NW4END2_4", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_NW4A3_4", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW4B3_4", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_SW4A3_4", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WW2END0_4", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SW2A2_4", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_ER1BEG2_4", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH1_4", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW4END0_4", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_EE4C2_4", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_SW4END2_4", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_WL1END2_4", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH4_4", - "VBRK_LH4" - ], - [ - "CLK_HROW_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_LH3_4", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4A0_4", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SE4C1_4", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_EE4A1_4", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_LH12_4", - "VBRK_LH12" - ], - [ - "CLK_HROW_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_SE2A2_4", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EL1BEG1_4", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_WW4B1_4", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_WR1END0_4", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_NW4END0_4", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_NE4BEG3_4", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_LH11_4", - "VBRK_LH11" - ], - [ - "CLK_HROW_EE4B3_4", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_WW4B0_4", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW2END1_4", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_LH8_4", - "VBRK_LH8" - ], - [ - "CLK_HROW_WW4END0_4", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW4A3_4", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_SE4C0_4", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_SW2A3_4", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WW4C0_4", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NW2A3_4", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE2A3_4", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_EE4C0_4", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_SE4BEG2_4", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_NE2A0_4", - "VBRK_NE2A0" - ] - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_BRAM_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_BRAM_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_BRAM_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_BRAM_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_BRAM_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_BRAM_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_BRAM_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_BRAM_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "HCLK_BRAM_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_BRAM_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_BRAM_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_BRAM_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_BRAM_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_BRAM_CK_IN9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_BRAM_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_BRAM_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_BRAM_CK_IN0", - "HCLK_VBRK_MUX_CLK0" - ], - [ - "HCLK_BRAM_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_BRAM_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_BRAM_CK_IN3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_BRAM_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_BRAM_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_BRAM_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_BRAM_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_BRAM_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_BRAM_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_BRAM_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_BRAM_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_BRAM_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_BRAM_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ] - ], - "tile_types": [ - "HCLK_BRAM", - "HCLK_VBRK" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_ER1BEG2_8", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_EE4B2_8", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_ER1BEG1_8", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_WW4B2_8", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_WW2A1_8", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_SE4C3_8", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_NW2A1_8", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_LH10_8", - "VBRK_LH10" - ], - [ - "CMT_TOP_LH11_8", - "VBRK_LH11" - ], - [ - "CMT_TOP_SW4A1_8", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_WW2END1_8", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_NW2A3_8", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_NE4BEG2_8", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_LH7_8", - "VBRK_LH7" - ], - [ - "CMT_TOP_SE4C0_8", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_NW4A1_8", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_EE2A2_8", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_SW2A1_8", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_SE2A2_8", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_WW4B1_8", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WW4A3_8", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_LH8_8", - "VBRK_LH8" - ], - [ - "CMT_TOP_NE2A2_8", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_WW4B3_8", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_EE2BEG1_8", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_WW2A3_8", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_SW2A2_8", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_WW4C0_8", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_NE4BEG1_8", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_NE4BEG0_8", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_SW4A0_8", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_EE4C3_8", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NE4C3_8", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_WW4A2_8", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_WL1END0_8", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_EE4B1_8", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_WR1END1_8", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_NE4C1_8", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_WW4END0_8", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_EE4BEG1_8", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_SW4END0_8", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_NE4C2_8", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_NW2A0_8", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_SW4END2_8", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_SW4END3_8", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SE2A3_8", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_WL1END3_8", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_LH6_8", - "VBRK_LH6" - ], - [ - "CMT_TOP_WW2END0_8", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_SE4BEG3_8", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_EL1BEG1_8", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_WL1END2_8", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_WR1END0_8", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_SW2A0_8", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_EE4A3_8", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_EE4B3_8", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_SE2A1_8", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_EL1BEG0_8", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WW4END3_8", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_NW4A2_8", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_EE4C0_8", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_SE4C1_8", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_WW4C3_8", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_EE2A3_8", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_LH12_8", - "VBRK_LH12" - ], - [ - "CMT_TOP_SW4END1_8", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_WW4B0_8", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_WW4A0_8", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_NW4END2_8", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_EE2BEG0_8", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_EE2BEG2_8", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_LH2_8", - "VBRK_LH2" - ], - [ - "CMT_TOP_SE4BEG1_8", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_WR1END3_8", - "VBRK_WR1END3" - ], - [ - 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"BRKH_INT_NN6E0", - "NN6END0" - ], - [ - "BRKH_INT_SS6C3", - "SS6B3" - ], - [ - "BRKH_INT_SE6C0", - "SE6B0" - ], - [ - "BRKH_INT_NN6B2", - "NN6C2" - ], - [ - "BRKH_INT_LV4", - "LV5" - ], - [ - "BRKH_INT_LV7", - "LV8" - ], - [ - "BRKH_INT_BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" - ], - [ - "BRKH_INT_LV16", - "LV17" - ], - [ - "BRKH_INT_NE6C2", - "NE6D2" - ], - [ - "BRKH_INT_SW2A1", - "SW2BEG1" - ], - [ - "BRKH_INT_BYP_BOUNCE7", - "BYP_BOUNCE_N3_7" - ], - [ - "BRKH_INT_LVB1", - "LVB1" - ], - [ - "BRKH_INT_NW6B1", - "NW6C1" - ], - [ - "BRKH_INT_NN6D1", - "NN6E1" - ], - [ - "BRKH_INT_NN2BEG3", - "NN2A3" - ], - [ - "BRKH_INT_WW4END_S0_0", - "WW4END0" - ], - [ - "BRKH_INT_NE6A0", - "NE6B0" - ], - [ - "BRKH_INT_SS6E1", - "SS6D1" - ], - [ - "BRKH_INT_SE6E2", - "SE6D2" - ], - [ - "BRKH_INT_LVB7", - "LVB7" - ], - [ - "BRKH_INT_SL1END3_SLOW", - "SL1BEG3" - ], - [ - "BRKH_INT_LV11", - "LV12" - ], - [ - "BRKH_INT_LV6", - "LV7" - ], - [ - "BRKH_INT_SS2END2", - "SS2A2" - ], - [ - "BRKH_INT_NN6D3", - "NN6E3" - ], - [ - "BRKH_INT_SS6B0", - "SS6A0" - ], - [ - "BRKH_INT_SS6END1", - "SS6E1" - ], - [ - "BRKH_INT_NN2A3", - "NN2END3" - ], - [ - "BRKH_INT_SE6B1", - "SE6A1" - ], - [ - "BRKH_INT_NN6BEG0", - "NN6A0" - ], - [ - "BRKH_INT_NN6BEG2", - "NN6A2" - ], - [ - "BRKH_INT_NN6A2", - "NN6B2" - ], - [ - "BRKH_INT_ER1BEG_S0", - "ER1BEG0" - ], - [ - "BRKH_INT_NN2BEG1", - "NN2A1" - ], - [ - "BRKH_INT_SS6B2", - "SS6A2" - ], - [ - "BRKH_INT_NW6C2", - "NW6D2" - ], - [ - "BRKH_INT_EL1BEG3", - "EL1BEG_N3" - ], - [ - "BRKH_INT_NE6C3", - "NE6D3" - ], - [ - "BRKH_INT_NW6B3", - "NW6C3" - ], - [ - "BRKH_INT_NR1BEG3_SLOW", - "NR1END3" - ], - [ - "BRKH_INT_SS6B1", - "SS6A1" - ], - [ - "BRKH_INT_NE6D2", - "NE6E2" - ], - [ - "BRKH_INT_NW6A1", - "NW6B1" - ], - [ - "BRKH_INT_SW6D2", - "SW6C2" - ], - [ - "BRKH_INT_LV0", - "LV1" - ], - [ - "BRKH_INT_SS6D3", - "SS6C3" - ], - [ - "BRKH_INT_SW2A0", - "SW2BEG0" - ], - [ - "BRKH_INT_NN6C3", - "NN6D3" - ], - [ - "BRKH_INT_NW6C1", - "NW6D1" - ], - [ - "BRKH_INT_SE6D2", - "SE6C2" - ], - [ - "BRKH_INT_NW2BEG2", - "NW2A2" - ], - [ - "BRKH_INT_SR1END_N3_3", - "SR1END_N3_3" - ], - [ - "BRKH_INT_LVB9", - "LVB9" - ], - [ - "BRKH_INT_NN6E3", - "NN6END3" - ], - [ - "BRKH_INT_SS6B3", - "SS6A3" - ], - [ - "BRKH_INT_WL1BEG3", - "WL1BEG_N3" - ], - [ - "BRKH_INT_NR1BEG0_SLOW", - "NR1END0" - ], - [ - "BRKH_INT_SW6B2", - "SW6A2" - ], - [ - "BRKH_INT_NN6D2", - "NN6E2" - ], - [ - "BRKH_INT_SS2END1", - "SS2A1" - ], - [ - "BRKH_INT_SE2A1", - "SE2BEG1" - ], - [ - "BRKH_INT_NE6C1", - "NE6D1" - ], - [ - "BRKH_INT_NW2BEG3", - "NW2A3" - ], - [ - "BRKH_INT_SS2END_N0_3", - "SS2END_N0_3" - ], - [ - "BRKH_INT_NN6A0", - "NN6B0" - ], - [ - "BRKH_INT_NW2BEG0", - "NW2A0" - ], - [ - "BRKH_INT_SE2A0", - "SE2BEG0" - ], - [ - "BRKH_INT_SS6D1", - "SS6C1" - ], - [ - "BRKH_INT_SS2A1", - "SS2BEG1" - ], - [ - "BRKH_INT_NE6D1", - "NE6E1" - ], - [ - "BRKH_INT_SE6E0", - "SE6D0" - ], - [ - "BRKH_INT_NN2A0", - "NN2END0" - ], - [ - "BRKH_INT_NE2BEG0", - "NE2A0" - ], - [ - "BRKH_INT_SE6B2", - "SE6A2" - ], - [ - "BRKH_INT_LV1", - "LV2" - ], - [ - "BRKH_INT_SE6D3", - "SE6C3" - ], - [ - "BRKH_INT_LVB8", - "LVB8" - ], - [ - "BRKH_INT_LVB6", - "LVB6" - ], - [ - "BRKH_INT_NL1END_S3_0", - "NL1END0" - ], - [ - "BRKH_INT_SS6E3", - "SS6D3" - ], - [ - "BRKH_INT_SS6END3", - "SS6E3" - ], - [ - "BRKH_INT_LV13", - "LV14" - ], - [ - "BRKH_INT_SS6E0", - "SS6D0" - ], - [ - "BRKH_INT_NE6A3", - "NE6B3" - ], - [ - "BRKH_INT_SW6B3", - "SW6A3" - ], - [ - "BRKH_INT_NW6C0", - "NW6D0" - ], - [ - "BRKH_INT_LV3", - "LV4" - ], - [ - "BRKH_INT_SR1END1_SLOW", - "SR1BEG1" - ], - [ - "BRKH_INT_NN6D0", - "NN6E0" - ], - [ - "BRKH_INT_LV12", - "LV13" - ], - [ - "BRKH_INT_SW6B0", - "SW6A0" - ], - [ - "BRKH_INT_NL1BEG1_SLOW", - "NL1END1" - ], - [ - "BRKH_INT_LV8", - "LV9" - ], - [ - "BRKH_INT_SS2A3", - "SS2BEG3" - ], - [ - "BRKH_INT_NN6BEG3", - "NN6A3" - ], - [ - "BRKH_INT_SS6END_N0_3", - "SS6END_N0_3" - ], - [ - "BRKH_INT_NE2BEG2", - "NE2A2" - ], - [ - "BRKH_INT_SS6A3", - "SS6BEG3" - ], - [ - "BRKH_INT_NW6D0", - "NW6E0" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_6", - "FAN_BOUNCE6" - ], - [ - "BRKH_INT_NR1BEG2_SLOW", - "NR1END2" - ], - [ - "BRKH_INT_LV15", - "LV16" - ], - [ - "BRKH_INT_NN6B3", - "NN6C3" - ], - [ - "BRKH_INT_LV2", - "LV3" - ], - [ - "BRKH_INT_SW2END3", - "SW2END_N0_3" - ], - [ - "BRKH_INT_NN6BEG1", - "NN6A1" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_0", - "FAN_BOUNCE0" - ], - [ - "BRKH_INT_SW2A2", - "SW2BEG2" - ], - [ - "BRKH_INT_NE6B3", - "NE6C3" - ], - [ - "BRKH_INT_SW6C2", - "SW6B2" - ], - [ - "BRKH_INT_NW6D1", - "NW6E1" - ], - [ - "BRKH_INT_WW2END3", - "WW2END_N0_3" - ], - [ - "BRKH_INT_NE6A2", - "NE6B2" - ], - [ - "BRKH_INT_SE6B3", - "SE6A3" - ], - [ - "BRKH_INT_SW2A3", - "SW2BEG3" - ], - [ - "BRKH_INT_NE6B2", - "NE6C2" - ], - [ - "BRKH_INT_SW6E2", - "SW6D2" - ], - [ - "BRKH_INT_NN2BEG2", - "NN2A2" - ], - [ - "BRKH_INT_NE6B1", - "NE6C1" - ], - [ - "BRKH_INT_NW6B2", - "NW6C2" - ], - [ - "BRKH_INT_WR1BEG_S0", - "WR1BEG0" - ], - [ - "BRKH_INT_NW6D2", - "NW6E2" - ], - [ - "BRKH_INT_NW6C3", - "NW6D3" - ], - [ - "BRKH_INT_SE6D0", - "SE6C0" - ], - [ - "BRKH_INT_NL1BEG0_SLOW", - "NL1END0" - ], - [ - "BRKH_INT_SW6B1", - "SW6A1" - ], - [ - "BRKH_INT_SW6END3", - "SW6END_N0_3" - ], - [ - "BRKH_INT_NN6A1", - "NN6B1" - ], - [ - "BRKH_INT_SW6E3", - "SW6D3" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_4", - "FAN_BOUNCE4" - ], - [ - "BRKH_INT_SS6D0", - "SS6C0" - ], - [ - "BRKH_INT_NE6D0", - "NE6E0" - ], - [ - "BRKH_INT_NE6D3", - "NE6E3" - ], - [ - "BRKH_INT_LV9", - "LV10" - ], - [ - "BRKH_INT_LVB11", - "LVB11" - ], - [ - "BRKH_INT_LVB5", - "LVB5" - ], - [ - "BRKH_INT_LVB4", - "LVB4" - ], - [ - "BRKH_INT_SW6C0", - "SW6B0" - ], - [ - "BRKH_INT_NN2BEG0", - "NN2A0" - ], - [ - "BRKH_INT_NN2END_S2_0", - "NN2END0" - ], - [ - "BRKH_INT_SS2END0", - "SS2A0" - ], - [ - "BRKH_INT_SS2A0", - "SS2BEG0" - ], - [ - "BRKH_INT_SE2A3", - "SE2BEG3" - ], - [ - "BRKH_INT_NE2BEG3", - "NE2A3" - ], - [ - "BRKH_INT_SE6E3", - "SE6D3" - ], - [ - "BRKH_INT_SW6E1", - "SW6D1" - ], - [ - "BRKH_INT_LV5", - "LV6" - ], - [ - "BRKH_INT_WL1END3", - "WL1END_N1_3" - ], - [ - "BRKH_INT_SE6E1", - "SE6D1" - ], - [ - "BRKH_INT_SS6C1", - "SS6B1" - ], - [ - "BRKH_INT_SS2END3", - "SS2A3" - ], - [ - "BRKH_INT_SS6C2", - "SS6B2" - ], - [ - "BRKH_INT_SE6C2", - "SE6B2" - ], - [ - "BRKH_INT_NN6B1", - "NN6C1" - ], - [ - "BRKH_INT_LVB2", - "LVB2" - ], - [ - "BRKH_INT_LVB10", - "LVB10" - ], - [ - "BRKH_INT_SS6A0", - "SS6BEG0" - ], - [ - "BRKH_INT_NW6D3", - "NW6E3" - ], - [ - "BRKH_INT_NL1BEG2_SLOW", - "NL1END2" - ], - [ - "BRKH_INT_LV10", - "LV11" - ], - [ - "BRKH_INT_SS6A1", - "SS6BEG1" - ], - [ - "BRKH_INT_NE6B0", - "NE6C0" - ], - [ - "BRKH_INT_SS6END0", - "SS6E0" - ], - [ - "BRKH_INT_NN6B0", - "NN6C0" - ], - [ - "BRKH_INT_SR1END2_SLOW", - "SR1BEG2" - ], - [ - "BRKH_INT_NN6E2", - "NN6END2" - ], - [ - "BRKH_INT_SW6D1", - "SW6C1" - ], - [ - "BRKH_INT_SW6C3", - "SW6B3" - ], - [ - "BRKH_INT_SW6C1", - "SW6B1" - ], - [ - "BRKH_INT_WR1END_S1_0", - "WR1END0" - ], - [ - "BRKH_INT_NE2BEG1", - "NE2A1" - ], - [ - "BRKH_INT_NN6E1", - "NN6END1" - ], - [ - "BRKH_INT_NW2END_S0_0", - "NW2END0" - ], - [ - "BRKH_INT_NN6C2", - "NN6D2" - ], - [ - "BRKH_INT_NN6A3", - "NN6B3" - ], - [ - "BRKH_INT_NW2BEG1", - "NW2A1" - ], - [ - "BRKH_INT_SE6D1", - "SE6C1" - ], - [ - "BRKH_INT_NW6A0", - "NW6B0" - ], - [ - "BRKH_INT_LVB3", - "LVB3" - ], - [ - "BRKH_INT_SL1END1_SLOW", - "SL1BEG1" - ], - [ - "BRKH_INT_SW6D0", - "SW6C0" - ], - [ - "BRKH_INT_SE6B0", - "SE6A0" - ], - [ - "BRKH_INT_NR1BEG1_SLOW", - "NR1END1" - ], - [ - "BRKH_INT_NE2END_S3_0", - "NE2END0" - ], - [ - "BRKH_INT_NE6C0", - "NE6D0" - ], - [ - "BRKH_INT_SL1END2_SLOW", - "SL1BEG2" - ], - [ - "BRKH_INT_SE2A2", - "SE2BEG2" - ], - [ - "BRKH_INT_SR1END3_SLOW", - "SR1BEG3" - ], - [ - "BRKH_INT_NN2A1", - "NN2END1" - ], - [ - "BRKH_INT_SE6C1", - "SE6B1" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_2", - "FAN_BOUNCE2" - ], - [ - "BRKH_INT_NE6A1", - "NE6B1" - ], - [ - "BRKH_INT_SE6C3", - "SE6B3" - ], - [ - "BRKH_INT_BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "BRKH_INT_NW6END_S0_0", - "NW6END0" - ], - [ - "BRKH_INT_NW6B0", - "NW6C0" - ], - [ - "BRKH_INT_SS6C0", - "SS6B0" - ], - [ - "BRKH_INT_BYP_BOUNCE3", - "BYP_BOUNCE_N3_3" - ], - [ - "BRKH_INT_SS6END2", - "SS6E2" - ], - [ - "BRKH_INT_EL1END_S3_0", - "EL1END0" - ], - [ - "BRKH_INT_NW6A3", - "NW6B3" - ], - [ - "BRKH_INT_NW6A2", - "NW6B2" - ], - [ - "BRKH_INT_SS6D2", - "SS6C2" - ], - [ - "BRKH_INT_SW6E0", - "SW6D0" - ], - [ - "BRKH_INT_SW6D3", - "SW6C3" - ], - [ - "BRKH_INT_LV17", - "LV18" - ], - [ - "BRKH_INT_LVB12", - "LVB12" - ], - [ - "BRKH_INT_SS6A2", - "SS6BEG2" - ], - [ - "BRKH_INT_NN6C1", - "NN6D1" - ], - [ - "BRKH_INT_NN2A2", - "NN2END2" - ], - [ - "BRKH_INT_SL1END0_SLOW", - "SL1BEG0" - ], - [ - "BRKH_INT_SS6E2", - "SS6D2" - ] - ], - "tile_types": [ - "BRKH_INT", - "INT_R" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_INT_INTERFACE_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_CK_IN2", - "HCLK_CK_IN2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_INT_INTERFACE_CK_IN3", - "HCLK_CK_IN3" - ], - [ - "HCLK_INT_INTERFACE_CK_IN0", - "HCLK_CK_IN0" - ], - [ - "HCLK_INT_INTERFACE_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_INT_PERFCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - "HCLK_INT_INTERFACE_CCIO0", - "HCLK_CCIO0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_CK_BUFRCLK3" - ], - [ - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_CCIO2" - ], - [ - "HCLK_INT_INTERFACE_CK_IN11", - "HCLK_CK_IN11" - ], - [ - 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"VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_IMUX16_7", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX37_7", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_LOGIC_OUTS_B16_7", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_CTRL0_7", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_LOGIC_OUTS_B21_7", - "VBRK_EXT_LOGIC_OUTS_B21" - ], - [ - "GTPE2_LOGIC_OUTS_B2_7", - "VBRK_EXT_LOGIC_OUTS_B2" - ], - [ - "GTPE2_IMUX36_7", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_IMUX33_7", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX25_7", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_BYP7_7", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX2_7", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX34_7", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_IMUX26_7", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_FAN1_7", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_LOGIC_OUTS_B7_7", - "VBRK_EXT_LOGIC_OUTS_B7" - ], - [ - "GTPE2_IMUX29_7", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B14_7", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_BYP3_7", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX18_7", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_LOGIC_OUTS_B13_7", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_FAN4_7", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX39_7", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX24_7", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_LOGIC_OUTS_B3_7", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_BYP4_7", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX7_7", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX40_7", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_CLK1_7", - "VBRK_EXT_CLK1" - ] - ], - "tile_types": [ - "GTP_CHANNEL_3", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - -2 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_CMT_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_CMT_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_CMT_CK_IN9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_CMT_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_CMT_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK3", - "HCLK_VBRK_PHSR_PERFCLK3" - ], - [ - "HCLK_CMT_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_CMT_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK1", - "HCLK_VBRK_PHSR_PERFCLK1" - ], - [ - "HCLK_CMT_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_CMT_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_CMT_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_CMT_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_CMT_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_CMT_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_CMT_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_CMT_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_CMT_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK0", - "HCLK_VBRK_PHSR_PERFCLK0" - ], - [ - "HCLK_CMT_CK_IN0", - "HCLK_VBRK_MUX_CLK0" - ], - [ - "HCLK_CMT_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_CMT_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_CMT_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_CMT_CK_IN3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_CMT_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_CMT_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_CMT_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_CMT_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_CMT_MUX_PHSR_PERFCLK2", - "HCLK_VBRK_PHSR_PERFCLK2" - ], - [ - "HCLK_CMT_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_CMT_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_CMT_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_CMT_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_CMT_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ] - ], - "tile_types": [ - "HCLK_CMT_L", - "HCLK_VBRK" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "BRKH_CLB_COUT0_L", - "CLBLL_LL_CIN" - ], - [ - "BRKH_CLB_COUT1_L", - "CLBLL_L_CIN" - ] - ], - "tile_types": [ - "BRKH_CLB", - "CLBLL_L" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CMT_FIFO_L_CTRL1_8", - "INT_INTERFACE_CTRL1" - ], - [ - "CMT_FIFO_L_IMUX22_8", - "INT_INTERFACE_IMUX22" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS1_8", - "INT_INTERFACE_LOGIC_OUTS_B1" - ], - [ - "CMT_FIFO_L_CLK1_8", - "INT_INTERFACE_CLK1" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS12_8", - "INT_INTERFACE_LOGIC_OUTS_B12" - ], - [ - "CMT_FIFO_L_BYP3_8", - "INT_INTERFACE_BYP3" - ], - [ - "CMT_FIFO_EE4C3_8", - "INT_INTERFACE_EE4C3" - ], - [ - "CMT_FIFO_L_BYP6_8", - "INT_INTERFACE_BYP6" - ], - [ - "CMT_FIFO_L_IMUX36_8", - "INT_INTERFACE_IMUX36" - ], - [ - "CMT_FIFO_L_BYP7_8", - "INT_INTERFACE_BYP7" - ], - [ - "CMT_FIFO_LH8_8", - "INT_INTERFACE_LH8" - ], - [ - "CMT_FIFO_L_IMUX35_8", - "INT_INTERFACE_IMUX35" - ], - [ - "CMT_FIFO_WL1END0_8", - "INT_INTERFACE_WL1END0" - ], - [ - "CMT_FIFO_SW2A2_8", - "INT_INTERFACE_SW2A2" - ], - [ - "CMT_FIFO_EE4B0_8", - "INT_INTERFACE_EE4B0" - ], - [ - "CMT_FIFO_EE2BEG3_8", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CMT_FIFO_EE4B2_8", - "INT_INTERFACE_EE4B2" - ], - [ - "CMT_FIFO_L_IMUX32_8", - "INT_INTERFACE_IMUX32" - ], - [ - "CMT_FIFO_SW4END2_8", - "INT_INTERFACE_SW4END2" - ], - [ - "CMT_FIFO_EL1BEG2_8", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CMT_FIFO_LH10_8", - "INT_INTERFACE_LH10" - ], - [ - "CMT_FIFO_NW2A3_8", - "INT_INTERFACE_NW2A3" - ], - [ - "CMT_FIFO_L_IMUX27_8", - "INT_INTERFACE_IMUX27" - ], - [ - "CMT_FIFO_L_CLK0_8", - "INT_INTERFACE_CLK0" - ], - [ - "CMT_FIFO_WR1END3_8", - "INT_INTERFACE_WR1END3" - ], - [ - "CMT_FIFO_EE4B1_8", - "INT_INTERFACE_EE4B1" - ], - [ - "CMT_FIFO_L_IMUX13_8", - "INT_INTERFACE_IMUX13" - ], - [ - "CMT_FIFO_EE4C1_8", - "INT_INTERFACE_EE4C1" - ], - [ - "CMT_FIFO_L_IMUX29_8", - "INT_INTERFACE_IMUX29" - ], - [ - "CMT_FIFO_WW4END0_8", - "INT_INTERFACE_WW4END0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS18_8", - "INT_INTERFACE_LOGIC_OUTS_B18" - ], - [ - "CMT_FIFO_NE4C3_8", - "INT_INTERFACE_NE4C3" - ], - [ - "CMT_FIFO_L_IMUX28_8", - "INT_INTERFACE_IMUX28" - ], - [ - "CMT_FIFO_EE4BEG0_8", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CMT_FIFO_WL1END2_8", - "INT_INTERFACE_WL1END2" - ], - [ - "CMT_FIFO_L_IMUX24_8", - "INT_INTERFACE_IMUX24" - ], - [ - "CMT_FIFO_L_IMUX18_8", - "INT_INTERFACE_IMUX18" - ], - [ - "CMT_FIFO_NW4A1_8", - "INT_INTERFACE_NW4A1" - ], - [ - "CMT_FIFO_EE2A2_8", - "INT_INTERFACE_EE2A2" - ], - [ - "CMT_FIFO_WW4C0_8", - "INT_INTERFACE_WW4C0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS23_8", - "INT_INTERFACE_LOGIC_OUTS_B23" - ], - [ - "CMT_FIFO_LH4_8", - "INT_INTERFACE_LH4" - ], - [ - "CMT_FIFO_ER1BEG0_8", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CMT_FIFO_L_IMUX47_8", - "INT_INTERFACE_IMUX47" - ], - [ - "CMT_FIFO_WW4C3_8", - "INT_INTERFACE_WW4C3" - ], - [ - "CMT_FIFO_SE4BEG0_8", - "INT_INTERFACE_SE4BEG0" - ], - [ - "FIFO_DQS_IOTOPHASER_3", - "L_INT_INTER_DQS_IOTOPHASER" - ], - [ - "CMT_FIFO_L_IMUX41_8", - "INT_INTERFACE_IMUX41" - ], - [ - "CMT_FIFO_L_IMUX12_8", - "INT_INTERFACE_IMUX12" - ], - [ - "CMT_FIFO_L_IMUX4_8", - "INT_INTERFACE_IMUX4" - ], - [ - "CMT_FIFO_L_IMUX20_8", - "INT_INTERFACE_IMUX20" - ], - [ - "CMT_FIFO_NW2A2_8", - "INT_INTERFACE_NW2A2" - ], - [ - "CMT_FIFO_NE4BEG3_8", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS8_8", - "INT_INTERFACE_LOGIC_OUTS_B8" - ], - [ - "CMT_FIFO_EE4A1_8", - "INT_INTERFACE_EE4A1" - ], - [ - "CMT_FIFO_L_IMUX43_8", - "INT_INTERFACE_IMUX43" - ], - [ - "CMT_FIFO_EE4BEG2_8", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CMT_FIFO_L_IMUX34_8", - "INT_INTERFACE_IMUX34" - ], - [ - "CMT_FIFO_L_IMUX39_8", - "INT_INTERFACE_IMUX39" - ], - [ - "CMT_FIFO_WR1END2_8", - "INT_INTERFACE_WR1END2" - ], - [ - "CMT_FIFO_NE2A1_8", - "INT_INTERFACE_NE2A1" - ], - [ - "CMT_FIFO_NW2A1_8", - "INT_INTERFACE_NW2A1" - ], - [ - "CMT_FIFO_L_IMUX33_8", - "INT_INTERFACE_IMUX33" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS9_8", - "INT_INTERFACE_LOGIC_OUTS_B9" - ], - [ - "CMT_FIFO_LH2_8", - "INT_INTERFACE_LH2" - ], - [ - "CMT_FIFO_SW4A3_8", - "INT_INTERFACE_SW4A3" - ], - [ - "CMT_FIFO_SE4C0_8", - "INT_INTERFACE_SE4C0" - ], - [ - "CMT_FIFO_EL1BEG1_8", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CMT_FIFO_WW4A1_8", - "INT_INTERFACE_WW4A1" - ], - [ - "CMT_FIFO_NE4C0_8", - "INT_INTERFACE_NE4C0" - ], - [ - "CMT_FIFO_L_IMUX9_8", - "INT_INTERFACE_IMUX9" - ], - [ - "CMT_FIFO_L_IMUX37_8", - "INT_INTERFACE_IMUX37" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS7_8", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CMT_FIFO_L_IMUX25_8", - "INT_INTERFACE_IMUX25" - ], - [ - "CMT_FIFO_L_CTRL0_8", - "INT_INTERFACE_CTRL0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS20_8", - "INT_INTERFACE_LOGIC_OUTS_B20" - ], - [ - "CMT_FIFO_L_IMUX15_8", - "INT_INTERFACE_IMUX15" - ], - [ - "CMT_FIFO_L_IMUX26_8", - "INT_INTERFACE_IMUX26" - ], - [ - "CMT_FIFO_SE2A0_8", - "INT_INTERFACE_SE2A0" - ], - [ - "CMT_FIFO_WW2A3_8", - "INT_INTERFACE_WW2A3" - ], - [ - "CMT_FIFO_WW2END2_8", - "INT_INTERFACE_WW2END2" - ], - [ - "CMT_FIFO_SE4C1_8", - "INT_INTERFACE_SE4C1" - ], - [ - "CMT_FIFO_L_IMUX42_8", - "INT_INTERFACE_IMUX42" - ], - [ - "CMT_FIFO_SW4END1_8", - "INT_INTERFACE_SW4END1" - ], - [ - "CMT_FIFO_L_IMUX17_8", - "INT_INTERFACE_IMUX17" - ], - [ - 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[ - "BRAM_CASCOUT_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" - ], - [ - "BRAM_PMVBRAM_SELECT4", - "HCLK_BRAM_PMVBRAM_SELECT4" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" - ], - [ - "BRAM_PMVBRAM_ODIV4", - "HCLK_BRAM_PMVBRAM_ODIV4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" - ], - [ - "BRAM_PMVBRAM_SELECT1", - "HCLK_BRAM_PMVBRAM_SELECT1" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" - ], - [ - "BRAM_FIFO36_CASCADEINB", - "HCLK_BRAM_CASCADEB_L" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" - ], - [ - "BRAM_PMVBRAM_SELECT2", - "HCLK_BRAM_PMVBRAM_SELECT2" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" - ], - [ - "BRAM_CASCOUT_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" - ], - [ - "BRAM_PMVBRAM_ODIV2", - "HCLK_BRAM_PMVBRAM_ODIV2" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" - ], - [ - "BRAM_CASCINBOT_ADDRARDADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" - ], - [ - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" - ], - [ - "BRAM_CASCOUT_ADDRBWRADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" - ] - ], - "tile_types": [ - "BRAM_L", - "HCLK_BRAM" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "DSP_PCOUT33", - "HCLK_DSP_PCIN33" - ], - [ - "DSP_BCOUT11", - "HCLK_DSP_BCIN11" - ], - [ - "DSP_PCOUT8", - "HCLK_DSP_PCIN8" - ], - [ - "DSP_ACOUT22", - "HCLK_DSP_ACIN22" - ], - [ - "DSP_PCOUT37", - "HCLK_DSP_PCIN37" - ], - [ - "DSP_ACOUT17", - "HCLK_DSP_ACIN17" - ], - [ - "DSP_BCOUT14", - "HCLK_DSP_BCIN14" - ], - [ - "DSP_ACOUT20", - "HCLK_DSP_ACIN20" - ], - [ - "DSP_BCOUT8", - "HCLK_DSP_BCIN8" - ], - [ - "DSP_PCOUT6", - "HCLK_DSP_PCIN6" - ], - [ - "DSP_ACOUT7", - "HCLK_DSP_ACIN7" - ], - [ - "DSP_ACOUT24", - "HCLK_DSP_ACIN24" - ], - [ - "DSP_BCOUT0", - "HCLK_DSP_BCIN0" - ], - [ - "DSP_ACOUT0", - "HCLK_DSP_ACIN0" - ], - [ - "DSP_PCOUT41", - "HCLK_DSP_PCIN41" - ], - [ - "DSP_ACOUT16", - "HCLK_DSP_ACIN16" - ], - [ - "DSP_BCOUT17", - "HCLK_DSP_BCIN17" - ], - [ - "DSP_BCOUT2", - "HCLK_DSP_BCIN2" - ], - [ - "DSP_ACOUT4", - "HCLK_DSP_ACIN4" - ], - [ - "DSP_PCOUT11", - "HCLK_DSP_PCIN11" - ], - [ - "DSP_PCOUT31", - "HCLK_DSP_PCIN31" - ], - [ - "DSP_ACOUT9", - "HCLK_DSP_ACIN9" - ], - [ - "DSP_PCOUT18", - "HCLK_DSP_PCIN18" - ], - [ - "DSP_PCOUT39", - "HCLK_DSP_PCIN39" - ], - [ - "DSP_PCOUT9", - "HCLK_DSP_PCIN9" - ], - [ - "DSP_BCOUT12", - "HCLK_DSP_BCIN12" - ], - [ - "DSP_ACOUT12", - "HCLK_DSP_ACIN12" - ], - [ - "DSP_PCOUT13", - "HCLK_DSP_PCIN13" - ], - [ - "DSP_ACOUT14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_PCOUT21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_BCOUT15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_BCOUT9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_PCOUT27", - "HCLK_DSP_PCIN27" - ], - [ - "DSP_PCOUT3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_PCOUT24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_BCOUT16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_PCOUT38", - "HCLK_DSP_PCIN38" - ], - [ - "DSP_BCOUT5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_ACOUT23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_CARRYCASCOUT", - "HCLK_DSP_CARRYCASCIN" - ], - [ - "DSP_PCOUT40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_ACOUT10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_BCOUT6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_PCOUT20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_ACOUT21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_BCOUT4", - "HCLK_DSP_BCIN4" - ], - [ - "DSP_BCOUT13", - "HCLK_DSP_BCIN13" - ], - [ - "DSP_BCOUT10", - "HCLK_DSP_BCIN10" - ], - [ - "DSP_ACOUT29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_PCOUT42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_PCOUT23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_PCOUT26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_ACOUT8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_PCOUT25", - "HCLK_DSP_PCIN25" - ], - [ - "DSP_ACOUT5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_PCOUT10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_PCOUT5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_PCOUT32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_PCOUT0", - "HCLK_DSP_PCIN0" - ], - [ - "DSP_BCOUT3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_PCOUT16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_PCOUT34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_PCOUT12", - "HCLK_DSP_PCIN12" - ], - [ - "DSP_PCOUT22", - "HCLK_DSP_PCIN22" - ], - [ - "DSP_ACOUT25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_BCOUT1", - "HCLK_DSP_BCIN1" - ], - [ - "DSP_ACOUT2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_PCOUT30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_BCOUT7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_PCOUT17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_PCOUT7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_PCOUT2", - "HCLK_DSP_PCIN2" - ], - [ - "DSP_ACOUT3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_PCOUT35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_PCOUT47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_PCOUT14", - "HCLK_DSP_PCIN14" - ], - [ - "DSP_MULTSIGNOUT", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_ACOUT26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_PCOUT43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_ACOUT6", - "HCLK_DSP_ACIN6" - ], - [ - "DSP_ACOUT28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_PCOUT36", - "HCLK_DSP_PCIN36" - ], - [ - "DSP_ACOUT27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_PCOUT15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_ACOUT1", - "HCLK_DSP_ACIN1" - ], - [ - "DSP_PCOUT1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_PCOUT45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_PCOUT29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_ACOUT13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_ACOUT18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_PCOUT28", - "HCLK_DSP_PCIN28" - ], - [ - "DSP_PCOUT44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_ACOUT19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_PCOUT19", - "HCLK_DSP_PCIN19" - ], - [ - "DSP_PCOUT46", - "HCLK_DSP_PCIN46" - ], - [ - "DSP_ACOUT15", - "HCLK_DSP_ACIN15" - ], - [ - "DSP_ACOUT11", - "HCLK_DSP_ACIN11" - ], - [ - "DSP_PCOUT4", - "HCLK_DSP_PCIN4" - ] - ], - "tile_types": [ - "DSP_R", - "HCLK_DSP_R" - ], - "grid_deltas": [ - 0, - -5 - ] - }, - { - "wire_pairs": [ - [ - "CFG_CENTER_ER1BEG1_0", - "INT_FEEDTHRU_2_ER1BEG1" - ], - [ - "CFG_CENTER_SW4A2_0", - "INT_FEEDTHRU_2_SW4A2" - ], - [ - "CFG_CENTER_SE4C0_0", - "INT_FEEDTHRU_2_SE4C0" - ], - [ - "CFG_CENTER_EE4BEG0_0", - "INT_FEEDTHRU_2_EE4BEG0" - ], - [ - "CFG_CENTER_WR1END2_0", - "INT_FEEDTHRU_2_WR1END2" - ], - [ - "CFG_CENTER_WW2A3_0", - "INT_FEEDTHRU_2_WW2A3" - ], - [ - "CFG_CENTER_WW4B1_0", - "INT_FEEDTHRU_2_WW4B1" - ], - [ - "CFG_CENTER_SW2A3_0", - "INT_FEEDTHRU_2_SW2A3" - ], - [ - "CFG_CENTER_WW4END1_0", - "INT_FEEDTHRU_2_WW4END1" - ], - [ - "CFG_CENTER_SE4BEG3_0", - "INT_FEEDTHRU_2_SE4BEG3" - ], - [ - "CFG_CENTER_NW2A3_0", - "INT_FEEDTHRU_2_NW2A3" - ], - [ - "CFG_CENTER_WW4B2_0", - "INT_FEEDTHRU_2_WW4B2" - ], - [ - "CFG_CENTER_NW4END3_0", - "INT_FEEDTHRU_2_NW4END3" - ], - [ - "CFG_CENTER_NW4A2_0", - "INT_FEEDTHRU_2_NW4A2" - ], - [ - "CFG_CENTER_LH7_0", - "INT_FEEDTHRU_2_LH7" - ], - [ - "CFG_CENTER_LH11_0", - "INT_FEEDTHRU_2_LH11" - ], - [ - "CFG_CENTER_LH5_0", - "INT_FEEDTHRU_2_LH5" - ], - [ - "CFG_CENTER_LH3_0", - "INT_FEEDTHRU_2_LH3" - ], - [ - "CFG_CENTER_WW4A2_0", - "INT_FEEDTHRU_2_WW4A2" - ], - [ - "CFG_CENTER_EE4B1_0", - "INT_FEEDTHRU_2_EE4B1" - ], - [ - "CFG_CENTER_WW4A1_0", - "INT_FEEDTHRU_2_WW4A1" - ], - [ - "CFG_CENTER_EE2A3_0", - "INT_FEEDTHRU_2_EE2A3" - ], - [ - "CFG_CENTER_SE2A2_0", - "INT_FEEDTHRU_2_SE2A2" - ], - [ - "CFG_CENTER_NW4A3_0", - "INT_FEEDTHRU_2_NW4A3" - ], - [ - "CFG_CENTER_NW2A2_0", - "INT_FEEDTHRU_2_NW2A2" - ], - [ - "CFG_CENTER_WW2END2_0", - "INT_FEEDTHRU_2_WW2END2" - ], - [ - "CFG_CENTER_LH12_0", - "INT_FEEDTHRU_2_LH12" - ], - [ - "CFG_CENTER_WW2A0_0", - "INT_FEEDTHRU_2_WW2A0" - ], - [ - "CFG_CENTER_LH4_0", - "INT_FEEDTHRU_2_LH4" - ], - [ - "CFG_CENTER_NE2A1_0", - "INT_FEEDTHRU_2_NE2A1" - ], - [ - "CFG_CENTER_LH6_0", - "INT_FEEDTHRU_2_LH6" - ], - [ - "CFG_CENTER_WW2END1_0", - "INT_FEEDTHRU_2_WW2END1" - ], - [ - "CFG_CENTER_WL1END0_0", - "INT_FEEDTHRU_2_WL1END0" - ], - [ - "CFG_CENTER_EE4B3_0", - "INT_FEEDTHRU_2_EE4B3" - ], - [ - "CFG_CENTER_SW2A1_0", - "INT_FEEDTHRU_2_SW2A1" - ], - [ - "CFG_CENTER_EE4B2_0", - "INT_FEEDTHRU_2_EE4B2" - ], - [ - "CFG_CENTER_NW4END2_0", - "INT_FEEDTHRU_2_NW4END2" - ], - [ - "CFG_CENTER_EE4C2_0", - "INT_FEEDTHRU_2_EE4C2" - ], - [ - "CFG_CENTER_NE4C0_0", - "INT_FEEDTHRU_2_NE4C0" - ], - [ - "CFG_CENTER_EE4C1_0", - "INT_FEEDTHRU_2_EE4C1" - ], - [ - "CFG_CENTER_EE2BEG3_0", - "INT_FEEDTHRU_2_EE2BEG3" - ], - [ - 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"INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "PCIE_BYP4_R_15", - "INT_INTERFACE_BYP4" - ] - ], - "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -5 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK14" - ], - [ - "CLK_FEED_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK5" - ], - [ - "CLK_FEED_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK17" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK18" - ], - [ - "CLK_FEED_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK1" - ], - [ - "CLK_FEED_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK4" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_HROW_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK7" - ], - [ - "CLK_FEED_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK26" - ], - [ - "CLK_FEED_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK13" - ], - [ - "CLK_FEED_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK8" - ], - [ - "CLK_FEED_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK30" - ], - [ - "CLK_FEED_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK2" - ], - [ - "CLK_FEED_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK6" - ], - [ - "CLK_FEED_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK3" - ], - [ - "CLK_FEED_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK27" - ], - [ - "CLK_FEED_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK16" - ], - [ - "CLK_FEED_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK29" - ], - [ - "CLK_FEED_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK28" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK24" - ], - [ - "CLK_FEED_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK23" - ], - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK12" - ], - [ - "CLK_FEED_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK10" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK19" - ], - [ - "CLK_FEED_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK22" - ], - [ - "CLK_FEED_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK15" - ], - [ - "CLK_FEED_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK21" - ], - [ - "CLK_FEED_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK25" - ] - ], - "tile_types": [ - "CLK_FEED", - "CLK_HROW_BOT_R" - ], - "grid_deltas": [ - 0, - -5 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLK_FEED_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLK_FEED_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLK_FEED_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLK_FEED_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLK_FEED_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_LH3", - "VBRK_LH3" - ], - [ - "CLK_FEED_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLK_FEED_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLK_FEED_LH8", - "VBRK_LH8" - ], - [ - "CLK_FEED_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLK_FEED_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLK_FEED_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLK_FEED_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLK_FEED_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLK_FEED_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLK_FEED_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLK_FEED_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLK_FEED_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLK_FEED_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLK_FEED_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLK_FEED_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLK_FEED_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLK_FEED_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLK_FEED_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLK_FEED_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLK_FEED_LH12", - "VBRK_LH12" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_NE2A2", - "VBRK_NE2A2" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_WW4C2", - "VBRK_WW4C2" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLK_FEED_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLK_FEED_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLK_FEED_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLK_FEED_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLK_FEED_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLK_FEED_LH2", - "VBRK_LH2" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLK_FEED_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_EE4B1", - "VBRK_EE4B1" - ], - [ - "CLK_FEED_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLK_FEED_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLK_FEED_LH7", - "VBRK_LH7" - ], - [ - "CLK_FEED_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLK_FEED_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLK_FEED_EE4BEG2", - "VBRK_EE4BEG2" - ] - ], - "tile_types": [ - "CLK_MTBF2", - "VBRK" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "DSP_0_ACIN8", - "DSP_ACOUT8" - ], - [ - "DSP_0_PCIN1", - "DSP_PCOUT1" - ], - [ - "DSP_0_PCIN12", - "DSP_PCOUT12" - ], - [ - "DSP_0_ACIN26", - "DSP_ACOUT26" - ], - [ - "DSP_0_ACIN4", - "DSP_ACOUT4" - ], - [ - "DSP_0_PCIN21", - "DSP_PCOUT21" - ], - [ - "DSP_0_PCIN36", - "DSP_PCOUT36" - ], - [ - "DSP_0_PCIN42", - "DSP_PCOUT42" - ], - [ - "DSP_0_ACIN9", - "DSP_ACOUT9" - ], - [ - "DSP_0_BCIN9", - "DSP_BCOUT9" - ], - [ - "DSP_0_MULTSIGNIN", - "DSP_MULTSIGNOUT" - ], - [ - "DSP_0_BCIN0", - "DSP_BCOUT0" - ], - [ - "DSP_0_PCIN39", - "DSP_PCOUT39" - ], - [ - "DSP_0_ACIN27", - "DSP_ACOUT27" - ], - [ - "DSP_0_ACIN1", - "DSP_ACOUT1" - ], - [ - "DSP_0_BCIN17", - "DSP_BCOUT17" - ], - [ - "DSP_0_PCIN16", - "DSP_PCOUT16" - ], - [ - "DSP_0_ACIN6", - "DSP_ACOUT6" - ], - [ - "DSP_0_ACIN7", - "DSP_ACOUT7" - ], - [ - "DSP_0_ACIN22", - "DSP_ACOUT22" - ], - [ - "DSP_0_PCIN46", - "DSP_PCOUT46" - ], - [ - "DSP_0_ACIN12", - "DSP_ACOUT12" - ], - [ - "DSP_0_PCIN13", - "DSP_PCOUT13" - ], - [ - "DSP_0_PCIN8", - "DSP_PCOUT8" - ], - [ - "DSP_0_PCIN26", - "DSP_PCOUT26" - ], - [ - "DSP_0_PCIN41", - "DSP_PCOUT41" - ], - [ - "DSP_0_PCIN19", - "DSP_PCOUT19" - ], - [ - "DSP_0_PCIN24", - "DSP_PCOUT24" - ], - [ - "DSP_0_BCIN16", - "DSP_BCOUT16" - ], - [ - "DSP_0_BCIN8", - "DSP_BCOUT8" - ], - [ - "DSP_0_ACIN15", - "DSP_ACOUT15" - ], - [ - "DSP_0_BCIN2", - "DSP_BCOUT2" - ], - [ - "DSP_0_PCIN14", - "DSP_PCOUT14" - ], - [ - "DSP_0_BCIN7", - "DSP_BCOUT7" - ], - [ - "DSP_0_PCIN5", - "DSP_PCOUT5" - ], - [ - "DSP_0_PCIN34", - "DSP_PCOUT34" - ], - [ - "DSP_0_PCIN29", - "DSP_PCOUT29" - ], - [ - "DSP_0_ACIN25", - "DSP_ACOUT25" - ], - [ - "DSP_0_PCIN25", - "DSP_PCOUT25" - ], - [ - "DSP_0_BCIN3", - "DSP_BCOUT3" - ], - [ - "DSP_0_BCIN14", - "DSP_BCOUT14" - ], - [ - "DSP_0_PCIN4", - "DSP_PCOUT4" - ], - [ - "DSP_0_BCIN13", - "DSP_BCOUT13" - ], - [ - "DSP_0_ACIN24", - "DSP_ACOUT24" - ], - [ - "DSP_0_BCIN1", - "DSP_BCOUT1" - ], - [ - "DSP_0_ACIN14", - "DSP_ACOUT14" - ], - [ - "DSP_0_BCIN11", - "DSP_BCOUT11" - ], - [ - "DSP_0_PCIN10", - "DSP_PCOUT10" - ], - [ - "DSP_0_PCIN23", - "DSP_PCOUT23" - ], - [ - "DSP_0_PCIN28", - "DSP_PCOUT28" - ], - [ - "DSP_0_PCIN17", - "DSP_PCOUT17" - ], - [ - "DSP_0_PCIN40", - "DSP_PCOUT40" - ], - [ - "DSP_0_BCIN5", - "DSP_BCOUT5" - ], - [ - "DSP_0_BCIN15", - "DSP_BCOUT15" - ], - [ - "DSP_0_PCIN30", - "DSP_PCOUT30" - ], - [ - "DSP_0_PCIN18", - "DSP_PCOUT18" - ], - [ - "DSP_0_PCIN9", - "DSP_PCOUT9" - ], - [ - "DSP_0_PCIN6", - "DSP_PCOUT6" - ], - [ - "DSP_0_ACIN3", - "DSP_ACOUT3" - ], - [ - "DSP_0_PCIN38", - "DSP_PCOUT38" - ], - [ - "DSP_0_PCIN11", - "DSP_PCOUT11" - ], - [ - "DSP_0_ACIN11", - "DSP_ACOUT11" - ], - [ - "DSP_0_ACIN19", - "DSP_ACOUT19" - ], - [ - "DSP_0_ACIN16", - "DSP_ACOUT16" - ], - [ - "DSP_0_ACIN2", - "DSP_ACOUT2" - ], - [ - "DSP_0_ACIN23", - "DSP_ACOUT23" - ], - [ - "DSP_0_PCIN0", - "DSP_PCOUT0" - ], - [ - "DSP_0_PCIN20", - "DSP_PCOUT20" - ], - [ - "DSP_0_PCIN35", - "DSP_PCOUT35" - ], - [ - "DSP_0_ACIN10", - "DSP_ACOUT10" - ], - [ - "DSP_0_ACIN29", - "DSP_ACOUT29" - ], - [ - "DSP_0_ACIN20", - "DSP_ACOUT20" - ], - [ - "DSP_0_ACIN0", - "DSP_ACOUT0" - ], - [ - "DSP_0_ACIN17", - "DSP_ACOUT17" - ], - [ - "DSP_0_BCIN12", - "DSP_BCOUT12" - ], - [ - "DSP_0_PCIN43", - "DSP_PCOUT43" - ], - [ - "DSP_0_PCIN47", - "DSP_PCOUT47" - ], - [ - "DSP_0_ACIN13", - "DSP_ACOUT13" - ], - [ - "DSP_0_PCIN45", - "DSP_PCOUT45" - ], - [ - "DSP_0_ACIN5", - "DSP_ACOUT5" - ], - [ - "DSP_0_PCIN27", - "DSP_PCOUT27" - ], - [ - "DSP_0_PCIN31", - "DSP_PCOUT31" - ], - [ - "DSP_0_PCIN7", - "DSP_PCOUT7" - ], - [ - "DSP_0_BCIN4", - "DSP_BCOUT4" - ], - [ - "DSP_0_PCIN2", - "DSP_PCOUT2" - ], - [ - "DSP_0_PCIN32", - "DSP_PCOUT32" - ], - [ - "DSP_0_ACIN21", - "DSP_ACOUT21" - ], - [ - "DSP_0_ACIN28", - "DSP_ACOUT28" - ], - [ - "DSP_0_PCIN37", - "DSP_PCOUT37" - ], - [ - "DSP_0_PCIN3", - "DSP_PCOUT3" - ], - [ - "DSP_0_CARRYCASCIN", - "DSP_CARRYCASCOUT" - ], - [ - "DSP_0_ACIN18", - "DSP_ACOUT18" - ], - [ - "DSP_0_PCIN15", - "DSP_PCOUT15" - ], - [ - "DSP_0_PCIN22", - "DSP_PCOUT22" - ], - [ - "DSP_0_BCIN10", - "DSP_BCOUT10" - ], - [ - "DSP_0_PCIN33", - "DSP_PCOUT33" - ], - [ - "DSP_0_BCIN6", - "DSP_BCOUT6" - ], - [ - "DSP_0_PCIN44", - "DSP_PCOUT44" - ] - ], - "tile_types": [ - "DSP_R", - "DSP_R" - ], - "grid_deltas": [ - 0, - 5 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "BRAM_LH4_1", - "VBRK_LH4" - ], - [ - "BRAM_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "BRAM_LH3_1", - "VBRK_LH3" - ], - [ - "BRAM_LH5_1", - "VBRK_LH5" - ], - [ - "BRAM_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "BRAM_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "BRAM_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "BRAM_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "BRAM_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "BRAM_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "BRAM_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "BRAM_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "BRAM_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "BRAM_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "BRAM_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "BRAM_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "BRAM_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "BRAM_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "BRAM_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "BRAM_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "BRAM_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "BRAM_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "BRAM_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "BRAM_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "BRAM_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "BRAM_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "BRAM_LH11_1", - "VBRK_LH11" - ], - [ - "BRAM_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "BRAM_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "BRAM_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "BRAM_LH9_1", - "VBRK_LH9" - ], - [ - "BRAM_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "BRAM_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "BRAM_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "BRAM_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "BRAM_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "BRAM_SE4BEG2_1", - "VBRK_SE4BEG2" - ], - [ - "BRAM_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "BRAM_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "BRAM_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "BRAM_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "BRAM_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "BRAM_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "BRAM_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "BRAM_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "BRAM_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "BRAM_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "BRAM_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "BRAM_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "BRAM_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "BRAM_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "BRAM_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "BRAM_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "BRAM_LH12_1", - "VBRK_LH12" - ], - [ - "BRAM_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "BRAM_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "BRAM_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "BRAM_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "BRAM_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "BRAM_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "BRAM_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "BRAM_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "BRAM_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "BRAM_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "BRAM_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "BRAM_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "BRAM_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "BRAM_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "BRAM_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "BRAM_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "BRAM_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "BRAM_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "BRAM_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "BRAM_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "BRAM_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "BRAM_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "BRAM_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "BRAM_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "BRAM_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "BRAM_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "BRAM_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "BRAM_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "BRAM_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "BRAM_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "BRAM_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "BRAM_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "BRAM_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "BRAM_LH1_1", - "VBRK_LH1" - ], - [ - "BRAM_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "BRAM_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "BRAM_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "BRAM_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "BRAM_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "BRAM_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "BRAM_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "BRAM_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "BRAM_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "BRAM_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "BRAM_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "BRAM_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "BRAM_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "BRAM_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "BRAM_LH8_1", - "VBRK_LH8" - ], - [ - "BRAM_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "BRAM_LH6_1", - "VBRK_LH6" - ], - [ - "BRAM_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "BRAM_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "BRAM_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "BRAM_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "BRAM_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "BRAM_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "BRAM_LH10_1", - "VBRK_LH10" - ], - [ - "BRAM_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "BRAM_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "BRAM_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "BRAM_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "BRAM_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "BRAM_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "BRAM_LH7_1", - "VBRK_LH7" - ], - [ - "BRAM_LH2_1", - "VBRK_LH2" - ], - [ - "BRAM_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "BRAM_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "BRAM_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "BRAM_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "BRAM_NE4BEG2_1", - "VBRK_NE4BEG2" - ] - ], - "tile_types": [ - "BRAM_L", - "VBRK" - ], - "grid_deltas": [ - -1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "MMCM_CLK_FREQ_BB_REBUF1_NS", - "TERM_CMT_FREQ_REF_NS1" - ], - [ - "MMCM_CLK_FREQ_BB_REBUF0_NS", - "TERM_CMT_FREQ_REF_NS0" - ], - [ - "MMCM_CLK_FREQ_BB_REBUF3_NS", - "TERM_CMT_FREQ_REF_NS3" - ], - [ - "MMCM_CLK_FREQ_BB_REBUF2_NS", - "TERM_CMT_FREQ_REF_NS2" - ] - ], - "tile_types": [ - "CMT_TOP_R_LOWER_B", - "TERM_CMT" - ], - "grid_deltas": [ - 0, - 9 - ] - }, - { - "wire_pairs": [ - [ - "IOB_DIFF_TERM_INT_EN", - "RIOI_DIFF_TERM_INT_EN" - ], - [ - "IOB_O0", - "RIOI_O0" - ], - [ - "IOB_O1", - "RIOI_O1" - ], - [ - "IOB_KEEPER_INT_EN_1", - "RIOI_KEEPER_INT_EN_1" - ], - [ - "IOB_PU_INT_EN_0", - "RIOI_PU_INT_EN_0" - ], - [ - "IOB_T1", - "RIOI_T1" - ], - [ - "IOB_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE0" - ], - [ - "IOB_T0", - "RIOI_T0" - ], - [ - "IOB_IBUF0", - "RIOI_IBUF0" - ], - [ - "LIOB_IN_TERM1", - "RIOI_DCI_T_TERM1" - ], - [ - "IOB_KEEPER_INT_EN_0", - "RIOI_KEEPER_INT_EN_0" - ], - [ - "IOB_PD_INT_EN_1", - "RIOI_PD_INT_EN_1" - ], - [ - "RIOB_MONITOR_N", - "IOI_MONITOR_N" - ], - [ - "IOB_PU_INT_EN_1", - "RIOI_PU_INT_EN_1" - ], - [ - "IOB_IBUF1", - "RIOI_IBUF1" - ], - [ - "LIOB_IN_TERM0", - "RIOI_DCI_T_TERM0" - ], - [ - "IOB_PD_INT_EN_0", - "RIOI_PD_INT_EN_0" - ], - [ - "IOB_IBUF_DISABLE1", - "RIOI_IBUF_DISABLE1" - ], - [ - "RIOB_MONITOR_P", - "IOI_MONITOR_P" - ] - ], - "tile_types": [ - "RIOB33", - "RIOI3" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_EE4BEG2_3", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4END1_3", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_EE4C1_3", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW4A1_3", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_SW2A1_3", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH7_3", - "VBRK_LH7" - ], - [ - "CLK_HROW_LH3_3", - "VBRK_LH3" - ], - [ - "CLK_HROW_EE4C3_3", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WL1END0_3", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EL1BEG1_3", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_SW2A2_3", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_SW4END2_3", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EL1BEG2_3", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_WW4END3_3", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE4BEG3_3", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WW4B3_3", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_EL1BEG3_3", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_LH6_3", - "VBRK_LH6" - ], - [ - "CLK_HROW_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_WW4END2_3", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EL1BEG0_3", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_ER1BEG3_3", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE4B1_3", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE4B2_3", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_WR1END0_3", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_EE2BEG0_3", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_EE4BEG0_3", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW2END3_3", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NE4BEG3_3", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_NW4END1_3", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_NE2A2_3", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WL1END1_3", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NW4A0_3", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EE4A3_3", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NW2A0_3", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WR1END3_3", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_LH4_3", - "VBRK_LH4" - ], - [ - "CLK_HROW_NW2A2_3", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4A3_3", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_EE4BEG1_3", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SW4END3_3", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_SE2A3_3", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_SE4C1_3", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_ER1BEG2_3", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH5_3", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_ER1BEG1_3", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_SE4BEG0_3", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_NE2A0_3", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE2A3_3", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_WW4C3_3", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_ER1BEG0_3", - "VBRK_ER1BEG0" - ], - [ - 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], - [ - "HCLK_LV13", - "LV14" - ], - [ - "HCLK_SE6C1", - "SE6B1" - ], - [ - "HCLK_SE2A1", - "SE2BEG1" - ], - [ - "HCLK_NE6B2", - "NE6C2" - ], - [ - "HCLK_SE2A0", - "SE2BEG0" - ], - [ - "HCLK_NE6A1", - "NE6B1" - ], - [ - "HCLK_SL1END2", - "SL1BEG2" - ], - [ - "HCLK_LEAF_CLK_B_TOP5", - "GCLK_B5" - ], - [ - "HCLK_NR1BEG2", - "NR1END2" - ], - [ - "HCLK_SW6E3", - "SW6D3" - ], - [ - "HCLK_LEAF_CLK_B_TOP3", - "GCLK_B3" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END0" - ], - [ - "HCLK_SE6D1", - "SE6C1" - ], - [ - "HCLK_SS2END_N0_3", - "SS2END_N0_3" - ], - [ - "HCLK_LVB9", - "LVB9" - ], - [ - "HCLK_BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" - ], - [ - "HCLK_SS6E2", - "SS6D2" - ], - [ - "HCLK_LVB8", - "LVB8" - ], - [ - "HCLK_SW6D2", - "SW6C2" - ], - [ - "HCLK_SR1END2", - "SR1BEG2" - ], - [ - "HCLK_NN6BEG0", - "NN6A0" - ], - [ - "HCLK_SS6B0", - "SS6A0" - ], - [ - "HCLK_SW2A3", - "SW2BEG3" - ], - [ - "HCLK_NE6A2", - "NE6B2" - ], - [ - "HCLK_LV10", - "LV11" - ], - [ - "HCLK_LV2", - "LV3" - ], - [ - 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"BRKH_INT_NN2BEG1", - "NN2BEG1" - ], - [ - "BRKH_INT_NN6A3", - "NN6A3" - ], - [ - "BRKH_INT_NN6E1", - "NN6E1" - ], - [ - "BRKH_INT_SS2A0", - "SS2A0" - ], - [ - "BRKH_INT_SW6E3", - "SW6E3" - ], - [ - "BRKH_INT_NE2BEG1", - "NE2BEG1" - ], - [ - "BRKH_INT_SS6B3", - "SS6B3" - ], - [ - "BRKH_INT_NE6A1", - "NE6A1" - ], - [ - "BRKH_INT_LVB5", - "LVB4" - ], - [ - "BRKH_INT_NN2BEG3", - "NN2BEG3" - ], - [ - "BRKH_INT_SW6END3", - "SW6END3" - ], - [ - "BRKH_INT_SW6D0", - "SW6D0" - ], - [ - "BRKH_INT_NN6END_S1_0", - "NN6END_S1_0" - ], - [ - "BRKH_INT_LV17", - "LV17" - ], - [ - "BRKH_INT_WR1END_S1_0", - "WR1END_S1_0" - ], - [ - "BRKH_INT_SS6E3", - "SS6E3" - ], - [ - "BRKH_INT_NW2BEG0", - "NW2BEG0" - ], - [ - "BRKH_INT_LVB12", - "LVB11" - ], - [ - "BRKH_INT_NE2BEG0", - "NE2BEG0" - ], - [ - "BRKH_INT_SE6E1", - "SE6E1" - ], - [ - "BRKH_INT_SW6E1", - "SW6E1" - ], - [ - "BRKH_INT_SE6C1", - "SE6C1" - ], - [ - "BRKH_INT_BYP_BOUNCE3", - "BYP_BOUNCE3" - ], - [ - "BRKH_INT_WL1BEG3", - "WL1BEG3" - ], - [ - "BRKH_INT_SW2A3", - "SW2A3" - ], - [ - "BRKH_INT_SW6B2", - "SW6B2" - ], - [ - "BRKH_INT_NE6D0", - "NE6D0" - ], - [ - "BRKH_INT_LV4", - "LV4" - ], - [ - "BRKH_INT_SW6E0", - "SW6E0" - ], - [ - "BRKH_INT_NN6C0", - "NN6C0" - ], - [ - "BRKH_INT_SS6D1", - "SS6D1" - ], - [ - "BRKH_INT_NN6BEG0", - "NN6BEG0" - ], - [ - "BRKH_INT_NW2BEG2", - "NW2BEG2" - ], - [ - "BRKH_INT_NN6C2", - "NN6C2" - ], - [ - "BRKH_INT_NW6A2", - "NW6A2" - ], - [ - "BRKH_INT_NW6B2", - "NW6B2" - ], - [ - "BRKH_INT_NW6B1", - "NW6B1" - ], - [ - "BRKH_INT_SW6B1", - "SW6B1" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_6", - "FAN_BOUNCE_S3_6" - ], - [ - "BRKH_INT_SS6C2", - "SS6C2" - ], - [ - "BRKH_INT_NN6BEG2", - "NN6BEG2" - ], - [ - "BRKH_INT_NW6C1", - "NW6C1" - ], - [ - "BRKH_INT_SE6C0", - "SE6C0" - ], - [ - "BRKH_INT_NE6A0", - "NE6A0" - ], - [ - "BRKH_INT_NW6D0", - "NW6D0" - ], - [ - "BRKH_INT_WW2END3", - "WW2END3" - ], - [ - "BRKH_INT_SS6B0", - "SS6B0" - ], - [ - "BRKH_INT_NR1BEG1", - "NR1BEG1" - ], - [ - "BRKH_INT_SR1END2", - "SR1END2" - ], - [ - "BRKH_INT_SS6D3", - "SS6D3" - ], - [ - "BRKH_INT_SE6D3", - "SE6D3" - ], - [ - "BRKH_INT_SS2A3", - "SS2A3" - ], - [ - "BRKH_INT_SE6B1", - "SE6B1" - ], - [ - "BRKH_INT_SR1END3", - "SR1END3" - ], - [ - "BRKH_INT_SL1END1", - "SL1END1" - ], - [ - "BRKH_INT_NL1BEG1", - "NL1BEG1" - ], - [ - "BRKH_INT_LVB3", - "LVB2" - ], - [ - "BRKH_INT_NN2BEG0", - "NN2BEG0" - ], - [ - "BRKH_INT_NN2A0", - "NN2A0" - ], - [ - "BRKH_INT_SW6D3", - "SW6D3" - ], - [ - "BRKH_INT_NE6B2", - "NE6B2" - ], - [ - "BRKH_INT_NN6BEG3", - "NN6BEG3" - ], - [ - "BRKH_INT_NN6D2", - "NN6D2" - ], - [ - "BRKH_INT_NR1BEG2", - "NR1BEG2" - ], - [ - "BRKH_INT_SS2A1", - "SS2A1" - ], - [ - "BRKH_INT_SS6C3", - "SS6C3" - ], - [ - "BRKH_INT_NR1BEG0", - "NR1BEG0" - ], - [ - "BRKH_INT_NW6A3", - "NW6A3" - ], - [ - "BRKH_INT_WR1BEG_S0", - "WR1BEG_S0" - ], - [ - "BRKH_INT_SE6E2", - "SE6E2" - ], - [ - "BRKH_INT_SE6B0", - "SE6B0" - ], - [ - "BRKH_INT_SS6END_N0_3", - "SS6END3" - ], - [ - "BRKH_INT_NN6A2", - "NN6A2" - ], - [ - "BRKH_INT_SS2END3", - "SS2END3" - ], - [ - "BRKH_INT_NN6D1", - "NN6D1" - ], - [ - "BRKH_INT_NN6D3", - "NN6D3" - ], - [ - "BRKH_INT_BYP_BOUNCE2", - "BYP_BOUNCE2" - ], - [ - "BRKH_INT_LVB8", - "LVB7" - ], - [ - "BRKH_INT_NN2END_S2_0", - "NN2END_S2_0" - ], - [ - "BRKH_INT_NN6E3", - "NN6E3" - ], - [ - "BRKH_INT_NW6B3", - "NW6B3" - ], - [ - "BRKH_INT_SS6D0", - "SS6D0" - ], - [ - "BRKH_INT_NW2BEG3", - "NW2BEG3" - ], - [ - "BRKH_INT_NE6C1", - "NE6C1" - ], - [ - "BRKH_INT_SE6D2", - "SE6D2" - ], - [ - "BRKH_INT_SR1END_N3_3", - "SR1END3" - ], - [ - "BRKH_INT_LV11", - "LV11" - ], - [ - "BRKH_INT_LV6", - "LV6" - ], - [ - "BRKH_INT_SE6C2", - "SE6C2" - ], - [ - "BRKH_INT_SW6C1", - "SW6C1" - ], - [ - "BRKH_INT_BYP_BOUNCE7", - "BYP_BOUNCE7" - ], - [ - "BRKH_INT_NE6B0", - "NE6B0" - ], - [ - "BRKH_INT_SS6END1", - "SS6END1" - ], - [ - "BRKH_INT_LV9", - "LV9" - ], - [ - "BRKH_INT_NE6A3", - "NE6A3" - ], - [ - "BRKH_INT_NE6C3", - "NE6C3" - ], - [ - "BRKH_INT_SS6C1", - "SS6C1" - ], - [ - "BRKH_INT_NW2BEG1", - "NW2BEG1" - ], - [ - "BRKH_INT_NN6E2", - "NN6E2" - ], - [ - "BRKH_INT_SE6C3", - "SE6C3" - ], - [ - "BRKH_INT_LVB10", - "LVB9" - ], - [ - "BRKH_INT_LV8", - "LV8" - ], - [ - "BRKH_INT_NN6C1", - "NN6C1" - ], - [ - "BRKH_INT_SS2A2", - "SS2A2" - ], - [ - "BRKH_INT_SW6D2", - "SW6D2" - ], - [ - "BRKH_INT_NE6D1", - "NE6D1" - ], - [ - "BRKH_INT_NW6B0", - "NW6B0" - ], - [ - "BRKH_INT_SS6C0", - "SS6C0" - ], - [ - "BRKH_INT_SS6E0", - "SS6E0" - ], - [ - "BRKH_INT_SE6B3", - "SE6B3" - ], - [ - "BRKH_INT_SR1END1", - "SR1END1" - ], - [ - "BRKH_INT_SE2A3", - "SE2A3" - ], - [ - "BRKH_INT_FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_0" - ], - [ - "BRKH_INT_NW6C2", - "NW6C2" - ], - [ - "BRKH_INT_ER1END3", - "ER1END3" - ], - [ - "BRKH_INT_LV3", - "LV3" - ], - [ - "BRKH_INT_LV12", - "LV12" - ], - [ - "BRKH_INT_LV1", - "LV1" - ], - [ - "BRKH_INT_EL1BEG3", - "EL1BEG3" - ], - [ - "BRKH_INT_WW4END_S0_0", - "WW4END_S0_0" - ], - [ - "BRKH_INT_SS6END2", - "SS6END2" - ], - [ - "BRKH_INT_SS6END0", - "SS6END0" - ], - [ - "BRKH_INT_SW6C0", - "SW6C0" - ], - [ - "BRKH_INT_SL1END0", - "SL1END0" - ], - [ - "BRKH_INT_NE6B1", - "NE6B1" - ], - [ - "BRKH_INT_LVB11", - "LVB10" - ], - [ - "BRKH_INT_NN2A2", - "NN2A2" - ], - [ - "BRKH_INT_SE2A2", - "SE2A2" - ], - [ - "BRKH_INT_LV2", - "LV2" - ], - [ - "BRKH_INT_LVB1", - "LVB0" - ], - [ - "BRKH_INT_NW6C0", - "NW6C0" - ], - [ - "BRKH_INT_NN6C3", - "NN6C3" - ], - [ - "BRKH_INT_SS2END_N0_3", - "SS2END3" - ], - [ - "BRKH_INT_NE6C0", - "NE6C0" - ], - [ - "BRKH_INT_SS2END2", - "SS2END2" - ], - [ - "BRKH_INT_NE6D2", - "NE6D2" - ], - [ - "BRKH_INT_SS6B2", - "SS6B2" - ], - [ - "BRKH_INT_LV14", - "LV14" - ], - [ - "BRKH_INT_LV13", - "LV13" - ], - [ - "BRKH_INT_SS6A2", - "SS6A2" - ], - [ - "BRKH_INT_NE6C2", - "NE6C2" - ], - [ - "BRKH_INT_SE6E0", - "SE6E0" - ], - [ - "BRKH_INT_NW6D2", - "NW6D2" - ], - [ - "BRKH_INT_NE6A2", - "NE6A2" - ], - [ - "BRKH_INT_NN6BEG1", - "NN6BEG1" - ], - [ - "BRKH_INT_SW2A0", - "SW2A0" - ], - [ - "BRKH_INT_SW6B0", - "SW6B0" - ], - [ - "BRKH_INT_SL1END3", - "SL1END3" - ], - [ - "BRKH_INT_NW6A0", - "NW6A0" - ], - [ - "BRKH_INT_NN6B3", - "NN6B3" - ], - [ - "BRKH_INT_SW2A1", - "SW2A1" - ], - [ - "BRKH_INT_SS6E2", - "SS6E2" - ], - [ - "BRKH_INT_LVB4", - "LVB3" - ], - [ - "BRKH_INT_SW2END3", - "SW2END3" - ], - [ - "BRKH_INT_SE6E3", - "SE6E3" - ] - ], - "tile_types": [ - "BRKH_INT", - "INT_R" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_FIFO_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK1" - ], - [ - "HCLK_FIFO_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK8" - ], - [ - "HCLK_FIFO_PERFCLK2", - "HCLK_INT_INTERFACE_PERFCLK2" - ], - [ - "HCLK_FIFO_CCIO1", - "HCLK_INT_INTERFACE_CCIO1" - ], - [ - "HCLK_FIFO_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK0" - ], - [ - "HCLK_FIFO_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK4" - ], - [ - "HCLK_FIFO_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK2" - ], - [ - "HCLK_FIFO_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_BUFRCLK3" - ], - [ - "HCLK_FIFO_CCIO3", - "HCLK_INT_INTERFACE_CCIO3" - ], - [ - "HCLK_FIFO_CCIO0", - "HCLK_INT_INTERFACE_CCIO0" - ], - [ - "HCLK_FIFO_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK11" - ], - [ - "HCLK_FIFO_PERFCLK0", - "HCLK_INT_INTERFACE_PERFCLK0" - ], - [ - "HCLK_FIFO_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK6" - ], - [ - "HCLK_FIFO_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK1" - ], - [ - "HCLK_FIFO_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK5" - ], - [ - "HCLK_FIFO_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK0" - ], - [ - "HCLK_FIFO_PERFCLK3", - "HCLK_INT_INTERFACE_PERFCLK3" - ], - [ - "HCLK_FIFO_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK10" - ], - [ - "HCLK_FIFO_CCIO2", - "HCLK_INT_INTERFACE_CCIO2" - ], - [ - "HCLK_FIFO_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK3" - ], - [ - "HCLK_FIFO_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFHCLK9" - ], - [ - "HCLK_FIFO_PERFCLK1", - "HCLK_INT_INTERFACE_PERFCLK1" - ], - [ - "HCLK_FIFO_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK2" - ], - [ - "HCLK_FIFO_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK7" - ] - ], - "tile_types": [ - "HCLK_FIFO_L", - "HCLK_INT_INTERFACE" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "INT_INTERFACE_SE4C1", - "SE6E1" - ], - [ - "INT_INTERFACE_NE2A1", - "NE2A1" - ], - [ - "INT_INTERFACE_CTRL0", - "CTRL0" - ], - [ - "INT_INTERFACE_EE4BEG3", - "EE4BEG3" - ], - [ - "INT_INTERFACE_EE4BEG0", - "EE4BEG0" - ], - [ - "INT_INTERFACE_BRAM_IMUX16", - "IMUX16" - ], - [ - "INT_INTERFACE_NE4BEG3", - "NE6BEG3" - ], - [ - "INT_INTERFACE_BRAM_IMUX45", - "IMUX45" - ], - [ - "INT_INTERFACE_NE4BEG1", - "NE6BEG1" - ], - [ - "INT_INTERFACE_SW4A1", - "SW6A1" - ], - [ - "INT_INTERFACE_WW4A3", - "WW4A3" - ], - [ - "INT_INTERFACE_SE4C0", - "SE6E0" - ], - [ - "INT_INTERFACE_EL1BEG3", - "EL1BEG3" - ], - [ - "INT_INTERFACE_BRAM_IMUX5", - "IMUX5" - ], - [ - "INT_INTERFACE_BRAM_IMUX22", - "IMUX22" - ], - [ - "INT_INTERFACE_LOGIC_OUTS22", - "LOGIC_OUTS22" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "IMUX1" - ], - [ - "INT_INTERFACE_EE4B3", - "EE4B3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS8", - "LOGIC_OUTS8" - ], - [ - "INT_INTERFACE_WW2A1", - "WW2A1" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "IMUX4" - ], - [ - "INT_INTERFACE_EE4C3", - "EE4C3" - ], - [ - "INT_INTERFACE_NW2A1", - "NW2END1" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "IMUX44" - ], - [ - "INT_INTERFACE_LOGIC_OUTS6", - "LOGIC_OUTS6" - ], - [ - "INT_INTERFACE_EE4A3", - "EE4A3" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "IMUX32" - ], - [ - "INT_INTERFACE_WW4B3", - "WW4B3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS0", - "LOGIC_OUTS0" - ], - [ - "INT_INTERFACE_BRAM_IMUX42", - "IMUX42" - ], - [ - "INT_INTERFACE_SE4C2", - "SE6E2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS18", - "LOGIC_OUTS18" - ], - [ - "INT_INTERFACE_NE2A2", - "NE2A2" - ], - [ - "INT_INTERFACE_EE4C1", - "EE4C1" - ], - [ - "INT_INTERFACE_WW2A0", - "WW2A0" - ], - [ - "INT_INTERFACE_WW4A1", - "WW4A1" - ], - [ - "INT_INTERFACE_WW2END3", - "WW2END3" - ], - [ - "INT_INTERFACE_EL1BEG2", - "EL1BEG2" - ], - [ - "INT_INTERFACE_EE4B1", - "EE4B1" - ], - [ - "INT_INTERFACE_CTRL1", - "CTRL1" - ], - [ - "INT_INTERFACE_WL1END0", - "WL1END0" - ], - [ - "INT_INTERFACE_NE4C1", - "NE6E1" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "IMUX2" - ], - [ - "INT_INTERFACE_LH2", - "LH2" - ], - [ - "INT_INTERFACE_BRAM_IMUX13", - "IMUX13" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "IMUX31" - ], - [ - "INT_INTERFACE_EL1BEG1", - "EL1BEG1" - ], - [ - "INT_INTERFACE_WW4END3", - "WW4END3" - ], - [ - "INT_INTERFACE_FAN2", - "FAN2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS15", - "LOGIC_OUTS15" - ], - [ - "INT_INTERFACE_WL1END1", - "WL1END1" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "IMUX38" - ], - [ - "INT_INTERFACE_WW4C2", - "WW4C2" - ], - [ - "INT_INTERFACE_NW2A0", - "NW2END0" - ], - [ - "INT_INTERFACE_CLK1", - "CLK1" - ], - [ - "INT_INTERFACE_WW2END1", - "WW2END1" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "IMUX28" - ], - [ - "INT_INTERFACE_NE4BEG0", - "NE6BEG0" - ], - [ - "INT_INTERFACE_SW4END0", - "SW6END0" - ], - [ - "INT_INTERFACE_NW4END1", - "NW6END1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS12", - "LOGIC_OUTS12" - ], - [ - "INT_INTERFACE_LH10", - "LH10" - ], - [ - "INT_INTERFACE_LOGIC_OUTS17", - "LOGIC_OUTS17" - ], - [ - "INT_INTERFACE_SW2A3", - "SW2END3" - ], - [ - "INT_INTERFACE_BRAM_IMUX43", - "IMUX43" - ], - [ - "INT_INTERFACE_EE2A2", - "EE2A2" - ], - [ - "INT_INTERFACE_LOGIC_OUTS20", - "LOGIC_OUTS20" - ], - [ - "INT_INTERFACE_ER1BEG3", - "ER1BEG3" - ], - [ - "INT_INTERFACE_SE4BEG0", - "SE6BEG0" - ], - [ - "INT_INTERFACE_BRAM_IMUX23", - "IMUX23" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "IMUX15" - ], - [ - "INT_INTERFACE_BYP3", - "BYP3" - ], - [ - "INT_INTERFACE_BYP6", - "BYP6" - ], - [ - "INT_INTERFACE_BRAM_IMUX8", - "IMUX8" - ], - [ - "INT_INTERFACE_WW4A0", - "WW4A0" - ], - [ - "INT_INTERFACE_WW4C3", - "WW4C3" - ], - [ - "INT_INTERFACE_BRAM_IMUX35", - "IMUX35" - ], - [ - "INT_INTERFACE_LOGIC_OUTS13", - "LOGIC_OUTS13" - ], - [ - "INT_INTERFACE_EE4BEG1", - "EE4BEG1" - ], - [ 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"IMUX36" - ], - [ - "INT_INTERFACE_SW4A0", - "SW6A0" - ], - [ - "INT_INTERFACE_SE4BEG2", - "SE6BEG2" - ], - [ - "INT_INTERFACE_WW4C1", - "WW4C1" - ], - [ - "INT_INTERFACE_SW4END1", - "SW6END1" - ], - [ - "INT_INTERFACE_NW4A3", - "NW6A3" - ], - [ - "INT_INTERFACE_BYP0", - "BYP0" - ], - [ - "INT_INTERFACE_SE4C3", - "SE6E3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS7", - "LOGIC_OUTS7" - ], - [ - "INT_INTERFACE_BYP4", - "BYP4" - ], - [ - "INT_INTERFACE_WL1END2", - "WL1END2" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "IMUX37" - ], - [ - "INT_INTERFACE_EL1BEG0", - "EL1BEG0" - ], - [ - "INT_INTERFACE_LH1", - "LH1" - ], - [ - "INT_INTERFACE_MONITOR_N", - "MONITOR_N" - ], - [ - "INT_INTERFACE_WW4END0", - "WW4END0" - ], - [ - "INT_INTERFACE_LH7", - "LH7" - ], - [ - "INT_INTERFACE_SW4A3", - "SW6A3" - ], - [ - "INT_INTERFACE_NW4END2", - "NW6END2" - ], - [ - "INT_INTERFACE_WW2END0", - "WW2END0" - ], - [ - "INT_INTERFACE_WW4C0", - "WW4C0" - ], - [ - "INT_INTERFACE_EE2A1", - "EE2A1" - ], - [ - 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"VBRK_SW2A0" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLK_FEED_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLK_FEED_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLK_FEED_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLK_FEED_LH12", - "VBRK_LH12" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_NE2A2", - "VBRK_NE2A2" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_WW4C2", - "VBRK_WW4C2" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLK_FEED_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" - ], - [ - "CLK_FEED_WW4B1", - "VBRK_WW4B1" - ], - [ - "CLK_FEED_SE4BEG3", - "VBRK_SE4BEG3" - ], - [ - "CLK_FEED_WW2END1", - "VBRK_WW2END1" - ], - [ - "CLK_FEED_SE4C2", - "VBRK_SE4C2" - ], - [ - "CLK_FEED_LH2", - "VBRK_LH2" - ], - [ - "CLK_FEED_ER1BEG0", - "VBRK_ER1BEG0" - ], - [ - "CLK_FEED_WW4END2", - "VBRK_WW4END2" - ], - [ - "CLK_FEED_NE4C2", - "VBRK_NE4C2" - ], - [ - "CLK_FEED_ER1BEG3", - "VBRK_ER1BEG3" - ], - [ - "CLK_FEED_SW4END3", - "VBRK_SW4END3" - ], - [ - "CLK_FEED_LH5", - "VBRK_LH5" - ], - [ - "CLK_FEED_EE4BEG0", - "VBRK_EE4BEG0" - ], - [ - "CLK_FEED_EE2A0", - "VBRK_EE2A0" - ], - [ - "CLK_FEED_LH10", - "VBRK_LH10" - ], - [ - "CLK_FEED_NW4END1", - "VBRK_NW4END1" - ], - [ - "CLK_FEED_EE4B1", - "VBRK_EE4B1" - ], - [ - "CLK_FEED_EE4A0", - "VBRK_EE4A0" - ], - [ - "CLK_FEED_WL1END0", - "VBRK_WL1END0" - ], - [ - "CLK_FEED_LH7", - "VBRK_LH7" - ], - [ - "CLK_FEED_NW2A3", - "VBRK_NW2A3" - ], - [ - "CLK_FEED_NW4A0", - "VBRK_NW4A0" - ], - [ - "CLK_FEED_SE2A2", - "VBRK_SE2A2" - ], - [ - "CLK_FEED_EL1BEG3", - "VBRK_EL1BEG3" - ], - [ - "CLK_FEED_NW4END0", - "VBRK_NW4END0" - ], - [ - "CLK_FEED_ER1BEG2", - "VBRK_ER1BEG2" - ], - [ - "CLK_FEED_SW4A2", - "VBRK_SW4A2" - ], - [ - "CLK_FEED_EE4BEG2", - "VBRK_EE4BEG2" - ] - ], - "tile_types": [ - "CLK_FEED", - "VBRK" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "PCIE_NW2A1_7", - "INT_INTERFACE_NW2A1" - ], - [ - "PCIE_IMUX26_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT26" - ], - [ - "PCIE_EE4B0_7", - "INT_INTERFACE_EE4B0" - ], - [ - "PCIE_IMUX8_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT8" - ], - [ - "PCIE_NW2A0_7", - "INT_INTERFACE_NW2A0" - ], - [ - "PCIE_IMUX32_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT32" - ], - [ - "PCIE_EE2A0_7", - "INT_INTERFACE_EE2A0" - ], - [ - "PCIE_ER1BEG0_7", - "INT_INTERFACE_ER1BEG0" - ], - [ - "PCIE_LOGIC_OUTS_B22_R_7", - "INT_INTERFACE_LOGIC_OUTS_B22" - ], - [ - "PCIE_MONITOR_P_7", - "INT_INTERFACE_MONITOR_P" - ], - [ - "PCIE_WR1END2_7", - "INT_INTERFACE_WR1END2" - ], - [ - "PCIE_EE4BEG2_7", - "INT_INTERFACE_EE4BEG2" - ], - [ - "PCIE_FAN5_R_7", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_NE4BEG2_7", - "INT_INTERFACE_NE4BEG2" - ], - [ - "PCIE_NW4END2_7", - "INT_INTERFACE_NW4END2" - ], - [ - "PCIE_BYP0_R_7", - "INT_INTERFACE_BYP0" - ], - [ - "PCIE_IMUX33_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT33" - ], - [ - "PCIE_LH1_7", - "INT_INTERFACE_LH1" - ], - [ - "PCIE_CTRL0_R_7", - "INT_INTERFACE_CTRL0" - ], - [ - "PCIE_EE4A1_7", - "INT_INTERFACE_EE4A1" - ], - [ - "PCIE_WW4END3_7", - "INT_INTERFACE_WW4END3" - ], - [ - "PCIE_FAN3_R_7", - "INT_INTERFACE_FAN3" - ], - [ - "PCIE_IMUX34_R_7", - "PCIE_INT_INTERFACE_IMUX_OUT34" - ], - [ - "PCIE_BYP6_R_7", - "INT_INTERFACE_BYP6" - ], - [ - "PCIE_LOGIC_OUTS_B11_R_7", - "INT_INTERFACE_LOGIC_OUTS_B11" - ], - [ - "PCIE_WW4C0_7", - "INT_INTERFACE_WW4C0" - ], - [ - "PCIE_WW2A2_7", - "INT_INTERFACE_WW2A2" - ], - [ - "PCIE_EL1BEG3_7", - "INT_INTERFACE_EL1BEG3" - ], - [ - "PCIE_LH5_7", - "INT_INTERFACE_LH5" - ], - [ - "PCIE_WW2END1_7", - "INT_INTERFACE_WW2END1" - ], - [ - "PCIE_SW4A3_7", - "INT_INTERFACE_SW4A3" - ], - [ - "PCIE_IMUX2_R_7", - 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"BRAM_IMUX8_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "BRAM_IMUX44_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "BRAM_LOGIC_OUTS_B3_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX42", - "BRAM_IMUX42_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX13", - "BRAM_IMUX13_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX21", - "BRAM_IMUX21_UTURN_1" - ], - [ - "INT_INTERFACE_NW2A0", - "BRAM_NW2A0_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "BRAM_LOGIC_OUTS_B16_1" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_1" - ], - [ - "INT_INTERFACE_FAN2", - "BRAM_FAN2_1" - ], - [ - "INT_INTERFACE_WW4C0", - "BRAM_WW4C0_1" - ], - [ - "INT_INTERFACE_BYP6", - "BRAM_BYP6_1" - ], - [ - "INT_INTERFACE_EE4C0", - "BRAM_EE4C0_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX39", - "BRAM_IMUX39_UTURN_1" - ], - [ - "INT_INTERFACE_BYP3", - "BRAM_BYP3_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "BRAM_LOGIC_OUTS_B20_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX36", - "BRAM_IMUX36_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX10", - "BRAM_IMUX10_UTURN_1" - ], - [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_1" - ], - [ - "INT_INTERFACE_ER1BEG1", - "BRAM_ER1BEG1_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX1", - "BRAM_IMUX1_1" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_1" - ], - [ - "INT_INTERFACE_LH9", - "BRAM_LH9_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX28", - "BRAM_IMUX28_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX19", - "BRAM_IMUX19_UTURN_1" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_1" - ], - [ - "INT_INTERFACE_FAN3", - "BRAM_FAN3_1" - ], - [ - "INT_INTERFACE_SW2A2", - "BRAM_SW2A2_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX31", - "BRAM_IMUX31_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX38", - "BRAM_IMUX38_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX16", - "BRAM_IMUX16_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX15", - "BRAM_IMUX15_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX37", - "BRAM_IMUX37_UTURN_1" - ], - [ - "INT_INTERFACE_EE4C3", - "BRAM_EE4C3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX21", - "BRAM_IMUX21_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX41", - "BRAM_IMUX41_UTURN_1" - ], - [ - "INT_INTERFACE_NW4A3", - "BRAM_NW4A3_1" - ], - [ - "INT_INTERFACE_EE2BEG0", - "BRAM_EE2BEG0_1" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "BRAM_LOGIC_OUTS_B2_1" - ], - [ - "INT_INTERFACE_LH4", - "BRAM_LH4_1" - ], - [ - "INT_INTERFACE_LH10", - "BRAM_LH10_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "BRAM_IMUX3_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX24", - "BRAM_IMUX24_1" - ], - [ - "INT_INTERFACE_BRAM_IMUX41", - "BRAM_IMUX41_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX20", - "BRAM_IMUX20_UTURN_1" - ], - [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_1" - ], - [ - "INT_INTERFACE_MONITOR_P", - "BRAM_MONITOR_P_1" - ], - [ - "INT_INTERFACE_NE2A3", - "BRAM_NE2A3_1" - ], - [ - "INT_INTERFACE_SE4C1", - "BRAM_SE4C1_1" - ], - [ - "INT_INTERFACE_WL1END3", - "BRAM_WL1END3_1" - ], - [ - "INT_INTERFACE_SE4BEG0", - "BRAM_SE4BEG0_1" - ], - [ - "INT_INTERFACE_NE4BEG3", - "BRAM_NE4BEG3_1" - ], - [ - "INT_INTERFACE_NE4C1", - "BRAM_NE4C1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX17", - "BRAM_IMUX17_UTURN_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX46", - "BRAM_IMUX46_UTURN_1" - ], - [ - "INT_INTERFACE_FAN4", - "BRAM_FAN4_1" - ], - [ - "INT_INTERFACE_SW4A3", - "BRAM_SW4A3_1" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_1" - ], - [ - "INT_INTERFACE_BRAM_UTURN_IMUX40", - "BRAM_IMUX40_UTURN_1" - ], - [ - "INT_INTERFACE_LH6", - "BRAM_LH6_1" - ], - [ - "INT_INTERFACE_EE4B0", - "BRAM_EE4B0_1" - ] - ], - "tile_types": [ - "BRAM_INT_INTERFACE_L", - "BRAM_L" - ], - "grid_deltas": [ - -1, - 1 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_VBRK_CK_BUFRCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK1" - ], - [ - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK1" - ], - [ - "HCLK_CLB_CK_IN7", - "HCLK_VBRK_MUX_CLK7" - ], - [ - "HCLK_CLB_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK0" - ], - [ - "HCLK_CLB_CK_IN2", - "HCLK_VBRK_MUX_CLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_VBRK_MUX_CLK13" - ], - [ - "HCLK_CLB_PERFCLK3", - "HCLK_VBRK_PHSR_PERFCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_VBRK_MUX_CLK4" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_VBRK_MUX_CLK5" - ], - [ - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK7" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_VBRK_MUX_CLK12" - ], - [ - "HCLK_CLB_PERFCLK2", - "HCLK_VBRK_PHSR_PERFCLK2" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_VBRK_MUX_CLK6" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_VBRK_MUX_CLK8" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_VBRK_MUX_CLK10" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK10" - ], - [ - "HCLK_CLB_CK_IN0", - "HCLK_VBRK_MUX_CLK0" - ], - [ - "HCLK_CLB_PERFCLK0", - "HCLK_VBRK_PHSR_PERFCLK0" - ], - [ - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK2" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_VBRK_MUX_CLK11" - ], - [ - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK8" - ], - [ - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK2" - ], - [ - "HCLK_CLB_PERFCLK1", - "HCLK_VBRK_PHSR_PERFCLK1" - ], - [ - "HCLK_CLB_CK_IN1", - "HCLK_VBRK_MUX_CLK1" - ], - [ - "HCLK_CLB_CK_IN3", - "HCLK_VBRK_MUX_CLK3" - ], - [ - "HCLK_CLB_CK_IN9", - "HCLK_VBRK_MUX_CLK9" - ], - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFHCLK9" - ], - [ - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK4" - ], - [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK0" - ] - ], - "tile_types": [ - "HCLK_CLB", - "HCLK_VBRK" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "GTPE2_LOGIC_OUTS_B13_0", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_CLK0_0", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_BYP1_0", - "VBRK_EXT_BYP1" - ], - [ - "GTPE2_FAN0_0", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_IMUX10_0", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX46_0", - "VBRK_EXT_IMUX46" - ], - [ - "GTPE2_IMUX30_0", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B23_0", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_IMUX28_0", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX34_0", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_LOGIC_OUTS_B18_0", - "VBRK_EXT_LOGIC_OUTS_B18" - ], - [ - "GTPE2_IMUX36_0", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_FAN5_0", - "VBRK_EXT_FAN5" - ], - [ - "GTPE2_IMUX45_0", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_IMUX39_0", - "VBRK_EXT_IMUX39" - ], - [ - "GTPE2_IMUX24_0", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_LOGIC_OUTS_B22_0", - "VBRK_EXT_LOGIC_OUTS_B22" - ], - [ - "GTPE2_IMUX15_0", - "VBRK_EXT_IMUX15" - ], - [ - "GTPE2_FAN2_0", - "VBRK_EXT_FAN2" - ], - [ - "GTPE2_LOGIC_OUTS_B10_0", - "VBRK_EXT_LOGIC_OUTS_B10" - ], - [ - "GTPE2_IMUX42_0", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX38_0", - "VBRK_EXT_IMUX38" - ], - [ - "GTPE2_IMUX33_0", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_LOGIC_OUTS_B19_0", - "VBRK_EXT_LOGIC_OUTS_B19" - ], - [ - "GTPE2_CLK1_0", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_FAN7_0", - "VBRK_EXT_FAN7" - ], - [ - "GTPE2_IMUX43_0", - "VBRK_EXT_IMUX43" - ], - [ - "GTPE2_BYP6_0", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_BYP3_0", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_LOGIC_OUTS_B8_0", - "VBRK_EXT_LOGIC_OUTS_B8" - ], - [ - "GTPE2_IMUX8_0", - "VBRK_EXT_IMUX8" - ], - [ - "GTPE2_IMUX40_0", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_IMUX27_0", - "VBRK_EXT_IMUX27" - ], - [ - "GTPE2_IMUX19_0", - "VBRK_EXT_IMUX19" - ], - [ - "GTPE2_IMUX3_0", - "VBRK_EXT_IMUX3" - ], - [ - "GTPE2_IMUX29_0", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_LOGIC_OUTS_B11_0", - "VBRK_EXT_LOGIC_OUTS_B11" - ], - [ - "GTPE2_IMUX44_0", - "VBRK_EXT_IMUX44" - ], - [ - "GTPE2_IMUX31_0", - "VBRK_EXT_IMUX31" - ], - [ - "GTPE2_IMUX25_0", - "VBRK_EXT_IMUX25" - ], - [ - "GTPE2_IMUX13_0", - "VBRK_EXT_IMUX13" - ], - [ - "GTPE2_IMUX17_0", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX4_0", - "VBRK_EXT_IMUX4" - ], - [ - "GTPE2_IMUX12_0", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX35_0", - "VBRK_EXT_IMUX35" - ], - [ - "GTPE2_CTRL0_0", - "VBRK_EXT_CTRL0" - ], - [ - "GTPE2_BYP7_0", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_CTRL1_0", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_FAN1_0", - "VBRK_EXT_FAN1" - ], - [ - "GTPE2_IMUX26_0", - "VBRK_EXT_IMUX26" - ], - [ - "GTPE2_LOGIC_OUTS_B12_0", - "VBRK_EXT_LOGIC_OUTS_B12" - ], - [ - "GTPE2_FAN3_0", - "VBRK_EXT_FAN3" - ], - [ - "GTPE2_BYP4_0", - "VBRK_EXT_BYP4" - ], - [ - "GTPE2_IMUX22_0", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX11_0", - "VBRK_EXT_IMUX11" - ], - [ - "GTPE2_FAN6_0", - "VBRK_EXT_FAN6" - ], - [ - "GTPE2_FAN4_0", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX0_0", - "VBRK_EXT_IMUX0" - ], - [ - "GTPE2_IMUX47_0", - "VBRK_EXT_IMUX47" - ], - [ - "GTPE2_IMUX9_0", - "VBRK_EXT_IMUX9" - ], - [ - "GTPE2_LOGIC_OUTS_B14_0", - "VBRK_EXT_LOGIC_OUTS_B14" - ], - [ - "GTPE2_IMUX23_0", - "VBRK_EXT_IMUX23" - ], - [ - "GTPE2_IMUX16_0", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX14_0", - "VBRK_EXT_IMUX14" - ], - [ - "GTPE2_IMUX20_0", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_IMUX41_0", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX5_0", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_IMUX7_0", - "VBRK_EXT_IMUX7" - ], - [ - "GTPE2_IMUX2_0", - "VBRK_EXT_IMUX2" - ], - [ - "GTPE2_IMUX1_0", - "VBRK_EXT_IMUX1" - ], - [ - "GTPE2_BYP0_0", - "VBRK_EXT_BYP0" - ], - [ - "GTPE2_IMUX37_0", - "VBRK_EXT_IMUX37" - ], - [ - "GTPE2_LOGIC_OUTS_B20_0", - "VBRK_EXT_LOGIC_OUTS_B20" - ], - [ - "GTPE2_IMUX21_0", - "VBRK_EXT_IMUX21" - ], - [ - "GTPE2_LOGIC_OUTS_B9_0", - "VBRK_EXT_LOGIC_OUTS_B9" - ], - [ - "GTPE2_BYP5_0", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX6_0", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_LOGIC_OUTS_B15_0", - "VBRK_EXT_LOGIC_OUTS_B15" - ], - [ - "GTPE2_LOGIC_OUTS_B16_0", - "VBRK_EXT_LOGIC_OUTS_B16" - ], - [ - "GTPE2_IMUX32_0", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_IMUX18_0", - "VBRK_EXT_IMUX18" - ], - [ - "GTPE2_BYP2_0", - "VBRK_EXT_BYP2" - ] - ], - "tile_types": [ - "GTP_CHANNEL_0", - "VBRK_EXT" - ], - "grid_deltas": [ - -1, - 5 - ] - }, - { - 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"INT_INTERFACE_ER1BEG3" - ], - [ - "PCIE_IMUX19_L_13", - "PCIE_INT_INTERFACE_IMUX_L_OUT19" - ], - [ - "PCIE_FAN5_L_13", - "INT_INTERFACE_FAN5" - ], - [ - "PCIE_SE4BEG1_13", - "INT_INTERFACE_SE4BEG1" - ], - [ - "PCIE_LOGIC_OUTS_B16_L_13", - "INT_INTERFACE_LOGIC_OUTS_L_B16" - ] - ], - "tile_types": [ - "PCIE_BOT", - "PCIE_INT_INTERFACE_L" - ], - "grid_deltas": [ - 5, - -3 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_CLK0_4", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_EE4B1_4", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_HROW_SE4BEG2_4", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_HROW_SW2A3_4", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_IMUX5_4", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_IMUX8_4", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_HROW_IMUX41_4", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SW2A2_4", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_LH10_4", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_NE4BEG0_4", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_HROW_SE4BEG0_4", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_HROW_SE4C1_4", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_HROW_WR1END0_4", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_HROW_WW4C2_4", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_IMUX1_4", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_WW4A0_4", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_NW2A0_4", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_HROW_IMUX29_4", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_HROW_NW4END2_4", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_HROW_EE4C0_4", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_EE4BEG2_4", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_HROW_BYP2_4", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_WW4C0_4", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_HROW_IMUX6_4", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_SW2A1_4", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_EE4A2_4", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_EL1BEG2_4", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_HROW_SE2A3_4", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_HROW_WW2END3_4", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_HROW_EE2BEG3_4", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_FAN4_4", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_HROW_IMUX14_4", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_EL1BEG1_4", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_HROW_WW2END1_4", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WL1END3_4", - "INT_INTERFACE_WL1END3" - ], - [ - "CLK_HROW_BYP3_4", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NW2A1_4", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_HROW_NW4A2_4", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_WR1END1_4", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_EE2BEG0_4", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_SW4END1_4", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_IMUX30_4", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_IMUX27_4", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_HROW_SW4A1_4", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_HROW_IMUX10_4", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_HROW_NW2A3_4", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_HROW_NE4C2_4", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_EE4BEG3_4", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_HROW_EE4A0_4", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_HROW_NW4A0_4", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_HROW_WW2END2_4", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_IMUX47_4", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_HROW_EE4C3_4", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_HROW_IMUX24_4", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_HROW_IMUX35_4", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_IMUX20_4", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_HROW_SE4C0_4", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_HROW_LH7_4", - "INT_INTERFACE_LH7" - ], - [ - "CLK_HROW_NE2A2_4", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_HROW_IMUX19_4", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_IMUX15_4", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_HROW_LH1_4", - "INT_INTERFACE_LH1" - ], - [ - "CLK_HROW_IMUX16_4", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_HROW_WW4C1_4", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_SE4BEG1_4", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_HROW_EE4A1_4", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_NE4C1_4", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_HROW_CLK1_4", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_IMUX12_4", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_IMUX40_4", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_ER1BEG3_4", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_MONITOR_P_4", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_HROW_FAN0_4", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_IMUX39_4", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_HROW_WW2END0_4", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_HROW_NE4BEG1_4", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_ER1BEG2_4", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_HROW_NE4C3_4", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_HROW_IMUX21_4", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_IMUX43_4", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_HROW_EE2BEG2_4", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_HROW_IMUX11_4", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_LH12_4", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_IMUX0_4", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_HROW_EE2A2_4", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_HROW_NE2A0_4", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_HROW_WW4END0_4", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_LH6_4", - "INT_INTERFACE_LH6" - ], - [ - "CLK_HROW_MONITOR_N_4", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_HROW_EE4B0_4", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_HROW_EE2A0_4", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_SE2A1_4", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_IMUX22_4", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_HROW_WL1END2_4", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_HROW_NW4A1_4", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_IMUX33_4", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_LH2_4", - "INT_INTERFACE_LH2" - ], - [ - "CLK_HROW_WW2A3_4", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_HROW_LH5_4", - "INT_INTERFACE_LH5" - ], - [ - "CLK_HROW_NE4C0_4", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_NE2A3_4", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_HROW_NE2A1_4", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_HROW_WR1END3_4", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_HROW_IMUX36_4", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_WW4A3_4", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_SE4C3_4", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_WR1END2_4", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_HROW_NW4END1_4", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_HROW_FAN7_4", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WW2A1_4", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_HROW_NW2A2_4", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_SE4C2_4", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_HROW_NW4END0_4", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_CTRL0_4", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_HROW_NW4A3_4", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_HROW_WL1END0_4", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_NE4BEG3_4", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_IMUX46_4", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_SE2A2_4", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_HROW_BYP0_4", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_HROW_EE2BEG1_4", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_HROW_ER1BEG1_4", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_HROW_SW4END0_4", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_HROW_WW2A0_4", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_WW4END3_4", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_HROW_IMUX44_4", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_HROW_IMUX4_4", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_HROW_IMUX3_4", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_HROW_IMUX23_4", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_SW2A0_4", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_HROW_EL1BEG0_4", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_WW4C3_4", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_HROW_BYP6_4", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_HROW_IMUX18_4", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_SE4BEG3_4", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_HROW_BYP4_4", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_HROW_NW4END3_4", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_HROW_FAN5_4", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_HROW_LH3_4", - "INT_INTERFACE_LH3" - ], - [ - "CLK_HROW_IMUX32_4", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_HROW_BYP7_4", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_HROW_IMUX9_4", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EE4BEG1_4", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_HROW_FAN3_4", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_IMUX42_4", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_NE4BEG2_4", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_HROW_SW4END3_4", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_HROW_WW2A2_4", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_HROW_WW4B3_4", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_EE4BEG0_4", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_HROW_IMUX13_4", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_SW4A3_4", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_ER1BEG0_4", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_HROW_IMUX28_4", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_HROW_SW4A2_4", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_IMUX2_4", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_SW4END2_4", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_HROW_IMUX45_4", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_HROW_EE4B2_4", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_HROW_WW4B2_4", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_FAN2_4", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_LH11_4", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_IMUX38_4", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_HROW_WW4B0_4", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_LH4_4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_BYP5_4", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_HROW_IMUX17_4", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_WW4END2_4", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_HROW_SE2A0_4", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_HROW_EE2A1_4", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_HROW_WW4END1_4", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_HROW_IMUX31_4", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_IMUX25_4", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EE4C2_4", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_HROW_FAN1_4", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_HROW_SW4A0_4", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_EE4B3_4", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_HROW_CTRL1_4", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_FAN6_4", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_HROW_IMUX7_4", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_EE4C1_4", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_LH8_4", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_IMUX26_4", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_WW4A1_4", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_WL1END1_4", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_WW4B1_4", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_BYP1_4", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_WW4A2_4", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_HROW_EE2A3_4", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_HROW_EE4A3_4", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_HROW_EL1BEG3_4", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_LH9_4", - "INT_INTERFACE_LH9" - ], - [ - "CLK_HROW_IMUX37_4", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_IMUX34_4", - "INT_INTERFACE_IMUX34" - ] - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CLBLM_L_COUT_N", - "HCLK_CLB_COUT0_R" - ], - [ - "CLBLM_M_COUT_N", - "HCLK_CLB_COUT1_R" - ] - ], - "tile_types": [ - "CLBLM_R", - "HCLK_CLB" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_NW6D2", - "NW6E2" - ], - [ - "HCLK_SE6C0", - "SE6B0" - ], - [ - "HCLK_FAN_BOUNCE_S3_4", - "FAN_BOUNCE4" - ], - [ - "HCLK_NE2BEG2", - "NE2A2" - ], - [ - "HCLK_NN6C3", - "NN6D3" - ], - [ - "HCLK_SE6B1", - "SE6A1" - ], - [ - "HCLK_NW6C0", - "NW6D0" - ], - [ - "HCLK_NW6A0", - "NW6B0" - ], - [ - "HCLK_EL1BEG3", - "EL1BEG_N3" - ], - [ - "HCLK_NL1BEG2", - "NL1END2" - ], - [ - "HCLK_NN2A3", - "NN2END3" - ], - [ - "HCLK_SR1END_N3_3", - "SR1END_N3_3" - ], - [ - "HCLK_LVB1", - "LVB_L1" - ], - [ - "HCLK_SE6D0", - "SE6C0" - ], - [ - "HCLK_SS2BEG3", - "SS2BEG3" - ], - [ - "HCLK_SS6END2", - "SS6E2" - ], - [ - "HCLK_SS6C2", - "SS6B2" - ], - [ - "HCLK_LV1", - "LV_L2" - ], - [ - "HCLK_NR1BEG3", - "NR1END3" - ], - [ - "HCLK_SE6B0", - "SE6A0" - ], - [ - "HCLK_NW6B1", - "NW6C1" - ], - [ - "HCLK_NN6E2", - "NN6END2" - ], - [ - "HCLK_NW6D0", - "NW6E0" - ], - [ - "HCLK_SL1END3", - "SL1BEG3" - ], - [ - "HCLK_LV14", - "LV_L15" - ], - [ - "HCLK_SW6C3", - "SW6B3" - ], - [ - "HCLK_NN6A0", - "NN6B0" - ], - [ - "HCLK_NW6B2", - "NW6C2" - ], - [ - "HCLK_SW6E0", - "SW6D0" - ], - [ - "HCLK_NW6B0", - "NW6C0" - ], - [ - "HCLK_SS6B3", - "SS6A3" - ], - [ - "HCLK_SW6C2", - "SW6B2" - ], - [ - "HCLK_NE6C2", - "NE6D2" - ], - [ - "HCLK_SS6B1", - "SS6A1" - ], - [ - "HCLK_FAN_BOUNCE_S3_0", - "FAN_BOUNCE0" - ], - [ - "HCLK_WL1END3", - "WL1END_N1_3" - ], - [ - "HCLK_SE6E1", - "SE6D1" - ], - [ - "HCLK_SW6D0", - "SW6C0" - ], - [ - "HCLK_NW6END_S0_0", - "NW6END0" - ], - [ - "HCLK_SW2END2", - "SW2BEG2" - ], - [ - "HCLK_NN6A2", - "NN6B2" - ], - [ - "HCLK_LEAF_CLK_B_TOPL3", - "GCLK_L_B9" - ], - [ - "HCLK_NN6B1", - "NN6C1" - ], - [ - "HCLK_SE6E2", - "SE6D2" - ], - [ - "HCLK_NR1BEG0", - "NR1END0" - ], - [ - "HCLK_NN2END_S2_0", - "NN2END0" - ], - [ - "HCLK_SS2END0", - "SS2A0" - ], - [ - "HCLK_LVB7", - "LVB_L7" - ], - [ - "HCLK_NW6B3", - "NW6C3" - ], - [ - "HCLK_NN6A1", - "NN6B1" - ], - [ - "HCLK_SS6C3", - "SS6B3" - ], - [ - "HCLK_SS6E1", - "SS6D1" - ], - [ - "HCLK_SS6A1", - "SS6BEG1" - ], - [ - "HCLK_FAN_BOUNCE_S3_2", - "FAN_BOUNCE2" - ], - [ - "HCLK_SS6B2", - "SS6A2" - ], - [ - "HCLK_NE2BEG0", - "NE2A0" - ], - [ - "HCLK_SW6D3", - "SW6C3" - ], - [ - "HCLK_SS6C1", - "SS6B1" - ], - [ - "HCLK_NL1BEG0", - "NL1END0" - ], - [ - "HCLK_WW4END_S0_0", - "WW4END0" - ], - [ - "HCLK_LVB2", - "LVB_L2" - ], - [ - "HCLK_NW6C2", - "NW6D2" - ], - [ - "HCLK_SS6D0", - "SS6C0" - ], - [ - "HCLK_LV10", - "LV_L11" - ], - [ - "HCLK_SW6D1", - "SW6C1" - ], - [ - "HCLK_NE6A0", - "NE6B0" - ], - [ - "HCLK_NE6B0", - "NE6C0" - ], - [ - "HCLK_SW6B1", - "SW6A1" - ], - [ - "HCLK_LV5", - "LV_L6" - ], - [ - "HCLK_SW6B3", - "SW6A3" - ], - [ - "HCLK_SL1END1", - "SL1BEG1" - ], - [ - "HCLK_WL1BEG3", - "WL1BEG_N3" - ], - [ - "HCLK_LEAF_CLK_B_TOPL4", - "GCLK_L_B10" - ], - [ - "HCLK_SE6E3", - "SE6D3" - ], - [ - "HCLK_NN6C1", - "NN6D1" - ], - [ - "HCLK_NN6B0", - "NN6C0" - ], - [ - "HCLK_SL1END0", - "SL1BEG0" - ], - [ - "HCLK_NN2BEG1", - "NN2A1" - ], - [ - "HCLK_LVB11", - "LVB_L11" - ], - [ - "HCLK_SS2END1", - "SS2A1" - ], - [ - "HCLK_LV8", - "LV_L9" - ], - [ - "HCLK_NE6D2", - "NE6E2" - ], - [ - "HCLK_NN6C2", - "NN6D2" - ], - [ - "HCLK_NN6BEG2", - "NN6A2" - ], - [ - "HCLK_SE6B3", - "SE6A3" - ], - [ - "HCLK_SS6D3", - "SS6C3" - ], - [ - "HCLK_SS6A0", - "SS6BEG0" - ], - [ - "HCLK_NE6C3", - "NE6D3" - ], - [ - "HCLK_LV2", - "LV_L3" - ], - [ - "HCLK_NN6A3", - "NN6B3" - ], - [ - "HCLK_LVB4", - "LVB_L4" - ], - [ - "HCLK_SR1END1", - "SR1BEG1" - ], - [ - "HCLK_SE6C2", - "SE6B2" - ], - [ - "HCLK_EL1END_S3_0", - "EL1END0" - ], - [ - "HCLK_NN6BEG3", - "NN6A3" - ], - [ - "HCLK_SW6C0", - "SW6B0" - ], - [ - "HCLK_SS6END1", - "SS6E1" - ], - [ - "HCLK_NW2A0", - "NW2A0" - ], - [ - "HCLK_LEAF_CLK_B_TOPL2", - "GCLK_L_B8" - ], - [ - "HCLK_NN6E0", - "NN6END0" - ], - [ - "HCLK_SS6E3", - "SS6D3" - ], - [ - "HCLK_SS6D1", - "SS6C1" - ], - [ - "HCLK_NN6D3", - "NN6E3" - ], - [ - "HCLK_SW2END1", - "SW2BEG1" - ], - [ - "HCLK_NN6E1", - "NN6END1" - ], - [ - "HCLK_LV0", - "LV_L1" - ], - [ - "HCLK_SE6C3", - "SE6B3" - ], - [ - "HCLK_SW6E1", - "SW6D1" - ], - [ - "HCLK_NL1END_S3_0", - "NL1END0" - ], - [ - "HCLK_SW6B0", - "SW6A0" - ], - [ - "HCLK_NL1BEG1", - "NL1END1" - ], - [ - "HCLK_NW6C3", - "NW6D3" - ], - [ - "HCLK_SE6E0", - "SE6D0" - ], - [ - "HCLK_SS2A1", - "SS2BEG1" - ], - [ - "HCLK_LEAF_CLK_B_TOPL5", - "GCLK_L_B11" - ], - [ - "HCLK_SS6END3", - "SS6E3" - ], - [ - "HCLK_LVB8", - "LVB_L8" - ], - [ - "HCLK_SS6C0", - "SS6B0" - ], - [ - "HCLK_SW6END3", - "SW6END_N0_3" - ], - [ - "HCLK_NW2END_S0_0", - "NW2END0" - ], - [ - "HCLK_NN6END_S1_0", - "NN6END0" - ], - [ - "HCLK_NE2BEG1", - "NE2A1" - ], - [ - "HCLK_SS6A3", - "SS6BEG3" - ], - [ - "HCLK_LEAF_CLK_B_TOPL0", - "GCLK_L_B6" - ], - [ - "HCLK_WR1BEG_S0", - "WR1BEG0" - ], - [ - "HCLK_NN6BEG1", - "NN6A1" - ], - [ - "HCLK_SS6E0", - "SS6D0" - ], - [ - "HCLK_LV12", - "LV_L13" - ], - [ - "HCLK_FAN_BOUNCE_S3_6", - "FAN_BOUNCE6" - ], - [ - "HCLK_SS2A3", - "SS2A3" - ], - [ - "HCLK_SW6B2", - "SW6A2" - ], - [ - "HCLK_NW6D1", - "NW6E1" - ], - [ - "HCLK_NN2A1", - "NN2END1" - ], - [ - "HCLK_ER1BEG_S0", - "ER1BEG0" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE_N3_2" - ], - [ - "HCLK_NE6D0", - "NE6E0" - ], - [ - "HCLK_SE2A2", - "SE2BEG2" - ], - [ - "HCLK_SE6D3", - "SE6C3" - ], - [ - "HCLK_ER1END3", - "ER1END_N3_3" - ], - [ - "HCLK_NN6E3", - "NN6END3" - ], - [ - "HCLK_LV17", - "LV_L18" - ], - [ - "HCLK_SE6B2", - "SE6A2" - ], - [ - "HCLK_LV13", - "LV_L14" - ], - [ - "HCLK_NN6D1", - "NN6E1" - ], - [ - "HCLK_NN6D0", - "NN6E0" - ], - [ - "HCLK_SS6A2", - "SS6BEG2" - ], - [ - "HCLK_LVB6", - "LVB_L6" - ], - [ - "HCLK_NW2A3", - "NW2A3" - ], - [ - "HCLK_LVB9", - "LVB_L9" - ], - [ - "HCLK_NE6C1", - "NE6D1" - ], - [ - "HCLK_NE6B3", - "NE6C3" - ], - [ - "HCLK_NN6C0", - "NN6D0" - ], - [ - "HCLK_NW6D3", - "NW6E3" - ], - [ - "HCLK_LVB12", - "LVB_L12" - ], - [ - "HCLK_NR1BEG1", - "NR1END1" - ], - [ - "HCLK_SE2A1", - "SE2BEG1" - ], - [ - "HCLK_SE6C1", - "SE6B1" - ], - [ - "HCLK_NE6B2", - "NE6C2" - ], - [ - "HCLK_SE2A0", - "SE2BEG0" - ], - [ - "HCLK_NE6A1", - "NE6B1" - ], - [ - "HCLK_SL1END2", - "SL1BEG2" - ], - [ - "HCLK_NR1BEG2", - "NR1END2" - ], - [ - "HCLK_LV3", - "LV_L4" - ], - [ - "HCLK_SW6E3", - "SW6D3" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END0" - ], - [ - "HCLK_SE6D1", - "SE6C1" - ], - [ - "HCLK_SS2END_N0_3", - "SS2END_N0_3" - ], - [ - "HCLK_LV7", - "LV_L8" - ], - [ - "HCLK_BYP_BOUNCE6", - "BYP_BOUNCE_N3_6" - ], - [ - "HCLK_SS6E2", - "SS6D2" - ], - [ - "HCLK_NN6BEG0", - "NN6A0" - ], - [ - "HCLK_SW6D2", - "SW6C2" - ], - [ - "HCLK_SR1END2", - "SR1BEG2" - ], - [ - "HCLK_LVB3", - "LVB_L3" - ], - [ - "HCLK_SS6B0", - "SS6A0" - ], - [ - "HCLK_SW2A3", - "SW2BEG3" - ], - [ - "HCLK_NE6A2", - "NE6B2" - ], - [ - "HCLK_LEAF_CLK_B_TOPL1", - "GCLK_L_B7" - ], - [ - "HCLK_LV16", - "LV_L17" - ], - [ - "HCLK_SW2END0", - "SW2BEG0" - ], - [ - "HCLK_NE6D1", - "NE6E1" - ], - [ - "HCLK_LV11", - "LV_L12" - ], - [ - "HCLK_SS6END_N0_3", - "SS6END_N0_3" - ], - [ - "HCLK_NN6B3", - "NN6C3" - ], - [ - "HCLK_NW6A2", - "NW6B2" - ], - [ - "HCLK_SE6D2", - "SE6C2" - ], - [ - "HCLK_SS2A2", - "SS2BEG2" - ], - [ - "HCLK_NN2BEG0", - "NN2A0" - ], - [ - "HCLK_SR1BEG3", - "SR1BEG3" - ], - [ - "HCLK_NN2BEG2", - "NN2A2" - ], - [ - "HCLK_NN6D2", - "NN6E2" - ], - [ - "HCLK_LVB5", - "LVB_L5" - ], - [ - "HCLK_NW2A2", - "NW2A2" - ], - [ - "HCLK_NW6A1", - "NW6B1" - ], - [ - "HCLK_LV4", - "LV_L5" - ], - [ - "HCLK_LV9", - "LV_L10" - ], - [ - "HCLK_SS2A0", - "SS2BEG0" - ], - [ - "HCLK_SE2A3", - "SE2BEG3" - ], - [ - "HCLK_BYP_BOUNCE3", - "BYP_BOUNCE_N3_3" - ], - [ - "HCLK_NW6C1", - "NW6D1" - ], - [ - "HCLK_NW2A1", - "NW2A1" - ], - [ - "HCLK_NN2BEG3", - "NN2A3" - ], - [ - "HCLK_SS6END0", - "SS6E0" - ], - [ - "HCLK_LV6", - "LV_L7" - ], - [ - "HCLK_LV15", - "LV_L16" - ], - [ - "HCLK_NE2END_S3_0", - "NE2END0" - ], - [ - "HCLK_NW6A3", - "NW6B3" - ], - [ - "HCLK_LVB10", - "LVB_L10" - ], - [ - "HCLK_NN2A0", - "NN2END0" - ], - [ - "HCLK_NE6D3", - "NE6E3" - ], - [ - "HCLK_SS2END2", - "SS2A2" - ], - [ - "HCLK_NE2BEG3", - "NE2A3" - ], - [ - "HCLK_NE6A3", - "NE6B3" - ], - [ - "HCLK_WW2END3", - "WW2END_N0_3" - ], - [ - "HCLK_NE6C0", - "NE6D0" - ], - [ - "HCLK_BYP_BOUNCE7", - "BYP_BOUNCE_N3_7" - ], - [ - "HCLK_NE6B1", - "NE6C1" - ], - [ - "HCLK_NN6B2", - "NN6C2" - ], - [ - "HCLK_SW6E2", - "SW6D2" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END_N0_3" - ], - [ - "HCLK_SS6D2", - "SS6C2" - ], - [ - "HCLK_SW6C1", - "SW6B1" - ], - [ - "HCLK_NN2A2", - "NN2END2" - ] - ], - "tile_types": [ - "HCLK_L", - "INT_L" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CLBLM_L_CIN", - "HCLK_CLB_COUT0_R" - ], - [ - "CLBLM_M_CIN", - "HCLK_CLB_COUT1_R" - ] - ], - "tile_types": [ - "CLBLM_R", - "HCLK_CLB" - ], - "grid_deltas": [ - 0, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_LH6_11", - "VBRK_LH6" - ], - [ - "CMT_TOP_LH12_11", - "VBRK_LH12" - ], - [ - "CMT_TOP_NW4END0_11", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_WW2END3_11", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_SW4END2_11", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_EE2BEG3_11", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_EE4C1_11", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_EE2A0_11", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_EE2A1_11", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_SE4BEG3_11", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW4A2_11", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_WW4C2_11", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_LH11_11", - "VBRK_LH11" - ], - [ - "CMT_TOP_WW4C1_11", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_SW4A0_11", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_SE4BEG2_11", - "VBRK_SE4BEG2" - ], - [ - "CMT_TOP_EE4BEG1_11", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_NE4C2_11", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_NW4END3_11", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_EL1BEG3_11", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_WL1END1_11", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_EE4A0_11", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_NW2A1_11", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_WW2END0_11", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_ER1BEG0_11", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NE4C3_11", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_SE4C1_11", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_EE2BEG2_11", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_WW4A3_11", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_SW4A1_11", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_SW4END3_11", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SE2A2_11", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_LH3_11", - "VBRK_LH3" - ], - [ - "CMT_TOP_EE4A1_11", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_NE4BEG1_11", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_SW4END0_11", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_SE4C2_11", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_WR1END2_11", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW4END0_11", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_EE4C0_11", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_SW2A1_11", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_SW4END1_11", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_LH9_11", - "VBRK_LH9" - ], - [ - "CMT_TOP_NW4A1_11", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WR1END3_11", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW2A3_11", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_LH4_11", - "VBRK_LH4" - ], - [ - "CMT_TOP_WW2A1_11", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WW4END2_11", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_EE4C3_11", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_EE4BEG2_11", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_NE2A1_11", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_ER1BEG1_11", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EE2BEG0_11", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_EE2BEG1_11", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_WL1END0_11", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_NW4A2_11", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_NE4C1_11", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_SE2A1_11", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_SE4BEG0_11", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_NE4BEG2_11", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_EE4BEG0_11", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_WW4A1_11", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_NE4BEG0_11", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_EE4B2_11", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_WR1END1_11", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_EE4B3_11", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_WW4B0_11", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_NE2A2_11", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_SE2A0_11", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_NW4A0_11", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_NE2A3_11", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_NE2A0_11", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_EE2A3_11", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_SE4C0_11", - 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[ - "CMT_TOP_WL1END0_4", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_LH8_4", - "VBRK_LH8" - ], - [ - "CMT_TOP_SW2A1_4", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_WW4A1_4", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_EE4A2_4", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_LH7_4", - "VBRK_LH7" - ], - [ - "CMT_TOP_WR1END1_4", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_WW2A0_4", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_NW4END3_4", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_WW4END2_4", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_NE4BEG0_4", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_EE2BEG2_4", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_NE2A0_4", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_NW4END1_4", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_NW2A0_4", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_WW2A2_4", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_NW2A2_4", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WW2A1_4", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_WW2A3_4", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_EE4B1_4", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_WW4C3_4", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_SE4BEG0_4", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_NE4BEG2_4", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_WL1END3_4", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_EE4BEG3_4", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_SE4BEG3_4", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW4C2_4", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_EE4BEG2_4", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_EL1BEG0_4", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WW2END3_4", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_ER1BEG1_4", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_EE2BEG0_4", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_EE4BEG1_4", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_MONITOR_N_4", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_WW4C1_4", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_NE2A3_4", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_NE4C3_4", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_WW4A0_4", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_EE2A0_4", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_EL1BEG2_4", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_EE4B2_4", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_LH9_4", - "VBRK_LH9" - ], - [ - "CMT_TOP_EE4C3_4", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_WW4END1_4", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_LH6_4", - "VBRK_LH6" - ], - [ - "CMT_TOP_EE2A1_4", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_NE4BEG1_4", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_EE2BEG1_4", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_EE4A0_4", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_WW4B2_4", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_LH3_4", - "VBRK_LH3" - ], - [ - "CMT_TOP_SW4A1_4", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_WR1END2_4", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_EE4A3_4", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_SW4END3_4", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_SE4C2_4", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_NE2A1_4", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_WL1END1_4", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_ER1BEG0_4", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NW4A1_4", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_WW4B0_4", - "VBRK_WW4B0" - ] - ], - "tile_types": [ - "CMT_TOP_L_UPPER_T", - "VBRK" - ], - "grid_deltas": [ - -1, - 1 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH8_2", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_LH11_2", - "VBRK_LH11" - ], - [ - "CLK_HROW_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_LH3_2", - "VBRK_LH3" - ], - [ - "CLK_HROW_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_LH1_2", - "VBRK_LH1" - ], - [ - "CLK_HROW_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH9_2", - "VBRK_LH9" - ], - [ - "CLK_HROW_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_LH4_2", - "VBRK_LH4" - ], - [ - "CLK_HROW_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_LH5_2", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH7_2", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_LH10_2", - "VBRK_LH10" - ], - [ - "CLK_HROW_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_LH12_2", - "VBRK_LH12" - ], - [ - "CLK_HROW_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_LH2_2", - "VBRK_LH2" - ], - [ - "CLK_HROW_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_LH6_2", - "VBRK_LH6" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - 2 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_LH8_2", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_LH11_2", - "VBRK_LH11" - ], - [ - "CLK_HROW_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_LH3_2", - "VBRK_LH3" - ], - [ - "CLK_HROW_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_LH1_2", - "VBRK_LH1" - ], - [ - "CLK_HROW_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH9_2", - "VBRK_LH9" - ], - [ - "CLK_HROW_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_LH4_2", - "VBRK_LH4" - ], - [ - "CLK_HROW_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_LH5_2", - "VBRK_LH5" - ], - [ - "CLK_HROW_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH7_2", - "VBRK_LH7" - ], - [ - "CLK_HROW_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_LH10_2", - "VBRK_LH10" - ], - [ - "CLK_HROW_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_LH12_2", - "VBRK_LH12" - ], - [ - "CLK_HROW_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_LH2_2", - "VBRK_LH2" - ], - [ - "CLK_HROW_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_SE4BEG2_2", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_LH6_2", - "VBRK_LH6" - ] - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "grid_deltas": [ - 1, - 2 - ] - }, - { - "wire_pairs": [ - [ - "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "HCLK_CMT_PHASEREF_ABOVE0" - ], - [ - "MMCM_CLK_FREQBB_REBUFOUT2", - "HCLK_CMT_FREQ_REF_NS2" - ], - [ - "CMT_PHASER_BOT_OBURSTPENDING0", - "HCLK_CMT_OBURSTPENDING0" - ], - [ - "CMT_PHASER_BOT_REFMUX_2", - "HCLK_CMT_FREQ_PHASER_REFMUX_2" - ], - [ - "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "HCLK_CMT_PHASEREF_BELOW0" - ], - [ - "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "HCLK_CMT_PHASEREF_ABOVE1" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM8", - "HCLK_CMT_MUX_CLK_MMCM8" - ], - [ - "CMT_BOT_HCLKMUX_CLKINT_1", - "HCLK_CMT_MUX_CLKINT_1" - ], - [ - "CMT_PHASER_BOT_REFMUX_1", - "HCLK_CMT_FREQ_PHASER_REFMUX_1" - ], - [ - "CMT_PHASER_BOT_IBURSTPENDING1", - "HCLK_CMT_IBURSTPENDING1" - ], - [ - "CMT_PHASER_BOT_ENCALIB1", - "HCLK_CMT_ECALIB1" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM9", - "HCLK_CMT_MUX_CLK_MMCM9" - ], - [ - "CMT_PHASER_BOT_REFMUX_0", - "HCLK_CMT_FREQ_PHASER_REFMUX_0" - ], - [ - "MMCM_CLK_FREQBB_REBUFOUT3", - "HCLK_CMT_FREQ_REF_NS3" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM7", - "HCLK_CMT_MUX_CLK_MMCM7" - ], - [ - "CMT_PHASER_DOWN_PHASERREF1", - "HCLK_CMT_BUFMR_PHASEREF1" - ], - [ - "CMT_LR_LOWER_T_CLK_IN3_HCLK", - "HCLK_CMT_MUX_MMCM_CLKFBIN" - ], - [ - "CMT_LR_LOWER_T_CLK_IN1_HCLK", - "HCLK_CMT_MUX_MMCM_CLKIN1" - ], - [ - "CMT_BOT_HCLKMUX_CLKINT_0", - "HCLK_CMT_MUX_CLKINT_0" - ], - [ - "CMT_PHASER_BOT_IRANKA0", - "HCLK_CMT_PHY_CONTROL_IRANKA0" - ], - [ - "CMT_PHASER_BOT_ENCALIB0", - "HCLK_CMT_ECALIB0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM4", - "HCLK_CMT_MUX_CLK_MMCM4" - ], - [ - "CMT_LR_LOWER_T_CLK_PERF2", - "HCLK_CMT_MUX_MMCM_MUXED2" - ], - [ - "CMT_PHASER_IN_B_RCLK1", - "HCLK_CMT_PHASERIN_RCLK1" - ], - [ - "CMT_LR_LOWER_T_CLK_PERF1", - "HCLK_CMT_MUX_MMCM_MUXED1" - ], - [ - "MMCM_CLK_FREQBB_REBUFOUT1", - "HCLK_CMT_FREQ_REF_NS1" - ], - [ - "CMT_PHASER_BOT_IRANKB0", - "HCLK_CMT_PHY_CONTROL_IRANKB0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM11", - "HCLK_CMT_MUX_CLK_MMCM11" - ], - [ - "CMT_PHASER_BOT_IRANKA1", - "HCLK_CMT_PHY_CONTROL_IRANKA1" - ], - [ - "CMT_LR_LOWER_T_CLK_PERF0", - "HCLK_CMT_MUX_MMCM_MUXED0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM1", - "HCLK_CMT_MUX_CLK_MMCM1" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM3", - "HCLK_CMT_MUX_CLK_MMCM3" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM12", - "HCLK_CMT_MUX_CLK_MMCM12" - ], - [ - "CMT_PHASER_BOT_SYNC_BB", - "HCLK_CMT_PHY_SYNC_BB" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM2", - "HCLK_CMT_MUX_CLK_MMCM2" - ], - [ - "CMT_PHASER_BOT_IBURSTPENDING0", - "HCLK_CMT_IBURSTPENDING0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM13", - "HCLK_CMT_MUX_CLK_MMCM13" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM0", - "HCLK_CMT_MUX_CLK_MMCM0" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM10", - "HCLK_CMT_MUX_CLK_MMCM10" - ], - [ - "CMT_LR_LOWER_T_CLK_IN2_HCLK", - "HCLK_CMT_MUX_MMCM_CLKIN2" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM6", - "HCLK_CMT_MUX_CLK_MMCM6" - ], - [ - "CMT_LR_LOWER_T_CLK_PERF3", - "HCLK_CMT_MUX_MMCM_MUXED3" - ], - [ - "CMT_PHASER_BOT_IRANKB1", - "HCLK_CMT_PHY_CONTROL_IRANKB1" - ], - [ - "CMT_PHASER_BOT_OBURSTPENDING1", - "HCLK_CMT_OBURSTPENDING1" - ], - [ - "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "HCLK_CMT_PHASEREF_BELOW1" - ], - [ - "CMT_LR_LOWER_T_CLK_MMCM5", - "HCLK_CMT_MUX_CLK_MMCM5" - ], - [ - "CMT_PHASER_IN_A_RCLK0", - "HCLK_CMT_PHASERIN_RCLK0" - ], - [ - "CMT_PHASER_DOWN_PHASERREF0", - "HCLK_CMT_BUFMR_PHASEREF0" - ], - [ - "MMCM_CLK_FREQBB_REBUFOUT0", - "HCLK_CMT_FREQ_REF_NS0" - ] - ], - "tile_types": [ - "CMT_TOP_L_LOWER_T", - "HCLK_CMT_L" - ], - "grid_deltas": [ - 0, - -8 - ] - }, - { - "wire_pairs": [ - [ - "INT_FEEDTHRU_2_SW4A2", - "MONITOR_SW4A2_8" - ], - [ - "INT_FEEDTHRU_2_EE4BEG1", - "MONITOR_EE4BEG1_8" - ], - [ - "INT_FEEDTHRU_2_EE4C3", - "MONITOR_EE4C3_8" - ], - [ - "INT_FEEDTHRU_2_EE4A3", - "MONITOR_EE4A3_8" - ], - [ - "INT_FEEDTHRU_2_LH11", - "MONITOR_LH11_8" - ], - [ - "INT_FEEDTHRU_2_SE4C0", - "MONITOR_SE4C0_8" - ], - [ - "INT_FEEDTHRU_2_WR1END3", - "MONITOR_WR1END3_8" - ], - [ - "INT_FEEDTHRU_2_WW4END0", - "MONITOR_WW4END0_8" - ], - [ - "INT_FEEDTHRU_2_NW2A0", - "MONITOR_NW2A0_8" - ], - [ - "INT_FEEDTHRU_2_NE4C1", - "MONITOR_NE4C1_8" - ], - [ - "INT_FEEDTHRU_2_NW2A2", - "MONITOR_NW2A2_8" - ], - [ - "INT_FEEDTHRU_2_NE2A3", - "MONITOR_NE2A3_8" - ], - [ - "INT_FEEDTHRU_2_WW4C0", - "MONITOR_WW4C0_8" - ], - [ - "INT_FEEDTHRU_2_WW2END0", - "MONITOR_WW2END0_8" - ], - [ - "INT_FEEDTHRU_2_WW2A1", - "MONITOR_WW2A1_8" - ], - [ - "INT_FEEDTHRU_2_EE4A0", - "MONITOR_EE4A0_8" - ], - [ - "INT_FEEDTHRU_2_ER1BEG2", - "MONITOR_ER1BEG2_8" - ], - [ - "INT_FEEDTHRU_2_LH2", - "MONITOR_LH2_8" - ], - [ - "INT_FEEDTHRU_2_SW4END0", - "MONITOR_SW4END0_8" - ], - [ - "INT_FEEDTHRU_2_ER1BEG0", - "MONITOR_ER1BEG0_8" - ], - [ - "INT_FEEDTHRU_2_SW4A0", - "MONITOR_SW4A0_8" - ], - [ - "INT_FEEDTHRU_2_NE4C2", - "MONITOR_NE4C2_8" - ], - [ - "INT_FEEDTHRU_2_WW4B0", - "MONITOR_WW4B0_8" - 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"INT_INTERFACE_BRAM_IMUX11", - "BRAM_IMUX11_0" - ], - [ - "INT_INTERFACE_SW2A0", - "BRAM_SW2A0_0" - ], - [ - "INT_INTERFACE_BYP1", - "BRAM_BYP1_0" - ], - [ - "INT_INTERFACE_EE2A2", - "BRAM_EE2A2_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX18", - "BRAM_IMUX18_UTURN_0" - ], - [ - "INT_INTERFACE_LH12", - "BRAM_LH12_0" - ], - [ - "INT_INTERFACE_WW2A0", - "BRAM_WW2A0_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX32", - "BRAM_IMUX32_0" - ], - [ - "INT_INTERFACE_SE2A0", - "BRAM_SE2A0_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX4", - "BRAM_IMUX4_0" - ], - [ - "INT_INTERFACE_SW4END3", - "BRAM_SW4END3_0" - ], - [ - "INT_INTERFACE_WW4B3", - "BRAM_WW4B3_0" - ], - [ - "INT_INTERFACE_SE2A2", - "BRAM_SE2A2_0" - ], - [ - "INT_INTERFACE_BYP6", - "BRAM_BYP6_0" - ], - [ - "INT_INTERFACE_SW4END0", - "BRAM_SW4END0_0" - ], - [ - "INT_INTERFACE_EE4C2", - "BRAM_EE4C2_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX46", - "BRAM_IMUX46_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX6", - "BRAM_IMUX6_UTURN_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B20", - "BRAM_LOGIC_OUTS_B20_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX35", - "BRAM_IMUX35_0" - ], - [ - "INT_INTERFACE_CLK1", - "BRAM_CLK1_0" - ], - [ - "INT_INTERFACE_NE2A2", - "BRAM_NE2A2_0" - ], - [ - "INT_INTERFACE_NW2A1", - "BRAM_NW2A1_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX33", - "BRAM_IMUX33_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX36", - "BRAM_IMUX36_UTURN_0" - ], - [ - "INT_INTERFACE_FAN1", - "BRAM_FAN1_0" - ], - [ - "INT_INTERFACE_MONITOR_N", - "BRAM_MONITOR_N_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX12", - "BRAM_IMUX12_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B15", - "BRAM_LOGIC_OUTS_B15_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX5", - "BRAM_IMUX5_UTURN_0" - ], - [ - "INT_INTERFACE_SE4BEG2", - "BRAM_SE4BEG2_0" - ], - [ - "INT_INTERFACE_WR1END2", - "BRAM_WR1END2_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX31", - "BRAM_IMUX31_UTURN_0" - ], - [ - "INT_INTERFACE_SW2A3", - "BRAM_SW2A3_0" - ], - [ - "INT_INTERFACE_BYP0", - "BRAM_BYP0_0" - ], - [ - "INT_INTERFACE_BYP5", - "BRAM_BYP5_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX45", - "BRAM_IMUX45_UTURN_0" - ], - [ - "INT_INTERFACE_NW4END1", - "BRAM_NW4END1_0" - ], - [ - "INT_INTERFACE_SW4A2", - "BRAM_SW4A2_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX24", - "BRAM_IMUX24_UTURN_0" - ], - [ - "INT_INTERFACE_WL1END3", - "BRAM_WL1END3_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX43", - "BRAM_IMUX43_UTURN_0" - ], - [ - "INT_INTERFACE_SE2A1", - "BRAM_SE2A1_0" - ], - [ - "INT_INTERFACE_LH6", - "BRAM_LH6_0" - ], - [ - "INT_INTERFACE_WW4C2", - "BRAM_WW4C2_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX26", - "BRAM_IMUX26_0" - ], - [ - "INT_INTERFACE_FAN7", - "BRAM_FAN7_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B3", - "BRAM_LOGIC_OUTS_B3_0" - ], - [ - "INT_INTERFACE_LH4", - "BRAM_LH4_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX9", - "BRAM_IMUX9_0" - ], - [ - "INT_INTERFACE_BYP7", - "BRAM_BYP7_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B13", - "BRAM_LOGIC_OUTS_B13_0" - ], - [ - "INT_INTERFACE_WR1END3", - "BRAM_WR1END3_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX47", - "BRAM_IMUX47_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX25", - "BRAM_IMUX25_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX1", - "BRAM_IMUX1_UTURN_0" - ], - [ - "INT_INTERFACE_NE4BEG1", - "BRAM_NE4BEG1_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX22", - "BRAM_IMUX22_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX44", - "BRAM_IMUX44_0" - ], - [ - "INT_INTERFACE_ER1BEG3", - "BRAM_ER1BEG3_0" - ], - [ - "INT_INTERFACE_SE4C2", - "BRAM_SE4C2_0" - ], - [ - "INT_INTERFACE_WW4A0", - "BRAM_WW4A0_0" - ], - [ - "INT_INTERFACE_WW4A3", - "BRAM_WW4A3_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX42", - "BRAM_IMUX42_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B19", - "BRAM_LOGIC_OUTS_B19_0" - ], - [ - "INT_INTERFACE_EE4BEG2", - "BRAM_EE4BEG2_0" - ], - [ - "INT_INTERFACE_EL1BEG3", - "BRAM_EL1BEG3_0" - ], - [ - "INT_INTERFACE_WW2END3", - "BRAM_WW2END3_0" - ], - [ - "INT_INTERFACE_WW4C1", - "BRAM_WW4C1_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX2", - "BRAM_IMUX2_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B5", - "BRAM_LOGIC_OUTS_B5_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B7", - "BRAM_LOGIC_OUTS_B7_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX2", - "BRAM_IMUX2_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX39", - "BRAM_IMUX39_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX37", - "BRAM_IMUX37_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX3", - "BRAM_IMUX3_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX31", - "BRAM_IMUX31_0" - ], - [ - "INT_INTERFACE_NW2A0", - "BRAM_NW2A0_0" - ], - [ - "INT_INTERFACE_EE2BEG0", - "BRAM_EE2BEG0_0" - ], - [ - "INT_INTERFACE_EE2BEG2", - "BRAM_EE2BEG2_0" - ], - [ - "INT_INTERFACE_WW4A1", - "BRAM_WW4A1_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX14", - "BRAM_IMUX14_0" - ], - [ - "INT_INTERFACE_SE4BEG1", - "BRAM_SE4BEG1_0" - ], - [ - "INT_INTERFACE_BRAM_IMUX40", - "BRAM_IMUX40_0" - ], - [ - "INT_INTERFACE_WW2END0", - "BRAM_WW2END0_0" - ], - [ - "INT_INTERFACE_SW2A1", - "BRAM_SW2A1_0" - ], - [ - "INT_INTERFACE_EE4C1", - "BRAM_EE4C1_0" - ], - [ - "INT_INTERFACE_LH11", - "BRAM_LH11_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX27", - "BRAM_IMUX27_UTURN_0" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_B12", - "BRAM_LOGIC_OUTS_B12_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX28", - "BRAM_IMUX28_UTURN_0" - ], - [ - "INT_INTERFACE_BRAM_UTURN_R_IMUX22", - "BRAM_IMUX22_UTURN_0" - ], - [ - "INT_INTERFACE_WW2END2", - "BRAM_WW2END2_0" - ] - ], - "tile_types": [ - "BRAM_INT_INTERFACE_R", - "BRAM_R" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_SW4A1", - "VBRK_SW4A1" - ], - [ - "CLK_FEED_EE2A2", - "VBRK_EE2A2" - ], - [ - "CLK_FEED_WW4B2", - "VBRK_WW4B2" - ], - [ - "CLK_FEED_EE2BEG0", - "VBRK_EE2BEG0" - ], - [ - "CLK_FEED_SE4BEG1", - "VBRK_SE4BEG1" - ], - [ - "CLK_FEED_EE4BEG3", - "VBRK_EE4BEG3" - ], - [ - "CLK_FEED_NW4END3", - "VBRK_NW4END3" - ], - [ - "CLK_FEED_EL1BEG1", - "VBRK_EL1BEG1" - ], - [ - "CLK_FEED_EE4BEG1", - "VBRK_EE4BEG1" - ], - [ - "CLK_FEED_WR1END3", - "VBRK_WR1END3" - ], - [ - "CLK_FEED_NE4BEG1", - "VBRK_NE4BEG1" - ], - [ - "CLK_FEED_WW2A1", - "VBRK_WW2A1" - ], - [ - "CLK_FEED_WW2A2", - "VBRK_WW2A2" - ], - [ - "CLK_FEED_WW2A0", - "VBRK_WW2A0" - ], - [ - "CLK_FEED_EE4C3", - "VBRK_EE4C3" - ], - [ - "CLK_FEED_LH3", - "VBRK_LH3" - ], - [ - "CLK_FEED_WW4A2", - "VBRK_WW4A2" - ], - [ - "CLK_FEED_SW2A1", - "VBRK_SW2A1" - ], - [ - "CLK_FEED_WW4END1", - "VBRK_WW4END1" - ], - [ - "CLK_FEED_SE2A3", - "VBRK_SE2A3" - ], - [ - "CLK_FEED_SW2A2", - "VBRK_SW2A2" - ], - [ - "CLK_FEED_SE4BEG2", - "VBRK_SE4BEG2" - ], - [ - "CLK_FEED_LH8", - "VBRK_LH8" - ], - [ - "CLK_FEED_WW4C3", - "VBRK_WW4C3" - ], - [ - "CLK_FEED_SW2A3", - "VBRK_SW2A3" - ], - [ - "CLK_FEED_NW4A3", - "VBRK_NW4A3" - ], - [ - "CLK_FEED_EE4B2", - "VBRK_EE4B2" - ], - [ - "CLK_FEED_WW4C0", - "VBRK_WW4C0" - ], - [ - "CLK_FEED_EE2BEG2", - "VBRK_EE2BEG2" - ], - [ - "CLK_FEED_WW2END3", - "VBRK_WW2END3" - ], - [ - "CLK_FEED_NE2A1", - "VBRK_NE2A1" - ], - [ - "CLK_FEED_EE4A1", - "VBRK_EE4A1" - ], - [ - "CLK_FEED_EE2A3", - "VBRK_EE2A3" - ], - [ - "CLK_FEED_NW4A2", - "VBRK_NW4A2" - ], - [ - "CLK_FEED_WW4B0", - "VBRK_WW4B0" - ], - [ - "CLK_FEED_SW2A0", - "VBRK_SW2A0" - ], - [ - "CLK_FEED_EE4C2", - "VBRK_EE4C2" - ], - [ - "CLK_FEED_SW4A3", - "VBRK_SW4A3" - ], - [ - "CLK_FEED_WW4END3", - "VBRK_WW4END3" - ], - [ - "CLK_FEED_MONITOR_N", - "VBRK_MONITOR_N" - ], - [ - "CLK_FEED_EE4A3", - "VBRK_EE4A3" - ], - [ - "CLK_FEED_WW4A1", - "VBRK_WW4A1" - ], - [ - "CLK_FEED_NW2A2", - "VBRK_NW2A2" - ], - [ - "CLK_FEED_NE2A0", - "VBRK_NE2A0" - ], - [ - "CLK_FEED_WL1END1", - "VBRK_WL1END1" - ], - [ - "CLK_FEED_SE4C1", - "VBRK_SE4C1" - ], - [ - "CLK_FEED_NE4C3", - "VBRK_NE4C3" - ], - [ - "CLK_FEED_NE4C0", - "VBRK_NE4C0" - ], - [ - "CLK_FEED_SE4BEG0", - "VBRK_SE4BEG0" - ], - [ - "CLK_FEED_LH1", - "VBRK_LH1" - ], - [ - "CLK_FEED_WW2A3", - "VBRK_WW2A3" - ], - [ - "CLK_FEED_EE4A2", - "VBRK_EE4A2" - ], - [ - "CLK_FEED_SE4C3", - "VBRK_SE4C3" - ], - [ - "CLK_FEED_SW4END0", - "VBRK_SW4END0" - ], - [ - "CLK_FEED_WW2END0", - "VBRK_WW2END0" - ], - [ - "CLK_FEED_WW4A0", - "VBRK_WW4A0" - ], - [ - "CLK_FEED_EE4C0", - "VBRK_EE4C0" - ], - [ - "CLK_FEED_WL1END2", - "VBRK_WL1END2" - ], - [ - "CLK_FEED_LH12", - "VBRK_LH12" - ], - [ - "CLK_FEED_WW4A3", - "VBRK_WW4A3" - ], - [ - "CLK_FEED_EL1BEG2", - "VBRK_EL1BEG2" - ], - [ - "CLK_FEED_WW2END2", - "VBRK_WW2END2" - ], - [ - "CLK_FEED_EE4C1", - "VBRK_EE4C1" - ], - [ - "CLK_FEED_NE2A2", - "VBRK_NE2A2" - ], - [ - "CLK_FEED_WW4C1", - "VBRK_WW4C1" - ], - [ - "CLK_FEED_LH9", - "VBRK_LH9" - ], - [ - "CLK_FEED_LH4", - "VBRK_LH4" - ], - [ - "CLK_FEED_LH11", - "VBRK_LH11" - ], - [ - "CLK_FEED_NE4BEG2", - "VBRK_NE4BEG2" - ], - [ - "CLK_FEED_ER1BEG1", - "VBRK_ER1BEG1" - ], - [ - "CLK_FEED_NW2A0", - "VBRK_NW2A0" - ], - [ - "CLK_FEED_NE2A3", - "VBRK_NE2A3" - ], - [ - "CLK_FEED_EE2A1", - "VBRK_EE2A1" - ], - [ - "CLK_FEED_WW4END0", - "VBRK_WW4END0" - ], - [ - "CLK_FEED_EE4B0", - "VBRK_EE4B0" - ], - [ - "CLK_FEED_SW4END2", - "VBRK_SW4END2" - ], - [ - "CLK_FEED_WL1END3", - "VBRK_WL1END3" - ], - [ - "CLK_FEED_NE4BEG3", - "VBRK_NE4BEG3" - ], - [ - "CLK_FEED_NE4BEG0", - "VBRK_NE4BEG0" - ], - [ - "CLK_FEED_NW4END2", - "VBRK_NW4END2" - ], - [ - "CLK_FEED_WW4B3", - "VBRK_WW4B3" - ], - [ - "CLK_FEED_EE2BEG1", - "VBRK_EE2BEG1" - ], - [ - "CLK_FEED_NE4C1", - "VBRK_NE4C1" - ], - [ - "CLK_FEED_EE4B3", - "VBRK_EE4B3" - ], - [ - "CLK_FEED_EL1BEG0", - "VBRK_EL1BEG0" - ], - [ - "CLK_FEED_MONITOR_P", - "VBRK_MONITOR_P" - ], - [ - "CLK_FEED_SE2A0", - "VBRK_SE2A0" - ], - [ - "CLK_FEED_WR1END1", - "VBRK_WR1END1" - ], - [ - "CLK_FEED_SW4A0", - "VBRK_SW4A0" - ], - [ - "CLK_FEED_WW4C2", - "VBRK_WW4C2" - ], - [ - "CLK_FEED_SE4C0", - "VBRK_SE4C0" - ], - [ - "CLK_FEED_LH6", - "VBRK_LH6" - ], - [ - "CLK_FEED_EE2BEG3", - "VBRK_EE2BEG3" - ], - [ - "CLK_FEED_WR1END0", - "VBRK_WR1END0" - ], - [ - "CLK_FEED_SW4END1", - "VBRK_SW4END1" - ], - [ - "CLK_FEED_SE2A1", - "VBRK_SE2A1" - ], - [ - "CLK_FEED_NW2A1", - "VBRK_NW2A1" - ], - [ - "CLK_FEED_WR1END2", - "VBRK_WR1END2" - ], - [ - "CLK_FEED_NW4A1", - "VBRK_NW4A1" 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"CMT_FIFO_L_BYP4_3", - "INT_INTERFACE_BYP4" - ], - [ - "CMT_FIFO_NE2A2_3", - "INT_INTERFACE_NE2A2" - ], - [ - "CMT_FIFO_LH5_3", - "INT_INTERFACE_LH5" - ], - [ - "CMT_FIFO_SW4A3_3", - "INT_INTERFACE_SW4A3" - ], - [ - "CMT_FIFO_WW2END2_3", - "INT_INTERFACE_WW2END2" - ], - [ - "CMT_FIFO_WR1END0_3", - "INT_INTERFACE_WR1END0" - ], - [ - "CMT_FIFO_SW4A2_3", - "INT_INTERFACE_SW4A2" - ], - [ - "CMT_FIFO_LH6_3", - "INT_INTERFACE_LH6" - ] - ], - "tile_types": [ - "CMT_FIFO_L", - "INT_INTERFACE_L" - ], - "grid_deltas": [ - 1, - 3 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_WL1END0_6", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_WW4B0_6", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW4B1_6", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_SW4A0_6", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_SE4BEG2_6", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_WW2A0_6", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_NE4C3_6", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_NE4BEG3_6", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_WW4END1_6", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_WL1END3_6", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE4A0_6", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_WW4A0_6", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_SW2A3_6", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_SE4BEG1_6", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_SW2A1_6", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_SE4BEG0_6", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_EL1BEG1_6", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_EE4C0_6", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_NW4END0_6", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_LH4_6", - "VBRK_LH4" - ], - [ - "CLK_HROW_SW4A3_6", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_LH3_6", - "VBRK_LH3" - ], - [ - "CLK_HROW_SW4A2_6", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW4A2_6", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_SW4A1_6", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_NW4END2_6", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE2A1_6", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW4A2_6", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_SE4C3_6", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_SW4END2_6", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_LH7_6", - "VBRK_LH7" - ], - [ - "CLK_HROW_SW2A2_6", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_WW4B2_6", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_WW4C2_6", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_EL1BEG0_6", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW4C0_6", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_WW4END0_6", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_WW4END3_6", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_WW4END2_6", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_LH9_6", - "VBRK_LH9" - ], - [ - "CLK_HROW_WW2END1_6", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_NE4BEG0_6", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WW4B3_6", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WR1END1_6", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NW4END3_6", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_WL1END2_6", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_NE4BEG1_6", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_NE4C1_6", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_NE2A2_6", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_SE2A1_6", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE4B1_6", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EE4C1_6", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_WW4C3_6", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_EE4C2_6", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_SE4C2_6", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_EE4B3_6", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_EE4A3_6", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_NE2A3_6", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_SE4C1_6", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_EE2BEG0_6", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_EE4BEG2_6", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WW4A3_6", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_SW2A0_6", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_SW4END1_6", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_WL1END1_6", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_NW4END1_6", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_WW2END3_6", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NW4A1_6", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE4A2_6", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_LH5_6", - "VBRK_LH5" - ], - [ - "CLK_HROW_NW4A0_6", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_WW2A2_6", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_EE4BEG0_6", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_EE4BEG1_6", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_SE2A0_6", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_ER1BEG1_6", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_LH10_6", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE2BEG1_6", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_LH2_6", - "VBRK_LH2" - ], - [ - "CLK_HROW_NE4C2_6", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW4C1_6", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_EE4B0_6", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_NW4A3_6", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_EL1BEG2_6", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_MONITOR_N_6", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_EE2A3_6", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_EE2BEG3_6", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_ER1BEG0_6", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_NE4BEG2_6", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_EE2A2_6", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NW2A0_6", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_EE4C3_6", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_NE4C0_6", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_EL1BEG3_6", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_WW2A3_6", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_LH1_6", - "VBRK_LH1" - ], - [ - "CLK_HROW_NE2A0_6", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WR1END2_6", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_NW2A1_6", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SW4END0_6", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW2A1_6", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW4A1_6", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_ER1BEG2_6", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_LH6_6", - "VBRK_LH6" - ], - [ - "CLK_HROW_NE2A1_6", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_LH12_6", - "VBRK_LH12" - ], - [ - "CLK_HROW_WR1END0_6", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_MONITOR_P_6", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_WR1END3_6", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_SE4BEG3_6", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2END2_6", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_LH11_6", - "VBRK_LH11" - ], - [ - "CLK_HROW_SE2A3_6", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_EE4BEG3_6", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_EE4A1_6", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_EE2BEG2_6", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_EE4B2_6", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH8_6", - "VBRK_LH8" - ], - [ - "CLK_HROW_ER1BEG3_6", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_EE2A0_6", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_NW2A3_6", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_SE4C0_6", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_WW2END0_6", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_SE2A2_6", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_NW2A2_6", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4END3_6", - "VBRK_SW4END3" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -3 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_SE6B3", - "SE6B3" - ], - [ - "HCLK_SS6A2", - "SS6A2" - ], - [ - "HCLK_NW6A2", - "NW6A2" - ], - [ - "HCLK_SR1BEG3", - "SR1END3" - ], - [ - "HCLK_NE2BEG2", - "NE2BEG2" - ], - [ - "HCLK_WR1BEG_S0", - "WR1BEG_S0" - ], - [ - "HCLK_NE6C2", - "NE6C2" - ], - [ - "HCLK_SR1END1", - "SR1END1" - ], - [ - "HCLK_LVB10", - "LVB9" - ], - [ - "HCLK_NE6A0", - "NE6A0" - ], - [ - "HCLK_LVB7", - "LVB6" - ], - [ - "HCLK_SS6E1", - "SS6E1" - ], - [ - "HCLK_NW2A1", - "NW2BEG1" - ], - [ - "HCLK_NE2BEG1", - "NE2BEG1" - ], - [ - "HCLK_NR1BEG3", - "NR1BEG3" - ], - [ - "HCLK_NE6A1", - "NE6A1" - ], - [ - "HCLK_SE6C2", - "SE6C2" - ], - [ - "HCLK_FAN_BOUNCE_S3_6", - "FAN_BOUNCE_S3_6" - ], - [ - "HCLK_NL1END_S3_0", - "NL1END_S3_0" - ], - [ - "HCLK_NR1BEG1", - "NR1BEG1" - ], - [ - "HCLK_NN2A2", - "NN2A2" - ], - [ - "HCLK_LVB2", - "LVB1" - ], - [ - "HCLK_LEAF_CLK_B_BOT1", - "GCLK_B1" - ], - [ - "HCLK_LV1", - "LV1" - ], - [ - "HCLK_SE6C3", - "SE6C3" - ], - [ - "HCLK_SS2END2", - "SS2END2" - ], - [ - "HCLK_SE6D0", - "SE6D0" - ], - [ - "HCLK_NN6C3", - "NN6C3" - ], - [ - "HCLK_SS6END_N0_3", - "SS6END3" - ], - [ - "HCLK_SW6E0", - "SW6E0" - ], - [ - "HCLK_NE6D3", - "NE6D3" - ], - [ - "HCLK_SE2A1", - "SE2A1" - ], - [ - "HCLK_SW2END1", - "SW2A1" - ], - [ - "HCLK_NE6C3", - "NE6C3" - ], - [ - "HCLK_ER1END3", - "ER1END3" - ], - [ - "HCLK_NW6D2", - "NW6D2" - ], - [ - "HCLK_LVB8", - "LVB7" - ], - [ - "HCLK_SE6C1", - "SE6C1" - ], - [ - "HCLK_NN6B1", - "NN6B1" - ], - [ - "HCLK_LVB11", - "LVB10" - ], - [ - "HCLK_NW6B0", - "NW6B0" - ], - [ - "HCLK_EL1BEG3", - "EL1BEG3" - ], - [ - "HCLK_SE6E1", - "SE6E1" - ], - [ - "HCLK_SS2A0", - "SS2A0" - ], - [ - "HCLK_NN6C1", - "NN6C1" - ], - [ - "HCLK_NN2A3", - "NN2A3" - ], - [ - "HCLK_SS2BEG3", - "SS2A3" - ], - [ - "HCLK_NE6B3", - "NE6B3" - ], - [ - "HCLK_NN6B3", - "NN6B3" - ], - [ - "HCLK_SE6D1", - "SE6D1" - ], - [ - "HCLK_SS6C2", - "SS6C2" - ], - [ - "HCLK_SW6C3", - "SW6C3" - ], - [ - "HCLK_NN2BEG1", - "NN2BEG1" - ], - [ - "HCLK_ER1BEG_S0", - "ER1BEG_S0" - ], - [ - "HCLK_LV14", - "LV14" - ], - [ - "HCLK_NN2BEG2", - "NN2BEG2" - ], - [ - "HCLK_NN2BEG0", - "NN2BEG0" - ], - [ - "HCLK_SS2A1", - "SS2A1" - ], - [ - "HCLK_SS6END1", - "SS6END1" - ], - [ - "HCLK_NE2END_S3_0", - "NE2END_S3_0" - ], - [ - "HCLK_NE2BEG0", - "NE2BEG0" - ], - [ - "HCLK_NL1BEG1", - "NL1BEG1" - ], - [ - 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- [ - "HCLK_NW6C0", - "NW6C0" - ], - [ - "HCLK_LEAF_CLK_B_BOT3", - "GCLK_B3" - ], - [ - "HCLK_SL1END3", - "SL1END3" - ], - [ - "HCLK_NE6B1", - "NE6B1" - ], - [ - "HCLK_SE6E3", - "SE6E3" - ], - [ - "HCLK_NE6B2", - "NE6B2" - ], - [ - "HCLK_NW6C3", - "NW6C3" - ], - [ - "HCLK_SW6B3", - "SW6B3" - ], - [ - "HCLK_LVB9", - "LVB8" - ], - [ - "HCLK_NN6BEG0", - "NN6BEG0" - ], - [ - "HCLK_LV10", - "LV10" - ], - [ - "HCLK_BYP_BOUNCE2", - "BYP_BOUNCE2" - ], - [ - "HCLK_SW6D0", - "SW6D0" - ], - [ - "HCLK_NN6D0", - "NN6D0" - ], - [ - "HCLK_LVB4", - "LVB3" - ], - [ - "HCLK_NN6D1", - "NN6D1" - ], - [ - "HCLK_SS6D2", - "SS6D2" - ], - [ - "HCLK_SW6D2", - "SW6D2" - ], - [ - "HCLK_SW6E2", - "SW6E2" - ], - [ - "HCLK_WR1END_S1_0", - "WR1END_S1_0" - ], - [ - "HCLK_WW4END_S0_0", - "WW4END_S0_0" - ], - [ - "HCLK_NN2END_S2_0", - "NN2END_S2_0" - ], - [ - "HCLK_SW2END_N0_3", - "SW2END3" - ], - [ - "HCLK_LVB1", - "LVB0" - ], - [ - "HCLK_SS2A3", - "SS2END3" - ], - [ - "HCLK_SE6D2", - "SE6D2" - ], - [ - "HCLK_SS6A1", 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7 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_GTX_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN12" - ], - [ - "HCLK_GTX_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN10" - ], - [ - "HCLK_GTX_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN8" - ], - [ - "HCLK_GTX_CK_IN9", - "HCLK_INT_INTERFACE_CK_IN9" - ], - [ - "HCLK_GTX_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN7" - ], - [ - "HCLK_GTX_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN6" - ], - [ - "HCLK_GTX_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN13" - ], - [ - "HCLK_GTX_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN5" - ], - [ - "HCLK_GTX_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN4" - ], - [ - "HCLK_GTX_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN11" - ] - ], - "tile_types": [ - "HCLK_GTX", - "HCLK_INT_INTERFACE" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_PMV_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CLK_PMV_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "CLK_PMV_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CLK_PMV_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CLK_PMV_WW4A1_2", - "VBRK_WW4A1" - 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"DSP_ACOUT14", - "HCLK_DSP_ACIN14" - ], - [ - "DSP_PCOUT21", - "HCLK_DSP_PCIN21" - ], - [ - "DSP_BCOUT15", - "HCLK_DSP_BCIN15" - ], - [ - "DSP_BCOUT9", - "HCLK_DSP_BCIN9" - ], - [ - "DSP_PCOUT27", - "HCLK_DSP_PCIN27" - ], - [ - "DSP_PCOUT3", - "HCLK_DSP_PCIN3" - ], - [ - "DSP_PCOUT24", - "HCLK_DSP_PCIN24" - ], - [ - "DSP_BCOUT16", - "HCLK_DSP_BCIN16" - ], - [ - "DSP_PCOUT38", - "HCLK_DSP_PCIN38" - ], - [ - "DSP_BCOUT5", - "HCLK_DSP_BCIN5" - ], - [ - "DSP_ACOUT23", - "HCLK_DSP_ACIN23" - ], - [ - "DSP_CARRYCASCOUT", - "HCLK_DSP_CARRYCASCIN" - ], - [ - "DSP_PCOUT40", - "HCLK_DSP_PCIN40" - ], - [ - "DSP_ACOUT10", - "HCLK_DSP_ACIN10" - ], - [ - "DSP_BCOUT6", - "HCLK_DSP_BCIN6" - ], - [ - "DSP_PCOUT20", - "HCLK_DSP_PCIN20" - ], - [ - "DSP_ACOUT21", - "HCLK_DSP_ACIN21" - ], - [ - "DSP_BCOUT4", - "HCLK_DSP_BCIN4" - ], - [ - "DSP_BCOUT13", - "HCLK_DSP_BCIN13" - ], - [ - "DSP_BCOUT10", - "HCLK_DSP_BCIN10" - ], - [ - "DSP_ACOUT29", - "HCLK_DSP_ACIN29" - ], - [ - "DSP_PCOUT42", - "HCLK_DSP_PCIN42" - ], - [ - "DSP_PCOUT23", - "HCLK_DSP_PCIN23" - ], - [ - "DSP_PCOUT26", - "HCLK_DSP_PCIN26" - ], - [ - "DSP_ACOUT8", - "HCLK_DSP_ACIN8" - ], - [ - "DSP_PCOUT25", - "HCLK_DSP_PCIN25" - ], - [ - "DSP_ACOUT5", - "HCLK_DSP_ACIN5" - ], - [ - "DSP_PCOUT10", - "HCLK_DSP_PCIN10" - ], - [ - "DSP_PCOUT5", - "HCLK_DSP_PCIN5" - ], - [ - "DSP_PCOUT32", - "HCLK_DSP_PCIN32" - ], - [ - "DSP_PCOUT0", - "HCLK_DSP_PCIN0" - ], - [ - "DSP_BCOUT3", - "HCLK_DSP_BCIN3" - ], - [ - "DSP_PCOUT16", - "HCLK_DSP_PCIN16" - ], - [ - "DSP_PCOUT34", - "HCLK_DSP_PCIN34" - ], - [ - "DSP_PCOUT12", - "HCLK_DSP_PCIN12" - ], - [ - "DSP_PCOUT22", - "HCLK_DSP_PCIN22" - ], - [ - "DSP_ACOUT25", - "HCLK_DSP_ACIN25" - ], - [ - "DSP_BCOUT1", - "HCLK_DSP_BCIN1" - ], - [ - "DSP_ACOUT2", - "HCLK_DSP_ACIN2" - ], - [ - "DSP_PCOUT30", - "HCLK_DSP_PCIN30" - ], - [ - "DSP_BCOUT7", - "HCLK_DSP_BCIN7" - ], - [ - "DSP_PCOUT17", - "HCLK_DSP_PCIN17" - ], - [ - "DSP_PCOUT7", - "HCLK_DSP_PCIN7" - ], - [ - "DSP_PCOUT2", - "HCLK_DSP_PCIN2" - ], - [ - "DSP_ACOUT3", - "HCLK_DSP_ACIN3" - ], - [ - "DSP_PCOUT35", - "HCLK_DSP_PCIN35" - ], - [ - "DSP_PCOUT47", - "HCLK_DSP_PCIN47" - ], - [ - "DSP_PCOUT14", - "HCLK_DSP_PCIN14" - ], - [ - "DSP_MULTSIGNOUT", - "HCLK_DSP_MULTSIGNIN" - ], - [ - "DSP_ACOUT26", - "HCLK_DSP_ACIN26" - ], - [ - "DSP_PCOUT43", - "HCLK_DSP_PCIN43" - ], - [ - "DSP_ACOUT6", - "HCLK_DSP_ACIN6" - ], - [ - "DSP_ACOUT28", - "HCLK_DSP_ACIN28" - ], - [ - "DSP_PCOUT36", - "HCLK_DSP_PCIN36" - ], - [ - "DSP_ACOUT27", - "HCLK_DSP_ACIN27" - ], - [ - "DSP_PCOUT15", - "HCLK_DSP_PCIN15" - ], - [ - "DSP_PCOUT1", - "HCLK_DSP_PCIN1" - ], - [ - "DSP_ACOUT1", - "HCLK_DSP_ACIN1" - ], - [ - "DSP_PCOUT45", - "HCLK_DSP_PCIN45" - ], - [ - "DSP_PCOUT29", - "HCLK_DSP_PCIN29" - ], - [ - "DSP_ACOUT13", - "HCLK_DSP_ACIN13" - ], - [ - "DSP_ACOUT18", - "HCLK_DSP_ACIN18" - ], - [ - "DSP_PCOUT28", - "HCLK_DSP_PCIN28" - ], - [ - "DSP_PCOUT44", - "HCLK_DSP_PCIN44" - ], - [ - "DSP_ACOUT19", - "HCLK_DSP_ACIN19" - ], - [ - "DSP_PCOUT19", - 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"HCLK_CLB_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK2" - ], - [ - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_CLB_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CLB_PERFCLK1", - "HCLK_INT_PERFCLK1" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_CLB_PERFCLK3", - "HCLK_INT_PERFCLK3" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_CLB_PERFCLK2", - "HCLK_INT_PERFCLK2" - ], - [ - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_CK_BUFRCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_IN3", - "HCLK_CK_IN3" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CLB_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK0" - ], - [ - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_CLB_PERFCLK0", - "HCLK_INT_PERFCLK0" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CLB_CK_IN0", - "HCLK_CK_IN0" - ], - [ - "HCLK_CLB_CK_IN2", - "HCLK_CK_IN2" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CLB_CK_IN7", - "HCLK_CK_IN7" - ], - [ - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK1" - ] - ], - "tile_types": [ - "HCLK_CLB", - "HCLK_L" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "INT_INTERFACE_WW2A2", - "PCIE_WW2A2_3" - ], - [ - "INT_INTERFACE_EE4C2", - "PCIE_EE4C2_3" - ], - [ - "INT_INTERFACE_LH7", - "PCIE_LH7_3" - ], - [ - "INT_INTERFACE_EE4BEG3", - "PCIE_EE4BEG3_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "PCIE_LOGIC_OUTS_B22_L_3" - ], - [ - "INT_INTERFACE_WW4A2", - "PCIE_WW4A2_3" - ], - [ - "INT_INTERFACE_NW2A2", - "PCIE_NW2A2_3" - ], - [ - "INT_INTERFACE_NW4END2", - "PCIE_NW4END2_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT18", - "PCIE_IMUX18_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT36", - "PCIE_IMUX36_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT3", - "PCIE_IMUX3_L_3" - ], - [ - "INT_INTERFACE_BYP1", - "PCIE_BYP1_L_3" - ], - [ - "INT_INTERFACE_WW2A0", - "PCIE_WW2A0_3" - ], - [ - "INT_INTERFACE_BYP5", - "PCIE_BYP5_L_3" - ], - [ - "INT_INTERFACE_SW4END1", - "PCIE_SW4END1_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT0", - "PCIE_IMUX0_L_3" - ], - [ - "INT_INTERFACE_FAN6", - "PCIE_FAN6_L_3" - ], - [ - "INT_INTERFACE_FAN4", - "PCIE_FAN4_L_3" - ], - [ - "INT_INTERFACE_NE2A0", - "PCIE_NE2A0_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "PCIE_LOGIC_OUTS_B11_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT4", - "PCIE_IMUX4_L_3" - ], - [ - "INT_INTERFACE_EE4BEG1", - "PCIE_EE4BEG1_3" - ], - [ - "INT_INTERFACE_SE4C0", - "PCIE_SE4C0_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "PCIE_LOGIC_OUTS_B15_L_3" - ], - [ - "INT_INTERFACE_ER1BEG2", - "PCIE_ER1BEG2_3" - ], - [ - "INT_INTERFACE_EE2A3", - "PCIE_EE2A3_3" - ], - [ - "INT_INTERFACE_EE4C3", - "PCIE_EE4C3_3" - ], - [ - "INT_INTERFACE_BYP6", - "PCIE_BYP6_L_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "PCIE_LOGIC_OUTS_B20_L_3" - ], - [ - "INT_INTERFACE_LH4", - "PCIE_LH4_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT12", - "PCIE_IMUX12_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT29", - "PCIE_IMUX29_L_3" - ], - [ - "INT_INTERFACE_NE4BEG0", - "PCIE_NE4BEG0_3" - ], - [ - "INT_INTERFACE_LH11", - "PCIE_LH11_3" - ], - [ - "INT_INTERFACE_LH2", - "PCIE_LH2_3" - ], - [ - "INT_INTERFACE_NW4A1", - "PCIE_NW4A1_3" - ], - [ - "INT_INTERFACE_BYP0", - "PCIE_BYP0_L_3" - ], - [ - "INT_INTERFACE_WW4A0", - "PCIE_WW4A0_3" - ], - [ - "INT_INTERFACE_NW2A0", - "PCIE_NW2A0_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT44", - "PCIE_IMUX44_L_3" - ], - [ - "INT_INTERFACE_EE2A0", - "PCIE_EE2A0_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT9", - "PCIE_IMUX9_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT25", - "PCIE_IMUX25_L_3" - ], - [ - "INT_INTERFACE_EE4C0", - "PCIE_EE4C0_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT19", - "PCIE_IMUX19_L_3" - ], - [ - "INT_INTERFACE_SE4BEG0", - "PCIE_SE4BEG0_3" - ], - [ - "INT_INTERFACE_NE4C2", - "PCIE_NE4C2_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT35", - "PCIE_IMUX35_L_3" - ], - [ - "INT_INTERFACE_ER1BEG1", - "PCIE_ER1BEG1_3" - ], - [ - "INT_INTERFACE_BYP7", - "PCIE_BYP7_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT26", - "PCIE_IMUX26_L_3" - ], - [ - "INT_INTERFACE_CLK1", - "PCIE_CLK1_L_3" - ], - [ - "INT_INTERFACE_NE2A2", - "PCIE_NE2A2_3" - ], - [ - "INT_INTERFACE_SE4BEG1", - "PCIE_SE4BEG1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "PCIE_LOGIC_OUTS_B0_L_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "PCIE_LOGIC_OUTS_B18_L_3" - ], - [ - "INT_INTERFACE_EE4B1", - "PCIE_EE4B1_3" - ], - [ - "INT_INTERFACE_SE4C1", - "PCIE_SE4C1_3" - ], - [ - "INT_INTERFACE_NE2A1", - "PCIE_NE2A1_3" - ], - [ - "INT_INTERFACE_EE2BEG2", - "PCIE_EE2BEG2_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT32", - "PCIE_IMUX32_L_3" - ], - [ - "INT_INTERFACE_NE4C3", - "PCIE_NE4C3_3" - ], - [ - "INT_INTERFACE_SW2A2", - "PCIE_SW2A2_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT10", - "PCIE_IMUX10_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT27", - "PCIE_IMUX27_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT39", - "PCIE_IMUX39_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT23", - "PCIE_IMUX23_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT43", - "PCIE_IMUX43_L_3" - ], - [ - "INT_INTERFACE_WW4END1", - "PCIE_WW4END1_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT6", - "PCIE_IMUX6_L_3" - ], - [ - "INT_INTERFACE_SW4A2", - "PCIE_SW4A2_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "PCIE_LOGIC_OUTS_B5_L_3" - ], - [ - "INT_INTERFACE_MONITOR_P", - "PCIE_MONITOR_P_3" - ], - [ - "INT_INTERFACE_EE2A1", - "PCIE_EE2A1_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT30", - "PCIE_IMUX30_L_3" - ], - [ - "INT_INTERFACE_WW4END2", - "PCIE_WW4END2_3" - ], - [ - "INT_INTERFACE_ER1BEG3", - "PCIE_ER1BEG3_3" - ], - [ - "INT_INTERFACE_EE4B2", - "PCIE_EE4B2_3" - ], - [ - "INT_INTERFACE_WR1END3", - "PCIE_WR1END3_3" - ], - [ - "INT_INTERFACE_WR1END1", - "PCIE_WR1END1_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT40", - "PCIE_IMUX40_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT38", - "PCIE_IMUX38_L_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "PCIE_LOGIC_OUTS_B10_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT37", - "PCIE_IMUX37_L_3" - ], - [ - "INT_INTERFACE_BYP2", - "PCIE_BYP2_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT2", - "PCIE_IMUX2_L_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "PCIE_LOGIC_OUTS_B1_L_3" - ], - [ - "INT_INTERFACE_EL1BEG1", - "PCIE_EL1BEG1_3" - ], - [ - "INT_INTERFACE_WW2END1", - "PCIE_WW2END1_3" - ], - [ - "INT_INTERFACE_SE2A0", - "PCIE_SE2A0_3" - ], - [ - "INT_INTERFACE_LH12", - "PCIE_LH12_3" - ], - [ - "INT_INTERFACE_WW2A3", - "PCIE_WW2A3_3" - ], - [ - "INT_INTERFACE_EE4A0", - "PCIE_EE4A0_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT20", - "PCIE_IMUX20_L_3" - ], - [ - "INT_INTERFACE_CLK0", - "PCIE_CLK0_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT13", - "PCIE_IMUX13_L_3" - ], - [ - "INT_INTERFACE_WW4C2", - "PCIE_WW4C2_3" - ], - [ - "INT_INTERFACE_SW2A3", - "PCIE_SW2A3_3" - ], - [ - "INT_INTERFACE_FAN1", - "PCIE_FAN1_L_3" - ], - [ - "INT_INTERFACE_WL1END0", - "PCIE_WL1END0_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT14", - "PCIE_IMUX14_L_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "PCIE_LOGIC_OUTS_B17_L_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "PCIE_LOGIC_OUTS_B21_L_3" - ], - [ - "INT_INTERFACE_WW4C0", - "PCIE_WW4C0_3" - ], - [ - "INT_INTERFACE_EE4B3", - "PCIE_EE4B3_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT11", - "PCIE_IMUX11_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT7", - "PCIE_IMUX7_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT17", - "PCIE_IMUX17_L_3" - ], - [ - "INT_INTERFACE_SE4C3", - "PCIE_SE4C3_3" - ], - [ - "INT_INTERFACE_WW4A1", - "PCIE_WW4A1_3" - ], - [ - "INT_INTERFACE_EE4C1", - "PCIE_EE4C1_3" - ], - [ - "INT_INTERFACE_WW4B1", - "PCIE_WW4B1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "PCIE_LOGIC_OUTS_B19_L_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "PCIE_LOGIC_OUTS_B9_L_3" - ], - [ - "INT_INTERFACE_EL1BEG0", - "PCIE_EL1BEG0_3" - ], - [ - "INT_INTERFACE_WR1END2", - "PCIE_WR1END2_3" - ], - [ - "INT_INTERFACE_NE4BEG3", - "PCIE_NE4BEG3_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT24", - "PCIE_IMUX24_L_3" - ], - [ - "INT_INTERFACE_LH3", - "PCIE_LH3_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "PCIE_LOGIC_OUTS_B8_L_3" - ], - [ - "INT_INTERFACE_BYP3", - "PCIE_BYP3_L_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "PCIE_LOGIC_OUTS_B13_L_3" - ], - [ - "INT_INTERFACE_LH5", - "PCIE_LH5_3" - ], - [ - "INT_INTERFACE_FAN2", - "PCIE_FAN2_L_3" - ], - [ - "INT_INTERFACE_NW2A3", - "PCIE_NW2A3_3" - ], - [ - "INT_INTERFACE_FAN0", - "PCIE_FAN0_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT46", - "PCIE_IMUX46_L_3" - ], - [ - "INT_INTERFACE_NW4END0", - "PCIE_NW4END0_3" - ], - [ - "INT_INTERFACE_NW4A2", - "PCIE_NW4A2_3" - ], - [ - "INT_INTERFACE_LH1", - "PCIE_LH1_3" - ], - [ - "INT_INTERFACE_WW2END3", - "PCIE_WW2END3_3" - ], - [ - "INT_INTERFACE_WW4END0", - "PCIE_WW4END0_3" - ], - [ - "INT_INTERFACE_NE4BEG2", - "PCIE_NE4BEG2_3" - ], - [ - "INT_INTERFACE_NE4C0", - "PCIE_NE4C0_3" - ], - [ - "INT_INTERFACE_WW2END0", - "PCIE_WW2END0_3" - ], - [ - "INT_INTERFACE_WW4B2", - "PCIE_WW4B2_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "PCIE_LOGIC_OUTS_B7_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT1", - "PCIE_IMUX1_L_3" - ], - [ - "INT_INTERFACE_WW4C1", - "PCIE_WW4C1_3" - ], - [ - "INT_INTERFACE_EE2BEG1", - "PCIE_EE2BEG1_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "PCIE_LOGIC_OUTS_B12_L_3" - ], - [ - "INT_INTERFACE_SW4A1", - "PCIE_SW4A1_3" - ], - [ - "INT_INTERFACE_MONITOR_N", - "PCIE_MONITOR_N_3" - ], - [ - "INT_INTERFACE_SE4C2", - "PCIE_SE4C2_3" - ], - [ - "INT_INTERFACE_SE2A3", - "PCIE_SE2A3_3" - ], - [ - "INT_INTERFACE_LH10", - "PCIE_LH10_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT33", - "PCIE_IMUX33_L_3" - ], - [ - "INT_INTERFACE_CTRL1", - "PCIE_CTRL1_L_3" - ], - [ - "INT_INTERFACE_CTRL0", - "PCIE_CTRL0_L_3" - ], - [ - "INT_INTERFACE_WW2A1", - "PCIE_WW2A1_3" - ], - [ - "INT_INTERFACE_NW4END3", - "PCIE_NW4END3_3" - ], - [ - "INT_INTERFACE_WW4B0", - "PCIE_WW4B0_3" - ], - [ - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "PCIE_LOGIC_OUTS_B2_L_3" - ], - [ - "INT_INTERFACE_EE2BEG0", - "PCIE_EE2BEG0_3" - ], - [ - "INT_INTERFACE_FAN3", - "PCIE_FAN3_L_3" - ], - [ - "INT_INTERFACE_WL1END2", - "PCIE_WL1END2_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT41", - "PCIE_IMUX41_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT8", - "PCIE_IMUX8_L_3" - ], - [ - "PCIE_INT_INTERFACE_IMUX_L_OUT28", - "PCIE_IMUX28_L_3" - ], - [ - "INT_INTERFACE_SW4A3", - "PCIE_SW4A3_3" - ], - [ - "INT_INTERFACE_SW2A0", - "PCIE_SW2A0_3" - ], - [ - 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"VFRAME_WR1END2" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B23_4", - "VFRAME_LOGIC_OUTS_B23" - ], - [ - "CFG_CENTER_LH8_4", - "VFRAME_LH8" - ], - [ - "CFG_CENTER_BYP4_4", - "VFRAME_BYP4" - ], - [ - "CFG_CENTER_SW4A1_4", - "VFRAME_SW4A1" - ], - [ - "CFG_CENTER_IMUX41_4", - "VFRAME_IMUX41" - ], - [ - "CFG_CENTER_LOGIC_OUTS_B13_4", - "VFRAME_LOGIC_OUTS_B13" - ], - [ - "CFG_CENTER_SW4END0_4", - "VFRAME_SW4END0" - ], - [ - "CFG_CENTER_EE4C2_4", - "VFRAME_EE4C2" - ], - [ - "CFG_CENTER_EL1BEG3_4", - "VFRAME_EL1BEG3" - ], - [ - "CFG_CENTER_WW4B1_4", - "VFRAME_WW4B1" - ], - [ - "CFG_CENTER_CTRL1_4", - "VFRAME_CTRL1" - ], - [ - "CFG_CENTER_IMUX1_4", - "VFRAME_IMUX1" - ], - [ - "CFG_CENTER_SE4BEG2_4", - "VFRAME_SE4BEG2" - ], - [ - "CFG_CENTER_LH7_4", - "VFRAME_LH7" - ], - [ - "CFG_CENTER_EE2BEG1_4", - "VFRAME_EE2BEG1" - ], - [ - "CFG_CENTER_IMUX38_4", - "VFRAME_IMUX38" - ], - [ - "CFG_CENTER_IMUX36_4", - "VFRAME_IMUX36" - ], - [ - "CFG_CENTER_EE4C1_4", - "VFRAME_EE4C1" - ], - [ - "CFG_CENTER_NE4C1_4", - "VFRAME_NE4C1" - ], - [ - "CFG_CENTER_SW2A0_4", - "VFRAME_SW2A0" - ], - [ - "CFG_CENTER_IMUX47_4", - "VFRAME_IMUX47" - ], - [ - "CFG_CENTER_EL1BEG1_4", - "VFRAME_EL1BEG1" - ], - [ - "CFG_CENTER_WW4B0_4", - "VFRAME_WW4B0" - ], - [ - "CFG_CENTER_SW2A2_4", - "VFRAME_SW2A2" - ], - [ - "CFG_CENTER_FAN0_4", - "VFRAME_FAN0" - ], - [ - "CFG_CENTER_FAN6_4", - "VFRAME_FAN6" - ], - [ - "CFG_CENTER_WW4A2_4", - "VFRAME_WW4A2" - ], - [ - "CFG_CENTER_LH5_4", - "VFRAME_LH5" - ], - [ - "CFG_CENTER_IMUX20_4", - "VFRAME_IMUX20" - ], - [ - "CFG_CENTER_WW4END0_4", - "VFRAME_WW4END0" - ], - [ - "CFG_CENTER_SE4BEG3_4", - "VFRAME_SE4BEG3" - ], - [ - "CFG_CENTER_IMUX28_4", - "VFRAME_IMUX28" - ], - [ - "CFG_CENTER_LH6_4", - "VFRAME_LH6" - ] - ], - "tile_types": [ - "CFG_CENTER_MID", - "VFRAME" - ], - "grid_deltas": [ - 1, - 7 - ] - }, - { - "wire_pairs": [ - [ - "BRKH_CLK_R_CK_GCLK8", - "CLK_BUFG_CK_GCLK8" + "CLK_BUFG_CK_GCLK12" ], [ "BRKH_CLK_R_CK_GCLK27", "CLK_BUFG_CK_GCLK27" ], [ - "BRKH_CLK_R_CK_GCLK29", - "CLK_BUFG_CK_GCLK29" + "BRKH_CLK_R_CK_GCLK11", + "CLK_BUFG_CK_GCLK11" ], [ - "BRKH_CLK_R_CK_GCLK2", - "CLK_BUFG_CK_GCLK2" + "BRKH_CLK_R_CK_GCLK4", + "CLK_BUFG_CK_GCLK4" ], [ - "BRKH_CLK_R_CK_GCLK21", - "CLK_BUFG_CK_GCLK21" + "BRKH_CLK_R_CK_GCLK8", + "CLK_BUFG_CK_GCLK8" ], [ - "BRKH_CLK_R_CK_GCLK20", - "CLK_BUFG_CK_GCLK20" + "BRKH_CLK_R_CK_GCLK1", + "CLK_BUFG_CK_GCLK1" ], [ - "BRKH_CLK_R_CK_GCLK18", - "CLK_BUFG_CK_GCLK18" - ], - [ - "BRKH_CLK_R_CK_GCLK25", - "CLK_BUFG_CK_GCLK25" - ], - [ - "BRKH_CLK_R_CK_GCLK24", - "CLK_BUFG_CK_GCLK24" + "BRKH_CLK_R_CK_GCLK15", + "CLK_BUFG_CK_GCLK15" ], [ "BRKH_CLK_R_CK_GCLK16", @@ -433278,36416 +69274,344 @@ "CLK_BUFG_CK_GCLK13" ], [ - "BRKH_CLK_R_CK_GCLK31", - "CLK_BUFG_CK_GCLK31" - ], - [ - "BRKH_CLK_R_CK_GCLK11", - "CLK_BUFG_CK_GCLK11" - ], - [ - "BRKH_CLK_R_CK_GCLK0", - "CLK_BUFG_CK_GCLK0" - ], - [ - "BRKH_CLK_R_CK_GCLK12", - "CLK_BUFG_CK_GCLK12" - ], - [ - "BRKH_CLK_R_CK_GCLK28", - "CLK_BUFG_CK_GCLK28" - ], - [ - "BRKH_CLK_R_CK_GCLK30", - "CLK_BUFG_CK_GCLK30" - ], - [ - "BRKH_CLK_R_CK_GCLK5", - "CLK_BUFG_CK_GCLK5" - ], - [ - "BRKH_CLK_R_CK_GCLK19", - "CLK_BUFG_CK_GCLK19" - ], - [ - "BRKH_CLK_R_CK_GCLK22", - "CLK_BUFG_CK_GCLK22" - ], - [ - "BRKH_CLK_R_CK_GCLK4", - "CLK_BUFG_CK_GCLK4" - ], - [ - "BRKH_CLK_R_CK_GCLK26", - "CLK_BUFG_CK_GCLK26" - ], - [ - "BRKH_CLK_R_CK_GCLK14", - "CLK_BUFG_CK_GCLK14" - ], - [ - "BRKH_CLK_R_CK_GCLK1", - "CLK_BUFG_CK_GCLK1" - ], - [ - "BRKH_CLK_R_CK_GCLK10", - "CLK_BUFG_CK_GCLK10" - ], - [ - "BRKH_CLK_R_CK_GCLK3", - "CLK_BUFG_CK_GCLK3" + "BRKH_CLK_R_CK_GCLK2", + "CLK_BUFG_CK_GCLK2" ], [ "BRKH_CLK_R_CK_GCLK17", "CLK_BUFG_CK_GCLK17" ], [ - "BRKH_CLK_R_CK_GCLK9", - "CLK_BUFG_CK_GCLK9" + "BRKH_CLK_R_CK_GCLK22", + "CLK_BUFG_CK_GCLK22" ], [ "BRKH_CLK_R_CK_GCLK23", "CLK_BUFG_CK_GCLK23" ], [ - "BRKH_CLK_R_CK_GCLK15", - "CLK_BUFG_CK_GCLK15" + "BRKH_CLK_R_CK_GCLK18", + "CLK_BUFG_CK_GCLK18" + ], + [ + "BRKH_CLK_R_CK_GCLK14", + "CLK_BUFG_CK_GCLK14" + ], + [ + "BRKH_CLK_R_CK_GCLK19", + "CLK_BUFG_CK_GCLK19" + ], + [ + "BRKH_CLK_R_CK_GCLK7", + "CLK_BUFG_CK_GCLK7" ], [ "BRKH_CLK_R_CK_GCLK6", "CLK_BUFG_CK_GCLK6" ], [ - "BRKH_CLK_R_CK_GCLK7", - "CLK_BUFG_CK_GCLK7" + "BRKH_CLK_R_CK_GCLK31", + "CLK_BUFG_CK_GCLK31" + ], + [ + "BRKH_CLK_R_CK_GCLK20", + "CLK_BUFG_CK_GCLK20" + ], + [ + "BRKH_CLK_R_CK_GCLK28", + "CLK_BUFG_CK_GCLK28" + ], + [ + "BRKH_CLK_R_CK_GCLK9", + "CLK_BUFG_CK_GCLK9" + ], + [ + "BRKH_CLK_R_CK_GCLK3", + "CLK_BUFG_CK_GCLK3" + ], + [ + "BRKH_CLK_R_CK_GCLK5", + "CLK_BUFG_CK_GCLK5" + ], + [ + "BRKH_CLK_R_CK_GCLK25", + "CLK_BUFG_CK_GCLK25" + ], + [ + "BRKH_CLK_R_CK_GCLK0", + "CLK_BUFG_CK_GCLK0" + ], + [ + "BRKH_CLK_R_CK_GCLK29", + "CLK_BUFG_CK_GCLK29" + ], + [ + "BRKH_CLK_R_CK_GCLK24", + "CLK_BUFG_CK_GCLK24" + ], + [ + "BRKH_CLK_R_CK_GCLK30", + "CLK_BUFG_CK_GCLK30" + ], + [ + "BRKH_CLK_R_CK_GCLK26", + "CLK_BUFG_CK_GCLK26" + ], + [ + "BRKH_CLK_R_CK_GCLK10", + "CLK_BUFG_CK_GCLK10" ] - ], - "tile_types": [ - "BRKH_CLK", - "CLK_BUFG_TOP_R" - ], - "grid_deltas": [ - 0, - -1 ] }, { - "wire_pairs": [ - [ - "CLK_PMV_EE4C3_4", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_PMV_IMUX5_4", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_NW2A2_4", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_PMV_IMUX39_4", - "INT_INTERFACE_IMUX39" - ], - [ - "CLK_PMV_IMUX24_4", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_PMV_WW4B0_4", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_PMV_LH9_4", - "INT_INTERFACE_LH9" - ], - [ - "CLK_PMV_IMUX29_4", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_PMV_IMUX14_4", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_PMV_ER1BEG1_4", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_PMV_SW4A0_4", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_PMV_WR1END1_4", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_PMV_EL1BEG0_4", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_PMV_NE4C1_4", - "INT_INTERFACE_NE4C1" - ], - [ - "CLK_PMV_NE4C2_4", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_PMV_IMUX4_4", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_PMV_IMUX9_4", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_PMV_SE4BEG3_4", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_LH8_4", - "INT_INTERFACE_LH8" - ], - [ - "CLK_PMV_EE4B0_4", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_PMV_EE4A1_4", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_PMV_WW2END3_4", - "INT_INTERFACE_WW2END3" - ], - [ - "CLK_PMV_WL1END1_4", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_PMV_IMUX43_4", - "INT_INTERFACE_IMUX43" - ], - [ - "CLK_PMV_WW4B2_4", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_PMV_IMUX27_4", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_PMV_WW2A2_4", - "INT_INTERFACE_WW2A2" - ], - [ - "CLK_PMV_WW4C2_4", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_PMV_IMUX38_4", - "INT_INTERFACE_IMUX38" - ], - [ - "CLK_PMV_EE4A3_4", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_EE4B2_4", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_BYP3_4", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_PMV_NW4A3_4", - "INT_INTERFACE_NW4A3" - ], - [ - "CLK_PMV_FAN7_4", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_PMV_EE4A2_4", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_CLK0_4", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_PMV_EL1BEG2_4", - "INT_INTERFACE_EL1BEG2" - ], - [ - "CLK_PMV_IMUX33_4", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_IMUX32_4", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_PMV_IMUX34_4", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_PMV_ER1BEG0_4", - "INT_INTERFACE_ER1BEG0" - ], - [ - "CLK_PMV_SW4A3_4", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_PMV_NW2A3_4", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_PMV_IMUX21_4", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_PMV_EE2BEG2_4", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_PMV_IMUX2_4", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_IMUX7_4", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_PMV_IMUX35_4", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_PMV_IMUX44_4", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_PMV_SW2A3_4", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_PMV_SE4BEG1_4", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_PMV_ER1BEG2_4", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_PMV_WW4A1_4", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_PMV_EE2A3_4", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_PMV_SW4END1_4", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_PMV_LH1_4", - "INT_INTERFACE_LH1" - ], - [ - "CLK_PMV_IMUX46_4", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_PMV_FAN0_4", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_SW2A0_4", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_PMV_WW2END1_4", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_PMV_WW4C3_4", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_FAN4_4", - "INT_INTERFACE_FAN4" - ], - [ - "CLK_PMV_EE2BEG1_4", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_IMUX11_4", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_PMV_IMUX30_4", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_PMV_IMUX36_4", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_PMV_BYP4_4", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_PMV_IMUX6_4", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_PMV_WL1END2_4", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_PMV_WW2A3_4", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_PMV_SW4END3_4", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_PMV_IMUX45_4", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_NE2A2_4", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_PMV_WW4C0_4", - "INT_INTERFACE_WW4C0" - ], - [ - "CLK_PMV_SW4END0_4", - "INT_INTERFACE_SW4END0" - ], - [ - "CLK_PMV_IMUX31_4", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_PMV_IMUX13_4", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_SE4C1_4", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_PMV_IMUX23_4", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_PMV_SE4C0_4", - "INT_INTERFACE_SE4C0" - ], - [ - "CLK_PMV_WW4END1_4", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_WW4A2_4", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_SE4BEG2_4", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_PMV_EE4C1_4", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_PMV_NE4BEG2_4", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_PMV_WR1END0_4", - "INT_INTERFACE_WR1END0" - ], - [ - "CLK_PMV_EE2A0_4", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_PMV_FAN5_4", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_BYP1_4", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_WW4B3_4", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_PMV_EE4B3_4", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_IMUX10_4", - "INT_INTERFACE_IMUX10" - ], - [ - "CLK_PMV_SE4C2_4", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_PMV_LH7_4", - "INT_INTERFACE_LH7" - ], - [ - "CLK_PMV_IMUX40_4", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_PMV_IMUX15_4", - "INT_INTERFACE_IMUX15" - ], - [ - "CLK_PMV_NE4BEG1_4", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_PMV_WL1END0_4", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_PMV_LH11_4", - "INT_INTERFACE_LH11" - ], - [ - "CLK_PMV_SE4BEG0_4", - "INT_INTERFACE_SE4BEG0" - ], - [ - "CLK_PMV_FAN3_4", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_EE2A1_4", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_EE4B1_4", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_BYP5_4", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_SE2A2_4", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_IMUX19_4", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_PMV_IMUX20_4", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_IMUX28_4", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_PMV_LH2_4", - "INT_INTERFACE_LH2" - ], - [ - "CLK_PMV_NW4END0_4", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_NW4END2_4", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_EE4C2_4", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_PMV_BYP7_4", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_SE2A1_4", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_EE4BEG2_4", - "INT_INTERFACE_EE4BEG2" - ], - [ - "CLK_PMV_BYP2_4", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_PMV_MONITOR_N_4", - "INT_INTERFACE_MONITOR_N" - ], - [ - "CLK_PMV_EL1BEG1_4", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_LH6_4", - "INT_INTERFACE_LH6" - ], - [ - "CLK_PMV_LH3_4", - "INT_INTERFACE_LH3" - ], - [ - "CLK_PMV_SW2A1_4", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_PMV_NE4BEG3_4", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_CTRL0_4", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_PMV_EE4A0_4", - "INT_INTERFACE_EE4A0" - ], - [ - "CLK_PMV_EE2BEG0_4", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_IMUX8_4", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_PMV_IMUX18_4", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_PMV_WW2END2_4", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_PMV_WW4B1_4", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_PMV_IMUX3_4", - "INT_INTERFACE_IMUX3" - ], - [ - "CLK_PMV_NE4C3_4", - "INT_INTERFACE_NE4C3" - ], - [ - "CLK_PMV_SE4C3_4", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_PMV_NW4A0_4", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_WW4END0_4", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_PMV_IMUX47_4", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_FAN6_4", - "INT_INTERFACE_FAN6" - ], - [ - "CLK_PMV_EE4BEG1_4", - "INT_INTERFACE_EE4BEG1" - ], - [ - "CLK_PMV_IMUX1_4", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_PMV_NW4A1_4", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_PMV_LH12_4", - "INT_INTERFACE_LH12" - ], - [ - "CLK_PMV_IMUX26_4", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_PMV_EE2A2_4", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_PMV_IMUX22_4", - "INT_INTERFACE_IMUX22" - ], - [ - "CLK_PMV_NW4END3_4", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_PMV_SE2A0_4", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_PMV_NW4END1_4", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_PMV_IMUX41_4", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_PMV_FAN1_4", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_NW2A1_4", - "INT_INTERFACE_NW2A1" - ], - [ - "CLK_PMV_NW4A2_4", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_PMV_MONITOR_P_4", - "INT_INTERFACE_MONITOR_P" - ], - [ - "CLK_PMV_CLK1_4", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_WW4A3_4", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_PMV_WW4END3_4", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_PMV_SW2A2_4", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_PMV_WW2END0_4", - "INT_INTERFACE_WW2END0" - ], - [ - "CLK_PMV_IMUX12_4", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_IMUX16_4", - "INT_INTERFACE_IMUX16" - ], - [ - "CLK_PMV_NW2A0_4", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_PMV_IMUX0_4", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_PMV_WW4C1_4", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_PMV_SW4END2_4", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_PMV_BYP6_4", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_PMV_SW4A1_4", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_PMV_SE2A3_4", - "INT_INTERFACE_SE2A3" - ], - [ - "CLK_PMV_IMUX42_4", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_PMV_WW2A0_4", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_LH4_4", - "INT_INTERFACE_LH4" - ], - [ - "CLK_PMV_NE2A3_4", - "INT_INTERFACE_NE2A3" - ], - [ - "CLK_PMV_EL1BEG3_4", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_PMV_NE2A0_4", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_WR1END2_4", - "INT_INTERFACE_WR1END2" - ], - [ - "CLK_PMV_EE4BEG0_4", - "INT_INTERFACE_EE4BEG0" - ], - [ - "CLK_PMV_WW4A0_4", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_PMV_LH10_4", - "INT_INTERFACE_LH10" - ], - [ - "CLK_PMV_NE2A1_4", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_PMV_IMUX17_4", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_BYP0_4", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_PMV_NE4BEG0_4", - "INT_INTERFACE_NE4BEG0" - ], - [ - "CLK_PMV_NE4C0_4", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_PMV_WW4END2_4", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_PMV_IMUX25_4", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_PMV_WW2A1_4", - "INT_INTERFACE_WW2A1" - ], - [ - "CLK_PMV_IMUX37_4", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_PMV_ER1BEG3_4", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_PMV_EE4BEG3_4", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_PMV_CTRL1_4", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_PMV_EE4C0_4", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_WR1END3_4", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_PMV_SW4A2_4", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_FAN2_4", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_PMV_EE2BEG3_4", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_PMV_LH5_4", - "INT_INTERFACE_LH5" - ], - [ - "CLK_PMV_WL1END3_4", - "INT_INTERFACE_WL1END3" - ] - ], - "tile_types": [ - "CLK_PMV", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -4 - ] - }, - { - "wire_pairs": [ - [ - "DSP_SW4END2_1", - "VBRK_SW4END2" - ], - [ - "DSP_SW2A3_1", - "VBRK_SW2A3" - ], - [ - "DSP_NE4BEG2_1", - "VBRK_NE4BEG2" - ], - [ - "DSP_MONITOR_P_1", - "VBRK_MONITOR_P" - ], - [ - "DSP_WW2END0_1", - "VBRK_WW2END0" - ], - [ - "DSP_NW2A2_1", - "VBRK_NW2A2" - ], - [ - "DSP_SW4A0_1", - "VBRK_SW4A0" - ], - [ - "DSP_WW2END1_1", - "VBRK_WW2END1" - ], - [ - "DSP_WR1END1_1", - "VBRK_WR1END1" - ], - [ - "DSP_SE4BEG0_1", - "VBRK_SE4BEG0" - ], - [ - "DSP_LH11_1", - "VBRK_LH11" - ], - [ - "DSP_SW4END3_1", - "VBRK_SW4END3" - ], - [ - "DSP_EE4B0_1", - "VBRK_EE4B0" - ], - [ - "DSP_NW4A0_1", - "VBRK_NW4A0" - ], - [ - "DSP_LH2_1", - "VBRK_LH2" - ], - [ - "DSP_LH3_1", - "VBRK_LH3" - ], - [ - "DSP_EE4BEG0_1", - "VBRK_EE4BEG0" - ], - [ - "DSP_LH9_1", - "VBRK_LH9" - ], - [ - "DSP_WW2END3_1", - "VBRK_WW2END3" - ], - [ - "DSP_ER1BEG3_1", - "VBRK_ER1BEG3" - ], - [ - "DSP_NW2A0_1", - "VBRK_NW2A0" - ], - [ - "DSP_WW2A3_1", - "VBRK_WW2A3" - ], - [ - "DSP_SE2A2_1", - "VBRK_SE2A2" - ], - [ - "DSP_EE4C0_1", - "VBRK_EE4C0" - ], - [ - "DSP_LH6_1", - "VBRK_LH6" - ], - [ - "DSP_NW4END2_1", - "VBRK_NW4END2" - ], - [ - "DSP_WW4END2_1", - "VBRK_WW4END2" - ], - [ - "DSP_WR1END2_1", - "VBRK_WR1END2" - ], - [ - "DSP_EE4A3_1", - "VBRK_EE4A3" - ], - [ - "DSP_NE4BEG0_1", - "VBRK_NE4BEG0" - ], - [ - "DSP_SE2A3_1", - "VBRK_SE2A3" - ], - [ - "DSP_SE4C3_1", - "VBRK_SE4C3" - ], - [ - "DSP_WW4B2_1", - "VBRK_WW4B2" - ], - [ - "DSP_WL1END2_1", - "VBRK_WL1END2" - ], - [ - "DSP_NE4C3_1", - "VBRK_NE4C3" - ], - [ - "DSP_SE4C1_1", - "VBRK_SE4C1" - ], - [ - "DSP_EE4A1_1", - "VBRK_EE4A1" - ], - [ - "DSP_EE4C2_1", - "VBRK_EE4C2" - ], - [ - "DSP_LH5_1", - "VBRK_LH5" - ], - [ - "DSP_WW4C3_1", - "VBRK_WW4C3" - ], - [ - "DSP_NW4A1_1", - "VBRK_NW4A1" - ], - [ - "DSP_LH8_1", - "VBRK_LH8" - ], - [ - "DSP_SE2A0_1", - "VBRK_SE2A0" - ], - [ - "DSP_WW4END0_1", - "VBRK_WW4END0" - ], - [ - "DSP_NW4A3_1", - "VBRK_NW4A3" - ], - [ - "DSP_NE2A1_1", - "VBRK_NE2A1" - ], - [ - "DSP_SE4C0_1", - "VBRK_SE4C0" - ], - [ - "DSP_EL1BEG3_1", - "VBRK_EL1BEG3" - ], - [ - "DSP_WW2A1_1", - "VBRK_WW2A1" - ], - [ - "DSP_SW4A2_1", - "VBRK_SW4A2" - ], - [ - "DSP_SE4BEG1_1", - "VBRK_SE4BEG1" - ], - [ - "DSP_ER1BEG0_1", - "VBRK_ER1BEG0" - ], - [ - "DSP_LH12_1", - "VBRK_LH12" - ], - [ - "DSP_WW4B3_1", - "VBRK_WW4B3" - ], - [ - "DSP_EE4BEG3_1", - "VBRK_EE4BEG3" - ], - [ - "DSP_NW2A1_1", - "VBRK_NW2A1" - ], - [ - "DSP_WW2A2_1", - "VBRK_WW2A2" - ], - [ - "DSP_ER1BEG1_1", - "VBRK_ER1BEG1" - ], - [ - "DSP_EE4BEG2_1", - "VBRK_EE4BEG2" - ], - [ - "DSP_LH4_1", - "VBRK_LH4" - ], - [ - "DSP_EE2A2_1", - "VBRK_EE2A2" - ], - [ - "DSP_NE4C2_1", - "VBRK_NE4C2" - ], - [ - "DSP_WL1END0_1", - "VBRK_WL1END0" - ], - [ - "DSP_EE4B2_1", - "VBRK_EE4B2" - ], - [ - "DSP_NW4END3_1", - "VBRK_NW4END3" - ], - [ - "DSP_MONITOR_N_1", - "VBRK_MONITOR_N" - ], - [ - "DSP_SW4A1_1", - "VBRK_SW4A1" - ], - [ - "DSP_EE4A2_1", - "VBRK_EE4A2" - ], - [ - "DSP_WW4A1_1", - "VBRK_WW4A1" - ], - [ - "DSP_WW4END1_1", - "VBRK_WW4END1" - ], - [ - "DSP_EE4B3_1", - "VBRK_EE4B3" - ], - [ - "DSP_WW4B1_1", - "VBRK_WW4B1" - ], - [ - "DSP_WW4C0_1", - "VBRK_WW4C0" - ], - [ - "DSP_SW2A2_1", - "VBRK_SW2A2" - ], - [ - "DSP_WW4END3_1", - "VBRK_WW4END3" - ], - [ - "DSP_WW4B0_1", - "VBRK_WW4B0" - ], - [ - "DSP_EE2BEG1_1", - "VBRK_EE2BEG1" - ], - [ - "DSP_EL1BEG0_1", - "VBRK_EL1BEG0" - ], - [ - "DSP_NW4END1_1", - "VBRK_NW4END1" - ], - [ - "DSP_LH7_1", - "VBRK_LH7" - ], - [ - "DSP_EE4A0_1", - "VBRK_EE4A0" - ], - [ - "DSP_NE2A0_1", - "VBRK_NE2A0" - ], - [ - "DSP_EE2A3_1", - "VBRK_EE2A3" - ], - [ - "DSP_EE2BEG2_1", - "VBRK_EE2BEG2" - ], - [ - "DSP_NW4END0_1", - "VBRK_NW4END0" - ], - [ - "DSP_SW4END0_1", - "VBRK_SW4END0" - ], - [ - "DSP_EE4C1_1", - "VBRK_EE4C1" - ], - [ - "DSP_EE4C3_1", - "VBRK_EE4C3" - ], - [ - "DSP_EE2A0_1", - "VBRK_EE2A0" - ], - [ - "DSP_SE2A1_1", - "VBRK_SE2A1" - ], - [ - "DSP_EE2BEG0_1", - "VBRK_EE2BEG0" - ], - [ - "DSP_SW2A1_1", - "VBRK_SW2A1" - ], - [ - "DSP_EE4BEG1_1", - "VBRK_EE4BEG1" - ], - [ - "DSP_WW4A0_1", - "VBRK_WW4A0" - ], - [ - "DSP_SW4END1_1", - "VBRK_SW4END1" - ], - [ - "DSP_EL1BEG1_1", - "VBRK_EL1BEG1" - ], - [ - "DSP_SW4A3_1", - "VBRK_SW4A3" - ], - [ - "DSP_WW4A3_1", - "VBRK_WW4A3" - ], - [ - "DSP_NE4BEG1_1", - "VBRK_NE4BEG1" - ], - [ - "DSP_WL1END3_1", - "VBRK_WL1END3" - ], - [ - "DSP_WR1END3_1", - "VBRK_WR1END3" - ], - [ - "DSP_SE4C2_1", - "VBRK_SE4C2" - ], - [ - "DSP_SE4BEG3_1", - "VBRK_SE4BEG3" - ], - [ - "DSP_WW4C1_1", - "VBRK_WW4C1" - ], - [ - "DSP_WR1END0_1", - "VBRK_WR1END0" - ], - [ - "DSP_LH1_1", - "VBRK_LH1" - ], - [ - "DSP_EL1BEG2_1", - "VBRK_EL1BEG2" - ], - [ - "DSP_NE4BEG3_1", - "VBRK_NE4BEG3" - ], - [ - "DSP_WW4A2_1", - "VBRK_WW4A2" - ], - [ - "DSP_NE2A3_1", - "VBRK_NE2A3" - ], - [ - "DSP_NE4C0_1", - "VBRK_NE4C0" - ], - [ - "DSP_NE2A2_1", - "VBRK_NE2A2" - ], - [ - "DSP_NE4C1_1", - "VBRK_NE4C1" - ], - [ - "DSP_EE2BEG3_1", - "VBRK_EE2BEG3" - ], - [ - "DSP_SW2A0_1", - "VBRK_SW2A0" - ], - [ - "DSP_ER1BEG2_1", - "VBRK_ER1BEG2" - ], - [ - "DSP_WW4C2_1", - "VBRK_WW4C2" - ], - [ - "DSP_EE2A1_1", - "VBRK_EE2A1" - ], - [ - "DSP_WL1END1_1", - "VBRK_WL1END1" - ], - [ - "DSP_WW2A0_1", - "VBRK_WW2A0" - ], - [ - "DSP_LH10_1", - "VBRK_LH10" - ], - [ - "DSP_EE4B1_1", - "VBRK_EE4B1" - ], - [ - "DSP_NW2A3_1", - "VBRK_NW2A3" - ], - [ - "DSP_WW2END2_1", - "VBRK_WW2END2" - ], - [ - "DSP_NW4A2_1", - "VBRK_NW4A2" - ], - [ - "DSP_SE4BEG2_1", - "VBRK_SE4BEG2" - ] - ], - "tile_types": [ - "DSP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -1 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CK_BUFHCLK9" - ], - [ - "HCLK_CLB_CK_IN12", - "HCLK_CK_IN12" - ], - [ - "HCLK_CLB_CK_IN8", - "HCLK_CK_IN8" - ], - [ - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK8" - ], - [ - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK2" - ], - [ - "HCLK_CLB_CK_IN9", - "HCLK_CK_IN9" - ], - [ - "HCLK_CLB_CK_IN11", - "HCLK_CK_IN11" - ], - [ - "HCLK_CLB_CK_IN6", - "HCLK_CK_IN6" - ], - [ - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK10" - ], - [ - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK6" - ], - [ - "HCLK_CLB_CK_IN4", - "HCLK_CK_IN4" - ], - [ - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK3" - ], - [ - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK7" - ], - [ - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK11" - ], - [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK0" - ], - [ - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK1" - ], - [ - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK5" - ], - [ - "HCLK_CLB_CK_IN13", - "HCLK_CK_IN13" - ], - [ - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK4" - ], - [ - "HCLK_CLB_CK_IN5", - "HCLK_CK_IN5" - ], - [ - "HCLK_CLB_CK_IN10", - "HCLK_CK_IN10" - ], - [ - "HCLK_CLB_CK_IN7", - "HCLK_CK_IN7" - ] - ], - "tile_types": [ - "HCLK_CLB", - "HCLK_L_BOT_UTURN" - ], - "grid_deltas": [ - 1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK20" - ], - [ - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK0" - ], - [ - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK11" - ], - [ - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK31" - ], - [ - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_R_CK_GCLK9" - ], - [ - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK24" - ], - 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"CMT_FIFO_L_CLK0_11", - "INT_INTERFACE_CLK0" - ], - [ - "CMT_FIFO_L_IMUX29_11", - "INT_INTERFACE_IMUX29" - ], - [ - "CMT_FIFO_L_IMUX20_11", - "INT_INTERFACE_IMUX20" - ], - [ - "CMT_FIFO_L_IMUX25_11", - "INT_INTERFACE_IMUX25" - ], - [ - "CMT_FIFO_WW4B2_11", - "INT_INTERFACE_WW4B2" - ], - [ - "CMT_FIFO_L_BYP3_11", - "INT_INTERFACE_BYP3" - ], - [ - "CMT_FIFO_EL1BEG0_11", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS21_11", - "INT_INTERFACE_LOGIC_OUTS_B21" - ], - [ - "CMT_FIFO_ER1BEG1_11", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CMT_FIFO_WR1END1_11", - "INT_INTERFACE_WR1END1" - ], - [ - "CMT_FIFO_SW2A2_11", - "INT_INTERFACE_SW2A2" - ], - [ - "CMT_FIFO_SE2A1_11", - "INT_INTERFACE_SE2A1" - ], - [ - "CMT_FIFO_NW4END3_11", - "INT_INTERFACE_NW4END3" - ], - [ - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV" - ], - [ - "CMT_FIFO_SW4A1_11", - "INT_INTERFACE_SW4A1" - ], - [ - "CMT_FIFO_SW4END0_11", - "INT_INTERFACE_SW4END0" - ], - [ - "CMT_FIFO_EE4A2_11", - "INT_INTERFACE_EE4A2" - ], - [ - "CMT_FIFO_L_IMUX47_11", - "INT_INTERFACE_IMUX47" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS5_11", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CMT_FIFO_WW2END0_11", - "INT_INTERFACE_WW2END0" - ], - [ - "CMT_FIFO_L_LOGIC_OUTS4_11", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CMT_FIFO_NE4BEG1_11", - "INT_INTERFACE_NE4BEG1" - ] - ], - "tile_types": [ - "CMT_FIFO_R", - "INT_INTERFACE_R" - ], - "grid_deltas": [ - -1, - -5 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_LH7_0", - "VBRK_LH7" - ], - [ - "CLK_HROW_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_MONITOR_N_0", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_LH12_0", - "VBRK_LH12" - ], - [ - "CLK_HROW_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_LH9_0", - "VBRK_LH9" - ], - [ - "CLK_HROW_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_LH6_0", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_LH2_0", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE4C3_0", - "VBRK_EE4C3" - ], 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"VBRK_WW4END2" - ], - [ - "CLK_HROW_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_HROW_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH5_0", - "VBRK_LH5" - ], - [ - "CLK_HROW_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_LH1_0", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_LH11_0", - "VBRK_LH11" - ], - [ - "CLK_HROW_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_MONITOR_P_0", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_LH8_0", - "VBRK_LH8" - ], - [ - "CLK_HROW_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4A2_0", - "VBRK_EE4A2" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - 4 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_TERM_PERFCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_TERM_CK_BUFHCLK2" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_TERM_CK_BUFHCLK4" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_TERM_CK_BUFHCLK8" - ], - [ - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_TERM_CCIO1" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_TERM_PERFCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_TERM_CK_BUFHCLK7" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_TERM_CK_BUFHCLK5" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_TERM_CK_BUFRCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_TERM_CK_BUFHCLK10" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_TERM_CK_BUFHCLK1" - ], - [ - "HCLK_INT_INTERFACE_CCIO0", - "HCLK_TERM_CCIO0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_TERM_CK_BUFRCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_TERM_CK_BUFHCLK6" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_TERM_CK_BUFHCLK3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_TERM_CK_BUFRCLK0" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_TERM_CK_BUFRCLK2" - ], - [ - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_TERM_CCIO3" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_TERM_CK_BUFHCLK0" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_TERM_PERFCLK3" - ], - [ - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_TERM_CCIO2" - ], - [ - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_TERM_PERFCLK1" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_TERM_CK_BUFHCLK11" - ], - [ - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_TERM_CK_BUFHCLK9" - ] - ], - "tile_types": [ - "HCLK_INT_INTERFACE", - "HCLK_TERM" - ], - "grid_deltas": [ - -1, - 0 - ] - }, - { - "wire_pairs": [ - [ - "HCLK_IOI_RCLK2IO0", - "IOI_RCLK_FORIO0" - ], - [ - "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_IDELAYCTRL_UPPULSEOUT" - ], - [ - "HCLK_IOI_LEAF_GCLK_TOP4", - "IOI_LEAF_GCLK4" - ], - [ - "HCLK_IOI_LEAF_GCLK_TOP5", - "IOI_LEAF_GCLK5" - ], - [ - "HCLK_IOI_RCLK_IMUX0", - "IOI_IMUX_RC0" - ], - [ - "HCLK_IOI_LEAF_GCLK_TOP2", - "IOI_LEAF_GCLK2" - ], - [ - "HCLK_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1" - ], - [ - "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_DNPULSEOUT" - ], - [ - "HCLK_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE1" - ], - [ - "HCLK_IOI_IOCLK1", - "IOI_IOCLK1" - ], - [ - "HCLK_IOI_LEAF_GCLK_TOP1", - "IOI_LEAF_GCLK1" - ], - [ - "HCLK_IOI_I2IOCLK_TOP0", - "LIOI_I2GCLK_TOP0" - ], - [ - "HCLK_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE0" - ], - [ - "HCLK_IOI_RCLK2IO3", - "IOI_RCLK_FORIO3" - ], - [ - "HCLK_IOI_LEAF_GCLK_TOP3", - "IOI_LEAF_GCLK3" - ], - [ - "HCLK_IOI_IOCLK0", - "IOI_IOCLK0" - ], - [ - "HCLK_IOI_RCLK2IO2", - "IOI_RCLK_FORIO2" - ], - [ - "HCLK_IOI_IOCLK2", - "IOI_IOCLK2" - ], - [ - "HCLK_IOI_LEAF_GCLK_TOP0", - "IOI_LEAF_GCLK0" - ], - [ - "HCLK_IOI_RCLK_IMUX1", - "IOI_IMUX_RC1" - ], - [ - "HCLK_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0" - ], - [ - "HCLK_IOI_IOCLK3", - "IOI_IOCLK3" - ], - [ - "HCLK_IOI_I2IOCLK_TOP1", - "LIOI_I2GCLK_TOP1" - ], - [ - "HCLK_IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_RST" - ], - [ - "HCLK_IOI_RCLK2IO1", - "IOI_RCLK_FORIO1" - ] - ], - "tile_types": [ - "HCLK_IOI3", - "LIOI3" - ], - "grid_deltas": [ - 0, - -1 - ] - }, - { - "wire_pairs": [ - [ - "CMT_TOP_SW4END2_2", - "VBRK_SW4END2" - ], - [ - "CMT_TOP_WL1END0_2", - "VBRK_WL1END0" - ], - [ - "CMT_TOP_SW4END1_2", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_EE2A0_2", - "VBRK_EE2A0" - ], - [ - "CMT_TOP_WW4B2_2", - "VBRK_WW4B2" - ], - [ - "CMT_TOP_LH1_2", - "VBRK_LH1" - ], - [ - "CMT_TOP_EE4BEG1_2", - "VBRK_EE4BEG1" - ], - [ - "CMT_TOP_NE2A0_2", - "VBRK_NE2A0" - ], - [ - "CMT_TOP_EE4C0_2", - "VBRK_EE4C0" - ], - [ - "CMT_TOP_SW2A0_2", - "VBRK_SW2A0" - ], - [ - "CMT_TOP_ER1BEG3_2", - "VBRK_ER1BEG3" - ], - [ - "CMT_TOP_EE4A3_2", - "VBRK_EE4A3" - ], - [ - "CMT_TOP_SW2A3_2", - "VBRK_SW2A3" - ], - [ - "CMT_TOP_WW2A3_2", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_MONITOR_P_2", - "VBRK_MONITOR_P" - ], - [ - "CMT_TOP_EE4B0_2", - "VBRK_EE4B0" - ], - [ - "CMT_TOP_NE4C1_2", - "VBRK_NE4C1" - ], - [ - "CMT_TOP_EE4BEG2_2", - "VBRK_EE4BEG2" - ], - [ - "CMT_TOP_EE2A1_2", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_EE4A2_2", - "VBRK_EE4A2" - ], - [ - "CMT_TOP_SE2A3_2", - "VBRK_SE2A3" - ], - [ - "CMT_TOP_EE2BEG2_2", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_ER1BEG0_2", - "VBRK_ER1BEG0" - ], - [ - "CMT_TOP_NW4A2_2", - "VBRK_NW4A2" - ], - [ - "CMT_TOP_EE4BEG3_2", - "VBRK_EE4BEG3" - ], - [ - "CMT_TOP_NW2A1_2", - "VBRK_NW2A1" - ], - [ - "CMT_TOP_WL1END3_2", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_WR1END1_2", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_LH3_2", - "VBRK_LH3" - ], - [ - "CMT_TOP_NW4END2_2", - "VBRK_NW4END2" - ], - [ - "CMT_TOP_NW4END0_2", - "VBRK_NW4END0" - ], - [ - "CMT_TOP_NW2A3_2", - "VBRK_NW2A3" - ], - [ - "CMT_TOP_EE4A1_2", - "VBRK_EE4A1" - ], - [ - "CMT_TOP_EE2A2_2", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_EL1BEG2_2", - "VBRK_EL1BEG2" - ], - [ - "CMT_TOP_NW2A0_2", - "VBRK_NW2A0" - ], - [ - "CMT_TOP_SE4BEG3_2", - "VBRK_SE4BEG3" - ], - [ - "CMT_TOP_WW2A0_2", - "VBRK_WW2A0" - ], - [ - "CMT_TOP_WW4A1_2", - "VBRK_WW4A1" - ], - [ - "CMT_TOP_ER1BEG2_2", - "VBRK_ER1BEG2" - ], - [ - "CMT_TOP_MONITOR_N_2", - "VBRK_MONITOR_N" - ], - [ - "CMT_TOP_WR1END3_2", - "VBRK_WR1END3" - ], - [ - "CMT_TOP_WW4C1_2", - "VBRK_WW4C1" - ], - [ - "CMT_TOP_EL1BEG3_2", - "VBRK_EL1BEG3" - ], - [ - "CMT_TOP_LH5_2", - "VBRK_LH5" - ], - [ - "CMT_TOP_SE2A1_2", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_NE4BEG0_2", - "VBRK_NE4BEG0" - ], - [ - "CMT_TOP_NW4END3_2", - "VBRK_NW4END3" - ], - [ - "CMT_TOP_LH4_2", - "VBRK_LH4" - ], - [ - "CMT_TOP_WW2END3_2", - "VBRK_WW2END3" - ], - [ - "CMT_TOP_NW4END1_2", - "VBRK_NW4END1" - ], - [ - "CMT_TOP_EL1BEG1_2", - "VBRK_EL1BEG1" - ], - [ - "CMT_TOP_WW4B1_2", - "VBRK_WW4B1" - ], - [ - "CMT_TOP_WW2END0_2", - "VBRK_WW2END0" - ], - [ - "CMT_TOP_NE4C0_2", - "VBRK_NE4C0" - ], - [ - "CMT_TOP_EL1BEG0_2", - "VBRK_EL1BEG0" - ], - [ - "CMT_TOP_WR1END0_2", - "VBRK_WR1END0" - ], - [ - "CMT_TOP_WW4B3_2", - "VBRK_WW4B3" - ], - [ - "CMT_TOP_NW4A3_2", - "VBRK_NW4A3" - ], - [ - "CMT_TOP_EE2BEG0_2", - "VBRK_EE2BEG0" - ], - [ - "CMT_TOP_ER1BEG1_2", - "VBRK_ER1BEG1" - ], - [ - "CMT_TOP_SE2A2_2", - "VBRK_SE2A2" - ], - [ - "CMT_TOP_EE4B2_2", - "VBRK_EE4B2" - ], - [ - "CMT_TOP_WW4END1_2", - "VBRK_WW4END1" - ], - [ - "CMT_TOP_SE4C2_2", - "VBRK_SE4C2" - ], - [ - "CMT_TOP_SE4C0_2", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_NE4BEG1_2", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_EE4C3_2", - "VBRK_EE4C3" - ], - [ - "CMT_TOP_NW4A0_2", - "VBRK_NW4A0" - ], - [ - "CMT_TOP_WL1END1_2", - "VBRK_WL1END1" - ], - [ - "CMT_TOP_EE4B3_2", - "VBRK_EE4B3" - ], - [ - "CMT_TOP_WW4A0_2", - "VBRK_WW4A0" - ], - [ - "CMT_TOP_WW2END2_2", - "VBRK_WW2END2" - ], - [ - "CMT_TOP_NE2A2_2", - "VBRK_NE2A2" - ], - [ - "CMT_TOP_SE4C1_2", - "VBRK_SE4C1" - ], - [ - "CMT_TOP_WW2A2_2", - "VBRK_WW2A2" - ], - [ - "CMT_TOP_NW4A1_2", - "VBRK_NW4A1" - ], - [ - "CMT_TOP_SW4A1_2", - "VBRK_SW4A1" - ], - [ - "CMT_TOP_WW4A2_2", - "VBRK_WW4A2" - ], - [ - "CMT_TOP_NE4BEG2_2", - "VBRK_NE4BEG2" - ], - [ - "CMT_TOP_LH8_2", - "VBRK_LH8" - ], - [ - "CMT_TOP_LH10_2", - "VBRK_LH10" - ], - [ - "CMT_TOP_WR1END2_2", - "VBRK_WR1END2" - ], - [ - "CMT_TOP_WW4C3_2", - "VBRK_WW4C3" - ], - [ - "CMT_TOP_SW2A1_2", - "VBRK_SW2A1" - ], - [ - "CMT_TOP_SW4END3_2", - "VBRK_SW4END3" - ], - [ - "CMT_TOP_LH6_2", - "VBRK_LH6" - ], - [ - "CMT_TOP_WW2A1_2", - "VBRK_WW2A1" - ], - [ - "CMT_TOP_LH12_2", - "VBRK_LH12" - ], - [ - "CMT_TOP_SE4C3_2", - "VBRK_SE4C3" - ], - [ - "CMT_TOP_WL1END2_2", - "VBRK_WL1END2" - ], - [ - "CMT_TOP_EE4B1_2", - "VBRK_EE4B1" - ], - [ - "CMT_TOP_WW4C0_2", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_LH9_2", - "VBRK_LH9" - ], - [ - "CMT_TOP_NE4C3_2", - "VBRK_NE4C3" - ], - [ - "CMT_TOP_EE2BEG3_2", - "VBRK_EE2BEG3" - ], - [ - "CMT_TOP_EE4BEG0_2", - "VBRK_EE4BEG0" - ], - [ - "CMT_TOP_SE4BEG0_2", - "VBRK_SE4BEG0" - ], - [ - "CMT_TOP_SW4A0_2", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_NE2A1_2", - "VBRK_NE2A1" - ], - [ - "CMT_TOP_WW2END1_2", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_LH2_2", - "VBRK_LH2" - ], - [ - "CMT_TOP_WW4END2_2", - "VBRK_WW4END2" - ], - [ - "CMT_TOP_SW4A2_2", - "VBRK_SW4A2" - ], - [ - "CMT_TOP_EE2BEG1_2", - "VBRK_EE2BEG1" - ], - [ - "CMT_TOP_EE2A3_2", - "VBRK_EE2A3" - ], - [ - "CMT_TOP_LH11_2", - "VBRK_LH11" - ], - [ - "CMT_TOP_EE4C2_2", - "VBRK_EE4C2" - ], - [ - "CMT_TOP_SW2A2_2", - "VBRK_SW2A2" - ], - [ - "CMT_TOP_SW4A3_2", - "VBRK_SW4A3" - ], - [ - "CMT_TOP_WW4A3_2", - "VBRK_WW4A3" - ], - [ - "CMT_TOP_WW4B0_2", - "VBRK_WW4B0" - ], - [ - "CMT_TOP_EE4C1_2", - "VBRK_EE4C1" - ], - [ - "CMT_TOP_NE2A3_2", - "VBRK_NE2A3" - ], - [ - "CMT_TOP_SW4END0_2", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_NW2A2_2", - "VBRK_NW2A2" - ], - [ - "CMT_TOP_WW4END0_2", - "VBRK_WW4END0" - ], - [ - "CMT_TOP_SE4BEG1_2", - "VBRK_SE4BEG1" - ], - [ - "CMT_TOP_SE2A0_2", - "VBRK_SE2A0" - ], - [ - "CMT_TOP_NE4BEG3_2", - "VBRK_NE4BEG3" - ], - [ - "CMT_TOP_WW4C2_2", - "VBRK_WW4C2" - ], - [ - "CMT_TOP_LH7_2", - "VBRK_LH7" - ], - [ - "CMT_TOP_WW4END3_2", - "VBRK_WW4END3" - ], - [ - "CMT_TOP_NE4C2_2", - "VBRK_NE4C2" - ], - [ - "CMT_TOP_EE4A0_2", - "VBRK_EE4A0" - ], - [ - "CMT_TOP_SE4BEG2_2", - "VBRK_SE4BEG2" - ] - ], - "tile_types": [ - "CMT_TOP_L_UPPER_T", - "VBRK" - ], - "grid_deltas": [ - -1, - 3 - ] - }, - { - "wire_pairs": [ - [ - "BRAM_WW4B3_4", - "CLBLM_WW4B3" - ], - [ - "BRAM_SE4C2_4", - "CLBLM_SE4C2" - ], - [ - "BRAM_EL1BEG1_4", - "CLBLM_EL1BEG1" - ], - [ - "BRAM_EE4C3_4", - "CLBLM_EE4C3" - ], - [ - "BRAM_NW2A0_4", - "CLBLM_NW2A0" - ], - [ - "BRAM_LH10_4", - "CLBLM_LH10" - ], - [ - "BRAM_SE4BEG0_4", - "CLBLM_SE4BEG0" - ], - [ - "BRAM_SW2A3_4", - "CLBLM_SW2A3" - ], - [ - "BRAM_NW4END1_4", - "CLBLM_NW4END1" - ], - [ - "BRAM_EE2A1_4", - "CLBLM_EE2A1" - ], - [ - "BRAM_NE4BEG2_4", - "CLBLM_NE4BEG2" - ], - [ - "BRAM_SE4BEG3_4", - "CLBLM_SE4BEG3" - ], - [ - "BRAM_WW4A2_4", - "CLBLM_WW4A2" - ], - [ - "BRAM_SE4C1_4", - "CLBLM_SE4C1" - ], - [ - "BRAM_WW4END3_4", - "CLBLM_WW4END3" - ], - [ - "BRAM_NE4C1_4", - "CLBLM_NE4C1" - ], - [ - "BRAM_NE4C2_4", - "CLBLM_NE4C2" - ], - [ - "BRAM_WR1END2_4", - "CLBLM_WR1END2" - ], - [ - "BRAM_NW4A3_4", - "CLBLM_NW4A3" - ], - [ - "BRAM_EE2A0_4", - "CLBLM_EE2A0" - ], - [ - "BRAM_SE4BEG2_4", - "CLBLM_SE4BEG2" - ], - [ - "BRAM_SE4BEG1_4", - "CLBLM_SE4BEG1" - ], - [ - "BRAM_LH2_4", - "CLBLM_LH2" - ], - [ - "BRAM_NW4END3_4", - "CLBLM_NW4END3" - ], - [ - "BRAM_WW4END0_4", - "CLBLM_WW4END0" - ], - [ - "BRAM_SW4A0_4", - "CLBLM_SW4A0" - ], - [ - "BRAM_LH8_4", - "CLBLM_LH8" - ], - [ - "BRAM_WR1END1_4", - "CLBLM_WR1END1" - ], - [ - "BRAM_EE4BEG1_4", - "CLBLM_EE4BEG1" - ], - [ - "BRAM_WW2A1_4", - "CLBLM_WW2A1" - ], - [ - "BRAM_LH4_4", - "CLBLM_LH4" - ], - [ - "BRAM_WL1END0_4", - "CLBLM_WL1END0" - ], - [ - "BRAM_WL1END2_4", - "CLBLM_WL1END2" - ], - [ - "BRAM_WL1END1_4", - "CLBLM_WL1END1" - ], - [ - "BRAM_LH7_4", - "CLBLM_LH7" - ], - [ - "BRAM_SE4C0_4", - "CLBLM_SE4C0" - ], - [ - "BRAM_EE2A3_4", - "CLBLM_EE2A3" - ], - [ - "BRAM_EE4B0_4", - "CLBLM_EE4B0" - ], - [ - "BRAM_SW4END0_4", - "CLBLM_SW4END0" - ], - [ - "BRAM_EE2BEG1_4", - "CLBLM_EE2BEG1" - ], - [ - "BRAM_SE2A0_4", - "CLBLM_SE2A0" - ], - [ - "BRAM_SW4END2_4", - "CLBLM_SW4END2" - ], - [ - "BRAM_ER1BEG3_4", - "CLBLM_ER1BEG3" - ], - [ - "BRAM_EL1BEG0_4", - "CLBLM_EL1BEG0" - ], - [ - "BRAM_WW4B2_4", - "CLBLM_WW4B2" - ], - [ - "BRAM_EE4BEG3_4", - "CLBLM_EE4BEG3" - ], - [ - "BRAM_NW2A1_4", - "CLBLM_NW2A1" - ], - [ - "BRAM_EE4C2_4", - "CLBLM_EE4C2" - ], - [ - "BRAM_WW4A1_4", - "CLBLM_WW4A1" - ], - [ - "BRAM_EL1BEG2_4", - "CLBLM_EL1BEG2" - ], - [ - "BRAM_EE2BEG0_4", - "CLBLM_EE2BEG0" - ], - [ - "BRAM_NE4C0_4", - "CLBLM_NE4C0" - ], - [ - "BRAM_LH11_4", - "CLBLM_LH11" - ], - [ - "BRAM_SW2A2_4", - "CLBLM_SW2A2" - ], - [ - "BRAM_SE4C3_4", - "CLBLM_SE4C3" - ], - [ - "BRAM_EE4BEG0_4", - "CLBLM_EE4BEG0" - ], - [ - "BRAM_WW4C0_4", - "CLBLM_WW4C0" - ], - [ - "BRAM_MONITOR_N_4", - "CLBLM_MONITOR_N" - ], - [ - "BRAM_SW2A0_4", - "CLBLM_SW2A0" - ], - [ - "BRAM_NW4END0_4", - "CLBLM_NW4END0" - ], - [ - "BRAM_ER1BEG2_4", - "CLBLM_ER1BEG2" - ], - [ - "BRAM_LH3_4", - "CLBLM_LH3" - ], - [ - "BRAM_SE2A2_4", - "CLBLM_SE2A2" - ], - [ - "BRAM_NW4A1_4", - "CLBLM_NW4A1" - ], - [ - "BRAM_NW2A2_4", - "CLBLM_NW2A2" - ], - [ - "BRAM_LH1_4", - "CLBLM_LH1" - ], - [ - "BRAM_SW4END3_4", - "CLBLM_SW4END3" - ], - [ - "BRAM_NE4BEG0_4", - "CLBLM_NE4BEG0" - ], - [ - "BRAM_NE4BEG1_4", - "CLBLM_NE4BEG1" - ], - [ - "BRAM_NW2A3_4", - "CLBLM_NW2A3" - ], - [ - "BRAM_NW4A2_4", - "CLBLM_NW4A2" - ], - [ - "BRAM_WR1END3_4", - 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"CLK_HROW_EE2BEG0_7", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_NE4BEG1_7", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_LH1_7", - "VBRK_LH1" - ], - [ - "CLK_HROW_SW2A2_7", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_SE2A1_7", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EE4B2_7", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_NE4C0_7", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_SE4BEG1_7", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_NW2A1_7", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_SE2A2_7", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EL1BEG1_7", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_WW4A2_7", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_LH10_7", - "VBRK_LH10" - ], - [ - "CLK_HROW_NW4A0_7", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_EE4C2_7", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_NW4END2_7", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_WW2END2_7", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_WR1END2_7", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_ER1BEG0_7", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_WW2A3_7", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_SE2A3_7", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_EE4A0_7", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_SW4END3_7", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_NE2A0_7", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_SW4A1_7", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_ER1BEG3_7", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_WL1END3_7", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_EE2BEG2_7", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_ER1BEG1_7", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WR1END1_7", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_WW2A1_7", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW4A1_7", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NW2A2_7", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4A2_7", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_WW4C1_7", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_WW4A0_7", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_NW2A3_7", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE2A1_7", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_SE4C3_7", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_WW4C2_7", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_LH12_7", - "VBRK_LH12" - ], - [ - "CLK_HROW_SE4C0_7", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_EE4BEG2_7", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_LH9_7", - "VBRK_LH9" - ], - [ - "CLK_HROW_EE4A1_7", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_EE4C0_7", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_LH8_7", - "VBRK_LH8" - ], - [ - "CLK_HROW_EE2BEG3_7", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_SW2A3_7", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_NE4BEG0_7", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_SW4END0_7", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_LH4_7", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE2A2_7", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_WW4C0_7", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_SE4C2_7", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_NE4BEG3_7", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_SE4BEG2_7", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_EE2A3_7", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_SW4A0_7", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_EE4B1_7", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_WW4END2_7", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_NW4END0_7", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_WW4C3_7", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_WL1END1_7", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE4BEG3_7", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_EE4C3_7", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_WW2A0_7", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_EE4A3_7", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW2A2_7", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_NE4BEG2_7", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NW4END1_7", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_EE4A2_7", - "VBRK_EE4A2" - ], - [ - "CLK_HROW_WW4A3_7", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WW4END3_7", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_EE4B0_7", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_WW4B3_7", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_EE4BEG0_7", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_LH11_7", - "VBRK_LH11" - ], - [ - "CLK_HROW_WW2END0_7", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_NW4A1_7", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_EE4C1_7", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_LH6_7", - "VBRK_LH6" - ], - [ - "CLK_HROW_LH5_7", - "VBRK_LH5" - ], - [ - "CLK_HROW_EE2A0_7", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_SE4BEG3_7", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_SW4END2_7", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_LH3_7", - "VBRK_LH3" - ], - [ - "CLK_HROW_NW4A2_7", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_SW2A0_7", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_WW4B2_7", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EE4B3_7", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_NW4A3_7", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_WR1END0_7", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_WL1END2_7", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_WW4B0_7", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_WW2END3_7", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_NE4C1_7", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_EL1BEG0_7", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_NE4C2_7", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_WW4END1_7", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_LH7_7", - "VBRK_LH7" - ], - [ - "CLK_HROW_NW2A0_7", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WL1END0_7", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_LH2_7", - "VBRK_LH2" - ], - [ - "CLK_HROW_WW4B1_7", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_SE4C1_7", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_NE4C3_7", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_SW4A3_7", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_SW4END1_7", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_ER1BEG2_7", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_NE2A3_7", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_SE2A0_7", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_EE2BEG1_7", - "VBRK_EE2BEG1" - ] - ], - "tile_types": [ - "CLK_HROW_TOP_R", - "VBRK" - ], - "grid_deltas": [ - 1, - -4 - ] - }, - { - "wire_pairs": [ - [ - "CLK_PMV_NW4END1_1", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_PMV_IMUX5_1", - "INT_INTERFACE_IMUX5" - ], - [ - "CLK_PMV_IMUX13_1", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_PMV_LH7_1", - "INT_INTERFACE_LH7" - ], - [ - "CLK_PMV_NW2A0_1", - "INT_INTERFACE_NW2A0" - ], - [ - "CLK_PMV_BYP5_1", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_PMV_SE4BEG2_1", - "INT_INTERFACE_SE4BEG2" - ], - [ - "CLK_PMV_EE2BEG0_1", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_PMV_EE4B1_1", - "INT_INTERFACE_EE4B1" - ], - [ - "CLK_PMV_IMUX42_1", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_PMV_EE2BEG1_1", - "INT_INTERFACE_EE2BEG1" - ], - [ - "CLK_PMV_SW4A0_1", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_PMV_EE4C0_1", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_PMV_WW4END1_1", - "INT_INTERFACE_WW4END1" - ], - [ - "CLK_PMV_IMUX32_1", - "INT_INTERFACE_IMUX32" - ], - [ - "CLK_PMV_WW2END2_1", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_PMV_EE2A3_1", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_PMV_WW4END3_1", - "INT_INTERFACE_WW4END3" - ], - [ - "CLK_PMV_EE4C2_1", - "INT_INTERFACE_EE4C2" - ], - [ - "CLK_PMV_SW4END2_1", - "INT_INTERFACE_SW4END2" - ], - [ - "CLK_PMV_SW2A0_1", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_PMV_BYP1_1", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_PMV_SE2A1_1", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_PMV_EE4B0_1", - "INT_INTERFACE_EE4B0" - ], - [ - "CLK_PMV_IMUX33_1", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_PMV_BYP0_1", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_PMV_WL1END2_1", - "INT_INTERFACE_WL1END2" - ], - [ - "CLK_PMV_FAN3_1", - "INT_INTERFACE_FAN3" - ], - [ - "CLK_PMV_WW4B2_1", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_PMV_IMUX19_1", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_PMV_ER1BEG2_1", - "INT_INTERFACE_ER1BEG2" - ], - [ - "CLK_PMV_IMUX45_1", - "INT_INTERFACE_IMUX45" - ], - [ - "CLK_PMV_NW4A0_1", - "INT_INTERFACE_NW4A0" - ], - [ - "CLK_PMV_SW2A1_1", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_PMV_SE2A0_1", - "INT_INTERFACE_SE2A0" - ], - [ - "CLK_PMV_WW4C3_1", - "INT_INTERFACE_WW4C3" - ], - [ - "CLK_PMV_NE4BEG3_1", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_PMV_LH6_1", - "INT_INTERFACE_LH6" - ], - [ - "CLK_PMV_NE4BEG2_1", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_PMV_EL1BEG0_1", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_PMV_FAN7_1", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_PMV_WW4A0_1", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_PMV_CLK1_1", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_PMV_CLK0_1", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_PMV_FAN0_1", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_PMV_WW4A2_1", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_PMV_EE2BEG2_1", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_PMV_SE4BEG3_1", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_PMV_EE4B2_1", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_PMV_WW4END0_1", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_PMV_EE2A2_1", - "INT_INTERFACE_EE2A2" - ], - [ - "CLK_PMV_SW4A3_1", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_PMV_WW2A0_1", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_PMV_EE4B3_1", - "INT_INTERFACE_EE4B3" - ], - [ - "CLK_PMV_BYP6_1", - "INT_INTERFACE_BYP6" - ], - [ - "CLK_PMV_EL1BEG1_1", - "INT_INTERFACE_EL1BEG1" - ], - [ - "CLK_PMV_SW4A2_1", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_PMV_NW2A3_1", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_PMV_NW4END0_1", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_PMV_NE2A2_1", - "INT_INTERFACE_NE2A2" - ], - [ - "CLK_PMV_IMUX35_1", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_PMV_CTRL0_1", - "INT_INTERFACE_CTRL0" - ], - [ - "CLK_PMV_SE4C2_1", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_PMV_SW2A2_1", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_PMV_EE4A2_1", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_PMV_EE4BEG3_1", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_PMV_WR1END1_1", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_PMV_LH9_1", - "INT_INTERFACE_LH9" - ], - [ - "CLK_PMV_LH2_1", - "INT_INTERFACE_LH2" - ], - [ - "CLK_PMV_ER1BEG1_1", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_PMV_IMUX40_1", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_PMV_SE2A2_1", - "INT_INTERFACE_SE2A2" - ], - [ - "CLK_PMV_IMUX17_1", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_PMV_IMUX4_1", - "INT_INTERFACE_IMUX4" - ], - [ - "CLK_PMV_EE4A1_1", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_PMV_LH4_1", - "INT_INTERFACE_LH4" - ], - [ - "CLK_PMV_IMUX0_1", - "INT_INTERFACE_IMUX0" - ], - [ - "CLK_PMV_NW4A1_1", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_PMV_EE4A3_1", - "INT_INTERFACE_EE4A3" - ], - [ - "CLK_PMV_IMUX41_1", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_PMV_BYP2_1", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_PMV_NW4END2_1", - "INT_INTERFACE_NW4END2" - ], - [ - "CLK_PMV_NE2A0_1", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_PMV_IMUX8_1", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_PMV_EE2A1_1", - "INT_INTERFACE_EE2A1" - ], - [ - "CLK_PMV_LH8_1", - "INT_INTERFACE_LH8" - ], - [ - "CLK_PMV_SW4A1_1", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_PMV_IMUX2_1", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_PMV_FAN1_1", - "INT_INTERFACE_FAN1" - ], - [ - "CLK_PMV_IMUX20_1", - "INT_INTERFACE_IMUX20" - ], - [ - "CLK_PMV_IMUX26_1", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_PMV_WW2END1_1", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_PMV_IMUX37_1", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_PMV_IMUX46_1", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_PMV_IMUX47_1", - "INT_INTERFACE_IMUX47" - ], - [ - "CLK_PMV_FAN5_1", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_PMV_BYP7_1", - "INT_INTERFACE_BYP7" - ], - [ - "CLK_PMV_EL1BEG3_1", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_PMV_IMUX12_1", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_PMV_WW2A3_1", - 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"CMT_TOP_SW4A0_3", - "VBRK_SW4A0" - ], - [ - "CMT_TOP_LH8_3", - "VBRK_LH8" - ], - [ - "CMT_TOP_WW4C0_3", - "VBRK_WW4C0" - ], - [ - "CMT_TOP_WW2END1_3", - "VBRK_WW2END1" - ], - [ - "CMT_TOP_NE4BEG1_3", - "VBRK_NE4BEG1" - ], - [ - "CMT_TOP_EE2A0_3", + "CMT_TOP_EE2A0_10", "VBRK_EE2A0" ], [ - "CMT_TOP_SE4C0_3", - "VBRK_SE4C0" - ], - [ - "CMT_TOP_EE2BEG2_3", - "VBRK_EE2BEG2" - ], - [ - "CMT_TOP_EE2A2_3", - "VBRK_EE2A2" - ], - [ - "CMT_TOP_WR1END1_3", - "VBRK_WR1END1" - ], - [ - "CMT_TOP_EE2A1_3", - "VBRK_EE2A1" - ], - [ - "CMT_TOP_LH1_3", - "VBRK_LH1" - ], - [ - "CMT_TOP_SW4END0_3", - "VBRK_SW4END0" - ], - [ - "CMT_TOP_SE2A1_3", - "VBRK_SE2A1" - ], - [ - "CMT_TOP_SW4END1_3", - "VBRK_SW4END1" - ], - [ - "CMT_TOP_LH2_3", - "VBRK_LH2" - ], - [ - "CMT_TOP_WW2A3_3", - "VBRK_WW2A3" - ], - [ - "CMT_TOP_WL1END3_3", - "VBRK_WL1END3" - ], - [ - "CMT_TOP_LH5_3", - "VBRK_LH5" - ] - ], - "tile_types": [ - "CMT_TOP_R_LOWER_T", - "VBRK" - ], - "grid_deltas": [ - 1, - -2 - ] - }, - { - "wire_pairs": [ - [ - "CLK_HROW_ER1BEG1_0", - "VBRK_ER1BEG1" - ], - [ - "CLK_HROW_WW4B1_0", - "VBRK_WW4B1" - ], - [ - "CLK_HROW_NW4END0_0", - "VBRK_NW4END0" - ], - [ - "CLK_HROW_LH7_0", - "VBRK_LH7" - ], - [ - "CLK_HROW_NE2A3_0", - "VBRK_NE2A3" - ], - [ - "CLK_HROW_EE4C1_0", - "VBRK_EE4C1" - ], - [ - "CLK_HROW_NE4BEG1_0", - "VBRK_NE4BEG1" - ], - [ - "CLK_HROW_SE4C0_0", - "VBRK_SE4C0" - ], - [ - "CLK_HROW_NW4A3_0", - "VBRK_NW4A3" - ], - [ - "CLK_HROW_SE4C1_0", - "VBRK_SE4C1" - ], - [ - "CLK_HROW_SE2A2_0", - "VBRK_SE2A2" - ], - [ - "CLK_HROW_EE4A1_0", - "VBRK_EE4A1" - ], - [ - "CLK_HROW_EE4BEG0_0", - "VBRK_EE4BEG0" - ], - [ - "CLK_HROW_SE4BEG0_0", - "VBRK_SE4BEG0" - ], - [ - "CLK_HROW_WW2END0_0", - "VBRK_WW2END0" - ], - [ - "CLK_HROW_WW4A3_0", - "VBRK_WW4A3" - ], - [ - "CLK_HROW_WW4A1_0", - "VBRK_WW4A1" - ], - [ - "CLK_HROW_NE4BEG3_0", - "VBRK_NE4BEG3" - ], - [ - "CLK_HROW_EE2BEG2_0", - "VBRK_EE2BEG2" - ], - [ - "CLK_HROW_MONITOR_N_0", - "VBRK_MONITOR_N" - ], - [ - "CLK_HROW_WW4A2_0", - "VBRK_WW4A2" - ], - [ - "CLK_HROW_NE4C0_0", - "VBRK_NE4C0" - ], - [ - "CLK_HROW_LH12_0", - "VBRK_LH12" - ], - [ - "CLK_HROW_NE4C1_0", - "VBRK_NE4C1" - ], - [ - "CLK_HROW_LH9_0", - "VBRK_LH9" - ], - [ - "CLK_HROW_SW2A0_0", - "VBRK_SW2A0" - ], - [ - "CLK_HROW_LH6_0", - "VBRK_LH6" - ], - [ - "CLK_HROW_WW4A0_0", - "VBRK_WW4A0" - ], - [ - "CLK_HROW_EE2A3_0", - "VBRK_EE2A3" - ], - [ - "CLK_HROW_EE4A0_0", - "VBRK_EE4A0" - ], - [ - "CLK_HROW_EE4BEG1_0", - "VBRK_EE4BEG1" - ], - [ - "CLK_HROW_NE2A0_0", - "VBRK_NE2A0" - ], - [ - "CLK_HROW_WL1END0_0", - "VBRK_WL1END0" - ], - [ - "CLK_HROW_LH2_0", - "VBRK_LH2" - ], - [ - "CLK_HROW_NW4A2_0", - "VBRK_NW4A2" - ], - [ - "CLK_HROW_EL1BEG1_0", - "VBRK_EL1BEG1" - ], - [ - "CLK_HROW_WW4B2_0", - "VBRK_WW4B2" - ], - [ - "CLK_HROW_EE4BEG3_0", - "VBRK_EE4BEG3" - ], - [ - "CLK_HROW_WR1END3_0", - "VBRK_WR1END3" - ], - [ - "CLK_HROW_NW4END3_0", - "VBRK_NW4END3" - ], - [ - "CLK_HROW_SW4END0_0", - "VBRK_SW4END0" - ], - [ - "CLK_HROW_WW2A0_0", - "VBRK_WW2A0" - ], - [ - "CLK_HROW_SE4BEG1_0", - "VBRK_SE4BEG1" - ], - [ - "CLK_HROW_SE4BEG3_0", - "VBRK_SE4BEG3" - ], - [ - "CLK_HROW_WW2END1_0", - "VBRK_WW2END1" - ], - [ - "CLK_HROW_WL1END1_0", - "VBRK_WL1END1" - ], - [ - "CLK_HROW_EE2A2_0", - "VBRK_EE2A2" - ], - [ - "CLK_HROW_NW4A0_0", - "VBRK_NW4A0" - ], - [ - "CLK_HROW_NW2A1_0", - "VBRK_NW2A1" - ], - [ - "CLK_HROW_ER1BEG0_0", - "VBRK_ER1BEG0" - ], - [ - "CLK_HROW_SW4A1_0", - "VBRK_SW4A1" - ], - [ - "CLK_HROW_SE4C3_0", - "VBRK_SE4C3" - ], - [ - "CLK_HROW_EE4C3_0", - "VBRK_EE4C3" - ], - [ - "CLK_HROW_NW4A1_0", - "VBRK_NW4A1" - ], - [ - "CLK_HROW_WW2A2_0", - "VBRK_WW2A2" - ], - [ - "CLK_HROW_WW4END1_0", - "VBRK_WW4END1" - ], - [ - "CLK_HROW_ER1BEG2_0", - "VBRK_ER1BEG2" - ], - [ - "CLK_HROW_EE2BEG0_0", - "VBRK_EE2BEG0" - ], - [ - "CLK_HROW_SE2A0_0", - "VBRK_SE2A0" - ], - [ - "CLK_HROW_WR1END1_0", - "VBRK_WR1END1" - ], - [ - "CLK_HROW_NE4C2_0", - "VBRK_NE4C2" - ], - [ - "CLK_HROW_NE4BEG2_0", - "VBRK_NE4BEG2" - ], - [ - "CLK_HROW_NW4END2_0", - "VBRK_NW4END2" - ], - [ - "CLK_HROW_EE4C0_0", - "VBRK_EE4C0" - ], - [ - "CLK_HROW_EE4BEG2_0", - "VBRK_EE4BEG2" - ], - [ - "CLK_HROW_WL1END2_0", - "VBRK_WL1END2" - ], - [ - "CLK_HROW_WW4END0_0", - "VBRK_WW4END0" - ], - [ - "CLK_HROW_SE4C2_0", - "VBRK_SE4C2" - ], - [ - "CLK_HROW_WW4END3_0", - "VBRK_WW4END3" - ], - [ - "CLK_HROW_SW4A2_0", - "VBRK_SW4A2" - ], - [ - "CLK_HROW_EE4B2_0", - "VBRK_EE4B2" - ], - [ - "CLK_HROW_LH10_0", - "VBRK_LH10" - ], - [ - "CLK_HROW_EE4A3_0", - "VBRK_EE4A3" - ], - [ - "CLK_HROW_WW4END2_0", - "VBRK_WW4END2" - ], - [ - "CLK_HROW_EE2BEG1_0", - "VBRK_EE2BEG1" - ], - [ - "CLK_HROW_WW4C1_0", - "VBRK_WW4C1" - ], - [ - "CLK_HROW_LH3_0", - "VBRK_LH3" - ], - [ - "CLK_HROW_NE2A1_0", - "VBRK_NE2A1" - ], - [ - "CLK_HROW_WR1END2_0", - "VBRK_WR1END2" - ], - [ - "CLK_HROW_SW4A0_0", - "VBRK_SW4A0" - ], - [ - "CLK_HROW_EE4B0_0", - "VBRK_EE4B0" - ], - [ - "CLK_HROW_SW4A3_0", - "VBRK_SW4A3" - ], - [ - "CLK_HROW_SE2A1_0", - "VBRK_SE2A1" - ], - [ - "CLK_HROW_EL1BEG0_0", - "VBRK_EL1BEG0" - ], - [ - "CLK_HROW_WW2A1_0", - "VBRK_WW2A1" - ], - [ - "CLK_HROW_WW2END2_0", - "VBRK_WW2END2" - ], - [ - "CLK_HROW_SW4END2_0", - "VBRK_SW4END2" - ], - [ - "CLK_HROW_SW2A2_0", - "VBRK_SW2A2" - ], - [ - "CLK_HROW_NW2A0_0", - "VBRK_NW2A0" - ], - [ - "CLK_HROW_WL1END3_0", - "VBRK_WL1END3" - ], - [ - "CLK_HROW_NE4C3_0", - "VBRK_NE4C3" - ], - [ - "CLK_HROW_SW2A1_0", - "VBRK_SW2A1" - ], - [ - "CLK_HROW_LH5_0", - "VBRK_LH5" - ], - [ - "CLK_HROW_NW4END1_0", - "VBRK_NW4END1" - ], - [ - "CLK_HROW_LH1_0", - "VBRK_LH1" - ], - [ - "CLK_HROW_EE4C2_0", - "VBRK_EE4C2" - ], - [ - "CLK_HROW_WW4B0_0", - "VBRK_WW4B0" - ], - [ - "CLK_HROW_SW4END3_0", - "VBRK_SW4END3" - ], - [ - "CLK_HROW_NE2A2_0", - "VBRK_NE2A2" - ], - [ - "CLK_HROW_EE2A0_0", - "VBRK_EE2A0" - ], - [ - "CLK_HROW_WW4C0_0", - "VBRK_WW4C0" - ], - [ - "CLK_HROW_EE2A1_0", - "VBRK_EE2A1" - ], - [ - "CLK_HROW_NW2A2_0", - "VBRK_NW2A2" - ], - [ - "CLK_HROW_SW4END1_0", - "VBRK_SW4END1" - ], - [ - "CLK_HROW_EL1BEG2_0", - "VBRK_EL1BEG2" - ], - [ - "CLK_HROW_EE2BEG3_0", - "VBRK_EE2BEG3" - ], - [ - "CLK_HROW_SW2A3_0", - "VBRK_SW2A3" - ], - [ - "CLK_HROW_LH11_0", - "VBRK_LH11" - ], - [ - "CLK_HROW_NE4BEG0_0", - "VBRK_NE4BEG0" - ], - [ - "CLK_HROW_WW4B3_0", - "VBRK_WW4B3" - ], - [ - "CLK_HROW_WW4C2_0", - "VBRK_WW4C2" - ], - [ - "CLK_HROW_WW4C3_0", - "VBRK_WW4C3" - ], - [ - "CLK_HROW_WR1END0_0", - "VBRK_WR1END0" - ], - [ - "CLK_HROW_SE4BEG2_0", - "VBRK_SE4BEG2" - ], - [ - "CLK_HROW_SE2A3_0", - "VBRK_SE2A3" - ], - [ - "CLK_HROW_ER1BEG3_0", - "VBRK_ER1BEG3" - ], - [ - "CLK_HROW_NW2A3_0", - "VBRK_NW2A3" - ], - [ - "CLK_HROW_EE4B1_0", - "VBRK_EE4B1" - ], - [ - "CLK_HROW_EL1BEG3_0", - "VBRK_EL1BEG3" - ], - [ - "CLK_HROW_MONITOR_P_0", - "VBRK_MONITOR_P" - ], - [ - "CLK_HROW_LH8_0", - "VBRK_LH8" - ], - [ - "CLK_HROW_WW2A3_0", - "VBRK_WW2A3" - ], - [ - "CLK_HROW_WW2END3_0", - "VBRK_WW2END3" - ], - [ - "CLK_HROW_EE4B3_0", - "VBRK_EE4B3" - ], - [ - "CLK_HROW_LH4_0", - "VBRK_LH4" - ], - [ - "CLK_HROW_EE4A2_0", - "VBRK_EE4A2" - ] - ], - "tile_types": [ - "CLK_HROW_BOT_R", - "VBRK" - ], - "grid_deltas": [ - 1, - 4 - ] - }, - { - "wire_pairs": [ - [ - "GTPE2_LOGIC_OUTS_B6_6", - "VBRK_EXT_LOGIC_OUTS_B6" - ], - [ - "GTPE2_BYP3_6", - "VBRK_EXT_BYP3" - ], - [ - "GTPE2_IMUX10_6", - "VBRK_EXT_IMUX10" - ], - [ - "GTPE2_IMUX40_6", - "VBRK_EXT_IMUX40" - ], - [ - "GTPE2_CTRL1_6", - "VBRK_EXT_CTRL1" - ], - [ - "GTPE2_IMUX17_6", - "VBRK_EXT_IMUX17" - ], - [ - "GTPE2_IMUX12_6", - "VBRK_EXT_IMUX12" - ], - [ - "GTPE2_IMUX30_6", - "VBRK_EXT_IMUX30" - ], - [ - "GTPE2_LOGIC_OUTS_B4_6", - "VBRK_EXT_LOGIC_OUTS_B4" - ], - [ - "GTPE2_LOGIC_OUTS_B17_6", - "VBRK_EXT_LOGIC_OUTS_B17" - ], - [ - "GTPE2_IMUX33_6", - "VBRK_EXT_IMUX33" - ], - [ - "GTPE2_IMUX20_6", - "VBRK_EXT_IMUX20" - ], - [ - "GTPE2_BYP2_6", - "VBRK_EXT_BYP2" - ], - [ - "GTPE2_IMUX28_6", - "VBRK_EXT_IMUX28" - ], - [ - "GTPE2_IMUX6_6", - "VBRK_EXT_IMUX6" - ], - [ - "GTPE2_IMUX16_6", - "VBRK_EXT_IMUX16" - ], - [ - "GTPE2_IMUX22_6", - "VBRK_EXT_IMUX22" - ], - [ - "GTPE2_IMUX41_6", - "VBRK_EXT_IMUX41" - ], - [ - "GTPE2_IMUX36_6", - "VBRK_EXT_IMUX36" - ], - [ - "GTPE2_IMUX34_6", - "VBRK_EXT_IMUX34" - ], - [ - "GTPE2_LOGIC_OUTS_B23_6", - "VBRK_EXT_LOGIC_OUTS_B23" - ], - [ - "GTPE2_CLK0_6", - "VBRK_EXT_CLK0" - ], - [ - "GTPE2_LOGIC_OUTS_B3_6", - "VBRK_EXT_LOGIC_OUTS_B3" - ], - [ - "GTPE2_IMUX45_6", - "VBRK_EXT_IMUX45" - ], - [ - "GTPE2_LOGIC_OUTS_B13_6", - "VBRK_EXT_LOGIC_OUTS_B13" - ], - [ - "GTPE2_CLK1_6", - "VBRK_EXT_CLK1" - ], - [ - "GTPE2_IMUX32_6", - "VBRK_EXT_IMUX32" - ], - [ - "GTPE2_BYP5_6", - "VBRK_EXT_BYP5" - ], - [ - "GTPE2_IMUX42_6", - "VBRK_EXT_IMUX42" - ], - [ - "GTPE2_IMUX24_6", - "VBRK_EXT_IMUX24" - ], - [ - "GTPE2_FAN0_6", - "VBRK_EXT_FAN0" - ], - [ - "GTPE2_BYP6_6", - "VBRK_EXT_BYP6" - ], - [ - "GTPE2_IMUX29_6", - "VBRK_EXT_IMUX29" - ], - [ - "GTPE2_BYP7_6", - "VBRK_EXT_BYP7" - ], - [ - "GTPE2_IMUX5_6", - "VBRK_EXT_IMUX5" - ], - [ - "GTPE2_FAN4_6", - "VBRK_EXT_FAN4" - ], - [ - "GTPE2_IMUX38_6", - "VBRK_EXT_IMUX38" - ], - [ - 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"INT_INTERFACE_IMUX5" - ], - [ - "CLK_HROW_SW4END1_0", - "INT_INTERFACE_SW4END1" - ], - [ - "CLK_HROW_BYP2_0", - "INT_INTERFACE_BYP2" - ], - [ - "CLK_HROW_FAN2_0", - "INT_INTERFACE_FAN2" - ], - [ - "CLK_HROW_FAN0_0", - "INT_INTERFACE_FAN0" - ], - [ - "CLK_HROW_WW4B2_0", - "INT_INTERFACE_WW4B2" - ], - [ - "CLK_HROW_EE2BEG2_0", - "INT_INTERFACE_EE2BEG2" - ], - [ - "CLK_BUFG_IMUX2_0", - "INT_INTERFACE_IMUX2" - ], - [ - "CLK_HROW_WR1END3_0", - "INT_INTERFACE_WR1END3" - ], - [ - "CLK_BUFG_IMUX27_0", - "INT_INTERFACE_IMUX27" - ], - [ - "CLK_BUFG_IMUX13_0", - "INT_INTERFACE_IMUX13" - ], - [ - "CLK_HROW_WW2A3_0", - "INT_INTERFACE_WW2A3" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B4_0", - "INT_INTERFACE_LOGIC_OUTS_B4" - ], - [ - "CLK_HROW_NE2A0_0", - "INT_INTERFACE_NE2A0" - ], - [ - "CLK_BUFG_IMUX19_0", - "INT_INTERFACE_IMUX19" - ], - [ - "CLK_HROW_NW4END1_0", - "INT_INTERFACE_NW4END1" - ], - [ - "CLK_BUFG_IMUX17_0", - "INT_INTERFACE_IMUX17" - ], - [ - "CLK_HROW_EE4C2_0", - "INT_INTERFACE_EE4C2" - ], - [ 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"INT_INTERFACE_IMUX43" - ], - [ - "CLK_BUFG_IMUX12_0", - "INT_INTERFACE_IMUX12" - ], - [ - "CLK_HROW_SW4A3_0", - "INT_INTERFACE_SW4A3" - ], - [ - "CLK_HROW_NE2A1_0", - "INT_INTERFACE_NE2A1" - ], - [ - "CLK_BUFG_IMUX23_0", - "INT_INTERFACE_IMUX23" - ], - [ - "CLK_HROW_BYP1_0", - "INT_INTERFACE_BYP1" - ], - [ - "CLK_HROW_SE2A1_0", - "INT_INTERFACE_SE2A1" - ], - [ - "CLK_HROW_CLK0_0", - "INT_INTERFACE_CLK0" - ], - [ - "CLK_HROW_SW2A2_0", - "INT_INTERFACE_SW2A2" - ], - [ - "CLK_HROW_WW2END1_0", - "INT_INTERFACE_WW2END1" - ], - [ - "CLK_HROW_WW4B1_0", - "INT_INTERFACE_WW4B1" - ], - [ - "CLK_HROW_WR1END1_0", - "INT_INTERFACE_WR1END1" - ], - [ - "CLK_HROW_WW4A3_0", - "INT_INTERFACE_WW4A3" - ], - [ - "CLK_HROW_WW4A2_0", - "INT_INTERFACE_WW4A2" - ], - [ - "CLK_BUFG_IMUX41_0", - "INT_INTERFACE_IMUX41" - ], - [ - "CLK_HROW_SW4A2_0", - "INT_INTERFACE_SW4A2" - ], - [ - "CLK_HROW_LH11_0", - "INT_INTERFACE_LH11" - ], - [ - "CLK_HROW_EE2BEG0_0", - "INT_INTERFACE_EE2BEG0" - ], - [ - "CLK_HROW_NE2A2_0", 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"INT_INTERFACE_FAN3" - ], - [ - "CLK_HROW_LH12_0", - "INT_INTERFACE_LH12" - ], - [ - "CLK_HROW_WL1END0_0", - "INT_INTERFACE_WL1END0" - ], - [ - "CLK_HROW_SE4C1_0", - "INT_INTERFACE_SE4C1" - ], - [ - "CLK_BUFG_IMUX26_0", - "INT_INTERFACE_IMUX26" - ], - [ - "CLK_HROW_FAN7_0", - "INT_INTERFACE_FAN7" - ], - [ - "CLK_HROW_WL1END1_0", - "INT_INTERFACE_WL1END1" - ], - [ - "CLK_HROW_NW2A2_0", - "INT_INTERFACE_NW2A2" - ], - [ - "CLK_HROW_SE4BEG1_0", - "INT_INTERFACE_SE4BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B7_0", - "INT_INTERFACE_LOGIC_OUTS_B7" - ], - [ - "CLK_HROW_SW2A3_0", - "INT_INTERFACE_SW2A3" - ], - [ - "CLK_HROW_SE4C2_0", - "INT_INTERFACE_SE4C2" - ], - [ - "CLK_BUFG_IMUX18_0", - "INT_INTERFACE_IMUX18" - ], - [ - "CLK_HROW_EE4B2_0", - "INT_INTERFACE_EE4B2" - ], - [ - "CLK_BUFG_IMUX35_0", - "INT_INTERFACE_IMUX35" - ], - [ - "CLK_HROW_WW4A0_0", - "INT_INTERFACE_WW4A0" - ], - [ - "CLK_HROW_EL1BEG3_0", - "INT_INTERFACE_EL1BEG3" - ], - [ - "CLK_HROW_WW4B3_0", - "INT_INTERFACE_WW4B3" - ], - [ - "CLK_HROW_WW2A0_0", - "INT_INTERFACE_WW2A0" - ], - [ - "CLK_HROW_SW2A1_0", - "INT_INTERFACE_SW2A1" - ], - [ - "CLK_HROW_SW4A0_0", - "INT_INTERFACE_SW4A0" - ], - [ - "CLK_HROW_EE4A2_0", - "INT_INTERFACE_EE4A2" - ], - [ - "CLK_HROW_NE4C2_0", - "INT_INTERFACE_NE4C2" - ], - [ - "CLK_HROW_BYP3_0", - "INT_INTERFACE_BYP3" - ], - [ - "CLK_HROW_NE4BEG3_0", - "INT_INTERFACE_NE4BEG3" - ], - [ - "CLK_HROW_EE2A0_0", - "INT_INTERFACE_EE2A0" - ], - [ - "CLK_HROW_CTRL1_0", - "INT_INTERFACE_CTRL1" - ], - [ - "CLK_HROW_BYP0_0", - "INT_INTERFACE_BYP0" - ], - [ - "CLK_BUFG_IMUX29_0", - "INT_INTERFACE_IMUX29" - ], - [ - "CLK_BUFG_IMUX33_0", - "INT_INTERFACE_IMUX33" - ], - [ - "CLK_HROW_SW4A1_0", - "INT_INTERFACE_SW4A1" - ], - [ - "CLK_BUFG_IMUX14_0", - "INT_INTERFACE_IMUX14" - ], - [ - "CLK_HROW_LH10_0", - "INT_INTERFACE_LH10" - ], - [ - "CLK_HROW_EE4C0_0", - "INT_INTERFACE_EE4C0" - ], - [ - "CLK_HROW_ER1BEG3_0", - "INT_INTERFACE_ER1BEG3" - ], - [ - "CLK_HROW_WW2END3_0", - "INT_INTERFACE_WW2END3" - ], - [ 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"INT_INTERFACE_NW4A0" - ], - [ - "CLK_BUFG_IMUX36_0", - "INT_INTERFACE_IMUX36" - ], - [ - "CLK_HROW_EE4A1_0", - "INT_INTERFACE_EE4A1" - ], - [ - "CLK_HROW_SW4END3_0", - "INT_INTERFACE_SW4END3" - ], - [ - "CLK_BUFG_IMUX28_0", - "INT_INTERFACE_IMUX28" - ], - [ - "CLK_BUFG_IMUX25_0", - "INT_INTERFACE_IMUX25" - ], - [ - "CLK_HROW_EE4C3_0", - "INT_INTERFACE_EE4C3" - ], - [ - "CLK_BUFG_IMUX37_0", - "INT_INTERFACE_IMUX37" - ], - [ - "CLK_HROW_NE4BEG1_0", - "INT_INTERFACE_NE4BEG1" - ], - [ - "CLK_HROW_WW4C1_0", - "INT_INTERFACE_WW4C1" - ], - [ - "CLK_HROW_WW4B0_0", - "INT_INTERFACE_WW4B0" - ], - [ - "CLK_HROW_LH2_0", - "INT_INTERFACE_LH2" - ], - [ - "CLK_BUFG_IMUX40_0", - "INT_INTERFACE_IMUX40" - ], - [ - "CLK_HROW_NW4END0_0", - "INT_INTERFACE_NW4END0" - ], - [ - "CLK_HROW_SE4C3_0", - "INT_INTERFACE_SE4C3" - ], - [ - "CLK_HROW_NW4A2_0", - "INT_INTERFACE_NW4A2" - ], - [ - "CLK_HROW_NW4END3_0", - "INT_INTERFACE_NW4END3" - ], - [ - "CLK_BUFG_IMUX21_0", - "INT_INTERFACE_IMUX21" - ], - [ - "CLK_HROW_WW2END2_0", - "INT_INTERFACE_WW2END2" - ], - [ - "CLK_HROW_CLK1_0", - "INT_INTERFACE_CLK1" - ], - [ - "CLK_HROW_WW4A1_0", - "INT_INTERFACE_WW4A1" - ], - [ - "CLK_HROW_EE4BEG3_0", - "INT_INTERFACE_EE4BEG3" - ], - [ - "CLK_BUFG_IMUX42_0", - "INT_INTERFACE_IMUX42" - ], - [ - "CLK_HROW_BYP5_0", - "INT_INTERFACE_BYP5" - ], - [ - "CLK_BUFG_IMUX46_0", - "INT_INTERFACE_IMUX46" - ], - [ - "CLK_HROW_EE2A3_0", - "INT_INTERFACE_EE2A3" - ], - [ - "CLK_BUFG_IMUX7_0", - "INT_INTERFACE_IMUX7" - ], - [ - "CLK_HROW_BYP4_0", - "INT_INTERFACE_BYP4" - ], - [ - "CLK_BUFG_IMUX1_0", - "INT_INTERFACE_IMUX1" - ], - [ - "CLK_HROW_NW2A3_0", - "INT_INTERFACE_NW2A3" - ], - [ - "CLK_BUFG_IMUX30_0", - "INT_INTERFACE_IMUX30" - ], - [ - "CLK_HROW_SE4BEG3_0", - "INT_INTERFACE_SE4BEG3" - ], - [ - "CLK_BUFG_IMUX44_0", - "INT_INTERFACE_IMUX44" - ], - [ - "CLK_BUFG_IMUX11_0", - "INT_INTERFACE_IMUX11" - ], - [ - "CLK_HROW_SW2A0_0", - "INT_INTERFACE_SW2A0" - ], - [ - "CLK_BUFG_IMUX6_0", - "INT_INTERFACE_IMUX6" - ], - [ - "CLK_HROW_LH8_0", - "INT_INTERFACE_LH8" - ], - [ - "CLK_HROW_EE2BEG3_0", - "INT_INTERFACE_EE2BEG3" - ], - [ - "CLK_HROW_FAN5_0", - "INT_INTERFACE_FAN5" - ], - [ - "CLK_BUFG_IMUX31_0", - "INT_INTERFACE_IMUX31" - ], - [ - "CLK_HROW_NE4C0_0", - "INT_INTERFACE_NE4C0" - ], - [ - "CLK_HROW_WW4END2_0", - "INT_INTERFACE_WW4END2" - ], - [ - "CLK_BUFG_IMUX8_0", - "INT_INTERFACE_IMUX8" - ], - [ - "CLK_BUFG_IMUX9_0", - "INT_INTERFACE_IMUX9" - ], - [ - "CLK_HROW_EL1BEG0_0", - "INT_INTERFACE_EL1BEG0" - ], - [ - "CLK_HROW_ER1BEG1_0", - "INT_INTERFACE_ER1BEG1" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B3_0", - "INT_INTERFACE_LOGIC_OUTS_B3" - ], - [ - "CLK_HROW_LH5_0", - "INT_INTERFACE_LH5" - ], - [ - "CLK_BUFG_LOGIC_OUTS_B5_0", - "INT_INTERFACE_LOGIC_OUTS_B5" - ], - [ - "CLK_BUFG_IMUX24_0", - "INT_INTERFACE_IMUX24" - ], - [ - "CLK_BUFG_IMUX34_0", - "INT_INTERFACE_IMUX34" - ], - [ - "CLK_HROW_EE4C1_0", - "INT_INTERFACE_EE4C1" - ], - [ - "CLK_HROW_WW4C2_0", - "INT_INTERFACE_WW4C2" - ], - [ - "CLK_HROW_LH4_0", - "INT_INTERFACE_LH4" - ], - [ - "CLK_HROW_WW4END0_0", - "INT_INTERFACE_WW4END0" - ], - [ - "CLK_HROW_NW4A1_0", - "INT_INTERFACE_NW4A1" - ], - [ - "CLK_HROW_NE4BEG2_0", - "INT_INTERFACE_NE4BEG2" - ], - [ - "CLK_BUFG_IMUX16_0", - "INT_INTERFACE_IMUX16" - ] - ], "tile_types": [ - "CLK_BUFG_TOP_R", + "CLK_HROW_TOP_R", "INT_INTERFACE_R" ], "grid_deltas": [ -1, - 0 + 3 + ], + "wire_pairs": [ + [ + "CLK_HROW_WW2A1_1", + "INT_INTERFACE_WW2A1" + ], + [ + "CLK_HROW_IMUX32_1", + "INT_INTERFACE_IMUX32" + ], + [ + "CLK_HROW_ER1BEG0_1", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_IMUX19_1", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_IMUX29_1", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX34_1", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_NE4BEG3_1", + "INT_INTERFACE_NE4BEG3" + ], + [ + "CLK_HROW_WW2A2_1", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_EE4BEG2_1", + "INT_INTERFACE_EE4BEG2" + ], + [ + "CLK_HROW_WR1END3_1", + "INT_INTERFACE_WR1END3" + ], + [ + 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+ [ + "HCLK_CMT_CK_IN0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_CK_IN6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_IN2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ] + ] + }, + { + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ], + "grid_deltas": [ + 1, + 2 + ], + "wire_pairs": [ + [ + "CLK_HROW_LH2_2", + "VBRK_LH2" + ], + [ + "CLK_HROW_SE2A1_2", + "VBRK_SE2A1" + ], + [ + "CLK_HROW_EE4A2_2", + "VBRK_EE4A2" + ], + [ + "CLK_HROW_EE4A0_2", + "VBRK_EE4A0" + ], + [ + "CLK_HROW_WR1END2_2", + "VBRK_WR1END2" + ], + [ + "CLK_HROW_WW4B2_2", + "VBRK_WW4B2" + ], + [ + "CLK_HROW_WW4B0_2", + "VBRK_WW4B0" + ], + [ + "CLK_HROW_EE4BEG3_2", + "VBRK_EE4BEG3" + ], + [ + "CLK_HROW_WW4B3_2", + "VBRK_WW4B3" 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"VBRK_EE2BEG0" + ], + [ + "CMT_TOP_WW2END0_0", + "VBRK_WW2END0" + ], + [ + "CMT_TOP_SE4C2_0", + "VBRK_SE4C2" + ], + [ + "CMT_TOP_EE4A2_0", + "VBRK_EE4A2" + ], + [ + "CMT_TOP_WW4END1_0", + "VBRK_WW4END1" + ], + [ + "CMT_TOP_LH9_0", + "VBRK_LH9" + ], + [ + "CMT_TOP_NW2A3_0", + "VBRK_NW2A3" + ], + [ + "CMT_TOP_NE4C3_0", + "VBRK_NE4C3" + ], + [ + "CMT_TOP_NW2A2_0", + "VBRK_NW2A2" + ], + [ + "CMT_TOP_SE4BEG1_0", + "VBRK_SE4BEG1" + ], + [ + "CMT_TOP_NE4C1_0", + "VBRK_NE4C1" + ], + [ + "CMT_TOP_WW4B1_0", + "VBRK_WW4B1" + ], + [ + "CMT_TOP_SW4END1_0", + "VBRK_SW4END1" + ], + [ + "CMT_TOP_SW4A0_0", + "VBRK_SW4A0" + ], + [ + "CMT_TOP_SW2A2_0", + "VBRK_SW2A2" + ], + [ + "CMT_TOP_SE2A2_0", + "VBRK_SE2A2" + ], + [ + "CMT_TOP_LH3_0", + "VBRK_LH3" + ], + [ + "CMT_TOP_EE4B3_0", + "VBRK_EE4B3" + ], + [ + "CMT_TOP_NW4END1_0", + "VBRK_NW4END1" + ], + [ + "CMT_TOP_LH11_0", + "VBRK_LH11" + ], + [ + "CMT_TOP_EE4C1_0", + "VBRK_EE4C1" + ], + [ + "CMT_TOP_WW4END0_0", + "VBRK_WW4END0" + ], + [ + "CMT_TOP_SE4BEG3_0", + "VBRK_SE4BEG3" + ], + [ + "CMT_TOP_WW4B3_0", + "VBRK_WW4B3" + ], + [ + "CMT_TOP_NE2A0_0", + "VBRK_NE2A0" + ], + [ + "CMT_TOP_NE4BEG2_0", + "VBRK_NE4BEG2" + ], + [ + "CMT_TOP_WW4B2_0", + "VBRK_WW4B2" + ], + [ + "CMT_TOP_EE4BEG0_0", + "VBRK_EE4BEG0" + ], + [ + "CMT_TOP_SE4C3_0", + "VBRK_SE4C3" + ], + [ + "CMT_TOP_WL1END1_0", + "VBRK_WL1END1" + ], + [ + "CMT_TOP_SE2A1_0", + "VBRK_SE2A1" + ], + [ + "CMT_TOP_EE4BEG2_0", + "VBRK_EE4BEG2" + ], + [ + "CMT_TOP_LH6_0", + "VBRK_LH6" + ], + [ + "CMT_TOP_EL1BEG0_0", + "VBRK_EL1BEG0" + ], + [ + "CMT_TOP_NW2A0_0", + "VBRK_NW2A0" + ], + [ + "CMT_TOP_WW4A3_0", + "VBRK_WW4A3" + ], + [ + "CMT_TOP_LH2_0", + "VBRK_LH2" + ], + [ + "CMT_TOP_WW2A1_0", + "VBRK_WW2A1" + ], + [ + "CMT_TOP_WW4B0_0", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_ER1BEG1_0", + "VBRK_ER1BEG1" + ], + [ + "CMT_TOP_EE4B1_0", + "VBRK_EE4B1" + ], + [ + "CMT_TOP_WR1END1_0", + "VBRK_WR1END1" + ], + [ + "CMT_TOP_WW2A0_0", + "VBRK_WW2A0" + ], + [ + "CMT_TOP_LH12_0", + "VBRK_LH12" + ], + [ + "CMT_TOP_NW4A3_0", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_WW4A1_0", + "VBRK_WW4A1" + ], + [ + "CMT_TOP_EE4A1_0", + "VBRK_EE4A1" + ], + [ + "CMT_TOP_ER1BEG2_0", + "VBRK_ER1BEG2" + ], + [ + "CMT_TOP_EL1BEG1_0", + "VBRK_EL1BEG1" + ], + [ + "CMT_TOP_SE2A0_0", + "VBRK_SE2A0" + ], + [ + "CMT_TOP_WW4END2_0", + "VBRK_WW4END2" + ], + [ + "CMT_TOP_SE2A3_0", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_LH7_0", + "VBRK_LH7" + ], + [ + "CMT_TOP_WR1END0_0", + "VBRK_WR1END0" + ], + [ + "CMT_TOP_NE4BEG1_0", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_SW4A1_0", + "VBRK_SW4A1" + ], + [ + "CMT_TOP_SW4A3_0", + "VBRK_SW4A3" + ], + [ + "CMT_TOP_WR1END3_0", + "VBRK_WR1END3" + ], + [ + "CMT_TOP_NE2A1_0", + "VBRK_NE2A1" + ], + [ + "CMT_TOP_SW4END0_0", + "VBRK_SW4END0" + ], + [ + "CMT_TOP_WW4END3_0", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_EE2A0_0", + "VBRK_EE2A0" + ], + [ + "CMT_TOP_WW4C2_0", + "VBRK_WW4C2" + ], + [ + "CMT_TOP_SW2A1_0", + "VBRK_SW2A1" + ], + [ + "CMT_TOP_EE2A1_0", + "VBRK_EE2A1" + ], + [ + "CMT_TOP_EE4BEG3_0", + "VBRK_EE4BEG3" + ], + [ + "CMT_TOP_NE4BEG0_0", + "VBRK_NE4BEG0" + ], + [ + "CMT_TOP_WW2END2_0", + "VBRK_WW2END2" + ], + [ + "CMT_TOP_LH10_0", + "VBRK_LH10" + ], + [ + "CMT_TOP_NW4A2_0", + "VBRK_NW4A2" + ], + [ + "CMT_TOP_WW4A2_0", + "VBRK_WW4A2" + ], + [ + "CMT_TOP_EE2BEG2_0", + "VBRK_EE2BEG2" + ], + [ + "CMT_TOP_NE2A2_0", + "VBRK_NE2A2" + ], + [ + "CMT_TOP_SE4BEG2_0", + "VBRK_SE4BEG2" + ], + [ + "CMT_TOP_WL1END0_0", + "VBRK_WL1END0" + ], + [ + "CMT_TOP_SE4C0_0", + "VBRK_SE4C0" + ], + [ + "CMT_TOP_NW2A1_0", + "VBRK_NW2A1" + ], + [ + "CMT_TOP_NW4END3_0", + "VBRK_NW4END3" + ], + [ + "CMT_TOP_SW2A3_0", + "VBRK_SW2A3" + ], + [ + "CMT_TOP_EE2A2_0", + "VBRK_EE2A2" + ], + [ + "CMT_TOP_NW4END0_0", + "VBRK_NW4END0" + ], + [ + "CMT_TOP_WW2END3_0", + "VBRK_WW2END3" + ], + [ + "CMT_TOP_EE4A3_0", + "VBRK_EE4A3" + ], + [ + "CMT_TOP_EE4A0_0", + "VBRK_EE4A0" + ], + [ + "CMT_TOP_WW4C0_0", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW4A2_0", + "VBRK_SW4A2" + ], + [ + "CMT_TOP_LH1_0", + "VBRK_LH1" + ], + [ + "CMT_TOP_NW4A0_0", + "VBRK_NW4A0" + ], + [ + "CMT_TOP_EL1BEG2_0", + "VBRK_EL1BEG2" + ], + [ + "CMT_TOP_SW4END2_0", + "VBRK_SW4END2" + ], + [ + "CMT_TOP_WW4A0_0", + "VBRK_WW4A0" + ], + [ + "CMT_TOP_EE4BEG1_0", + "VBRK_EE4BEG1" + ], + [ + "CMT_TOP_WR1END2_0", + "VBRK_WR1END2" + ], + [ + "CMT_TOP_WL1END2_0", + "VBRK_WL1END2" + ], + [ + "CMT_TOP_EE4C3_0", + "VBRK_EE4C3" + ], + [ + "CMT_TOP_EE4C2_0", + "VBRK_EE4C2" + ], + [ + "CMT_TOP_WW2A2_0", + "VBRK_WW2A2" + ], + [ + "CMT_TOP_NE4BEG3_0", + "VBRK_NE4BEG3" + ], + [ + "CMT_TOP_EE4B2_0", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_EE4C0_0", + "VBRK_EE4C0" + ], + [ + "CMT_TOP_EE2BEG1_0", + "VBRK_EE2BEG1" + ], + [ + "CMT_TOP_NE2A3_0", + "VBRK_NE2A3" + ], + [ + "CMT_TOP_ER1BEG3_0", + "VBRK_ER1BEG3" + ], + [ + "CMT_TOP_WL1END3_0", + "VBRK_WL1END3" + ], + [ + "CMT_TOP_NW4END2_0", + "VBRK_NW4END2" + ], + [ + "CMT_TOP_EE2A3_0", + "VBRK_EE2A3" + ], + [ + "CMT_TOP_SW4END3_0", + "VBRK_SW4END3" + ], + [ + "CMT_TOP_SW2A0_0", + "VBRK_SW2A0" + ], + [ + "CMT_TOP_NE4C2_0", + "VBRK_NE4C2" + ], + [ + "CMT_TOP_LH4_0", + "VBRK_LH4" + ], + [ + "CMT_TOP_EL1BEG3_0", + "VBRK_EL1BEG3" + ], + [ + "CMT_TOP_WW2END1_0", + "VBRK_WW2END1" + ] ] }, { - "wire_pairs": [ - [ - "IOI_RCLK_FORIO0", - "IOI_SING_RCLK_FORIO0" - ], - [ - "IOI_LEAF_GCLK4", - "IOI_SING_LEAF_GCLK4" - ], - [ - "IOI_IOCLK3", - "IOI_SING_IOCLK3" - ], - [ - "IOI_IOCLK0", - "IOI_SING_IOCLK0" - ], - [ - "IOI_IOCLK2", - "IOI_SING_IOCLK2" - ], - [ - "IOI_RCLK_FORIO2", - "IOI_SING_RCLK_FORIO2" - ], - [ - "IOI_LEAF_GCLK0", - "IOI_SING_LEAF_GCLK0" - ], - [ - "IOI_LEAF_GCLK5", - "IOI_SING_LEAF_GCLK5" - ], - [ - "IOI_LEAF_GCLK1", - "IOI_SING_LEAF_GCLK1" - ], - [ - "IOI_RCLK_FORIO1", - "IOI_SING_RCLK_FORIO1" - ], - [ - "IOI_IOCLK1", - "IOI_SING_IOCLK1" - ], - [ - "IOI_LEAF_GCLK2", - "IOI_SING_LEAF_GCLK2" - ], - [ - "IOI_TBYTEIN", - "IOI_SING_TBYTEIN" - ], - [ - "IOI_RCLK_FORIO3", - "IOI_SING_RCLK_FORIO3" - ], - [ - "IOI_LEAF_GCLK3", - "IOI_SING_LEAF_GCLK3" - ] - ], "tile_types": [ - "LIOI3", - "LIOI3_SING" + "HCLK_CLB", + "HCLK_L" ], "grid_deltas": [ - 0, - -2 + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CLB_CK_IN9", + "HCLK_CK_IN9" + ], + [ + "HCLK_CLB_CK_IN11", + "HCLK_CK_IN11" + ], + [ + "HCLK_CLB_CK_IN7", + "HCLK_CK_IN7" + ], + [ + "HCLK_CLB_CK_BUFHCLK5", + "HCLK_CK_BUFHCLK5" + ], + [ + "HCLK_CLB_CK_BUFRCLK3", + "HCLK_CK_BUFRCLK3" + ], + [ + "HCLK_CLB_CK_BUFRCLK1", + "HCLK_CK_BUFRCLK1" + ], + [ + "HCLK_CLB_CK_IN6", + "HCLK_CK_IN6" + ], + [ + "HCLK_CLB_CK_IN2", + "HCLK_CK_IN2" + ], + [ + "HCLK_CLB_PERFCLK3", + "HCLK_INT_PERFCLK3" + ], + [ + "HCLK_CLB_CK_BUFHCLK10", + "HCLK_CK_BUFHCLK10" + ], + [ + "HCLK_CLB_CK_IN1", + "HCLK_CK_IN1" + ], + [ + "HCLK_CLB_CK_BUFHCLK3", + "HCLK_CK_BUFHCLK3" + ], + [ + "HCLK_CLB_CK_IN5", + "HCLK_CK_IN5" + ], + [ + "HCLK_CLB_CK_IN10", + "HCLK_CK_IN10" + ], + [ + "HCLK_CLB_CK_BUFHCLK1", + "HCLK_CK_BUFHCLK1" + ], + [ + "HCLK_CLB_PERFCLK0", + "HCLK_INT_PERFCLK0" + ], + [ + "HCLK_CLB_CK_IN3", + "HCLK_CK_IN3" + ], + [ + "HCLK_CLB_CK_BUFHCLK6", + "HCLK_CK_BUFHCLK6" + ], + [ + "HCLK_CLB_CK_IN12", + "HCLK_CK_IN12" + ], + [ + "HCLK_CLB_CK_BUFHCLK8", + "HCLK_CK_BUFHCLK8" + ], + [ + "HCLK_CLB_CK_IN13", + "HCLK_CK_IN13" + ], + [ + "HCLK_CLB_CK_BUFHCLK11", + "HCLK_CK_BUFHCLK11" + ], + [ + "HCLK_CLB_CK_BUFHCLK7", + "HCLK_CK_BUFHCLK7" + ], + [ + "HCLK_CLB_PERFCLK1", + "HCLK_INT_PERFCLK1" + ], + [ + "HCLK_CLB_CK_BUFHCLK0", + "HCLK_CK_BUFHCLK0" + ], + [ + "HCLK_CLB_CK_IN4", + "HCLK_CK_IN4" + ], + [ + "HCLK_CLB_PERFCLK2", + "HCLK_INT_PERFCLK2" + ], + [ + "HCLK_CLB_CK_BUFRCLK0", + "HCLK_CK_BUFRCLK0" + ], + [ + "HCLK_CLB_CK_IN0", + "HCLK_CK_IN0" + ], + [ + "HCLK_CLB_CK_BUFHCLK4", + "HCLK_CK_BUFHCLK4" + ], + [ + "HCLK_CLB_CK_BUFHCLK2", + "HCLK_CK_BUFHCLK2" + ], + [ + "HCLK_CLB_CK_BUFHCLK9", + "HCLK_CK_BUFHCLK9" + ], + [ + "HCLK_CLB_CK_IN8", + "HCLK_CK_IN8" + ], + [ + "HCLK_CLB_CK_BUFRCLK2", + "HCLK_CK_BUFRCLK2" + ] ] }, { + "tile_types": [ + "CMT_TOP_R_UPPER_T", + "VBRK" + ], + "grid_deltas": [ + 1, + -1 + ], "wire_pairs": [ [ - "GTPE2_CLK1_9", - "VBRK_EXT_CLK1" + "CMT_TOP_EE4A1_6", + "VBRK_EE4A1" ], [ - "GTPE2_LOGIC_OUTS_B13_9", - "VBRK_EXT_LOGIC_OUTS_B13" + "CMT_TOP_EE4C0_6", + "VBRK_EE4C0" ], [ - "GTPE2_IMUX47_9", - "VBRK_EXT_IMUX47" + "CMT_TOP_WW4B1_6", + "VBRK_WW4B1" ], [ - "GTPE2_IMUX11_9", - "VBRK_EXT_IMUX11" + "CMT_TOP_SW2A1_6", + "VBRK_SW2A1" ], [ - "GTPE2_LOGIC_OUTS_B15_9", - "VBRK_EXT_LOGIC_OUTS_B15" + "CMT_TOP_EE4C1_6", + "VBRK_EE4C1" ], [ - "GTPE2_IMUX26_9", - "VBRK_EXT_IMUX26" + "CMT_TOP_EL1BEG2_6", + "VBRK_EL1BEG2" ], [ - "GTPE2_IMUX42_9", - "VBRK_EXT_IMUX42" + "CMT_TOP_SW4END2_6", + "VBRK_SW4END2" ], [ - "GTPE2_IMUX25_9", - "VBRK_EXT_IMUX25" + "CMT_TOP_EE4BEG1_6", + "VBRK_EE4BEG1" ], [ - "GTPE2_IMUX34_9", - "VBRK_EXT_IMUX34" + "CMT_TOP_SE4BEG1_6", + "VBRK_SE4BEG1" ], [ - "GTPE2_IMUX6_9", - "VBRK_EXT_IMUX6" + "CMT_TOP_NE4BEG0_6", + "VBRK_NE4BEG0" ], [ - "GTPE2_IMUX2_9", - "VBRK_EXT_IMUX2" + "CMT_TOP_SE4BEG0_6", + "VBRK_SE4BEG0" ], [ - "GTPE2_IMUX41_9", - "VBRK_EXT_IMUX41" + "CMT_TOP_SW4A2_6", + "VBRK_SW4A2" ], [ - "GTPE2_FAN5_9", - "VBRK_EXT_FAN5" + "CMT_TOP_EL1BEG1_6", + "VBRK_EL1BEG1" ], [ - "GTPE2_BYP1_9", - "VBRK_EXT_BYP1" + "CMT_TOP_EE2A2_6", + "VBRK_EE2A2" ], [ - "GTPE2_IMUX16_9", - "VBRK_EXT_IMUX16" + "CMT_TOP_ER1BEG3_6", + "VBRK_ER1BEG3" ], [ - "GTPE2_LOGIC_OUTS_B20_9", - "VBRK_EXT_LOGIC_OUTS_B20" + "CMT_TOP_LH11_6", + "VBRK_LH11" ], [ - "GTPE2_LOGIC_OUTS_B23_9", - "VBRK_EXT_LOGIC_OUTS_B23" + "CMT_TOP_SE2A2_6", + "VBRK_SE2A2" ], [ - "GTPE2_FAN0_9", - "VBRK_EXT_FAN0" + "CMT_TOP_SW4END3_6", + "VBRK_SW4END3" ], [ - "GTPE2_IMUX4_9", - "VBRK_EXT_IMUX4" + "CMT_TOP_WL1END0_6", + "VBRK_WL1END0" ], [ - "GTPE2_LOGIC_OUTS_B18_9", - "VBRK_EXT_LOGIC_OUTS_B18" + "CMT_TOP_WW2A1_6", + "VBRK_WW2A1" ], [ - "GTPE2_IMUX38_9", - "VBRK_EXT_IMUX38" + "CMT_TOP_WL1END2_6", + "VBRK_WL1END2" ], [ - "GTPE2_IMUX24_9", - "VBRK_EXT_IMUX24" + "CMT_TOP_EE2A3_6", + "VBRK_EE2A3" ], [ - "GTPE2_IMUX18_9", - "VBRK_EXT_IMUX18" + "CMT_TOP_EE4B3_6", + "VBRK_EE4B3" ], [ - "GTPE2_FAN2_9", - "VBRK_EXT_FAN2" + "CMT_TOP_WW4B2_6", + "VBRK_WW4B2" ], [ - "GTPE2_LOGIC_OUTS_B14_9", - "VBRK_EXT_LOGIC_OUTS_B14" + "CMT_TOP_NE2A2_6", + "VBRK_NE2A2" ], [ - "GTPE2_IMUX36_9", - "VBRK_EXT_IMUX36" + "CMT_TOP_NE4BEG1_6", + "VBRK_NE4BEG1" ], [ - "GTPE2_BYP3_9", - "VBRK_EXT_BYP3" + "CMT_TOP_WW4A0_6", + "VBRK_WW4A0" ], [ - "GTPE2_IMUX35_9", - "VBRK_EXT_IMUX35" + "CMT_TOP_EE2BEG0_6", + "VBRK_EE2BEG0" ], [ - "GTPE2_IMUX17_9", - "VBRK_EXT_IMUX17" + "CMT_TOP_EE4B1_6", + "VBRK_EE4B1" ], [ - "GTPE2_FAN7_9", - "VBRK_EXT_FAN7" + "CMT_TOP_NW4A1_6", + "VBRK_NW4A1" ], [ - "GTPE2_IMUX3_9", - "VBRK_EXT_IMUX3" + "CMT_TOP_NE2A3_6", + "VBRK_NE2A3" ], [ - "GTPE2_IMUX27_9", - "VBRK_EXT_IMUX27" + "CMT_TOP_NW4A3_6", + "VBRK_NW4A3" ], [ - "GTPE2_BYP7_9", - "VBRK_EXT_BYP7" + "CMT_TOP_WL1END1_6", + "VBRK_WL1END1" ], [ - "GTPE2_IMUX12_9", - "VBRK_EXT_IMUX12" + "CMT_TOP_NW2A1_6", + "VBRK_NW2A1" ], [ - "GTPE2_IMUX20_9", - "VBRK_EXT_IMUX20" + "CMT_TOP_NW4END1_6", + "VBRK_NW4END1" ], [ - "GTPE2_IMUX14_9", - "VBRK_EXT_IMUX14" + "CMT_TOP_SE4BEG2_6", + "VBRK_SE4BEG2" ], [ - "GTPE2_IMUX21_9", - "VBRK_EXT_IMUX21" + "CMT_TOP_WW4A3_6", + "VBRK_WW4A3" ], [ - "GTPE2_IMUX19_9", - "VBRK_EXT_IMUX19" + "CMT_TOP_NW4A0_6", + "VBRK_NW4A0" ], [ - "GTPE2_IMUX39_9", - "VBRK_EXT_IMUX39" + "CMT_TOP_EE2BEG2_6", + "VBRK_EE2BEG2" ], [ - "GTPE2_LOGIC_OUTS_B2_9", - "VBRK_EXT_LOGIC_OUTS_B2" + "CMT_TOP_MONITOR_P_6", + "VBRK_MONITOR_P" ], [ - "GTPE2_LOGIC_OUTS_B7_9", - "VBRK_EXT_LOGIC_OUTS_B7" + "CMT_TOP_EE4A3_6", + "VBRK_EE4A3" ], [ - "GTPE2_IMUX15_9", - "VBRK_EXT_IMUX15" + "CMT_TOP_SW2A0_6", + "VBRK_SW2A0" ], [ - "GTPE2_LOGIC_OUTS_B9_9", - "VBRK_EXT_LOGIC_OUTS_B9" + "CMT_TOP_SE4C1_6", + "VBRK_SE4C1" ], [ - "GTPE2_LOGIC_OUTS_B0_9", - "VBRK_EXT_LOGIC_OUTS_B0" + "CMT_TOP_SW4A3_6", + "VBRK_SW4A3" ], [ - "GTPE2_IMUX44_9", - "VBRK_EXT_IMUX44" + "CMT_TOP_EE4A0_6", + "VBRK_EE4A0" ], [ - "GTPE2_LOGIC_OUTS_B12_9", - "VBRK_EXT_LOGIC_OUTS_B12" + "CMT_TOP_SE4C2_6", + "VBRK_SE4C2" ], [ - "GTPE2_IMUX32_9", - "VBRK_EXT_IMUX32" + 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"VBRK_EXT_IMUX10" + "CMT_TOP_LH7_6", + "VBRK_LH7" ], [ - "GTPE2_LOGIC_OUTS_B16_9", - "VBRK_EXT_LOGIC_OUTS_B16" + "CMT_TOP_WW4END3_6", + "VBRK_WW4END3" ], [ - "GTPE2_FAN1_9", - "VBRK_EXT_FAN1" + "CMT_TOP_LH9_6", + "VBRK_LH9" ], [ - "GTPE2_IMUX43_9", - "VBRK_EXT_IMUX43" + "CMT_TOP_EE4BEG3_6", + "VBRK_EE4BEG3" ], [ - "GTPE2_IMUX9_9", - "VBRK_EXT_IMUX9" + "CMT_TOP_NW4END3_6", + "VBRK_NW4END3" ], [ - "GTPE2_IMUX8_9", - "VBRK_EXT_IMUX8" + "CMT_TOP_SW4END1_6", + "VBRK_SW4END1" ], [ - "GTPE2_IMUX40_9", - "VBRK_EXT_IMUX40" + "CMT_TOP_EE4C3_6", + "VBRK_EE4C3" ], [ - "GTPE2_BYP5_9", - "VBRK_EXT_BYP5" + "CMT_TOP_SE2A0_6", + "VBRK_SE2A0" ], [ - "GTPE2_IMUX29_9", - "VBRK_EXT_IMUX29" + "CMT_TOP_LH4_6", + "VBRK_LH4" ], [ - "GTPE2_IMUX1_9", - "VBRK_EXT_IMUX1" + "CMT_TOP_SW2A3_6", + "VBRK_SW2A3" ], [ - "GTPE2_IMUX5_9", - "VBRK_EXT_IMUX5" + "CMT_TOP_WW2A2_6", + "VBRK_WW2A2" ], [ - "GTPE2_CTRL0_9", - "VBRK_EXT_CTRL0" + "CMT_TOP_LH8_6", + "VBRK_LH8" ], [ - "GTPE2_IMUX23_9", - "VBRK_EXT_IMUX23" + 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"VBRK_EE2A3" + ], + [ + "CMT_TOP_WW4C0_4", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_SW2A0_4", + "VBRK_SW2A0" + ] + ] + }, + { + "tile_types": [ + "CLK_PMV", + "VBRK" + ], + "grid_deltas": [ + 1, + -5 + ], + "wire_pairs": [ + [ + "CLK_PMV_EE4B3_5", + "VBRK_EE4B3" + ], + [ + "CLK_PMV_LH11_5", + "VBRK_LH11" + ], + [ + "CLK_PMV_WW2END3_5", + "VBRK_WW2END3" + ], + [ + "CLK_PMV_WW4C2_5", + "VBRK_WW4C2" + ], [ "CLK_PMV_NE2A1_5", "VBRK_NE2A1" ], [ - "CLK_PMV_ER1BEG0_5", - "VBRK_ER1BEG0" + "CLK_PMV_ER1BEG2_5", + "VBRK_ER1BEG2" ], [ - "CLK_PMV_LH10_5", - "VBRK_LH10" + "CLK_PMV_WW4A1_5", + "VBRK_WW4A1" ], [ - "CLK_PMV_EE4B0_5", - "VBRK_EE4B0" + "CLK_PMV_NE4BEG3_5", + "VBRK_NE4BEG3" ], [ - "CLK_PMV_LH4_5", - "VBRK_LH4" + "CLK_PMV_WW4B0_5", + "VBRK_WW4B0" ], [ - "CLK_PMV_WW4A3_5", - "VBRK_WW4A3" + "CLK_PMV_EE2BEG2_5", + "VBRK_EE2BEG2" ], [ - "CLK_PMV_SW4A2_5", - "VBRK_SW4A2" + "CLK_PMV_SW4END2_5", + "VBRK_SW4END2" ], [ - "CLK_PMV_WW2END1_5", - "VBRK_WW2END1" + "CLK_PMV_EE4C1_5", + "VBRK_EE4C1" ], [ - "CLK_PMV_NW2A2_5", - "VBRK_NW2A2" + "CLK_PMV_WW2END0_5", + "VBRK_WW2END0" ], [ - "CLK_PMV_SW2A2_5", - "VBRK_SW2A2" + "CLK_PMV_WR1END2_5", + "VBRK_WR1END2" ], [ - "CLK_PMV_EL1BEG0_5", - "VBRK_EL1BEG0" + "CLK_PMV_NW4END2_5", + "VBRK_NW4END2" ], [ - "CLK_PMV_SE4C0_5", - "VBRK_SE4C0" + "CLK_PMV_SE2A0_5", + "VBRK_SE2A0" ], [ - "CLK_PMV_EE4C2_5", - "VBRK_EE4C2" + "CLK_PMV_NE4C2_5", + "VBRK_NE4C2" ], [ - "CLK_PMV_SW2A0_5", - "VBRK_SW2A0" + "CLK_PMV_NE4C0_5", + "VBRK_NE4C0" ], [ - "CLK_PMV_WW2A2_5", - "VBRK_WW2A2" + "CLK_PMV_NW4END0_5", + "VBRK_NW4END0" ], [ - "CLK_PMV_WR1END1_5", - "VBRK_WR1END1" + "CLK_PMV_SW4END3_5", + "VBRK_SW4END3" ], [ - "CLK_PMV_NE4C1_5", - "VBRK_NE4C1" + "CLK_PMV_NW4END3_5", + "VBRK_NW4END3" + ], + [ + "CLK_PMV_WW4END3_5", + "VBRK_WW4END3" + ], + [ + "CLK_PMV_WW4A2_5", + "VBRK_WW4A2" ], [ "CLK_PMV_SW2A1_5", "VBRK_SW2A1" ], [ - "CLK_PMV_WW2A0_5", - "VBRK_WW2A0" + "CLK_PMV_SW4END1_5", + "VBRK_SW4END1" ], [ - "CLK_PMV_EE2BEG3_5", - "VBRK_EE2BEG3" + "CLK_PMV_WW2END2_5", + "VBRK_WW2END2" ], [ - "CLK_PMV_EE4A3_5", - "VBRK_EE4A3" + "CLK_PMV_WL1END0_5", + "VBRK_WL1END0" ], [ - "CLK_PMV_NW4END0_5", - "VBRK_NW4END0" + "CLK_PMV_EE4A1_5", + "VBRK_EE4A1" + ], + [ + "CLK_PMV_WW2A1_5", + "VBRK_WW2A1" + ], + [ + "CLK_PMV_LH9_5", + "VBRK_LH9" + ], + [ + "CLK_PMV_EE4A2_5", + "VBRK_EE4A2" + ], + [ + "CLK_PMV_SE4C2_5", + "VBRK_SE4C2" + ], + [ + "CLK_PMV_ER1BEG0_5", + "VBRK_ER1BEG0" + ], + [ + "CLK_PMV_WW4B2_5", + "VBRK_WW4B2" + ], + [ + "CLK_PMV_EE4BEG2_5", + "VBRK_EE4BEG2" + ], + [ + "CLK_PMV_EE2A3_5", + "VBRK_EE2A3" + ], + [ + "CLK_PMV_EE2A0_5", + "VBRK_EE2A0" + ], + [ + "CLK_PMV_WW4C0_5", + "VBRK_WW4C0" + ], + [ + "CLK_PMV_EE2BEG0_5", + "VBRK_EE2BEG0" + ], + [ + "CLK_PMV_WW4A3_5", + "VBRK_WW4A3" + ], + [ + "CLK_PMV_EE4B2_5", + "VBRK_EE4B2" + ], + [ + "CLK_PMV_WW2A2_5", + "VBRK_WW2A2" + ], + [ + "CLK_PMV_WL1END1_5", + "VBRK_WL1END1" + ], + [ + "CLK_PMV_LH12_5", + "VBRK_LH12" + ], + [ + "CLK_PMV_EL1BEG1_5", + "VBRK_EL1BEG1" + ], + [ + "CLK_PMV_NW4A1_5", + "VBRK_NW4A1" + ], + [ + "CLK_PMV_LH5_5", + "VBRK_LH5" + ], + [ + "CLK_PMV_WW4END1_5", + "VBRK_WW4END1" + ], + [ + "CLK_PMV_NE2A3_5", + "VBRK_NE2A3" + ], + [ + "CLK_PMV_SE2A3_5", + "VBRK_SE2A3" + ], + [ + "CLK_PMV_LH4_5", + "VBRK_LH4" + ], + [ + "CLK_PMV_WW4B3_5", + "VBRK_WW4B3" + ], + [ + "CLK_PMV_SW2A2_5", + "VBRK_SW2A2" + ], + [ + "CLK_PMV_WW4C1_5", + "VBRK_WW4C1" + ], + [ + "CLK_PMV_SE4C0_5", + "VBRK_SE4C0" + ], + [ + "CLK_PMV_SW4A2_5", + "VBRK_SW4A2" + ], + [ + "CLK_PMV_NW2A3_5", + "VBRK_NW2A3" + ], + [ + "CLK_PMV_NW2A1_5", + "VBRK_NW2A1" + ], + [ + "CLK_PMV_NW4A3_5", + "VBRK_NW4A3" + ], + [ + "CLK_PMV_LH3_5", + "VBRK_LH3" + ], + [ + "CLK_PMV_NE4BEG0_5", + "VBRK_NE4BEG0" + ], + [ + "CLK_PMV_SE4C1_5", + "VBRK_SE4C1" + ], + [ + "CLK_PMV_EE4A0_5", + "VBRK_EE4A0" + ], + [ + "CLK_PMV_EE4B0_5", + "VBRK_EE4B0" + ], + [ + "CLK_PMV_EL1BEG3_5", + "VBRK_EL1BEG3" + ], + [ + "CLK_PMV_NE2A2_5", + "VBRK_NE2A2" + ], + [ + "CLK_PMV_NE4BEG1_5", + "VBRK_NE4BEG1" + ], + [ + "CLK_PMV_SE4BEG0_5", + "VBRK_SE4BEG0" + ], + [ + "CLK_PMV_WL1END3_5", + "VBRK_WL1END3" + ], + [ + "CLK_PMV_SW2A3_5", + "VBRK_SW2A3" + ], + [ + "CLK_PMV_LH6_5", + "VBRK_LH6" ], [ "CLK_PMV_WW2A3_5", @@ -473722,285 +121698,352309 @@ "VBRK_WW4A0" ], [ - "CLK_PMV_NW4END2_5", - "VBRK_NW4END2" + "CLK_PMV_SW4A3_5", + "VBRK_SW4A3" ], [ - "CLK_PMV_WW2END3_5", - "VBRK_WW2END3" + "CLK_PMV_EE4C2_5", + "VBRK_EE4C2" ], [ - "CLK_PMV_WW4A1_5", - "VBRK_WW4A1" - ], - [ - "CLK_PMV_EE4BEG2_5", - "VBRK_EE4BEG2" - ], - [ - "CLK_PMV_SE2A2_5", - "VBRK_SE2A2" - ], - [ - "CLK_PMV_EE2BEG2_5", - "VBRK_EE2BEG2" - ], - [ - "CLK_PMV_LH1_5", - "VBRK_LH1" - ], - [ - "CLK_PMV_WW4B2_5", - "VBRK_WW4B2" - ], - [ - "CLK_PMV_SW4END0_5", - "VBRK_SW4END0" - ], - [ - "CLK_PMV_SE4C1_5", - "VBRK_SE4C1" - ], - [ - "CLK_PMV_NW2A3_5", - "VBRK_NW2A3" - ], - [ - "CLK_PMV_EE4BEG1_5", - "VBRK_EE4BEG1" - ], - [ - "CLK_PMV_EE4A0_5", - "VBRK_EE4A0" - ], - [ - "CLK_PMV_WL1END0_5", - "VBRK_WL1END0" - ], - [ - "CLK_PMV_SE4C2_5", - "VBRK_SE4C2" - ], - [ - "CLK_PMV_EE4B2_5", - "VBRK_EE4B2" - ], - [ - "CLK_PMV_EE4B3_5", - "VBRK_EE4B3" - ], - [ - "CLK_PMV_LH9_5", - "VBRK_LH9" - ], - [ - "CLK_PMV_SW4A1_5", - "VBRK_SW4A1" - ], - [ - "CLK_PMV_WW4C0_5", - "VBRK_WW4C0" - ], - [ - "CLK_PMV_SE2A0_5", - "VBRK_SE2A0" + "CLK_PMV_EE4C3_5", + "VBRK_EE4C3" ], [ "CLK_PMV_EE2A1_5", "VBRK_EE2A1" ], - [ - "CLK_PMV_LH7_5", - "VBRK_LH7" - ], - [ - "CLK_PMV_NW2A0_5", - "VBRK_NW2A0" - ], - [ - "CLK_PMV_EL1BEG3_5", - "VBRK_EL1BEG3" - ], - [ - "CLK_PMV_WW4END2_5", - "VBRK_WW4END2" - ], - [ - "CLK_PMV_NE4BEG0_5", - "VBRK_NE4BEG0" - ], - [ - "CLK_PMV_NE4BEG3_5", - "VBRK_NE4BEG3" - ], - [ - "CLK_PMV_WL1END1_5", - "VBRK_WL1END1" - ], - [ - "CLK_PMV_NW4A2_5", - "VBRK_NW4A2" - ], - [ - "CLK_PMV_EE4B1_5", - "VBRK_EE4B1" - ], - [ - "CLK_PMV_LH12_5", - "VBRK_LH12" - ], - [ - "CLK_PMV_LH11_5", - "VBRK_LH11" - ], - [ - "CLK_PMV_SW4END2_5", - "VBRK_SW4END2" - ], [ "CLK_PMV_EE4BEG3_5", "VBRK_EE4BEG3" ], [ - "CLK_PMV_NE2A3_5", - "VBRK_NE2A3" + "CLK_PMV_WW2END1_5", + "VBRK_WW2END1" ], [ - "CLK_PMV_WW4C1_5", - "VBRK_WW4C1" + "CLK_PMV_EE2BEG3_5", + "VBRK_EE2BEG3" ], [ - "CLK_PMV_EE4C0_5", - "VBRK_EE4C0" + "CLK_PMV_NE4BEG2_5", + "VBRK_NE4BEG2" ], [ - "CLK_PMV_WW4END0_5", - "VBRK_WW4END0" + "CLK_PMV_ER1BEG1_5", + "VBRK_ER1BEG1" ], [ - "CLK_PMV_SE4BEG0_5", - "VBRK_SE4BEG0" - ], - [ - "CLK_PMV_WW4END3_5", - "VBRK_WW4END3" - ], - [ - "CLK_PMV_NE2A2_5", - "VBRK_NE2A2" - ], - [ - "CLK_PMV_LH5_5", - "VBRK_LH5" - ], - [ - "CLK_PMV_SW4A0_5", - "VBRK_SW4A0" - ], - [ - "CLK_PMV_SW4A3_5", - "VBRK_SW4A3" - ], - [ - "CLK_PMV_WW4C2_5", - "VBRK_WW4C2" - ], - [ - "CLK_PMV_NW2A1_5", - "VBRK_NW2A1" - ], - [ - "CLK_PMV_LH8_5", - "VBRK_LH8" - ], - [ - "CLK_PMV_NW4A0_5", - "VBRK_NW4A0" - ], - [ - "CLK_PMV_NE4C0_5", - "VBRK_NE4C0" - ], - [ - "CLK_PMV_SW2A3_5", - "VBRK_SW2A3" - ], - [ - "CLK_PMV_EE2BEG0_5", - "VBRK_EE2BEG0" - ], - [ - "CLK_PMV_WW2END2_5", - "VBRK_WW2END2" - ], - [ - "CLK_PMV_WW4C3_5", - "VBRK_WW4C3" - ], - [ - "CLK_PMV_EE2A3_5", - "VBRK_EE2A3" - ], - [ - "CLK_PMV_LH6_5", - "VBRK_LH6" - ], - [ - "CLK_PMV_WL1END3_5", - "VBRK_WL1END3" - ], - [ - "CLK_PMV_WR1END2_5", - "VBRK_WR1END2" - ], - [ - "CLK_PMV_SE2A1_5", - "VBRK_SE2A1" - ], - [ - "CLK_PMV_NW4END1_5", - "VBRK_NW4END1" - ], - [ - "CLK_PMV_EE4A2_5", - "VBRK_EE4A2" - ], - [ - "CLK_PMV_WW4B3_5", - "VBRK_WW4B3" - ], - [ - "CLK_PMV_WW4A2_5", - "VBRK_WW4A2" - ], - [ - "CLK_PMV_WW4END1_5", - "VBRK_WW4END1" - ], - [ - "CLK_PMV_EE2A0_5", - "VBRK_EE2A0" + "CLK_PMV_WR1END1_5", + "VBRK_WR1END1" ], [ "CLK_PMV_WL1END2_5", "VBRK_WL1END2" ], + [ + "CLK_PMV_NW2A2_5", + "VBRK_NW2A2" + ], + [ + "CLK_PMV_EL1BEG2_5", + "VBRK_EL1BEG2" + ], + [ + "CLK_PMV_NW4A0_5", + "VBRK_NW4A0" + ], + [ + "CLK_PMV_EE4B1_5", + "VBRK_EE4B1" + ], + [ + "CLK_PMV_SE2A2_5", + "VBRK_SE2A2" + ], + [ + "CLK_PMV_WR1END0_5", + "VBRK_WR1END0" + ], + [ + "CLK_PMV_NE4C1_5", + "VBRK_NE4C1" + ], + [ + "CLK_PMV_LH2_5", + "VBRK_LH2" + ], + [ + "CLK_PMV_LH7_5", + "VBRK_LH7" + ], + [ + "CLK_PMV_LH1_5", + "VBRK_LH1" + ], + [ + "CLK_PMV_SE4BEG1_5", + "VBRK_SE4BEG1" + ], + [ + "CLK_PMV_EE2A2_5", + "VBRK_EE2A2" + ], [ "CLK_PMV_WW4B1_5", "VBRK_WW4B1" ], [ - "CLK_PMV_NW4A3_5", - "VBRK_NW4A3" + "CLK_PMV_EL1BEG0_5", + "VBRK_EL1BEG0" + ], + [ + "CLK_PMV_SE2A1_5", + "VBRK_SE2A1" + ], + [ + "CLK_PMV_EE4A3_5", + "VBRK_EE4A3" + ], + [ + "CLK_PMV_WW2A0_5", + "VBRK_WW2A0" + ], + [ + "CLK_PMV_NE2A0_5", + "VBRK_NE2A0" + ], + [ + "CLK_PMV_WW4END0_5", + "VBRK_WW4END0" + ], + [ + "CLK_PMV_WW4C3_5", + "VBRK_WW4C3" + ], + [ + "CLK_PMV_LH10_5", + "VBRK_LH10" + ], + [ + "CLK_PMV_SW4A0_5", + "VBRK_SW4A0" + ], + [ + "CLK_PMV_LH8_5", + "VBRK_LH8" + ], + [ + "CLK_PMV_SE4BEG2_5", + "VBRK_SE4BEG2" + ], + [ + "CLK_PMV_EE4BEG1_5", + "VBRK_EE4BEG1" + ], + [ + "CLK_PMV_NW4A2_5", + "VBRK_NW4A2" + ], + [ + "CLK_PMV_NW4END1_5", + "VBRK_NW4END1" + ], + [ + "CLK_PMV_WR1END3_5", + "VBRK_WR1END3" + ], + [ + "CLK_PMV_SW4A1_5", + "VBRK_SW4A1" + ], + [ + "CLK_PMV_SW4END0_5", + "VBRK_SW4END0" + ], + [ + "CLK_PMV_EE4BEG0_5", + "VBRK_EE4BEG0" + ], + [ + "CLK_PMV_NE4C3_5", + "VBRK_NE4C3" + ], + [ + "CLK_PMV_SW2A0_5", + "VBRK_SW2A0" + ], + [ + "CLK_PMV_SE4BEG3_5", + "VBRK_SE4BEG3" + ], + [ + "CLK_PMV_ER1BEG3_5", + "VBRK_ER1BEG3" + ], + [ + "CLK_PMV_EE2BEG1_5", + "VBRK_EE2BEG1" + ], + [ + "CLK_PMV_NW2A0_5", + "VBRK_NW2A0" + ], + [ + "CLK_PMV_WW4END2_5", + "VBRK_WW4END2" + ], + [ + "CLK_PMV_SE4C3_5", + "VBRK_SE4C3" + ], + [ + "CLK_PMV_EE4C0_5", + "VBRK_EE4C0" ] + ] + }, + { + "tile_types": [ + "DSP_R", + "HCLK_DSP_R" ], + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "DSP_PCOUT18", + "HCLK_DSP_PCIN18" + ], + [ + "DSP_PCOUT16", + "HCLK_DSP_PCIN16" + ], + [ + "DSP_PCOUT8", + "HCLK_DSP_PCIN8" + ], + [ + "DSP_PCOUT46", + "HCLK_DSP_PCIN46" + ], + [ + "DSP_ACOUT23", + "HCLK_DSP_ACIN23" + ], + [ + "DSP_PCOUT4", + "HCLK_DSP_PCIN4" + ], + [ + "DSP_ACOUT9", + "HCLK_DSP_ACIN9" + ], + [ + "DSP_ACOUT8", + "HCLK_DSP_ACIN8" + ], + [ + "DSP_PCOUT0", + "HCLK_DSP_PCIN0" + ], + [ + "DSP_ACOUT29", + "HCLK_DSP_ACIN29" + ], + [ + "DSP_ACOUT12", + "HCLK_DSP_ACIN12" + ], + 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"HCLK_IOI3", + "LIOI3" + ], + "grid_deltas": [ + 0, + 2 + ], + "wire_pairs": [ + [ + "HCLK_IOI_IOCLK1", + "IOI_IOCLK1" + ], + [ + "HCLK_RCLK_DIV_CLR2", + "IOI_RCLK_DIV_CLR2" + ], + [ + "HCLK_IOI_RCLK_IMUX3", + "IOI_IMUX_RC3" + ], + [ + "HCLK_IOI_RCLK2IO0", + "IOI_RCLK_FORIO0" + ], + [ + "HCLK_IOI_RCLK2IO1", + "IOI_RCLK_FORIO1" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT5", + "IOI_LEAF_GCLK5" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT3", + "IOI_LEAF_GCLK3" + ], + [ + "HCLK_RCLK_DIV_CLR3", + "IOI_RCLK_DIV_CLR3" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN65", + "IOI_IDELAYCTRL_OUTN65" + ], + [ + "HCLK_IOI_IDELAYCTRL_OUTN1", + "IOI_IDELAYCTRL_OUTN1" + ], + [ + "HCLK_IOI_LEAF_GCLK_BOT0", + "IOI_LEAF_GCLK0" + ], + [ + "HCLK_RCLK_DIV_CE2", + "IOI_RCLK_DIV_CE2" + ], + [ + "HCLK_IOI_RCLK2IO2", + "IOI_RCLK_FORIO2" + ], + [ + "HCLK_RCLK_DIV_CE3", + "IOI_RCLK_DIV_CE3" + ], + [ + "HCLK_IOI_I2IOCLK_BOT1", + "LIOI_I2GCLK_TOP0" + ], + [ + "HCLK_IOI_IOCLK2", + "IOI_IOCLK2" + ], + [ + "HCLK_IOI_I2IOCLK_BOT0", + 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"CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "BRKH_CLK_R_CK_GCLK21", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "BRKH_CLK_R_CK_GCLK22", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "BRKH_CLK_R_CK_GCLK0", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "BRKH_CLK_R_CK_GCLK15", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "BRKH_CLK_R_CK_GCLK27", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "BRKH_CLK_R_CK_GCLK24", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "BRKH_CLK_R_CK_GCLK2", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "BRKH_CLK_R_CK_GCLK23", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "BRKH_CLK_R_CK_GCLK5", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "BRKH_CLK_R_CK_GCLK16", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "BRKH_CLK_R_CK_GCLK30", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "BRKH_CLK_R_CK_GCLK11", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "BRKH_CLK_R_CK_GCLK10", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "BRKH_CLK_R_CK_GCLK18", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "BRKH_CLK_R_CK_GCLK1", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "BRKH_CLK_R_CK_GCLK17", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "BRKH_CLK_R_CK_GCLK4", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "BRKH_CLK_R_CK_GCLK31", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "BRKH_CLK_R_CK_GCLK13", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "BRKH_CLK_R_CK_GCLK7", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "BRKH_CLK_R_CK_GCLK9", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "BRKH_CLK_R_CK_GCLK26", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "BRKH_CLK_R_CK_GCLK14", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "BRKH_CLK_R_CK_GCLK19", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "BRKH_CLK_R_CK_GCLK28", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "BRKH_CLK_R_CK_GCLK12", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "BRKH_CLK_R_CK_GCLK20", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "BRKH_CLK_R_CK_GCLK29", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "BRKH_CLK_R_CK_GCLK25", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "BRKH_CLK_R_CK_GCLK3", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "BRKH_CLK_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ] + ] + }, + { + "tile_types": [ + "CLK_BUFG_REBUF", + "CLK_FEED" + ], + "grid_deltas": [ + 0, + 1 + ], + "wire_pairs": [ + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", + "CLK_FEED_R_CK_BUFG_CASC10" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", + "CLK_FEED_R_CK_GCLK18" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", + "CLK_FEED_R_CK_GCLK15" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", + "CLK_FEED_R_CK_BUFG_CASC23" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", + "CLK_FEED_R_CK_BUFG_CASC8" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", + "CLK_FEED_R_CK_BUFG_CASC18" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", + "CLK_FEED_R_CK_BUFG_CASC15" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", + "CLK_FEED_R_CK_GCLK24" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", + "CLK_FEED_R_CK_GCLK21" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", + "CLK_FEED_R_CK_BUFG_CASC5" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", + "CLK_FEED_R_CK_BUFG_CASC4" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", + "CLK_FEED_R_CK_BUFG_CASC6" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", + "CLK_FEED_R_CK_GCLK8" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", + "CLK_FEED_R_CK_GCLK2" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", + "CLK_FEED_R_CK_GCLK29" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", + "CLK_FEED_R_CK_GCLK16" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", + "CLK_FEED_R_CK_BUFG_CASC3" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", + "CLK_FEED_R_CK_GCLK26" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", + "CLK_FEED_R_CK_BUFG_CASC2" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", + "CLK_FEED_R_CK_GCLK10" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", + "CLK_FEED_R_CK_BUFG_CASC13" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", + "CLK_FEED_R_CK_GCLK17" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", + "CLK_FEED_R_CK_BUFG_CASC24" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", + "CLK_FEED_R_CK_BUFG_CASC20" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", + "CLK_FEED_R_CK_GCLK20" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", + "CLK_FEED_R_CK_BUFG_CASC7" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", + "CLK_FEED_R_CK_GCLK11" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", + "CLK_FEED_R_CK_BUFG_CASC25" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", + "CLK_FEED_R_CK_GCLK5" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", + "CLK_FEED_R_CK_GCLK13" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", + "CLK_FEED_R_CK_GCLK6" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", + "CLK_FEED_R_CK_GCLK28" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", + "CLK_FEED_R_CK_GCLK4" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", + "CLK_FEED_R_CK_GCLK31" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", + "CLK_FEED_R_CK_GCLK30" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", + "CLK_FEED_R_CK_GCLK25" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", + "CLK_FEED_R_CK_BUFG_CASC30" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", + "CLK_FEED_R_CK_BUFG_CASC17" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", + "CLK_FEED_R_CK_BUFG_CASC26" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", + "CLK_FEED_R_CK_BUFG_CASC28" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", + "CLK_FEED_R_CK_BUFG_CASC14" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", + "CLK_FEED_R_CK_BUFG_CASC0" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", + "CLK_FEED_R_CK_BUFG_CASC31" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", + "CLK_FEED_R_CK_GCLK1" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", + "CLK_FEED_R_CK_GCLK3" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", + "CLK_FEED_R_CK_GCLK12" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", + "CLK_FEED_R_CK_GCLK27" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", + "CLK_FEED_R_CK_BUFG_CASC27" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", + "CLK_FEED_R_CK_GCLK19" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", + "CLK_FEED_R_CK_BUFG_CASC29" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", + "CLK_FEED_R_CK_BUFG_CASC11" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", + "CLK_FEED_R_CK_BUFG_CASC21" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", + "CLK_FEED_R_CK_GCLK22" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", + "CLK_FEED_R_CK_GCLK23" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", + "CLK_FEED_R_CK_GCLK9" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", + "CLK_FEED_R_CK_BUFG_CASC9" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", + "CLK_FEED_R_CK_GCLK7" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", + "CLK_FEED_R_CK_BUFG_CASC16" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", + "CLK_FEED_R_CK_BUFG_CASC19" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", + "CLK_FEED_R_CK_BUFG_CASC22" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", + "CLK_FEED_R_CK_BUFG_CASC1" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", + "CLK_FEED_R_CK_GCLK14" + ], + [ + "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", + "CLK_FEED_R_CK_GCLK0" + ], + [ + "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", + "CLK_FEED_R_CK_BUFG_CASC12" + ] + ] + }, + { + "tile_types": [ + "HCLK_CMT_L", + "HCLK_FIFO_L" + ], + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_FIFO_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_FIFO_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_CCIO3", + "HCLK_FIFO_CCIO3" + ], + [ + "HCLK_CMT_CCIO0", + "HCLK_FIFO_CCIO0" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_FIFO_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_FIFO_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_FIFO_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_FIFO_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_FIFO_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_CCIO2", + "HCLK_FIFO_CCIO2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_FIFO_PERFCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_FIFO_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_FIFO_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_FIFO_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_FIFO_CK_BUFHCLK2" + ], + [ + "HCLK_CMT_CCIO1", + "HCLK_FIFO_CCIO1" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_FIFO_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_FIFO_PERFCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_FIFO_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_FIFO_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_FIFO_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_FIFO_PERFCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + 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"IOI_IMUX7_1", + "TERM_INT_IMUX7" + ], + [ + "IOI_FAN1_1", + "TERM_INT_FAN1" + ], + [ + "IOI_BLOCK_OUTS2_1", + "TERM_INT_BLOCK_OUTS_L_B2" + ], + [ + "IOI_IMUX29_1", + "TERM_INT_IMUX29" + ], + [ + "IOI_LOGIC_OUTS3_1", + "TERM_INT_LOGIC_OUTS_L_B3" + ], + [ + "IOI_IMUX43_1", + "TERM_INT_IMUX43" + ], + [ + "IOI_IMUX37_1", + "TERM_INT_IMUX37" + ], + [ + "IOI_IMUX47_1", + "TERM_INT_IMUX47" + ], + [ + "IOI_LOGIC_OUTS16_1", + "TERM_INT_LOGIC_OUTS_L_B16" + ], + [ + "IOI_FAN3_1", + "TERM_INT_FAN3" + ], + [ + "IOI_IMUX36_1", + "TERM_INT_IMUX36" + ], + [ + "IOI_IMUX8_1", + "TERM_INT_IMUX8" + ], + [ + "IOI_BYP0_1", + "TERM_INT_BYP0" + ], + [ + "IOI_BLOCK_OUTS0_1", + "TERM_INT_BLOCK_OUTS_L_B0" + ], + [ + "IOI_IMUX6_1", + "TERM_INT_IMUX6" + ], + [ + "IOI_FAN7_1", + "TERM_INT_FAN7" + ], + [ + "IOI_CLK0_1", + "TERM_INT_CLK0" + ], + [ + "IOI_IMUX21_1", + "TERM_INT_IMUX21" + ], + [ + "IOI_IMUX40_1", + "TERM_INT_IMUX40" + ], + [ + "IOI_BYP2_1", + "TERM_INT_BYP2" + ], + [ + "IOI_IMUX45_1", + "TERM_INT_IMUX45" + ], + [ + "IOI_BYP3_1", + "TERM_INT_BYP3" + ], + [ + "IOI_IMUX3_1", + "TERM_INT_IMUX3" + ], + [ + "IOI_IMUX1_1", + "TERM_INT_IMUX1" + ], + [ + "IOI_IMUX18_1", + "TERM_INT_IMUX18" + ], + [ + "IOI_IMUX35_1", + "TERM_INT_IMUX35" + ], + [ + "IOI_IMUX30_1", + "TERM_INT_IMUX30" + ], + [ + "IOI_IMUX27_1", + "TERM_INT_IMUX27" + ], + [ + "IOI_IMUX20_1", + "TERM_INT_IMUX20" + ], + [ + "IOI_LOGIC_OUTS13_1", + "TERM_INT_LOGIC_OUTS_L_B13" + ], + [ + "IOI_LOGIC_OUTS23_1", + "TERM_INT_LOGIC_OUTS_L_B23" + ], + [ + "IOI_IMUX24_1", + "TERM_INT_IMUX24" + ], + [ + "IOI_BYP6_1", + "TERM_INT_BYP6" + ], + [ + "IOI_LOGIC_OUTS15_1", + "TERM_INT_LOGIC_OUTS_L_B15" + ], + [ + "IOI_IMUX4_1", + "TERM_INT_IMUX4" + ], + [ + "IOI_LOGIC_OUTS9_1", + "TERM_INT_LOGIC_OUTS_L_B9" + ], + [ + "IOI_LOGIC_OUTS0_1", + "TERM_INT_LOGIC_OUTS_L_B0" + ], + [ + "IOI_IMUX26_1", + "TERM_INT_IMUX26" + ], + [ + "IOI_LOGIC_OUTS11_1", + "TERM_INT_LOGIC_OUTS_L_B11" + ], + [ + "IOI_PHASER_TO_IO_ICLK_0", + "L_TERM_INT_PHASER_TO_IO_ICLK" + ], + [ + "IOI_FAN5_1", + "TERM_INT_FAN5" + ], + [ + "IOI_IMUX34_1", + "TERM_INT_IMUX34" + ], + [ + "IOI_FAN0_1", + "TERM_INT_FAN0" + ], + [ + "IOI_LOGIC_OUTS20_1", + "TERM_INT_LOGIC_OUTS_L_B20" + ], + [ + "IOI_LOGIC_OUTS2_1", + "TERM_INT_LOGIC_OUTS_L_B2" + ], + [ + "IOI_IMUX13_1", + "TERM_INT_IMUX13" + ], + [ + "IOI_IMUX38_1", + "TERM_INT_IMUX38" + ], + [ + "IOI_IMUX22_1", + "TERM_INT_IMUX22" + ], + [ + "IOI_IMUX14_1", + "TERM_INT_IMUX14" + ], + [ + "IOI_FAN4_1", + "TERM_INT_FAN4" + ], + [ + "IOI_BYP5_1", + "TERM_INT_BYP5" + ] + ] + }, + { + "tile_types": [ + "HCLK_IOB", + "HCLK_IOI3" + ], + "grid_deltas": [ + -1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_IOB_CK_BUFHCLK10", + "HCLK_IOI_CK_BUFHCLK10" + ], + [ + "HCLK_IOB_CK_BUFHCLK0", + "HCLK_IOI_CK_BUFHCLK0" + ], + [ + "HCLK_IOB_PERFCLK3", + "HCLK_IOI_IOCLK_PLL3" + ], + [ + "HCLK_IOB_CK_BUFHCLK6", + "HCLK_IOI_CK_BUFHCLK6" + ], + [ + "HCLK_IOB_CK_BUFHCLK7", + "HCLK_IOI_CK_BUFHCLK7" + ], + [ + "HCLK_IOB_CK_BUFHCLK8", + "HCLK_IOI_CK_BUFHCLK8" + ], + [ + "HCLK_IOB_CK_BUFHCLK9", + "HCLK_IOI_CK_BUFHCLK9" + ], + [ + "HCLK_IOB_CK_BUFHCLK11", + "HCLK_IOI_CK_BUFHCLK11" + ], + [ + "HCLK_IOB_PERFCLK1", + "HCLK_IOI_IOCLK_PLL1" + ], + [ + "HCLK_IOB_CK_BUFHCLK4", + "HCLK_IOI_CK_BUFHCLK4" + ], + [ + "HCLK_IOB_PERFCLK2", + "HCLK_IOI_IOCLK_PLL2" + ], + [ + "HCLK_IOB_PERFCLK0", + "HCLK_IOI_IOCLK_PLL0" + ], + [ + "HCLK_IOB_CK_BUFRCLK1", + "HCLK_IOI_CK_BUFRCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK1", + "HCLK_IOI_CK_BUFHCLK1" + ], + [ + "HCLK_IOB_CK_BUFHCLK3", + "HCLK_IOI_CK_BUFHCLK3" + ], + [ + "HCLK_IOB_CK_BUFHCLK5", + "HCLK_IOI_CK_BUFHCLK5" + ], + [ + "HCLK_IOB_CK_BUFRCLK3", + "HCLK_IOI_CK_BUFRCLK3" + ], + [ + "HCLK_IOB_CK_BUFHCLK2", + "HCLK_IOI_CK_BUFHCLK2" + ], + [ + "HCLK_IOB_CK_BUFRCLK0", + "HCLK_IOI_CK_BUFRCLK0" + ], + [ + "HCLK_IOB_CK_BUFRCLK2", + "HCLK_IOI_CK_BUFRCLK2" + ] + ] + }, + { + "tile_types": [ + "CLK_HROW_TOP_R", + "INT_INTERFACE_R" + ], + "grid_deltas": [ + -1, + 2 + ], + "wire_pairs": [ + [ + "CLK_HROW_EE2BEG1_2", + "INT_INTERFACE_EE2BEG1" + ], + [ + "CLK_HROW_LH7_2", + "INT_INTERFACE_LH7" + ], + [ + "CLK_HROW_EE4A3_2", + "INT_INTERFACE_EE4A3" + ], + [ + "CLK_HROW_WW2A3_2", + "INT_INTERFACE_WW2A3" + ], + [ + "CLK_HROW_WL1END2_2", + "INT_INTERFACE_WL1END2" + ], + [ + "CLK_HROW_FAN3_2", + "INT_INTERFACE_FAN3" + ], + [ + "CLK_HROW_IMUX2_2", + "INT_INTERFACE_IMUX2" + ], + [ + "CLK_HROW_LH2_2", + "INT_INTERFACE_LH2" + ], + [ + "CLK_HROW_SW4A2_2", + "INT_INTERFACE_SW4A2" + ], + [ + "CLK_HROW_EE2BEG3_2", + "INT_INTERFACE_EE2BEG3" + ], + [ + "CLK_HROW_LH5_2", + "INT_INTERFACE_LH5" + ], + [ + "CLK_HROW_ER1BEG1_2", + "INT_INTERFACE_ER1BEG1" + ], + [ + "CLK_HROW_NE2A2_2", + "INT_INTERFACE_NE2A2" + ], + [ + "CLK_HROW_FAN1_2", + "INT_INTERFACE_FAN1" + ], + [ + "CLK_HROW_NE2A0_2", + "INT_INTERFACE_NE2A0" + ], + [ + "CLK_HROW_IMUX41_2", + "INT_INTERFACE_IMUX41" + ], + [ + "CLK_HROW_BYP0_2", + "INT_INTERFACE_BYP0" + ], + [ + "CLK_HROW_IMUX35_2", + "INT_INTERFACE_IMUX35" + ], + [ + "CLK_HROW_WW4B0_2", + "INT_INTERFACE_WW4B0" + ], + [ + "CLK_HROW_IMUX13_2", + "INT_INTERFACE_IMUX13" + ], + [ + "CLK_HROW_WW4END2_2", + "INT_INTERFACE_WW4END2" + ], + [ + "CLK_HROW_IMUX17_2", + "INT_INTERFACE_IMUX17" + ], + [ + "CLK_HROW_IMUX26_2", + "INT_INTERFACE_IMUX26" + ], + [ + "CLK_HROW_EE4BEG0_2", + "INT_INTERFACE_EE4BEG0" + ], + [ + "CLK_HROW_SE4BEG2_2", + "INT_INTERFACE_SE4BEG2" + ], + [ + "CLK_HROW_SW2A2_2", + "INT_INTERFACE_SW2A2" + ], + [ + "CLK_HROW_WW2A2_2", + "INT_INTERFACE_WW2A2" + ], + [ + "CLK_HROW_WR1END0_2", + "INT_INTERFACE_WR1END0" + ], + [ + "CLK_HROW_SE4BEG0_2", + "INT_INTERFACE_SE4BEG0" + ], + [ + "CLK_HROW_EE2A2_2", + "INT_INTERFACE_EE2A2" + ], + [ + "CLK_HROW_EE4BEG3_2", + "INT_INTERFACE_EE4BEG3" + ], + [ + "CLK_HROW_IMUX42_2", + "INT_INTERFACE_IMUX42" + ], + [ + "CLK_HROW_IMUX0_2", + "INT_INTERFACE_IMUX0" + ], + [ + "CLK_HROW_IMUX5_2", + "INT_INTERFACE_IMUX5" + ], + [ + "CLK_HROW_SW2A3_2", + "INT_INTERFACE_SW2A3" + ], + [ + "CLK_HROW_IMUX19_2", + "INT_INTERFACE_IMUX19" + ], + [ + "CLK_HROW_BYP4_2", + "INT_INTERFACE_BYP4" + ], + [ + "CLK_HROW_WW4A2_2", + "INT_INTERFACE_WW4A2" + ], + [ + "CLK_HROW_EL1BEG2_2", + "INT_INTERFACE_EL1BEG2" + ], + [ + "CLK_HROW_NW2A2_2", + "INT_INTERFACE_NW2A2" + ], + [ + "CLK_HROW_WW4END0_2", + "INT_INTERFACE_WW4END0" + ], + [ + "CLK_HROW_CLK0_2", + "INT_INTERFACE_CLK0" + ], + [ + "CLK_HROW_MONITOR_N_2", + "INT_INTERFACE_MONITOR_N" + ], + [ + "CLK_HROW_SE2A1_2", + "INT_INTERFACE_SE2A1" + ], + [ + "CLK_HROW_ER1BEG3_2", + "INT_INTERFACE_ER1BEG3" + ], + [ + "CLK_HROW_EE4C3_2", + "INT_INTERFACE_EE4C3" + ], + [ + "CLK_HROW_IMUX39_2", + "INT_INTERFACE_IMUX39" + ], + [ + "CLK_HROW_IMUX6_2", + "INT_INTERFACE_IMUX6" + ], + [ + "CLK_HROW_BYP1_2", + "INT_INTERFACE_BYP1" + ], + [ + "CLK_HROW_ER1BEG0_2", + "INT_INTERFACE_ER1BEG0" + ], + [ + "CLK_HROW_IMUX30_2", + "INT_INTERFACE_IMUX30" + ], + [ + "CLK_HROW_WR1END3_2", + "INT_INTERFACE_WR1END3" + ], + [ + "CLK_HROW_WW2END0_2", + "INT_INTERFACE_WW2END0" + ], + [ + "CLK_HROW_ER1BEG2_2", + "INT_INTERFACE_ER1BEG2" + ], + [ + "CLK_HROW_IMUX15_2", + "INT_INTERFACE_IMUX15" + ], + [ + "CLK_HROW_NW4END0_2", + "INT_INTERFACE_NW4END0" + ], + [ + "CLK_HROW_LH12_2", + "INT_INTERFACE_LH12" + ], + [ + "CLK_HROW_NW4A3_2", + "INT_INTERFACE_NW4A3" + ], + [ + "CLK_HROW_NE4BEG2_2", + "INT_INTERFACE_NE4BEG2" + ], + [ + "CLK_HROW_EL1BEG1_2", + "INT_INTERFACE_EL1BEG1" + ], + [ + "CLK_HROW_EE2A3_2", + "INT_INTERFACE_EE2A3" + ], + [ + "CLK_HROW_NE2A3_2", + "INT_INTERFACE_NE2A3" + ], + [ + "CLK_HROW_WW2A0_2", + "INT_INTERFACE_WW2A0" + ], + [ + "CLK_HROW_EE4C2_2", + "INT_INTERFACE_EE4C2" + ], + [ + "CLK_HROW_EE4B0_2", + "INT_INTERFACE_EE4B0" + ], + [ + "CLK_HROW_IMUX40_2", + "INT_INTERFACE_IMUX40" + ], + [ + "CLK_HROW_SW4END3_2", + "INT_INTERFACE_SW4END3" + ], + [ + "CLK_HROW_SW2A1_2", + "INT_INTERFACE_SW2A1" + ], + [ + "CLK_HROW_WW4C3_2", + "INT_INTERFACE_WW4C3" + ], + [ + "CLK_HROW_NE4C0_2", + "INT_INTERFACE_NE4C0" + ], + [ + "CLK_HROW_SE4BEG3_2", + "INT_INTERFACE_SE4BEG3" + ], + [ + "CLK_HROW_IMUX34_2", + "INT_INTERFACE_IMUX34" + ], + [ + "CLK_HROW_EL1BEG0_2", + "INT_INTERFACE_EL1BEG0" + ], + [ + "CLK_HROW_IMUX29_2", + "INT_INTERFACE_IMUX29" + ], + [ + "CLK_HROW_IMUX22_2", + "INT_INTERFACE_IMUX22" + ], + [ + "CLK_HROW_FAN0_2", + "INT_INTERFACE_FAN0" + ], + [ + "CLK_HROW_IMUX9_2", + "INT_INTERFACE_IMUX9" + ], + [ + "CLK_HROW_SW4A3_2", + "INT_INTERFACE_SW4A3" + ], + [ + "CLK_HROW_WW4B2_2", + "INT_INTERFACE_WW4B2" + ], + [ + "CLK_HROW_WW4C1_2", + "INT_INTERFACE_WW4C1" + ], + [ + "CLK_HROW_NW4A1_2", + "INT_INTERFACE_NW4A1" + ], + [ + "CLK_HROW_EE4C1_2", + "INT_INTERFACE_EE4C1" + ], + [ + "CLK_HROW_LH9_2", + "INT_INTERFACE_LH9" + ], + [ + "CLK_HROW_IMUX23_2", + "INT_INTERFACE_IMUX23" + ], + [ + "CLK_HROW_NE4BEG1_2", + "INT_INTERFACE_NE4BEG1" + ], + [ + "CLK_HROW_IMUX33_2", + "INT_INTERFACE_IMUX33" + ], + [ + "CLK_HROW_NW2A1_2", + "INT_INTERFACE_NW2A1" + ], + [ + "CLK_HROW_EE4C0_2", + "INT_INTERFACE_EE4C0" + ], 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"INT_INTERFACE_IMUX10" + ], + [ + "CLK_HROW_SW4END0_2", + "INT_INTERFACE_SW4END0" + ], + [ + "CLK_HROW_SW4A1_2", + "INT_INTERFACE_SW4A1" + ], + [ + "CLK_HROW_NE2A1_2", + "INT_INTERFACE_NE2A1" + ], + [ + "CLK_HROW_LH11_2", + "INT_INTERFACE_LH11" + ], + [ + "CLK_HROW_IMUX21_2", + "INT_INTERFACE_IMUX21" + ], + [ + "CLK_HROW_IMUX43_2", + "INT_INTERFACE_IMUX43" + ], + [ + "CLK_HROW_IMUX12_2", + "INT_INTERFACE_IMUX12" + ], + [ + "CLK_HROW_SE4C2_2", + "INT_INTERFACE_SE4C2" + ], + [ + "CLK_HROW_NE4C2_2", + "INT_INTERFACE_NE4C2" + ], + [ + "CLK_HROW_LH3_2", + "INT_INTERFACE_LH3" + ], + [ + "CLK_HROW_NW4END3_2", + "INT_INTERFACE_NW4END3" + ], + [ + "CLK_HROW_CLK1_2", + "INT_INTERFACE_CLK1" + ], + [ + "CLK_HROW_WL1END0_2", + "INT_INTERFACE_WL1END0" + ], + [ + "CLK_HROW_IMUX24_2", + "INT_INTERFACE_IMUX24" + ], + [ + "CLK_HROW_SW4A0_2", + "INT_INTERFACE_SW4A0" + ], + [ + "CLK_HROW_WW2END3_2", + "INT_INTERFACE_WW2END3" + ], + [ + "CLK_HROW_IMUX45_2", + "INT_INTERFACE_IMUX45" + ], + [ + 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"HCLK_INT_INTERFACE_CK_IN7", + "HCLK_VFRAME_CK_IN7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK11", + "HCLK_VFRAME_CK_BUFHCLK11" + ], + [ + "HCLK_INT_INTERFACE_CK_IN5", + "HCLK_VFRAME_CK_IN5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK5", + "HCLK_VFRAME_CK_BUFHCLK5" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK8", + "HCLK_VFRAME_CK_BUFHCLK8" + ], + [ + "HCLK_INT_INTERFACE_CK_IN2", + "HCLK_VFRAME_CK_IN2" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK4", + "HCLK_VFRAME_CK_BUFHCLK4" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK2", + "HCLK_VFRAME_CK_BUFRCLK2" + ], + [ + "HCLK_INT_INTERFACE_CK_IN0", + "HCLK_VFRAME_CK_IN0" + ], + [ + "HCLK_INT_INTERFACE_CK_IN13", + "HCLK_VFRAME_CK_IN13" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK3", + "HCLK_VFRAME_CK_BUFHCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_IN11", + "HCLK_VFRAME_CK_IN11" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK7", + "HCLK_VFRAME_CK_BUFHCLK7" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK3", + "HCLK_VFRAME_CK_BUFRCLK3" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK9", + "HCLK_VFRAME_CK_BUFHCLK9" + ], + [ + "HCLK_INT_INTERFACE_CK_IN9", + "HCLK_VFRAME_CK_IN9" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK1", + "HCLK_VFRAME_CK_BUFHCLK1" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFRCLK0", + "HCLK_VFRAME_CK_BUFRCLK0" + ], + [ + "HCLK_INT_INTERFACE_CK_BUFHCLK10", + "HCLK_VFRAME_CK_BUFHCLK10" + ], + [ + "HCLK_INT_INTERFACE_CK_IN10", + "HCLK_VFRAME_CK_IN10" + ] + ] + }, + { + "tile_types": [ + "CLK_HROW_TOP_R", + "VBRK" + ], + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_EE4BEG0_4", + "VBRK_EE4BEG0" + ], + [ + "CLK_HROW_EL1BEG2_4", + "VBRK_EL1BEG2" + ], + [ + "CLK_HROW_SW4A0_4", + "VBRK_SW4A0" + ], + [ + "CLK_HROW_LH2_4", + "VBRK_LH2" + ], + [ + "CLK_HROW_NE4BEG0_4", + "VBRK_NE4BEG0" + ], + [ + "CLK_HROW_SW4END0_4", + "VBRK_SW4END0" + ], + [ + "CLK_HROW_LH1_4", + "VBRK_LH1" + ], + [ + "CLK_HROW_SW2A3_4", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_SW2A2_4", + "VBRK_SW2A2" + ], + [ + "CLK_HROW_EL1BEG1_4", + "VBRK_EL1BEG1" + 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"CMT_TOP_NW4A3_11", + "VBRK_NW4A3" + ], + [ + "CMT_TOP_LH5_11", + "VBRK_LH5" + ], + [ + "CMT_TOP_WW4C3_11", + "VBRK_WW4C3" + ], + [ + "CMT_TOP_NE4BEG1_11", + "VBRK_NE4BEG1" + ], + [ + "CMT_TOP_WW4C0_11", + "VBRK_WW4C0" + ], + [ + "CMT_TOP_EE4B2_11", + "VBRK_EE4B2" + ], + [ + "CMT_TOP_SE2A3_11", + "VBRK_SE2A3" + ], + [ + "CMT_TOP_WW4END3_11", + "VBRK_WW4END3" + ], + [ + "CMT_TOP_LH4_11", + "VBRK_LH4" + ], + [ + "CMT_TOP_WW4B0_11", + "VBRK_WW4B0" + ], + [ + "CMT_TOP_EE4A3_11", + "VBRK_EE4A3" + ] + ] + }, + { + "tile_types": [ + "BRAM_R", + "HCLK_BRAM" + ], + "grid_deltas": [ + 0, + -5 + ], + "wire_pairs": [ + [ + "BRAM_CASCINTOP_ADDRARDADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU7", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU9", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU1", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU8", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU6", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU4", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU9", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU6", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" + ], + [ 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], + [ + "BRAM_CASCOUT_ADDRARDADDRU3", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU10", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU0", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU14", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU2", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU12", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU13", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU12", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" + ], + [ + "BRAM_CASCINTOP_ADDRBWRADDRU2", + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU4", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU14", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU5", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" + ], + [ + "BRAM_CASCOUT_ADDRARDADDRU7", + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU10", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU13", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" + ], + [ + "BRAM_CASCOUT_ADDRBWRADDRU11", + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" + ], + [ + "BRAM_CASCINTOP_ADDRARDADDRU5", + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" + ] + ] + }, + { + "tile_types": [ + "HCLK_CMT", + "HCLK_VBRK" + ], + "grid_deltas": [ + 1, + 0 + ], + "wire_pairs": [ + [ + "HCLK_CMT_CK_BUFHCLK10", + "HCLK_VBRK_CK_BUFHCLK10" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK2", + "HCLK_VBRK_PHSR_PERFCLK2" + ], + [ + "HCLK_CMT_MUX_CLK_11", + "HCLK_VBRK_MUX_CLK11" + ], + [ + "HCLK_CMT_CK_BUFRCLK0", + "HCLK_VBRK_CK_BUFRCLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK0", + "HCLK_VBRK_PHSR_PERFCLK0" + ], + [ + "HCLK_CMT_CK_BUFHCLK8", + "HCLK_VBRK_CK_BUFHCLK8" + ], + [ + "HCLK_CMT_MUX_CLK_10", + "HCLK_VBRK_MUX_CLK10" + ], + [ + "HCLK_CMT_CK_BUFRCLK2", + "HCLK_VBRK_CK_BUFRCLK2" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK3", + "HCLK_VBRK_PHSR_PERFCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK9", + "HCLK_VBRK_CK_BUFHCLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK11", + "HCLK_VBRK_CK_BUFHCLK11" + ], + [ + "HCLK_CMT_CK_BUFHCLK0", + "HCLK_VBRK_CK_BUFHCLK0" + ], + [ + "HCLK_CMT_MUX_CLK_8", + "HCLK_VBRK_MUX_CLK8" + ], + [ + "HCLK_CMT_MUX_CLK_2", + "HCLK_VBRK_MUX_CLK2" + ], + [ + "HCLK_CMT_CK_BUFRCLK3", + "HCLK_VBRK_CK_BUFRCLK3" + ], + [ + "HCLK_CMT_MUX_CLK_3", + "HCLK_VBRK_MUX_CLK3" + ], + [ + "HCLK_CMT_MUX_CLK_13", + "HCLK_VBRK_MUX_CLK13" + ], + [ + "HCLK_CMT_MUX_CLK_4", + "HCLK_VBRK_MUX_CLK4" + ], + [ + "HCLK_CMT_CK_BUFHCLK5", + "HCLK_VBRK_CK_BUFHCLK5" + ], + [ + "HCLK_CMT_CK_BUFHCLK1", + "HCLK_VBRK_CK_BUFHCLK1" + ], + [ + "HCLK_CMT_CK_BUFRCLK1", + "HCLK_VBRK_CK_BUFRCLK1" + ], + [ + "HCLK_CMT_MUX_CLK_9", + "HCLK_VBRK_MUX_CLK9" + ], + [ + "HCLK_CMT_CK_BUFHCLK4", + "HCLK_VBRK_CK_BUFHCLK4" + ], + [ + "HCLK_CMT_MUX_CLK_6", + "HCLK_VBRK_MUX_CLK6" + ], + [ + "HCLK_CMT_MUX_CLK_5", + "HCLK_VBRK_MUX_CLK5" + ], + [ + "HCLK_CMT_MUX_CLK_7", + "HCLK_VBRK_MUX_CLK7" + ], + [ + "HCLK_CMT_MUX_CLK_1", + "HCLK_VBRK_MUX_CLK1" + ], + [ + "HCLK_CMT_MUX_CLK_12", + "HCLK_VBRK_MUX_CLK12" + ], + [ + "HCLK_CMT_MUX_CLK_0", + "HCLK_VBRK_MUX_CLK0" + ], + [ + "HCLK_CMT_MUX_PHSR_PERFCLK1", + "HCLK_VBRK_PHSR_PERFCLK1" + ], + [ + "HCLK_CMT_CK_BUFHCLK6", + "HCLK_VBRK_CK_BUFHCLK6" + ], + [ + "HCLK_CMT_CK_BUFHCLK7", + "HCLK_VBRK_CK_BUFHCLK7" + ], + [ + "HCLK_CMT_CK_BUFHCLK3", + "HCLK_VBRK_CK_BUFHCLK3" + ], + [ + "HCLK_CMT_CK_BUFHCLK2", + "HCLK_VBRK_CK_BUFHCLK2" + ] + ] + }, + { + "tile_types": [ + "GTP_CHANNEL_1", + "VBRK_EXT" + ], + "grid_deltas": [ + -1, + 4 + ], + "wire_pairs": [ + [ + "GTPE2_IMUX5_1", + "VBRK_EXT_IMUX5" + ], + [ + "GTPE2_BYP0_1", + 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"GTPE2_LOGIC_OUTS_B15_1", + "VBRK_EXT_LOGIC_OUTS_B15" + ], + [ + "GTPE2_IMUX43_1", + "VBRK_EXT_IMUX43" + ], + [ + "GTPE2_CTRL0_1", + "VBRK_EXT_CTRL0" + ], + [ + "GTPE2_BYP2_1", + "VBRK_EXT_BYP2" + ], + [ + "GTPE2_LOGIC_OUTS_B5_1", + "VBRK_EXT_LOGIC_OUTS_B5" + ], + [ + "GTPE2_IMUX37_1", + "VBRK_EXT_IMUX37" + ], + [ + "GTPE2_FAN5_1", + "VBRK_EXT_FAN5" + ], + [ + "GTPE2_FAN3_1", + "VBRK_EXT_FAN3" + ], + [ + "GTPE2_IMUX46_1", + "VBRK_EXT_IMUX46" + ], + [ + "GTPE2_LOGIC_OUTS_B23_1", + "VBRK_EXT_LOGIC_OUTS_B23" + ], + [ + "GTPE2_IMUX2_1", + "VBRK_EXT_IMUX2" + ], + [ + "GTPE2_IMUX15_1", + "VBRK_EXT_IMUX15" + ], + [ + "GTPE2_IMUX31_1", + "VBRK_EXT_IMUX31" + ], + [ + "GTPE2_LOGIC_OUTS_B17_1", + "VBRK_EXT_LOGIC_OUTS_B17" + ], + [ + "GTPE2_IMUX9_1", + "VBRK_EXT_IMUX9" + ], + [ + "GTPE2_IMUX4_1", + "VBRK_EXT_IMUX4" + ], + [ + "GTPE2_IMUX1_1", + "VBRK_EXT_IMUX1" + ], + [ + "GTPE2_IMUX44_1", + "VBRK_EXT_IMUX44" + ], + [ + "GTPE2_CLK1_1", + "VBRK_EXT_CLK1" + ], + [ + "GTPE2_LOGIC_OUTS_B20_1", + "VBRK_EXT_LOGIC_OUTS_B20" + ], + [ + "GTPE2_IMUX40_1", + "VBRK_EXT_IMUX40" + ], + [ + "GTPE2_IMUX30_1", + "VBRK_EXT_IMUX30" + ], + [ + "GTPE2_CTRL1_1", + "VBRK_EXT_CTRL1" + ], + [ + "GTPE2_BYP1_1", + "VBRK_EXT_BYP1" + ], + [ + "GTPE2_IMUX42_1", + "VBRK_EXT_IMUX42" + ], + [ + "GTPE2_LOGIC_OUTS_B18_1", + "VBRK_EXT_LOGIC_OUTS_B18" + ], + [ + "GTPE2_BYP6_1", + "VBRK_EXT_BYP6" + ], + [ + "GTPE2_IMUX38_1", + "VBRK_EXT_IMUX38" + ], + [ + "GTPE2_IMUX33_1", + "VBRK_EXT_IMUX33" + ], + [ + "GTPE2_IMUX29_1", + "VBRK_EXT_IMUX29" + ], + [ + "GTPE2_IMUX36_1", + "VBRK_EXT_IMUX36" + ], + [ + "GTPE2_BYP7_1", + "VBRK_EXT_BYP7" + ], + [ + "GTPE2_IMUX41_1", + "VBRK_EXT_IMUX41" + ], + [ + "GTPE2_CLK0_1", + "VBRK_EXT_CLK0" + ], + [ + "GTPE2_IMUX45_1", + "VBRK_EXT_IMUX45" + ], + [ + "GTPE2_IMUX21_1", + "VBRK_EXT_IMUX21" + ], + [ + "GTPE2_IMUX39_1", + "VBRK_EXT_IMUX39" + ], + [ + "GTPE2_FAN4_1", + "VBRK_EXT_FAN4" + ], + [ + "GTPE2_LOGIC_OUTS_B14_1", + "VBRK_EXT_LOGIC_OUTS_B14" + ], + [ + "GTPE2_FAN0_1", + "VBRK_EXT_FAN0" + ], + [ + "GTPE2_IMUX35_1", + "VBRK_EXT_IMUX35" + ], + [ + "GTPE2_BYP3_1", + "VBRK_EXT_BYP3" + ], + [ + "GTPE2_IMUX27_1", + "VBRK_EXT_IMUX27" + ], + [ + "GTPE2_IMUX47_1", + "VBRK_EXT_IMUX47" + ], + [ + "GTPE2_IMUX28_1", + "VBRK_EXT_IMUX28" + ], + [ + "GTPE2_BYP4_1", + "VBRK_EXT_BYP4" + ], + [ + "GTPE2_IMUX26_1", + "VBRK_EXT_IMUX26" + ], + [ + "GTPE2_IMUX13_1", + "VBRK_EXT_IMUX13" + ], + [ + "GTPE2_LOGIC_OUTS_B13_1", + "VBRK_EXT_LOGIC_OUTS_B13" + ], + [ + "GTPE2_IMUX22_1", + "VBRK_EXT_IMUX22" + ], + [ + "GTPE2_IMUX7_1", + "VBRK_EXT_IMUX7" + ], + [ + "GTPE2_IMUX6_1", + "VBRK_EXT_IMUX6" + ], + [ + "GTPE2_IMUX3_1", + "VBRK_EXT_IMUX3" + ], + [ + "GTPE2_LOGIC_OUTS_B22_1", + "VBRK_EXT_LOGIC_OUTS_B22" + ], + [ + "GTPE2_FAN7_1", + "VBRK_EXT_FAN7" + ], + [ + "GTPE2_IMUX34_1", + "VBRK_EXT_IMUX34" + ], + [ + "GTPE2_LOGIC_OUTS_B8_1", + "VBRK_EXT_LOGIC_OUTS_B8" + ], + [ + "GTPE2_IMUX18_1", + "VBRK_EXT_IMUX18" + ], + [ + "GTPE2_IMUX20_1", + "VBRK_EXT_IMUX20" + ], + [ + "GTPE2_FAN2_1", + "VBRK_EXT_FAN2" + ], + [ + "GTPE2_BYP5_1", + "VBRK_EXT_BYP5" + ], + [ + "GTPE2_FAN6_1", + "VBRK_EXT_FAN6" + ], + [ + "GTPE2_IMUX16_1", + "VBRK_EXT_IMUX16" + ] + ] + }, + { + "tile_types": [ + "CLK_BUFG_TOP_R", + "VBRK" + ], + "grid_deltas": [ + 1, + -1 + ], + "wire_pairs": [ + [ + "CLK_HROW_SE4C1_1", + "VBRK_SE4C1" + ], + [ + "CLK_HROW_WW4C2_1", + "VBRK_WW4C2" + ], + [ + "CLK_HROW_EE4A1_1", + "VBRK_EE4A1" + ], + [ + "CLK_HROW_WL1END1_1", + "VBRK_WL1END1" + ], + [ + "CLK_HROW_WW4A3_1", + "VBRK_WW4A3" + ], + [ + "CLK_HROW_NW4END2_1", + "VBRK_NW4END2" + ], + [ + "CLK_HROW_EE4C2_1", + "VBRK_EE4C2" + ], + [ + "CLK_HROW_EE4B3_1", + "VBRK_EE4B3" + ], + [ + "CLK_HROW_WR1END3_1", + "VBRK_WR1END3" + ], + [ + "CLK_HROW_EE2BEG2_1", + "VBRK_EE2BEG2" + ], + [ + "CLK_HROW_SE4C2_1", + "VBRK_SE4C2" + ], + [ + "CLK_HROW_SW2A3_1", + "VBRK_SW2A3" + ], + [ + "CLK_HROW_SE4C3_1", + "VBRK_SE4C3" + ], + [ + "CLK_HROW_LH9_1", + "VBRK_LH9" + ], + [ + "CLK_HROW_LH4_1", + "VBRK_LH4" + ], + [ + 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"CLBLM_R_X7Y93": { + "bits": {}, + "grid_x": 23, + "grid_y": 59, + "segment": "SEG_CLBLM_R_X7Y93", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y93": "SLICEM", + "SLICE_X9Y93": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y94": { + "bits": {}, + "grid_x": 23, + "grid_y": 58, + "segment": "SEG_CLBLM_R_X7Y94", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y94": "SLICEM", + "SLICE_X9Y94": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y95": { + "bits": {}, + "grid_x": 23, + "grid_y": 57, + "segment": "SEG_CLBLM_R_X7Y95", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y95": "SLICEM", + "SLICE_X9Y95": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y96": { + "bits": {}, + "grid_x": 23, + "grid_y": 56, + "segment": "SEG_CLBLM_R_X7Y96", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y96": "SLICEM", + "SLICE_X9Y96": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y97": { + "bits": {}, + "grid_x": 23, + "grid_y": 55, + "segment": "SEG_CLBLM_R_X7Y97", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y97": "SLICEM", + "SLICE_X9Y97": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y98": { + "bits": {}, + "grid_x": 23, + "grid_y": 54, + "segment": "SEG_CLBLM_R_X7Y98", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y98": "SLICEM", + "SLICE_X9Y98": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLBLM_R_X7Y99": { + "bits": {}, + "grid_x": 23, + "grid_y": 53, + "segment": "SEG_CLBLM_R_X7Y99", + "segment_type": "clblm_r", + "sites": { + "SLICE_X8Y99": "SLICEM", + "SLICE_X9Y99": "SLICEL" + }, + "type": "CLBLM_R" + }, + "CLK_BUFG_BOT_R_X60Y48": { + "bits": {}, + "grid_x": 60, + "grid_y": 108, + "sites": { + "BUFGCTRL_X0Y0": "BUFGCTRL", + "BUFGCTRL_X0Y1": "BUFGCTRL", + "BUFGCTRL_X0Y10": "BUFGCTRL", + "BUFGCTRL_X0Y11": "BUFGCTRL", + "BUFGCTRL_X0Y12": "BUFGCTRL", + "BUFGCTRL_X0Y13": "BUFGCTRL", + "BUFGCTRL_X0Y14": "BUFGCTRL", + "BUFGCTRL_X0Y15": "BUFGCTRL", + "BUFGCTRL_X0Y2": "BUFGCTRL", + "BUFGCTRL_X0Y3": "BUFGCTRL", + "BUFGCTRL_X0Y4": "BUFGCTRL", + "BUFGCTRL_X0Y5": "BUFGCTRL", + "BUFGCTRL_X0Y6": "BUFGCTRL", + "BUFGCTRL_X0Y7": "BUFGCTRL", + "BUFGCTRL_X0Y8": "BUFGCTRL", + "BUFGCTRL_X0Y9": "BUFGCTRL" + }, + "type": "CLK_BUFG_BOT_R" + }, + "CLK_BUFG_REBUF_X60Y117": { + "bits": {}, + "grid_x": 60, + "grid_y": 39, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X60Y13": { + "bits": {}, + "grid_x": 60, + "grid_y": 143, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X60Y142": { + "bits": {}, + "grid_x": 60, + "grid_y": 14, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X60Y38": { + "bits": {}, + "grid_x": 60, + "grid_y": 118, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X60Y65": { + "bits": {}, + "grid_x": 60, + "grid_y": 91, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_REBUF_X60Y90": { + "bits": {}, + "grid_x": 60, + "grid_y": 66, + "sites": {}, + "type": "CLK_BUFG_REBUF" + }, + "CLK_BUFG_TOP_R_X60Y53": { + "bits": {}, + "grid_x": 60, + "grid_y": 103, + "sites": { + "BUFGCTRL_X0Y16": "BUFGCTRL", + "BUFGCTRL_X0Y17": "BUFGCTRL", + "BUFGCTRL_X0Y18": "BUFGCTRL", + "BUFGCTRL_X0Y19": "BUFGCTRL", + "BUFGCTRL_X0Y20": "BUFGCTRL", + "BUFGCTRL_X0Y21": "BUFGCTRL", + "BUFGCTRL_X0Y22": "BUFGCTRL", + "BUFGCTRL_X0Y23": "BUFGCTRL", + "BUFGCTRL_X0Y24": "BUFGCTRL", + "BUFGCTRL_X0Y25": "BUFGCTRL", + "BUFGCTRL_X0Y26": "BUFGCTRL", + "BUFGCTRL_X0Y27": "BUFGCTRL", + "BUFGCTRL_X0Y28": "BUFGCTRL", + "BUFGCTRL_X0Y29": "BUFGCTRL", + "BUFGCTRL_X0Y30": "BUFGCTRL", + "BUFGCTRL_X0Y31": "BUFGCTRL" + }, + "type": "CLK_BUFG_TOP_R" + }, + "CLK_FEED_X60Y1": { + "bits": {}, + "grid_x": 60, + "grid_y": 155, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y10": { + "bits": {}, + "grid_x": 60, + "grid_y": 146, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y100": { + "bits": {}, + "grid_x": 60, + "grid_y": 56, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y101": { + "bits": {}, + "grid_x": 60, + "grid_y": 55, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y102": { + "bits": {}, + "grid_x": 60, + "grid_y": 54, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y103": { + "bits": {}, + "grid_x": 60, + "grid_y": 53, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y105": { + "bits": {}, + "grid_x": 60, + "grid_y": 51, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y106": { + "bits": {}, + "grid_x": 60, + "grid_y": 50, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y107": { + "bits": {}, + "grid_x": 60, + "grid_y": 49, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y108": { + "bits": {}, + "grid_x": 60, + "grid_y": 48, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y109": { + "bits": {}, + "grid_x": 60, + "grid_y": 47, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y11": { + "bits": {}, + "grid_x": 60, + "grid_y": 145, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y110": { + "bits": {}, + "grid_x": 60, + "grid_y": 46, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y111": { + "bits": {}, + "grid_x": 60, + "grid_y": 45, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y112": { + "bits": {}, + "grid_x": 60, + "grid_y": 44, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y113": { + "bits": {}, + "grid_x": 60, + "grid_y": 43, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y114": { + "bits": {}, + "grid_x": 60, + "grid_y": 42, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y115": { + "bits": {}, + "grid_x": 60, + "grid_y": 41, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y116": { + "bits": {}, + "grid_x": 60, + "grid_y": 40, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y119": { + "bits": {}, + "grid_x": 60, + "grid_y": 37, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y12": { + "bits": {}, + "grid_x": 60, + "grid_y": 144, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y120": { + "bits": {}, + "grid_x": 60, + "grid_y": 36, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y121": { + "bits": {}, + "grid_x": 60, + "grid_y": 35, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y122": { + "bits": {}, + "grid_x": 60, + "grid_y": 34, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y123": { + "bits": {}, + "grid_x": 60, + "grid_y": 33, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y124": { + "bits": {}, + "grid_x": 60, + "grid_y": 32, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y125": { + "bits": {}, + "grid_x": 60, + "grid_y": 31, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y135": { + "bits": {}, + "grid_x": 60, + "grid_y": 21, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y136": { + "bits": {}, + "grid_x": 60, + "grid_y": 20, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y137": { + "bits": {}, + "grid_x": 60, + "grid_y": 19, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y138": { + "bits": {}, + "grid_x": 60, + "grid_y": 18, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y139": { + "bits": {}, + "grid_x": 60, + "grid_y": 17, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y140": { + "bits": {}, + "grid_x": 60, + "grid_y": 16, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y141": { + "bits": {}, + "grid_x": 60, + "grid_y": 15, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y144": { + "bits": {}, + "grid_x": 60, + "grid_y": 12, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y145": { + "bits": {}, + "grid_x": 60, + "grid_y": 11, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y146": { + "bits": {}, + "grid_x": 60, + "grid_y": 10, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y147": { + "bits": {}, + "grid_x": 60, + "grid_y": 9, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y148": { + "bits": {}, + "grid_x": 60, + "grid_y": 8, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y149": { + "bits": {}, + "grid_x": 60, + "grid_y": 7, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y15": { + "bits": {}, + "grid_x": 60, + "grid_y": 141, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y150": { + "bits": {}, + "grid_x": 60, + "grid_y": 6, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y151": { + "bits": {}, + "grid_x": 60, + "grid_y": 5, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y152": { + "bits": {}, + "grid_x": 60, + "grid_y": 4, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y153": { + "bits": {}, + "grid_x": 60, + "grid_y": 3, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y154": { + "bits": {}, + "grid_x": 60, + "grid_y": 2, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y155": { + "bits": {}, + "grid_x": 60, + "grid_y": 1, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y16": { + "bits": {}, + "grid_x": 60, + "grid_y": 140, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y17": { + "bits": {}, + "grid_x": 60, + "grid_y": 139, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y19": { + "bits": {}, + "grid_x": 60, + "grid_y": 137, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y20": { + "bits": {}, + "grid_x": 60, + "grid_y": 136, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y21": { + "bits": {}, + "grid_x": 60, + "grid_y": 135, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y31": { + "bits": {}, + "grid_x": 60, + "grid_y": 125, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y32": { + "bits": {}, + "grid_x": 60, + "grid_y": 124, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y33": { + "bits": {}, + "grid_x": 60, + "grid_y": 123, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y35": { + "bits": {}, + "grid_x": 60, + "grid_y": 121, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y36": { + "bits": {}, + "grid_x": 60, + "grid_y": 120, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y37": { + "bits": {}, + "grid_x": 60, + "grid_y": 119, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y40": { + "bits": {}, + "grid_x": 60, + "grid_y": 116, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y41": { + "bits": {}, + "grid_x": 60, + "grid_y": 115, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y42": { + "bits": {}, + "grid_x": 60, + "grid_y": 114, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y44": { + "bits": {}, + "grid_x": 60, + "grid_y": 112, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y45": { + "bits": {}, + "grid_x": 60, + "grid_y": 111, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y46": { + "bits": {}, + "grid_x": 60, + "grid_y": 110, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y57": { + "bits": {}, + "grid_x": 60, + "grid_y": 99, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y58": { + "bits": {}, + "grid_x": 60, + "grid_y": 98, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y59": { + "bits": {}, + "grid_x": 60, + "grid_y": 97, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y60": { + "bits": {}, + "grid_x": 60, + "grid_y": 96, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y61": { + "bits": {}, + "grid_x": 60, + "grid_y": 95, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y62": { + "bits": {}, + "grid_x": 60, + "grid_y": 94, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y63": { + "bits": {}, + "grid_x": 60, + "grid_y": 93, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y64": { + "bits": {}, + "grid_x": 60, + "grid_y": 92, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y67": { + "bits": {}, + "grid_x": 60, + "grid_y": 89, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y68": { + "bits": {}, + "grid_x": 60, + "grid_y": 88, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y69": { + "bits": {}, + "grid_x": 60, + "grid_y": 87, + "sites": {}, + "type": "CLK_FEED" + }, + "CLK_FEED_X60Y70": { + "bits": {}, + "grid_x": 60, + "grid_y": 86, + "sites": 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"segment": "SEG_HCLK_R_X12Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X12Y26": { + "bits": {}, + "grid_x": 12, + "grid_y": 130, + "segment": "SEG_HCLK_R_X12Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X12Y78": { + "bits": {}, + "grid_x": 12, + "grid_y": 78, + "segment": "SEG_HCLK_R_X12Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X16Y130": { + "bits": {}, + "grid_x": 16, + "grid_y": 26, + "segment": "SEG_HCLK_R_X16Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X16Y26": { + "bits": {}, + "grid_x": 16, + "grid_y": 130, + "segment": "SEG_HCLK_R_X16Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X16Y78": { + "bits": {}, + "grid_x": 16, + "grid_y": 78, + "segment": "SEG_HCLK_R_X16Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X22Y130": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00020380", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 22, + "grid_y": 26, + "segment": "SEG_HCLK_R_X22Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X22Y26": { + "bits": {}, + "grid_x": 22, + "grid_y": 130, + "segment": "SEG_HCLK_R_X22Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X22Y78": { + "bits": {}, + "grid_x": 22, + "grid_y": 78, + "segment": "SEG_HCLK_R_X22Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X26Y130": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00020480", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 26, + "grid_y": 26, + "segment": "SEG_HCLK_R_X26Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X26Y26": { + "bits": {}, + "grid_x": 26, + "grid_y": 130, + "segment": "SEG_HCLK_R_X26Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X26Y78": { + "bits": {}, + "grid_x": 26, + "grid_y": 78, + "segment": "SEG_HCLK_R_X26Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X32Y130": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00020580", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 32, + "grid_y": 26, + "segment": "SEG_HCLK_R_X32Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X32Y26": { + "bits": {}, + "grid_x": 32, + "grid_y": 130, + "segment": "SEG_HCLK_R_X32Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X32Y78": { + "bits": {}, + "grid_x": 32, + "grid_y": 78, + "segment": "SEG_HCLK_R_X32Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X37Y130": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00020680", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 37, + "grid_y": 26, + "segment": "SEG_HCLK_R_X37Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X41Y130": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00020780", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 41, + "grid_y": 26, + "segment": "SEG_HCLK_R_X41Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X45Y130": { + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00020880", + "frames": 26, + "height": 1, + "offset": 50, + "words": 1 + } + }, + "grid_x": 45, + "grid_y": 26, + "segment": "SEG_HCLK_R_X45Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X50Y130": { + "bits": {}, + "grid_x": 50, + "grid_y": 26, + "segment": "SEG_HCLK_R_X50Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X50Y26": { + "bits": {}, + "grid_x": 50, + "grid_y": 130, + "segment": "SEG_HCLK_R_X50Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X50Y78": { + "bits": {}, + "grid_x": 50, + "grid_y": 78, + "segment": "SEG_HCLK_R_X50Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X54Y130": { + "bits": {}, + "grid_x": 54, + "grid_y": 26, + "segment": "SEG_HCLK_R_X54Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X54Y26": { + "bits": {}, + "grid_x": 54, + "grid_y": 130, + "segment": "SEG_HCLK_R_X54Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X54Y78": { + "bits": {}, + "grid_x": 54, + "grid_y": 78, + "segment": "SEG_HCLK_R_X54Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X58Y130": { + "bits": {}, + "grid_x": 58, + "grid_y": 26, + "segment": "SEG_HCLK_R_X58Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X58Y26": { + "bits": {}, + "grid_x": 58, + "grid_y": 130, + "segment": "SEG_HCLK_R_X58Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X58Y78": { + "bits": {}, + "grid_x": 58, + "grid_y": 78, + "segment": "SEG_HCLK_R_X58Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X5Y130": { + "bits": {}, + "grid_x": 5, + "grid_y": 26, + "segment": "SEG_HCLK_R_X5Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X5Y26": { + "bits": {}, + "grid_x": 5, + "grid_y": 130, + "segment": "SEG_HCLK_R_X5Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X5Y78": { + "bits": {}, + "grid_x": 5, + "grid_y": 78, + "segment": "SEG_HCLK_R_X5Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X64Y130": { + "bits": {}, + "grid_x": 64, + "grid_y": 26, + "segment": "SEG_HCLK_R_X64Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X64Y26": { + "bits": {}, + "grid_x": 64, + "grid_y": 130, + "segment": "SEG_HCLK_R_X64Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X64Y78": { + "bits": {}, + "grid_x": 64, + "grid_y": 78, + "segment": "SEG_HCLK_R_X64Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X69Y130": { + "bits": {}, + "grid_x": 69, + "grid_y": 26, + "segment": "SEG_HCLK_R_X69Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X69Y26": { + "bits": {}, + "grid_x": 69, + "grid_y": 130, + "segment": "SEG_HCLK_R_X69Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X69Y78": { + "bits": {}, + "grid_x": 69, + "grid_y": 78, + "segment": "SEG_HCLK_R_X69Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X73Y26": { + "bits": {}, + "grid_x": 73, + "grid_y": 130, + "segment": "SEG_HCLK_R_X73Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X73Y78": { + "bits": {}, + "grid_x": 73, + "grid_y": 78, + "segment": "SEG_HCLK_R_X73Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X78Y130": { + "bits": {}, + "grid_x": 78, + "grid_y": 26, + "segment": "SEG_HCLK_R_X78Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X78Y26": { + "bits": {}, + "grid_x": 78, + "grid_y": 130, + "segment": "SEG_HCLK_R_X78Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X78Y78": { + "bits": {}, + "grid_x": 78, + "grid_y": 78, + "segment": "SEG_HCLK_R_X78Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X83Y130": { + "bits": {}, + "grid_x": 83, + "grid_y": 26, + "segment": "SEG_HCLK_R_X83Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X83Y26": { + "bits": {}, + "grid_x": 83, + "grid_y": 130, + "segment": "SEG_HCLK_R_X83Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X83Y78": { + "bits": {}, + "grid_x": 83, + "grid_y": 78, + "segment": "SEG_HCLK_R_X83Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X89Y130": { + "bits": {}, + "grid_x": 89, + "grid_y": 26, + "segment": "SEG_HCLK_R_X89Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X89Y26": { + "bits": {}, + "grid_x": 89, + "grid_y": 130, + "segment": "SEG_HCLK_R_X89Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X89Y78": { + "bits": {}, + "grid_x": 89, + "grid_y": 78, + "segment": "SEG_HCLK_R_X89Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X93Y130": { + "bits": {}, + "grid_x": 93, + "grid_y": 26, + "segment": "SEG_HCLK_R_X93Y130", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X93Y26": { + "bits": {}, + "grid_x": 93, + "grid_y": 130, + "segment": "SEG_HCLK_R_X93Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X93Y78": { + "bits": {}, + "grid_x": 93, + "grid_y": 78, + "segment": "SEG_HCLK_R_X93Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X99Y26": { + "bits": {}, + "grid_x": 99, + "grid_y": 130, + "segment": "SEG_HCLK_R_X99Y26", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_R_X99Y78": { + "bits": {}, + "grid_x": 99, + "grid_y": 78, + "segment": "SEG_HCLK_R_X99Y78", + "segment_type": "hclk_r", + "sites": {}, + "type": "HCLK_R" + }, + "HCLK_TERM_GTX_X96Y130": { + "bits": {}, + "grid_x": 96, + "grid_y": 26, + "sites": {}, + "type": "HCLK_TERM_GTX" + }, + "HCLK_TERM_X112Y26": { + "bits": {}, + "grid_x": 112, + "grid_y": 130, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_TERM_X112Y78": { + "bits": {}, + "grid_x": 112, + "grid_y": 78, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_TERM_X2Y130": { + "bits": {}, + "grid_x": 2, + "grid_y": 26, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_TERM_X2Y26": { + "bits": {}, + "grid_x": 2, + "grid_y": 130, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_TERM_X2Y78": { + "bits": {}, + "grid_x": 2, + "grid_y": 78, + "sites": {}, + "type": "HCLK_TERM" + }, + "HCLK_VBRK_X105Y26": { + "bits": {}, + "grid_x": 105, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X105Y78": { + "bits": {}, + "grid_x": 105, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X18Y130": { + "bits": {}, + "grid_x": 18, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X18Y26": { + "bits": {}, + "grid_x": 18, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X18Y78": { + "bits": {}, + "grid_x": 18, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X29Y130": { + "bits": {}, + "grid_x": 29, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X29Y26": { + "bits": {}, + "grid_x": 29, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X29Y78": { + "bits": {}, + "grid_x": 29, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X34Y130": { + "bits": {}, + "grid_x": 34, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X34Y26": { + "bits": {}, + "grid_x": 34, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X34Y78": { + "bits": {}, + "grid_x": 34, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X61Y130": { + "bits": {}, + "grid_x": 61, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X61Y26": { + "bits": {}, + "grid_x": 61, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X61Y78": { + "bits": {}, + "grid_x": 61, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X66Y130": { + "bits": {}, + "grid_x": 66, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X66Y26": { + "bits": {}, + "grid_x": 66, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X66Y78": { + "bits": {}, + "grid_x": 66, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X80Y130": { + "bits": {}, + "grid_x": 80, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X80Y26": { + "bits": {}, + "grid_x": 80, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X80Y78": { + "bits": {}, + "grid_x": 80, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X85Y130": { + "bits": {}, + "grid_x": 85, + "grid_y": 26, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X85Y26": { + "bits": {}, + "grid_x": 85, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X85Y78": { + "bits": {}, + "grid_x": 85, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X96Y26": { + "bits": {}, + "grid_x": 96, + "grid_y": 130, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X96Y78": { + "bits": {}, + "grid_x": 96, + "grid_y": 78, + "sites": {}, + "type": "HCLK_VBRK" + }, + "HCLK_VBRK_X9Y130": { + "bits": {}, + "grid_x": 9, + "grid_y": 26, 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